From 59d9be43ffcbb443367d9b9cf92ad8041ab506f4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 30 Mar 2021 10:55:43 +0000 Subject: [PATCH] update 4k SRAM ls180.il --- experiments9/build_full_4ksram.sh | 1 + .../non_generated/full_core_4_4ksram_ls180.il | 230281 ++++++--------- 2 files changed, 97596 insertions(+), 132686 deletions(-) diff --git a/experiments9/build_full_4ksram.sh b/experiments9/build_full_4ksram.sh index c63e814..d2c7a81 100755 --- a/experiments9/build_full_4ksram.sh +++ b/experiments9/build_full_4ksram.sh @@ -4,6 +4,7 @@ # doDesign.py before running! # change the settings to the larger chip/corona size echo "remember to check doDesign core size" +echo "also use yosys 049e3abf9" # initialise/update the pinmux submodule git submodule update --init --remote diff --git a/experiments9/non_generated/full_core_4_4ksram_ls180.il b/experiments9/non_generated/full_core_4_4ksram_ls180.il index 56e2e69..f4ef796 100644 --- a/experiments9/non_generated/full_core_4_4ksram_ls180.il +++ b/experiments9/non_generated/full_core_4_4ksram_ls180.il @@ -1,5 +1,5 @@ -# Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) -autoidx 15098 +# Generated by Yosys 0.9+3981 (git sha1 a3528649, clang 9.0.1-12 -fPIC -Os) +autoidx 14620 attribute \src "libresoc.v:5.1-335.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" @@ -29747,60 +29747,60 @@ module \SPR_dec31_dec_sub19 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:20720.1-20992.10" +attribute \src "libresoc.v:20720.1-21040.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" attribute \generator "nMigen" module \_fsm - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $0\fsm_state$next[3:0]$464 attribute \src "libresoc.v:20806.3-20807.35" wire width 4 $0\fsm_state[3:0] attribute \src "libresoc.v:20721.7-20721.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20812.3-20839.6" + attribute \src "libresoc.v:20812.3-20863.6" wire $0\isdr$next[0:0]$460 attribute \src "libresoc.v:20808.3-20809.25" wire $0\isdr[0:0] - attribute \src "libresoc.v:20955.3-20982.6" + attribute \src "libresoc.v:20979.3-21030.6" wire $0\isir$next[0:0]$477 attribute \src "libresoc.v:20810.3-20811.25" wire $0\isir[0:0] - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $10\fsm_state$next[3:0]$474 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $11\fsm_state$next[3:0]$475 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $1\fsm_state$next[3:0]$465 attribute \src "libresoc.v:20761.13-20761.29" wire width 4 $1\fsm_state[3:0] - attribute \src "libresoc.v:20812.3-20839.6" + attribute \src "libresoc.v:20812.3-20863.6" wire $1\isdr$next[0:0]$461 attribute \src "libresoc.v:20766.7-20766.18" wire $1\isdr[0:0] - attribute \src "libresoc.v:20955.3-20982.6" + attribute \src "libresoc.v:20979.3-21030.6" wire $1\isir$next[0:0]$478 attribute \src "libresoc.v:20771.7-20771.18" wire $1\isir[0:0] - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $2\fsm_state$next[3:0]$466 - attribute \src "libresoc.v:20812.3-20839.6" + attribute \src "libresoc.v:20812.3-20863.6" wire $2\isdr$next[0:0]$462 - attribute \src "libresoc.v:20955.3-20982.6" + attribute \src "libresoc.v:20979.3-21030.6" wire $2\isir$next[0:0]$479 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $3\fsm_state$next[3:0]$467 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $4\fsm_state$next[3:0]$468 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $5\fsm_state$next[3:0]$469 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $6\fsm_state$next[3:0]$470 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $7\fsm_state$next[3:0]$471 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $8\fsm_state$next[3:0]$472 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $9\fsm_state$next[3:0]$473 attribute \src "libresoc.v:20790.17-20790.110" wire $eq$libresoc.v:20790$440_Y @@ -30131,7 +30131,7 @@ module \_fsm sync posedge \local_clk update \isir $0\isir[0:0] end - attribute \src "libresoc.v:20812.3-20839.6" + attribute \src "libresoc.v:20812.3-20863.6" process $proc$libresoc.v:20812$459 assign { } { } assign { } { } @@ -30166,6 +30166,24 @@ module \_fsm assign $2\isdr$next[0:0]$462 \isdr end attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\isdr$next[0:0]$461 \isdr + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\isdr$next[0:0]$461 \isdr + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\isdr$next[0:0]$461 \isdr + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\isdr$next[0:0]$461 \isdr + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\isdr$next[0:0]$461 \isdr + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign $1\isdr$next[0:0]$461 \isdr + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\isdr$next[0:0]$461 1'0 @@ -30175,14 +30193,14 @@ module \_fsm sync always update \isdr$next $0\isdr$next[0:0]$460 end - attribute \src "libresoc.v:20840.3-20954.6" - process $proc$libresoc.v:20840$463 + attribute \src "libresoc.v:20864.3-20978.6" + process $proc$libresoc.v:20864$463 assign { } { } assign { } { } assign $0\fsm_state$next[3:0]$464 $1\fsm_state$next[3:0]$465 - attribute \src "libresoc.v:20841.5-20841.29" + attribute \src "libresoc.v:20865.5-20865.29" switch \initial - attribute \src "libresoc.v:20841.9-20841.17" + attribute \src "libresoc.v:20865.9-20865.17" case 1'1 case end @@ -30336,14 +30354,14 @@ module \_fsm sync always update \fsm_state$next $0\fsm_state$next[3:0]$464 end - attribute \src "libresoc.v:20955.3-20982.6" - process $proc$libresoc.v:20955$476 + attribute \src "libresoc.v:20979.3-21030.6" + process $proc$libresoc.v:20979$476 assign { } { } assign { } { } assign $0\isir$next[0:0]$477 $1\isir$next[0:0]$478 - attribute \src "libresoc.v:20956.5-20956.29" + attribute \src "libresoc.v:20980.5-20980.29" switch \initial - attribute \src "libresoc.v:20956.9-20956.17" + attribute \src "libresoc.v:20980.9-20980.17" case 1'1 case end @@ -30358,6 +30376,9 @@ module \_fsm assign { } { } assign $1\isir$next[0:0]$478 1'0 attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\isir$next[0:0]$478 \isir + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\isir$next[0:0]$478 $2\isir$next[0:0]$479 @@ -30371,6 +30392,21 @@ module \_fsm assign $2\isir$next[0:0]$479 \isir end attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\isir$next[0:0]$478 \isir + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\isir$next[0:0]$478 \isir + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\isir$next[0:0]$478 \isir + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\isir$next[0:0]$478 \isir + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign $1\isir$next[0:0]$478 \isir + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\isir$next[0:0]$478 1'0 @@ -30406,29 +30442,29 @@ module \_fsm connect \posjtag_rst \rst connect \posjtag_clk \TAP_bus__tck end -attribute \src "libresoc.v:20996.1-21068.10" +attribute \src "libresoc.v:21044.1-21116.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" attribute \generator "nMigen" module \_idblock - attribute \src "libresoc.v:21041.3-21061.6" + attribute \src "libresoc.v:21089.3-21109.6" wire width 32 $0\TAP_id_sr$next[31:0]$489 - attribute \src "libresoc.v:21039.3-21040.35" + attribute \src "libresoc.v:21087.3-21088.35" wire width 32 $0\TAP_id_sr[31:0] - attribute \src "libresoc.v:20997.7-20997.20" + attribute \src "libresoc.v:21045.7-21045.20" wire $0\initial[0:0] - attribute \src "libresoc.v:21041.3-21061.6" + attribute \src "libresoc.v:21089.3-21109.6" wire width 32 $1\TAP_id_sr$next[31:0]$490 - attribute \src "libresoc.v:21007.14-21007.31" + attribute \src "libresoc.v:21055.14-21055.31" wire width 32 $1\TAP_id_sr[31:0] - attribute \src "libresoc.v:21041.3-21061.6" + attribute \src "libresoc.v:21089.3-21109.6" wire width 32 $2\TAP_id_sr$next[31:0]$491 - attribute \src "libresoc.v:21036.17-21036.110" - wire $and$libresoc.v:21036$484_Y - attribute \src "libresoc.v:21037.17-21037.108" - wire $and$libresoc.v:21037$485_Y - attribute \src "libresoc.v:21038.17-21038.109" - wire $and$libresoc.v:21038$486_Y + attribute \src "libresoc.v:21084.17-21084.110" + wire $and$libresoc.v:21084$484_Y + attribute \src "libresoc.v:21085.17-21085.108" + wire $and$libresoc.v:21085$485_Y + attribute \src "libresoc.v:21086.17-21086.109" + wire $and$libresoc.v:21086$486_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" @@ -30457,7 +30493,7 @@ module \_idblock wire input 2 \capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" wire input 1 \id_bypass - attribute \src "libresoc.v:20997.7-20997.15" + attribute \src "libresoc.v:21045.7-21045.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire input 8 \posjtag_clk @@ -30470,7 +30506,7 @@ module \_idblock attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire input 4 \update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" - cell $and $and$libresoc.v:21036$484 + cell $and $and$libresoc.v:21084$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30478,10 +30514,10 @@ module \_idblock parameter \Y_WIDTH 1 connect \A \select_id connect \B \capture - connect \Y $and$libresoc.v:21036$484_Y + connect \Y $and$libresoc.v:21084$484_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" - cell $and $and$libresoc.v:21037$485 + cell $and $and$libresoc.v:21085$485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30489,10 +30525,10 @@ module \_idblock parameter \Y_WIDTH 1 connect \A \select_id connect \B \shift - connect \Y $and$libresoc.v:21037$485_Y + connect \Y $and$libresoc.v:21085$485_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" - cell $and $and$libresoc.v:21038$486 + cell $and $and$libresoc.v:21086$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30500,39 +30536,39 @@ module \_idblock parameter \Y_WIDTH 1 connect \A \select_id connect \B \update - connect \Y $and$libresoc.v:21038$486_Y + connect \Y $and$libresoc.v:21086$486_Y end - attribute \src "libresoc.v:20997.7-20997.20" - process $proc$libresoc.v:20997$492 + attribute \src "libresoc.v:21045.7-21045.20" + process $proc$libresoc.v:21045$492 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21007.14-21007.31" - process $proc$libresoc.v:21007$493 + attribute \src "libresoc.v:21055.14-21055.31" + process $proc$libresoc.v:21055$493 assign { } { } assign $1\TAP_id_sr[31:0] 0 sync always sync init update \TAP_id_sr $1\TAP_id_sr[31:0] end - attribute \src "libresoc.v:21039.3-21040.35" - process $proc$libresoc.v:21039$487 + attribute \src "libresoc.v:21087.3-21088.35" + process $proc$libresoc.v:21087$487 assign { } { } assign $0\TAP_id_sr[31:0] \TAP_id_sr$next sync posedge \posjtag_clk update \TAP_id_sr $0\TAP_id_sr[31:0] end - attribute \src "libresoc.v:21041.3-21061.6" - process $proc$libresoc.v:21041$488 + attribute \src "libresoc.v:21089.3-21109.6" + process $proc$libresoc.v:21089$488 assign { } { } assign { } { } assign $0\TAP_id_sr$next[31:0]$489 $1\TAP_id_sr$next[31:0]$490 - attribute \src "libresoc.v:21042.5-21042.29" + attribute \src "libresoc.v:21090.5-21090.29" switch \initial - attribute \src "libresoc.v:21042.9-21042.17" + attribute \src "libresoc.v:21090.9-21090.17" case 1'1 case end @@ -30563,9 +30599,9 @@ module \_idblock sync always update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$489 end - connect \$1 $and$libresoc.v:21036$484_Y - connect \$3 $and$libresoc.v:21037$485_Y - connect \$5 $and$libresoc.v:21038$486_Y + connect \$1 $and$libresoc.v:21084$484_Y + connect \$3 $and$libresoc.v:21085$485_Y + connect \$5 $and$libresoc.v:21086$486_Y connect \TAP_id_tdo \TAP_id_sr [0] connect \_bypass \id_bypass connect \_update \$5 @@ -30573,43 +30609,43 @@ module \_idblock connect \_capture \$1 connect \_tdi \TAP_bus__tdi end -attribute \src "libresoc.v:21072.1-21156.10" +attribute \src "libresoc.v:21120.1-21204.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" attribute \generator "nMigen" module \_irblock - attribute \src "libresoc.v:21073.7-21073.20" + attribute \src "libresoc.v:21121.7-21121.20" wire $0\initial[0:0] - attribute \src "libresoc.v:21134.3-21154.6" + attribute \src "libresoc.v:21182.3-21202.6" wire width 4 $0\ir$next[3:0]$506 - attribute \src "libresoc.v:21117.3-21118.21" + attribute \src "libresoc.v:21165.3-21166.21" wire width 4 $0\ir[3:0] - attribute \src "libresoc.v:21121.3-21133.6" + attribute \src "libresoc.v:21169.3-21181.6" wire width 4 $0\shift_ir$next[3:0]$503 - attribute \src "libresoc.v:21119.3-21120.33" + attribute \src "libresoc.v:21167.3-21168.33" wire width 4 $0\shift_ir[3:0] - attribute \src "libresoc.v:21134.3-21154.6" + attribute \src "libresoc.v:21182.3-21202.6" wire width 4 $1\ir$next[3:0]$507 - attribute \src "libresoc.v:21092.13-21092.22" + attribute \src "libresoc.v:21140.13-21140.22" wire width 4 $1\ir[3:0] - attribute \src "libresoc.v:21121.3-21133.6" + attribute \src "libresoc.v:21169.3-21181.6" wire width 4 $1\shift_ir$next[3:0]$504 - attribute \src "libresoc.v:21104.13-21104.28" + attribute \src "libresoc.v:21152.13-21152.28" wire width 4 $1\shift_ir[3:0] - attribute \src "libresoc.v:21134.3-21154.6" + attribute \src "libresoc.v:21182.3-21202.6" wire width 4 $2\ir$next[3:0]$508 - attribute \src "libresoc.v:21111.17-21111.103" - wire $and$libresoc.v:21111$494_Y - attribute \src "libresoc.v:21112.18-21112.105" - wire $and$libresoc.v:21112$495_Y - attribute \src "libresoc.v:21113.17-21113.105" - wire $and$libresoc.v:21113$496_Y - attribute \src "libresoc.v:21114.17-21114.103" - wire $and$libresoc.v:21114$497_Y - attribute \src "libresoc.v:21115.17-21115.104" - wire $and$libresoc.v:21115$498_Y - attribute \src "libresoc.v:21116.17-21116.105" - wire $and$libresoc.v:21116$499_Y + attribute \src "libresoc.v:21159.17-21159.103" + wire $and$libresoc.v:21159$494_Y + attribute \src "libresoc.v:21160.18-21160.105" + wire $and$libresoc.v:21160$495_Y + attribute \src "libresoc.v:21161.17-21161.105" + wire $and$libresoc.v:21161$496_Y + attribute \src "libresoc.v:21162.17-21162.103" + wire $and$libresoc.v:21162$497_Y + attribute \src "libresoc.v:21163.17-21163.104" + wire $and$libresoc.v:21163$498_Y + attribute \src "libresoc.v:21164.17-21164.105" + wire $and$libresoc.v:21164$499_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" @@ -30626,7 +30662,7 @@ module \_irblock wire input 4 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" wire input 1 \capture - attribute \src "libresoc.v:21073.7-21073.15" + attribute \src "libresoc.v:21121.7-21121.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" wire width 4 output 9 \ir @@ -30649,7 +30685,7 @@ module \_irblock attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire input 3 \update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - cell $and $and$libresoc.v:21111$494 + cell $and $and$libresoc.v:21159$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30657,10 +30693,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \shift - connect \Y $and$libresoc.v:21111$494_Y + connect \Y $and$libresoc.v:21159$494_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - cell $and $and$libresoc.v:21112$495 + cell $and $and$libresoc.v:21160$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30668,10 +30704,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \update - connect \Y $and$libresoc.v:21112$495_Y + connect \Y $and$libresoc.v:21160$495_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - cell $and $and$libresoc.v:21113$496 + cell $and $and$libresoc.v:21161$496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30679,10 +30715,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \capture - connect \Y $and$libresoc.v:21113$496_Y + connect \Y $and$libresoc.v:21161$496_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - cell $and $and$libresoc.v:21114$497 + cell $and $and$libresoc.v:21162$497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30690,10 +30726,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \shift - connect \Y $and$libresoc.v:21114$497_Y + connect \Y $and$libresoc.v:21162$497_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - cell $and $and$libresoc.v:21115$498 + cell $and $and$libresoc.v:21163$498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30701,10 +30737,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \update - connect \Y $and$libresoc.v:21115$498_Y + connect \Y $and$libresoc.v:21163$498_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - cell $and $and$libresoc.v:21116$499 + cell $and $and$libresoc.v:21164$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30712,54 +30748,54 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \capture - connect \Y $and$libresoc.v:21116$499_Y + connect \Y $and$libresoc.v:21164$499_Y end - attribute \src "libresoc.v:21073.7-21073.20" - process $proc$libresoc.v:21073$509 + attribute \src "libresoc.v:21121.7-21121.20" + process $proc$libresoc.v:21121$509 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21092.13-21092.22" - process $proc$libresoc.v:21092$510 + attribute \src "libresoc.v:21140.13-21140.22" + process $proc$libresoc.v:21140$510 assign { } { } assign $1\ir[3:0] 4'0001 sync always sync init update \ir $1\ir[3:0] end - attribute \src "libresoc.v:21104.13-21104.28" - process $proc$libresoc.v:21104$511 + attribute \src "libresoc.v:21152.13-21152.28" + process $proc$libresoc.v:21152$511 assign { } { } assign $1\shift_ir[3:0] 4'0000 sync always sync init update \shift_ir $1\shift_ir[3:0] end - attribute \src "libresoc.v:21117.3-21118.21" - process $proc$libresoc.v:21117$500 + attribute \src "libresoc.v:21165.3-21166.21" + process $proc$libresoc.v:21165$500 assign { } { } assign $0\ir[3:0] \ir$next sync posedge \posjtag_clk update \ir $0\ir[3:0] end - attribute \src "libresoc.v:21119.3-21120.33" - process $proc$libresoc.v:21119$501 + attribute \src "libresoc.v:21167.3-21168.33" + process $proc$libresoc.v:21167$501 assign { } { } assign $0\shift_ir[3:0] \shift_ir$next sync posedge \posjtag_clk update \shift_ir $0\shift_ir[3:0] end - attribute \src "libresoc.v:21121.3-21133.6" - process $proc$libresoc.v:21121$502 + attribute \src "libresoc.v:21169.3-21181.6" + process $proc$libresoc.v:21169$502 assign { } { } assign { } { } assign $0\shift_ir$next[3:0]$503 $1\shift_ir$next[3:0]$504 - attribute \src "libresoc.v:21122.5-21122.29" + attribute \src "libresoc.v:21170.5-21170.29" switch \initial - attribute \src "libresoc.v:21122.9-21122.17" + attribute \src "libresoc.v:21170.9-21170.17" case 1'1 case end @@ -30779,15 +30815,15 @@ module \_irblock sync always update \shift_ir$next $0\shift_ir$next[3:0]$503 end - attribute \src "libresoc.v:21134.3-21154.6" - process $proc$libresoc.v:21134$505 + attribute \src "libresoc.v:21182.3-21202.6" + process $proc$libresoc.v:21182$505 assign { } { } assign { } { } assign { } { } assign $0\ir$next[3:0]$506 $2\ir$next[3:0]$508 - attribute \src "libresoc.v:21135.5-21135.29" + attribute \src "libresoc.v:21183.5-21183.29" switch \initial - attribute \src "libresoc.v:21135.9-21135.17" + attribute \src "libresoc.v:21183.9-21183.17" case 1'1 case end @@ -30818,45 +30854,45 @@ module \_irblock sync always update \ir$next $0\ir$next[3:0]$506 end - connect \$9 $and$libresoc.v:21111$494_Y - connect \$11 $and$libresoc.v:21112$495_Y - connect \$1 $and$libresoc.v:21113$496_Y - connect \$3 $and$libresoc.v:21114$497_Y - connect \$5 $and$libresoc.v:21115$498_Y - connect \$7 $and$libresoc.v:21116$499_Y + connect \$9 $and$libresoc.v:21159$494_Y + connect \$11 $and$libresoc.v:21160$495_Y + connect \$1 $and$libresoc.v:21161$496_Y + connect \$3 $and$libresoc.v:21162$497_Y + connect \$5 $and$libresoc.v:21163$498_Y + connect \$7 $and$libresoc.v:21164$499_Y connect \tdo \ir [0] end -attribute \src "libresoc.v:21160.1-21218.10" +attribute \src "libresoc.v:21208.1-21266.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.adr_l" attribute \generator "nMigen" module \adr_l - attribute \src "libresoc.v:21161.7-21161.20" + attribute \src "libresoc.v:21209.7-21209.20" wire $0\initial[0:0] - attribute \src "libresoc.v:21206.3-21214.6" + attribute \src "libresoc.v:21254.3-21262.6" wire $0\q_int$next[0:0]$522 - attribute \src "libresoc.v:21204.3-21205.27" + attribute \src "libresoc.v:21252.3-21253.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:21206.3-21214.6" + attribute \src "libresoc.v:21254.3-21262.6" wire $1\q_int$next[0:0]$523 - attribute \src "libresoc.v:21185.7-21185.19" + attribute \src "libresoc.v:21233.7-21233.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:21196.17-21196.96" - wire $and$libresoc.v:21196$512_Y - attribute \src "libresoc.v:21201.17-21201.96" - wire $and$libresoc.v:21201$517_Y - attribute \src "libresoc.v:21198.18-21198.93" - wire $not$libresoc.v:21198$514_Y - attribute \src "libresoc.v:21200.17-21200.92" - wire $not$libresoc.v:21200$516_Y - attribute \src "libresoc.v:21203.17-21203.92" - wire $not$libresoc.v:21203$519_Y - attribute \src "libresoc.v:21197.18-21197.98" - wire $or$libresoc.v:21197$513_Y - attribute \src "libresoc.v:21199.18-21199.99" - wire $or$libresoc.v:21199$515_Y - attribute \src "libresoc.v:21202.17-21202.97" - wire $or$libresoc.v:21202$518_Y + attribute \src "libresoc.v:21244.17-21244.96" + wire $and$libresoc.v:21244$512_Y + attribute \src "libresoc.v:21249.17-21249.96" + wire $and$libresoc.v:21249$517_Y + attribute \src "libresoc.v:21246.18-21246.93" + wire $not$libresoc.v:21246$514_Y + attribute \src "libresoc.v:21248.17-21248.92" + wire $not$libresoc.v:21248$516_Y + attribute \src "libresoc.v:21251.17-21251.92" + wire $not$libresoc.v:21251$519_Y + attribute \src "libresoc.v:21245.18-21245.98" + wire $or$libresoc.v:21245$513_Y + attribute \src "libresoc.v:21247.18-21247.99" + wire $or$libresoc.v:21247$515_Y + attribute \src "libresoc.v:21250.17-21250.97" + wire $or$libresoc.v:21250$518_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -30873,11 +30909,11 @@ module \adr_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:21161.7-21161.15" + attribute \src "libresoc.v:21209.7-21209.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_adr @@ -30894,7 +30930,7 @@ module \adr_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:21196$512 + cell $and $and$libresoc.v:21244$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30902,10 +30938,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:21196$512_Y + connect \Y $and$libresoc.v:21244$512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:21201$517 + cell $and $and$libresoc.v:21249$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30913,34 +30949,34 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:21201$517_Y + connect \Y $and$libresoc.v:21249$517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:21198$514 + cell $not $not$libresoc.v:21246$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_adr - connect \Y $not$libresoc.v:21198$514_Y + connect \Y $not$libresoc.v:21246$514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:21200$516 + cell $not $not$libresoc.v:21248$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_adr - connect \Y $not$libresoc.v:21200$516_Y + connect \Y $not$libresoc.v:21248$516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:21203$519 + cell $not $not$libresoc.v:21251$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_adr - connect \Y $not$libresoc.v:21203$519_Y + connect \Y $not$libresoc.v:21251$519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:21197$513 + cell $or $or$libresoc.v:21245$513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30948,10 +30984,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_adr - connect \Y $or$libresoc.v:21197$513_Y + connect \Y $or$libresoc.v:21245$513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:21199$515 + cell $or $or$libresoc.v:21247$515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30959,10 +30995,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_adr connect \B \q_int - connect \Y $or$libresoc.v:21199$515_Y + connect \Y $or$libresoc.v:21247$515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:21202$518 + cell $or $or$libresoc.v:21250$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30970,39 +31006,39 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_adr - connect \Y $or$libresoc.v:21202$518_Y + connect \Y $or$libresoc.v:21250$518_Y end - attribute \src "libresoc.v:21161.7-21161.20" - process $proc$libresoc.v:21161$524 + attribute \src "libresoc.v:21209.7-21209.20" + process $proc$libresoc.v:21209$524 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21185.7-21185.19" - process $proc$libresoc.v:21185$525 + attribute \src "libresoc.v:21233.7-21233.19" + process $proc$libresoc.v:21233$525 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:21204.3-21205.27" - process $proc$libresoc.v:21204$520 + attribute \src "libresoc.v:21252.3-21253.27" + process $proc$libresoc.v:21252$520 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:21206.3-21214.6" - process $proc$libresoc.v:21206$521 + attribute \src "libresoc.v:21254.3-21262.6" + process $proc$libresoc.v:21254$521 assign { } { } assign { } { } assign $0\q_int$next[0:0]$522 $1\q_int$next[0:0]$523 - attribute \src "libresoc.v:21207.5-21207.29" + attribute \src "libresoc.v:21255.5-21255.29" switch \initial - attribute \src "libresoc.v:21207.9-21207.17" + attribute \src "libresoc.v:21255.9-21255.17" case 1'1 case end @@ -31018,49 +31054,49 @@ module \adr_l sync always update \q_int$next $0\q_int$next[0:0]$522 end - connect \$9 $and$libresoc.v:21196$512_Y - connect \$11 $or$libresoc.v:21197$513_Y - connect \$13 $not$libresoc.v:21198$514_Y - connect \$15 $or$libresoc.v:21199$515_Y - connect \$1 $not$libresoc.v:21200$516_Y - connect \$3 $and$libresoc.v:21201$517_Y - connect \$5 $or$libresoc.v:21202$518_Y - connect \$7 $not$libresoc.v:21203$519_Y + connect \$9 $and$libresoc.v:21244$512_Y + connect \$11 $or$libresoc.v:21245$513_Y + connect \$13 $not$libresoc.v:21246$514_Y + connect \$15 $or$libresoc.v:21247$515_Y + connect \$1 $not$libresoc.v:21248$516_Y + connect \$3 $and$libresoc.v:21249$517_Y + connect \$5 $or$libresoc.v:21250$518_Y + connect \$7 $not$libresoc.v:21251$519_Y connect \qlq_adr \$15 connect \qn_adr \$13 connect \q_adr \$11 end -attribute \src "libresoc.v:21222.1-21280.10" +attribute \src "libresoc.v:21270.1-21328.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.adrok_l" attribute \generator "nMigen" module \adrok_l - attribute \src "libresoc.v:21223.7-21223.20" + attribute \src "libresoc.v:21271.7-21271.20" wire $0\initial[0:0] - attribute \src "libresoc.v:21268.3-21276.6" + attribute \src "libresoc.v:21316.3-21324.6" wire $0\q_int$next[0:0]$536 - attribute \src "libresoc.v:21266.3-21267.27" + attribute \src "libresoc.v:21314.3-21315.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:21268.3-21276.6" + attribute \src "libresoc.v:21316.3-21324.6" wire $1\q_int$next[0:0]$537 - attribute \src "libresoc.v:21247.7-21247.19" + attribute \src "libresoc.v:21295.7-21295.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:21258.17-21258.96" - wire $and$libresoc.v:21258$526_Y - attribute \src "libresoc.v:21263.17-21263.96" - wire $and$libresoc.v:21263$531_Y - attribute \src "libresoc.v:21260.18-21260.100" - wire $not$libresoc.v:21260$528_Y - attribute \src "libresoc.v:21262.17-21262.99" - wire $not$libresoc.v:21262$530_Y - attribute \src "libresoc.v:21265.17-21265.99" - wire $not$libresoc.v:21265$533_Y - attribute \src "libresoc.v:21259.18-21259.105" - wire $or$libresoc.v:21259$527_Y - attribute \src "libresoc.v:21261.18-21261.106" - wire $or$libresoc.v:21261$529_Y - attribute \src "libresoc.v:21264.17-21264.104" - wire $or$libresoc.v:21264$532_Y + attribute \src "libresoc.v:21306.17-21306.96" + wire $and$libresoc.v:21306$526_Y + attribute \src "libresoc.v:21311.17-21311.96" + wire $and$libresoc.v:21311$531_Y + attribute \src "libresoc.v:21308.18-21308.100" + wire $not$libresoc.v:21308$528_Y + attribute \src "libresoc.v:21310.17-21310.99" + wire $not$libresoc.v:21310$530_Y + attribute \src "libresoc.v:21313.17-21313.99" + wire $not$libresoc.v:21313$533_Y + attribute \src "libresoc.v:21307.18-21307.105" + wire $or$libresoc.v:21307$527_Y + attribute \src "libresoc.v:21309.18-21309.106" + wire $or$libresoc.v:21309$529_Y + attribute \src "libresoc.v:21312.17-21312.104" + wire $or$libresoc.v:21312$532_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -31077,11 +31113,11 @@ module \adrok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 6 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:21223.7-21223.15" + attribute \src "libresoc.v:21271.7-21271.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 5 \q_addr_acked @@ -31098,7 +31134,7 @@ module \adrok_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:21258$526 + cell $and $and$libresoc.v:21306$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -31106,10 +31142,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:21258$526_Y + connect \Y $and$libresoc.v:21306$526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:21263$531 + cell $and $and$libresoc.v:21311$531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -31117,34 +31153,34 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:21263$531_Y + connect \Y $and$libresoc.v:21311$531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:21260$528 + cell $not $not$libresoc.v:21308$528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_addr_acked - connect \Y $not$libresoc.v:21260$528_Y + connect \Y $not$libresoc.v:21308$528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:21262$530 + cell $not $not$libresoc.v:21310$530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_addr_acked - connect \Y $not$libresoc.v:21262$530_Y + connect \Y $not$libresoc.v:21310$530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:21265$533 + cell $not $not$libresoc.v:21313$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_addr_acked - connect \Y $not$libresoc.v:21265$533_Y + connect \Y $not$libresoc.v:21313$533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:21259$527 + cell $or $or$libresoc.v:21307$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -31152,10 +31188,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_addr_acked - connect \Y $or$libresoc.v:21259$527_Y + connect \Y $or$libresoc.v:21307$527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:21261$529 + cell $or $or$libresoc.v:21309$529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -31163,10 +31199,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_addr_acked connect \B \q_int - connect \Y $or$libresoc.v:21261$529_Y + connect \Y $or$libresoc.v:21309$529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:21264$532 + cell $or $or$libresoc.v:21312$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -31174,39 +31210,39 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_addr_acked - connect \Y $or$libresoc.v:21264$532_Y + connect \Y $or$libresoc.v:21312$532_Y end - attribute \src "libresoc.v:21223.7-21223.20" - process $proc$libresoc.v:21223$538 + attribute \src "libresoc.v:21271.7-21271.20" + process $proc$libresoc.v:21271$538 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21247.7-21247.19" - process $proc$libresoc.v:21247$539 + attribute \src "libresoc.v:21295.7-21295.19" + process $proc$libresoc.v:21295$539 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:21266.3-21267.27" - process $proc$libresoc.v:21266$534 + attribute \src "libresoc.v:21314.3-21315.27" + process $proc$libresoc.v:21314$534 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:21268.3-21276.6" - process $proc$libresoc.v:21268$535 + attribute \src "libresoc.v:21316.3-21324.6" + process $proc$libresoc.v:21316$535 assign { } { } assign { } { } assign $0\q_int$next[0:0]$536 $1\q_int$next[0:0]$537 - attribute \src "libresoc.v:21269.5-21269.29" + attribute \src "libresoc.v:21317.5-21317.29" switch \initial - attribute \src "libresoc.v:21269.9-21269.17" + attribute \src "libresoc.v:21317.9-21317.17" case 1'1 case end @@ -31222,593 +31258,593 @@ module \adrok_l sync always update \q_int$next $0\q_int$next[0:0]$536 end - connect \$9 $and$libresoc.v:21258$526_Y - connect \$11 $or$libresoc.v:21259$527_Y - connect \$13 $not$libresoc.v:21260$528_Y - connect \$15 $or$libresoc.v:21261$529_Y - connect \$1 $not$libresoc.v:21262$530_Y - connect \$3 $and$libresoc.v:21263$531_Y - connect \$5 $or$libresoc.v:21264$532_Y - connect \$7 $not$libresoc.v:21265$533_Y + connect \$9 $and$libresoc.v:21306$526_Y + connect \$11 $or$libresoc.v:21307$527_Y + connect \$13 $not$libresoc.v:21308$528_Y + connect \$15 $or$libresoc.v:21309$529_Y + connect \$1 $not$libresoc.v:21310$530_Y + connect \$3 $and$libresoc.v:21311$531_Y + connect \$5 $or$libresoc.v:21312$532_Y + connect \$7 $not$libresoc.v:21313$533_Y connect \qlq_addr_acked \$15 connect \qn_addr_acked \$13 connect \q_addr_acked \$11 end -attribute \src "libresoc.v:21284.1-22615.10" +attribute \src "libresoc.v:21332.1-22663.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0" attribute \generator "nMigen" module \alu0 - attribute \src "libresoc.v:22126.3-22127.25" + attribute \src "libresoc.v:22174.3-22175.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 4 $0\alu_alu0_alu_op__data_len$next[3:0]$686 - attribute \src "libresoc.v:22098.3-22099.67" + attribute \src "libresoc.v:22146.3-22147.67" wire width 4 $0\alu_alu0_alu_op__data_len[3:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 14 $0\alu_alu0_alu_op__fn_unit$next[13:0]$687 - attribute \src "libresoc.v:22068.3-22069.65" + attribute \src "libresoc.v:22116.3-22117.65" wire width 14 $0\alu_alu0_alu_op__fn_unit[13:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 64 $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 - attribute \src "libresoc.v:22070.3-22071.79" + attribute \src "libresoc.v:22118.3-22119.79" wire width 64 $0\alu_alu0_alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 - attribute \src "libresoc.v:22072.3-22073.75" + attribute \src "libresoc.v:22120.3-22121.75" wire $0\alu_alu0_alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 2 $0\alu_alu0_alu_op__input_carry$next[1:0]$690 - attribute \src "libresoc.v:22090.3-22091.73" + attribute \src "libresoc.v:22138.3-22139.73" wire width 2 $0\alu_alu0_alu_op__input_carry[1:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 32 $0\alu_alu0_alu_op__insn$next[31:0]$691 - attribute \src "libresoc.v:22100.3-22101.59" + attribute \src "libresoc.v:22148.3-22149.59" wire width 32 $0\alu_alu0_alu_op__insn[31:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 7 $0\alu_alu0_alu_op__insn_type$next[6:0]$692 - attribute \src "libresoc.v:22066.3-22067.69" + attribute \src "libresoc.v:22114.3-22115.69" wire width 7 $0\alu_alu0_alu_op__insn_type[6:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__invert_in$next[0:0]$693 - attribute \src "libresoc.v:22082.3-22083.69" + attribute \src "libresoc.v:22130.3-22131.69" wire $0\alu_alu0_alu_op__invert_in[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__invert_out$next[0:0]$694 - attribute \src "libresoc.v:22086.3-22087.71" + attribute \src "libresoc.v:22134.3-22135.71" wire $0\alu_alu0_alu_op__invert_out[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 - attribute \src "libresoc.v:22094.3-22095.67" + attribute \src "libresoc.v:22142.3-22143.67" wire $0\alu_alu0_alu_op__is_32bit[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__is_signed$next[0:0]$696 - attribute \src "libresoc.v:22096.3-22097.69" + attribute \src "libresoc.v:22144.3-22145.69" wire $0\alu_alu0_alu_op__is_signed[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 - attribute \src "libresoc.v:22078.3-22079.63" + attribute \src "libresoc.v:22126.3-22127.63" wire $0\alu_alu0_alu_op__oe__oe[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 - attribute \src "libresoc.v:22080.3-22081.63" + attribute \src "libresoc.v:22128.3-22129.63" wire $0\alu_alu0_alu_op__oe__ok[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__output_carry$next[0:0]$699 - attribute \src "libresoc.v:22092.3-22093.75" + attribute \src "libresoc.v:22140.3-22141.75" wire $0\alu_alu0_alu_op__output_carry[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 - attribute \src "libresoc.v:22076.3-22077.63" + attribute \src "libresoc.v:22124.3-22125.63" wire $0\alu_alu0_alu_op__rc__ok[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 - attribute \src "libresoc.v:22074.3-22075.63" + attribute \src "libresoc.v:22122.3-22123.63" wire $0\alu_alu0_alu_op__rc__rc[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 - attribute \src "libresoc.v:22088.3-22089.69" + attribute \src "libresoc.v:22136.3-22137.69" wire $0\alu_alu0_alu_op__write_cr0[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__zero_a$next[0:0]$703 - attribute \src "libresoc.v:22084.3-22085.63" + attribute \src "libresoc.v:22132.3-22133.63" wire $0\alu_alu0_alu_op__zero_a[0:0] - attribute \src "libresoc.v:22124.3-22125.40" + attribute \src "libresoc.v:22172.3-22173.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:22514.3-22522.6" + attribute \src "libresoc.v:22562.3-22570.6" wire $0\alu_l_r_alu$next[0:0]$784 - attribute \src "libresoc.v:22034.3-22035.39" + attribute \src "libresoc.v:22082.3-22083.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:22505.3-22513.6" + attribute \src "libresoc.v:22553.3-22561.6" wire $0\alui_l_r_alui$next[0:0]$781 - attribute \src "libresoc.v:22036.3-22037.43" + attribute \src "libresoc.v:22084.3-22085.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:22355.3-22376.6" + attribute \src "libresoc.v:22403.3-22424.6" wire width 64 $0\data_r0__o$next[63:0]$729 - attribute \src "libresoc.v:22062.3-22063.37" + attribute \src "libresoc.v:22110.3-22111.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:22355.3-22376.6" + attribute \src "libresoc.v:22403.3-22424.6" wire $0\data_r0__o_ok$next[0:0]$730 - attribute \src "libresoc.v:22064.3-22065.43" + attribute \src "libresoc.v:22112.3-22113.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:22377.3-22398.6" + attribute \src "libresoc.v:22425.3-22446.6" wire width 4 $0\data_r1__cr_a$next[3:0]$737 - attribute \src "libresoc.v:22058.3-22059.43" + attribute \src "libresoc.v:22106.3-22107.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:22377.3-22398.6" + attribute \src "libresoc.v:22425.3-22446.6" wire $0\data_r1__cr_a_ok$next[0:0]$738 - attribute \src "libresoc.v:22060.3-22061.49" + attribute \src "libresoc.v:22108.3-22109.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:22399.3-22420.6" + attribute \src "libresoc.v:22447.3-22468.6" wire width 2 $0\data_r2__xer_ca$next[1:0]$745 - attribute \src "libresoc.v:22054.3-22055.47" + attribute \src "libresoc.v:22102.3-22103.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:22399.3-22420.6" + attribute \src "libresoc.v:22447.3-22468.6" wire $0\data_r2__xer_ca_ok$next[0:0]$746 - attribute \src "libresoc.v:22056.3-22057.53" + attribute \src "libresoc.v:22104.3-22105.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:22421.3-22442.6" + attribute \src "libresoc.v:22469.3-22490.6" wire width 2 $0\data_r3__xer_ov$next[1:0]$753 - attribute \src "libresoc.v:22050.3-22051.47" + attribute \src "libresoc.v:22098.3-22099.47" wire width 2 $0\data_r3__xer_ov[1:0] - attribute \src "libresoc.v:22421.3-22442.6" + attribute \src "libresoc.v:22469.3-22490.6" wire $0\data_r3__xer_ov_ok$next[0:0]$754 - attribute \src "libresoc.v:22052.3-22053.53" + attribute \src "libresoc.v:22100.3-22101.53" wire $0\data_r3__xer_ov_ok[0:0] - attribute \src "libresoc.v:22443.3-22464.6" + attribute \src "libresoc.v:22491.3-22512.6" wire $0\data_r4__xer_so$next[0:0]$761 - attribute \src "libresoc.v:22046.3-22047.47" + attribute \src "libresoc.v:22094.3-22095.47" wire $0\data_r4__xer_so[0:0] - attribute \src "libresoc.v:22443.3-22464.6" + attribute \src "libresoc.v:22491.3-22512.6" wire $0\data_r4__xer_so_ok$next[0:0]$762 - attribute \src "libresoc.v:22048.3-22049.53" + attribute \src "libresoc.v:22096.3-22097.53" wire $0\data_r4__xer_so_ok[0:0] - attribute \src "libresoc.v:22523.3-22532.6" + attribute \src "libresoc.v:22571.3-22580.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:22533.3-22542.6" + attribute \src "libresoc.v:22581.3-22590.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:22543.3-22552.6" + attribute \src "libresoc.v:22591.3-22600.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:22553.3-22562.6" + attribute \src "libresoc.v:22601.3-22610.6" wire width 2 $0\dest4_o[1:0] - attribute \src "libresoc.v:22563.3-22572.6" + attribute \src "libresoc.v:22611.3-22620.6" wire $0\dest5_o[0:0] - attribute \src "libresoc.v:21285.7-21285.20" + attribute \src "libresoc.v:21333.7-21333.20" wire $0\initial[0:0] - attribute \src "libresoc.v:22271.3-22279.6" + attribute \src "libresoc.v:22319.3-22327.6" wire $0\opc_l_r_opc$next[0:0]$671 - attribute \src "libresoc.v:22110.3-22111.39" + attribute \src "libresoc.v:22158.3-22159.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:22262.3-22270.6" + attribute \src "libresoc.v:22310.3-22318.6" wire $0\opc_l_s_opc$next[0:0]$668 - attribute \src "libresoc.v:22112.3-22113.39" + attribute \src "libresoc.v:22160.3-22161.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:22573.3-22581.6" + attribute \src "libresoc.v:22621.3-22629.6" wire width 5 $0\prev_wr_go$next[4:0]$792 - attribute \src "libresoc.v:22122.3-22123.37" + attribute \src "libresoc.v:22170.3-22171.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:22216.3-22225.6" + attribute \src "libresoc.v:22264.3-22273.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:22307.3-22315.6" + attribute \src "libresoc.v:22355.3-22363.6" wire width 5 $0\req_l_r_req$next[4:0]$683 - attribute \src "libresoc.v:22102.3-22103.39" + attribute \src "libresoc.v:22150.3-22151.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:22298.3-22306.6" + attribute \src "libresoc.v:22346.3-22354.6" wire width 5 $0\req_l_s_req$next[4:0]$680 - attribute \src "libresoc.v:22104.3-22105.39" + attribute \src "libresoc.v:22152.3-22153.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:22235.3-22243.6" + attribute \src "libresoc.v:22283.3-22291.6" wire $0\rok_l_r_rdok$next[0:0]$659 - attribute \src "libresoc.v:22118.3-22119.41" + attribute \src "libresoc.v:22166.3-22167.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:22226.3-22234.6" + attribute \src "libresoc.v:22274.3-22282.6" wire $0\rok_l_s_rdok$next[0:0]$656 - attribute \src "libresoc.v:22120.3-22121.41" + attribute \src "libresoc.v:22168.3-22169.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:22253.3-22261.6" + attribute \src "libresoc.v:22301.3-22309.6" wire $0\rst_l_r_rst$next[0:0]$665 - attribute \src "libresoc.v:22114.3-22115.39" + attribute \src "libresoc.v:22162.3-22163.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:22244.3-22252.6" + attribute \src "libresoc.v:22292.3-22300.6" wire $0\rst_l_s_rst$next[0:0]$662 - attribute \src "libresoc.v:22116.3-22117.39" + attribute \src "libresoc.v:22164.3-22165.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:22289.3-22297.6" + attribute \src "libresoc.v:22337.3-22345.6" wire width 4 $0\src_l_r_src$next[3:0]$677 - attribute \src "libresoc.v:22106.3-22107.39" + attribute \src "libresoc.v:22154.3-22155.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:22280.3-22288.6" + attribute \src "libresoc.v:22328.3-22336.6" wire width 4 $0\src_l_s_src$next[3:0]$674 - attribute \src "libresoc.v:22108.3-22109.39" + attribute \src "libresoc.v:22156.3-22157.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:22465.3-22474.6" + attribute \src "libresoc.v:22513.3-22522.6" wire width 64 $0\src_r0$next[63:0]$769 - attribute \src "libresoc.v:22044.3-22045.29" + attribute \src "libresoc.v:22092.3-22093.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:22475.3-22484.6" + attribute \src "libresoc.v:22523.3-22532.6" wire width 64 $0\src_r1$next[63:0]$772 - attribute \src "libresoc.v:22042.3-22043.29" + attribute \src "libresoc.v:22090.3-22091.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:22485.3-22494.6" + attribute \src "libresoc.v:22533.3-22542.6" wire $0\src_r2$next[0:0]$775 - attribute \src "libresoc.v:22040.3-22041.29" + attribute \src "libresoc.v:22088.3-22089.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:22495.3-22504.6" + attribute \src "libresoc.v:22543.3-22552.6" wire width 2 $0\src_r3$next[1:0]$778 - attribute \src "libresoc.v:22038.3-22039.29" + attribute \src "libresoc.v:22086.3-22087.29" wire width 2 $0\src_r3[1:0] - attribute \src "libresoc.v:21423.7-21423.24" + attribute \src "libresoc.v:21471.7-21471.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 4 $1\alu_alu0_alu_op__data_len$next[3:0]$704 - attribute \src "libresoc.v:21431.13-21431.45" + attribute \src "libresoc.v:21479.13-21479.45" wire width 4 $1\alu_alu0_alu_op__data_len[3:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 14 $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 - attribute \src "libresoc.v:21450.14-21450.49" + attribute \src "libresoc.v:21498.14-21498.49" wire width 14 $1\alu_alu0_alu_op__fn_unit[13:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 64 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 - attribute \src "libresoc.v:21454.14-21454.68" + attribute \src "libresoc.v:21502.14-21502.68" wire width 64 $1\alu_alu0_alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 - attribute \src "libresoc.v:21458.7-21458.43" + attribute \src "libresoc.v:21506.7-21506.43" wire $1\alu_alu0_alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 2 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 - attribute \src "libresoc.v:21466.13-21466.48" + attribute \src "libresoc.v:21514.13-21514.48" wire width 2 $1\alu_alu0_alu_op__input_carry[1:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 32 $1\alu_alu0_alu_op__insn$next[31:0]$709 - attribute \src "libresoc.v:21470.14-21470.43" + attribute \src "libresoc.v:21518.14-21518.43" wire width 32 $1\alu_alu0_alu_op__insn[31:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 7 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 - attribute \src "libresoc.v:21549.13-21549.47" + attribute \src "libresoc.v:21597.13-21597.47" wire width 7 $1\alu_alu0_alu_op__insn_type[6:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__invert_in$next[0:0]$711 - attribute \src "libresoc.v:21553.7-21553.40" + attribute \src "libresoc.v:21601.7-21601.40" wire $1\alu_alu0_alu_op__invert_in[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__invert_out$next[0:0]$712 - attribute \src "libresoc.v:21557.7-21557.41" + attribute \src "libresoc.v:21605.7-21605.41" wire $1\alu_alu0_alu_op__invert_out[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 - attribute \src "libresoc.v:21561.7-21561.39" + attribute \src "libresoc.v:21609.7-21609.39" wire $1\alu_alu0_alu_op__is_32bit[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__is_signed$next[0:0]$714 - attribute \src "libresoc.v:21565.7-21565.40" + attribute \src "libresoc.v:21613.7-21613.40" wire $1\alu_alu0_alu_op__is_signed[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 - attribute \src "libresoc.v:21569.7-21569.37" + attribute \src "libresoc.v:21617.7-21617.37" wire $1\alu_alu0_alu_op__oe__oe[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 - attribute \src "libresoc.v:21573.7-21573.37" + attribute \src "libresoc.v:21621.7-21621.37" wire $1\alu_alu0_alu_op__oe__ok[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__output_carry$next[0:0]$717 - attribute \src "libresoc.v:21577.7-21577.43" + attribute \src "libresoc.v:21625.7-21625.43" wire $1\alu_alu0_alu_op__output_carry[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 - attribute \src "libresoc.v:21581.7-21581.37" + attribute \src "libresoc.v:21629.7-21629.37" wire $1\alu_alu0_alu_op__rc__ok[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 - attribute \src "libresoc.v:21585.7-21585.37" + attribute \src "libresoc.v:21633.7-21633.37" wire $1\alu_alu0_alu_op__rc__rc[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 - attribute \src "libresoc.v:21589.7-21589.40" + attribute \src "libresoc.v:21637.7-21637.40" wire $1\alu_alu0_alu_op__write_cr0[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__zero_a$next[0:0]$721 - attribute \src "libresoc.v:21593.7-21593.37" + attribute \src "libresoc.v:21641.7-21641.37" wire $1\alu_alu0_alu_op__zero_a[0:0] - attribute \src "libresoc.v:21625.7-21625.26" + attribute \src "libresoc.v:21673.7-21673.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:22514.3-22522.6" + attribute \src "libresoc.v:22562.3-22570.6" wire $1\alu_l_r_alu$next[0:0]$785 - attribute \src "libresoc.v:21633.7-21633.25" + attribute \src "libresoc.v:21681.7-21681.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:22505.3-22513.6" + attribute \src "libresoc.v:22553.3-22561.6" wire $1\alui_l_r_alui$next[0:0]$782 - attribute \src "libresoc.v:21645.7-21645.27" + attribute \src "libresoc.v:21693.7-21693.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:22355.3-22376.6" + attribute \src "libresoc.v:22403.3-22424.6" wire width 64 $1\data_r0__o$next[63:0]$731 - attribute \src "libresoc.v:21679.14-21679.47" + attribute \src "libresoc.v:21727.14-21727.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:22355.3-22376.6" + attribute \src "libresoc.v:22403.3-22424.6" wire $1\data_r0__o_ok$next[0:0]$732 - attribute \src "libresoc.v:21683.7-21683.27" + attribute \src "libresoc.v:21731.7-21731.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:22377.3-22398.6" + attribute \src "libresoc.v:22425.3-22446.6" wire width 4 $1\data_r1__cr_a$next[3:0]$739 - attribute \src "libresoc.v:21687.13-21687.33" + attribute \src "libresoc.v:21735.13-21735.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:22377.3-22398.6" + attribute \src "libresoc.v:22425.3-22446.6" wire $1\data_r1__cr_a_ok$next[0:0]$740 - attribute \src "libresoc.v:21691.7-21691.30" + attribute \src "libresoc.v:21739.7-21739.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:22399.3-22420.6" + attribute \src "libresoc.v:22447.3-22468.6" wire width 2 $1\data_r2__xer_ca$next[1:0]$747 - attribute \src "libresoc.v:21695.13-21695.35" + attribute \src "libresoc.v:21743.13-21743.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:22399.3-22420.6" + attribute \src "libresoc.v:22447.3-22468.6" wire $1\data_r2__xer_ca_ok$next[0:0]$748 - attribute \src "libresoc.v:21699.7-21699.32" + attribute \src "libresoc.v:21747.7-21747.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:22421.3-22442.6" + attribute \src "libresoc.v:22469.3-22490.6" wire width 2 $1\data_r3__xer_ov$next[1:0]$755 - attribute \src "libresoc.v:21703.13-21703.35" + attribute \src "libresoc.v:21751.13-21751.35" wire width 2 $1\data_r3__xer_ov[1:0] - attribute \src "libresoc.v:22421.3-22442.6" + attribute \src "libresoc.v:22469.3-22490.6" wire $1\data_r3__xer_ov_ok$next[0:0]$756 - attribute \src "libresoc.v:21707.7-21707.32" + attribute \src "libresoc.v:21755.7-21755.32" wire $1\data_r3__xer_ov_ok[0:0] - attribute \src "libresoc.v:22443.3-22464.6" + attribute \src "libresoc.v:22491.3-22512.6" wire $1\data_r4__xer_so$next[0:0]$763 - attribute \src "libresoc.v:21711.7-21711.29" + attribute \src "libresoc.v:21759.7-21759.29" wire $1\data_r4__xer_so[0:0] - attribute \src "libresoc.v:22443.3-22464.6" + attribute \src "libresoc.v:22491.3-22512.6" wire $1\data_r4__xer_so_ok$next[0:0]$764 - attribute \src "libresoc.v:21715.7-21715.32" + attribute \src "libresoc.v:21763.7-21763.32" wire $1\data_r4__xer_so_ok[0:0] - attribute \src "libresoc.v:22523.3-22532.6" + attribute \src "libresoc.v:22571.3-22580.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:22533.3-22542.6" + attribute \src "libresoc.v:22581.3-22590.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:22543.3-22552.6" + attribute \src "libresoc.v:22591.3-22600.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:22553.3-22562.6" + attribute \src "libresoc.v:22601.3-22610.6" wire width 2 $1\dest4_o[1:0] - attribute \src "libresoc.v:22563.3-22572.6" + attribute \src "libresoc.v:22611.3-22620.6" wire $1\dest5_o[0:0] - attribute \src "libresoc.v:22271.3-22279.6" + attribute \src "libresoc.v:22319.3-22327.6" wire $1\opc_l_r_opc$next[0:0]$672 - attribute \src "libresoc.v:21738.7-21738.25" + attribute \src "libresoc.v:21786.7-21786.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:22262.3-22270.6" + attribute \src "libresoc.v:22310.3-22318.6" wire $1\opc_l_s_opc$next[0:0]$669 - attribute \src "libresoc.v:21742.7-21742.25" + attribute \src "libresoc.v:21790.7-21790.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:22573.3-22581.6" + attribute \src "libresoc.v:22621.3-22629.6" wire width 5 $1\prev_wr_go$next[4:0]$793 - attribute \src "libresoc.v:21876.13-21876.31" + attribute \src "libresoc.v:21924.13-21924.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:22216.3-22225.6" + attribute \src "libresoc.v:22264.3-22273.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:22307.3-22315.6" + attribute \src "libresoc.v:22355.3-22363.6" wire width 5 $1\req_l_r_req$next[4:0]$684 - attribute \src "libresoc.v:21884.13-21884.32" + attribute \src "libresoc.v:21932.13-21932.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:22298.3-22306.6" + attribute \src "libresoc.v:22346.3-22354.6" wire width 5 $1\req_l_s_req$next[4:0]$681 - attribute \src "libresoc.v:21888.13-21888.32" + attribute \src "libresoc.v:21936.13-21936.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:22235.3-22243.6" + attribute \src "libresoc.v:22283.3-22291.6" wire $1\rok_l_r_rdok$next[0:0]$660 - attribute \src "libresoc.v:21900.7-21900.26" + attribute \src "libresoc.v:21948.7-21948.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:22226.3-22234.6" + attribute \src "libresoc.v:22274.3-22282.6" wire $1\rok_l_s_rdok$next[0:0]$657 - attribute \src "libresoc.v:21904.7-21904.26" + attribute \src "libresoc.v:21952.7-21952.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:22253.3-22261.6" + attribute \src "libresoc.v:22301.3-22309.6" wire $1\rst_l_r_rst$next[0:0]$666 - attribute \src "libresoc.v:21908.7-21908.25" + attribute \src "libresoc.v:21956.7-21956.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:22244.3-22252.6" + attribute \src "libresoc.v:22292.3-22300.6" wire $1\rst_l_s_rst$next[0:0]$663 - attribute \src "libresoc.v:21912.7-21912.25" + attribute \src "libresoc.v:21960.7-21960.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:22289.3-22297.6" + attribute \src "libresoc.v:22337.3-22345.6" wire width 4 $1\src_l_r_src$next[3:0]$678 - attribute \src "libresoc.v:21928.13-21928.31" + attribute \src "libresoc.v:21976.13-21976.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:22280.3-22288.6" + attribute \src "libresoc.v:22328.3-22336.6" wire width 4 $1\src_l_s_src$next[3:0]$675 - attribute \src "libresoc.v:21932.13-21932.31" + attribute \src "libresoc.v:21980.13-21980.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:22465.3-22474.6" + attribute \src "libresoc.v:22513.3-22522.6" wire width 64 $1\src_r0$next[63:0]$770 - attribute \src "libresoc.v:21940.14-21940.43" + attribute \src "libresoc.v:21988.14-21988.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:22475.3-22484.6" + attribute \src "libresoc.v:22523.3-22532.6" wire width 64 $1\src_r1$next[63:0]$773 - attribute \src "libresoc.v:21944.14-21944.43" + attribute \src "libresoc.v:21992.14-21992.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:22485.3-22494.6" + attribute \src "libresoc.v:22533.3-22542.6" wire $1\src_r2$next[0:0]$776 - attribute \src "libresoc.v:21948.7-21948.20" + attribute \src "libresoc.v:21996.7-21996.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:22495.3-22504.6" + attribute \src "libresoc.v:22543.3-22552.6" wire width 2 $1\src_r3$next[1:0]$779 - attribute \src "libresoc.v:21952.13-21952.26" + attribute \src "libresoc.v:22000.13-22000.26" wire width 2 $1\src_r3[1:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 64 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 - attribute \src "libresoc.v:22355.3-22376.6" + attribute \src "libresoc.v:22403.3-22424.6" wire width 64 $2\data_r0__o$next[63:0]$733 - attribute \src "libresoc.v:22355.3-22376.6" + attribute \src "libresoc.v:22403.3-22424.6" wire $2\data_r0__o_ok$next[0:0]$734 - attribute \src "libresoc.v:22377.3-22398.6" + attribute \src "libresoc.v:22425.3-22446.6" wire width 4 $2\data_r1__cr_a$next[3:0]$741 - attribute \src "libresoc.v:22377.3-22398.6" + attribute \src "libresoc.v:22425.3-22446.6" wire $2\data_r1__cr_a_ok$next[0:0]$742 - attribute \src "libresoc.v:22399.3-22420.6" + attribute \src "libresoc.v:22447.3-22468.6" wire width 2 $2\data_r2__xer_ca$next[1:0]$749 - attribute \src "libresoc.v:22399.3-22420.6" + attribute \src "libresoc.v:22447.3-22468.6" wire $2\data_r2__xer_ca_ok$next[0:0]$750 - attribute \src "libresoc.v:22421.3-22442.6" + attribute \src "libresoc.v:22469.3-22490.6" wire width 2 $2\data_r3__xer_ov$next[1:0]$757 - attribute \src "libresoc.v:22421.3-22442.6" + attribute \src "libresoc.v:22469.3-22490.6" wire $2\data_r3__xer_ov_ok$next[0:0]$758 - attribute \src "libresoc.v:22443.3-22464.6" + attribute \src "libresoc.v:22491.3-22512.6" wire $2\data_r4__xer_so$next[0:0]$765 - attribute \src "libresoc.v:22443.3-22464.6" + attribute \src "libresoc.v:22491.3-22512.6" wire $2\data_r4__xer_so_ok$next[0:0]$766 - attribute \src "libresoc.v:22355.3-22376.6" + attribute \src "libresoc.v:22403.3-22424.6" wire $3\data_r0__o_ok$next[0:0]$735 - attribute \src "libresoc.v:22377.3-22398.6" + attribute \src "libresoc.v:22425.3-22446.6" wire $3\data_r1__cr_a_ok$next[0:0]$743 - attribute \src "libresoc.v:22399.3-22420.6" + attribute \src "libresoc.v:22447.3-22468.6" wire $3\data_r2__xer_ca_ok$next[0:0]$751 - attribute \src "libresoc.v:22421.3-22442.6" + attribute \src "libresoc.v:22469.3-22490.6" wire $3\data_r3__xer_ov_ok$next[0:0]$759 - attribute \src "libresoc.v:22443.3-22464.6" + attribute \src "libresoc.v:22491.3-22512.6" wire $3\data_r4__xer_so_ok$next[0:0]$767 - attribute \src "libresoc.v:21968.18-21968.134" - wire $and$libresoc.v:21968$541_Y - attribute \src "libresoc.v:21969.19-21969.133" - wire $and$libresoc.v:21969$542_Y - attribute \src "libresoc.v:21970.19-21970.161" - wire width 4 $and$libresoc.v:21970$543_Y - attribute \src "libresoc.v:21973.19-21973.134" - wire width 4 $and$libresoc.v:21973$546_Y - attribute \src "libresoc.v:21975.19-21975.115" - wire width 4 $and$libresoc.v:21975$548_Y - attribute \src "libresoc.v:21976.19-21976.125" - wire $and$libresoc.v:21976$549_Y - attribute \src "libresoc.v:21977.19-21977.125" - wire $and$libresoc.v:21977$550_Y - attribute \src "libresoc.v:21978.18-21978.110" - wire $and$libresoc.v:21978$551_Y - attribute \src "libresoc.v:21979.19-21979.125" - wire $and$libresoc.v:21979$552_Y - attribute \src "libresoc.v:21980.19-21980.125" - wire $and$libresoc.v:21980$553_Y - attribute \src "libresoc.v:21981.19-21981.125" - wire $and$libresoc.v:21981$554_Y - attribute \src "libresoc.v:21982.19-21982.157" - wire width 5 $and$libresoc.v:21982$555_Y - attribute \src "libresoc.v:21983.19-21983.121" - wire width 5 $and$libresoc.v:21983$556_Y - attribute \src "libresoc.v:21984.19-21984.127" - wire $and$libresoc.v:21984$557_Y - attribute \src "libresoc.v:21985.19-21985.127" - wire $and$libresoc.v:21985$558_Y - attribute \src "libresoc.v:21986.19-21986.127" - wire $and$libresoc.v:21986$559_Y - attribute \src "libresoc.v:21987.19-21987.127" - wire $and$libresoc.v:21987$560_Y - attribute \src "libresoc.v:21988.19-21988.127" - wire $and$libresoc.v:21988$561_Y - attribute \src "libresoc.v:21990.18-21990.98" - wire $and$libresoc.v:21990$563_Y - attribute \src "libresoc.v:21992.18-21992.100" - wire $and$libresoc.v:21992$565_Y - attribute \src "libresoc.v:21993.18-21993.171" - wire width 5 $and$libresoc.v:21993$566_Y - attribute \src "libresoc.v:21995.18-21995.119" - wire width 5 $and$libresoc.v:21995$568_Y - attribute \src "libresoc.v:21998.18-21998.116" - wire $and$libresoc.v:21998$571_Y - attribute \src "libresoc.v:22002.17-22002.123" - wire $and$libresoc.v:22002$575_Y - attribute \src "libresoc.v:22004.18-22004.113" - wire $and$libresoc.v:22004$577_Y - attribute \src "libresoc.v:22005.18-22005.125" - wire width 5 $and$libresoc.v:22005$578_Y - attribute \src "libresoc.v:22007.18-22007.112" - wire $and$libresoc.v:22007$580_Y - attribute \src "libresoc.v:22009.18-22009.126" - wire $and$libresoc.v:22009$582_Y - attribute \src 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$and$libresoc.v:22059$584_Y + attribute \src "libresoc.v:22064.18-22064.130" + wire $and$libresoc.v:22064$589_Y + attribute \src "libresoc.v:22065.18-22065.124" + wire width 5 $and$libresoc.v:22065$590_Y + attribute \src "libresoc.v:22068.18-22068.116" + wire $and$libresoc.v:22068$593_Y + attribute \src "libresoc.v:22069.18-22069.119" + wire $and$libresoc.v:22069$594_Y + attribute \src "libresoc.v:22070.18-22070.121" + wire $and$libresoc.v:22070$595_Y + attribute \src "libresoc.v:22071.18-22071.121" + wire $and$libresoc.v:22071$596_Y + attribute \src "libresoc.v:22072.18-22072.121" + wire $and$libresoc.v:22072$597_Y + attribute \src "libresoc.v:22054.18-22054.113" + wire $eq$libresoc.v:22054$579_Y + attribute \src "libresoc.v:22056.18-22056.119" + wire $eq$libresoc.v:22056$581_Y + attribute \src "libresoc.v:22019.19-22019.126" + wire $not$libresoc.v:22019$544_Y + attribute \src "libresoc.v:22020.19-22020.132" + wire $not$libresoc.v:22020$545_Y + attribute \src "libresoc.v:22022.19-22022.115" + wire width 4 $not$libresoc.v:22022$547_Y + attribute \src "libresoc.v:22037.18-22037.97" + wire $not$libresoc.v:22037$562_Y + attribute \src "libresoc.v:22039.18-22039.99" + wire $not$libresoc.v:22039$564_Y + attribute \src "libresoc.v:22042.18-22042.113" + wire width 5 $not$libresoc.v:22042$567_Y + attribute \src "libresoc.v:22045.18-22045.106" + wire $not$libresoc.v:22045$570_Y + attribute \src "libresoc.v:22051.18-22051.120" + wire $not$libresoc.v:22051$576_Y + attribute \src "libresoc.v:22066.17-22066.113" + wire width 4 $not$libresoc.v:22066$591_Y + attribute \src "libresoc.v:22049.18-22049.112" + wire $or$libresoc.v:22049$574_Y + attribute \src "libresoc.v:22060.18-22060.122" + wire $or$libresoc.v:22060$585_Y + attribute \src "libresoc.v:22061.18-22061.124" + wire $or$libresoc.v:22061$586_Y + attribute \src "libresoc.v:22062.18-22062.181" + wire width 5 $or$libresoc.v:22062$587_Y + attribute \src "libresoc.v:22063.18-22063.168" + wire width 4 $or$libresoc.v:22063$588_Y + attribute \src "libresoc.v:22067.18-22067.120" + wire width 5 $or$libresoc.v:22067$592_Y + attribute \src "libresoc.v:22076.17-22076.117" + wire width 4 $or$libresoc.v:22076$601_Y + attribute \src "libresoc.v:22015.17-22015.104" + wire $reduce_and$libresoc.v:22015$540_Y + attribute \src "libresoc.v:22044.18-22044.106" + wire $reduce_or$libresoc.v:22044$569_Y + attribute \src "libresoc.v:22047.18-22047.113" + wire $reduce_or$libresoc.v:22047$572_Y + attribute \src "libresoc.v:22048.18-22048.112" + wire $reduce_or$libresoc.v:22048$573_Y + attribute \src "libresoc.v:22073.18-22073.154" + wire $ternary$libresoc.v:22073$598_Y + attribute \src "libresoc.v:22074.18-22074.155" + wire width 64 $ternary$libresoc.v:22074$599_Y + attribute \src "libresoc.v:22075.18-22075.160" + wire $ternary$libresoc.v:22075$600_Y + attribute \src "libresoc.v:22077.18-22077.172" + wire width 64 $ternary$libresoc.v:22077$602_Y + attribute \src "libresoc.v:22078.18-22078.115" + wire width 64 $ternary$libresoc.v:22078$603_Y + attribute \src "libresoc.v:22079.18-22079.125" + wire width 64 $ternary$libresoc.v:22079$604_Y + attribute \src "libresoc.v:22080.18-22080.118" + wire $ternary$libresoc.v:22080$605_Y + attribute \src "libresoc.v:22081.18-22081.118" + wire width 2 $ternary$libresoc.v:22081$606_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -32119,13 +32155,13 @@ module \alu0 wire \alu_alu0_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \alu_alu0_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_alu0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_alu0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_alu0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_alu0_p_ready_o @@ -32135,13 +32171,13 @@ module \alu0 wire width 64 \alu_alu0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_alu0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \alu_alu0_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \alu_alu0_xer_ca$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \alu_alu0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \alu_alu0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_alu0_xer_so$1 @@ -32173,11 +32209,11 @@ module \alu0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 21 \cu_busy_o @@ -32251,9 +32287,9 @@ module \alu0 wire width 2 output 38 \dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 40 \dest5_o - attribute \src "libresoc.v:21285.7-21285.15" + attribute \src "libresoc.v:21333.7-21333.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc @@ -32438,9 +32474,9 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 25 \src1_i + wire width 64 input 26 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 26 \src2_i + wire width 64 input 25 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 27 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" @@ -32481,14 +32517,14 @@ module \alu0 wire \src_sel$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 35 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 37 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 39 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:21968$541 + cell $and $and$libresoc.v:22016$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32496,10 +32532,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:21968$541_Y + connect \Y $and$libresoc.v:22016$541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:21969$542 + cell $and $and$libresoc.v:22017$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32507,10 +32543,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:21969$542_Y + connect \Y $and$libresoc.v:22017$542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21970$543 + cell $and $and$libresoc.v:22018$543 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32518,10 +32554,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:21970$543_Y + connect \Y $and$libresoc.v:22018$543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21973$546 + cell $and $and$libresoc.v:22021$546 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32529,10 +32565,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$103 connect \B { 2'11 \$107 \$105 } - connect \Y $and$libresoc.v:21973$546_Y + connect \Y $and$libresoc.v:22021$546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21975$548 + cell $and $and$libresoc.v:22023$548 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32540,10 +32576,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$109 connect \B \$111 - connect \Y $and$libresoc.v:21975$548_Y + connect \Y $and$libresoc.v:22023$548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21976$549 + cell $and $and$libresoc.v:22024$549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32551,10 +32587,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21976$549_Y + connect \Y $and$libresoc.v:22024$549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21977$550 + cell $and $and$libresoc.v:22025$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32562,10 +32598,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21977$550_Y + connect \Y $and$libresoc.v:22025$550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:21978$551 + cell $and $and$libresoc.v:22026$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32573,10 +32609,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:21978$551_Y + connect \Y $and$libresoc.v:22026$551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21979$552 + cell $and $and$libresoc.v:22027$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32584,10 +32620,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21979$552_Y + connect \Y $and$libresoc.v:22027$552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21980$553 + cell $and $and$libresoc.v:22028$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32595,10 +32631,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21980$553_Y + connect \Y $and$libresoc.v:22028$553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21981$554 + cell $and $and$libresoc.v:22029$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32606,10 +32642,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21981$554_Y + connect \Y $and$libresoc.v:22029$554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:21982$555 + cell $and $and$libresoc.v:22030$555 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32617,10 +32653,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$115 \$117 \$119 \$121 \$123 } - connect \Y $and$libresoc.v:21982$555_Y + connect \Y $and$libresoc.v:22030$555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:21983$556 + cell $and $and$libresoc.v:22031$556 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32628,10 +32664,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \$125 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:21983$556_Y + connect \Y $and$libresoc.v:22031$556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21984$557 + cell $and $and$libresoc.v:22032$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32639,10 +32675,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21984$557_Y + connect \Y $and$libresoc.v:22032$557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21985$558 + cell $and $and$libresoc.v:22033$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32650,10 +32686,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21985$558_Y + connect \Y $and$libresoc.v:22033$558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21986$559 + cell $and $and$libresoc.v:22034$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32661,10 +32697,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21986$559_Y + connect \Y $and$libresoc.v:22034$559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21987$560 + cell $and $and$libresoc.v:22035$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32672,10 +32708,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21987$560_Y + connect \Y $and$libresoc.v:22035$560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21988$561 + cell $and $and$libresoc.v:22036$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32683,10 +32719,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21988$561_Y + connect \Y $and$libresoc.v:22036$561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:21990$563 + cell $and $and$libresoc.v:22038$563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32694,10 +32730,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:21990$563_Y + connect \Y $and$libresoc.v:22038$563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:21992$565 + cell $and $and$libresoc.v:22040$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32705,10 +32741,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:21992$565_Y + connect \Y $and$libresoc.v:22040$565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:21993$566 + cell $and $and$libresoc.v:22041$566 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32716,10 +32752,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:21993$566_Y + connect \Y $and$libresoc.v:22041$566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:21995$568 + cell $and $and$libresoc.v:22043$568 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32727,10 +32763,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:21995$568_Y + connect \Y $and$libresoc.v:22043$568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:21998$571 + cell $and $and$libresoc.v:22046$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32738,10 +32774,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:21998$571_Y + connect \Y $and$libresoc.v:22046$571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:22002$575 + cell $and $and$libresoc.v:22050$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32749,10 +32785,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:22002$575_Y + connect \Y $and$libresoc.v:22050$575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:22004$577 + cell $and $and$libresoc.v:22052$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32760,10 +32796,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:22004$577_Y + connect \Y $and$libresoc.v:22052$577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:22005$578 + cell $and $and$libresoc.v:22053$578 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32771,10 +32807,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:22005$578_Y + connect \Y $and$libresoc.v:22053$578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:22007$580 + cell $and $and$libresoc.v:22055$580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32782,10 +32818,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:22007$580_Y + connect \Y $and$libresoc.v:22055$580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:22009$582 + cell $and $and$libresoc.v:22057$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32793,10 +32829,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_alu0_n_ready_i - connect \Y $and$libresoc.v:22009$582_Y + connect \Y $and$libresoc.v:22057$582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:22010$583 + cell $and $and$libresoc.v:22058$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32804,10 +32840,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_alu0_n_valid_o - connect \Y $and$libresoc.v:22010$583_Y + connect \Y $and$libresoc.v:22058$583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:22011$584 + cell $and $and$libresoc.v:22059$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32815,10 +32851,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:22011$584_Y + connect \Y $and$libresoc.v:22059$584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:22016$589 + cell $and $and$libresoc.v:22064$589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32826,10 +32862,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:22016$589_Y + connect \Y $and$libresoc.v:22064$589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:22017$590 + cell $and $and$libresoc.v:22065$590 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32837,10 +32873,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:22017$590_Y + connect \Y $and$libresoc.v:22065$590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:22020$593 + cell $and $and$libresoc.v:22068$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32848,10 +32884,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:22020$593_Y + connect \Y $and$libresoc.v:22068$593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:22021$594 + cell $and $and$libresoc.v:22069$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32859,10 +32895,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:22021$594_Y + connect \Y $and$libresoc.v:22069$594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:22022$595 + cell $and $and$libresoc.v:22070$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32870,10 +32906,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:22022$595_Y + connect \Y $and$libresoc.v:22070$595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:22023$596 + cell $and $and$libresoc.v:22071$596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32881,10 +32917,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:22023$596_Y + connect \Y $and$libresoc.v:22071$596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:22024$597 + cell $and $and$libresoc.v:22072$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32892,10 +32928,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:22024$597_Y + connect \Y $and$libresoc.v:22072$597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:22006$579 + cell $eq $eq$libresoc.v:22054$579 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32903,10 +32939,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:22006$579_Y + connect \Y $eq$libresoc.v:22054$579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:22008$581 + cell $eq $eq$libresoc.v:22056$581 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32914,82 +32950,82 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:22008$581_Y + connect \Y $eq$libresoc.v:22056$581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:21971$544 + cell $not $not$libresoc.v:22019$544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_alu_op__zero_a - connect \Y $not$libresoc.v:21971$544_Y + connect \Y $not$libresoc.v:22019$544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:21972$545 + cell $not $not$libresoc.v:22020$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_alu_op__imm_data__ok - connect \Y $not$libresoc.v:21972$545_Y + connect \Y $not$libresoc.v:22020$545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:21974$547 + cell $not $not$libresoc.v:22022$547 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:21974$547_Y + connect \Y $not$libresoc.v:22022$547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:21989$562 + cell $not $not$libresoc.v:22037$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:21989$562_Y + connect \Y $not$libresoc.v:22037$562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:21991$564 + cell $not $not$libresoc.v:22039$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:21991$564_Y + connect \Y $not$libresoc.v:22039$564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:21994$567 + cell $not $not$libresoc.v:22042$567 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:21994$567_Y + connect \Y $not$libresoc.v:22042$567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:21997$570 + cell $not $not$libresoc.v:22045$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:21997$570_Y + connect \Y $not$libresoc.v:22045$570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:22003$576 + cell $not $not$libresoc.v:22051$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_ready_i - connect \Y $not$libresoc.v:22003$576_Y + connect \Y $not$libresoc.v:22051$576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:22018$591 + cell $not $not$libresoc.v:22066$591 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:22018$591_Y + connect \Y $not$libresoc.v:22066$591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:22001$574 + cell $or $or$libresoc.v:22049$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32997,10 +33033,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:22001$574_Y + connect \Y $or$libresoc.v:22049$574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:22012$585 + cell $or $or$libresoc.v:22060$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -33008,10 +33044,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:22012$585_Y + connect \Y $or$libresoc.v:22060$585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:22013$586 + cell $or $or$libresoc.v:22061$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -33019,10 +33055,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:22013$586_Y + connect \Y $or$libresoc.v:22061$586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:22014$587 + cell $or $or$libresoc.v:22062$587 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -33030,10 +33066,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:22014$587_Y + connect \Y $or$libresoc.v:22062$587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:22015$588 + cell $or $or$libresoc.v:22063$588 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -33041,10 +33077,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:22015$588_Y + connect \Y $or$libresoc.v:22063$588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:22019$592 + cell $or $or$libresoc.v:22067$592 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -33052,10 +33088,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:22019$592_Y + connect \Y $or$libresoc.v:22067$592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:22028$601 + cell $or $or$libresoc.v:22076$601 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -33063,106 +33099,106 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:22028$601_Y + connect \Y $or$libresoc.v:22076$601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:21967$540 + cell $reduce_and $reduce_and$libresoc.v:22015$540 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:21967$540_Y + connect \Y $reduce_and$libresoc.v:22015$540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:21996$569 + cell $reduce_or $reduce_or$libresoc.v:22044$569 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:21996$569_Y + connect \Y $reduce_or$libresoc.v:22044$569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:21999$572 + cell $reduce_or $reduce_or$libresoc.v:22047$572 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:21999$572_Y + connect \Y $reduce_or$libresoc.v:22047$572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:22000$573 + cell $reduce_or $reduce_or$libresoc.v:22048$573 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:22000$573_Y + connect \Y $reduce_or$libresoc.v:22048$573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:22025$598 + cell $mux $ternary$libresoc.v:22073$598 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_alu0_alu_op__zero_a - connect \Y $ternary$libresoc.v:22025$598_Y + connect \Y $ternary$libresoc.v:22073$598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:22026$599 + cell $mux $ternary$libresoc.v:22074$599 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_alu0_alu_op__zero_a - connect \Y $ternary$libresoc.v:22026$599_Y + connect \Y $ternary$libresoc.v:22074$599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:22027$600 + cell $mux $ternary$libresoc.v:22075$600 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $ternary$libresoc.v:22027$600_Y + connect \Y $ternary$libresoc.v:22075$600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:22029$602 + cell $mux $ternary$libresoc.v:22077$602 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_alu0_alu_op__imm_data__data connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $ternary$libresoc.v:22029$602_Y + connect \Y $ternary$libresoc.v:22077$602_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:22030$603 + cell $mux $ternary$libresoc.v:22078$603 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:22030$603_Y + connect \Y $ternary$libresoc.v:22078$603_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:22031$604 + cell $mux $ternary$libresoc.v:22079$604 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$88 connect \S \src_sel$85 - connect \Y $ternary$libresoc.v:22031$604_Y + connect \Y $ternary$libresoc.v:22079$604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:22032$605 + cell $mux $ternary$libresoc.v:22080$605 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:22032$605_Y + connect \Y $ternary$libresoc.v:22080$605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:22033$606 + cell $mux $ternary$libresoc.v:22081$606 parameter \WIDTH 2 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:22033$606_Y + connect \Y $ternary$libresoc.v:22081$606_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:22128.12-22167.4" + attribute \src "libresoc.v:22176.12-22215.4" cell \alu_alu0 \alu_alu0 connect \alu_op__data_len \alu_alu0_alu_op__data_len connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit @@ -33204,7 +33240,7 @@ module \alu0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:22168.9-22174.4" + attribute \src "libresoc.v:22216.9-22222.4" cell \alu_l \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33213,7 +33249,7 @@ module \alu0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:22175.10-22181.4" + attribute \src "libresoc.v:22223.10-22229.4" cell \alui_l \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33222,7 +33258,7 @@ module \alu0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:22182.9-22188.4" + attribute \src "libresoc.v:22230.9-22236.4" cell \opc_l \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33231,7 +33267,7 @@ module \alu0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:22189.9-22195.4" + attribute \src "libresoc.v:22237.9-22243.4" cell \req_l \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33240,7 +33276,7 @@ module \alu0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:22196.9-22202.4" + attribute \src "libresoc.v:22244.9-22250.4" cell \rok_l \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33249,7 +33285,7 @@ module \alu0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:22203.9-22208.4" + attribute \src "libresoc.v:22251.9-22256.4" cell \rst_l \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33257,7 +33293,7 @@ module \alu0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:22209.9-22215.4" + attribute \src "libresoc.v:22257.9-22263.4" cell \src_l \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33265,727 +33301,727 @@ module \alu0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:21285.7-21285.20" - process $proc$libresoc.v:21285$794 + attribute \src "libresoc.v:21333.7-21333.20" + process $proc$libresoc.v:21333$794 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21423.7-21423.24" - process $proc$libresoc.v:21423$795 + attribute \src "libresoc.v:21471.7-21471.24" + process $proc$libresoc.v:21471$795 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:21431.13-21431.45" - process $proc$libresoc.v:21431$796 + attribute \src "libresoc.v:21479.13-21479.45" + process $proc$libresoc.v:21479$796 assign { } { } assign $1\alu_alu0_alu_op__data_len[3:0] 4'0000 sync always sync init update \alu_alu0_alu_op__data_len $1\alu_alu0_alu_op__data_len[3:0] end - attribute \src "libresoc.v:21450.14-21450.49" - process $proc$libresoc.v:21450$797 + attribute \src "libresoc.v:21498.14-21498.49" + process $proc$libresoc.v:21498$797 assign { } { } assign $1\alu_alu0_alu_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:21454.14-21454.68" - process $proc$libresoc.v:21454$798 + attribute \src "libresoc.v:21502.14-21502.68" + process $proc$libresoc.v:21502$798 assign { } { } assign $1\alu_alu0_alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_alu0_alu_op__imm_data__data $1\alu_alu0_alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:21458.7-21458.43" - process $proc$libresoc.v:21458$799 + attribute \src "libresoc.v:21506.7-21506.43" + process $proc$libresoc.v:21506$799 assign { } { } assign $1\alu_alu0_alu_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__imm_data__ok $1\alu_alu0_alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:21466.13-21466.48" - process $proc$libresoc.v:21466$800 + attribute \src "libresoc.v:21514.13-21514.48" + process $proc$libresoc.v:21514$800 assign { } { } assign $1\alu_alu0_alu_op__input_carry[1:0] 2'00 sync always sync init update \alu_alu0_alu_op__input_carry $1\alu_alu0_alu_op__input_carry[1:0] end - attribute \src "libresoc.v:21470.14-21470.43" - process $proc$libresoc.v:21470$801 + attribute \src "libresoc.v:21518.14-21518.43" + process $proc$libresoc.v:21518$801 assign { } { } assign $1\alu_alu0_alu_op__insn[31:0] 0 sync always sync init update \alu_alu0_alu_op__insn $1\alu_alu0_alu_op__insn[31:0] end - attribute \src "libresoc.v:21549.13-21549.47" - process $proc$libresoc.v:21549$802 + attribute \src "libresoc.v:21597.13-21597.47" + process $proc$libresoc.v:21597$802 assign { } { } assign $1\alu_alu0_alu_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_alu0_alu_op__insn_type $1\alu_alu0_alu_op__insn_type[6:0] end - attribute \src "libresoc.v:21553.7-21553.40" - process $proc$libresoc.v:21553$803 + attribute \src "libresoc.v:21601.7-21601.40" + process $proc$libresoc.v:21601$803 assign { } { } assign $1\alu_alu0_alu_op__invert_in[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__invert_in $1\alu_alu0_alu_op__invert_in[0:0] end - attribute \src "libresoc.v:21557.7-21557.41" - process $proc$libresoc.v:21557$804 + attribute \src "libresoc.v:21605.7-21605.41" + process $proc$libresoc.v:21605$804 assign { } { } assign $1\alu_alu0_alu_op__invert_out[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__invert_out $1\alu_alu0_alu_op__invert_out[0:0] end - attribute \src "libresoc.v:21561.7-21561.39" - process $proc$libresoc.v:21561$805 + attribute \src "libresoc.v:21609.7-21609.39" + process $proc$libresoc.v:21609$805 assign { } { } assign $1\alu_alu0_alu_op__is_32bit[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__is_32bit $1\alu_alu0_alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:21565.7-21565.40" - process $proc$libresoc.v:21565$806 + attribute \src "libresoc.v:21613.7-21613.40" + process $proc$libresoc.v:21613$806 assign { } { } assign $1\alu_alu0_alu_op__is_signed[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__is_signed $1\alu_alu0_alu_op__is_signed[0:0] end - attribute \src "libresoc.v:21569.7-21569.37" - process $proc$libresoc.v:21569$807 + attribute \src "libresoc.v:21617.7-21617.37" + process $proc$libresoc.v:21617$807 assign { } { } assign $1\alu_alu0_alu_op__oe__oe[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__oe__oe $1\alu_alu0_alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:21573.7-21573.37" - process $proc$libresoc.v:21573$808 + attribute \src "libresoc.v:21621.7-21621.37" + process $proc$libresoc.v:21621$808 assign { } { } assign $1\alu_alu0_alu_op__oe__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__oe__ok $1\alu_alu0_alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:21577.7-21577.43" - process $proc$libresoc.v:21577$809 + attribute \src "libresoc.v:21625.7-21625.43" + process $proc$libresoc.v:21625$809 assign { } { } assign $1\alu_alu0_alu_op__output_carry[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__output_carry $1\alu_alu0_alu_op__output_carry[0:0] end - attribute \src "libresoc.v:21581.7-21581.37" - process $proc$libresoc.v:21581$810 + attribute \src "libresoc.v:21629.7-21629.37" + process $proc$libresoc.v:21629$810 assign { } { } assign $1\alu_alu0_alu_op__rc__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__rc__ok $1\alu_alu0_alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:21585.7-21585.37" - process $proc$libresoc.v:21585$811 + attribute \src "libresoc.v:21633.7-21633.37" + process $proc$libresoc.v:21633$811 assign { } { } assign $1\alu_alu0_alu_op__rc__rc[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__rc__rc $1\alu_alu0_alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:21589.7-21589.40" - process $proc$libresoc.v:21589$812 + attribute \src "libresoc.v:21637.7-21637.40" + process $proc$libresoc.v:21637$812 assign { } { } assign $1\alu_alu0_alu_op__write_cr0[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__write_cr0 $1\alu_alu0_alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:21593.7-21593.37" - process $proc$libresoc.v:21593$813 + attribute \src "libresoc.v:21641.7-21641.37" + process $proc$libresoc.v:21641$813 assign { } { } assign $1\alu_alu0_alu_op__zero_a[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__zero_a $1\alu_alu0_alu_op__zero_a[0:0] end - attribute \src "libresoc.v:21625.7-21625.26" - process $proc$libresoc.v:21625$814 + attribute \src "libresoc.v:21673.7-21673.26" + process $proc$libresoc.v:21673$814 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:21633.7-21633.25" - process $proc$libresoc.v:21633$815 + attribute \src "libresoc.v:21681.7-21681.25" + process $proc$libresoc.v:21681$815 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:21645.7-21645.27" - process $proc$libresoc.v:21645$816 + attribute \src "libresoc.v:21693.7-21693.27" + process $proc$libresoc.v:21693$816 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:21679.14-21679.47" - process $proc$libresoc.v:21679$817 + attribute \src "libresoc.v:21727.14-21727.47" + process $proc$libresoc.v:21727$817 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:21683.7-21683.27" - process $proc$libresoc.v:21683$818 + attribute \src "libresoc.v:21731.7-21731.27" + process $proc$libresoc.v:21731$818 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:21687.13-21687.33" - process $proc$libresoc.v:21687$819 + attribute \src "libresoc.v:21735.13-21735.33" + process $proc$libresoc.v:21735$819 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:21691.7-21691.30" - process $proc$libresoc.v:21691$820 + attribute \src "libresoc.v:21739.7-21739.30" + process $proc$libresoc.v:21739$820 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:21695.13-21695.35" - process $proc$libresoc.v:21695$821 + attribute \src "libresoc.v:21743.13-21743.35" + process $proc$libresoc.v:21743$821 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:21699.7-21699.32" - process $proc$libresoc.v:21699$822 + attribute \src "libresoc.v:21747.7-21747.32" + process $proc$libresoc.v:21747$822 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:21703.13-21703.35" - process $proc$libresoc.v:21703$823 + attribute \src "libresoc.v:21751.13-21751.35" + process $proc$libresoc.v:21751$823 assign { } { } assign $1\data_r3__xer_ov[1:0] 2'00 sync always sync init update \data_r3__xer_ov $1\data_r3__xer_ov[1:0] end - attribute \src "libresoc.v:21707.7-21707.32" - process $proc$libresoc.v:21707$824 + attribute \src "libresoc.v:21755.7-21755.32" + process $proc$libresoc.v:21755$824 assign { } { } assign $1\data_r3__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r3__xer_ov_ok $1\data_r3__xer_ov_ok[0:0] end - attribute \src "libresoc.v:21711.7-21711.29" - process $proc$libresoc.v:21711$825 + attribute \src "libresoc.v:21759.7-21759.29" + process $proc$libresoc.v:21759$825 assign { } { } assign $1\data_r4__xer_so[0:0] 1'0 sync always sync init update \data_r4__xer_so $1\data_r4__xer_so[0:0] end - attribute \src "libresoc.v:21715.7-21715.32" - process $proc$libresoc.v:21715$826 + attribute \src "libresoc.v:21763.7-21763.32" + process $proc$libresoc.v:21763$826 assign { } { } assign $1\data_r4__xer_so_ok[0:0] 1'0 sync always sync init update \data_r4__xer_so_ok $1\data_r4__xer_so_ok[0:0] end - attribute \src "libresoc.v:21738.7-21738.25" - process $proc$libresoc.v:21738$827 + attribute \src "libresoc.v:21786.7-21786.25" + process $proc$libresoc.v:21786$827 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:21742.7-21742.25" - process $proc$libresoc.v:21742$828 + attribute \src "libresoc.v:21790.7-21790.25" + process $proc$libresoc.v:21790$828 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:21876.13-21876.31" - process $proc$libresoc.v:21876$829 + attribute \src "libresoc.v:21924.13-21924.31" + process $proc$libresoc.v:21924$829 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:21884.13-21884.32" - process $proc$libresoc.v:21884$830 + attribute \src "libresoc.v:21932.13-21932.32" + process $proc$libresoc.v:21932$830 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:21888.13-21888.32" - process $proc$libresoc.v:21888$831 + attribute \src "libresoc.v:21936.13-21936.32" + process $proc$libresoc.v:21936$831 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:21900.7-21900.26" - process $proc$libresoc.v:21900$832 + attribute \src "libresoc.v:21948.7-21948.26" + process $proc$libresoc.v:21948$832 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:21904.7-21904.26" - process $proc$libresoc.v:21904$833 + attribute \src "libresoc.v:21952.7-21952.26" + process $proc$libresoc.v:21952$833 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:21908.7-21908.25" - process $proc$libresoc.v:21908$834 + attribute \src "libresoc.v:21956.7-21956.25" + process $proc$libresoc.v:21956$834 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:21912.7-21912.25" - process $proc$libresoc.v:21912$835 + attribute \src "libresoc.v:21960.7-21960.25" + process $proc$libresoc.v:21960$835 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:21928.13-21928.31" - process $proc$libresoc.v:21928$836 + attribute \src "libresoc.v:21976.13-21976.31" + process $proc$libresoc.v:21976$836 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:21932.13-21932.31" - process $proc$libresoc.v:21932$837 + attribute \src "libresoc.v:21980.13-21980.31" + process $proc$libresoc.v:21980$837 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:21940.14-21940.43" - process $proc$libresoc.v:21940$838 + attribute \src "libresoc.v:21988.14-21988.43" + process $proc$libresoc.v:21988$838 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:21944.14-21944.43" - process $proc$libresoc.v:21944$839 + attribute \src "libresoc.v:21992.14-21992.43" + process $proc$libresoc.v:21992$839 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:21948.7-21948.20" - process $proc$libresoc.v:21948$840 + attribute \src "libresoc.v:21996.7-21996.20" + process $proc$libresoc.v:21996$840 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:21952.13-21952.26" - process $proc$libresoc.v:21952$841 + attribute \src "libresoc.v:22000.13-22000.26" + process $proc$libresoc.v:22000$841 assign { } { } assign $1\src_r3[1:0] 2'00 sync always sync init update \src_r3 $1\src_r3[1:0] end - attribute \src "libresoc.v:22034.3-22035.39" - process $proc$libresoc.v:22034$607 + attribute \src "libresoc.v:22082.3-22083.39" + process $proc$libresoc.v:22082$607 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:22036.3-22037.43" - process $proc$libresoc.v:22036$608 + attribute \src "libresoc.v:22084.3-22085.43" + process $proc$libresoc.v:22084$608 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:22038.3-22039.29" - process $proc$libresoc.v:22038$609 + attribute \src "libresoc.v:22086.3-22087.29" + process $proc$libresoc.v:22086$609 assign { } { } assign $0\src_r3[1:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[1:0] end - attribute \src "libresoc.v:22040.3-22041.29" - process $proc$libresoc.v:22040$610 + attribute \src "libresoc.v:22088.3-22089.29" + process $proc$libresoc.v:22088$610 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:22042.3-22043.29" - process $proc$libresoc.v:22042$611 + attribute \src "libresoc.v:22090.3-22091.29" + process $proc$libresoc.v:22090$611 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:22044.3-22045.29" - process $proc$libresoc.v:22044$612 + attribute \src "libresoc.v:22092.3-22093.29" + process $proc$libresoc.v:22092$612 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:22046.3-22047.47" - process $proc$libresoc.v:22046$613 + attribute \src "libresoc.v:22094.3-22095.47" + process $proc$libresoc.v:22094$613 assign { } { } assign $0\data_r4__xer_so[0:0] \data_r4__xer_so$next sync posedge \coresync_clk update \data_r4__xer_so $0\data_r4__xer_so[0:0] end - attribute \src "libresoc.v:22048.3-22049.53" - process $proc$libresoc.v:22048$614 + attribute \src "libresoc.v:22096.3-22097.53" + process $proc$libresoc.v:22096$614 assign { } { } assign $0\data_r4__xer_so_ok[0:0] \data_r4__xer_so_ok$next sync posedge \coresync_clk update \data_r4__xer_so_ok $0\data_r4__xer_so_ok[0:0] end - attribute \src "libresoc.v:22050.3-22051.47" - process $proc$libresoc.v:22050$615 + attribute \src "libresoc.v:22098.3-22099.47" + process $proc$libresoc.v:22098$615 assign { } { } assign $0\data_r3__xer_ov[1:0] \data_r3__xer_ov$next sync posedge \coresync_clk update \data_r3__xer_ov $0\data_r3__xer_ov[1:0] end - attribute \src "libresoc.v:22052.3-22053.53" - process $proc$libresoc.v:22052$616 + attribute \src "libresoc.v:22100.3-22101.53" + process $proc$libresoc.v:22100$616 assign { } { } assign $0\data_r3__xer_ov_ok[0:0] \data_r3__xer_ov_ok$next sync posedge \coresync_clk update \data_r3__xer_ov_ok $0\data_r3__xer_ov_ok[0:0] end - attribute \src "libresoc.v:22054.3-22055.47" - process $proc$libresoc.v:22054$617 + attribute \src "libresoc.v:22102.3-22103.47" + process $proc$libresoc.v:22102$617 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:22056.3-22057.53" - process $proc$libresoc.v:22056$618 + attribute \src "libresoc.v:22104.3-22105.53" + process $proc$libresoc.v:22104$618 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:22058.3-22059.43" - process $proc$libresoc.v:22058$619 + attribute \src "libresoc.v:22106.3-22107.43" + process $proc$libresoc.v:22106$619 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:22060.3-22061.49" - process $proc$libresoc.v:22060$620 + attribute \src "libresoc.v:22108.3-22109.49" + process $proc$libresoc.v:22108$620 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:22062.3-22063.37" - process $proc$libresoc.v:22062$621 + attribute \src "libresoc.v:22110.3-22111.37" + process $proc$libresoc.v:22110$621 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:22064.3-22065.43" - process $proc$libresoc.v:22064$622 + attribute \src "libresoc.v:22112.3-22113.43" + process $proc$libresoc.v:22112$622 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:22066.3-22067.69" - process $proc$libresoc.v:22066$623 + attribute \src "libresoc.v:22114.3-22115.69" + process $proc$libresoc.v:22114$623 assign { } { } assign $0\alu_alu0_alu_op__insn_type[6:0] \alu_alu0_alu_op__insn_type$next sync posedge \coresync_clk update \alu_alu0_alu_op__insn_type $0\alu_alu0_alu_op__insn_type[6:0] end - attribute \src "libresoc.v:22068.3-22069.65" - process $proc$libresoc.v:22068$624 + attribute \src "libresoc.v:22116.3-22117.65" + process $proc$libresoc.v:22116$624 assign { } { } assign $0\alu_alu0_alu_op__fn_unit[13:0] \alu_alu0_alu_op__fn_unit$next sync posedge \coresync_clk update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:22070.3-22071.79" - process $proc$libresoc.v:22070$625 + attribute \src "libresoc.v:22118.3-22119.79" + process $proc$libresoc.v:22118$625 assign { } { } assign $0\alu_alu0_alu_op__imm_data__data[63:0] \alu_alu0_alu_op__imm_data__data$next sync posedge \coresync_clk update \alu_alu0_alu_op__imm_data__data $0\alu_alu0_alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:22072.3-22073.75" - process $proc$libresoc.v:22072$626 + attribute \src "libresoc.v:22120.3-22121.75" + process $proc$libresoc.v:22120$626 assign { } { } assign $0\alu_alu0_alu_op__imm_data__ok[0:0] \alu_alu0_alu_op__imm_data__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__imm_data__ok $0\alu_alu0_alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:22074.3-22075.63" - process $proc$libresoc.v:22074$627 + attribute \src "libresoc.v:22122.3-22123.63" + process $proc$libresoc.v:22122$627 assign { } { } assign $0\alu_alu0_alu_op__rc__rc[0:0] \alu_alu0_alu_op__rc__rc$next sync posedge \coresync_clk update \alu_alu0_alu_op__rc__rc $0\alu_alu0_alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:22076.3-22077.63" - process $proc$libresoc.v:22076$628 + attribute \src "libresoc.v:22124.3-22125.63" + process $proc$libresoc.v:22124$628 assign { } { } assign $0\alu_alu0_alu_op__rc__ok[0:0] \alu_alu0_alu_op__rc__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__rc__ok $0\alu_alu0_alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:22078.3-22079.63" - process $proc$libresoc.v:22078$629 + attribute \src "libresoc.v:22126.3-22127.63" + process $proc$libresoc.v:22126$629 assign { } { } assign $0\alu_alu0_alu_op__oe__oe[0:0] \alu_alu0_alu_op__oe__oe$next sync posedge \coresync_clk update \alu_alu0_alu_op__oe__oe $0\alu_alu0_alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:22080.3-22081.63" - process $proc$libresoc.v:22080$630 + attribute \src "libresoc.v:22128.3-22129.63" + process $proc$libresoc.v:22128$630 assign { } { } assign $0\alu_alu0_alu_op__oe__ok[0:0] \alu_alu0_alu_op__oe__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__oe__ok $0\alu_alu0_alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:22082.3-22083.69" - process $proc$libresoc.v:22082$631 + attribute \src "libresoc.v:22130.3-22131.69" + process $proc$libresoc.v:22130$631 assign { } { } assign $0\alu_alu0_alu_op__invert_in[0:0] \alu_alu0_alu_op__invert_in$next sync posedge \coresync_clk update \alu_alu0_alu_op__invert_in $0\alu_alu0_alu_op__invert_in[0:0] end - attribute \src "libresoc.v:22084.3-22085.63" - process $proc$libresoc.v:22084$632 + attribute \src "libresoc.v:22132.3-22133.63" + process $proc$libresoc.v:22132$632 assign { } { } assign $0\alu_alu0_alu_op__zero_a[0:0] \alu_alu0_alu_op__zero_a$next sync posedge \coresync_clk update \alu_alu0_alu_op__zero_a $0\alu_alu0_alu_op__zero_a[0:0] end - attribute \src "libresoc.v:22086.3-22087.71" - process $proc$libresoc.v:22086$633 + attribute \src "libresoc.v:22134.3-22135.71" + process $proc$libresoc.v:22134$633 assign { } { } assign $0\alu_alu0_alu_op__invert_out[0:0] \alu_alu0_alu_op__invert_out$next sync posedge \coresync_clk update \alu_alu0_alu_op__invert_out $0\alu_alu0_alu_op__invert_out[0:0] end - attribute \src "libresoc.v:22088.3-22089.69" - process $proc$libresoc.v:22088$634 + attribute \src "libresoc.v:22136.3-22137.69" + process $proc$libresoc.v:22136$634 assign { } { } assign $0\alu_alu0_alu_op__write_cr0[0:0] \alu_alu0_alu_op__write_cr0$next sync posedge \coresync_clk update \alu_alu0_alu_op__write_cr0 $0\alu_alu0_alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:22090.3-22091.73" - process $proc$libresoc.v:22090$635 + attribute \src "libresoc.v:22138.3-22139.73" + process $proc$libresoc.v:22138$635 assign { } { } assign $0\alu_alu0_alu_op__input_carry[1:0] \alu_alu0_alu_op__input_carry$next sync posedge \coresync_clk update \alu_alu0_alu_op__input_carry $0\alu_alu0_alu_op__input_carry[1:0] end - attribute \src "libresoc.v:22092.3-22093.75" - process $proc$libresoc.v:22092$636 + attribute \src "libresoc.v:22140.3-22141.75" + process $proc$libresoc.v:22140$636 assign { } { } assign $0\alu_alu0_alu_op__output_carry[0:0] \alu_alu0_alu_op__output_carry$next sync posedge \coresync_clk update \alu_alu0_alu_op__output_carry $0\alu_alu0_alu_op__output_carry[0:0] end - attribute \src "libresoc.v:22094.3-22095.67" - process $proc$libresoc.v:22094$637 + attribute \src "libresoc.v:22142.3-22143.67" + process $proc$libresoc.v:22142$637 assign { } { } assign $0\alu_alu0_alu_op__is_32bit[0:0] \alu_alu0_alu_op__is_32bit$next sync posedge \coresync_clk update \alu_alu0_alu_op__is_32bit $0\alu_alu0_alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:22096.3-22097.69" - process $proc$libresoc.v:22096$638 + attribute \src "libresoc.v:22144.3-22145.69" + process $proc$libresoc.v:22144$638 assign { } { } assign $0\alu_alu0_alu_op__is_signed[0:0] \alu_alu0_alu_op__is_signed$next sync posedge \coresync_clk update \alu_alu0_alu_op__is_signed $0\alu_alu0_alu_op__is_signed[0:0] end - attribute \src "libresoc.v:22098.3-22099.67" - process $proc$libresoc.v:22098$639 + attribute \src "libresoc.v:22146.3-22147.67" + process $proc$libresoc.v:22146$639 assign { } { } assign $0\alu_alu0_alu_op__data_len[3:0] \alu_alu0_alu_op__data_len$next sync posedge \coresync_clk update \alu_alu0_alu_op__data_len $0\alu_alu0_alu_op__data_len[3:0] end - attribute \src "libresoc.v:22100.3-22101.59" - process $proc$libresoc.v:22100$640 + attribute \src "libresoc.v:22148.3-22149.59" + process $proc$libresoc.v:22148$640 assign { } { } assign $0\alu_alu0_alu_op__insn[31:0] \alu_alu0_alu_op__insn$next sync posedge \coresync_clk update \alu_alu0_alu_op__insn $0\alu_alu0_alu_op__insn[31:0] end - attribute \src "libresoc.v:22102.3-22103.39" - process $proc$libresoc.v:22102$641 + attribute \src "libresoc.v:22150.3-22151.39" + process $proc$libresoc.v:22150$641 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:22104.3-22105.39" - process $proc$libresoc.v:22104$642 + attribute \src "libresoc.v:22152.3-22153.39" + process $proc$libresoc.v:22152$642 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:22106.3-22107.39" - process $proc$libresoc.v:22106$643 + attribute \src "libresoc.v:22154.3-22155.39" + process $proc$libresoc.v:22154$643 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:22108.3-22109.39" - process $proc$libresoc.v:22108$644 + attribute \src "libresoc.v:22156.3-22157.39" + process $proc$libresoc.v:22156$644 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:22110.3-22111.39" - process $proc$libresoc.v:22110$645 + attribute \src "libresoc.v:22158.3-22159.39" + process $proc$libresoc.v:22158$645 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:22112.3-22113.39" - process $proc$libresoc.v:22112$646 + attribute \src "libresoc.v:22160.3-22161.39" + process $proc$libresoc.v:22160$646 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:22114.3-22115.39" - process $proc$libresoc.v:22114$647 + attribute \src "libresoc.v:22162.3-22163.39" + process $proc$libresoc.v:22162$647 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:22116.3-22117.39" - process $proc$libresoc.v:22116$648 + attribute \src "libresoc.v:22164.3-22165.39" + process $proc$libresoc.v:22164$648 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:22118.3-22119.41" - process $proc$libresoc.v:22118$649 + attribute \src "libresoc.v:22166.3-22167.41" + process $proc$libresoc.v:22166$649 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:22120.3-22121.41" - process $proc$libresoc.v:22120$650 + attribute \src "libresoc.v:22168.3-22169.41" + process $proc$libresoc.v:22168$650 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:22122.3-22123.37" - process $proc$libresoc.v:22122$651 + attribute \src "libresoc.v:22170.3-22171.37" + process $proc$libresoc.v:22170$651 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:22124.3-22125.40" - process $proc$libresoc.v:22124$652 + attribute \src "libresoc.v:22172.3-22173.40" + process $proc$libresoc.v:22172$652 assign { } { } assign $0\alu_done_dly[0:0] \alu_alu0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:22126.3-22127.25" - process $proc$libresoc.v:22126$653 + attribute \src "libresoc.v:22174.3-22175.25" + process $proc$libresoc.v:22174$653 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:22216.3-22225.6" - process $proc$libresoc.v:22216$654 + attribute \src "libresoc.v:22264.3-22273.6" + process $proc$libresoc.v:22264$654 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:22217.5-22217.29" + attribute \src "libresoc.v:22265.5-22265.29" switch \initial - attribute \src "libresoc.v:22217.9-22217.17" + attribute \src "libresoc.v:22265.9-22265.17" case 1'1 case end @@ -34001,14 +34037,14 @@ module \alu0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:22226.3-22234.6" - process $proc$libresoc.v:22226$655 + attribute \src "libresoc.v:22274.3-22282.6" + process $proc$libresoc.v:22274$655 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$656 $1\rok_l_s_rdok$next[0:0]$657 - attribute \src "libresoc.v:22227.5-22227.29" + attribute \src "libresoc.v:22275.5-22275.29" switch \initial - attribute \src "libresoc.v:22227.9-22227.17" + attribute \src "libresoc.v:22275.9-22275.17" case 1'1 case end @@ -34024,14 +34060,14 @@ module \alu0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$656 end - attribute \src "libresoc.v:22235.3-22243.6" - process $proc$libresoc.v:22235$658 + attribute \src "libresoc.v:22283.3-22291.6" + process $proc$libresoc.v:22283$658 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$659 $1\rok_l_r_rdok$next[0:0]$660 - attribute \src "libresoc.v:22236.5-22236.29" + attribute \src "libresoc.v:22284.5-22284.29" switch \initial - attribute \src "libresoc.v:22236.9-22236.17" + attribute \src "libresoc.v:22284.9-22284.17" case 1'1 case end @@ -34047,14 +34083,14 @@ module \alu0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$659 end - attribute \src "libresoc.v:22244.3-22252.6" - process $proc$libresoc.v:22244$661 + attribute \src "libresoc.v:22292.3-22300.6" + process $proc$libresoc.v:22292$661 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$662 $1\rst_l_s_rst$next[0:0]$663 - attribute \src "libresoc.v:22245.5-22245.29" + attribute \src "libresoc.v:22293.5-22293.29" switch \initial - attribute \src "libresoc.v:22245.9-22245.17" + attribute \src "libresoc.v:22293.9-22293.17" case 1'1 case end @@ -34070,14 +34106,14 @@ module \alu0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$662 end - attribute \src "libresoc.v:22253.3-22261.6" - process $proc$libresoc.v:22253$664 + attribute \src "libresoc.v:22301.3-22309.6" + process $proc$libresoc.v:22301$664 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$665 $1\rst_l_r_rst$next[0:0]$666 - attribute \src "libresoc.v:22254.5-22254.29" + attribute \src "libresoc.v:22302.5-22302.29" switch \initial - attribute \src "libresoc.v:22254.9-22254.17" + attribute \src "libresoc.v:22302.9-22302.17" case 1'1 case end @@ -34093,14 +34129,14 @@ module \alu0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$665 end - attribute \src "libresoc.v:22262.3-22270.6" - process $proc$libresoc.v:22262$667 + attribute \src "libresoc.v:22310.3-22318.6" + process $proc$libresoc.v:22310$667 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$668 $1\opc_l_s_opc$next[0:0]$669 - attribute \src "libresoc.v:22263.5-22263.29" + attribute \src "libresoc.v:22311.5-22311.29" switch \initial - attribute \src "libresoc.v:22263.9-22263.17" + attribute \src "libresoc.v:22311.9-22311.17" case 1'1 case end @@ -34116,14 +34152,14 @@ module \alu0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$668 end - attribute \src "libresoc.v:22271.3-22279.6" - process $proc$libresoc.v:22271$670 + attribute \src "libresoc.v:22319.3-22327.6" + process $proc$libresoc.v:22319$670 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$671 $1\opc_l_r_opc$next[0:0]$672 - attribute \src "libresoc.v:22272.5-22272.29" + attribute \src "libresoc.v:22320.5-22320.29" switch \initial - attribute \src "libresoc.v:22272.9-22272.17" + attribute \src "libresoc.v:22320.9-22320.17" case 1'1 case end @@ -34139,14 +34175,14 @@ module \alu0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$671 end - attribute \src "libresoc.v:22280.3-22288.6" - process $proc$libresoc.v:22280$673 + attribute \src "libresoc.v:22328.3-22336.6" + process $proc$libresoc.v:22328$673 assign { } { } assign { } { } assign $0\src_l_s_src$next[3:0]$674 $1\src_l_s_src$next[3:0]$675 - attribute \src "libresoc.v:22281.5-22281.29" + attribute \src "libresoc.v:22329.5-22329.29" switch \initial - attribute \src "libresoc.v:22281.9-22281.17" + attribute \src "libresoc.v:22329.9-22329.17" case 1'1 case end @@ -34162,14 +34198,14 @@ module \alu0 sync always update \src_l_s_src$next $0\src_l_s_src$next[3:0]$674 end - attribute \src "libresoc.v:22289.3-22297.6" - process $proc$libresoc.v:22289$676 + attribute \src "libresoc.v:22337.3-22345.6" + process $proc$libresoc.v:22337$676 assign { } { } assign { } { } assign $0\src_l_r_src$next[3:0]$677 $1\src_l_r_src$next[3:0]$678 - attribute \src "libresoc.v:22290.5-22290.29" + attribute \src "libresoc.v:22338.5-22338.29" switch \initial - attribute \src "libresoc.v:22290.9-22290.17" + attribute \src "libresoc.v:22338.9-22338.17" case 1'1 case end @@ -34185,14 +34221,14 @@ module \alu0 sync always update \src_l_r_src$next $0\src_l_r_src$next[3:0]$677 end - attribute \src "libresoc.v:22298.3-22306.6" - process $proc$libresoc.v:22298$679 + attribute \src "libresoc.v:22346.3-22354.6" + process $proc$libresoc.v:22346$679 assign { } { } assign { } { } assign $0\req_l_s_req$next[4:0]$680 $1\req_l_s_req$next[4:0]$681 - attribute \src "libresoc.v:22299.5-22299.29" + attribute \src "libresoc.v:22347.5-22347.29" switch \initial - attribute \src "libresoc.v:22299.9-22299.17" + attribute \src "libresoc.v:22347.9-22347.17" case 1'1 case end @@ -34208,14 +34244,14 @@ module \alu0 sync always update \req_l_s_req$next $0\req_l_s_req$next[4:0]$680 end - attribute \src "libresoc.v:22307.3-22315.6" - process $proc$libresoc.v:22307$682 + attribute \src "libresoc.v:22355.3-22363.6" + process $proc$libresoc.v:22355$682 assign { } { } assign { } { } assign $0\req_l_r_req$next[4:0]$683 $1\req_l_r_req$next[4:0]$684 - attribute \src "libresoc.v:22308.5-22308.29" + attribute \src "libresoc.v:22356.5-22356.29" switch \initial - attribute \src "libresoc.v:22308.9-22308.17" + attribute \src "libresoc.v:22356.9-22356.17" case 1'1 case end @@ -34231,8 +34267,8 @@ module \alu0 sync always update \req_l_r_req$next $0\req_l_r_req$next[4:0]$683 end - attribute \src "libresoc.v:22316.3-22354.6" - process $proc$libresoc.v:22316$685 + attribute \src "libresoc.v:22364.3-22402.6" + process $proc$libresoc.v:22364$685 assign { } { } assign { } { } assign { } { } @@ -34293,9 +34329,9 @@ module \alu0 assign $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 assign $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 assign $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 - attribute \src "libresoc.v:22317.5-22317.29" + attribute \src "libresoc.v:22365.5-22365.29" switch \initial - attribute \src "libresoc.v:22317.9-22317.17" + attribute \src "libresoc.v:22365.9-22365.17" case 1'1 case end @@ -34386,8 +34422,8 @@ module \alu0 update \alu_alu0_alu_op__write_cr0$next $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 update \alu_alu0_alu_op__zero_a$next $0\alu_alu0_alu_op__zero_a$next[0:0]$703 end - attribute \src "libresoc.v:22355.3-22376.6" - process $proc$libresoc.v:22355$728 + attribute \src "libresoc.v:22403.3-22424.6" + process $proc$libresoc.v:22403$728 assign { } { } assign { } { } assign { } { } @@ -34397,9 +34433,9 @@ module \alu0 assign $0\data_r0__o$next[63:0]$729 $2\data_r0__o$next[63:0]$733 assign { } { } assign $0\data_r0__o_ok$next[0:0]$730 $3\data_r0__o_ok$next[0:0]$735 - attribute \src "libresoc.v:22356.5-22356.29" + attribute \src "libresoc.v:22404.5-22404.29" switch \initial - attribute \src "libresoc.v:22356.9-22356.17" + attribute \src "libresoc.v:22404.9-22404.17" case 1'1 case end @@ -34438,8 +34474,8 @@ module \alu0 update \data_r0__o$next $0\data_r0__o$next[63:0]$729 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$730 end - attribute \src "libresoc.v:22377.3-22398.6" - process $proc$libresoc.v:22377$736 + attribute \src "libresoc.v:22425.3-22446.6" + process $proc$libresoc.v:22425$736 assign { } { } assign { } { } assign { } { } @@ -34449,9 +34485,9 @@ module \alu0 assign $0\data_r1__cr_a$next[3:0]$737 $2\data_r1__cr_a$next[3:0]$741 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$738 $3\data_r1__cr_a_ok$next[0:0]$743 - attribute \src "libresoc.v:22378.5-22378.29" + attribute \src "libresoc.v:22426.5-22426.29" switch \initial - attribute \src "libresoc.v:22378.9-22378.17" + attribute \src "libresoc.v:22426.9-22426.17" case 1'1 case end @@ -34490,8 +34526,8 @@ module \alu0 update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$737 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$738 end - attribute \src "libresoc.v:22399.3-22420.6" - process $proc$libresoc.v:22399$744 + attribute \src "libresoc.v:22447.3-22468.6" + process $proc$libresoc.v:22447$744 assign { } { } assign { } { } assign { } { } @@ -34501,9 +34537,9 @@ module \alu0 assign $0\data_r2__xer_ca$next[1:0]$745 $2\data_r2__xer_ca$next[1:0]$749 assign { } { } assign $0\data_r2__xer_ca_ok$next[0:0]$746 $3\data_r2__xer_ca_ok$next[0:0]$751 - attribute \src "libresoc.v:22400.5-22400.29" + attribute \src "libresoc.v:22448.5-22448.29" switch \initial - attribute \src "libresoc.v:22400.9-22400.17" + attribute \src "libresoc.v:22448.9-22448.17" case 1'1 case end @@ -34542,8 +34578,8 @@ module \alu0 update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$745 update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$746 end - attribute \src "libresoc.v:22421.3-22442.6" - process $proc$libresoc.v:22421$752 + attribute \src "libresoc.v:22469.3-22490.6" + process $proc$libresoc.v:22469$752 assign { } { } assign { } { } assign { } { } @@ -34553,9 +34589,9 @@ module \alu0 assign $0\data_r3__xer_ov$next[1:0]$753 $2\data_r3__xer_ov$next[1:0]$757 assign { } { } assign $0\data_r3__xer_ov_ok$next[0:0]$754 $3\data_r3__xer_ov_ok$next[0:0]$759 - attribute \src "libresoc.v:22422.5-22422.29" + attribute \src "libresoc.v:22470.5-22470.29" switch \initial - attribute \src "libresoc.v:22422.9-22422.17" + attribute \src "libresoc.v:22470.9-22470.17" case 1'1 case end @@ -34594,8 +34630,8 @@ module \alu0 update \data_r3__xer_ov$next $0\data_r3__xer_ov$next[1:0]$753 update \data_r3__xer_ov_ok$next $0\data_r3__xer_ov_ok$next[0:0]$754 end - attribute \src "libresoc.v:22443.3-22464.6" - process $proc$libresoc.v:22443$760 + attribute \src "libresoc.v:22491.3-22512.6" + process $proc$libresoc.v:22491$760 assign { } { } assign { } { } assign { } { } @@ -34605,9 +34641,9 @@ module \alu0 assign $0\data_r4__xer_so$next[0:0]$761 $2\data_r4__xer_so$next[0:0]$765 assign { } { } assign $0\data_r4__xer_so_ok$next[0:0]$762 $3\data_r4__xer_so_ok$next[0:0]$767 - attribute \src "libresoc.v:22444.5-22444.29" + attribute \src "libresoc.v:22492.5-22492.29" switch \initial - attribute \src "libresoc.v:22444.9-22444.17" + attribute \src "libresoc.v:22492.9-22492.17" case 1'1 case end @@ -34646,14 +34682,14 @@ module \alu0 update \data_r4__xer_so$next $0\data_r4__xer_so$next[0:0]$761 update \data_r4__xer_so_ok$next $0\data_r4__xer_so_ok$next[0:0]$762 end - attribute \src "libresoc.v:22465.3-22474.6" - process $proc$libresoc.v:22465$768 + attribute \src "libresoc.v:22513.3-22522.6" + process $proc$libresoc.v:22513$768 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$769 $1\src_r0$next[63:0]$770 - attribute \src "libresoc.v:22466.5-22466.29" + attribute \src "libresoc.v:22514.5-22514.29" switch \initial - attribute \src "libresoc.v:22466.9-22466.17" + attribute \src "libresoc.v:22514.9-22514.17" case 1'1 case end @@ -34669,14 +34705,14 @@ module \alu0 sync always update \src_r0$next $0\src_r0$next[63:0]$769 end - attribute \src "libresoc.v:22475.3-22484.6" - process $proc$libresoc.v:22475$771 + attribute \src "libresoc.v:22523.3-22532.6" + process $proc$libresoc.v:22523$771 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$772 $1\src_r1$next[63:0]$773 - attribute \src "libresoc.v:22476.5-22476.29" + attribute \src "libresoc.v:22524.5-22524.29" switch \initial - attribute \src "libresoc.v:22476.9-22476.17" + attribute \src "libresoc.v:22524.9-22524.17" case 1'1 case end @@ -34692,14 +34728,14 @@ module \alu0 sync always update \src_r1$next $0\src_r1$next[63:0]$772 end - attribute \src "libresoc.v:22485.3-22494.6" - process $proc$libresoc.v:22485$774 + attribute \src "libresoc.v:22533.3-22542.6" + process $proc$libresoc.v:22533$774 assign { } { } assign { } { } assign $0\src_r2$next[0:0]$775 $1\src_r2$next[0:0]$776 - attribute \src "libresoc.v:22486.5-22486.29" + attribute \src "libresoc.v:22534.5-22534.29" switch \initial - attribute \src "libresoc.v:22486.9-22486.17" + attribute \src "libresoc.v:22534.9-22534.17" case 1'1 case end @@ -34715,14 +34751,14 @@ module \alu0 sync always update \src_r2$next $0\src_r2$next[0:0]$775 end - attribute \src "libresoc.v:22495.3-22504.6" - process $proc$libresoc.v:22495$777 + attribute \src "libresoc.v:22543.3-22552.6" + process $proc$libresoc.v:22543$777 assign { } { } assign { } { } assign $0\src_r3$next[1:0]$778 $1\src_r3$next[1:0]$779 - attribute \src "libresoc.v:22496.5-22496.29" + attribute \src "libresoc.v:22544.5-22544.29" switch \initial - attribute \src "libresoc.v:22496.9-22496.17" + attribute \src "libresoc.v:22544.9-22544.17" case 1'1 case end @@ -34738,14 +34774,14 @@ module \alu0 sync always update \src_r3$next $0\src_r3$next[1:0]$778 end - attribute \src "libresoc.v:22505.3-22513.6" - process $proc$libresoc.v:22505$780 + attribute \src "libresoc.v:22553.3-22561.6" + process $proc$libresoc.v:22553$780 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$781 $1\alui_l_r_alui$next[0:0]$782 - attribute \src "libresoc.v:22506.5-22506.29" + attribute \src "libresoc.v:22554.5-22554.29" switch \initial - attribute \src "libresoc.v:22506.9-22506.17" + attribute \src "libresoc.v:22554.9-22554.17" case 1'1 case end @@ -34761,14 +34797,14 @@ module \alu0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$781 end - attribute \src "libresoc.v:22514.3-22522.6" - process $proc$libresoc.v:22514$783 + attribute \src "libresoc.v:22562.3-22570.6" + process $proc$libresoc.v:22562$783 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$784 $1\alu_l_r_alu$next[0:0]$785 - attribute \src "libresoc.v:22515.5-22515.29" + attribute \src "libresoc.v:22563.5-22563.29" switch \initial - attribute \src "libresoc.v:22515.9-22515.17" + attribute \src "libresoc.v:22563.9-22563.17" case 1'1 case end @@ -34784,14 +34820,14 @@ module \alu0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$784 end - attribute \src "libresoc.v:22523.3-22532.6" - process $proc$libresoc.v:22523$786 + attribute \src "libresoc.v:22571.3-22580.6" + process $proc$libresoc.v:22571$786 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:22524.5-22524.29" + attribute \src "libresoc.v:22572.5-22572.29" switch \initial - attribute \src "libresoc.v:22524.9-22524.17" + attribute \src "libresoc.v:22572.9-22572.17" case 1'1 case end @@ -34807,14 +34843,14 @@ module \alu0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:22533.3-22542.6" - process $proc$libresoc.v:22533$787 + attribute \src "libresoc.v:22581.3-22590.6" + process $proc$libresoc.v:22581$787 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:22534.5-22534.29" + attribute \src "libresoc.v:22582.5-22582.29" switch \initial - attribute \src "libresoc.v:22534.9-22534.17" + attribute \src "libresoc.v:22582.9-22582.17" case 1'1 case end @@ -34830,14 +34866,14 @@ module \alu0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:22543.3-22552.6" - process $proc$libresoc.v:22543$788 + attribute \src "libresoc.v:22591.3-22600.6" + process $proc$libresoc.v:22591$788 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:22544.5-22544.29" + attribute \src "libresoc.v:22592.5-22592.29" switch \initial - attribute \src "libresoc.v:22544.9-22544.17" + attribute \src "libresoc.v:22592.9-22592.17" case 1'1 case end @@ -34853,14 +34889,14 @@ module \alu0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:22553.3-22562.6" - process $proc$libresoc.v:22553$789 + attribute \src "libresoc.v:22601.3-22610.6" + process $proc$libresoc.v:22601$789 assign { } { } assign { } { } assign $0\dest4_o[1:0] $1\dest4_o[1:0] - attribute \src "libresoc.v:22554.5-22554.29" + attribute \src "libresoc.v:22602.5-22602.29" switch \initial - attribute \src "libresoc.v:22554.9-22554.17" + attribute \src "libresoc.v:22602.9-22602.17" case 1'1 case end @@ -34876,14 +34912,14 @@ module \alu0 sync always update \dest4_o $0\dest4_o[1:0] end - attribute \src "libresoc.v:22563.3-22572.6" - process $proc$libresoc.v:22563$790 + attribute \src "libresoc.v:22611.3-22620.6" + process $proc$libresoc.v:22611$790 assign { } { } assign { } { } assign $0\dest5_o[0:0] $1\dest5_o[0:0] - attribute \src "libresoc.v:22564.5-22564.29" + attribute \src "libresoc.v:22612.5-22612.29" switch \initial - attribute \src "libresoc.v:22564.9-22564.17" + attribute \src "libresoc.v:22612.9-22612.17" case 1'1 case end @@ -34899,14 +34935,14 @@ module \alu0 sync always update \dest5_o $0\dest5_o[0:0] end - attribute \src "libresoc.v:22573.3-22581.6" - process $proc$libresoc.v:22573$791 + attribute \src "libresoc.v:22621.3-22629.6" + process $proc$libresoc.v:22621$791 assign { } { } assign { } { } assign $0\prev_wr_go$next[4:0]$792 $1\prev_wr_go$next[4:0]$793 - attribute \src "libresoc.v:22574.5-22574.29" + attribute \src "libresoc.v:22622.5-22622.29" switch \initial - attribute \src "libresoc.v:22574.9-22574.17" + attribute \src "libresoc.v:22622.9-22622.17" case 1'1 case end @@ -34922,73 +34958,73 @@ module \alu0 sync always update \prev_wr_go$next $0\prev_wr_go$next[4:0]$792 end - connect \$5 $reduce_and$libresoc.v:21967$540_Y - connect \$99 $and$libresoc.v:21968$541_Y - connect \$101 $and$libresoc.v:21969$542_Y - connect \$103 $and$libresoc.v:21970$543_Y - connect \$105 $not$libresoc.v:21971$544_Y - connect \$107 $not$libresoc.v:21972$545_Y - connect \$109 $and$libresoc.v:21973$546_Y - connect \$111 $not$libresoc.v:21974$547_Y - connect \$113 $and$libresoc.v:21975$548_Y - connect \$115 $and$libresoc.v:21976$549_Y - connect \$117 $and$libresoc.v:21977$550_Y - connect \$11 $and$libresoc.v:21978$551_Y - connect \$119 $and$libresoc.v:21979$552_Y - connect \$121 $and$libresoc.v:21980$553_Y - connect \$123 $and$libresoc.v:21981$554_Y - connect \$125 $and$libresoc.v:21982$555_Y - connect \$127 $and$libresoc.v:21983$556_Y - connect \$129 $and$libresoc.v:21984$557_Y - connect \$131 $and$libresoc.v:21985$558_Y - connect \$133 $and$libresoc.v:21986$559_Y - connect \$135 $and$libresoc.v:21987$560_Y - connect \$137 $and$libresoc.v:21988$561_Y - connect \$13 $not$libresoc.v:21989$562_Y - connect \$15 $and$libresoc.v:21990$563_Y - connect \$17 $not$libresoc.v:21991$564_Y - connect \$19 $and$libresoc.v:21992$565_Y - connect \$21 $and$libresoc.v:21993$566_Y - connect \$25 $not$libresoc.v:21994$567_Y - connect \$27 $and$libresoc.v:21995$568_Y - connect \$24 $reduce_or$libresoc.v:21996$569_Y - connect \$23 $not$libresoc.v:21997$570_Y - connect \$31 $and$libresoc.v:21998$571_Y - connect \$33 $reduce_or$libresoc.v:21999$572_Y - connect \$35 $reduce_or$libresoc.v:22000$573_Y - connect \$37 $or$libresoc.v:22001$574_Y - connect \$3 $and$libresoc.v:22002$575_Y - connect \$39 $not$libresoc.v:22003$576_Y - connect \$41 $and$libresoc.v:22004$577_Y - connect \$43 $and$libresoc.v:22005$578_Y - connect \$45 $eq$libresoc.v:22006$579_Y - connect \$47 $and$libresoc.v:22007$580_Y - connect \$49 $eq$libresoc.v:22008$581_Y - connect \$51 $and$libresoc.v:22009$582_Y - connect \$53 $and$libresoc.v:22010$583_Y - connect \$55 $and$libresoc.v:22011$584_Y - connect \$57 $or$libresoc.v:22012$585_Y - connect \$59 $or$libresoc.v:22013$586_Y - connect \$61 $or$libresoc.v:22014$587_Y - connect \$63 $or$libresoc.v:22015$588_Y - connect \$65 $and$libresoc.v:22016$589_Y - connect \$67 $and$libresoc.v:22017$590_Y - connect \$6 $not$libresoc.v:22018$591_Y - connect \$69 $or$libresoc.v:22019$592_Y - connect \$71 $and$libresoc.v:22020$593_Y - connect \$73 $and$libresoc.v:22021$594_Y - connect \$75 $and$libresoc.v:22022$595_Y - connect \$77 $and$libresoc.v:22023$596_Y - connect \$79 $and$libresoc.v:22024$597_Y - connect \$81 $ternary$libresoc.v:22025$598_Y - connect \$83 $ternary$libresoc.v:22026$599_Y - connect \$86 $ternary$libresoc.v:22027$600_Y - connect \$8 $or$libresoc.v:22028$601_Y - connect \$89 $ternary$libresoc.v:22029$602_Y - connect \$91 $ternary$libresoc.v:22030$603_Y - connect \$93 $ternary$libresoc.v:22031$604_Y - connect \$95 $ternary$libresoc.v:22032$605_Y - connect \$97 $ternary$libresoc.v:22033$606_Y + connect \$5 $reduce_and$libresoc.v:22015$540_Y + connect \$99 $and$libresoc.v:22016$541_Y + connect \$101 $and$libresoc.v:22017$542_Y + connect \$103 $and$libresoc.v:22018$543_Y + connect \$105 $not$libresoc.v:22019$544_Y + connect \$107 $not$libresoc.v:22020$545_Y + connect \$109 $and$libresoc.v:22021$546_Y + connect \$111 $not$libresoc.v:22022$547_Y + connect \$113 $and$libresoc.v:22023$548_Y + connect \$115 $and$libresoc.v:22024$549_Y + connect \$117 $and$libresoc.v:22025$550_Y + connect \$11 $and$libresoc.v:22026$551_Y + connect \$119 $and$libresoc.v:22027$552_Y + connect \$121 $and$libresoc.v:22028$553_Y + connect \$123 $and$libresoc.v:22029$554_Y + connect \$125 $and$libresoc.v:22030$555_Y + connect \$127 $and$libresoc.v:22031$556_Y + connect \$129 $and$libresoc.v:22032$557_Y + connect \$131 $and$libresoc.v:22033$558_Y + connect \$133 $and$libresoc.v:22034$559_Y + connect \$135 $and$libresoc.v:22035$560_Y + connect \$137 $and$libresoc.v:22036$561_Y + connect \$13 $not$libresoc.v:22037$562_Y + connect \$15 $and$libresoc.v:22038$563_Y + connect \$17 $not$libresoc.v:22039$564_Y + connect \$19 $and$libresoc.v:22040$565_Y + connect \$21 $and$libresoc.v:22041$566_Y + connect \$25 $not$libresoc.v:22042$567_Y + connect \$27 $and$libresoc.v:22043$568_Y + connect \$24 $reduce_or$libresoc.v:22044$569_Y + connect \$23 $not$libresoc.v:22045$570_Y + connect \$31 $and$libresoc.v:22046$571_Y + connect \$33 $reduce_or$libresoc.v:22047$572_Y + connect \$35 $reduce_or$libresoc.v:22048$573_Y + connect \$37 $or$libresoc.v:22049$574_Y + connect \$3 $and$libresoc.v:22050$575_Y + connect \$39 $not$libresoc.v:22051$576_Y + connect \$41 $and$libresoc.v:22052$577_Y + connect \$43 $and$libresoc.v:22053$578_Y + connect \$45 $eq$libresoc.v:22054$579_Y + connect \$47 $and$libresoc.v:22055$580_Y + connect \$49 $eq$libresoc.v:22056$581_Y + connect \$51 $and$libresoc.v:22057$582_Y + connect \$53 $and$libresoc.v:22058$583_Y + connect \$55 $and$libresoc.v:22059$584_Y + connect \$57 $or$libresoc.v:22060$585_Y + connect \$59 $or$libresoc.v:22061$586_Y + connect \$61 $or$libresoc.v:22062$587_Y + connect \$63 $or$libresoc.v:22063$588_Y + connect \$65 $and$libresoc.v:22064$589_Y + connect \$67 $and$libresoc.v:22065$590_Y + connect \$6 $not$libresoc.v:22066$591_Y + connect \$69 $or$libresoc.v:22067$592_Y + connect \$71 $and$libresoc.v:22068$593_Y + connect \$73 $and$libresoc.v:22069$594_Y + connect \$75 $and$libresoc.v:22070$595_Y + connect \$77 $and$libresoc.v:22071$596_Y + connect \$79 $and$libresoc.v:22072$597_Y + connect \$81 $ternary$libresoc.v:22073$598_Y + connect \$83 $ternary$libresoc.v:22074$599_Y + connect \$86 $ternary$libresoc.v:22075$600_Y + connect \$8 $or$libresoc.v:22076$601_Y + connect \$89 $ternary$libresoc.v:22077$602_Y + connect \$91 $ternary$libresoc.v:22078$603_Y + connect \$93 $ternary$libresoc.v:22079$604_Y + connect \$95 $ternary$libresoc.v:22080$605_Y + connect \$97 $ternary$libresoc.v:22081$606_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$127 @@ -35023,7 +35059,7 @@ module \alu0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:22619.1-23697.10" +attribute \src "libresoc.v:22667.1-23745.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0" attribute \generator "nMigen" @@ -35288,13 +35324,13 @@ module \alu_alu0 wire input 18 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 28 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid @@ -35304,9 +35340,9 @@ module \alu_alu0 wire input 8 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 7 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 27 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 37 \p_ready_o @@ -35572,9 +35608,9 @@ module \alu_alu0 wire \pipe1_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__zero_a$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe1_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe1_muxid @@ -35584,9 +35620,9 @@ module \alu_alu0 wire \pipe1_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe1_p_ready_o @@ -35596,21 +35632,21 @@ module \alu_alu0 wire width 64 \pipe1_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe1_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \pipe1_xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe1_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe1_xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe2_alu_op__data_len @@ -35872,13 +35908,13 @@ module \alu_alu0 wire \pipe2_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__zero_a$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe2_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe2_cr_a$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_cr_a_ok$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe2_muxid @@ -35888,76 +35924,76 @@ module \alu_alu0 wire \pipe2_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_o_ok$44 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe2_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe2_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe2_xer_ca$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_ca_ok$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe2_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe2_xer_ov$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_ov_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_so$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_so_ok$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 32 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 33 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 29 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 35 \xer_ca$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 30 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 31 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 34 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 6 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:23536.5-23539.4" + attribute \src "libresoc.v:23584.5-23587.4" cell \n \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:23540.5-23543.4" + attribute \src "libresoc.v:23588.5-23591.4" cell \p \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:23544.9-23603.4" + attribute \src "libresoc.v:23592.9-23651.4" cell \pipe1 \pipe1 connect \alu_op__data_len \pipe1_alu_op__data_len connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 @@ -36019,7 +36055,7 @@ module \alu_alu0 connect \xer_so_ok \pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:23604.9-23669.4" + attribute \src "libresoc.v:23652.9-23717.4" cell \pipe2 \pipe2 connect \alu_op__data_len \pipe2_alu_op__data_len connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 @@ -36114,7 +36150,7 @@ module \alu_alu0 connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:23701.1-24248.10" +attribute \src "libresoc.v:23749.1-24296.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0" attribute \generator "nMigen" @@ -36331,23 +36367,23 @@ module \alu_branch0 wire input 13 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 20 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 15 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 18 \fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 16 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \fast2$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid @@ -36357,9 +36393,9 @@ module \alu_branch0 wire input 6 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 17 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \nia_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 22 \p_ready_o @@ -36581,15 +36617,15 @@ module \alu_branch0 wire width 4 \pipe_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_fast1$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_fast2$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid @@ -36599,28 +36635,28 @@ module \alu_branch0 wire \pipe_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_nia_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_p_valid_i attribute \module_not_derived 1 - attribute \src "libresoc.v:24190.10-24193.4" + attribute \src "libresoc.v:24238.10-24241.4" cell \n$18 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:24194.10-24197.4" + attribute \src "libresoc.v:24242.10-24245.4" cell \p$17 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:24198.13-24232.4" + attribute \src "libresoc.v:24246.13-24280.4" cell \pipe$19 \pipe connect \br_op__cia \pipe_br_op__cia connect \br_op__cia$2 \pipe_br_op__cia$4 @@ -36672,20 +36708,20 @@ module \alu_branch0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:24252.1-24767.10" +attribute \src "libresoc.v:24300.1-24815.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0" attribute \generator "nMigen" module \alu_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 12 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 16 \cr_a$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 17 \cr_b @@ -36883,11 +36919,11 @@ module \alu_cr0 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \cr_op__insn_type$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 output 11 \full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 input 15 \full_cr$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \full_cr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid @@ -36897,9 +36933,9 @@ module \alu_cr0 wire input 6 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 10 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 20 \p_ready_o @@ -36907,9 +36943,9 @@ module \alu_cr0 wire input 19 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \pipe_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe_cr_a$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \pipe_cr_b @@ -37109,9 +37145,9 @@ module \alu_cr0 wire width 7 \pipe_cr_op__insn_type$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 \pipe_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 \pipe_full_cr$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_full_cr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid @@ -37121,9 +37157,9 @@ module \alu_cr0 wire \pipe_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_p_ready_o @@ -37138,19 +37174,19 @@ module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 14 \rb attribute \module_not_derived 1 - attribute \src "libresoc.v:24713.9-24716.4" + attribute \src "libresoc.v:24761.9-24764.4" cell \n$6 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:24717.9-24720.4" + attribute \src "libresoc.v:24765.9-24768.4" cell \p$5 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:24721.8-24748.4" + attribute \src "libresoc.v:24769.8-24796.4" cell \pipe \pipe connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -37198,18 +37234,18 @@ module \alu_cr0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:24771.1-26236.10" +attribute \src "libresoc.v:24819.1-26284.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0" attribute \generator "nMigen" module \alu_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 35 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 27 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 24 \logical_op__data_len @@ -37479,17 +37515,17 @@ module \alu_div0 wire input 7 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 6 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 26 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 34 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 33 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe_end_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_end_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \pipe_end_div_by_zero @@ -37769,9 +37805,9 @@ module \alu_div0 wire \pipe_end_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_end_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_end_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_end_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_end_p_ready_o @@ -37785,15 +37821,15 @@ module \alu_div0 wire width 64 \pipe_end_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" wire width 192 \pipe_end_remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe_end_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_end_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe_end_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_end_xer_so$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_end_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \pipe_middle_0_div_by_zero @@ -38413,30 +38449,30 @@ module \alu_div0 wire width 64 input 30 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 31 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 28 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 32 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:25992.10-25995.4" + attribute \src "libresoc.v:26040.10-26043.4" cell \n$75 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:25996.10-25999.4" + attribute \src "libresoc.v:26044.10-26047.4" cell \p$74 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:26000.12-26063.4" + attribute \src "libresoc.v:26048.12-26111.4" cell \pipe_end \pipe_end connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38502,7 +38538,7 @@ module \alu_div0 connect \xer_so_ok \pipe_end_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:26064.17-26130.4" + attribute \src "libresoc.v:26112.17-26178.4" cell \pipe_middle_0 \pipe_middle_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38571,7 +38607,7 @@ module \alu_div0 connect \xer_so$22 \pipe_middle_0_xer_so$45 end attribute \module_not_derived 1 - attribute \src "libresoc.v:26131.14-26190.4" + attribute \src "libresoc.v:26179.14-26238.4" cell \pipe_start \pipe_start connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38678,37 +38714,37 @@ module \alu_div0 connect \pipe_start_n_ready_i \pipe_middle_0_p_ready_o connect \pipe_middle_0_p_valid_i \pipe_start_n_valid_o end -attribute \src "libresoc.v:26240.1-26298.10" +attribute \src "libresoc.v:26288.1-26346.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_l" attribute \generator "nMigen" module \alu_l - attribute \src "libresoc.v:26241.7-26241.20" + attribute \src "libresoc.v:26289.7-26289.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26286.3-26294.6" + attribute \src "libresoc.v:26334.3-26342.6" wire $0\q_int$next[0:0]$852 - attribute \src "libresoc.v:26284.3-26285.27" + attribute \src "libresoc.v:26332.3-26333.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26286.3-26294.6" + attribute \src "libresoc.v:26334.3-26342.6" wire $1\q_int$next[0:0]$853 - attribute \src "libresoc.v:26265.7-26265.19" + attribute \src "libresoc.v:26313.7-26313.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26276.17-26276.96" - wire $and$libresoc.v:26276$842_Y - attribute \src "libresoc.v:26281.17-26281.96" - wire $and$libresoc.v:26281$847_Y - attribute \src "libresoc.v:26278.18-26278.93" - wire $not$libresoc.v:26278$844_Y - attribute \src "libresoc.v:26280.17-26280.92" - wire $not$libresoc.v:26280$846_Y - attribute \src "libresoc.v:26283.17-26283.92" - wire $not$libresoc.v:26283$849_Y - attribute \src "libresoc.v:26277.18-26277.98" - wire $or$libresoc.v:26277$843_Y - attribute \src "libresoc.v:26279.18-26279.99" - wire $or$libresoc.v:26279$845_Y - attribute \src "libresoc.v:26282.17-26282.97" - wire $or$libresoc.v:26282$848_Y + attribute \src "libresoc.v:26324.17-26324.96" + wire $and$libresoc.v:26324$842_Y + attribute \src "libresoc.v:26329.17-26329.96" + wire $and$libresoc.v:26329$847_Y + attribute \src "libresoc.v:26326.18-26326.93" + wire $not$libresoc.v:26326$844_Y + attribute \src "libresoc.v:26328.17-26328.92" + wire $not$libresoc.v:26328$846_Y + attribute \src "libresoc.v:26331.17-26331.92" + wire $not$libresoc.v:26331$849_Y + attribute \src "libresoc.v:26325.18-26325.98" + wire $or$libresoc.v:26325$843_Y + attribute \src "libresoc.v:26327.18-26327.99" + wire $or$libresoc.v:26327$845_Y + attribute \src "libresoc.v:26330.17-26330.97" + wire $or$libresoc.v:26330$848_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -38725,11 +38761,11 @@ module \alu_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:26241.7-26241.15" + attribute \src "libresoc.v:26289.7-26289.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -38746,7 +38782,7 @@ module \alu_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26276$842 + cell $and $and$libresoc.v:26324$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38754,10 +38790,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26276$842_Y + connect \Y $and$libresoc.v:26324$842_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26281$847 + cell $and $and$libresoc.v:26329$847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38765,34 +38801,34 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26281$847_Y + connect \Y $and$libresoc.v:26329$847_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26278$844 + cell $not $not$libresoc.v:26326$844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26278$844_Y + connect \Y $not$libresoc.v:26326$844_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26280$846 + cell $not $not$libresoc.v:26328$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26280$846_Y + connect \Y $not$libresoc.v:26328$846_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26283$849 + cell $not $not$libresoc.v:26331$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26283$849_Y + connect \Y $not$libresoc.v:26331$849_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26277$843 + cell $or $or$libresoc.v:26325$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38800,10 +38836,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26277$843_Y + connect \Y $or$libresoc.v:26325$843_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26279$845 + cell $or $or$libresoc.v:26327$845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38811,10 +38847,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26279$845_Y + connect \Y $or$libresoc.v:26327$845_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26282$848 + cell $or $or$libresoc.v:26330$848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38822,39 +38858,39 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26282$848_Y + connect \Y $or$libresoc.v:26330$848_Y end - attribute \src "libresoc.v:26241.7-26241.20" - process $proc$libresoc.v:26241$854 + attribute \src "libresoc.v:26289.7-26289.20" + process $proc$libresoc.v:26289$854 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26265.7-26265.19" - process $proc$libresoc.v:26265$855 + attribute \src "libresoc.v:26313.7-26313.19" + process $proc$libresoc.v:26313$855 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26284.3-26285.27" - process $proc$libresoc.v:26284$850 + attribute \src "libresoc.v:26332.3-26333.27" + process $proc$libresoc.v:26332$850 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26286.3-26294.6" - process $proc$libresoc.v:26286$851 + attribute \src "libresoc.v:26334.3-26342.6" + process $proc$libresoc.v:26334$851 assign { } { } assign { } { } assign $0\q_int$next[0:0]$852 $1\q_int$next[0:0]$853 - attribute \src "libresoc.v:26287.5-26287.29" + attribute \src "libresoc.v:26335.5-26335.29" switch \initial - attribute \src "libresoc.v:26287.9-26287.17" + attribute \src "libresoc.v:26335.9-26335.17" case 1'1 case end @@ -38870,49 +38906,49 @@ module \alu_l sync always update \q_int$next $0\q_int$next[0:0]$852 end - connect \$9 $and$libresoc.v:26276$842_Y - connect \$11 $or$libresoc.v:26277$843_Y - connect \$13 $not$libresoc.v:26278$844_Y - connect \$15 $or$libresoc.v:26279$845_Y - connect \$1 $not$libresoc.v:26280$846_Y - connect \$3 $and$libresoc.v:26281$847_Y - connect \$5 $or$libresoc.v:26282$848_Y - connect \$7 $not$libresoc.v:26283$849_Y + connect \$9 $and$libresoc.v:26324$842_Y + connect \$11 $or$libresoc.v:26325$843_Y + connect \$13 $not$libresoc.v:26326$844_Y + connect \$15 $or$libresoc.v:26327$845_Y + connect \$1 $not$libresoc.v:26328$846_Y + connect \$3 $and$libresoc.v:26329$847_Y + connect \$5 $or$libresoc.v:26330$848_Y + connect \$7 $not$libresoc.v:26331$849_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26302.1-26360.10" +attribute \src "libresoc.v:26350.1-26408.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_l" attribute \generator "nMigen" module \alu_l$107 - attribute \src "libresoc.v:26303.7-26303.20" + attribute \src "libresoc.v:26351.7-26351.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26348.3-26356.6" + attribute \src "libresoc.v:26396.3-26404.6" wire $0\q_int$next[0:0]$866 - attribute \src "libresoc.v:26346.3-26347.27" + attribute \src "libresoc.v:26394.3-26395.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26348.3-26356.6" + attribute \src "libresoc.v:26396.3-26404.6" wire $1\q_int$next[0:0]$867 - attribute \src "libresoc.v:26327.7-26327.19" + attribute \src "libresoc.v:26375.7-26375.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26338.17-26338.96" - wire $and$libresoc.v:26338$856_Y - attribute \src "libresoc.v:26343.17-26343.96" - wire $and$libresoc.v:26343$861_Y - attribute \src "libresoc.v:26340.18-26340.93" - wire $not$libresoc.v:26340$858_Y - attribute \src "libresoc.v:26342.17-26342.92" - wire $not$libresoc.v:26342$860_Y - attribute \src "libresoc.v:26345.17-26345.92" - wire $not$libresoc.v:26345$863_Y - attribute \src "libresoc.v:26339.18-26339.98" - wire $or$libresoc.v:26339$857_Y - attribute \src "libresoc.v:26341.18-26341.99" - wire $or$libresoc.v:26341$859_Y - attribute \src "libresoc.v:26344.17-26344.97" - wire $or$libresoc.v:26344$862_Y + attribute \src "libresoc.v:26386.17-26386.96" + wire $and$libresoc.v:26386$856_Y + attribute \src "libresoc.v:26391.17-26391.96" + wire $and$libresoc.v:26391$861_Y + attribute \src "libresoc.v:26388.18-26388.93" + wire $not$libresoc.v:26388$858_Y + attribute \src "libresoc.v:26390.17-26390.92" + wire $not$libresoc.v:26390$860_Y + attribute \src "libresoc.v:26393.17-26393.92" + wire $not$libresoc.v:26393$863_Y + attribute \src "libresoc.v:26387.18-26387.98" + wire $or$libresoc.v:26387$857_Y + attribute \src "libresoc.v:26389.18-26389.99" + wire $or$libresoc.v:26389$859_Y + attribute \src "libresoc.v:26392.17-26392.97" + wire $or$libresoc.v:26392$862_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -38929,11 +38965,11 @@ module \alu_l$107 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:26303.7-26303.15" + attribute \src "libresoc.v:26351.7-26351.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -38950,7 +38986,7 @@ module \alu_l$107 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26338$856 + cell $and $and$libresoc.v:26386$856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38958,10 +38994,10 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26338$856_Y + connect \Y $and$libresoc.v:26386$856_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26343$861 + cell $and $and$libresoc.v:26391$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38969,34 +39005,34 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26343$861_Y + connect \Y $and$libresoc.v:26391$861_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26340$858 + cell $not $not$libresoc.v:26388$858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26340$858_Y + connect \Y $not$libresoc.v:26388$858_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26342$860 + cell $not $not$libresoc.v:26390$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26342$860_Y + connect \Y $not$libresoc.v:26390$860_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26345$863 + cell $not $not$libresoc.v:26393$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26345$863_Y + connect \Y $not$libresoc.v:26393$863_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26339$857 + cell $or $or$libresoc.v:26387$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39004,10 +39040,10 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26339$857_Y + connect \Y $or$libresoc.v:26387$857_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26341$859 + cell $or $or$libresoc.v:26389$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39015,10 +39051,10 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26341$859_Y + connect \Y $or$libresoc.v:26389$859_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26344$862 + cell $or $or$libresoc.v:26392$862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39026,39 +39062,39 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26344$862_Y + connect \Y $or$libresoc.v:26392$862_Y end - attribute \src "libresoc.v:26303.7-26303.20" - process $proc$libresoc.v:26303$868 + attribute \src "libresoc.v:26351.7-26351.20" + process $proc$libresoc.v:26351$868 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26327.7-26327.19" - process $proc$libresoc.v:26327$869 + attribute \src "libresoc.v:26375.7-26375.19" + process $proc$libresoc.v:26375$869 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26346.3-26347.27" - process $proc$libresoc.v:26346$864 + attribute \src "libresoc.v:26394.3-26395.27" + process $proc$libresoc.v:26394$864 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26348.3-26356.6" - process $proc$libresoc.v:26348$865 + attribute \src "libresoc.v:26396.3-26404.6" + process $proc$libresoc.v:26396$865 assign { } { } assign { } { } assign $0\q_int$next[0:0]$866 $1\q_int$next[0:0]$867 - attribute \src "libresoc.v:26349.5-26349.29" + attribute \src "libresoc.v:26397.5-26397.29" switch \initial - attribute \src "libresoc.v:26349.9-26349.17" + attribute \src "libresoc.v:26397.9-26397.17" case 1'1 case end @@ -39074,49 +39110,49 @@ module \alu_l$107 sync always update \q_int$next $0\q_int$next[0:0]$866 end - connect \$9 $and$libresoc.v:26338$856_Y - connect \$11 $or$libresoc.v:26339$857_Y - connect \$13 $not$libresoc.v:26340$858_Y - connect \$15 $or$libresoc.v:26341$859_Y - connect \$1 $not$libresoc.v:26342$860_Y - connect \$3 $and$libresoc.v:26343$861_Y - connect \$5 $or$libresoc.v:26344$862_Y - connect \$7 $not$libresoc.v:26345$863_Y + connect \$9 $and$libresoc.v:26386$856_Y + connect \$11 $or$libresoc.v:26387$857_Y + connect \$13 $not$libresoc.v:26388$858_Y + connect \$15 $or$libresoc.v:26389$859_Y + connect \$1 $not$libresoc.v:26390$860_Y + connect \$3 $and$libresoc.v:26391$861_Y + connect \$5 $or$libresoc.v:26392$862_Y + connect \$7 $not$libresoc.v:26393$863_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26364.1-26422.10" +attribute \src "libresoc.v:26412.1-26470.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_l" attribute \generator "nMigen" module \alu_l$125 - attribute \src "libresoc.v:26365.7-26365.20" + attribute \src "libresoc.v:26413.7-26413.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26410.3-26418.6" + attribute \src "libresoc.v:26458.3-26466.6" wire $0\q_int$next[0:0]$880 - attribute \src "libresoc.v:26408.3-26409.27" + attribute \src "libresoc.v:26456.3-26457.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26410.3-26418.6" + attribute \src "libresoc.v:26458.3-26466.6" wire $1\q_int$next[0:0]$881 - attribute \src "libresoc.v:26389.7-26389.19" + attribute \src "libresoc.v:26437.7-26437.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26400.17-26400.96" - wire $and$libresoc.v:26400$870_Y - attribute \src "libresoc.v:26405.17-26405.96" - wire $and$libresoc.v:26405$875_Y - attribute \src "libresoc.v:26402.18-26402.93" - wire $not$libresoc.v:26402$872_Y - attribute \src "libresoc.v:26404.17-26404.92" - wire $not$libresoc.v:26404$874_Y - attribute \src "libresoc.v:26407.17-26407.92" - wire $not$libresoc.v:26407$877_Y - attribute \src "libresoc.v:26401.18-26401.98" - wire $or$libresoc.v:26401$871_Y - attribute \src "libresoc.v:26403.18-26403.99" - wire $or$libresoc.v:26403$873_Y - attribute \src "libresoc.v:26406.17-26406.97" - wire $or$libresoc.v:26406$876_Y + attribute \src "libresoc.v:26448.17-26448.96" + wire $and$libresoc.v:26448$870_Y + attribute \src "libresoc.v:26453.17-26453.96" + wire $and$libresoc.v:26453$875_Y + attribute \src "libresoc.v:26450.18-26450.93" + wire $not$libresoc.v:26450$872_Y + attribute \src "libresoc.v:26452.17-26452.92" + wire $not$libresoc.v:26452$874_Y + attribute \src "libresoc.v:26455.17-26455.92" + wire $not$libresoc.v:26455$877_Y + attribute \src "libresoc.v:26449.18-26449.98" + wire $or$libresoc.v:26449$871_Y + attribute \src "libresoc.v:26451.18-26451.99" + wire $or$libresoc.v:26451$873_Y + attribute \src "libresoc.v:26454.17-26454.97" + wire $or$libresoc.v:26454$876_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39133,11 +39169,11 @@ module \alu_l$125 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:26365.7-26365.15" + attribute \src "libresoc.v:26413.7-26413.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -39154,7 +39190,7 @@ module \alu_l$125 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26400$870 + cell $and $and$libresoc.v:26448$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39162,10 +39198,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26400$870_Y + connect \Y $and$libresoc.v:26448$870_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26405$875 + cell $and $and$libresoc.v:26453$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39173,34 +39209,34 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26405$875_Y + connect \Y $and$libresoc.v:26453$875_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26402$872 + cell $not $not$libresoc.v:26450$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26402$872_Y + connect \Y $not$libresoc.v:26450$872_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26404$874 + cell $not $not$libresoc.v:26452$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26404$874_Y + connect \Y $not$libresoc.v:26452$874_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26407$877 + cell $not $not$libresoc.v:26455$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26407$877_Y + connect \Y $not$libresoc.v:26455$877_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26401$871 + cell $or $or$libresoc.v:26449$871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39208,10 +39244,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26401$871_Y + connect \Y $or$libresoc.v:26449$871_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26403$873 + cell $or $or$libresoc.v:26451$873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39219,10 +39255,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26403$873_Y + connect \Y $or$libresoc.v:26451$873_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26406$876 + cell $or $or$libresoc.v:26454$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39230,39 +39266,39 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26406$876_Y + connect \Y $or$libresoc.v:26454$876_Y end - attribute \src "libresoc.v:26365.7-26365.20" - process $proc$libresoc.v:26365$882 + attribute \src "libresoc.v:26413.7-26413.20" + process $proc$libresoc.v:26413$882 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26389.7-26389.19" - process $proc$libresoc.v:26389$883 + attribute \src "libresoc.v:26437.7-26437.19" + process $proc$libresoc.v:26437$883 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26408.3-26409.27" - process $proc$libresoc.v:26408$878 + attribute \src "libresoc.v:26456.3-26457.27" + process $proc$libresoc.v:26456$878 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26410.3-26418.6" - process $proc$libresoc.v:26410$879 + attribute \src "libresoc.v:26458.3-26466.6" + process $proc$libresoc.v:26458$879 assign { } { } assign { } { } assign $0\q_int$next[0:0]$880 $1\q_int$next[0:0]$881 - attribute \src "libresoc.v:26411.5-26411.29" + attribute \src "libresoc.v:26459.5-26459.29" switch \initial - attribute \src "libresoc.v:26411.9-26411.17" + attribute \src "libresoc.v:26459.9-26459.17" case 1'1 case end @@ -39278,49 +39314,49 @@ module \alu_l$125 sync always update \q_int$next $0\q_int$next[0:0]$880 end - connect \$9 $and$libresoc.v:26400$870_Y - connect \$11 $or$libresoc.v:26401$871_Y - connect \$13 $not$libresoc.v:26402$872_Y - connect \$15 $or$libresoc.v:26403$873_Y - connect \$1 $not$libresoc.v:26404$874_Y - connect \$3 $and$libresoc.v:26405$875_Y - connect \$5 $or$libresoc.v:26406$876_Y - connect \$7 $not$libresoc.v:26407$877_Y + connect \$9 $and$libresoc.v:26448$870_Y + connect \$11 $or$libresoc.v:26449$871_Y + connect \$13 $not$libresoc.v:26450$872_Y + connect \$15 $or$libresoc.v:26451$873_Y + connect \$1 $not$libresoc.v:26452$874_Y + connect \$3 $and$libresoc.v:26453$875_Y + connect \$5 $or$libresoc.v:26454$876_Y + connect \$7 $not$libresoc.v:26455$877_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26426.1-26484.10" +attribute \src "libresoc.v:26474.1-26532.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.alu_l" attribute \generator "nMigen" module \alu_l$128 - attribute \src "libresoc.v:26427.7-26427.20" + attribute \src "libresoc.v:26475.7-26475.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26472.3-26480.6" + attribute \src "libresoc.v:26520.3-26528.6" wire $0\q_int$next[0:0]$894 - attribute \src "libresoc.v:26470.3-26471.27" + attribute \src "libresoc.v:26518.3-26519.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26472.3-26480.6" + attribute \src "libresoc.v:26520.3-26528.6" wire $1\q_int$next[0:0]$895 - attribute \src "libresoc.v:26451.7-26451.19" + attribute \src "libresoc.v:26499.7-26499.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26462.17-26462.96" - wire $and$libresoc.v:26462$884_Y - attribute \src "libresoc.v:26467.17-26467.96" - wire $and$libresoc.v:26467$889_Y - attribute \src "libresoc.v:26464.18-26464.93" - wire $not$libresoc.v:26464$886_Y - attribute \src "libresoc.v:26466.17-26466.92" - wire $not$libresoc.v:26466$888_Y - attribute \src "libresoc.v:26469.17-26469.92" - wire $not$libresoc.v:26469$891_Y - attribute \src "libresoc.v:26463.18-26463.98" - wire $or$libresoc.v:26463$885_Y - attribute \src "libresoc.v:26465.18-26465.99" - wire $or$libresoc.v:26465$887_Y - attribute \src "libresoc.v:26468.17-26468.97" - wire $or$libresoc.v:26468$890_Y + attribute \src "libresoc.v:26510.17-26510.96" + wire $and$libresoc.v:26510$884_Y + attribute \src "libresoc.v:26515.17-26515.96" + wire $and$libresoc.v:26515$889_Y + attribute \src "libresoc.v:26512.18-26512.93" + wire $not$libresoc.v:26512$886_Y + attribute \src "libresoc.v:26514.17-26514.92" + wire $not$libresoc.v:26514$888_Y + attribute \src "libresoc.v:26517.17-26517.92" + wire $not$libresoc.v:26517$891_Y + attribute \src "libresoc.v:26511.18-26511.98" + wire $or$libresoc.v:26511$885_Y + attribute \src "libresoc.v:26513.18-26513.99" + wire $or$libresoc.v:26513$887_Y + attribute \src "libresoc.v:26516.17-26516.97" + wire $or$libresoc.v:26516$890_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39337,11 +39373,11 @@ module \alu_l$128 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:26427.7-26427.15" + attribute \src "libresoc.v:26475.7-26475.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_alu @@ -39358,7 +39394,7 @@ module \alu_l$128 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26462$884 + cell $and $and$libresoc.v:26510$884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39366,10 +39402,10 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26462$884_Y + connect \Y $and$libresoc.v:26510$884_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26467$889 + cell $and $and$libresoc.v:26515$889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39377,34 +39413,34 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26467$889_Y + connect \Y $and$libresoc.v:26515$889_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26464$886 + cell $not $not$libresoc.v:26512$886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26464$886_Y + connect \Y $not$libresoc.v:26512$886_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26466$888 + cell $not $not$libresoc.v:26514$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26466$888_Y + connect \Y $not$libresoc.v:26514$888_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26469$891 + cell $not $not$libresoc.v:26517$891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26469$891_Y + connect \Y $not$libresoc.v:26517$891_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26463$885 + cell $or $or$libresoc.v:26511$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39412,10 +39448,10 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26463$885_Y + connect \Y $or$libresoc.v:26511$885_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26465$887 + cell $or $or$libresoc.v:26513$887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39423,10 +39459,10 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26465$887_Y + connect \Y $or$libresoc.v:26513$887_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26468$890 + cell $or $or$libresoc.v:26516$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39434,39 +39470,39 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26468$890_Y + connect \Y $or$libresoc.v:26516$890_Y end - attribute \src "libresoc.v:26427.7-26427.20" - process $proc$libresoc.v:26427$896 + attribute \src "libresoc.v:26475.7-26475.20" + process $proc$libresoc.v:26475$896 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26451.7-26451.19" - process $proc$libresoc.v:26451$897 + attribute \src "libresoc.v:26499.7-26499.19" + process $proc$libresoc.v:26499$897 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26470.3-26471.27" - process $proc$libresoc.v:26470$892 + attribute \src "libresoc.v:26518.3-26519.27" + process $proc$libresoc.v:26518$892 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26472.3-26480.6" - process $proc$libresoc.v:26472$893 + attribute \src "libresoc.v:26520.3-26528.6" + process $proc$libresoc.v:26520$893 assign { } { } assign { } { } assign $0\q_int$next[0:0]$894 $1\q_int$next[0:0]$895 - attribute \src "libresoc.v:26473.5-26473.29" + attribute \src "libresoc.v:26521.5-26521.29" switch \initial - attribute \src "libresoc.v:26473.9-26473.17" + attribute \src "libresoc.v:26521.9-26521.17" case 1'1 case end @@ -39482,49 +39518,49 @@ module \alu_l$128 sync always update \q_int$next $0\q_int$next[0:0]$894 end - connect \$9 $and$libresoc.v:26462$884_Y - connect \$11 $or$libresoc.v:26463$885_Y - connect \$13 $not$libresoc.v:26464$886_Y - connect \$15 $or$libresoc.v:26465$887_Y - connect \$1 $not$libresoc.v:26466$888_Y - connect \$3 $and$libresoc.v:26467$889_Y - connect \$5 $or$libresoc.v:26468$890_Y - connect \$7 $not$libresoc.v:26469$891_Y + connect \$9 $and$libresoc.v:26510$884_Y + connect \$11 $or$libresoc.v:26511$885_Y + connect \$13 $not$libresoc.v:26512$886_Y + connect \$15 $or$libresoc.v:26513$887_Y + connect \$1 $not$libresoc.v:26514$888_Y + connect \$3 $and$libresoc.v:26515$889_Y + connect \$5 $or$libresoc.v:26516$890_Y + connect \$7 $not$libresoc.v:26517$891_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26488.1-26546.10" +attribute \src "libresoc.v:26536.1-26594.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_l" attribute \generator "nMigen" module \alu_l$16 - attribute \src "libresoc.v:26489.7-26489.20" + attribute \src "libresoc.v:26537.7-26537.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26534.3-26542.6" + attribute \src "libresoc.v:26582.3-26590.6" wire $0\q_int$next[0:0]$908 - attribute \src "libresoc.v:26532.3-26533.27" + attribute \src "libresoc.v:26580.3-26581.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26534.3-26542.6" + attribute \src "libresoc.v:26582.3-26590.6" wire $1\q_int$next[0:0]$909 - attribute \src "libresoc.v:26513.7-26513.19" + attribute \src "libresoc.v:26561.7-26561.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26524.17-26524.96" - wire $and$libresoc.v:26524$898_Y - attribute \src "libresoc.v:26529.17-26529.96" - wire $and$libresoc.v:26529$903_Y - attribute \src "libresoc.v:26526.18-26526.93" - wire $not$libresoc.v:26526$900_Y - attribute \src "libresoc.v:26528.17-26528.92" - wire $not$libresoc.v:26528$902_Y - attribute \src "libresoc.v:26531.17-26531.92" - wire $not$libresoc.v:26531$905_Y - attribute \src "libresoc.v:26525.18-26525.98" - wire $or$libresoc.v:26525$899_Y - attribute \src "libresoc.v:26527.18-26527.99" - wire $or$libresoc.v:26527$901_Y - attribute \src "libresoc.v:26530.17-26530.97" - wire $or$libresoc.v:26530$904_Y + attribute \src "libresoc.v:26572.17-26572.96" + wire $and$libresoc.v:26572$898_Y + attribute \src "libresoc.v:26577.17-26577.96" + wire $and$libresoc.v:26577$903_Y + attribute \src "libresoc.v:26574.18-26574.93" + wire $not$libresoc.v:26574$900_Y + attribute \src "libresoc.v:26576.17-26576.92" + wire $not$libresoc.v:26576$902_Y + attribute \src "libresoc.v:26579.17-26579.92" + wire $not$libresoc.v:26579$905_Y + attribute \src "libresoc.v:26573.18-26573.98" + wire $or$libresoc.v:26573$899_Y + attribute \src "libresoc.v:26575.18-26575.99" + wire $or$libresoc.v:26575$901_Y + attribute \src "libresoc.v:26578.17-26578.97" + wire $or$libresoc.v:26578$904_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39541,11 +39577,11 @@ module \alu_l$16 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:26489.7-26489.15" + attribute \src "libresoc.v:26537.7-26537.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -39562,7 +39598,7 @@ module \alu_l$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26524$898 + cell $and $and$libresoc.v:26572$898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39570,10 +39606,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26524$898_Y + connect \Y $and$libresoc.v:26572$898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26529$903 + cell $and $and$libresoc.v:26577$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39581,34 +39617,34 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26529$903_Y + connect \Y $and$libresoc.v:26577$903_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26526$900 + cell $not $not$libresoc.v:26574$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26526$900_Y + connect \Y $not$libresoc.v:26574$900_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26528$902 + cell $not $not$libresoc.v:26576$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26528$902_Y + connect \Y $not$libresoc.v:26576$902_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26531$905 + cell $not $not$libresoc.v:26579$905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26531$905_Y + connect \Y $not$libresoc.v:26579$905_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26525$899 + cell $or $or$libresoc.v:26573$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39616,10 +39652,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26525$899_Y + connect \Y $or$libresoc.v:26573$899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26527$901 + cell $or $or$libresoc.v:26575$901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39627,10 +39663,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26527$901_Y + connect \Y $or$libresoc.v:26575$901_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26530$904 + cell $or $or$libresoc.v:26578$904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39638,39 +39674,39 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26530$904_Y + connect \Y $or$libresoc.v:26578$904_Y end - attribute \src "libresoc.v:26489.7-26489.20" - process $proc$libresoc.v:26489$910 + attribute \src "libresoc.v:26537.7-26537.20" + process $proc$libresoc.v:26537$910 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26513.7-26513.19" - process $proc$libresoc.v:26513$911 + attribute \src "libresoc.v:26561.7-26561.19" + process $proc$libresoc.v:26561$911 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26532.3-26533.27" - process $proc$libresoc.v:26532$906 + attribute \src "libresoc.v:26580.3-26581.27" + process $proc$libresoc.v:26580$906 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26534.3-26542.6" - process $proc$libresoc.v:26534$907 + attribute \src "libresoc.v:26582.3-26590.6" + process $proc$libresoc.v:26582$907 assign { } { } assign { } { } assign $0\q_int$next[0:0]$908 $1\q_int$next[0:0]$909 - attribute \src "libresoc.v:26535.5-26535.29" + attribute \src "libresoc.v:26583.5-26583.29" switch \initial - attribute \src "libresoc.v:26535.9-26535.17" + attribute \src "libresoc.v:26583.9-26583.17" case 1'1 case end @@ -39686,49 +39722,49 @@ module \alu_l$16 sync always update \q_int$next $0\q_int$next[0:0]$908 end - connect \$9 $and$libresoc.v:26524$898_Y - connect \$11 $or$libresoc.v:26525$899_Y - connect \$13 $not$libresoc.v:26526$900_Y - connect \$15 $or$libresoc.v:26527$901_Y - connect \$1 $not$libresoc.v:26528$902_Y - connect \$3 $and$libresoc.v:26529$903_Y - connect \$5 $or$libresoc.v:26530$904_Y - connect \$7 $not$libresoc.v:26531$905_Y + connect \$9 $and$libresoc.v:26572$898_Y + connect \$11 $or$libresoc.v:26573$899_Y + connect \$13 $not$libresoc.v:26574$900_Y + connect \$15 $or$libresoc.v:26575$901_Y + connect \$1 $not$libresoc.v:26576$902_Y + connect \$3 $and$libresoc.v:26577$903_Y + connect \$5 $or$libresoc.v:26578$904_Y + connect \$7 $not$libresoc.v:26579$905_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26550.1-26608.10" +attribute \src "libresoc.v:26598.1-26656.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_l" attribute \generator "nMigen" module \alu_l$29 - attribute \src "libresoc.v:26551.7-26551.20" + attribute \src "libresoc.v:26599.7-26599.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26596.3-26604.6" + attribute \src "libresoc.v:26644.3-26652.6" wire $0\q_int$next[0:0]$922 - attribute \src "libresoc.v:26594.3-26595.27" + attribute \src "libresoc.v:26642.3-26643.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26596.3-26604.6" + attribute \src "libresoc.v:26644.3-26652.6" wire $1\q_int$next[0:0]$923 - attribute \src "libresoc.v:26575.7-26575.19" + attribute \src "libresoc.v:26623.7-26623.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26586.17-26586.96" - wire $and$libresoc.v:26586$912_Y - attribute \src "libresoc.v:26591.17-26591.96" - wire $and$libresoc.v:26591$917_Y - attribute \src "libresoc.v:26588.18-26588.93" - wire $not$libresoc.v:26588$914_Y - attribute \src "libresoc.v:26590.17-26590.92" - wire $not$libresoc.v:26590$916_Y - attribute \src "libresoc.v:26593.17-26593.92" - wire $not$libresoc.v:26593$919_Y - attribute \src "libresoc.v:26587.18-26587.98" - wire $or$libresoc.v:26587$913_Y - attribute \src "libresoc.v:26589.18-26589.99" - wire $or$libresoc.v:26589$915_Y - attribute \src "libresoc.v:26592.17-26592.97" - wire $or$libresoc.v:26592$918_Y + attribute \src "libresoc.v:26634.17-26634.96" + wire $and$libresoc.v:26634$912_Y + attribute \src "libresoc.v:26639.17-26639.96" + wire $and$libresoc.v:26639$917_Y + attribute \src "libresoc.v:26636.18-26636.93" + wire $not$libresoc.v:26636$914_Y + attribute \src "libresoc.v:26638.17-26638.92" + wire $not$libresoc.v:26638$916_Y + attribute \src "libresoc.v:26641.17-26641.92" + wire $not$libresoc.v:26641$919_Y + attribute \src "libresoc.v:26635.18-26635.98" + wire $or$libresoc.v:26635$913_Y + attribute \src "libresoc.v:26637.18-26637.99" + wire $or$libresoc.v:26637$915_Y + attribute \src "libresoc.v:26640.17-26640.97" + wire $or$libresoc.v:26640$918_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39745,11 +39781,11 @@ module \alu_l$29 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:26551.7-26551.15" + attribute \src "libresoc.v:26599.7-26599.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -39766,7 +39802,7 @@ module \alu_l$29 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26586$912 + cell $and $and$libresoc.v:26634$912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39774,10 +39810,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26586$912_Y + connect \Y $and$libresoc.v:26634$912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26591$917 + cell $and $and$libresoc.v:26639$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39785,34 +39821,34 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26591$917_Y + connect \Y $and$libresoc.v:26639$917_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26588$914 + cell $not $not$libresoc.v:26636$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26588$914_Y + connect \Y $not$libresoc.v:26636$914_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26590$916 + cell $not $not$libresoc.v:26638$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26590$916_Y + connect \Y $not$libresoc.v:26638$916_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26593$919 + cell $not $not$libresoc.v:26641$919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26593$919_Y + connect \Y $not$libresoc.v:26641$919_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26587$913 + cell $or $or$libresoc.v:26635$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39820,10 +39856,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26587$913_Y + connect \Y $or$libresoc.v:26635$913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26589$915 + cell $or $or$libresoc.v:26637$915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39831,10 +39867,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26589$915_Y + connect \Y $or$libresoc.v:26637$915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26592$918 + cell $or $or$libresoc.v:26640$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39842,39 +39878,39 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26592$918_Y + connect \Y $or$libresoc.v:26640$918_Y end - attribute \src "libresoc.v:26551.7-26551.20" - process $proc$libresoc.v:26551$924 + attribute \src "libresoc.v:26599.7-26599.20" + process $proc$libresoc.v:26599$924 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26575.7-26575.19" - process $proc$libresoc.v:26575$925 + attribute \src "libresoc.v:26623.7-26623.19" + process $proc$libresoc.v:26623$925 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26594.3-26595.27" - process $proc$libresoc.v:26594$920 + attribute \src "libresoc.v:26642.3-26643.27" + process $proc$libresoc.v:26642$920 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26596.3-26604.6" - process $proc$libresoc.v:26596$921 + attribute \src "libresoc.v:26644.3-26652.6" + process $proc$libresoc.v:26644$921 assign { } { } assign { } { } assign $0\q_int$next[0:0]$922 $1\q_int$next[0:0]$923 - attribute \src "libresoc.v:26597.5-26597.29" + attribute \src "libresoc.v:26645.5-26645.29" switch \initial - attribute \src "libresoc.v:26597.9-26597.17" + attribute \src "libresoc.v:26645.9-26645.17" case 1'1 case end @@ -39890,49 +39926,49 @@ module \alu_l$29 sync always update \q_int$next $0\q_int$next[0:0]$922 end - connect \$9 $and$libresoc.v:26586$912_Y - connect \$11 $or$libresoc.v:26587$913_Y - connect \$13 $not$libresoc.v:26588$914_Y - connect \$15 $or$libresoc.v:26589$915_Y - connect \$1 $not$libresoc.v:26590$916_Y - connect \$3 $and$libresoc.v:26591$917_Y - connect \$5 $or$libresoc.v:26592$918_Y - connect \$7 $not$libresoc.v:26593$919_Y + connect \$9 $and$libresoc.v:26634$912_Y + connect \$11 $or$libresoc.v:26635$913_Y + connect \$13 $not$libresoc.v:26636$914_Y + connect \$15 $or$libresoc.v:26637$915_Y + connect \$1 $not$libresoc.v:26638$916_Y + connect \$3 $and$libresoc.v:26639$917_Y + connect \$5 $or$libresoc.v:26640$918_Y + connect \$7 $not$libresoc.v:26641$919_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26612.1-26670.10" +attribute \src "libresoc.v:26660.1-26718.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_l" attribute \generator "nMigen" module \alu_l$45 - attribute \src "libresoc.v:26613.7-26613.20" + attribute \src "libresoc.v:26661.7-26661.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26658.3-26666.6" + attribute \src "libresoc.v:26706.3-26714.6" wire $0\q_int$next[0:0]$936 - attribute \src "libresoc.v:26656.3-26657.27" + attribute \src "libresoc.v:26704.3-26705.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26658.3-26666.6" + attribute \src "libresoc.v:26706.3-26714.6" wire $1\q_int$next[0:0]$937 - attribute \src "libresoc.v:26637.7-26637.19" + attribute \src "libresoc.v:26685.7-26685.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26648.17-26648.96" - wire $and$libresoc.v:26648$926_Y - attribute \src "libresoc.v:26653.17-26653.96" - wire $and$libresoc.v:26653$931_Y - attribute \src "libresoc.v:26650.18-26650.93" - wire $not$libresoc.v:26650$928_Y - attribute \src "libresoc.v:26652.17-26652.92" - wire $not$libresoc.v:26652$930_Y - attribute \src "libresoc.v:26655.17-26655.92" - wire $not$libresoc.v:26655$933_Y - attribute \src "libresoc.v:26649.18-26649.98" - wire $or$libresoc.v:26649$927_Y - attribute \src "libresoc.v:26651.18-26651.99" - wire $or$libresoc.v:26651$929_Y - attribute \src "libresoc.v:26654.17-26654.97" - wire $or$libresoc.v:26654$932_Y + attribute \src "libresoc.v:26696.17-26696.96" + wire $and$libresoc.v:26696$926_Y + attribute \src "libresoc.v:26701.17-26701.96" + wire $and$libresoc.v:26701$931_Y + attribute \src "libresoc.v:26698.18-26698.93" + wire $not$libresoc.v:26698$928_Y + attribute \src "libresoc.v:26700.17-26700.92" + wire $not$libresoc.v:26700$930_Y + attribute \src "libresoc.v:26703.17-26703.92" + wire $not$libresoc.v:26703$933_Y + attribute \src "libresoc.v:26697.18-26697.98" + wire $or$libresoc.v:26697$927_Y + attribute \src "libresoc.v:26699.18-26699.99" + wire $or$libresoc.v:26699$929_Y + attribute \src "libresoc.v:26702.17-26702.97" + wire $or$libresoc.v:26702$932_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39949,11 +39985,11 @@ module \alu_l$45 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:26613.7-26613.15" + attribute \src "libresoc.v:26661.7-26661.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -39970,7 +40006,7 @@ module \alu_l$45 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26648$926 + cell $and $and$libresoc.v:26696$926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39978,10 +40014,10 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26648$926_Y + connect \Y $and$libresoc.v:26696$926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26653$931 + cell $and $and$libresoc.v:26701$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39989,34 +40025,34 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26653$931_Y + connect \Y $and$libresoc.v:26701$931_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26650$928 + cell $not $not$libresoc.v:26698$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26650$928_Y + connect \Y $not$libresoc.v:26698$928_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26652$930 + cell $not $not$libresoc.v:26700$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26652$930_Y + connect \Y $not$libresoc.v:26700$930_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26655$933 + cell $not $not$libresoc.v:26703$933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26655$933_Y + connect \Y $not$libresoc.v:26703$933_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26649$927 + cell $or $or$libresoc.v:26697$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40024,10 +40060,10 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26649$927_Y + connect \Y $or$libresoc.v:26697$927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26651$929 + cell $or $or$libresoc.v:26699$929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40035,10 +40071,10 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26651$929_Y + connect \Y $or$libresoc.v:26699$929_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26654$932 + cell $or $or$libresoc.v:26702$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40046,39 +40082,39 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26654$932_Y + connect \Y $or$libresoc.v:26702$932_Y end - attribute \src "libresoc.v:26613.7-26613.20" - process $proc$libresoc.v:26613$938 + attribute \src "libresoc.v:26661.7-26661.20" + process $proc$libresoc.v:26661$938 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26637.7-26637.19" - process $proc$libresoc.v:26637$939 + attribute \src "libresoc.v:26685.7-26685.19" + process $proc$libresoc.v:26685$939 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26656.3-26657.27" - process $proc$libresoc.v:26656$934 + attribute \src "libresoc.v:26704.3-26705.27" + process $proc$libresoc.v:26704$934 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26658.3-26666.6" - process $proc$libresoc.v:26658$935 + attribute \src "libresoc.v:26706.3-26714.6" + process $proc$libresoc.v:26706$935 assign { } { } assign { } { } assign $0\q_int$next[0:0]$936 $1\q_int$next[0:0]$937 - attribute \src "libresoc.v:26659.5-26659.29" + attribute \src "libresoc.v:26707.5-26707.29" switch \initial - attribute \src "libresoc.v:26659.9-26659.17" + attribute \src "libresoc.v:26707.9-26707.17" case 1'1 case end @@ -40094,49 +40130,49 @@ module \alu_l$45 sync always update \q_int$next $0\q_int$next[0:0]$936 end - connect \$9 $and$libresoc.v:26648$926_Y - connect \$11 $or$libresoc.v:26649$927_Y - connect \$13 $not$libresoc.v:26650$928_Y - connect \$15 $or$libresoc.v:26651$929_Y - connect \$1 $not$libresoc.v:26652$930_Y - connect \$3 $and$libresoc.v:26653$931_Y - connect \$5 $or$libresoc.v:26654$932_Y - connect \$7 $not$libresoc.v:26655$933_Y + connect \$9 $and$libresoc.v:26696$926_Y + connect \$11 $or$libresoc.v:26697$927_Y + connect \$13 $not$libresoc.v:26698$928_Y + connect \$15 $or$libresoc.v:26699$929_Y + connect \$1 $not$libresoc.v:26700$930_Y + connect \$3 $and$libresoc.v:26701$931_Y + connect \$5 $or$libresoc.v:26702$932_Y + connect \$7 $not$libresoc.v:26703$933_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26674.1-26732.10" +attribute \src "libresoc.v:26722.1-26780.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_l" attribute \generator "nMigen" module \alu_l$61 - attribute \src "libresoc.v:26675.7-26675.20" + attribute \src "libresoc.v:26723.7-26723.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26720.3-26728.6" + attribute \src "libresoc.v:26768.3-26776.6" wire $0\q_int$next[0:0]$950 - attribute \src "libresoc.v:26718.3-26719.27" + attribute \src "libresoc.v:26766.3-26767.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26720.3-26728.6" + attribute \src "libresoc.v:26768.3-26776.6" wire $1\q_int$next[0:0]$951 - attribute \src "libresoc.v:26699.7-26699.19" + attribute \src "libresoc.v:26747.7-26747.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26710.17-26710.96" - wire $and$libresoc.v:26710$940_Y - attribute \src "libresoc.v:26715.17-26715.96" - wire $and$libresoc.v:26715$945_Y - attribute \src "libresoc.v:26712.18-26712.93" - wire $not$libresoc.v:26712$942_Y - attribute \src "libresoc.v:26714.17-26714.92" - wire $not$libresoc.v:26714$944_Y - attribute \src "libresoc.v:26717.17-26717.92" - wire $not$libresoc.v:26717$947_Y - attribute \src "libresoc.v:26711.18-26711.98" - wire $or$libresoc.v:26711$941_Y - attribute \src "libresoc.v:26713.18-26713.99" - wire $or$libresoc.v:26713$943_Y - attribute \src "libresoc.v:26716.17-26716.97" - wire $or$libresoc.v:26716$946_Y + attribute \src "libresoc.v:26758.17-26758.96" + wire $and$libresoc.v:26758$940_Y + attribute \src "libresoc.v:26763.17-26763.96" + wire $and$libresoc.v:26763$945_Y + attribute \src "libresoc.v:26760.18-26760.93" + wire $not$libresoc.v:26760$942_Y + attribute \src "libresoc.v:26762.17-26762.92" + wire $not$libresoc.v:26762$944_Y + attribute \src "libresoc.v:26765.17-26765.92" + wire $not$libresoc.v:26765$947_Y + attribute \src "libresoc.v:26759.18-26759.98" + wire $or$libresoc.v:26759$941_Y + attribute \src "libresoc.v:26761.18-26761.99" + wire $or$libresoc.v:26761$943_Y + attribute \src "libresoc.v:26764.17-26764.97" + wire $or$libresoc.v:26764$946_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -40153,11 +40189,11 @@ module \alu_l$61 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:26675.7-26675.15" + attribute \src "libresoc.v:26723.7-26723.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -40174,7 +40210,7 @@ module \alu_l$61 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26710$940 + cell $and $and$libresoc.v:26758$940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40182,10 +40218,10 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26710$940_Y + connect \Y $and$libresoc.v:26758$940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26715$945 + cell $and $and$libresoc.v:26763$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40193,34 +40229,34 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26715$945_Y + connect \Y $and$libresoc.v:26763$945_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26712$942 + cell $not $not$libresoc.v:26760$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26712$942_Y + connect \Y $not$libresoc.v:26760$942_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26714$944 + cell $not $not$libresoc.v:26762$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26714$944_Y + connect \Y $not$libresoc.v:26762$944_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26717$947 + cell $not $not$libresoc.v:26765$947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26717$947_Y + connect \Y $not$libresoc.v:26765$947_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26711$941 + cell $or $or$libresoc.v:26759$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40228,10 +40264,10 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26711$941_Y + connect \Y $or$libresoc.v:26759$941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26713$943 + cell $or $or$libresoc.v:26761$943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40239,10 +40275,10 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26713$943_Y + connect \Y $or$libresoc.v:26761$943_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26716$946 + cell $or $or$libresoc.v:26764$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40250,39 +40286,39 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26716$946_Y + connect \Y $or$libresoc.v:26764$946_Y end - attribute \src "libresoc.v:26675.7-26675.20" - process $proc$libresoc.v:26675$952 + attribute \src "libresoc.v:26723.7-26723.20" + process $proc$libresoc.v:26723$952 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26699.7-26699.19" - process $proc$libresoc.v:26699$953 + attribute \src "libresoc.v:26747.7-26747.19" + process $proc$libresoc.v:26747$953 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26718.3-26719.27" - process $proc$libresoc.v:26718$948 + attribute \src "libresoc.v:26766.3-26767.27" + process $proc$libresoc.v:26766$948 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26720.3-26728.6" - process $proc$libresoc.v:26720$949 + attribute \src "libresoc.v:26768.3-26776.6" + process $proc$libresoc.v:26768$949 assign { } { } assign { } { } assign $0\q_int$next[0:0]$950 $1\q_int$next[0:0]$951 - attribute \src "libresoc.v:26721.5-26721.29" + attribute \src "libresoc.v:26769.5-26769.29" switch \initial - attribute \src "libresoc.v:26721.9-26721.17" + attribute \src "libresoc.v:26769.9-26769.17" case 1'1 case end @@ -40298,49 +40334,49 @@ module \alu_l$61 sync always update \q_int$next $0\q_int$next[0:0]$950 end - connect \$9 $and$libresoc.v:26710$940_Y - connect \$11 $or$libresoc.v:26711$941_Y - connect \$13 $not$libresoc.v:26712$942_Y - connect \$15 $or$libresoc.v:26713$943_Y - connect \$1 $not$libresoc.v:26714$944_Y - connect \$3 $and$libresoc.v:26715$945_Y - connect \$5 $or$libresoc.v:26716$946_Y - connect \$7 $not$libresoc.v:26717$947_Y + connect \$9 $and$libresoc.v:26758$940_Y + connect \$11 $or$libresoc.v:26759$941_Y + connect \$13 $not$libresoc.v:26760$942_Y + connect \$15 $or$libresoc.v:26761$943_Y + connect \$1 $not$libresoc.v:26762$944_Y + connect \$3 $and$libresoc.v:26763$945_Y + connect \$5 $or$libresoc.v:26764$946_Y + connect \$7 $not$libresoc.v:26765$947_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26736.1-26794.10" +attribute \src "libresoc.v:26784.1-26842.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_l" attribute \generator "nMigen" module \alu_l$73 - attribute \src "libresoc.v:26737.7-26737.20" + attribute \src "libresoc.v:26785.7-26785.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26782.3-26790.6" + attribute \src "libresoc.v:26830.3-26838.6" wire $0\q_int$next[0:0]$964 - attribute \src "libresoc.v:26780.3-26781.27" + attribute \src "libresoc.v:26828.3-26829.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26782.3-26790.6" + attribute \src "libresoc.v:26830.3-26838.6" wire $1\q_int$next[0:0]$965 - attribute \src "libresoc.v:26761.7-26761.19" + attribute \src "libresoc.v:26809.7-26809.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26772.17-26772.96" - wire $and$libresoc.v:26772$954_Y - attribute \src "libresoc.v:26777.17-26777.96" - wire $and$libresoc.v:26777$959_Y - attribute \src "libresoc.v:26774.18-26774.93" - wire $not$libresoc.v:26774$956_Y - attribute \src "libresoc.v:26776.17-26776.92" - wire $not$libresoc.v:26776$958_Y - attribute \src "libresoc.v:26779.17-26779.92" - wire $not$libresoc.v:26779$961_Y - attribute \src "libresoc.v:26773.18-26773.98" - wire $or$libresoc.v:26773$955_Y - attribute \src "libresoc.v:26775.18-26775.99" - wire $or$libresoc.v:26775$957_Y - attribute \src "libresoc.v:26778.17-26778.97" - wire $or$libresoc.v:26778$960_Y + attribute \src "libresoc.v:26820.17-26820.96" + wire $and$libresoc.v:26820$954_Y + attribute \src "libresoc.v:26825.17-26825.96" + wire $and$libresoc.v:26825$959_Y + attribute \src "libresoc.v:26822.18-26822.93" + wire $not$libresoc.v:26822$956_Y + attribute \src "libresoc.v:26824.17-26824.92" + wire $not$libresoc.v:26824$958_Y + attribute \src "libresoc.v:26827.17-26827.92" + wire $not$libresoc.v:26827$961_Y + attribute \src "libresoc.v:26821.18-26821.98" + wire $or$libresoc.v:26821$955_Y + attribute \src "libresoc.v:26823.18-26823.99" + wire $or$libresoc.v:26823$957_Y + attribute \src "libresoc.v:26826.17-26826.97" + wire $or$libresoc.v:26826$960_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -40357,11 +40393,11 @@ module \alu_l$73 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:26737.7-26737.15" + attribute \src "libresoc.v:26785.7-26785.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -40378,7 +40414,7 @@ module \alu_l$73 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26772$954 + cell $and $and$libresoc.v:26820$954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40386,10 +40422,10 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26772$954_Y + connect \Y $and$libresoc.v:26820$954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26777$959 + cell $and $and$libresoc.v:26825$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40397,34 +40433,34 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26777$959_Y + connect \Y $and$libresoc.v:26825$959_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26774$956 + cell $not $not$libresoc.v:26822$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26774$956_Y + connect \Y $not$libresoc.v:26822$956_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26776$958 + cell $not $not$libresoc.v:26824$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26776$958_Y + connect \Y $not$libresoc.v:26824$958_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26779$961 + cell $not $not$libresoc.v:26827$961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26779$961_Y + connect \Y $not$libresoc.v:26827$961_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26773$955 + cell $or $or$libresoc.v:26821$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40432,10 +40468,10 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26773$955_Y + connect \Y $or$libresoc.v:26821$955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26775$957 + cell $or $or$libresoc.v:26823$957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40443,10 +40479,10 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26775$957_Y + connect \Y $or$libresoc.v:26823$957_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26778$960 + cell $or $or$libresoc.v:26826$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40454,39 +40490,39 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26778$960_Y + connect \Y $or$libresoc.v:26826$960_Y end - attribute \src "libresoc.v:26737.7-26737.20" - process $proc$libresoc.v:26737$966 + attribute \src "libresoc.v:26785.7-26785.20" + process $proc$libresoc.v:26785$966 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26761.7-26761.19" - process $proc$libresoc.v:26761$967 + attribute \src "libresoc.v:26809.7-26809.19" + process $proc$libresoc.v:26809$967 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26780.3-26781.27" - process $proc$libresoc.v:26780$962 + attribute \src "libresoc.v:26828.3-26829.27" + process $proc$libresoc.v:26828$962 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26782.3-26790.6" - process $proc$libresoc.v:26782$963 + attribute \src "libresoc.v:26830.3-26838.6" + process $proc$libresoc.v:26830$963 assign { } { } assign { } { } assign $0\q_int$next[0:0]$964 $1\q_int$next[0:0]$965 - attribute \src "libresoc.v:26783.5-26783.29" + attribute \src "libresoc.v:26831.5-26831.29" switch \initial - attribute \src "libresoc.v:26783.9-26783.17" + attribute \src "libresoc.v:26831.9-26831.17" case 1'1 case end @@ -40502,49 +40538,49 @@ module \alu_l$73 sync always update \q_int$next $0\q_int$next[0:0]$964 end - connect \$9 $and$libresoc.v:26772$954_Y - connect \$11 $or$libresoc.v:26773$955_Y - connect \$13 $not$libresoc.v:26774$956_Y - connect \$15 $or$libresoc.v:26775$957_Y - connect \$1 $not$libresoc.v:26776$958_Y - connect \$3 $and$libresoc.v:26777$959_Y - connect \$5 $or$libresoc.v:26778$960_Y - connect \$7 $not$libresoc.v:26779$961_Y + connect \$9 $and$libresoc.v:26820$954_Y + connect \$11 $or$libresoc.v:26821$955_Y + connect \$13 $not$libresoc.v:26822$956_Y + connect \$15 $or$libresoc.v:26823$957_Y + connect \$1 $not$libresoc.v:26824$958_Y + connect \$3 $and$libresoc.v:26825$959_Y + connect \$5 $or$libresoc.v:26826$960_Y + connect \$7 $not$libresoc.v:26827$961_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26798.1-26856.10" +attribute \src "libresoc.v:26846.1-26904.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_l" attribute \generator "nMigen" module \alu_l$90 - attribute \src "libresoc.v:26799.7-26799.20" + attribute \src "libresoc.v:26847.7-26847.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26844.3-26852.6" + attribute \src "libresoc.v:26892.3-26900.6" wire $0\q_int$next[0:0]$978 - attribute \src "libresoc.v:26842.3-26843.27" + attribute \src "libresoc.v:26890.3-26891.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26844.3-26852.6" + attribute \src "libresoc.v:26892.3-26900.6" wire $1\q_int$next[0:0]$979 - attribute \src "libresoc.v:26823.7-26823.19" + attribute \src "libresoc.v:26871.7-26871.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26834.17-26834.96" - wire $and$libresoc.v:26834$968_Y - attribute \src "libresoc.v:26839.17-26839.96" - wire $and$libresoc.v:26839$973_Y - attribute \src "libresoc.v:26836.18-26836.93" - wire $not$libresoc.v:26836$970_Y - attribute \src "libresoc.v:26838.17-26838.92" - wire $not$libresoc.v:26838$972_Y - attribute \src "libresoc.v:26841.17-26841.92" - wire $not$libresoc.v:26841$975_Y - attribute \src "libresoc.v:26835.18-26835.98" - wire $or$libresoc.v:26835$969_Y - attribute \src "libresoc.v:26837.18-26837.99" - wire $or$libresoc.v:26837$971_Y - attribute \src "libresoc.v:26840.17-26840.97" - wire $or$libresoc.v:26840$974_Y + attribute \src "libresoc.v:26882.17-26882.96" + wire $and$libresoc.v:26882$968_Y + attribute \src "libresoc.v:26887.17-26887.96" + wire $and$libresoc.v:26887$973_Y + attribute \src "libresoc.v:26884.18-26884.93" + wire $not$libresoc.v:26884$970_Y + attribute \src "libresoc.v:26886.17-26886.92" + wire $not$libresoc.v:26886$972_Y + attribute \src "libresoc.v:26889.17-26889.92" + wire $not$libresoc.v:26889$975_Y + attribute \src "libresoc.v:26883.18-26883.98" + wire $or$libresoc.v:26883$969_Y + attribute \src "libresoc.v:26885.18-26885.99" + wire $or$libresoc.v:26885$971_Y + attribute \src "libresoc.v:26888.17-26888.97" + wire $or$libresoc.v:26888$974_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -40561,11 +40597,11 @@ module \alu_l$90 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:26799.7-26799.15" + attribute \src "libresoc.v:26847.7-26847.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -40582,7 +40618,7 @@ module \alu_l$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26834$968 + cell $and $and$libresoc.v:26882$968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40590,10 +40626,10 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26834$968_Y + connect \Y $and$libresoc.v:26882$968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26839$973 + cell $and $and$libresoc.v:26887$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40601,34 +40637,34 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26839$973_Y + connect \Y $and$libresoc.v:26887$973_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26836$970 + cell $not $not$libresoc.v:26884$970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26836$970_Y + connect \Y $not$libresoc.v:26884$970_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26838$972 + cell $not $not$libresoc.v:26886$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26838$972_Y + connect \Y $not$libresoc.v:26886$972_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26841$975 + cell $not $not$libresoc.v:26889$975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26841$975_Y + connect \Y $not$libresoc.v:26889$975_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26835$969 + cell $or $or$libresoc.v:26883$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40636,10 +40672,10 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26835$969_Y + connect \Y $or$libresoc.v:26883$969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26837$971 + cell $or $or$libresoc.v:26885$971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40647,10 +40683,10 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26837$971_Y + connect \Y $or$libresoc.v:26885$971_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26840$974 + cell $or $or$libresoc.v:26888$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40658,39 +40694,39 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26840$974_Y + connect \Y $or$libresoc.v:26888$974_Y end - attribute \src "libresoc.v:26799.7-26799.20" - process $proc$libresoc.v:26799$980 + attribute \src "libresoc.v:26847.7-26847.20" + process $proc$libresoc.v:26847$980 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26823.7-26823.19" - process $proc$libresoc.v:26823$981 + attribute \src "libresoc.v:26871.7-26871.19" + process $proc$libresoc.v:26871$981 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26842.3-26843.27" - process $proc$libresoc.v:26842$976 + attribute \src "libresoc.v:26890.3-26891.27" + process $proc$libresoc.v:26890$976 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26844.3-26852.6" - process $proc$libresoc.v:26844$977 + attribute \src "libresoc.v:26892.3-26900.6" + process $proc$libresoc.v:26892$977 assign { } { } assign { } { } assign $0\q_int$next[0:0]$978 $1\q_int$next[0:0]$979 - attribute \src "libresoc.v:26845.5-26845.29" + attribute \src "libresoc.v:26893.5-26893.29" switch \initial - attribute \src "libresoc.v:26845.9-26845.17" + attribute \src "libresoc.v:26893.9-26893.17" case 1'1 case end @@ -40706,30 +40742,30 @@ module \alu_l$90 sync always update \q_int$next $0\q_int$next[0:0]$978 end - connect \$9 $and$libresoc.v:26834$968_Y - connect \$11 $or$libresoc.v:26835$969_Y - connect \$13 $not$libresoc.v:26836$970_Y - connect \$15 $or$libresoc.v:26837$971_Y - connect \$1 $not$libresoc.v:26838$972_Y - connect \$3 $and$libresoc.v:26839$973_Y - connect \$5 $or$libresoc.v:26840$974_Y - connect \$7 $not$libresoc.v:26841$975_Y + connect \$9 $and$libresoc.v:26882$968_Y + connect \$11 $or$libresoc.v:26883$969_Y + connect \$13 $not$libresoc.v:26884$970_Y + connect \$15 $or$libresoc.v:26885$971_Y + connect \$1 $not$libresoc.v:26886$972_Y + connect \$3 $and$libresoc.v:26887$973_Y + connect \$5 $or$libresoc.v:26888$974_Y + connect \$7 $not$libresoc.v:26889$975_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26860.1-27873.10" +attribute \src "libresoc.v:26908.1-27921.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0" attribute \generator "nMigen" module \alu_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 22 \logical_op__data_len @@ -40991,9 +41027,9 @@ module \alu_logical0 wire input 15 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \logical_pipe1_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe1_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_pipe1_logical_op__data_len @@ -41263,9 +41299,9 @@ module \alu_logical0 wire \logical_pipe1_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \logical_pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \logical_pipe1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe1_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \logical_pipe1_p_ready_o @@ -41275,19 +41311,19 @@ module \alu_logical0 wire width 64 \logical_pipe1_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \logical_pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe1_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \logical_pipe1_xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe1_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \logical_pipe2_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \logical_pipe2_cr_a$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe2_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe2_cr_a_ok$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_pipe2_logical_op__data_len @@ -41557,21 +41593,21 @@ module \alu_logical0 wire \logical_pipe2_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \logical_pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \logical_pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \logical_pipe2_o$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe2_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe2_o_ok$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \logical_pipe2_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \logical_pipe2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe2_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid @@ -41581,9 +41617,9 @@ module \alu_logical0 wire input 5 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 4 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 24 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 30 \p_ready_o @@ -41596,7 +41632,7 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 28 \xer_so attribute \module_not_derived 1 - attribute \src "libresoc.v:27733.17-27787.4" + attribute \src "libresoc.v:27781.17-27835.4" cell \logical_pipe1 \logical_pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -41653,7 +41689,7 @@ module \alu_logical0 connect \xer_so_ok \logical_pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:27788.17-27843.4" + attribute \src "libresoc.v:27836.17-27891.4" cell \logical_pipe2 \logical_pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -41711,13 +41747,13 @@ module \alu_logical0 connect \xer_so_ok \logical_pipe2_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:27844.10-27847.4" + attribute \src "libresoc.v:27892.10-27895.4" cell \n$47 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:27848.10-27851.4" + attribute \src "libresoc.v:27896.10-27899.4" cell \p$46 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i @@ -41744,18 +41780,18 @@ module \alu_logical0 connect \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o connect \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o end -attribute \src "libresoc.v:27877.1-29094.10" +attribute \src "libresoc.v:27925.1-29142.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0" attribute \generator "nMigen" module \alu_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \cr_a_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -42499,9 +42535,9 @@ module \alu_mul0 wire \mul_pipe2_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul_pipe2_xer_so$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \mul_pipe3_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul_pipe3_cr_a_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -42745,23 +42781,23 @@ module \alu_mul0 wire \mul_pipe3_neg_res32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 \mul_pipe3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \mul_pipe3_o$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul_pipe3_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \mul_pipe3_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \mul_pipe3_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \mul_pipe3_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul_pipe3_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul_pipe3_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul_pipe3_xer_so$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul_pipe3_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid @@ -42771,9 +42807,9 @@ module \alu_mul0 wire input 7 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 6 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 20 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 28 \p_ready_o @@ -42783,18 +42819,18 @@ module \alu_mul0 wire width 64 input 24 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 25 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 22 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 26 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:28922.13-28963.4" + attribute \src "libresoc.v:28970.13-29011.4" cell \mul_pipe1 \mul_pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42838,7 +42874,7 @@ module \alu_mul0 connect \xer_so$16 \mul_pipe1_xer_so$17 end attribute \module_not_derived 1 - attribute \src "libresoc.v:28964.13-29006.4" + attribute \src "libresoc.v:29012.13-29054.4" cell \mul_pipe2 \mul_pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42883,7 +42919,7 @@ module \alu_mul0 connect \xer_so$14 \mul_pipe2_xer_so$31 end attribute \module_not_derived 1 - attribute \src "libresoc.v:29007.13-29052.4" + attribute \src "libresoc.v:29055.13-29100.4" cell \mul_pipe3 \mul_pipe3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42931,13 +42967,13 @@ module \alu_mul0 connect \xer_so_ok \mul_pipe3_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:29053.10-29056.4" + attribute \src "libresoc.v:29101.10-29104.4" cell \n$92 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:29057.10-29060.4" + attribute \src "libresoc.v:29105.10-29108.4" cell \p$91 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i @@ -42976,18 +43012,18 @@ module \alu_mul0 connect \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o connect \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o end -attribute \src "libresoc.v:29098.1-30131.10" +attribute \src "libresoc.v:29146.1-30179.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" attribute \generator "nMigen" module \alu_shift_rot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid @@ -42997,17 +43033,17 @@ module \alu_shift_rot0 wire input 6 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 24 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 33 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 32 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe1_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe1_muxid @@ -43017,9 +43053,9 @@ module \alu_shift_rot0 wire \pipe1_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe1_p_ready_o @@ -43287,25 +43323,25 @@ module \alu_shift_rot0 wire \pipe1_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__write_cr0$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe1_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \pipe1_xer_ca$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe1_xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe2_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe2_cr_a$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_cr_a_ok$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe2_muxid @@ -43315,13 +43351,13 @@ module \alu_shift_rot0 wire \pipe2_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_o$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_o_ok$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe2_p_ready_o @@ -43583,17 +43619,17 @@ module \alu_shift_rot0 wire \pipe2_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__write_cr0$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe2_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe2_xer_ca$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_ca_ok$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 27 \ra @@ -43857,28 +43893,28 @@ module \alu_shift_rot0 wire input 15 \sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__write_cr0$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 26 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 31 \xer_ca$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 30 \xer_so attribute \module_not_derived 1 - attribute \src "libresoc.v:29983.11-29986.4" + attribute \src "libresoc.v:30031.11-30034.4" cell \n$109 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:29987.11-29990.4" + attribute \src "libresoc.v:30035.11-30038.4" cell \p$108 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:29991.15-30047.4" + attribute \src "libresoc.v:30039.15-30095.4" cell \pipe1$110 \pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -43937,7 +43973,7 @@ module \alu_shift_rot0 connect \xer_so_ok \pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:30048.15-30105.4" + attribute \src "libresoc.v:30096.15-30153.4" cell \pipe2$115 \pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -44022,20 +44058,20 @@ module \alu_shift_rot0 connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:30135.1-30693.10" +attribute \src "libresoc.v:30183.1-30741.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0" attribute \generator "nMigen" module \alu_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 28 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 16 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 22 \fast1$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 6 \fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid @@ -44045,9 +44081,9 @@ module \alu_spr0 wire input 9 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 8 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 14 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 27 \p_ready_o @@ -44055,9 +44091,9 @@ module \alu_spr0 wire input 26 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_fast1$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid @@ -44067,9 +44103,9 @@ module \alu_spr0 wire \pipe_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_p_ready_o @@ -44079,9 +44115,9 @@ module \alu_spr0 wire width 64 \pipe_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_spr1$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_spr1_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -44281,29 +44317,29 @@ module \alu_spr0 wire \pipe_spr_op__is_32bit$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \pipe_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe_xer_ca$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \pipe_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe_xer_ov$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_xer_so$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 15 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 21 \spr1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 7 \spr1_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -44501,38 +44537,38 @@ module \alu_spr0 wire input 13 \spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \spr_op__is_32bit$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 19 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 25 \xer_ca$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 18 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 24 \xer_ov$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 17 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 23 \xer_so$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:30628.10-30631.4" + attribute \src "libresoc.v:30676.10-30679.4" cell \n$63 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:30632.10-30635.4" + attribute \src "libresoc.v:30680.10-30683.4" cell \p$62 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:30636.13-30671.4" + attribute \src "libresoc.v:30684.13-30719.4" cell \pipe$64 \pipe connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -44591,30 +44627,30 @@ module \alu_spr0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:30697.1-31570.10" +attribute \src "libresoc.v:30745.1-31618.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0" attribute \generator "nMigen" module \alu_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 19 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 25 \fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 20 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 26 \fast2$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 22 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 6 \msr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid @@ -44624,13 +44660,13 @@ module \alu_trap0 wire input 8 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 7 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 21 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 18 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 28 \p_ready_o @@ -44882,19 +44918,19 @@ module \alu_trap0 wire width 8 \pipe1_trap_op__traptype$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe2_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_fast1$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe2_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_fast2$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_msr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe2_muxid @@ -44904,13 +44940,13 @@ module \alu_trap0 wire \pipe2_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe2_p_ready_o @@ -45357,19 +45393,19 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$36 attribute \module_not_derived 1 - attribute \src "libresoc.v:31458.10-31461.4" + attribute \src "libresoc.v:31506.10-31509.4" cell \n$31 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:31462.10-31465.4" + attribute \src "libresoc.v:31510.10-31513.4" cell \p$30 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:31466.14-31501.4" + attribute \src "libresoc.v:31514.14-31549.4" cell \pipe1$32 \pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -45407,7 +45443,7 @@ module \alu_trap0 connect \trap_op__traptype$8 \pipe1_trap_op__traptype$10 end attribute \module_not_derived 1 - attribute \src "libresoc.v:31502.14-31543.4" + attribute \src "libresoc.v:31550.14-31591.4" cell \pipe2$35 \pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -45477,37 +45513,37 @@ module \alu_trap0 connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:31574.1-31632.10" +attribute \src "libresoc.v:31622.1-31680.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alui_l" attribute \generator "nMigen" module \alui_l - attribute \src "libresoc.v:31575.7-31575.20" + attribute \src "libresoc.v:31623.7-31623.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31620.3-31628.6" + attribute \src "libresoc.v:31668.3-31676.6" wire $0\q_int$next[0:0]$992 - attribute \src "libresoc.v:31618.3-31619.27" + attribute \src "libresoc.v:31666.3-31667.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31620.3-31628.6" + attribute \src "libresoc.v:31668.3-31676.6" wire $1\q_int$next[0:0]$993 - attribute \src "libresoc.v:31599.7-31599.19" + attribute \src "libresoc.v:31647.7-31647.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31610.17-31610.96" - wire $and$libresoc.v:31610$982_Y - attribute \src "libresoc.v:31615.17-31615.96" - wire $and$libresoc.v:31615$987_Y - attribute \src "libresoc.v:31612.18-31612.94" - wire $not$libresoc.v:31612$984_Y - attribute \src "libresoc.v:31614.17-31614.93" - wire $not$libresoc.v:31614$986_Y - attribute \src "libresoc.v:31617.17-31617.93" - wire $not$libresoc.v:31617$989_Y - attribute \src "libresoc.v:31611.18-31611.99" - wire $or$libresoc.v:31611$983_Y - attribute \src "libresoc.v:31613.18-31613.100" - wire $or$libresoc.v:31613$985_Y - attribute \src "libresoc.v:31616.17-31616.98" - wire $or$libresoc.v:31616$988_Y + attribute \src "libresoc.v:31658.17-31658.96" + wire $and$libresoc.v:31658$982_Y + attribute \src "libresoc.v:31663.17-31663.96" + wire $and$libresoc.v:31663$987_Y + attribute \src "libresoc.v:31660.18-31660.94" + wire $not$libresoc.v:31660$984_Y + attribute \src "libresoc.v:31662.17-31662.93" + wire $not$libresoc.v:31662$986_Y + attribute \src "libresoc.v:31665.17-31665.93" + wire $not$libresoc.v:31665$989_Y + attribute \src "libresoc.v:31659.18-31659.99" + wire $or$libresoc.v:31659$983_Y + attribute \src "libresoc.v:31661.18-31661.100" + wire $or$libresoc.v:31661$985_Y + attribute \src "libresoc.v:31664.17-31664.98" + wire $or$libresoc.v:31664$988_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -45524,11 +45560,11 @@ module \alui_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:31575.7-31575.15" + attribute \src "libresoc.v:31623.7-31623.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -45545,7 +45581,7 @@ module \alui_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31610$982 + cell $and $and$libresoc.v:31658$982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45553,10 +45589,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31610$982_Y + connect \Y $and$libresoc.v:31658$982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31615$987 + cell $and $and$libresoc.v:31663$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45564,34 +45600,34 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31615$987_Y + connect \Y $and$libresoc.v:31663$987_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31612$984 + cell $not $not$libresoc.v:31660$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31612$984_Y + connect \Y $not$libresoc.v:31660$984_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31614$986 + cell $not $not$libresoc.v:31662$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31614$986_Y + connect \Y $not$libresoc.v:31662$986_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31617$989 + cell $not $not$libresoc.v:31665$989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31617$989_Y + connect \Y $not$libresoc.v:31665$989_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31611$983 + cell $or $or$libresoc.v:31659$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45599,10 +45635,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31611$983_Y + connect \Y $or$libresoc.v:31659$983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31613$985 + cell $or $or$libresoc.v:31661$985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45610,10 +45646,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31613$985_Y + connect \Y $or$libresoc.v:31661$985_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31616$988 + cell $or $or$libresoc.v:31664$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45621,39 +45657,39 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31616$988_Y + connect \Y $or$libresoc.v:31664$988_Y end - attribute \src "libresoc.v:31575.7-31575.20" - process $proc$libresoc.v:31575$994 + attribute \src "libresoc.v:31623.7-31623.20" + process $proc$libresoc.v:31623$994 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31599.7-31599.19" - process $proc$libresoc.v:31599$995 + attribute \src "libresoc.v:31647.7-31647.19" + process $proc$libresoc.v:31647$995 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31618.3-31619.27" - process $proc$libresoc.v:31618$990 + attribute \src "libresoc.v:31666.3-31667.27" + process $proc$libresoc.v:31666$990 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31620.3-31628.6" - process $proc$libresoc.v:31620$991 + attribute \src "libresoc.v:31668.3-31676.6" + process $proc$libresoc.v:31668$991 assign { } { } assign { } { } assign $0\q_int$next[0:0]$992 $1\q_int$next[0:0]$993 - attribute \src "libresoc.v:31621.5-31621.29" + attribute \src "libresoc.v:31669.5-31669.29" switch \initial - attribute \src "libresoc.v:31621.9-31621.17" + attribute \src "libresoc.v:31669.9-31669.17" case 1'1 case end @@ -45669,49 +45705,49 @@ module \alui_l sync always update \q_int$next $0\q_int$next[0:0]$992 end - connect \$9 $and$libresoc.v:31610$982_Y - connect \$11 $or$libresoc.v:31611$983_Y - connect \$13 $not$libresoc.v:31612$984_Y - connect \$15 $or$libresoc.v:31613$985_Y - connect \$1 $not$libresoc.v:31614$986_Y - connect \$3 $and$libresoc.v:31615$987_Y - connect \$5 $or$libresoc.v:31616$988_Y - connect \$7 $not$libresoc.v:31617$989_Y + connect \$9 $and$libresoc.v:31658$982_Y + connect \$11 $or$libresoc.v:31659$983_Y + connect \$13 $not$libresoc.v:31660$984_Y + connect \$15 $or$libresoc.v:31661$985_Y + connect \$1 $not$libresoc.v:31662$986_Y + connect \$3 $and$libresoc.v:31663$987_Y + connect \$5 $or$libresoc.v:31664$988_Y + connect \$7 $not$libresoc.v:31665$989_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31636.1-31694.10" +attribute \src "libresoc.v:31684.1-31742.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alui_l" attribute \generator "nMigen" module \alui_l$106 - attribute \src "libresoc.v:31637.7-31637.20" + attribute \src "libresoc.v:31685.7-31685.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31682.3-31690.6" + attribute \src "libresoc.v:31730.3-31738.6" wire $0\q_int$next[0:0]$1006 - attribute \src "libresoc.v:31680.3-31681.27" + attribute \src "libresoc.v:31728.3-31729.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31682.3-31690.6" + attribute \src "libresoc.v:31730.3-31738.6" wire $1\q_int$next[0:0]$1007 - attribute \src "libresoc.v:31661.7-31661.19" + attribute \src "libresoc.v:31709.7-31709.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31672.17-31672.96" - wire $and$libresoc.v:31672$996_Y - attribute \src "libresoc.v:31677.17-31677.96" - wire $and$libresoc.v:31677$1001_Y - attribute \src "libresoc.v:31674.18-31674.94" - wire $not$libresoc.v:31674$998_Y - attribute \src "libresoc.v:31676.17-31676.93" - wire $not$libresoc.v:31676$1000_Y - attribute \src "libresoc.v:31679.17-31679.93" - wire $not$libresoc.v:31679$1003_Y - attribute \src "libresoc.v:31673.18-31673.99" - wire $or$libresoc.v:31673$997_Y - attribute \src "libresoc.v:31675.18-31675.100" - wire $or$libresoc.v:31675$999_Y - attribute \src "libresoc.v:31678.17-31678.98" - wire $or$libresoc.v:31678$1002_Y + attribute \src "libresoc.v:31720.17-31720.96" + wire $and$libresoc.v:31720$996_Y + attribute \src "libresoc.v:31725.17-31725.96" + wire $and$libresoc.v:31725$1001_Y + attribute \src "libresoc.v:31722.18-31722.94" + wire $not$libresoc.v:31722$998_Y + attribute \src "libresoc.v:31724.17-31724.93" + wire $not$libresoc.v:31724$1000_Y + attribute \src "libresoc.v:31727.17-31727.93" + wire $not$libresoc.v:31727$1003_Y + attribute \src "libresoc.v:31721.18-31721.99" + wire $or$libresoc.v:31721$997_Y + attribute \src "libresoc.v:31723.18-31723.100" + wire $or$libresoc.v:31723$999_Y + attribute \src "libresoc.v:31726.17-31726.98" + wire $or$libresoc.v:31726$1002_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -45728,11 +45764,11 @@ module \alui_l$106 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:31637.7-31637.15" + attribute \src "libresoc.v:31685.7-31685.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -45749,7 +45785,7 @@ module \alui_l$106 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31672$996 + cell $and $and$libresoc.v:31720$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45757,10 +45793,10 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31672$996_Y + connect \Y $and$libresoc.v:31720$996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31677$1001 + cell $and $and$libresoc.v:31725$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45768,34 +45804,34 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31677$1001_Y + connect \Y $and$libresoc.v:31725$1001_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31674$998 + cell $not $not$libresoc.v:31722$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31674$998_Y + connect \Y $not$libresoc.v:31722$998_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31676$1000 + cell $not $not$libresoc.v:31724$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31676$1000_Y + connect \Y $not$libresoc.v:31724$1000_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31679$1003 + cell $not $not$libresoc.v:31727$1003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31679$1003_Y + connect \Y $not$libresoc.v:31727$1003_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31673$997 + cell $or $or$libresoc.v:31721$997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45803,10 +45839,10 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31673$997_Y + connect \Y $or$libresoc.v:31721$997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31675$999 + cell $or $or$libresoc.v:31723$999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45814,10 +45850,10 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31675$999_Y + connect \Y $or$libresoc.v:31723$999_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31678$1002 + cell $or $or$libresoc.v:31726$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45825,39 +45861,39 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31678$1002_Y + connect \Y $or$libresoc.v:31726$1002_Y end - attribute \src "libresoc.v:31637.7-31637.20" - process $proc$libresoc.v:31637$1008 + attribute \src "libresoc.v:31685.7-31685.20" + process $proc$libresoc.v:31685$1008 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31661.7-31661.19" - process $proc$libresoc.v:31661$1009 + attribute \src "libresoc.v:31709.7-31709.19" + process $proc$libresoc.v:31709$1009 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31680.3-31681.27" - process $proc$libresoc.v:31680$1004 + attribute \src "libresoc.v:31728.3-31729.27" + process $proc$libresoc.v:31728$1004 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31682.3-31690.6" - process $proc$libresoc.v:31682$1005 + attribute \src "libresoc.v:31730.3-31738.6" + process $proc$libresoc.v:31730$1005 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1006 $1\q_int$next[0:0]$1007 - attribute \src "libresoc.v:31683.5-31683.29" + attribute \src "libresoc.v:31731.5-31731.29" switch \initial - attribute \src "libresoc.v:31683.9-31683.17" + attribute \src "libresoc.v:31731.9-31731.17" case 1'1 case end @@ -45873,49 +45909,49 @@ module \alui_l$106 sync always update \q_int$next $0\q_int$next[0:0]$1006 end - connect \$9 $and$libresoc.v:31672$996_Y - connect \$11 $or$libresoc.v:31673$997_Y - connect \$13 $not$libresoc.v:31674$998_Y - connect \$15 $or$libresoc.v:31675$999_Y - connect \$1 $not$libresoc.v:31676$1000_Y - connect \$3 $and$libresoc.v:31677$1001_Y - connect \$5 $or$libresoc.v:31678$1002_Y - connect \$7 $not$libresoc.v:31679$1003_Y + connect \$9 $and$libresoc.v:31720$996_Y + connect \$11 $or$libresoc.v:31721$997_Y + connect \$13 $not$libresoc.v:31722$998_Y + connect \$15 $or$libresoc.v:31723$999_Y + connect \$1 $not$libresoc.v:31724$1000_Y + connect \$3 $and$libresoc.v:31725$1001_Y + connect \$5 $or$libresoc.v:31726$1002_Y + connect \$7 $not$libresoc.v:31727$1003_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31698.1-31756.10" +attribute \src "libresoc.v:31746.1-31804.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alui_l" attribute \generator "nMigen" module \alui_l$124 - attribute \src "libresoc.v:31699.7-31699.20" + attribute \src "libresoc.v:31747.7-31747.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31744.3-31752.6" + attribute \src "libresoc.v:31792.3-31800.6" wire $0\q_int$next[0:0]$1020 - attribute \src "libresoc.v:31742.3-31743.27" + attribute \src "libresoc.v:31790.3-31791.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31744.3-31752.6" + attribute \src "libresoc.v:31792.3-31800.6" wire $1\q_int$next[0:0]$1021 - attribute \src "libresoc.v:31723.7-31723.19" + attribute \src "libresoc.v:31771.7-31771.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31734.17-31734.96" - wire $and$libresoc.v:31734$1010_Y - attribute \src "libresoc.v:31739.17-31739.96" - wire $and$libresoc.v:31739$1015_Y - attribute \src "libresoc.v:31736.18-31736.94" - wire $not$libresoc.v:31736$1012_Y - attribute \src "libresoc.v:31738.17-31738.93" - wire $not$libresoc.v:31738$1014_Y - attribute \src "libresoc.v:31741.17-31741.93" - wire $not$libresoc.v:31741$1017_Y - attribute \src "libresoc.v:31735.18-31735.99" - wire $or$libresoc.v:31735$1011_Y - attribute \src "libresoc.v:31737.18-31737.100" - wire $or$libresoc.v:31737$1013_Y - attribute \src "libresoc.v:31740.17-31740.98" - wire $or$libresoc.v:31740$1016_Y + attribute \src "libresoc.v:31782.17-31782.96" + wire $and$libresoc.v:31782$1010_Y + attribute \src "libresoc.v:31787.17-31787.96" + wire $and$libresoc.v:31787$1015_Y + attribute \src "libresoc.v:31784.18-31784.94" + wire $not$libresoc.v:31784$1012_Y + attribute \src "libresoc.v:31786.17-31786.93" + wire $not$libresoc.v:31786$1014_Y + attribute \src "libresoc.v:31789.17-31789.93" + wire $not$libresoc.v:31789$1017_Y + attribute \src "libresoc.v:31783.18-31783.99" + wire $or$libresoc.v:31783$1011_Y + attribute \src "libresoc.v:31785.18-31785.100" + wire $or$libresoc.v:31785$1013_Y + attribute \src "libresoc.v:31788.17-31788.98" + wire $or$libresoc.v:31788$1016_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -45932,11 +45968,11 @@ module \alui_l$124 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:31699.7-31699.15" + attribute \src "libresoc.v:31747.7-31747.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -45953,7 +45989,7 @@ module \alui_l$124 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31734$1010 + cell $and $and$libresoc.v:31782$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45961,10 +45997,10 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31734$1010_Y + connect \Y $and$libresoc.v:31782$1010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31739$1015 + cell $and $and$libresoc.v:31787$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45972,34 +46008,34 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31739$1015_Y + connect \Y $and$libresoc.v:31787$1015_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31736$1012 + cell $not $not$libresoc.v:31784$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31736$1012_Y + connect \Y $not$libresoc.v:31784$1012_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31738$1014 + cell $not $not$libresoc.v:31786$1014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31738$1014_Y + connect \Y $not$libresoc.v:31786$1014_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31741$1017 + cell $not $not$libresoc.v:31789$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31741$1017_Y + connect \Y $not$libresoc.v:31789$1017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31735$1011 + cell $or $or$libresoc.v:31783$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46007,10 +46043,10 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31735$1011_Y + connect \Y $or$libresoc.v:31783$1011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31737$1013 + cell $or $or$libresoc.v:31785$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46018,10 +46054,10 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31737$1013_Y + connect \Y $or$libresoc.v:31785$1013_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31740$1016 + cell $or $or$libresoc.v:31788$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46029,39 +46065,39 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31740$1016_Y + connect \Y $or$libresoc.v:31788$1016_Y end - attribute \src "libresoc.v:31699.7-31699.20" - process $proc$libresoc.v:31699$1022 + attribute \src "libresoc.v:31747.7-31747.20" + process $proc$libresoc.v:31747$1022 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31723.7-31723.19" - process $proc$libresoc.v:31723$1023 + attribute \src "libresoc.v:31771.7-31771.19" + process $proc$libresoc.v:31771$1023 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31742.3-31743.27" - process $proc$libresoc.v:31742$1018 + attribute \src "libresoc.v:31790.3-31791.27" + process $proc$libresoc.v:31790$1018 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31744.3-31752.6" - process $proc$libresoc.v:31744$1019 + attribute \src "libresoc.v:31792.3-31800.6" + process $proc$libresoc.v:31792$1019 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1020 $1\q_int$next[0:0]$1021 - attribute \src "libresoc.v:31745.5-31745.29" + attribute \src "libresoc.v:31793.5-31793.29" switch \initial - attribute \src "libresoc.v:31745.9-31745.17" + attribute \src "libresoc.v:31793.9-31793.17" case 1'1 case end @@ -46077,49 +46113,49 @@ module \alui_l$124 sync always update \q_int$next $0\q_int$next[0:0]$1020 end - connect \$9 $and$libresoc.v:31734$1010_Y - connect \$11 $or$libresoc.v:31735$1011_Y - connect \$13 $not$libresoc.v:31736$1012_Y - connect \$15 $or$libresoc.v:31737$1013_Y - connect \$1 $not$libresoc.v:31738$1014_Y - connect \$3 $and$libresoc.v:31739$1015_Y - connect \$5 $or$libresoc.v:31740$1016_Y - connect \$7 $not$libresoc.v:31741$1017_Y + connect \$9 $and$libresoc.v:31782$1010_Y + connect \$11 $or$libresoc.v:31783$1011_Y + connect \$13 $not$libresoc.v:31784$1012_Y + connect \$15 $or$libresoc.v:31785$1013_Y + connect \$1 $not$libresoc.v:31786$1014_Y + connect \$3 $and$libresoc.v:31787$1015_Y + connect \$5 $or$libresoc.v:31788$1016_Y + connect \$7 $not$libresoc.v:31789$1017_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31760.1-31818.10" +attribute \src "libresoc.v:31808.1-31866.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alui_l" attribute \generator "nMigen" module \alui_l$15 - attribute \src "libresoc.v:31761.7-31761.20" + attribute \src "libresoc.v:31809.7-31809.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31806.3-31814.6" + attribute \src "libresoc.v:31854.3-31862.6" wire $0\q_int$next[0:0]$1034 - attribute \src "libresoc.v:31804.3-31805.27" + attribute \src "libresoc.v:31852.3-31853.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31806.3-31814.6" + attribute \src "libresoc.v:31854.3-31862.6" wire $1\q_int$next[0:0]$1035 - attribute \src "libresoc.v:31785.7-31785.19" + attribute \src "libresoc.v:31833.7-31833.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31796.17-31796.96" - wire $and$libresoc.v:31796$1024_Y - attribute \src "libresoc.v:31801.17-31801.96" - wire $and$libresoc.v:31801$1029_Y - attribute \src "libresoc.v:31798.18-31798.94" - wire $not$libresoc.v:31798$1026_Y - attribute \src "libresoc.v:31800.17-31800.93" - wire $not$libresoc.v:31800$1028_Y - attribute \src "libresoc.v:31803.17-31803.93" - wire $not$libresoc.v:31803$1031_Y - attribute \src "libresoc.v:31797.18-31797.99" - wire $or$libresoc.v:31797$1025_Y - attribute \src "libresoc.v:31799.18-31799.100" - wire $or$libresoc.v:31799$1027_Y - attribute \src "libresoc.v:31802.17-31802.98" - wire $or$libresoc.v:31802$1030_Y + attribute \src "libresoc.v:31844.17-31844.96" + wire $and$libresoc.v:31844$1024_Y + attribute \src "libresoc.v:31849.17-31849.96" + wire $and$libresoc.v:31849$1029_Y + attribute \src "libresoc.v:31846.18-31846.94" + wire $not$libresoc.v:31846$1026_Y + attribute \src "libresoc.v:31848.17-31848.93" + wire $not$libresoc.v:31848$1028_Y + attribute \src "libresoc.v:31851.17-31851.93" + wire $not$libresoc.v:31851$1031_Y + attribute \src "libresoc.v:31845.18-31845.99" + wire $or$libresoc.v:31845$1025_Y + attribute \src "libresoc.v:31847.18-31847.100" + wire $or$libresoc.v:31847$1027_Y + attribute \src "libresoc.v:31850.17-31850.98" + wire $or$libresoc.v:31850$1030_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46136,11 +46172,11 @@ module \alui_l$15 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:31761.7-31761.15" + attribute \src "libresoc.v:31809.7-31809.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46157,7 +46193,7 @@ module \alui_l$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31796$1024 + cell $and $and$libresoc.v:31844$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46165,10 +46201,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31796$1024_Y + connect \Y $and$libresoc.v:31844$1024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31801$1029 + cell $and $and$libresoc.v:31849$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46176,34 +46212,34 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31801$1029_Y + connect \Y $and$libresoc.v:31849$1029_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31798$1026 + cell $not $not$libresoc.v:31846$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31798$1026_Y + connect \Y $not$libresoc.v:31846$1026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31800$1028 + cell $not $not$libresoc.v:31848$1028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31800$1028_Y + connect \Y $not$libresoc.v:31848$1028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31803$1031 + cell $not $not$libresoc.v:31851$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31803$1031_Y + connect \Y $not$libresoc.v:31851$1031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31797$1025 + cell $or $or$libresoc.v:31845$1025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46211,10 +46247,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31797$1025_Y + connect \Y $or$libresoc.v:31845$1025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31799$1027 + cell $or $or$libresoc.v:31847$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46222,10 +46258,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31799$1027_Y + connect \Y $or$libresoc.v:31847$1027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31802$1030 + cell $or $or$libresoc.v:31850$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46233,39 +46269,39 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31802$1030_Y + connect \Y $or$libresoc.v:31850$1030_Y end - attribute \src "libresoc.v:31761.7-31761.20" - process $proc$libresoc.v:31761$1036 + attribute \src "libresoc.v:31809.7-31809.20" + process $proc$libresoc.v:31809$1036 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31785.7-31785.19" - process $proc$libresoc.v:31785$1037 + attribute \src "libresoc.v:31833.7-31833.19" + process $proc$libresoc.v:31833$1037 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31804.3-31805.27" - process $proc$libresoc.v:31804$1032 + attribute \src "libresoc.v:31852.3-31853.27" + process $proc$libresoc.v:31852$1032 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31806.3-31814.6" - process $proc$libresoc.v:31806$1033 + attribute \src "libresoc.v:31854.3-31862.6" + process $proc$libresoc.v:31854$1033 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1034 $1\q_int$next[0:0]$1035 - attribute \src "libresoc.v:31807.5-31807.29" + attribute \src "libresoc.v:31855.5-31855.29" switch \initial - attribute \src "libresoc.v:31807.9-31807.17" + attribute \src "libresoc.v:31855.9-31855.17" case 1'1 case end @@ -46281,49 +46317,49 @@ module \alui_l$15 sync always update \q_int$next $0\q_int$next[0:0]$1034 end - connect \$9 $and$libresoc.v:31796$1024_Y - connect \$11 $or$libresoc.v:31797$1025_Y - connect \$13 $not$libresoc.v:31798$1026_Y - connect \$15 $or$libresoc.v:31799$1027_Y - connect \$1 $not$libresoc.v:31800$1028_Y - connect \$3 $and$libresoc.v:31801$1029_Y - connect \$5 $or$libresoc.v:31802$1030_Y - connect \$7 $not$libresoc.v:31803$1031_Y + connect \$9 $and$libresoc.v:31844$1024_Y + connect \$11 $or$libresoc.v:31845$1025_Y + connect \$13 $not$libresoc.v:31846$1026_Y + connect \$15 $or$libresoc.v:31847$1027_Y + connect \$1 $not$libresoc.v:31848$1028_Y + connect \$3 $and$libresoc.v:31849$1029_Y + connect \$5 $or$libresoc.v:31850$1030_Y + connect \$7 $not$libresoc.v:31851$1031_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31822.1-31880.10" +attribute \src "libresoc.v:31870.1-31928.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alui_l" attribute \generator "nMigen" module \alui_l$28 - attribute \src "libresoc.v:31823.7-31823.20" + attribute \src "libresoc.v:31871.7-31871.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31868.3-31876.6" + attribute \src "libresoc.v:31916.3-31924.6" wire $0\q_int$next[0:0]$1048 - attribute \src "libresoc.v:31866.3-31867.27" + attribute \src "libresoc.v:31914.3-31915.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31868.3-31876.6" + attribute \src "libresoc.v:31916.3-31924.6" wire $1\q_int$next[0:0]$1049 - attribute \src "libresoc.v:31847.7-31847.19" + attribute \src "libresoc.v:31895.7-31895.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31858.17-31858.96" - wire $and$libresoc.v:31858$1038_Y - attribute \src "libresoc.v:31863.17-31863.96" - wire $and$libresoc.v:31863$1043_Y - attribute \src "libresoc.v:31860.18-31860.94" - wire $not$libresoc.v:31860$1040_Y - attribute \src "libresoc.v:31862.17-31862.93" - wire $not$libresoc.v:31862$1042_Y - attribute \src "libresoc.v:31865.17-31865.93" - wire $not$libresoc.v:31865$1045_Y - attribute \src "libresoc.v:31859.18-31859.99" - wire $or$libresoc.v:31859$1039_Y - attribute \src "libresoc.v:31861.18-31861.100" - wire $or$libresoc.v:31861$1041_Y - attribute \src "libresoc.v:31864.17-31864.98" - wire $or$libresoc.v:31864$1044_Y + attribute \src "libresoc.v:31906.17-31906.96" + wire $and$libresoc.v:31906$1038_Y + attribute \src "libresoc.v:31911.17-31911.96" + wire $and$libresoc.v:31911$1043_Y + attribute \src "libresoc.v:31908.18-31908.94" + wire $not$libresoc.v:31908$1040_Y + attribute \src "libresoc.v:31910.17-31910.93" + wire $not$libresoc.v:31910$1042_Y + attribute \src "libresoc.v:31913.17-31913.93" + wire $not$libresoc.v:31913$1045_Y + attribute \src "libresoc.v:31907.18-31907.99" + wire $or$libresoc.v:31907$1039_Y + attribute \src "libresoc.v:31909.18-31909.100" + wire $or$libresoc.v:31909$1041_Y + attribute \src "libresoc.v:31912.17-31912.98" + wire $or$libresoc.v:31912$1044_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46340,11 +46376,11 @@ module \alui_l$28 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:31823.7-31823.15" + attribute \src "libresoc.v:31871.7-31871.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46361,7 +46397,7 @@ module \alui_l$28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31858$1038 + cell $and $and$libresoc.v:31906$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46369,10 +46405,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31858$1038_Y + connect \Y $and$libresoc.v:31906$1038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31863$1043 + cell $and $and$libresoc.v:31911$1043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46380,34 +46416,34 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31863$1043_Y + connect \Y $and$libresoc.v:31911$1043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31860$1040 + cell $not $not$libresoc.v:31908$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31860$1040_Y + connect \Y $not$libresoc.v:31908$1040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31862$1042 + cell $not $not$libresoc.v:31910$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31862$1042_Y + connect \Y $not$libresoc.v:31910$1042_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31865$1045 + cell $not $not$libresoc.v:31913$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31865$1045_Y + connect \Y $not$libresoc.v:31913$1045_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31859$1039 + cell $or $or$libresoc.v:31907$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46415,10 +46451,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31859$1039_Y + connect \Y $or$libresoc.v:31907$1039_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31861$1041 + cell $or $or$libresoc.v:31909$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46426,10 +46462,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31861$1041_Y + connect \Y $or$libresoc.v:31909$1041_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31864$1044 + cell $or $or$libresoc.v:31912$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46437,39 +46473,39 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31864$1044_Y + connect \Y $or$libresoc.v:31912$1044_Y end - attribute \src "libresoc.v:31823.7-31823.20" - process $proc$libresoc.v:31823$1050 + attribute \src "libresoc.v:31871.7-31871.20" + process $proc$libresoc.v:31871$1050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31847.7-31847.19" - process $proc$libresoc.v:31847$1051 + attribute \src "libresoc.v:31895.7-31895.19" + process $proc$libresoc.v:31895$1051 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31866.3-31867.27" - process $proc$libresoc.v:31866$1046 + attribute \src "libresoc.v:31914.3-31915.27" + process $proc$libresoc.v:31914$1046 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31868.3-31876.6" - process $proc$libresoc.v:31868$1047 + attribute \src "libresoc.v:31916.3-31924.6" + process $proc$libresoc.v:31916$1047 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1048 $1\q_int$next[0:0]$1049 - attribute \src "libresoc.v:31869.5-31869.29" + attribute \src "libresoc.v:31917.5-31917.29" switch \initial - attribute \src "libresoc.v:31869.9-31869.17" + attribute \src "libresoc.v:31917.9-31917.17" case 1'1 case end @@ -46485,49 +46521,49 @@ module \alui_l$28 sync always update \q_int$next $0\q_int$next[0:0]$1048 end - connect \$9 $and$libresoc.v:31858$1038_Y - connect \$11 $or$libresoc.v:31859$1039_Y - connect \$13 $not$libresoc.v:31860$1040_Y - connect \$15 $or$libresoc.v:31861$1041_Y - connect \$1 $not$libresoc.v:31862$1042_Y - connect \$3 $and$libresoc.v:31863$1043_Y - connect \$5 $or$libresoc.v:31864$1044_Y - connect \$7 $not$libresoc.v:31865$1045_Y + connect \$9 $and$libresoc.v:31906$1038_Y + connect \$11 $or$libresoc.v:31907$1039_Y + connect \$13 $not$libresoc.v:31908$1040_Y + connect \$15 $or$libresoc.v:31909$1041_Y + connect \$1 $not$libresoc.v:31910$1042_Y + connect \$3 $and$libresoc.v:31911$1043_Y + connect \$5 $or$libresoc.v:31912$1044_Y + connect \$7 $not$libresoc.v:31913$1045_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31884.1-31942.10" +attribute \src "libresoc.v:31932.1-31990.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alui_l" attribute \generator "nMigen" module \alui_l$44 - attribute \src "libresoc.v:31885.7-31885.20" + attribute \src "libresoc.v:31933.7-31933.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31930.3-31938.6" + attribute \src "libresoc.v:31978.3-31986.6" wire $0\q_int$next[0:0]$1062 - attribute \src "libresoc.v:31928.3-31929.27" + attribute \src "libresoc.v:31976.3-31977.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31930.3-31938.6" + attribute \src "libresoc.v:31978.3-31986.6" wire $1\q_int$next[0:0]$1063 - attribute \src "libresoc.v:31909.7-31909.19" + attribute \src "libresoc.v:31957.7-31957.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31920.17-31920.96" - wire $and$libresoc.v:31920$1052_Y - attribute \src "libresoc.v:31925.17-31925.96" - wire $and$libresoc.v:31925$1057_Y - attribute \src "libresoc.v:31922.18-31922.94" - wire $not$libresoc.v:31922$1054_Y - attribute \src "libresoc.v:31924.17-31924.93" - wire $not$libresoc.v:31924$1056_Y - attribute \src "libresoc.v:31927.17-31927.93" - wire $not$libresoc.v:31927$1059_Y - attribute \src "libresoc.v:31921.18-31921.99" - wire $or$libresoc.v:31921$1053_Y - attribute \src "libresoc.v:31923.18-31923.100" - wire $or$libresoc.v:31923$1055_Y - attribute \src "libresoc.v:31926.17-31926.98" - wire $or$libresoc.v:31926$1058_Y + attribute \src "libresoc.v:31968.17-31968.96" + wire $and$libresoc.v:31968$1052_Y + attribute \src "libresoc.v:31973.17-31973.96" + wire $and$libresoc.v:31973$1057_Y + attribute \src "libresoc.v:31970.18-31970.94" + wire $not$libresoc.v:31970$1054_Y + attribute \src "libresoc.v:31972.17-31972.93" + wire $not$libresoc.v:31972$1056_Y + attribute \src "libresoc.v:31975.17-31975.93" + wire $not$libresoc.v:31975$1059_Y + attribute \src "libresoc.v:31969.18-31969.99" + wire $or$libresoc.v:31969$1053_Y + attribute \src "libresoc.v:31971.18-31971.100" + wire $or$libresoc.v:31971$1055_Y + attribute \src "libresoc.v:31974.17-31974.98" + wire $or$libresoc.v:31974$1058_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46544,11 +46580,11 @@ module \alui_l$44 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:31885.7-31885.15" + attribute \src "libresoc.v:31933.7-31933.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46565,7 +46601,7 @@ module \alui_l$44 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31920$1052 + cell $and $and$libresoc.v:31968$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46573,10 +46609,10 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31920$1052_Y + connect \Y $and$libresoc.v:31968$1052_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31925$1057 + cell $and $and$libresoc.v:31973$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46584,34 +46620,34 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31925$1057_Y + connect \Y $and$libresoc.v:31973$1057_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31922$1054 + cell $not $not$libresoc.v:31970$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31922$1054_Y + connect \Y $not$libresoc.v:31970$1054_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31924$1056 + cell $not $not$libresoc.v:31972$1056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31924$1056_Y + connect \Y $not$libresoc.v:31972$1056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31927$1059 + cell $not $not$libresoc.v:31975$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31927$1059_Y + connect \Y $not$libresoc.v:31975$1059_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31921$1053 + cell $or $or$libresoc.v:31969$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46619,10 +46655,10 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31921$1053_Y + connect \Y $or$libresoc.v:31969$1053_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31923$1055 + cell $or $or$libresoc.v:31971$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46630,10 +46666,10 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31923$1055_Y + connect \Y $or$libresoc.v:31971$1055_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31926$1058 + cell $or $or$libresoc.v:31974$1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46641,39 +46677,39 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31926$1058_Y + connect \Y $or$libresoc.v:31974$1058_Y end - attribute \src "libresoc.v:31885.7-31885.20" - process $proc$libresoc.v:31885$1064 + attribute \src "libresoc.v:31933.7-31933.20" + process $proc$libresoc.v:31933$1064 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31909.7-31909.19" - process $proc$libresoc.v:31909$1065 + attribute \src "libresoc.v:31957.7-31957.19" + process $proc$libresoc.v:31957$1065 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31928.3-31929.27" - process $proc$libresoc.v:31928$1060 + attribute \src "libresoc.v:31976.3-31977.27" + process $proc$libresoc.v:31976$1060 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31930.3-31938.6" - process $proc$libresoc.v:31930$1061 + attribute \src "libresoc.v:31978.3-31986.6" + process $proc$libresoc.v:31978$1061 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1062 $1\q_int$next[0:0]$1063 - attribute \src "libresoc.v:31931.5-31931.29" + attribute \src "libresoc.v:31979.5-31979.29" switch \initial - attribute \src "libresoc.v:31931.9-31931.17" + attribute \src "libresoc.v:31979.9-31979.17" case 1'1 case end @@ -46689,49 +46725,49 @@ module \alui_l$44 sync always update \q_int$next $0\q_int$next[0:0]$1062 end - connect \$9 $and$libresoc.v:31920$1052_Y - connect \$11 $or$libresoc.v:31921$1053_Y - connect \$13 $not$libresoc.v:31922$1054_Y - connect \$15 $or$libresoc.v:31923$1055_Y - connect \$1 $not$libresoc.v:31924$1056_Y - connect \$3 $and$libresoc.v:31925$1057_Y - connect \$5 $or$libresoc.v:31926$1058_Y - connect \$7 $not$libresoc.v:31927$1059_Y + connect \$9 $and$libresoc.v:31968$1052_Y + connect \$11 $or$libresoc.v:31969$1053_Y + connect \$13 $not$libresoc.v:31970$1054_Y + connect \$15 $or$libresoc.v:31971$1055_Y + connect \$1 $not$libresoc.v:31972$1056_Y + connect \$3 $and$libresoc.v:31973$1057_Y + connect \$5 $or$libresoc.v:31974$1058_Y + connect \$7 $not$libresoc.v:31975$1059_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31946.1-32004.10" +attribute \src "libresoc.v:31994.1-32052.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alui_l" attribute \generator "nMigen" module \alui_l$60 - attribute \src "libresoc.v:31947.7-31947.20" + attribute \src "libresoc.v:31995.7-31995.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31992.3-32000.6" + attribute \src "libresoc.v:32040.3-32048.6" wire $0\q_int$next[0:0]$1076 - attribute \src "libresoc.v:31990.3-31991.27" + attribute \src "libresoc.v:32038.3-32039.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31992.3-32000.6" + attribute \src "libresoc.v:32040.3-32048.6" wire $1\q_int$next[0:0]$1077 - attribute \src "libresoc.v:31971.7-31971.19" + attribute \src "libresoc.v:32019.7-32019.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31982.17-31982.96" - wire $and$libresoc.v:31982$1066_Y - attribute \src "libresoc.v:31987.17-31987.96" - wire $and$libresoc.v:31987$1071_Y - attribute \src "libresoc.v:31984.18-31984.94" - wire $not$libresoc.v:31984$1068_Y - attribute \src "libresoc.v:31986.17-31986.93" - wire $not$libresoc.v:31986$1070_Y - attribute \src "libresoc.v:31989.17-31989.93" - wire $not$libresoc.v:31989$1073_Y - attribute \src "libresoc.v:31983.18-31983.99" - wire $or$libresoc.v:31983$1067_Y - attribute \src "libresoc.v:31985.18-31985.100" - wire $or$libresoc.v:31985$1069_Y - attribute \src "libresoc.v:31988.17-31988.98" - wire $or$libresoc.v:31988$1072_Y + attribute \src "libresoc.v:32030.17-32030.96" + wire $and$libresoc.v:32030$1066_Y + attribute \src "libresoc.v:32035.17-32035.96" + wire $and$libresoc.v:32035$1071_Y + attribute \src "libresoc.v:32032.18-32032.94" + wire $not$libresoc.v:32032$1068_Y + attribute \src "libresoc.v:32034.17-32034.93" + wire $not$libresoc.v:32034$1070_Y + attribute \src "libresoc.v:32037.17-32037.93" + wire $not$libresoc.v:32037$1073_Y + attribute \src "libresoc.v:32031.18-32031.99" + wire $or$libresoc.v:32031$1067_Y + attribute \src "libresoc.v:32033.18-32033.100" + wire $or$libresoc.v:32033$1069_Y + attribute \src "libresoc.v:32036.17-32036.98" + wire $or$libresoc.v:32036$1072_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46748,11 +46784,11 @@ module \alui_l$60 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:31947.7-31947.15" + attribute \src "libresoc.v:31995.7-31995.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46769,7 +46805,7 @@ module \alui_l$60 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31982$1066 + cell $and $and$libresoc.v:32030$1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46777,10 +46813,10 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31982$1066_Y + connect \Y $and$libresoc.v:32030$1066_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31987$1071 + cell $and $and$libresoc.v:32035$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46788,34 +46824,34 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31987$1071_Y + connect \Y $and$libresoc.v:32035$1071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31984$1068 + cell $not $not$libresoc.v:32032$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31984$1068_Y + connect \Y $not$libresoc.v:32032$1068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31986$1070 + cell $not $not$libresoc.v:32034$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31986$1070_Y + connect \Y $not$libresoc.v:32034$1070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31989$1073 + cell $not $not$libresoc.v:32037$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31989$1073_Y + connect \Y $not$libresoc.v:32037$1073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31983$1067 + cell $or $or$libresoc.v:32031$1067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46823,10 +46859,10 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31983$1067_Y + connect \Y $or$libresoc.v:32031$1067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31985$1069 + cell $or $or$libresoc.v:32033$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46834,10 +46870,10 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31985$1069_Y + connect \Y $or$libresoc.v:32033$1069_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31988$1072 + cell $or $or$libresoc.v:32036$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46845,39 +46881,39 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31988$1072_Y + connect \Y $or$libresoc.v:32036$1072_Y end - attribute \src "libresoc.v:31947.7-31947.20" - process $proc$libresoc.v:31947$1078 + attribute \src "libresoc.v:31995.7-31995.20" + process $proc$libresoc.v:31995$1078 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31971.7-31971.19" - process $proc$libresoc.v:31971$1079 + attribute \src "libresoc.v:32019.7-32019.19" + process $proc$libresoc.v:32019$1079 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31990.3-31991.27" - process $proc$libresoc.v:31990$1074 + attribute \src "libresoc.v:32038.3-32039.27" + process $proc$libresoc.v:32038$1074 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31992.3-32000.6" - process $proc$libresoc.v:31992$1075 + attribute \src "libresoc.v:32040.3-32048.6" + process $proc$libresoc.v:32040$1075 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1076 $1\q_int$next[0:0]$1077 - attribute \src "libresoc.v:31993.5-31993.29" + attribute \src "libresoc.v:32041.5-32041.29" switch \initial - attribute \src "libresoc.v:31993.9-31993.17" + attribute \src "libresoc.v:32041.9-32041.17" case 1'1 case end @@ -46893,49 +46929,49 @@ module \alui_l$60 sync always update \q_int$next $0\q_int$next[0:0]$1076 end - connect \$9 $and$libresoc.v:31982$1066_Y - connect \$11 $or$libresoc.v:31983$1067_Y - connect \$13 $not$libresoc.v:31984$1068_Y - connect \$15 $or$libresoc.v:31985$1069_Y - connect \$1 $not$libresoc.v:31986$1070_Y - connect \$3 $and$libresoc.v:31987$1071_Y - connect \$5 $or$libresoc.v:31988$1072_Y - connect \$7 $not$libresoc.v:31989$1073_Y + connect \$9 $and$libresoc.v:32030$1066_Y + connect \$11 $or$libresoc.v:32031$1067_Y + connect \$13 $not$libresoc.v:32032$1068_Y + connect \$15 $or$libresoc.v:32033$1069_Y + connect \$1 $not$libresoc.v:32034$1070_Y + connect \$3 $and$libresoc.v:32035$1071_Y + connect \$5 $or$libresoc.v:32036$1072_Y + connect \$7 $not$libresoc.v:32037$1073_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:32008.1-32066.10" +attribute \src "libresoc.v:32056.1-32114.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alui_l" attribute \generator "nMigen" module \alui_l$72 - attribute \src "libresoc.v:32009.7-32009.20" + attribute \src "libresoc.v:32057.7-32057.20" wire $0\initial[0:0] - attribute \src "libresoc.v:32054.3-32062.6" + attribute \src "libresoc.v:32102.3-32110.6" wire $0\q_int$next[0:0]$1090 - attribute \src "libresoc.v:32052.3-32053.27" + attribute \src "libresoc.v:32100.3-32101.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:32054.3-32062.6" + attribute \src "libresoc.v:32102.3-32110.6" wire $1\q_int$next[0:0]$1091 - attribute \src "libresoc.v:32033.7-32033.19" + attribute \src "libresoc.v:32081.7-32081.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:32044.17-32044.96" - wire $and$libresoc.v:32044$1080_Y - attribute \src "libresoc.v:32049.17-32049.96" - wire $and$libresoc.v:32049$1085_Y - attribute \src "libresoc.v:32046.18-32046.94" - wire $not$libresoc.v:32046$1082_Y - attribute \src "libresoc.v:32048.17-32048.93" - wire $not$libresoc.v:32048$1084_Y - attribute \src "libresoc.v:32051.17-32051.93" - wire $not$libresoc.v:32051$1087_Y - attribute \src "libresoc.v:32045.18-32045.99" - wire $or$libresoc.v:32045$1081_Y - attribute \src "libresoc.v:32047.18-32047.100" - wire $or$libresoc.v:32047$1083_Y - attribute \src "libresoc.v:32050.17-32050.98" - wire $or$libresoc.v:32050$1086_Y + attribute \src "libresoc.v:32092.17-32092.96" + wire $and$libresoc.v:32092$1080_Y + attribute \src "libresoc.v:32097.17-32097.96" + wire $and$libresoc.v:32097$1085_Y + attribute \src "libresoc.v:32094.18-32094.94" + wire $not$libresoc.v:32094$1082_Y + attribute \src "libresoc.v:32096.17-32096.93" + wire $not$libresoc.v:32096$1084_Y + attribute \src "libresoc.v:32099.17-32099.93" + wire $not$libresoc.v:32099$1087_Y + attribute \src "libresoc.v:32093.18-32093.99" + wire $or$libresoc.v:32093$1081_Y + attribute \src "libresoc.v:32095.18-32095.100" + wire $or$libresoc.v:32095$1083_Y + attribute \src "libresoc.v:32098.17-32098.98" + wire $or$libresoc.v:32098$1086_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46952,11 +46988,11 @@ module \alui_l$72 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:32009.7-32009.15" + attribute \src "libresoc.v:32057.7-32057.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46973,7 +47009,7 @@ module \alui_l$72 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:32044$1080 + cell $and $and$libresoc.v:32092$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46981,10 +47017,10 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:32044$1080_Y + connect \Y $and$libresoc.v:32092$1080_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:32049$1085 + cell $and $and$libresoc.v:32097$1085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46992,34 +47028,34 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:32049$1085_Y + connect \Y $and$libresoc.v:32097$1085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:32046$1082 + cell $not $not$libresoc.v:32094$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:32046$1082_Y + connect \Y $not$libresoc.v:32094$1082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:32048$1084 + cell $not $not$libresoc.v:32096$1084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:32048$1084_Y + connect \Y $not$libresoc.v:32096$1084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:32051$1087 + cell $not $not$libresoc.v:32099$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:32051$1087_Y + connect \Y $not$libresoc.v:32099$1087_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:32045$1081 + cell $or $or$libresoc.v:32093$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47027,10 +47063,10 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:32045$1081_Y + connect \Y $or$libresoc.v:32093$1081_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:32047$1083 + cell $or $or$libresoc.v:32095$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47038,10 +47074,10 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:32047$1083_Y + connect \Y $or$libresoc.v:32095$1083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:32050$1086 + cell $or $or$libresoc.v:32098$1086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47049,39 +47085,39 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:32050$1086_Y + connect \Y $or$libresoc.v:32098$1086_Y end - attribute \src "libresoc.v:32009.7-32009.20" - process $proc$libresoc.v:32009$1092 + attribute \src "libresoc.v:32057.7-32057.20" + process $proc$libresoc.v:32057$1092 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:32033.7-32033.19" - process $proc$libresoc.v:32033$1093 + attribute \src "libresoc.v:32081.7-32081.19" + process $proc$libresoc.v:32081$1093 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:32052.3-32053.27" - process $proc$libresoc.v:32052$1088 + attribute \src "libresoc.v:32100.3-32101.27" + process $proc$libresoc.v:32100$1088 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:32054.3-32062.6" - process $proc$libresoc.v:32054$1089 + attribute \src "libresoc.v:32102.3-32110.6" + process $proc$libresoc.v:32102$1089 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1090 $1\q_int$next[0:0]$1091 - attribute \src "libresoc.v:32055.5-32055.29" + attribute \src "libresoc.v:32103.5-32103.29" switch \initial - attribute \src "libresoc.v:32055.9-32055.17" + attribute \src "libresoc.v:32103.9-32103.17" case 1'1 case end @@ -47097,49 +47133,49 @@ module \alui_l$72 sync always update \q_int$next $0\q_int$next[0:0]$1090 end - connect \$9 $and$libresoc.v:32044$1080_Y - connect \$11 $or$libresoc.v:32045$1081_Y - connect \$13 $not$libresoc.v:32046$1082_Y - connect \$15 $or$libresoc.v:32047$1083_Y - connect \$1 $not$libresoc.v:32048$1084_Y - connect \$3 $and$libresoc.v:32049$1085_Y - connect \$5 $or$libresoc.v:32050$1086_Y - connect \$7 $not$libresoc.v:32051$1087_Y + connect \$9 $and$libresoc.v:32092$1080_Y + connect \$11 $or$libresoc.v:32093$1081_Y + connect \$13 $not$libresoc.v:32094$1082_Y + connect \$15 $or$libresoc.v:32095$1083_Y + connect \$1 $not$libresoc.v:32096$1084_Y + connect \$3 $and$libresoc.v:32097$1085_Y + connect \$5 $or$libresoc.v:32098$1086_Y + connect \$7 $not$libresoc.v:32099$1087_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:32070.1-32128.10" +attribute \src "libresoc.v:32118.1-32176.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alui_l" attribute \generator "nMigen" module \alui_l$89 - attribute \src "libresoc.v:32071.7-32071.20" + attribute \src "libresoc.v:32119.7-32119.20" wire $0\initial[0:0] - attribute \src "libresoc.v:32116.3-32124.6" + attribute \src "libresoc.v:32164.3-32172.6" wire $0\q_int$next[0:0]$1104 - attribute \src "libresoc.v:32114.3-32115.27" + attribute \src "libresoc.v:32162.3-32163.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:32116.3-32124.6" + attribute \src "libresoc.v:32164.3-32172.6" wire $1\q_int$next[0:0]$1105 - attribute \src "libresoc.v:32095.7-32095.19" + attribute \src "libresoc.v:32143.7-32143.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:32106.17-32106.96" - wire $and$libresoc.v:32106$1094_Y - attribute \src "libresoc.v:32111.17-32111.96" - wire $and$libresoc.v:32111$1099_Y - attribute \src "libresoc.v:32108.18-32108.94" - wire $not$libresoc.v:32108$1096_Y - attribute \src "libresoc.v:32110.17-32110.93" - wire $not$libresoc.v:32110$1098_Y - attribute \src "libresoc.v:32113.17-32113.93" - wire $not$libresoc.v:32113$1101_Y - attribute \src "libresoc.v:32107.18-32107.99" - wire $or$libresoc.v:32107$1095_Y - attribute \src "libresoc.v:32109.18-32109.100" - wire $or$libresoc.v:32109$1097_Y - attribute \src "libresoc.v:32112.17-32112.98" - wire $or$libresoc.v:32112$1100_Y + attribute \src "libresoc.v:32154.17-32154.96" + wire $and$libresoc.v:32154$1094_Y + attribute \src "libresoc.v:32159.17-32159.96" + wire $and$libresoc.v:32159$1099_Y + attribute \src "libresoc.v:32156.18-32156.94" + wire $not$libresoc.v:32156$1096_Y + attribute \src "libresoc.v:32158.17-32158.93" + wire $not$libresoc.v:32158$1098_Y + attribute \src "libresoc.v:32161.17-32161.93" + wire $not$libresoc.v:32161$1101_Y + attribute \src "libresoc.v:32155.18-32155.99" + wire $or$libresoc.v:32155$1095_Y + attribute \src "libresoc.v:32157.18-32157.100" + wire $or$libresoc.v:32157$1097_Y + attribute \src "libresoc.v:32160.17-32160.98" + wire $or$libresoc.v:32160$1100_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -47156,11 +47192,11 @@ module \alui_l$89 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:32071.7-32071.15" + attribute \src "libresoc.v:32119.7-32119.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -47177,7 +47213,7 @@ module \alui_l$89 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:32106$1094 + cell $and $and$libresoc.v:32154$1094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47185,10 +47221,10 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:32106$1094_Y + connect \Y $and$libresoc.v:32154$1094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:32111$1099 + cell $and $and$libresoc.v:32159$1099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47196,34 +47232,34 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:32111$1099_Y + connect \Y $and$libresoc.v:32159$1099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:32108$1096 + cell $not $not$libresoc.v:32156$1096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:32108$1096_Y + connect \Y $not$libresoc.v:32156$1096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:32110$1098 + cell $not $not$libresoc.v:32158$1098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:32110$1098_Y + connect \Y $not$libresoc.v:32158$1098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:32113$1101 + cell $not $not$libresoc.v:32161$1101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:32113$1101_Y + connect \Y $not$libresoc.v:32161$1101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:32107$1095 + cell $or $or$libresoc.v:32155$1095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47231,10 +47267,10 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:32107$1095_Y + connect \Y $or$libresoc.v:32155$1095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:32109$1097 + cell $or $or$libresoc.v:32157$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47242,10 +47278,10 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:32109$1097_Y + connect \Y $or$libresoc.v:32157$1097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:32112$1100 + cell $or $or$libresoc.v:32160$1100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47253,39 +47289,39 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:32112$1100_Y + connect \Y $or$libresoc.v:32160$1100_Y end - attribute \src "libresoc.v:32071.7-32071.20" - process $proc$libresoc.v:32071$1106 + attribute \src "libresoc.v:32119.7-32119.20" + process $proc$libresoc.v:32119$1106 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:32095.7-32095.19" - process $proc$libresoc.v:32095$1107 + attribute \src "libresoc.v:32143.7-32143.19" + process $proc$libresoc.v:32143$1107 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:32114.3-32115.27" - process $proc$libresoc.v:32114$1102 + attribute \src "libresoc.v:32162.3-32163.27" + process $proc$libresoc.v:32162$1102 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:32116.3-32124.6" - process $proc$libresoc.v:32116$1103 + attribute \src "libresoc.v:32164.3-32172.6" + process $proc$libresoc.v:32164$1103 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1104 $1\q_int$next[0:0]$1105 - attribute \src "libresoc.v:32117.5-32117.29" + attribute \src "libresoc.v:32165.5-32165.29" switch \initial - attribute \src "libresoc.v:32117.9-32117.17" + attribute \src "libresoc.v:32165.9-32165.17" case 1'1 case end @@ -47301,75 +47337,75 @@ module \alui_l$89 sync always update \q_int$next $0\q_int$next[0:0]$1104 end - connect \$9 $and$libresoc.v:32106$1094_Y - connect \$11 $or$libresoc.v:32107$1095_Y - connect \$13 $not$libresoc.v:32108$1096_Y - connect \$15 $or$libresoc.v:32109$1097_Y - connect \$1 $not$libresoc.v:32110$1098_Y - connect \$3 $and$libresoc.v:32111$1099_Y - connect \$5 $or$libresoc.v:32112$1100_Y - connect \$7 $not$libresoc.v:32113$1101_Y + connect \$9 $and$libresoc.v:32154$1094_Y + connect \$11 $or$libresoc.v:32155$1095_Y + connect \$13 $not$libresoc.v:32156$1096_Y + connect \$15 $or$libresoc.v:32157$1097_Y + connect \$1 $not$libresoc.v:32158$1098_Y + connect \$3 $and$libresoc.v:32159$1099_Y + connect \$5 $or$libresoc.v:32160$1100_Y + connect \$7 $not$libresoc.v:32161$1101_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:32132.1-33476.10" +attribute \src "libresoc.v:32180.1-33524.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" attribute \generator "nMigen" module \bpermd - attribute \src "libresoc.v:32133.7-32133.20" + attribute \src "libresoc.v:32181.7-32181.20" wire $0\initial[0:0] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire width 64 $0\perm[63:0] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $10\perm[4:4] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $11\perm[5:5] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $12\perm[5:5] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $13\perm[6:6] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $14\perm[6:6] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $15\perm[7:7] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $16\perm[7:7] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $1\perm[0:0] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $2\perm[0:0] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $3\perm[1:1] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $4\perm[1:1] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $5\perm[2:2] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $6\perm[2:2] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $7\perm[3:3] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $8\perm[3:3] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $9\perm[4:4] - attribute \src "libresoc.v:32302.17-32302.104" - wire $lt$libresoc.v:32302$1108_Y - attribute \src "libresoc.v:32303.18-32303.105" - wire $lt$libresoc.v:32303$1109_Y - attribute \src "libresoc.v:32304.18-32304.105" - wire $lt$libresoc.v:32304$1110_Y - attribute \src "libresoc.v:32305.18-32305.105" - wire $lt$libresoc.v:32305$1111_Y - attribute \src "libresoc.v:32306.17-32306.104" - wire $lt$libresoc.v:32306$1112_Y - attribute \src "libresoc.v:32307.17-32307.104" - wire $lt$libresoc.v:32307$1113_Y - attribute \src "libresoc.v:32308.17-32308.104" - wire $lt$libresoc.v:32308$1114_Y - attribute \src "libresoc.v:32309.17-32309.104" - wire $lt$libresoc.v:32309$1115_Y + attribute \src "libresoc.v:32350.17-32350.104" + wire $lt$libresoc.v:32350$1108_Y + attribute \src "libresoc.v:32351.18-32351.105" + wire $lt$libresoc.v:32351$1109_Y + attribute \src "libresoc.v:32352.18-32352.105" + wire $lt$libresoc.v:32352$1110_Y + attribute \src "libresoc.v:32353.18-32353.105" + wire $lt$libresoc.v:32353$1111_Y + attribute \src "libresoc.v:32354.17-32354.104" + wire $lt$libresoc.v:32354$1112_Y + attribute \src "libresoc.v:32355.17-32355.104" + wire $lt$libresoc.v:32355$1113_Y + attribute \src "libresoc.v:32356.17-32356.104" + wire $lt$libresoc.v:32356$1114_Y + attribute \src "libresoc.v:32357.17-32357.104" + wire $lt$libresoc.v:32357$1115_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" @@ -47402,7 +47438,7 @@ module \bpermd wire width 8 \idx_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" wire width 8 \idx_7 - attribute \src "libresoc.v:32133.7-32133.15" + attribute \src "libresoc.v:32181.7-32181.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" wire width 64 \perm @@ -47541,7 +47577,7 @@ module \bpermd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" wire width 64 input 3 \rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32302$1108 + cell $lt $lt$libresoc.v:32350$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47549,10 +47585,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_4 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32302$1108_Y + connect \Y $lt$libresoc.v:32350$1108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32303$1109 + cell $lt $lt$libresoc.v:32351$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47560,10 +47596,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_5 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32303$1109_Y + connect \Y $lt$libresoc.v:32351$1109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32304$1110 + cell $lt $lt$libresoc.v:32352$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47571,10 +47607,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_6 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32304$1110_Y + connect \Y $lt$libresoc.v:32352$1110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32305$1111 + cell $lt $lt$libresoc.v:32353$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47582,10 +47618,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_7 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32305$1111_Y + connect \Y $lt$libresoc.v:32353$1111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32306$1112 + cell $lt $lt$libresoc.v:32354$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47593,10 +47629,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_0 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32306$1112_Y + connect \Y $lt$libresoc.v:32354$1112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32307$1113 + cell $lt $lt$libresoc.v:32355$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47604,10 +47640,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_1 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32307$1113_Y + connect \Y $lt$libresoc.v:32355$1113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32308$1114 + cell $lt $lt$libresoc.v:32356$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47615,10 +47651,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_2 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32308$1114_Y + connect \Y $lt$libresoc.v:32356$1114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32309$1115 + cell $lt $lt$libresoc.v:32357$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47626,18 +47662,18 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_3 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32309$1115_Y + connect \Y $lt$libresoc.v:32357$1115_Y end - attribute \src "libresoc.v:32133.7-32133.20" - process $proc$libresoc.v:32133$1117 + attribute \src "libresoc.v:32181.7-32181.20" + process $proc$libresoc.v:32181$1117 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:32310.3-33401.6" - process $proc$libresoc.v:32310$1116 + attribute \src "libresoc.v:32358.3-33449.6" + process $proc$libresoc.v:32358$1116 assign { } { } assign $0\perm[63:0] [63:8] 56'00000000000000000000000000000000000000000000000000000000 assign $0\perm[63:0] [0] $1\perm[0:0] @@ -47648,9 +47684,9 @@ module \bpermd assign $0\perm[63:0] [5] $11\perm[5:5] assign $0\perm[63:0] [6] $13\perm[6:6] assign $0\perm[63:0] [7] $15\perm[7:7] - attribute \src "libresoc.v:32311.5-32311.29" + attribute \src "libresoc.v:32359.5-32359.29" switch \initial - attribute \src "libresoc.v:32311.9-32311.17" + attribute \src "libresoc.v:32359.9-32359.17" case 1'1 case end @@ -49817,14 +49853,14 @@ module \bpermd sync always update \perm $0\perm[63:0] end - connect \$9 $lt$libresoc.v:32302$1108_Y - connect \$11 $lt$libresoc.v:32303$1109_Y - connect \$13 $lt$libresoc.v:32304$1110_Y - connect \$15 $lt$libresoc.v:32305$1111_Y - connect \$1 $lt$libresoc.v:32306$1112_Y - connect \$3 $lt$libresoc.v:32307$1113_Y - connect \$5 $lt$libresoc.v:32308$1114_Y - connect \$7 $lt$libresoc.v:32309$1115_Y + connect \$9 $lt$libresoc.v:32350$1108_Y + connect \$11 $lt$libresoc.v:32351$1109_Y + connect \$13 $lt$libresoc.v:32352$1110_Y + connect \$15 $lt$libresoc.v:32353$1111_Y + connect \$1 $lt$libresoc.v:32354$1112_Y + connect \$3 $lt$libresoc.v:32355$1113_Y + connect \$5 $lt$libresoc.v:32356$1114_Y + connect \$7 $lt$libresoc.v:32357$1115_Y connect \ra [7:0] \perm [7:0] connect \ra [63:8] 56'00000000000000000000000000000000000000000000000000000000 connect \idx_7 \rs [63:56] @@ -49900,413 +49936,413 @@ module \bpermd connect \rb64_1 \rb [62] connect \rb64_0 \rb [63] end -attribute \src "libresoc.v:33480.1-34535.10" +attribute \src "libresoc.v:33528.1-34583.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0" attribute \generator "nMigen" module \branch0 - attribute \src "libresoc.v:34152.3-34153.25" + attribute \src "libresoc.v:34200.3-34201.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $0\alu_branch0_br_op__cia$next[63:0]$1239 - attribute \src "libresoc.v:34112.3-34113.61" + attribute \src "libresoc.v:34160.3-34161.61" wire width 64 $0\alu_branch0_br_op__cia[63:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 14 $0\alu_branch0_br_op__fn_unit$next[13:0]$1240 - attribute \src "libresoc.v:34116.3-34117.69" + attribute \src "libresoc.v:34164.3-34165.69" wire width 14 $0\alu_branch0_br_op__fn_unit[13:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 - attribute \src "libresoc.v:34120.3-34121.83" + attribute \src "libresoc.v:34168.3-34169.83" wire width 64 $0\alu_branch0_br_op__imm_data__data[63:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 - attribute \src "libresoc.v:34122.3-34123.79" + attribute \src "libresoc.v:34170.3-34171.79" wire $0\alu_branch0_br_op__imm_data__ok[0:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 32 $0\alu_branch0_br_op__insn$next[31:0]$1243 - attribute \src "libresoc.v:34118.3-34119.63" + attribute \src "libresoc.v:34166.3-34167.63" wire width 32 $0\alu_branch0_br_op__insn[31:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 7 $0\alu_branch0_br_op__insn_type$next[6:0]$1244 - attribute \src "libresoc.v:34114.3-34115.73" + attribute \src "libresoc.v:34162.3-34163.73" wire width 7 $0\alu_branch0_br_op__insn_type[6:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 - attribute \src "libresoc.v:34126.3-34127.71" + attribute \src "libresoc.v:34174.3-34175.71" wire $0\alu_branch0_br_op__is_32bit[0:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire $0\alu_branch0_br_op__lk$next[0:0]$1246 - attribute \src "libresoc.v:34124.3-34125.59" + attribute \src "libresoc.v:34172.3-34173.59" wire $0\alu_branch0_br_op__lk[0:0] - attribute \src "libresoc.v:34150.3-34151.43" + attribute \src "libresoc.v:34198.3-34199.43" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:34457.3-34465.6" + attribute \src "libresoc.v:34505.3-34513.6" wire $0\alu_l_r_alu$next[0:0]$1294 - attribute \src "libresoc.v:34090.3-34091.39" + attribute \src "libresoc.v:34138.3-34139.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:34448.3-34456.6" + attribute \src "libresoc.v:34496.3-34504.6" wire $0\alui_l_r_alui$next[0:0]$1291 - attribute \src "libresoc.v:34092.3-34093.43" + attribute \src "libresoc.v:34140.3-34141.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:34352.3-34373.6" + attribute \src "libresoc.v:34400.3-34421.6" wire width 64 $0\data_r0__fast1$next[63:0]$1258 - attribute \src "libresoc.v:34108.3-34109.45" + attribute \src "libresoc.v:34156.3-34157.45" wire width 64 $0\data_r0__fast1[63:0] - attribute \src "libresoc.v:34352.3-34373.6" + attribute \src "libresoc.v:34400.3-34421.6" wire $0\data_r0__fast1_ok$next[0:0]$1259 - attribute \src "libresoc.v:34110.3-34111.51" + attribute \src "libresoc.v:34158.3-34159.51" wire $0\data_r0__fast1_ok[0:0] - attribute \src "libresoc.v:34374.3-34395.6" + attribute \src "libresoc.v:34422.3-34443.6" wire width 64 $0\data_r1__fast2$next[63:0]$1266 - attribute \src "libresoc.v:34104.3-34105.45" + attribute \src "libresoc.v:34152.3-34153.45" wire width 64 $0\data_r1__fast2[63:0] - attribute \src "libresoc.v:34374.3-34395.6" + attribute \src "libresoc.v:34422.3-34443.6" wire $0\data_r1__fast2_ok$next[0:0]$1267 - attribute \src "libresoc.v:34106.3-34107.51" + attribute \src "libresoc.v:34154.3-34155.51" wire $0\data_r1__fast2_ok[0:0] - attribute \src "libresoc.v:34396.3-34417.6" + attribute \src "libresoc.v:34444.3-34465.6" wire width 64 $0\data_r2__nia$next[63:0]$1274 - attribute \src "libresoc.v:34100.3-34101.41" + attribute \src "libresoc.v:34148.3-34149.41" wire width 64 $0\data_r2__nia[63:0] - attribute \src "libresoc.v:34396.3-34417.6" + attribute \src "libresoc.v:34444.3-34465.6" wire $0\data_r2__nia_ok$next[0:0]$1275 - attribute \src "libresoc.v:34102.3-34103.47" + attribute \src "libresoc.v:34150.3-34151.47" wire $0\data_r2__nia_ok[0:0] - attribute \src "libresoc.v:34466.3-34475.6" + attribute \src "libresoc.v:34514.3-34523.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:34476.3-34485.6" + attribute \src "libresoc.v:34524.3-34533.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:34486.3-34495.6" + attribute \src "libresoc.v:34534.3-34543.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:33481.7-33481.20" + attribute \src "libresoc.v:33529.7-33529.20" wire $0\initial[0:0] - attribute \src "libresoc.v:34282.3-34290.6" + attribute \src "libresoc.v:34330.3-34338.6" wire $0\opc_l_r_opc$next[0:0]$1224 - attribute \src "libresoc.v:34136.3-34137.39" + attribute \src "libresoc.v:34184.3-34185.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:34273.3-34281.6" + attribute \src "libresoc.v:34321.3-34329.6" wire $0\opc_l_s_opc$next[0:0]$1221 - attribute \src "libresoc.v:34138.3-34139.39" + attribute \src "libresoc.v:34186.3-34187.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:34496.3-34504.6" + attribute \src "libresoc.v:34544.3-34552.6" wire width 3 $0\prev_wr_go$next[2:0]$1300 - attribute \src "libresoc.v:34148.3-34149.37" + attribute \src "libresoc.v:34196.3-34197.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:34227.3-34236.6" + attribute \src "libresoc.v:34275.3-34284.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:34318.3-34326.6" + attribute \src "libresoc.v:34366.3-34374.6" wire width 3 $0\req_l_r_req$next[2:0]$1236 - attribute \src "libresoc.v:34128.3-34129.39" + attribute \src "libresoc.v:34176.3-34177.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:34309.3-34317.6" + attribute \src "libresoc.v:34357.3-34365.6" wire width 3 $0\req_l_s_req$next[2:0]$1233 - attribute \src "libresoc.v:34130.3-34131.39" + attribute \src "libresoc.v:34178.3-34179.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:34246.3-34254.6" + attribute \src "libresoc.v:34294.3-34302.6" wire $0\rok_l_r_rdok$next[0:0]$1212 - attribute \src "libresoc.v:34144.3-34145.41" + attribute \src "libresoc.v:34192.3-34193.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:34237.3-34245.6" + attribute \src "libresoc.v:34285.3-34293.6" wire $0\rok_l_s_rdok$next[0:0]$1209 - attribute \src "libresoc.v:34146.3-34147.41" + attribute \src "libresoc.v:34194.3-34195.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:34264.3-34272.6" + attribute \src "libresoc.v:34312.3-34320.6" wire $0\rst_l_r_rst$next[0:0]$1218 - attribute \src "libresoc.v:34140.3-34141.39" + attribute \src "libresoc.v:34188.3-34189.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:34255.3-34263.6" + attribute \src "libresoc.v:34303.3-34311.6" wire $0\rst_l_s_rst$next[0:0]$1215 - attribute \src "libresoc.v:34142.3-34143.39" + attribute \src "libresoc.v:34190.3-34191.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:34300.3-34308.6" + attribute \src "libresoc.v:34348.3-34356.6" wire width 3 $0\src_l_r_src$next[2:0]$1230 - attribute \src "libresoc.v:34132.3-34133.39" + attribute \src "libresoc.v:34180.3-34181.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:34291.3-34299.6" + attribute \src "libresoc.v:34339.3-34347.6" wire width 3 $0\src_l_s_src$next[2:0]$1227 - attribute \src "libresoc.v:34134.3-34135.39" + attribute \src "libresoc.v:34182.3-34183.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:34418.3-34427.6" + attribute \src "libresoc.v:34466.3-34475.6" wire width 64 $0\src_r0$next[63:0]$1282 - attribute \src "libresoc.v:34098.3-34099.29" + attribute \src "libresoc.v:34146.3-34147.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:34428.3-34437.6" + attribute \src "libresoc.v:34476.3-34485.6" wire width 64 $0\src_r1$next[63:0]$1285 - attribute \src "libresoc.v:34096.3-34097.29" + attribute \src "libresoc.v:34144.3-34145.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:34438.3-34447.6" + attribute \src "libresoc.v:34486.3-34495.6" wire width 4 $0\src_r2$next[3:0]$1288 - attribute \src "libresoc.v:34094.3-34095.29" + attribute \src "libresoc.v:34142.3-34143.29" wire width 4 $0\src_r2[3:0] - attribute \src "libresoc.v:33599.7-33599.24" + attribute \src "libresoc.v:33647.7-33647.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $1\alu_branch0_br_op__cia$next[63:0]$1247 - attribute \src "libresoc.v:33607.14-33607.59" + attribute \src "libresoc.v:33655.14-33655.59" wire width 64 $1\alu_branch0_br_op__cia[63:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 14 $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 - attribute \src "libresoc.v:33626.14-33626.51" + attribute \src "libresoc.v:33674.14-33674.51" wire width 14 $1\alu_branch0_br_op__fn_unit[13:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 - attribute \src "libresoc.v:33630.14-33630.70" + attribute \src "libresoc.v:33678.14-33678.70" wire width 64 $1\alu_branch0_br_op__imm_data__data[63:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 - attribute \src "libresoc.v:33634.7-33634.45" + attribute \src "libresoc.v:33682.7-33682.45" wire $1\alu_branch0_br_op__imm_data__ok[0:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 32 $1\alu_branch0_br_op__insn$next[31:0]$1251 - attribute \src "libresoc.v:33638.14-33638.45" + attribute \src "libresoc.v:33686.14-33686.45" wire width 32 $1\alu_branch0_br_op__insn[31:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 7 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 - attribute \src "libresoc.v:33717.13-33717.49" + attribute \src "libresoc.v:33765.13-33765.49" wire width 7 $1\alu_branch0_br_op__insn_type[6:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 - attribute \src "libresoc.v:33721.7-33721.41" + attribute \src "libresoc.v:33769.7-33769.41" wire $1\alu_branch0_br_op__is_32bit[0:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire $1\alu_branch0_br_op__lk$next[0:0]$1254 - attribute \src "libresoc.v:33725.7-33725.35" + attribute \src "libresoc.v:33773.7-33773.35" wire $1\alu_branch0_br_op__lk[0:0] - attribute \src "libresoc.v:33751.7-33751.26" + attribute \src "libresoc.v:33799.7-33799.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:34457.3-34465.6" + attribute \src "libresoc.v:34505.3-34513.6" wire $1\alu_l_r_alu$next[0:0]$1295 - attribute \src "libresoc.v:33759.7-33759.25" + attribute \src "libresoc.v:33807.7-33807.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:34448.3-34456.6" + attribute \src "libresoc.v:34496.3-34504.6" wire $1\alui_l_r_alui$next[0:0]$1292 - attribute \src "libresoc.v:33771.7-33771.27" + attribute \src "libresoc.v:33819.7-33819.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:34352.3-34373.6" + attribute \src "libresoc.v:34400.3-34421.6" wire width 64 $1\data_r0__fast1$next[63:0]$1260 - attribute \src "libresoc.v:33803.14-33803.51" + attribute \src "libresoc.v:33851.14-33851.51" wire width 64 $1\data_r0__fast1[63:0] - attribute \src "libresoc.v:34352.3-34373.6" + attribute \src "libresoc.v:34400.3-34421.6" wire $1\data_r0__fast1_ok$next[0:0]$1261 - attribute \src "libresoc.v:33807.7-33807.31" + attribute \src "libresoc.v:33855.7-33855.31" wire $1\data_r0__fast1_ok[0:0] - attribute \src "libresoc.v:34374.3-34395.6" + attribute \src "libresoc.v:34422.3-34443.6" wire width 64 $1\data_r1__fast2$next[63:0]$1268 - attribute \src "libresoc.v:33811.14-33811.51" + attribute \src "libresoc.v:33859.14-33859.51" wire width 64 $1\data_r1__fast2[63:0] - attribute \src "libresoc.v:34374.3-34395.6" + attribute \src "libresoc.v:34422.3-34443.6" wire $1\data_r1__fast2_ok$next[0:0]$1269 - attribute \src "libresoc.v:33815.7-33815.31" + attribute \src "libresoc.v:33863.7-33863.31" wire $1\data_r1__fast2_ok[0:0] - attribute \src "libresoc.v:34396.3-34417.6" + attribute \src "libresoc.v:34444.3-34465.6" wire width 64 $1\data_r2__nia$next[63:0]$1276 - attribute \src "libresoc.v:33819.14-33819.49" + attribute \src "libresoc.v:33867.14-33867.49" wire width 64 $1\data_r2__nia[63:0] - attribute \src "libresoc.v:34396.3-34417.6" + attribute \src "libresoc.v:34444.3-34465.6" wire $1\data_r2__nia_ok$next[0:0]$1277 - attribute \src "libresoc.v:33823.7-33823.29" + attribute \src "libresoc.v:33871.7-33871.29" wire $1\data_r2__nia_ok[0:0] - attribute \src "libresoc.v:34466.3-34475.6" + attribute \src "libresoc.v:34514.3-34523.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:34476.3-34485.6" + attribute \src "libresoc.v:34524.3-34533.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:34486.3-34495.6" + attribute \src "libresoc.v:34534.3-34543.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:34282.3-34290.6" + attribute \src "libresoc.v:34330.3-34338.6" wire $1\opc_l_r_opc$next[0:0]$1225 - attribute \src "libresoc.v:33844.7-33844.25" + attribute \src "libresoc.v:33892.7-33892.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:34273.3-34281.6" + attribute \src "libresoc.v:34321.3-34329.6" wire $1\opc_l_s_opc$next[0:0]$1222 - attribute \src "libresoc.v:33848.7-33848.25" + attribute \src "libresoc.v:33896.7-33896.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:34496.3-34504.6" + attribute \src "libresoc.v:34544.3-34552.6" wire width 3 $1\prev_wr_go$next[2:0]$1301 - attribute \src "libresoc.v:33958.13-33958.30" + attribute \src "libresoc.v:34006.13-34006.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:34227.3-34236.6" + attribute \src "libresoc.v:34275.3-34284.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:34318.3-34326.6" + attribute \src "libresoc.v:34366.3-34374.6" wire width 3 $1\req_l_r_req$next[2:0]$1237 - attribute \src "libresoc.v:33966.13-33966.31" + attribute \src "libresoc.v:34014.13-34014.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:34309.3-34317.6" + attribute \src "libresoc.v:34357.3-34365.6" wire width 3 $1\req_l_s_req$next[2:0]$1234 - attribute \src "libresoc.v:33970.13-33970.31" + attribute \src "libresoc.v:34018.13-34018.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:34246.3-34254.6" + attribute \src "libresoc.v:34294.3-34302.6" wire $1\rok_l_r_rdok$next[0:0]$1213 - attribute \src "libresoc.v:33982.7-33982.26" + attribute \src "libresoc.v:34030.7-34030.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:34237.3-34245.6" + attribute \src "libresoc.v:34285.3-34293.6" wire $1\rok_l_s_rdok$next[0:0]$1210 - attribute \src "libresoc.v:33986.7-33986.26" + attribute \src "libresoc.v:34034.7-34034.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:34264.3-34272.6" + attribute \src "libresoc.v:34312.3-34320.6" wire $1\rst_l_r_rst$next[0:0]$1219 - attribute \src "libresoc.v:33990.7-33990.25" + attribute \src "libresoc.v:34038.7-34038.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:34255.3-34263.6" + attribute \src "libresoc.v:34303.3-34311.6" wire $1\rst_l_s_rst$next[0:0]$1216 - attribute \src "libresoc.v:33994.7-33994.25" + attribute \src "libresoc.v:34042.7-34042.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:34300.3-34308.6" + attribute \src "libresoc.v:34348.3-34356.6" wire width 3 $1\src_l_r_src$next[2:0]$1231 - attribute \src "libresoc.v:34008.13-34008.31" + attribute \src "libresoc.v:34056.13-34056.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:34291.3-34299.6" + attribute \src "libresoc.v:34339.3-34347.6" wire width 3 $1\src_l_s_src$next[2:0]$1228 - attribute \src "libresoc.v:34012.13-34012.31" + attribute \src "libresoc.v:34060.13-34060.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:34418.3-34427.6" + attribute \src "libresoc.v:34466.3-34475.6" wire width 64 $1\src_r0$next[63:0]$1283 - attribute \src "libresoc.v:34018.14-34018.43" + attribute \src "libresoc.v:34066.14-34066.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:34428.3-34437.6" + attribute \src "libresoc.v:34476.3-34485.6" wire width 64 $1\src_r1$next[63:0]$1286 - attribute \src "libresoc.v:34022.14-34022.43" + attribute \src "libresoc.v:34070.14-34070.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:34438.3-34447.6" + attribute \src "libresoc.v:34486.3-34495.6" wire width 4 $1\src_r2$next[3:0]$1289 - attribute \src "libresoc.v:34026.13-34026.26" + attribute \src "libresoc.v:34074.13-34074.26" wire width 4 $1\src_r2[3:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 - attribute \src "libresoc.v:34352.3-34373.6" + attribute \src "libresoc.v:34400.3-34421.6" wire width 64 $2\data_r0__fast1$next[63:0]$1262 - attribute \src "libresoc.v:34352.3-34373.6" + attribute \src "libresoc.v:34400.3-34421.6" wire $2\data_r0__fast1_ok$next[0:0]$1263 - attribute \src "libresoc.v:34374.3-34395.6" + attribute \src "libresoc.v:34422.3-34443.6" wire width 64 $2\data_r1__fast2$next[63:0]$1270 - attribute \src "libresoc.v:34374.3-34395.6" + attribute \src "libresoc.v:34422.3-34443.6" wire $2\data_r1__fast2_ok$next[0:0]$1271 - attribute \src "libresoc.v:34396.3-34417.6" + attribute \src "libresoc.v:34444.3-34465.6" wire width 64 $2\data_r2__nia$next[63:0]$1278 - attribute \src "libresoc.v:34396.3-34417.6" + attribute \src "libresoc.v:34444.3-34465.6" wire $2\data_r2__nia_ok$next[0:0]$1279 - attribute \src "libresoc.v:34352.3-34373.6" + attribute \src "libresoc.v:34400.3-34421.6" wire $3\data_r0__fast1_ok$next[0:0]$1264 - attribute \src "libresoc.v:34374.3-34395.6" + attribute \src "libresoc.v:34422.3-34443.6" wire $3\data_r1__fast2_ok$next[0:0]$1272 - attribute \src "libresoc.v:34396.3-34417.6" + attribute \src "libresoc.v:34444.3-34465.6" wire $3\data_r2__nia_ok$next[0:0]$1280 - attribute \src "libresoc.v:34034.18-34034.112" - wire width 3 $and$libresoc.v:34034$1119_Y - attribute \src "libresoc.v:34035.19-34035.125" - wire $and$libresoc.v:34035$1120_Y - attribute \src "libresoc.v:34036.19-34036.125" - wire $and$libresoc.v:34036$1121_Y - attribute \src "libresoc.v:34037.19-34037.125" - wire $and$libresoc.v:34037$1122_Y - attribute \src "libresoc.v:34038.19-34038.141" - wire width 3 $and$libresoc.v:34038$1123_Y - attribute \src "libresoc.v:34039.19-34039.121" - wire width 3 $and$libresoc.v:34039$1124_Y - attribute \src "libresoc.v:34040.19-34040.127" - wire $and$libresoc.v:34040$1125_Y - attribute \src "libresoc.v:34041.19-34041.127" - wire $and$libresoc.v:34041$1126_Y - attribute \src "libresoc.v:34042.19-34042.127" - wire $and$libresoc.v:34042$1127_Y - attribute \src "libresoc.v:34043.18-34043.110" - wire $and$libresoc.v:34043$1128_Y - attribute \src "libresoc.v:34045.18-34045.98" - wire $and$libresoc.v:34045$1130_Y - attribute \src "libresoc.v:34047.18-34047.100" - wire $and$libresoc.v:34047$1132_Y - attribute \src "libresoc.v:34048.18-34048.149" - wire width 3 $and$libresoc.v:34048$1133_Y - attribute \src "libresoc.v:34050.18-34050.119" - wire width 3 $and$libresoc.v:34050$1135_Y - attribute \src "libresoc.v:34053.18-34053.116" - wire $and$libresoc.v:34053$1138_Y - attribute \src "libresoc.v:34057.17-34057.123" - wire $and$libresoc.v:34057$1142_Y - attribute \src "libresoc.v:34059.18-34059.113" - wire $and$libresoc.v:34059$1144_Y - attribute \src "libresoc.v:34060.18-34060.125" - wire width 3 $and$libresoc.v:34060$1145_Y - attribute \src "libresoc.v:34062.18-34062.112" - wire $and$libresoc.v:34062$1147_Y - attribute \src "libresoc.v:34064.18-34064.129" - wire $and$libresoc.v:34064$1149_Y - attribute \src "libresoc.v:34065.18-34065.129" - wire $and$libresoc.v:34065$1150_Y - attribute \src "libresoc.v:34066.18-34066.117" - wire $and$libresoc.v:34066$1151_Y - attribute \src "libresoc.v:34071.18-34071.133" - wire $and$libresoc.v:34071$1156_Y - attribute \src "libresoc.v:34072.18-34072.124" - wire width 3 $and$libresoc.v:34072$1157_Y - attribute \src "libresoc.v:34075.18-34075.120" - wire $and$libresoc.v:34075$1160_Y - attribute \src "libresoc.v:34076.18-34076.120" - wire $and$libresoc.v:34076$1161_Y - attribute \src "libresoc.v:34077.18-34077.118" - wire $and$libresoc.v:34077$1162_Y - attribute \src "libresoc.v:34083.18-34083.137" - wire $and$libresoc.v:34083$1168_Y - attribute \src "libresoc.v:34085.18-34085.135" - wire $and$libresoc.v:34085$1170_Y - attribute \src "libresoc.v:34086.18-34086.149" - wire width 3 $and$libresoc.v:34086$1171_Y - attribute \src "libresoc.v:34088.18-34088.129" - wire width 3 $and$libresoc.v:34088$1173_Y - attribute \src "libresoc.v:34061.18-34061.113" - wire $eq$libresoc.v:34061$1146_Y - attribute \src "libresoc.v:34063.18-34063.119" - wire $eq$libresoc.v:34063$1148_Y - attribute \src "libresoc.v:34044.18-34044.97" - wire $not$libresoc.v:34044$1129_Y - attribute \src "libresoc.v:34046.18-34046.99" - wire $not$libresoc.v:34046$1131_Y - attribute \src "libresoc.v:34049.18-34049.113" - wire width 3 $not$libresoc.v:34049$1134_Y - attribute \src "libresoc.v:34052.18-34052.106" - wire $not$libresoc.v:34052$1137_Y - attribute \src "libresoc.v:34058.18-34058.123" - wire $not$libresoc.v:34058$1143_Y - attribute \src "libresoc.v:34073.17-34073.113" - wire width 3 $not$libresoc.v:34073$1158_Y - attribute \src "libresoc.v:34087.18-34087.133" - wire $not$libresoc.v:34087$1172_Y - attribute \src "libresoc.v:34089.18-34089.114" - wire width 3 $not$libresoc.v:34089$1174_Y - attribute \src "libresoc.v:34056.18-34056.112" - wire $or$libresoc.v:34056$1141_Y - attribute \src "libresoc.v:34067.18-34067.122" - wire $or$libresoc.v:34067$1152_Y - attribute \src "libresoc.v:34068.18-34068.124" - wire $or$libresoc.v:34068$1153_Y - attribute \src "libresoc.v:34069.18-34069.155" - wire width 3 $or$libresoc.v:34069$1154_Y - attribute \src "libresoc.v:34070.18-34070.155" - wire width 3 $or$libresoc.v:34070$1155_Y - attribute \src "libresoc.v:34074.18-34074.120" - wire width 3 $or$libresoc.v:34074$1159_Y - attribute \src "libresoc.v:34084.17-34084.117" - wire width 3 $or$libresoc.v:34084$1169_Y - attribute \src "libresoc.v:34033.17-34033.104" - wire $reduce_and$libresoc.v:34033$1118_Y - attribute \src "libresoc.v:34051.18-34051.106" - wire $reduce_or$libresoc.v:34051$1136_Y - attribute \src "libresoc.v:34054.18-34054.113" - wire $reduce_or$libresoc.v:34054$1139_Y - attribute \src "libresoc.v:34055.18-34055.112" - wire $reduce_or$libresoc.v:34055$1140_Y - attribute \src "libresoc.v:34078.18-34078.162" - wire $ternary$libresoc.v:34078$1163_Y - attribute \src "libresoc.v:34079.18-34079.176" - wire width 64 $ternary$libresoc.v:34079$1164_Y - attribute \src "libresoc.v:34080.18-34080.118" - wire width 64 $ternary$libresoc.v:34080$1165_Y - attribute \src "libresoc.v:34081.18-34081.115" - wire width 64 $ternary$libresoc.v:34081$1166_Y - attribute \src "libresoc.v:34082.18-34082.118" - wire width 4 $ternary$libresoc.v:34082$1167_Y + attribute \src "libresoc.v:34082.18-34082.112" + wire width 3 $and$libresoc.v:34082$1119_Y + attribute \src "libresoc.v:34083.19-34083.125" + wire $and$libresoc.v:34083$1120_Y + attribute \src "libresoc.v:34084.19-34084.125" + wire $and$libresoc.v:34084$1121_Y + attribute \src "libresoc.v:34085.19-34085.125" + wire $and$libresoc.v:34085$1122_Y + attribute \src "libresoc.v:34086.19-34086.141" + wire width 3 $and$libresoc.v:34086$1123_Y + attribute \src "libresoc.v:34087.19-34087.121" + wire width 3 $and$libresoc.v:34087$1124_Y + attribute \src "libresoc.v:34088.19-34088.127" + wire $and$libresoc.v:34088$1125_Y + attribute \src "libresoc.v:34089.19-34089.127" + wire $and$libresoc.v:34089$1126_Y + attribute \src "libresoc.v:34090.19-34090.127" + wire $and$libresoc.v:34090$1127_Y + attribute \src "libresoc.v:34091.18-34091.110" + wire $and$libresoc.v:34091$1128_Y + attribute \src "libresoc.v:34093.18-34093.98" + wire $and$libresoc.v:34093$1130_Y + attribute \src "libresoc.v:34095.18-34095.100" + wire $and$libresoc.v:34095$1132_Y + attribute \src "libresoc.v:34096.18-34096.149" + wire width 3 $and$libresoc.v:34096$1133_Y + attribute \src "libresoc.v:34098.18-34098.119" + wire width 3 $and$libresoc.v:34098$1135_Y + attribute \src "libresoc.v:34101.18-34101.116" + wire $and$libresoc.v:34101$1138_Y + attribute \src "libresoc.v:34105.17-34105.123" + wire $and$libresoc.v:34105$1142_Y + attribute \src "libresoc.v:34107.18-34107.113" + wire $and$libresoc.v:34107$1144_Y + attribute \src "libresoc.v:34108.18-34108.125" + wire width 3 $and$libresoc.v:34108$1145_Y + attribute \src "libresoc.v:34110.18-34110.112" + wire $and$libresoc.v:34110$1147_Y + attribute \src "libresoc.v:34112.18-34112.129" + wire $and$libresoc.v:34112$1149_Y + attribute \src "libresoc.v:34113.18-34113.129" + wire $and$libresoc.v:34113$1150_Y + attribute \src "libresoc.v:34114.18-34114.117" + wire $and$libresoc.v:34114$1151_Y + attribute \src "libresoc.v:34119.18-34119.133" + wire $and$libresoc.v:34119$1156_Y + attribute \src "libresoc.v:34120.18-34120.124" + wire width 3 $and$libresoc.v:34120$1157_Y + attribute \src "libresoc.v:34123.18-34123.120" + wire $and$libresoc.v:34123$1160_Y + attribute \src "libresoc.v:34124.18-34124.120" + wire $and$libresoc.v:34124$1161_Y + attribute \src "libresoc.v:34125.18-34125.118" + wire $and$libresoc.v:34125$1162_Y + attribute \src "libresoc.v:34131.18-34131.137" + wire $and$libresoc.v:34131$1168_Y + attribute \src "libresoc.v:34133.18-34133.135" + wire $and$libresoc.v:34133$1170_Y + attribute \src "libresoc.v:34134.18-34134.149" + wire width 3 $and$libresoc.v:34134$1171_Y + attribute \src "libresoc.v:34136.18-34136.129" + wire width 3 $and$libresoc.v:34136$1173_Y + attribute \src "libresoc.v:34109.18-34109.113" + wire $eq$libresoc.v:34109$1146_Y + attribute \src "libresoc.v:34111.18-34111.119" + wire $eq$libresoc.v:34111$1148_Y + attribute \src "libresoc.v:34092.18-34092.97" + wire $not$libresoc.v:34092$1129_Y + attribute \src "libresoc.v:34094.18-34094.99" + wire $not$libresoc.v:34094$1131_Y + attribute \src "libresoc.v:34097.18-34097.113" + wire width 3 $not$libresoc.v:34097$1134_Y + attribute \src "libresoc.v:34100.18-34100.106" + wire $not$libresoc.v:34100$1137_Y + attribute \src "libresoc.v:34106.18-34106.123" + wire $not$libresoc.v:34106$1143_Y + attribute \src "libresoc.v:34121.17-34121.113" + wire width 3 $not$libresoc.v:34121$1158_Y + attribute \src "libresoc.v:34135.18-34135.133" + wire $not$libresoc.v:34135$1172_Y + attribute \src "libresoc.v:34137.18-34137.114" + wire width 3 $not$libresoc.v:34137$1174_Y + attribute \src "libresoc.v:34104.18-34104.112" + wire $or$libresoc.v:34104$1141_Y + attribute \src "libresoc.v:34115.18-34115.122" + wire $or$libresoc.v:34115$1152_Y + attribute \src "libresoc.v:34116.18-34116.124" + wire $or$libresoc.v:34116$1153_Y + attribute \src "libresoc.v:34117.18-34117.155" + wire width 3 $or$libresoc.v:34117$1154_Y + attribute \src "libresoc.v:34118.18-34118.155" + wire width 3 $or$libresoc.v:34118$1155_Y + attribute \src "libresoc.v:34122.18-34122.120" + wire width 3 $or$libresoc.v:34122$1159_Y + attribute \src "libresoc.v:34132.17-34132.117" + wire width 3 $or$libresoc.v:34132$1169_Y + attribute \src "libresoc.v:34081.17-34081.104" + wire $reduce_and$libresoc.v:34081$1118_Y + attribute \src "libresoc.v:34099.18-34099.106" + wire $reduce_or$libresoc.v:34099$1136_Y + attribute \src "libresoc.v:34102.18-34102.113" + wire $reduce_or$libresoc.v:34102$1139_Y + attribute \src "libresoc.v:34103.18-34103.112" + wire $reduce_or$libresoc.v:34103$1140_Y + attribute \src "libresoc.v:34126.18-34126.162" + wire $ternary$libresoc.v:34126$1163_Y + attribute \src "libresoc.v:34127.18-34127.176" + wire width 64 $ternary$libresoc.v:34127$1164_Y + attribute \src "libresoc.v:34128.18-34128.118" + wire width 64 $ternary$libresoc.v:34128$1165_Y + attribute \src "libresoc.v:34129.18-34129.115" + wire width 64 $ternary$libresoc.v:34129$1166_Y + attribute \src "libresoc.v:34130.18-34130.118" + wire width 4 $ternary$libresoc.v:34130$1167_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -50555,11 +50591,11 @@ module \branch0 wire \alu_branch0_br_op__lk$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \alu_branch0_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_branch0_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_branch0_fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_branch0_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_branch0_fast2$2 @@ -50567,7 +50603,7 @@ module \branch0 wire \alu_branch0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_branch0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_branch0_nia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_branch0_p_ready_o @@ -50601,9 +50637,9 @@ module \branch0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 11 \cu_busy_o @@ -50657,13 +50693,13 @@ module \branch0 wire width 64 output 23 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 25 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 18 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 21 \fast2_ok - attribute \src "libresoc.v:33481.7-33481.15" + attribute \src "libresoc.v:33529.7-33529.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 24 \nia_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc @@ -50858,7 +50894,7 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:34034$1119 + cell $and $and$libresoc.v:34082$1119 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50866,10 +50902,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:34034$1119_Y + connect \Y $and$libresoc.v:34082$1119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:34035$1120 + cell $and $and$libresoc.v:34083$1120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50877,10 +50913,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:34035$1120_Y + connect \Y $and$libresoc.v:34083$1120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:34036$1121 + cell $and $and$libresoc.v:34084$1121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50888,10 +50924,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:34036$1121_Y + connect \Y $and$libresoc.v:34084$1121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:34037$1122 + cell $and $and$libresoc.v:34085$1122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50899,10 +50935,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:34037$1122_Y + connect \Y $and$libresoc.v:34085$1122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:34038$1123 + cell $and $and$libresoc.v:34086$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50910,10 +50946,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } - connect \Y $and$libresoc.v:34038$1123_Y + connect \Y $and$libresoc.v:34086$1123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:34039$1124 + cell $and $and$libresoc.v:34087$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50921,10 +50957,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:34039$1124_Y + connect \Y $and$libresoc.v:34087$1124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:34040$1125 + cell $and $and$libresoc.v:34088$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50932,10 +50968,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:34040$1125_Y + connect \Y $and$libresoc.v:34088$1125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:34041$1126 + cell $and $and$libresoc.v:34089$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50943,10 +50979,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:34041$1126_Y + connect \Y $and$libresoc.v:34089$1126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:34042$1127 + cell $and $and$libresoc.v:34090$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50954,10 +50990,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:34042$1127_Y + connect \Y $and$libresoc.v:34090$1127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:34043$1128 + cell $and $and$libresoc.v:34091$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50965,10 +51001,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:34043$1128_Y + connect \Y $and$libresoc.v:34091$1128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:34045$1130 + cell $and $and$libresoc.v:34093$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50976,10 +51012,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:34045$1130_Y + connect \Y $and$libresoc.v:34093$1130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:34047$1132 + cell $and $and$libresoc.v:34095$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50987,10 +51023,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:34047$1132_Y + connect \Y $and$libresoc.v:34095$1132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:34048$1133 + cell $and $and$libresoc.v:34096$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50998,10 +51034,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:34048$1133_Y + connect \Y $and$libresoc.v:34096$1133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:34050$1135 + cell $and $and$libresoc.v:34098$1135 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51009,10 +51045,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:34050$1135_Y + connect \Y $and$libresoc.v:34098$1135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:34053$1138 + cell $and $and$libresoc.v:34101$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51020,10 +51056,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:34053$1138_Y + connect \Y $and$libresoc.v:34101$1138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:34057$1142 + cell $and $and$libresoc.v:34105$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51031,10 +51067,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:34057$1142_Y + connect \Y $and$libresoc.v:34105$1142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:34059$1144 + cell $and $and$libresoc.v:34107$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51042,10 +51078,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:34059$1144_Y + connect \Y $and$libresoc.v:34107$1144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:34060$1145 + cell $and $and$libresoc.v:34108$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51053,10 +51089,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:34060$1145_Y + connect \Y $and$libresoc.v:34108$1145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:34062$1147 + cell $and $and$libresoc.v:34110$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51064,10 +51100,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:34062$1147_Y + connect \Y $and$libresoc.v:34110$1147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:34064$1149 + cell $and $and$libresoc.v:34112$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51075,10 +51111,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_branch0_n_ready_i - connect \Y $and$libresoc.v:34064$1149_Y + connect \Y $and$libresoc.v:34112$1149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:34065$1150 + cell $and $and$libresoc.v:34113$1150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51086,10 +51122,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_branch0_n_valid_o - connect \Y $and$libresoc.v:34065$1150_Y + connect \Y $and$libresoc.v:34113$1150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:34066$1151 + cell $and $and$libresoc.v:34114$1151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51097,10 +51133,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:34066$1151_Y + connect \Y $and$libresoc.v:34114$1151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:34071$1156 + cell $and $and$libresoc.v:34119$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51108,10 +51144,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:34071$1156_Y + connect \Y $and$libresoc.v:34119$1156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:34072$1157 + cell $and $and$libresoc.v:34120$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51119,10 +51155,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:34072$1157_Y + connect \Y $and$libresoc.v:34120$1157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:34075$1160 + cell $and $and$libresoc.v:34123$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51130,10 +51166,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:34075$1160_Y + connect \Y $and$libresoc.v:34123$1160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:34076$1161 + cell $and $and$libresoc.v:34124$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51141,10 +51177,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:34076$1161_Y + connect \Y $and$libresoc.v:34124$1161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:34077$1162 + cell $and $and$libresoc.v:34125$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51152,10 +51188,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:34077$1162_Y + connect \Y $and$libresoc.v:34125$1162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:34083$1168 + cell $and $and$libresoc.v:34131$1168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51163,10 +51199,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:34083$1168_Y + connect \Y $and$libresoc.v:34131$1168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:34085$1170 + cell $and $and$libresoc.v:34133$1170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51174,10 +51210,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:34085$1170_Y + connect \Y $and$libresoc.v:34133$1170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:34086$1171 + cell $and $and$libresoc.v:34134$1171 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51185,10 +51221,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:34086$1171_Y + connect \Y $and$libresoc.v:34134$1171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:34088$1173 + cell $and $and$libresoc.v:34136$1173 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51196,10 +51232,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$91 connect \B { 1'1 \$93 1'1 } - connect \Y $and$libresoc.v:34088$1173_Y + connect \Y $and$libresoc.v:34136$1173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:34061$1146 + cell $eq $eq$libresoc.v:34109$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51207,10 +51243,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:34061$1146_Y + connect \Y $eq$libresoc.v:34109$1146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:34063$1148 + cell $eq $eq$libresoc.v:34111$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51218,74 +51254,74 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:34063$1148_Y + connect \Y $eq$libresoc.v:34111$1148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:34044$1129 + cell $not $not$libresoc.v:34092$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:34044$1129_Y + connect \Y $not$libresoc.v:34092$1129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:34046$1131 + cell $not $not$libresoc.v:34094$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:34046$1131_Y + connect \Y $not$libresoc.v:34094$1131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:34049$1134 + cell $not $not$libresoc.v:34097$1134 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:34049$1134_Y + connect \Y $not$libresoc.v:34097$1134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:34052$1137 + cell $not $not$libresoc.v:34100$1137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:34052$1137_Y + connect \Y $not$libresoc.v:34100$1137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:34058$1143 + cell $not $not$libresoc.v:34106$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_ready_i - connect \Y $not$libresoc.v:34058$1143_Y + connect \Y $not$libresoc.v:34106$1143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:34073$1158 + cell $not $not$libresoc.v:34121$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:34073$1158_Y + connect \Y $not$libresoc.v:34121$1158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:34087$1172 + cell $not $not$libresoc.v:34135$1172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_br_op__imm_data__ok - connect \Y $not$libresoc.v:34087$1172_Y + connect \Y $not$libresoc.v:34135$1172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:34089$1174 + cell $not $not$libresoc.v:34137$1174 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:34089$1174_Y + connect \Y $not$libresoc.v:34137$1174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:34056$1141 + cell $or $or$libresoc.v:34104$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51293,10 +51329,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:34056$1141_Y + connect \Y $or$libresoc.v:34104$1141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:34067$1152 + cell $or $or$libresoc.v:34115$1152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51304,10 +51340,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:34067$1152_Y + connect \Y $or$libresoc.v:34115$1152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:34068$1153 + cell $or $or$libresoc.v:34116$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51315,10 +51351,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:34068$1153_Y + connect \Y $or$libresoc.v:34116$1153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:34069$1154 + cell $or $or$libresoc.v:34117$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51326,10 +51362,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:34069$1154_Y + connect \Y $or$libresoc.v:34117$1154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:34070$1155 + cell $or $or$libresoc.v:34118$1155 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51337,10 +51373,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:34070$1155_Y + connect \Y $or$libresoc.v:34118$1155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:34074$1159 + cell $or $or$libresoc.v:34122$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51348,10 +51384,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:34074$1159_Y + connect \Y $or$libresoc.v:34122$1159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:34084$1169 + cell $or $or$libresoc.v:34132$1169 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51359,82 +51395,82 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:34084$1169_Y + connect \Y $or$libresoc.v:34132$1169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:34033$1118 + cell $reduce_and $reduce_and$libresoc.v:34081$1118 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:34033$1118_Y + connect \Y $reduce_and$libresoc.v:34081$1118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:34051$1136 + cell $reduce_or $reduce_or$libresoc.v:34099$1136 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:34051$1136_Y + connect \Y $reduce_or$libresoc.v:34099$1136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:34054$1139 + cell $reduce_or $reduce_or$libresoc.v:34102$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:34054$1139_Y + connect \Y $reduce_or$libresoc.v:34102$1139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:34055$1140 + cell $reduce_or $reduce_or$libresoc.v:34103$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:34055$1140_Y + connect \Y $reduce_or$libresoc.v:34103$1140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:34078$1163 + cell $mux $ternary$libresoc.v:34126$1163 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $ternary$libresoc.v:34078$1163_Y + connect \Y $ternary$libresoc.v:34126$1163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:34079$1164 + cell $mux $ternary$libresoc.v:34127$1164 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_branch0_br_op__imm_data__data connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $ternary$libresoc.v:34079$1164_Y + connect \Y $ternary$libresoc.v:34127$1164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:34080$1165 + cell $mux $ternary$libresoc.v:34128$1165 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:34080$1165_Y + connect \Y $ternary$libresoc.v:34128$1165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:34081$1166 + cell $mux $ternary$libresoc.v:34129$1166 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:34081$1166_Y + connect \Y $ternary$libresoc.v:34129$1166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:34082$1167 + cell $mux $ternary$libresoc.v:34130$1167 parameter \WIDTH 4 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:34082$1167_Y + connect \Y $ternary$libresoc.v:34130$1167_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:34154.15-34178.4" + attribute \src "libresoc.v:34202.15-34226.4" cell \alu_branch0 \alu_branch0 connect \br_op__cia \alu_branch0_br_op__cia connect \br_op__fn_unit \alu_branch0_br_op__fn_unit @@ -51461,7 +51497,7 @@ module \branch0 connect \p_valid_i \alu_branch0_p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:34179.14-34185.4" + attribute \src "libresoc.v:34227.14-34233.4" cell \alu_l$29 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51470,7 +51506,7 @@ module \branch0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:34186.15-34192.4" + attribute \src "libresoc.v:34234.15-34240.4" cell \alui_l$28 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51479,7 +51515,7 @@ module \branch0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:34193.14-34199.4" + attribute \src "libresoc.v:34241.14-34247.4" cell \opc_l$24 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51488,7 +51524,7 @@ module \branch0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:34200.14-34206.4" + attribute \src "libresoc.v:34248.14-34254.4" cell \req_l$25 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51497,7 +51533,7 @@ module \branch0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:34207.14-34213.4" + attribute \src "libresoc.v:34255.14-34261.4" cell \rok_l$27 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51506,7 +51542,7 @@ module \branch0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:34214.14-34219.4" + attribute \src "libresoc.v:34262.14-34267.4" cell \rst_l$26 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51514,7 +51550,7 @@ module \branch0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:34220.14-34226.4" + attribute \src "libresoc.v:34268.14-34274.4" cell \src_l$23 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51522,502 +51558,502 @@ module \branch0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:33481.7-33481.20" - process $proc$libresoc.v:33481$1302 + attribute \src "libresoc.v:33529.7-33529.20" + process $proc$libresoc.v:33529$1302 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:33599.7-33599.24" - process $proc$libresoc.v:33599$1303 + attribute \src "libresoc.v:33647.7-33647.24" + process $proc$libresoc.v:33647$1303 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:33607.14-33607.59" - process $proc$libresoc.v:33607$1304 + attribute \src "libresoc.v:33655.14-33655.59" + process $proc$libresoc.v:33655$1304 assign { } { } assign $1\alu_branch0_br_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_branch0_br_op__cia $1\alu_branch0_br_op__cia[63:0] end - attribute \src "libresoc.v:33626.14-33626.51" - process $proc$libresoc.v:33626$1305 + attribute \src "libresoc.v:33674.14-33674.51" + process $proc$libresoc.v:33674$1305 assign { } { } assign $1\alu_branch0_br_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[13:0] end - attribute \src "libresoc.v:33630.14-33630.70" - process $proc$libresoc.v:33630$1306 + attribute \src "libresoc.v:33678.14-33678.70" + process $proc$libresoc.v:33678$1306 assign { } { } assign $1\alu_branch0_br_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_branch0_br_op__imm_data__data $1\alu_branch0_br_op__imm_data__data[63:0] end - attribute \src "libresoc.v:33634.7-33634.45" - process $proc$libresoc.v:33634$1307 + attribute \src "libresoc.v:33682.7-33682.45" + process $proc$libresoc.v:33682$1307 assign { } { } assign $1\alu_branch0_br_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_branch0_br_op__imm_data__ok $1\alu_branch0_br_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:33638.14-33638.45" - process $proc$libresoc.v:33638$1308 + attribute \src "libresoc.v:33686.14-33686.45" + process $proc$libresoc.v:33686$1308 assign { } { } assign $1\alu_branch0_br_op__insn[31:0] 0 sync always sync init update \alu_branch0_br_op__insn $1\alu_branch0_br_op__insn[31:0] end - attribute \src "libresoc.v:33717.13-33717.49" - process $proc$libresoc.v:33717$1309 + attribute \src "libresoc.v:33765.13-33765.49" + process $proc$libresoc.v:33765$1309 assign { } { } assign $1\alu_branch0_br_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_branch0_br_op__insn_type $1\alu_branch0_br_op__insn_type[6:0] end - attribute \src "libresoc.v:33721.7-33721.41" - process $proc$libresoc.v:33721$1310 + attribute \src "libresoc.v:33769.7-33769.41" + process $proc$libresoc.v:33769$1310 assign { } { } assign $1\alu_branch0_br_op__is_32bit[0:0] 1'0 sync always sync init update \alu_branch0_br_op__is_32bit $1\alu_branch0_br_op__is_32bit[0:0] end - attribute \src "libresoc.v:33725.7-33725.35" - process $proc$libresoc.v:33725$1311 + attribute \src "libresoc.v:33773.7-33773.35" + process $proc$libresoc.v:33773$1311 assign { } { } assign $1\alu_branch0_br_op__lk[0:0] 1'0 sync always sync init update \alu_branch0_br_op__lk $1\alu_branch0_br_op__lk[0:0] end - attribute \src "libresoc.v:33751.7-33751.26" - process $proc$libresoc.v:33751$1312 + attribute \src "libresoc.v:33799.7-33799.26" + process $proc$libresoc.v:33799$1312 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:33759.7-33759.25" - process $proc$libresoc.v:33759$1313 + attribute \src "libresoc.v:33807.7-33807.25" + process $proc$libresoc.v:33807$1313 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:33771.7-33771.27" - process $proc$libresoc.v:33771$1314 + attribute \src "libresoc.v:33819.7-33819.27" + process $proc$libresoc.v:33819$1314 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:33803.14-33803.51" - process $proc$libresoc.v:33803$1315 + attribute \src "libresoc.v:33851.14-33851.51" + process $proc$libresoc.v:33851$1315 assign { } { } assign $1\data_r0__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__fast1 $1\data_r0__fast1[63:0] end - attribute \src "libresoc.v:33807.7-33807.31" - process $proc$libresoc.v:33807$1316 + attribute \src "libresoc.v:33855.7-33855.31" + process $proc$libresoc.v:33855$1316 assign { } { } assign $1\data_r0__fast1_ok[0:0] 1'0 sync always sync init update \data_r0__fast1_ok $1\data_r0__fast1_ok[0:0] end - attribute \src "libresoc.v:33811.14-33811.51" - process $proc$libresoc.v:33811$1317 + attribute \src "libresoc.v:33859.14-33859.51" + process $proc$libresoc.v:33859$1317 assign { } { } assign $1\data_r1__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast2 $1\data_r1__fast2[63:0] end - attribute \src "libresoc.v:33815.7-33815.31" - process $proc$libresoc.v:33815$1318 + attribute \src "libresoc.v:33863.7-33863.31" + process $proc$libresoc.v:33863$1318 assign { } { } assign $1\data_r1__fast2_ok[0:0] 1'0 sync always sync init update \data_r1__fast2_ok $1\data_r1__fast2_ok[0:0] end - attribute \src "libresoc.v:33819.14-33819.49" - process $proc$libresoc.v:33819$1319 + attribute \src "libresoc.v:33867.14-33867.49" + process $proc$libresoc.v:33867$1319 assign { } { } assign $1\data_r2__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__nia $1\data_r2__nia[63:0] end - attribute \src "libresoc.v:33823.7-33823.29" - process $proc$libresoc.v:33823$1320 + attribute \src "libresoc.v:33871.7-33871.29" + process $proc$libresoc.v:33871$1320 assign { } { } assign $1\data_r2__nia_ok[0:0] 1'0 sync always sync init update \data_r2__nia_ok $1\data_r2__nia_ok[0:0] end - attribute \src "libresoc.v:33844.7-33844.25" - process $proc$libresoc.v:33844$1321 + attribute \src "libresoc.v:33892.7-33892.25" + process $proc$libresoc.v:33892$1321 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:33848.7-33848.25" - process $proc$libresoc.v:33848$1322 + attribute \src "libresoc.v:33896.7-33896.25" + process $proc$libresoc.v:33896$1322 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:33958.13-33958.30" - process $proc$libresoc.v:33958$1323 + attribute \src "libresoc.v:34006.13-34006.30" + process $proc$libresoc.v:34006$1323 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:33966.13-33966.31" - process $proc$libresoc.v:33966$1324 + attribute \src "libresoc.v:34014.13-34014.31" + process $proc$libresoc.v:34014$1324 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:33970.13-33970.31" - process $proc$libresoc.v:33970$1325 + attribute \src "libresoc.v:34018.13-34018.31" + process $proc$libresoc.v:34018$1325 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:33982.7-33982.26" - process $proc$libresoc.v:33982$1326 + attribute \src "libresoc.v:34030.7-34030.26" + process $proc$libresoc.v:34030$1326 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:33986.7-33986.26" - process $proc$libresoc.v:33986$1327 + attribute \src "libresoc.v:34034.7-34034.26" + process $proc$libresoc.v:34034$1327 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:33990.7-33990.25" - process $proc$libresoc.v:33990$1328 + attribute \src "libresoc.v:34038.7-34038.25" + process $proc$libresoc.v:34038$1328 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:33994.7-33994.25" - process $proc$libresoc.v:33994$1329 + attribute \src "libresoc.v:34042.7-34042.25" + process $proc$libresoc.v:34042$1329 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:34008.13-34008.31" - process $proc$libresoc.v:34008$1330 + attribute \src "libresoc.v:34056.13-34056.31" + process $proc$libresoc.v:34056$1330 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:34012.13-34012.31" - process $proc$libresoc.v:34012$1331 + attribute \src "libresoc.v:34060.13-34060.31" + process $proc$libresoc.v:34060$1331 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:34018.14-34018.43" - process $proc$libresoc.v:34018$1332 + attribute \src "libresoc.v:34066.14-34066.43" + process $proc$libresoc.v:34066$1332 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:34022.14-34022.43" - process $proc$libresoc.v:34022$1333 + attribute \src "libresoc.v:34070.14-34070.43" + process $proc$libresoc.v:34070$1333 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:34026.13-34026.26" - process $proc$libresoc.v:34026$1334 + attribute \src "libresoc.v:34074.13-34074.26" + process $proc$libresoc.v:34074$1334 assign { } { } assign $1\src_r2[3:0] 4'0000 sync always sync init update \src_r2 $1\src_r2[3:0] end - attribute \src "libresoc.v:34090.3-34091.39" - process $proc$libresoc.v:34090$1175 + attribute \src "libresoc.v:34138.3-34139.39" + process $proc$libresoc.v:34138$1175 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:34092.3-34093.43" - process $proc$libresoc.v:34092$1176 + attribute \src "libresoc.v:34140.3-34141.43" + process $proc$libresoc.v:34140$1176 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:34094.3-34095.29" - process $proc$libresoc.v:34094$1177 + attribute \src "libresoc.v:34142.3-34143.29" + process $proc$libresoc.v:34142$1177 assign { } { } assign $0\src_r2[3:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[3:0] end - attribute \src "libresoc.v:34096.3-34097.29" - process $proc$libresoc.v:34096$1178 + attribute \src "libresoc.v:34144.3-34145.29" + process $proc$libresoc.v:34144$1178 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:34098.3-34099.29" - process $proc$libresoc.v:34098$1179 + attribute \src "libresoc.v:34146.3-34147.29" + process $proc$libresoc.v:34146$1179 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:34100.3-34101.41" - process $proc$libresoc.v:34100$1180 + attribute \src "libresoc.v:34148.3-34149.41" + process $proc$libresoc.v:34148$1180 assign { } { } assign $0\data_r2__nia[63:0] \data_r2__nia$next sync posedge \coresync_clk update \data_r2__nia $0\data_r2__nia[63:0] end - attribute \src "libresoc.v:34102.3-34103.47" - process $proc$libresoc.v:34102$1181 + attribute \src "libresoc.v:34150.3-34151.47" + process $proc$libresoc.v:34150$1181 assign { } { } assign $0\data_r2__nia_ok[0:0] \data_r2__nia_ok$next sync posedge \coresync_clk update \data_r2__nia_ok $0\data_r2__nia_ok[0:0] end - attribute \src "libresoc.v:34104.3-34105.45" - process $proc$libresoc.v:34104$1182 + attribute \src "libresoc.v:34152.3-34153.45" + process $proc$libresoc.v:34152$1182 assign { } { } assign $0\data_r1__fast2[63:0] \data_r1__fast2$next sync posedge \coresync_clk update \data_r1__fast2 $0\data_r1__fast2[63:0] end - attribute \src "libresoc.v:34106.3-34107.51" - process $proc$libresoc.v:34106$1183 + attribute \src "libresoc.v:34154.3-34155.51" + process $proc$libresoc.v:34154$1183 assign { } { } assign $0\data_r1__fast2_ok[0:0] \data_r1__fast2_ok$next sync posedge \coresync_clk update \data_r1__fast2_ok $0\data_r1__fast2_ok[0:0] end - attribute \src "libresoc.v:34108.3-34109.45" - process $proc$libresoc.v:34108$1184 + attribute \src "libresoc.v:34156.3-34157.45" + process $proc$libresoc.v:34156$1184 assign { } { } assign $0\data_r0__fast1[63:0] \data_r0__fast1$next sync posedge \coresync_clk update \data_r0__fast1 $0\data_r0__fast1[63:0] end - attribute \src "libresoc.v:34110.3-34111.51" - process $proc$libresoc.v:34110$1185 + attribute \src "libresoc.v:34158.3-34159.51" + process $proc$libresoc.v:34158$1185 assign { } { } assign $0\data_r0__fast1_ok[0:0] \data_r0__fast1_ok$next sync posedge \coresync_clk update \data_r0__fast1_ok $0\data_r0__fast1_ok[0:0] end - attribute \src "libresoc.v:34112.3-34113.61" - process $proc$libresoc.v:34112$1186 + attribute \src "libresoc.v:34160.3-34161.61" + process $proc$libresoc.v:34160$1186 assign { } { } assign $0\alu_branch0_br_op__cia[63:0] \alu_branch0_br_op__cia$next sync posedge \coresync_clk update \alu_branch0_br_op__cia $0\alu_branch0_br_op__cia[63:0] end - attribute \src "libresoc.v:34114.3-34115.73" - process $proc$libresoc.v:34114$1187 + attribute \src "libresoc.v:34162.3-34163.73" + process $proc$libresoc.v:34162$1187 assign { } { } assign $0\alu_branch0_br_op__insn_type[6:0] \alu_branch0_br_op__insn_type$next sync posedge \coresync_clk update \alu_branch0_br_op__insn_type $0\alu_branch0_br_op__insn_type[6:0] end - attribute \src "libresoc.v:34116.3-34117.69" - process $proc$libresoc.v:34116$1188 + attribute \src "libresoc.v:34164.3-34165.69" + process $proc$libresoc.v:34164$1188 assign { } { } assign $0\alu_branch0_br_op__fn_unit[13:0] \alu_branch0_br_op__fn_unit$next sync posedge \coresync_clk update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[13:0] end - attribute \src "libresoc.v:34118.3-34119.63" - process $proc$libresoc.v:34118$1189 + attribute \src "libresoc.v:34166.3-34167.63" + process $proc$libresoc.v:34166$1189 assign { } { } assign $0\alu_branch0_br_op__insn[31:0] \alu_branch0_br_op__insn$next sync posedge \coresync_clk update \alu_branch0_br_op__insn $0\alu_branch0_br_op__insn[31:0] end - attribute \src "libresoc.v:34120.3-34121.83" - process $proc$libresoc.v:34120$1190 + attribute \src "libresoc.v:34168.3-34169.83" + process $proc$libresoc.v:34168$1190 assign { } { } assign $0\alu_branch0_br_op__imm_data__data[63:0] \alu_branch0_br_op__imm_data__data$next sync posedge \coresync_clk update \alu_branch0_br_op__imm_data__data $0\alu_branch0_br_op__imm_data__data[63:0] end - attribute \src "libresoc.v:34122.3-34123.79" - process $proc$libresoc.v:34122$1191 + attribute \src "libresoc.v:34170.3-34171.79" + process $proc$libresoc.v:34170$1191 assign { } { } assign $0\alu_branch0_br_op__imm_data__ok[0:0] \alu_branch0_br_op__imm_data__ok$next sync posedge \coresync_clk update \alu_branch0_br_op__imm_data__ok $0\alu_branch0_br_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:34124.3-34125.59" - process $proc$libresoc.v:34124$1192 + attribute \src "libresoc.v:34172.3-34173.59" + process $proc$libresoc.v:34172$1192 assign { } { } assign $0\alu_branch0_br_op__lk[0:0] \alu_branch0_br_op__lk$next sync posedge \coresync_clk update \alu_branch0_br_op__lk $0\alu_branch0_br_op__lk[0:0] end - attribute \src "libresoc.v:34126.3-34127.71" - process $proc$libresoc.v:34126$1193 + attribute \src "libresoc.v:34174.3-34175.71" + process $proc$libresoc.v:34174$1193 assign { } { } assign $0\alu_branch0_br_op__is_32bit[0:0] \alu_branch0_br_op__is_32bit$next sync posedge \coresync_clk update \alu_branch0_br_op__is_32bit $0\alu_branch0_br_op__is_32bit[0:0] end - attribute \src "libresoc.v:34128.3-34129.39" - process $proc$libresoc.v:34128$1194 + attribute \src "libresoc.v:34176.3-34177.39" + process $proc$libresoc.v:34176$1194 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:34130.3-34131.39" - process $proc$libresoc.v:34130$1195 + attribute \src "libresoc.v:34178.3-34179.39" + process $proc$libresoc.v:34178$1195 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:34132.3-34133.39" - process $proc$libresoc.v:34132$1196 + attribute \src "libresoc.v:34180.3-34181.39" + process $proc$libresoc.v:34180$1196 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:34134.3-34135.39" - process $proc$libresoc.v:34134$1197 + attribute \src "libresoc.v:34182.3-34183.39" + process $proc$libresoc.v:34182$1197 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:34136.3-34137.39" - process $proc$libresoc.v:34136$1198 + attribute \src "libresoc.v:34184.3-34185.39" + process $proc$libresoc.v:34184$1198 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:34138.3-34139.39" - process $proc$libresoc.v:34138$1199 + attribute \src "libresoc.v:34186.3-34187.39" + process $proc$libresoc.v:34186$1199 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:34140.3-34141.39" - process $proc$libresoc.v:34140$1200 + attribute \src "libresoc.v:34188.3-34189.39" + process $proc$libresoc.v:34188$1200 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:34142.3-34143.39" - process $proc$libresoc.v:34142$1201 + attribute \src "libresoc.v:34190.3-34191.39" + process $proc$libresoc.v:34190$1201 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:34144.3-34145.41" - process $proc$libresoc.v:34144$1202 + attribute \src "libresoc.v:34192.3-34193.41" + process $proc$libresoc.v:34192$1202 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:34146.3-34147.41" - process $proc$libresoc.v:34146$1203 + attribute \src "libresoc.v:34194.3-34195.41" + process $proc$libresoc.v:34194$1203 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:34148.3-34149.37" - process $proc$libresoc.v:34148$1204 + attribute \src "libresoc.v:34196.3-34197.37" + process $proc$libresoc.v:34196$1204 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:34150.3-34151.43" - process $proc$libresoc.v:34150$1205 + attribute \src "libresoc.v:34198.3-34199.43" + process $proc$libresoc.v:34198$1205 assign { } { } assign $0\alu_done_dly[0:0] \alu_branch0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:34152.3-34153.25" - process $proc$libresoc.v:34152$1206 + attribute \src "libresoc.v:34200.3-34201.25" + process $proc$libresoc.v:34200$1206 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:34227.3-34236.6" - process $proc$libresoc.v:34227$1207 + attribute \src "libresoc.v:34275.3-34284.6" + process $proc$libresoc.v:34275$1207 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:34228.5-34228.29" + attribute \src "libresoc.v:34276.5-34276.29" switch \initial - attribute \src "libresoc.v:34228.9-34228.17" + attribute \src "libresoc.v:34276.9-34276.17" case 1'1 case end @@ -52033,14 +52069,14 @@ module \branch0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:34237.3-34245.6" - process $proc$libresoc.v:34237$1208 + attribute \src "libresoc.v:34285.3-34293.6" + process $proc$libresoc.v:34285$1208 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$1209 $1\rok_l_s_rdok$next[0:0]$1210 - attribute \src "libresoc.v:34238.5-34238.29" + attribute \src "libresoc.v:34286.5-34286.29" switch \initial - attribute \src "libresoc.v:34238.9-34238.17" + attribute \src "libresoc.v:34286.9-34286.17" case 1'1 case end @@ -52056,14 +52092,14 @@ module \branch0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$1209 end - attribute \src "libresoc.v:34246.3-34254.6" - process $proc$libresoc.v:34246$1211 + attribute \src "libresoc.v:34294.3-34302.6" + process $proc$libresoc.v:34294$1211 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$1212 $1\rok_l_r_rdok$next[0:0]$1213 - attribute \src "libresoc.v:34247.5-34247.29" + attribute \src "libresoc.v:34295.5-34295.29" switch \initial - attribute \src "libresoc.v:34247.9-34247.17" + attribute \src "libresoc.v:34295.9-34295.17" case 1'1 case end @@ -52079,14 +52115,14 @@ module \branch0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$1212 end - attribute \src "libresoc.v:34255.3-34263.6" - process $proc$libresoc.v:34255$1214 + attribute \src "libresoc.v:34303.3-34311.6" + process $proc$libresoc.v:34303$1214 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$1215 $1\rst_l_s_rst$next[0:0]$1216 - attribute \src "libresoc.v:34256.5-34256.29" + attribute \src "libresoc.v:34304.5-34304.29" switch \initial - attribute \src "libresoc.v:34256.9-34256.17" + attribute \src "libresoc.v:34304.9-34304.17" case 1'1 case end @@ -52102,14 +52138,14 @@ module \branch0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$1215 end - attribute \src "libresoc.v:34264.3-34272.6" - process $proc$libresoc.v:34264$1217 + attribute \src "libresoc.v:34312.3-34320.6" + process $proc$libresoc.v:34312$1217 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$1218 $1\rst_l_r_rst$next[0:0]$1219 - attribute \src "libresoc.v:34265.5-34265.29" + attribute \src "libresoc.v:34313.5-34313.29" switch \initial - attribute \src "libresoc.v:34265.9-34265.17" + attribute \src "libresoc.v:34313.9-34313.17" case 1'1 case end @@ -52125,14 +52161,14 @@ module \branch0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$1218 end - attribute \src "libresoc.v:34273.3-34281.6" - process $proc$libresoc.v:34273$1220 + attribute \src "libresoc.v:34321.3-34329.6" + process $proc$libresoc.v:34321$1220 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$1221 $1\opc_l_s_opc$next[0:0]$1222 - attribute \src "libresoc.v:34274.5-34274.29" + attribute \src "libresoc.v:34322.5-34322.29" switch \initial - attribute \src "libresoc.v:34274.9-34274.17" + attribute \src "libresoc.v:34322.9-34322.17" case 1'1 case end @@ -52148,14 +52184,14 @@ module \branch0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$1221 end - attribute \src "libresoc.v:34282.3-34290.6" - process $proc$libresoc.v:34282$1223 + attribute \src "libresoc.v:34330.3-34338.6" + process $proc$libresoc.v:34330$1223 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$1224 $1\opc_l_r_opc$next[0:0]$1225 - attribute \src "libresoc.v:34283.5-34283.29" + attribute \src "libresoc.v:34331.5-34331.29" switch \initial - attribute \src "libresoc.v:34283.9-34283.17" + attribute \src "libresoc.v:34331.9-34331.17" case 1'1 case end @@ -52171,14 +52207,14 @@ module \branch0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$1224 end - attribute \src "libresoc.v:34291.3-34299.6" - process $proc$libresoc.v:34291$1226 + attribute \src "libresoc.v:34339.3-34347.6" + process $proc$libresoc.v:34339$1226 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$1227 $1\src_l_s_src$next[2:0]$1228 - attribute \src "libresoc.v:34292.5-34292.29" + attribute \src "libresoc.v:34340.5-34340.29" switch \initial - attribute \src "libresoc.v:34292.9-34292.17" + attribute \src "libresoc.v:34340.9-34340.17" case 1'1 case end @@ -52194,14 +52230,14 @@ module \branch0 sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$1227 end - attribute \src "libresoc.v:34300.3-34308.6" - process $proc$libresoc.v:34300$1229 + attribute \src "libresoc.v:34348.3-34356.6" + process $proc$libresoc.v:34348$1229 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$1230 $1\src_l_r_src$next[2:0]$1231 - attribute \src "libresoc.v:34301.5-34301.29" + attribute \src "libresoc.v:34349.5-34349.29" switch \initial - attribute \src "libresoc.v:34301.9-34301.17" + attribute \src "libresoc.v:34349.9-34349.17" case 1'1 case end @@ -52217,14 +52253,14 @@ module \branch0 sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$1230 end - attribute \src "libresoc.v:34309.3-34317.6" - process $proc$libresoc.v:34309$1232 + attribute \src "libresoc.v:34357.3-34365.6" + process $proc$libresoc.v:34357$1232 assign { } { } assign { } { } assign $0\req_l_s_req$next[2:0]$1233 $1\req_l_s_req$next[2:0]$1234 - attribute \src "libresoc.v:34310.5-34310.29" + attribute \src "libresoc.v:34358.5-34358.29" switch \initial - attribute \src "libresoc.v:34310.9-34310.17" + attribute \src "libresoc.v:34358.9-34358.17" case 1'1 case end @@ -52240,14 +52276,14 @@ module \branch0 sync always update \req_l_s_req$next $0\req_l_s_req$next[2:0]$1233 end - attribute \src "libresoc.v:34318.3-34326.6" - process $proc$libresoc.v:34318$1235 + attribute \src "libresoc.v:34366.3-34374.6" + process $proc$libresoc.v:34366$1235 assign { } { } assign { } { } assign $0\req_l_r_req$next[2:0]$1236 $1\req_l_r_req$next[2:0]$1237 - attribute \src "libresoc.v:34319.5-34319.29" + attribute \src "libresoc.v:34367.5-34367.29" switch \initial - attribute \src "libresoc.v:34319.9-34319.17" + attribute \src "libresoc.v:34367.9-34367.17" case 1'1 case end @@ -52263,8 +52299,8 @@ module \branch0 sync always update \req_l_r_req$next $0\req_l_r_req$next[2:0]$1236 end - attribute \src "libresoc.v:34327.3-34351.6" - process $proc$libresoc.v:34327$1238 + attribute \src "libresoc.v:34375.3-34399.6" + process $proc$libresoc.v:34375$1238 assign { } { } assign { } { } assign { } { } @@ -52291,9 +52327,9 @@ module \branch0 assign $0\alu_branch0_br_op__lk$next[0:0]$1246 $1\alu_branch0_br_op__lk$next[0:0]$1254 assign $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 assign $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 - attribute \src "libresoc.v:34328.5-34328.29" + attribute \src "libresoc.v:34376.5-34376.29" switch \initial - attribute \src "libresoc.v:34328.9-34328.17" + attribute \src "libresoc.v:34376.9-34376.17" case 1'1 case end @@ -52342,8 +52378,8 @@ module \branch0 update \alu_branch0_br_op__is_32bit$next $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 update \alu_branch0_br_op__lk$next $0\alu_branch0_br_op__lk$next[0:0]$1246 end - attribute \src "libresoc.v:34352.3-34373.6" - process $proc$libresoc.v:34352$1257 + attribute \src "libresoc.v:34400.3-34421.6" + process $proc$libresoc.v:34400$1257 assign { } { } assign { } { } assign { } { } @@ -52353,9 +52389,9 @@ module \branch0 assign $0\data_r0__fast1$next[63:0]$1258 $2\data_r0__fast1$next[63:0]$1262 assign { } { } assign $0\data_r0__fast1_ok$next[0:0]$1259 $3\data_r0__fast1_ok$next[0:0]$1264 - attribute \src "libresoc.v:34353.5-34353.29" + attribute \src "libresoc.v:34401.5-34401.29" switch \initial - attribute \src "libresoc.v:34353.9-34353.17" + attribute \src "libresoc.v:34401.9-34401.17" case 1'1 case end @@ -52394,8 +52430,8 @@ module \branch0 update \data_r0__fast1$next $0\data_r0__fast1$next[63:0]$1258 update \data_r0__fast1_ok$next $0\data_r0__fast1_ok$next[0:0]$1259 end - attribute \src "libresoc.v:34374.3-34395.6" - process $proc$libresoc.v:34374$1265 + attribute \src "libresoc.v:34422.3-34443.6" + process $proc$libresoc.v:34422$1265 assign { } { } assign { } { } assign { } { } @@ -52405,9 +52441,9 @@ module \branch0 assign $0\data_r1__fast2$next[63:0]$1266 $2\data_r1__fast2$next[63:0]$1270 assign { } { } assign $0\data_r1__fast2_ok$next[0:0]$1267 $3\data_r1__fast2_ok$next[0:0]$1272 - attribute \src "libresoc.v:34375.5-34375.29" + attribute \src "libresoc.v:34423.5-34423.29" switch \initial - attribute \src "libresoc.v:34375.9-34375.17" + attribute \src "libresoc.v:34423.9-34423.17" case 1'1 case end @@ -52446,8 +52482,8 @@ module \branch0 update \data_r1__fast2$next $0\data_r1__fast2$next[63:0]$1266 update \data_r1__fast2_ok$next $0\data_r1__fast2_ok$next[0:0]$1267 end - attribute \src "libresoc.v:34396.3-34417.6" - process $proc$libresoc.v:34396$1273 + attribute \src "libresoc.v:34444.3-34465.6" + process $proc$libresoc.v:34444$1273 assign { } { } assign { } { } assign { } { } @@ -52457,9 +52493,9 @@ module \branch0 assign $0\data_r2__nia$next[63:0]$1274 $2\data_r2__nia$next[63:0]$1278 assign { } { } assign $0\data_r2__nia_ok$next[0:0]$1275 $3\data_r2__nia_ok$next[0:0]$1280 - attribute \src "libresoc.v:34397.5-34397.29" + attribute \src "libresoc.v:34445.5-34445.29" switch \initial - attribute \src "libresoc.v:34397.9-34397.17" + attribute \src "libresoc.v:34445.9-34445.17" case 1'1 case end @@ -52498,14 +52534,14 @@ module \branch0 update \data_r2__nia$next $0\data_r2__nia$next[63:0]$1274 update \data_r2__nia_ok$next $0\data_r2__nia_ok$next[0:0]$1275 end - attribute \src "libresoc.v:34418.3-34427.6" - process $proc$libresoc.v:34418$1281 + attribute \src "libresoc.v:34466.3-34475.6" + process $proc$libresoc.v:34466$1281 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$1282 $1\src_r0$next[63:0]$1283 - attribute \src "libresoc.v:34419.5-34419.29" + attribute \src "libresoc.v:34467.5-34467.29" switch \initial - attribute \src "libresoc.v:34419.9-34419.17" + attribute \src "libresoc.v:34467.9-34467.17" case 1'1 case end @@ -52521,14 +52557,14 @@ module \branch0 sync always update \src_r0$next $0\src_r0$next[63:0]$1282 end - attribute \src "libresoc.v:34428.3-34437.6" - process $proc$libresoc.v:34428$1284 + attribute \src "libresoc.v:34476.3-34485.6" + process $proc$libresoc.v:34476$1284 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$1285 $1\src_r1$next[63:0]$1286 - attribute \src "libresoc.v:34429.5-34429.29" + attribute \src "libresoc.v:34477.5-34477.29" switch \initial - attribute \src "libresoc.v:34429.9-34429.17" + attribute \src "libresoc.v:34477.9-34477.17" case 1'1 case end @@ -52544,14 +52580,14 @@ module \branch0 sync always update \src_r1$next $0\src_r1$next[63:0]$1285 end - attribute \src "libresoc.v:34438.3-34447.6" - process $proc$libresoc.v:34438$1287 + attribute \src "libresoc.v:34486.3-34495.6" + process $proc$libresoc.v:34486$1287 assign { } { } assign { } { } assign $0\src_r2$next[3:0]$1288 $1\src_r2$next[3:0]$1289 - attribute \src "libresoc.v:34439.5-34439.29" + attribute \src "libresoc.v:34487.5-34487.29" switch \initial - attribute \src "libresoc.v:34439.9-34439.17" + attribute \src "libresoc.v:34487.9-34487.17" case 1'1 case end @@ -52567,14 +52603,14 @@ module \branch0 sync always update \src_r2$next $0\src_r2$next[3:0]$1288 end - attribute \src "libresoc.v:34448.3-34456.6" - process $proc$libresoc.v:34448$1290 + attribute \src "libresoc.v:34496.3-34504.6" + process $proc$libresoc.v:34496$1290 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$1291 $1\alui_l_r_alui$next[0:0]$1292 - attribute \src "libresoc.v:34449.5-34449.29" + attribute \src "libresoc.v:34497.5-34497.29" switch \initial - attribute \src "libresoc.v:34449.9-34449.17" + attribute \src "libresoc.v:34497.9-34497.17" case 1'1 case end @@ -52590,14 +52626,14 @@ module \branch0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$1291 end - attribute \src "libresoc.v:34457.3-34465.6" - process $proc$libresoc.v:34457$1293 + attribute \src "libresoc.v:34505.3-34513.6" + process $proc$libresoc.v:34505$1293 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$1294 $1\alu_l_r_alu$next[0:0]$1295 - attribute \src "libresoc.v:34458.5-34458.29" + attribute \src "libresoc.v:34506.5-34506.29" switch \initial - attribute \src "libresoc.v:34458.9-34458.17" + attribute \src "libresoc.v:34506.9-34506.17" case 1'1 case end @@ -52613,14 +52649,14 @@ module \branch0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$1294 end - attribute \src "libresoc.v:34466.3-34475.6" - process $proc$libresoc.v:34466$1296 + attribute \src "libresoc.v:34514.3-34523.6" + process $proc$libresoc.v:34514$1296 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:34467.5-34467.29" + attribute \src "libresoc.v:34515.5-34515.29" switch \initial - attribute \src "libresoc.v:34467.9-34467.17" + attribute \src "libresoc.v:34515.9-34515.17" case 1'1 case end @@ -52636,14 +52672,14 @@ module \branch0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:34476.3-34485.6" - process $proc$libresoc.v:34476$1297 + attribute \src "libresoc.v:34524.3-34533.6" + process $proc$libresoc.v:34524$1297 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:34477.5-34477.29" + attribute \src "libresoc.v:34525.5-34525.29" switch \initial - attribute \src "libresoc.v:34477.9-34477.17" + attribute \src "libresoc.v:34525.9-34525.17" case 1'1 case end @@ -52659,14 +52695,14 @@ module \branch0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:34486.3-34495.6" - process $proc$libresoc.v:34486$1298 + attribute \src "libresoc.v:34534.3-34543.6" + process $proc$libresoc.v:34534$1298 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:34487.5-34487.29" + attribute \src "libresoc.v:34535.5-34535.29" switch \initial - attribute \src "libresoc.v:34487.9-34487.17" + attribute \src "libresoc.v:34535.9-34535.17" case 1'1 case end @@ -52682,14 +52718,14 @@ module \branch0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:34496.3-34504.6" - process $proc$libresoc.v:34496$1299 + attribute \src "libresoc.v:34544.3-34552.6" + process $proc$libresoc.v:34544$1299 assign { } { } assign { } { } assign $0\prev_wr_go$next[2:0]$1300 $1\prev_wr_go$next[2:0]$1301 - attribute \src "libresoc.v:34497.5-34497.29" + attribute \src "libresoc.v:34545.5-34545.29" switch \initial - attribute \src "libresoc.v:34497.9-34497.17" + attribute \src "libresoc.v:34545.9-34545.17" case 1'1 case end @@ -52705,63 +52741,63 @@ module \branch0 sync always update \prev_wr_go$next $0\prev_wr_go$next[2:0]$1300 end - connect \$5 $reduce_and$libresoc.v:34033$1118_Y - connect \$99 $and$libresoc.v:34034$1119_Y - connect \$101 $and$libresoc.v:34035$1120_Y - connect \$103 $and$libresoc.v:34036$1121_Y - connect \$105 $and$libresoc.v:34037$1122_Y - connect \$107 $and$libresoc.v:34038$1123_Y - connect \$109 $and$libresoc.v:34039$1124_Y - connect \$111 $and$libresoc.v:34040$1125_Y - connect \$113 $and$libresoc.v:34041$1126_Y - connect \$115 $and$libresoc.v:34042$1127_Y - connect \$11 $and$libresoc.v:34043$1128_Y - connect \$13 $not$libresoc.v:34044$1129_Y - connect \$15 $and$libresoc.v:34045$1130_Y - connect \$17 $not$libresoc.v:34046$1131_Y - connect \$19 $and$libresoc.v:34047$1132_Y - connect \$21 $and$libresoc.v:34048$1133_Y - connect \$25 $not$libresoc.v:34049$1134_Y - connect \$27 $and$libresoc.v:34050$1135_Y - connect \$24 $reduce_or$libresoc.v:34051$1136_Y - connect \$23 $not$libresoc.v:34052$1137_Y - connect \$31 $and$libresoc.v:34053$1138_Y - connect \$33 $reduce_or$libresoc.v:34054$1139_Y - connect \$35 $reduce_or$libresoc.v:34055$1140_Y - connect \$37 $or$libresoc.v:34056$1141_Y - connect \$3 $and$libresoc.v:34057$1142_Y - connect \$39 $not$libresoc.v:34058$1143_Y - connect \$41 $and$libresoc.v:34059$1144_Y - connect \$43 $and$libresoc.v:34060$1145_Y - connect \$45 $eq$libresoc.v:34061$1146_Y - connect \$47 $and$libresoc.v:34062$1147_Y - connect \$49 $eq$libresoc.v:34063$1148_Y - connect \$51 $and$libresoc.v:34064$1149_Y - connect \$53 $and$libresoc.v:34065$1150_Y - connect \$55 $and$libresoc.v:34066$1151_Y - connect \$57 $or$libresoc.v:34067$1152_Y - connect \$59 $or$libresoc.v:34068$1153_Y - connect \$61 $or$libresoc.v:34069$1154_Y - connect \$63 $or$libresoc.v:34070$1155_Y - connect \$65 $and$libresoc.v:34071$1156_Y - connect \$67 $and$libresoc.v:34072$1157_Y - connect \$6 $not$libresoc.v:34073$1158_Y - connect \$69 $or$libresoc.v:34074$1159_Y - connect \$71 $and$libresoc.v:34075$1160_Y - connect \$73 $and$libresoc.v:34076$1161_Y - connect \$75 $and$libresoc.v:34077$1162_Y - connect \$77 $ternary$libresoc.v:34078$1163_Y - connect \$79 $ternary$libresoc.v:34079$1164_Y - connect \$81 $ternary$libresoc.v:34080$1165_Y - connect \$83 $ternary$libresoc.v:34081$1166_Y - connect \$85 $ternary$libresoc.v:34082$1167_Y - connect \$87 $and$libresoc.v:34083$1168_Y - connect \$8 $or$libresoc.v:34084$1169_Y - connect \$89 $and$libresoc.v:34085$1170_Y - connect \$91 $and$libresoc.v:34086$1171_Y - connect \$93 $not$libresoc.v:34087$1172_Y - connect \$95 $and$libresoc.v:34088$1173_Y - connect \$97 $not$libresoc.v:34089$1174_Y + connect \$5 $reduce_and$libresoc.v:34081$1118_Y + connect \$99 $and$libresoc.v:34082$1119_Y + connect \$101 $and$libresoc.v:34083$1120_Y + connect \$103 $and$libresoc.v:34084$1121_Y + connect \$105 $and$libresoc.v:34085$1122_Y + connect \$107 $and$libresoc.v:34086$1123_Y + connect \$109 $and$libresoc.v:34087$1124_Y + connect \$111 $and$libresoc.v:34088$1125_Y + connect \$113 $and$libresoc.v:34089$1126_Y + connect \$115 $and$libresoc.v:34090$1127_Y + connect \$11 $and$libresoc.v:34091$1128_Y + connect \$13 $not$libresoc.v:34092$1129_Y + connect \$15 $and$libresoc.v:34093$1130_Y + connect \$17 $not$libresoc.v:34094$1131_Y + connect \$19 $and$libresoc.v:34095$1132_Y + connect \$21 $and$libresoc.v:34096$1133_Y + connect \$25 $not$libresoc.v:34097$1134_Y + connect \$27 $and$libresoc.v:34098$1135_Y + connect \$24 $reduce_or$libresoc.v:34099$1136_Y + connect \$23 $not$libresoc.v:34100$1137_Y + connect \$31 $and$libresoc.v:34101$1138_Y + connect \$33 $reduce_or$libresoc.v:34102$1139_Y + connect \$35 $reduce_or$libresoc.v:34103$1140_Y + connect \$37 $or$libresoc.v:34104$1141_Y + connect \$3 $and$libresoc.v:34105$1142_Y + connect \$39 $not$libresoc.v:34106$1143_Y + connect \$41 $and$libresoc.v:34107$1144_Y + connect \$43 $and$libresoc.v:34108$1145_Y + connect \$45 $eq$libresoc.v:34109$1146_Y + connect \$47 $and$libresoc.v:34110$1147_Y + connect \$49 $eq$libresoc.v:34111$1148_Y + connect \$51 $and$libresoc.v:34112$1149_Y + connect \$53 $and$libresoc.v:34113$1150_Y + connect \$55 $and$libresoc.v:34114$1151_Y + connect \$57 $or$libresoc.v:34115$1152_Y + connect \$59 $or$libresoc.v:34116$1153_Y + connect \$61 $or$libresoc.v:34117$1154_Y + connect \$63 $or$libresoc.v:34118$1155_Y + connect \$65 $and$libresoc.v:34119$1156_Y + connect \$67 $and$libresoc.v:34120$1157_Y + connect \$6 $not$libresoc.v:34121$1158_Y + connect \$69 $or$libresoc.v:34122$1159_Y + connect \$71 $and$libresoc.v:34123$1160_Y + connect \$73 $and$libresoc.v:34124$1161_Y + connect \$75 $and$libresoc.v:34125$1162_Y + connect \$77 $ternary$libresoc.v:34126$1163_Y + connect \$79 $ternary$libresoc.v:34127$1164_Y + connect \$81 $ternary$libresoc.v:34128$1165_Y + connect \$83 $ternary$libresoc.v:34129$1166_Y + connect \$85 $ternary$libresoc.v:34130$1167_Y + connect \$87 $and$libresoc.v:34131$1168_Y + connect \$8 $or$libresoc.v:34132$1169_Y + connect \$89 $and$libresoc.v:34133$1170_Y + connect \$91 $and$libresoc.v:34134$1171_Y + connect \$93 $not$libresoc.v:34135$1172_Y + connect \$95 $and$libresoc.v:34136$1173_Y + connect \$97 $not$libresoc.v:34137$1174_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 @@ -52793,37 +52829,37 @@ module \branch0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:34539.1-34597.10" +attribute \src "libresoc.v:34587.1-34645.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.busy_l" attribute \generator "nMigen" module \busy_l - attribute \src "libresoc.v:34540.7-34540.20" + attribute \src "libresoc.v:34588.7-34588.20" wire $0\initial[0:0] - attribute \src "libresoc.v:34585.3-34593.6" + attribute \src "libresoc.v:34633.3-34641.6" wire $0\q_int$next[0:0]$1345 - attribute \src "libresoc.v:34583.3-34584.27" + attribute \src "libresoc.v:34631.3-34632.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:34585.3-34593.6" + attribute \src "libresoc.v:34633.3-34641.6" wire $1\q_int$next[0:0]$1346 - attribute \src "libresoc.v:34564.7-34564.19" + attribute \src "libresoc.v:34612.7-34612.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:34575.17-34575.96" - wire $and$libresoc.v:34575$1335_Y - attribute \src "libresoc.v:34580.17-34580.96" - wire $and$libresoc.v:34580$1340_Y - attribute \src "libresoc.v:34577.18-34577.94" - wire $not$libresoc.v:34577$1337_Y - attribute \src "libresoc.v:34579.17-34579.93" - wire $not$libresoc.v:34579$1339_Y - attribute \src "libresoc.v:34582.17-34582.93" - wire $not$libresoc.v:34582$1342_Y - attribute \src "libresoc.v:34576.18-34576.99" - wire $or$libresoc.v:34576$1336_Y - attribute \src "libresoc.v:34578.18-34578.100" - wire $or$libresoc.v:34578$1338_Y - attribute \src "libresoc.v:34581.17-34581.98" - wire $or$libresoc.v:34581$1341_Y + attribute \src "libresoc.v:34623.17-34623.96" + wire $and$libresoc.v:34623$1335_Y + attribute \src "libresoc.v:34628.17-34628.96" + wire $and$libresoc.v:34628$1340_Y + attribute \src "libresoc.v:34625.18-34625.94" + wire $not$libresoc.v:34625$1337_Y + attribute \src "libresoc.v:34627.17-34627.93" + wire $not$libresoc.v:34627$1339_Y + attribute \src "libresoc.v:34630.17-34630.93" + wire $not$libresoc.v:34630$1342_Y + attribute \src "libresoc.v:34624.18-34624.99" + wire $or$libresoc.v:34624$1336_Y + attribute \src "libresoc.v:34626.18-34626.100" + wire $or$libresoc.v:34626$1338_Y + attribute \src "libresoc.v:34629.17-34629.98" + wire $or$libresoc.v:34629$1341_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -52840,11 +52876,11 @@ module \busy_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:34540.7-34540.15" + attribute \src "libresoc.v:34588.7-34588.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_busy @@ -52861,7 +52897,7 @@ module \busy_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:34575$1335 + cell $and $and$libresoc.v:34623$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52869,10 +52905,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:34575$1335_Y + connect \Y $and$libresoc.v:34623$1335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:34580$1340 + cell $and $and$libresoc.v:34628$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52880,34 +52916,34 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:34580$1340_Y + connect \Y $and$libresoc.v:34628$1340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:34577$1337 + cell $not $not$libresoc.v:34625$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_busy - connect \Y $not$libresoc.v:34577$1337_Y + connect \Y $not$libresoc.v:34625$1337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:34579$1339 + cell $not $not$libresoc.v:34627$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_busy - connect \Y $not$libresoc.v:34579$1339_Y + connect \Y $not$libresoc.v:34627$1339_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:34582$1342 + cell $not $not$libresoc.v:34630$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_busy - connect \Y $not$libresoc.v:34582$1342_Y + connect \Y $not$libresoc.v:34630$1342_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:34576$1336 + cell $or $or$libresoc.v:34624$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52915,10 +52951,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_busy - connect \Y $or$libresoc.v:34576$1336_Y + connect \Y $or$libresoc.v:34624$1336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:34578$1338 + cell $or $or$libresoc.v:34626$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52926,10 +52962,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_busy connect \B \q_int - connect \Y $or$libresoc.v:34578$1338_Y + connect \Y $or$libresoc.v:34626$1338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:34581$1341 + cell $or $or$libresoc.v:34629$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52937,39 +52973,39 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_busy - connect \Y $or$libresoc.v:34581$1341_Y + connect \Y $or$libresoc.v:34629$1341_Y end - attribute \src "libresoc.v:34540.7-34540.20" - process $proc$libresoc.v:34540$1347 + attribute \src "libresoc.v:34588.7-34588.20" + process $proc$libresoc.v:34588$1347 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:34564.7-34564.19" - process $proc$libresoc.v:34564$1348 + attribute \src "libresoc.v:34612.7-34612.19" + process $proc$libresoc.v:34612$1348 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:34583.3-34584.27" - process $proc$libresoc.v:34583$1343 + attribute \src "libresoc.v:34631.3-34632.27" + process $proc$libresoc.v:34631$1343 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:34585.3-34593.6" - process $proc$libresoc.v:34585$1344 + attribute \src "libresoc.v:34633.3-34641.6" + process $proc$libresoc.v:34633$1344 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1345 $1\q_int$next[0:0]$1346 - attribute \src "libresoc.v:34586.5-34586.29" + attribute \src "libresoc.v:34634.5-34634.29" switch \initial - attribute \src "libresoc.v:34586.9-34586.17" + attribute \src "libresoc.v:34634.9-34634.17" case 1'1 case end @@ -52985,525 +53021,525 @@ module \busy_l sync always update \q_int$next $0\q_int$next[0:0]$1345 end - connect \$9 $and$libresoc.v:34575$1335_Y - connect \$11 $or$libresoc.v:34576$1336_Y - connect \$13 $not$libresoc.v:34577$1337_Y - connect \$15 $or$libresoc.v:34578$1338_Y - connect \$1 $not$libresoc.v:34579$1339_Y - connect \$3 $and$libresoc.v:34580$1340_Y - connect \$5 $or$libresoc.v:34581$1341_Y - connect \$7 $not$libresoc.v:34582$1342_Y + connect \$9 $and$libresoc.v:34623$1335_Y + connect \$11 $or$libresoc.v:34624$1336_Y + connect \$13 $not$libresoc.v:34625$1337_Y + connect \$15 $or$libresoc.v:34626$1338_Y + connect \$1 $not$libresoc.v:34627$1339_Y + connect \$3 $and$libresoc.v:34628$1340_Y + connect \$5 $or$libresoc.v:34629$1341_Y + connect \$7 $not$libresoc.v:34630$1342_Y connect \qlq_busy \$15 connect \qn_busy \$13 connect \q_busy \$11 end -attribute \src "libresoc.v:34601.1-36209.10" +attribute \src "libresoc.v:34649.1-36257.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" attribute \generator "nMigen" module \clz - attribute \src "libresoc.v:35076.3-35090.6" + attribute \src "libresoc.v:35124.3-35138.6" wire width 2 $0\cnt_1_0[1:0] - attribute \src "libresoc.v:35166.3-35180.6" + attribute \src "libresoc.v:35214.3-35228.6" wire width 2 $0\cnt_1_10[1:0] - attribute \src "libresoc.v:35181.3-35195.6" + attribute \src "libresoc.v:35229.3-35243.6" wire width 2 $0\cnt_1_11[1:0] - attribute \src "libresoc.v:35196.3-35210.6" + attribute \src "libresoc.v:35244.3-35258.6" wire width 2 $0\cnt_1_12[1:0] - attribute \src "libresoc.v:35211.3-35225.6" + attribute \src "libresoc.v:35259.3-35273.6" wire width 2 $0\cnt_1_13[1:0] - attribute \src "libresoc.v:35226.3-35240.6" + attribute \src "libresoc.v:35274.3-35288.6" wire width 2 $0\cnt_1_14[1:0] - attribute \src "libresoc.v:35256.3-35270.6" + attribute \src "libresoc.v:35304.3-35318.6" wire width 2 $0\cnt_1_15[1:0] - attribute \src "libresoc.v:35271.3-35285.6" + attribute \src "libresoc.v:35319.3-35333.6" wire width 2 $0\cnt_1_16[1:0] - attribute \src "libresoc.v:35286.3-35300.6" + attribute \src "libresoc.v:35334.3-35348.6" wire width 2 $0\cnt_1_17[1:0] - attribute \src "libresoc.v:35301.3-35315.6" + attribute \src "libresoc.v:35349.3-35363.6" wire width 2 $0\cnt_1_18[1:0] - attribute \src "libresoc.v:35316.3-35330.6" + attribute \src "libresoc.v:35364.3-35378.6" wire width 2 $0\cnt_1_19[1:0] - attribute \src "libresoc.v:35241.3-35255.6" + attribute \src "libresoc.v:35289.3-35303.6" wire width 2 $0\cnt_1_1[1:0] - attribute \src "libresoc.v:35331.3-35345.6" + attribute \src "libresoc.v:35379.3-35393.6" wire width 2 $0\cnt_1_20[1:0] - attribute \src "libresoc.v:35346.3-35360.6" + attribute \src "libresoc.v:35394.3-35408.6" wire width 2 $0\cnt_1_21[1:0] - attribute \src "libresoc.v:35361.3-35375.6" + attribute \src "libresoc.v:35409.3-35423.6" wire width 2 $0\cnt_1_22[1:0] - attribute \src "libresoc.v:35376.3-35390.6" + attribute \src "libresoc.v:35424.3-35438.6" wire width 2 $0\cnt_1_23[1:0] - attribute \src "libresoc.v:35391.3-35405.6" + attribute \src "libresoc.v:35439.3-35453.6" wire width 2 $0\cnt_1_24[1:0] - attribute \src "libresoc.v:35421.3-35435.6" + attribute \src "libresoc.v:35469.3-35483.6" wire width 2 $0\cnt_1_25[1:0] - attribute \src "libresoc.v:35436.3-35450.6" + attribute \src "libresoc.v:35484.3-35498.6" wire width 2 $0\cnt_1_26[1:0] - attribute \src "libresoc.v:35451.3-35465.6" + attribute \src "libresoc.v:35499.3-35513.6" wire width 2 $0\cnt_1_27[1:0] - attribute \src "libresoc.v:35466.3-35480.6" + attribute \src "libresoc.v:35514.3-35528.6" wire width 2 $0\cnt_1_28[1:0] - attribute \src "libresoc.v:35481.3-35495.6" + attribute \src "libresoc.v:35529.3-35543.6" wire width 2 $0\cnt_1_29[1:0] - attribute \src "libresoc.v:35406.3-35420.6" + attribute \src "libresoc.v:35454.3-35468.6" wire width 2 $0\cnt_1_2[1:0] - attribute \src "libresoc.v:35496.3-35510.6" + attribute \src "libresoc.v:35544.3-35558.6" wire width 2 $0\cnt_1_30[1:0] - attribute \src "libresoc.v:35511.3-35525.6" + attribute \src "libresoc.v:35559.3-35573.6" wire width 2 $0\cnt_1_31[1:0] - attribute \src "libresoc.v:35646.3-35660.6" + attribute \src "libresoc.v:35694.3-35708.6" wire width 2 $0\cnt_1_3[1:0] - attribute \src "libresoc.v:36061.3-36075.6" + attribute \src "libresoc.v:36109.3-36123.6" wire width 2 $0\cnt_1_4[1:0] - attribute \src "libresoc.v:35091.3-35105.6" + attribute \src "libresoc.v:35139.3-35153.6" wire width 2 $0\cnt_1_5[1:0] - attribute \src "libresoc.v:35106.3-35120.6" + attribute \src "libresoc.v:35154.3-35168.6" wire width 2 $0\cnt_1_6[1:0] - attribute \src "libresoc.v:35121.3-35135.6" + attribute \src "libresoc.v:35169.3-35183.6" wire width 2 $0\cnt_1_7[1:0] - attribute \src "libresoc.v:35136.3-35150.6" + attribute \src "libresoc.v:35184.3-35198.6" wire width 2 $0\cnt_1_8[1:0] - attribute \src "libresoc.v:35151.3-35165.6" + attribute \src "libresoc.v:35199.3-35213.6" wire width 2 $0\cnt_1_9[1:0] - attribute \src "libresoc.v:35526.3-35545.6" + attribute \src "libresoc.v:35574.3-35593.6" wire width 3 $0\cnt_2_0[2:0] - attribute \src "libresoc.v:35626.3-35645.6" + attribute \src "libresoc.v:35674.3-35693.6" wire width 3 $0\cnt_2_10[2:0] - attribute \src "libresoc.v:35661.3-35680.6" + attribute \src "libresoc.v:35709.3-35728.6" wire width 3 $0\cnt_2_12[2:0] - attribute \src "libresoc.v:35681.3-35700.6" + attribute \src "libresoc.v:35729.3-35748.6" wire width 3 $0\cnt_2_14[2:0] - attribute \src "libresoc.v:35701.3-35720.6" + attribute \src "libresoc.v:35749.3-35768.6" wire width 3 $0\cnt_2_16[2:0] - attribute \src "libresoc.v:35721.3-35740.6" + attribute \src "libresoc.v:35769.3-35788.6" wire width 3 $0\cnt_2_18[2:0] - attribute \src "libresoc.v:35741.3-35760.6" + attribute \src "libresoc.v:35789.3-35808.6" wire width 3 $0\cnt_2_20[2:0] - attribute \src "libresoc.v:35761.3-35780.6" + attribute \src "libresoc.v:35809.3-35828.6" wire width 3 $0\cnt_2_22[2:0] - attribute \src "libresoc.v:35781.3-35800.6" + attribute \src "libresoc.v:35829.3-35848.6" wire width 3 $0\cnt_2_24[2:0] - attribute \src "libresoc.v:35801.3-35820.6" + attribute \src "libresoc.v:35849.3-35868.6" wire width 3 $0\cnt_2_26[2:0] - attribute \src "libresoc.v:35821.3-35840.6" + attribute \src "libresoc.v:35869.3-35888.6" wire width 3 $0\cnt_2_28[2:0] - attribute \src "libresoc.v:35546.3-35565.6" + attribute \src "libresoc.v:35594.3-35613.6" wire width 3 $0\cnt_2_2[2:0] - attribute \src "libresoc.v:35841.3-35860.6" + attribute \src "libresoc.v:35889.3-35908.6" wire width 3 $0\cnt_2_30[2:0] - attribute \src "libresoc.v:35566.3-35585.6" + attribute \src "libresoc.v:35614.3-35633.6" wire width 3 $0\cnt_2_4[2:0] - attribute \src "libresoc.v:35586.3-35605.6" + attribute \src "libresoc.v:35634.3-35653.6" wire width 3 $0\cnt_2_6[2:0] - attribute \src "libresoc.v:35606.3-35625.6" + attribute \src "libresoc.v:35654.3-35673.6" wire width 3 $0\cnt_2_8[2:0] - attribute \src "libresoc.v:35861.3-35880.6" + attribute \src "libresoc.v:35909.3-35928.6" wire width 4 $0\cnt_3_0[3:0] - attribute \src "libresoc.v:35961.3-35980.6" + attribute \src "libresoc.v:36009.3-36028.6" wire width 4 $0\cnt_3_10[3:0] - attribute \src "libresoc.v:35981.3-36000.6" + attribute \src "libresoc.v:36029.3-36048.6" wire width 4 $0\cnt_3_12[3:0] - attribute \src "libresoc.v:36001.3-36020.6" + attribute \src "libresoc.v:36049.3-36068.6" wire width 4 $0\cnt_3_14[3:0] - attribute \src "libresoc.v:35881.3-35900.6" + attribute \src "libresoc.v:35929.3-35948.6" wire width 4 $0\cnt_3_2[3:0] - attribute \src "libresoc.v:35901.3-35920.6" + attribute \src "libresoc.v:35949.3-35968.6" wire width 4 $0\cnt_3_4[3:0] - attribute \src "libresoc.v:35921.3-35940.6" + attribute \src "libresoc.v:35969.3-35988.6" wire width 4 $0\cnt_3_6[3:0] - attribute \src "libresoc.v:35941.3-35960.6" + attribute \src "libresoc.v:35989.3-36008.6" wire width 4 $0\cnt_3_8[3:0] - attribute \src "libresoc.v:36021.3-36040.6" + attribute \src "libresoc.v:36069.3-36088.6" wire width 5 $0\cnt_4_0[4:0] - attribute \src "libresoc.v:36041.3-36060.6" + attribute \src "libresoc.v:36089.3-36108.6" wire width 5 $0\cnt_4_2[4:0] - attribute \src "libresoc.v:36076.3-36095.6" + attribute \src "libresoc.v:36124.3-36143.6" wire width 5 $0\cnt_4_4[4:0] - attribute \src "libresoc.v:36096.3-36115.6" + attribute \src "libresoc.v:36144.3-36163.6" wire width 5 $0\cnt_4_6[4:0] - attribute \src "libresoc.v:36116.3-36135.6" + attribute \src "libresoc.v:36164.3-36183.6" wire width 6 $0\cnt_5_0[5:0] - attribute \src "libresoc.v:36136.3-36155.6" + attribute \src "libresoc.v:36184.3-36203.6" wire width 6 $0\cnt_5_2[5:0] - attribute \src "libresoc.v:36156.3-36175.6" + attribute \src "libresoc.v:36204.3-36223.6" wire width 7 $0\cnt_6_0[6:0] - attribute \src "libresoc.v:34602.7-34602.20" + attribute \src "libresoc.v:34650.7-34650.20" wire $0\initial[0:0] - attribute \src "libresoc.v:35076.3-35090.6" + attribute \src "libresoc.v:35124.3-35138.6" wire width 2 $1\cnt_1_0[1:0] - attribute \src "libresoc.v:35166.3-35180.6" + attribute \src "libresoc.v:35214.3-35228.6" wire width 2 $1\cnt_1_10[1:0] - attribute \src "libresoc.v:35181.3-35195.6" + attribute \src "libresoc.v:35229.3-35243.6" wire width 2 $1\cnt_1_11[1:0] - attribute \src "libresoc.v:35196.3-35210.6" + attribute \src "libresoc.v:35244.3-35258.6" wire width 2 $1\cnt_1_12[1:0] - attribute \src "libresoc.v:35211.3-35225.6" + attribute \src "libresoc.v:35259.3-35273.6" wire width 2 $1\cnt_1_13[1:0] - attribute \src "libresoc.v:35226.3-35240.6" + attribute \src "libresoc.v:35274.3-35288.6" wire width 2 $1\cnt_1_14[1:0] - attribute \src "libresoc.v:35256.3-35270.6" + attribute \src "libresoc.v:35304.3-35318.6" wire width 2 $1\cnt_1_15[1:0] - attribute \src "libresoc.v:35271.3-35285.6" + attribute \src "libresoc.v:35319.3-35333.6" wire width 2 $1\cnt_1_16[1:0] - attribute \src "libresoc.v:35286.3-35300.6" + attribute \src "libresoc.v:35334.3-35348.6" wire width 2 $1\cnt_1_17[1:0] - attribute \src "libresoc.v:35301.3-35315.6" + attribute \src "libresoc.v:35349.3-35363.6" wire width 2 $1\cnt_1_18[1:0] - attribute \src "libresoc.v:35316.3-35330.6" + attribute \src "libresoc.v:35364.3-35378.6" wire width 2 $1\cnt_1_19[1:0] - attribute \src "libresoc.v:35241.3-35255.6" + attribute \src "libresoc.v:35289.3-35303.6" wire width 2 $1\cnt_1_1[1:0] - attribute \src "libresoc.v:35331.3-35345.6" + attribute \src "libresoc.v:35379.3-35393.6" wire width 2 $1\cnt_1_20[1:0] - attribute \src "libresoc.v:35346.3-35360.6" + attribute \src "libresoc.v:35394.3-35408.6" wire width 2 $1\cnt_1_21[1:0] - attribute \src "libresoc.v:35361.3-35375.6" + attribute \src "libresoc.v:35409.3-35423.6" wire width 2 $1\cnt_1_22[1:0] - attribute \src "libresoc.v:35376.3-35390.6" + attribute \src "libresoc.v:35424.3-35438.6" wire width 2 $1\cnt_1_23[1:0] - attribute \src "libresoc.v:35391.3-35405.6" + attribute \src "libresoc.v:35439.3-35453.6" wire width 2 $1\cnt_1_24[1:0] - attribute \src "libresoc.v:35421.3-35435.6" + attribute \src "libresoc.v:35469.3-35483.6" wire width 2 $1\cnt_1_25[1:0] - attribute \src "libresoc.v:35436.3-35450.6" + attribute \src "libresoc.v:35484.3-35498.6" wire width 2 $1\cnt_1_26[1:0] - attribute \src "libresoc.v:35451.3-35465.6" + attribute \src "libresoc.v:35499.3-35513.6" wire width 2 $1\cnt_1_27[1:0] - attribute \src "libresoc.v:35466.3-35480.6" + attribute \src "libresoc.v:35514.3-35528.6" wire width 2 $1\cnt_1_28[1:0] - attribute \src "libresoc.v:35481.3-35495.6" + attribute \src "libresoc.v:35529.3-35543.6" wire width 2 $1\cnt_1_29[1:0] - attribute \src "libresoc.v:35406.3-35420.6" + attribute \src "libresoc.v:35454.3-35468.6" wire width 2 $1\cnt_1_2[1:0] - attribute \src "libresoc.v:35496.3-35510.6" + attribute \src "libresoc.v:35544.3-35558.6" wire width 2 $1\cnt_1_30[1:0] - attribute \src "libresoc.v:35511.3-35525.6" + attribute \src "libresoc.v:35559.3-35573.6" wire width 2 $1\cnt_1_31[1:0] - attribute \src "libresoc.v:35646.3-35660.6" + attribute \src "libresoc.v:35694.3-35708.6" wire width 2 $1\cnt_1_3[1:0] - attribute \src "libresoc.v:36061.3-36075.6" + attribute \src "libresoc.v:36109.3-36123.6" wire width 2 $1\cnt_1_4[1:0] - attribute \src "libresoc.v:35091.3-35105.6" + attribute \src "libresoc.v:35139.3-35153.6" wire width 2 $1\cnt_1_5[1:0] - attribute \src "libresoc.v:35106.3-35120.6" + attribute \src "libresoc.v:35154.3-35168.6" wire width 2 $1\cnt_1_6[1:0] - attribute \src "libresoc.v:35121.3-35135.6" + attribute \src "libresoc.v:35169.3-35183.6" wire width 2 $1\cnt_1_7[1:0] - attribute \src "libresoc.v:35136.3-35150.6" + attribute \src "libresoc.v:35184.3-35198.6" wire width 2 $1\cnt_1_8[1:0] - attribute \src "libresoc.v:35151.3-35165.6" + attribute \src "libresoc.v:35199.3-35213.6" wire width 2 $1\cnt_1_9[1:0] - attribute \src "libresoc.v:35526.3-35545.6" + attribute \src "libresoc.v:35574.3-35593.6" wire width 3 $1\cnt_2_0[2:0] - attribute \src "libresoc.v:35626.3-35645.6" + attribute \src "libresoc.v:35674.3-35693.6" wire width 3 $1\cnt_2_10[2:0] - attribute \src "libresoc.v:35661.3-35680.6" + attribute \src "libresoc.v:35709.3-35728.6" wire width 3 $1\cnt_2_12[2:0] - attribute \src "libresoc.v:35681.3-35700.6" + attribute \src "libresoc.v:35729.3-35748.6" wire width 3 $1\cnt_2_14[2:0] - attribute \src "libresoc.v:35701.3-35720.6" + attribute \src "libresoc.v:35749.3-35768.6" wire width 3 $1\cnt_2_16[2:0] - attribute \src "libresoc.v:35721.3-35740.6" + attribute \src "libresoc.v:35769.3-35788.6" wire width 3 $1\cnt_2_18[2:0] - attribute \src "libresoc.v:35741.3-35760.6" + attribute \src "libresoc.v:35789.3-35808.6" wire width 3 $1\cnt_2_20[2:0] - attribute \src "libresoc.v:35761.3-35780.6" + attribute \src "libresoc.v:35809.3-35828.6" wire width 3 $1\cnt_2_22[2:0] - attribute \src "libresoc.v:35781.3-35800.6" + attribute \src "libresoc.v:35829.3-35848.6" wire width 3 $1\cnt_2_24[2:0] - attribute \src "libresoc.v:35801.3-35820.6" + attribute \src "libresoc.v:35849.3-35868.6" wire width 3 $1\cnt_2_26[2:0] - attribute \src "libresoc.v:35821.3-35840.6" + attribute \src "libresoc.v:35869.3-35888.6" wire width 3 $1\cnt_2_28[2:0] - attribute \src "libresoc.v:35546.3-35565.6" + attribute \src "libresoc.v:35594.3-35613.6" wire width 3 $1\cnt_2_2[2:0] - attribute \src "libresoc.v:35841.3-35860.6" + attribute \src "libresoc.v:35889.3-35908.6" wire width 3 $1\cnt_2_30[2:0] - attribute \src "libresoc.v:35566.3-35585.6" + attribute \src "libresoc.v:35614.3-35633.6" wire width 3 $1\cnt_2_4[2:0] - attribute \src "libresoc.v:35586.3-35605.6" + attribute \src "libresoc.v:35634.3-35653.6" wire width 3 $1\cnt_2_6[2:0] - attribute \src "libresoc.v:35606.3-35625.6" + attribute \src "libresoc.v:35654.3-35673.6" wire width 3 $1\cnt_2_8[2:0] - attribute \src "libresoc.v:35861.3-35880.6" + attribute \src "libresoc.v:35909.3-35928.6" wire width 4 $1\cnt_3_0[3:0] - attribute \src "libresoc.v:35961.3-35980.6" + attribute \src "libresoc.v:36009.3-36028.6" wire width 4 $1\cnt_3_10[3:0] - attribute \src "libresoc.v:35981.3-36000.6" + attribute \src "libresoc.v:36029.3-36048.6" wire width 4 $1\cnt_3_12[3:0] - attribute \src "libresoc.v:36001.3-36020.6" + attribute \src "libresoc.v:36049.3-36068.6" wire width 4 $1\cnt_3_14[3:0] - attribute \src "libresoc.v:35881.3-35900.6" + attribute \src "libresoc.v:35929.3-35948.6" wire width 4 $1\cnt_3_2[3:0] - attribute \src "libresoc.v:35901.3-35920.6" + attribute \src "libresoc.v:35949.3-35968.6" wire width 4 $1\cnt_3_4[3:0] - attribute \src "libresoc.v:35921.3-35940.6" + attribute \src "libresoc.v:35969.3-35988.6" wire width 4 $1\cnt_3_6[3:0] - attribute \src "libresoc.v:35941.3-35960.6" + attribute \src "libresoc.v:35989.3-36008.6" wire width 4 $1\cnt_3_8[3:0] - attribute \src "libresoc.v:36021.3-36040.6" + attribute \src "libresoc.v:36069.3-36088.6" wire width 5 $1\cnt_4_0[4:0] - attribute \src "libresoc.v:36041.3-36060.6" + attribute \src "libresoc.v:36089.3-36108.6" wire width 5 $1\cnt_4_2[4:0] - attribute \src "libresoc.v:36076.3-36095.6" + attribute \src "libresoc.v:36124.3-36143.6" wire width 5 $1\cnt_4_4[4:0] - attribute \src "libresoc.v:36096.3-36115.6" + attribute \src "libresoc.v:36144.3-36163.6" wire width 5 $1\cnt_4_6[4:0] - attribute \src "libresoc.v:36116.3-36135.6" + attribute \src "libresoc.v:36164.3-36183.6" wire width 6 $1\cnt_5_0[5:0] - attribute \src "libresoc.v:36136.3-36155.6" + attribute \src "libresoc.v:36184.3-36203.6" wire width 6 $1\cnt_5_2[5:0] - attribute \src "libresoc.v:36156.3-36175.6" + attribute \src "libresoc.v:36204.3-36223.6" wire width 7 $1\cnt_6_0[6:0] - attribute \src "libresoc.v:35526.3-35545.6" + attribute \src "libresoc.v:35574.3-35593.6" wire width 3 $2\cnt_2_0[2:0] - attribute \src "libresoc.v:35626.3-35645.6" + attribute \src "libresoc.v:35674.3-35693.6" wire width 3 $2\cnt_2_10[2:0] - attribute \src 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attribute \src "libresoc.v:35088.18-35088.103" + wire $eq$libresoc.v:35088$1406_Y + attribute \src "libresoc.v:35090.18-35090.103" + wire $eq$libresoc.v:35090$1408_Y + attribute \src "libresoc.v:35091.17-35091.101" + wire $eq$libresoc.v:35091$1409_Y + attribute \src "libresoc.v:35092.18-35092.103" + wire $eq$libresoc.v:35092$1410_Y + attribute \src "libresoc.v:35094.18-35094.103" + wire $eq$libresoc.v:35094$1412_Y + attribute \src "libresoc.v:35095.18-35095.103" + wire $eq$libresoc.v:35095$1413_Y + attribute \src "libresoc.v:35097.18-35097.103" + wire $eq$libresoc.v:35097$1415_Y + attribute \src "libresoc.v:35098.18-35098.103" + wire $eq$libresoc.v:35098$1416_Y + attribute \src "libresoc.v:35100.18-35100.103" + wire $eq$libresoc.v:35100$1418_Y + attribute \src "libresoc.v:35101.18-35101.103" + wire $eq$libresoc.v:35101$1419_Y + attribute \src "libresoc.v:35104.18-35104.103" + wire $eq$libresoc.v:35104$1422_Y + attribute \src "libresoc.v:35105.18-35105.103" + wire $eq$libresoc.v:35105$1423_Y + attribute \src "libresoc.v:35107.18-35107.103" + wire $eq$libresoc.v:35107$1425_Y + attribute \src "libresoc.v:35108.18-35108.103" + wire $eq$libresoc.v:35108$1426_Y + attribute \src "libresoc.v:35110.18-35110.103" + wire $eq$libresoc.v:35110$1428_Y + attribute \src "libresoc.v:35111.18-35111.103" + wire $eq$libresoc.v:35111$1429_Y + attribute \src "libresoc.v:35113.17-35113.101" + wire $eq$libresoc.v:35113$1431_Y + attribute \src "libresoc.v:35114.18-35114.103" + wire $eq$libresoc.v:35114$1432_Y + attribute \src "libresoc.v:35115.18-35115.103" + wire $eq$libresoc.v:35115$1433_Y + attribute \src "libresoc.v:35117.18-35117.103" + wire $eq$libresoc.v:35117$1435_Y + attribute \src "libresoc.v:35118.18-35118.103" + wire $eq$libresoc.v:35118$1436_Y + attribute \src "libresoc.v:35120.18-35120.103" + wire $eq$libresoc.v:35120$1438_Y + attribute \src "libresoc.v:35121.18-35121.103" + wire $eq$libresoc.v:35121$1439_Y + attribute \src "libresoc.v:35123.18-35123.102" + wire $eq$libresoc.v:35123$1441_Y + attribute \src "libresoc.v:35033.19-35033.109" + wire width 4 $pos$libresoc.v:35033$1351_Y + attribute \src "libresoc.v:35036.19-35036.109" + wire width 4 $pos$libresoc.v:35036$1354_Y + attribute \src "libresoc.v:35039.19-35039.109" + wire width 4 $pos$libresoc.v:35039$1357_Y + attribute \src "libresoc.v:35042.18-35042.106" + wire width 3 $pos$libresoc.v:35042$1360_Y + attribute \src "libresoc.v:35043.19-35043.110" + wire width 4 $pos$libresoc.v:35043$1361_Y + attribute \src "libresoc.v:35046.19-35046.110" + wire width 4 $pos$libresoc.v:35046$1364_Y + attribute \src "libresoc.v:35049.19-35049.110" + wire width 4 $pos$libresoc.v:35049$1367_Y + attribute \src "libresoc.v:35052.19-35052.110" + wire width 4 $pos$libresoc.v:35052$1370_Y + attribute \src "libresoc.v:35056.19-35056.110" + wire width 4 $pos$libresoc.v:35056$1374_Y + attribute \src "libresoc.v:35059.19-35059.109" + wire width 5 $pos$libresoc.v:35059$1377_Y + attribute \src "libresoc.v:35062.19-35062.109" + wire width 5 $pos$libresoc.v:35062$1380_Y + attribute \src "libresoc.v:35066.19-35066.109" + wire width 5 $pos$libresoc.v:35066$1384_Y + attribute \src "libresoc.v:35069.19-35069.110" + wire width 5 $pos$libresoc.v:35069$1387_Y + attribute \src "libresoc.v:35072.19-35072.109" + wire width 6 $pos$libresoc.v:35072$1390_Y + attribute \src "libresoc.v:35075.18-35075.106" + wire width 3 $pos$libresoc.v:35075$1393_Y + attribute \src "libresoc.v:35076.19-35076.109" + wire width 6 $pos$libresoc.v:35076$1394_Y + attribute \src "libresoc.v:35079.19-35079.109" + wire width 7 $pos$libresoc.v:35079$1397_Y + attribute \src "libresoc.v:35083.18-35083.106" + wire width 3 $pos$libresoc.v:35083$1401_Y + attribute \src "libresoc.v:35086.18-35086.106" + wire width 3 $pos$libresoc.v:35086$1404_Y + attribute \src "libresoc.v:35089.18-35089.107" + wire width 3 $pos$libresoc.v:35089$1407_Y + attribute \src "libresoc.v:35093.18-35093.107" + wire width 3 $pos$libresoc.v:35093$1411_Y + attribute \src "libresoc.v:35096.18-35096.107" + wire width 3 $pos$libresoc.v:35096$1414_Y + attribute \src "libresoc.v:35099.18-35099.107" + wire width 3 $pos$libresoc.v:35099$1417_Y + attribute \src "libresoc.v:35102.17-35102.105" + wire width 3 $pos$libresoc.v:35102$1420_Y + attribute \src "libresoc.v:35103.18-35103.107" + wire width 3 $pos$libresoc.v:35103$1421_Y + attribute \src "libresoc.v:35106.18-35106.107" + wire width 3 $pos$libresoc.v:35106$1424_Y + attribute \src "libresoc.v:35109.18-35109.107" + wire width 3 $pos$libresoc.v:35109$1427_Y + attribute \src "libresoc.v:35112.18-35112.107" + wire width 3 $pos$libresoc.v:35112$1430_Y + attribute \src "libresoc.v:35116.18-35116.107" + wire width 3 $pos$libresoc.v:35116$1434_Y + attribute \src "libresoc.v:35119.18-35119.107" + wire width 3 $pos$libresoc.v:35119$1437_Y + attribute \src "libresoc.v:35122.18-35122.107" + wire width 3 $pos$libresoc.v:35122$1440_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" @@ -53816,7 +53852,7 @@ module \clz wire width 6 \cnt_5_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 7 \cnt_6_0 - attribute \src "libresoc.v:34602.7-34602.15" + attribute \src "libresoc.v:34650.7-34650.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" wire width 7 output 1 \lz @@ -53887,7 +53923,7 @@ module \clz attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:16" wire width 64 input 2 \sig_in attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34983$1349 + cell $eq $eq$libresoc.v:35031$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53895,10 +53931,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_2 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34983$1349_Y + connect \Y $eq$libresoc.v:35031$1349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34984$1350 + cell $eq $eq$libresoc.v:35032$1350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53906,10 +53942,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_0 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34984$1350_Y + connect \Y $eq$libresoc.v:35032$1350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34986$1352 + cell $eq $eq$libresoc.v:35034$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53917,10 +53953,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_6 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34986$1352_Y + connect \Y $eq$libresoc.v:35034$1352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34987$1353 + cell $eq $eq$libresoc.v:35035$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53928,10 +53964,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_4 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34987$1353_Y + connect \Y $eq$libresoc.v:35035$1353_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34989$1355 + cell $eq $eq$libresoc.v:35037$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53939,10 +53975,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_10 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34989$1355_Y + connect \Y $eq$libresoc.v:35037$1355_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34990$1356 + cell $eq $eq$libresoc.v:35038$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53950,10 +53986,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_8 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34990$1356_Y + connect \Y $eq$libresoc.v:35038$1356_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34992$1358 + cell $eq $eq$libresoc.v:35040$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53961,10 +53997,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_14 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34992$1358_Y + connect \Y $eq$libresoc.v:35040$1358_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34993$1359 + cell $eq $eq$libresoc.v:35041$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53972,10 +54008,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_12 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34993$1359_Y + connect \Y $eq$libresoc.v:35041$1359_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34996$1362 + cell $eq $eq$libresoc.v:35044$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53983,10 +54019,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_18 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34996$1362_Y + connect \Y $eq$libresoc.v:35044$1362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34997$1363 + cell $eq $eq$libresoc.v:35045$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53994,10 +54030,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_16 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34997$1363_Y + connect \Y $eq$libresoc.v:35045$1363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34999$1365 + cell $eq $eq$libresoc.v:35047$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54005,10 +54041,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_22 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34999$1365_Y + connect \Y $eq$libresoc.v:35047$1365_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35000$1366 + cell $eq $eq$libresoc.v:35048$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54016,10 +54052,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_20 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:35000$1366_Y + connect \Y $eq$libresoc.v:35048$1366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35002$1368 + cell $eq $eq$libresoc.v:35050$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54027,10 +54063,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_26 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:35002$1368_Y + connect \Y $eq$libresoc.v:35050$1368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35003$1369 + cell $eq $eq$libresoc.v:35051$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54038,10 +54074,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_24 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:35003$1369_Y + connect \Y $eq$libresoc.v:35051$1369_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35005$1371 + cell $eq $eq$libresoc.v:35053$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54049,10 +54085,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_5 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35005$1371_Y + connect \Y $eq$libresoc.v:35053$1371_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35006$1372 + cell $eq $eq$libresoc.v:35054$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54060,10 +54096,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_30 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:35006$1372_Y + connect \Y $eq$libresoc.v:35054$1372_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35007$1373 + cell $eq $eq$libresoc.v:35055$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54071,10 +54107,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_28 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:35007$1373_Y + connect \Y $eq$libresoc.v:35055$1373_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35009$1375 + cell $eq $eq$libresoc.v:35057$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54082,10 +54118,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_2 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35009$1375_Y + connect \Y $eq$libresoc.v:35057$1375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35010$1376 + cell $eq $eq$libresoc.v:35058$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54093,10 +54129,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_0 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35010$1376_Y + connect \Y $eq$libresoc.v:35058$1376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35012$1378 + cell $eq $eq$libresoc.v:35060$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54104,10 +54140,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_6 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35012$1378_Y + connect \Y $eq$libresoc.v:35060$1378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35013$1379 + cell $eq $eq$libresoc.v:35061$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54115,10 +54151,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_4 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35013$1379_Y + connect \Y $eq$libresoc.v:35061$1379_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35015$1381 + cell $eq $eq$libresoc.v:35063$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54126,10 +54162,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_10 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35015$1381_Y + connect \Y $eq$libresoc.v:35063$1381_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35016$1382 + cell $eq $eq$libresoc.v:35064$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54137,10 +54173,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_4 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35016$1382_Y + connect \Y $eq$libresoc.v:35064$1382_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35017$1383 + cell $eq $eq$libresoc.v:35065$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54148,10 +54184,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_8 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35017$1383_Y + connect \Y $eq$libresoc.v:35065$1383_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35019$1385 + cell $eq $eq$libresoc.v:35067$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54159,10 +54195,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_14 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35019$1385_Y + connect \Y $eq$libresoc.v:35067$1385_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35020$1386 + cell $eq $eq$libresoc.v:35068$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54170,10 +54206,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_12 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35020$1386_Y + connect \Y $eq$libresoc.v:35068$1386_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35022$1388 + cell $eq $eq$libresoc.v:35070$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54181,10 +54217,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_2 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:35022$1388_Y + connect \Y $eq$libresoc.v:35070$1388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35023$1389 + cell $eq $eq$libresoc.v:35071$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54192,10 +54228,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_0 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:35023$1389_Y + connect \Y $eq$libresoc.v:35071$1389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35025$1391 + cell $eq $eq$libresoc.v:35073$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54203,10 +54239,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_6 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:35025$1391_Y + connect \Y $eq$libresoc.v:35073$1391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35026$1392 + cell $eq $eq$libresoc.v:35074$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54214,10 +54250,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_4 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:35026$1392_Y + connect \Y $eq$libresoc.v:35074$1392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35029$1395 + cell $eq $eq$libresoc.v:35077$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54225,10 +54261,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_5_2 [5] connect \B 1'1 - connect \Y $eq$libresoc.v:35029$1395_Y + connect \Y $eq$libresoc.v:35077$1395_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35030$1396 + cell $eq $eq$libresoc.v:35078$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54236,10 +54272,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_5_0 [5] connect \B 1'1 - connect \Y $eq$libresoc.v:35030$1396_Y + connect \Y $eq$libresoc.v:35078$1396_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35032$1398 + cell $eq $eq$libresoc.v:35080$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54247,10 +54283,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_1 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35032$1398_Y + connect \Y $eq$libresoc.v:35080$1398_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35033$1399 + cell $eq $eq$libresoc.v:35081$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54258,10 +54294,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_7 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35033$1399_Y + connect \Y $eq$libresoc.v:35081$1399_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35034$1400 + cell $eq $eq$libresoc.v:35082$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54269,10 +54305,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_6 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35034$1400_Y + connect \Y $eq$libresoc.v:35082$1400_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35036$1402 + cell $eq $eq$libresoc.v:35084$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54280,10 +54316,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_9 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35036$1402_Y + connect \Y $eq$libresoc.v:35084$1402_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35037$1403 + cell $eq $eq$libresoc.v:35085$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54291,10 +54327,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_8 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35037$1403_Y + connect \Y $eq$libresoc.v:35085$1403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35039$1405 + cell $eq $eq$libresoc.v:35087$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54302,10 +54338,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_11 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35039$1405_Y + connect \Y $eq$libresoc.v:35087$1405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35040$1406 + cell $eq $eq$libresoc.v:35088$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54313,10 +54349,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_10 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35040$1406_Y + connect \Y $eq$libresoc.v:35088$1406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35042$1408 + cell $eq $eq$libresoc.v:35090$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54324,10 +54360,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_13 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35042$1408_Y + connect \Y $eq$libresoc.v:35090$1408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35043$1409 + cell $eq $eq$libresoc.v:35091$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54335,10 +54371,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_0 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35043$1409_Y + connect \Y $eq$libresoc.v:35091$1409_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35044$1410 + cell $eq $eq$libresoc.v:35092$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54346,10 +54382,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_12 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35044$1410_Y + connect \Y $eq$libresoc.v:35092$1410_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35046$1412 + cell $eq $eq$libresoc.v:35094$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54357,10 +54393,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_15 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35046$1412_Y + connect \Y $eq$libresoc.v:35094$1412_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35047$1413 + cell $eq $eq$libresoc.v:35095$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54368,10 +54404,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_14 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35047$1413_Y + connect \Y $eq$libresoc.v:35095$1413_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35049$1415 + cell $eq $eq$libresoc.v:35097$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54379,10 +54415,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_17 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35049$1415_Y + connect \Y $eq$libresoc.v:35097$1415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35050$1416 + cell $eq $eq$libresoc.v:35098$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54390,10 +54426,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_16 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35050$1416_Y + connect \Y $eq$libresoc.v:35098$1416_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35052$1418 + cell $eq $eq$libresoc.v:35100$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54401,10 +54437,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_19 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35052$1418_Y + connect \Y $eq$libresoc.v:35100$1418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35053$1419 + cell $eq $eq$libresoc.v:35101$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54412,10 +54448,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_18 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35053$1419_Y + connect \Y $eq$libresoc.v:35101$1419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35056$1422 + cell $eq $eq$libresoc.v:35104$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54423,10 +54459,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_21 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35056$1422_Y + connect \Y $eq$libresoc.v:35104$1422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35057$1423 + cell $eq $eq$libresoc.v:35105$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54434,10 +54470,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_20 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35057$1423_Y + connect \Y $eq$libresoc.v:35105$1423_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35059$1425 + cell $eq $eq$libresoc.v:35107$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54445,10 +54481,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_23 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35059$1425_Y + connect \Y $eq$libresoc.v:35107$1425_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35060$1426 + cell $eq $eq$libresoc.v:35108$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54456,10 +54492,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_22 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35060$1426_Y + connect \Y $eq$libresoc.v:35108$1426_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35062$1428 + cell $eq $eq$libresoc.v:35110$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54467,10 +54503,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_25 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35062$1428_Y + connect \Y $eq$libresoc.v:35110$1428_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35063$1429 + cell $eq $eq$libresoc.v:35111$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54478,10 +54514,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_24 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35063$1429_Y + connect \Y $eq$libresoc.v:35111$1429_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35065$1431 + cell $eq $eq$libresoc.v:35113$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54489,10 +54525,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_3 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35065$1431_Y + connect \Y $eq$libresoc.v:35113$1431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35066$1432 + cell $eq $eq$libresoc.v:35114$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54500,10 +54536,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_27 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35066$1432_Y + connect \Y $eq$libresoc.v:35114$1432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35067$1433 + cell $eq $eq$libresoc.v:35115$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54511,10 +54547,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_26 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35067$1433_Y + connect \Y $eq$libresoc.v:35115$1433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35069$1435 + cell $eq $eq$libresoc.v:35117$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54522,10 +54558,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_29 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35069$1435_Y + connect \Y $eq$libresoc.v:35117$1435_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35070$1436 + cell $eq $eq$libresoc.v:35118$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54533,10 +54569,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_28 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35070$1436_Y + connect \Y $eq$libresoc.v:35118$1436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35072$1438 + cell $eq $eq$libresoc.v:35120$1438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54544,10 +54580,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_31 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35072$1438_Y + connect \Y $eq$libresoc.v:35120$1438_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35073$1439 + cell $eq $eq$libresoc.v:35121$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54555,10 +54591,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_30 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35073$1439_Y + connect \Y $eq$libresoc.v:35121$1439_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35075$1441 + cell $eq $eq$libresoc.v:35123$1441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54566,271 +54602,271 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_2 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:35075$1441_Y + connect \Y $eq$libresoc.v:35123$1441_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34985$1351 + cell $pos $pos$libresoc.v:35033$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_0 [1:0] } - connect \Y $pos$libresoc.v:34985$1351_Y + connect \Y $pos$libresoc.v:35033$1351_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34988$1354 + cell $pos $pos$libresoc.v:35036$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_4 [1:0] } - connect \Y $pos$libresoc.v:34988$1354_Y + connect \Y $pos$libresoc.v:35036$1354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34991$1357 + cell $pos $pos$libresoc.v:35039$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_8 [1:0] } - connect \Y $pos$libresoc.v:34991$1357_Y + connect \Y $pos$libresoc.v:35039$1357_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34994$1360 + cell $pos $pos$libresoc.v:35042$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_2 [0] } - connect \Y $pos$libresoc.v:34994$1360_Y + connect \Y $pos$libresoc.v:35042$1360_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34995$1361 + cell $pos $pos$libresoc.v:35043$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_12 [1:0] } - connect \Y $pos$libresoc.v:34995$1361_Y + connect \Y $pos$libresoc.v:35043$1361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34998$1364 + cell $pos $pos$libresoc.v:35046$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_16 [1:0] } - connect \Y $pos$libresoc.v:34998$1364_Y + connect \Y $pos$libresoc.v:35046$1364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35001$1367 + cell $pos $pos$libresoc.v:35049$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_20 [1:0] } - connect \Y $pos$libresoc.v:35001$1367_Y + connect \Y $pos$libresoc.v:35049$1367_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35004$1370 + cell $pos $pos$libresoc.v:35052$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_24 [1:0] } - connect \Y $pos$libresoc.v:35004$1370_Y + connect \Y $pos$libresoc.v:35052$1370_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35008$1374 + cell $pos $pos$libresoc.v:35056$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_28 [1:0] } - connect \Y $pos$libresoc.v:35008$1374_Y + connect \Y $pos$libresoc.v:35056$1374_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35011$1377 + cell $pos $pos$libresoc.v:35059$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_0 [2:0] } - connect \Y $pos$libresoc.v:35011$1377_Y + connect \Y $pos$libresoc.v:35059$1377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35014$1380 + cell $pos $pos$libresoc.v:35062$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_4 [2:0] } - connect \Y $pos$libresoc.v:35014$1380_Y + connect \Y $pos$libresoc.v:35062$1380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35018$1384 + cell $pos $pos$libresoc.v:35066$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_8 [2:0] } - connect \Y $pos$libresoc.v:35018$1384_Y + connect \Y $pos$libresoc.v:35066$1384_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35021$1387 + cell $pos $pos$libresoc.v:35069$1387 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_12 [2:0] } - connect \Y $pos$libresoc.v:35021$1387_Y + connect \Y $pos$libresoc.v:35069$1387_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35024$1390 + cell $pos $pos$libresoc.v:35072$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'01 \cnt_4_0 [3:0] } - connect \Y $pos$libresoc.v:35024$1390_Y + connect \Y $pos$libresoc.v:35072$1390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35027$1393 + cell $pos $pos$libresoc.v:35075$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_4 [0] } - connect \Y $pos$libresoc.v:35027$1393_Y + connect \Y $pos$libresoc.v:35075$1393_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35028$1394 + cell $pos $pos$libresoc.v:35076$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'01 \cnt_4_4 [3:0] } - connect \Y $pos$libresoc.v:35028$1394_Y + connect \Y $pos$libresoc.v:35076$1394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35031$1397 + cell $pos $pos$libresoc.v:35079$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { 2'01 \cnt_5_0 [4:0] } - connect \Y $pos$libresoc.v:35031$1397_Y + connect \Y $pos$libresoc.v:35079$1397_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35035$1401 + cell $pos $pos$libresoc.v:35083$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_6 [0] } - connect \Y $pos$libresoc.v:35035$1401_Y + connect \Y $pos$libresoc.v:35083$1401_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35038$1404 + cell $pos $pos$libresoc.v:35086$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_8 [0] } - connect \Y $pos$libresoc.v:35038$1404_Y + connect \Y $pos$libresoc.v:35086$1404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35041$1407 + cell $pos $pos$libresoc.v:35089$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_10 [0] } - connect \Y $pos$libresoc.v:35041$1407_Y + connect \Y $pos$libresoc.v:35089$1407_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35045$1411 + cell $pos $pos$libresoc.v:35093$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_12 [0] } - connect \Y $pos$libresoc.v:35045$1411_Y + connect \Y $pos$libresoc.v:35093$1411_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35048$1414 + cell $pos $pos$libresoc.v:35096$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_14 [0] } - connect \Y $pos$libresoc.v:35048$1414_Y + connect \Y $pos$libresoc.v:35096$1414_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35051$1417 + cell $pos $pos$libresoc.v:35099$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_16 [0] } - connect \Y $pos$libresoc.v:35051$1417_Y + connect \Y $pos$libresoc.v:35099$1417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35054$1420 + cell $pos $pos$libresoc.v:35102$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_0 [0] } - connect \Y $pos$libresoc.v:35054$1420_Y + connect \Y $pos$libresoc.v:35102$1420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35055$1421 + cell $pos $pos$libresoc.v:35103$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_18 [0] } - connect \Y $pos$libresoc.v:35055$1421_Y + connect \Y $pos$libresoc.v:35103$1421_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35058$1424 + cell $pos $pos$libresoc.v:35106$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_20 [0] } - connect \Y $pos$libresoc.v:35058$1424_Y + connect \Y $pos$libresoc.v:35106$1424_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35061$1427 + cell $pos $pos$libresoc.v:35109$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_22 [0] } - connect \Y $pos$libresoc.v:35061$1427_Y + connect \Y $pos$libresoc.v:35109$1427_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35064$1430 + cell $pos $pos$libresoc.v:35112$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_24 [0] } - connect \Y $pos$libresoc.v:35064$1430_Y + connect \Y $pos$libresoc.v:35112$1430_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35068$1434 + cell $pos $pos$libresoc.v:35116$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_26 [0] } - connect \Y $pos$libresoc.v:35068$1434_Y + connect \Y $pos$libresoc.v:35116$1434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35071$1437 + cell $pos $pos$libresoc.v:35119$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_28 [0] } - connect \Y $pos$libresoc.v:35071$1437_Y + connect \Y $pos$libresoc.v:35119$1437_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35074$1440 + cell $pos $pos$libresoc.v:35122$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_30 [0] } - connect \Y $pos$libresoc.v:35074$1440_Y + connect \Y $pos$libresoc.v:35122$1440_Y end - attribute \src "libresoc.v:34602.7-34602.20" - process $proc$libresoc.v:34602$1505 + attribute \src "libresoc.v:34650.7-34650.20" + process $proc$libresoc.v:34650$1505 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:35076.3-35090.6" - process $proc$libresoc.v:35076$1442 + attribute \src "libresoc.v:35124.3-35138.6" + process $proc$libresoc.v:35124$1442 assign { } { } assign $0\cnt_1_0[1:0] $1\cnt_1_0[1:0] - attribute \src "libresoc.v:35077.5-35077.29" + attribute \src "libresoc.v:35125.5-35125.29" switch \initial - attribute \src "libresoc.v:35077.9-35077.17" + attribute \src "libresoc.v:35125.9-35125.17" case 1'1 case end @@ -54852,13 +54888,13 @@ module \clz sync always update \cnt_1_0 $0\cnt_1_0[1:0] end - attribute \src "libresoc.v:35091.3-35105.6" - process $proc$libresoc.v:35091$1443 + attribute \src "libresoc.v:35139.3-35153.6" + process $proc$libresoc.v:35139$1443 assign { } { } assign $0\cnt_1_5[1:0] $1\cnt_1_5[1:0] - attribute \src "libresoc.v:35092.5-35092.29" + attribute \src "libresoc.v:35140.5-35140.29" switch \initial - attribute \src "libresoc.v:35092.9-35092.17" + attribute \src "libresoc.v:35140.9-35140.17" case 1'1 case end @@ -54880,13 +54916,13 @@ module \clz sync always update \cnt_1_5 $0\cnt_1_5[1:0] end - attribute \src "libresoc.v:35106.3-35120.6" - process $proc$libresoc.v:35106$1444 + attribute \src "libresoc.v:35154.3-35168.6" + process $proc$libresoc.v:35154$1444 assign { } { } assign $0\cnt_1_6[1:0] $1\cnt_1_6[1:0] - attribute \src "libresoc.v:35107.5-35107.29" + attribute \src "libresoc.v:35155.5-35155.29" switch \initial - attribute \src "libresoc.v:35107.9-35107.17" + attribute \src "libresoc.v:35155.9-35155.17" case 1'1 case end @@ -54908,13 +54944,13 @@ module \clz sync always update \cnt_1_6 $0\cnt_1_6[1:0] end - attribute \src "libresoc.v:35121.3-35135.6" - process $proc$libresoc.v:35121$1445 + attribute \src "libresoc.v:35169.3-35183.6" + process $proc$libresoc.v:35169$1445 assign { } { } assign $0\cnt_1_7[1:0] $1\cnt_1_7[1:0] - attribute \src "libresoc.v:35122.5-35122.29" + attribute \src "libresoc.v:35170.5-35170.29" switch \initial - attribute \src "libresoc.v:35122.9-35122.17" + attribute \src "libresoc.v:35170.9-35170.17" case 1'1 case end @@ -54936,13 +54972,13 @@ module \clz sync always update \cnt_1_7 $0\cnt_1_7[1:0] end - attribute \src "libresoc.v:35136.3-35150.6" - process $proc$libresoc.v:35136$1446 + attribute \src "libresoc.v:35184.3-35198.6" + process $proc$libresoc.v:35184$1446 assign { } { } assign $0\cnt_1_8[1:0] $1\cnt_1_8[1:0] - attribute \src "libresoc.v:35137.5-35137.29" + attribute \src "libresoc.v:35185.5-35185.29" switch \initial - attribute \src "libresoc.v:35137.9-35137.17" + attribute \src "libresoc.v:35185.9-35185.17" case 1'1 case end @@ -54964,13 +55000,13 @@ module \clz sync always update \cnt_1_8 $0\cnt_1_8[1:0] end - attribute \src "libresoc.v:35151.3-35165.6" - process $proc$libresoc.v:35151$1447 + attribute \src "libresoc.v:35199.3-35213.6" + process $proc$libresoc.v:35199$1447 assign { } { } assign $0\cnt_1_9[1:0] $1\cnt_1_9[1:0] - attribute \src "libresoc.v:35152.5-35152.29" + attribute \src "libresoc.v:35200.5-35200.29" switch \initial - attribute \src "libresoc.v:35152.9-35152.17" + attribute \src "libresoc.v:35200.9-35200.17" case 1'1 case end @@ -54992,13 +55028,13 @@ module \clz sync always update \cnt_1_9 $0\cnt_1_9[1:0] end - attribute \src "libresoc.v:35166.3-35180.6" - process $proc$libresoc.v:35166$1448 + attribute \src "libresoc.v:35214.3-35228.6" + process $proc$libresoc.v:35214$1448 assign { } { } assign $0\cnt_1_10[1:0] $1\cnt_1_10[1:0] - attribute \src "libresoc.v:35167.5-35167.29" + attribute \src "libresoc.v:35215.5-35215.29" switch \initial - attribute \src "libresoc.v:35167.9-35167.17" + attribute \src "libresoc.v:35215.9-35215.17" case 1'1 case end @@ -55020,13 +55056,13 @@ module \clz sync always update \cnt_1_10 $0\cnt_1_10[1:0] end - attribute \src "libresoc.v:35181.3-35195.6" - process $proc$libresoc.v:35181$1449 + attribute \src "libresoc.v:35229.3-35243.6" + process $proc$libresoc.v:35229$1449 assign { } { } assign $0\cnt_1_11[1:0] $1\cnt_1_11[1:0] - attribute \src "libresoc.v:35182.5-35182.29" + attribute \src "libresoc.v:35230.5-35230.29" switch \initial - attribute \src "libresoc.v:35182.9-35182.17" + attribute \src "libresoc.v:35230.9-35230.17" case 1'1 case end @@ -55048,13 +55084,13 @@ module \clz sync always update \cnt_1_11 $0\cnt_1_11[1:0] end - attribute \src "libresoc.v:35196.3-35210.6" - process $proc$libresoc.v:35196$1450 + attribute \src "libresoc.v:35244.3-35258.6" + process $proc$libresoc.v:35244$1450 assign { } { } assign $0\cnt_1_12[1:0] $1\cnt_1_12[1:0] - attribute \src "libresoc.v:35197.5-35197.29" + attribute \src "libresoc.v:35245.5-35245.29" switch \initial - attribute \src "libresoc.v:35197.9-35197.17" + attribute \src "libresoc.v:35245.9-35245.17" case 1'1 case end @@ -55076,13 +55112,13 @@ module \clz sync always update \cnt_1_12 $0\cnt_1_12[1:0] end - attribute \src "libresoc.v:35211.3-35225.6" - process $proc$libresoc.v:35211$1451 + attribute \src "libresoc.v:35259.3-35273.6" + process $proc$libresoc.v:35259$1451 assign { } { } assign $0\cnt_1_13[1:0] $1\cnt_1_13[1:0] - attribute \src "libresoc.v:35212.5-35212.29" + attribute \src "libresoc.v:35260.5-35260.29" switch \initial - attribute \src "libresoc.v:35212.9-35212.17" + attribute \src "libresoc.v:35260.9-35260.17" case 1'1 case end @@ -55104,13 +55140,13 @@ module \clz sync always update \cnt_1_13 $0\cnt_1_13[1:0] end - attribute \src "libresoc.v:35226.3-35240.6" - process $proc$libresoc.v:35226$1452 + attribute \src "libresoc.v:35274.3-35288.6" + process $proc$libresoc.v:35274$1452 assign { } { } assign $0\cnt_1_14[1:0] $1\cnt_1_14[1:0] - attribute \src "libresoc.v:35227.5-35227.29" + attribute \src "libresoc.v:35275.5-35275.29" switch \initial - attribute \src "libresoc.v:35227.9-35227.17" + attribute \src "libresoc.v:35275.9-35275.17" case 1'1 case end @@ -55132,13 +55168,13 @@ module \clz sync always update \cnt_1_14 $0\cnt_1_14[1:0] end - attribute \src "libresoc.v:35241.3-35255.6" - process $proc$libresoc.v:35241$1453 + attribute \src "libresoc.v:35289.3-35303.6" + process $proc$libresoc.v:35289$1453 assign { } { } assign $0\cnt_1_1[1:0] $1\cnt_1_1[1:0] - attribute \src "libresoc.v:35242.5-35242.29" + attribute \src "libresoc.v:35290.5-35290.29" switch \initial - attribute \src "libresoc.v:35242.9-35242.17" + attribute \src "libresoc.v:35290.9-35290.17" case 1'1 case end @@ -55160,13 +55196,13 @@ module \clz sync always update \cnt_1_1 $0\cnt_1_1[1:0] end - attribute \src "libresoc.v:35256.3-35270.6" - process $proc$libresoc.v:35256$1454 + attribute \src "libresoc.v:35304.3-35318.6" + process $proc$libresoc.v:35304$1454 assign { } { } assign $0\cnt_1_15[1:0] $1\cnt_1_15[1:0] - attribute \src "libresoc.v:35257.5-35257.29" + attribute \src "libresoc.v:35305.5-35305.29" switch \initial - attribute \src "libresoc.v:35257.9-35257.17" + attribute \src "libresoc.v:35305.9-35305.17" case 1'1 case end @@ -55188,13 +55224,13 @@ module \clz sync always update \cnt_1_15 $0\cnt_1_15[1:0] end - attribute \src "libresoc.v:35271.3-35285.6" - process $proc$libresoc.v:35271$1455 + attribute \src "libresoc.v:35319.3-35333.6" + process $proc$libresoc.v:35319$1455 assign { } { } assign $0\cnt_1_16[1:0] $1\cnt_1_16[1:0] - attribute \src "libresoc.v:35272.5-35272.29" + attribute \src "libresoc.v:35320.5-35320.29" switch \initial - attribute \src "libresoc.v:35272.9-35272.17" + attribute \src "libresoc.v:35320.9-35320.17" case 1'1 case end @@ -55216,13 +55252,13 @@ module \clz sync always update \cnt_1_16 $0\cnt_1_16[1:0] end - attribute \src "libresoc.v:35286.3-35300.6" - process $proc$libresoc.v:35286$1456 + attribute \src "libresoc.v:35334.3-35348.6" + process $proc$libresoc.v:35334$1456 assign { } { } assign $0\cnt_1_17[1:0] $1\cnt_1_17[1:0] - attribute \src "libresoc.v:35287.5-35287.29" + attribute \src "libresoc.v:35335.5-35335.29" switch \initial - attribute \src "libresoc.v:35287.9-35287.17" + attribute \src "libresoc.v:35335.9-35335.17" case 1'1 case end @@ -55244,13 +55280,13 @@ module \clz sync always update \cnt_1_17 $0\cnt_1_17[1:0] end - attribute \src "libresoc.v:35301.3-35315.6" - process $proc$libresoc.v:35301$1457 + attribute \src "libresoc.v:35349.3-35363.6" + process $proc$libresoc.v:35349$1457 assign { } { } assign $0\cnt_1_18[1:0] $1\cnt_1_18[1:0] - attribute \src "libresoc.v:35302.5-35302.29" + attribute \src "libresoc.v:35350.5-35350.29" switch \initial - attribute \src "libresoc.v:35302.9-35302.17" + attribute \src "libresoc.v:35350.9-35350.17" case 1'1 case end @@ -55272,13 +55308,13 @@ module \clz sync always update \cnt_1_18 $0\cnt_1_18[1:0] end - attribute \src "libresoc.v:35316.3-35330.6" - process $proc$libresoc.v:35316$1458 + attribute \src "libresoc.v:35364.3-35378.6" + process $proc$libresoc.v:35364$1458 assign { } { } assign $0\cnt_1_19[1:0] $1\cnt_1_19[1:0] - attribute \src "libresoc.v:35317.5-35317.29" + attribute \src "libresoc.v:35365.5-35365.29" switch \initial - attribute \src "libresoc.v:35317.9-35317.17" + attribute \src "libresoc.v:35365.9-35365.17" case 1'1 case end @@ -55300,13 +55336,13 @@ module \clz sync always update \cnt_1_19 $0\cnt_1_19[1:0] end - attribute \src "libresoc.v:35331.3-35345.6" - process $proc$libresoc.v:35331$1459 + attribute \src "libresoc.v:35379.3-35393.6" + process $proc$libresoc.v:35379$1459 assign { } { } assign $0\cnt_1_20[1:0] $1\cnt_1_20[1:0] - attribute \src "libresoc.v:35332.5-35332.29" + attribute \src "libresoc.v:35380.5-35380.29" switch \initial - attribute \src "libresoc.v:35332.9-35332.17" + attribute \src "libresoc.v:35380.9-35380.17" case 1'1 case end @@ -55328,13 +55364,13 @@ module \clz sync always update \cnt_1_20 $0\cnt_1_20[1:0] end - attribute \src "libresoc.v:35346.3-35360.6" - process $proc$libresoc.v:35346$1460 + attribute \src "libresoc.v:35394.3-35408.6" + process $proc$libresoc.v:35394$1460 assign { } { } assign $0\cnt_1_21[1:0] $1\cnt_1_21[1:0] - attribute \src "libresoc.v:35347.5-35347.29" + attribute \src "libresoc.v:35395.5-35395.29" switch \initial - attribute \src "libresoc.v:35347.9-35347.17" + attribute \src "libresoc.v:35395.9-35395.17" case 1'1 case end @@ -55356,13 +55392,13 @@ module \clz sync always update \cnt_1_21 $0\cnt_1_21[1:0] end - attribute \src "libresoc.v:35361.3-35375.6" - process $proc$libresoc.v:35361$1461 + attribute \src "libresoc.v:35409.3-35423.6" + process $proc$libresoc.v:35409$1461 assign { } { } assign $0\cnt_1_22[1:0] $1\cnt_1_22[1:0] - attribute \src "libresoc.v:35362.5-35362.29" + attribute \src "libresoc.v:35410.5-35410.29" switch \initial - attribute \src "libresoc.v:35362.9-35362.17" + attribute \src "libresoc.v:35410.9-35410.17" case 1'1 case end @@ -55384,13 +55420,13 @@ module \clz sync always update \cnt_1_22 $0\cnt_1_22[1:0] end - attribute \src "libresoc.v:35376.3-35390.6" - process $proc$libresoc.v:35376$1462 + attribute \src "libresoc.v:35424.3-35438.6" + process $proc$libresoc.v:35424$1462 assign { } { } assign $0\cnt_1_23[1:0] $1\cnt_1_23[1:0] - attribute \src "libresoc.v:35377.5-35377.29" + attribute \src "libresoc.v:35425.5-35425.29" switch \initial - attribute \src "libresoc.v:35377.9-35377.17" + attribute \src "libresoc.v:35425.9-35425.17" case 1'1 case end @@ -55412,13 +55448,13 @@ module \clz sync always update \cnt_1_23 $0\cnt_1_23[1:0] end - attribute \src "libresoc.v:35391.3-35405.6" - process $proc$libresoc.v:35391$1463 + attribute \src "libresoc.v:35439.3-35453.6" + process $proc$libresoc.v:35439$1463 assign { } { } assign $0\cnt_1_24[1:0] $1\cnt_1_24[1:0] - attribute \src "libresoc.v:35392.5-35392.29" + attribute \src "libresoc.v:35440.5-35440.29" switch \initial - attribute \src "libresoc.v:35392.9-35392.17" + attribute \src "libresoc.v:35440.9-35440.17" case 1'1 case end @@ -55440,13 +55476,13 @@ module \clz sync always update \cnt_1_24 $0\cnt_1_24[1:0] end - attribute \src "libresoc.v:35406.3-35420.6" - process $proc$libresoc.v:35406$1464 + attribute \src "libresoc.v:35454.3-35468.6" + process $proc$libresoc.v:35454$1464 assign { } { } assign $0\cnt_1_2[1:0] $1\cnt_1_2[1:0] - attribute \src "libresoc.v:35407.5-35407.29" + attribute \src "libresoc.v:35455.5-35455.29" switch \initial - attribute \src "libresoc.v:35407.9-35407.17" + attribute \src "libresoc.v:35455.9-35455.17" case 1'1 case end @@ -55468,13 +55504,13 @@ module \clz sync always update \cnt_1_2 $0\cnt_1_2[1:0] end - attribute \src "libresoc.v:35421.3-35435.6" - process $proc$libresoc.v:35421$1465 + attribute \src "libresoc.v:35469.3-35483.6" + process $proc$libresoc.v:35469$1465 assign { } { } assign $0\cnt_1_25[1:0] $1\cnt_1_25[1:0] - attribute \src "libresoc.v:35422.5-35422.29" + attribute \src "libresoc.v:35470.5-35470.29" switch \initial - attribute \src "libresoc.v:35422.9-35422.17" + attribute \src "libresoc.v:35470.9-35470.17" case 1'1 case end @@ -55496,13 +55532,13 @@ module \clz sync always update \cnt_1_25 $0\cnt_1_25[1:0] end - attribute \src "libresoc.v:35436.3-35450.6" - process $proc$libresoc.v:35436$1466 + attribute \src "libresoc.v:35484.3-35498.6" + process $proc$libresoc.v:35484$1466 assign { } { } assign $0\cnt_1_26[1:0] $1\cnt_1_26[1:0] - attribute \src "libresoc.v:35437.5-35437.29" + attribute \src "libresoc.v:35485.5-35485.29" switch \initial - attribute \src "libresoc.v:35437.9-35437.17" + attribute \src "libresoc.v:35485.9-35485.17" case 1'1 case end @@ -55524,13 +55560,13 @@ module \clz sync always update \cnt_1_26 $0\cnt_1_26[1:0] end - attribute \src "libresoc.v:35451.3-35465.6" - process $proc$libresoc.v:35451$1467 + attribute \src "libresoc.v:35499.3-35513.6" + process $proc$libresoc.v:35499$1467 assign { } { } assign $0\cnt_1_27[1:0] $1\cnt_1_27[1:0] - attribute \src "libresoc.v:35452.5-35452.29" + attribute \src "libresoc.v:35500.5-35500.29" switch \initial - attribute \src "libresoc.v:35452.9-35452.17" + attribute \src "libresoc.v:35500.9-35500.17" case 1'1 case end @@ -55552,13 +55588,13 @@ module \clz sync always update \cnt_1_27 $0\cnt_1_27[1:0] end - attribute \src "libresoc.v:35466.3-35480.6" - process $proc$libresoc.v:35466$1468 + attribute \src "libresoc.v:35514.3-35528.6" + process $proc$libresoc.v:35514$1468 assign { } { } assign $0\cnt_1_28[1:0] $1\cnt_1_28[1:0] - attribute \src "libresoc.v:35467.5-35467.29" + attribute \src "libresoc.v:35515.5-35515.29" switch \initial - attribute \src "libresoc.v:35467.9-35467.17" + attribute \src "libresoc.v:35515.9-35515.17" case 1'1 case end @@ -55580,13 +55616,13 @@ module \clz sync always update \cnt_1_28 $0\cnt_1_28[1:0] end - attribute \src "libresoc.v:35481.3-35495.6" - process $proc$libresoc.v:35481$1469 + attribute \src "libresoc.v:35529.3-35543.6" + process $proc$libresoc.v:35529$1469 assign { } { } assign $0\cnt_1_29[1:0] $1\cnt_1_29[1:0] - attribute \src "libresoc.v:35482.5-35482.29" + attribute \src "libresoc.v:35530.5-35530.29" switch \initial - attribute \src "libresoc.v:35482.9-35482.17" + attribute \src "libresoc.v:35530.9-35530.17" case 1'1 case end @@ -55608,13 +55644,13 @@ module \clz sync always update \cnt_1_29 $0\cnt_1_29[1:0] end - attribute \src "libresoc.v:35496.3-35510.6" - process $proc$libresoc.v:35496$1470 + attribute \src "libresoc.v:35544.3-35558.6" + process $proc$libresoc.v:35544$1470 assign { } { } assign $0\cnt_1_30[1:0] $1\cnt_1_30[1:0] - attribute \src "libresoc.v:35497.5-35497.29" + attribute \src "libresoc.v:35545.5-35545.29" switch \initial - attribute \src "libresoc.v:35497.9-35497.17" + attribute \src "libresoc.v:35545.9-35545.17" case 1'1 case end @@ -55636,13 +55672,13 @@ module \clz sync always update \cnt_1_30 $0\cnt_1_30[1:0] end - attribute \src "libresoc.v:35511.3-35525.6" - process $proc$libresoc.v:35511$1471 + attribute \src "libresoc.v:35559.3-35573.6" + process $proc$libresoc.v:35559$1471 assign { } { } assign $0\cnt_1_31[1:0] $1\cnt_1_31[1:0] - attribute \src "libresoc.v:35512.5-35512.29" + attribute \src "libresoc.v:35560.5-35560.29" switch \initial - attribute \src "libresoc.v:35512.9-35512.17" + attribute \src "libresoc.v:35560.9-35560.17" case 1'1 case end @@ -55664,13 +55700,13 @@ module \clz sync always update \cnt_1_31 $0\cnt_1_31[1:0] end - attribute \src "libresoc.v:35526.3-35545.6" - process $proc$libresoc.v:35526$1472 + attribute \src "libresoc.v:35574.3-35593.6" + process $proc$libresoc.v:35574$1472 assign { } { } assign $0\cnt_2_0[2:0] $1\cnt_2_0[2:0] - attribute \src "libresoc.v:35527.5-35527.29" + attribute \src "libresoc.v:35575.5-35575.29" switch \initial - attribute \src "libresoc.v:35527.9-35527.17" + attribute \src "libresoc.v:35575.9-35575.17" case 1'1 case end @@ -55699,13 +55735,13 @@ module \clz sync always update \cnt_2_0 $0\cnt_2_0[2:0] end - attribute \src "libresoc.v:35546.3-35565.6" - process $proc$libresoc.v:35546$1473 + attribute \src "libresoc.v:35594.3-35613.6" + process $proc$libresoc.v:35594$1473 assign { } { } assign $0\cnt_2_2[2:0] $1\cnt_2_2[2:0] - attribute \src "libresoc.v:35547.5-35547.29" + attribute \src "libresoc.v:35595.5-35595.29" switch \initial - attribute \src "libresoc.v:35547.9-35547.17" + attribute \src "libresoc.v:35595.9-35595.17" case 1'1 case end @@ -55734,13 +55770,13 @@ module \clz sync always update \cnt_2_2 $0\cnt_2_2[2:0] end - attribute \src "libresoc.v:35566.3-35585.6" - process $proc$libresoc.v:35566$1474 + attribute \src "libresoc.v:35614.3-35633.6" + process $proc$libresoc.v:35614$1474 assign { } { } assign $0\cnt_2_4[2:0] $1\cnt_2_4[2:0] - attribute \src "libresoc.v:35567.5-35567.29" + attribute \src "libresoc.v:35615.5-35615.29" switch \initial - attribute \src "libresoc.v:35567.9-35567.17" + attribute \src "libresoc.v:35615.9-35615.17" case 1'1 case end @@ -55769,13 +55805,13 @@ module \clz sync always update \cnt_2_4 $0\cnt_2_4[2:0] end - attribute \src "libresoc.v:35586.3-35605.6" - process $proc$libresoc.v:35586$1475 + attribute \src "libresoc.v:35634.3-35653.6" + process $proc$libresoc.v:35634$1475 assign { } { } assign $0\cnt_2_6[2:0] $1\cnt_2_6[2:0] - attribute \src "libresoc.v:35587.5-35587.29" + attribute \src "libresoc.v:35635.5-35635.29" switch \initial - attribute \src "libresoc.v:35587.9-35587.17" + attribute \src "libresoc.v:35635.9-35635.17" case 1'1 case end @@ -55804,13 +55840,13 @@ module \clz sync always update \cnt_2_6 $0\cnt_2_6[2:0] end - attribute \src "libresoc.v:35606.3-35625.6" - process $proc$libresoc.v:35606$1476 + attribute \src "libresoc.v:35654.3-35673.6" + process $proc$libresoc.v:35654$1476 assign { } { } assign $0\cnt_2_8[2:0] $1\cnt_2_8[2:0] - attribute \src "libresoc.v:35607.5-35607.29" + attribute \src "libresoc.v:35655.5-35655.29" switch \initial - attribute \src "libresoc.v:35607.9-35607.17" + attribute \src "libresoc.v:35655.9-35655.17" case 1'1 case end @@ -55839,13 +55875,13 @@ module \clz sync always update \cnt_2_8 $0\cnt_2_8[2:0] end - attribute \src "libresoc.v:35626.3-35645.6" - process $proc$libresoc.v:35626$1477 + attribute \src "libresoc.v:35674.3-35693.6" + process $proc$libresoc.v:35674$1477 assign { } { } assign $0\cnt_2_10[2:0] $1\cnt_2_10[2:0] - attribute \src "libresoc.v:35627.5-35627.29" + attribute \src "libresoc.v:35675.5-35675.29" switch \initial - attribute \src "libresoc.v:35627.9-35627.17" + attribute \src "libresoc.v:35675.9-35675.17" case 1'1 case end @@ -55874,13 +55910,13 @@ module \clz sync always update \cnt_2_10 $0\cnt_2_10[2:0] end - attribute \src "libresoc.v:35646.3-35660.6" - process $proc$libresoc.v:35646$1478 + attribute \src "libresoc.v:35694.3-35708.6" + process $proc$libresoc.v:35694$1478 assign { } { } assign $0\cnt_1_3[1:0] $1\cnt_1_3[1:0] - attribute \src "libresoc.v:35647.5-35647.29" + attribute \src "libresoc.v:35695.5-35695.29" switch \initial - attribute \src "libresoc.v:35647.9-35647.17" + attribute \src "libresoc.v:35695.9-35695.17" case 1'1 case end @@ -55902,13 +55938,13 @@ module \clz sync always update \cnt_1_3 $0\cnt_1_3[1:0] end - attribute \src "libresoc.v:35661.3-35680.6" - process $proc$libresoc.v:35661$1479 + attribute \src "libresoc.v:35709.3-35728.6" + process $proc$libresoc.v:35709$1479 assign { } { } assign $0\cnt_2_12[2:0] $1\cnt_2_12[2:0] - attribute \src "libresoc.v:35662.5-35662.29" + attribute \src "libresoc.v:35710.5-35710.29" switch \initial - attribute \src "libresoc.v:35662.9-35662.17" + attribute \src "libresoc.v:35710.9-35710.17" case 1'1 case end @@ -55937,13 +55973,13 @@ module \clz sync always update \cnt_2_12 $0\cnt_2_12[2:0] end - attribute \src "libresoc.v:35681.3-35700.6" - process $proc$libresoc.v:35681$1480 + attribute \src "libresoc.v:35729.3-35748.6" + process $proc$libresoc.v:35729$1480 assign { } { } assign $0\cnt_2_14[2:0] $1\cnt_2_14[2:0] - attribute \src "libresoc.v:35682.5-35682.29" + attribute \src "libresoc.v:35730.5-35730.29" switch \initial - attribute \src "libresoc.v:35682.9-35682.17" + attribute \src "libresoc.v:35730.9-35730.17" case 1'1 case end @@ -55972,13 +56008,13 @@ module \clz sync always update \cnt_2_14 $0\cnt_2_14[2:0] end - attribute \src "libresoc.v:35701.3-35720.6" - process $proc$libresoc.v:35701$1481 + attribute \src "libresoc.v:35749.3-35768.6" + process $proc$libresoc.v:35749$1481 assign { } { } assign $0\cnt_2_16[2:0] $1\cnt_2_16[2:0] - attribute \src "libresoc.v:35702.5-35702.29" + attribute \src "libresoc.v:35750.5-35750.29" switch \initial - attribute \src "libresoc.v:35702.9-35702.17" + attribute \src "libresoc.v:35750.9-35750.17" case 1'1 case end @@ -56007,13 +56043,13 @@ module \clz sync always update \cnt_2_16 $0\cnt_2_16[2:0] end - attribute \src "libresoc.v:35721.3-35740.6" - process $proc$libresoc.v:35721$1482 + attribute \src "libresoc.v:35769.3-35788.6" + process $proc$libresoc.v:35769$1482 assign { } { } assign $0\cnt_2_18[2:0] $1\cnt_2_18[2:0] - attribute \src "libresoc.v:35722.5-35722.29" + attribute \src "libresoc.v:35770.5-35770.29" switch \initial - attribute \src "libresoc.v:35722.9-35722.17" + attribute \src "libresoc.v:35770.9-35770.17" case 1'1 case end @@ -56042,13 +56078,13 @@ module \clz sync always update \cnt_2_18 $0\cnt_2_18[2:0] end - attribute \src "libresoc.v:35741.3-35760.6" - process $proc$libresoc.v:35741$1483 + attribute \src "libresoc.v:35789.3-35808.6" + process $proc$libresoc.v:35789$1483 assign { } { } assign $0\cnt_2_20[2:0] $1\cnt_2_20[2:0] - attribute \src "libresoc.v:35742.5-35742.29" + attribute \src "libresoc.v:35790.5-35790.29" switch \initial - attribute \src "libresoc.v:35742.9-35742.17" + attribute \src "libresoc.v:35790.9-35790.17" case 1'1 case end @@ -56077,13 +56113,13 @@ module \clz sync always update \cnt_2_20 $0\cnt_2_20[2:0] end - attribute \src "libresoc.v:35761.3-35780.6" - process $proc$libresoc.v:35761$1484 + attribute \src "libresoc.v:35809.3-35828.6" + process $proc$libresoc.v:35809$1484 assign { } { } assign $0\cnt_2_22[2:0] $1\cnt_2_22[2:0] - attribute \src "libresoc.v:35762.5-35762.29" + attribute \src "libresoc.v:35810.5-35810.29" switch \initial - attribute \src "libresoc.v:35762.9-35762.17" + attribute \src "libresoc.v:35810.9-35810.17" case 1'1 case end @@ -56112,13 +56148,13 @@ module \clz sync always update \cnt_2_22 $0\cnt_2_22[2:0] end - attribute \src "libresoc.v:35781.3-35800.6" - process $proc$libresoc.v:35781$1485 + attribute \src "libresoc.v:35829.3-35848.6" + process $proc$libresoc.v:35829$1485 assign { } { } assign $0\cnt_2_24[2:0] $1\cnt_2_24[2:0] - attribute \src "libresoc.v:35782.5-35782.29" + attribute \src "libresoc.v:35830.5-35830.29" switch \initial - attribute \src "libresoc.v:35782.9-35782.17" + attribute \src "libresoc.v:35830.9-35830.17" case 1'1 case end @@ -56147,13 +56183,13 @@ module \clz sync always update \cnt_2_24 $0\cnt_2_24[2:0] end - attribute \src "libresoc.v:35801.3-35820.6" - process $proc$libresoc.v:35801$1486 + attribute \src "libresoc.v:35849.3-35868.6" + process $proc$libresoc.v:35849$1486 assign { } { } assign $0\cnt_2_26[2:0] $1\cnt_2_26[2:0] - attribute \src "libresoc.v:35802.5-35802.29" + attribute \src "libresoc.v:35850.5-35850.29" switch \initial - attribute \src "libresoc.v:35802.9-35802.17" + attribute \src "libresoc.v:35850.9-35850.17" case 1'1 case end @@ -56182,13 +56218,13 @@ module \clz sync always update \cnt_2_26 $0\cnt_2_26[2:0] end - attribute \src "libresoc.v:35821.3-35840.6" - process $proc$libresoc.v:35821$1487 + attribute \src "libresoc.v:35869.3-35888.6" + process $proc$libresoc.v:35869$1487 assign { } { } assign $0\cnt_2_28[2:0] $1\cnt_2_28[2:0] - attribute \src "libresoc.v:35822.5-35822.29" + attribute \src "libresoc.v:35870.5-35870.29" switch \initial - attribute \src "libresoc.v:35822.9-35822.17" + attribute \src "libresoc.v:35870.9-35870.17" case 1'1 case end @@ -56217,13 +56253,13 @@ module \clz sync always update \cnt_2_28 $0\cnt_2_28[2:0] end - attribute \src "libresoc.v:35841.3-35860.6" - process $proc$libresoc.v:35841$1488 + attribute \src "libresoc.v:35889.3-35908.6" + process $proc$libresoc.v:35889$1488 assign { } { } assign $0\cnt_2_30[2:0] $1\cnt_2_30[2:0] - attribute \src "libresoc.v:35842.5-35842.29" + attribute \src "libresoc.v:35890.5-35890.29" switch \initial - attribute \src "libresoc.v:35842.9-35842.17" + attribute \src "libresoc.v:35890.9-35890.17" case 1'1 case end @@ -56252,13 +56288,13 @@ module \clz sync always update \cnt_2_30 $0\cnt_2_30[2:0] end - attribute \src "libresoc.v:35861.3-35880.6" - process $proc$libresoc.v:35861$1489 + attribute \src "libresoc.v:35909.3-35928.6" + process $proc$libresoc.v:35909$1489 assign { } { } assign $0\cnt_3_0[3:0] $1\cnt_3_0[3:0] - attribute \src "libresoc.v:35862.5-35862.29" + attribute \src "libresoc.v:35910.5-35910.29" switch \initial - attribute \src "libresoc.v:35862.9-35862.17" + attribute \src "libresoc.v:35910.9-35910.17" case 1'1 case end @@ -56287,13 +56323,13 @@ module \clz sync always update \cnt_3_0 $0\cnt_3_0[3:0] end - attribute \src "libresoc.v:35881.3-35900.6" - process $proc$libresoc.v:35881$1490 + attribute \src "libresoc.v:35929.3-35948.6" + process $proc$libresoc.v:35929$1490 assign { } { } assign $0\cnt_3_2[3:0] $1\cnt_3_2[3:0] - attribute \src "libresoc.v:35882.5-35882.29" + attribute \src "libresoc.v:35930.5-35930.29" switch \initial - attribute \src "libresoc.v:35882.9-35882.17" + attribute \src "libresoc.v:35930.9-35930.17" case 1'1 case end @@ -56322,13 +56358,13 @@ module \clz sync always update \cnt_3_2 $0\cnt_3_2[3:0] end - attribute \src "libresoc.v:35901.3-35920.6" - process $proc$libresoc.v:35901$1491 + attribute \src "libresoc.v:35949.3-35968.6" + process $proc$libresoc.v:35949$1491 assign { } { } assign $0\cnt_3_4[3:0] $1\cnt_3_4[3:0] - attribute \src "libresoc.v:35902.5-35902.29" + attribute \src "libresoc.v:35950.5-35950.29" switch \initial - attribute \src "libresoc.v:35902.9-35902.17" + attribute \src "libresoc.v:35950.9-35950.17" case 1'1 case end @@ -56357,13 +56393,13 @@ module \clz sync always update \cnt_3_4 $0\cnt_3_4[3:0] end - attribute \src "libresoc.v:35921.3-35940.6" - process $proc$libresoc.v:35921$1492 + attribute \src "libresoc.v:35969.3-35988.6" + process $proc$libresoc.v:35969$1492 assign { } { } assign $0\cnt_3_6[3:0] $1\cnt_3_6[3:0] - attribute \src "libresoc.v:35922.5-35922.29" + attribute \src "libresoc.v:35970.5-35970.29" switch \initial - attribute \src "libresoc.v:35922.9-35922.17" + attribute \src "libresoc.v:35970.9-35970.17" case 1'1 case end @@ -56392,13 +56428,13 @@ module \clz sync always update \cnt_3_6 $0\cnt_3_6[3:0] end - attribute \src "libresoc.v:35941.3-35960.6" - process $proc$libresoc.v:35941$1493 + attribute \src "libresoc.v:35989.3-36008.6" + process $proc$libresoc.v:35989$1493 assign { } { } assign $0\cnt_3_8[3:0] $1\cnt_3_8[3:0] - attribute \src "libresoc.v:35942.5-35942.29" + attribute \src "libresoc.v:35990.5-35990.29" switch \initial - attribute \src "libresoc.v:35942.9-35942.17" + attribute \src "libresoc.v:35990.9-35990.17" case 1'1 case end @@ -56427,13 +56463,13 @@ module \clz sync always update \cnt_3_8 $0\cnt_3_8[3:0] end - attribute \src "libresoc.v:35961.3-35980.6" - process $proc$libresoc.v:35961$1494 + attribute \src "libresoc.v:36009.3-36028.6" + process $proc$libresoc.v:36009$1494 assign { } { } assign $0\cnt_3_10[3:0] $1\cnt_3_10[3:0] - attribute \src "libresoc.v:35962.5-35962.29" + attribute \src "libresoc.v:36010.5-36010.29" switch \initial - attribute \src "libresoc.v:35962.9-35962.17" + attribute \src "libresoc.v:36010.9-36010.17" case 1'1 case end @@ -56462,13 +56498,13 @@ module \clz sync always update \cnt_3_10 $0\cnt_3_10[3:0] end - attribute \src "libresoc.v:35981.3-36000.6" - process $proc$libresoc.v:35981$1495 + attribute \src "libresoc.v:36029.3-36048.6" + process $proc$libresoc.v:36029$1495 assign { } { } assign $0\cnt_3_12[3:0] $1\cnt_3_12[3:0] - attribute \src "libresoc.v:35982.5-35982.29" + attribute \src "libresoc.v:36030.5-36030.29" switch \initial - attribute \src "libresoc.v:35982.9-35982.17" + attribute \src "libresoc.v:36030.9-36030.17" case 1'1 case end @@ -56497,13 +56533,13 @@ module \clz sync always update \cnt_3_12 $0\cnt_3_12[3:0] end - attribute \src "libresoc.v:36001.3-36020.6" - process $proc$libresoc.v:36001$1496 + attribute \src "libresoc.v:36049.3-36068.6" + process $proc$libresoc.v:36049$1496 assign { } { } assign $0\cnt_3_14[3:0] $1\cnt_3_14[3:0] - attribute \src "libresoc.v:36002.5-36002.29" + attribute \src "libresoc.v:36050.5-36050.29" switch \initial - attribute \src "libresoc.v:36002.9-36002.17" + attribute \src "libresoc.v:36050.9-36050.17" case 1'1 case end @@ -56532,13 +56568,13 @@ module \clz sync always update \cnt_3_14 $0\cnt_3_14[3:0] end - attribute \src "libresoc.v:36021.3-36040.6" - process $proc$libresoc.v:36021$1497 + attribute \src "libresoc.v:36069.3-36088.6" + process $proc$libresoc.v:36069$1497 assign { } { } assign $0\cnt_4_0[4:0] $1\cnt_4_0[4:0] - attribute \src "libresoc.v:36022.5-36022.29" + attribute \src "libresoc.v:36070.5-36070.29" switch \initial - attribute \src "libresoc.v:36022.9-36022.17" + attribute \src "libresoc.v:36070.9-36070.17" case 1'1 case end @@ -56567,13 +56603,13 @@ module \clz sync always update \cnt_4_0 $0\cnt_4_0[4:0] end - attribute \src "libresoc.v:36041.3-36060.6" - process $proc$libresoc.v:36041$1498 + attribute \src "libresoc.v:36089.3-36108.6" + process $proc$libresoc.v:36089$1498 assign { } { } assign $0\cnt_4_2[4:0] $1\cnt_4_2[4:0] - attribute \src "libresoc.v:36042.5-36042.29" + attribute \src "libresoc.v:36090.5-36090.29" switch \initial - attribute \src "libresoc.v:36042.9-36042.17" + attribute \src "libresoc.v:36090.9-36090.17" case 1'1 case end @@ -56602,13 +56638,13 @@ module \clz sync always update \cnt_4_2 $0\cnt_4_2[4:0] end - attribute \src "libresoc.v:36061.3-36075.6" - process $proc$libresoc.v:36061$1499 + attribute \src "libresoc.v:36109.3-36123.6" + process $proc$libresoc.v:36109$1499 assign { } { } assign $0\cnt_1_4[1:0] $1\cnt_1_4[1:0] - attribute \src "libresoc.v:36062.5-36062.29" + attribute \src "libresoc.v:36110.5-36110.29" switch \initial - attribute \src "libresoc.v:36062.9-36062.17" + attribute \src "libresoc.v:36110.9-36110.17" case 1'1 case end @@ -56630,13 +56666,13 @@ module \clz sync always update \cnt_1_4 $0\cnt_1_4[1:0] end - attribute \src "libresoc.v:36076.3-36095.6" - process $proc$libresoc.v:36076$1500 + attribute \src "libresoc.v:36124.3-36143.6" + process $proc$libresoc.v:36124$1500 assign { } { } assign $0\cnt_4_4[4:0] $1\cnt_4_4[4:0] - attribute \src "libresoc.v:36077.5-36077.29" + attribute \src "libresoc.v:36125.5-36125.29" switch \initial - attribute \src "libresoc.v:36077.9-36077.17" + attribute \src "libresoc.v:36125.9-36125.17" case 1'1 case end @@ -56665,13 +56701,13 @@ module \clz sync always update \cnt_4_4 $0\cnt_4_4[4:0] end - attribute \src "libresoc.v:36096.3-36115.6" - process $proc$libresoc.v:36096$1501 + attribute \src "libresoc.v:36144.3-36163.6" + process $proc$libresoc.v:36144$1501 assign { } { } assign $0\cnt_4_6[4:0] $1\cnt_4_6[4:0] - attribute \src "libresoc.v:36097.5-36097.29" + attribute \src "libresoc.v:36145.5-36145.29" switch \initial - attribute \src "libresoc.v:36097.9-36097.17" + attribute \src "libresoc.v:36145.9-36145.17" case 1'1 case end @@ -56700,13 +56736,13 @@ module \clz sync always update \cnt_4_6 $0\cnt_4_6[4:0] end - attribute \src "libresoc.v:36116.3-36135.6" - process $proc$libresoc.v:36116$1502 + attribute \src "libresoc.v:36164.3-36183.6" + process $proc$libresoc.v:36164$1502 assign { } { } assign $0\cnt_5_0[5:0] $1\cnt_5_0[5:0] - attribute \src "libresoc.v:36117.5-36117.29" + attribute \src "libresoc.v:36165.5-36165.29" switch \initial - attribute \src "libresoc.v:36117.9-36117.17" + attribute \src "libresoc.v:36165.9-36165.17" case 1'1 case end @@ -56735,13 +56771,13 @@ module \clz sync always update \cnt_5_0 $0\cnt_5_0[5:0] end - attribute \src "libresoc.v:36136.3-36155.6" - process $proc$libresoc.v:36136$1503 + attribute \src "libresoc.v:36184.3-36203.6" + process $proc$libresoc.v:36184$1503 assign { } { } assign $0\cnt_5_2[5:0] $1\cnt_5_2[5:0] - attribute \src "libresoc.v:36137.5-36137.29" + attribute \src "libresoc.v:36185.5-36185.29" switch \initial - attribute \src "libresoc.v:36137.9-36137.17" + attribute \src "libresoc.v:36185.9-36185.17" case 1'1 case end @@ -56770,13 +56806,13 @@ module \clz sync always update \cnt_5_2 $0\cnt_5_2[5:0] end - attribute \src "libresoc.v:36156.3-36175.6" - process $proc$libresoc.v:36156$1504 + attribute \src "libresoc.v:36204.3-36223.6" + process $proc$libresoc.v:36204$1504 assign { } { } assign $0\cnt_6_0[6:0] $1\cnt_6_0[6:0] - attribute \src "libresoc.v:36157.5-36157.29" + attribute \src "libresoc.v:36205.5-36205.29" switch \initial - attribute \src "libresoc.v:36157.9-36157.17" + attribute \src "libresoc.v:36205.9-36205.17" case 1'1 case end @@ -56805,99 +56841,99 @@ module \clz sync always update \cnt_6_0 $0\cnt_6_0[6:0] end - connect \$9 $eq$libresoc.v:34983$1349_Y - connect \$99 $eq$libresoc.v:34984$1350_Y - connect \$101 $pos$libresoc.v:34985$1351_Y - connect \$103 $eq$libresoc.v:34986$1352_Y - connect \$105 $eq$libresoc.v:34987$1353_Y - connect \$107 $pos$libresoc.v:34988$1354_Y - connect \$109 $eq$libresoc.v:34989$1355_Y - connect \$111 $eq$libresoc.v:34990$1356_Y - connect \$113 $pos$libresoc.v:34991$1357_Y - connect \$115 $eq$libresoc.v:34992$1358_Y - connect \$117 $eq$libresoc.v:34993$1359_Y - connect \$11 $pos$libresoc.v:34994$1360_Y - connect \$119 $pos$libresoc.v:34995$1361_Y - connect \$121 $eq$libresoc.v:34996$1362_Y - connect \$123 $eq$libresoc.v:34997$1363_Y - connect \$125 $pos$libresoc.v:34998$1364_Y - connect \$127 $eq$libresoc.v:34999$1365_Y - connect \$129 $eq$libresoc.v:35000$1366_Y - connect \$131 $pos$libresoc.v:35001$1367_Y - connect \$133 $eq$libresoc.v:35002$1368_Y - connect \$135 $eq$libresoc.v:35003$1369_Y - connect \$137 $pos$libresoc.v:35004$1370_Y - connect \$13 $eq$libresoc.v:35005$1371_Y - connect \$139 $eq$libresoc.v:35006$1372_Y - connect \$141 $eq$libresoc.v:35007$1373_Y - connect \$143 $pos$libresoc.v:35008$1374_Y - connect \$145 $eq$libresoc.v:35009$1375_Y - connect \$147 $eq$libresoc.v:35010$1376_Y - connect \$149 $pos$libresoc.v:35011$1377_Y - connect \$151 $eq$libresoc.v:35012$1378_Y - connect \$153 $eq$libresoc.v:35013$1379_Y - connect \$155 $pos$libresoc.v:35014$1380_Y - connect \$157 $eq$libresoc.v:35015$1381_Y - connect \$15 $eq$libresoc.v:35016$1382_Y - connect \$159 $eq$libresoc.v:35017$1383_Y - connect \$161 $pos$libresoc.v:35018$1384_Y - connect \$163 $eq$libresoc.v:35019$1385_Y - connect \$165 $eq$libresoc.v:35020$1386_Y - connect \$167 $pos$libresoc.v:35021$1387_Y - connect \$169 $eq$libresoc.v:35022$1388_Y - connect \$171 $eq$libresoc.v:35023$1389_Y - connect \$173 $pos$libresoc.v:35024$1390_Y - connect \$175 $eq$libresoc.v:35025$1391_Y - connect \$177 $eq$libresoc.v:35026$1392_Y - connect \$17 $pos$libresoc.v:35027$1393_Y - connect \$179 $pos$libresoc.v:35028$1394_Y - connect \$181 $eq$libresoc.v:35029$1395_Y - connect \$183 $eq$libresoc.v:35030$1396_Y - connect \$185 $pos$libresoc.v:35031$1397_Y - connect \$1 $eq$libresoc.v:35032$1398_Y - connect \$19 $eq$libresoc.v:35033$1399_Y - connect \$21 $eq$libresoc.v:35034$1400_Y - connect \$23 $pos$libresoc.v:35035$1401_Y - connect \$25 $eq$libresoc.v:35036$1402_Y - connect \$27 $eq$libresoc.v:35037$1403_Y - connect \$29 $pos$libresoc.v:35038$1404_Y - connect \$31 $eq$libresoc.v:35039$1405_Y - connect \$33 $eq$libresoc.v:35040$1406_Y - connect \$35 $pos$libresoc.v:35041$1407_Y - connect \$37 $eq$libresoc.v:35042$1408_Y - connect \$3 $eq$libresoc.v:35043$1409_Y - connect \$39 $eq$libresoc.v:35044$1410_Y - connect \$41 $pos$libresoc.v:35045$1411_Y - connect \$43 $eq$libresoc.v:35046$1412_Y - connect \$45 $eq$libresoc.v:35047$1413_Y - connect \$47 $pos$libresoc.v:35048$1414_Y - connect \$49 $eq$libresoc.v:35049$1415_Y - connect \$51 $eq$libresoc.v:35050$1416_Y - connect \$53 $pos$libresoc.v:35051$1417_Y - connect \$55 $eq$libresoc.v:35052$1418_Y - connect \$57 $eq$libresoc.v:35053$1419_Y - connect \$5 $pos$libresoc.v:35054$1420_Y - connect \$59 $pos$libresoc.v:35055$1421_Y - connect \$61 $eq$libresoc.v:35056$1422_Y - connect \$63 $eq$libresoc.v:35057$1423_Y - connect \$65 $pos$libresoc.v:35058$1424_Y - connect \$67 $eq$libresoc.v:35059$1425_Y - connect \$69 $eq$libresoc.v:35060$1426_Y - connect \$71 $pos$libresoc.v:35061$1427_Y - connect \$73 $eq$libresoc.v:35062$1428_Y - connect \$75 $eq$libresoc.v:35063$1429_Y - connect \$77 $pos$libresoc.v:35064$1430_Y - connect \$7 $eq$libresoc.v:35065$1431_Y - connect \$79 $eq$libresoc.v:35066$1432_Y - connect \$81 $eq$libresoc.v:35067$1433_Y - connect \$83 $pos$libresoc.v:35068$1434_Y - connect \$85 $eq$libresoc.v:35069$1435_Y - connect \$87 $eq$libresoc.v:35070$1436_Y - connect \$89 $pos$libresoc.v:35071$1437_Y - connect \$91 $eq$libresoc.v:35072$1438_Y - connect \$93 $eq$libresoc.v:35073$1439_Y - connect \$95 $pos$libresoc.v:35074$1440_Y - connect \$97 $eq$libresoc.v:35075$1441_Y + connect \$9 $eq$libresoc.v:35031$1349_Y + connect \$99 $eq$libresoc.v:35032$1350_Y + connect \$101 $pos$libresoc.v:35033$1351_Y + connect \$103 $eq$libresoc.v:35034$1352_Y + connect \$105 $eq$libresoc.v:35035$1353_Y + connect \$107 $pos$libresoc.v:35036$1354_Y + connect \$109 $eq$libresoc.v:35037$1355_Y + connect \$111 $eq$libresoc.v:35038$1356_Y + connect \$113 $pos$libresoc.v:35039$1357_Y + connect \$115 $eq$libresoc.v:35040$1358_Y + connect \$117 $eq$libresoc.v:35041$1359_Y + connect \$11 $pos$libresoc.v:35042$1360_Y + connect \$119 $pos$libresoc.v:35043$1361_Y + connect \$121 $eq$libresoc.v:35044$1362_Y + connect \$123 $eq$libresoc.v:35045$1363_Y + connect \$125 $pos$libresoc.v:35046$1364_Y + connect \$127 $eq$libresoc.v:35047$1365_Y + connect \$129 $eq$libresoc.v:35048$1366_Y + connect \$131 $pos$libresoc.v:35049$1367_Y + connect \$133 $eq$libresoc.v:35050$1368_Y + connect \$135 $eq$libresoc.v:35051$1369_Y + connect \$137 $pos$libresoc.v:35052$1370_Y + connect \$13 $eq$libresoc.v:35053$1371_Y + connect \$139 $eq$libresoc.v:35054$1372_Y + connect \$141 $eq$libresoc.v:35055$1373_Y + connect \$143 $pos$libresoc.v:35056$1374_Y + connect \$145 $eq$libresoc.v:35057$1375_Y + connect \$147 $eq$libresoc.v:35058$1376_Y + connect \$149 $pos$libresoc.v:35059$1377_Y + connect \$151 $eq$libresoc.v:35060$1378_Y + connect \$153 $eq$libresoc.v:35061$1379_Y + connect \$155 $pos$libresoc.v:35062$1380_Y + connect \$157 $eq$libresoc.v:35063$1381_Y + connect \$15 $eq$libresoc.v:35064$1382_Y + connect \$159 $eq$libresoc.v:35065$1383_Y + connect \$161 $pos$libresoc.v:35066$1384_Y + connect \$163 $eq$libresoc.v:35067$1385_Y + connect \$165 $eq$libresoc.v:35068$1386_Y + connect \$167 $pos$libresoc.v:35069$1387_Y + connect \$169 $eq$libresoc.v:35070$1388_Y + connect \$171 $eq$libresoc.v:35071$1389_Y + connect \$173 $pos$libresoc.v:35072$1390_Y + connect \$175 $eq$libresoc.v:35073$1391_Y + connect \$177 $eq$libresoc.v:35074$1392_Y + connect \$17 $pos$libresoc.v:35075$1393_Y + connect \$179 $pos$libresoc.v:35076$1394_Y + connect \$181 $eq$libresoc.v:35077$1395_Y + connect \$183 $eq$libresoc.v:35078$1396_Y + connect \$185 $pos$libresoc.v:35079$1397_Y + connect \$1 $eq$libresoc.v:35080$1398_Y + connect \$19 $eq$libresoc.v:35081$1399_Y + connect \$21 $eq$libresoc.v:35082$1400_Y + connect \$23 $pos$libresoc.v:35083$1401_Y + connect \$25 $eq$libresoc.v:35084$1402_Y + connect \$27 $eq$libresoc.v:35085$1403_Y + connect \$29 $pos$libresoc.v:35086$1404_Y + connect \$31 $eq$libresoc.v:35087$1405_Y + connect \$33 $eq$libresoc.v:35088$1406_Y + connect \$35 $pos$libresoc.v:35089$1407_Y + connect \$37 $eq$libresoc.v:35090$1408_Y + connect \$3 $eq$libresoc.v:35091$1409_Y + connect \$39 $eq$libresoc.v:35092$1410_Y + connect \$41 $pos$libresoc.v:35093$1411_Y + connect \$43 $eq$libresoc.v:35094$1412_Y + connect \$45 $eq$libresoc.v:35095$1413_Y + connect \$47 $pos$libresoc.v:35096$1414_Y + connect \$49 $eq$libresoc.v:35097$1415_Y + connect \$51 $eq$libresoc.v:35098$1416_Y + connect \$53 $pos$libresoc.v:35099$1417_Y + connect \$55 $eq$libresoc.v:35100$1418_Y + connect \$57 $eq$libresoc.v:35101$1419_Y + connect \$5 $pos$libresoc.v:35102$1420_Y + connect \$59 $pos$libresoc.v:35103$1421_Y + connect \$61 $eq$libresoc.v:35104$1422_Y + connect \$63 $eq$libresoc.v:35105$1423_Y + connect \$65 $pos$libresoc.v:35106$1424_Y + connect \$67 $eq$libresoc.v:35107$1425_Y + connect \$69 $eq$libresoc.v:35108$1426_Y + connect \$71 $pos$libresoc.v:35109$1427_Y + connect \$73 $eq$libresoc.v:35110$1428_Y + connect \$75 $eq$libresoc.v:35111$1429_Y + connect \$77 $pos$libresoc.v:35112$1430_Y + connect \$7 $eq$libresoc.v:35113$1431_Y + connect \$79 $eq$libresoc.v:35114$1432_Y + connect \$81 $eq$libresoc.v:35115$1433_Y + connect \$83 $pos$libresoc.v:35116$1434_Y + connect \$85 $eq$libresoc.v:35117$1435_Y + connect \$87 $eq$libresoc.v:35118$1436_Y + connect \$89 $pos$libresoc.v:35119$1437_Y + connect \$91 $eq$libresoc.v:35120$1438_Y + connect \$93 $eq$libresoc.v:35121$1439_Y + connect \$95 $pos$libresoc.v:35122$1440_Y + connect \$97 $eq$libresoc.v:35123$1441_Y connect \lz \cnt_6_0 connect \pair62 \sig_in [63:62] connect \pair60 \sig_in [61:60] @@ -56932,4152 +56968,4150 @@ module \clz connect \pair2 \sig_in [3:2] connect \pair0 \sig_in [1:0] end -attribute \src "libresoc.v:36213.1-49141.10" +attribute \src "libresoc.v:36261.1-48917.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core" attribute \generator "nMigen" module \core - attribute \src "libresoc.v:46587.3-46607.6" - wire $0\core_terminate_o$next[0:0]$2673 - attribute \src "libresoc.v:42982.3-42983.49" + attribute \src "libresoc.v:46390.3-46410.6" + wire $0\core_terminate_o$next[0:0]$2679 + attribute \src "libresoc.v:42786.3-42787.49" wire $0\core_terminate_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $0\corebusy_o[0:0] - attribute \src "libresoc.v:46431.3-46457.6" - wire width 2 $0\counter$next[1:0]$2654 - attribute \src "libresoc.v:42984.3-42985.31" + attribute \src "libresoc.v:46220.3-46250.6" + wire width 2 $0\counter$next[1:0]$2657 + attribute \src "libresoc.v:42788.3-42789.31" wire width 2 $0\counter[1:0] - attribute \src "libresoc.v:46412.3-46420.6" + attribute \src "libresoc.v:46192.3-46200.6" wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 - attribute \src "libresoc.v:42918.3-42919.57" + attribute \src "libresoc.v:42722.3-42723.57" wire $0\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:46393.3-46401.6" + attribute \src "libresoc.v:46173.3-46181.6" wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 - attribute \src "libresoc.v:42920.3-42921.49" + attribute \src "libresoc.v:42724.3-42725.49" wire $0\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:46458.3-46466.6" - wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 - attribute \src "libresoc.v:42916.3-42917.49" + attribute \src "libresoc.v:46211.3-46219.6" + wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2654 + attribute \src "libresoc.v:42720.3-42721.49" wire $0\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:46568.3-46576.6" - wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 - attribute \src "libresoc.v:42914.3-42915.49" + attribute \src "libresoc.v:46261.3-46269.6" + wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 + attribute \src "libresoc.v:42718.3-42719.49" wire $0\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:46374.3-46382.6" + attribute \src "libresoc.v:46154.3-46162.6" wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 - attribute \src "libresoc.v:42922.3-42923.55" + attribute \src "libresoc.v:42726.3-42727.55" wire $0\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:46608.3-46616.6" - wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 - attribute \src "libresoc.v:42912.3-42913.63" + attribute \src "libresoc.v:46371.3-46379.6" + wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2673 + attribute \src "libresoc.v:42716.3-42717.63" wire $0\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:46675.3-46683.6" - wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 - attribute \src "libresoc.v:42908.3-42909.57" + attribute \src "libresoc.v:46478.3-46486.6" + wire $0\dp_FAST_fast1_branch0_3$next[0:0]$2697 + attribute \src "libresoc.v:42710.3-42711.63" + wire $0\dp_FAST_fast1_branch0_3[0:0] + attribute \src "libresoc.v:46430.3-46438.6" + wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2690 + attribute \src "libresoc.v:42712.3-42713.57" wire $0\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:46627.3-46635.6" + attribute \src "libresoc.v:46411.3-46419.6" wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 - attribute \src "libresoc.v:42910.3-42911.59" + attribute \src "libresoc.v:42714.3-42715.59" wire $0\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:46723.3-46731.6" - wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 - attribute \src "libresoc.v:42906.3-42907.63" - wire $0\dp_FAST_fast2_branch0_0[0:0] - attribute \src "libresoc.v:46742.3-46750.6" - wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 - attribute \src "libresoc.v:42904.3-42905.59" - wire $0\dp_FAST_fast2_trap0_1[0:0] - attribute \src "libresoc.v:45823.3-45831.6" - wire $0\dp_INT_ra_alu0_0$next[0:0]$2474 - attribute \src "libresoc.v:42980.3-42981.49" - wire $0\dp_INT_ra_alu0_0[0:0] - attribute \src "libresoc.v:45842.3-45850.6" - wire $0\dp_INT_ra_cr0_1$next[0:0]$2478 - attribute \src "libresoc.v:42978.3-42979.47" - wire $0\dp_INT_ra_cr0_1[0:0] - attribute \src "libresoc.v:45918.3-45926.6" - wire $0\dp_INT_ra_div0_5$next[0:0]$2502 - attribute \src "libresoc.v:42970.3-42971.49" - wire $0\dp_INT_ra_div0_5[0:0] - attribute \src "libresoc.v:45975.3-45983.6" - wire $0\dp_INT_ra_ldst0_8$next[0:0]$2520 - attribute \src "libresoc.v:42964.3-42965.51" - wire $0\dp_INT_ra_ldst0_8[0:0] - attribute \src "libresoc.v:45880.3-45888.6" - wire $0\dp_INT_ra_logical0_3$next[0:0]$2490 - attribute \src "libresoc.v:42974.3-42975.57" - wire $0\dp_INT_ra_logical0_3[0:0] - attribute \src "libresoc.v:45937.3-45945.6" - wire $0\dp_INT_ra_mul0_6$next[0:0]$2508 - attribute \src "libresoc.v:42968.3-42969.49" - wire $0\dp_INT_ra_mul0_6[0:0] - attribute \src "libresoc.v:45956.3-45964.6" - wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 - attribute \src "libresoc.v:42966.3-42967.59" - wire $0\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "libresoc.v:45899.3-45907.6" - wire $0\dp_INT_ra_spr0_4$next[0:0]$2496 - attribute \src "libresoc.v:42972.3-42973.49" - wire $0\dp_INT_ra_spr0_4[0:0] - attribute \src "libresoc.v:45861.3-45869.6" - wire $0\dp_INT_ra_trap0_2$next[0:0]$2484 - attribute \src "libresoc.v:42976.3-42977.51" - wire $0\dp_INT_ra_trap0_2[0:0] - attribute \src "libresoc.v:45994.3-46002.6" - wire $0\dp_INT_rb_alu0_0$next[0:0]$2526 - attribute \src "libresoc.v:42962.3-42963.49" - wire $0\dp_INT_rb_alu0_0[0:0] - attribute \src "libresoc.v:46013.3-46021.6" - wire $0\dp_INT_rb_cr0_1$next[0:0]$2530 - attribute \src "libresoc.v:42960.3-42961.47" - wire $0\dp_INT_rb_cr0_1[0:0] - attribute \src "libresoc.v:46070.3-46078.6" - wire $0\dp_INT_rb_div0_4$next[0:0]$2548 - attribute \src "libresoc.v:42954.3-42955.49" - wire $0\dp_INT_rb_div0_4[0:0] - attribute \src "libresoc.v:46127.3-46135.6" - wire $0\dp_INT_rb_ldst0_7$next[0:0]$2566 - attribute \src "libresoc.v:42948.3-42949.51" - wire $0\dp_INT_rb_ldst0_7[0:0] - attribute \src "libresoc.v:46051.3-46059.6" - wire $0\dp_INT_rb_logical0_3$next[0:0]$2542 - attribute \src "libresoc.v:42956.3-42957.57" - wire $0\dp_INT_rb_logical0_3[0:0] - attribute \src "libresoc.v:46089.3-46097.6" - wire $0\dp_INT_rb_mul0_5$next[0:0]$2554 - attribute \src "libresoc.v:42952.3-42953.49" - wire $0\dp_INT_rb_mul0_5[0:0] - attribute \src "libresoc.v:46108.3-46116.6" - wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 - attribute \src "libresoc.v:42950.3-42951.59" - wire $0\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "libresoc.v:46032.3-46040.6" - wire $0\dp_INT_rb_trap0_2$next[0:0]$2536 - attribute \src "libresoc.v:42958.3-42959.51" - wire $0\dp_INT_rb_trap0_2[0:0] - attribute \src "libresoc.v:46165.3-46173.6" - wire $0\dp_INT_rc_ldst0_1$next[0:0]$2576 - attribute \src "libresoc.v:42944.3-42945.51" - wire $0\dp_INT_rc_ldst0_1[0:0] - attribute \src "libresoc.v:46146.3-46154.6" - wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 - attribute \src "libresoc.v:42946.3-42947.59" - wire $0\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "libresoc.v:46791.3-46799.6" - wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 - attribute \src "libresoc.v:42902.3-42903.53" + attribute \src "libresoc.v:46497.3-46505.6" + wire $0\dp_FAST_fast1_trap0_4$next[0:0]$2703 + attribute \src "libresoc.v:42708.3-42709.59" + wire $0\dp_FAST_fast1_trap0_4[0:0] + attribute \src "libresoc.v:45603.3-45611.6" + wire $0\dp_INT_rabc_alu0_0$next[0:0]$2474 + attribute \src "libresoc.v:42784.3-42785.53" + wire $0\dp_INT_rabc_alu0_0[0:0] + attribute \src "libresoc.v:45793.3-45801.6" + wire $0\dp_INT_rabc_alu0_10$next[0:0]$2530 + attribute \src "libresoc.v:42764.3-42765.55" + wire $0\dp_INT_rabc_alu0_10[0:0] + attribute \src "libresoc.v:45622.3-45630.6" + wire $0\dp_INT_rabc_cr0_1$next[0:0]$2478 + attribute \src "libresoc.v:45812.3-45820.6" + wire $0\dp_INT_rabc_cr0_11$next[0:0]$2534 + attribute \src "libresoc.v:42762.3-42763.53" + wire $0\dp_INT_rabc_cr0_11[0:0] + attribute \src "libresoc.v:42782.3-42783.51" + wire $0\dp_INT_rabc_cr0_1[0:0] + attribute \src "libresoc.v:45888.3-45896.6" + wire $0\dp_INT_rabc_div0_15$next[0:0]$2558 + attribute \src "libresoc.v:42754.3-42755.55" + wire $0\dp_INT_rabc_div0_15[0:0] + attribute \src "libresoc.v:45679.3-45687.6" + wire $0\dp_INT_rabc_div0_4$next[0:0]$2496 + attribute \src "libresoc.v:42776.3-42777.53" + wire $0\dp_INT_rabc_div0_4[0:0] + attribute \src "libresoc.v:45945.3-45953.6" + wire $0\dp_INT_rabc_ldst0_18$next[0:0]$2576 + attribute \src "libresoc.v:42748.3-42749.57" + wire $0\dp_INT_rabc_ldst0_18[0:0] + attribute \src "libresoc.v:45736.3-45744.6" + wire $0\dp_INT_rabc_ldst0_7$next[0:0]$2514 + attribute \src "libresoc.v:42770.3-42771.55" + wire $0\dp_INT_rabc_ldst0_7[0:0] + attribute \src "libresoc.v:45774.3-45782.6" + wire $0\dp_INT_rabc_ldst0_9$next[0:0]$2524 + attribute \src "libresoc.v:42766.3-42767.55" + wire $0\dp_INT_rabc_ldst0_9[0:0] + attribute \src "libresoc.v:45850.3-45858.6" + wire $0\dp_INT_rabc_logical0_13$next[0:0]$2546 + attribute \src "libresoc.v:42758.3-42759.63" + wire $0\dp_INT_rabc_logical0_13[0:0] + attribute \src "libresoc.v:45660.3-45668.6" + wire $0\dp_INT_rabc_logical0_3$next[0:0]$2490 + attribute \src "libresoc.v:42778.3-42779.61" + wire $0\dp_INT_rabc_logical0_3[0:0] + attribute \src "libresoc.v:45907.3-45915.6" + wire $0\dp_INT_rabc_mul0_16$next[0:0]$2564 + attribute \src "libresoc.v:42752.3-42753.55" + wire $0\dp_INT_rabc_mul0_16[0:0] + attribute \src "libresoc.v:45698.3-45706.6" + wire $0\dp_INT_rabc_mul0_5$next[0:0]$2502 + attribute \src "libresoc.v:42774.3-42775.53" + wire $0\dp_INT_rabc_mul0_5[0:0] + attribute \src "libresoc.v:45926.3-45934.6" + wire $0\dp_INT_rabc_shiftrot0_17$next[0:0]$2570 + attribute \src "libresoc.v:42750.3-42751.65" + wire $0\dp_INT_rabc_shiftrot0_17[0:0] + attribute \src "libresoc.v:45717.3-45725.6" + wire $0\dp_INT_rabc_shiftrot0_6$next[0:0]$2508 + attribute \src "libresoc.v:42772.3-42773.63" + wire $0\dp_INT_rabc_shiftrot0_6[0:0] + attribute \src "libresoc.v:45755.3-45763.6" + wire $0\dp_INT_rabc_shiftrot0_8$next[0:0]$2520 + attribute \src "libresoc.v:42768.3-42769.63" + wire $0\dp_INT_rabc_shiftrot0_8[0:0] + attribute \src "libresoc.v:45869.3-45877.6" + wire $0\dp_INT_rabc_spr0_14$next[0:0]$2552 + attribute \src "libresoc.v:42756.3-42757.55" + wire $0\dp_INT_rabc_spr0_14[0:0] + attribute \src "libresoc.v:45831.3-45839.6" + wire $0\dp_INT_rabc_trap0_12$next[0:0]$2540 + attribute \src "libresoc.v:42760.3-42761.57" + wire $0\dp_INT_rabc_trap0_12[0:0] + attribute \src "libresoc.v:45641.3-45649.6" + wire $0\dp_INT_rabc_trap0_2$next[0:0]$2484 + attribute \src "libresoc.v:42780.3-42781.55" + wire $0\dp_INT_rabc_trap0_2[0:0] + attribute \src "libresoc.v:46545.3-46553.6" + wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2710 + attribute \src "libresoc.v:42706.3-42707.53" wire $0\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:46298.3-46306.6" + attribute \src "libresoc.v:46078.3-46086.6" wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 - attribute \src "libresoc.v:42930.3-42931.57" + attribute \src "libresoc.v:42734.3-42735.57" wire $0\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:46336.3-46344.6" + attribute \src "libresoc.v:46116.3-46124.6" wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 - attribute \src "libresoc.v:42926.3-42927.67" + attribute \src "libresoc.v:42730.3-42731.67" wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:46317.3-46325.6" + attribute \src "libresoc.v:46097.3-46105.6" wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 - attribute \src "libresoc.v:42928.3-42929.57" + attribute \src "libresoc.v:42732.3-42733.57" wire $0\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:46355.3-46363.6" + attribute \src "libresoc.v:46135.3-46143.6" wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 - attribute \src "libresoc.v:42924.3-42925.57" + attribute \src "libresoc.v:42728.3-42729.57" wire $0\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:46184.3-46192.6" + attribute \src "libresoc.v:45964.3-45972.6" wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 - attribute \src "libresoc.v:42942.3-42943.57" + attribute \src "libresoc.v:42746.3-42747.57" wire $0\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:46241.3-46249.6" + attribute \src "libresoc.v:46021.3-46029.6" wire $0\dp_XER_xer_so_div0_3$next[0:0]$2598 - attribute \src "libresoc.v:42936.3-42937.57" + attribute \src "libresoc.v:42740.3-42741.57" wire $0\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:46203.3-46211.6" + attribute \src "libresoc.v:45983.3-45991.6" wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 - attribute \src "libresoc.v:42940.3-42941.65" + attribute \src "libresoc.v:42744.3-42745.65" wire $0\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:46260.3-46268.6" + attribute \src "libresoc.v:46040.3-46048.6" wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 - attribute \src "libresoc.v:42934.3-42935.57" + attribute \src "libresoc.v:42738.3-42739.57" wire $0\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:46279.3-46287.6" + attribute \src "libresoc.v:46059.3-46067.6" wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 - attribute \src "libresoc.v:42932.3-42933.67" + attribute \src "libresoc.v:42736.3-42737.67" wire $0\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:46222.3-46230.6" + attribute \src "libresoc.v:46002.3-46010.6" wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 - attribute \src "libresoc.v:42938.3-42939.57" + attribute \src "libresoc.v:42742.3-42743.57" wire $0\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:47566.3-47594.6" - wire $0\fus_cu_issue_i$13[0:0]$2821 - attribute \src "libresoc.v:47900.3-47928.6" + attribute \src "libresoc.v:47359.3-47387.6" + wire $0\fus_cu_issue_i$13[0:0]$2824 + attribute \src "libresoc.v:47684.3-47712.6" wire $0\fus_cu_issue_i$16[0:0]$2862 - attribute \src "libresoc.v:48219.3-48247.6" + attribute \src "libresoc.v:48003.3-48031.6" wire $0\fus_cu_issue_i$19[0:0]$2881 - attribute \src "libresoc.v:43868.3-43896.6" + attribute \src "libresoc.v:43648.3-43676.6" wire $0\fus_cu_issue_i$22[0:0]$2359 - attribute \src "libresoc.v:44042.3-44070.6" + attribute \src "libresoc.v:43822.3-43850.6" wire $0\fus_cu_issue_i$25[0:0]$2373 - attribute \src "libresoc.v:44538.3-44566.6" + attribute \src "libresoc.v:44318.3-44346.6" wire $0\fus_cu_issue_i$28[0:0]$2398 - attribute \src "libresoc.v:44860.3-44888.6" + attribute \src "libresoc.v:44640.3-44668.6" wire $0\fus_cu_issue_i$31[0:0]$2417 - attribute \src "libresoc.v:45327.3-45355.6" + attribute \src "libresoc.v:45107.3-45135.6" wire $0\fus_cu_issue_i$34[0:0]$2441 - attribute \src "libresoc.v:45765.3-45793.6" + attribute \src "libresoc.v:45545.3-45573.6" wire $0\fus_cu_issue_i$37[0:0]$2464 - attribute \src "libresoc.v:47349.3-47377.6" + attribute \src "libresoc.v:47151.3-47179.6" wire $0\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47604.3-47632.6" - wire width 6 $0\fus_cu_rdmaskn_i$15[5:0]$2829 - attribute \src "libresoc.v:47929.3-47957.6" + attribute \src "libresoc.v:47406.3-47434.6" + wire width 6 $0\fus_cu_rdmaskn_i$15[5:0]$2835 + attribute \src "libresoc.v:47713.3-47741.6" wire width 3 $0\fus_cu_rdmaskn_i$18[2:0]$2867 - attribute \src "libresoc.v:48248.3-48276.6" + attribute \src "libresoc.v:48032.3-48060.6" wire width 4 $0\fus_cu_rdmaskn_i$21[3:0]$2886 - attribute \src "libresoc.v:43897.3-43925.6" + attribute \src "libresoc.v:43677.3-43705.6" wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2364 - attribute \src "libresoc.v:44071.3-44099.6" + attribute \src "libresoc.v:43851.3-43879.6" wire width 6 $0\fus_cu_rdmaskn_i$27[5:0]$2378 - attribute \src "libresoc.v:44567.3-44595.6" + attribute \src "libresoc.v:44347.3-44375.6" wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2403 - attribute \src "libresoc.v:44889.3-44917.6" + attribute \src "libresoc.v:44669.3-44697.6" wire width 3 $0\fus_cu_rdmaskn_i$33[2:0]$2422 - attribute \src "libresoc.v:45356.3-45384.6" + attribute \src "libresoc.v:45136.3-45164.6" wire width 5 $0\fus_cu_rdmaskn_i$36[4:0]$2446 - attribute \src "libresoc.v:45794.3-45822.6" + attribute \src "libresoc.v:45574.3-45602.6" wire width 3 $0\fus_cu_rdmaskn_i$39[2:0]$2469 - attribute \src "libresoc.v:47396.3-47424.6" + attribute \src "libresoc.v:47189.3-47217.6" wire width 4 $0\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47273.3-47301.6" + attribute \src "libresoc.v:47066.3-47094.6" wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46694.3-46722.6" + attribute \src "libresoc.v:46516.3-46544.6" wire width 14 $0\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46564.3-46593.6" wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46564.3-46593.6" wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:47094.3-47122.6" + attribute \src "libresoc.v:46896.3-46924.6" wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47311.3-47339.6" + attribute \src "libresoc.v:47104.3-47132.6" wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46646.3-46674.6" + attribute \src "libresoc.v:46449.3-46477.6" wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46933.3-46961.6" + attribute \src "libresoc.v:46735.3-46763.6" wire $0\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:47018.3-47046.6" + attribute \src "libresoc.v:46811.3-46839.6" wire $0\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47188.3-47216.6" + attribute \src "libresoc.v:46981.3-47009.6" wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47226.3-47254.6" + attribute \src "libresoc.v:47019.3-47047.6" wire $0\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:47141.3-47169.6" + attribute \src "libresoc.v:46943.3-46971.6" wire $0\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:47056.3-47084.6" + attribute \src "libresoc.v:46849.3-46877.6" wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46980.3-47008.6" + attribute \src "libresoc.v:46773.3-46801.6" wire $0\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:47651.3-47679.6" + attribute \src "libresoc.v:47444.3-47472.6" wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47736.3-47764.6" + attribute \src "libresoc.v:47529.3-47557.6" wire width 14 $0\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47596.3-47625.6" wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47596.3-47625.6" wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47774.3-47802.6" + attribute \src "libresoc.v:47567.3-47595.6" wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47689.3-47717.6" + attribute \src "libresoc.v:47482.3-47510.6" wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47871.3-47899.6" + attribute \src "libresoc.v:47655.3-47683.6" wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47842.3-47870.6" + attribute \src "libresoc.v:47626.3-47654.6" wire $0\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47481.3-47509.6" + attribute \src "libresoc.v:47274.3-47302.6" wire width 14 $0\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47528.3-47556.6" + attribute \src "libresoc.v:47321.3-47349.6" wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47434.3-47462.6" + attribute \src "libresoc.v:47236.3-47264.6" wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:44480.3-44508.6" + attribute \src "libresoc.v:44260.3-44288.6" wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44129.3-44157.6" + attribute \src "libresoc.v:43909.3-43937.6" wire width 14 $0\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:43938.3-43967.6" wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:43938.3-43967.6" wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44306.3-44334.6" + attribute \src "libresoc.v:44086.3-44114.6" wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44509.3-44537.6" + attribute \src "libresoc.v:44289.3-44317.6" wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44100.3-44128.6" + attribute \src "libresoc.v:43880.3-43908.6" wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44248.3-44276.6" + attribute \src "libresoc.v:44028.3-44056.6" wire $0\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44335.3-44363.6" + attribute \src "libresoc.v:44115.3-44143.6" wire $0\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44422.3-44450.6" + attribute \src "libresoc.v:44202.3-44230.6" wire $0\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44451.3-44479.6" + attribute \src "libresoc.v:44231.3-44259.6" wire $0\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $0\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $0\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44393.3-44421.6" + attribute \src "libresoc.v:44173.3-44201.6" wire $0\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $0\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $0\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44364.3-44392.6" + attribute \src "libresoc.v:44144.3-44172.6" wire $0\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44277.3-44305.6" + attribute \src "libresoc.v:44057.3-44085.6" wire $0\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43810.3-43838.6" + attribute \src "libresoc.v:43590.3-43618.6" wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48306.3-48334.6" + attribute \src "libresoc.v:48090.3-48118.6" wire width 14 $0\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48119.3-48148.6" wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48119.3-48148.6" wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48483.3-48511.6" + attribute \src "libresoc.v:48267.3-48295.6" wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:43839.3-43867.6" + attribute \src "libresoc.v:43619.3-43647.6" wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48277.3-48305.6" + attribute \src "libresoc.v:48061.3-48089.6" wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48425.3-48453.6" + attribute \src "libresoc.v:48209.3-48237.6" wire $0\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48512.3-48540.6" + attribute \src "libresoc.v:48296.3-48324.6" wire $0\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:43752.3-43780.6" + attribute \src "libresoc.v:43532.3-43560.6" wire $0\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43781.3-43809.6" + attribute \src "libresoc.v:43561.3-43589.6" wire $0\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $0\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $0\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:43723.3-43751.6" + attribute \src "libresoc.v:43503.3-43531.6" wire $0\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $0\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $0\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48541.3-48569.6" + attribute \src "libresoc.v:48325.3-48353.6" wire $0\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48454.3-48482.6" + attribute \src "libresoc.v:48238.3-48266.6" wire $0\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44625.3-44653.6" + attribute \src "libresoc.v:44405.3-44433.6" wire width 14 $0\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44434.3-44463.6" wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44434.3-44463.6" wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44831.3-44859.6" + attribute \src "libresoc.v:44611.3-44639.6" wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44596.3-44624.6" + attribute \src "libresoc.v:44376.3-44404.6" wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44773.3-44801.6" + attribute \src "libresoc.v:44553.3-44581.6" wire $0\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44802.3-44830.6" + attribute \src "libresoc.v:44582.3-44610.6" wire $0\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $0\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $0\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $0\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $0\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44744.3-44772.6" + attribute \src "libresoc.v:44524.3-44552.6" wire $0\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44947.3-44975.6" + attribute \src "libresoc.v:44727.3-44755.6" wire width 14 $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:44756.3-44785.6" wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:44756.3-44785.6" wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:45124.3-45152.6" + attribute \src "libresoc.v:44904.3-44932.6" wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45182.3-45210.6" + attribute \src "libresoc.v:44962.3-44990.6" wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45298.3-45326.6" + attribute \src "libresoc.v:45078.3-45106.6" wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44918.3-44946.6" + attribute \src "libresoc.v:44698.3-44726.6" wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:45095.3-45123.6" + attribute \src "libresoc.v:44875.3-44903.6" wire $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45240.3-45268.6" + attribute \src "libresoc.v:45020.3-45048.6" wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45269.3-45297.6" + attribute \src "libresoc.v:45049.3-45077.6" wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45153.3-45181.6" + attribute \src "libresoc.v:44933.3-44961.6" wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45211.3-45239.6" + attribute \src "libresoc.v:44991.3-45019.6" wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:45066.3-45094.6" + attribute \src "libresoc.v:44846.3-44874.6" wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:43955.3-43983.6" + attribute \src "libresoc.v:43735.3-43763.6" wire width 14 $0\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43984.3-44012.6" + attribute \src "libresoc.v:43764.3-43792.6" wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43926.3-43954.6" + attribute \src "libresoc.v:43706.3-43734.6" wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:44013.3-44041.6" + attribute \src "libresoc.v:43793.3-43821.6" wire $0\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:48074.3-48102.6" + attribute \src "libresoc.v:47858.3-47886.6" wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47987.3-48015.6" + attribute \src "libresoc.v:47771.3-47799.6" wire width 14 $0\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:48016.3-48044.6" + attribute \src "libresoc.v:47800.3-47828.6" wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47958.3-47986.6" + attribute \src "libresoc.v:47742.3-47770.6" wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:48103.3-48131.6" + attribute \src "libresoc.v:47887.3-47915.6" wire $0\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48190.3-48218.6" + attribute \src "libresoc.v:47974.3-48002.6" wire width 8 $0\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48045.3-48073.6" + attribute \src "libresoc.v:47829.3-47857.6" wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48161.3-48189.6" + attribute \src "libresoc.v:47945.3-47973.6" wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48132.3-48160.6" + attribute \src "libresoc.v:47916.3-47944.6" wire width 8 $0\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45649.3-45677.6" + attribute \src "libresoc.v:45429.3-45457.6" wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45620.3-45648.6" + attribute \src "libresoc.v:45400.3-45428.6" wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45414.3-45442.6" + attribute \src "libresoc.v:45194.3-45222.6" wire width 14 $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45223.3-45252.6" wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45223.3-45252.6" wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45736.3-45764.6" + attribute \src "libresoc.v:45516.3-45544.6" wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45385.3-45413.6" + attribute \src "libresoc.v:45165.3-45193.6" wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45562.3-45590.6" + attribute \src "libresoc.v:45342.3-45370.6" wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45591.3-45619.6" + attribute \src "libresoc.v:45371.3-45399.6" wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45707.3-45735.6" + attribute \src "libresoc.v:45487.3-45515.6" wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45678.3-45706.6" + attribute \src "libresoc.v:45458.3-45486.6" wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45473.3-45501.6" + attribute \src "libresoc.v:45253.3-45281.6" wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45851.3-45860.6" - wire width 64 $0\fus_src1_i$42[63:0]$2481 - attribute \src "libresoc.v:45870.3-45879.6" - wire width 64 $0\fus_src1_i$45[63:0]$2487 - attribute \src "libresoc.v:45889.3-45898.6" - wire width 64 $0\fus_src1_i$48[63:0]$2493 - attribute \src "libresoc.v:45908.3-45917.6" - wire width 64 $0\fus_src1_i$51[63:0]$2499 - attribute \src "libresoc.v:45927.3-45936.6" - wire width 64 $0\fus_src1_i$54[63:0]$2505 - attribute \src "libresoc.v:45946.3-45955.6" - wire width 64 $0\fus_src1_i$57[63:0]$2511 - attribute \src "libresoc.v:45965.3-45974.6" - wire width 64 $0\fus_src1_i$60[63:0]$2517 - attribute \src "libresoc.v:45984.3-45993.6" - wire width 64 $0\fus_src1_i$63[63:0]$2523 - attribute \src "libresoc.v:46617.3-46626.6" - wire width 64 $0\fus_src1_i$86[63:0]$2681 - attribute \src "libresoc.v:45832.3-45841.6" + attribute \src "libresoc.v:45821.3-45830.6" + wire width 64 $0\fus_src1_i$62[63:0]$2537 + attribute \src "libresoc.v:45840.3-45849.6" + wire width 64 $0\fus_src1_i$63[63:0]$2543 + attribute \src "libresoc.v:45859.3-45868.6" + wire width 64 $0\fus_src1_i$64[63:0]$2549 + attribute \src "libresoc.v:45878.3-45887.6" + wire width 64 $0\fus_src1_i$67[63:0]$2555 + attribute \src "libresoc.v:45897.3-45906.6" + wire width 64 $0\fus_src1_i$68[63:0]$2561 + attribute \src "libresoc.v:45916.3-45925.6" + wire width 64 $0\fus_src1_i$69[63:0]$2567 + attribute \src "libresoc.v:45935.3-45944.6" + wire width 64 $0\fus_src1_i$70[63:0]$2573 + attribute \src "libresoc.v:45954.3-45963.6" + wire width 64 $0\fus_src1_i$71[63:0]$2579 + attribute \src "libresoc.v:46380.3-46389.6" + wire width 64 $0\fus_src1_i$86[63:0]$2676 + attribute \src "libresoc.v:45802.3-45811.6" wire width 64 $0\fus_src1_i[63:0] - attribute \src "libresoc.v:46022.3-46031.6" - wire width 64 $0\fus_src2_i$64[63:0]$2533 - attribute \src "libresoc.v:46041.3-46050.6" - wire width 64 $0\fus_src2_i$65[63:0]$2539 - attribute \src "libresoc.v:46060.3-46069.6" - wire width 64 $0\fus_src2_i$66[63:0]$2545 - attribute \src "libresoc.v:46079.3-46088.6" - wire width 64 $0\fus_src2_i$67[63:0]$2551 - attribute \src "libresoc.v:46098.3-46107.6" - wire width 64 $0\fus_src2_i$68[63:0]$2557 - attribute \src "libresoc.v:46117.3-46126.6" - wire width 64 $0\fus_src2_i$69[63:0]$2563 - attribute \src "libresoc.v:46136.3-46145.6" - wire width 64 $0\fus_src2_i$70[63:0]$2569 - attribute \src "libresoc.v:46732.3-46741.6" - wire width 64 $0\fus_src2_i$89[63:0]$2701 - attribute \src "libresoc.v:46800.3-46809.6" - wire width 64 $0\fus_src2_i$91[63:0]$2714 - attribute \src "libresoc.v:46003.3-46012.6" + attribute \src "libresoc.v:45631.3-45640.6" + wire width 64 $0\fus_src2_i$42[63:0]$2481 + attribute \src "libresoc.v:45650.3-45659.6" + wire width 64 $0\fus_src2_i$45[63:0]$2487 + attribute \src "libresoc.v:45669.3-45678.6" + wire width 64 $0\fus_src2_i$48[63:0]$2493 + attribute \src "libresoc.v:45688.3-45697.6" + wire width 64 $0\fus_src2_i$51[63:0]$2499 + attribute \src "libresoc.v:45707.3-45716.6" + wire width 64 $0\fus_src2_i$54[63:0]$2505 + attribute \src "libresoc.v:45726.3-45735.6" + wire width 64 $0\fus_src2_i$57[63:0]$2511 + attribute \src "libresoc.v:45745.3-45754.6" + wire width 64 $0\fus_src2_i$60[63:0]$2517 + attribute \src "libresoc.v:46487.3-46496.6" + wire width 64 $0\fus_src2_i$89[63:0]$2700 + attribute \src "libresoc.v:46554.3-46563.6" + wire width 64 $0\fus_src2_i$91[63:0]$2713 + attribute \src "libresoc.v:45612.3-45621.6" wire width 64 $0\fus_src2_i[63:0] - attribute \src "libresoc.v:46174.3-46183.6" - wire width 64 $0\fus_src3_i$71[63:0]$2579 - attribute \src "libresoc.v:46193.3-46202.6" + attribute \src "libresoc.v:45783.3-45792.6" + wire width 64 $0\fus_src3_i$61[63:0]$2527 + attribute \src "libresoc.v:45973.3-45982.6" wire $0\fus_src3_i$72[0:0]$2585 - attribute \src "libresoc.v:46212.3-46221.6" + attribute \src "libresoc.v:45992.3-46001.6" wire $0\fus_src3_i$73[0:0]$2591 - attribute \src "libresoc.v:46250.3-46259.6" + attribute \src "libresoc.v:46030.3-46039.6" wire $0\fus_src3_i$74[0:0]$2601 - attribute \src "libresoc.v:46269.3-46278.6" + attribute \src "libresoc.v:46049.3-46058.6" wire $0\fus_src3_i$75[0:0]$2607 - attribute \src "libresoc.v:46383.3-46392.6" + attribute \src "libresoc.v:46163.3-46172.6" wire width 32 $0\fus_src3_i$79[31:0]$2639 - attribute \src "libresoc.v:46421.3-46430.6" + attribute \src "libresoc.v:46201.3-46210.6" wire width 4 $0\fus_src3_i$83[3:0]$2651 - attribute \src "libresoc.v:46636.3-46645.6" + attribute \src "libresoc.v:46420.3-46429.6" wire width 64 $0\fus_src3_i$87[63:0]$2687 - attribute \src "libresoc.v:46684.3-46693.6" - wire width 64 $0\fus_src3_i$88[63:0]$2694 - attribute \src "libresoc.v:46155.3-46164.6" + attribute \src "libresoc.v:46439.3-46448.6" + wire width 64 $0\fus_src3_i$88[63:0]$2693 + attribute \src "libresoc.v:45764.3-45773.6" wire width 64 $0\fus_src3_i[63:0] - attribute \src "libresoc.v:46288.3-46297.6" + attribute \src "libresoc.v:46068.3-46077.6" wire $0\fus_src4_i$76[0:0]$2613 - attribute \src "libresoc.v:46307.3-46316.6" + attribute \src "libresoc.v:46087.3-46096.6" wire width 2 $0\fus_src4_i$77[1:0]$2619 - attribute \src "libresoc.v:46402.3-46411.6" + attribute \src "libresoc.v:46182.3-46191.6" wire width 4 $0\fus_src4_i$80[3:0]$2645 - attribute \src "libresoc.v:46751.3-46760.6" - wire width 64 $0\fus_src4_i$90[63:0]$2707 - attribute \src "libresoc.v:46231.3-46240.6" + attribute \src "libresoc.v:46506.3-46515.6" + wire width 64 $0\fus_src4_i$90[63:0]$2706 + attribute \src "libresoc.v:46011.3-46020.6" wire $0\fus_src4_i[0:0] - attribute \src "libresoc.v:46364.3-46373.6" + attribute \src "libresoc.v:46144.3-46153.6" wire width 2 $0\fus_src5_i$78[1:0]$2633 - attribute \src "libresoc.v:46467.3-46476.6" + attribute \src "libresoc.v:46251.3-46260.6" wire width 4 $0\fus_src5_i$84[3:0]$2663 - attribute \src "libresoc.v:46345.3-46354.6" + attribute \src "libresoc.v:46125.3-46134.6" wire width 2 $0\fus_src5_i[1:0] - attribute \src "libresoc.v:46577.3-46586.6" - wire width 4 $0\fus_src6_i$85[3:0]$2670 - attribute \src "libresoc.v:46326.3-46335.6" + attribute \src "libresoc.v:46270.3-46279.6" + wire width 4 $0\fus_src6_i$85[3:0]$2669 + attribute \src "libresoc.v:46106.3-46115.6" wire width 2 $0\fus_src6_i[1:0] - attribute \src "libresoc.v:36214.7-36214.20" + attribute \src "libresoc.v:36262.7-36262.20" wire $0\initial[0:0] - attribute \src "libresoc.v:46858.3-46866.6" - wire $0\wr_pick_dly$1010$next[0:0]$2724 - attribute \src "libresoc.v:42896.3-42897.51" - wire $0\wr_pick_dly$1010[0:0]$2307 - attribute \src "libresoc.v:41726.7-41726.32" - wire $0\wr_pick_dly$1010[0:0]$2945 - attribute \src "libresoc.v:46867.3-46875.6" - wire $0\wr_pick_dly$1031$next[0:0]$2727 - attribute \src "libresoc.v:42894.3-42895.51" - wire $0\wr_pick_dly$1031[0:0]$2305 - attribute \src "libresoc.v:41730.7-41730.32" - wire $0\wr_pick_dly$1031[0:0]$2947 - attribute \src "libresoc.v:46906.3-46914.6" - wire $0\wr_pick_dly$1049$next[0:0]$2731 - attribute \src "libresoc.v:42892.3-42893.51" - wire $0\wr_pick_dly$1049[0:0]$2303 - attribute \src "libresoc.v:41734.7-41734.32" - wire $0\wr_pick_dly$1049[0:0]$2949 - attribute \src "libresoc.v:46915.3-46923.6" - wire $0\wr_pick_dly$1071$next[0:0]$2734 - attribute \src "libresoc.v:42890.3-42891.51" - wire $0\wr_pick_dly$1071[0:0]$2301 - attribute \src "libresoc.v:41738.7-41738.32" - wire $0\wr_pick_dly$1071[0:0]$2951 - attribute \src "libresoc.v:46924.3-46932.6" - wire $0\wr_pick_dly$1091$next[0:0]$2737 - attribute \src "libresoc.v:42888.3-42889.51" - wire $0\wr_pick_dly$1091[0:0]$2299 - attribute \src "libresoc.v:41742.7-41742.32" - wire $0\wr_pick_dly$1091[0:0]$2953 - attribute \src "libresoc.v:46962.3-46970.6" - wire $0\wr_pick_dly$1111$next[0:0]$2741 - attribute \src "libresoc.v:42886.3-42887.51" - wire $0\wr_pick_dly$1111[0:0]$2297 - attribute \src "libresoc.v:41746.7-41746.32" - wire $0\wr_pick_dly$1111[0:0]$2955 - attribute \src "libresoc.v:46971.3-46979.6" - wire $0\wr_pick_dly$1130$next[0:0]$2744 - attribute \src "libresoc.v:42884.3-42885.51" - wire $0\wr_pick_dly$1130[0:0]$2295 - attribute \src "libresoc.v:41750.7-41750.32" - wire $0\wr_pick_dly$1130[0:0]$2957 - attribute \src "libresoc.v:47009.3-47017.6" - wire $0\wr_pick_dly$1148$next[0:0]$2748 - attribute \src "libresoc.v:42882.3-42883.51" - wire $0\wr_pick_dly$1148[0:0]$2293 - attribute \src "libresoc.v:41754.7-41754.32" - wire $0\wr_pick_dly$1148[0:0]$2959 - attribute \src "libresoc.v:47047.3-47055.6" - wire $0\wr_pick_dly$1222$next[0:0]$2752 - attribute \src "libresoc.v:42880.3-42881.51" - wire $0\wr_pick_dly$1222[0:0]$2291 - attribute \src "libresoc.v:41758.7-41758.32" - wire $0\wr_pick_dly$1222[0:0]$2961 - attribute \src "libresoc.v:47085.3-47093.6" - wire $0\wr_pick_dly$1250$next[0:0]$2756 - attribute \src "libresoc.v:42878.3-42879.51" - wire $0\wr_pick_dly$1250[0:0]$2289 - attribute \src "libresoc.v:41762.7-41762.32" - wire $0\wr_pick_dly$1250[0:0]$2963 - attribute \src "libresoc.v:47123.3-47131.6" - wire $0\wr_pick_dly$1270$next[0:0]$2760 - attribute \src "libresoc.v:42876.3-42877.51" - wire $0\wr_pick_dly$1270[0:0]$2287 - attribute \src "libresoc.v:41766.7-41766.32" - wire $0\wr_pick_dly$1270[0:0]$2965 - attribute \src "libresoc.v:47132.3-47140.6" - wire $0\wr_pick_dly$1290$next[0:0]$2763 - attribute \src "libresoc.v:42874.3-42875.51" - wire $0\wr_pick_dly$1290[0:0]$2285 - attribute \src "libresoc.v:41770.7-41770.32" - wire $0\wr_pick_dly$1290[0:0]$2967 - attribute \src "libresoc.v:47170.3-47178.6" - wire $0\wr_pick_dly$1310$next[0:0]$2767 - attribute \src "libresoc.v:42872.3-42873.51" - wire $0\wr_pick_dly$1310[0:0]$2283 - attribute \src "libresoc.v:41774.7-41774.32" - wire $0\wr_pick_dly$1310[0:0]$2969 - attribute \src "libresoc.v:47179.3-47187.6" - wire $0\wr_pick_dly$1330$next[0:0]$2770 - attribute \src "libresoc.v:42870.3-42871.51" - wire $0\wr_pick_dly$1330[0:0]$2281 - attribute \src "libresoc.v:41778.7-41778.32" - wire $0\wr_pick_dly$1330[0:0]$2971 - attribute \src "libresoc.v:47217.3-47225.6" - wire $0\wr_pick_dly$1350$next[0:0]$2774 - attribute \src "libresoc.v:42868.3-42869.51" - wire $0\wr_pick_dly$1350[0:0]$2279 - attribute \src "libresoc.v:41782.7-41782.32" - wire $0\wr_pick_dly$1350[0:0]$2973 - attribute \src "libresoc.v:47255.3-47263.6" - wire $0\wr_pick_dly$1397$next[0:0]$2778 - attribute \src "libresoc.v:42866.3-42867.51" - wire $0\wr_pick_dly$1397[0:0]$2277 - attribute \src "libresoc.v:41786.7-41786.32" - wire $0\wr_pick_dly$1397[0:0]$2975 - attribute \src "libresoc.v:47264.3-47272.6" - wire $0\wr_pick_dly$1413$next[0:0]$2781 - attribute \src "libresoc.v:42864.3-42865.51" - wire $0\wr_pick_dly$1413[0:0]$2275 - attribute \src "libresoc.v:41790.7-41790.32" - wire $0\wr_pick_dly$1413[0:0]$2977 - attribute \src "libresoc.v:47302.3-47310.6" - wire $0\wr_pick_dly$1429$next[0:0]$2785 - attribute \src "libresoc.v:42862.3-42863.51" - wire $0\wr_pick_dly$1429[0:0]$2273 - attribute \src "libresoc.v:41794.7-41794.32" - wire $0\wr_pick_dly$1429[0:0]$2979 - attribute \src "libresoc.v:47340.3-47348.6" - wire $0\wr_pick_dly$1463$next[0:0]$2789 - attribute \src "libresoc.v:42860.3-42861.51" - wire $0\wr_pick_dly$1463[0:0]$2271 - attribute \src "libresoc.v:41798.7-41798.32" - wire $0\wr_pick_dly$1463[0:0]$2981 - attribute \src "libresoc.v:47378.3-47386.6" - wire $0\wr_pick_dly$1479$next[0:0]$2793 - attribute \src "libresoc.v:42858.3-42859.51" - wire $0\wr_pick_dly$1479[0:0]$2269 - attribute \src "libresoc.v:41802.7-41802.32" - wire $0\wr_pick_dly$1479[0:0]$2983 - attribute \src "libresoc.v:47387.3-47395.6" - wire $0\wr_pick_dly$1495$next[0:0]$2796 - attribute \src "libresoc.v:42856.3-42857.51" - wire $0\wr_pick_dly$1495[0:0]$2267 - attribute \src "libresoc.v:41806.7-41806.32" - wire $0\wr_pick_dly$1495[0:0]$2985 - attribute \src "libresoc.v:47425.3-47433.6" - wire $0\wr_pick_dly$1511$next[0:0]$2800 - attribute \src "libresoc.v:42854.3-42855.51" - wire $0\wr_pick_dly$1511[0:0]$2265 - attribute \src "libresoc.v:41810.7-41810.32" - wire $0\wr_pick_dly$1511[0:0]$2987 - attribute \src "libresoc.v:47463.3-47471.6" - wire $0\wr_pick_dly$1547$next[0:0]$2804 - attribute \src "libresoc.v:42852.3-42853.51" - wire $0\wr_pick_dly$1547[0:0]$2263 - attribute \src "libresoc.v:41814.7-41814.32" - wire $0\wr_pick_dly$1547[0:0]$2989 - attribute \src "libresoc.v:47472.3-47480.6" - wire $0\wr_pick_dly$1563$next[0:0]$2807 - attribute \src "libresoc.v:42850.3-42851.51" - wire $0\wr_pick_dly$1563[0:0]$2261 - attribute \src "libresoc.v:41818.7-41818.32" - wire $0\wr_pick_dly$1563[0:0]$2991 - attribute \src "libresoc.v:47510.3-47518.6" - wire $0\wr_pick_dly$1579$next[0:0]$2811 - attribute \src "libresoc.v:42848.3-42849.51" - wire $0\wr_pick_dly$1579[0:0]$2259 - attribute \src "libresoc.v:41822.7-41822.32" - wire $0\wr_pick_dly$1579[0:0]$2993 - attribute \src "libresoc.v:47519.3-47527.6" - wire $0\wr_pick_dly$1595$next[0:0]$2814 - attribute \src "libresoc.v:42846.3-42847.51" - wire $0\wr_pick_dly$1595[0:0]$2257 - attribute \src "libresoc.v:41826.7-41826.32" - wire $0\wr_pick_dly$1595[0:0]$2995 - attribute \src "libresoc.v:47557.3-47565.6" - wire $0\wr_pick_dly$1637$next[0:0]$2818 - attribute \src "libresoc.v:42844.3-42845.51" - wire $0\wr_pick_dly$1637[0:0]$2255 - attribute \src "libresoc.v:41830.7-41830.32" - wire $0\wr_pick_dly$1637[0:0]$2997 - attribute \src "libresoc.v:47595.3-47603.6" - wire $0\wr_pick_dly$1656$next[0:0]$2826 - attribute \src "libresoc.v:42842.3-42843.51" - wire $0\wr_pick_dly$1656[0:0]$2253 - attribute \src "libresoc.v:41834.7-41834.32" - wire $0\wr_pick_dly$1656[0:0]$2999 - attribute \src "libresoc.v:47633.3-47641.6" - wire $0\wr_pick_dly$1672$next[0:0]$2834 - attribute \src "libresoc.v:42840.3-42841.51" - wire $0\wr_pick_dly$1672[0:0]$2251 - attribute \src "libresoc.v:41838.7-41838.32" - wire $0\wr_pick_dly$1672[0:0]$3001 - attribute \src "libresoc.v:47642.3-47650.6" - wire $0\wr_pick_dly$1688$next[0:0]$2837 - attribute \src "libresoc.v:42838.3-42839.51" - wire $0\wr_pick_dly$1688[0:0]$2249 - attribute \src "libresoc.v:41842.7-41842.32" - wire $0\wr_pick_dly$1688[0:0]$3003 - attribute \src "libresoc.v:47680.3-47688.6" - wire $0\wr_pick_dly$1704$next[0:0]$2841 - attribute \src "libresoc.v:42836.3-42837.51" - wire $0\wr_pick_dly$1704[0:0]$2247 - attribute \src "libresoc.v:41846.7-41846.32" - wire $0\wr_pick_dly$1704[0:0]$3005 - attribute \src "libresoc.v:47718.3-47726.6" - wire $0\wr_pick_dly$1748$next[0:0]$2845 - attribute \src "libresoc.v:42834.3-42835.51" - wire $0\wr_pick_dly$1748[0:0]$2245 - attribute \src "libresoc.v:41850.7-41850.32" - wire $0\wr_pick_dly$1748[0:0]$3007 - attribute \src "libresoc.v:47727.3-47735.6" - wire $0\wr_pick_dly$1764$next[0:0]$2848 - attribute \src "libresoc.v:42832.3-42833.51" - wire $0\wr_pick_dly$1764[0:0]$2243 - attribute \src "libresoc.v:41854.7-41854.32" - wire $0\wr_pick_dly$1764[0:0]$3009 - attribute \src "libresoc.v:47765.3-47773.6" - wire $0\wr_pick_dly$1788$next[0:0]$2852 - attribute \src "libresoc.v:42830.3-42831.51" - wire $0\wr_pick_dly$1788[0:0]$2241 - attribute \src "libresoc.v:41858.7-41858.32" - wire $0\wr_pick_dly$1788[0:0]$3011 - attribute \src "libresoc.v:47803.3-47811.6" - wire $0\wr_pick_dly$1808$next[0:0]$2856 - attribute \src "libresoc.v:42828.3-42829.51" - wire $0\wr_pick_dly$1808[0:0]$2239 - attribute \src "libresoc.v:41862.7-41862.32" - wire $0\wr_pick_dly$1808[0:0]$3013 - attribute \src "libresoc.v:46819.3-46827.6" - wire $0\wr_pick_dly$991$next[0:0]$2720 - attribute \src "libresoc.v:42898.3-42899.49" - wire $0\wr_pick_dly$991[0:0]$2309 - attribute \src "libresoc.v:41866.7-41866.31" - wire $0\wr_pick_dly$991[0:0]$3015 - attribute \src "libresoc.v:46810.3-46818.6" + attribute \src "libresoc.v:46612.3-46620.6" + wire $0\wr_pick_dly$1008$next[0:0]$2723 + attribute \src "libresoc.v:42700.3-42701.51" + wire $0\wr_pick_dly$1008[0:0]$2307 + attribute \src "libresoc.v:41530.7-41530.32" + wire $0\wr_pick_dly$1008[0:0]$2945 + attribute \src "libresoc.v:46651.3-46659.6" + wire $0\wr_pick_dly$1029$next[0:0]$2727 + attribute \src "libresoc.v:42698.3-42699.51" + wire $0\wr_pick_dly$1029[0:0]$2305 + attribute \src "libresoc.v:41534.7-41534.32" + wire $0\wr_pick_dly$1029[0:0]$2947 + attribute \src "libresoc.v:46660.3-46668.6" + wire $0\wr_pick_dly$1047$next[0:0]$2730 + attribute \src "libresoc.v:42696.3-42697.51" + wire $0\wr_pick_dly$1047[0:0]$2303 + attribute \src "libresoc.v:41538.7-41538.32" + wire $0\wr_pick_dly$1047[0:0]$2949 + attribute \src "libresoc.v:46669.3-46677.6" + wire $0\wr_pick_dly$1069$next[0:0]$2733 + attribute \src "libresoc.v:42694.3-42695.51" + wire $0\wr_pick_dly$1069[0:0]$2301 + attribute \src "libresoc.v:41542.7-41542.32" + wire $0\wr_pick_dly$1069[0:0]$2951 + attribute \src "libresoc.v:46708.3-46716.6" + wire $0\wr_pick_dly$1089$next[0:0]$2737 + attribute \src "libresoc.v:42692.3-42693.51" + wire $0\wr_pick_dly$1089[0:0]$2299 + attribute \src "libresoc.v:41546.7-41546.32" + wire $0\wr_pick_dly$1089[0:0]$2953 + attribute \src "libresoc.v:46717.3-46725.6" + wire $0\wr_pick_dly$1109$next[0:0]$2740 + attribute \src "libresoc.v:42690.3-42691.51" + wire $0\wr_pick_dly$1109[0:0]$2297 + attribute \src "libresoc.v:41550.7-41550.32" + wire $0\wr_pick_dly$1109[0:0]$2955 + attribute \src "libresoc.v:46726.3-46734.6" + wire $0\wr_pick_dly$1128$next[0:0]$2743 + attribute \src "libresoc.v:42688.3-42689.51" + wire $0\wr_pick_dly$1128[0:0]$2295 + attribute \src "libresoc.v:41554.7-41554.32" + wire $0\wr_pick_dly$1128[0:0]$2957 + attribute \src "libresoc.v:46764.3-46772.6" + wire $0\wr_pick_dly$1146$next[0:0]$2747 + attribute \src "libresoc.v:42686.3-42687.51" + wire $0\wr_pick_dly$1146[0:0]$2293 + attribute \src "libresoc.v:41558.7-41558.32" + wire $0\wr_pick_dly$1146[0:0]$2959 + attribute \src "libresoc.v:46802.3-46810.6" + wire $0\wr_pick_dly$1220$next[0:0]$2751 + attribute \src "libresoc.v:42684.3-42685.51" + wire $0\wr_pick_dly$1220[0:0]$2291 + attribute \src "libresoc.v:41562.7-41562.32" + wire $0\wr_pick_dly$1220[0:0]$2961 + attribute \src "libresoc.v:46840.3-46848.6" + wire $0\wr_pick_dly$1248$next[0:0]$2755 + attribute \src "libresoc.v:42682.3-42683.51" + wire $0\wr_pick_dly$1248[0:0]$2289 + attribute \src "libresoc.v:41566.7-41566.32" + wire $0\wr_pick_dly$1248[0:0]$2963 + attribute \src "libresoc.v:46878.3-46886.6" + wire $0\wr_pick_dly$1268$next[0:0]$2759 + attribute \src "libresoc.v:42680.3-42681.51" + wire $0\wr_pick_dly$1268[0:0]$2287 + attribute \src "libresoc.v:41570.7-41570.32" + wire $0\wr_pick_dly$1268[0:0]$2965 + attribute \src "libresoc.v:46887.3-46895.6" + wire $0\wr_pick_dly$1288$next[0:0]$2762 + attribute \src "libresoc.v:42678.3-42679.51" + wire $0\wr_pick_dly$1288[0:0]$2285 + attribute \src "libresoc.v:41574.7-41574.32" + wire $0\wr_pick_dly$1288[0:0]$2967 + attribute \src "libresoc.v:46925.3-46933.6" + wire $0\wr_pick_dly$1308$next[0:0]$2766 + attribute \src "libresoc.v:42676.3-42677.51" + wire $0\wr_pick_dly$1308[0:0]$2283 + attribute \src "libresoc.v:41578.7-41578.32" + wire $0\wr_pick_dly$1308[0:0]$2969 + attribute \src "libresoc.v:46934.3-46942.6" + wire $0\wr_pick_dly$1328$next[0:0]$2769 + attribute \src "libresoc.v:42674.3-42675.51" + wire $0\wr_pick_dly$1328[0:0]$2281 + attribute \src "libresoc.v:41582.7-41582.32" + wire $0\wr_pick_dly$1328[0:0]$2971 + attribute \src "libresoc.v:46972.3-46980.6" + wire $0\wr_pick_dly$1348$next[0:0]$2773 + attribute \src "libresoc.v:42672.3-42673.51" + wire $0\wr_pick_dly$1348[0:0]$2279 + attribute \src "libresoc.v:41586.7-41586.32" + wire $0\wr_pick_dly$1348[0:0]$2973 + attribute \src "libresoc.v:47010.3-47018.6" + wire $0\wr_pick_dly$1395$next[0:0]$2777 + attribute \src "libresoc.v:42670.3-42671.51" + wire $0\wr_pick_dly$1395[0:0]$2277 + attribute \src "libresoc.v:41590.7-41590.32" + wire $0\wr_pick_dly$1395[0:0]$2975 + attribute \src "libresoc.v:47048.3-47056.6" + wire $0\wr_pick_dly$1411$next[0:0]$2781 + attribute \src "libresoc.v:42668.3-42669.51" + wire $0\wr_pick_dly$1411[0:0]$2275 + attribute \src "libresoc.v:41594.7-41594.32" + wire $0\wr_pick_dly$1411[0:0]$2977 + attribute \src "libresoc.v:47057.3-47065.6" + wire $0\wr_pick_dly$1427$next[0:0]$2784 + attribute \src "libresoc.v:42666.3-42667.51" + wire $0\wr_pick_dly$1427[0:0]$2273 + attribute \src "libresoc.v:41598.7-41598.32" + wire $0\wr_pick_dly$1427[0:0]$2979 + attribute \src "libresoc.v:47095.3-47103.6" + wire $0\wr_pick_dly$1461$next[0:0]$2788 + attribute \src "libresoc.v:42664.3-42665.51" + wire $0\wr_pick_dly$1461[0:0]$2271 + attribute \src "libresoc.v:41602.7-41602.32" + wire $0\wr_pick_dly$1461[0:0]$2981 + attribute \src "libresoc.v:47133.3-47141.6" + wire $0\wr_pick_dly$1477$next[0:0]$2792 + attribute \src "libresoc.v:42662.3-42663.51" + wire $0\wr_pick_dly$1477[0:0]$2269 + attribute \src "libresoc.v:41606.7-41606.32" + wire $0\wr_pick_dly$1477[0:0]$2983 + attribute \src "libresoc.v:47142.3-47150.6" + wire $0\wr_pick_dly$1493$next[0:0]$2795 + attribute \src "libresoc.v:42660.3-42661.51" + wire $0\wr_pick_dly$1493[0:0]$2267 + attribute \src "libresoc.v:41610.7-41610.32" + wire $0\wr_pick_dly$1493[0:0]$2985 + attribute \src "libresoc.v:47180.3-47188.6" + wire $0\wr_pick_dly$1509$next[0:0]$2799 + attribute \src "libresoc.v:42658.3-42659.51" + wire $0\wr_pick_dly$1509[0:0]$2265 + attribute \src "libresoc.v:41614.7-41614.32" + wire $0\wr_pick_dly$1509[0:0]$2987 + attribute \src "libresoc.v:47218.3-47226.6" + wire $0\wr_pick_dly$1545$next[0:0]$2803 + attribute \src "libresoc.v:42656.3-42657.51" + wire $0\wr_pick_dly$1545[0:0]$2263 + attribute \src "libresoc.v:41618.7-41618.32" + wire $0\wr_pick_dly$1545[0:0]$2989 + attribute \src "libresoc.v:47227.3-47235.6" + wire $0\wr_pick_dly$1561$next[0:0]$2806 + attribute \src "libresoc.v:42654.3-42655.51" + wire $0\wr_pick_dly$1561[0:0]$2261 + attribute \src "libresoc.v:41622.7-41622.32" + wire $0\wr_pick_dly$1561[0:0]$2991 + attribute \src "libresoc.v:47265.3-47273.6" + wire $0\wr_pick_dly$1577$next[0:0]$2810 + attribute \src "libresoc.v:42652.3-42653.51" + wire $0\wr_pick_dly$1577[0:0]$2259 + attribute \src "libresoc.v:41626.7-41626.32" + wire $0\wr_pick_dly$1577[0:0]$2993 + attribute \src "libresoc.v:47303.3-47311.6" + wire $0\wr_pick_dly$1593$next[0:0]$2814 + attribute \src "libresoc.v:42650.3-42651.51" + wire $0\wr_pick_dly$1593[0:0]$2257 + attribute \src "libresoc.v:41630.7-41630.32" + wire $0\wr_pick_dly$1593[0:0]$2995 + attribute \src "libresoc.v:47312.3-47320.6" + wire $0\wr_pick_dly$1635$next[0:0]$2817 + attribute \src "libresoc.v:42648.3-42649.51" + wire $0\wr_pick_dly$1635[0:0]$2255 + attribute \src "libresoc.v:41634.7-41634.32" + wire $0\wr_pick_dly$1635[0:0]$2997 + attribute \src "libresoc.v:47350.3-47358.6" + wire $0\wr_pick_dly$1654$next[0:0]$2821 + attribute \src "libresoc.v:42646.3-42647.51" + wire $0\wr_pick_dly$1654[0:0]$2253 + attribute \src "libresoc.v:41638.7-41638.32" + wire $0\wr_pick_dly$1654[0:0]$2999 + attribute \src "libresoc.v:47388.3-47396.6" + wire $0\wr_pick_dly$1670$next[0:0]$2829 + attribute \src "libresoc.v:42644.3-42645.51" + wire $0\wr_pick_dly$1670[0:0]$2251 + attribute \src "libresoc.v:41642.7-41642.32" + wire $0\wr_pick_dly$1670[0:0]$3001 + attribute \src "libresoc.v:47397.3-47405.6" + wire $0\wr_pick_dly$1686$next[0:0]$2832 + attribute \src "libresoc.v:42642.3-42643.51" + wire $0\wr_pick_dly$1686[0:0]$2249 + attribute \src "libresoc.v:41646.7-41646.32" + wire $0\wr_pick_dly$1686[0:0]$3003 + attribute \src "libresoc.v:47435.3-47443.6" + wire $0\wr_pick_dly$1702$next[0:0]$2840 + attribute \src "libresoc.v:42640.3-42641.51" + wire $0\wr_pick_dly$1702[0:0]$2247 + attribute \src "libresoc.v:41650.7-41650.32" + wire $0\wr_pick_dly$1702[0:0]$3005 + attribute \src "libresoc.v:47473.3-47481.6" + wire $0\wr_pick_dly$1746$next[0:0]$2844 + attribute \src "libresoc.v:42638.3-42639.51" + wire $0\wr_pick_dly$1746[0:0]$2245 + attribute \src "libresoc.v:41654.7-41654.32" + wire $0\wr_pick_dly$1746[0:0]$3007 + attribute \src "libresoc.v:47511.3-47519.6" + wire $0\wr_pick_dly$1762$next[0:0]$2848 + attribute \src "libresoc.v:42636.3-42637.51" + wire $0\wr_pick_dly$1762[0:0]$2243 + attribute \src "libresoc.v:41658.7-41658.32" + wire $0\wr_pick_dly$1762[0:0]$3009 + attribute \src "libresoc.v:47520.3-47528.6" + wire $0\wr_pick_dly$1786$next[0:0]$2851 + attribute \src "libresoc.v:42634.3-42635.51" + wire $0\wr_pick_dly$1786[0:0]$2241 + attribute \src "libresoc.v:41662.7-41662.32" + wire $0\wr_pick_dly$1786[0:0]$3011 + attribute \src "libresoc.v:47558.3-47566.6" + wire $0\wr_pick_dly$1806$next[0:0]$2855 + attribute \src "libresoc.v:42632.3-42633.51" + wire $0\wr_pick_dly$1806[0:0]$2239 + attribute \src "libresoc.v:41666.7-41666.32" + wire $0\wr_pick_dly$1806[0:0]$3013 + attribute \src "libresoc.v:46603.3-46611.6" + wire $0\wr_pick_dly$989$next[0:0]$2720 + attribute \src "libresoc.v:42702.3-42703.49" + wire $0\wr_pick_dly$989[0:0]$2309 + attribute \src "libresoc.v:41670.7-41670.31" + wire $0\wr_pick_dly$989[0:0]$3015 + attribute \src "libresoc.v:46594.3-46602.6" wire $0\wr_pick_dly$next[0:0]$2717 - attribute \src "libresoc.v:42900.3-42901.39" + attribute \src "libresoc.v:42704.3-42705.39" wire $0\wr_pick_dly[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $10\corebusy_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $11\corebusy_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $12\corebusy_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $13\corebusy_o[0:0] - attribute \src "libresoc.v:46587.3-46607.6" - wire $1\core_terminate_o$next[0:0]$2674 - attribute \src "libresoc.v:38263.7-38263.30" + attribute \src "libresoc.v:46390.3-46410.6" + wire $1\core_terminate_o$next[0:0]$2680 + attribute \src "libresoc.v:38103.7-38103.30" wire $1\core_terminate_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $1\corebusy_o[0:0] - attribute \src "libresoc.v:46431.3-46457.6" - wire width 2 $1\counter$next[1:0]$2655 - attribute \src "libresoc.v:38276.13-38276.27" + attribute \src "libresoc.v:46220.3-46250.6" + wire width 2 $1\counter$next[1:0]$2658 + attribute \src "libresoc.v:38116.13-38116.27" wire width 2 $1\counter[1:0] - attribute \src "libresoc.v:46412.3-46420.6" + attribute \src "libresoc.v:46192.3-46200.6" wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 - attribute \src "libresoc.v:39443.7-39443.34" + attribute \src "libresoc.v:39283.7-39283.34" wire $1\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:46393.3-46401.6" + attribute \src "libresoc.v:46173.3-46181.6" wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 - attribute \src "libresoc.v:39447.7-39447.30" + attribute \src "libresoc.v:39287.7-39287.30" wire $1\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:46458.3-46466.6" - wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 - attribute \src "libresoc.v:39451.7-39451.30" + attribute \src "libresoc.v:46211.3-46219.6" + wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2655 + attribute \src "libresoc.v:39291.7-39291.30" wire $1\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:46568.3-46576.6" - wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 - attribute \src "libresoc.v:39455.7-39455.30" + attribute \src "libresoc.v:46261.3-46269.6" + wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 + attribute \src "libresoc.v:39295.7-39295.30" wire $1\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:46374.3-46382.6" + attribute \src "libresoc.v:46154.3-46162.6" wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 - attribute \src "libresoc.v:39459.7-39459.33" + attribute \src "libresoc.v:39299.7-39299.33" wire $1\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:46608.3-46616.6" - wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 - attribute \src "libresoc.v:39463.7-39463.37" + attribute \src "libresoc.v:46371.3-46379.6" + wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2674 + attribute \src "libresoc.v:39303.7-39303.37" wire $1\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:46675.3-46683.6" - wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 - attribute \src "libresoc.v:39467.7-39467.34" + attribute \src "libresoc.v:46478.3-46486.6" + wire $1\dp_FAST_fast1_branch0_3$next[0:0]$2698 + attribute \src "libresoc.v:39307.7-39307.37" + wire $1\dp_FAST_fast1_branch0_3[0:0] + attribute \src "libresoc.v:46430.3-46438.6" + wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2691 + attribute \src "libresoc.v:39311.7-39311.34" wire $1\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:46627.3-46635.6" + attribute \src "libresoc.v:46411.3-46419.6" wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 - attribute \src "libresoc.v:39471.7-39471.35" + attribute \src "libresoc.v:39315.7-39315.35" wire $1\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:46723.3-46731.6" - wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 - attribute \src "libresoc.v:39475.7-39475.37" - wire $1\dp_FAST_fast2_branch0_0[0:0] - attribute \src "libresoc.v:46742.3-46750.6" - wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 - attribute \src "libresoc.v:39479.7-39479.35" - wire $1\dp_FAST_fast2_trap0_1[0:0] - attribute \src "libresoc.v:45823.3-45831.6" - wire $1\dp_INT_ra_alu0_0$next[0:0]$2475 - attribute \src "libresoc.v:39483.7-39483.30" - wire $1\dp_INT_ra_alu0_0[0:0] - attribute \src "libresoc.v:45842.3-45850.6" - wire $1\dp_INT_ra_cr0_1$next[0:0]$2479 - attribute \src "libresoc.v:39487.7-39487.29" - wire $1\dp_INT_ra_cr0_1[0:0] - attribute \src "libresoc.v:45918.3-45926.6" - wire $1\dp_INT_ra_div0_5$next[0:0]$2503 - attribute \src "libresoc.v:39491.7-39491.30" - wire $1\dp_INT_ra_div0_5[0:0] - attribute \src "libresoc.v:45975.3-45983.6" - wire $1\dp_INT_ra_ldst0_8$next[0:0]$2521 - attribute \src "libresoc.v:39495.7-39495.31" - wire $1\dp_INT_ra_ldst0_8[0:0] - attribute \src "libresoc.v:45880.3-45888.6" - wire $1\dp_INT_ra_logical0_3$next[0:0]$2491 - attribute \src "libresoc.v:39499.7-39499.34" - wire $1\dp_INT_ra_logical0_3[0:0] - attribute \src "libresoc.v:45937.3-45945.6" - wire $1\dp_INT_ra_mul0_6$next[0:0]$2509 - attribute \src "libresoc.v:39503.7-39503.30" - wire $1\dp_INT_ra_mul0_6[0:0] - attribute \src "libresoc.v:45956.3-45964.6" - wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 - attribute \src "libresoc.v:39507.7-39507.35" - wire $1\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "libresoc.v:45899.3-45907.6" - wire $1\dp_INT_ra_spr0_4$next[0:0]$2497 - attribute \src "libresoc.v:39511.7-39511.30" - wire $1\dp_INT_ra_spr0_4[0:0] - attribute \src "libresoc.v:45861.3-45869.6" - wire $1\dp_INT_ra_trap0_2$next[0:0]$2485 - attribute \src "libresoc.v:39515.7-39515.31" - wire $1\dp_INT_ra_trap0_2[0:0] - attribute \src "libresoc.v:45994.3-46002.6" - wire $1\dp_INT_rb_alu0_0$next[0:0]$2527 - attribute \src "libresoc.v:39519.7-39519.30" - wire $1\dp_INT_rb_alu0_0[0:0] - attribute \src "libresoc.v:46013.3-46021.6" - wire $1\dp_INT_rb_cr0_1$next[0:0]$2531 - attribute \src "libresoc.v:39523.7-39523.29" - wire $1\dp_INT_rb_cr0_1[0:0] - attribute \src "libresoc.v:46070.3-46078.6" - wire $1\dp_INT_rb_div0_4$next[0:0]$2549 - attribute \src "libresoc.v:39527.7-39527.30" - wire $1\dp_INT_rb_div0_4[0:0] - attribute \src "libresoc.v:46127.3-46135.6" - wire $1\dp_INT_rb_ldst0_7$next[0:0]$2567 - attribute \src "libresoc.v:39531.7-39531.31" - wire $1\dp_INT_rb_ldst0_7[0:0] - attribute \src "libresoc.v:46051.3-46059.6" - wire $1\dp_INT_rb_logical0_3$next[0:0]$2543 - attribute \src "libresoc.v:39535.7-39535.34" - wire $1\dp_INT_rb_logical0_3[0:0] - attribute \src "libresoc.v:46089.3-46097.6" - wire $1\dp_INT_rb_mul0_5$next[0:0]$2555 - attribute \src "libresoc.v:39539.7-39539.30" - wire $1\dp_INT_rb_mul0_5[0:0] - attribute \src "libresoc.v:46108.3-46116.6" - wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 - attribute \src "libresoc.v:39543.7-39543.35" - wire $1\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "libresoc.v:46032.3-46040.6" - wire $1\dp_INT_rb_trap0_2$next[0:0]$2537 - attribute \src "libresoc.v:39547.7-39547.31" - wire $1\dp_INT_rb_trap0_2[0:0] - attribute \src "libresoc.v:46165.3-46173.6" - wire $1\dp_INT_rc_ldst0_1$next[0:0]$2577 - attribute \src "libresoc.v:39551.7-39551.31" - wire $1\dp_INT_rc_ldst0_1[0:0] - attribute \src "libresoc.v:46146.3-46154.6" - wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 - attribute \src "libresoc.v:39555.7-39555.35" - wire $1\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "libresoc.v:46791.3-46799.6" - wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 - attribute \src "libresoc.v:39559.7-39559.32" + attribute \src "libresoc.v:46497.3-46505.6" + wire $1\dp_FAST_fast1_trap0_4$next[0:0]$2704 + attribute \src "libresoc.v:39319.7-39319.35" + wire $1\dp_FAST_fast1_trap0_4[0:0] + attribute \src "libresoc.v:45603.3-45611.6" + wire $1\dp_INT_rabc_alu0_0$next[0:0]$2475 + attribute \src "libresoc.v:39323.7-39323.32" + wire $1\dp_INT_rabc_alu0_0[0:0] + attribute \src "libresoc.v:45793.3-45801.6" + wire $1\dp_INT_rabc_alu0_10$next[0:0]$2531 + attribute \src "libresoc.v:39327.7-39327.33" + wire $1\dp_INT_rabc_alu0_10[0:0] + attribute \src "libresoc.v:45622.3-45630.6" + wire $1\dp_INT_rabc_cr0_1$next[0:0]$2479 + attribute \src "libresoc.v:45812.3-45820.6" + wire $1\dp_INT_rabc_cr0_11$next[0:0]$2535 + attribute \src "libresoc.v:39335.7-39335.32" + wire $1\dp_INT_rabc_cr0_11[0:0] + attribute \src "libresoc.v:39331.7-39331.31" + wire $1\dp_INT_rabc_cr0_1[0:0] + attribute \src "libresoc.v:45888.3-45896.6" + wire $1\dp_INT_rabc_div0_15$next[0:0]$2559 + attribute \src "libresoc.v:39339.7-39339.33" + wire $1\dp_INT_rabc_div0_15[0:0] + attribute \src "libresoc.v:45679.3-45687.6" + wire $1\dp_INT_rabc_div0_4$next[0:0]$2497 + attribute \src "libresoc.v:39343.7-39343.32" + wire $1\dp_INT_rabc_div0_4[0:0] + attribute \src "libresoc.v:45945.3-45953.6" + wire $1\dp_INT_rabc_ldst0_18$next[0:0]$2577 + attribute \src "libresoc.v:39347.7-39347.34" + wire $1\dp_INT_rabc_ldst0_18[0:0] + attribute \src "libresoc.v:45736.3-45744.6" + wire $1\dp_INT_rabc_ldst0_7$next[0:0]$2515 + attribute \src "libresoc.v:39351.7-39351.33" + wire $1\dp_INT_rabc_ldst0_7[0:0] + attribute \src "libresoc.v:45774.3-45782.6" + wire $1\dp_INT_rabc_ldst0_9$next[0:0]$2525 + attribute \src "libresoc.v:39355.7-39355.33" + wire $1\dp_INT_rabc_ldst0_9[0:0] + attribute \src "libresoc.v:45850.3-45858.6" + wire $1\dp_INT_rabc_logical0_13$next[0:0]$2547 + attribute \src "libresoc.v:39359.7-39359.37" + wire $1\dp_INT_rabc_logical0_13[0:0] + attribute \src "libresoc.v:45660.3-45668.6" + wire $1\dp_INT_rabc_logical0_3$next[0:0]$2491 + attribute \src "libresoc.v:39363.7-39363.36" + wire $1\dp_INT_rabc_logical0_3[0:0] + attribute \src "libresoc.v:45907.3-45915.6" + wire $1\dp_INT_rabc_mul0_16$next[0:0]$2565 + attribute \src "libresoc.v:39367.7-39367.33" + wire $1\dp_INT_rabc_mul0_16[0:0] + attribute \src "libresoc.v:45698.3-45706.6" + wire $1\dp_INT_rabc_mul0_5$next[0:0]$2503 + attribute \src "libresoc.v:39371.7-39371.32" + wire $1\dp_INT_rabc_mul0_5[0:0] + attribute \src "libresoc.v:45926.3-45934.6" + wire $1\dp_INT_rabc_shiftrot0_17$next[0:0]$2571 + attribute \src "libresoc.v:39375.7-39375.38" + wire $1\dp_INT_rabc_shiftrot0_17[0:0] + attribute \src "libresoc.v:45717.3-45725.6" + wire $1\dp_INT_rabc_shiftrot0_6$next[0:0]$2509 + attribute \src "libresoc.v:39379.7-39379.37" + wire $1\dp_INT_rabc_shiftrot0_6[0:0] + attribute \src "libresoc.v:45755.3-45763.6" + wire $1\dp_INT_rabc_shiftrot0_8$next[0:0]$2521 + attribute \src "libresoc.v:39383.7-39383.37" + wire $1\dp_INT_rabc_shiftrot0_8[0:0] + attribute \src "libresoc.v:45869.3-45877.6" + wire $1\dp_INT_rabc_spr0_14$next[0:0]$2553 + attribute \src "libresoc.v:39387.7-39387.33" + wire $1\dp_INT_rabc_spr0_14[0:0] + attribute \src "libresoc.v:45831.3-45839.6" + wire $1\dp_INT_rabc_trap0_12$next[0:0]$2541 + attribute \src "libresoc.v:39391.7-39391.34" + wire $1\dp_INT_rabc_trap0_12[0:0] + attribute \src "libresoc.v:45641.3-45649.6" + wire $1\dp_INT_rabc_trap0_2$next[0:0]$2485 + attribute \src "libresoc.v:39395.7-39395.33" + wire $1\dp_INT_rabc_trap0_2[0:0] + attribute \src "libresoc.v:46545.3-46553.6" + wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2711 + attribute \src "libresoc.v:39399.7-39399.32" wire $1\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:46298.3-46306.6" + attribute \src "libresoc.v:46078.3-46086.6" wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 - attribute \src "libresoc.v:39563.7-39563.34" + attribute \src "libresoc.v:39403.7-39403.34" wire $1\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:46336.3-46344.6" + attribute \src "libresoc.v:46116.3-46124.6" wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 - attribute \src "libresoc.v:39567.7-39567.39" + attribute \src "libresoc.v:39407.7-39407.39" wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:46317.3-46325.6" + attribute \src "libresoc.v:46097.3-46105.6" wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 - attribute \src "libresoc.v:39571.7-39571.34" + attribute \src "libresoc.v:39411.7-39411.34" wire $1\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:46355.3-46363.6" + attribute \src "libresoc.v:46135.3-46143.6" wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 - attribute \src "libresoc.v:39575.7-39575.34" + attribute \src "libresoc.v:39415.7-39415.34" wire $1\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:46184.3-46192.6" + attribute \src "libresoc.v:45964.3-45972.6" wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 - attribute \src "libresoc.v:39579.7-39579.34" + attribute \src "libresoc.v:39419.7-39419.34" wire $1\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:46241.3-46249.6" + attribute \src "libresoc.v:46021.3-46029.6" wire $1\dp_XER_xer_so_div0_3$next[0:0]$2599 - attribute \src "libresoc.v:39583.7-39583.34" + attribute \src "libresoc.v:39423.7-39423.34" wire $1\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:46203.3-46211.6" + attribute \src "libresoc.v:45983.3-45991.6" wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 - attribute \src "libresoc.v:39587.7-39587.38" + attribute \src "libresoc.v:39427.7-39427.38" wire $1\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:46260.3-46268.6" + attribute \src "libresoc.v:46040.3-46048.6" wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 - attribute \src "libresoc.v:39591.7-39591.34" + attribute \src "libresoc.v:39431.7-39431.34" wire $1\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:46279.3-46287.6" + attribute \src "libresoc.v:46059.3-46067.6" wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 - attribute \src "libresoc.v:39595.7-39595.39" + attribute \src "libresoc.v:39435.7-39435.39" wire $1\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:46222.3-46230.6" + attribute \src "libresoc.v:46002.3-46010.6" wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 - attribute \src "libresoc.v:39599.7-39599.34" + attribute \src "libresoc.v:39439.7-39439.34" wire $1\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:47566.3-47594.6" - wire $1\fus_cu_issue_i$13[0:0]$2822 - attribute \src "libresoc.v:47900.3-47928.6" + attribute \src "libresoc.v:47359.3-47387.6" + wire $1\fus_cu_issue_i$13[0:0]$2825 + attribute \src "libresoc.v:47684.3-47712.6" wire $1\fus_cu_issue_i$16[0:0]$2863 - attribute \src "libresoc.v:48219.3-48247.6" + attribute \src "libresoc.v:48003.3-48031.6" wire $1\fus_cu_issue_i$19[0:0]$2882 - attribute \src "libresoc.v:43868.3-43896.6" + attribute \src "libresoc.v:43648.3-43676.6" wire $1\fus_cu_issue_i$22[0:0]$2360 - attribute \src "libresoc.v:44042.3-44070.6" + attribute \src "libresoc.v:43822.3-43850.6" wire $1\fus_cu_issue_i$25[0:0]$2374 - attribute \src "libresoc.v:44538.3-44566.6" + attribute \src "libresoc.v:44318.3-44346.6" wire $1\fus_cu_issue_i$28[0:0]$2399 - attribute \src "libresoc.v:44860.3-44888.6" + attribute \src "libresoc.v:44640.3-44668.6" wire $1\fus_cu_issue_i$31[0:0]$2418 - attribute \src "libresoc.v:45327.3-45355.6" + attribute \src "libresoc.v:45107.3-45135.6" wire $1\fus_cu_issue_i$34[0:0]$2442 - attribute \src "libresoc.v:45765.3-45793.6" + attribute \src "libresoc.v:45545.3-45573.6" wire $1\fus_cu_issue_i$37[0:0]$2465 - attribute \src "libresoc.v:47349.3-47377.6" + attribute \src "libresoc.v:47151.3-47179.6" wire $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47604.3-47632.6" - wire width 6 $1\fus_cu_rdmaskn_i$15[5:0]$2830 - attribute \src "libresoc.v:47929.3-47957.6" + attribute \src "libresoc.v:47406.3-47434.6" + wire width 6 $1\fus_cu_rdmaskn_i$15[5:0]$2836 + attribute \src "libresoc.v:47713.3-47741.6" wire width 3 $1\fus_cu_rdmaskn_i$18[2:0]$2868 - attribute \src "libresoc.v:48248.3-48276.6" + attribute \src "libresoc.v:48032.3-48060.6" wire width 4 $1\fus_cu_rdmaskn_i$21[3:0]$2887 - attribute \src "libresoc.v:43897.3-43925.6" + attribute \src "libresoc.v:43677.3-43705.6" wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2365 - attribute \src "libresoc.v:44071.3-44099.6" + attribute \src "libresoc.v:43851.3-43879.6" wire width 6 $1\fus_cu_rdmaskn_i$27[5:0]$2379 - attribute \src "libresoc.v:44567.3-44595.6" + attribute \src "libresoc.v:44347.3-44375.6" wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2404 - attribute \src "libresoc.v:44889.3-44917.6" + attribute \src "libresoc.v:44669.3-44697.6" wire width 3 $1\fus_cu_rdmaskn_i$33[2:0]$2423 - attribute \src "libresoc.v:45356.3-45384.6" + attribute \src "libresoc.v:45136.3-45164.6" wire width 5 $1\fus_cu_rdmaskn_i$36[4:0]$2447 - attribute \src "libresoc.v:45794.3-45822.6" + attribute \src "libresoc.v:45574.3-45602.6" wire width 3 $1\fus_cu_rdmaskn_i$39[2:0]$2470 - attribute \src "libresoc.v:47396.3-47424.6" + attribute \src "libresoc.v:47189.3-47217.6" wire width 4 $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47273.3-47301.6" + attribute \src "libresoc.v:47066.3-47094.6" wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46694.3-46722.6" + attribute \src "libresoc.v:46516.3-46544.6" wire width 14 $1\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46564.3-46593.6" wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46564.3-46593.6" wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:47094.3-47122.6" + attribute \src "libresoc.v:46896.3-46924.6" wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47311.3-47339.6" + attribute \src "libresoc.v:47104.3-47132.6" wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46646.3-46674.6" + attribute \src "libresoc.v:46449.3-46477.6" wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46933.3-46961.6" + attribute \src "libresoc.v:46735.3-46763.6" wire $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:47018.3-47046.6" + attribute \src "libresoc.v:46811.3-46839.6" wire $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47188.3-47216.6" + attribute \src "libresoc.v:46981.3-47009.6" wire $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47226.3-47254.6" + attribute \src "libresoc.v:47019.3-47047.6" wire $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:47141.3-47169.6" + attribute \src "libresoc.v:46943.3-46971.6" wire $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:47056.3-47084.6" + attribute \src "libresoc.v:46849.3-46877.6" wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46980.3-47008.6" + attribute \src "libresoc.v:46773.3-46801.6" wire $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:47651.3-47679.6" + attribute \src "libresoc.v:47444.3-47472.6" wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47736.3-47764.6" + attribute \src "libresoc.v:47529.3-47557.6" wire width 14 $1\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47596.3-47625.6" wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47596.3-47625.6" wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47774.3-47802.6" + attribute \src "libresoc.v:47567.3-47595.6" wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47689.3-47717.6" + attribute \src "libresoc.v:47482.3-47510.6" wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47871.3-47899.6" + attribute \src "libresoc.v:47655.3-47683.6" wire $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47842.3-47870.6" + attribute \src "libresoc.v:47626.3-47654.6" wire $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47481.3-47509.6" + attribute \src "libresoc.v:47274.3-47302.6" wire width 14 $1\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47528.3-47556.6" + attribute \src "libresoc.v:47321.3-47349.6" wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47434.3-47462.6" + attribute \src "libresoc.v:47236.3-47264.6" wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:44480.3-44508.6" + attribute \src "libresoc.v:44260.3-44288.6" wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44129.3-44157.6" + attribute \src "libresoc.v:43909.3-43937.6" wire width 14 $1\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:43938.3-43967.6" wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:43938.3-43967.6" wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44306.3-44334.6" + attribute \src "libresoc.v:44086.3-44114.6" wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44509.3-44537.6" + attribute \src "libresoc.v:44289.3-44317.6" wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44100.3-44128.6" + attribute \src "libresoc.v:43880.3-43908.6" wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44248.3-44276.6" + attribute \src "libresoc.v:44028.3-44056.6" wire $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44335.3-44363.6" + attribute \src "libresoc.v:44115.3-44143.6" wire $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44422.3-44450.6" + attribute \src "libresoc.v:44202.3-44230.6" wire $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44451.3-44479.6" + attribute \src "libresoc.v:44231.3-44259.6" wire $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $1\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44393.3-44421.6" + attribute \src "libresoc.v:44173.3-44201.6" wire $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $1\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44364.3-44392.6" + attribute \src "libresoc.v:44144.3-44172.6" wire $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44277.3-44305.6" + attribute \src "libresoc.v:44057.3-44085.6" wire $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43810.3-43838.6" + attribute \src "libresoc.v:43590.3-43618.6" wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48306.3-48334.6" + attribute \src "libresoc.v:48090.3-48118.6" wire width 14 $1\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48119.3-48148.6" wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48119.3-48148.6" wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48483.3-48511.6" + attribute \src "libresoc.v:48267.3-48295.6" wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:43839.3-43867.6" + attribute \src "libresoc.v:43619.3-43647.6" wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48277.3-48305.6" + attribute \src "libresoc.v:48061.3-48089.6" wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48425.3-48453.6" + attribute \src "libresoc.v:48209.3-48237.6" wire $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48512.3-48540.6" + attribute \src "libresoc.v:48296.3-48324.6" wire $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:43752.3-43780.6" + attribute \src "libresoc.v:43532.3-43560.6" wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43781.3-43809.6" + attribute \src "libresoc.v:43561.3-43589.6" wire $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:43723.3-43751.6" + attribute \src "libresoc.v:43503.3-43531.6" wire $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48541.3-48569.6" + attribute \src "libresoc.v:48325.3-48353.6" wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48454.3-48482.6" + attribute \src "libresoc.v:48238.3-48266.6" wire $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44625.3-44653.6" + attribute \src "libresoc.v:44405.3-44433.6" wire width 14 $1\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44434.3-44463.6" wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44434.3-44463.6" wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44831.3-44859.6" + attribute \src "libresoc.v:44611.3-44639.6" wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44596.3-44624.6" + attribute \src "libresoc.v:44376.3-44404.6" wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44773.3-44801.6" + attribute \src "libresoc.v:44553.3-44581.6" wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44802.3-44830.6" + attribute \src "libresoc.v:44582.3-44610.6" wire $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44744.3-44772.6" + attribute \src "libresoc.v:44524.3-44552.6" wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44947.3-44975.6" + attribute \src "libresoc.v:44727.3-44755.6" wire width 14 $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:44756.3-44785.6" wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:44756.3-44785.6" wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:45124.3-45152.6" + attribute \src "libresoc.v:44904.3-44932.6" wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45182.3-45210.6" + attribute \src "libresoc.v:44962.3-44990.6" wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45298.3-45326.6" + attribute \src "libresoc.v:45078.3-45106.6" wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44918.3-44946.6" + attribute \src "libresoc.v:44698.3-44726.6" wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:45095.3-45123.6" + attribute \src "libresoc.v:44875.3-44903.6" wire $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45240.3-45268.6" + attribute \src "libresoc.v:45020.3-45048.6" wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45269.3-45297.6" + attribute \src "libresoc.v:45049.3-45077.6" wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45153.3-45181.6" + attribute \src "libresoc.v:44933.3-44961.6" wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45211.3-45239.6" + attribute \src "libresoc.v:44991.3-45019.6" wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:45066.3-45094.6" + attribute \src "libresoc.v:44846.3-44874.6" wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:43955.3-43983.6" + attribute \src "libresoc.v:43735.3-43763.6" wire width 14 $1\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43984.3-44012.6" + attribute \src "libresoc.v:43764.3-43792.6" wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43926.3-43954.6" + attribute \src "libresoc.v:43706.3-43734.6" wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:44013.3-44041.6" + attribute \src "libresoc.v:43793.3-43821.6" wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:48074.3-48102.6" + attribute \src "libresoc.v:47858.3-47886.6" wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47987.3-48015.6" + attribute \src "libresoc.v:47771.3-47799.6" wire width 14 $1\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:48016.3-48044.6" + attribute \src "libresoc.v:47800.3-47828.6" wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47958.3-47986.6" + attribute \src "libresoc.v:47742.3-47770.6" wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:48103.3-48131.6" + attribute \src "libresoc.v:47887.3-47915.6" wire $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48190.3-48218.6" + attribute \src "libresoc.v:47974.3-48002.6" wire width 8 $1\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48045.3-48073.6" + attribute \src "libresoc.v:47829.3-47857.6" wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48161.3-48189.6" + attribute \src "libresoc.v:47945.3-47973.6" wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48132.3-48160.6" + attribute \src "libresoc.v:47916.3-47944.6" wire width 8 $1\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45649.3-45677.6" + attribute \src "libresoc.v:45429.3-45457.6" wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45620.3-45648.6" + attribute \src "libresoc.v:45400.3-45428.6" wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45414.3-45442.6" + attribute \src "libresoc.v:45194.3-45222.6" wire width 14 $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45223.3-45252.6" wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45223.3-45252.6" wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45736.3-45764.6" + attribute \src "libresoc.v:45516.3-45544.6" wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45385.3-45413.6" + attribute \src "libresoc.v:45165.3-45193.6" wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45562.3-45590.6" + attribute \src "libresoc.v:45342.3-45370.6" wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45591.3-45619.6" + attribute \src "libresoc.v:45371.3-45399.6" wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45707.3-45735.6" + attribute \src "libresoc.v:45487.3-45515.6" wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45678.3-45706.6" + attribute \src "libresoc.v:45458.3-45486.6" wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45473.3-45501.6" + attribute \src "libresoc.v:45253.3-45281.6" wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45851.3-45860.6" - wire width 64 $1\fus_src1_i$42[63:0]$2482 - attribute \src "libresoc.v:45870.3-45879.6" - wire width 64 $1\fus_src1_i$45[63:0]$2488 - attribute \src "libresoc.v:45889.3-45898.6" - wire width 64 $1\fus_src1_i$48[63:0]$2494 - attribute \src "libresoc.v:45908.3-45917.6" - wire width 64 $1\fus_src1_i$51[63:0]$2500 - attribute \src "libresoc.v:45927.3-45936.6" - wire width 64 $1\fus_src1_i$54[63:0]$2506 - attribute \src "libresoc.v:45946.3-45955.6" - wire width 64 $1\fus_src1_i$57[63:0]$2512 - attribute \src "libresoc.v:45965.3-45974.6" - wire width 64 $1\fus_src1_i$60[63:0]$2518 - attribute \src "libresoc.v:45984.3-45993.6" - wire width 64 $1\fus_src1_i$63[63:0]$2524 - attribute \src "libresoc.v:46617.3-46626.6" - wire width 64 $1\fus_src1_i$86[63:0]$2682 - attribute \src "libresoc.v:45832.3-45841.6" + attribute \src "libresoc.v:45821.3-45830.6" + wire width 64 $1\fus_src1_i$62[63:0]$2538 + attribute \src "libresoc.v:45840.3-45849.6" + wire width 64 $1\fus_src1_i$63[63:0]$2544 + attribute \src "libresoc.v:45859.3-45868.6" + wire width 64 $1\fus_src1_i$64[63:0]$2550 + attribute \src "libresoc.v:45878.3-45887.6" + wire width 64 $1\fus_src1_i$67[63:0]$2556 + attribute \src "libresoc.v:45897.3-45906.6" + wire width 64 $1\fus_src1_i$68[63:0]$2562 + attribute \src "libresoc.v:45916.3-45925.6" + wire width 64 $1\fus_src1_i$69[63:0]$2568 + attribute \src "libresoc.v:45935.3-45944.6" + wire width 64 $1\fus_src1_i$70[63:0]$2574 + attribute \src "libresoc.v:45954.3-45963.6" + wire width 64 $1\fus_src1_i$71[63:0]$2580 + attribute \src "libresoc.v:46380.3-46389.6" + wire width 64 $1\fus_src1_i$86[63:0]$2677 + attribute \src "libresoc.v:45802.3-45811.6" wire width 64 $1\fus_src1_i[63:0] - attribute \src "libresoc.v:46022.3-46031.6" - wire width 64 $1\fus_src2_i$64[63:0]$2534 - attribute \src "libresoc.v:46041.3-46050.6" - wire width 64 $1\fus_src2_i$65[63:0]$2540 - attribute \src "libresoc.v:46060.3-46069.6" - wire width 64 $1\fus_src2_i$66[63:0]$2546 - attribute \src "libresoc.v:46079.3-46088.6" - wire width 64 $1\fus_src2_i$67[63:0]$2552 - attribute \src "libresoc.v:46098.3-46107.6" - wire width 64 $1\fus_src2_i$68[63:0]$2558 - attribute \src "libresoc.v:46117.3-46126.6" - wire width 64 $1\fus_src2_i$69[63:0]$2564 - attribute \src "libresoc.v:46136.3-46145.6" - wire width 64 $1\fus_src2_i$70[63:0]$2570 - attribute \src "libresoc.v:46732.3-46741.6" - wire width 64 $1\fus_src2_i$89[63:0]$2702 - attribute \src "libresoc.v:46800.3-46809.6" - wire width 64 $1\fus_src2_i$91[63:0]$2715 - attribute \src "libresoc.v:46003.3-46012.6" + attribute \src "libresoc.v:45631.3-45640.6" + wire width 64 $1\fus_src2_i$42[63:0]$2482 + attribute \src "libresoc.v:45650.3-45659.6" + wire width 64 $1\fus_src2_i$45[63:0]$2488 + attribute \src "libresoc.v:45669.3-45678.6" + wire width 64 $1\fus_src2_i$48[63:0]$2494 + attribute \src "libresoc.v:45688.3-45697.6" + wire width 64 $1\fus_src2_i$51[63:0]$2500 + attribute \src "libresoc.v:45707.3-45716.6" + wire width 64 $1\fus_src2_i$54[63:0]$2506 + attribute \src "libresoc.v:45726.3-45735.6" + wire width 64 $1\fus_src2_i$57[63:0]$2512 + attribute \src "libresoc.v:45745.3-45754.6" + wire width 64 $1\fus_src2_i$60[63:0]$2518 + attribute \src "libresoc.v:46487.3-46496.6" + wire width 64 $1\fus_src2_i$89[63:0]$2701 + attribute \src "libresoc.v:46554.3-46563.6" + wire width 64 $1\fus_src2_i$91[63:0]$2714 + attribute \src "libresoc.v:45612.3-45621.6" wire width 64 $1\fus_src2_i[63:0] - attribute \src "libresoc.v:46174.3-46183.6" - wire width 64 $1\fus_src3_i$71[63:0]$2580 - attribute \src "libresoc.v:46193.3-46202.6" + attribute \src "libresoc.v:45783.3-45792.6" + wire width 64 $1\fus_src3_i$61[63:0]$2528 + attribute \src "libresoc.v:45973.3-45982.6" wire $1\fus_src3_i$72[0:0]$2586 - attribute \src "libresoc.v:46212.3-46221.6" + attribute \src "libresoc.v:45992.3-46001.6" wire $1\fus_src3_i$73[0:0]$2592 - attribute \src "libresoc.v:46250.3-46259.6" + attribute \src "libresoc.v:46030.3-46039.6" wire $1\fus_src3_i$74[0:0]$2602 - attribute \src "libresoc.v:46269.3-46278.6" + attribute \src "libresoc.v:46049.3-46058.6" wire $1\fus_src3_i$75[0:0]$2608 - attribute \src "libresoc.v:46383.3-46392.6" + attribute \src "libresoc.v:46163.3-46172.6" wire width 32 $1\fus_src3_i$79[31:0]$2640 - attribute \src "libresoc.v:46421.3-46430.6" + attribute \src "libresoc.v:46201.3-46210.6" wire width 4 $1\fus_src3_i$83[3:0]$2652 - attribute \src "libresoc.v:46636.3-46645.6" + attribute \src "libresoc.v:46420.3-46429.6" wire width 64 $1\fus_src3_i$87[63:0]$2688 - attribute \src "libresoc.v:46684.3-46693.6" - wire width 64 $1\fus_src3_i$88[63:0]$2695 - attribute \src "libresoc.v:46155.3-46164.6" + attribute \src "libresoc.v:46439.3-46448.6" + wire width 64 $1\fus_src3_i$88[63:0]$2694 + attribute \src "libresoc.v:45764.3-45773.6" wire width 64 $1\fus_src3_i[63:0] - attribute \src "libresoc.v:46288.3-46297.6" + attribute \src "libresoc.v:46068.3-46077.6" wire $1\fus_src4_i$76[0:0]$2614 - attribute \src "libresoc.v:46307.3-46316.6" + attribute \src "libresoc.v:46087.3-46096.6" wire width 2 $1\fus_src4_i$77[1:0]$2620 - attribute \src "libresoc.v:46402.3-46411.6" + attribute \src "libresoc.v:46182.3-46191.6" wire width 4 $1\fus_src4_i$80[3:0]$2646 - attribute \src "libresoc.v:46751.3-46760.6" - wire width 64 $1\fus_src4_i$90[63:0]$2708 - attribute \src "libresoc.v:46231.3-46240.6" + attribute \src "libresoc.v:46506.3-46515.6" + wire width 64 $1\fus_src4_i$90[63:0]$2707 + attribute \src "libresoc.v:46011.3-46020.6" wire $1\fus_src4_i[0:0] - attribute \src "libresoc.v:46364.3-46373.6" + attribute \src "libresoc.v:46144.3-46153.6" wire width 2 $1\fus_src5_i$78[1:0]$2634 - attribute \src "libresoc.v:46467.3-46476.6" + attribute \src "libresoc.v:46251.3-46260.6" wire width 4 $1\fus_src5_i$84[3:0]$2664 - attribute \src "libresoc.v:46345.3-46354.6" + attribute \src "libresoc.v:46125.3-46134.6" wire width 2 $1\fus_src5_i[1:0] - attribute \src "libresoc.v:46577.3-46586.6" - wire width 4 $1\fus_src6_i$85[3:0]$2671 - attribute \src "libresoc.v:46326.3-46335.6" + attribute \src "libresoc.v:46270.3-46279.6" + wire width 4 $1\fus_src6_i$85[3:0]$2670 + attribute \src "libresoc.v:46106.3-46115.6" wire width 2 $1\fus_src6_i[1:0] - attribute \src "libresoc.v:46858.3-46866.6" - wire $1\wr_pick_dly$1010$next[0:0]$2725 - attribute \src "libresoc.v:46867.3-46875.6" - wire $1\wr_pick_dly$1031$next[0:0]$2728 - attribute \src "libresoc.v:46906.3-46914.6" - wire $1\wr_pick_dly$1049$next[0:0]$2732 - attribute \src "libresoc.v:46915.3-46923.6" - wire $1\wr_pick_dly$1071$next[0:0]$2735 - attribute \src "libresoc.v:46924.3-46932.6" - wire $1\wr_pick_dly$1091$next[0:0]$2738 - attribute \src "libresoc.v:46962.3-46970.6" - wire $1\wr_pick_dly$1111$next[0:0]$2742 - attribute \src "libresoc.v:46971.3-46979.6" - wire $1\wr_pick_dly$1130$next[0:0]$2745 - attribute \src "libresoc.v:47009.3-47017.6" - wire $1\wr_pick_dly$1148$next[0:0]$2749 - attribute \src "libresoc.v:47047.3-47055.6" - wire $1\wr_pick_dly$1222$next[0:0]$2753 - attribute \src "libresoc.v:47085.3-47093.6" - wire $1\wr_pick_dly$1250$next[0:0]$2757 - attribute \src "libresoc.v:47123.3-47131.6" - wire $1\wr_pick_dly$1270$next[0:0]$2761 - attribute \src "libresoc.v:47132.3-47140.6" - wire $1\wr_pick_dly$1290$next[0:0]$2764 - attribute \src "libresoc.v:47170.3-47178.6" - wire $1\wr_pick_dly$1310$next[0:0]$2768 - attribute \src "libresoc.v:47179.3-47187.6" - wire $1\wr_pick_dly$1330$next[0:0]$2771 - attribute \src "libresoc.v:47217.3-47225.6" - wire $1\wr_pick_dly$1350$next[0:0]$2775 - attribute \src "libresoc.v:47255.3-47263.6" - wire $1\wr_pick_dly$1397$next[0:0]$2779 - attribute \src "libresoc.v:47264.3-47272.6" - wire $1\wr_pick_dly$1413$next[0:0]$2782 - attribute \src "libresoc.v:47302.3-47310.6" - wire $1\wr_pick_dly$1429$next[0:0]$2786 - attribute \src "libresoc.v:47340.3-47348.6" - wire $1\wr_pick_dly$1463$next[0:0]$2790 - attribute \src "libresoc.v:47378.3-47386.6" - wire $1\wr_pick_dly$1479$next[0:0]$2794 - attribute \src "libresoc.v:47387.3-47395.6" - wire $1\wr_pick_dly$1495$next[0:0]$2797 - attribute \src "libresoc.v:47425.3-47433.6" - wire $1\wr_pick_dly$1511$next[0:0]$2801 - attribute \src "libresoc.v:47463.3-47471.6" - wire $1\wr_pick_dly$1547$next[0:0]$2805 - attribute \src "libresoc.v:47472.3-47480.6" - wire $1\wr_pick_dly$1563$next[0:0]$2808 - attribute \src "libresoc.v:47510.3-47518.6" - wire $1\wr_pick_dly$1579$next[0:0]$2812 - attribute \src "libresoc.v:47519.3-47527.6" - wire $1\wr_pick_dly$1595$next[0:0]$2815 - attribute \src "libresoc.v:47557.3-47565.6" - wire $1\wr_pick_dly$1637$next[0:0]$2819 - attribute \src "libresoc.v:47595.3-47603.6" - wire $1\wr_pick_dly$1656$next[0:0]$2827 - attribute \src "libresoc.v:47633.3-47641.6" - wire $1\wr_pick_dly$1672$next[0:0]$2835 - attribute \src "libresoc.v:47642.3-47650.6" - wire $1\wr_pick_dly$1688$next[0:0]$2838 - attribute \src "libresoc.v:47680.3-47688.6" - wire $1\wr_pick_dly$1704$next[0:0]$2842 - attribute \src "libresoc.v:47718.3-47726.6" - wire $1\wr_pick_dly$1748$next[0:0]$2846 - attribute \src "libresoc.v:47727.3-47735.6" - wire $1\wr_pick_dly$1764$next[0:0]$2849 - attribute \src "libresoc.v:47765.3-47773.6" - wire $1\wr_pick_dly$1788$next[0:0]$2853 - attribute \src "libresoc.v:47803.3-47811.6" - wire $1\wr_pick_dly$1808$next[0:0]$2857 - attribute \src "libresoc.v:46819.3-46827.6" - wire $1\wr_pick_dly$991$next[0:0]$2721 - attribute \src "libresoc.v:46810.3-46818.6" + attribute \src "libresoc.v:46612.3-46620.6" + wire $1\wr_pick_dly$1008$next[0:0]$2724 + attribute \src "libresoc.v:46651.3-46659.6" + wire $1\wr_pick_dly$1029$next[0:0]$2728 + attribute \src "libresoc.v:46660.3-46668.6" + wire $1\wr_pick_dly$1047$next[0:0]$2731 + attribute \src "libresoc.v:46669.3-46677.6" + wire $1\wr_pick_dly$1069$next[0:0]$2734 + attribute \src "libresoc.v:46708.3-46716.6" + wire $1\wr_pick_dly$1089$next[0:0]$2738 + attribute \src "libresoc.v:46717.3-46725.6" + wire $1\wr_pick_dly$1109$next[0:0]$2741 + attribute \src "libresoc.v:46726.3-46734.6" + wire $1\wr_pick_dly$1128$next[0:0]$2744 + attribute \src "libresoc.v:46764.3-46772.6" + wire $1\wr_pick_dly$1146$next[0:0]$2748 + attribute \src "libresoc.v:46802.3-46810.6" + wire $1\wr_pick_dly$1220$next[0:0]$2752 + attribute \src "libresoc.v:46840.3-46848.6" + wire $1\wr_pick_dly$1248$next[0:0]$2756 + attribute \src "libresoc.v:46878.3-46886.6" + wire $1\wr_pick_dly$1268$next[0:0]$2760 + attribute \src "libresoc.v:46887.3-46895.6" + wire $1\wr_pick_dly$1288$next[0:0]$2763 + attribute \src "libresoc.v:46925.3-46933.6" + wire $1\wr_pick_dly$1308$next[0:0]$2767 + attribute \src "libresoc.v:46934.3-46942.6" + wire $1\wr_pick_dly$1328$next[0:0]$2770 + attribute \src "libresoc.v:46972.3-46980.6" + wire $1\wr_pick_dly$1348$next[0:0]$2774 + attribute \src "libresoc.v:47010.3-47018.6" + wire $1\wr_pick_dly$1395$next[0:0]$2778 + attribute \src "libresoc.v:47048.3-47056.6" + wire $1\wr_pick_dly$1411$next[0:0]$2782 + attribute \src "libresoc.v:47057.3-47065.6" + wire $1\wr_pick_dly$1427$next[0:0]$2785 + attribute \src "libresoc.v:47095.3-47103.6" + wire $1\wr_pick_dly$1461$next[0:0]$2789 + attribute \src "libresoc.v:47133.3-47141.6" + wire $1\wr_pick_dly$1477$next[0:0]$2793 + attribute \src "libresoc.v:47142.3-47150.6" + wire $1\wr_pick_dly$1493$next[0:0]$2796 + attribute \src "libresoc.v:47180.3-47188.6" + wire $1\wr_pick_dly$1509$next[0:0]$2800 + attribute \src "libresoc.v:47218.3-47226.6" + wire $1\wr_pick_dly$1545$next[0:0]$2804 + attribute \src "libresoc.v:47227.3-47235.6" + wire $1\wr_pick_dly$1561$next[0:0]$2807 + attribute \src "libresoc.v:47265.3-47273.6" + wire $1\wr_pick_dly$1577$next[0:0]$2811 + attribute \src "libresoc.v:47303.3-47311.6" + wire $1\wr_pick_dly$1593$next[0:0]$2815 + attribute \src "libresoc.v:47312.3-47320.6" + wire $1\wr_pick_dly$1635$next[0:0]$2818 + attribute \src "libresoc.v:47350.3-47358.6" + wire $1\wr_pick_dly$1654$next[0:0]$2822 + attribute \src "libresoc.v:47388.3-47396.6" + wire $1\wr_pick_dly$1670$next[0:0]$2830 + attribute \src "libresoc.v:47397.3-47405.6" + wire $1\wr_pick_dly$1686$next[0:0]$2833 + attribute \src "libresoc.v:47435.3-47443.6" + wire $1\wr_pick_dly$1702$next[0:0]$2841 + attribute \src "libresoc.v:47473.3-47481.6" + wire $1\wr_pick_dly$1746$next[0:0]$2845 + attribute \src "libresoc.v:47511.3-47519.6" + wire $1\wr_pick_dly$1762$next[0:0]$2849 + attribute \src "libresoc.v:47520.3-47528.6" + wire $1\wr_pick_dly$1786$next[0:0]$2852 + attribute \src "libresoc.v:47558.3-47566.6" + wire $1\wr_pick_dly$1806$next[0:0]$2856 + attribute \src "libresoc.v:46603.3-46611.6" + wire $1\wr_pick_dly$989$next[0:0]$2721 + attribute \src "libresoc.v:46594.3-46602.6" wire $1\wr_pick_dly$next[0:0]$2718 - attribute \src "libresoc.v:41724.7-41724.25" + attribute \src "libresoc.v:41528.7-41528.25" wire $1\wr_pick_dly[0:0] - attribute \src "libresoc.v:46587.3-46607.6" - wire $2\core_terminate_o$next[0:0]$2675 - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46390.3-46410.6" + wire $2\core_terminate_o$next[0:0]$2681 + attribute \src "libresoc.v:46280.3-46370.6" wire $2\corebusy_o[0:0] - attribute \src "libresoc.v:46431.3-46457.6" - wire width 2 $2\counter$next[1:0]$2656 - attribute \src "libresoc.v:47566.3-47594.6" - wire $2\fus_cu_issue_i$13[0:0]$2823 - attribute \src "libresoc.v:47900.3-47928.6" + attribute \src "libresoc.v:46220.3-46250.6" + wire width 2 $2\counter$next[1:0]$2659 + attribute \src "libresoc.v:47359.3-47387.6" + wire $2\fus_cu_issue_i$13[0:0]$2826 + attribute \src "libresoc.v:47684.3-47712.6" wire $2\fus_cu_issue_i$16[0:0]$2864 - attribute \src "libresoc.v:48219.3-48247.6" + attribute \src "libresoc.v:48003.3-48031.6" wire $2\fus_cu_issue_i$19[0:0]$2883 - attribute \src "libresoc.v:43868.3-43896.6" + attribute \src "libresoc.v:43648.3-43676.6" wire $2\fus_cu_issue_i$22[0:0]$2361 - attribute \src "libresoc.v:44042.3-44070.6" + attribute \src "libresoc.v:43822.3-43850.6" wire $2\fus_cu_issue_i$25[0:0]$2375 - attribute \src "libresoc.v:44538.3-44566.6" + attribute \src "libresoc.v:44318.3-44346.6" wire $2\fus_cu_issue_i$28[0:0]$2400 - attribute \src "libresoc.v:44860.3-44888.6" + attribute \src "libresoc.v:44640.3-44668.6" wire $2\fus_cu_issue_i$31[0:0]$2419 - attribute \src "libresoc.v:45327.3-45355.6" + attribute \src "libresoc.v:45107.3-45135.6" wire $2\fus_cu_issue_i$34[0:0]$2443 - attribute \src "libresoc.v:45765.3-45793.6" + attribute \src "libresoc.v:45545.3-45573.6" wire $2\fus_cu_issue_i$37[0:0]$2466 - attribute \src "libresoc.v:47349.3-47377.6" + attribute \src "libresoc.v:47151.3-47179.6" wire $2\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47604.3-47632.6" - wire width 6 $2\fus_cu_rdmaskn_i$15[5:0]$2831 - attribute \src "libresoc.v:47929.3-47957.6" + attribute \src "libresoc.v:47406.3-47434.6" + wire width 6 $2\fus_cu_rdmaskn_i$15[5:0]$2837 + attribute \src "libresoc.v:47713.3-47741.6" wire width 3 $2\fus_cu_rdmaskn_i$18[2:0]$2869 - attribute \src "libresoc.v:48248.3-48276.6" + attribute \src "libresoc.v:48032.3-48060.6" wire width 4 $2\fus_cu_rdmaskn_i$21[3:0]$2888 - attribute \src "libresoc.v:43897.3-43925.6" + attribute \src "libresoc.v:43677.3-43705.6" wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2366 - attribute \src "libresoc.v:44071.3-44099.6" + attribute \src "libresoc.v:43851.3-43879.6" wire width 6 $2\fus_cu_rdmaskn_i$27[5:0]$2380 - attribute \src "libresoc.v:44567.3-44595.6" + attribute \src "libresoc.v:44347.3-44375.6" wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2405 - attribute \src "libresoc.v:44889.3-44917.6" + attribute \src "libresoc.v:44669.3-44697.6" wire width 3 $2\fus_cu_rdmaskn_i$33[2:0]$2424 - attribute \src "libresoc.v:45356.3-45384.6" + attribute \src "libresoc.v:45136.3-45164.6" wire width 5 $2\fus_cu_rdmaskn_i$36[4:0]$2448 - attribute \src "libresoc.v:45794.3-45822.6" + attribute \src "libresoc.v:45574.3-45602.6" wire width 3 $2\fus_cu_rdmaskn_i$39[2:0]$2471 - attribute \src "libresoc.v:47396.3-47424.6" + attribute \src "libresoc.v:47189.3-47217.6" wire width 4 $2\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47273.3-47301.6" + attribute \src "libresoc.v:47066.3-47094.6" wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46694.3-46722.6" + attribute \src "libresoc.v:46516.3-46544.6" wire width 14 $2\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46564.3-46593.6" wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46564.3-46593.6" wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:47094.3-47122.6" + attribute \src "libresoc.v:46896.3-46924.6" wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47311.3-47339.6" + attribute \src "libresoc.v:47104.3-47132.6" wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46646.3-46674.6" + attribute \src "libresoc.v:46449.3-46477.6" wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46933.3-46961.6" + attribute \src "libresoc.v:46735.3-46763.6" wire $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:47018.3-47046.6" + attribute \src "libresoc.v:46811.3-46839.6" wire $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47188.3-47216.6" + attribute \src "libresoc.v:46981.3-47009.6" wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47226.3-47254.6" + attribute \src "libresoc.v:47019.3-47047.6" wire $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:47141.3-47169.6" + attribute \src "libresoc.v:46943.3-46971.6" wire $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:47056.3-47084.6" + attribute \src "libresoc.v:46849.3-46877.6" wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46980.3-47008.6" + attribute \src "libresoc.v:46773.3-46801.6" wire $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:47651.3-47679.6" + attribute \src "libresoc.v:47444.3-47472.6" wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47736.3-47764.6" + attribute \src "libresoc.v:47529.3-47557.6" wire width 14 $2\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47596.3-47625.6" wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47596.3-47625.6" wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47774.3-47802.6" + attribute \src "libresoc.v:47567.3-47595.6" wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47689.3-47717.6" + attribute \src "libresoc.v:47482.3-47510.6" wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47871.3-47899.6" + attribute \src "libresoc.v:47655.3-47683.6" wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47842.3-47870.6" + attribute \src "libresoc.v:47626.3-47654.6" wire $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47481.3-47509.6" + attribute \src "libresoc.v:47274.3-47302.6" wire width 14 $2\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47528.3-47556.6" + attribute \src "libresoc.v:47321.3-47349.6" wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47434.3-47462.6" + attribute \src "libresoc.v:47236.3-47264.6" wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:44480.3-44508.6" + attribute \src "libresoc.v:44260.3-44288.6" wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44129.3-44157.6" + attribute \src "libresoc.v:43909.3-43937.6" wire width 14 $2\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:43938.3-43967.6" wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:43938.3-43967.6" wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44306.3-44334.6" + attribute \src "libresoc.v:44086.3-44114.6" wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44509.3-44537.6" + attribute \src "libresoc.v:44289.3-44317.6" wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44100.3-44128.6" + attribute \src "libresoc.v:43880.3-43908.6" wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44248.3-44276.6" + attribute \src "libresoc.v:44028.3-44056.6" wire $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44335.3-44363.6" + attribute \src "libresoc.v:44115.3-44143.6" wire $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44422.3-44450.6" + attribute \src "libresoc.v:44202.3-44230.6" wire $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44451.3-44479.6" + attribute \src "libresoc.v:44231.3-44259.6" wire $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $2\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44393.3-44421.6" + attribute \src "libresoc.v:44173.3-44201.6" wire $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $2\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44364.3-44392.6" + attribute \src "libresoc.v:44144.3-44172.6" wire $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44277.3-44305.6" + attribute \src "libresoc.v:44057.3-44085.6" wire $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43810.3-43838.6" + attribute \src "libresoc.v:43590.3-43618.6" wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48306.3-48334.6" + attribute \src "libresoc.v:48090.3-48118.6" wire width 14 $2\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48119.3-48148.6" wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48119.3-48148.6" wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48483.3-48511.6" + attribute \src "libresoc.v:48267.3-48295.6" wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:43839.3-43867.6" + attribute \src "libresoc.v:43619.3-43647.6" wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48277.3-48305.6" + attribute \src "libresoc.v:48061.3-48089.6" wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48425.3-48453.6" + attribute \src "libresoc.v:48209.3-48237.6" wire $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48512.3-48540.6" + attribute \src "libresoc.v:48296.3-48324.6" wire $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:43752.3-43780.6" + attribute \src "libresoc.v:43532.3-43560.6" wire $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43781.3-43809.6" + attribute \src "libresoc.v:43561.3-43589.6" wire $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $2\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:43723.3-43751.6" + attribute \src "libresoc.v:43503.3-43531.6" wire $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $2\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48541.3-48569.6" + attribute \src "libresoc.v:48325.3-48353.6" wire $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48454.3-48482.6" + attribute \src "libresoc.v:48238.3-48266.6" wire $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44625.3-44653.6" + attribute \src "libresoc.v:44405.3-44433.6" wire width 14 $2\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44434.3-44463.6" wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44434.3-44463.6" wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44831.3-44859.6" + attribute \src "libresoc.v:44611.3-44639.6" wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44596.3-44624.6" + attribute \src "libresoc.v:44376.3-44404.6" wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44773.3-44801.6" + attribute \src "libresoc.v:44553.3-44581.6" wire $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44802.3-44830.6" + attribute \src "libresoc.v:44582.3-44610.6" wire $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $2\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $2\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44744.3-44772.6" + attribute \src "libresoc.v:44524.3-44552.6" wire $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44947.3-44975.6" + attribute \src "libresoc.v:44727.3-44755.6" wire width 14 $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:44756.3-44785.6" wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:44756.3-44785.6" wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:45124.3-45152.6" + attribute \src "libresoc.v:44904.3-44932.6" wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45182.3-45210.6" + attribute \src "libresoc.v:44962.3-44990.6" wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45298.3-45326.6" + attribute \src "libresoc.v:45078.3-45106.6" wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44918.3-44946.6" + attribute \src "libresoc.v:44698.3-44726.6" wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:45095.3-45123.6" + attribute \src "libresoc.v:44875.3-44903.6" wire $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45240.3-45268.6" + attribute \src "libresoc.v:45020.3-45048.6" wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45269.3-45297.6" + attribute \src "libresoc.v:45049.3-45077.6" wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45153.3-45181.6" + attribute \src "libresoc.v:44933.3-44961.6" wire $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45211.3-45239.6" + attribute \src "libresoc.v:44991.3-45019.6" wire $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:45066.3-45094.6" + attribute \src "libresoc.v:44846.3-44874.6" wire $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:43955.3-43983.6" + attribute \src "libresoc.v:43735.3-43763.6" wire width 14 $2\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43984.3-44012.6" + attribute \src "libresoc.v:43764.3-43792.6" wire width 32 $2\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43926.3-43954.6" + attribute \src "libresoc.v:43706.3-43734.6" wire width 7 $2\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:44013.3-44041.6" + attribute \src "libresoc.v:43793.3-43821.6" wire $2\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:48074.3-48102.6" + attribute \src "libresoc.v:47858.3-47886.6" wire width 64 $2\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47987.3-48015.6" + attribute \src "libresoc.v:47771.3-47799.6" wire width 14 $2\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:48016.3-48044.6" + attribute \src "libresoc.v:47800.3-47828.6" wire width 32 $2\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47958.3-47986.6" + attribute \src "libresoc.v:47742.3-47770.6" wire width 7 $2\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:48103.3-48131.6" + attribute \src "libresoc.v:47887.3-47915.6" wire $2\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48190.3-48218.6" + attribute \src "libresoc.v:47974.3-48002.6" wire width 8 $2\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48045.3-48073.6" + attribute \src "libresoc.v:47829.3-47857.6" wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48161.3-48189.6" + attribute \src "libresoc.v:47945.3-47973.6" wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48132.3-48160.6" + attribute \src "libresoc.v:47916.3-47944.6" wire width 8 $2\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45649.3-45677.6" + attribute \src "libresoc.v:45429.3-45457.6" wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45620.3-45648.6" + attribute \src "libresoc.v:45400.3-45428.6" wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45414.3-45442.6" + attribute \src "libresoc.v:45194.3-45222.6" wire width 14 $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45223.3-45252.6" wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45223.3-45252.6" wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45736.3-45764.6" + attribute \src "libresoc.v:45516.3-45544.6" wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45385.3-45413.6" + attribute \src "libresoc.v:45165.3-45193.6" wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45562.3-45590.6" + attribute \src "libresoc.v:45342.3-45370.6" wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45591.3-45619.6" + attribute \src "libresoc.v:45371.3-45399.6" wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45707.3-45735.6" + attribute \src "libresoc.v:45487.3-45515.6" wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45678.3-45706.6" + attribute \src "libresoc.v:45458.3-45486.6" wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45473.3-45501.6" + attribute \src "libresoc.v:45253.3-45281.6" wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:46587.3-46607.6" - wire $3\core_terminate_o$next[0:0]$2676 - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46390.3-46410.6" + wire $3\core_terminate_o$next[0:0]$2682 + attribute \src "libresoc.v:46280.3-46370.6" wire $3\corebusy_o[0:0] - attribute \src "libresoc.v:46431.3-46457.6" - wire width 2 $3\counter$next[1:0]$2657 - attribute \src "libresoc.v:47566.3-47594.6" - wire $3\fus_cu_issue_i$13[0:0]$2824 - attribute \src "libresoc.v:47900.3-47928.6" + attribute \src "libresoc.v:46220.3-46250.6" + wire width 2 $3\counter$next[1:0]$2660 + attribute \src "libresoc.v:47359.3-47387.6" + wire $3\fus_cu_issue_i$13[0:0]$2827 + attribute \src "libresoc.v:47684.3-47712.6" wire $3\fus_cu_issue_i$16[0:0]$2865 - attribute \src "libresoc.v:48219.3-48247.6" + attribute \src "libresoc.v:48003.3-48031.6" wire $3\fus_cu_issue_i$19[0:0]$2884 - attribute \src "libresoc.v:43868.3-43896.6" + attribute \src "libresoc.v:43648.3-43676.6" wire $3\fus_cu_issue_i$22[0:0]$2362 - attribute \src "libresoc.v:44042.3-44070.6" + attribute \src "libresoc.v:43822.3-43850.6" wire $3\fus_cu_issue_i$25[0:0]$2376 - attribute \src "libresoc.v:44538.3-44566.6" + attribute \src "libresoc.v:44318.3-44346.6" wire $3\fus_cu_issue_i$28[0:0]$2401 - attribute \src "libresoc.v:44860.3-44888.6" + attribute \src "libresoc.v:44640.3-44668.6" wire $3\fus_cu_issue_i$31[0:0]$2420 - attribute \src "libresoc.v:45327.3-45355.6" + attribute \src "libresoc.v:45107.3-45135.6" wire $3\fus_cu_issue_i$34[0:0]$2444 - attribute \src "libresoc.v:45765.3-45793.6" + attribute \src "libresoc.v:45545.3-45573.6" wire $3\fus_cu_issue_i$37[0:0]$2467 - attribute \src "libresoc.v:47349.3-47377.6" + attribute \src "libresoc.v:47151.3-47179.6" wire $3\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47604.3-47632.6" - wire width 6 $3\fus_cu_rdmaskn_i$15[5:0]$2832 - attribute \src "libresoc.v:47929.3-47957.6" + attribute \src "libresoc.v:47406.3-47434.6" + wire width 6 $3\fus_cu_rdmaskn_i$15[5:0]$2838 + attribute \src "libresoc.v:47713.3-47741.6" wire width 3 $3\fus_cu_rdmaskn_i$18[2:0]$2870 - attribute \src "libresoc.v:48248.3-48276.6" + attribute \src "libresoc.v:48032.3-48060.6" wire width 4 $3\fus_cu_rdmaskn_i$21[3:0]$2889 - attribute \src "libresoc.v:43897.3-43925.6" + attribute \src "libresoc.v:43677.3-43705.6" wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2367 - attribute \src "libresoc.v:44071.3-44099.6" + attribute \src "libresoc.v:43851.3-43879.6" wire width 6 $3\fus_cu_rdmaskn_i$27[5:0]$2381 - attribute \src "libresoc.v:44567.3-44595.6" + attribute \src "libresoc.v:44347.3-44375.6" wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2406 - attribute \src "libresoc.v:44889.3-44917.6" + attribute \src "libresoc.v:44669.3-44697.6" wire width 3 $3\fus_cu_rdmaskn_i$33[2:0]$2425 - attribute \src "libresoc.v:45356.3-45384.6" + attribute \src "libresoc.v:45136.3-45164.6" wire width 5 $3\fus_cu_rdmaskn_i$36[4:0]$2449 - attribute \src "libresoc.v:45794.3-45822.6" + attribute \src "libresoc.v:45574.3-45602.6" wire width 3 $3\fus_cu_rdmaskn_i$39[2:0]$2472 - attribute \src "libresoc.v:47396.3-47424.6" + attribute \src "libresoc.v:47189.3-47217.6" wire width 4 $3\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47273.3-47301.6" + attribute \src "libresoc.v:47066.3-47094.6" wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46694.3-46722.6" + attribute \src "libresoc.v:46516.3-46544.6" wire width 14 $3\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46564.3-46593.6" wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46564.3-46593.6" wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:47094.3-47122.6" + attribute \src "libresoc.v:46896.3-46924.6" wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47311.3-47339.6" + attribute \src "libresoc.v:47104.3-47132.6" wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46646.3-46674.6" + attribute \src "libresoc.v:46449.3-46477.6" wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46933.3-46961.6" + attribute \src "libresoc.v:46735.3-46763.6" wire $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:47018.3-47046.6" + attribute \src "libresoc.v:46811.3-46839.6" wire $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47188.3-47216.6" + attribute \src "libresoc.v:46981.3-47009.6" wire $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47226.3-47254.6" + attribute \src "libresoc.v:47019.3-47047.6" wire $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $3\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46678.3-46707.6" wire $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:47141.3-47169.6" + attribute \src "libresoc.v:46943.3-46971.6" wire $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $3\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46621.3-46650.6" wire $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:47056.3-47084.6" + attribute \src "libresoc.v:46849.3-46877.6" wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46980.3-47008.6" + attribute \src "libresoc.v:46773.3-46801.6" wire $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:47651.3-47679.6" + attribute \src "libresoc.v:47444.3-47472.6" wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47736.3-47764.6" + attribute \src "libresoc.v:47529.3-47557.6" wire width 14 $3\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47596.3-47625.6" wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47596.3-47625.6" wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47774.3-47802.6" + attribute \src "libresoc.v:47567.3-47595.6" wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47689.3-47717.6" + attribute \src "libresoc.v:47482.3-47510.6" wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47871.3-47899.6" + attribute \src "libresoc.v:47655.3-47683.6" wire $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47842.3-47870.6" + attribute \src "libresoc.v:47626.3-47654.6" wire $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47481.3-47509.6" + attribute \src "libresoc.v:47274.3-47302.6" wire width 14 $3\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47528.3-47556.6" + attribute \src "libresoc.v:47321.3-47349.6" wire width 32 $3\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47434.3-47462.6" + attribute \src "libresoc.v:47236.3-47264.6" wire width 7 $3\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:44480.3-44508.6" + attribute \src "libresoc.v:44260.3-44288.6" wire width 4 $3\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44129.3-44157.6" + attribute \src "libresoc.v:43909.3-43937.6" wire width 14 $3\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:43938.3-43967.6" wire width 64 $3\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:43938.3-43967.6" wire $3\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44306.3-44334.6" + attribute \src "libresoc.v:44086.3-44114.6" wire width 2 $3\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44509.3-44537.6" + attribute \src "libresoc.v:44289.3-44317.6" wire width 32 $3\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44100.3-44128.6" + attribute \src "libresoc.v:43880.3-43908.6" wire width 7 $3\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44248.3-44276.6" + attribute \src "libresoc.v:44028.3-44056.6" wire $3\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44335.3-44363.6" + attribute \src "libresoc.v:44115.3-44143.6" wire $3\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44422.3-44450.6" + attribute \src "libresoc.v:44202.3-44230.6" wire $3\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44451.3-44479.6" + attribute \src "libresoc.v:44231.3-44259.6" wire $3\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $3\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:43998.3-44027.6" wire $3\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44393.3-44421.6" + attribute \src "libresoc.v:44173.3-44201.6" wire $3\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $3\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:43968.3-43997.6" wire $3\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44364.3-44392.6" + attribute \src "libresoc.v:44144.3-44172.6" wire $3\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44277.3-44305.6" + attribute \src "libresoc.v:44057.3-44085.6" wire $3\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43810.3-43838.6" + attribute \src "libresoc.v:43590.3-43618.6" wire width 4 $3\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48306.3-48334.6" + attribute \src "libresoc.v:48090.3-48118.6" wire width 14 $3\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48119.3-48148.6" wire width 64 $3\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48119.3-48148.6" wire $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48483.3-48511.6" + attribute \src "libresoc.v:48267.3-48295.6" wire width 2 $3\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:43839.3-43867.6" + attribute \src "libresoc.v:43619.3-43647.6" wire width 32 $3\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48277.3-48305.6" + attribute \src "libresoc.v:48061.3-48089.6" wire width 7 $3\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48425.3-48453.6" + attribute \src "libresoc.v:48209.3-48237.6" wire $3\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48512.3-48540.6" + attribute \src "libresoc.v:48296.3-48324.6" wire $3\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:43752.3-43780.6" + attribute \src "libresoc.v:43532.3-43560.6" wire $3\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43781.3-43809.6" + attribute \src "libresoc.v:43561.3-43589.6" wire $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $3\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48179.3-48208.6" wire $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:43723.3-43751.6" + attribute \src "libresoc.v:43503.3-43531.6" wire $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $3\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48149.3-48178.6" wire $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48541.3-48569.6" + attribute \src "libresoc.v:48325.3-48353.6" wire $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48454.3-48482.6" + attribute \src "libresoc.v:48238.3-48266.6" wire $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44625.3-44653.6" + attribute \src "libresoc.v:44405.3-44433.6" wire width 14 $3\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44434.3-44463.6" wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44434.3-44463.6" wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44831.3-44859.6" + attribute \src "libresoc.v:44611.3-44639.6" wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44596.3-44624.6" + attribute \src "libresoc.v:44376.3-44404.6" wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44773.3-44801.6" + attribute \src "libresoc.v:44553.3-44581.6" wire $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44802.3-44830.6" + attribute \src "libresoc.v:44582.3-44610.6" wire $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $3\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44494.3-44523.6" wire $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $3\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44464.3-44493.6" wire $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44744.3-44772.6" + attribute \src "libresoc.v:44524.3-44552.6" wire $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44947.3-44975.6" + attribute \src "libresoc.v:44727.3-44755.6" wire width 14 $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:44756.3-44785.6" wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:44756.3-44785.6" wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:45124.3-45152.6" + attribute \src "libresoc.v:44904.3-44932.6" wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45182.3-45210.6" + attribute \src "libresoc.v:44962.3-44990.6" wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45298.3-45326.6" + attribute \src "libresoc.v:45078.3-45106.6" wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44918.3-44946.6" + attribute \src "libresoc.v:44698.3-44726.6" wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:45095.3-45123.6" + attribute \src "libresoc.v:44875.3-44903.6" wire $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45240.3-45268.6" + attribute \src "libresoc.v:45020.3-45048.6" wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45269.3-45297.6" + attribute \src "libresoc.v:45049.3-45077.6" wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:44816.3-44845.6" wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45153.3-45181.6" + attribute \src "libresoc.v:44933.3-44961.6" wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45211.3-45239.6" + attribute \src "libresoc.v:44991.3-45019.6" wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:44786.3-44815.6" wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:45066.3-45094.6" + attribute \src "libresoc.v:44846.3-44874.6" wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:43955.3-43983.6" + attribute \src "libresoc.v:43735.3-43763.6" wire width 14 $3\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43984.3-44012.6" + attribute \src "libresoc.v:43764.3-43792.6" wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43926.3-43954.6" + attribute \src "libresoc.v:43706.3-43734.6" wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:44013.3-44041.6" + attribute \src "libresoc.v:43793.3-43821.6" wire $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:48074.3-48102.6" + attribute \src "libresoc.v:47858.3-47886.6" wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47987.3-48015.6" + attribute \src "libresoc.v:47771.3-47799.6" wire width 14 $3\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:48016.3-48044.6" + attribute \src "libresoc.v:47800.3-47828.6" wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47958.3-47986.6" + attribute \src "libresoc.v:47742.3-47770.6" wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:48103.3-48131.6" + attribute \src "libresoc.v:47887.3-47915.6" wire $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48190.3-48218.6" + attribute \src "libresoc.v:47974.3-48002.6" wire width 8 $3\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48045.3-48073.6" + attribute \src "libresoc.v:47829.3-47857.6" wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48161.3-48189.6" + attribute \src "libresoc.v:47945.3-47973.6" wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48132.3-48160.6" + attribute \src "libresoc.v:47916.3-47944.6" wire width 8 $3\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45649.3-45677.6" + attribute \src "libresoc.v:45429.3-45457.6" wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45620.3-45648.6" + attribute \src "libresoc.v:45400.3-45428.6" wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45414.3-45442.6" + attribute \src "libresoc.v:45194.3-45222.6" wire width 14 $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45223.3-45252.6" wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45223.3-45252.6" wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45736.3-45764.6" + attribute \src "libresoc.v:45516.3-45544.6" wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45385.3-45413.6" + attribute \src "libresoc.v:45165.3-45193.6" wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45562.3-45590.6" + attribute \src "libresoc.v:45342.3-45370.6" wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45591.3-45619.6" + attribute \src "libresoc.v:45371.3-45399.6" wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45707.3-45735.6" + attribute \src "libresoc.v:45487.3-45515.6" wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45312.3-45341.6" wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45282.3-45311.6" wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45678.3-45706.6" + attribute \src "libresoc.v:45458.3-45486.6" wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45473.3-45501.6" + attribute \src "libresoc.v:45253.3-45281.6" wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $4\corebusy_o[0:0] - attribute \src "libresoc.v:46431.3-46457.6" - wire width 2 $4\counter$next[1:0]$2658 - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46220.3-46250.6" + wire width 2 $4\counter$next[1:0]$2661 + attribute \src "libresoc.v:46280.3-46370.6" wire $5\corebusy_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $6\corebusy_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $7\corebusy_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $8\corebusy_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46280.3-46370.6" wire $9\corebusy_o[0:0] - attribute \src "libresoc.v:42103.20-42103.122" - wire $and$libresoc.v:42103$1506_Y - attribute \src "libresoc.v:42105.20-42105.122" - wire $and$libresoc.v:42105$1508_Y - attribute \src "libresoc.v:42106.20-42106.126" - wire $and$libresoc.v:42106$1509_Y - attribute \src "libresoc.v:42108.20-42108.110" - wire $and$libresoc.v:42108$1511_Y - attribute \src "libresoc.v:42109.20-42109.123" - wire $and$libresoc.v:42109$1512_Y - attribute \src "libresoc.v:42111.20-42111.122" - wire $and$libresoc.v:42111$1514_Y - attribute \src "libresoc.v:42112.20-42112.126" - wire $and$libresoc.v:42112$1515_Y - attribute \src "libresoc.v:42114.20-42114.110" - wire $and$libresoc.v:42114$1517_Y + attribute \src "libresoc.v:41908.20-41908.122" + wire $and$libresoc.v:41908$1507_Y + attribute \src "libresoc.v:41909.20-41909.126" + wire $and$libresoc.v:41909$1508_Y + attribute \src "libresoc.v:41911.20-41911.110" + wire $and$libresoc.v:41911$1510_Y + attribute \src "libresoc.v:41912.20-41912.123" + wire $and$libresoc.v:41912$1511_Y + attribute \src "libresoc.v:41914.20-41914.122" + wire $and$libresoc.v:41914$1513_Y + attribute \src "libresoc.v:41915.20-41915.126" + wire $and$libresoc.v:41915$1514_Y + attribute \src "libresoc.v:41917.20-41917.110" + wire $and$libresoc.v:41917$1516_Y + attribute \src "libresoc.v:41918.20-41918.123" + wire $and$libresoc.v:41918$1517_Y + attribute \src "libresoc.v:41920.20-41920.123" + wire $and$libresoc.v:41920$1519_Y + attribute \src "libresoc.v:41921.20-41921.126" + wire $and$libresoc.v:41921$1520_Y + attribute \src "libresoc.v:41923.20-41923.110" + wire $and$libresoc.v:41923$1522_Y + attribute \src "libresoc.v:41924.20-41924.123" + wire $and$libresoc.v:41924$1523_Y + attribute \src "libresoc.v:41926.20-41926.123" + wire $and$libresoc.v:41926$1525_Y + attribute \src "libresoc.v:41927.20-41927.126" + wire $and$libresoc.v:41927$1526_Y + attribute \src "libresoc.v:41929.20-41929.110" + wire $and$libresoc.v:41929$1528_Y + attribute \src "libresoc.v:41930.20-41930.123" + wire $and$libresoc.v:41930$1529_Y + attribute \src "libresoc.v:41932.20-41932.123" + wire $and$libresoc.v:41932$1531_Y + attribute \src "libresoc.v:41933.20-41933.126" + wire $and$libresoc.v:41933$1532_Y + attribute \src "libresoc.v:41935.20-41935.110" + wire $and$libresoc.v:41935$1534_Y + attribute \src "libresoc.v:41936.20-41936.123" + wire $and$libresoc.v:41936$1535_Y + attribute \src "libresoc.v:41938.20-41938.123" + wire $and$libresoc.v:41938$1537_Y + attribute \src "libresoc.v:41939.20-41939.126" + wire $and$libresoc.v:41939$1538_Y + attribute \src "libresoc.v:41941.20-41941.110" + wire $and$libresoc.v:41941$1540_Y + attribute \src "libresoc.v:41942.20-41942.123" + wire $and$libresoc.v:41942$1541_Y + attribute \src "libresoc.v:41944.20-41944.113" + wire $and$libresoc.v:41944$1543_Y + attribute \src "libresoc.v:41945.20-41945.126" + wire $and$libresoc.v:41945$1544_Y + attribute \src "libresoc.v:41947.20-41947.110" + wire $and$libresoc.v:41947$1546_Y + attribute \src "libresoc.v:41948.20-41948.123" + wire $and$libresoc.v:41948$1547_Y + attribute \src "libresoc.v:41950.20-41950.114" + wire $and$libresoc.v:41950$1549_Y + attribute \src "libresoc.v:41951.20-41951.126" + wire $and$libresoc.v:41951$1550_Y + attribute \src "libresoc.v:41953.20-41953.110" + wire $and$libresoc.v:41953$1552_Y + attribute \src "libresoc.v:41954.20-41954.123" + wire $and$libresoc.v:41954$1553_Y + attribute \src "libresoc.v:41983.20-41983.123" + wire $and$libresoc.v:41983$1582_Y + attribute \src "libresoc.v:41984.20-41984.128" + wire $and$libresoc.v:41984$1583_Y + attribute \src "libresoc.v:41985.20-41985.133" + wire $and$libresoc.v:41985$1584_Y + attribute \src "libresoc.v:41987.20-41987.110" + wire $and$libresoc.v:41987$1586_Y + attribute \src "libresoc.v:41988.20-41988.128" + wire $and$libresoc.v:41988$1587_Y + attribute \src "libresoc.v:41990.20-41990.116" + wire $and$libresoc.v:41990$1589_Y + attribute \src "libresoc.v:41991.20-41991.123" + wire $and$libresoc.v:41991$1590_Y + attribute \src "libresoc.v:41992.20-41992.128" + wire $and$libresoc.v:41992$1591_Y + attribute \src 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"libresoc.v:42330.19-42330.131" + wire $and$libresoc.v:42330$1934_Y + attribute \src "libresoc.v:42332.19-42332.127" + wire $and$libresoc.v:42332$1936_Y + attribute \src "libresoc.v:42333.19-42333.114" + wire $and$libresoc.v:42333$1937_Y + attribute \src "libresoc.v:42335.19-42335.102" + wire $and$libresoc.v:42335$1939_Y + attribute \src "libresoc.v:42336.19-42336.131" + wire $and$libresoc.v:42336$1940_Y + attribute \src "libresoc.v:42338.19-42338.127" + wire $and$libresoc.v:42338$1942_Y + attribute \src "libresoc.v:42339.19-42339.114" + wire $and$libresoc.v:42339$1943_Y + attribute \src "libresoc.v:42341.19-42341.102" + wire $and$libresoc.v:42341$1945_Y + attribute \src "libresoc.v:42342.19-42342.131" + wire $and$libresoc.v:42342$1946_Y + attribute \src "libresoc.v:42344.19-42344.127" + wire $and$libresoc.v:42344$1948_Y + attribute \src "libresoc.v:42345.19-42345.114" + wire $and$libresoc.v:42345$1949_Y + attribute \src "libresoc.v:42347.19-42347.102" + wire $and$libresoc.v:42347$1951_Y + attribute \src "libresoc.v:42348.19-42348.131" + wire $and$libresoc.v:42348$1952_Y + attribute \src "libresoc.v:42350.19-42350.127" + wire $and$libresoc.v:42350$1954_Y + attribute \src "libresoc.v:42351.19-42351.114" + wire $and$libresoc.v:42351$1955_Y + attribute \src "libresoc.v:42353.19-42353.102" + wire $and$libresoc.v:42353$1957_Y + attribute \src "libresoc.v:42354.19-42354.131" + wire $and$libresoc.v:42354$1958_Y + attribute \src "libresoc.v:42356.19-42356.127" + wire $and$libresoc.v:42356$1960_Y + attribute \src "libresoc.v:42357.19-42357.114" + wire $and$libresoc.v:42357$1961_Y + attribute \src "libresoc.v:42359.19-42359.102" + wire $and$libresoc.v:42359$1963_Y + attribute \src "libresoc.v:42360.19-42360.131" + wire $and$libresoc.v:42360$1964_Y + attribute \src "libresoc.v:42362.19-42362.127" + wire $and$libresoc.v:42362$1966_Y + attribute \src "libresoc.v:42363.19-42363.114" + wire $and$libresoc.v:42363$1967_Y + attribute \src "libresoc.v:42365.19-42365.102" + wire $and$libresoc.v:42365$1969_Y + attribute \src "libresoc.v:42366.19-42366.131" + wire $and$libresoc.v:42366$1970_Y + attribute \src "libresoc.v:42368.19-42368.127" + wire $and$libresoc.v:42368$1972_Y + attribute \src "libresoc.v:42369.19-42369.114" + wire $and$libresoc.v:42369$1973_Y + attribute \src "libresoc.v:42371.19-42371.102" + wire $and$libresoc.v:42371$1975_Y + attribute \src "libresoc.v:42372.19-42372.131" + wire $and$libresoc.v:42372$1976_Y + attribute \src "libresoc.v:42374.19-42374.122" + wire $and$libresoc.v:42374$1978_Y + attribute \src "libresoc.v:42375.19-42375.114" + wire $and$libresoc.v:42375$1979_Y + attribute \src "libresoc.v:42377.19-42377.102" + wire $and$libresoc.v:42377$1981_Y + attribute \src "libresoc.v:42378.19-42378.132" + wire $and$libresoc.v:42378$1982_Y + attribute \src "libresoc.v:42380.19-42380.127" + wire $and$libresoc.v:42380$1984_Y + attribute \src "libresoc.v:42381.19-42381.114" + wire $and$libresoc.v:42381$1985_Y + attribute \src "libresoc.v:42383.19-42383.102" + wire $and$libresoc.v:42383$1987_Y + attribute \src "libresoc.v:42384.19-42384.132" + wire $and$libresoc.v:42384$1988_Y + attribute \src "libresoc.v:42386.19-42386.127" + wire $and$libresoc.v:42386$1990_Y + attribute \src "libresoc.v:42387.19-42387.114" + wire $and$libresoc.v:42387$1991_Y + attribute \src "libresoc.v:42389.19-42389.102" + wire $and$libresoc.v:42389$1993_Y + attribute \src "libresoc.v:42390.19-42390.132" + wire $and$libresoc.v:42390$1994_Y + attribute \src "libresoc.v:42392.19-42392.127" + wire $and$libresoc.v:42392$1996_Y + attribute \src "libresoc.v:42393.19-42393.114" + wire $and$libresoc.v:42393$1997_Y + attribute \src "libresoc.v:42395.19-42395.102" + wire $and$libresoc.v:42395$1999_Y + attribute \src "libresoc.v:42396.19-42396.132" + wire $and$libresoc.v:42396$2000_Y + attribute \src "libresoc.v:42398.19-42398.127" + wire $and$libresoc.v:42398$2002_Y + attribute \src "libresoc.v:42399.19-42399.114" + wire $and$libresoc.v:42399$2003_Y + attribute \src "libresoc.v:42401.19-42401.102" + wire $and$libresoc.v:42401$2005_Y + attribute \src "libresoc.v:42402.19-42402.132" + wire $and$libresoc.v:42402$2006_Y + attribute \src "libresoc.v:42404.19-42404.127" + wire $and$libresoc.v:42404$2008_Y + attribute \src "libresoc.v:42405.19-42405.114" + wire $and$libresoc.v:42405$2009_Y + attribute \src "libresoc.v:42407.19-42407.102" + wire $and$libresoc.v:42407$2011_Y + attribute \src "libresoc.v:42408.19-42408.132" + wire $and$libresoc.v:42408$2012_Y + attribute \src "libresoc.v:42410.19-42410.127" + wire $and$libresoc.v:42410$2014_Y + attribute \src "libresoc.v:42411.19-42411.114" + wire $and$libresoc.v:42411$2015_Y + attribute \src "libresoc.v:42413.19-42413.102" + wire $and$libresoc.v:42413$2017_Y + attribute \src "libresoc.v:42414.19-42414.132" + wire $and$libresoc.v:42414$2018_Y + attribute \src "libresoc.v:42416.19-42416.127" + wire $and$libresoc.v:42416$2020_Y + attribute \src "libresoc.v:42417.19-42417.114" + wire $and$libresoc.v:42417$2021_Y + attribute \src "libresoc.v:42419.19-42419.102" + wire $and$libresoc.v:42419$2023_Y + attribute \src "libresoc.v:42420.19-42420.132" + wire $and$libresoc.v:42420$2024_Y + attribute \src "libresoc.v:42422.19-42422.127" + wire $and$libresoc.v:42422$2026_Y + attribute \src "libresoc.v:42423.19-42423.114" + wire $and$libresoc.v:42423$2027_Y + attribute \src "libresoc.v:42425.19-42425.102" + wire $and$libresoc.v:42425$2029_Y + attribute \src "libresoc.v:42426.19-42426.132" + wire $and$libresoc.v:42426$2030_Y + attribute \src "libresoc.v:42447.19-42447.131" + wire $and$libresoc.v:42447$2051_Y + attribute \src "libresoc.v:42448.19-42448.119" + wire width 3 $and$libresoc.v:42448$2052_Y + attribute \src "libresoc.v:42451.19-42451.131" + wire $and$libresoc.v:42451$2055_Y + attribute \src "libresoc.v:42453.19-42453.122" + wire $and$libresoc.v:42453$2057_Y + attribute \src "libresoc.v:42454.19-42454.116" + wire $and$libresoc.v:42454$2058_Y + attribute \src "libresoc.v:42456.19-42456.102" + wire $and$libresoc.v:42456$2060_Y + attribute \src "libresoc.v:42457.19-42457.135" + wire $and$libresoc.v:42457$2061_Y + attribute \src "libresoc.v:42459.19-42459.127" + wire $and$libresoc.v:42459$2063_Y + attribute \src "libresoc.v:42460.19-42460.116" + wire $and$libresoc.v:42460$2064_Y + attribute \src "libresoc.v:42462.19-42462.102" + wire $and$libresoc.v:42462$2066_Y + attribute \src "libresoc.v:42463.19-42463.135" + wire $and$libresoc.v:42463$2067_Y + attribute \src "libresoc.v:42465.19-42465.127" + wire $and$libresoc.v:42465$2069_Y + attribute \src "libresoc.v:42466.19-42466.116" + wire $and$libresoc.v:42466$2070_Y + attribute \src "libresoc.v:42468.19-42468.102" + wire $and$libresoc.v:42468$2072_Y + attribute \src "libresoc.v:42469.19-42469.135" + wire $and$libresoc.v:42469$2073_Y + attribute \src "libresoc.v:42471.19-42471.127" + wire $and$libresoc.v:42471$2075_Y + attribute \src "libresoc.v:42472.19-42472.116" + wire $and$libresoc.v:42472$2076_Y + attribute \src "libresoc.v:42474.19-42474.102" + wire $and$libresoc.v:42474$2078_Y + attribute \src "libresoc.v:42475.19-42475.135" + wire $and$libresoc.v:42475$2079_Y + attribute \src "libresoc.v:42477.19-42477.127" + wire $and$libresoc.v:42477$2081_Y + attribute \src "libresoc.v:42478.19-42478.116" + wire $and$libresoc.v:42478$2082_Y + attribute \src "libresoc.v:42480.19-42480.102" + wire $and$libresoc.v:42480$2084_Y + attribute \src "libresoc.v:42481.19-42481.135" + wire $and$libresoc.v:42481$2085_Y + attribute \src "libresoc.v:42483.19-42483.127" + wire $and$libresoc.v:42483$2087_Y + attribute \src "libresoc.v:42484.19-42484.116" + wire $and$libresoc.v:42484$2088_Y + attribute \src "libresoc.v:42486.19-42486.102" + wire $and$libresoc.v:42486$2090_Y + attribute \src "libresoc.v:42487.19-42487.135" + wire $and$libresoc.v:42487$2091_Y + attribute \src "libresoc.v:42496.19-42496.119" + wire width 3 $and$libresoc.v:42496$2101_Y + attribute \src "libresoc.v:42499.19-42499.122" + wire $and$libresoc.v:42499$2104_Y + attribute \src "libresoc.v:42500.19-42500.116" + wire $and$libresoc.v:42500$2105_Y + attribute \src "libresoc.v:42502.19-42502.102" + wire $and$libresoc.v:42502$2107_Y + attribute \src "libresoc.v:42503.19-42503.135" + wire $and$libresoc.v:42503$2108_Y + attribute \src "libresoc.v:42505.19-42505.127" + wire $and$libresoc.v:42505$2110_Y + attribute \src "libresoc.v:42506.19-42506.116" + wire $and$libresoc.v:42506$2111_Y + attribute \src "libresoc.v:42508.19-42508.102" + wire $and$libresoc.v:42508$2113_Y + attribute \src "libresoc.v:42509.19-42509.135" + wire $and$libresoc.v:42509$2114_Y + attribute \src "libresoc.v:42511.19-42511.127" + wire $and$libresoc.v:42511$2116_Y + attribute \src "libresoc.v:42512.19-42512.116" + wire $and$libresoc.v:42512$2117_Y attribute \src "libresoc.v:42514.19-42514.102" - wire $and$libresoc.v:42514$1922_Y - attribute \src "libresoc.v:42515.19-42515.127" - wire $and$libresoc.v:42515$1923_Y - attribute \src "libresoc.v:42517.19-42517.127" - wire $and$libresoc.v:42517$1925_Y - attribute \src "libresoc.v:42518.19-42518.112" - wire $and$libresoc.v:42518$1926_Y - attribute \src "libresoc.v:42520.19-42520.102" - wire $and$libresoc.v:42520$1928_Y - attribute \src "libresoc.v:42521.19-42521.127" - wire $and$libresoc.v:42521$1929_Y - attribute \src "libresoc.v:42523.19-42523.127" - wire $and$libresoc.v:42523$1931_Y - attribute \src "libresoc.v:42524.19-42524.112" - wire $and$libresoc.v:42524$1932_Y - attribute \src "libresoc.v:42526.19-42526.102" - wire $and$libresoc.v:42526$1934_Y - attribute \src "libresoc.v:42527.19-42527.127" - wire $and$libresoc.v:42527$1935_Y - attribute \src "libresoc.v:42529.19-42529.127" - wire $and$libresoc.v:42529$1937_Y - attribute \src "libresoc.v:42530.19-42530.112" - wire $and$libresoc.v:42530$1938_Y - attribute \src "libresoc.v:42532.19-42532.102" - wire $and$libresoc.v:42532$1940_Y - attribute \src "libresoc.v:42533.19-42533.127" - wire $and$libresoc.v:42533$1941_Y - attribute \src "libresoc.v:42535.19-42535.127" - wire $and$libresoc.v:42535$1943_Y - attribute \src "libresoc.v:42536.19-42536.112" - wire $and$libresoc.v:42536$1944_Y - attribute \src "libresoc.v:42538.19-42538.102" - wire $and$libresoc.v:42538$1946_Y - attribute \src "libresoc.v:42539.19-42539.127" - wire $and$libresoc.v:42539$1947_Y - attribute \src "libresoc.v:42541.19-42541.127" - wire $and$libresoc.v:42541$1949_Y - attribute \src "libresoc.v:42542.19-42542.112" - wire $and$libresoc.v:42542$1950_Y - attribute \src "libresoc.v:42544.19-42544.102" - wire $and$libresoc.v:42544$1952_Y - attribute \src "libresoc.v:42545.19-42545.127" - wire $and$libresoc.v:42545$1953_Y - attribute \src "libresoc.v:42547.19-42547.127" - wire $and$libresoc.v:42547$1955_Y - attribute \src "libresoc.v:42548.19-42548.112" - wire $and$libresoc.v:42548$1956_Y - attribute \src "libresoc.v:42550.19-42550.102" - wire $and$libresoc.v:42550$1958_Y - attribute \src "libresoc.v:42551.19-42551.127" - wire $and$libresoc.v:42551$1959_Y + wire $and$libresoc.v:42514$2119_Y + attribute \src "libresoc.v:42515.19-42515.135" + wire $and$libresoc.v:42515$2120_Y + attribute \src "libresoc.v:42520.19-42520.131" + wire $and$libresoc.v:42520$2126_Y + attribute \src "libresoc.v:42521.19-42521.119" + wire width 3 $and$libresoc.v:42521$2127_Y + attribute \src "libresoc.v:42524.19-42524.127" + wire $and$libresoc.v:42524$2130_Y + attribute \src "libresoc.v:42525.19-42525.116" + wire $and$libresoc.v:42525$2131_Y + attribute \src "libresoc.v:42527.19-42527.102" + wire $and$libresoc.v:42527$2133_Y + attribute \src "libresoc.v:42528.19-42528.132" + wire $and$libresoc.v:42528$2134_Y + attribute \src "libresoc.v:42530.19-42530.127" + wire $and$libresoc.v:42530$2136_Y + attribute \src "libresoc.v:42531.19-42531.116" + wire $and$libresoc.v:42531$2137_Y + attribute \src "libresoc.v:42533.19-42533.102" + wire $and$libresoc.v:42533$2139_Y + attribute \src "libresoc.v:42534.19-42534.132" + wire $and$libresoc.v:42534$2140_Y + attribute \src "libresoc.v:42536.19-42536.127" + wire $and$libresoc.v:42536$2142_Y + attribute \src "libresoc.v:42537.19-42537.113" + wire $and$libresoc.v:42537$2143_Y + attribute \src "libresoc.v:42539.19-42539.102" + wire $and$libresoc.v:42539$2145_Y + attribute \src "libresoc.v:42540.19-42540.129" + wire $and$libresoc.v:42540$2146_Y + attribute \src "libresoc.v:42544.19-42544.127" + wire $and$libresoc.v:42544$2150_Y + attribute \src "libresoc.v:42545.19-42545.113" + wire $and$libresoc.v:42545$2151_Y + attribute \src "libresoc.v:42547.19-42547.102" + wire $and$libresoc.v:42547$2153_Y + attribute \src "libresoc.v:42548.19-42548.129" + wire $and$libresoc.v:42548$2154_Y attribute \src "libresoc.v:42553.19-42553.127" - wire $and$libresoc.v:42553$1961_Y - attribute \src "libresoc.v:42554.19-42554.112" - wire $and$libresoc.v:42554$1962_Y + wire $and$libresoc.v:42553$2159_Y + attribute \src "libresoc.v:42554.19-42554.113" + wire $and$libresoc.v:42554$2160_Y attribute \src "libresoc.v:42556.19-42556.102" - wire $and$libresoc.v:42556$1964_Y - attribute \src "libresoc.v:42557.19-42557.127" - wire $and$libresoc.v:42557$1965_Y - attribute \src "libresoc.v:42559.19-42559.127" - wire $and$libresoc.v:42559$1967_Y - attribute \src "libresoc.v:42560.19-42560.112" - wire $and$libresoc.v:42560$1968_Y - attribute \src "libresoc.v:42562.19-42562.102" - wire $and$libresoc.v:42562$1970_Y - attribute \src "libresoc.v:42563.19-42563.127" - wire $and$libresoc.v:42563$1971_Y - attribute \src "libresoc.v:42574.19-42574.122" - wire $and$libresoc.v:42574$1982_Y - attribute \src "libresoc.v:42575.19-42575.112" - wire $and$libresoc.v:42575$1983_Y - attribute \src "libresoc.v:42577.19-42577.102" - wire $and$libresoc.v:42577$1985_Y - attribute \src "libresoc.v:42578.19-42578.127" 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"/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire \$1665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + wire \$1668 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$1659 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - wire \$1662 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - wire width 3 \$1665 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - wire \$1667 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - wire \$1670 + wire \$1671 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + wire \$1676 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + wire width 3 \$1679 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire \$1681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + wire \$1684 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$1675 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - wire \$1678 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - wire width 3 \$1681 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - wire \$1683 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - wire \$1686 + wire \$1687 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1689 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + wire \$1692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + wire width 3 \$1695 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire \$1697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + wire \$1700 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$1691 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - wire \$1694 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - wire width 3 \$1697 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - wire \$1699 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - wire \$1702 + wire \$1703 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1705 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$1707 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - wire \$1710 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - wire width 3 \$1713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + wire \$1708 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + wire width 3 \$1711 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - wire width 64 \$1715 + wire width 64 \$1713 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + wire width 64 \$1715 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$1717 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$1719 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - wire width 64 \$1721 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - wire width 3 \$1723 + wire width 3 \$1721 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + wire width 3 \$1723 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 3 \$1725 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 3 \$1727 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - wire width 3 \$1729 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - wire \$1731 + wire \$1729 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + wire \$1731 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$1733 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$1735 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1737 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1739 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1741 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire \$1743 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - wire \$1746 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + wire \$1744 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$1749 + wire \$1747 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$1751 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - wire \$1754 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + wire \$1749 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + wire \$1752 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + wire \$1755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1757 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - wire \$1759 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - wire \$1762 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + wire \$1760 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$1765 + wire \$1763 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$1767 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - wire \$1770 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - wire \$1773 + wire \$1765 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + wire \$1768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + wire \$1771 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - wire width 64 \$1775 + wire width 64 \$1773 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - wire width 3 \$1777 + wire width 3 \$1775 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - wire \$1778 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + wire \$1776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire \$1779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1781 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire \$1783 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - wire \$1786 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + wire \$1784 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$1789 + wire \$1787 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$1791 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - wire \$1794 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - wire width 2 \$1797 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - wire width 3 \$1799 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + wire \$1789 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + wire \$1792 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + wire width 2 \$1795 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" + wire width 3 \$1797 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire \$1799 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1801 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire \$1803 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - wire \$1806 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + wire \$1804 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + wire \$1807 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1809 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$181 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$1811 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - wire \$1814 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - wire width 10 \$1817 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + wire \$1812 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + wire width 10 \$1815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$189 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$193 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$201 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$205 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$209 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$213 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$217 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" wire \$221 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" wire width 3 \$223 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" wire width 3 \$224 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" wire \$226 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 4 \$228 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$229 @@ -61099,13 +61133,13 @@ module \core wire \$245 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$247 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 6 \$250 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$252 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 4 \$254 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$256 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$257 @@ -61119,7 +61153,7 @@ module \core wire \$265 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 6 \$270 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$271 @@ -61149,7 +61183,7 @@ module \core wire \$295 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$297 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$300 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$301 @@ -61163,7 +61197,7 @@ module \core wire \$309 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$311 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$314 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$315 @@ -61177,7 +61211,7 @@ module \core wire \$323 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$325 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 5 \$328 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$329 @@ -61199,817 +61233,815 @@ module \core wire \$345 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$347 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$350 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$352 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$354 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$356 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$358 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$360 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$362 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$364 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$366 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$368 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$370 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$372 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$374 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$376 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$378 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$380 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$382 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$384 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$386 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$388 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$390 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$392 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$394 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$396 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$398 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$400 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$402 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$404 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 3 \addr_en_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 3 \addr_en_FAST_fast1_branch0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 3 \addr_en_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 3 \addr_en_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 3 \addr_en_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 3 \addr_en_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 7 \addr_en_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 7 \addr_en_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 7 \addr_en_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 7 \addr_en_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 7 \addr_en_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 7 \addr_en_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 7 \addr_en_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 7 \addr_en_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 7 \addr_en_INT_ra_trap0_2 - attribute \src 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\addr_en_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 7 \addr_en_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 3 \addr_en_FAST_fast1_trap0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 7 \addr_en_INT_rabc_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 7 \addr_en_INT_rabc_alu0_10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 7 \addr_en_INT_rabc_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 7 \addr_en_INT_rabc_cr0_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 7 \addr_en_INT_rabc_div0_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 7 \addr_en_INT_rabc_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 7 \addr_en_INT_rabc_ldst0_18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 7 \addr_en_INT_rabc_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 7 \addr_en_INT_rabc_ldst0_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 7 \addr_en_INT_rabc_logical0_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 7 \addr_en_INT_rabc_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 7 \addr_en_INT_rabc_mul0_16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 7 \addr_en_INT_rabc_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" + wire width 7 \addr_en_INT_rabc_shiftrot0_17 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 2 \addr_en_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 2 \addr_en_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 3 \addr_en_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" wire input 67 \bigendian_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 8 \cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 7 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" wire width 64 input 42 \core_core_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 input 61 \core_core_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 62 \core_core_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 input 63 \core_core_cr_wr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 52 \core_core_exc_$signal @@ -62042,15 +62074,15 @@ module \core attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire width 14 input 45 \core_core_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" wire width 2 input 50 \core_core_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 32 input 43 \core_core_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -62127,317 +62159,113 @@ module \core attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 7 input 44 \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" wire input 64 \core_core_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 input 41 \core_core_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 48 \core_core_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 49 \core_core_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 46 \core_core_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 47 \core_core_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" wire width 13 input 60 \core_core_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" wire width 8 input 51 \core_core_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 34 \core_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 35 \core_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 36 \core_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 38 \core_cr_in2$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 37 \core_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 39 \core_cr_in2_ok$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 40 \core_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 17 \core_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 input 28 \core_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 29 \core_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 input 30 \core_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 31 \core_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 input 32 \core_fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 input 33 \core_fasto2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 65 \core_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 18 \core_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 19 \core_reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 20 \core_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 21 \core_reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 22 \core_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 23 \core_reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 16 \core_rego attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 input 25 \core_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 26 \core_spr1_ok attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 input 24 \core_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire output 14 \core_terminate_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire \core_terminate_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" wire width 3 input 27 \core_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" wire output 2 \corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 97 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" wire width 2 \counter - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" wire width 2 \counter$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \cr_data_i @@ -62627,7 +62455,7 @@ module \core wire \dec_ALU_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_ALU_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \dec_ALU_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_BRANCH_BRANCH__cia @@ -62973,7 +62801,7 @@ module \core wire \dec_DIV_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_DIV_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \dec_DIV_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__byte_reverse @@ -63106,7 +62934,7 @@ module \core wire \dec_LDST_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_LDST_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \dec_LDST_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_LOGICAL_LOGICAL__data_len @@ -63242,7 +63070,7 @@ module \core wire \dec_LOGICAL_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_LOGICAL_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \dec_LOGICAL_sv_a_nz attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -63602,187 +63430,187 @@ module \core wire width 64 output 76 \dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 75 \dmi__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_a_branch0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_a_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_b_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_c_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_full_cr_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_FAST_fast1_branch0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_FAST_fast1_branch0_3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_spr0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_FAST_fast2_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_FAST_fast2_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_div0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_ldst0_8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_mul0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_shiftrot0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_spr0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_ra_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_div0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_ldst0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_mul0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_shiftrot0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rb_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rc_ldst0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \dp_INT_rc_shiftrot0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_FAST_fast1_trap0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_FAST_fast1_trap0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_alu0_10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_alu0_10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_cr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_cr0_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_cr0_11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_div0_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_div0_15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_div0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_ldst0_18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_ldst0_18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_ldst0_7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_ldst0_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_ldst0_9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_logical0_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_logical0_13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_logical0_3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_mul0_16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_mul0_16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_mul0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_shiftrot0_17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_shiftrot0_17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_shiftrot0_6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_shiftrot0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_shiftrot0_8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_spr0_14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_spr0_14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_trap0_12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_trap0_12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + wire \dp_INT_rabc_trap0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_SPR_spr1_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_shiftrot0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_spr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ov_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_div0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_logical0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_mul0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_shiftrot0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_spr0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_alu0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_branch0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_ldst0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_shiftrot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_trap0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \fast_dest1__addr @@ -63796,13 +63624,7 @@ module \core wire width 64 \fast_src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \fast_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 \fast_src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \fast_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire \fast_src2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire width 10 \fu_enable attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 output 78 \full_rd2__data_o @@ -63812,17 +63634,17 @@ module \core wire width 6 output 80 \full_rd__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 79 \full_rd__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_cr_a_ok$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_cr_a_ok$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_cr_a_ok$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_cr_a_ok$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_cr_a_ok$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire \fus_cu_busy_o @@ -63873,15 +63695,15 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__go_i$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_rd__go_i$50 + wire width 3 \fus_cu_rd__go_i$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__go_i$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$56 + wire width 5 \fus_cu_rd__go_i$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_rd__go_i$59 + wire width 3 \fus_cu_rd__go_i$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$62 + wire width 6 \fus_cu_rd__go_i$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__go_i$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" @@ -63893,15 +63715,15 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__rel_o$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_rd__rel_o$49 + wire width 3 \fus_cu_rd__rel_o$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__rel_o$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$55 + wire width 5 \fus_cu_rd__rel_o$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_rd__rel_o$58 + wire width 3 \fus_cu_rd__rel_o$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$61 + wire width 6 \fus_cu_rd__rel_o$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__rel_o$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" @@ -64034,23 +63856,23 @@ module \core wire width 64 \fus_dest5_o$161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 \fus_dest6_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fus_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_fast1_ok$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_fast1_ok$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_fast2_ok$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 96 \fus_ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire \fus_ldst_port0_addr_ok_o @@ -64078,37 +63900,37 @@ module \core wire \fus_ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire \fus_ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fus_ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fus_ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_nia_ok$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fus_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \fus_oper_i_alu_alu0__data_len @@ -65277,44 +65099,44 @@ module \core wire \fus_oper_i_ldst_ldst0__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_ldst_ldst0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$42 + wire width 64 \fus_src1_i$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$45 + wire width 64 \fus_src1_i$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$48 + wire width 64 \fus_src1_i$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$51 + wire width 64 \fus_src1_i$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$54 + wire width 64 \fus_src1_i$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$57 + wire width 64 \fus_src1_i$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$60 + wire width 64 \fus_src1_i$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$63 + wire width 64 \fus_src1_i$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src1_i$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$64 + wire width 64 \fus_src2_i$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$65 + wire width 64 \fus_src2_i$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$66 + wire width 64 \fus_src2_i$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$67 + wire width 64 \fus_src2_i$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$68 + wire width 64 \fus_src2_i$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$69 + wire width 64 \fus_src2_i$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$70 + wire width 64 \fus_src2_i$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" @@ -65322,7 +65144,7 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i$71 + wire width 64 \fus_src3_i$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire \fus_src3_i$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" @@ -65359,29 +65181,29 @@ module \core wire width 2 \fus_src6_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 \fus_src6_i$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_ca_ok$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_ca_ok$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_ov_ok$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_ov_ok$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_ov_ok$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_so_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_so_ok$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_so_ok$143 - attribute \src "libresoc.v:36214.7-36214.15" + attribute \src "libresoc.v:36262.7-36262.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 \int_dest1__addr @@ -65390,23 +65212,11 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \int_dest1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 \int_src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \int_src1__data_o + wire width 5 \int_src__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire \int_src1__ren + wire width 64 \int_src__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 \int_src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \int_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire \int_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 \int_src3__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \int_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire \int_src3__ren + wire \int_src__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 81 \issue__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" @@ -65419,123 +65229,123 @@ module \core wire input 82 \issue__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 85 \issue__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" wire input 72 \issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105" wire input 71 \ivalid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 15 \msr__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 13 \msr__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_FAST_fast1_branch0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - wire \pick_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_FAST_fast1_trap0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_alu0_10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_cr0_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_div0_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_ldst0_18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_ldst0_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_logical0_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_mul0_16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_shiftrot0_17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_shiftrot0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_spr0_14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_trap0_12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \pick_INT_rabc_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" wire width 32 input 66 \raw_insn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_CR_cr_a_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_CR_cr_b_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_CR_cr_c_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_CR_full_cr_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_FAST_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" - wire \rdflag_FAST_fast2_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" - wire \rdflag_INT_ra_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" - wire \rdflag_INT_rb_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" - wire \rdflag_INT_rc_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" + wire \rdflag_FAST_fast1_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" + wire \rdflag_INT_rabc_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" + wire \rdflag_INT_rabc_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" + wire \rdflag_INT_rabc_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_SPR_spr1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_XER_xer_ca_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_XER_xer_ov_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_XER_xer_so_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_CR_cr_a_en_o @@ -65564,33 +65374,15 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_FAST_fast1_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 3 \rdpick_FAST_fast1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 3 \rdpick_FAST_fast1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \rdpick_FAST_fast2_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 2 \rdpick_FAST_fast2_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 2 \rdpick_FAST_fast2_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \rdpick_INT_ra_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 9 \rdpick_INT_ra_i + wire width 5 \rdpick_FAST_fast1_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 9 \rdpick_INT_ra_o + wire width 5 \rdpick_FAST_fast1_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \rdpick_INT_rb_en_o + wire \rdpick_INT_rabc_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \rdpick_INT_rb_i + wire width 19 \rdpick_INT_rabc_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \rdpick_INT_rb_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \rdpick_INT_rc_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 2 \rdpick_INT_rc_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 2 \rdpick_INT_rc_o + wire width 19 \rdpick_INT_rabc_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_SPR_spr1_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" @@ -65615,90 +65407,90 @@ module \core wire width 6 \rdpick_XER_xer_so_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 6 \rdpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_FAST_fast1_branch0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire \rp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_FAST_fast1_trap0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_alu0_10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_cr0_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_div0_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_ldst0_18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_ldst0_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_logical0_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_mul0_16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_shiftrot0_17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_shiftrot0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_spr0_14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_trap0_12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + wire \rp_INT_rabc_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_spr0_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 7 \spr_spr1__addr + wire width 4 \spr_spr1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 7 \spr_spr1__addr$175 + wire width 4 \spr_spr1__addr$175 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \spr_spr1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" @@ -65719,17 +65511,17 @@ module \core wire width 64 output 10 \sv__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 9 \sv__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" wire input 68 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \sv_a_nz$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \sv_a_nz$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \sv_a_nz$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \sv_a_nz$179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \sv_a_nz$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 87 \wb_dcache_en @@ -65737,320 +65529,324 @@ module \core wire width 3 input 11 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 69 \wen$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1020 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1038 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1060 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1080 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1227 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1255 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1275 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1295 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1315 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1335 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1355 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1402 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1418 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1434 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1468 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1484 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1500 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1516 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1552 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1568 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1584 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1600 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1645 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1661 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1677 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1693 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1709 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1753 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1769 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1793 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$1813 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" - wire \wp$999 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1036 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1058 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1078 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1098 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1293 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1313 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1353 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1400 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1416 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1432 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1482 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1566 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1582 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1598 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1691 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1707 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1767 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$1811 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" + wire \wp$997 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1007 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1028 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1046 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1068 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1088 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1219 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1247 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1287 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1307 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1327 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1347 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1394 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1410 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1426 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1460 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1476 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1492 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1508 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1544 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1560 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1576 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1592 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1634 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1653 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1669 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1685 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1701 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1745 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1761 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1785 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$1805 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" - wire \wr_pick$988 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1044 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1066 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1325 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1345 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1458 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1474 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1490 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1558 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1632 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1743 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1759 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1783 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$1803 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" + wire \wr_pick$986 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1010 + wire \wr_pick_dly$1008 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1010$next + wire \wr_pick_dly$1008$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1031 + wire \wr_pick_dly$1029 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1031$next + wire \wr_pick_dly$1029$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1049 + wire \wr_pick_dly$1047 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1049$next + wire \wr_pick_dly$1047$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1071 + wire \wr_pick_dly$1069 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1071$next + wire \wr_pick_dly$1069$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1091 + wire \wr_pick_dly$1089 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1091$next + wire \wr_pick_dly$1089$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1111 + wire \wr_pick_dly$1109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1111$next + wire \wr_pick_dly$1109$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1130 + wire \wr_pick_dly$1128 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1130$next + wire \wr_pick_dly$1128$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1148 + wire \wr_pick_dly$1146 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1148$next + wire \wr_pick_dly$1146$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1222 + wire \wr_pick_dly$1220 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1222$next + wire \wr_pick_dly$1220$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1250 + wire \wr_pick_dly$1248 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1250$next + wire \wr_pick_dly$1248$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1270 + wire \wr_pick_dly$1268 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1270$next + wire \wr_pick_dly$1268$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1290 + wire \wr_pick_dly$1288 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1290$next + wire \wr_pick_dly$1288$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1310 + wire \wr_pick_dly$1308 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1310$next + wire \wr_pick_dly$1308$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1330 + wire \wr_pick_dly$1328 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1330$next + wire \wr_pick_dly$1328$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1350 + wire \wr_pick_dly$1348 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1350$next + wire \wr_pick_dly$1348$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1397 + wire \wr_pick_dly$1395 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1397$next + wire \wr_pick_dly$1395$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1413 + wire \wr_pick_dly$1411 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1413$next + wire \wr_pick_dly$1411$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1429 + wire \wr_pick_dly$1427 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1429$next + wire \wr_pick_dly$1427$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1463 + wire \wr_pick_dly$1461 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1463$next + wire \wr_pick_dly$1461$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1479 + wire \wr_pick_dly$1477 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1479$next + wire \wr_pick_dly$1477$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1495 + wire \wr_pick_dly$1493 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1495$next + wire \wr_pick_dly$1493$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1511 + wire \wr_pick_dly$1509 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1511$next + wire \wr_pick_dly$1509$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1547 + wire \wr_pick_dly$1545 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1547$next + wire \wr_pick_dly$1545$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1563 + wire \wr_pick_dly$1561 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1563$next + wire \wr_pick_dly$1561$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1579 + wire \wr_pick_dly$1577 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1579$next + wire \wr_pick_dly$1577$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1595 + wire \wr_pick_dly$1593 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1595$next + wire \wr_pick_dly$1593$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1637 + wire \wr_pick_dly$1635 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1637$next + wire \wr_pick_dly$1635$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1656 + wire \wr_pick_dly$1654 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1656$next + wire \wr_pick_dly$1654$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1672 + wire \wr_pick_dly$1670 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1672$next + wire \wr_pick_dly$1670$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1688 + wire \wr_pick_dly$1686 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1688$next + wire \wr_pick_dly$1686$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1704 + wire \wr_pick_dly$1702 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1704$next + wire \wr_pick_dly$1702$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1748 + wire \wr_pick_dly$1746 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1748$next + wire \wr_pick_dly$1746$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1764 + wire \wr_pick_dly$1762 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1764$next + wire \wr_pick_dly$1762$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1788 + wire \wr_pick_dly$1786 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1788$next + wire \wr_pick_dly$1786$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1808 + wire \wr_pick_dly$1806 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1808$next + wire \wr_pick_dly$1806$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$991 + wire \wr_pick_dly$989 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$991$next + wire \wr_pick_dly$989$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1011 + wire \wr_pick_rise$1009 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1014 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$1015 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1016 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1017 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1018 + wire \wr_pick_rise$1030 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1019 + wire \wr_pick_rise$1035 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1032 + wire \wr_pick_rise$1048 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1037 + wire \wr_pick_rise$1053 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1050 + wire \wr_pick_rise$1054 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1055 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" @@ -66058,128 +65854,124 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1057 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1058 + wire \wr_pick_rise$1070 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1059 + wire \wr_pick_rise$1075 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1072 + wire \wr_pick_rise$1076 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1077 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1078 + wire \wr_pick_rise$1090 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1079 + wire \wr_pick_rise$1095 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1092 + wire \wr_pick_rise$1096 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1097 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1098 + wire \wr_pick_rise$1110 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1099 + wire \wr_pick_rise$1115 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1112 + wire \wr_pick_rise$1116 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1117 + wire \wr_pick_rise$1129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1118 + wire \wr_pick_rise$1134 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1131 + wire \wr_pick_rise$1636 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1136 + wire \wr_pick_rise$1641 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1638 + wire \wr_pick_rise$1642 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1643 + wire \wr_pick_rise$976 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1644 + wire \wr_pick_rise$977 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$978 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$979 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$980 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$981 + wire \wr_pick_rise$990 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$992 + wire \wr_pick_rise$995 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$997 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$998 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \wr_pick_rise$996 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_xer_ov_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_xer_so_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_branch0_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_branch0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_branch0_nia_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_cr0_cr_a_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_cr0_full_cr_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_cr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_div0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_div0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_div0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_div0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_ldst0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_ldst0_o_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_logical0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_logical0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_mul0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_mul0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_mul0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_mul0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_shiftrot0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_shiftrot0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_shiftrot0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_spr1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_xer_ca_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_xer_ov_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_msr_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_nia_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_o_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_CR_cr_a_en_o @@ -66265,19 +66057,8 @@ module \core wire width 3 \xer_wen$171 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_wen$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42103$1506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$988 - connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42103$1506_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42105$1508 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41908$1507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66285,10 +66066,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$95 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42105$1508_Y + connect \Y $and$libresoc.v:41908$1507_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42106$1509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41909$1508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66296,32 +66077,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [2] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42106$1509_Y + connect \Y $and$libresoc.v:41909$1508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42108$1511 + cell $and $and$libresoc.v:41911$1510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1007 - connect \B \$1012 - connect \Y $and$libresoc.v:42108$1511_Y + connect \A \wr_pick$1005 + connect \B \$1010 + connect \Y $and$libresoc.v:41911$1510_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42109$1512 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41912$1511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1007 + connect \A \wr_pick$1005 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42109$1512_Y + connect \Y $and$libresoc.v:41912$1511_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42111$1514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41914$1513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66329,10 +66110,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$98 connect \B \fus_cu_busy_o$23 - connect \Y $and$libresoc.v:42111$1514_Y + connect \Y $and$libresoc.v:41914$1513_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42112$1515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41915$1514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66340,32 +66121,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [3] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42112$1515_Y + connect \Y $and$libresoc.v:41915$1514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42114$1517 + cell $and $and$libresoc.v:41917$1516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1028 - connect \B \$1033 - connect \Y $and$libresoc.v:42114$1517_Y + connect \A \wr_pick$1026 + connect \B \$1031 + connect \Y $and$libresoc.v:41917$1516_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42115$1518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41918$1517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1028 + connect \A \wr_pick$1026 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42115$1518_Y + connect \Y $and$libresoc.v:41918$1517_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42117$1520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41920$1519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66373,10 +66154,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$101 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42117$1520_Y + connect \Y $and$libresoc.v:41920$1519_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42118$1521 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41921$1520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66384,32 +66165,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [4] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42118$1521_Y + connect \Y $and$libresoc.v:41921$1520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42120$1523 + cell $and $and$libresoc.v:41923$1522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1046 - connect \B \$1051 - connect \Y $and$libresoc.v:42120$1523_Y + connect \A \wr_pick$1044 + connect \B \$1049 + connect \Y $and$libresoc.v:41923$1522_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42121$1524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41924$1523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1046 + connect \A \wr_pick$1044 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42121$1524_Y + connect \Y $and$libresoc.v:41924$1523_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42123$1526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41926$1525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66417,10 +66198,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$104 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:42123$1526_Y + connect \Y $and$libresoc.v:41926$1525_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42124$1527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41927$1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66428,32 +66209,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [5] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42124$1527_Y + connect \Y $and$libresoc.v:41927$1526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42126$1529 + cell $and $and$libresoc.v:41929$1528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1068 - connect \B \$1073 - connect \Y $and$libresoc.v:42126$1529_Y + connect \A \wr_pick$1066 + connect \B \$1071 + connect \Y $and$libresoc.v:41929$1528_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42127$1530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41930$1529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1068 + connect \A \wr_pick$1066 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42127$1530_Y + connect \Y $and$libresoc.v:41930$1529_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42129$1532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41932$1531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66461,10 +66242,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$107 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42129$1532_Y + connect \Y $and$libresoc.v:41932$1531_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42130$1533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41933$1532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66472,32 +66253,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [6] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42130$1533_Y + connect \Y $and$libresoc.v:41933$1532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42132$1535 + cell $and $and$libresoc.v:41935$1534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1088 - connect \B \$1093 - connect \Y $and$libresoc.v:42132$1535_Y + connect \A \wr_pick$1086 + connect \B \$1091 + connect \Y $and$libresoc.v:41935$1534_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42133$1536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41936$1535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1088 + connect \A \wr_pick$1086 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42133$1536_Y + connect \Y $and$libresoc.v:41936$1535_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42135$1538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41938$1537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66505,10 +66286,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$110 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:42135$1538_Y + connect \Y $and$libresoc.v:41938$1537_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42136$1539 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41939$1538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66516,32 +66297,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [7] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42136$1539_Y + connect \Y $and$libresoc.v:41939$1538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42138$1541 + cell $and $and$libresoc.v:41941$1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1108 - connect \B \$1113 - connect \Y $and$libresoc.v:42138$1541_Y + connect \A \wr_pick$1106 + connect \B \$1111 + connect \Y $and$libresoc.v:41941$1540_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42139$1542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41942$1541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1108 + connect \A \wr_pick$1106 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42139$1542_Y + connect \Y $and$libresoc.v:41942$1541_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42141$1544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41944$1543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66549,10 +66330,10 @@ module \core parameter \Y_WIDTH 1 connect \A \o_ok connect \B \fus_cu_busy_o$38 - connect \Y $and$libresoc.v:42141$1544_Y + connect \Y $and$libresoc.v:41944$1543_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42142$1545 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41945$1544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66560,32 +66341,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [8] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42142$1545_Y + connect \Y $and$libresoc.v:41945$1544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42144$1547 + cell $and $and$libresoc.v:41947$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1127 - connect \B \$1132 - connect \Y $and$libresoc.v:42144$1547_Y + connect \A \wr_pick$1125 + connect \B \$1130 + connect \Y $and$libresoc.v:41947$1546_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42145$1548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41948$1547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1127 + connect \A \wr_pick$1125 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42145$1548_Y + connect \Y $and$libresoc.v:41948$1547_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42147$1550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41950$1549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66593,10 +66374,10 @@ module \core parameter \Y_WIDTH 1 connect \A \ea_ok connect \B \fus_cu_busy_o$38 - connect \Y $and$libresoc.v:42147$1550_Y + connect \Y $and$libresoc.v:41950$1549_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42148$1551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41951$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66604,32 +66385,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [9] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42148$1551_Y + connect \Y $and$libresoc.v:41951$1550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42150$1553 + cell $and $and$libresoc.v:41953$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1145 - connect \B \$1149 - connect \Y $and$libresoc.v:42150$1553_Y + connect \A \wr_pick$1143 + connect \B \$1147 + connect \Y $and$libresoc.v:41953$1552_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42151$1554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41954$1553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1145 + connect \A \wr_pick$1143 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42151$1554_Y + connect \Y $and$libresoc.v:41954$1553_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42180$1583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41983$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66637,10 +66418,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_full_cr_ok connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:42180$1583_Y + connect \Y $and$libresoc.v:41983$1582_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42181$1584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:41984$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66648,10 +66429,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [1] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42181$1584_Y + connect \Y $and$libresoc.v:41984$1583_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42182$1585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41985$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66659,32 +66440,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_full_cr_o connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:42182$1585_Y + connect \Y $and$libresoc.v:41985$1584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42184$1587 + cell $and $and$libresoc.v:41987$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1219 - connect \B \$1223 - connect \Y $and$libresoc.v:42184$1587_Y + connect \A \wr_pick$1217 + connect \B \$1221 + connect \Y $and$libresoc.v:41987$1586_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42185$1588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:41988$1587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1219 + connect \A \wr_pick$1217 connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:42185$1588_Y + connect \Y $and$libresoc.v:41988$1587_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42187$1590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41990$1589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66692,10 +66473,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42187$1590_Y + connect \Y $and$libresoc.v:41990$1589_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42188$1591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:41991$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66703,10 +66484,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [1] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42188$1591_Y + connect \Y $and$libresoc.v:41991$1590_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42189$1592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:41992$1591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66714,10 +66495,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [2] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42189$1592_Y + connect \Y $and$libresoc.v:41992$1591_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42190$1593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:41993$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66725,10 +66506,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [1] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42190$1593_Y + connect \Y $and$libresoc.v:41993$1592_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42191$1594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:41994$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66736,10 +66517,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [1] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42191$1594_Y + connect \Y $and$libresoc.v:41994$1593_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42192$1595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:41995$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66747,10 +66528,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [1] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42192$1595_Y + connect \Y $and$libresoc.v:41995$1594_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42193$1596 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:41996$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66758,10 +66539,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [1] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42193$1596_Y + connect \Y $and$libresoc.v:41996$1595_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42194$1597 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:41997$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66769,32 +66550,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [0] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42194$1597_Y + connect \Y $and$libresoc.v:41997$1596_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42196$1599 + cell $and $and$libresoc.v:41999$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1247 - connect \B \$1251 - connect \Y $and$libresoc.v:42196$1599_Y + connect \A \wr_pick$1245 + connect \B \$1249 + connect \Y $and$libresoc.v:41999$1598_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42197$1600 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42000$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1247 + connect \A \wr_pick$1245 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42197$1600_Y + connect \Y $and$libresoc.v:42000$1599_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42201$1604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42004$1603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66802,10 +66583,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$122 connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:42201$1604_Y + connect \Y $and$libresoc.v:42004$1603_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42202$1605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42005$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66813,32 +66594,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [1] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42202$1605_Y + connect \Y $and$libresoc.v:42005$1604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42204$1607 + cell $and $and$libresoc.v:42007$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1267 - connect \B \$1271 - connect \Y $and$libresoc.v:42204$1607_Y + connect \A \wr_pick$1265 + connect \B \$1269 + connect \Y $and$libresoc.v:42007$1606_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42205$1608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42008$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1267 + connect \A \wr_pick$1265 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42205$1608_Y + connect \Y $and$libresoc.v:42008$1607_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42209$1612 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42012$1611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66846,10 +66627,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$123 connect \B \fus_cu_busy_o$23 - connect \Y $and$libresoc.v:42209$1612_Y + connect \Y $and$libresoc.v:42012$1611_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42210$1613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42013$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66857,32 +66638,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [2] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42210$1613_Y + connect \Y $and$libresoc.v:42013$1612_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42212$1615 + cell $and $and$libresoc.v:42015$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1287 - connect \B \$1291 - connect \Y $and$libresoc.v:42212$1615_Y + connect \A \wr_pick$1285 + connect \B \$1289 + connect \Y $and$libresoc.v:42015$1614_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42213$1616 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42016$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1287 + connect \A \wr_pick$1285 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42213$1616_Y + connect \Y $and$libresoc.v:42016$1615_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42217$1620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42020$1619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66890,10 +66671,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$124 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:42217$1620_Y + connect \Y $and$libresoc.v:42020$1619_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42218$1621 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42021$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66901,32 +66682,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [3] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42218$1621_Y + connect \Y $and$libresoc.v:42021$1620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42220$1623 + cell $and $and$libresoc.v:42023$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1307 - connect \B \$1311 - connect \Y $and$libresoc.v:42220$1623_Y + connect \A \wr_pick$1305 + connect \B \$1309 + connect \Y $and$libresoc.v:42023$1622_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42221$1624 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42024$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1307 + connect \A \wr_pick$1305 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42221$1624_Y + connect \Y $and$libresoc.v:42024$1623_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42225$1628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42028$1627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66934,10 +66715,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$125 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42225$1628_Y + connect \Y $and$libresoc.v:42028$1627_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42226$1629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42029$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66945,32 +66726,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [4] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42226$1629_Y + connect \Y $and$libresoc.v:42029$1628_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42228$1631 + cell $and $and$libresoc.v:42031$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1327 - connect \B \$1331 - connect \Y $and$libresoc.v:42228$1631_Y + connect \A \wr_pick$1325 + connect \B \$1329 + connect \Y $and$libresoc.v:42031$1630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42229$1632 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42032$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1327 + connect \A \wr_pick$1325 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42229$1632_Y + connect \Y $and$libresoc.v:42032$1631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42233$1636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42036$1635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66978,10 +66759,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$126 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:42233$1636_Y + connect \Y $and$libresoc.v:42036$1635_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42234$1637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42037$1636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66989,32 +66770,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [5] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42234$1637_Y + connect \Y $and$libresoc.v:42037$1636_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42236$1639 + cell $and $and$libresoc.v:42039$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1347 - connect \B \$1351 - connect \Y $and$libresoc.v:42236$1639_Y + connect \A \wr_pick$1345 + connect \B \$1349 + connect \Y $and$libresoc.v:42039$1638_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42237$1640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42040$1639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1347 + connect \A \wr_pick$1345 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42237$1640_Y + connect \Y $and$libresoc.v:42040$1639_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42251$1654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42054$1653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67022,10 +66803,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42251$1654_Y + connect \Y $and$libresoc.v:42054$1653_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42252$1655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42055$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67033,10 +66814,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [2] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42252$1655_Y + connect \Y $and$libresoc.v:42055$1654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42253$1656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42056$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67044,10 +66825,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [5] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42253$1656_Y + connect \Y $and$libresoc.v:42056$1655_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42254$1657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42057$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67055,10 +66836,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [2] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42254$1657_Y + connect \Y $and$libresoc.v:42057$1656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42255$1658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42058$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67066,32 +66847,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [0] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42255$1658_Y + connect \Y $and$libresoc.v:42058$1657_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42257$1660 + cell $and $and$libresoc.v:42060$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1394 - connect \B \$1398 - connect \Y $and$libresoc.v:42257$1660_Y + connect \A \wr_pick$1392 + connect \B \$1396 + connect \Y $and$libresoc.v:42060$1659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42258$1661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42061$1660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1394 + connect \A \wr_pick$1392 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42258$1661_Y + connect \Y $and$libresoc.v:42061$1660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42260$1663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42063$1662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67099,10 +66880,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$132 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42260$1663_Y + connect \Y $and$libresoc.v:42063$1662_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42261$1664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42064$1663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67110,32 +66891,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [1] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42261$1664_Y + connect \Y $and$libresoc.v:42064$1663_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42263$1666 + cell $and $and$libresoc.v:42066$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1410 - connect \B \$1414 - connect \Y $and$libresoc.v:42263$1666_Y + connect \A \wr_pick$1408 + connect \B \$1412 + connect \Y $and$libresoc.v:42066$1665_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42264$1667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42067$1666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1410 + connect \A \wr_pick$1408 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42264$1667_Y + connect \Y $and$libresoc.v:42067$1666_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42266$1669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42069$1668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67143,10 +66924,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$133 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:42266$1669_Y + connect \Y $and$libresoc.v:42069$1668_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42267$1670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42070$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67154,32 +66935,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [2] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42267$1670_Y + connect \Y $and$libresoc.v:42070$1669_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42269$1672 + cell $and $and$libresoc.v:42072$1671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1426 - connect \B \$1430 - connect \Y $and$libresoc.v:42269$1672_Y + connect \A \wr_pick$1424 + connect \B \$1428 + connect \Y $and$libresoc.v:42072$1671_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42270$1673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42073$1672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1426 + connect \A \wr_pick$1424 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42270$1673_Y + connect \Y $and$libresoc.v:42073$1672_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42277$1681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42080$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67187,10 +66968,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42277$1681_Y + connect \Y $and$libresoc.v:42080$1680_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42278$1682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42081$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67198,10 +66979,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [3] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42278$1682_Y + connect \Y $and$libresoc.v:42081$1681_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42279$1683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42082$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67209,10 +66990,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [4] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42279$1683_Y + connect \Y $and$libresoc.v:42082$1682_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42280$1684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42083$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67220,10 +67001,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [2] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42280$1684_Y + connect \Y $and$libresoc.v:42083$1683_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42281$1685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42084$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67231,10 +67012,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [2] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42281$1685_Y + connect \Y $and$libresoc.v:42084$1684_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42282$1686 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42085$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67242,32 +67023,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [0] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42282$1686_Y + connect \Y $and$libresoc.v:42085$1685_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42284$1688 + cell $and $and$libresoc.v:42087$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1460 - connect \B \$1464 - connect \Y $and$libresoc.v:42284$1688_Y + connect \A \wr_pick$1458 + connect \B \$1462 + connect \Y $and$libresoc.v:42087$1687_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42285$1689 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42088$1688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1460 + connect \A \wr_pick$1458 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42285$1689_Y + connect \Y $and$libresoc.v:42088$1688_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42287$1691 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42090$1690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67275,10 +67056,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$136 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42287$1691_Y + connect \Y $and$libresoc.v:42090$1690_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42288$1692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42091$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67286,32 +67067,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [1] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42288$1692_Y + connect \Y $and$libresoc.v:42091$1691_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42290$1694 + cell $and $and$libresoc.v:42093$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1476 - connect \B \$1480 - connect \Y $and$libresoc.v:42290$1694_Y + connect \A \wr_pick$1474 + connect \B \$1478 + connect \Y $and$libresoc.v:42093$1693_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42291$1695 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42094$1694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1476 + connect \A \wr_pick$1474 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42291$1695_Y + connect \Y $and$libresoc.v:42094$1694_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42293$1697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42096$1696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67319,10 +67100,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$137 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:42293$1697_Y + connect \Y $and$libresoc.v:42096$1696_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42294$1698 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42097$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67330,32 +67111,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [2] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42294$1698_Y + connect \Y $and$libresoc.v:42097$1697_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42296$1700 + cell $and $and$libresoc.v:42099$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1492 - connect \B \$1496 - connect \Y $and$libresoc.v:42296$1700_Y + connect \A \wr_pick$1490 + connect \B \$1494 + connect \Y $and$libresoc.v:42099$1699_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42297$1701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42100$1700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1492 + connect \A \wr_pick$1490 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42297$1701_Y + connect \Y $and$libresoc.v:42100$1700_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42299$1703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42102$1702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67363,10 +67144,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$138 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42299$1703_Y + connect \Y $and$libresoc.v:42102$1702_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42300$1704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42103$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67374,32 +67155,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [3] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42300$1704_Y + connect \Y $and$libresoc.v:42103$1703_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42302$1706 + cell $and $and$libresoc.v:42105$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1508 - connect \B \$1512 - connect \Y $and$libresoc.v:42302$1706_Y + connect \A \wr_pick$1506 + connect \B \$1510 + connect \Y $and$libresoc.v:42105$1705_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42303$1707 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42106$1706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1508 + connect \A \wr_pick$1506 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42303$1707_Y + connect \Y $and$libresoc.v:42106$1706_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42311$1715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42114$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67407,10 +67188,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42311$1715_Y + connect \Y $and$libresoc.v:42114$1714_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42312$1716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42115$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67418,10 +67199,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [4] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42312$1716_Y + connect \Y $and$libresoc.v:42115$1715_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42313$1717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42116$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67429,10 +67210,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [3] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42313$1717_Y + connect \Y $and$libresoc.v:42116$1716_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42314$1718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42117$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67440,10 +67221,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [3] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42314$1718_Y + connect \Y $and$libresoc.v:42117$1717_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42315$1719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42118$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67451,10 +67232,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [3] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42315$1719_Y + connect \Y $and$libresoc.v:42118$1718_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42316$1720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42119$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67462,32 +67243,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [0] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42316$1720_Y + connect \Y $and$libresoc.v:42119$1719_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42318$1722 + cell $and $and$libresoc.v:42121$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1544 - connect \B \$1548 - connect \Y $and$libresoc.v:42318$1722_Y + connect \A \wr_pick$1542 + connect \B \$1546 + connect \Y $and$libresoc.v:42121$1721_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42319$1723 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42122$1722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1544 + connect \A \wr_pick$1542 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42319$1723_Y + connect \Y $and$libresoc.v:42122$1722_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42321$1725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42124$1724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67495,10 +67276,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$141 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42321$1725_Y + connect \Y $and$libresoc.v:42124$1724_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42322$1726 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42125$1725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67506,32 +67287,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [1] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42322$1726_Y + connect \Y $and$libresoc.v:42125$1725_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42324$1728 + cell $and $and$libresoc.v:42127$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1560 - connect \B \$1564 - connect \Y $and$libresoc.v:42324$1728_Y + connect \A \wr_pick$1558 + connect \B \$1562 + connect \Y $and$libresoc.v:42127$1727_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42325$1729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42128$1728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1560 + connect \A \wr_pick$1558 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42325$1729_Y + connect \Y $and$libresoc.v:42128$1728_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42327$1731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42130$1730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67539,10 +67320,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$142 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:42327$1731_Y + connect \Y $and$libresoc.v:42130$1730_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42328$1732 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42131$1731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67550,32 +67331,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [2] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42328$1732_Y + connect \Y $and$libresoc.v:42131$1731_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42330$1734 + cell $and $and$libresoc.v:42133$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1576 - connect \B \$1580 - connect \Y $and$libresoc.v:42330$1734_Y + connect \A \wr_pick$1574 + connect \B \$1578 + connect \Y $and$libresoc.v:42133$1733_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42331$1735 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42134$1734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1576 + connect \A \wr_pick$1574 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42331$1735_Y + connect \Y $and$libresoc.v:42134$1734_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42333$1737 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42136$1736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67583,10 +67364,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$143 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42333$1737_Y + connect \Y $and$libresoc.v:42136$1736_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42334$1738 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42137$1737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67594,32 +67375,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [3] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42334$1738_Y + connect \Y $and$libresoc.v:42137$1737_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42336$1740 + cell $and $and$libresoc.v:42139$1739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1592 - connect \B \$1596 - connect \Y $and$libresoc.v:42336$1740_Y + connect \A \wr_pick$1590 + connect \B \$1594 + connect \Y $and$libresoc.v:42139$1739_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42337$1741 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42140$1740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1592 + connect \A \wr_pick$1590 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42337$1741_Y + connect \Y $and$libresoc.v:42140$1740_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42347$1753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42150$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67627,10 +67408,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42347$1753_Y + connect \Y $and$libresoc.v:42150$1752_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42348$1754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42151$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67638,10 +67419,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [0] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42348$1754_Y + connect \Y $and$libresoc.v:42151$1753_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42349$1755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42152$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67649,10 +67430,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [1] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42349$1755_Y + connect \Y $and$libresoc.v:42152$1754_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42350$1756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42153$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67660,10 +67441,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [2] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42350$1756_Y + connect \Y $and$libresoc.v:42153$1755_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42351$1757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42154$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67671,10 +67452,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [1] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42351$1757_Y + connect \Y $and$libresoc.v:42154$1756_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42352$1758 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42155$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67682,10 +67463,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [2] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42352$1758_Y + connect \Y $and$libresoc.v:42155$1757_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42353$1759 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42156$1758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67693,32 +67474,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [0] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42353$1759_Y + connect \Y $and$libresoc.v:42156$1758_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42355$1761 + cell $and $and$libresoc.v:42158$1760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1634 - connect \B \$1639 - connect \Y $and$libresoc.v:42355$1761_Y + connect \A \wr_pick$1632 + connect \B \$1637 + connect \Y $and$libresoc.v:42158$1760_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42356$1762 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42159$1761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1634 + connect \A \wr_pick$1632 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42356$1762_Y + connect \Y $and$libresoc.v:42159$1761_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42358$1764 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42161$1763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67726,10 +67507,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok$150 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42358$1764_Y + connect \Y $and$libresoc.v:42161$1763_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42359$1765 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42162$1764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67737,32 +67518,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [1] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42359$1765_Y + connect \Y $and$libresoc.v:42162$1764_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42361$1767 + cell $and $and$libresoc.v:42164$1766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1653 - connect \B \$1657 - connect \Y $and$libresoc.v:42361$1767_Y + connect \A \wr_pick$1651 + connect \B \$1655 + connect \Y $and$libresoc.v:42164$1766_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42362$1768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42165$1767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1653 + connect \A \wr_pick$1651 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42362$1768_Y + connect \Y $and$libresoc.v:42165$1767_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42364$1770 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42167$1769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67770,10 +67551,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok$151 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42364$1770_Y + connect \Y $and$libresoc.v:42167$1769_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42365$1771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42168$1770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67781,32 +67562,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [2] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42365$1771_Y + connect \Y $and$libresoc.v:42168$1770_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42367$1773 + cell $and $and$libresoc.v:42170$1772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1669 - connect \B \$1673 - connect \Y $and$libresoc.v:42367$1773_Y + connect \A \wr_pick$1667 + connect \B \$1671 + connect \Y $and$libresoc.v:42170$1772_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42368$1774 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42171$1773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1669 + connect \A \wr_pick$1667 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42368$1774_Y + connect \Y $and$libresoc.v:42171$1773_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42370$1776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42173$1775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67814,10 +67595,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast2_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42370$1776_Y + connect \Y $and$libresoc.v:42173$1775_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42371$1777 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42174$1776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67825,32 +67606,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [3] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42371$1777_Y + connect \Y $and$libresoc.v:42174$1776_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42373$1779 + cell $and $and$libresoc.v:42176$1778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1685 - connect \B \$1689 - connect \Y $and$libresoc.v:42373$1779_Y + connect \A \wr_pick$1683 + connect \B \$1687 + connect \Y $and$libresoc.v:42176$1778_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42374$1780 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42177$1779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1685 + connect \A \wr_pick$1683 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42374$1780_Y + connect \Y $and$libresoc.v:42177$1779_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42376$1782 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42179$1781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67858,10 +67639,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast2_ok$152 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42376$1782_Y + connect \Y $and$libresoc.v:42179$1781_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42377$1783 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42180$1782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67869,32 +67650,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [4] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42377$1783_Y + connect \Y $and$libresoc.v:42180$1782_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42379$1785 + cell $and $and$libresoc.v:42182$1784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1701 - connect \B \$1705 - connect \Y $and$libresoc.v:42379$1785_Y + connect \A \wr_pick$1699 + connect \B \$1703 + connect \Y $and$libresoc.v:42182$1784_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42380$1786 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42183$1785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1701 + connect \A \wr_pick$1699 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42380$1786_Y + connect \Y $and$libresoc.v:42183$1785_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42394$1800 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42197$1799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67902,10 +67683,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_nia_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42394$1800_Y + connect \Y $and$libresoc.v:42197$1799_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42395$1801 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42198$1800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67913,10 +67694,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [2] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42395$1801_Y + connect \Y $and$libresoc.v:42198$1800_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42396$1802 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42199$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67924,10 +67705,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [3] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42396$1802_Y + connect \Y $and$libresoc.v:42199$1801_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42397$1803 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42200$1802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67935,32 +67716,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [0] connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42397$1803_Y + connect \Y $and$libresoc.v:42200$1802_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42399$1805 + cell $and $and$libresoc.v:42202$1804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1745 - connect \B \$1749 - connect \Y $and$libresoc.v:42399$1805_Y + connect \A \wr_pick$1743 + connect \B \$1747 + connect \Y $and$libresoc.v:42202$1804_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42400$1806 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42203$1805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1745 + connect \A \wr_pick$1743 connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42400$1806_Y + connect \Y $and$libresoc.v:42203$1805_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42402$1808 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42205$1807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67968,10 +67749,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_nia_ok$158 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42402$1808_Y + connect \Y $and$libresoc.v:42205$1807_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42403$1809 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42206$1808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67979,32 +67760,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [1] connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42403$1809_Y + connect \Y $and$libresoc.v:42206$1808_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42405$1811 + cell $and $and$libresoc.v:42208$1810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1761 - connect \B \$1765 - connect \Y $and$libresoc.v:42405$1811_Y + connect \A \wr_pick$1759 + connect \B \$1763 + connect \Y $and$libresoc.v:42208$1810_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42406$1812 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42209$1811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1761 + connect \A \wr_pick$1759 connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42406$1812_Y + connect \Y $and$libresoc.v:42209$1811_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42411$1818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42214$1817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68012,10 +67793,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_msr_ok connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42411$1818_Y + connect \Y $and$libresoc.v:42214$1817_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42412$1819 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42215$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68023,10 +67804,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [4] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42412$1819_Y + connect \Y $and$libresoc.v:42215$1818_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42413$1820 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42216$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68034,32 +67815,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_msr_o connect \B \wrpick_STATE_msr_en_o - connect \Y $and$libresoc.v:42413$1820_Y + connect \Y $and$libresoc.v:42216$1819_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42415$1822 + cell $and $and$libresoc.v:42218$1821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1785 - connect \B \$1789 - connect \Y $and$libresoc.v:42415$1822_Y + connect \A \wr_pick$1783 + connect \B \$1787 + connect \Y $and$libresoc.v:42218$1821_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42416$1823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42219$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1785 + connect \A \wr_pick$1783 connect \B \wrpick_STATE_msr_en_o - connect \Y $and$libresoc.v:42416$1823_Y + connect \Y $and$libresoc.v:42219$1822_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42419$1827 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42222$1826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68067,10 +67848,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_spr1_ok connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42419$1827_Y + connect \Y $and$libresoc.v:42222$1826_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42420$1828 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42223$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68078,10 +67859,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [1] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42420$1828_Y + connect \Y $and$libresoc.v:42223$1827_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42421$1829 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42224$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68089,32 +67870,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_SPR_spr1_o connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42421$1829_Y + connect \Y $and$libresoc.v:42224$1828_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42423$1831 + cell $and $and$libresoc.v:42226$1830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1805 - connect \B \$1809 - connect \Y $and$libresoc.v:42423$1831_Y + connect \A \wr_pick$1803 + connect \B \$1807 + connect \Y $and$libresoc.v:42226$1830_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42424$1832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42227$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1805 + connect \A \wr_pick$1803 connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42424$1832_Y + connect \Y $and$libresoc.v:42227$1831_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42426$1834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42229$1833 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68122,10 +67903,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 2'10 - connect \Y $and$libresoc.v:42426$1834_Y + connect \Y $and$libresoc.v:42229$1833_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42428$1836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42231$1835 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68133,10 +67914,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 7'1000000 - connect \Y $and$libresoc.v:42428$1836_Y + connect \Y $and$libresoc.v:42231$1835_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42430$1838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42233$1837 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68144,10 +67925,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 6'100000 - connect \Y $and$libresoc.v:42430$1838_Y + connect \Y $and$libresoc.v:42233$1837_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42432$1840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42235$1839 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68155,10 +67936,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 8'10000000 - connect \Y $and$libresoc.v:42432$1840_Y + connect \Y $and$libresoc.v:42235$1839_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42434$1842 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42237$1841 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68166,10 +67947,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 5'10000 - connect \Y $and$libresoc.v:42434$1842_Y + connect \Y $and$libresoc.v:42237$1841_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42436$1844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42239$1843 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68177,10 +67958,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 11'10000000000 - connect \Y $and$libresoc.v:42436$1844_Y + connect \Y $and$libresoc.v:42239$1843_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42438$1846 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42241$1845 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68188,10 +67969,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 10'1000000000 - connect \Y $and$libresoc.v:42438$1846_Y + connect \Y $and$libresoc.v:42241$1845_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42440$1848 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42243$1847 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68199,10 +67980,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 9'100000000 - connect \Y $and$libresoc.v:42440$1848_Y + connect \Y $and$libresoc.v:42243$1847_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42442$1850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42245$1849 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68210,10 +67991,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 4'1000 - connect \Y $and$libresoc.v:42442$1850_Y + connect \Y $and$libresoc.v:42245$1849_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42444$1852 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $and $and$libresoc.v:42247$1851 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68221,10 +68002,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 3'100 - connect \Y $and$libresoc.v:42444$1852_Y + connect \Y $and$libresoc.v:42247$1851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42449$1857 + cell $and $and$libresoc.v:42252$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68232,10 +68013,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42449$1857_Y + connect \Y $and$libresoc.v:42252$1856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42450$1858 + cell $and $and$libresoc.v:42253$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68243,10 +68024,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42450$1858_Y + connect \Y $and$libresoc.v:42253$1857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42453$1861 + cell $and $and$libresoc.v:42256$1860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68254,10 +68035,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42453$1861_Y + connect \Y $and$libresoc.v:42256$1860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42456$1864 + cell $and $and$libresoc.v:42259$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68265,10 +68046,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42456$1864_Y + connect \Y $and$libresoc.v:42259$1863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42463$1871 + cell $and $and$libresoc.v:42266$1870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68276,10 +68057,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42463$1871_Y + connect \Y $and$libresoc.v:42266$1870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42464$1872 + cell $and $and$libresoc.v:42267$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68287,10 +68068,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42464$1872_Y + connect \Y $and$libresoc.v:42267$1871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42467$1875 + cell $and $and$libresoc.v:42270$1874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68298,10 +68079,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42467$1875_Y + connect \Y $and$libresoc.v:42270$1874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42470$1878 + cell $and $and$libresoc.v:42273$1877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68309,10 +68090,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42470$1878_Y + connect \Y $and$libresoc.v:42273$1877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42471$1879 + cell $and $and$libresoc.v:42274$1878 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68320,10 +68101,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42471$1879_Y + connect \Y $and$libresoc.v:42274$1878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42474$1882 + cell $and $and$libresoc.v:42277$1881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68331,10 +68112,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42474$1882_Y + connect \Y $and$libresoc.v:42277$1881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:42476$1884 + cell $and $and$libresoc.v:42279$1883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68342,10 +68123,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42476$1884_Y + connect \Y $and$libresoc.v:42279$1883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:42477$1885 + cell $and $and$libresoc.v:42280$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68353,10 +68134,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 - connect \Y $and$libresoc.v:42477$1885_Y + connect \Y $and$libresoc.v:42280$1884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42481$1889 + cell $and $and$libresoc.v:42284$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68364,10 +68145,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42481$1889_Y + connect \Y $and$libresoc.v:42284$1888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42485$1893 + cell $and $and$libresoc.v:42288$1892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68375,10 +68156,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42485$1893_Y + connect \Y $and$libresoc.v:42288$1892_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42486$1894 + cell $and $and$libresoc.v:42289$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68386,10 +68167,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42486$1894_Y + connect \Y $and$libresoc.v:42289$1893_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42489$1897 + cell $and $and$libresoc.v:42292$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68397,10 +68178,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42489$1897_Y + connect \Y $and$libresoc.v:42292$1896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42492$1900 + cell $and $and$libresoc.v:42295$1899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68408,10 +68189,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42492$1900_Y + connect \Y $and$libresoc.v:42295$1899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42493$1901 + cell $and $and$libresoc.v:42296$1900 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68419,10 +68200,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42493$1901_Y + connect \Y $and$libresoc.v:42296$1900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42496$1904 + cell $and $and$libresoc.v:42299$1903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68430,10 +68211,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42496$1904_Y + connect \Y $and$libresoc.v:42299$1903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42499$1907 + cell $and $and$libresoc.v:42302$1906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68441,10 +68222,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42499$1907_Y + connect \Y $and$libresoc.v:42302$1906_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42500$1908 + cell $and $and$libresoc.v:42303$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68452,10 +68233,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42500$1908_Y + connect \Y $and$libresoc.v:42303$1907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42503$1911 + cell $and $and$libresoc.v:42306$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68463,10 +68244,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42503$1911_Y + connect \Y $and$libresoc.v:42306$1910_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42506$1914 + cell $and $and$libresoc.v:42309$1913 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68474,32 +68255,32 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42506$1914_Y + connect \Y $and$libresoc.v:42309$1913_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42511$1919 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42314$1918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [0] + connect \A \fus_cu_rd__rel_o [1] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42511$1919_Y + connect \Y $and$libresoc.v:42314$1918_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42512$1920 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42315$1919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$352 - connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42512$1920_Y + connect \B \rdflag_INT_rabc_0 + connect \Y $and$libresoc.v:42315$1919_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42514$1922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42317$1921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68507,43 +68288,43 @@ module \core parameter \Y_WIDTH 1 connect \A \$354 connect \B \$356 - connect \Y $and$libresoc.v:42514$1922_Y + connect \Y $and$libresoc.v:42317$1921_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42515$1923 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42318$1922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [0] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42515$1923_Y + connect \A \rdpick_INT_rabc_o [0] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42318$1922_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42517$1925 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42320$1924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [0] + connect \A \fus_cu_rd__rel_o$40 [1] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42517$1925_Y + connect \Y $and$libresoc.v:42320$1924_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42518$1926 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42321$1925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$364 - connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42518$1926_Y + connect \B \rdflag_INT_rabc_0 + connect \Y $and$libresoc.v:42321$1925_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42520$1928 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42323$1927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68551,43 +68332,43 @@ module \core parameter \Y_WIDTH 1 connect \A \$366 connect \B \$368 - connect \Y $and$libresoc.v:42520$1928_Y + connect \Y $and$libresoc.v:42323$1927_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42521$1929 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42324$1928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [1] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42521$1929_Y + connect \A \rdpick_INT_rabc_o [1] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42324$1928_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42523$1931 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42326$1930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$43 [0] + connect \A \fus_cu_rd__rel_o$43 [1] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42523$1931_Y + connect \Y $and$libresoc.v:42326$1930_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42524$1932 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42327$1931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$376 - connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42524$1932_Y + connect \B \rdflag_INT_rabc_0 + connect \Y $and$libresoc.v:42327$1931_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42526$1934 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42329$1933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68595,43 +68376,43 @@ module \core parameter \Y_WIDTH 1 connect \A \$378 connect \B \$380 - connect \Y $and$libresoc.v:42526$1934_Y + connect \Y $and$libresoc.v:42329$1933_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42527$1935 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42330$1934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [2] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42527$1935_Y + connect \A \rdpick_INT_rabc_o [2] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42330$1934_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42529$1937 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42332$1936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$46 [0] + connect \A \fus_cu_rd__rel_o$46 [1] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42529$1937_Y + connect \Y $and$libresoc.v:42332$1936_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42530$1938 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42333$1937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$388 - connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42530$1938_Y + connect \B \rdflag_INT_rabc_0 + connect \Y $and$libresoc.v:42333$1937_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42532$1940 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42335$1939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68639,43 +68420,43 @@ module \core parameter \Y_WIDTH 1 connect \A \$390 connect \B \$392 - connect \Y $and$libresoc.v:42532$1940_Y + connect \Y $and$libresoc.v:42335$1939_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42533$1941 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42336$1940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [3] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42533$1941_Y + connect \A \rdpick_INT_rabc_o [3] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42336$1940_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42535$1943 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42338$1942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [0] - connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42535$1943_Y + connect \A \fus_cu_rd__rel_o$49 [1] + connect \B \fu_enable [6] + connect \Y $and$libresoc.v:42338$1942_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42536$1944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42339$1943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$400 - connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42536$1944_Y + connect \B \rdflag_INT_rabc_0 + connect \Y $and$libresoc.v:42339$1943_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42538$1946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42341$1945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68683,43 +68464,43 @@ module \core parameter \Y_WIDTH 1 connect \A \$402 connect \B \$404 - connect \Y $and$libresoc.v:42538$1946_Y + connect \Y $and$libresoc.v:42341$1945_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42539$1947 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42342$1946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [4] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42539$1947_Y + connect \A \rdpick_INT_rabc_o [4] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42342$1946_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42541$1949 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42344$1948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$52 [0] - connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42541$1949_Y + connect \A \fus_cu_rd__rel_o$52 [1] + connect \B \fu_enable [7] + connect \Y $and$libresoc.v:42344$1948_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42542$1950 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42345$1949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$412 - connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42542$1950_Y + connect \B \rdflag_INT_rabc_0 + connect \Y $and$libresoc.v:42345$1949_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42544$1952 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42347$1951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68727,43 +68508,43 @@ module \core parameter \Y_WIDTH 1 connect \A \$414 connect \B \$416 - connect \Y $and$libresoc.v:42544$1952_Y + connect \Y $and$libresoc.v:42347$1951_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42545$1953 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42348$1952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [5] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42545$1953_Y + connect \A \rdpick_INT_rabc_o [5] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42348$1952_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42547$1955 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42350$1954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$55 [0] - connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42547$1955_Y + connect \A \fus_cu_rd__rel_o$55 [1] + connect \B \fu_enable [8] + connect \Y $and$libresoc.v:42350$1954_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42548$1956 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42351$1955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$424 - connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42548$1956_Y + connect \B \rdflag_INT_rabc_0 + connect \Y $and$libresoc.v:42351$1955_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42550$1958 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42353$1957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68771,43 +68552,43 @@ module \core parameter \Y_WIDTH 1 connect \A \$426 connect \B \$428 - connect \Y $and$libresoc.v:42550$1958_Y + connect \Y $and$libresoc.v:42353$1957_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42551$1959 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42354$1958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [6] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42551$1959_Y + connect \A \rdpick_INT_rabc_o [6] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42354$1958_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42553$1961 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42356$1960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$58 [0] - connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42553$1961_Y + connect \A \fus_cu_rd__rel_o$58 [1] + connect \B \fu_enable [9] + connect \Y $and$libresoc.v:42356$1960_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42554$1962 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42357$1961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$436 - connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42554$1962_Y + connect \B \rdflag_INT_rabc_0 + connect \Y $and$libresoc.v:42357$1961_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42556$1964 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42359$1963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68815,43 +68596,43 @@ module \core parameter \Y_WIDTH 1 connect \A \$438 connect \B \$440 - connect \Y $and$libresoc.v:42556$1964_Y + connect \Y $and$libresoc.v:42359$1963_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42557$1965 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42360$1964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [7] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42557$1965_Y + connect \A \rdpick_INT_rabc_o [7] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42360$1964_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42559$1967 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42362$1966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$61 [0] - connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42559$1967_Y + connect \A \fus_cu_rd__rel_o$55 [2] + connect \B \fu_enable [8] + connect \Y $and$libresoc.v:42362$1966_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42560$1968 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42363$1967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$448 - connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42560$1968_Y + connect \B \rdflag_INT_rabc_1 + connect \Y $and$libresoc.v:42363$1967_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42562$1970 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42365$1969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68859,461 +68640,461 @@ module \core parameter \Y_WIDTH 1 connect \A \$450 connect \B \$452 - connect \Y $and$libresoc.v:42562$1970_Y + connect \Y $and$libresoc.v:42365$1969_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42563$1971 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42366$1970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [8] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42563$1971_Y + connect \A \rdpick_INT_rabc_o [8] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42366$1970_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42574$1982 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42368$1972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [1] - connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42574$1982_Y + connect \A \fus_cu_rd__rel_o$58 [2] + connect \B \fu_enable [9] + connect \Y $and$libresoc.v:42368$1972_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42575$1983 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42369$1973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$479 - connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42575$1983_Y + connect \A \$460 + connect \B \rdflag_INT_rabc_1 + connect \Y $and$libresoc.v:42369$1973_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42577$1985 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42371$1975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$481 - connect \B \$483 - connect \Y $and$libresoc.v:42577$1985_Y + connect \A \$462 + connect \B \$464 + connect \Y $and$libresoc.v:42371$1975_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42578$1986 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42372$1976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [0] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42578$1986_Y + connect \A \rdpick_INT_rabc_o [9] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42372$1976_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42580$1988 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42374$1978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [1] - connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42580$1988_Y + connect \A \fus_cu_rd__rel_o [0] + connect \B \fu_enable [0] + connect \Y $and$libresoc.v:42374$1978_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42581$1989 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42375$1979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$491 - connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42581$1989_Y + connect \A \$472 + connect \B \rdflag_INT_rabc_2 + connect \Y $and$libresoc.v:42375$1979_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42583$1991 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42377$1981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$493 - connect \B \$495 - connect \Y $and$libresoc.v:42583$1991_Y + connect \A \$474 + connect \B \$476 + connect \Y $and$libresoc.v:42377$1981_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42584$1992 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42378$1982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [1] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42584$1992_Y + connect \A \rdpick_INT_rabc_o [10] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42378$1982_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42586$1994 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42380$1984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$43 [1] - connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42586$1994_Y + connect \A \fus_cu_rd__rel_o$40 [0] + connect \B \fu_enable [1] + connect \Y $and$libresoc.v:42380$1984_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42587$1995 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42381$1985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$503 - connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42587$1995_Y + connect \A \$484 + connect \B \rdflag_INT_rabc_2 + connect \Y $and$libresoc.v:42381$1985_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42589$1997 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42383$1987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$505 - connect \B \$507 - connect \Y $and$libresoc.v:42589$1997_Y + connect \A \$486 + connect \B \$488 + connect \Y $and$libresoc.v:42383$1987_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42590$1998 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42384$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [2] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42590$1998_Y + connect \A \rdpick_INT_rabc_o [11] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42384$1988_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42592$2000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42386$1990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$46 [1] - connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42592$2000_Y + connect \A \fus_cu_rd__rel_o$43 [0] + connect \B \fu_enable [3] + connect \Y $and$libresoc.v:42386$1990_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42593$2001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42387$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$515 - connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42593$2001_Y + connect \A \$496 + connect \B \rdflag_INT_rabc_2 + connect \Y $and$libresoc.v:42387$1991_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42595$2003 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42389$1993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$517 - connect \B \$519 - connect \Y $and$libresoc.v:42595$2003_Y + connect \A \$498 + connect \B \$500 + connect \Y $and$libresoc.v:42389$1993_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42596$2004 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42390$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [3] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42596$2004_Y + connect \A \rdpick_INT_rabc_o [12] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42390$1994_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42598$2006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42392$1996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$52 [1] - connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42598$2006_Y + connect \A \fus_cu_rd__rel_o$46 [0] + connect \B \fu_enable [4] + connect \Y $and$libresoc.v:42392$1996_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42599$2007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42393$1997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$527 - connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42599$2007_Y + connect \A \$508 + connect \B \rdflag_INT_rabc_2 + connect \Y $and$libresoc.v:42393$1997_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42601$2009 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42395$1999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$529 - connect \B \$531 - connect \Y $and$libresoc.v:42601$2009_Y + connect \A \$510 + connect \B \$512 + connect \Y $and$libresoc.v:42395$1999_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42602$2010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42396$2000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [4] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42602$2010_Y + connect \A \rdpick_INT_rabc_o [13] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42396$2000_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42604$2012 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42398$2002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$55 [1] - connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42604$2012_Y + connect \A \fus_cu_rd__rel_o$65 [0] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:42398$2002_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42605$2013 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42399$2003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$539 - connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42605$2013_Y + connect \A \$520 + connect \B \rdflag_INT_rabc_2 + connect \Y $and$libresoc.v:42399$2003_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42607$2015 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42401$2005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$541 - connect \B \$543 - connect \Y $and$libresoc.v:42607$2015_Y + connect \A \$522 + connect \B \$524 + connect \Y $and$libresoc.v:42401$2005_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42608$2016 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42402$2006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [5] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42608$2016_Y + connect \A \rdpick_INT_rabc_o [14] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42402$2006_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42610$2018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42404$2008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$58 [1] - connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42610$2018_Y + connect \A \fus_cu_rd__rel_o$49 [0] + connect \B \fu_enable [6] + connect \Y $and$libresoc.v:42404$2008_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42611$2019 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42405$2009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$551 - connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42611$2019_Y + connect \A \$532 + connect \B \rdflag_INT_rabc_2 + connect \Y $and$libresoc.v:42405$2009_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42613$2021 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42407$2011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$553 - connect \B \$555 - connect \Y $and$libresoc.v:42613$2021_Y + connect \A \$534 + connect \B \$536 + connect \Y $and$libresoc.v:42407$2011_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42614$2022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42408$2012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [6] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42614$2022_Y + connect \A \rdpick_INT_rabc_o [15] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42408$2012_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42616$2024 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42410$2014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$61 [1] - connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42616$2024_Y + connect \A \fus_cu_rd__rel_o$52 [0] + connect \B \fu_enable [7] + connect \Y $and$libresoc.v:42410$2014_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42617$2025 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42411$2015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$563 - connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42617$2025_Y + connect \A \$544 + connect \B \rdflag_INT_rabc_2 + connect \Y $and$libresoc.v:42411$2015_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42619$2027 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42413$2017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$565 - connect \B \$567 - connect \Y $and$libresoc.v:42619$2027_Y + connect \A \$546 + connect \B \$548 + connect \Y $and$libresoc.v:42413$2017_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42620$2028 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42414$2018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [7] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42620$2028_Y + connect \A \rdpick_INT_rabc_o [16] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42414$2018_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42630$2038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42416$2020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$58 [2] + connect \A \fus_cu_rd__rel_o$55 [0] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42630$2038_Y + connect \Y $and$libresoc.v:42416$2020_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42631$2039 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42417$2021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$592 - connect \B \rdflag_INT_rc_0 - connect \Y $and$libresoc.v:42631$2039_Y + connect \A \$556 + connect \B \rdflag_INT_rabc_2 + connect \Y $and$libresoc.v:42417$2021_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42633$2041 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42419$2023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$594 - connect \B \$596 - connect \Y $and$libresoc.v:42633$2041_Y + connect \A \$558 + connect \B \$560 + connect \Y $and$libresoc.v:42419$2023_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42634$2042 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42420$2024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rc_o [0] - connect \B \rdpick_INT_rc_en_o - connect \Y $and$libresoc.v:42634$2042_Y + connect \A \rdpick_INT_rabc_o [17] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42420$2024_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42636$2044 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42422$2026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$61 [2] + connect \A \fus_cu_rd__rel_o$58 [0] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42636$2044_Y + connect \Y $and$libresoc.v:42422$2026_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42637$2045 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42423$2027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$604 - connect \B \rdflag_INT_rc_0 - connect \Y $and$libresoc.v:42637$2045_Y + connect \A \$568 + connect \B \rdflag_INT_rabc_2 + connect \Y $and$libresoc.v:42423$2027_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42639$2047 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42425$2029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$606 - connect \B \$608 - connect \Y $and$libresoc.v:42639$2047_Y + connect \A \$570 + connect \B \$572 + connect \Y $and$libresoc.v:42425$2029_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42640$2048 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42426$2030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rc_o [1] - connect \B \rdpick_INT_rc_en_o - connect \Y $and$libresoc.v:42640$2048_Y + connect \A \rdpick_INT_rabc_o [18] + connect \B \rdpick_INT_rabc_en_o + connect \Y $and$libresoc.v:42426$2030_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42644$2052 + cell $and $and$libresoc.v:42447$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69321,10 +69102,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42644$2052_Y + connect \Y $and$libresoc.v:42447$2051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42645$2053 + cell $and $and$libresoc.v:42448$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69332,10 +69113,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42645$2053_Y + connect \Y $and$libresoc.v:42448$2052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42648$2056 + cell $and $and$libresoc.v:42451$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69343,10 +69124,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42648$2056_Y + connect \Y $and$libresoc.v:42451$2055_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42650$2058 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42453$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69354,32 +69135,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [2] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42650$2058_Y + connect \Y $and$libresoc.v:42453$2057_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42651$2059 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42454$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$633 + connect \A \$631 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42651$2059_Y + connect \Y $and$libresoc.v:42454$2058_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42653$2061 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42456$2060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$635 - connect \B \$637 - connect \Y $and$libresoc.v:42653$2061_Y + connect \A \$633 + connect \B \$635 + connect \Y $and$libresoc.v:42456$2060_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42654$2062 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42457$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69387,10 +69168,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [0] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42654$2062_Y + connect \Y $and$libresoc.v:42457$2061_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42656$2064 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42459$2063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69398,32 +69179,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [2] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42656$2064_Y + connect \Y $and$libresoc.v:42459$2063_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42657$2065 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42460$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$645 + connect \A \$643 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42657$2065_Y + connect \Y $and$libresoc.v:42460$2064_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42659$2067 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42462$2066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$647 - connect \B \$649 - connect \Y $and$libresoc.v:42659$2067_Y + connect \A \$645 + connect \B \$647 + connect \Y $and$libresoc.v:42462$2066_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42660$2068 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42463$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69431,43 +69212,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [1] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42660$2068_Y + connect \Y $and$libresoc.v:42463$2067_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42662$2070 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42465$2069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [3] + connect \A \fus_cu_rd__rel_o$65 [3] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42662$2070_Y + connect \Y $and$libresoc.v:42465$2069_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42663$2071 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42466$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$657 + connect \A \$655 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42663$2071_Y + connect \Y $and$libresoc.v:42466$2070_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42665$2073 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42468$2072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$659 - connect \B \$661 - connect \Y $and$libresoc.v:42665$2073_Y + connect \A \$657 + connect \B \$659 + connect \Y $and$libresoc.v:42468$2072_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42666$2074 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42469$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69475,43 +69256,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [2] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42666$2074_Y + connect \Y $and$libresoc.v:42469$2073_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42668$2076 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42471$2075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$52 [2] + connect \A \fus_cu_rd__rel_o$49 [2] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42668$2076_Y + connect \Y $and$libresoc.v:42471$2075_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42669$2077 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42472$2076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$669 + connect \A \$667 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42669$2077_Y + connect \Y $and$libresoc.v:42472$2076_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42671$2079 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42474$2078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$671 - connect \B \$673 - connect \Y $and$libresoc.v:42671$2079_Y + connect \A \$669 + connect \B \$671 + connect \Y $and$libresoc.v:42474$2078_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42672$2080 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42475$2079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69519,43 +69300,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [3] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42672$2080_Y + connect \Y $and$libresoc.v:42475$2079_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42674$2082 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42477$2081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$55 [2] + connect \A \fus_cu_rd__rel_o$52 [2] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42674$2082_Y + connect \Y $and$libresoc.v:42477$2081_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42675$2083 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42478$2082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$681 + connect \A \$679 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42675$2083_Y + connect \Y $and$libresoc.v:42478$2082_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42677$2085 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42480$2084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$683 - connect \B \$685 - connect \Y $and$libresoc.v:42677$2085_Y + connect \A \$681 + connect \B \$683 + connect \Y $and$libresoc.v:42480$2084_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42678$2086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42481$2085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69563,43 +69344,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [4] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42678$2086_Y + connect \Y $and$libresoc.v:42481$2085_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42680$2088 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42483$2087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$58 [3] + connect \A \fus_cu_rd__rel_o$55 [3] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42680$2088_Y + connect \Y $and$libresoc.v:42483$2087_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42681$2089 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42484$2088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$693 + connect \A \$691 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42681$2089_Y + connect \Y $and$libresoc.v:42484$2088_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42683$2091 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42486$2090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$695 - connect \B \$697 - connect \Y $and$libresoc.v:42683$2091_Y + connect \A \$693 + connect \B \$695 + connect \Y $and$libresoc.v:42486$2090_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42684$2092 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42487$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69607,10 +69388,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [5] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42684$2092_Y + connect \Y $and$libresoc.v:42487$2091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42693$2102 + cell $and $and$libresoc.v:42496$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69618,10 +69399,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42693$2102_Y + connect \Y $and$libresoc.v:42496$2101_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42696$2105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42499$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69629,32 +69410,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [3] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42696$2105_Y + connect \Y $and$libresoc.v:42499$2104_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42697$2106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42500$2105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$725 + connect \A \$723 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42697$2106_Y + connect \Y $and$libresoc.v:42500$2105_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42699$2108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42502$2107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$727 - connect \B \$729 - connect \Y $and$libresoc.v:42699$2108_Y + connect \A \$725 + connect \B \$727 + connect \Y $and$libresoc.v:42502$2107_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42700$2109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42503$2108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69662,43 +69443,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [0] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42700$2109_Y + connect \Y $and$libresoc.v:42503$2108_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42702$2111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42505$2110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [5] + connect \A \fus_cu_rd__rel_o$65 [5] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42702$2111_Y + connect \Y $and$libresoc.v:42505$2110_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42703$2112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42506$2111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$737 + connect \A \$735 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42703$2112_Y + connect \Y $and$libresoc.v:42506$2111_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42705$2114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42508$2113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$739 - connect \B \$741 - connect \Y $and$libresoc.v:42705$2114_Y + connect \A \$737 + connect \B \$739 + connect \Y $and$libresoc.v:42508$2113_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42706$2115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42509$2114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69706,43 +69487,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [1] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42706$2115_Y + connect \Y $and$libresoc.v:42509$2114_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42708$2117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42511$2116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$58 [4] + connect \A \fus_cu_rd__rel_o$55 [4] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42708$2117_Y + connect \Y $and$libresoc.v:42511$2116_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42709$2118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42512$2117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$749 + connect \A \$747 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42709$2118_Y + connect \Y $and$libresoc.v:42512$2117_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42711$2120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42514$2119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$751 - connect \B \$753 - connect \Y $and$libresoc.v:42711$2120_Y + connect \A \$749 + connect \B \$751 + connect \Y $and$libresoc.v:42514$2119_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42712$2121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42515$2120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69750,10 +69531,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [2] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42712$2121_Y + connect \Y $and$libresoc.v:42515$2120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:42717$2127 + cell $and $and$libresoc.v:42520$2126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69761,10 +69542,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42717$2127_Y + connect \Y $and$libresoc.v:42520$2126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:42718$2128 + cell $and $and$libresoc.v:42521$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69772,43 +69553,43 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 - connect \Y $and$libresoc.v:42718$2128_Y + connect \Y $and$libresoc.v:42521$2127_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42721$2131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42524$2130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [4] + connect \A \fus_cu_rd__rel_o$65 [4] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42721$2131_Y + connect \Y $and$libresoc.v:42524$2130_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42722$2132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42525$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$775 + connect \A \$773 connect \B \rdflag_XER_xer_ov_0 - connect \Y $and$libresoc.v:42722$2132_Y + connect \Y $and$libresoc.v:42525$2131_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42724$2134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42527$2133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$777 - connect \B \$779 - connect \Y $and$libresoc.v:42724$2134_Y + connect \A \$775 + connect \B \$777 + connect \Y $and$libresoc.v:42527$2133_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42725$2135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42528$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69816,10 +69597,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ov_o connect \B \rdpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42725$2135_Y + connect \Y $and$libresoc.v:42528$2134_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42727$2137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42530$2136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69827,32 +69608,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [2] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42727$2137_Y + connect \Y $and$libresoc.v:42530$2136_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42728$2138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42531$2137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$787 + connect \A \$785 connect \B \rdflag_CR_full_cr_0 - connect \Y $and$libresoc.v:42728$2138_Y + connect \Y $and$libresoc.v:42531$2137_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42730$2140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42533$2139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$789 - connect \B \$791 - connect \Y $and$libresoc.v:42730$2140_Y + connect \A \$787 + connect \B \$789 + connect \Y $and$libresoc.v:42533$2139_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42731$2141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42534$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69860,10 +69641,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_full_cr_o connect \B \rdpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:42731$2141_Y + connect \Y $and$libresoc.v:42534$2140_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42733$2143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42536$2142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69871,32 +69652,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [3] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42733$2143_Y + connect \Y $and$libresoc.v:42536$2142_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42734$2144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42537$2143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$799 + connect \A \$797 connect \B \rdflag_CR_cr_a_0 - connect \Y $and$libresoc.v:42734$2144_Y + connect \Y $and$libresoc.v:42537$2143_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42736$2146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42539$2145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$801 - connect \B \$803 - connect \Y $and$libresoc.v:42736$2146_Y + connect \A \$799 + connect \B \$801 + connect \Y $and$libresoc.v:42539$2145_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42737$2147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42540$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69904,10 +69685,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [0] connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42737$2147_Y + connect \Y $and$libresoc.v:42540$2146_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42741$2151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42544$2150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69915,32 +69696,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [2] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42741$2151_Y + connect \Y $and$libresoc.v:42544$2150_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42742$2152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42545$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$815 + connect \A \$813 connect \B \rdflag_CR_cr_a_0 - connect \Y $and$libresoc.v:42742$2152_Y + connect \Y $and$libresoc.v:42545$2151_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42744$2154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42547$2153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$817 - connect \B \$819 - connect \Y $and$libresoc.v:42744$2154_Y + connect \A \$815 + connect \B \$817 + connect \Y $and$libresoc.v:42547$2153_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42745$2155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42548$2154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69948,10 +69729,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [1] connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42745$2155_Y + connect \Y $and$libresoc.v:42548$2154_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42750$2160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42553$2159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69959,32 +69740,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [4] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42750$2160_Y + connect \Y $and$libresoc.v:42553$2159_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42751$2161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42554$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$834 + connect \A \$832 connect \B \rdflag_CR_cr_b_0 - connect \Y $and$libresoc.v:42751$2161_Y + connect \Y $and$libresoc.v:42554$2160_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42753$2163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42556$2162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$836 - connect \B \$838 - connect \Y $and$libresoc.v:42753$2163_Y + connect \A \$834 + connect \B \$836 + connect \Y $and$libresoc.v:42556$2162_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42754$2164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42557$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69992,10 +69773,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_b_o connect \B \rdpick_CR_cr_b_en_o - connect \Y $and$libresoc.v:42754$2164_Y + connect \Y $and$libresoc.v:42557$2163_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42758$2168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42561$2167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70003,32 +69784,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [5] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42758$2168_Y + connect \Y $and$libresoc.v:42561$2167_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42759$2169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42562$2168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$850 + connect \A \$848 connect \B \rdflag_CR_cr_c_0 - connect \Y $and$libresoc.v:42759$2169_Y + connect \Y $and$libresoc.v:42562$2168_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42761$2171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42564$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$852 - connect \B \$854 - connect \Y $and$libresoc.v:42761$2171_Y + connect \A \$850 + connect \B \$852 + connect \Y $and$libresoc.v:42564$2170_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42762$2172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42565$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70036,10 +69817,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_c_o connect \B \rdpick_CR_cr_c_en_o - connect \Y $and$libresoc.v:42762$2172_Y + connect \Y $and$libresoc.v:42565$2171_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42766$2176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42569$2175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70047,32 +69828,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [0] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42766$2176_Y + connect \Y $and$libresoc.v:42569$2175_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42767$2177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42570$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$866 + connect \A \$864 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42767$2177_Y + connect \Y $and$libresoc.v:42570$2176_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42769$2179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42572$2178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$868 - connect \B \$870 - connect \Y $and$libresoc.v:42769$2179_Y + connect \A \$866 + connect \B \$868 + connect \Y $and$libresoc.v:42572$2178_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42770$2180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42573$2179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70080,10 +69861,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [0] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42770$2180_Y + connect \Y $and$libresoc.v:42573$2179_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42772$2182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42575$2181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70091,32 +69872,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [2] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42772$2182_Y + connect \Y $and$libresoc.v:42575$2181_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42773$2183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42576$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$878 + connect \A \$876 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42773$2183_Y + connect \Y $and$libresoc.v:42576$2182_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42775$2185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42578$2184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$880 - connect \B \$882 - connect \Y $and$libresoc.v:42775$2185_Y + connect \A \$878 + connect \B \$880 + connect \Y $and$libresoc.v:42578$2184_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42776$2186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42579$2185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70124,43 +69905,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [1] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42776$2186_Y + connect \Y $and$libresoc.v:42579$2185_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42778$2188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42581$2187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [2] + connect \A \fus_cu_rd__rel_o$65 [2] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42778$2188_Y + connect \Y $and$libresoc.v:42581$2187_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42779$2189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42582$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$890 + connect \A \$888 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42779$2189_Y + connect \Y $and$libresoc.v:42582$2188_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42781$2191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42584$2190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$892 - connect \B \$894 - connect \Y $and$libresoc.v:42781$2191_Y + connect \A \$890 + connect \B \$892 + connect \Y $and$libresoc.v:42584$2190_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42782$2192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42585$2191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70168,10 +69949,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [2] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42782$2192_Y + connect \Y $and$libresoc.v:42585$2191_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42787$2197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42587$2193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70179,43 +69960,43 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [1] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42787$2197_Y + connect \Y $and$libresoc.v:42587$2193_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42788$2198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42588$2194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$908 - connect \B \rdflag_FAST_fast2_0 - connect \Y $and$libresoc.v:42788$2198_Y + connect \A \$900 + connect \B \rdflag_FAST_fast1_1 + connect \Y $and$libresoc.v:42588$2194_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42790$2200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42590$2196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$910 - connect \B \$912 - connect \Y $and$libresoc.v:42790$2200_Y + connect \A \$902 + connect \B \$904 + connect \Y $and$libresoc.v:42590$2196_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42791$2201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42591$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast2_o [0] - connect \B \rdpick_FAST_fast2_en_o - connect \Y $and$libresoc.v:42791$2201_Y + connect \A \rdpick_FAST_fast1_o [3] + connect \B \rdpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:42591$2197_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42793$2203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42593$2199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70223,76 +70004,76 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [3] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42793$2203_Y + connect \Y $and$libresoc.v:42593$2199_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42794$2204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42594$2200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$920 - connect \B \rdflag_FAST_fast2_0 - connect \Y $and$libresoc.v:42794$2204_Y + connect \A \$912 + connect \B \rdflag_FAST_fast1_1 + connect \Y $and$libresoc.v:42594$2200_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42796$2206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42596$2202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$922 - connect \B \$924 - connect \Y $and$libresoc.v:42796$2206_Y + connect \A \$914 + connect \B \$916 + connect \Y $and$libresoc.v:42596$2202_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42797$2207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42597$2203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast2_o [1] - connect \B \rdpick_FAST_fast2_en_o - connect \Y $and$libresoc.v:42797$2207_Y + connect \A \rdpick_FAST_fast1_o [4] + connect \B \rdpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:42597$2203_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42801$2211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42604$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [1] + connect \A \fus_cu_rd__rel_o$65 [1] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42801$2211_Y + connect \Y $and$libresoc.v:42604$2210_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42802$2212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" + cell $and $and$libresoc.v:42605$2211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$936 + connect \A \$934 connect \B \rdflag_SPR_spr1_0 - connect \Y $and$libresoc.v:42802$2212_Y + connect \Y $and$libresoc.v:42605$2211_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42804$2214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $and $and$libresoc.v:42607$2213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$938 - connect \B \$940 - connect \Y $and$libresoc.v:42804$2214_Y + connect \A \$936 + connect \B \$938 + connect \Y $and$libresoc.v:42607$2213_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42805$2215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + cell $and $and$libresoc.v:42608$2214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70300,10 +70081,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_SPR_spr1_o connect \B \rdpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42805$2215_Y + connect \Y $and$libresoc.v:42608$2214_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42808$2218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42611$2217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70311,10 +70092,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42808$2218_Y + connect \Y $and$libresoc.v:42611$2217_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42809$2219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42612$2218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70322,10 +70103,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [0] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42809$2219_Y + connect \Y $and$libresoc.v:42612$2218_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42810$2220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42613$2219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70333,10 +70114,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [0] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42810$2220_Y + connect \Y $and$libresoc.v:42613$2219_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42811$2221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42614$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70344,10 +70125,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [0] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42811$2221_Y + connect \Y $and$libresoc.v:42614$2220_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42812$2222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42615$2221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70355,10 +70136,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [0] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42812$2222_Y + connect \Y $and$libresoc.v:42615$2221_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42813$2223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42616$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70366,10 +70147,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [0] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42813$2223_Y + connect \Y $and$libresoc.v:42616$2222_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42814$2224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42617$2223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70377,10 +70158,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [0] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42814$2224_Y + connect \Y $and$libresoc.v:42617$2223_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42815$2225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42618$2224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70388,10 +70169,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [0] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42815$2225_Y + connect \Y $and$libresoc.v:42618$2224_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42816$2226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42619$2225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70399,10 +70180,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [0] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42816$2226_Y + connect \Y $and$libresoc.v:42619$2225_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42817$2227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42620$2226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70410,10 +70191,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$113 [0] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42817$2227_Y + connect \Y $and$libresoc.v:42620$2226_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42818$2228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + cell $and $and$libresoc.v:42621$2227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70421,10 +70202,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$113 [1] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42818$2228_Y + connect \Y $and$libresoc.v:42621$2227_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42819$2229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42622$2228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70432,21 +70213,21 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [0] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42819$2229_Y + connect \Y $and$libresoc.v:42622$2228_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42821$2231 + cell $and $and$libresoc.v:42624$2230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick - connect \B \$974 - connect \Y $and$libresoc.v:42821$2231_Y + connect \B \$972 + connect \Y $and$libresoc.v:42624$2230_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42822$2232 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42625$2231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70454,10 +70235,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42822$2232_Y + connect \Y $and$libresoc.v:42625$2231_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42824$2234 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42627$2233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70465,10 +70246,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$92 connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:42824$2234_Y + connect \Y $and$libresoc.v:42627$2233_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42825$2235 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" + cell $and $and$libresoc.v:42628$2234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70476,21 +70257,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [1] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42825$2235_Y + connect \Y $and$libresoc.v:42628$2234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42827$2237 + cell $and $and$libresoc.v:42630$2236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$986 + connect \B \$991 + connect \Y $and$libresoc.v:42630$2236_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" + cell $and $and$libresoc.v:42631$2237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$988 - connect \B \$993 - connect \Y $and$libresoc.v:42827$2237_Y + connect \A \wr_pick$986 + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:42631$2237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42451$1859 + cell $eq $eq$libresoc.v:42254$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70498,10 +70290,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$231 connect \B 1'1 - connect \Y $eq$libresoc.v:42451$1859_Y + connect \Y $eq$libresoc.v:42254$1858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42455$1863 + cell $eq $eq$libresoc.v:42258$1862 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70509,10 +70301,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42455$1863_Y + connect \Y $eq$libresoc.v:42258$1862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42457$1865 + cell $eq $eq$libresoc.v:42260$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70520,10 +70312,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$243 connect \B 3'100 - connect \Y $eq$libresoc.v:42457$1865_Y + connect \Y $eq$libresoc.v:42260$1864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42465$1873 + cell $eq $eq$libresoc.v:42268$1872 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70531,10 +70323,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$259 connect \B 1'1 - connect \Y $eq$libresoc.v:42465$1873_Y + connect \Y $eq$libresoc.v:42268$1872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42472$1880 + cell $eq $eq$libresoc.v:42275$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70542,10 +70334,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$273 connect \B 1'1 - connect \Y $eq$libresoc.v:42472$1880_Y + connect \Y $eq$libresoc.v:42275$1879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$libresoc.v:42478$1886 + cell $eq $eq$libresoc.v:42281$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70553,10 +70345,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$285 connect \B 2'10 - connect \Y $eq$libresoc.v:42478$1886_Y + connect \Y $eq$libresoc.v:42281$1885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42480$1888 + cell $eq $eq$libresoc.v:42283$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70564,10 +70356,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42480$1888_Y + connect \Y $eq$libresoc.v:42283$1887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42482$1890 + cell $eq $eq$libresoc.v:42285$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70575,10 +70367,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$293 connect \B 3'100 - connect \Y $eq$libresoc.v:42482$1890_Y + connect \Y $eq$libresoc.v:42285$1889_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42487$1895 + cell $eq $eq$libresoc.v:42290$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70586,10 +70378,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$303 connect \B 1'1 - connect \Y $eq$libresoc.v:42487$1895_Y + connect \Y $eq$libresoc.v:42290$1894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42494$1902 + cell $eq $eq$libresoc.v:42297$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70597,10 +70389,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$317 connect \B 1'1 - connect \Y $eq$libresoc.v:42494$1902_Y + connect \Y $eq$libresoc.v:42297$1901_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42501$1909 + cell $eq $eq$libresoc.v:42304$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70608,10 +70400,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$331 connect \B 1'1 - connect \Y $eq$libresoc.v:42501$1909_Y + connect \Y $eq$libresoc.v:42304$1908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42505$1913 + cell $eq $eq$libresoc.v:42308$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70619,10 +70411,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42505$1913_Y + connect \Y $eq$libresoc.v:42308$1912_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42507$1915 + cell $eq $eq$libresoc.v:42310$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70630,21 +70422,21 @@ module \core parameter \Y_WIDTH 1 connect \A \$343 connect \B 3'100 - connect \Y $eq$libresoc.v:42507$1915_Y + connect \Y $eq$libresoc.v:42310$1914_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42646$2054 + cell $eq $eq$libresoc.v:42449$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$623 + connect \A \$621 connect \B 1'1 - connect \Y $eq$libresoc.v:42646$2054_Y + connect \Y $eq$libresoc.v:42449$2053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42692$2101 + cell $eq $eq$libresoc.v:42495$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70652,88 +70444,88 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42692$2101_Y + connect \Y $eq$libresoc.v:42495$2100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42694$2103 + cell $eq $eq$libresoc.v:42497$2102 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$719 + connect \A \$717 connect \B 3'100 - connect \Y $eq$libresoc.v:42694$2103_Y + connect \Y $eq$libresoc.v:42497$2102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$libresoc.v:42719$2129 + cell $eq $eq$libresoc.v:42522$2128 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \$769 + connect \A \$767 connect \B 2'10 - connect \Y $eq$libresoc.v:42719$2129_Y + connect \Y $eq$libresoc.v:42522$2128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42276$1679 + cell $pos $extend$libresoc.v:42079$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 - connect \A \$1447 - connect \Y $extend$libresoc.v:42276$1679_Y + connect \A \$1445 + connect \Y $extend$libresoc.v:42079$1678_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42342$1746 + cell $pos $extend$libresoc.v:42145$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 - connect \A \$1611 - connect \Y $extend$libresoc.v:42342$1746_Y + connect \A \$1609 + connect \Y $extend$libresoc.v:42145$1745_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42346$1751 + cell $pos $extend$libresoc.v:42149$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \$1619 - connect \Y $extend$libresoc.v:42346$1751_Y + connect \A \$1617 + connect \Y $extend$libresoc.v:42149$1750_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $pos $extend$libresoc.v:42410$1816 + cell $pos $extend$libresoc.v:42213$1815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \$1778 - connect \Y $extend$libresoc.v:42410$1816_Y + connect \A \$1776 + connect \Y $extend$libresoc.v:42213$1815_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $pos $extend$libresoc.v:42418$1825 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" + cell $pos $extend$libresoc.v:42221$1824 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 - connect \A \addr_en$1796 - connect \Y $extend$libresoc.v:42418$1825_Y + connect \A \addr_en$1794 + connect \Y $extend$libresoc.v:42221$1824_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42691$2099 + cell $pos $extend$libresoc.v:42494$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \$714 - connect \Y $extend$libresoc.v:42691$2099_Y + connect \A \$712 + connect \Y $extend$libresoc.v:42494$2098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42716$2125 + cell $pos $extend$libresoc.v:42519$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 - connect \A \$764 - connect \Y $extend$libresoc.v:42716$2125_Y + connect \A \$762 + connect \Y $extend$libresoc.v:42519$2124_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - cell $ne $ne$libresoc.v:42446$1854 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + cell $ne $ne$libresoc.v:42249$1853 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70741,10 +70533,10 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $ne$libresoc.v:42446$1854_Y + connect \Y $ne$libresoc.v:42249$1853_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - cell $ne $ne$libresoc.v:42448$1856 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + cell $ne $ne$libresoc.v:42251$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70752,706 +70544,706 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $ne$libresoc.v:42448$1856_Y + connect \Y $ne$libresoc.v:42251$1855_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42107$1510 + cell $not $not$libresoc.v:41910$1509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1010 - connect \Y $not$libresoc.v:42107$1510_Y + connect \A \wr_pick_dly$1008 + connect \Y $not$libresoc.v:41910$1509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42113$1516 + cell $not $not$libresoc.v:41916$1515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1031 - connect \Y $not$libresoc.v:42113$1516_Y + connect \A \wr_pick_dly$1029 + connect \Y $not$libresoc.v:41916$1515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42119$1522 + cell $not $not$libresoc.v:41922$1521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1049 - connect \Y $not$libresoc.v:42119$1522_Y + connect \A \wr_pick_dly$1047 + connect \Y $not$libresoc.v:41922$1521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42125$1528 + cell $not $not$libresoc.v:41928$1527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1071 - connect \Y $not$libresoc.v:42125$1528_Y + connect \A \wr_pick_dly$1069 + connect \Y $not$libresoc.v:41928$1527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42131$1534 + cell $not $not$libresoc.v:41934$1533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1091 - connect \Y $not$libresoc.v:42131$1534_Y + connect \A \wr_pick_dly$1089 + connect \Y $not$libresoc.v:41934$1533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42137$1540 + cell $not $not$libresoc.v:41940$1539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1111 - connect \Y $not$libresoc.v:42137$1540_Y + connect \A \wr_pick_dly$1109 + connect \Y $not$libresoc.v:41940$1539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42143$1546 + cell $not $not$libresoc.v:41946$1545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1130 - connect \Y $not$libresoc.v:42143$1546_Y + connect \A \wr_pick_dly$1128 + connect \Y $not$libresoc.v:41946$1545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42149$1552 + cell $not $not$libresoc.v:41952$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1148 - connect \Y $not$libresoc.v:42149$1552_Y + connect \A \wr_pick_dly$1146 + connect \Y $not$libresoc.v:41952$1551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42183$1586 + cell $not $not$libresoc.v:41986$1585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1222 - connect \Y $not$libresoc.v:42183$1586_Y + connect \A \wr_pick_dly$1220 + connect \Y $not$libresoc.v:41986$1585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42195$1598 + cell $not $not$libresoc.v:41998$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1250 - connect \Y $not$libresoc.v:42195$1598_Y + connect \A \wr_pick_dly$1248 + connect \Y $not$libresoc.v:41998$1597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42203$1606 + cell $not $not$libresoc.v:42006$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1270 - connect \Y $not$libresoc.v:42203$1606_Y + connect \A \wr_pick_dly$1268 + connect \Y $not$libresoc.v:42006$1605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42211$1614 + cell $not $not$libresoc.v:42014$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1290 - connect \Y $not$libresoc.v:42211$1614_Y + connect \A \wr_pick_dly$1288 + connect \Y $not$libresoc.v:42014$1613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42219$1622 + cell $not $not$libresoc.v:42022$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1310 - connect \Y $not$libresoc.v:42219$1622_Y + connect \A \wr_pick_dly$1308 + connect \Y $not$libresoc.v:42022$1621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42227$1630 + cell $not $not$libresoc.v:42030$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1330 - connect \Y $not$libresoc.v:42227$1630_Y + connect \A \wr_pick_dly$1328 + connect \Y $not$libresoc.v:42030$1629_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42235$1638 + cell $not $not$libresoc.v:42038$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1350 - connect \Y $not$libresoc.v:42235$1638_Y + connect \A \wr_pick_dly$1348 + connect \Y $not$libresoc.v:42038$1637_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42256$1659 + cell $not $not$libresoc.v:42059$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1397 - connect \Y $not$libresoc.v:42256$1659_Y + connect \A \wr_pick_dly$1395 + connect \Y $not$libresoc.v:42059$1658_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42262$1665 + cell $not $not$libresoc.v:42065$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1413 - connect \Y $not$libresoc.v:42262$1665_Y + connect \A \wr_pick_dly$1411 + connect \Y $not$libresoc.v:42065$1664_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42268$1671 + cell $not $not$libresoc.v:42071$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1429 - connect \Y $not$libresoc.v:42268$1671_Y + connect \A \wr_pick_dly$1427 + connect \Y $not$libresoc.v:42071$1670_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42283$1687 + cell $not $not$libresoc.v:42086$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1463 - connect \Y $not$libresoc.v:42283$1687_Y + connect \A \wr_pick_dly$1461 + connect \Y $not$libresoc.v:42086$1686_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42289$1693 + cell $not $not$libresoc.v:42092$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1479 - connect \Y $not$libresoc.v:42289$1693_Y + connect \A \wr_pick_dly$1477 + connect \Y $not$libresoc.v:42092$1692_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42295$1699 + cell $not $not$libresoc.v:42098$1698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1495 - connect \Y $not$libresoc.v:42295$1699_Y + connect \A \wr_pick_dly$1493 + connect \Y $not$libresoc.v:42098$1698_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42301$1705 + cell $not $not$libresoc.v:42104$1704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1511 - connect \Y $not$libresoc.v:42301$1705_Y + connect \A \wr_pick_dly$1509 + connect \Y $not$libresoc.v:42104$1704_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42317$1721 + cell $not $not$libresoc.v:42120$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1547 - connect \Y $not$libresoc.v:42317$1721_Y + connect \A \wr_pick_dly$1545 + connect \Y $not$libresoc.v:42120$1720_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42323$1727 + cell $not $not$libresoc.v:42126$1726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1563 - connect \Y $not$libresoc.v:42323$1727_Y + connect \A \wr_pick_dly$1561 + connect \Y $not$libresoc.v:42126$1726_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42329$1733 + cell $not $not$libresoc.v:42132$1732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1579 - connect \Y $not$libresoc.v:42329$1733_Y + connect \A \wr_pick_dly$1577 + connect \Y $not$libresoc.v:42132$1732_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42335$1739 + cell $not $not$libresoc.v:42138$1738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1595 - connect \Y $not$libresoc.v:42335$1739_Y + connect \A \wr_pick_dly$1593 + connect \Y $not$libresoc.v:42138$1738_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42354$1760 + cell $not $not$libresoc.v:42157$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1637 - connect \Y $not$libresoc.v:42354$1760_Y + connect \A \wr_pick_dly$1635 + connect \Y $not$libresoc.v:42157$1759_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42360$1766 + cell $not $not$libresoc.v:42163$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1656 - connect \Y $not$libresoc.v:42360$1766_Y + connect \A \wr_pick_dly$1654 + connect \Y $not$libresoc.v:42163$1765_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42366$1772 + cell $not $not$libresoc.v:42169$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1672 - connect \Y $not$libresoc.v:42366$1772_Y + connect \A \wr_pick_dly$1670 + connect \Y $not$libresoc.v:42169$1771_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42372$1778 + cell $not $not$libresoc.v:42175$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1688 - connect \Y $not$libresoc.v:42372$1778_Y + connect \A \wr_pick_dly$1686 + connect \Y $not$libresoc.v:42175$1777_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42378$1784 + cell $not $not$libresoc.v:42181$1783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1704 - connect \Y $not$libresoc.v:42378$1784_Y + connect \A \wr_pick_dly$1702 + connect \Y $not$libresoc.v:42181$1783_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42398$1804 + cell $not $not$libresoc.v:42201$1803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1748 - connect \Y $not$libresoc.v:42398$1804_Y + connect \A \wr_pick_dly$1746 + connect \Y $not$libresoc.v:42201$1803_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42404$1810 + cell $not $not$libresoc.v:42207$1809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1764 - connect \Y $not$libresoc.v:42404$1810_Y + connect \A \wr_pick_dly$1762 + connect \Y $not$libresoc.v:42207$1809_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42414$1821 + cell $not $not$libresoc.v:42217$1820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1788 - connect \Y $not$libresoc.v:42414$1821_Y + connect \A \wr_pick_dly$1786 + connect \Y $not$libresoc.v:42217$1820_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42422$1830 + cell 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$not$libresoc.v:42676$2084 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42479$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_so_mul0_4 - connect \Y $not$libresoc.v:42676$2084_Y + connect \Y $not$libresoc.v:42479$2083_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42682$2090 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42485$2089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_so_shiftrot0_5 - connect \Y $not$libresoc.v:42682$2090_Y + connect \Y $not$libresoc.v:42485$2089_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42698$2107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42501$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ca_alu0_0 - connect \Y $not$libresoc.v:42698$2107_Y + connect \Y $not$libresoc.v:42501$2106_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42704$2113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42507$2112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ca_spr0_1 - connect \Y $not$libresoc.v:42704$2113_Y + connect \Y $not$libresoc.v:42507$2112_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42710$2119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42513$2118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ca_shiftrot0_2 - connect \Y $not$libresoc.v:42710$2119_Y + connect \Y $not$libresoc.v:42513$2118_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42723$2133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42526$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ov_spr0_0 - connect \Y $not$libresoc.v:42723$2133_Y + connect \Y $not$libresoc.v:42526$2132_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42729$2139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42532$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_full_cr_cr0_0 - connect \Y $not$libresoc.v:42729$2139_Y + connect \Y $not$libresoc.v:42532$2138_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42735$2145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42538$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_cr0_0 - connect \Y $not$libresoc.v:42735$2145_Y + connect \Y $not$libresoc.v:42538$2144_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42743$2153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42546$2152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_branch0_1 - connect \Y $not$libresoc.v:42743$2153_Y + connect \Y $not$libresoc.v:42546$2152_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42752$2162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42555$2161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_b_cr0_0 - connect \Y $not$libresoc.v:42752$2162_Y + connect \Y $not$libresoc.v:42555$2161_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42760$2170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42563$2169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_c_cr0_0 - connect \Y $not$libresoc.v:42760$2170_Y + connect \Y $not$libresoc.v:42563$2169_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42768$2178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42571$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_branch0_0 - connect \Y $not$libresoc.v:42768$2178_Y + connect \Y $not$libresoc.v:42571$2177_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42774$2184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42577$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_trap0_1 - connect \Y $not$libresoc.v:42774$2184_Y + connect \Y $not$libresoc.v:42577$2183_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42780$2190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42583$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_spr0_2 - connect \Y $not$libresoc.v:42780$2190_Y + connect \Y $not$libresoc.v:42583$2189_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42789$2199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42589$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dp_FAST_fast2_branch0_0 - connect \Y $not$libresoc.v:42789$2199_Y + connect \A \dp_FAST_fast1_branch0_3 + connect \Y $not$libresoc.v:42589$2195_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42795$2205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42595$2201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dp_FAST_fast2_trap0_1 - connect \Y $not$libresoc.v:42795$2205_Y + connect \A \dp_FAST_fast1_trap0_4 + connect \Y $not$libresoc.v:42595$2201_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42803$2213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" + cell $not $not$libresoc.v:42606$2212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_SPR_spr1_spr0_0 - connect \Y $not$libresoc.v:42803$2213_Y + connect \Y $not$libresoc.v:42606$2212_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42820$2230 + cell $not $not$libresoc.v:42623$2229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly - connect \Y $not$libresoc.v:42820$2230_Y + connect \Y $not$libresoc.v:42623$2229_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42826$2236 + cell $not $not$libresoc.v:42629$2235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$991 - connect \Y $not$libresoc.v:42826$2236_Y + connect \A \wr_pick_dly$989 + connect \Y $not$libresoc.v:42629$2235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42153$1556 + cell $or $or$libresoc.v:41956$1555 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71459,10 +71251,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o connect \B \fus_dest1_o$115 - connect \Y $or$libresoc.v:42153$1556_Y + connect \Y $or$libresoc.v:41956$1555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42154$1557 + cell $or $or$libresoc.v:41957$1556 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71470,32 +71262,32 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$117 connect \B \fus_dest1_o$118 - connect \Y $or$libresoc.v:42154$1557_Y + connect \Y $or$libresoc.v:41957$1556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42155$1558 + cell $or $or$libresoc.v:41958$1557 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest1_o$116 - connect \B \$1162 - connect \Y $or$libresoc.v:42155$1558_Y + connect \B \$1160 + connect \Y $or$libresoc.v:41958$1557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42156$1559 + cell $or $or$libresoc.v:41959$1558 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \$1160 - connect \B \$1164 - connect \Y $or$libresoc.v:42156$1559_Y + connect \A \$1158 + connect \B \$1162 + connect \Y $or$libresoc.v:41959$1558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42157$1560 + cell $or $or$libresoc.v:41960$1559 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71503,10 +71295,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$119 connect \B \fus_dest1_o$120 - connect \Y $or$libresoc.v:42157$1560_Y + connect \Y $or$libresoc.v:41960$1559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42158$1561 + cell $or $or$libresoc.v:41961$1560 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \B_SIGNED 0 @@ -71514,241 +71306,241 @@ module \core parameter \Y_WIDTH 65 connect \A { \o_ok \fus_o } connect \B { \ea_ok \fus_ea } - connect \Y $or$libresoc.v:42158$1561_Y + connect \Y $or$libresoc.v:41961$1560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42159$1562 + cell $or $or$libresoc.v:41962$1561 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 connect \A \fus_dest1_o$121 - connect \B \$1170 - connect \Y $or$libresoc.v:42159$1562_Y + connect \B \$1168 + connect \Y $or$libresoc.v:41962$1561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42160$1563 + cell $or $or$libresoc.v:41963$1562 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 - connect \A \$1168 - connect \B \$1172 - connect \Y $or$libresoc.v:42160$1563_Y + connect \A \$1166 + connect \B \$1170 + connect \Y $or$libresoc.v:41963$1562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42161$1564 + cell $or $or$libresoc.v:41964$1563 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 - connect \A \$1166 - connect \B \$1174 - connect \Y $or$libresoc.v:42161$1564_Y + connect \A \$1164 + connect \B \$1172 + connect \Y $or$libresoc.v:41964$1563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42162$1565 + cell $or $or$libresoc.v:41965$1564 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en - connect \B \addr_en$1002 - connect \Y $or$libresoc.v:42162$1565_Y + connect \B \addr_en$1000 + connect \Y $or$libresoc.v:41965$1564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42163$1566 + cell $or $or$libresoc.v:41966$1565 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en$1041 - connect \B \addr_en$1063 - connect \Y $or$libresoc.v:42163$1566_Y + connect \A \addr_en$1039 + connect \B \addr_en$1061 + connect \Y $or$libresoc.v:41966$1565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42164$1567 + cell $or $or$libresoc.v:41967$1566 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en$1023 - connect \B \$1181 - connect \Y $or$libresoc.v:42164$1567_Y + connect \A \addr_en$1021 + connect \B \$1179 + connect \Y $or$libresoc.v:41967$1566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42165$1568 + cell $or $or$libresoc.v:41968$1567 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$1179 - connect \B \$1183 - connect \Y $or$libresoc.v:42165$1568_Y + connect \A \$1177 + connect \B \$1181 + connect \Y $or$libresoc.v:41968$1567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42166$1569 + cell $or $or$libresoc.v:41969$1568 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en$1083 - connect \B \addr_en$1103 - connect \Y $or$libresoc.v:42166$1569_Y + connect \A \addr_en$1081 + connect \B \addr_en$1101 + connect \Y $or$libresoc.v:41969$1568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42167$1570 + cell $or $or$libresoc.v:41970$1569 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en$1140 - connect \B \addr_en$1156 - connect \Y $or$libresoc.v:42167$1570_Y + connect \A \addr_en$1138 + connect \B \addr_en$1154 + connect \Y $or$libresoc.v:41970$1569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42168$1571 + cell $or $or$libresoc.v:41971$1570 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en$1122 - connect \B \$1189 - connect \Y $or$libresoc.v:42168$1571_Y + connect \A \addr_en$1120 + connect \B \$1187 + connect \Y $or$libresoc.v:41971$1570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42169$1572 + cell $or $or$libresoc.v:41972$1571 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$1187 - connect \B \$1191 - connect \Y $or$libresoc.v:42169$1572_Y + connect \A \$1185 + connect \B \$1189 + connect \Y $or$libresoc.v:41972$1571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42170$1573 + cell $or $or$libresoc.v:41973$1572 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$1185 - connect \B \$1193 - connect \Y $or$libresoc.v:42170$1573_Y + connect \A \$1183 + connect \B \$1191 + connect \Y $or$libresoc.v:41973$1572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42171$1574 + cell $or $or$libresoc.v:41974$1573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wp - connect \B \wp$999 - connect \Y $or$libresoc.v:42171$1574_Y + connect \B \wp$997 + connect \Y $or$libresoc.v:41974$1573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42172$1575 + cell $or $or$libresoc.v:41975$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1038 - connect \B \wp$1060 - connect \Y $or$libresoc.v:42172$1575_Y + connect \A \wp$1036 + connect \B \wp$1058 + connect \Y $or$libresoc.v:41975$1574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42173$1576 + cell $or $or$libresoc.v:41976$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1020 - connect \B \$1199 - connect \Y $or$libresoc.v:42173$1576_Y + connect \A \wp$1018 + connect \B \$1197 + connect \Y $or$libresoc.v:41976$1575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42174$1577 + cell $or $or$libresoc.v:41977$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1197 - connect \B \$1201 - connect \Y $or$libresoc.v:42174$1577_Y + connect \A \$1195 + connect \B \$1199 + connect \Y $or$libresoc.v:41977$1576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42175$1578 + cell $or $or$libresoc.v:41978$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1080 - connect \B \wp$1100 - connect \Y $or$libresoc.v:42175$1578_Y + connect \A \wp$1078 + connect \B \wp$1098 + connect \Y $or$libresoc.v:41978$1577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42176$1579 + cell $or $or$libresoc.v:41979$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1137 - connect \B \wp$1153 - connect \Y $or$libresoc.v:42176$1579_Y + connect \A \wp$1135 + connect \B \wp$1151 + connect \Y $or$libresoc.v:41979$1578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42177$1580 + cell $or $or$libresoc.v:41980$1579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1119 - connect \B \$1207 - connect \Y $or$libresoc.v:42177$1580_Y + connect \A \wp$1117 + connect \B \$1205 + connect \Y $or$libresoc.v:41980$1579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42178$1581 + cell $or $or$libresoc.v:41981$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1205 - connect \B \$1209 - connect \Y $or$libresoc.v:42178$1581_Y + connect \A \$1203 + connect \B \$1207 + connect \Y $or$libresoc.v:41981$1580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42179$1582 + cell $or $or$libresoc.v:41982$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1203 - connect \B \$1211 - connect \Y $or$libresoc.v:42179$1582_Y + connect \A \$1201 + connect \B \$1209 + connect \Y $or$libresoc.v:41982$1581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42241$1644 + cell $or $or$libresoc.v:42044$1643 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71756,21 +71548,21 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest3_o connect \B \fus_dest2_o$128 - connect \Y $or$libresoc.v:42241$1644_Y + connect \Y $or$libresoc.v:42044$1643_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42242$1645 + cell $or $or$libresoc.v:42045$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_dest2_o$127 - connect \B \$1365 - connect \Y $or$libresoc.v:42242$1645_Y + connect \B \$1363 + connect \Y $or$libresoc.v:42045$1644_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42243$1646 + cell $or $or$libresoc.v:42046$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71778,87 +71570,87 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest2_o$130 connect \B \fus_dest2_o$131 - connect \Y $or$libresoc.v:42243$1646_Y + connect \Y $or$libresoc.v:42046$1645_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42244$1647 + cell $or $or$libresoc.v:42047$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_dest2_o$129 - connect \B \$1369 - connect \Y $or$libresoc.v:42244$1647_Y + connect \B \$1367 + connect \Y $or$libresoc.v:42047$1646_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42245$1648 + cell $or $or$libresoc.v:42048$1647 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \$1367 - connect \B \$1371 - connect \Y $or$libresoc.v:42245$1648_Y + connect \A \$1365 + connect \B \$1369 + connect \Y $or$libresoc.v:42048$1647_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42246$1649 + cell $or $or$libresoc.v:42049$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 - connect \A \addr_en$1278 - connect \B \addr_en$1298 - connect \Y $or$libresoc.v:42246$1649_Y + connect \A \addr_en$1276 + connect \B \addr_en$1296 + connect \Y $or$libresoc.v:42049$1648_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42247$1650 + cell $or $or$libresoc.v:42050$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 - connect \A \addr_en$1258 - connect \B \$1376 - connect \Y $or$libresoc.v:42247$1650_Y + connect \A \addr_en$1256 + connect \B \$1374 + connect \Y $or$libresoc.v:42050$1649_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42248$1651 + cell $or $or$libresoc.v:42051$1650 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 - connect \A \addr_en$1338 - connect \B \addr_en$1358 - connect \Y $or$libresoc.v:42248$1651_Y + connect \A \addr_en$1336 + connect \B \addr_en$1356 + connect \Y $or$libresoc.v:42051$1650_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42249$1652 + cell $or $or$libresoc.v:42052$1651 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 - connect \A \addr_en$1318 - connect \B \$1380 - connect \Y $or$libresoc.v:42249$1652_Y + connect \A \addr_en$1316 + connect \B \$1378 + connect \Y $or$libresoc.v:42052$1651_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42250$1653 + cell $or $or$libresoc.v:42053$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 - connect \A \$1378 - connect \B \$1382 - connect \Y $or$libresoc.v:42250$1653_Y + connect \A \$1376 + connect \B \$1380 + connect \Y $or$libresoc.v:42053$1652_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42272$1675 + cell $or $or$libresoc.v:42075$1674 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71866,43 +71658,43 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest6_o connect \B \fus_dest3_o$135 - connect \Y $or$libresoc.v:42272$1675_Y + connect \Y $or$libresoc.v:42075$1674_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42273$1676 + cell $or $or$libresoc.v:42076$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \fus_dest3_o$134 - connect \B \$1440 - connect \Y $or$libresoc.v:42273$1676_Y + connect \B \$1438 + connect \Y $or$libresoc.v:42076$1675_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42274$1677 + cell $or $or$libresoc.v:42077$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \addr_en$1421 - connect \B \addr_en$1437 - connect \Y $or$libresoc.v:42274$1677_Y + connect \A \addr_en$1419 + connect \B \addr_en$1435 + connect \Y $or$libresoc.v:42077$1676_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42275$1678 + cell $or $or$libresoc.v:42078$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \addr_en$1405 - connect \B \$1445 - connect \Y $or$libresoc.v:42275$1678_Y + connect \A \addr_en$1403 + connect \B \$1443 + connect \Y $or$libresoc.v:42078$1677_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42305$1709 + cell $or $or$libresoc.v:42108$1708 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71910,10 +71702,10 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest4_o connect \B \fus_dest5_o - connect \Y $or$libresoc.v:42305$1709_Y + connect \Y $or$libresoc.v:42108$1708_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42306$1710 + cell $or $or$libresoc.v:42109$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71921,54 +71713,54 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest3_o$139 connect \B \fus_dest3_o$140 - connect \Y $or$libresoc.v:42306$1710_Y + connect \Y $or$libresoc.v:42109$1709_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42307$1711 + cell $or $or$libresoc.v:42110$1710 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \$1522 - connect \B \$1524 - connect \Y $or$libresoc.v:42307$1711_Y + connect \A \$1520 + connect \B \$1522 + connect \Y $or$libresoc.v:42110$1710_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42308$1712 + cell $or $or$libresoc.v:42111$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1471 - connect \B \addr_en$1487 - connect \Y $or$libresoc.v:42308$1712_Y + connect \A \addr_en$1469 + connect \B \addr_en$1485 + connect \Y $or$libresoc.v:42111$1711_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42309$1713 + cell $or $or$libresoc.v:42112$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1503 - connect \B \addr_en$1519 - connect \Y $or$libresoc.v:42309$1713_Y + connect \A \addr_en$1501 + connect \B \addr_en$1517 + connect \Y $or$libresoc.v:42112$1712_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42310$1714 + cell $or $or$libresoc.v:42113$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \$1528 - connect \B \$1530 - connect \Y $or$libresoc.v:42310$1714_Y + connect \A \$1526 + connect \B \$1528 + connect \Y $or$libresoc.v:42113$1713_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42339$1743 + cell $or $or$libresoc.v:42142$1742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71976,10 +71768,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_dest5_o$144 connect \B \fus_dest4_o$145 - connect \Y $or$libresoc.v:42339$1743_Y + connect \Y $or$libresoc.v:42142$1742_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42340$1744 + cell $or $or$libresoc.v:42143$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71987,54 +71779,54 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_dest4_o$146 connect \B \fus_dest4_o$147 - connect \Y $or$libresoc.v:42340$1744_Y + connect \Y $or$libresoc.v:42143$1743_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42341$1745 + cell $or $or$libresoc.v:42144$1744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1607 - connect \B \$1609 - connect \Y $or$libresoc.v:42341$1745_Y + connect \A \$1605 + connect \B \$1607 + connect \Y $or$libresoc.v:42144$1744_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42343$1748 + cell $or $or$libresoc.v:42146$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en$1555 - connect \B \addr_en$1571 - connect \Y $or$libresoc.v:42343$1748_Y + connect \A \addr_en$1553 + connect \B \addr_en$1569 + connect \Y $or$libresoc.v:42146$1747_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42344$1749 + cell $or $or$libresoc.v:42147$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en$1587 - connect \B \addr_en$1603 - connect \Y $or$libresoc.v:42344$1749_Y + connect \A \addr_en$1585 + connect \B \addr_en$1601 + connect \Y $or$libresoc.v:42147$1748_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42345$1750 + cell $or $or$libresoc.v:42148$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1615 - connect \B \$1617 - connect \Y $or$libresoc.v:42345$1750_Y + connect \A \$1613 + connect \B \$1615 + connect \Y $or$libresoc.v:42148$1749_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42382$1788 + cell $or $or$libresoc.v:42185$1787 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -72042,10 +71834,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$153 connect \B \fus_dest2_o$154 - connect \Y $or$libresoc.v:42382$1788_Y + connect \Y $or$libresoc.v:42185$1787_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42383$1789 + cell $or $or$libresoc.v:42186$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -72053,120 +71845,120 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest2_o$156 connect \B \fus_dest3_o$157 - connect \Y $or$libresoc.v:42383$1789_Y + connect \Y $or$libresoc.v:42186$1788_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42384$1790 + cell $or $or$libresoc.v:42187$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest3_o$155 - connect \B \$1717 - connect \Y $or$libresoc.v:42384$1790_Y + connect \B \$1715 + connect \Y $or$libresoc.v:42187$1789_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42385$1791 + cell $or $or$libresoc.v:42188$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \$1715 - connect \B \$1719 - connect \Y $or$libresoc.v:42385$1791_Y + connect \A \$1713 + connect \B \$1717 + connect \Y $or$libresoc.v:42188$1790_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42386$1792 + cell $or $or$libresoc.v:42189$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1648 - connect \B \addr_en$1664 - connect \Y $or$libresoc.v:42386$1792_Y + connect \A \addr_en$1646 + connect \B \addr_en$1662 + connect \Y $or$libresoc.v:42189$1791_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42387$1793 + cell $or $or$libresoc.v:42190$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1696 - connect \B \addr_en$1712 - connect \Y $or$libresoc.v:42387$1793_Y + connect \A \addr_en$1694 + connect \B \addr_en$1710 + connect \Y $or$libresoc.v:42190$1792_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42388$1794 + cell $or $or$libresoc.v:42191$1793 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1680 - connect \B \$1725 - connect \Y $or$libresoc.v:42388$1794_Y + connect \A \addr_en$1678 + connect \B \$1723 + connect \Y $or$libresoc.v:42191$1793_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42389$1795 + cell $or $or$libresoc.v:42192$1794 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \$1723 - connect \B \$1727 - connect \Y $or$libresoc.v:42389$1795_Y + connect \A \$1721 + connect \B \$1725 + connect \Y $or$libresoc.v:42192$1794_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42390$1796 + cell $or $or$libresoc.v:42193$1795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1645 - connect \B \wp$1661 - connect \Y $or$libresoc.v:42390$1796_Y + connect \A \wp$1643 + connect \B \wp$1659 + connect \Y $or$libresoc.v:42193$1795_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42391$1797 + cell $or $or$libresoc.v:42194$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1693 - connect \B \wp$1709 - connect \Y $or$libresoc.v:42391$1797_Y + connect \A \wp$1691 + connect \B \wp$1707 + connect \Y $or$libresoc.v:42194$1796_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42392$1798 + cell $or $or$libresoc.v:42195$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1677 - connect \B \$1733 - connect \Y $or$libresoc.v:42392$1798_Y + connect \A \wp$1675 + connect \B \$1731 + connect \Y $or$libresoc.v:42195$1797_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42393$1799 + cell $or $or$libresoc.v:42196$1798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1731 - connect \B \$1735 - connect \Y $or$libresoc.v:42393$1799_Y + connect \A \$1729 + connect \B \$1733 + connect \Y $or$libresoc.v:42196$1798_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42408$1814 + cell $or $or$libresoc.v:42211$1813 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -72174,21 +71966,21 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest3_o$159 connect \B \fus_dest4_o$160 - connect \Y $or$libresoc.v:42408$1814_Y + connect \Y $or$libresoc.v:42211$1813_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42409$1815 + cell $or $or$libresoc.v:42212$1814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en$1756 - connect \B \addr_en$1772 - connect \Y $or$libresoc.v:42409$1815_Y + connect \A \addr_en$1754 + connect \B \addr_en$1770 + connect \Y $or$libresoc.v:42212$1814_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42452$1860 + cell $or $or$libresoc.v:42255$1859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72196,10 +71988,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$229 connect \B \$233 - connect \Y $or$libresoc.v:42452$1860_Y + connect \Y $or$libresoc.v:42255$1859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42454$1862 + cell $or $or$libresoc.v:42257$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72207,10 +71999,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$235 connect \B \$237 - connect \Y $or$libresoc.v:42454$1862_Y + connect \Y $or$libresoc.v:42257$1861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42458$1866 + cell $or $or$libresoc.v:42261$1865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72218,10 +72010,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$241 connect \B \$245 - connect \Y $or$libresoc.v:42458$1866_Y + connect \Y $or$libresoc.v:42261$1865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42466$1874 + cell $or $or$libresoc.v:42269$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72229,10 +72021,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$257 connect \B \$261 - connect \Y $or$libresoc.v:42466$1874_Y + connect \Y $or$libresoc.v:42269$1873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42468$1876 + cell $or $or$libresoc.v:42271$1875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72240,10 +72032,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$263 connect \B \$265 - connect \Y $or$libresoc.v:42468$1876_Y + connect \Y $or$libresoc.v:42271$1875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42473$1881 + cell $or $or$libresoc.v:42276$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72251,10 +72043,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$271 connect \B \$275 - connect \Y $or$libresoc.v:42473$1881_Y + connect \Y $or$libresoc.v:42276$1880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42475$1883 + cell $or $or$libresoc.v:42278$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72262,10 +72054,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$277 connect \B \$279 - connect \Y $or$libresoc.v:42475$1883_Y + connect \Y $or$libresoc.v:42278$1882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$libresoc.v:42479$1887 + cell $or $or$libresoc.v:42282$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72273,10 +72065,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$283 connect \B \$287 - connect \Y $or$libresoc.v:42479$1887_Y + connect \Y $or$libresoc.v:42282$1886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42483$1891 + cell $or $or$libresoc.v:42286$1890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72284,10 +72076,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$291 connect \B \$295 - connect \Y $or$libresoc.v:42483$1891_Y + connect \Y $or$libresoc.v:42286$1890_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42488$1896 + cell $or $or$libresoc.v:42291$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72295,10 +72087,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$301 connect \B \$305 - connect \Y $or$libresoc.v:42488$1896_Y + connect \Y $or$libresoc.v:42291$1895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42490$1898 + cell $or $or$libresoc.v:42293$1897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72306,10 +72098,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$307 connect \B \$309 - connect \Y $or$libresoc.v:42490$1898_Y + connect \Y $or$libresoc.v:42293$1897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42495$1903 + cell $or $or$libresoc.v:42298$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72317,10 +72109,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$315 connect \B \$319 - connect \Y $or$libresoc.v:42495$1903_Y + connect \Y $or$libresoc.v:42298$1902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42497$1905 + cell $or $or$libresoc.v:42300$1904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72328,10 +72120,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$321 connect \B \$323 - connect \Y $or$libresoc.v:42497$1905_Y + connect \Y $or$libresoc.v:42300$1904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42502$1910 + cell $or $or$libresoc.v:42305$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72339,10 +72131,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$329 connect \B \$333 - connect \Y $or$libresoc.v:42502$1910_Y + connect \Y $or$libresoc.v:42305$1909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42504$1912 + cell $or $or$libresoc.v:42307$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72350,10 +72142,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$335 connect \B \$337 - connect \Y $or$libresoc.v:42504$1912_Y + connect \Y $or$libresoc.v:42307$1911_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42508$1916 + cell $or $or$libresoc.v:42311$1915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72361,208 +72153,230 @@ module \core parameter \Y_WIDTH 1 connect \A \$341 connect \B \$345 - connect \Y $or$libresoc.v:42508$1916_Y + connect \Y $or$libresoc.v:42311$1915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42565$1973 + cell $or $or$libresoc.v:42428$2032 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en_INT_ra_alu0_0 - connect \B \addr_en_INT_ra_cr0_1 - connect \Y $or$libresoc.v:42565$1973_Y + connect \A \addr_en_INT_rabc_alu0_0 + connect \B \addr_en_INT_rabc_cr0_1 + connect \Y $or$libresoc.v:42428$2032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42566$1974 + cell $or $or$libresoc.v:42429$2033 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en_INT_ra_trap0_2 - connect \B \addr_en_INT_ra_logical0_3 - connect \Y $or$libresoc.v:42566$1974_Y + connect \A \addr_en_INT_rabc_trap0_2 + connect \B \addr_en_INT_rabc_logical0_3 + connect \Y $or$libresoc.v:42429$2033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42567$1975 + cell $or $or$libresoc.v:42430$2034 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$461 - connect \B \$463 - connect \Y $or$libresoc.v:42567$1975_Y + connect \A \$581 + connect \B \$583 + connect \Y $or$libresoc.v:42430$2034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42568$1976 + cell $or $or$libresoc.v:42431$2035 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en_INT_ra_spr0_4 - connect \B \addr_en_INT_ra_div0_5 - connect \Y $or$libresoc.v:42568$1976_Y + connect \A \addr_en_INT_rabc_div0_4 + connect \B \addr_en_INT_rabc_mul0_5 + connect \Y $or$libresoc.v:42431$2035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42569$1977 + cell $or $or$libresoc.v:42432$2036 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en_INT_ra_shiftrot0_7 - connect \B \addr_en_INT_ra_ldst0_8 - connect \Y $or$libresoc.v:42569$1977_Y + connect \A \addr_en_INT_rabc_ldst0_7 + connect \B \addr_en_INT_rabc_shiftrot0_8 + connect \Y $or$libresoc.v:42432$2036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42570$1978 + cell $or $or$libresoc.v:42433$2037 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en_INT_ra_mul0_6 - connect \B \$469 - connect \Y $or$libresoc.v:42570$1978_Y + connect \A \addr_en_INT_rabc_shiftrot0_6 + connect \B \$589 + connect \Y $or$libresoc.v:42433$2037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42571$1979 + cell $or $or$libresoc.v:42434$2038 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$467 - connect \B \$471 - connect \Y $or$libresoc.v:42571$1979_Y + connect \A \$587 + connect \B \$591 + connect \Y $or$libresoc.v:42434$2038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42572$1980 + cell $or $or$libresoc.v:42435$2039 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$465 - connect \B \$473 - connect \Y $or$libresoc.v:42572$1980_Y + connect \A \$585 + connect \B \$593 + connect \Y $or$libresoc.v:42435$2039_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42622$2030 + cell $or $or$libresoc.v:42436$2040 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en_INT_rb_alu0_0 - connect \B \addr_en_INT_rb_cr0_1 - connect \Y $or$libresoc.v:42622$2030_Y + connect \A \addr_en_INT_rabc_ldst0_9 + connect \B \addr_en_INT_rabc_alu0_10 + connect \Y $or$libresoc.v:42436$2040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42623$2031 + cell $or $or$libresoc.v:42437$2041 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en_INT_rb_trap0_2 - connect \B \addr_en_INT_rb_logical0_3 - connect \Y $or$libresoc.v:42623$2031_Y + connect \A \addr_en_INT_rabc_trap0_12 + connect \B \addr_en_INT_rabc_logical0_13 + connect \Y $or$libresoc.v:42437$2041_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42624$2032 + cell $or $or$libresoc.v:42438$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$576 - connect \B \$578 - connect \Y $or$libresoc.v:42624$2032_Y + connect \A \addr_en_INT_rabc_cr0_11 + connect \B \$599 + connect \Y $or$libresoc.v:42438$2042_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42439$2043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A \$597 + connect \B \$601 + connect \Y $or$libresoc.v:42439$2043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42625$2033 + cell $or $or$libresoc.v:42440$2044 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en_INT_rb_div0_4 - connect \B \addr_en_INT_rb_mul0_5 - connect \Y $or$libresoc.v:42625$2033_Y + connect \A \addr_en_INT_rabc_spr0_14 + connect \B \addr_en_INT_rabc_div0_15 + connect \Y $or$libresoc.v:42440$2044_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42626$2034 + cell $or $or$libresoc.v:42441$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en_INT_rb_shiftrot0_6 - connect \B \addr_en_INT_rb_ldst0_7 - connect \Y $or$libresoc.v:42626$2034_Y + connect \A \addr_en_INT_rabc_shiftrot0_17 + connect \B \addr_en_INT_rabc_ldst0_18 + connect \Y $or$libresoc.v:42441$2045_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42627$2035 + cell $or $or$libresoc.v:42442$2046 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$582 - connect \B \$584 - connect \Y $or$libresoc.v:42627$2035_Y + connect \A \addr_en_INT_rabc_mul0_16 + connect \B \$607 + connect \Y $or$libresoc.v:42442$2046_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42628$2036 + cell $or $or$libresoc.v:42443$2047 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$580 - connect \B \$586 - connect \Y $or$libresoc.v:42628$2036_Y + connect \A \$605 + connect \B \$609 + connect \Y $or$libresoc.v:42443$2047_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42642$2050 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42444$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en_INT_rc_shiftrot0_0 - connect \B \addr_en_INT_rc_ldst0_1 - connect \Y $or$libresoc.v:42642$2050_Y + connect \A \$603 + connect \B \$611 + connect \Y $or$libresoc.v:42444$2048_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42445$2049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A \$595 + connect \B \$613 + connect \Y $or$libresoc.v:42445$2049_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42647$2055 + cell $or $or$libresoc.v:42450$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$621 - connect \B \$625 - connect \Y $or$libresoc.v:42647$2055_Y + connect \A \$619 + connect \B \$623 + connect \Y $or$libresoc.v:42450$2054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42649$2057 + cell $or $or$libresoc.v:42452$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$627 - connect \B \$629 - connect \Y $or$libresoc.v:42649$2057_Y + connect \A \$625 + connect \B \$627 + connect \Y $or$libresoc.v:42452$2056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42686$2094 + cell $or $or$libresoc.v:42489$2093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72570,21 +72384,21 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_logical0_1 connect \B \addr_en_XER_xer_so_spr0_2 - connect \Y $or$libresoc.v:42686$2094_Y + connect \Y $or$libresoc.v:42489$2093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42687$2095 + cell $or $or$libresoc.v:42490$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_alu0_0 - connect \B \$706 - connect \Y $or$libresoc.v:42687$2095_Y + connect \B \$704 + connect \Y $or$libresoc.v:42490$2094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42688$2096 + cell $or $or$libresoc.v:42491$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72592,43 +72406,43 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_mul0_4 connect \B \addr_en_XER_xer_so_shiftrot0_5 - connect \Y $or$libresoc.v:42688$2096_Y + connect \Y $or$libresoc.v:42491$2095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42689$2097 + cell $or $or$libresoc.v:42492$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_div0_3 - connect \B \$710 - connect \Y $or$libresoc.v:42689$2097_Y + connect \B \$708 + connect \Y $or$libresoc.v:42492$2096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42690$2098 + cell $or $or$libresoc.v:42493$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$708 - connect \B \$712 - connect \Y $or$libresoc.v:42690$2098_Y + connect \A \$706 + connect \B \$710 + connect \Y $or$libresoc.v:42493$2097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42695$2104 + cell $or $or$libresoc.v:42498$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$717 - connect \B \$721 - connect \Y $or$libresoc.v:42695$2104_Y + connect \A \$715 + connect \B \$719 + connect \Y $or$libresoc.v:42498$2103_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42714$2123 + cell $or $or$libresoc.v:42517$2122 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -72636,32 +72450,32 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_spr0_1 connect \B \addr_en_XER_xer_ca_shiftrot0_2 - connect \Y $or$libresoc.v:42714$2123_Y + connect \Y $or$libresoc.v:42517$2122_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42715$2124 + cell $or $or$libresoc.v:42518$2123 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_alu0_0 - connect \B \$762 - connect \Y $or$libresoc.v:42715$2124_Y + connect \B \$760 + connect \Y $or$libresoc.v:42518$2123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$libresoc.v:42720$2130 + cell $or $or$libresoc.v:42523$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$767 - connect \B \$771 - connect \Y $or$libresoc.v:42720$2130_Y + connect \A \$765 + connect \B \$769 + connect \Y $or$libresoc.v:42523$2129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42749$2159 + cell $or $or$libresoc.v:42552$2158 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -72669,337 +72483,324 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en_CR_cr_a_cr0_0 connect \B \addr_en_CR_cr_a_branch0_1 - connect \Y $or$libresoc.v:42749$2159_Y + connect \Y $or$libresoc.v:42552$2158_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42784$2194 + cell $or $or$libresoc.v:42599$2205 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en_FAST_fast1_trap0_1 - connect \B \addr_en_FAST_fast1_spr0_2 - connect \Y $or$libresoc.v:42784$2194_Y + connect \A \addr_en_FAST_fast1_branch0_0 + connect \B \addr_en_FAST_fast1_trap0_1 + connect \Y $or$libresoc.v:42599$2205_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:42600$2206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en_FAST_fast1_branch0_3 + connect \B \addr_en_FAST_fast1_trap0_4 + connect \Y $or$libresoc.v:42600$2206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42785$2195 + cell $or $or$libresoc.v:42601$2207 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en_FAST_fast1_branch0_0 - connect \B \$902 - connect \Y $or$libresoc.v:42785$2195_Y + connect \A \addr_en_FAST_fast1_spr0_2 + connect \B \$926 + connect \Y $or$libresoc.v:42601$2207_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42799$2209 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:42602$2208 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en_FAST_fast2_branch0_0 - connect \B \addr_en_FAST_fast2_trap0_1 - connect \Y $or$libresoc.v:42799$2209_Y + connect \A \$924 + connect \B \$928 + connect \Y $or$libresoc.v:42602$2208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42276$1680 + cell $pos $pos$libresoc.v:42079$1679 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42276$1679_Y - connect \Y $pos$libresoc.v:42276$1680_Y + connect \A $extend$libresoc.v:42079$1678_Y + connect \Y $pos$libresoc.v:42079$1679_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42342$1747 + cell $pos $pos$libresoc.v:42145$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:42342$1746_Y - connect \Y $pos$libresoc.v:42342$1747_Y + connect \A $extend$libresoc.v:42145$1745_Y + connect \Y $pos$libresoc.v:42145$1746_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42346$1752 + cell $pos $pos$libresoc.v:42149$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42346$1751_Y - connect \Y $pos$libresoc.v:42346$1752_Y + connect \A $extend$libresoc.v:42149$1750_Y + connect \Y $pos$libresoc.v:42149$1751_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $pos $pos$libresoc.v:42410$1817 + cell $pos $pos$libresoc.v:42213$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42410$1816_Y - connect \Y $pos$libresoc.v:42410$1817_Y + connect \A $extend$libresoc.v:42213$1815_Y + connect \Y $pos$libresoc.v:42213$1816_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $pos $pos$libresoc.v:42418$1826 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" + cell $pos $pos$libresoc.v:42221$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42418$1825_Y - connect \Y $pos$libresoc.v:42418$1826_Y + connect \A $extend$libresoc.v:42221$1824_Y + connect \Y $pos$libresoc.v:42221$1825_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42691$2100 + cell $pos $pos$libresoc.v:42494$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42691$2099_Y - connect \Y $pos$libresoc.v:42691$2100_Y + connect \A $extend$libresoc.v:42494$2098_Y + connect \Y $pos$libresoc.v:42494$2099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42716$2126 + cell $pos $pos$libresoc.v:42519$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42716$2125_Y - connect \Y $pos$libresoc.v:42716$2126_Y + connect \A $extend$libresoc.v:42519$2124_Y + connect \Y $pos$libresoc.v:42519$2125_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42427$1835 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42230$1834 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$182 - connect \Y $reduce_or$libresoc.v:42427$1835_Y + connect \Y $reduce_or$libresoc.v:42230$1834_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42429$1837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42232$1836 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$186 - connect \Y $reduce_or$libresoc.v:42429$1837_Y + connect \Y $reduce_or$libresoc.v:42232$1836_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42431$1839 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42234$1838 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$190 - connect \Y $reduce_or$libresoc.v:42431$1839_Y + connect \Y $reduce_or$libresoc.v:42234$1838_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42433$1841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42236$1840 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$194 - connect \Y $reduce_or$libresoc.v:42433$1841_Y + connect \Y $reduce_or$libresoc.v:42236$1840_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42435$1843 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42238$1842 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$198 - connect \Y $reduce_or$libresoc.v:42435$1843_Y + connect \Y $reduce_or$libresoc.v:42238$1842_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42437$1845 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42240$1844 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$202 - connect \Y $reduce_or$libresoc.v:42437$1845_Y + connect \Y $reduce_or$libresoc.v:42240$1844_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42439$1847 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42242$1846 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$206 - connect \Y $reduce_or$libresoc.v:42439$1847_Y + connect \Y $reduce_or$libresoc.v:42242$1846_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42441$1849 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42244$1848 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$210 - connect \Y $reduce_or$libresoc.v:42441$1849_Y + connect \Y $reduce_or$libresoc.v:42244$1848_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42443$1851 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42246$1850 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$214 - connect \Y $reduce_or$libresoc.v:42443$1851_Y + connect \Y $reduce_or$libresoc.v:42246$1850_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42445$1853 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + cell $reduce_or $reduce_or$libresoc.v:42248$1852 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$218 - connect \Y $reduce_or$libresoc.v:42445$1853_Y + connect \Y $reduce_or$libresoc.v:42248$1852_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" - cell $reduce_or $reduce_or$libresoc.v:42573$1981 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" + cell $reduce_or $reduce_or$libresoc.v:42446$2050 parameter \A_SIGNED 0 - parameter \A_WIDTH 9 + parameter \A_WIDTH 19 parameter \Y_WIDTH 1 - connect \A { \rp_INT_ra_ldst0_8 \rp_INT_ra_shiftrot0_7 \rp_INT_ra_mul0_6 \rp_INT_ra_div0_5 \rp_INT_ra_spr0_4 \rp_INT_ra_logical0_3 \rp_INT_ra_trap0_2 \rp_INT_ra_cr0_1 \rp_INT_ra_alu0_0 } - connect \Y $reduce_or$libresoc.v:42573$1981_Y + connect \A { \rp_INT_rabc_ldst0_18 \rp_INT_rabc_shiftrot0_17 \rp_INT_rabc_mul0_16 \rp_INT_rabc_div0_15 \rp_INT_rabc_spr0_14 \rp_INT_rabc_logical0_13 \rp_INT_rabc_trap0_12 \rp_INT_rabc_cr0_11 \rp_INT_rabc_alu0_10 \rp_INT_rabc_ldst0_9 \rp_INT_rabc_shiftrot0_8 \rp_INT_rabc_ldst0_7 \rp_INT_rabc_shiftrot0_6 \rp_INT_rabc_mul0_5 \rp_INT_rabc_div0_4 \rp_INT_rabc_logical0_3 \rp_INT_rabc_trap0_2 \rp_INT_rabc_cr0_1 \rp_INT_rabc_alu0_0 } + connect \Y $reduce_or$libresoc.v:42446$2050_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" - cell $reduce_or $reduce_or$libresoc.v:42629$2037 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" + cell $reduce_or $reduce_or$libresoc.v:42603$2209 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \rp_INT_rb_ldst0_7 \rp_INT_rb_shiftrot0_6 \rp_INT_rb_mul0_5 \rp_INT_rb_div0_4 \rp_INT_rb_logical0_3 \rp_INT_rb_trap0_2 \rp_INT_rb_cr0_1 \rp_INT_rb_alu0_0 } - connect \Y $reduce_or$libresoc.v:42629$2037_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" - cell $reduce_or $reduce_or$libresoc.v:42643$2051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \rp_INT_rc_ldst0_1 \rp_INT_rc_shiftrot0_0 } - connect \Y $reduce_or$libresoc.v:42643$2051_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" - cell $reduce_or $reduce_or$libresoc.v:42786$2196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 } - connect \Y $reduce_or$libresoc.v:42786$2196_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" - cell $reduce_or $reduce_or$libresoc.v:42800$2210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 5 parameter \Y_WIDTH 1 - connect \A { \rp_FAST_fast2_trap0_1 \rp_FAST_fast2_branch0_0 } - connect \Y $reduce_or$libresoc.v:42800$2210_Y + connect \A { \rp_FAST_fast1_trap0_4 \rp_FAST_fast1_branch0_3 \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 } + connect \Y $reduce_or$libresoc.v:42603$2209_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" - cell $reduce_or $reduce_or$libresoc.v:42807$2217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" + cell $reduce_or $reduce_or$libresoc.v:42610$2216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rp_SPR_spr1_spr0_0 - connect \Y $reduce_or$libresoc.v:42807$2217_Y + connect \Y $reduce_or$libresoc.v:42610$2216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42199$1602 + cell $sshl $sshl$libresoc.v:42002$1601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1259 - connect \Y $sshl$libresoc.v:42199$1602_Y + connect \B \$1257 + connect \Y $sshl$libresoc.v:42002$1601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42207$1610 + cell $sshl $sshl$libresoc.v:42010$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1279 - connect \Y $sshl$libresoc.v:42207$1610_Y + connect \B \$1277 + connect \Y $sshl$libresoc.v:42010$1609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42215$1618 + cell $sshl $sshl$libresoc.v:42018$1617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1299 - connect \Y $sshl$libresoc.v:42215$1618_Y + connect \B \$1297 + connect \Y $sshl$libresoc.v:42018$1617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42223$1626 + cell $sshl $sshl$libresoc.v:42026$1625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1319 - connect \Y $sshl$libresoc.v:42223$1626_Y + connect \B \$1317 + connect \Y $sshl$libresoc.v:42026$1625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42231$1634 + cell $sshl $sshl$libresoc.v:42034$1633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1339 - connect \Y $sshl$libresoc.v:42231$1634_Y + connect \B \$1337 + connect \Y $sshl$libresoc.v:42034$1633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42239$1642 + cell $sshl $sshl$libresoc.v:42042$1641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1359 - connect \Y $sshl$libresoc.v:42239$1642_Y + connect \B \$1357 + connect \Y $sshl$libresoc.v:42042$1641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$libresoc.v:42739$2149 + cell $sshl $sshl$libresoc.v:42542$2148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$809 - connect \Y $sshl$libresoc.v:42739$2149_Y + connect \B \$807 + connect \Y $sshl$libresoc.v:42542$2148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$libresoc.v:42747$2157 + cell $sshl $sshl$libresoc.v:42550$2156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$825 - connect \Y $sshl$libresoc.v:42747$2157_Y + connect \B \$823 + connect \Y $sshl$libresoc.v:42550$2156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sshl $sshl$libresoc.v:42756$2166 + cell $sshl $sshl$libresoc.v:42559$2165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$844 - connect \Y $sshl$libresoc.v:42756$2166_Y + connect \B \$842 + connect \Y $sshl$libresoc.v:42559$2165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sshl $sshl$libresoc.v:42764$2174 + cell $sshl $sshl$libresoc.v:42567$2173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$860 - connect \Y $sshl$libresoc.v:42764$2174_Y + connect \B \$858 + connect \Y $sshl$libresoc.v:42567$2173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42198$1601 + cell $sub $sub$libresoc.v:42001$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73007,10 +72808,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42198$1601_Y + connect \Y $sub$libresoc.v:42001$1600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42206$1609 + cell $sub $sub$libresoc.v:42009$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73018,10 +72819,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42206$1609_Y + connect \Y $sub$libresoc.v:42009$1608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42214$1617 + cell $sub $sub$libresoc.v:42017$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73029,10 +72830,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42214$1617_Y + connect \Y $sub$libresoc.v:42017$1616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42222$1625 + cell $sub $sub$libresoc.v:42025$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73040,10 +72841,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42222$1625_Y + connect \Y $sub$libresoc.v:42025$1624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42230$1633 + cell $sub $sub$libresoc.v:42033$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73051,10 +72852,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42230$1633_Y + connect \Y $sub$libresoc.v:42033$1632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42238$1641 + cell $sub $sub$libresoc.v:42041$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73062,10 +72863,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42238$1641_Y + connect \Y $sub$libresoc.v:42041$1640_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" - cell $sub $sub$libresoc.v:42447$1855 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" + cell $sub $sub$libresoc.v:42250$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -73073,10 +72874,10 @@ module \core parameter \Y_WIDTH 3 connect \A \counter connect \B 1'1 - connect \Y $sub$libresoc.v:42447$1855_Y + connect \Y $sub$libresoc.v:42250$1854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$libresoc.v:42738$2148 + cell $sub $sub$libresoc.v:42541$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73084,10 +72885,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in1 - connect \Y $sub$libresoc.v:42738$2148_Y + connect \Y $sub$libresoc.v:42541$2147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$libresoc.v:42746$2156 + cell $sub $sub$libresoc.v:42549$2155 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73095,10 +72896,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in1 - connect \Y $sub$libresoc.v:42746$2156_Y + connect \Y $sub$libresoc.v:42549$2155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sub $sub$libresoc.v:42755$2165 + cell $sub $sub$libresoc.v:42558$2164 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73106,10 +72907,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in2 - connect \Y $sub$libresoc.v:42755$2165_Y + connect \Y $sub$libresoc.v:42558$2164_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sub $sub$libresoc.v:42763$2173 + cell $sub $sub$libresoc.v:42566$2172 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73117,626 +72918,626 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in2$1 - connect \Y $sub$libresoc.v:42763$2173_Y + connect \Y $sub$libresoc.v:42566$2172_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42104$1507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41907$1506 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$999 - connect \Y $ternary$libresoc.v:42104$1507_Y + connect \S \wp$997 + connect \Y $ternary$libresoc.v:41907$1506_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42110$1513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41913$1512 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1020 - connect \Y $ternary$libresoc.v:42110$1513_Y + connect \S \wp$1018 + connect \Y $ternary$libresoc.v:41913$1512_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42116$1519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41919$1518 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1038 - connect \Y $ternary$libresoc.v:42116$1519_Y + connect \S \wp$1036 + connect \Y $ternary$libresoc.v:41919$1518_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42122$1525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41925$1524 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1060 - connect \Y $ternary$libresoc.v:42122$1525_Y + connect \S \wp$1058 + connect \Y $ternary$libresoc.v:41925$1524_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42128$1531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41931$1530 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1080 - connect \Y $ternary$libresoc.v:42128$1531_Y + connect \S \wp$1078 + connect \Y $ternary$libresoc.v:41931$1530_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42134$1537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41937$1536 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1100 - connect \Y $ternary$libresoc.v:42134$1537_Y + connect \S \wp$1098 + connect \Y $ternary$libresoc.v:41937$1536_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42140$1543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41943$1542 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1119 - connect \Y $ternary$libresoc.v:42140$1543_Y + connect \S \wp$1117 + connect \Y $ternary$libresoc.v:41943$1542_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42146$1549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41949$1548 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1137 - connect \Y $ternary$libresoc.v:42146$1549_Y + connect \S \wp$1135 + connect \Y $ternary$libresoc.v:41949$1548_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42152$1555 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41955$1554 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_ea - connect \S \wp$1153 - connect \Y $ternary$libresoc.v:42152$1555_Y + connect \S \wp$1151 + connect \Y $ternary$libresoc.v:41955$1554_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42186$1589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:41989$1588 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_wr - connect \S \wp$1227 - connect \Y $ternary$libresoc.v:42186$1589_Y + connect \S \wp$1225 + connect \Y $ternary$libresoc.v:41989$1588_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42200$1603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42003$1602 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$1261 - connect \S \wp$1255 - connect \Y $ternary$libresoc.v:42200$1603_Y + connect \B \$1259 + connect \S \wp$1253 + connect \Y $ternary$libresoc.v:42003$1602_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42208$1611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42011$1610 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$1281 - connect \S \wp$1275 - connect \Y $ternary$libresoc.v:42208$1611_Y + connect \B \$1279 + connect \S \wp$1273 + connect \Y $ternary$libresoc.v:42011$1610_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42216$1619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42019$1618 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$1301 - connect \S \wp$1295 - connect \Y $ternary$libresoc.v:42216$1619_Y + connect \B \$1299 + connect \S \wp$1293 + connect \Y $ternary$libresoc.v:42019$1618_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42224$1627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42027$1626 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$1321 - connect \S \wp$1315 - connect \Y $ternary$libresoc.v:42224$1627_Y + connect \B \$1319 + connect \S \wp$1313 + connect \Y $ternary$libresoc.v:42027$1626_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42232$1635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42035$1634 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$1341 - connect \S \wp$1335 - connect \Y $ternary$libresoc.v:42232$1635_Y + connect \B \$1339 + connect \S \wp$1333 + connect \Y $ternary$libresoc.v:42035$1634_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42240$1643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42043$1642 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$1361 - connect \S \wp$1355 - connect \Y $ternary$libresoc.v:42240$1643_Y + connect \B \$1359 + connect \S \wp$1353 + connect \Y $ternary$libresoc.v:42043$1642_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42259$1662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42062$1661 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1402 - connect \Y $ternary$libresoc.v:42259$1662_Y + connect \S \wp$1400 + connect \Y $ternary$libresoc.v:42062$1661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42265$1668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42068$1667 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1418 - connect \Y $ternary$libresoc.v:42265$1668_Y + connect \S \wp$1416 + connect \Y $ternary$libresoc.v:42068$1667_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42271$1674 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42074$1673 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1434 - connect \Y $ternary$libresoc.v:42271$1674_Y + connect \S \wp$1432 + connect \Y $ternary$libresoc.v:42074$1673_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42286$1690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42089$1689 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1468 - connect \Y $ternary$libresoc.v:42286$1690_Y + connect \S \wp$1466 + connect \Y $ternary$libresoc.v:42089$1689_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42292$1696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42095$1695 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1484 - connect \Y $ternary$libresoc.v:42292$1696_Y + connect \S \wp$1482 + connect \Y $ternary$libresoc.v:42095$1695_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42298$1702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42101$1701 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1500 - connect \Y $ternary$libresoc.v:42298$1702_Y + connect \S \wp$1498 + connect \Y $ternary$libresoc.v:42101$1701_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42304$1708 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42107$1707 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1516 - connect \Y $ternary$libresoc.v:42304$1708_Y + connect \S \wp$1514 + connect \Y $ternary$libresoc.v:42107$1707_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42320$1724 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42123$1723 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1552 - connect \Y $ternary$libresoc.v:42320$1724_Y + connect \S \wp$1550 + connect \Y $ternary$libresoc.v:42123$1723_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42326$1730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42129$1729 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1568 - connect \Y $ternary$libresoc.v:42326$1730_Y + connect \S \wp$1566 + connect \Y $ternary$libresoc.v:42129$1729_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42332$1736 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42135$1735 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1584 - connect \Y $ternary$libresoc.v:42332$1736_Y + connect \S \wp$1582 + connect \Y $ternary$libresoc.v:42135$1735_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42338$1742 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42141$1741 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1600 - connect \Y $ternary$libresoc.v:42338$1742_Y + connect \S \wp$1598 + connect \Y $ternary$libresoc.v:42141$1741_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42357$1763 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42160$1762 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 - connect \S \wp$1645 - connect \Y $ternary$libresoc.v:42357$1763_Y + connect \S \wp$1643 + connect \Y $ternary$libresoc.v:42160$1762_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42363$1769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42166$1768 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 - connect \S \wp$1661 - connect \Y $ternary$libresoc.v:42363$1769_Y + connect \S \wp$1659 + connect \Y $ternary$libresoc.v:42166$1768_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42369$1775 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42172$1774 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 - connect \S \wp$1677 - connect \Y $ternary$libresoc.v:42369$1775_Y + connect \S \wp$1675 + connect \Y $ternary$libresoc.v:42172$1774_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42375$1781 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42178$1780 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 - connect \S \wp$1693 - connect \Y $ternary$libresoc.v:42375$1781_Y + connect \S \wp$1691 + connect \Y $ternary$libresoc.v:42178$1780_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42381$1787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42184$1786 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 - connect \S \wp$1709 - connect \Y $ternary$libresoc.v:42381$1787_Y + connect \S \wp$1707 + connect \Y $ternary$libresoc.v:42184$1786_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42401$1807 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42204$1806 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1753 - connect \Y $ternary$libresoc.v:42401$1807_Y + connect \S \wp$1751 + connect \Y $ternary$libresoc.v:42204$1806_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42407$1813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42210$1812 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1769 - connect \Y $ternary$libresoc.v:42407$1813_Y + connect \S \wp$1767 + connect \Y $ternary$libresoc.v:42210$1812_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42417$1824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42220$1823 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1793 - connect \Y $ternary$libresoc.v:42417$1824_Y + connect \S \wp$1791 + connect \Y $ternary$libresoc.v:42220$1823_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42425$1833 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42228$1832 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spro - connect \S \wp$1813 - connect \Y $ternary$libresoc.v:42425$1833_Y + connect \S \wp$1811 + connect \Y $ternary$libresoc.v:42228$1832_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42516$1924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42319$1923 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg1 - connect \S \rp_INT_ra_alu0_0 - connect \Y $ternary$libresoc.v:42516$1924_Y + connect \B \core_reg2 + connect \S \rp_INT_rabc_alu0_0 + connect \Y $ternary$libresoc.v:42319$1923_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42522$1930 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42325$1929 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg1 - connect \S \rp_INT_ra_cr0_1 - connect \Y $ternary$libresoc.v:42522$1930_Y + connect \B \core_reg2 + connect \S \rp_INT_rabc_cr0_1 + connect \Y $ternary$libresoc.v:42325$1929_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42528$1936 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42331$1935 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg1 - connect \S \rp_INT_ra_trap0_2 - connect \Y $ternary$libresoc.v:42528$1936_Y + connect \B \core_reg2 + connect \S \rp_INT_rabc_trap0_2 + connect \Y $ternary$libresoc.v:42331$1935_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42534$1942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42337$1941 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg1 - connect \S \rp_INT_ra_logical0_3 - connect \Y $ternary$libresoc.v:42534$1942_Y + connect \B \core_reg2 + connect \S \rp_INT_rabc_logical0_3 + connect \Y $ternary$libresoc.v:42337$1941_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42540$1948 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42343$1947 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg1 - connect \S \rp_INT_ra_spr0_4 - connect \Y $ternary$libresoc.v:42540$1948_Y + connect \B \core_reg2 + connect \S \rp_INT_rabc_div0_4 + connect \Y $ternary$libresoc.v:42343$1947_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42546$1954 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42349$1953 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg1 - connect \S \rp_INT_ra_div0_5 - connect \Y $ternary$libresoc.v:42546$1954_Y + connect \B \core_reg2 + connect \S \rp_INT_rabc_mul0_5 + connect \Y $ternary$libresoc.v:42349$1953_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42552$1960 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42355$1959 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg1 - connect \S \rp_INT_ra_mul0_6 - connect \Y $ternary$libresoc.v:42552$1960_Y + connect \B \core_reg2 + connect \S \rp_INT_rabc_shiftrot0_6 + connect \Y $ternary$libresoc.v:42355$1959_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42558$1966 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42361$1965 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg1 - connect \S \rp_INT_ra_shiftrot0_7 - connect \Y $ternary$libresoc.v:42558$1966_Y + connect \B \core_reg2 + connect \S \rp_INT_rabc_ldst0_7 + connect \Y $ternary$libresoc.v:42361$1965_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42564$1972 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42367$1971 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg1 - connect \S \rp_INT_ra_ldst0_8 - connect \Y $ternary$libresoc.v:42564$1972_Y + connect \B \core_reg3 + connect \S \rp_INT_rabc_shiftrot0_8 + connect \Y $ternary$libresoc.v:42367$1971_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42579$1987 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42373$1977 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg2 - connect \S \rp_INT_rb_alu0_0 - connect \Y $ternary$libresoc.v:42579$1987_Y + connect \B \core_reg3 + connect \S \rp_INT_rabc_ldst0_9 + connect \Y $ternary$libresoc.v:42373$1977_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42585$1993 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42379$1983 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg2 - connect \S \rp_INT_rb_cr0_1 - connect \Y $ternary$libresoc.v:42585$1993_Y + connect \B \core_reg1 + connect \S \rp_INT_rabc_alu0_10 + connect \Y $ternary$libresoc.v:42379$1983_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42591$1999 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42385$1989 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg2 - connect \S \rp_INT_rb_trap0_2 - connect \Y $ternary$libresoc.v:42591$1999_Y + connect \B \core_reg1 + connect \S \rp_INT_rabc_cr0_11 + connect \Y $ternary$libresoc.v:42385$1989_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42597$2005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42391$1995 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg2 - connect \S \rp_INT_rb_logical0_3 - connect \Y $ternary$libresoc.v:42597$2005_Y + connect \B \core_reg1 + connect \S \rp_INT_rabc_trap0_12 + connect \Y $ternary$libresoc.v:42391$1995_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42603$2011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42397$2001 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg2 - connect \S \rp_INT_rb_div0_4 - connect \Y $ternary$libresoc.v:42603$2011_Y + connect \B \core_reg1 + connect \S \rp_INT_rabc_logical0_13 + connect \Y $ternary$libresoc.v:42397$2001_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42609$2017 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42403$2007 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg2 - connect \S \rp_INT_rb_mul0_5 - connect \Y $ternary$libresoc.v:42609$2017_Y + connect \B \core_reg1 + connect \S \rp_INT_rabc_spr0_14 + connect \Y $ternary$libresoc.v:42403$2007_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42615$2023 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42409$2013 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg2 - connect \S \rp_INT_rb_shiftrot0_6 - connect \Y $ternary$libresoc.v:42615$2023_Y + connect \B \core_reg1 + connect \S \rp_INT_rabc_div0_15 + connect \Y $ternary$libresoc.v:42409$2013_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42621$2029 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42415$2019 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg2 - connect \S \rp_INT_rb_ldst0_7 - connect \Y $ternary$libresoc.v:42621$2029_Y + connect \B \core_reg1 + connect \S \rp_INT_rabc_mul0_16 + connect \Y $ternary$libresoc.v:42415$2019_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42635$2043 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42421$2025 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg3 - connect \S \rp_INT_rc_shiftrot0_0 - connect \Y $ternary$libresoc.v:42635$2043_Y + connect \B \core_reg1 + connect \S \rp_INT_rabc_shiftrot0_17 + connect \Y $ternary$libresoc.v:42421$2025_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42641$2049 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42427$2031 parameter \WIDTH 7 connect \A 7'0000000 - connect \B \core_reg3 - connect \S \rp_INT_rc_ldst0_1 - connect \Y $ternary$libresoc.v:42641$2049_Y + connect \B \core_reg1 + connect \S \rp_INT_rabc_ldst0_18 + connect \Y $ternary$libresoc.v:42427$2031_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42655$2063 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42458$2062 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_alu0_0 - connect \Y $ternary$libresoc.v:42655$2063_Y + connect \Y $ternary$libresoc.v:42458$2062_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42661$2069 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42464$2068 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_logical0_1 - connect \Y $ternary$libresoc.v:42661$2069_Y + connect \Y $ternary$libresoc.v:42464$2068_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42667$2075 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42470$2074 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_spr0_2 - connect \Y $ternary$libresoc.v:42667$2075_Y + connect \Y $ternary$libresoc.v:42470$2074_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42673$2081 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42476$2080 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_div0_3 - connect \Y $ternary$libresoc.v:42673$2081_Y + connect \Y $ternary$libresoc.v:42476$2080_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42679$2087 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42482$2086 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_mul0_4 - connect \Y $ternary$libresoc.v:42679$2087_Y + connect \Y $ternary$libresoc.v:42482$2086_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42685$2093 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42488$2092 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_shiftrot0_5 - connect \Y $ternary$libresoc.v:42685$2093_Y + connect \Y $ternary$libresoc.v:42488$2092_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42701$2110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42504$2109 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_alu0_0 - connect \Y $ternary$libresoc.v:42701$2110_Y + connect \Y $ternary$libresoc.v:42504$2109_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42707$2116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42510$2115 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_spr0_1 - connect \Y $ternary$libresoc.v:42707$2116_Y + connect \Y $ternary$libresoc.v:42510$2115_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42713$2122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42516$2121 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_shiftrot0_2 - connect \Y $ternary$libresoc.v:42713$2122_Y + connect \Y $ternary$libresoc.v:42516$2121_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42726$2136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42529$2135 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \rp_XER_xer_ov_spr0_0 - connect \Y $ternary$libresoc.v:42726$2136_Y + connect \Y $ternary$libresoc.v:42529$2135_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42732$2142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42535$2141 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_rd connect \S \rp_CR_full_cr_cr0_0 - connect \Y $ternary$libresoc.v:42732$2142_Y + connect \Y $ternary$libresoc.v:42535$2141_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42740$2150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42543$2149 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$811 + connect \B \$809 connect \S \rp_CR_cr_a_cr0_0 - connect \Y $ternary$libresoc.v:42740$2150_Y + connect \Y $ternary$libresoc.v:42543$2149_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42748$2158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42551$2157 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$827 + connect \B \$825 connect \S \rp_CR_cr_a_branch0_1 - connect \Y $ternary$libresoc.v:42748$2158_Y + connect \Y $ternary$libresoc.v:42551$2157_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42757$2167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42560$2166 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$846 + connect \B \$844 connect \S \rp_CR_cr_b_cr0_0 - connect \Y $ternary$libresoc.v:42757$2167_Y + connect \Y $ternary$libresoc.v:42560$2166_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42765$2175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42568$2174 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$862 + connect \B \$860 connect \S \rp_CR_cr_c_cr0_0 - connect \Y $ternary$libresoc.v:42765$2175_Y + connect \Y $ternary$libresoc.v:42568$2174_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42771$2181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42574$2180 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_branch0_0 - connect \Y $ternary$libresoc.v:42771$2181_Y + connect \Y $ternary$libresoc.v:42574$2180_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42777$2187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42580$2186 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_trap0_1 - connect \Y $ternary$libresoc.v:42777$2187_Y + connect \Y $ternary$libresoc.v:42580$2186_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42783$2193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42586$2192 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_spr0_2 - connect \Y $ternary$libresoc.v:42783$2193_Y + connect \Y $ternary$libresoc.v:42586$2192_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42792$2202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42592$2198 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 - connect \S \rp_FAST_fast2_branch0_0 - connect \Y $ternary$libresoc.v:42792$2202_Y + connect \S \rp_FAST_fast1_branch0_3 + connect \Y $ternary$libresoc.v:42592$2198_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42798$2208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42598$2204 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 - connect \S \rp_FAST_fast2_trap0_1 - connect \Y $ternary$libresoc.v:42798$2208_Y + connect \S \rp_FAST_fast1_trap0_4 + connect \Y $ternary$libresoc.v:42598$2204_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42806$2216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" + cell $mux $ternary$libresoc.v:42609$2215 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spr1 connect \S \rp_SPR_spr1_spr0_0 - connect \Y $ternary$libresoc.v:42806$2216_Y + connect \Y $ternary$libresoc.v:42609$2215_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42823$2233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" + cell $mux $ternary$libresoc.v:42626$2232 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp - connect \Y $ternary$libresoc.v:42823$2233_Y + connect \Y $ternary$libresoc.v:42626$2232_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:42986.6-43003.4" + attribute \src "libresoc.v:42790.6-42807.4" cell \cr \cr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73756,7 +73557,7 @@ module \core connect \wen \cr_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43004.11-43026.4" + attribute \src "libresoc.v:42808.11-42830.4" cell \dec_ALU \dec_ALU connect \ALU__data_len \dec_ALU_ALU__data_len connect \ALU__fn_unit \dec_ALU_ALU__fn_unit @@ -73781,7 +73582,7 @@ module \core connect \sv_a_nz \dec_ALU_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:43027.14-43039.4" + attribute \src "libresoc.v:42831.14-42843.4" cell \dec_BRANCH \dec_BRANCH connect \BRANCH__cia \dec_BRANCH_BRANCH__cia connect \BRANCH__fn_unit \dec_BRANCH_BRANCH__fn_unit @@ -73796,7 +73597,7 @@ module \core connect \raw_opcode_in \dec_BRANCH_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43040.10-43046.4" + attribute \src "libresoc.v:42844.10-42850.4" cell \dec_CR \dec_CR connect \CR__fn_unit \dec_CR_CR__fn_unit connect \CR__insn \dec_CR_CR__insn @@ -73805,7 +73606,7 @@ module \core connect \raw_opcode_in \dec_CR_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43047.11-43069.4" + attribute \src "libresoc.v:42851.11-42873.4" cell \dec_DIV \dec_DIV connect \DIV__data_len \dec_DIV_DIV__data_len connect \DIV__fn_unit \dec_DIV_DIV__fn_unit @@ -73830,7 +73631,7 @@ module \core connect \sv_a_nz \dec_DIV_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:43070.12-43090.4" + attribute \src "libresoc.v:42874.12-42894.4" cell \dec_LDST \dec_LDST connect \LDST__byte_reverse \dec_LDST_LDST__byte_reverse connect \LDST__data_len \dec_LDST_LDST__data_len @@ -73853,7 +73654,7 @@ module \core connect \sv_a_nz \dec_LDST_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:43091.15-43113.4" + attribute \src "libresoc.v:42895.15-42917.4" cell \dec_LOGICAL \dec_LOGICAL connect \LOGICAL__data_len \dec_LOGICAL_LOGICAL__data_len connect \LOGICAL__fn_unit \dec_LOGICAL_LOGICAL__fn_unit @@ -73878,7 +73679,7 @@ module \core connect \sv_a_nz \dec_LOGICAL_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:43114.11-43129.4" + attribute \src "libresoc.v:42918.11-42933.4" cell \dec_MUL \dec_MUL connect \MUL__fn_unit \dec_MUL_MUL__fn_unit connect \MUL__imm_data__data \dec_MUL_MUL__imm_data__data @@ -73896,7 +73697,7 @@ module \core connect \raw_opcode_in \dec_MUL_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43130.17-43150.4" + attribute \src "libresoc.v:42934.17-42954.4" cell \dec_SHIFT_ROT \dec_SHIFT_ROT connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT__fn_unit connect \SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data @@ -73919,7 +73720,7 @@ module \core connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43151.11-43158.4" + attribute \src "libresoc.v:42955.11-42962.4" cell \dec_SPR \dec_SPR connect \SPR__fn_unit \dec_SPR_SPR__fn_unit connect \SPR__insn \dec_SPR_SPR__insn @@ -73929,7 +73730,7 @@ module \core connect \raw_opcode_in \dec_SPR_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43159.8-43177.4" + attribute \src "libresoc.v:42963.8-42978.4" cell \fast \fast connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73945,12 +73746,9 @@ module \core connect \src1__addr \fast_src1__addr connect \src1__data_o \fast_src1__data_o connect \src1__ren \fast_src1__ren - connect \src2__addr \fast_src2__addr - connect \src2__data_o \fast_src2__data_o - connect \src2__ren \fast_src2__ren end attribute \module_not_derived 1 - attribute \src "libresoc.v:43178.7-43509.4" + attribute \src "libresoc.v:42979.7-43310.4" cell \fus \fus connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73990,7 +73788,7 @@ module \core connect \cu_rd__go_i$41 \fus_cu_rd__go_i$53 connect \cu_rd__go_i$44 \fus_cu_rd__go_i$56 connect \cu_rd__go_i$47 \fus_cu_rd__go_i$59 - connect \cu_rd__go_i$50 \fus_cu_rd__go_i$62 + connect \cu_rd__go_i$54 \fus_cu_rd__go_i$66 connect \cu_rd__go_i$70 \fus_cu_rd__go_i$82 connect \cu_rd__rel_o \fus_cu_rd__rel_o connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$40 @@ -74000,7 +73798,7 @@ module \core connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$52 connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$55 connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$58 - connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$61 + connect \cu_rd__rel_o$53 \fus_cu_rd__rel_o$65 connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$81 connect \cu_rdmaskn_i \fus_cu_rdmaskn_i connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$24 @@ -74232,27 +74030,27 @@ module \core connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a connect \spr1_ok \fus_spr1_ok connect \src1_i \fus_src1_i - connect \src1_i$30 \fus_src1_i$42 - connect \src1_i$33 \fus_src1_i$45 - connect \src1_i$36 \fus_src1_i$48 - connect \src1_i$39 \fus_src1_i$51 - connect \src1_i$42 \fus_src1_i$54 - connect \src1_i$45 \fus_src1_i$57 - connect \src1_i$48 \fus_src1_i$60 + connect \src1_i$50 \fus_src1_i$62 connect \src1_i$51 \fus_src1_i$63 + connect \src1_i$52 \fus_src1_i$64 + connect \src1_i$55 \fus_src1_i$67 + connect \src1_i$56 \fus_src1_i$68 + connect \src1_i$57 \fus_src1_i$69 + connect \src1_i$58 \fus_src1_i$70 + connect \src1_i$59 \fus_src1_i$71 connect \src1_i$74 \fus_src1_i$86 connect \src2_i \fus_src2_i - connect \src2_i$52 \fus_src2_i$64 - connect \src2_i$53 \fus_src2_i$65 - connect \src2_i$54 \fus_src2_i$66 - connect \src2_i$55 \fus_src2_i$67 - connect \src2_i$56 \fus_src2_i$68 - connect \src2_i$57 \fus_src2_i$69 - connect \src2_i$58 \fus_src2_i$70 + connect \src2_i$30 \fus_src2_i$42 + connect \src2_i$33 \fus_src2_i$45 + connect \src2_i$36 \fus_src2_i$48 + connect \src2_i$39 \fus_src2_i$51 + connect \src2_i$42 \fus_src2_i$54 + connect \src2_i$45 \fus_src2_i$57 + connect \src2_i$48 \fus_src2_i$60 connect \src2_i$77 \fus_src2_i$89 connect \src2_i$79 \fus_src2_i$91 connect \src3_i \fus_src3_i - connect \src3_i$59 \fus_src3_i$71 + connect \src3_i$49 \fus_src3_i$61 connect \src3_i$60 \fus_src3_i$72 connect \src3_i$61 \fus_src3_i$73 connect \src3_i$62 \fus_src3_i$74 @@ -74284,7 +74082,7 @@ module \core connect \xer_so_ok$131 \fus_xer_so_ok$143 end attribute \module_not_derived 1 - attribute \src "libresoc.v:43510.9-43528.4" + attribute \src "libresoc.v:43311.9-43323.4" cell \int \int connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74294,18 +74092,12 @@ module \core connect \dmi__addr \dmi__addr connect \dmi__data_o \dmi__data_o connect \dmi__ren \dmi__ren - connect \src1__addr \int_src1__addr - connect \src1__data_o \int_src1__data_o - connect \src1__ren \int_src1__ren - connect \src2__addr \int_src2__addr - connect \src2__data_o \int_src2__data_o - connect \src2__ren \int_src2__ren - connect \src3__addr \int_src3__addr - connect \src3__data_o \int_src3__data_o - connect \src3__ren \int_src3__ren + connect \src__addr \int_src__addr + connect \src__data_o \int_src__data_o + connect \src__ren \int_src__ren end attribute \module_not_derived 1 - attribute \src "libresoc.v:43529.6-43561.4" + attribute \src "libresoc.v:43324.6-43356.4" cell \l0 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74340,98 +74132,77 @@ module \core connect \wb_dcache_en \wb_dcache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:43562.18-43566.4" + attribute \src "libresoc.v:43357.18-43361.4" cell \rdpick_CR_cr_a \rdpick_CR_cr_a connect \en_o \rdpick_CR_cr_a_en_o connect \i \rdpick_CR_cr_a_i connect \o \rdpick_CR_cr_a_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43567.18-43571.4" + attribute \src "libresoc.v:43362.18-43366.4" cell \rdpick_CR_cr_b \rdpick_CR_cr_b connect \en_o \rdpick_CR_cr_b_en_o connect \i \rdpick_CR_cr_b_i connect \o \rdpick_CR_cr_b_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43572.18-43576.4" + attribute \src "libresoc.v:43367.18-43371.4" cell \rdpick_CR_cr_c \rdpick_CR_cr_c connect \en_o \rdpick_CR_cr_c_en_o connect \i \rdpick_CR_cr_c_i connect \o \rdpick_CR_cr_c_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43577.21-43581.4" + attribute \src "libresoc.v:43372.21-43376.4" cell \rdpick_CR_full_cr \rdpick_CR_full_cr connect \en_o \rdpick_CR_full_cr_en_o connect \i \rdpick_CR_full_cr_i connect \o \rdpick_CR_full_cr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43582.21-43586.4" + attribute \src "libresoc.v:43377.21-43381.4" cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 connect \en_o \rdpick_FAST_fast1_en_o connect \i \rdpick_FAST_fast1_i connect \o \rdpick_FAST_fast1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43587.21-43591.4" - cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 - connect \en_o \rdpick_FAST_fast2_en_o - connect \i \rdpick_FAST_fast2_i - connect \o \rdpick_FAST_fast2_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43592.17-43596.4" - cell \rdpick_INT_ra \rdpick_INT_ra - connect \en_o \rdpick_INT_ra_en_o - connect \i \rdpick_INT_ra_i - connect \o \rdpick_INT_ra_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43597.17-43601.4" - cell \rdpick_INT_rb \rdpick_INT_rb - connect \en_o \rdpick_INT_rb_en_o - connect \i \rdpick_INT_rb_i - connect \o \rdpick_INT_rb_o + attribute \src "libresoc.v:43382.19-43386.4" + cell \rdpick_INT_rabc \rdpick_INT_rabc + connect \en_o \rdpick_INT_rabc_en_o + connect \i \rdpick_INT_rabc_i + connect \o \rdpick_INT_rabc_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43602.17-43606.4" - cell \rdpick_INT_rc \rdpick_INT_rc - connect \en_o \rdpick_INT_rc_en_o - connect \i \rdpick_INT_rc_i - connect \o \rdpick_INT_rc_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43607.19-43611.4" + attribute \src "libresoc.v:43387.19-43391.4" cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 connect \en_o \rdpick_SPR_spr1_en_o connect \i \rdpick_SPR_spr1_i connect \o \rdpick_SPR_spr1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43612.21-43616.4" + attribute \src "libresoc.v:43392.21-43396.4" cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca connect \en_o \rdpick_XER_xer_ca_en_o connect \i \rdpick_XER_xer_ca_i connect \o \rdpick_XER_xer_ca_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43617.21-43621.4" + attribute \src "libresoc.v:43397.21-43401.4" cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov connect \en_o \rdpick_XER_xer_ov_en_o connect \i \rdpick_XER_xer_ov_i connect \o \rdpick_XER_xer_ov_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43622.21-43626.4" + attribute \src "libresoc.v:43402.21-43406.4" cell \rdpick_XER_xer_so \rdpick_XER_xer_so connect \en_o \rdpick_XER_xer_so_en_o connect \i \rdpick_XER_xer_so_i connect \o \rdpick_XER_xer_so_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43627.7-43636.4" + attribute \src "libresoc.v:43407.7-43416.4" cell \spr \spr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74443,7 +74214,7 @@ module \core connect \spr1__wen \spr_spr1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43637.9-43654.4" + attribute \src "libresoc.v:43417.9-43434.4" cell \state \state connect \cia__data_o \cia__data_o connect \cia__ren \cia__ren @@ -74463,77 +74234,77 @@ module \core connect \wen$5 \state_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43655.18-43659.4" + attribute \src "libresoc.v:43435.18-43439.4" cell \wrpick_CR_cr_a \wrpick_CR_cr_a connect \en_o \wrpick_CR_cr_a_en_o connect \i \wrpick_CR_cr_a_i connect \o \wrpick_CR_cr_a_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43660.21-43664.4" + attribute \src "libresoc.v:43440.21-43444.4" cell \wrpick_CR_full_cr \wrpick_CR_full_cr connect \en_o \wrpick_CR_full_cr_en_o connect \i \wrpick_CR_full_cr_i connect \o \wrpick_CR_full_cr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43665.21-43669.4" + attribute \src "libresoc.v:43445.21-43449.4" cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 connect \en_o \wrpick_FAST_fast1_en_o connect \i \wrpick_FAST_fast1_i connect \o \wrpick_FAST_fast1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43670.16-43674.4" + attribute \src "libresoc.v:43450.16-43454.4" cell \wrpick_INT_o \wrpick_INT_o connect \en_o \wrpick_INT_o_en_o connect \i \wrpick_INT_o_i connect \o \wrpick_INT_o_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43675.19-43679.4" + attribute \src "libresoc.v:43455.19-43459.4" cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 connect \en_o \wrpick_SPR_spr1_en_o connect \i \wrpick_SPR_spr1_i connect \o \wrpick_SPR_spr1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43680.20-43684.4" + attribute \src "libresoc.v:43460.20-43464.4" cell \wrpick_STATE_msr \wrpick_STATE_msr connect \en_o \wrpick_STATE_msr_en_o connect \i \wrpick_STATE_msr_i connect \o \wrpick_STATE_msr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43685.20-43689.4" + attribute \src "libresoc.v:43465.20-43469.4" cell \wrpick_STATE_nia \wrpick_STATE_nia connect \en_o \wrpick_STATE_nia_en_o connect \i \wrpick_STATE_nia_i connect \o \wrpick_STATE_nia_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43690.21-43694.4" + attribute \src "libresoc.v:43470.21-43474.4" cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca connect \en_o \wrpick_XER_xer_ca_en_o connect \i \wrpick_XER_xer_ca_i connect \o \wrpick_XER_xer_ca_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43695.21-43699.4" + attribute \src "libresoc.v:43475.21-43479.4" cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov connect \en_o \wrpick_XER_xer_ov_en_o connect \i \wrpick_XER_xer_ov_i connect \o \wrpick_XER_xer_ov_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43700.21-43704.4" + attribute \src "libresoc.v:43480.21-43484.4" cell \wrpick_XER_xer_so \wrpick_XER_xer_so connect \en_o \wrpick_XER_xer_so_en_o connect \i \wrpick_XER_xer_so_i connect \o \wrpick_XER_xer_so_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43705.7-43722.4" + attribute \src "libresoc.v:43485.7-43502.4" cell \xer \xer connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74552,1217 +74323,1217 @@ module \core connect \wen$2 \xer_wen$171 connect \wen$4 \xer_wen$173 end - attribute \src "libresoc.v:36214.7-36214.20" - process $proc$libresoc.v:36214$2900 + attribute \src "libresoc.v:36262.7-36262.20" + process $proc$libresoc.v:36262$2900 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:38263.7-38263.30" - process $proc$libresoc.v:38263$2901 + attribute \src "libresoc.v:38103.7-38103.30" + process $proc$libresoc.v:38103$2901 assign { } { } assign $1\core_terminate_o[0:0] 1'0 sync always sync init update \core_terminate_o $1\core_terminate_o[0:0] end - attribute \src "libresoc.v:38276.13-38276.27" - process $proc$libresoc.v:38276$2902 + attribute \src "libresoc.v:38116.13-38116.27" + process $proc$libresoc.v:38116$2902 assign { } { } assign $1\counter[1:0] 2'00 sync always sync init update \counter $1\counter[1:0] end - attribute \src "libresoc.v:39443.7-39443.34" - process $proc$libresoc.v:39443$2903 + attribute \src "libresoc.v:39283.7-39283.34" + process $proc$libresoc.v:39283$2903 assign { } { } assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 sync always sync init update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] end - attribute \src "libresoc.v:39447.7-39447.30" - process $proc$libresoc.v:39447$2904 + attribute \src "libresoc.v:39287.7-39287.30" + process $proc$libresoc.v:39287$2904 assign { } { } assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] end - attribute \src "libresoc.v:39451.7-39451.30" - process $proc$libresoc.v:39451$2905 + attribute \src "libresoc.v:39291.7-39291.30" + process $proc$libresoc.v:39291$2905 assign { } { } assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] end - attribute \src "libresoc.v:39455.7-39455.30" - process $proc$libresoc.v:39455$2906 + attribute \src "libresoc.v:39295.7-39295.30" + process $proc$libresoc.v:39295$2906 assign { } { } assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] end - attribute \src "libresoc.v:39459.7-39459.33" - process $proc$libresoc.v:39459$2907 + attribute \src "libresoc.v:39299.7-39299.33" + process $proc$libresoc.v:39299$2907 assign { } { } assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] end - attribute \src "libresoc.v:39463.7-39463.37" - process $proc$libresoc.v:39463$2908 + attribute \src "libresoc.v:39303.7-39303.37" + process $proc$libresoc.v:39303$2908 assign { } { } assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 sync always sync init update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] end - attribute \src "libresoc.v:39467.7-39467.34" - process $proc$libresoc.v:39467$2909 + attribute \src "libresoc.v:39307.7-39307.37" + process $proc$libresoc.v:39307$2909 assign { } { } - assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 + assign $1\dp_FAST_fast1_branch0_3[0:0] 1'0 sync always sync init - update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] + update \dp_FAST_fast1_branch0_3 $1\dp_FAST_fast1_branch0_3[0:0] end - attribute \src "libresoc.v:39471.7-39471.35" - process $proc$libresoc.v:39471$2910 + attribute \src "libresoc.v:39311.7-39311.34" + process $proc$libresoc.v:39311$2910 assign { } { } - assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 + assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 sync always sync init - update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] + update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] end - attribute \src "libresoc.v:39475.7-39475.37" - process $proc$libresoc.v:39475$2911 + attribute \src "libresoc.v:39315.7-39315.35" + process $proc$libresoc.v:39315$2911 assign { } { } - assign $1\dp_FAST_fast2_branch0_0[0:0] 1'0 + assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 sync always sync init - update \dp_FAST_fast2_branch0_0 $1\dp_FAST_fast2_branch0_0[0:0] + update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] end - attribute \src "libresoc.v:39479.7-39479.35" - process $proc$libresoc.v:39479$2912 + attribute \src "libresoc.v:39319.7-39319.35" + process $proc$libresoc.v:39319$2912 assign { } { } - assign $1\dp_FAST_fast2_trap0_1[0:0] 1'0 + assign $1\dp_FAST_fast1_trap0_4[0:0] 1'0 sync always sync init - update \dp_FAST_fast2_trap0_1 $1\dp_FAST_fast2_trap0_1[0:0] + update \dp_FAST_fast1_trap0_4 $1\dp_FAST_fast1_trap0_4[0:0] end - attribute \src "libresoc.v:39483.7-39483.30" - process $proc$libresoc.v:39483$2913 + attribute \src "libresoc.v:39323.7-39323.32" + process $proc$libresoc.v:39323$2913 assign { } { } - assign $1\dp_INT_ra_alu0_0[0:0] 1'0 + assign $1\dp_INT_rabc_alu0_0[0:0] 1'0 sync always sync init - update \dp_INT_ra_alu0_0 $1\dp_INT_ra_alu0_0[0:0] + update \dp_INT_rabc_alu0_0 $1\dp_INT_rabc_alu0_0[0:0] end - attribute \src "libresoc.v:39487.7-39487.29" - process $proc$libresoc.v:39487$2914 + attribute \src "libresoc.v:39327.7-39327.33" + process $proc$libresoc.v:39327$2914 assign { } { } - assign $1\dp_INT_ra_cr0_1[0:0] 1'0 + assign $1\dp_INT_rabc_alu0_10[0:0] 1'0 sync always sync init - update \dp_INT_ra_cr0_1 $1\dp_INT_ra_cr0_1[0:0] + update \dp_INT_rabc_alu0_10 $1\dp_INT_rabc_alu0_10[0:0] end - attribute \src "libresoc.v:39491.7-39491.30" - process $proc$libresoc.v:39491$2915 + attribute \src "libresoc.v:39331.7-39331.31" + process $proc$libresoc.v:39331$2915 assign { } { } - assign $1\dp_INT_ra_div0_5[0:0] 1'0 + assign $1\dp_INT_rabc_cr0_1[0:0] 1'0 sync always sync init - update \dp_INT_ra_div0_5 $1\dp_INT_ra_div0_5[0:0] + update \dp_INT_rabc_cr0_1 $1\dp_INT_rabc_cr0_1[0:0] end - attribute \src "libresoc.v:39495.7-39495.31" - process $proc$libresoc.v:39495$2916 + attribute \src "libresoc.v:39335.7-39335.32" + process $proc$libresoc.v:39335$2916 assign { } { } - assign $1\dp_INT_ra_ldst0_8[0:0] 1'0 + assign $1\dp_INT_rabc_cr0_11[0:0] 1'0 sync always sync init - update \dp_INT_ra_ldst0_8 $1\dp_INT_ra_ldst0_8[0:0] + update \dp_INT_rabc_cr0_11 $1\dp_INT_rabc_cr0_11[0:0] end - attribute \src "libresoc.v:39499.7-39499.34" - process $proc$libresoc.v:39499$2917 + attribute \src "libresoc.v:39339.7-39339.33" + process $proc$libresoc.v:39339$2917 assign { } { } - assign $1\dp_INT_ra_logical0_3[0:0] 1'0 + assign $1\dp_INT_rabc_div0_15[0:0] 1'0 sync always sync init - update \dp_INT_ra_logical0_3 $1\dp_INT_ra_logical0_3[0:0] + update \dp_INT_rabc_div0_15 $1\dp_INT_rabc_div0_15[0:0] end - attribute \src "libresoc.v:39503.7-39503.30" - process $proc$libresoc.v:39503$2918 + attribute \src "libresoc.v:39343.7-39343.32" + process $proc$libresoc.v:39343$2918 assign { } { } - assign $1\dp_INT_ra_mul0_6[0:0] 1'0 + assign $1\dp_INT_rabc_div0_4[0:0] 1'0 sync always sync init - update \dp_INT_ra_mul0_6 $1\dp_INT_ra_mul0_6[0:0] + update \dp_INT_rabc_div0_4 $1\dp_INT_rabc_div0_4[0:0] end - attribute \src "libresoc.v:39507.7-39507.35" - process $proc$libresoc.v:39507$2919 + attribute \src "libresoc.v:39347.7-39347.34" + process $proc$libresoc.v:39347$2919 assign { } { } - assign $1\dp_INT_ra_shiftrot0_7[0:0] 1'0 + assign $1\dp_INT_rabc_ldst0_18[0:0] 1'0 sync always sync init - update \dp_INT_ra_shiftrot0_7 $1\dp_INT_ra_shiftrot0_7[0:0] + update \dp_INT_rabc_ldst0_18 $1\dp_INT_rabc_ldst0_18[0:0] end - attribute \src "libresoc.v:39511.7-39511.30" - process $proc$libresoc.v:39511$2920 + attribute \src "libresoc.v:39351.7-39351.33" + process $proc$libresoc.v:39351$2920 assign { } { } - assign $1\dp_INT_ra_spr0_4[0:0] 1'0 + assign $1\dp_INT_rabc_ldst0_7[0:0] 1'0 sync always sync init - update \dp_INT_ra_spr0_4 $1\dp_INT_ra_spr0_4[0:0] + update \dp_INT_rabc_ldst0_7 $1\dp_INT_rabc_ldst0_7[0:0] end - attribute \src "libresoc.v:39515.7-39515.31" - process $proc$libresoc.v:39515$2921 + attribute \src "libresoc.v:39355.7-39355.33" + process $proc$libresoc.v:39355$2921 assign { } { } - assign $1\dp_INT_ra_trap0_2[0:0] 1'0 + assign $1\dp_INT_rabc_ldst0_9[0:0] 1'0 sync always sync init - update \dp_INT_ra_trap0_2 $1\dp_INT_ra_trap0_2[0:0] + update \dp_INT_rabc_ldst0_9 $1\dp_INT_rabc_ldst0_9[0:0] end - attribute \src "libresoc.v:39519.7-39519.30" - process $proc$libresoc.v:39519$2922 + attribute \src "libresoc.v:39359.7-39359.37" + process $proc$libresoc.v:39359$2922 assign { } { } - assign $1\dp_INT_rb_alu0_0[0:0] 1'0 + assign $1\dp_INT_rabc_logical0_13[0:0] 1'0 sync always sync init - update \dp_INT_rb_alu0_0 $1\dp_INT_rb_alu0_0[0:0] + update \dp_INT_rabc_logical0_13 $1\dp_INT_rabc_logical0_13[0:0] end - attribute \src "libresoc.v:39523.7-39523.29" - process $proc$libresoc.v:39523$2923 + attribute \src "libresoc.v:39363.7-39363.36" + process $proc$libresoc.v:39363$2923 assign { } { } - assign $1\dp_INT_rb_cr0_1[0:0] 1'0 + assign $1\dp_INT_rabc_logical0_3[0:0] 1'0 sync always sync init - update \dp_INT_rb_cr0_1 $1\dp_INT_rb_cr0_1[0:0] + update \dp_INT_rabc_logical0_3 $1\dp_INT_rabc_logical0_3[0:0] end - attribute \src "libresoc.v:39527.7-39527.30" - process $proc$libresoc.v:39527$2924 + attribute \src "libresoc.v:39367.7-39367.33" + process $proc$libresoc.v:39367$2924 assign { } { } - assign $1\dp_INT_rb_div0_4[0:0] 1'0 + assign $1\dp_INT_rabc_mul0_16[0:0] 1'0 sync always sync init - update \dp_INT_rb_div0_4 $1\dp_INT_rb_div0_4[0:0] + update \dp_INT_rabc_mul0_16 $1\dp_INT_rabc_mul0_16[0:0] end - attribute \src "libresoc.v:39531.7-39531.31" - process $proc$libresoc.v:39531$2925 + attribute \src "libresoc.v:39371.7-39371.32" + process $proc$libresoc.v:39371$2925 assign { } { } - assign $1\dp_INT_rb_ldst0_7[0:0] 1'0 + assign $1\dp_INT_rabc_mul0_5[0:0] 1'0 sync always sync init - update \dp_INT_rb_ldst0_7 $1\dp_INT_rb_ldst0_7[0:0] + update \dp_INT_rabc_mul0_5 $1\dp_INT_rabc_mul0_5[0:0] end - attribute \src "libresoc.v:39535.7-39535.34" - process $proc$libresoc.v:39535$2926 + attribute \src "libresoc.v:39375.7-39375.38" + process $proc$libresoc.v:39375$2926 assign { } { } - assign $1\dp_INT_rb_logical0_3[0:0] 1'0 + assign $1\dp_INT_rabc_shiftrot0_17[0:0] 1'0 sync always sync init - update \dp_INT_rb_logical0_3 $1\dp_INT_rb_logical0_3[0:0] + update \dp_INT_rabc_shiftrot0_17 $1\dp_INT_rabc_shiftrot0_17[0:0] end - attribute \src "libresoc.v:39539.7-39539.30" - process $proc$libresoc.v:39539$2927 + attribute \src "libresoc.v:39379.7-39379.37" + process $proc$libresoc.v:39379$2927 assign { } { } - assign $1\dp_INT_rb_mul0_5[0:0] 1'0 + assign $1\dp_INT_rabc_shiftrot0_6[0:0] 1'0 sync always sync init - update \dp_INT_rb_mul0_5 $1\dp_INT_rb_mul0_5[0:0] + update \dp_INT_rabc_shiftrot0_6 $1\dp_INT_rabc_shiftrot0_6[0:0] end - attribute \src "libresoc.v:39543.7-39543.35" - process $proc$libresoc.v:39543$2928 + attribute \src "libresoc.v:39383.7-39383.37" + process $proc$libresoc.v:39383$2928 assign { } { } - assign $1\dp_INT_rb_shiftrot0_6[0:0] 1'0 + assign $1\dp_INT_rabc_shiftrot0_8[0:0] 1'0 sync always sync init - update \dp_INT_rb_shiftrot0_6 $1\dp_INT_rb_shiftrot0_6[0:0] + update \dp_INT_rabc_shiftrot0_8 $1\dp_INT_rabc_shiftrot0_8[0:0] end - attribute \src "libresoc.v:39547.7-39547.31" - process $proc$libresoc.v:39547$2929 + attribute \src "libresoc.v:39387.7-39387.33" + process $proc$libresoc.v:39387$2929 assign { } { } - assign $1\dp_INT_rb_trap0_2[0:0] 1'0 + assign $1\dp_INT_rabc_spr0_14[0:0] 1'0 sync always sync init - update \dp_INT_rb_trap0_2 $1\dp_INT_rb_trap0_2[0:0] + update \dp_INT_rabc_spr0_14 $1\dp_INT_rabc_spr0_14[0:0] end - attribute \src "libresoc.v:39551.7-39551.31" - process $proc$libresoc.v:39551$2930 + attribute \src "libresoc.v:39391.7-39391.34" + process $proc$libresoc.v:39391$2930 assign { } { } - assign $1\dp_INT_rc_ldst0_1[0:0] 1'0 + assign $1\dp_INT_rabc_trap0_12[0:0] 1'0 sync always sync init - update \dp_INT_rc_ldst0_1 $1\dp_INT_rc_ldst0_1[0:0] + update \dp_INT_rabc_trap0_12 $1\dp_INT_rabc_trap0_12[0:0] end - attribute \src "libresoc.v:39555.7-39555.35" - process $proc$libresoc.v:39555$2931 + attribute \src "libresoc.v:39395.7-39395.33" + process $proc$libresoc.v:39395$2931 assign { } { } - assign $1\dp_INT_rc_shiftrot0_0[0:0] 1'0 + assign $1\dp_INT_rabc_trap0_2[0:0] 1'0 sync always sync init - update \dp_INT_rc_shiftrot0_0 $1\dp_INT_rc_shiftrot0_0[0:0] + update \dp_INT_rabc_trap0_2 $1\dp_INT_rabc_trap0_2[0:0] end - attribute \src "libresoc.v:39559.7-39559.32" - process $proc$libresoc.v:39559$2932 + attribute \src "libresoc.v:39399.7-39399.32" + process $proc$libresoc.v:39399$2932 assign { } { } assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 sync always sync init update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] end - attribute \src "libresoc.v:39563.7-39563.34" - process $proc$libresoc.v:39563$2933 + attribute \src "libresoc.v:39403.7-39403.34" + process $proc$libresoc.v:39403$2933 assign { } { } assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] end - attribute \src "libresoc.v:39567.7-39567.39" - process $proc$libresoc.v:39567$2934 + attribute \src "libresoc.v:39407.7-39407.39" + process $proc$libresoc.v:39407$2934 assign { } { } assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] end - attribute \src "libresoc.v:39571.7-39571.34" - process $proc$libresoc.v:39571$2935 + attribute \src "libresoc.v:39411.7-39411.34" + process $proc$libresoc.v:39411$2935 assign { } { } assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] end - attribute \src "libresoc.v:39575.7-39575.34" - process $proc$libresoc.v:39575$2936 + attribute \src "libresoc.v:39415.7-39415.34" + process $proc$libresoc.v:39415$2936 assign { } { } assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] end - attribute \src "libresoc.v:39579.7-39579.34" - process $proc$libresoc.v:39579$2937 + attribute \src "libresoc.v:39419.7-39419.34" + process $proc$libresoc.v:39419$2937 assign { } { } assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] end - attribute \src "libresoc.v:39583.7-39583.34" - process $proc$libresoc.v:39583$2938 + attribute \src "libresoc.v:39423.7-39423.34" + process $proc$libresoc.v:39423$2938 assign { } { } assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 sync always sync init update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] end - attribute \src "libresoc.v:39587.7-39587.38" - process $proc$libresoc.v:39587$2939 + attribute \src "libresoc.v:39427.7-39427.38" + process $proc$libresoc.v:39427$2939 assign { } { } assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] end - attribute \src "libresoc.v:39591.7-39591.34" - process $proc$libresoc.v:39591$2940 + attribute \src "libresoc.v:39431.7-39431.34" + process $proc$libresoc.v:39431$2940 assign { } { } assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 sync always sync init update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] end - attribute \src "libresoc.v:39595.7-39595.39" - process $proc$libresoc.v:39595$2941 + attribute \src "libresoc.v:39435.7-39435.39" + process $proc$libresoc.v:39435$2941 assign { } { } assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 sync always sync init update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] end - attribute \src "libresoc.v:39599.7-39599.34" - process $proc$libresoc.v:39599$2942 + attribute \src "libresoc.v:39439.7-39439.34" + process $proc$libresoc.v:39439$2942 assign { } { } assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] end - attribute \src "libresoc.v:41724.7-41724.25" - process $proc$libresoc.v:41724$2943 + attribute \src "libresoc.v:41528.7-41528.25" + process $proc$libresoc.v:41528$2943 assign { } { } assign $1\wr_pick_dly[0:0] 1'0 sync always sync init update \wr_pick_dly $1\wr_pick_dly[0:0] end - attribute \src "libresoc.v:41726.7-41726.32" - process $proc$libresoc.v:41726$2944 + attribute \src "libresoc.v:41530.7-41530.32" + process $proc$libresoc.v:41530$2944 assign { } { } - assign $0\wr_pick_dly$1010[0:0]$2945 1'0 + assign $0\wr_pick_dly$1008[0:0]$2945 1'0 sync always sync init - update \wr_pick_dly$1010 $0\wr_pick_dly$1010[0:0]$2945 + update \wr_pick_dly$1008 $0\wr_pick_dly$1008[0:0]$2945 end - attribute \src "libresoc.v:41730.7-41730.32" - process $proc$libresoc.v:41730$2946 + attribute \src "libresoc.v:41534.7-41534.32" + process $proc$libresoc.v:41534$2946 assign { } { } - assign $0\wr_pick_dly$1031[0:0]$2947 1'0 + assign $0\wr_pick_dly$1029[0:0]$2947 1'0 sync always sync init - update \wr_pick_dly$1031 $0\wr_pick_dly$1031[0:0]$2947 + update \wr_pick_dly$1029 $0\wr_pick_dly$1029[0:0]$2947 end - attribute \src "libresoc.v:41734.7-41734.32" - process $proc$libresoc.v:41734$2948 + attribute \src "libresoc.v:41538.7-41538.32" + process $proc$libresoc.v:41538$2948 assign { } { } - assign $0\wr_pick_dly$1049[0:0]$2949 1'0 + assign $0\wr_pick_dly$1047[0:0]$2949 1'0 sync always sync init - update \wr_pick_dly$1049 $0\wr_pick_dly$1049[0:0]$2949 + update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2949 end - attribute \src "libresoc.v:41738.7-41738.32" - process $proc$libresoc.v:41738$2950 + attribute \src "libresoc.v:41542.7-41542.32" + process $proc$libresoc.v:41542$2950 assign { } { } - assign $0\wr_pick_dly$1071[0:0]$2951 1'0 + assign $0\wr_pick_dly$1069[0:0]$2951 1'0 sync always sync init - update \wr_pick_dly$1071 $0\wr_pick_dly$1071[0:0]$2951 + update \wr_pick_dly$1069 $0\wr_pick_dly$1069[0:0]$2951 end - attribute \src "libresoc.v:41742.7-41742.32" - process $proc$libresoc.v:41742$2952 + attribute \src "libresoc.v:41546.7-41546.32" + process $proc$libresoc.v:41546$2952 assign { } { } - assign $0\wr_pick_dly$1091[0:0]$2953 1'0 + assign $0\wr_pick_dly$1089[0:0]$2953 1'0 sync always sync init - update \wr_pick_dly$1091 $0\wr_pick_dly$1091[0:0]$2953 + update \wr_pick_dly$1089 $0\wr_pick_dly$1089[0:0]$2953 end - attribute \src "libresoc.v:41746.7-41746.32" - process $proc$libresoc.v:41746$2954 + attribute \src "libresoc.v:41550.7-41550.32" + process $proc$libresoc.v:41550$2954 assign { } { } - assign $0\wr_pick_dly$1111[0:0]$2955 1'0 + assign $0\wr_pick_dly$1109[0:0]$2955 1'0 sync always sync init - update \wr_pick_dly$1111 $0\wr_pick_dly$1111[0:0]$2955 + update \wr_pick_dly$1109 $0\wr_pick_dly$1109[0:0]$2955 end - attribute \src "libresoc.v:41750.7-41750.32" - process $proc$libresoc.v:41750$2956 + attribute \src "libresoc.v:41554.7-41554.32" + process $proc$libresoc.v:41554$2956 assign { } { } - assign $0\wr_pick_dly$1130[0:0]$2957 1'0 + assign $0\wr_pick_dly$1128[0:0]$2957 1'0 sync always sync init - update \wr_pick_dly$1130 $0\wr_pick_dly$1130[0:0]$2957 + update \wr_pick_dly$1128 $0\wr_pick_dly$1128[0:0]$2957 end - attribute \src "libresoc.v:41754.7-41754.32" - process $proc$libresoc.v:41754$2958 + attribute \src "libresoc.v:41558.7-41558.32" + process $proc$libresoc.v:41558$2958 assign { } { } - assign $0\wr_pick_dly$1148[0:0]$2959 1'0 + assign $0\wr_pick_dly$1146[0:0]$2959 1'0 sync always sync init - update \wr_pick_dly$1148 $0\wr_pick_dly$1148[0:0]$2959 + update \wr_pick_dly$1146 $0\wr_pick_dly$1146[0:0]$2959 end - attribute \src "libresoc.v:41758.7-41758.32" - process $proc$libresoc.v:41758$2960 + attribute \src "libresoc.v:41562.7-41562.32" + process $proc$libresoc.v:41562$2960 assign { } { } - assign $0\wr_pick_dly$1222[0:0]$2961 1'0 + assign $0\wr_pick_dly$1220[0:0]$2961 1'0 sync always sync init - update \wr_pick_dly$1222 $0\wr_pick_dly$1222[0:0]$2961 + update \wr_pick_dly$1220 $0\wr_pick_dly$1220[0:0]$2961 end - attribute \src "libresoc.v:41762.7-41762.32" - process $proc$libresoc.v:41762$2962 + attribute \src "libresoc.v:41566.7-41566.32" + process $proc$libresoc.v:41566$2962 assign { } { } - assign $0\wr_pick_dly$1250[0:0]$2963 1'0 + assign $0\wr_pick_dly$1248[0:0]$2963 1'0 sync always sync init - update \wr_pick_dly$1250 $0\wr_pick_dly$1250[0:0]$2963 + update \wr_pick_dly$1248 $0\wr_pick_dly$1248[0:0]$2963 end - attribute \src "libresoc.v:41766.7-41766.32" - process $proc$libresoc.v:41766$2964 + attribute \src "libresoc.v:41570.7-41570.32" + process $proc$libresoc.v:41570$2964 assign { } { } - assign $0\wr_pick_dly$1270[0:0]$2965 1'0 + assign $0\wr_pick_dly$1268[0:0]$2965 1'0 sync always sync init - update \wr_pick_dly$1270 $0\wr_pick_dly$1270[0:0]$2965 + update \wr_pick_dly$1268 $0\wr_pick_dly$1268[0:0]$2965 end - attribute \src "libresoc.v:41770.7-41770.32" - process $proc$libresoc.v:41770$2966 + attribute \src "libresoc.v:41574.7-41574.32" + process $proc$libresoc.v:41574$2966 assign { } { } - assign $0\wr_pick_dly$1290[0:0]$2967 1'0 + assign $0\wr_pick_dly$1288[0:0]$2967 1'0 sync always sync init - update \wr_pick_dly$1290 $0\wr_pick_dly$1290[0:0]$2967 + update \wr_pick_dly$1288 $0\wr_pick_dly$1288[0:0]$2967 end - attribute \src "libresoc.v:41774.7-41774.32" - process $proc$libresoc.v:41774$2968 + attribute \src "libresoc.v:41578.7-41578.32" + process $proc$libresoc.v:41578$2968 assign { } { } - assign $0\wr_pick_dly$1310[0:0]$2969 1'0 + assign $0\wr_pick_dly$1308[0:0]$2969 1'0 sync always sync init - update \wr_pick_dly$1310 $0\wr_pick_dly$1310[0:0]$2969 + update \wr_pick_dly$1308 $0\wr_pick_dly$1308[0:0]$2969 end - attribute \src "libresoc.v:41778.7-41778.32" - process $proc$libresoc.v:41778$2970 + attribute \src "libresoc.v:41582.7-41582.32" + process $proc$libresoc.v:41582$2970 assign { } { } - assign $0\wr_pick_dly$1330[0:0]$2971 1'0 + assign $0\wr_pick_dly$1328[0:0]$2971 1'0 sync always sync init - update \wr_pick_dly$1330 $0\wr_pick_dly$1330[0:0]$2971 + update \wr_pick_dly$1328 $0\wr_pick_dly$1328[0:0]$2971 end - attribute \src "libresoc.v:41782.7-41782.32" - process $proc$libresoc.v:41782$2972 + attribute \src "libresoc.v:41586.7-41586.32" + process $proc$libresoc.v:41586$2972 assign { } { } - assign $0\wr_pick_dly$1350[0:0]$2973 1'0 + assign $0\wr_pick_dly$1348[0:0]$2973 1'0 sync always sync init - update \wr_pick_dly$1350 $0\wr_pick_dly$1350[0:0]$2973 + update \wr_pick_dly$1348 $0\wr_pick_dly$1348[0:0]$2973 end - attribute \src "libresoc.v:41786.7-41786.32" - process $proc$libresoc.v:41786$2974 + attribute \src "libresoc.v:41590.7-41590.32" + process $proc$libresoc.v:41590$2974 assign { } { } - assign $0\wr_pick_dly$1397[0:0]$2975 1'0 + assign $0\wr_pick_dly$1395[0:0]$2975 1'0 sync always sync init - update \wr_pick_dly$1397 $0\wr_pick_dly$1397[0:0]$2975 + update \wr_pick_dly$1395 $0\wr_pick_dly$1395[0:0]$2975 end - attribute \src "libresoc.v:41790.7-41790.32" - process $proc$libresoc.v:41790$2976 + attribute \src "libresoc.v:41594.7-41594.32" + process $proc$libresoc.v:41594$2976 assign { } { } - assign $0\wr_pick_dly$1413[0:0]$2977 1'0 + assign $0\wr_pick_dly$1411[0:0]$2977 1'0 sync always sync init - update \wr_pick_dly$1413 $0\wr_pick_dly$1413[0:0]$2977 + update \wr_pick_dly$1411 $0\wr_pick_dly$1411[0:0]$2977 end - attribute \src "libresoc.v:41794.7-41794.32" - process $proc$libresoc.v:41794$2978 + attribute \src "libresoc.v:41598.7-41598.32" + process $proc$libresoc.v:41598$2978 assign { } { } - assign $0\wr_pick_dly$1429[0:0]$2979 1'0 + assign $0\wr_pick_dly$1427[0:0]$2979 1'0 sync always sync init - update \wr_pick_dly$1429 $0\wr_pick_dly$1429[0:0]$2979 + update \wr_pick_dly$1427 $0\wr_pick_dly$1427[0:0]$2979 end - attribute \src "libresoc.v:41798.7-41798.32" - process $proc$libresoc.v:41798$2980 + attribute \src "libresoc.v:41602.7-41602.32" + process $proc$libresoc.v:41602$2980 assign { } { } - assign $0\wr_pick_dly$1463[0:0]$2981 1'0 + assign $0\wr_pick_dly$1461[0:0]$2981 1'0 sync always sync init - update \wr_pick_dly$1463 $0\wr_pick_dly$1463[0:0]$2981 + update \wr_pick_dly$1461 $0\wr_pick_dly$1461[0:0]$2981 end - attribute \src "libresoc.v:41802.7-41802.32" - process $proc$libresoc.v:41802$2982 + attribute \src "libresoc.v:41606.7-41606.32" + process $proc$libresoc.v:41606$2982 assign { } { } - assign $0\wr_pick_dly$1479[0:0]$2983 1'0 + assign $0\wr_pick_dly$1477[0:0]$2983 1'0 sync always sync init - update \wr_pick_dly$1479 $0\wr_pick_dly$1479[0:0]$2983 + update \wr_pick_dly$1477 $0\wr_pick_dly$1477[0:0]$2983 end - attribute \src "libresoc.v:41806.7-41806.32" - process $proc$libresoc.v:41806$2984 + attribute \src "libresoc.v:41610.7-41610.32" + process $proc$libresoc.v:41610$2984 assign { } { } - assign $0\wr_pick_dly$1495[0:0]$2985 1'0 + assign $0\wr_pick_dly$1493[0:0]$2985 1'0 sync always sync init - update \wr_pick_dly$1495 $0\wr_pick_dly$1495[0:0]$2985 + update \wr_pick_dly$1493 $0\wr_pick_dly$1493[0:0]$2985 end - attribute \src "libresoc.v:41810.7-41810.32" - process $proc$libresoc.v:41810$2986 + attribute \src "libresoc.v:41614.7-41614.32" + process $proc$libresoc.v:41614$2986 assign { } { } - assign $0\wr_pick_dly$1511[0:0]$2987 1'0 + assign $0\wr_pick_dly$1509[0:0]$2987 1'0 sync always sync init - update \wr_pick_dly$1511 $0\wr_pick_dly$1511[0:0]$2987 + update \wr_pick_dly$1509 $0\wr_pick_dly$1509[0:0]$2987 end - attribute \src "libresoc.v:41814.7-41814.32" - process $proc$libresoc.v:41814$2988 + attribute \src "libresoc.v:41618.7-41618.32" + process $proc$libresoc.v:41618$2988 assign { } { } - assign $0\wr_pick_dly$1547[0:0]$2989 1'0 + assign $0\wr_pick_dly$1545[0:0]$2989 1'0 sync always sync init - update \wr_pick_dly$1547 $0\wr_pick_dly$1547[0:0]$2989 + update \wr_pick_dly$1545 $0\wr_pick_dly$1545[0:0]$2989 end - attribute \src "libresoc.v:41818.7-41818.32" - process $proc$libresoc.v:41818$2990 + attribute \src "libresoc.v:41622.7-41622.32" + process $proc$libresoc.v:41622$2990 assign { } { } - assign $0\wr_pick_dly$1563[0:0]$2991 1'0 + assign $0\wr_pick_dly$1561[0:0]$2991 1'0 sync always sync init - update \wr_pick_dly$1563 $0\wr_pick_dly$1563[0:0]$2991 + update \wr_pick_dly$1561 $0\wr_pick_dly$1561[0:0]$2991 end - attribute \src "libresoc.v:41822.7-41822.32" - process $proc$libresoc.v:41822$2992 + attribute \src "libresoc.v:41626.7-41626.32" + process $proc$libresoc.v:41626$2992 assign { } { } - assign $0\wr_pick_dly$1579[0:0]$2993 1'0 + assign $0\wr_pick_dly$1577[0:0]$2993 1'0 sync always sync init - update \wr_pick_dly$1579 $0\wr_pick_dly$1579[0:0]$2993 + update \wr_pick_dly$1577 $0\wr_pick_dly$1577[0:0]$2993 end - attribute \src "libresoc.v:41826.7-41826.32" - process $proc$libresoc.v:41826$2994 + attribute \src "libresoc.v:41630.7-41630.32" + process $proc$libresoc.v:41630$2994 assign { } { } - assign $0\wr_pick_dly$1595[0:0]$2995 1'0 + assign $0\wr_pick_dly$1593[0:0]$2995 1'0 sync always sync init - update \wr_pick_dly$1595 $0\wr_pick_dly$1595[0:0]$2995 + update \wr_pick_dly$1593 $0\wr_pick_dly$1593[0:0]$2995 end - attribute \src "libresoc.v:41830.7-41830.32" - process $proc$libresoc.v:41830$2996 + attribute \src "libresoc.v:41634.7-41634.32" + process $proc$libresoc.v:41634$2996 assign { } { } - assign $0\wr_pick_dly$1637[0:0]$2997 1'0 + assign $0\wr_pick_dly$1635[0:0]$2997 1'0 sync always sync init - update \wr_pick_dly$1637 $0\wr_pick_dly$1637[0:0]$2997 + update \wr_pick_dly$1635 $0\wr_pick_dly$1635[0:0]$2997 end - attribute \src "libresoc.v:41834.7-41834.32" - process $proc$libresoc.v:41834$2998 + attribute \src "libresoc.v:41638.7-41638.32" + process $proc$libresoc.v:41638$2998 assign { } { } - assign $0\wr_pick_dly$1656[0:0]$2999 1'0 + assign $0\wr_pick_dly$1654[0:0]$2999 1'0 sync always sync init - update \wr_pick_dly$1656 $0\wr_pick_dly$1656[0:0]$2999 + update \wr_pick_dly$1654 $0\wr_pick_dly$1654[0:0]$2999 end - attribute \src "libresoc.v:41838.7-41838.32" - process $proc$libresoc.v:41838$3000 + attribute \src "libresoc.v:41642.7-41642.32" + process $proc$libresoc.v:41642$3000 assign { } { } - assign $0\wr_pick_dly$1672[0:0]$3001 1'0 + assign $0\wr_pick_dly$1670[0:0]$3001 1'0 sync always sync init - update \wr_pick_dly$1672 $0\wr_pick_dly$1672[0:0]$3001 + update \wr_pick_dly$1670 $0\wr_pick_dly$1670[0:0]$3001 end - attribute \src "libresoc.v:41842.7-41842.32" - process $proc$libresoc.v:41842$3002 + attribute \src "libresoc.v:41646.7-41646.32" + process $proc$libresoc.v:41646$3002 assign { } { } - assign $0\wr_pick_dly$1688[0:0]$3003 1'0 + assign $0\wr_pick_dly$1686[0:0]$3003 1'0 sync always sync init - update \wr_pick_dly$1688 $0\wr_pick_dly$1688[0:0]$3003 + update \wr_pick_dly$1686 $0\wr_pick_dly$1686[0:0]$3003 end - attribute \src "libresoc.v:41846.7-41846.32" - process $proc$libresoc.v:41846$3004 + attribute \src "libresoc.v:41650.7-41650.32" + process $proc$libresoc.v:41650$3004 assign { } { } - assign $0\wr_pick_dly$1704[0:0]$3005 1'0 + assign $0\wr_pick_dly$1702[0:0]$3005 1'0 sync always sync init - update \wr_pick_dly$1704 $0\wr_pick_dly$1704[0:0]$3005 + update \wr_pick_dly$1702 $0\wr_pick_dly$1702[0:0]$3005 end - attribute \src "libresoc.v:41850.7-41850.32" - process $proc$libresoc.v:41850$3006 + attribute \src "libresoc.v:41654.7-41654.32" + process $proc$libresoc.v:41654$3006 assign { } { } - assign $0\wr_pick_dly$1748[0:0]$3007 1'0 + assign $0\wr_pick_dly$1746[0:0]$3007 1'0 sync always sync init - update \wr_pick_dly$1748 $0\wr_pick_dly$1748[0:0]$3007 + update \wr_pick_dly$1746 $0\wr_pick_dly$1746[0:0]$3007 end - attribute \src "libresoc.v:41854.7-41854.32" - process $proc$libresoc.v:41854$3008 + attribute \src "libresoc.v:41658.7-41658.32" + process $proc$libresoc.v:41658$3008 assign { } { } - assign $0\wr_pick_dly$1764[0:0]$3009 1'0 + assign $0\wr_pick_dly$1762[0:0]$3009 1'0 sync always sync init - update \wr_pick_dly$1764 $0\wr_pick_dly$1764[0:0]$3009 + update \wr_pick_dly$1762 $0\wr_pick_dly$1762[0:0]$3009 end - attribute \src "libresoc.v:41858.7-41858.32" - process $proc$libresoc.v:41858$3010 + attribute \src "libresoc.v:41662.7-41662.32" + process $proc$libresoc.v:41662$3010 assign { } { } - assign $0\wr_pick_dly$1788[0:0]$3011 1'0 + assign $0\wr_pick_dly$1786[0:0]$3011 1'0 sync always sync init - update \wr_pick_dly$1788 $0\wr_pick_dly$1788[0:0]$3011 + update \wr_pick_dly$1786 $0\wr_pick_dly$1786[0:0]$3011 end - attribute \src "libresoc.v:41862.7-41862.32" - process $proc$libresoc.v:41862$3012 + attribute \src "libresoc.v:41666.7-41666.32" + process $proc$libresoc.v:41666$3012 assign { } { } - assign $0\wr_pick_dly$1808[0:0]$3013 1'0 + assign $0\wr_pick_dly$1806[0:0]$3013 1'0 sync always sync init - update \wr_pick_dly$1808 $0\wr_pick_dly$1808[0:0]$3013 + update \wr_pick_dly$1806 $0\wr_pick_dly$1806[0:0]$3013 end - attribute \src "libresoc.v:41866.7-41866.31" - process $proc$libresoc.v:41866$3014 + attribute \src "libresoc.v:41670.7-41670.31" + process $proc$libresoc.v:41670$3014 assign { } { } - assign $0\wr_pick_dly$991[0:0]$3015 1'0 + assign $0\wr_pick_dly$989[0:0]$3015 1'0 sync always sync init - update \wr_pick_dly$991 $0\wr_pick_dly$991[0:0]$3015 + update \wr_pick_dly$989 $0\wr_pick_dly$989[0:0]$3015 end - attribute \src "libresoc.v:42828.3-42829.51" - process $proc$libresoc.v:42828$2238 + attribute \src "libresoc.v:42632.3-42633.51" + process $proc$libresoc.v:42632$2238 assign { } { } - assign $0\wr_pick_dly$1808[0:0]$2239 \wr_pick_dly$1808$next + assign $0\wr_pick_dly$1806[0:0]$2239 \wr_pick_dly$1806$next sync posedge \coresync_clk - update \wr_pick_dly$1808 $0\wr_pick_dly$1808[0:0]$2239 + update \wr_pick_dly$1806 $0\wr_pick_dly$1806[0:0]$2239 end - attribute \src "libresoc.v:42830.3-42831.51" - process $proc$libresoc.v:42830$2240 + attribute \src "libresoc.v:42634.3-42635.51" + process $proc$libresoc.v:42634$2240 assign { } { } - assign $0\wr_pick_dly$1788[0:0]$2241 \wr_pick_dly$1788$next + assign $0\wr_pick_dly$1786[0:0]$2241 \wr_pick_dly$1786$next sync posedge \coresync_clk - update \wr_pick_dly$1788 $0\wr_pick_dly$1788[0:0]$2241 + update \wr_pick_dly$1786 $0\wr_pick_dly$1786[0:0]$2241 end - attribute \src "libresoc.v:42832.3-42833.51" - process $proc$libresoc.v:42832$2242 + attribute \src "libresoc.v:42636.3-42637.51" + process $proc$libresoc.v:42636$2242 assign { } { } - assign $0\wr_pick_dly$1764[0:0]$2243 \wr_pick_dly$1764$next + assign $0\wr_pick_dly$1762[0:0]$2243 \wr_pick_dly$1762$next sync posedge \coresync_clk - update \wr_pick_dly$1764 $0\wr_pick_dly$1764[0:0]$2243 + update \wr_pick_dly$1762 $0\wr_pick_dly$1762[0:0]$2243 end - attribute \src "libresoc.v:42834.3-42835.51" - process $proc$libresoc.v:42834$2244 + attribute \src "libresoc.v:42638.3-42639.51" + process $proc$libresoc.v:42638$2244 assign { } { } - assign $0\wr_pick_dly$1748[0:0]$2245 \wr_pick_dly$1748$next + assign $0\wr_pick_dly$1746[0:0]$2245 \wr_pick_dly$1746$next sync posedge \coresync_clk - update \wr_pick_dly$1748 $0\wr_pick_dly$1748[0:0]$2245 + update \wr_pick_dly$1746 $0\wr_pick_dly$1746[0:0]$2245 end - attribute \src "libresoc.v:42836.3-42837.51" - process $proc$libresoc.v:42836$2246 + attribute \src "libresoc.v:42640.3-42641.51" + process $proc$libresoc.v:42640$2246 assign { } { } - assign $0\wr_pick_dly$1704[0:0]$2247 \wr_pick_dly$1704$next + assign $0\wr_pick_dly$1702[0:0]$2247 \wr_pick_dly$1702$next sync posedge \coresync_clk - update \wr_pick_dly$1704 $0\wr_pick_dly$1704[0:0]$2247 + update \wr_pick_dly$1702 $0\wr_pick_dly$1702[0:0]$2247 end - attribute \src "libresoc.v:42838.3-42839.51" - process $proc$libresoc.v:42838$2248 + attribute \src "libresoc.v:42642.3-42643.51" + process $proc$libresoc.v:42642$2248 assign { } { } - assign $0\wr_pick_dly$1688[0:0]$2249 \wr_pick_dly$1688$next + assign $0\wr_pick_dly$1686[0:0]$2249 \wr_pick_dly$1686$next sync posedge \coresync_clk - update \wr_pick_dly$1688 $0\wr_pick_dly$1688[0:0]$2249 + update \wr_pick_dly$1686 $0\wr_pick_dly$1686[0:0]$2249 end - attribute \src "libresoc.v:42840.3-42841.51" - process $proc$libresoc.v:42840$2250 + attribute \src "libresoc.v:42644.3-42645.51" + process $proc$libresoc.v:42644$2250 assign { } { } - assign $0\wr_pick_dly$1672[0:0]$2251 \wr_pick_dly$1672$next + assign $0\wr_pick_dly$1670[0:0]$2251 \wr_pick_dly$1670$next sync posedge \coresync_clk - update \wr_pick_dly$1672 $0\wr_pick_dly$1672[0:0]$2251 + update \wr_pick_dly$1670 $0\wr_pick_dly$1670[0:0]$2251 end - attribute \src "libresoc.v:42842.3-42843.51" - process $proc$libresoc.v:42842$2252 + attribute \src "libresoc.v:42646.3-42647.51" + process $proc$libresoc.v:42646$2252 assign { } { } - assign $0\wr_pick_dly$1656[0:0]$2253 \wr_pick_dly$1656$next + assign $0\wr_pick_dly$1654[0:0]$2253 \wr_pick_dly$1654$next sync posedge \coresync_clk - update \wr_pick_dly$1656 $0\wr_pick_dly$1656[0:0]$2253 + update \wr_pick_dly$1654 $0\wr_pick_dly$1654[0:0]$2253 end - attribute \src "libresoc.v:42844.3-42845.51" - process $proc$libresoc.v:42844$2254 + attribute \src "libresoc.v:42648.3-42649.51" + process $proc$libresoc.v:42648$2254 assign { } { } - assign $0\wr_pick_dly$1637[0:0]$2255 \wr_pick_dly$1637$next + assign $0\wr_pick_dly$1635[0:0]$2255 \wr_pick_dly$1635$next sync posedge \coresync_clk - update \wr_pick_dly$1637 $0\wr_pick_dly$1637[0:0]$2255 + update \wr_pick_dly$1635 $0\wr_pick_dly$1635[0:0]$2255 end - attribute \src "libresoc.v:42846.3-42847.51" - process $proc$libresoc.v:42846$2256 + attribute \src "libresoc.v:42650.3-42651.51" + process $proc$libresoc.v:42650$2256 assign { } { } - assign $0\wr_pick_dly$1595[0:0]$2257 \wr_pick_dly$1595$next + assign $0\wr_pick_dly$1593[0:0]$2257 \wr_pick_dly$1593$next sync posedge \coresync_clk - update \wr_pick_dly$1595 $0\wr_pick_dly$1595[0:0]$2257 + update \wr_pick_dly$1593 $0\wr_pick_dly$1593[0:0]$2257 end - attribute \src "libresoc.v:42848.3-42849.51" - process $proc$libresoc.v:42848$2258 + attribute \src "libresoc.v:42652.3-42653.51" + process $proc$libresoc.v:42652$2258 assign { } { } - assign $0\wr_pick_dly$1579[0:0]$2259 \wr_pick_dly$1579$next + assign $0\wr_pick_dly$1577[0:0]$2259 \wr_pick_dly$1577$next sync posedge \coresync_clk - update \wr_pick_dly$1579 $0\wr_pick_dly$1579[0:0]$2259 + update \wr_pick_dly$1577 $0\wr_pick_dly$1577[0:0]$2259 end - attribute \src "libresoc.v:42850.3-42851.51" - process $proc$libresoc.v:42850$2260 + attribute \src "libresoc.v:42654.3-42655.51" + process $proc$libresoc.v:42654$2260 assign { } { } - assign $0\wr_pick_dly$1563[0:0]$2261 \wr_pick_dly$1563$next + assign $0\wr_pick_dly$1561[0:0]$2261 \wr_pick_dly$1561$next sync posedge \coresync_clk - update \wr_pick_dly$1563 $0\wr_pick_dly$1563[0:0]$2261 + update \wr_pick_dly$1561 $0\wr_pick_dly$1561[0:0]$2261 end - attribute \src "libresoc.v:42852.3-42853.51" - process $proc$libresoc.v:42852$2262 + attribute \src "libresoc.v:42656.3-42657.51" + process $proc$libresoc.v:42656$2262 assign { } { } - assign $0\wr_pick_dly$1547[0:0]$2263 \wr_pick_dly$1547$next + assign $0\wr_pick_dly$1545[0:0]$2263 \wr_pick_dly$1545$next sync posedge \coresync_clk - update \wr_pick_dly$1547 $0\wr_pick_dly$1547[0:0]$2263 + update \wr_pick_dly$1545 $0\wr_pick_dly$1545[0:0]$2263 end - attribute \src "libresoc.v:42854.3-42855.51" - process $proc$libresoc.v:42854$2264 + attribute \src "libresoc.v:42658.3-42659.51" + process $proc$libresoc.v:42658$2264 assign { } { } - assign $0\wr_pick_dly$1511[0:0]$2265 \wr_pick_dly$1511$next + assign $0\wr_pick_dly$1509[0:0]$2265 \wr_pick_dly$1509$next sync posedge \coresync_clk - update \wr_pick_dly$1511 $0\wr_pick_dly$1511[0:0]$2265 + update \wr_pick_dly$1509 $0\wr_pick_dly$1509[0:0]$2265 end - attribute \src "libresoc.v:42856.3-42857.51" - process $proc$libresoc.v:42856$2266 + attribute \src "libresoc.v:42660.3-42661.51" + process $proc$libresoc.v:42660$2266 assign { } { } - assign $0\wr_pick_dly$1495[0:0]$2267 \wr_pick_dly$1495$next + assign $0\wr_pick_dly$1493[0:0]$2267 \wr_pick_dly$1493$next sync posedge \coresync_clk - update \wr_pick_dly$1495 $0\wr_pick_dly$1495[0:0]$2267 + update \wr_pick_dly$1493 $0\wr_pick_dly$1493[0:0]$2267 end - attribute \src "libresoc.v:42858.3-42859.51" - process $proc$libresoc.v:42858$2268 + attribute \src "libresoc.v:42662.3-42663.51" + process $proc$libresoc.v:42662$2268 assign { } { } - assign $0\wr_pick_dly$1479[0:0]$2269 \wr_pick_dly$1479$next + assign $0\wr_pick_dly$1477[0:0]$2269 \wr_pick_dly$1477$next sync posedge \coresync_clk - update \wr_pick_dly$1479 $0\wr_pick_dly$1479[0:0]$2269 + update \wr_pick_dly$1477 $0\wr_pick_dly$1477[0:0]$2269 end - attribute \src "libresoc.v:42860.3-42861.51" - process $proc$libresoc.v:42860$2270 + attribute \src "libresoc.v:42664.3-42665.51" + process $proc$libresoc.v:42664$2270 assign { } { } - assign $0\wr_pick_dly$1463[0:0]$2271 \wr_pick_dly$1463$next + assign $0\wr_pick_dly$1461[0:0]$2271 \wr_pick_dly$1461$next sync posedge \coresync_clk - update \wr_pick_dly$1463 $0\wr_pick_dly$1463[0:0]$2271 + update \wr_pick_dly$1461 $0\wr_pick_dly$1461[0:0]$2271 end - attribute \src "libresoc.v:42862.3-42863.51" - process $proc$libresoc.v:42862$2272 + attribute \src "libresoc.v:42666.3-42667.51" + process $proc$libresoc.v:42666$2272 assign { } { } - assign $0\wr_pick_dly$1429[0:0]$2273 \wr_pick_dly$1429$next + assign $0\wr_pick_dly$1427[0:0]$2273 \wr_pick_dly$1427$next sync posedge \coresync_clk - update \wr_pick_dly$1429 $0\wr_pick_dly$1429[0:0]$2273 + update \wr_pick_dly$1427 $0\wr_pick_dly$1427[0:0]$2273 end - attribute \src "libresoc.v:42864.3-42865.51" - process $proc$libresoc.v:42864$2274 + attribute \src "libresoc.v:42668.3-42669.51" + process $proc$libresoc.v:42668$2274 assign { } { } - assign $0\wr_pick_dly$1413[0:0]$2275 \wr_pick_dly$1413$next + assign $0\wr_pick_dly$1411[0:0]$2275 \wr_pick_dly$1411$next sync posedge \coresync_clk - update \wr_pick_dly$1413 $0\wr_pick_dly$1413[0:0]$2275 + update \wr_pick_dly$1411 $0\wr_pick_dly$1411[0:0]$2275 end - attribute \src "libresoc.v:42866.3-42867.51" - process $proc$libresoc.v:42866$2276 + attribute \src "libresoc.v:42670.3-42671.51" + process $proc$libresoc.v:42670$2276 assign { } { } - assign $0\wr_pick_dly$1397[0:0]$2277 \wr_pick_dly$1397$next + assign $0\wr_pick_dly$1395[0:0]$2277 \wr_pick_dly$1395$next sync posedge \coresync_clk - update \wr_pick_dly$1397 $0\wr_pick_dly$1397[0:0]$2277 + update \wr_pick_dly$1395 $0\wr_pick_dly$1395[0:0]$2277 end - attribute \src "libresoc.v:42868.3-42869.51" - process $proc$libresoc.v:42868$2278 + attribute \src "libresoc.v:42672.3-42673.51" + process $proc$libresoc.v:42672$2278 assign { } { } - assign $0\wr_pick_dly$1350[0:0]$2279 \wr_pick_dly$1350$next + assign $0\wr_pick_dly$1348[0:0]$2279 \wr_pick_dly$1348$next sync posedge \coresync_clk - update \wr_pick_dly$1350 $0\wr_pick_dly$1350[0:0]$2279 + update \wr_pick_dly$1348 $0\wr_pick_dly$1348[0:0]$2279 end - attribute \src "libresoc.v:42870.3-42871.51" - process $proc$libresoc.v:42870$2280 + attribute \src "libresoc.v:42674.3-42675.51" + process $proc$libresoc.v:42674$2280 assign { } { } - assign $0\wr_pick_dly$1330[0:0]$2281 \wr_pick_dly$1330$next + assign $0\wr_pick_dly$1328[0:0]$2281 \wr_pick_dly$1328$next sync posedge \coresync_clk - update \wr_pick_dly$1330 $0\wr_pick_dly$1330[0:0]$2281 + update \wr_pick_dly$1328 $0\wr_pick_dly$1328[0:0]$2281 end - attribute \src "libresoc.v:42872.3-42873.51" - process $proc$libresoc.v:42872$2282 + attribute \src "libresoc.v:42676.3-42677.51" + process $proc$libresoc.v:42676$2282 assign { } { } - assign $0\wr_pick_dly$1310[0:0]$2283 \wr_pick_dly$1310$next + assign $0\wr_pick_dly$1308[0:0]$2283 \wr_pick_dly$1308$next sync posedge \coresync_clk - update \wr_pick_dly$1310 $0\wr_pick_dly$1310[0:0]$2283 + update \wr_pick_dly$1308 $0\wr_pick_dly$1308[0:0]$2283 end - attribute \src "libresoc.v:42874.3-42875.51" - process $proc$libresoc.v:42874$2284 + attribute \src "libresoc.v:42678.3-42679.51" + process $proc$libresoc.v:42678$2284 assign { } { } - assign $0\wr_pick_dly$1290[0:0]$2285 \wr_pick_dly$1290$next + assign $0\wr_pick_dly$1288[0:0]$2285 \wr_pick_dly$1288$next sync posedge \coresync_clk - update \wr_pick_dly$1290 $0\wr_pick_dly$1290[0:0]$2285 + update \wr_pick_dly$1288 $0\wr_pick_dly$1288[0:0]$2285 end - attribute \src "libresoc.v:42876.3-42877.51" - process $proc$libresoc.v:42876$2286 + attribute \src "libresoc.v:42680.3-42681.51" + process $proc$libresoc.v:42680$2286 assign { } { } - assign $0\wr_pick_dly$1270[0:0]$2287 \wr_pick_dly$1270$next + assign $0\wr_pick_dly$1268[0:0]$2287 \wr_pick_dly$1268$next sync posedge \coresync_clk - update \wr_pick_dly$1270 $0\wr_pick_dly$1270[0:0]$2287 + update \wr_pick_dly$1268 $0\wr_pick_dly$1268[0:0]$2287 end - attribute \src "libresoc.v:42878.3-42879.51" - process $proc$libresoc.v:42878$2288 + attribute \src "libresoc.v:42682.3-42683.51" + process $proc$libresoc.v:42682$2288 assign { } { } - assign $0\wr_pick_dly$1250[0:0]$2289 \wr_pick_dly$1250$next + assign $0\wr_pick_dly$1248[0:0]$2289 \wr_pick_dly$1248$next sync posedge \coresync_clk - update \wr_pick_dly$1250 $0\wr_pick_dly$1250[0:0]$2289 + update \wr_pick_dly$1248 $0\wr_pick_dly$1248[0:0]$2289 end - attribute \src "libresoc.v:42880.3-42881.51" - process $proc$libresoc.v:42880$2290 + attribute \src "libresoc.v:42684.3-42685.51" + process $proc$libresoc.v:42684$2290 assign { } { } - assign $0\wr_pick_dly$1222[0:0]$2291 \wr_pick_dly$1222$next + assign $0\wr_pick_dly$1220[0:0]$2291 \wr_pick_dly$1220$next sync posedge \coresync_clk - update \wr_pick_dly$1222 $0\wr_pick_dly$1222[0:0]$2291 + update \wr_pick_dly$1220 $0\wr_pick_dly$1220[0:0]$2291 end - attribute \src "libresoc.v:42882.3-42883.51" - process $proc$libresoc.v:42882$2292 + attribute \src "libresoc.v:42686.3-42687.51" + process $proc$libresoc.v:42686$2292 assign { } { } - assign $0\wr_pick_dly$1148[0:0]$2293 \wr_pick_dly$1148$next + assign $0\wr_pick_dly$1146[0:0]$2293 \wr_pick_dly$1146$next sync posedge \coresync_clk - update \wr_pick_dly$1148 $0\wr_pick_dly$1148[0:0]$2293 + update \wr_pick_dly$1146 $0\wr_pick_dly$1146[0:0]$2293 end - attribute \src "libresoc.v:42884.3-42885.51" - process $proc$libresoc.v:42884$2294 + attribute \src "libresoc.v:42688.3-42689.51" + process $proc$libresoc.v:42688$2294 assign { } { } - assign $0\wr_pick_dly$1130[0:0]$2295 \wr_pick_dly$1130$next + assign $0\wr_pick_dly$1128[0:0]$2295 \wr_pick_dly$1128$next sync posedge \coresync_clk - update \wr_pick_dly$1130 $0\wr_pick_dly$1130[0:0]$2295 + update \wr_pick_dly$1128 $0\wr_pick_dly$1128[0:0]$2295 end - attribute \src "libresoc.v:42886.3-42887.51" - process $proc$libresoc.v:42886$2296 + attribute \src "libresoc.v:42690.3-42691.51" + process $proc$libresoc.v:42690$2296 assign { } { } - assign $0\wr_pick_dly$1111[0:0]$2297 \wr_pick_dly$1111$next + assign $0\wr_pick_dly$1109[0:0]$2297 \wr_pick_dly$1109$next sync posedge \coresync_clk - update \wr_pick_dly$1111 $0\wr_pick_dly$1111[0:0]$2297 + update \wr_pick_dly$1109 $0\wr_pick_dly$1109[0:0]$2297 end - attribute \src "libresoc.v:42888.3-42889.51" - process $proc$libresoc.v:42888$2298 + attribute \src "libresoc.v:42692.3-42693.51" + process $proc$libresoc.v:42692$2298 assign { } { } - assign $0\wr_pick_dly$1091[0:0]$2299 \wr_pick_dly$1091$next + assign $0\wr_pick_dly$1089[0:0]$2299 \wr_pick_dly$1089$next sync posedge \coresync_clk - update \wr_pick_dly$1091 $0\wr_pick_dly$1091[0:0]$2299 + update \wr_pick_dly$1089 $0\wr_pick_dly$1089[0:0]$2299 end - attribute \src "libresoc.v:42890.3-42891.51" - process $proc$libresoc.v:42890$2300 + attribute \src "libresoc.v:42694.3-42695.51" + process $proc$libresoc.v:42694$2300 assign { } { } - assign $0\wr_pick_dly$1071[0:0]$2301 \wr_pick_dly$1071$next + assign $0\wr_pick_dly$1069[0:0]$2301 \wr_pick_dly$1069$next sync posedge \coresync_clk - update \wr_pick_dly$1071 $0\wr_pick_dly$1071[0:0]$2301 + update \wr_pick_dly$1069 $0\wr_pick_dly$1069[0:0]$2301 end - attribute \src "libresoc.v:42892.3-42893.51" - process $proc$libresoc.v:42892$2302 + attribute \src "libresoc.v:42696.3-42697.51" + process $proc$libresoc.v:42696$2302 assign { } { } - assign $0\wr_pick_dly$1049[0:0]$2303 \wr_pick_dly$1049$next + assign $0\wr_pick_dly$1047[0:0]$2303 \wr_pick_dly$1047$next sync posedge \coresync_clk - update \wr_pick_dly$1049 $0\wr_pick_dly$1049[0:0]$2303 + update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2303 end - attribute \src "libresoc.v:42894.3-42895.51" - process $proc$libresoc.v:42894$2304 + attribute \src "libresoc.v:42698.3-42699.51" + process $proc$libresoc.v:42698$2304 assign { } { } - assign $0\wr_pick_dly$1031[0:0]$2305 \wr_pick_dly$1031$next + assign $0\wr_pick_dly$1029[0:0]$2305 \wr_pick_dly$1029$next sync posedge \coresync_clk - update \wr_pick_dly$1031 $0\wr_pick_dly$1031[0:0]$2305 + update \wr_pick_dly$1029 $0\wr_pick_dly$1029[0:0]$2305 end - attribute \src "libresoc.v:42896.3-42897.51" - process $proc$libresoc.v:42896$2306 + attribute \src "libresoc.v:42700.3-42701.51" + process $proc$libresoc.v:42700$2306 assign { } { } - assign $0\wr_pick_dly$1010[0:0]$2307 \wr_pick_dly$1010$next + assign $0\wr_pick_dly$1008[0:0]$2307 \wr_pick_dly$1008$next sync posedge \coresync_clk - update \wr_pick_dly$1010 $0\wr_pick_dly$1010[0:0]$2307 + update \wr_pick_dly$1008 $0\wr_pick_dly$1008[0:0]$2307 end - attribute \src "libresoc.v:42898.3-42899.49" - process $proc$libresoc.v:42898$2308 + attribute \src "libresoc.v:42702.3-42703.49" + process $proc$libresoc.v:42702$2308 assign { } { } - assign $0\wr_pick_dly$991[0:0]$2309 \wr_pick_dly$991$next + assign $0\wr_pick_dly$989[0:0]$2309 \wr_pick_dly$989$next sync posedge \coresync_clk - update \wr_pick_dly$991 $0\wr_pick_dly$991[0:0]$2309 + update \wr_pick_dly$989 $0\wr_pick_dly$989[0:0]$2309 end - attribute \src "libresoc.v:42900.3-42901.39" - process $proc$libresoc.v:42900$2310 + attribute \src "libresoc.v:42704.3-42705.39" + process $proc$libresoc.v:42704$2310 assign { } { } assign $0\wr_pick_dly[0:0] \wr_pick_dly$next sync posedge \coresync_clk update \wr_pick_dly $0\wr_pick_dly[0:0] end - attribute \src "libresoc.v:42902.3-42903.53" - process $proc$libresoc.v:42902$2311 + attribute \src "libresoc.v:42706.3-42707.53" + process $proc$libresoc.v:42706$2311 assign { } { } assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next sync posedge \coresync_clk update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] end - attribute \src "libresoc.v:42904.3-42905.59" - process $proc$libresoc.v:42904$2312 + attribute \src "libresoc.v:42708.3-42709.59" + process $proc$libresoc.v:42708$2312 assign { } { } - assign $0\dp_FAST_fast2_trap0_1[0:0] \dp_FAST_fast2_trap0_1$next + assign $0\dp_FAST_fast1_trap0_4[0:0] \dp_FAST_fast1_trap0_4$next sync posedge \coresync_clk - update \dp_FAST_fast2_trap0_1 $0\dp_FAST_fast2_trap0_1[0:0] + update \dp_FAST_fast1_trap0_4 $0\dp_FAST_fast1_trap0_4[0:0] end - attribute \src "libresoc.v:42906.3-42907.63" - process $proc$libresoc.v:42906$2313 + attribute \src "libresoc.v:42710.3-42711.63" + process $proc$libresoc.v:42710$2313 assign { } { } - assign $0\dp_FAST_fast2_branch0_0[0:0] \dp_FAST_fast2_branch0_0$next + assign $0\dp_FAST_fast1_branch0_3[0:0] \dp_FAST_fast1_branch0_3$next sync posedge \coresync_clk - update \dp_FAST_fast2_branch0_0 $0\dp_FAST_fast2_branch0_0[0:0] + update \dp_FAST_fast1_branch0_3 $0\dp_FAST_fast1_branch0_3[0:0] end - attribute \src "libresoc.v:42908.3-42909.57" - process $proc$libresoc.v:42908$2314 + attribute \src "libresoc.v:42712.3-42713.57" + process $proc$libresoc.v:42712$2314 assign { } { } assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next sync posedge \coresync_clk update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] end - attribute \src "libresoc.v:42910.3-42911.59" - process $proc$libresoc.v:42910$2315 + attribute \src "libresoc.v:42714.3-42715.59" + process $proc$libresoc.v:42714$2315 assign { } { } assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next sync posedge \coresync_clk update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] end - attribute \src "libresoc.v:42912.3-42913.63" - process $proc$libresoc.v:42912$2316 + attribute \src "libresoc.v:42716.3-42717.63" + process $proc$libresoc.v:42716$2316 assign { } { } assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next sync posedge \coresync_clk update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] end - attribute \src "libresoc.v:42914.3-42915.49" - process $proc$libresoc.v:42914$2317 + attribute \src "libresoc.v:42718.3-42719.49" + process $proc$libresoc.v:42718$2317 assign { } { } assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] end - attribute \src "libresoc.v:42916.3-42917.49" - process $proc$libresoc.v:42916$2318 + attribute \src "libresoc.v:42720.3-42721.49" + process $proc$libresoc.v:42720$2318 assign { } { } assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] end - attribute \src "libresoc.v:42918.3-42919.57" - process $proc$libresoc.v:42918$2319 + attribute \src "libresoc.v:42722.3-42723.57" + process $proc$libresoc.v:42722$2319 assign { } { } assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next sync posedge \coresync_clk update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] end - attribute \src "libresoc.v:42920.3-42921.49" - process $proc$libresoc.v:42920$2320 + attribute \src "libresoc.v:42724.3-42725.49" + process $proc$libresoc.v:42724$2320 assign { } { } assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] end - attribute \src "libresoc.v:42922.3-42923.55" - process $proc$libresoc.v:42922$2321 + attribute \src "libresoc.v:42726.3-42727.55" + process $proc$libresoc.v:42726$2321 assign { } { } assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next sync posedge \coresync_clk update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] end - attribute \src "libresoc.v:42924.3-42925.57" - process $proc$libresoc.v:42924$2322 + attribute \src "libresoc.v:42728.3-42729.57" + process $proc$libresoc.v:42728$2322 assign { } { } assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next sync posedge \coresync_clk update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] end - attribute \src "libresoc.v:42926.3-42927.67" - process $proc$libresoc.v:42926$2323 + attribute \src "libresoc.v:42730.3-42731.67" + process $proc$libresoc.v:42730$2323 assign { } { } assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next sync posedge \coresync_clk update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] end - attribute \src "libresoc.v:42928.3-42929.57" - process $proc$libresoc.v:42928$2324 + attribute \src "libresoc.v:42732.3-42733.57" + process $proc$libresoc.v:42732$2324 assign { } { } assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next sync posedge \coresync_clk update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] end - attribute \src "libresoc.v:42930.3-42931.57" - process $proc$libresoc.v:42930$2325 + attribute \src "libresoc.v:42734.3-42735.57" + process $proc$libresoc.v:42734$2325 assign { } { } assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] end - attribute \src "libresoc.v:42932.3-42933.67" - process $proc$libresoc.v:42932$2326 + attribute \src "libresoc.v:42736.3-42737.67" + process $proc$libresoc.v:42736$2326 assign { } { } assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next sync posedge \coresync_clk update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] end - attribute \src "libresoc.v:42934.3-42935.57" - process $proc$libresoc.v:42934$2327 + attribute \src "libresoc.v:42738.3-42739.57" + process $proc$libresoc.v:42738$2327 assign { } { } assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next sync posedge \coresync_clk update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] end - attribute \src "libresoc.v:42936.3-42937.57" - process $proc$libresoc.v:42936$2328 + attribute \src "libresoc.v:42740.3-42741.57" + process $proc$libresoc.v:42740$2328 assign { } { } assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next sync posedge \coresync_clk update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] end - attribute \src "libresoc.v:42938.3-42939.57" - process $proc$libresoc.v:42938$2329 + attribute \src "libresoc.v:42742.3-42743.57" + process $proc$libresoc.v:42742$2329 assign { } { } assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next sync posedge \coresync_clk update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] end - attribute \src "libresoc.v:42940.3-42941.65" - process $proc$libresoc.v:42940$2330 + attribute \src "libresoc.v:42744.3-42745.65" + process $proc$libresoc.v:42744$2330 assign { } { } assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next sync posedge \coresync_clk update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] end - attribute \src "libresoc.v:42942.3-42943.57" - process $proc$libresoc.v:42942$2331 + attribute \src "libresoc.v:42746.3-42747.57" + process $proc$libresoc.v:42746$2331 assign { } { } assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] end - attribute \src "libresoc.v:42944.3-42945.51" - process $proc$libresoc.v:42944$2332 + attribute \src "libresoc.v:42748.3-42749.57" + process $proc$libresoc.v:42748$2332 assign { } { } - assign $0\dp_INT_rc_ldst0_1[0:0] \dp_INT_rc_ldst0_1$next + assign $0\dp_INT_rabc_ldst0_18[0:0] \dp_INT_rabc_ldst0_18$next sync posedge \coresync_clk - update \dp_INT_rc_ldst0_1 $0\dp_INT_rc_ldst0_1[0:0] + update \dp_INT_rabc_ldst0_18 $0\dp_INT_rabc_ldst0_18[0:0] end - attribute \src "libresoc.v:42946.3-42947.59" - process $proc$libresoc.v:42946$2333 + attribute \src "libresoc.v:42750.3-42751.65" + process $proc$libresoc.v:42750$2333 assign { } { } - assign $0\dp_INT_rc_shiftrot0_0[0:0] \dp_INT_rc_shiftrot0_0$next + assign $0\dp_INT_rabc_shiftrot0_17[0:0] \dp_INT_rabc_shiftrot0_17$next sync posedge \coresync_clk - update \dp_INT_rc_shiftrot0_0 $0\dp_INT_rc_shiftrot0_0[0:0] + update \dp_INT_rabc_shiftrot0_17 $0\dp_INT_rabc_shiftrot0_17[0:0] end - attribute \src "libresoc.v:42948.3-42949.51" - process $proc$libresoc.v:42948$2334 + attribute \src "libresoc.v:42752.3-42753.55" + process $proc$libresoc.v:42752$2334 assign { } { } - assign $0\dp_INT_rb_ldst0_7[0:0] \dp_INT_rb_ldst0_7$next + assign $0\dp_INT_rabc_mul0_16[0:0] \dp_INT_rabc_mul0_16$next sync posedge \coresync_clk - update \dp_INT_rb_ldst0_7 $0\dp_INT_rb_ldst0_7[0:0] + update \dp_INT_rabc_mul0_16 $0\dp_INT_rabc_mul0_16[0:0] end - attribute \src "libresoc.v:42950.3-42951.59" - process $proc$libresoc.v:42950$2335 + attribute \src "libresoc.v:42754.3-42755.55" + process $proc$libresoc.v:42754$2335 assign { } { } - assign $0\dp_INT_rb_shiftrot0_6[0:0] \dp_INT_rb_shiftrot0_6$next + assign $0\dp_INT_rabc_div0_15[0:0] \dp_INT_rabc_div0_15$next sync posedge \coresync_clk - update \dp_INT_rb_shiftrot0_6 $0\dp_INT_rb_shiftrot0_6[0:0] + update \dp_INT_rabc_div0_15 $0\dp_INT_rabc_div0_15[0:0] end - attribute \src "libresoc.v:42952.3-42953.49" - process $proc$libresoc.v:42952$2336 + attribute \src "libresoc.v:42756.3-42757.55" + process $proc$libresoc.v:42756$2336 assign { } { } - assign $0\dp_INT_rb_mul0_5[0:0] \dp_INT_rb_mul0_5$next + assign $0\dp_INT_rabc_spr0_14[0:0] \dp_INT_rabc_spr0_14$next sync posedge \coresync_clk - update \dp_INT_rb_mul0_5 $0\dp_INT_rb_mul0_5[0:0] + update \dp_INT_rabc_spr0_14 $0\dp_INT_rabc_spr0_14[0:0] end - attribute \src "libresoc.v:42954.3-42955.49" - process $proc$libresoc.v:42954$2337 + attribute \src "libresoc.v:42758.3-42759.63" + process $proc$libresoc.v:42758$2337 assign { } { } - assign $0\dp_INT_rb_div0_4[0:0] \dp_INT_rb_div0_4$next + assign $0\dp_INT_rabc_logical0_13[0:0] \dp_INT_rabc_logical0_13$next sync posedge \coresync_clk - update \dp_INT_rb_div0_4 $0\dp_INT_rb_div0_4[0:0] + update \dp_INT_rabc_logical0_13 $0\dp_INT_rabc_logical0_13[0:0] end - attribute \src "libresoc.v:42956.3-42957.57" - process $proc$libresoc.v:42956$2338 + attribute \src "libresoc.v:42760.3-42761.57" + process $proc$libresoc.v:42760$2338 assign { } { } - assign $0\dp_INT_rb_logical0_3[0:0] \dp_INT_rb_logical0_3$next + assign $0\dp_INT_rabc_trap0_12[0:0] \dp_INT_rabc_trap0_12$next sync posedge \coresync_clk - update \dp_INT_rb_logical0_3 $0\dp_INT_rb_logical0_3[0:0] + update \dp_INT_rabc_trap0_12 $0\dp_INT_rabc_trap0_12[0:0] end - attribute \src "libresoc.v:42958.3-42959.51" - process $proc$libresoc.v:42958$2339 + attribute \src "libresoc.v:42762.3-42763.53" + process $proc$libresoc.v:42762$2339 assign { } { } - assign $0\dp_INT_rb_trap0_2[0:0] \dp_INT_rb_trap0_2$next + assign $0\dp_INT_rabc_cr0_11[0:0] \dp_INT_rabc_cr0_11$next sync posedge \coresync_clk - update \dp_INT_rb_trap0_2 $0\dp_INT_rb_trap0_2[0:0] + update \dp_INT_rabc_cr0_11 $0\dp_INT_rabc_cr0_11[0:0] end - attribute \src "libresoc.v:42960.3-42961.47" - process $proc$libresoc.v:42960$2340 + attribute \src "libresoc.v:42764.3-42765.55" + process $proc$libresoc.v:42764$2340 assign { } { } - assign $0\dp_INT_rb_cr0_1[0:0] \dp_INT_rb_cr0_1$next + assign $0\dp_INT_rabc_alu0_10[0:0] \dp_INT_rabc_alu0_10$next sync posedge \coresync_clk - update \dp_INT_rb_cr0_1 $0\dp_INT_rb_cr0_1[0:0] + update \dp_INT_rabc_alu0_10 $0\dp_INT_rabc_alu0_10[0:0] end - attribute \src "libresoc.v:42962.3-42963.49" - process $proc$libresoc.v:42962$2341 + attribute \src "libresoc.v:42766.3-42767.55" + process $proc$libresoc.v:42766$2341 assign { } { } - assign $0\dp_INT_rb_alu0_0[0:0] \dp_INT_rb_alu0_0$next + assign $0\dp_INT_rabc_ldst0_9[0:0] \dp_INT_rabc_ldst0_9$next sync posedge \coresync_clk - update \dp_INT_rb_alu0_0 $0\dp_INT_rb_alu0_0[0:0] + update \dp_INT_rabc_ldst0_9 $0\dp_INT_rabc_ldst0_9[0:0] end - attribute \src "libresoc.v:42964.3-42965.51" - process $proc$libresoc.v:42964$2342 + attribute \src "libresoc.v:42768.3-42769.63" + process $proc$libresoc.v:42768$2342 assign { } { } - assign $0\dp_INT_ra_ldst0_8[0:0] \dp_INT_ra_ldst0_8$next + assign $0\dp_INT_rabc_shiftrot0_8[0:0] \dp_INT_rabc_shiftrot0_8$next sync posedge \coresync_clk - update \dp_INT_ra_ldst0_8 $0\dp_INT_ra_ldst0_8[0:0] + update \dp_INT_rabc_shiftrot0_8 $0\dp_INT_rabc_shiftrot0_8[0:0] end - attribute \src "libresoc.v:42966.3-42967.59" - process $proc$libresoc.v:42966$2343 + attribute \src "libresoc.v:42770.3-42771.55" + process $proc$libresoc.v:42770$2343 assign { } { } - assign $0\dp_INT_ra_shiftrot0_7[0:0] \dp_INT_ra_shiftrot0_7$next + assign $0\dp_INT_rabc_ldst0_7[0:0] \dp_INT_rabc_ldst0_7$next sync posedge \coresync_clk - update \dp_INT_ra_shiftrot0_7 $0\dp_INT_ra_shiftrot0_7[0:0] + update \dp_INT_rabc_ldst0_7 $0\dp_INT_rabc_ldst0_7[0:0] end - attribute \src "libresoc.v:42968.3-42969.49" - process $proc$libresoc.v:42968$2344 + attribute \src "libresoc.v:42772.3-42773.63" + process $proc$libresoc.v:42772$2344 assign { } { } - assign $0\dp_INT_ra_mul0_6[0:0] \dp_INT_ra_mul0_6$next + assign $0\dp_INT_rabc_shiftrot0_6[0:0] \dp_INT_rabc_shiftrot0_6$next sync posedge \coresync_clk - update \dp_INT_ra_mul0_6 $0\dp_INT_ra_mul0_6[0:0] + update \dp_INT_rabc_shiftrot0_6 $0\dp_INT_rabc_shiftrot0_6[0:0] end - attribute \src "libresoc.v:42970.3-42971.49" - process $proc$libresoc.v:42970$2345 + attribute \src "libresoc.v:42774.3-42775.53" + process $proc$libresoc.v:42774$2345 assign { } { } - assign $0\dp_INT_ra_div0_5[0:0] \dp_INT_ra_div0_5$next + assign $0\dp_INT_rabc_mul0_5[0:0] \dp_INT_rabc_mul0_5$next sync posedge \coresync_clk - update \dp_INT_ra_div0_5 $0\dp_INT_ra_div0_5[0:0] + update \dp_INT_rabc_mul0_5 $0\dp_INT_rabc_mul0_5[0:0] end - attribute \src "libresoc.v:42972.3-42973.49" - process $proc$libresoc.v:42972$2346 + attribute \src "libresoc.v:42776.3-42777.53" + process $proc$libresoc.v:42776$2346 assign { } { } - assign $0\dp_INT_ra_spr0_4[0:0] \dp_INT_ra_spr0_4$next + assign $0\dp_INT_rabc_div0_4[0:0] \dp_INT_rabc_div0_4$next sync posedge \coresync_clk - update \dp_INT_ra_spr0_4 $0\dp_INT_ra_spr0_4[0:0] + update \dp_INT_rabc_div0_4 $0\dp_INT_rabc_div0_4[0:0] end - attribute \src "libresoc.v:42974.3-42975.57" - process $proc$libresoc.v:42974$2347 + attribute \src "libresoc.v:42778.3-42779.61" + process $proc$libresoc.v:42778$2347 assign { } { } - assign $0\dp_INT_ra_logical0_3[0:0] \dp_INT_ra_logical0_3$next + assign $0\dp_INT_rabc_logical0_3[0:0] \dp_INT_rabc_logical0_3$next sync posedge \coresync_clk - update \dp_INT_ra_logical0_3 $0\dp_INT_ra_logical0_3[0:0] + update \dp_INT_rabc_logical0_3 $0\dp_INT_rabc_logical0_3[0:0] end - attribute \src "libresoc.v:42976.3-42977.51" - process $proc$libresoc.v:42976$2348 + attribute \src "libresoc.v:42780.3-42781.55" + process $proc$libresoc.v:42780$2348 assign { } { } - assign $0\dp_INT_ra_trap0_2[0:0] \dp_INT_ra_trap0_2$next + assign $0\dp_INT_rabc_trap0_2[0:0] \dp_INT_rabc_trap0_2$next sync posedge \coresync_clk - update \dp_INT_ra_trap0_2 $0\dp_INT_ra_trap0_2[0:0] + update \dp_INT_rabc_trap0_2 $0\dp_INT_rabc_trap0_2[0:0] end - attribute \src "libresoc.v:42978.3-42979.47" - process $proc$libresoc.v:42978$2349 + attribute \src "libresoc.v:42782.3-42783.51" + process $proc$libresoc.v:42782$2349 assign { } { } - assign $0\dp_INT_ra_cr0_1[0:0] \dp_INT_ra_cr0_1$next + assign $0\dp_INT_rabc_cr0_1[0:0] \dp_INT_rabc_cr0_1$next sync posedge \coresync_clk - update \dp_INT_ra_cr0_1 $0\dp_INT_ra_cr0_1[0:0] + update \dp_INT_rabc_cr0_1 $0\dp_INT_rabc_cr0_1[0:0] end - attribute \src "libresoc.v:42980.3-42981.49" - process $proc$libresoc.v:42980$2350 + attribute \src "libresoc.v:42784.3-42785.53" + process $proc$libresoc.v:42784$2350 assign { } { } - assign $0\dp_INT_ra_alu0_0[0:0] \dp_INT_ra_alu0_0$next + assign $0\dp_INT_rabc_alu0_0[0:0] \dp_INT_rabc_alu0_0$next sync posedge \coresync_clk - update \dp_INT_ra_alu0_0 $0\dp_INT_ra_alu0_0[0:0] + update \dp_INT_rabc_alu0_0 $0\dp_INT_rabc_alu0_0[0:0] end - attribute \src "libresoc.v:42982.3-42983.49" - process $proc$libresoc.v:42982$2351 + attribute \src "libresoc.v:42786.3-42787.49" + process $proc$libresoc.v:42786$2351 assign { } { } assign $0\core_terminate_o[0:0] \core_terminate_o$next sync posedge \coresync_clk update \core_terminate_o $0\core_terminate_o[0:0] end - attribute \src "libresoc.v:42984.3-42985.31" - process $proc$libresoc.v:42984$2352 + attribute \src "libresoc.v:42788.3-42789.31" + process $proc$libresoc.v:42788$2352 assign { } { } assign $0\counter[1:0] \counter$next sync posedge \coresync_clk update \counter $0\counter[1:0] end - attribute \src "libresoc.v:43723.3-43751.6" - process $proc$libresoc.v:43723$2353 + attribute \src "libresoc.v:43503.3-43531.6" + process $proc$libresoc.v:43503$2353 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:43724.5-43724.29" + attribute \src "libresoc.v:43504.5-43504.29" switch \initial - attribute \src "libresoc.v:43724.9-43724.17" + attribute \src "libresoc.v:43504.9-43504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75774,7 +75545,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75790,24 +75561,24 @@ module \core sync always update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] end - attribute \src "libresoc.v:43752.3-43780.6" - process $proc$libresoc.v:43752$2354 + attribute \src "libresoc.v:43532.3-43560.6" + process $proc$libresoc.v:43532$2354 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43753.5-43753.29" + attribute \src "libresoc.v:43533.5-43533.29" switch \initial - attribute \src "libresoc.v:43753.9-43753.17" + attribute \src "libresoc.v:43533.9-43533.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75819,7 +75590,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75835,24 +75606,24 @@ module \core sync always update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] end - attribute \src "libresoc.v:43781.3-43809.6" - process $proc$libresoc.v:43781$2355 + attribute \src "libresoc.v:43561.3-43589.6" + process $proc$libresoc.v:43561$2355 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:43782.5-43782.29" + attribute \src "libresoc.v:43562.5-43562.29" switch \initial - attribute \src "libresoc.v:43782.9-43782.17" + attribute \src "libresoc.v:43562.9-43562.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75864,7 +75635,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75880,24 +75651,24 @@ module \core sync always update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] end - attribute \src "libresoc.v:43810.3-43838.6" - process $proc$libresoc.v:43810$2356 + attribute \src "libresoc.v:43590.3-43618.6" + process $proc$libresoc.v:43590$2356 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:43811.5-43811.29" + attribute \src "libresoc.v:43591.5-43591.29" switch \initial - attribute \src "libresoc.v:43811.9-43811.17" + attribute \src "libresoc.v:43591.9-43591.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75909,7 +75680,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75925,24 +75696,24 @@ module \core sync always update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] end - attribute \src "libresoc.v:43839.3-43867.6" - process $proc$libresoc.v:43839$2357 + attribute \src "libresoc.v:43619.3-43647.6" + process $proc$libresoc.v:43619$2357 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:43840.5-43840.29" + attribute \src "libresoc.v:43620.5-43620.29" switch \initial - attribute \src "libresoc.v:43840.9-43840.17" + attribute \src "libresoc.v:43620.9-43620.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75954,7 +75725,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75970,24 +75741,24 @@ module \core sync always update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] end - attribute \src "libresoc.v:43868.3-43896.6" - process $proc$libresoc.v:43868$2358 + attribute \src "libresoc.v:43648.3-43676.6" + process $proc$libresoc.v:43648$2358 assign { } { } assign { } { } assign $0\fus_cu_issue_i$22[0:0]$2359 $1\fus_cu_issue_i$22[0:0]$2360 - attribute \src "libresoc.v:43869.5-43869.29" + attribute \src "libresoc.v:43649.5-43649.29" switch \initial - attribute \src "libresoc.v:43869.9-43869.17" + attribute \src "libresoc.v:43649.9-43649.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$22[0:0]$2360 $2\fus_cu_issue_i$22[0:0]$2361 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75999,7 +75770,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$22[0:0]$2361 $3\fus_cu_issue_i$22[0:0]$2362 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76015,24 +75786,24 @@ module \core sync always update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2359 end - attribute \src "libresoc.v:43897.3-43925.6" - process $proc$libresoc.v:43897$2363 + attribute \src "libresoc.v:43677.3-43705.6" + process $proc$libresoc.v:43677$2363 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$24[2:0]$2364 $1\fus_cu_rdmaskn_i$24[2:0]$2365 - attribute \src "libresoc.v:43898.5-43898.29" + attribute \src "libresoc.v:43678.5-43678.29" switch \initial - attribute \src "libresoc.v:43898.9-43898.17" + attribute \src "libresoc.v:43678.9-43678.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$24[2:0]$2365 $2\fus_cu_rdmaskn_i$24[2:0]$2366 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76044,7 +75815,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 $3\fus_cu_rdmaskn_i$24[2:0]$2367 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76060,24 +75831,24 @@ module \core sync always update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2364 end - attribute \src "libresoc.v:43926.3-43954.6" - process $proc$libresoc.v:43926$2368 + attribute \src "libresoc.v:43706.3-43734.6" + process $proc$libresoc.v:43706$2368 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43927.5-43927.29" + attribute \src "libresoc.v:43707.5-43707.29" switch \initial - attribute \src "libresoc.v:43927.9-43927.17" + attribute \src "libresoc.v:43707.9-43707.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76089,7 +75860,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76105,24 +75876,24 @@ module \core sync always update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] end - attribute \src "libresoc.v:43955.3-43983.6" - process $proc$libresoc.v:43955$2369 + attribute \src "libresoc.v:43735.3-43763.6" + process $proc$libresoc.v:43735$2369 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__fn_unit[13:0] $1\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43956.5-43956.29" + attribute \src "libresoc.v:43736.5-43736.29" switch \initial - attribute \src "libresoc.v:43956.9-43956.17" + attribute \src "libresoc.v:43736.9-43736.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__fn_unit[13:0] $2\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76134,7 +75905,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] $3\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76150,24 +75921,24 @@ module \core sync always update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[13:0] end - attribute \src "libresoc.v:43984.3-44012.6" - process $proc$libresoc.v:43984$2370 + attribute \src "libresoc.v:43764.3-43792.6" + process $proc$libresoc.v:43764$2370 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43985.5-43985.29" + attribute \src "libresoc.v:43765.5-43765.29" switch \initial - attribute \src "libresoc.v:43985.9-43985.17" + attribute \src "libresoc.v:43765.9-43765.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76179,7 +75950,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76195,24 +75966,24 @@ module \core sync always update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] end - attribute \src "libresoc.v:44013.3-44041.6" - process $proc$libresoc.v:44013$2371 + attribute \src "libresoc.v:43793.3-43821.6" + process $proc$libresoc.v:43793$2371 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:44014.5-44014.29" + attribute \src "libresoc.v:43794.5-43794.29" switch \initial - attribute \src "libresoc.v:44014.9-44014.17" + attribute \src "libresoc.v:43794.9-43794.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76224,7 +75995,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76240,24 +76011,24 @@ module \core sync always update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] end - attribute \src "libresoc.v:44042.3-44070.6" - process $proc$libresoc.v:44042$2372 + attribute \src "libresoc.v:43822.3-43850.6" + process $proc$libresoc.v:43822$2372 assign { } { } assign { } { } assign $0\fus_cu_issue_i$25[0:0]$2373 $1\fus_cu_issue_i$25[0:0]$2374 - attribute \src "libresoc.v:44043.5-44043.29" + attribute \src "libresoc.v:43823.5-43823.29" switch \initial - attribute \src "libresoc.v:44043.9-44043.17" + attribute \src "libresoc.v:43823.9-43823.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$25[0:0]$2374 $2\fus_cu_issue_i$25[0:0]$2375 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76269,7 +76040,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$25[0:0]$2375 $3\fus_cu_issue_i$25[0:0]$2376 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76285,24 +76056,24 @@ module \core sync always update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2373 end - attribute \src "libresoc.v:44071.3-44099.6" - process $proc$libresoc.v:44071$2377 + attribute \src "libresoc.v:43851.3-43879.6" + process $proc$libresoc.v:43851$2377 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$27[5:0]$2378 $1\fus_cu_rdmaskn_i$27[5:0]$2379 - attribute \src "libresoc.v:44072.5-44072.29" + attribute \src "libresoc.v:43852.5-43852.29" switch \initial - attribute \src "libresoc.v:44072.9-44072.17" + attribute \src "libresoc.v:43852.9-43852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$27[5:0]$2379 $2\fus_cu_rdmaskn_i$27[5:0]$2380 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76314,7 +76085,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 $3\fus_cu_rdmaskn_i$27[5:0]$2381 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76330,24 +76101,24 @@ module \core sync always update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[5:0]$2378 end - attribute \src "libresoc.v:44100.3-44128.6" - process $proc$libresoc.v:44100$2382 + attribute \src "libresoc.v:43880.3-43908.6" + process $proc$libresoc.v:43880$2382 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44101.5-44101.29" + attribute \src "libresoc.v:43881.5-43881.29" switch \initial - attribute \src "libresoc.v:44101.9-44101.17" + attribute \src "libresoc.v:43881.9-43881.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__insn_type[6:0] $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76359,7 +76130,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__insn_type[6:0] $3\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76375,24 +76146,24 @@ module \core sync always update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] end - attribute \src "libresoc.v:44129.3-44157.6" - process $proc$libresoc.v:44129$2383 + attribute \src "libresoc.v:43909.3-43937.6" + process $proc$libresoc.v:43909$2383 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__fn_unit[13:0] $1\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44130.5-44130.29" + attribute \src "libresoc.v:43910.5-43910.29" switch \initial - attribute \src "libresoc.v:44130.9-44130.17" + attribute \src "libresoc.v:43910.9-43910.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__fn_unit[13:0] $2\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76404,7 +76175,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__fn_unit[13:0] $3\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76420,21 +76191,21 @@ module \core sync always update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[13:0] end - attribute \src "libresoc.v:44158.3-44187.6" - process $proc$libresoc.v:44158$2384 + attribute \src "libresoc.v:43938.3-43967.6" + process $proc$libresoc.v:43938$2384 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44159.5-44159.29" + attribute \src "libresoc.v:43939.5-43939.29" switch \initial - attribute \src "libresoc.v:44159.9-44159.17" + attribute \src "libresoc.v:43939.9-43939.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76442,7 +76213,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] $2\fus_oper_i_alu_div0__imm_data__data[63:0] assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76458,7 +76229,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76478,21 +76249,21 @@ module \core update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44188.3-44217.6" - process $proc$libresoc.v:44188$2385 + attribute \src "libresoc.v:43968.3-43997.6" + process $proc$libresoc.v:43968$2385 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44189.5-44189.29" + attribute \src "libresoc.v:43969.5-43969.29" switch \initial - attribute \src "libresoc.v:44189.9-44189.17" + attribute \src "libresoc.v:43969.9-43969.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76500,7 +76271,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__rc__ok[0:0] $2\fus_oper_i_alu_div0__rc__ok[0:0] assign $1\fus_oper_i_alu_div0__rc__rc[0:0] $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76516,7 +76287,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__ok[0:0] assign $2\fus_oper_i_alu_div0__rc__rc[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76536,21 +76307,21 @@ module \core update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] end - attribute \src "libresoc.v:44218.3-44247.6" - process $proc$libresoc.v:44218$2386 + attribute \src "libresoc.v:43998.3-44027.6" + process $proc$libresoc.v:43998$2386 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44219.5-44219.29" + attribute \src "libresoc.v:43999.5-43999.29" switch \initial - attribute \src "libresoc.v:44219.9-44219.17" + attribute \src "libresoc.v:43999.9-43999.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76558,7 +76329,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__oe__oe[0:0] $2\fus_oper_i_alu_div0__oe__oe[0:0] assign $1\fus_oper_i_alu_div0__oe__ok[0:0] $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76574,7 +76345,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__oe__oe[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] assign $2\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76594,24 +76365,24 @@ module \core update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] end - attribute \src "libresoc.v:44248.3-44276.6" - process $proc$libresoc.v:44248$2387 + attribute \src "libresoc.v:44028.3-44056.6" + process $proc$libresoc.v:44028$2387 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44249.5-44249.29" + attribute \src "libresoc.v:44029.5-44029.29" switch \initial - attribute \src "libresoc.v:44249.9-44249.17" + attribute \src "libresoc.v:44029.9-44029.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__invert_in[0:0] $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76623,7 +76394,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__invert_in[0:0] $3\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76639,24 +76410,24 @@ module \core sync always update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] end - attribute \src "libresoc.v:44277.3-44305.6" - process $proc$libresoc.v:44277$2388 + attribute \src "libresoc.v:44057.3-44085.6" + process $proc$libresoc.v:44057$2388 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:44278.5-44278.29" + attribute \src "libresoc.v:44058.5-44058.29" switch \initial - attribute \src "libresoc.v:44278.9-44278.17" + attribute \src "libresoc.v:44058.9-44058.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__zero_a[0:0] $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76668,7 +76439,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__zero_a[0:0] $3\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76684,24 +76455,24 @@ module \core sync always update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] end - attribute \src "libresoc.v:44306.3-44334.6" - process $proc$libresoc.v:44306$2389 + attribute \src "libresoc.v:44086.3-44114.6" + process $proc$libresoc.v:44086$2389 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44307.5-44307.29" + attribute \src "libresoc.v:44087.5-44087.29" switch \initial - attribute \src "libresoc.v:44307.9-44307.17" + attribute \src "libresoc.v:44087.9-44087.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__input_carry[1:0] $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76713,7 +76484,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__input_carry[1:0] $3\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76729,24 +76500,24 @@ module \core sync always update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] end - attribute \src "libresoc.v:44335.3-44363.6" - process $proc$libresoc.v:44335$2390 + attribute \src "libresoc.v:44115.3-44143.6" + process $proc$libresoc.v:44115$2390 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44336.5-44336.29" + attribute \src "libresoc.v:44116.5-44116.29" switch \initial - attribute \src "libresoc.v:44336.9-44336.17" + attribute \src "libresoc.v:44116.9-44116.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__invert_out[0:0] $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76758,7 +76529,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__invert_out[0:0] $3\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76774,24 +76545,24 @@ module \core sync always update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] end - attribute \src "libresoc.v:44364.3-44392.6" - process $proc$libresoc.v:44364$2391 + attribute \src "libresoc.v:44144.3-44172.6" + process $proc$libresoc.v:44144$2391 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44365.5-44365.29" + attribute \src "libresoc.v:44145.5-44145.29" switch \initial - attribute \src "libresoc.v:44365.9-44365.17" + attribute \src "libresoc.v:44145.9-44145.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__write_cr0[0:0] $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76803,7 +76574,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__write_cr0[0:0] $3\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76819,24 +76590,24 @@ module \core sync always update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] end - attribute \src "libresoc.v:44393.3-44421.6" - process $proc$libresoc.v:44393$2392 + attribute \src "libresoc.v:44173.3-44201.6" + process $proc$libresoc.v:44173$2392 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44394.5-44394.29" + attribute \src "libresoc.v:44174.5-44174.29" switch \initial - attribute \src "libresoc.v:44394.9-44394.17" + attribute \src "libresoc.v:44174.9-44174.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__output_carry[0:0] $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76848,7 +76619,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__output_carry[0:0] $3\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76864,24 +76635,24 @@ module \core sync always update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] end - attribute \src "libresoc.v:44422.3-44450.6" - process $proc$libresoc.v:44422$2393 + attribute \src "libresoc.v:44202.3-44230.6" + process $proc$libresoc.v:44202$2393 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44423.5-44423.29" + attribute \src "libresoc.v:44203.5-44203.29" switch \initial - attribute \src "libresoc.v:44423.9-44423.17" + attribute \src "libresoc.v:44203.9-44203.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__is_32bit[0:0] $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76893,7 +76664,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__is_32bit[0:0] $3\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76909,24 +76680,24 @@ module \core sync always update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] end - attribute \src "libresoc.v:44451.3-44479.6" - process $proc$libresoc.v:44451$2394 + attribute \src "libresoc.v:44231.3-44259.6" + process $proc$libresoc.v:44231$2394 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44452.5-44452.29" + attribute \src "libresoc.v:44232.5-44232.29" switch \initial - attribute \src "libresoc.v:44452.9-44452.17" + attribute \src "libresoc.v:44232.9-44232.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__is_signed[0:0] $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76938,7 +76709,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__is_signed[0:0] $3\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76954,24 +76725,24 @@ module \core sync always update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] end - attribute \src "libresoc.v:44480.3-44508.6" - process $proc$libresoc.v:44480$2395 + attribute \src "libresoc.v:44260.3-44288.6" + process $proc$libresoc.v:44260$2395 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44481.5-44481.29" + attribute \src "libresoc.v:44261.5-44261.29" switch \initial - attribute \src "libresoc.v:44481.9-44481.17" + attribute \src "libresoc.v:44261.9-44261.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__data_len[3:0] $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76983,7 +76754,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__data_len[3:0] $3\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76999,24 +76770,24 @@ module \core sync always update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] end - attribute \src "libresoc.v:44509.3-44537.6" - process $proc$libresoc.v:44509$2396 + attribute \src "libresoc.v:44289.3-44317.6" + process $proc$libresoc.v:44289$2396 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44510.5-44510.29" + attribute \src "libresoc.v:44290.5-44290.29" switch \initial - attribute \src "libresoc.v:44510.9-44510.17" + attribute \src "libresoc.v:44290.9-44290.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__insn[31:0] $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77028,7 +76799,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__insn[31:0] $3\fus_oper_i_alu_div0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77044,24 +76815,24 @@ module \core sync always update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] end - attribute \src "libresoc.v:44538.3-44566.6" - process $proc$libresoc.v:44538$2397 + attribute \src "libresoc.v:44318.3-44346.6" + process $proc$libresoc.v:44318$2397 assign { } { } assign { } { } assign $0\fus_cu_issue_i$28[0:0]$2398 $1\fus_cu_issue_i$28[0:0]$2399 - attribute \src "libresoc.v:44539.5-44539.29" + attribute \src "libresoc.v:44319.5-44319.29" switch \initial - attribute \src "libresoc.v:44539.9-44539.17" + attribute \src "libresoc.v:44319.9-44319.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$28[0:0]$2399 $2\fus_cu_issue_i$28[0:0]$2400 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77073,7 +76844,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$28[0:0]$2400 $3\fus_cu_issue_i$28[0:0]$2401 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77089,24 +76860,24 @@ module \core sync always update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2398 end - attribute \src "libresoc.v:44567.3-44595.6" - process $proc$libresoc.v:44567$2402 + attribute \src "libresoc.v:44347.3-44375.6" + process $proc$libresoc.v:44347$2402 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$30[2:0]$2403 $1\fus_cu_rdmaskn_i$30[2:0]$2404 - attribute \src "libresoc.v:44568.5-44568.29" + attribute \src "libresoc.v:44348.5-44348.29" switch \initial - attribute \src "libresoc.v:44568.9-44568.17" + attribute \src "libresoc.v:44348.9-44348.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$30[2:0]$2404 $2\fus_cu_rdmaskn_i$30[2:0]$2405 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77118,7 +76889,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 $3\fus_cu_rdmaskn_i$30[2:0]$2406 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77134,24 +76905,24 @@ module \core sync always update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2403 end - attribute \src "libresoc.v:44596.3-44624.6" - process $proc$libresoc.v:44596$2407 + attribute \src "libresoc.v:44376.3-44404.6" + process $proc$libresoc.v:44376$2407 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44597.5-44597.29" + attribute \src "libresoc.v:44377.5-44377.29" switch \initial - attribute \src "libresoc.v:44597.9-44597.17" + attribute \src "libresoc.v:44377.9-44377.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__insn_type[6:0] $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77163,7 +76934,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__insn_type[6:0] $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77179,24 +76950,24 @@ module \core sync always update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] end - attribute \src "libresoc.v:44625.3-44653.6" - process $proc$libresoc.v:44625$2408 + attribute \src "libresoc.v:44405.3-44433.6" + process $proc$libresoc.v:44405$2408 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__fn_unit[13:0] $1\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44626.5-44626.29" + attribute \src "libresoc.v:44406.5-44406.29" switch \initial - attribute \src "libresoc.v:44626.9-44626.17" + attribute \src "libresoc.v:44406.9-44406.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__fn_unit[13:0] $2\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77208,7 +76979,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] $3\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77224,21 +76995,21 @@ module \core sync always update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[13:0] end - attribute \src "libresoc.v:44654.3-44683.6" - process $proc$libresoc.v:44654$2409 + attribute \src "libresoc.v:44434.3-44463.6" + process $proc$libresoc.v:44434$2409 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44655.5-44655.29" + attribute \src "libresoc.v:44435.5-44435.29" switch \initial - attribute \src "libresoc.v:44655.9-44655.17" + attribute \src "libresoc.v:44435.9-44435.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77246,7 +77017,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] $2\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77262,7 +77033,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77282,21 +77053,21 @@ module \core update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44684.3-44713.6" - process $proc$libresoc.v:44684$2410 + attribute \src "libresoc.v:44464.3-44493.6" + process $proc$libresoc.v:44464$2410 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44685.5-44685.29" + attribute \src "libresoc.v:44465.5-44465.29" switch \initial - attribute \src "libresoc.v:44685.9-44685.17" + attribute \src "libresoc.v:44465.9-44465.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77304,7 +77075,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] $2\fus_oper_i_alu_mul0__rc__ok[0:0] assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77320,7 +77091,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__ok[0:0] assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77340,21 +77111,21 @@ module \core update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] end - attribute \src "libresoc.v:44714.3-44743.6" - process $proc$libresoc.v:44714$2411 + attribute \src "libresoc.v:44494.3-44523.6" + process $proc$libresoc.v:44494$2411 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44715.5-44715.29" + attribute \src "libresoc.v:44495.5-44495.29" switch \initial - attribute \src "libresoc.v:44715.9-44715.17" + attribute \src "libresoc.v:44495.9-44495.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77362,7 +77133,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] $2\fus_oper_i_alu_mul0__oe__oe[0:0] assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77378,7 +77149,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77398,24 +77169,24 @@ module \core update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] end - attribute \src "libresoc.v:44744.3-44772.6" - process $proc$libresoc.v:44744$2412 + attribute \src "libresoc.v:44524.3-44552.6" + process $proc$libresoc.v:44524$2412 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44745.5-44745.29" + attribute \src "libresoc.v:44525.5-44525.29" switch \initial - attribute \src "libresoc.v:44745.9-44745.17" + attribute \src "libresoc.v:44525.9-44525.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77427,7 +77198,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77443,24 +77214,24 @@ module \core sync always update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] end - attribute \src "libresoc.v:44773.3-44801.6" - process $proc$libresoc.v:44773$2413 + attribute \src "libresoc.v:44553.3-44581.6" + process $proc$libresoc.v:44553$2413 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44774.5-44774.29" + attribute \src "libresoc.v:44554.5-44554.29" switch \initial - attribute \src "libresoc.v:44774.9-44774.17" + attribute \src "libresoc.v:44554.9-44554.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77472,7 +77243,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77488,24 +77259,24 @@ module \core sync always update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] end - attribute \src "libresoc.v:44802.3-44830.6" - process $proc$libresoc.v:44802$2414 + attribute \src "libresoc.v:44582.3-44610.6" + process $proc$libresoc.v:44582$2414 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44803.5-44803.29" + attribute \src "libresoc.v:44583.5-44583.29" switch \initial - attribute \src "libresoc.v:44803.9-44803.17" + attribute \src "libresoc.v:44583.9-44583.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__is_signed[0:0] $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77517,7 +77288,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__is_signed[0:0] $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77533,24 +77304,24 @@ module \core sync always update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] end - attribute \src "libresoc.v:44831.3-44859.6" - process $proc$libresoc.v:44831$2415 + attribute \src "libresoc.v:44611.3-44639.6" + process $proc$libresoc.v:44611$2415 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44832.5-44832.29" + attribute \src "libresoc.v:44612.5-44612.29" switch \initial - attribute \src "libresoc.v:44832.9-44832.17" + attribute \src "libresoc.v:44612.9-44612.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__insn[31:0] $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77562,7 +77333,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__insn[31:0] $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77578,24 +77349,24 @@ module \core sync always update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] end - attribute \src "libresoc.v:44860.3-44888.6" - process $proc$libresoc.v:44860$2416 + attribute \src "libresoc.v:44640.3-44668.6" + process $proc$libresoc.v:44640$2416 assign { } { } assign { } { } assign $0\fus_cu_issue_i$31[0:0]$2417 $1\fus_cu_issue_i$31[0:0]$2418 - attribute \src "libresoc.v:44861.5-44861.29" + attribute \src "libresoc.v:44641.5-44641.29" switch \initial - attribute \src "libresoc.v:44861.9-44861.17" + attribute \src "libresoc.v:44641.9-44641.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$31[0:0]$2418 $2\fus_cu_issue_i$31[0:0]$2419 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77607,7 +77378,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$31[0:0]$2419 $3\fus_cu_issue_i$31[0:0]$2420 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77623,24 +77394,24 @@ module \core sync always update \fus_cu_issue_i$31 $0\fus_cu_issue_i$31[0:0]$2417 end - attribute \src "libresoc.v:44889.3-44917.6" - process $proc$libresoc.v:44889$2421 + attribute \src "libresoc.v:44669.3-44697.6" + process $proc$libresoc.v:44669$2421 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$33[2:0]$2422 $1\fus_cu_rdmaskn_i$33[2:0]$2423 - attribute \src "libresoc.v:44890.5-44890.29" + attribute \src "libresoc.v:44670.5-44670.29" switch \initial - attribute \src "libresoc.v:44890.9-44890.17" + attribute \src "libresoc.v:44670.9-44670.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$33[2:0]$2423 $2\fus_cu_rdmaskn_i$33[2:0]$2424 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77652,7 +77423,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 $3\fus_cu_rdmaskn_i$33[2:0]$2425 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77668,24 +77439,24 @@ module \core sync always update \fus_cu_rdmaskn_i$33 $0\fus_cu_rdmaskn_i$33[2:0]$2422 end - attribute \src "libresoc.v:44918.3-44946.6" - process $proc$libresoc.v:44918$2426 + attribute \src "libresoc.v:44698.3-44726.6" + process $proc$libresoc.v:44698$2426 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44919.5-44919.29" + attribute \src "libresoc.v:44699.5-44699.29" switch \initial - attribute \src "libresoc.v:44919.9-44919.17" + attribute \src "libresoc.v:44699.9-44699.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77697,7 +77468,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77713,24 +77484,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] end - attribute \src "libresoc.v:44947.3-44975.6" - process $proc$libresoc.v:44947$2427 + attribute \src "libresoc.v:44727.3-44755.6" + process $proc$libresoc.v:44727$2427 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44948.5-44948.29" + attribute \src "libresoc.v:44728.5-44728.29" switch \initial - attribute \src "libresoc.v:44948.9-44948.17" + attribute \src "libresoc.v:44728.9-44728.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77742,7 +77513,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77758,21 +77529,21 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] end - attribute \src "libresoc.v:44976.3-45005.6" - process $proc$libresoc.v:44976$2428 + attribute \src "libresoc.v:44756.3-44785.6" + process $proc$libresoc.v:44756$2428 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44977.5-44977.29" + attribute \src "libresoc.v:44757.5-44757.29" switch \initial - attribute \src "libresoc.v:44977.9-44977.17" + attribute \src "libresoc.v:44757.9-44757.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77780,7 +77551,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77796,7 +77567,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77816,21 +77587,21 @@ module \core update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] end - attribute \src "libresoc.v:45006.3-45035.6" - process $proc$libresoc.v:45006$2429 + attribute \src "libresoc.v:44786.3-44815.6" + process $proc$libresoc.v:44786$2429 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:45007.5-45007.29" + attribute \src "libresoc.v:44787.5-44787.29" switch \initial - attribute \src "libresoc.v:45007.9-45007.17" + attribute \src "libresoc.v:44787.9-44787.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77838,7 +77609,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77854,7 +77625,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77874,21 +77645,21 @@ module \core update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] end - attribute \src "libresoc.v:45036.3-45065.6" - process $proc$libresoc.v:45036$2430 + attribute \src "libresoc.v:44816.3-44845.6" + process $proc$libresoc.v:44816$2430 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45037.5-45037.29" + attribute \src "libresoc.v:44817.5-44817.29" switch \initial - attribute \src "libresoc.v:45037.9-45037.17" + attribute \src "libresoc.v:44817.9-44817.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77896,7 +77667,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77912,7 +77683,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77932,24 +77703,24 @@ module \core update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] end - attribute \src "libresoc.v:45066.3-45094.6" - process $proc$libresoc.v:45066$2431 + attribute \src "libresoc.v:44846.3-44874.6" + process $proc$libresoc.v:44846$2431 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:45067.5-45067.29" + attribute \src "libresoc.v:44847.5-44847.29" switch \initial - attribute \src "libresoc.v:45067.9-45067.17" + attribute \src "libresoc.v:44847.9-44847.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77961,7 +77732,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77977,24 +77748,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] end - attribute \src "libresoc.v:45095.3-45123.6" - process $proc$libresoc.v:45095$2432 + attribute \src "libresoc.v:44875.3-44903.6" + process $proc$libresoc.v:44875$2432 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45096.5-45096.29" + attribute \src "libresoc.v:44876.5-44876.29" switch \initial - attribute \src "libresoc.v:45096.9-45096.17" + attribute \src "libresoc.v:44876.9-44876.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78006,7 +77777,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78022,24 +77793,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__invert_in $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] end - attribute \src "libresoc.v:45124.3-45152.6" - process $proc$libresoc.v:45124$2433 + attribute \src "libresoc.v:44904.3-44932.6" + process $proc$libresoc.v:44904$2433 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45125.5-45125.29" + attribute \src "libresoc.v:44905.5-44905.29" switch \initial - attribute \src "libresoc.v:45125.9-45125.17" + attribute \src "libresoc.v:44905.9-44905.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78051,7 +77822,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78067,24 +77838,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] end - attribute \src "libresoc.v:45153.3-45181.6" - process $proc$libresoc.v:45153$2434 + attribute \src "libresoc.v:44933.3-44961.6" + process $proc$libresoc.v:44933$2434 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45154.5-45154.29" + attribute \src "libresoc.v:44934.5-44934.29" switch \initial - attribute \src "libresoc.v:45154.9-45154.17" + attribute \src "libresoc.v:44934.9-44934.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78096,7 +77867,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78112,24 +77883,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] end - attribute \src "libresoc.v:45182.3-45210.6" - process $proc$libresoc.v:45182$2435 + attribute \src "libresoc.v:44962.3-44990.6" + process $proc$libresoc.v:44962$2435 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45183.5-45183.29" + attribute \src "libresoc.v:44963.5-44963.29" switch \initial - attribute \src "libresoc.v:45183.9-45183.17" + attribute \src "libresoc.v:44963.9-44963.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78141,7 +77912,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78157,24 +77928,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] end - attribute \src "libresoc.v:45211.3-45239.6" - process $proc$libresoc.v:45211$2436 + attribute \src "libresoc.v:44991.3-45019.6" + process $proc$libresoc.v:44991$2436 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:45212.5-45212.29" + attribute \src "libresoc.v:44992.5-44992.29" switch \initial - attribute \src "libresoc.v:45212.9-45212.17" + attribute \src "libresoc.v:44992.9-44992.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78186,7 +77957,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78202,24 +77973,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] end - attribute \src "libresoc.v:45240.3-45268.6" - process $proc$libresoc.v:45240$2437 + attribute \src "libresoc.v:45020.3-45048.6" + process $proc$libresoc.v:45020$2437 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45241.5-45241.29" + attribute \src "libresoc.v:45021.5-45021.29" switch \initial - attribute \src "libresoc.v:45241.9-45241.17" + attribute \src "libresoc.v:45021.9-45021.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78231,7 +78002,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78247,24 +78018,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] end - attribute \src "libresoc.v:45269.3-45297.6" - process $proc$libresoc.v:45269$2438 + attribute \src "libresoc.v:45049.3-45077.6" + process $proc$libresoc.v:45049$2438 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45270.5-45270.29" + attribute \src "libresoc.v:45050.5-45050.29" switch \initial - attribute \src "libresoc.v:45270.9-45270.17" + attribute \src "libresoc.v:45050.9-45050.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78276,7 +78047,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78292,24 +78063,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] end - attribute \src "libresoc.v:45298.3-45326.6" - process $proc$libresoc.v:45298$2439 + attribute \src "libresoc.v:45078.3-45106.6" + process $proc$libresoc.v:45078$2439 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:45299.5-45299.29" + attribute \src "libresoc.v:45079.5-45079.29" switch \initial - attribute \src "libresoc.v:45299.9-45299.17" + attribute \src "libresoc.v:45079.9-45079.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78321,7 +78092,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78337,24 +78108,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] end - attribute \src "libresoc.v:45327.3-45355.6" - process $proc$libresoc.v:45327$2440 + attribute \src "libresoc.v:45107.3-45135.6" + process $proc$libresoc.v:45107$2440 assign { } { } assign { } { } assign $0\fus_cu_issue_i$34[0:0]$2441 $1\fus_cu_issue_i$34[0:0]$2442 - attribute \src "libresoc.v:45328.5-45328.29" + attribute \src "libresoc.v:45108.5-45108.29" switch \initial - attribute \src "libresoc.v:45328.9-45328.17" + attribute \src "libresoc.v:45108.9-45108.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$34[0:0]$2442 $2\fus_cu_issue_i$34[0:0]$2443 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78366,7 +78137,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$34[0:0]$2443 $3\fus_cu_issue_i$34[0:0]$2444 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78382,24 +78153,24 @@ module \core sync always update \fus_cu_issue_i$34 $0\fus_cu_issue_i$34[0:0]$2441 end - attribute \src "libresoc.v:45356.3-45384.6" - process $proc$libresoc.v:45356$2445 + attribute \src "libresoc.v:45136.3-45164.6" + process $proc$libresoc.v:45136$2445 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$36[4:0]$2446 $1\fus_cu_rdmaskn_i$36[4:0]$2447 - attribute \src "libresoc.v:45357.5-45357.29" + attribute \src "libresoc.v:45137.5-45137.29" switch \initial - attribute \src "libresoc.v:45357.9-45357.17" + attribute \src "libresoc.v:45137.9-45137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$36[4:0]$2447 $2\fus_cu_rdmaskn_i$36[4:0]$2448 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78411,7 +78182,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 $3\fus_cu_rdmaskn_i$36[4:0]$2449 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78427,24 +78198,24 @@ module \core sync always update \fus_cu_rdmaskn_i$36 $0\fus_cu_rdmaskn_i$36[4:0]$2446 end - attribute \src "libresoc.v:45385.3-45413.6" - process $proc$libresoc.v:45385$2450 + attribute \src "libresoc.v:45165.3-45193.6" + process $proc$libresoc.v:45165$2450 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45386.5-45386.29" + attribute \src "libresoc.v:45166.5-45166.29" switch \initial - attribute \src "libresoc.v:45386.9-45386.17" + attribute \src "libresoc.v:45166.9-45166.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78456,7 +78227,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78472,24 +78243,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] end - attribute \src "libresoc.v:45414.3-45442.6" - process $proc$libresoc.v:45414$2451 + attribute \src "libresoc.v:45194.3-45222.6" + process $proc$libresoc.v:45194$2451 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45415.5-45415.29" + attribute \src "libresoc.v:45195.5-45195.29" switch \initial - attribute \src "libresoc.v:45415.9-45415.17" + attribute \src "libresoc.v:45195.9-45195.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78501,7 +78272,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78517,21 +78288,21 @@ module \core sync always update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] end - attribute \src "libresoc.v:45443.3-45472.6" - process $proc$libresoc.v:45443$2452 + attribute \src "libresoc.v:45223.3-45252.6" + process $proc$libresoc.v:45223$2452 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45444.5-45444.29" + attribute \src "libresoc.v:45224.5-45224.29" switch \initial - attribute \src "libresoc.v:45444.9-45444.17" + attribute \src "libresoc.v:45224.9-45224.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78539,7 +78310,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78555,7 +78326,7 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78575,24 +78346,24 @@ module \core update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] end - attribute \src "libresoc.v:45473.3-45501.6" - process $proc$libresoc.v:45473$2453 + attribute \src "libresoc.v:45253.3-45281.6" + process $proc$libresoc.v:45253$2453 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45474.5-45474.29" + attribute \src "libresoc.v:45254.5-45254.29" switch \initial - attribute \src "libresoc.v:45474.9-45474.17" + attribute \src "libresoc.v:45254.9-45254.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78604,7 +78375,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78620,21 +78391,21 @@ module \core sync always update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] end - attribute \src "libresoc.v:45502.3-45531.6" - process $proc$libresoc.v:45502$2454 + attribute \src "libresoc.v:45282.3-45311.6" + process $proc$libresoc.v:45282$2454 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45503.5-45503.29" + attribute \src "libresoc.v:45283.5-45283.29" switch \initial - attribute \src "libresoc.v:45503.9-45503.17" + attribute \src "libresoc.v:45283.9-45283.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78642,7 +78413,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78658,7 +78429,7 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78678,21 +78449,21 @@ module \core update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] end - attribute \src "libresoc.v:45532.3-45561.6" - process $proc$libresoc.v:45532$2455 + attribute \src "libresoc.v:45312.3-45341.6" + process $proc$libresoc.v:45312$2455 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45533.5-45533.29" + attribute \src "libresoc.v:45313.5-45313.29" switch \initial - attribute \src "libresoc.v:45533.9-45533.17" + attribute \src "libresoc.v:45313.9-45313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78700,7 +78471,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78716,7 +78487,7 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78736,24 +78507,24 @@ module \core update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] end - attribute \src "libresoc.v:45562.3-45590.6" - process $proc$libresoc.v:45562$2456 + attribute \src "libresoc.v:45342.3-45370.6" + process $proc$libresoc.v:45342$2456 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45563.5-45563.29" + attribute \src "libresoc.v:45343.5-45343.29" switch \initial - attribute \src "libresoc.v:45563.9-45563.17" + attribute \src "libresoc.v:45343.9-45343.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78765,7 +78536,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78781,24 +78552,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] end - attribute \src "libresoc.v:45591.3-45619.6" - process $proc$libresoc.v:45591$2457 + attribute \src "libresoc.v:45371.3-45399.6" + process $proc$libresoc.v:45371$2457 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45592.5-45592.29" + attribute \src "libresoc.v:45372.5-45372.29" switch \initial - attribute \src "libresoc.v:45592.9-45592.17" + attribute \src "libresoc.v:45372.9-45372.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78810,7 +78581,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78826,24 +78597,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] end - attribute \src "libresoc.v:45620.3-45648.6" - process $proc$libresoc.v:45620$2458 + attribute \src "libresoc.v:45400.3-45428.6" + process $proc$libresoc.v:45400$2458 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45621.5-45621.29" + attribute \src "libresoc.v:45401.5-45401.29" switch \initial - attribute \src "libresoc.v:45621.9-45621.17" + attribute \src "libresoc.v:45401.9-45401.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78855,7 +78626,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78871,24 +78642,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] end - attribute \src "libresoc.v:45649.3-45677.6" - process $proc$libresoc.v:45649$2459 + attribute \src "libresoc.v:45429.3-45457.6" + process $proc$libresoc.v:45429$2459 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45650.5-45650.29" + attribute \src "libresoc.v:45430.5-45430.29" switch \initial - attribute \src "libresoc.v:45650.9-45650.17" + attribute \src "libresoc.v:45430.9-45430.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78900,7 +78671,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78916,24 +78687,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] end - attribute \src "libresoc.v:45678.3-45706.6" - process $proc$libresoc.v:45678$2460 + attribute \src "libresoc.v:45458.3-45486.6" + process $proc$libresoc.v:45458$2460 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45679.5-45679.29" + attribute \src "libresoc.v:45459.5-45459.29" switch \initial - attribute \src "libresoc.v:45679.9-45679.17" + attribute \src "libresoc.v:45459.9-45459.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78945,7 +78716,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78961,24 +78732,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] end - attribute \src "libresoc.v:45707.3-45735.6" - process $proc$libresoc.v:45707$2461 + attribute \src "libresoc.v:45487.3-45515.6" + process $proc$libresoc.v:45487$2461 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45708.5-45708.29" + attribute \src "libresoc.v:45488.5-45488.29" switch \initial - attribute \src "libresoc.v:45708.9-45708.17" + attribute \src "libresoc.v:45488.9-45488.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78990,7 +78761,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -79006,24 +78777,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] end - attribute \src "libresoc.v:45736.3-45764.6" - process $proc$libresoc.v:45736$2462 + attribute \src "libresoc.v:45516.3-45544.6" + process $proc$libresoc.v:45516$2462 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45737.5-45737.29" + attribute \src "libresoc.v:45517.5-45517.29" switch \initial - attribute \src "libresoc.v:45737.9-45737.17" + attribute \src "libresoc.v:45517.9-45517.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__insn[31:0] $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -79035,7 +78806,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__insn[31:0] $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -79051,24 +78822,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] end - attribute \src "libresoc.v:45765.3-45793.6" - process $proc$libresoc.v:45765$2463 + attribute \src "libresoc.v:45545.3-45573.6" + process $proc$libresoc.v:45545$2463 assign { } { } assign { } { } assign $0\fus_cu_issue_i$37[0:0]$2464 $1\fus_cu_issue_i$37[0:0]$2465 - attribute \src "libresoc.v:45766.5-45766.29" + attribute \src "libresoc.v:45546.5-45546.29" switch \initial - attribute \src "libresoc.v:45766.9-45766.17" + attribute \src "libresoc.v:45546.9-45546.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$37[0:0]$2465 $2\fus_cu_issue_i$37[0:0]$2466 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -79080,7 +78851,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$37[0:0]$2466 $3\fus_cu_issue_i$37[0:0]$2467 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -79096,24 +78867,24 @@ module \core sync always update \fus_cu_issue_i$37 $0\fus_cu_issue_i$37[0:0]$2464 end - attribute \src "libresoc.v:45794.3-45822.6" - process $proc$libresoc.v:45794$2468 + attribute \src "libresoc.v:45574.3-45602.6" + process $proc$libresoc.v:45574$2468 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$39[2:0]$2469 $1\fus_cu_rdmaskn_i$39[2:0]$2470 - attribute \src "libresoc.v:45795.5-45795.29" + attribute \src "libresoc.v:45575.5-45575.29" switch \initial - attribute \src "libresoc.v:45795.9-45795.17" + attribute \src "libresoc.v:45575.9-45575.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$39[2:0]$2470 $2\fus_cu_rdmaskn_i$39[2:0]$2471 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -79125,7 +78896,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 $3\fus_cu_rdmaskn_i$39[2:0]$2472 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -79141,14 +78912,14 @@ module \core sync always update \fus_cu_rdmaskn_i$39 $0\fus_cu_rdmaskn_i$39[2:0]$2469 end - attribute \src "libresoc.v:45823.3-45831.6" - process $proc$libresoc.v:45823$2473 + attribute \src "libresoc.v:45603.3-45611.6" + process $proc$libresoc.v:45603$2473 assign { } { } assign { } { } - assign $0\dp_INT_ra_alu0_0$next[0:0]$2474 $1\dp_INT_ra_alu0_0$next[0:0]$2475 - attribute \src "libresoc.v:45824.5-45824.29" + assign $0\dp_INT_rabc_alu0_0$next[0:0]$2474 $1\dp_INT_rabc_alu0_0$next[0:0]$2475 + attribute \src "libresoc.v:45604.5-45604.29" switch \initial - attribute \src "libresoc.v:45824.9-45824.17" + attribute \src "libresoc.v:45604.9-45604.17" case 1'1 case end @@ -79157,44 +78928,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_alu0_0$next[0:0]$2475 1'0 + assign $1\dp_INT_rabc_alu0_0$next[0:0]$2475 1'0 case - assign $1\dp_INT_ra_alu0_0$next[0:0]$2475 \rp_INT_ra_alu0_0 + assign $1\dp_INT_rabc_alu0_0$next[0:0]$2475 \rp_INT_rabc_alu0_0 end sync always - update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2474 + update \dp_INT_rabc_alu0_0$next $0\dp_INT_rabc_alu0_0$next[0:0]$2474 end - attribute \src "libresoc.v:45832.3-45841.6" - process $proc$libresoc.v:45832$2476 + attribute \src "libresoc.v:45612.3-45621.6" + process $proc$libresoc.v:45612$2476 assign { } { } assign { } { } - assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] - attribute \src "libresoc.v:45833.5-45833.29" + assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] + attribute \src "libresoc.v:45613.5-45613.29" switch \initial - attribute \src "libresoc.v:45833.9-45833.17" + attribute \src "libresoc.v:45613.9-45613.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_ra_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i[63:0] \int_src1__data_o + assign $1\fus_src2_i[63:0] \int_src__data_o case - assign $1\fus_src1_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i $0\fus_src1_i[63:0] + update \fus_src2_i $0\fus_src2_i[63:0] end - attribute \src "libresoc.v:45842.3-45850.6" - process $proc$libresoc.v:45842$2477 + attribute \src "libresoc.v:45622.3-45630.6" + process $proc$libresoc.v:45622$2477 assign { } { } assign { } { } - assign $0\dp_INT_ra_cr0_1$next[0:0]$2478 $1\dp_INT_ra_cr0_1$next[0:0]$2479 - attribute \src "libresoc.v:45843.5-45843.29" + assign $0\dp_INT_rabc_cr0_1$next[0:0]$2478 $1\dp_INT_rabc_cr0_1$next[0:0]$2479 + attribute \src "libresoc.v:45623.5-45623.29" switch \initial - attribute \src "libresoc.v:45843.9-45843.17" + attribute \src "libresoc.v:45623.9-45623.17" case 1'1 case end @@ -79203,44 +78974,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_cr0_1$next[0:0]$2479 1'0 + assign $1\dp_INT_rabc_cr0_1$next[0:0]$2479 1'0 case - assign $1\dp_INT_ra_cr0_1$next[0:0]$2479 \rp_INT_ra_cr0_1 + assign $1\dp_INT_rabc_cr0_1$next[0:0]$2479 \rp_INT_rabc_cr0_1 end sync always - update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2478 + update \dp_INT_rabc_cr0_1$next $0\dp_INT_rabc_cr0_1$next[0:0]$2478 end - attribute \src "libresoc.v:45851.3-45860.6" - process $proc$libresoc.v:45851$2480 + attribute \src "libresoc.v:45631.3-45640.6" + process $proc$libresoc.v:45631$2480 assign { } { } assign { } { } - assign $0\fus_src1_i$42[63:0]$2481 $1\fus_src1_i$42[63:0]$2482 - attribute \src "libresoc.v:45852.5-45852.29" + assign $0\fus_src2_i$42[63:0]$2481 $1\fus_src2_i$42[63:0]$2482 + attribute \src "libresoc.v:45632.5-45632.29" switch \initial - attribute \src "libresoc.v:45852.9-45852.17" + attribute \src "libresoc.v:45632.9-45632.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_ra_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_cr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$42[63:0]$2482 \int_src1__data_o + assign $1\fus_src2_i$42[63:0]$2482 \int_src__data_o case - assign $1\fus_src1_i$42[63:0]$2482 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$42[63:0]$2482 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$42 $0\fus_src1_i$42[63:0]$2481 + update \fus_src2_i$42 $0\fus_src2_i$42[63:0]$2481 end - attribute \src "libresoc.v:45861.3-45869.6" - process $proc$libresoc.v:45861$2483 + attribute \src "libresoc.v:45641.3-45649.6" + process $proc$libresoc.v:45641$2483 assign { } { } assign { } { } - assign $0\dp_INT_ra_trap0_2$next[0:0]$2484 $1\dp_INT_ra_trap0_2$next[0:0]$2485 - attribute \src "libresoc.v:45862.5-45862.29" + assign $0\dp_INT_rabc_trap0_2$next[0:0]$2484 $1\dp_INT_rabc_trap0_2$next[0:0]$2485 + attribute \src "libresoc.v:45642.5-45642.29" switch \initial - attribute \src "libresoc.v:45862.9-45862.17" + attribute \src "libresoc.v:45642.9-45642.17" case 1'1 case end @@ -79249,44 +79020,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_trap0_2$next[0:0]$2485 1'0 + assign $1\dp_INT_rabc_trap0_2$next[0:0]$2485 1'0 case - assign $1\dp_INT_ra_trap0_2$next[0:0]$2485 \rp_INT_ra_trap0_2 + assign $1\dp_INT_rabc_trap0_2$next[0:0]$2485 \rp_INT_rabc_trap0_2 end sync always - update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2484 + update \dp_INT_rabc_trap0_2$next $0\dp_INT_rabc_trap0_2$next[0:0]$2484 end - attribute \src "libresoc.v:45870.3-45879.6" - process $proc$libresoc.v:45870$2486 + attribute \src "libresoc.v:45650.3-45659.6" + process $proc$libresoc.v:45650$2486 assign { } { } assign { } { } - assign $0\fus_src1_i$45[63:0]$2487 $1\fus_src1_i$45[63:0]$2488 - attribute \src "libresoc.v:45871.5-45871.29" + assign $0\fus_src2_i$45[63:0]$2487 $1\fus_src2_i$45[63:0]$2488 + attribute \src "libresoc.v:45651.5-45651.29" switch \initial - attribute \src "libresoc.v:45871.9-45871.17" + attribute \src "libresoc.v:45651.9-45651.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_ra_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_trap0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$45[63:0]$2488 \int_src1__data_o + assign $1\fus_src2_i$45[63:0]$2488 \int_src__data_o case - assign $1\fus_src1_i$45[63:0]$2488 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$45[63:0]$2488 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$45 $0\fus_src1_i$45[63:0]$2487 + update \fus_src2_i$45 $0\fus_src2_i$45[63:0]$2487 end - attribute \src "libresoc.v:45880.3-45888.6" - process $proc$libresoc.v:45880$2489 + attribute \src "libresoc.v:45660.3-45668.6" + process $proc$libresoc.v:45660$2489 assign { } { } assign { } { } - assign $0\dp_INT_ra_logical0_3$next[0:0]$2490 $1\dp_INT_ra_logical0_3$next[0:0]$2491 - attribute \src "libresoc.v:45881.5-45881.29" + assign $0\dp_INT_rabc_logical0_3$next[0:0]$2490 $1\dp_INT_rabc_logical0_3$next[0:0]$2491 + attribute \src "libresoc.v:45661.5-45661.29" switch \initial - attribute \src "libresoc.v:45881.9-45881.17" + attribute \src "libresoc.v:45661.9-45661.17" case 1'1 case end @@ -79295,44 +79066,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_logical0_3$next[0:0]$2491 1'0 + assign $1\dp_INT_rabc_logical0_3$next[0:0]$2491 1'0 case - assign $1\dp_INT_ra_logical0_3$next[0:0]$2491 \rp_INT_ra_logical0_3 + assign $1\dp_INT_rabc_logical0_3$next[0:0]$2491 \rp_INT_rabc_logical0_3 end sync always - update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2490 + update \dp_INT_rabc_logical0_3$next $0\dp_INT_rabc_logical0_3$next[0:0]$2490 end - attribute \src "libresoc.v:45889.3-45898.6" - process $proc$libresoc.v:45889$2492 + attribute \src "libresoc.v:45669.3-45678.6" + process $proc$libresoc.v:45669$2492 assign { } { } assign { } { } - assign $0\fus_src1_i$48[63:0]$2493 $1\fus_src1_i$48[63:0]$2494 - attribute \src "libresoc.v:45890.5-45890.29" + assign $0\fus_src2_i$48[63:0]$2493 $1\fus_src2_i$48[63:0]$2494 + attribute \src "libresoc.v:45670.5-45670.29" switch \initial - attribute \src "libresoc.v:45890.9-45890.17" + attribute \src "libresoc.v:45670.9-45670.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_ra_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_logical0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$48[63:0]$2494 \int_src1__data_o + assign $1\fus_src2_i$48[63:0]$2494 \int_src__data_o case - assign $1\fus_src1_i$48[63:0]$2494 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$48[63:0]$2494 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$48 $0\fus_src1_i$48[63:0]$2493 + update \fus_src2_i$48 $0\fus_src2_i$48[63:0]$2493 end - attribute \src "libresoc.v:45899.3-45907.6" - process $proc$libresoc.v:45899$2495 + attribute \src "libresoc.v:45679.3-45687.6" + process $proc$libresoc.v:45679$2495 assign { } { } assign { } { } - assign $0\dp_INT_ra_spr0_4$next[0:0]$2496 $1\dp_INT_ra_spr0_4$next[0:0]$2497 - attribute \src "libresoc.v:45900.5-45900.29" + assign $0\dp_INT_rabc_div0_4$next[0:0]$2496 $1\dp_INT_rabc_div0_4$next[0:0]$2497 + attribute \src "libresoc.v:45680.5-45680.29" switch \initial - attribute \src "libresoc.v:45900.9-45900.17" + attribute \src "libresoc.v:45680.9-45680.17" case 1'1 case end @@ -79341,44 +79112,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_spr0_4$next[0:0]$2497 1'0 + assign $1\dp_INT_rabc_div0_4$next[0:0]$2497 1'0 case - assign $1\dp_INT_ra_spr0_4$next[0:0]$2497 \rp_INT_ra_spr0_4 + assign $1\dp_INT_rabc_div0_4$next[0:0]$2497 \rp_INT_rabc_div0_4 end sync always - update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2496 + update \dp_INT_rabc_div0_4$next $0\dp_INT_rabc_div0_4$next[0:0]$2496 end - attribute \src "libresoc.v:45908.3-45917.6" - process $proc$libresoc.v:45908$2498 + attribute \src "libresoc.v:45688.3-45697.6" + process $proc$libresoc.v:45688$2498 assign { } { } assign { } { } - assign $0\fus_src1_i$51[63:0]$2499 $1\fus_src1_i$51[63:0]$2500 - attribute \src "libresoc.v:45909.5-45909.29" + assign $0\fus_src2_i$51[63:0]$2499 $1\fus_src2_i$51[63:0]$2500 + attribute \src "libresoc.v:45689.5-45689.29" switch \initial - attribute \src "libresoc.v:45909.9-45909.17" + attribute \src "libresoc.v:45689.9-45689.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_ra_spr0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_div0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$51[63:0]$2500 \int_src1__data_o + assign $1\fus_src2_i$51[63:0]$2500 \int_src__data_o case - assign $1\fus_src1_i$51[63:0]$2500 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$51[63:0]$2500 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$51 $0\fus_src1_i$51[63:0]$2499 + update \fus_src2_i$51 $0\fus_src2_i$51[63:0]$2499 end - attribute \src "libresoc.v:45918.3-45926.6" - process $proc$libresoc.v:45918$2501 + attribute \src "libresoc.v:45698.3-45706.6" + process $proc$libresoc.v:45698$2501 assign { } { } assign { } { } - assign $0\dp_INT_ra_div0_5$next[0:0]$2502 $1\dp_INT_ra_div0_5$next[0:0]$2503 - attribute \src "libresoc.v:45919.5-45919.29" + assign $0\dp_INT_rabc_mul0_5$next[0:0]$2502 $1\dp_INT_rabc_mul0_5$next[0:0]$2503 + attribute \src "libresoc.v:45699.5-45699.29" switch \initial - attribute \src "libresoc.v:45919.9-45919.17" + attribute \src "libresoc.v:45699.9-45699.17" case 1'1 case end @@ -79387,44 +79158,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_div0_5$next[0:0]$2503 1'0 + assign $1\dp_INT_rabc_mul0_5$next[0:0]$2503 1'0 case - assign $1\dp_INT_ra_div0_5$next[0:0]$2503 \rp_INT_ra_div0_5 + assign $1\dp_INT_rabc_mul0_5$next[0:0]$2503 \rp_INT_rabc_mul0_5 end sync always - update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2502 + update \dp_INT_rabc_mul0_5$next $0\dp_INT_rabc_mul0_5$next[0:0]$2502 end - attribute \src "libresoc.v:45927.3-45936.6" - process $proc$libresoc.v:45927$2504 + attribute \src "libresoc.v:45707.3-45716.6" + process $proc$libresoc.v:45707$2504 assign { } { } assign { } { } - assign $0\fus_src1_i$54[63:0]$2505 $1\fus_src1_i$54[63:0]$2506 - attribute \src "libresoc.v:45928.5-45928.29" + assign $0\fus_src2_i$54[63:0]$2505 $1\fus_src2_i$54[63:0]$2506 + attribute \src "libresoc.v:45708.5-45708.29" switch \initial - attribute \src "libresoc.v:45928.9-45928.17" + attribute \src "libresoc.v:45708.9-45708.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_ra_div0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_mul0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$54[63:0]$2506 \int_src1__data_o + assign $1\fus_src2_i$54[63:0]$2506 \int_src__data_o case - assign $1\fus_src1_i$54[63:0]$2506 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$54[63:0]$2506 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$54 $0\fus_src1_i$54[63:0]$2505 + update \fus_src2_i$54 $0\fus_src2_i$54[63:0]$2505 end - attribute \src "libresoc.v:45937.3-45945.6" - process $proc$libresoc.v:45937$2507 + attribute \src "libresoc.v:45717.3-45725.6" + process $proc$libresoc.v:45717$2507 assign { } { } assign { } { } - assign $0\dp_INT_ra_mul0_6$next[0:0]$2508 $1\dp_INT_ra_mul0_6$next[0:0]$2509 - attribute \src "libresoc.v:45938.5-45938.29" + assign $0\dp_INT_rabc_shiftrot0_6$next[0:0]$2508 $1\dp_INT_rabc_shiftrot0_6$next[0:0]$2509 + attribute \src "libresoc.v:45718.5-45718.29" switch \initial - attribute \src "libresoc.v:45938.9-45938.17" + attribute \src "libresoc.v:45718.9-45718.17" case 1'1 case end @@ -79433,44 +79204,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_mul0_6$next[0:0]$2509 1'0 + assign $1\dp_INT_rabc_shiftrot0_6$next[0:0]$2509 1'0 case - assign $1\dp_INT_ra_mul0_6$next[0:0]$2509 \rp_INT_ra_mul0_6 + assign $1\dp_INT_rabc_shiftrot0_6$next[0:0]$2509 \rp_INT_rabc_shiftrot0_6 end sync always - update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2508 + update \dp_INT_rabc_shiftrot0_6$next $0\dp_INT_rabc_shiftrot0_6$next[0:0]$2508 end - attribute \src "libresoc.v:45946.3-45955.6" - process $proc$libresoc.v:45946$2510 + attribute \src "libresoc.v:45726.3-45735.6" + process $proc$libresoc.v:45726$2510 assign { } { } assign { } { } - assign $0\fus_src1_i$57[63:0]$2511 $1\fus_src1_i$57[63:0]$2512 - attribute \src "libresoc.v:45947.5-45947.29" + assign $0\fus_src2_i$57[63:0]$2511 $1\fus_src2_i$57[63:0]$2512 + attribute \src "libresoc.v:45727.5-45727.29" switch \initial - attribute \src "libresoc.v:45947.9-45947.17" + attribute \src "libresoc.v:45727.9-45727.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_ra_mul0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_shiftrot0_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$57[63:0]$2512 \int_src1__data_o + assign $1\fus_src2_i$57[63:0]$2512 \int_src__data_o case - assign $1\fus_src1_i$57[63:0]$2512 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$57[63:0]$2512 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$57 $0\fus_src1_i$57[63:0]$2511 + update \fus_src2_i$57 $0\fus_src2_i$57[63:0]$2511 end - attribute \src "libresoc.v:45956.3-45964.6" - process $proc$libresoc.v:45956$2513 + attribute \src "libresoc.v:45736.3-45744.6" + process $proc$libresoc.v:45736$2513 assign { } { } assign { } { } - assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 - attribute \src "libresoc.v:45957.5-45957.29" + assign $0\dp_INT_rabc_ldst0_7$next[0:0]$2514 $1\dp_INT_rabc_ldst0_7$next[0:0]$2515 + attribute \src "libresoc.v:45737.5-45737.29" switch \initial - attribute \src "libresoc.v:45957.9-45957.17" + attribute \src "libresoc.v:45737.9-45737.17" case 1'1 case end @@ -79479,44 +79250,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 1'0 + assign $1\dp_INT_rabc_ldst0_7$next[0:0]$2515 1'0 case - assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 \rp_INT_ra_shiftrot0_7 + assign $1\dp_INT_rabc_ldst0_7$next[0:0]$2515 \rp_INT_rabc_ldst0_7 end sync always - update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 + update \dp_INT_rabc_ldst0_7$next $0\dp_INT_rabc_ldst0_7$next[0:0]$2514 end - attribute \src "libresoc.v:45965.3-45974.6" - process $proc$libresoc.v:45965$2516 + attribute \src "libresoc.v:45745.3-45754.6" + process $proc$libresoc.v:45745$2516 assign { } { } assign { } { } - assign $0\fus_src1_i$60[63:0]$2517 $1\fus_src1_i$60[63:0]$2518 - attribute \src "libresoc.v:45966.5-45966.29" + assign $0\fus_src2_i$60[63:0]$2517 $1\fus_src2_i$60[63:0]$2518 + attribute \src "libresoc.v:45746.5-45746.29" switch \initial - attribute \src "libresoc.v:45966.9-45966.17" + attribute \src "libresoc.v:45746.9-45746.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_ra_shiftrot0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_ldst0_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$60[63:0]$2518 \int_src1__data_o + assign $1\fus_src2_i$60[63:0]$2518 \int_src__data_o case - assign $1\fus_src1_i$60[63:0]$2518 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$60[63:0]$2518 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$60 $0\fus_src1_i$60[63:0]$2517 + update \fus_src2_i$60 $0\fus_src2_i$60[63:0]$2517 end - attribute \src "libresoc.v:45975.3-45983.6" - process $proc$libresoc.v:45975$2519 + attribute \src "libresoc.v:45755.3-45763.6" + process $proc$libresoc.v:45755$2519 assign { } { } assign { } { } - assign $0\dp_INT_ra_ldst0_8$next[0:0]$2520 $1\dp_INT_ra_ldst0_8$next[0:0]$2521 - attribute \src "libresoc.v:45976.5-45976.29" + assign $0\dp_INT_rabc_shiftrot0_8$next[0:0]$2520 $1\dp_INT_rabc_shiftrot0_8$next[0:0]$2521 + attribute \src "libresoc.v:45756.5-45756.29" switch \initial - attribute \src "libresoc.v:45976.9-45976.17" + attribute \src "libresoc.v:45756.9-45756.17" case 1'1 case end @@ -79525,44 +79296,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_ldst0_8$next[0:0]$2521 1'0 + assign $1\dp_INT_rabc_shiftrot0_8$next[0:0]$2521 1'0 case - assign $1\dp_INT_ra_ldst0_8$next[0:0]$2521 \rp_INT_ra_ldst0_8 + assign $1\dp_INT_rabc_shiftrot0_8$next[0:0]$2521 \rp_INT_rabc_shiftrot0_8 end sync always - update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2520 + update \dp_INT_rabc_shiftrot0_8$next $0\dp_INT_rabc_shiftrot0_8$next[0:0]$2520 end - attribute \src "libresoc.v:45984.3-45993.6" - process $proc$libresoc.v:45984$2522 + attribute \src "libresoc.v:45764.3-45773.6" + process $proc$libresoc.v:45764$2522 assign { } { } assign { } { } - assign $0\fus_src1_i$63[63:0]$2523 $1\fus_src1_i$63[63:0]$2524 - attribute \src "libresoc.v:45985.5-45985.29" + assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] + attribute \src "libresoc.v:45765.5-45765.29" switch \initial - attribute \src "libresoc.v:45985.9-45985.17" + attribute \src "libresoc.v:45765.9-45765.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_ra_ldst0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_shiftrot0_8 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$63[63:0]$2524 \int_src1__data_o + assign $1\fus_src3_i[63:0] \int_src__data_o case - assign $1\fus_src1_i$63[63:0]$2524 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src3_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$63 $0\fus_src1_i$63[63:0]$2523 + update \fus_src3_i $0\fus_src3_i[63:0] end - attribute \src "libresoc.v:45994.3-46002.6" - process $proc$libresoc.v:45994$2525 + attribute \src "libresoc.v:45774.3-45782.6" + process $proc$libresoc.v:45774$2523 assign { } { } assign { } { } - assign $0\dp_INT_rb_alu0_0$next[0:0]$2526 $1\dp_INT_rb_alu0_0$next[0:0]$2527 - attribute \src "libresoc.v:45995.5-45995.29" + assign $0\dp_INT_rabc_ldst0_9$next[0:0]$2524 $1\dp_INT_rabc_ldst0_9$next[0:0]$2525 + attribute \src "libresoc.v:45775.5-45775.29" switch \initial - attribute \src "libresoc.v:45995.9-45995.17" + attribute \src "libresoc.v:45775.9-45775.17" case 1'1 case end @@ -79571,44 +79342,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_alu0_0$next[0:0]$2527 1'0 + assign $1\dp_INT_rabc_ldst0_9$next[0:0]$2525 1'0 case - assign $1\dp_INT_rb_alu0_0$next[0:0]$2527 \rp_INT_rb_alu0_0 + assign $1\dp_INT_rabc_ldst0_9$next[0:0]$2525 \rp_INT_rabc_ldst0_9 end sync always - update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2526 + update \dp_INT_rabc_ldst0_9$next $0\dp_INT_rabc_ldst0_9$next[0:0]$2524 end - attribute \src "libresoc.v:46003.3-46012.6" - process $proc$libresoc.v:46003$2528 + attribute \src "libresoc.v:45783.3-45792.6" + process $proc$libresoc.v:45783$2526 assign { } { } assign { } { } - assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] - attribute \src "libresoc.v:46004.5-46004.29" + assign $0\fus_src3_i$61[63:0]$2527 $1\fus_src3_i$61[63:0]$2528 + attribute \src "libresoc.v:45784.5-45784.29" switch \initial - attribute \src "libresoc.v:46004.9-46004.17" + attribute \src "libresoc.v:45784.9-45784.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_rb_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_ldst0_9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i[63:0] \int_src2__data_o + assign $1\fus_src3_i$61[63:0]$2528 \int_src__data_o case - assign $1\fus_src2_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src3_i$61[63:0]$2528 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i $0\fus_src2_i[63:0] + update \fus_src3_i$61 $0\fus_src3_i$61[63:0]$2527 end - attribute \src "libresoc.v:46013.3-46021.6" - process $proc$libresoc.v:46013$2529 + attribute \src "libresoc.v:45793.3-45801.6" + process $proc$libresoc.v:45793$2529 assign { } { } assign { } { } - assign $0\dp_INT_rb_cr0_1$next[0:0]$2530 $1\dp_INT_rb_cr0_1$next[0:0]$2531 - attribute \src "libresoc.v:46014.5-46014.29" + assign $0\dp_INT_rabc_alu0_10$next[0:0]$2530 $1\dp_INT_rabc_alu0_10$next[0:0]$2531 + attribute \src "libresoc.v:45794.5-45794.29" switch \initial - attribute \src "libresoc.v:46014.9-46014.17" + attribute \src "libresoc.v:45794.9-45794.17" case 1'1 case end @@ -79617,44 +79388,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_cr0_1$next[0:0]$2531 1'0 + assign $1\dp_INT_rabc_alu0_10$next[0:0]$2531 1'0 case - assign $1\dp_INT_rb_cr0_1$next[0:0]$2531 \rp_INT_rb_cr0_1 + assign $1\dp_INT_rabc_alu0_10$next[0:0]$2531 \rp_INT_rabc_alu0_10 end sync always - update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2530 + update \dp_INT_rabc_alu0_10$next $0\dp_INT_rabc_alu0_10$next[0:0]$2530 end - attribute \src "libresoc.v:46022.3-46031.6" - process $proc$libresoc.v:46022$2532 + attribute \src "libresoc.v:45802.3-45811.6" + process $proc$libresoc.v:45802$2532 assign { } { } assign { } { } - assign $0\fus_src2_i$64[63:0]$2533 $1\fus_src2_i$64[63:0]$2534 - attribute \src "libresoc.v:46023.5-46023.29" + assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] + attribute \src "libresoc.v:45803.5-45803.29" switch \initial - attribute \src "libresoc.v:46023.9-46023.17" + attribute \src "libresoc.v:45803.9-45803.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_rb_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_alu0_10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$64[63:0]$2534 \int_src2__data_o + assign $1\fus_src1_i[63:0] \int_src__data_o case - assign $1\fus_src2_i$64[63:0]$2534 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$64 $0\fus_src2_i$64[63:0]$2533 + update \fus_src1_i $0\fus_src1_i[63:0] end - attribute \src "libresoc.v:46032.3-46040.6" - process $proc$libresoc.v:46032$2535 + attribute \src "libresoc.v:45812.3-45820.6" + process $proc$libresoc.v:45812$2533 assign { } { } assign { } { } - assign $0\dp_INT_rb_trap0_2$next[0:0]$2536 $1\dp_INT_rb_trap0_2$next[0:0]$2537 - attribute \src "libresoc.v:46033.5-46033.29" + assign $0\dp_INT_rabc_cr0_11$next[0:0]$2534 $1\dp_INT_rabc_cr0_11$next[0:0]$2535 + attribute \src "libresoc.v:45813.5-45813.29" switch \initial - attribute \src "libresoc.v:46033.9-46033.17" + attribute \src "libresoc.v:45813.9-45813.17" case 1'1 case end @@ -79663,44 +79434,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_trap0_2$next[0:0]$2537 1'0 + assign $1\dp_INT_rabc_cr0_11$next[0:0]$2535 1'0 case - assign $1\dp_INT_rb_trap0_2$next[0:0]$2537 \rp_INT_rb_trap0_2 + assign $1\dp_INT_rabc_cr0_11$next[0:0]$2535 \rp_INT_rabc_cr0_11 end sync always - update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2536 + update \dp_INT_rabc_cr0_11$next $0\dp_INT_rabc_cr0_11$next[0:0]$2534 end - attribute \src "libresoc.v:46041.3-46050.6" - process $proc$libresoc.v:46041$2538 + attribute \src "libresoc.v:45821.3-45830.6" + process $proc$libresoc.v:45821$2536 assign { } { } assign { } { } - assign $0\fus_src2_i$65[63:0]$2539 $1\fus_src2_i$65[63:0]$2540 - attribute \src "libresoc.v:46042.5-46042.29" + assign $0\fus_src1_i$62[63:0]$2537 $1\fus_src1_i$62[63:0]$2538 + attribute \src "libresoc.v:45822.5-45822.29" switch \initial - attribute \src "libresoc.v:46042.9-46042.17" + attribute \src "libresoc.v:45822.9-45822.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_rb_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_cr0_11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$65[63:0]$2540 \int_src2__data_o + assign $1\fus_src1_i$62[63:0]$2538 \int_src__data_o case - assign $1\fus_src2_i$65[63:0]$2540 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$62[63:0]$2538 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$65 $0\fus_src2_i$65[63:0]$2539 + update \fus_src1_i$62 $0\fus_src1_i$62[63:0]$2537 end - attribute \src "libresoc.v:46051.3-46059.6" - process $proc$libresoc.v:46051$2541 + attribute \src "libresoc.v:45831.3-45839.6" + process $proc$libresoc.v:45831$2539 assign { } { } assign { } { } - assign $0\dp_INT_rb_logical0_3$next[0:0]$2542 $1\dp_INT_rb_logical0_3$next[0:0]$2543 - attribute \src "libresoc.v:46052.5-46052.29" + assign $0\dp_INT_rabc_trap0_12$next[0:0]$2540 $1\dp_INT_rabc_trap0_12$next[0:0]$2541 + attribute \src "libresoc.v:45832.5-45832.29" switch \initial - attribute \src "libresoc.v:46052.9-46052.17" + attribute \src "libresoc.v:45832.9-45832.17" case 1'1 case end @@ -79709,44 +79480,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_logical0_3$next[0:0]$2543 1'0 + assign $1\dp_INT_rabc_trap0_12$next[0:0]$2541 1'0 case - assign $1\dp_INT_rb_logical0_3$next[0:0]$2543 \rp_INT_rb_logical0_3 + assign $1\dp_INT_rabc_trap0_12$next[0:0]$2541 \rp_INT_rabc_trap0_12 end sync always - update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2542 + update \dp_INT_rabc_trap0_12$next $0\dp_INT_rabc_trap0_12$next[0:0]$2540 end - attribute \src "libresoc.v:46060.3-46069.6" - process $proc$libresoc.v:46060$2544 + attribute \src "libresoc.v:45840.3-45849.6" + process $proc$libresoc.v:45840$2542 assign { } { } assign { } { } - assign $0\fus_src2_i$66[63:0]$2545 $1\fus_src2_i$66[63:0]$2546 - attribute \src "libresoc.v:46061.5-46061.29" + assign $0\fus_src1_i$63[63:0]$2543 $1\fus_src1_i$63[63:0]$2544 + attribute \src "libresoc.v:45841.5-45841.29" switch \initial - attribute \src "libresoc.v:46061.9-46061.17" + attribute \src "libresoc.v:45841.9-45841.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_rb_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_trap0_12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$66[63:0]$2546 \int_src2__data_o + assign $1\fus_src1_i$63[63:0]$2544 \int_src__data_o case - assign $1\fus_src2_i$66[63:0]$2546 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$63[63:0]$2544 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$66 $0\fus_src2_i$66[63:0]$2545 + update \fus_src1_i$63 $0\fus_src1_i$63[63:0]$2543 end - attribute \src "libresoc.v:46070.3-46078.6" - process $proc$libresoc.v:46070$2547 + attribute \src "libresoc.v:45850.3-45858.6" + process $proc$libresoc.v:45850$2545 assign { } { } assign { } { } - assign $0\dp_INT_rb_div0_4$next[0:0]$2548 $1\dp_INT_rb_div0_4$next[0:0]$2549 - attribute \src "libresoc.v:46071.5-46071.29" + assign $0\dp_INT_rabc_logical0_13$next[0:0]$2546 $1\dp_INT_rabc_logical0_13$next[0:0]$2547 + attribute \src "libresoc.v:45851.5-45851.29" switch \initial - attribute \src "libresoc.v:46071.9-46071.17" + attribute \src "libresoc.v:45851.9-45851.17" case 1'1 case end @@ -79755,44 +79526,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_div0_4$next[0:0]$2549 1'0 + assign $1\dp_INT_rabc_logical0_13$next[0:0]$2547 1'0 case - assign $1\dp_INT_rb_div0_4$next[0:0]$2549 \rp_INT_rb_div0_4 + assign $1\dp_INT_rabc_logical0_13$next[0:0]$2547 \rp_INT_rabc_logical0_13 end sync always - update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2548 + update \dp_INT_rabc_logical0_13$next $0\dp_INT_rabc_logical0_13$next[0:0]$2546 end - attribute \src "libresoc.v:46079.3-46088.6" - process $proc$libresoc.v:46079$2550 + attribute \src "libresoc.v:45859.3-45868.6" + process $proc$libresoc.v:45859$2548 assign { } { } assign { } { } - assign $0\fus_src2_i$67[63:0]$2551 $1\fus_src2_i$67[63:0]$2552 - attribute \src "libresoc.v:46080.5-46080.29" + assign $0\fus_src1_i$64[63:0]$2549 $1\fus_src1_i$64[63:0]$2550 + attribute \src "libresoc.v:45860.5-45860.29" switch \initial - attribute \src "libresoc.v:46080.9-46080.17" + attribute \src "libresoc.v:45860.9-45860.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_rb_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_logical0_13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$67[63:0]$2552 \int_src2__data_o + assign $1\fus_src1_i$64[63:0]$2550 \int_src__data_o case - assign $1\fus_src2_i$67[63:0]$2552 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$64[63:0]$2550 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$67 $0\fus_src2_i$67[63:0]$2551 + update \fus_src1_i$64 $0\fus_src1_i$64[63:0]$2549 end - attribute \src "libresoc.v:46089.3-46097.6" - process $proc$libresoc.v:46089$2553 + attribute \src "libresoc.v:45869.3-45877.6" + process $proc$libresoc.v:45869$2551 assign { } { } assign { } { } - assign $0\dp_INT_rb_mul0_5$next[0:0]$2554 $1\dp_INT_rb_mul0_5$next[0:0]$2555 - attribute \src "libresoc.v:46090.5-46090.29" + assign $0\dp_INT_rabc_spr0_14$next[0:0]$2552 $1\dp_INT_rabc_spr0_14$next[0:0]$2553 + attribute \src "libresoc.v:45870.5-45870.29" switch \initial - attribute \src "libresoc.v:46090.9-46090.17" + attribute \src "libresoc.v:45870.9-45870.17" case 1'1 case end @@ -79801,44 +79572,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_mul0_5$next[0:0]$2555 1'0 + assign $1\dp_INT_rabc_spr0_14$next[0:0]$2553 1'0 case - assign $1\dp_INT_rb_mul0_5$next[0:0]$2555 \rp_INT_rb_mul0_5 + assign $1\dp_INT_rabc_spr0_14$next[0:0]$2553 \rp_INT_rabc_spr0_14 end sync always - update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2554 + update \dp_INT_rabc_spr0_14$next $0\dp_INT_rabc_spr0_14$next[0:0]$2552 end - attribute \src "libresoc.v:46098.3-46107.6" - process $proc$libresoc.v:46098$2556 + attribute \src "libresoc.v:45878.3-45887.6" + process $proc$libresoc.v:45878$2554 assign { } { } assign { } { } - assign $0\fus_src2_i$68[63:0]$2557 $1\fus_src2_i$68[63:0]$2558 - attribute \src "libresoc.v:46099.5-46099.29" + assign $0\fus_src1_i$67[63:0]$2555 $1\fus_src1_i$67[63:0]$2556 + attribute \src "libresoc.v:45879.5-45879.29" switch \initial - attribute \src "libresoc.v:46099.9-46099.17" + attribute \src "libresoc.v:45879.9-45879.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_rb_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_spr0_14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$68[63:0]$2558 \int_src2__data_o + assign $1\fus_src1_i$67[63:0]$2556 \int_src__data_o case - assign $1\fus_src2_i$68[63:0]$2558 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$67[63:0]$2556 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$68 $0\fus_src2_i$68[63:0]$2557 + update \fus_src1_i$67 $0\fus_src1_i$67[63:0]$2555 end - attribute \src "libresoc.v:46108.3-46116.6" - process $proc$libresoc.v:46108$2559 + attribute \src "libresoc.v:45888.3-45896.6" + process $proc$libresoc.v:45888$2557 assign { } { } assign { } { } - assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 - attribute \src "libresoc.v:46109.5-46109.29" + assign $0\dp_INT_rabc_div0_15$next[0:0]$2558 $1\dp_INT_rabc_div0_15$next[0:0]$2559 + attribute \src "libresoc.v:45889.5-45889.29" switch \initial - attribute \src "libresoc.v:46109.9-46109.17" + attribute \src "libresoc.v:45889.9-45889.17" case 1'1 case end @@ -79847,44 +79618,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 1'0 + assign $1\dp_INT_rabc_div0_15$next[0:0]$2559 1'0 case - assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 \rp_INT_rb_shiftrot0_6 + assign $1\dp_INT_rabc_div0_15$next[0:0]$2559 \rp_INT_rabc_div0_15 end sync always - update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 + update \dp_INT_rabc_div0_15$next $0\dp_INT_rabc_div0_15$next[0:0]$2558 end - attribute \src "libresoc.v:46117.3-46126.6" - process $proc$libresoc.v:46117$2562 + attribute \src "libresoc.v:45897.3-45906.6" + process $proc$libresoc.v:45897$2560 assign { } { } assign { } { } - assign $0\fus_src2_i$69[63:0]$2563 $1\fus_src2_i$69[63:0]$2564 - attribute \src "libresoc.v:46118.5-46118.29" + assign $0\fus_src1_i$68[63:0]$2561 $1\fus_src1_i$68[63:0]$2562 + attribute \src "libresoc.v:45898.5-45898.29" switch \initial - attribute \src "libresoc.v:46118.9-46118.17" + attribute \src "libresoc.v:45898.9-45898.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_rb_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_div0_15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$69[63:0]$2564 \int_src2__data_o + assign $1\fus_src1_i$68[63:0]$2562 \int_src__data_o case - assign $1\fus_src2_i$69[63:0]$2564 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$68[63:0]$2562 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$69 $0\fus_src2_i$69[63:0]$2563 + update \fus_src1_i$68 $0\fus_src1_i$68[63:0]$2561 end - attribute \src "libresoc.v:46127.3-46135.6" - process $proc$libresoc.v:46127$2565 + attribute \src "libresoc.v:45907.3-45915.6" + process $proc$libresoc.v:45907$2563 assign { } { } assign { } { } - assign $0\dp_INT_rb_ldst0_7$next[0:0]$2566 $1\dp_INT_rb_ldst0_7$next[0:0]$2567 - attribute \src "libresoc.v:46128.5-46128.29" + assign $0\dp_INT_rabc_mul0_16$next[0:0]$2564 $1\dp_INT_rabc_mul0_16$next[0:0]$2565 + attribute \src "libresoc.v:45908.5-45908.29" switch \initial - attribute \src "libresoc.v:46128.9-46128.17" + attribute \src "libresoc.v:45908.9-45908.17" case 1'1 case end @@ -79893,44 +79664,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_ldst0_7$next[0:0]$2567 1'0 + assign $1\dp_INT_rabc_mul0_16$next[0:0]$2565 1'0 case - assign $1\dp_INT_rb_ldst0_7$next[0:0]$2567 \rp_INT_rb_ldst0_7 + assign $1\dp_INT_rabc_mul0_16$next[0:0]$2565 \rp_INT_rabc_mul0_16 end sync always - update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2566 + update \dp_INT_rabc_mul0_16$next $0\dp_INT_rabc_mul0_16$next[0:0]$2564 end - attribute \src "libresoc.v:46136.3-46145.6" - process $proc$libresoc.v:46136$2568 + attribute \src "libresoc.v:45916.3-45925.6" + process $proc$libresoc.v:45916$2566 assign { } { } assign { } { } - assign $0\fus_src2_i$70[63:0]$2569 $1\fus_src2_i$70[63:0]$2570 - attribute \src "libresoc.v:46137.5-46137.29" + assign $0\fus_src1_i$69[63:0]$2567 $1\fus_src1_i$69[63:0]$2568 + attribute \src "libresoc.v:45917.5-45917.29" switch \initial - attribute \src "libresoc.v:46137.9-46137.17" + attribute \src "libresoc.v:45917.9-45917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_rb_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_mul0_16 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$70[63:0]$2570 \int_src2__data_o + assign $1\fus_src1_i$69[63:0]$2568 \int_src__data_o case - assign $1\fus_src2_i$70[63:0]$2570 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$69[63:0]$2568 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$70 $0\fus_src2_i$70[63:0]$2569 + update \fus_src1_i$69 $0\fus_src1_i$69[63:0]$2567 end - attribute \src "libresoc.v:46146.3-46154.6" - process $proc$libresoc.v:46146$2571 + attribute \src "libresoc.v:45926.3-45934.6" + process $proc$libresoc.v:45926$2569 assign { } { } assign { } { } - assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 - attribute \src "libresoc.v:46147.5-46147.29" + assign $0\dp_INT_rabc_shiftrot0_17$next[0:0]$2570 $1\dp_INT_rabc_shiftrot0_17$next[0:0]$2571 + attribute \src "libresoc.v:45927.5-45927.29" switch \initial - attribute \src "libresoc.v:46147.9-46147.17" + attribute \src "libresoc.v:45927.9-45927.17" case 1'1 case end @@ -79939,44 +79710,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 1'0 + assign $1\dp_INT_rabc_shiftrot0_17$next[0:0]$2571 1'0 case - assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 \rp_INT_rc_shiftrot0_0 + assign $1\dp_INT_rabc_shiftrot0_17$next[0:0]$2571 \rp_INT_rabc_shiftrot0_17 end sync always - update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 + update \dp_INT_rabc_shiftrot0_17$next $0\dp_INT_rabc_shiftrot0_17$next[0:0]$2570 end - attribute \src "libresoc.v:46155.3-46164.6" - process $proc$libresoc.v:46155$2574 + attribute \src "libresoc.v:45935.3-45944.6" + process $proc$libresoc.v:45935$2572 assign { } { } assign { } { } - assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] - attribute \src "libresoc.v:46156.5-46156.29" + assign $0\fus_src1_i$70[63:0]$2573 $1\fus_src1_i$70[63:0]$2574 + attribute \src "libresoc.v:45936.5-45936.29" switch \initial - attribute \src "libresoc.v:46156.9-46156.17" + attribute \src "libresoc.v:45936.9-45936.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_rc_shiftrot0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_shiftrot0_17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i[63:0] \int_src3__data_o + assign $1\fus_src1_i$70[63:0]$2574 \int_src__data_o case - assign $1\fus_src3_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$70[63:0]$2574 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src3_i $0\fus_src3_i[63:0] + update \fus_src1_i$70 $0\fus_src1_i$70[63:0]$2573 end - attribute \src "libresoc.v:46165.3-46173.6" - process $proc$libresoc.v:46165$2575 + attribute \src "libresoc.v:45945.3-45953.6" + process $proc$libresoc.v:45945$2575 assign { } { } assign { } { } - assign $0\dp_INT_rc_ldst0_1$next[0:0]$2576 $1\dp_INT_rc_ldst0_1$next[0:0]$2577 - attribute \src "libresoc.v:46166.5-46166.29" + assign $0\dp_INT_rabc_ldst0_18$next[0:0]$2576 $1\dp_INT_rabc_ldst0_18$next[0:0]$2577 + attribute \src "libresoc.v:45946.5-45946.29" switch \initial - attribute \src "libresoc.v:46166.9-46166.17" + attribute \src "libresoc.v:45946.9-45946.17" case 1'1 case end @@ -79985,44 +79756,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rc_ldst0_1$next[0:0]$2577 1'0 + assign $1\dp_INT_rabc_ldst0_18$next[0:0]$2577 1'0 case - assign $1\dp_INT_rc_ldst0_1$next[0:0]$2577 \rp_INT_rc_ldst0_1 + assign $1\dp_INT_rabc_ldst0_18$next[0:0]$2577 \rp_INT_rabc_ldst0_18 end sync always - update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2576 + update \dp_INT_rabc_ldst0_18$next $0\dp_INT_rabc_ldst0_18$next[0:0]$2576 end - attribute \src "libresoc.v:46174.3-46183.6" - process $proc$libresoc.v:46174$2578 + attribute \src "libresoc.v:45954.3-45963.6" + process $proc$libresoc.v:45954$2578 assign { } { } assign { } { } - assign $0\fus_src3_i$71[63:0]$2579 $1\fus_src3_i$71[63:0]$2580 - attribute \src "libresoc.v:46175.5-46175.29" + assign $0\fus_src1_i$71[63:0]$2579 $1\fus_src1_i$71[63:0]$2580 + attribute \src "libresoc.v:45955.5-45955.29" switch \initial - attribute \src "libresoc.v:46175.9-46175.17" + attribute \src "libresoc.v:45955.9-45955.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_INT_rc_ldst0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_INT_rabc_ldst0_18 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$71[63:0]$2580 \int_src3__data_o + assign $1\fus_src1_i$71[63:0]$2580 \int_src__data_o case - assign $1\fus_src3_i$71[63:0]$2580 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$71[63:0]$2580 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src3_i$71 $0\fus_src3_i$71[63:0]$2579 + update \fus_src1_i$71 $0\fus_src1_i$71[63:0]$2579 end - attribute \src "libresoc.v:46184.3-46192.6" - process $proc$libresoc.v:46184$2581 + attribute \src "libresoc.v:45964.3-45972.6" + process $proc$libresoc.v:45964$2581 assign { } { } assign { } { } assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 - attribute \src "libresoc.v:46185.5-46185.29" + attribute \src "libresoc.v:45965.5-45965.29" switch \initial - attribute \src "libresoc.v:46185.9-46185.17" + attribute \src "libresoc.v:45965.9-45965.17" case 1'1 case end @@ -80038,18 +79809,18 @@ module \core sync always update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 end - attribute \src "libresoc.v:46193.3-46202.6" - process $proc$libresoc.v:46193$2584 + attribute \src "libresoc.v:45973.3-45982.6" + process $proc$libresoc.v:45973$2584 assign { } { } assign { } { } assign $0\fus_src3_i$72[0:0]$2585 $1\fus_src3_i$72[0:0]$2586 - attribute \src "libresoc.v:46194.5-46194.29" + attribute \src "libresoc.v:45974.5-45974.29" switch \initial - attribute \src "libresoc.v:46194.9-46194.17" + attribute \src "libresoc.v:45974.9-45974.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80061,14 +79832,14 @@ module \core sync always update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2585 end - attribute \src "libresoc.v:46203.3-46211.6" - process $proc$libresoc.v:46203$2587 + attribute \src "libresoc.v:45983.3-45991.6" + process $proc$libresoc.v:45983$2587 assign { } { } assign { } { } assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 - attribute \src "libresoc.v:46204.5-46204.29" + attribute \src "libresoc.v:45984.5-45984.29" switch \initial - attribute \src "libresoc.v:46204.9-46204.17" + attribute \src "libresoc.v:45984.9-45984.17" case 1'1 case end @@ -80084,18 +79855,18 @@ module \core sync always update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 end - attribute \src "libresoc.v:46212.3-46221.6" - process $proc$libresoc.v:46212$2590 + attribute \src "libresoc.v:45992.3-46001.6" + process $proc$libresoc.v:45992$2590 assign { } { } assign { } { } assign $0\fus_src3_i$73[0:0]$2591 $1\fus_src3_i$73[0:0]$2592 - attribute \src "libresoc.v:46213.5-46213.29" + attribute \src "libresoc.v:45993.5-45993.29" switch \initial - attribute \src "libresoc.v:46213.9-46213.17" + attribute \src "libresoc.v:45993.9-45993.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_logical0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80107,14 +79878,14 @@ module \core sync always update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2591 end - attribute \src "libresoc.v:46222.3-46230.6" - process $proc$libresoc.v:46222$2593 + attribute \src "libresoc.v:46002.3-46010.6" + process $proc$libresoc.v:46002$2593 assign { } { } assign { } { } assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 - attribute \src "libresoc.v:46223.5-46223.29" + attribute \src "libresoc.v:46003.5-46003.29" switch \initial - attribute \src "libresoc.v:46223.9-46223.17" + attribute \src "libresoc.v:46003.9-46003.17" case 1'1 case end @@ -80130,18 +79901,18 @@ module \core sync always update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 end - attribute \src "libresoc.v:46231.3-46240.6" - process $proc$libresoc.v:46231$2596 + attribute \src "libresoc.v:46011.3-46020.6" + process $proc$libresoc.v:46011$2596 assign { } { } assign { } { } assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] - attribute \src "libresoc.v:46232.5-46232.29" + attribute \src "libresoc.v:46012.5-46012.29" switch \initial - attribute \src "libresoc.v:46232.9-46232.17" + attribute \src "libresoc.v:46012.9-46012.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_spr0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80153,14 +79924,14 @@ module \core sync always update \fus_src4_i $0\fus_src4_i[0:0] end - attribute \src "libresoc.v:46241.3-46249.6" - process $proc$libresoc.v:46241$2597 + attribute \src "libresoc.v:46021.3-46029.6" + process $proc$libresoc.v:46021$2597 assign { } { } assign { } { } assign $0\dp_XER_xer_so_div0_3$next[0:0]$2598 $1\dp_XER_xer_so_div0_3$next[0:0]$2599 - attribute \src "libresoc.v:46242.5-46242.29" + attribute \src "libresoc.v:46022.5-46022.29" switch \initial - attribute \src "libresoc.v:46242.9-46242.17" + attribute \src "libresoc.v:46022.9-46022.17" case 1'1 case end @@ -80176,18 +79947,18 @@ module \core sync always update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2598 end - attribute \src "libresoc.v:46250.3-46259.6" - process $proc$libresoc.v:46250$2600 + attribute \src "libresoc.v:46030.3-46039.6" + process $proc$libresoc.v:46030$2600 assign { } { } assign { } { } assign $0\fus_src3_i$74[0:0]$2601 $1\fus_src3_i$74[0:0]$2602 - attribute \src "libresoc.v:46251.5-46251.29" + attribute \src "libresoc.v:46031.5-46031.29" switch \initial - attribute \src "libresoc.v:46251.9-46251.17" + attribute \src "libresoc.v:46031.9-46031.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_div0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80199,14 +79970,14 @@ module \core sync always update \fus_src3_i$74 $0\fus_src3_i$74[0:0]$2601 end - attribute \src "libresoc.v:46260.3-46268.6" - process $proc$libresoc.v:46260$2603 + attribute \src "libresoc.v:46040.3-46048.6" + process $proc$libresoc.v:46040$2603 assign { } { } assign { } { } assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 - attribute \src "libresoc.v:46261.5-46261.29" + attribute \src "libresoc.v:46041.5-46041.29" switch \initial - attribute \src "libresoc.v:46261.9-46261.17" + attribute \src "libresoc.v:46041.9-46041.17" case 1'1 case end @@ -80222,18 +79993,18 @@ module \core sync always update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 end - attribute \src "libresoc.v:46269.3-46278.6" - process $proc$libresoc.v:46269$2606 + attribute \src "libresoc.v:46049.3-46058.6" + process $proc$libresoc.v:46049$2606 assign { } { } assign { } { } assign $0\fus_src3_i$75[0:0]$2607 $1\fus_src3_i$75[0:0]$2608 - attribute \src "libresoc.v:46270.5-46270.29" + attribute \src "libresoc.v:46050.5-46050.29" switch \initial - attribute \src "libresoc.v:46270.9-46270.17" + attribute \src "libresoc.v:46050.9-46050.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_mul0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80245,14 +80016,14 @@ module \core sync always update \fus_src3_i$75 $0\fus_src3_i$75[0:0]$2607 end - attribute \src "libresoc.v:46279.3-46287.6" - process $proc$libresoc.v:46279$2609 + attribute \src "libresoc.v:46059.3-46067.6" + process $proc$libresoc.v:46059$2609 assign { } { } assign { } { } assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 - attribute \src "libresoc.v:46280.5-46280.29" + attribute \src "libresoc.v:46060.5-46060.29" switch \initial - attribute \src "libresoc.v:46280.9-46280.17" + attribute \src "libresoc.v:46060.9-46060.17" case 1'1 case end @@ -80268,18 +80039,18 @@ module \core sync always update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 end - attribute \src "libresoc.v:46288.3-46297.6" - process $proc$libresoc.v:46288$2612 + attribute \src "libresoc.v:46068.3-46077.6" + process $proc$libresoc.v:46068$2612 assign { } { } assign { } { } assign $0\fus_src4_i$76[0:0]$2613 $1\fus_src4_i$76[0:0]$2614 - attribute \src "libresoc.v:46289.5-46289.29" + attribute \src "libresoc.v:46069.5-46069.29" switch \initial - attribute \src "libresoc.v:46289.9-46289.17" + attribute \src "libresoc.v:46069.9-46069.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_shiftrot0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80291,14 +80062,14 @@ module \core sync always update \fus_src4_i$76 $0\fus_src4_i$76[0:0]$2613 end - attribute \src "libresoc.v:46298.3-46306.6" - process $proc$libresoc.v:46298$2615 + attribute \src "libresoc.v:46078.3-46086.6" + process $proc$libresoc.v:46078$2615 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 - attribute \src "libresoc.v:46299.5-46299.29" + attribute \src "libresoc.v:46079.5-46079.29" switch \initial - attribute \src "libresoc.v:46299.9-46299.17" + attribute \src "libresoc.v:46079.9-46079.17" case 1'1 case end @@ -80314,18 +80085,18 @@ module \core sync always update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 end - attribute \src "libresoc.v:46307.3-46316.6" - process $proc$libresoc.v:46307$2618 + attribute \src "libresoc.v:46087.3-46096.6" + process $proc$libresoc.v:46087$2618 assign { } { } assign { } { } assign $0\fus_src4_i$77[1:0]$2619 $1\fus_src4_i$77[1:0]$2620 - attribute \src "libresoc.v:46308.5-46308.29" + attribute \src "libresoc.v:46088.5-46088.29" switch \initial - attribute \src "libresoc.v:46308.9-46308.17" + attribute \src "libresoc.v:46088.9-46088.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_ca_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80337,14 +80108,14 @@ module \core sync always update \fus_src4_i$77 $0\fus_src4_i$77[1:0]$2619 end - attribute \src "libresoc.v:46317.3-46325.6" - process $proc$libresoc.v:46317$2621 + attribute \src "libresoc.v:46097.3-46105.6" + process $proc$libresoc.v:46097$2621 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 - attribute \src "libresoc.v:46318.5-46318.29" + attribute \src "libresoc.v:46098.5-46098.29" switch \initial - attribute \src "libresoc.v:46318.9-46318.17" + attribute \src "libresoc.v:46098.9-46098.17" case 1'1 case end @@ -80360,18 +80131,18 @@ module \core sync always update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 end - attribute \src "libresoc.v:46326.3-46335.6" - process $proc$libresoc.v:46326$2624 + attribute \src "libresoc.v:46106.3-46115.6" + process $proc$libresoc.v:46106$2624 assign { } { } assign { } { } assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] - attribute \src "libresoc.v:46327.5-46327.29" + attribute \src "libresoc.v:46107.5-46107.29" switch \initial - attribute \src "libresoc.v:46327.9-46327.17" + attribute \src "libresoc.v:46107.9-46107.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_ca_spr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80383,14 +80154,14 @@ module \core sync always update \fus_src6_i $0\fus_src6_i[1:0] end - attribute \src "libresoc.v:46336.3-46344.6" - process $proc$libresoc.v:46336$2625 + attribute \src "libresoc.v:46116.3-46124.6" + process $proc$libresoc.v:46116$2625 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 - attribute \src "libresoc.v:46337.5-46337.29" + attribute \src "libresoc.v:46117.5-46117.29" switch \initial - attribute \src "libresoc.v:46337.9-46337.17" + attribute \src "libresoc.v:46117.9-46117.17" case 1'1 case end @@ -80406,18 +80177,18 @@ module \core sync always update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 end - attribute \src "libresoc.v:46345.3-46354.6" - process $proc$libresoc.v:46345$2628 + attribute \src "libresoc.v:46125.3-46134.6" + process $proc$libresoc.v:46125$2628 assign { } { } assign { } { } assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] - attribute \src "libresoc.v:46346.5-46346.29" + attribute \src "libresoc.v:46126.5-46126.29" switch \initial - attribute \src "libresoc.v:46346.9-46346.17" + attribute \src "libresoc.v:46126.9-46126.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_ca_shiftrot0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80429,14 +80200,14 @@ module \core sync always update \fus_src5_i $0\fus_src5_i[1:0] end - attribute \src "libresoc.v:46355.3-46363.6" - process $proc$libresoc.v:46355$2629 + attribute \src "libresoc.v:46135.3-46143.6" + process $proc$libresoc.v:46135$2629 assign { } { } assign { } { } assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 - attribute \src "libresoc.v:46356.5-46356.29" + attribute \src "libresoc.v:46136.5-46136.29" switch \initial - attribute \src "libresoc.v:46356.9-46356.17" + attribute \src "libresoc.v:46136.9-46136.17" case 1'1 case end @@ -80452,18 +80223,18 @@ module \core sync always update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 end - attribute \src "libresoc.v:46364.3-46373.6" - process $proc$libresoc.v:46364$2632 + attribute \src "libresoc.v:46144.3-46153.6" + process $proc$libresoc.v:46144$2632 assign { } { } assign { } { } assign $0\fus_src5_i$78[1:0]$2633 $1\fus_src5_i$78[1:0]$2634 - attribute \src "libresoc.v:46365.5-46365.29" + attribute \src "libresoc.v:46145.5-46145.29" switch \initial - attribute \src "libresoc.v:46365.9-46365.17" + attribute \src "libresoc.v:46145.9-46145.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_ov_spr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80475,14 +80246,14 @@ module \core sync always update \fus_src5_i$78 $0\fus_src5_i$78[1:0]$2633 end - attribute \src "libresoc.v:46374.3-46382.6" - process $proc$libresoc.v:46374$2635 + attribute \src "libresoc.v:46154.3-46162.6" + process $proc$libresoc.v:46154$2635 assign { } { } assign { } { } assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 - attribute \src "libresoc.v:46375.5-46375.29" + attribute \src "libresoc.v:46155.5-46155.29" switch \initial - attribute \src "libresoc.v:46375.9-46375.17" + attribute \src "libresoc.v:46155.9-46155.17" case 1'1 case end @@ -80498,18 +80269,18 @@ module \core sync always update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 end - attribute \src "libresoc.v:46383.3-46392.6" - process $proc$libresoc.v:46383$2638 + attribute \src "libresoc.v:46163.3-46172.6" + process $proc$libresoc.v:46163$2638 assign { } { } assign { } { } assign $0\fus_src3_i$79[31:0]$2639 $1\fus_src3_i$79[31:0]$2640 - attribute \src "libresoc.v:46384.5-46384.29" + attribute \src "libresoc.v:46164.5-46164.29" switch \initial - attribute \src "libresoc.v:46384.9-46384.17" + attribute \src "libresoc.v:46164.9-46164.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_CR_full_cr_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80521,14 +80292,14 @@ module \core sync always update \fus_src3_i$79 $0\fus_src3_i$79[31:0]$2639 end - attribute \src "libresoc.v:46393.3-46401.6" - process $proc$libresoc.v:46393$2641 + attribute \src "libresoc.v:46173.3-46181.6" + process $proc$libresoc.v:46173$2641 assign { } { } assign { } { } assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 - attribute \src "libresoc.v:46394.5-46394.29" + attribute \src "libresoc.v:46174.5-46174.29" switch \initial - attribute \src "libresoc.v:46394.9-46394.17" + attribute \src "libresoc.v:46174.9-46174.17" case 1'1 case end @@ -80544,18 +80315,18 @@ module \core sync always update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 end - attribute \src "libresoc.v:46402.3-46411.6" - process $proc$libresoc.v:46402$2644 + attribute \src "libresoc.v:46182.3-46191.6" + process $proc$libresoc.v:46182$2644 assign { } { } assign { } { } assign $0\fus_src4_i$80[3:0]$2645 $1\fus_src4_i$80[3:0]$2646 - attribute \src "libresoc.v:46403.5-46403.29" + attribute \src "libresoc.v:46183.5-46183.29" switch \initial - attribute \src "libresoc.v:46403.9-46403.17" + attribute \src "libresoc.v:46183.9-46183.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_CR_cr_a_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80567,14 +80338,14 @@ module \core sync always update \fus_src4_i$80 $0\fus_src4_i$80[3:0]$2645 end - attribute \src "libresoc.v:46412.3-46420.6" - process $proc$libresoc.v:46412$2647 + attribute \src "libresoc.v:46192.3-46200.6" + process $proc$libresoc.v:46192$2647 assign { } { } assign { } { } assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 - attribute \src "libresoc.v:46413.5-46413.29" + attribute \src "libresoc.v:46193.5-46193.29" switch \initial - attribute \src "libresoc.v:46413.9-46413.17" + attribute \src "libresoc.v:46193.9-46193.17" case 1'1 case end @@ -80590,18 +80361,18 @@ module \core sync always update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 end - attribute \src "libresoc.v:46421.3-46430.6" - process $proc$libresoc.v:46421$2650 + attribute \src "libresoc.v:46201.3-46210.6" + process $proc$libresoc.v:46201$2650 assign { } { } assign { } { } assign $0\fus_src3_i$83[3:0]$2651 $1\fus_src3_i$83[3:0]$2652 - attribute \src "libresoc.v:46422.5-46422.29" + attribute \src "libresoc.v:46202.5-46202.29" switch \initial - attribute \src "libresoc.v:46422.9-46422.17" + attribute \src "libresoc.v:46202.9-46202.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_CR_cr_a_branch0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80613,66 +80384,115 @@ module \core sync always update \fus_src3_i$83 $0\fus_src3_i$83[3:0]$2651 end - attribute \src "libresoc.v:46431.3-46457.6" - process $proc$libresoc.v:46431$2653 + attribute \src "libresoc.v:46211.3-46219.6" + process $proc$libresoc.v:46211$2653 assign { } { } + assign { } { } + assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2654 $1\dp_CR_cr_b_cr0_0$next[0:0]$2655 + attribute \src "libresoc.v:46212.5-46212.29" + switch \initial + attribute \src "libresoc.v:46212.9-46212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2655 1'0 + case + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2655 \rp_CR_cr_b_cr0_0 + end + sync always + update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2654 + end + attribute \src "libresoc.v:46220.3-46250.6" + process $proc$libresoc.v:46220$2656 assign { } { } assign { } { } assign { } { } - assign $0\counter$next[1:0]$2654 $4\counter$next[1:0]$2658 - attribute \src "libresoc.v:46432.5-46432.29" + assign { } { } + assign $0\counter$next[1:0]$2657 $4\counter$next[1:0]$2661 + attribute \src "libresoc.v:46221.5-46221.29" switch \initial - attribute \src "libresoc.v:46432.9-46432.17" + attribute \src "libresoc.v:46221.9-46221.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch \$221 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\counter$next[1:0]$2655 \$223 [1:0] + assign $1\counter$next[1:0]$2658 \$223 [1:0] case - assign $1\counter$next[1:0]$2655 \counter + assign $1\counter$next[1:0]$2658 \counter end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\counter$next[1:0]$2656 $3\counter$next[1:0]$2657 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + assign $2\counter$next[1:0]$2659 $3\counter$next[1:0]$2660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $3\counter$next[1:0]$2660 $1\counter$next[1:0]$2658 + attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign { } { } - assign $3\counter$next[1:0]$2657 2'10 + assign $3\counter$next[1:0]$2660 2'10 case - assign $3\counter$next[1:0]$2657 $1\counter$next[1:0]$2655 + assign $3\counter$next[1:0]$2660 $1\counter$next[1:0]$2658 end case - assign $2\counter$next[1:0]$2656 $1\counter$next[1:0]$2655 + assign $2\counter$next[1:0]$2659 $1\counter$next[1:0]$2658 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\counter$next[1:0]$2658 2'00 + assign $4\counter$next[1:0]$2661 2'00 + case + assign $4\counter$next[1:0]$2661 $2\counter$next[1:0]$2659 + end + sync always + update \counter$next $0\counter$next[1:0]$2657 + end + attribute \src "libresoc.v:46251.3-46260.6" + process $proc$libresoc.v:46251$2662 + assign { } { } + assign { } { } + assign $0\fus_src5_i$84[3:0]$2663 $1\fus_src5_i$84[3:0]$2664 + attribute \src "libresoc.v:46252.5-46252.29" + switch \initial + attribute \src "libresoc.v:46252.9-46252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_CR_cr_b_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$84[3:0]$2664 \cr_src2__data_o case - assign $4\counter$next[1:0]$2658 $2\counter$next[1:0]$2656 + assign $1\fus_src5_i$84[3:0]$2664 4'0000 end sync always - update \counter$next $0\counter$next[1:0]$2654 + update \fus_src5_i$84 $0\fus_src5_i$84[3:0]$2663 end - attribute \src "libresoc.v:46458.3-46466.6" - process $proc$libresoc.v:46458$2659 + attribute \src "libresoc.v:46261.3-46269.6" + process $proc$libresoc.v:46261$2665 assign { } { } assign { } { } - assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 - attribute \src "libresoc.v:46459.5-46459.29" + assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 + attribute \src "libresoc.v:46262.5-46262.29" switch \initial - attribute \src "libresoc.v:46459.9-46459.17" + attribute \src "libresoc.v:46262.9-46262.17" case 1'1 case end @@ -80681,49 +80501,49 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 1'0 + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 1'0 case - assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 \rp_CR_cr_b_cr0_0 + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 \rp_CR_cr_c_cr0_0 end sync always - update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 + update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 end - attribute \src "libresoc.v:46467.3-46476.6" - process $proc$libresoc.v:46467$2662 + attribute \src "libresoc.v:46270.3-46279.6" + process $proc$libresoc.v:46270$2668 assign { } { } assign { } { } - assign $0\fus_src5_i$84[3:0]$2663 $1\fus_src5_i$84[3:0]$2664 - attribute \src "libresoc.v:46468.5-46468.29" + assign $0\fus_src6_i$85[3:0]$2669 $1\fus_src6_i$85[3:0]$2670 + attribute \src "libresoc.v:46271.5-46271.29" switch \initial - attribute \src "libresoc.v:46468.9-46468.17" + attribute \src "libresoc.v:46271.9-46271.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_CR_cr_c_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src5_i$84[3:0]$2664 \cr_src2__data_o + assign $1\fus_src6_i$85[3:0]$2670 \cr_src3__data_o case - assign $1\fus_src5_i$84[3:0]$2664 4'0000 + assign $1\fus_src6_i$85[3:0]$2670 4'0000 end sync always - update \fus_src5_i$84 $0\fus_src5_i$84[3:0]$2663 + update \fus_src6_i$85 $0\fus_src6_i$85[3:0]$2669 end - attribute \src "libresoc.v:46477.3-46567.6" - process $proc$libresoc.v:46477$2665 + attribute \src "libresoc.v:46280.3-46370.6" + process $proc$libresoc.v:46280$2671 assign { } { } assign { } { } assign { } { } assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] - attribute \src "libresoc.v:46478.5-46478.29" + attribute \src "libresoc.v:46281.5-46281.29" switch \initial - attribute \src "libresoc.v:46478.9-46478.17" + attribute \src "libresoc.v:46281.9-46281.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch \$226 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80732,13 +80552,13 @@ module \core case assign $1\corebusy_o[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80760,7 +80580,7 @@ module \core assign { } { } assign { } { } assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80769,7 +80589,7 @@ module \core case assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80778,7 +80598,7 @@ module \core case assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80787,7 +80607,7 @@ module \core case assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80796,7 +80616,7 @@ module \core case assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80805,7 +80625,7 @@ module \core case assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80814,7 +80634,7 @@ module \core case assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80823,7 +80643,7 @@ module \core case assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80832,7 +80652,7 @@ module \core case assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80841,7 +80661,7 @@ module \core case assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80857,14 +80677,14 @@ module \core sync always update \corebusy_o $0\corebusy_o[0:0] end - attribute \src "libresoc.v:46568.3-46576.6" - process $proc$libresoc.v:46568$2666 + attribute \src "libresoc.v:46371.3-46379.6" + process $proc$libresoc.v:46371$2672 assign { } { } assign { } { } - assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 - attribute \src "libresoc.v:46569.5-46569.29" + assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2673 $1\dp_FAST_fast1_branch0_0$next[0:0]$2674 + attribute \src "libresoc.v:46372.5-46372.29" switch \initial - attribute \src "libresoc.v:46569.9-46569.17" + attribute \src "libresoc.v:46372.9-46372.17" case 1'1 case end @@ -80873,86 +80693,86 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 1'0 + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2674 1'0 case - assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 \rp_CR_cr_c_cr0_0 + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2674 \rp_FAST_fast1_branch0_0 end sync always - update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 + update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2673 end - attribute \src "libresoc.v:46577.3-46586.6" - process $proc$libresoc.v:46577$2669 + attribute \src "libresoc.v:46380.3-46389.6" + process $proc$libresoc.v:46380$2675 assign { } { } assign { } { } - assign $0\fus_src6_i$85[3:0]$2670 $1\fus_src6_i$85[3:0]$2671 - attribute \src "libresoc.v:46578.5-46578.29" + assign $0\fus_src1_i$86[63:0]$2676 $1\fus_src1_i$86[63:0]$2677 + attribute \src "libresoc.v:46381.5-46381.29" switch \initial - attribute \src "libresoc.v:46578.9-46578.17" + attribute \src "libresoc.v:46381.9-46381.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_FAST_fast1_branch0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src6_i$85[3:0]$2671 \cr_src3__data_o + assign $1\fus_src1_i$86[63:0]$2677 \fast_src1__data_o case - assign $1\fus_src6_i$85[3:0]$2671 4'0000 + assign $1\fus_src1_i$86[63:0]$2677 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src6_i$85 $0\fus_src6_i$85[3:0]$2670 + update \fus_src1_i$86 $0\fus_src1_i$86[63:0]$2676 end - attribute \src "libresoc.v:46587.3-46607.6" - process $proc$libresoc.v:46587$2672 + attribute \src "libresoc.v:46390.3-46410.6" + process $proc$libresoc.v:46390$2678 assign { } { } assign { } { } assign { } { } - assign $0\core_terminate_o$next[0:0]$2673 $3\core_terminate_o$next[0:0]$2676 - attribute \src "libresoc.v:46588.5-46588.29" + assign $0\core_terminate_o$next[0:0]$2679 $3\core_terminate_o$next[0:0]$2682 + attribute \src "libresoc.v:46391.5-46391.29" switch \initial - attribute \src "libresoc.v:46588.9-46588.17" + attribute \src "libresoc.v:46391.9-46391.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_terminate_o$next[0:0]$2674 $2\core_terminate_o$next[0:0]$2675 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + assign $1\core_terminate_o$next[0:0]$2680 $2\core_terminate_o$next[0:0]$2681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign { } { } - assign $2\core_terminate_o$next[0:0]$2675 1'1 + assign $2\core_terminate_o$next[0:0]$2681 1'1 case - assign $2\core_terminate_o$next[0:0]$2675 \core_terminate_o + assign $2\core_terminate_o$next[0:0]$2681 \core_terminate_o end case - assign $1\core_terminate_o$next[0:0]$2674 \core_terminate_o + assign $1\core_terminate_o$next[0:0]$2680 \core_terminate_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_terminate_o$next[0:0]$2676 1'0 + assign $3\core_terminate_o$next[0:0]$2682 1'0 case - assign $3\core_terminate_o$next[0:0]$2676 $1\core_terminate_o$next[0:0]$2674 + assign $3\core_terminate_o$next[0:0]$2682 $1\core_terminate_o$next[0:0]$2680 end sync always - update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2673 + update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2679 end - attribute \src "libresoc.v:46608.3-46616.6" - process $proc$libresoc.v:46608$2677 + attribute \src "libresoc.v:46411.3-46419.6" + process $proc$libresoc.v:46411$2683 assign { } { } assign { } { } - assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 - attribute \src "libresoc.v:46609.5-46609.29" + assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 + attribute \src "libresoc.v:46412.5-46412.29" switch \initial - attribute \src "libresoc.v:46609.9-46609.17" + attribute \src "libresoc.v:46412.9-46412.17" case 1'1 case end @@ -80961,44 +80781,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 1'0 + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 1'0 case - assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 \rp_FAST_fast1_branch0_0 + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 \rp_FAST_fast1_trap0_1 end sync always - update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 + update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 end - attribute \src "libresoc.v:46617.3-46626.6" - process $proc$libresoc.v:46617$2680 + attribute \src "libresoc.v:46420.3-46429.6" + process $proc$libresoc.v:46420$2686 assign { } { } assign { } { } - assign $0\fus_src1_i$86[63:0]$2681 $1\fus_src1_i$86[63:0]$2682 - attribute \src "libresoc.v:46618.5-46618.29" + assign $0\fus_src3_i$87[63:0]$2687 $1\fus_src3_i$87[63:0]$2688 + attribute \src "libresoc.v:46421.5-46421.29" switch \initial - attribute \src "libresoc.v:46618.9-46618.17" + attribute \src "libresoc.v:46421.9-46421.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_FAST_fast1_trap0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$86[63:0]$2682 \fast_src1__data_o + assign $1\fus_src3_i$87[63:0]$2688 \fast_src1__data_o case - assign $1\fus_src1_i$86[63:0]$2682 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src3_i$87[63:0]$2688 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$86 $0\fus_src1_i$86[63:0]$2681 + update \fus_src3_i$87 $0\fus_src3_i$87[63:0]$2687 end - attribute \src "libresoc.v:46627.3-46635.6" - process $proc$libresoc.v:46627$2683 + attribute \src "libresoc.v:46430.3-46438.6" + process $proc$libresoc.v:46430$2689 assign { } { } assign { } { } - assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 - attribute \src "libresoc.v:46628.5-46628.29" + assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2690 $1\dp_FAST_fast1_spr0_2$next[0:0]$2691 + attribute \src "libresoc.v:46431.5-46431.29" switch \initial - attribute \src "libresoc.v:46628.9-46628.17" + attribute \src "libresoc.v:46431.9-46431.17" case 1'1 case end @@ -81007,54 +80827,54 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 1'0 + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2691 1'0 case - assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 \rp_FAST_fast1_trap0_1 + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2691 \rp_FAST_fast1_spr0_2 end sync always - update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 + update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2690 end - attribute \src "libresoc.v:46636.3-46645.6" - process $proc$libresoc.v:46636$2686 + attribute \src "libresoc.v:46439.3-46448.6" + process $proc$libresoc.v:46439$2692 assign { } { } assign { } { } - assign $0\fus_src3_i$87[63:0]$2687 $1\fus_src3_i$87[63:0]$2688 - attribute \src "libresoc.v:46637.5-46637.29" + assign $0\fus_src3_i$88[63:0]$2693 $1\fus_src3_i$88[63:0]$2694 + attribute \src "libresoc.v:46440.5-46440.29" switch \initial - attribute \src "libresoc.v:46637.9-46637.17" + attribute \src "libresoc.v:46440.9-46440.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_FAST_fast1_spr0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$87[63:0]$2688 \fast_src1__data_o + assign $1\fus_src3_i$88[63:0]$2694 \fast_src1__data_o case - assign $1\fus_src3_i$87[63:0]$2688 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src3_i$88[63:0]$2694 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src3_i$87 $0\fus_src3_i$87[63:0]$2687 + update \fus_src3_i$88 $0\fus_src3_i$88[63:0]$2693 end - attribute \src "libresoc.v:46646.3-46674.6" - process $proc$libresoc.v:46646$2689 + attribute \src "libresoc.v:46449.3-46477.6" + process $proc$libresoc.v:46449$2695 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46647.5-46647.29" + attribute \src "libresoc.v:46450.5-46450.29" switch \initial - attribute \src "libresoc.v:46647.9-46647.17" + attribute \src "libresoc.v:46450.9-46450.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81066,7 +80886,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81082,14 +80902,14 @@ module \core sync always update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] end - attribute \src "libresoc.v:46675.3-46683.6" - process $proc$libresoc.v:46675$2690 + attribute \src "libresoc.v:46478.3-46486.6" + process $proc$libresoc.v:46478$2696 assign { } { } assign { } { } - assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 - attribute \src "libresoc.v:46676.5-46676.29" + assign $0\dp_FAST_fast1_branch0_3$next[0:0]$2697 $1\dp_FAST_fast1_branch0_3$next[0:0]$2698 + attribute \src "libresoc.v:46479.5-46479.29" switch \initial - attribute \src "libresoc.v:46676.9-46676.17" + attribute \src "libresoc.v:46479.9-46479.17" case 1'1 case end @@ -81098,135 +80918,135 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 1'0 + assign $1\dp_FAST_fast1_branch0_3$next[0:0]$2698 1'0 case - assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 \rp_FAST_fast1_spr0_2 + assign $1\dp_FAST_fast1_branch0_3$next[0:0]$2698 \rp_FAST_fast1_branch0_3 end sync always - update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 + update \dp_FAST_fast1_branch0_3$next $0\dp_FAST_fast1_branch0_3$next[0:0]$2697 end - attribute \src "libresoc.v:46684.3-46693.6" - process $proc$libresoc.v:46684$2693 + attribute \src "libresoc.v:46487.3-46496.6" + process $proc$libresoc.v:46487$2699 assign { } { } assign { } { } - assign $0\fus_src3_i$88[63:0]$2694 $1\fus_src3_i$88[63:0]$2695 - attribute \src "libresoc.v:46685.5-46685.29" + assign $0\fus_src2_i$89[63:0]$2700 $1\fus_src2_i$89[63:0]$2701 + attribute \src "libresoc.v:46488.5-46488.29" switch \initial - attribute \src "libresoc.v:46685.9-46685.17" + attribute \src "libresoc.v:46488.9-46488.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_FAST_fast1_branch0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$88[63:0]$2695 \fast_src1__data_o + assign $1\fus_src2_i$89[63:0]$2701 \fast_src1__data_o case - assign $1\fus_src3_i$88[63:0]$2695 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$89[63:0]$2701 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src3_i$88 $0\fus_src3_i$88[63:0]$2694 + update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2700 end - attribute \src "libresoc.v:46694.3-46722.6" - process $proc$libresoc.v:46694$2696 + attribute \src "libresoc.v:46497.3-46505.6" + process $proc$libresoc.v:46497$2702 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__fn_unit[13:0] $1\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46695.5-46695.29" + assign $0\dp_FAST_fast1_trap0_4$next[0:0]$2703 $1\dp_FAST_fast1_trap0_4$next[0:0]$2704 + attribute \src "libresoc.v:46498.5-46498.29" switch \initial - attribute \src "libresoc.v:46695.9-46695.17" + attribute \src "libresoc.v:46498.9-46498.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" - switch \ivalid_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] $2\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] $3\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] \dec_ALU_ALU__fn_unit - case - assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 - end - end + assign $1\dp_FAST_fast1_trap0_4$next[0:0]$2704 1'0 case - assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + assign $1\dp_FAST_fast1_trap0_4$next[0:0]$2704 \rp_FAST_fast1_trap0_4 end sync always - update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[13:0] + update \dp_FAST_fast1_trap0_4$next $0\dp_FAST_fast1_trap0_4$next[0:0]$2703 end - attribute \src "libresoc.v:46723.3-46731.6" - process $proc$libresoc.v:46723$2697 + attribute \src "libresoc.v:46506.3-46515.6" + process $proc$libresoc.v:46506$2705 assign { } { } assign { } { } - assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 - attribute \src "libresoc.v:46724.5-46724.29" + assign $0\fus_src4_i$90[63:0]$2706 $1\fus_src4_i$90[63:0]$2707 + attribute \src "libresoc.v:46507.5-46507.29" switch \initial - attribute \src "libresoc.v:46724.9-46724.17" + attribute \src "libresoc.v:46507.9-46507.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_FAST_fast1_trap0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 1'0 + assign $1\fus_src4_i$90[63:0]$2707 \fast_src1__data_o case - assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 \rp_FAST_fast2_branch0_0 + assign $1\fus_src4_i$90[63:0]$2707 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 + update \fus_src4_i$90 $0\fus_src4_i$90[63:0]$2706 end - attribute \src "libresoc.v:46732.3-46741.6" - process $proc$libresoc.v:46732$2700 + attribute \src "libresoc.v:46516.3-46544.6" + process $proc$libresoc.v:46516$2708 assign { } { } assign { } { } - assign $0\fus_src2_i$89[63:0]$2701 $1\fus_src2_i$89[63:0]$2702 - attribute \src "libresoc.v:46733.5-46733.29" + assign $0\fus_oper_i_alu_alu0__fn_unit[13:0] $1\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46517.5-46517.29" switch \initial - attribute \src "libresoc.v:46733.9-46733.17" + attribute \src "libresoc.v:46517.9-46517.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" + switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$89[63:0]$2702 \fast_src2__data_o + assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] $2\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] $3\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] \dec_ALU_ALU__fn_unit + case + assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + end + end case - assign $1\fus_src2_i$89[63:0]$2702 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2701 + update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[13:0] end - attribute \src "libresoc.v:46742.3-46750.6" - process $proc$libresoc.v:46742$2703 + attribute \src "libresoc.v:46545.3-46553.6" + process $proc$libresoc.v:46545$2709 assign { } { } assign { } { } - assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 - attribute \src "libresoc.v:46743.5-46743.29" + assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2710 $1\dp_SPR_spr1_spr0_0$next[0:0]$2711 + attribute \src "libresoc.v:46546.5-46546.29" switch \initial - attribute \src "libresoc.v:46743.9-46743.17" + attribute \src "libresoc.v:46546.9-46546.17" case 1'1 case end @@ -81235,51 +81055,51 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 1'0 + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2711 1'0 case - assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 \rp_FAST_fast2_trap0_1 + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2711 \rp_SPR_spr1_spr0_0 end sync always - update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 + update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2710 end - attribute \src "libresoc.v:46751.3-46760.6" - process $proc$libresoc.v:46751$2706 + attribute \src "libresoc.v:46554.3-46563.6" + process $proc$libresoc.v:46554$2712 assign { } { } assign { } { } - assign $0\fus_src4_i$90[63:0]$2707 $1\fus_src4_i$90[63:0]$2708 - attribute \src "libresoc.v:46752.5-46752.29" + assign $0\fus_src2_i$91[63:0]$2713 $1\fus_src2_i$91[63:0]$2714 + attribute \src "libresoc.v:46555.5-46555.29" switch \initial - attribute \src "libresoc.v:46752.9-46752.17" + attribute \src "libresoc.v:46555.9-46555.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_FAST_fast2_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" + switch \dp_SPR_spr1_spr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i$90[63:0]$2708 \fast_src2__data_o + assign $1\fus_src2_i$91[63:0]$2714 \spr_spr1__data_o case - assign $1\fus_src4_i$90[63:0]$2708 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$91[63:0]$2714 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src4_i$90 $0\fus_src4_i$90[63:0]$2707 + update \fus_src2_i$91 $0\fus_src2_i$91[63:0]$2713 end - attribute \src "libresoc.v:46761.3-46790.6" - process $proc$libresoc.v:46761$2709 + attribute \src "libresoc.v:46564.3-46593.6" + process $proc$libresoc.v:46564$2715 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46762.5-46762.29" + attribute \src "libresoc.v:46565.5-46565.29" switch \initial - attribute \src "libresoc.v:46762.9-46762.17" + attribute \src "libresoc.v:46565.9-46565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81287,7 +81107,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81303,7 +81123,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81323,14 +81143,14 @@ module \core update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] end - attribute \src "libresoc.v:46791.3-46799.6" - process $proc$libresoc.v:46791$2710 + attribute \src "libresoc.v:46594.3-46602.6" + process $proc$libresoc.v:46594$2716 assign { } { } assign { } { } - assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 - attribute \src "libresoc.v:46792.5-46792.29" + assign $0\wr_pick_dly$next[0:0]$2717 $1\wr_pick_dly$next[0:0]$2718 + attribute \src "libresoc.v:46595.5-46595.29" switch \initial - attribute \src "libresoc.v:46792.9-46792.17" + attribute \src "libresoc.v:46595.9-46595.17" case 1'1 case end @@ -81339,44 +81159,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 1'0 - case - assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 \rp_SPR_spr1_spr0_0 - end - sync always - update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 - end - attribute \src "libresoc.v:46800.3-46809.6" - process $proc$libresoc.v:46800$2713 - assign { } { } - assign { } { } - assign $0\fus_src2_i$91[63:0]$2714 $1\fus_src2_i$91[63:0]$2715 - attribute \src "libresoc.v:46801.5-46801.29" - switch \initial - attribute \src "libresoc.v:46801.9-46801.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" - switch \dp_SPR_spr1_spr0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$91[63:0]$2715 \spr_spr1__data_o + assign $1\wr_pick_dly$next[0:0]$2718 1'0 case - assign $1\fus_src2_i$91[63:0]$2715 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\wr_pick_dly$next[0:0]$2718 \wr_pick end sync always - update \fus_src2_i$91 $0\fus_src2_i$91[63:0]$2714 + update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2717 end - attribute \src "libresoc.v:46810.3-46818.6" - process $proc$libresoc.v:46810$2716 + attribute \src "libresoc.v:46603.3-46611.6" + process $proc$libresoc.v:46603$2719 assign { } { } assign { } { } - assign $0\wr_pick_dly$next[0:0]$2717 $1\wr_pick_dly$next[0:0]$2718 - attribute \src "libresoc.v:46811.5-46811.29" + assign $0\wr_pick_dly$989$next[0:0]$2720 $1\wr_pick_dly$989$next[0:0]$2721 + attribute \src "libresoc.v:46604.5-46604.29" switch \initial - attribute \src "libresoc.v:46811.9-46811.17" + attribute \src "libresoc.v:46604.9-46604.17" case 1'1 case end @@ -81385,21 +81182,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$next[0:0]$2718 1'0 + assign $1\wr_pick_dly$989$next[0:0]$2721 1'0 case - assign $1\wr_pick_dly$next[0:0]$2718 \wr_pick + assign $1\wr_pick_dly$989$next[0:0]$2721 \wr_pick$986 end sync always - update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2717 + update \wr_pick_dly$989$next $0\wr_pick_dly$989$next[0:0]$2720 end - attribute \src "libresoc.v:46819.3-46827.6" - process $proc$libresoc.v:46819$2719 + attribute \src "libresoc.v:46612.3-46620.6" + process $proc$libresoc.v:46612$2722 assign { } { } assign { } { } - assign $0\wr_pick_dly$991$next[0:0]$2720 $1\wr_pick_dly$991$next[0:0]$2721 - attribute \src "libresoc.v:46820.5-46820.29" + assign $0\wr_pick_dly$1008$next[0:0]$2723 $1\wr_pick_dly$1008$next[0:0]$2724 + attribute \src "libresoc.v:46613.5-46613.29" switch \initial - attribute \src "libresoc.v:46820.9-46820.17" + attribute \src "libresoc.v:46613.9-46613.17" case 1'1 case end @@ -81408,28 +81205,28 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$991$next[0:0]$2721 1'0 + assign $1\wr_pick_dly$1008$next[0:0]$2724 1'0 case - assign $1\wr_pick_dly$991$next[0:0]$2721 \wr_pick$988 + assign $1\wr_pick_dly$1008$next[0:0]$2724 \wr_pick$1005 end sync always - update \wr_pick_dly$991$next $0\wr_pick_dly$991$next[0:0]$2720 + update \wr_pick_dly$1008$next $0\wr_pick_dly$1008$next[0:0]$2723 end - attribute \src "libresoc.v:46828.3-46857.6" - process $proc$libresoc.v:46828$2722 + attribute \src "libresoc.v:46621.3-46650.6" + process $proc$libresoc.v:46621$2725 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46829.5-46829.29" + attribute \src "libresoc.v:46622.5-46622.29" switch \initial - attribute \src "libresoc.v:46829.9-46829.17" + attribute \src "libresoc.v:46622.9-46622.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81437,7 +81234,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81453,7 +81250,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81473,14 +81270,14 @@ module \core update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] end - attribute \src "libresoc.v:46858.3-46866.6" - process $proc$libresoc.v:46858$2723 + attribute \src "libresoc.v:46651.3-46659.6" + process $proc$libresoc.v:46651$2726 assign { } { } assign { } { } - assign $0\wr_pick_dly$1010$next[0:0]$2724 $1\wr_pick_dly$1010$next[0:0]$2725 - attribute \src "libresoc.v:46859.5-46859.29" + assign $0\wr_pick_dly$1029$next[0:0]$2727 $1\wr_pick_dly$1029$next[0:0]$2728 + attribute \src "libresoc.v:46652.5-46652.29" switch \initial - attribute \src "libresoc.v:46859.9-46859.17" + attribute \src "libresoc.v:46652.9-46652.17" case 1'1 case end @@ -81489,21 +81286,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1010$next[0:0]$2725 1'0 + assign $1\wr_pick_dly$1029$next[0:0]$2728 1'0 case - assign $1\wr_pick_dly$1010$next[0:0]$2725 \wr_pick$1007 + assign $1\wr_pick_dly$1029$next[0:0]$2728 \wr_pick$1026 end sync always - update \wr_pick_dly$1010$next $0\wr_pick_dly$1010$next[0:0]$2724 + update \wr_pick_dly$1029$next $0\wr_pick_dly$1029$next[0:0]$2727 end - attribute \src "libresoc.v:46867.3-46875.6" - process $proc$libresoc.v:46867$2726 + attribute \src "libresoc.v:46660.3-46668.6" + process $proc$libresoc.v:46660$2729 assign { } { } assign { } { } - assign $0\wr_pick_dly$1031$next[0:0]$2727 $1\wr_pick_dly$1031$next[0:0]$2728 - attribute \src "libresoc.v:46868.5-46868.29" + assign $0\wr_pick_dly$1047$next[0:0]$2730 $1\wr_pick_dly$1047$next[0:0]$2731 + attribute \src "libresoc.v:46661.5-46661.29" switch \initial - attribute \src "libresoc.v:46868.9-46868.17" + attribute \src "libresoc.v:46661.9-46661.17" case 1'1 case end @@ -81512,28 +81309,51 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1031$next[0:0]$2728 1'0 + assign $1\wr_pick_dly$1047$next[0:0]$2731 1'0 case - assign $1\wr_pick_dly$1031$next[0:0]$2728 \wr_pick$1028 + assign $1\wr_pick_dly$1047$next[0:0]$2731 \wr_pick$1044 end sync always - update \wr_pick_dly$1031$next $0\wr_pick_dly$1031$next[0:0]$2727 + update \wr_pick_dly$1047$next $0\wr_pick_dly$1047$next[0:0]$2730 end - attribute \src "libresoc.v:46876.3-46905.6" - process $proc$libresoc.v:46876$2729 + attribute \src "libresoc.v:46669.3-46677.6" + process $proc$libresoc.v:46669$2732 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1069$next[0:0]$2733 $1\wr_pick_dly$1069$next[0:0]$2734 + attribute \src "libresoc.v:46670.5-46670.29" + switch \initial + attribute \src "libresoc.v:46670.9-46670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1069$next[0:0]$2734 1'0 + case + assign $1\wr_pick_dly$1069$next[0:0]$2734 \wr_pick$1066 + end + sync always + update \wr_pick_dly$1069$next $0\wr_pick_dly$1069$next[0:0]$2733 + end + attribute \src "libresoc.v:46678.3-46707.6" + process $proc$libresoc.v:46678$2735 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46877.5-46877.29" + attribute \src "libresoc.v:46679.5-46679.29" switch \initial - attribute \src "libresoc.v:46877.9-46877.17" + attribute \src "libresoc.v:46679.9-46679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81541,7 +81361,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81557,7 +81377,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81577,14 +81397,14 @@ module \core update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] end - attribute \src "libresoc.v:46906.3-46914.6" - process $proc$libresoc.v:46906$2730 + attribute \src "libresoc.v:46708.3-46716.6" + process $proc$libresoc.v:46708$2736 assign { } { } assign { } { } - assign $0\wr_pick_dly$1049$next[0:0]$2731 $1\wr_pick_dly$1049$next[0:0]$2732 - attribute \src "libresoc.v:46907.5-46907.29" + assign $0\wr_pick_dly$1089$next[0:0]$2737 $1\wr_pick_dly$1089$next[0:0]$2738 + attribute \src "libresoc.v:46709.5-46709.29" switch \initial - attribute \src "libresoc.v:46907.9-46907.17" + attribute \src "libresoc.v:46709.9-46709.17" case 1'1 case end @@ -81593,21 +81413,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1049$next[0:0]$2732 1'0 + assign $1\wr_pick_dly$1089$next[0:0]$2738 1'0 case - assign $1\wr_pick_dly$1049$next[0:0]$2732 \wr_pick$1046 + assign $1\wr_pick_dly$1089$next[0:0]$2738 \wr_pick$1086 end sync always - update \wr_pick_dly$1049$next $0\wr_pick_dly$1049$next[0:0]$2731 + update \wr_pick_dly$1089$next $0\wr_pick_dly$1089$next[0:0]$2737 end - attribute \src "libresoc.v:46915.3-46923.6" - process $proc$libresoc.v:46915$2733 + attribute \src "libresoc.v:46717.3-46725.6" + process $proc$libresoc.v:46717$2739 assign { } { } assign { } { } - assign $0\wr_pick_dly$1071$next[0:0]$2734 $1\wr_pick_dly$1071$next[0:0]$2735 - attribute \src "libresoc.v:46916.5-46916.29" + assign $0\wr_pick_dly$1109$next[0:0]$2740 $1\wr_pick_dly$1109$next[0:0]$2741 + attribute \src "libresoc.v:46718.5-46718.29" switch \initial - attribute \src "libresoc.v:46916.9-46916.17" + attribute \src "libresoc.v:46718.9-46718.17" case 1'1 case end @@ -81616,21 +81436,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1071$next[0:0]$2735 1'0 + assign $1\wr_pick_dly$1109$next[0:0]$2741 1'0 case - assign $1\wr_pick_dly$1071$next[0:0]$2735 \wr_pick$1068 + assign $1\wr_pick_dly$1109$next[0:0]$2741 \wr_pick$1106 end sync always - update \wr_pick_dly$1071$next $0\wr_pick_dly$1071$next[0:0]$2734 + update \wr_pick_dly$1109$next $0\wr_pick_dly$1109$next[0:0]$2740 end - attribute \src "libresoc.v:46924.3-46932.6" - process $proc$libresoc.v:46924$2736 + attribute \src "libresoc.v:46726.3-46734.6" + process $proc$libresoc.v:46726$2742 assign { } { } assign { } { } - assign $0\wr_pick_dly$1091$next[0:0]$2737 $1\wr_pick_dly$1091$next[0:0]$2738 - attribute \src "libresoc.v:46925.5-46925.29" + assign $0\wr_pick_dly$1128$next[0:0]$2743 $1\wr_pick_dly$1128$next[0:0]$2744 + attribute \src "libresoc.v:46727.5-46727.29" switch \initial - attribute \src "libresoc.v:46925.9-46925.17" + attribute \src "libresoc.v:46727.9-46727.17" case 1'1 case end @@ -81639,31 +81459,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1091$next[0:0]$2738 1'0 + assign $1\wr_pick_dly$1128$next[0:0]$2744 1'0 case - assign $1\wr_pick_dly$1091$next[0:0]$2738 \wr_pick$1088 + assign $1\wr_pick_dly$1128$next[0:0]$2744 \wr_pick$1125 end sync always - update \wr_pick_dly$1091$next $0\wr_pick_dly$1091$next[0:0]$2737 + update \wr_pick_dly$1128$next $0\wr_pick_dly$1128$next[0:0]$2743 end - attribute \src "libresoc.v:46933.3-46961.6" - process $proc$libresoc.v:46933$2739 + attribute \src "libresoc.v:46735.3-46763.6" + process $proc$libresoc.v:46735$2745 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46934.5-46934.29" + attribute \src "libresoc.v:46736.5-46736.29" switch \initial - attribute \src "libresoc.v:46934.9-46934.17" + attribute \src "libresoc.v:46736.9-46736.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81675,7 +81495,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81691,14 +81511,14 @@ module \core sync always update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] end - attribute \src "libresoc.v:46962.3-46970.6" - process $proc$libresoc.v:46962$2740 + attribute \src "libresoc.v:46764.3-46772.6" + process $proc$libresoc.v:46764$2746 assign { } { } assign { } { } - assign $0\wr_pick_dly$1111$next[0:0]$2741 $1\wr_pick_dly$1111$next[0:0]$2742 - attribute \src "libresoc.v:46963.5-46963.29" + assign $0\wr_pick_dly$1146$next[0:0]$2747 $1\wr_pick_dly$1146$next[0:0]$2748 + attribute \src "libresoc.v:46765.5-46765.29" switch \initial - attribute \src "libresoc.v:46963.9-46963.17" + attribute \src "libresoc.v:46765.9-46765.17" case 1'1 case end @@ -81707,54 +81527,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1111$next[0:0]$2742 1'0 + assign $1\wr_pick_dly$1146$next[0:0]$2748 1'0 case - assign $1\wr_pick_dly$1111$next[0:0]$2742 \wr_pick$1108 + assign $1\wr_pick_dly$1146$next[0:0]$2748 \wr_pick$1143 end sync always - update \wr_pick_dly$1111$next $0\wr_pick_dly$1111$next[0:0]$2741 + update \wr_pick_dly$1146$next $0\wr_pick_dly$1146$next[0:0]$2747 end - attribute \src "libresoc.v:46971.3-46979.6" - process $proc$libresoc.v:46971$2743 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1130$next[0:0]$2744 $1\wr_pick_dly$1130$next[0:0]$2745 - attribute \src "libresoc.v:46972.5-46972.29" - switch \initial - attribute \src "libresoc.v:46972.9-46972.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1130$next[0:0]$2745 1'0 - case - assign $1\wr_pick_dly$1130$next[0:0]$2745 \wr_pick$1127 - end - sync always - update \wr_pick_dly$1130$next $0\wr_pick_dly$1130$next[0:0]$2744 - end - attribute \src "libresoc.v:46980.3-47008.6" - process $proc$libresoc.v:46980$2746 + attribute \src "libresoc.v:46773.3-46801.6" + process $proc$libresoc.v:46773$2749 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46981.5-46981.29" + attribute \src "libresoc.v:46774.5-46774.29" switch \initial - attribute \src "libresoc.v:46981.9-46981.17" + attribute \src "libresoc.v:46774.9-46774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81766,7 +81563,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81782,14 +81579,14 @@ module \core sync always update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] end - attribute \src "libresoc.v:47009.3-47017.6" - process $proc$libresoc.v:47009$2747 + attribute \src "libresoc.v:46802.3-46810.6" + process $proc$libresoc.v:46802$2750 assign { } { } assign { } { } - assign $0\wr_pick_dly$1148$next[0:0]$2748 $1\wr_pick_dly$1148$next[0:0]$2749 - attribute \src "libresoc.v:47010.5-47010.29" + assign $0\wr_pick_dly$1220$next[0:0]$2751 $1\wr_pick_dly$1220$next[0:0]$2752 + attribute \src "libresoc.v:46803.5-46803.29" switch \initial - attribute \src "libresoc.v:47010.9-47010.17" + attribute \src "libresoc.v:46803.9-46803.17" case 1'1 case end @@ -81798,31 +81595,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1148$next[0:0]$2749 1'0 + assign $1\wr_pick_dly$1220$next[0:0]$2752 1'0 case - assign $1\wr_pick_dly$1148$next[0:0]$2749 \wr_pick$1145 + assign $1\wr_pick_dly$1220$next[0:0]$2752 \wr_pick$1217 end sync always - update \wr_pick_dly$1148$next $0\wr_pick_dly$1148$next[0:0]$2748 + update \wr_pick_dly$1220$next $0\wr_pick_dly$1220$next[0:0]$2751 end - attribute \src "libresoc.v:47018.3-47046.6" - process $proc$libresoc.v:47018$2750 + attribute \src "libresoc.v:46811.3-46839.6" + process $proc$libresoc.v:46811$2753 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47019.5-47019.29" + attribute \src "libresoc.v:46812.5-46812.29" switch \initial - attribute \src "libresoc.v:47019.9-47019.17" + attribute \src "libresoc.v:46812.9-46812.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__invert_out[0:0] $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81834,7 +81631,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__invert_out[0:0] $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81850,14 +81647,14 @@ module \core sync always update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] end - attribute \src "libresoc.v:47047.3-47055.6" - process $proc$libresoc.v:47047$2751 + attribute \src "libresoc.v:46840.3-46848.6" + process $proc$libresoc.v:46840$2754 assign { } { } assign { } { } - assign $0\wr_pick_dly$1222$next[0:0]$2752 $1\wr_pick_dly$1222$next[0:0]$2753 - attribute \src "libresoc.v:47048.5-47048.29" + assign $0\wr_pick_dly$1248$next[0:0]$2755 $1\wr_pick_dly$1248$next[0:0]$2756 + attribute \src "libresoc.v:46841.5-46841.29" switch \initial - attribute \src "libresoc.v:47048.9-47048.17" + attribute \src "libresoc.v:46841.9-46841.17" case 1'1 case end @@ -81866,31 +81663,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1222$next[0:0]$2753 1'0 + assign $1\wr_pick_dly$1248$next[0:0]$2756 1'0 case - assign $1\wr_pick_dly$1222$next[0:0]$2753 \wr_pick$1219 + assign $1\wr_pick_dly$1248$next[0:0]$2756 \wr_pick$1245 end sync always - update \wr_pick_dly$1222$next $0\wr_pick_dly$1222$next[0:0]$2752 + update \wr_pick_dly$1248$next $0\wr_pick_dly$1248$next[0:0]$2755 end - attribute \src "libresoc.v:47056.3-47084.6" - process $proc$libresoc.v:47056$2754 + attribute \src "libresoc.v:46849.3-46877.6" + process $proc$libresoc.v:46849$2757 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:47057.5-47057.29" + attribute \src "libresoc.v:46850.5-46850.29" switch \initial - attribute \src "libresoc.v:47057.9-47057.17" + attribute \src "libresoc.v:46850.9-46850.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81902,7 +81699,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81918,14 +81715,14 @@ module \core sync always update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] end - attribute \src "libresoc.v:47085.3-47093.6" - process $proc$libresoc.v:47085$2755 + attribute \src "libresoc.v:46878.3-46886.6" + process $proc$libresoc.v:46878$2758 assign { } { } assign { } { } - assign $0\wr_pick_dly$1250$next[0:0]$2756 $1\wr_pick_dly$1250$next[0:0]$2757 - attribute \src "libresoc.v:47086.5-47086.29" + assign $0\wr_pick_dly$1268$next[0:0]$2759 $1\wr_pick_dly$1268$next[0:0]$2760 + attribute \src "libresoc.v:46879.5-46879.29" switch \initial - attribute \src "libresoc.v:47086.9-47086.17" + attribute \src "libresoc.v:46879.9-46879.17" case 1'1 case end @@ -81934,31 +81731,54 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1250$next[0:0]$2757 1'0 + assign $1\wr_pick_dly$1268$next[0:0]$2760 1'0 case - assign $1\wr_pick_dly$1250$next[0:0]$2757 \wr_pick$1247 + assign $1\wr_pick_dly$1268$next[0:0]$2760 \wr_pick$1265 end sync always - update \wr_pick_dly$1250$next $0\wr_pick_dly$1250$next[0:0]$2756 + update \wr_pick_dly$1268$next $0\wr_pick_dly$1268$next[0:0]$2759 end - attribute \src "libresoc.v:47094.3-47122.6" - process $proc$libresoc.v:47094$2758 + attribute \src "libresoc.v:46887.3-46895.6" + process $proc$libresoc.v:46887$2761 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1288$next[0:0]$2762 $1\wr_pick_dly$1288$next[0:0]$2763 + attribute \src "libresoc.v:46888.5-46888.29" + switch \initial + attribute \src "libresoc.v:46888.9-46888.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1288$next[0:0]$2763 1'0 + case + assign $1\wr_pick_dly$1288$next[0:0]$2763 \wr_pick$1285 + end + sync always + update \wr_pick_dly$1288$next $0\wr_pick_dly$1288$next[0:0]$2762 + end + attribute \src "libresoc.v:46896.3-46924.6" + process $proc$libresoc.v:46896$2764 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47095.5-47095.29" + attribute \src "libresoc.v:46897.5-46897.29" switch \initial - attribute \src "libresoc.v:47095.9-47095.17" + attribute \src "libresoc.v:46897.9-46897.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__input_carry[1:0] $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81970,7 +81790,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__input_carry[1:0] $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81986,14 +81806,14 @@ module \core sync always update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] end - attribute \src "libresoc.v:47123.3-47131.6" - process $proc$libresoc.v:47123$2759 + attribute \src "libresoc.v:46925.3-46933.6" + process $proc$libresoc.v:46925$2765 assign { } { } assign { } { } - assign $0\wr_pick_dly$1270$next[0:0]$2760 $1\wr_pick_dly$1270$next[0:0]$2761 - attribute \src "libresoc.v:47124.5-47124.29" + assign $0\wr_pick_dly$1308$next[0:0]$2766 $1\wr_pick_dly$1308$next[0:0]$2767 + attribute \src "libresoc.v:46926.5-46926.29" switch \initial - attribute \src "libresoc.v:47124.9-47124.17" + attribute \src "libresoc.v:46926.9-46926.17" case 1'1 case end @@ -82002,21 +81822,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1270$next[0:0]$2761 1'0 + assign $1\wr_pick_dly$1308$next[0:0]$2767 1'0 case - assign $1\wr_pick_dly$1270$next[0:0]$2761 \wr_pick$1267 + assign $1\wr_pick_dly$1308$next[0:0]$2767 \wr_pick$1305 end sync always - update \wr_pick_dly$1270$next $0\wr_pick_dly$1270$next[0:0]$2760 + update \wr_pick_dly$1308$next $0\wr_pick_dly$1308$next[0:0]$2766 end - attribute \src "libresoc.v:47132.3-47140.6" - process $proc$libresoc.v:47132$2762 + attribute \src "libresoc.v:46934.3-46942.6" + process $proc$libresoc.v:46934$2768 assign { } { } assign { } { } - assign $0\wr_pick_dly$1290$next[0:0]$2763 $1\wr_pick_dly$1290$next[0:0]$2764 - attribute \src "libresoc.v:47133.5-47133.29" + assign $0\wr_pick_dly$1328$next[0:0]$2769 $1\wr_pick_dly$1328$next[0:0]$2770 + attribute \src "libresoc.v:46935.5-46935.29" switch \initial - attribute \src "libresoc.v:47133.9-47133.17" + attribute \src "libresoc.v:46935.9-46935.17" case 1'1 case end @@ -82025,31 +81845,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1290$next[0:0]$2764 1'0 + assign $1\wr_pick_dly$1328$next[0:0]$2770 1'0 case - assign $1\wr_pick_dly$1290$next[0:0]$2764 \wr_pick$1287 + assign $1\wr_pick_dly$1328$next[0:0]$2770 \wr_pick$1325 end sync always - update \wr_pick_dly$1290$next $0\wr_pick_dly$1290$next[0:0]$2763 + update \wr_pick_dly$1328$next $0\wr_pick_dly$1328$next[0:0]$2769 end - attribute \src "libresoc.v:47141.3-47169.6" - process $proc$libresoc.v:47141$2765 + attribute \src "libresoc.v:46943.3-46971.6" + process $proc$libresoc.v:46943$2771 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:47142.5-47142.29" + attribute \src "libresoc.v:46944.5-46944.29" switch \initial - attribute \src "libresoc.v:47142.9-47142.17" + attribute \src "libresoc.v:46944.9-46944.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__output_carry[0:0] $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82061,7 +81881,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__output_carry[0:0] $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82077,14 +81897,14 @@ module \core sync always update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] end - attribute \src "libresoc.v:47170.3-47178.6" - process $proc$libresoc.v:47170$2766 + attribute \src "libresoc.v:46972.3-46980.6" + process $proc$libresoc.v:46972$2772 assign { } { } assign { } { } - assign $0\wr_pick_dly$1310$next[0:0]$2767 $1\wr_pick_dly$1310$next[0:0]$2768 - attribute \src "libresoc.v:47171.5-47171.29" + assign $0\wr_pick_dly$1348$next[0:0]$2773 $1\wr_pick_dly$1348$next[0:0]$2774 + attribute \src "libresoc.v:46973.5-46973.29" switch \initial - attribute \src "libresoc.v:47171.9-47171.17" + attribute \src "libresoc.v:46973.9-46973.17" case 1'1 case end @@ -82093,54 +81913,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1310$next[0:0]$2768 1'0 + assign $1\wr_pick_dly$1348$next[0:0]$2774 1'0 case - assign $1\wr_pick_dly$1310$next[0:0]$2768 \wr_pick$1307 + assign $1\wr_pick_dly$1348$next[0:0]$2774 \wr_pick$1345 end sync always - update \wr_pick_dly$1310$next $0\wr_pick_dly$1310$next[0:0]$2767 + update \wr_pick_dly$1348$next $0\wr_pick_dly$1348$next[0:0]$2773 end - attribute \src "libresoc.v:47179.3-47187.6" - process $proc$libresoc.v:47179$2769 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1330$next[0:0]$2770 $1\wr_pick_dly$1330$next[0:0]$2771 - attribute \src "libresoc.v:47180.5-47180.29" - switch \initial - attribute \src "libresoc.v:47180.9-47180.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1330$next[0:0]$2771 1'0 - case - assign $1\wr_pick_dly$1330$next[0:0]$2771 \wr_pick$1327 - end - sync always - update \wr_pick_dly$1330$next $0\wr_pick_dly$1330$next[0:0]$2770 - end - attribute \src "libresoc.v:47188.3-47216.6" - process $proc$libresoc.v:47188$2772 + attribute \src "libresoc.v:46981.3-47009.6" + process $proc$libresoc.v:46981$2775 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47189.5-47189.29" + attribute \src "libresoc.v:46982.5-46982.29" switch \initial - attribute \src "libresoc.v:47189.9-47189.17" + attribute \src "libresoc.v:46982.9-46982.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82152,7 +81949,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82168,14 +81965,14 @@ module \core sync always update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] end - attribute \src "libresoc.v:47217.3-47225.6" - process $proc$libresoc.v:47217$2773 + attribute \src "libresoc.v:47010.3-47018.6" + process $proc$libresoc.v:47010$2776 assign { } { } assign { } { } - assign $0\wr_pick_dly$1350$next[0:0]$2774 $1\wr_pick_dly$1350$next[0:0]$2775 - attribute \src "libresoc.v:47218.5-47218.29" + assign $0\wr_pick_dly$1395$next[0:0]$2777 $1\wr_pick_dly$1395$next[0:0]$2778 + attribute \src "libresoc.v:47011.5-47011.29" switch \initial - attribute \src "libresoc.v:47218.9-47218.17" + attribute \src "libresoc.v:47011.9-47011.17" case 1'1 case end @@ -82184,31 +81981,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1350$next[0:0]$2775 1'0 + assign $1\wr_pick_dly$1395$next[0:0]$2778 1'0 case - assign $1\wr_pick_dly$1350$next[0:0]$2775 \wr_pick$1347 + assign $1\wr_pick_dly$1395$next[0:0]$2778 \wr_pick$1392 end sync always - update \wr_pick_dly$1350$next $0\wr_pick_dly$1350$next[0:0]$2774 + update \wr_pick_dly$1395$next $0\wr_pick_dly$1395$next[0:0]$2777 end - attribute \src "libresoc.v:47226.3-47254.6" - process $proc$libresoc.v:47226$2776 + attribute \src "libresoc.v:47019.3-47047.6" + process $proc$libresoc.v:47019$2779 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:47227.5-47227.29" + attribute \src "libresoc.v:47020.5-47020.29" switch \initial - attribute \src "libresoc.v:47227.9-47227.17" + attribute \src "libresoc.v:47020.9-47020.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__is_signed[0:0] $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82220,7 +82017,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__is_signed[0:0] $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82236,14 +82033,14 @@ module \core sync always update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] end - attribute \src "libresoc.v:47255.3-47263.6" - process $proc$libresoc.v:47255$2777 + attribute \src "libresoc.v:47048.3-47056.6" + process $proc$libresoc.v:47048$2780 assign { } { } assign { } { } - assign $0\wr_pick_dly$1397$next[0:0]$2778 $1\wr_pick_dly$1397$next[0:0]$2779 - attribute \src "libresoc.v:47256.5-47256.29" + assign $0\wr_pick_dly$1411$next[0:0]$2781 $1\wr_pick_dly$1411$next[0:0]$2782 + attribute \src "libresoc.v:47049.5-47049.29" switch \initial - attribute \src "libresoc.v:47256.9-47256.17" + attribute \src "libresoc.v:47049.9-47049.17" case 1'1 case end @@ -82252,21 +82049,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1397$next[0:0]$2779 1'0 + assign $1\wr_pick_dly$1411$next[0:0]$2782 1'0 case - assign $1\wr_pick_dly$1397$next[0:0]$2779 \wr_pick$1394 + assign $1\wr_pick_dly$1411$next[0:0]$2782 \wr_pick$1408 end sync always - update \wr_pick_dly$1397$next $0\wr_pick_dly$1397$next[0:0]$2778 + update \wr_pick_dly$1411$next $0\wr_pick_dly$1411$next[0:0]$2781 end - attribute \src "libresoc.v:47264.3-47272.6" - process $proc$libresoc.v:47264$2780 + attribute \src "libresoc.v:47057.3-47065.6" + process $proc$libresoc.v:47057$2783 assign { } { } assign { } { } - assign $0\wr_pick_dly$1413$next[0:0]$2781 $1\wr_pick_dly$1413$next[0:0]$2782 - attribute \src "libresoc.v:47265.5-47265.29" + assign $0\wr_pick_dly$1427$next[0:0]$2784 $1\wr_pick_dly$1427$next[0:0]$2785 + attribute \src "libresoc.v:47058.5-47058.29" switch \initial - attribute \src "libresoc.v:47265.9-47265.17" + attribute \src "libresoc.v:47058.9-47058.17" case 1'1 case end @@ -82275,31 +82072,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1413$next[0:0]$2782 1'0 + assign $1\wr_pick_dly$1427$next[0:0]$2785 1'0 case - assign $1\wr_pick_dly$1413$next[0:0]$2782 \wr_pick$1410 + assign $1\wr_pick_dly$1427$next[0:0]$2785 \wr_pick$1424 end sync always - update \wr_pick_dly$1413$next $0\wr_pick_dly$1413$next[0:0]$2781 + update \wr_pick_dly$1427$next $0\wr_pick_dly$1427$next[0:0]$2784 end - attribute \src "libresoc.v:47273.3-47301.6" - process $proc$libresoc.v:47273$2783 + attribute \src "libresoc.v:47066.3-47094.6" + process $proc$libresoc.v:47066$2786 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:47274.5-47274.29" + attribute \src "libresoc.v:47067.5-47067.29" switch \initial - attribute \src "libresoc.v:47274.9-47274.17" + attribute \src "libresoc.v:47067.9-47067.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__data_len[3:0] $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82311,7 +82108,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__data_len[3:0] $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82327,14 +82124,14 @@ module \core sync always update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] end - attribute \src "libresoc.v:47302.3-47310.6" - process $proc$libresoc.v:47302$2784 + attribute \src "libresoc.v:47095.3-47103.6" + process $proc$libresoc.v:47095$2787 assign { } { } assign { } { } - assign $0\wr_pick_dly$1429$next[0:0]$2785 $1\wr_pick_dly$1429$next[0:0]$2786 - attribute \src "libresoc.v:47303.5-47303.29" + assign $0\wr_pick_dly$1461$next[0:0]$2788 $1\wr_pick_dly$1461$next[0:0]$2789 + attribute \src "libresoc.v:47096.5-47096.29" switch \initial - attribute \src "libresoc.v:47303.9-47303.17" + attribute \src "libresoc.v:47096.9-47096.17" case 1'1 case end @@ -82343,31 +82140,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1429$next[0:0]$2786 1'0 + assign $1\wr_pick_dly$1461$next[0:0]$2789 1'0 case - assign $1\wr_pick_dly$1429$next[0:0]$2786 \wr_pick$1426 + assign $1\wr_pick_dly$1461$next[0:0]$2789 \wr_pick$1458 end sync always - update \wr_pick_dly$1429$next $0\wr_pick_dly$1429$next[0:0]$2785 + update \wr_pick_dly$1461$next $0\wr_pick_dly$1461$next[0:0]$2788 end - attribute \src "libresoc.v:47311.3-47339.6" - process $proc$libresoc.v:47311$2787 + attribute \src "libresoc.v:47104.3-47132.6" + process $proc$libresoc.v:47104$2790 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:47312.5-47312.29" + attribute \src "libresoc.v:47105.5-47105.29" switch \initial - attribute \src "libresoc.v:47312.9-47312.17" + attribute \src "libresoc.v:47105.9-47105.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__insn[31:0] $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82379,7 +82176,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__insn[31:0] $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82395,14 +82192,37 @@ module \core sync always update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] end - attribute \src "libresoc.v:47340.3-47348.6" - process $proc$libresoc.v:47340$2788 + attribute \src "libresoc.v:47133.3-47141.6" + process $proc$libresoc.v:47133$2791 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1477$next[0:0]$2792 $1\wr_pick_dly$1477$next[0:0]$2793 + attribute \src "libresoc.v:47134.5-47134.29" + switch \initial + attribute \src "libresoc.v:47134.9-47134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1477$next[0:0]$2793 1'0 + case + assign $1\wr_pick_dly$1477$next[0:0]$2793 \wr_pick$1474 + end + sync always + update \wr_pick_dly$1477$next $0\wr_pick_dly$1477$next[0:0]$2792 + end + attribute \src "libresoc.v:47142.3-47150.6" + process $proc$libresoc.v:47142$2794 assign { } { } assign { } { } - assign $0\wr_pick_dly$1463$next[0:0]$2789 $1\wr_pick_dly$1463$next[0:0]$2790 - attribute \src "libresoc.v:47341.5-47341.29" + assign $0\wr_pick_dly$1493$next[0:0]$2795 $1\wr_pick_dly$1493$next[0:0]$2796 + attribute \src "libresoc.v:47143.5-47143.29" switch \initial - attribute \src "libresoc.v:47341.9-47341.17" + attribute \src "libresoc.v:47143.9-47143.17" case 1'1 case end @@ -82411,31 +82231,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1463$next[0:0]$2790 1'0 + assign $1\wr_pick_dly$1493$next[0:0]$2796 1'0 case - assign $1\wr_pick_dly$1463$next[0:0]$2790 \wr_pick$1460 + assign $1\wr_pick_dly$1493$next[0:0]$2796 \wr_pick$1490 end sync always - update \wr_pick_dly$1463$next $0\wr_pick_dly$1463$next[0:0]$2789 + update \wr_pick_dly$1493$next $0\wr_pick_dly$1493$next[0:0]$2795 end - attribute \src "libresoc.v:47349.3-47377.6" - process $proc$libresoc.v:47349$2791 + attribute \src "libresoc.v:47151.3-47179.6" + process $proc$libresoc.v:47151$2797 assign { } { } assign { } { } assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47350.5-47350.29" + attribute \src "libresoc.v:47152.5-47152.29" switch \initial - attribute \src "libresoc.v:47350.9-47350.17" + attribute \src "libresoc.v:47152.9-47152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i[0:0] $2\fus_cu_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82447,7 +82267,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i[0:0] $3\fus_cu_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82463,14 +82283,14 @@ module \core sync always update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] end - attribute \src "libresoc.v:47378.3-47386.6" - process $proc$libresoc.v:47378$2792 + attribute \src "libresoc.v:47180.3-47188.6" + process $proc$libresoc.v:47180$2798 assign { } { } assign { } { } - assign $0\wr_pick_dly$1479$next[0:0]$2793 $1\wr_pick_dly$1479$next[0:0]$2794 - attribute \src "libresoc.v:47379.5-47379.29" + assign $0\wr_pick_dly$1509$next[0:0]$2799 $1\wr_pick_dly$1509$next[0:0]$2800 + attribute \src "libresoc.v:47181.5-47181.29" switch \initial - attribute \src "libresoc.v:47379.9-47379.17" + attribute \src "libresoc.v:47181.9-47181.17" case 1'1 case end @@ -82479,54 +82299,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1479$next[0:0]$2794 1'0 + assign $1\wr_pick_dly$1509$next[0:0]$2800 1'0 case - assign $1\wr_pick_dly$1479$next[0:0]$2794 \wr_pick$1476 + assign $1\wr_pick_dly$1509$next[0:0]$2800 \wr_pick$1506 end sync always - update \wr_pick_dly$1479$next $0\wr_pick_dly$1479$next[0:0]$2793 + update \wr_pick_dly$1509$next $0\wr_pick_dly$1509$next[0:0]$2799 end - attribute \src "libresoc.v:47387.3-47395.6" - process $proc$libresoc.v:47387$2795 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1495$next[0:0]$2796 $1\wr_pick_dly$1495$next[0:0]$2797 - attribute \src "libresoc.v:47388.5-47388.29" - switch \initial - attribute \src "libresoc.v:47388.9-47388.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1495$next[0:0]$2797 1'0 - case - assign $1\wr_pick_dly$1495$next[0:0]$2797 \wr_pick$1492 - end - sync always - update \wr_pick_dly$1495$next $0\wr_pick_dly$1495$next[0:0]$2796 - end - attribute \src "libresoc.v:47396.3-47424.6" - process $proc$libresoc.v:47396$2798 + attribute \src "libresoc.v:47189.3-47217.6" + process $proc$libresoc.v:47189$2801 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47397.5-47397.29" + attribute \src "libresoc.v:47190.5-47190.29" switch \initial - attribute \src "libresoc.v:47397.9-47397.17" + attribute \src "libresoc.v:47190.9-47190.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i[3:0] $2\fus_cu_rdmaskn_i[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82538,7 +82335,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i[3:0] $3\fus_cu_rdmaskn_i[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82554,14 +82351,37 @@ module \core sync always update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] end - attribute \src "libresoc.v:47425.3-47433.6" - process $proc$libresoc.v:47425$2799 + attribute \src "libresoc.v:47218.3-47226.6" + process $proc$libresoc.v:47218$2802 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1545$next[0:0]$2803 $1\wr_pick_dly$1545$next[0:0]$2804 + attribute \src "libresoc.v:47219.5-47219.29" + switch \initial + attribute \src "libresoc.v:47219.9-47219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1545$next[0:0]$2804 1'0 + case + assign $1\wr_pick_dly$1545$next[0:0]$2804 \wr_pick$1542 + end + sync always + update \wr_pick_dly$1545$next $0\wr_pick_dly$1545$next[0:0]$2803 + end + attribute \src "libresoc.v:47227.3-47235.6" + process $proc$libresoc.v:47227$2805 assign { } { } assign { } { } - assign $0\wr_pick_dly$1511$next[0:0]$2800 $1\wr_pick_dly$1511$next[0:0]$2801 - attribute \src "libresoc.v:47426.5-47426.29" + assign $0\wr_pick_dly$1561$next[0:0]$2806 $1\wr_pick_dly$1561$next[0:0]$2807 + attribute \src "libresoc.v:47228.5-47228.29" switch \initial - attribute \src "libresoc.v:47426.9-47426.17" + attribute \src "libresoc.v:47228.9-47228.17" case 1'1 case end @@ -82570,31 +82390,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1511$next[0:0]$2801 1'0 + assign $1\wr_pick_dly$1561$next[0:0]$2807 1'0 case - assign $1\wr_pick_dly$1511$next[0:0]$2801 \wr_pick$1508 + assign $1\wr_pick_dly$1561$next[0:0]$2807 \wr_pick$1558 end sync always - update \wr_pick_dly$1511$next $0\wr_pick_dly$1511$next[0:0]$2800 + update \wr_pick_dly$1561$next $0\wr_pick_dly$1561$next[0:0]$2806 end - attribute \src "libresoc.v:47434.3-47462.6" - process $proc$libresoc.v:47434$2802 + attribute \src "libresoc.v:47236.3-47264.6" + process $proc$libresoc.v:47236$2808 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:47435.5-47435.29" + attribute \src "libresoc.v:47237.5-47237.29" switch \initial - attribute \src "libresoc.v:47435.9-47435.17" + attribute \src "libresoc.v:47237.9-47237.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__insn_type[6:0] $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82606,7 +82426,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_cr0__insn_type[6:0] $3\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82622,14 +82442,14 @@ module \core sync always update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] end - attribute \src "libresoc.v:47463.3-47471.6" - process $proc$libresoc.v:47463$2803 + attribute \src "libresoc.v:47265.3-47273.6" + process $proc$libresoc.v:47265$2809 assign { } { } assign { } { } - assign $0\wr_pick_dly$1547$next[0:0]$2804 $1\wr_pick_dly$1547$next[0:0]$2805 - attribute \src "libresoc.v:47464.5-47464.29" + assign $0\wr_pick_dly$1577$next[0:0]$2810 $1\wr_pick_dly$1577$next[0:0]$2811 + attribute \src "libresoc.v:47266.5-47266.29" switch \initial - attribute \src "libresoc.v:47464.9-47464.17" + attribute \src "libresoc.v:47266.9-47266.17" case 1'1 case end @@ -82638,54 +82458,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1547$next[0:0]$2805 1'0 + assign $1\wr_pick_dly$1577$next[0:0]$2811 1'0 case - assign $1\wr_pick_dly$1547$next[0:0]$2805 \wr_pick$1544 + assign $1\wr_pick_dly$1577$next[0:0]$2811 \wr_pick$1574 end sync always - update \wr_pick_dly$1547$next $0\wr_pick_dly$1547$next[0:0]$2804 + update \wr_pick_dly$1577$next $0\wr_pick_dly$1577$next[0:0]$2810 end - attribute \src "libresoc.v:47472.3-47480.6" - process $proc$libresoc.v:47472$2806 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1563$next[0:0]$2807 $1\wr_pick_dly$1563$next[0:0]$2808 - attribute \src "libresoc.v:47473.5-47473.29" - switch \initial - attribute \src "libresoc.v:47473.9-47473.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1563$next[0:0]$2808 1'0 - case - assign $1\wr_pick_dly$1563$next[0:0]$2808 \wr_pick$1560 - end - sync always - update \wr_pick_dly$1563$next $0\wr_pick_dly$1563$next[0:0]$2807 - end - attribute \src "libresoc.v:47481.3-47509.6" - process $proc$libresoc.v:47481$2809 + attribute \src "libresoc.v:47274.3-47302.6" + process $proc$libresoc.v:47274$2812 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__fn_unit[13:0] $1\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47482.5-47482.29" + attribute \src "libresoc.v:47275.5-47275.29" switch \initial - attribute \src "libresoc.v:47482.9-47482.17" + attribute \src "libresoc.v:47275.9-47275.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__fn_unit[13:0] $2\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82697,7 +82494,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] $3\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82713,14 +82510,14 @@ module \core sync always update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[13:0] end - attribute \src "libresoc.v:47510.3-47518.6" - process $proc$libresoc.v:47510$2810 + attribute \src "libresoc.v:47303.3-47311.6" + process $proc$libresoc.v:47303$2813 assign { } { } assign { } { } - assign $0\wr_pick_dly$1579$next[0:0]$2811 $1\wr_pick_dly$1579$next[0:0]$2812 - attribute \src "libresoc.v:47511.5-47511.29" + assign $0\wr_pick_dly$1593$next[0:0]$2814 $1\wr_pick_dly$1593$next[0:0]$2815 + attribute \src "libresoc.v:47304.5-47304.29" switch \initial - attribute \src "libresoc.v:47511.9-47511.17" + attribute \src "libresoc.v:47304.9-47304.17" case 1'1 case end @@ -82729,21 +82526,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1579$next[0:0]$2812 1'0 + assign $1\wr_pick_dly$1593$next[0:0]$2815 1'0 case - assign $1\wr_pick_dly$1579$next[0:0]$2812 \wr_pick$1576 + assign $1\wr_pick_dly$1593$next[0:0]$2815 \wr_pick$1590 end sync always - update \wr_pick_dly$1579$next $0\wr_pick_dly$1579$next[0:0]$2811 + update \wr_pick_dly$1593$next $0\wr_pick_dly$1593$next[0:0]$2814 end - attribute \src "libresoc.v:47519.3-47527.6" - process $proc$libresoc.v:47519$2813 + attribute \src "libresoc.v:47312.3-47320.6" + process $proc$libresoc.v:47312$2816 assign { } { } assign { } { } - assign $0\wr_pick_dly$1595$next[0:0]$2814 $1\wr_pick_dly$1595$next[0:0]$2815 - attribute \src "libresoc.v:47520.5-47520.29" + assign $0\wr_pick_dly$1635$next[0:0]$2817 $1\wr_pick_dly$1635$next[0:0]$2818 + attribute \src "libresoc.v:47313.5-47313.29" switch \initial - attribute \src "libresoc.v:47520.9-47520.17" + attribute \src "libresoc.v:47313.9-47313.17" case 1'1 case end @@ -82752,31 +82549,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1595$next[0:0]$2815 1'0 + assign $1\wr_pick_dly$1635$next[0:0]$2818 1'0 case - assign $1\wr_pick_dly$1595$next[0:0]$2815 \wr_pick$1592 + assign $1\wr_pick_dly$1635$next[0:0]$2818 \wr_pick$1632 end sync always - update \wr_pick_dly$1595$next $0\wr_pick_dly$1595$next[0:0]$2814 + update \wr_pick_dly$1635$next $0\wr_pick_dly$1635$next[0:0]$2817 end - attribute \src "libresoc.v:47528.3-47556.6" - process $proc$libresoc.v:47528$2816 + attribute \src "libresoc.v:47321.3-47349.6" + process $proc$libresoc.v:47321$2819 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47529.5-47529.29" + attribute \src "libresoc.v:47322.5-47322.29" switch \initial - attribute \src "libresoc.v:47529.9-47529.17" + attribute \src "libresoc.v:47322.9-47322.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__insn[31:0] $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82788,7 +82585,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_cr0__insn[31:0] $3\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82804,14 +82601,14 @@ module \core sync always update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] end - attribute \src "libresoc.v:47557.3-47565.6" - process $proc$libresoc.v:47557$2817 + attribute \src "libresoc.v:47350.3-47358.6" + process $proc$libresoc.v:47350$2820 assign { } { } assign { } { } - assign $0\wr_pick_dly$1637$next[0:0]$2818 $1\wr_pick_dly$1637$next[0:0]$2819 - attribute \src "libresoc.v:47558.5-47558.29" + assign $0\wr_pick_dly$1654$next[0:0]$2821 $1\wr_pick_dly$1654$next[0:0]$2822 + attribute \src "libresoc.v:47351.5-47351.29" switch \initial - attribute \src "libresoc.v:47558.9-47558.17" + attribute \src "libresoc.v:47351.9-47351.17" case 1'1 case end @@ -82820,66 +82617,89 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1637$next[0:0]$2819 1'0 + assign $1\wr_pick_dly$1654$next[0:0]$2822 1'0 case - assign $1\wr_pick_dly$1637$next[0:0]$2819 \wr_pick$1634 + assign $1\wr_pick_dly$1654$next[0:0]$2822 \wr_pick$1651 end sync always - update \wr_pick_dly$1637$next $0\wr_pick_dly$1637$next[0:0]$2818 + update \wr_pick_dly$1654$next $0\wr_pick_dly$1654$next[0:0]$2821 end - attribute \src "libresoc.v:47566.3-47594.6" - process $proc$libresoc.v:47566$2820 + attribute \src "libresoc.v:47359.3-47387.6" + process $proc$libresoc.v:47359$2823 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$13[0:0]$2821 $1\fus_cu_issue_i$13[0:0]$2822 - attribute \src "libresoc.v:47567.5-47567.29" + assign $0\fus_cu_issue_i$13[0:0]$2824 $1\fus_cu_issue_i$13[0:0]$2825 + attribute \src "libresoc.v:47360.5-47360.29" switch \initial - attribute \src "libresoc.v:47567.9-47567.17" + attribute \src "libresoc.v:47360.9-47360.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$13[0:0]$2822 $2\fus_cu_issue_i$13[0:0]$2823 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + assign $1\fus_cu_issue_i$13[0:0]$2825 $2\fus_cu_issue_i$13[0:0]$2826 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$13[0:0]$2823 1'0 + assign $2\fus_cu_issue_i$13[0:0]$2826 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$13[0:0]$2823 1'0 + assign $2\fus_cu_issue_i$13[0:0]$2826 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$13[0:0]$2823 $3\fus_cu_issue_i$13[0:0]$2824 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + assign $2\fus_cu_issue_i$13[0:0]$2826 $3\fus_cu_issue_i$13[0:0]$2827 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$13[0:0]$2824 \issue_i + assign $3\fus_cu_issue_i$13[0:0]$2827 \issue_i case - assign $3\fus_cu_issue_i$13[0:0]$2824 1'0 + assign $3\fus_cu_issue_i$13[0:0]$2827 1'0 end end case - assign $1\fus_cu_issue_i$13[0:0]$2822 1'0 + assign $1\fus_cu_issue_i$13[0:0]$2825 1'0 + end + sync always + update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2824 + end + attribute \src "libresoc.v:47388.3-47396.6" + process $proc$libresoc.v:47388$2828 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1670$next[0:0]$2829 $1\wr_pick_dly$1670$next[0:0]$2830 + attribute \src "libresoc.v:47389.5-47389.29" + switch \initial + attribute \src "libresoc.v:47389.9-47389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1670$next[0:0]$2830 1'0 + case + assign $1\wr_pick_dly$1670$next[0:0]$2830 \wr_pick$1667 end sync always - update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2821 + update \wr_pick_dly$1670$next $0\wr_pick_dly$1670$next[0:0]$2829 end - attribute \src "libresoc.v:47595.3-47603.6" - process $proc$libresoc.v:47595$2825 + attribute \src "libresoc.v:47397.3-47405.6" + process $proc$libresoc.v:47397$2831 assign { } { } assign { } { } - assign $0\wr_pick_dly$1656$next[0:0]$2826 $1\wr_pick_dly$1656$next[0:0]$2827 - attribute \src "libresoc.v:47596.5-47596.29" + assign $0\wr_pick_dly$1686$next[0:0]$2832 $1\wr_pick_dly$1686$next[0:0]$2833 + attribute \src "libresoc.v:47398.5-47398.29" switch \initial - attribute \src "libresoc.v:47596.9-47596.17" + attribute \src "libresoc.v:47398.9-47398.17" case 1'1 case end @@ -82888,66 +82708,66 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1656$next[0:0]$2827 1'0 + assign $1\wr_pick_dly$1686$next[0:0]$2833 1'0 case - assign $1\wr_pick_dly$1656$next[0:0]$2827 \wr_pick$1653 + assign $1\wr_pick_dly$1686$next[0:0]$2833 \wr_pick$1683 end sync always - update \wr_pick_dly$1656$next $0\wr_pick_dly$1656$next[0:0]$2826 + update \wr_pick_dly$1686$next $0\wr_pick_dly$1686$next[0:0]$2832 end - attribute \src "libresoc.v:47604.3-47632.6" - process $proc$libresoc.v:47604$2828 + attribute \src "libresoc.v:47406.3-47434.6" + process $proc$libresoc.v:47406$2834 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$15[5:0]$2829 $1\fus_cu_rdmaskn_i$15[5:0]$2830 - attribute \src "libresoc.v:47605.5-47605.29" + assign $0\fus_cu_rdmaskn_i$15[5:0]$2835 $1\fus_cu_rdmaskn_i$15[5:0]$2836 + attribute \src "libresoc.v:47407.5-47407.29" switch \initial - attribute \src "libresoc.v:47605.9-47605.17" + attribute \src "libresoc.v:47407.9-47407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$15[5:0]$2830 $2\fus_cu_rdmaskn_i$15[5:0]$2831 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + assign $1\fus_cu_rdmaskn_i$15[5:0]$2836 $2\fus_cu_rdmaskn_i$15[5:0]$2837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 6'000000 + assign $2\fus_cu_rdmaskn_i$15[5:0]$2837 6'000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 6'000000 + assign $2\fus_cu_rdmaskn_i$15[5:0]$2837 6'000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 $3\fus_cu_rdmaskn_i$15[5:0]$2832 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + assign $2\fus_cu_rdmaskn_i$15[5:0]$2837 $3\fus_cu_rdmaskn_i$15[5:0]$2838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$15[5:0]$2832 \$250 + assign $3\fus_cu_rdmaskn_i$15[5:0]$2838 \$250 case - assign $3\fus_cu_rdmaskn_i$15[5:0]$2832 6'000000 + assign $3\fus_cu_rdmaskn_i$15[5:0]$2838 6'000000 end end case - assign $1\fus_cu_rdmaskn_i$15[5:0]$2830 6'000000 + assign $1\fus_cu_rdmaskn_i$15[5:0]$2836 6'000000 end sync always - update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[5:0]$2829 + update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[5:0]$2835 end - attribute \src "libresoc.v:47633.3-47641.6" - process $proc$libresoc.v:47633$2833 + attribute \src "libresoc.v:47435.3-47443.6" + process $proc$libresoc.v:47435$2839 assign { } { } assign { } { } - assign $0\wr_pick_dly$1672$next[0:0]$2834 $1\wr_pick_dly$1672$next[0:0]$2835 - attribute \src "libresoc.v:47634.5-47634.29" + assign $0\wr_pick_dly$1702$next[0:0]$2840 $1\wr_pick_dly$1702$next[0:0]$2841 + attribute \src "libresoc.v:47436.5-47436.29" switch \initial - attribute \src "libresoc.v:47634.9-47634.17" + attribute \src "libresoc.v:47436.9-47436.17" case 1'1 case end @@ -82956,54 +82776,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1672$next[0:0]$2835 1'0 + assign $1\wr_pick_dly$1702$next[0:0]$2841 1'0 case - assign $1\wr_pick_dly$1672$next[0:0]$2835 \wr_pick$1669 + assign $1\wr_pick_dly$1702$next[0:0]$2841 \wr_pick$1699 end sync always - update \wr_pick_dly$1672$next $0\wr_pick_dly$1672$next[0:0]$2834 + update \wr_pick_dly$1702$next $0\wr_pick_dly$1702$next[0:0]$2840 end - attribute \src "libresoc.v:47642.3-47650.6" - process $proc$libresoc.v:47642$2836 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1688$next[0:0]$2837 $1\wr_pick_dly$1688$next[0:0]$2838 - attribute \src "libresoc.v:47643.5-47643.29" - switch \initial - attribute \src "libresoc.v:47643.9-47643.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1688$next[0:0]$2838 1'0 - case - assign $1\wr_pick_dly$1688$next[0:0]$2838 \wr_pick$1685 - end - sync always - update \wr_pick_dly$1688$next $0\wr_pick_dly$1688$next[0:0]$2837 - end - attribute \src "libresoc.v:47651.3-47679.6" - process $proc$libresoc.v:47651$2839 + attribute \src "libresoc.v:47444.3-47472.6" + process $proc$libresoc.v:47444$2842 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47652.5-47652.29" + attribute \src "libresoc.v:47445.5-47445.29" switch \initial - attribute \src "libresoc.v:47652.9-47652.17" + attribute \src "libresoc.v:47445.9-47445.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__cia[63:0] $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83015,7 +82812,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__cia[63:0] $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83031,14 +82828,14 @@ module \core sync always update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] end - attribute \src "libresoc.v:47680.3-47688.6" - process $proc$libresoc.v:47680$2840 + attribute \src "libresoc.v:47473.3-47481.6" + process $proc$libresoc.v:47473$2843 assign { } { } assign { } { } - assign $0\wr_pick_dly$1704$next[0:0]$2841 $1\wr_pick_dly$1704$next[0:0]$2842 - attribute \src "libresoc.v:47681.5-47681.29" + assign $0\wr_pick_dly$1746$next[0:0]$2844 $1\wr_pick_dly$1746$next[0:0]$2845 + attribute \src "libresoc.v:47474.5-47474.29" switch \initial - attribute \src "libresoc.v:47681.9-47681.17" + attribute \src "libresoc.v:47474.9-47474.17" case 1'1 case end @@ -83047,31 +82844,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1704$next[0:0]$2842 1'0 + assign $1\wr_pick_dly$1746$next[0:0]$2845 1'0 case - assign $1\wr_pick_dly$1704$next[0:0]$2842 \wr_pick$1701 + assign $1\wr_pick_dly$1746$next[0:0]$2845 \wr_pick$1743 end sync always - update \wr_pick_dly$1704$next $0\wr_pick_dly$1704$next[0:0]$2841 + update \wr_pick_dly$1746$next $0\wr_pick_dly$1746$next[0:0]$2844 end - attribute \src "libresoc.v:47689.3-47717.6" - process $proc$libresoc.v:47689$2843 + attribute \src "libresoc.v:47482.3-47510.6" + process $proc$libresoc.v:47482$2846 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47690.5-47690.29" + attribute \src "libresoc.v:47483.5-47483.29" switch \initial - attribute \src "libresoc.v:47690.9-47690.17" + attribute \src "libresoc.v:47483.9-47483.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__insn_type[6:0] $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83083,7 +82880,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__insn_type[6:0] $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83099,14 +82896,14 @@ module \core sync always update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] end - attribute \src "libresoc.v:47718.3-47726.6" - process $proc$libresoc.v:47718$2844 + attribute \src "libresoc.v:47511.3-47519.6" + process $proc$libresoc.v:47511$2847 assign { } { } assign { } { } - assign $0\wr_pick_dly$1748$next[0:0]$2845 $1\wr_pick_dly$1748$next[0:0]$2846 - attribute \src "libresoc.v:47719.5-47719.29" + assign $0\wr_pick_dly$1762$next[0:0]$2848 $1\wr_pick_dly$1762$next[0:0]$2849 + attribute \src "libresoc.v:47512.5-47512.29" switch \initial - attribute \src "libresoc.v:47719.9-47719.17" + attribute \src "libresoc.v:47512.9-47512.17" case 1'1 case end @@ -83115,21 +82912,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1748$next[0:0]$2846 1'0 + assign $1\wr_pick_dly$1762$next[0:0]$2849 1'0 case - assign $1\wr_pick_dly$1748$next[0:0]$2846 \wr_pick$1745 + assign $1\wr_pick_dly$1762$next[0:0]$2849 \wr_pick$1759 end sync always - update \wr_pick_dly$1748$next $0\wr_pick_dly$1748$next[0:0]$2845 + update \wr_pick_dly$1762$next $0\wr_pick_dly$1762$next[0:0]$2848 end - attribute \src "libresoc.v:47727.3-47735.6" - process $proc$libresoc.v:47727$2847 + attribute \src "libresoc.v:47520.3-47528.6" + process $proc$libresoc.v:47520$2850 assign { } { } assign { } { } - assign $0\wr_pick_dly$1764$next[0:0]$2848 $1\wr_pick_dly$1764$next[0:0]$2849 - attribute \src "libresoc.v:47728.5-47728.29" + assign $0\wr_pick_dly$1786$next[0:0]$2851 $1\wr_pick_dly$1786$next[0:0]$2852 + attribute \src "libresoc.v:47521.5-47521.29" switch \initial - attribute \src "libresoc.v:47728.9-47728.17" + attribute \src "libresoc.v:47521.9-47521.17" case 1'1 case end @@ -83138,31 +82935,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1764$next[0:0]$2849 1'0 + assign $1\wr_pick_dly$1786$next[0:0]$2852 1'0 case - assign $1\wr_pick_dly$1764$next[0:0]$2849 \wr_pick$1761 + assign $1\wr_pick_dly$1786$next[0:0]$2852 \wr_pick$1783 end sync always - update \wr_pick_dly$1764$next $0\wr_pick_dly$1764$next[0:0]$2848 + update \wr_pick_dly$1786$next $0\wr_pick_dly$1786$next[0:0]$2851 end - attribute \src "libresoc.v:47736.3-47764.6" - process $proc$libresoc.v:47736$2850 + attribute \src "libresoc.v:47529.3-47557.6" + process $proc$libresoc.v:47529$2853 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__fn_unit[13:0] $1\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47737.5-47737.29" + attribute \src "libresoc.v:47530.5-47530.29" switch \initial - attribute \src "libresoc.v:47737.9-47737.17" + attribute \src "libresoc.v:47530.9-47530.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__fn_unit[13:0] $2\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83174,7 +82971,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] $3\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83190,14 +82987,14 @@ module \core sync always update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[13:0] end - attribute \src "libresoc.v:47765.3-47773.6" - process $proc$libresoc.v:47765$2851 + attribute \src "libresoc.v:47558.3-47566.6" + process $proc$libresoc.v:47558$2854 assign { } { } assign { } { } - assign $0\wr_pick_dly$1788$next[0:0]$2852 $1\wr_pick_dly$1788$next[0:0]$2853 - attribute \src "libresoc.v:47766.5-47766.29" + assign $0\wr_pick_dly$1806$next[0:0]$2855 $1\wr_pick_dly$1806$next[0:0]$2856 + attribute \src "libresoc.v:47559.5-47559.29" switch \initial - attribute \src "libresoc.v:47766.9-47766.17" + attribute \src "libresoc.v:47559.9-47559.17" case 1'1 case end @@ -83206,31 +83003,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1788$next[0:0]$2853 1'0 + assign $1\wr_pick_dly$1806$next[0:0]$2856 1'0 case - assign $1\wr_pick_dly$1788$next[0:0]$2853 \wr_pick$1785 + assign $1\wr_pick_dly$1806$next[0:0]$2856 \wr_pick$1803 end sync always - update \wr_pick_dly$1788$next $0\wr_pick_dly$1788$next[0:0]$2852 + update \wr_pick_dly$1806$next $0\wr_pick_dly$1806$next[0:0]$2855 end - attribute \src "libresoc.v:47774.3-47802.6" - process $proc$libresoc.v:47774$2854 + attribute \src "libresoc.v:47567.3-47595.6" + process $proc$libresoc.v:47567$2857 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47775.5-47775.29" + attribute \src "libresoc.v:47568.5-47568.29" switch \initial - attribute \src "libresoc.v:47775.9-47775.17" + attribute \src "libresoc.v:47568.9-47568.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__insn[31:0] $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83242,7 +83039,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__insn[31:0] $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83258,44 +83055,21 @@ module \core sync always update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] end - attribute \src "libresoc.v:47803.3-47811.6" - process $proc$libresoc.v:47803$2855 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1808$next[0:0]$2856 $1\wr_pick_dly$1808$next[0:0]$2857 - attribute \src "libresoc.v:47804.5-47804.29" - switch \initial - attribute \src "libresoc.v:47804.9-47804.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1808$next[0:0]$2857 1'0 - case - assign $1\wr_pick_dly$1808$next[0:0]$2857 \wr_pick$1805 - end - sync always - update \wr_pick_dly$1808$next $0\wr_pick_dly$1808$next[0:0]$2856 - end - attribute \src "libresoc.v:47812.3-47841.6" - process $proc$libresoc.v:47812$2858 + attribute \src "libresoc.v:47596.3-47625.6" + process $proc$libresoc.v:47596$2858 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47813.5-47813.29" + attribute \src "libresoc.v:47597.5-47597.29" switch \initial - attribute \src "libresoc.v:47813.9-47813.17" + attribute \src "libresoc.v:47597.9-47597.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83303,7 +83077,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] $2\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83319,7 +83093,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83339,24 +83113,24 @@ module \core update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] end - attribute \src "libresoc.v:47842.3-47870.6" - process $proc$libresoc.v:47842$2859 + attribute \src "libresoc.v:47626.3-47654.6" + process $proc$libresoc.v:47626$2859 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47843.5-47843.29" + attribute \src "libresoc.v:47627.5-47627.29" switch \initial - attribute \src "libresoc.v:47843.9-47843.17" + attribute \src "libresoc.v:47627.9-47627.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83368,7 +83142,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83384,24 +83158,24 @@ module \core sync always update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] end - attribute \src "libresoc.v:47871.3-47899.6" - process $proc$libresoc.v:47871$2860 + attribute \src "libresoc.v:47655.3-47683.6" + process $proc$libresoc.v:47655$2860 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47872.5-47872.29" + attribute \src "libresoc.v:47656.5-47656.29" switch \initial - attribute \src "libresoc.v:47872.9-47872.17" + attribute \src "libresoc.v:47656.9-47656.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83413,7 +83187,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83429,24 +83203,24 @@ module \core sync always update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] end - attribute \src "libresoc.v:47900.3-47928.6" - process $proc$libresoc.v:47900$2861 + attribute \src "libresoc.v:47684.3-47712.6" + process $proc$libresoc.v:47684$2861 assign { } { } assign { } { } assign $0\fus_cu_issue_i$16[0:0]$2862 $1\fus_cu_issue_i$16[0:0]$2863 - attribute \src "libresoc.v:47901.5-47901.29" + attribute \src "libresoc.v:47685.5-47685.29" switch \initial - attribute \src "libresoc.v:47901.9-47901.17" + attribute \src "libresoc.v:47685.9-47685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$16[0:0]$2863 $2\fus_cu_issue_i$16[0:0]$2864 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83458,7 +83232,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$16[0:0]$2864 $3\fus_cu_issue_i$16[0:0]$2865 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83474,24 +83248,24 @@ module \core sync always update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2862 end - attribute \src "libresoc.v:47929.3-47957.6" - process $proc$libresoc.v:47929$2866 + attribute \src "libresoc.v:47713.3-47741.6" + process $proc$libresoc.v:47713$2866 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$18[2:0]$2867 $1\fus_cu_rdmaskn_i$18[2:0]$2868 - attribute \src "libresoc.v:47930.5-47930.29" + attribute \src "libresoc.v:47714.5-47714.29" switch \initial - attribute \src "libresoc.v:47930.9-47930.17" + attribute \src "libresoc.v:47714.9-47714.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$18[2:0]$2868 $2\fus_cu_rdmaskn_i$18[2:0]$2869 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83503,7 +83277,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 $3\fus_cu_rdmaskn_i$18[2:0]$2870 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83519,24 +83293,24 @@ module \core sync always update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[2:0]$2867 end - attribute \src "libresoc.v:47958.3-47986.6" - process $proc$libresoc.v:47958$2871 + attribute \src "libresoc.v:47742.3-47770.6" + process $proc$libresoc.v:47742$2871 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47959.5-47959.29" + attribute \src "libresoc.v:47743.5-47743.29" switch \initial - attribute \src "libresoc.v:47959.9-47959.17" + attribute \src "libresoc.v:47743.9-47743.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83548,7 +83322,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83564,24 +83338,24 @@ module \core sync always update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] end - attribute \src "libresoc.v:47987.3-48015.6" - process $proc$libresoc.v:47987$2872 + attribute \src "libresoc.v:47771.3-47799.6" + process $proc$libresoc.v:47771$2872 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__fn_unit[13:0] $1\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:47988.5-47988.29" + attribute \src "libresoc.v:47772.5-47772.29" switch \initial - attribute \src "libresoc.v:47988.9-47988.17" + attribute \src "libresoc.v:47772.9-47772.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__fn_unit[13:0] $2\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83593,7 +83367,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] $3\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83609,24 +83383,24 @@ module \core sync always update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[13:0] end - attribute \src "libresoc.v:48016.3-48044.6" - process $proc$libresoc.v:48016$2873 + attribute \src "libresoc.v:47800.3-47828.6" + process $proc$libresoc.v:47800$2873 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:48017.5-48017.29" + attribute \src "libresoc.v:47801.5-47801.29" switch \initial - attribute \src "libresoc.v:48017.9-48017.17" + attribute \src "libresoc.v:47801.9-47801.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83638,7 +83412,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83654,24 +83428,24 @@ module \core sync always update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] end - attribute \src "libresoc.v:48045.3-48073.6" - process $proc$libresoc.v:48045$2874 + attribute \src "libresoc.v:47829.3-47857.6" + process $proc$libresoc.v:47829$2874 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48046.5-48046.29" + attribute \src "libresoc.v:47830.5-47830.29" switch \initial - attribute \src "libresoc.v:48046.9-48046.17" + attribute \src "libresoc.v:47830.9-47830.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83683,7 +83457,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83699,24 +83473,24 @@ module \core sync always update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] end - attribute \src "libresoc.v:48074.3-48102.6" - process $proc$libresoc.v:48074$2875 + attribute \src "libresoc.v:47858.3-47886.6" + process $proc$libresoc.v:47858$2875 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:48075.5-48075.29" + attribute \src "libresoc.v:47859.5-47859.29" switch \initial - attribute \src "libresoc.v:48075.9-48075.17" + attribute \src "libresoc.v:47859.9-47859.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83728,7 +83502,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83744,24 +83518,24 @@ module \core sync always update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] end - attribute \src "libresoc.v:48103.3-48131.6" - process $proc$libresoc.v:48103$2876 + attribute \src "libresoc.v:47887.3-47915.6" + process $proc$libresoc.v:47887$2876 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48104.5-48104.29" + attribute \src "libresoc.v:47888.5-47888.29" switch \initial - attribute \src "libresoc.v:48104.9-48104.17" + attribute \src "libresoc.v:47888.9-47888.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83773,7 +83547,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83789,24 +83563,24 @@ module \core sync always update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] end - attribute \src "libresoc.v:48132.3-48160.6" - process $proc$libresoc.v:48132$2877 + attribute \src "libresoc.v:47916.3-47944.6" + process $proc$libresoc.v:47916$2877 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__traptype[7:0] $1\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:48133.5-48133.29" + attribute \src "libresoc.v:47917.5-47917.29" switch \initial - attribute \src "libresoc.v:48133.9-48133.17" + attribute \src "libresoc.v:47917.9-47917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__traptype[7:0] $2\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83818,7 +83592,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__traptype[7:0] $3\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83834,24 +83608,24 @@ module \core sync always update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[7:0] end - attribute \src "libresoc.v:48161.3-48189.6" - process $proc$libresoc.v:48161$2878 + attribute \src "libresoc.v:47945.3-47973.6" + process $proc$libresoc.v:47945$2878 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48162.5-48162.29" + attribute \src "libresoc.v:47946.5-47946.29" switch \initial - attribute \src "libresoc.v:48162.9-48162.17" + attribute \src "libresoc.v:47946.9-47946.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83863,7 +83637,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83879,24 +83653,24 @@ module \core sync always update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] end - attribute \src "libresoc.v:48190.3-48218.6" - process $proc$libresoc.v:48190$2879 + attribute \src "libresoc.v:47974.3-48002.6" + process $proc$libresoc.v:47974$2879 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__ldst_exc[7:0] $1\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48191.5-48191.29" + attribute \src "libresoc.v:47975.5-47975.29" switch \initial - attribute \src "libresoc.v:48191.9-48191.17" + attribute \src "libresoc.v:47975.9-47975.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] $2\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83908,7 +83682,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] $3\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83924,24 +83698,24 @@ module \core sync always update \fus_oper_i_alu_trap0__ldst_exc $0\fus_oper_i_alu_trap0__ldst_exc[7:0] end - attribute \src "libresoc.v:48219.3-48247.6" - process $proc$libresoc.v:48219$2880 + attribute \src "libresoc.v:48003.3-48031.6" + process $proc$libresoc.v:48003$2880 assign { } { } assign { } { } assign $0\fus_cu_issue_i$19[0:0]$2881 $1\fus_cu_issue_i$19[0:0]$2882 - attribute \src "libresoc.v:48220.5-48220.29" + attribute \src "libresoc.v:48004.5-48004.29" switch \initial - attribute \src "libresoc.v:48220.9-48220.17" + attribute \src "libresoc.v:48004.9-48004.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$19[0:0]$2882 $2\fus_cu_issue_i$19[0:0]$2883 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83953,7 +83727,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i$19[0:0]$2883 $3\fus_cu_issue_i$19[0:0]$2884 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83969,24 +83743,24 @@ module \core sync always update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2881 end - attribute \src "libresoc.v:48248.3-48276.6" - process $proc$libresoc.v:48248$2885 + attribute \src "libresoc.v:48032.3-48060.6" + process $proc$libresoc.v:48032$2885 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$21[3:0]$2886 $1\fus_cu_rdmaskn_i$21[3:0]$2887 - attribute \src "libresoc.v:48249.5-48249.29" + attribute \src "libresoc.v:48033.5-48033.29" switch \initial - attribute \src "libresoc.v:48249.9-48249.17" + attribute \src "libresoc.v:48033.9-48033.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$21[3:0]$2887 $2\fus_cu_rdmaskn_i$21[3:0]$2888 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83998,7 +83772,7 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 $3\fus_cu_rdmaskn_i$21[3:0]$2889 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84014,24 +83788,24 @@ module \core sync always update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[3:0]$2886 end - attribute \src "libresoc.v:48277.3-48305.6" - process $proc$libresoc.v:48277$2890 + attribute \src "libresoc.v:48061.3-48089.6" + process $proc$libresoc.v:48061$2890 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48278.5-48278.29" + attribute \src "libresoc.v:48062.5-48062.29" switch \initial - attribute \src "libresoc.v:48278.9-48278.17" + attribute \src "libresoc.v:48062.9-48062.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__insn_type[6:0] $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84043,7 +83817,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__insn_type[6:0] $3\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84059,24 +83833,24 @@ module \core sync always update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] end - attribute \src "libresoc.v:48306.3-48334.6" - process $proc$libresoc.v:48306$2891 + attribute \src "libresoc.v:48090.3-48118.6" + process $proc$libresoc.v:48090$2891 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__fn_unit[13:0] $1\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48307.5-48307.29" + attribute \src "libresoc.v:48091.5-48091.29" switch \initial - attribute \src "libresoc.v:48307.9-48307.17" + attribute \src "libresoc.v:48091.9-48091.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__fn_unit[13:0] $2\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84088,7 +83862,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] $3\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84104,21 +83878,21 @@ module \core sync always update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[13:0] end - attribute \src "libresoc.v:48335.3-48364.6" - process $proc$libresoc.v:48335$2892 + attribute \src "libresoc.v:48119.3-48148.6" + process $proc$libresoc.v:48119$2892 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48336.5-48336.29" + attribute \src "libresoc.v:48120.5-48120.29" switch \initial - attribute \src "libresoc.v:48336.9-48336.17" + attribute \src "libresoc.v:48120.9-48120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84126,7 +83900,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] $2\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84142,7 +83916,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84162,21 +83936,21 @@ module \core update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] end - attribute \src "libresoc.v:48365.3-48394.6" - process $proc$libresoc.v:48365$2893 + attribute \src "libresoc.v:48149.3-48178.6" + process $proc$libresoc.v:48149$2893 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48366.5-48366.29" + attribute \src "libresoc.v:48150.5-48150.29" switch \initial - attribute \src "libresoc.v:48366.9-48366.17" + attribute \src "libresoc.v:48150.9-48150.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84184,7 +83958,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] $2\fus_oper_i_alu_logical0__rc__ok[0:0] assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84200,7 +83974,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__ok[0:0] assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84220,21 +83994,21 @@ module \core update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] end - attribute \src "libresoc.v:48395.3-48424.6" - process $proc$libresoc.v:48395$2894 + attribute \src "libresoc.v:48179.3-48208.6" + process $proc$libresoc.v:48179$2894 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:48396.5-48396.29" + attribute \src "libresoc.v:48180.5-48180.29" switch \initial - attribute \src "libresoc.v:48396.9-48396.17" + attribute \src "libresoc.v:48180.9-48180.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84242,7 +84016,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] $2\fus_oper_i_alu_logical0__oe__oe[0:0] assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84258,7 +84032,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84278,24 +84052,24 @@ module \core update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] end - attribute \src "libresoc.v:48425.3-48453.6" - process $proc$libresoc.v:48425$2895 + attribute \src "libresoc.v:48209.3-48237.6" + process $proc$libresoc.v:48209$2895 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48426.5-48426.29" + attribute \src "libresoc.v:48210.5-48210.29" switch \initial - attribute \src "libresoc.v:48426.9-48426.17" + attribute \src "libresoc.v:48210.9-48210.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__invert_in[0:0] $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84307,7 +84081,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__invert_in[0:0] $3\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84323,24 +84097,24 @@ module \core sync always update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] end - attribute \src "libresoc.v:48454.3-48482.6" - process $proc$libresoc.v:48454$2896 + attribute \src "libresoc.v:48238.3-48266.6" + process $proc$libresoc.v:48238$2896 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:48455.5-48455.29" + attribute \src "libresoc.v:48239.5-48239.29" switch \initial - attribute \src "libresoc.v:48455.9-48455.17" + attribute \src "libresoc.v:48239.9-48239.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__zero_a[0:0] $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84352,7 +84126,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__zero_a[0:0] $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84368,24 +84142,24 @@ module \core sync always update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] end - attribute \src "libresoc.v:48483.3-48511.6" - process $proc$libresoc.v:48483$2897 + attribute \src "libresoc.v:48267.3-48295.6" + process $proc$libresoc.v:48267$2897 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:48484.5-48484.29" + attribute \src "libresoc.v:48268.5-48268.29" switch \initial - attribute \src "libresoc.v:48484.9-48484.17" + attribute \src "libresoc.v:48268.9-48268.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__input_carry[1:0] $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84397,7 +84171,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__input_carry[1:0] $3\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84413,24 +84187,24 @@ module \core sync always update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] end - attribute \src "libresoc.v:48512.3-48540.6" - process $proc$libresoc.v:48512$2898 + attribute \src "libresoc.v:48296.3-48324.6" + process $proc$libresoc.v:48296$2898 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:48513.5-48513.29" + attribute \src "libresoc.v:48297.5-48297.29" switch \initial - attribute \src "libresoc.v:48513.9-48513.17" + attribute \src "libresoc.v:48297.9-48297.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__invert_out[0:0] $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84442,7 +84216,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__invert_out[0:0] $3\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84458,24 +84232,24 @@ module \core sync always update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] end - attribute \src "libresoc.v:48541.3-48569.6" - process $proc$libresoc.v:48541$2899 + attribute \src "libresoc.v:48325.3-48353.6" + process $proc$libresoc.v:48325$2899 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48542.5-48542.29" + attribute \src "libresoc.v:48326.5-48326.29" switch \initial - attribute \src "libresoc.v:48542.9-48542.17" + attribute \src "libresoc.v:48326.9-48326.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -84487,7 +84261,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -84503,1255 +84277,1247 @@ module \core sync always update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] end - connect \$1000 $and$libresoc.v:42103$1506_Y - connect \$1003 $ternary$libresoc.v:42104$1507_Y - connect \$1005 $and$libresoc.v:42105$1508_Y - connect \$1008 $and$libresoc.v:42106$1509_Y - connect \$1012 $not$libresoc.v:42107$1510_Y - connect \$1014 $and$libresoc.v:42108$1511_Y - connect \$1021 $and$libresoc.v:42109$1512_Y - connect \$1024 $ternary$libresoc.v:42110$1513_Y - connect \$1026 $and$libresoc.v:42111$1514_Y - connect \$1029 $and$libresoc.v:42112$1515_Y - connect \$1033 $not$libresoc.v:42113$1516_Y - connect \$1035 $and$libresoc.v:42114$1517_Y - connect \$1039 $and$libresoc.v:42115$1518_Y - connect \$1042 $ternary$libresoc.v:42116$1519_Y - connect \$1044 $and$libresoc.v:42117$1520_Y - connect \$1047 $and$libresoc.v:42118$1521_Y - connect \$1051 $not$libresoc.v:42119$1522_Y - connect \$1053 $and$libresoc.v:42120$1523_Y - connect \$1061 $and$libresoc.v:42121$1524_Y - connect \$1064 $ternary$libresoc.v:42122$1525_Y - connect \$1066 $and$libresoc.v:42123$1526_Y - connect \$1069 $and$libresoc.v:42124$1527_Y - connect \$1073 $not$libresoc.v:42125$1528_Y - connect \$1075 $and$libresoc.v:42126$1529_Y - connect \$1081 $and$libresoc.v:42127$1530_Y - connect \$1084 $ternary$libresoc.v:42128$1531_Y - connect \$1086 $and$libresoc.v:42129$1532_Y - connect \$1089 $and$libresoc.v:42130$1533_Y - connect \$1093 $not$libresoc.v:42131$1534_Y - connect \$1095 $and$libresoc.v:42132$1535_Y - connect \$1101 $and$libresoc.v:42133$1536_Y - connect \$1104 $ternary$libresoc.v:42134$1537_Y - connect \$1106 $and$libresoc.v:42135$1538_Y - connect \$1109 $and$libresoc.v:42136$1539_Y - connect \$1113 $not$libresoc.v:42137$1540_Y - connect \$1115 $and$libresoc.v:42138$1541_Y - connect \$1120 $and$libresoc.v:42139$1542_Y - connect \$1123 $ternary$libresoc.v:42140$1543_Y - connect \$1125 $and$libresoc.v:42141$1544_Y - connect \$1128 $and$libresoc.v:42142$1545_Y - connect \$1132 $not$libresoc.v:42143$1546_Y - connect \$1134 $and$libresoc.v:42144$1547_Y - connect \$1138 $and$libresoc.v:42145$1548_Y - connect \$1141 $ternary$libresoc.v:42146$1549_Y - connect \$1143 $and$libresoc.v:42147$1550_Y - connect \$1146 $and$libresoc.v:42148$1551_Y - connect \$1149 $not$libresoc.v:42149$1552_Y - connect \$1151 $and$libresoc.v:42150$1553_Y - connect \$1154 $and$libresoc.v:42151$1554_Y - connect \$1157 $ternary$libresoc.v:42152$1555_Y - connect \$1160 $or$libresoc.v:42153$1556_Y - connect \$1162 $or$libresoc.v:42154$1557_Y - connect \$1164 $or$libresoc.v:42155$1558_Y - connect \$1166 $or$libresoc.v:42156$1559_Y - connect \$1168 $or$libresoc.v:42157$1560_Y - connect \$1170 $or$libresoc.v:42158$1561_Y - connect \$1172 $or$libresoc.v:42159$1562_Y - connect \$1174 $or$libresoc.v:42160$1563_Y - connect \$1176 $or$libresoc.v:42161$1564_Y - connect \$1179 $or$libresoc.v:42162$1565_Y - connect \$1181 $or$libresoc.v:42163$1566_Y - connect \$1183 $or$libresoc.v:42164$1567_Y - connect \$1185 $or$libresoc.v:42165$1568_Y - connect \$1187 $or$libresoc.v:42166$1569_Y - connect \$1189 $or$libresoc.v:42167$1570_Y - connect \$1191 $or$libresoc.v:42168$1571_Y - connect \$1193 $or$libresoc.v:42169$1572_Y - connect \$1195 $or$libresoc.v:42170$1573_Y - connect \$1197 $or$libresoc.v:42171$1574_Y - connect \$1199 $or$libresoc.v:42172$1575_Y - connect \$1201 $or$libresoc.v:42173$1576_Y - connect \$1203 $or$libresoc.v:42174$1577_Y - connect \$1205 $or$libresoc.v:42175$1578_Y - connect \$1207 $or$libresoc.v:42176$1579_Y - connect \$1209 $or$libresoc.v:42177$1580_Y - connect \$1211 $or$libresoc.v:42178$1581_Y - connect \$1213 $or$libresoc.v:42179$1582_Y - connect \$1215 $and$libresoc.v:42180$1583_Y - connect \$1217 $and$libresoc.v:42181$1584_Y - connect \$1220 $and$libresoc.v:42182$1585_Y - connect \$1223 $not$libresoc.v:42183$1586_Y - connect \$1225 $and$libresoc.v:42184$1587_Y - connect \$1228 $and$libresoc.v:42185$1588_Y - connect \$1231 $ternary$libresoc.v:42186$1589_Y - connect \$1233 $and$libresoc.v:42187$1590_Y - connect \$1235 $and$libresoc.v:42188$1591_Y - connect \$1237 $and$libresoc.v:42189$1592_Y - connect \$1239 $and$libresoc.v:42190$1593_Y - connect \$1241 $and$libresoc.v:42191$1594_Y - connect \$1243 $and$libresoc.v:42192$1595_Y - connect \$1245 $and$libresoc.v:42193$1596_Y - connect \$1248 $and$libresoc.v:42194$1597_Y - connect \$1251 $not$libresoc.v:42195$1598_Y - connect \$1253 $and$libresoc.v:42196$1599_Y - connect \$1256 $and$libresoc.v:42197$1600_Y - connect \$1259 $sub$libresoc.v:42198$1601_Y - connect \$1261 $sshl$libresoc.v:42199$1602_Y - connect \$1263 $ternary$libresoc.v:42200$1603_Y - connect \$1265 $and$libresoc.v:42201$1604_Y - connect \$1268 $and$libresoc.v:42202$1605_Y - connect \$1271 $not$libresoc.v:42203$1606_Y - connect \$1273 $and$libresoc.v:42204$1607_Y - connect \$1276 $and$libresoc.v:42205$1608_Y - connect \$1279 $sub$libresoc.v:42206$1609_Y - connect \$1281 $sshl$libresoc.v:42207$1610_Y - connect \$1283 $ternary$libresoc.v:42208$1611_Y - connect \$1285 $and$libresoc.v:42209$1612_Y - connect \$1288 $and$libresoc.v:42210$1613_Y - connect \$1291 $not$libresoc.v:42211$1614_Y - connect \$1293 $and$libresoc.v:42212$1615_Y - connect \$1296 $and$libresoc.v:42213$1616_Y - connect \$1299 $sub$libresoc.v:42214$1617_Y - connect \$1301 $sshl$libresoc.v:42215$1618_Y - connect \$1303 $ternary$libresoc.v:42216$1619_Y - connect \$1305 $and$libresoc.v:42217$1620_Y - connect \$1308 $and$libresoc.v:42218$1621_Y - connect \$1311 $not$libresoc.v:42219$1622_Y - connect \$1313 $and$libresoc.v:42220$1623_Y - connect \$1316 $and$libresoc.v:42221$1624_Y - connect \$1319 $sub$libresoc.v:42222$1625_Y - connect \$1321 $sshl$libresoc.v:42223$1626_Y - connect \$1323 $ternary$libresoc.v:42224$1627_Y - connect \$1325 $and$libresoc.v:42225$1628_Y - connect \$1328 $and$libresoc.v:42226$1629_Y - connect \$1331 $not$libresoc.v:42227$1630_Y - connect \$1333 $and$libresoc.v:42228$1631_Y - connect \$1336 $and$libresoc.v:42229$1632_Y - connect \$1339 $sub$libresoc.v:42230$1633_Y - connect \$1341 $sshl$libresoc.v:42231$1634_Y - connect \$1343 $ternary$libresoc.v:42232$1635_Y - connect \$1345 $and$libresoc.v:42233$1636_Y - connect \$1348 $and$libresoc.v:42234$1637_Y - connect \$1351 $not$libresoc.v:42235$1638_Y - connect \$1353 $and$libresoc.v:42236$1639_Y - connect \$1356 $and$libresoc.v:42237$1640_Y - connect \$1359 $sub$libresoc.v:42238$1641_Y - connect \$1361 $sshl$libresoc.v:42239$1642_Y - connect \$1363 $ternary$libresoc.v:42240$1643_Y - connect \$1365 $or$libresoc.v:42241$1644_Y - connect \$1367 $or$libresoc.v:42242$1645_Y - connect \$1369 $or$libresoc.v:42243$1646_Y - connect \$1371 $or$libresoc.v:42244$1647_Y - connect \$1373 $or$libresoc.v:42245$1648_Y - connect \$1376 $or$libresoc.v:42246$1649_Y - connect \$1378 $or$libresoc.v:42247$1650_Y - connect \$1380 $or$libresoc.v:42248$1651_Y - connect \$1382 $or$libresoc.v:42249$1652_Y - connect \$1384 $or$libresoc.v:42250$1653_Y - connect \$1386 $and$libresoc.v:42251$1654_Y - connect \$1388 $and$libresoc.v:42252$1655_Y - connect \$1390 $and$libresoc.v:42253$1656_Y - connect \$1392 $and$libresoc.v:42254$1657_Y - connect \$1395 $and$libresoc.v:42255$1658_Y - connect \$1398 $not$libresoc.v:42256$1659_Y - connect \$1400 $and$libresoc.v:42257$1660_Y - connect \$1403 $and$libresoc.v:42258$1661_Y - connect \$1406 $ternary$libresoc.v:42259$1662_Y - connect \$1408 $and$libresoc.v:42260$1663_Y - connect \$1411 $and$libresoc.v:42261$1664_Y - connect \$1414 $not$libresoc.v:42262$1665_Y - connect \$1416 $and$libresoc.v:42263$1666_Y - connect \$1419 $and$libresoc.v:42264$1667_Y - connect \$1422 $ternary$libresoc.v:42265$1668_Y - connect \$1424 $and$libresoc.v:42266$1669_Y - connect \$1427 $and$libresoc.v:42267$1670_Y - connect \$1430 $not$libresoc.v:42268$1671_Y - connect \$1432 $and$libresoc.v:42269$1672_Y - connect \$1435 $and$libresoc.v:42270$1673_Y - connect \$1438 $ternary$libresoc.v:42271$1674_Y - connect \$1440 $or$libresoc.v:42272$1675_Y - connect \$1442 $or$libresoc.v:42273$1676_Y - connect \$1445 $or$libresoc.v:42274$1677_Y - connect \$1447 $or$libresoc.v:42275$1678_Y - connect \$1444 $pos$libresoc.v:42276$1680_Y - connect \$1450 $and$libresoc.v:42277$1681_Y - connect \$1452 $and$libresoc.v:42278$1682_Y - connect \$1454 $and$libresoc.v:42279$1683_Y - connect \$1456 $and$libresoc.v:42280$1684_Y - connect \$1458 $and$libresoc.v:42281$1685_Y - connect \$1461 $and$libresoc.v:42282$1686_Y - connect \$1464 $not$libresoc.v:42283$1687_Y - connect \$1466 $and$libresoc.v:42284$1688_Y - connect \$1469 $and$libresoc.v:42285$1689_Y - connect \$1472 $ternary$libresoc.v:42286$1690_Y - connect \$1474 $and$libresoc.v:42287$1691_Y - connect \$1477 $and$libresoc.v:42288$1692_Y - connect \$1480 $not$libresoc.v:42289$1693_Y - connect \$1482 $and$libresoc.v:42290$1694_Y - connect \$1485 $and$libresoc.v:42291$1695_Y - connect \$1488 $ternary$libresoc.v:42292$1696_Y - connect \$1490 $and$libresoc.v:42293$1697_Y - connect \$1493 $and$libresoc.v:42294$1698_Y - connect \$1496 $not$libresoc.v:42295$1699_Y - connect \$1498 $and$libresoc.v:42296$1700_Y - connect \$1501 $and$libresoc.v:42297$1701_Y - connect \$1504 $ternary$libresoc.v:42298$1702_Y - connect \$1506 $and$libresoc.v:42299$1703_Y - connect \$1509 $and$libresoc.v:42300$1704_Y - connect \$1512 $not$libresoc.v:42301$1705_Y - connect \$1514 $and$libresoc.v:42302$1706_Y - connect \$1517 $and$libresoc.v:42303$1707_Y - connect \$1520 $ternary$libresoc.v:42304$1708_Y - connect \$1522 $or$libresoc.v:42305$1709_Y - connect \$1524 $or$libresoc.v:42306$1710_Y - connect \$1526 $or$libresoc.v:42307$1711_Y - connect \$1528 $or$libresoc.v:42308$1712_Y - connect \$1530 $or$libresoc.v:42309$1713_Y - connect \$1532 $or$libresoc.v:42310$1714_Y - connect \$1534 $and$libresoc.v:42311$1715_Y - connect \$1536 $and$libresoc.v:42312$1716_Y - connect \$1538 $and$libresoc.v:42313$1717_Y - connect \$1540 $and$libresoc.v:42314$1718_Y - connect \$1542 $and$libresoc.v:42315$1719_Y - connect \$1545 $and$libresoc.v:42316$1720_Y - connect \$1548 $not$libresoc.v:42317$1721_Y - connect \$1550 $and$libresoc.v:42318$1722_Y - connect \$1553 $and$libresoc.v:42319$1723_Y - connect \$1556 $ternary$libresoc.v:42320$1724_Y - connect \$1558 $and$libresoc.v:42321$1725_Y - connect \$1561 $and$libresoc.v:42322$1726_Y - connect \$1564 $not$libresoc.v:42323$1727_Y - connect \$1566 $and$libresoc.v:42324$1728_Y - connect \$1569 $and$libresoc.v:42325$1729_Y - connect \$1572 $ternary$libresoc.v:42326$1730_Y - connect \$1574 $and$libresoc.v:42327$1731_Y - connect \$1577 $and$libresoc.v:42328$1732_Y - connect \$1580 $not$libresoc.v:42329$1733_Y - connect \$1582 $and$libresoc.v:42330$1734_Y - connect \$1585 $and$libresoc.v:42331$1735_Y - connect \$1588 $ternary$libresoc.v:42332$1736_Y - connect \$1590 $and$libresoc.v:42333$1737_Y - connect \$1593 $and$libresoc.v:42334$1738_Y - connect \$1596 $not$libresoc.v:42335$1739_Y - connect \$1598 $and$libresoc.v:42336$1740_Y - connect \$1601 $and$libresoc.v:42337$1741_Y - connect \$1604 $ternary$libresoc.v:42338$1742_Y - connect \$1607 $or$libresoc.v:42339$1743_Y - connect \$1609 $or$libresoc.v:42340$1744_Y - connect \$1611 $or$libresoc.v:42341$1745_Y - connect \$1606 $pos$libresoc.v:42342$1747_Y - connect \$1615 $or$libresoc.v:42343$1748_Y - connect \$1617 $or$libresoc.v:42344$1749_Y - connect \$1619 $or$libresoc.v:42345$1750_Y - connect \$1614 $pos$libresoc.v:42346$1752_Y - connect \$1622 $and$libresoc.v:42347$1753_Y - connect \$1624 $and$libresoc.v:42348$1754_Y - connect \$1626 $and$libresoc.v:42349$1755_Y - connect \$1628 $and$libresoc.v:42350$1756_Y - connect \$1630 $and$libresoc.v:42351$1757_Y - connect \$1632 $and$libresoc.v:42352$1758_Y - connect \$1635 $and$libresoc.v:42353$1759_Y - connect \$1639 $not$libresoc.v:42354$1760_Y - connect \$1641 $and$libresoc.v:42355$1761_Y - connect \$1646 $and$libresoc.v:42356$1762_Y - connect \$1649 $ternary$libresoc.v:42357$1763_Y - connect \$1651 $and$libresoc.v:42358$1764_Y - connect \$1654 $and$libresoc.v:42359$1765_Y - connect \$1657 $not$libresoc.v:42360$1766_Y - connect \$1659 $and$libresoc.v:42361$1767_Y - connect \$1662 $and$libresoc.v:42362$1768_Y - connect \$1665 $ternary$libresoc.v:42363$1769_Y - connect \$1667 $and$libresoc.v:42364$1770_Y - connect \$1670 $and$libresoc.v:42365$1771_Y - connect \$1673 $not$libresoc.v:42366$1772_Y - connect \$1675 $and$libresoc.v:42367$1773_Y - connect \$1678 $and$libresoc.v:42368$1774_Y - connect \$1681 $ternary$libresoc.v:42369$1775_Y - connect \$1683 $and$libresoc.v:42370$1776_Y - connect \$1686 $and$libresoc.v:42371$1777_Y - connect \$1689 $not$libresoc.v:42372$1778_Y - connect \$1691 $and$libresoc.v:42373$1779_Y - connect \$1694 $and$libresoc.v:42374$1780_Y - connect \$1697 $ternary$libresoc.v:42375$1781_Y - connect \$1699 $and$libresoc.v:42376$1782_Y - connect \$1702 $and$libresoc.v:42377$1783_Y - connect \$1705 $not$libresoc.v:42378$1784_Y - connect \$1707 $and$libresoc.v:42379$1785_Y - connect \$1710 $and$libresoc.v:42380$1786_Y - connect \$1713 $ternary$libresoc.v:42381$1787_Y - connect \$1715 $or$libresoc.v:42382$1788_Y - connect \$1717 $or$libresoc.v:42383$1789_Y - connect \$1719 $or$libresoc.v:42384$1790_Y - connect \$1721 $or$libresoc.v:42385$1791_Y - connect \$1723 $or$libresoc.v:42386$1792_Y - connect \$1725 $or$libresoc.v:42387$1793_Y - connect \$1727 $or$libresoc.v:42388$1794_Y - connect \$1729 $or$libresoc.v:42389$1795_Y - connect \$1731 $or$libresoc.v:42390$1796_Y - connect \$1733 $or$libresoc.v:42391$1797_Y - connect \$1735 $or$libresoc.v:42392$1798_Y - connect \$1737 $or$libresoc.v:42393$1799_Y - connect \$1739 $and$libresoc.v:42394$1800_Y - connect \$1741 $and$libresoc.v:42395$1801_Y - connect \$1743 $and$libresoc.v:42396$1802_Y - connect \$1746 $and$libresoc.v:42397$1803_Y - connect \$1749 $not$libresoc.v:42398$1804_Y - connect \$1751 $and$libresoc.v:42399$1805_Y - connect \$1754 $and$libresoc.v:42400$1806_Y - connect \$1757 $ternary$libresoc.v:42401$1807_Y - connect \$1759 $and$libresoc.v:42402$1808_Y - connect \$1762 $and$libresoc.v:42403$1809_Y - connect \$1765 $not$libresoc.v:42404$1810_Y - connect \$1767 $and$libresoc.v:42405$1811_Y - connect \$1770 $and$libresoc.v:42406$1812_Y - connect \$1773 $ternary$libresoc.v:42407$1813_Y - connect \$1775 $or$libresoc.v:42408$1814_Y - connect \$1778 $or$libresoc.v:42409$1815_Y - connect \$1777 $pos$libresoc.v:42410$1817_Y - connect \$1781 $and$libresoc.v:42411$1818_Y - connect \$1783 $and$libresoc.v:42412$1819_Y - connect \$1786 $and$libresoc.v:42413$1820_Y - connect \$1789 $not$libresoc.v:42414$1821_Y - connect \$1791 $and$libresoc.v:42415$1822_Y - connect \$1794 $and$libresoc.v:42416$1823_Y - connect \$1797 $ternary$libresoc.v:42417$1824_Y - connect \$1799 $pos$libresoc.v:42418$1826_Y - connect \$1801 $and$libresoc.v:42419$1827_Y - connect \$1803 $and$libresoc.v:42420$1828_Y - connect \$1806 $and$libresoc.v:42421$1829_Y - connect \$1809 $not$libresoc.v:42422$1830_Y - connect \$1811 $and$libresoc.v:42423$1831_Y - connect \$1814 $and$libresoc.v:42424$1832_Y - connect \$1817 $ternary$libresoc.v:42425$1833_Y - connect \$182 $and$libresoc.v:42426$1834_Y - connect \$181 $reduce_or$libresoc.v:42427$1835_Y - connect \$186 $and$libresoc.v:42428$1836_Y - connect \$185 $reduce_or$libresoc.v:42429$1837_Y - connect \$190 $and$libresoc.v:42430$1838_Y - connect \$189 $reduce_or$libresoc.v:42431$1839_Y - connect \$194 $and$libresoc.v:42432$1840_Y - connect \$193 $reduce_or$libresoc.v:42433$1841_Y - connect \$198 $and$libresoc.v:42434$1842_Y - connect \$197 $reduce_or$libresoc.v:42435$1843_Y - connect \$202 $and$libresoc.v:42436$1844_Y - connect \$201 $reduce_or$libresoc.v:42437$1845_Y - connect \$206 $and$libresoc.v:42438$1846_Y - connect \$205 $reduce_or$libresoc.v:42439$1847_Y - connect \$210 $and$libresoc.v:42440$1848_Y - connect \$209 $reduce_or$libresoc.v:42441$1849_Y - connect \$214 $and$libresoc.v:42442$1850_Y - connect \$213 $reduce_or$libresoc.v:42443$1851_Y - connect \$218 $and$libresoc.v:42444$1852_Y - connect \$217 $reduce_or$libresoc.v:42445$1853_Y - connect \$221 $ne$libresoc.v:42446$1854_Y - connect \$224 $sub$libresoc.v:42447$1855_Y - connect \$226 $ne$libresoc.v:42448$1856_Y - connect \$229 $and$libresoc.v:42449$1857_Y - connect \$231 $and$libresoc.v:42450$1858_Y - connect \$233 $eq$libresoc.v:42451$1859_Y - connect \$235 $or$libresoc.v:42452$1860_Y - connect \$237 $and$libresoc.v:42453$1861_Y - connect \$239 $or$libresoc.v:42454$1862_Y - connect \$241 $eq$libresoc.v:42455$1863_Y - connect \$243 $and$libresoc.v:42456$1864_Y - connect \$245 $eq$libresoc.v:42457$1865_Y - connect \$247 $or$libresoc.v:42458$1866_Y - connect \$228 $not$libresoc.v:42459$1867_Y - connect \$250 $not$libresoc.v:42460$1868_Y - connect \$252 $not$libresoc.v:42461$1869_Y - connect \$254 $not$libresoc.v:42462$1870_Y - connect \$257 $and$libresoc.v:42463$1871_Y - connect \$259 $and$libresoc.v:42464$1872_Y - connect \$261 $eq$libresoc.v:42465$1873_Y - connect \$263 $or$libresoc.v:42466$1874_Y - connect \$265 $and$libresoc.v:42467$1875_Y - connect \$267 $or$libresoc.v:42468$1876_Y - connect \$256 $not$libresoc.v:42469$1877_Y - connect \$271 $and$libresoc.v:42470$1878_Y - connect \$273 $and$libresoc.v:42471$1879_Y - connect \$275 $eq$libresoc.v:42472$1880_Y - connect \$277 $or$libresoc.v:42473$1881_Y - connect \$279 $and$libresoc.v:42474$1882_Y - connect \$281 $or$libresoc.v:42475$1883_Y - connect \$283 $and$libresoc.v:42476$1884_Y - connect \$285 $and$libresoc.v:42477$1885_Y - connect \$287 $eq$libresoc.v:42478$1886_Y - connect \$289 $or$libresoc.v:42479$1887_Y - connect \$291 $eq$libresoc.v:42480$1888_Y - connect \$293 $and$libresoc.v:42481$1889_Y - connect \$295 $eq$libresoc.v:42482$1890_Y - connect \$297 $or$libresoc.v:42483$1891_Y - connect \$270 $not$libresoc.v:42484$1892_Y - connect \$301 $and$libresoc.v:42485$1893_Y - connect \$303 $and$libresoc.v:42486$1894_Y - connect \$305 $eq$libresoc.v:42487$1895_Y - connect \$307 $or$libresoc.v:42488$1896_Y - connect \$309 $and$libresoc.v:42489$1897_Y - connect \$311 $or$libresoc.v:42490$1898_Y - connect \$300 $not$libresoc.v:42491$1899_Y - connect \$315 $and$libresoc.v:42492$1900_Y - connect \$317 $and$libresoc.v:42493$1901_Y - connect \$319 $eq$libresoc.v:42494$1902_Y - connect \$321 $or$libresoc.v:42495$1903_Y - connect \$323 $and$libresoc.v:42496$1904_Y - connect \$325 $or$libresoc.v:42497$1905_Y - connect \$314 $not$libresoc.v:42498$1906_Y - connect \$329 $and$libresoc.v:42499$1907_Y - connect \$331 $and$libresoc.v:42500$1908_Y - connect \$333 $eq$libresoc.v:42501$1909_Y - connect \$335 $or$libresoc.v:42502$1910_Y - connect \$337 $and$libresoc.v:42503$1911_Y - connect \$339 $or$libresoc.v:42504$1912_Y - connect \$341 $eq$libresoc.v:42505$1913_Y - connect \$343 $and$libresoc.v:42506$1914_Y - connect \$345 $eq$libresoc.v:42507$1915_Y - connect \$347 $or$libresoc.v:42508$1916_Y - connect \$328 $not$libresoc.v:42509$1917_Y - connect \$350 $not$libresoc.v:42510$1918_Y - connect \$352 $and$libresoc.v:42511$1919_Y - connect \$354 $and$libresoc.v:42512$1920_Y - connect \$356 $not$libresoc.v:42513$1921_Y - connect \$358 $and$libresoc.v:42514$1922_Y - connect \$360 $and$libresoc.v:42515$1923_Y - connect \$362 $ternary$libresoc.v:42516$1924_Y - connect \$364 $and$libresoc.v:42517$1925_Y - connect \$366 $and$libresoc.v:42518$1926_Y - connect \$368 $not$libresoc.v:42519$1927_Y - connect \$370 $and$libresoc.v:42520$1928_Y - connect \$372 $and$libresoc.v:42521$1929_Y - connect \$374 $ternary$libresoc.v:42522$1930_Y - connect \$376 $and$libresoc.v:42523$1931_Y - connect \$378 $and$libresoc.v:42524$1932_Y - connect \$380 $not$libresoc.v:42525$1933_Y - connect \$382 $and$libresoc.v:42526$1934_Y - connect \$384 $and$libresoc.v:42527$1935_Y - connect \$386 $ternary$libresoc.v:42528$1936_Y - connect \$388 $and$libresoc.v:42529$1937_Y - connect \$390 $and$libresoc.v:42530$1938_Y - connect \$392 $not$libresoc.v:42531$1939_Y - connect \$394 $and$libresoc.v:42532$1940_Y - connect \$396 $and$libresoc.v:42533$1941_Y - connect \$398 $ternary$libresoc.v:42534$1942_Y - connect \$400 $and$libresoc.v:42535$1943_Y - connect \$402 $and$libresoc.v:42536$1944_Y - connect \$404 $not$libresoc.v:42537$1945_Y - connect \$406 $and$libresoc.v:42538$1946_Y - connect \$408 $and$libresoc.v:42539$1947_Y - connect \$410 $ternary$libresoc.v:42540$1948_Y - connect \$412 $and$libresoc.v:42541$1949_Y - connect \$414 $and$libresoc.v:42542$1950_Y - connect \$416 $not$libresoc.v:42543$1951_Y - connect \$418 $and$libresoc.v:42544$1952_Y - connect \$420 $and$libresoc.v:42545$1953_Y - connect \$422 $ternary$libresoc.v:42546$1954_Y - connect \$424 $and$libresoc.v:42547$1955_Y - connect \$426 $and$libresoc.v:42548$1956_Y - connect \$428 $not$libresoc.v:42549$1957_Y - connect \$430 $and$libresoc.v:42550$1958_Y - connect \$432 $and$libresoc.v:42551$1959_Y - connect \$434 $ternary$libresoc.v:42552$1960_Y - connect \$436 $and$libresoc.v:42553$1961_Y - connect \$438 $and$libresoc.v:42554$1962_Y - connect \$440 $not$libresoc.v:42555$1963_Y - connect \$442 $and$libresoc.v:42556$1964_Y - connect \$444 $and$libresoc.v:42557$1965_Y - connect \$446 $ternary$libresoc.v:42558$1966_Y - connect \$448 $and$libresoc.v:42559$1967_Y - connect \$450 $and$libresoc.v:42560$1968_Y - connect \$452 $not$libresoc.v:42561$1969_Y - connect \$454 $and$libresoc.v:42562$1970_Y - connect \$456 $and$libresoc.v:42563$1971_Y - connect \$458 $ternary$libresoc.v:42564$1972_Y - connect \$461 $or$libresoc.v:42565$1973_Y - connect \$463 $or$libresoc.v:42566$1974_Y - connect \$465 $or$libresoc.v:42567$1975_Y - connect \$467 $or$libresoc.v:42568$1976_Y - connect \$469 $or$libresoc.v:42569$1977_Y - connect \$471 $or$libresoc.v:42570$1978_Y - connect \$473 $or$libresoc.v:42571$1979_Y - connect \$475 $or$libresoc.v:42572$1980_Y - connect \$477 $reduce_or$libresoc.v:42573$1981_Y - connect \$479 $and$libresoc.v:42574$1982_Y - connect \$481 $and$libresoc.v:42575$1983_Y - connect \$483 $not$libresoc.v:42576$1984_Y - connect \$485 $and$libresoc.v:42577$1985_Y - connect \$487 $and$libresoc.v:42578$1986_Y - connect \$489 $ternary$libresoc.v:42579$1987_Y - connect \$491 $and$libresoc.v:42580$1988_Y - connect \$493 $and$libresoc.v:42581$1989_Y - connect \$495 $not$libresoc.v:42582$1990_Y - connect \$497 $and$libresoc.v:42583$1991_Y - connect \$499 $and$libresoc.v:42584$1992_Y - connect \$501 $ternary$libresoc.v:42585$1993_Y - connect \$503 $and$libresoc.v:42586$1994_Y - connect \$505 $and$libresoc.v:42587$1995_Y - connect \$507 $not$libresoc.v:42588$1996_Y - connect \$509 $and$libresoc.v:42589$1997_Y - connect \$511 $and$libresoc.v:42590$1998_Y - connect \$513 $ternary$libresoc.v:42591$1999_Y - connect \$515 $and$libresoc.v:42592$2000_Y - connect \$517 $and$libresoc.v:42593$2001_Y - connect \$519 $not$libresoc.v:42594$2002_Y - connect \$521 $and$libresoc.v:42595$2003_Y - connect \$523 $and$libresoc.v:42596$2004_Y - connect \$525 $ternary$libresoc.v:42597$2005_Y - connect \$527 $and$libresoc.v:42598$2006_Y - connect \$529 $and$libresoc.v:42599$2007_Y - connect \$531 $not$libresoc.v:42600$2008_Y - connect \$533 $and$libresoc.v:42601$2009_Y - connect \$535 $and$libresoc.v:42602$2010_Y - connect \$537 $ternary$libresoc.v:42603$2011_Y - connect \$539 $and$libresoc.v:42604$2012_Y - connect \$541 $and$libresoc.v:42605$2013_Y - connect \$543 $not$libresoc.v:42606$2014_Y - connect \$545 $and$libresoc.v:42607$2015_Y - connect \$547 $and$libresoc.v:42608$2016_Y - connect \$549 $ternary$libresoc.v:42609$2017_Y - connect \$551 $and$libresoc.v:42610$2018_Y - connect \$553 $and$libresoc.v:42611$2019_Y - connect \$555 $not$libresoc.v:42612$2020_Y - connect \$557 $and$libresoc.v:42613$2021_Y - connect \$559 $and$libresoc.v:42614$2022_Y - connect \$561 $ternary$libresoc.v:42615$2023_Y - connect \$563 $and$libresoc.v:42616$2024_Y - connect \$565 $and$libresoc.v:42617$2025_Y - connect \$567 $not$libresoc.v:42618$2026_Y - connect \$569 $and$libresoc.v:42619$2027_Y - connect \$571 $and$libresoc.v:42620$2028_Y - connect \$573 $ternary$libresoc.v:42621$2029_Y - connect \$576 $or$libresoc.v:42622$2030_Y - connect \$578 $or$libresoc.v:42623$2031_Y - connect \$580 $or$libresoc.v:42624$2032_Y - connect \$582 $or$libresoc.v:42625$2033_Y - connect \$584 $or$libresoc.v:42626$2034_Y - connect \$586 $or$libresoc.v:42627$2035_Y - connect \$588 $or$libresoc.v:42628$2036_Y - connect \$590 $reduce_or$libresoc.v:42629$2037_Y - connect \$592 $and$libresoc.v:42630$2038_Y - connect \$594 $and$libresoc.v:42631$2039_Y - connect \$596 $not$libresoc.v:42632$2040_Y - connect \$598 $and$libresoc.v:42633$2041_Y - connect \$600 $and$libresoc.v:42634$2042_Y - connect \$602 $ternary$libresoc.v:42635$2043_Y - connect \$604 $and$libresoc.v:42636$2044_Y - connect \$606 $and$libresoc.v:42637$2045_Y - connect \$608 $not$libresoc.v:42638$2046_Y - connect \$610 $and$libresoc.v:42639$2047_Y - connect \$612 $and$libresoc.v:42640$2048_Y - connect \$614 $ternary$libresoc.v:42641$2049_Y - connect \$617 $or$libresoc.v:42642$2050_Y - connect \$619 $reduce_or$libresoc.v:42643$2051_Y - connect \$621 $and$libresoc.v:42644$2052_Y - connect \$623 $and$libresoc.v:42645$2053_Y - connect \$625 $eq$libresoc.v:42646$2054_Y - connect \$627 $or$libresoc.v:42647$2055_Y - connect \$629 $and$libresoc.v:42648$2056_Y - connect \$631 $or$libresoc.v:42649$2057_Y - connect \$633 $and$libresoc.v:42650$2058_Y - connect \$635 $and$libresoc.v:42651$2059_Y - connect \$637 $not$libresoc.v:42652$2060_Y - connect \$639 $and$libresoc.v:42653$2061_Y - connect \$641 $and$libresoc.v:42654$2062_Y - connect \$643 $ternary$libresoc.v:42655$2063_Y - connect \$645 $and$libresoc.v:42656$2064_Y - connect \$647 $and$libresoc.v:42657$2065_Y - connect \$649 $not$libresoc.v:42658$2066_Y - connect \$651 $and$libresoc.v:42659$2067_Y - connect \$653 $and$libresoc.v:42660$2068_Y - connect \$655 $ternary$libresoc.v:42661$2069_Y - connect \$657 $and$libresoc.v:42662$2070_Y - connect \$659 $and$libresoc.v:42663$2071_Y - connect \$661 $not$libresoc.v:42664$2072_Y - connect \$663 $and$libresoc.v:42665$2073_Y - connect \$665 $and$libresoc.v:42666$2074_Y - connect \$667 $ternary$libresoc.v:42667$2075_Y - connect \$669 $and$libresoc.v:42668$2076_Y - connect \$671 $and$libresoc.v:42669$2077_Y - connect \$673 $not$libresoc.v:42670$2078_Y - connect \$675 $and$libresoc.v:42671$2079_Y - connect \$677 $and$libresoc.v:42672$2080_Y - connect \$679 $ternary$libresoc.v:42673$2081_Y - connect \$681 $and$libresoc.v:42674$2082_Y - connect \$683 $and$libresoc.v:42675$2083_Y - connect \$685 $not$libresoc.v:42676$2084_Y - connect \$687 $and$libresoc.v:42677$2085_Y - connect \$689 $and$libresoc.v:42678$2086_Y - connect \$691 $ternary$libresoc.v:42679$2087_Y - connect \$693 $and$libresoc.v:42680$2088_Y - connect \$695 $and$libresoc.v:42681$2089_Y - connect \$697 $not$libresoc.v:42682$2090_Y - connect \$699 $and$libresoc.v:42683$2091_Y - connect \$701 $and$libresoc.v:42684$2092_Y - connect \$703 $ternary$libresoc.v:42685$2093_Y - connect \$706 $or$libresoc.v:42686$2094_Y - connect \$708 $or$libresoc.v:42687$2095_Y - connect \$710 $or$libresoc.v:42688$2096_Y - connect \$712 $or$libresoc.v:42689$2097_Y - connect \$714 $or$libresoc.v:42690$2098_Y - connect \$705 $pos$libresoc.v:42691$2100_Y - connect \$717 $eq$libresoc.v:42692$2101_Y - connect \$719 $and$libresoc.v:42693$2102_Y - connect \$721 $eq$libresoc.v:42694$2103_Y - connect \$723 $or$libresoc.v:42695$2104_Y - connect \$725 $and$libresoc.v:42696$2105_Y - connect \$727 $and$libresoc.v:42697$2106_Y - connect \$729 $not$libresoc.v:42698$2107_Y - connect \$731 $and$libresoc.v:42699$2108_Y - connect \$733 $and$libresoc.v:42700$2109_Y - connect \$735 $ternary$libresoc.v:42701$2110_Y - connect \$737 $and$libresoc.v:42702$2111_Y - connect \$739 $and$libresoc.v:42703$2112_Y - connect \$741 $not$libresoc.v:42704$2113_Y - connect \$743 $and$libresoc.v:42705$2114_Y - connect \$745 $and$libresoc.v:42706$2115_Y - connect \$747 $ternary$libresoc.v:42707$2116_Y - connect \$749 $and$libresoc.v:42708$2117_Y - connect \$751 $and$libresoc.v:42709$2118_Y - connect \$753 $not$libresoc.v:42710$2119_Y - connect \$755 $and$libresoc.v:42711$2120_Y - connect \$757 $and$libresoc.v:42712$2121_Y - connect \$759 $ternary$libresoc.v:42713$2122_Y - connect \$762 $or$libresoc.v:42714$2123_Y - connect \$764 $or$libresoc.v:42715$2124_Y - connect \$761 $pos$libresoc.v:42716$2126_Y - connect \$767 $and$libresoc.v:42717$2127_Y - connect \$769 $and$libresoc.v:42718$2128_Y - connect \$771 $eq$libresoc.v:42719$2129_Y - connect \$773 $or$libresoc.v:42720$2130_Y - connect \$775 $and$libresoc.v:42721$2131_Y - connect \$777 $and$libresoc.v:42722$2132_Y - connect \$779 $not$libresoc.v:42723$2133_Y - connect \$781 $and$libresoc.v:42724$2134_Y - connect \$783 $and$libresoc.v:42725$2135_Y - connect \$785 $ternary$libresoc.v:42726$2136_Y - connect \$787 $and$libresoc.v:42727$2137_Y - connect \$789 $and$libresoc.v:42728$2138_Y - connect \$791 $not$libresoc.v:42729$2139_Y - connect \$793 $and$libresoc.v:42730$2140_Y - connect \$795 $and$libresoc.v:42731$2141_Y - connect \$797 $ternary$libresoc.v:42732$2142_Y - connect \$799 $and$libresoc.v:42733$2143_Y - connect \$801 $and$libresoc.v:42734$2144_Y - connect \$803 $not$libresoc.v:42735$2145_Y - connect \$805 $and$libresoc.v:42736$2146_Y - connect \$807 $and$libresoc.v:42737$2147_Y - connect \$809 $sub$libresoc.v:42738$2148_Y - connect \$811 $sshl$libresoc.v:42739$2149_Y - connect \$813 $ternary$libresoc.v:42740$2150_Y - connect \$815 $and$libresoc.v:42741$2151_Y - connect \$817 $and$libresoc.v:42742$2152_Y - connect \$819 $not$libresoc.v:42743$2153_Y - connect \$821 $and$libresoc.v:42744$2154_Y - connect \$823 $and$libresoc.v:42745$2155_Y - connect \$825 $sub$libresoc.v:42746$2156_Y - connect \$827 $sshl$libresoc.v:42747$2157_Y - connect \$829 $ternary$libresoc.v:42748$2158_Y - connect \$832 $or$libresoc.v:42749$2159_Y - connect \$834 $and$libresoc.v:42750$2160_Y - connect \$836 $and$libresoc.v:42751$2161_Y - connect \$838 $not$libresoc.v:42752$2162_Y - connect \$840 $and$libresoc.v:42753$2163_Y - connect \$842 $and$libresoc.v:42754$2164_Y - connect \$844 $sub$libresoc.v:42755$2165_Y - connect \$846 $sshl$libresoc.v:42756$2166_Y - connect \$848 $ternary$libresoc.v:42757$2167_Y - connect \$850 $and$libresoc.v:42758$2168_Y - connect \$852 $and$libresoc.v:42759$2169_Y - connect \$854 $not$libresoc.v:42760$2170_Y - connect \$856 $and$libresoc.v:42761$2171_Y - connect \$858 $and$libresoc.v:42762$2172_Y - connect \$860 $sub$libresoc.v:42763$2173_Y - connect \$862 $sshl$libresoc.v:42764$2174_Y - connect \$864 $ternary$libresoc.v:42765$2175_Y - connect \$866 $and$libresoc.v:42766$2176_Y - connect \$868 $and$libresoc.v:42767$2177_Y - connect \$870 $not$libresoc.v:42768$2178_Y - connect \$872 $and$libresoc.v:42769$2179_Y - connect \$874 $and$libresoc.v:42770$2180_Y - connect \$876 $ternary$libresoc.v:42771$2181_Y - connect \$878 $and$libresoc.v:42772$2182_Y - connect \$880 $and$libresoc.v:42773$2183_Y - connect \$882 $not$libresoc.v:42774$2184_Y - connect \$884 $and$libresoc.v:42775$2185_Y - connect \$886 $and$libresoc.v:42776$2186_Y - connect \$888 $ternary$libresoc.v:42777$2187_Y - connect \$890 $and$libresoc.v:42778$2188_Y - connect \$892 $and$libresoc.v:42779$2189_Y - connect \$894 $not$libresoc.v:42780$2190_Y - connect \$896 $and$libresoc.v:42781$2191_Y - connect \$898 $and$libresoc.v:42782$2192_Y - connect \$900 $ternary$libresoc.v:42783$2193_Y - connect \$902 $or$libresoc.v:42784$2194_Y - connect \$904 $or$libresoc.v:42785$2195_Y - connect \$906 $reduce_or$libresoc.v:42786$2196_Y - connect \$908 $and$libresoc.v:42787$2197_Y - connect \$910 $and$libresoc.v:42788$2198_Y - connect \$912 $not$libresoc.v:42789$2199_Y - connect \$914 $and$libresoc.v:42790$2200_Y - connect \$916 $and$libresoc.v:42791$2201_Y - connect \$918 $ternary$libresoc.v:42792$2202_Y - connect \$920 $and$libresoc.v:42793$2203_Y - connect \$922 $and$libresoc.v:42794$2204_Y - connect \$924 $not$libresoc.v:42795$2205_Y - connect \$926 $and$libresoc.v:42796$2206_Y - connect \$928 $and$libresoc.v:42797$2207_Y - connect \$930 $ternary$libresoc.v:42798$2208_Y - connect \$932 $or$libresoc.v:42799$2209_Y - connect \$934 $reduce_or$libresoc.v:42800$2210_Y - connect \$936 $and$libresoc.v:42801$2211_Y - connect \$938 $and$libresoc.v:42802$2212_Y - connect \$940 $not$libresoc.v:42803$2213_Y - connect \$942 $and$libresoc.v:42804$2214_Y - connect \$944 $and$libresoc.v:42805$2215_Y - connect \$946 $ternary$libresoc.v:42806$2216_Y - connect \$948 $reduce_or$libresoc.v:42807$2217_Y - connect \$950 $and$libresoc.v:42808$2218_Y - connect \$952 $and$libresoc.v:42809$2219_Y - connect \$954 $and$libresoc.v:42810$2220_Y - connect \$956 $and$libresoc.v:42811$2221_Y - connect \$958 $and$libresoc.v:42812$2222_Y - connect \$960 $and$libresoc.v:42813$2223_Y - connect \$962 $and$libresoc.v:42814$2224_Y - connect \$964 $and$libresoc.v:42815$2225_Y - connect \$966 $and$libresoc.v:42816$2226_Y - connect \$968 $and$libresoc.v:42817$2227_Y - connect \$970 $and$libresoc.v:42818$2228_Y - connect \$972 $and$libresoc.v:42819$2229_Y - connect \$974 $not$libresoc.v:42820$2230_Y - connect \$976 $and$libresoc.v:42821$2231_Y - connect \$982 $and$libresoc.v:42822$2232_Y - connect \$984 $ternary$libresoc.v:42823$2233_Y - connect \$986 $and$libresoc.v:42824$2234_Y - connect \$989 $and$libresoc.v:42825$2235_Y - connect \$993 $not$libresoc.v:42826$2236_Y - connect \$995 $and$libresoc.v:42827$2237_Y + connect \$1001 $ternary$libresoc.v:41907$1506_Y + connect \$1003 $and$libresoc.v:41908$1507_Y + connect \$1006 $and$libresoc.v:41909$1508_Y + connect \$1010 $not$libresoc.v:41910$1509_Y + connect \$1012 $and$libresoc.v:41911$1510_Y + connect \$1019 $and$libresoc.v:41912$1511_Y + connect \$1022 $ternary$libresoc.v:41913$1512_Y + connect \$1024 $and$libresoc.v:41914$1513_Y + connect \$1027 $and$libresoc.v:41915$1514_Y + connect \$1031 $not$libresoc.v:41916$1515_Y + connect \$1033 $and$libresoc.v:41917$1516_Y + connect \$1037 $and$libresoc.v:41918$1517_Y + connect \$1040 $ternary$libresoc.v:41919$1518_Y + connect \$1042 $and$libresoc.v:41920$1519_Y + connect \$1045 $and$libresoc.v:41921$1520_Y + connect \$1049 $not$libresoc.v:41922$1521_Y + connect \$1051 $and$libresoc.v:41923$1522_Y + connect \$1059 $and$libresoc.v:41924$1523_Y + connect \$1062 $ternary$libresoc.v:41925$1524_Y + connect \$1064 $and$libresoc.v:41926$1525_Y + connect \$1067 $and$libresoc.v:41927$1526_Y + connect \$1071 $not$libresoc.v:41928$1527_Y + connect \$1073 $and$libresoc.v:41929$1528_Y + connect \$1079 $and$libresoc.v:41930$1529_Y + connect \$1082 $ternary$libresoc.v:41931$1530_Y + connect \$1084 $and$libresoc.v:41932$1531_Y + connect \$1087 $and$libresoc.v:41933$1532_Y + connect \$1091 $not$libresoc.v:41934$1533_Y + connect \$1093 $and$libresoc.v:41935$1534_Y + connect \$1099 $and$libresoc.v:41936$1535_Y + connect \$1102 $ternary$libresoc.v:41937$1536_Y + connect \$1104 $and$libresoc.v:41938$1537_Y + connect \$1107 $and$libresoc.v:41939$1538_Y + connect \$1111 $not$libresoc.v:41940$1539_Y + connect \$1113 $and$libresoc.v:41941$1540_Y + connect \$1118 $and$libresoc.v:41942$1541_Y + connect \$1121 $ternary$libresoc.v:41943$1542_Y + connect \$1123 $and$libresoc.v:41944$1543_Y + connect \$1126 $and$libresoc.v:41945$1544_Y + connect \$1130 $not$libresoc.v:41946$1545_Y + connect \$1132 $and$libresoc.v:41947$1546_Y + connect \$1136 $and$libresoc.v:41948$1547_Y + connect \$1139 $ternary$libresoc.v:41949$1548_Y + connect \$1141 $and$libresoc.v:41950$1549_Y + connect \$1144 $and$libresoc.v:41951$1550_Y + connect \$1147 $not$libresoc.v:41952$1551_Y + connect \$1149 $and$libresoc.v:41953$1552_Y + connect \$1152 $and$libresoc.v:41954$1553_Y + connect \$1155 $ternary$libresoc.v:41955$1554_Y + connect \$1158 $or$libresoc.v:41956$1555_Y + connect \$1160 $or$libresoc.v:41957$1556_Y + connect \$1162 $or$libresoc.v:41958$1557_Y + connect \$1164 $or$libresoc.v:41959$1558_Y + connect \$1166 $or$libresoc.v:41960$1559_Y + connect \$1168 $or$libresoc.v:41961$1560_Y + connect \$1170 $or$libresoc.v:41962$1561_Y + connect \$1172 $or$libresoc.v:41963$1562_Y + connect \$1174 $or$libresoc.v:41964$1563_Y + connect \$1177 $or$libresoc.v:41965$1564_Y + connect \$1179 $or$libresoc.v:41966$1565_Y + connect \$1181 $or$libresoc.v:41967$1566_Y + connect \$1183 $or$libresoc.v:41968$1567_Y + connect \$1185 $or$libresoc.v:41969$1568_Y + connect \$1187 $or$libresoc.v:41970$1569_Y + connect \$1189 $or$libresoc.v:41971$1570_Y + connect \$1191 $or$libresoc.v:41972$1571_Y + connect \$1193 $or$libresoc.v:41973$1572_Y + connect \$1195 $or$libresoc.v:41974$1573_Y + connect \$1197 $or$libresoc.v:41975$1574_Y + connect \$1199 $or$libresoc.v:41976$1575_Y + connect \$1201 $or$libresoc.v:41977$1576_Y + connect \$1203 $or$libresoc.v:41978$1577_Y + connect \$1205 $or$libresoc.v:41979$1578_Y + connect \$1207 $or$libresoc.v:41980$1579_Y + connect \$1209 $or$libresoc.v:41981$1580_Y + connect \$1211 $or$libresoc.v:41982$1581_Y + connect \$1213 $and$libresoc.v:41983$1582_Y + connect \$1215 $and$libresoc.v:41984$1583_Y + connect \$1218 $and$libresoc.v:41985$1584_Y + connect \$1221 $not$libresoc.v:41986$1585_Y + connect \$1223 $and$libresoc.v:41987$1586_Y + connect \$1226 $and$libresoc.v:41988$1587_Y + connect \$1229 $ternary$libresoc.v:41989$1588_Y + connect \$1231 $and$libresoc.v:41990$1589_Y + connect \$1233 $and$libresoc.v:41991$1590_Y + connect \$1235 $and$libresoc.v:41992$1591_Y + connect \$1237 $and$libresoc.v:41993$1592_Y + connect \$1239 $and$libresoc.v:41994$1593_Y + connect \$1241 $and$libresoc.v:41995$1594_Y + connect \$1243 $and$libresoc.v:41996$1595_Y + connect \$1246 $and$libresoc.v:41997$1596_Y + connect \$1249 $not$libresoc.v:41998$1597_Y + connect \$1251 $and$libresoc.v:41999$1598_Y + connect \$1254 $and$libresoc.v:42000$1599_Y + connect \$1257 $sub$libresoc.v:42001$1600_Y + connect \$1259 $sshl$libresoc.v:42002$1601_Y + connect \$1261 $ternary$libresoc.v:42003$1602_Y + connect \$1263 $and$libresoc.v:42004$1603_Y + connect \$1266 $and$libresoc.v:42005$1604_Y + connect \$1269 $not$libresoc.v:42006$1605_Y + connect \$1271 $and$libresoc.v:42007$1606_Y + connect \$1274 $and$libresoc.v:42008$1607_Y + connect \$1277 $sub$libresoc.v:42009$1608_Y + connect \$1279 $sshl$libresoc.v:42010$1609_Y + connect \$1281 $ternary$libresoc.v:42011$1610_Y + connect \$1283 $and$libresoc.v:42012$1611_Y + connect \$1286 $and$libresoc.v:42013$1612_Y + connect \$1289 $not$libresoc.v:42014$1613_Y + connect \$1291 $and$libresoc.v:42015$1614_Y + connect \$1294 $and$libresoc.v:42016$1615_Y + connect \$1297 $sub$libresoc.v:42017$1616_Y + connect \$1299 $sshl$libresoc.v:42018$1617_Y + connect \$1301 $ternary$libresoc.v:42019$1618_Y + connect \$1303 $and$libresoc.v:42020$1619_Y + connect \$1306 $and$libresoc.v:42021$1620_Y + connect \$1309 $not$libresoc.v:42022$1621_Y + connect \$1311 $and$libresoc.v:42023$1622_Y + connect \$1314 $and$libresoc.v:42024$1623_Y + connect \$1317 $sub$libresoc.v:42025$1624_Y + connect \$1319 $sshl$libresoc.v:42026$1625_Y + connect \$1321 $ternary$libresoc.v:42027$1626_Y + connect \$1323 $and$libresoc.v:42028$1627_Y + connect \$1326 $and$libresoc.v:42029$1628_Y + connect \$1329 $not$libresoc.v:42030$1629_Y + connect \$1331 $and$libresoc.v:42031$1630_Y + connect \$1334 $and$libresoc.v:42032$1631_Y + connect \$1337 $sub$libresoc.v:42033$1632_Y + connect \$1339 $sshl$libresoc.v:42034$1633_Y + connect \$1341 $ternary$libresoc.v:42035$1634_Y + connect \$1343 $and$libresoc.v:42036$1635_Y + connect \$1346 $and$libresoc.v:42037$1636_Y + connect \$1349 $not$libresoc.v:42038$1637_Y + connect \$1351 $and$libresoc.v:42039$1638_Y + connect \$1354 $and$libresoc.v:42040$1639_Y + connect \$1357 $sub$libresoc.v:42041$1640_Y + connect \$1359 $sshl$libresoc.v:42042$1641_Y + connect \$1361 $ternary$libresoc.v:42043$1642_Y + connect \$1363 $or$libresoc.v:42044$1643_Y + connect \$1365 $or$libresoc.v:42045$1644_Y + connect \$1367 $or$libresoc.v:42046$1645_Y + connect \$1369 $or$libresoc.v:42047$1646_Y + connect \$1371 $or$libresoc.v:42048$1647_Y + connect \$1374 $or$libresoc.v:42049$1648_Y + connect \$1376 $or$libresoc.v:42050$1649_Y + connect \$1378 $or$libresoc.v:42051$1650_Y + connect \$1380 $or$libresoc.v:42052$1651_Y + connect \$1382 $or$libresoc.v:42053$1652_Y + connect \$1384 $and$libresoc.v:42054$1653_Y + connect \$1386 $and$libresoc.v:42055$1654_Y + connect \$1388 $and$libresoc.v:42056$1655_Y + connect \$1390 $and$libresoc.v:42057$1656_Y + connect \$1393 $and$libresoc.v:42058$1657_Y + connect \$1396 $not$libresoc.v:42059$1658_Y + connect \$1398 $and$libresoc.v:42060$1659_Y + connect \$1401 $and$libresoc.v:42061$1660_Y + connect \$1404 $ternary$libresoc.v:42062$1661_Y + connect \$1406 $and$libresoc.v:42063$1662_Y + connect \$1409 $and$libresoc.v:42064$1663_Y + connect \$1412 $not$libresoc.v:42065$1664_Y + connect \$1414 $and$libresoc.v:42066$1665_Y + connect \$1417 $and$libresoc.v:42067$1666_Y + connect \$1420 $ternary$libresoc.v:42068$1667_Y + connect \$1422 $and$libresoc.v:42069$1668_Y + connect \$1425 $and$libresoc.v:42070$1669_Y + connect \$1428 $not$libresoc.v:42071$1670_Y + connect \$1430 $and$libresoc.v:42072$1671_Y + connect \$1433 $and$libresoc.v:42073$1672_Y + connect \$1436 $ternary$libresoc.v:42074$1673_Y + connect \$1438 $or$libresoc.v:42075$1674_Y + connect \$1440 $or$libresoc.v:42076$1675_Y + connect \$1443 $or$libresoc.v:42077$1676_Y + connect \$1445 $or$libresoc.v:42078$1677_Y + connect \$1442 $pos$libresoc.v:42079$1679_Y + connect \$1448 $and$libresoc.v:42080$1680_Y + connect \$1450 $and$libresoc.v:42081$1681_Y + connect \$1452 $and$libresoc.v:42082$1682_Y + connect \$1454 $and$libresoc.v:42083$1683_Y + connect \$1456 $and$libresoc.v:42084$1684_Y + connect \$1459 $and$libresoc.v:42085$1685_Y + connect \$1462 $not$libresoc.v:42086$1686_Y + connect \$1464 $and$libresoc.v:42087$1687_Y + connect \$1467 $and$libresoc.v:42088$1688_Y + connect \$1470 $ternary$libresoc.v:42089$1689_Y + connect \$1472 $and$libresoc.v:42090$1690_Y + connect \$1475 $and$libresoc.v:42091$1691_Y + connect \$1478 $not$libresoc.v:42092$1692_Y + connect \$1480 $and$libresoc.v:42093$1693_Y + connect \$1483 $and$libresoc.v:42094$1694_Y + connect \$1486 $ternary$libresoc.v:42095$1695_Y + connect \$1488 $and$libresoc.v:42096$1696_Y + connect \$1491 $and$libresoc.v:42097$1697_Y + connect \$1494 $not$libresoc.v:42098$1698_Y + connect \$1496 $and$libresoc.v:42099$1699_Y + connect \$1499 $and$libresoc.v:42100$1700_Y + connect \$1502 $ternary$libresoc.v:42101$1701_Y + connect \$1504 $and$libresoc.v:42102$1702_Y + connect \$1507 $and$libresoc.v:42103$1703_Y + connect \$1510 $not$libresoc.v:42104$1704_Y + connect \$1512 $and$libresoc.v:42105$1705_Y + connect \$1515 $and$libresoc.v:42106$1706_Y + connect \$1518 $ternary$libresoc.v:42107$1707_Y + connect \$1520 $or$libresoc.v:42108$1708_Y + connect \$1522 $or$libresoc.v:42109$1709_Y + connect \$1524 $or$libresoc.v:42110$1710_Y + connect \$1526 $or$libresoc.v:42111$1711_Y + connect \$1528 $or$libresoc.v:42112$1712_Y + connect \$1530 $or$libresoc.v:42113$1713_Y + connect \$1532 $and$libresoc.v:42114$1714_Y + connect \$1534 $and$libresoc.v:42115$1715_Y + connect \$1536 $and$libresoc.v:42116$1716_Y + connect \$1538 $and$libresoc.v:42117$1717_Y + connect \$1540 $and$libresoc.v:42118$1718_Y + connect \$1543 $and$libresoc.v:42119$1719_Y + connect \$1546 $not$libresoc.v:42120$1720_Y + connect \$1548 $and$libresoc.v:42121$1721_Y + connect \$1551 $and$libresoc.v:42122$1722_Y + connect \$1554 $ternary$libresoc.v:42123$1723_Y + connect \$1556 $and$libresoc.v:42124$1724_Y + connect \$1559 $and$libresoc.v:42125$1725_Y + connect \$1562 $not$libresoc.v:42126$1726_Y + connect \$1564 $and$libresoc.v:42127$1727_Y + connect \$1567 $and$libresoc.v:42128$1728_Y + connect \$1570 $ternary$libresoc.v:42129$1729_Y + connect \$1572 $and$libresoc.v:42130$1730_Y + connect \$1575 $and$libresoc.v:42131$1731_Y + connect \$1578 $not$libresoc.v:42132$1732_Y + connect \$1580 $and$libresoc.v:42133$1733_Y + connect \$1583 $and$libresoc.v:42134$1734_Y + connect \$1586 $ternary$libresoc.v:42135$1735_Y + connect \$1588 $and$libresoc.v:42136$1736_Y + connect \$1591 $and$libresoc.v:42137$1737_Y + connect \$1594 $not$libresoc.v:42138$1738_Y + connect \$1596 $and$libresoc.v:42139$1739_Y + connect \$1599 $and$libresoc.v:42140$1740_Y + connect \$1602 $ternary$libresoc.v:42141$1741_Y + connect \$1605 $or$libresoc.v:42142$1742_Y + connect \$1607 $or$libresoc.v:42143$1743_Y + connect \$1609 $or$libresoc.v:42144$1744_Y + connect \$1604 $pos$libresoc.v:42145$1746_Y + connect \$1613 $or$libresoc.v:42146$1747_Y + connect \$1615 $or$libresoc.v:42147$1748_Y + connect \$1617 $or$libresoc.v:42148$1749_Y + connect \$1612 $pos$libresoc.v:42149$1751_Y + connect \$1620 $and$libresoc.v:42150$1752_Y + connect \$1622 $and$libresoc.v:42151$1753_Y + connect \$1624 $and$libresoc.v:42152$1754_Y + connect \$1626 $and$libresoc.v:42153$1755_Y + connect \$1628 $and$libresoc.v:42154$1756_Y + connect \$1630 $and$libresoc.v:42155$1757_Y + connect \$1633 $and$libresoc.v:42156$1758_Y + connect \$1637 $not$libresoc.v:42157$1759_Y + connect \$1639 $and$libresoc.v:42158$1760_Y + connect \$1644 $and$libresoc.v:42159$1761_Y + connect \$1647 $ternary$libresoc.v:42160$1762_Y + connect \$1649 $and$libresoc.v:42161$1763_Y + connect \$1652 $and$libresoc.v:42162$1764_Y + connect \$1655 $not$libresoc.v:42163$1765_Y + connect \$1657 $and$libresoc.v:42164$1766_Y + connect \$1660 $and$libresoc.v:42165$1767_Y + connect \$1663 $ternary$libresoc.v:42166$1768_Y + connect \$1665 $and$libresoc.v:42167$1769_Y + connect \$1668 $and$libresoc.v:42168$1770_Y + connect \$1671 $not$libresoc.v:42169$1771_Y + connect \$1673 $and$libresoc.v:42170$1772_Y + connect \$1676 $and$libresoc.v:42171$1773_Y + connect \$1679 $ternary$libresoc.v:42172$1774_Y + connect \$1681 $and$libresoc.v:42173$1775_Y + connect \$1684 $and$libresoc.v:42174$1776_Y + connect \$1687 $not$libresoc.v:42175$1777_Y + connect \$1689 $and$libresoc.v:42176$1778_Y + connect \$1692 $and$libresoc.v:42177$1779_Y + connect \$1695 $ternary$libresoc.v:42178$1780_Y + connect \$1697 $and$libresoc.v:42179$1781_Y + connect \$1700 $and$libresoc.v:42180$1782_Y + connect \$1703 $not$libresoc.v:42181$1783_Y + connect \$1705 $and$libresoc.v:42182$1784_Y + connect \$1708 $and$libresoc.v:42183$1785_Y + connect \$1711 $ternary$libresoc.v:42184$1786_Y + connect \$1713 $or$libresoc.v:42185$1787_Y + connect \$1715 $or$libresoc.v:42186$1788_Y + connect \$1717 $or$libresoc.v:42187$1789_Y + connect \$1719 $or$libresoc.v:42188$1790_Y + connect \$1721 $or$libresoc.v:42189$1791_Y + connect \$1723 $or$libresoc.v:42190$1792_Y + connect \$1725 $or$libresoc.v:42191$1793_Y + connect \$1727 $or$libresoc.v:42192$1794_Y + connect \$1729 $or$libresoc.v:42193$1795_Y + connect \$1731 $or$libresoc.v:42194$1796_Y + connect \$1733 $or$libresoc.v:42195$1797_Y + connect \$1735 $or$libresoc.v:42196$1798_Y + connect \$1737 $and$libresoc.v:42197$1799_Y + connect \$1739 $and$libresoc.v:42198$1800_Y + connect \$1741 $and$libresoc.v:42199$1801_Y + connect \$1744 $and$libresoc.v:42200$1802_Y + connect \$1747 $not$libresoc.v:42201$1803_Y + connect \$1749 $and$libresoc.v:42202$1804_Y + connect \$1752 $and$libresoc.v:42203$1805_Y + connect \$1755 $ternary$libresoc.v:42204$1806_Y + connect \$1757 $and$libresoc.v:42205$1807_Y + connect \$1760 $and$libresoc.v:42206$1808_Y + connect \$1763 $not$libresoc.v:42207$1809_Y + connect \$1765 $and$libresoc.v:42208$1810_Y + connect \$1768 $and$libresoc.v:42209$1811_Y + connect \$1771 $ternary$libresoc.v:42210$1812_Y + connect \$1773 $or$libresoc.v:42211$1813_Y + connect \$1776 $or$libresoc.v:42212$1814_Y + connect \$1775 $pos$libresoc.v:42213$1816_Y + connect \$1779 $and$libresoc.v:42214$1817_Y + connect \$1781 $and$libresoc.v:42215$1818_Y + connect \$1784 $and$libresoc.v:42216$1819_Y + connect \$1787 $not$libresoc.v:42217$1820_Y + connect \$1789 $and$libresoc.v:42218$1821_Y + connect \$1792 $and$libresoc.v:42219$1822_Y + connect \$1795 $ternary$libresoc.v:42220$1823_Y + connect \$1797 $pos$libresoc.v:42221$1825_Y + connect \$1799 $and$libresoc.v:42222$1826_Y + connect \$1801 $and$libresoc.v:42223$1827_Y + connect \$1804 $and$libresoc.v:42224$1828_Y + connect \$1807 $not$libresoc.v:42225$1829_Y + connect \$1809 $and$libresoc.v:42226$1830_Y + connect \$1812 $and$libresoc.v:42227$1831_Y + connect \$1815 $ternary$libresoc.v:42228$1832_Y + connect \$182 $and$libresoc.v:42229$1833_Y + connect \$181 $reduce_or$libresoc.v:42230$1834_Y + connect \$186 $and$libresoc.v:42231$1835_Y + connect \$185 $reduce_or$libresoc.v:42232$1836_Y + connect \$190 $and$libresoc.v:42233$1837_Y + connect \$189 $reduce_or$libresoc.v:42234$1838_Y + connect \$194 $and$libresoc.v:42235$1839_Y + connect \$193 $reduce_or$libresoc.v:42236$1840_Y + connect \$198 $and$libresoc.v:42237$1841_Y + connect \$197 $reduce_or$libresoc.v:42238$1842_Y + connect \$202 $and$libresoc.v:42239$1843_Y + connect \$201 $reduce_or$libresoc.v:42240$1844_Y + connect \$206 $and$libresoc.v:42241$1845_Y + connect \$205 $reduce_or$libresoc.v:42242$1846_Y + connect \$210 $and$libresoc.v:42243$1847_Y + connect \$209 $reduce_or$libresoc.v:42244$1848_Y + connect \$214 $and$libresoc.v:42245$1849_Y + connect \$213 $reduce_or$libresoc.v:42246$1850_Y + connect \$218 $and$libresoc.v:42247$1851_Y + connect \$217 $reduce_or$libresoc.v:42248$1852_Y + connect \$221 $ne$libresoc.v:42249$1853_Y + connect \$224 $sub$libresoc.v:42250$1854_Y + connect \$226 $ne$libresoc.v:42251$1855_Y + connect \$229 $and$libresoc.v:42252$1856_Y + connect \$231 $and$libresoc.v:42253$1857_Y + connect \$233 $eq$libresoc.v:42254$1858_Y + connect \$235 $or$libresoc.v:42255$1859_Y + connect \$237 $and$libresoc.v:42256$1860_Y + connect \$239 $or$libresoc.v:42257$1861_Y + connect \$241 $eq$libresoc.v:42258$1862_Y + connect \$243 $and$libresoc.v:42259$1863_Y + connect \$245 $eq$libresoc.v:42260$1864_Y + connect \$247 $or$libresoc.v:42261$1865_Y + connect \$228 $not$libresoc.v:42262$1866_Y + connect \$250 $not$libresoc.v:42263$1867_Y + connect \$252 $not$libresoc.v:42264$1868_Y + connect \$254 $not$libresoc.v:42265$1869_Y + connect \$257 $and$libresoc.v:42266$1870_Y + connect \$259 $and$libresoc.v:42267$1871_Y + connect \$261 $eq$libresoc.v:42268$1872_Y + connect \$263 $or$libresoc.v:42269$1873_Y + connect \$265 $and$libresoc.v:42270$1874_Y + connect \$267 $or$libresoc.v:42271$1875_Y + connect \$256 $not$libresoc.v:42272$1876_Y + connect \$271 $and$libresoc.v:42273$1877_Y + connect \$273 $and$libresoc.v:42274$1878_Y + connect \$275 $eq$libresoc.v:42275$1879_Y + connect \$277 $or$libresoc.v:42276$1880_Y + connect \$279 $and$libresoc.v:42277$1881_Y + connect \$281 $or$libresoc.v:42278$1882_Y + connect \$283 $and$libresoc.v:42279$1883_Y + connect \$285 $and$libresoc.v:42280$1884_Y + connect \$287 $eq$libresoc.v:42281$1885_Y + connect \$289 $or$libresoc.v:42282$1886_Y + connect \$291 $eq$libresoc.v:42283$1887_Y + connect \$293 $and$libresoc.v:42284$1888_Y + connect \$295 $eq$libresoc.v:42285$1889_Y + connect \$297 $or$libresoc.v:42286$1890_Y + connect \$270 $not$libresoc.v:42287$1891_Y + connect \$301 $and$libresoc.v:42288$1892_Y + connect \$303 $and$libresoc.v:42289$1893_Y + connect \$305 $eq$libresoc.v:42290$1894_Y + connect \$307 $or$libresoc.v:42291$1895_Y + connect \$309 $and$libresoc.v:42292$1896_Y + connect \$311 $or$libresoc.v:42293$1897_Y + connect \$300 $not$libresoc.v:42294$1898_Y + connect \$315 $and$libresoc.v:42295$1899_Y + connect \$317 $and$libresoc.v:42296$1900_Y + connect \$319 $eq$libresoc.v:42297$1901_Y + connect \$321 $or$libresoc.v:42298$1902_Y + connect \$323 $and$libresoc.v:42299$1903_Y + connect \$325 $or$libresoc.v:42300$1904_Y + connect \$314 $not$libresoc.v:42301$1905_Y + connect \$329 $and$libresoc.v:42302$1906_Y + connect \$331 $and$libresoc.v:42303$1907_Y + connect \$333 $eq$libresoc.v:42304$1908_Y + connect \$335 $or$libresoc.v:42305$1909_Y + connect \$337 $and$libresoc.v:42306$1910_Y + connect \$339 $or$libresoc.v:42307$1911_Y + connect \$341 $eq$libresoc.v:42308$1912_Y + connect \$343 $and$libresoc.v:42309$1913_Y + connect \$345 $eq$libresoc.v:42310$1914_Y + connect \$347 $or$libresoc.v:42311$1915_Y + connect \$328 $not$libresoc.v:42312$1916_Y + connect \$350 $not$libresoc.v:42313$1917_Y + connect \$352 $and$libresoc.v:42314$1918_Y + connect \$354 $and$libresoc.v:42315$1919_Y + connect \$356 $not$libresoc.v:42316$1920_Y + connect \$358 $and$libresoc.v:42317$1921_Y + connect \$360 $and$libresoc.v:42318$1922_Y + connect \$362 $ternary$libresoc.v:42319$1923_Y + connect \$364 $and$libresoc.v:42320$1924_Y + connect \$366 $and$libresoc.v:42321$1925_Y + connect \$368 $not$libresoc.v:42322$1926_Y + connect \$370 $and$libresoc.v:42323$1927_Y + connect \$372 $and$libresoc.v:42324$1928_Y + connect \$374 $ternary$libresoc.v:42325$1929_Y + connect \$376 $and$libresoc.v:42326$1930_Y + connect \$378 $and$libresoc.v:42327$1931_Y + connect \$380 $not$libresoc.v:42328$1932_Y + connect \$382 $and$libresoc.v:42329$1933_Y + connect \$384 $and$libresoc.v:42330$1934_Y + connect \$386 $ternary$libresoc.v:42331$1935_Y + connect \$388 $and$libresoc.v:42332$1936_Y + connect \$390 $and$libresoc.v:42333$1937_Y + connect \$392 $not$libresoc.v:42334$1938_Y + connect \$394 $and$libresoc.v:42335$1939_Y + connect \$396 $and$libresoc.v:42336$1940_Y + connect \$398 $ternary$libresoc.v:42337$1941_Y + connect \$400 $and$libresoc.v:42338$1942_Y + connect \$402 $and$libresoc.v:42339$1943_Y + connect \$404 $not$libresoc.v:42340$1944_Y + connect \$406 $and$libresoc.v:42341$1945_Y + connect \$408 $and$libresoc.v:42342$1946_Y + connect \$410 $ternary$libresoc.v:42343$1947_Y + connect \$412 $and$libresoc.v:42344$1948_Y + connect \$414 $and$libresoc.v:42345$1949_Y + connect \$416 $not$libresoc.v:42346$1950_Y + connect \$418 $and$libresoc.v:42347$1951_Y + connect \$420 $and$libresoc.v:42348$1952_Y + connect \$422 $ternary$libresoc.v:42349$1953_Y + connect \$424 $and$libresoc.v:42350$1954_Y + connect \$426 $and$libresoc.v:42351$1955_Y + connect \$428 $not$libresoc.v:42352$1956_Y + connect \$430 $and$libresoc.v:42353$1957_Y + connect \$432 $and$libresoc.v:42354$1958_Y + connect \$434 $ternary$libresoc.v:42355$1959_Y + connect \$436 $and$libresoc.v:42356$1960_Y + connect \$438 $and$libresoc.v:42357$1961_Y + connect \$440 $not$libresoc.v:42358$1962_Y + connect \$442 $and$libresoc.v:42359$1963_Y + connect \$444 $and$libresoc.v:42360$1964_Y + connect \$446 $ternary$libresoc.v:42361$1965_Y + connect \$448 $and$libresoc.v:42362$1966_Y + connect \$450 $and$libresoc.v:42363$1967_Y + connect \$452 $not$libresoc.v:42364$1968_Y + connect \$454 $and$libresoc.v:42365$1969_Y + connect \$456 $and$libresoc.v:42366$1970_Y + connect \$458 $ternary$libresoc.v:42367$1971_Y + connect \$460 $and$libresoc.v:42368$1972_Y + connect \$462 $and$libresoc.v:42369$1973_Y + connect \$464 $not$libresoc.v:42370$1974_Y + connect \$466 $and$libresoc.v:42371$1975_Y + connect \$468 $and$libresoc.v:42372$1976_Y + connect \$470 $ternary$libresoc.v:42373$1977_Y + connect \$472 $and$libresoc.v:42374$1978_Y + connect \$474 $and$libresoc.v:42375$1979_Y + connect \$476 $not$libresoc.v:42376$1980_Y + connect \$478 $and$libresoc.v:42377$1981_Y + connect \$480 $and$libresoc.v:42378$1982_Y + connect \$482 $ternary$libresoc.v:42379$1983_Y + connect \$484 $and$libresoc.v:42380$1984_Y + connect \$486 $and$libresoc.v:42381$1985_Y + connect \$488 $not$libresoc.v:42382$1986_Y + connect \$490 $and$libresoc.v:42383$1987_Y + connect \$492 $and$libresoc.v:42384$1988_Y + connect \$494 $ternary$libresoc.v:42385$1989_Y + connect \$496 $and$libresoc.v:42386$1990_Y + connect \$498 $and$libresoc.v:42387$1991_Y + connect \$500 $not$libresoc.v:42388$1992_Y + connect \$502 $and$libresoc.v:42389$1993_Y + connect \$504 $and$libresoc.v:42390$1994_Y + connect \$506 $ternary$libresoc.v:42391$1995_Y + connect \$508 $and$libresoc.v:42392$1996_Y + connect \$510 $and$libresoc.v:42393$1997_Y + connect \$512 $not$libresoc.v:42394$1998_Y + connect \$514 $and$libresoc.v:42395$1999_Y + connect \$516 $and$libresoc.v:42396$2000_Y + connect \$518 $ternary$libresoc.v:42397$2001_Y + connect \$520 $and$libresoc.v:42398$2002_Y + connect \$522 $and$libresoc.v:42399$2003_Y + connect \$524 $not$libresoc.v:42400$2004_Y + connect \$526 $and$libresoc.v:42401$2005_Y + connect \$528 $and$libresoc.v:42402$2006_Y + connect \$530 $ternary$libresoc.v:42403$2007_Y + connect \$532 $and$libresoc.v:42404$2008_Y + connect \$534 $and$libresoc.v:42405$2009_Y + connect \$536 $not$libresoc.v:42406$2010_Y + connect \$538 $and$libresoc.v:42407$2011_Y + connect \$540 $and$libresoc.v:42408$2012_Y + connect \$542 $ternary$libresoc.v:42409$2013_Y + connect \$544 $and$libresoc.v:42410$2014_Y + connect \$546 $and$libresoc.v:42411$2015_Y + connect \$548 $not$libresoc.v:42412$2016_Y + connect \$550 $and$libresoc.v:42413$2017_Y + connect \$552 $and$libresoc.v:42414$2018_Y + connect \$554 $ternary$libresoc.v:42415$2019_Y + connect \$556 $and$libresoc.v:42416$2020_Y + connect \$558 $and$libresoc.v:42417$2021_Y + connect \$560 $not$libresoc.v:42418$2022_Y + connect \$562 $and$libresoc.v:42419$2023_Y + connect \$564 $and$libresoc.v:42420$2024_Y + connect \$566 $ternary$libresoc.v:42421$2025_Y + connect \$568 $and$libresoc.v:42422$2026_Y + connect \$570 $and$libresoc.v:42423$2027_Y + connect \$572 $not$libresoc.v:42424$2028_Y + connect \$574 $and$libresoc.v:42425$2029_Y + connect \$576 $and$libresoc.v:42426$2030_Y + connect \$578 $ternary$libresoc.v:42427$2031_Y + connect \$581 $or$libresoc.v:42428$2032_Y + connect \$583 $or$libresoc.v:42429$2033_Y + connect \$585 $or$libresoc.v:42430$2034_Y + connect \$587 $or$libresoc.v:42431$2035_Y + connect \$589 $or$libresoc.v:42432$2036_Y + connect \$591 $or$libresoc.v:42433$2037_Y + connect \$593 $or$libresoc.v:42434$2038_Y + connect \$595 $or$libresoc.v:42435$2039_Y + connect \$597 $or$libresoc.v:42436$2040_Y + connect \$599 $or$libresoc.v:42437$2041_Y + connect \$601 $or$libresoc.v:42438$2042_Y + connect \$603 $or$libresoc.v:42439$2043_Y + connect \$605 $or$libresoc.v:42440$2044_Y + connect \$607 $or$libresoc.v:42441$2045_Y + connect \$609 $or$libresoc.v:42442$2046_Y + connect \$611 $or$libresoc.v:42443$2047_Y + connect \$613 $or$libresoc.v:42444$2048_Y + connect \$615 $or$libresoc.v:42445$2049_Y + connect \$617 $reduce_or$libresoc.v:42446$2050_Y + connect \$619 $and$libresoc.v:42447$2051_Y + connect \$621 $and$libresoc.v:42448$2052_Y + connect \$623 $eq$libresoc.v:42449$2053_Y + connect \$625 $or$libresoc.v:42450$2054_Y + connect \$627 $and$libresoc.v:42451$2055_Y + connect \$629 $or$libresoc.v:42452$2056_Y + connect \$631 $and$libresoc.v:42453$2057_Y + connect \$633 $and$libresoc.v:42454$2058_Y + connect \$635 $not$libresoc.v:42455$2059_Y + connect \$637 $and$libresoc.v:42456$2060_Y + connect \$639 $and$libresoc.v:42457$2061_Y + connect \$641 $ternary$libresoc.v:42458$2062_Y + connect \$643 $and$libresoc.v:42459$2063_Y + connect \$645 $and$libresoc.v:42460$2064_Y + connect \$647 $not$libresoc.v:42461$2065_Y + connect \$649 $and$libresoc.v:42462$2066_Y + connect \$651 $and$libresoc.v:42463$2067_Y + connect \$653 $ternary$libresoc.v:42464$2068_Y + connect \$655 $and$libresoc.v:42465$2069_Y + connect \$657 $and$libresoc.v:42466$2070_Y + connect \$659 $not$libresoc.v:42467$2071_Y + connect \$661 $and$libresoc.v:42468$2072_Y + connect \$663 $and$libresoc.v:42469$2073_Y + connect \$665 $ternary$libresoc.v:42470$2074_Y + connect \$667 $and$libresoc.v:42471$2075_Y + connect \$669 $and$libresoc.v:42472$2076_Y + connect \$671 $not$libresoc.v:42473$2077_Y + connect \$673 $and$libresoc.v:42474$2078_Y + connect \$675 $and$libresoc.v:42475$2079_Y + connect \$677 $ternary$libresoc.v:42476$2080_Y + connect \$679 $and$libresoc.v:42477$2081_Y + connect \$681 $and$libresoc.v:42478$2082_Y + connect \$683 $not$libresoc.v:42479$2083_Y + connect \$685 $and$libresoc.v:42480$2084_Y + connect \$687 $and$libresoc.v:42481$2085_Y + connect \$689 $ternary$libresoc.v:42482$2086_Y + connect \$691 $and$libresoc.v:42483$2087_Y + connect \$693 $and$libresoc.v:42484$2088_Y + connect \$695 $not$libresoc.v:42485$2089_Y + connect \$697 $and$libresoc.v:42486$2090_Y + connect \$699 $and$libresoc.v:42487$2091_Y + connect \$701 $ternary$libresoc.v:42488$2092_Y + connect \$704 $or$libresoc.v:42489$2093_Y + connect \$706 $or$libresoc.v:42490$2094_Y + connect \$708 $or$libresoc.v:42491$2095_Y + connect \$710 $or$libresoc.v:42492$2096_Y + connect \$712 $or$libresoc.v:42493$2097_Y + connect \$703 $pos$libresoc.v:42494$2099_Y + connect \$715 $eq$libresoc.v:42495$2100_Y + connect \$717 $and$libresoc.v:42496$2101_Y + connect \$719 $eq$libresoc.v:42497$2102_Y + connect \$721 $or$libresoc.v:42498$2103_Y + connect \$723 $and$libresoc.v:42499$2104_Y + connect \$725 $and$libresoc.v:42500$2105_Y + connect \$727 $not$libresoc.v:42501$2106_Y + connect \$729 $and$libresoc.v:42502$2107_Y + connect \$731 $and$libresoc.v:42503$2108_Y + connect \$733 $ternary$libresoc.v:42504$2109_Y + connect \$735 $and$libresoc.v:42505$2110_Y + connect \$737 $and$libresoc.v:42506$2111_Y + connect \$739 $not$libresoc.v:42507$2112_Y + connect \$741 $and$libresoc.v:42508$2113_Y + connect \$743 $and$libresoc.v:42509$2114_Y + connect \$745 $ternary$libresoc.v:42510$2115_Y + connect \$747 $and$libresoc.v:42511$2116_Y + connect \$749 $and$libresoc.v:42512$2117_Y + connect \$751 $not$libresoc.v:42513$2118_Y + connect \$753 $and$libresoc.v:42514$2119_Y + connect \$755 $and$libresoc.v:42515$2120_Y + connect \$757 $ternary$libresoc.v:42516$2121_Y + connect \$760 $or$libresoc.v:42517$2122_Y + connect \$762 $or$libresoc.v:42518$2123_Y + connect \$759 $pos$libresoc.v:42519$2125_Y + connect \$765 $and$libresoc.v:42520$2126_Y + connect \$767 $and$libresoc.v:42521$2127_Y + connect \$769 $eq$libresoc.v:42522$2128_Y + connect \$771 $or$libresoc.v:42523$2129_Y + connect \$773 $and$libresoc.v:42524$2130_Y + connect \$775 $and$libresoc.v:42525$2131_Y + connect \$777 $not$libresoc.v:42526$2132_Y + connect \$779 $and$libresoc.v:42527$2133_Y + connect \$781 $and$libresoc.v:42528$2134_Y + connect \$783 $ternary$libresoc.v:42529$2135_Y + connect \$785 $and$libresoc.v:42530$2136_Y + connect \$787 $and$libresoc.v:42531$2137_Y + connect \$789 $not$libresoc.v:42532$2138_Y + connect \$791 $and$libresoc.v:42533$2139_Y + connect \$793 $and$libresoc.v:42534$2140_Y + connect \$795 $ternary$libresoc.v:42535$2141_Y + connect \$797 $and$libresoc.v:42536$2142_Y + connect \$799 $and$libresoc.v:42537$2143_Y + connect \$801 $not$libresoc.v:42538$2144_Y + connect \$803 $and$libresoc.v:42539$2145_Y + connect \$805 $and$libresoc.v:42540$2146_Y + connect \$807 $sub$libresoc.v:42541$2147_Y + connect \$809 $sshl$libresoc.v:42542$2148_Y + connect \$811 $ternary$libresoc.v:42543$2149_Y + connect \$813 $and$libresoc.v:42544$2150_Y + connect \$815 $and$libresoc.v:42545$2151_Y + connect \$817 $not$libresoc.v:42546$2152_Y + connect \$819 $and$libresoc.v:42547$2153_Y + connect \$821 $and$libresoc.v:42548$2154_Y + connect \$823 $sub$libresoc.v:42549$2155_Y + connect \$825 $sshl$libresoc.v:42550$2156_Y + connect \$827 $ternary$libresoc.v:42551$2157_Y + connect \$830 $or$libresoc.v:42552$2158_Y + connect \$832 $and$libresoc.v:42553$2159_Y + connect \$834 $and$libresoc.v:42554$2160_Y + connect \$836 $not$libresoc.v:42555$2161_Y + connect \$838 $and$libresoc.v:42556$2162_Y + connect \$840 $and$libresoc.v:42557$2163_Y + connect \$842 $sub$libresoc.v:42558$2164_Y + connect \$844 $sshl$libresoc.v:42559$2165_Y + connect \$846 $ternary$libresoc.v:42560$2166_Y + connect \$848 $and$libresoc.v:42561$2167_Y + connect \$850 $and$libresoc.v:42562$2168_Y + connect \$852 $not$libresoc.v:42563$2169_Y + connect \$854 $and$libresoc.v:42564$2170_Y + connect \$856 $and$libresoc.v:42565$2171_Y + connect \$858 $sub$libresoc.v:42566$2172_Y + connect \$860 $sshl$libresoc.v:42567$2173_Y + connect \$862 $ternary$libresoc.v:42568$2174_Y + connect \$864 $and$libresoc.v:42569$2175_Y + connect \$866 $and$libresoc.v:42570$2176_Y + connect \$868 $not$libresoc.v:42571$2177_Y + connect \$870 $and$libresoc.v:42572$2178_Y + connect \$872 $and$libresoc.v:42573$2179_Y + connect \$874 $ternary$libresoc.v:42574$2180_Y + connect \$876 $and$libresoc.v:42575$2181_Y + connect \$878 $and$libresoc.v:42576$2182_Y + connect \$880 $not$libresoc.v:42577$2183_Y + connect \$882 $and$libresoc.v:42578$2184_Y + connect \$884 $and$libresoc.v:42579$2185_Y + connect \$886 $ternary$libresoc.v:42580$2186_Y + connect \$888 $and$libresoc.v:42581$2187_Y + connect \$890 $and$libresoc.v:42582$2188_Y + connect \$892 $not$libresoc.v:42583$2189_Y + connect \$894 $and$libresoc.v:42584$2190_Y + connect \$896 $and$libresoc.v:42585$2191_Y + connect \$898 $ternary$libresoc.v:42586$2192_Y + connect \$900 $and$libresoc.v:42587$2193_Y + connect \$902 $and$libresoc.v:42588$2194_Y + connect \$904 $not$libresoc.v:42589$2195_Y + connect \$906 $and$libresoc.v:42590$2196_Y + connect \$908 $and$libresoc.v:42591$2197_Y + connect \$910 $ternary$libresoc.v:42592$2198_Y + connect \$912 $and$libresoc.v:42593$2199_Y + connect \$914 $and$libresoc.v:42594$2200_Y + connect \$916 $not$libresoc.v:42595$2201_Y + connect \$918 $and$libresoc.v:42596$2202_Y + connect \$920 $and$libresoc.v:42597$2203_Y + connect \$922 $ternary$libresoc.v:42598$2204_Y + connect \$924 $or$libresoc.v:42599$2205_Y + connect \$926 $or$libresoc.v:42600$2206_Y + connect \$928 $or$libresoc.v:42601$2207_Y + connect \$930 $or$libresoc.v:42602$2208_Y + connect \$932 $reduce_or$libresoc.v:42603$2209_Y + connect \$934 $and$libresoc.v:42604$2210_Y + connect \$936 $and$libresoc.v:42605$2211_Y + connect \$938 $not$libresoc.v:42606$2212_Y + connect \$940 $and$libresoc.v:42607$2213_Y + connect \$942 $and$libresoc.v:42608$2214_Y + connect \$944 $ternary$libresoc.v:42609$2215_Y + connect \$946 $reduce_or$libresoc.v:42610$2216_Y + connect \$948 $and$libresoc.v:42611$2217_Y + connect \$950 $and$libresoc.v:42612$2218_Y + connect \$952 $and$libresoc.v:42613$2219_Y + connect \$954 $and$libresoc.v:42614$2220_Y + connect \$956 $and$libresoc.v:42615$2221_Y + connect \$958 $and$libresoc.v:42616$2222_Y + connect \$960 $and$libresoc.v:42617$2223_Y + connect \$962 $and$libresoc.v:42618$2224_Y + connect \$964 $and$libresoc.v:42619$2225_Y + connect \$966 $and$libresoc.v:42620$2226_Y + connect \$968 $and$libresoc.v:42621$2227_Y + connect \$970 $and$libresoc.v:42622$2228_Y + connect \$972 $not$libresoc.v:42623$2229_Y + connect \$974 $and$libresoc.v:42624$2230_Y + connect \$980 $and$libresoc.v:42625$2231_Y + connect \$982 $ternary$libresoc.v:42626$2232_Y + connect \$984 $and$libresoc.v:42627$2233_Y + connect \$987 $and$libresoc.v:42628$2234_Y + connect \$991 $not$libresoc.v:42629$2235_Y + connect \$993 $and$libresoc.v:42630$2236_Y + connect \$998 $and$libresoc.v:42631$2237_Y connect \$223 \$224 - connect \$460 \$475 - connect \$575 \$588 - connect \$616 \$617 - connect \$831 \$832 - connect \$1159 \$1176 - connect \$1178 \$1195 - connect \$1375 \$1384 + connect \$580 \$615 + connect \$829 \$830 + connect \$1157 \$1174 + connect \$1176 \$1193 + connect \$1373 \$1382 connect \o_ok 1'0 connect \ea_ok 1'0 - connect \spr_spr1__wen \wp$1813 - connect \spr_spr1__addr$175 \addr_en$1816 [6:0] + connect \spr_spr1__wen \wp$1811 + connect \spr_spr1__addr$175 \addr_en$1814 [3:0] connect \spr_spr1__data_i \fus_dest2_o$162 - connect \addr_en$1816 \$1817 - connect \wp$1813 \$1814 - connect \wr_pick_rise$1059 \$1811 - connect \wr_pick$1805 \$1806 - connect \wrpick_SPR_spr1_i \$1803 - connect \wrflag_spr0_spr1_1 \$1801 - connect \state_wen \$1799 + connect \addr_en$1814 \$1815 + connect \wp$1811 \$1812 + connect \wr_pick_rise$1057 \$1809 + connect \wr_pick$1803 \$1804 + connect \wrpick_SPR_spr1_i \$1801 + connect \wrflag_spr0_spr1_1 \$1799 + connect \state_wen \$1797 connect \state_data_i$174 \fus_dest5_o$161 - connect \addr_en$1796 \$1797 - connect \wp$1793 \$1794 - connect \wr_pick_rise$1019 \$1791 - connect \wr_pick$1785 \$1786 - connect \wrpick_STATE_msr_i \$1783 - connect \wrflag_trap0_msr_4 \$1781 - connect \state_nia_wen \$1777 - connect \state_data_i \$1775 - connect \addr_en$1772 \$1773 - connect \wp$1769 \$1770 - connect \wr_pick_rise$1018 \$1767 - connect \wr_pick$1761 \$1762 - connect \wrflag_trap0_nia_3 \$1759 - connect \addr_en$1756 \$1757 - connect \wp$1753 \$1754 - connect \wr_pick_rise$1644 \$1751 - connect \wr_pick$1745 \$1746 - connect \wrpick_STATE_nia_i [1] \$1743 - connect \wrpick_STATE_nia_i [0] \$1741 - connect \wrflag_branch0_nia_2 \$1739 - connect \fast_dest1__wen \$1737 - connect \fast_dest1__addr \$1729 - connect \fast_dest1__data_i \$1721 - connect \addr_en$1712 \$1713 - connect \wp$1709 \$1710 - connect \wr_pick_rise$1017 \$1707 - connect \wr_pick$1701 \$1702 - connect \wrflag_trap0_fast1_2 \$1699 - connect \addr_en$1696 \$1697 - connect \wp$1693 \$1694 - connect \wr_pick_rise$1643 \$1691 - connect \wr_pick$1685 \$1686 - connect \wrflag_branch0_fast1_1 \$1683 - connect \addr_en$1680 \$1681 - connect \wp$1677 \$1678 - connect \wr_pick_rise$1058 \$1675 - connect \wr_pick$1669 \$1670 - connect \wrflag_spr0_fast1_2 \$1667 - connect \addr_en$1664 \$1665 - connect \wp$1661 \$1662 - connect \wr_pick_rise$1016 \$1659 - connect \wr_pick$1653 \$1654 - connect \wrflag_trap0_fast1_1 \$1651 - connect \addr_en$1648 \$1649 - connect \wp$1645 \$1646 - connect \fus_cu_wr__go_i$149 [2] \wr_pick_rise$1644 - connect \fus_cu_wr__go_i$149 [1] \wr_pick_rise$1643 - connect \fus_cu_wr__go_i$149 [0] \wr_pick_rise$1638 - connect \wr_pick_rise$1638 \$1641 - connect \wr_pick$1634 \$1635 - connect \wrpick_FAST_fast1_i [4] \$1632 - connect \wrpick_FAST_fast1_i [3] \$1630 - connect \wrpick_FAST_fast1_i [2] \$1628 - connect \wrpick_FAST_fast1_i [1] \$1626 - connect \wrpick_FAST_fast1_i [0] \$1624 - connect \wrflag_branch0_fast1_0 \$1622 - connect \xer_wen$173 \$1614 - connect \xer_data_i$172 \$1606 - connect \addr_en$1603 \$1604 - connect \wp$1600 \$1601 - connect \wr_pick_rise$1099 \$1598 - connect \wr_pick$1592 \$1593 - connect \wrflag_mul0_xer_so_3 \$1590 - connect \addr_en$1587 \$1588 - connect \wp$1584 \$1585 - connect \wr_pick_rise$1079 \$1582 - connect \wr_pick$1576 \$1577 - connect \wrflag_div0_xer_so_3 \$1574 - connect \addr_en$1571 \$1572 - connect \wp$1568 \$1569 - connect \wr_pick_rise$1057 \$1566 - connect \wr_pick$1560 \$1561 - connect \wrflag_spr0_xer_so_3 \$1558 - connect \addr_en$1555 \$1556 - connect \wp$1552 \$1553 - connect \wr_pick_rise$981 \$1550 - connect \wr_pick$1544 \$1545 - connect \wrpick_XER_xer_so_i [3] \$1542 - connect \wrpick_XER_xer_so_i [2] \$1540 - connect \wrpick_XER_xer_so_i [1] \$1538 - connect \wrpick_XER_xer_so_i [0] \$1536 - connect \wrflag_alu0_xer_so_4 \$1534 - connect \xer_wen$171 \$1532 - connect \xer_data_i$170 \$1526 - connect \addr_en$1519 \$1520 - connect \wp$1516 \$1517 - connect \wr_pick_rise$1098 \$1514 - connect \wr_pick$1508 \$1509 - connect \wrflag_mul0_xer_ov_2 \$1506 - connect \addr_en$1503 \$1504 - connect \wp$1500 \$1501 - connect \wr_pick_rise$1078 \$1498 - connect \wr_pick$1492 \$1493 - connect \wrflag_div0_xer_ov_2 \$1490 - connect \addr_en$1487 \$1488 - connect \wp$1484 \$1485 - connect \wr_pick_rise$1056 \$1482 - connect \wr_pick$1476 \$1477 - connect \wrflag_spr0_xer_ov_4 \$1474 - connect \addr_en$1471 \$1472 - connect \wp$1468 \$1469 - connect \wr_pick_rise$980 \$1466 - connect \wr_pick$1460 \$1461 - connect \wrpick_XER_xer_ov_i [3] \$1458 - connect \wrpick_XER_xer_ov_i [2] \$1456 - connect \wrpick_XER_xer_ov_i [1] \$1454 - connect \wrpick_XER_xer_ov_i [0] \$1452 - connect \wrflag_alu0_xer_ov_3 \$1450 - connect \xer_wen \$1444 - connect \xer_data_i \$1442 - connect \addr_en$1437 \$1438 - connect \wp$1434 \$1435 - connect \wr_pick_rise$1118 \$1432 - connect \wr_pick$1426 \$1427 - connect \wrflag_shiftrot0_xer_ca_2 \$1424 - connect \addr_en$1421 \$1422 - connect \wp$1418 \$1419 - connect \wr_pick_rise$1055 \$1416 - connect \wr_pick$1410 \$1411 - connect \wrflag_spr0_xer_ca_5 \$1408 - connect \addr_en$1405 \$1406 - connect \wp$1402 \$1403 - connect \wr_pick_rise$979 \$1400 - connect \wr_pick$1394 \$1395 - connect \wrpick_XER_xer_ca_i [2] \$1392 - connect \wrpick_XER_xer_ca_i [1] \$1390 - connect \wrpick_XER_xer_ca_i [0] \$1388 - connect \wrflag_alu0_xer_ca_2 \$1386 - connect \cr_wen \$1384 [7:0] - connect \cr_data_i \$1373 - connect \addr_en$1358 \$1363 - connect \wp$1355 \$1356 - connect \wr_pick_rise$1117 \$1353 - connect \wr_pick$1347 \$1348 - connect \wrflag_shiftrot0_cr_a_1 \$1345 - connect \addr_en$1338 \$1343 - connect \wp$1335 \$1336 - connect \wr_pick_rise$1097 \$1333 - connect \wr_pick$1327 \$1328 - connect \wrflag_mul0_cr_a_1 \$1325 - connect \addr_en$1318 \$1323 - connect \wp$1315 \$1316 - connect \wr_pick_rise$1077 \$1313 - connect \wr_pick$1307 \$1308 - connect \wrflag_div0_cr_a_1 \$1305 - connect \addr_en$1298 \$1303 - connect \wp$1295 \$1296 - connect \wr_pick_rise$1037 \$1293 - connect \wr_pick$1287 \$1288 - connect \wrflag_logical0_cr_a_1 \$1285 - connect \addr_en$1278 \$1283 - connect \wp$1275 \$1276 - connect \wr_pick_rise$998 \$1273 - connect \wr_pick$1267 \$1268 - connect \wrflag_cr0_cr_a_2 \$1265 - connect \addr_en$1258 \$1263 - connect \wp$1255 \$1256 - connect \wr_pick_rise$978 \$1253 - connect \wr_pick$1247 \$1248 - connect \wrpick_CR_cr_a_i [5] \$1245 - connect \wrpick_CR_cr_a_i [4] \$1243 - connect \wrpick_CR_cr_a_i [3] \$1241 - connect \wrpick_CR_cr_a_i [2] \$1239 - connect \wrpick_CR_cr_a_i [1] \$1237 - connect \wrpick_CR_cr_a_i [0] \$1235 - connect \wrflag_alu0_cr_a_1 \$1233 - connect \cr_full_wr__wen \addr_en$1230 + connect \addr_en$1794 \$1795 + connect \wp$1791 \$1792 + connect \wr_pick_rise$1017 \$1789 + connect \wr_pick$1783 \$1784 + connect \wrpick_STATE_msr_i \$1781 + connect \wrflag_trap0_msr_4 \$1779 + connect \state_nia_wen \$1775 + connect \state_data_i \$1773 + connect \addr_en$1770 \$1771 + connect \wp$1767 \$1768 + connect \wr_pick_rise$1016 \$1765 + connect \wr_pick$1759 \$1760 + connect \wrflag_trap0_nia_3 \$1757 + connect \addr_en$1754 \$1755 + connect \wp$1751 \$1752 + connect \wr_pick_rise$1642 \$1749 + connect \wr_pick$1743 \$1744 + connect \wrpick_STATE_nia_i [1] \$1741 + connect \wrpick_STATE_nia_i [0] \$1739 + connect \wrflag_branch0_nia_2 \$1737 + connect \fast_dest1__wen \$1735 + connect \fast_dest1__addr \$1727 + connect \fast_dest1__data_i \$1719 + connect \addr_en$1710 \$1711 + connect \wp$1707 \$1708 + connect \wr_pick_rise$1015 \$1705 + connect \wr_pick$1699 \$1700 + connect \wrflag_trap0_fast1_2 \$1697 + connect \addr_en$1694 \$1695 + connect \wp$1691 \$1692 + connect \wr_pick_rise$1641 \$1689 + connect \wr_pick$1683 \$1684 + connect \wrflag_branch0_fast1_1 \$1681 + connect \addr_en$1678 \$1679 + connect \wp$1675 \$1676 + connect \wr_pick_rise$1056 \$1673 + connect \wr_pick$1667 \$1668 + connect \wrflag_spr0_fast1_2 \$1665 + connect \addr_en$1662 \$1663 + connect \wp$1659 \$1660 + connect \wr_pick_rise$1014 \$1657 + connect \wr_pick$1651 \$1652 + connect \wrflag_trap0_fast1_1 \$1649 + connect \addr_en$1646 \$1647 + connect \wp$1643 \$1644 + connect \fus_cu_wr__go_i$149 [2] \wr_pick_rise$1642 + connect \fus_cu_wr__go_i$149 [1] \wr_pick_rise$1641 + connect \fus_cu_wr__go_i$149 [0] \wr_pick_rise$1636 + connect \wr_pick_rise$1636 \$1639 + connect \wr_pick$1632 \$1633 + connect \wrpick_FAST_fast1_i [4] \$1630 + connect \wrpick_FAST_fast1_i [3] \$1628 + connect \wrpick_FAST_fast1_i [2] \$1626 + connect \wrpick_FAST_fast1_i [1] \$1624 + connect \wrpick_FAST_fast1_i [0] \$1622 + connect \wrflag_branch0_fast1_0 \$1620 + connect \xer_wen$173 \$1612 + connect \xer_data_i$172 \$1604 + connect \addr_en$1601 \$1602 + connect \wp$1598 \$1599 + connect \wr_pick_rise$1097 \$1596 + connect \wr_pick$1590 \$1591 + connect \wrflag_mul0_xer_so_3 \$1588 + connect \addr_en$1585 \$1586 + connect \wp$1582 \$1583 + connect \wr_pick_rise$1077 \$1580 + connect \wr_pick$1574 \$1575 + connect \wrflag_div0_xer_so_3 \$1572 + connect \addr_en$1569 \$1570 + connect \wp$1566 \$1567 + connect \wr_pick_rise$1055 \$1564 + connect \wr_pick$1558 \$1559 + connect \wrflag_spr0_xer_so_3 \$1556 + connect \addr_en$1553 \$1554 + connect \wp$1550 \$1551 + connect \wr_pick_rise$979 \$1548 + connect \wr_pick$1542 \$1543 + connect \wrpick_XER_xer_so_i [3] \$1540 + connect \wrpick_XER_xer_so_i [2] \$1538 + connect \wrpick_XER_xer_so_i [1] \$1536 + connect \wrpick_XER_xer_so_i [0] \$1534 + connect \wrflag_alu0_xer_so_4 \$1532 + connect \xer_wen$171 \$1530 + connect \xer_data_i$170 \$1524 + connect \addr_en$1517 \$1518 + connect \wp$1514 \$1515 + connect \wr_pick_rise$1096 \$1512 + connect \wr_pick$1506 \$1507 + connect \wrflag_mul0_xer_ov_2 \$1504 + connect \addr_en$1501 \$1502 + connect \wp$1498 \$1499 + connect \wr_pick_rise$1076 \$1496 + connect \wr_pick$1490 \$1491 + connect \wrflag_div0_xer_ov_2 \$1488 + connect \addr_en$1485 \$1486 + connect \wp$1482 \$1483 + connect \wr_pick_rise$1054 \$1480 + connect \wr_pick$1474 \$1475 + connect \wrflag_spr0_xer_ov_4 \$1472 + connect \addr_en$1469 \$1470 + connect \wp$1466 \$1467 + connect \wr_pick_rise$978 \$1464 + connect \wr_pick$1458 \$1459 + connect \wrpick_XER_xer_ov_i [3] \$1456 + connect \wrpick_XER_xer_ov_i [2] \$1454 + connect \wrpick_XER_xer_ov_i [1] \$1452 + connect \wrpick_XER_xer_ov_i [0] \$1450 + connect \wrflag_alu0_xer_ov_3 \$1448 + connect \xer_wen \$1442 + connect \xer_data_i \$1440 + connect \addr_en$1435 \$1436 + connect \wp$1432 \$1433 + connect \wr_pick_rise$1116 \$1430 + connect \wr_pick$1424 \$1425 + connect \wrflag_shiftrot0_xer_ca_2 \$1422 + connect \addr_en$1419 \$1420 + connect \wp$1416 \$1417 + connect \wr_pick_rise$1053 \$1414 + connect \wr_pick$1408 \$1409 + connect \wrflag_spr0_xer_ca_5 \$1406 + connect \addr_en$1403 \$1404 + connect \wp$1400 \$1401 + connect \wr_pick_rise$977 \$1398 + connect \wr_pick$1392 \$1393 + connect \wrpick_XER_xer_ca_i [2] \$1390 + connect \wrpick_XER_xer_ca_i [1] \$1388 + connect \wrpick_XER_xer_ca_i [0] \$1386 + connect \wrflag_alu0_xer_ca_2 \$1384 + connect \cr_wen \$1382 [7:0] + connect \cr_data_i \$1371 + connect \addr_en$1356 \$1361 + connect \wp$1353 \$1354 + connect \wr_pick_rise$1115 \$1351 + connect \wr_pick$1345 \$1346 + connect \wrflag_shiftrot0_cr_a_1 \$1343 + connect \addr_en$1336 \$1341 + connect \wp$1333 \$1334 + connect \wr_pick_rise$1095 \$1331 + connect \wr_pick$1325 \$1326 + connect \wrflag_mul0_cr_a_1 \$1323 + connect \addr_en$1316 \$1321 + connect \wp$1313 \$1314 + connect \wr_pick_rise$1075 \$1311 + connect \wr_pick$1305 \$1306 + connect \wrflag_div0_cr_a_1 \$1303 + connect \addr_en$1296 \$1301 + connect \wp$1293 \$1294 + connect \wr_pick_rise$1035 \$1291 + connect \wr_pick$1285 \$1286 + connect \wrflag_logical0_cr_a_1 \$1283 + connect \addr_en$1276 \$1281 + connect \wp$1273 \$1274 + connect \wr_pick_rise$996 \$1271 + connect \wr_pick$1265 \$1266 + connect \wrflag_cr0_cr_a_2 \$1263 + connect \addr_en$1256 \$1261 + connect \wp$1253 \$1254 + connect \wr_pick_rise$976 \$1251 + connect \wr_pick$1245 \$1246 + connect \wrpick_CR_cr_a_i [5] \$1243 + connect \wrpick_CR_cr_a_i [4] \$1241 + connect \wrpick_CR_cr_a_i [3] \$1239 + connect \wrpick_CR_cr_a_i [2] \$1237 + connect \wrpick_CR_cr_a_i [1] \$1235 + connect \wrpick_CR_cr_a_i [0] \$1233 + connect \wrflag_alu0_cr_a_1 \$1231 + connect \cr_full_wr__wen \addr_en$1228 connect \cr_full_wr__data_i \fus_dest2_o - connect \addr_en$1230 \$1231 - connect \wp$1227 \$1228 - connect \wr_pick_rise$997 \$1225 - connect \wr_pick$1219 \$1220 - connect \wrpick_CR_full_cr_i \$1217 - connect \wrflag_cr0_full_cr_1 \$1215 - connect \int_dest1__wen \$1213 - connect \int_dest1__addr \$1195 [4:0] - connect \int_dest1__data_i \$1176 [63:0] - connect \addr_en$1156 \$1157 - connect \wp$1153 \$1154 - connect \wr_pick_rise$1136 \$1151 - connect \wr_pick$1145 \$1146 - connect \wrflag_ldst0_o_1 \$1143 - connect \addr_en$1140 \$1141 - connect \wp$1137 \$1138 - connect \fus_cu_wr__go_i$114 [1] \wr_pick_rise$1136 - connect \fus_cu_wr__go_i$114 [0] \wr_pick_rise$1131 - connect \wr_pick_rise$1131 \$1134 - connect \wr_pick$1127 \$1128 - connect \wrflag_ldst0_o_0 \$1125 - connect \addr_en$1122 \$1123 - connect \wp$1119 \$1120 - connect \fus_cu_wr__go_i$112 [2] \wr_pick_rise$1118 - connect \fus_cu_wr__go_i$112 [1] \wr_pick_rise$1117 - connect \fus_cu_wr__go_i$112 [0] \wr_pick_rise$1112 - connect \wr_pick_rise$1112 \$1115 - connect \wr_pick$1108 \$1109 - connect \wrflag_shiftrot0_o_0 \$1106 - connect \addr_en$1103 \$1104 - connect \wp$1100 \$1101 - connect \fus_cu_wr__go_i$109 [3] \wr_pick_rise$1099 - connect \fus_cu_wr__go_i$109 [2] \wr_pick_rise$1098 - connect \fus_cu_wr__go_i$109 [1] \wr_pick_rise$1097 - connect \fus_cu_wr__go_i$109 [0] \wr_pick_rise$1092 - connect \wr_pick_rise$1092 \$1095 - connect \wr_pick$1088 \$1089 - connect \wrflag_mul0_o_0 \$1086 - connect \addr_en$1083 \$1084 - connect \wp$1080 \$1081 - connect \fus_cu_wr__go_i$106 [3] \wr_pick_rise$1079 - connect \fus_cu_wr__go_i$106 [2] \wr_pick_rise$1078 - connect \fus_cu_wr__go_i$106 [1] \wr_pick_rise$1077 - connect \fus_cu_wr__go_i$106 [0] \wr_pick_rise$1072 - connect \wr_pick_rise$1072 \$1075 - connect \wr_pick$1068 \$1069 - connect \wrflag_div0_o_0 \$1066 - connect \addr_en$1063 \$1064 - connect \wp$1060 \$1061 - connect \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1059 - connect \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1058 - connect \fus_cu_wr__go_i$103 [3] \wr_pick_rise$1057 - connect \fus_cu_wr__go_i$103 [4] \wr_pick_rise$1056 - connect \fus_cu_wr__go_i$103 [5] \wr_pick_rise$1055 - connect \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1050 - connect \wr_pick_rise$1050 \$1053 - connect \wr_pick$1046 \$1047 - connect \wrflag_spr0_o_0 \$1044 - connect \addr_en$1041 \$1042 - connect \wp$1038 \$1039 - connect \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1037 - connect \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1032 - connect \wr_pick_rise$1032 \$1035 - connect \wr_pick$1028 \$1029 - connect \wrflag_logical0_o_0 \$1026 - connect \addr_en$1023 \$1024 - connect \wp$1020 \$1021 - connect \fus_cu_wr__go_i$97 [4] \wr_pick_rise$1019 - connect \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1018 - connect \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1017 - connect \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1016 - connect \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1011 - connect \wr_pick_rise$1011 \$1014 - connect \wr_pick$1007 \$1008 - connect \wrflag_trap0_o_0 \$1005 - connect \addr_en$1002 \$1003 - connect \wp$999 \$1000 - connect \fus_cu_wr__go_i$94 [2] \wr_pick_rise$998 - connect \fus_cu_wr__go_i$94 [1] \wr_pick_rise$997 - connect \fus_cu_wr__go_i$94 [0] \wr_pick_rise$992 - connect \wr_pick_rise$992 \$995 - connect \wr_pick$988 \$989 - connect \wrflag_cr0_o_0 \$986 - connect \addr_en \$984 - connect \wp \$982 - connect \fus_cu_wr__go_i [4] \wr_pick_rise$981 - connect \fus_cu_wr__go_i [3] \wr_pick_rise$980 - connect \fus_cu_wr__go_i [2] \wr_pick_rise$979 - connect \fus_cu_wr__go_i [1] \wr_pick_rise$978 + connect \addr_en$1228 \$1229 + connect \wp$1225 \$1226 + connect \wr_pick_rise$995 \$1223 + connect \wr_pick$1217 \$1218 + connect \wrpick_CR_full_cr_i \$1215 + connect \wrflag_cr0_full_cr_1 \$1213 + connect \int_dest1__wen \$1211 + connect \int_dest1__addr \$1193 [4:0] + connect \int_dest1__data_i \$1174 [63:0] + connect \addr_en$1154 \$1155 + connect \wp$1151 \$1152 + connect \wr_pick_rise$1134 \$1149 + connect \wr_pick$1143 \$1144 + connect \wrflag_ldst0_o_1 \$1141 + connect \addr_en$1138 \$1139 + connect \wp$1135 \$1136 + connect \fus_cu_wr__go_i$114 [1] \wr_pick_rise$1134 + connect \fus_cu_wr__go_i$114 [0] \wr_pick_rise$1129 + connect \wr_pick_rise$1129 \$1132 + connect \wr_pick$1125 \$1126 + connect \wrflag_ldst0_o_0 \$1123 + connect \addr_en$1120 \$1121 + connect \wp$1117 \$1118 + connect \fus_cu_wr__go_i$112 [2] \wr_pick_rise$1116 + connect \fus_cu_wr__go_i$112 [1] \wr_pick_rise$1115 + connect \fus_cu_wr__go_i$112 [0] \wr_pick_rise$1110 + connect \wr_pick_rise$1110 \$1113 + connect \wr_pick$1106 \$1107 + connect \wrflag_shiftrot0_o_0 \$1104 + connect \addr_en$1101 \$1102 + connect \wp$1098 \$1099 + connect \fus_cu_wr__go_i$109 [3] \wr_pick_rise$1097 + connect \fus_cu_wr__go_i$109 [2] \wr_pick_rise$1096 + connect \fus_cu_wr__go_i$109 [1] \wr_pick_rise$1095 + connect \fus_cu_wr__go_i$109 [0] \wr_pick_rise$1090 + connect \wr_pick_rise$1090 \$1093 + connect \wr_pick$1086 \$1087 + connect \wrflag_mul0_o_0 \$1084 + connect \addr_en$1081 \$1082 + connect \wp$1078 \$1079 + connect \fus_cu_wr__go_i$106 [3] \wr_pick_rise$1077 + connect \fus_cu_wr__go_i$106 [2] \wr_pick_rise$1076 + connect \fus_cu_wr__go_i$106 [1] \wr_pick_rise$1075 + connect \fus_cu_wr__go_i$106 [0] \wr_pick_rise$1070 + connect \wr_pick_rise$1070 \$1073 + connect \wr_pick$1066 \$1067 + connect \wrflag_div0_o_0 \$1064 + connect \addr_en$1061 \$1062 + connect \wp$1058 \$1059 + connect \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1057 + connect \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1056 + connect \fus_cu_wr__go_i$103 [3] \wr_pick_rise$1055 + connect \fus_cu_wr__go_i$103 [4] \wr_pick_rise$1054 + connect \fus_cu_wr__go_i$103 [5] \wr_pick_rise$1053 + connect \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1048 + connect \wr_pick_rise$1048 \$1051 + connect \wr_pick$1044 \$1045 + connect \wrflag_spr0_o_0 \$1042 + connect \addr_en$1039 \$1040 + connect \wp$1036 \$1037 + connect \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1035 + connect \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1030 + connect \wr_pick_rise$1030 \$1033 + connect \wr_pick$1026 \$1027 + connect \wrflag_logical0_o_0 \$1024 + connect \addr_en$1021 \$1022 + connect \wp$1018 \$1019 + connect \fus_cu_wr__go_i$97 [4] \wr_pick_rise$1017 + connect \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1016 + connect \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1015 + connect \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1014 + connect \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1009 + connect \wr_pick_rise$1009 \$1012 + connect \wr_pick$1005 \$1006 + connect \wrflag_trap0_o_0 \$1003 + connect \addr_en$1000 \$1001 + connect \wp$997 \$998 + connect \fus_cu_wr__go_i$94 [2] \wr_pick_rise$996 + connect \fus_cu_wr__go_i$94 [1] \wr_pick_rise$995 + connect \fus_cu_wr__go_i$94 [0] \wr_pick_rise$990 + connect \wr_pick_rise$990 \$993 + connect \wr_pick$986 \$987 + connect \wrflag_cr0_o_0 \$984 + connect \addr_en \$982 + connect \wp \$980 + connect \fus_cu_wr__go_i [4] \wr_pick_rise$979 + connect \fus_cu_wr__go_i [3] \wr_pick_rise$978 + connect \fus_cu_wr__go_i [2] \wr_pick_rise$977 + connect \fus_cu_wr__go_i [1] \wr_pick_rise$976 connect \fus_cu_wr__go_i [0] \wr_pick_rise - connect \wr_pick_rise \$976 - connect \wr_pick \$972 - connect \wrpick_INT_o_i [9] \$970 - connect \wrpick_INT_o_i [8] \$968 - connect \wrpick_INT_o_i [7] \$966 - connect \wrpick_INT_o_i [6] \$964 - connect \wrpick_INT_o_i [5] \$962 - connect \wrpick_INT_o_i [4] \$960 - connect \wrpick_INT_o_i [3] \$958 - connect \wrpick_INT_o_i [2] \$956 - connect \wrpick_INT_o_i [1] \$954 - connect \wrpick_INT_o_i [0] \$952 - connect \wrflag_alu0_o_0 \$950 - connect \spr_spr1__ren \$948 - connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] - connect \addr_en_SPR_spr1_spr0_0 \$946 - connect \rp_SPR_spr1_spr0_0 \$944 + connect \wr_pick_rise \$974 + connect \wr_pick \$970 + connect \wrpick_INT_o_i [9] \$968 + connect \wrpick_INT_o_i [8] \$966 + connect \wrpick_INT_o_i [7] \$964 + connect \wrpick_INT_o_i [6] \$962 + connect \wrpick_INT_o_i [5] \$960 + connect \wrpick_INT_o_i [4] \$958 + connect \wrpick_INT_o_i [3] \$956 + connect \wrpick_INT_o_i [2] \$954 + connect \wrpick_INT_o_i [1] \$952 + connect \wrpick_INT_o_i [0] \$950 + connect \wrflag_alu0_o_0 \$948 + connect \spr_spr1__ren \$946 + connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [3:0] + connect \addr_en_SPR_spr1_spr0_0 \$944 + connect \rp_SPR_spr1_spr0_0 \$942 connect \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 - connect \pick_SPR_spr1_spr0_0 \$942 + connect \pick_SPR_spr1_spr0_0 \$940 connect \rdflag_SPR_spr1_0 \core_spr1_ok - connect \fast_src2__ren \$934 - connect \fast_src2__addr \$932 - connect \addr_en_FAST_fast2_trap0_1 \$930 - connect \rp_FAST_fast2_trap0_1 \$928 - connect \pick_FAST_fast2_trap0_1 \$926 - connect \addr_en_FAST_fast2_branch0_0 \$918 - connect \rp_FAST_fast2_branch0_0 \$916 - connect \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1 - connect \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0 - connect \pick_FAST_fast2_branch0_0 \$914 - connect \rdflag_FAST_fast2_0 \core_fast2_ok - connect \fast_src1__ren \$906 - connect \fast_src1__addr \$904 - connect \addr_en_FAST_fast1_spr0_2 \$900 - connect \rp_FAST_fast1_spr0_2 \$898 - connect \pick_FAST_fast1_spr0_2 \$896 - connect \addr_en_FAST_fast1_trap0_1 \$888 - connect \rp_FAST_fast1_trap0_1 \$886 - connect \pick_FAST_fast1_trap0_1 \$884 - connect \addr_en_FAST_fast1_branch0_0 \$876 - connect \rp_FAST_fast1_branch0_0 \$874 + connect \fast_src1__ren \$932 + connect \fast_src1__addr \$930 + connect \addr_en_FAST_fast1_trap0_4 \$922 + connect \rp_FAST_fast1_trap0_4 \$920 + connect \pick_FAST_fast1_trap0_4 \$918 + connect \addr_en_FAST_fast1_branch0_3 \$910 + connect \rp_FAST_fast1_branch0_3 \$908 + connect \pick_FAST_fast1_branch0_3 \$906 + connect \addr_en_FAST_fast1_spr0_2 \$898 + connect \rp_FAST_fast1_spr0_2 \$896 + connect \pick_FAST_fast1_spr0_2 \$894 + connect \addr_en_FAST_fast1_trap0_1 \$886 + connect \rp_FAST_fast1_trap0_1 \$884 + connect \pick_FAST_fast1_trap0_1 \$882 + connect \addr_en_FAST_fast1_branch0_0 \$874 + connect \rp_FAST_fast1_branch0_0 \$872 + connect \rdpick_FAST_fast1_i [4] \pick_FAST_fast1_trap0_4 + connect \rdpick_FAST_fast1_i [3] \pick_FAST_fast1_branch0_3 connect \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 connect \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 connect \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 - connect \pick_FAST_fast1_branch0_0 \$872 + connect \pick_FAST_fast1_branch0_0 \$870 + connect \rdflag_FAST_fast1_1 \core_fast2_ok connect \rdflag_FAST_fast1_0 \core_fast1_ok connect \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] - connect \addr_en_CR_cr_c_cr0_0 \$864 - connect \rp_CR_cr_c_cr0_0 \$858 + connect \addr_en_CR_cr_c_cr0_0 \$862 + connect \rp_CR_cr_c_cr0_0 \$856 connect \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 - connect \pick_CR_cr_c_cr0_0 \$856 + connect \pick_CR_cr_c_cr0_0 \$854 connect \rdflag_CR_cr_c_0 \core_cr_in2_ok$2 connect \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] - connect \addr_en_CR_cr_b_cr0_0 \$848 - connect \rp_CR_cr_b_cr0_0 \$842 + connect \addr_en_CR_cr_b_cr0_0 \$846 + connect \rp_CR_cr_b_cr0_0 \$840 connect \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 - connect \pick_CR_cr_b_cr0_0 \$840 + connect \pick_CR_cr_b_cr0_0 \$838 connect \rdflag_CR_cr_b_0 \core_cr_in2_ok - connect \cr_src1__ren \$832 [7:0] - connect \addr_en_CR_cr_a_branch0_1 \$829 - connect \rp_CR_cr_a_branch0_1 \$823 - connect \fus_cu_rd__go_i$82 [1] \dp_FAST_fast2_branch0_0 + connect \cr_src1__ren \$830 [7:0] + connect \addr_en_CR_cr_a_branch0_1 \$827 + connect \rp_CR_cr_a_branch0_1 \$821 + connect \fus_cu_rd__go_i$82 [1] \dp_FAST_fast1_branch0_3 connect \fus_cu_rd__go_i$82 [0] \dp_FAST_fast1_branch0_0 connect \fus_cu_rd__go_i$82 [2] \dp_CR_cr_a_branch0_1 - connect \pick_CR_cr_a_branch0_1 \$821 - connect \addr_en_CR_cr_a_cr0_0 \$813 - connect \rp_CR_cr_a_cr0_0 \$807 + connect \pick_CR_cr_a_branch0_1 \$819 + connect \addr_en_CR_cr_a_cr0_0 \$811 + connect \rp_CR_cr_a_cr0_0 \$805 connect \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 connect \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 - connect \pick_CR_cr_a_cr0_0 \$805 + connect \pick_CR_cr_a_cr0_0 \$803 connect \rdflag_CR_cr_a_0 \core_cr_in1_ok connect \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 - connect \addr_en_CR_full_cr_cr0_0 \$797 - connect \rp_CR_full_cr_cr0_0 \$795 + connect \addr_en_CR_full_cr_cr0_0 \$795 + connect \rp_CR_full_cr_cr0_0 \$793 connect \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 - connect \pick_CR_full_cr_cr0_0 \$793 + connect \pick_CR_full_cr_cr0_0 \$791 connect \rdflag_CR_full_cr_0 \core_core_cr_rd_ok connect \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 - connect \addr_en_XER_xer_ov_spr0_0 \$785 - connect \rp_XER_xer_ov_spr0_0 \$783 + connect \addr_en_XER_xer_ov_spr0_0 \$783 + connect \rp_XER_xer_ov_spr0_0 \$781 connect \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 - connect \pick_XER_xer_ov_spr0_0 \$781 - connect \rdflag_XER_xer_ov_0 \$773 - connect \xer_src2__ren \$761 - connect \addr_en_XER_xer_ca_shiftrot0_2 \$759 - connect \rp_XER_xer_ca_shiftrot0_2 \$757 - connect \pick_XER_xer_ca_shiftrot0_2 \$755 - connect \addr_en_XER_xer_ca_spr0_1 \$747 - connect \rp_XER_xer_ca_spr0_1 \$745 - connect \pick_XER_xer_ca_spr0_1 \$743 - connect \addr_en_XER_xer_ca_alu0_0 \$735 - connect \rp_XER_xer_ca_alu0_0 \$733 + connect \pick_XER_xer_ov_spr0_0 \$779 + connect \rdflag_XER_xer_ov_0 \$771 + connect \xer_src2__ren \$759 + connect \addr_en_XER_xer_ca_shiftrot0_2 \$757 + connect \rp_XER_xer_ca_shiftrot0_2 \$755 + connect \pick_XER_xer_ca_shiftrot0_2 \$753 + connect \addr_en_XER_xer_ca_spr0_1 \$745 + connect \rp_XER_xer_ca_spr0_1 \$743 + connect \pick_XER_xer_ca_spr0_1 \$741 + connect \addr_en_XER_xer_ca_alu0_0 \$733 + connect \rp_XER_xer_ca_alu0_0 \$731 connect \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 connect \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 connect \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 - connect \pick_XER_xer_ca_alu0_0 \$731 - connect \rdflag_XER_xer_ca_0 \$723 - connect \xer_src1__ren \$705 - connect \addr_en_XER_xer_so_shiftrot0_5 \$703 - connect \rp_XER_xer_so_shiftrot0_5 \$701 - connect \pick_XER_xer_so_shiftrot0_5 \$699 - connect \addr_en_XER_xer_so_mul0_4 \$691 - connect \rp_XER_xer_so_mul0_4 \$689 - connect \pick_XER_xer_so_mul0_4 \$687 - connect \addr_en_XER_xer_so_div0_3 \$679 - connect \rp_XER_xer_so_div0_3 \$677 - connect \pick_XER_xer_so_div0_3 \$675 - connect \addr_en_XER_xer_so_spr0_2 \$667 - connect \rp_XER_xer_so_spr0_2 \$665 - connect \pick_XER_xer_so_spr0_2 \$663 - connect \addr_en_XER_xer_so_logical0_1 \$655 - connect \rp_XER_xer_so_logical0_1 \$653 - connect \pick_XER_xer_so_logical0_1 \$651 - connect \addr_en_XER_xer_so_alu0_0 \$643 - connect \rp_XER_xer_so_alu0_0 \$641 + connect \pick_XER_xer_ca_alu0_0 \$729 + connect \rdflag_XER_xer_ca_0 \$721 + connect \xer_src1__ren \$703 + connect \addr_en_XER_xer_so_shiftrot0_5 \$701 + connect \rp_XER_xer_so_shiftrot0_5 \$699 + connect \pick_XER_xer_so_shiftrot0_5 \$697 + connect \addr_en_XER_xer_so_mul0_4 \$689 + connect \rp_XER_xer_so_mul0_4 \$687 + connect \pick_XER_xer_so_mul0_4 \$685 + connect \addr_en_XER_xer_so_div0_3 \$677 + connect \rp_XER_xer_so_div0_3 \$675 + connect \pick_XER_xer_so_div0_3 \$673 + connect \addr_en_XER_xer_so_spr0_2 \$665 + connect \rp_XER_xer_so_spr0_2 \$663 + connect \pick_XER_xer_so_spr0_2 \$661 + connect \addr_en_XER_xer_so_logical0_1 \$653 + connect \rp_XER_xer_so_logical0_1 \$651 + connect \pick_XER_xer_so_logical0_1 \$649 + connect \addr_en_XER_xer_so_alu0_0 \$641 + connect \rp_XER_xer_so_alu0_0 \$639 connect \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5 connect \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4 connect \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3 connect \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2 connect \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1 connect \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 - connect \pick_XER_xer_so_alu0_0 \$639 - connect \rdflag_XER_xer_so_0 \$631 - connect \int_src3__ren \$619 - connect \int_src3__addr \$617 [4:0] - connect \addr_en_INT_rc_ldst0_1 \$614 - connect \rp_INT_rc_ldst0_1 \$612 - connect \pick_INT_rc_ldst0_1 \$610 - connect \addr_en_INT_rc_shiftrot0_0 \$602 - connect \rp_INT_rc_shiftrot0_0 \$600 - connect \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1 - connect \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0 - connect \pick_INT_rc_shiftrot0_0 \$598 - connect \rdflag_INT_rc_0 \core_reg3_ok - connect \int_src2__ren \$590 - connect \int_src2__addr \$588 [4:0] - connect \addr_en_INT_rb_ldst0_7 \$573 - connect \rp_INT_rb_ldst0_7 \$571 - connect \pick_INT_rb_ldst0_7 \$569 - connect \addr_en_INT_rb_shiftrot0_6 \$561 - connect \rp_INT_rb_shiftrot0_6 \$559 - connect \pick_INT_rb_shiftrot0_6 \$557 - connect \addr_en_INT_rb_mul0_5 \$549 - connect \rp_INT_rb_mul0_5 \$547 - connect \pick_INT_rb_mul0_5 \$545 - connect \addr_en_INT_rb_div0_4 \$537 - connect \rp_INT_rb_div0_4 \$535 - connect \pick_INT_rb_div0_4 \$533 - connect \addr_en_INT_rb_logical0_3 \$525 - connect \rp_INT_rb_logical0_3 \$523 - connect \pick_INT_rb_logical0_3 \$521 - connect \addr_en_INT_rb_trap0_2 \$513 - connect \rp_INT_rb_trap0_2 \$511 - connect \pick_INT_rb_trap0_2 \$509 - connect \addr_en_INT_rb_cr0_1 \$501 - connect \rp_INT_rb_cr0_1 \$499 - connect \pick_INT_rb_cr0_1 \$497 - connect \addr_en_INT_rb_alu0_0 \$489 - connect \rp_INT_rb_alu0_0 \$487 - connect \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7 - connect \rdpick_INT_rb_i [6] \pick_INT_rb_shiftrot0_6 - connect \rdpick_INT_rb_i [5] \pick_INT_rb_mul0_5 - connect \rdpick_INT_rb_i [4] \pick_INT_rb_div0_4 - connect \rdpick_INT_rb_i [3] \pick_INT_rb_logical0_3 - connect \rdpick_INT_rb_i [2] \pick_INT_rb_trap0_2 - connect \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1 - connect \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0 - connect \pick_INT_rb_alu0_0 \$485 - connect \rdflag_INT_rb_0 \core_reg2_ok - connect \int_src1__ren \$477 - connect \int_src1__addr \$475 [4:0] - connect \addr_en_INT_ra_ldst0_8 \$458 - connect \rp_INT_ra_ldst0_8 \$456 - connect \fus_cu_rd__go_i$62 [2] \dp_INT_rc_ldst0_1 - connect \fus_cu_rd__go_i$62 [1] \dp_INT_rb_ldst0_7 - connect \fus_cu_rd__go_i$62 [0] \dp_INT_ra_ldst0_8 - connect \pick_INT_ra_ldst0_8 \$454 - connect \addr_en_INT_ra_shiftrot0_7 \$446 - connect \rp_INT_ra_shiftrot0_7 \$444 - connect \fus_cu_rd__go_i$59 [4] \dp_XER_xer_ca_shiftrot0_2 - connect \fus_cu_rd__go_i$59 [3] \dp_XER_xer_so_shiftrot0_5 - connect \fus_cu_rd__go_i$59 [2] \dp_INT_rc_shiftrot0_0 - connect \fus_cu_rd__go_i$59 [1] \dp_INT_rb_shiftrot0_6 - connect \fus_cu_rd__go_i$59 [0] \dp_INT_ra_shiftrot0_7 - connect \pick_INT_ra_shiftrot0_7 \$442 - connect \addr_en_INT_ra_mul0_6 \$434 - connect \rp_INT_ra_mul0_6 \$432 - connect \fus_cu_rd__go_i$56 [2] \dp_XER_xer_so_mul0_4 - connect \fus_cu_rd__go_i$56 [1] \dp_INT_rb_mul0_5 - connect \fus_cu_rd__go_i$56 [0] \dp_INT_ra_mul0_6 - connect \pick_INT_ra_mul0_6 \$430 - connect \addr_en_INT_ra_div0_5 \$422 - connect \rp_INT_ra_div0_5 \$420 - connect \fus_cu_rd__go_i$53 [2] \dp_XER_xer_so_div0_3 - connect \fus_cu_rd__go_i$53 [1] \dp_INT_rb_div0_4 - connect \fus_cu_rd__go_i$53 [0] \dp_INT_ra_div0_5 - connect \pick_INT_ra_div0_5 \$418 - connect \addr_en_INT_ra_spr0_4 \$410 - connect \rp_INT_ra_spr0_4 \$408 - connect \fus_cu_rd__go_i$50 [1] \dp_SPR_spr1_spr0_0 - connect \fus_cu_rd__go_i$50 [2] \dp_FAST_fast1_spr0_2 - connect \fus_cu_rd__go_i$50 [4] \dp_XER_xer_ov_spr0_0 - connect \fus_cu_rd__go_i$50 [5] \dp_XER_xer_ca_spr0_1 - connect \fus_cu_rd__go_i$50 [3] \dp_XER_xer_so_spr0_2 - connect \fus_cu_rd__go_i$50 [0] \dp_INT_ra_spr0_4 - connect \pick_INT_ra_spr0_4 \$406 - connect \addr_en_INT_ra_logical0_3 \$398 - connect \rp_INT_ra_logical0_3 \$396 + connect \pick_XER_xer_so_alu0_0 \$637 + connect \rdflag_XER_xer_so_0 \$629 + connect \int_src__ren \$617 + connect \int_src__addr \$615 [4:0] + connect \addr_en_INT_rabc_ldst0_18 \$578 + connect \rp_INT_rabc_ldst0_18 \$576 + connect \pick_INT_rabc_ldst0_18 \$574 + connect \addr_en_INT_rabc_shiftrot0_17 \$566 + connect \rp_INT_rabc_shiftrot0_17 \$564 + connect \pick_INT_rabc_shiftrot0_17 \$562 + connect \addr_en_INT_rabc_mul0_16 \$554 + connect \rp_INT_rabc_mul0_16 \$552 + connect \pick_INT_rabc_mul0_16 \$550 + connect \addr_en_INT_rabc_div0_15 \$542 + connect \rp_INT_rabc_div0_15 \$540 + connect \pick_INT_rabc_div0_15 \$538 + connect \addr_en_INT_rabc_spr0_14 \$530 + connect \rp_INT_rabc_spr0_14 \$528 + connect \fus_cu_rd__go_i$66 [1] \dp_SPR_spr1_spr0_0 + connect \fus_cu_rd__go_i$66 [2] \dp_FAST_fast1_spr0_2 + connect \fus_cu_rd__go_i$66 [4] \dp_XER_xer_ov_spr0_0 + connect \fus_cu_rd__go_i$66 [5] \dp_XER_xer_ca_spr0_1 + connect \fus_cu_rd__go_i$66 [3] \dp_XER_xer_so_spr0_2 + connect \fus_cu_rd__go_i$66 [0] \dp_INT_rabc_spr0_14 + connect \pick_INT_rabc_spr0_14 \$526 + connect \addr_en_INT_rabc_logical0_13 \$518 + connect \rp_INT_rabc_logical0_13 \$516 + connect \pick_INT_rabc_logical0_13 \$514 + connect \addr_en_INT_rabc_trap0_12 \$506 + connect \rp_INT_rabc_trap0_12 \$504 + connect \pick_INT_rabc_trap0_12 \$502 + connect \addr_en_INT_rabc_cr0_11 \$494 + connect \rp_INT_rabc_cr0_11 \$492 + connect \pick_INT_rabc_cr0_11 \$490 + connect \addr_en_INT_rabc_alu0_10 \$482 + connect \rp_INT_rabc_alu0_10 \$480 + connect \pick_INT_rabc_alu0_10 \$478 + connect \addr_en_INT_rabc_ldst0_9 \$470 + connect \rp_INT_rabc_ldst0_9 \$468 + connect \pick_INT_rabc_ldst0_9 \$466 + connect \addr_en_INT_rabc_shiftrot0_8 \$458 + connect \rp_INT_rabc_shiftrot0_8 \$456 + connect \pick_INT_rabc_shiftrot0_8 \$454 + connect \addr_en_INT_rabc_ldst0_7 \$446 + connect \rp_INT_rabc_ldst0_7 \$444 + connect \fus_cu_rd__go_i$59 [0] \dp_INT_rabc_ldst0_18 + connect \fus_cu_rd__go_i$59 [2] \dp_INT_rabc_ldst0_9 + connect \fus_cu_rd__go_i$59 [1] \dp_INT_rabc_ldst0_7 + connect \pick_INT_rabc_ldst0_7 \$442 + connect \addr_en_INT_rabc_shiftrot0_6 \$434 + connect \rp_INT_rabc_shiftrot0_6 \$432 + connect \fus_cu_rd__go_i$56 [4] \dp_XER_xer_ca_shiftrot0_2 + connect \fus_cu_rd__go_i$56 [3] \dp_XER_xer_so_shiftrot0_5 + connect \fus_cu_rd__go_i$56 [0] \dp_INT_rabc_shiftrot0_17 + connect \fus_cu_rd__go_i$56 [2] \dp_INT_rabc_shiftrot0_8 + connect \fus_cu_rd__go_i$56 [1] \dp_INT_rabc_shiftrot0_6 + connect \pick_INT_rabc_shiftrot0_6 \$430 + connect \addr_en_INT_rabc_mul0_5 \$422 + connect \rp_INT_rabc_mul0_5 \$420 + connect \fus_cu_rd__go_i$53 [2] \dp_XER_xer_so_mul0_4 + connect \fus_cu_rd__go_i$53 [0] \dp_INT_rabc_mul0_16 + connect \fus_cu_rd__go_i$53 [1] \dp_INT_rabc_mul0_5 + connect \pick_INT_rabc_mul0_5 \$418 + connect \addr_en_INT_rabc_div0_4 \$410 + connect \rp_INT_rabc_div0_4 \$408 + connect \fus_cu_rd__go_i$50 [2] \dp_XER_xer_so_div0_3 + connect \fus_cu_rd__go_i$50 [0] \dp_INT_rabc_div0_15 + connect \fus_cu_rd__go_i$50 [1] \dp_INT_rabc_div0_4 + connect \pick_INT_rabc_div0_4 \$406 + connect \addr_en_INT_rabc_logical0_3 \$398 + connect \rp_INT_rabc_logical0_3 \$396 connect \fus_cu_rd__go_i$47 [2] \dp_XER_xer_so_logical0_1 - connect \fus_cu_rd__go_i$47 [1] \dp_INT_rb_logical0_3 - connect \fus_cu_rd__go_i$47 [0] \dp_INT_ra_logical0_3 - connect \pick_INT_ra_logical0_3 \$394 - connect \addr_en_INT_ra_trap0_2 \$386 - connect \rp_INT_ra_trap0_2 \$384 - connect \fus_cu_rd__go_i$44 [3] \dp_FAST_fast2_trap0_1 + connect \fus_cu_rd__go_i$47 [0] \dp_INT_rabc_logical0_13 + connect \fus_cu_rd__go_i$47 [1] \dp_INT_rabc_logical0_3 + connect \pick_INT_rabc_logical0_3 \$394 + connect \addr_en_INT_rabc_trap0_2 \$386 + connect \rp_INT_rabc_trap0_2 \$384 + connect \fus_cu_rd__go_i$44 [3] \dp_FAST_fast1_trap0_4 connect \fus_cu_rd__go_i$44 [2] \dp_FAST_fast1_trap0_1 - connect \fus_cu_rd__go_i$44 [1] \dp_INT_rb_trap0_2 - connect \fus_cu_rd__go_i$44 [0] \dp_INT_ra_trap0_2 - connect \pick_INT_ra_trap0_2 \$382 - connect \addr_en_INT_ra_cr0_1 \$374 - connect \rp_INT_ra_cr0_1 \$372 + connect \fus_cu_rd__go_i$44 [0] \dp_INT_rabc_trap0_12 + connect \fus_cu_rd__go_i$44 [1] \dp_INT_rabc_trap0_2 + connect \pick_INT_rabc_trap0_2 \$382 + connect \addr_en_INT_rabc_cr0_1 \$374 + connect \rp_INT_rabc_cr0_1 \$372 connect \fus_cu_rd__go_i$41 [5] \dp_CR_cr_c_cr0_0 connect \fus_cu_rd__go_i$41 [4] \dp_CR_cr_b_cr0_0 connect \fus_cu_rd__go_i$41 [3] \dp_CR_cr_a_cr0_0 connect \fus_cu_rd__go_i$41 [2] \dp_CR_full_cr_cr0_0 - connect \fus_cu_rd__go_i$41 [1] \dp_INT_rb_cr0_1 - connect \fus_cu_rd__go_i$41 [0] \dp_INT_ra_cr0_1 - connect \pick_INT_ra_cr0_1 \$370 - connect \addr_en_INT_ra_alu0_0 \$362 - connect \rp_INT_ra_alu0_0 \$360 + connect \fus_cu_rd__go_i$41 [0] \dp_INT_rabc_cr0_11 + connect \fus_cu_rd__go_i$41 [1] \dp_INT_rabc_cr0_1 + connect \pick_INT_rabc_cr0_1 \$370 + connect \addr_en_INT_rabc_alu0_0 \$362 + connect \rp_INT_rabc_alu0_0 \$360 connect \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 connect \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0 - connect \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0 - connect \fus_cu_rd__go_i [0] \dp_INT_ra_alu0_0 - connect \rdpick_INT_ra_i [8] \pick_INT_ra_ldst0_8 - connect \rdpick_INT_ra_i [7] \pick_INT_ra_shiftrot0_7 - connect \rdpick_INT_ra_i [6] \pick_INT_ra_mul0_6 - connect \rdpick_INT_ra_i [5] \pick_INT_ra_div0_5 - connect \rdpick_INT_ra_i [4] \pick_INT_ra_spr0_4 - connect \rdpick_INT_ra_i [3] \pick_INT_ra_logical0_3 - connect \rdpick_INT_ra_i [2] \pick_INT_ra_trap0_2 - connect \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1 - connect \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0 - connect \pick_INT_ra_alu0_0 \$358 - connect \rdflag_INT_ra_0 \core_reg1_ok + connect \fus_cu_rd__go_i [0] \dp_INT_rabc_alu0_10 + connect \fus_cu_rd__go_i [1] \dp_INT_rabc_alu0_0 + connect \rdpick_INT_rabc_i [18] \pick_INT_rabc_ldst0_18 + connect \rdpick_INT_rabc_i [17] \pick_INT_rabc_shiftrot0_17 + connect \rdpick_INT_rabc_i [16] \pick_INT_rabc_mul0_16 + connect \rdpick_INT_rabc_i [15] \pick_INT_rabc_div0_15 + connect \rdpick_INT_rabc_i [14] \pick_INT_rabc_spr0_14 + connect \rdpick_INT_rabc_i [13] \pick_INT_rabc_logical0_13 + connect \rdpick_INT_rabc_i [12] \pick_INT_rabc_trap0_12 + connect \rdpick_INT_rabc_i [11] \pick_INT_rabc_cr0_11 + connect \rdpick_INT_rabc_i [10] \pick_INT_rabc_alu0_10 + connect \rdpick_INT_rabc_i [9] \pick_INT_rabc_ldst0_9 + connect \rdpick_INT_rabc_i [8] \pick_INT_rabc_shiftrot0_8 + connect \rdpick_INT_rabc_i [7] \pick_INT_rabc_ldst0_7 + connect \rdpick_INT_rabc_i [6] \pick_INT_rabc_shiftrot0_6 + connect \rdpick_INT_rabc_i [5] \pick_INT_rabc_mul0_5 + connect \rdpick_INT_rabc_i [4] \pick_INT_rabc_div0_4 + connect \rdpick_INT_rabc_i [3] \pick_INT_rabc_logical0_3 + connect \rdpick_INT_rabc_i [2] \pick_INT_rabc_trap0_2 + connect \rdpick_INT_rabc_i [1] \pick_INT_rabc_cr0_1 + connect \rdpick_INT_rabc_i [0] \pick_INT_rabc_alu0_0 + connect \pick_INT_rabc_alu0_0 \$358 + connect \rdflag_INT_rabc_2 \core_reg1_ok + connect \rdflag_INT_rabc_1 \core_reg3_ok + connect \rdflag_INT_rabc_0 \core_reg2_ok connect \en_ldst0 \$217 connect \en_shiftrot0 \$213 connect \en_mul0 \$209 @@ -85800,125 +85566,97 @@ module \core connect \dec_ALU_bigendian \bigendian_i connect \dec_ALU_raw_opcode_in \raw_insn_i end -attribute \src "libresoc.v:49145.1-49881.10" +attribute \src "libresoc.v:48921.1-49554.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr" attribute \generator "nMigen" module \cr - attribute \src "libresoc.v:49840.3-49849.6" - wire width 4 $0\cr_pred__data_o[3:0] - attribute \src "libresoc.v:49146.7-49146.20" + attribute \src "libresoc.v:48922.7-48922.20" wire $0\initial[0:0] - attribute \src "libresoc.v:49774.3-49782.6" - wire width 8 $0\ren_delay$17$next[7:0]$3056 - attribute \src "libresoc.v:49594.3-49595.43" - wire width 8 $0\ren_delay$17[7:0]$3053 - attribute \src "libresoc.v:49526.13-49526.35" - wire width 8 $0\ren_delay$17[7:0]$3074 - attribute \src "libresoc.v:49793.3-49801.6" - wire width 8 $0\ren_delay$34$next[7:0]$3060 - attribute \src "libresoc.v:49592.3-49593.43" - wire width 8 $0\ren_delay$34[7:0]$3051 - attribute \src "libresoc.v:49530.13-49530.35" - wire width 8 $0\ren_delay$34[7:0]$3076 - attribute \src "libresoc.v:49812.3-49820.6" - wire width 8 $0\ren_delay$51$next[7:0]$3064 - attribute \src "libresoc.v:49590.3-49591.43" - wire width 8 $0\ren_delay$51[7:0]$3049 - attribute \src "libresoc.v:49534.13-49534.35" - wire width 8 $0\ren_delay$51[7:0]$3078 - attribute \src "libresoc.v:49831.3-49839.6" - wire width 8 $0\ren_delay$next[7:0]$3068 - attribute \src "libresoc.v:49596.3-49597.35" + attribute \src "libresoc.v:49468.3-49476.6" + wire width 8 $0\ren_delay$17$next[7:0]$3046 + attribute \src "libresoc.v:49304.3-49305.43" + wire width 8 $0\ren_delay$17[7:0]$3043 + attribute \src "libresoc.v:49250.13-49250.35" + wire width 8 $0\ren_delay$17[7:0]$3060 + attribute \src "libresoc.v:49487.3-49495.6" + wire width 8 $0\ren_delay$34$next[7:0]$3050 + attribute \src "libresoc.v:49302.3-49303.43" + wire width 8 $0\ren_delay$34[7:0]$3041 + attribute \src "libresoc.v:49254.13-49254.35" + wire width 8 $0\ren_delay$34[7:0]$3062 + attribute \src "libresoc.v:49506.3-49514.6" + wire width 8 $0\ren_delay$next[7:0]$3054 + attribute \src "libresoc.v:49306.3-49307.35" wire width 8 $0\ren_delay[7:0] - attribute \src "libresoc.v:49783.3-49792.6" + attribute \src "libresoc.v:49515.3-49524.6" wire width 4 $0\src1__data_o[3:0] - attribute \src "libresoc.v:49802.3-49811.6" + attribute \src "libresoc.v:49477.3-49486.6" wire width 4 $0\src2__data_o[3:0] - attribute \src "libresoc.v:49821.3-49830.6" + attribute \src "libresoc.v:49496.3-49505.6" wire width 4 $0\src3__data_o[3:0] - attribute \src "libresoc.v:49840.3-49849.6" - wire width 4 $1\cr_pred__data_o[3:0] - attribute \src "libresoc.v:49774.3-49782.6" - wire width 8 $1\ren_delay$17$next[7:0]$3057 - attribute \src "libresoc.v:49793.3-49801.6" - wire width 8 $1\ren_delay$34$next[7:0]$3061 - attribute \src "libresoc.v:49812.3-49820.6" - wire width 8 $1\ren_delay$51$next[7:0]$3065 - attribute \src "libresoc.v:49831.3-49839.6" - wire width 8 $1\ren_delay$next[7:0]$3069 - attribute \src "libresoc.v:49524.13-49524.30" + attribute \src "libresoc.v:49468.3-49476.6" + wire width 8 $1\ren_delay$17$next[7:0]$3047 + attribute \src "libresoc.v:49487.3-49495.6" + wire width 8 $1\ren_delay$34$next[7:0]$3051 + attribute \src "libresoc.v:49506.3-49514.6" + wire width 8 $1\ren_delay$next[7:0]$3055 + attribute \src "libresoc.v:49248.13-49248.30" wire width 8 $1\ren_delay[7:0] - attribute \src "libresoc.v:49783.3-49792.6" + attribute \src "libresoc.v:49515.3-49524.6" wire width 4 $1\src1__data_o[3:0] - attribute \src "libresoc.v:49802.3-49811.6" + attribute \src "libresoc.v:49477.3-49486.6" wire width 4 $1\src2__data_o[3:0] - attribute \src "libresoc.v:49821.3-49830.6" + attribute \src "libresoc.v:49496.3-49505.6" wire width 4 $1\src3__data_o[3:0] - attribute \src "libresoc.v:49558.17-49558.131" - wire width 4 $or$libresoc.v:49558$3016_Y - attribute \src "libresoc.v:49559.18-49559.132" - wire width 4 $or$libresoc.v:49559$3017_Y - attribute \src "libresoc.v:49560.18-49560.96" - wire width 4 $or$libresoc.v:49560$3018_Y - attribute \src "libresoc.v:49561.18-49561.96" - wire width 4 $or$libresoc.v:49561$3019_Y - attribute \src "libresoc.v:49564.18-49564.126" - wire width 4 $or$libresoc.v:49564$3022_Y - attribute \src "libresoc.v:49565.18-49565.126" - wire width 4 $or$libresoc.v:49565$3023_Y - attribute \src "libresoc.v:49566.18-49566.97" - wire width 4 $or$libresoc.v:49566$3024_Y - attribute \src "libresoc.v:49567.18-49567.126" - wire width 4 $or$libresoc.v:49567$3025_Y - attribute \src "libresoc.v:49568.18-49568.126" - wire width 4 $or$libresoc.v:49568$3026_Y - attribute \src "libresoc.v:49569.18-49569.97" - wire width 4 $or$libresoc.v:49569$3027_Y - attribute \src "libresoc.v:49570.18-49570.97" - wire width 4 $or$libresoc.v:49570$3028_Y - attribute \src "libresoc.v:49572.18-49572.126" - wire width 4 $or$libresoc.v:49572$3030_Y - attribute \src "libresoc.v:49573.17-49573.131" - wire width 4 $or$libresoc.v:49573$3031_Y - attribute \src "libresoc.v:49574.18-49574.126" - wire width 4 $or$libresoc.v:49574$3032_Y - attribute \src "libresoc.v:49575.18-49575.97" - wire width 4 $or$libresoc.v:49575$3033_Y - attribute \src "libresoc.v:49576.18-49576.126" - wire width 4 $or$libresoc.v:49576$3034_Y - attribute \src "libresoc.v:49577.18-49577.126" - wire width 4 $or$libresoc.v:49577$3035_Y - attribute \src "libresoc.v:49578.18-49578.97" - wire width 4 $or$libresoc.v:49578$3036_Y - attribute \src "libresoc.v:49579.18-49579.97" - wire width 4 $or$libresoc.v:49579$3037_Y - attribute \src "libresoc.v:49581.18-49581.126" - wire width 4 $or$libresoc.v:49581$3039_Y - attribute \src "libresoc.v:49582.18-49582.126" - wire width 4 $or$libresoc.v:49582$3040_Y - attribute \src "libresoc.v:49583.18-49583.97" - wire width 4 $or$libresoc.v:49583$3041_Y - attribute \src "libresoc.v:49584.17-49584.131" - wire width 4 $or$libresoc.v:49584$3042_Y - attribute \src "libresoc.v:49585.18-49585.126" - wire width 4 $or$libresoc.v:49585$3043_Y - attribute \src "libresoc.v:49586.18-49586.126" - wire width 4 $or$libresoc.v:49586$3044_Y - attribute \src "libresoc.v:49587.18-49587.97" - wire width 4 $or$libresoc.v:49587$3045_Y - attribute \src "libresoc.v:49588.18-49588.97" - wire width 4 $or$libresoc.v:49588$3046_Y - attribute \src "libresoc.v:49589.17-49589.94" - wire width 4 $or$libresoc.v:49589$3047_Y - attribute \src "libresoc.v:49562.18-49562.100" - wire $reduce_or$libresoc.v:49562$3020_Y - attribute \src "libresoc.v:49563.17-49563.95" - wire $reduce_or$libresoc.v:49563$3021_Y - attribute \src "libresoc.v:49571.18-49571.100" - wire $reduce_or$libresoc.v:49571$3029_Y - attribute \src "libresoc.v:49580.18-49580.100" - wire $reduce_or$libresoc.v:49580$3038_Y + attribute \src "libresoc.v:49278.17-49278.125" + wire width 4 $or$libresoc.v:49278$3016_Y + attribute \src "libresoc.v:49279.18-49279.126" + wire width 4 $or$libresoc.v:49279$3017_Y + attribute \src "libresoc.v:49280.18-49280.96" + wire width 4 $or$libresoc.v:49280$3018_Y + attribute \src "libresoc.v:49281.18-49281.96" + wire width 4 $or$libresoc.v:49281$3019_Y + attribute \src "libresoc.v:49284.18-49284.126" + wire width 4 $or$libresoc.v:49284$3022_Y + attribute \src "libresoc.v:49285.18-49285.126" + wire width 4 $or$libresoc.v:49285$3023_Y + attribute \src "libresoc.v:49286.18-49286.97" + wire width 4 $or$libresoc.v:49286$3024_Y + attribute \src "libresoc.v:49287.18-49287.126" + wire width 4 $or$libresoc.v:49287$3025_Y + attribute \src "libresoc.v:49288.18-49288.126" + wire width 4 $or$libresoc.v:49288$3026_Y + attribute \src "libresoc.v:49289.18-49289.97" + wire width 4 $or$libresoc.v:49289$3027_Y + attribute \src "libresoc.v:49290.18-49290.97" + wire width 4 $or$libresoc.v:49290$3028_Y + attribute \src "libresoc.v:49292.18-49292.126" + wire width 4 $or$libresoc.v:49292$3030_Y + attribute \src "libresoc.v:49293.17-49293.125" + wire width 4 $or$libresoc.v:49293$3031_Y + attribute \src "libresoc.v:49294.18-49294.126" + wire width 4 $or$libresoc.v:49294$3032_Y + attribute \src "libresoc.v:49295.18-49295.97" + wire width 4 $or$libresoc.v:49295$3033_Y + attribute \src "libresoc.v:49296.18-49296.126" + wire width 4 $or$libresoc.v:49296$3034_Y + attribute \src "libresoc.v:49297.18-49297.126" + wire width 4 $or$libresoc.v:49297$3035_Y + attribute \src "libresoc.v:49298.18-49298.97" + wire width 4 $or$libresoc.v:49298$3036_Y + attribute \src "libresoc.v:49299.18-49299.97" + wire width 4 $or$libresoc.v:49299$3037_Y + attribute \src "libresoc.v:49300.17-49300.125" + wire width 4 $or$libresoc.v:49300$3038_Y + attribute \src "libresoc.v:49301.17-49301.94" + wire width 4 $or$libresoc.v:49301$3039_Y + attribute \src "libresoc.v:49282.18-49282.100" + wire $reduce_or$libresoc.v:49282$3020_Y + attribute \src "libresoc.v:49283.17-49283.95" + wire $reduce_or$libresoc.v:49283$3021_Y + attribute \src "libresoc.v:49291.18-49291.100" + wire $reduce_or$libresoc.v:49291$3029_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -85963,38 +85701,18 @@ module \cr wire width 4 \$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire \$52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - wire width 4 \$54 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - wire width 4 \$56 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - wire width 4 \$58 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - wire width 4 \$60 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - wire width 4 \$62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - wire width 4 \$64 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - wire width 4 \$66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \cr_pred__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 8 \cr_pred__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 14 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \data_i$69 + wire width 4 \data_i$52 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 output 3 \full_rd2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" @@ -86007,13 +85725,9 @@ module \cr wire width 32 input 12 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 13 \full_wr__wen - attribute \src "libresoc.v:49146.7-49146.15" + attribute \src "libresoc.v:48922.7-48922.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \reg_0_cr_pred0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire \reg_0_cr_pred0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_dest10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_dest10__wen @@ -86046,10 +85760,6 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_w0__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \reg_1_cr_pred1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire \reg_1_cr_pred1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_dest11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_dest11__wen @@ -86082,10 +85792,6 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_w1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \reg_2_cr_pred2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire \reg_2_cr_pred2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_dest12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_dest12__wen @@ -86118,10 +85824,6 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_w2__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \reg_3_cr_pred3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire \reg_3_cr_pred3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_dest13__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_dest13__wen @@ -86154,10 +85856,6 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_w3__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \reg_4_cr_pred4__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire \reg_4_cr_pred4__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_dest14__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_dest14__wen @@ -86190,10 +85888,6 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_w4__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \reg_5_cr_pred5__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire \reg_5_cr_pred5__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_dest15__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_dest15__wen @@ -86226,10 +85920,6 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_w5__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \reg_6_cr_pred6__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire \reg_6_cr_pred6__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_dest16__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_dest16__wen @@ -86262,10 +85952,6 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_w6__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \reg_7_cr_pred7__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire \reg_7_cr_pred7__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_dest17__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_dest17__wen @@ -86308,10 +85994,6 @@ module \cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$34$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 8 \ren_delay$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 8 \ren_delay$51$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 6 \src1__data_o @@ -86328,31 +86010,31 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 15 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 8 \wen$68 + wire width 8 \wen$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49558$3016 + cell $or $or$libresoc.v:49278$3016 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_4_cr_pred4__data_o - connect \B \reg_5_cr_pred5__data_o - connect \Y $or$libresoc.v:49558$3016_Y + connect \A \reg_4_src14__data_o + connect \B \reg_5_src15__data_o + connect \Y $or$libresoc.v:49278$3016_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49559$3017 + cell $or $or$libresoc.v:49279$3017 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_6_cr_pred6__data_o - connect \B \reg_7_cr_pred7__data_o - connect \Y $or$libresoc.v:49559$3017_Y + connect \A \reg_6_src16__data_o + connect \B \reg_7_src17__data_o + connect \Y $or$libresoc.v:49279$3017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49560$3018 + cell $or $or$libresoc.v:49280$3018 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86360,10 +86042,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:49560$3018_Y + connect \Y $or$libresoc.v:49280$3018_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49561$3019 + cell $or $or$libresoc.v:49281$3019 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86371,32 +86053,32 @@ module \cr parameter \Y_WIDTH 4 connect \A \$7 connect \B \$13 - connect \Y $or$libresoc.v:49561$3019_Y + connect \Y $or$libresoc.v:49281$3019_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49564$3022 + cell $or $or$libresoc.v:49284$3022 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_0_src10__data_o - connect \B \reg_1_src11__data_o - connect \Y $or$libresoc.v:49564$3022_Y + connect \A \reg_0_src20__data_o + connect \B \reg_1_src21__data_o + connect \Y $or$libresoc.v:49284$3022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49565$3023 + cell $or $or$libresoc.v:49285$3023 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_2_src12__data_o - connect \B \reg_3_src13__data_o - connect \Y $or$libresoc.v:49565$3023_Y + connect \A \reg_2_src22__data_o + connect \B \reg_3_src23__data_o + connect \Y $or$libresoc.v:49285$3023_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49566$3024 + cell $or $or$libresoc.v:49286$3024 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86404,32 +86086,32 @@ module \cr parameter \Y_WIDTH 4 connect \A \$20 connect \B \$22 - connect \Y $or$libresoc.v:49566$3024_Y + connect \Y $or$libresoc.v:49286$3024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49567$3025 + cell $or $or$libresoc.v:49287$3025 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_4_src14__data_o - connect \B \reg_5_src15__data_o - connect \Y $or$libresoc.v:49567$3025_Y + connect \A \reg_4_src24__data_o + connect \B \reg_5_src25__data_o + connect \Y $or$libresoc.v:49287$3025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49568$3026 + cell $or $or$libresoc.v:49288$3026 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_6_src16__data_o - connect \B \reg_7_src17__data_o - connect \Y $or$libresoc.v:49568$3026_Y + connect \A \reg_6_src26__data_o + connect \B \reg_7_src27__data_o + connect \Y $or$libresoc.v:49288$3026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49569$3027 + cell $or $or$libresoc.v:49289$3027 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86437,10 +86119,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:49569$3027_Y + connect \Y $or$libresoc.v:49289$3027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49570$3028 + cell $or $or$libresoc.v:49290$3028 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86448,43 +86130,43 @@ module \cr parameter \Y_WIDTH 4 connect \A \$24 connect \B \$30 - connect \Y $or$libresoc.v:49570$3028_Y + connect \Y $or$libresoc.v:49290$3028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49572$3030 + cell $or $or$libresoc.v:49292$3030 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_0_src20__data_o - connect \B \reg_1_src21__data_o - connect \Y $or$libresoc.v:49572$3030_Y + connect \A \reg_0_src30__data_o + connect \B \reg_1_src31__data_o + connect \Y $or$libresoc.v:49292$3030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49573$3031 + cell $or $or$libresoc.v:49293$3031 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_0_cr_pred0__data_o - connect \B \reg_1_cr_pred1__data_o - connect \Y $or$libresoc.v:49573$3031_Y + connect \A \reg_0_src10__data_o + connect \B \reg_1_src11__data_o + connect \Y $or$libresoc.v:49293$3031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49574$3032 + cell $or $or$libresoc.v:49294$3032 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_2_src22__data_o - connect \B \reg_3_src23__data_o - connect \Y $or$libresoc.v:49574$3032_Y + connect \A \reg_2_src32__data_o + connect \B \reg_3_src33__data_o + connect \Y $or$libresoc.v:49294$3032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49575$3033 + cell $or $or$libresoc.v:49295$3033 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86492,32 +86174,32 @@ module \cr parameter \Y_WIDTH 4 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:49575$3033_Y + connect \Y $or$libresoc.v:49295$3033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49576$3034 + cell $or $or$libresoc.v:49296$3034 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_4_src24__data_o - connect \B \reg_5_src25__data_o - connect \Y $or$libresoc.v:49576$3034_Y + connect \A \reg_4_src34__data_o + connect \B \reg_5_src35__data_o + connect \Y $or$libresoc.v:49296$3034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49577$3035 + cell $or $or$libresoc.v:49297$3035 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_6_src26__data_o - connect \B \reg_7_src27__data_o - connect \Y $or$libresoc.v:49577$3035_Y + connect \A \reg_6_src36__data_o + connect \B \reg_7_src37__data_o + connect \Y $or$libresoc.v:49297$3035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49578$3036 + cell $or $or$libresoc.v:49298$3036 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86525,10 +86207,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$43 connect \B \$45 - connect \Y $or$libresoc.v:49578$3036_Y + connect \Y $or$libresoc.v:49298$3036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49579$3037 + cell $or $or$libresoc.v:49299$3037 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86536,98 +86218,21 @@ module \cr parameter \Y_WIDTH 4 connect \A \$41 connect \B \$47 - connect \Y $or$libresoc.v:49579$3037_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49581$3039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_0_src30__data_o - connect \B \reg_1_src31__data_o - connect \Y $or$libresoc.v:49581$3039_Y + connect \Y $or$libresoc.v:49299$3037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49582$3040 + cell $or $or$libresoc.v:49300$3038 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_2_src32__data_o - connect \B \reg_3_src33__data_o - connect \Y $or$libresoc.v:49582$3040_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49583$3041 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$54 - connect \B \$56 - connect \Y $or$libresoc.v:49583$3041_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49584$3042 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_2_cr_pred2__data_o - connect \B \reg_3_cr_pred3__data_o - connect \Y $or$libresoc.v:49584$3042_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49585$3043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_4_src34__data_o - connect \B \reg_5_src35__data_o - connect \Y $or$libresoc.v:49585$3043_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49586$3044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_6_src36__data_o - connect \B \reg_7_src37__data_o - connect \Y $or$libresoc.v:49586$3044_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49587$3045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$60 - connect \B \$62 - connect \Y $or$libresoc.v:49587$3045_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49588$3046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$58 - connect \B \$64 - connect \Y $or$libresoc.v:49588$3046_Y + connect \A \reg_2_src12__data_o + connect \B \reg_3_src13__data_o + connect \Y $or$libresoc.v:49300$3038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49589$3047 + cell $or $or$libresoc.v:49301$3039 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86635,47 +86240,37 @@ module \cr parameter \Y_WIDTH 4 connect \A \$3 connect \B \$5 - connect \Y $or$libresoc.v:49589$3047_Y + connect \Y $or$libresoc.v:49301$3039_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49562$3020 + cell $reduce_or $reduce_or$libresoc.v:49282$3020 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$17 - connect \Y $reduce_or$libresoc.v:49562$3020_Y + connect \Y $reduce_or$libresoc.v:49282$3020_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49563$3021 + cell $reduce_or $reduce_or$libresoc.v:49283$3021 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:49563$3021_Y + connect \Y $reduce_or$libresoc.v:49283$3021_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49571$3029 + cell $reduce_or $reduce_or$libresoc.v:49291$3029 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$34 - connect \Y $reduce_or$libresoc.v:49571$3029_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49580$3038 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ren_delay$51 - connect \Y $reduce_or$libresoc.v:49580$3038_Y + connect \Y $reduce_or$libresoc.v:49291$3029_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:49598.9-49619.4" + attribute \src "libresoc.v:49308.9-49327.4" cell \reg_0 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \cr_pred0__data_o \reg_0_cr_pred0__data_o - connect \cr_pred0__ren \reg_0_cr_pred0__ren connect \dest10__data_i \reg_0_dest10__data_i connect \dest10__wen \reg_0_dest10__wen connect \dest20__data_i \reg_0_dest20__data_i @@ -86694,12 +86289,10 @@ module \cr connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49620.9-49641.4" + attribute \src "libresoc.v:49328.9-49347.4" cell \reg_1 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \cr_pred1__data_o \reg_1_cr_pred1__data_o - connect \cr_pred1__ren \reg_1_cr_pred1__ren connect \dest11__data_i \reg_1_dest11__data_i connect \dest11__wen \reg_1_dest11__wen connect \dest21__data_i \reg_1_dest21__data_i @@ -86718,12 +86311,10 @@ module \cr connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49642.9-49663.4" + attribute \src "libresoc.v:49348.9-49367.4" cell \reg_2 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \cr_pred2__data_o \reg_2_cr_pred2__data_o - connect \cr_pred2__ren \reg_2_cr_pred2__ren connect \dest12__data_i \reg_2_dest12__data_i connect \dest12__wen \reg_2_dest12__wen connect \dest22__data_i \reg_2_dest22__data_i @@ -86742,12 +86333,10 @@ module \cr connect \w2__wen \reg_2_w2__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49664.9-49685.4" + attribute \src "libresoc.v:49368.9-49387.4" cell \reg_3 \reg_3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \cr_pred3__data_o \reg_3_cr_pred3__data_o - connect \cr_pred3__ren \reg_3_cr_pred3__ren connect \dest13__data_i \reg_3_dest13__data_i connect \dest13__wen \reg_3_dest13__wen connect \dest23__data_i \reg_3_dest23__data_i @@ -86766,12 +86355,10 @@ module \cr connect \w3__wen \reg_3_w3__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49686.9-49707.4" + attribute \src "libresoc.v:49388.9-49407.4" cell \reg_4 \reg_4 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \cr_pred4__data_o \reg_4_cr_pred4__data_o - connect \cr_pred4__ren \reg_4_cr_pred4__ren connect \dest14__data_i \reg_4_dest14__data_i connect \dest14__wen \reg_4_dest14__wen connect \dest24__data_i \reg_4_dest24__data_i @@ -86790,12 +86377,10 @@ module \cr connect \w4__wen \reg_4_w4__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49708.9-49729.4" + attribute \src "libresoc.v:49408.9-49427.4" cell \reg_5 \reg_5 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \cr_pred5__data_o \reg_5_cr_pred5__data_o - connect \cr_pred5__ren \reg_5_cr_pred5__ren connect \dest15__data_i \reg_5_dest15__data_i connect \dest15__wen \reg_5_dest15__wen connect \dest25__data_i \reg_5_dest25__data_i @@ -86814,12 +86399,10 @@ module \cr connect \w5__wen \reg_5_w5__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49730.9-49751.4" + attribute \src "libresoc.v:49428.9-49447.4" cell \reg_6 \reg_6 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \cr_pred6__data_o \reg_6_cr_pred6__data_o - connect \cr_pred6__ren \reg_6_cr_pred6__ren connect \dest16__data_i \reg_6_dest16__data_i connect \dest16__wen \reg_6_dest16__wen connect \dest26__data_i \reg_6_dest26__data_i @@ -86838,12 +86421,10 @@ module \cr connect \w6__wen \reg_6_w6__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49752.9-49773.4" + attribute \src "libresoc.v:49448.9-49467.4" cell \reg_7 \reg_7 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \cr_pred7__data_o \reg_7_cr_pred7__data_o - connect \cr_pred7__ren \reg_7_cr_pred7__ren connect \dest17__data_i \reg_7_dest17__data_i connect \dest17__wen \reg_7_dest17__wen connect \dest27__data_i \reg_7_dest27__data_i @@ -86861,82 +86442,67 @@ module \cr connect \w7__data_i \reg_7_w7__data_i connect \w7__wen \reg_7_w7__wen end - attribute \src "libresoc.v:49146.7-49146.20" - process $proc$libresoc.v:49146$3071 + attribute \src "libresoc.v:48922.7-48922.20" + process $proc$libresoc.v:48922$3057 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49524.13-49524.30" - process $proc$libresoc.v:49524$3072 + attribute \src "libresoc.v:49248.13-49248.30" + process $proc$libresoc.v:49248$3058 assign { } { } assign $1\ren_delay[7:0] 8'00000000 sync always sync init update \ren_delay $1\ren_delay[7:0] end - attribute \src "libresoc.v:49526.13-49526.35" - process $proc$libresoc.v:49526$3073 - assign { } { } - assign $0\ren_delay$17[7:0]$3074 8'00000000 - sync always - sync init - update \ren_delay$17 $0\ren_delay$17[7:0]$3074 - end - attribute \src "libresoc.v:49530.13-49530.35" - process $proc$libresoc.v:49530$3075 + attribute \src "libresoc.v:49250.13-49250.35" + process $proc$libresoc.v:49250$3059 assign { } { } - assign $0\ren_delay$34[7:0]$3076 8'00000000 + assign $0\ren_delay$17[7:0]$3060 8'00000000 sync always sync init - update \ren_delay$34 $0\ren_delay$34[7:0]$3076 + update \ren_delay$17 $0\ren_delay$17[7:0]$3060 end - attribute \src "libresoc.v:49534.13-49534.35" - process $proc$libresoc.v:49534$3077 + attribute \src "libresoc.v:49254.13-49254.35" + process $proc$libresoc.v:49254$3061 assign { } { } - assign $0\ren_delay$51[7:0]$3078 8'00000000 + assign $0\ren_delay$34[7:0]$3062 8'00000000 sync always sync init - update \ren_delay$51 $0\ren_delay$51[7:0]$3078 + update \ren_delay$34 $0\ren_delay$34[7:0]$3062 end - attribute \src "libresoc.v:49590.3-49591.43" - process $proc$libresoc.v:49590$3048 + attribute \src "libresoc.v:49302.3-49303.43" + process $proc$libresoc.v:49302$3040 assign { } { } - assign $0\ren_delay$51[7:0]$3049 \ren_delay$51$next + assign $0\ren_delay$34[7:0]$3041 \ren_delay$34$next sync posedge \coresync_clk - update \ren_delay$51 $0\ren_delay$51[7:0]$3049 + update \ren_delay$34 $0\ren_delay$34[7:0]$3041 end - attribute \src "libresoc.v:49592.3-49593.43" - process $proc$libresoc.v:49592$3050 + attribute \src "libresoc.v:49304.3-49305.43" + process $proc$libresoc.v:49304$3042 assign { } { } - assign $0\ren_delay$34[7:0]$3051 \ren_delay$34$next + assign $0\ren_delay$17[7:0]$3043 \ren_delay$17$next sync posedge \coresync_clk - update \ren_delay$34 $0\ren_delay$34[7:0]$3051 + update \ren_delay$17 $0\ren_delay$17[7:0]$3043 end - attribute \src "libresoc.v:49594.3-49595.43" - process $proc$libresoc.v:49594$3052 - assign { } { } - assign $0\ren_delay$17[7:0]$3053 \ren_delay$17$next - sync posedge \coresync_clk - update \ren_delay$17 $0\ren_delay$17[7:0]$3053 - end - attribute \src "libresoc.v:49596.3-49597.35" - process $proc$libresoc.v:49596$3054 + attribute \src "libresoc.v:49306.3-49307.35" + process $proc$libresoc.v:49306$3044 assign { } { } assign $0\ren_delay[7:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[7:0] end - attribute \src "libresoc.v:49774.3-49782.6" - process $proc$libresoc.v:49774$3055 + attribute \src "libresoc.v:49468.3-49476.6" + process $proc$libresoc.v:49468$3045 assign { } { } assign { } { } - assign $0\ren_delay$17$next[7:0]$3056 $1\ren_delay$17$next[7:0]$3057 - attribute \src "libresoc.v:49775.5-49775.29" + assign $0\ren_delay$17$next[7:0]$3046 $1\ren_delay$17$next[7:0]$3047 + attribute \src "libresoc.v:49469.5-49469.29" switch \initial - attribute \src "libresoc.v:49775.9-49775.17" + attribute \src "libresoc.v:49469.9-49469.17" case 1'1 case end @@ -86945,90 +86511,44 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$17$next[7:0]$3057 8'00000000 + assign $1\ren_delay$17$next[7:0]$3047 8'00000000 case - assign $1\ren_delay$17$next[7:0]$3057 \src1__ren + assign $1\ren_delay$17$next[7:0]$3047 \src2__ren end sync always - update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3056 + update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3046 end - attribute \src "libresoc.v:49783.3-49792.6" - process $proc$libresoc.v:49783$3058 - assign { } { } - assign { } { } - assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] - attribute \src "libresoc.v:49784.5-49784.29" - switch \initial - attribute \src "libresoc.v:49784.9-49784.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$18 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src1__data_o[3:0] \$32 - case - assign $1\src1__data_o[3:0] 4'0000 - end - sync always - update \src1__data_o $0\src1__data_o[3:0] - end - attribute \src "libresoc.v:49793.3-49801.6" - process $proc$libresoc.v:49793$3059 - assign { } { } - assign { } { } - assign $0\ren_delay$34$next[7:0]$3060 $1\ren_delay$34$next[7:0]$3061 - attribute \src "libresoc.v:49794.5-49794.29" - switch \initial - attribute \src "libresoc.v:49794.9-49794.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$34$next[7:0]$3061 8'00000000 - case - assign $1\ren_delay$34$next[7:0]$3061 \src2__ren - end - sync always - update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3060 - end - attribute \src "libresoc.v:49802.3-49811.6" - process $proc$libresoc.v:49802$3062 + attribute \src "libresoc.v:49477.3-49486.6" + process $proc$libresoc.v:49477$3048 assign { } { } assign { } { } assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] - attribute \src "libresoc.v:49803.5-49803.29" + attribute \src "libresoc.v:49478.5-49478.29" switch \initial - attribute \src "libresoc.v:49803.9-49803.17" + attribute \src "libresoc.v:49478.9-49478.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$35 + switch \$18 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src2__data_o[3:0] \$49 + assign $1\src2__data_o[3:0] \$32 case assign $1\src2__data_o[3:0] 4'0000 end sync always update \src2__data_o $0\src2__data_o[3:0] end - attribute \src "libresoc.v:49812.3-49820.6" - process $proc$libresoc.v:49812$3063 + attribute \src "libresoc.v:49487.3-49495.6" + process $proc$libresoc.v:49487$3049 assign { } { } assign { } { } - assign $0\ren_delay$51$next[7:0]$3064 $1\ren_delay$51$next[7:0]$3065 - attribute \src "libresoc.v:49813.5-49813.29" + assign $0\ren_delay$34$next[7:0]$3050 $1\ren_delay$34$next[7:0]$3051 + attribute \src "libresoc.v:49488.5-49488.29" switch \initial - attribute \src "libresoc.v:49813.9-49813.17" + attribute \src "libresoc.v:49488.9-49488.17" case 1'1 case end @@ -87037,44 +86557,44 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$51$next[7:0]$3065 8'00000000 + assign $1\ren_delay$34$next[7:0]$3051 8'00000000 case - assign $1\ren_delay$51$next[7:0]$3065 \src3__ren + assign $1\ren_delay$34$next[7:0]$3051 \src3__ren end sync always - update \ren_delay$51$next $0\ren_delay$51$next[7:0]$3064 + update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3050 end - attribute \src "libresoc.v:49821.3-49830.6" - process $proc$libresoc.v:49821$3066 + attribute \src "libresoc.v:49496.3-49505.6" + process $proc$libresoc.v:49496$3052 assign { } { } assign { } { } assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] - attribute \src "libresoc.v:49822.5-49822.29" + attribute \src "libresoc.v:49497.5-49497.29" switch \initial - attribute \src "libresoc.v:49822.9-49822.17" + attribute \src "libresoc.v:49497.9-49497.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$52 + switch \$35 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src3__data_o[3:0] \$66 + assign $1\src3__data_o[3:0] \$49 case assign $1\src3__data_o[3:0] 4'0000 end sync always update \src3__data_o $0\src3__data_o[3:0] end - attribute \src "libresoc.v:49831.3-49839.6" - process $proc$libresoc.v:49831$3067 + attribute \src "libresoc.v:49506.3-49514.6" + process $proc$libresoc.v:49506$3053 assign { } { } assign { } { } - assign $0\ren_delay$next[7:0]$3068 $1\ren_delay$next[7:0]$3069 - attribute \src "libresoc.v:49832.5-49832.29" + assign $0\ren_delay$next[7:0]$3054 $1\ren_delay$next[7:0]$3055 + attribute \src "libresoc.v:49507.5-49507.29" switch \initial - attribute \src "libresoc.v:49832.9-49832.17" + attribute \src "libresoc.v:49507.9-49507.17" case 1'1 case end @@ -87083,21 +86603,21 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[7:0]$3069 8'00000000 + assign $1\ren_delay$next[7:0]$3055 8'00000000 case - assign $1\ren_delay$next[7:0]$3069 \cr_pred__ren + assign $1\ren_delay$next[7:0]$3055 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[7:0]$3068 + update \ren_delay$next $0\ren_delay$next[7:0]$3054 end - attribute \src "libresoc.v:49840.3-49849.6" - process $proc$libresoc.v:49840$3070 + attribute \src "libresoc.v:49515.3-49524.6" + process $proc$libresoc.v:49515$3056 assign { } { } assign { } { } - assign $0\cr_pred__data_o[3:0] $1\cr_pred__data_o[3:0] - attribute \src "libresoc.v:49841.5-49841.29" + assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] + attribute \src "libresoc.v:49516.5-49516.29" switch \initial - attribute \src "libresoc.v:49841.9-49841.17" + attribute \src "libresoc.v:49516.9-49516.17" case 1'1 case end @@ -87106,48 +86626,39 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\cr_pred__data_o[3:0] \$15 - case - assign $1\cr_pred__data_o[3:0] 4'0000 - end - sync always - update \cr_pred__data_o $0\cr_pred__data_o[3:0] - end - connect \$9 $or$libresoc.v:49558$3016_Y - connect \$11 $or$libresoc.v:49559$3017_Y - connect \$13 $or$libresoc.v:49560$3018_Y - connect \$15 $or$libresoc.v:49561$3019_Y - connect \$18 $reduce_or$libresoc.v:49562$3020_Y - connect \$1 $reduce_or$libresoc.v:49563$3021_Y - connect \$20 $or$libresoc.v:49564$3022_Y - connect \$22 $or$libresoc.v:49565$3023_Y - connect \$24 $or$libresoc.v:49566$3024_Y - connect \$26 $or$libresoc.v:49567$3025_Y - connect \$28 $or$libresoc.v:49568$3026_Y - connect \$30 $or$libresoc.v:49569$3027_Y - connect \$32 $or$libresoc.v:49570$3028_Y - connect \$35 $reduce_or$libresoc.v:49571$3029_Y - connect \$37 $or$libresoc.v:49572$3030_Y - connect \$3 $or$libresoc.v:49573$3031_Y - connect \$39 $or$libresoc.v:49574$3032_Y - connect \$41 $or$libresoc.v:49575$3033_Y - connect \$43 $or$libresoc.v:49576$3034_Y - connect \$45 $or$libresoc.v:49577$3035_Y - connect \$47 $or$libresoc.v:49578$3036_Y - connect \$49 $or$libresoc.v:49579$3037_Y - connect \$52 $reduce_or$libresoc.v:49580$3038_Y - connect \$54 $or$libresoc.v:49581$3039_Y - connect \$56 $or$libresoc.v:49582$3040_Y - connect \$58 $or$libresoc.v:49583$3041_Y - connect \$5 $or$libresoc.v:49584$3042_Y - connect \$60 $or$libresoc.v:49585$3043_Y - connect \$62 $or$libresoc.v:49586$3044_Y - connect \$64 $or$libresoc.v:49587$3045_Y - connect \$66 $or$libresoc.v:49588$3046_Y - connect \$7 $or$libresoc.v:49589$3047_Y - connect \cr_pred__ren 8'00000000 - connect \wen$68 8'00000000 - connect \data_i$69 4'0000 + assign $1\src1__data_o[3:0] \$15 + case + assign $1\src1__data_o[3:0] 4'0000 + end + sync always + update \src1__data_o $0\src1__data_o[3:0] + end + connect \$9 $or$libresoc.v:49278$3016_Y + connect \$11 $or$libresoc.v:49279$3017_Y + connect \$13 $or$libresoc.v:49280$3018_Y + connect \$15 $or$libresoc.v:49281$3019_Y + connect \$18 $reduce_or$libresoc.v:49282$3020_Y + connect \$1 $reduce_or$libresoc.v:49283$3021_Y + connect \$20 $or$libresoc.v:49284$3022_Y + connect \$22 $or$libresoc.v:49285$3023_Y + connect \$24 $or$libresoc.v:49286$3024_Y + connect \$26 $or$libresoc.v:49287$3025_Y + connect \$28 $or$libresoc.v:49288$3026_Y + connect \$30 $or$libresoc.v:49289$3027_Y + connect \$32 $or$libresoc.v:49290$3028_Y + connect \$35 $reduce_or$libresoc.v:49291$3029_Y + connect \$37 $or$libresoc.v:49292$3030_Y + connect \$3 $or$libresoc.v:49293$3031_Y + connect \$39 $or$libresoc.v:49294$3032_Y + connect \$41 $or$libresoc.v:49295$3033_Y + connect \$43 $or$libresoc.v:49296$3034_Y + connect \$45 $or$libresoc.v:49297$3035_Y + connect \$47 $or$libresoc.v:49298$3036_Y + connect \$49 $or$libresoc.v:49299$3037_Y + connect \$5 $or$libresoc.v:49300$3038_Y + connect \$7 $or$libresoc.v:49301$3039_Y + connect \wen$51 8'00000000 + connect \data_i$52 4'0000 connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen connect { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i connect { \reg_7_r27__ren \reg_6_r26__ren \reg_5_r25__ren \reg_4_r24__ren \reg_3_r23__ren \reg_2_r22__ren \reg_1_r21__ren \reg_0_r20__ren } \full_rd2__ren @@ -87175,395 +86686,394 @@ module \cr connect { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren - connect { \reg_7_cr_pred7__ren \reg_6_cr_pred6__ren \reg_5_cr_pred5__ren \reg_4_cr_pred4__ren \reg_3_cr_pred3__ren \reg_2_cr_pred2__ren \reg_1_cr_pred1__ren \reg_0_cr_pred0__ren } 8'00000000 end -attribute \src "libresoc.v:49885.1-50942.10" +attribute \src "libresoc.v:49558.1-50615.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0" attribute \generator "nMigen" module \cr0 - attribute \src "libresoc.v:50543.3-50544.25" + attribute \src "libresoc.v:50216.3-50217.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:50716.3-50727.6" - wire width 14 $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 - attribute \src "libresoc.v:50515.3-50516.61" + attribute \src "libresoc.v:50389.3-50400.6" + wire width 14 $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 + attribute \src "libresoc.v:50188.3-50189.61" wire width 14 $0\alu_cr0_cr_op__fn_unit[13:0] - attribute \src "libresoc.v:50716.3-50727.6" - wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3199 - attribute \src "libresoc.v:50517.3-50518.55" + attribute \src "libresoc.v:50389.3-50400.6" + wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3183 + attribute \src "libresoc.v:50190.3-50191.55" wire width 32 $0\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50716.3-50727.6" - wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 - attribute \src "libresoc.v:50513.3-50514.65" + attribute \src "libresoc.v:50389.3-50400.6" + wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 + attribute \src "libresoc.v:50186.3-50187.65" wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:50541.3-50542.39" + attribute \src "libresoc.v:50214.3-50215.39" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:50863.3-50871.6" - wire $0\alu_l_r_alu$next[0:0]$3250 - attribute \src "libresoc.v:50485.3-50486.39" + attribute \src "libresoc.v:50536.3-50544.6" + wire $0\alu_l_r_alu$next[0:0]$3234 + attribute \src "libresoc.v:50158.3-50159.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50854.3-50862.6" - wire $0\alui_l_r_alui$next[0:0]$3247 - attribute \src "libresoc.v:50487.3-50488.43" + attribute \src "libresoc.v:50527.3-50535.6" + wire $0\alui_l_r_alui$next[0:0]$3231 + attribute \src "libresoc.v:50160.3-50161.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50728.3-50749.6" - wire width 64 $0\data_r0__o$next[63:0]$3205 - attribute \src "libresoc.v:50509.3-50510.37" + attribute \src "libresoc.v:50401.3-50422.6" + wire width 64 $0\data_r0__o$next[63:0]$3189 + attribute \src "libresoc.v:50182.3-50183.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:50728.3-50749.6" - wire $0\data_r0__o_ok$next[0:0]$3206 - attribute \src "libresoc.v:50511.3-50512.43" + attribute \src "libresoc.v:50401.3-50422.6" + wire $0\data_r0__o_ok$next[0:0]$3190 + attribute \src "libresoc.v:50184.3-50185.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50750.3-50771.6" - wire width 32 $0\data_r1__full_cr$next[31:0]$3213 - attribute \src "libresoc.v:50505.3-50506.49" + attribute \src "libresoc.v:50423.3-50444.6" + wire width 32 $0\data_r1__full_cr$next[31:0]$3197 + attribute \src "libresoc.v:50178.3-50179.49" wire width 32 $0\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50750.3-50771.6" - wire $0\data_r1__full_cr_ok$next[0:0]$3214 - attribute \src "libresoc.v:50507.3-50508.55" + attribute \src "libresoc.v:50423.3-50444.6" + wire $0\data_r1__full_cr_ok$next[0:0]$3198 + attribute \src "libresoc.v:50180.3-50181.55" wire $0\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50772.3-50793.6" - wire width 4 $0\data_r2__cr_a$next[3:0]$3221 - attribute \src "libresoc.v:50501.3-50502.43" + attribute \src "libresoc.v:50445.3-50466.6" + wire width 4 $0\data_r2__cr_a$next[3:0]$3205 + attribute \src "libresoc.v:50174.3-50175.43" wire width 4 $0\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50772.3-50793.6" - wire $0\data_r2__cr_a_ok$next[0:0]$3222 - attribute \src "libresoc.v:50503.3-50504.49" + attribute \src "libresoc.v:50445.3-50466.6" + wire $0\data_r2__cr_a_ok$next[0:0]$3206 + attribute \src "libresoc.v:50176.3-50177.49" wire $0\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50872.3-50881.6" + attribute \src "libresoc.v:50545.3-50554.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:50882.3-50891.6" + attribute \src "libresoc.v:50555.3-50564.6" wire width 32 $0\dest2_o[31:0] - attribute \src "libresoc.v:50892.3-50901.6" + attribute \src "libresoc.v:50565.3-50574.6" wire width 4 $0\dest3_o[3:0] - attribute \src "libresoc.v:49886.7-49886.20" + attribute \src "libresoc.v:49559.7-49559.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50671.3-50679.6" - wire $0\opc_l_r_opc$next[0:0]$3183 - attribute \src "libresoc.v:50527.3-50528.39" + attribute \src "libresoc.v:50344.3-50352.6" + wire $0\opc_l_r_opc$next[0:0]$3167 + attribute \src "libresoc.v:50200.3-50201.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50662.3-50670.6" - wire $0\opc_l_s_opc$next[0:0]$3180 - attribute \src "libresoc.v:50529.3-50530.39" + attribute \src "libresoc.v:50335.3-50343.6" + wire $0\opc_l_s_opc$next[0:0]$3164 + attribute \src "libresoc.v:50202.3-50203.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50902.3-50910.6" - wire width 3 $0\prev_wr_go$next[2:0]$3256 - attribute \src "libresoc.v:50539.3-50540.37" + attribute \src "libresoc.v:50575.3-50583.6" + wire width 3 $0\prev_wr_go$next[2:0]$3240 + attribute \src "libresoc.v:50212.3-50213.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:50616.3-50625.6" + attribute \src "libresoc.v:50289.3-50298.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:50707.3-50715.6" - wire width 3 $0\req_l_r_req$next[2:0]$3195 - attribute \src "libresoc.v:50519.3-50520.39" + attribute \src "libresoc.v:50380.3-50388.6" + wire width 3 $0\req_l_r_req$next[2:0]$3179 + attribute \src "libresoc.v:50192.3-50193.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:50698.3-50706.6" - wire width 3 $0\req_l_s_req$next[2:0]$3192 - attribute \src "libresoc.v:50521.3-50522.39" + attribute \src "libresoc.v:50371.3-50379.6" + wire width 3 $0\req_l_s_req$next[2:0]$3176 + attribute \src "libresoc.v:50194.3-50195.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:50635.3-50643.6" - wire $0\rok_l_r_rdok$next[0:0]$3171 - attribute \src "libresoc.v:50535.3-50536.41" + attribute \src "libresoc.v:50308.3-50316.6" + wire $0\rok_l_r_rdok$next[0:0]$3155 + attribute \src "libresoc.v:50208.3-50209.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:50626.3-50634.6" - wire $0\rok_l_s_rdok$next[0:0]$3168 - attribute \src "libresoc.v:50537.3-50538.41" + attribute \src "libresoc.v:50299.3-50307.6" + wire $0\rok_l_s_rdok$next[0:0]$3152 + attribute \src "libresoc.v:50210.3-50211.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:50653.3-50661.6" - wire $0\rst_l_r_rst$next[0:0]$3177 - attribute \src "libresoc.v:50531.3-50532.39" + attribute \src "libresoc.v:50326.3-50334.6" + wire $0\rst_l_r_rst$next[0:0]$3161 + attribute \src "libresoc.v:50204.3-50205.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:50644.3-50652.6" - wire $0\rst_l_s_rst$next[0:0]$3174 - attribute \src "libresoc.v:50533.3-50534.39" + attribute \src "libresoc.v:50317.3-50325.6" + wire $0\rst_l_s_rst$next[0:0]$3158 + attribute \src "libresoc.v:50206.3-50207.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:50689.3-50697.6" - wire width 6 $0\src_l_r_src$next[5:0]$3189 - attribute \src "libresoc.v:50523.3-50524.39" + attribute \src "libresoc.v:50362.3-50370.6" + wire width 6 $0\src_l_r_src$next[5:0]$3173 + attribute \src "libresoc.v:50196.3-50197.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:50680.3-50688.6" - wire width 6 $0\src_l_s_src$next[5:0]$3186 - attribute \src "libresoc.v:50525.3-50526.39" + attribute \src "libresoc.v:50353.3-50361.6" + wire width 6 $0\src_l_s_src$next[5:0]$3170 + attribute \src "libresoc.v:50198.3-50199.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:50794.3-50803.6" - wire width 64 $0\src_r0$next[63:0]$3229 - attribute \src "libresoc.v:50499.3-50500.29" + attribute \src "libresoc.v:50467.3-50476.6" + wire width 64 $0\src_r0$next[63:0]$3213 + attribute \src "libresoc.v:50172.3-50173.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:50804.3-50813.6" - wire width 64 $0\src_r1$next[63:0]$3232 - attribute \src "libresoc.v:50497.3-50498.29" + attribute \src "libresoc.v:50477.3-50486.6" + wire width 64 $0\src_r1$next[63:0]$3216 + attribute \src "libresoc.v:50170.3-50171.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:50814.3-50823.6" - wire width 32 $0\src_r2$next[31:0]$3235 - attribute \src "libresoc.v:50495.3-50496.29" + attribute \src "libresoc.v:50487.3-50496.6" + wire width 32 $0\src_r2$next[31:0]$3219 + attribute \src "libresoc.v:50168.3-50169.29" wire width 32 $0\src_r2[31:0] - attribute \src "libresoc.v:50824.3-50833.6" - wire width 4 $0\src_r3$next[3:0]$3238 - attribute \src "libresoc.v:50493.3-50494.29" + attribute \src "libresoc.v:50497.3-50506.6" + wire width 4 $0\src_r3$next[3:0]$3222 + attribute \src "libresoc.v:50166.3-50167.29" wire width 4 $0\src_r3[3:0] - attribute \src "libresoc.v:50834.3-50843.6" - wire width 4 $0\src_r4$next[3:0]$3241 - attribute \src "libresoc.v:50491.3-50492.29" + attribute \src "libresoc.v:50507.3-50516.6" + wire width 4 $0\src_r4$next[3:0]$3225 + attribute \src "libresoc.v:50164.3-50165.29" wire width 4 $0\src_r4[3:0] - attribute \src "libresoc.v:50844.3-50853.6" - wire width 4 $0\src_r5$next[3:0]$3244 - attribute \src "libresoc.v:50489.3-50490.29" + attribute \src "libresoc.v:50517.3-50526.6" + wire width 4 $0\src_r5$next[3:0]$3228 + attribute \src "libresoc.v:50162.3-50163.29" wire width 4 $0\src_r5[3:0] - attribute \src "libresoc.v:50004.7-50004.24" + attribute \src "libresoc.v:49677.7-49677.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:50716.3-50727.6" - wire width 14 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 - attribute \src "libresoc.v:50035.14-50035.47" + attribute \src "libresoc.v:50389.3-50400.6" + wire width 14 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 + attribute \src "libresoc.v:49708.14-49708.47" wire width 14 $1\alu_cr0_cr_op__fn_unit[13:0] - attribute \src "libresoc.v:50716.3-50727.6" - wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3202 - attribute \src "libresoc.v:50039.14-50039.41" + attribute \src "libresoc.v:50389.3-50400.6" + wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3186 + attribute \src "libresoc.v:49712.14-49712.41" wire width 32 $1\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50716.3-50727.6" - wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 - attribute \src "libresoc.v:50118.13-50118.45" + attribute \src "libresoc.v:50389.3-50400.6" + wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 + attribute \src "libresoc.v:49791.13-49791.45" wire width 7 $1\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:50142.7-50142.26" + attribute \src "libresoc.v:49815.7-49815.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:50863.3-50871.6" - wire $1\alu_l_r_alu$next[0:0]$3251 - attribute \src "libresoc.v:50150.7-50150.25" + attribute \src "libresoc.v:50536.3-50544.6" + wire $1\alu_l_r_alu$next[0:0]$3235 + attribute \src "libresoc.v:49823.7-49823.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50854.3-50862.6" - wire $1\alui_l_r_alui$next[0:0]$3248 - attribute \src "libresoc.v:50162.7-50162.27" + attribute \src "libresoc.v:50527.3-50535.6" + wire $1\alui_l_r_alui$next[0:0]$3232 + attribute \src "libresoc.v:49835.7-49835.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50728.3-50749.6" - wire width 64 $1\data_r0__o$next[63:0]$3207 - attribute \src "libresoc.v:50196.14-50196.47" + attribute \src "libresoc.v:50401.3-50422.6" + wire width 64 $1\data_r0__o$next[63:0]$3191 + attribute \src "libresoc.v:49869.14-49869.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:50728.3-50749.6" - wire $1\data_r0__o_ok$next[0:0]$3208 - attribute \src "libresoc.v:50200.7-50200.27" + attribute \src "libresoc.v:50401.3-50422.6" + wire $1\data_r0__o_ok$next[0:0]$3192 + attribute \src "libresoc.v:49873.7-49873.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50750.3-50771.6" - wire width 32 $1\data_r1__full_cr$next[31:0]$3215 - attribute \src "libresoc.v:50204.14-50204.38" + attribute \src "libresoc.v:50423.3-50444.6" + wire width 32 $1\data_r1__full_cr$next[31:0]$3199 + attribute \src "libresoc.v:49877.14-49877.38" wire width 32 $1\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50750.3-50771.6" - wire $1\data_r1__full_cr_ok$next[0:0]$3216 - attribute \src "libresoc.v:50208.7-50208.33" + attribute \src "libresoc.v:50423.3-50444.6" + wire $1\data_r1__full_cr_ok$next[0:0]$3200 + attribute \src "libresoc.v:49881.7-49881.33" wire $1\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50772.3-50793.6" - wire width 4 $1\data_r2__cr_a$next[3:0]$3223 - attribute \src "libresoc.v:50212.13-50212.33" + attribute \src "libresoc.v:50445.3-50466.6" + wire width 4 $1\data_r2__cr_a$next[3:0]$3207 + attribute \src "libresoc.v:49885.13-49885.33" wire width 4 $1\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50772.3-50793.6" - wire $1\data_r2__cr_a_ok$next[0:0]$3224 - attribute \src "libresoc.v:50216.7-50216.30" + attribute \src "libresoc.v:50445.3-50466.6" + wire $1\data_r2__cr_a_ok$next[0:0]$3208 + attribute \src "libresoc.v:49889.7-49889.30" wire $1\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50872.3-50881.6" + attribute \src "libresoc.v:50545.3-50554.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:50882.3-50891.6" + attribute \src "libresoc.v:50555.3-50564.6" wire width 32 $1\dest2_o[31:0] - attribute \src "libresoc.v:50892.3-50901.6" + attribute \src "libresoc.v:50565.3-50574.6" wire width 4 $1\dest3_o[3:0] - attribute \src "libresoc.v:50671.3-50679.6" - wire $1\opc_l_r_opc$next[0:0]$3184 - attribute \src "libresoc.v:50235.7-50235.25" + attribute \src "libresoc.v:50344.3-50352.6" + wire $1\opc_l_r_opc$next[0:0]$3168 + attribute \src "libresoc.v:49908.7-49908.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50662.3-50670.6" - wire $1\opc_l_s_opc$next[0:0]$3181 - attribute \src "libresoc.v:50239.7-50239.25" + attribute \src "libresoc.v:50335.3-50343.6" + wire $1\opc_l_s_opc$next[0:0]$3165 + attribute \src "libresoc.v:49912.7-49912.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50902.3-50910.6" - wire width 3 $1\prev_wr_go$next[2:0]$3257 - attribute \src "libresoc.v:50339.13-50339.30" + attribute \src "libresoc.v:50575.3-50583.6" + wire width 3 $1\prev_wr_go$next[2:0]$3241 + attribute \src "libresoc.v:50012.13-50012.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:50616.3-50625.6" + attribute \src "libresoc.v:50289.3-50298.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:50707.3-50715.6" - wire width 3 $1\req_l_r_req$next[2:0]$3196 - attribute \src "libresoc.v:50347.13-50347.31" + attribute \src "libresoc.v:50380.3-50388.6" + wire width 3 $1\req_l_r_req$next[2:0]$3180 + attribute \src "libresoc.v:50020.13-50020.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:50698.3-50706.6" - wire width 3 $1\req_l_s_req$next[2:0]$3193 - attribute \src "libresoc.v:50351.13-50351.31" + attribute \src "libresoc.v:50371.3-50379.6" + wire width 3 $1\req_l_s_req$next[2:0]$3177 + attribute \src "libresoc.v:50024.13-50024.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:50635.3-50643.6" - wire $1\rok_l_r_rdok$next[0:0]$3172 - attribute \src "libresoc.v:50363.7-50363.26" + attribute \src "libresoc.v:50308.3-50316.6" + wire $1\rok_l_r_rdok$next[0:0]$3156 + attribute \src "libresoc.v:50036.7-50036.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:50626.3-50634.6" - wire $1\rok_l_s_rdok$next[0:0]$3169 - attribute \src "libresoc.v:50367.7-50367.26" + attribute \src "libresoc.v:50299.3-50307.6" + wire $1\rok_l_s_rdok$next[0:0]$3153 + attribute \src "libresoc.v:50040.7-50040.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:50653.3-50661.6" - wire $1\rst_l_r_rst$next[0:0]$3178 - attribute \src "libresoc.v:50371.7-50371.25" + attribute \src "libresoc.v:50326.3-50334.6" + wire $1\rst_l_r_rst$next[0:0]$3162 + attribute \src "libresoc.v:50044.7-50044.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:50644.3-50652.6" - wire $1\rst_l_s_rst$next[0:0]$3175 - attribute \src "libresoc.v:50375.7-50375.25" + attribute \src "libresoc.v:50317.3-50325.6" + wire $1\rst_l_s_rst$next[0:0]$3159 + attribute \src "libresoc.v:50048.7-50048.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:50689.3-50697.6" - wire width 6 $1\src_l_r_src$next[5:0]$3190 - attribute \src "libresoc.v:50395.13-50395.32" + attribute \src "libresoc.v:50362.3-50370.6" + wire width 6 $1\src_l_r_src$next[5:0]$3174 + attribute \src "libresoc.v:50068.13-50068.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:50680.3-50688.6" - wire width 6 $1\src_l_s_src$next[5:0]$3187 - attribute \src "libresoc.v:50399.13-50399.32" + attribute \src "libresoc.v:50353.3-50361.6" + wire width 6 $1\src_l_s_src$next[5:0]$3171 + attribute \src "libresoc.v:50072.13-50072.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:50794.3-50803.6" - wire width 64 $1\src_r0$next[63:0]$3230 - attribute \src "libresoc.v:50403.14-50403.43" + attribute \src "libresoc.v:50467.3-50476.6" + wire width 64 $1\src_r0$next[63:0]$3214 + attribute \src "libresoc.v:50076.14-50076.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:50804.3-50813.6" - wire width 64 $1\src_r1$next[63:0]$3233 - attribute \src "libresoc.v:50407.14-50407.43" + attribute \src "libresoc.v:50477.3-50486.6" + wire width 64 $1\src_r1$next[63:0]$3217 + attribute \src "libresoc.v:50080.14-50080.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:50814.3-50823.6" - wire width 32 $1\src_r2$next[31:0]$3236 - attribute \src "libresoc.v:50411.14-50411.28" + attribute \src "libresoc.v:50487.3-50496.6" + wire width 32 $1\src_r2$next[31:0]$3220 + attribute \src "libresoc.v:50084.14-50084.28" wire width 32 $1\src_r2[31:0] - attribute \src "libresoc.v:50824.3-50833.6" - wire width 4 $1\src_r3$next[3:0]$3239 - attribute \src "libresoc.v:50415.13-50415.26" + attribute \src "libresoc.v:50497.3-50506.6" + wire width 4 $1\src_r3$next[3:0]$3223 + attribute \src "libresoc.v:50088.13-50088.26" wire width 4 $1\src_r3[3:0] - attribute \src "libresoc.v:50834.3-50843.6" - wire width 4 $1\src_r4$next[3:0]$3242 - attribute \src "libresoc.v:50419.13-50419.26" + attribute \src "libresoc.v:50507.3-50516.6" + wire width 4 $1\src_r4$next[3:0]$3226 + attribute \src "libresoc.v:50092.13-50092.26" wire width 4 $1\src_r4[3:0] - attribute \src "libresoc.v:50844.3-50853.6" - wire width 4 $1\src_r5$next[3:0]$3245 - attribute \src "libresoc.v:50423.13-50423.26" + attribute \src "libresoc.v:50517.3-50526.6" + wire width 4 $1\src_r5$next[3:0]$3229 + attribute \src "libresoc.v:50096.13-50096.26" wire width 4 $1\src_r5[3:0] - attribute \src "libresoc.v:50728.3-50749.6" - wire width 64 $2\data_r0__o$next[63:0]$3209 - attribute \src "libresoc.v:50728.3-50749.6" - wire $2\data_r0__o_ok$next[0:0]$3210 - attribute \src "libresoc.v:50750.3-50771.6" - wire width 32 $2\data_r1__full_cr$next[31:0]$3217 - attribute \src "libresoc.v:50750.3-50771.6" - wire $2\data_r1__full_cr_ok$next[0:0]$3218 - attribute \src "libresoc.v:50772.3-50793.6" - wire width 4 $2\data_r2__cr_a$next[3:0]$3225 - attribute \src "libresoc.v:50772.3-50793.6" - wire $2\data_r2__cr_a_ok$next[0:0]$3226 - attribute \src "libresoc.v:50728.3-50749.6" - wire $3\data_r0__o_ok$next[0:0]$3211 - attribute \src "libresoc.v:50750.3-50771.6" - wire $3\data_r1__full_cr_ok$next[0:0]$3219 - attribute \src "libresoc.v:50772.3-50793.6" - wire $3\data_r2__cr_a_ok$next[0:0]$3227 - attribute \src "libresoc.v:50429.18-50429.112" - wire width 6 $and$libresoc.v:50429$3080_Y - attribute \src "libresoc.v:50430.19-50430.125" - wire $and$libresoc.v:50430$3081_Y - attribute \src "libresoc.v:50431.19-50431.125" - wire $and$libresoc.v:50431$3082_Y - attribute \src "libresoc.v:50432.19-50432.125" - wire $and$libresoc.v:50432$3083_Y - attribute \src "libresoc.v:50433.19-50433.141" - wire width 3 $and$libresoc.v:50433$3084_Y - attribute \src "libresoc.v:50434.19-50434.121" - wire width 3 $and$libresoc.v:50434$3085_Y - attribute \src "libresoc.v:50435.19-50435.127" - wire $and$libresoc.v:50435$3086_Y - attribute \src "libresoc.v:50436.19-50436.127" - wire $and$libresoc.v:50436$3087_Y - attribute \src "libresoc.v:50437.19-50437.127" - wire $and$libresoc.v:50437$3088_Y - attribute \src "libresoc.v:50438.18-50438.110" - wire $and$libresoc.v:50438$3089_Y - attribute \src "libresoc.v:50440.18-50440.98" - wire $and$libresoc.v:50440$3091_Y - attribute \src "libresoc.v:50442.18-50442.100" - wire $and$libresoc.v:50442$3093_Y - attribute \src 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"libresoc.v:50101.17-50101.104" + wire $reduce_and$libresoc.v:50101$3063_Y + attribute \src "libresoc.v:50119.18-50119.106" + wire $reduce_or$libresoc.v:50119$3081_Y + attribute \src "libresoc.v:50122.18-50122.113" + wire $reduce_or$libresoc.v:50122$3084_Y + attribute \src "libresoc.v:50123.18-50123.112" + wire $reduce_or$libresoc.v:50123$3085_Y + attribute \src "libresoc.v:50146.18-50146.118" + wire width 64 $ternary$libresoc.v:50146$3108_Y + attribute \src "libresoc.v:50147.18-50147.118" + wire width 64 $ternary$libresoc.v:50147$3109_Y + attribute \src "libresoc.v:50148.18-50148.118" + wire width 32 $ternary$libresoc.v:50148$3110_Y + attribute \src "libresoc.v:50149.18-50149.118" + wire width 4 $ternary$libresoc.v:50149$3111_Y + attribute \src "libresoc.v:50150.18-50150.118" + wire width 4 $ternary$libresoc.v:50150$3112_Y + attribute \src "libresoc.v:50151.18-50151.118" + wire width 4 $ternary$libresoc.v:50151$3113_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -87688,7 +87198,7 @@ module \cr0 wire \all_rd_pulse attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \alu_cr0_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \alu_cr0_cr_a$2 @@ -87798,7 +87308,7 @@ module \cr0 wire width 7 \alu_cr0_cr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_cr0_cr_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 \alu_cr0_full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 \alu_cr0_full_cr$1 @@ -87806,7 +87316,7 @@ module \cr0 wire \alu_cr0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_cr0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_cr0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_cr0_p_ready_o @@ -87844,11 +87354,11 @@ module \cr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 24 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 22 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 6 \cu_busy_o @@ -87902,11 +87412,11 @@ module \cr0 wire width 32 output 21 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 23 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 20 \full_cr_ok - attribute \src "libresoc.v:49886.7-49886.15" + attribute \src "libresoc.v:49559.7-49559.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 16 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc @@ -88057,9 +87567,9 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 10 \src1_i + wire width 64 input 11 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 11 \src2_i + wire width 64 input 10 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 32 input 12 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" @@ -88105,7 +87615,7 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50429$3080 + cell $and $and$libresoc.v:50102$3064 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88113,10 +87623,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:50429$3080_Y + connect \Y $and$libresoc.v:50102$3064_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50430$3081 + cell $and $and$libresoc.v:50103$3065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88124,10 +87634,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50430$3081_Y + connect \Y $and$libresoc.v:50103$3065_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50431$3082 + cell $and $and$libresoc.v:50104$3066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88135,10 +87645,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50431$3082_Y + connect \Y $and$libresoc.v:50104$3066_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50432$3083 + cell $and $and$libresoc.v:50105$3067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88146,10 +87656,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50432$3083_Y + connect \Y $and$libresoc.v:50105$3067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:50433$3084 + cell $and $and$libresoc.v:50106$3068 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88157,10 +87667,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } - connect \Y $and$libresoc.v:50433$3084_Y + connect \Y $and$libresoc.v:50106$3068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:50434$3085 + cell $and $and$libresoc.v:50107$3069 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88168,10 +87678,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50434$3085_Y + connect \Y $and$libresoc.v:50107$3069_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50435$3086 + cell $and $and$libresoc.v:50108$3070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88179,10 +87689,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50435$3086_Y + connect \Y $and$libresoc.v:50108$3070_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50436$3087 + cell $and $and$libresoc.v:50109$3071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88190,10 +87700,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50436$3087_Y + connect \Y $and$libresoc.v:50109$3071_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50437$3088 + cell $and $and$libresoc.v:50110$3072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88201,10 +87711,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50437$3088_Y + connect \Y $and$libresoc.v:50110$3072_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:50438$3089 + cell $and $and$libresoc.v:50111$3073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88212,10 +87722,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:50438$3089_Y + connect \Y $and$libresoc.v:50111$3073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:50440$3091 + cell $and $and$libresoc.v:50113$3075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88223,10 +87733,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:50440$3091_Y + connect \Y $and$libresoc.v:50113$3075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:50442$3093 + cell $and $and$libresoc.v:50115$3077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88234,10 +87744,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:50442$3093_Y + connect \Y $and$libresoc.v:50115$3077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:50443$3094 + cell $and $and$libresoc.v:50116$3078 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88245,10 +87755,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:50443$3094_Y + connect \Y $and$libresoc.v:50116$3078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:50445$3096 + cell $and $and$libresoc.v:50118$3080 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88256,10 +87766,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:50445$3096_Y + connect \Y $and$libresoc.v:50118$3080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:50448$3099 + cell $and $and$libresoc.v:50121$3083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88267,10 +87777,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:50448$3099_Y + connect \Y $and$libresoc.v:50121$3083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:50452$3103 + cell $and $and$libresoc.v:50125$3087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88278,10 +87788,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:50452$3103_Y + connect \Y $and$libresoc.v:50125$3087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:50454$3105 + cell $and $and$libresoc.v:50127$3089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88289,10 +87799,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:50454$3105_Y + connect \Y $and$libresoc.v:50127$3089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:50455$3106 + cell $and $and$libresoc.v:50128$3090 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88300,10 +87810,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50455$3106_Y + connect \Y $and$libresoc.v:50128$3090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:50457$3108 + cell $and $and$libresoc.v:50130$3092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88311,10 +87821,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:50457$3108_Y + connect \Y $and$libresoc.v:50130$3092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50459$3110 + cell $and $and$libresoc.v:50132$3094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88322,10 +87832,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_cr0_n_ready_i - connect \Y $and$libresoc.v:50459$3110_Y + connect \Y $and$libresoc.v:50132$3094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50460$3111 + cell $and $and$libresoc.v:50133$3095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88333,10 +87843,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_cr0_n_valid_o - connect \Y $and$libresoc.v:50460$3111_Y + connect \Y $and$libresoc.v:50133$3095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50461$3112 + cell $and $and$libresoc.v:50134$3096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88344,10 +87854,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:50461$3112_Y + connect \Y $and$libresoc.v:50134$3096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:50466$3117 + cell $and $and$libresoc.v:50139$3101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88355,10 +87865,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:50466$3117_Y + connect \Y $and$libresoc.v:50139$3101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:50467$3118 + cell $and $and$libresoc.v:50140$3102 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88366,10 +87876,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50467$3118_Y + connect \Y $and$libresoc.v:50140$3102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50470$3121 + cell $and $and$libresoc.v:50143$3105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88377,10 +87887,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50470$3121_Y + connect \Y $and$libresoc.v:50143$3105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50471$3122 + cell $and $and$libresoc.v:50144$3106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88388,10 +87898,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \full_cr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50471$3122_Y + connect \Y $and$libresoc.v:50144$3106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50472$3123 + cell $and $and$libresoc.v:50145$3107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88399,10 +87909,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50472$3123_Y + connect \Y $and$libresoc.v:50145$3107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:50480$3131 + cell $and $and$libresoc.v:50153$3115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88410,10 +87920,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:50480$3131_Y + connect \Y $and$libresoc.v:50153$3115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:50481$3132 + cell $and $and$libresoc.v:50154$3116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88421,10 +87931,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:50481$3132_Y + connect \Y $and$libresoc.v:50154$3116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50482$3133 + cell $and $and$libresoc.v:50155$3117 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88432,10 +87942,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:50482$3133_Y + connect \Y $and$libresoc.v:50155$3117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50483$3134 + cell $and $and$libresoc.v:50156$3118 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88443,10 +87953,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$93 connect \B 6'111111 - connect \Y $and$libresoc.v:50483$3134_Y + connect \Y $and$libresoc.v:50156$3118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:50456$3107 + cell $eq $eq$libresoc.v:50129$3091 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88454,10 +87964,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:50456$3107_Y + connect \Y $eq$libresoc.v:50129$3091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:50458$3109 + cell $eq $eq$libresoc.v:50131$3093 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88465,66 +87975,66 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:50458$3109_Y + connect \Y $eq$libresoc.v:50131$3093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:50439$3090 + cell $not $not$libresoc.v:50112$3074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:50439$3090_Y + connect \Y $not$libresoc.v:50112$3074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:50441$3092 + cell $not $not$libresoc.v:50114$3076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:50441$3092_Y + connect \Y $not$libresoc.v:50114$3076_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:50444$3095 + cell $not $not$libresoc.v:50117$3079 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:50444$3095_Y + connect \Y $not$libresoc.v:50117$3079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:50447$3098 + cell $not $not$libresoc.v:50120$3082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:50447$3098_Y + connect \Y $not$libresoc.v:50120$3082_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:50453$3104 + cell $not $not$libresoc.v:50126$3088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_ready_i - connect \Y $not$libresoc.v:50453$3104_Y + connect \Y $not$libresoc.v:50126$3088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:50468$3119 + cell $not $not$libresoc.v:50141$3103 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:50468$3119_Y + connect \Y $not$libresoc.v:50141$3103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:50484$3135 + cell $not $not$libresoc.v:50157$3119 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:50484$3135_Y + connect \Y $not$libresoc.v:50157$3119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:50451$3102 + cell $or $or$libresoc.v:50124$3086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88532,10 +88042,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:50451$3102_Y + connect \Y $or$libresoc.v:50124$3086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:50462$3113 + cell $or $or$libresoc.v:50135$3097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88543,10 +88053,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:50462$3113_Y + connect \Y $or$libresoc.v:50135$3097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:50463$3114 + cell $or $or$libresoc.v:50136$3098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88554,10 +88064,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:50463$3114_Y + connect \Y $or$libresoc.v:50136$3098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:50464$3115 + cell $or $or$libresoc.v:50137$3099 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88565,10 +88075,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:50464$3115_Y + connect \Y $or$libresoc.v:50137$3099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:50465$3116 + cell $or $or$libresoc.v:50138$3100 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88576,10 +88086,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:50465$3116_Y + connect \Y $or$libresoc.v:50138$3100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:50469$3120 + cell $or $or$libresoc.v:50142$3104 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88587,10 +88097,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:50469$3120_Y + connect \Y $or$libresoc.v:50142$3104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:50479$3130 + cell $or $or$libresoc.v:50152$3114 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88598,90 +88108,90 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:50479$3130_Y + connect \Y $or$libresoc.v:50152$3114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:50428$3079 + cell $reduce_and $reduce_and$libresoc.v:50101$3063 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:50428$3079_Y + connect \Y $reduce_and$libresoc.v:50101$3063_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:50446$3097 + cell $reduce_or $reduce_or$libresoc.v:50119$3081 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:50446$3097_Y + connect \Y $reduce_or$libresoc.v:50119$3081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:50449$3100 + cell $reduce_or $reduce_or$libresoc.v:50122$3084 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:50449$3100_Y + connect \Y $reduce_or$libresoc.v:50122$3084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:50450$3101 + cell $reduce_or $reduce_or$libresoc.v:50123$3085 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:50450$3101_Y + connect \Y $reduce_or$libresoc.v:50123$3085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50473$3124 + cell $mux $ternary$libresoc.v:50146$3108 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:50473$3124_Y + connect \Y $ternary$libresoc.v:50146$3108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50474$3125 + cell $mux $ternary$libresoc.v:50147$3109 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:50474$3125_Y + connect \Y $ternary$libresoc.v:50147$3109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50475$3126 + cell $mux $ternary$libresoc.v:50148$3110 parameter \WIDTH 32 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:50475$3126_Y + connect \Y $ternary$libresoc.v:50148$3110_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50476$3127 + cell $mux $ternary$libresoc.v:50149$3111 parameter \WIDTH 4 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:50476$3127_Y + connect \Y $ternary$libresoc.v:50149$3111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50477$3128 + cell $mux $ternary$libresoc.v:50150$3112 parameter \WIDTH 4 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:50477$3128_Y + connect \Y $ternary$libresoc.v:50150$3112_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50478$3129 + cell $mux $ternary$libresoc.v:50151$3113 parameter \WIDTH 4 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:50478$3129_Y + connect \Y $ternary$libresoc.v:50151$3113_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:50545.11-50567.4" + attribute \src "libresoc.v:50218.11-50240.4" cell \alu_cr0 \alu_cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88706,7 +88216,7 @@ module \cr0 connect \rb \alu_cr0_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:50568.14-50574.4" + attribute \src "libresoc.v:50241.14-50247.4" cell \alu_l$16 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88715,7 +88225,7 @@ module \cr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:50575.15-50581.4" + attribute \src "libresoc.v:50248.15-50254.4" cell \alui_l$15 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88724,7 +88234,7 @@ module \cr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:50582.14-50588.4" + attribute \src "libresoc.v:50255.14-50261.4" cell \opc_l$11 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88733,7 +88243,7 @@ module \cr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:50589.14-50595.4" + attribute \src "libresoc.v:50262.14-50268.4" cell \req_l$12 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88742,7 +88252,7 @@ module \cr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:50596.14-50602.4" + attribute \src "libresoc.v:50269.14-50275.4" cell \rok_l$14 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88751,7 +88261,7 @@ module \cr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:50603.14-50608.4" + attribute \src "libresoc.v:50276.14-50281.4" cell \rst_l$13 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88759,7 +88269,7 @@ module \cr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:50609.14-50615.4" + attribute \src "libresoc.v:50282.14-50288.4" cell \src_l$10 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88767,472 +88277,472 @@ module \cr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:49886.7-49886.20" - process $proc$libresoc.v:49886$3258 + attribute \src "libresoc.v:49559.7-49559.20" + process $proc$libresoc.v:49559$3242 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50004.7-50004.24" - process $proc$libresoc.v:50004$3259 + attribute \src "libresoc.v:49677.7-49677.24" + process $proc$libresoc.v:49677$3243 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:50035.14-50035.47" - process $proc$libresoc.v:50035$3260 + attribute \src "libresoc.v:49708.14-49708.47" + process $proc$libresoc.v:49708$3244 assign { } { } assign $1\alu_cr0_cr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[13:0] end - attribute \src "libresoc.v:50039.14-50039.41" - process $proc$libresoc.v:50039$3261 + attribute \src "libresoc.v:49712.14-49712.41" + process $proc$libresoc.v:49712$3245 assign { } { } assign $1\alu_cr0_cr_op__insn[31:0] 0 sync always sync init update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:50118.13-50118.45" - process $proc$libresoc.v:50118$3262 + attribute \src "libresoc.v:49791.13-49791.45" + process $proc$libresoc.v:49791$3246 assign { } { } assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:50142.7-50142.26" - process $proc$libresoc.v:50142$3263 + attribute \src "libresoc.v:49815.7-49815.26" + process $proc$libresoc.v:49815$3247 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:50150.7-50150.25" - process $proc$libresoc.v:50150$3264 + attribute \src "libresoc.v:49823.7-49823.25" + process $proc$libresoc.v:49823$3248 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:50162.7-50162.27" - process $proc$libresoc.v:50162$3265 + attribute \src "libresoc.v:49835.7-49835.27" + process $proc$libresoc.v:49835$3249 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:50196.14-50196.47" - process $proc$libresoc.v:50196$3266 + attribute \src "libresoc.v:49869.14-49869.47" + process $proc$libresoc.v:49869$3250 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:50200.7-50200.27" - process $proc$libresoc.v:50200$3267 + attribute \src "libresoc.v:49873.7-49873.27" + process $proc$libresoc.v:49873$3251 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:50204.14-50204.38" - process $proc$libresoc.v:50204$3268 + attribute \src "libresoc.v:49877.14-49877.38" + process $proc$libresoc.v:49877$3252 assign { } { } assign $1\data_r1__full_cr[31:0] 0 sync always sync init update \data_r1__full_cr $1\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:50208.7-50208.33" - process $proc$libresoc.v:50208$3269 + attribute \src "libresoc.v:49881.7-49881.33" + process $proc$libresoc.v:49881$3253 assign { } { } assign $1\data_r1__full_cr_ok[0:0] 1'0 sync always sync init update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:50212.13-50212.33" - process $proc$libresoc.v:50212$3270 + attribute \src "libresoc.v:49885.13-49885.33" + process $proc$libresoc.v:49885$3254 assign { } { } assign $1\data_r2__cr_a[3:0] 4'0000 sync always sync init update \data_r2__cr_a $1\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:50216.7-50216.30" - process $proc$libresoc.v:50216$3271 + attribute \src "libresoc.v:49889.7-49889.30" + process $proc$libresoc.v:49889$3255 assign { } { } assign $1\data_r2__cr_a_ok[0:0] 1'0 sync always sync init update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:50235.7-50235.25" - process $proc$libresoc.v:50235$3272 + attribute \src "libresoc.v:49908.7-49908.25" + process $proc$libresoc.v:49908$3256 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:50239.7-50239.25" - process $proc$libresoc.v:50239$3273 + attribute \src "libresoc.v:49912.7-49912.25" + process $proc$libresoc.v:49912$3257 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:50339.13-50339.30" - process $proc$libresoc.v:50339$3274 + attribute \src "libresoc.v:50012.13-50012.30" + process $proc$libresoc.v:50012$3258 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:50347.13-50347.31" - process $proc$libresoc.v:50347$3275 + attribute \src "libresoc.v:50020.13-50020.31" + process $proc$libresoc.v:50020$3259 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:50351.13-50351.31" - process $proc$libresoc.v:50351$3276 + attribute \src "libresoc.v:50024.13-50024.31" + process $proc$libresoc.v:50024$3260 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:50363.7-50363.26" - process $proc$libresoc.v:50363$3277 + attribute \src "libresoc.v:50036.7-50036.26" + process $proc$libresoc.v:50036$3261 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:50367.7-50367.26" - process $proc$libresoc.v:50367$3278 + attribute \src "libresoc.v:50040.7-50040.26" + process $proc$libresoc.v:50040$3262 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:50371.7-50371.25" - process $proc$libresoc.v:50371$3279 + attribute \src "libresoc.v:50044.7-50044.25" + process $proc$libresoc.v:50044$3263 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:50375.7-50375.25" - process $proc$libresoc.v:50375$3280 + attribute \src "libresoc.v:50048.7-50048.25" + process $proc$libresoc.v:50048$3264 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:50395.13-50395.32" - process $proc$libresoc.v:50395$3281 + attribute \src "libresoc.v:50068.13-50068.32" + process $proc$libresoc.v:50068$3265 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:50399.13-50399.32" - process $proc$libresoc.v:50399$3282 + attribute \src "libresoc.v:50072.13-50072.32" + process $proc$libresoc.v:50072$3266 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:50403.14-50403.43" - process $proc$libresoc.v:50403$3283 + attribute \src "libresoc.v:50076.14-50076.43" + process $proc$libresoc.v:50076$3267 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:50407.14-50407.43" - process $proc$libresoc.v:50407$3284 + attribute \src "libresoc.v:50080.14-50080.43" + process $proc$libresoc.v:50080$3268 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:50411.14-50411.28" - process $proc$libresoc.v:50411$3285 + attribute \src "libresoc.v:50084.14-50084.28" + process $proc$libresoc.v:50084$3269 assign { } { } assign $1\src_r2[31:0] 0 sync always sync init update \src_r2 $1\src_r2[31:0] end - attribute \src "libresoc.v:50415.13-50415.26" - process $proc$libresoc.v:50415$3286 + attribute \src "libresoc.v:50088.13-50088.26" + process $proc$libresoc.v:50088$3270 assign { } { } assign $1\src_r3[3:0] 4'0000 sync always sync init update \src_r3 $1\src_r3[3:0] end - attribute \src "libresoc.v:50419.13-50419.26" - process $proc$libresoc.v:50419$3287 + attribute \src "libresoc.v:50092.13-50092.26" + process $proc$libresoc.v:50092$3271 assign { } { } assign $1\src_r4[3:0] 4'0000 sync always sync init update \src_r4 $1\src_r4[3:0] end - attribute \src "libresoc.v:50423.13-50423.26" - process $proc$libresoc.v:50423$3288 + attribute \src "libresoc.v:50096.13-50096.26" + process $proc$libresoc.v:50096$3272 assign { } { } assign $1\src_r5[3:0] 4'0000 sync always sync init update \src_r5 $1\src_r5[3:0] end - attribute \src "libresoc.v:50485.3-50486.39" - process $proc$libresoc.v:50485$3136 + attribute \src "libresoc.v:50158.3-50159.39" + process $proc$libresoc.v:50158$3120 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:50487.3-50488.43" - process $proc$libresoc.v:50487$3137 + attribute \src "libresoc.v:50160.3-50161.43" + process $proc$libresoc.v:50160$3121 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:50489.3-50490.29" - process $proc$libresoc.v:50489$3138 + attribute \src "libresoc.v:50162.3-50163.29" + process $proc$libresoc.v:50162$3122 assign { } { } assign $0\src_r5[3:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[3:0] end - attribute \src "libresoc.v:50491.3-50492.29" - process $proc$libresoc.v:50491$3139 + attribute \src "libresoc.v:50164.3-50165.29" + process $proc$libresoc.v:50164$3123 assign { } { } assign $0\src_r4[3:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[3:0] end - attribute \src "libresoc.v:50493.3-50494.29" - process $proc$libresoc.v:50493$3140 + attribute \src "libresoc.v:50166.3-50167.29" + process $proc$libresoc.v:50166$3124 assign { } { } assign $0\src_r3[3:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[3:0] end - attribute \src "libresoc.v:50495.3-50496.29" - process $proc$libresoc.v:50495$3141 + attribute \src "libresoc.v:50168.3-50169.29" + process $proc$libresoc.v:50168$3125 assign { } { } assign $0\src_r2[31:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[31:0] end - attribute \src "libresoc.v:50497.3-50498.29" - process $proc$libresoc.v:50497$3142 + attribute \src "libresoc.v:50170.3-50171.29" + process $proc$libresoc.v:50170$3126 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:50499.3-50500.29" - process $proc$libresoc.v:50499$3143 + attribute \src "libresoc.v:50172.3-50173.29" + process $proc$libresoc.v:50172$3127 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:50501.3-50502.43" - process $proc$libresoc.v:50501$3144 + attribute \src "libresoc.v:50174.3-50175.43" + process $proc$libresoc.v:50174$3128 assign { } { } assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next sync posedge \coresync_clk update \data_r2__cr_a $0\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:50503.3-50504.49" - process $proc$libresoc.v:50503$3145 + attribute \src "libresoc.v:50176.3-50177.49" + process $proc$libresoc.v:50176$3129 assign { } { } assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next sync posedge \coresync_clk update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:50505.3-50506.49" - process $proc$libresoc.v:50505$3146 + attribute \src "libresoc.v:50178.3-50179.49" + process $proc$libresoc.v:50178$3130 assign { } { } assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next sync posedge \coresync_clk update \data_r1__full_cr $0\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:50507.3-50508.55" - process $proc$libresoc.v:50507$3147 + attribute \src "libresoc.v:50180.3-50181.55" + process $proc$libresoc.v:50180$3131 assign { } { } assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next sync posedge \coresync_clk update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:50509.3-50510.37" - process $proc$libresoc.v:50509$3148 + attribute \src "libresoc.v:50182.3-50183.37" + process $proc$libresoc.v:50182$3132 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:50511.3-50512.43" - process $proc$libresoc.v:50511$3149 + attribute \src "libresoc.v:50184.3-50185.43" + process $proc$libresoc.v:50184$3133 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:50513.3-50514.65" - process $proc$libresoc.v:50513$3150 + attribute \src "libresoc.v:50186.3-50187.65" + process $proc$libresoc.v:50186$3134 assign { } { } assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:50515.3-50516.61" - process $proc$libresoc.v:50515$3151 + attribute \src "libresoc.v:50188.3-50189.61" + process $proc$libresoc.v:50188$3135 assign { } { } assign $0\alu_cr0_cr_op__fn_unit[13:0] \alu_cr0_cr_op__fn_unit$next sync posedge \coresync_clk update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[13:0] end - attribute \src "libresoc.v:50517.3-50518.55" - process $proc$libresoc.v:50517$3152 + attribute \src "libresoc.v:50190.3-50191.55" + process $proc$libresoc.v:50190$3136 assign { } { } assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:50519.3-50520.39" - process $proc$libresoc.v:50519$3153 + attribute \src "libresoc.v:50192.3-50193.39" + process $proc$libresoc.v:50192$3137 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:50521.3-50522.39" - process $proc$libresoc.v:50521$3154 + attribute \src "libresoc.v:50194.3-50195.39" + process $proc$libresoc.v:50194$3138 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:50523.3-50524.39" - process $proc$libresoc.v:50523$3155 + attribute \src "libresoc.v:50196.3-50197.39" + process $proc$libresoc.v:50196$3139 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:50525.3-50526.39" - process $proc$libresoc.v:50525$3156 + attribute \src "libresoc.v:50198.3-50199.39" + process $proc$libresoc.v:50198$3140 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:50527.3-50528.39" - process $proc$libresoc.v:50527$3157 + attribute \src "libresoc.v:50200.3-50201.39" + process $proc$libresoc.v:50200$3141 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:50529.3-50530.39" - process $proc$libresoc.v:50529$3158 + attribute \src "libresoc.v:50202.3-50203.39" + process $proc$libresoc.v:50202$3142 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:50531.3-50532.39" - process $proc$libresoc.v:50531$3159 + attribute \src "libresoc.v:50204.3-50205.39" + process $proc$libresoc.v:50204$3143 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:50533.3-50534.39" - process $proc$libresoc.v:50533$3160 + attribute \src "libresoc.v:50206.3-50207.39" + process $proc$libresoc.v:50206$3144 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:50535.3-50536.41" - process $proc$libresoc.v:50535$3161 + attribute \src "libresoc.v:50208.3-50209.41" + process $proc$libresoc.v:50208$3145 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:50537.3-50538.41" - process $proc$libresoc.v:50537$3162 + attribute \src "libresoc.v:50210.3-50211.41" + process $proc$libresoc.v:50210$3146 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:50539.3-50540.37" - process $proc$libresoc.v:50539$3163 + attribute \src "libresoc.v:50212.3-50213.37" + process $proc$libresoc.v:50212$3147 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:50541.3-50542.39" - process $proc$libresoc.v:50541$3164 + attribute \src "libresoc.v:50214.3-50215.39" + process $proc$libresoc.v:50214$3148 assign { } { } assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:50543.3-50544.25" - process $proc$libresoc.v:50543$3165 + attribute \src "libresoc.v:50216.3-50217.25" + process $proc$libresoc.v:50216$3149 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:50616.3-50625.6" - process $proc$libresoc.v:50616$3166 + attribute \src "libresoc.v:50289.3-50298.6" + process $proc$libresoc.v:50289$3150 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:50617.5-50617.29" + attribute \src "libresoc.v:50290.5-50290.29" switch \initial - attribute \src "libresoc.v:50617.9-50617.17" + attribute \src "libresoc.v:50290.9-50290.17" case 1'1 case end @@ -89248,14 +88758,14 @@ module \cr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:50626.3-50634.6" - process $proc$libresoc.v:50626$3167 + attribute \src "libresoc.v:50299.3-50307.6" + process $proc$libresoc.v:50299$3151 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$3168 $1\rok_l_s_rdok$next[0:0]$3169 - attribute \src "libresoc.v:50627.5-50627.29" + assign $0\rok_l_s_rdok$next[0:0]$3152 $1\rok_l_s_rdok$next[0:0]$3153 + attribute \src "libresoc.v:50300.5-50300.29" switch \initial - attribute \src "libresoc.v:50627.9-50627.17" + attribute \src "libresoc.v:50300.9-50300.17" case 1'1 case end @@ -89264,21 +88774,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$3169 1'0 + assign $1\rok_l_s_rdok$next[0:0]$3153 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$3169 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$3153 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3168 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3152 end - attribute \src "libresoc.v:50635.3-50643.6" - process $proc$libresoc.v:50635$3170 + attribute \src "libresoc.v:50308.3-50316.6" + process $proc$libresoc.v:50308$3154 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$3171 $1\rok_l_r_rdok$next[0:0]$3172 - attribute \src "libresoc.v:50636.5-50636.29" + assign $0\rok_l_r_rdok$next[0:0]$3155 $1\rok_l_r_rdok$next[0:0]$3156 + attribute \src "libresoc.v:50309.5-50309.29" switch \initial - attribute \src "libresoc.v:50636.9-50636.17" + attribute \src "libresoc.v:50309.9-50309.17" case 1'1 case end @@ -89287,21 +88797,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$3172 1'1 + assign $1\rok_l_r_rdok$next[0:0]$3156 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$3172 \$65 + assign $1\rok_l_r_rdok$next[0:0]$3156 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3171 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3155 end - attribute \src "libresoc.v:50644.3-50652.6" - process $proc$libresoc.v:50644$3173 + attribute \src "libresoc.v:50317.3-50325.6" + process $proc$libresoc.v:50317$3157 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$3174 $1\rst_l_s_rst$next[0:0]$3175 - attribute \src "libresoc.v:50645.5-50645.29" + assign $0\rst_l_s_rst$next[0:0]$3158 $1\rst_l_s_rst$next[0:0]$3159 + attribute \src "libresoc.v:50318.5-50318.29" switch \initial - attribute \src "libresoc.v:50645.9-50645.17" + attribute \src "libresoc.v:50318.9-50318.17" case 1'1 case end @@ -89310,21 +88820,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$3175 1'0 + assign $1\rst_l_s_rst$next[0:0]$3159 1'0 case - assign $1\rst_l_s_rst$next[0:0]$3175 \all_rd + assign $1\rst_l_s_rst$next[0:0]$3159 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3174 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3158 end - attribute \src "libresoc.v:50653.3-50661.6" - process $proc$libresoc.v:50653$3176 + attribute \src "libresoc.v:50326.3-50334.6" + process $proc$libresoc.v:50326$3160 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$3177 $1\rst_l_r_rst$next[0:0]$3178 - attribute \src "libresoc.v:50654.5-50654.29" + assign $0\rst_l_r_rst$next[0:0]$3161 $1\rst_l_r_rst$next[0:0]$3162 + attribute \src "libresoc.v:50327.5-50327.29" switch \initial - attribute \src "libresoc.v:50654.9-50654.17" + attribute \src "libresoc.v:50327.9-50327.17" case 1'1 case end @@ -89333,21 +88843,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$3178 1'1 + assign $1\rst_l_r_rst$next[0:0]$3162 1'1 case - assign $1\rst_l_r_rst$next[0:0]$3178 \rst_r + assign $1\rst_l_r_rst$next[0:0]$3162 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3177 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3161 end - attribute \src "libresoc.v:50662.3-50670.6" - process $proc$libresoc.v:50662$3179 + attribute \src "libresoc.v:50335.3-50343.6" + process $proc$libresoc.v:50335$3163 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$3180 $1\opc_l_s_opc$next[0:0]$3181 - attribute \src "libresoc.v:50663.5-50663.29" + assign $0\opc_l_s_opc$next[0:0]$3164 $1\opc_l_s_opc$next[0:0]$3165 + attribute \src "libresoc.v:50336.5-50336.29" switch \initial - attribute \src "libresoc.v:50663.9-50663.17" + attribute \src "libresoc.v:50336.9-50336.17" case 1'1 case end @@ -89356,21 +88866,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$3181 1'0 + assign $1\opc_l_s_opc$next[0:0]$3165 1'0 case - assign $1\opc_l_s_opc$next[0:0]$3181 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$3165 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3180 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3164 end - attribute \src "libresoc.v:50671.3-50679.6" - process $proc$libresoc.v:50671$3182 + attribute \src "libresoc.v:50344.3-50352.6" + process $proc$libresoc.v:50344$3166 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$3183 $1\opc_l_r_opc$next[0:0]$3184 - attribute \src "libresoc.v:50672.5-50672.29" + assign $0\opc_l_r_opc$next[0:0]$3167 $1\opc_l_r_opc$next[0:0]$3168 + attribute \src "libresoc.v:50345.5-50345.29" switch \initial - attribute \src "libresoc.v:50672.9-50672.17" + attribute \src "libresoc.v:50345.9-50345.17" case 1'1 case end @@ -89379,21 +88889,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$3184 1'1 + assign $1\opc_l_r_opc$next[0:0]$3168 1'1 case - assign $1\opc_l_r_opc$next[0:0]$3184 \req_done + assign $1\opc_l_r_opc$next[0:0]$3168 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3183 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3167 end - attribute \src "libresoc.v:50680.3-50688.6" - process $proc$libresoc.v:50680$3185 + attribute \src "libresoc.v:50353.3-50361.6" + process $proc$libresoc.v:50353$3169 assign { } { } assign { } { } - assign $0\src_l_s_src$next[5:0]$3186 $1\src_l_s_src$next[5:0]$3187 - attribute \src "libresoc.v:50681.5-50681.29" + assign $0\src_l_s_src$next[5:0]$3170 $1\src_l_s_src$next[5:0]$3171 + attribute \src "libresoc.v:50354.5-50354.29" switch \initial - attribute \src "libresoc.v:50681.9-50681.17" + attribute \src "libresoc.v:50354.9-50354.17" case 1'1 case end @@ -89402,21 +88912,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[5:0]$3187 6'000000 + assign $1\src_l_s_src$next[5:0]$3171 6'000000 case - assign $1\src_l_s_src$next[5:0]$3187 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[5:0]$3171 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3186 + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3170 end - attribute \src "libresoc.v:50689.3-50697.6" - process $proc$libresoc.v:50689$3188 + attribute \src "libresoc.v:50362.3-50370.6" + process $proc$libresoc.v:50362$3172 assign { } { } assign { } { } - assign $0\src_l_r_src$next[5:0]$3189 $1\src_l_r_src$next[5:0]$3190 - attribute \src "libresoc.v:50690.5-50690.29" + assign $0\src_l_r_src$next[5:0]$3173 $1\src_l_r_src$next[5:0]$3174 + attribute \src "libresoc.v:50363.5-50363.29" switch \initial - attribute \src "libresoc.v:50690.9-50690.17" + attribute \src "libresoc.v:50363.9-50363.17" case 1'1 case end @@ -89425,21 +88935,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[5:0]$3190 6'111111 + assign $1\src_l_r_src$next[5:0]$3174 6'111111 case - assign $1\src_l_r_src$next[5:0]$3190 \reset_r + assign $1\src_l_r_src$next[5:0]$3174 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3189 + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3173 end - attribute \src "libresoc.v:50698.3-50706.6" - process $proc$libresoc.v:50698$3191 + attribute \src "libresoc.v:50371.3-50379.6" + process $proc$libresoc.v:50371$3175 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$3192 $1\req_l_s_req$next[2:0]$3193 - attribute \src "libresoc.v:50699.5-50699.29" + assign $0\req_l_s_req$next[2:0]$3176 $1\req_l_s_req$next[2:0]$3177 + attribute \src "libresoc.v:50372.5-50372.29" switch \initial - attribute \src "libresoc.v:50699.9-50699.17" + attribute \src "libresoc.v:50372.9-50372.17" case 1'1 case end @@ -89448,21 +88958,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[2:0]$3193 3'000 + assign $1\req_l_s_req$next[2:0]$3177 3'000 case - assign $1\req_l_s_req$next[2:0]$3193 \$67 + assign $1\req_l_s_req$next[2:0]$3177 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3192 + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3176 end - attribute \src "libresoc.v:50707.3-50715.6" - process $proc$libresoc.v:50707$3194 + attribute \src "libresoc.v:50380.3-50388.6" + process $proc$libresoc.v:50380$3178 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$3195 $1\req_l_r_req$next[2:0]$3196 - attribute \src "libresoc.v:50708.5-50708.29" + assign $0\req_l_r_req$next[2:0]$3179 $1\req_l_r_req$next[2:0]$3180 + attribute \src "libresoc.v:50381.5-50381.29" switch \initial - attribute \src "libresoc.v:50708.9-50708.17" + attribute \src "libresoc.v:50381.9-50381.17" case 1'1 case end @@ -89471,27 +88981,27 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[2:0]$3196 3'111 + assign $1\req_l_r_req$next[2:0]$3180 3'111 case - assign $1\req_l_r_req$next[2:0]$3196 \$69 + assign $1\req_l_r_req$next[2:0]$3180 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3195 + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3179 end - attribute \src "libresoc.v:50716.3-50727.6" - process $proc$libresoc.v:50716$3197 + attribute \src "libresoc.v:50389.3-50400.6" + process $proc$libresoc.v:50389$3181 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 - assign $0\alu_cr0_cr_op__insn$next[31:0]$3199 $1\alu_cr0_cr_op__insn$next[31:0]$3202 - assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 - attribute \src "libresoc.v:50717.5-50717.29" + assign $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 + assign $0\alu_cr0_cr_op__insn$next[31:0]$3183 $1\alu_cr0_cr_op__insn$next[31:0]$3186 + assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 + attribute \src "libresoc.v:50390.5-50390.29" switch \initial - attribute \src "libresoc.v:50717.9-50717.17" + attribute \src "libresoc.v:50390.9-50390.17" case 1'1 case end @@ -89502,31 +89012,31 @@ module \cr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_cr0_cr_op__insn$next[31:0]$3202 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } + assign { $1\alu_cr0_cr_op__insn$next[31:0]$3186 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } case - assign $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 \alu_cr0_cr_op__fn_unit - assign $1\alu_cr0_cr_op__insn$next[31:0]$3202 \alu_cr0_cr_op__insn - assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 \alu_cr0_cr_op__insn_type + assign $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 \alu_cr0_cr_op__fn_unit + assign $1\alu_cr0_cr_op__insn$next[31:0]$3186 \alu_cr0_cr_op__insn + assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 \alu_cr0_cr_op__insn_type end sync always - update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 - update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3199 - update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 + update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 + update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3183 + update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 end - attribute \src "libresoc.v:50728.3-50749.6" - process $proc$libresoc.v:50728$3204 + attribute \src "libresoc.v:50401.3-50422.6" + process $proc$libresoc.v:50401$3188 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$3205 $2\data_r0__o$next[63:0]$3209 + assign $0\data_r0__o$next[63:0]$3189 $2\data_r0__o$next[63:0]$3193 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$3206 $3\data_r0__o_ok$next[0:0]$3211 - attribute \src "libresoc.v:50729.5-50729.29" + assign $0\data_r0__o_ok$next[0:0]$3190 $3\data_r0__o_ok$next[0:0]$3195 + attribute \src "libresoc.v:50402.5-50402.29" switch \initial - attribute \src "libresoc.v:50729.9-50729.17" + attribute \src "libresoc.v:50402.9-50402.17" case 1'1 case end @@ -89536,10 +89046,10 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$3208 $1\data_r0__o$next[63:0]$3207 } { \o_ok \alu_cr0_o } + assign { $1\data_r0__o_ok$next[0:0]$3192 $1\data_r0__o$next[63:0]$3191 } { \o_ok \alu_cr0_o } case - assign $1\data_r0__o$next[63:0]$3207 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$3208 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$3191 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$3192 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -89547,38 +89057,38 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$3210 $2\data_r0__o$next[63:0]$3209 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$3194 $2\data_r0__o$next[63:0]$3193 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$3209 $1\data_r0__o$next[63:0]$3207 - assign $2\data_r0__o_ok$next[0:0]$3210 $1\data_r0__o_ok$next[0:0]$3208 + assign $2\data_r0__o$next[63:0]$3193 $1\data_r0__o$next[63:0]$3191 + assign $2\data_r0__o_ok$next[0:0]$3194 $1\data_r0__o_ok$next[0:0]$3192 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$3211 1'0 + assign $3\data_r0__o_ok$next[0:0]$3195 1'0 case - assign $3\data_r0__o_ok$next[0:0]$3211 $2\data_r0__o_ok$next[0:0]$3210 + assign $3\data_r0__o_ok$next[0:0]$3195 $2\data_r0__o_ok$next[0:0]$3194 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$3205 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3206 + update \data_r0__o$next $0\data_r0__o$next[63:0]$3189 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3190 end - attribute \src "libresoc.v:50750.3-50771.6" - process $proc$libresoc.v:50750$3212 + attribute \src "libresoc.v:50423.3-50444.6" + process $proc$libresoc.v:50423$3196 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__full_cr$next[31:0]$3213 $2\data_r1__full_cr$next[31:0]$3217 + assign $0\data_r1__full_cr$next[31:0]$3197 $2\data_r1__full_cr$next[31:0]$3201 assign { } { } - assign $0\data_r1__full_cr_ok$next[0:0]$3214 $3\data_r1__full_cr_ok$next[0:0]$3219 - attribute \src "libresoc.v:50751.5-50751.29" + assign $0\data_r1__full_cr_ok$next[0:0]$3198 $3\data_r1__full_cr_ok$next[0:0]$3203 + attribute \src "libresoc.v:50424.5-50424.29" switch \initial - attribute \src "libresoc.v:50751.9-50751.17" + attribute \src "libresoc.v:50424.9-50424.17" case 1'1 case end @@ -89588,10 +89098,10 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__full_cr_ok$next[0:0]$3216 $1\data_r1__full_cr$next[31:0]$3215 } { \full_cr_ok \alu_cr0_full_cr } + assign { $1\data_r1__full_cr_ok$next[0:0]$3200 $1\data_r1__full_cr$next[31:0]$3199 } { \full_cr_ok \alu_cr0_full_cr } case - assign $1\data_r1__full_cr$next[31:0]$3215 \data_r1__full_cr - assign $1\data_r1__full_cr_ok$next[0:0]$3216 \data_r1__full_cr_ok + assign $1\data_r1__full_cr$next[31:0]$3199 \data_r1__full_cr + assign $1\data_r1__full_cr_ok$next[0:0]$3200 \data_r1__full_cr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -89599,38 +89109,38 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__full_cr_ok$next[0:0]$3218 $2\data_r1__full_cr$next[31:0]$3217 } 33'000000000000000000000000000000000 + assign { $2\data_r1__full_cr_ok$next[0:0]$3202 $2\data_r1__full_cr$next[31:0]$3201 } 33'000000000000000000000000000000000 case - assign $2\data_r1__full_cr$next[31:0]$3217 $1\data_r1__full_cr$next[31:0]$3215 - assign $2\data_r1__full_cr_ok$next[0:0]$3218 $1\data_r1__full_cr_ok$next[0:0]$3216 + assign $2\data_r1__full_cr$next[31:0]$3201 $1\data_r1__full_cr$next[31:0]$3199 + assign $2\data_r1__full_cr_ok$next[0:0]$3202 $1\data_r1__full_cr_ok$next[0:0]$3200 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__full_cr_ok$next[0:0]$3219 1'0 + assign $3\data_r1__full_cr_ok$next[0:0]$3203 1'0 case - assign $3\data_r1__full_cr_ok$next[0:0]$3219 $2\data_r1__full_cr_ok$next[0:0]$3218 + assign $3\data_r1__full_cr_ok$next[0:0]$3203 $2\data_r1__full_cr_ok$next[0:0]$3202 end sync always - update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3213 - update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3214 + update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3197 + update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3198 end - attribute \src "libresoc.v:50772.3-50793.6" - process $proc$libresoc.v:50772$3220 + attribute \src "libresoc.v:50445.3-50466.6" + process $proc$libresoc.v:50445$3204 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__cr_a$next[3:0]$3221 $2\data_r2__cr_a$next[3:0]$3225 + assign $0\data_r2__cr_a$next[3:0]$3205 $2\data_r2__cr_a$next[3:0]$3209 assign { } { } - assign $0\data_r2__cr_a_ok$next[0:0]$3222 $3\data_r2__cr_a_ok$next[0:0]$3227 - attribute \src "libresoc.v:50773.5-50773.29" + assign $0\data_r2__cr_a_ok$next[0:0]$3206 $3\data_r2__cr_a_ok$next[0:0]$3211 + attribute \src "libresoc.v:50446.5-50446.29" switch \initial - attribute \src "libresoc.v:50773.9-50773.17" + attribute \src "libresoc.v:50446.9-50446.17" case 1'1 case end @@ -89640,10 +89150,10 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__cr_a_ok$next[0:0]$3224 $1\data_r2__cr_a$next[3:0]$3223 } { \cr_a_ok \alu_cr0_cr_a } + assign { $1\data_r2__cr_a_ok$next[0:0]$3208 $1\data_r2__cr_a$next[3:0]$3207 } { \cr_a_ok \alu_cr0_cr_a } case - assign $1\data_r2__cr_a$next[3:0]$3223 \data_r2__cr_a - assign $1\data_r2__cr_a_ok$next[0:0]$3224 \data_r2__cr_a_ok + assign $1\data_r2__cr_a$next[3:0]$3207 \data_r2__cr_a + assign $1\data_r2__cr_a_ok$next[0:0]$3208 \data_r2__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -89651,32 +89161,32 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__cr_a_ok$next[0:0]$3226 $2\data_r2__cr_a$next[3:0]$3225 } 5'00000 + assign { $2\data_r2__cr_a_ok$next[0:0]$3210 $2\data_r2__cr_a$next[3:0]$3209 } 5'00000 case - assign $2\data_r2__cr_a$next[3:0]$3225 $1\data_r2__cr_a$next[3:0]$3223 - assign $2\data_r2__cr_a_ok$next[0:0]$3226 $1\data_r2__cr_a_ok$next[0:0]$3224 + assign $2\data_r2__cr_a$next[3:0]$3209 $1\data_r2__cr_a$next[3:0]$3207 + assign $2\data_r2__cr_a_ok$next[0:0]$3210 $1\data_r2__cr_a_ok$next[0:0]$3208 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__cr_a_ok$next[0:0]$3227 1'0 + assign $3\data_r2__cr_a_ok$next[0:0]$3211 1'0 case - assign $3\data_r2__cr_a_ok$next[0:0]$3227 $2\data_r2__cr_a_ok$next[0:0]$3226 + assign $3\data_r2__cr_a_ok$next[0:0]$3211 $2\data_r2__cr_a_ok$next[0:0]$3210 end sync always - update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3221 - update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3222 + update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3205 + update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3206 end - attribute \src "libresoc.v:50794.3-50803.6" - process $proc$libresoc.v:50794$3228 + attribute \src "libresoc.v:50467.3-50476.6" + process $proc$libresoc.v:50467$3212 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$3229 $1\src_r0$next[63:0]$3230 - attribute \src "libresoc.v:50795.5-50795.29" + assign $0\src_r0$next[63:0]$3213 $1\src_r0$next[63:0]$3214 + attribute \src "libresoc.v:50468.5-50468.29" switch \initial - attribute \src "libresoc.v:50795.9-50795.17" + attribute \src "libresoc.v:50468.9-50468.17" case 1'1 case end @@ -89685,21 +89195,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$3230 \src1_i + assign $1\src_r0$next[63:0]$3214 \src1_i case - assign $1\src_r0$next[63:0]$3230 \src_r0 + assign $1\src_r0$next[63:0]$3214 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$3229 + update \src_r0$next $0\src_r0$next[63:0]$3213 end - attribute \src "libresoc.v:50804.3-50813.6" - process $proc$libresoc.v:50804$3231 + attribute \src "libresoc.v:50477.3-50486.6" + process $proc$libresoc.v:50477$3215 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$3232 $1\src_r1$next[63:0]$3233 - attribute \src "libresoc.v:50805.5-50805.29" + assign $0\src_r1$next[63:0]$3216 $1\src_r1$next[63:0]$3217 + attribute \src "libresoc.v:50478.5-50478.29" switch \initial - attribute \src "libresoc.v:50805.9-50805.17" + attribute \src "libresoc.v:50478.9-50478.17" case 1'1 case end @@ -89708,21 +89218,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$3233 \src2_i + assign $1\src_r1$next[63:0]$3217 \src2_i case - assign $1\src_r1$next[63:0]$3233 \src_r1 + assign $1\src_r1$next[63:0]$3217 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$3232 + update \src_r1$next $0\src_r1$next[63:0]$3216 end - attribute \src "libresoc.v:50814.3-50823.6" - process $proc$libresoc.v:50814$3234 + attribute \src "libresoc.v:50487.3-50496.6" + process $proc$libresoc.v:50487$3218 assign { } { } assign { } { } - assign $0\src_r2$next[31:0]$3235 $1\src_r2$next[31:0]$3236 - attribute \src "libresoc.v:50815.5-50815.29" + assign $0\src_r2$next[31:0]$3219 $1\src_r2$next[31:0]$3220 + attribute \src "libresoc.v:50488.5-50488.29" switch \initial - attribute \src "libresoc.v:50815.9-50815.17" + attribute \src "libresoc.v:50488.9-50488.17" case 1'1 case end @@ -89731,21 +89241,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[31:0]$3236 \src3_i + assign $1\src_r2$next[31:0]$3220 \src3_i case - assign $1\src_r2$next[31:0]$3236 \src_r2 + assign $1\src_r2$next[31:0]$3220 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[31:0]$3235 + update \src_r2$next $0\src_r2$next[31:0]$3219 end - attribute \src "libresoc.v:50824.3-50833.6" - process $proc$libresoc.v:50824$3237 + attribute \src "libresoc.v:50497.3-50506.6" + process $proc$libresoc.v:50497$3221 assign { } { } assign { } { } - assign $0\src_r3$next[3:0]$3238 $1\src_r3$next[3:0]$3239 - attribute \src "libresoc.v:50825.5-50825.29" + assign $0\src_r3$next[3:0]$3222 $1\src_r3$next[3:0]$3223 + attribute \src "libresoc.v:50498.5-50498.29" switch \initial - attribute \src "libresoc.v:50825.9-50825.17" + attribute \src "libresoc.v:50498.9-50498.17" case 1'1 case end @@ -89754,21 +89264,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[3:0]$3239 \src4_i + assign $1\src_r3$next[3:0]$3223 \src4_i case - assign $1\src_r3$next[3:0]$3239 \src_r3 + assign $1\src_r3$next[3:0]$3223 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[3:0]$3238 + update \src_r3$next $0\src_r3$next[3:0]$3222 end - attribute \src "libresoc.v:50834.3-50843.6" - process $proc$libresoc.v:50834$3240 + attribute \src "libresoc.v:50507.3-50516.6" + process $proc$libresoc.v:50507$3224 assign { } { } assign { } { } - assign $0\src_r4$next[3:0]$3241 $1\src_r4$next[3:0]$3242 - attribute \src "libresoc.v:50835.5-50835.29" + assign $0\src_r4$next[3:0]$3225 $1\src_r4$next[3:0]$3226 + attribute \src "libresoc.v:50508.5-50508.29" switch \initial - attribute \src "libresoc.v:50835.9-50835.17" + attribute \src "libresoc.v:50508.9-50508.17" case 1'1 case end @@ -89777,21 +89287,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[3:0]$3242 \src5_i + assign $1\src_r4$next[3:0]$3226 \src5_i case - assign $1\src_r4$next[3:0]$3242 \src_r4 + assign $1\src_r4$next[3:0]$3226 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[3:0]$3241 + update \src_r4$next $0\src_r4$next[3:0]$3225 end - attribute \src "libresoc.v:50844.3-50853.6" - process $proc$libresoc.v:50844$3243 + attribute \src "libresoc.v:50517.3-50526.6" + process $proc$libresoc.v:50517$3227 assign { } { } assign { } { } - assign $0\src_r5$next[3:0]$3244 $1\src_r5$next[3:0]$3245 - attribute \src "libresoc.v:50845.5-50845.29" + assign $0\src_r5$next[3:0]$3228 $1\src_r5$next[3:0]$3229 + attribute \src "libresoc.v:50518.5-50518.29" switch \initial - attribute \src "libresoc.v:50845.9-50845.17" + attribute \src "libresoc.v:50518.9-50518.17" case 1'1 case end @@ -89800,21 +89310,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r5$next[3:0]$3245 \src6_i + assign $1\src_r5$next[3:0]$3229 \src6_i case - assign $1\src_r5$next[3:0]$3245 \src_r5 + assign $1\src_r5$next[3:0]$3229 \src_r5 end sync always - update \src_r5$next $0\src_r5$next[3:0]$3244 + update \src_r5$next $0\src_r5$next[3:0]$3228 end - attribute \src "libresoc.v:50854.3-50862.6" - process $proc$libresoc.v:50854$3246 + attribute \src "libresoc.v:50527.3-50535.6" + process $proc$libresoc.v:50527$3230 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$3247 $1\alui_l_r_alui$next[0:0]$3248 - attribute \src "libresoc.v:50855.5-50855.29" + assign $0\alui_l_r_alui$next[0:0]$3231 $1\alui_l_r_alui$next[0:0]$3232 + attribute \src "libresoc.v:50528.5-50528.29" switch \initial - attribute \src "libresoc.v:50855.9-50855.17" + attribute \src "libresoc.v:50528.9-50528.17" case 1'1 case end @@ -89823,21 +89333,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$3248 1'1 + assign $1\alui_l_r_alui$next[0:0]$3232 1'1 case - assign $1\alui_l_r_alui$next[0:0]$3248 \$89 + assign $1\alui_l_r_alui$next[0:0]$3232 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3247 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3231 end - attribute \src "libresoc.v:50863.3-50871.6" - process $proc$libresoc.v:50863$3249 + attribute \src "libresoc.v:50536.3-50544.6" + process $proc$libresoc.v:50536$3233 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$3250 $1\alu_l_r_alu$next[0:0]$3251 - attribute \src "libresoc.v:50864.5-50864.29" + assign $0\alu_l_r_alu$next[0:0]$3234 $1\alu_l_r_alu$next[0:0]$3235 + attribute \src "libresoc.v:50537.5-50537.29" switch \initial - attribute \src "libresoc.v:50864.9-50864.17" + attribute \src "libresoc.v:50537.9-50537.17" case 1'1 case end @@ -89846,21 +89356,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$3251 1'1 + assign $1\alu_l_r_alu$next[0:0]$3235 1'1 case - assign $1\alu_l_r_alu$next[0:0]$3251 \$91 + assign $1\alu_l_r_alu$next[0:0]$3235 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3250 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3234 end - attribute \src "libresoc.v:50872.3-50881.6" - process $proc$libresoc.v:50872$3252 + attribute \src "libresoc.v:50545.3-50554.6" + process $proc$libresoc.v:50545$3236 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:50873.5-50873.29" + attribute \src "libresoc.v:50546.5-50546.29" switch \initial - attribute \src "libresoc.v:50873.9-50873.17" + attribute \src "libresoc.v:50546.9-50546.17" case 1'1 case end @@ -89876,14 +89386,14 @@ module \cr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:50882.3-50891.6" - process $proc$libresoc.v:50882$3253 + attribute \src "libresoc.v:50555.3-50564.6" + process $proc$libresoc.v:50555$3237 assign { } { } assign { } { } assign $0\dest2_o[31:0] $1\dest2_o[31:0] - attribute \src "libresoc.v:50883.5-50883.29" + attribute \src "libresoc.v:50556.5-50556.29" switch \initial - attribute \src "libresoc.v:50883.9-50883.17" + attribute \src "libresoc.v:50556.9-50556.17" case 1'1 case end @@ -89899,14 +89409,14 @@ module \cr0 sync always update \dest2_o $0\dest2_o[31:0] end - attribute \src "libresoc.v:50892.3-50901.6" - process $proc$libresoc.v:50892$3254 + attribute \src "libresoc.v:50565.3-50574.6" + process $proc$libresoc.v:50565$3238 assign { } { } assign { } { } assign $0\dest3_o[3:0] $1\dest3_o[3:0] - attribute \src "libresoc.v:50893.5-50893.29" + attribute \src "libresoc.v:50566.5-50566.29" switch \initial - attribute \src "libresoc.v:50893.9-50893.17" + attribute \src "libresoc.v:50566.9-50566.17" case 1'1 case end @@ -89922,14 +89432,14 @@ module \cr0 sync always update \dest3_o $0\dest3_o[3:0] end - attribute \src "libresoc.v:50902.3-50910.6" - process $proc$libresoc.v:50902$3255 + attribute \src "libresoc.v:50575.3-50583.6" + process $proc$libresoc.v:50575$3239 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$3256 $1\prev_wr_go$next[2:0]$3257 - attribute \src "libresoc.v:50903.5-50903.29" + assign $0\prev_wr_go$next[2:0]$3240 $1\prev_wr_go$next[2:0]$3241 + attribute \src "libresoc.v:50576.5-50576.29" switch \initial - attribute \src "libresoc.v:50903.9-50903.17" + attribute \src "libresoc.v:50576.9-50576.17" case 1'1 case end @@ -89938,70 +89448,70 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[2:0]$3257 3'000 - case - assign $1\prev_wr_go$next[2:0]$3257 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3256 - end - connect \$5 $reduce_and$libresoc.v:50428$3079_Y - connect \$99 $and$libresoc.v:50429$3080_Y - connect \$101 $and$libresoc.v:50430$3081_Y - connect \$103 $and$libresoc.v:50431$3082_Y - connect \$105 $and$libresoc.v:50432$3083_Y - connect \$107 $and$libresoc.v:50433$3084_Y - connect \$109 $and$libresoc.v:50434$3085_Y - connect \$111 $and$libresoc.v:50435$3086_Y - connect \$113 $and$libresoc.v:50436$3087_Y - connect \$115 $and$libresoc.v:50437$3088_Y - connect \$11 $and$libresoc.v:50438$3089_Y - connect \$13 $not$libresoc.v:50439$3090_Y - connect \$15 $and$libresoc.v:50440$3091_Y - connect \$17 $not$libresoc.v:50441$3092_Y - connect \$19 $and$libresoc.v:50442$3093_Y - connect \$21 $and$libresoc.v:50443$3094_Y - connect \$25 $not$libresoc.v:50444$3095_Y - connect \$27 $and$libresoc.v:50445$3096_Y - connect \$24 $reduce_or$libresoc.v:50446$3097_Y - connect \$23 $not$libresoc.v:50447$3098_Y - connect \$31 $and$libresoc.v:50448$3099_Y - connect \$33 $reduce_or$libresoc.v:50449$3100_Y - connect \$35 $reduce_or$libresoc.v:50450$3101_Y - connect \$37 $or$libresoc.v:50451$3102_Y - connect \$3 $and$libresoc.v:50452$3103_Y - connect \$39 $not$libresoc.v:50453$3104_Y - connect \$41 $and$libresoc.v:50454$3105_Y - connect \$43 $and$libresoc.v:50455$3106_Y - connect \$45 $eq$libresoc.v:50456$3107_Y - connect \$47 $and$libresoc.v:50457$3108_Y - connect \$49 $eq$libresoc.v:50458$3109_Y - connect \$51 $and$libresoc.v:50459$3110_Y - connect \$53 $and$libresoc.v:50460$3111_Y - connect \$55 $and$libresoc.v:50461$3112_Y - connect \$57 $or$libresoc.v:50462$3113_Y - connect \$59 $or$libresoc.v:50463$3114_Y - connect \$61 $or$libresoc.v:50464$3115_Y - connect \$63 $or$libresoc.v:50465$3116_Y - connect \$65 $and$libresoc.v:50466$3117_Y - connect \$67 $and$libresoc.v:50467$3118_Y - connect \$6 $not$libresoc.v:50468$3119_Y - connect \$69 $or$libresoc.v:50469$3120_Y - connect \$71 $and$libresoc.v:50470$3121_Y - connect \$73 $and$libresoc.v:50471$3122_Y - connect \$75 $and$libresoc.v:50472$3123_Y - connect \$77 $ternary$libresoc.v:50473$3124_Y - connect \$79 $ternary$libresoc.v:50474$3125_Y - connect \$81 $ternary$libresoc.v:50475$3126_Y - connect \$83 $ternary$libresoc.v:50476$3127_Y - connect \$85 $ternary$libresoc.v:50477$3128_Y - connect \$87 $ternary$libresoc.v:50478$3129_Y - connect \$8 $or$libresoc.v:50479$3130_Y - connect \$89 $and$libresoc.v:50480$3131_Y - connect \$91 $and$libresoc.v:50481$3132_Y - connect \$93 $and$libresoc.v:50482$3133_Y - connect \$95 $and$libresoc.v:50483$3134_Y - connect \$97 $not$libresoc.v:50484$3135_Y + assign $1\prev_wr_go$next[2:0]$3241 3'000 + case + assign $1\prev_wr_go$next[2:0]$3241 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3240 + end + connect \$5 $reduce_and$libresoc.v:50101$3063_Y + connect \$99 $and$libresoc.v:50102$3064_Y + connect \$101 $and$libresoc.v:50103$3065_Y + connect \$103 $and$libresoc.v:50104$3066_Y + connect \$105 $and$libresoc.v:50105$3067_Y + connect \$107 $and$libresoc.v:50106$3068_Y + connect \$109 $and$libresoc.v:50107$3069_Y + connect \$111 $and$libresoc.v:50108$3070_Y + connect \$113 $and$libresoc.v:50109$3071_Y + connect \$115 $and$libresoc.v:50110$3072_Y + connect \$11 $and$libresoc.v:50111$3073_Y + connect \$13 $not$libresoc.v:50112$3074_Y + connect \$15 $and$libresoc.v:50113$3075_Y + connect \$17 $not$libresoc.v:50114$3076_Y + connect \$19 $and$libresoc.v:50115$3077_Y + connect \$21 $and$libresoc.v:50116$3078_Y + connect \$25 $not$libresoc.v:50117$3079_Y + connect \$27 $and$libresoc.v:50118$3080_Y + connect \$24 $reduce_or$libresoc.v:50119$3081_Y + connect \$23 $not$libresoc.v:50120$3082_Y + connect \$31 $and$libresoc.v:50121$3083_Y + connect \$33 $reduce_or$libresoc.v:50122$3084_Y + connect \$35 $reduce_or$libresoc.v:50123$3085_Y + connect \$37 $or$libresoc.v:50124$3086_Y + connect \$3 $and$libresoc.v:50125$3087_Y + connect \$39 $not$libresoc.v:50126$3088_Y + connect \$41 $and$libresoc.v:50127$3089_Y + connect \$43 $and$libresoc.v:50128$3090_Y + connect \$45 $eq$libresoc.v:50129$3091_Y + connect \$47 $and$libresoc.v:50130$3092_Y + connect \$49 $eq$libresoc.v:50131$3093_Y + connect \$51 $and$libresoc.v:50132$3094_Y + connect \$53 $and$libresoc.v:50133$3095_Y + connect \$55 $and$libresoc.v:50134$3096_Y + connect \$57 $or$libresoc.v:50135$3097_Y + connect \$59 $or$libresoc.v:50136$3098_Y + connect \$61 $or$libresoc.v:50137$3099_Y + connect \$63 $or$libresoc.v:50138$3100_Y + connect \$65 $and$libresoc.v:50139$3101_Y + connect \$67 $and$libresoc.v:50140$3102_Y + connect \$6 $not$libresoc.v:50141$3103_Y + connect \$69 $or$libresoc.v:50142$3104_Y + connect \$71 $and$libresoc.v:50143$3105_Y + connect \$73 $and$libresoc.v:50144$3106_Y + connect \$75 $and$libresoc.v:50145$3107_Y + connect \$77 $ternary$libresoc.v:50146$3108_Y + connect \$79 $ternary$libresoc.v:50147$3109_Y + connect \$81 $ternary$libresoc.v:50148$3110_Y + connect \$83 $ternary$libresoc.v:50149$3111_Y + connect \$85 $ternary$libresoc.v:50150$3112_Y + connect \$87 $ternary$libresoc.v:50151$3113_Y + connect \$8 $or$libresoc.v:50152$3114_Y + connect \$89 $and$libresoc.v:50153$3115_Y + connect \$91 $and$libresoc.v:50154$3116_Y + connect \$93 $and$libresoc.v:50155$3117_Y + connect \$95 $and$libresoc.v:50156$3118_Y + connect \$97 $not$libresoc.v:50157$3119_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 @@ -90034,31 +89544,31 @@ module \cr0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:50946.1-50995.10" +attribute \src "libresoc.v:50619.1-50668.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l" attribute \generator "nMigen" module \cyc_l - attribute \src "libresoc.v:50947.7-50947.20" + attribute \src "libresoc.v:50620.7-50620.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50983.3-50991.6" - wire $0\q_int$next[0:0]$3296 - attribute \src "libresoc.v:50981.3-50982.27" + attribute \src "libresoc.v:50656.3-50664.6" + wire $0\q_int$next[0:0]$3280 + attribute \src "libresoc.v:50654.3-50655.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:50983.3-50991.6" - wire $1\q_int$next[0:0]$3297 - attribute \src "libresoc.v:50965.7-50965.19" + attribute \src "libresoc.v:50656.3-50664.6" + wire $1\q_int$next[0:0]$3281 + attribute \src "libresoc.v:50638.7-50638.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:50978.17-50978.96" - wire $and$libresoc.v:50978$3291_Y - attribute \src "libresoc.v:50977.17-50977.92" - wire $not$libresoc.v:50977$3290_Y - attribute \src "libresoc.v:50980.17-50980.92" - wire $not$libresoc.v:50980$3293_Y - attribute \src "libresoc.v:50976.17-50976.98" - wire $or$libresoc.v:50976$3289_Y - attribute \src "libresoc.v:50979.17-50979.97" - wire $or$libresoc.v:50979$3292_Y + attribute \src "libresoc.v:50651.17-50651.96" + wire $and$libresoc.v:50651$3275_Y + attribute \src "libresoc.v:50650.17-50650.92" + wire $not$libresoc.v:50650$3274_Y + attribute \src "libresoc.v:50653.17-50653.92" + wire $not$libresoc.v:50653$3277_Y + attribute \src "libresoc.v:50649.17-50649.98" + wire $or$libresoc.v:50649$3273_Y + attribute \src "libresoc.v:50652.17-50652.97" + wire $or$libresoc.v:50652$3276_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -90069,11 +89579,11 @@ module \cyc_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:50947.7-50947.15" + attribute \src "libresoc.v:50620.7-50620.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_cyc @@ -90090,7 +89600,7 @@ module \cyc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:50978$3291 + cell $and $and$libresoc.v:50651$3275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90098,26 +89608,26 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:50978$3291_Y + connect \Y $and$libresoc.v:50651$3275_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:50977$3290 + cell $not $not$libresoc.v:50650$3274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_cyc - connect \Y $not$libresoc.v:50977$3290_Y + connect \Y $not$libresoc.v:50650$3274_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:50980$3293 + cell $not $not$libresoc.v:50653$3277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_cyc - connect \Y $not$libresoc.v:50980$3293_Y + connect \Y $not$libresoc.v:50653$3277_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:50976$3289 + cell $or $or$libresoc.v:50649$3273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90125,10 +89635,10 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_cyc connect \B \q_int - connect \Y $or$libresoc.v:50976$3289_Y + connect \Y $or$libresoc.v:50649$3273_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:50979$3292 + cell $or $or$libresoc.v:50652$3276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90136,39 +89646,39 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_cyc - connect \Y $or$libresoc.v:50979$3292_Y + connect \Y $or$libresoc.v:50652$3276_Y end - attribute \src "libresoc.v:50947.7-50947.20" - process $proc$libresoc.v:50947$3298 + attribute \src "libresoc.v:50620.7-50620.20" + process $proc$libresoc.v:50620$3282 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50965.7-50965.19" - process $proc$libresoc.v:50965$3299 + attribute \src "libresoc.v:50638.7-50638.19" + process $proc$libresoc.v:50638$3283 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:50981.3-50982.27" - process $proc$libresoc.v:50981$3294 + attribute \src "libresoc.v:50654.3-50655.27" + process $proc$libresoc.v:50654$3278 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:50983.3-50991.6" - process $proc$libresoc.v:50983$3295 + attribute \src "libresoc.v:50656.3-50664.6" + process $proc$libresoc.v:50656$3279 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$3296 $1\q_int$next[0:0]$3297 - attribute \src "libresoc.v:50984.5-50984.29" + assign $0\q_int$next[0:0]$3280 $1\q_int$next[0:0]$3281 + attribute \src "libresoc.v:50657.5-50657.29" switch \initial - attribute \src "libresoc.v:50984.9-50984.17" + attribute \src "libresoc.v:50657.9-50657.17" case 1'1 case end @@ -90177,331 +89687,331 @@ module \cyc_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$3297 1'0 + assign $1\q_int$next[0:0]$3281 1'0 case - assign $1\q_int$next[0:0]$3297 \$5 + assign $1\q_int$next[0:0]$3281 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$3296 + update \q_int$next $0\q_int$next[0:0]$3280 end - connect \$9 $or$libresoc.v:50976$3289_Y - connect \$1 $not$libresoc.v:50977$3290_Y - connect \$3 $and$libresoc.v:50978$3291_Y - connect \$5 $or$libresoc.v:50979$3292_Y - connect \$7 $not$libresoc.v:50980$3293_Y + connect \$9 $or$libresoc.v:50649$3273_Y + connect \$1 $not$libresoc.v:50650$3274_Y + connect \$3 $and$libresoc.v:50651$3275_Y + connect \$5 $or$libresoc.v:50652$3276_Y + connect \$7 $not$libresoc.v:50653$3277_Y connect \qlq_cyc \$9 connect \qn_cyc \$7 connect \q_cyc \q_int end -attribute \src "libresoc.v:50999.1-51731.10" +attribute \src "libresoc.v:50672.1-51413.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dbg" attribute \generator "nMigen" module \dbg - attribute \src "libresoc.v:51544.3-51553.6" + attribute \src "libresoc.v:51217.3-51229.6" wire $0\d_cr_req[0:0] - attribute \src "libresoc.v:51351.3-51360.6" + attribute \src "libresoc.v:51024.3-51033.6" wire $0\d_gpr_req[0:0] - attribute \src "libresoc.v:51554.3-51563.6" + attribute \src "libresoc.v:51230.3-51245.6" wire $0\d_xer_req[0:0] - attribute \src "libresoc.v:51333.3-51350.6" + attribute \src "libresoc.v:51006.3-51023.6" wire $0\dmi_ack_o[0:0] - attribute \src "libresoc.v:51564.3-51597.6" + attribute \src "libresoc.v:51246.3-51279.6" wire width 64 $0\dmi_dout[63:0] - attribute \src "libresoc.v:51535.3-51543.6" - wire $0\dmi_read_log_data$next[0:0]$3414 - attribute \src "libresoc.v:51311.3-51312.51" + attribute \src "libresoc.v:51208.3-51216.6" + wire $0\dmi_read_log_data$next[0:0]$3398 + attribute \src "libresoc.v:50984.3-50985.51" wire $0\dmi_read_log_data[0:0] - attribute \src "libresoc.v:51526.3-51534.6" - wire $0\dmi_read_log_data_1$next[0:0]$3411 - attribute \src "libresoc.v:51313.3-51314.55" + attribute \src "libresoc.v:51199.3-51207.6" + wire $0\dmi_read_log_data_1$next[0:0]$3395 + attribute \src "libresoc.v:50986.3-50987.55" wire $0\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:51361.3-51369.6" - wire $0\dmi_req_i_1$next[0:0]$3377 - attribute \src "libresoc.v:51323.3-51324.39" + attribute \src "libresoc.v:51034.3-51042.6" + wire $0\dmi_req_i_1$next[0:0]$3361 + attribute \src "libresoc.v:50996.3-50997.39" wire $0\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51688.3-51721.6" - wire $0\do_dmi_log_rd$next[0:0]$3441 - attribute \src "libresoc.v:51325.3-51326.43" + attribute \src "libresoc.v:51370.3-51403.6" + wire $0\do_dmi_log_rd$next[0:0]$3425 + attribute \src "libresoc.v:50998.3-50999.43" wire $0\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51658.3-51687.6" - wire $0\do_icreset$next[0:0]$3434 - attribute \src "libresoc.v:51327.3-51328.37" + attribute \src "libresoc.v:51340.3-51369.6" + wire $0\do_icreset$next[0:0]$3418 + attribute \src "libresoc.v:51000.3-51001.37" wire $0\do_icreset[0:0] - attribute \src "libresoc.v:51628.3-51657.6" - wire $0\do_reset$next[0:0]$3427 - attribute \src "libresoc.v:51329.3-51330.33" + attribute \src "libresoc.v:51310.3-51339.6" + wire $0\do_reset$next[0:0]$3411 + attribute \src "libresoc.v:51002.3-51003.33" wire $0\do_reset[0:0] - attribute \src "libresoc.v:51598.3-51627.6" - wire $0\do_step$next[0:0]$3420 - attribute \src "libresoc.v:51331.3-51332.31" + attribute \src "libresoc.v:51280.3-51309.6" + wire $0\do_step$next[0:0]$3404 + attribute \src "libresoc.v:51004.3-51005.31" wire $0\do_step[0:0] - attribute \src "libresoc.v:51464.3-51491.6" - wire width 7 $0\gspr_index$next[6:0]$3399 - attribute \src "libresoc.v:51317.3-51318.37" + attribute \src "libresoc.v:51137.3-51164.6" + wire width 7 $0\gspr_index$next[6:0]$3383 + attribute \src "libresoc.v:50990.3-50991.37" wire width 7 $0\gspr_index[6:0] - attribute \src "libresoc.v:51000.7-51000.20" + attribute \src "libresoc.v:50673.7-50673.20" wire $0\initial[0:0] - attribute \src "libresoc.v:51492.3-51525.6" - wire width 32 $0\log_dmi_addr$next[31:0]$3405 - attribute \src "libresoc.v:51315.3-51316.41" + attribute \src "libresoc.v:51165.3-51198.6" + wire width 32 $0\log_dmi_addr$next[31:0]$3389 + attribute \src "libresoc.v:50988.3-50989.41" wire width 32 $0\log_dmi_addr[31:0] - attribute \src "libresoc.v:51420.3-51463.6" - wire $0\stopping$next[0:0]$3390 - attribute \src "libresoc.v:51319.3-51320.33" + attribute \src "libresoc.v:51093.3-51136.6" + wire $0\stopping$next[0:0]$3374 + attribute \src "libresoc.v:50992.3-50993.33" wire $0\stopping[0:0] - attribute \src "libresoc.v:51370.3-51419.6" - wire $0\terminated$next[0:0]$3380 - attribute \src "libresoc.v:51321.3-51322.37" + attribute \src "libresoc.v:51043.3-51092.6" + wire $0\terminated$next[0:0]$3364 + attribute \src "libresoc.v:50994.3-50995.37" wire $0\terminated[0:0] - attribute \src "libresoc.v:51544.3-51553.6" + attribute \src "libresoc.v:51217.3-51229.6" wire $1\d_cr_req[0:0] - attribute \src "libresoc.v:51351.3-51360.6" + attribute \src "libresoc.v:51024.3-51033.6" wire $1\d_gpr_req[0:0] - attribute \src "libresoc.v:51554.3-51563.6" + attribute \src "libresoc.v:51230.3-51245.6" wire $1\d_xer_req[0:0] - attribute \src "libresoc.v:51333.3-51350.6" + attribute \src "libresoc.v:51006.3-51023.6" wire $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:51564.3-51597.6" + attribute \src "libresoc.v:51246.3-51279.6" wire width 64 $1\dmi_dout[63:0] - attribute \src "libresoc.v:51535.3-51543.6" - wire $1\dmi_read_log_data$next[0:0]$3415 - attribute \src "libresoc.v:51187.7-51187.31" + attribute \src "libresoc.v:51208.3-51216.6" + wire $1\dmi_read_log_data$next[0:0]$3399 + attribute \src "libresoc.v:50860.7-50860.31" wire $1\dmi_read_log_data[0:0] - attribute \src "libresoc.v:51526.3-51534.6" - wire $1\dmi_read_log_data_1$next[0:0]$3412 - attribute \src "libresoc.v:51191.7-51191.33" + attribute \src "libresoc.v:51199.3-51207.6" + wire $1\dmi_read_log_data_1$next[0:0]$3396 + attribute \src "libresoc.v:50864.7-50864.33" wire $1\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:51361.3-51369.6" - wire $1\dmi_req_i_1$next[0:0]$3378 - attribute \src "libresoc.v:51197.7-51197.25" + attribute \src "libresoc.v:51034.3-51042.6" + wire $1\dmi_req_i_1$next[0:0]$3362 + attribute \src "libresoc.v:50870.7-50870.25" wire $1\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51688.3-51721.6" - wire $1\do_dmi_log_rd$next[0:0]$3442 - attribute \src "libresoc.v:51203.7-51203.27" + attribute \src "libresoc.v:51370.3-51403.6" + wire $1\do_dmi_log_rd$next[0:0]$3426 + attribute \src "libresoc.v:50876.7-50876.27" wire $1\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51658.3-51687.6" - wire $1\do_icreset$next[0:0]$3435 - attribute \src "libresoc.v:51207.7-51207.24" + attribute \src "libresoc.v:51340.3-51369.6" + wire $1\do_icreset$next[0:0]$3419 + attribute \src "libresoc.v:50880.7-50880.24" wire $1\do_icreset[0:0] - attribute \src "libresoc.v:51628.3-51657.6" - wire $1\do_reset$next[0:0]$3428 - attribute \src "libresoc.v:51211.7-51211.22" + attribute \src "libresoc.v:51310.3-51339.6" + wire $1\do_reset$next[0:0]$3412 + attribute \src "libresoc.v:50884.7-50884.22" wire $1\do_reset[0:0] - attribute \src "libresoc.v:51598.3-51627.6" - wire $1\do_step$next[0:0]$3421 - attribute \src "libresoc.v:51215.7-51215.21" + attribute \src "libresoc.v:51280.3-51309.6" + wire $1\do_step$next[0:0]$3405 + attribute \src "libresoc.v:50888.7-50888.21" wire $1\do_step[0:0] - attribute \src "libresoc.v:51464.3-51491.6" - wire width 7 $1\gspr_index$next[6:0]$3400 - attribute \src "libresoc.v:51219.13-51219.31" + attribute \src "libresoc.v:51137.3-51164.6" + wire width 7 $1\gspr_index$next[6:0]$3384 + attribute \src "libresoc.v:50892.13-50892.31" wire width 7 $1\gspr_index[6:0] - attribute \src "libresoc.v:51492.3-51525.6" - wire width 32 $1\log_dmi_addr$next[31:0]$3406 - attribute \src "libresoc.v:51225.14-51225.34" + attribute \src "libresoc.v:51165.3-51198.6" + wire width 32 $1\log_dmi_addr$next[31:0]$3390 + attribute \src "libresoc.v:50898.14-50898.34" wire width 32 $1\log_dmi_addr[31:0] - attribute \src "libresoc.v:51420.3-51463.6" - wire $1\stopping$next[0:0]$3391 - attribute \src "libresoc.v:51237.7-51237.22" + attribute \src "libresoc.v:51093.3-51136.6" + wire $1\stopping$next[0:0]$3375 + attribute \src "libresoc.v:50910.7-50910.22" wire $1\stopping[0:0] - attribute \src "libresoc.v:51370.3-51419.6" - wire $1\terminated$next[0:0]$3381 - attribute \src "libresoc.v:51243.7-51243.24" + attribute \src "libresoc.v:51043.3-51092.6" + wire $1\terminated$next[0:0]$3365 + attribute \src "libresoc.v:50916.7-50916.24" wire $1\terminated[0:0] - attribute \src "libresoc.v:51688.3-51721.6" - wire $2\do_dmi_log_rd$next[0:0]$3443 - attribute \src "libresoc.v:51658.3-51687.6" - wire $2\do_icreset$next[0:0]$3436 - attribute \src "libresoc.v:51628.3-51657.6" - wire $2\do_reset$next[0:0]$3429 - attribute \src "libresoc.v:51598.3-51627.6" - wire $2\do_step$next[0:0]$3422 - attribute \src "libresoc.v:51464.3-51491.6" - wire width 7 $2\gspr_index$next[6:0]$3401 - attribute \src "libresoc.v:51492.3-51525.6" - wire width 32 $2\log_dmi_addr$next[31:0]$3407 - attribute \src "libresoc.v:51420.3-51463.6" - wire $2\stopping$next[0:0]$3392 - attribute \src "libresoc.v:51370.3-51419.6" - wire $2\terminated$next[0:0]$3382 - attribute \src "libresoc.v:51688.3-51721.6" - wire $3\do_dmi_log_rd$next[0:0]$3444 - attribute \src "libresoc.v:51658.3-51687.6" - wire $3\do_icreset$next[0:0]$3437 - attribute \src "libresoc.v:51628.3-51657.6" - wire $3\do_reset$next[0:0]$3430 - attribute \src "libresoc.v:51598.3-51627.6" - wire $3\do_step$next[0:0]$3423 - attribute \src "libresoc.v:51464.3-51491.6" - wire width 7 $3\gspr_index$next[6:0]$3402 - attribute \src "libresoc.v:51492.3-51525.6" - wire width 32 $3\log_dmi_addr$next[31:0]$3408 - attribute \src "libresoc.v:51420.3-51463.6" - wire $3\stopping$next[0:0]$3393 - attribute \src "libresoc.v:51370.3-51419.6" - wire $3\terminated$next[0:0]$3383 - attribute \src "libresoc.v:51688.3-51721.6" - wire $4\do_dmi_log_rd$next[0:0]$3445 - attribute \src "libresoc.v:51658.3-51687.6" - wire $4\do_icreset$next[0:0]$3438 - attribute \src "libresoc.v:51628.3-51657.6" - wire $4\do_reset$next[0:0]$3431 - attribute \src "libresoc.v:51598.3-51627.6" - wire $4\do_step$next[0:0]$3424 - attribute \src "libresoc.v:51464.3-51491.6" - wire width 7 $4\gspr_index$next[6:0]$3403 - attribute \src "libresoc.v:51492.3-51525.6" - wire width 32 $4\log_dmi_addr$next[31:0]$3409 - attribute \src "libresoc.v:51420.3-51463.6" - wire $4\stopping$next[0:0]$3394 - attribute \src "libresoc.v:51370.3-51419.6" - wire $4\terminated$next[0:0]$3384 - attribute \src "libresoc.v:51658.3-51687.6" - wire $5\do_icreset$next[0:0]$3439 - attribute \src "libresoc.v:51628.3-51657.6" - wire $5\do_reset$next[0:0]$3432 - attribute \src "libresoc.v:51598.3-51627.6" - wire $5\do_step$next[0:0]$3425 - attribute \src "libresoc.v:51420.3-51463.6" - wire $5\stopping$next[0:0]$3395 - attribute \src "libresoc.v:51370.3-51419.6" - wire $5\terminated$next[0:0]$3385 - attribute \src "libresoc.v:51420.3-51463.6" - wire $6\stopping$next[0:0]$3396 - attribute \src "libresoc.v:51370.3-51419.6" - wire $6\terminated$next[0:0]$3386 - attribute \src "libresoc.v:51420.3-51463.6" - wire $7\stopping$next[0:0]$3397 - attribute \src "libresoc.v:51370.3-51419.6" - wire $7\terminated$next[0:0]$3387 - attribute \src "libresoc.v:51370.3-51419.6" - wire $8\terminated$next[0:0]$3388 - attribute \src "libresoc.v:51258.19-51258.110" - wire width 3 $add$libresoc.v:51258$3310_Y - attribute \src "libresoc.v:51252.19-51252.103" - wire $and$libresoc.v:51252$3304_Y - attribute \src "libresoc.v:51254.19-51254.113" - wire $and$libresoc.v:51254$3306_Y - attribute \src "libresoc.v:51259.18-51259.110" - wire $and$libresoc.v:51259$3311_Y - attribute \src "libresoc.v:51261.19-51261.103" - wire $and$libresoc.v:51261$3313_Y - attribute \src "libresoc.v:51263.19-51263.102" - wire $and$libresoc.v:51263$3315_Y - attribute \src "libresoc.v:51269.18-51269.101" - wire $and$libresoc.v:51269$3321_Y - attribute \src "libresoc.v:51271.18-51271.111" - wire $and$libresoc.v:51271$3323_Y - attribute \src "libresoc.v:51276.18-51276.101" - wire $and$libresoc.v:51276$3328_Y - attribute \src "libresoc.v:51279.18-51279.111" - wire $and$libresoc.v:51279$3331_Y - attribute \src "libresoc.v:51284.18-51284.101" - wire $and$libresoc.v:51284$3336_Y - attribute \src "libresoc.v:51286.18-51286.111" - wire $and$libresoc.v:51286$3338_Y - attribute \src "libresoc.v:51292.18-51292.101" - wire $and$libresoc.v:51292$3344_Y - attribute \src "libresoc.v:51294.18-51294.111" - wire $and$libresoc.v:51294$3346_Y - attribute \src "libresoc.v:51299.18-51299.101" - wire $and$libresoc.v:51299$3351_Y - attribute \src "libresoc.v:51300.17-51300.99" - wire $and$libresoc.v:51300$3352_Y - attribute \src "libresoc.v:51302.18-51302.111" - wire $and$libresoc.v:51302$3354_Y - attribute \src "libresoc.v:51307.18-51307.101" - wire $and$libresoc.v:51307$3359_Y - attribute \src "libresoc.v:51309.18-51309.111" - wire $and$libresoc.v:51309$3361_Y - attribute \src "libresoc.v:51249.18-51249.103" - wire $eq$libresoc.v:51249$3301_Y - attribute \src "libresoc.v:51250.19-51250.104" - wire $eq$libresoc.v:51250$3302_Y - attribute \src "libresoc.v:51255.19-51255.104" - wire $eq$libresoc.v:51255$3307_Y - attribute \src "libresoc.v:51256.19-51256.104" - wire $eq$libresoc.v:51256$3308_Y - attribute \src "libresoc.v:51257.19-51257.104" - wire $eq$libresoc.v:51257$3309_Y - attribute \src "libresoc.v:51260.19-51260.104" - wire $eq$libresoc.v:51260$3312_Y - attribute \src "libresoc.v:51264.18-51264.103" - wire $eq$libresoc.v:51264$3316_Y - attribute \src "libresoc.v:51265.18-51265.103" - wire $eq$libresoc.v:51265$3317_Y - attribute \src "libresoc.v:51266.18-51266.103" - wire $eq$libresoc.v:51266$3318_Y - attribute \src "libresoc.v:51272.18-51272.103" - wire $eq$libresoc.v:51272$3324_Y - attribute \src "libresoc.v:51273.18-51273.103" - wire $eq$libresoc.v:51273$3325_Y - attribute \src "libresoc.v:51274.18-51274.103" - wire $eq$libresoc.v:51274$3326_Y - attribute \src "libresoc.v:51280.18-51280.103" - wire $eq$libresoc.v:51280$3332_Y - attribute \src "libresoc.v:51281.18-51281.103" - wire $eq$libresoc.v:51281$3333_Y - attribute \src "libresoc.v:51282.18-51282.103" - wire $eq$libresoc.v:51282$3334_Y - attribute \src "libresoc.v:51287.18-51287.103" - wire $eq$libresoc.v:51287$3339_Y - attribute \src "libresoc.v:51288.18-51288.103" - wire $eq$libresoc.v:51288$3340_Y - attribute \src "libresoc.v:51290.18-51290.103" - wire $eq$libresoc.v:51290$3342_Y - attribute \src "libresoc.v:51295.18-51295.103" - wire $eq$libresoc.v:51295$3347_Y - attribute \src "libresoc.v:51296.18-51296.103" - wire $eq$libresoc.v:51296$3348_Y - attribute \src "libresoc.v:51297.18-51297.103" - wire $eq$libresoc.v:51297$3349_Y - attribute \src "libresoc.v:51303.18-51303.103" - wire $eq$libresoc.v:51303$3355_Y - attribute \src "libresoc.v:51304.18-51304.103" - wire $eq$libresoc.v:51304$3356_Y - attribute \src "libresoc.v:51305.18-51305.103" - wire $eq$libresoc.v:51305$3357_Y - attribute \src "libresoc.v:51310.18-51310.103" - wire $eq$libresoc.v:51310$3362_Y - attribute \src "libresoc.v:51248.17-51248.103" - wire $not$libresoc.v:51248$3300_Y - attribute \src "libresoc.v:51251.19-51251.99" - wire $not$libresoc.v:51251$3303_Y - attribute \src "libresoc.v:51253.19-51253.105" - wire $not$libresoc.v:51253$3305_Y - attribute \src "libresoc.v:51262.19-51262.95" - wire $not$libresoc.v:51262$3314_Y - attribute \src "libresoc.v:51268.18-51268.98" - wire $not$libresoc.v:51268$3320_Y - attribute \src "libresoc.v:51270.18-51270.104" - wire $not$libresoc.v:51270$3322_Y - attribute \src "libresoc.v:51275.18-51275.98" - wire $not$libresoc.v:51275$3327_Y - attribute \src "libresoc.v:51277.18-51277.104" - wire $not$libresoc.v:51277$3329_Y - attribute \src "libresoc.v:51283.18-51283.98" - wire $not$libresoc.v:51283$3335_Y - attribute \src "libresoc.v:51285.18-51285.104" - wire $not$libresoc.v:51285$3337_Y - attribute \src "libresoc.v:51289.17-51289.97" - wire $not$libresoc.v:51289$3341_Y - attribute \src "libresoc.v:51291.18-51291.98" - wire $not$libresoc.v:51291$3343_Y - attribute \src "libresoc.v:51293.18-51293.104" - wire $not$libresoc.v:51293$3345_Y - attribute \src "libresoc.v:51298.18-51298.98" - wire $not$libresoc.v:51298$3350_Y - attribute \src "libresoc.v:51301.18-51301.104" - wire $not$libresoc.v:51301$3353_Y - attribute \src "libresoc.v:51306.18-51306.98" - wire $not$libresoc.v:51306$3358_Y - attribute \src "libresoc.v:51308.18-51308.104" - wire $not$libresoc.v:51308$3360_Y - attribute \src "libresoc.v:51267.17-51267.126" - wire width 64 $pos$libresoc.v:51267$3319_Y - attribute \src "libresoc.v:51278.17-51278.245" - wire width 64 $pos$libresoc.v:51278$3330_Y + attribute \src "libresoc.v:51370.3-51403.6" + wire $2\do_dmi_log_rd$next[0:0]$3427 + attribute \src "libresoc.v:51340.3-51369.6" + wire $2\do_icreset$next[0:0]$3420 + attribute \src "libresoc.v:51310.3-51339.6" + wire $2\do_reset$next[0:0]$3413 + attribute \src "libresoc.v:51280.3-51309.6" + wire $2\do_step$next[0:0]$3406 + attribute \src "libresoc.v:51137.3-51164.6" + wire width 7 $2\gspr_index$next[6:0]$3385 + attribute \src "libresoc.v:51165.3-51198.6" + wire width 32 $2\log_dmi_addr$next[31:0]$3391 + attribute \src "libresoc.v:51093.3-51136.6" + wire $2\stopping$next[0:0]$3376 + attribute \src "libresoc.v:51043.3-51092.6" + wire $2\terminated$next[0:0]$3366 + attribute \src "libresoc.v:51370.3-51403.6" + wire $3\do_dmi_log_rd$next[0:0]$3428 + attribute \src "libresoc.v:51340.3-51369.6" + wire $3\do_icreset$next[0:0]$3421 + attribute \src "libresoc.v:51310.3-51339.6" + wire $3\do_reset$next[0:0]$3414 + attribute \src "libresoc.v:51280.3-51309.6" + wire $3\do_step$next[0:0]$3407 + attribute \src "libresoc.v:51137.3-51164.6" + wire width 7 $3\gspr_index$next[6:0]$3386 + attribute \src "libresoc.v:51165.3-51198.6" + wire width 32 $3\log_dmi_addr$next[31:0]$3392 + attribute \src "libresoc.v:51093.3-51136.6" + wire $3\stopping$next[0:0]$3377 + attribute \src "libresoc.v:51043.3-51092.6" + wire $3\terminated$next[0:0]$3367 + attribute \src "libresoc.v:51370.3-51403.6" + wire $4\do_dmi_log_rd$next[0:0]$3429 + attribute \src "libresoc.v:51340.3-51369.6" + wire $4\do_icreset$next[0:0]$3422 + attribute \src "libresoc.v:51310.3-51339.6" + wire $4\do_reset$next[0:0]$3415 + attribute \src "libresoc.v:51280.3-51309.6" + wire $4\do_step$next[0:0]$3408 + attribute \src "libresoc.v:51137.3-51164.6" + wire width 7 $4\gspr_index$next[6:0]$3387 + attribute \src "libresoc.v:51165.3-51198.6" + wire width 32 $4\log_dmi_addr$next[31:0]$3393 + attribute \src "libresoc.v:51093.3-51136.6" + wire $4\stopping$next[0:0]$3378 + attribute \src "libresoc.v:51043.3-51092.6" + wire $4\terminated$next[0:0]$3368 + attribute \src "libresoc.v:51340.3-51369.6" + wire $5\do_icreset$next[0:0]$3423 + attribute \src "libresoc.v:51310.3-51339.6" + wire $5\do_reset$next[0:0]$3416 + attribute \src "libresoc.v:51280.3-51309.6" + wire $5\do_step$next[0:0]$3409 + attribute \src "libresoc.v:51093.3-51136.6" + wire $5\stopping$next[0:0]$3379 + attribute \src "libresoc.v:51043.3-51092.6" + wire $5\terminated$next[0:0]$3369 + attribute \src "libresoc.v:51093.3-51136.6" + wire $6\stopping$next[0:0]$3380 + attribute \src "libresoc.v:51043.3-51092.6" + wire $6\terminated$next[0:0]$3370 + attribute \src "libresoc.v:51093.3-51136.6" + wire $7\stopping$next[0:0]$3381 + attribute \src "libresoc.v:51043.3-51092.6" + wire $7\terminated$next[0:0]$3371 + attribute \src "libresoc.v:51043.3-51092.6" + wire $8\terminated$next[0:0]$3372 + attribute \src "libresoc.v:50931.19-50931.110" + wire width 3 $add$libresoc.v:50931$3294_Y + attribute \src "libresoc.v:50925.19-50925.103" + wire $and$libresoc.v:50925$3288_Y + attribute \src "libresoc.v:50927.19-50927.113" + wire $and$libresoc.v:50927$3290_Y + attribute \src "libresoc.v:50932.18-50932.110" + wire $and$libresoc.v:50932$3295_Y + attribute \src "libresoc.v:50934.19-50934.103" + wire $and$libresoc.v:50934$3297_Y + attribute \src "libresoc.v:50936.19-50936.102" + wire $and$libresoc.v:50936$3299_Y + attribute \src "libresoc.v:50942.18-50942.101" + wire $and$libresoc.v:50942$3305_Y + attribute \src "libresoc.v:50944.18-50944.111" + wire $and$libresoc.v:50944$3307_Y + attribute \src "libresoc.v:50949.18-50949.101" + wire $and$libresoc.v:50949$3312_Y + attribute \src "libresoc.v:50952.18-50952.111" + wire $and$libresoc.v:50952$3315_Y + attribute \src "libresoc.v:50957.18-50957.101" + wire $and$libresoc.v:50957$3320_Y + attribute \src "libresoc.v:50959.18-50959.111" + wire $and$libresoc.v:50959$3322_Y + attribute \src "libresoc.v:50965.18-50965.101" + wire $and$libresoc.v:50965$3328_Y + attribute \src "libresoc.v:50967.18-50967.111" + wire $and$libresoc.v:50967$3330_Y + attribute \src "libresoc.v:50972.18-50972.101" + wire $and$libresoc.v:50972$3335_Y + attribute \src "libresoc.v:50973.17-50973.99" + wire $and$libresoc.v:50973$3336_Y + attribute \src "libresoc.v:50975.18-50975.111" + wire $and$libresoc.v:50975$3338_Y + attribute \src "libresoc.v:50980.18-50980.101" + wire $and$libresoc.v:50980$3343_Y + attribute \src "libresoc.v:50982.18-50982.111" + wire $and$libresoc.v:50982$3345_Y + attribute \src "libresoc.v:50922.18-50922.103" + wire $eq$libresoc.v:50922$3285_Y + attribute \src "libresoc.v:50923.19-50923.104" + wire $eq$libresoc.v:50923$3286_Y + attribute \src "libresoc.v:50928.19-50928.104" + wire $eq$libresoc.v:50928$3291_Y + attribute \src "libresoc.v:50929.19-50929.104" + wire $eq$libresoc.v:50929$3292_Y + attribute \src "libresoc.v:50930.19-50930.104" + wire $eq$libresoc.v:50930$3293_Y + attribute \src "libresoc.v:50933.19-50933.104" + wire $eq$libresoc.v:50933$3296_Y + attribute \src "libresoc.v:50937.18-50937.103" + wire $eq$libresoc.v:50937$3300_Y + attribute \src "libresoc.v:50938.18-50938.103" + wire $eq$libresoc.v:50938$3301_Y + attribute \src "libresoc.v:50939.18-50939.103" + wire $eq$libresoc.v:50939$3302_Y + attribute \src "libresoc.v:50945.18-50945.103" + wire $eq$libresoc.v:50945$3308_Y + attribute \src "libresoc.v:50946.18-50946.103" + wire $eq$libresoc.v:50946$3309_Y + attribute \src "libresoc.v:50947.18-50947.103" + wire $eq$libresoc.v:50947$3310_Y + attribute \src "libresoc.v:50953.18-50953.103" + wire $eq$libresoc.v:50953$3316_Y + attribute \src "libresoc.v:50954.18-50954.103" + wire $eq$libresoc.v:50954$3317_Y + attribute \src "libresoc.v:50955.18-50955.103" + wire $eq$libresoc.v:50955$3318_Y + attribute \src "libresoc.v:50960.18-50960.103" + wire $eq$libresoc.v:50960$3323_Y + attribute \src "libresoc.v:50961.18-50961.103" + wire $eq$libresoc.v:50961$3324_Y + attribute \src "libresoc.v:50963.18-50963.103" + wire $eq$libresoc.v:50963$3326_Y + attribute \src "libresoc.v:50968.18-50968.103" + wire $eq$libresoc.v:50968$3331_Y + attribute \src "libresoc.v:50969.18-50969.103" + wire $eq$libresoc.v:50969$3332_Y + attribute \src "libresoc.v:50970.18-50970.103" + wire $eq$libresoc.v:50970$3333_Y + attribute \src "libresoc.v:50976.18-50976.103" + wire $eq$libresoc.v:50976$3339_Y + attribute \src "libresoc.v:50977.18-50977.103" + wire $eq$libresoc.v:50977$3340_Y + attribute \src "libresoc.v:50978.18-50978.103" + wire $eq$libresoc.v:50978$3341_Y + attribute \src "libresoc.v:50983.18-50983.103" + wire $eq$libresoc.v:50983$3346_Y + attribute \src "libresoc.v:50921.17-50921.103" + wire $not$libresoc.v:50921$3284_Y + attribute \src "libresoc.v:50924.19-50924.99" + wire $not$libresoc.v:50924$3287_Y + attribute \src "libresoc.v:50926.19-50926.105" + wire $not$libresoc.v:50926$3289_Y + attribute \src "libresoc.v:50935.19-50935.95" + wire $not$libresoc.v:50935$3298_Y + attribute \src "libresoc.v:50941.18-50941.98" + wire $not$libresoc.v:50941$3304_Y + attribute \src "libresoc.v:50943.18-50943.104" + wire $not$libresoc.v:50943$3306_Y + attribute \src "libresoc.v:50948.18-50948.98" + wire $not$libresoc.v:50948$3311_Y + attribute \src "libresoc.v:50950.18-50950.104" + wire $not$libresoc.v:50950$3313_Y + attribute \src "libresoc.v:50956.18-50956.98" + wire $not$libresoc.v:50956$3319_Y + attribute \src "libresoc.v:50958.18-50958.104" + wire $not$libresoc.v:50958$3321_Y + attribute \src "libresoc.v:50962.17-50962.97" + wire $not$libresoc.v:50962$3325_Y + attribute \src "libresoc.v:50964.18-50964.98" + wire $not$libresoc.v:50964$3327_Y + attribute \src "libresoc.v:50966.18-50966.104" + wire $not$libresoc.v:50966$3329_Y + attribute \src "libresoc.v:50971.18-50971.98" + wire $not$libresoc.v:50971$3334_Y + attribute \src "libresoc.v:50974.18-50974.104" + wire $not$libresoc.v:50974$3337_Y + attribute \src "libresoc.v:50979.18-50979.98" + wire $not$libresoc.v:50979$3342_Y + attribute \src "libresoc.v:50981.18-50981.104" + wire $not$libresoc.v:50981$3344_Y + attribute \src "libresoc.v:50940.17-50940.126" + wire width 64 $pos$libresoc.v:50940$3303_Y + attribute \src "libresoc.v:50951.17-50951.245" + wire width 64 $pos$libresoc.v:50951$3314_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" @@ -90630,7 +90140,7 @@ module \dbg wire \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 30 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 input 13 \core_dbg_core_dbg_dststep @@ -90720,7 +90230,7 @@ module \dbg wire width 7 \gspr_index$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:100" wire \icache_rst_o - attribute \src "libresoc.v:51000.7-51000.15" + attribute \src "libresoc.v:50673.7-50673.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" wire width 32 \log_dmi_addr @@ -90730,7 +90240,7 @@ module \dbg wire width 64 \log_dmi_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" wire width 64 \stat_reg @@ -90747,7 +90257,7 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" wire \terminated_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" - cell $add $add$libresoc.v:51258$3310 + cell $add $add$libresoc.v:50931$3294 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -90755,10 +90265,10 @@ module \dbg parameter \Y_WIDTH 3 connect \A \log_dmi_addr [1:0] connect \B 1'1 - connect \Y $add$libresoc.v:51258$3310_Y + connect \Y $add$libresoc.v:50931$3294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51252$3304 + cell $and $and$libresoc.v:50925$3288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90766,10 +90276,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$103 - connect \Y $and$libresoc.v:51252$3304_Y + connect \Y $and$libresoc.v:50925$3288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51254$3306 + cell $and $and$libresoc.v:50927$3290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90777,10 +90287,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$107 - connect \Y $and$libresoc.v:51254$3306_Y + connect \Y $and$libresoc.v:50927$3290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51259$3311 + cell $and $and$libresoc.v:50932$3295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90788,10 +90298,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$9 - connect \Y $and$libresoc.v:51259$3311_Y + connect \Y $and$libresoc.v:50932$3295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" - cell $and $and$libresoc.v:51261$3313 + cell $and $and$libresoc.v:50934$3297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90799,10 +90309,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$120 - connect \Y $and$libresoc.v:51261$3313_Y + connect \Y $and$libresoc.v:50934$3297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" - cell $and $and$libresoc.v:51263$3315 + cell $and $and$libresoc.v:50936$3299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90810,10 +90320,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \stopping connect \B \$124 - connect \Y $and$libresoc.v:51263$3315_Y + connect \Y $and$libresoc.v:50936$3299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51269$3321 + cell $and $and$libresoc.v:50942$3305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90821,10 +90331,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$19 - connect \Y $and$libresoc.v:51269$3321_Y + connect \Y $and$libresoc.v:50942$3305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51271$3323 + cell $and $and$libresoc.v:50944$3307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90832,10 +90342,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$23 - connect \Y $and$libresoc.v:51271$3323_Y + connect \Y $and$libresoc.v:50944$3307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51276$3328 + cell $and $and$libresoc.v:50949$3312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90843,10 +90353,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$33 - connect \Y $and$libresoc.v:51276$3328_Y + connect \Y $and$libresoc.v:50949$3312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51279$3331 + cell $and $and$libresoc.v:50952$3315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90854,10 +90364,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$37 - connect \Y $and$libresoc.v:51279$3331_Y + connect \Y $and$libresoc.v:50952$3315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51284$3336 + cell $and $and$libresoc.v:50957$3320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90865,10 +90375,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$47 - connect \Y $and$libresoc.v:51284$3336_Y + connect \Y $and$libresoc.v:50957$3320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51286$3338 + cell $and $and$libresoc.v:50959$3322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90876,10 +90386,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$51 - connect \Y $and$libresoc.v:51286$3338_Y + connect \Y $and$libresoc.v:50959$3322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51292$3344 + cell $and $and$libresoc.v:50965$3328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90887,10 +90397,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$61 - connect \Y $and$libresoc.v:51292$3344_Y + connect \Y $and$libresoc.v:50965$3328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51294$3346 + cell $and $and$libresoc.v:50967$3330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90898,10 +90408,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$65 - connect \Y $and$libresoc.v:51294$3346_Y + connect \Y $and$libresoc.v:50967$3330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51299$3351 + cell $and $and$libresoc.v:50972$3335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90909,10 +90419,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$75 - connect \Y $and$libresoc.v:51299$3351_Y + connect \Y $and$libresoc.v:50972$3335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51300$3352 + cell $and $and$libresoc.v:50973$3336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90920,10 +90430,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$5 - connect \Y $and$libresoc.v:51300$3352_Y + connect \Y $and$libresoc.v:50973$3336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51302$3354 + cell $and $and$libresoc.v:50975$3338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90931,10 +90441,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$79 - connect \Y $and$libresoc.v:51302$3354_Y + connect \Y $and$libresoc.v:50975$3338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51307$3359 + cell $and $and$libresoc.v:50980$3343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90942,10 +90452,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$89 - connect \Y $and$libresoc.v:51307$3359_Y + connect \Y $and$libresoc.v:50980$3343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51309$3361 + cell $and $and$libresoc.v:50982$3345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90953,10 +90463,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$93 - connect \Y $and$libresoc.v:51309$3361_Y + connect \Y $and$libresoc.v:50982$3345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51249$3301 + cell $eq $eq$libresoc.v:50922$3285 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90964,10 +90474,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51249$3301_Y + connect \Y $eq$libresoc.v:50922$3285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51250$3302 + cell $eq $eq$libresoc.v:50923$3286 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90975,10 +90485,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51250$3302_Y + connect \Y $eq$libresoc.v:50923$3286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51255$3307 + cell $eq $eq$libresoc.v:50928$3291 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90986,10 +90496,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51255$3307_Y + connect \Y $eq$libresoc.v:50928$3291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51256$3308 + cell $eq $eq$libresoc.v:50929$3292 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90997,10 +90507,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51256$3308_Y + connect \Y $eq$libresoc.v:50929$3292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51257$3309 + cell $eq $eq$libresoc.v:50930$3293 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91008,10 +90518,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51257$3309_Y + connect \Y $eq$libresoc.v:50930$3293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" - cell $eq $eq$libresoc.v:51260$3312 + cell $eq $eq$libresoc.v:50933$3296 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91019,10 +90529,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'111 - connect \Y $eq$libresoc.v:51260$3312_Y + connect \Y $eq$libresoc.v:50933$3296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51264$3316 + cell $eq $eq$libresoc.v:50937$3300 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91030,10 +90540,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51264$3316_Y + connect \Y $eq$libresoc.v:50937$3300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51265$3317 + cell $eq $eq$libresoc.v:50938$3301 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91041,10 +90551,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51265$3317_Y + connect \Y $eq$libresoc.v:50938$3301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51266$3318 + cell $eq $eq$libresoc.v:50939$3302 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91052,10 +90562,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51266$3318_Y + connect \Y $eq$libresoc.v:50939$3302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51272$3324 + cell $eq $eq$libresoc.v:50945$3308 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91063,10 +90573,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51272$3324_Y + connect \Y $eq$libresoc.v:50945$3308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51273$3325 + cell $eq $eq$libresoc.v:50946$3309 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91074,10 +90584,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51273$3325_Y + connect \Y $eq$libresoc.v:50946$3309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51274$3326 + cell $eq $eq$libresoc.v:50947$3310 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91085,10 +90595,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51274$3326_Y + connect \Y $eq$libresoc.v:50947$3310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51280$3332 + cell $eq $eq$libresoc.v:50953$3316 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91096,10 +90606,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51280$3332_Y + connect \Y $eq$libresoc.v:50953$3316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51281$3333 + cell $eq $eq$libresoc.v:50954$3317 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91107,10 +90617,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51281$3333_Y + connect \Y $eq$libresoc.v:50954$3317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51282$3334 + cell $eq $eq$libresoc.v:50955$3318 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91118,10 +90628,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51282$3334_Y + connect \Y $eq$libresoc.v:50955$3318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51287$3339 + cell $eq $eq$libresoc.v:50960$3323 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91129,10 +90639,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51287$3339_Y + connect \Y $eq$libresoc.v:50960$3323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51288$3340 + cell $eq $eq$libresoc.v:50961$3324 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91140,10 +90650,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51288$3340_Y + connect \Y $eq$libresoc.v:50961$3324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51290$3342 + cell $eq $eq$libresoc.v:50963$3326 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91151,10 +90661,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51290$3342_Y + connect \Y $eq$libresoc.v:50963$3326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51295$3347 + cell $eq $eq$libresoc.v:50968$3331 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91162,10 +90672,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51295$3347_Y + connect \Y $eq$libresoc.v:50968$3331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51296$3348 + cell $eq $eq$libresoc.v:50969$3332 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91173,10 +90683,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51296$3348_Y + connect \Y $eq$libresoc.v:50969$3332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51297$3349 + cell $eq $eq$libresoc.v:50970$3333 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91184,10 +90694,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51297$3349_Y + connect \Y $eq$libresoc.v:50970$3333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51303$3355 + cell $eq $eq$libresoc.v:50976$3339 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91195,10 +90705,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51303$3355_Y + connect \Y $eq$libresoc.v:50976$3339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51304$3356 + cell $eq $eq$libresoc.v:50977$3340 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91206,10 +90716,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51304$3356_Y + connect \Y $eq$libresoc.v:50977$3340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51305$3357 + cell $eq $eq$libresoc.v:50978$3341 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91217,10 +90727,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51305$3357_Y + connect \Y $eq$libresoc.v:50978$3341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51310$3362 + cell $eq $eq$libresoc.v:50983$3346 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91228,340 +90738,340 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51310$3362_Y + connect \Y $eq$libresoc.v:50983$3346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51248$3300 + cell $not $not$libresoc.v:50921$3284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51248$3300_Y + connect \Y $not$libresoc.v:50921$3284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51251$3303 + cell $not $not$libresoc.v:50924$3287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51251$3303_Y + connect \Y $not$libresoc.v:50924$3287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51253$3305 + cell $not $not$libresoc.v:50926$3289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51253$3305_Y + connect \Y $not$libresoc.v:50926$3289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" - cell $not $not$libresoc.v:51262$3314 + cell $not $not$libresoc.v:50935$3298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \do_step - connect \Y $not$libresoc.v:51262$3314_Y + connect \Y $not$libresoc.v:50935$3298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51268$3320 + cell $not $not$libresoc.v:50941$3304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51268$3320_Y + connect \Y $not$libresoc.v:50941$3304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51270$3322 + cell $not $not$libresoc.v:50943$3306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51270$3322_Y + connect \Y $not$libresoc.v:50943$3306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51275$3327 + cell $not $not$libresoc.v:50948$3311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51275$3327_Y + connect \Y $not$libresoc.v:50948$3311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51277$3329 + cell $not $not$libresoc.v:50950$3313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51277$3329_Y + connect \Y $not$libresoc.v:50950$3313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51283$3335 + cell $not $not$libresoc.v:50956$3319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51283$3335_Y + connect \Y $not$libresoc.v:50956$3319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51285$3337 + cell $not $not$libresoc.v:50958$3321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51285$3337_Y + connect \Y $not$libresoc.v:50958$3321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51289$3341 + cell $not $not$libresoc.v:50962$3325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51289$3341_Y + connect \Y $not$libresoc.v:50962$3325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51291$3343 + cell $not $not$libresoc.v:50964$3327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51291$3343_Y + connect \Y $not$libresoc.v:50964$3327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51293$3345 + cell $not $not$libresoc.v:50966$3329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51293$3345_Y + connect \Y $not$libresoc.v:50966$3329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51298$3350 + cell $not $not$libresoc.v:50971$3334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51298$3350_Y + connect \Y $not$libresoc.v:50971$3334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51301$3353 + cell $not $not$libresoc.v:50974$3337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51301$3353_Y + connect \Y $not$libresoc.v:50974$3337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51306$3358 + cell $not $not$libresoc.v:50979$3342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51306$3358_Y + connect \Y $not$libresoc.v:50979$3342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51308$3360 + cell $not $not$libresoc.v:50981$3344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51308$3360_Y + connect \Y $not$libresoc.v:50981$3344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $pos $pos$libresoc.v:51267$3319 + cell $pos $pos$libresoc.v:50940$3303 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } - connect \Y $pos$libresoc.v:51267$3319_Y + connect \Y $pos$libresoc.v:50940$3303_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:51278$3330 + cell $pos $pos$libresoc.v:50951$3314 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \core_dbg_core_dbg_maxvl \core_dbg_core_dbg_vl \core_dbg_core_dbg_srcstep \core_dbg_core_dbg_dststep \core_dbg_core_dbg_subvl \core_dbg_core_dbg_svstep } - connect \Y $pos$libresoc.v:51278$3330_Y + connect \Y $pos$libresoc.v:50951$3314_Y end - attribute \src "libresoc.v:51000.7-51000.20" - process $proc$libresoc.v:51000$3446 + attribute \src "libresoc.v:50673.7-50673.20" + process $proc$libresoc.v:50673$3430 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:51187.7-51187.31" - process $proc$libresoc.v:51187$3447 + attribute \src "libresoc.v:50860.7-50860.31" + process $proc$libresoc.v:50860$3431 assign { } { } assign $1\dmi_read_log_data[0:0] 1'0 sync always sync init update \dmi_read_log_data $1\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:51191.7-51191.33" - process $proc$libresoc.v:51191$3448 + attribute \src "libresoc.v:50864.7-50864.33" + process $proc$libresoc.v:50864$3432 assign { } { } assign $1\dmi_read_log_data_1[0:0] 1'0 sync always sync init update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:51197.7-51197.25" - process $proc$libresoc.v:51197$3449 + attribute \src "libresoc.v:50870.7-50870.25" + process $proc$libresoc.v:50870$3433 assign { } { } assign $1\dmi_req_i_1[0:0] 1'0 sync always sync init update \dmi_req_i_1 $1\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:51203.7-51203.27" - process $proc$libresoc.v:51203$3450 + attribute \src "libresoc.v:50876.7-50876.27" + process $proc$libresoc.v:50876$3434 assign { } { } assign $1\do_dmi_log_rd[0:0] 1'0 sync always sync init update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:51207.7-51207.24" - process $proc$libresoc.v:51207$3451 + attribute \src "libresoc.v:50880.7-50880.24" + process $proc$libresoc.v:50880$3435 assign { } { } assign $1\do_icreset[0:0] 1'0 sync always sync init update \do_icreset $1\do_icreset[0:0] end - attribute \src "libresoc.v:51211.7-51211.22" - process $proc$libresoc.v:51211$3452 + attribute \src "libresoc.v:50884.7-50884.22" + process $proc$libresoc.v:50884$3436 assign { } { } assign $1\do_reset[0:0] 1'0 sync always sync init update \do_reset $1\do_reset[0:0] end - attribute \src "libresoc.v:51215.7-51215.21" - process $proc$libresoc.v:51215$3453 + attribute \src "libresoc.v:50888.7-50888.21" + process $proc$libresoc.v:50888$3437 assign { } { } assign $1\do_step[0:0] 1'0 sync always sync init update \do_step $1\do_step[0:0] end - attribute \src "libresoc.v:51219.13-51219.31" - process $proc$libresoc.v:51219$3454 + attribute \src "libresoc.v:50892.13-50892.31" + process $proc$libresoc.v:50892$3438 assign { } { } assign $1\gspr_index[6:0] 7'0000000 sync always sync init update \gspr_index $1\gspr_index[6:0] end - attribute \src "libresoc.v:51225.14-51225.34" - process $proc$libresoc.v:51225$3455 + attribute \src "libresoc.v:50898.14-50898.34" + process $proc$libresoc.v:50898$3439 assign { } { } assign $1\log_dmi_addr[31:0] 0 sync always sync init update \log_dmi_addr $1\log_dmi_addr[31:0] end - attribute \src "libresoc.v:51237.7-51237.22" - process $proc$libresoc.v:51237$3456 + attribute \src "libresoc.v:50910.7-50910.22" + process $proc$libresoc.v:50910$3440 assign { } { } assign $1\stopping[0:0] 1'0 sync always sync init update \stopping $1\stopping[0:0] end - attribute \src "libresoc.v:51243.7-51243.24" - process $proc$libresoc.v:51243$3457 + attribute \src "libresoc.v:50916.7-50916.24" + process $proc$libresoc.v:50916$3441 assign { } { } assign $1\terminated[0:0] 1'0 sync always sync init update \terminated $1\terminated[0:0] end - attribute \src "libresoc.v:51311.3-51312.51" - process $proc$libresoc.v:51311$3363 + attribute \src "libresoc.v:50984.3-50985.51" + process $proc$libresoc.v:50984$3347 assign { } { } assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next sync posedge \clk update \dmi_read_log_data $0\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:51313.3-51314.55" - process $proc$libresoc.v:51313$3364 + attribute \src "libresoc.v:50986.3-50987.55" + process $proc$libresoc.v:50986$3348 assign { } { } assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next sync posedge \clk update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:51315.3-51316.41" - process $proc$libresoc.v:51315$3365 + attribute \src "libresoc.v:50988.3-50989.41" + process $proc$libresoc.v:50988$3349 assign { } { } assign $0\log_dmi_addr[31:0] \log_dmi_addr$next sync posedge \clk update \log_dmi_addr $0\log_dmi_addr[31:0] end - attribute \src "libresoc.v:51317.3-51318.37" - process $proc$libresoc.v:51317$3366 + attribute \src "libresoc.v:50990.3-50991.37" + process $proc$libresoc.v:50990$3350 assign { } { } assign $0\gspr_index[6:0] \gspr_index$next sync posedge \clk update \gspr_index $0\gspr_index[6:0] end - attribute \src "libresoc.v:51319.3-51320.33" - process $proc$libresoc.v:51319$3367 + attribute \src "libresoc.v:50992.3-50993.33" + process $proc$libresoc.v:50992$3351 assign { } { } assign $0\stopping[0:0] \stopping$next sync posedge \clk update \stopping $0\stopping[0:0] end - attribute \src "libresoc.v:51321.3-51322.37" - process $proc$libresoc.v:51321$3368 + attribute \src "libresoc.v:50994.3-50995.37" + process $proc$libresoc.v:50994$3352 assign { } { } assign $0\terminated[0:0] \terminated$next sync posedge \clk update \terminated $0\terminated[0:0] end - attribute \src "libresoc.v:51323.3-51324.39" - process $proc$libresoc.v:51323$3369 + attribute \src "libresoc.v:50996.3-50997.39" + process $proc$libresoc.v:50996$3353 assign { } { } assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next sync posedge \clk update \dmi_req_i_1 $0\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:51325.3-51326.43" - process $proc$libresoc.v:51325$3370 + attribute \src "libresoc.v:50998.3-50999.43" + process $proc$libresoc.v:50998$3354 assign { } { } assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next sync posedge \clk update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:51327.3-51328.37" - process $proc$libresoc.v:51327$3371 + attribute \src "libresoc.v:51000.3-51001.37" + process $proc$libresoc.v:51000$3355 assign { } { } assign $0\do_icreset[0:0] \do_icreset$next sync posedge \clk update \do_icreset $0\do_icreset[0:0] end - attribute \src "libresoc.v:51329.3-51330.33" - process $proc$libresoc.v:51329$3372 + attribute \src "libresoc.v:51002.3-51003.33" + process $proc$libresoc.v:51002$3356 assign { } { } assign $0\do_reset[0:0] \do_reset$next sync posedge \clk update \do_reset $0\do_reset[0:0] end - attribute \src "libresoc.v:51331.3-51332.31" - process $proc$libresoc.v:51331$3373 + attribute \src "libresoc.v:51004.3-51005.31" + process $proc$libresoc.v:51004$3357 assign { } { } assign $0\do_step[0:0] \do_step$next sync posedge \clk update \do_step $0\do_step[0:0] end - attribute \src "libresoc.v:51333.3-51350.6" - process $proc$libresoc.v:51333$3374 + attribute \src "libresoc.v:51006.3-51023.6" + process $proc$libresoc.v:51006$3358 assign { } { } assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:51334.5-51334.29" + attribute \src "libresoc.v:51007.5-51007.29" switch \initial - attribute \src "libresoc.v:51334.9-51334.17" + attribute \src "libresoc.v:51007.9-51007.17" case 1'1 case end @@ -91587,14 +91097,14 @@ module \dbg sync always update \dmi_ack_o $0\dmi_ack_o[0:0] end - attribute \src "libresoc.v:51351.3-51360.6" - process $proc$libresoc.v:51351$3375 + attribute \src "libresoc.v:51024.3-51033.6" + process $proc$libresoc.v:51024$3359 assign { } { } assign { } { } assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] - attribute \src "libresoc.v:51352.5-51352.29" + attribute \src "libresoc.v:51025.5-51025.29" switch \initial - attribute \src "libresoc.v:51352.9-51352.17" + attribute \src "libresoc.v:51025.9-51025.17" case 1'1 case end @@ -91610,14 +91120,14 @@ module \dbg sync always update \d_gpr_req $0\d_gpr_req[0:0] end - attribute \src "libresoc.v:51361.3-51369.6" - process $proc$libresoc.v:51361$3376 + attribute \src "libresoc.v:51034.3-51042.6" + process $proc$libresoc.v:51034$3360 assign { } { } assign { } { } - assign $0\dmi_req_i_1$next[0:0]$3377 $1\dmi_req_i_1$next[0:0]$3378 - attribute \src "libresoc.v:51362.5-51362.29" + assign $0\dmi_req_i_1$next[0:0]$3361 $1\dmi_req_i_1$next[0:0]$3362 + attribute \src "libresoc.v:51035.5-51035.29" switch \initial - attribute \src "libresoc.v:51362.9-51362.17" + attribute \src "libresoc.v:51035.9-51035.17" case 1'1 case end @@ -91626,23 +91136,23 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_req_i_1$next[0:0]$3378 1'0 + assign $1\dmi_req_i_1$next[0:0]$3362 1'0 case - assign $1\dmi_req_i_1$next[0:0]$3378 \dmi_req_i + assign $1\dmi_req_i_1$next[0:0]$3362 \dmi_req_i end sync always - update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3377 + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3361 end - attribute \src "libresoc.v:51370.3-51419.6" - process $proc$libresoc.v:51370$3379 + attribute \src "libresoc.v:51043.3-51092.6" + process $proc$libresoc.v:51043$3363 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\terminated$next[0:0]$3380 $8\terminated$next[0:0]$3388 - attribute \src "libresoc.v:51371.5-51371.29" + assign $0\terminated$next[0:0]$3364 $8\terminated$next[0:0]$3372 + attribute \src "libresoc.v:51044.5-51044.29" switch \initial - attribute \src "libresoc.v:51371.9-51371.17" + attribute \src "libresoc.v:51044.9-51044.17" case 1'1 case end @@ -91651,13 +91161,13 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\terminated$next[0:0]$3381 $2\terminated$next[0:0]$3382 + assign $1\terminated$next[0:0]$3365 $2\terminated$next[0:0]$3366 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\terminated$next[0:0]$3382 $3\terminated$next[0:0]$3383 + assign $2\terminated$next[0:0]$3366 $3\terminated$next[0:0]$3367 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$73 \$71 \$69 } attribute \src "libresoc.v:0.0-0.0" @@ -91665,74 +91175,74 @@ module \dbg assign { } { } assign { } { } assign { } { } - assign $3\terminated$next[0:0]$3383 $6\terminated$next[0:0]$3386 + assign $3\terminated$next[0:0]$3367 $6\terminated$next[0:0]$3370 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" switch \dmi_din [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\terminated$next[0:0]$3384 1'0 + assign $4\terminated$next[0:0]$3368 1'0 case - assign $4\terminated$next[0:0]$3384 \terminated + assign $4\terminated$next[0:0]$3368 \terminated end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" switch \dmi_din [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\terminated$next[0:0]$3385 1'0 + assign $5\terminated$next[0:0]$3369 1'0 case - assign $5\terminated$next[0:0]$3385 $4\terminated$next[0:0]$3384 + assign $5\terminated$next[0:0]$3369 $4\terminated$next[0:0]$3368 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" switch \dmi_din [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\terminated$next[0:0]$3386 1'0 + assign $6\terminated$next[0:0]$3370 1'0 case - assign $6\terminated$next[0:0]$3386 $5\terminated$next[0:0]$3385 + assign $6\terminated$next[0:0]$3370 $5\terminated$next[0:0]$3369 end case - assign $3\terminated$next[0:0]$3383 \terminated + assign $3\terminated$next[0:0]$3367 \terminated end case - assign $2\terminated$next[0:0]$3382 \terminated + assign $2\terminated$next[0:0]$3366 \terminated end case - assign $1\terminated$next[0:0]$3381 \terminated + assign $1\terminated$next[0:0]$3365 \terminated end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" switch \terminate_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\terminated$next[0:0]$3387 1'1 + assign $7\terminated$next[0:0]$3371 1'1 case - assign $7\terminated$next[0:0]$3387 $1\terminated$next[0:0]$3381 + assign $7\terminated$next[0:0]$3371 $1\terminated$next[0:0]$3365 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\terminated$next[0:0]$3388 1'0 + assign $8\terminated$next[0:0]$3372 1'0 case - assign $8\terminated$next[0:0]$3388 $7\terminated$next[0:0]$3387 + assign $8\terminated$next[0:0]$3372 $7\terminated$next[0:0]$3371 end sync always - update \terminated$next $0\terminated$next[0:0]$3380 + update \terminated$next $0\terminated$next[0:0]$3364 end - attribute \src "libresoc.v:51420.3-51463.6" - process $proc$libresoc.v:51420$3389 + attribute \src "libresoc.v:51093.3-51136.6" + process $proc$libresoc.v:51093$3373 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\stopping$next[0:0]$3390 $7\stopping$next[0:0]$3397 - attribute \src "libresoc.v:51421.5-51421.29" + assign $0\stopping$next[0:0]$3374 $7\stopping$next[0:0]$3381 + attribute \src "libresoc.v:51094.5-51094.29" switch \initial - attribute \src "libresoc.v:51421.9-51421.17" + attribute \src "libresoc.v:51094.9-51094.17" case 1'1 case end @@ -91741,77 +91251,77 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\stopping$next[0:0]$3391 $2\stopping$next[0:0]$3392 + assign $1\stopping$next[0:0]$3375 $2\stopping$next[0:0]$3376 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\stopping$next[0:0]$3392 $3\stopping$next[0:0]$3393 + assign $2\stopping$next[0:0]$3376 $3\stopping$next[0:0]$3377 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$87 \$85 \$83 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign { } { } - assign $3\stopping$next[0:0]$3393 $5\stopping$next[0:0]$3395 + assign $3\stopping$next[0:0]$3377 $5\stopping$next[0:0]$3379 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:214" switch \dmi_din [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\stopping$next[0:0]$3394 1'1 + assign $4\stopping$next[0:0]$3378 1'1 case - assign $4\stopping$next[0:0]$3394 \stopping + assign $4\stopping$next[0:0]$3378 \stopping end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" switch \dmi_din [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\stopping$next[0:0]$3395 1'0 + assign $5\stopping$next[0:0]$3379 1'0 case - assign $5\stopping$next[0:0]$3395 $4\stopping$next[0:0]$3394 + assign $5\stopping$next[0:0]$3379 $4\stopping$next[0:0]$3378 end case - assign $3\stopping$next[0:0]$3393 \stopping + assign $3\stopping$next[0:0]$3377 \stopping end case - assign $2\stopping$next[0:0]$3392 \stopping + assign $2\stopping$next[0:0]$3376 \stopping end case - assign $1\stopping$next[0:0]$3391 \stopping + assign $1\stopping$next[0:0]$3375 \stopping end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" switch \terminate_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\stopping$next[0:0]$3396 1'1 + assign $6\stopping$next[0:0]$3380 1'1 case - assign $6\stopping$next[0:0]$3396 $1\stopping$next[0:0]$3391 + assign $6\stopping$next[0:0]$3380 $1\stopping$next[0:0]$3375 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\stopping$next[0:0]$3397 1'0 + assign $7\stopping$next[0:0]$3381 1'0 case - assign $7\stopping$next[0:0]$3397 $6\stopping$next[0:0]$3396 + assign $7\stopping$next[0:0]$3381 $6\stopping$next[0:0]$3380 end sync always - update \stopping$next $0\stopping$next[0:0]$3390 + update \stopping$next $0\stopping$next[0:0]$3374 end - attribute \src "libresoc.v:51464.3-51491.6" - process $proc$libresoc.v:51464$3398 + attribute \src "libresoc.v:51137.3-51164.6" + process $proc$libresoc.v:51137$3382 assign { } { } assign { } { } assign { } { } - assign $0\gspr_index$next[6:0]$3399 $4\gspr_index$next[6:0]$3403 - attribute \src "libresoc.v:51465.5-51465.29" + assign $0\gspr_index$next[6:0]$3383 $4\gspr_index$next[6:0]$3387 + attribute \src "libresoc.v:51138.5-51138.29" switch \initial - attribute \src "libresoc.v:51465.9-51465.17" + attribute \src "libresoc.v:51138.9-51138.17" case 1'1 case end @@ -91820,52 +91330,52 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\gspr_index$next[6:0]$3400 $2\gspr_index$next[6:0]$3401 + assign $1\gspr_index$next[6:0]$3384 $2\gspr_index$next[6:0]$3385 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\gspr_index$next[6:0]$3401 $3\gspr_index$next[6:0]$3402 + assign $2\gspr_index$next[6:0]$3385 $3\gspr_index$next[6:0]$3386 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$101 \$99 \$97 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\gspr_index$next[6:0]$3402 \gspr_index + assign $3\gspr_index$next[6:0]$3386 \gspr_index attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $3\gspr_index$next[6:0]$3402 \dmi_din [6:0] + assign $3\gspr_index$next[6:0]$3386 \dmi_din [6:0] case - assign $3\gspr_index$next[6:0]$3402 \gspr_index + assign $3\gspr_index$next[6:0]$3386 \gspr_index end case - assign $2\gspr_index$next[6:0]$3401 \gspr_index + assign $2\gspr_index$next[6:0]$3385 \gspr_index end case - assign $1\gspr_index$next[6:0]$3400 \gspr_index + assign $1\gspr_index$next[6:0]$3384 \gspr_index end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\gspr_index$next[6:0]$3403 7'0000000 + assign $4\gspr_index$next[6:0]$3387 7'0000000 case - assign $4\gspr_index$next[6:0]$3403 $1\gspr_index$next[6:0]$3400 + assign $4\gspr_index$next[6:0]$3387 $1\gspr_index$next[6:0]$3384 end sync always - update \gspr_index$next $0\gspr_index$next[6:0]$3399 + update \gspr_index$next $0\gspr_index$next[6:0]$3383 end - attribute \src "libresoc.v:51492.3-51525.6" - process $proc$libresoc.v:51492$3404 + attribute \src "libresoc.v:51165.3-51198.6" + process $proc$libresoc.v:51165$3388 assign { } { } assign { } { } assign { } { } - assign $0\log_dmi_addr$next[31:0]$3405 $4\log_dmi_addr$next[31:0]$3409 - attribute \src "libresoc.v:51493.5-51493.29" + assign $0\log_dmi_addr$next[31:0]$3389 $4\log_dmi_addr$next[31:0]$3393 + attribute \src "libresoc.v:51166.5-51166.29" switch \initial - attribute \src "libresoc.v:51493.9-51493.17" + attribute \src "libresoc.v:51166.9-51166.17" case 1'1 case end @@ -91874,58 +91384,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\log_dmi_addr$next[31:0]$3406 $2\log_dmi_addr$next[31:0]$3407 + assign $1\log_dmi_addr$next[31:0]$3390 $2\log_dmi_addr$next[31:0]$3391 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\log_dmi_addr$next[31:0]$3407 $3\log_dmi_addr$next[31:0]$3408 + assign $2\log_dmi_addr$next[31:0]$3391 $3\log_dmi_addr$next[31:0]$3392 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$115 \$113 \$111 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $3\log_dmi_addr$next[31:0]$3408 \dmi_din [31:0] + assign $3\log_dmi_addr$next[31:0]$3392 \dmi_din [31:0] case - assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr end case - assign $2\log_dmi_addr$next[31:0]$3407 \log_dmi_addr + assign $2\log_dmi_addr$next[31:0]$3391 \log_dmi_addr end attribute \src "libresoc.v:0.0-0.0" case 2'1- - assign $1\log_dmi_addr$next[31:0]$3406 [31:2] \log_dmi_addr [31:2] - assign $1\log_dmi_addr$next[31:0]$3406 [1:0] \$117 [1:0] + assign $1\log_dmi_addr$next[31:0]$3390 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$3390 [1:0] \$117 [1:0] case - assign $1\log_dmi_addr$next[31:0]$3406 \log_dmi_addr + assign $1\log_dmi_addr$next[31:0]$3390 \log_dmi_addr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\log_dmi_addr$next[31:0]$3409 0 + assign $4\log_dmi_addr$next[31:0]$3393 0 case - assign $4\log_dmi_addr$next[31:0]$3409 $1\log_dmi_addr$next[31:0]$3406 + assign $4\log_dmi_addr$next[31:0]$3393 $1\log_dmi_addr$next[31:0]$3390 end sync always - update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3405 + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3389 end - attribute \src "libresoc.v:51526.3-51534.6" - process $proc$libresoc.v:51526$3410 + attribute \src "libresoc.v:51199.3-51207.6" + process $proc$libresoc.v:51199$3394 assign { } { } assign { } { } - assign $0\dmi_read_log_data_1$next[0:0]$3411 $1\dmi_read_log_data_1$next[0:0]$3412 - attribute \src "libresoc.v:51527.5-51527.29" + assign $0\dmi_read_log_data_1$next[0:0]$3395 $1\dmi_read_log_data_1$next[0:0]$3396 + attribute \src "libresoc.v:51200.5-51200.29" switch \initial - attribute \src "libresoc.v:51527.9-51527.17" + attribute \src "libresoc.v:51200.9-51200.17" case 1'1 case end @@ -91934,21 +91444,21 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_read_log_data_1$next[0:0]$3412 1'0 + assign $1\dmi_read_log_data_1$next[0:0]$3396 1'0 case - assign $1\dmi_read_log_data_1$next[0:0]$3412 \dmi_read_log_data + assign $1\dmi_read_log_data_1$next[0:0]$3396 \dmi_read_log_data end sync always - update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3411 + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3395 end - attribute \src "libresoc.v:51535.3-51543.6" - process $proc$libresoc.v:51535$3413 + attribute \src "libresoc.v:51208.3-51216.6" + process $proc$libresoc.v:51208$3397 assign { } { } assign { } { } - assign $0\dmi_read_log_data$next[0:0]$3414 $1\dmi_read_log_data$next[0:0]$3415 - attribute \src "libresoc.v:51536.5-51536.29" + assign $0\dmi_read_log_data$next[0:0]$3398 $1\dmi_read_log_data$next[0:0]$3399 + attribute \src "libresoc.v:51209.5-51209.29" switch \initial - attribute \src "libresoc.v:51536.9-51536.17" + attribute \src "libresoc.v:51209.9-51209.17" case 1'1 case end @@ -91957,27 +91467,30 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_read_log_data$next[0:0]$3415 1'0 + assign $1\dmi_read_log_data$next[0:0]$3399 1'0 case - assign $1\dmi_read_log_data$next[0:0]$3415 \$122 + assign $1\dmi_read_log_data$next[0:0]$3399 \$122 end sync always - update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3414 + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3398 end - attribute \src "libresoc.v:51544.3-51553.6" - process $proc$libresoc.v:51544$3416 + attribute \src "libresoc.v:51217.3-51229.6" + process $proc$libresoc.v:51217$3400 assign { } { } assign { } { } assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] - attribute \src "libresoc.v:51545.5-51545.29" + attribute \src "libresoc.v:51218.5-51218.29" switch \initial - attribute \src "libresoc.v:51545.9-51545.17" + attribute \src "libresoc.v:51218.9-51218.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\d_cr_req[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\d_cr_req[0:0] \dmi_req_i @@ -91987,20 +91500,26 @@ module \dbg sync always update \d_cr_req $0\d_cr_req[0:0] end - attribute \src "libresoc.v:51554.3-51563.6" - process $proc$libresoc.v:51554$3417 + attribute \src "libresoc.v:51230.3-51245.6" + process $proc$libresoc.v:51230$3401 assign { } { } assign { } { } assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] - attribute \src "libresoc.v:51555.5-51555.29" + attribute \src "libresoc.v:51231.5-51231.29" switch \initial - attribute \src "libresoc.v:51555.9-51555.17" + attribute \src "libresoc.v:51231.9-51231.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\d_xer_req[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign $1\d_xer_req[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\d_xer_req[0:0] \dmi_req_i @@ -92010,14 +91529,14 @@ module \dbg sync always update \d_xer_req $0\d_xer_req[0:0] end - attribute \src "libresoc.v:51564.3-51597.6" - process $proc$libresoc.v:51564$3418 + attribute \src "libresoc.v:51246.3-51279.6" + process $proc$libresoc.v:51246$3402 assign { } { } assign { } { } assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] - attribute \src "libresoc.v:51565.5-51565.29" + attribute \src "libresoc.v:51247.5-51247.29" switch \initial - attribute \src "libresoc.v:51565.9-51565.17" + attribute \src "libresoc.v:51247.9-51247.17" case 1'1 case end @@ -92065,15 +91584,15 @@ module \dbg sync always update \dmi_dout $0\dmi_dout[63:0] end - attribute \src "libresoc.v:51598.3-51627.6" - process $proc$libresoc.v:51598$3419 + attribute \src "libresoc.v:51280.3-51309.6" + process $proc$libresoc.v:51280$3403 assign { } { } assign { } { } assign { } { } - assign $0\do_step$next[0:0]$3420 $5\do_step$next[0:0]$3425 - attribute \src "libresoc.v:51599.5-51599.29" + assign $0\do_step$next[0:0]$3404 $5\do_step$next[0:0]$3409 + attribute \src "libresoc.v:51281.5-51281.29" switch \initial - attribute \src "libresoc.v:51599.9-51599.17" + attribute \src "libresoc.v:51281.9-51281.17" case 1'1 case end @@ -92082,58 +91601,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_step$next[0:0]$3421 $2\do_step$next[0:0]$3422 + assign $1\do_step$next[0:0]$3405 $2\do_step$next[0:0]$3406 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_step$next[0:0]$3422 $3\do_step$next[0:0]$3423 + assign $2\do_step$next[0:0]$3406 $3\do_step$next[0:0]$3407 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$17 \$15 \$13 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_step$next[0:0]$3423 $4\do_step$next[0:0]$3424 + assign $3\do_step$next[0:0]$3407 $4\do_step$next[0:0]$3408 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" switch \dmi_din [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_step$next[0:0]$3424 1'1 + assign $4\do_step$next[0:0]$3408 1'1 case - assign $4\do_step$next[0:0]$3424 1'0 + assign $4\do_step$next[0:0]$3408 1'0 end case - assign $3\do_step$next[0:0]$3423 1'0 + assign $3\do_step$next[0:0]$3407 1'0 end case - assign $2\do_step$next[0:0]$3422 1'0 + assign $2\do_step$next[0:0]$3406 1'0 end case - assign $1\do_step$next[0:0]$3421 1'0 + assign $1\do_step$next[0:0]$3405 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_step$next[0:0]$3425 1'0 + assign $5\do_step$next[0:0]$3409 1'0 case - assign $5\do_step$next[0:0]$3425 $1\do_step$next[0:0]$3421 + assign $5\do_step$next[0:0]$3409 $1\do_step$next[0:0]$3405 end sync always - update \do_step$next $0\do_step$next[0:0]$3420 + update \do_step$next $0\do_step$next[0:0]$3404 end - attribute \src "libresoc.v:51628.3-51657.6" - process $proc$libresoc.v:51628$3426 + attribute \src "libresoc.v:51310.3-51339.6" + process $proc$libresoc.v:51310$3410 assign { } { } assign { } { } assign { } { } - assign $0\do_reset$next[0:0]$3427 $5\do_reset$next[0:0]$3432 - attribute \src "libresoc.v:51629.5-51629.29" + assign $0\do_reset$next[0:0]$3411 $5\do_reset$next[0:0]$3416 + attribute \src "libresoc.v:51311.5-51311.29" switch \initial - attribute \src "libresoc.v:51629.9-51629.17" + attribute \src "libresoc.v:51311.9-51311.17" case 1'1 case end @@ -92142,58 +91661,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_reset$next[0:0]$3428 $2\do_reset$next[0:0]$3429 + assign $1\do_reset$next[0:0]$3412 $2\do_reset$next[0:0]$3413 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_reset$next[0:0]$3429 $3\do_reset$next[0:0]$3430 + assign $2\do_reset$next[0:0]$3413 $3\do_reset$next[0:0]$3414 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$31 \$29 \$27 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_reset$next[0:0]$3430 $4\do_reset$next[0:0]$3431 + assign $3\do_reset$next[0:0]$3414 $4\do_reset$next[0:0]$3415 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" switch \dmi_din [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_reset$next[0:0]$3431 1'1 + assign $4\do_reset$next[0:0]$3415 1'1 case - assign $4\do_reset$next[0:0]$3431 1'0 + assign $4\do_reset$next[0:0]$3415 1'0 end case - assign $3\do_reset$next[0:0]$3430 1'0 + assign $3\do_reset$next[0:0]$3414 1'0 end case - assign $2\do_reset$next[0:0]$3429 1'0 + assign $2\do_reset$next[0:0]$3413 1'0 end case - assign $1\do_reset$next[0:0]$3428 1'0 + assign $1\do_reset$next[0:0]$3412 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_reset$next[0:0]$3432 1'0 + assign $5\do_reset$next[0:0]$3416 1'0 case - assign $5\do_reset$next[0:0]$3432 $1\do_reset$next[0:0]$3428 + assign $5\do_reset$next[0:0]$3416 $1\do_reset$next[0:0]$3412 end sync always - update \do_reset$next $0\do_reset$next[0:0]$3427 + update \do_reset$next $0\do_reset$next[0:0]$3411 end - attribute \src "libresoc.v:51658.3-51687.6" - process $proc$libresoc.v:51658$3433 + attribute \src "libresoc.v:51340.3-51369.6" + process $proc$libresoc.v:51340$3417 assign { } { } assign { } { } assign { } { } - assign $0\do_icreset$next[0:0]$3434 $5\do_icreset$next[0:0]$3439 - attribute \src "libresoc.v:51659.5-51659.29" + assign $0\do_icreset$next[0:0]$3418 $5\do_icreset$next[0:0]$3423 + attribute \src "libresoc.v:51341.5-51341.29" switch \initial - attribute \src "libresoc.v:51659.9-51659.17" + attribute \src "libresoc.v:51341.9-51341.17" case 1'1 case end @@ -92202,58 +91721,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_icreset$next[0:0]$3435 $2\do_icreset$next[0:0]$3436 + assign $1\do_icreset$next[0:0]$3419 $2\do_icreset$next[0:0]$3420 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_icreset$next[0:0]$3436 $3\do_icreset$next[0:0]$3437 + assign $2\do_icreset$next[0:0]$3420 $3\do_icreset$next[0:0]$3421 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$45 \$43 \$41 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_icreset$next[0:0]$3437 $4\do_icreset$next[0:0]$3438 + assign $3\do_icreset$next[0:0]$3421 $4\do_icreset$next[0:0]$3422 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" switch \dmi_din [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_icreset$next[0:0]$3438 1'1 + assign $4\do_icreset$next[0:0]$3422 1'1 case - assign $4\do_icreset$next[0:0]$3438 1'0 + assign $4\do_icreset$next[0:0]$3422 1'0 end case - assign $3\do_icreset$next[0:0]$3437 1'0 + assign $3\do_icreset$next[0:0]$3421 1'0 end case - assign $2\do_icreset$next[0:0]$3436 1'0 + assign $2\do_icreset$next[0:0]$3420 1'0 end case - assign $1\do_icreset$next[0:0]$3435 1'0 + assign $1\do_icreset$next[0:0]$3419 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_icreset$next[0:0]$3439 1'0 + assign $5\do_icreset$next[0:0]$3423 1'0 case - assign $5\do_icreset$next[0:0]$3439 $1\do_icreset$next[0:0]$3435 + assign $5\do_icreset$next[0:0]$3423 $1\do_icreset$next[0:0]$3419 end sync always - update \do_icreset$next $0\do_icreset$next[0:0]$3434 + update \do_icreset$next $0\do_icreset$next[0:0]$3418 end - attribute \src "libresoc.v:51688.3-51721.6" - process $proc$libresoc.v:51688$3440 + attribute \src "libresoc.v:51370.3-51403.6" + process $proc$libresoc.v:51370$3424 assign { } { } assign { } { } assign { } { } - assign $0\do_dmi_log_rd$next[0:0]$3441 $4\do_dmi_log_rd$next[0:0]$3445 - attribute \src "libresoc.v:51689.5-51689.29" + assign $0\do_dmi_log_rd$next[0:0]$3425 $4\do_dmi_log_rd$next[0:0]$3429 + attribute \src "libresoc.v:51371.5-51371.29" switch \initial - attribute \src "libresoc.v:51689.9-51689.17" + attribute \src "libresoc.v:51371.9-51371.17" case 1'1 case end @@ -92262,113 +91781,113 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3442 $2\do_dmi_log_rd$next[0:0]$3443 + assign $1\do_dmi_log_rd$next[0:0]$3426 $2\do_dmi_log_rd$next[0:0]$3427 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_dmi_log_rd$next[0:0]$3443 $3\do_dmi_log_rd$next[0:0]$3444 + assign $2\do_dmi_log_rd$next[0:0]$3427 $3\do_dmi_log_rd$next[0:0]$3428 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$59 \$57 \$55 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\do_dmi_log_rd$next[0:0]$3444 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $3\do_dmi_log_rd$next[0:0]$3444 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $3\do_dmi_log_rd$next[0:0]$3444 1'1 + assign $3\do_dmi_log_rd$next[0:0]$3428 1'1 case - assign $3\do_dmi_log_rd$next[0:0]$3444 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 end case - assign $2\do_dmi_log_rd$next[0:0]$3443 1'0 + assign $2\do_dmi_log_rd$next[0:0]$3427 1'0 end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3442 1'1 + assign $1\do_dmi_log_rd$next[0:0]$3426 1'1 case - assign $1\do_dmi_log_rd$next[0:0]$3442 1'0 + assign $1\do_dmi_log_rd$next[0:0]$3426 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_dmi_log_rd$next[0:0]$3445 1'0 - case - assign $4\do_dmi_log_rd$next[0:0]$3445 $1\do_dmi_log_rd$next[0:0]$3442 - end - sync always - update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3441 - end - connect \$9 $not$libresoc.v:51248$3300_Y - connect \$99 $eq$libresoc.v:51249$3301_Y - connect \$101 $eq$libresoc.v:51250$3302_Y - connect \$103 $not$libresoc.v:51251$3303_Y - connect \$105 $and$libresoc.v:51252$3304_Y - connect \$107 $not$libresoc.v:51253$3305_Y - connect \$109 $and$libresoc.v:51254$3306_Y - connect \$111 $eq$libresoc.v:51255$3307_Y - connect \$113 $eq$libresoc.v:51256$3308_Y - connect \$115 $eq$libresoc.v:51257$3309_Y - connect \$118 $add$libresoc.v:51258$3310_Y - connect \$11 $and$libresoc.v:51259$3311_Y - connect \$120 $eq$libresoc.v:51260$3312_Y - connect \$122 $and$libresoc.v:51261$3313_Y - connect \$124 $not$libresoc.v:51262$3314_Y - connect \$126 $and$libresoc.v:51263$3315_Y - connect \$13 $eq$libresoc.v:51264$3316_Y - connect \$15 $eq$libresoc.v:51265$3317_Y - connect \$17 $eq$libresoc.v:51266$3318_Y - connect \$1 $pos$libresoc.v:51267$3319_Y - connect \$19 $not$libresoc.v:51268$3320_Y - connect \$21 $and$libresoc.v:51269$3321_Y - connect \$23 $not$libresoc.v:51270$3322_Y - connect \$25 $and$libresoc.v:51271$3323_Y - connect \$27 $eq$libresoc.v:51272$3324_Y - connect \$29 $eq$libresoc.v:51273$3325_Y - connect \$31 $eq$libresoc.v:51274$3326_Y - connect \$33 $not$libresoc.v:51275$3327_Y - connect \$35 $and$libresoc.v:51276$3328_Y - connect \$37 $not$libresoc.v:51277$3329_Y - connect \$3 $pos$libresoc.v:51278$3330_Y - connect \$39 $and$libresoc.v:51279$3331_Y - connect \$41 $eq$libresoc.v:51280$3332_Y - connect \$43 $eq$libresoc.v:51281$3333_Y - connect \$45 $eq$libresoc.v:51282$3334_Y - connect \$47 $not$libresoc.v:51283$3335_Y - connect \$49 $and$libresoc.v:51284$3336_Y - connect \$51 $not$libresoc.v:51285$3337_Y - connect \$53 $and$libresoc.v:51286$3338_Y - connect \$55 $eq$libresoc.v:51287$3339_Y - connect \$57 $eq$libresoc.v:51288$3340_Y - connect \$5 $not$libresoc.v:51289$3341_Y - connect \$59 $eq$libresoc.v:51290$3342_Y - connect \$61 $not$libresoc.v:51291$3343_Y - connect \$63 $and$libresoc.v:51292$3344_Y - connect \$65 $not$libresoc.v:51293$3345_Y - connect \$67 $and$libresoc.v:51294$3346_Y - connect \$69 $eq$libresoc.v:51295$3347_Y - connect \$71 $eq$libresoc.v:51296$3348_Y - connect \$73 $eq$libresoc.v:51297$3349_Y - connect \$75 $not$libresoc.v:51298$3350_Y - connect \$77 $and$libresoc.v:51299$3351_Y - connect \$7 $and$libresoc.v:51300$3352_Y - connect \$79 $not$libresoc.v:51301$3353_Y - connect \$81 $and$libresoc.v:51302$3354_Y - connect \$83 $eq$libresoc.v:51303$3355_Y - connect \$85 $eq$libresoc.v:51304$3356_Y - connect \$87 $eq$libresoc.v:51305$3357_Y - connect \$89 $not$libresoc.v:51306$3358_Y - connect \$91 $and$libresoc.v:51307$3359_Y - connect \$93 $not$libresoc.v:51308$3360_Y - connect \$95 $and$libresoc.v:51309$3361_Y - connect \$97 $eq$libresoc.v:51310$3362_Y + assign $4\do_dmi_log_rd$next[0:0]$3429 1'0 + case + assign $4\do_dmi_log_rd$next[0:0]$3429 $1\do_dmi_log_rd$next[0:0]$3426 + end + sync always + update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3425 + end + connect \$9 $not$libresoc.v:50921$3284_Y + connect \$99 $eq$libresoc.v:50922$3285_Y + connect \$101 $eq$libresoc.v:50923$3286_Y + connect \$103 $not$libresoc.v:50924$3287_Y + connect \$105 $and$libresoc.v:50925$3288_Y + connect \$107 $not$libresoc.v:50926$3289_Y + connect \$109 $and$libresoc.v:50927$3290_Y + connect \$111 $eq$libresoc.v:50928$3291_Y + connect \$113 $eq$libresoc.v:50929$3292_Y + connect \$115 $eq$libresoc.v:50930$3293_Y + connect \$118 $add$libresoc.v:50931$3294_Y + connect \$11 $and$libresoc.v:50932$3295_Y + connect \$120 $eq$libresoc.v:50933$3296_Y + connect \$122 $and$libresoc.v:50934$3297_Y + connect \$124 $not$libresoc.v:50935$3298_Y + connect \$126 $and$libresoc.v:50936$3299_Y + connect \$13 $eq$libresoc.v:50937$3300_Y + connect \$15 $eq$libresoc.v:50938$3301_Y + connect \$17 $eq$libresoc.v:50939$3302_Y + connect \$1 $pos$libresoc.v:50940$3303_Y + connect \$19 $not$libresoc.v:50941$3304_Y + connect \$21 $and$libresoc.v:50942$3305_Y + connect \$23 $not$libresoc.v:50943$3306_Y + connect \$25 $and$libresoc.v:50944$3307_Y + connect \$27 $eq$libresoc.v:50945$3308_Y + connect \$29 $eq$libresoc.v:50946$3309_Y + connect \$31 $eq$libresoc.v:50947$3310_Y + connect \$33 $not$libresoc.v:50948$3311_Y + connect \$35 $and$libresoc.v:50949$3312_Y + connect \$37 $not$libresoc.v:50950$3313_Y + connect \$3 $pos$libresoc.v:50951$3314_Y + connect \$39 $and$libresoc.v:50952$3315_Y + connect \$41 $eq$libresoc.v:50953$3316_Y + connect \$43 $eq$libresoc.v:50954$3317_Y + connect \$45 $eq$libresoc.v:50955$3318_Y + connect \$47 $not$libresoc.v:50956$3319_Y + connect \$49 $and$libresoc.v:50957$3320_Y + connect \$51 $not$libresoc.v:50958$3321_Y + connect \$53 $and$libresoc.v:50959$3322_Y + connect \$55 $eq$libresoc.v:50960$3323_Y + connect \$57 $eq$libresoc.v:50961$3324_Y + connect \$5 $not$libresoc.v:50962$3325_Y + connect \$59 $eq$libresoc.v:50963$3326_Y + connect \$61 $not$libresoc.v:50964$3327_Y + connect \$63 $and$libresoc.v:50965$3328_Y + connect \$65 $not$libresoc.v:50966$3329_Y + connect \$67 $and$libresoc.v:50967$3330_Y + connect \$69 $eq$libresoc.v:50968$3331_Y + connect \$71 $eq$libresoc.v:50969$3332_Y + connect \$73 $eq$libresoc.v:50970$3333_Y + connect \$75 $not$libresoc.v:50971$3334_Y + connect \$77 $and$libresoc.v:50972$3335_Y + connect \$7 $and$libresoc.v:50973$3336_Y + connect \$79 $not$libresoc.v:50974$3337_Y + connect \$81 $and$libresoc.v:50975$3338_Y + connect \$83 $eq$libresoc.v:50976$3339_Y + connect \$85 $eq$libresoc.v:50977$3340_Y + connect \$87 $eq$libresoc.v:50978$3341_Y + connect \$89 $not$libresoc.v:50979$3342_Y + connect \$91 $and$libresoc.v:50980$3343_Y + connect \$93 $not$libresoc.v:50981$3344_Y + connect \$95 $and$libresoc.v:50982$3345_Y + connect \$97 $eq$libresoc.v:50983$3346_Y connect \$117 \$118 connect \log_write_addr_o 0 connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -92379,71 +91898,71 @@ module \dbg connect \d_gpr_addr \gspr_index connect \stat_reg \$1 end -attribute \src "libresoc.v:51735.1-53785.10" +attribute \src "libresoc.v:51417.1-53467.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec" attribute \generator "nMigen" module \dec - attribute \src "libresoc.v:53346.3-53379.6" + attribute \src "libresoc.v:53028.3-53061.6" wire width 3 $0\ALU_cr_in[2:0] - attribute \src "libresoc.v:53380.3-53413.6" + attribute \src "libresoc.v:53062.3-53095.6" wire width 3 $0\ALU_cr_out[2:0] - attribute \src "libresoc.v:53006.3-53039.6" + attribute \src "libresoc.v:52688.3-52721.6" wire width 2 $0\ALU_cry_in[1:0] - attribute \src "libresoc.v:53108.3-53141.6" + attribute \src "libresoc.v:52790.3-52823.6" wire $0\ALU_cry_out[0:0] - attribute \src "libresoc.v:53210.3-53243.6" + attribute \src "libresoc.v:52892.3-52925.6" wire width 14 $0\ALU_function_unit[13:0] - attribute \src "libresoc.v:53278.3-53311.6" + attribute \src "libresoc.v:52960.3-52993.6" wire width 3 $0\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53312.3-53345.6" + attribute \src "libresoc.v:52994.3-53027.6" wire width 4 $0\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53244.3-53277.6" + attribute \src "libresoc.v:52926.3-52959.6" wire width 7 $0\ALU_internal_op[6:0] - attribute \src "libresoc.v:53040.3-53073.6" + attribute \src "libresoc.v:52722.3-52755.6" wire $0\ALU_inv_a[0:0] - attribute \src "libresoc.v:53074.3-53107.6" + attribute \src "libresoc.v:52756.3-52789.6" wire $0\ALU_inv_out[0:0] - attribute \src "libresoc.v:53142.3-53175.6" + attribute \src "libresoc.v:52824.3-52857.6" wire $0\ALU_is_32b[0:0] - attribute \src "libresoc.v:53414.3-53447.6" + attribute \src "libresoc.v:53096.3-53129.6" wire width 4 $0\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52972.3-53005.6" + attribute \src "libresoc.v:52654.3-52687.6" wire width 2 $0\ALU_rc_sel[1:0] - attribute \src "libresoc.v:53176.3-53209.6" + attribute \src "libresoc.v:52858.3-52891.6" wire $0\ALU_sgn[0:0] - attribute \src "libresoc.v:51736.7-51736.20" + attribute \src "libresoc.v:51418.7-51418.20" wire $0\initial[0:0] - attribute \src "libresoc.v:53346.3-53379.6" + attribute \src "libresoc.v:53028.3-53061.6" wire width 3 $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:53380.3-53413.6" + attribute \src "libresoc.v:53062.3-53095.6" wire width 3 $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:53006.3-53039.6" + attribute \src "libresoc.v:52688.3-52721.6" wire width 2 $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:53108.3-53141.6" + attribute \src "libresoc.v:52790.3-52823.6" wire $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:53210.3-53243.6" + attribute \src "libresoc.v:52892.3-52925.6" wire width 14 $1\ALU_function_unit[13:0] - attribute \src "libresoc.v:53278.3-53311.6" + attribute \src "libresoc.v:52960.3-52993.6" wire width 3 $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53312.3-53345.6" + attribute \src "libresoc.v:52994.3-53027.6" wire width 4 $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53244.3-53277.6" + attribute \src "libresoc.v:52926.3-52959.6" wire width 7 $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:53040.3-53073.6" + attribute \src "libresoc.v:52722.3-52755.6" wire $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:53074.3-53107.6" + attribute \src "libresoc.v:52756.3-52789.6" wire $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:53142.3-53175.6" + attribute \src "libresoc.v:52824.3-52857.6" wire $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:53414.3-53447.6" + attribute \src "libresoc.v:53096.3-53129.6" wire width 4 $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52972.3-53005.6" + attribute \src "libresoc.v:52654.3-52687.6" wire width 2 $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:53176.3-53209.6" + attribute \src "libresoc.v:52858.3-52891.6" wire $1\ALU_sgn[0:0] - attribute \src "libresoc.v:52937.17-52937.211" - wire width 32 $ternary$libresoc.v:52937$3458_Y + attribute \src "libresoc.v:52619.17-52619.211" + wire width 32 $ternary$libresoc.v:52619$3442_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -93625,7 +93144,7 @@ module \dec wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:51736.7-51736.15" + attribute \src "libresoc.v:51418.7-51418.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -93634,15 +93153,15 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:52937$3458 + cell $mux $ternary$libresoc.v:52619$3442 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:52937$3458_Y + connect \Y $ternary$libresoc.v:52619$3442_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:52938.13-52954.4" + attribute \src "libresoc.v:52620.13-52636.4" cell \ALU_dec19 \ALU_dec19 connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out @@ -93661,7 +93180,7 @@ module \dec connect \opcode_in \ALU_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:52955.13-52971.4" + attribute \src "libresoc.v:52637.13-52653.4" cell \ALU_dec31 \ALU_dec31 connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out @@ -93679,22 +93198,22 @@ module \dec connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn connect \opcode_in \ALU_dec31_opcode_in end - attribute \src "libresoc.v:51736.7-51736.20" - process $proc$libresoc.v:51736$3473 + attribute \src "libresoc.v:51418.7-51418.20" + process $proc$libresoc.v:51418$3457 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:52972.3-53005.6" - process $proc$libresoc.v:52972$3459 + attribute \src "libresoc.v:52654.3-52687.6" + process $proc$libresoc.v:52654$3443 assign { } { } assign { } { } assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:52973.5-52973.29" + attribute \src "libresoc.v:52655.5-52655.29" switch \initial - attribute \src "libresoc.v:52973.9-52973.17" + attribute \src "libresoc.v:52655.9-52655.17" case 1'1 case end @@ -93742,14 +93261,14 @@ module \dec sync always update \ALU_rc_sel $0\ALU_rc_sel[1:0] end - attribute \src "libresoc.v:53006.3-53039.6" - process $proc$libresoc.v:53006$3460 + attribute \src "libresoc.v:52688.3-52721.6" + process $proc$libresoc.v:52688$3444 assign { } { } assign { } { } assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:53007.5-53007.29" + attribute \src "libresoc.v:52689.5-52689.29" switch \initial - attribute \src "libresoc.v:53007.9-53007.17" + attribute \src "libresoc.v:52689.9-52689.17" case 1'1 case end @@ -93797,14 +93316,14 @@ module \dec sync always update \ALU_cry_in $0\ALU_cry_in[1:0] end - attribute \src "libresoc.v:53040.3-53073.6" - process $proc$libresoc.v:53040$3461 + attribute \src "libresoc.v:52722.3-52755.6" + process $proc$libresoc.v:52722$3445 assign { } { } assign { } { } assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:53041.5-53041.29" + attribute \src "libresoc.v:52723.5-52723.29" switch \initial - attribute \src "libresoc.v:53041.9-53041.17" + attribute \src "libresoc.v:52723.9-52723.17" case 1'1 case end @@ -93852,14 +93371,14 @@ module \dec sync always update \ALU_inv_a $0\ALU_inv_a[0:0] end - attribute \src "libresoc.v:53074.3-53107.6" - process $proc$libresoc.v:53074$3462 + attribute \src "libresoc.v:52756.3-52789.6" + process $proc$libresoc.v:52756$3446 assign { } { } assign { } { } assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:53075.5-53075.29" + attribute \src "libresoc.v:52757.5-52757.29" switch \initial - attribute \src "libresoc.v:53075.9-53075.17" + attribute \src "libresoc.v:52757.9-52757.17" case 1'1 case end @@ -93907,14 +93426,14 @@ module \dec sync always update \ALU_inv_out $0\ALU_inv_out[0:0] end - attribute \src "libresoc.v:53108.3-53141.6" - process $proc$libresoc.v:53108$3463 + attribute \src "libresoc.v:52790.3-52823.6" + process $proc$libresoc.v:52790$3447 assign { } { } assign { } { } assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:53109.5-53109.29" + attribute \src "libresoc.v:52791.5-52791.29" switch \initial - attribute \src "libresoc.v:53109.9-53109.17" + attribute \src "libresoc.v:52791.9-52791.17" case 1'1 case end @@ -93962,14 +93481,14 @@ module \dec sync always update \ALU_cry_out $0\ALU_cry_out[0:0] end - attribute \src "libresoc.v:53142.3-53175.6" - process $proc$libresoc.v:53142$3464 + attribute \src "libresoc.v:52824.3-52857.6" + process $proc$libresoc.v:52824$3448 assign { } { } assign { } { } assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:53143.5-53143.29" + attribute \src "libresoc.v:52825.5-52825.29" switch \initial - attribute \src "libresoc.v:53143.9-53143.17" + attribute \src "libresoc.v:52825.9-52825.17" case 1'1 case end @@ -94017,14 +93536,14 @@ module \dec sync always update \ALU_is_32b $0\ALU_is_32b[0:0] end - attribute \src "libresoc.v:53176.3-53209.6" - process $proc$libresoc.v:53176$3465 + attribute \src "libresoc.v:52858.3-52891.6" + process $proc$libresoc.v:52858$3449 assign { } { } assign { } { } assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] - attribute \src "libresoc.v:53177.5-53177.29" + attribute \src "libresoc.v:52859.5-52859.29" switch \initial - attribute \src "libresoc.v:53177.9-53177.17" + attribute \src "libresoc.v:52859.9-52859.17" case 1'1 case end @@ -94072,14 +93591,14 @@ module \dec sync always update \ALU_sgn $0\ALU_sgn[0:0] end - attribute \src "libresoc.v:53210.3-53243.6" - process $proc$libresoc.v:53210$3466 + attribute \src "libresoc.v:52892.3-52925.6" + process $proc$libresoc.v:52892$3450 assign { } { } assign { } { } assign $0\ALU_function_unit[13:0] $1\ALU_function_unit[13:0] - attribute \src "libresoc.v:53211.5-53211.29" + attribute \src "libresoc.v:52893.5-52893.29" switch \initial - attribute \src "libresoc.v:53211.9-53211.17" + attribute \src "libresoc.v:52893.9-52893.17" case 1'1 case end @@ -94127,14 +93646,14 @@ module \dec sync always update \ALU_function_unit $0\ALU_function_unit[13:0] end - attribute \src "libresoc.v:53244.3-53277.6" - process $proc$libresoc.v:53244$3467 + attribute \src "libresoc.v:52926.3-52959.6" + process $proc$libresoc.v:52926$3451 assign { } { } assign { } { } assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:53245.5-53245.29" + attribute \src "libresoc.v:52927.5-52927.29" switch \initial - attribute \src "libresoc.v:53245.9-53245.17" + attribute \src "libresoc.v:52927.9-52927.17" case 1'1 case end @@ -94182,14 +93701,14 @@ module \dec sync always update \ALU_internal_op $0\ALU_internal_op[6:0] end - attribute \src "libresoc.v:53278.3-53311.6" - process $proc$libresoc.v:53278$3468 + attribute \src "libresoc.v:52960.3-52993.6" + process $proc$libresoc.v:52960$3452 assign { } { } assign { } { } assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53279.5-53279.29" + attribute \src "libresoc.v:52961.5-52961.29" switch \initial - attribute \src "libresoc.v:53279.9-53279.17" + attribute \src "libresoc.v:52961.9-52961.17" case 1'1 case end @@ -94237,14 +93756,14 @@ module \dec sync always update \ALU_in1_sel $0\ALU_in1_sel[2:0] end - attribute \src "libresoc.v:53312.3-53345.6" - process $proc$libresoc.v:53312$3469 + attribute \src "libresoc.v:52994.3-53027.6" + process $proc$libresoc.v:52994$3453 assign { } { } assign { } { } assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53313.5-53313.29" + attribute \src "libresoc.v:52995.5-52995.29" switch \initial - attribute \src "libresoc.v:53313.9-53313.17" + attribute \src "libresoc.v:52995.9-52995.17" case 1'1 case end @@ -94292,14 +93811,14 @@ module \dec sync always update \ALU_in2_sel $0\ALU_in2_sel[3:0] end - attribute \src "libresoc.v:53346.3-53379.6" - process $proc$libresoc.v:53346$3470 + attribute \src "libresoc.v:53028.3-53061.6" + process $proc$libresoc.v:53028$3454 assign { } { } assign { } { } assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:53347.5-53347.29" + attribute \src "libresoc.v:53029.5-53029.29" switch \initial - attribute \src "libresoc.v:53347.9-53347.17" + attribute \src "libresoc.v:53029.9-53029.17" case 1'1 case end @@ -94347,14 +93866,14 @@ module \dec sync always update \ALU_cr_in $0\ALU_cr_in[2:0] end - attribute \src "libresoc.v:53380.3-53413.6" - process $proc$libresoc.v:53380$3471 + attribute \src "libresoc.v:53062.3-53095.6" + process $proc$libresoc.v:53062$3455 assign { } { } assign { } { } assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:53381.5-53381.29" + attribute \src "libresoc.v:53063.5-53063.29" switch \initial - attribute \src "libresoc.v:53381.9-53381.17" + attribute \src "libresoc.v:53063.9-53063.17" case 1'1 case end @@ -94402,14 +93921,14 @@ module \dec sync always update \ALU_cr_out $0\ALU_cr_out[2:0] end - attribute \src "libresoc.v:53414.3-53447.6" - process $proc$libresoc.v:53414$3472 + attribute \src "libresoc.v:53096.3-53129.6" + process $proc$libresoc.v:53096$3456 assign { } { } assign { } { } assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:53415.5-53415.29" + attribute \src "libresoc.v:53097.5-53097.29" switch \initial - attribute \src "libresoc.v:53415.9-53415.17" + attribute \src "libresoc.v:53097.9-53097.17" case 1'1 case end @@ -94457,7 +93976,7 @@ module \dec sync always update \ALU_ldst_len $0\ALU_ldst_len[3:0] end - connect \$1 $ternary$libresoc.v:52937$3458_Y + connect \$1 $ternary$libresoc.v:52619$3442_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -94796,35 +94315,35 @@ module \dec connect \ALU_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:53789.1-55254.10" +attribute \src "libresoc.v:53471.1-54936.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec" attribute \generator "nMigen" module \dec$138 - attribute \src "libresoc.v:54878.3-54890.6" + attribute \src "libresoc.v:54560.3-54572.6" wire width 3 $0\CR_cr_in[2:0] - attribute \src "libresoc.v:54891.3-54903.6" + attribute \src "libresoc.v:54573.3-54585.6" wire width 3 $0\CR_cr_out[2:0] - attribute \src "libresoc.v:54852.3-54864.6" + attribute \src "libresoc.v:54534.3-54546.6" wire width 14 $0\CR_function_unit[13:0] - attribute \src "libresoc.v:54865.3-54877.6" + attribute \src "libresoc.v:54547.3-54559.6" wire width 7 $0\CR_internal_op[6:0] - attribute \src "libresoc.v:54904.3-54916.6" + attribute \src "libresoc.v:54586.3-54598.6" wire width 2 $0\CR_rc_sel[1:0] - attribute \src "libresoc.v:53790.7-53790.20" + attribute \src "libresoc.v:53472.7-53472.20" wire $0\initial[0:0] - attribute \src "libresoc.v:54878.3-54890.6" + attribute \src "libresoc.v:54560.3-54572.6" wire width 3 $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54891.3-54903.6" + attribute \src "libresoc.v:54573.3-54585.6" wire width 3 $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54852.3-54864.6" + attribute \src "libresoc.v:54534.3-54546.6" wire width 14 $1\CR_function_unit[13:0] - attribute \src "libresoc.v:54865.3-54877.6" + attribute \src "libresoc.v:54547.3-54559.6" wire width 7 $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54904.3-54916.6" + attribute \src "libresoc.v:54586.3-54598.6" wire width 2 $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54835.17-54835.211" - wire width 32 $ternary$libresoc.v:54835$3474_Y + attribute \src "libresoc.v:54517.17-54517.211" + wire width 32 $ternary$libresoc.v:54517$3458_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -95859,7 +95378,7 @@ module \dec$138 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:53790.7-53790.15" + attribute \src "libresoc.v:53472.7-53472.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -95868,15 +95387,15 @@ module \dec$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 10 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:54835$3474 + cell $mux $ternary$libresoc.v:54517$3458 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:54835$3474_Y + connect \Y $ternary$libresoc.v:54517$3458_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:54836.12-54843.4" + attribute \src "libresoc.v:54518.12-54525.4" cell \CR_dec19 \CR_dec19 connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out @@ -95886,7 +95405,7 @@ module \dec$138 connect \opcode_in \CR_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:54844.12-54851.4" + attribute \src "libresoc.v:54526.12-54533.4" cell \CR_dec31 \CR_dec31 connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out @@ -95895,22 +95414,22 @@ module \dec$138 connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel connect \opcode_in \CR_dec31_opcode_in end - attribute \src "libresoc.v:53790.7-53790.20" - process $proc$libresoc.v:53790$3480 + attribute \src "libresoc.v:53472.7-53472.20" + process $proc$libresoc.v:53472$3464 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:54852.3-54864.6" - process $proc$libresoc.v:54852$3475 + attribute \src "libresoc.v:54534.3-54546.6" + process $proc$libresoc.v:54534$3459 assign { } { } assign { } { } assign $0\CR_function_unit[13:0] $1\CR_function_unit[13:0] - attribute \src "libresoc.v:54853.5-54853.29" + attribute \src "libresoc.v:54535.5-54535.29" switch \initial - attribute \src "libresoc.v:54853.9-54853.17" + attribute \src "libresoc.v:54535.9-54535.17" case 1'1 case end @@ -95930,14 +95449,14 @@ module \dec$138 sync always update \CR_function_unit $0\CR_function_unit[13:0] end - attribute \src "libresoc.v:54865.3-54877.6" - process $proc$libresoc.v:54865$3476 + attribute \src "libresoc.v:54547.3-54559.6" + process $proc$libresoc.v:54547$3460 assign { } { } assign { } { } assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54866.5-54866.29" + attribute \src "libresoc.v:54548.5-54548.29" switch \initial - attribute \src "libresoc.v:54866.9-54866.17" + attribute \src "libresoc.v:54548.9-54548.17" case 1'1 case end @@ -95957,14 +95476,14 @@ module \dec$138 sync always update \CR_internal_op $0\CR_internal_op[6:0] end - attribute \src "libresoc.v:54878.3-54890.6" - process $proc$libresoc.v:54878$3477 + attribute \src "libresoc.v:54560.3-54572.6" + process $proc$libresoc.v:54560$3461 assign { } { } assign { } { } assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54879.5-54879.29" + attribute \src "libresoc.v:54561.5-54561.29" switch \initial - attribute \src "libresoc.v:54879.9-54879.17" + attribute \src "libresoc.v:54561.9-54561.17" case 1'1 case end @@ -95984,14 +95503,14 @@ module \dec$138 sync always update \CR_cr_in $0\CR_cr_in[2:0] end - attribute \src "libresoc.v:54891.3-54903.6" - process $proc$libresoc.v:54891$3478 + attribute \src "libresoc.v:54573.3-54585.6" + process $proc$libresoc.v:54573$3462 assign { } { } assign { } { } assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54892.5-54892.29" + attribute \src "libresoc.v:54574.5-54574.29" switch \initial - attribute \src "libresoc.v:54892.9-54892.17" + attribute \src "libresoc.v:54574.9-54574.17" case 1'1 case end @@ -96011,14 +95530,14 @@ module \dec$138 sync always update \CR_cr_out $0\CR_cr_out[2:0] end - attribute \src "libresoc.v:54904.3-54916.6" - process $proc$libresoc.v:54904$3479 + attribute \src "libresoc.v:54586.3-54598.6" + process $proc$libresoc.v:54586$3463 assign { } { } assign { } { } assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54905.5-54905.29" + attribute \src "libresoc.v:54587.5-54587.29" switch \initial - attribute \src "libresoc.v:54905.9-54905.17" + attribute \src "libresoc.v:54587.9-54587.17" case 1'1 case end @@ -96038,7 +95557,7 @@ module \dec$138 sync always update \CR_rc_sel $0\CR_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:54835$3474_Y + connect \$1 $ternary$libresoc.v:54517$3458_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -96377,47 +95896,47 @@ module \dec$138 connect \CR_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:55258.1-56703.10" +attribute \src "libresoc.v:54940.1-56385.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec" attribute \generator "nMigen" module \dec$141 - attribute \src "libresoc.v:56287.3-56302.6" + attribute \src "libresoc.v:55969.3-55984.6" wire width 3 $0\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56303.3-56318.6" + attribute \src "libresoc.v:55985.3-56000.6" wire width 3 $0\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56239.3-56254.6" + attribute \src "libresoc.v:55921.3-55936.6" wire width 14 $0\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56271.3-56286.6" + attribute \src "libresoc.v:55953.3-55968.6" wire width 4 $0\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56255.3-56270.6" + attribute \src "libresoc.v:55937.3-55952.6" wire width 7 $0\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56335.3-56350.6" + attribute \src "libresoc.v:56017.3-56032.6" wire $0\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56351.3-56366.6" + attribute \src "libresoc.v:56033.3-56048.6" wire $0\BRANCH_lk[0:0] - attribute \src "libresoc.v:56319.3-56334.6" + attribute \src "libresoc.v:56001.3-56016.6" wire width 2 $0\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:55259.7-55259.20" + attribute \src "libresoc.v:54941.7-54941.20" wire $0\initial[0:0] - attribute \src "libresoc.v:56287.3-56302.6" + attribute \src "libresoc.v:55969.3-55984.6" wire width 3 $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56303.3-56318.6" + attribute \src "libresoc.v:55985.3-56000.6" wire width 3 $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56239.3-56254.6" + attribute \src "libresoc.v:55921.3-55936.6" wire width 14 $1\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56271.3-56286.6" + attribute \src "libresoc.v:55953.3-55968.6" wire width 4 $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56255.3-56270.6" + attribute \src "libresoc.v:55937.3-55952.6" wire width 7 $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56335.3-56350.6" + attribute \src "libresoc.v:56017.3-56032.6" wire $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56351.3-56366.6" + attribute \src "libresoc.v:56033.3-56048.6" wire $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:56319.3-56334.6" + attribute \src "libresoc.v:56001.3-56016.6" wire width 2 $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:56227.17-56227.211" - wire width 32 $ternary$libresoc.v:56227$3481_Y + attribute \src "libresoc.v:55909.17-55909.211" + wire width 32 $ternary$libresoc.v:55909$3465_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -97372,7 +96891,7 @@ module \dec$141 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:55259.7-55259.15" + attribute \src "libresoc.v:54941.7-54941.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -97381,15 +96900,15 @@ module \dec$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:56227$3481 + cell $mux $ternary$libresoc.v:55909$3465 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:56227$3481_Y + connect \Y $ternary$libresoc.v:55909$3465_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:56228.16-56238.4" + attribute \src "libresoc.v:55910.16-55920.4" cell \BRANCH_dec19 \BRANCH_dec19 connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out @@ -97401,22 +96920,22 @@ module \dec$141 connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel connect \opcode_in \BRANCH_dec19_opcode_in end - attribute \src "libresoc.v:55259.7-55259.20" - process $proc$libresoc.v:55259$3490 + attribute \src "libresoc.v:54941.7-54941.20" + process $proc$libresoc.v:54941$3474 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:56239.3-56254.6" - process $proc$libresoc.v:56239$3482 + attribute \src "libresoc.v:55921.3-55936.6" + process $proc$libresoc.v:55921$3466 assign { } { } assign { } { } assign $0\BRANCH_function_unit[13:0] $1\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56240.5-56240.29" + attribute \src "libresoc.v:55922.5-55922.29" switch \initial - attribute \src "libresoc.v:56240.9-56240.17" + attribute \src "libresoc.v:55922.9-55922.17" case 1'1 case end @@ -97440,14 +96959,14 @@ module \dec$141 sync always update \BRANCH_function_unit $0\BRANCH_function_unit[13:0] end - attribute \src "libresoc.v:56255.3-56270.6" - process $proc$libresoc.v:56255$3483 + attribute \src "libresoc.v:55937.3-55952.6" + process $proc$libresoc.v:55937$3467 assign { } { } assign { } { } assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56256.5-56256.29" + attribute \src "libresoc.v:55938.5-55938.29" switch \initial - attribute \src "libresoc.v:56256.9-56256.17" + attribute \src "libresoc.v:55938.9-55938.17" case 1'1 case end @@ -97471,14 +96990,14 @@ module \dec$141 sync always update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] end - attribute \src "libresoc.v:56271.3-56286.6" - process $proc$libresoc.v:56271$3484 + attribute \src "libresoc.v:55953.3-55968.6" + process $proc$libresoc.v:55953$3468 assign { } { } assign { } { } assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56272.5-56272.29" + attribute \src "libresoc.v:55954.5-55954.29" switch \initial - attribute \src "libresoc.v:56272.9-56272.17" + attribute \src "libresoc.v:55954.9-55954.17" case 1'1 case end @@ -97502,14 +97021,14 @@ module \dec$141 sync always update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] end - attribute \src "libresoc.v:56287.3-56302.6" - process $proc$libresoc.v:56287$3485 + attribute \src "libresoc.v:55969.3-55984.6" + process $proc$libresoc.v:55969$3469 assign { } { } assign { } { } assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56288.5-56288.29" + attribute \src "libresoc.v:55970.5-55970.29" switch \initial - attribute \src "libresoc.v:56288.9-56288.17" + attribute \src "libresoc.v:55970.9-55970.17" case 1'1 case end @@ -97533,14 +97052,14 @@ module \dec$141 sync always update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] end - attribute \src "libresoc.v:56303.3-56318.6" - process $proc$libresoc.v:56303$3486 + attribute \src "libresoc.v:55985.3-56000.6" + process $proc$libresoc.v:55985$3470 assign { } { } assign { } { } assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56304.5-56304.29" + attribute \src "libresoc.v:55986.5-55986.29" switch \initial - attribute \src "libresoc.v:56304.9-56304.17" + attribute \src "libresoc.v:55986.9-55986.17" case 1'1 case end @@ -97564,14 +97083,14 @@ module \dec$141 sync always update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] end - attribute \src "libresoc.v:56319.3-56334.6" - process $proc$libresoc.v:56319$3487 + attribute \src "libresoc.v:56001.3-56016.6" + process $proc$libresoc.v:56001$3471 assign { } { } assign { } { } assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:56320.5-56320.29" + attribute \src "libresoc.v:56002.5-56002.29" switch \initial - attribute \src "libresoc.v:56320.9-56320.17" + attribute \src "libresoc.v:56002.9-56002.17" case 1'1 case end @@ -97595,14 +97114,14 @@ module \dec$141 sync always update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] end - attribute \src "libresoc.v:56335.3-56350.6" - process $proc$libresoc.v:56335$3488 + attribute \src "libresoc.v:56017.3-56032.6" + process $proc$libresoc.v:56017$3472 assign { } { } assign { } { } assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56336.5-56336.29" + attribute \src "libresoc.v:56018.5-56018.29" switch \initial - attribute \src "libresoc.v:56336.9-56336.17" + attribute \src "libresoc.v:56018.9-56018.17" case 1'1 case end @@ -97626,14 +97145,14 @@ module \dec$141 sync always update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] end - attribute \src "libresoc.v:56351.3-56366.6" - process $proc$libresoc.v:56351$3489 + attribute \src "libresoc.v:56033.3-56048.6" + process $proc$libresoc.v:56033$3473 assign { } { } assign { } { } assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:56352.5-56352.29" + attribute \src "libresoc.v:56034.5-56034.29" switch \initial - attribute \src "libresoc.v:56352.9-56352.17" + attribute \src "libresoc.v:56034.9-56034.17" case 1'1 case end @@ -97657,7 +97176,7 @@ module \dec$141 sync always update \BRANCH_lk $0\BRANCH_lk[0:0] end - connect \$1 $ternary$libresoc.v:56227$3481_Y + connect \$1 $ternary$libresoc.v:55909$3465_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -97995,71 +97514,71 @@ module \dec$141 connect \BRANCH_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:56707.1-58484.10" +attribute \src "libresoc.v:56389.1-58166.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec" attribute \generator "nMigen" module \dec$145 - attribute \src "libresoc.v:58036.3-58063.6" + attribute \src "libresoc.v:57718.3-57745.6" wire width 3 $0\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:58064.3-58091.6" + attribute \src "libresoc.v:57746.3-57773.6" wire width 3 $0\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57756.3-57783.6" + attribute \src "libresoc.v:57438.3-57465.6" wire width 2 $0\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57840.3-57867.6" + attribute \src "libresoc.v:57522.3-57549.6" wire $0\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57924.3-57951.6" + attribute \src "libresoc.v:57606.3-57633.6" wire width 14 $0\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57980.3-58007.6" + attribute \src "libresoc.v:57662.3-57689.6" wire width 3 $0\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:58008.3-58035.6" + attribute \src "libresoc.v:57690.3-57717.6" wire width 4 $0\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57952.3-57979.6" + attribute \src "libresoc.v:57634.3-57661.6" wire width 7 $0\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57784.3-57811.6" + attribute \src "libresoc.v:57466.3-57493.6" wire $0\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57812.3-57839.6" + attribute \src "libresoc.v:57494.3-57521.6" wire $0\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57868.3-57895.6" + attribute \src "libresoc.v:57550.3-57577.6" wire $0\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:58092.3-58119.6" + attribute \src "libresoc.v:57774.3-57801.6" wire width 4 $0\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58120.3-58147.6" + attribute \src "libresoc.v:57802.3-57829.6" wire width 2 $0\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57896.3-57923.6" + attribute \src "libresoc.v:57578.3-57605.6" wire $0\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:56708.7-56708.20" + attribute \src "libresoc.v:56390.7-56390.20" wire $0\initial[0:0] - attribute \src "libresoc.v:58036.3-58063.6" + attribute \src "libresoc.v:57718.3-57745.6" wire width 3 $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:58064.3-58091.6" + attribute \src "libresoc.v:57746.3-57773.6" wire width 3 $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57756.3-57783.6" + attribute \src "libresoc.v:57438.3-57465.6" wire width 2 $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57840.3-57867.6" + attribute \src "libresoc.v:57522.3-57549.6" wire $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57924.3-57951.6" + attribute \src "libresoc.v:57606.3-57633.6" wire width 14 $1\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57980.3-58007.6" + attribute \src "libresoc.v:57662.3-57689.6" wire width 3 $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:58008.3-58035.6" + attribute \src "libresoc.v:57690.3-57717.6" wire width 4 $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57952.3-57979.6" + attribute \src "libresoc.v:57634.3-57661.6" wire width 7 $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57784.3-57811.6" + attribute \src "libresoc.v:57466.3-57493.6" wire $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57812.3-57839.6" + attribute \src "libresoc.v:57494.3-57521.6" wire $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57868.3-57895.6" + attribute \src "libresoc.v:57550.3-57577.6" wire $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:58092.3-58119.6" + attribute \src "libresoc.v:57774.3-57801.6" wire width 4 $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58120.3-58147.6" + attribute \src "libresoc.v:57802.3-57829.6" wire width 2 $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57896.3-57923.6" + attribute \src "libresoc.v:57578.3-57605.6" wire $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57738.17-57738.211" - wire width 32 $ternary$libresoc.v:57738$3491_Y + attribute \src "libresoc.v:57420.17-57420.211" + wire width 32 $ternary$libresoc.v:57420$3475_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -99070,7 +98589,7 @@ module \dec$145 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:56708.7-56708.15" + attribute \src "libresoc.v:56390.7-56390.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -99079,15 +98598,15 @@ module \dec$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:57738$3491 + cell $mux $ternary$libresoc.v:57420$3475 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:57738$3491_Y + connect \Y $ternary$libresoc.v:57420$3475_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:57739.17-57755.4" + attribute \src "libresoc.v:57421.17-57437.4" cell \LOGICAL_dec31 \LOGICAL_dec31 connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out @@ -99105,22 +98624,22 @@ module \dec$145 connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn connect \opcode_in \LOGICAL_dec31_opcode_in end - attribute \src "libresoc.v:56708.7-56708.20" - process $proc$libresoc.v:56708$3506 + attribute \src "libresoc.v:56390.7-56390.20" + process $proc$libresoc.v:56390$3490 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:57756.3-57783.6" - process $proc$libresoc.v:57756$3492 + attribute \src "libresoc.v:57438.3-57465.6" + process $proc$libresoc.v:57438$3476 assign { } { } assign { } { } assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57757.5-57757.29" + attribute \src "libresoc.v:57439.5-57439.29" switch \initial - attribute \src "libresoc.v:57757.9-57757.17" + attribute \src "libresoc.v:57439.9-57439.17" case 1'1 case end @@ -99160,14 +98679,14 @@ module \dec$145 sync always update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] end - attribute \src "libresoc.v:57784.3-57811.6" - process $proc$libresoc.v:57784$3493 + attribute \src "libresoc.v:57466.3-57493.6" + process $proc$libresoc.v:57466$3477 assign { } { } assign { } { } assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57785.5-57785.29" + attribute \src "libresoc.v:57467.5-57467.29" switch \initial - attribute \src "libresoc.v:57785.9-57785.17" + attribute \src "libresoc.v:57467.9-57467.17" case 1'1 case end @@ -99207,14 +98726,14 @@ module \dec$145 sync always update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] end - attribute \src "libresoc.v:57812.3-57839.6" - process $proc$libresoc.v:57812$3494 + attribute \src "libresoc.v:57494.3-57521.6" + process $proc$libresoc.v:57494$3478 assign { } { } assign { } { } assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57813.5-57813.29" + attribute \src "libresoc.v:57495.5-57495.29" switch \initial - attribute \src "libresoc.v:57813.9-57813.17" + attribute \src "libresoc.v:57495.9-57495.17" case 1'1 case end @@ -99254,14 +98773,14 @@ module \dec$145 sync always update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] end - attribute \src "libresoc.v:57840.3-57867.6" - process $proc$libresoc.v:57840$3495 + attribute \src "libresoc.v:57522.3-57549.6" + process $proc$libresoc.v:57522$3479 assign { } { } assign { } { } assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57841.5-57841.29" + attribute \src "libresoc.v:57523.5-57523.29" switch \initial - attribute \src "libresoc.v:57841.9-57841.17" + attribute \src "libresoc.v:57523.9-57523.17" case 1'1 case end @@ -99301,14 +98820,14 @@ module \dec$145 sync always update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] end - attribute \src "libresoc.v:57868.3-57895.6" - process $proc$libresoc.v:57868$3496 + attribute \src "libresoc.v:57550.3-57577.6" + process $proc$libresoc.v:57550$3480 assign { } { } assign { } { } assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57869.5-57869.29" + attribute \src "libresoc.v:57551.5-57551.29" switch \initial - attribute \src "libresoc.v:57869.9-57869.17" + attribute \src "libresoc.v:57551.9-57551.17" case 1'1 case end @@ -99348,14 +98867,14 @@ module \dec$145 sync always update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] end - attribute \src "libresoc.v:57896.3-57923.6" - process $proc$libresoc.v:57896$3497 + attribute \src "libresoc.v:57578.3-57605.6" + process $proc$libresoc.v:57578$3481 assign { } { } assign { } { } assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57897.5-57897.29" + attribute \src "libresoc.v:57579.5-57579.29" switch \initial - attribute \src "libresoc.v:57897.9-57897.17" + attribute \src "libresoc.v:57579.9-57579.17" case 1'1 case end @@ -99395,14 +98914,14 @@ module \dec$145 sync always update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] end - attribute \src "libresoc.v:57924.3-57951.6" - process $proc$libresoc.v:57924$3498 + attribute \src "libresoc.v:57606.3-57633.6" + process $proc$libresoc.v:57606$3482 assign { } { } assign { } { } assign $0\LOGICAL_function_unit[13:0] $1\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57925.5-57925.29" + attribute \src "libresoc.v:57607.5-57607.29" switch \initial - attribute \src "libresoc.v:57925.9-57925.17" + attribute \src "libresoc.v:57607.9-57607.17" case 1'1 case end @@ -99442,14 +98961,14 @@ module \dec$145 sync always update \LOGICAL_function_unit $0\LOGICAL_function_unit[13:0] end - attribute \src "libresoc.v:57952.3-57979.6" - process $proc$libresoc.v:57952$3499 + attribute \src "libresoc.v:57634.3-57661.6" + process $proc$libresoc.v:57634$3483 assign { } { } assign { } { } assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57953.5-57953.29" + attribute \src "libresoc.v:57635.5-57635.29" switch \initial - attribute \src "libresoc.v:57953.9-57953.17" + attribute \src "libresoc.v:57635.9-57635.17" case 1'1 case end @@ -99489,14 +99008,14 @@ module \dec$145 sync always update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] end - attribute \src "libresoc.v:57980.3-58007.6" - process $proc$libresoc.v:57980$3500 + attribute \src "libresoc.v:57662.3-57689.6" + process $proc$libresoc.v:57662$3484 assign { } { } assign { } { } assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57981.5-57981.29" + attribute \src "libresoc.v:57663.5-57663.29" switch \initial - attribute \src "libresoc.v:57981.9-57981.17" + attribute \src "libresoc.v:57663.9-57663.17" case 1'1 case end @@ -99536,14 +99055,14 @@ module \dec$145 sync always update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] end - attribute \src "libresoc.v:58008.3-58035.6" - process $proc$libresoc.v:58008$3501 + attribute \src "libresoc.v:57690.3-57717.6" + process $proc$libresoc.v:57690$3485 assign { } { } assign { } { } assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:58009.5-58009.29" + attribute \src "libresoc.v:57691.5-57691.29" switch \initial - attribute \src "libresoc.v:58009.9-58009.17" + attribute \src "libresoc.v:57691.9-57691.17" case 1'1 case end @@ -99583,14 +99102,14 @@ module \dec$145 sync always update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] end - attribute \src "libresoc.v:58036.3-58063.6" - process $proc$libresoc.v:58036$3502 + attribute \src "libresoc.v:57718.3-57745.6" + process $proc$libresoc.v:57718$3486 assign { } { } assign { } { } assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:58037.5-58037.29" + attribute \src "libresoc.v:57719.5-57719.29" switch \initial - attribute \src "libresoc.v:58037.9-58037.17" + attribute \src "libresoc.v:57719.9-57719.17" case 1'1 case end @@ -99630,14 +99149,14 @@ module \dec$145 sync always update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] end - attribute \src "libresoc.v:58064.3-58091.6" - process $proc$libresoc.v:58064$3503 + attribute \src "libresoc.v:57746.3-57773.6" + process $proc$libresoc.v:57746$3487 assign { } { } assign { } { } assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:58065.5-58065.29" + attribute \src "libresoc.v:57747.5-57747.29" switch \initial - attribute \src "libresoc.v:58065.9-58065.17" + attribute \src "libresoc.v:57747.9-57747.17" case 1'1 case end @@ -99677,14 +99196,14 @@ module \dec$145 sync always update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] end - attribute \src "libresoc.v:58092.3-58119.6" - process $proc$libresoc.v:58092$3504 + attribute \src "libresoc.v:57774.3-57801.6" + process $proc$libresoc.v:57774$3488 assign { } { } assign { } { } assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58093.5-58093.29" + attribute \src "libresoc.v:57775.5-57775.29" switch \initial - attribute \src "libresoc.v:58093.9-58093.17" + attribute \src "libresoc.v:57775.9-57775.17" case 1'1 case end @@ -99724,14 +99243,14 @@ module \dec$145 sync always update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] end - attribute \src "libresoc.v:58120.3-58147.6" - process $proc$libresoc.v:58120$3505 + attribute \src "libresoc.v:57802.3-57829.6" + process $proc$libresoc.v:57802$3489 assign { } { } assign { } { } assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:58121.5-58121.29" + attribute \src "libresoc.v:57803.5-57803.29" switch \initial - attribute \src "libresoc.v:58121.9-58121.17" + attribute \src "libresoc.v:57803.9-57803.17" case 1'1 case end @@ -99771,7 +99290,7 @@ module \dec$145 sync always update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:57738$3491_Y + connect \$1 $ternary$libresoc.v:57420$3475_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -100109,39 +99628,39 @@ module \dec$145 connect \LOGICAL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:58488.1-59823.10" +attribute \src "libresoc.v:58170.1-59505.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec" attribute \generator "nMigen" module \dec$150 - attribute \src "libresoc.v:59447.3-59456.6" + attribute \src "libresoc.v:59129.3-59138.6" wire width 3 $0\SPR_cr_in[2:0] - attribute \src "libresoc.v:59457.3-59466.6" + attribute \src "libresoc.v:59139.3-59148.6" wire width 3 $0\SPR_cr_out[2:0] - attribute \src "libresoc.v:59427.3-59436.6" + attribute \src "libresoc.v:59109.3-59118.6" wire width 14 $0\SPR_function_unit[13:0] - attribute \src "libresoc.v:59437.3-59446.6" + attribute \src "libresoc.v:59119.3-59128.6" wire width 7 $0\SPR_internal_op[6:0] - attribute \src "libresoc.v:59477.3-59486.6" + attribute \src "libresoc.v:59159.3-59168.6" wire $0\SPR_is_32b[0:0] - attribute \src "libresoc.v:59467.3-59476.6" + attribute \src "libresoc.v:59149.3-59158.6" wire width 2 $0\SPR_rc_sel[1:0] - attribute \src "libresoc.v:58489.7-58489.20" + attribute \src "libresoc.v:58171.7-58171.20" wire $0\initial[0:0] - attribute \src "libresoc.v:59447.3-59456.6" + attribute \src "libresoc.v:59129.3-59138.6" wire width 3 $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:59457.3-59466.6" + attribute \src "libresoc.v:59139.3-59148.6" wire width 3 $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:59427.3-59436.6" + attribute \src "libresoc.v:59109.3-59118.6" wire width 14 $1\SPR_function_unit[13:0] - attribute \src "libresoc.v:59437.3-59446.6" + attribute \src "libresoc.v:59119.3-59128.6" wire width 7 $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:59477.3-59486.6" + attribute \src "libresoc.v:59159.3-59168.6" wire $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:59467.3-59476.6" + attribute \src "libresoc.v:59149.3-59158.6" wire width 2 $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:59417.17-59417.211" - wire width 32 $ternary$libresoc.v:59417$3507_Y + attribute \src "libresoc.v:59099.17-59099.211" + wire width 32 $ternary$libresoc.v:59099$3491_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -101058,7 +100577,7 @@ module \dec$150 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:58489.7-58489.15" + attribute \src "libresoc.v:58171.7-58171.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -101067,15 +100586,15 @@ module \dec$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 11 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:59417$3507 + cell $mux $ternary$libresoc.v:59099$3491 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:59417$3507_Y + connect \Y $ternary$libresoc.v:59099$3491_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:59418.13-59426.4" + attribute \src "libresoc.v:59100.13-59108.4" cell \SPR_dec31 \SPR_dec31 connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out @@ -101085,22 +100604,22 @@ module \dec$150 connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel connect \opcode_in \SPR_dec31_opcode_in end - attribute \src "libresoc.v:58489.7-58489.20" - process $proc$libresoc.v:58489$3514 + attribute \src "libresoc.v:58171.7-58171.20" + process $proc$libresoc.v:58171$3498 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:59427.3-59436.6" - process $proc$libresoc.v:59427$3508 + attribute \src "libresoc.v:59109.3-59118.6" + process $proc$libresoc.v:59109$3492 assign { } { } assign { } { } assign $0\SPR_function_unit[13:0] $1\SPR_function_unit[13:0] - attribute \src "libresoc.v:59428.5-59428.29" + attribute \src "libresoc.v:59110.5-59110.29" switch \initial - attribute \src "libresoc.v:59428.9-59428.17" + attribute \src "libresoc.v:59110.9-59110.17" case 1'1 case end @@ -101116,14 +100635,14 @@ module \dec$150 sync always update \SPR_function_unit $0\SPR_function_unit[13:0] end - attribute \src "libresoc.v:59437.3-59446.6" - process $proc$libresoc.v:59437$3509 + attribute \src "libresoc.v:59119.3-59128.6" + process $proc$libresoc.v:59119$3493 assign { } { } assign { } { } assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:59438.5-59438.29" + attribute \src "libresoc.v:59120.5-59120.29" switch \initial - attribute \src "libresoc.v:59438.9-59438.17" + attribute \src "libresoc.v:59120.9-59120.17" case 1'1 case end @@ -101139,14 +100658,14 @@ module \dec$150 sync always update \SPR_internal_op $0\SPR_internal_op[6:0] end - attribute \src "libresoc.v:59447.3-59456.6" - process $proc$libresoc.v:59447$3510 + attribute \src "libresoc.v:59129.3-59138.6" + process $proc$libresoc.v:59129$3494 assign { } { } assign { } { } assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:59448.5-59448.29" + attribute \src "libresoc.v:59130.5-59130.29" switch \initial - attribute \src "libresoc.v:59448.9-59448.17" + attribute \src "libresoc.v:59130.9-59130.17" case 1'1 case end @@ -101162,14 +100681,14 @@ module \dec$150 sync always update \SPR_cr_in $0\SPR_cr_in[2:0] end - attribute \src "libresoc.v:59457.3-59466.6" - process $proc$libresoc.v:59457$3511 + attribute \src "libresoc.v:59139.3-59148.6" + process $proc$libresoc.v:59139$3495 assign { } { } assign { } { } assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:59458.5-59458.29" + attribute \src "libresoc.v:59140.5-59140.29" switch \initial - attribute \src "libresoc.v:59458.9-59458.17" + attribute \src "libresoc.v:59140.9-59140.17" case 1'1 case end @@ -101185,14 +100704,14 @@ module \dec$150 sync always update \SPR_cr_out $0\SPR_cr_out[2:0] end - attribute \src "libresoc.v:59467.3-59476.6" - process $proc$libresoc.v:59467$3512 + attribute \src "libresoc.v:59149.3-59158.6" + process $proc$libresoc.v:59149$3496 assign { } { } assign { } { } assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:59468.5-59468.29" + attribute \src "libresoc.v:59150.5-59150.29" switch \initial - attribute \src "libresoc.v:59468.9-59468.17" + attribute \src "libresoc.v:59150.9-59150.17" case 1'1 case end @@ -101208,14 +100727,14 @@ module \dec$150 sync always update \SPR_rc_sel $0\SPR_rc_sel[1:0] end - attribute \src "libresoc.v:59477.3-59486.6" - process $proc$libresoc.v:59477$3513 + attribute \src "libresoc.v:59159.3-59168.6" + process $proc$libresoc.v:59159$3497 assign { } { } assign { } { } assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:59478.5-59478.29" + attribute \src "libresoc.v:59160.5-59160.29" switch \initial - attribute \src "libresoc.v:59478.9-59478.17" + attribute \src "libresoc.v:59160.9-59160.17" case 1'1 case end @@ -101231,7 +100750,7 @@ module \dec$150 sync always update \SPR_is_32b $0\SPR_is_32b[0:0] end - connect \$1 $ternary$libresoc.v:59417$3507_Y + connect \$1 $ternary$libresoc.v:59099$3491_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -101569,71 +101088,71 @@ module \dec$150 connect \SPR_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:59827.1-61352.10" +attribute \src "libresoc.v:59509.1-61034.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec" attribute \generator "nMigen" module \dec$153 - attribute \src "libresoc.v:60976.3-60985.6" + attribute \src "libresoc.v:60658.3-60667.6" wire width 3 $0\DIV_cr_in[2:0] - attribute \src "libresoc.v:60986.3-60995.6" + attribute \src "libresoc.v:60668.3-60677.6" wire width 3 $0\DIV_cr_out[2:0] - attribute \src "libresoc.v:60876.3-60885.6" + attribute \src "libresoc.v:60558.3-60567.6" wire width 2 $0\DIV_cry_in[1:0] - attribute \src "libresoc.v:60906.3-60915.6" + attribute \src "libresoc.v:60588.3-60597.6" wire $0\DIV_cry_out[0:0] - attribute \src "libresoc.v:60936.3-60945.6" + attribute \src "libresoc.v:60618.3-60627.6" wire width 14 $0\DIV_function_unit[13:0] - attribute \src "libresoc.v:60956.3-60965.6" + attribute \src "libresoc.v:60638.3-60647.6" wire width 3 $0\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60966.3-60975.6" + attribute \src "libresoc.v:60648.3-60657.6" wire width 4 $0\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60946.3-60955.6" + attribute \src "libresoc.v:60628.3-60637.6" wire width 7 $0\DIV_internal_op[6:0] - attribute \src "libresoc.v:60886.3-60895.6" + attribute \src "libresoc.v:60568.3-60577.6" wire $0\DIV_inv_a[0:0] - attribute \src "libresoc.v:60896.3-60905.6" + attribute \src "libresoc.v:60578.3-60587.6" wire $0\DIV_inv_out[0:0] - attribute \src "libresoc.v:60916.3-60925.6" + attribute \src "libresoc.v:60598.3-60607.6" wire $0\DIV_is_32b[0:0] - attribute \src "libresoc.v:60996.3-61005.6" + attribute \src "libresoc.v:60678.3-60687.6" wire width 4 $0\DIV_ldst_len[3:0] - attribute \src "libresoc.v:61006.3-61015.6" + attribute \src "libresoc.v:60688.3-60697.6" wire width 2 $0\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60926.3-60935.6" + attribute \src "libresoc.v:60608.3-60617.6" wire $0\DIV_sgn[0:0] - attribute \src "libresoc.v:59828.7-59828.20" + attribute \src "libresoc.v:59510.7-59510.20" wire $0\initial[0:0] - attribute \src "libresoc.v:60976.3-60985.6" + attribute \src "libresoc.v:60658.3-60667.6" wire width 3 $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60986.3-60995.6" + attribute \src "libresoc.v:60668.3-60677.6" wire width 3 $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60876.3-60885.6" + attribute \src "libresoc.v:60558.3-60567.6" wire width 2 $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60906.3-60915.6" + attribute \src "libresoc.v:60588.3-60597.6" wire $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60936.3-60945.6" + attribute \src "libresoc.v:60618.3-60627.6" wire width 14 $1\DIV_function_unit[13:0] - attribute \src "libresoc.v:60956.3-60965.6" + attribute \src "libresoc.v:60638.3-60647.6" wire width 3 $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60966.3-60975.6" + attribute \src "libresoc.v:60648.3-60657.6" wire width 4 $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60946.3-60955.6" + attribute \src "libresoc.v:60628.3-60637.6" wire width 7 $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60886.3-60895.6" + attribute \src "libresoc.v:60568.3-60577.6" wire $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60896.3-60905.6" + attribute \src "libresoc.v:60578.3-60587.6" wire $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60916.3-60925.6" + attribute \src "libresoc.v:60598.3-60607.6" wire $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60996.3-61005.6" + attribute \src "libresoc.v:60678.3-60687.6" wire width 4 $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:61006.3-61015.6" + attribute \src "libresoc.v:60688.3-60697.6" wire width 2 $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60926.3-60935.6" + attribute \src "libresoc.v:60608.3-60617.6" wire $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60858.17-60858.211" - wire width 32 $ternary$libresoc.v:60858$3515_Y + attribute \src "libresoc.v:60540.17-60540.211" + wire width 32 $ternary$libresoc.v:60540$3499_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -102644,7 +102163,7 @@ module \dec$153 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:59828.7-59828.15" + attribute \src "libresoc.v:59510.7-59510.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -102653,15 +102172,15 @@ module \dec$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:60858$3515 + cell $mux $ternary$libresoc.v:60540$3499 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:60858$3515_Y + connect \Y $ternary$libresoc.v:60540$3499_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:60859.13-60875.4" + attribute \src "libresoc.v:60541.13-60557.4" cell \DIV_dec31 \DIV_dec31 connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out @@ -102679,22 +102198,22 @@ module \dec$153 connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn connect \opcode_in \DIV_dec31_opcode_in end - attribute \src "libresoc.v:59828.7-59828.20" - process $proc$libresoc.v:59828$3530 + attribute \src "libresoc.v:59510.7-59510.20" + process $proc$libresoc.v:59510$3514 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:60876.3-60885.6" - process $proc$libresoc.v:60876$3516 + attribute \src "libresoc.v:60558.3-60567.6" + process $proc$libresoc.v:60558$3500 assign { } { } assign { } { } assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60877.5-60877.29" + attribute \src "libresoc.v:60559.5-60559.29" switch \initial - attribute \src "libresoc.v:60877.9-60877.17" + attribute \src "libresoc.v:60559.9-60559.17" case 1'1 case end @@ -102710,14 +102229,14 @@ module \dec$153 sync always update \DIV_cry_in $0\DIV_cry_in[1:0] end - attribute \src "libresoc.v:60886.3-60895.6" - process $proc$libresoc.v:60886$3517 + attribute \src "libresoc.v:60568.3-60577.6" + process $proc$libresoc.v:60568$3501 assign { } { } assign { } { } assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60887.5-60887.29" + attribute \src "libresoc.v:60569.5-60569.29" switch \initial - attribute \src "libresoc.v:60887.9-60887.17" + attribute \src "libresoc.v:60569.9-60569.17" case 1'1 case end @@ -102733,14 +102252,14 @@ module \dec$153 sync always update \DIV_inv_a $0\DIV_inv_a[0:0] end - attribute \src "libresoc.v:60896.3-60905.6" - process $proc$libresoc.v:60896$3518 + attribute \src "libresoc.v:60578.3-60587.6" + process $proc$libresoc.v:60578$3502 assign { } { } assign { } { } assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60897.5-60897.29" + attribute \src "libresoc.v:60579.5-60579.29" switch \initial - attribute \src "libresoc.v:60897.9-60897.17" + attribute \src "libresoc.v:60579.9-60579.17" case 1'1 case end @@ -102756,14 +102275,14 @@ module \dec$153 sync always update \DIV_inv_out $0\DIV_inv_out[0:0] end - attribute \src "libresoc.v:60906.3-60915.6" - process $proc$libresoc.v:60906$3519 + attribute \src "libresoc.v:60588.3-60597.6" + process $proc$libresoc.v:60588$3503 assign { } { } assign { } { } assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60907.5-60907.29" + attribute \src "libresoc.v:60589.5-60589.29" switch \initial - attribute \src "libresoc.v:60907.9-60907.17" + attribute \src "libresoc.v:60589.9-60589.17" case 1'1 case end @@ -102779,14 +102298,14 @@ module \dec$153 sync always update \DIV_cry_out $0\DIV_cry_out[0:0] end - attribute \src "libresoc.v:60916.3-60925.6" - process $proc$libresoc.v:60916$3520 + attribute \src "libresoc.v:60598.3-60607.6" + process $proc$libresoc.v:60598$3504 assign { } { } assign { } { } assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60917.5-60917.29" + attribute \src "libresoc.v:60599.5-60599.29" switch \initial - attribute \src "libresoc.v:60917.9-60917.17" + attribute \src "libresoc.v:60599.9-60599.17" case 1'1 case end @@ -102802,14 +102321,14 @@ module \dec$153 sync always update \DIV_is_32b $0\DIV_is_32b[0:0] end - attribute \src "libresoc.v:60926.3-60935.6" - process $proc$libresoc.v:60926$3521 + attribute \src "libresoc.v:60608.3-60617.6" + process $proc$libresoc.v:60608$3505 assign { } { } assign { } { } assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60927.5-60927.29" + attribute \src "libresoc.v:60609.5-60609.29" switch \initial - attribute \src "libresoc.v:60927.9-60927.17" + attribute \src "libresoc.v:60609.9-60609.17" case 1'1 case end @@ -102825,14 +102344,14 @@ module \dec$153 sync always update \DIV_sgn $0\DIV_sgn[0:0] end - attribute \src "libresoc.v:60936.3-60945.6" - process $proc$libresoc.v:60936$3522 + attribute \src "libresoc.v:60618.3-60627.6" + process $proc$libresoc.v:60618$3506 assign { } { } assign { } { } assign $0\DIV_function_unit[13:0] $1\DIV_function_unit[13:0] - attribute \src "libresoc.v:60937.5-60937.29" + attribute \src "libresoc.v:60619.5-60619.29" switch \initial - attribute \src "libresoc.v:60937.9-60937.17" + attribute \src "libresoc.v:60619.9-60619.17" case 1'1 case end @@ -102848,14 +102367,14 @@ module \dec$153 sync always update \DIV_function_unit $0\DIV_function_unit[13:0] end - attribute \src "libresoc.v:60946.3-60955.6" - process $proc$libresoc.v:60946$3523 + attribute \src "libresoc.v:60628.3-60637.6" + process $proc$libresoc.v:60628$3507 assign { } { } assign { } { } assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60947.5-60947.29" + attribute \src "libresoc.v:60629.5-60629.29" switch \initial - attribute \src "libresoc.v:60947.9-60947.17" + attribute \src "libresoc.v:60629.9-60629.17" case 1'1 case end @@ -102871,14 +102390,14 @@ module \dec$153 sync always update \DIV_internal_op $0\DIV_internal_op[6:0] end - attribute \src "libresoc.v:60956.3-60965.6" - process $proc$libresoc.v:60956$3524 + attribute \src "libresoc.v:60638.3-60647.6" + process $proc$libresoc.v:60638$3508 assign { } { } assign { } { } assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60957.5-60957.29" + attribute \src "libresoc.v:60639.5-60639.29" switch \initial - attribute \src "libresoc.v:60957.9-60957.17" + attribute \src "libresoc.v:60639.9-60639.17" case 1'1 case end @@ -102894,14 +102413,14 @@ module \dec$153 sync always update \DIV_in1_sel $0\DIV_in1_sel[2:0] end - attribute \src "libresoc.v:60966.3-60975.6" - process $proc$libresoc.v:60966$3525 + attribute \src "libresoc.v:60648.3-60657.6" + process $proc$libresoc.v:60648$3509 assign { } { } assign { } { } assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60967.5-60967.29" + attribute \src "libresoc.v:60649.5-60649.29" switch \initial - attribute \src "libresoc.v:60967.9-60967.17" + attribute \src "libresoc.v:60649.9-60649.17" case 1'1 case end @@ -102917,14 +102436,14 @@ module \dec$153 sync always update \DIV_in2_sel $0\DIV_in2_sel[3:0] end - attribute \src "libresoc.v:60976.3-60985.6" - process $proc$libresoc.v:60976$3526 + attribute \src "libresoc.v:60658.3-60667.6" + process $proc$libresoc.v:60658$3510 assign { } { } assign { } { } assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60977.5-60977.29" + attribute \src "libresoc.v:60659.5-60659.29" switch \initial - attribute \src "libresoc.v:60977.9-60977.17" + attribute \src "libresoc.v:60659.9-60659.17" case 1'1 case end @@ -102940,14 +102459,14 @@ module \dec$153 sync always update \DIV_cr_in $0\DIV_cr_in[2:0] end - attribute \src "libresoc.v:60986.3-60995.6" - process $proc$libresoc.v:60986$3527 + attribute \src "libresoc.v:60668.3-60677.6" + process $proc$libresoc.v:60668$3511 assign { } { } assign { } { } assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60987.5-60987.29" + attribute \src "libresoc.v:60669.5-60669.29" switch \initial - attribute \src "libresoc.v:60987.9-60987.17" + attribute \src "libresoc.v:60669.9-60669.17" case 1'1 case end @@ -102963,14 +102482,14 @@ module \dec$153 sync always update \DIV_cr_out $0\DIV_cr_out[2:0] end - attribute \src "libresoc.v:60996.3-61005.6" - process $proc$libresoc.v:60996$3528 + attribute \src "libresoc.v:60678.3-60687.6" + process $proc$libresoc.v:60678$3512 assign { } { } assign { } { } assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60997.5-60997.29" + attribute \src "libresoc.v:60679.5-60679.29" switch \initial - attribute \src "libresoc.v:60997.9-60997.17" + attribute \src "libresoc.v:60679.9-60679.17" case 1'1 case end @@ -102986,14 +102505,14 @@ module \dec$153 sync always update \DIV_ldst_len $0\DIV_ldst_len[3:0] end - attribute \src "libresoc.v:61006.3-61015.6" - process $proc$libresoc.v:61006$3529 + attribute \src "libresoc.v:60688.3-60697.6" + process $proc$libresoc.v:60688$3513 assign { } { } assign { } { } assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:61007.5-61007.29" + attribute \src "libresoc.v:60689.5-60689.29" switch \initial - attribute \src "libresoc.v:61007.9-61007.17" + attribute \src "libresoc.v:60689.9-60689.17" case 1'1 case end @@ -103009,7 +102528,7 @@ module \dec$153 sync always update \DIV_rc_sel $0\DIV_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:60858$3515_Y + connect \$1 $ternary$libresoc.v:60540$3499_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -103347,47 +102866,47 @@ module \dec$153 connect \DIV_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:61356.1-62777.10" +attribute \src "libresoc.v:61038.1-62459.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec" attribute \generator "nMigen" module \dec$158 - attribute \src "libresoc.v:62376.3-62388.6" + attribute \src "libresoc.v:62058.3-62070.6" wire width 3 $0\MUL_cr_in[2:0] - attribute \src "libresoc.v:62389.3-62401.6" + attribute \src "libresoc.v:62071.3-62083.6" wire width 3 $0\MUL_cr_out[2:0] - attribute \src "libresoc.v:62337.3-62349.6" + attribute \src "libresoc.v:62019.3-62031.6" wire width 14 $0\MUL_function_unit[13:0] - attribute \src "libresoc.v:62363.3-62375.6" + attribute \src "libresoc.v:62045.3-62057.6" wire width 4 $0\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62350.3-62362.6" + attribute \src "libresoc.v:62032.3-62044.6" wire width 7 $0\MUL_internal_op[6:0] - attribute \src "libresoc.v:62415.3-62427.6" + attribute \src "libresoc.v:62097.3-62109.6" wire $0\MUL_is_32b[0:0] - attribute \src "libresoc.v:62402.3-62414.6" + attribute \src "libresoc.v:62084.3-62096.6" wire width 2 $0\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62428.3-62440.6" + attribute \src "libresoc.v:62110.3-62122.6" wire $0\MUL_sgn[0:0] - attribute \src "libresoc.v:61357.7-61357.20" + attribute \src "libresoc.v:61039.7-61039.20" wire $0\initial[0:0] - attribute \src "libresoc.v:62376.3-62388.6" + attribute \src "libresoc.v:62058.3-62070.6" wire width 3 $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:62389.3-62401.6" + attribute \src "libresoc.v:62071.3-62083.6" wire width 3 $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:62337.3-62349.6" + attribute \src "libresoc.v:62019.3-62031.6" wire width 14 $1\MUL_function_unit[13:0] - attribute \src "libresoc.v:62363.3-62375.6" + attribute \src "libresoc.v:62045.3-62057.6" wire width 4 $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62350.3-62362.6" + attribute \src "libresoc.v:62032.3-62044.6" wire width 7 $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:62415.3-62427.6" + attribute \src "libresoc.v:62097.3-62109.6" wire $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:62402.3-62414.6" + attribute \src "libresoc.v:62084.3-62096.6" wire width 2 $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62428.3-62440.6" + attribute \src "libresoc.v:62110.3-62122.6" wire $1\MUL_sgn[0:0] - attribute \src "libresoc.v:62325.17-62325.211" - wire width 32 $ternary$libresoc.v:62325$3531_Y + attribute \src "libresoc.v:62007.17-62007.211" + wire width 32 $ternary$libresoc.v:62007$3515_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -104342,7 +103861,7 @@ module \dec$158 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:61357.7-61357.15" + attribute \src "libresoc.v:61039.7-61039.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -104351,15 +103870,15 @@ module \dec$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 20 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:62325$3531 + cell $mux $ternary$libresoc.v:62007$3515 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:62325$3531_Y + connect \Y $ternary$libresoc.v:62007$3515_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:62326.13-62336.4" + attribute \src "libresoc.v:62008.13-62018.4" cell \MUL_dec31 \MUL_dec31 connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out @@ -104371,22 +103890,22 @@ module \dec$158 connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn connect \opcode_in \MUL_dec31_opcode_in end - attribute \src "libresoc.v:61357.7-61357.20" - process $proc$libresoc.v:61357$3540 + attribute \src "libresoc.v:61039.7-61039.20" + process $proc$libresoc.v:61039$3524 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:62337.3-62349.6" - process $proc$libresoc.v:62337$3532 + attribute \src "libresoc.v:62019.3-62031.6" + process $proc$libresoc.v:62019$3516 assign { } { } assign { } { } assign $0\MUL_function_unit[13:0] $1\MUL_function_unit[13:0] - attribute \src "libresoc.v:62338.5-62338.29" + attribute \src "libresoc.v:62020.5-62020.29" switch \initial - attribute \src "libresoc.v:62338.9-62338.17" + attribute \src "libresoc.v:62020.9-62020.17" case 1'1 case end @@ -104406,14 +103925,14 @@ module \dec$158 sync always update \MUL_function_unit $0\MUL_function_unit[13:0] end - attribute \src "libresoc.v:62350.3-62362.6" - process $proc$libresoc.v:62350$3533 + attribute \src "libresoc.v:62032.3-62044.6" + process $proc$libresoc.v:62032$3517 assign { } { } assign { } { } assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:62351.5-62351.29" + attribute \src "libresoc.v:62033.5-62033.29" switch \initial - attribute \src "libresoc.v:62351.9-62351.17" + attribute \src "libresoc.v:62033.9-62033.17" case 1'1 case end @@ -104433,14 +103952,14 @@ module \dec$158 sync always update \MUL_internal_op $0\MUL_internal_op[6:0] end - attribute \src "libresoc.v:62363.3-62375.6" - process $proc$libresoc.v:62363$3534 + attribute \src "libresoc.v:62045.3-62057.6" + process $proc$libresoc.v:62045$3518 assign { } { } assign { } { } assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62364.5-62364.29" + attribute \src "libresoc.v:62046.5-62046.29" switch \initial - attribute \src "libresoc.v:62364.9-62364.17" + attribute \src "libresoc.v:62046.9-62046.17" case 1'1 case end @@ -104460,14 +103979,14 @@ module \dec$158 sync always update \MUL_in2_sel $0\MUL_in2_sel[3:0] end - attribute \src "libresoc.v:62376.3-62388.6" - process $proc$libresoc.v:62376$3535 + attribute \src "libresoc.v:62058.3-62070.6" + process $proc$libresoc.v:62058$3519 assign { } { } assign { } { } assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:62377.5-62377.29" + attribute \src "libresoc.v:62059.5-62059.29" switch \initial - attribute \src "libresoc.v:62377.9-62377.17" + attribute \src "libresoc.v:62059.9-62059.17" case 1'1 case end @@ -104487,14 +104006,14 @@ module \dec$158 sync always update \MUL_cr_in $0\MUL_cr_in[2:0] end - attribute \src "libresoc.v:62389.3-62401.6" - process $proc$libresoc.v:62389$3536 + attribute \src "libresoc.v:62071.3-62083.6" + process $proc$libresoc.v:62071$3520 assign { } { } assign { } { } assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:62390.5-62390.29" + attribute \src "libresoc.v:62072.5-62072.29" switch \initial - attribute \src "libresoc.v:62390.9-62390.17" + attribute \src "libresoc.v:62072.9-62072.17" case 1'1 case end @@ -104514,14 +104033,14 @@ module \dec$158 sync always update \MUL_cr_out $0\MUL_cr_out[2:0] end - attribute \src "libresoc.v:62402.3-62414.6" - process $proc$libresoc.v:62402$3537 + attribute \src "libresoc.v:62084.3-62096.6" + process $proc$libresoc.v:62084$3521 assign { } { } assign { } { } assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62403.5-62403.29" + attribute \src "libresoc.v:62085.5-62085.29" switch \initial - attribute \src "libresoc.v:62403.9-62403.17" + attribute \src "libresoc.v:62085.9-62085.17" case 1'1 case end @@ -104541,14 +104060,14 @@ module \dec$158 sync always update \MUL_rc_sel $0\MUL_rc_sel[1:0] end - attribute \src "libresoc.v:62415.3-62427.6" - process $proc$libresoc.v:62415$3538 + attribute \src "libresoc.v:62097.3-62109.6" + process $proc$libresoc.v:62097$3522 assign { } { } assign { } { } assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:62416.5-62416.29" + attribute \src "libresoc.v:62098.5-62098.29" switch \initial - attribute \src "libresoc.v:62416.9-62416.17" + attribute \src "libresoc.v:62098.9-62098.17" case 1'1 case end @@ -104568,14 +104087,14 @@ module \dec$158 sync always update \MUL_is_32b $0\MUL_is_32b[0:0] end - attribute \src "libresoc.v:62428.3-62440.6" - process $proc$libresoc.v:62428$3539 + attribute \src "libresoc.v:62110.3-62122.6" + process $proc$libresoc.v:62110$3523 assign { } { } assign { } { } assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] - attribute \src "libresoc.v:62429.5-62429.29" + attribute \src "libresoc.v:62111.5-62111.29" switch \initial - attribute \src "libresoc.v:62429.9-62429.17" + attribute \src "libresoc.v:62111.9-62111.17" case 1'1 case end @@ -104595,7 +104114,7 @@ module \dec$158 sync always update \MUL_sgn $0\MUL_sgn[0:0] end - connect \$1 $ternary$libresoc.v:62325$3531_Y + connect \$1 $ternary$libresoc.v:62007$3515_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -104933,59 +104452,59 @@ module \dec$158 connect \MUL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:62781.1-64535.10" +attribute \src "libresoc.v:62463.1-64217.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec" attribute \generator "nMigen" module \dec$162 - attribute \src "libresoc.v:64110.3-64131.6" + attribute \src "libresoc.v:63792.3-63813.6" wire width 3 $0\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64132.3-64153.6" + attribute \src "libresoc.v:63814.3-63835.6" wire width 3 $0\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64176.3-64197.6" + attribute \src "libresoc.v:63858.3-63879.6" wire width 2 $0\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63978.3-63999.6" + attribute \src "libresoc.v:63660.3-63681.6" wire $0\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:64044.3-64065.6" + attribute \src "libresoc.v:63726.3-63747.6" wire width 14 $0\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:64088.3-64109.6" + attribute \src "libresoc.v:63770.3-63791.6" wire width 4 $0\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:64066.3-64087.6" + attribute \src "libresoc.v:63748.3-63769.6" wire width 7 $0\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63956.3-63977.6" + attribute \src "libresoc.v:63638.3-63659.6" wire $0\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:64000.3-64021.6" + attribute \src "libresoc.v:63682.3-63703.6" wire $0\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:64154.3-64175.6" + attribute \src "libresoc.v:63836.3-63857.6" wire width 2 $0\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:64022.3-64043.6" + attribute \src "libresoc.v:63704.3-63725.6" wire $0\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:62782.7-62782.20" + attribute \src "libresoc.v:62464.7-62464.20" wire $0\initial[0:0] - attribute \src "libresoc.v:64110.3-64131.6" + attribute \src "libresoc.v:63792.3-63813.6" wire width 3 $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64132.3-64153.6" + attribute \src "libresoc.v:63814.3-63835.6" wire width 3 $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64176.3-64197.6" + attribute \src "libresoc.v:63858.3-63879.6" wire width 2 $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63978.3-63999.6" + attribute \src "libresoc.v:63660.3-63681.6" wire $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:64044.3-64065.6" + attribute \src "libresoc.v:63726.3-63747.6" wire width 14 $1\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:64088.3-64109.6" + attribute \src "libresoc.v:63770.3-63791.6" wire width 4 $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:64066.3-64087.6" + attribute \src "libresoc.v:63748.3-63769.6" wire width 7 $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63956.3-63977.6" + attribute \src "libresoc.v:63638.3-63659.6" wire $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:64000.3-64021.6" + attribute \src "libresoc.v:63682.3-63703.6" wire $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:64154.3-64175.6" + attribute \src "libresoc.v:63836.3-63857.6" wire width 2 $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:64022.3-64043.6" + attribute \src "libresoc.v:63704.3-63725.6" wire $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63927.17-63927.211" - wire width 32 $ternary$libresoc.v:63927$3541_Y + attribute \src "libresoc.v:63609.17-63609.211" + wire width 32 $ternary$libresoc.v:63609$3525_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -106113,7 +105632,7 @@ module \dec$162 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:62782.7-62782.15" + attribute \src "libresoc.v:62464.7-62464.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -106122,15 +105641,15 @@ module \dec$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 24 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:63927$3541 + cell $mux $ternary$libresoc.v:63609$3525 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:63927$3541_Y + connect \Y $ternary$libresoc.v:63609$3525_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:63928.19-63941.4" + attribute \src "libresoc.v:63610.19-63623.4" cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out @@ -106146,7 +105665,7 @@ module \dec$162 connect \opcode_in \SHIFT_ROT_dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:63942.19-63955.4" + attribute \src "libresoc.v:63624.19-63637.4" cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out @@ -106161,22 +105680,22 @@ module \dec$162 connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn connect \opcode_in \SHIFT_ROT_dec31_opcode_in end - attribute \src "libresoc.v:62782.7-62782.20" - process $proc$libresoc.v:62782$3553 + attribute \src "libresoc.v:62464.7-62464.20" + process $proc$libresoc.v:62464$3537 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:63956.3-63977.6" - process $proc$libresoc.v:63956$3542 + attribute \src "libresoc.v:63638.3-63659.6" + process $proc$libresoc.v:63638$3526 assign { } { } assign { } { } assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63957.5-63957.29" + attribute \src "libresoc.v:63639.5-63639.29" switch \initial - attribute \src "libresoc.v:63957.9-63957.17" + attribute \src "libresoc.v:63639.9-63639.17" case 1'1 case end @@ -106208,14 +105727,14 @@ module \dec$162 sync always update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0] end - attribute \src "libresoc.v:63978.3-63999.6" - process $proc$libresoc.v:63978$3543 + attribute \src "libresoc.v:63660.3-63681.6" + process $proc$libresoc.v:63660$3527 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63979.5-63979.29" + attribute \src "libresoc.v:63661.5-63661.29" switch \initial - attribute \src "libresoc.v:63979.9-63979.17" + attribute \src "libresoc.v:63661.9-63661.17" case 1'1 case end @@ -106247,14 +105766,14 @@ module \dec$162 sync always update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] end - attribute \src "libresoc.v:64000.3-64021.6" - process $proc$libresoc.v:64000$3544 + attribute \src "libresoc.v:63682.3-63703.6" + process $proc$libresoc.v:63682$3528 assign { } { } assign { } { } assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:64001.5-64001.29" + attribute \src "libresoc.v:63683.5-63683.29" switch \initial - attribute \src "libresoc.v:64001.9-64001.17" + attribute \src "libresoc.v:63683.9-63683.17" case 1'1 case end @@ -106286,14 +105805,14 @@ module \dec$162 sync always update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] end - attribute \src "libresoc.v:64022.3-64043.6" - process $proc$libresoc.v:64022$3545 + attribute \src "libresoc.v:63704.3-63725.6" + process $proc$libresoc.v:63704$3529 assign { } { } assign { } { } assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:64023.5-64023.29" + attribute \src "libresoc.v:63705.5-63705.29" switch \initial - attribute \src "libresoc.v:64023.9-64023.17" + attribute \src "libresoc.v:63705.9-63705.17" case 1'1 case end @@ -106325,14 +105844,14 @@ module \dec$162 sync always update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] end - attribute \src "libresoc.v:64044.3-64065.6" - process $proc$libresoc.v:64044$3546 + attribute \src "libresoc.v:63726.3-63747.6" + process $proc$libresoc.v:63726$3530 assign { } { } assign { } { } assign $0\SHIFT_ROT_function_unit[13:0] $1\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:64045.5-64045.29" + attribute \src "libresoc.v:63727.5-63727.29" switch \initial - attribute \src "libresoc.v:64045.9-64045.17" + attribute \src "libresoc.v:63727.9-63727.17" case 1'1 case end @@ -106364,14 +105883,14 @@ module \dec$162 sync always update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[13:0] end - attribute \src "libresoc.v:64066.3-64087.6" - process $proc$libresoc.v:64066$3547 + attribute \src "libresoc.v:63748.3-63769.6" + process $proc$libresoc.v:63748$3531 assign { } { } assign { } { } assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:64067.5-64067.29" + attribute \src "libresoc.v:63749.5-63749.29" switch \initial - attribute \src "libresoc.v:64067.9-64067.17" + attribute \src "libresoc.v:63749.9-63749.17" case 1'1 case end @@ -106403,14 +105922,14 @@ module \dec$162 sync always update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] end - attribute \src "libresoc.v:64088.3-64109.6" - process $proc$libresoc.v:64088$3548 + attribute \src "libresoc.v:63770.3-63791.6" + process $proc$libresoc.v:63770$3532 assign { } { } assign { } { } assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:64089.5-64089.29" + attribute \src "libresoc.v:63771.5-63771.29" switch \initial - attribute \src "libresoc.v:64089.9-64089.17" + attribute \src "libresoc.v:63771.9-63771.17" case 1'1 case end @@ -106442,14 +105961,14 @@ module \dec$162 sync always update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] end - attribute \src "libresoc.v:64110.3-64131.6" - process $proc$libresoc.v:64110$3549 + attribute \src "libresoc.v:63792.3-63813.6" + process $proc$libresoc.v:63792$3533 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64111.5-64111.29" + attribute \src "libresoc.v:63793.5-63793.29" switch \initial - attribute \src "libresoc.v:64111.9-64111.17" + attribute \src "libresoc.v:63793.9-63793.17" case 1'1 case end @@ -106481,14 +106000,14 @@ module \dec$162 sync always update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] end - attribute \src "libresoc.v:64132.3-64153.6" - process $proc$libresoc.v:64132$3550 + attribute \src "libresoc.v:63814.3-63835.6" + process $proc$libresoc.v:63814$3534 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64133.5-64133.29" + attribute \src "libresoc.v:63815.5-63815.29" switch \initial - attribute \src "libresoc.v:64133.9-64133.17" + attribute \src "libresoc.v:63815.9-63815.17" case 1'1 case end @@ -106520,14 +106039,14 @@ module \dec$162 sync always update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] end - attribute \src "libresoc.v:64154.3-64175.6" - process $proc$libresoc.v:64154$3551 + attribute \src "libresoc.v:63836.3-63857.6" + process $proc$libresoc.v:63836$3535 assign { } { } assign { } { } assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:64155.5-64155.29" + attribute \src "libresoc.v:63837.5-63837.29" switch \initial - attribute \src "libresoc.v:64155.9-64155.17" + attribute \src "libresoc.v:63837.9-63837.17" case 1'1 case end @@ -106559,14 +106078,14 @@ module \dec$162 sync always update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] end - attribute \src "libresoc.v:64176.3-64197.6" - process $proc$libresoc.v:64176$3552 + attribute \src "libresoc.v:63858.3-63879.6" + process $proc$libresoc.v:63858$3536 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:64177.5-64177.29" + attribute \src "libresoc.v:63859.5-63859.29" switch \initial - attribute \src "libresoc.v:64177.9-64177.17" + attribute \src "libresoc.v:63859.9-63859.17" case 1'1 case end @@ -106598,7 +106117,7 @@ module \dec$162 sync always update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] end - connect \$1 $ternary$libresoc.v:63927$3541_Y + connect \$1 $ternary$libresoc.v:63609$3525_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -106937,67 +106456,67 @@ module \dec$162 connect \SHIFT_ROT_dec30_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:64539.1-67048.10" +attribute \src "libresoc.v:64221.1-66730.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec" attribute \generator "nMigen" module \dec$166 - attribute \src "libresoc.v:66130.3-66187.6" + attribute \src "libresoc.v:65812.3-65869.6" wire $0\LDST_br[0:0] - attribute \src "libresoc.v:66594.3-66651.6" + attribute \src "libresoc.v:66276.3-66333.6" wire width 3 $0\LDST_cr_in[2:0] - attribute \src "libresoc.v:66652.3-66709.6" + attribute \src "libresoc.v:66334.3-66391.6" wire width 3 $0\LDST_cr_out[2:0] - attribute \src "libresoc.v:66362.3-66419.6" + attribute \src "libresoc.v:66044.3-66101.6" wire width 14 $0\LDST_function_unit[13:0] - attribute \src "libresoc.v:66478.3-66535.6" + attribute \src "libresoc.v:66160.3-66217.6" wire width 3 $0\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66536.3-66593.6" + attribute \src "libresoc.v:66218.3-66275.6" wire width 4 $0\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66420.3-66477.6" + attribute \src "libresoc.v:66102.3-66159.6" wire width 7 $0\LDST_internal_op[6:0] - attribute \src "libresoc.v:66246.3-66303.6" + attribute \src "libresoc.v:65928.3-65985.6" wire $0\LDST_is_32b[0:0] - attribute \src "libresoc.v:65956.3-66013.6" + attribute \src "libresoc.v:65638.3-65695.6" wire width 4 $0\LDST_ldst_len[3:0] - attribute \src "libresoc.v:66072.3-66129.6" + attribute \src "libresoc.v:65754.3-65811.6" wire width 2 $0\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66304.3-66361.6" + attribute \src "libresoc.v:65986.3-66043.6" wire $0\LDST_sgn[0:0] - attribute \src "libresoc.v:66188.3-66245.6" + attribute \src "libresoc.v:65870.3-65927.6" wire $0\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:66014.3-66071.6" + attribute \src "libresoc.v:65696.3-65753.6" wire width 2 $0\LDST_upd[1:0] - attribute \src "libresoc.v:64540.7-64540.20" + attribute \src "libresoc.v:64222.7-64222.20" wire $0\initial[0:0] - attribute \src "libresoc.v:66130.3-66187.6" + attribute \src "libresoc.v:65812.3-65869.6" wire $1\LDST_br[0:0] - attribute \src "libresoc.v:66594.3-66651.6" + attribute \src "libresoc.v:66276.3-66333.6" wire width 3 $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:66652.3-66709.6" + attribute \src "libresoc.v:66334.3-66391.6" wire width 3 $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:66362.3-66419.6" + attribute \src "libresoc.v:66044.3-66101.6" wire width 14 $1\LDST_function_unit[13:0] - attribute \src "libresoc.v:66478.3-66535.6" + attribute \src "libresoc.v:66160.3-66217.6" wire width 3 $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66536.3-66593.6" + attribute \src "libresoc.v:66218.3-66275.6" wire width 4 $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66420.3-66477.6" + attribute \src "libresoc.v:66102.3-66159.6" wire width 7 $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:66246.3-66303.6" + attribute \src "libresoc.v:65928.3-65985.6" wire $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:65956.3-66013.6" + attribute \src "libresoc.v:65638.3-65695.6" wire width 4 $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:66072.3-66129.6" + attribute \src "libresoc.v:65754.3-65811.6" wire width 2 $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66304.3-66361.6" + attribute \src "libresoc.v:65986.3-66043.6" wire $1\LDST_sgn[0:0] - attribute \src "libresoc.v:66188.3-66245.6" + attribute \src "libresoc.v:65870.3-65927.6" wire $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:66014.3-66071.6" + attribute \src "libresoc.v:65696.3-65753.6" wire width 2 $1\LDST_upd[1:0] - attribute \src "libresoc.v:65907.17-65907.211" - wire width 32 $ternary$libresoc.v:65907$3554_Y + attribute \src "libresoc.v:65589.17-65589.211" + wire width 32 $ternary$libresoc.v:65589$3538_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -108346,7 +107865,7 @@ module \dec$166 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:64540.7-64540.15" + attribute \src "libresoc.v:64222.7-64222.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -108355,15 +107874,15 @@ module \dec$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 26 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:65907$3554 + cell $mux $ternary$libresoc.v:65589$3538 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:65907$3554_Y + connect \Y $ternary$libresoc.v:65589$3538_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:65908.14-65923.4" + attribute \src "libresoc.v:65590.14-65605.4" cell \LDST_dec31 \LDST_dec31 connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in @@ -108381,7 +107900,7 @@ module \dec$166 connect \opcode_in \LDST_dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:65924.14-65939.4" + attribute \src "libresoc.v:65606.14-65621.4" cell \LDST_dec58 \LDST_dec58 connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in @@ -108399,7 +107918,7 @@ module \dec$166 connect \opcode_in \LDST_dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:65940.14-65955.4" + attribute \src "libresoc.v:65622.14-65637.4" cell \LDST_dec62 \LDST_dec62 connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in @@ -108416,22 +107935,22 @@ module \dec$166 connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd connect \opcode_in \LDST_dec62_opcode_in end - attribute \src "libresoc.v:64540.7-64540.20" - process $proc$libresoc.v:64540$3568 + attribute \src "libresoc.v:64222.7-64222.20" + process $proc$libresoc.v:64222$3552 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:65956.3-66013.6" - process $proc$libresoc.v:65956$3555 + attribute \src "libresoc.v:65638.3-65695.6" + process $proc$libresoc.v:65638$3539 assign { } { } assign { } { } assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65957.5-65957.29" + attribute \src "libresoc.v:65639.5-65639.29" switch \initial - attribute \src "libresoc.v:65957.9-65957.17" + attribute \src "libresoc.v:65639.9-65639.17" case 1'1 case end @@ -108511,14 +108030,14 @@ module \dec$166 sync always update \LDST_ldst_len $0\LDST_ldst_len[3:0] end - attribute \src "libresoc.v:66014.3-66071.6" - process $proc$libresoc.v:66014$3556 + attribute \src "libresoc.v:65696.3-65753.6" + process $proc$libresoc.v:65696$3540 assign { } { } assign { } { } assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] - attribute \src "libresoc.v:66015.5-66015.29" + attribute \src "libresoc.v:65697.5-65697.29" switch \initial - attribute \src "libresoc.v:66015.9-66015.17" + attribute \src "libresoc.v:65697.9-65697.17" case 1'1 case end @@ -108598,14 +108117,14 @@ module \dec$166 sync always update \LDST_upd $0\LDST_upd[1:0] end - attribute \src "libresoc.v:66072.3-66129.6" - process $proc$libresoc.v:66072$3557 + attribute \src "libresoc.v:65754.3-65811.6" + process $proc$libresoc.v:65754$3541 assign { } { } assign { } { } assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66073.5-66073.29" + attribute \src "libresoc.v:65755.5-65755.29" switch \initial - attribute \src "libresoc.v:66073.9-66073.17" + attribute \src "libresoc.v:65755.9-65755.17" case 1'1 case end @@ -108685,14 +108204,14 @@ module \dec$166 sync always update \LDST_rc_sel $0\LDST_rc_sel[1:0] end - attribute \src "libresoc.v:66130.3-66187.6" - process $proc$libresoc.v:66130$3558 + attribute \src "libresoc.v:65812.3-65869.6" + process $proc$libresoc.v:65812$3542 assign { } { } assign { } { } assign $0\LDST_br[0:0] $1\LDST_br[0:0] - attribute \src "libresoc.v:66131.5-66131.29" + attribute \src "libresoc.v:65813.5-65813.29" switch \initial - attribute \src "libresoc.v:66131.9-66131.17" + attribute \src "libresoc.v:65813.9-65813.17" case 1'1 case end @@ -108772,14 +108291,14 @@ module \dec$166 sync always update \LDST_br $0\LDST_br[0:0] end - attribute \src "libresoc.v:66188.3-66245.6" - process $proc$libresoc.v:66188$3559 + attribute \src "libresoc.v:65870.3-65927.6" + process $proc$libresoc.v:65870$3543 assign { } { } assign { } { } assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:66189.5-66189.29" + attribute \src "libresoc.v:65871.5-65871.29" switch \initial - attribute \src "libresoc.v:66189.9-66189.17" + attribute \src "libresoc.v:65871.9-65871.17" case 1'1 case end @@ -108859,14 +108378,14 @@ module \dec$166 sync always update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] end - attribute \src "libresoc.v:66246.3-66303.6" - process $proc$libresoc.v:66246$3560 + attribute \src "libresoc.v:65928.3-65985.6" + process $proc$libresoc.v:65928$3544 assign { } { } assign { } { } assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:66247.5-66247.29" + attribute \src "libresoc.v:65929.5-65929.29" switch \initial - attribute \src "libresoc.v:66247.9-66247.17" + attribute \src "libresoc.v:65929.9-65929.17" case 1'1 case end @@ -108946,14 +108465,14 @@ module \dec$166 sync always update \LDST_is_32b $0\LDST_is_32b[0:0] end - attribute \src "libresoc.v:66304.3-66361.6" - process $proc$libresoc.v:66304$3561 + attribute \src "libresoc.v:65986.3-66043.6" + process $proc$libresoc.v:65986$3545 assign { } { } assign { } { } assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] - attribute \src "libresoc.v:66305.5-66305.29" + attribute \src "libresoc.v:65987.5-65987.29" switch \initial - attribute \src "libresoc.v:66305.9-66305.17" + attribute \src "libresoc.v:65987.9-65987.17" case 1'1 case end @@ -109033,14 +108552,14 @@ module \dec$166 sync always update \LDST_sgn $0\LDST_sgn[0:0] end - attribute \src "libresoc.v:66362.3-66419.6" - process $proc$libresoc.v:66362$3562 + attribute \src "libresoc.v:66044.3-66101.6" + process $proc$libresoc.v:66044$3546 assign { } { } assign { } { } assign $0\LDST_function_unit[13:0] $1\LDST_function_unit[13:0] - attribute \src "libresoc.v:66363.5-66363.29" + attribute \src "libresoc.v:66045.5-66045.29" switch \initial - attribute \src "libresoc.v:66363.9-66363.17" + attribute \src "libresoc.v:66045.9-66045.17" case 1'1 case end @@ -109120,14 +108639,14 @@ module \dec$166 sync always update \LDST_function_unit $0\LDST_function_unit[13:0] end - attribute \src "libresoc.v:66420.3-66477.6" - process $proc$libresoc.v:66420$3563 + attribute \src "libresoc.v:66102.3-66159.6" + process $proc$libresoc.v:66102$3547 assign { } { } assign { } { } assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:66421.5-66421.29" + attribute \src "libresoc.v:66103.5-66103.29" switch \initial - attribute \src "libresoc.v:66421.9-66421.17" + attribute \src "libresoc.v:66103.9-66103.17" case 1'1 case end @@ -109207,14 +108726,14 @@ module \dec$166 sync always update \LDST_internal_op $0\LDST_internal_op[6:0] end - attribute \src "libresoc.v:66478.3-66535.6" - process $proc$libresoc.v:66478$3564 + attribute \src "libresoc.v:66160.3-66217.6" + process $proc$libresoc.v:66160$3548 assign { } { } assign { } { } assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66479.5-66479.29" + attribute \src "libresoc.v:66161.5-66161.29" switch \initial - attribute \src "libresoc.v:66479.9-66479.17" + attribute \src "libresoc.v:66161.9-66161.17" case 1'1 case end @@ -109294,14 +108813,14 @@ module \dec$166 sync always update \LDST_in1_sel $0\LDST_in1_sel[2:0] end - attribute \src "libresoc.v:66536.3-66593.6" - process $proc$libresoc.v:66536$3565 + attribute \src "libresoc.v:66218.3-66275.6" + process $proc$libresoc.v:66218$3549 assign { } { } assign { } { } assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66537.5-66537.29" + attribute \src "libresoc.v:66219.5-66219.29" switch \initial - attribute \src "libresoc.v:66537.9-66537.17" + attribute \src "libresoc.v:66219.9-66219.17" case 1'1 case end @@ -109381,14 +108900,14 @@ module \dec$166 sync always update \LDST_in2_sel $0\LDST_in2_sel[3:0] end - attribute \src "libresoc.v:66594.3-66651.6" - process $proc$libresoc.v:66594$3566 + attribute \src "libresoc.v:66276.3-66333.6" + process $proc$libresoc.v:66276$3550 assign { } { } assign { } { } assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:66595.5-66595.29" + attribute \src "libresoc.v:66277.5-66277.29" switch \initial - attribute \src "libresoc.v:66595.9-66595.17" + attribute \src "libresoc.v:66277.9-66277.17" case 1'1 case end @@ -109468,14 +108987,14 @@ module \dec$166 sync always update \LDST_cr_in $0\LDST_cr_in[2:0] end - attribute \src "libresoc.v:66652.3-66709.6" - process $proc$libresoc.v:66652$3567 + attribute \src "libresoc.v:66334.3-66391.6" + process $proc$libresoc.v:66334$3551 assign { } { } assign { } { } assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:66653.5-66653.29" + attribute \src "libresoc.v:66335.5-66335.29" switch \initial - attribute \src "libresoc.v:66653.9-66653.17" + attribute \src "libresoc.v:66335.9-66335.17" case 1'1 case end @@ -109555,7 +109074,7 @@ module \dec$166 sync always update \LDST_cr_out $0\LDST_cr_out[2:0] end - connect \$1 $ternary$libresoc.v:65907$3554_Y + connect \$1 $ternary$libresoc.v:65589$3538_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -109895,213 +109414,213 @@ module \dec$166 connect \LDST_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:67052.1-75269.10" +attribute \src "libresoc.v:66734.1-74954.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" attribute \generator "nMigen" module \dec$171 - attribute \src "libresoc.v:70432.3-70576.6" + attribute \src "libresoc.v:70117.3-70261.6" wire width 2 $0\SV_Etype[1:0] - attribute \src "libresoc.v:70577.3-70721.6" + attribute \src "libresoc.v:70262.3-70406.6" wire width 2 $0\SV_Ptype[1:0] - attribute \src "libresoc.v:70290.3-70431.6" + attribute \src "libresoc.v:69972.3-70116.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:73622.3-73766.6" + attribute \src "libresoc.v:73307.3-73451.6" wire $0\br[0:0] - attribute \src "libresoc.v:71302.3-71446.6" + attribute \src "libresoc.v:70987.3-71131.6" wire width 3 $0\cr_in[2:0] - attribute \src "libresoc.v:71447.3-71591.6" + attribute \src "libresoc.v:71132.3-71276.6" wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:73042.3-73186.6" + attribute \src "libresoc.v:72727.3-72871.6" wire width 2 $0\cry_in[1:0] - attribute \src "libresoc.v:73477.3-73621.6" + attribute \src "libresoc.v:73162.3-73306.6" wire $0\cry_out[0:0] - attribute \src "libresoc.v:70145.3-70289.6" + attribute \src "libresoc.v:69827.3-69971.6" wire width 5 $0\form[4:0] - attribute \src "libresoc.v:74637.3-74781.6" + attribute \src "libresoc.v:74322.3-74466.6" wire width 14 $0\function_unit[13:0] - attribute \src "libresoc.v:70722.3-70866.6" + attribute \src "libresoc.v:70407.3-70551.6" wire width 3 $0\in1_sel[2:0] - attribute \src "libresoc.v:70867.3-71011.6" + attribute \src "libresoc.v:70552.3-70696.6" wire width 4 $0\in2_sel[3:0] - attribute \src "libresoc.v:71012.3-71156.6" + attribute \src "libresoc.v:70697.3-70841.6" wire width 2 $0\in3_sel[1:0] - attribute \src "libresoc.v:67053.7-67053.20" + attribute \src "libresoc.v:66735.7-66735.20" wire $0\initial[0:0] - attribute \src "libresoc.v:74782.3-74926.6" + attribute \src "libresoc.v:74467.3-74611.6" wire width 7 $0\internal_op[6:0] - attribute \src "libresoc.v:73187.3-73331.6" + attribute \src "libresoc.v:72872.3-73016.6" wire $0\inv_a[0:0] - attribute \src "libresoc.v:73332.3-73476.6" + attribute \src "libresoc.v:73017.3-73161.6" wire $0\inv_out[0:0] - attribute \src "libresoc.v:74057.3-74201.6" + attribute \src "libresoc.v:73742.3-73886.6" wire $0\is_32b[0:0] - attribute \src "libresoc.v:72607.3-72751.6" + attribute \src "libresoc.v:72292.3-72436.6" wire width 4 $0\ldst_len[3:0] - attribute \src "libresoc.v:74347.3-74491.6" + attribute \src "libresoc.v:74032.3-74176.6" wire $0\lk[0:0] - attribute \src "libresoc.v:71157.3-71301.6" + attribute \src "libresoc.v:70842.3-70986.6" wire width 3 $0\out_sel[2:0] - attribute \src "libresoc.v:72897.3-73041.6" + attribute \src "libresoc.v:72582.3-72726.6" wire width 2 $0\rc_sel[1:0] - attribute \src "libresoc.v:73912.3-74056.6" + attribute \src "libresoc.v:73597.3-73741.6" wire $0\rsrv[0:0] - attribute \src "libresoc.v:74492.3-74636.6" + attribute \src "libresoc.v:74177.3-74321.6" wire $0\sgl_pipe[0:0] - attribute \src "libresoc.v:74202.3-74346.6" + attribute \src "libresoc.v:73887.3-74031.6" wire $0\sgn[0:0] - attribute \src "libresoc.v:73767.3-73911.6" + attribute \src "libresoc.v:73452.3-73596.6" wire $0\sgn_ext[0:0] - attribute \src "libresoc.v:72317.3-72461.6" + attribute \src "libresoc.v:72002.3-72146.6" wire width 3 $0\sv_cr_in[2:0] - attribute \src "libresoc.v:72462.3-72606.6" + attribute \src "libresoc.v:72147.3-72291.6" wire width 3 $0\sv_cr_out[2:0] - attribute \src "libresoc.v:71592.3-71736.6" + attribute \src "libresoc.v:71277.3-71421.6" wire width 3 $0\sv_in1[2:0] - attribute \src "libresoc.v:71737.3-71881.6" + attribute \src "libresoc.v:71422.3-71566.6" wire width 3 $0\sv_in2[2:0] - attribute \src "libresoc.v:71882.3-72026.6" + attribute \src "libresoc.v:71567.3-71711.6" wire width 3 $0\sv_in3[2:0] - attribute \src "libresoc.v:72172.3-72316.6" + attribute \src "libresoc.v:71857.3-72001.6" wire width 3 $0\sv_out2[2:0] - attribute \src "libresoc.v:72027.3-72171.6" + attribute \src "libresoc.v:71712.3-71856.6" wire width 3 $0\sv_out[2:0] - attribute \src "libresoc.v:72752.3-72896.6" + attribute \src "libresoc.v:72437.3-72581.6" wire width 2 $0\upd[1:0] - attribute \src "libresoc.v:70432.3-70576.6" + attribute \src "libresoc.v:70117.3-70261.6" wire width 2 $1\SV_Etype[1:0] - attribute \src "libresoc.v:70577.3-70721.6" + attribute \src "libresoc.v:70262.3-70406.6" wire width 2 $1\SV_Ptype[1:0] - attribute \src "libresoc.v:70290.3-70431.6" + attribute \src "libresoc.v:69972.3-70116.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:73622.3-73766.6" + attribute \src "libresoc.v:73307.3-73451.6" wire $1\br[0:0] - attribute \src "libresoc.v:71302.3-71446.6" + attribute \src "libresoc.v:70987.3-71131.6" wire width 3 $1\cr_in[2:0] - attribute \src "libresoc.v:71447.3-71591.6" + attribute \src "libresoc.v:71132.3-71276.6" wire width 3 $1\cr_out[2:0] - attribute \src "libresoc.v:73042.3-73186.6" + attribute \src "libresoc.v:72727.3-72871.6" wire width 2 $1\cry_in[1:0] - attribute \src "libresoc.v:73477.3-73621.6" + attribute \src "libresoc.v:73162.3-73306.6" wire $1\cry_out[0:0] - attribute \src "libresoc.v:70145.3-70289.6" + attribute \src "libresoc.v:69827.3-69971.6" wire width 5 $1\form[4:0] - attribute \src "libresoc.v:74637.3-74781.6" + attribute \src "libresoc.v:74322.3-74466.6" wire width 14 $1\function_unit[13:0] - attribute \src "libresoc.v:70722.3-70866.6" + attribute \src "libresoc.v:70407.3-70551.6" wire width 3 $1\in1_sel[2:0] - attribute \src "libresoc.v:70867.3-71011.6" + attribute \src "libresoc.v:70552.3-70696.6" wire width 4 $1\in2_sel[3:0] - attribute \src "libresoc.v:71012.3-71156.6" + attribute \src "libresoc.v:70697.3-70841.6" wire width 2 $1\in3_sel[1:0] - attribute \src "libresoc.v:74782.3-74926.6" + attribute \src "libresoc.v:74467.3-74611.6" wire width 7 $1\internal_op[6:0] - attribute \src "libresoc.v:73187.3-73331.6" + attribute \src "libresoc.v:72872.3-73016.6" wire $1\inv_a[0:0] - attribute \src "libresoc.v:73332.3-73476.6" + attribute \src "libresoc.v:73017.3-73161.6" wire $1\inv_out[0:0] - attribute \src "libresoc.v:74057.3-74201.6" + attribute \src "libresoc.v:73742.3-73886.6" wire $1\is_32b[0:0] - attribute \src "libresoc.v:72607.3-72751.6" + attribute \src "libresoc.v:72292.3-72436.6" wire width 4 $1\ldst_len[3:0] - attribute \src "libresoc.v:74347.3-74491.6" + attribute \src "libresoc.v:74032.3-74176.6" wire $1\lk[0:0] - attribute \src "libresoc.v:71157.3-71301.6" + attribute \src "libresoc.v:70842.3-70986.6" wire width 3 $1\out_sel[2:0] - attribute \src "libresoc.v:72897.3-73041.6" + attribute \src "libresoc.v:72582.3-72726.6" wire width 2 $1\rc_sel[1:0] - attribute \src "libresoc.v:73912.3-74056.6" + attribute \src "libresoc.v:73597.3-73741.6" wire $1\rsrv[0:0] - attribute \src "libresoc.v:74492.3-74636.6" + attribute \src "libresoc.v:74177.3-74321.6" wire $1\sgl_pipe[0:0] - attribute \src "libresoc.v:74202.3-74346.6" + attribute \src "libresoc.v:73887.3-74031.6" wire $1\sgn[0:0] - attribute \src "libresoc.v:73767.3-73911.6" + attribute \src "libresoc.v:73452.3-73596.6" wire $1\sgn_ext[0:0] - attribute \src "libresoc.v:72317.3-72461.6" + attribute \src "libresoc.v:72002.3-72146.6" wire width 3 $1\sv_cr_in[2:0] - attribute \src "libresoc.v:72462.3-72606.6" + attribute \src "libresoc.v:72147.3-72291.6" wire width 3 $1\sv_cr_out[2:0] - attribute \src "libresoc.v:71592.3-71736.6" + attribute \src "libresoc.v:71277.3-71421.6" wire width 3 $1\sv_in1[2:0] - attribute \src "libresoc.v:71737.3-71881.6" + attribute \src "libresoc.v:71422.3-71566.6" wire width 3 $1\sv_in2[2:0] - attribute \src "libresoc.v:71882.3-72026.6" + attribute \src "libresoc.v:71567.3-71711.6" wire width 3 $1\sv_in3[2:0] - attribute \src "libresoc.v:72172.3-72316.6" + attribute \src "libresoc.v:71857.3-72001.6" wire width 3 $1\sv_out2[2:0] - attribute \src "libresoc.v:72027.3-72171.6" + attribute \src "libresoc.v:71712.3-71856.6" wire width 3 $1\sv_out[2:0] - attribute \src "libresoc.v:72752.3-72896.6" + attribute \src "libresoc.v:72437.3-72581.6" wire width 2 $1\upd[1:0] - attribute \src "libresoc.v:70432.3-70576.6" + attribute \src "libresoc.v:70117.3-70261.6" wire width 2 $2\SV_Etype[1:0] - attribute \src "libresoc.v:70577.3-70721.6" + attribute \src "libresoc.v:70262.3-70406.6" wire width 2 $2\SV_Ptype[1:0] - attribute \src "libresoc.v:70290.3-70431.6" + attribute \src "libresoc.v:69972.3-70116.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:73622.3-73766.6" + attribute \src "libresoc.v:73307.3-73451.6" wire $2\br[0:0] - attribute \src "libresoc.v:71302.3-71446.6" + attribute \src "libresoc.v:70987.3-71131.6" wire width 3 $2\cr_in[2:0] - attribute \src "libresoc.v:71447.3-71591.6" + attribute \src "libresoc.v:71132.3-71276.6" wire width 3 $2\cr_out[2:0] - attribute \src "libresoc.v:73042.3-73186.6" + attribute \src "libresoc.v:72727.3-72871.6" wire width 2 $2\cry_in[1:0] - attribute \src "libresoc.v:73477.3-73621.6" + attribute \src "libresoc.v:73162.3-73306.6" wire $2\cry_out[0:0] - attribute \src "libresoc.v:70145.3-70289.6" + attribute \src "libresoc.v:69827.3-69971.6" wire width 5 $2\form[4:0] - attribute \src "libresoc.v:74637.3-74781.6" + attribute \src "libresoc.v:74322.3-74466.6" wire width 14 $2\function_unit[13:0] - attribute \src "libresoc.v:70722.3-70866.6" + attribute \src "libresoc.v:70407.3-70551.6" wire width 3 $2\in1_sel[2:0] - attribute \src "libresoc.v:70867.3-71011.6" + attribute \src "libresoc.v:70552.3-70696.6" wire width 4 $2\in2_sel[3:0] - attribute \src "libresoc.v:71012.3-71156.6" + attribute \src "libresoc.v:70697.3-70841.6" wire width 2 $2\in3_sel[1:0] - attribute \src "libresoc.v:74782.3-74926.6" + attribute \src "libresoc.v:74467.3-74611.6" wire width 7 $2\internal_op[6:0] - attribute \src "libresoc.v:73187.3-73331.6" + attribute \src "libresoc.v:72872.3-73016.6" wire $2\inv_a[0:0] - attribute \src "libresoc.v:73332.3-73476.6" + attribute \src "libresoc.v:73017.3-73161.6" wire $2\inv_out[0:0] - attribute \src "libresoc.v:74057.3-74201.6" + attribute \src "libresoc.v:73742.3-73886.6" wire $2\is_32b[0:0] - attribute \src "libresoc.v:72607.3-72751.6" + attribute \src "libresoc.v:72292.3-72436.6" wire width 4 $2\ldst_len[3:0] - attribute \src "libresoc.v:74347.3-74491.6" + attribute \src "libresoc.v:74032.3-74176.6" wire $2\lk[0:0] - attribute \src "libresoc.v:71157.3-71301.6" + attribute \src "libresoc.v:70842.3-70986.6" wire width 3 $2\out_sel[2:0] - attribute \src "libresoc.v:72897.3-73041.6" + attribute \src "libresoc.v:72582.3-72726.6" wire width 2 $2\rc_sel[1:0] - attribute \src "libresoc.v:73912.3-74056.6" + attribute \src "libresoc.v:73597.3-73741.6" wire $2\rsrv[0:0] - attribute \src "libresoc.v:74492.3-74636.6" + attribute \src "libresoc.v:74177.3-74321.6" wire $2\sgl_pipe[0:0] - attribute \src "libresoc.v:74202.3-74346.6" + attribute \src "libresoc.v:73887.3-74031.6" wire $2\sgn[0:0] - attribute \src "libresoc.v:73767.3-73911.6" + attribute \src "libresoc.v:73452.3-73596.6" wire $2\sgn_ext[0:0] - attribute \src "libresoc.v:72317.3-72461.6" + attribute \src "libresoc.v:72002.3-72146.6" wire width 3 $2\sv_cr_in[2:0] - attribute \src "libresoc.v:72462.3-72606.6" + attribute \src "libresoc.v:72147.3-72291.6" wire width 3 $2\sv_cr_out[2:0] - attribute \src "libresoc.v:71592.3-71736.6" + attribute \src "libresoc.v:71277.3-71421.6" wire width 3 $2\sv_in1[2:0] - attribute \src "libresoc.v:71737.3-71881.6" + attribute \src "libresoc.v:71422.3-71566.6" wire width 3 $2\sv_in2[2:0] - attribute \src "libresoc.v:71882.3-72026.6" + attribute \src "libresoc.v:71567.3-71711.6" wire width 3 $2\sv_in3[2:0] - attribute \src "libresoc.v:72172.3-72316.6" + attribute \src "libresoc.v:71857.3-72001.6" wire width 3 $2\sv_out2[2:0] - attribute \src "libresoc.v:72027.3-72171.6" + attribute \src "libresoc.v:71712.3-71856.6" wire width 3 $2\sv_out[2:0] - attribute \src "libresoc.v:72752.3-72896.6" + attribute \src "libresoc.v:72437.3-72581.6" wire width 2 $2\upd[1:0] - attribute \src "libresoc.v:69928.17-69928.211" - wire width 32 $ternary$libresoc.v:69928$3569_Y + attribute \src "libresoc.v:69610.17-69610.211" + wire width 32 $ternary$libresoc.v:69610$3553_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -112767,7 +112286,7 @@ module \dec$171 attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 15 \in3_sel - attribute \src "libresoc.v:67053.7-67053.15" + attribute \src "libresoc.v:66735.7-66735.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -112965,15 +112484,15 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 18 \upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:69928$3569 + cell $mux $ternary$libresoc.v:69610$3553 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:69928$3569_Y + connect \Y $ternary$libresoc.v:69610$3553_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:69929.9-69964.4" + attribute \src "libresoc.v:69611.9-69646.4" cell \dec19 \dec19 connect \dec19_SV_Etype \dec19_dec19_SV_Etype connect \dec19_SV_Ptype \dec19_dec19_SV_Ptype @@ -113011,7 +112530,7 @@ module \dec$171 connect \opcode_in \dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69965.9-70000.4" + attribute \src "libresoc.v:69647.9-69682.4" cell \dec22 \dec22 connect \dec22_SV_Etype \dec22_dec22_SV_Etype connect \dec22_SV_Ptype \dec22_dec22_SV_Ptype @@ -113049,7 +112568,7 @@ module \dec$171 connect \opcode_in \dec22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:70001.9-70036.4" + attribute \src "libresoc.v:69683.9-69718.4" cell \dec30 \dec30 connect \dec30_SV_Etype \dec30_dec30_SV_Etype connect \dec30_SV_Ptype \dec30_dec30_SV_Ptype @@ -113087,7 +112606,7 @@ module \dec$171 connect \opcode_in \dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:70037.9-70072.4" + attribute \src "libresoc.v:69719.9-69754.4" cell \dec31 \dec31 connect \dec31_SV_Etype \dec31_dec31_SV_Etype connect \dec31_SV_Ptype \dec31_dec31_SV_Ptype @@ -113125,7 +112644,7 @@ module \dec$171 connect \opcode_in \dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:70073.9-70108.4" + attribute \src "libresoc.v:69755.9-69790.4" cell \dec58 \dec58 connect \dec58_SV_Etype \dec58_dec58_SV_Etype connect \dec58_SV_Ptype \dec58_dec58_SV_Ptype @@ -113163,7 +112682,7 @@ module \dec$171 connect \opcode_in \dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:70109.9-70144.4" + attribute \src "libresoc.v:69791.9-69826.4" cell \dec62 \dec62 connect \dec62_SV_Etype \dec62_dec62_SV_Etype connect \dec62_SV_Ptype \dec62_dec62_SV_Ptype @@ -113200,23 +112719,23 @@ module \dec$171 connect \dec62_upd \dec62_dec62_upd connect \opcode_in \dec62_opcode_in end - attribute \src "libresoc.v:67053.7-67053.20" - process $proc$libresoc.v:67053$3603 + attribute \src "libresoc.v:66735.7-66735.20" + process $proc$libresoc.v:66735$3587 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:70145.3-70289.6" - process $proc$libresoc.v:70145$3570 + attribute \src "libresoc.v:69827.3-69971.6" + process $proc$libresoc.v:69827$3554 assign { } { } assign { } { } assign { } { } assign $0\form[4:0] $2\form[4:0] - attribute \src "libresoc.v:70146.5-70146.29" + attribute \src "libresoc.v:69828.5-69828.29" switch \initial - attribute \src "libresoc.v:70146.9-70146.17" + attribute \src "libresoc.v:69828.9-69828.17" case 1'1 case end @@ -113413,15 +112932,15 @@ module \dec$171 sync always update \form $0\form[4:0] end - attribute \src "libresoc.v:70290.3-70431.6" - process $proc$libresoc.v:70290$3571 + attribute \src "libresoc.v:69972.3-70116.6" + process $proc$libresoc.v:69972$3555 assign { } { } assign { } { } assign { } { } assign $0\asmcode[7:0] $2\asmcode[7:0] - attribute \src "libresoc.v:70291.5-70291.29" + attribute \src "libresoc.v:69973.5-69973.29" switch \initial - attribute \src "libresoc.v:70291.9-70291.17" + attribute \src "libresoc.v:69973.9-69973.17" case 1'1 case end @@ -113468,6 +112987,9 @@ module \dec$171 assign { } { } assign $1\asmcode[7:0] 8'00001001 attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign $1\asmcode[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\asmcode[7:0] 8'00010001 @@ -113614,15 +113136,15 @@ module \dec$171 sync always update \asmcode $0\asmcode[7:0] end - attribute \src "libresoc.v:70432.3-70576.6" - process $proc$libresoc.v:70432$3572 + attribute \src "libresoc.v:70117.3-70261.6" + process $proc$libresoc.v:70117$3556 assign { } { } assign { } { } assign { } { } assign $0\SV_Etype[1:0] $2\SV_Etype[1:0] - attribute \src "libresoc.v:70433.5-70433.29" + attribute \src "libresoc.v:70118.5-70118.29" switch \initial - attribute \src "libresoc.v:70433.9-70433.17" + attribute \src "libresoc.v:70118.9-70118.17" case 1'1 case end @@ -113819,15 +113341,15 @@ module \dec$171 sync always update \SV_Etype $0\SV_Etype[1:0] end - attribute \src "libresoc.v:70577.3-70721.6" - process $proc$libresoc.v:70577$3573 + attribute \src "libresoc.v:70262.3-70406.6" + process $proc$libresoc.v:70262$3557 assign { } { } assign { } { } assign { } { } assign $0\SV_Ptype[1:0] $2\SV_Ptype[1:0] - attribute \src "libresoc.v:70578.5-70578.29" + attribute \src "libresoc.v:70263.5-70263.29" switch \initial - attribute \src "libresoc.v:70578.9-70578.17" + attribute \src "libresoc.v:70263.9-70263.17" case 1'1 case end @@ -114024,15 +113546,15 @@ module \dec$171 sync always update \SV_Ptype $0\SV_Ptype[1:0] end - attribute \src "libresoc.v:70722.3-70866.6" - process $proc$libresoc.v:70722$3574 + attribute \src "libresoc.v:70407.3-70551.6" + process $proc$libresoc.v:70407$3558 assign { } { } assign { } { } assign { } { } assign $0\in1_sel[2:0] $2\in1_sel[2:0] - attribute \src "libresoc.v:70723.5-70723.29" + attribute \src "libresoc.v:70408.5-70408.29" switch \initial - attribute \src "libresoc.v:70723.9-70723.17" + attribute \src "libresoc.v:70408.9-70408.17" case 1'1 case end @@ -114229,15 +113751,15 @@ module \dec$171 sync always update \in1_sel $0\in1_sel[2:0] end - attribute \src "libresoc.v:70867.3-71011.6" - process $proc$libresoc.v:70867$3575 + attribute \src "libresoc.v:70552.3-70696.6" + process $proc$libresoc.v:70552$3559 assign { } { } assign { } { } assign { } { } assign $0\in2_sel[3:0] $2\in2_sel[3:0] - attribute \src "libresoc.v:70868.5-70868.29" + attribute \src "libresoc.v:70553.5-70553.29" switch \initial - attribute \src "libresoc.v:70868.9-70868.17" + attribute \src "libresoc.v:70553.9-70553.17" case 1'1 case end @@ -114434,15 +113956,15 @@ module \dec$171 sync always update \in2_sel $0\in2_sel[3:0] end - attribute \src "libresoc.v:71012.3-71156.6" - process $proc$libresoc.v:71012$3576 + attribute \src "libresoc.v:70697.3-70841.6" + process $proc$libresoc.v:70697$3560 assign { } { } assign { } { } assign { } { } assign $0\in3_sel[1:0] $2\in3_sel[1:0] - attribute \src "libresoc.v:71013.5-71013.29" + attribute \src "libresoc.v:70698.5-70698.29" switch \initial - attribute \src "libresoc.v:71013.9-71013.17" + attribute \src "libresoc.v:70698.9-70698.17" case 1'1 case end @@ -114639,15 +114161,15 @@ module \dec$171 sync always update \in3_sel $0\in3_sel[1:0] end - attribute \src "libresoc.v:71157.3-71301.6" - process $proc$libresoc.v:71157$3577 + attribute \src "libresoc.v:70842.3-70986.6" + process $proc$libresoc.v:70842$3561 assign { } { } assign { } { } assign { } { } assign $0\out_sel[2:0] $2\out_sel[2:0] - attribute \src "libresoc.v:71158.5-71158.29" + attribute \src "libresoc.v:70843.5-70843.29" switch \initial - attribute \src "libresoc.v:71158.9-71158.17" + attribute \src "libresoc.v:70843.9-70843.17" case 1'1 case end @@ -114844,15 +114366,15 @@ module \dec$171 sync always update \out_sel $0\out_sel[2:0] end - attribute \src "libresoc.v:71302.3-71446.6" - process $proc$libresoc.v:71302$3578 + attribute \src "libresoc.v:70987.3-71131.6" + process $proc$libresoc.v:70987$3562 assign { } { } assign { } { } assign { } { } assign $0\cr_in[2:0] $2\cr_in[2:0] - attribute \src "libresoc.v:71303.5-71303.29" + attribute \src "libresoc.v:70988.5-70988.29" switch \initial - attribute \src "libresoc.v:71303.9-71303.17" + attribute \src "libresoc.v:70988.9-70988.17" case 1'1 case end @@ -115049,15 +114571,15 @@ module \dec$171 sync always update \cr_in $0\cr_in[2:0] end - attribute \src "libresoc.v:71447.3-71591.6" - process $proc$libresoc.v:71447$3579 + attribute \src "libresoc.v:71132.3-71276.6" + process $proc$libresoc.v:71132$3563 assign { } { } assign { } { } assign { } { } assign $0\cr_out[2:0] $2\cr_out[2:0] - attribute \src "libresoc.v:71448.5-71448.29" + attribute \src "libresoc.v:71133.5-71133.29" switch \initial - attribute \src "libresoc.v:71448.9-71448.17" + attribute \src "libresoc.v:71133.9-71133.17" case 1'1 case end @@ -115254,15 +114776,15 @@ module \dec$171 sync always update \cr_out $0\cr_out[2:0] end - attribute \src "libresoc.v:71592.3-71736.6" - process $proc$libresoc.v:71592$3580 + attribute \src "libresoc.v:71277.3-71421.6" + process $proc$libresoc.v:71277$3564 assign { } { } assign { } { } assign { } { } assign $0\sv_in1[2:0] $2\sv_in1[2:0] - attribute \src "libresoc.v:71593.5-71593.29" + attribute \src "libresoc.v:71278.5-71278.29" switch \initial - attribute \src "libresoc.v:71593.9-71593.17" + attribute \src "libresoc.v:71278.9-71278.17" case 1'1 case end @@ -115459,15 +114981,15 @@ module \dec$171 sync always update \sv_in1 $0\sv_in1[2:0] end - attribute \src "libresoc.v:71737.3-71881.6" - process $proc$libresoc.v:71737$3581 + attribute \src "libresoc.v:71422.3-71566.6" + process $proc$libresoc.v:71422$3565 assign { } { } assign { } { } assign { } { } assign $0\sv_in2[2:0] $2\sv_in2[2:0] - attribute \src "libresoc.v:71738.5-71738.29" + attribute \src "libresoc.v:71423.5-71423.29" switch \initial - attribute \src "libresoc.v:71738.9-71738.17" + attribute \src "libresoc.v:71423.9-71423.17" case 1'1 case end @@ -115664,15 +115186,15 @@ module \dec$171 sync always update \sv_in2 $0\sv_in2[2:0] end - attribute \src "libresoc.v:71882.3-72026.6" - process $proc$libresoc.v:71882$3582 + attribute \src "libresoc.v:71567.3-71711.6" + process $proc$libresoc.v:71567$3566 assign { } { } assign { } { } assign { } { } assign $0\sv_in3[2:0] $2\sv_in3[2:0] - attribute \src "libresoc.v:71883.5-71883.29" + attribute \src "libresoc.v:71568.5-71568.29" switch \initial - attribute \src "libresoc.v:71883.9-71883.17" + attribute \src "libresoc.v:71568.9-71568.17" case 1'1 case end @@ -115869,15 +115391,15 @@ module \dec$171 sync always update \sv_in3 $0\sv_in3[2:0] end - attribute \src "libresoc.v:72027.3-72171.6" - process $proc$libresoc.v:72027$3583 + attribute \src "libresoc.v:71712.3-71856.6" + process $proc$libresoc.v:71712$3567 assign { } { } assign { } { } assign { } { } assign $0\sv_out[2:0] $2\sv_out[2:0] - attribute \src "libresoc.v:72028.5-72028.29" + attribute \src "libresoc.v:71713.5-71713.29" switch \initial - attribute \src "libresoc.v:72028.9-72028.17" + attribute \src "libresoc.v:71713.9-71713.17" case 1'1 case end @@ -116074,15 +115596,15 @@ module \dec$171 sync always update \sv_out $0\sv_out[2:0] end - attribute \src "libresoc.v:72172.3-72316.6" - process $proc$libresoc.v:72172$3584 + attribute \src "libresoc.v:71857.3-72001.6" + process $proc$libresoc.v:71857$3568 assign { } { } assign { } { } assign { } { } assign $0\sv_out2[2:0] $2\sv_out2[2:0] - attribute \src "libresoc.v:72173.5-72173.29" + attribute \src "libresoc.v:71858.5-71858.29" switch \initial - attribute \src "libresoc.v:72173.9-72173.17" + attribute \src "libresoc.v:71858.9-71858.17" case 1'1 case end @@ -116279,15 +115801,15 @@ module \dec$171 sync always update \sv_out2 $0\sv_out2[2:0] end - attribute \src "libresoc.v:72317.3-72461.6" - process $proc$libresoc.v:72317$3585 + attribute \src "libresoc.v:72002.3-72146.6" + process $proc$libresoc.v:72002$3569 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_in[2:0] $2\sv_cr_in[2:0] - attribute \src "libresoc.v:72318.5-72318.29" + attribute \src "libresoc.v:72003.5-72003.29" switch \initial - attribute \src "libresoc.v:72318.9-72318.17" + attribute \src "libresoc.v:72003.9-72003.17" case 1'1 case end @@ -116484,15 +116006,15 @@ module \dec$171 sync always update \sv_cr_in $0\sv_cr_in[2:0] end - attribute \src "libresoc.v:72462.3-72606.6" - process $proc$libresoc.v:72462$3586 + attribute \src "libresoc.v:72147.3-72291.6" + process $proc$libresoc.v:72147$3570 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_out[2:0] $2\sv_cr_out[2:0] - attribute \src "libresoc.v:72463.5-72463.29" + attribute \src "libresoc.v:72148.5-72148.29" switch \initial - attribute \src "libresoc.v:72463.9-72463.17" + attribute \src "libresoc.v:72148.9-72148.17" case 1'1 case end @@ -116689,15 +116211,15 @@ module \dec$171 sync always update \sv_cr_out $0\sv_cr_out[2:0] end - attribute \src "libresoc.v:72607.3-72751.6" - process $proc$libresoc.v:72607$3587 + attribute \src "libresoc.v:72292.3-72436.6" + process $proc$libresoc.v:72292$3571 assign { } { } assign { } { } assign { } { } assign $0\ldst_len[3:0] $2\ldst_len[3:0] - attribute \src "libresoc.v:72608.5-72608.29" + attribute \src "libresoc.v:72293.5-72293.29" switch \initial - attribute \src "libresoc.v:72608.9-72608.17" + attribute \src "libresoc.v:72293.9-72293.17" case 1'1 case end @@ -116894,15 +116416,15 @@ module \dec$171 sync always update \ldst_len $0\ldst_len[3:0] end - attribute \src "libresoc.v:72752.3-72896.6" - process $proc$libresoc.v:72752$3588 + attribute \src "libresoc.v:72437.3-72581.6" + process $proc$libresoc.v:72437$3572 assign { } { } assign { } { } assign { } { } assign $0\upd[1:0] $2\upd[1:0] - attribute \src "libresoc.v:72753.5-72753.29" + attribute \src "libresoc.v:72438.5-72438.29" switch \initial - attribute \src "libresoc.v:72753.9-72753.17" + attribute \src "libresoc.v:72438.9-72438.17" case 1'1 case end @@ -117099,15 +116621,15 @@ module \dec$171 sync always update \upd $0\upd[1:0] end - attribute \src "libresoc.v:72897.3-73041.6" - process $proc$libresoc.v:72897$3589 + attribute \src "libresoc.v:72582.3-72726.6" + process $proc$libresoc.v:72582$3573 assign { } { } assign { } { } assign { } { } assign $0\rc_sel[1:0] $2\rc_sel[1:0] - attribute \src "libresoc.v:72898.5-72898.29" + attribute \src "libresoc.v:72583.5-72583.29" switch \initial - attribute \src "libresoc.v:72898.9-72898.17" + attribute \src "libresoc.v:72583.9-72583.17" case 1'1 case end @@ -117304,15 +116826,15 @@ module \dec$171 sync always update \rc_sel $0\rc_sel[1:0] end - attribute \src "libresoc.v:73042.3-73186.6" - process $proc$libresoc.v:73042$3590 + attribute \src "libresoc.v:72727.3-72871.6" + process $proc$libresoc.v:72727$3574 assign { } { } assign { } { } assign { } { } assign $0\cry_in[1:0] $2\cry_in[1:0] - attribute \src "libresoc.v:73043.5-73043.29" + attribute \src "libresoc.v:72728.5-72728.29" switch \initial - attribute \src "libresoc.v:73043.9-73043.17" + attribute \src "libresoc.v:72728.9-72728.17" case 1'1 case end @@ -117509,15 +117031,15 @@ module \dec$171 sync always update \cry_in $0\cry_in[1:0] end - attribute \src "libresoc.v:73187.3-73331.6" - process $proc$libresoc.v:73187$3591 + attribute \src "libresoc.v:72872.3-73016.6" + process $proc$libresoc.v:72872$3575 assign { } { } assign { } { } assign { } { } assign $0\inv_a[0:0] $2\inv_a[0:0] - attribute \src "libresoc.v:73188.5-73188.29" + attribute \src "libresoc.v:72873.5-72873.29" switch \initial - attribute \src "libresoc.v:73188.9-73188.17" + attribute \src "libresoc.v:72873.9-72873.17" case 1'1 case end @@ -117714,15 +117236,15 @@ module \dec$171 sync always update \inv_a $0\inv_a[0:0] end - attribute \src "libresoc.v:73332.3-73476.6" - process $proc$libresoc.v:73332$3592 + attribute \src "libresoc.v:73017.3-73161.6" + process $proc$libresoc.v:73017$3576 assign { } { } assign { } { } assign { } { } assign $0\inv_out[0:0] $2\inv_out[0:0] - attribute \src "libresoc.v:73333.5-73333.29" + attribute \src "libresoc.v:73018.5-73018.29" switch \initial - attribute \src "libresoc.v:73333.9-73333.17" + attribute \src "libresoc.v:73018.9-73018.17" case 1'1 case end @@ -117919,15 +117441,15 @@ module \dec$171 sync always update \inv_out $0\inv_out[0:0] end - attribute \src "libresoc.v:73477.3-73621.6" - process $proc$libresoc.v:73477$3593 + attribute \src "libresoc.v:73162.3-73306.6" + process $proc$libresoc.v:73162$3577 assign { } { } assign { } { } assign { } { } assign $0\cry_out[0:0] $2\cry_out[0:0] - attribute \src "libresoc.v:73478.5-73478.29" + attribute \src "libresoc.v:73163.5-73163.29" switch \initial - attribute \src "libresoc.v:73478.9-73478.17" + attribute \src "libresoc.v:73163.9-73163.17" case 1'1 case end @@ -118124,15 +117646,15 @@ module \dec$171 sync always update \cry_out $0\cry_out[0:0] end - attribute \src "libresoc.v:73622.3-73766.6" - process $proc$libresoc.v:73622$3594 + attribute \src "libresoc.v:73307.3-73451.6" + process $proc$libresoc.v:73307$3578 assign { } { } assign { } { } assign { } { } assign $0\br[0:0] $2\br[0:0] - attribute \src "libresoc.v:73623.5-73623.29" + attribute \src "libresoc.v:73308.5-73308.29" switch \initial - attribute \src "libresoc.v:73623.9-73623.17" + attribute \src "libresoc.v:73308.9-73308.17" case 1'1 case end @@ -118329,15 +117851,15 @@ module \dec$171 sync always update \br $0\br[0:0] end - attribute \src "libresoc.v:73767.3-73911.6" - process $proc$libresoc.v:73767$3595 + attribute \src "libresoc.v:73452.3-73596.6" + process $proc$libresoc.v:73452$3579 assign { } { } assign { } { } assign { } { } assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] - attribute \src "libresoc.v:73768.5-73768.29" + attribute \src "libresoc.v:73453.5-73453.29" switch \initial - attribute \src "libresoc.v:73768.9-73768.17" + attribute \src "libresoc.v:73453.9-73453.17" case 1'1 case end @@ -118534,15 +118056,15 @@ module \dec$171 sync always update \sgn_ext $0\sgn_ext[0:0] end - attribute \src "libresoc.v:73912.3-74056.6" - process $proc$libresoc.v:73912$3596 + attribute \src "libresoc.v:73597.3-73741.6" + process $proc$libresoc.v:73597$3580 assign { } { } assign { } { } assign { } { } assign $0\rsrv[0:0] $2\rsrv[0:0] - attribute \src "libresoc.v:73913.5-73913.29" + attribute \src "libresoc.v:73598.5-73598.29" switch \initial - attribute \src "libresoc.v:73913.9-73913.17" + attribute \src "libresoc.v:73598.9-73598.17" case 1'1 case end @@ -118739,15 +118261,15 @@ module \dec$171 sync always update \rsrv $0\rsrv[0:0] end - attribute \src "libresoc.v:74057.3-74201.6" - process $proc$libresoc.v:74057$3597 + attribute \src "libresoc.v:73742.3-73886.6" + process $proc$libresoc.v:73742$3581 assign { } { } assign { } { } assign { } { } assign $0\is_32b[0:0] $2\is_32b[0:0] - attribute \src "libresoc.v:74058.5-74058.29" + attribute \src "libresoc.v:73743.5-73743.29" switch \initial - attribute \src "libresoc.v:74058.9-74058.17" + attribute \src "libresoc.v:73743.9-73743.17" case 1'1 case end @@ -118944,15 +118466,15 @@ module \dec$171 sync always update \is_32b $0\is_32b[0:0] end - attribute \src "libresoc.v:74202.3-74346.6" - process $proc$libresoc.v:74202$3598 + attribute \src "libresoc.v:73887.3-74031.6" + process $proc$libresoc.v:73887$3582 assign { } { } assign { } { } assign { } { } assign $0\sgn[0:0] $2\sgn[0:0] - attribute \src "libresoc.v:74203.5-74203.29" + attribute \src "libresoc.v:73888.5-73888.29" switch \initial - attribute \src "libresoc.v:74203.9-74203.17" + attribute \src "libresoc.v:73888.9-73888.17" case 1'1 case end @@ -119149,15 +118671,15 @@ module \dec$171 sync always update \sgn $0\sgn[0:0] end - attribute \src "libresoc.v:74347.3-74491.6" - process $proc$libresoc.v:74347$3599 + attribute \src "libresoc.v:74032.3-74176.6" + process $proc$libresoc.v:74032$3583 assign { } { } assign { } { } assign { } { } assign $0\lk[0:0] $2\lk[0:0] - attribute \src "libresoc.v:74348.5-74348.29" + attribute \src "libresoc.v:74033.5-74033.29" switch \initial - attribute \src "libresoc.v:74348.9-74348.17" + attribute \src "libresoc.v:74033.9-74033.17" case 1'1 case end @@ -119354,15 +118876,15 @@ module \dec$171 sync always update \lk $0\lk[0:0] end - attribute \src "libresoc.v:74492.3-74636.6" - process $proc$libresoc.v:74492$3600 + attribute \src "libresoc.v:74177.3-74321.6" + process $proc$libresoc.v:74177$3584 assign { } { } assign { } { } assign { } { } assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] - attribute \src "libresoc.v:74493.5-74493.29" + attribute \src "libresoc.v:74178.5-74178.29" switch \initial - attribute \src "libresoc.v:74493.9-74493.17" + attribute \src "libresoc.v:74178.9-74178.17" case 1'1 case end @@ -119559,15 +119081,15 @@ module \dec$171 sync always update \sgl_pipe $0\sgl_pipe[0:0] end - attribute \src "libresoc.v:74637.3-74781.6" - process $proc$libresoc.v:74637$3601 + attribute \src "libresoc.v:74322.3-74466.6" + process $proc$libresoc.v:74322$3585 assign { } { } assign { } { } assign { } { } assign $0\function_unit[13:0] $2\function_unit[13:0] - attribute \src "libresoc.v:74638.5-74638.29" + attribute \src "libresoc.v:74323.5-74323.29" switch \initial - attribute \src "libresoc.v:74638.9-74638.17" + attribute \src "libresoc.v:74323.9-74323.17" case 1'1 case end @@ -119764,15 +119286,15 @@ module \dec$171 sync always update \function_unit $0\function_unit[13:0] end - attribute \src "libresoc.v:74782.3-74926.6" - process $proc$libresoc.v:74782$3602 + attribute \src "libresoc.v:74467.3-74611.6" + process $proc$libresoc.v:74467$3586 assign { } { } assign { } { } assign { } { } assign $0\internal_op[6:0] $2\internal_op[6:0] - attribute \src "libresoc.v:74783.5-74783.29" + attribute \src "libresoc.v:74468.5-74468.29" switch \initial - attribute \src "libresoc.v:74783.9-74783.17" + attribute \src "libresoc.v:74468.9-74468.17" case 1'1 case end @@ -119969,7 +119491,7 @@ module \dec$171 sync always update \internal_op $0\internal_op[6:0] end - connect \$2 $ternary$libresoc.v:69928$3569_Y + connect \$2 $ternary$libresoc.v:69610$3553_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -120313,144 +119835,144 @@ module \dec$171 connect \dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:75273.1-77339.10" +attribute \src "libresoc.v:74958.1-77024.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" attribute \generator "nMigen" module \dec19 - attribute \src "libresoc.v:77026.3-77077.6" + attribute \src "libresoc.v:76711.3-76762.6" wire width 2 $0\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:77078.3-77129.6" + attribute \src "libresoc.v:76763.3-76814.6" wire width 2 $0\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:76402.3-76453.6" + attribute \src "libresoc.v:76087.3-76138.6" wire width 8 $0\dec19_asmcode[7:0] - attribute \src "libresoc.v:76610.3-76661.6" + attribute \src "libresoc.v:76295.3-76346.6" wire $0\dec19_br[0:0] - attribute \src "libresoc.v:75674.3-75725.6" + attribute \src "libresoc.v:75359.3-75410.6" wire width 3 $0\dec19_cr_in[2:0] - attribute \src "libresoc.v:75726.3-75777.6" + attribute \src "libresoc.v:75411.3-75462.6" wire width 3 $0\dec19_cr_out[2:0] - attribute \src "libresoc.v:76350.3-76401.6" + attribute \src "libresoc.v:76035.3-76086.6" wire width 2 $0\dec19_cry_in[1:0] - attribute \src "libresoc.v:76558.3-76609.6" + attribute \src "libresoc.v:76243.3-76294.6" wire $0\dec19_cry_out[0:0] - attribute \src "libresoc.v:76766.3-76817.6" + attribute \src "libresoc.v:76451.3-76502.6" wire width 5 $0\dec19_form[4:0] - attribute \src "libresoc.v:75622.3-75673.6" + attribute \src "libresoc.v:75307.3-75358.6" wire width 14 $0\dec19_function_unit[13:0] - attribute \src "libresoc.v:77130.3-77181.6" + attribute \src "libresoc.v:76815.3-76866.6" wire width 3 $0\dec19_in1_sel[2:0] - attribute \src "libresoc.v:77182.3-77233.6" + attribute \src "libresoc.v:76867.3-76918.6" wire width 4 $0\dec19_in2_sel[3:0] - attribute \src "libresoc.v:77234.3-77285.6" + attribute \src "libresoc.v:76919.3-76970.6" wire width 2 $0\dec19_in3_sel[1:0] - attribute \src "libresoc.v:76194.3-76245.6" + attribute \src "libresoc.v:75879.3-75930.6" wire width 7 $0\dec19_internal_op[6:0] - attribute \src "libresoc.v:76454.3-76505.6" + attribute \src "libresoc.v:76139.3-76190.6" wire $0\dec19_inv_a[0:0] - attribute \src "libresoc.v:76506.3-76557.6" + attribute \src "libresoc.v:76191.3-76242.6" wire $0\dec19_inv_out[0:0] - attribute \src "libresoc.v:76818.3-76869.6" + attribute \src "libresoc.v:76503.3-76554.6" wire $0\dec19_is_32b[0:0] - attribute \src "libresoc.v:76142.3-76193.6" + attribute \src "libresoc.v:75827.3-75878.6" wire width 4 $0\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76922.3-76973.6" + attribute \src "libresoc.v:76607.3-76658.6" wire $0\dec19_lk[0:0] - attribute \src "libresoc.v:77286.3-77337.6" + attribute \src "libresoc.v:76971.3-77022.6" wire width 3 $0\dec19_out_sel[2:0] - attribute \src "libresoc.v:76298.3-76349.6" + attribute \src "libresoc.v:75983.3-76034.6" wire width 2 $0\dec19_rc_sel[1:0] - attribute \src "libresoc.v:76714.3-76765.6" + attribute \src "libresoc.v:76399.3-76450.6" wire $0\dec19_rsrv[0:0] - attribute \src "libresoc.v:76974.3-77025.6" + attribute \src "libresoc.v:76659.3-76710.6" wire $0\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76870.3-76921.6" + attribute \src "libresoc.v:76555.3-76606.6" wire $0\dec19_sgn[0:0] - attribute \src "libresoc.v:76662.3-76713.6" + attribute \src "libresoc.v:76347.3-76398.6" wire $0\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:76038.3-76089.6" + attribute \src "libresoc.v:75723.3-75774.6" wire width 3 $0\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:76090.3-76141.6" + attribute \src "libresoc.v:75775.3-75826.6" wire width 3 $0\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75778.3-75829.6" + attribute \src "libresoc.v:75463.3-75514.6" wire width 3 $0\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75830.3-75881.6" + attribute \src "libresoc.v:75515.3-75566.6" wire width 3 $0\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75882.3-75933.6" + attribute \src "libresoc.v:75567.3-75618.6" wire width 3 $0\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75986.3-76037.6" + attribute \src "libresoc.v:75671.3-75722.6" wire width 3 $0\dec19_sv_out2[2:0] - attribute \src "libresoc.v:75934.3-75985.6" + attribute \src "libresoc.v:75619.3-75670.6" wire width 3 $0\dec19_sv_out[2:0] - attribute \src "libresoc.v:76246.3-76297.6" + attribute \src "libresoc.v:75931.3-75982.6" wire width 2 $0\dec19_upd[1:0] - attribute \src "libresoc.v:75274.7-75274.20" + attribute \src "libresoc.v:74959.7-74959.20" wire $0\initial[0:0] - attribute \src "libresoc.v:77026.3-77077.6" + attribute \src "libresoc.v:76711.3-76762.6" wire width 2 $1\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:77078.3-77129.6" + attribute \src "libresoc.v:76763.3-76814.6" wire width 2 $1\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:76402.3-76453.6" + attribute \src "libresoc.v:76087.3-76138.6" wire width 8 $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:76610.3-76661.6" + attribute \src "libresoc.v:76295.3-76346.6" wire $1\dec19_br[0:0] - attribute \src "libresoc.v:75674.3-75725.6" + attribute \src "libresoc.v:75359.3-75410.6" wire width 3 $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:75726.3-75777.6" + attribute \src "libresoc.v:75411.3-75462.6" wire width 3 $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:76350.3-76401.6" + attribute \src "libresoc.v:76035.3-76086.6" wire width 2 $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:76558.3-76609.6" + attribute \src "libresoc.v:76243.3-76294.6" wire $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:76766.3-76817.6" + attribute \src "libresoc.v:76451.3-76502.6" wire width 5 $1\dec19_form[4:0] - attribute \src "libresoc.v:75622.3-75673.6" + attribute \src "libresoc.v:75307.3-75358.6" wire width 14 $1\dec19_function_unit[13:0] - attribute \src "libresoc.v:77130.3-77181.6" + attribute \src "libresoc.v:76815.3-76866.6" wire width 3 $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:77182.3-77233.6" + attribute \src "libresoc.v:76867.3-76918.6" wire width 4 $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:77234.3-77285.6" + attribute \src "libresoc.v:76919.3-76970.6" wire width 2 $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:76194.3-76245.6" + attribute \src "libresoc.v:75879.3-75930.6" wire width 7 $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:76454.3-76505.6" + attribute \src "libresoc.v:76139.3-76190.6" wire $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:76506.3-76557.6" + attribute \src "libresoc.v:76191.3-76242.6" wire $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:76818.3-76869.6" + attribute \src "libresoc.v:76503.3-76554.6" wire $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:76142.3-76193.6" + attribute \src "libresoc.v:75827.3-75878.6" wire width 4 $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76922.3-76973.6" + attribute \src "libresoc.v:76607.3-76658.6" wire $1\dec19_lk[0:0] - attribute \src "libresoc.v:77286.3-77337.6" + attribute \src "libresoc.v:76971.3-77022.6" wire width 3 $1\dec19_out_sel[2:0] - attribute \src "libresoc.v:76298.3-76349.6" + attribute \src "libresoc.v:75983.3-76034.6" wire width 2 $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:76714.3-76765.6" + attribute \src "libresoc.v:76399.3-76450.6" wire $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:76974.3-77025.6" + attribute \src "libresoc.v:76659.3-76710.6" wire $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76870.3-76921.6" + attribute \src "libresoc.v:76555.3-76606.6" wire $1\dec19_sgn[0:0] - attribute \src "libresoc.v:76662.3-76713.6" + attribute \src "libresoc.v:76347.3-76398.6" wire $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:76038.3-76089.6" + attribute \src "libresoc.v:75723.3-75774.6" wire width 3 $1\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:76090.3-76141.6" + attribute \src "libresoc.v:75775.3-75826.6" wire width 3 $1\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75778.3-75829.6" + attribute \src "libresoc.v:75463.3-75514.6" wire width 3 $1\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75830.3-75881.6" + attribute \src "libresoc.v:75515.3-75566.6" wire width 3 $1\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75882.3-75933.6" + attribute \src "libresoc.v:75567.3-75618.6" wire width 3 $1\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75986.3-76037.6" + attribute \src "libresoc.v:75671.3-75722.6" wire width 3 $1\dec19_sv_out2[2:0] - attribute \src "libresoc.v:75934.3-75985.6" + attribute \src "libresoc.v:75619.3-75670.6" wire width 3 $1\dec19_sv_out[2:0] - attribute \src "libresoc.v:76246.3-76297.6" + attribute \src "libresoc.v:75931.3-75982.6" wire width 2 $1\dec19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -120762,28 +120284,28 @@ module \dec19 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec19_upd - attribute \src "libresoc.v:75274.7-75274.15" + attribute \src "libresoc.v:74959.7-74959.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch - attribute \src "libresoc.v:75274.7-75274.20" - process $proc$libresoc.v:75274$3637 + attribute \src "libresoc.v:74959.7-74959.20" + process $proc$libresoc.v:74959$3621 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:75622.3-75673.6" - process $proc$libresoc.v:75622$3604 + attribute \src "libresoc.v:75307.3-75358.6" + process $proc$libresoc.v:75307$3588 assign { } { } assign { } { } assign $0\dec19_function_unit[13:0] $1\dec19_function_unit[13:0] - attribute \src "libresoc.v:75623.5-75623.29" + attribute \src "libresoc.v:75308.5-75308.29" switch \initial - attribute \src "libresoc.v:75623.9-75623.17" + attribute \src "libresoc.v:75308.9-75308.17" case 1'1 case end @@ -120855,14 +120377,14 @@ module \dec19 sync always update \dec19_function_unit $0\dec19_function_unit[13:0] end - attribute \src "libresoc.v:75674.3-75725.6" - process $proc$libresoc.v:75674$3605 + attribute \src "libresoc.v:75359.3-75410.6" + process $proc$libresoc.v:75359$3589 assign { } { } assign { } { } assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:75675.5-75675.29" + attribute \src "libresoc.v:75360.5-75360.29" switch \initial - attribute \src "libresoc.v:75675.9-75675.17" + attribute \src "libresoc.v:75360.9-75360.17" case 1'1 case end @@ -120934,14 +120456,14 @@ module \dec19 sync always update \dec19_cr_in $0\dec19_cr_in[2:0] end - attribute \src "libresoc.v:75726.3-75777.6" - process $proc$libresoc.v:75726$3606 + attribute \src "libresoc.v:75411.3-75462.6" + process $proc$libresoc.v:75411$3590 assign { } { } assign { } { } assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:75727.5-75727.29" + attribute \src "libresoc.v:75412.5-75412.29" switch \initial - attribute \src "libresoc.v:75727.9-75727.17" + attribute \src "libresoc.v:75412.9-75412.17" case 1'1 case end @@ -121013,14 +120535,14 @@ module \dec19 sync always update \dec19_cr_out $0\dec19_cr_out[2:0] end - attribute \src "libresoc.v:75778.3-75829.6" - process $proc$libresoc.v:75778$3607 + attribute \src "libresoc.v:75463.3-75514.6" + process $proc$libresoc.v:75463$3591 assign { } { } assign { } { } assign $0\dec19_sv_in1[2:0] $1\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75779.5-75779.29" + attribute \src "libresoc.v:75464.5-75464.29" switch \initial - attribute \src "libresoc.v:75779.9-75779.17" + attribute \src "libresoc.v:75464.9-75464.17" case 1'1 case end @@ -121092,14 +120614,14 @@ module \dec19 sync always update \dec19_sv_in1 $0\dec19_sv_in1[2:0] end - attribute \src "libresoc.v:75830.3-75881.6" - process $proc$libresoc.v:75830$3608 + attribute \src "libresoc.v:75515.3-75566.6" + process $proc$libresoc.v:75515$3592 assign { } { } assign { } { } assign $0\dec19_sv_in2[2:0] $1\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75831.5-75831.29" + attribute \src "libresoc.v:75516.5-75516.29" switch \initial - attribute \src "libresoc.v:75831.9-75831.17" + attribute \src "libresoc.v:75516.9-75516.17" case 1'1 case end @@ -121171,14 +120693,14 @@ module \dec19 sync always update \dec19_sv_in2 $0\dec19_sv_in2[2:0] end - attribute \src "libresoc.v:75882.3-75933.6" - process $proc$libresoc.v:75882$3609 + attribute \src "libresoc.v:75567.3-75618.6" + process $proc$libresoc.v:75567$3593 assign { } { } assign { } { } assign $0\dec19_sv_in3[2:0] $1\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75883.5-75883.29" + attribute \src "libresoc.v:75568.5-75568.29" switch \initial - attribute \src "libresoc.v:75883.9-75883.17" + attribute \src "libresoc.v:75568.9-75568.17" case 1'1 case end @@ -121250,14 +120772,14 @@ module \dec19 sync always update \dec19_sv_in3 $0\dec19_sv_in3[2:0] end - attribute \src "libresoc.v:75934.3-75985.6" - process $proc$libresoc.v:75934$3610 + attribute \src "libresoc.v:75619.3-75670.6" + process $proc$libresoc.v:75619$3594 assign { } { } assign { } { } assign $0\dec19_sv_out[2:0] $1\dec19_sv_out[2:0] - attribute \src "libresoc.v:75935.5-75935.29" + attribute \src "libresoc.v:75620.5-75620.29" switch \initial - attribute \src "libresoc.v:75935.9-75935.17" + attribute \src "libresoc.v:75620.9-75620.17" case 1'1 case end @@ -121329,14 +120851,14 @@ module \dec19 sync always update \dec19_sv_out $0\dec19_sv_out[2:0] end - attribute \src "libresoc.v:75986.3-76037.6" - process $proc$libresoc.v:75986$3611 + attribute \src "libresoc.v:75671.3-75722.6" + process $proc$libresoc.v:75671$3595 assign { } { } assign { } { } assign $0\dec19_sv_out2[2:0] $1\dec19_sv_out2[2:0] - attribute \src "libresoc.v:75987.5-75987.29" + attribute \src "libresoc.v:75672.5-75672.29" switch \initial - attribute \src "libresoc.v:75987.9-75987.17" + attribute \src "libresoc.v:75672.9-75672.17" case 1'1 case end @@ -121408,14 +120930,14 @@ module \dec19 sync always update \dec19_sv_out2 $0\dec19_sv_out2[2:0] end - attribute \src "libresoc.v:76038.3-76089.6" - process $proc$libresoc.v:76038$3612 + attribute \src "libresoc.v:75723.3-75774.6" + process $proc$libresoc.v:75723$3596 assign { } { } assign { } { } assign $0\dec19_sv_cr_in[2:0] $1\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:76039.5-76039.29" + attribute \src "libresoc.v:75724.5-75724.29" switch \initial - attribute \src "libresoc.v:76039.9-76039.17" + attribute \src "libresoc.v:75724.9-75724.17" case 1'1 case end @@ -121487,14 +121009,14 @@ module \dec19 sync always update \dec19_sv_cr_in $0\dec19_sv_cr_in[2:0] end - attribute \src "libresoc.v:76090.3-76141.6" - process $proc$libresoc.v:76090$3613 + attribute \src "libresoc.v:75775.3-75826.6" + process $proc$libresoc.v:75775$3597 assign { } { } assign { } { } assign $0\dec19_sv_cr_out[2:0] $1\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:76091.5-76091.29" + attribute \src "libresoc.v:75776.5-75776.29" switch \initial - attribute \src "libresoc.v:76091.9-76091.17" + attribute \src "libresoc.v:75776.9-75776.17" case 1'1 case end @@ -121566,14 +121088,14 @@ module \dec19 sync always update \dec19_sv_cr_out $0\dec19_sv_cr_out[2:0] end - attribute \src "libresoc.v:76142.3-76193.6" - process $proc$libresoc.v:76142$3614 + attribute \src "libresoc.v:75827.3-75878.6" + process $proc$libresoc.v:75827$3598 assign { } { } assign { } { } assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76143.5-76143.29" + attribute \src "libresoc.v:75828.5-75828.29" switch \initial - attribute \src "libresoc.v:76143.9-76143.17" + attribute \src "libresoc.v:75828.9-75828.17" case 1'1 case end @@ -121645,14 +121167,14 @@ module \dec19 sync always update \dec19_ldst_len $0\dec19_ldst_len[3:0] end - attribute \src "libresoc.v:76194.3-76245.6" - process $proc$libresoc.v:76194$3615 + attribute \src "libresoc.v:75879.3-75930.6" + process $proc$libresoc.v:75879$3599 assign { } { } assign { } { } assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:76195.5-76195.29" + attribute \src "libresoc.v:75880.5-75880.29" switch \initial - attribute \src "libresoc.v:76195.9-76195.17" + attribute \src "libresoc.v:75880.9-75880.17" case 1'1 case end @@ -121724,14 +121246,14 @@ module \dec19 sync always update \dec19_internal_op $0\dec19_internal_op[6:0] end - attribute \src "libresoc.v:76246.3-76297.6" - process $proc$libresoc.v:76246$3616 + attribute \src "libresoc.v:75931.3-75982.6" + process $proc$libresoc.v:75931$3600 assign { } { } assign { } { } assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] - attribute \src "libresoc.v:76247.5-76247.29" + attribute \src "libresoc.v:75932.5-75932.29" switch \initial - attribute \src "libresoc.v:76247.9-76247.17" + attribute \src "libresoc.v:75932.9-75932.17" case 1'1 case end @@ -121803,14 +121325,14 @@ module \dec19 sync always update \dec19_upd $0\dec19_upd[1:0] end - attribute \src "libresoc.v:76298.3-76349.6" - process $proc$libresoc.v:76298$3617 + attribute \src "libresoc.v:75983.3-76034.6" + process $proc$libresoc.v:75983$3601 assign { } { } assign { } { } assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:76299.5-76299.29" + attribute \src "libresoc.v:75984.5-75984.29" switch \initial - attribute \src "libresoc.v:76299.9-76299.17" + attribute \src "libresoc.v:75984.9-75984.17" case 1'1 case end @@ -121882,14 +121404,14 @@ module \dec19 sync always update \dec19_rc_sel $0\dec19_rc_sel[1:0] end - attribute \src "libresoc.v:76350.3-76401.6" - process $proc$libresoc.v:76350$3618 + attribute \src "libresoc.v:76035.3-76086.6" + process $proc$libresoc.v:76035$3602 assign { } { } assign { } { } assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:76351.5-76351.29" + attribute \src "libresoc.v:76036.5-76036.29" switch \initial - attribute \src "libresoc.v:76351.9-76351.17" + attribute \src "libresoc.v:76036.9-76036.17" case 1'1 case end @@ -121961,14 +121483,14 @@ module \dec19 sync always update \dec19_cry_in $0\dec19_cry_in[1:0] end - attribute \src "libresoc.v:76402.3-76453.6" - process $proc$libresoc.v:76402$3619 + attribute \src "libresoc.v:76087.3-76138.6" + process $proc$libresoc.v:76087$3603 assign { } { } assign { } { } assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:76403.5-76403.29" + attribute \src "libresoc.v:76088.5-76088.29" switch \initial - attribute \src "libresoc.v:76403.9-76403.17" + attribute \src "libresoc.v:76088.9-76088.17" case 1'1 case end @@ -122040,14 +121562,14 @@ module \dec19 sync always update \dec19_asmcode $0\dec19_asmcode[7:0] end - attribute \src "libresoc.v:76454.3-76505.6" - process $proc$libresoc.v:76454$3620 + attribute \src "libresoc.v:76139.3-76190.6" + process $proc$libresoc.v:76139$3604 assign { } { } assign { } { } assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:76455.5-76455.29" + attribute \src "libresoc.v:76140.5-76140.29" switch \initial - attribute \src "libresoc.v:76455.9-76455.17" + attribute \src "libresoc.v:76140.9-76140.17" case 1'1 case end @@ -122119,14 +121641,14 @@ module \dec19 sync always update \dec19_inv_a $0\dec19_inv_a[0:0] end - attribute \src "libresoc.v:76506.3-76557.6" - process $proc$libresoc.v:76506$3621 + attribute \src "libresoc.v:76191.3-76242.6" + process $proc$libresoc.v:76191$3605 assign { } { } assign { } { } assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:76507.5-76507.29" + attribute \src "libresoc.v:76192.5-76192.29" switch \initial - attribute \src "libresoc.v:76507.9-76507.17" + attribute \src "libresoc.v:76192.9-76192.17" case 1'1 case end @@ -122198,14 +121720,14 @@ module \dec19 sync always update \dec19_inv_out $0\dec19_inv_out[0:0] end - attribute \src "libresoc.v:76558.3-76609.6" - process $proc$libresoc.v:76558$3622 + attribute \src "libresoc.v:76243.3-76294.6" + process $proc$libresoc.v:76243$3606 assign { } { } assign { } { } assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:76559.5-76559.29" + attribute \src "libresoc.v:76244.5-76244.29" switch \initial - attribute \src "libresoc.v:76559.9-76559.17" + attribute \src "libresoc.v:76244.9-76244.17" case 1'1 case end @@ -122277,14 +121799,14 @@ module \dec19 sync always update \dec19_cry_out $0\dec19_cry_out[0:0] end - attribute \src "libresoc.v:76610.3-76661.6" - process $proc$libresoc.v:76610$3623 + attribute \src "libresoc.v:76295.3-76346.6" + process $proc$libresoc.v:76295$3607 assign { } { } assign { } { } assign $0\dec19_br[0:0] $1\dec19_br[0:0] - attribute \src "libresoc.v:76611.5-76611.29" + attribute \src "libresoc.v:76296.5-76296.29" switch \initial - attribute \src "libresoc.v:76611.9-76611.17" + attribute \src "libresoc.v:76296.9-76296.17" case 1'1 case end @@ -122356,14 +121878,14 @@ module \dec19 sync always update \dec19_br $0\dec19_br[0:0] end - attribute \src "libresoc.v:76662.3-76713.6" - process $proc$libresoc.v:76662$3624 + attribute \src "libresoc.v:76347.3-76398.6" + process $proc$libresoc.v:76347$3608 assign { } { } assign { } { } assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:76663.5-76663.29" + attribute \src "libresoc.v:76348.5-76348.29" switch \initial - attribute \src "libresoc.v:76663.9-76663.17" + attribute \src "libresoc.v:76348.9-76348.17" case 1'1 case end @@ -122435,14 +121957,14 @@ module \dec19 sync always update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] end - attribute \src "libresoc.v:76714.3-76765.6" - process $proc$libresoc.v:76714$3625 + attribute \src "libresoc.v:76399.3-76450.6" + process $proc$libresoc.v:76399$3609 assign { } { } assign { } { } assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:76715.5-76715.29" + attribute \src "libresoc.v:76400.5-76400.29" switch \initial - attribute \src "libresoc.v:76715.9-76715.17" + attribute \src "libresoc.v:76400.9-76400.17" case 1'1 case end @@ -122514,14 +122036,14 @@ module \dec19 sync always update \dec19_rsrv $0\dec19_rsrv[0:0] end - attribute \src "libresoc.v:76766.3-76817.6" - process $proc$libresoc.v:76766$3626 + attribute \src "libresoc.v:76451.3-76502.6" + process $proc$libresoc.v:76451$3610 assign { } { } assign { } { } assign $0\dec19_form[4:0] $1\dec19_form[4:0] - attribute \src "libresoc.v:76767.5-76767.29" + attribute \src "libresoc.v:76452.5-76452.29" switch \initial - attribute \src "libresoc.v:76767.9-76767.17" + attribute \src "libresoc.v:76452.9-76452.17" case 1'1 case end @@ -122593,14 +122115,14 @@ module \dec19 sync always update \dec19_form $0\dec19_form[4:0] end - attribute \src "libresoc.v:76818.3-76869.6" - process $proc$libresoc.v:76818$3627 + attribute \src "libresoc.v:76503.3-76554.6" + process $proc$libresoc.v:76503$3611 assign { } { } assign { } { } assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:76819.5-76819.29" + attribute \src "libresoc.v:76504.5-76504.29" switch \initial - attribute \src "libresoc.v:76819.9-76819.17" + attribute \src "libresoc.v:76504.9-76504.17" case 1'1 case end @@ -122672,14 +122194,14 @@ module \dec19 sync always update \dec19_is_32b $0\dec19_is_32b[0:0] end - attribute \src "libresoc.v:76870.3-76921.6" - process $proc$libresoc.v:76870$3628 + attribute \src "libresoc.v:76555.3-76606.6" + process $proc$libresoc.v:76555$3612 assign { } { } assign { } { } assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] - attribute \src "libresoc.v:76871.5-76871.29" + attribute \src "libresoc.v:76556.5-76556.29" switch \initial - attribute \src "libresoc.v:76871.9-76871.17" + attribute \src "libresoc.v:76556.9-76556.17" case 1'1 case end @@ -122751,14 +122273,14 @@ module \dec19 sync always update \dec19_sgn $0\dec19_sgn[0:0] end - attribute \src "libresoc.v:76922.3-76973.6" - process $proc$libresoc.v:76922$3629 + attribute \src "libresoc.v:76607.3-76658.6" + process $proc$libresoc.v:76607$3613 assign { } { } assign { } { } assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] - attribute \src "libresoc.v:76923.5-76923.29" + attribute \src "libresoc.v:76608.5-76608.29" switch \initial - attribute \src "libresoc.v:76923.9-76923.17" + attribute \src "libresoc.v:76608.9-76608.17" case 1'1 case end @@ -122830,14 +122352,14 @@ module \dec19 sync always update \dec19_lk $0\dec19_lk[0:0] end - attribute \src "libresoc.v:76974.3-77025.6" - process $proc$libresoc.v:76974$3630 + attribute \src "libresoc.v:76659.3-76710.6" + process $proc$libresoc.v:76659$3614 assign { } { } assign { } { } assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76975.5-76975.29" + attribute \src "libresoc.v:76660.5-76660.29" switch \initial - attribute \src "libresoc.v:76975.9-76975.17" + attribute \src "libresoc.v:76660.9-76660.17" case 1'1 case end @@ -122909,14 +122431,14 @@ module \dec19 sync always update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] end - attribute \src "libresoc.v:77026.3-77077.6" - process $proc$libresoc.v:77026$3631 + attribute \src "libresoc.v:76711.3-76762.6" + process $proc$libresoc.v:76711$3615 assign { } { } assign { } { } assign $0\dec19_SV_Etype[1:0] $1\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:77027.5-77027.29" + attribute \src "libresoc.v:76712.5-76712.29" switch \initial - attribute \src "libresoc.v:77027.9-77027.17" + attribute \src "libresoc.v:76712.9-76712.17" case 1'1 case end @@ -122988,14 +122510,14 @@ module \dec19 sync always update \dec19_SV_Etype $0\dec19_SV_Etype[1:0] end - attribute \src "libresoc.v:77078.3-77129.6" - process $proc$libresoc.v:77078$3632 + attribute \src "libresoc.v:76763.3-76814.6" + process $proc$libresoc.v:76763$3616 assign { } { } assign { } { } assign $0\dec19_SV_Ptype[1:0] $1\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:77079.5-77079.29" + attribute \src "libresoc.v:76764.5-76764.29" switch \initial - attribute \src "libresoc.v:77079.9-77079.17" + attribute \src "libresoc.v:76764.9-76764.17" case 1'1 case end @@ -123067,14 +122589,14 @@ module \dec19 sync always update \dec19_SV_Ptype $0\dec19_SV_Ptype[1:0] end - attribute \src "libresoc.v:77130.3-77181.6" - process $proc$libresoc.v:77130$3633 + attribute \src "libresoc.v:76815.3-76866.6" + process $proc$libresoc.v:76815$3617 assign { } { } assign { } { } assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:77131.5-77131.29" + attribute \src "libresoc.v:76816.5-76816.29" switch \initial - attribute \src "libresoc.v:77131.9-77131.17" + attribute \src "libresoc.v:76816.9-76816.17" case 1'1 case end @@ -123146,14 +122668,14 @@ module \dec19 sync always update \dec19_in1_sel $0\dec19_in1_sel[2:0] end - attribute \src "libresoc.v:77182.3-77233.6" - process $proc$libresoc.v:77182$3634 + attribute \src "libresoc.v:76867.3-76918.6" + process $proc$libresoc.v:76867$3618 assign { } { } assign { } { } assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:77183.5-77183.29" + attribute \src "libresoc.v:76868.5-76868.29" switch \initial - attribute \src "libresoc.v:77183.9-77183.17" + attribute \src "libresoc.v:76868.9-76868.17" case 1'1 case end @@ -123225,14 +122747,14 @@ module \dec19 sync always update \dec19_in2_sel $0\dec19_in2_sel[3:0] end - attribute \src "libresoc.v:77234.3-77285.6" - process $proc$libresoc.v:77234$3635 + attribute \src "libresoc.v:76919.3-76970.6" + process $proc$libresoc.v:76919$3619 assign { } { } assign { } { } assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:77235.5-77235.29" + attribute \src "libresoc.v:76920.5-76920.29" switch \initial - attribute \src "libresoc.v:77235.9-77235.17" + attribute \src "libresoc.v:76920.9-76920.17" case 1'1 case end @@ -123304,14 +122826,14 @@ module \dec19 sync always update \dec19_in3_sel $0\dec19_in3_sel[1:0] end - attribute \src "libresoc.v:77286.3-77337.6" - process $proc$libresoc.v:77286$3636 + attribute \src "libresoc.v:76971.3-77022.6" + process $proc$libresoc.v:76971$3620 assign { } { } assign { } { } assign $0\dec19_out_sel[2:0] $1\dec19_out_sel[2:0] - attribute \src "libresoc.v:77287.5-77287.29" + attribute \src "libresoc.v:76972.5-76972.29" switch \initial - attribute \src "libresoc.v:77287.9-77287.17" + attribute \src "libresoc.v:76972.9-76972.17" case 1'1 case end @@ -123385,872 +122907,872 @@ module \dec19 end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:77343.1-79564.10" +attribute \src "libresoc.v:77028.1-79249.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2" attribute \generator "nMigen" module \dec2 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $0\cia[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\cr_in1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_in1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire width 7 $0\cr_in2$1[6:0]$3698 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire width 7 $0\cr_in2$1[6:0]$3682 + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\cr_in2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire $0\cr_in2_ok$2[0:0]$3699 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire $0\cr_in2_ok$2[0:0]$3683 + attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_in2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\cr_out[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_out_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $0\cr_rd[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_rd_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $0\cr_wr[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_wr_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\ea[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\ea_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire $0\exc_$signal$3[0:0]$3701 - attribute \src "libresoc.v:79327.3-79484.6" - wire $0\exc_$signal$4[0:0]$3702 - attribute \src "libresoc.v:79327.3-79484.6" - wire $0\exc_$signal$5[0:0]$3703 - attribute \src "libresoc.v:79327.3-79484.6" - wire $0\exc_$signal$6[0:0]$3704 - attribute \src "libresoc.v:79327.3-79484.6" - wire $0\exc_$signal$7[0:0]$3705 - attribute \src "libresoc.v:79327.3-79484.6" - wire $0\exc_$signal$8[0:0]$3706 - attribute \src "libresoc.v:79327.3-79484.6" - wire $0\exc_$signal$9[0:0]$3707 - attribute \src "libresoc.v:79327.3-79484.6" - wire $0\exc_$signal[0:0]$3700 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire $0\exc_$signal$3[0:0]$3685 + attribute \src "libresoc.v:79012.3-79169.6" + wire $0\exc_$signal$4[0:0]$3686 + attribute \src "libresoc.v:79012.3-79169.6" + wire $0\exc_$signal$5[0:0]$3687 + attribute \src "libresoc.v:79012.3-79169.6" + wire $0\exc_$signal$6[0:0]$3688 + attribute \src "libresoc.v:79012.3-79169.6" + wire $0\exc_$signal$7[0:0]$3689 + attribute \src "libresoc.v:79012.3-79169.6" + wire $0\exc_$signal$8[0:0]$3690 + attribute \src "libresoc.v:79012.3-79169.6" + wire $0\exc_$signal$9[0:0]$3691 + attribute \src "libresoc.v:79012.3-79169.6" + wire $0\exc_$signal[0:0]$3684 + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\fast1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\fast2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\fasto1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\fasto1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\fasto2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\fasto2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 14 $0\fn_unit[13:0] - attribute \src "libresoc.v:77344.7-77344.20" + attribute \src "libresoc.v:77029.7-77029.20" wire $0\initial[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 2 $0\input_carry[1:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 32 $0\insn[31:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\insn_type[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:79303.3-79326.6" + attribute \src "libresoc.v:78988.3-79011.6" wire $0\is_priv_insn[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\lk[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\oe[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\rc[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\reg1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\reg1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\reg2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\reg2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\reg3[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\reg3_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\rego[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\rego_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $0\spr1[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $0\spro[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\spro_ok[0:0] - attribute \src "libresoc.v:79229.3-79243.6" + attribute \src "libresoc.v:78914.3-78928.6" wire width 14 $0\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:79254.3-79266.6" + attribute \src "libresoc.v:78939.3-78951.6" wire width 7 $0\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:79244.3-79253.6" + attribute \src "libresoc.v:78929.3-78938.6" wire $0\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:79293.3-79302.6" + attribute \src "libresoc.v:78978.3-78987.6" wire width 13 $0\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:79267.3-79282.6" + attribute \src "libresoc.v:78952.3-78967.6" wire width 3 $0\tmp_xer_in[2:0] - attribute \src "libresoc.v:79283.3-79292.6" + attribute \src "libresoc.v:78968.3-78977.6" wire $0\tmp_xer_out[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 13 $0\trapaddr[12:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $0\traptype[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\xer_in[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $0\xer_out[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $1\cia[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\cr_in1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_in1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire width 7 $1\cr_in2$1[6:0]$3708 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire width 7 $1\cr_in2$1[6:0]$3692 + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\cr_in2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire $1\cr_in2_ok$2[0:0]$3709 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire $1\cr_in2_ok$2[0:0]$3693 + attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_in2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\cr_out[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_out_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $1\cr_rd[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_rd_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $1\cr_wr[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_wr_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\ea[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\ea_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire $1\exc_$signal$3[0:0]$3711 - attribute \src "libresoc.v:79327.3-79484.6" - wire $1\exc_$signal$4[0:0]$3712 - attribute \src "libresoc.v:79327.3-79484.6" - wire $1\exc_$signal$5[0:0]$3713 - attribute \src "libresoc.v:79327.3-79484.6" - wire $1\exc_$signal$6[0:0]$3714 - attribute \src "libresoc.v:79327.3-79484.6" - wire $1\exc_$signal$7[0:0]$3715 - attribute \src "libresoc.v:79327.3-79484.6" - wire $1\exc_$signal$8[0:0]$3716 - attribute \src "libresoc.v:79327.3-79484.6" - wire $1\exc_$signal$9[0:0]$3717 - attribute \src "libresoc.v:79327.3-79484.6" - wire $1\exc_$signal[0:0]$3710 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire $1\exc_$signal$3[0:0]$3695 + attribute \src "libresoc.v:79012.3-79169.6" + wire $1\exc_$signal$4[0:0]$3696 + attribute \src "libresoc.v:79012.3-79169.6" + wire $1\exc_$signal$5[0:0]$3697 + attribute \src "libresoc.v:79012.3-79169.6" + wire $1\exc_$signal$6[0:0]$3698 + attribute \src "libresoc.v:79012.3-79169.6" + wire $1\exc_$signal$7[0:0]$3699 + attribute \src "libresoc.v:79012.3-79169.6" + wire $1\exc_$signal$8[0:0]$3700 + attribute \src "libresoc.v:79012.3-79169.6" + wire $1\exc_$signal$9[0:0]$3701 + attribute \src "libresoc.v:79012.3-79169.6" + wire $1\exc_$signal[0:0]$3694 + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\fast1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\fast2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\fasto1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\fasto1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\fasto2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\fasto2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 14 $1\fn_unit[13:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 2 $1\input_carry[1:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 32 $1\insn[31:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\insn_type[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:79303.3-79326.6" + attribute \src "libresoc.v:78988.3-79011.6" wire $1\is_priv_insn[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\lk[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\oe[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\rc[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\rc_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\reg1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\reg1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\reg2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\reg2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\reg3[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\reg3_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\rego[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\rego_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $1\spr1[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $1\spro[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\spro_ok[0:0] - attribute \src "libresoc.v:79229.3-79243.6" + attribute \src "libresoc.v:78914.3-78928.6" wire width 14 $1\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:79254.3-79266.6" + attribute \src "libresoc.v:78939.3-78951.6" wire width 7 $1\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:79244.3-79253.6" + attribute \src "libresoc.v:78929.3-78938.6" wire $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:79293.3-79302.6" + attribute \src "libresoc.v:78978.3-78987.6" wire width 13 $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:79267.3-79282.6" + attribute \src "libresoc.v:78952.3-78967.6" wire width 3 $1\tmp_xer_in[2:0] - attribute \src "libresoc.v:79283.3-79292.6" + attribute \src "libresoc.v:78968.3-78977.6" wire $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 13 $1\trapaddr[12:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $1\traptype[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\xer_in[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $1\xer_out[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $2\cia[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\cr_in1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_in1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire width 7 $2\cr_in2$1[6:0]$3718 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire width 7 $2\cr_in2$1[6:0]$3702 + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\cr_in2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire $2\cr_in2_ok$2[0:0]$3719 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire $2\cr_in2_ok$2[0:0]$3703 + attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_in2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\cr_out[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_out_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $2\cr_rd[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_rd_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $2\cr_wr[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_wr_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\ea[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\ea_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire $2\exc_$signal$3[0:0]$3721 - attribute \src "libresoc.v:79327.3-79484.6" - wire $2\exc_$signal$4[0:0]$3722 - attribute \src "libresoc.v:79327.3-79484.6" - wire $2\exc_$signal$5[0:0]$3723 - attribute \src "libresoc.v:79327.3-79484.6" - wire $2\exc_$signal$6[0:0]$3724 - attribute \src "libresoc.v:79327.3-79484.6" - wire $2\exc_$signal$7[0:0]$3725 - attribute \src "libresoc.v:79327.3-79484.6" - wire $2\exc_$signal$8[0:0]$3726 - attribute \src "libresoc.v:79327.3-79484.6" - wire $2\exc_$signal$9[0:0]$3727 - attribute \src "libresoc.v:79327.3-79484.6" - wire $2\exc_$signal[0:0]$3720 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire $2\exc_$signal$3[0:0]$3705 + attribute \src "libresoc.v:79012.3-79169.6" + wire $2\exc_$signal$4[0:0]$3706 + attribute \src "libresoc.v:79012.3-79169.6" + wire $2\exc_$signal$5[0:0]$3707 + attribute \src "libresoc.v:79012.3-79169.6" + wire $2\exc_$signal$6[0:0]$3708 + attribute \src "libresoc.v:79012.3-79169.6" + wire $2\exc_$signal$7[0:0]$3709 + attribute \src "libresoc.v:79012.3-79169.6" + wire $2\exc_$signal$8[0:0]$3710 + attribute \src "libresoc.v:79012.3-79169.6" + wire $2\exc_$signal$9[0:0]$3711 + attribute \src "libresoc.v:79012.3-79169.6" + wire $2\exc_$signal[0:0]$3704 + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\fast1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\fast2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\fasto1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\fasto1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\fasto2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\fasto2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 14 $2\fn_unit[13:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 2 $2\input_carry[1:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 32 $2\insn[31:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\insn_type[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\is_32bit[0:0] - attribute \src "libresoc.v:79303.3-79326.6" + attribute \src "libresoc.v:78988.3-79011.6" wire $2\is_priv_insn[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\lk[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\oe[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\oe_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\rc[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\rc_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\reg1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\reg1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\reg2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\reg2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\reg3[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\reg3_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\rego[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\rego_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $2\spr1[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $2\spro[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\spro_ok[0:0] - attribute \src "libresoc.v:79267.3-79282.6" + attribute \src "libresoc.v:78952.3-78967.6" wire width 3 $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 13 $2\trapaddr[12:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $2\traptype[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\xer_in[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $2\xer_out[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $3\asmcode[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $3\cia[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\cr_in1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_in1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire width 7 $3\cr_in2$1[6:0]$3728 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire width 7 $3\cr_in2$1[6:0]$3712 + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\cr_in2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire $3\cr_in2_ok$2[0:0]$3729 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire $3\cr_in2_ok$2[0:0]$3713 + attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_in2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\cr_out[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_out_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $3\cr_rd[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_rd_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $3\cr_wr[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_wr_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\ea[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\ea_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire $3\exc_$signal$3[0:0]$3731 - attribute \src "libresoc.v:79327.3-79484.6" - wire $3\exc_$signal$4[0:0]$3732 - attribute \src "libresoc.v:79327.3-79484.6" - wire $3\exc_$signal$5[0:0]$3733 - attribute \src "libresoc.v:79327.3-79484.6" - wire $3\exc_$signal$6[0:0]$3734 - attribute \src "libresoc.v:79327.3-79484.6" - wire $3\exc_$signal$7[0:0]$3735 - attribute \src "libresoc.v:79327.3-79484.6" - wire $3\exc_$signal$8[0:0]$3736 - attribute \src "libresoc.v:79327.3-79484.6" - wire $3\exc_$signal$9[0:0]$3737 - attribute \src "libresoc.v:79327.3-79484.6" - wire $3\exc_$signal[0:0]$3730 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire $3\exc_$signal$3[0:0]$3715 + attribute \src "libresoc.v:79012.3-79169.6" + wire $3\exc_$signal$4[0:0]$3716 + attribute \src "libresoc.v:79012.3-79169.6" + wire $3\exc_$signal$5[0:0]$3717 + attribute \src "libresoc.v:79012.3-79169.6" + wire $3\exc_$signal$6[0:0]$3718 + attribute \src "libresoc.v:79012.3-79169.6" + wire $3\exc_$signal$7[0:0]$3719 + attribute \src "libresoc.v:79012.3-79169.6" + wire $3\exc_$signal$8[0:0]$3720 + attribute \src "libresoc.v:79012.3-79169.6" + wire $3\exc_$signal$9[0:0]$3721 + attribute \src "libresoc.v:79012.3-79169.6" + wire $3\exc_$signal[0:0]$3714 + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\fast1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\fast1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\fast2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\fast2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\fasto1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\fasto1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\fasto2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\fasto2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 14 $3\fn_unit[13:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 2 $3\input_carry[1:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 32 $3\insn[31:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\insn_type[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\is_32bit[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\lk[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $3\msr[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\oe[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\oe_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\rc[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\rc_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\reg1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\reg1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\reg2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\reg2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\reg3[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\reg3_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\rego[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\rego_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $3\spr1[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\spr1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $3\spro[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\spro_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 13 $3\trapaddr[12:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $3\traptype[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\xer_in[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $3\xer_out[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $4\asmcode[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $4\cia[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\cr_in1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_in1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire width 7 $4\cr_in2$1[6:0]$3738 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire width 7 $4\cr_in2$1[6:0]$3722 + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\cr_in2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire $4\cr_in2_ok$2[0:0]$3739 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire $4\cr_in2_ok$2[0:0]$3723 + attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_in2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\cr_out[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_out_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $4\cr_rd[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_rd_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $4\cr_wr[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_wr_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\ea[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\ea_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" - wire $4\exc_$signal$3[0:0]$3741 - attribute \src "libresoc.v:79327.3-79484.6" - wire $4\exc_$signal$4[0:0]$3742 - attribute \src "libresoc.v:79327.3-79484.6" - wire $4\exc_$signal$5[0:0]$3743 - attribute \src "libresoc.v:79327.3-79484.6" - wire $4\exc_$signal$6[0:0]$3744 - attribute \src "libresoc.v:79327.3-79484.6" - wire $4\exc_$signal$7[0:0]$3745 - attribute \src "libresoc.v:79327.3-79484.6" - wire $4\exc_$signal$8[0:0]$3746 - attribute \src "libresoc.v:79327.3-79484.6" - wire $4\exc_$signal$9[0:0]$3747 - attribute \src "libresoc.v:79327.3-79484.6" - wire $4\exc_$signal[0:0]$3740 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" + wire $4\exc_$signal$3[0:0]$3725 + attribute \src "libresoc.v:79012.3-79169.6" + wire $4\exc_$signal$4[0:0]$3726 + attribute \src "libresoc.v:79012.3-79169.6" + wire $4\exc_$signal$5[0:0]$3727 + attribute \src "libresoc.v:79012.3-79169.6" + wire $4\exc_$signal$6[0:0]$3728 + attribute \src "libresoc.v:79012.3-79169.6" + wire $4\exc_$signal$7[0:0]$3729 + attribute \src "libresoc.v:79012.3-79169.6" + wire $4\exc_$signal$8[0:0]$3730 + attribute \src "libresoc.v:79012.3-79169.6" + wire $4\exc_$signal$9[0:0]$3731 + attribute \src "libresoc.v:79012.3-79169.6" + wire $4\exc_$signal[0:0]$3724 + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $4\fast1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\fast1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $4\fast2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79012.3-79169.6" wire $4\fast2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src 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"libresoc.v:78759.18-78759.110" + wire $or$libresoc.v:78759$3656_Y + attribute \src "libresoc.v:78728.19-78728.124" + wire width 7 $pos$libresoc.v:78728$3623_Y + attribute \src "libresoc.v:78729.19-78729.124" + wire width 7 $pos$libresoc.v:78729$3625_Y + attribute \src "libresoc.v:78730.19-78730.123" + wire width 7 $pos$libresoc.v:78730$3627_Y + attribute \src "libresoc.v:78767.18-78767.111" + wire width 7 $pos$libresoc.v:78767$3665_Y + attribute \src "libresoc.v:78768.18-78768.111" + wire width 7 $pos$libresoc.v:78768$3667_Y + attribute \src "libresoc.v:78769.18-78769.111" + wire width 7 $pos$libresoc.v:78769$3669_Y + attribute \src "libresoc.v:78770.18-78770.113" + wire width 7 $pos$libresoc.v:78770$3671_Y + attribute \src "libresoc.v:78771.18-78771.121" + wire width 7 $pos$libresoc.v:78771$3673_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" wire \$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" wire \$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" wire \$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" wire \$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249" wire \$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250" wire \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251" wire \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252" wire \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" wire width 8 output 5 \asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" wire width 64 output 39 \cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 30 \cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 31 \cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 32 \cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 34 \cr_in2$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 35 \cr_in2_ok$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 36 \cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 37 \cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 output 59 \cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 60 \cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 output 61 \cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 62 \cr_wr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 input 64 \cur_dec @@ -124314,13 +123836,13 @@ module \dec2 wire width 3 \dec_X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_a_fast_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_a_fast_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 \dec_a_reg_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_a_reg_a_ok attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -124328,7 +123850,7 @@ module \dec2 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" wire width 3 \dec_a_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -124444,21 +123966,21 @@ module \dec2 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \dec_a_spr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_a_spr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" wire \dec_a_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_b_fast_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_b_fast_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec_b_reg_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_b_reg_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -124475,17 +123997,17 @@ module \dec2 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" wire width 4 \dec_b_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 \dec_c_reg_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_c_reg_c_ok attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" wire width 2 \dec_c_sel_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -124498,23 +124020,23 @@ module \dec2 attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_cr_in_cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_cr_in_cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_cr_in_cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_cr_in_cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_cr_in_cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_cr_in_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \dec_cr_in_cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_cr_in_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -124525,7 +124047,7 @@ module \dec2 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" wire width 3 \dec_cr_in_sel_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -124536,17 +124058,17 @@ module \dec2 attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_cr_out_cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \dec_cr_out_cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_cr_out_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:597" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -124555,7 +124077,7 @@ module \dec2 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:617" wire width 3 \dec_cr_out_sel_in attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" @@ -124688,29 +124210,29 @@ module \dec2 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1244" wire \dec_irq_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_is_32b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_o2_fast_o2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_o2_fast_o2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" wire \dec_o2_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 \dec_o2_reg_o2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_o2_reg_o2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_o_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_o_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 \dec_o_reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_o_reg_o_ok attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -124718,7 +124240,7 @@ module \dec2 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" wire width 3 \dec_o_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -124834,19 +124356,19 @@ module \dec2 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \dec_o_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_o_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in @@ -124858,9 +124380,9 @@ module \dec2 attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" @@ -124872,7 +124394,7 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" @@ -124881,9 +124403,9 @@ module \dec2 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 8 \ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 9 \ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 50 \exc_$signal @@ -124901,23 +124423,23 @@ module \dec2 wire output 56 \exc_$signal$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 57 \exc_$signal$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1214" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1243" wire \ext_irq_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 22 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 24 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 26 \fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 28 \fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \fasto2_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -124934,33 +124456,33 @@ module \dec2 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire width 14 output 42 \fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1246" wire \illeg_ok - attribute \src "libresoc.v:77344.7-77344.15" + attribute \src "libresoc.v:77029.7-77029.15" wire \initial attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" wire width 2 output 48 \input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 32 output 40 \insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:96" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" wire width 32 \insn_in$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" wire width 32 \insn_in$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" wire width 32 \insn_in$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352" wire width 32 \insn_in$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" wire width 32 \insn_in$89 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -125037,47 +124559,47 @@ module \dec2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 7 output 41 \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" wire output 63 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:53" wire \is_priv_insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" wire output 43 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 output 38 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 46 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 47 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1245" wire \priv_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 4 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 44 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 45 \rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 10 \reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 11 \reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 12 \reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 13 \reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 14 \reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 15 \reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 6 \rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 7 \rego_ok attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -125085,9 +124607,9 @@ module \dec2 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:415" wire width 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -125203,9 +124725,9 @@ module \dec2 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 output 18 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 19 \spr1_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -125321,65 +124843,65 @@ module \dec2 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 output 16 \spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 17 \spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire input 65 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" wire width 8 \tmp_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_cr_in2$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_cr_in2_ok$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \tmp_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \tmp_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \tmp_fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \tmp_fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_fasto2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_rego_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -125495,9 +125017,9 @@ module \dec2 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \tmp_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_spr1_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -125613,19 +125135,19 @@ module \dec2 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \tmp_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" wire width 64 \tmp_tmp_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \tmp_tmp_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_tmp_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \tmp_tmp_cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_tmp_cr_wr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \tmp_tmp_exc_$signal @@ -125658,15 +125180,15 @@ module \dec2 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire width 14 \tmp_tmp_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" wire width 2 \tmp_tmp_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 32 \tmp_tmp_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -125743,40 +125265,40 @@ module \dec2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 7 \tmp_tmp_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" wire \tmp_tmp_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" wire \tmp_tmp_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \tmp_tmp_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_tmp_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_tmp_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_tmp_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_tmp_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" wire width 13 \tmp_tmp_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" wire width 8 \tmp_tmp_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" wire width 3 \tmp_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" wire \tmp_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" wire width 13 output 58 \trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" wire width 8 output 49 \traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" wire width 3 output 20 \xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" wire output 21 \xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" - cell $and $and$libresoc.v:79050$3648 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249" + cell $and $and$libresoc.v:78735$3632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125784,10 +125306,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_eint connect \B \cur_msr [15] - connect \Y $and$libresoc.v:79050$3648_Y + connect \Y $and$libresoc.v:78735$3632_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1221" - cell $and $and$libresoc.v:79051$3649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250" + cell $and $and$libresoc.v:78736$3633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125795,10 +125317,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_dec [63] connect \B \cur_msr [15] - connect \Y $and$libresoc.v:79051$3649_Y + connect \Y $and$libresoc.v:78736$3633_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" - cell $and $and$libresoc.v:79052$3650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251" + cell $and $and$libresoc.v:78737$3634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125806,10 +125328,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_priv_insn connect \B \cur_msr [14] - connect \Y $and$libresoc.v:79052$3650_Y + connect \Y $and$libresoc.v:78737$3634_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:79059$3657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:78744$3641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125817,10 +125339,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$37 - connect \Y $and$libresoc.v:79059$3657_Y + connect \Y $and$libresoc.v:78744$3641_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:79060$3658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:78745$3642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125828,10 +125350,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$39 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:79060$3658_Y + connect \Y $and$libresoc.v:78745$3642_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:79062$3660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:78747$3644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125839,10 +125361,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$43 - connect \Y $and$libresoc.v:79062$3660_Y + connect \Y $and$libresoc.v:78747$3644_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:79064$3662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:78749$3646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125850,10 +125372,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:79064$3662_Y + connect \Y $and$libresoc.v:78749$3646_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:79076$3674 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:78761$3658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125861,10 +125383,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$71 - connect \Y $and$libresoc.v:79076$3674_Y + connect \Y $and$libresoc.v:78761$3658_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:79077$3675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:78762$3659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125872,10 +125394,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$73 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:79077$3675_Y + connect \Y $and$libresoc.v:78762$3659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:79079$3677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:78764$3661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125883,10 +125405,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$77 - connect \Y $and$libresoc.v:79079$3677_Y + connect \Y $and$libresoc.v:78764$3661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:79081$3679 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:78766$3663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125894,10 +125416,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 - connect \Y $and$libresoc.v:79081$3679_Y + connect \Y $and$libresoc.v:78766$3663_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189" - cell $eq $eq$libresoc.v:79046$3644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" + cell $eq $eq$libresoc.v:78731$3628 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125905,10 +125427,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:79046$3644_Y + connect \Y $eq$libresoc.v:78731$3628_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191" - cell $eq $eq$libresoc.v:79047$3645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" + cell $eq $eq$libresoc.v:78732$3629 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125916,10 +125438,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0001010 - connect \Y $eq$libresoc.v:79047$3645_Y + connect \Y $eq$libresoc.v:78732$3629_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193" - cell $eq $eq$libresoc.v:79048$3646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" + cell $eq $eq$libresoc.v:78733$3630 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125927,10 +125449,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:79048$3646_Y + connect \Y $eq$libresoc.v:78733$3630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" - cell $eq $eq$libresoc.v:79049$3647 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" + cell $eq $eq$libresoc.v:78734$3631 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125938,10 +125460,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0111111 - connect \Y $eq$libresoc.v:79049$3647_Y + connect \Y $eq$libresoc.v:78734$3631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1223" - cell $eq $eq$libresoc.v:79053$3651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252" + cell $eq $eq$libresoc.v:78738$3635 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125949,10 +125471,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0000000 - connect \Y $eq$libresoc.v:79053$3651_Y + connect \Y $eq$libresoc.v:78738$3635_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1271" - cell $eq $eq$libresoc.v:79054$3652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300" + cell $eq $eq$libresoc.v:78739$3636 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125960,10 +125482,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'0111111 - connect \Y $eq$libresoc.v:79054$3652_Y + connect \Y $eq$libresoc.v:78739$3636_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" - cell $eq $eq$libresoc.v:79055$3653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" + cell $eq $eq$libresoc.v:78740$3637 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125971,10 +125493,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1001001 - connect \Y $eq$libresoc.v:79055$3653_Y + connect \Y $eq$libresoc.v:78740$3637_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281" - cell $eq $eq$libresoc.v:79057$3655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" + cell $eq $eq$libresoc.v:78742$3639 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125982,10 +125504,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1000110 - connect \Y $eq$libresoc.v:79057$3655_Y + connect \Y $eq$libresoc.v:78742$3639_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:79058$3656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:78743$3640 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -125993,10 +125515,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:79058$3656_Y + connect \Y $eq$libresoc.v:78743$3640_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:79061$3659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:78746$3643 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -126004,10 +125526,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:79061$3659_Y + connect \Y $eq$libresoc.v:78746$3643_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:79065$3663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" + cell $eq $eq$libresoc.v:78750$3647 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -126015,10 +125537,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:79065$3663_Y + connect \Y $eq$libresoc.v:78750$3647_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:79066$3664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $eq $eq$libresoc.v:78751$3648 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -126026,10 +125548,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:79066$3664_Y + connect \Y $eq$libresoc.v:78751$3648_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:79068$3666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:78753$3650 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -126037,10 +125559,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:79068$3666_Y + connect \Y $eq$libresoc.v:78753$3650_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:79069$3667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:78754$3651 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -126048,10 +125570,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:79069$3667_Y + connect \Y $eq$libresoc.v:78754$3651_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:79071$3669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:78756$3653 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -126059,10 +125581,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:79071$3669_Y + connect \Y $eq$libresoc.v:78756$3653_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:79073$3671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $eq $eq$libresoc.v:78758$3655 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -126070,10 +125592,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:79073$3671_Y + connect \Y $eq$libresoc.v:78758$3655_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:79075$3673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:78760$3657 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -126081,10 +125603,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:79075$3673_Y + connect \Y $eq$libresoc.v:78760$3657_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:79078$3676 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:78763$3660 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -126092,90 +125614,90 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:79078$3676_Y + connect \Y $eq$libresoc.v:78763$3660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79043$3638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $extend$libresoc.v:78728$3622 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield_b - connect \Y $extend$libresoc.v:79043$3638_Y + connect \Y $extend$libresoc.v:78728$3622_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79044$3640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $extend$libresoc.v:78729$3624 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield_o - connect \Y $extend$libresoc.v:79044$3640_Y + connect \Y $extend$libresoc.v:78729$3624_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79045$3642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $extend$libresoc.v:78730$3626 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_out_cr_bitfield - connect \Y $extend$libresoc.v:79045$3642_Y + connect \Y $extend$libresoc.v:78730$3626_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79082$3680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $extend$libresoc.v:78767$3664 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_a_reg_a - connect \Y $extend$libresoc.v:79082$3680_Y + connect \Y $extend$libresoc.v:78767$3664_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79083$3682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $extend$libresoc.v:78768$3666 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_c_reg_c - connect \Y $extend$libresoc.v:79083$3682_Y + connect \Y $extend$libresoc.v:78768$3666_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79084$3684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $extend$libresoc.v:78769$3668 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_o_reg_o - connect \Y $extend$libresoc.v:79084$3684_Y + connect \Y $extend$libresoc.v:78769$3668_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79085$3686 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $extend$libresoc.v:78770$3670 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_o2_reg_o2 - connect \Y $extend$libresoc.v:79085$3686_Y + connect \Y $extend$libresoc.v:78770$3670_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79086$3688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $extend$libresoc.v:78771$3672 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield - connect \Y $extend$libresoc.v:79086$3688_Y + connect \Y $extend$libresoc.v:78771$3672_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:79063$3661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:78748$3645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:79063$3661_Y + connect \Y $not$libresoc.v:78748$3645_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:79080$3678 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:78765$3662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:79080$3678_Y + connect \Y $not$libresoc.v:78765$3662_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" - cell $or $or$libresoc.v:79056$3654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" + cell $or $or$libresoc.v:78741$3638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -126183,10 +125705,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$28 connect \B \$30 - connect \Y $or$libresoc.v:79056$3654_Y + connect \Y $or$libresoc.v:78741$3638_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:79067$3665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $or $or$libresoc.v:78752$3649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -126194,10 +125716,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:79067$3665_Y + connect \Y $or$libresoc.v:78752$3649_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:79070$3668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:78755$3652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -126205,10 +125727,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$57 connect \B \$59 - connect \Y $or$libresoc.v:79070$3668_Y + connect \Y $or$libresoc.v:78755$3652_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:79072$3670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:78757$3654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -126216,10 +125738,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$61 connect \B \$63 - connect \Y $or$libresoc.v:79072$3670_Y + connect \Y $or$libresoc.v:78757$3654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:79074$3672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $or $or$libresoc.v:78759$3656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -126227,74 +125749,74 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$65 connect \B \$67 - connect \Y $or$libresoc.v:79074$3672_Y + connect \Y $or$libresoc.v:78759$3656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79043$3639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $pos$libresoc.v:78728$3623 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79043$3638_Y - connect \Y $pos$libresoc.v:79043$3639_Y + connect \A $extend$libresoc.v:78728$3622_Y + connect \Y $pos$libresoc.v:78728$3623_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79044$3641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $pos$libresoc.v:78729$3625 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79044$3640_Y - connect \Y $pos$libresoc.v:79044$3641_Y + connect \A $extend$libresoc.v:78729$3624_Y + connect \Y $pos$libresoc.v:78729$3625_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79045$3643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $pos$libresoc.v:78730$3627 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79045$3642_Y - connect \Y $pos$libresoc.v:79045$3643_Y + connect \A $extend$libresoc.v:78730$3626_Y + connect \Y $pos$libresoc.v:78730$3627_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79082$3681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $pos$libresoc.v:78767$3665 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79082$3680_Y - connect \Y $pos$libresoc.v:79082$3681_Y + connect \A $extend$libresoc.v:78767$3664_Y + connect \Y $pos$libresoc.v:78767$3665_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79083$3683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $pos$libresoc.v:78768$3667 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79083$3682_Y - connect \Y $pos$libresoc.v:79083$3683_Y + connect \A $extend$libresoc.v:78768$3666_Y + connect \Y $pos$libresoc.v:78768$3667_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79084$3685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $pos$libresoc.v:78769$3669 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79084$3684_Y - connect \Y $pos$libresoc.v:79084$3685_Y + connect \A $extend$libresoc.v:78769$3668_Y + connect \Y $pos$libresoc.v:78769$3669_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79085$3687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $pos$libresoc.v:78770$3671 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79085$3686_Y - connect \Y $pos$libresoc.v:79085$3687_Y + connect \A $extend$libresoc.v:78770$3670_Y + connect \Y $pos$libresoc.v:78770$3671_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79086$3689 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $pos$libresoc.v:78771$3673 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79086$3688_Y - connect \Y $pos$libresoc.v:79086$3689_Y + connect \A $extend$libresoc.v:78771$3672_Y + connect \Y $pos$libresoc.v:78771$3673_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:79087.13-79124.4" + attribute \src "libresoc.v:78772.13-78809.4" cell \dec$171 \dec connect \BA \dec_BA connect \BB \dec_BB @@ -126334,7 +125856,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:79125.9-79140.4" + attribute \src "libresoc.v:78810.9-78825.4" cell \dec_a \dec_a connect \BO \dec_BO connect \RA \dec_RA @@ -126352,7 +125874,7 @@ module \dec2 connect \sv_nz \dec_a_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:79141.9-79151.4" + attribute \src "libresoc.v:78826.9-78836.4" cell \dec_b \dec_b connect \RB \dec_RB connect \RS \dec_RS @@ -126365,7 +125887,7 @@ module \dec2 connect \sel_in \dec_b_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79152.9-79158.4" + attribute \src "libresoc.v:78837.9-78843.4" cell \dec_c \dec_c connect \RB \dec_RB connect \RS \dec_RS @@ -126374,7 +125896,7 @@ module \dec2 connect \sel_in \dec_c_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79159.13-79178.4" + attribute \src "libresoc.v:78844.13-78863.4" cell \dec_cr_in \dec_cr_in$10 connect \BA \dec_BA connect \BB \dec_BB @@ -126396,7 +125918,7 @@ module \dec2 connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79179.14-79191.4" + attribute \src "libresoc.v:78864.14-78876.4" cell \dec_cr_out \dec_cr_out$11 connect \FXM \dec_FXM connect \XL_BT \dec_XL_BT @@ -126411,7 +125933,7 @@ module \dec2 connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79192.9-79205.4" + attribute \src "libresoc.v:78877.9-78890.4" cell \dec_o \dec_o connect \BO \dec_BO connect \RA \dec_RA @@ -126427,7 +125949,7 @@ module \dec2 connect \spr_o_ok \dec_o_spr_o_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:79206.10-79215.4" + attribute \src "libresoc.v:78891.10-78900.4" cell \dec_o2 \dec_o2 connect \RA \dec_RA connect \fast_o2 \dec_o2_fast_o2 @@ -126439,7 +125961,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:79216.16-79222.4" + attribute \src "libresoc.v:78901.16-78907.4" cell \dec_oe$173 \dec_oe connect \OE \dec_OE connect \internal_op \dec_internal_op @@ -126448,32 +125970,32 @@ module \dec2 connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79223.16-79228.4" + attribute \src "libresoc.v:78908.16-78913.4" cell \dec_rc$172 \dec_rc connect \Rc \dec_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:77344.7-77344.20" - process $proc$libresoc.v:77344$3748 + attribute \src "libresoc.v:77029.7-77029.20" + process $proc$libresoc.v:77029$3732 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:79229.3-79243.6" - process $proc$libresoc.v:79229$3690 + attribute \src "libresoc.v:78914.3-78928.6" + process $proc$libresoc.v:78914$3674 assign { } { } assign $0\tmp_tmp_fn_unit[13:0] $1\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:79230.5-79230.29" + attribute \src "libresoc.v:78915.5-78915.29" switch \initial - attribute \src "libresoc.v:79230.9-79230.17" + attribute \src "libresoc.v:78915.9-78915.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$83 \$75 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -126491,18 +126013,18 @@ module \dec2 sync always update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[13:0] end - attribute \src "libresoc.v:79244.3-79253.6" - process $proc$libresoc.v:79244$3691 + attribute \src "libresoc.v:78929.3-78938.6" + process $proc$libresoc.v:78929$3675 assign { } { } assign { } { } assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:79245.5-79245.29" + attribute \src "libresoc.v:78930.5-78930.29" switch \initial - attribute \src "libresoc.v:79245.9-79245.17" + attribute \src "libresoc.v:78930.9-78930.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:870" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" switch \dec_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126514,18 +126036,18 @@ module \dec2 sync always update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] end - attribute \src "libresoc.v:79254.3-79266.6" - process $proc$libresoc.v:79254$3692 + attribute \src "libresoc.v:78939.3-78951.6" + process $proc$libresoc.v:78939$3676 assign { } { } assign { } { } assign $0\tmp_tmp_insn_type[6:0] $1\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:79255.5-79255.29" + attribute \src "libresoc.v:78940.5-78940.29" switch \initial - attribute \src "libresoc.v:79255.9-79255.17" + attribute \src "libresoc.v:78940.9-78940.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$49 \$41 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -126541,19 +126063,19 @@ module \dec2 sync always update \tmp_tmp_insn_type $0\tmp_tmp_insn_type[6:0] end - attribute \src "libresoc.v:79267.3-79282.6" - process $proc$libresoc.v:79267$3693 + attribute \src "libresoc.v:78952.3-78967.6" + process $proc$libresoc.v:78952$3677 assign { } { } assign { } { } assign { } { } assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:79268.5-79268.29" + attribute \src "libresoc.v:78953.5-78953.29" switch \initial - attribute \src "libresoc.v:79268.9-79268.17" + attribute \src "libresoc.v:78953.9-78953.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" switch \$106 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126562,7 +126084,7 @@ module \dec2 case assign $1\tmp_xer_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" switch \$108 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126574,18 +126096,18 @@ module \dec2 sync always update \tmp_xer_in $0\tmp_xer_in[2:0] end - attribute \src "libresoc.v:79283.3-79292.6" - process $proc$libresoc.v:79283$3694 + attribute \src "libresoc.v:78968.3-78977.6" + process $proc$libresoc.v:78968$3678 assign { } { } assign { } { } assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:79284.5-79284.29" + attribute \src "libresoc.v:78969.5-78969.29" switch \initial - attribute \src "libresoc.v:79284.9-79284.17" + attribute \src "libresoc.v:78969.9-78969.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" switch \$110 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126597,18 +126119,18 @@ module \dec2 sync always update \tmp_xer_out $0\tmp_xer_out[0:0] end - attribute \src "libresoc.v:79293.3-79302.6" - process $proc$libresoc.v:79293$3695 + attribute \src "libresoc.v:78978.3-78987.6" + process $proc$libresoc.v:78978$3679 assign { } { } assign { } { } assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:79294.5-79294.29" + attribute \src "libresoc.v:78979.5-78979.29" switch \initial - attribute \src "libresoc.v:79294.9-79294.17" + attribute \src "libresoc.v:78979.9-78979.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" switch \$112 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126620,18 +126142,18 @@ module \dec2 sync always update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] end - attribute \src "libresoc.v:79303.3-79326.6" - process $proc$libresoc.v:79303$3696 + attribute \src "libresoc.v:78988.3-79011.6" + process $proc$libresoc.v:78988$3680 assign { } { } assign { } { } assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] - attribute \src "libresoc.v:79304.5-79304.29" + attribute \src "libresoc.v:78989.5-78989.29" switch \initial - attribute \src "libresoc.v:79304.9-79304.17" + attribute \src "libresoc.v:78989.9-78989.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54" switch \dec_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 @@ -126645,7 +126167,7 @@ module \dec2 case 7'0101110 , 7'0110001 assign { } { } assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" switch \tmp_tmp_insn [20] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126660,8 +126182,8 @@ module \dec2 sync always update \is_priv_insn $0\is_priv_insn[0:0] end - attribute \src "libresoc.v:79327.3-79484.6" - process $proc$libresoc.v:79327$3697 + attribute \src "libresoc.v:79012.3-79169.6" + process $proc$libresoc.v:79012$3681 assign { } { } assign { } { } assign { } { } @@ -126738,22 +126260,22 @@ module \dec2 assign $0\cr_in1[6:0] $1\cr_in1[6:0] assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] assign $0\cr_in2[6:0] $1\cr_in2[6:0] - assign $0\cr_in2$1[6:0]$3698 $1\cr_in2$1[6:0]$3708 + assign $0\cr_in2$1[6:0]$3682 $1\cr_in2$1[6:0]$3692 assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] - assign $0\cr_in2_ok$2[0:0]$3699 $1\cr_in2_ok$2[0:0]$3709 + assign $0\cr_in2_ok$2[0:0]$3683 $1\cr_in2_ok$2[0:0]$3693 assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] assign $0\cr_rd[7:0] $1\cr_rd[7:0] assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] assign $0\cr_wr[7:0] $1\cr_wr[7:0] assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] - assign $0\exc_$signal[0:0]$3700 $1\exc_$signal[0:0]$3710 - assign $0\exc_$signal$3[0:0]$3701 $1\exc_$signal$3[0:0]$3711 - assign $0\exc_$signal$4[0:0]$3702 $1\exc_$signal$4[0:0]$3712 - assign $0\exc_$signal$5[0:0]$3703 $1\exc_$signal$5[0:0]$3713 - assign $0\exc_$signal$6[0:0]$3704 $1\exc_$signal$6[0:0]$3714 - assign $0\exc_$signal$7[0:0]$3705 $1\exc_$signal$7[0:0]$3715 - assign $0\exc_$signal$8[0:0]$3706 $1\exc_$signal$8[0:0]$3716 - assign $0\exc_$signal$9[0:0]$3707 $1\exc_$signal$9[0:0]$3717 + assign $0\exc_$signal[0:0]$3684 $1\exc_$signal[0:0]$3694 + assign $0\exc_$signal$3[0:0]$3685 $1\exc_$signal$3[0:0]$3695 + assign $0\exc_$signal$4[0:0]$3686 $1\exc_$signal$4[0:0]$3696 + assign $0\exc_$signal$5[0:0]$3687 $1\exc_$signal$5[0:0]$3697 + assign $0\exc_$signal$6[0:0]$3688 $1\exc_$signal$6[0:0]$3698 + assign $0\exc_$signal$7[0:0]$3689 $1\exc_$signal$7[0:0]$3699 + assign $0\exc_$signal$8[0:0]$3690 $1\exc_$signal$8[0:0]$3700 + assign $0\exc_$signal$9[0:0]$3691 $1\exc_$signal$9[0:0]$3701 assign { } { } assign { } { } assign { } { } @@ -126789,13 +126311,13 @@ module \dec2 assign $0\fast2[2:0] $5\fast2[2:0] assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] assign $0\asmcode[7:0] \dec_asmcode - attribute \src "libresoc.v:79328.5-79328.29" + attribute \src "libresoc.v:79013.5-79013.29" switch \initial - attribute \src "libresoc.v:79328.9-79328.17" + attribute \src "libresoc.v:79013.9-79013.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1256" switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } attribute \src "libresoc.v:0.0-0.0" case 5'----1 @@ -126875,22 +126397,22 @@ module \dec2 assign $1\cr_in1[6:0] $2\cr_in1[6:0] assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0] assign $1\cr_in2[6:0] $2\cr_in2[6:0] - assign $1\cr_in2$1[6:0]$3708 $2\cr_in2$1[6:0]$3718 + assign $1\cr_in2$1[6:0]$3692 $2\cr_in2$1[6:0]$3702 assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0] - assign $1\cr_in2_ok$2[0:0]$3709 $2\cr_in2_ok$2[0:0]$3719 + assign $1\cr_in2_ok$2[0:0]$3693 $2\cr_in2_ok$2[0:0]$3703 assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0] assign $1\cr_rd[7:0] $2\cr_rd[7:0] assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0] assign $1\cr_wr[7:0] $2\cr_wr[7:0] assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0] - assign $1\exc_$signal[0:0]$3710 $2\exc_$signal[0:0]$3720 - assign $1\exc_$signal$3[0:0]$3711 $2\exc_$signal$3[0:0]$3721 - assign $1\exc_$signal$4[0:0]$3712 $2\exc_$signal$4[0:0]$3722 - assign $1\exc_$signal$5[0:0]$3713 $2\exc_$signal$5[0:0]$3723 - assign $1\exc_$signal$6[0:0]$3714 $2\exc_$signal$6[0:0]$3724 - assign $1\exc_$signal$7[0:0]$3715 $2\exc_$signal$7[0:0]$3725 - assign $1\exc_$signal$8[0:0]$3716 $2\exc_$signal$8[0:0]$3726 - assign $1\exc_$signal$9[0:0]$3717 $2\exc_$signal$9[0:0]$3727 + assign $1\exc_$signal[0:0]$3694 $2\exc_$signal[0:0]$3704 + assign $1\exc_$signal$3[0:0]$3695 $2\exc_$signal$3[0:0]$3705 + assign $1\exc_$signal$4[0:0]$3696 $2\exc_$signal$4[0:0]$3706 + assign $1\exc_$signal$5[0:0]$3697 $2\exc_$signal$5[0:0]$3707 + assign $1\exc_$signal$6[0:0]$3698 $2\exc_$signal$6[0:0]$3708 + assign $1\exc_$signal$7[0:0]$3699 $2\exc_$signal$7[0:0]$3709 + assign $1\exc_$signal$8[0:0]$3700 $2\exc_$signal$8[0:0]$3710 + assign $1\exc_$signal$9[0:0]$3701 $2\exc_$signal$9[0:0]$3711 assign $1\fasto1[2:0] $2\fasto1[2:0] assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] assign $1\fasto2[2:0] $2\fasto2[2:0] @@ -126917,7 +126439,7 @@ module \dec2 assign $1\traptype[7:0] $2\traptype[7:0] assign $1\xer_in[2:0] $2\xer_in[2:0] assign $1\xer_out[0:0] $2\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1228" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1257" switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -126980,7 +126502,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3727 $2\exc_$signal$8[0:0]$3726 $2\exc_$signal$7[0:0]$3725 $2\exc_$signal$6[0:0]$3724 $2\exc_$signal$5[0:0]$3723 $2\exc_$signal$4[0:0]$3722 $2\exc_$signal$3[0:0]$3721 $2\exc_$signal[0:0]$3720 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3719 $2\cr_in2$1[6:0]$3718 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3711 $2\exc_$signal$8[0:0]$3710 $2\exc_$signal$7[0:0]$3709 $2\exc_$signal$6[0:0]$3708 $2\exc_$signal$5[0:0]$3707 $2\exc_$signal$4[0:0]$3706 $2\exc_$signal$3[0:0]$3705 $2\exc_$signal[0:0]$3704 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3703 $2\cr_in2$1[6:0]$3702 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $2\insn[31:0] \dec_opcode_in assign $2\insn_type[6:0] 7'0111111 assign $2\fn_unit[13:0] 14'00000010000000 @@ -127066,22 +126588,22 @@ module \dec2 assign $2\cr_in1[6:0] $3\cr_in1[6:0] assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0] assign $2\cr_in2[6:0] $3\cr_in2[6:0] - assign $2\cr_in2$1[6:0]$3718 $3\cr_in2$1[6:0]$3728 + assign $2\cr_in2$1[6:0]$3702 $3\cr_in2$1[6:0]$3712 assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0] - assign $2\cr_in2_ok$2[0:0]$3719 $3\cr_in2_ok$2[0:0]$3729 + assign $2\cr_in2_ok$2[0:0]$3703 $3\cr_in2_ok$2[0:0]$3713 assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0] assign $2\cr_rd[7:0] $3\cr_rd[7:0] assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0] assign $2\cr_wr[7:0] $3\cr_wr[7:0] assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0] - assign $2\exc_$signal[0:0]$3720 $3\exc_$signal[0:0]$3730 - assign $2\exc_$signal$3[0:0]$3721 $3\exc_$signal$3[0:0]$3731 - assign $2\exc_$signal$4[0:0]$3722 $3\exc_$signal$4[0:0]$3732 - assign $2\exc_$signal$5[0:0]$3723 $3\exc_$signal$5[0:0]$3733 - assign $2\exc_$signal$6[0:0]$3724 $3\exc_$signal$6[0:0]$3734 - assign $2\exc_$signal$7[0:0]$3725 $3\exc_$signal$7[0:0]$3735 - assign $2\exc_$signal$8[0:0]$3726 $3\exc_$signal$8[0:0]$3736 - assign $2\exc_$signal$9[0:0]$3727 $3\exc_$signal$9[0:0]$3737 + assign $2\exc_$signal[0:0]$3704 $3\exc_$signal[0:0]$3714 + assign $2\exc_$signal$3[0:0]$3705 $3\exc_$signal$3[0:0]$3715 + assign $2\exc_$signal$4[0:0]$3706 $3\exc_$signal$4[0:0]$3716 + assign $2\exc_$signal$5[0:0]$3707 $3\exc_$signal$5[0:0]$3717 + assign $2\exc_$signal$6[0:0]$3708 $3\exc_$signal$6[0:0]$3718 + assign $2\exc_$signal$7[0:0]$3709 $3\exc_$signal$7[0:0]$3719 + assign $2\exc_$signal$8[0:0]$3710 $3\exc_$signal$8[0:0]$3720 + assign $2\exc_$signal$9[0:0]$3711 $3\exc_$signal$9[0:0]$3721 assign $2\fasto1[2:0] $3\fasto1[2:0] assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] assign $2\fasto2[2:0] $3\fasto2[2:0] @@ -127108,7 +126630,7 @@ module \dec2 assign $2\traptype[7:0] $3\traptype[7:0] assign $2\xer_in[2:0] $3\xer_in[2:0] assign $2\xer_out[0:0] $3\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" switch \dec2_exc_$signal$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -127171,7 +126693,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3737 $3\exc_$signal$8[0:0]$3736 $3\exc_$signal$7[0:0]$3735 $3\exc_$signal$6[0:0]$3734 $3\exc_$signal$5[0:0]$3733 $3\exc_$signal$4[0:0]$3732 $3\exc_$signal$3[0:0]$3731 $3\exc_$signal[0:0]$3730 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3729 $3\cr_in2$1[6:0]$3728 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3721 $3\exc_$signal$8[0:0]$3720 $3\exc_$signal$7[0:0]$3719 $3\exc_$signal$6[0:0]$3718 $3\exc_$signal$5[0:0]$3717 $3\exc_$signal$4[0:0]$3716 $3\exc_$signal$3[0:0]$3715 $3\exc_$signal[0:0]$3714 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3713 $3\cr_in2$1[6:0]$3712 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $3\insn[31:0] \dec_opcode_in assign $3\insn_type[6:0] 7'0111111 assign $3\fn_unit[13:0] 14'00000010000000 @@ -127240,13 +126762,13 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3729 $3\cr_in2$1[6:0]$3728 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3713 $3\cr_in2$1[6:0]$3712 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $3\insn[31:0] \dec_opcode_in assign $3\insn_type[6:0] 7'0111111 assign $3\fn_unit[13:0] 14'00000010000000 assign $3\trapaddr[12:0] 13'0000001000000 assign $3\traptype[7:0] 8'01000000 - assign { $3\exc_$signal$9[0:0]$3737 $3\exc_$signal$8[0:0]$3736 $3\exc_$signal$7[0:0]$3735 $3\exc_$signal$6[0:0]$3734 $3\exc_$signal$5[0:0]$3733 $3\exc_$signal$4[0:0]$3732 $3\exc_$signal$3[0:0]$3731 $3\exc_$signal[0:0]$3730 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } + assign { $3\exc_$signal$9[0:0]$3721 $3\exc_$signal$8[0:0]$3720 $3\exc_$signal$7[0:0]$3719 $3\exc_$signal$6[0:0]$3718 $3\exc_$signal$5[0:0]$3717 $3\exc_$signal$4[0:0]$3716 $3\exc_$signal$3[0:0]$3715 $3\exc_$signal[0:0]$3714 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } assign $3\msr[63:0] \cur_msr assign $3\cia[63:0] \cur_pc end @@ -127328,22 +126850,22 @@ module \dec2 assign $2\cr_in1[6:0] $4\cr_in1[6:0] assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0] assign $2\cr_in2[6:0] $4\cr_in2[6:0] - assign $2\cr_in2$1[6:0]$3718 $4\cr_in2$1[6:0]$3738 + assign $2\cr_in2$1[6:0]$3702 $4\cr_in2$1[6:0]$3722 assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0] - assign $2\cr_in2_ok$2[0:0]$3719 $4\cr_in2_ok$2[0:0]$3739 + assign $2\cr_in2_ok$2[0:0]$3703 $4\cr_in2_ok$2[0:0]$3723 assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0] assign $2\cr_rd[7:0] $4\cr_rd[7:0] assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0] assign $2\cr_wr[7:0] $4\cr_wr[7:0] assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0] - assign $2\exc_$signal[0:0]$3720 $4\exc_$signal[0:0]$3740 - assign $2\exc_$signal$3[0:0]$3721 $4\exc_$signal$3[0:0]$3741 - assign $2\exc_$signal$4[0:0]$3722 $4\exc_$signal$4[0:0]$3742 - assign $2\exc_$signal$5[0:0]$3723 $4\exc_$signal$5[0:0]$3743 - assign $2\exc_$signal$6[0:0]$3724 $4\exc_$signal$6[0:0]$3744 - assign $2\exc_$signal$7[0:0]$3725 $4\exc_$signal$7[0:0]$3745 - assign $2\exc_$signal$8[0:0]$3726 $4\exc_$signal$8[0:0]$3746 - assign $2\exc_$signal$9[0:0]$3727 $4\exc_$signal$9[0:0]$3747 + assign $2\exc_$signal[0:0]$3704 $4\exc_$signal[0:0]$3724 + assign $2\exc_$signal$3[0:0]$3705 $4\exc_$signal$3[0:0]$3725 + assign $2\exc_$signal$4[0:0]$3706 $4\exc_$signal$4[0:0]$3726 + assign $2\exc_$signal$5[0:0]$3707 $4\exc_$signal$5[0:0]$3727 + assign $2\exc_$signal$6[0:0]$3708 $4\exc_$signal$6[0:0]$3728 + assign $2\exc_$signal$7[0:0]$3709 $4\exc_$signal$7[0:0]$3729 + assign $2\exc_$signal$8[0:0]$3710 $4\exc_$signal$8[0:0]$3730 + assign $2\exc_$signal$9[0:0]$3711 $4\exc_$signal$9[0:0]$3731 assign $2\fasto1[2:0] $4\fasto1[2:0] assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] assign $2\fasto2[2:0] $4\fasto2[2:0] @@ -127370,7 +126892,7 @@ module \dec2 assign $2\traptype[7:0] $4\traptype[7:0] assign $2\xer_in[2:0] $4\xer_in[2:0] assign $2\xer_out[0:0] $4\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1237" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1266" switch \dec2_exc_$signal$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -127433,7 +126955,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3747 $4\exc_$signal$8[0:0]$3746 $4\exc_$signal$7[0:0]$3745 $4\exc_$signal$6[0:0]$3744 $4\exc_$signal$5[0:0]$3743 $4\exc_$signal$4[0:0]$3742 $4\exc_$signal$3[0:0]$3741 $4\exc_$signal[0:0]$3740 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3739 $4\cr_in2$1[6:0]$3738 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3731 $4\exc_$signal$8[0:0]$3730 $4\exc_$signal$7[0:0]$3729 $4\exc_$signal$6[0:0]$3728 $4\exc_$signal$5[0:0]$3727 $4\exc_$signal$4[0:0]$3726 $4\exc_$signal$3[0:0]$3725 $4\exc_$signal[0:0]$3724 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3723 $4\cr_in2$1[6:0]$3722 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $4\insn[31:0] \dec_opcode_in assign $4\insn_type[6:0] 7'0111111 assign $4\fn_unit[13:0] 14'00000010000000 @@ -127502,7 +127024,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3747 $4\exc_$signal$8[0:0]$3746 $4\exc_$signal$7[0:0]$3745 $4\exc_$signal$6[0:0]$3744 $4\exc_$signal$5[0:0]$3743 $4\exc_$signal$4[0:0]$3742 $4\exc_$signal$3[0:0]$3741 $4\exc_$signal[0:0]$3740 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3739 $4\cr_in2$1[6:0]$3738 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3731 $4\exc_$signal$8[0:0]$3730 $4\exc_$signal$7[0:0]$3729 $4\exc_$signal$6[0:0]$3728 $4\exc_$signal$5[0:0]$3727 $4\exc_$signal$4[0:0]$3726 $4\exc_$signal$3[0:0]$3725 $4\exc_$signal[0:0]$3724 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3723 $4\cr_in2$1[6:0]$3722 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $4\insn[31:0] \dec_opcode_in assign $4\insn_type[6:0] 7'0111111 assign $4\fn_unit[13:0] 14'00000010000000 @@ -127573,7 +127095,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 @@ -127642,7 +127164,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 @@ -127711,7 +127233,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 @@ -127780,7 +127302,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 @@ -127849,9 +127371,9 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[13:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[13:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" switch \$32 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -127869,7 +127391,7 @@ module \dec2 assign $5\fasto2[2:0] $1\fasto2[2:0] assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" switch \$34 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -127905,22 +127427,22 @@ module \dec2 update \cr_in1 $0\cr_in1[6:0] update \cr_in1_ok $0\cr_in1_ok[0:0] update \cr_in2 $0\cr_in2[6:0] - update \cr_in2$1 $0\cr_in2$1[6:0]$3698 + update \cr_in2$1 $0\cr_in2$1[6:0]$3682 update \cr_in2_ok $0\cr_in2_ok[0:0] - update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3699 + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3683 update \cr_out_ok $0\cr_out_ok[0:0] update \cr_rd $0\cr_rd[7:0] update \cr_rd_ok $0\cr_rd_ok[0:0] update \cr_wr $0\cr_wr[7:0] update \cr_wr_ok $0\cr_wr_ok[0:0] - update \exc_$signal $0\exc_$signal[0:0]$3700 - update \exc_$signal$3 $0\exc_$signal$3[0:0]$3701 - update \exc_$signal$4 $0\exc_$signal$4[0:0]$3702 - update \exc_$signal$5 $0\exc_$signal$5[0:0]$3703 - update \exc_$signal$6 $0\exc_$signal$6[0:0]$3704 - update \exc_$signal$7 $0\exc_$signal$7[0:0]$3705 - update \exc_$signal$8 $0\exc_$signal$8[0:0]$3706 - update \exc_$signal$9 $0\exc_$signal$9[0:0]$3707 + update \exc_$signal $0\exc_$signal[0:0]$3684 + update \exc_$signal$3 $0\exc_$signal$3[0:0]$3685 + update \exc_$signal$4 $0\exc_$signal$4[0:0]$3686 + update \exc_$signal$5 $0\exc_$signal$5[0:0]$3687 + update \exc_$signal$6 $0\exc_$signal$6[0:0]$3688 + update \exc_$signal$7 $0\exc_$signal$7[0:0]$3689 + update \exc_$signal$8 $0\exc_$signal$8[0:0]$3690 + update \exc_$signal$9 $0\exc_$signal$9[0:0]$3691 update \fasto1 $0\fasto1[2:0] update \fasto1_ok $0\fasto1_ok[0:0] update \fasto2 $0\fasto2[2:0] @@ -127948,50 +127470,50 @@ module \dec2 update \xer_in $0\xer_in[2:0] update \xer_out $0\xer_out[0:0] end - connect \$100 $pos$libresoc.v:79043$3639_Y - connect \$102 $pos$libresoc.v:79044$3641_Y - connect \$104 $pos$libresoc.v:79045$3643_Y - connect \$106 $eq$libresoc.v:79046$3644_Y - connect \$108 $eq$libresoc.v:79047$3645_Y - connect \$110 $eq$libresoc.v:79048$3646_Y - connect \$112 $eq$libresoc.v:79049$3647_Y - connect \$114 $and$libresoc.v:79050$3648_Y - connect \$116 $and$libresoc.v:79051$3649_Y - connect \$118 $and$libresoc.v:79052$3650_Y - connect \$120 $eq$libresoc.v:79053$3651_Y - connect \$28 $eq$libresoc.v:79054$3652_Y - connect \$30 $eq$libresoc.v:79055$3653_Y - connect \$32 $or$libresoc.v:79056$3654_Y - connect \$34 $eq$libresoc.v:79057$3655_Y - connect \$37 $eq$libresoc.v:79058$3656_Y - connect \$39 $and$libresoc.v:79059$3657_Y - connect \$41 $and$libresoc.v:79060$3658_Y - connect \$43 $eq$libresoc.v:79061$3659_Y - connect \$45 $and$libresoc.v:79062$3660_Y - connect \$47 $not$libresoc.v:79063$3661_Y - connect \$49 $and$libresoc.v:79064$3662_Y - connect \$51 $eq$libresoc.v:79065$3663_Y - connect \$53 $eq$libresoc.v:79066$3664_Y - connect \$55 $or$libresoc.v:79067$3665_Y - connect \$57 $eq$libresoc.v:79068$3666_Y - connect \$59 $eq$libresoc.v:79069$3667_Y - connect \$61 $or$libresoc.v:79070$3668_Y - connect \$63 $eq$libresoc.v:79071$3669_Y - connect \$65 $or$libresoc.v:79072$3670_Y - connect \$67 $eq$libresoc.v:79073$3671_Y - connect \$69 $or$libresoc.v:79074$3672_Y - connect \$71 $eq$libresoc.v:79075$3673_Y - connect \$73 $and$libresoc.v:79076$3674_Y - connect \$75 $and$libresoc.v:79077$3675_Y - connect \$77 $eq$libresoc.v:79078$3676_Y - connect \$79 $and$libresoc.v:79079$3677_Y - connect \$81 $not$libresoc.v:79080$3678_Y - connect \$83 $and$libresoc.v:79081$3679_Y - connect \$90 $pos$libresoc.v:79082$3681_Y - connect \$92 $pos$libresoc.v:79083$3683_Y - connect \$94 $pos$libresoc.v:79084$3685_Y - connect \$96 $pos$libresoc.v:79085$3687_Y - connect \$98 $pos$libresoc.v:79086$3689_Y + connect \$100 $pos$libresoc.v:78728$3623_Y + connect \$102 $pos$libresoc.v:78729$3625_Y + connect \$104 $pos$libresoc.v:78730$3627_Y + connect \$106 $eq$libresoc.v:78731$3628_Y + connect \$108 $eq$libresoc.v:78732$3629_Y + connect \$110 $eq$libresoc.v:78733$3630_Y + connect \$112 $eq$libresoc.v:78734$3631_Y + connect \$114 $and$libresoc.v:78735$3632_Y + connect \$116 $and$libresoc.v:78736$3633_Y + connect \$118 $and$libresoc.v:78737$3634_Y + connect \$120 $eq$libresoc.v:78738$3635_Y + connect \$28 $eq$libresoc.v:78739$3636_Y + connect \$30 $eq$libresoc.v:78740$3637_Y + connect \$32 $or$libresoc.v:78741$3638_Y + connect \$34 $eq$libresoc.v:78742$3639_Y + connect \$37 $eq$libresoc.v:78743$3640_Y + connect \$39 $and$libresoc.v:78744$3641_Y + connect \$41 $and$libresoc.v:78745$3642_Y + connect \$43 $eq$libresoc.v:78746$3643_Y + connect \$45 $and$libresoc.v:78747$3644_Y + connect \$47 $not$libresoc.v:78748$3645_Y + connect \$49 $and$libresoc.v:78749$3646_Y + connect \$51 $eq$libresoc.v:78750$3647_Y + connect \$53 $eq$libresoc.v:78751$3648_Y + connect \$55 $or$libresoc.v:78752$3649_Y + connect \$57 $eq$libresoc.v:78753$3650_Y + connect \$59 $eq$libresoc.v:78754$3651_Y + connect \$61 $or$libresoc.v:78755$3652_Y + connect \$63 $eq$libresoc.v:78756$3653_Y + connect \$65 $or$libresoc.v:78757$3654_Y + connect \$67 $eq$libresoc.v:78758$3655_Y + connect \$69 $or$libresoc.v:78759$3656_Y + connect \$71 $eq$libresoc.v:78760$3657_Y + connect \$73 $and$libresoc.v:78761$3658_Y + connect \$75 $and$libresoc.v:78762$3659_Y + connect \$77 $eq$libresoc.v:78763$3660_Y + connect \$79 $and$libresoc.v:78764$3661_Y + connect \$81 $not$libresoc.v:78765$3662_Y + connect \$83 $and$libresoc.v:78766$3663_Y + connect \$90 $pos$libresoc.v:78767$3665_Y + connect \$92 $pos$libresoc.v:78768$3667_Y + connect \$94 $pos$libresoc.v:78769$3669_Y + connect \$96 $pos$libresoc.v:78770$3671_Y + connect \$98 $pos$libresoc.v:78771$3673_Y connect \dec2_exc_$signal 1'0 connect \dec2_exc_$signal$12 1'0 connect \dec2_exc_$signal$13 1'0 @@ -128072,144 +127594,144 @@ module \dec2 connect \insn_in$36 \dec_opcode_in connect \insn_in \dec_opcode_in end -attribute \src "libresoc.v:79568.1-80248.10" +attribute \src "libresoc.v:79253.1-79933.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec22" attribute \generator "nMigen" module \dec22 - attribute \src "libresoc.v:80187.3-80196.6" + attribute \src "libresoc.v:79872.3-79881.6" wire width 2 $0\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:80197.3-80206.6" + attribute \src "libresoc.v:79882.3-79891.6" wire width 2 $0\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:80067.3-80076.6" + attribute \src "libresoc.v:79752.3-79761.6" wire width 8 $0\dec22_asmcode[7:0] - attribute \src "libresoc.v:80107.3-80116.6" + attribute \src "libresoc.v:79792.3-79801.6" wire $0\dec22_br[0:0] - attribute \src "libresoc.v:79927.3-79936.6" + attribute \src "libresoc.v:79612.3-79621.6" wire width 3 $0\dec22_cr_in[2:0] - attribute \src "libresoc.v:79937.3-79946.6" + attribute \src "libresoc.v:79622.3-79631.6" wire width 3 $0\dec22_cr_out[2:0] - attribute \src "libresoc.v:80057.3-80066.6" + attribute \src "libresoc.v:79742.3-79751.6" wire width 2 $0\dec22_cry_in[1:0] - attribute \src "libresoc.v:80097.3-80106.6" + attribute \src "libresoc.v:79782.3-79791.6" wire $0\dec22_cry_out[0:0] - attribute \src "libresoc.v:80137.3-80146.6" + attribute \src "libresoc.v:79822.3-79831.6" wire width 5 $0\dec22_form[4:0] - attribute \src "libresoc.v:79917.3-79926.6" + attribute \src "libresoc.v:79602.3-79611.6" wire width 14 $0\dec22_function_unit[13:0] - attribute \src "libresoc.v:80207.3-80216.6" + attribute \src "libresoc.v:79892.3-79901.6" wire width 3 $0\dec22_in1_sel[2:0] - attribute \src "libresoc.v:80217.3-80226.6" + attribute \src "libresoc.v:79902.3-79911.6" wire width 4 $0\dec22_in2_sel[3:0] - attribute \src "libresoc.v:80227.3-80236.6" + attribute \src "libresoc.v:79912.3-79921.6" wire width 2 $0\dec22_in3_sel[1:0] - attribute \src "libresoc.v:80027.3-80036.6" + attribute \src "libresoc.v:79712.3-79721.6" wire width 7 $0\dec22_internal_op[6:0] - attribute \src "libresoc.v:80077.3-80086.6" + attribute \src "libresoc.v:79762.3-79771.6" wire $0\dec22_inv_a[0:0] - attribute \src "libresoc.v:80087.3-80096.6" + attribute \src "libresoc.v:79772.3-79781.6" wire $0\dec22_inv_out[0:0] - attribute \src "libresoc.v:80147.3-80156.6" + attribute \src "libresoc.v:79832.3-79841.6" wire $0\dec22_is_32b[0:0] - attribute \src "libresoc.v:80017.3-80026.6" + attribute \src "libresoc.v:79702.3-79711.6" wire width 4 $0\dec22_ldst_len[3:0] - attribute \src "libresoc.v:80167.3-80176.6" + attribute \src "libresoc.v:79852.3-79861.6" wire $0\dec22_lk[0:0] - attribute \src "libresoc.v:80237.3-80246.6" + attribute \src "libresoc.v:79922.3-79931.6" wire width 3 $0\dec22_out_sel[2:0] - attribute \src "libresoc.v:80047.3-80056.6" + attribute \src "libresoc.v:79732.3-79741.6" wire width 2 $0\dec22_rc_sel[1:0] - attribute \src "libresoc.v:80127.3-80136.6" + attribute \src "libresoc.v:79812.3-79821.6" wire $0\dec22_rsrv[0:0] - attribute \src "libresoc.v:80177.3-80186.6" + attribute \src "libresoc.v:79862.3-79871.6" wire $0\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:80157.3-80166.6" + attribute \src "libresoc.v:79842.3-79851.6" wire $0\dec22_sgn[0:0] - attribute \src "libresoc.v:80117.3-80126.6" + attribute \src "libresoc.v:79802.3-79811.6" wire $0\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:79997.3-80006.6" + attribute \src "libresoc.v:79682.3-79691.6" wire width 3 $0\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:80007.3-80016.6" + attribute \src "libresoc.v:79692.3-79701.6" wire width 3 $0\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:79947.3-79956.6" + attribute \src "libresoc.v:79632.3-79641.6" wire width 3 $0\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79957.3-79966.6" + attribute \src "libresoc.v:79642.3-79651.6" wire width 3 $0\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79967.3-79976.6" + attribute \src "libresoc.v:79652.3-79661.6" wire width 3 $0\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79987.3-79996.6" + attribute \src "libresoc.v:79672.3-79681.6" wire width 3 $0\dec22_sv_out2[2:0] - attribute \src "libresoc.v:79977.3-79986.6" + attribute \src "libresoc.v:79662.3-79671.6" wire width 3 $0\dec22_sv_out[2:0] - attribute \src "libresoc.v:80037.3-80046.6" + attribute \src "libresoc.v:79722.3-79731.6" wire width 2 $0\dec22_upd[1:0] - attribute \src "libresoc.v:79569.7-79569.20" + attribute \src "libresoc.v:79254.7-79254.20" wire $0\initial[0:0] - attribute \src "libresoc.v:80187.3-80196.6" + attribute \src "libresoc.v:79872.3-79881.6" wire width 2 $1\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:80197.3-80206.6" + attribute \src "libresoc.v:79882.3-79891.6" wire width 2 $1\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:80067.3-80076.6" + attribute \src "libresoc.v:79752.3-79761.6" wire width 8 $1\dec22_asmcode[7:0] - attribute \src "libresoc.v:80107.3-80116.6" + attribute \src "libresoc.v:79792.3-79801.6" wire $1\dec22_br[0:0] - attribute \src "libresoc.v:79927.3-79936.6" + attribute \src "libresoc.v:79612.3-79621.6" wire width 3 $1\dec22_cr_in[2:0] - attribute \src "libresoc.v:79937.3-79946.6" + attribute \src "libresoc.v:79622.3-79631.6" wire width 3 $1\dec22_cr_out[2:0] - attribute \src "libresoc.v:80057.3-80066.6" + attribute \src "libresoc.v:79742.3-79751.6" wire width 2 $1\dec22_cry_in[1:0] - attribute \src "libresoc.v:80097.3-80106.6" + attribute \src "libresoc.v:79782.3-79791.6" wire $1\dec22_cry_out[0:0] - attribute \src "libresoc.v:80137.3-80146.6" + attribute \src "libresoc.v:79822.3-79831.6" wire width 5 $1\dec22_form[4:0] - attribute \src "libresoc.v:79917.3-79926.6" + attribute \src "libresoc.v:79602.3-79611.6" wire width 14 $1\dec22_function_unit[13:0] - attribute \src "libresoc.v:80207.3-80216.6" + attribute \src "libresoc.v:79892.3-79901.6" wire width 3 $1\dec22_in1_sel[2:0] - attribute \src "libresoc.v:80217.3-80226.6" + attribute \src "libresoc.v:79902.3-79911.6" wire width 4 $1\dec22_in2_sel[3:0] - attribute \src "libresoc.v:80227.3-80236.6" + attribute \src "libresoc.v:79912.3-79921.6" wire width 2 $1\dec22_in3_sel[1:0] - attribute \src "libresoc.v:80027.3-80036.6" + attribute \src "libresoc.v:79712.3-79721.6" wire width 7 $1\dec22_internal_op[6:0] - attribute \src "libresoc.v:80077.3-80086.6" + attribute \src "libresoc.v:79762.3-79771.6" wire $1\dec22_inv_a[0:0] - attribute \src "libresoc.v:80087.3-80096.6" + attribute \src "libresoc.v:79772.3-79781.6" wire $1\dec22_inv_out[0:0] - attribute \src "libresoc.v:80147.3-80156.6" + attribute \src "libresoc.v:79832.3-79841.6" wire $1\dec22_is_32b[0:0] - attribute \src "libresoc.v:80017.3-80026.6" + attribute \src "libresoc.v:79702.3-79711.6" wire width 4 $1\dec22_ldst_len[3:0] - attribute \src "libresoc.v:80167.3-80176.6" + attribute \src "libresoc.v:79852.3-79861.6" wire $1\dec22_lk[0:0] - attribute \src "libresoc.v:80237.3-80246.6" + attribute \src "libresoc.v:79922.3-79931.6" wire width 3 $1\dec22_out_sel[2:0] - attribute \src "libresoc.v:80047.3-80056.6" + attribute \src "libresoc.v:79732.3-79741.6" wire width 2 $1\dec22_rc_sel[1:0] - attribute \src "libresoc.v:80127.3-80136.6" + attribute \src "libresoc.v:79812.3-79821.6" wire $1\dec22_rsrv[0:0] - attribute \src "libresoc.v:80177.3-80186.6" + attribute \src "libresoc.v:79862.3-79871.6" wire $1\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:80157.3-80166.6" + attribute \src "libresoc.v:79842.3-79851.6" wire $1\dec22_sgn[0:0] - attribute \src "libresoc.v:80117.3-80126.6" + attribute \src "libresoc.v:79802.3-79811.6" wire $1\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:79997.3-80006.6" + attribute \src "libresoc.v:79682.3-79691.6" wire width 3 $1\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:80007.3-80016.6" + attribute \src "libresoc.v:79692.3-79701.6" wire width 3 $1\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:79947.3-79956.6" + attribute \src "libresoc.v:79632.3-79641.6" wire width 3 $1\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79957.3-79966.6" + attribute \src "libresoc.v:79642.3-79651.6" wire width 3 $1\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79967.3-79976.6" + attribute \src "libresoc.v:79652.3-79661.6" wire width 3 $1\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79987.3-79996.6" + attribute \src "libresoc.v:79672.3-79681.6" wire width 3 $1\dec22_sv_out2[2:0] - attribute \src "libresoc.v:79977.3-79986.6" + attribute \src "libresoc.v:79662.3-79671.6" wire width 3 $1\dec22_sv_out[2:0] - attribute \src "libresoc.v:80037.3-80046.6" + attribute \src "libresoc.v:79722.3-79731.6" wire width 2 $1\dec22_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -128521,28 +128043,28 @@ module \dec22 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec22_upd - attribute \src "libresoc.v:79569.7-79569.15" + attribute \src "libresoc.v:79254.7-79254.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch - attribute \src "libresoc.v:79569.7-79569.20" - process $proc$libresoc.v:79569$3782 + attribute \src "libresoc.v:79254.7-79254.20" + process $proc$libresoc.v:79254$3766 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:79917.3-79926.6" - process $proc$libresoc.v:79917$3749 + attribute \src "libresoc.v:79602.3-79611.6" + process $proc$libresoc.v:79602$3733 assign { } { } assign { } { } assign $0\dec22_function_unit[13:0] $1\dec22_function_unit[13:0] - attribute \src "libresoc.v:79918.5-79918.29" + attribute \src "libresoc.v:79603.5-79603.29" switch \initial - attribute \src "libresoc.v:79918.9-79918.17" + attribute \src "libresoc.v:79603.9-79603.17" case 1'1 case end @@ -128558,14 +128080,14 @@ module \dec22 sync always update \dec22_function_unit $0\dec22_function_unit[13:0] end - attribute \src "libresoc.v:79927.3-79936.6" - process $proc$libresoc.v:79927$3750 + attribute \src "libresoc.v:79612.3-79621.6" + process $proc$libresoc.v:79612$3734 assign { } { } assign { } { } assign $0\dec22_cr_in[2:0] $1\dec22_cr_in[2:0] - attribute \src "libresoc.v:79928.5-79928.29" + attribute \src "libresoc.v:79613.5-79613.29" switch \initial - attribute \src "libresoc.v:79928.9-79928.17" + attribute \src "libresoc.v:79613.9-79613.17" case 1'1 case end @@ -128581,14 +128103,14 @@ module \dec22 sync always update \dec22_cr_in $0\dec22_cr_in[2:0] end - attribute \src "libresoc.v:79937.3-79946.6" - process $proc$libresoc.v:79937$3751 + attribute \src "libresoc.v:79622.3-79631.6" + process $proc$libresoc.v:79622$3735 assign { } { } assign { } { } assign $0\dec22_cr_out[2:0] $1\dec22_cr_out[2:0] - attribute \src "libresoc.v:79938.5-79938.29" + attribute \src "libresoc.v:79623.5-79623.29" switch \initial - attribute \src "libresoc.v:79938.9-79938.17" + attribute \src "libresoc.v:79623.9-79623.17" case 1'1 case end @@ -128604,14 +128126,14 @@ module \dec22 sync always update \dec22_cr_out $0\dec22_cr_out[2:0] end - attribute \src "libresoc.v:79947.3-79956.6" - process $proc$libresoc.v:79947$3752 + attribute \src "libresoc.v:79632.3-79641.6" + process $proc$libresoc.v:79632$3736 assign { } { } assign { } { } assign $0\dec22_sv_in1[2:0] $1\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79948.5-79948.29" + attribute \src "libresoc.v:79633.5-79633.29" switch \initial - attribute \src "libresoc.v:79948.9-79948.17" + attribute \src "libresoc.v:79633.9-79633.17" case 1'1 case end @@ -128627,14 +128149,14 @@ module \dec22 sync always update \dec22_sv_in1 $0\dec22_sv_in1[2:0] end - attribute \src "libresoc.v:79957.3-79966.6" - process $proc$libresoc.v:79957$3753 + attribute \src "libresoc.v:79642.3-79651.6" + process $proc$libresoc.v:79642$3737 assign { } { } assign { } { } assign $0\dec22_sv_in2[2:0] $1\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79958.5-79958.29" + attribute \src "libresoc.v:79643.5-79643.29" switch \initial - attribute \src "libresoc.v:79958.9-79958.17" + attribute \src "libresoc.v:79643.9-79643.17" case 1'1 case end @@ -128650,14 +128172,14 @@ module \dec22 sync always update \dec22_sv_in2 $0\dec22_sv_in2[2:0] end - attribute \src "libresoc.v:79967.3-79976.6" - process $proc$libresoc.v:79967$3754 + attribute \src "libresoc.v:79652.3-79661.6" + process $proc$libresoc.v:79652$3738 assign { } { } assign { } { } assign $0\dec22_sv_in3[2:0] $1\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79968.5-79968.29" + attribute \src "libresoc.v:79653.5-79653.29" switch \initial - attribute \src "libresoc.v:79968.9-79968.17" + attribute \src "libresoc.v:79653.9-79653.17" case 1'1 case end @@ -128673,14 +128195,14 @@ module \dec22 sync always update \dec22_sv_in3 $0\dec22_sv_in3[2:0] end - attribute \src "libresoc.v:79977.3-79986.6" - process $proc$libresoc.v:79977$3755 + attribute \src "libresoc.v:79662.3-79671.6" + process $proc$libresoc.v:79662$3739 assign { } { } assign { } { } assign $0\dec22_sv_out[2:0] $1\dec22_sv_out[2:0] - attribute \src "libresoc.v:79978.5-79978.29" + attribute \src "libresoc.v:79663.5-79663.29" switch \initial - attribute \src "libresoc.v:79978.9-79978.17" + attribute \src "libresoc.v:79663.9-79663.17" case 1'1 case end @@ -128696,14 +128218,14 @@ module \dec22 sync always update \dec22_sv_out $0\dec22_sv_out[2:0] end - attribute \src "libresoc.v:79987.3-79996.6" - process $proc$libresoc.v:79987$3756 + attribute \src "libresoc.v:79672.3-79681.6" + process $proc$libresoc.v:79672$3740 assign { } { } assign { } { } assign $0\dec22_sv_out2[2:0] $1\dec22_sv_out2[2:0] - attribute \src "libresoc.v:79988.5-79988.29" + attribute \src "libresoc.v:79673.5-79673.29" switch \initial - attribute \src "libresoc.v:79988.9-79988.17" + attribute \src "libresoc.v:79673.9-79673.17" case 1'1 case end @@ -128719,14 +128241,14 @@ module \dec22 sync always update \dec22_sv_out2 $0\dec22_sv_out2[2:0] end - attribute \src "libresoc.v:79997.3-80006.6" - process $proc$libresoc.v:79997$3757 + attribute \src "libresoc.v:79682.3-79691.6" + process $proc$libresoc.v:79682$3741 assign { } { } assign { } { } assign $0\dec22_sv_cr_in[2:0] $1\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:79998.5-79998.29" + attribute \src "libresoc.v:79683.5-79683.29" switch \initial - attribute \src "libresoc.v:79998.9-79998.17" + attribute \src "libresoc.v:79683.9-79683.17" case 1'1 case end @@ -128742,14 +128264,14 @@ module \dec22 sync always update \dec22_sv_cr_in $0\dec22_sv_cr_in[2:0] end - attribute \src "libresoc.v:80007.3-80016.6" - process $proc$libresoc.v:80007$3758 + attribute \src "libresoc.v:79692.3-79701.6" + process $proc$libresoc.v:79692$3742 assign { } { } assign { } { } assign $0\dec22_sv_cr_out[2:0] $1\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:80008.5-80008.29" + attribute \src "libresoc.v:79693.5-79693.29" switch \initial - attribute \src "libresoc.v:80008.9-80008.17" + attribute \src "libresoc.v:79693.9-79693.17" case 1'1 case end @@ -128765,14 +128287,14 @@ module \dec22 sync always update \dec22_sv_cr_out $0\dec22_sv_cr_out[2:0] end - attribute \src "libresoc.v:80017.3-80026.6" - process $proc$libresoc.v:80017$3759 + attribute \src "libresoc.v:79702.3-79711.6" + process $proc$libresoc.v:79702$3743 assign { } { } assign { } { } assign $0\dec22_ldst_len[3:0] $1\dec22_ldst_len[3:0] - attribute \src "libresoc.v:80018.5-80018.29" + attribute \src "libresoc.v:79703.5-79703.29" switch \initial - attribute \src "libresoc.v:80018.9-80018.17" + attribute \src "libresoc.v:79703.9-79703.17" case 1'1 case end @@ -128788,14 +128310,14 @@ module \dec22 sync always update \dec22_ldst_len $0\dec22_ldst_len[3:0] end - attribute \src "libresoc.v:80027.3-80036.6" - process $proc$libresoc.v:80027$3760 + attribute \src "libresoc.v:79712.3-79721.6" + process $proc$libresoc.v:79712$3744 assign { } { } assign { } { } assign $0\dec22_internal_op[6:0] $1\dec22_internal_op[6:0] - attribute \src "libresoc.v:80028.5-80028.29" + attribute \src "libresoc.v:79713.5-79713.29" switch \initial - attribute \src "libresoc.v:80028.9-80028.17" + attribute \src "libresoc.v:79713.9-79713.17" case 1'1 case end @@ -128811,14 +128333,14 @@ module \dec22 sync always update \dec22_internal_op $0\dec22_internal_op[6:0] end - attribute \src "libresoc.v:80037.3-80046.6" - process $proc$libresoc.v:80037$3761 + attribute \src "libresoc.v:79722.3-79731.6" + process $proc$libresoc.v:79722$3745 assign { } { } assign { } { } assign $0\dec22_upd[1:0] $1\dec22_upd[1:0] - attribute \src "libresoc.v:80038.5-80038.29" + attribute \src "libresoc.v:79723.5-79723.29" switch \initial - attribute \src "libresoc.v:80038.9-80038.17" + attribute \src "libresoc.v:79723.9-79723.17" case 1'1 case end @@ -128834,14 +128356,14 @@ module \dec22 sync always update \dec22_upd $0\dec22_upd[1:0] end - attribute \src "libresoc.v:80047.3-80056.6" - process $proc$libresoc.v:80047$3762 + attribute \src "libresoc.v:79732.3-79741.6" + process $proc$libresoc.v:79732$3746 assign { } { } assign { } { } assign $0\dec22_rc_sel[1:0] $1\dec22_rc_sel[1:0] - attribute \src "libresoc.v:80048.5-80048.29" + attribute \src "libresoc.v:79733.5-79733.29" switch \initial - attribute \src "libresoc.v:80048.9-80048.17" + attribute \src "libresoc.v:79733.9-79733.17" case 1'1 case end @@ -128857,14 +128379,14 @@ module \dec22 sync always update \dec22_rc_sel $0\dec22_rc_sel[1:0] end - attribute \src "libresoc.v:80057.3-80066.6" - process $proc$libresoc.v:80057$3763 + attribute \src "libresoc.v:79742.3-79751.6" + process $proc$libresoc.v:79742$3747 assign { } { } assign { } { } assign $0\dec22_cry_in[1:0] $1\dec22_cry_in[1:0] - attribute \src "libresoc.v:80058.5-80058.29" + attribute \src "libresoc.v:79743.5-79743.29" switch \initial - attribute \src "libresoc.v:80058.9-80058.17" + attribute \src "libresoc.v:79743.9-79743.17" case 1'1 case end @@ -128880,14 +128402,14 @@ module \dec22 sync always update \dec22_cry_in $0\dec22_cry_in[1:0] end - attribute \src "libresoc.v:80067.3-80076.6" - process $proc$libresoc.v:80067$3764 + attribute \src "libresoc.v:79752.3-79761.6" + process $proc$libresoc.v:79752$3748 assign { } { } assign { } { } assign $0\dec22_asmcode[7:0] $1\dec22_asmcode[7:0] - attribute \src "libresoc.v:80068.5-80068.29" + attribute \src "libresoc.v:79753.5-79753.29" switch \initial - attribute \src "libresoc.v:80068.9-80068.17" + attribute \src "libresoc.v:79753.9-79753.17" case 1'1 case end @@ -128903,14 +128425,14 @@ module \dec22 sync always update \dec22_asmcode $0\dec22_asmcode[7:0] end - attribute \src "libresoc.v:80077.3-80086.6" - process $proc$libresoc.v:80077$3765 + attribute \src "libresoc.v:79762.3-79771.6" + process $proc$libresoc.v:79762$3749 assign { } { } assign { } { } assign $0\dec22_inv_a[0:0] $1\dec22_inv_a[0:0] - attribute \src "libresoc.v:80078.5-80078.29" + attribute \src "libresoc.v:79763.5-79763.29" switch \initial - attribute \src "libresoc.v:80078.9-80078.17" + attribute \src "libresoc.v:79763.9-79763.17" case 1'1 case end @@ -128926,14 +128448,14 @@ module \dec22 sync always update \dec22_inv_a $0\dec22_inv_a[0:0] end - attribute \src "libresoc.v:80087.3-80096.6" - process $proc$libresoc.v:80087$3766 + attribute \src "libresoc.v:79772.3-79781.6" + process $proc$libresoc.v:79772$3750 assign { } { } assign { } { } assign $0\dec22_inv_out[0:0] $1\dec22_inv_out[0:0] - attribute \src "libresoc.v:80088.5-80088.29" + attribute \src "libresoc.v:79773.5-79773.29" switch \initial - attribute \src "libresoc.v:80088.9-80088.17" + attribute \src "libresoc.v:79773.9-79773.17" case 1'1 case end @@ -128949,14 +128471,14 @@ module \dec22 sync always update \dec22_inv_out $0\dec22_inv_out[0:0] end - attribute \src "libresoc.v:80097.3-80106.6" - process $proc$libresoc.v:80097$3767 + attribute \src "libresoc.v:79782.3-79791.6" + process $proc$libresoc.v:79782$3751 assign { } { } assign { } { } assign $0\dec22_cry_out[0:0] $1\dec22_cry_out[0:0] - attribute \src "libresoc.v:80098.5-80098.29" + attribute \src "libresoc.v:79783.5-79783.29" switch \initial - attribute \src "libresoc.v:80098.9-80098.17" + attribute \src "libresoc.v:79783.9-79783.17" case 1'1 case end @@ -128972,14 +128494,14 @@ module \dec22 sync always update \dec22_cry_out $0\dec22_cry_out[0:0] end - attribute \src "libresoc.v:80107.3-80116.6" - process $proc$libresoc.v:80107$3768 + attribute \src "libresoc.v:79792.3-79801.6" + process $proc$libresoc.v:79792$3752 assign { } { } assign { } { } assign $0\dec22_br[0:0] $1\dec22_br[0:0] - attribute \src "libresoc.v:80108.5-80108.29" + attribute \src "libresoc.v:79793.5-79793.29" switch \initial - attribute \src "libresoc.v:80108.9-80108.17" + attribute \src "libresoc.v:79793.9-79793.17" case 1'1 case end @@ -128995,14 +128517,14 @@ module \dec22 sync always update \dec22_br $0\dec22_br[0:0] end - attribute \src "libresoc.v:80117.3-80126.6" - process $proc$libresoc.v:80117$3769 + attribute \src "libresoc.v:79802.3-79811.6" + process $proc$libresoc.v:79802$3753 assign { } { } assign { } { } assign $0\dec22_sgn_ext[0:0] $1\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:80118.5-80118.29" + attribute \src "libresoc.v:79803.5-79803.29" switch \initial - attribute \src "libresoc.v:80118.9-80118.17" + attribute \src "libresoc.v:79803.9-79803.17" case 1'1 case end @@ -129018,14 +128540,14 @@ module \dec22 sync always update \dec22_sgn_ext $0\dec22_sgn_ext[0:0] end - attribute \src "libresoc.v:80127.3-80136.6" - process $proc$libresoc.v:80127$3770 + attribute \src "libresoc.v:79812.3-79821.6" + process $proc$libresoc.v:79812$3754 assign { } { } assign { } { } assign $0\dec22_rsrv[0:0] $1\dec22_rsrv[0:0] - attribute \src "libresoc.v:80128.5-80128.29" + attribute \src "libresoc.v:79813.5-79813.29" switch \initial - attribute \src "libresoc.v:80128.9-80128.17" + attribute \src "libresoc.v:79813.9-79813.17" case 1'1 case end @@ -129041,14 +128563,14 @@ module \dec22 sync always update \dec22_rsrv $0\dec22_rsrv[0:0] end - attribute \src "libresoc.v:80137.3-80146.6" - process $proc$libresoc.v:80137$3771 + attribute \src "libresoc.v:79822.3-79831.6" + process $proc$libresoc.v:79822$3755 assign { } { } assign { } { } assign $0\dec22_form[4:0] $1\dec22_form[4:0] - attribute \src "libresoc.v:80138.5-80138.29" + attribute \src "libresoc.v:79823.5-79823.29" switch \initial - attribute \src "libresoc.v:80138.9-80138.17" + attribute \src "libresoc.v:79823.9-79823.17" case 1'1 case end @@ -129064,14 +128586,14 @@ module \dec22 sync always update \dec22_form $0\dec22_form[4:0] end - attribute \src "libresoc.v:80147.3-80156.6" - process $proc$libresoc.v:80147$3772 + attribute \src "libresoc.v:79832.3-79841.6" + process $proc$libresoc.v:79832$3756 assign { } { } assign { } { } assign $0\dec22_is_32b[0:0] $1\dec22_is_32b[0:0] - attribute \src "libresoc.v:80148.5-80148.29" + attribute \src "libresoc.v:79833.5-79833.29" switch \initial - attribute \src "libresoc.v:80148.9-80148.17" + attribute \src "libresoc.v:79833.9-79833.17" case 1'1 case end @@ -129087,14 +128609,14 @@ module \dec22 sync always update \dec22_is_32b $0\dec22_is_32b[0:0] end - attribute \src "libresoc.v:80157.3-80166.6" - process $proc$libresoc.v:80157$3773 + attribute \src "libresoc.v:79842.3-79851.6" + process $proc$libresoc.v:79842$3757 assign { } { } assign { } { } assign $0\dec22_sgn[0:0] $1\dec22_sgn[0:0] - attribute \src "libresoc.v:80158.5-80158.29" + attribute \src "libresoc.v:79843.5-79843.29" switch \initial - attribute \src "libresoc.v:80158.9-80158.17" + attribute \src "libresoc.v:79843.9-79843.17" case 1'1 case end @@ -129110,14 +128632,14 @@ module \dec22 sync always update \dec22_sgn $0\dec22_sgn[0:0] end - attribute \src "libresoc.v:80167.3-80176.6" - process $proc$libresoc.v:80167$3774 + attribute \src "libresoc.v:79852.3-79861.6" + process $proc$libresoc.v:79852$3758 assign { } { } assign { } { } assign $0\dec22_lk[0:0] $1\dec22_lk[0:0] - attribute \src "libresoc.v:80168.5-80168.29" + attribute \src "libresoc.v:79853.5-79853.29" switch \initial - attribute \src "libresoc.v:80168.9-80168.17" + attribute \src "libresoc.v:79853.9-79853.17" case 1'1 case end @@ -129133,14 +128655,14 @@ module \dec22 sync always update \dec22_lk $0\dec22_lk[0:0] end - attribute \src "libresoc.v:80177.3-80186.6" - process $proc$libresoc.v:80177$3775 + attribute \src "libresoc.v:79862.3-79871.6" + process $proc$libresoc.v:79862$3759 assign { } { } assign { } { } assign $0\dec22_sgl_pipe[0:0] $1\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:80178.5-80178.29" + attribute \src "libresoc.v:79863.5-79863.29" switch \initial - attribute \src "libresoc.v:80178.9-80178.17" + attribute \src "libresoc.v:79863.9-79863.17" case 1'1 case end @@ -129156,14 +128678,14 @@ module \dec22 sync always update \dec22_sgl_pipe $0\dec22_sgl_pipe[0:0] end - attribute \src "libresoc.v:80187.3-80196.6" - process $proc$libresoc.v:80187$3776 + attribute \src "libresoc.v:79872.3-79881.6" + process $proc$libresoc.v:79872$3760 assign { } { } assign { } { } assign $0\dec22_SV_Etype[1:0] $1\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:80188.5-80188.29" + attribute \src "libresoc.v:79873.5-79873.29" switch \initial - attribute \src "libresoc.v:80188.9-80188.17" + attribute \src "libresoc.v:79873.9-79873.17" case 1'1 case end @@ -129179,14 +128701,14 @@ module \dec22 sync always update \dec22_SV_Etype $0\dec22_SV_Etype[1:0] end - attribute \src "libresoc.v:80197.3-80206.6" - process $proc$libresoc.v:80197$3777 + attribute \src "libresoc.v:79882.3-79891.6" + process $proc$libresoc.v:79882$3761 assign { } { } assign { } { } assign $0\dec22_SV_Ptype[1:0] $1\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:80198.5-80198.29" + attribute \src "libresoc.v:79883.5-79883.29" switch \initial - attribute \src "libresoc.v:80198.9-80198.17" + attribute \src "libresoc.v:79883.9-79883.17" case 1'1 case end @@ -129202,14 +128724,14 @@ module \dec22 sync always update \dec22_SV_Ptype $0\dec22_SV_Ptype[1:0] end - attribute \src "libresoc.v:80207.3-80216.6" - process $proc$libresoc.v:80207$3778 + attribute \src "libresoc.v:79892.3-79901.6" + process $proc$libresoc.v:79892$3762 assign { } { } assign { } { } assign $0\dec22_in1_sel[2:0] $1\dec22_in1_sel[2:0] - attribute \src "libresoc.v:80208.5-80208.29" + attribute \src "libresoc.v:79893.5-79893.29" switch \initial - attribute \src "libresoc.v:80208.9-80208.17" + attribute \src "libresoc.v:79893.9-79893.17" case 1'1 case end @@ -129225,14 +128747,14 @@ module \dec22 sync always update \dec22_in1_sel $0\dec22_in1_sel[2:0] end - attribute \src "libresoc.v:80217.3-80226.6" - process $proc$libresoc.v:80217$3779 + attribute \src "libresoc.v:79902.3-79911.6" + process $proc$libresoc.v:79902$3763 assign { } { } assign { } { } assign $0\dec22_in2_sel[3:0] $1\dec22_in2_sel[3:0] - attribute \src "libresoc.v:80218.5-80218.29" + attribute \src "libresoc.v:79903.5-79903.29" switch \initial - attribute \src "libresoc.v:80218.9-80218.17" + attribute \src "libresoc.v:79903.9-79903.17" case 1'1 case end @@ -129248,14 +128770,14 @@ module \dec22 sync always update \dec22_in2_sel $0\dec22_in2_sel[3:0] end - attribute \src "libresoc.v:80227.3-80236.6" - process $proc$libresoc.v:80227$3780 + attribute \src "libresoc.v:79912.3-79921.6" + process $proc$libresoc.v:79912$3764 assign { } { } assign { } { } assign $0\dec22_in3_sel[1:0] $1\dec22_in3_sel[1:0] - attribute \src "libresoc.v:80228.5-80228.29" + attribute \src "libresoc.v:79913.5-79913.29" switch \initial - attribute \src "libresoc.v:80228.9-80228.17" + attribute \src "libresoc.v:79913.9-79913.17" case 1'1 case end @@ -129271,14 +128793,14 @@ module \dec22 sync always update \dec22_in3_sel $0\dec22_in3_sel[1:0] end - attribute \src "libresoc.v:80237.3-80246.6" - process $proc$libresoc.v:80237$3781 + attribute \src "libresoc.v:79922.3-79931.6" + process $proc$libresoc.v:79922$3765 assign { } { } assign { } { } assign $0\dec22_out_sel[2:0] $1\dec22_out_sel[2:0] - attribute \src "libresoc.v:80238.5-80238.29" + attribute \src "libresoc.v:79923.5-79923.29" switch \initial - attribute \src "libresoc.v:80238.9-80238.17" + attribute \src "libresoc.v:79923.9-79923.17" case 1'1 case end @@ -129296,144 +128818,144 @@ module \dec22 end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:80252.1-81823.10" +attribute \src "libresoc.v:79937.1-81508.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" attribute \generator "nMigen" module \dec30 - attribute \src "libresoc.v:81600.3-81636.6" + attribute \src "libresoc.v:81285.3-81321.6" wire width 2 $0\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81637.3-81673.6" + attribute \src "libresoc.v:81322.3-81358.6" wire width 2 $0\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:81156.3-81192.6" + attribute \src "libresoc.v:80841.3-80877.6" wire width 8 $0\dec30_asmcode[7:0] - attribute \src "libresoc.v:81304.3-81340.6" + attribute \src "libresoc.v:80989.3-81025.6" wire $0\dec30_br[0:0] - attribute \src "libresoc.v:80638.3-80674.6" + attribute \src "libresoc.v:80323.3-80359.6" wire width 3 $0\dec30_cr_in[2:0] - attribute \src "libresoc.v:80675.3-80711.6" + attribute \src "libresoc.v:80360.3-80396.6" wire width 3 $0\dec30_cr_out[2:0] - attribute \src "libresoc.v:81119.3-81155.6" + attribute \src "libresoc.v:80804.3-80840.6" wire width 2 $0\dec30_cry_in[1:0] - attribute \src "libresoc.v:81267.3-81303.6" + attribute \src "libresoc.v:80952.3-80988.6" wire $0\dec30_cry_out[0:0] - attribute \src "libresoc.v:81415.3-81451.6" + attribute \src "libresoc.v:81100.3-81136.6" wire width 5 $0\dec30_form[4:0] - attribute \src "libresoc.v:80601.3-80637.6" + attribute \src "libresoc.v:80286.3-80322.6" wire width 14 $0\dec30_function_unit[13:0] - attribute \src "libresoc.v:81674.3-81710.6" + attribute \src "libresoc.v:81359.3-81395.6" wire width 3 $0\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81711.3-81747.6" + attribute \src "libresoc.v:81396.3-81432.6" wire width 4 $0\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81748.3-81784.6" + attribute \src "libresoc.v:81433.3-81469.6" wire width 2 $0\dec30_in3_sel[1:0] - attribute \src "libresoc.v:81008.3-81044.6" + attribute \src "libresoc.v:80693.3-80729.6" wire width 7 $0\dec30_internal_op[6:0] - attribute \src "libresoc.v:81193.3-81229.6" + attribute \src "libresoc.v:80878.3-80914.6" wire $0\dec30_inv_a[0:0] - attribute \src "libresoc.v:81230.3-81266.6" + attribute \src "libresoc.v:80915.3-80951.6" wire $0\dec30_inv_out[0:0] - attribute \src "libresoc.v:81452.3-81488.6" + attribute \src "libresoc.v:81137.3-81173.6" wire $0\dec30_is_32b[0:0] - attribute \src "libresoc.v:80971.3-81007.6" + attribute \src "libresoc.v:80656.3-80692.6" wire width 4 $0\dec30_ldst_len[3:0] - attribute \src "libresoc.v:81526.3-81562.6" + attribute \src "libresoc.v:81211.3-81247.6" wire $0\dec30_lk[0:0] - attribute \src "libresoc.v:81785.3-81821.6" + attribute \src "libresoc.v:81470.3-81506.6" wire width 3 $0\dec30_out_sel[2:0] - attribute \src "libresoc.v:81082.3-81118.6" + attribute \src "libresoc.v:80767.3-80803.6" wire width 2 $0\dec30_rc_sel[1:0] - attribute \src "libresoc.v:81378.3-81414.6" + attribute \src "libresoc.v:81063.3-81099.6" wire $0\dec30_rsrv[0:0] - attribute \src "libresoc.v:81563.3-81599.6" + attribute \src "libresoc.v:81248.3-81284.6" wire $0\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81489.3-81525.6" + attribute \src "libresoc.v:81174.3-81210.6" wire $0\dec30_sgn[0:0] - attribute \src "libresoc.v:81341.3-81377.6" + attribute \src "libresoc.v:81026.3-81062.6" wire $0\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:80897.3-80933.6" + attribute \src "libresoc.v:80582.3-80618.6" wire width 3 $0\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80934.3-80970.6" + attribute \src "libresoc.v:80619.3-80655.6" wire width 3 $0\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80712.3-80748.6" + attribute \src "libresoc.v:80397.3-80433.6" wire width 3 $0\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80749.3-80785.6" + attribute \src "libresoc.v:80434.3-80470.6" wire width 3 $0\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80786.3-80822.6" + attribute \src "libresoc.v:80471.3-80507.6" wire width 3 $0\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80860.3-80896.6" + attribute \src "libresoc.v:80545.3-80581.6" wire width 3 $0\dec30_sv_out2[2:0] - attribute \src "libresoc.v:80823.3-80859.6" + attribute \src "libresoc.v:80508.3-80544.6" wire width 3 $0\dec30_sv_out[2:0] - attribute \src "libresoc.v:81045.3-81081.6" + attribute \src "libresoc.v:80730.3-80766.6" wire width 2 $0\dec30_upd[1:0] - attribute \src "libresoc.v:80253.7-80253.20" + attribute \src "libresoc.v:79938.7-79938.20" wire $0\initial[0:0] - attribute \src "libresoc.v:81600.3-81636.6" + attribute \src "libresoc.v:81285.3-81321.6" wire width 2 $1\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81637.3-81673.6" + attribute \src "libresoc.v:81322.3-81358.6" wire width 2 $1\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:81156.3-81192.6" + attribute \src "libresoc.v:80841.3-80877.6" wire width 8 $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:81304.3-81340.6" + attribute \src "libresoc.v:80989.3-81025.6" wire $1\dec30_br[0:0] - attribute \src "libresoc.v:80638.3-80674.6" + attribute \src "libresoc.v:80323.3-80359.6" wire width 3 $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:80675.3-80711.6" + attribute \src "libresoc.v:80360.3-80396.6" wire width 3 $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:81119.3-81155.6" + attribute \src "libresoc.v:80804.3-80840.6" wire width 2 $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:81267.3-81303.6" + attribute \src "libresoc.v:80952.3-80988.6" wire $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:81415.3-81451.6" + attribute \src "libresoc.v:81100.3-81136.6" wire width 5 $1\dec30_form[4:0] - attribute \src "libresoc.v:80601.3-80637.6" + attribute \src "libresoc.v:80286.3-80322.6" wire width 14 $1\dec30_function_unit[13:0] - attribute \src "libresoc.v:81674.3-81710.6" + attribute \src "libresoc.v:81359.3-81395.6" wire width 3 $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81711.3-81747.6" + attribute \src "libresoc.v:81396.3-81432.6" wire width 4 $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81748.3-81784.6" + attribute \src "libresoc.v:81433.3-81469.6" wire width 2 $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:81008.3-81044.6" + attribute \src "libresoc.v:80693.3-80729.6" wire width 7 $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:81193.3-81229.6" + attribute \src "libresoc.v:80878.3-80914.6" wire $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:81230.3-81266.6" + attribute \src "libresoc.v:80915.3-80951.6" wire $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:81452.3-81488.6" + attribute \src "libresoc.v:81137.3-81173.6" wire $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:80971.3-81007.6" + attribute \src "libresoc.v:80656.3-80692.6" wire width 4 $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:81526.3-81562.6" + attribute \src "libresoc.v:81211.3-81247.6" wire $1\dec30_lk[0:0] - attribute \src "libresoc.v:81785.3-81821.6" + attribute \src "libresoc.v:81470.3-81506.6" wire width 3 $1\dec30_out_sel[2:0] - attribute \src "libresoc.v:81082.3-81118.6" + attribute \src "libresoc.v:80767.3-80803.6" wire width 2 $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:81378.3-81414.6" + attribute \src "libresoc.v:81063.3-81099.6" wire $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:81563.3-81599.6" + attribute \src "libresoc.v:81248.3-81284.6" wire $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81489.3-81525.6" + attribute \src "libresoc.v:81174.3-81210.6" wire $1\dec30_sgn[0:0] - attribute \src "libresoc.v:81341.3-81377.6" + attribute \src "libresoc.v:81026.3-81062.6" wire $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:80897.3-80933.6" + attribute \src "libresoc.v:80582.3-80618.6" wire width 3 $1\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80934.3-80970.6" + attribute \src "libresoc.v:80619.3-80655.6" wire width 3 $1\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80712.3-80748.6" + attribute \src "libresoc.v:80397.3-80433.6" wire width 3 $1\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80749.3-80785.6" + attribute \src "libresoc.v:80434.3-80470.6" wire width 3 $1\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80786.3-80822.6" + attribute \src "libresoc.v:80471.3-80507.6" wire width 3 $1\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80860.3-80896.6" + attribute \src "libresoc.v:80545.3-80581.6" wire width 3 $1\dec30_sv_out2[2:0] - attribute \src "libresoc.v:80823.3-80859.6" + attribute \src "libresoc.v:80508.3-80544.6" wire width 3 $1\dec30_sv_out[2:0] - attribute \src "libresoc.v:81045.3-81081.6" + attribute \src "libresoc.v:80730.3-80766.6" wire width 2 $1\dec30_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -129745,28 +129267,28 @@ module \dec30 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec30_upd - attribute \src "libresoc.v:80253.7-80253.15" + attribute \src "libresoc.v:79938.7-79938.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch - attribute \src "libresoc.v:80253.7-80253.20" - process $proc$libresoc.v:80253$3816 + attribute \src "libresoc.v:79938.7-79938.20" + process $proc$libresoc.v:79938$3800 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:80601.3-80637.6" - process $proc$libresoc.v:80601$3783 + attribute \src "libresoc.v:80286.3-80322.6" + process $proc$libresoc.v:80286$3767 assign { } { } assign { } { } assign $0\dec30_function_unit[13:0] $1\dec30_function_unit[13:0] - attribute \src "libresoc.v:80602.5-80602.29" + attribute \src "libresoc.v:80287.5-80287.29" switch \initial - attribute \src "libresoc.v:80602.9-80602.17" + attribute \src "libresoc.v:80287.9-80287.17" case 1'1 case end @@ -129818,14 +129340,14 @@ module \dec30 sync always update \dec30_function_unit $0\dec30_function_unit[13:0] end - attribute \src "libresoc.v:80638.3-80674.6" - process $proc$libresoc.v:80638$3784 + attribute \src "libresoc.v:80323.3-80359.6" + process $proc$libresoc.v:80323$3768 assign { } { } assign { } { } assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:80639.5-80639.29" + attribute \src "libresoc.v:80324.5-80324.29" switch \initial - attribute \src "libresoc.v:80639.9-80639.17" + attribute \src "libresoc.v:80324.9-80324.17" case 1'1 case end @@ -129877,14 +129399,14 @@ module \dec30 sync always update \dec30_cr_in $0\dec30_cr_in[2:0] end - attribute \src "libresoc.v:80675.3-80711.6" - process $proc$libresoc.v:80675$3785 + attribute \src "libresoc.v:80360.3-80396.6" + process $proc$libresoc.v:80360$3769 assign { } { } assign { } { } assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:80676.5-80676.29" + attribute \src "libresoc.v:80361.5-80361.29" switch \initial - attribute \src "libresoc.v:80676.9-80676.17" + attribute \src "libresoc.v:80361.9-80361.17" case 1'1 case end @@ -129936,14 +129458,14 @@ module \dec30 sync always update \dec30_cr_out $0\dec30_cr_out[2:0] end - attribute \src "libresoc.v:80712.3-80748.6" - process $proc$libresoc.v:80712$3786 + attribute \src "libresoc.v:80397.3-80433.6" + process $proc$libresoc.v:80397$3770 assign { } { } assign { } { } assign $0\dec30_sv_in1[2:0] $1\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80713.5-80713.29" + attribute \src "libresoc.v:80398.5-80398.29" switch \initial - attribute \src "libresoc.v:80713.9-80713.17" + attribute \src "libresoc.v:80398.9-80398.17" case 1'1 case end @@ -129995,14 +129517,14 @@ module \dec30 sync always update \dec30_sv_in1 $0\dec30_sv_in1[2:0] end - attribute \src "libresoc.v:80749.3-80785.6" - process $proc$libresoc.v:80749$3787 + attribute \src "libresoc.v:80434.3-80470.6" + process $proc$libresoc.v:80434$3771 assign { } { } assign { } { } assign $0\dec30_sv_in2[2:0] $1\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80750.5-80750.29" + attribute \src "libresoc.v:80435.5-80435.29" switch \initial - attribute \src "libresoc.v:80750.9-80750.17" + attribute \src "libresoc.v:80435.9-80435.17" case 1'1 case end @@ -130054,14 +129576,14 @@ module \dec30 sync always update \dec30_sv_in2 $0\dec30_sv_in2[2:0] end - attribute \src "libresoc.v:80786.3-80822.6" - process $proc$libresoc.v:80786$3788 + attribute \src "libresoc.v:80471.3-80507.6" + process $proc$libresoc.v:80471$3772 assign { } { } assign { } { } assign $0\dec30_sv_in3[2:0] $1\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80787.5-80787.29" + attribute \src "libresoc.v:80472.5-80472.29" switch \initial - attribute \src "libresoc.v:80787.9-80787.17" + attribute \src "libresoc.v:80472.9-80472.17" case 1'1 case end @@ -130113,14 +129635,14 @@ module \dec30 sync always update \dec30_sv_in3 $0\dec30_sv_in3[2:0] end - attribute \src "libresoc.v:80823.3-80859.6" - process $proc$libresoc.v:80823$3789 + attribute \src "libresoc.v:80508.3-80544.6" + process $proc$libresoc.v:80508$3773 assign { } { } assign { } { } assign $0\dec30_sv_out[2:0] $1\dec30_sv_out[2:0] - attribute \src "libresoc.v:80824.5-80824.29" + attribute \src "libresoc.v:80509.5-80509.29" switch \initial - attribute \src "libresoc.v:80824.9-80824.17" + attribute \src "libresoc.v:80509.9-80509.17" case 1'1 case end @@ -130172,14 +129694,14 @@ module \dec30 sync always update \dec30_sv_out $0\dec30_sv_out[2:0] end - attribute \src "libresoc.v:80860.3-80896.6" - process $proc$libresoc.v:80860$3790 + attribute \src "libresoc.v:80545.3-80581.6" + process $proc$libresoc.v:80545$3774 assign { } { } assign { } { } assign $0\dec30_sv_out2[2:0] $1\dec30_sv_out2[2:0] - attribute \src "libresoc.v:80861.5-80861.29" + attribute \src "libresoc.v:80546.5-80546.29" switch \initial - attribute \src "libresoc.v:80861.9-80861.17" + attribute \src "libresoc.v:80546.9-80546.17" case 1'1 case end @@ -130231,14 +129753,14 @@ module \dec30 sync always update \dec30_sv_out2 $0\dec30_sv_out2[2:0] end - attribute \src "libresoc.v:80897.3-80933.6" - process $proc$libresoc.v:80897$3791 + attribute \src "libresoc.v:80582.3-80618.6" + process $proc$libresoc.v:80582$3775 assign { } { } assign { } { } assign $0\dec30_sv_cr_in[2:0] $1\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80898.5-80898.29" + attribute \src "libresoc.v:80583.5-80583.29" switch \initial - attribute \src "libresoc.v:80898.9-80898.17" + attribute \src "libresoc.v:80583.9-80583.17" case 1'1 case end @@ -130290,14 +129812,14 @@ module \dec30 sync always update \dec30_sv_cr_in $0\dec30_sv_cr_in[2:0] end - attribute \src "libresoc.v:80934.3-80970.6" - process $proc$libresoc.v:80934$3792 + attribute \src "libresoc.v:80619.3-80655.6" + process $proc$libresoc.v:80619$3776 assign { } { } assign { } { } assign $0\dec30_sv_cr_out[2:0] $1\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80935.5-80935.29" + attribute \src "libresoc.v:80620.5-80620.29" switch \initial - attribute \src "libresoc.v:80935.9-80935.17" + attribute \src "libresoc.v:80620.9-80620.17" case 1'1 case end @@ -130349,14 +129871,14 @@ module \dec30 sync always update \dec30_sv_cr_out $0\dec30_sv_cr_out[2:0] end - attribute \src "libresoc.v:80971.3-81007.6" - process $proc$libresoc.v:80971$3793 + attribute \src "libresoc.v:80656.3-80692.6" + process $proc$libresoc.v:80656$3777 assign { } { } assign { } { } assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:80972.5-80972.29" + attribute \src "libresoc.v:80657.5-80657.29" switch \initial - attribute \src "libresoc.v:80972.9-80972.17" + attribute \src "libresoc.v:80657.9-80657.17" case 1'1 case end @@ -130408,14 +129930,14 @@ module \dec30 sync always update \dec30_ldst_len $0\dec30_ldst_len[3:0] end - attribute \src "libresoc.v:81008.3-81044.6" - process $proc$libresoc.v:81008$3794 + attribute \src "libresoc.v:80693.3-80729.6" + process $proc$libresoc.v:80693$3778 assign { } { } assign { } { } assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:81009.5-81009.29" + attribute \src "libresoc.v:80694.5-80694.29" switch \initial - attribute \src "libresoc.v:81009.9-81009.17" + attribute \src "libresoc.v:80694.9-80694.17" case 1'1 case end @@ -130467,14 +129989,14 @@ module \dec30 sync always update \dec30_internal_op $0\dec30_internal_op[6:0] end - attribute \src "libresoc.v:81045.3-81081.6" - process $proc$libresoc.v:81045$3795 + attribute \src "libresoc.v:80730.3-80766.6" + process $proc$libresoc.v:80730$3779 assign { } { } assign { } { } assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] - attribute \src "libresoc.v:81046.5-81046.29" + attribute \src "libresoc.v:80731.5-80731.29" switch \initial - attribute \src "libresoc.v:81046.9-81046.17" + attribute \src "libresoc.v:80731.9-80731.17" case 1'1 case end @@ -130526,14 +130048,14 @@ module \dec30 sync always update \dec30_upd $0\dec30_upd[1:0] end - attribute \src "libresoc.v:81082.3-81118.6" - process $proc$libresoc.v:81082$3796 + attribute \src "libresoc.v:80767.3-80803.6" + process $proc$libresoc.v:80767$3780 assign { } { } assign { } { } assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:81083.5-81083.29" + attribute \src "libresoc.v:80768.5-80768.29" switch \initial - attribute \src "libresoc.v:81083.9-81083.17" + attribute \src "libresoc.v:80768.9-80768.17" case 1'1 case end @@ -130585,14 +130107,14 @@ module \dec30 sync always update \dec30_rc_sel $0\dec30_rc_sel[1:0] end - attribute \src "libresoc.v:81119.3-81155.6" - process $proc$libresoc.v:81119$3797 + attribute \src "libresoc.v:80804.3-80840.6" + process $proc$libresoc.v:80804$3781 assign { } { } assign { } { } assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:81120.5-81120.29" + attribute \src "libresoc.v:80805.5-80805.29" switch \initial - attribute \src "libresoc.v:81120.9-81120.17" + attribute \src "libresoc.v:80805.9-80805.17" case 1'1 case end @@ -130644,14 +130166,14 @@ module \dec30 sync always update \dec30_cry_in $0\dec30_cry_in[1:0] end - attribute \src "libresoc.v:81156.3-81192.6" - process $proc$libresoc.v:81156$3798 + attribute \src "libresoc.v:80841.3-80877.6" + process $proc$libresoc.v:80841$3782 assign { } { } assign { } { } assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:81157.5-81157.29" + attribute \src "libresoc.v:80842.5-80842.29" switch \initial - attribute \src "libresoc.v:81157.9-81157.17" + attribute \src "libresoc.v:80842.9-80842.17" case 1'1 case end @@ -130703,14 +130225,14 @@ module \dec30 sync always update \dec30_asmcode $0\dec30_asmcode[7:0] end - attribute \src "libresoc.v:81193.3-81229.6" - process $proc$libresoc.v:81193$3799 + attribute \src "libresoc.v:80878.3-80914.6" + process $proc$libresoc.v:80878$3783 assign { } { } assign { } { } assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:81194.5-81194.29" + attribute \src "libresoc.v:80879.5-80879.29" switch \initial - attribute \src "libresoc.v:81194.9-81194.17" + attribute \src "libresoc.v:80879.9-80879.17" case 1'1 case end @@ -130762,14 +130284,14 @@ module \dec30 sync always update \dec30_inv_a $0\dec30_inv_a[0:0] end - attribute \src "libresoc.v:81230.3-81266.6" - process $proc$libresoc.v:81230$3800 + attribute \src "libresoc.v:80915.3-80951.6" + process $proc$libresoc.v:80915$3784 assign { } { } assign { } { } assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:81231.5-81231.29" + attribute \src "libresoc.v:80916.5-80916.29" switch \initial - attribute \src "libresoc.v:81231.9-81231.17" + attribute \src "libresoc.v:80916.9-80916.17" case 1'1 case end @@ -130821,14 +130343,14 @@ module \dec30 sync always update \dec30_inv_out $0\dec30_inv_out[0:0] end - attribute \src "libresoc.v:81267.3-81303.6" - process $proc$libresoc.v:81267$3801 + attribute \src "libresoc.v:80952.3-80988.6" + process $proc$libresoc.v:80952$3785 assign { } { } assign { } { } assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:81268.5-81268.29" + attribute \src "libresoc.v:80953.5-80953.29" switch \initial - attribute \src "libresoc.v:81268.9-81268.17" + attribute \src "libresoc.v:80953.9-80953.17" case 1'1 case end @@ -130880,14 +130402,14 @@ module \dec30 sync always update \dec30_cry_out $0\dec30_cry_out[0:0] end - attribute \src "libresoc.v:81304.3-81340.6" - process $proc$libresoc.v:81304$3802 + attribute \src "libresoc.v:80989.3-81025.6" + process $proc$libresoc.v:80989$3786 assign { } { } assign { } { } assign $0\dec30_br[0:0] $1\dec30_br[0:0] - attribute \src "libresoc.v:81305.5-81305.29" + attribute \src "libresoc.v:80990.5-80990.29" switch \initial - attribute \src "libresoc.v:81305.9-81305.17" + attribute \src "libresoc.v:80990.9-80990.17" case 1'1 case end @@ -130939,14 +130461,14 @@ module \dec30 sync always update \dec30_br $0\dec30_br[0:0] end - attribute \src "libresoc.v:81341.3-81377.6" - process $proc$libresoc.v:81341$3803 + attribute \src "libresoc.v:81026.3-81062.6" + process $proc$libresoc.v:81026$3787 assign { } { } assign { } { } assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:81342.5-81342.29" + attribute \src "libresoc.v:81027.5-81027.29" switch \initial - attribute \src "libresoc.v:81342.9-81342.17" + attribute \src "libresoc.v:81027.9-81027.17" case 1'1 case end @@ -130998,14 +130520,14 @@ module \dec30 sync always update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] end - attribute \src "libresoc.v:81378.3-81414.6" - process $proc$libresoc.v:81378$3804 + attribute \src "libresoc.v:81063.3-81099.6" + process $proc$libresoc.v:81063$3788 assign { } { } assign { } { } assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:81379.5-81379.29" + attribute \src "libresoc.v:81064.5-81064.29" switch \initial - attribute \src "libresoc.v:81379.9-81379.17" + attribute \src "libresoc.v:81064.9-81064.17" case 1'1 case end @@ -131057,14 +130579,14 @@ module \dec30 sync always update \dec30_rsrv $0\dec30_rsrv[0:0] end - attribute \src "libresoc.v:81415.3-81451.6" - process $proc$libresoc.v:81415$3805 + attribute \src "libresoc.v:81100.3-81136.6" + process $proc$libresoc.v:81100$3789 assign { } { } assign { } { } assign $0\dec30_form[4:0] $1\dec30_form[4:0] - attribute \src "libresoc.v:81416.5-81416.29" + attribute \src "libresoc.v:81101.5-81101.29" switch \initial - attribute \src "libresoc.v:81416.9-81416.17" + attribute \src "libresoc.v:81101.9-81101.17" case 1'1 case end @@ -131116,14 +130638,14 @@ module \dec30 sync always update \dec30_form $0\dec30_form[4:0] end - attribute \src "libresoc.v:81452.3-81488.6" - process $proc$libresoc.v:81452$3806 + attribute \src "libresoc.v:81137.3-81173.6" + process $proc$libresoc.v:81137$3790 assign { } { } assign { } { } assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:81453.5-81453.29" + attribute \src "libresoc.v:81138.5-81138.29" switch \initial - attribute \src "libresoc.v:81453.9-81453.17" + attribute \src "libresoc.v:81138.9-81138.17" case 1'1 case end @@ -131175,14 +130697,14 @@ module \dec30 sync always update \dec30_is_32b $0\dec30_is_32b[0:0] end - attribute \src "libresoc.v:81489.3-81525.6" - process $proc$libresoc.v:81489$3807 + attribute \src "libresoc.v:81174.3-81210.6" + process $proc$libresoc.v:81174$3791 assign { } { } assign { } { } assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] - attribute \src "libresoc.v:81490.5-81490.29" + attribute \src "libresoc.v:81175.5-81175.29" switch \initial - attribute \src "libresoc.v:81490.9-81490.17" + attribute \src "libresoc.v:81175.9-81175.17" case 1'1 case end @@ -131234,14 +130756,14 @@ module \dec30 sync always update \dec30_sgn $0\dec30_sgn[0:0] end - attribute \src "libresoc.v:81526.3-81562.6" - process $proc$libresoc.v:81526$3808 + attribute \src "libresoc.v:81211.3-81247.6" + process $proc$libresoc.v:81211$3792 assign { } { } assign { } { } assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] - attribute \src "libresoc.v:81527.5-81527.29" + attribute \src "libresoc.v:81212.5-81212.29" switch \initial - attribute \src "libresoc.v:81527.9-81527.17" + attribute \src "libresoc.v:81212.9-81212.17" case 1'1 case end @@ -131293,14 +130815,14 @@ module \dec30 sync always update \dec30_lk $0\dec30_lk[0:0] end - attribute \src "libresoc.v:81563.3-81599.6" - process $proc$libresoc.v:81563$3809 + attribute \src "libresoc.v:81248.3-81284.6" + process $proc$libresoc.v:81248$3793 assign { } { } assign { } { } assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81564.5-81564.29" + attribute \src "libresoc.v:81249.5-81249.29" switch \initial - attribute \src "libresoc.v:81564.9-81564.17" + attribute \src "libresoc.v:81249.9-81249.17" case 1'1 case end @@ -131352,14 +130874,14 @@ module \dec30 sync always update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] end - attribute \src "libresoc.v:81600.3-81636.6" - process $proc$libresoc.v:81600$3810 + attribute \src "libresoc.v:81285.3-81321.6" + process $proc$libresoc.v:81285$3794 assign { } { } assign { } { } assign $0\dec30_SV_Etype[1:0] $1\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81601.5-81601.29" + attribute \src "libresoc.v:81286.5-81286.29" switch \initial - attribute \src "libresoc.v:81601.9-81601.17" + attribute \src "libresoc.v:81286.9-81286.17" case 1'1 case end @@ -131411,14 +130933,14 @@ module \dec30 sync always update \dec30_SV_Etype $0\dec30_SV_Etype[1:0] end - attribute \src "libresoc.v:81637.3-81673.6" - process $proc$libresoc.v:81637$3811 + attribute \src "libresoc.v:81322.3-81358.6" + process $proc$libresoc.v:81322$3795 assign { } { } assign { } { } assign $0\dec30_SV_Ptype[1:0] $1\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:81638.5-81638.29" + attribute \src "libresoc.v:81323.5-81323.29" switch \initial - attribute \src "libresoc.v:81638.9-81638.17" + attribute \src "libresoc.v:81323.9-81323.17" case 1'1 case end @@ -131470,14 +130992,14 @@ module \dec30 sync always update \dec30_SV_Ptype $0\dec30_SV_Ptype[1:0] end - attribute \src "libresoc.v:81674.3-81710.6" - process $proc$libresoc.v:81674$3812 + attribute \src "libresoc.v:81359.3-81395.6" + process $proc$libresoc.v:81359$3796 assign { } { } assign { } { } assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81675.5-81675.29" + attribute \src "libresoc.v:81360.5-81360.29" switch \initial - attribute \src "libresoc.v:81675.9-81675.17" + attribute \src "libresoc.v:81360.9-81360.17" case 1'1 case end @@ -131529,14 +131051,14 @@ module \dec30 sync always update \dec30_in1_sel $0\dec30_in1_sel[2:0] end - attribute \src "libresoc.v:81711.3-81747.6" - process $proc$libresoc.v:81711$3813 + attribute \src "libresoc.v:81396.3-81432.6" + process $proc$libresoc.v:81396$3797 assign { } { } assign { } { } assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81712.5-81712.29" + attribute \src "libresoc.v:81397.5-81397.29" switch \initial - attribute \src "libresoc.v:81712.9-81712.17" + attribute \src "libresoc.v:81397.9-81397.17" case 1'1 case end @@ -131588,14 +131110,14 @@ module \dec30 sync always update \dec30_in2_sel $0\dec30_in2_sel[3:0] end - attribute \src "libresoc.v:81748.3-81784.6" - process $proc$libresoc.v:81748$3814 + attribute \src "libresoc.v:81433.3-81469.6" + process $proc$libresoc.v:81433$3798 assign { } { } assign { } { } assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:81749.5-81749.29" + attribute \src "libresoc.v:81434.5-81434.29" switch \initial - attribute \src "libresoc.v:81749.9-81749.17" + attribute \src "libresoc.v:81434.9-81434.17" case 1'1 case end @@ -131647,14 +131169,14 @@ module \dec30 sync always update \dec30_in3_sel $0\dec30_in3_sel[1:0] end - attribute \src "libresoc.v:81785.3-81821.6" - process $proc$libresoc.v:81785$3815 + attribute \src "libresoc.v:81470.3-81506.6" + process $proc$libresoc.v:81470$3799 assign { } { } assign { } { } assign $0\dec30_out_sel[2:0] $1\dec30_out_sel[2:0] - attribute \src "libresoc.v:81786.5-81786.29" + attribute \src "libresoc.v:81471.5-81471.29" switch \initial - attribute \src "libresoc.v:81786.9-81786.17" + attribute \src "libresoc.v:81471.9-81471.17" case 1'1 case end @@ -131708,144 +131230,144 @@ module \dec30 end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:81827.1-90475.10" +attribute \src "libresoc.v:81512.1-90160.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" attribute \generator "nMigen" module \dec31 - attribute \src "libresoc.v:88686.3-88746.6" + attribute \src "libresoc.v:88371.3-88431.6" wire width 2 $0\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88747.3-88807.6" + attribute \src "libresoc.v:88432.3-88492.6" wire width 2 $0\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:88625.3-88685.6" + attribute \src "libresoc.v:88310.3-88370.6" wire width 8 $0\dec31_asmcode[7:0] - attribute \src "libresoc.v:90028.3-90088.6" + attribute \src "libresoc.v:89713.3-89773.6" wire $0\dec31_br[0:0] - attribute \src "libresoc.v:89052.3-89112.6" + attribute \src "libresoc.v:88737.3-88797.6" wire width 3 $0\dec31_cr_in[2:0] - attribute \src "libresoc.v:89113.3-89173.6" + attribute \src "libresoc.v:88798.3-88858.6" wire width 3 $0\dec31_cr_out[2:0] - attribute \src "libresoc.v:89784.3-89844.6" + attribute \src "libresoc.v:89469.3-89529.6" wire width 2 $0\dec31_cry_in[1:0] - attribute \src "libresoc.v:89967.3-90027.6" + attribute \src "libresoc.v:89652.3-89712.6" wire $0\dec31_cry_out[0:0] - attribute \src "libresoc.v:88564.3-88624.6" + attribute \src "libresoc.v:88249.3-88309.6" wire width 5 $0\dec31_form[4:0] - attribute \src "libresoc.v:88442.3-88502.6" + attribute \src "libresoc.v:88127.3-88187.6" wire width 14 $0\dec31_function_unit[13:0] - attribute \src "libresoc.v:88808.3-88868.6" + attribute \src "libresoc.v:88493.3-88553.6" wire width 3 $0\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88869.3-88929.6" + attribute \src "libresoc.v:88554.3-88614.6" wire width 4 $0\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88930.3-88990.6" + attribute \src "libresoc.v:88615.3-88675.6" wire width 2 $0\dec31_in3_sel[1:0] - attribute \src "libresoc.v:88503.3-88563.6" + attribute \src "libresoc.v:88188.3-88248.6" wire width 7 $0\dec31_internal_op[6:0] - attribute \src "libresoc.v:89845.3-89905.6" + attribute \src "libresoc.v:89530.3-89590.6" wire $0\dec31_inv_a[0:0] - attribute \src "libresoc.v:89906.3-89966.6" + attribute \src "libresoc.v:89591.3-89651.6" wire $0\dec31_inv_out[0:0] - attribute \src "libresoc.v:90211.3-90271.6" + attribute \src "libresoc.v:89896.3-89956.6" wire $0\dec31_is_32b[0:0] - attribute \src "libresoc.v:89601.3-89661.6" + attribute \src "libresoc.v:89286.3-89346.6" wire width 4 $0\dec31_ldst_len[3:0] - attribute \src "libresoc.v:90333.3-90393.6" + attribute \src "libresoc.v:90018.3-90078.6" wire $0\dec31_lk[0:0] - attribute \src "libresoc.v:88991.3-89051.6" + attribute \src "libresoc.v:88676.3-88736.6" wire width 3 $0\dec31_out_sel[2:0] - attribute \src "libresoc.v:89723.3-89783.6" + attribute \src "libresoc.v:89408.3-89468.6" wire width 2 $0\dec31_rc_sel[1:0] - attribute \src "libresoc.v:90150.3-90210.6" + attribute \src "libresoc.v:89835.3-89895.6" wire $0\dec31_rsrv[0:0] - attribute \src "libresoc.v:90394.3-90454.6" + attribute \src "libresoc.v:90079.3-90139.6" wire $0\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:90272.3-90332.6" + attribute \src "libresoc.v:89957.3-90017.6" wire $0\dec31_sgn[0:0] - attribute \src "libresoc.v:90089.3-90149.6" + attribute \src "libresoc.v:89774.3-89834.6" wire $0\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:89479.3-89539.6" + attribute \src "libresoc.v:89164.3-89224.6" wire width 3 $0\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:89540.3-89600.6" + attribute \src "libresoc.v:89225.3-89285.6" wire width 3 $0\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:89174.3-89234.6" + attribute \src "libresoc.v:88859.3-88919.6" wire width 3 $0\dec31_sv_in1[2:0] - attribute \src "libresoc.v:89235.3-89295.6" + attribute \src "libresoc.v:88920.3-88980.6" wire width 3 $0\dec31_sv_in2[2:0] - attribute \src "libresoc.v:89296.3-89356.6" + attribute \src "libresoc.v:88981.3-89041.6" wire width 3 $0\dec31_sv_in3[2:0] - attribute \src "libresoc.v:89418.3-89478.6" + attribute \src "libresoc.v:89103.3-89163.6" wire width 3 $0\dec31_sv_out2[2:0] - attribute \src "libresoc.v:89357.3-89417.6" + attribute \src "libresoc.v:89042.3-89102.6" wire width 3 $0\dec31_sv_out[2:0] - attribute \src "libresoc.v:89662.3-89722.6" + attribute \src "libresoc.v:89347.3-89407.6" wire width 2 $0\dec31_upd[1:0] - attribute \src "libresoc.v:81828.7-81828.20" + attribute \src "libresoc.v:81513.7-81513.20" wire $0\initial[0:0] - attribute \src "libresoc.v:88686.3-88746.6" + attribute \src "libresoc.v:88371.3-88431.6" wire width 2 $1\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88747.3-88807.6" + attribute \src "libresoc.v:88432.3-88492.6" wire width 2 $1\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:88625.3-88685.6" + attribute \src "libresoc.v:88310.3-88370.6" wire width 8 $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:90028.3-90088.6" + attribute \src "libresoc.v:89713.3-89773.6" wire $1\dec31_br[0:0] - attribute \src "libresoc.v:89052.3-89112.6" + attribute \src "libresoc.v:88737.3-88797.6" wire width 3 $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:89113.3-89173.6" + attribute \src "libresoc.v:88798.3-88858.6" wire width 3 $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:89784.3-89844.6" + attribute \src "libresoc.v:89469.3-89529.6" wire width 2 $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:89967.3-90027.6" + attribute \src "libresoc.v:89652.3-89712.6" wire $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:88564.3-88624.6" + attribute \src "libresoc.v:88249.3-88309.6" wire width 5 $1\dec31_form[4:0] - attribute \src "libresoc.v:88442.3-88502.6" + attribute \src "libresoc.v:88127.3-88187.6" wire width 14 $1\dec31_function_unit[13:0] - attribute \src "libresoc.v:88808.3-88868.6" + attribute \src "libresoc.v:88493.3-88553.6" wire width 3 $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88869.3-88929.6" + attribute \src "libresoc.v:88554.3-88614.6" wire width 4 $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88930.3-88990.6" + attribute \src "libresoc.v:88615.3-88675.6" wire width 2 $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:88503.3-88563.6" + attribute \src "libresoc.v:88188.3-88248.6" wire width 7 $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:89845.3-89905.6" + attribute \src "libresoc.v:89530.3-89590.6" wire $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:89906.3-89966.6" + attribute \src "libresoc.v:89591.3-89651.6" wire $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:90211.3-90271.6" + attribute \src "libresoc.v:89896.3-89956.6" wire $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:89601.3-89661.6" + attribute \src "libresoc.v:89286.3-89346.6" wire width 4 $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:90333.3-90393.6" + attribute \src "libresoc.v:90018.3-90078.6" wire $1\dec31_lk[0:0] - attribute \src "libresoc.v:88991.3-89051.6" + attribute \src "libresoc.v:88676.3-88736.6" wire width 3 $1\dec31_out_sel[2:0] - attribute \src "libresoc.v:89723.3-89783.6" + attribute \src "libresoc.v:89408.3-89468.6" wire width 2 $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:90150.3-90210.6" + attribute \src "libresoc.v:89835.3-89895.6" wire $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:90394.3-90454.6" + attribute \src "libresoc.v:90079.3-90139.6" wire $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:90272.3-90332.6" + attribute \src "libresoc.v:89957.3-90017.6" wire $1\dec31_sgn[0:0] - attribute \src "libresoc.v:90089.3-90149.6" + attribute \src "libresoc.v:89774.3-89834.6" wire $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:89479.3-89539.6" + attribute \src "libresoc.v:89164.3-89224.6" wire width 3 $1\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:89540.3-89600.6" + attribute \src "libresoc.v:89225.3-89285.6" wire width 3 $1\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:89174.3-89234.6" + attribute \src "libresoc.v:88859.3-88919.6" wire width 3 $1\dec31_sv_in1[2:0] - attribute \src "libresoc.v:89235.3-89295.6" + attribute \src "libresoc.v:88920.3-88980.6" wire width 3 $1\dec31_sv_in2[2:0] - attribute \src "libresoc.v:89296.3-89356.6" + attribute \src "libresoc.v:88981.3-89041.6" wire width 3 $1\dec31_sv_in3[2:0] - attribute \src "libresoc.v:89418.3-89478.6" + attribute \src "libresoc.v:89103.3-89163.6" wire width 3 $1\dec31_sv_out2[2:0] - attribute \src "libresoc.v:89357.3-89417.6" + attribute \src "libresoc.v:89042.3-89102.6" wire width 3 $1\dec31_sv_out[2:0] - attribute \src "libresoc.v:89662.3-89722.6" + attribute \src "libresoc.v:89347.3-89407.6" wire width 2 $1\dec31_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -137773,7 +137295,7 @@ module \dec31 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_upd - attribute \src "libresoc.v:81828.7-81828.15" + attribute \src "libresoc.v:81513.7-81513.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in @@ -137782,7 +137304,7 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:87794.18-87829.4" + attribute \src "libresoc.v:87479.18-87514.4" cell \dec31_dec_sub0 \dec31_dec_sub0 connect \dec31_dec_sub0_SV_Etype \dec31_dec_sub0_dec31_dec_sub0_SV_Etype connect \dec31_dec_sub0_SV_Ptype \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype @@ -137820,7 +137342,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87830.19-87865.4" + attribute \src "libresoc.v:87515.19-87550.4" cell \dec31_dec_sub10 \dec31_dec_sub10 connect \dec31_dec_sub10_SV_Etype \dec31_dec_sub10_dec31_dec_sub10_SV_Etype connect \dec31_dec_sub10_SV_Ptype \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype @@ -137858,7 +137380,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub10_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87866.19-87901.4" + attribute \src "libresoc.v:87551.19-87586.4" cell \dec31_dec_sub11 \dec31_dec_sub11 connect \dec31_dec_sub11_SV_Etype \dec31_dec_sub11_dec31_dec_sub11_SV_Etype connect \dec31_dec_sub11_SV_Ptype \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype @@ -137896,7 +137418,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87902.19-87937.4" + attribute \src "libresoc.v:87587.19-87622.4" cell \dec31_dec_sub15 \dec31_dec_sub15 connect \dec31_dec_sub15_SV_Etype \dec31_dec_sub15_dec31_dec_sub15_SV_Etype connect \dec31_dec_sub15_SV_Ptype \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype @@ -137934,7 +137456,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub15_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87938.19-87973.4" + attribute \src "libresoc.v:87623.19-87658.4" cell \dec31_dec_sub16 \dec31_dec_sub16 connect \dec31_dec_sub16_SV_Etype \dec31_dec_sub16_dec31_dec_sub16_SV_Etype connect \dec31_dec_sub16_SV_Ptype \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype @@ -137972,7 +137494,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub16_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87974.19-88009.4" + attribute \src "libresoc.v:87659.19-87694.4" cell \dec31_dec_sub18 \dec31_dec_sub18 connect \dec31_dec_sub18_SV_Etype \dec31_dec_sub18_dec31_dec_sub18_SV_Etype connect \dec31_dec_sub18_SV_Ptype \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype @@ -138010,7 +137532,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub18_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88010.19-88045.4" + attribute \src "libresoc.v:87695.19-87730.4" cell \dec31_dec_sub19 \dec31_dec_sub19 connect \dec31_dec_sub19_SV_Etype \dec31_dec_sub19_dec31_dec_sub19_SV_Etype connect \dec31_dec_sub19_SV_Ptype \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype @@ -138048,7 +137570,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88046.19-88081.4" + attribute \src "libresoc.v:87731.19-87766.4" cell \dec31_dec_sub20 \dec31_dec_sub20 connect \dec31_dec_sub20_SV_Etype \dec31_dec_sub20_dec31_dec_sub20_SV_Etype connect \dec31_dec_sub20_SV_Ptype \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype @@ -138086,7 +137608,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub20_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88082.19-88117.4" + attribute \src "libresoc.v:87767.19-87802.4" cell \dec31_dec_sub21 \dec31_dec_sub21 connect \dec31_dec_sub21_SV_Etype \dec31_dec_sub21_dec31_dec_sub21_SV_Etype connect \dec31_dec_sub21_SV_Ptype \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype @@ -138124,7 +137646,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub21_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88118.19-88153.4" + attribute \src "libresoc.v:87803.19-87838.4" cell \dec31_dec_sub22 \dec31_dec_sub22 connect \dec31_dec_sub22_SV_Etype \dec31_dec_sub22_dec31_dec_sub22_SV_Etype connect \dec31_dec_sub22_SV_Ptype \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype @@ -138162,7 +137684,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88154.19-88189.4" + attribute \src "libresoc.v:87839.19-87874.4" cell \dec31_dec_sub23 \dec31_dec_sub23 connect \dec31_dec_sub23_SV_Etype \dec31_dec_sub23_dec31_dec_sub23_SV_Etype connect \dec31_dec_sub23_SV_Ptype \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype @@ -138200,7 +137722,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub23_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88190.19-88225.4" + attribute \src "libresoc.v:87875.19-87910.4" cell \dec31_dec_sub24 \dec31_dec_sub24 connect \dec31_dec_sub24_SV_Etype \dec31_dec_sub24_dec31_dec_sub24_SV_Etype connect \dec31_dec_sub24_SV_Ptype \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype @@ -138238,7 +137760,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub24_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88226.19-88261.4" + attribute \src "libresoc.v:87911.19-87946.4" cell \dec31_dec_sub26 \dec31_dec_sub26 connect \dec31_dec_sub26_SV_Etype \dec31_dec_sub26_dec31_dec_sub26_SV_Etype connect \dec31_dec_sub26_SV_Ptype \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype @@ -138276,7 +137798,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88262.19-88297.4" + attribute \src "libresoc.v:87947.19-87982.4" cell \dec31_dec_sub27 \dec31_dec_sub27 connect \dec31_dec_sub27_SV_Etype \dec31_dec_sub27_dec31_dec_sub27_SV_Etype connect \dec31_dec_sub27_SV_Ptype \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype @@ -138314,7 +137836,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub27_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88298.19-88333.4" + attribute \src "libresoc.v:87983.19-88018.4" cell \dec31_dec_sub28 \dec31_dec_sub28 connect \dec31_dec_sub28_SV_Etype \dec31_dec_sub28_dec31_dec_sub28_SV_Etype connect \dec31_dec_sub28_SV_Ptype \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype @@ -138352,7 +137874,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub28_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88334.18-88369.4" + attribute \src "libresoc.v:88019.18-88054.4" cell \dec31_dec_sub4 \dec31_dec_sub4 connect \dec31_dec_sub4_SV_Etype \dec31_dec_sub4_dec31_dec_sub4_SV_Etype connect \dec31_dec_sub4_SV_Ptype \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype @@ -138390,7 +137912,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub4_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88370.18-88405.4" + attribute \src "libresoc.v:88055.18-88090.4" cell \dec31_dec_sub8 \dec31_dec_sub8 connect \dec31_dec_sub8_SV_Etype \dec31_dec_sub8_dec31_dec_sub8_SV_Etype connect \dec31_dec_sub8_SV_Ptype \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype @@ -138428,7 +137950,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub8_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88406.18-88441.4" + attribute \src "libresoc.v:88091.18-88126.4" cell \dec31_dec_sub9 \dec31_dec_sub9 connect \dec31_dec_sub9_SV_Etype \dec31_dec_sub9_dec31_dec_sub9_SV_Etype connect \dec31_dec_sub9_SV_Ptype \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype @@ -138465,22 +137987,22 @@ module \dec31 connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd connect \opcode_in \dec31_dec_sub9_opcode_in end - attribute \src "libresoc.v:81828.7-81828.20" - process $proc$libresoc.v:81828$3850 + attribute \src "libresoc.v:81513.7-81513.20" + process $proc$libresoc.v:81513$3834 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:88442.3-88502.6" - process $proc$libresoc.v:88442$3817 + attribute \src "libresoc.v:88127.3-88187.6" + process $proc$libresoc.v:88127$3801 assign { } { } assign { } { } assign $0\dec31_function_unit[13:0] $1\dec31_function_unit[13:0] - attribute \src "libresoc.v:88443.5-88443.29" + attribute \src "libresoc.v:88128.5-88128.29" switch \initial - attribute \src "libresoc.v:88443.9-88443.17" + attribute \src "libresoc.v:88128.9-88128.17" case 1'1 case end @@ -138564,14 +138086,14 @@ module \dec31 sync always update \dec31_function_unit $0\dec31_function_unit[13:0] end - attribute \src "libresoc.v:88503.3-88563.6" - process $proc$libresoc.v:88503$3818 + attribute \src "libresoc.v:88188.3-88248.6" + process $proc$libresoc.v:88188$3802 assign { } { } assign { } { } assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:88504.5-88504.29" + attribute \src "libresoc.v:88189.5-88189.29" switch \initial - attribute \src "libresoc.v:88504.9-88504.17" + attribute \src "libresoc.v:88189.9-88189.17" case 1'1 case end @@ -138655,14 +138177,14 @@ module \dec31 sync always update \dec31_internal_op $0\dec31_internal_op[6:0] end - attribute \src "libresoc.v:88564.3-88624.6" - process $proc$libresoc.v:88564$3819 + attribute \src "libresoc.v:88249.3-88309.6" + process $proc$libresoc.v:88249$3803 assign { } { } assign { } { } assign $0\dec31_form[4:0] $1\dec31_form[4:0] - attribute \src "libresoc.v:88565.5-88565.29" + attribute \src "libresoc.v:88250.5-88250.29" switch \initial - attribute \src "libresoc.v:88565.9-88565.17" + attribute \src "libresoc.v:88250.9-88250.17" case 1'1 case end @@ -138746,14 +138268,14 @@ module \dec31 sync always update \dec31_form $0\dec31_form[4:0] end - attribute \src "libresoc.v:88625.3-88685.6" - process $proc$libresoc.v:88625$3820 + attribute \src "libresoc.v:88310.3-88370.6" + process $proc$libresoc.v:88310$3804 assign { } { } assign { } { } assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:88626.5-88626.29" + attribute \src "libresoc.v:88311.5-88311.29" switch \initial - attribute \src "libresoc.v:88626.9-88626.17" + attribute \src "libresoc.v:88311.9-88311.17" case 1'1 case end @@ -138837,14 +138359,14 @@ module \dec31 sync always update \dec31_asmcode $0\dec31_asmcode[7:0] end - attribute \src "libresoc.v:88686.3-88746.6" - process $proc$libresoc.v:88686$3821 + attribute \src "libresoc.v:88371.3-88431.6" + process $proc$libresoc.v:88371$3805 assign { } { } assign { } { } assign $0\dec31_SV_Etype[1:0] $1\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88687.5-88687.29" + attribute \src "libresoc.v:88372.5-88372.29" switch \initial - attribute \src "libresoc.v:88687.9-88687.17" + attribute \src "libresoc.v:88372.9-88372.17" case 1'1 case end @@ -138928,14 +138450,14 @@ module \dec31 sync always update \dec31_SV_Etype $0\dec31_SV_Etype[1:0] end - attribute \src "libresoc.v:88747.3-88807.6" - process $proc$libresoc.v:88747$3822 + attribute \src "libresoc.v:88432.3-88492.6" + process $proc$libresoc.v:88432$3806 assign { } { } assign { } { } assign $0\dec31_SV_Ptype[1:0] $1\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:88748.5-88748.29" + attribute \src "libresoc.v:88433.5-88433.29" switch \initial - attribute \src "libresoc.v:88748.9-88748.17" + attribute \src "libresoc.v:88433.9-88433.17" case 1'1 case end @@ -139019,14 +138541,14 @@ module \dec31 sync always update \dec31_SV_Ptype $0\dec31_SV_Ptype[1:0] end - attribute \src "libresoc.v:88808.3-88868.6" - process $proc$libresoc.v:88808$3823 + attribute \src "libresoc.v:88493.3-88553.6" + process $proc$libresoc.v:88493$3807 assign { } { } assign { } { } assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88809.5-88809.29" + attribute \src "libresoc.v:88494.5-88494.29" switch \initial - attribute \src "libresoc.v:88809.9-88809.17" + attribute \src "libresoc.v:88494.9-88494.17" case 1'1 case end @@ -139110,14 +138632,14 @@ module \dec31 sync always update \dec31_in1_sel $0\dec31_in1_sel[2:0] end - attribute \src "libresoc.v:88869.3-88929.6" - process $proc$libresoc.v:88869$3824 + attribute \src "libresoc.v:88554.3-88614.6" + process $proc$libresoc.v:88554$3808 assign { } { } assign { } { } assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88870.5-88870.29" + attribute \src "libresoc.v:88555.5-88555.29" switch \initial - attribute \src "libresoc.v:88870.9-88870.17" + attribute \src "libresoc.v:88555.9-88555.17" case 1'1 case end @@ -139201,14 +138723,14 @@ module \dec31 sync always update \dec31_in2_sel $0\dec31_in2_sel[3:0] end - attribute \src "libresoc.v:88930.3-88990.6" - process $proc$libresoc.v:88930$3825 + attribute \src "libresoc.v:88615.3-88675.6" + process $proc$libresoc.v:88615$3809 assign { } { } assign { } { } assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:88931.5-88931.29" + attribute \src "libresoc.v:88616.5-88616.29" switch \initial - attribute \src "libresoc.v:88931.9-88931.17" + attribute \src "libresoc.v:88616.9-88616.17" case 1'1 case end @@ -139292,14 +138814,14 @@ module \dec31 sync always update \dec31_in3_sel $0\dec31_in3_sel[1:0] end - attribute \src "libresoc.v:88991.3-89051.6" - process $proc$libresoc.v:88991$3826 + attribute \src "libresoc.v:88676.3-88736.6" + process $proc$libresoc.v:88676$3810 assign { } { } assign { } { } assign $0\dec31_out_sel[2:0] $1\dec31_out_sel[2:0] - attribute \src "libresoc.v:88992.5-88992.29" + attribute \src "libresoc.v:88677.5-88677.29" switch \initial - attribute \src "libresoc.v:88992.9-88992.17" + attribute \src "libresoc.v:88677.9-88677.17" case 1'1 case end @@ -139383,14 +138905,14 @@ module \dec31 sync always update \dec31_out_sel $0\dec31_out_sel[2:0] end - attribute \src "libresoc.v:89052.3-89112.6" - process $proc$libresoc.v:89052$3827 + attribute \src "libresoc.v:88737.3-88797.6" + process $proc$libresoc.v:88737$3811 assign { } { } assign { } { } assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:89053.5-89053.29" + attribute \src "libresoc.v:88738.5-88738.29" switch \initial - attribute \src "libresoc.v:89053.9-89053.17" + attribute \src "libresoc.v:88738.9-88738.17" case 1'1 case end @@ -139474,14 +138996,14 @@ module \dec31 sync always update \dec31_cr_in $0\dec31_cr_in[2:0] end - attribute \src "libresoc.v:89113.3-89173.6" - process $proc$libresoc.v:89113$3828 + attribute \src "libresoc.v:88798.3-88858.6" + process $proc$libresoc.v:88798$3812 assign { } { } assign { } { } assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:89114.5-89114.29" + attribute \src "libresoc.v:88799.5-88799.29" switch \initial - attribute \src "libresoc.v:89114.9-89114.17" + attribute \src "libresoc.v:88799.9-88799.17" case 1'1 case end @@ -139565,14 +139087,14 @@ module \dec31 sync always update \dec31_cr_out $0\dec31_cr_out[2:0] end - attribute \src "libresoc.v:89174.3-89234.6" - process $proc$libresoc.v:89174$3829 + attribute \src "libresoc.v:88859.3-88919.6" + process $proc$libresoc.v:88859$3813 assign { } { } assign { } { } assign $0\dec31_sv_in1[2:0] $1\dec31_sv_in1[2:0] - attribute \src "libresoc.v:89175.5-89175.29" + attribute \src "libresoc.v:88860.5-88860.29" switch \initial - attribute \src "libresoc.v:89175.9-89175.17" + attribute \src "libresoc.v:88860.9-88860.17" case 1'1 case end @@ -139656,14 +139178,14 @@ module \dec31 sync always update \dec31_sv_in1 $0\dec31_sv_in1[2:0] end - attribute \src "libresoc.v:89235.3-89295.6" - process $proc$libresoc.v:89235$3830 + attribute \src "libresoc.v:88920.3-88980.6" + process $proc$libresoc.v:88920$3814 assign { } { } assign { } { } assign $0\dec31_sv_in2[2:0] $1\dec31_sv_in2[2:0] - attribute \src "libresoc.v:89236.5-89236.29" + attribute \src "libresoc.v:88921.5-88921.29" switch \initial - attribute \src "libresoc.v:89236.9-89236.17" + attribute \src "libresoc.v:88921.9-88921.17" case 1'1 case end @@ -139747,14 +139269,14 @@ module \dec31 sync always update \dec31_sv_in2 $0\dec31_sv_in2[2:0] end - attribute \src "libresoc.v:89296.3-89356.6" - process $proc$libresoc.v:89296$3831 + attribute \src "libresoc.v:88981.3-89041.6" + process $proc$libresoc.v:88981$3815 assign { } { } assign { } { } assign $0\dec31_sv_in3[2:0] $1\dec31_sv_in3[2:0] - attribute \src "libresoc.v:89297.5-89297.29" + attribute \src "libresoc.v:88982.5-88982.29" switch \initial - attribute \src "libresoc.v:89297.9-89297.17" + attribute \src "libresoc.v:88982.9-88982.17" case 1'1 case end @@ -139838,14 +139360,14 @@ module \dec31 sync always update \dec31_sv_in3 $0\dec31_sv_in3[2:0] end - attribute \src "libresoc.v:89357.3-89417.6" - process $proc$libresoc.v:89357$3832 + attribute \src "libresoc.v:89042.3-89102.6" + process $proc$libresoc.v:89042$3816 assign { } { } assign { } { } assign $0\dec31_sv_out[2:0] $1\dec31_sv_out[2:0] - attribute \src "libresoc.v:89358.5-89358.29" + attribute \src "libresoc.v:89043.5-89043.29" switch \initial - attribute \src "libresoc.v:89358.9-89358.17" + attribute \src "libresoc.v:89043.9-89043.17" case 1'1 case end @@ -139929,14 +139451,14 @@ module \dec31 sync always update \dec31_sv_out $0\dec31_sv_out[2:0] end - attribute \src "libresoc.v:89418.3-89478.6" - process $proc$libresoc.v:89418$3833 + attribute \src "libresoc.v:89103.3-89163.6" + process $proc$libresoc.v:89103$3817 assign { } { } assign { } { } assign $0\dec31_sv_out2[2:0] $1\dec31_sv_out2[2:0] - attribute \src "libresoc.v:89419.5-89419.29" + attribute \src "libresoc.v:89104.5-89104.29" switch \initial - attribute \src "libresoc.v:89419.9-89419.17" + attribute \src "libresoc.v:89104.9-89104.17" case 1'1 case end @@ -140020,14 +139542,14 @@ module \dec31 sync always update \dec31_sv_out2 $0\dec31_sv_out2[2:0] end - attribute \src "libresoc.v:89479.3-89539.6" - process $proc$libresoc.v:89479$3834 + attribute \src "libresoc.v:89164.3-89224.6" + process $proc$libresoc.v:89164$3818 assign { } { } assign { } { } assign $0\dec31_sv_cr_in[2:0] $1\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:89480.5-89480.29" + attribute \src "libresoc.v:89165.5-89165.29" switch \initial - attribute \src "libresoc.v:89480.9-89480.17" + attribute \src "libresoc.v:89165.9-89165.17" case 1'1 case end @@ -140111,14 +139633,14 @@ module \dec31 sync always update \dec31_sv_cr_in $0\dec31_sv_cr_in[2:0] end - attribute \src "libresoc.v:89540.3-89600.6" - process $proc$libresoc.v:89540$3835 + attribute \src "libresoc.v:89225.3-89285.6" + process $proc$libresoc.v:89225$3819 assign { } { } assign { } { } assign $0\dec31_sv_cr_out[2:0] $1\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:89541.5-89541.29" + attribute \src "libresoc.v:89226.5-89226.29" switch \initial - attribute \src "libresoc.v:89541.9-89541.17" + attribute \src "libresoc.v:89226.9-89226.17" case 1'1 case end @@ -140202,14 +139724,14 @@ module \dec31 sync always update \dec31_sv_cr_out $0\dec31_sv_cr_out[2:0] end - attribute \src "libresoc.v:89601.3-89661.6" - process $proc$libresoc.v:89601$3836 + attribute \src "libresoc.v:89286.3-89346.6" + process $proc$libresoc.v:89286$3820 assign { } { } assign { } { } assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:89602.5-89602.29" + attribute \src "libresoc.v:89287.5-89287.29" switch \initial - attribute \src "libresoc.v:89602.9-89602.17" + attribute \src "libresoc.v:89287.9-89287.17" case 1'1 case end @@ -140293,14 +139815,14 @@ module \dec31 sync always update \dec31_ldst_len $0\dec31_ldst_len[3:0] end - attribute \src "libresoc.v:89662.3-89722.6" - process $proc$libresoc.v:89662$3837 + attribute \src "libresoc.v:89347.3-89407.6" + process $proc$libresoc.v:89347$3821 assign { } { } assign { } { } assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] - attribute \src "libresoc.v:89663.5-89663.29" + attribute \src "libresoc.v:89348.5-89348.29" switch \initial - attribute \src "libresoc.v:89663.9-89663.17" + attribute \src "libresoc.v:89348.9-89348.17" case 1'1 case end @@ -140384,14 +139906,14 @@ module \dec31 sync always update \dec31_upd $0\dec31_upd[1:0] end - attribute \src "libresoc.v:89723.3-89783.6" - process $proc$libresoc.v:89723$3838 + attribute \src "libresoc.v:89408.3-89468.6" + process $proc$libresoc.v:89408$3822 assign { } { } assign { } { } assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:89724.5-89724.29" + attribute \src "libresoc.v:89409.5-89409.29" switch \initial - attribute \src "libresoc.v:89724.9-89724.17" + attribute \src "libresoc.v:89409.9-89409.17" case 1'1 case end @@ -140475,14 +139997,14 @@ module \dec31 sync always update \dec31_rc_sel $0\dec31_rc_sel[1:0] end - attribute \src "libresoc.v:89784.3-89844.6" - process $proc$libresoc.v:89784$3839 + attribute \src "libresoc.v:89469.3-89529.6" + process $proc$libresoc.v:89469$3823 assign { } { } assign { } { } assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:89785.5-89785.29" + attribute \src "libresoc.v:89470.5-89470.29" switch \initial - attribute \src "libresoc.v:89785.9-89785.17" + attribute \src "libresoc.v:89470.9-89470.17" case 1'1 case end @@ -140566,14 +140088,14 @@ module \dec31 sync always update \dec31_cry_in $0\dec31_cry_in[1:0] end - attribute \src "libresoc.v:89845.3-89905.6" - process $proc$libresoc.v:89845$3840 + attribute \src "libresoc.v:89530.3-89590.6" + process $proc$libresoc.v:89530$3824 assign { } { } assign { } { } assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:89846.5-89846.29" + attribute \src "libresoc.v:89531.5-89531.29" switch \initial - attribute \src "libresoc.v:89846.9-89846.17" + attribute \src "libresoc.v:89531.9-89531.17" case 1'1 case end @@ -140657,14 +140179,14 @@ module \dec31 sync always update \dec31_inv_a $0\dec31_inv_a[0:0] end - attribute \src "libresoc.v:89906.3-89966.6" - process $proc$libresoc.v:89906$3841 + attribute \src "libresoc.v:89591.3-89651.6" + process $proc$libresoc.v:89591$3825 assign { } { } assign { } { } assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:89907.5-89907.29" + attribute \src "libresoc.v:89592.5-89592.29" switch \initial - attribute \src "libresoc.v:89907.9-89907.17" + attribute \src "libresoc.v:89592.9-89592.17" case 1'1 case end @@ -140748,14 +140270,14 @@ module \dec31 sync always update \dec31_inv_out $0\dec31_inv_out[0:0] end - attribute \src "libresoc.v:89967.3-90027.6" - process $proc$libresoc.v:89967$3842 + attribute \src "libresoc.v:89652.3-89712.6" + process $proc$libresoc.v:89652$3826 assign { } { } assign { } { } assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:89968.5-89968.29" + attribute \src "libresoc.v:89653.5-89653.29" switch \initial - attribute \src "libresoc.v:89968.9-89968.17" + attribute \src "libresoc.v:89653.9-89653.17" case 1'1 case end @@ -140839,14 +140361,14 @@ module \dec31 sync always update \dec31_cry_out $0\dec31_cry_out[0:0] end - attribute \src "libresoc.v:90028.3-90088.6" - process $proc$libresoc.v:90028$3843 + attribute \src "libresoc.v:89713.3-89773.6" + process $proc$libresoc.v:89713$3827 assign { } { } assign { } { } assign $0\dec31_br[0:0] $1\dec31_br[0:0] - attribute \src "libresoc.v:90029.5-90029.29" + attribute \src "libresoc.v:89714.5-89714.29" switch \initial - attribute \src "libresoc.v:90029.9-90029.17" + attribute \src "libresoc.v:89714.9-89714.17" case 1'1 case end @@ -140930,14 +140452,14 @@ module \dec31 sync always update \dec31_br $0\dec31_br[0:0] end - attribute \src "libresoc.v:90089.3-90149.6" - process $proc$libresoc.v:90089$3844 + attribute \src "libresoc.v:89774.3-89834.6" + process $proc$libresoc.v:89774$3828 assign { } { } assign { } { } assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:90090.5-90090.29" + attribute \src "libresoc.v:89775.5-89775.29" switch \initial - attribute \src "libresoc.v:90090.9-90090.17" + attribute \src "libresoc.v:89775.9-89775.17" case 1'1 case end @@ -141021,14 +140543,14 @@ module \dec31 sync always update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] end - attribute \src "libresoc.v:90150.3-90210.6" - process $proc$libresoc.v:90150$3845 + attribute \src "libresoc.v:89835.3-89895.6" + process $proc$libresoc.v:89835$3829 assign { } { } assign { } { } assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:90151.5-90151.29" + attribute \src "libresoc.v:89836.5-89836.29" switch \initial - attribute \src "libresoc.v:90151.9-90151.17" + attribute \src "libresoc.v:89836.9-89836.17" case 1'1 case end @@ -141112,14 +140634,14 @@ module \dec31 sync always update \dec31_rsrv $0\dec31_rsrv[0:0] end - attribute \src "libresoc.v:90211.3-90271.6" - process $proc$libresoc.v:90211$3846 + attribute \src "libresoc.v:89896.3-89956.6" + process $proc$libresoc.v:89896$3830 assign { } { } assign { } { } assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:90212.5-90212.29" + attribute \src "libresoc.v:89897.5-89897.29" switch \initial - attribute \src "libresoc.v:90212.9-90212.17" + attribute \src "libresoc.v:89897.9-89897.17" case 1'1 case end @@ -141203,14 +140725,14 @@ module \dec31 sync always update \dec31_is_32b $0\dec31_is_32b[0:0] end - attribute \src "libresoc.v:90272.3-90332.6" - process $proc$libresoc.v:90272$3847 + attribute \src "libresoc.v:89957.3-90017.6" + process $proc$libresoc.v:89957$3831 assign { } { } assign { } { } assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] - attribute \src "libresoc.v:90273.5-90273.29" + attribute \src "libresoc.v:89958.5-89958.29" switch \initial - attribute \src "libresoc.v:90273.9-90273.17" + attribute \src "libresoc.v:89958.9-89958.17" case 1'1 case end @@ -141294,14 +140816,14 @@ module \dec31 sync always update \dec31_sgn $0\dec31_sgn[0:0] end - attribute \src "libresoc.v:90333.3-90393.6" - process $proc$libresoc.v:90333$3848 + attribute \src "libresoc.v:90018.3-90078.6" + process $proc$libresoc.v:90018$3832 assign { } { } assign { } { } assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] - attribute \src "libresoc.v:90334.5-90334.29" + attribute \src "libresoc.v:90019.5-90019.29" switch \initial - attribute \src "libresoc.v:90334.9-90334.17" + attribute \src "libresoc.v:90019.9-90019.17" case 1'1 case end @@ -141385,14 +140907,14 @@ module \dec31 sync always update \dec31_lk $0\dec31_lk[0:0] end - attribute \src "libresoc.v:90394.3-90454.6" - process $proc$libresoc.v:90394$3849 + attribute \src "libresoc.v:90079.3-90139.6" + process $proc$libresoc.v:90079$3833 assign { } { } assign { } { } assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:90395.5-90395.29" + attribute \src "libresoc.v:90080.5-90080.29" switch \initial - attribute \src "libresoc.v:90395.9-90395.17" + attribute \src "libresoc.v:90080.9-90080.17" case 1'1 case end @@ -141497,144 +141019,144 @@ module \dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:90479.1-91456.10" +attribute \src "libresoc.v:90164.1-91141.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" attribute \generator "nMigen" module \dec31_dec_sub0 - attribute \src "libresoc.v:91341.3-91359.6" + attribute \src "libresoc.v:91026.3-91044.6" wire width 2 $0\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:91360.3-91378.6" + attribute \src "libresoc.v:91045.3-91063.6" wire width 2 $0\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:91113.3-91131.6" + attribute \src "libresoc.v:90798.3-90816.6" wire width 8 $0\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:91189.3-91207.6" + attribute \src "libresoc.v:90874.3-90892.6" wire $0\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:90847.3-90865.6" + attribute \src "libresoc.v:90532.3-90550.6" wire width 3 $0\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90866.3-90884.6" + attribute \src "libresoc.v:90551.3-90569.6" wire width 3 $0\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:91094.3-91112.6" + attribute \src "libresoc.v:90779.3-90797.6" wire width 2 $0\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:91170.3-91188.6" + attribute \src "libresoc.v:90855.3-90873.6" wire $0\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:91246.3-91264.6" + attribute \src "libresoc.v:90931.3-90949.6" wire width 5 $0\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:90828.3-90846.6" + attribute \src "libresoc.v:90513.3-90531.6" wire width 14 $0\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:91379.3-91397.6" + attribute \src "libresoc.v:91064.3-91082.6" wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:91398.3-91416.6" + attribute \src "libresoc.v:91083.3-91101.6" wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:91417.3-91435.6" + attribute \src "libresoc.v:91102.3-91120.6" wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:91037.3-91055.6" + attribute \src "libresoc.v:90722.3-90740.6" wire width 7 $0\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:91132.3-91150.6" + attribute \src "libresoc.v:90817.3-90835.6" wire $0\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:91151.3-91169.6" + attribute \src "libresoc.v:90836.3-90854.6" wire $0\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:91265.3-91283.6" + attribute \src "libresoc.v:90950.3-90968.6" wire $0\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:91018.3-91036.6" + attribute \src "libresoc.v:90703.3-90721.6" wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:91303.3-91321.6" + attribute \src "libresoc.v:90988.3-91006.6" wire $0\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:91436.3-91454.6" + attribute \src "libresoc.v:91121.3-91139.6" wire width 3 $0\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:91075.3-91093.6" + attribute \src "libresoc.v:90760.3-90778.6" wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:91227.3-91245.6" + attribute \src "libresoc.v:90912.3-90930.6" wire $0\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:91322.3-91340.6" + attribute \src "libresoc.v:91007.3-91025.6" wire $0\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:91284.3-91302.6" + attribute \src "libresoc.v:90969.3-90987.6" wire $0\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:91208.3-91226.6" + attribute \src "libresoc.v:90893.3-90911.6" wire $0\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:90980.3-90998.6" + attribute \src "libresoc.v:90665.3-90683.6" wire width 3 $0\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90999.3-91017.6" + attribute \src "libresoc.v:90684.3-90702.6" wire width 3 $0\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:90885.3-90903.6" + attribute \src "libresoc.v:90570.3-90588.6" wire width 3 $0\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90904.3-90922.6" + attribute \src "libresoc.v:90589.3-90607.6" wire width 3 $0\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90923.3-90941.6" + attribute \src "libresoc.v:90608.3-90626.6" wire width 3 $0\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90961.3-90979.6" + attribute \src "libresoc.v:90646.3-90664.6" wire width 3 $0\dec31_dec_sub0_sv_out2[2:0] - attribute \src "libresoc.v:90942.3-90960.6" + attribute \src "libresoc.v:90627.3-90645.6" wire width 3 $0\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:91056.3-91074.6" + attribute \src "libresoc.v:90741.3-90759.6" wire width 2 $0\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:90480.7-90480.20" + attribute \src "libresoc.v:90165.7-90165.20" wire $0\initial[0:0] - attribute \src "libresoc.v:91341.3-91359.6" + attribute \src "libresoc.v:91026.3-91044.6" wire width 2 $1\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:91360.3-91378.6" + attribute \src "libresoc.v:91045.3-91063.6" wire width 2 $1\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:91113.3-91131.6" + attribute \src "libresoc.v:90798.3-90816.6" wire width 8 $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:91189.3-91207.6" + attribute \src "libresoc.v:90874.3-90892.6" wire $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:90847.3-90865.6" + attribute \src "libresoc.v:90532.3-90550.6" wire width 3 $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90866.3-90884.6" + attribute \src "libresoc.v:90551.3-90569.6" wire width 3 $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:91094.3-91112.6" + attribute \src "libresoc.v:90779.3-90797.6" wire width 2 $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:91170.3-91188.6" + attribute \src "libresoc.v:90855.3-90873.6" wire $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:91246.3-91264.6" + attribute \src "libresoc.v:90931.3-90949.6" wire width 5 $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:90828.3-90846.6" + attribute \src "libresoc.v:90513.3-90531.6" wire width 14 $1\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:91379.3-91397.6" + attribute \src "libresoc.v:91064.3-91082.6" wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:91398.3-91416.6" + attribute \src "libresoc.v:91083.3-91101.6" wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:91417.3-91435.6" + attribute \src "libresoc.v:91102.3-91120.6" wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:91037.3-91055.6" + attribute \src "libresoc.v:90722.3-90740.6" wire width 7 $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:91132.3-91150.6" + attribute \src "libresoc.v:90817.3-90835.6" wire $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:91151.3-91169.6" + attribute \src "libresoc.v:90836.3-90854.6" wire $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:91265.3-91283.6" + attribute \src "libresoc.v:90950.3-90968.6" wire $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:91018.3-91036.6" + attribute \src "libresoc.v:90703.3-90721.6" wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:91303.3-91321.6" + attribute \src "libresoc.v:90988.3-91006.6" wire $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:91436.3-91454.6" + attribute \src "libresoc.v:91121.3-91139.6" wire width 3 $1\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:91075.3-91093.6" + attribute \src "libresoc.v:90760.3-90778.6" wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:91227.3-91245.6" + attribute \src "libresoc.v:90912.3-90930.6" wire $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:91322.3-91340.6" + attribute \src "libresoc.v:91007.3-91025.6" wire $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:91284.3-91302.6" + attribute \src "libresoc.v:90969.3-90987.6" wire $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:91208.3-91226.6" + attribute \src "libresoc.v:90893.3-90911.6" wire $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:90980.3-90998.6" + attribute \src "libresoc.v:90665.3-90683.6" wire width 3 $1\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90999.3-91017.6" + attribute \src "libresoc.v:90684.3-90702.6" wire width 3 $1\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:90885.3-90903.6" + attribute \src "libresoc.v:90570.3-90588.6" wire width 3 $1\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90904.3-90922.6" + attribute \src "libresoc.v:90589.3-90607.6" wire width 3 $1\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90923.3-90941.6" + attribute \src "libresoc.v:90608.3-90626.6" wire width 3 $1\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90961.3-90979.6" + attribute \src "libresoc.v:90646.3-90664.6" wire width 3 $1\dec31_dec_sub0_sv_out2[2:0] - attribute \src "libresoc.v:90942.3-90960.6" + attribute \src "libresoc.v:90627.3-90645.6" wire width 3 $1\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:91056.3-91074.6" + attribute \src "libresoc.v:90741.3-90759.6" wire width 2 $1\dec31_dec_sub0_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -141946,28 +141468,28 @@ module \dec31_dec_sub0 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub0_upd - attribute \src "libresoc.v:90480.7-90480.15" + attribute \src "libresoc.v:90165.7-90165.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:90480.7-90480.20" - process $proc$libresoc.v:90480$3884 + attribute \src "libresoc.v:90165.7-90165.20" + process $proc$libresoc.v:90165$3868 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:90828.3-90846.6" - process $proc$libresoc.v:90828$3851 + attribute \src "libresoc.v:90513.3-90531.6" + process $proc$libresoc.v:90513$3835 assign { } { } assign { } { } assign $0\dec31_dec_sub0_function_unit[13:0] $1\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:90829.5-90829.29" + attribute \src "libresoc.v:90514.5-90514.29" switch \initial - attribute \src "libresoc.v:90829.9-90829.17" + attribute \src "libresoc.v:90514.9-90514.17" case 1'1 case end @@ -141995,14 +141517,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[13:0] end - attribute \src "libresoc.v:90847.3-90865.6" - process $proc$libresoc.v:90847$3852 + attribute \src "libresoc.v:90532.3-90550.6" + process $proc$libresoc.v:90532$3836 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90848.5-90848.29" + attribute \src "libresoc.v:90533.5-90533.29" switch \initial - attribute \src "libresoc.v:90848.9-90848.17" + attribute \src "libresoc.v:90533.9-90533.17" case 1'1 case end @@ -142030,14 +141552,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] end - attribute \src "libresoc.v:90866.3-90884.6" - process $proc$libresoc.v:90866$3853 + attribute \src "libresoc.v:90551.3-90569.6" + process $proc$libresoc.v:90551$3837 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:90867.5-90867.29" + attribute \src "libresoc.v:90552.5-90552.29" switch \initial - attribute \src "libresoc.v:90867.9-90867.17" + attribute \src "libresoc.v:90552.9-90552.17" case 1'1 case end @@ -142065,14 +141587,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] end - attribute \src "libresoc.v:90885.3-90903.6" - process $proc$libresoc.v:90885$3854 + attribute \src "libresoc.v:90570.3-90588.6" + process $proc$libresoc.v:90570$3838 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in1[2:0] $1\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90886.5-90886.29" + attribute \src "libresoc.v:90571.5-90571.29" switch \initial - attribute \src "libresoc.v:90886.9-90886.17" + attribute \src "libresoc.v:90571.9-90571.17" case 1'1 case end @@ -142100,14 +141622,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in1 $0\dec31_dec_sub0_sv_in1[2:0] end - attribute \src "libresoc.v:90904.3-90922.6" - process $proc$libresoc.v:90904$3855 + attribute \src "libresoc.v:90589.3-90607.6" + process $proc$libresoc.v:90589$3839 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in2[2:0] $1\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90905.5-90905.29" + attribute \src "libresoc.v:90590.5-90590.29" switch \initial - attribute \src "libresoc.v:90905.9-90905.17" + attribute \src "libresoc.v:90590.9-90590.17" case 1'1 case end @@ -142135,14 +141657,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in2 $0\dec31_dec_sub0_sv_in2[2:0] end - attribute \src "libresoc.v:90923.3-90941.6" - process $proc$libresoc.v:90923$3856 + attribute \src "libresoc.v:90608.3-90626.6" + process $proc$libresoc.v:90608$3840 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in3[2:0] $1\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90924.5-90924.29" + attribute \src "libresoc.v:90609.5-90609.29" switch \initial - attribute \src "libresoc.v:90924.9-90924.17" + attribute \src "libresoc.v:90609.9-90609.17" case 1'1 case end @@ -142170,14 +141692,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in3 $0\dec31_dec_sub0_sv_in3[2:0] end - attribute \src "libresoc.v:90942.3-90960.6" - process $proc$libresoc.v:90942$3857 + attribute \src "libresoc.v:90627.3-90645.6" + process $proc$libresoc.v:90627$3841 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_out[2:0] $1\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:90943.5-90943.29" + attribute \src "libresoc.v:90628.5-90628.29" switch \initial - attribute \src "libresoc.v:90943.9-90943.17" + attribute \src "libresoc.v:90628.9-90628.17" case 1'1 case end @@ -142205,14 +141727,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_out $0\dec31_dec_sub0_sv_out[2:0] end - attribute \src "libresoc.v:90961.3-90979.6" - process $proc$libresoc.v:90961$3858 + attribute \src "libresoc.v:90646.3-90664.6" + process $proc$libresoc.v:90646$3842 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_out2[2:0] $1\dec31_dec_sub0_sv_out2[2:0] - attribute \src "libresoc.v:90962.5-90962.29" + attribute \src "libresoc.v:90647.5-90647.29" switch \initial - attribute \src "libresoc.v:90962.9-90962.17" + attribute \src "libresoc.v:90647.9-90647.17" case 1'1 case end @@ -142240,14 +141762,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_out2 $0\dec31_dec_sub0_sv_out2[2:0] end - attribute \src "libresoc.v:90980.3-90998.6" - process $proc$libresoc.v:90980$3859 + attribute \src "libresoc.v:90665.3-90683.6" + process $proc$libresoc.v:90665$3843 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_in[2:0] $1\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90981.5-90981.29" + attribute \src "libresoc.v:90666.5-90666.29" switch \initial - attribute \src "libresoc.v:90981.9-90981.17" + attribute \src "libresoc.v:90666.9-90666.17" case 1'1 case end @@ -142275,14 +141797,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_cr_in $0\dec31_dec_sub0_sv_cr_in[2:0] end - attribute \src "libresoc.v:90999.3-91017.6" - process $proc$libresoc.v:90999$3860 + attribute \src "libresoc.v:90684.3-90702.6" + process $proc$libresoc.v:90684$3844 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_out[2:0] $1\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:91000.5-91000.29" + attribute \src "libresoc.v:90685.5-90685.29" switch \initial - attribute \src "libresoc.v:91000.9-91000.17" + attribute \src "libresoc.v:90685.9-90685.17" case 1'1 case end @@ -142310,14 +141832,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_cr_out $0\dec31_dec_sub0_sv_cr_out[2:0] end - attribute \src "libresoc.v:91018.3-91036.6" - process $proc$libresoc.v:91018$3861 + attribute \src "libresoc.v:90703.3-90721.6" + process $proc$libresoc.v:90703$3845 assign { } { } assign { } { } assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:91019.5-91019.29" + attribute \src "libresoc.v:90704.5-90704.29" switch \initial - attribute \src "libresoc.v:91019.9-91019.17" + attribute \src "libresoc.v:90704.9-90704.17" case 1'1 case end @@ -142345,14 +141867,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] end - attribute \src "libresoc.v:91037.3-91055.6" - process $proc$libresoc.v:91037$3862 + attribute \src "libresoc.v:90722.3-90740.6" + process $proc$libresoc.v:90722$3846 assign { } { } assign { } { } assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:91038.5-91038.29" + attribute \src "libresoc.v:90723.5-90723.29" switch \initial - attribute \src "libresoc.v:91038.9-91038.17" + attribute \src "libresoc.v:90723.9-90723.17" case 1'1 case end @@ -142380,14 +141902,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] end - attribute \src "libresoc.v:91056.3-91074.6" - process $proc$libresoc.v:91056$3863 + attribute \src "libresoc.v:90741.3-90759.6" + process $proc$libresoc.v:90741$3847 assign { } { } assign { } { } assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:91057.5-91057.29" + attribute \src "libresoc.v:90742.5-90742.29" switch \initial - attribute \src "libresoc.v:91057.9-91057.17" + attribute \src "libresoc.v:90742.9-90742.17" case 1'1 case end @@ -142415,14 +141937,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] end - attribute \src "libresoc.v:91075.3-91093.6" - process $proc$libresoc.v:91075$3864 + attribute \src "libresoc.v:90760.3-90778.6" + process $proc$libresoc.v:90760$3848 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:91076.5-91076.29" + attribute \src "libresoc.v:90761.5-90761.29" switch \initial - attribute \src "libresoc.v:91076.9-91076.17" + attribute \src "libresoc.v:90761.9-90761.17" case 1'1 case end @@ -142450,14 +141972,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] end - attribute \src "libresoc.v:91094.3-91112.6" - process $proc$libresoc.v:91094$3865 + attribute \src "libresoc.v:90779.3-90797.6" + process $proc$libresoc.v:90779$3849 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:91095.5-91095.29" + attribute \src "libresoc.v:90780.5-90780.29" switch \initial - attribute \src "libresoc.v:91095.9-91095.17" + attribute \src "libresoc.v:90780.9-90780.17" case 1'1 case end @@ -142485,14 +142007,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] end - attribute \src "libresoc.v:91113.3-91131.6" - process $proc$libresoc.v:91113$3866 + attribute \src "libresoc.v:90798.3-90816.6" + process $proc$libresoc.v:90798$3850 assign { } { } assign { } { } assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:91114.5-91114.29" + attribute \src "libresoc.v:90799.5-90799.29" switch \initial - attribute \src "libresoc.v:91114.9-91114.17" + attribute \src "libresoc.v:90799.9-90799.17" case 1'1 case end @@ -142520,14 +142042,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] end - attribute \src "libresoc.v:91132.3-91150.6" - process $proc$libresoc.v:91132$3867 + attribute \src "libresoc.v:90817.3-90835.6" + process $proc$libresoc.v:90817$3851 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:91133.5-91133.29" + attribute \src "libresoc.v:90818.5-90818.29" switch \initial - attribute \src "libresoc.v:91133.9-91133.17" + attribute \src "libresoc.v:90818.9-90818.17" case 1'1 case end @@ -142555,14 +142077,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] end - attribute \src "libresoc.v:91151.3-91169.6" - process $proc$libresoc.v:91151$3868 + attribute \src "libresoc.v:90836.3-90854.6" + process $proc$libresoc.v:90836$3852 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:91152.5-91152.29" + attribute \src "libresoc.v:90837.5-90837.29" switch \initial - attribute \src "libresoc.v:91152.9-91152.17" + attribute \src "libresoc.v:90837.9-90837.17" case 1'1 case end @@ -142590,14 +142112,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] end - attribute \src "libresoc.v:91170.3-91188.6" - process $proc$libresoc.v:91170$3869 + attribute \src "libresoc.v:90855.3-90873.6" + process $proc$libresoc.v:90855$3853 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:91171.5-91171.29" + attribute \src "libresoc.v:90856.5-90856.29" switch \initial - attribute \src "libresoc.v:91171.9-91171.17" + attribute \src "libresoc.v:90856.9-90856.17" case 1'1 case end @@ -142625,14 +142147,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] end - attribute \src "libresoc.v:91189.3-91207.6" - process $proc$libresoc.v:91189$3870 + attribute \src "libresoc.v:90874.3-90892.6" + process $proc$libresoc.v:90874$3854 assign { } { } assign { } { } assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:91190.5-91190.29" + attribute \src "libresoc.v:90875.5-90875.29" switch \initial - attribute \src "libresoc.v:91190.9-91190.17" + attribute \src "libresoc.v:90875.9-90875.17" case 1'1 case end @@ -142660,14 +142182,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] end - attribute \src "libresoc.v:91208.3-91226.6" - process $proc$libresoc.v:91208$3871 + attribute \src "libresoc.v:90893.3-90911.6" + process $proc$libresoc.v:90893$3855 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:91209.5-91209.29" + attribute \src "libresoc.v:90894.5-90894.29" switch \initial - attribute \src "libresoc.v:91209.9-91209.17" + attribute \src "libresoc.v:90894.9-90894.17" case 1'1 case end @@ -142695,14 +142217,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] end - attribute \src "libresoc.v:91227.3-91245.6" - process $proc$libresoc.v:91227$3872 + attribute \src "libresoc.v:90912.3-90930.6" + process $proc$libresoc.v:90912$3856 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:91228.5-91228.29" + attribute \src "libresoc.v:90913.5-90913.29" switch \initial - attribute \src "libresoc.v:91228.9-91228.17" + attribute \src "libresoc.v:90913.9-90913.17" case 1'1 case end @@ -142730,14 +142252,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] end - attribute \src "libresoc.v:91246.3-91264.6" - process $proc$libresoc.v:91246$3873 + attribute \src "libresoc.v:90931.3-90949.6" + process $proc$libresoc.v:90931$3857 assign { } { } assign { } { } assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:91247.5-91247.29" + attribute \src "libresoc.v:90932.5-90932.29" switch \initial - attribute \src "libresoc.v:91247.9-91247.17" + attribute \src "libresoc.v:90932.9-90932.17" case 1'1 case end @@ -142765,14 +142287,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] end - attribute \src "libresoc.v:91265.3-91283.6" - process $proc$libresoc.v:91265$3874 + attribute \src "libresoc.v:90950.3-90968.6" + process $proc$libresoc.v:90950$3858 assign { } { } assign { } { } assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:91266.5-91266.29" + attribute \src "libresoc.v:90951.5-90951.29" switch \initial - attribute \src "libresoc.v:91266.9-91266.17" + attribute \src "libresoc.v:90951.9-90951.17" case 1'1 case end @@ -142800,14 +142322,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] end - attribute \src "libresoc.v:91284.3-91302.6" - process $proc$libresoc.v:91284$3875 + attribute \src "libresoc.v:90969.3-90987.6" + process $proc$libresoc.v:90969$3859 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:91285.5-91285.29" + attribute \src "libresoc.v:90970.5-90970.29" switch \initial - attribute \src "libresoc.v:91285.9-91285.17" + attribute \src "libresoc.v:90970.9-90970.17" case 1'1 case end @@ -142835,14 +142357,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] end - attribute \src "libresoc.v:91303.3-91321.6" - process $proc$libresoc.v:91303$3876 + attribute \src "libresoc.v:90988.3-91006.6" + process $proc$libresoc.v:90988$3860 assign { } { } assign { } { } assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:91304.5-91304.29" + attribute \src "libresoc.v:90989.5-90989.29" switch \initial - attribute \src "libresoc.v:91304.9-91304.17" + attribute \src "libresoc.v:90989.9-90989.17" case 1'1 case end @@ -142870,14 +142392,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] end - attribute \src "libresoc.v:91322.3-91340.6" - process $proc$libresoc.v:91322$3877 + attribute \src "libresoc.v:91007.3-91025.6" + process $proc$libresoc.v:91007$3861 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:91323.5-91323.29" + attribute \src "libresoc.v:91008.5-91008.29" switch \initial - attribute \src "libresoc.v:91323.9-91323.17" + attribute \src "libresoc.v:91008.9-91008.17" case 1'1 case end @@ -142905,14 +142427,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] end - attribute \src "libresoc.v:91341.3-91359.6" - process $proc$libresoc.v:91341$3878 + attribute \src "libresoc.v:91026.3-91044.6" + process $proc$libresoc.v:91026$3862 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Etype[1:0] $1\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:91342.5-91342.29" + attribute \src "libresoc.v:91027.5-91027.29" switch \initial - attribute \src "libresoc.v:91342.9-91342.17" + attribute \src "libresoc.v:91027.9-91027.17" case 1'1 case end @@ -142940,14 +142462,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_SV_Etype $0\dec31_dec_sub0_SV_Etype[1:0] end - attribute \src "libresoc.v:91360.3-91378.6" - process $proc$libresoc.v:91360$3879 + attribute \src "libresoc.v:91045.3-91063.6" + process $proc$libresoc.v:91045$3863 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Ptype[1:0] $1\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:91361.5-91361.29" + attribute \src "libresoc.v:91046.5-91046.29" switch \initial - attribute \src "libresoc.v:91361.9-91361.17" + attribute \src "libresoc.v:91046.9-91046.17" case 1'1 case end @@ -142975,14 +142497,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_SV_Ptype $0\dec31_dec_sub0_SV_Ptype[1:0] end - attribute \src "libresoc.v:91379.3-91397.6" - process $proc$libresoc.v:91379$3880 + attribute \src "libresoc.v:91064.3-91082.6" + process $proc$libresoc.v:91064$3864 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:91380.5-91380.29" + attribute \src "libresoc.v:91065.5-91065.29" switch \initial - attribute \src "libresoc.v:91380.9-91380.17" + attribute \src "libresoc.v:91065.9-91065.17" case 1'1 case end @@ -143010,14 +142532,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] end - attribute \src "libresoc.v:91398.3-91416.6" - process $proc$libresoc.v:91398$3881 + attribute \src "libresoc.v:91083.3-91101.6" + process $proc$libresoc.v:91083$3865 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:91399.5-91399.29" + attribute \src "libresoc.v:91084.5-91084.29" switch \initial - attribute \src "libresoc.v:91399.9-91399.17" + attribute \src "libresoc.v:91084.9-91084.17" case 1'1 case end @@ -143045,14 +142567,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] end - attribute \src "libresoc.v:91417.3-91435.6" - process $proc$libresoc.v:91417$3882 + attribute \src "libresoc.v:91102.3-91120.6" + process $proc$libresoc.v:91102$3866 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:91418.5-91418.29" + attribute \src "libresoc.v:91103.5-91103.29" switch \initial - attribute \src "libresoc.v:91418.9-91418.17" + attribute \src "libresoc.v:91103.9-91103.17" case 1'1 case end @@ -143080,14 +142602,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] end - attribute \src "libresoc.v:91436.3-91454.6" - process $proc$libresoc.v:91436$3883 + attribute \src "libresoc.v:91121.3-91139.6" + process $proc$libresoc.v:91121$3867 assign { } { } assign { } { } assign $0\dec31_dec_sub0_out_sel[2:0] $1\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:91437.5-91437.29" + attribute \src "libresoc.v:91122.5-91122.29" switch \initial - attribute \src "libresoc.v:91437.9-91437.17" + attribute \src "libresoc.v:91122.9-91122.17" case 1'1 case end @@ -143117,144 +142639,144 @@ module \dec31_dec_sub0 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:91460.1-93031.10" +attribute \src "libresoc.v:91145.1-92716.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" attribute \generator "nMigen" module \dec31_dec_sub10 - attribute \src "libresoc.v:92808.3-92844.6" + attribute \src "libresoc.v:92493.3-92529.6" wire width 2 $0\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92845.3-92881.6" + attribute \src "libresoc.v:92530.3-92566.6" wire width 2 $0\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:92364.3-92400.6" + attribute \src "libresoc.v:92049.3-92085.6" wire width 8 $0\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:92512.3-92548.6" + attribute \src "libresoc.v:92197.3-92233.6" wire $0\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:91846.3-91882.6" + attribute \src "libresoc.v:91531.3-91567.6" wire width 3 $0\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91883.3-91919.6" + attribute \src "libresoc.v:91568.3-91604.6" wire width 3 $0\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:92327.3-92363.6" + attribute \src "libresoc.v:92012.3-92048.6" wire width 2 $0\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:92475.3-92511.6" + attribute \src "libresoc.v:92160.3-92196.6" wire $0\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:92623.3-92659.6" + attribute \src "libresoc.v:92308.3-92344.6" wire width 5 $0\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:91809.3-91845.6" + attribute \src "libresoc.v:91494.3-91530.6" wire width 14 $0\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:92882.3-92918.6" + attribute \src "libresoc.v:92567.3-92603.6" wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92919.3-92955.6" + attribute \src "libresoc.v:92604.3-92640.6" wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92956.3-92992.6" + attribute \src "libresoc.v:92641.3-92677.6" wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:92216.3-92252.6" + attribute \src "libresoc.v:91901.3-91937.6" wire width 7 $0\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:92401.3-92437.6" + attribute \src "libresoc.v:92086.3-92122.6" wire $0\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:92438.3-92474.6" + attribute \src "libresoc.v:92123.3-92159.6" wire $0\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:92660.3-92696.6" + attribute \src "libresoc.v:92345.3-92381.6" wire $0\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:92179.3-92215.6" + attribute \src "libresoc.v:91864.3-91900.6" wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:92734.3-92770.6" + attribute \src "libresoc.v:92419.3-92455.6" wire $0\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:92993.3-93029.6" + attribute \src "libresoc.v:92678.3-92714.6" wire width 3 $0\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:92290.3-92326.6" + attribute \src "libresoc.v:91975.3-92011.6" wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:92586.3-92622.6" + attribute \src "libresoc.v:92271.3-92307.6" wire $0\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:92771.3-92807.6" + attribute \src "libresoc.v:92456.3-92492.6" wire $0\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:92697.3-92733.6" + attribute \src "libresoc.v:92382.3-92418.6" wire $0\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:92549.3-92585.6" + attribute \src "libresoc.v:92234.3-92270.6" wire $0\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:92105.3-92141.6" + attribute \src "libresoc.v:91790.3-91826.6" wire width 3 $0\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:92142.3-92178.6" + attribute \src "libresoc.v:91827.3-91863.6" wire width 3 $0\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:91920.3-91956.6" + attribute \src "libresoc.v:91605.3-91641.6" wire width 3 $0\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91957.3-91993.6" + attribute \src "libresoc.v:91642.3-91678.6" wire width 3 $0\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91994.3-92030.6" + attribute \src "libresoc.v:91679.3-91715.6" wire width 3 $0\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:92068.3-92104.6" + attribute \src "libresoc.v:91753.3-91789.6" wire width 3 $0\dec31_dec_sub10_sv_out2[2:0] - attribute \src "libresoc.v:92031.3-92067.6" + attribute \src "libresoc.v:91716.3-91752.6" wire width 3 $0\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:92253.3-92289.6" + attribute \src "libresoc.v:91938.3-91974.6" wire width 2 $0\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:91461.7-91461.20" + attribute \src "libresoc.v:91146.7-91146.20" wire $0\initial[0:0] - attribute \src "libresoc.v:92808.3-92844.6" + attribute \src "libresoc.v:92493.3-92529.6" wire width 2 $1\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92845.3-92881.6" + attribute \src "libresoc.v:92530.3-92566.6" wire width 2 $1\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:92364.3-92400.6" + attribute \src "libresoc.v:92049.3-92085.6" wire width 8 $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:92512.3-92548.6" + attribute \src "libresoc.v:92197.3-92233.6" wire $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:91846.3-91882.6" + attribute \src "libresoc.v:91531.3-91567.6" wire width 3 $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91883.3-91919.6" + attribute \src "libresoc.v:91568.3-91604.6" wire width 3 $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:92327.3-92363.6" + attribute \src "libresoc.v:92012.3-92048.6" wire width 2 $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:92475.3-92511.6" + attribute \src "libresoc.v:92160.3-92196.6" wire $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:92623.3-92659.6" + attribute \src "libresoc.v:92308.3-92344.6" wire width 5 $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:91809.3-91845.6" + attribute \src "libresoc.v:91494.3-91530.6" wire width 14 $1\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:92882.3-92918.6" + attribute \src "libresoc.v:92567.3-92603.6" wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92919.3-92955.6" + attribute \src "libresoc.v:92604.3-92640.6" wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92956.3-92992.6" + attribute \src "libresoc.v:92641.3-92677.6" wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:92216.3-92252.6" + attribute \src "libresoc.v:91901.3-91937.6" wire width 7 $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:92401.3-92437.6" + attribute \src "libresoc.v:92086.3-92122.6" wire $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:92438.3-92474.6" + attribute \src "libresoc.v:92123.3-92159.6" wire $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:92660.3-92696.6" + attribute \src "libresoc.v:92345.3-92381.6" wire $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:92179.3-92215.6" + attribute \src "libresoc.v:91864.3-91900.6" wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:92734.3-92770.6" + attribute \src "libresoc.v:92419.3-92455.6" wire $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:92993.3-93029.6" + attribute \src "libresoc.v:92678.3-92714.6" wire width 3 $1\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:92290.3-92326.6" + attribute \src "libresoc.v:91975.3-92011.6" wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:92586.3-92622.6" + attribute \src "libresoc.v:92271.3-92307.6" wire $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:92771.3-92807.6" + attribute \src "libresoc.v:92456.3-92492.6" wire $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:92697.3-92733.6" + attribute \src "libresoc.v:92382.3-92418.6" wire $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:92549.3-92585.6" + attribute \src "libresoc.v:92234.3-92270.6" wire $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:92105.3-92141.6" + attribute \src "libresoc.v:91790.3-91826.6" wire width 3 $1\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:92142.3-92178.6" + attribute \src "libresoc.v:91827.3-91863.6" wire width 3 $1\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:91920.3-91956.6" + attribute \src "libresoc.v:91605.3-91641.6" wire width 3 $1\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91957.3-91993.6" + attribute \src "libresoc.v:91642.3-91678.6" wire width 3 $1\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91994.3-92030.6" + attribute \src "libresoc.v:91679.3-91715.6" wire width 3 $1\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:92068.3-92104.6" + attribute \src "libresoc.v:91753.3-91789.6" wire width 3 $1\dec31_dec_sub10_sv_out2[2:0] - attribute \src "libresoc.v:92031.3-92067.6" + attribute \src "libresoc.v:91716.3-91752.6" wire width 3 $1\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:92253.3-92289.6" + attribute \src "libresoc.v:91938.3-91974.6" wire width 2 $1\dec31_dec_sub10_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -143566,28 +143088,28 @@ module \dec31_dec_sub10 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub10_upd - attribute \src "libresoc.v:91461.7-91461.15" + attribute \src "libresoc.v:91146.7-91146.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:91461.7-91461.20" - process $proc$libresoc.v:91461$3918 + attribute \src "libresoc.v:91146.7-91146.20" + process $proc$libresoc.v:91146$3902 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:91809.3-91845.6" - process $proc$libresoc.v:91809$3885 + attribute \src "libresoc.v:91494.3-91530.6" + process $proc$libresoc.v:91494$3869 assign { } { } assign { } { } assign $0\dec31_dec_sub10_function_unit[13:0] $1\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:91810.5-91810.29" + attribute \src "libresoc.v:91495.5-91495.29" switch \initial - attribute \src "libresoc.v:91810.9-91810.17" + attribute \src "libresoc.v:91495.9-91495.17" case 1'1 case end @@ -143639,14 +143161,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[13:0] end - attribute \src "libresoc.v:91846.3-91882.6" - process $proc$libresoc.v:91846$3886 + attribute \src "libresoc.v:91531.3-91567.6" + process $proc$libresoc.v:91531$3870 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91847.5-91847.29" + attribute \src "libresoc.v:91532.5-91532.29" switch \initial - attribute \src "libresoc.v:91847.9-91847.17" + attribute \src "libresoc.v:91532.9-91532.17" case 1'1 case end @@ -143698,14 +143220,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] end - attribute \src "libresoc.v:91883.3-91919.6" - process $proc$libresoc.v:91883$3887 + attribute \src "libresoc.v:91568.3-91604.6" + process $proc$libresoc.v:91568$3871 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:91884.5-91884.29" + attribute \src "libresoc.v:91569.5-91569.29" switch \initial - attribute \src "libresoc.v:91884.9-91884.17" + attribute \src "libresoc.v:91569.9-91569.17" case 1'1 case end @@ -143757,14 +143279,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] end - attribute \src "libresoc.v:91920.3-91956.6" - process $proc$libresoc.v:91920$3888 + attribute \src "libresoc.v:91605.3-91641.6" + process $proc$libresoc.v:91605$3872 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in1[2:0] $1\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91921.5-91921.29" + attribute \src "libresoc.v:91606.5-91606.29" switch \initial - attribute \src "libresoc.v:91921.9-91921.17" + attribute \src "libresoc.v:91606.9-91606.17" case 1'1 case end @@ -143816,14 +143338,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in1 $0\dec31_dec_sub10_sv_in1[2:0] end - attribute \src "libresoc.v:91957.3-91993.6" - process $proc$libresoc.v:91957$3889 + attribute \src "libresoc.v:91642.3-91678.6" + process $proc$libresoc.v:91642$3873 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in2[2:0] $1\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91958.5-91958.29" + attribute \src "libresoc.v:91643.5-91643.29" switch \initial - attribute \src "libresoc.v:91958.9-91958.17" + attribute \src "libresoc.v:91643.9-91643.17" case 1'1 case end @@ -143875,14 +143397,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in2 $0\dec31_dec_sub10_sv_in2[2:0] end - attribute \src "libresoc.v:91994.3-92030.6" - process $proc$libresoc.v:91994$3890 + attribute \src "libresoc.v:91679.3-91715.6" + process $proc$libresoc.v:91679$3874 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in3[2:0] $1\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:91995.5-91995.29" + attribute \src "libresoc.v:91680.5-91680.29" switch \initial - attribute \src "libresoc.v:91995.9-91995.17" + attribute \src "libresoc.v:91680.9-91680.17" case 1'1 case end @@ -143934,14 +143456,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in3 $0\dec31_dec_sub10_sv_in3[2:0] end - attribute \src "libresoc.v:92031.3-92067.6" - process $proc$libresoc.v:92031$3891 + attribute \src "libresoc.v:91716.3-91752.6" + process $proc$libresoc.v:91716$3875 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_out[2:0] $1\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:92032.5-92032.29" + attribute \src "libresoc.v:91717.5-91717.29" switch \initial - attribute \src "libresoc.v:92032.9-92032.17" + attribute \src "libresoc.v:91717.9-91717.17" case 1'1 case end @@ -143993,14 +143515,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_out $0\dec31_dec_sub10_sv_out[2:0] end - attribute \src "libresoc.v:92068.3-92104.6" - process $proc$libresoc.v:92068$3892 + attribute \src "libresoc.v:91753.3-91789.6" + process $proc$libresoc.v:91753$3876 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_out2[2:0] $1\dec31_dec_sub10_sv_out2[2:0] - attribute \src "libresoc.v:92069.5-92069.29" + attribute \src "libresoc.v:91754.5-91754.29" switch \initial - attribute \src "libresoc.v:92069.9-92069.17" + attribute \src "libresoc.v:91754.9-91754.17" case 1'1 case end @@ -144052,14 +143574,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_out2 $0\dec31_dec_sub10_sv_out2[2:0] end - attribute \src "libresoc.v:92105.3-92141.6" - process $proc$libresoc.v:92105$3893 + attribute \src "libresoc.v:91790.3-91826.6" + process $proc$libresoc.v:91790$3877 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_in[2:0] $1\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:92106.5-92106.29" + attribute \src "libresoc.v:91791.5-91791.29" switch \initial - attribute \src "libresoc.v:92106.9-92106.17" + attribute \src "libresoc.v:91791.9-91791.17" case 1'1 case end @@ -144111,14 +143633,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_cr_in $0\dec31_dec_sub10_sv_cr_in[2:0] end - attribute \src "libresoc.v:92142.3-92178.6" - process $proc$libresoc.v:92142$3894 + attribute \src "libresoc.v:91827.3-91863.6" + process $proc$libresoc.v:91827$3878 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_out[2:0] $1\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:92143.5-92143.29" + attribute \src "libresoc.v:91828.5-91828.29" switch \initial - attribute \src "libresoc.v:92143.9-92143.17" + attribute \src "libresoc.v:91828.9-91828.17" case 1'1 case end @@ -144170,14 +143692,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_cr_out $0\dec31_dec_sub10_sv_cr_out[2:0] end - attribute \src "libresoc.v:92179.3-92215.6" - process $proc$libresoc.v:92179$3895 + attribute \src "libresoc.v:91864.3-91900.6" + process $proc$libresoc.v:91864$3879 assign { } { } assign { } { } assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:92180.5-92180.29" + attribute \src "libresoc.v:91865.5-91865.29" switch \initial - attribute \src "libresoc.v:92180.9-92180.17" + attribute \src "libresoc.v:91865.9-91865.17" case 1'1 case end @@ -144229,14 +143751,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] end - attribute \src "libresoc.v:92216.3-92252.6" - process $proc$libresoc.v:92216$3896 + attribute \src "libresoc.v:91901.3-91937.6" + process $proc$libresoc.v:91901$3880 assign { } { } assign { } { } assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:92217.5-92217.29" + attribute \src "libresoc.v:91902.5-91902.29" switch \initial - attribute \src "libresoc.v:92217.9-92217.17" + attribute \src "libresoc.v:91902.9-91902.17" case 1'1 case end @@ -144288,14 +143810,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] end - attribute \src "libresoc.v:92253.3-92289.6" - process $proc$libresoc.v:92253$3897 + attribute \src "libresoc.v:91938.3-91974.6" + process $proc$libresoc.v:91938$3881 assign { } { } assign { } { } assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:92254.5-92254.29" + attribute \src "libresoc.v:91939.5-91939.29" switch \initial - attribute \src "libresoc.v:92254.9-92254.17" + attribute \src "libresoc.v:91939.9-91939.17" case 1'1 case end @@ -144347,14 +143869,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] end - attribute \src "libresoc.v:92290.3-92326.6" - process $proc$libresoc.v:92290$3898 + attribute \src "libresoc.v:91975.3-92011.6" + process $proc$libresoc.v:91975$3882 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:92291.5-92291.29" + attribute \src "libresoc.v:91976.5-91976.29" switch \initial - attribute \src "libresoc.v:92291.9-92291.17" + attribute \src "libresoc.v:91976.9-91976.17" case 1'1 case end @@ -144406,14 +143928,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] end - attribute \src "libresoc.v:92327.3-92363.6" - process $proc$libresoc.v:92327$3899 + attribute \src "libresoc.v:92012.3-92048.6" + process $proc$libresoc.v:92012$3883 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:92328.5-92328.29" + attribute \src "libresoc.v:92013.5-92013.29" switch \initial - attribute \src "libresoc.v:92328.9-92328.17" + attribute \src "libresoc.v:92013.9-92013.17" case 1'1 case end @@ -144465,14 +143987,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] end - attribute \src "libresoc.v:92364.3-92400.6" - process $proc$libresoc.v:92364$3900 + attribute \src "libresoc.v:92049.3-92085.6" + process $proc$libresoc.v:92049$3884 assign { } { } assign { } { } assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:92365.5-92365.29" + attribute \src "libresoc.v:92050.5-92050.29" switch \initial - attribute \src "libresoc.v:92365.9-92365.17" + attribute \src "libresoc.v:92050.9-92050.17" case 1'1 case end @@ -144524,14 +144046,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] end - attribute \src "libresoc.v:92401.3-92437.6" - process $proc$libresoc.v:92401$3901 + attribute \src "libresoc.v:92086.3-92122.6" + process $proc$libresoc.v:92086$3885 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:92402.5-92402.29" + attribute \src "libresoc.v:92087.5-92087.29" switch \initial - attribute \src "libresoc.v:92402.9-92402.17" + attribute \src "libresoc.v:92087.9-92087.17" case 1'1 case end @@ -144583,14 +144105,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] end - attribute \src "libresoc.v:92438.3-92474.6" - process $proc$libresoc.v:92438$3902 + attribute \src "libresoc.v:92123.3-92159.6" + process $proc$libresoc.v:92123$3886 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:92439.5-92439.29" + attribute \src "libresoc.v:92124.5-92124.29" switch \initial - attribute \src "libresoc.v:92439.9-92439.17" + attribute \src "libresoc.v:92124.9-92124.17" case 1'1 case end @@ -144642,14 +144164,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] end - attribute \src "libresoc.v:92475.3-92511.6" - process $proc$libresoc.v:92475$3903 + attribute \src "libresoc.v:92160.3-92196.6" + process $proc$libresoc.v:92160$3887 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:92476.5-92476.29" + attribute \src "libresoc.v:92161.5-92161.29" switch \initial - attribute \src "libresoc.v:92476.9-92476.17" + attribute \src "libresoc.v:92161.9-92161.17" case 1'1 case end @@ -144701,14 +144223,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] end - attribute \src "libresoc.v:92512.3-92548.6" - process $proc$libresoc.v:92512$3904 + attribute \src "libresoc.v:92197.3-92233.6" + process $proc$libresoc.v:92197$3888 assign { } { } assign { } { } assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:92513.5-92513.29" + attribute \src "libresoc.v:92198.5-92198.29" switch \initial - attribute \src "libresoc.v:92513.9-92513.17" + attribute \src "libresoc.v:92198.9-92198.17" case 1'1 case end @@ -144760,14 +144282,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] end - attribute \src "libresoc.v:92549.3-92585.6" - process $proc$libresoc.v:92549$3905 + attribute \src "libresoc.v:92234.3-92270.6" + process $proc$libresoc.v:92234$3889 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:92550.5-92550.29" + attribute \src "libresoc.v:92235.5-92235.29" switch \initial - attribute \src "libresoc.v:92550.9-92550.17" + attribute \src "libresoc.v:92235.9-92235.17" case 1'1 case end @@ -144819,14 +144341,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] end - attribute \src "libresoc.v:92586.3-92622.6" - process $proc$libresoc.v:92586$3906 + attribute \src "libresoc.v:92271.3-92307.6" + process $proc$libresoc.v:92271$3890 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:92587.5-92587.29" + attribute \src "libresoc.v:92272.5-92272.29" switch \initial - attribute \src "libresoc.v:92587.9-92587.17" + attribute \src "libresoc.v:92272.9-92272.17" case 1'1 case end @@ -144878,14 +144400,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] end - attribute \src "libresoc.v:92623.3-92659.6" - process $proc$libresoc.v:92623$3907 + attribute \src "libresoc.v:92308.3-92344.6" + process $proc$libresoc.v:92308$3891 assign { } { } assign { } { } assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:92624.5-92624.29" + attribute \src "libresoc.v:92309.5-92309.29" switch \initial - attribute \src "libresoc.v:92624.9-92624.17" + attribute \src "libresoc.v:92309.9-92309.17" case 1'1 case end @@ -144937,14 +144459,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] end - attribute \src "libresoc.v:92660.3-92696.6" - process $proc$libresoc.v:92660$3908 + attribute \src "libresoc.v:92345.3-92381.6" + process $proc$libresoc.v:92345$3892 assign { } { } assign { } { } assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:92661.5-92661.29" + attribute \src "libresoc.v:92346.5-92346.29" switch \initial - attribute \src "libresoc.v:92661.9-92661.17" + attribute \src "libresoc.v:92346.9-92346.17" case 1'1 case end @@ -144996,14 +144518,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] end - attribute \src "libresoc.v:92697.3-92733.6" - process $proc$libresoc.v:92697$3909 + attribute \src "libresoc.v:92382.3-92418.6" + process $proc$libresoc.v:92382$3893 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:92698.5-92698.29" + attribute \src "libresoc.v:92383.5-92383.29" switch \initial - attribute \src "libresoc.v:92698.9-92698.17" + attribute \src "libresoc.v:92383.9-92383.17" case 1'1 case end @@ -145055,14 +144577,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] end - attribute \src "libresoc.v:92734.3-92770.6" - process $proc$libresoc.v:92734$3910 + attribute \src "libresoc.v:92419.3-92455.6" + process $proc$libresoc.v:92419$3894 assign { } { } assign { } { } assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:92735.5-92735.29" + attribute \src "libresoc.v:92420.5-92420.29" switch \initial - attribute \src "libresoc.v:92735.9-92735.17" + attribute \src "libresoc.v:92420.9-92420.17" case 1'1 case end @@ -145114,14 +144636,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] end - attribute \src "libresoc.v:92771.3-92807.6" - process $proc$libresoc.v:92771$3911 + attribute \src "libresoc.v:92456.3-92492.6" + process $proc$libresoc.v:92456$3895 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:92772.5-92772.29" + attribute \src "libresoc.v:92457.5-92457.29" switch \initial - attribute \src "libresoc.v:92772.9-92772.17" + attribute \src "libresoc.v:92457.9-92457.17" case 1'1 case end @@ -145173,14 +144695,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] end - attribute \src "libresoc.v:92808.3-92844.6" - process $proc$libresoc.v:92808$3912 + attribute \src "libresoc.v:92493.3-92529.6" + process $proc$libresoc.v:92493$3896 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Etype[1:0] $1\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92809.5-92809.29" + attribute \src "libresoc.v:92494.5-92494.29" switch \initial - attribute \src "libresoc.v:92809.9-92809.17" + attribute \src "libresoc.v:92494.9-92494.17" case 1'1 case end @@ -145232,14 +144754,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_SV_Etype $0\dec31_dec_sub10_SV_Etype[1:0] end - attribute \src "libresoc.v:92845.3-92881.6" - process $proc$libresoc.v:92845$3913 + attribute \src "libresoc.v:92530.3-92566.6" + process $proc$libresoc.v:92530$3897 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Ptype[1:0] $1\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:92846.5-92846.29" + attribute \src "libresoc.v:92531.5-92531.29" switch \initial - attribute \src "libresoc.v:92846.9-92846.17" + attribute \src "libresoc.v:92531.9-92531.17" case 1'1 case end @@ -145291,14 +144813,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_SV_Ptype $0\dec31_dec_sub10_SV_Ptype[1:0] end - attribute \src "libresoc.v:92882.3-92918.6" - process $proc$libresoc.v:92882$3914 + attribute \src "libresoc.v:92567.3-92603.6" + process $proc$libresoc.v:92567$3898 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92883.5-92883.29" + attribute \src "libresoc.v:92568.5-92568.29" switch \initial - attribute \src "libresoc.v:92883.9-92883.17" + attribute \src "libresoc.v:92568.9-92568.17" case 1'1 case end @@ -145350,14 +144872,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] end - attribute \src "libresoc.v:92919.3-92955.6" - process $proc$libresoc.v:92919$3915 + attribute \src "libresoc.v:92604.3-92640.6" + process $proc$libresoc.v:92604$3899 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92920.5-92920.29" + attribute \src "libresoc.v:92605.5-92605.29" switch \initial - attribute \src "libresoc.v:92920.9-92920.17" + attribute \src "libresoc.v:92605.9-92605.17" case 1'1 case end @@ -145409,14 +144931,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] end - attribute \src "libresoc.v:92956.3-92992.6" - process $proc$libresoc.v:92956$3916 + attribute \src "libresoc.v:92641.3-92677.6" + process $proc$libresoc.v:92641$3900 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:92957.5-92957.29" + attribute \src "libresoc.v:92642.5-92642.29" switch \initial - attribute \src "libresoc.v:92957.9-92957.17" + attribute \src "libresoc.v:92642.9-92642.17" case 1'1 case end @@ -145468,14 +144990,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] end - attribute \src "libresoc.v:92993.3-93029.6" - process $proc$libresoc.v:92993$3917 + attribute \src "libresoc.v:92678.3-92714.6" + process $proc$libresoc.v:92678$3901 assign { } { } assign { } { } assign $0\dec31_dec_sub10_out_sel[2:0] $1\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:92994.5-92994.29" + attribute \src "libresoc.v:92679.5-92679.29" switch \initial - attribute \src "libresoc.v:92994.9-92994.17" + attribute \src "libresoc.v:92679.9-92679.17" case 1'1 case end @@ -145529,144 +145051,144 @@ module \dec31_dec_sub10 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:93035.1-95200.10" +attribute \src "libresoc.v:92720.1-94885.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" attribute \generator "nMigen" module \dec31_dec_sub11 - attribute \src "libresoc.v:94869.3-94923.6" + attribute \src "libresoc.v:94554.3-94608.6" wire width 2 $0\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94924.3-94978.6" + attribute \src "libresoc.v:94609.3-94663.6" wire width 2 $0\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:94209.3-94263.6" + attribute \src "libresoc.v:93894.3-93948.6" wire width 8 $0\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:94429.3-94483.6" + attribute \src "libresoc.v:94114.3-94168.6" wire $0\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:93439.3-93493.6" + attribute \src "libresoc.v:93124.3-93178.6" wire width 3 $0\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:93494.3-93548.6" + attribute \src "libresoc.v:93179.3-93233.6" wire width 3 $0\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:94154.3-94208.6" + attribute \src "libresoc.v:93839.3-93893.6" wire width 2 $0\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:94374.3-94428.6" + attribute \src "libresoc.v:94059.3-94113.6" wire $0\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:94594.3-94648.6" + attribute \src "libresoc.v:94279.3-94333.6" wire width 5 $0\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:93384.3-93438.6" + attribute \src "libresoc.v:93069.3-93123.6" wire width 14 $0\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:94979.3-95033.6" + attribute \src "libresoc.v:94664.3-94718.6" wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:95034.3-95088.6" + attribute \src "libresoc.v:94719.3-94773.6" wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:95089.3-95143.6" + attribute \src "libresoc.v:94774.3-94828.6" wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:93989.3-94043.6" + attribute \src "libresoc.v:93674.3-93728.6" wire width 7 $0\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:94264.3-94318.6" + attribute \src "libresoc.v:93949.3-94003.6" wire $0\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:94319.3-94373.6" + attribute \src "libresoc.v:94004.3-94058.6" wire $0\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:94649.3-94703.6" + attribute \src "libresoc.v:94334.3-94388.6" wire $0\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:93934.3-93988.6" + attribute \src "libresoc.v:93619.3-93673.6" wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:94759.3-94813.6" + attribute \src "libresoc.v:94444.3-94498.6" wire $0\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:95144.3-95198.6" + attribute \src "libresoc.v:94829.3-94883.6" wire width 3 $0\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:94099.3-94153.6" + attribute \src "libresoc.v:93784.3-93838.6" wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:94539.3-94593.6" + attribute \src "libresoc.v:94224.3-94278.6" wire $0\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:94814.3-94868.6" + attribute \src "libresoc.v:94499.3-94553.6" wire $0\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:94704.3-94758.6" + attribute \src "libresoc.v:94389.3-94443.6" wire $0\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:94484.3-94538.6" + attribute \src "libresoc.v:94169.3-94223.6" wire $0\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:93824.3-93878.6" + attribute \src "libresoc.v:93509.3-93563.6" wire width 3 $0\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:93879.3-93933.6" + attribute \src "libresoc.v:93564.3-93618.6" wire width 3 $0\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:93549.3-93603.6" + attribute \src "libresoc.v:93234.3-93288.6" wire width 3 $0\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:93604.3-93658.6" + attribute \src "libresoc.v:93289.3-93343.6" wire width 3 $0\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:93659.3-93713.6" + attribute \src "libresoc.v:93344.3-93398.6" wire width 3 $0\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:93769.3-93823.6" + attribute \src "libresoc.v:93454.3-93508.6" wire width 3 $0\dec31_dec_sub11_sv_out2[2:0] - attribute \src "libresoc.v:93714.3-93768.6" + attribute \src "libresoc.v:93399.3-93453.6" wire width 3 $0\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:94044.3-94098.6" + attribute \src "libresoc.v:93729.3-93783.6" wire width 2 $0\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:93036.7-93036.20" + attribute \src "libresoc.v:92721.7-92721.20" wire $0\initial[0:0] - attribute \src "libresoc.v:94869.3-94923.6" + attribute \src "libresoc.v:94554.3-94608.6" wire width 2 $1\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94924.3-94978.6" + attribute \src "libresoc.v:94609.3-94663.6" wire width 2 $1\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:94209.3-94263.6" + attribute \src "libresoc.v:93894.3-93948.6" wire width 8 $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:94429.3-94483.6" + attribute \src "libresoc.v:94114.3-94168.6" wire $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:93439.3-93493.6" + attribute \src "libresoc.v:93124.3-93178.6" wire width 3 $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:93494.3-93548.6" + attribute \src "libresoc.v:93179.3-93233.6" wire width 3 $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:94154.3-94208.6" + attribute \src "libresoc.v:93839.3-93893.6" wire width 2 $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:94374.3-94428.6" + attribute \src "libresoc.v:94059.3-94113.6" wire $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:94594.3-94648.6" + attribute \src "libresoc.v:94279.3-94333.6" wire width 5 $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:93384.3-93438.6" + attribute \src "libresoc.v:93069.3-93123.6" wire width 14 $1\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:94979.3-95033.6" + attribute \src "libresoc.v:94664.3-94718.6" wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:95034.3-95088.6" + attribute \src "libresoc.v:94719.3-94773.6" wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:95089.3-95143.6" + attribute \src "libresoc.v:94774.3-94828.6" wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:93989.3-94043.6" + attribute \src "libresoc.v:93674.3-93728.6" wire width 7 $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:94264.3-94318.6" + attribute \src "libresoc.v:93949.3-94003.6" wire $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:94319.3-94373.6" + attribute \src "libresoc.v:94004.3-94058.6" wire $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:94649.3-94703.6" + attribute \src "libresoc.v:94334.3-94388.6" wire $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:93934.3-93988.6" + attribute \src "libresoc.v:93619.3-93673.6" wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:94759.3-94813.6" + attribute \src "libresoc.v:94444.3-94498.6" wire $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:95144.3-95198.6" + attribute \src "libresoc.v:94829.3-94883.6" wire width 3 $1\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:94099.3-94153.6" + attribute \src "libresoc.v:93784.3-93838.6" wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:94539.3-94593.6" + attribute \src "libresoc.v:94224.3-94278.6" wire $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:94814.3-94868.6" + attribute \src "libresoc.v:94499.3-94553.6" wire $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:94704.3-94758.6" + attribute \src "libresoc.v:94389.3-94443.6" wire $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:94484.3-94538.6" + attribute \src "libresoc.v:94169.3-94223.6" wire $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:93824.3-93878.6" + attribute \src "libresoc.v:93509.3-93563.6" wire width 3 $1\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:93879.3-93933.6" + attribute \src "libresoc.v:93564.3-93618.6" wire width 3 $1\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:93549.3-93603.6" + attribute \src "libresoc.v:93234.3-93288.6" wire width 3 $1\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:93604.3-93658.6" + attribute \src "libresoc.v:93289.3-93343.6" wire width 3 $1\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:93659.3-93713.6" + attribute \src "libresoc.v:93344.3-93398.6" wire width 3 $1\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:93769.3-93823.6" + attribute \src "libresoc.v:93454.3-93508.6" wire width 3 $1\dec31_dec_sub11_sv_out2[2:0] - attribute \src "libresoc.v:93714.3-93768.6" + attribute \src "libresoc.v:93399.3-93453.6" wire width 3 $1\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:94044.3-94098.6" + attribute \src "libresoc.v:93729.3-93783.6" wire width 2 $1\dec31_dec_sub11_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -145978,28 +145500,28 @@ module \dec31_dec_sub11 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub11_upd - attribute \src "libresoc.v:93036.7-93036.15" + attribute \src "libresoc.v:92721.7-92721.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:93036.7-93036.20" - process $proc$libresoc.v:93036$3952 + attribute \src "libresoc.v:92721.7-92721.20" + process $proc$libresoc.v:92721$3936 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:93384.3-93438.6" - process $proc$libresoc.v:93384$3919 + attribute \src "libresoc.v:93069.3-93123.6" + process $proc$libresoc.v:93069$3903 assign { } { } assign { } { } assign $0\dec31_dec_sub11_function_unit[13:0] $1\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:93385.5-93385.29" + attribute \src "libresoc.v:93070.5-93070.29" switch \initial - attribute \src "libresoc.v:93385.9-93385.17" + attribute \src "libresoc.v:93070.9-93070.17" case 1'1 case end @@ -146075,14 +145597,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[13:0] end - attribute \src "libresoc.v:93439.3-93493.6" - process $proc$libresoc.v:93439$3920 + attribute \src "libresoc.v:93124.3-93178.6" + process $proc$libresoc.v:93124$3904 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:93440.5-93440.29" + attribute \src "libresoc.v:93125.5-93125.29" switch \initial - attribute \src "libresoc.v:93440.9-93440.17" + attribute \src "libresoc.v:93125.9-93125.17" case 1'1 case end @@ -146158,14 +145680,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] end - attribute \src "libresoc.v:93494.3-93548.6" - process $proc$libresoc.v:93494$3921 + attribute \src "libresoc.v:93179.3-93233.6" + process $proc$libresoc.v:93179$3905 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:93495.5-93495.29" + attribute \src "libresoc.v:93180.5-93180.29" switch \initial - attribute \src "libresoc.v:93495.9-93495.17" + attribute \src "libresoc.v:93180.9-93180.17" case 1'1 case end @@ -146241,14 +145763,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] end - attribute \src "libresoc.v:93549.3-93603.6" - process $proc$libresoc.v:93549$3922 + attribute \src "libresoc.v:93234.3-93288.6" + process $proc$libresoc.v:93234$3906 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in1[2:0] $1\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:93550.5-93550.29" + attribute \src "libresoc.v:93235.5-93235.29" switch \initial - attribute \src "libresoc.v:93550.9-93550.17" + attribute \src "libresoc.v:93235.9-93235.17" case 1'1 case end @@ -146324,14 +145846,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in1 $0\dec31_dec_sub11_sv_in1[2:0] end - attribute \src "libresoc.v:93604.3-93658.6" - process $proc$libresoc.v:93604$3923 + attribute \src "libresoc.v:93289.3-93343.6" + process $proc$libresoc.v:93289$3907 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in2[2:0] $1\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:93605.5-93605.29" + attribute \src "libresoc.v:93290.5-93290.29" switch \initial - attribute \src "libresoc.v:93605.9-93605.17" + attribute \src "libresoc.v:93290.9-93290.17" case 1'1 case end @@ -146407,14 +145929,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in2 $0\dec31_dec_sub11_sv_in2[2:0] end - attribute \src "libresoc.v:93659.3-93713.6" - process $proc$libresoc.v:93659$3924 + attribute \src "libresoc.v:93344.3-93398.6" + process $proc$libresoc.v:93344$3908 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in3[2:0] $1\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:93660.5-93660.29" + attribute \src "libresoc.v:93345.5-93345.29" switch \initial - attribute \src "libresoc.v:93660.9-93660.17" + attribute \src "libresoc.v:93345.9-93345.17" case 1'1 case end @@ -146490,14 +146012,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in3 $0\dec31_dec_sub11_sv_in3[2:0] end - attribute \src "libresoc.v:93714.3-93768.6" - process $proc$libresoc.v:93714$3925 + attribute \src "libresoc.v:93399.3-93453.6" + process $proc$libresoc.v:93399$3909 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_out[2:0] $1\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:93715.5-93715.29" + attribute \src "libresoc.v:93400.5-93400.29" switch \initial - attribute \src "libresoc.v:93715.9-93715.17" + attribute \src "libresoc.v:93400.9-93400.17" case 1'1 case end @@ -146573,14 +146095,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_out $0\dec31_dec_sub11_sv_out[2:0] end - attribute \src "libresoc.v:93769.3-93823.6" - process $proc$libresoc.v:93769$3926 + attribute \src "libresoc.v:93454.3-93508.6" + process $proc$libresoc.v:93454$3910 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_out2[2:0] $1\dec31_dec_sub11_sv_out2[2:0] - attribute \src "libresoc.v:93770.5-93770.29" + attribute \src "libresoc.v:93455.5-93455.29" switch \initial - attribute \src "libresoc.v:93770.9-93770.17" + attribute \src "libresoc.v:93455.9-93455.17" case 1'1 case end @@ -146656,14 +146178,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_out2 $0\dec31_dec_sub11_sv_out2[2:0] end - attribute \src "libresoc.v:93824.3-93878.6" - process $proc$libresoc.v:93824$3927 + attribute \src "libresoc.v:93509.3-93563.6" + process $proc$libresoc.v:93509$3911 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_in[2:0] $1\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:93825.5-93825.29" + attribute \src "libresoc.v:93510.5-93510.29" switch \initial - attribute \src "libresoc.v:93825.9-93825.17" + attribute \src "libresoc.v:93510.9-93510.17" case 1'1 case end @@ -146739,14 +146261,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_cr_in $0\dec31_dec_sub11_sv_cr_in[2:0] end - attribute \src "libresoc.v:93879.3-93933.6" - process $proc$libresoc.v:93879$3928 + attribute \src "libresoc.v:93564.3-93618.6" + process $proc$libresoc.v:93564$3912 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_out[2:0] $1\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:93880.5-93880.29" + attribute \src "libresoc.v:93565.5-93565.29" switch \initial - attribute \src "libresoc.v:93880.9-93880.17" + attribute \src "libresoc.v:93565.9-93565.17" case 1'1 case end @@ -146822,14 +146344,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_cr_out $0\dec31_dec_sub11_sv_cr_out[2:0] end - attribute \src "libresoc.v:93934.3-93988.6" - process $proc$libresoc.v:93934$3929 + attribute \src "libresoc.v:93619.3-93673.6" + process $proc$libresoc.v:93619$3913 assign { } { } assign { } { } assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:93935.5-93935.29" + attribute \src "libresoc.v:93620.5-93620.29" switch \initial - attribute \src "libresoc.v:93935.9-93935.17" + attribute \src "libresoc.v:93620.9-93620.17" case 1'1 case end @@ -146905,14 +146427,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] end - attribute \src "libresoc.v:93989.3-94043.6" - process $proc$libresoc.v:93989$3930 + attribute \src "libresoc.v:93674.3-93728.6" + process $proc$libresoc.v:93674$3914 assign { } { } assign { } { } assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:93990.5-93990.29" + attribute \src "libresoc.v:93675.5-93675.29" switch \initial - attribute \src "libresoc.v:93990.9-93990.17" + attribute \src "libresoc.v:93675.9-93675.17" case 1'1 case end @@ -146988,14 +146510,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] end - attribute \src "libresoc.v:94044.3-94098.6" - process $proc$libresoc.v:94044$3931 + attribute \src "libresoc.v:93729.3-93783.6" + process $proc$libresoc.v:93729$3915 assign { } { } assign { } { } assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:94045.5-94045.29" + attribute \src "libresoc.v:93730.5-93730.29" switch \initial - attribute \src "libresoc.v:94045.9-94045.17" + attribute \src "libresoc.v:93730.9-93730.17" case 1'1 case end @@ -147071,14 +146593,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] end - attribute \src "libresoc.v:94099.3-94153.6" - process $proc$libresoc.v:94099$3932 + attribute \src "libresoc.v:93784.3-93838.6" + process $proc$libresoc.v:93784$3916 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:94100.5-94100.29" + attribute \src "libresoc.v:93785.5-93785.29" switch \initial - attribute \src "libresoc.v:94100.9-94100.17" + attribute \src "libresoc.v:93785.9-93785.17" case 1'1 case end @@ -147154,14 +146676,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] end - attribute \src "libresoc.v:94154.3-94208.6" - process $proc$libresoc.v:94154$3933 + attribute \src "libresoc.v:93839.3-93893.6" + process $proc$libresoc.v:93839$3917 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:94155.5-94155.29" + attribute \src "libresoc.v:93840.5-93840.29" switch \initial - attribute \src "libresoc.v:94155.9-94155.17" + attribute \src "libresoc.v:93840.9-93840.17" case 1'1 case end @@ -147237,14 +146759,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] end - attribute \src "libresoc.v:94209.3-94263.6" - process $proc$libresoc.v:94209$3934 + attribute \src "libresoc.v:93894.3-93948.6" + process $proc$libresoc.v:93894$3918 assign { } { } assign { } { } assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:94210.5-94210.29" + attribute \src "libresoc.v:93895.5-93895.29" switch \initial - attribute \src "libresoc.v:94210.9-94210.17" + attribute \src "libresoc.v:93895.9-93895.17" case 1'1 case end @@ -147320,14 +146842,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] end - attribute \src "libresoc.v:94264.3-94318.6" - process $proc$libresoc.v:94264$3935 + attribute \src "libresoc.v:93949.3-94003.6" + process $proc$libresoc.v:93949$3919 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:94265.5-94265.29" + attribute \src "libresoc.v:93950.5-93950.29" switch \initial - attribute \src "libresoc.v:94265.9-94265.17" + attribute \src "libresoc.v:93950.9-93950.17" case 1'1 case end @@ -147403,14 +146925,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] end - attribute \src "libresoc.v:94319.3-94373.6" - process $proc$libresoc.v:94319$3936 + attribute \src "libresoc.v:94004.3-94058.6" + process $proc$libresoc.v:94004$3920 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:94320.5-94320.29" + attribute \src "libresoc.v:94005.5-94005.29" switch \initial - attribute \src "libresoc.v:94320.9-94320.17" + attribute \src "libresoc.v:94005.9-94005.17" case 1'1 case end @@ -147486,14 +147008,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] end - attribute \src "libresoc.v:94374.3-94428.6" - process $proc$libresoc.v:94374$3937 + attribute \src "libresoc.v:94059.3-94113.6" + process $proc$libresoc.v:94059$3921 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:94375.5-94375.29" + attribute \src "libresoc.v:94060.5-94060.29" switch \initial - attribute \src "libresoc.v:94375.9-94375.17" + attribute \src "libresoc.v:94060.9-94060.17" case 1'1 case end @@ -147569,14 +147091,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] end - attribute \src "libresoc.v:94429.3-94483.6" - process $proc$libresoc.v:94429$3938 + attribute \src "libresoc.v:94114.3-94168.6" + process $proc$libresoc.v:94114$3922 assign { } { } assign { } { } assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:94430.5-94430.29" + attribute \src "libresoc.v:94115.5-94115.29" switch \initial - attribute \src "libresoc.v:94430.9-94430.17" + attribute \src "libresoc.v:94115.9-94115.17" case 1'1 case end @@ -147652,14 +147174,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] end - attribute \src "libresoc.v:94484.3-94538.6" - process $proc$libresoc.v:94484$3939 + attribute \src "libresoc.v:94169.3-94223.6" + process $proc$libresoc.v:94169$3923 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:94485.5-94485.29" + attribute \src "libresoc.v:94170.5-94170.29" switch \initial - attribute \src "libresoc.v:94485.9-94485.17" + attribute \src "libresoc.v:94170.9-94170.17" case 1'1 case end @@ -147735,14 +147257,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] end - attribute \src "libresoc.v:94539.3-94593.6" - process $proc$libresoc.v:94539$3940 + attribute \src "libresoc.v:94224.3-94278.6" + process $proc$libresoc.v:94224$3924 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:94540.5-94540.29" + attribute \src "libresoc.v:94225.5-94225.29" switch \initial - attribute \src "libresoc.v:94540.9-94540.17" + attribute \src "libresoc.v:94225.9-94225.17" case 1'1 case end @@ -147818,14 +147340,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] end - attribute \src "libresoc.v:94594.3-94648.6" - process $proc$libresoc.v:94594$3941 + attribute \src "libresoc.v:94279.3-94333.6" + process $proc$libresoc.v:94279$3925 assign { } { } assign { } { } assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:94595.5-94595.29" + attribute \src "libresoc.v:94280.5-94280.29" switch \initial - attribute \src "libresoc.v:94595.9-94595.17" + attribute \src "libresoc.v:94280.9-94280.17" case 1'1 case end @@ -147901,14 +147423,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] end - attribute \src "libresoc.v:94649.3-94703.6" - process $proc$libresoc.v:94649$3942 + attribute \src "libresoc.v:94334.3-94388.6" + process $proc$libresoc.v:94334$3926 assign { } { } assign { } { } assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:94650.5-94650.29" + attribute \src "libresoc.v:94335.5-94335.29" switch \initial - attribute \src "libresoc.v:94650.9-94650.17" + attribute \src "libresoc.v:94335.9-94335.17" case 1'1 case end @@ -147984,14 +147506,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] end - attribute \src "libresoc.v:94704.3-94758.6" - process $proc$libresoc.v:94704$3943 + attribute \src "libresoc.v:94389.3-94443.6" + process $proc$libresoc.v:94389$3927 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:94705.5-94705.29" + attribute \src "libresoc.v:94390.5-94390.29" switch \initial - attribute \src "libresoc.v:94705.9-94705.17" + attribute \src "libresoc.v:94390.9-94390.17" case 1'1 case end @@ -148067,14 +147589,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] end - attribute \src "libresoc.v:94759.3-94813.6" - process $proc$libresoc.v:94759$3944 + attribute \src "libresoc.v:94444.3-94498.6" + process $proc$libresoc.v:94444$3928 assign { } { } assign { } { } assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:94760.5-94760.29" + attribute \src "libresoc.v:94445.5-94445.29" switch \initial - attribute \src "libresoc.v:94760.9-94760.17" + attribute \src "libresoc.v:94445.9-94445.17" case 1'1 case end @@ -148150,14 +147672,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] end - attribute \src "libresoc.v:94814.3-94868.6" - process $proc$libresoc.v:94814$3945 + attribute \src "libresoc.v:94499.3-94553.6" + process $proc$libresoc.v:94499$3929 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:94815.5-94815.29" + attribute \src "libresoc.v:94500.5-94500.29" switch \initial - attribute \src "libresoc.v:94815.9-94815.17" + attribute \src "libresoc.v:94500.9-94500.17" case 1'1 case end @@ -148233,14 +147755,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] end - attribute \src "libresoc.v:94869.3-94923.6" - process $proc$libresoc.v:94869$3946 + attribute \src "libresoc.v:94554.3-94608.6" + process $proc$libresoc.v:94554$3930 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Etype[1:0] $1\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94870.5-94870.29" + attribute \src "libresoc.v:94555.5-94555.29" switch \initial - attribute \src "libresoc.v:94870.9-94870.17" + attribute \src "libresoc.v:94555.9-94555.17" case 1'1 case end @@ -148316,14 +147838,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_SV_Etype $0\dec31_dec_sub11_SV_Etype[1:0] end - attribute \src "libresoc.v:94924.3-94978.6" - process $proc$libresoc.v:94924$3947 + attribute \src "libresoc.v:94609.3-94663.6" + process $proc$libresoc.v:94609$3931 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Ptype[1:0] $1\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:94925.5-94925.29" + attribute \src "libresoc.v:94610.5-94610.29" switch \initial - attribute \src "libresoc.v:94925.9-94925.17" + attribute \src "libresoc.v:94610.9-94610.17" case 1'1 case end @@ -148399,14 +147921,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_SV_Ptype $0\dec31_dec_sub11_SV_Ptype[1:0] end - attribute \src "libresoc.v:94979.3-95033.6" - process $proc$libresoc.v:94979$3948 + attribute \src "libresoc.v:94664.3-94718.6" + process $proc$libresoc.v:94664$3932 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:94980.5-94980.29" + attribute \src "libresoc.v:94665.5-94665.29" switch \initial - attribute \src "libresoc.v:94980.9-94980.17" + attribute \src "libresoc.v:94665.9-94665.17" case 1'1 case end @@ -148482,14 +148004,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] end - attribute \src "libresoc.v:95034.3-95088.6" - process $proc$libresoc.v:95034$3949 + attribute \src "libresoc.v:94719.3-94773.6" + process $proc$libresoc.v:94719$3933 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:95035.5-95035.29" + attribute \src "libresoc.v:94720.5-94720.29" switch \initial - attribute \src "libresoc.v:95035.9-95035.17" + attribute \src "libresoc.v:94720.9-94720.17" case 1'1 case end @@ -148565,14 +148087,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] end - attribute \src "libresoc.v:95089.3-95143.6" - process $proc$libresoc.v:95089$3950 + attribute \src "libresoc.v:94774.3-94828.6" + process $proc$libresoc.v:94774$3934 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:95090.5-95090.29" + attribute \src "libresoc.v:94775.5-94775.29" switch \initial - attribute \src "libresoc.v:95090.9-95090.17" + attribute \src "libresoc.v:94775.9-94775.17" case 1'1 case end @@ -148648,14 +148170,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] end - attribute \src "libresoc.v:95144.3-95198.6" - process $proc$libresoc.v:95144$3951 + attribute \src "libresoc.v:94829.3-94883.6" + process $proc$libresoc.v:94829$3935 assign { } { } assign { } { } assign $0\dec31_dec_sub11_out_sel[2:0] $1\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:95145.5-95145.29" + attribute \src "libresoc.v:94830.5-94830.29" switch \initial - attribute \src "libresoc.v:95145.9-95145.17" + attribute \src "libresoc.v:94830.9-94830.17" case 1'1 case end @@ -148733,144 +148255,144 @@ module \dec31_dec_sub11 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:95204.1-98953.10" +attribute \src "libresoc.v:94889.1-98638.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" attribute \generator "nMigen" module \dec31_dec_sub15 - attribute \src "libresoc.v:98334.3-98436.6" + attribute \src "libresoc.v:98019.3-98121.6" wire width 2 $0\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:98437.3-98539.6" + attribute \src "libresoc.v:98122.3-98224.6" wire width 2 $0\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:97098.3-97200.6" + attribute \src "libresoc.v:96783.3-96885.6" wire width 8 $0\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:97510.3-97612.6" + attribute \src "libresoc.v:97195.3-97297.6" wire $0\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:95656.3-95758.6" + attribute \src "libresoc.v:95341.3-95443.6" wire width 3 $0\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:95759.3-95861.6" + attribute \src "libresoc.v:95444.3-95546.6" wire width 3 $0\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:96995.3-97097.6" + attribute \src "libresoc.v:96680.3-96782.6" wire width 2 $0\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:97407.3-97509.6" + attribute \src "libresoc.v:97092.3-97194.6" wire $0\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:97819.3-97921.6" + attribute \src "libresoc.v:97504.3-97606.6" wire width 5 $0\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:95553.3-95655.6" + attribute \src "libresoc.v:95238.3-95340.6" wire width 14 $0\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:98540.3-98642.6" + attribute \src "libresoc.v:98225.3-98327.6" wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:98643.3-98745.6" + attribute \src "libresoc.v:98328.3-98430.6" wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:98746.3-98848.6" + attribute \src "libresoc.v:98431.3-98533.6" wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:96686.3-96788.6" + attribute \src "libresoc.v:96371.3-96473.6" wire width 7 $0\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:97201.3-97303.6" + attribute \src "libresoc.v:96886.3-96988.6" wire $0\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:97304.3-97406.6" + attribute \src "libresoc.v:96989.3-97091.6" wire $0\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:97922.3-98024.6" + attribute \src "libresoc.v:97607.3-97709.6" wire $0\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:96583.3-96685.6" + attribute \src "libresoc.v:96268.3-96370.6" wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:98128.3-98230.6" + attribute \src "libresoc.v:97813.3-97915.6" wire $0\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:98849.3-98951.6" + attribute \src "libresoc.v:98534.3-98636.6" wire width 3 $0\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:96892.3-96994.6" + attribute \src "libresoc.v:96577.3-96679.6" wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:97716.3-97818.6" + attribute \src "libresoc.v:97401.3-97503.6" wire $0\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:98231.3-98333.6" + attribute \src "libresoc.v:97916.3-98018.6" wire $0\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:98025.3-98127.6" + attribute \src "libresoc.v:97710.3-97812.6" wire $0\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:97613.3-97715.6" + attribute \src "libresoc.v:97298.3-97400.6" wire $0\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:96377.3-96479.6" + attribute \src "libresoc.v:96062.3-96164.6" wire width 3 $0\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:96480.3-96582.6" + attribute \src "libresoc.v:96165.3-96267.6" wire width 3 $0\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:95862.3-95964.6" + attribute \src "libresoc.v:95547.3-95649.6" wire width 3 $0\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95965.3-96067.6" + attribute \src "libresoc.v:95650.3-95752.6" wire width 3 $0\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:96068.3-96170.6" + attribute \src "libresoc.v:95753.3-95855.6" wire width 3 $0\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:96274.3-96376.6" + attribute \src "libresoc.v:95959.3-96061.6" wire width 3 $0\dec31_dec_sub15_sv_out2[2:0] - attribute \src "libresoc.v:96171.3-96273.6" + attribute \src "libresoc.v:95856.3-95958.6" wire width 3 $0\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:96789.3-96891.6" + attribute \src "libresoc.v:96474.3-96576.6" wire width 2 $0\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:95205.7-95205.20" + attribute \src "libresoc.v:94890.7-94890.20" wire $0\initial[0:0] - attribute \src "libresoc.v:98334.3-98436.6" + attribute \src "libresoc.v:98019.3-98121.6" wire width 2 $1\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:98437.3-98539.6" + attribute \src "libresoc.v:98122.3-98224.6" wire width 2 $1\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:97098.3-97200.6" + attribute \src "libresoc.v:96783.3-96885.6" wire width 8 $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:97510.3-97612.6" + attribute \src "libresoc.v:97195.3-97297.6" wire $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:95656.3-95758.6" + attribute \src "libresoc.v:95341.3-95443.6" wire width 3 $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:95759.3-95861.6" + attribute \src "libresoc.v:95444.3-95546.6" wire width 3 $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:96995.3-97097.6" + attribute \src "libresoc.v:96680.3-96782.6" wire width 2 $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:97407.3-97509.6" + attribute \src "libresoc.v:97092.3-97194.6" wire $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:97819.3-97921.6" + attribute \src "libresoc.v:97504.3-97606.6" wire width 5 $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:95553.3-95655.6" + attribute \src "libresoc.v:95238.3-95340.6" wire width 14 $1\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:98540.3-98642.6" + attribute \src "libresoc.v:98225.3-98327.6" wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:98643.3-98745.6" + attribute \src "libresoc.v:98328.3-98430.6" wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:98746.3-98848.6" + attribute \src "libresoc.v:98431.3-98533.6" wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:96686.3-96788.6" + attribute \src "libresoc.v:96371.3-96473.6" wire width 7 $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:97201.3-97303.6" + attribute \src "libresoc.v:96886.3-96988.6" wire $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:97304.3-97406.6" + attribute \src "libresoc.v:96989.3-97091.6" wire $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:97922.3-98024.6" + attribute \src "libresoc.v:97607.3-97709.6" wire $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:96583.3-96685.6" + attribute \src "libresoc.v:96268.3-96370.6" wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:98128.3-98230.6" + attribute \src "libresoc.v:97813.3-97915.6" wire $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:98849.3-98951.6" + attribute \src "libresoc.v:98534.3-98636.6" wire width 3 $1\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:96892.3-96994.6" + attribute \src "libresoc.v:96577.3-96679.6" wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:97716.3-97818.6" + attribute \src "libresoc.v:97401.3-97503.6" wire $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:98231.3-98333.6" + attribute \src "libresoc.v:97916.3-98018.6" wire $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:98025.3-98127.6" + attribute \src "libresoc.v:97710.3-97812.6" wire $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:97613.3-97715.6" + attribute \src "libresoc.v:97298.3-97400.6" wire $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:96377.3-96479.6" + attribute \src "libresoc.v:96062.3-96164.6" wire width 3 $1\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:96480.3-96582.6" + attribute \src "libresoc.v:96165.3-96267.6" wire width 3 $1\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:95862.3-95964.6" + attribute \src "libresoc.v:95547.3-95649.6" wire width 3 $1\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95965.3-96067.6" + attribute \src "libresoc.v:95650.3-95752.6" wire width 3 $1\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:96068.3-96170.6" + attribute \src "libresoc.v:95753.3-95855.6" wire width 3 $1\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:96274.3-96376.6" + attribute \src "libresoc.v:95959.3-96061.6" wire width 3 $1\dec31_dec_sub15_sv_out2[2:0] - attribute \src "libresoc.v:96171.3-96273.6" + attribute \src "libresoc.v:95856.3-95958.6" wire width 3 $1\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:96789.3-96891.6" + attribute \src "libresoc.v:96474.3-96576.6" wire width 2 $1\dec31_dec_sub15_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -149182,28 +148704,28 @@ module \dec31_dec_sub15 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub15_upd - attribute \src "libresoc.v:95205.7-95205.15" + attribute \src "libresoc.v:94890.7-94890.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:95205.7-95205.20" - process $proc$libresoc.v:95205$3986 + attribute \src "libresoc.v:94890.7-94890.20" + process $proc$libresoc.v:94890$3970 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:95553.3-95655.6" - process $proc$libresoc.v:95553$3953 + attribute \src "libresoc.v:95238.3-95340.6" + process $proc$libresoc.v:95238$3937 assign { } { } assign { } { } assign $0\dec31_dec_sub15_function_unit[13:0] $1\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:95554.5-95554.29" + attribute \src "libresoc.v:95239.5-95239.29" switch \initial - attribute \src "libresoc.v:95554.9-95554.17" + attribute \src "libresoc.v:95239.9-95239.17" case 1'1 case end @@ -149343,14 +148865,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[13:0] end - attribute \src "libresoc.v:95656.3-95758.6" - process $proc$libresoc.v:95656$3954 + attribute \src "libresoc.v:95341.3-95443.6" + process $proc$libresoc.v:95341$3938 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:95657.5-95657.29" + attribute \src "libresoc.v:95342.5-95342.29" switch \initial - attribute \src "libresoc.v:95657.9-95657.17" + attribute \src "libresoc.v:95342.9-95342.17" case 1'1 case end @@ -149490,14 +149012,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] end - attribute \src "libresoc.v:95759.3-95861.6" - process $proc$libresoc.v:95759$3955 + attribute \src "libresoc.v:95444.3-95546.6" + process $proc$libresoc.v:95444$3939 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:95760.5-95760.29" + attribute \src "libresoc.v:95445.5-95445.29" switch \initial - attribute \src "libresoc.v:95760.9-95760.17" + attribute \src "libresoc.v:95445.9-95445.17" case 1'1 case end @@ -149637,14 +149159,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] end - attribute \src "libresoc.v:95862.3-95964.6" - process $proc$libresoc.v:95862$3956 + attribute \src "libresoc.v:95547.3-95649.6" + process $proc$libresoc.v:95547$3940 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in1[2:0] $1\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95863.5-95863.29" + attribute \src "libresoc.v:95548.5-95548.29" switch \initial - attribute \src "libresoc.v:95863.9-95863.17" + attribute \src "libresoc.v:95548.9-95548.17" case 1'1 case end @@ -149784,14 +149306,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in1 $0\dec31_dec_sub15_sv_in1[2:0] end - attribute \src "libresoc.v:95965.3-96067.6" - process $proc$libresoc.v:95965$3957 + attribute \src "libresoc.v:95650.3-95752.6" + process $proc$libresoc.v:95650$3941 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in2[2:0] $1\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:95966.5-95966.29" + attribute \src "libresoc.v:95651.5-95651.29" switch \initial - attribute \src "libresoc.v:95966.9-95966.17" + attribute \src "libresoc.v:95651.9-95651.17" case 1'1 case end @@ -149931,14 +149453,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in2 $0\dec31_dec_sub15_sv_in2[2:0] end - attribute \src "libresoc.v:96068.3-96170.6" - process $proc$libresoc.v:96068$3958 + attribute \src "libresoc.v:95753.3-95855.6" + process $proc$libresoc.v:95753$3942 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in3[2:0] $1\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:96069.5-96069.29" + attribute \src "libresoc.v:95754.5-95754.29" switch \initial - attribute \src "libresoc.v:96069.9-96069.17" + attribute \src "libresoc.v:95754.9-95754.17" case 1'1 case end @@ -150078,14 +149600,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in3 $0\dec31_dec_sub15_sv_in3[2:0] end - attribute \src "libresoc.v:96171.3-96273.6" - process $proc$libresoc.v:96171$3959 + attribute \src "libresoc.v:95856.3-95958.6" + process $proc$libresoc.v:95856$3943 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_out[2:0] $1\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:96172.5-96172.29" + attribute \src "libresoc.v:95857.5-95857.29" switch \initial - attribute \src "libresoc.v:96172.9-96172.17" + attribute \src "libresoc.v:95857.9-95857.17" case 1'1 case end @@ -150225,14 +149747,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_out $0\dec31_dec_sub15_sv_out[2:0] end - attribute \src "libresoc.v:96274.3-96376.6" - process $proc$libresoc.v:96274$3960 + attribute \src "libresoc.v:95959.3-96061.6" + process $proc$libresoc.v:95959$3944 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_out2[2:0] $1\dec31_dec_sub15_sv_out2[2:0] - attribute \src "libresoc.v:96275.5-96275.29" + attribute \src "libresoc.v:95960.5-95960.29" switch \initial - attribute \src "libresoc.v:96275.9-96275.17" + attribute \src "libresoc.v:95960.9-95960.17" case 1'1 case end @@ -150372,14 +149894,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_out2 $0\dec31_dec_sub15_sv_out2[2:0] end - attribute \src "libresoc.v:96377.3-96479.6" - process $proc$libresoc.v:96377$3961 + attribute \src "libresoc.v:96062.3-96164.6" + process $proc$libresoc.v:96062$3945 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_in[2:0] $1\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:96378.5-96378.29" + attribute \src "libresoc.v:96063.5-96063.29" switch \initial - attribute \src "libresoc.v:96378.9-96378.17" + attribute \src "libresoc.v:96063.9-96063.17" case 1'1 case end @@ -150519,14 +150041,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_cr_in $0\dec31_dec_sub15_sv_cr_in[2:0] end - attribute \src "libresoc.v:96480.3-96582.6" - process $proc$libresoc.v:96480$3962 + attribute \src "libresoc.v:96165.3-96267.6" + process $proc$libresoc.v:96165$3946 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_out[2:0] $1\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:96481.5-96481.29" + attribute \src "libresoc.v:96166.5-96166.29" switch \initial - attribute \src "libresoc.v:96481.9-96481.17" + attribute \src "libresoc.v:96166.9-96166.17" case 1'1 case end @@ -150666,14 +150188,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_cr_out $0\dec31_dec_sub15_sv_cr_out[2:0] end - attribute \src "libresoc.v:96583.3-96685.6" - process $proc$libresoc.v:96583$3963 + attribute \src "libresoc.v:96268.3-96370.6" + process $proc$libresoc.v:96268$3947 assign { } { } assign { } { } assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:96584.5-96584.29" + attribute \src "libresoc.v:96269.5-96269.29" switch \initial - attribute \src "libresoc.v:96584.9-96584.17" + attribute \src "libresoc.v:96269.9-96269.17" case 1'1 case end @@ -150813,14 +150335,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] end - attribute \src "libresoc.v:96686.3-96788.6" - process $proc$libresoc.v:96686$3964 + attribute \src "libresoc.v:96371.3-96473.6" + process $proc$libresoc.v:96371$3948 assign { } { } assign { } { } assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:96687.5-96687.29" + attribute \src "libresoc.v:96372.5-96372.29" switch \initial - attribute \src "libresoc.v:96687.9-96687.17" + attribute \src "libresoc.v:96372.9-96372.17" case 1'1 case end @@ -150960,14 +150482,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] end - attribute \src "libresoc.v:96789.3-96891.6" - process $proc$libresoc.v:96789$3965 + attribute \src "libresoc.v:96474.3-96576.6" + process $proc$libresoc.v:96474$3949 assign { } { } assign { } { } assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:96790.5-96790.29" + attribute \src "libresoc.v:96475.5-96475.29" switch \initial - attribute \src "libresoc.v:96790.9-96790.17" + attribute \src "libresoc.v:96475.9-96475.17" case 1'1 case end @@ -151107,14 +150629,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] end - attribute \src "libresoc.v:96892.3-96994.6" - process $proc$libresoc.v:96892$3966 + attribute \src "libresoc.v:96577.3-96679.6" + process $proc$libresoc.v:96577$3950 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:96893.5-96893.29" + attribute \src "libresoc.v:96578.5-96578.29" switch \initial - attribute \src "libresoc.v:96893.9-96893.17" + attribute \src "libresoc.v:96578.9-96578.17" case 1'1 case end @@ -151254,14 +150776,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] end - attribute \src "libresoc.v:96995.3-97097.6" - process $proc$libresoc.v:96995$3967 + attribute \src "libresoc.v:96680.3-96782.6" + process $proc$libresoc.v:96680$3951 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:96996.5-96996.29" + attribute \src "libresoc.v:96681.5-96681.29" switch \initial - attribute \src "libresoc.v:96996.9-96996.17" + attribute \src "libresoc.v:96681.9-96681.17" case 1'1 case end @@ -151401,14 +150923,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] end - attribute \src "libresoc.v:97098.3-97200.6" - process $proc$libresoc.v:97098$3968 + attribute \src "libresoc.v:96783.3-96885.6" + process $proc$libresoc.v:96783$3952 assign { } { } assign { } { } assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:97099.5-97099.29" + attribute \src "libresoc.v:96784.5-96784.29" switch \initial - attribute \src "libresoc.v:97099.9-97099.17" + attribute \src "libresoc.v:96784.9-96784.17" case 1'1 case end @@ -151548,14 +151070,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] end - attribute \src "libresoc.v:97201.3-97303.6" - process $proc$libresoc.v:97201$3969 + attribute \src "libresoc.v:96886.3-96988.6" + process $proc$libresoc.v:96886$3953 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:97202.5-97202.29" + attribute \src "libresoc.v:96887.5-96887.29" switch \initial - attribute \src "libresoc.v:97202.9-97202.17" + attribute \src "libresoc.v:96887.9-96887.17" case 1'1 case end @@ -151695,14 +151217,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] end - attribute \src "libresoc.v:97304.3-97406.6" - process $proc$libresoc.v:97304$3970 + attribute \src "libresoc.v:96989.3-97091.6" + process $proc$libresoc.v:96989$3954 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:97305.5-97305.29" + attribute \src "libresoc.v:96990.5-96990.29" switch \initial - attribute \src "libresoc.v:97305.9-97305.17" + attribute \src "libresoc.v:96990.9-96990.17" case 1'1 case end @@ -151842,14 +151364,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] end - attribute \src "libresoc.v:97407.3-97509.6" - process $proc$libresoc.v:97407$3971 + attribute \src "libresoc.v:97092.3-97194.6" + process $proc$libresoc.v:97092$3955 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:97408.5-97408.29" + attribute \src "libresoc.v:97093.5-97093.29" switch \initial - attribute \src "libresoc.v:97408.9-97408.17" + attribute \src "libresoc.v:97093.9-97093.17" case 1'1 case end @@ -151989,14 +151511,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] end - attribute \src "libresoc.v:97510.3-97612.6" - process $proc$libresoc.v:97510$3972 + attribute \src "libresoc.v:97195.3-97297.6" + process $proc$libresoc.v:97195$3956 assign { } { } assign { } { } assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:97511.5-97511.29" + attribute \src "libresoc.v:97196.5-97196.29" switch \initial - attribute \src "libresoc.v:97511.9-97511.17" + attribute \src "libresoc.v:97196.9-97196.17" case 1'1 case end @@ -152136,14 +151658,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] end - attribute \src "libresoc.v:97613.3-97715.6" - process $proc$libresoc.v:97613$3973 + attribute \src "libresoc.v:97298.3-97400.6" + process $proc$libresoc.v:97298$3957 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:97614.5-97614.29" + attribute \src "libresoc.v:97299.5-97299.29" switch \initial - attribute \src "libresoc.v:97614.9-97614.17" + attribute \src "libresoc.v:97299.9-97299.17" case 1'1 case end @@ -152283,14 +151805,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] end - attribute \src "libresoc.v:97716.3-97818.6" - process $proc$libresoc.v:97716$3974 + attribute \src "libresoc.v:97401.3-97503.6" + process $proc$libresoc.v:97401$3958 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:97717.5-97717.29" + attribute \src "libresoc.v:97402.5-97402.29" switch \initial - attribute \src "libresoc.v:97717.9-97717.17" + attribute \src "libresoc.v:97402.9-97402.17" case 1'1 case end @@ -152430,14 +151952,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] end - attribute \src "libresoc.v:97819.3-97921.6" - process $proc$libresoc.v:97819$3975 + attribute \src "libresoc.v:97504.3-97606.6" + process $proc$libresoc.v:97504$3959 assign { } { } assign { } { } assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:97820.5-97820.29" + attribute \src "libresoc.v:97505.5-97505.29" switch \initial - attribute \src "libresoc.v:97820.9-97820.17" + attribute \src "libresoc.v:97505.9-97505.17" case 1'1 case end @@ -152577,14 +152099,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] end - attribute \src "libresoc.v:97922.3-98024.6" - process $proc$libresoc.v:97922$3976 + attribute \src "libresoc.v:97607.3-97709.6" + process $proc$libresoc.v:97607$3960 assign { } { } assign { } { } assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:97923.5-97923.29" + attribute \src "libresoc.v:97608.5-97608.29" switch \initial - attribute \src "libresoc.v:97923.9-97923.17" + attribute \src "libresoc.v:97608.9-97608.17" case 1'1 case end @@ -152724,14 +152246,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] end - attribute \src "libresoc.v:98025.3-98127.6" - process $proc$libresoc.v:98025$3977 + attribute \src "libresoc.v:97710.3-97812.6" + process $proc$libresoc.v:97710$3961 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:98026.5-98026.29" + attribute \src "libresoc.v:97711.5-97711.29" switch \initial - attribute \src "libresoc.v:98026.9-98026.17" + attribute \src "libresoc.v:97711.9-97711.17" case 1'1 case end @@ -152871,14 +152393,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] end - attribute \src "libresoc.v:98128.3-98230.6" - process $proc$libresoc.v:98128$3978 + attribute \src "libresoc.v:97813.3-97915.6" + process $proc$libresoc.v:97813$3962 assign { } { } assign { } { } assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:98129.5-98129.29" + attribute \src "libresoc.v:97814.5-97814.29" switch \initial - attribute \src "libresoc.v:98129.9-98129.17" + attribute \src "libresoc.v:97814.9-97814.17" case 1'1 case end @@ -153018,14 +152540,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] end - attribute \src "libresoc.v:98231.3-98333.6" - process $proc$libresoc.v:98231$3979 + attribute \src "libresoc.v:97916.3-98018.6" + process $proc$libresoc.v:97916$3963 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:98232.5-98232.29" + attribute \src "libresoc.v:97917.5-97917.29" switch \initial - attribute \src "libresoc.v:98232.9-98232.17" + attribute \src "libresoc.v:97917.9-97917.17" case 1'1 case end @@ -153165,14 +152687,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] end - attribute \src "libresoc.v:98334.3-98436.6" - process $proc$libresoc.v:98334$3980 + attribute \src "libresoc.v:98019.3-98121.6" + process $proc$libresoc.v:98019$3964 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Etype[1:0] $1\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:98335.5-98335.29" + attribute \src "libresoc.v:98020.5-98020.29" switch \initial - attribute \src "libresoc.v:98335.9-98335.17" + attribute \src "libresoc.v:98020.9-98020.17" case 1'1 case end @@ -153312,14 +152834,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_SV_Etype $0\dec31_dec_sub15_SV_Etype[1:0] end - attribute \src "libresoc.v:98437.3-98539.6" - process $proc$libresoc.v:98437$3981 + attribute \src "libresoc.v:98122.3-98224.6" + process $proc$libresoc.v:98122$3965 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Ptype[1:0] $1\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:98438.5-98438.29" + attribute \src "libresoc.v:98123.5-98123.29" switch \initial - attribute \src "libresoc.v:98438.9-98438.17" + attribute \src "libresoc.v:98123.9-98123.17" case 1'1 case end @@ -153459,14 +152981,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_SV_Ptype $0\dec31_dec_sub15_SV_Ptype[1:0] end - attribute \src "libresoc.v:98540.3-98642.6" - process $proc$libresoc.v:98540$3982 + attribute \src "libresoc.v:98225.3-98327.6" + process $proc$libresoc.v:98225$3966 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:98541.5-98541.29" + attribute \src "libresoc.v:98226.5-98226.29" switch \initial - attribute \src "libresoc.v:98541.9-98541.17" + attribute \src "libresoc.v:98226.9-98226.17" case 1'1 case end @@ -153606,14 +153128,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] end - attribute \src "libresoc.v:98643.3-98745.6" - process $proc$libresoc.v:98643$3983 + attribute \src "libresoc.v:98328.3-98430.6" + process $proc$libresoc.v:98328$3967 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:98644.5-98644.29" + attribute \src "libresoc.v:98329.5-98329.29" switch \initial - attribute \src "libresoc.v:98644.9-98644.17" + attribute \src "libresoc.v:98329.9-98329.17" case 1'1 case end @@ -153753,14 +153275,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] end - attribute \src "libresoc.v:98746.3-98848.6" - process $proc$libresoc.v:98746$3984 + attribute \src "libresoc.v:98431.3-98533.6" + process $proc$libresoc.v:98431$3968 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:98747.5-98747.29" + attribute \src "libresoc.v:98432.5-98432.29" switch \initial - attribute \src "libresoc.v:98747.9-98747.17" + attribute \src "libresoc.v:98432.9-98432.17" case 1'1 case end @@ -153900,14 +153422,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] end - attribute \src "libresoc.v:98849.3-98951.6" - process $proc$libresoc.v:98849$3985 + attribute \src "libresoc.v:98534.3-98636.6" + process $proc$libresoc.v:98534$3969 assign { } { } assign { } { } assign $0\dec31_dec_sub15_out_sel[2:0] $1\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:98850.5-98850.29" + attribute \src "libresoc.v:98535.5-98535.29" switch \initial - attribute \src "libresoc.v:98850.9-98850.17" + attribute \src "libresoc.v:98535.9-98535.17" case 1'1 case end @@ -154049,144 +153571,144 @@ module \dec31_dec_sub15 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:98957.1-99637.10" +attribute \src "libresoc.v:98642.1-99322.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" attribute \generator "nMigen" module \dec31_dec_sub16 - attribute \src "libresoc.v:99576.3-99585.6" + attribute \src "libresoc.v:99261.3-99270.6" wire width 2 $0\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:99586.3-99595.6" + attribute \src "libresoc.v:99271.3-99280.6" wire width 2 $0\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:99456.3-99465.6" + attribute \src "libresoc.v:99141.3-99150.6" wire width 8 $0\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:99496.3-99505.6" + attribute \src "libresoc.v:99181.3-99190.6" wire $0\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:99316.3-99325.6" + attribute \src "libresoc.v:99001.3-99010.6" wire width 3 $0\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:99326.3-99335.6" + attribute \src "libresoc.v:99011.3-99020.6" wire width 3 $0\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:99446.3-99455.6" + attribute \src "libresoc.v:99131.3-99140.6" wire width 2 $0\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:99486.3-99495.6" + attribute \src "libresoc.v:99171.3-99180.6" wire $0\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:99526.3-99535.6" + attribute \src "libresoc.v:99211.3-99220.6" wire width 5 $0\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:99306.3-99315.6" + attribute \src "libresoc.v:98991.3-99000.6" wire width 14 $0\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:99596.3-99605.6" + attribute \src "libresoc.v:99281.3-99290.6" wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:99606.3-99615.6" + attribute \src "libresoc.v:99291.3-99300.6" wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:99616.3-99625.6" + attribute \src "libresoc.v:99301.3-99310.6" wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:99416.3-99425.6" + attribute \src "libresoc.v:99101.3-99110.6" wire width 7 $0\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:99466.3-99475.6" + attribute \src "libresoc.v:99151.3-99160.6" wire $0\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:99476.3-99485.6" + attribute \src "libresoc.v:99161.3-99170.6" wire $0\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:99536.3-99545.6" + attribute \src "libresoc.v:99221.3-99230.6" wire $0\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:99406.3-99415.6" + attribute \src "libresoc.v:99091.3-99100.6" wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:99556.3-99565.6" + attribute \src "libresoc.v:99241.3-99250.6" wire $0\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:99626.3-99635.6" + attribute \src "libresoc.v:99311.3-99320.6" wire width 3 $0\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:99436.3-99445.6" + attribute \src "libresoc.v:99121.3-99130.6" wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:99516.3-99525.6" + attribute \src "libresoc.v:99201.3-99210.6" wire $0\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:99566.3-99575.6" + attribute \src "libresoc.v:99251.3-99260.6" wire $0\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:99546.3-99555.6" + attribute \src "libresoc.v:99231.3-99240.6" wire $0\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:99506.3-99515.6" + attribute \src "libresoc.v:99191.3-99200.6" wire $0\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:99386.3-99395.6" + attribute \src "libresoc.v:99071.3-99080.6" wire width 3 $0\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:99396.3-99405.6" + attribute \src "libresoc.v:99081.3-99090.6" wire width 3 $0\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:99336.3-99345.6" + attribute \src "libresoc.v:99021.3-99030.6" wire width 3 $0\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:99346.3-99355.6" + attribute \src "libresoc.v:99031.3-99040.6" wire width 3 $0\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:99356.3-99365.6" + attribute \src "libresoc.v:99041.3-99050.6" wire width 3 $0\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:99376.3-99385.6" + attribute \src "libresoc.v:99061.3-99070.6" wire width 3 $0\dec31_dec_sub16_sv_out2[2:0] - attribute \src "libresoc.v:99366.3-99375.6" + attribute \src "libresoc.v:99051.3-99060.6" wire width 3 $0\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:99426.3-99435.6" + attribute \src "libresoc.v:99111.3-99120.6" wire width 2 $0\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:98958.7-98958.20" + attribute \src "libresoc.v:98643.7-98643.20" wire $0\initial[0:0] - attribute \src "libresoc.v:99576.3-99585.6" + attribute \src "libresoc.v:99261.3-99270.6" wire width 2 $1\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:99586.3-99595.6" + attribute \src "libresoc.v:99271.3-99280.6" wire width 2 $1\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:99456.3-99465.6" + attribute \src "libresoc.v:99141.3-99150.6" wire width 8 $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:99496.3-99505.6" + attribute \src "libresoc.v:99181.3-99190.6" wire $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:99316.3-99325.6" + attribute \src "libresoc.v:99001.3-99010.6" wire width 3 $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:99326.3-99335.6" + attribute \src "libresoc.v:99011.3-99020.6" wire width 3 $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:99446.3-99455.6" + attribute \src "libresoc.v:99131.3-99140.6" wire width 2 $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:99486.3-99495.6" + attribute \src "libresoc.v:99171.3-99180.6" wire $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:99526.3-99535.6" + attribute \src "libresoc.v:99211.3-99220.6" wire width 5 $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:99306.3-99315.6" + attribute \src "libresoc.v:98991.3-99000.6" wire width 14 $1\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:99596.3-99605.6" + attribute \src "libresoc.v:99281.3-99290.6" wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:99606.3-99615.6" + attribute \src "libresoc.v:99291.3-99300.6" wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:99616.3-99625.6" + attribute \src "libresoc.v:99301.3-99310.6" wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:99416.3-99425.6" + attribute \src "libresoc.v:99101.3-99110.6" wire width 7 $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:99466.3-99475.6" + attribute \src "libresoc.v:99151.3-99160.6" wire $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:99476.3-99485.6" + attribute \src "libresoc.v:99161.3-99170.6" wire $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:99536.3-99545.6" + attribute \src "libresoc.v:99221.3-99230.6" wire $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:99406.3-99415.6" + attribute \src "libresoc.v:99091.3-99100.6" wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:99556.3-99565.6" + attribute \src "libresoc.v:99241.3-99250.6" wire $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:99626.3-99635.6" + attribute \src "libresoc.v:99311.3-99320.6" wire width 3 $1\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:99436.3-99445.6" + attribute \src "libresoc.v:99121.3-99130.6" wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:99516.3-99525.6" + attribute \src "libresoc.v:99201.3-99210.6" wire $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:99566.3-99575.6" + attribute \src "libresoc.v:99251.3-99260.6" wire $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:99546.3-99555.6" + attribute \src "libresoc.v:99231.3-99240.6" wire $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:99506.3-99515.6" + attribute \src "libresoc.v:99191.3-99200.6" wire $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:99386.3-99395.6" + attribute \src "libresoc.v:99071.3-99080.6" wire width 3 $1\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:99396.3-99405.6" + attribute \src "libresoc.v:99081.3-99090.6" wire width 3 $1\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:99336.3-99345.6" + attribute \src "libresoc.v:99021.3-99030.6" wire width 3 $1\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:99346.3-99355.6" + attribute \src "libresoc.v:99031.3-99040.6" wire width 3 $1\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:99356.3-99365.6" + attribute \src "libresoc.v:99041.3-99050.6" wire width 3 $1\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:99376.3-99385.6" + attribute \src "libresoc.v:99061.3-99070.6" wire width 3 $1\dec31_dec_sub16_sv_out2[2:0] - attribute \src "libresoc.v:99366.3-99375.6" + attribute \src "libresoc.v:99051.3-99060.6" wire width 3 $1\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:99426.3-99435.6" + attribute \src "libresoc.v:99111.3-99120.6" wire width 2 $1\dec31_dec_sub16_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -154498,28 +154020,28 @@ module \dec31_dec_sub16 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub16_upd - attribute \src "libresoc.v:98958.7-98958.15" + attribute \src "libresoc.v:98643.7-98643.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:98958.7-98958.20" - process $proc$libresoc.v:98958$4020 + attribute \src "libresoc.v:98643.7-98643.20" + process $proc$libresoc.v:98643$4004 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:99306.3-99315.6" - process $proc$libresoc.v:99306$3987 + attribute \src "libresoc.v:98991.3-99000.6" + process $proc$libresoc.v:98991$3971 assign { } { } assign { } { } assign $0\dec31_dec_sub16_function_unit[13:0] $1\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:99307.5-99307.29" + attribute \src "libresoc.v:98992.5-98992.29" switch \initial - attribute \src "libresoc.v:99307.9-99307.17" + attribute \src "libresoc.v:98992.9-98992.17" case 1'1 case end @@ -154535,14 +154057,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[13:0] end - attribute \src "libresoc.v:99316.3-99325.6" - process $proc$libresoc.v:99316$3988 + attribute \src "libresoc.v:99001.3-99010.6" + process $proc$libresoc.v:99001$3972 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:99317.5-99317.29" + attribute \src "libresoc.v:99002.5-99002.29" switch \initial - attribute \src "libresoc.v:99317.9-99317.17" + attribute \src "libresoc.v:99002.9-99002.17" case 1'1 case end @@ -154558,14 +154080,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] end - attribute \src "libresoc.v:99326.3-99335.6" - process $proc$libresoc.v:99326$3989 + attribute \src "libresoc.v:99011.3-99020.6" + process $proc$libresoc.v:99011$3973 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:99327.5-99327.29" + attribute \src "libresoc.v:99012.5-99012.29" switch \initial - attribute \src "libresoc.v:99327.9-99327.17" + attribute \src "libresoc.v:99012.9-99012.17" case 1'1 case end @@ -154581,14 +154103,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] end - attribute \src "libresoc.v:99336.3-99345.6" - process $proc$libresoc.v:99336$3990 + attribute \src "libresoc.v:99021.3-99030.6" + process $proc$libresoc.v:99021$3974 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in1[2:0] $1\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:99337.5-99337.29" + attribute \src "libresoc.v:99022.5-99022.29" switch \initial - attribute \src "libresoc.v:99337.9-99337.17" + attribute \src "libresoc.v:99022.9-99022.17" case 1'1 case end @@ -154604,14 +154126,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in1 $0\dec31_dec_sub16_sv_in1[2:0] end - attribute \src "libresoc.v:99346.3-99355.6" - process $proc$libresoc.v:99346$3991 + attribute \src "libresoc.v:99031.3-99040.6" + process $proc$libresoc.v:99031$3975 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in2[2:0] $1\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:99347.5-99347.29" + attribute \src "libresoc.v:99032.5-99032.29" switch \initial - attribute \src "libresoc.v:99347.9-99347.17" + attribute \src "libresoc.v:99032.9-99032.17" case 1'1 case end @@ -154627,14 +154149,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in2 $0\dec31_dec_sub16_sv_in2[2:0] end - attribute \src "libresoc.v:99356.3-99365.6" - process $proc$libresoc.v:99356$3992 + attribute \src "libresoc.v:99041.3-99050.6" + process $proc$libresoc.v:99041$3976 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in3[2:0] $1\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:99357.5-99357.29" + attribute \src "libresoc.v:99042.5-99042.29" switch \initial - attribute \src "libresoc.v:99357.9-99357.17" + attribute \src "libresoc.v:99042.9-99042.17" case 1'1 case end @@ -154650,14 +154172,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in3 $0\dec31_dec_sub16_sv_in3[2:0] end - attribute \src "libresoc.v:99366.3-99375.6" - process $proc$libresoc.v:99366$3993 + attribute \src "libresoc.v:99051.3-99060.6" + process $proc$libresoc.v:99051$3977 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_out[2:0] $1\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:99367.5-99367.29" + attribute \src "libresoc.v:99052.5-99052.29" switch \initial - attribute \src "libresoc.v:99367.9-99367.17" + attribute \src "libresoc.v:99052.9-99052.17" case 1'1 case end @@ -154673,14 +154195,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_out $0\dec31_dec_sub16_sv_out[2:0] end - attribute \src "libresoc.v:99376.3-99385.6" - process $proc$libresoc.v:99376$3994 + attribute \src "libresoc.v:99061.3-99070.6" + process $proc$libresoc.v:99061$3978 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_out2[2:0] $1\dec31_dec_sub16_sv_out2[2:0] - attribute \src "libresoc.v:99377.5-99377.29" + attribute \src "libresoc.v:99062.5-99062.29" switch \initial - attribute \src "libresoc.v:99377.9-99377.17" + attribute \src "libresoc.v:99062.9-99062.17" case 1'1 case end @@ -154696,14 +154218,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_out2 $0\dec31_dec_sub16_sv_out2[2:0] end - attribute \src "libresoc.v:99386.3-99395.6" - process $proc$libresoc.v:99386$3995 + attribute \src "libresoc.v:99071.3-99080.6" + process $proc$libresoc.v:99071$3979 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_in[2:0] $1\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:99387.5-99387.29" + attribute \src "libresoc.v:99072.5-99072.29" switch \initial - attribute \src "libresoc.v:99387.9-99387.17" + attribute \src "libresoc.v:99072.9-99072.17" case 1'1 case end @@ -154719,14 +154241,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_cr_in $0\dec31_dec_sub16_sv_cr_in[2:0] end - attribute \src "libresoc.v:99396.3-99405.6" - process $proc$libresoc.v:99396$3996 + attribute \src "libresoc.v:99081.3-99090.6" + process $proc$libresoc.v:99081$3980 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_out[2:0] $1\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:99397.5-99397.29" + attribute \src "libresoc.v:99082.5-99082.29" switch \initial - attribute \src "libresoc.v:99397.9-99397.17" + attribute \src "libresoc.v:99082.9-99082.17" case 1'1 case end @@ -154742,14 +154264,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_cr_out $0\dec31_dec_sub16_sv_cr_out[2:0] end - attribute \src "libresoc.v:99406.3-99415.6" - process $proc$libresoc.v:99406$3997 + attribute \src "libresoc.v:99091.3-99100.6" + process $proc$libresoc.v:99091$3981 assign { } { } assign { } { } assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:99407.5-99407.29" + attribute \src "libresoc.v:99092.5-99092.29" switch \initial - attribute \src "libresoc.v:99407.9-99407.17" + attribute \src "libresoc.v:99092.9-99092.17" case 1'1 case end @@ -154765,14 +154287,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] end - attribute \src "libresoc.v:99416.3-99425.6" - process $proc$libresoc.v:99416$3998 + attribute \src "libresoc.v:99101.3-99110.6" + process $proc$libresoc.v:99101$3982 assign { } { } assign { } { } assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:99417.5-99417.29" + attribute \src "libresoc.v:99102.5-99102.29" switch \initial - attribute \src "libresoc.v:99417.9-99417.17" + attribute \src "libresoc.v:99102.9-99102.17" case 1'1 case end @@ -154788,14 +154310,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] end - attribute \src "libresoc.v:99426.3-99435.6" - process $proc$libresoc.v:99426$3999 + attribute \src "libresoc.v:99111.3-99120.6" + process $proc$libresoc.v:99111$3983 assign { } { } assign { } { } assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:99427.5-99427.29" + attribute \src "libresoc.v:99112.5-99112.29" switch \initial - attribute \src "libresoc.v:99427.9-99427.17" + attribute \src "libresoc.v:99112.9-99112.17" case 1'1 case end @@ -154811,14 +154333,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] end - attribute \src "libresoc.v:99436.3-99445.6" - process $proc$libresoc.v:99436$4000 + attribute \src "libresoc.v:99121.3-99130.6" + process $proc$libresoc.v:99121$3984 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:99437.5-99437.29" + attribute \src "libresoc.v:99122.5-99122.29" switch \initial - attribute \src "libresoc.v:99437.9-99437.17" + attribute \src "libresoc.v:99122.9-99122.17" case 1'1 case end @@ -154834,14 +154356,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] end - attribute \src "libresoc.v:99446.3-99455.6" - process $proc$libresoc.v:99446$4001 + attribute \src "libresoc.v:99131.3-99140.6" + process $proc$libresoc.v:99131$3985 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:99447.5-99447.29" + attribute \src "libresoc.v:99132.5-99132.29" switch \initial - attribute \src "libresoc.v:99447.9-99447.17" + attribute \src "libresoc.v:99132.9-99132.17" case 1'1 case end @@ -154857,14 +154379,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] end - attribute \src "libresoc.v:99456.3-99465.6" - process $proc$libresoc.v:99456$4002 + attribute \src "libresoc.v:99141.3-99150.6" + process $proc$libresoc.v:99141$3986 assign { } { } assign { } { } assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:99457.5-99457.29" + attribute \src "libresoc.v:99142.5-99142.29" switch \initial - attribute \src "libresoc.v:99457.9-99457.17" + attribute \src "libresoc.v:99142.9-99142.17" case 1'1 case end @@ -154880,14 +154402,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] end - attribute \src "libresoc.v:99466.3-99475.6" - process $proc$libresoc.v:99466$4003 + attribute \src "libresoc.v:99151.3-99160.6" + process $proc$libresoc.v:99151$3987 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:99467.5-99467.29" + attribute \src "libresoc.v:99152.5-99152.29" switch \initial - attribute \src "libresoc.v:99467.9-99467.17" + attribute \src "libresoc.v:99152.9-99152.17" case 1'1 case end @@ -154903,14 +154425,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] end - attribute \src "libresoc.v:99476.3-99485.6" - process $proc$libresoc.v:99476$4004 + attribute \src "libresoc.v:99161.3-99170.6" + process $proc$libresoc.v:99161$3988 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:99477.5-99477.29" + attribute \src "libresoc.v:99162.5-99162.29" switch \initial - attribute \src "libresoc.v:99477.9-99477.17" + attribute \src "libresoc.v:99162.9-99162.17" case 1'1 case end @@ -154926,14 +154448,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] end - attribute \src "libresoc.v:99486.3-99495.6" - process $proc$libresoc.v:99486$4005 + attribute \src "libresoc.v:99171.3-99180.6" + process $proc$libresoc.v:99171$3989 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:99487.5-99487.29" + attribute \src "libresoc.v:99172.5-99172.29" switch \initial - attribute \src "libresoc.v:99487.9-99487.17" + attribute \src "libresoc.v:99172.9-99172.17" case 1'1 case end @@ -154949,14 +154471,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] end - attribute \src "libresoc.v:99496.3-99505.6" - process $proc$libresoc.v:99496$4006 + attribute \src "libresoc.v:99181.3-99190.6" + process $proc$libresoc.v:99181$3990 assign { } { } assign { } { } assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:99497.5-99497.29" + attribute \src "libresoc.v:99182.5-99182.29" switch \initial - attribute \src "libresoc.v:99497.9-99497.17" + attribute \src "libresoc.v:99182.9-99182.17" case 1'1 case end @@ -154972,14 +154494,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] end - attribute \src "libresoc.v:99506.3-99515.6" - process $proc$libresoc.v:99506$4007 + attribute \src "libresoc.v:99191.3-99200.6" + process $proc$libresoc.v:99191$3991 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:99507.5-99507.29" + attribute \src "libresoc.v:99192.5-99192.29" switch \initial - attribute \src "libresoc.v:99507.9-99507.17" + attribute \src "libresoc.v:99192.9-99192.17" case 1'1 case end @@ -154995,14 +154517,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] end - attribute \src "libresoc.v:99516.3-99525.6" - process $proc$libresoc.v:99516$4008 + attribute \src "libresoc.v:99201.3-99210.6" + process $proc$libresoc.v:99201$3992 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:99517.5-99517.29" + attribute \src "libresoc.v:99202.5-99202.29" switch \initial - attribute \src "libresoc.v:99517.9-99517.17" + attribute \src "libresoc.v:99202.9-99202.17" case 1'1 case end @@ -155018,14 +154540,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] end - attribute \src "libresoc.v:99526.3-99535.6" - process $proc$libresoc.v:99526$4009 + attribute \src "libresoc.v:99211.3-99220.6" + process $proc$libresoc.v:99211$3993 assign { } { } assign { } { } assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:99527.5-99527.29" + attribute \src "libresoc.v:99212.5-99212.29" switch \initial - attribute \src "libresoc.v:99527.9-99527.17" + attribute \src "libresoc.v:99212.9-99212.17" case 1'1 case end @@ -155041,14 +154563,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] end - attribute \src "libresoc.v:99536.3-99545.6" - process $proc$libresoc.v:99536$4010 + attribute \src "libresoc.v:99221.3-99230.6" + process $proc$libresoc.v:99221$3994 assign { } { } assign { } { } assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:99537.5-99537.29" + attribute \src "libresoc.v:99222.5-99222.29" switch \initial - attribute \src "libresoc.v:99537.9-99537.17" + attribute \src "libresoc.v:99222.9-99222.17" case 1'1 case end @@ -155064,14 +154586,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] end - attribute \src "libresoc.v:99546.3-99555.6" - process $proc$libresoc.v:99546$4011 + attribute \src "libresoc.v:99231.3-99240.6" + process $proc$libresoc.v:99231$3995 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:99547.5-99547.29" + attribute \src "libresoc.v:99232.5-99232.29" switch \initial - attribute \src "libresoc.v:99547.9-99547.17" + attribute \src "libresoc.v:99232.9-99232.17" case 1'1 case end @@ -155087,14 +154609,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] end - attribute \src "libresoc.v:99556.3-99565.6" - process $proc$libresoc.v:99556$4012 + attribute \src "libresoc.v:99241.3-99250.6" + process $proc$libresoc.v:99241$3996 assign { } { } assign { } { } assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:99557.5-99557.29" + attribute \src "libresoc.v:99242.5-99242.29" switch \initial - attribute \src "libresoc.v:99557.9-99557.17" + attribute \src "libresoc.v:99242.9-99242.17" case 1'1 case end @@ -155110,14 +154632,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] end - attribute \src "libresoc.v:99566.3-99575.6" - process $proc$libresoc.v:99566$4013 + attribute \src "libresoc.v:99251.3-99260.6" + process $proc$libresoc.v:99251$3997 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:99567.5-99567.29" + attribute \src "libresoc.v:99252.5-99252.29" switch \initial - attribute \src "libresoc.v:99567.9-99567.17" + attribute \src "libresoc.v:99252.9-99252.17" case 1'1 case end @@ -155133,14 +154655,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] end - attribute \src "libresoc.v:99576.3-99585.6" - process $proc$libresoc.v:99576$4014 + attribute \src "libresoc.v:99261.3-99270.6" + process $proc$libresoc.v:99261$3998 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Etype[1:0] $1\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:99577.5-99577.29" + attribute \src "libresoc.v:99262.5-99262.29" switch \initial - attribute \src "libresoc.v:99577.9-99577.17" + attribute \src "libresoc.v:99262.9-99262.17" case 1'1 case end @@ -155156,14 +154678,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_SV_Etype $0\dec31_dec_sub16_SV_Etype[1:0] end - attribute \src "libresoc.v:99586.3-99595.6" - process $proc$libresoc.v:99586$4015 + attribute \src "libresoc.v:99271.3-99280.6" + process $proc$libresoc.v:99271$3999 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Ptype[1:0] $1\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:99587.5-99587.29" + attribute \src "libresoc.v:99272.5-99272.29" switch \initial - attribute \src "libresoc.v:99587.9-99587.17" + attribute \src "libresoc.v:99272.9-99272.17" case 1'1 case end @@ -155179,14 +154701,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_SV_Ptype $0\dec31_dec_sub16_SV_Ptype[1:0] end - attribute \src "libresoc.v:99596.3-99605.6" - process $proc$libresoc.v:99596$4016 + attribute \src "libresoc.v:99281.3-99290.6" + process $proc$libresoc.v:99281$4000 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:99597.5-99597.29" + attribute \src "libresoc.v:99282.5-99282.29" switch \initial - attribute \src "libresoc.v:99597.9-99597.17" + attribute \src "libresoc.v:99282.9-99282.17" case 1'1 case end @@ -155202,14 +154724,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] end - attribute \src "libresoc.v:99606.3-99615.6" - process $proc$libresoc.v:99606$4017 + attribute \src "libresoc.v:99291.3-99300.6" + process $proc$libresoc.v:99291$4001 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:99607.5-99607.29" + attribute \src "libresoc.v:99292.5-99292.29" switch \initial - attribute \src "libresoc.v:99607.9-99607.17" + attribute \src "libresoc.v:99292.9-99292.17" case 1'1 case end @@ -155225,14 +154747,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] end - attribute \src "libresoc.v:99616.3-99625.6" - process $proc$libresoc.v:99616$4018 + attribute \src "libresoc.v:99301.3-99310.6" + process $proc$libresoc.v:99301$4002 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:99617.5-99617.29" + attribute \src "libresoc.v:99302.5-99302.29" switch \initial - attribute \src "libresoc.v:99617.9-99617.17" + attribute \src "libresoc.v:99302.9-99302.17" case 1'1 case end @@ -155248,14 +154770,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] end - attribute \src "libresoc.v:99626.3-99635.6" - process $proc$libresoc.v:99626$4019 + attribute \src "libresoc.v:99311.3-99320.6" + process $proc$libresoc.v:99311$4003 assign { } { } assign { } { } assign $0\dec31_dec_sub16_out_sel[2:0] $1\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:99627.5-99627.29" + attribute \src "libresoc.v:99312.5-99312.29" switch \initial - attribute \src "libresoc.v:99627.9-99627.17" + attribute \src "libresoc.v:99312.9-99312.17" case 1'1 case end @@ -155273,144 +154795,144 @@ module \dec31_dec_sub16 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:99641.1-100717.10" +attribute \src "libresoc.v:99326.1-100402.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" attribute \generator "nMigen" module \dec31_dec_sub18 - attribute \src "libresoc.v:100584.3-100605.6" + attribute \src "libresoc.v:100269.3-100290.6" wire width 2 $0\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:100606.3-100627.6" + attribute \src "libresoc.v:100291.3-100312.6" wire width 2 $0\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:100320.3-100341.6" + attribute \src "libresoc.v:100005.3-100026.6" wire width 8 $0\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:100408.3-100429.6" + attribute \src "libresoc.v:100093.3-100114.6" wire $0\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:100012.3-100033.6" + attribute \src "libresoc.v:99697.3-99718.6" wire width 3 $0\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:100034.3-100055.6" + attribute \src "libresoc.v:99719.3-99740.6" wire width 3 $0\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:100298.3-100319.6" + attribute \src "libresoc.v:99983.3-100004.6" wire width 2 $0\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:100386.3-100407.6" + attribute \src "libresoc.v:100071.3-100092.6" wire $0\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:100474.3-100495.6" + attribute \src "libresoc.v:100159.3-100180.6" wire width 5 $0\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:99990.3-100011.6" + attribute \src "libresoc.v:99675.3-99696.6" wire width 14 $0\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:100628.3-100649.6" + attribute \src "libresoc.v:100313.3-100334.6" wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:100650.3-100671.6" + attribute \src "libresoc.v:100335.3-100356.6" wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:100672.3-100693.6" + attribute \src "libresoc.v:100357.3-100378.6" wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:100232.3-100253.6" + attribute \src "libresoc.v:99917.3-99938.6" wire width 7 $0\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:100342.3-100363.6" + attribute \src "libresoc.v:100027.3-100048.6" wire $0\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:100364.3-100385.6" + attribute \src "libresoc.v:100049.3-100070.6" wire $0\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:100496.3-100517.6" + attribute \src "libresoc.v:100181.3-100202.6" wire $0\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:100210.3-100231.6" + attribute \src "libresoc.v:99895.3-99916.6" wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:100540.3-100561.6" + attribute \src "libresoc.v:100225.3-100246.6" wire $0\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:100694.3-100715.6" + attribute \src "libresoc.v:100379.3-100400.6" wire width 3 $0\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:100276.3-100297.6" + attribute \src "libresoc.v:99961.3-99982.6" wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:100452.3-100473.6" + attribute \src "libresoc.v:100137.3-100158.6" wire $0\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:100562.3-100583.6" + attribute \src "libresoc.v:100247.3-100268.6" wire $0\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:100518.3-100539.6" + attribute \src "libresoc.v:100203.3-100224.6" wire $0\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:100430.3-100451.6" + attribute \src "libresoc.v:100115.3-100136.6" wire $0\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:100166.3-100187.6" + attribute \src "libresoc.v:99851.3-99872.6" wire width 3 $0\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:100188.3-100209.6" + attribute \src "libresoc.v:99873.3-99894.6" wire width 3 $0\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:100056.3-100077.6" + attribute \src "libresoc.v:99741.3-99762.6" wire width 3 $0\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:100078.3-100099.6" + attribute \src "libresoc.v:99763.3-99784.6" wire width 3 $0\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:100100.3-100121.6" + attribute \src "libresoc.v:99785.3-99806.6" wire width 3 $0\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:100144.3-100165.6" + attribute \src "libresoc.v:99829.3-99850.6" wire width 3 $0\dec31_dec_sub18_sv_out2[2:0] - attribute \src "libresoc.v:100122.3-100143.6" + attribute \src "libresoc.v:99807.3-99828.6" wire width 3 $0\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:100254.3-100275.6" + attribute \src "libresoc.v:99939.3-99960.6" wire width 2 $0\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:99642.7-99642.20" + attribute \src "libresoc.v:99327.7-99327.20" wire $0\initial[0:0] - attribute \src "libresoc.v:100584.3-100605.6" + attribute \src "libresoc.v:100269.3-100290.6" wire width 2 $1\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:100606.3-100627.6" + attribute \src "libresoc.v:100291.3-100312.6" wire width 2 $1\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:100320.3-100341.6" + attribute \src "libresoc.v:100005.3-100026.6" wire width 8 $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:100408.3-100429.6" + attribute \src "libresoc.v:100093.3-100114.6" wire $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:100012.3-100033.6" + attribute \src "libresoc.v:99697.3-99718.6" wire width 3 $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:100034.3-100055.6" + attribute \src "libresoc.v:99719.3-99740.6" wire width 3 $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:100298.3-100319.6" + attribute \src "libresoc.v:99983.3-100004.6" wire width 2 $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:100386.3-100407.6" + attribute \src "libresoc.v:100071.3-100092.6" wire $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:100474.3-100495.6" + attribute \src "libresoc.v:100159.3-100180.6" wire width 5 $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:99990.3-100011.6" + attribute \src "libresoc.v:99675.3-99696.6" wire width 14 $1\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:100628.3-100649.6" + attribute \src "libresoc.v:100313.3-100334.6" wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:100650.3-100671.6" + attribute \src "libresoc.v:100335.3-100356.6" wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:100672.3-100693.6" + attribute \src "libresoc.v:100357.3-100378.6" wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:100232.3-100253.6" + attribute \src "libresoc.v:99917.3-99938.6" wire width 7 $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:100342.3-100363.6" + attribute \src "libresoc.v:100027.3-100048.6" wire $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:100364.3-100385.6" + attribute \src "libresoc.v:100049.3-100070.6" wire $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:100496.3-100517.6" + attribute \src "libresoc.v:100181.3-100202.6" wire $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:100210.3-100231.6" + attribute \src "libresoc.v:99895.3-99916.6" wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:100540.3-100561.6" + attribute \src "libresoc.v:100225.3-100246.6" wire $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:100694.3-100715.6" + attribute \src "libresoc.v:100379.3-100400.6" wire width 3 $1\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:100276.3-100297.6" + attribute \src "libresoc.v:99961.3-99982.6" wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:100452.3-100473.6" + attribute \src "libresoc.v:100137.3-100158.6" wire $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:100562.3-100583.6" + attribute \src "libresoc.v:100247.3-100268.6" wire $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:100518.3-100539.6" + attribute \src "libresoc.v:100203.3-100224.6" wire $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:100430.3-100451.6" + attribute \src "libresoc.v:100115.3-100136.6" wire $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:100166.3-100187.6" + attribute \src "libresoc.v:99851.3-99872.6" wire width 3 $1\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:100188.3-100209.6" + attribute \src "libresoc.v:99873.3-99894.6" wire width 3 $1\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:100056.3-100077.6" + attribute \src "libresoc.v:99741.3-99762.6" wire width 3 $1\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:100078.3-100099.6" + attribute \src "libresoc.v:99763.3-99784.6" wire width 3 $1\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:100100.3-100121.6" + attribute \src "libresoc.v:99785.3-99806.6" wire width 3 $1\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:100144.3-100165.6" + attribute \src "libresoc.v:99829.3-99850.6" wire width 3 $1\dec31_dec_sub18_sv_out2[2:0] - attribute \src "libresoc.v:100122.3-100143.6" + attribute \src "libresoc.v:99807.3-99828.6" wire width 3 $1\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:100254.3-100275.6" + attribute \src "libresoc.v:99939.3-99960.6" wire width 2 $1\dec31_dec_sub18_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -155722,566 +155244,20 @@ module \dec31_dec_sub18 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub18_upd - attribute \src "libresoc.v:99642.7-99642.15" + attribute \src "libresoc.v:99327.7-99327.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:100012.3-100033.6" - process $proc$libresoc.v:100012$4022 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:100013.5-100013.29" - switch \initial - attribute \src "libresoc.v:100013.9-100013.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] - end - attribute \src "libresoc.v:100034.3-100055.6" - process $proc$libresoc.v:100034$4023 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:100035.5-100035.29" - switch \initial - attribute \src "libresoc.v:100035.9-100035.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] - end - attribute \src "libresoc.v:100056.3-100077.6" - process $proc$libresoc.v:100056$4024 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:100057.5-100057.29" - switch \initial - attribute \src "libresoc.v:100057.9-100057.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 - case - assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0] - end - attribute \src "libresoc.v:100078.3-100099.6" - process $proc$libresoc.v:100078$4025 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:100079.5-100079.29" - switch \initial - attribute \src "libresoc.v:100079.9-100079.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 - case - assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0] - end - attribute \src "libresoc.v:100100.3-100121.6" - process $proc$libresoc.v:100100$4026 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:100101.5-100101.29" - switch \initial - attribute \src "libresoc.v:100101.9-100101.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 - case - assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0] - end - attribute \src "libresoc.v:100122.3-100143.6" - process $proc$libresoc.v:100122$4027 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:100123.5-100123.29" - switch \initial - attribute \src "libresoc.v:100123.9-100123.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 - case - assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0] - end - attribute \src "libresoc.v:100144.3-100165.6" - process $proc$libresoc.v:100144$4028 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sv_out2[2:0] $1\dec31_dec_sub18_sv_out2[2:0] - attribute \src "libresoc.v:100145.5-100145.29" - switch \initial - attribute \src "libresoc.v:100145.9-100145.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 - case - assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_sv_out2 $0\dec31_dec_sub18_sv_out2[2:0] - end - attribute \src "libresoc.v:100166.3-100187.6" - process $proc$libresoc.v:100166$4029 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:100167.5-100167.29" - switch \initial - attribute \src "libresoc.v:100167.9-100167.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0] - end - attribute \src "libresoc.v:100188.3-100209.6" - process $proc$libresoc.v:100188$4030 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:100189.5-100189.29" - switch \initial - attribute \src "libresoc.v:100189.9-100189.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0] - end - attribute \src "libresoc.v:100210.3-100231.6" - process $proc$libresoc.v:100210$4031 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:100211.5-100211.29" - switch \initial - attribute \src "libresoc.v:100211.9-100211.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] - end - attribute \src "libresoc.v:100232.3-100253.6" - process $proc$libresoc.v:100232$4032 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:100233.5-100233.29" - switch \initial - attribute \src "libresoc.v:100233.9-100233.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 - case - assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] - end - attribute \src "libresoc.v:100254.3-100275.6" - process $proc$libresoc.v:100254$4033 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:100255.5-100255.29" - switch \initial - attribute \src "libresoc.v:100255.9-100255.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] - end - attribute \src "libresoc.v:100276.3-100297.6" - process $proc$libresoc.v:100276$4034 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:100277.5-100277.29" - switch \initial - attribute \src "libresoc.v:100277.9-100277.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] - end - attribute \src "libresoc.v:100298.3-100319.6" - process $proc$libresoc.v:100298$4035 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:100299.5-100299.29" - switch \initial - attribute \src "libresoc.v:100299.9-100299.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] - end - attribute \src "libresoc.v:100320.3-100341.6" - process $proc$libresoc.v:100320$4036 + attribute \src "libresoc.v:100005.3-100026.6" + process $proc$libresoc.v:100005$4020 assign { } { } assign { } { } assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:100321.5-100321.29" + attribute \src "libresoc.v:100006.5-100006.29" switch \initial - attribute \src "libresoc.v:100321.9-100321.17" + attribute \src "libresoc.v:100006.9-100006.17" case 1'1 case end @@ -156313,14 +155289,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] end - attribute \src "libresoc.v:100342.3-100363.6" - process $proc$libresoc.v:100342$4037 + attribute \src "libresoc.v:100027.3-100048.6" + process $proc$libresoc.v:100027$4021 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:100343.5-100343.29" + attribute \src "libresoc.v:100028.5-100028.29" switch \initial - attribute \src "libresoc.v:100343.9-100343.17" + attribute \src "libresoc.v:100028.9-100028.17" case 1'1 case end @@ -156352,14 +155328,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] end - attribute \src "libresoc.v:100364.3-100385.6" - process $proc$libresoc.v:100364$4038 + attribute \src "libresoc.v:100049.3-100070.6" + process $proc$libresoc.v:100049$4022 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:100365.5-100365.29" + attribute \src "libresoc.v:100050.5-100050.29" switch \initial - attribute \src "libresoc.v:100365.9-100365.17" + attribute \src "libresoc.v:100050.9-100050.17" case 1'1 case end @@ -156391,14 +155367,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] end - attribute \src "libresoc.v:100386.3-100407.6" - process $proc$libresoc.v:100386$4039 + attribute \src "libresoc.v:100071.3-100092.6" + process $proc$libresoc.v:100071$4023 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:100387.5-100387.29" + attribute \src "libresoc.v:100072.5-100072.29" switch \initial - attribute \src "libresoc.v:100387.9-100387.17" + attribute \src "libresoc.v:100072.9-100072.17" case 1'1 case end @@ -156430,14 +155406,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] end - attribute \src "libresoc.v:100408.3-100429.6" - process $proc$libresoc.v:100408$4040 + attribute \src "libresoc.v:100093.3-100114.6" + process $proc$libresoc.v:100093$4024 assign { } { } assign { } { } assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:100409.5-100409.29" + attribute \src "libresoc.v:100094.5-100094.29" switch \initial - attribute \src "libresoc.v:100409.9-100409.17" + attribute \src "libresoc.v:100094.9-100094.17" case 1'1 case end @@ -156469,14 +155445,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] end - attribute \src "libresoc.v:100430.3-100451.6" - process $proc$libresoc.v:100430$4041 + attribute \src "libresoc.v:100115.3-100136.6" + process $proc$libresoc.v:100115$4025 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:100431.5-100431.29" + attribute \src "libresoc.v:100116.5-100116.29" switch \initial - attribute \src "libresoc.v:100431.9-100431.17" + attribute \src "libresoc.v:100116.9-100116.17" case 1'1 case end @@ -156508,14 +155484,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] end - attribute \src "libresoc.v:100452.3-100473.6" - process $proc$libresoc.v:100452$4042 + attribute \src "libresoc.v:100137.3-100158.6" + process $proc$libresoc.v:100137$4026 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:100453.5-100453.29" + attribute \src "libresoc.v:100138.5-100138.29" switch \initial - attribute \src "libresoc.v:100453.9-100453.17" + attribute \src "libresoc.v:100138.9-100138.17" case 1'1 case end @@ -156547,14 +155523,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] end - attribute \src "libresoc.v:100474.3-100495.6" - process $proc$libresoc.v:100474$4043 + attribute \src "libresoc.v:100159.3-100180.6" + process $proc$libresoc.v:100159$4027 assign { } { } assign { } { } assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:100475.5-100475.29" + attribute \src "libresoc.v:100160.5-100160.29" switch \initial - attribute \src "libresoc.v:100475.9-100475.17" + attribute \src "libresoc.v:100160.9-100160.17" case 1'1 case end @@ -156586,14 +155562,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] end - attribute \src "libresoc.v:100496.3-100517.6" - process $proc$libresoc.v:100496$4044 + attribute \src "libresoc.v:100181.3-100202.6" + process $proc$libresoc.v:100181$4028 assign { } { } assign { } { } assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:100497.5-100497.29" + attribute \src "libresoc.v:100182.5-100182.29" switch \initial - attribute \src "libresoc.v:100497.9-100497.17" + attribute \src "libresoc.v:100182.9-100182.17" case 1'1 case end @@ -156625,14 +155601,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] end - attribute \src "libresoc.v:100518.3-100539.6" - process $proc$libresoc.v:100518$4045 + attribute \src "libresoc.v:100203.3-100224.6" + process $proc$libresoc.v:100203$4029 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:100519.5-100519.29" + attribute \src "libresoc.v:100204.5-100204.29" switch \initial - attribute \src "libresoc.v:100519.9-100519.17" + attribute \src "libresoc.v:100204.9-100204.17" case 1'1 case end @@ -156664,14 +155640,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] end - attribute \src "libresoc.v:100540.3-100561.6" - process $proc$libresoc.v:100540$4046 + attribute \src "libresoc.v:100225.3-100246.6" + process $proc$libresoc.v:100225$4030 assign { } { } assign { } { } assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:100541.5-100541.29" + attribute \src "libresoc.v:100226.5-100226.29" switch \initial - attribute \src "libresoc.v:100541.9-100541.17" + attribute \src "libresoc.v:100226.9-100226.17" case 1'1 case end @@ -156703,14 +155679,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] end - attribute \src "libresoc.v:100562.3-100583.6" - process $proc$libresoc.v:100562$4047 + attribute \src "libresoc.v:100247.3-100268.6" + process $proc$libresoc.v:100247$4031 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:100563.5-100563.29" + attribute \src "libresoc.v:100248.5-100248.29" switch \initial - attribute \src "libresoc.v:100563.9-100563.17" + attribute \src "libresoc.v:100248.9-100248.17" case 1'1 case end @@ -156742,14 +155718,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] end - attribute \src "libresoc.v:100584.3-100605.6" - process $proc$libresoc.v:100584$4048 + attribute \src "libresoc.v:100269.3-100290.6" + process $proc$libresoc.v:100269$4032 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Etype[1:0] $1\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:100585.5-100585.29" + attribute \src "libresoc.v:100270.5-100270.29" switch \initial - attribute \src "libresoc.v:100585.9-100585.17" + attribute \src "libresoc.v:100270.9-100270.17" case 1'1 case end @@ -156781,14 +155757,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_SV_Etype $0\dec31_dec_sub18_SV_Etype[1:0] end - attribute \src "libresoc.v:100606.3-100627.6" - process $proc$libresoc.v:100606$4049 + attribute \src "libresoc.v:100291.3-100312.6" + process $proc$libresoc.v:100291$4033 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Ptype[1:0] $1\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:100607.5-100607.29" + attribute \src "libresoc.v:100292.5-100292.29" switch \initial - attribute \src "libresoc.v:100607.9-100607.17" + attribute \src "libresoc.v:100292.9-100292.17" case 1'1 case end @@ -156820,14 +155796,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_SV_Ptype $0\dec31_dec_sub18_SV_Ptype[1:0] end - attribute \src "libresoc.v:100628.3-100649.6" - process $proc$libresoc.v:100628$4050 + attribute \src "libresoc.v:100313.3-100334.6" + process $proc$libresoc.v:100313$4034 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:100629.5-100629.29" + attribute \src "libresoc.v:100314.5-100314.29" switch \initial - attribute \src "libresoc.v:100629.9-100629.17" + attribute \src "libresoc.v:100314.9-100314.17" case 1'1 case end @@ -156859,14 +155835,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] end - attribute \src "libresoc.v:100650.3-100671.6" - process $proc$libresoc.v:100650$4051 + attribute \src "libresoc.v:100335.3-100356.6" + process $proc$libresoc.v:100335$4035 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:100651.5-100651.29" + attribute \src "libresoc.v:100336.5-100336.29" switch \initial - attribute \src "libresoc.v:100651.9-100651.17" + attribute \src "libresoc.v:100336.9-100336.17" case 1'1 case end @@ -156898,14 +155874,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] end - attribute \src "libresoc.v:100672.3-100693.6" - process $proc$libresoc.v:100672$4052 + attribute \src "libresoc.v:100357.3-100378.6" + process $proc$libresoc.v:100357$4036 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:100673.5-100673.29" + attribute \src "libresoc.v:100358.5-100358.29" switch \initial - attribute \src "libresoc.v:100673.9-100673.17" + attribute \src "libresoc.v:100358.9-100358.17" case 1'1 case end @@ -156937,14 +155913,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] end - attribute \src "libresoc.v:100694.3-100715.6" - process $proc$libresoc.v:100694$4053 + attribute \src "libresoc.v:100379.3-100400.6" + process $proc$libresoc.v:100379$4037 assign { } { } assign { } { } assign $0\dec31_dec_sub18_out_sel[2:0] $1\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:100695.5-100695.29" + attribute \src "libresoc.v:100380.5-100380.29" switch \initial - attribute \src "libresoc.v:100695.9-100695.17" + attribute \src "libresoc.v:100380.9-100380.17" case 1'1 case end @@ -156976,22 +155952,22 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[2:0] end - attribute \src "libresoc.v:99642.7-99642.20" - process $proc$libresoc.v:99642$4054 + attribute \src "libresoc.v:99327.7-99327.20" + process $proc$libresoc.v:99327$4038 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:99990.3-100011.6" - process $proc$libresoc.v:99990$4021 + attribute \src "libresoc.v:99675.3-99696.6" + process $proc$libresoc.v:99675$4005 assign { } { } assign { } { } assign $0\dec31_dec_sub18_function_unit[13:0] $1\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:99991.5-99991.29" + attribute \src "libresoc.v:99676.5-99676.29" switch \initial - attribute \src "libresoc.v:99991.9-99991.17" + attribute \src "libresoc.v:99676.9-99676.17" case 1'1 case end @@ -157023,146 +155999,692 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[13:0] end + attribute \src "libresoc.v:99697.3-99718.6" + process $proc$libresoc.v:99697$4006 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:99698.5-99698.29" + switch \initial + attribute \src "libresoc.v:99698.9-99698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] + end + attribute \src "libresoc.v:99719.3-99740.6" + process $proc$libresoc.v:99719$4007 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:99720.5-99720.29" + switch \initial + attribute \src "libresoc.v:99720.9-99720.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] + end + attribute \src "libresoc.v:99741.3-99762.6" + process $proc$libresoc.v:99741$4008 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0] + attribute \src "libresoc.v:99742.5-99742.29" + switch \initial + attribute \src "libresoc.v:99742.9-99742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0] + end + attribute \src "libresoc.v:99763.3-99784.6" + process $proc$libresoc.v:99763$4009 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0] + attribute \src "libresoc.v:99764.5-99764.29" + switch \initial + attribute \src "libresoc.v:99764.9-99764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0] + end + attribute \src "libresoc.v:99785.3-99806.6" + process $proc$libresoc.v:99785$4010 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0] + attribute \src "libresoc.v:99786.5-99786.29" + switch \initial + attribute \src "libresoc.v:99786.9-99786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0] + end + attribute \src "libresoc.v:99807.3-99828.6" + process $proc$libresoc.v:99807$4011 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0] + attribute \src "libresoc.v:99808.5-99808.29" + switch \initial + attribute \src "libresoc.v:99808.9-99808.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0] + end + attribute \src "libresoc.v:99829.3-99850.6" + process $proc$libresoc.v:99829$4012 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_out2[2:0] $1\dec31_dec_sub18_sv_out2[2:0] + attribute \src "libresoc.v:99830.5-99830.29" + switch \initial + attribute \src "libresoc.v:99830.9-99830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_out2 $0\dec31_dec_sub18_sv_out2[2:0] + end + attribute \src "libresoc.v:99851.3-99872.6" + process $proc$libresoc.v:99851$4013 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0] + attribute \src "libresoc.v:99852.5-99852.29" + switch \initial + attribute \src "libresoc.v:99852.9-99852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0] + end + attribute \src "libresoc.v:99873.3-99894.6" + process $proc$libresoc.v:99873$4014 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0] + attribute \src "libresoc.v:99874.5-99874.29" + switch \initial + attribute \src "libresoc.v:99874.9-99874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0] + end + attribute \src "libresoc.v:99895.3-99916.6" + process $proc$libresoc.v:99895$4015 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:99896.5-99896.29" + switch \initial + attribute \src "libresoc.v:99896.9-99896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] + end + attribute \src "libresoc.v:99917.3-99938.6" + process $proc$libresoc.v:99917$4016 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:99918.5-99918.29" + switch \initial + attribute \src "libresoc.v:99918.9-99918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + case + assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] + end + attribute \src "libresoc.v:99939.3-99960.6" + process $proc$libresoc.v:99939$4017 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:99940.5-99940.29" + switch \initial + attribute \src "libresoc.v:99940.9-99940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] + end + attribute \src "libresoc.v:99961.3-99982.6" + process $proc$libresoc.v:99961$4018 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:99962.5-99962.29" + switch \initial + attribute \src "libresoc.v:99962.9-99962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] + end + attribute \src "libresoc.v:99983.3-100004.6" + process $proc$libresoc.v:99983$4019 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:99984.5-99984.29" + switch \initial + attribute \src "libresoc.v:99984.9-99984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] + end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:100721.1-101698.10" +attribute \src "libresoc.v:100406.1-101383.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" attribute \generator "nMigen" module \dec31_dec_sub19 - attribute \src "libresoc.v:101583.3-101601.6" + attribute \src "libresoc.v:101268.3-101286.6" wire width 2 $0\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:101602.3-101620.6" + attribute \src "libresoc.v:101287.3-101305.6" wire width 2 $0\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:101355.3-101373.6" + attribute \src "libresoc.v:101040.3-101058.6" wire width 8 $0\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:101431.3-101449.6" + attribute \src "libresoc.v:101116.3-101134.6" wire $0\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:101089.3-101107.6" + attribute \src "libresoc.v:100774.3-100792.6" wire width 3 $0\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:101108.3-101126.6" + attribute \src "libresoc.v:100793.3-100811.6" wire width 3 $0\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:101336.3-101354.6" + attribute \src "libresoc.v:101021.3-101039.6" wire width 2 $0\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:101412.3-101430.6" + attribute \src "libresoc.v:101097.3-101115.6" wire $0\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:101488.3-101506.6" + attribute \src "libresoc.v:101173.3-101191.6" wire width 5 $0\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:101070.3-101088.6" + attribute \src "libresoc.v:100755.3-100773.6" wire width 14 $0\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:101621.3-101639.6" + attribute \src "libresoc.v:101306.3-101324.6" wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:101640.3-101658.6" + attribute \src "libresoc.v:101325.3-101343.6" wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:101659.3-101677.6" + attribute \src "libresoc.v:101344.3-101362.6" wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:101279.3-101297.6" + attribute \src "libresoc.v:100964.3-100982.6" wire width 7 $0\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:101374.3-101392.6" + attribute \src "libresoc.v:101059.3-101077.6" wire $0\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:101393.3-101411.6" + attribute \src "libresoc.v:101078.3-101096.6" wire $0\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:101507.3-101525.6" + attribute \src "libresoc.v:101192.3-101210.6" wire $0\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:101260.3-101278.6" + attribute \src "libresoc.v:100945.3-100963.6" wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:101545.3-101563.6" + attribute \src "libresoc.v:101230.3-101248.6" wire $0\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:101678.3-101696.6" + attribute \src "libresoc.v:101363.3-101381.6" wire width 3 $0\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:101317.3-101335.6" + attribute \src "libresoc.v:101002.3-101020.6" wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:101469.3-101487.6" + attribute \src "libresoc.v:101154.3-101172.6" wire $0\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:101564.3-101582.6" + attribute \src "libresoc.v:101249.3-101267.6" wire $0\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:101526.3-101544.6" + attribute \src "libresoc.v:101211.3-101229.6" wire $0\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:101450.3-101468.6" + attribute \src "libresoc.v:101135.3-101153.6" wire $0\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:101222.3-101240.6" + attribute \src "libresoc.v:100907.3-100925.6" wire width 3 $0\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:101241.3-101259.6" + attribute \src "libresoc.v:100926.3-100944.6" wire width 3 $0\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:101127.3-101145.6" + attribute \src "libresoc.v:100812.3-100830.6" wire width 3 $0\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:101146.3-101164.6" + attribute \src "libresoc.v:100831.3-100849.6" wire width 3 $0\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:101165.3-101183.6" + attribute \src "libresoc.v:100850.3-100868.6" wire width 3 $0\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:101203.3-101221.6" + attribute \src "libresoc.v:100888.3-100906.6" wire width 3 $0\dec31_dec_sub19_sv_out2[2:0] - attribute \src "libresoc.v:101184.3-101202.6" + attribute \src "libresoc.v:100869.3-100887.6" wire width 3 $0\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:101298.3-101316.6" + attribute \src "libresoc.v:100983.3-101001.6" wire width 2 $0\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:100722.7-100722.20" + attribute \src "libresoc.v:100407.7-100407.20" wire $0\initial[0:0] - attribute \src "libresoc.v:101583.3-101601.6" + attribute \src "libresoc.v:101268.3-101286.6" wire width 2 $1\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:101602.3-101620.6" + attribute \src "libresoc.v:101287.3-101305.6" wire width 2 $1\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:101355.3-101373.6" + attribute \src "libresoc.v:101040.3-101058.6" wire width 8 $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:101431.3-101449.6" + attribute \src "libresoc.v:101116.3-101134.6" wire $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:101089.3-101107.6" + attribute \src "libresoc.v:100774.3-100792.6" wire width 3 $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:101108.3-101126.6" + attribute \src "libresoc.v:100793.3-100811.6" wire width 3 $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:101336.3-101354.6" + attribute \src "libresoc.v:101021.3-101039.6" wire width 2 $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:101412.3-101430.6" + attribute \src "libresoc.v:101097.3-101115.6" wire $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:101488.3-101506.6" + attribute \src "libresoc.v:101173.3-101191.6" wire width 5 $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:101070.3-101088.6" + attribute \src "libresoc.v:100755.3-100773.6" wire width 14 $1\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:101621.3-101639.6" + attribute \src "libresoc.v:101306.3-101324.6" wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:101640.3-101658.6" + attribute \src "libresoc.v:101325.3-101343.6" wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:101659.3-101677.6" + attribute \src "libresoc.v:101344.3-101362.6" wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:101279.3-101297.6" + attribute \src "libresoc.v:100964.3-100982.6" wire width 7 $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:101374.3-101392.6" + attribute \src "libresoc.v:101059.3-101077.6" wire $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:101393.3-101411.6" + attribute \src "libresoc.v:101078.3-101096.6" wire $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:101507.3-101525.6" + attribute \src "libresoc.v:101192.3-101210.6" wire $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:101260.3-101278.6" + attribute \src "libresoc.v:100945.3-100963.6" wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:101545.3-101563.6" + attribute \src "libresoc.v:101230.3-101248.6" wire $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:101678.3-101696.6" + attribute \src "libresoc.v:101363.3-101381.6" wire width 3 $1\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:101317.3-101335.6" + attribute \src "libresoc.v:101002.3-101020.6" wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:101469.3-101487.6" + attribute \src "libresoc.v:101154.3-101172.6" wire $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:101564.3-101582.6" + attribute \src "libresoc.v:101249.3-101267.6" wire $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:101526.3-101544.6" + attribute \src "libresoc.v:101211.3-101229.6" wire $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:101450.3-101468.6" + attribute \src "libresoc.v:101135.3-101153.6" wire $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:101222.3-101240.6" + attribute \src "libresoc.v:100907.3-100925.6" wire width 3 $1\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:101241.3-101259.6" + attribute \src "libresoc.v:100926.3-100944.6" wire width 3 $1\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:101127.3-101145.6" + attribute \src "libresoc.v:100812.3-100830.6" wire width 3 $1\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:101146.3-101164.6" + attribute \src "libresoc.v:100831.3-100849.6" wire width 3 $1\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:101165.3-101183.6" + attribute \src "libresoc.v:100850.3-100868.6" wire width 3 $1\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:101203.3-101221.6" + attribute \src "libresoc.v:100888.3-100906.6" wire width 3 $1\dec31_dec_sub19_sv_out2[2:0] - attribute \src "libresoc.v:101184.3-101202.6" + attribute \src "libresoc.v:100869.3-100887.6" wire width 3 $1\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:101298.3-101316.6" + attribute \src "libresoc.v:100983.3-101001.6" wire width 2 $1\dec31_dec_sub19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -157474,28 +156996,28 @@ module \dec31_dec_sub19 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub19_upd - attribute \src "libresoc.v:100722.7-100722.15" + attribute \src "libresoc.v:100407.7-100407.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:100722.7-100722.20" - process $proc$libresoc.v:100722$4088 + attribute \src "libresoc.v:100407.7-100407.20" + process $proc$libresoc.v:100407$4072 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:101070.3-101088.6" - process $proc$libresoc.v:101070$4055 + attribute \src "libresoc.v:100755.3-100773.6" + process $proc$libresoc.v:100755$4039 assign { } { } assign { } { } assign $0\dec31_dec_sub19_function_unit[13:0] $1\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:101071.5-101071.29" + attribute \src "libresoc.v:100756.5-100756.29" switch \initial - attribute \src "libresoc.v:101071.9-101071.17" + attribute \src "libresoc.v:100756.9-100756.17" case 1'1 case end @@ -157523,14 +157045,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[13:0] end - attribute \src "libresoc.v:101089.3-101107.6" - process $proc$libresoc.v:101089$4056 + attribute \src "libresoc.v:100774.3-100792.6" + process $proc$libresoc.v:100774$4040 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:101090.5-101090.29" + attribute \src "libresoc.v:100775.5-100775.29" switch \initial - attribute \src "libresoc.v:101090.9-101090.17" + attribute \src "libresoc.v:100775.9-100775.17" case 1'1 case end @@ -157558,14 +157080,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] end - attribute \src "libresoc.v:101108.3-101126.6" - process $proc$libresoc.v:101108$4057 + attribute \src "libresoc.v:100793.3-100811.6" + process $proc$libresoc.v:100793$4041 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:101109.5-101109.29" + attribute \src "libresoc.v:100794.5-100794.29" switch \initial - attribute \src "libresoc.v:101109.9-101109.17" + attribute \src "libresoc.v:100794.9-100794.17" case 1'1 case end @@ -157593,14 +157115,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] end - attribute \src "libresoc.v:101127.3-101145.6" - process $proc$libresoc.v:101127$4058 + attribute \src "libresoc.v:100812.3-100830.6" + process $proc$libresoc.v:100812$4042 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:101128.5-101128.29" + attribute \src "libresoc.v:100813.5-100813.29" switch \initial - attribute \src "libresoc.v:101128.9-101128.17" + attribute \src "libresoc.v:100813.9-100813.17" case 1'1 case end @@ -157628,14 +157150,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0] end - attribute \src "libresoc.v:101146.3-101164.6" - process $proc$libresoc.v:101146$4059 + attribute \src "libresoc.v:100831.3-100849.6" + process $proc$libresoc.v:100831$4043 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:101147.5-101147.29" + attribute \src "libresoc.v:100832.5-100832.29" switch \initial - attribute \src "libresoc.v:101147.9-101147.17" + attribute \src "libresoc.v:100832.9-100832.17" case 1'1 case end @@ -157663,14 +157185,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0] end - attribute \src "libresoc.v:101165.3-101183.6" - process $proc$libresoc.v:101165$4060 + attribute \src "libresoc.v:100850.3-100868.6" + process $proc$libresoc.v:100850$4044 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:101166.5-101166.29" + attribute \src "libresoc.v:100851.5-100851.29" switch \initial - attribute \src "libresoc.v:101166.9-101166.17" + attribute \src "libresoc.v:100851.9-100851.17" case 1'1 case end @@ -157698,14 +157220,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0] end - attribute \src "libresoc.v:101184.3-101202.6" - process $proc$libresoc.v:101184$4061 + attribute \src "libresoc.v:100869.3-100887.6" + process $proc$libresoc.v:100869$4045 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:101185.5-101185.29" + attribute \src "libresoc.v:100870.5-100870.29" switch \initial - attribute \src "libresoc.v:101185.9-101185.17" + attribute \src "libresoc.v:100870.9-100870.17" case 1'1 case end @@ -157733,14 +157255,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0] end - attribute \src "libresoc.v:101203.3-101221.6" - process $proc$libresoc.v:101203$4062 + attribute \src "libresoc.v:100888.3-100906.6" + process $proc$libresoc.v:100888$4046 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_out2[2:0] $1\dec31_dec_sub19_sv_out2[2:0] - attribute \src "libresoc.v:101204.5-101204.29" + attribute \src "libresoc.v:100889.5-100889.29" switch \initial - attribute \src "libresoc.v:101204.9-101204.17" + attribute \src "libresoc.v:100889.9-100889.17" case 1'1 case end @@ -157768,14 +157290,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_out2 $0\dec31_dec_sub19_sv_out2[2:0] end - attribute \src "libresoc.v:101222.3-101240.6" - process $proc$libresoc.v:101222$4063 + attribute \src "libresoc.v:100907.3-100925.6" + process $proc$libresoc.v:100907$4047 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:101223.5-101223.29" + attribute \src "libresoc.v:100908.5-100908.29" switch \initial - attribute \src "libresoc.v:101223.9-101223.17" + attribute \src "libresoc.v:100908.9-100908.17" case 1'1 case end @@ -157803,14 +157325,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0] end - attribute \src "libresoc.v:101241.3-101259.6" - process $proc$libresoc.v:101241$4064 + attribute \src "libresoc.v:100926.3-100944.6" + process $proc$libresoc.v:100926$4048 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_out[2:0] $1\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:101242.5-101242.29" + attribute \src "libresoc.v:100927.5-100927.29" switch \initial - attribute \src "libresoc.v:101242.9-101242.17" + attribute \src "libresoc.v:100927.9-100927.17" case 1'1 case end @@ -157838,14 +157360,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_cr_out $0\dec31_dec_sub19_sv_cr_out[2:0] end - attribute \src "libresoc.v:101260.3-101278.6" - process $proc$libresoc.v:101260$4065 + attribute \src "libresoc.v:100945.3-100963.6" + process $proc$libresoc.v:100945$4049 assign { } { } assign { } { } assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:101261.5-101261.29" + attribute \src "libresoc.v:100946.5-100946.29" switch \initial - attribute \src "libresoc.v:101261.9-101261.17" + attribute \src "libresoc.v:100946.9-100946.17" case 1'1 case end @@ -157873,14 +157395,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] end - attribute \src "libresoc.v:101279.3-101297.6" - process $proc$libresoc.v:101279$4066 + attribute \src "libresoc.v:100964.3-100982.6" + process $proc$libresoc.v:100964$4050 assign { } { } assign { } { } assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:101280.5-101280.29" + attribute \src "libresoc.v:100965.5-100965.29" switch \initial - attribute \src "libresoc.v:101280.9-101280.17" + attribute \src "libresoc.v:100965.9-100965.17" case 1'1 case end @@ -157908,14 +157430,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] end - attribute \src "libresoc.v:101298.3-101316.6" - process $proc$libresoc.v:101298$4067 + attribute \src "libresoc.v:100983.3-101001.6" + process $proc$libresoc.v:100983$4051 assign { } { } assign { } { } assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:101299.5-101299.29" + attribute \src "libresoc.v:100984.5-100984.29" switch \initial - attribute \src "libresoc.v:101299.9-101299.17" + attribute \src "libresoc.v:100984.9-100984.17" case 1'1 case end @@ -157943,14 +157465,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] end - attribute \src "libresoc.v:101317.3-101335.6" - process $proc$libresoc.v:101317$4068 + attribute \src "libresoc.v:101002.3-101020.6" + process $proc$libresoc.v:101002$4052 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:101318.5-101318.29" + attribute \src "libresoc.v:101003.5-101003.29" switch \initial - attribute \src "libresoc.v:101318.9-101318.17" + attribute \src "libresoc.v:101003.9-101003.17" case 1'1 case end @@ -157978,14 +157500,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] end - attribute \src "libresoc.v:101336.3-101354.6" - process $proc$libresoc.v:101336$4069 + attribute \src "libresoc.v:101021.3-101039.6" + process $proc$libresoc.v:101021$4053 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:101337.5-101337.29" + attribute \src "libresoc.v:101022.5-101022.29" switch \initial - attribute \src "libresoc.v:101337.9-101337.17" + attribute \src "libresoc.v:101022.9-101022.17" case 1'1 case end @@ -158013,14 +157535,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] end - attribute \src "libresoc.v:101355.3-101373.6" - process $proc$libresoc.v:101355$4070 + attribute \src "libresoc.v:101040.3-101058.6" + process $proc$libresoc.v:101040$4054 assign { } { } assign { } { } assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:101356.5-101356.29" + attribute \src "libresoc.v:101041.5-101041.29" switch \initial - attribute \src "libresoc.v:101356.9-101356.17" + attribute \src "libresoc.v:101041.9-101041.17" case 1'1 case end @@ -158048,14 +157570,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] end - attribute \src "libresoc.v:101374.3-101392.6" - process $proc$libresoc.v:101374$4071 + attribute \src "libresoc.v:101059.3-101077.6" + process $proc$libresoc.v:101059$4055 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:101375.5-101375.29" + attribute \src "libresoc.v:101060.5-101060.29" switch \initial - attribute \src "libresoc.v:101375.9-101375.17" + attribute \src "libresoc.v:101060.9-101060.17" case 1'1 case end @@ -158083,14 +157605,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] end - attribute \src "libresoc.v:101393.3-101411.6" - process $proc$libresoc.v:101393$4072 + attribute \src "libresoc.v:101078.3-101096.6" + process $proc$libresoc.v:101078$4056 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:101394.5-101394.29" + attribute \src "libresoc.v:101079.5-101079.29" switch \initial - attribute \src "libresoc.v:101394.9-101394.17" + attribute \src "libresoc.v:101079.9-101079.17" case 1'1 case end @@ -158118,14 +157640,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] end - attribute \src "libresoc.v:101412.3-101430.6" - process $proc$libresoc.v:101412$4073 + attribute \src "libresoc.v:101097.3-101115.6" + process $proc$libresoc.v:101097$4057 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:101413.5-101413.29" + attribute \src "libresoc.v:101098.5-101098.29" switch \initial - attribute \src "libresoc.v:101413.9-101413.17" + attribute \src "libresoc.v:101098.9-101098.17" case 1'1 case end @@ -158153,14 +157675,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] end - attribute \src "libresoc.v:101431.3-101449.6" - process $proc$libresoc.v:101431$4074 + attribute \src "libresoc.v:101116.3-101134.6" + process $proc$libresoc.v:101116$4058 assign { } { } assign { } { } assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:101432.5-101432.29" + attribute \src "libresoc.v:101117.5-101117.29" switch \initial - attribute \src "libresoc.v:101432.9-101432.17" + attribute \src "libresoc.v:101117.9-101117.17" case 1'1 case end @@ -158188,14 +157710,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] end - attribute \src "libresoc.v:101450.3-101468.6" - process $proc$libresoc.v:101450$4075 + attribute \src "libresoc.v:101135.3-101153.6" + process $proc$libresoc.v:101135$4059 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:101451.5-101451.29" + attribute \src "libresoc.v:101136.5-101136.29" switch \initial - attribute \src "libresoc.v:101451.9-101451.17" + attribute \src "libresoc.v:101136.9-101136.17" case 1'1 case end @@ -158223,14 +157745,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] end - attribute \src "libresoc.v:101469.3-101487.6" - process $proc$libresoc.v:101469$4076 + attribute \src "libresoc.v:101154.3-101172.6" + process $proc$libresoc.v:101154$4060 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:101470.5-101470.29" + attribute \src "libresoc.v:101155.5-101155.29" switch \initial - attribute \src "libresoc.v:101470.9-101470.17" + attribute \src "libresoc.v:101155.9-101155.17" case 1'1 case end @@ -158258,14 +157780,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] end - attribute \src "libresoc.v:101488.3-101506.6" - process $proc$libresoc.v:101488$4077 + attribute \src "libresoc.v:101173.3-101191.6" + process $proc$libresoc.v:101173$4061 assign { } { } assign { } { } assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:101489.5-101489.29" + attribute \src "libresoc.v:101174.5-101174.29" switch \initial - attribute \src "libresoc.v:101489.9-101489.17" + attribute \src "libresoc.v:101174.9-101174.17" case 1'1 case end @@ -158293,14 +157815,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] end - attribute \src "libresoc.v:101507.3-101525.6" - process $proc$libresoc.v:101507$4078 + attribute \src "libresoc.v:101192.3-101210.6" + process $proc$libresoc.v:101192$4062 assign { } { } assign { } { } assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:101508.5-101508.29" + attribute \src "libresoc.v:101193.5-101193.29" switch \initial - attribute \src "libresoc.v:101508.9-101508.17" + attribute \src "libresoc.v:101193.9-101193.17" case 1'1 case end @@ -158328,14 +157850,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] end - attribute \src "libresoc.v:101526.3-101544.6" - process $proc$libresoc.v:101526$4079 + attribute \src "libresoc.v:101211.3-101229.6" + process $proc$libresoc.v:101211$4063 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:101527.5-101527.29" + attribute \src "libresoc.v:101212.5-101212.29" switch \initial - attribute \src "libresoc.v:101527.9-101527.17" + attribute \src "libresoc.v:101212.9-101212.17" case 1'1 case end @@ -158363,14 +157885,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] end - attribute \src "libresoc.v:101545.3-101563.6" - process $proc$libresoc.v:101545$4080 + attribute \src "libresoc.v:101230.3-101248.6" + process $proc$libresoc.v:101230$4064 assign { } { } assign { } { } assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:101546.5-101546.29" + attribute \src "libresoc.v:101231.5-101231.29" switch \initial - attribute \src "libresoc.v:101546.9-101546.17" + attribute \src "libresoc.v:101231.9-101231.17" case 1'1 case end @@ -158398,14 +157920,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] end - attribute \src "libresoc.v:101564.3-101582.6" - process $proc$libresoc.v:101564$4081 + attribute \src "libresoc.v:101249.3-101267.6" + process $proc$libresoc.v:101249$4065 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:101565.5-101565.29" + attribute \src "libresoc.v:101250.5-101250.29" switch \initial - attribute \src "libresoc.v:101565.9-101565.17" + attribute \src "libresoc.v:101250.9-101250.17" case 1'1 case end @@ -158433,14 +157955,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] end - attribute \src "libresoc.v:101583.3-101601.6" - process $proc$libresoc.v:101583$4082 + attribute \src "libresoc.v:101268.3-101286.6" + process $proc$libresoc.v:101268$4066 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Etype[1:0] $1\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:101584.5-101584.29" + attribute \src "libresoc.v:101269.5-101269.29" switch \initial - attribute \src "libresoc.v:101584.9-101584.17" + attribute \src "libresoc.v:101269.9-101269.17" case 1'1 case end @@ -158468,14 +157990,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_SV_Etype $0\dec31_dec_sub19_SV_Etype[1:0] end - attribute \src "libresoc.v:101602.3-101620.6" - process $proc$libresoc.v:101602$4083 + attribute \src "libresoc.v:101287.3-101305.6" + process $proc$libresoc.v:101287$4067 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Ptype[1:0] $1\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:101603.5-101603.29" + attribute \src "libresoc.v:101288.5-101288.29" switch \initial - attribute \src "libresoc.v:101603.9-101603.17" + attribute \src "libresoc.v:101288.9-101288.17" case 1'1 case end @@ -158503,14 +158025,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_SV_Ptype $0\dec31_dec_sub19_SV_Ptype[1:0] end - attribute \src "libresoc.v:101621.3-101639.6" - process $proc$libresoc.v:101621$4084 + attribute \src "libresoc.v:101306.3-101324.6" + process $proc$libresoc.v:101306$4068 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:101622.5-101622.29" + attribute \src "libresoc.v:101307.5-101307.29" switch \initial - attribute \src "libresoc.v:101622.9-101622.17" + attribute \src "libresoc.v:101307.9-101307.17" case 1'1 case end @@ -158538,14 +158060,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] end - attribute \src "libresoc.v:101640.3-101658.6" - process $proc$libresoc.v:101640$4085 + attribute \src "libresoc.v:101325.3-101343.6" + process $proc$libresoc.v:101325$4069 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:101641.5-101641.29" + attribute \src "libresoc.v:101326.5-101326.29" switch \initial - attribute \src "libresoc.v:101641.9-101641.17" + attribute \src "libresoc.v:101326.9-101326.17" case 1'1 case end @@ -158573,14 +158095,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] end - attribute \src "libresoc.v:101659.3-101677.6" - process $proc$libresoc.v:101659$4086 + attribute \src "libresoc.v:101344.3-101362.6" + process $proc$libresoc.v:101344$4070 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:101660.5-101660.29" + attribute \src "libresoc.v:101345.5-101345.29" switch \initial - attribute \src "libresoc.v:101660.9-101660.17" + attribute \src "libresoc.v:101345.9-101345.17" case 1'1 case end @@ -158608,14 +158130,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] end - attribute \src "libresoc.v:101678.3-101696.6" - process $proc$libresoc.v:101678$4087 + attribute \src "libresoc.v:101363.3-101381.6" + process $proc$libresoc.v:101363$4071 assign { } { } assign { } { } assign $0\dec31_dec_sub19_out_sel[2:0] $1\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:101679.5-101679.29" + attribute \src "libresoc.v:101364.5-101364.29" switch \initial - attribute \src "libresoc.v:101679.9-101679.17" + attribute \src "libresoc.v:101364.9-101364.17" case 1'1 case end @@ -158645,144 +158167,144 @@ module \dec31_dec_sub19 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:101702.1-102877.10" +attribute \src "libresoc.v:101387.1-102562.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" attribute \generator "nMigen" module \dec31_dec_sub20 - attribute \src "libresoc.v:102726.3-102750.6" + attribute \src "libresoc.v:102411.3-102435.6" wire width 2 $0\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:102751.3-102775.6" + attribute \src "libresoc.v:102436.3-102460.6" wire width 2 $0\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:102426.3-102450.6" + attribute \src "libresoc.v:102111.3-102135.6" wire width 8 $0\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:102526.3-102550.6" + attribute \src "libresoc.v:102211.3-102235.6" wire $0\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:102076.3-102100.6" + attribute \src "libresoc.v:101761.3-101785.6" wire width 3 $0\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:102101.3-102125.6" + attribute \src "libresoc.v:101786.3-101810.6" wire width 3 $0\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:102401.3-102425.6" + attribute \src "libresoc.v:102086.3-102110.6" wire width 2 $0\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:102501.3-102525.6" + attribute \src "libresoc.v:102186.3-102210.6" wire $0\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:102601.3-102625.6" + attribute \src "libresoc.v:102286.3-102310.6" wire width 5 $0\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:102051.3-102075.6" + attribute \src "libresoc.v:101736.3-101760.6" wire width 14 $0\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:102776.3-102800.6" + attribute \src "libresoc.v:102461.3-102485.6" wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:102801.3-102825.6" + attribute \src "libresoc.v:102486.3-102510.6" wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:102826.3-102850.6" + attribute \src "libresoc.v:102511.3-102535.6" wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:102326.3-102350.6" + attribute \src "libresoc.v:102011.3-102035.6" wire width 7 $0\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:102451.3-102475.6" + attribute \src "libresoc.v:102136.3-102160.6" wire $0\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:102476.3-102500.6" + attribute \src "libresoc.v:102161.3-102185.6" wire $0\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:102626.3-102650.6" + attribute \src "libresoc.v:102311.3-102335.6" wire $0\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:102301.3-102325.6" + attribute \src "libresoc.v:101986.3-102010.6" wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:102676.3-102700.6" + attribute \src "libresoc.v:102361.3-102385.6" wire $0\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:102851.3-102875.6" + attribute \src "libresoc.v:102536.3-102560.6" wire width 3 $0\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:102376.3-102400.6" + attribute \src "libresoc.v:102061.3-102085.6" wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:102576.3-102600.6" + attribute \src "libresoc.v:102261.3-102285.6" wire $0\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:102701.3-102725.6" + attribute \src "libresoc.v:102386.3-102410.6" wire $0\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:102651.3-102675.6" + attribute \src "libresoc.v:102336.3-102360.6" wire $0\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:102551.3-102575.6" + attribute \src "libresoc.v:102236.3-102260.6" wire $0\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:102251.3-102275.6" + attribute \src "libresoc.v:101936.3-101960.6" wire width 3 $0\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:102276.3-102300.6" + attribute \src "libresoc.v:101961.3-101985.6" wire width 3 $0\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:102126.3-102150.6" + attribute \src "libresoc.v:101811.3-101835.6" wire width 3 $0\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:102151.3-102175.6" + attribute \src "libresoc.v:101836.3-101860.6" wire width 3 $0\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:102176.3-102200.6" + attribute \src "libresoc.v:101861.3-101885.6" wire width 3 $0\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:102226.3-102250.6" + attribute \src "libresoc.v:101911.3-101935.6" wire width 3 $0\dec31_dec_sub20_sv_out2[2:0] - attribute \src "libresoc.v:102201.3-102225.6" + attribute \src "libresoc.v:101886.3-101910.6" wire width 3 $0\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:102351.3-102375.6" + attribute \src "libresoc.v:102036.3-102060.6" wire width 2 $0\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:101703.7-101703.20" + attribute \src "libresoc.v:101388.7-101388.20" wire $0\initial[0:0] - attribute \src "libresoc.v:102726.3-102750.6" + attribute \src "libresoc.v:102411.3-102435.6" wire width 2 $1\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:102751.3-102775.6" + attribute \src "libresoc.v:102436.3-102460.6" wire width 2 $1\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:102426.3-102450.6" + attribute \src "libresoc.v:102111.3-102135.6" wire width 8 $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:102526.3-102550.6" + attribute \src "libresoc.v:102211.3-102235.6" wire $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:102076.3-102100.6" + attribute \src "libresoc.v:101761.3-101785.6" wire width 3 $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:102101.3-102125.6" + attribute \src "libresoc.v:101786.3-101810.6" wire width 3 $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:102401.3-102425.6" + attribute \src "libresoc.v:102086.3-102110.6" wire width 2 $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:102501.3-102525.6" + attribute \src "libresoc.v:102186.3-102210.6" wire $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:102601.3-102625.6" + attribute \src "libresoc.v:102286.3-102310.6" wire width 5 $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:102051.3-102075.6" + attribute \src "libresoc.v:101736.3-101760.6" wire width 14 $1\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:102776.3-102800.6" + attribute \src "libresoc.v:102461.3-102485.6" wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:102801.3-102825.6" + attribute \src "libresoc.v:102486.3-102510.6" wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:102826.3-102850.6" + attribute \src "libresoc.v:102511.3-102535.6" wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:102326.3-102350.6" + attribute \src "libresoc.v:102011.3-102035.6" wire width 7 $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:102451.3-102475.6" + attribute \src "libresoc.v:102136.3-102160.6" wire $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:102476.3-102500.6" + attribute \src "libresoc.v:102161.3-102185.6" wire $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:102626.3-102650.6" + attribute \src "libresoc.v:102311.3-102335.6" wire $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:102301.3-102325.6" + attribute \src "libresoc.v:101986.3-102010.6" wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:102676.3-102700.6" + attribute \src "libresoc.v:102361.3-102385.6" wire $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:102851.3-102875.6" + attribute \src "libresoc.v:102536.3-102560.6" wire width 3 $1\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:102376.3-102400.6" + attribute \src "libresoc.v:102061.3-102085.6" wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:102576.3-102600.6" + attribute \src "libresoc.v:102261.3-102285.6" wire $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:102701.3-102725.6" + attribute \src "libresoc.v:102386.3-102410.6" wire $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:102651.3-102675.6" + attribute \src "libresoc.v:102336.3-102360.6" wire $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:102551.3-102575.6" + attribute \src "libresoc.v:102236.3-102260.6" wire $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:102251.3-102275.6" + attribute \src "libresoc.v:101936.3-101960.6" wire width 3 $1\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:102276.3-102300.6" + attribute \src "libresoc.v:101961.3-101985.6" wire width 3 $1\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:102126.3-102150.6" + attribute \src "libresoc.v:101811.3-101835.6" wire width 3 $1\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:102151.3-102175.6" + attribute \src "libresoc.v:101836.3-101860.6" wire width 3 $1\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:102176.3-102200.6" + attribute \src "libresoc.v:101861.3-101885.6" wire width 3 $1\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:102226.3-102250.6" + attribute \src "libresoc.v:101911.3-101935.6" wire width 3 $1\dec31_dec_sub20_sv_out2[2:0] - attribute \src "libresoc.v:102201.3-102225.6" + attribute \src "libresoc.v:101886.3-101910.6" wire width 3 $1\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:102351.3-102375.6" + attribute \src "libresoc.v:102036.3-102060.6" wire width 2 $1\dec31_dec_sub20_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -159094,28 +158616,28 @@ module \dec31_dec_sub20 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub20_upd - attribute \src "libresoc.v:101703.7-101703.15" + attribute \src "libresoc.v:101388.7-101388.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:101703.7-101703.20" - process $proc$libresoc.v:101703$4122 + attribute \src "libresoc.v:101388.7-101388.20" + process $proc$libresoc.v:101388$4106 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:102051.3-102075.6" - process $proc$libresoc.v:102051$4089 + attribute \src "libresoc.v:101736.3-101760.6" + process $proc$libresoc.v:101736$4073 assign { } { } assign { } { } assign $0\dec31_dec_sub20_function_unit[13:0] $1\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:102052.5-102052.29" + attribute \src "libresoc.v:101737.5-101737.29" switch \initial - attribute \src "libresoc.v:102052.9-102052.17" + attribute \src "libresoc.v:101737.9-101737.17" case 1'1 case end @@ -159151,14 +158673,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[13:0] end - attribute \src "libresoc.v:102076.3-102100.6" - process $proc$libresoc.v:102076$4090 + attribute \src "libresoc.v:101761.3-101785.6" + process $proc$libresoc.v:101761$4074 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:102077.5-102077.29" + attribute \src "libresoc.v:101762.5-101762.29" switch \initial - attribute \src "libresoc.v:102077.9-102077.17" + attribute \src "libresoc.v:101762.9-101762.17" case 1'1 case end @@ -159194,14 +158716,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] end - attribute \src "libresoc.v:102101.3-102125.6" - process $proc$libresoc.v:102101$4091 + attribute \src "libresoc.v:101786.3-101810.6" + process $proc$libresoc.v:101786$4075 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:102102.5-102102.29" + attribute \src "libresoc.v:101787.5-101787.29" switch \initial - attribute \src "libresoc.v:102102.9-102102.17" + attribute \src "libresoc.v:101787.9-101787.17" case 1'1 case end @@ -159237,14 +158759,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] end - attribute \src "libresoc.v:102126.3-102150.6" - process $proc$libresoc.v:102126$4092 + attribute \src "libresoc.v:101811.3-101835.6" + process $proc$libresoc.v:101811$4076 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in1[2:0] $1\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:102127.5-102127.29" + attribute \src "libresoc.v:101812.5-101812.29" switch \initial - attribute \src "libresoc.v:102127.9-102127.17" + attribute \src "libresoc.v:101812.9-101812.17" case 1'1 case end @@ -159280,14 +158802,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in1 $0\dec31_dec_sub20_sv_in1[2:0] end - attribute \src "libresoc.v:102151.3-102175.6" - process $proc$libresoc.v:102151$4093 + attribute \src "libresoc.v:101836.3-101860.6" + process $proc$libresoc.v:101836$4077 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in2[2:0] $1\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:102152.5-102152.29" + attribute \src "libresoc.v:101837.5-101837.29" switch \initial - attribute \src "libresoc.v:102152.9-102152.17" + attribute \src "libresoc.v:101837.9-101837.17" case 1'1 case end @@ -159323,14 +158845,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in2 $0\dec31_dec_sub20_sv_in2[2:0] end - attribute \src "libresoc.v:102176.3-102200.6" - process $proc$libresoc.v:102176$4094 + attribute \src "libresoc.v:101861.3-101885.6" + process $proc$libresoc.v:101861$4078 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in3[2:0] $1\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:102177.5-102177.29" + attribute \src "libresoc.v:101862.5-101862.29" switch \initial - attribute \src "libresoc.v:102177.9-102177.17" + attribute \src "libresoc.v:101862.9-101862.17" case 1'1 case end @@ -159366,14 +158888,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in3 $0\dec31_dec_sub20_sv_in3[2:0] end - attribute \src "libresoc.v:102201.3-102225.6" - process $proc$libresoc.v:102201$4095 + attribute \src "libresoc.v:101886.3-101910.6" + process $proc$libresoc.v:101886$4079 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_out[2:0] $1\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:102202.5-102202.29" + attribute \src "libresoc.v:101887.5-101887.29" switch \initial - attribute \src "libresoc.v:102202.9-102202.17" + attribute \src "libresoc.v:101887.9-101887.17" case 1'1 case end @@ -159409,14 +158931,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_out $0\dec31_dec_sub20_sv_out[2:0] end - attribute \src "libresoc.v:102226.3-102250.6" - process $proc$libresoc.v:102226$4096 + attribute \src "libresoc.v:101911.3-101935.6" + process $proc$libresoc.v:101911$4080 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_out2[2:0] $1\dec31_dec_sub20_sv_out2[2:0] - attribute \src "libresoc.v:102227.5-102227.29" + attribute \src "libresoc.v:101912.5-101912.29" switch \initial - attribute \src "libresoc.v:102227.9-102227.17" + attribute \src "libresoc.v:101912.9-101912.17" case 1'1 case end @@ -159452,14 +158974,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_out2 $0\dec31_dec_sub20_sv_out2[2:0] end - attribute \src "libresoc.v:102251.3-102275.6" - process $proc$libresoc.v:102251$4097 + attribute \src "libresoc.v:101936.3-101960.6" + process $proc$libresoc.v:101936$4081 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_in[2:0] $1\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:102252.5-102252.29" + attribute \src "libresoc.v:101937.5-101937.29" switch \initial - attribute \src "libresoc.v:102252.9-102252.17" + attribute \src "libresoc.v:101937.9-101937.17" case 1'1 case end @@ -159495,14 +159017,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_cr_in $0\dec31_dec_sub20_sv_cr_in[2:0] end - attribute \src "libresoc.v:102276.3-102300.6" - process $proc$libresoc.v:102276$4098 + attribute \src "libresoc.v:101961.3-101985.6" + process $proc$libresoc.v:101961$4082 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_out[2:0] $1\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:102277.5-102277.29" + attribute \src "libresoc.v:101962.5-101962.29" switch \initial - attribute \src "libresoc.v:102277.9-102277.17" + attribute \src "libresoc.v:101962.9-101962.17" case 1'1 case end @@ -159538,14 +159060,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_cr_out $0\dec31_dec_sub20_sv_cr_out[2:0] end - attribute \src "libresoc.v:102301.3-102325.6" - process $proc$libresoc.v:102301$4099 + attribute \src "libresoc.v:101986.3-102010.6" + process $proc$libresoc.v:101986$4083 assign { } { } assign { } { } assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:102302.5-102302.29" + attribute \src "libresoc.v:101987.5-101987.29" switch \initial - attribute \src "libresoc.v:102302.9-102302.17" + attribute \src "libresoc.v:101987.9-101987.17" case 1'1 case end @@ -159581,14 +159103,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] end - attribute \src "libresoc.v:102326.3-102350.6" - process $proc$libresoc.v:102326$4100 + attribute \src "libresoc.v:102011.3-102035.6" + process $proc$libresoc.v:102011$4084 assign { } { } assign { } { } assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:102327.5-102327.29" + attribute \src "libresoc.v:102012.5-102012.29" switch \initial - attribute \src "libresoc.v:102327.9-102327.17" + attribute \src "libresoc.v:102012.9-102012.17" case 1'1 case end @@ -159624,14 +159146,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] end - attribute \src "libresoc.v:102351.3-102375.6" - process $proc$libresoc.v:102351$4101 + attribute \src "libresoc.v:102036.3-102060.6" + process $proc$libresoc.v:102036$4085 assign { } { } assign { } { } assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:102352.5-102352.29" + attribute \src "libresoc.v:102037.5-102037.29" switch \initial - attribute \src "libresoc.v:102352.9-102352.17" + attribute \src "libresoc.v:102037.9-102037.17" case 1'1 case end @@ -159667,14 +159189,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] end - attribute \src "libresoc.v:102376.3-102400.6" - process $proc$libresoc.v:102376$4102 + attribute \src "libresoc.v:102061.3-102085.6" + process $proc$libresoc.v:102061$4086 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:102377.5-102377.29" + attribute \src "libresoc.v:102062.5-102062.29" switch \initial - attribute \src "libresoc.v:102377.9-102377.17" + attribute \src "libresoc.v:102062.9-102062.17" case 1'1 case end @@ -159710,14 +159232,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] end - attribute \src "libresoc.v:102401.3-102425.6" - process $proc$libresoc.v:102401$4103 + attribute \src "libresoc.v:102086.3-102110.6" + process $proc$libresoc.v:102086$4087 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:102402.5-102402.29" + attribute \src "libresoc.v:102087.5-102087.29" switch \initial - attribute \src "libresoc.v:102402.9-102402.17" + attribute \src "libresoc.v:102087.9-102087.17" case 1'1 case end @@ -159753,14 +159275,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] end - attribute \src "libresoc.v:102426.3-102450.6" - process $proc$libresoc.v:102426$4104 + attribute \src "libresoc.v:102111.3-102135.6" + process $proc$libresoc.v:102111$4088 assign { } { } assign { } { } assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:102427.5-102427.29" + attribute \src "libresoc.v:102112.5-102112.29" switch \initial - attribute \src "libresoc.v:102427.9-102427.17" + attribute \src "libresoc.v:102112.9-102112.17" case 1'1 case end @@ -159796,14 +159318,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] end - attribute \src "libresoc.v:102451.3-102475.6" - process $proc$libresoc.v:102451$4105 + attribute \src "libresoc.v:102136.3-102160.6" + process $proc$libresoc.v:102136$4089 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:102452.5-102452.29" + attribute \src "libresoc.v:102137.5-102137.29" switch \initial - attribute \src "libresoc.v:102452.9-102452.17" + attribute \src "libresoc.v:102137.9-102137.17" case 1'1 case end @@ -159839,14 +159361,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] end - attribute \src "libresoc.v:102476.3-102500.6" - process $proc$libresoc.v:102476$4106 + attribute \src "libresoc.v:102161.3-102185.6" + process $proc$libresoc.v:102161$4090 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:102477.5-102477.29" + attribute \src "libresoc.v:102162.5-102162.29" switch \initial - attribute \src "libresoc.v:102477.9-102477.17" + attribute \src "libresoc.v:102162.9-102162.17" case 1'1 case end @@ -159882,14 +159404,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] end - attribute \src "libresoc.v:102501.3-102525.6" - process $proc$libresoc.v:102501$4107 + attribute \src "libresoc.v:102186.3-102210.6" + process $proc$libresoc.v:102186$4091 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:102502.5-102502.29" + attribute \src "libresoc.v:102187.5-102187.29" switch \initial - attribute \src "libresoc.v:102502.9-102502.17" + attribute \src "libresoc.v:102187.9-102187.17" case 1'1 case end @@ -159925,14 +159447,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] end - attribute \src "libresoc.v:102526.3-102550.6" - process $proc$libresoc.v:102526$4108 + attribute \src "libresoc.v:102211.3-102235.6" + process $proc$libresoc.v:102211$4092 assign { } { } assign { } { } assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:102527.5-102527.29" + attribute \src "libresoc.v:102212.5-102212.29" switch \initial - attribute \src "libresoc.v:102527.9-102527.17" + attribute \src "libresoc.v:102212.9-102212.17" case 1'1 case end @@ -159968,14 +159490,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] end - attribute \src "libresoc.v:102551.3-102575.6" - process $proc$libresoc.v:102551$4109 + attribute \src "libresoc.v:102236.3-102260.6" + process $proc$libresoc.v:102236$4093 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:102552.5-102552.29" + attribute \src "libresoc.v:102237.5-102237.29" switch \initial - attribute \src "libresoc.v:102552.9-102552.17" + attribute \src "libresoc.v:102237.9-102237.17" case 1'1 case end @@ -160011,14 +159533,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] end - attribute \src "libresoc.v:102576.3-102600.6" - process $proc$libresoc.v:102576$4110 + attribute \src "libresoc.v:102261.3-102285.6" + process $proc$libresoc.v:102261$4094 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:102577.5-102577.29" + attribute \src "libresoc.v:102262.5-102262.29" switch \initial - attribute \src "libresoc.v:102577.9-102577.17" + attribute \src "libresoc.v:102262.9-102262.17" case 1'1 case end @@ -160054,14 +159576,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] end - attribute \src "libresoc.v:102601.3-102625.6" - process $proc$libresoc.v:102601$4111 + attribute \src "libresoc.v:102286.3-102310.6" + process $proc$libresoc.v:102286$4095 assign { } { } assign { } { } assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:102602.5-102602.29" + attribute \src "libresoc.v:102287.5-102287.29" switch \initial - attribute \src "libresoc.v:102602.9-102602.17" + attribute \src "libresoc.v:102287.9-102287.17" case 1'1 case end @@ -160097,14 +159619,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] end - attribute \src "libresoc.v:102626.3-102650.6" - process $proc$libresoc.v:102626$4112 + attribute \src "libresoc.v:102311.3-102335.6" + process $proc$libresoc.v:102311$4096 assign { } { } assign { } { } assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:102627.5-102627.29" + attribute \src "libresoc.v:102312.5-102312.29" switch \initial - attribute \src "libresoc.v:102627.9-102627.17" + attribute \src "libresoc.v:102312.9-102312.17" case 1'1 case end @@ -160140,14 +159662,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] end - attribute \src "libresoc.v:102651.3-102675.6" - process $proc$libresoc.v:102651$4113 + attribute \src "libresoc.v:102336.3-102360.6" + process $proc$libresoc.v:102336$4097 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:102652.5-102652.29" + attribute \src "libresoc.v:102337.5-102337.29" switch \initial - attribute \src "libresoc.v:102652.9-102652.17" + attribute \src "libresoc.v:102337.9-102337.17" case 1'1 case end @@ -160183,14 +159705,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] end - attribute \src "libresoc.v:102676.3-102700.6" - process $proc$libresoc.v:102676$4114 + attribute \src "libresoc.v:102361.3-102385.6" + process $proc$libresoc.v:102361$4098 assign { } { } assign { } { } assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:102677.5-102677.29" + attribute \src "libresoc.v:102362.5-102362.29" switch \initial - attribute \src "libresoc.v:102677.9-102677.17" + attribute \src "libresoc.v:102362.9-102362.17" case 1'1 case end @@ -160226,14 +159748,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] end - attribute \src "libresoc.v:102701.3-102725.6" - process $proc$libresoc.v:102701$4115 + attribute \src "libresoc.v:102386.3-102410.6" + process $proc$libresoc.v:102386$4099 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:102702.5-102702.29" + attribute \src "libresoc.v:102387.5-102387.29" switch \initial - attribute \src "libresoc.v:102702.9-102702.17" + attribute \src "libresoc.v:102387.9-102387.17" case 1'1 case end @@ -160269,14 +159791,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] end - attribute \src "libresoc.v:102726.3-102750.6" - process $proc$libresoc.v:102726$4116 + attribute \src "libresoc.v:102411.3-102435.6" + process $proc$libresoc.v:102411$4100 assign { } { } assign { } { } assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:102727.5-102727.29" + attribute \src "libresoc.v:102412.5-102412.29" switch \initial - attribute \src "libresoc.v:102727.9-102727.17" + attribute \src "libresoc.v:102412.9-102412.17" case 1'1 case end @@ -160312,14 +159834,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0] end - attribute \src "libresoc.v:102751.3-102775.6" - process $proc$libresoc.v:102751$4117 + attribute \src "libresoc.v:102436.3-102460.6" + process $proc$libresoc.v:102436$4101 assign { } { } assign { } { } assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:102752.5-102752.29" + attribute \src "libresoc.v:102437.5-102437.29" switch \initial - attribute \src "libresoc.v:102752.9-102752.17" + attribute \src "libresoc.v:102437.9-102437.17" case 1'1 case end @@ -160355,14 +159877,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0] end - attribute \src "libresoc.v:102776.3-102800.6" - process $proc$libresoc.v:102776$4118 + attribute \src "libresoc.v:102461.3-102485.6" + process $proc$libresoc.v:102461$4102 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:102777.5-102777.29" + attribute \src "libresoc.v:102462.5-102462.29" switch \initial - attribute \src "libresoc.v:102777.9-102777.17" + attribute \src "libresoc.v:102462.9-102462.17" case 1'1 case end @@ -160398,14 +159920,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] end - attribute \src "libresoc.v:102801.3-102825.6" - process $proc$libresoc.v:102801$4119 + attribute \src "libresoc.v:102486.3-102510.6" + process $proc$libresoc.v:102486$4103 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:102802.5-102802.29" + attribute \src "libresoc.v:102487.5-102487.29" switch \initial - attribute \src "libresoc.v:102802.9-102802.17" + attribute \src "libresoc.v:102487.9-102487.17" case 1'1 case end @@ -160441,14 +159963,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] end - attribute \src "libresoc.v:102826.3-102850.6" - process $proc$libresoc.v:102826$4120 + attribute \src "libresoc.v:102511.3-102535.6" + process $proc$libresoc.v:102511$4104 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:102827.5-102827.29" + attribute \src "libresoc.v:102512.5-102512.29" switch \initial - attribute \src "libresoc.v:102827.9-102827.17" + attribute \src "libresoc.v:102512.9-102512.17" case 1'1 case end @@ -160484,14 +160006,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] end - attribute \src "libresoc.v:102851.3-102875.6" - process $proc$libresoc.v:102851$4121 + attribute \src "libresoc.v:102536.3-102560.6" + process $proc$libresoc.v:102536$4105 assign { } { } assign { } { } assign $0\dec31_dec_sub20_out_sel[2:0] $1\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:102852.5-102852.29" + attribute \src "libresoc.v:102537.5-102537.29" switch \initial - attribute \src "libresoc.v:102852.9-102852.17" + attribute \src "libresoc.v:102537.9-102537.17" case 1'1 case end @@ -160529,144 +160051,144 @@ module \dec31_dec_sub20 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:102881.1-104830.10" +attribute \src "libresoc.v:102566.1-104527.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" attribute \generator "nMigen" module \dec31_dec_sub21 - attribute \src "libresoc.v:104535.3-104583.6" + attribute \src "libresoc.v:104232.3-104280.6" wire width 2 $0\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:104584.3-104632.6" + attribute \src "libresoc.v:104281.3-104329.6" wire width 2 $0\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:104504.3-104534.6" + attribute \src "libresoc.v:104189.3-104231.6" wire width 8 $0\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:104112.3-104160.6" + attribute \src "libresoc.v:103797.3-103845.6" wire $0\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:103279.3-103327.6" + attribute \src "libresoc.v:102964.3-103012.6" wire width 3 $0\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:103328.3-103376.6" + attribute \src "libresoc.v:103013.3-103061.6" wire width 3 $0\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:103916.3-103964.6" + attribute \src "libresoc.v:103601.3-103649.6" wire width 2 $0\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:104063.3-104111.6" + attribute \src "libresoc.v:103748.3-103796.6" wire $0\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:104308.3-104356.6" + attribute \src "libresoc.v:103993.3-104041.6" wire width 5 $0\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:103230.3-103278.6" + attribute \src "libresoc.v:102915.3-102963.6" wire width 14 $0\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:104633.3-104681.6" + attribute \src "libresoc.v:104330.3-104378.6" wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:104682.3-104730.6" + attribute \src "libresoc.v:104379.3-104427.6" wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:104731.3-104779.6" + attribute \src "libresoc.v:104428.3-104476.6" wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:103769.3-103817.6" + attribute \src "libresoc.v:103454.3-103502.6" wire width 7 $0\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:103965.3-104013.6" + attribute \src "libresoc.v:103650.3-103698.6" wire $0\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:104014.3-104062.6" + attribute \src "libresoc.v:103699.3-103747.6" wire $0\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:104259.3-104307.6" + attribute \src "libresoc.v:103944.3-103992.6" wire $0\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:103720.3-103768.6" + attribute \src "libresoc.v:103405.3-103453.6" wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:104406.3-104454.6" + attribute \src "libresoc.v:104091.3-104139.6" wire $0\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:104780.3-104828.6" + attribute \src "libresoc.v:104477.3-104525.6" wire width 3 $0\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:103867.3-103915.6" + attribute \src "libresoc.v:103552.3-103600.6" wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:104210.3-104258.6" + attribute \src "libresoc.v:103895.3-103943.6" wire $0\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:104455.3-104503.6" + attribute \src "libresoc.v:104140.3-104188.6" wire $0\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:104357.3-104405.6" + attribute \src "libresoc.v:104042.3-104090.6" wire $0\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:104161.3-104209.6" + attribute \src "libresoc.v:103846.3-103894.6" wire $0\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:103622.3-103670.6" + attribute \src "libresoc.v:103307.3-103355.6" wire width 3 $0\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:103671.3-103719.6" + attribute \src "libresoc.v:103356.3-103404.6" wire width 3 $0\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:103377.3-103425.6" + attribute \src "libresoc.v:103062.3-103110.6" wire width 3 $0\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:103426.3-103474.6" + attribute \src "libresoc.v:103111.3-103159.6" wire width 3 $0\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:103475.3-103523.6" + attribute \src "libresoc.v:103160.3-103208.6" wire width 3 $0\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:103573.3-103621.6" + attribute \src "libresoc.v:103258.3-103306.6" wire width 3 $0\dec31_dec_sub21_sv_out2[2:0] - attribute \src "libresoc.v:103524.3-103572.6" + attribute \src "libresoc.v:103209.3-103257.6" wire width 3 $0\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:103818.3-103866.6" + attribute \src "libresoc.v:103503.3-103551.6" wire width 2 $0\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:102882.7-102882.20" + attribute \src "libresoc.v:102567.7-102567.20" wire $0\initial[0:0] - attribute \src "libresoc.v:104535.3-104583.6" + attribute \src "libresoc.v:104232.3-104280.6" wire width 2 $1\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:104584.3-104632.6" + attribute \src "libresoc.v:104281.3-104329.6" wire width 2 $1\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:104504.3-104534.6" + attribute \src "libresoc.v:104189.3-104231.6" wire width 8 $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:104112.3-104160.6" + attribute \src "libresoc.v:103797.3-103845.6" wire $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:103279.3-103327.6" + attribute \src "libresoc.v:102964.3-103012.6" wire width 3 $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:103328.3-103376.6" + attribute \src "libresoc.v:103013.3-103061.6" wire width 3 $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:103916.3-103964.6" + attribute \src "libresoc.v:103601.3-103649.6" wire width 2 $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:104063.3-104111.6" + attribute \src "libresoc.v:103748.3-103796.6" wire $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:104308.3-104356.6" + attribute \src "libresoc.v:103993.3-104041.6" wire width 5 $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:103230.3-103278.6" + attribute \src "libresoc.v:102915.3-102963.6" wire width 14 $1\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:104633.3-104681.6" + attribute \src "libresoc.v:104330.3-104378.6" wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:104682.3-104730.6" + attribute \src "libresoc.v:104379.3-104427.6" wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:104731.3-104779.6" + attribute \src "libresoc.v:104428.3-104476.6" wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:103769.3-103817.6" + attribute \src "libresoc.v:103454.3-103502.6" wire width 7 $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:103965.3-104013.6" + attribute \src "libresoc.v:103650.3-103698.6" wire $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:104014.3-104062.6" + attribute \src "libresoc.v:103699.3-103747.6" wire $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:104259.3-104307.6" + attribute \src "libresoc.v:103944.3-103992.6" wire $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:103720.3-103768.6" + attribute \src "libresoc.v:103405.3-103453.6" wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:104406.3-104454.6" + attribute \src "libresoc.v:104091.3-104139.6" wire $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:104780.3-104828.6" + attribute \src "libresoc.v:104477.3-104525.6" wire width 3 $1\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:103867.3-103915.6" + attribute \src "libresoc.v:103552.3-103600.6" wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:104210.3-104258.6" + attribute \src "libresoc.v:103895.3-103943.6" wire $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:104455.3-104503.6" + attribute \src "libresoc.v:104140.3-104188.6" wire $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:104357.3-104405.6" + attribute \src "libresoc.v:104042.3-104090.6" wire $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:104161.3-104209.6" + attribute \src "libresoc.v:103846.3-103894.6" wire $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:103622.3-103670.6" + attribute \src "libresoc.v:103307.3-103355.6" wire width 3 $1\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:103671.3-103719.6" + attribute \src "libresoc.v:103356.3-103404.6" wire width 3 $1\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:103377.3-103425.6" + attribute \src "libresoc.v:103062.3-103110.6" wire width 3 $1\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:103426.3-103474.6" + attribute \src "libresoc.v:103111.3-103159.6" wire width 3 $1\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:103475.3-103523.6" + attribute \src "libresoc.v:103160.3-103208.6" wire width 3 $1\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:103573.3-103621.6" + attribute \src "libresoc.v:103258.3-103306.6" wire width 3 $1\dec31_dec_sub21_sv_out2[2:0] - attribute \src "libresoc.v:103524.3-103572.6" + attribute \src "libresoc.v:103209.3-103257.6" wire width 3 $1\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:103818.3-103866.6" + attribute \src "libresoc.v:103503.3-103551.6" wire width 2 $1\dec31_dec_sub21_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -160978,28 +160500,28 @@ module \dec31_dec_sub21 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub21_upd - attribute \src "libresoc.v:102882.7-102882.15" + attribute \src "libresoc.v:102567.7-102567.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:102882.7-102882.20" - process $proc$libresoc.v:102882$4156 + attribute \src "libresoc.v:102567.7-102567.20" + process $proc$libresoc.v:102567$4140 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:103230.3-103278.6" - process $proc$libresoc.v:103230$4123 + attribute \src "libresoc.v:102915.3-102963.6" + process $proc$libresoc.v:102915$4107 assign { } { } assign { } { } assign $0\dec31_dec_sub21_function_unit[13:0] $1\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:103231.5-103231.29" + attribute \src "libresoc.v:102916.5-102916.29" switch \initial - attribute \src "libresoc.v:103231.9-103231.17" + attribute \src "libresoc.v:102916.9-102916.17" case 1'1 case end @@ -161067,14 +160589,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[13:0] end - attribute \src "libresoc.v:103279.3-103327.6" - process $proc$libresoc.v:103279$4124 + attribute \src "libresoc.v:102964.3-103012.6" + process $proc$libresoc.v:102964$4108 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:103280.5-103280.29" + attribute \src "libresoc.v:102965.5-102965.29" switch \initial - attribute \src "libresoc.v:103280.9-103280.17" + attribute \src "libresoc.v:102965.9-102965.17" case 1'1 case end @@ -161142,14 +160664,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] end - attribute \src "libresoc.v:103328.3-103376.6" - process $proc$libresoc.v:103328$4125 + attribute \src "libresoc.v:103013.3-103061.6" + process $proc$libresoc.v:103013$4109 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:103329.5-103329.29" + attribute \src "libresoc.v:103014.5-103014.29" switch \initial - attribute \src "libresoc.v:103329.9-103329.17" + attribute \src "libresoc.v:103014.9-103014.17" case 1'1 case end @@ -161217,14 +160739,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] end - attribute \src "libresoc.v:103377.3-103425.6" - process $proc$libresoc.v:103377$4126 + attribute \src "libresoc.v:103062.3-103110.6" + process $proc$libresoc.v:103062$4110 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in1[2:0] $1\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:103378.5-103378.29" + attribute \src "libresoc.v:103063.5-103063.29" switch \initial - attribute \src "libresoc.v:103378.9-103378.17" + attribute \src "libresoc.v:103063.9-103063.17" case 1'1 case end @@ -161292,14 +160814,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in1 $0\dec31_dec_sub21_sv_in1[2:0] end - attribute \src "libresoc.v:103426.3-103474.6" - process $proc$libresoc.v:103426$4127 + attribute \src "libresoc.v:103111.3-103159.6" + process $proc$libresoc.v:103111$4111 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in2[2:0] $1\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:103427.5-103427.29" + attribute \src "libresoc.v:103112.5-103112.29" switch \initial - attribute \src "libresoc.v:103427.9-103427.17" + attribute \src "libresoc.v:103112.9-103112.17" case 1'1 case end @@ -161367,14 +160889,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in2 $0\dec31_dec_sub21_sv_in2[2:0] end - attribute \src "libresoc.v:103475.3-103523.6" - process $proc$libresoc.v:103475$4128 + attribute \src "libresoc.v:103160.3-103208.6" + process $proc$libresoc.v:103160$4112 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in3[2:0] $1\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:103476.5-103476.29" + attribute \src "libresoc.v:103161.5-103161.29" switch \initial - attribute \src "libresoc.v:103476.9-103476.17" + attribute \src "libresoc.v:103161.9-103161.17" case 1'1 case end @@ -161442,14 +160964,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in3 $0\dec31_dec_sub21_sv_in3[2:0] end - attribute \src "libresoc.v:103524.3-103572.6" - process $proc$libresoc.v:103524$4129 + attribute \src "libresoc.v:103209.3-103257.6" + process $proc$libresoc.v:103209$4113 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_out[2:0] $1\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:103525.5-103525.29" + attribute \src "libresoc.v:103210.5-103210.29" switch \initial - attribute \src "libresoc.v:103525.9-103525.17" + attribute \src "libresoc.v:103210.9-103210.17" case 1'1 case end @@ -161517,14 +161039,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_out $0\dec31_dec_sub21_sv_out[2:0] end - attribute \src "libresoc.v:103573.3-103621.6" - process $proc$libresoc.v:103573$4130 + attribute \src "libresoc.v:103258.3-103306.6" + process $proc$libresoc.v:103258$4114 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_out2[2:0] $1\dec31_dec_sub21_sv_out2[2:0] - attribute \src "libresoc.v:103574.5-103574.29" + attribute \src "libresoc.v:103259.5-103259.29" switch \initial - attribute \src "libresoc.v:103574.9-103574.17" + attribute \src "libresoc.v:103259.9-103259.17" case 1'1 case end @@ -161592,14 +161114,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_out2 $0\dec31_dec_sub21_sv_out2[2:0] end - attribute \src "libresoc.v:103622.3-103670.6" - process $proc$libresoc.v:103622$4131 + attribute \src "libresoc.v:103307.3-103355.6" + process $proc$libresoc.v:103307$4115 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_in[2:0] $1\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:103623.5-103623.29" + attribute \src "libresoc.v:103308.5-103308.29" switch \initial - attribute \src "libresoc.v:103623.9-103623.17" + attribute \src "libresoc.v:103308.9-103308.17" case 1'1 case end @@ -161667,14 +161189,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_cr_in $0\dec31_dec_sub21_sv_cr_in[2:0] end - attribute \src "libresoc.v:103671.3-103719.6" - process $proc$libresoc.v:103671$4132 + attribute \src "libresoc.v:103356.3-103404.6" + process $proc$libresoc.v:103356$4116 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_out[2:0] $1\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:103672.5-103672.29" + attribute \src "libresoc.v:103357.5-103357.29" switch \initial - attribute \src "libresoc.v:103672.9-103672.17" + attribute \src "libresoc.v:103357.9-103357.17" case 1'1 case end @@ -161742,14 +161264,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_cr_out $0\dec31_dec_sub21_sv_cr_out[2:0] end - attribute \src "libresoc.v:103720.3-103768.6" - process $proc$libresoc.v:103720$4133 + attribute \src "libresoc.v:103405.3-103453.6" + process $proc$libresoc.v:103405$4117 assign { } { } assign { } { } assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:103721.5-103721.29" + attribute \src "libresoc.v:103406.5-103406.29" switch \initial - attribute \src "libresoc.v:103721.9-103721.17" + attribute \src "libresoc.v:103406.9-103406.17" case 1'1 case end @@ -161817,14 +161339,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] end - attribute \src "libresoc.v:103769.3-103817.6" - process $proc$libresoc.v:103769$4134 + attribute \src "libresoc.v:103454.3-103502.6" + process $proc$libresoc.v:103454$4118 assign { } { } assign { } { } assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:103770.5-103770.29" + attribute \src "libresoc.v:103455.5-103455.29" switch \initial - attribute \src "libresoc.v:103770.9-103770.17" + attribute \src "libresoc.v:103455.9-103455.17" case 1'1 case end @@ -161892,14 +161414,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] end - attribute \src "libresoc.v:103818.3-103866.6" - process $proc$libresoc.v:103818$4135 + attribute \src "libresoc.v:103503.3-103551.6" + process $proc$libresoc.v:103503$4119 assign { } { } assign { } { } assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:103819.5-103819.29" + attribute \src "libresoc.v:103504.5-103504.29" switch \initial - attribute \src "libresoc.v:103819.9-103819.17" + attribute \src "libresoc.v:103504.9-103504.17" case 1'1 case end @@ -161967,14 +161489,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] end - attribute \src "libresoc.v:103867.3-103915.6" - process $proc$libresoc.v:103867$4136 + attribute \src "libresoc.v:103552.3-103600.6" + process $proc$libresoc.v:103552$4120 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:103868.5-103868.29" + attribute \src "libresoc.v:103553.5-103553.29" switch \initial - attribute \src "libresoc.v:103868.9-103868.17" + attribute \src "libresoc.v:103553.9-103553.17" case 1'1 case end @@ -162042,14 +161564,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] end - attribute \src "libresoc.v:103916.3-103964.6" - process $proc$libresoc.v:103916$4137 + attribute \src "libresoc.v:103601.3-103649.6" + process $proc$libresoc.v:103601$4121 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:103917.5-103917.29" + attribute \src "libresoc.v:103602.5-103602.29" switch \initial - attribute \src "libresoc.v:103917.9-103917.17" + attribute \src "libresoc.v:103602.9-103602.17" case 1'1 case end @@ -162117,14 +161639,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] end - attribute \src "libresoc.v:103965.3-104013.6" - process $proc$libresoc.v:103965$4138 + attribute \src "libresoc.v:103650.3-103698.6" + process $proc$libresoc.v:103650$4122 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:103966.5-103966.29" + attribute \src "libresoc.v:103651.5-103651.29" switch \initial - attribute \src "libresoc.v:103966.9-103966.17" + attribute \src "libresoc.v:103651.9-103651.17" case 1'1 case end @@ -162192,14 +161714,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] end - attribute \src "libresoc.v:104014.3-104062.6" - process $proc$libresoc.v:104014$4139 + attribute \src "libresoc.v:103699.3-103747.6" + process $proc$libresoc.v:103699$4123 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:104015.5-104015.29" + attribute \src "libresoc.v:103700.5-103700.29" switch \initial - attribute \src "libresoc.v:104015.9-104015.17" + attribute \src "libresoc.v:103700.9-103700.17" case 1'1 case end @@ -162267,14 +161789,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] end - attribute \src "libresoc.v:104063.3-104111.6" - process $proc$libresoc.v:104063$4140 + attribute \src "libresoc.v:103748.3-103796.6" + process $proc$libresoc.v:103748$4124 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:104064.5-104064.29" + attribute \src "libresoc.v:103749.5-103749.29" switch \initial - attribute \src "libresoc.v:104064.9-104064.17" + attribute \src "libresoc.v:103749.9-103749.17" case 1'1 case end @@ -162342,14 +161864,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] end - attribute \src "libresoc.v:104112.3-104160.6" - process $proc$libresoc.v:104112$4141 + attribute \src "libresoc.v:103797.3-103845.6" + process $proc$libresoc.v:103797$4125 assign { } { } assign { } { } assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:104113.5-104113.29" + attribute \src "libresoc.v:103798.5-103798.29" switch \initial - attribute \src "libresoc.v:104113.9-104113.17" + attribute \src "libresoc.v:103798.9-103798.17" case 1'1 case end @@ -162417,14 +161939,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] end - attribute \src "libresoc.v:104161.3-104209.6" - process $proc$libresoc.v:104161$4142 + attribute \src "libresoc.v:103846.3-103894.6" + process $proc$libresoc.v:103846$4126 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:104162.5-104162.29" + attribute \src "libresoc.v:103847.5-103847.29" switch \initial - attribute \src "libresoc.v:104162.9-104162.17" + attribute \src "libresoc.v:103847.9-103847.17" case 1'1 case end @@ -162492,14 +162014,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] end - attribute \src "libresoc.v:104210.3-104258.6" - process $proc$libresoc.v:104210$4143 + attribute \src "libresoc.v:103895.3-103943.6" + process $proc$libresoc.v:103895$4127 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:104211.5-104211.29" + attribute \src "libresoc.v:103896.5-103896.29" switch \initial - attribute \src "libresoc.v:104211.9-104211.17" + attribute \src "libresoc.v:103896.9-103896.17" case 1'1 case end @@ -162567,14 +162089,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] end - attribute \src "libresoc.v:104259.3-104307.6" - process $proc$libresoc.v:104259$4144 + attribute \src "libresoc.v:103944.3-103992.6" + process $proc$libresoc.v:103944$4128 assign { } { } assign { } { } assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:104260.5-104260.29" + attribute \src "libresoc.v:103945.5-103945.29" switch \initial - attribute \src "libresoc.v:104260.9-104260.17" + attribute \src "libresoc.v:103945.9-103945.17" case 1'1 case end @@ -162642,14 +162164,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] end - attribute \src "libresoc.v:104308.3-104356.6" - process $proc$libresoc.v:104308$4145 + attribute \src "libresoc.v:103993.3-104041.6" + process $proc$libresoc.v:103993$4129 assign { } { } assign { } { } assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:104309.5-104309.29" + attribute \src "libresoc.v:103994.5-103994.29" switch \initial - attribute \src "libresoc.v:104309.9-104309.17" + attribute \src "libresoc.v:103994.9-103994.17" case 1'1 case end @@ -162717,14 +162239,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] end - attribute \src "libresoc.v:104357.3-104405.6" - process $proc$libresoc.v:104357$4146 + attribute \src "libresoc.v:104042.3-104090.6" + process $proc$libresoc.v:104042$4130 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:104358.5-104358.29" + attribute \src "libresoc.v:104043.5-104043.29" switch \initial - attribute \src "libresoc.v:104358.9-104358.17" + attribute \src "libresoc.v:104043.9-104043.17" case 1'1 case end @@ -162792,14 +162314,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] end - attribute \src "libresoc.v:104406.3-104454.6" - process $proc$libresoc.v:104406$4147 + attribute \src "libresoc.v:104091.3-104139.6" + process $proc$libresoc.v:104091$4131 assign { } { } assign { } { } assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:104407.5-104407.29" + attribute \src "libresoc.v:104092.5-104092.29" switch \initial - attribute \src "libresoc.v:104407.9-104407.17" + attribute \src "libresoc.v:104092.9-104092.17" case 1'1 case end @@ -162867,14 +162389,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] end - attribute \src "libresoc.v:104455.3-104503.6" - process $proc$libresoc.v:104455$4148 + attribute \src "libresoc.v:104140.3-104188.6" + process $proc$libresoc.v:104140$4132 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:104456.5-104456.29" + attribute \src "libresoc.v:104141.5-104141.29" switch \initial - attribute \src "libresoc.v:104456.9-104456.17" + attribute \src "libresoc.v:104141.9-104141.17" case 1'1 case end @@ -162942,20 +162464,26 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] end - attribute \src "libresoc.v:104504.3-104534.6" - process $proc$libresoc.v:104504$4149 + attribute \src "libresoc.v:104189.3-104231.6" + process $proc$libresoc.v:104189$4133 assign { } { } assign { } { } assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:104505.5-104505.29" + attribute \src "libresoc.v:104190.5-104190.29" switch \initial - attribute \src "libresoc.v:104505.9-104505.17" + attribute \src "libresoc.v:104190.9-104190.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 @@ -162964,6 +162492,9 @@ module \dec31_dec_sub21 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 @@ -162980,6 +162511,9 @@ module \dec31_dec_sub21 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'10101000 attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 @@ -162993,14 +162527,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] end - attribute \src "libresoc.v:104535.3-104583.6" - process $proc$libresoc.v:104535$4150 + attribute \src "libresoc.v:104232.3-104280.6" + process $proc$libresoc.v:104232$4134 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Etype[1:0] $1\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:104536.5-104536.29" + attribute \src "libresoc.v:104233.5-104233.29" switch \initial - attribute \src "libresoc.v:104536.9-104536.17" + attribute \src "libresoc.v:104233.9-104233.17" case 1'1 case end @@ -163068,14 +162602,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_SV_Etype $0\dec31_dec_sub21_SV_Etype[1:0] end - attribute \src "libresoc.v:104584.3-104632.6" - process $proc$libresoc.v:104584$4151 + attribute \src "libresoc.v:104281.3-104329.6" + process $proc$libresoc.v:104281$4135 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Ptype[1:0] $1\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:104585.5-104585.29" + attribute \src "libresoc.v:104282.5-104282.29" switch \initial - attribute \src "libresoc.v:104585.9-104585.17" + attribute \src "libresoc.v:104282.9-104282.17" case 1'1 case end @@ -163143,14 +162677,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_SV_Ptype $0\dec31_dec_sub21_SV_Ptype[1:0] end - attribute \src "libresoc.v:104633.3-104681.6" - process $proc$libresoc.v:104633$4152 + attribute \src "libresoc.v:104330.3-104378.6" + process $proc$libresoc.v:104330$4136 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:104634.5-104634.29" + attribute \src "libresoc.v:104331.5-104331.29" switch \initial - attribute \src "libresoc.v:104634.9-104634.17" + attribute \src "libresoc.v:104331.9-104331.17" case 1'1 case end @@ -163218,14 +162752,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] end - attribute \src "libresoc.v:104682.3-104730.6" - process $proc$libresoc.v:104682$4153 + attribute \src "libresoc.v:104379.3-104427.6" + process $proc$libresoc.v:104379$4137 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:104683.5-104683.29" + attribute \src "libresoc.v:104380.5-104380.29" switch \initial - attribute \src "libresoc.v:104683.9-104683.17" + attribute \src "libresoc.v:104380.9-104380.17" case 1'1 case end @@ -163293,14 +162827,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] end - attribute \src "libresoc.v:104731.3-104779.6" - process $proc$libresoc.v:104731$4154 + attribute \src "libresoc.v:104428.3-104476.6" + process $proc$libresoc.v:104428$4138 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:104732.5-104732.29" + attribute \src "libresoc.v:104429.5-104429.29" switch \initial - attribute \src "libresoc.v:104732.9-104732.17" + attribute \src "libresoc.v:104429.9-104429.17" case 1'1 case end @@ -163368,14 +162902,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] end - attribute \src "libresoc.v:104780.3-104828.6" - process $proc$libresoc.v:104780$4155 + attribute \src "libresoc.v:104477.3-104525.6" + process $proc$libresoc.v:104477$4139 assign { } { } assign { } { } assign $0\dec31_dec_sub21_out_sel[2:0] $1\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:104781.5-104781.29" + attribute \src "libresoc.v:104478.5-104478.29" switch \initial - attribute \src "libresoc.v:104781.9-104781.17" + attribute \src "libresoc.v:104478.9-104478.17" case 1'1 case end @@ -163445,144 +162979,144 @@ module \dec31_dec_sub21 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:104834.1-106999.10" +attribute \src "libresoc.v:104531.1-106696.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" attribute \generator "nMigen" module \dec31_dec_sub22 - attribute \src "libresoc.v:106668.3-106722.6" + attribute \src "libresoc.v:106365.3-106419.6" wire width 2 $0\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:106723.3-106777.6" + attribute \src "libresoc.v:106420.3-106474.6" wire width 2 $0\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:106008.3-106062.6" + attribute \src "libresoc.v:105705.3-105759.6" wire width 8 $0\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:106228.3-106282.6" + attribute \src "libresoc.v:105925.3-105979.6" wire $0\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:105238.3-105292.6" + attribute \src "libresoc.v:104935.3-104989.6" wire width 3 $0\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:105293.3-105347.6" + attribute \src "libresoc.v:104990.3-105044.6" wire width 3 $0\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:105953.3-106007.6" + attribute \src "libresoc.v:105650.3-105704.6" wire width 2 $0\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:106173.3-106227.6" + attribute \src "libresoc.v:105870.3-105924.6" wire $0\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:106393.3-106447.6" + attribute \src "libresoc.v:106090.3-106144.6" wire width 5 $0\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:105183.3-105237.6" + attribute \src "libresoc.v:104880.3-104934.6" wire width 14 $0\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:106778.3-106832.6" + attribute \src "libresoc.v:106475.3-106529.6" wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:106833.3-106887.6" + attribute \src "libresoc.v:106530.3-106584.6" wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:106888.3-106942.6" + attribute \src "libresoc.v:106585.3-106639.6" wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:105788.3-105842.6" + attribute \src "libresoc.v:105485.3-105539.6" wire width 7 $0\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:106063.3-106117.6" + attribute \src "libresoc.v:105760.3-105814.6" wire $0\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:106118.3-106172.6" + attribute \src "libresoc.v:105815.3-105869.6" wire $0\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:106448.3-106502.6" + attribute \src "libresoc.v:106145.3-106199.6" wire $0\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:105733.3-105787.6" + attribute \src "libresoc.v:105430.3-105484.6" wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:106558.3-106612.6" + attribute \src "libresoc.v:106255.3-106309.6" wire $0\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:106943.3-106997.6" + attribute \src "libresoc.v:106640.3-106694.6" wire width 3 $0\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:105898.3-105952.6" + attribute \src "libresoc.v:105595.3-105649.6" wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:106338.3-106392.6" + attribute \src "libresoc.v:106035.3-106089.6" wire $0\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:106613.3-106667.6" + attribute \src "libresoc.v:106310.3-106364.6" wire $0\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:106503.3-106557.6" + attribute \src "libresoc.v:106200.3-106254.6" wire $0\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:106283.3-106337.6" + attribute \src "libresoc.v:105980.3-106034.6" wire $0\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:105623.3-105677.6" + attribute \src "libresoc.v:105320.3-105374.6" wire width 3 $0\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:105678.3-105732.6" + attribute \src "libresoc.v:105375.3-105429.6" wire width 3 $0\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:105348.3-105402.6" + attribute \src "libresoc.v:105045.3-105099.6" wire width 3 $0\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:105403.3-105457.6" + attribute \src "libresoc.v:105100.3-105154.6" wire width 3 $0\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:105458.3-105512.6" + attribute \src "libresoc.v:105155.3-105209.6" wire width 3 $0\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:105568.3-105622.6" + attribute \src "libresoc.v:105265.3-105319.6" wire width 3 $0\dec31_dec_sub22_sv_out2[2:0] - attribute \src "libresoc.v:105513.3-105567.6" + attribute \src "libresoc.v:105210.3-105264.6" wire width 3 $0\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:105843.3-105897.6" + attribute \src "libresoc.v:105540.3-105594.6" wire width 2 $0\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:104835.7-104835.20" + attribute \src "libresoc.v:104532.7-104532.20" wire $0\initial[0:0] - attribute \src "libresoc.v:106668.3-106722.6" + attribute \src "libresoc.v:106365.3-106419.6" wire width 2 $1\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:106723.3-106777.6" + attribute \src "libresoc.v:106420.3-106474.6" wire width 2 $1\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:106008.3-106062.6" + attribute \src "libresoc.v:105705.3-105759.6" wire width 8 $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:106228.3-106282.6" + attribute \src "libresoc.v:105925.3-105979.6" wire $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:105238.3-105292.6" + attribute \src "libresoc.v:104935.3-104989.6" wire width 3 $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:105293.3-105347.6" + attribute \src "libresoc.v:104990.3-105044.6" wire width 3 $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:105953.3-106007.6" + attribute \src "libresoc.v:105650.3-105704.6" wire width 2 $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:106173.3-106227.6" + attribute \src "libresoc.v:105870.3-105924.6" wire $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:106393.3-106447.6" + attribute \src "libresoc.v:106090.3-106144.6" wire width 5 $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:105183.3-105237.6" + attribute \src "libresoc.v:104880.3-104934.6" wire width 14 $1\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:106778.3-106832.6" + attribute \src "libresoc.v:106475.3-106529.6" wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:106833.3-106887.6" + attribute \src "libresoc.v:106530.3-106584.6" wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:106888.3-106942.6" + attribute \src "libresoc.v:106585.3-106639.6" wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:105788.3-105842.6" + attribute \src "libresoc.v:105485.3-105539.6" wire width 7 $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:106063.3-106117.6" + attribute \src "libresoc.v:105760.3-105814.6" wire $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:106118.3-106172.6" + attribute \src "libresoc.v:105815.3-105869.6" wire $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:106448.3-106502.6" + attribute \src "libresoc.v:106145.3-106199.6" wire $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:105733.3-105787.6" + attribute \src "libresoc.v:105430.3-105484.6" wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:106558.3-106612.6" + attribute \src "libresoc.v:106255.3-106309.6" wire $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:106943.3-106997.6" + attribute \src "libresoc.v:106640.3-106694.6" wire width 3 $1\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:105898.3-105952.6" + attribute \src "libresoc.v:105595.3-105649.6" wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:106338.3-106392.6" + attribute \src "libresoc.v:106035.3-106089.6" wire $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:106613.3-106667.6" + attribute \src "libresoc.v:106310.3-106364.6" wire $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:106503.3-106557.6" + attribute \src "libresoc.v:106200.3-106254.6" wire $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:106283.3-106337.6" + attribute \src "libresoc.v:105980.3-106034.6" wire $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:105623.3-105677.6" + attribute \src "libresoc.v:105320.3-105374.6" wire width 3 $1\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:105678.3-105732.6" + attribute \src "libresoc.v:105375.3-105429.6" wire width 3 $1\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:105348.3-105402.6" + attribute \src "libresoc.v:105045.3-105099.6" wire width 3 $1\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:105403.3-105457.6" + attribute \src "libresoc.v:105100.3-105154.6" wire width 3 $1\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:105458.3-105512.6" + attribute \src "libresoc.v:105155.3-105209.6" wire width 3 $1\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:105568.3-105622.6" + attribute \src "libresoc.v:105265.3-105319.6" wire width 3 $1\dec31_dec_sub22_sv_out2[2:0] - attribute \src "libresoc.v:105513.3-105567.6" + attribute \src "libresoc.v:105210.3-105264.6" wire width 3 $1\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:105843.3-105897.6" + attribute \src "libresoc.v:105540.3-105594.6" wire width 2 $1\dec31_dec_sub22_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -163894,28 +163428,28 @@ module \dec31_dec_sub22 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub22_upd - attribute \src "libresoc.v:104835.7-104835.15" + attribute \src "libresoc.v:104532.7-104532.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:104835.7-104835.20" - process $proc$libresoc.v:104835$4190 + attribute \src "libresoc.v:104532.7-104532.20" + process $proc$libresoc.v:104532$4174 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:105183.3-105237.6" - process $proc$libresoc.v:105183$4157 + attribute \src "libresoc.v:104880.3-104934.6" + process $proc$libresoc.v:104880$4141 assign { } { } assign { } { } assign $0\dec31_dec_sub22_function_unit[13:0] $1\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:105184.5-105184.29" + attribute \src "libresoc.v:104881.5-104881.29" switch \initial - attribute \src "libresoc.v:105184.9-105184.17" + attribute \src "libresoc.v:104881.9-104881.17" case 1'1 case end @@ -163991,14 +163525,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[13:0] end - attribute \src "libresoc.v:105238.3-105292.6" - process $proc$libresoc.v:105238$4158 + attribute \src "libresoc.v:104935.3-104989.6" + process $proc$libresoc.v:104935$4142 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:105239.5-105239.29" + attribute \src "libresoc.v:104936.5-104936.29" switch \initial - attribute \src "libresoc.v:105239.9-105239.17" + attribute \src "libresoc.v:104936.9-104936.17" case 1'1 case end @@ -164074,14 +163608,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:105293.3-105347.6" - process $proc$libresoc.v:105293$4159 + attribute \src "libresoc.v:104990.3-105044.6" + process $proc$libresoc.v:104990$4143 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:105294.5-105294.29" + attribute \src "libresoc.v:104991.5-104991.29" switch \initial - attribute \src "libresoc.v:105294.9-105294.17" + attribute \src "libresoc.v:104991.9-104991.17" case 1'1 case end @@ -164157,14 +163691,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] end - attribute \src "libresoc.v:105348.3-105402.6" - process $proc$libresoc.v:105348$4160 + attribute \src "libresoc.v:105045.3-105099.6" + process $proc$libresoc.v:105045$4144 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in1[2:0] $1\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:105349.5-105349.29" + attribute \src "libresoc.v:105046.5-105046.29" switch \initial - attribute \src "libresoc.v:105349.9-105349.17" + attribute \src "libresoc.v:105046.9-105046.17" case 1'1 case end @@ -164240,14 +163774,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in1 $0\dec31_dec_sub22_sv_in1[2:0] end - attribute \src "libresoc.v:105403.3-105457.6" - process $proc$libresoc.v:105403$4161 + attribute \src "libresoc.v:105100.3-105154.6" + process $proc$libresoc.v:105100$4145 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in2[2:0] $1\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:105404.5-105404.29" + attribute \src "libresoc.v:105101.5-105101.29" switch \initial - attribute \src "libresoc.v:105404.9-105404.17" + attribute \src "libresoc.v:105101.9-105101.17" case 1'1 case end @@ -164323,14 +163857,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in2 $0\dec31_dec_sub22_sv_in2[2:0] end - attribute \src "libresoc.v:105458.3-105512.6" - process $proc$libresoc.v:105458$4162 + attribute \src "libresoc.v:105155.3-105209.6" + process $proc$libresoc.v:105155$4146 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in3[2:0] $1\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:105459.5-105459.29" + attribute \src "libresoc.v:105156.5-105156.29" switch \initial - attribute \src "libresoc.v:105459.9-105459.17" + attribute \src "libresoc.v:105156.9-105156.17" case 1'1 case end @@ -164406,14 +163940,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in3 $0\dec31_dec_sub22_sv_in3[2:0] end - attribute \src "libresoc.v:105513.3-105567.6" - process $proc$libresoc.v:105513$4163 + attribute \src "libresoc.v:105210.3-105264.6" + process $proc$libresoc.v:105210$4147 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_out[2:0] $1\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:105514.5-105514.29" + attribute \src "libresoc.v:105211.5-105211.29" switch \initial - attribute \src "libresoc.v:105514.9-105514.17" + attribute \src "libresoc.v:105211.9-105211.17" case 1'1 case end @@ -164489,14 +164023,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_out $0\dec31_dec_sub22_sv_out[2:0] end - attribute \src "libresoc.v:105568.3-105622.6" - process $proc$libresoc.v:105568$4164 + attribute \src "libresoc.v:105265.3-105319.6" + process $proc$libresoc.v:105265$4148 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_out2[2:0] $1\dec31_dec_sub22_sv_out2[2:0] - attribute \src "libresoc.v:105569.5-105569.29" + attribute \src "libresoc.v:105266.5-105266.29" switch \initial - attribute \src "libresoc.v:105569.9-105569.17" + attribute \src "libresoc.v:105266.9-105266.17" case 1'1 case end @@ -164572,14 +164106,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_out2 $0\dec31_dec_sub22_sv_out2[2:0] end - attribute \src "libresoc.v:105623.3-105677.6" - process $proc$libresoc.v:105623$4165 + attribute \src "libresoc.v:105320.3-105374.6" + process $proc$libresoc.v:105320$4149 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_in[2:0] $1\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:105624.5-105624.29" + attribute \src "libresoc.v:105321.5-105321.29" switch \initial - attribute \src "libresoc.v:105624.9-105624.17" + attribute \src "libresoc.v:105321.9-105321.17" case 1'1 case end @@ -164655,14 +164189,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_cr_in $0\dec31_dec_sub22_sv_cr_in[2:0] end - attribute \src "libresoc.v:105678.3-105732.6" - process $proc$libresoc.v:105678$4166 + attribute \src "libresoc.v:105375.3-105429.6" + process $proc$libresoc.v:105375$4150 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_out[2:0] $1\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:105679.5-105679.29" + attribute \src "libresoc.v:105376.5-105376.29" switch \initial - attribute \src "libresoc.v:105679.9-105679.17" + attribute \src "libresoc.v:105376.9-105376.17" case 1'1 case end @@ -164738,14 +164272,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_cr_out $0\dec31_dec_sub22_sv_cr_out[2:0] end - attribute \src "libresoc.v:105733.3-105787.6" - process $proc$libresoc.v:105733$4167 + attribute \src "libresoc.v:105430.3-105484.6" + process $proc$libresoc.v:105430$4151 assign { } { } assign { } { } assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:105734.5-105734.29" + attribute \src "libresoc.v:105431.5-105431.29" switch \initial - attribute \src "libresoc.v:105734.9-105734.17" + attribute \src "libresoc.v:105431.9-105431.17" case 1'1 case end @@ -164821,14 +164355,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] end - attribute \src "libresoc.v:105788.3-105842.6" - process $proc$libresoc.v:105788$4168 + attribute \src "libresoc.v:105485.3-105539.6" + process $proc$libresoc.v:105485$4152 assign { } { } assign { } { } assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:105789.5-105789.29" + attribute \src "libresoc.v:105486.5-105486.29" switch \initial - attribute \src "libresoc.v:105789.9-105789.17" + attribute \src "libresoc.v:105486.9-105486.17" case 1'1 case end @@ -164904,14 +164438,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] end - attribute \src "libresoc.v:105843.3-105897.6" - process $proc$libresoc.v:105843$4169 + attribute \src "libresoc.v:105540.3-105594.6" + process $proc$libresoc.v:105540$4153 assign { } { } assign { } { } assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:105844.5-105844.29" + attribute \src "libresoc.v:105541.5-105541.29" switch \initial - attribute \src "libresoc.v:105844.9-105844.17" + attribute \src "libresoc.v:105541.9-105541.17" case 1'1 case end @@ -164987,14 +164521,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] end - attribute \src "libresoc.v:105898.3-105952.6" - process $proc$libresoc.v:105898$4170 + attribute \src "libresoc.v:105595.3-105649.6" + process $proc$libresoc.v:105595$4154 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:105899.5-105899.29" + attribute \src "libresoc.v:105596.5-105596.29" switch \initial - attribute \src "libresoc.v:105899.9-105899.17" + attribute \src "libresoc.v:105596.9-105596.17" case 1'1 case end @@ -165070,14 +164604,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] end - attribute \src "libresoc.v:105953.3-106007.6" - process $proc$libresoc.v:105953$4171 + attribute \src "libresoc.v:105650.3-105704.6" + process $proc$libresoc.v:105650$4155 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:105954.5-105954.29" + attribute \src "libresoc.v:105651.5-105651.29" switch \initial - attribute \src "libresoc.v:105954.9-105954.17" + attribute \src "libresoc.v:105651.9-105651.17" case 1'1 case end @@ -165153,14 +164687,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] end - attribute \src "libresoc.v:106008.3-106062.6" - process $proc$libresoc.v:106008$4172 + attribute \src "libresoc.v:105705.3-105759.6" + process $proc$libresoc.v:105705$4156 assign { } { } assign { } { } assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:106009.5-106009.29" + attribute \src "libresoc.v:105706.5-105706.29" switch \initial - attribute \src "libresoc.v:106009.9-106009.17" + attribute \src "libresoc.v:105706.9-105706.17" case 1'1 case end @@ -165236,14 +164770,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] end - attribute \src "libresoc.v:106063.3-106117.6" - process $proc$libresoc.v:106063$4173 + attribute \src "libresoc.v:105760.3-105814.6" + process $proc$libresoc.v:105760$4157 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:106064.5-106064.29" + attribute \src "libresoc.v:105761.5-105761.29" switch \initial - attribute \src "libresoc.v:106064.9-106064.17" + attribute \src "libresoc.v:105761.9-105761.17" case 1'1 case end @@ -165319,14 +164853,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] end - attribute \src "libresoc.v:106118.3-106172.6" - process $proc$libresoc.v:106118$4174 + attribute \src "libresoc.v:105815.3-105869.6" + process $proc$libresoc.v:105815$4158 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:106119.5-106119.29" + attribute \src "libresoc.v:105816.5-105816.29" switch \initial - attribute \src "libresoc.v:106119.9-106119.17" + attribute \src "libresoc.v:105816.9-105816.17" case 1'1 case end @@ -165402,14 +164936,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] end - attribute \src "libresoc.v:106173.3-106227.6" - process $proc$libresoc.v:106173$4175 + attribute \src "libresoc.v:105870.3-105924.6" + process $proc$libresoc.v:105870$4159 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:106174.5-106174.29" + attribute \src "libresoc.v:105871.5-105871.29" switch \initial - attribute \src "libresoc.v:106174.9-106174.17" + attribute \src "libresoc.v:105871.9-105871.17" case 1'1 case end @@ -165485,14 +165019,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] end - attribute \src "libresoc.v:106228.3-106282.6" - process $proc$libresoc.v:106228$4176 + attribute \src "libresoc.v:105925.3-105979.6" + process $proc$libresoc.v:105925$4160 assign { } { } assign { } { } assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:106229.5-106229.29" + attribute \src "libresoc.v:105926.5-105926.29" switch \initial - attribute \src "libresoc.v:106229.9-106229.17" + attribute \src "libresoc.v:105926.9-105926.17" case 1'1 case end @@ -165568,14 +165102,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] end - attribute \src "libresoc.v:106283.3-106337.6" - process $proc$libresoc.v:106283$4177 + attribute \src "libresoc.v:105980.3-106034.6" + process $proc$libresoc.v:105980$4161 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:106284.5-106284.29" + attribute \src "libresoc.v:105981.5-105981.29" switch \initial - attribute \src "libresoc.v:106284.9-106284.17" + attribute \src "libresoc.v:105981.9-105981.17" case 1'1 case end @@ -165651,14 +165185,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] end - attribute \src "libresoc.v:106338.3-106392.6" - process $proc$libresoc.v:106338$4178 + attribute \src "libresoc.v:106035.3-106089.6" + process $proc$libresoc.v:106035$4162 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:106339.5-106339.29" + attribute \src "libresoc.v:106036.5-106036.29" switch \initial - attribute \src "libresoc.v:106339.9-106339.17" + attribute \src "libresoc.v:106036.9-106036.17" case 1'1 case end @@ -165734,14 +165268,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] end - attribute \src "libresoc.v:106393.3-106447.6" - process $proc$libresoc.v:106393$4179 + attribute \src "libresoc.v:106090.3-106144.6" + process $proc$libresoc.v:106090$4163 assign { } { } assign { } { } assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:106394.5-106394.29" + attribute \src "libresoc.v:106091.5-106091.29" switch \initial - attribute \src "libresoc.v:106394.9-106394.17" + attribute \src "libresoc.v:106091.9-106091.17" case 1'1 case end @@ -165817,14 +165351,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] end - attribute \src "libresoc.v:106448.3-106502.6" - process $proc$libresoc.v:106448$4180 + attribute \src "libresoc.v:106145.3-106199.6" + process $proc$libresoc.v:106145$4164 assign { } { } assign { } { } assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:106449.5-106449.29" + attribute \src "libresoc.v:106146.5-106146.29" switch \initial - attribute \src "libresoc.v:106449.9-106449.17" + attribute \src "libresoc.v:106146.9-106146.17" case 1'1 case end @@ -165900,14 +165434,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] end - attribute \src "libresoc.v:106503.3-106557.6" - process $proc$libresoc.v:106503$4181 + attribute \src "libresoc.v:106200.3-106254.6" + process $proc$libresoc.v:106200$4165 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:106504.5-106504.29" + attribute \src "libresoc.v:106201.5-106201.29" switch \initial - attribute \src "libresoc.v:106504.9-106504.17" + attribute \src "libresoc.v:106201.9-106201.17" case 1'1 case end @@ -165983,14 +165517,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] end - attribute \src "libresoc.v:106558.3-106612.6" - process $proc$libresoc.v:106558$4182 + attribute \src "libresoc.v:106255.3-106309.6" + process $proc$libresoc.v:106255$4166 assign { } { } assign { } { } assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:106559.5-106559.29" + attribute \src "libresoc.v:106256.5-106256.29" switch \initial - attribute \src "libresoc.v:106559.9-106559.17" + attribute \src "libresoc.v:106256.9-106256.17" case 1'1 case end @@ -166066,14 +165600,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] end - attribute \src "libresoc.v:106613.3-106667.6" - process $proc$libresoc.v:106613$4183 + attribute \src "libresoc.v:106310.3-106364.6" + process $proc$libresoc.v:106310$4167 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:106614.5-106614.29" + attribute \src "libresoc.v:106311.5-106311.29" switch \initial - attribute \src "libresoc.v:106614.9-106614.17" + attribute \src "libresoc.v:106311.9-106311.17" case 1'1 case end @@ -166149,14 +165683,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] end - attribute \src "libresoc.v:106668.3-106722.6" - process $proc$libresoc.v:106668$4184 + attribute \src "libresoc.v:106365.3-106419.6" + process $proc$libresoc.v:106365$4168 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Etype[1:0] $1\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:106669.5-106669.29" + attribute \src "libresoc.v:106366.5-106366.29" switch \initial - attribute \src "libresoc.v:106669.9-106669.17" + attribute \src "libresoc.v:106366.9-106366.17" case 1'1 case end @@ -166232,14 +165766,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_SV_Etype $0\dec31_dec_sub22_SV_Etype[1:0] end - attribute \src "libresoc.v:106723.3-106777.6" - process $proc$libresoc.v:106723$4185 + attribute \src "libresoc.v:106420.3-106474.6" + process $proc$libresoc.v:106420$4169 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Ptype[1:0] $1\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:106724.5-106724.29" + attribute \src "libresoc.v:106421.5-106421.29" switch \initial - attribute \src "libresoc.v:106724.9-106724.17" + attribute \src "libresoc.v:106421.9-106421.17" case 1'1 case end @@ -166315,14 +165849,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_SV_Ptype $0\dec31_dec_sub22_SV_Ptype[1:0] end - attribute \src "libresoc.v:106778.3-106832.6" - process $proc$libresoc.v:106778$4186 + attribute \src "libresoc.v:106475.3-106529.6" + process $proc$libresoc.v:106475$4170 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:106779.5-106779.29" + attribute \src "libresoc.v:106476.5-106476.29" switch \initial - attribute \src "libresoc.v:106779.9-106779.17" + attribute \src "libresoc.v:106476.9-106476.17" case 1'1 case end @@ -166398,14 +165932,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] end - attribute \src "libresoc.v:106833.3-106887.6" - process $proc$libresoc.v:106833$4187 + attribute \src "libresoc.v:106530.3-106584.6" + process $proc$libresoc.v:106530$4171 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:106834.5-106834.29" + attribute \src "libresoc.v:106531.5-106531.29" switch \initial - attribute \src "libresoc.v:106834.9-106834.17" + attribute \src "libresoc.v:106531.9-106531.17" case 1'1 case end @@ -166481,14 +166015,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:106888.3-106942.6" - process $proc$libresoc.v:106888$4188 + attribute \src "libresoc.v:106585.3-106639.6" + process $proc$libresoc.v:106585$4172 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:106889.5-106889.29" + attribute \src "libresoc.v:106586.5-106586.29" switch \initial - attribute \src "libresoc.v:106889.9-106889.17" + attribute \src "libresoc.v:106586.9-106586.17" case 1'1 case end @@ -166564,14 +166098,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] end - attribute \src "libresoc.v:106943.3-106997.6" - process $proc$libresoc.v:106943$4189 + attribute \src "libresoc.v:106640.3-106694.6" + process $proc$libresoc.v:106640$4173 assign { } { } assign { } { } assign $0\dec31_dec_sub22_out_sel[2:0] $1\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:106944.5-106944.29" + attribute \src "libresoc.v:106641.5-106641.29" switch \initial - attribute \src "libresoc.v:106944.9-106944.17" + attribute \src "libresoc.v:106641.9-106641.17" case 1'1 case end @@ -166649,144 +166183,144 @@ module \dec31_dec_sub22 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:107003.1-108970.10" +attribute \src "libresoc.v:106700.1-108667.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" attribute \generator "nMigen" module \dec31_dec_sub23 - attribute \src "libresoc.v:108675.3-108723.6" + attribute \src "libresoc.v:108372.3-108420.6" wire width 2 $0\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:108724.3-108772.6" + attribute \src "libresoc.v:108421.3-108469.6" wire width 2 $0\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:108087.3-108135.6" + attribute \src "libresoc.v:107784.3-107832.6" wire width 8 $0\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:108283.3-108331.6" + attribute \src "libresoc.v:107980.3-108028.6" wire $0\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:107401.3-107449.6" + attribute \src "libresoc.v:107098.3-107146.6" wire width 3 $0\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:107450.3-107498.6" + attribute \src "libresoc.v:107147.3-107195.6" wire width 3 $0\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:108038.3-108086.6" + attribute \src "libresoc.v:107735.3-107783.6" wire width 2 $0\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:108234.3-108282.6" + attribute \src "libresoc.v:107931.3-107979.6" wire $0\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:108430.3-108478.6" + attribute \src "libresoc.v:108127.3-108175.6" wire width 5 $0\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:107352.3-107400.6" + attribute \src "libresoc.v:107049.3-107097.6" wire width 14 $0\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:108773.3-108821.6" + attribute \src "libresoc.v:108470.3-108518.6" wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:108822.3-108870.6" + attribute \src "libresoc.v:108519.3-108567.6" wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:108871.3-108919.6" + attribute \src "libresoc.v:108568.3-108616.6" wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:107891.3-107939.6" + attribute \src "libresoc.v:107588.3-107636.6" wire width 7 $0\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:108136.3-108184.6" + attribute \src "libresoc.v:107833.3-107881.6" wire $0\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:108185.3-108233.6" + attribute \src "libresoc.v:107882.3-107930.6" wire $0\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:108479.3-108527.6" + attribute \src "libresoc.v:108176.3-108224.6" wire $0\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:107842.3-107890.6" + attribute \src "libresoc.v:107539.3-107587.6" wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:108577.3-108625.6" + attribute \src "libresoc.v:108274.3-108322.6" wire $0\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:108920.3-108968.6" + attribute \src "libresoc.v:108617.3-108665.6" wire width 3 $0\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:107989.3-108037.6" + attribute \src "libresoc.v:107686.3-107734.6" wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:108381.3-108429.6" + attribute \src "libresoc.v:108078.3-108126.6" wire $0\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:108626.3-108674.6" + attribute \src "libresoc.v:108323.3-108371.6" wire $0\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:108528.3-108576.6" + attribute \src "libresoc.v:108225.3-108273.6" wire $0\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:108332.3-108380.6" + attribute \src "libresoc.v:108029.3-108077.6" wire $0\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:107744.3-107792.6" + attribute \src "libresoc.v:107441.3-107489.6" wire width 3 $0\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:107793.3-107841.6" + attribute \src "libresoc.v:107490.3-107538.6" wire width 3 $0\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:107499.3-107547.6" + attribute \src "libresoc.v:107196.3-107244.6" wire width 3 $0\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:107548.3-107596.6" + attribute \src "libresoc.v:107245.3-107293.6" wire width 3 $0\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:107597.3-107645.6" + attribute \src "libresoc.v:107294.3-107342.6" wire width 3 $0\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:107695.3-107743.6" + attribute \src "libresoc.v:107392.3-107440.6" wire width 3 $0\dec31_dec_sub23_sv_out2[2:0] - attribute \src "libresoc.v:107646.3-107694.6" + attribute \src "libresoc.v:107343.3-107391.6" wire width 3 $0\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:107940.3-107988.6" + attribute \src "libresoc.v:107637.3-107685.6" wire width 2 $0\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:107004.7-107004.20" + attribute \src "libresoc.v:106701.7-106701.20" wire $0\initial[0:0] - attribute \src "libresoc.v:108675.3-108723.6" + attribute \src "libresoc.v:108372.3-108420.6" wire width 2 $1\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:108724.3-108772.6" + attribute \src "libresoc.v:108421.3-108469.6" wire width 2 $1\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:108087.3-108135.6" + attribute \src "libresoc.v:107784.3-107832.6" wire width 8 $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:108283.3-108331.6" + attribute \src "libresoc.v:107980.3-108028.6" wire $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:107401.3-107449.6" + attribute \src "libresoc.v:107098.3-107146.6" wire width 3 $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:107450.3-107498.6" + attribute \src "libresoc.v:107147.3-107195.6" wire width 3 $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:108038.3-108086.6" + attribute \src "libresoc.v:107735.3-107783.6" wire width 2 $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:108234.3-108282.6" + attribute \src "libresoc.v:107931.3-107979.6" wire $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:108430.3-108478.6" + attribute \src "libresoc.v:108127.3-108175.6" wire width 5 $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:107352.3-107400.6" + attribute \src "libresoc.v:107049.3-107097.6" wire width 14 $1\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:108773.3-108821.6" + attribute \src "libresoc.v:108470.3-108518.6" wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:108822.3-108870.6" + attribute \src "libresoc.v:108519.3-108567.6" wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:108871.3-108919.6" + attribute \src "libresoc.v:108568.3-108616.6" wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:107891.3-107939.6" + attribute \src "libresoc.v:107588.3-107636.6" wire width 7 $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:108136.3-108184.6" + attribute \src "libresoc.v:107833.3-107881.6" wire $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:108185.3-108233.6" + attribute \src "libresoc.v:107882.3-107930.6" wire $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:108479.3-108527.6" + attribute \src "libresoc.v:108176.3-108224.6" wire $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:107842.3-107890.6" + attribute \src "libresoc.v:107539.3-107587.6" wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:108577.3-108625.6" + attribute \src "libresoc.v:108274.3-108322.6" wire $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:108920.3-108968.6" + attribute \src "libresoc.v:108617.3-108665.6" wire width 3 $1\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:107989.3-108037.6" + attribute \src "libresoc.v:107686.3-107734.6" wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:108381.3-108429.6" + attribute \src "libresoc.v:108078.3-108126.6" wire $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:108626.3-108674.6" + attribute \src "libresoc.v:108323.3-108371.6" wire $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:108528.3-108576.6" + attribute \src "libresoc.v:108225.3-108273.6" wire $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:108332.3-108380.6" + attribute \src "libresoc.v:108029.3-108077.6" wire $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:107744.3-107792.6" + attribute \src "libresoc.v:107441.3-107489.6" wire width 3 $1\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:107793.3-107841.6" + attribute \src "libresoc.v:107490.3-107538.6" wire width 3 $1\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:107499.3-107547.6" + attribute \src "libresoc.v:107196.3-107244.6" wire width 3 $1\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:107548.3-107596.6" + attribute \src "libresoc.v:107245.3-107293.6" wire width 3 $1\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:107597.3-107645.6" + attribute \src "libresoc.v:107294.3-107342.6" wire width 3 $1\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:107695.3-107743.6" + attribute \src "libresoc.v:107392.3-107440.6" wire width 3 $1\dec31_dec_sub23_sv_out2[2:0] - attribute \src "libresoc.v:107646.3-107694.6" + attribute \src "libresoc.v:107343.3-107391.6" wire width 3 $1\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:107940.3-107988.6" + attribute \src "libresoc.v:107637.3-107685.6" wire width 2 $1\dec31_dec_sub23_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -167098,28 +166632,28 @@ module \dec31_dec_sub23 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub23_upd - attribute \src "libresoc.v:107004.7-107004.15" + attribute \src "libresoc.v:106701.7-106701.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:107004.7-107004.20" - process $proc$libresoc.v:107004$4224 + attribute \src "libresoc.v:106701.7-106701.20" + process $proc$libresoc.v:106701$4208 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:107352.3-107400.6" - process $proc$libresoc.v:107352$4191 + attribute \src "libresoc.v:107049.3-107097.6" + process $proc$libresoc.v:107049$4175 assign { } { } assign { } { } assign $0\dec31_dec_sub23_function_unit[13:0] $1\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:107353.5-107353.29" + attribute \src "libresoc.v:107050.5-107050.29" switch \initial - attribute \src "libresoc.v:107353.9-107353.17" + attribute \src "libresoc.v:107050.9-107050.17" case 1'1 case end @@ -167187,14 +166721,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[13:0] end - attribute \src "libresoc.v:107401.3-107449.6" - process $proc$libresoc.v:107401$4192 + attribute \src "libresoc.v:107098.3-107146.6" + process $proc$libresoc.v:107098$4176 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:107402.5-107402.29" + attribute \src "libresoc.v:107099.5-107099.29" switch \initial - attribute \src "libresoc.v:107402.9-107402.17" + attribute \src "libresoc.v:107099.9-107099.17" case 1'1 case end @@ -167262,14 +166796,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] end - attribute \src "libresoc.v:107450.3-107498.6" - process $proc$libresoc.v:107450$4193 + attribute \src "libresoc.v:107147.3-107195.6" + process $proc$libresoc.v:107147$4177 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:107451.5-107451.29" + attribute \src "libresoc.v:107148.5-107148.29" switch \initial - attribute \src "libresoc.v:107451.9-107451.17" + attribute \src "libresoc.v:107148.9-107148.17" case 1'1 case end @@ -167337,14 +166871,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] end - attribute \src "libresoc.v:107499.3-107547.6" - process $proc$libresoc.v:107499$4194 + attribute \src "libresoc.v:107196.3-107244.6" + process $proc$libresoc.v:107196$4178 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in1[2:0] $1\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:107500.5-107500.29" + attribute \src "libresoc.v:107197.5-107197.29" switch \initial - attribute \src "libresoc.v:107500.9-107500.17" + attribute \src "libresoc.v:107197.9-107197.17" case 1'1 case end @@ -167412,14 +166946,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in1 $0\dec31_dec_sub23_sv_in1[2:0] end - attribute \src "libresoc.v:107548.3-107596.6" - process $proc$libresoc.v:107548$4195 + attribute \src "libresoc.v:107245.3-107293.6" + process $proc$libresoc.v:107245$4179 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in2[2:0] $1\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:107549.5-107549.29" + attribute \src "libresoc.v:107246.5-107246.29" switch \initial - attribute \src "libresoc.v:107549.9-107549.17" + attribute \src "libresoc.v:107246.9-107246.17" case 1'1 case end @@ -167487,14 +167021,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in2 $0\dec31_dec_sub23_sv_in2[2:0] end - attribute \src "libresoc.v:107597.3-107645.6" - process $proc$libresoc.v:107597$4196 + attribute \src "libresoc.v:107294.3-107342.6" + process $proc$libresoc.v:107294$4180 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in3[2:0] $1\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:107598.5-107598.29" + attribute \src "libresoc.v:107295.5-107295.29" switch \initial - attribute \src "libresoc.v:107598.9-107598.17" + attribute \src "libresoc.v:107295.9-107295.17" case 1'1 case end @@ -167562,14 +167096,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in3 $0\dec31_dec_sub23_sv_in3[2:0] end - attribute \src "libresoc.v:107646.3-107694.6" - process $proc$libresoc.v:107646$4197 + attribute \src "libresoc.v:107343.3-107391.6" + process $proc$libresoc.v:107343$4181 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_out[2:0] $1\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:107647.5-107647.29" + attribute \src "libresoc.v:107344.5-107344.29" switch \initial - attribute \src "libresoc.v:107647.9-107647.17" + attribute \src "libresoc.v:107344.9-107344.17" case 1'1 case end @@ -167637,14 +167171,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_out $0\dec31_dec_sub23_sv_out[2:0] end - attribute \src "libresoc.v:107695.3-107743.6" - process $proc$libresoc.v:107695$4198 + attribute \src "libresoc.v:107392.3-107440.6" + process $proc$libresoc.v:107392$4182 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_out2[2:0] $1\dec31_dec_sub23_sv_out2[2:0] - attribute \src "libresoc.v:107696.5-107696.29" + attribute \src "libresoc.v:107393.5-107393.29" switch \initial - attribute \src "libresoc.v:107696.9-107696.17" + attribute \src "libresoc.v:107393.9-107393.17" case 1'1 case end @@ -167712,14 +167246,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_out2 $0\dec31_dec_sub23_sv_out2[2:0] end - attribute \src "libresoc.v:107744.3-107792.6" - process $proc$libresoc.v:107744$4199 + attribute \src "libresoc.v:107441.3-107489.6" + process $proc$libresoc.v:107441$4183 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_in[2:0] $1\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:107745.5-107745.29" + attribute \src "libresoc.v:107442.5-107442.29" switch \initial - attribute \src "libresoc.v:107745.9-107745.17" + attribute \src "libresoc.v:107442.9-107442.17" case 1'1 case end @@ -167787,14 +167321,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_cr_in $0\dec31_dec_sub23_sv_cr_in[2:0] end - attribute \src "libresoc.v:107793.3-107841.6" - process $proc$libresoc.v:107793$4200 + attribute \src "libresoc.v:107490.3-107538.6" + process $proc$libresoc.v:107490$4184 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_out[2:0] $1\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:107794.5-107794.29" + attribute \src "libresoc.v:107491.5-107491.29" switch \initial - attribute \src "libresoc.v:107794.9-107794.17" + attribute \src "libresoc.v:107491.9-107491.17" case 1'1 case end @@ -167862,14 +167396,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_cr_out $0\dec31_dec_sub23_sv_cr_out[2:0] end - attribute \src "libresoc.v:107842.3-107890.6" - process $proc$libresoc.v:107842$4201 + attribute \src "libresoc.v:107539.3-107587.6" + process $proc$libresoc.v:107539$4185 assign { } { } assign { } { } assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:107843.5-107843.29" + attribute \src "libresoc.v:107540.5-107540.29" switch \initial - attribute \src "libresoc.v:107843.9-107843.17" + attribute \src "libresoc.v:107540.9-107540.17" case 1'1 case end @@ -167937,14 +167471,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] end - attribute \src "libresoc.v:107891.3-107939.6" - process $proc$libresoc.v:107891$4202 + attribute \src "libresoc.v:107588.3-107636.6" + process $proc$libresoc.v:107588$4186 assign { } { } assign { } { } assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:107892.5-107892.29" + attribute \src "libresoc.v:107589.5-107589.29" switch \initial - attribute \src "libresoc.v:107892.9-107892.17" + attribute \src "libresoc.v:107589.9-107589.17" case 1'1 case end @@ -168012,14 +167546,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] end - attribute \src "libresoc.v:107940.3-107988.6" - process $proc$libresoc.v:107940$4203 + attribute \src "libresoc.v:107637.3-107685.6" + process $proc$libresoc.v:107637$4187 assign { } { } assign { } { } assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:107941.5-107941.29" + attribute \src "libresoc.v:107638.5-107638.29" switch \initial - attribute \src "libresoc.v:107941.9-107941.17" + attribute \src "libresoc.v:107638.9-107638.17" case 1'1 case end @@ -168087,14 +167621,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] end - attribute \src "libresoc.v:107989.3-108037.6" - process $proc$libresoc.v:107989$4204 + attribute \src "libresoc.v:107686.3-107734.6" + process $proc$libresoc.v:107686$4188 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:107990.5-107990.29" + attribute \src "libresoc.v:107687.5-107687.29" switch \initial - attribute \src "libresoc.v:107990.9-107990.17" + attribute \src "libresoc.v:107687.9-107687.17" case 1'1 case end @@ -168162,14 +167696,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] end - attribute \src "libresoc.v:108038.3-108086.6" - process $proc$libresoc.v:108038$4205 + attribute \src "libresoc.v:107735.3-107783.6" + process $proc$libresoc.v:107735$4189 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:108039.5-108039.29" + attribute \src "libresoc.v:107736.5-107736.29" switch \initial - attribute \src "libresoc.v:108039.9-108039.17" + attribute \src "libresoc.v:107736.9-107736.17" case 1'1 case end @@ -168237,14 +167771,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] end - attribute \src "libresoc.v:108087.3-108135.6" - process $proc$libresoc.v:108087$4206 + attribute \src "libresoc.v:107784.3-107832.6" + process $proc$libresoc.v:107784$4190 assign { } { } assign { } { } assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:108088.5-108088.29" + attribute \src "libresoc.v:107785.5-107785.29" switch \initial - attribute \src "libresoc.v:108088.9-108088.17" + attribute \src "libresoc.v:107785.9-107785.17" case 1'1 case end @@ -168312,14 +167846,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] end - attribute \src "libresoc.v:108136.3-108184.6" - process $proc$libresoc.v:108136$4207 + attribute \src "libresoc.v:107833.3-107881.6" + process $proc$libresoc.v:107833$4191 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:108137.5-108137.29" + attribute \src "libresoc.v:107834.5-107834.29" switch \initial - attribute \src "libresoc.v:108137.9-108137.17" + attribute \src "libresoc.v:107834.9-107834.17" case 1'1 case end @@ -168387,14 +167921,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] end - attribute \src "libresoc.v:108185.3-108233.6" - process $proc$libresoc.v:108185$4208 + attribute \src "libresoc.v:107882.3-107930.6" + process $proc$libresoc.v:107882$4192 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:108186.5-108186.29" + attribute \src "libresoc.v:107883.5-107883.29" switch \initial - attribute \src "libresoc.v:108186.9-108186.17" + attribute \src "libresoc.v:107883.9-107883.17" case 1'1 case end @@ -168462,14 +167996,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] end - attribute \src "libresoc.v:108234.3-108282.6" - process $proc$libresoc.v:108234$4209 + attribute \src "libresoc.v:107931.3-107979.6" + process $proc$libresoc.v:107931$4193 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:108235.5-108235.29" + attribute \src "libresoc.v:107932.5-107932.29" switch \initial - attribute \src "libresoc.v:108235.9-108235.17" + attribute \src "libresoc.v:107932.9-107932.17" case 1'1 case end @@ -168537,14 +168071,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] end - attribute \src "libresoc.v:108283.3-108331.6" - process $proc$libresoc.v:108283$4210 + attribute \src "libresoc.v:107980.3-108028.6" + process $proc$libresoc.v:107980$4194 assign { } { } assign { } { } assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:108284.5-108284.29" + attribute \src "libresoc.v:107981.5-107981.29" switch \initial - attribute \src "libresoc.v:108284.9-108284.17" + attribute \src "libresoc.v:107981.9-107981.17" case 1'1 case end @@ -168612,14 +168146,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] end - attribute \src "libresoc.v:108332.3-108380.6" - process $proc$libresoc.v:108332$4211 + attribute \src "libresoc.v:108029.3-108077.6" + process $proc$libresoc.v:108029$4195 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:108333.5-108333.29" + attribute \src "libresoc.v:108030.5-108030.29" switch \initial - attribute \src "libresoc.v:108333.9-108333.17" + attribute \src "libresoc.v:108030.9-108030.17" case 1'1 case end @@ -168687,14 +168221,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] end - attribute \src "libresoc.v:108381.3-108429.6" - process $proc$libresoc.v:108381$4212 + attribute \src "libresoc.v:108078.3-108126.6" + process $proc$libresoc.v:108078$4196 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:108382.5-108382.29" + attribute \src "libresoc.v:108079.5-108079.29" switch \initial - attribute \src "libresoc.v:108382.9-108382.17" + attribute \src "libresoc.v:108079.9-108079.17" case 1'1 case end @@ -168762,14 +168296,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] end - attribute \src "libresoc.v:108430.3-108478.6" - process $proc$libresoc.v:108430$4213 + attribute \src "libresoc.v:108127.3-108175.6" + process $proc$libresoc.v:108127$4197 assign { } { } assign { } { } assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:108431.5-108431.29" + attribute \src "libresoc.v:108128.5-108128.29" switch \initial - attribute \src "libresoc.v:108431.9-108431.17" + attribute \src "libresoc.v:108128.9-108128.17" case 1'1 case end @@ -168837,14 +168371,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] end - attribute \src "libresoc.v:108479.3-108527.6" - process $proc$libresoc.v:108479$4214 + attribute \src "libresoc.v:108176.3-108224.6" + process $proc$libresoc.v:108176$4198 assign { } { } assign { } { } assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:108480.5-108480.29" + attribute \src "libresoc.v:108177.5-108177.29" switch \initial - attribute \src "libresoc.v:108480.9-108480.17" + attribute \src "libresoc.v:108177.9-108177.17" case 1'1 case end @@ -168912,14 +168446,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] end - attribute \src "libresoc.v:108528.3-108576.6" - process $proc$libresoc.v:108528$4215 + attribute \src "libresoc.v:108225.3-108273.6" + process $proc$libresoc.v:108225$4199 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:108529.5-108529.29" + attribute \src "libresoc.v:108226.5-108226.29" switch \initial - attribute \src "libresoc.v:108529.9-108529.17" + attribute \src "libresoc.v:108226.9-108226.17" case 1'1 case end @@ -168987,14 +168521,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] end - attribute \src "libresoc.v:108577.3-108625.6" - process $proc$libresoc.v:108577$4216 + attribute \src "libresoc.v:108274.3-108322.6" + process $proc$libresoc.v:108274$4200 assign { } { } assign { } { } assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:108578.5-108578.29" + attribute \src "libresoc.v:108275.5-108275.29" switch \initial - attribute \src "libresoc.v:108578.9-108578.17" + attribute \src "libresoc.v:108275.9-108275.17" case 1'1 case end @@ -169062,14 +168596,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] end - attribute \src "libresoc.v:108626.3-108674.6" - process $proc$libresoc.v:108626$4217 + attribute \src "libresoc.v:108323.3-108371.6" + process $proc$libresoc.v:108323$4201 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:108627.5-108627.29" + attribute \src "libresoc.v:108324.5-108324.29" switch \initial - attribute \src "libresoc.v:108627.9-108627.17" + attribute \src "libresoc.v:108324.9-108324.17" case 1'1 case end @@ -169137,14 +168671,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] end - attribute \src "libresoc.v:108675.3-108723.6" - process $proc$libresoc.v:108675$4218 + attribute \src "libresoc.v:108372.3-108420.6" + process $proc$libresoc.v:108372$4202 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Etype[1:0] $1\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:108676.5-108676.29" + attribute \src "libresoc.v:108373.5-108373.29" switch \initial - attribute \src "libresoc.v:108676.9-108676.17" + attribute \src "libresoc.v:108373.9-108373.17" case 1'1 case end @@ -169212,14 +168746,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_SV_Etype $0\dec31_dec_sub23_SV_Etype[1:0] end - attribute \src "libresoc.v:108724.3-108772.6" - process $proc$libresoc.v:108724$4219 + attribute \src "libresoc.v:108421.3-108469.6" + process $proc$libresoc.v:108421$4203 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Ptype[1:0] $1\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:108725.5-108725.29" + attribute \src "libresoc.v:108422.5-108422.29" switch \initial - attribute \src "libresoc.v:108725.9-108725.17" + attribute \src "libresoc.v:108422.9-108422.17" case 1'1 case end @@ -169287,14 +168821,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_SV_Ptype $0\dec31_dec_sub23_SV_Ptype[1:0] end - attribute \src "libresoc.v:108773.3-108821.6" - process $proc$libresoc.v:108773$4220 + attribute \src "libresoc.v:108470.3-108518.6" + process $proc$libresoc.v:108470$4204 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:108774.5-108774.29" + attribute \src "libresoc.v:108471.5-108471.29" switch \initial - attribute \src "libresoc.v:108774.9-108774.17" + attribute \src "libresoc.v:108471.9-108471.17" case 1'1 case end @@ -169362,14 +168896,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] end - attribute \src "libresoc.v:108822.3-108870.6" - process $proc$libresoc.v:108822$4221 + attribute \src "libresoc.v:108519.3-108567.6" + process $proc$libresoc.v:108519$4205 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:108823.5-108823.29" + attribute \src "libresoc.v:108520.5-108520.29" switch \initial - attribute \src "libresoc.v:108823.9-108823.17" + attribute \src "libresoc.v:108520.9-108520.17" case 1'1 case end @@ -169437,14 +168971,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] end - attribute \src "libresoc.v:108871.3-108919.6" - process $proc$libresoc.v:108871$4222 + attribute \src "libresoc.v:108568.3-108616.6" + process $proc$libresoc.v:108568$4206 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:108872.5-108872.29" + attribute \src "libresoc.v:108569.5-108569.29" switch \initial - attribute \src "libresoc.v:108872.9-108872.17" + attribute \src "libresoc.v:108569.9-108569.17" case 1'1 case end @@ -169512,14 +169046,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] end - attribute \src "libresoc.v:108920.3-108968.6" - process $proc$libresoc.v:108920$4223 + attribute \src "libresoc.v:108617.3-108665.6" + process $proc$libresoc.v:108617$4207 assign { } { } assign { } { } assign $0\dec31_dec_sub23_out_sel[2:0] $1\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:108921.5-108921.29" + attribute \src "libresoc.v:108618.5-108618.29" switch \initial - attribute \src "libresoc.v:108921.9-108921.17" + attribute \src "libresoc.v:108618.9-108618.17" case 1'1 case end @@ -169589,144 +169123,144 @@ module \dec31_dec_sub23 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:108974.1-109951.10" +attribute \src "libresoc.v:108671.1-109648.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" attribute \generator "nMigen" module \dec31_dec_sub24 - attribute \src "libresoc.v:109836.3-109854.6" + attribute \src "libresoc.v:109533.3-109551.6" wire width 2 $0\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:109855.3-109873.6" + attribute \src "libresoc.v:109552.3-109570.6" wire width 2 $0\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:109608.3-109626.6" + attribute \src "libresoc.v:109305.3-109323.6" wire width 8 $0\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:109684.3-109702.6" + attribute \src "libresoc.v:109381.3-109399.6" wire $0\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:109342.3-109360.6" + attribute \src "libresoc.v:109039.3-109057.6" wire width 3 $0\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:109361.3-109379.6" + attribute \src "libresoc.v:109058.3-109076.6" wire width 3 $0\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:109589.3-109607.6" + attribute \src "libresoc.v:109286.3-109304.6" wire width 2 $0\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:109665.3-109683.6" + attribute \src "libresoc.v:109362.3-109380.6" wire $0\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:109741.3-109759.6" + attribute \src "libresoc.v:109438.3-109456.6" wire width 5 $0\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:109323.3-109341.6" + attribute \src "libresoc.v:109020.3-109038.6" wire width 14 $0\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:109874.3-109892.6" + attribute \src "libresoc.v:109571.3-109589.6" wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:109893.3-109911.6" + attribute \src "libresoc.v:109590.3-109608.6" wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:109912.3-109930.6" + attribute \src "libresoc.v:109609.3-109627.6" wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:109532.3-109550.6" + attribute \src "libresoc.v:109229.3-109247.6" wire width 7 $0\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:109627.3-109645.6" + attribute \src "libresoc.v:109324.3-109342.6" wire $0\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:109646.3-109664.6" + attribute \src "libresoc.v:109343.3-109361.6" wire $0\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:109760.3-109778.6" + attribute \src "libresoc.v:109457.3-109475.6" wire $0\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:109513.3-109531.6" + attribute \src "libresoc.v:109210.3-109228.6" wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:109798.3-109816.6" + attribute \src "libresoc.v:109495.3-109513.6" wire $0\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:109931.3-109949.6" + attribute \src "libresoc.v:109628.3-109646.6" wire width 3 $0\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:109570.3-109588.6" + attribute \src "libresoc.v:109267.3-109285.6" wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:109722.3-109740.6" + attribute \src "libresoc.v:109419.3-109437.6" wire $0\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:109817.3-109835.6" + attribute \src "libresoc.v:109514.3-109532.6" wire $0\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:109779.3-109797.6" + attribute \src "libresoc.v:109476.3-109494.6" wire $0\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:109703.3-109721.6" + attribute \src "libresoc.v:109400.3-109418.6" wire $0\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:109475.3-109493.6" + attribute \src "libresoc.v:109172.3-109190.6" wire width 3 $0\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:109494.3-109512.6" + attribute \src "libresoc.v:109191.3-109209.6" wire width 3 $0\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:109380.3-109398.6" + attribute \src "libresoc.v:109077.3-109095.6" wire width 3 $0\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:109399.3-109417.6" + attribute \src "libresoc.v:109096.3-109114.6" wire width 3 $0\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:109418.3-109436.6" + attribute \src "libresoc.v:109115.3-109133.6" wire width 3 $0\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:109456.3-109474.6" + attribute \src "libresoc.v:109153.3-109171.6" wire width 3 $0\dec31_dec_sub24_sv_out2[2:0] - attribute \src "libresoc.v:109437.3-109455.6" + attribute \src "libresoc.v:109134.3-109152.6" wire width 3 $0\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:109551.3-109569.6" + attribute \src "libresoc.v:109248.3-109266.6" wire width 2 $0\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:108975.7-108975.20" + attribute \src "libresoc.v:108672.7-108672.20" wire $0\initial[0:0] - attribute \src "libresoc.v:109836.3-109854.6" + attribute \src "libresoc.v:109533.3-109551.6" wire width 2 $1\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:109855.3-109873.6" + attribute \src "libresoc.v:109552.3-109570.6" wire width 2 $1\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:109608.3-109626.6" + attribute \src "libresoc.v:109305.3-109323.6" wire width 8 $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:109684.3-109702.6" + attribute \src "libresoc.v:109381.3-109399.6" wire $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:109342.3-109360.6" + attribute \src "libresoc.v:109039.3-109057.6" wire width 3 $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:109361.3-109379.6" + attribute \src "libresoc.v:109058.3-109076.6" wire width 3 $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:109589.3-109607.6" + attribute \src "libresoc.v:109286.3-109304.6" wire width 2 $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:109665.3-109683.6" + attribute \src "libresoc.v:109362.3-109380.6" wire $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:109741.3-109759.6" + attribute \src "libresoc.v:109438.3-109456.6" wire width 5 $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:109323.3-109341.6" + attribute \src "libresoc.v:109020.3-109038.6" wire width 14 $1\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:109874.3-109892.6" + attribute \src "libresoc.v:109571.3-109589.6" wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:109893.3-109911.6" + attribute \src "libresoc.v:109590.3-109608.6" wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:109912.3-109930.6" + attribute \src "libresoc.v:109609.3-109627.6" wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:109532.3-109550.6" + attribute \src "libresoc.v:109229.3-109247.6" wire width 7 $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:109627.3-109645.6" + attribute \src "libresoc.v:109324.3-109342.6" wire $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:109646.3-109664.6" + attribute \src "libresoc.v:109343.3-109361.6" wire $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:109760.3-109778.6" + attribute \src "libresoc.v:109457.3-109475.6" wire $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:109513.3-109531.6" + attribute \src "libresoc.v:109210.3-109228.6" wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:109798.3-109816.6" + attribute \src "libresoc.v:109495.3-109513.6" wire $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:109931.3-109949.6" + attribute \src "libresoc.v:109628.3-109646.6" wire width 3 $1\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:109570.3-109588.6" + attribute \src "libresoc.v:109267.3-109285.6" wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:109722.3-109740.6" + attribute \src "libresoc.v:109419.3-109437.6" wire $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:109817.3-109835.6" + attribute \src "libresoc.v:109514.3-109532.6" wire $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:109779.3-109797.6" + attribute \src "libresoc.v:109476.3-109494.6" wire $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:109703.3-109721.6" + attribute \src "libresoc.v:109400.3-109418.6" wire $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:109475.3-109493.6" + attribute \src "libresoc.v:109172.3-109190.6" wire width 3 $1\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:109494.3-109512.6" + attribute \src "libresoc.v:109191.3-109209.6" wire width 3 $1\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:109380.3-109398.6" + attribute \src "libresoc.v:109077.3-109095.6" wire width 3 $1\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:109399.3-109417.6" + attribute \src "libresoc.v:109096.3-109114.6" wire width 3 $1\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:109418.3-109436.6" + attribute \src "libresoc.v:109115.3-109133.6" wire width 3 $1\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:109456.3-109474.6" + attribute \src "libresoc.v:109153.3-109171.6" wire width 3 $1\dec31_dec_sub24_sv_out2[2:0] - attribute \src "libresoc.v:109437.3-109455.6" + attribute \src "libresoc.v:109134.3-109152.6" wire width 3 $1\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:109551.3-109569.6" + attribute \src "libresoc.v:109248.3-109266.6" wire width 2 $1\dec31_dec_sub24_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -170038,28 +169572,28 @@ module \dec31_dec_sub24 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub24_upd - attribute \src "libresoc.v:108975.7-108975.15" + attribute \src "libresoc.v:108672.7-108672.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:108975.7-108975.20" - process $proc$libresoc.v:108975$4258 + attribute \src "libresoc.v:108672.7-108672.20" + process $proc$libresoc.v:108672$4242 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:109323.3-109341.6" - process $proc$libresoc.v:109323$4225 + attribute \src "libresoc.v:109020.3-109038.6" + process $proc$libresoc.v:109020$4209 assign { } { } assign { } { } assign $0\dec31_dec_sub24_function_unit[13:0] $1\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:109324.5-109324.29" + attribute \src "libresoc.v:109021.5-109021.29" switch \initial - attribute \src "libresoc.v:109324.9-109324.17" + attribute \src "libresoc.v:109021.9-109021.17" case 1'1 case end @@ -170087,14 +169621,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[13:0] end - attribute \src "libresoc.v:109342.3-109360.6" - process $proc$libresoc.v:109342$4226 + attribute \src "libresoc.v:109039.3-109057.6" + process $proc$libresoc.v:109039$4210 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:109343.5-109343.29" + attribute \src "libresoc.v:109040.5-109040.29" switch \initial - attribute \src "libresoc.v:109343.9-109343.17" + attribute \src "libresoc.v:109040.9-109040.17" case 1'1 case end @@ -170122,14 +169656,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] end - attribute \src "libresoc.v:109361.3-109379.6" - process $proc$libresoc.v:109361$4227 + attribute \src "libresoc.v:109058.3-109076.6" + process $proc$libresoc.v:109058$4211 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:109362.5-109362.29" + attribute \src "libresoc.v:109059.5-109059.29" switch \initial - attribute \src "libresoc.v:109362.9-109362.17" + attribute \src "libresoc.v:109059.9-109059.17" case 1'1 case end @@ -170157,14 +169691,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] end - attribute \src "libresoc.v:109380.3-109398.6" - process $proc$libresoc.v:109380$4228 + attribute \src "libresoc.v:109077.3-109095.6" + process $proc$libresoc.v:109077$4212 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in1[2:0] $1\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:109381.5-109381.29" + attribute \src "libresoc.v:109078.5-109078.29" switch \initial - attribute \src "libresoc.v:109381.9-109381.17" + attribute \src "libresoc.v:109078.9-109078.17" case 1'1 case end @@ -170192,14 +169726,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in1 $0\dec31_dec_sub24_sv_in1[2:0] end - attribute \src "libresoc.v:109399.3-109417.6" - process $proc$libresoc.v:109399$4229 + attribute \src "libresoc.v:109096.3-109114.6" + process $proc$libresoc.v:109096$4213 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in2[2:0] $1\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:109400.5-109400.29" + attribute \src "libresoc.v:109097.5-109097.29" switch \initial - attribute \src "libresoc.v:109400.9-109400.17" + attribute \src "libresoc.v:109097.9-109097.17" case 1'1 case end @@ -170227,14 +169761,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in2 $0\dec31_dec_sub24_sv_in2[2:0] end - attribute \src "libresoc.v:109418.3-109436.6" - process $proc$libresoc.v:109418$4230 + attribute \src "libresoc.v:109115.3-109133.6" + process $proc$libresoc.v:109115$4214 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in3[2:0] $1\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:109419.5-109419.29" + attribute \src "libresoc.v:109116.5-109116.29" switch \initial - attribute \src "libresoc.v:109419.9-109419.17" + attribute \src "libresoc.v:109116.9-109116.17" case 1'1 case end @@ -170262,14 +169796,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in3 $0\dec31_dec_sub24_sv_in3[2:0] end - attribute \src "libresoc.v:109437.3-109455.6" - process $proc$libresoc.v:109437$4231 + attribute \src "libresoc.v:109134.3-109152.6" + process $proc$libresoc.v:109134$4215 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_out[2:0] $1\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:109438.5-109438.29" + attribute \src "libresoc.v:109135.5-109135.29" switch \initial - attribute \src "libresoc.v:109438.9-109438.17" + attribute \src "libresoc.v:109135.9-109135.17" case 1'1 case end @@ -170297,14 +169831,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_out $0\dec31_dec_sub24_sv_out[2:0] end - attribute \src "libresoc.v:109456.3-109474.6" - process $proc$libresoc.v:109456$4232 + attribute \src "libresoc.v:109153.3-109171.6" + process $proc$libresoc.v:109153$4216 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_out2[2:0] $1\dec31_dec_sub24_sv_out2[2:0] - attribute \src "libresoc.v:109457.5-109457.29" + attribute \src "libresoc.v:109154.5-109154.29" switch \initial - attribute \src "libresoc.v:109457.9-109457.17" + attribute \src "libresoc.v:109154.9-109154.17" case 1'1 case end @@ -170332,14 +169866,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_out2 $0\dec31_dec_sub24_sv_out2[2:0] end - attribute \src "libresoc.v:109475.3-109493.6" - process $proc$libresoc.v:109475$4233 + attribute \src "libresoc.v:109172.3-109190.6" + process $proc$libresoc.v:109172$4217 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_in[2:0] $1\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:109476.5-109476.29" + attribute \src "libresoc.v:109173.5-109173.29" switch \initial - attribute \src "libresoc.v:109476.9-109476.17" + attribute \src "libresoc.v:109173.9-109173.17" case 1'1 case end @@ -170367,14 +169901,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_cr_in $0\dec31_dec_sub24_sv_cr_in[2:0] end - attribute \src "libresoc.v:109494.3-109512.6" - process $proc$libresoc.v:109494$4234 + attribute \src "libresoc.v:109191.3-109209.6" + process $proc$libresoc.v:109191$4218 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_out[2:0] $1\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:109495.5-109495.29" + attribute \src "libresoc.v:109192.5-109192.29" switch \initial - attribute \src "libresoc.v:109495.9-109495.17" + attribute \src "libresoc.v:109192.9-109192.17" case 1'1 case end @@ -170402,14 +169936,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_cr_out $0\dec31_dec_sub24_sv_cr_out[2:0] end - attribute \src "libresoc.v:109513.3-109531.6" - process $proc$libresoc.v:109513$4235 + attribute \src "libresoc.v:109210.3-109228.6" + process $proc$libresoc.v:109210$4219 assign { } { } assign { } { } assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:109514.5-109514.29" + attribute \src "libresoc.v:109211.5-109211.29" switch \initial - attribute \src "libresoc.v:109514.9-109514.17" + attribute \src "libresoc.v:109211.9-109211.17" case 1'1 case end @@ -170437,14 +169971,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] end - attribute \src "libresoc.v:109532.3-109550.6" - process $proc$libresoc.v:109532$4236 + attribute \src "libresoc.v:109229.3-109247.6" + process $proc$libresoc.v:109229$4220 assign { } { } assign { } { } assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:109533.5-109533.29" + attribute \src "libresoc.v:109230.5-109230.29" switch \initial - attribute \src "libresoc.v:109533.9-109533.17" + attribute \src "libresoc.v:109230.9-109230.17" case 1'1 case end @@ -170472,14 +170006,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] end - attribute \src "libresoc.v:109551.3-109569.6" - process $proc$libresoc.v:109551$4237 + attribute \src "libresoc.v:109248.3-109266.6" + process $proc$libresoc.v:109248$4221 assign { } { } assign { } { } assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:109552.5-109552.29" + attribute \src "libresoc.v:109249.5-109249.29" switch \initial - attribute \src "libresoc.v:109552.9-109552.17" + attribute \src "libresoc.v:109249.9-109249.17" case 1'1 case end @@ -170507,14 +170041,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] end - attribute \src "libresoc.v:109570.3-109588.6" - process $proc$libresoc.v:109570$4238 + attribute \src "libresoc.v:109267.3-109285.6" + process $proc$libresoc.v:109267$4222 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:109571.5-109571.29" + attribute \src "libresoc.v:109268.5-109268.29" switch \initial - attribute \src "libresoc.v:109571.9-109571.17" + attribute \src "libresoc.v:109268.9-109268.17" case 1'1 case end @@ -170542,14 +170076,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] end - attribute \src "libresoc.v:109589.3-109607.6" - process $proc$libresoc.v:109589$4239 + attribute \src "libresoc.v:109286.3-109304.6" + process $proc$libresoc.v:109286$4223 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:109590.5-109590.29" + attribute \src "libresoc.v:109287.5-109287.29" switch \initial - attribute \src "libresoc.v:109590.9-109590.17" + attribute \src "libresoc.v:109287.9-109287.17" case 1'1 case end @@ -170577,14 +170111,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] end - attribute \src "libresoc.v:109608.3-109626.6" - process $proc$libresoc.v:109608$4240 + attribute \src "libresoc.v:109305.3-109323.6" + process $proc$libresoc.v:109305$4224 assign { } { } assign { } { } assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:109609.5-109609.29" + attribute \src "libresoc.v:109306.5-109306.29" switch \initial - attribute \src "libresoc.v:109609.9-109609.17" + attribute \src "libresoc.v:109306.9-109306.17" case 1'1 case end @@ -170612,14 +170146,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] end - attribute \src "libresoc.v:109627.3-109645.6" - process $proc$libresoc.v:109627$4241 + attribute \src "libresoc.v:109324.3-109342.6" + process $proc$libresoc.v:109324$4225 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:109628.5-109628.29" + attribute \src "libresoc.v:109325.5-109325.29" switch \initial - attribute \src "libresoc.v:109628.9-109628.17" + attribute \src "libresoc.v:109325.9-109325.17" case 1'1 case end @@ -170647,14 +170181,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] end - attribute \src "libresoc.v:109646.3-109664.6" - process $proc$libresoc.v:109646$4242 + attribute \src "libresoc.v:109343.3-109361.6" + process $proc$libresoc.v:109343$4226 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:109647.5-109647.29" + attribute \src "libresoc.v:109344.5-109344.29" switch \initial - attribute \src "libresoc.v:109647.9-109647.17" + attribute \src "libresoc.v:109344.9-109344.17" case 1'1 case end @@ -170682,14 +170216,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] end - attribute \src "libresoc.v:109665.3-109683.6" - process $proc$libresoc.v:109665$4243 + attribute \src "libresoc.v:109362.3-109380.6" + process $proc$libresoc.v:109362$4227 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:109666.5-109666.29" + attribute \src "libresoc.v:109363.5-109363.29" switch \initial - attribute \src "libresoc.v:109666.9-109666.17" + attribute \src "libresoc.v:109363.9-109363.17" case 1'1 case end @@ -170717,14 +170251,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] end - attribute \src "libresoc.v:109684.3-109702.6" - process $proc$libresoc.v:109684$4244 + attribute \src "libresoc.v:109381.3-109399.6" + process $proc$libresoc.v:109381$4228 assign { } { } assign { } { } assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:109685.5-109685.29" + attribute \src "libresoc.v:109382.5-109382.29" switch \initial - attribute \src "libresoc.v:109685.9-109685.17" + attribute \src "libresoc.v:109382.9-109382.17" case 1'1 case end @@ -170752,14 +170286,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] end - attribute \src "libresoc.v:109703.3-109721.6" - process $proc$libresoc.v:109703$4245 + attribute \src "libresoc.v:109400.3-109418.6" + process $proc$libresoc.v:109400$4229 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:109704.5-109704.29" + attribute \src "libresoc.v:109401.5-109401.29" switch \initial - attribute \src "libresoc.v:109704.9-109704.17" + attribute \src "libresoc.v:109401.9-109401.17" case 1'1 case end @@ -170787,14 +170321,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] end - attribute \src "libresoc.v:109722.3-109740.6" - process $proc$libresoc.v:109722$4246 + attribute \src "libresoc.v:109419.3-109437.6" + process $proc$libresoc.v:109419$4230 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:109723.5-109723.29" + attribute \src "libresoc.v:109420.5-109420.29" switch \initial - attribute \src "libresoc.v:109723.9-109723.17" + attribute \src "libresoc.v:109420.9-109420.17" case 1'1 case end @@ -170822,14 +170356,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] end - attribute \src "libresoc.v:109741.3-109759.6" - process $proc$libresoc.v:109741$4247 + attribute \src "libresoc.v:109438.3-109456.6" + process $proc$libresoc.v:109438$4231 assign { } { } assign { } { } assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:109742.5-109742.29" + attribute \src "libresoc.v:109439.5-109439.29" switch \initial - attribute \src "libresoc.v:109742.9-109742.17" + attribute \src "libresoc.v:109439.9-109439.17" case 1'1 case end @@ -170857,14 +170391,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] end - attribute \src "libresoc.v:109760.3-109778.6" - process $proc$libresoc.v:109760$4248 + attribute \src "libresoc.v:109457.3-109475.6" + process $proc$libresoc.v:109457$4232 assign { } { } assign { } { } assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:109761.5-109761.29" + attribute \src "libresoc.v:109458.5-109458.29" switch \initial - attribute \src "libresoc.v:109761.9-109761.17" + attribute \src "libresoc.v:109458.9-109458.17" case 1'1 case end @@ -170892,14 +170426,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] end - attribute \src "libresoc.v:109779.3-109797.6" - process $proc$libresoc.v:109779$4249 + attribute \src "libresoc.v:109476.3-109494.6" + process $proc$libresoc.v:109476$4233 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:109780.5-109780.29" + attribute \src "libresoc.v:109477.5-109477.29" switch \initial - attribute \src "libresoc.v:109780.9-109780.17" + attribute \src "libresoc.v:109477.9-109477.17" case 1'1 case end @@ -170927,14 +170461,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] end - attribute \src "libresoc.v:109798.3-109816.6" - process $proc$libresoc.v:109798$4250 + attribute \src "libresoc.v:109495.3-109513.6" + process $proc$libresoc.v:109495$4234 assign { } { } assign { } { } assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:109799.5-109799.29" + attribute \src "libresoc.v:109496.5-109496.29" switch \initial - attribute \src "libresoc.v:109799.9-109799.17" + attribute \src "libresoc.v:109496.9-109496.17" case 1'1 case end @@ -170962,14 +170496,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] end - attribute \src "libresoc.v:109817.3-109835.6" - process $proc$libresoc.v:109817$4251 + attribute \src "libresoc.v:109514.3-109532.6" + process $proc$libresoc.v:109514$4235 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:109818.5-109818.29" + attribute \src "libresoc.v:109515.5-109515.29" switch \initial - attribute \src "libresoc.v:109818.9-109818.17" + attribute \src "libresoc.v:109515.9-109515.17" case 1'1 case end @@ -170997,14 +170531,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] end - attribute \src "libresoc.v:109836.3-109854.6" - process $proc$libresoc.v:109836$4252 + attribute \src "libresoc.v:109533.3-109551.6" + process $proc$libresoc.v:109533$4236 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Etype[1:0] $1\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:109837.5-109837.29" + attribute \src "libresoc.v:109534.5-109534.29" switch \initial - attribute \src "libresoc.v:109837.9-109837.17" + attribute \src "libresoc.v:109534.9-109534.17" case 1'1 case end @@ -171032,14 +170566,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_SV_Etype $0\dec31_dec_sub24_SV_Etype[1:0] end - attribute \src "libresoc.v:109855.3-109873.6" - process $proc$libresoc.v:109855$4253 + attribute \src "libresoc.v:109552.3-109570.6" + process $proc$libresoc.v:109552$4237 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Ptype[1:0] $1\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:109856.5-109856.29" + attribute \src "libresoc.v:109553.5-109553.29" switch \initial - attribute \src "libresoc.v:109856.9-109856.17" + attribute \src "libresoc.v:109553.9-109553.17" case 1'1 case end @@ -171067,14 +170601,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_SV_Ptype $0\dec31_dec_sub24_SV_Ptype[1:0] end - attribute \src "libresoc.v:109874.3-109892.6" - process $proc$libresoc.v:109874$4254 + attribute \src "libresoc.v:109571.3-109589.6" + process $proc$libresoc.v:109571$4238 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:109875.5-109875.29" + attribute \src "libresoc.v:109572.5-109572.29" switch \initial - attribute \src "libresoc.v:109875.9-109875.17" + attribute \src "libresoc.v:109572.9-109572.17" case 1'1 case end @@ -171102,14 +170636,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] end - attribute \src "libresoc.v:109893.3-109911.6" - process $proc$libresoc.v:109893$4255 + attribute \src "libresoc.v:109590.3-109608.6" + process $proc$libresoc.v:109590$4239 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:109894.5-109894.29" + attribute \src "libresoc.v:109591.5-109591.29" switch \initial - attribute \src "libresoc.v:109894.9-109894.17" + attribute \src "libresoc.v:109591.9-109591.17" case 1'1 case end @@ -171137,14 +170671,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] end - attribute \src "libresoc.v:109912.3-109930.6" - process $proc$libresoc.v:109912$4256 + attribute \src "libresoc.v:109609.3-109627.6" + process $proc$libresoc.v:109609$4240 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:109913.5-109913.29" + attribute \src "libresoc.v:109610.5-109610.29" switch \initial - attribute \src "libresoc.v:109913.9-109913.17" + attribute \src "libresoc.v:109610.9-109610.17" case 1'1 case end @@ -171172,14 +170706,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] end - attribute \src "libresoc.v:109931.3-109949.6" - process $proc$libresoc.v:109931$4257 + attribute \src "libresoc.v:109628.3-109646.6" + process $proc$libresoc.v:109628$4241 assign { } { } assign { } { } assign $0\dec31_dec_sub24_out_sel[2:0] $1\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:109932.5-109932.29" + attribute \src "libresoc.v:109629.5-109629.29" switch \initial - attribute \src "libresoc.v:109932.9-109932.17" + attribute \src "libresoc.v:109629.9-109629.17" case 1'1 case end @@ -171209,144 +170743,144 @@ module \dec31_dec_sub24 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:109955.1-112021.10" +attribute \src "libresoc.v:109652.1-111718.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" attribute \generator "nMigen" module \dec31_dec_sub26 - attribute \src "libresoc.v:111708.3-111759.6" + attribute \src "libresoc.v:111405.3-111456.6" wire width 2 $0\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:111760.3-111811.6" + attribute \src "libresoc.v:111457.3-111508.6" wire width 2 $0\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:111084.3-111135.6" + attribute \src "libresoc.v:110781.3-110832.6" wire width 8 $0\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:111292.3-111343.6" + attribute \src "libresoc.v:110989.3-111040.6" wire $0\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:110356.3-110407.6" + attribute \src "libresoc.v:110053.3-110104.6" wire width 3 $0\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:110408.3-110459.6" + attribute \src "libresoc.v:110105.3-110156.6" wire width 3 $0\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:111032.3-111083.6" + attribute \src "libresoc.v:110729.3-110780.6" wire width 2 $0\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:111240.3-111291.6" + attribute \src "libresoc.v:110937.3-110988.6" wire $0\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:111448.3-111499.6" + attribute \src "libresoc.v:111145.3-111196.6" wire width 5 $0\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:110304.3-110355.6" + attribute \src "libresoc.v:110001.3-110052.6" wire width 14 $0\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:111812.3-111863.6" + attribute \src "libresoc.v:111509.3-111560.6" wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:111864.3-111915.6" + attribute \src "libresoc.v:111561.3-111612.6" wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:111916.3-111967.6" + attribute \src "libresoc.v:111613.3-111664.6" wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:110876.3-110927.6" + attribute \src "libresoc.v:110573.3-110624.6" wire width 7 $0\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:111136.3-111187.6" + attribute \src "libresoc.v:110833.3-110884.6" wire $0\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:111188.3-111239.6" + attribute \src "libresoc.v:110885.3-110936.6" wire $0\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:111500.3-111551.6" + attribute \src "libresoc.v:111197.3-111248.6" wire $0\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:110824.3-110875.6" + attribute \src "libresoc.v:110521.3-110572.6" wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:111604.3-111655.6" + attribute \src "libresoc.v:111301.3-111352.6" wire $0\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:111968.3-112019.6" + attribute \src "libresoc.v:111665.3-111716.6" wire width 3 $0\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:110980.3-111031.6" + attribute \src "libresoc.v:110677.3-110728.6" wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:111396.3-111447.6" + attribute \src "libresoc.v:111093.3-111144.6" wire $0\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:111656.3-111707.6" + attribute \src "libresoc.v:111353.3-111404.6" wire $0\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:111552.3-111603.6" + attribute \src "libresoc.v:111249.3-111300.6" wire $0\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:111344.3-111395.6" + attribute \src "libresoc.v:111041.3-111092.6" wire $0\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:110720.3-110771.6" + attribute \src "libresoc.v:110417.3-110468.6" wire width 3 $0\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:110772.3-110823.6" + attribute \src "libresoc.v:110469.3-110520.6" wire width 3 $0\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:110460.3-110511.6" + attribute \src "libresoc.v:110157.3-110208.6" wire width 3 $0\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:110512.3-110563.6" + attribute \src "libresoc.v:110209.3-110260.6" wire width 3 $0\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:110564.3-110615.6" + attribute \src "libresoc.v:110261.3-110312.6" wire width 3 $0\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:110668.3-110719.6" + attribute \src "libresoc.v:110365.3-110416.6" wire width 3 $0\dec31_dec_sub26_sv_out2[2:0] - attribute \src "libresoc.v:110616.3-110667.6" + attribute \src "libresoc.v:110313.3-110364.6" wire width 3 $0\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:110928.3-110979.6" + attribute \src "libresoc.v:110625.3-110676.6" wire width 2 $0\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:109956.7-109956.20" + attribute \src "libresoc.v:109653.7-109653.20" wire $0\initial[0:0] - attribute \src "libresoc.v:111708.3-111759.6" + attribute \src "libresoc.v:111405.3-111456.6" wire width 2 $1\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:111760.3-111811.6" + attribute \src "libresoc.v:111457.3-111508.6" wire width 2 $1\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:111084.3-111135.6" + attribute \src "libresoc.v:110781.3-110832.6" wire width 8 $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:111292.3-111343.6" + attribute \src "libresoc.v:110989.3-111040.6" wire $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:110356.3-110407.6" + attribute \src "libresoc.v:110053.3-110104.6" wire width 3 $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:110408.3-110459.6" + attribute \src "libresoc.v:110105.3-110156.6" wire width 3 $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:111032.3-111083.6" + attribute \src "libresoc.v:110729.3-110780.6" wire width 2 $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:111240.3-111291.6" + attribute \src "libresoc.v:110937.3-110988.6" wire $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:111448.3-111499.6" + attribute \src "libresoc.v:111145.3-111196.6" wire width 5 $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:110304.3-110355.6" + attribute \src "libresoc.v:110001.3-110052.6" wire width 14 $1\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:111812.3-111863.6" + attribute \src "libresoc.v:111509.3-111560.6" wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:111864.3-111915.6" + attribute \src "libresoc.v:111561.3-111612.6" wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:111916.3-111967.6" + attribute \src "libresoc.v:111613.3-111664.6" wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:110876.3-110927.6" + attribute \src "libresoc.v:110573.3-110624.6" wire width 7 $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:111136.3-111187.6" + attribute \src "libresoc.v:110833.3-110884.6" wire $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:111188.3-111239.6" + attribute \src "libresoc.v:110885.3-110936.6" wire $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:111500.3-111551.6" + attribute \src "libresoc.v:111197.3-111248.6" wire $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:110824.3-110875.6" + attribute \src "libresoc.v:110521.3-110572.6" wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:111604.3-111655.6" + attribute \src "libresoc.v:111301.3-111352.6" wire $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:111968.3-112019.6" + attribute \src "libresoc.v:111665.3-111716.6" wire width 3 $1\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:110980.3-111031.6" + attribute \src "libresoc.v:110677.3-110728.6" wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:111396.3-111447.6" + attribute \src "libresoc.v:111093.3-111144.6" wire $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:111656.3-111707.6" + attribute \src "libresoc.v:111353.3-111404.6" wire $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:111552.3-111603.6" + attribute \src "libresoc.v:111249.3-111300.6" wire $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:111344.3-111395.6" + attribute \src "libresoc.v:111041.3-111092.6" wire $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:110720.3-110771.6" + attribute \src "libresoc.v:110417.3-110468.6" wire width 3 $1\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:110772.3-110823.6" + attribute \src "libresoc.v:110469.3-110520.6" wire width 3 $1\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:110460.3-110511.6" + attribute \src "libresoc.v:110157.3-110208.6" wire width 3 $1\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:110512.3-110563.6" + attribute \src "libresoc.v:110209.3-110260.6" wire width 3 $1\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:110564.3-110615.6" + attribute \src "libresoc.v:110261.3-110312.6" wire width 3 $1\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:110668.3-110719.6" + attribute \src "libresoc.v:110365.3-110416.6" wire width 3 $1\dec31_dec_sub26_sv_out2[2:0] - attribute \src "libresoc.v:110616.3-110667.6" + attribute \src "libresoc.v:110313.3-110364.6" wire width 3 $1\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:110928.3-110979.6" + attribute \src "libresoc.v:110625.3-110676.6" wire width 2 $1\dec31_dec_sub26_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -171658,28 +171192,28 @@ module \dec31_dec_sub26 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub26_upd - attribute \src "libresoc.v:109956.7-109956.15" + attribute \src "libresoc.v:109653.7-109653.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:109956.7-109956.20" - process $proc$libresoc.v:109956$4292 + attribute \src "libresoc.v:109653.7-109653.20" + process $proc$libresoc.v:109653$4276 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:110304.3-110355.6" - process $proc$libresoc.v:110304$4259 + attribute \src "libresoc.v:110001.3-110052.6" + process $proc$libresoc.v:110001$4243 assign { } { } assign { } { } assign $0\dec31_dec_sub26_function_unit[13:0] $1\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:110305.5-110305.29" + attribute \src "libresoc.v:110002.5-110002.29" switch \initial - attribute \src "libresoc.v:110305.9-110305.17" + attribute \src "libresoc.v:110002.9-110002.17" case 1'1 case end @@ -171751,14 +171285,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[13:0] end - attribute \src "libresoc.v:110356.3-110407.6" - process $proc$libresoc.v:110356$4260 + attribute \src "libresoc.v:110053.3-110104.6" + process $proc$libresoc.v:110053$4244 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:110357.5-110357.29" + attribute \src "libresoc.v:110054.5-110054.29" switch \initial - attribute \src "libresoc.v:110357.9-110357.17" + attribute \src "libresoc.v:110054.9-110054.17" case 1'1 case end @@ -171830,14 +171364,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:110408.3-110459.6" - process $proc$libresoc.v:110408$4261 + attribute \src "libresoc.v:110105.3-110156.6" + process $proc$libresoc.v:110105$4245 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:110409.5-110409.29" + attribute \src "libresoc.v:110106.5-110106.29" switch \initial - attribute \src "libresoc.v:110409.9-110409.17" + attribute \src "libresoc.v:110106.9-110106.17" case 1'1 case end @@ -171909,14 +171443,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:110460.3-110511.6" - process $proc$libresoc.v:110460$4262 + attribute \src "libresoc.v:110157.3-110208.6" + process $proc$libresoc.v:110157$4246 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in1[2:0] $1\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:110461.5-110461.29" + attribute \src "libresoc.v:110158.5-110158.29" switch \initial - attribute \src "libresoc.v:110461.9-110461.17" + attribute \src "libresoc.v:110158.9-110158.17" case 1'1 case end @@ -171988,14 +171522,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in1 $0\dec31_dec_sub26_sv_in1[2:0] end - attribute \src "libresoc.v:110512.3-110563.6" - process $proc$libresoc.v:110512$4263 + attribute \src "libresoc.v:110209.3-110260.6" + process $proc$libresoc.v:110209$4247 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in2[2:0] $1\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:110513.5-110513.29" + attribute \src "libresoc.v:110210.5-110210.29" switch \initial - attribute \src "libresoc.v:110513.9-110513.17" + attribute \src "libresoc.v:110210.9-110210.17" case 1'1 case end @@ -172067,14 +171601,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in2 $0\dec31_dec_sub26_sv_in2[2:0] end - attribute \src "libresoc.v:110564.3-110615.6" - process $proc$libresoc.v:110564$4264 + attribute \src "libresoc.v:110261.3-110312.6" + process $proc$libresoc.v:110261$4248 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in3[2:0] $1\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:110565.5-110565.29" + attribute \src "libresoc.v:110262.5-110262.29" switch \initial - attribute \src "libresoc.v:110565.9-110565.17" + attribute \src "libresoc.v:110262.9-110262.17" case 1'1 case end @@ -172146,14 +171680,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in3 $0\dec31_dec_sub26_sv_in3[2:0] end - attribute \src "libresoc.v:110616.3-110667.6" - process $proc$libresoc.v:110616$4265 + attribute \src "libresoc.v:110313.3-110364.6" + process $proc$libresoc.v:110313$4249 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_out[2:0] $1\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:110617.5-110617.29" + attribute \src "libresoc.v:110314.5-110314.29" switch \initial - attribute \src "libresoc.v:110617.9-110617.17" + attribute \src "libresoc.v:110314.9-110314.17" case 1'1 case end @@ -172225,14 +171759,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_out $0\dec31_dec_sub26_sv_out[2:0] end - attribute \src "libresoc.v:110668.3-110719.6" - process $proc$libresoc.v:110668$4266 + attribute \src "libresoc.v:110365.3-110416.6" + process $proc$libresoc.v:110365$4250 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_out2[2:0] $1\dec31_dec_sub26_sv_out2[2:0] - attribute \src "libresoc.v:110669.5-110669.29" + attribute \src "libresoc.v:110366.5-110366.29" switch \initial - attribute \src "libresoc.v:110669.9-110669.17" + attribute \src "libresoc.v:110366.9-110366.17" case 1'1 case end @@ -172304,14 +171838,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_out2 $0\dec31_dec_sub26_sv_out2[2:0] end - attribute \src "libresoc.v:110720.3-110771.6" - process $proc$libresoc.v:110720$4267 + attribute \src "libresoc.v:110417.3-110468.6" + process $proc$libresoc.v:110417$4251 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_in[2:0] $1\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:110721.5-110721.29" + attribute \src "libresoc.v:110418.5-110418.29" switch \initial - attribute \src "libresoc.v:110721.9-110721.17" + attribute \src "libresoc.v:110418.9-110418.17" case 1'1 case end @@ -172383,14 +171917,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_cr_in $0\dec31_dec_sub26_sv_cr_in[2:0] end - attribute \src "libresoc.v:110772.3-110823.6" - process $proc$libresoc.v:110772$4268 + attribute \src "libresoc.v:110469.3-110520.6" + process $proc$libresoc.v:110469$4252 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_out[2:0] $1\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:110773.5-110773.29" + attribute \src "libresoc.v:110470.5-110470.29" switch \initial - attribute \src "libresoc.v:110773.9-110773.17" + attribute \src "libresoc.v:110470.9-110470.17" case 1'1 case end @@ -172462,14 +171996,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_cr_out $0\dec31_dec_sub26_sv_cr_out[2:0] end - attribute \src "libresoc.v:110824.3-110875.6" - process $proc$libresoc.v:110824$4269 + attribute \src "libresoc.v:110521.3-110572.6" + process $proc$libresoc.v:110521$4253 assign { } { } assign { } { } assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:110825.5-110825.29" + attribute \src "libresoc.v:110522.5-110522.29" switch \initial - attribute \src "libresoc.v:110825.9-110825.17" + attribute \src "libresoc.v:110522.9-110522.17" case 1'1 case end @@ -172541,14 +172075,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] end - attribute \src "libresoc.v:110876.3-110927.6" - process $proc$libresoc.v:110876$4270 + attribute \src "libresoc.v:110573.3-110624.6" + process $proc$libresoc.v:110573$4254 assign { } { } assign { } { } assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:110877.5-110877.29" + attribute \src "libresoc.v:110574.5-110574.29" switch \initial - attribute \src "libresoc.v:110877.9-110877.17" + attribute \src "libresoc.v:110574.9-110574.17" case 1'1 case end @@ -172620,14 +172154,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:110928.3-110979.6" - process $proc$libresoc.v:110928$4271 + attribute \src "libresoc.v:110625.3-110676.6" + process $proc$libresoc.v:110625$4255 assign { } { } assign { } { } assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:110929.5-110929.29" + attribute \src "libresoc.v:110626.5-110626.29" switch \initial - attribute \src "libresoc.v:110929.9-110929.17" + attribute \src "libresoc.v:110626.9-110626.17" case 1'1 case end @@ -172699,14 +172233,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] end - attribute \src "libresoc.v:110980.3-111031.6" - process $proc$libresoc.v:110980$4272 + attribute \src "libresoc.v:110677.3-110728.6" + process $proc$libresoc.v:110677$4256 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:110981.5-110981.29" + attribute \src "libresoc.v:110678.5-110678.29" switch \initial - attribute \src "libresoc.v:110981.9-110981.17" + attribute \src "libresoc.v:110678.9-110678.17" case 1'1 case end @@ -172778,14 +172312,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:111032.3-111083.6" - process $proc$libresoc.v:111032$4273 + attribute \src "libresoc.v:110729.3-110780.6" + process $proc$libresoc.v:110729$4257 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:111033.5-111033.29" + attribute \src "libresoc.v:110730.5-110730.29" switch \initial - attribute \src "libresoc.v:111033.9-111033.17" + attribute \src "libresoc.v:110730.9-110730.17" case 1'1 case end @@ -172857,14 +172391,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] end - attribute \src "libresoc.v:111084.3-111135.6" - process $proc$libresoc.v:111084$4274 + attribute \src "libresoc.v:110781.3-110832.6" + process $proc$libresoc.v:110781$4258 assign { } { } assign { } { } assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:111085.5-111085.29" + attribute \src "libresoc.v:110782.5-110782.29" switch \initial - attribute \src "libresoc.v:111085.9-111085.17" + attribute \src "libresoc.v:110782.9-110782.17" case 1'1 case end @@ -172936,14 +172470,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] end - attribute \src "libresoc.v:111136.3-111187.6" - process $proc$libresoc.v:111136$4275 + attribute \src "libresoc.v:110833.3-110884.6" + process $proc$libresoc.v:110833$4259 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:111137.5-111137.29" + attribute \src "libresoc.v:110834.5-110834.29" switch \initial - attribute \src "libresoc.v:111137.9-111137.17" + attribute \src "libresoc.v:110834.9-110834.17" case 1'1 case end @@ -173015,14 +172549,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:111188.3-111239.6" - process $proc$libresoc.v:111188$4276 + attribute \src "libresoc.v:110885.3-110936.6" + process $proc$libresoc.v:110885$4260 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:111189.5-111189.29" + attribute \src "libresoc.v:110886.5-110886.29" switch \initial - attribute \src "libresoc.v:111189.9-111189.17" + attribute \src "libresoc.v:110886.9-110886.17" case 1'1 case end @@ -173094,14 +172628,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] end - attribute \src "libresoc.v:111240.3-111291.6" - process $proc$libresoc.v:111240$4277 + attribute \src "libresoc.v:110937.3-110988.6" + process $proc$libresoc.v:110937$4261 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:111241.5-111241.29" + attribute \src "libresoc.v:110938.5-110938.29" switch \initial - attribute \src "libresoc.v:111241.9-111241.17" + attribute \src "libresoc.v:110938.9-110938.17" case 1'1 case end @@ -173173,14 +172707,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] end - attribute \src "libresoc.v:111292.3-111343.6" - process $proc$libresoc.v:111292$4278 + attribute \src "libresoc.v:110989.3-111040.6" + process $proc$libresoc.v:110989$4262 assign { } { } assign { } { } assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:111293.5-111293.29" + attribute \src "libresoc.v:110990.5-110990.29" switch \initial - attribute \src "libresoc.v:111293.9-111293.17" + attribute \src "libresoc.v:110990.9-110990.17" case 1'1 case end @@ -173252,14 +172786,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] end - attribute \src "libresoc.v:111344.3-111395.6" - process $proc$libresoc.v:111344$4279 + attribute \src "libresoc.v:111041.3-111092.6" + process $proc$libresoc.v:111041$4263 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:111345.5-111345.29" + attribute \src "libresoc.v:111042.5-111042.29" switch \initial - attribute \src "libresoc.v:111345.9-111345.17" + attribute \src "libresoc.v:111042.9-111042.17" case 1'1 case end @@ -173331,14 +172865,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] end - attribute \src "libresoc.v:111396.3-111447.6" - process $proc$libresoc.v:111396$4280 + attribute \src "libresoc.v:111093.3-111144.6" + process $proc$libresoc.v:111093$4264 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:111397.5-111397.29" + attribute \src "libresoc.v:111094.5-111094.29" switch \initial - attribute \src "libresoc.v:111397.9-111397.17" + attribute \src "libresoc.v:111094.9-111094.17" case 1'1 case end @@ -173410,14 +172944,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] end - attribute \src "libresoc.v:111448.3-111499.6" - process $proc$libresoc.v:111448$4281 + attribute \src "libresoc.v:111145.3-111196.6" + process $proc$libresoc.v:111145$4265 assign { } { } assign { } { } assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:111449.5-111449.29" + attribute \src "libresoc.v:111146.5-111146.29" switch \initial - attribute \src "libresoc.v:111449.9-111449.17" + attribute \src "libresoc.v:111146.9-111146.17" case 1'1 case end @@ -173489,14 +173023,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] end - attribute \src "libresoc.v:111500.3-111551.6" - process $proc$libresoc.v:111500$4282 + attribute \src "libresoc.v:111197.3-111248.6" + process $proc$libresoc.v:111197$4266 assign { } { } assign { } { } assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:111501.5-111501.29" + attribute \src "libresoc.v:111198.5-111198.29" switch \initial - attribute \src "libresoc.v:111501.9-111501.17" + attribute \src "libresoc.v:111198.9-111198.17" case 1'1 case end @@ -173568,14 +173102,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:111552.3-111603.6" - process $proc$libresoc.v:111552$4283 + attribute \src "libresoc.v:111249.3-111300.6" + process $proc$libresoc.v:111249$4267 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:111553.5-111553.29" + attribute \src "libresoc.v:111250.5-111250.29" switch \initial - attribute \src "libresoc.v:111553.9-111553.17" + attribute \src "libresoc.v:111250.9-111250.17" case 1'1 case end @@ -173647,14 +173181,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:111604.3-111655.6" - process $proc$libresoc.v:111604$4284 + attribute \src "libresoc.v:111301.3-111352.6" + process $proc$libresoc.v:111301$4268 assign { } { } assign { } { } assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:111605.5-111605.29" + attribute \src "libresoc.v:111302.5-111302.29" switch \initial - attribute \src "libresoc.v:111605.9-111605.17" + attribute \src "libresoc.v:111302.9-111302.17" case 1'1 case end @@ -173726,14 +173260,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] end - attribute \src "libresoc.v:111656.3-111707.6" - process $proc$libresoc.v:111656$4285 + attribute \src "libresoc.v:111353.3-111404.6" + process $proc$libresoc.v:111353$4269 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:111657.5-111657.29" + attribute \src "libresoc.v:111354.5-111354.29" switch \initial - attribute \src "libresoc.v:111657.9-111657.17" + attribute \src "libresoc.v:111354.9-111354.17" case 1'1 case end @@ -173805,14 +173339,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] end - attribute \src "libresoc.v:111708.3-111759.6" - process $proc$libresoc.v:111708$4286 + attribute \src "libresoc.v:111405.3-111456.6" + process $proc$libresoc.v:111405$4270 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Etype[1:0] $1\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:111709.5-111709.29" + attribute \src "libresoc.v:111406.5-111406.29" switch \initial - attribute \src "libresoc.v:111709.9-111709.17" + attribute \src "libresoc.v:111406.9-111406.17" case 1'1 case end @@ -173884,14 +173418,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_SV_Etype $0\dec31_dec_sub26_SV_Etype[1:0] end - attribute \src "libresoc.v:111760.3-111811.6" - process $proc$libresoc.v:111760$4287 + attribute \src "libresoc.v:111457.3-111508.6" + process $proc$libresoc.v:111457$4271 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Ptype[1:0] $1\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:111761.5-111761.29" + attribute \src "libresoc.v:111458.5-111458.29" switch \initial - attribute \src "libresoc.v:111761.9-111761.17" + attribute \src "libresoc.v:111458.9-111458.17" case 1'1 case end @@ -173963,14 +173497,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_SV_Ptype $0\dec31_dec_sub26_SV_Ptype[1:0] end - attribute \src "libresoc.v:111812.3-111863.6" - process $proc$libresoc.v:111812$4288 + attribute \src "libresoc.v:111509.3-111560.6" + process $proc$libresoc.v:111509$4272 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:111813.5-111813.29" + attribute \src "libresoc.v:111510.5-111510.29" switch \initial - attribute \src "libresoc.v:111813.9-111813.17" + attribute \src "libresoc.v:111510.9-111510.17" case 1'1 case end @@ -174042,14 +173576,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] end - attribute \src "libresoc.v:111864.3-111915.6" - process $proc$libresoc.v:111864$4289 + attribute \src "libresoc.v:111561.3-111612.6" + process $proc$libresoc.v:111561$4273 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:111865.5-111865.29" + attribute \src "libresoc.v:111562.5-111562.29" switch \initial - attribute \src "libresoc.v:111865.9-111865.17" + attribute \src "libresoc.v:111562.9-111562.17" case 1'1 case end @@ -174121,14 +173655,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:111916.3-111967.6" - process $proc$libresoc.v:111916$4290 + attribute \src "libresoc.v:111613.3-111664.6" + process $proc$libresoc.v:111613$4274 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:111917.5-111917.29" + attribute \src "libresoc.v:111614.5-111614.29" switch \initial - attribute \src "libresoc.v:111917.9-111917.17" + attribute \src "libresoc.v:111614.9-111614.17" case 1'1 case end @@ -174200,14 +173734,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] end - attribute \src "libresoc.v:111968.3-112019.6" - process $proc$libresoc.v:111968$4291 + attribute \src "libresoc.v:111665.3-111716.6" + process $proc$libresoc.v:111665$4275 assign { } { } assign { } { } assign $0\dec31_dec_sub26_out_sel[2:0] $1\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:111969.5-111969.29" + attribute \src "libresoc.v:111666.5-111666.29" switch \initial - attribute \src "libresoc.v:111969.9-111969.17" + attribute \src "libresoc.v:111666.9-111666.17" case 1'1 case end @@ -174281,144 +173815,144 @@ module \dec31_dec_sub26 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:112025.1-113002.10" +attribute \src "libresoc.v:111722.1-112699.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" attribute \generator "nMigen" module \dec31_dec_sub27 - attribute \src "libresoc.v:112887.3-112905.6" + attribute \src "libresoc.v:112584.3-112602.6" wire width 2 $0\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:112906.3-112924.6" + attribute \src "libresoc.v:112603.3-112621.6" wire width 2 $0\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:112659.3-112677.6" + attribute \src "libresoc.v:112356.3-112374.6" wire width 8 $0\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:112735.3-112753.6" + attribute \src "libresoc.v:112432.3-112450.6" wire $0\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:112393.3-112411.6" + attribute \src "libresoc.v:112090.3-112108.6" wire width 3 $0\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:112412.3-112430.6" + attribute \src "libresoc.v:112109.3-112127.6" wire width 3 $0\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:112640.3-112658.6" + attribute \src "libresoc.v:112337.3-112355.6" wire width 2 $0\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:112716.3-112734.6" + attribute \src "libresoc.v:112413.3-112431.6" wire $0\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:112792.3-112810.6" + attribute \src "libresoc.v:112489.3-112507.6" wire width 5 $0\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:112374.3-112392.6" + attribute \src "libresoc.v:112071.3-112089.6" wire width 14 $0\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:112925.3-112943.6" + attribute \src "libresoc.v:112622.3-112640.6" wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:112944.3-112962.6" + attribute \src "libresoc.v:112641.3-112659.6" wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:112963.3-112981.6" + attribute \src "libresoc.v:112660.3-112678.6" wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:112583.3-112601.6" + attribute \src "libresoc.v:112280.3-112298.6" wire width 7 $0\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:112678.3-112696.6" + attribute \src "libresoc.v:112375.3-112393.6" wire $0\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:112697.3-112715.6" + attribute \src "libresoc.v:112394.3-112412.6" wire $0\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:112811.3-112829.6" + attribute \src "libresoc.v:112508.3-112526.6" wire $0\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:112564.3-112582.6" + attribute \src "libresoc.v:112261.3-112279.6" wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:112849.3-112867.6" + attribute \src "libresoc.v:112546.3-112564.6" wire $0\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:112982.3-113000.6" + attribute \src "libresoc.v:112679.3-112697.6" wire width 3 $0\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:112621.3-112639.6" + attribute \src "libresoc.v:112318.3-112336.6" wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:112773.3-112791.6" + attribute \src "libresoc.v:112470.3-112488.6" wire $0\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:112868.3-112886.6" + attribute \src "libresoc.v:112565.3-112583.6" wire $0\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:112830.3-112848.6" + attribute \src "libresoc.v:112527.3-112545.6" wire $0\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:112754.3-112772.6" + attribute \src "libresoc.v:112451.3-112469.6" wire $0\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:112526.3-112544.6" + attribute \src "libresoc.v:112223.3-112241.6" wire width 3 $0\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:112545.3-112563.6" + attribute \src "libresoc.v:112242.3-112260.6" wire width 3 $0\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:112431.3-112449.6" + attribute \src "libresoc.v:112128.3-112146.6" wire width 3 $0\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:112450.3-112468.6" + attribute \src "libresoc.v:112147.3-112165.6" wire width 3 $0\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:112469.3-112487.6" + attribute \src "libresoc.v:112166.3-112184.6" wire width 3 $0\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:112507.3-112525.6" + attribute \src "libresoc.v:112204.3-112222.6" wire width 3 $0\dec31_dec_sub27_sv_out2[2:0] - attribute \src "libresoc.v:112488.3-112506.6" + attribute \src "libresoc.v:112185.3-112203.6" wire width 3 $0\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:112602.3-112620.6" + attribute \src "libresoc.v:112299.3-112317.6" wire width 2 $0\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:112026.7-112026.20" + attribute \src "libresoc.v:111723.7-111723.20" wire $0\initial[0:0] - attribute \src "libresoc.v:112887.3-112905.6" + attribute \src "libresoc.v:112584.3-112602.6" wire width 2 $1\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:112906.3-112924.6" + attribute \src "libresoc.v:112603.3-112621.6" wire width 2 $1\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:112659.3-112677.6" + attribute \src "libresoc.v:112356.3-112374.6" wire width 8 $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:112735.3-112753.6" + attribute \src "libresoc.v:112432.3-112450.6" wire $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:112393.3-112411.6" + attribute \src "libresoc.v:112090.3-112108.6" wire width 3 $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:112412.3-112430.6" + attribute \src "libresoc.v:112109.3-112127.6" wire width 3 $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:112640.3-112658.6" + attribute \src "libresoc.v:112337.3-112355.6" wire width 2 $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:112716.3-112734.6" + attribute \src "libresoc.v:112413.3-112431.6" wire $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:112792.3-112810.6" + attribute \src "libresoc.v:112489.3-112507.6" wire width 5 $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:112374.3-112392.6" + attribute \src "libresoc.v:112071.3-112089.6" wire width 14 $1\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:112925.3-112943.6" + attribute \src "libresoc.v:112622.3-112640.6" wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:112944.3-112962.6" + attribute \src "libresoc.v:112641.3-112659.6" wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:112963.3-112981.6" + attribute \src "libresoc.v:112660.3-112678.6" wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:112583.3-112601.6" + attribute \src "libresoc.v:112280.3-112298.6" wire width 7 $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:112678.3-112696.6" + attribute \src "libresoc.v:112375.3-112393.6" wire $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:112697.3-112715.6" + attribute \src "libresoc.v:112394.3-112412.6" wire $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:112811.3-112829.6" + attribute \src "libresoc.v:112508.3-112526.6" wire $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:112564.3-112582.6" + attribute \src "libresoc.v:112261.3-112279.6" wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:112849.3-112867.6" + attribute \src "libresoc.v:112546.3-112564.6" wire $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:112982.3-113000.6" + attribute \src "libresoc.v:112679.3-112697.6" wire width 3 $1\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:112621.3-112639.6" + attribute \src "libresoc.v:112318.3-112336.6" wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:112773.3-112791.6" + attribute \src "libresoc.v:112470.3-112488.6" wire $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:112868.3-112886.6" + attribute \src "libresoc.v:112565.3-112583.6" wire $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:112830.3-112848.6" + attribute \src "libresoc.v:112527.3-112545.6" wire $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:112754.3-112772.6" + attribute \src "libresoc.v:112451.3-112469.6" wire $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:112526.3-112544.6" + attribute \src "libresoc.v:112223.3-112241.6" wire width 3 $1\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:112545.3-112563.6" + attribute \src "libresoc.v:112242.3-112260.6" wire width 3 $1\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:112431.3-112449.6" + attribute \src "libresoc.v:112128.3-112146.6" wire width 3 $1\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:112450.3-112468.6" + attribute \src "libresoc.v:112147.3-112165.6" wire width 3 $1\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:112469.3-112487.6" + attribute \src "libresoc.v:112166.3-112184.6" wire width 3 $1\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:112507.3-112525.6" + attribute \src "libresoc.v:112204.3-112222.6" wire width 3 $1\dec31_dec_sub27_sv_out2[2:0] - attribute \src "libresoc.v:112488.3-112506.6" + attribute \src "libresoc.v:112185.3-112203.6" wire width 3 $1\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:112602.3-112620.6" + attribute \src "libresoc.v:112299.3-112317.6" wire width 2 $1\dec31_dec_sub27_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -174730,28 +174264,28 @@ module \dec31_dec_sub27 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub27_upd - attribute \src "libresoc.v:112026.7-112026.15" + attribute \src "libresoc.v:111723.7-111723.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:112026.7-112026.20" - process $proc$libresoc.v:112026$4326 + attribute \src "libresoc.v:111723.7-111723.20" + process $proc$libresoc.v:111723$4310 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:112374.3-112392.6" - process $proc$libresoc.v:112374$4293 + attribute \src "libresoc.v:112071.3-112089.6" + process $proc$libresoc.v:112071$4277 assign { } { } assign { } { } assign $0\dec31_dec_sub27_function_unit[13:0] $1\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:112375.5-112375.29" + attribute \src "libresoc.v:112072.5-112072.29" switch \initial - attribute \src "libresoc.v:112375.9-112375.17" + attribute \src "libresoc.v:112072.9-112072.17" case 1'1 case end @@ -174779,14 +174313,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[13:0] end - attribute \src "libresoc.v:112393.3-112411.6" - process $proc$libresoc.v:112393$4294 + attribute \src "libresoc.v:112090.3-112108.6" + process $proc$libresoc.v:112090$4278 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:112394.5-112394.29" + attribute \src "libresoc.v:112091.5-112091.29" switch \initial - attribute \src "libresoc.v:112394.9-112394.17" + attribute \src "libresoc.v:112091.9-112091.17" case 1'1 case end @@ -174814,14 +174348,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] end - attribute \src "libresoc.v:112412.3-112430.6" - process $proc$libresoc.v:112412$4295 + attribute \src "libresoc.v:112109.3-112127.6" + process $proc$libresoc.v:112109$4279 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:112413.5-112413.29" + attribute \src "libresoc.v:112110.5-112110.29" switch \initial - attribute \src "libresoc.v:112413.9-112413.17" + attribute \src "libresoc.v:112110.9-112110.17" case 1'1 case end @@ -174849,14 +174383,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] end - attribute \src "libresoc.v:112431.3-112449.6" - process $proc$libresoc.v:112431$4296 + attribute \src "libresoc.v:112128.3-112146.6" + process $proc$libresoc.v:112128$4280 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in1[2:0] $1\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:112432.5-112432.29" + attribute \src "libresoc.v:112129.5-112129.29" switch \initial - attribute \src "libresoc.v:112432.9-112432.17" + attribute \src "libresoc.v:112129.9-112129.17" case 1'1 case end @@ -174884,14 +174418,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in1 $0\dec31_dec_sub27_sv_in1[2:0] end - attribute \src "libresoc.v:112450.3-112468.6" - process $proc$libresoc.v:112450$4297 + attribute \src "libresoc.v:112147.3-112165.6" + process $proc$libresoc.v:112147$4281 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in2[2:0] $1\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:112451.5-112451.29" + attribute \src "libresoc.v:112148.5-112148.29" switch \initial - attribute \src "libresoc.v:112451.9-112451.17" + attribute \src "libresoc.v:112148.9-112148.17" case 1'1 case end @@ -174919,14 +174453,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in2 $0\dec31_dec_sub27_sv_in2[2:0] end - attribute \src "libresoc.v:112469.3-112487.6" - process $proc$libresoc.v:112469$4298 + attribute \src "libresoc.v:112166.3-112184.6" + process $proc$libresoc.v:112166$4282 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in3[2:0] $1\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:112470.5-112470.29" + attribute \src "libresoc.v:112167.5-112167.29" switch \initial - attribute \src "libresoc.v:112470.9-112470.17" + attribute \src "libresoc.v:112167.9-112167.17" case 1'1 case end @@ -174954,14 +174488,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in3 $0\dec31_dec_sub27_sv_in3[2:0] end - attribute \src "libresoc.v:112488.3-112506.6" - process $proc$libresoc.v:112488$4299 + attribute \src "libresoc.v:112185.3-112203.6" + process $proc$libresoc.v:112185$4283 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_out[2:0] $1\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:112489.5-112489.29" + attribute \src "libresoc.v:112186.5-112186.29" switch \initial - attribute \src "libresoc.v:112489.9-112489.17" + attribute \src "libresoc.v:112186.9-112186.17" case 1'1 case end @@ -174989,14 +174523,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_out $0\dec31_dec_sub27_sv_out[2:0] end - attribute \src "libresoc.v:112507.3-112525.6" - process $proc$libresoc.v:112507$4300 + attribute \src "libresoc.v:112204.3-112222.6" + process $proc$libresoc.v:112204$4284 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_out2[2:0] $1\dec31_dec_sub27_sv_out2[2:0] - attribute \src "libresoc.v:112508.5-112508.29" + attribute \src "libresoc.v:112205.5-112205.29" switch \initial - attribute \src "libresoc.v:112508.9-112508.17" + attribute \src "libresoc.v:112205.9-112205.17" case 1'1 case end @@ -175024,14 +174558,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_out2 $0\dec31_dec_sub27_sv_out2[2:0] end - attribute \src "libresoc.v:112526.3-112544.6" - process $proc$libresoc.v:112526$4301 + attribute \src "libresoc.v:112223.3-112241.6" + process $proc$libresoc.v:112223$4285 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_in[2:0] $1\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:112527.5-112527.29" + attribute \src "libresoc.v:112224.5-112224.29" switch \initial - attribute \src "libresoc.v:112527.9-112527.17" + attribute \src "libresoc.v:112224.9-112224.17" case 1'1 case end @@ -175059,14 +174593,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_cr_in $0\dec31_dec_sub27_sv_cr_in[2:0] end - attribute \src "libresoc.v:112545.3-112563.6" - process $proc$libresoc.v:112545$4302 + attribute \src "libresoc.v:112242.3-112260.6" + process $proc$libresoc.v:112242$4286 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_out[2:0] $1\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:112546.5-112546.29" + attribute \src "libresoc.v:112243.5-112243.29" switch \initial - attribute \src "libresoc.v:112546.9-112546.17" + attribute \src "libresoc.v:112243.9-112243.17" case 1'1 case end @@ -175094,14 +174628,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_cr_out $0\dec31_dec_sub27_sv_cr_out[2:0] end - attribute \src "libresoc.v:112564.3-112582.6" - process $proc$libresoc.v:112564$4303 + attribute \src "libresoc.v:112261.3-112279.6" + process $proc$libresoc.v:112261$4287 assign { } { } assign { } { } assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:112565.5-112565.29" + attribute \src "libresoc.v:112262.5-112262.29" switch \initial - attribute \src "libresoc.v:112565.9-112565.17" + attribute \src "libresoc.v:112262.9-112262.17" case 1'1 case end @@ -175129,14 +174663,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] end - attribute \src "libresoc.v:112583.3-112601.6" - process $proc$libresoc.v:112583$4304 + attribute \src "libresoc.v:112280.3-112298.6" + process $proc$libresoc.v:112280$4288 assign { } { } assign { } { } assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:112584.5-112584.29" + attribute \src "libresoc.v:112281.5-112281.29" switch \initial - attribute \src "libresoc.v:112584.9-112584.17" + attribute \src "libresoc.v:112281.9-112281.17" case 1'1 case end @@ -175164,14 +174698,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] end - attribute \src "libresoc.v:112602.3-112620.6" - process $proc$libresoc.v:112602$4305 + attribute \src "libresoc.v:112299.3-112317.6" + process $proc$libresoc.v:112299$4289 assign { } { } assign { } { } assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:112603.5-112603.29" + attribute \src "libresoc.v:112300.5-112300.29" switch \initial - attribute \src "libresoc.v:112603.9-112603.17" + attribute \src "libresoc.v:112300.9-112300.17" case 1'1 case end @@ -175199,14 +174733,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] end - attribute \src "libresoc.v:112621.3-112639.6" - process $proc$libresoc.v:112621$4306 + attribute \src "libresoc.v:112318.3-112336.6" + process $proc$libresoc.v:112318$4290 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:112622.5-112622.29" + attribute \src "libresoc.v:112319.5-112319.29" switch \initial - attribute \src "libresoc.v:112622.9-112622.17" + attribute \src "libresoc.v:112319.9-112319.17" case 1'1 case end @@ -175234,14 +174768,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] end - attribute \src "libresoc.v:112640.3-112658.6" - process $proc$libresoc.v:112640$4307 + attribute \src "libresoc.v:112337.3-112355.6" + process $proc$libresoc.v:112337$4291 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:112641.5-112641.29" + attribute \src "libresoc.v:112338.5-112338.29" switch \initial - attribute \src "libresoc.v:112641.9-112641.17" + attribute \src "libresoc.v:112338.9-112338.17" case 1'1 case end @@ -175269,14 +174803,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] end - attribute \src "libresoc.v:112659.3-112677.6" - process $proc$libresoc.v:112659$4308 + attribute \src "libresoc.v:112356.3-112374.6" + process $proc$libresoc.v:112356$4292 assign { } { } assign { } { } assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:112660.5-112660.29" + attribute \src "libresoc.v:112357.5-112357.29" switch \initial - attribute \src "libresoc.v:112660.9-112660.17" + attribute \src "libresoc.v:112357.9-112357.17" case 1'1 case end @@ -175304,14 +174838,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] end - attribute \src "libresoc.v:112678.3-112696.6" - process $proc$libresoc.v:112678$4309 + attribute \src "libresoc.v:112375.3-112393.6" + process $proc$libresoc.v:112375$4293 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:112679.5-112679.29" + attribute \src "libresoc.v:112376.5-112376.29" switch \initial - attribute \src "libresoc.v:112679.9-112679.17" + attribute \src "libresoc.v:112376.9-112376.17" case 1'1 case end @@ -175339,14 +174873,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] end - attribute \src "libresoc.v:112697.3-112715.6" - process $proc$libresoc.v:112697$4310 + attribute \src "libresoc.v:112394.3-112412.6" + process $proc$libresoc.v:112394$4294 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:112698.5-112698.29" + attribute \src "libresoc.v:112395.5-112395.29" switch \initial - attribute \src "libresoc.v:112698.9-112698.17" + attribute \src "libresoc.v:112395.9-112395.17" case 1'1 case end @@ -175374,14 +174908,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] end - attribute \src "libresoc.v:112716.3-112734.6" - process $proc$libresoc.v:112716$4311 + attribute \src "libresoc.v:112413.3-112431.6" + process $proc$libresoc.v:112413$4295 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:112717.5-112717.29" + attribute \src "libresoc.v:112414.5-112414.29" switch \initial - attribute \src "libresoc.v:112717.9-112717.17" + attribute \src "libresoc.v:112414.9-112414.17" case 1'1 case end @@ -175409,14 +174943,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] end - attribute \src "libresoc.v:112735.3-112753.6" - process $proc$libresoc.v:112735$4312 + attribute \src "libresoc.v:112432.3-112450.6" + process $proc$libresoc.v:112432$4296 assign { } { } assign { } { } assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:112736.5-112736.29" + attribute \src "libresoc.v:112433.5-112433.29" switch \initial - attribute \src "libresoc.v:112736.9-112736.17" + attribute \src "libresoc.v:112433.9-112433.17" case 1'1 case end @@ -175444,14 +174978,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] end - attribute \src "libresoc.v:112754.3-112772.6" - process $proc$libresoc.v:112754$4313 + attribute \src "libresoc.v:112451.3-112469.6" + process $proc$libresoc.v:112451$4297 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:112755.5-112755.29" + attribute \src "libresoc.v:112452.5-112452.29" switch \initial - attribute \src "libresoc.v:112755.9-112755.17" + attribute \src "libresoc.v:112452.9-112452.17" case 1'1 case end @@ -175479,14 +175013,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] end - attribute \src "libresoc.v:112773.3-112791.6" - process $proc$libresoc.v:112773$4314 + attribute \src "libresoc.v:112470.3-112488.6" + process $proc$libresoc.v:112470$4298 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:112774.5-112774.29" + attribute \src "libresoc.v:112471.5-112471.29" switch \initial - attribute \src "libresoc.v:112774.9-112774.17" + attribute \src "libresoc.v:112471.9-112471.17" case 1'1 case end @@ -175514,14 +175048,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] end - attribute \src "libresoc.v:112792.3-112810.6" - process $proc$libresoc.v:112792$4315 + attribute \src "libresoc.v:112489.3-112507.6" + process $proc$libresoc.v:112489$4299 assign { } { } assign { } { } assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:112793.5-112793.29" + attribute \src "libresoc.v:112490.5-112490.29" switch \initial - attribute \src "libresoc.v:112793.9-112793.17" + attribute \src "libresoc.v:112490.9-112490.17" case 1'1 case end @@ -175549,14 +175083,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] end - attribute \src "libresoc.v:112811.3-112829.6" - process $proc$libresoc.v:112811$4316 + attribute \src "libresoc.v:112508.3-112526.6" + process $proc$libresoc.v:112508$4300 assign { } { } assign { } { } assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:112812.5-112812.29" + attribute \src "libresoc.v:112509.5-112509.29" switch \initial - attribute \src "libresoc.v:112812.9-112812.17" + attribute \src "libresoc.v:112509.9-112509.17" case 1'1 case end @@ -175584,14 +175118,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] end - attribute \src "libresoc.v:112830.3-112848.6" - process $proc$libresoc.v:112830$4317 + attribute \src "libresoc.v:112527.3-112545.6" + process $proc$libresoc.v:112527$4301 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:112831.5-112831.29" + attribute \src "libresoc.v:112528.5-112528.29" switch \initial - attribute \src "libresoc.v:112831.9-112831.17" + attribute \src "libresoc.v:112528.9-112528.17" case 1'1 case end @@ -175619,14 +175153,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] end - attribute \src "libresoc.v:112849.3-112867.6" - process $proc$libresoc.v:112849$4318 + attribute \src "libresoc.v:112546.3-112564.6" + process $proc$libresoc.v:112546$4302 assign { } { } assign { } { } assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:112850.5-112850.29" + attribute \src "libresoc.v:112547.5-112547.29" switch \initial - attribute \src "libresoc.v:112850.9-112850.17" + attribute \src "libresoc.v:112547.9-112547.17" case 1'1 case end @@ -175654,14 +175188,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] end - attribute \src "libresoc.v:112868.3-112886.6" - process $proc$libresoc.v:112868$4319 + attribute \src "libresoc.v:112565.3-112583.6" + process $proc$libresoc.v:112565$4303 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:112869.5-112869.29" + attribute \src "libresoc.v:112566.5-112566.29" switch \initial - attribute \src "libresoc.v:112869.9-112869.17" + attribute \src "libresoc.v:112566.9-112566.17" case 1'1 case end @@ -175689,14 +175223,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] end - attribute \src "libresoc.v:112887.3-112905.6" - process $proc$libresoc.v:112887$4320 + attribute \src "libresoc.v:112584.3-112602.6" + process $proc$libresoc.v:112584$4304 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Etype[1:0] $1\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:112888.5-112888.29" + attribute \src "libresoc.v:112585.5-112585.29" switch \initial - attribute \src "libresoc.v:112888.9-112888.17" + attribute \src "libresoc.v:112585.9-112585.17" case 1'1 case end @@ -175724,14 +175258,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_SV_Etype $0\dec31_dec_sub27_SV_Etype[1:0] end - attribute \src "libresoc.v:112906.3-112924.6" - process $proc$libresoc.v:112906$4321 + attribute \src "libresoc.v:112603.3-112621.6" + process $proc$libresoc.v:112603$4305 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Ptype[1:0] $1\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:112907.5-112907.29" + attribute \src "libresoc.v:112604.5-112604.29" switch \initial - attribute \src "libresoc.v:112907.9-112907.17" + attribute \src "libresoc.v:112604.9-112604.17" case 1'1 case end @@ -175759,14 +175293,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_SV_Ptype $0\dec31_dec_sub27_SV_Ptype[1:0] end - attribute \src "libresoc.v:112925.3-112943.6" - process $proc$libresoc.v:112925$4322 + attribute \src "libresoc.v:112622.3-112640.6" + process $proc$libresoc.v:112622$4306 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:112926.5-112926.29" + attribute \src "libresoc.v:112623.5-112623.29" switch \initial - attribute \src "libresoc.v:112926.9-112926.17" + attribute \src "libresoc.v:112623.9-112623.17" case 1'1 case end @@ -175794,14 +175328,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] end - attribute \src "libresoc.v:112944.3-112962.6" - process $proc$libresoc.v:112944$4323 + attribute \src "libresoc.v:112641.3-112659.6" + process $proc$libresoc.v:112641$4307 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:112945.5-112945.29" + attribute \src "libresoc.v:112642.5-112642.29" switch \initial - attribute \src "libresoc.v:112945.9-112945.17" + attribute \src "libresoc.v:112642.9-112642.17" case 1'1 case end @@ -175829,14 +175363,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] end - attribute \src "libresoc.v:112963.3-112981.6" - process $proc$libresoc.v:112963$4324 + attribute \src "libresoc.v:112660.3-112678.6" + process $proc$libresoc.v:112660$4308 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:112964.5-112964.29" + attribute \src "libresoc.v:112661.5-112661.29" switch \initial - attribute \src "libresoc.v:112964.9-112964.17" + attribute \src "libresoc.v:112661.9-112661.17" case 1'1 case end @@ -175864,14 +175398,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] end - attribute \src "libresoc.v:112982.3-113000.6" - process $proc$libresoc.v:112982$4325 + attribute \src "libresoc.v:112679.3-112697.6" + process $proc$libresoc.v:112679$4309 assign { } { } assign { } { } assign $0\dec31_dec_sub27_out_sel[2:0] $1\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:112983.5-112983.29" + attribute \src "libresoc.v:112680.5-112680.29" switch \initial - attribute \src "libresoc.v:112983.9-112983.17" + attribute \src "libresoc.v:112680.9-112680.17" case 1'1 case end @@ -175901,144 +175435,144 @@ module \dec31_dec_sub27 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:113006.1-114577.10" +attribute \src "libresoc.v:112703.1-114274.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" attribute \generator "nMigen" module \dec31_dec_sub28 - attribute \src "libresoc.v:114354.3-114390.6" + attribute \src "libresoc.v:114051.3-114087.6" wire width 2 $0\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:114391.3-114427.6" + attribute \src "libresoc.v:114088.3-114124.6" wire width 2 $0\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:113910.3-113946.6" + attribute \src "libresoc.v:113607.3-113643.6" wire width 8 $0\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:114058.3-114094.6" + attribute \src "libresoc.v:113755.3-113791.6" wire $0\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:113392.3-113428.6" + attribute \src "libresoc.v:113089.3-113125.6" wire width 3 $0\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:113429.3-113465.6" + attribute \src "libresoc.v:113126.3-113162.6" wire width 3 $0\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:113873.3-113909.6" + attribute \src "libresoc.v:113570.3-113606.6" wire width 2 $0\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:114021.3-114057.6" + attribute \src "libresoc.v:113718.3-113754.6" wire $0\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:114169.3-114205.6" + attribute \src "libresoc.v:113866.3-113902.6" wire width 5 $0\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:113355.3-113391.6" + attribute \src "libresoc.v:113052.3-113088.6" wire width 14 $0\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:114428.3-114464.6" + attribute \src "libresoc.v:114125.3-114161.6" wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:114465.3-114501.6" + attribute \src "libresoc.v:114162.3-114198.6" wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:114502.3-114538.6" + attribute \src "libresoc.v:114199.3-114235.6" wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:113762.3-113798.6" + attribute \src "libresoc.v:113459.3-113495.6" wire width 7 $0\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:113947.3-113983.6" + attribute \src "libresoc.v:113644.3-113680.6" wire $0\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:113984.3-114020.6" + attribute \src "libresoc.v:113681.3-113717.6" wire $0\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:114206.3-114242.6" + attribute \src "libresoc.v:113903.3-113939.6" wire $0\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:113725.3-113761.6" + attribute \src "libresoc.v:113422.3-113458.6" wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:114280.3-114316.6" + attribute \src "libresoc.v:113977.3-114013.6" wire $0\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:114539.3-114575.6" + attribute \src "libresoc.v:114236.3-114272.6" wire width 3 $0\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:113836.3-113872.6" + attribute \src "libresoc.v:113533.3-113569.6" wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:114132.3-114168.6" + attribute \src "libresoc.v:113829.3-113865.6" wire $0\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:114317.3-114353.6" + attribute \src "libresoc.v:114014.3-114050.6" wire $0\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:114243.3-114279.6" + attribute \src "libresoc.v:113940.3-113976.6" wire $0\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:114095.3-114131.6" + attribute \src "libresoc.v:113792.3-113828.6" wire $0\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:113651.3-113687.6" + attribute \src "libresoc.v:113348.3-113384.6" wire width 3 $0\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:113688.3-113724.6" + attribute \src "libresoc.v:113385.3-113421.6" wire width 3 $0\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:113466.3-113502.6" + attribute \src "libresoc.v:113163.3-113199.6" wire width 3 $0\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:113503.3-113539.6" + attribute \src "libresoc.v:113200.3-113236.6" wire width 3 $0\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:113540.3-113576.6" + attribute \src "libresoc.v:113237.3-113273.6" wire width 3 $0\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:113614.3-113650.6" + attribute \src "libresoc.v:113311.3-113347.6" wire width 3 $0\dec31_dec_sub28_sv_out2[2:0] - attribute \src "libresoc.v:113577.3-113613.6" + attribute \src "libresoc.v:113274.3-113310.6" wire width 3 $0\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:113799.3-113835.6" + attribute \src "libresoc.v:113496.3-113532.6" wire width 2 $0\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:113007.7-113007.20" + attribute \src "libresoc.v:112704.7-112704.20" wire $0\initial[0:0] - attribute \src "libresoc.v:114354.3-114390.6" + attribute \src "libresoc.v:114051.3-114087.6" wire width 2 $1\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:114391.3-114427.6" + attribute \src "libresoc.v:114088.3-114124.6" wire width 2 $1\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:113910.3-113946.6" + attribute \src "libresoc.v:113607.3-113643.6" wire width 8 $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:114058.3-114094.6" + attribute \src "libresoc.v:113755.3-113791.6" wire $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:113392.3-113428.6" + attribute \src "libresoc.v:113089.3-113125.6" wire width 3 $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:113429.3-113465.6" + attribute \src "libresoc.v:113126.3-113162.6" wire width 3 $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:113873.3-113909.6" + attribute \src "libresoc.v:113570.3-113606.6" wire width 2 $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:114021.3-114057.6" + attribute \src "libresoc.v:113718.3-113754.6" wire $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:114169.3-114205.6" + attribute \src "libresoc.v:113866.3-113902.6" wire width 5 $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:113355.3-113391.6" + attribute \src "libresoc.v:113052.3-113088.6" wire width 14 $1\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:114428.3-114464.6" + attribute \src "libresoc.v:114125.3-114161.6" wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:114465.3-114501.6" + attribute \src "libresoc.v:114162.3-114198.6" wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:114502.3-114538.6" + attribute \src "libresoc.v:114199.3-114235.6" wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:113762.3-113798.6" + attribute \src "libresoc.v:113459.3-113495.6" wire width 7 $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:113947.3-113983.6" + attribute \src "libresoc.v:113644.3-113680.6" wire $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:113984.3-114020.6" + attribute \src "libresoc.v:113681.3-113717.6" wire $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:114206.3-114242.6" + attribute \src "libresoc.v:113903.3-113939.6" wire $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:113725.3-113761.6" + attribute \src "libresoc.v:113422.3-113458.6" wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:114280.3-114316.6" + attribute \src "libresoc.v:113977.3-114013.6" wire $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:114539.3-114575.6" + attribute \src "libresoc.v:114236.3-114272.6" wire width 3 $1\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:113836.3-113872.6" + attribute \src "libresoc.v:113533.3-113569.6" wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:114132.3-114168.6" + attribute \src "libresoc.v:113829.3-113865.6" wire $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:114317.3-114353.6" + attribute \src "libresoc.v:114014.3-114050.6" wire $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:114243.3-114279.6" + attribute \src "libresoc.v:113940.3-113976.6" wire $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:114095.3-114131.6" + attribute \src "libresoc.v:113792.3-113828.6" wire $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:113651.3-113687.6" + attribute \src "libresoc.v:113348.3-113384.6" wire width 3 $1\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:113688.3-113724.6" + attribute \src "libresoc.v:113385.3-113421.6" wire width 3 $1\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:113466.3-113502.6" + attribute \src "libresoc.v:113163.3-113199.6" wire width 3 $1\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:113503.3-113539.6" + attribute \src "libresoc.v:113200.3-113236.6" wire width 3 $1\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:113540.3-113576.6" + attribute \src "libresoc.v:113237.3-113273.6" wire width 3 $1\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:113614.3-113650.6" + attribute \src "libresoc.v:113311.3-113347.6" wire width 3 $1\dec31_dec_sub28_sv_out2[2:0] - attribute \src "libresoc.v:113577.3-113613.6" + attribute \src "libresoc.v:113274.3-113310.6" wire width 3 $1\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:113799.3-113835.6" + attribute \src "libresoc.v:113496.3-113532.6" wire width 2 $1\dec31_dec_sub28_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -176350,28 +175884,28 @@ module \dec31_dec_sub28 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub28_upd - attribute \src "libresoc.v:113007.7-113007.15" + attribute \src "libresoc.v:112704.7-112704.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:113007.7-113007.20" - process $proc$libresoc.v:113007$4360 + attribute \src "libresoc.v:112704.7-112704.20" + process $proc$libresoc.v:112704$4344 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:113355.3-113391.6" - process $proc$libresoc.v:113355$4327 + attribute \src "libresoc.v:113052.3-113088.6" + process $proc$libresoc.v:113052$4311 assign { } { } assign { } { } assign $0\dec31_dec_sub28_function_unit[13:0] $1\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:113356.5-113356.29" + attribute \src "libresoc.v:113053.5-113053.29" switch \initial - attribute \src "libresoc.v:113356.9-113356.17" + attribute \src "libresoc.v:113053.9-113053.17" case 1'1 case end @@ -176423,14 +175957,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[13:0] end - attribute \src "libresoc.v:113392.3-113428.6" - process $proc$libresoc.v:113392$4328 + attribute \src "libresoc.v:113089.3-113125.6" + process $proc$libresoc.v:113089$4312 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:113393.5-113393.29" + attribute \src "libresoc.v:113090.5-113090.29" switch \initial - attribute \src "libresoc.v:113393.9-113393.17" + attribute \src "libresoc.v:113090.9-113090.17" case 1'1 case end @@ -176482,14 +176016,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] end - attribute \src "libresoc.v:113429.3-113465.6" - process $proc$libresoc.v:113429$4329 + attribute \src "libresoc.v:113126.3-113162.6" + process $proc$libresoc.v:113126$4313 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:113430.5-113430.29" + attribute \src "libresoc.v:113127.5-113127.29" switch \initial - attribute \src "libresoc.v:113430.9-113430.17" + attribute \src "libresoc.v:113127.9-113127.17" case 1'1 case end @@ -176541,14 +176075,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] end - attribute \src "libresoc.v:113466.3-113502.6" - process $proc$libresoc.v:113466$4330 + attribute \src "libresoc.v:113163.3-113199.6" + process $proc$libresoc.v:113163$4314 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in1[2:0] $1\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:113467.5-113467.29" + attribute \src "libresoc.v:113164.5-113164.29" switch \initial - attribute \src "libresoc.v:113467.9-113467.17" + attribute \src "libresoc.v:113164.9-113164.17" case 1'1 case end @@ -176600,14 +176134,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in1 $0\dec31_dec_sub28_sv_in1[2:0] end - attribute \src "libresoc.v:113503.3-113539.6" - process $proc$libresoc.v:113503$4331 + attribute \src "libresoc.v:113200.3-113236.6" + process $proc$libresoc.v:113200$4315 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in2[2:0] $1\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:113504.5-113504.29" + attribute \src "libresoc.v:113201.5-113201.29" switch \initial - attribute \src "libresoc.v:113504.9-113504.17" + attribute \src "libresoc.v:113201.9-113201.17" case 1'1 case end @@ -176659,14 +176193,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in2 $0\dec31_dec_sub28_sv_in2[2:0] end - attribute \src "libresoc.v:113540.3-113576.6" - process $proc$libresoc.v:113540$4332 + attribute \src "libresoc.v:113237.3-113273.6" + process $proc$libresoc.v:113237$4316 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in3[2:0] $1\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:113541.5-113541.29" + attribute \src "libresoc.v:113238.5-113238.29" switch \initial - attribute \src "libresoc.v:113541.9-113541.17" + attribute \src "libresoc.v:113238.9-113238.17" case 1'1 case end @@ -176718,14 +176252,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in3 $0\dec31_dec_sub28_sv_in3[2:0] end - attribute \src "libresoc.v:113577.3-113613.6" - process $proc$libresoc.v:113577$4333 + attribute \src "libresoc.v:113274.3-113310.6" + process $proc$libresoc.v:113274$4317 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_out[2:0] $1\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:113578.5-113578.29" + attribute \src "libresoc.v:113275.5-113275.29" switch \initial - attribute \src "libresoc.v:113578.9-113578.17" + attribute \src "libresoc.v:113275.9-113275.17" case 1'1 case end @@ -176777,14 +176311,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_out $0\dec31_dec_sub28_sv_out[2:0] end - attribute \src "libresoc.v:113614.3-113650.6" - process $proc$libresoc.v:113614$4334 + attribute \src "libresoc.v:113311.3-113347.6" + process $proc$libresoc.v:113311$4318 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_out2[2:0] $1\dec31_dec_sub28_sv_out2[2:0] - attribute \src "libresoc.v:113615.5-113615.29" + attribute \src "libresoc.v:113312.5-113312.29" switch \initial - attribute \src "libresoc.v:113615.9-113615.17" + attribute \src "libresoc.v:113312.9-113312.17" case 1'1 case end @@ -176836,14 +176370,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_out2 $0\dec31_dec_sub28_sv_out2[2:0] end - attribute \src "libresoc.v:113651.3-113687.6" - process $proc$libresoc.v:113651$4335 + attribute \src "libresoc.v:113348.3-113384.6" + process $proc$libresoc.v:113348$4319 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_in[2:0] $1\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:113652.5-113652.29" + attribute \src "libresoc.v:113349.5-113349.29" switch \initial - attribute \src "libresoc.v:113652.9-113652.17" + attribute \src "libresoc.v:113349.9-113349.17" case 1'1 case end @@ -176895,14 +176429,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_cr_in $0\dec31_dec_sub28_sv_cr_in[2:0] end - attribute \src "libresoc.v:113688.3-113724.6" - process $proc$libresoc.v:113688$4336 + attribute \src "libresoc.v:113385.3-113421.6" + process $proc$libresoc.v:113385$4320 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_out[2:0] $1\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:113689.5-113689.29" + attribute \src "libresoc.v:113386.5-113386.29" switch \initial - attribute \src "libresoc.v:113689.9-113689.17" + attribute \src "libresoc.v:113386.9-113386.17" case 1'1 case end @@ -176954,14 +176488,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_cr_out $0\dec31_dec_sub28_sv_cr_out[2:0] end - attribute \src "libresoc.v:113725.3-113761.6" - process $proc$libresoc.v:113725$4337 + attribute \src "libresoc.v:113422.3-113458.6" + process $proc$libresoc.v:113422$4321 assign { } { } assign { } { } assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:113726.5-113726.29" + attribute \src "libresoc.v:113423.5-113423.29" switch \initial - attribute \src "libresoc.v:113726.9-113726.17" + attribute \src "libresoc.v:113423.9-113423.17" case 1'1 case end @@ -177013,14 +176547,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] end - attribute \src "libresoc.v:113762.3-113798.6" - process $proc$libresoc.v:113762$4338 + attribute \src "libresoc.v:113459.3-113495.6" + process $proc$libresoc.v:113459$4322 assign { } { } assign { } { } assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:113763.5-113763.29" + attribute \src "libresoc.v:113460.5-113460.29" switch \initial - attribute \src "libresoc.v:113763.9-113763.17" + attribute \src "libresoc.v:113460.9-113460.17" case 1'1 case end @@ -177072,14 +176606,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] end - attribute \src "libresoc.v:113799.3-113835.6" - process $proc$libresoc.v:113799$4339 + attribute \src "libresoc.v:113496.3-113532.6" + process $proc$libresoc.v:113496$4323 assign { } { } assign { } { } assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:113800.5-113800.29" + attribute \src "libresoc.v:113497.5-113497.29" switch \initial - attribute \src "libresoc.v:113800.9-113800.17" + attribute \src "libresoc.v:113497.9-113497.17" case 1'1 case end @@ -177131,14 +176665,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] end - attribute \src "libresoc.v:113836.3-113872.6" - process $proc$libresoc.v:113836$4340 + attribute \src "libresoc.v:113533.3-113569.6" + process $proc$libresoc.v:113533$4324 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:113837.5-113837.29" + attribute \src "libresoc.v:113534.5-113534.29" switch \initial - attribute \src "libresoc.v:113837.9-113837.17" + attribute \src "libresoc.v:113534.9-113534.17" case 1'1 case end @@ -177190,14 +176724,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] end - attribute \src "libresoc.v:113873.3-113909.6" - process $proc$libresoc.v:113873$4341 + attribute \src "libresoc.v:113570.3-113606.6" + process $proc$libresoc.v:113570$4325 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:113874.5-113874.29" + attribute \src "libresoc.v:113571.5-113571.29" switch \initial - attribute \src "libresoc.v:113874.9-113874.17" + attribute \src "libresoc.v:113571.9-113571.17" case 1'1 case end @@ -177249,14 +176783,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] end - attribute \src "libresoc.v:113910.3-113946.6" - process $proc$libresoc.v:113910$4342 + attribute \src "libresoc.v:113607.3-113643.6" + process $proc$libresoc.v:113607$4326 assign { } { } assign { } { } assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:113911.5-113911.29" + attribute \src "libresoc.v:113608.5-113608.29" switch \initial - attribute \src "libresoc.v:113911.9-113911.17" + attribute \src "libresoc.v:113608.9-113608.17" case 1'1 case end @@ -177308,14 +176842,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] end - attribute \src "libresoc.v:113947.3-113983.6" - process $proc$libresoc.v:113947$4343 + attribute \src "libresoc.v:113644.3-113680.6" + process $proc$libresoc.v:113644$4327 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:113948.5-113948.29" + attribute \src "libresoc.v:113645.5-113645.29" switch \initial - attribute \src "libresoc.v:113948.9-113948.17" + attribute \src "libresoc.v:113645.9-113645.17" case 1'1 case end @@ -177367,14 +176901,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] end - attribute \src "libresoc.v:113984.3-114020.6" - process $proc$libresoc.v:113984$4344 + attribute \src "libresoc.v:113681.3-113717.6" + process $proc$libresoc.v:113681$4328 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:113985.5-113985.29" + attribute \src "libresoc.v:113682.5-113682.29" switch \initial - attribute \src "libresoc.v:113985.9-113985.17" + attribute \src "libresoc.v:113682.9-113682.17" case 1'1 case end @@ -177426,14 +176960,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] end - attribute \src "libresoc.v:114021.3-114057.6" - process $proc$libresoc.v:114021$4345 + attribute \src "libresoc.v:113718.3-113754.6" + process $proc$libresoc.v:113718$4329 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:114022.5-114022.29" + attribute \src "libresoc.v:113719.5-113719.29" switch \initial - attribute \src "libresoc.v:114022.9-114022.17" + attribute \src "libresoc.v:113719.9-113719.17" case 1'1 case end @@ -177485,14 +177019,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] end - attribute \src "libresoc.v:114058.3-114094.6" - process $proc$libresoc.v:114058$4346 + attribute \src "libresoc.v:113755.3-113791.6" + process $proc$libresoc.v:113755$4330 assign { } { } assign { } { } assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:114059.5-114059.29" + attribute \src "libresoc.v:113756.5-113756.29" switch \initial - attribute \src "libresoc.v:114059.9-114059.17" + attribute \src "libresoc.v:113756.9-113756.17" case 1'1 case end @@ -177544,14 +177078,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] end - attribute \src "libresoc.v:114095.3-114131.6" - process $proc$libresoc.v:114095$4347 + attribute \src "libresoc.v:113792.3-113828.6" + process $proc$libresoc.v:113792$4331 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:114096.5-114096.29" + attribute \src "libresoc.v:113793.5-113793.29" switch \initial - attribute \src "libresoc.v:114096.9-114096.17" + attribute \src "libresoc.v:113793.9-113793.17" case 1'1 case end @@ -177603,14 +177137,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] end - attribute \src "libresoc.v:114132.3-114168.6" - process $proc$libresoc.v:114132$4348 + attribute \src "libresoc.v:113829.3-113865.6" + process $proc$libresoc.v:113829$4332 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:114133.5-114133.29" + attribute \src "libresoc.v:113830.5-113830.29" switch \initial - attribute \src "libresoc.v:114133.9-114133.17" + attribute \src "libresoc.v:113830.9-113830.17" case 1'1 case end @@ -177662,14 +177196,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] end - attribute \src "libresoc.v:114169.3-114205.6" - process $proc$libresoc.v:114169$4349 + attribute \src "libresoc.v:113866.3-113902.6" + process $proc$libresoc.v:113866$4333 assign { } { } assign { } { } assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:114170.5-114170.29" + attribute \src "libresoc.v:113867.5-113867.29" switch \initial - attribute \src "libresoc.v:114170.9-114170.17" + attribute \src "libresoc.v:113867.9-113867.17" case 1'1 case end @@ -177721,14 +177255,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] end - attribute \src "libresoc.v:114206.3-114242.6" - process $proc$libresoc.v:114206$4350 + attribute \src "libresoc.v:113903.3-113939.6" + process $proc$libresoc.v:113903$4334 assign { } { } assign { } { } assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:114207.5-114207.29" + attribute \src "libresoc.v:113904.5-113904.29" switch \initial - attribute \src "libresoc.v:114207.9-114207.17" + attribute \src "libresoc.v:113904.9-113904.17" case 1'1 case end @@ -177780,14 +177314,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] end - attribute \src "libresoc.v:114243.3-114279.6" - process $proc$libresoc.v:114243$4351 + attribute \src "libresoc.v:113940.3-113976.6" + process $proc$libresoc.v:113940$4335 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:114244.5-114244.29" + attribute \src "libresoc.v:113941.5-113941.29" switch \initial - attribute \src "libresoc.v:114244.9-114244.17" + attribute \src "libresoc.v:113941.9-113941.17" case 1'1 case end @@ -177839,14 +177373,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] end - attribute \src "libresoc.v:114280.3-114316.6" - process $proc$libresoc.v:114280$4352 + attribute \src "libresoc.v:113977.3-114013.6" + process $proc$libresoc.v:113977$4336 assign { } { } assign { } { } assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:114281.5-114281.29" + attribute \src "libresoc.v:113978.5-113978.29" switch \initial - attribute \src "libresoc.v:114281.9-114281.17" + attribute \src "libresoc.v:113978.9-113978.17" case 1'1 case end @@ -177898,14 +177432,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] end - attribute \src "libresoc.v:114317.3-114353.6" - process $proc$libresoc.v:114317$4353 + attribute \src "libresoc.v:114014.3-114050.6" + process $proc$libresoc.v:114014$4337 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:114318.5-114318.29" + attribute \src "libresoc.v:114015.5-114015.29" switch \initial - attribute \src "libresoc.v:114318.9-114318.17" + attribute \src "libresoc.v:114015.9-114015.17" case 1'1 case end @@ -177957,14 +177491,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] end - attribute \src "libresoc.v:114354.3-114390.6" - process $proc$libresoc.v:114354$4354 + attribute \src "libresoc.v:114051.3-114087.6" + process $proc$libresoc.v:114051$4338 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Etype[1:0] $1\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:114355.5-114355.29" + attribute \src "libresoc.v:114052.5-114052.29" switch \initial - attribute \src "libresoc.v:114355.9-114355.17" + attribute \src "libresoc.v:114052.9-114052.17" case 1'1 case end @@ -178016,14 +177550,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_SV_Etype $0\dec31_dec_sub28_SV_Etype[1:0] end - attribute \src "libresoc.v:114391.3-114427.6" - process $proc$libresoc.v:114391$4355 + attribute \src "libresoc.v:114088.3-114124.6" + process $proc$libresoc.v:114088$4339 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Ptype[1:0] $1\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:114392.5-114392.29" + attribute \src "libresoc.v:114089.5-114089.29" switch \initial - attribute \src "libresoc.v:114392.9-114392.17" + attribute \src "libresoc.v:114089.9-114089.17" case 1'1 case end @@ -178075,14 +177609,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_SV_Ptype $0\dec31_dec_sub28_SV_Ptype[1:0] end - attribute \src "libresoc.v:114428.3-114464.6" - process $proc$libresoc.v:114428$4356 + attribute \src "libresoc.v:114125.3-114161.6" + process $proc$libresoc.v:114125$4340 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:114429.5-114429.29" + attribute \src "libresoc.v:114126.5-114126.29" switch \initial - attribute \src "libresoc.v:114429.9-114429.17" + attribute \src "libresoc.v:114126.9-114126.17" case 1'1 case end @@ -178134,14 +177668,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] end - attribute \src "libresoc.v:114465.3-114501.6" - process $proc$libresoc.v:114465$4357 + attribute \src "libresoc.v:114162.3-114198.6" + process $proc$libresoc.v:114162$4341 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:114466.5-114466.29" + attribute \src "libresoc.v:114163.5-114163.29" switch \initial - attribute \src "libresoc.v:114466.9-114466.17" + attribute \src "libresoc.v:114163.9-114163.17" case 1'1 case end @@ -178193,14 +177727,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] end - attribute \src "libresoc.v:114502.3-114538.6" - process $proc$libresoc.v:114502$4358 + attribute \src "libresoc.v:114199.3-114235.6" + process $proc$libresoc.v:114199$4342 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:114503.5-114503.29" + attribute \src "libresoc.v:114200.5-114200.29" switch \initial - attribute \src "libresoc.v:114503.9-114503.17" + attribute \src "libresoc.v:114200.9-114200.17" case 1'1 case end @@ -178252,14 +177786,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] end - attribute \src "libresoc.v:114539.3-114575.6" - process $proc$libresoc.v:114539$4359 + attribute \src "libresoc.v:114236.3-114272.6" + process $proc$libresoc.v:114236$4343 assign { } { } assign { } { } assign $0\dec31_dec_sub28_out_sel[2:0] $1\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:114540.5-114540.29" + attribute \src "libresoc.v:114237.5-114237.29" switch \initial - attribute \src "libresoc.v:114540.9-114540.17" + attribute \src "libresoc.v:114237.9-114237.17" case 1'1 case end @@ -178313,144 +177847,144 @@ module \dec31_dec_sub28 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:114581.1-115360.10" +attribute \src "libresoc.v:114278.1-115057.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" attribute \generator "nMigen" module \dec31_dec_sub4 - attribute \src "libresoc.v:115281.3-115293.6" + attribute \src "libresoc.v:114978.3-114990.6" wire width 2 $0\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:115294.3-115306.6" + attribute \src "libresoc.v:114991.3-115003.6" wire width 2 $0\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:115125.3-115137.6" + attribute \src "libresoc.v:114822.3-114834.6" wire width 8 $0\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:115177.3-115189.6" + attribute \src "libresoc.v:114874.3-114886.6" wire $0\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:114943.3-114955.6" + attribute \src "libresoc.v:114640.3-114652.6" wire width 3 $0\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:114956.3-114968.6" + attribute \src "libresoc.v:114653.3-114665.6" wire width 3 $0\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:115112.3-115124.6" + attribute \src "libresoc.v:114809.3-114821.6" wire width 2 $0\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:115164.3-115176.6" + attribute \src "libresoc.v:114861.3-114873.6" wire $0\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:115216.3-115228.6" + attribute \src "libresoc.v:114913.3-114925.6" wire width 5 $0\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:114930.3-114942.6" + attribute \src "libresoc.v:114627.3-114639.6" wire width 14 $0\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:115307.3-115319.6" + attribute \src "libresoc.v:115004.3-115016.6" wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:115320.3-115332.6" + attribute \src "libresoc.v:115017.3-115029.6" wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:115333.3-115345.6" + attribute \src "libresoc.v:115030.3-115042.6" wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:115073.3-115085.6" + attribute \src "libresoc.v:114770.3-114782.6" wire width 7 $0\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:115138.3-115150.6" + attribute \src "libresoc.v:114835.3-114847.6" wire $0\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:115151.3-115163.6" + attribute \src "libresoc.v:114848.3-114860.6" wire $0\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:115229.3-115241.6" + attribute \src "libresoc.v:114926.3-114938.6" wire $0\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:115060.3-115072.6" + attribute \src "libresoc.v:114757.3-114769.6" wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:115255.3-115267.6" + attribute \src "libresoc.v:114952.3-114964.6" wire $0\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:115346.3-115358.6" + attribute \src "libresoc.v:115043.3-115055.6" wire width 3 $0\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:115099.3-115111.6" + attribute \src "libresoc.v:114796.3-114808.6" wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:115203.3-115215.6" + attribute \src "libresoc.v:114900.3-114912.6" wire $0\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:115268.3-115280.6" + attribute \src "libresoc.v:114965.3-114977.6" wire $0\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:115242.3-115254.6" + attribute \src "libresoc.v:114939.3-114951.6" wire $0\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:115190.3-115202.6" + attribute \src "libresoc.v:114887.3-114899.6" wire $0\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:115034.3-115046.6" + attribute \src "libresoc.v:114731.3-114743.6" wire width 3 $0\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:115047.3-115059.6" + attribute \src "libresoc.v:114744.3-114756.6" wire width 3 $0\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:114969.3-114981.6" + attribute \src "libresoc.v:114666.3-114678.6" wire width 3 $0\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:114982.3-114994.6" + attribute \src "libresoc.v:114679.3-114691.6" wire width 3 $0\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:114995.3-115007.6" + attribute \src "libresoc.v:114692.3-114704.6" wire width 3 $0\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:115021.3-115033.6" + attribute \src "libresoc.v:114718.3-114730.6" wire width 3 $0\dec31_dec_sub4_sv_out2[2:0] - attribute \src "libresoc.v:115008.3-115020.6" + attribute \src "libresoc.v:114705.3-114717.6" wire width 3 $0\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:115086.3-115098.6" + attribute \src "libresoc.v:114783.3-114795.6" wire width 2 $0\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:114582.7-114582.20" + attribute \src "libresoc.v:114279.7-114279.20" wire $0\initial[0:0] - attribute \src "libresoc.v:115281.3-115293.6" + attribute \src "libresoc.v:114978.3-114990.6" wire width 2 $1\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:115294.3-115306.6" + attribute \src "libresoc.v:114991.3-115003.6" wire width 2 $1\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:115125.3-115137.6" + attribute \src "libresoc.v:114822.3-114834.6" wire width 8 $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:115177.3-115189.6" + attribute \src "libresoc.v:114874.3-114886.6" wire $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:114943.3-114955.6" + attribute \src "libresoc.v:114640.3-114652.6" wire width 3 $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:114956.3-114968.6" + attribute \src "libresoc.v:114653.3-114665.6" wire width 3 $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:115112.3-115124.6" + attribute \src "libresoc.v:114809.3-114821.6" wire width 2 $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:115164.3-115176.6" + attribute \src "libresoc.v:114861.3-114873.6" wire $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:115216.3-115228.6" + attribute \src "libresoc.v:114913.3-114925.6" wire width 5 $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:114930.3-114942.6" + attribute \src "libresoc.v:114627.3-114639.6" wire width 14 $1\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:115307.3-115319.6" + attribute \src "libresoc.v:115004.3-115016.6" wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:115320.3-115332.6" + attribute \src "libresoc.v:115017.3-115029.6" wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:115333.3-115345.6" + attribute \src "libresoc.v:115030.3-115042.6" wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:115073.3-115085.6" + attribute \src "libresoc.v:114770.3-114782.6" wire width 7 $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:115138.3-115150.6" + attribute \src "libresoc.v:114835.3-114847.6" wire $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:115151.3-115163.6" + attribute \src "libresoc.v:114848.3-114860.6" wire $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:115229.3-115241.6" + attribute \src "libresoc.v:114926.3-114938.6" wire $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:115060.3-115072.6" + attribute \src "libresoc.v:114757.3-114769.6" wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:115255.3-115267.6" + attribute \src "libresoc.v:114952.3-114964.6" wire $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:115346.3-115358.6" + attribute \src "libresoc.v:115043.3-115055.6" wire width 3 $1\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:115099.3-115111.6" + attribute \src "libresoc.v:114796.3-114808.6" wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:115203.3-115215.6" + attribute \src "libresoc.v:114900.3-114912.6" wire $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:115268.3-115280.6" + attribute \src "libresoc.v:114965.3-114977.6" wire $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:115242.3-115254.6" + attribute \src "libresoc.v:114939.3-114951.6" wire $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:115190.3-115202.6" + attribute \src "libresoc.v:114887.3-114899.6" wire $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:115034.3-115046.6" + attribute \src "libresoc.v:114731.3-114743.6" wire width 3 $1\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:115047.3-115059.6" + attribute \src "libresoc.v:114744.3-114756.6" wire width 3 $1\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:114969.3-114981.6" + attribute \src "libresoc.v:114666.3-114678.6" wire width 3 $1\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:114982.3-114994.6" + attribute \src "libresoc.v:114679.3-114691.6" wire width 3 $1\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:114995.3-115007.6" + attribute \src "libresoc.v:114692.3-114704.6" wire width 3 $1\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:115021.3-115033.6" + attribute \src "libresoc.v:114718.3-114730.6" wire width 3 $1\dec31_dec_sub4_sv_out2[2:0] - attribute \src "libresoc.v:115008.3-115020.6" + attribute \src "libresoc.v:114705.3-114717.6" wire width 3 $1\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:115086.3-115098.6" + attribute \src "libresoc.v:114783.3-114795.6" wire width 2 $1\dec31_dec_sub4_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -178762,28 +178296,28 @@ module \dec31_dec_sub4 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub4_upd - attribute \src "libresoc.v:114582.7-114582.15" + attribute \src "libresoc.v:114279.7-114279.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:114582.7-114582.20" - process $proc$libresoc.v:114582$4394 + attribute \src "libresoc.v:114279.7-114279.20" + process $proc$libresoc.v:114279$4378 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:114930.3-114942.6" - process $proc$libresoc.v:114930$4361 + attribute \src "libresoc.v:114627.3-114639.6" + process $proc$libresoc.v:114627$4345 assign { } { } assign { } { } assign $0\dec31_dec_sub4_function_unit[13:0] $1\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:114931.5-114931.29" + attribute \src "libresoc.v:114628.5-114628.29" switch \initial - attribute \src "libresoc.v:114931.9-114931.17" + attribute \src "libresoc.v:114628.9-114628.17" case 1'1 case end @@ -178803,14 +178337,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[13:0] end - attribute \src "libresoc.v:114943.3-114955.6" - process $proc$libresoc.v:114943$4362 + attribute \src "libresoc.v:114640.3-114652.6" + process $proc$libresoc.v:114640$4346 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:114944.5-114944.29" + attribute \src "libresoc.v:114641.5-114641.29" switch \initial - attribute \src "libresoc.v:114944.9-114944.17" + attribute \src "libresoc.v:114641.9-114641.17" case 1'1 case end @@ -178830,14 +178364,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] end - attribute \src "libresoc.v:114956.3-114968.6" - process $proc$libresoc.v:114956$4363 + attribute \src "libresoc.v:114653.3-114665.6" + process $proc$libresoc.v:114653$4347 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:114957.5-114957.29" + attribute \src "libresoc.v:114654.5-114654.29" switch \initial - attribute \src "libresoc.v:114957.9-114957.17" + attribute \src "libresoc.v:114654.9-114654.17" case 1'1 case end @@ -178857,14 +178391,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] end - attribute \src "libresoc.v:114969.3-114981.6" - process $proc$libresoc.v:114969$4364 + attribute \src "libresoc.v:114666.3-114678.6" + process $proc$libresoc.v:114666$4348 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in1[2:0] $1\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:114970.5-114970.29" + attribute \src "libresoc.v:114667.5-114667.29" switch \initial - attribute \src "libresoc.v:114970.9-114970.17" + attribute \src "libresoc.v:114667.9-114667.17" case 1'1 case end @@ -178884,14 +178418,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in1 $0\dec31_dec_sub4_sv_in1[2:0] end - attribute \src "libresoc.v:114982.3-114994.6" - process $proc$libresoc.v:114982$4365 + attribute \src "libresoc.v:114679.3-114691.6" + process $proc$libresoc.v:114679$4349 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in2[2:0] $1\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:114983.5-114983.29" + attribute \src "libresoc.v:114680.5-114680.29" switch \initial - attribute \src "libresoc.v:114983.9-114983.17" + attribute \src "libresoc.v:114680.9-114680.17" case 1'1 case end @@ -178911,14 +178445,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in2 $0\dec31_dec_sub4_sv_in2[2:0] end - attribute \src "libresoc.v:114995.3-115007.6" - process $proc$libresoc.v:114995$4366 + attribute \src "libresoc.v:114692.3-114704.6" + process $proc$libresoc.v:114692$4350 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in3[2:0] $1\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:114996.5-114996.29" + attribute \src "libresoc.v:114693.5-114693.29" switch \initial - attribute \src "libresoc.v:114996.9-114996.17" + attribute \src "libresoc.v:114693.9-114693.17" case 1'1 case end @@ -178938,14 +178472,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in3 $0\dec31_dec_sub4_sv_in3[2:0] end - attribute \src "libresoc.v:115008.3-115020.6" - process $proc$libresoc.v:115008$4367 + attribute \src "libresoc.v:114705.3-114717.6" + process $proc$libresoc.v:114705$4351 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_out[2:0] $1\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:115009.5-115009.29" + attribute \src "libresoc.v:114706.5-114706.29" switch \initial - attribute \src "libresoc.v:115009.9-115009.17" + attribute \src "libresoc.v:114706.9-114706.17" case 1'1 case end @@ -178965,14 +178499,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_out $0\dec31_dec_sub4_sv_out[2:0] end - attribute \src "libresoc.v:115021.3-115033.6" - process $proc$libresoc.v:115021$4368 + attribute \src "libresoc.v:114718.3-114730.6" + process $proc$libresoc.v:114718$4352 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_out2[2:0] $1\dec31_dec_sub4_sv_out2[2:0] - attribute \src "libresoc.v:115022.5-115022.29" + attribute \src "libresoc.v:114719.5-114719.29" switch \initial - attribute \src "libresoc.v:115022.9-115022.17" + attribute \src "libresoc.v:114719.9-114719.17" case 1'1 case end @@ -178992,14 +178526,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_out2 $0\dec31_dec_sub4_sv_out2[2:0] end - attribute \src "libresoc.v:115034.3-115046.6" - process $proc$libresoc.v:115034$4369 + attribute \src "libresoc.v:114731.3-114743.6" + process $proc$libresoc.v:114731$4353 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_in[2:0] $1\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:115035.5-115035.29" + attribute \src "libresoc.v:114732.5-114732.29" switch \initial - attribute \src "libresoc.v:115035.9-115035.17" + attribute \src "libresoc.v:114732.9-114732.17" case 1'1 case end @@ -179019,14 +178553,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_cr_in $0\dec31_dec_sub4_sv_cr_in[2:0] end - attribute \src "libresoc.v:115047.3-115059.6" - process $proc$libresoc.v:115047$4370 + attribute \src "libresoc.v:114744.3-114756.6" + process $proc$libresoc.v:114744$4354 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_out[2:0] $1\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:115048.5-115048.29" + attribute \src "libresoc.v:114745.5-114745.29" switch \initial - attribute \src "libresoc.v:115048.9-115048.17" + attribute \src "libresoc.v:114745.9-114745.17" case 1'1 case end @@ -179046,14 +178580,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_cr_out $0\dec31_dec_sub4_sv_cr_out[2:0] end - attribute \src "libresoc.v:115060.3-115072.6" - process $proc$libresoc.v:115060$4371 + attribute \src "libresoc.v:114757.3-114769.6" + process $proc$libresoc.v:114757$4355 assign { } { } assign { } { } assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:115061.5-115061.29" + attribute \src "libresoc.v:114758.5-114758.29" switch \initial - attribute \src "libresoc.v:115061.9-115061.17" + attribute \src "libresoc.v:114758.9-114758.17" case 1'1 case end @@ -179073,14 +178607,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] end - attribute \src "libresoc.v:115073.3-115085.6" - process $proc$libresoc.v:115073$4372 + attribute \src "libresoc.v:114770.3-114782.6" + process $proc$libresoc.v:114770$4356 assign { } { } assign { } { } assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:115074.5-115074.29" + attribute \src "libresoc.v:114771.5-114771.29" switch \initial - attribute \src "libresoc.v:115074.9-115074.17" + attribute \src "libresoc.v:114771.9-114771.17" case 1'1 case end @@ -179100,14 +178634,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] end - attribute \src "libresoc.v:115086.3-115098.6" - process $proc$libresoc.v:115086$4373 + attribute \src "libresoc.v:114783.3-114795.6" + process $proc$libresoc.v:114783$4357 assign { } { } assign { } { } assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:115087.5-115087.29" + attribute \src "libresoc.v:114784.5-114784.29" switch \initial - attribute \src "libresoc.v:115087.9-115087.17" + attribute \src "libresoc.v:114784.9-114784.17" case 1'1 case end @@ -179127,14 +178661,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] end - attribute \src "libresoc.v:115099.3-115111.6" - process $proc$libresoc.v:115099$4374 + attribute \src "libresoc.v:114796.3-114808.6" + process $proc$libresoc.v:114796$4358 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:115100.5-115100.29" + attribute \src "libresoc.v:114797.5-114797.29" switch \initial - attribute \src "libresoc.v:115100.9-115100.17" + attribute \src "libresoc.v:114797.9-114797.17" case 1'1 case end @@ -179154,14 +178688,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] end - attribute \src "libresoc.v:115112.3-115124.6" - process $proc$libresoc.v:115112$4375 + attribute \src "libresoc.v:114809.3-114821.6" + process $proc$libresoc.v:114809$4359 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:115113.5-115113.29" + attribute \src "libresoc.v:114810.5-114810.29" switch \initial - attribute \src "libresoc.v:115113.9-115113.17" + attribute \src "libresoc.v:114810.9-114810.17" case 1'1 case end @@ -179181,14 +178715,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] end - attribute \src "libresoc.v:115125.3-115137.6" - process $proc$libresoc.v:115125$4376 + attribute \src "libresoc.v:114822.3-114834.6" + process $proc$libresoc.v:114822$4360 assign { } { } assign { } { } assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:115126.5-115126.29" + attribute \src "libresoc.v:114823.5-114823.29" switch \initial - attribute \src "libresoc.v:115126.9-115126.17" + attribute \src "libresoc.v:114823.9-114823.17" case 1'1 case end @@ -179208,14 +178742,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] end - attribute \src "libresoc.v:115138.3-115150.6" - process $proc$libresoc.v:115138$4377 + attribute \src "libresoc.v:114835.3-114847.6" + process $proc$libresoc.v:114835$4361 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:115139.5-115139.29" + attribute \src "libresoc.v:114836.5-114836.29" switch \initial - attribute \src "libresoc.v:115139.9-115139.17" + attribute \src "libresoc.v:114836.9-114836.17" case 1'1 case end @@ -179235,14 +178769,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] end - attribute \src "libresoc.v:115151.3-115163.6" - process $proc$libresoc.v:115151$4378 + attribute \src "libresoc.v:114848.3-114860.6" + process $proc$libresoc.v:114848$4362 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:115152.5-115152.29" + attribute \src "libresoc.v:114849.5-114849.29" switch \initial - attribute \src "libresoc.v:115152.9-115152.17" + attribute \src "libresoc.v:114849.9-114849.17" case 1'1 case end @@ -179262,14 +178796,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] end - attribute \src "libresoc.v:115164.3-115176.6" - process $proc$libresoc.v:115164$4379 + attribute \src "libresoc.v:114861.3-114873.6" + process $proc$libresoc.v:114861$4363 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:115165.5-115165.29" + attribute \src "libresoc.v:114862.5-114862.29" switch \initial - attribute \src "libresoc.v:115165.9-115165.17" + attribute \src "libresoc.v:114862.9-114862.17" case 1'1 case end @@ -179289,14 +178823,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] end - attribute \src "libresoc.v:115177.3-115189.6" - process $proc$libresoc.v:115177$4380 + attribute \src "libresoc.v:114874.3-114886.6" + process $proc$libresoc.v:114874$4364 assign { } { } assign { } { } assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:115178.5-115178.29" + attribute \src "libresoc.v:114875.5-114875.29" switch \initial - attribute \src "libresoc.v:115178.9-115178.17" + attribute \src "libresoc.v:114875.9-114875.17" case 1'1 case end @@ -179316,14 +178850,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] end - attribute \src "libresoc.v:115190.3-115202.6" - process $proc$libresoc.v:115190$4381 + attribute \src "libresoc.v:114887.3-114899.6" + process $proc$libresoc.v:114887$4365 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:115191.5-115191.29" + attribute \src "libresoc.v:114888.5-114888.29" switch \initial - attribute \src "libresoc.v:115191.9-115191.17" + attribute \src "libresoc.v:114888.9-114888.17" case 1'1 case end @@ -179343,14 +178877,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] end - attribute \src "libresoc.v:115203.3-115215.6" - process $proc$libresoc.v:115203$4382 + attribute \src "libresoc.v:114900.3-114912.6" + process $proc$libresoc.v:114900$4366 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:115204.5-115204.29" + attribute \src "libresoc.v:114901.5-114901.29" switch \initial - attribute \src "libresoc.v:115204.9-115204.17" + attribute \src "libresoc.v:114901.9-114901.17" case 1'1 case end @@ -179370,14 +178904,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] end - attribute \src "libresoc.v:115216.3-115228.6" - process $proc$libresoc.v:115216$4383 + attribute \src "libresoc.v:114913.3-114925.6" + process $proc$libresoc.v:114913$4367 assign { } { } assign { } { } assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:115217.5-115217.29" + attribute \src "libresoc.v:114914.5-114914.29" switch \initial - attribute \src "libresoc.v:115217.9-115217.17" + attribute \src "libresoc.v:114914.9-114914.17" case 1'1 case end @@ -179397,14 +178931,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] end - attribute \src "libresoc.v:115229.3-115241.6" - process $proc$libresoc.v:115229$4384 + attribute \src "libresoc.v:114926.3-114938.6" + process $proc$libresoc.v:114926$4368 assign { } { } assign { } { } assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:115230.5-115230.29" + attribute \src "libresoc.v:114927.5-114927.29" switch \initial - attribute \src "libresoc.v:115230.9-115230.17" + attribute \src "libresoc.v:114927.9-114927.17" case 1'1 case end @@ -179424,14 +178958,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] end - attribute \src "libresoc.v:115242.3-115254.6" - process $proc$libresoc.v:115242$4385 + attribute \src "libresoc.v:114939.3-114951.6" + process $proc$libresoc.v:114939$4369 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:115243.5-115243.29" + attribute \src "libresoc.v:114940.5-114940.29" switch \initial - attribute \src "libresoc.v:115243.9-115243.17" + attribute \src "libresoc.v:114940.9-114940.17" case 1'1 case end @@ -179451,14 +178985,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] end - attribute \src "libresoc.v:115255.3-115267.6" - process $proc$libresoc.v:115255$4386 + attribute \src "libresoc.v:114952.3-114964.6" + process $proc$libresoc.v:114952$4370 assign { } { } assign { } { } assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:115256.5-115256.29" + attribute \src "libresoc.v:114953.5-114953.29" switch \initial - attribute \src "libresoc.v:115256.9-115256.17" + attribute \src "libresoc.v:114953.9-114953.17" case 1'1 case end @@ -179478,14 +179012,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] end - attribute \src "libresoc.v:115268.3-115280.6" - process $proc$libresoc.v:115268$4387 + attribute \src "libresoc.v:114965.3-114977.6" + process $proc$libresoc.v:114965$4371 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:115269.5-115269.29" + attribute \src "libresoc.v:114966.5-114966.29" switch \initial - attribute \src "libresoc.v:115269.9-115269.17" + attribute \src "libresoc.v:114966.9-114966.17" case 1'1 case end @@ -179505,14 +179039,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] end - attribute \src "libresoc.v:115281.3-115293.6" - process $proc$libresoc.v:115281$4388 + attribute \src "libresoc.v:114978.3-114990.6" + process $proc$libresoc.v:114978$4372 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Etype[1:0] $1\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:115282.5-115282.29" + attribute \src "libresoc.v:114979.5-114979.29" switch \initial - attribute \src "libresoc.v:115282.9-115282.17" + attribute \src "libresoc.v:114979.9-114979.17" case 1'1 case end @@ -179532,14 +179066,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_SV_Etype $0\dec31_dec_sub4_SV_Etype[1:0] end - attribute \src "libresoc.v:115294.3-115306.6" - process $proc$libresoc.v:115294$4389 + attribute \src "libresoc.v:114991.3-115003.6" + process $proc$libresoc.v:114991$4373 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Ptype[1:0] $1\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:115295.5-115295.29" + attribute \src "libresoc.v:114992.5-114992.29" switch \initial - attribute \src "libresoc.v:115295.9-115295.17" + attribute \src "libresoc.v:114992.9-114992.17" case 1'1 case end @@ -179559,14 +179093,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_SV_Ptype $0\dec31_dec_sub4_SV_Ptype[1:0] end - attribute \src "libresoc.v:115307.3-115319.6" - process $proc$libresoc.v:115307$4390 + attribute \src "libresoc.v:115004.3-115016.6" + process $proc$libresoc.v:115004$4374 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:115308.5-115308.29" + attribute \src "libresoc.v:115005.5-115005.29" switch \initial - attribute \src "libresoc.v:115308.9-115308.17" + attribute \src "libresoc.v:115005.9-115005.17" case 1'1 case end @@ -179586,14 +179120,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] end - attribute \src "libresoc.v:115320.3-115332.6" - process $proc$libresoc.v:115320$4391 + attribute \src "libresoc.v:115017.3-115029.6" + process $proc$libresoc.v:115017$4375 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:115321.5-115321.29" + attribute \src "libresoc.v:115018.5-115018.29" switch \initial - attribute \src "libresoc.v:115321.9-115321.17" + attribute \src "libresoc.v:115018.9-115018.17" case 1'1 case end @@ -179613,14 +179147,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] end - attribute \src "libresoc.v:115333.3-115345.6" - process $proc$libresoc.v:115333$4392 + attribute \src "libresoc.v:115030.3-115042.6" + process $proc$libresoc.v:115030$4376 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:115334.5-115334.29" + attribute \src "libresoc.v:115031.5-115031.29" switch \initial - attribute \src "libresoc.v:115334.9-115334.17" + attribute \src "libresoc.v:115031.9-115031.17" case 1'1 case end @@ -179640,14 +179174,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] end - attribute \src "libresoc.v:115346.3-115358.6" - process $proc$libresoc.v:115346$4393 + attribute \src "libresoc.v:115043.3-115055.6" + process $proc$libresoc.v:115043$4377 assign { } { } assign { } { } assign $0\dec31_dec_sub4_out_sel[2:0] $1\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:115347.5-115347.29" + attribute \src "libresoc.v:115044.5-115044.29" switch \initial - attribute \src "libresoc.v:115347.9-115347.17" + attribute \src "libresoc.v:115044.9-115044.17" case 1'1 case end @@ -179669,144 +179203,144 @@ module \dec31_dec_sub4 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:115364.1-117133.10" +attribute \src "libresoc.v:115061.1-116830.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" attribute \generator "nMigen" module \dec31_dec_sub8 - attribute \src "libresoc.v:116874.3-116916.6" + attribute \src "libresoc.v:116571.3-116613.6" wire width 2 $0\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:116917.3-116959.6" + attribute \src "libresoc.v:116614.3-116656.6" wire width 2 $0\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:116358.3-116400.6" + attribute \src "libresoc.v:116055.3-116097.6" wire width 8 $0\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:116530.3-116572.6" + attribute \src "libresoc.v:116227.3-116269.6" wire $0\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:115756.3-115798.6" + attribute \src "libresoc.v:115453.3-115495.6" wire width 3 $0\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:115799.3-115841.6" + attribute \src "libresoc.v:115496.3-115538.6" wire width 3 $0\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:116315.3-116357.6" + attribute \src "libresoc.v:116012.3-116054.6" wire width 2 $0\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:116487.3-116529.6" + attribute \src "libresoc.v:116184.3-116226.6" wire $0\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:116659.3-116701.6" + attribute \src "libresoc.v:116356.3-116398.6" wire width 5 $0\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:115713.3-115755.6" + attribute \src "libresoc.v:115410.3-115452.6" wire width 14 $0\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:116960.3-117002.6" + attribute \src "libresoc.v:116657.3-116699.6" wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:117003.3-117045.6" + attribute \src "libresoc.v:116700.3-116742.6" wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:117046.3-117088.6" + attribute \src "libresoc.v:116743.3-116785.6" wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:116186.3-116228.6" + attribute \src "libresoc.v:115883.3-115925.6" wire width 7 $0\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:116401.3-116443.6" + attribute \src "libresoc.v:116098.3-116140.6" wire $0\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:116444.3-116486.6" + attribute \src "libresoc.v:116141.3-116183.6" wire $0\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:116702.3-116744.6" + attribute \src "libresoc.v:116399.3-116441.6" wire $0\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:116143.3-116185.6" + attribute \src "libresoc.v:115840.3-115882.6" wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:116788.3-116830.6" + attribute \src "libresoc.v:116485.3-116527.6" wire $0\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:117089.3-117131.6" + attribute \src "libresoc.v:116786.3-116828.6" wire width 3 $0\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:116272.3-116314.6" + attribute \src "libresoc.v:115969.3-116011.6" wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:116616.3-116658.6" + attribute \src "libresoc.v:116313.3-116355.6" wire $0\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:116831.3-116873.6" + attribute \src "libresoc.v:116528.3-116570.6" wire $0\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:116745.3-116787.6" + attribute \src "libresoc.v:116442.3-116484.6" wire $0\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:116573.3-116615.6" + attribute \src "libresoc.v:116270.3-116312.6" wire $0\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:116057.3-116099.6" + attribute \src "libresoc.v:115754.3-115796.6" wire width 3 $0\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:116100.3-116142.6" + attribute \src "libresoc.v:115797.3-115839.6" wire width 3 $0\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:115842.3-115884.6" + attribute \src "libresoc.v:115539.3-115581.6" wire width 3 $0\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:115885.3-115927.6" + attribute \src "libresoc.v:115582.3-115624.6" wire width 3 $0\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:115928.3-115970.6" + attribute \src "libresoc.v:115625.3-115667.6" wire width 3 $0\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:116014.3-116056.6" + attribute \src "libresoc.v:115711.3-115753.6" wire width 3 $0\dec31_dec_sub8_sv_out2[2:0] - attribute \src "libresoc.v:115971.3-116013.6" + attribute \src "libresoc.v:115668.3-115710.6" wire width 3 $0\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:116229.3-116271.6" + attribute \src "libresoc.v:115926.3-115968.6" wire width 2 $0\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:115365.7-115365.20" + attribute \src "libresoc.v:115062.7-115062.20" wire $0\initial[0:0] - attribute \src "libresoc.v:116874.3-116916.6" + attribute \src "libresoc.v:116571.3-116613.6" wire width 2 $1\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:116917.3-116959.6" + attribute \src "libresoc.v:116614.3-116656.6" wire width 2 $1\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:116358.3-116400.6" + attribute \src "libresoc.v:116055.3-116097.6" wire width 8 $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:116530.3-116572.6" + attribute \src "libresoc.v:116227.3-116269.6" wire $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:115756.3-115798.6" + attribute \src "libresoc.v:115453.3-115495.6" wire width 3 $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:115799.3-115841.6" + attribute \src "libresoc.v:115496.3-115538.6" wire width 3 $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:116315.3-116357.6" + attribute \src "libresoc.v:116012.3-116054.6" wire width 2 $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:116487.3-116529.6" + attribute \src "libresoc.v:116184.3-116226.6" wire $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:116659.3-116701.6" + attribute \src "libresoc.v:116356.3-116398.6" wire width 5 $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:115713.3-115755.6" + attribute \src "libresoc.v:115410.3-115452.6" wire width 14 $1\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:116960.3-117002.6" + attribute \src "libresoc.v:116657.3-116699.6" wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:117003.3-117045.6" + attribute \src "libresoc.v:116700.3-116742.6" wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:117046.3-117088.6" + attribute \src "libresoc.v:116743.3-116785.6" wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:116186.3-116228.6" + attribute \src "libresoc.v:115883.3-115925.6" wire width 7 $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:116401.3-116443.6" + attribute \src "libresoc.v:116098.3-116140.6" wire $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:116444.3-116486.6" + attribute \src "libresoc.v:116141.3-116183.6" wire $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:116702.3-116744.6" + attribute \src "libresoc.v:116399.3-116441.6" wire $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:116143.3-116185.6" + attribute \src "libresoc.v:115840.3-115882.6" wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:116788.3-116830.6" + attribute \src "libresoc.v:116485.3-116527.6" wire $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:117089.3-117131.6" + attribute \src "libresoc.v:116786.3-116828.6" wire width 3 $1\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:116272.3-116314.6" + attribute \src "libresoc.v:115969.3-116011.6" wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:116616.3-116658.6" + attribute \src "libresoc.v:116313.3-116355.6" wire $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:116831.3-116873.6" + attribute \src "libresoc.v:116528.3-116570.6" wire $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:116745.3-116787.6" + attribute \src "libresoc.v:116442.3-116484.6" wire $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:116573.3-116615.6" + attribute \src "libresoc.v:116270.3-116312.6" wire $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:116057.3-116099.6" + attribute \src "libresoc.v:115754.3-115796.6" wire width 3 $1\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:116100.3-116142.6" + attribute \src "libresoc.v:115797.3-115839.6" wire width 3 $1\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:115842.3-115884.6" + attribute \src "libresoc.v:115539.3-115581.6" wire width 3 $1\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:115885.3-115927.6" + attribute \src "libresoc.v:115582.3-115624.6" wire width 3 $1\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:115928.3-115970.6" + attribute \src "libresoc.v:115625.3-115667.6" wire width 3 $1\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:116014.3-116056.6" + attribute \src "libresoc.v:115711.3-115753.6" wire width 3 $1\dec31_dec_sub8_sv_out2[2:0] - attribute \src "libresoc.v:115971.3-116013.6" + attribute \src "libresoc.v:115668.3-115710.6" wire width 3 $1\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:116229.3-116271.6" + attribute \src "libresoc.v:115926.3-115968.6" wire width 2 $1\dec31_dec_sub8_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -180118,28 +179652,28 @@ module \dec31_dec_sub8 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub8_upd - attribute \src "libresoc.v:115365.7-115365.15" + attribute \src "libresoc.v:115062.7-115062.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:115365.7-115365.20" - process $proc$libresoc.v:115365$4428 + attribute \src "libresoc.v:115062.7-115062.20" + process $proc$libresoc.v:115062$4412 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:115713.3-115755.6" - process $proc$libresoc.v:115713$4395 + attribute \src "libresoc.v:115410.3-115452.6" + process $proc$libresoc.v:115410$4379 assign { } { } assign { } { } assign $0\dec31_dec_sub8_function_unit[13:0] $1\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:115714.5-115714.29" + attribute \src "libresoc.v:115411.5-115411.29" switch \initial - attribute \src "libresoc.v:115714.9-115714.17" + attribute \src "libresoc.v:115411.9-115411.17" case 1'1 case end @@ -180199,14 +179733,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[13:0] end - attribute \src "libresoc.v:115756.3-115798.6" - process $proc$libresoc.v:115756$4396 + attribute \src "libresoc.v:115453.3-115495.6" + process $proc$libresoc.v:115453$4380 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:115757.5-115757.29" + attribute \src "libresoc.v:115454.5-115454.29" switch \initial - attribute \src "libresoc.v:115757.9-115757.17" + attribute \src "libresoc.v:115454.9-115454.17" case 1'1 case end @@ -180266,14 +179800,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] end - attribute \src "libresoc.v:115799.3-115841.6" - process $proc$libresoc.v:115799$4397 + attribute \src "libresoc.v:115496.3-115538.6" + process $proc$libresoc.v:115496$4381 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:115800.5-115800.29" + attribute \src "libresoc.v:115497.5-115497.29" switch \initial - attribute \src "libresoc.v:115800.9-115800.17" + attribute \src "libresoc.v:115497.9-115497.17" case 1'1 case end @@ -180333,14 +179867,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] end - attribute \src "libresoc.v:115842.3-115884.6" - process $proc$libresoc.v:115842$4398 + attribute \src "libresoc.v:115539.3-115581.6" + process $proc$libresoc.v:115539$4382 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in1[2:0] $1\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:115843.5-115843.29" + attribute \src "libresoc.v:115540.5-115540.29" switch \initial - attribute \src "libresoc.v:115843.9-115843.17" + attribute \src "libresoc.v:115540.9-115540.17" case 1'1 case end @@ -180400,14 +179934,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in1 $0\dec31_dec_sub8_sv_in1[2:0] end - attribute \src "libresoc.v:115885.3-115927.6" - process $proc$libresoc.v:115885$4399 + attribute \src "libresoc.v:115582.3-115624.6" + process $proc$libresoc.v:115582$4383 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in2[2:0] $1\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:115886.5-115886.29" + attribute \src "libresoc.v:115583.5-115583.29" switch \initial - attribute \src "libresoc.v:115886.9-115886.17" + attribute \src "libresoc.v:115583.9-115583.17" case 1'1 case end @@ -180467,14 +180001,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in2 $0\dec31_dec_sub8_sv_in2[2:0] end - attribute \src "libresoc.v:115928.3-115970.6" - process $proc$libresoc.v:115928$4400 + attribute \src "libresoc.v:115625.3-115667.6" + process $proc$libresoc.v:115625$4384 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in3[2:0] $1\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:115929.5-115929.29" + attribute \src "libresoc.v:115626.5-115626.29" switch \initial - attribute \src "libresoc.v:115929.9-115929.17" + attribute \src "libresoc.v:115626.9-115626.17" case 1'1 case end @@ -180534,14 +180068,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in3 $0\dec31_dec_sub8_sv_in3[2:0] end - attribute \src "libresoc.v:115971.3-116013.6" - process $proc$libresoc.v:115971$4401 + attribute \src "libresoc.v:115668.3-115710.6" + process $proc$libresoc.v:115668$4385 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_out[2:0] $1\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:115972.5-115972.29" + attribute \src "libresoc.v:115669.5-115669.29" switch \initial - attribute \src "libresoc.v:115972.9-115972.17" + attribute \src "libresoc.v:115669.9-115669.17" case 1'1 case end @@ -180601,14 +180135,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_out $0\dec31_dec_sub8_sv_out[2:0] end - attribute \src "libresoc.v:116014.3-116056.6" - process $proc$libresoc.v:116014$4402 + attribute \src "libresoc.v:115711.3-115753.6" + process $proc$libresoc.v:115711$4386 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_out2[2:0] $1\dec31_dec_sub8_sv_out2[2:0] - attribute \src "libresoc.v:116015.5-116015.29" + attribute \src "libresoc.v:115712.5-115712.29" switch \initial - attribute \src "libresoc.v:116015.9-116015.17" + attribute \src "libresoc.v:115712.9-115712.17" case 1'1 case end @@ -180668,14 +180202,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_out2 $0\dec31_dec_sub8_sv_out2[2:0] end - attribute \src "libresoc.v:116057.3-116099.6" - process $proc$libresoc.v:116057$4403 + attribute \src "libresoc.v:115754.3-115796.6" + process $proc$libresoc.v:115754$4387 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_in[2:0] $1\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:116058.5-116058.29" + attribute \src "libresoc.v:115755.5-115755.29" switch \initial - attribute \src "libresoc.v:116058.9-116058.17" + attribute \src "libresoc.v:115755.9-115755.17" case 1'1 case end @@ -180735,14 +180269,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_cr_in $0\dec31_dec_sub8_sv_cr_in[2:0] end - attribute \src "libresoc.v:116100.3-116142.6" - process $proc$libresoc.v:116100$4404 + attribute \src "libresoc.v:115797.3-115839.6" + process $proc$libresoc.v:115797$4388 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_out[2:0] $1\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:116101.5-116101.29" + attribute \src "libresoc.v:115798.5-115798.29" switch \initial - attribute \src "libresoc.v:116101.9-116101.17" + attribute \src "libresoc.v:115798.9-115798.17" case 1'1 case end @@ -180802,14 +180336,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_cr_out $0\dec31_dec_sub8_sv_cr_out[2:0] end - attribute \src "libresoc.v:116143.3-116185.6" - process $proc$libresoc.v:116143$4405 + attribute \src "libresoc.v:115840.3-115882.6" + process $proc$libresoc.v:115840$4389 assign { } { } assign { } { } assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:116144.5-116144.29" + attribute \src "libresoc.v:115841.5-115841.29" switch \initial - attribute \src "libresoc.v:116144.9-116144.17" + attribute \src "libresoc.v:115841.9-115841.17" case 1'1 case end @@ -180869,14 +180403,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] end - attribute \src "libresoc.v:116186.3-116228.6" - process $proc$libresoc.v:116186$4406 + attribute \src "libresoc.v:115883.3-115925.6" + process $proc$libresoc.v:115883$4390 assign { } { } assign { } { } assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:116187.5-116187.29" + attribute \src "libresoc.v:115884.5-115884.29" switch \initial - attribute \src "libresoc.v:116187.9-116187.17" + attribute \src "libresoc.v:115884.9-115884.17" case 1'1 case end @@ -180936,14 +180470,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] end - attribute \src "libresoc.v:116229.3-116271.6" - process $proc$libresoc.v:116229$4407 + attribute \src "libresoc.v:115926.3-115968.6" + process $proc$libresoc.v:115926$4391 assign { } { } assign { } { } assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:116230.5-116230.29" + attribute \src "libresoc.v:115927.5-115927.29" switch \initial - attribute \src "libresoc.v:116230.9-116230.17" + attribute \src "libresoc.v:115927.9-115927.17" case 1'1 case end @@ -181003,14 +180537,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] end - attribute \src "libresoc.v:116272.3-116314.6" - process $proc$libresoc.v:116272$4408 + attribute \src "libresoc.v:115969.3-116011.6" + process $proc$libresoc.v:115969$4392 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:116273.5-116273.29" + attribute \src "libresoc.v:115970.5-115970.29" switch \initial - attribute \src "libresoc.v:116273.9-116273.17" + attribute \src "libresoc.v:115970.9-115970.17" case 1'1 case end @@ -181070,14 +180604,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] end - attribute \src "libresoc.v:116315.3-116357.6" - process $proc$libresoc.v:116315$4409 + attribute \src "libresoc.v:116012.3-116054.6" + process $proc$libresoc.v:116012$4393 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:116316.5-116316.29" + attribute \src "libresoc.v:116013.5-116013.29" switch \initial - attribute \src "libresoc.v:116316.9-116316.17" + attribute \src "libresoc.v:116013.9-116013.17" case 1'1 case end @@ -181137,14 +180671,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] end - attribute \src "libresoc.v:116358.3-116400.6" - process $proc$libresoc.v:116358$4410 + attribute \src "libresoc.v:116055.3-116097.6" + process $proc$libresoc.v:116055$4394 assign { } { } assign { } { } assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:116359.5-116359.29" + attribute \src "libresoc.v:116056.5-116056.29" switch \initial - attribute \src "libresoc.v:116359.9-116359.17" + attribute \src "libresoc.v:116056.9-116056.17" case 1'1 case end @@ -181204,14 +180738,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] end - attribute \src "libresoc.v:116401.3-116443.6" - process $proc$libresoc.v:116401$4411 + attribute \src "libresoc.v:116098.3-116140.6" + process $proc$libresoc.v:116098$4395 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:116402.5-116402.29" + attribute \src "libresoc.v:116099.5-116099.29" switch \initial - attribute \src "libresoc.v:116402.9-116402.17" + attribute \src "libresoc.v:116099.9-116099.17" case 1'1 case end @@ -181271,14 +180805,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] end - attribute \src "libresoc.v:116444.3-116486.6" - process $proc$libresoc.v:116444$4412 + attribute \src "libresoc.v:116141.3-116183.6" + process $proc$libresoc.v:116141$4396 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:116445.5-116445.29" + attribute \src "libresoc.v:116142.5-116142.29" switch \initial - attribute \src "libresoc.v:116445.9-116445.17" + attribute \src "libresoc.v:116142.9-116142.17" case 1'1 case end @@ -181338,14 +180872,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] end - attribute \src "libresoc.v:116487.3-116529.6" - process $proc$libresoc.v:116487$4413 + attribute \src "libresoc.v:116184.3-116226.6" + process $proc$libresoc.v:116184$4397 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:116488.5-116488.29" + attribute \src "libresoc.v:116185.5-116185.29" switch \initial - attribute \src "libresoc.v:116488.9-116488.17" + attribute \src "libresoc.v:116185.9-116185.17" case 1'1 case end @@ -181405,14 +180939,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] end - attribute \src "libresoc.v:116530.3-116572.6" - process $proc$libresoc.v:116530$4414 + attribute \src "libresoc.v:116227.3-116269.6" + process $proc$libresoc.v:116227$4398 assign { } { } assign { } { } assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:116531.5-116531.29" + attribute \src "libresoc.v:116228.5-116228.29" switch \initial - attribute \src "libresoc.v:116531.9-116531.17" + attribute \src "libresoc.v:116228.9-116228.17" case 1'1 case end @@ -181472,14 +181006,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] end - attribute \src "libresoc.v:116573.3-116615.6" - process $proc$libresoc.v:116573$4415 + attribute \src "libresoc.v:116270.3-116312.6" + process $proc$libresoc.v:116270$4399 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:116574.5-116574.29" + attribute \src "libresoc.v:116271.5-116271.29" switch \initial - attribute \src "libresoc.v:116574.9-116574.17" + attribute \src "libresoc.v:116271.9-116271.17" case 1'1 case end @@ -181539,14 +181073,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] end - attribute \src "libresoc.v:116616.3-116658.6" - process $proc$libresoc.v:116616$4416 + attribute \src "libresoc.v:116313.3-116355.6" + process $proc$libresoc.v:116313$4400 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:116617.5-116617.29" + attribute \src "libresoc.v:116314.5-116314.29" switch \initial - attribute \src "libresoc.v:116617.9-116617.17" + attribute \src "libresoc.v:116314.9-116314.17" case 1'1 case end @@ -181606,14 +181140,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] end - attribute \src "libresoc.v:116659.3-116701.6" - process $proc$libresoc.v:116659$4417 + attribute \src "libresoc.v:116356.3-116398.6" + process $proc$libresoc.v:116356$4401 assign { } { } assign { } { } assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:116660.5-116660.29" + attribute \src "libresoc.v:116357.5-116357.29" switch \initial - attribute \src "libresoc.v:116660.9-116660.17" + attribute \src "libresoc.v:116357.9-116357.17" case 1'1 case end @@ -181673,14 +181207,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] end - attribute \src "libresoc.v:116702.3-116744.6" - process $proc$libresoc.v:116702$4418 + attribute \src "libresoc.v:116399.3-116441.6" + process $proc$libresoc.v:116399$4402 assign { } { } assign { } { } assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:116703.5-116703.29" + attribute \src "libresoc.v:116400.5-116400.29" switch \initial - attribute \src "libresoc.v:116703.9-116703.17" + attribute \src "libresoc.v:116400.9-116400.17" case 1'1 case end @@ -181740,14 +181274,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] end - attribute \src "libresoc.v:116745.3-116787.6" - process $proc$libresoc.v:116745$4419 + attribute \src "libresoc.v:116442.3-116484.6" + process $proc$libresoc.v:116442$4403 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:116746.5-116746.29" + attribute \src "libresoc.v:116443.5-116443.29" switch \initial - attribute \src "libresoc.v:116746.9-116746.17" + attribute \src "libresoc.v:116443.9-116443.17" case 1'1 case end @@ -181807,14 +181341,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] end - attribute \src "libresoc.v:116788.3-116830.6" - process $proc$libresoc.v:116788$4420 + attribute \src "libresoc.v:116485.3-116527.6" + process $proc$libresoc.v:116485$4404 assign { } { } assign { } { } assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:116789.5-116789.29" + attribute \src "libresoc.v:116486.5-116486.29" switch \initial - attribute \src "libresoc.v:116789.9-116789.17" + attribute \src "libresoc.v:116486.9-116486.17" case 1'1 case end @@ -181874,14 +181408,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] end - attribute \src "libresoc.v:116831.3-116873.6" - process $proc$libresoc.v:116831$4421 + attribute \src "libresoc.v:116528.3-116570.6" + process $proc$libresoc.v:116528$4405 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:116832.5-116832.29" + attribute \src "libresoc.v:116529.5-116529.29" switch \initial - attribute \src "libresoc.v:116832.9-116832.17" + attribute \src "libresoc.v:116529.9-116529.17" case 1'1 case end @@ -181941,14 +181475,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] end - attribute \src "libresoc.v:116874.3-116916.6" - process $proc$libresoc.v:116874$4422 + attribute \src "libresoc.v:116571.3-116613.6" + process $proc$libresoc.v:116571$4406 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Etype[1:0] $1\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:116875.5-116875.29" + attribute \src "libresoc.v:116572.5-116572.29" switch \initial - attribute \src "libresoc.v:116875.9-116875.17" + attribute \src "libresoc.v:116572.9-116572.17" case 1'1 case end @@ -182008,14 +181542,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_SV_Etype $0\dec31_dec_sub8_SV_Etype[1:0] end - attribute \src "libresoc.v:116917.3-116959.6" - process $proc$libresoc.v:116917$4423 + attribute \src "libresoc.v:116614.3-116656.6" + process $proc$libresoc.v:116614$4407 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Ptype[1:0] $1\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:116918.5-116918.29" + attribute \src "libresoc.v:116615.5-116615.29" switch \initial - attribute \src "libresoc.v:116918.9-116918.17" + attribute \src "libresoc.v:116615.9-116615.17" case 1'1 case end @@ -182075,14 +181609,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_SV_Ptype $0\dec31_dec_sub8_SV_Ptype[1:0] end - attribute \src "libresoc.v:116960.3-117002.6" - process $proc$libresoc.v:116960$4424 + attribute \src "libresoc.v:116657.3-116699.6" + process $proc$libresoc.v:116657$4408 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:116961.5-116961.29" + attribute \src "libresoc.v:116658.5-116658.29" switch \initial - attribute \src "libresoc.v:116961.9-116961.17" + attribute \src "libresoc.v:116658.9-116658.17" case 1'1 case end @@ -182142,14 +181676,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] end - attribute \src "libresoc.v:117003.3-117045.6" - process $proc$libresoc.v:117003$4425 + attribute \src "libresoc.v:116700.3-116742.6" + process $proc$libresoc.v:116700$4409 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:117004.5-117004.29" + attribute \src "libresoc.v:116701.5-116701.29" switch \initial - attribute \src "libresoc.v:117004.9-117004.17" + attribute \src "libresoc.v:116701.9-116701.17" case 1'1 case end @@ -182209,14 +181743,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] end - attribute \src "libresoc.v:117046.3-117088.6" - process $proc$libresoc.v:117046$4426 + attribute \src "libresoc.v:116743.3-116785.6" + process $proc$libresoc.v:116743$4410 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:117047.5-117047.29" + attribute \src "libresoc.v:116744.5-116744.29" switch \initial - attribute \src "libresoc.v:117047.9-117047.17" + attribute \src "libresoc.v:116744.9-116744.17" case 1'1 case end @@ -182276,14 +181810,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] end - attribute \src "libresoc.v:117089.3-117131.6" - process $proc$libresoc.v:117089$4427 + attribute \src "libresoc.v:116786.3-116828.6" + process $proc$libresoc.v:116786$4411 assign { } { } assign { } { } assign $0\dec31_dec_sub8_out_sel[2:0] $1\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:117090.5-117090.29" + attribute \src "libresoc.v:116787.5-116787.29" switch \initial - attribute \src "libresoc.v:117090.9-117090.17" + attribute \src "libresoc.v:116787.9-116787.17" case 1'1 case end @@ -182345,144 +181879,144 @@ module \dec31_dec_sub8 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:117137.1-119302.10" +attribute \src "libresoc.v:116834.1-118999.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" attribute \generator "nMigen" module \dec31_dec_sub9 - attribute \src "libresoc.v:118971.3-119025.6" + attribute \src "libresoc.v:118668.3-118722.6" wire width 2 $0\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:119026.3-119080.6" + attribute \src "libresoc.v:118723.3-118777.6" wire width 2 $0\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:118311.3-118365.6" + attribute \src "libresoc.v:118008.3-118062.6" wire width 8 $0\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:118531.3-118585.6" + attribute \src "libresoc.v:118228.3-118282.6" wire $0\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:117541.3-117595.6" + attribute \src "libresoc.v:117238.3-117292.6" wire width 3 $0\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:117596.3-117650.6" + attribute \src "libresoc.v:117293.3-117347.6" wire width 3 $0\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:118256.3-118310.6" + attribute \src "libresoc.v:117953.3-118007.6" wire width 2 $0\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:118476.3-118530.6" + attribute \src "libresoc.v:118173.3-118227.6" wire $0\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:118696.3-118750.6" + attribute \src "libresoc.v:118393.3-118447.6" wire width 5 $0\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:117486.3-117540.6" + attribute \src "libresoc.v:117183.3-117237.6" wire width 14 $0\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:119081.3-119135.6" + attribute \src "libresoc.v:118778.3-118832.6" wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:119136.3-119190.6" + attribute \src "libresoc.v:118833.3-118887.6" wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:119191.3-119245.6" + attribute \src "libresoc.v:118888.3-118942.6" wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:118091.3-118145.6" + attribute \src "libresoc.v:117788.3-117842.6" wire width 7 $0\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:118366.3-118420.6" + attribute \src "libresoc.v:118063.3-118117.6" wire $0\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:118421.3-118475.6" + attribute \src "libresoc.v:118118.3-118172.6" wire $0\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:118751.3-118805.6" + attribute \src "libresoc.v:118448.3-118502.6" wire $0\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:118036.3-118090.6" + attribute \src "libresoc.v:117733.3-117787.6" wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:118861.3-118915.6" + attribute \src "libresoc.v:118558.3-118612.6" wire $0\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:119246.3-119300.6" + attribute \src "libresoc.v:118943.3-118997.6" wire width 3 $0\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:118201.3-118255.6" + attribute \src "libresoc.v:117898.3-117952.6" wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:118641.3-118695.6" + attribute \src "libresoc.v:118338.3-118392.6" wire $0\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:118916.3-118970.6" + attribute \src "libresoc.v:118613.3-118667.6" wire $0\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:118806.3-118860.6" + attribute \src "libresoc.v:118503.3-118557.6" wire $0\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:118586.3-118640.6" + attribute \src "libresoc.v:118283.3-118337.6" wire $0\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:117926.3-117980.6" + attribute \src "libresoc.v:117623.3-117677.6" wire width 3 $0\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:117981.3-118035.6" + attribute \src "libresoc.v:117678.3-117732.6" wire width 3 $0\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:117651.3-117705.6" + attribute \src "libresoc.v:117348.3-117402.6" wire width 3 $0\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:117706.3-117760.6" + attribute \src "libresoc.v:117403.3-117457.6" wire width 3 $0\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:117761.3-117815.6" + attribute \src "libresoc.v:117458.3-117512.6" wire width 3 $0\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:117871.3-117925.6" + attribute \src "libresoc.v:117568.3-117622.6" wire width 3 $0\dec31_dec_sub9_sv_out2[2:0] - attribute \src "libresoc.v:117816.3-117870.6" + attribute \src "libresoc.v:117513.3-117567.6" wire width 3 $0\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:118146.3-118200.6" + attribute \src "libresoc.v:117843.3-117897.6" wire width 2 $0\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:117138.7-117138.20" + attribute \src "libresoc.v:116835.7-116835.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118971.3-119025.6" + attribute \src "libresoc.v:118668.3-118722.6" wire width 2 $1\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:119026.3-119080.6" + attribute \src "libresoc.v:118723.3-118777.6" wire width 2 $1\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:118311.3-118365.6" + attribute \src "libresoc.v:118008.3-118062.6" wire width 8 $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:118531.3-118585.6" + attribute \src "libresoc.v:118228.3-118282.6" wire $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:117541.3-117595.6" + attribute \src "libresoc.v:117238.3-117292.6" wire width 3 $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:117596.3-117650.6" + attribute \src "libresoc.v:117293.3-117347.6" wire width 3 $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:118256.3-118310.6" + attribute \src "libresoc.v:117953.3-118007.6" wire width 2 $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:118476.3-118530.6" + attribute \src "libresoc.v:118173.3-118227.6" wire $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:118696.3-118750.6" + attribute \src "libresoc.v:118393.3-118447.6" wire width 5 $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:117486.3-117540.6" + attribute \src "libresoc.v:117183.3-117237.6" wire width 14 $1\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:119081.3-119135.6" + attribute \src "libresoc.v:118778.3-118832.6" wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:119136.3-119190.6" + attribute \src "libresoc.v:118833.3-118887.6" wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:119191.3-119245.6" + attribute \src "libresoc.v:118888.3-118942.6" wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:118091.3-118145.6" + attribute \src "libresoc.v:117788.3-117842.6" wire width 7 $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:118366.3-118420.6" + attribute \src "libresoc.v:118063.3-118117.6" wire $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:118421.3-118475.6" + attribute \src "libresoc.v:118118.3-118172.6" wire $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:118751.3-118805.6" + attribute \src "libresoc.v:118448.3-118502.6" wire $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:118036.3-118090.6" + attribute \src "libresoc.v:117733.3-117787.6" wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:118861.3-118915.6" + attribute \src "libresoc.v:118558.3-118612.6" wire $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:119246.3-119300.6" + attribute \src "libresoc.v:118943.3-118997.6" wire width 3 $1\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:118201.3-118255.6" + attribute \src "libresoc.v:117898.3-117952.6" wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:118641.3-118695.6" + attribute \src "libresoc.v:118338.3-118392.6" wire $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:118916.3-118970.6" + attribute \src "libresoc.v:118613.3-118667.6" wire $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:118806.3-118860.6" + attribute \src "libresoc.v:118503.3-118557.6" wire $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:118586.3-118640.6" + attribute \src "libresoc.v:118283.3-118337.6" wire $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:117926.3-117980.6" + attribute \src "libresoc.v:117623.3-117677.6" wire width 3 $1\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:117981.3-118035.6" + attribute \src "libresoc.v:117678.3-117732.6" wire width 3 $1\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:117651.3-117705.6" + attribute \src "libresoc.v:117348.3-117402.6" wire width 3 $1\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:117706.3-117760.6" + attribute \src "libresoc.v:117403.3-117457.6" wire width 3 $1\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:117761.3-117815.6" + attribute \src "libresoc.v:117458.3-117512.6" wire width 3 $1\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:117871.3-117925.6" + attribute \src "libresoc.v:117568.3-117622.6" wire width 3 $1\dec31_dec_sub9_sv_out2[2:0] - attribute \src "libresoc.v:117816.3-117870.6" + attribute \src "libresoc.v:117513.3-117567.6" wire width 3 $1\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:118146.3-118200.6" + attribute \src "libresoc.v:117843.3-117897.6" wire width 2 $1\dec31_dec_sub9_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -182794,28 +182328,28 @@ module \dec31_dec_sub9 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub9_upd - attribute \src "libresoc.v:117138.7-117138.15" + attribute \src "libresoc.v:116835.7-116835.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:117138.7-117138.20" - process $proc$libresoc.v:117138$4462 + attribute \src "libresoc.v:116835.7-116835.20" + process $proc$libresoc.v:116835$4446 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:117486.3-117540.6" - process $proc$libresoc.v:117486$4429 + attribute \src "libresoc.v:117183.3-117237.6" + process $proc$libresoc.v:117183$4413 assign { } { } assign { } { } assign $0\dec31_dec_sub9_function_unit[13:0] $1\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:117487.5-117487.29" + attribute \src "libresoc.v:117184.5-117184.29" switch \initial - attribute \src "libresoc.v:117487.9-117487.17" + attribute \src "libresoc.v:117184.9-117184.17" case 1'1 case end @@ -182891,14 +182425,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[13:0] end - attribute \src "libresoc.v:117541.3-117595.6" - process $proc$libresoc.v:117541$4430 + attribute \src "libresoc.v:117238.3-117292.6" + process $proc$libresoc.v:117238$4414 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:117542.5-117542.29" + attribute \src "libresoc.v:117239.5-117239.29" switch \initial - attribute \src "libresoc.v:117542.9-117542.17" + attribute \src "libresoc.v:117239.9-117239.17" case 1'1 case end @@ -182974,14 +182508,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] end - attribute \src "libresoc.v:117596.3-117650.6" - process $proc$libresoc.v:117596$4431 + attribute \src "libresoc.v:117293.3-117347.6" + process $proc$libresoc.v:117293$4415 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:117597.5-117597.29" + attribute \src "libresoc.v:117294.5-117294.29" switch \initial - attribute \src "libresoc.v:117597.9-117597.17" + attribute \src "libresoc.v:117294.9-117294.17" case 1'1 case end @@ -183057,14 +182591,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] end - attribute \src "libresoc.v:117651.3-117705.6" - process $proc$libresoc.v:117651$4432 + attribute \src "libresoc.v:117348.3-117402.6" + process $proc$libresoc.v:117348$4416 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in1[2:0] $1\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:117652.5-117652.29" + attribute \src "libresoc.v:117349.5-117349.29" switch \initial - attribute \src "libresoc.v:117652.9-117652.17" + attribute \src "libresoc.v:117349.9-117349.17" case 1'1 case end @@ -183140,14 +182674,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in1 $0\dec31_dec_sub9_sv_in1[2:0] end - attribute \src "libresoc.v:117706.3-117760.6" - process $proc$libresoc.v:117706$4433 + attribute \src "libresoc.v:117403.3-117457.6" + process $proc$libresoc.v:117403$4417 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in2[2:0] $1\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:117707.5-117707.29" + attribute \src "libresoc.v:117404.5-117404.29" switch \initial - attribute \src "libresoc.v:117707.9-117707.17" + attribute \src "libresoc.v:117404.9-117404.17" case 1'1 case end @@ -183223,14 +182757,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in2 $0\dec31_dec_sub9_sv_in2[2:0] end - attribute \src "libresoc.v:117761.3-117815.6" - process $proc$libresoc.v:117761$4434 + attribute \src "libresoc.v:117458.3-117512.6" + process $proc$libresoc.v:117458$4418 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in3[2:0] $1\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:117762.5-117762.29" + attribute \src "libresoc.v:117459.5-117459.29" switch \initial - attribute \src "libresoc.v:117762.9-117762.17" + attribute \src "libresoc.v:117459.9-117459.17" case 1'1 case end @@ -183306,14 +182840,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in3 $0\dec31_dec_sub9_sv_in3[2:0] end - attribute \src "libresoc.v:117816.3-117870.6" - process $proc$libresoc.v:117816$4435 + attribute \src "libresoc.v:117513.3-117567.6" + process $proc$libresoc.v:117513$4419 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_out[2:0] $1\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:117817.5-117817.29" + attribute \src "libresoc.v:117514.5-117514.29" switch \initial - attribute \src "libresoc.v:117817.9-117817.17" + attribute \src "libresoc.v:117514.9-117514.17" case 1'1 case end @@ -183389,14 +182923,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_out $0\dec31_dec_sub9_sv_out[2:0] end - attribute \src "libresoc.v:117871.3-117925.6" - process $proc$libresoc.v:117871$4436 + attribute \src "libresoc.v:117568.3-117622.6" + process $proc$libresoc.v:117568$4420 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_out2[2:0] $1\dec31_dec_sub9_sv_out2[2:0] - attribute \src "libresoc.v:117872.5-117872.29" + attribute \src "libresoc.v:117569.5-117569.29" switch \initial - attribute \src "libresoc.v:117872.9-117872.17" + attribute \src "libresoc.v:117569.9-117569.17" case 1'1 case end @@ -183472,14 +183006,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_out2 $0\dec31_dec_sub9_sv_out2[2:0] end - attribute \src "libresoc.v:117926.3-117980.6" - process $proc$libresoc.v:117926$4437 + attribute \src "libresoc.v:117623.3-117677.6" + process $proc$libresoc.v:117623$4421 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_in[2:0] $1\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:117927.5-117927.29" + attribute \src "libresoc.v:117624.5-117624.29" switch \initial - attribute \src "libresoc.v:117927.9-117927.17" + attribute \src "libresoc.v:117624.9-117624.17" case 1'1 case end @@ -183555,14 +183089,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_cr_in $0\dec31_dec_sub9_sv_cr_in[2:0] end - attribute \src "libresoc.v:117981.3-118035.6" - process $proc$libresoc.v:117981$4438 + attribute \src "libresoc.v:117678.3-117732.6" + process $proc$libresoc.v:117678$4422 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_out[2:0] $1\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:117982.5-117982.29" + attribute \src "libresoc.v:117679.5-117679.29" switch \initial - attribute \src "libresoc.v:117982.9-117982.17" + attribute \src "libresoc.v:117679.9-117679.17" case 1'1 case end @@ -183638,14 +183172,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_cr_out $0\dec31_dec_sub9_sv_cr_out[2:0] end - attribute \src "libresoc.v:118036.3-118090.6" - process $proc$libresoc.v:118036$4439 + attribute \src "libresoc.v:117733.3-117787.6" + process $proc$libresoc.v:117733$4423 assign { } { } assign { } { } assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:118037.5-118037.29" + attribute \src "libresoc.v:117734.5-117734.29" switch \initial - attribute \src "libresoc.v:118037.9-118037.17" + attribute \src "libresoc.v:117734.9-117734.17" case 1'1 case end @@ -183721,14 +183255,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] end - attribute \src "libresoc.v:118091.3-118145.6" - process $proc$libresoc.v:118091$4440 + attribute \src "libresoc.v:117788.3-117842.6" + process $proc$libresoc.v:117788$4424 assign { } { } assign { } { } assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:118092.5-118092.29" + attribute \src "libresoc.v:117789.5-117789.29" switch \initial - attribute \src "libresoc.v:118092.9-118092.17" + attribute \src "libresoc.v:117789.9-117789.17" case 1'1 case end @@ -183804,14 +183338,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:118146.3-118200.6" - process $proc$libresoc.v:118146$4441 + attribute \src "libresoc.v:117843.3-117897.6" + process $proc$libresoc.v:117843$4425 assign { } { } assign { } { } assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:118147.5-118147.29" + attribute \src "libresoc.v:117844.5-117844.29" switch \initial - attribute \src "libresoc.v:118147.9-118147.17" + attribute \src "libresoc.v:117844.9-117844.17" case 1'1 case end @@ -183887,14 +183421,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] end - attribute \src "libresoc.v:118201.3-118255.6" - process $proc$libresoc.v:118201$4442 + attribute \src "libresoc.v:117898.3-117952.6" + process $proc$libresoc.v:117898$4426 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:118202.5-118202.29" + attribute \src "libresoc.v:117899.5-117899.29" switch \initial - attribute \src "libresoc.v:118202.9-118202.17" + attribute \src "libresoc.v:117899.9-117899.17" case 1'1 case end @@ -183970,14 +183504,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:118256.3-118310.6" - process $proc$libresoc.v:118256$4443 + attribute \src "libresoc.v:117953.3-118007.6" + process $proc$libresoc.v:117953$4427 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:118257.5-118257.29" + attribute \src "libresoc.v:117954.5-117954.29" switch \initial - attribute \src "libresoc.v:118257.9-118257.17" + attribute \src "libresoc.v:117954.9-117954.17" case 1'1 case end @@ -184053,14 +183587,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] end - attribute \src "libresoc.v:118311.3-118365.6" - process $proc$libresoc.v:118311$4444 + attribute \src "libresoc.v:118008.3-118062.6" + process $proc$libresoc.v:118008$4428 assign { } { } assign { } { } assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:118312.5-118312.29" + attribute \src "libresoc.v:118009.5-118009.29" switch \initial - attribute \src "libresoc.v:118312.9-118312.17" + attribute \src "libresoc.v:118009.9-118009.17" case 1'1 case end @@ -184136,14 +183670,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] end - attribute \src "libresoc.v:118366.3-118420.6" - process $proc$libresoc.v:118366$4445 + attribute \src "libresoc.v:118063.3-118117.6" + process $proc$libresoc.v:118063$4429 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:118367.5-118367.29" + attribute \src "libresoc.v:118064.5-118064.29" switch \initial - attribute \src "libresoc.v:118367.9-118367.17" + attribute \src "libresoc.v:118064.9-118064.17" case 1'1 case end @@ -184219,14 +183753,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] end - attribute \src "libresoc.v:118421.3-118475.6" - process $proc$libresoc.v:118421$4446 + attribute \src "libresoc.v:118118.3-118172.6" + process $proc$libresoc.v:118118$4430 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:118422.5-118422.29" + attribute \src "libresoc.v:118119.5-118119.29" switch \initial - attribute \src "libresoc.v:118422.9-118422.17" + attribute \src "libresoc.v:118119.9-118119.17" case 1'1 case end @@ -184302,14 +183836,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] end - attribute \src "libresoc.v:118476.3-118530.6" - process $proc$libresoc.v:118476$4447 + attribute \src "libresoc.v:118173.3-118227.6" + process $proc$libresoc.v:118173$4431 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:118477.5-118477.29" + attribute \src "libresoc.v:118174.5-118174.29" switch \initial - attribute \src "libresoc.v:118477.9-118477.17" + attribute \src "libresoc.v:118174.9-118174.17" case 1'1 case end @@ -184385,14 +183919,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] end - attribute \src "libresoc.v:118531.3-118585.6" - process $proc$libresoc.v:118531$4448 + attribute \src "libresoc.v:118228.3-118282.6" + process $proc$libresoc.v:118228$4432 assign { } { } assign { } { } assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:118532.5-118532.29" + attribute \src "libresoc.v:118229.5-118229.29" switch \initial - attribute \src "libresoc.v:118532.9-118532.17" + attribute \src "libresoc.v:118229.9-118229.17" case 1'1 case end @@ -184468,14 +184002,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] end - attribute \src "libresoc.v:118586.3-118640.6" - process $proc$libresoc.v:118586$4449 + attribute \src "libresoc.v:118283.3-118337.6" + process $proc$libresoc.v:118283$4433 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:118587.5-118587.29" + attribute \src "libresoc.v:118284.5-118284.29" switch \initial - attribute \src "libresoc.v:118587.9-118587.17" + attribute \src "libresoc.v:118284.9-118284.17" case 1'1 case end @@ -184551,14 +184085,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] end - attribute \src "libresoc.v:118641.3-118695.6" - process $proc$libresoc.v:118641$4450 + attribute \src "libresoc.v:118338.3-118392.6" + process $proc$libresoc.v:118338$4434 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:118642.5-118642.29" + attribute \src "libresoc.v:118339.5-118339.29" switch \initial - attribute \src "libresoc.v:118642.9-118642.17" + attribute \src "libresoc.v:118339.9-118339.17" case 1'1 case end @@ -184634,14 +184168,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] end - attribute \src "libresoc.v:118696.3-118750.6" - process $proc$libresoc.v:118696$4451 + attribute \src "libresoc.v:118393.3-118447.6" + process $proc$libresoc.v:118393$4435 assign { } { } assign { } { } assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:118697.5-118697.29" + attribute \src "libresoc.v:118394.5-118394.29" switch \initial - attribute \src "libresoc.v:118697.9-118697.17" + attribute \src "libresoc.v:118394.9-118394.17" case 1'1 case end @@ -184717,14 +184251,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] end - attribute \src "libresoc.v:118751.3-118805.6" - process $proc$libresoc.v:118751$4452 + attribute \src "libresoc.v:118448.3-118502.6" + process $proc$libresoc.v:118448$4436 assign { } { } assign { } { } assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:118752.5-118752.29" + attribute \src "libresoc.v:118449.5-118449.29" switch \initial - attribute \src "libresoc.v:118752.9-118752.17" + attribute \src "libresoc.v:118449.9-118449.17" case 1'1 case end @@ -184800,14 +184334,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] end - attribute \src "libresoc.v:118806.3-118860.6" - process $proc$libresoc.v:118806$4453 + attribute \src "libresoc.v:118503.3-118557.6" + process $proc$libresoc.v:118503$4437 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:118807.5-118807.29" + attribute \src "libresoc.v:118504.5-118504.29" switch \initial - attribute \src "libresoc.v:118807.9-118807.17" + attribute \src "libresoc.v:118504.9-118504.17" case 1'1 case end @@ -184883,14 +184417,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] end - attribute \src "libresoc.v:118861.3-118915.6" - process $proc$libresoc.v:118861$4454 + attribute \src "libresoc.v:118558.3-118612.6" + process $proc$libresoc.v:118558$4438 assign { } { } assign { } { } assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:118862.5-118862.29" + attribute \src "libresoc.v:118559.5-118559.29" switch \initial - attribute \src "libresoc.v:118862.9-118862.17" + attribute \src "libresoc.v:118559.9-118559.17" case 1'1 case end @@ -184966,14 +184500,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] end - attribute \src "libresoc.v:118916.3-118970.6" - process $proc$libresoc.v:118916$4455 + attribute \src "libresoc.v:118613.3-118667.6" + process $proc$libresoc.v:118613$4439 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:118917.5-118917.29" + attribute \src "libresoc.v:118614.5-118614.29" switch \initial - attribute \src "libresoc.v:118917.9-118917.17" + attribute \src "libresoc.v:118614.9-118614.17" case 1'1 case end @@ -185049,14 +184583,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] end - attribute \src "libresoc.v:118971.3-119025.6" - process $proc$libresoc.v:118971$4456 + attribute \src "libresoc.v:118668.3-118722.6" + process $proc$libresoc.v:118668$4440 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Etype[1:0] $1\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:118972.5-118972.29" + attribute \src "libresoc.v:118669.5-118669.29" switch \initial - attribute \src "libresoc.v:118972.9-118972.17" + attribute \src "libresoc.v:118669.9-118669.17" case 1'1 case end @@ -185132,14 +184666,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_SV_Etype $0\dec31_dec_sub9_SV_Etype[1:0] end - attribute \src "libresoc.v:119026.3-119080.6" - process $proc$libresoc.v:119026$4457 + attribute \src "libresoc.v:118723.3-118777.6" + process $proc$libresoc.v:118723$4441 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Ptype[1:0] $1\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:119027.5-119027.29" + attribute \src "libresoc.v:118724.5-118724.29" switch \initial - attribute \src "libresoc.v:119027.9-119027.17" + attribute \src "libresoc.v:118724.9-118724.17" case 1'1 case end @@ -185215,14 +184749,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_SV_Ptype $0\dec31_dec_sub9_SV_Ptype[1:0] end - attribute \src "libresoc.v:119081.3-119135.6" - process $proc$libresoc.v:119081$4458 + attribute \src "libresoc.v:118778.3-118832.6" + process $proc$libresoc.v:118778$4442 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:119082.5-119082.29" + attribute \src "libresoc.v:118779.5-118779.29" switch \initial - attribute \src "libresoc.v:119082.9-119082.17" + attribute \src "libresoc.v:118779.9-118779.17" case 1'1 case end @@ -185298,14 +184832,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] end - attribute \src "libresoc.v:119136.3-119190.6" - process $proc$libresoc.v:119136$4459 + attribute \src "libresoc.v:118833.3-118887.6" + process $proc$libresoc.v:118833$4443 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:119137.5-119137.29" + attribute \src "libresoc.v:118834.5-118834.29" switch \initial - attribute \src "libresoc.v:119137.9-119137.17" + attribute \src "libresoc.v:118834.9-118834.17" case 1'1 case end @@ -185381,14 +184915,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] end - attribute \src "libresoc.v:119191.3-119245.6" - process $proc$libresoc.v:119191$4460 + attribute \src "libresoc.v:118888.3-118942.6" + process $proc$libresoc.v:118888$4444 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:119192.5-119192.29" + attribute \src "libresoc.v:118889.5-118889.29" switch \initial - attribute \src "libresoc.v:119192.9-119192.17" + attribute \src "libresoc.v:118889.9-118889.17" case 1'1 case end @@ -185464,14 +184998,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] end - attribute \src "libresoc.v:119246.3-119300.6" - process $proc$libresoc.v:119246$4461 + attribute \src "libresoc.v:118943.3-118997.6" + process $proc$libresoc.v:118943$4445 assign { } { } assign { } { } assign $0\dec31_dec_sub9_out_sel[2:0] $1\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:119247.5-119247.29" + attribute \src "libresoc.v:118944.5-118944.29" switch \initial - attribute \src "libresoc.v:119247.9-119247.17" + attribute \src "libresoc.v:118944.9-118944.17" case 1'1 case end @@ -185549,144 +185083,144 @@ module \dec31_dec_sub9 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:119306.1-120184.10" +attribute \src "libresoc.v:119003.1-119881.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" attribute \generator "nMigen" module \dec58 - attribute \src "libresoc.v:120087.3-120102.6" + attribute \src "libresoc.v:119784.3-119799.6" wire width 2 $0\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:120103.3-120118.6" + attribute \src "libresoc.v:119800.3-119815.6" wire width 2 $0\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:119895.3-119910.6" + attribute \src "libresoc.v:119592.3-119607.6" wire width 8 $0\dec58_asmcode[7:0] - attribute \src "libresoc.v:119959.3-119974.6" + attribute \src "libresoc.v:119656.3-119671.6" wire $0\dec58_br[0:0] - attribute \src "libresoc.v:119671.3-119686.6" + attribute \src "libresoc.v:119368.3-119383.6" wire width 3 $0\dec58_cr_in[2:0] - attribute \src "libresoc.v:119687.3-119702.6" + attribute \src "libresoc.v:119384.3-119399.6" wire width 3 $0\dec58_cr_out[2:0] - attribute \src "libresoc.v:119879.3-119894.6" + attribute \src "libresoc.v:119576.3-119591.6" wire width 2 $0\dec58_cry_in[1:0] - attribute \src "libresoc.v:119943.3-119958.6" + attribute \src "libresoc.v:119640.3-119655.6" wire $0\dec58_cry_out[0:0] - attribute \src "libresoc.v:120007.3-120022.6" + attribute \src "libresoc.v:119704.3-119719.6" wire width 5 $0\dec58_form[4:0] - attribute \src "libresoc.v:119655.3-119670.6" + attribute \src "libresoc.v:119352.3-119367.6" wire width 14 $0\dec58_function_unit[13:0] - attribute \src "libresoc.v:120119.3-120134.6" + attribute \src "libresoc.v:119816.3-119831.6" wire width 3 $0\dec58_in1_sel[2:0] - attribute \src "libresoc.v:120135.3-120150.6" + attribute \src "libresoc.v:119832.3-119847.6" wire width 4 $0\dec58_in2_sel[3:0] - attribute \src "libresoc.v:120151.3-120166.6" + attribute \src "libresoc.v:119848.3-119863.6" wire width 2 $0\dec58_in3_sel[1:0] - attribute \src "libresoc.v:119831.3-119846.6" + attribute \src "libresoc.v:119528.3-119543.6" wire width 7 $0\dec58_internal_op[6:0] - attribute \src "libresoc.v:119911.3-119926.6" + attribute \src "libresoc.v:119608.3-119623.6" wire $0\dec58_inv_a[0:0] - attribute \src "libresoc.v:119927.3-119942.6" + attribute \src "libresoc.v:119624.3-119639.6" wire $0\dec58_inv_out[0:0] - attribute \src "libresoc.v:120023.3-120038.6" + attribute \src "libresoc.v:119720.3-119735.6" wire $0\dec58_is_32b[0:0] - attribute \src "libresoc.v:119815.3-119830.6" + attribute \src "libresoc.v:119512.3-119527.6" wire width 4 $0\dec58_ldst_len[3:0] - attribute \src "libresoc.v:120055.3-120070.6" + attribute \src "libresoc.v:119752.3-119767.6" wire $0\dec58_lk[0:0] - attribute \src "libresoc.v:120167.3-120182.6" + attribute \src "libresoc.v:119864.3-119879.6" wire width 3 $0\dec58_out_sel[2:0] - attribute \src "libresoc.v:119863.3-119878.6" + attribute \src "libresoc.v:119560.3-119575.6" wire width 2 $0\dec58_rc_sel[1:0] - attribute \src "libresoc.v:119991.3-120006.6" + attribute \src "libresoc.v:119688.3-119703.6" wire $0\dec58_rsrv[0:0] - attribute \src "libresoc.v:120071.3-120086.6" + attribute \src "libresoc.v:119768.3-119783.6" wire $0\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:120039.3-120054.6" + attribute \src "libresoc.v:119736.3-119751.6" wire $0\dec58_sgn[0:0] - attribute \src "libresoc.v:119975.3-119990.6" + attribute \src "libresoc.v:119672.3-119687.6" wire $0\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:119783.3-119798.6" + attribute \src "libresoc.v:119480.3-119495.6" wire width 3 $0\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:119799.3-119814.6" + attribute \src "libresoc.v:119496.3-119511.6" wire width 3 $0\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:119703.3-119718.6" + attribute \src "libresoc.v:119400.3-119415.6" wire width 3 $0\dec58_sv_in1[2:0] - attribute \src "libresoc.v:119719.3-119734.6" + attribute \src "libresoc.v:119416.3-119431.6" wire width 3 $0\dec58_sv_in2[2:0] - attribute \src "libresoc.v:119735.3-119750.6" + attribute \src "libresoc.v:119432.3-119447.6" wire width 3 $0\dec58_sv_in3[2:0] - attribute \src "libresoc.v:119767.3-119782.6" + attribute \src "libresoc.v:119464.3-119479.6" wire width 3 $0\dec58_sv_out2[2:0] - attribute \src "libresoc.v:119751.3-119766.6" + attribute \src "libresoc.v:119448.3-119463.6" wire width 3 $0\dec58_sv_out[2:0] - attribute \src "libresoc.v:119847.3-119862.6" + attribute \src "libresoc.v:119544.3-119559.6" wire width 2 $0\dec58_upd[1:0] - attribute \src "libresoc.v:119307.7-119307.20" + attribute \src "libresoc.v:119004.7-119004.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120087.3-120102.6" + attribute \src "libresoc.v:119784.3-119799.6" wire width 2 $1\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:120103.3-120118.6" + attribute \src "libresoc.v:119800.3-119815.6" wire width 2 $1\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:119895.3-119910.6" + attribute \src "libresoc.v:119592.3-119607.6" wire width 8 $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:119959.3-119974.6" + attribute \src "libresoc.v:119656.3-119671.6" wire $1\dec58_br[0:0] - attribute \src "libresoc.v:119671.3-119686.6" + attribute \src "libresoc.v:119368.3-119383.6" wire width 3 $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:119687.3-119702.6" + attribute \src "libresoc.v:119384.3-119399.6" wire width 3 $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:119879.3-119894.6" + attribute \src "libresoc.v:119576.3-119591.6" wire width 2 $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:119943.3-119958.6" + attribute \src "libresoc.v:119640.3-119655.6" wire $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:120007.3-120022.6" + attribute \src "libresoc.v:119704.3-119719.6" wire width 5 $1\dec58_form[4:0] - attribute \src "libresoc.v:119655.3-119670.6" + attribute \src "libresoc.v:119352.3-119367.6" wire width 14 $1\dec58_function_unit[13:0] - attribute \src "libresoc.v:120119.3-120134.6" + attribute \src "libresoc.v:119816.3-119831.6" wire width 3 $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:120135.3-120150.6" + attribute \src "libresoc.v:119832.3-119847.6" wire width 4 $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:120151.3-120166.6" + attribute \src "libresoc.v:119848.3-119863.6" wire width 2 $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:119831.3-119846.6" + attribute \src "libresoc.v:119528.3-119543.6" wire width 7 $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:119911.3-119926.6" + attribute \src "libresoc.v:119608.3-119623.6" wire $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:119927.3-119942.6" + attribute \src "libresoc.v:119624.3-119639.6" wire $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:120023.3-120038.6" + attribute \src "libresoc.v:119720.3-119735.6" wire $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:119815.3-119830.6" + attribute \src "libresoc.v:119512.3-119527.6" wire width 4 $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:120055.3-120070.6" + attribute \src "libresoc.v:119752.3-119767.6" wire $1\dec58_lk[0:0] - attribute \src "libresoc.v:120167.3-120182.6" + attribute \src "libresoc.v:119864.3-119879.6" wire width 3 $1\dec58_out_sel[2:0] - attribute \src "libresoc.v:119863.3-119878.6" + attribute \src "libresoc.v:119560.3-119575.6" wire width 2 $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:119991.3-120006.6" + attribute \src "libresoc.v:119688.3-119703.6" wire $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:120071.3-120086.6" + attribute \src "libresoc.v:119768.3-119783.6" wire $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:120039.3-120054.6" + attribute \src "libresoc.v:119736.3-119751.6" wire $1\dec58_sgn[0:0] - attribute \src "libresoc.v:119975.3-119990.6" + attribute \src "libresoc.v:119672.3-119687.6" wire $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:119783.3-119798.6" + attribute \src "libresoc.v:119480.3-119495.6" wire width 3 $1\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:119799.3-119814.6" + attribute \src "libresoc.v:119496.3-119511.6" wire width 3 $1\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:119703.3-119718.6" + attribute \src "libresoc.v:119400.3-119415.6" wire width 3 $1\dec58_sv_in1[2:0] - attribute \src "libresoc.v:119719.3-119734.6" + attribute \src "libresoc.v:119416.3-119431.6" wire width 3 $1\dec58_sv_in2[2:0] - attribute \src "libresoc.v:119735.3-119750.6" + attribute \src "libresoc.v:119432.3-119447.6" wire width 3 $1\dec58_sv_in3[2:0] - attribute \src "libresoc.v:119767.3-119782.6" + attribute \src "libresoc.v:119464.3-119479.6" wire width 3 $1\dec58_sv_out2[2:0] - attribute \src "libresoc.v:119751.3-119766.6" + attribute \src "libresoc.v:119448.3-119463.6" wire width 3 $1\dec58_sv_out[2:0] - attribute \src "libresoc.v:119847.3-119862.6" + attribute \src "libresoc.v:119544.3-119559.6" wire width 2 $1\dec58_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -185998,28 +185532,28 @@ module \dec58 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec58_upd - attribute \src "libresoc.v:119307.7-119307.15" + attribute \src "libresoc.v:119004.7-119004.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch - attribute \src "libresoc.v:119307.7-119307.20" - process $proc$libresoc.v:119307$4496 + attribute \src "libresoc.v:119004.7-119004.20" + process $proc$libresoc.v:119004$4480 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119655.3-119670.6" - process $proc$libresoc.v:119655$4463 + attribute \src "libresoc.v:119352.3-119367.6" + process $proc$libresoc.v:119352$4447 assign { } { } assign { } { } assign $0\dec58_function_unit[13:0] $1\dec58_function_unit[13:0] - attribute \src "libresoc.v:119656.5-119656.29" + attribute \src "libresoc.v:119353.5-119353.29" switch \initial - attribute \src "libresoc.v:119656.9-119656.17" + attribute \src "libresoc.v:119353.9-119353.17" case 1'1 case end @@ -186043,14 +185577,14 @@ module \dec58 sync always update \dec58_function_unit $0\dec58_function_unit[13:0] end - attribute \src "libresoc.v:119671.3-119686.6" - process $proc$libresoc.v:119671$4464 + attribute \src "libresoc.v:119368.3-119383.6" + process $proc$libresoc.v:119368$4448 assign { } { } assign { } { } assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:119672.5-119672.29" + attribute \src "libresoc.v:119369.5-119369.29" switch \initial - attribute \src "libresoc.v:119672.9-119672.17" + attribute \src "libresoc.v:119369.9-119369.17" case 1'1 case end @@ -186074,14 +185608,14 @@ module \dec58 sync always update \dec58_cr_in $0\dec58_cr_in[2:0] end - attribute \src "libresoc.v:119687.3-119702.6" - process $proc$libresoc.v:119687$4465 + attribute \src "libresoc.v:119384.3-119399.6" + process $proc$libresoc.v:119384$4449 assign { } { } assign { } { } assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:119688.5-119688.29" + attribute \src "libresoc.v:119385.5-119385.29" switch \initial - attribute \src "libresoc.v:119688.9-119688.17" + attribute \src "libresoc.v:119385.9-119385.17" case 1'1 case end @@ -186105,14 +185639,14 @@ module \dec58 sync always update \dec58_cr_out $0\dec58_cr_out[2:0] end - attribute \src "libresoc.v:119703.3-119718.6" - process $proc$libresoc.v:119703$4466 + attribute \src "libresoc.v:119400.3-119415.6" + process $proc$libresoc.v:119400$4450 assign { } { } assign { } { } assign $0\dec58_sv_in1[2:0] $1\dec58_sv_in1[2:0] - attribute \src "libresoc.v:119704.5-119704.29" + attribute \src "libresoc.v:119401.5-119401.29" switch \initial - attribute \src "libresoc.v:119704.9-119704.17" + attribute \src "libresoc.v:119401.9-119401.17" case 1'1 case end @@ -186136,14 +185670,14 @@ module \dec58 sync always update \dec58_sv_in1 $0\dec58_sv_in1[2:0] end - attribute \src "libresoc.v:119719.3-119734.6" - process $proc$libresoc.v:119719$4467 + attribute \src "libresoc.v:119416.3-119431.6" + process $proc$libresoc.v:119416$4451 assign { } { } assign { } { } assign $0\dec58_sv_in2[2:0] $1\dec58_sv_in2[2:0] - attribute \src "libresoc.v:119720.5-119720.29" + attribute \src "libresoc.v:119417.5-119417.29" switch \initial - attribute \src "libresoc.v:119720.9-119720.17" + attribute \src "libresoc.v:119417.9-119417.17" case 1'1 case end @@ -186167,14 +185701,14 @@ module \dec58 sync always update \dec58_sv_in2 $0\dec58_sv_in2[2:0] end - attribute \src "libresoc.v:119735.3-119750.6" - process $proc$libresoc.v:119735$4468 + attribute \src "libresoc.v:119432.3-119447.6" + process $proc$libresoc.v:119432$4452 assign { } { } assign { } { } assign $0\dec58_sv_in3[2:0] $1\dec58_sv_in3[2:0] - attribute \src "libresoc.v:119736.5-119736.29" + attribute \src "libresoc.v:119433.5-119433.29" switch \initial - attribute \src "libresoc.v:119736.9-119736.17" + attribute \src "libresoc.v:119433.9-119433.17" case 1'1 case end @@ -186198,14 +185732,14 @@ module \dec58 sync always update \dec58_sv_in3 $0\dec58_sv_in3[2:0] end - attribute \src "libresoc.v:119751.3-119766.6" - process $proc$libresoc.v:119751$4469 + attribute \src "libresoc.v:119448.3-119463.6" + process $proc$libresoc.v:119448$4453 assign { } { } assign { } { } assign $0\dec58_sv_out[2:0] $1\dec58_sv_out[2:0] - attribute \src "libresoc.v:119752.5-119752.29" + attribute \src "libresoc.v:119449.5-119449.29" switch \initial - attribute \src "libresoc.v:119752.9-119752.17" + attribute \src "libresoc.v:119449.9-119449.17" case 1'1 case end @@ -186229,14 +185763,14 @@ module \dec58 sync always update \dec58_sv_out $0\dec58_sv_out[2:0] end - attribute \src "libresoc.v:119767.3-119782.6" - process $proc$libresoc.v:119767$4470 + attribute \src "libresoc.v:119464.3-119479.6" + process $proc$libresoc.v:119464$4454 assign { } { } assign { } { } assign $0\dec58_sv_out2[2:0] $1\dec58_sv_out2[2:0] - attribute \src "libresoc.v:119768.5-119768.29" + attribute \src "libresoc.v:119465.5-119465.29" switch \initial - attribute \src "libresoc.v:119768.9-119768.17" + attribute \src "libresoc.v:119465.9-119465.17" case 1'1 case end @@ -186260,14 +185794,14 @@ module \dec58 sync always update \dec58_sv_out2 $0\dec58_sv_out2[2:0] end - attribute \src "libresoc.v:119783.3-119798.6" - process $proc$libresoc.v:119783$4471 + attribute \src "libresoc.v:119480.3-119495.6" + process $proc$libresoc.v:119480$4455 assign { } { } assign { } { } assign $0\dec58_sv_cr_in[2:0] $1\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:119784.5-119784.29" + attribute \src "libresoc.v:119481.5-119481.29" switch \initial - attribute \src "libresoc.v:119784.9-119784.17" + attribute \src "libresoc.v:119481.9-119481.17" case 1'1 case end @@ -186291,14 +185825,14 @@ module \dec58 sync always update \dec58_sv_cr_in $0\dec58_sv_cr_in[2:0] end - attribute \src "libresoc.v:119799.3-119814.6" - process $proc$libresoc.v:119799$4472 + attribute \src "libresoc.v:119496.3-119511.6" + process $proc$libresoc.v:119496$4456 assign { } { } assign { } { } assign $0\dec58_sv_cr_out[2:0] $1\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:119800.5-119800.29" + attribute \src "libresoc.v:119497.5-119497.29" switch \initial - attribute \src "libresoc.v:119800.9-119800.17" + attribute \src "libresoc.v:119497.9-119497.17" case 1'1 case end @@ -186322,14 +185856,14 @@ module \dec58 sync always update \dec58_sv_cr_out $0\dec58_sv_cr_out[2:0] end - attribute \src "libresoc.v:119815.3-119830.6" - process $proc$libresoc.v:119815$4473 + attribute \src "libresoc.v:119512.3-119527.6" + process $proc$libresoc.v:119512$4457 assign { } { } assign { } { } assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:119816.5-119816.29" + attribute \src "libresoc.v:119513.5-119513.29" switch \initial - attribute \src "libresoc.v:119816.9-119816.17" + attribute \src "libresoc.v:119513.9-119513.17" case 1'1 case end @@ -186353,14 +185887,14 @@ module \dec58 sync always update \dec58_ldst_len $0\dec58_ldst_len[3:0] end - attribute \src "libresoc.v:119831.3-119846.6" - process $proc$libresoc.v:119831$4474 + attribute \src "libresoc.v:119528.3-119543.6" + process $proc$libresoc.v:119528$4458 assign { } { } assign { } { } assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:119832.5-119832.29" + attribute \src "libresoc.v:119529.5-119529.29" switch \initial - attribute \src "libresoc.v:119832.9-119832.17" + attribute \src "libresoc.v:119529.9-119529.17" case 1'1 case end @@ -186384,14 +185918,14 @@ module \dec58 sync always update \dec58_internal_op $0\dec58_internal_op[6:0] end - attribute \src "libresoc.v:119847.3-119862.6" - process $proc$libresoc.v:119847$4475 + attribute \src "libresoc.v:119544.3-119559.6" + process $proc$libresoc.v:119544$4459 assign { } { } assign { } { } assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] - attribute \src "libresoc.v:119848.5-119848.29" + attribute \src "libresoc.v:119545.5-119545.29" switch \initial - attribute \src "libresoc.v:119848.9-119848.17" + attribute \src "libresoc.v:119545.9-119545.17" case 1'1 case end @@ -186415,14 +185949,14 @@ module \dec58 sync always update \dec58_upd $0\dec58_upd[1:0] end - attribute \src "libresoc.v:119863.3-119878.6" - process $proc$libresoc.v:119863$4476 + attribute \src "libresoc.v:119560.3-119575.6" + process $proc$libresoc.v:119560$4460 assign { } { } assign { } { } assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:119864.5-119864.29" + attribute \src "libresoc.v:119561.5-119561.29" switch \initial - attribute \src "libresoc.v:119864.9-119864.17" + attribute \src "libresoc.v:119561.9-119561.17" case 1'1 case end @@ -186446,14 +185980,14 @@ module \dec58 sync always update \dec58_rc_sel $0\dec58_rc_sel[1:0] end - attribute \src "libresoc.v:119879.3-119894.6" - process $proc$libresoc.v:119879$4477 + attribute \src "libresoc.v:119576.3-119591.6" + process $proc$libresoc.v:119576$4461 assign { } { } assign { } { } assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:119880.5-119880.29" + attribute \src "libresoc.v:119577.5-119577.29" switch \initial - attribute \src "libresoc.v:119880.9-119880.17" + attribute \src "libresoc.v:119577.9-119577.17" case 1'1 case end @@ -186477,14 +186011,14 @@ module \dec58 sync always update \dec58_cry_in $0\dec58_cry_in[1:0] end - attribute \src "libresoc.v:119895.3-119910.6" - process $proc$libresoc.v:119895$4478 + attribute \src "libresoc.v:119592.3-119607.6" + process $proc$libresoc.v:119592$4462 assign { } { } assign { } { } assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:119896.5-119896.29" + attribute \src "libresoc.v:119593.5-119593.29" switch \initial - attribute \src "libresoc.v:119896.9-119896.17" + attribute \src "libresoc.v:119593.9-119593.17" case 1'1 case end @@ -186508,14 +186042,14 @@ module \dec58 sync always update \dec58_asmcode $0\dec58_asmcode[7:0] end - attribute \src "libresoc.v:119911.3-119926.6" - process $proc$libresoc.v:119911$4479 + attribute \src "libresoc.v:119608.3-119623.6" + process $proc$libresoc.v:119608$4463 assign { } { } assign { } { } assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:119912.5-119912.29" + attribute \src "libresoc.v:119609.5-119609.29" switch \initial - attribute \src "libresoc.v:119912.9-119912.17" + attribute \src "libresoc.v:119609.9-119609.17" case 1'1 case end @@ -186539,14 +186073,14 @@ module \dec58 sync always update \dec58_inv_a $0\dec58_inv_a[0:0] end - attribute \src "libresoc.v:119927.3-119942.6" - process $proc$libresoc.v:119927$4480 + attribute \src "libresoc.v:119624.3-119639.6" + process $proc$libresoc.v:119624$4464 assign { } { } assign { } { } assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:119928.5-119928.29" + attribute \src "libresoc.v:119625.5-119625.29" switch \initial - attribute \src "libresoc.v:119928.9-119928.17" + attribute \src "libresoc.v:119625.9-119625.17" case 1'1 case end @@ -186570,14 +186104,14 @@ module \dec58 sync always update \dec58_inv_out $0\dec58_inv_out[0:0] end - attribute \src "libresoc.v:119943.3-119958.6" - process $proc$libresoc.v:119943$4481 + attribute \src "libresoc.v:119640.3-119655.6" + process $proc$libresoc.v:119640$4465 assign { } { } assign { } { } assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:119944.5-119944.29" + attribute \src "libresoc.v:119641.5-119641.29" switch \initial - attribute \src "libresoc.v:119944.9-119944.17" + attribute \src "libresoc.v:119641.9-119641.17" case 1'1 case end @@ -186601,14 +186135,14 @@ module \dec58 sync always update \dec58_cry_out $0\dec58_cry_out[0:0] end - attribute \src "libresoc.v:119959.3-119974.6" - process $proc$libresoc.v:119959$4482 + attribute \src "libresoc.v:119656.3-119671.6" + process $proc$libresoc.v:119656$4466 assign { } { } assign { } { } assign $0\dec58_br[0:0] $1\dec58_br[0:0] - attribute \src "libresoc.v:119960.5-119960.29" + attribute \src "libresoc.v:119657.5-119657.29" switch \initial - attribute \src "libresoc.v:119960.9-119960.17" + attribute \src "libresoc.v:119657.9-119657.17" case 1'1 case end @@ -186632,14 +186166,14 @@ module \dec58 sync always update \dec58_br $0\dec58_br[0:0] end - attribute \src "libresoc.v:119975.3-119990.6" - process $proc$libresoc.v:119975$4483 + attribute \src "libresoc.v:119672.3-119687.6" + process $proc$libresoc.v:119672$4467 assign { } { } assign { } { } assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:119976.5-119976.29" + attribute \src "libresoc.v:119673.5-119673.29" switch \initial - attribute \src "libresoc.v:119976.9-119976.17" + attribute \src "libresoc.v:119673.9-119673.17" case 1'1 case end @@ -186663,14 +186197,14 @@ module \dec58 sync always update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] end - attribute \src "libresoc.v:119991.3-120006.6" - process $proc$libresoc.v:119991$4484 + attribute \src "libresoc.v:119688.3-119703.6" + process $proc$libresoc.v:119688$4468 assign { } { } assign { } { } assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:119992.5-119992.29" + attribute \src "libresoc.v:119689.5-119689.29" switch \initial - attribute \src "libresoc.v:119992.9-119992.17" + attribute \src "libresoc.v:119689.9-119689.17" case 1'1 case end @@ -186694,14 +186228,14 @@ module \dec58 sync always update \dec58_rsrv $0\dec58_rsrv[0:0] end - attribute \src "libresoc.v:120007.3-120022.6" - process $proc$libresoc.v:120007$4485 + attribute \src "libresoc.v:119704.3-119719.6" + process $proc$libresoc.v:119704$4469 assign { } { } assign { } { } assign $0\dec58_form[4:0] $1\dec58_form[4:0] - attribute \src "libresoc.v:120008.5-120008.29" + attribute \src "libresoc.v:119705.5-119705.29" switch \initial - attribute \src "libresoc.v:120008.9-120008.17" + attribute \src "libresoc.v:119705.9-119705.17" case 1'1 case end @@ -186725,14 +186259,14 @@ module \dec58 sync always update \dec58_form $0\dec58_form[4:0] end - attribute \src "libresoc.v:120023.3-120038.6" - process $proc$libresoc.v:120023$4486 + attribute \src "libresoc.v:119720.3-119735.6" + process $proc$libresoc.v:119720$4470 assign { } { } assign { } { } assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:120024.5-120024.29" + attribute \src "libresoc.v:119721.5-119721.29" switch \initial - attribute \src "libresoc.v:120024.9-120024.17" + attribute \src "libresoc.v:119721.9-119721.17" case 1'1 case end @@ -186756,14 +186290,14 @@ module \dec58 sync always update \dec58_is_32b $0\dec58_is_32b[0:0] end - attribute \src "libresoc.v:120039.3-120054.6" - process $proc$libresoc.v:120039$4487 + attribute \src "libresoc.v:119736.3-119751.6" + process $proc$libresoc.v:119736$4471 assign { } { } assign { } { } assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] - attribute \src "libresoc.v:120040.5-120040.29" + attribute \src "libresoc.v:119737.5-119737.29" switch \initial - attribute \src "libresoc.v:120040.9-120040.17" + attribute \src "libresoc.v:119737.9-119737.17" case 1'1 case end @@ -186787,14 +186321,14 @@ module \dec58 sync always update \dec58_sgn $0\dec58_sgn[0:0] end - attribute \src "libresoc.v:120055.3-120070.6" - process $proc$libresoc.v:120055$4488 + attribute \src "libresoc.v:119752.3-119767.6" + process $proc$libresoc.v:119752$4472 assign { } { } assign { } { } assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] - attribute \src "libresoc.v:120056.5-120056.29" + attribute \src "libresoc.v:119753.5-119753.29" switch \initial - attribute \src "libresoc.v:120056.9-120056.17" + attribute \src "libresoc.v:119753.9-119753.17" case 1'1 case end @@ -186818,14 +186352,14 @@ module \dec58 sync always update \dec58_lk $0\dec58_lk[0:0] end - attribute \src "libresoc.v:120071.3-120086.6" - process $proc$libresoc.v:120071$4489 + attribute \src "libresoc.v:119768.3-119783.6" + process $proc$libresoc.v:119768$4473 assign { } { } assign { } { } assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:120072.5-120072.29" + attribute \src "libresoc.v:119769.5-119769.29" switch \initial - attribute \src "libresoc.v:120072.9-120072.17" + attribute \src "libresoc.v:119769.9-119769.17" case 1'1 case end @@ -186849,14 +186383,14 @@ module \dec58 sync always update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] end - attribute \src "libresoc.v:120087.3-120102.6" - process $proc$libresoc.v:120087$4490 + attribute \src "libresoc.v:119784.3-119799.6" + process $proc$libresoc.v:119784$4474 assign { } { } assign { } { } assign $0\dec58_SV_Etype[1:0] $1\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:120088.5-120088.29" + attribute \src "libresoc.v:119785.5-119785.29" switch \initial - attribute \src "libresoc.v:120088.9-120088.17" + attribute \src "libresoc.v:119785.9-119785.17" case 1'1 case end @@ -186880,14 +186414,14 @@ module \dec58 sync always update \dec58_SV_Etype $0\dec58_SV_Etype[1:0] end - attribute \src "libresoc.v:120103.3-120118.6" - process $proc$libresoc.v:120103$4491 + attribute \src "libresoc.v:119800.3-119815.6" + process $proc$libresoc.v:119800$4475 assign { } { } assign { } { } assign $0\dec58_SV_Ptype[1:0] $1\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:120104.5-120104.29" + attribute \src "libresoc.v:119801.5-119801.29" switch \initial - attribute \src "libresoc.v:120104.9-120104.17" + attribute \src "libresoc.v:119801.9-119801.17" case 1'1 case end @@ -186911,14 +186445,14 @@ module \dec58 sync always update \dec58_SV_Ptype $0\dec58_SV_Ptype[1:0] end - attribute \src "libresoc.v:120119.3-120134.6" - process $proc$libresoc.v:120119$4492 + attribute \src "libresoc.v:119816.3-119831.6" + process $proc$libresoc.v:119816$4476 assign { } { } assign { } { } assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:120120.5-120120.29" + attribute \src "libresoc.v:119817.5-119817.29" switch \initial - attribute \src "libresoc.v:120120.9-120120.17" + attribute \src "libresoc.v:119817.9-119817.17" case 1'1 case end @@ -186942,14 +186476,14 @@ module \dec58 sync always update \dec58_in1_sel $0\dec58_in1_sel[2:0] end - attribute \src "libresoc.v:120135.3-120150.6" - process $proc$libresoc.v:120135$4493 + attribute \src "libresoc.v:119832.3-119847.6" + process $proc$libresoc.v:119832$4477 assign { } { } assign { } { } assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:120136.5-120136.29" + attribute \src "libresoc.v:119833.5-119833.29" switch \initial - attribute \src "libresoc.v:120136.9-120136.17" + attribute \src "libresoc.v:119833.9-119833.17" case 1'1 case end @@ -186973,14 +186507,14 @@ module \dec58 sync always update \dec58_in2_sel $0\dec58_in2_sel[3:0] end - attribute \src "libresoc.v:120151.3-120166.6" - process $proc$libresoc.v:120151$4494 + attribute \src "libresoc.v:119848.3-119863.6" + process $proc$libresoc.v:119848$4478 assign { } { } assign { } { } assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:120152.5-120152.29" + attribute \src "libresoc.v:119849.5-119849.29" switch \initial - attribute \src "libresoc.v:120152.9-120152.17" + attribute \src "libresoc.v:119849.9-119849.17" case 1'1 case end @@ -187004,14 +186538,14 @@ module \dec58 sync always update \dec58_in3_sel $0\dec58_in3_sel[1:0] end - attribute \src "libresoc.v:120167.3-120182.6" - process $proc$libresoc.v:120167$4495 + attribute \src "libresoc.v:119864.3-119879.6" + process $proc$libresoc.v:119864$4479 assign { } { } assign { } { } assign $0\dec58_out_sel[2:0] $1\dec58_out_sel[2:0] - attribute \src "libresoc.v:120168.5-120168.29" + attribute \src "libresoc.v:119865.5-119865.29" switch \initial - attribute \src "libresoc.v:120168.9-120168.17" + attribute \src "libresoc.v:119865.9-119865.17" case 1'1 case end @@ -187037,144 +186571,144 @@ module \dec58 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:120188.1-120967.10" +attribute \src "libresoc.v:119885.1-120664.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" attribute \generator "nMigen" module \dec62 - attribute \src "libresoc.v:120888.3-120900.6" + attribute \src "libresoc.v:120585.3-120597.6" wire width 2 $0\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:120901.3-120913.6" + attribute \src "libresoc.v:120598.3-120610.6" wire width 2 $0\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:120732.3-120744.6" + attribute \src "libresoc.v:120429.3-120441.6" wire width 8 $0\dec62_asmcode[7:0] - attribute \src "libresoc.v:120784.3-120796.6" + attribute \src "libresoc.v:120481.3-120493.6" wire $0\dec62_br[0:0] - attribute \src "libresoc.v:120550.3-120562.6" + attribute \src "libresoc.v:120247.3-120259.6" wire width 3 $0\dec62_cr_in[2:0] - attribute \src "libresoc.v:120563.3-120575.6" + attribute \src "libresoc.v:120260.3-120272.6" wire width 3 $0\dec62_cr_out[2:0] - attribute \src "libresoc.v:120719.3-120731.6" + attribute \src "libresoc.v:120416.3-120428.6" wire width 2 $0\dec62_cry_in[1:0] - attribute \src "libresoc.v:120771.3-120783.6" + attribute \src "libresoc.v:120468.3-120480.6" wire $0\dec62_cry_out[0:0] - attribute \src "libresoc.v:120823.3-120835.6" + attribute \src "libresoc.v:120520.3-120532.6" wire width 5 $0\dec62_form[4:0] - attribute \src "libresoc.v:120537.3-120549.6" + attribute \src "libresoc.v:120234.3-120246.6" wire width 14 $0\dec62_function_unit[13:0] - attribute \src "libresoc.v:120914.3-120926.6" + attribute \src "libresoc.v:120611.3-120623.6" wire width 3 $0\dec62_in1_sel[2:0] - attribute \src "libresoc.v:120927.3-120939.6" + attribute \src "libresoc.v:120624.3-120636.6" wire width 4 $0\dec62_in2_sel[3:0] - attribute \src "libresoc.v:120940.3-120952.6" + attribute \src "libresoc.v:120637.3-120649.6" wire width 2 $0\dec62_in3_sel[1:0] - attribute \src "libresoc.v:120680.3-120692.6" + attribute \src "libresoc.v:120377.3-120389.6" wire width 7 $0\dec62_internal_op[6:0] - attribute \src "libresoc.v:120745.3-120757.6" + attribute \src "libresoc.v:120442.3-120454.6" wire $0\dec62_inv_a[0:0] - attribute \src "libresoc.v:120758.3-120770.6" + attribute \src "libresoc.v:120455.3-120467.6" wire $0\dec62_inv_out[0:0] - attribute \src "libresoc.v:120836.3-120848.6" + attribute \src "libresoc.v:120533.3-120545.6" wire $0\dec62_is_32b[0:0] - attribute \src "libresoc.v:120667.3-120679.6" + attribute \src "libresoc.v:120364.3-120376.6" wire width 4 $0\dec62_ldst_len[3:0] - attribute \src "libresoc.v:120862.3-120874.6" + attribute \src "libresoc.v:120559.3-120571.6" wire $0\dec62_lk[0:0] - attribute \src "libresoc.v:120953.3-120965.6" + attribute \src "libresoc.v:120650.3-120662.6" wire width 3 $0\dec62_out_sel[2:0] - attribute \src "libresoc.v:120706.3-120718.6" + attribute \src "libresoc.v:120403.3-120415.6" wire width 2 $0\dec62_rc_sel[1:0] - attribute \src "libresoc.v:120810.3-120822.6" + attribute \src "libresoc.v:120507.3-120519.6" wire $0\dec62_rsrv[0:0] - attribute \src "libresoc.v:120875.3-120887.6" + attribute \src "libresoc.v:120572.3-120584.6" wire $0\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:120849.3-120861.6" + attribute \src "libresoc.v:120546.3-120558.6" wire $0\dec62_sgn[0:0] - attribute \src "libresoc.v:120797.3-120809.6" + attribute \src "libresoc.v:120494.3-120506.6" wire $0\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:120641.3-120653.6" + attribute \src "libresoc.v:120338.3-120350.6" wire width 3 $0\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:120654.3-120666.6" + attribute \src "libresoc.v:120351.3-120363.6" wire width 3 $0\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:120576.3-120588.6" + attribute \src "libresoc.v:120273.3-120285.6" wire width 3 $0\dec62_sv_in1[2:0] - attribute \src "libresoc.v:120589.3-120601.6" + attribute \src "libresoc.v:120286.3-120298.6" wire width 3 $0\dec62_sv_in2[2:0] - attribute \src "libresoc.v:120602.3-120614.6" + attribute \src "libresoc.v:120299.3-120311.6" wire width 3 $0\dec62_sv_in3[2:0] - attribute \src "libresoc.v:120628.3-120640.6" + attribute \src "libresoc.v:120325.3-120337.6" wire width 3 $0\dec62_sv_out2[2:0] - attribute \src "libresoc.v:120615.3-120627.6" + attribute \src "libresoc.v:120312.3-120324.6" wire width 3 $0\dec62_sv_out[2:0] - attribute \src "libresoc.v:120693.3-120705.6" + attribute \src "libresoc.v:120390.3-120402.6" wire width 2 $0\dec62_upd[1:0] - attribute \src "libresoc.v:120189.7-120189.20" + attribute \src "libresoc.v:119886.7-119886.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120888.3-120900.6" + attribute \src "libresoc.v:120585.3-120597.6" wire width 2 $1\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:120901.3-120913.6" + attribute \src "libresoc.v:120598.3-120610.6" wire width 2 $1\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:120732.3-120744.6" + attribute \src "libresoc.v:120429.3-120441.6" wire width 8 $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:120784.3-120796.6" + attribute \src "libresoc.v:120481.3-120493.6" wire $1\dec62_br[0:0] - attribute \src "libresoc.v:120550.3-120562.6" + attribute \src "libresoc.v:120247.3-120259.6" wire width 3 $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:120563.3-120575.6" + attribute \src "libresoc.v:120260.3-120272.6" wire width 3 $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:120719.3-120731.6" + attribute \src "libresoc.v:120416.3-120428.6" wire width 2 $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:120771.3-120783.6" + attribute \src "libresoc.v:120468.3-120480.6" wire $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:120823.3-120835.6" + attribute \src "libresoc.v:120520.3-120532.6" wire width 5 $1\dec62_form[4:0] - attribute \src "libresoc.v:120537.3-120549.6" + attribute \src "libresoc.v:120234.3-120246.6" wire width 14 $1\dec62_function_unit[13:0] - attribute \src "libresoc.v:120914.3-120926.6" + attribute \src "libresoc.v:120611.3-120623.6" wire width 3 $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:120927.3-120939.6" + attribute \src "libresoc.v:120624.3-120636.6" wire width 4 $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:120940.3-120952.6" + attribute \src "libresoc.v:120637.3-120649.6" wire width 2 $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:120680.3-120692.6" + attribute \src "libresoc.v:120377.3-120389.6" wire width 7 $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:120745.3-120757.6" + attribute \src "libresoc.v:120442.3-120454.6" wire $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:120758.3-120770.6" + attribute \src "libresoc.v:120455.3-120467.6" wire $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:120836.3-120848.6" + attribute \src "libresoc.v:120533.3-120545.6" wire $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:120667.3-120679.6" + attribute \src "libresoc.v:120364.3-120376.6" wire width 4 $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:120862.3-120874.6" + attribute \src "libresoc.v:120559.3-120571.6" wire $1\dec62_lk[0:0] - attribute \src "libresoc.v:120953.3-120965.6" + attribute \src "libresoc.v:120650.3-120662.6" wire width 3 $1\dec62_out_sel[2:0] - attribute \src "libresoc.v:120706.3-120718.6" + attribute \src "libresoc.v:120403.3-120415.6" wire width 2 $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:120810.3-120822.6" + attribute \src "libresoc.v:120507.3-120519.6" wire $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:120875.3-120887.6" + attribute \src "libresoc.v:120572.3-120584.6" wire $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:120849.3-120861.6" + attribute \src "libresoc.v:120546.3-120558.6" wire $1\dec62_sgn[0:0] - attribute \src "libresoc.v:120797.3-120809.6" + attribute \src "libresoc.v:120494.3-120506.6" wire $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:120641.3-120653.6" + attribute \src "libresoc.v:120338.3-120350.6" wire width 3 $1\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:120654.3-120666.6" + attribute \src "libresoc.v:120351.3-120363.6" wire width 3 $1\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:120576.3-120588.6" + attribute \src "libresoc.v:120273.3-120285.6" wire width 3 $1\dec62_sv_in1[2:0] - attribute \src "libresoc.v:120589.3-120601.6" + attribute \src "libresoc.v:120286.3-120298.6" wire width 3 $1\dec62_sv_in2[2:0] - attribute \src "libresoc.v:120602.3-120614.6" + attribute \src "libresoc.v:120299.3-120311.6" wire width 3 $1\dec62_sv_in3[2:0] - attribute \src "libresoc.v:120628.3-120640.6" + attribute \src "libresoc.v:120325.3-120337.6" wire width 3 $1\dec62_sv_out2[2:0] - attribute \src "libresoc.v:120615.3-120627.6" + attribute \src "libresoc.v:120312.3-120324.6" wire width 3 $1\dec62_sv_out[2:0] - attribute \src "libresoc.v:120693.3-120705.6" + attribute \src "libresoc.v:120390.3-120402.6" wire width 2 $1\dec62_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -187486,28 +187020,28 @@ module \dec62 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec62_upd - attribute \src "libresoc.v:120189.7-120189.15" + attribute \src "libresoc.v:119886.7-119886.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch - attribute \src "libresoc.v:120189.7-120189.20" - process $proc$libresoc.v:120189$4530 + attribute \src "libresoc.v:119886.7-119886.20" + process $proc$libresoc.v:119886$4514 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120537.3-120549.6" - process $proc$libresoc.v:120537$4497 + attribute \src "libresoc.v:120234.3-120246.6" + process $proc$libresoc.v:120234$4481 assign { } { } assign { } { } assign $0\dec62_function_unit[13:0] $1\dec62_function_unit[13:0] - attribute \src "libresoc.v:120538.5-120538.29" + attribute \src "libresoc.v:120235.5-120235.29" switch \initial - attribute \src "libresoc.v:120538.9-120538.17" + attribute \src "libresoc.v:120235.9-120235.17" case 1'1 case end @@ -187527,14 +187061,14 @@ module \dec62 sync always update \dec62_function_unit $0\dec62_function_unit[13:0] end - attribute \src "libresoc.v:120550.3-120562.6" - process $proc$libresoc.v:120550$4498 + attribute \src "libresoc.v:120247.3-120259.6" + process $proc$libresoc.v:120247$4482 assign { } { } assign { } { } assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:120551.5-120551.29" + attribute \src "libresoc.v:120248.5-120248.29" switch \initial - attribute \src "libresoc.v:120551.9-120551.17" + attribute \src "libresoc.v:120248.9-120248.17" case 1'1 case end @@ -187554,14 +187088,14 @@ module \dec62 sync always update \dec62_cr_in $0\dec62_cr_in[2:0] end - attribute \src "libresoc.v:120563.3-120575.6" - process $proc$libresoc.v:120563$4499 + attribute \src "libresoc.v:120260.3-120272.6" + process $proc$libresoc.v:120260$4483 assign { } { } assign { } { } assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:120564.5-120564.29" + attribute \src "libresoc.v:120261.5-120261.29" switch \initial - attribute \src "libresoc.v:120564.9-120564.17" + attribute \src "libresoc.v:120261.9-120261.17" case 1'1 case end @@ -187581,14 +187115,14 @@ module \dec62 sync always update \dec62_cr_out $0\dec62_cr_out[2:0] end - attribute \src "libresoc.v:120576.3-120588.6" - process $proc$libresoc.v:120576$4500 + attribute \src "libresoc.v:120273.3-120285.6" + process $proc$libresoc.v:120273$4484 assign { } { } assign { } { } assign $0\dec62_sv_in1[2:0] $1\dec62_sv_in1[2:0] - attribute \src "libresoc.v:120577.5-120577.29" + attribute \src "libresoc.v:120274.5-120274.29" switch \initial - attribute \src "libresoc.v:120577.9-120577.17" + attribute \src "libresoc.v:120274.9-120274.17" case 1'1 case end @@ -187608,14 +187142,14 @@ module \dec62 sync always update \dec62_sv_in1 $0\dec62_sv_in1[2:0] end - attribute \src "libresoc.v:120589.3-120601.6" - process $proc$libresoc.v:120589$4501 + attribute \src "libresoc.v:120286.3-120298.6" + process $proc$libresoc.v:120286$4485 assign { } { } assign { } { } assign $0\dec62_sv_in2[2:0] $1\dec62_sv_in2[2:0] - attribute \src "libresoc.v:120590.5-120590.29" + attribute \src "libresoc.v:120287.5-120287.29" switch \initial - attribute \src "libresoc.v:120590.9-120590.17" + attribute \src "libresoc.v:120287.9-120287.17" case 1'1 case end @@ -187635,14 +187169,14 @@ module \dec62 sync always update \dec62_sv_in2 $0\dec62_sv_in2[2:0] end - attribute \src "libresoc.v:120602.3-120614.6" - process $proc$libresoc.v:120602$4502 + attribute \src "libresoc.v:120299.3-120311.6" + process $proc$libresoc.v:120299$4486 assign { } { } assign { } { } assign $0\dec62_sv_in3[2:0] $1\dec62_sv_in3[2:0] - attribute \src "libresoc.v:120603.5-120603.29" + attribute \src "libresoc.v:120300.5-120300.29" switch \initial - attribute \src "libresoc.v:120603.9-120603.17" + attribute \src "libresoc.v:120300.9-120300.17" case 1'1 case end @@ -187662,14 +187196,14 @@ module \dec62 sync always update \dec62_sv_in3 $0\dec62_sv_in3[2:0] end - attribute \src "libresoc.v:120615.3-120627.6" - process $proc$libresoc.v:120615$4503 + attribute \src "libresoc.v:120312.3-120324.6" + process $proc$libresoc.v:120312$4487 assign { } { } assign { } { } assign $0\dec62_sv_out[2:0] $1\dec62_sv_out[2:0] - attribute \src "libresoc.v:120616.5-120616.29" + attribute \src "libresoc.v:120313.5-120313.29" switch \initial - attribute \src "libresoc.v:120616.9-120616.17" + attribute \src "libresoc.v:120313.9-120313.17" case 1'1 case end @@ -187689,14 +187223,14 @@ module \dec62 sync always update \dec62_sv_out $0\dec62_sv_out[2:0] end - attribute \src "libresoc.v:120628.3-120640.6" - process $proc$libresoc.v:120628$4504 + attribute \src "libresoc.v:120325.3-120337.6" + process $proc$libresoc.v:120325$4488 assign { } { } assign { } { } assign $0\dec62_sv_out2[2:0] $1\dec62_sv_out2[2:0] - attribute \src "libresoc.v:120629.5-120629.29" + attribute \src "libresoc.v:120326.5-120326.29" switch \initial - attribute \src "libresoc.v:120629.9-120629.17" + attribute \src "libresoc.v:120326.9-120326.17" case 1'1 case end @@ -187716,14 +187250,14 @@ module \dec62 sync always update \dec62_sv_out2 $0\dec62_sv_out2[2:0] end - attribute \src "libresoc.v:120641.3-120653.6" - process $proc$libresoc.v:120641$4505 + attribute \src "libresoc.v:120338.3-120350.6" + process $proc$libresoc.v:120338$4489 assign { } { } assign { } { } assign $0\dec62_sv_cr_in[2:0] $1\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:120642.5-120642.29" + attribute \src "libresoc.v:120339.5-120339.29" switch \initial - attribute \src "libresoc.v:120642.9-120642.17" + attribute \src "libresoc.v:120339.9-120339.17" case 1'1 case end @@ -187743,14 +187277,14 @@ module \dec62 sync always update \dec62_sv_cr_in $0\dec62_sv_cr_in[2:0] end - attribute \src "libresoc.v:120654.3-120666.6" - process $proc$libresoc.v:120654$4506 + attribute \src "libresoc.v:120351.3-120363.6" + process $proc$libresoc.v:120351$4490 assign { } { } assign { } { } assign $0\dec62_sv_cr_out[2:0] $1\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:120655.5-120655.29" + attribute \src "libresoc.v:120352.5-120352.29" switch \initial - attribute \src "libresoc.v:120655.9-120655.17" + attribute \src "libresoc.v:120352.9-120352.17" case 1'1 case end @@ -187770,14 +187304,14 @@ module \dec62 sync always update \dec62_sv_cr_out $0\dec62_sv_cr_out[2:0] end - attribute \src "libresoc.v:120667.3-120679.6" - process $proc$libresoc.v:120667$4507 + attribute \src "libresoc.v:120364.3-120376.6" + process $proc$libresoc.v:120364$4491 assign { } { } assign { } { } assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:120668.5-120668.29" + attribute \src "libresoc.v:120365.5-120365.29" switch \initial - attribute \src "libresoc.v:120668.9-120668.17" + attribute \src "libresoc.v:120365.9-120365.17" case 1'1 case end @@ -187797,14 +187331,14 @@ module \dec62 sync always update \dec62_ldst_len $0\dec62_ldst_len[3:0] end - attribute \src "libresoc.v:120680.3-120692.6" - process $proc$libresoc.v:120680$4508 + attribute \src "libresoc.v:120377.3-120389.6" + process $proc$libresoc.v:120377$4492 assign { } { } assign { } { } assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:120681.5-120681.29" + attribute \src "libresoc.v:120378.5-120378.29" switch \initial - attribute \src "libresoc.v:120681.9-120681.17" + attribute \src "libresoc.v:120378.9-120378.17" case 1'1 case end @@ -187824,14 +187358,14 @@ module \dec62 sync always update \dec62_internal_op $0\dec62_internal_op[6:0] end - attribute \src "libresoc.v:120693.3-120705.6" - process $proc$libresoc.v:120693$4509 + attribute \src "libresoc.v:120390.3-120402.6" + process $proc$libresoc.v:120390$4493 assign { } { } assign { } { } assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] - attribute \src "libresoc.v:120694.5-120694.29" + attribute \src "libresoc.v:120391.5-120391.29" switch \initial - attribute \src "libresoc.v:120694.9-120694.17" + attribute \src "libresoc.v:120391.9-120391.17" case 1'1 case end @@ -187851,14 +187385,14 @@ module \dec62 sync always update \dec62_upd $0\dec62_upd[1:0] end - attribute \src "libresoc.v:120706.3-120718.6" - process $proc$libresoc.v:120706$4510 + attribute \src "libresoc.v:120403.3-120415.6" + process $proc$libresoc.v:120403$4494 assign { } { } assign { } { } assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:120707.5-120707.29" + attribute \src "libresoc.v:120404.5-120404.29" switch \initial - attribute \src "libresoc.v:120707.9-120707.17" + attribute \src "libresoc.v:120404.9-120404.17" case 1'1 case end @@ -187878,14 +187412,14 @@ module \dec62 sync always update \dec62_rc_sel $0\dec62_rc_sel[1:0] end - attribute \src "libresoc.v:120719.3-120731.6" - process $proc$libresoc.v:120719$4511 + attribute \src "libresoc.v:120416.3-120428.6" + process $proc$libresoc.v:120416$4495 assign { } { } assign { } { } assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:120720.5-120720.29" + attribute \src "libresoc.v:120417.5-120417.29" switch \initial - attribute \src "libresoc.v:120720.9-120720.17" + attribute \src "libresoc.v:120417.9-120417.17" case 1'1 case end @@ -187905,14 +187439,14 @@ module \dec62 sync always update \dec62_cry_in $0\dec62_cry_in[1:0] end - attribute \src "libresoc.v:120732.3-120744.6" - process $proc$libresoc.v:120732$4512 + attribute \src "libresoc.v:120429.3-120441.6" + process $proc$libresoc.v:120429$4496 assign { } { } assign { } { } assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:120733.5-120733.29" + attribute \src "libresoc.v:120430.5-120430.29" switch \initial - attribute \src "libresoc.v:120733.9-120733.17" + attribute \src "libresoc.v:120430.9-120430.17" case 1'1 case end @@ -187932,14 +187466,14 @@ module \dec62 sync always update \dec62_asmcode $0\dec62_asmcode[7:0] end - attribute \src "libresoc.v:120745.3-120757.6" - process $proc$libresoc.v:120745$4513 + attribute \src "libresoc.v:120442.3-120454.6" + process $proc$libresoc.v:120442$4497 assign { } { } assign { } { } assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:120746.5-120746.29" + attribute \src "libresoc.v:120443.5-120443.29" switch \initial - attribute \src "libresoc.v:120746.9-120746.17" + attribute \src "libresoc.v:120443.9-120443.17" case 1'1 case end @@ -187959,14 +187493,14 @@ module \dec62 sync always update \dec62_inv_a $0\dec62_inv_a[0:0] end - attribute \src "libresoc.v:120758.3-120770.6" - process $proc$libresoc.v:120758$4514 + attribute \src "libresoc.v:120455.3-120467.6" + process $proc$libresoc.v:120455$4498 assign { } { } assign { } { } assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:120759.5-120759.29" + attribute \src "libresoc.v:120456.5-120456.29" switch \initial - attribute \src "libresoc.v:120759.9-120759.17" + attribute \src "libresoc.v:120456.9-120456.17" case 1'1 case end @@ -187986,14 +187520,14 @@ module \dec62 sync always update \dec62_inv_out $0\dec62_inv_out[0:0] end - attribute \src "libresoc.v:120771.3-120783.6" - process $proc$libresoc.v:120771$4515 + attribute \src "libresoc.v:120468.3-120480.6" + process $proc$libresoc.v:120468$4499 assign { } { } assign { } { } assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:120772.5-120772.29" + attribute \src "libresoc.v:120469.5-120469.29" switch \initial - attribute \src "libresoc.v:120772.9-120772.17" + attribute \src "libresoc.v:120469.9-120469.17" case 1'1 case end @@ -188013,14 +187547,14 @@ module \dec62 sync always update \dec62_cry_out $0\dec62_cry_out[0:0] end - attribute \src "libresoc.v:120784.3-120796.6" - process $proc$libresoc.v:120784$4516 + attribute \src "libresoc.v:120481.3-120493.6" + process $proc$libresoc.v:120481$4500 assign { } { } assign { } { } assign $0\dec62_br[0:0] $1\dec62_br[0:0] - attribute \src "libresoc.v:120785.5-120785.29" + attribute \src "libresoc.v:120482.5-120482.29" switch \initial - attribute \src "libresoc.v:120785.9-120785.17" + attribute \src "libresoc.v:120482.9-120482.17" case 1'1 case end @@ -188040,14 +187574,14 @@ module \dec62 sync always update \dec62_br $0\dec62_br[0:0] end - attribute \src "libresoc.v:120797.3-120809.6" - process $proc$libresoc.v:120797$4517 + attribute \src "libresoc.v:120494.3-120506.6" + process $proc$libresoc.v:120494$4501 assign { } { } assign { } { } assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:120798.5-120798.29" + attribute \src "libresoc.v:120495.5-120495.29" switch \initial - attribute \src "libresoc.v:120798.9-120798.17" + attribute \src "libresoc.v:120495.9-120495.17" case 1'1 case end @@ -188067,14 +187601,14 @@ module \dec62 sync always update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] end - attribute \src "libresoc.v:120810.3-120822.6" - process $proc$libresoc.v:120810$4518 + attribute \src "libresoc.v:120507.3-120519.6" + process $proc$libresoc.v:120507$4502 assign { } { } assign { } { } assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:120811.5-120811.29" + attribute \src "libresoc.v:120508.5-120508.29" switch \initial - attribute \src "libresoc.v:120811.9-120811.17" + attribute \src "libresoc.v:120508.9-120508.17" case 1'1 case end @@ -188094,14 +187628,14 @@ module \dec62 sync always update \dec62_rsrv $0\dec62_rsrv[0:0] end - attribute \src "libresoc.v:120823.3-120835.6" - process $proc$libresoc.v:120823$4519 + attribute \src "libresoc.v:120520.3-120532.6" + process $proc$libresoc.v:120520$4503 assign { } { } assign { } { } assign $0\dec62_form[4:0] $1\dec62_form[4:0] - attribute \src "libresoc.v:120824.5-120824.29" + attribute \src "libresoc.v:120521.5-120521.29" switch \initial - attribute \src "libresoc.v:120824.9-120824.17" + attribute \src "libresoc.v:120521.9-120521.17" case 1'1 case end @@ -188121,14 +187655,14 @@ module \dec62 sync always update \dec62_form $0\dec62_form[4:0] end - attribute \src "libresoc.v:120836.3-120848.6" - process $proc$libresoc.v:120836$4520 + attribute \src "libresoc.v:120533.3-120545.6" + process $proc$libresoc.v:120533$4504 assign { } { } assign { } { } assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:120837.5-120837.29" + attribute \src "libresoc.v:120534.5-120534.29" switch \initial - attribute \src "libresoc.v:120837.9-120837.17" + attribute \src "libresoc.v:120534.9-120534.17" case 1'1 case end @@ -188148,14 +187682,14 @@ module \dec62 sync always update \dec62_is_32b $0\dec62_is_32b[0:0] end - attribute \src "libresoc.v:120849.3-120861.6" - process $proc$libresoc.v:120849$4521 + attribute \src "libresoc.v:120546.3-120558.6" + process $proc$libresoc.v:120546$4505 assign { } { } assign { } { } assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] - attribute \src "libresoc.v:120850.5-120850.29" + attribute \src "libresoc.v:120547.5-120547.29" switch \initial - attribute \src "libresoc.v:120850.9-120850.17" + attribute \src "libresoc.v:120547.9-120547.17" case 1'1 case end @@ -188175,14 +187709,14 @@ module \dec62 sync always update \dec62_sgn $0\dec62_sgn[0:0] end - attribute \src "libresoc.v:120862.3-120874.6" - process $proc$libresoc.v:120862$4522 + attribute \src "libresoc.v:120559.3-120571.6" + process $proc$libresoc.v:120559$4506 assign { } { } assign { } { } assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] - attribute \src "libresoc.v:120863.5-120863.29" + attribute \src "libresoc.v:120560.5-120560.29" switch \initial - attribute \src "libresoc.v:120863.9-120863.17" + attribute \src "libresoc.v:120560.9-120560.17" case 1'1 case end @@ -188202,14 +187736,14 @@ module \dec62 sync always update \dec62_lk $0\dec62_lk[0:0] end - attribute \src "libresoc.v:120875.3-120887.6" - process $proc$libresoc.v:120875$4523 + attribute \src "libresoc.v:120572.3-120584.6" + process $proc$libresoc.v:120572$4507 assign { } { } assign { } { } assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:120876.5-120876.29" + attribute \src "libresoc.v:120573.5-120573.29" switch \initial - attribute \src "libresoc.v:120876.9-120876.17" + attribute \src "libresoc.v:120573.9-120573.17" case 1'1 case end @@ -188229,14 +187763,14 @@ module \dec62 sync always update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] end - attribute \src "libresoc.v:120888.3-120900.6" - process $proc$libresoc.v:120888$4524 + attribute \src "libresoc.v:120585.3-120597.6" + process $proc$libresoc.v:120585$4508 assign { } { } assign { } { } assign $0\dec62_SV_Etype[1:0] $1\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:120889.5-120889.29" + attribute \src "libresoc.v:120586.5-120586.29" switch \initial - attribute \src "libresoc.v:120889.9-120889.17" + attribute \src "libresoc.v:120586.9-120586.17" case 1'1 case end @@ -188256,14 +187790,14 @@ module \dec62 sync always update \dec62_SV_Etype $0\dec62_SV_Etype[1:0] end - attribute \src "libresoc.v:120901.3-120913.6" - process $proc$libresoc.v:120901$4525 + attribute \src "libresoc.v:120598.3-120610.6" + process $proc$libresoc.v:120598$4509 assign { } { } assign { } { } assign $0\dec62_SV_Ptype[1:0] $1\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:120902.5-120902.29" + attribute \src "libresoc.v:120599.5-120599.29" switch \initial - attribute \src "libresoc.v:120902.9-120902.17" + attribute \src "libresoc.v:120599.9-120599.17" case 1'1 case end @@ -188283,14 +187817,14 @@ module \dec62 sync always update \dec62_SV_Ptype $0\dec62_SV_Ptype[1:0] end - attribute \src "libresoc.v:120914.3-120926.6" - process $proc$libresoc.v:120914$4526 + attribute \src "libresoc.v:120611.3-120623.6" + process $proc$libresoc.v:120611$4510 assign { } { } assign { } { } assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:120915.5-120915.29" + attribute \src "libresoc.v:120612.5-120612.29" switch \initial - attribute \src "libresoc.v:120915.9-120915.17" + attribute \src "libresoc.v:120612.9-120612.17" case 1'1 case end @@ -188310,14 +187844,14 @@ module \dec62 sync always update \dec62_in1_sel $0\dec62_in1_sel[2:0] end - attribute \src "libresoc.v:120927.3-120939.6" - process $proc$libresoc.v:120927$4527 + attribute \src "libresoc.v:120624.3-120636.6" + process $proc$libresoc.v:120624$4511 assign { } { } assign { } { } assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:120928.5-120928.29" + attribute \src "libresoc.v:120625.5-120625.29" switch \initial - attribute \src "libresoc.v:120928.9-120928.17" + attribute \src "libresoc.v:120625.9-120625.17" case 1'1 case end @@ -188337,14 +187871,14 @@ module \dec62 sync always update \dec62_in2_sel $0\dec62_in2_sel[3:0] end - attribute \src "libresoc.v:120940.3-120952.6" - process $proc$libresoc.v:120940$4528 + attribute \src "libresoc.v:120637.3-120649.6" + process $proc$libresoc.v:120637$4512 assign { } { } assign { } { } assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:120941.5-120941.29" + attribute \src "libresoc.v:120638.5-120638.29" switch \initial - attribute \src "libresoc.v:120941.9-120941.17" + attribute \src "libresoc.v:120638.9-120638.17" case 1'1 case end @@ -188364,14 +187898,14 @@ module \dec62 sync always update \dec62_in3_sel $0\dec62_in3_sel[1:0] end - attribute \src "libresoc.v:120953.3-120965.6" - process $proc$libresoc.v:120953$4529 + attribute \src "libresoc.v:120650.3-120662.6" + process $proc$libresoc.v:120650$4513 assign { } { } assign { } { } assign $0\dec62_out_sel[2:0] $1\dec62_out_sel[2:0] - attribute \src "libresoc.v:120954.5-120954.29" + attribute \src "libresoc.v:120651.5-120651.29" switch \initial - attribute \src "libresoc.v:120954.9-120954.17" + attribute \src "libresoc.v:120651.9-120651.17" case 1'1 case end @@ -188393,120 +187927,120 @@ module \dec62 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:120971.1-121554.10" +attribute \src "libresoc.v:120668.1-121251.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" attribute \generator "nMigen" module \dec_ALU - attribute \src "libresoc.v:121517.3-121531.6" + attribute \src "libresoc.v:121214.3-121228.6" wire width 14 $0\ALU__fn_unit[13:0] - attribute \src "libresoc.v:121504.3-121516.6" + attribute \src "libresoc.v:121201.3-121213.6" wire width 7 $0\ALU__insn_type[6:0] - attribute \src "libresoc.v:121489.3-121503.6" + attribute \src "libresoc.v:121186.3-121200.6" wire $0\ALU__write_cr0[0:0] - attribute \src "libresoc.v:120972.7-120972.20" + attribute \src "libresoc.v:120669.7-120669.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121517.3-121531.6" + attribute \src "libresoc.v:121214.3-121228.6" wire width 14 $1\ALU__fn_unit[13:0] - attribute \src "libresoc.v:121504.3-121516.6" + attribute \src "libresoc.v:121201.3-121213.6" wire width 7 $1\ALU__insn_type[6:0] - attribute \src "libresoc.v:121489.3-121503.6" + attribute \src "libresoc.v:121186.3-121200.6" wire $1\ALU__write_cr0[0:0] - attribute \src "libresoc.v:121405.18-121405.113" - wire $and$libresoc.v:121405$4531_Y - attribute \src "libresoc.v:121407.18-121407.110" - wire $and$libresoc.v:121407$4533_Y - attribute \src "libresoc.v:121420.18-121420.114" - wire $and$libresoc.v:121420$4546_Y - attribute \src "libresoc.v:121421.18-121421.116" - wire $and$libresoc.v:121421$4547_Y - attribute \src "libresoc.v:121423.18-121423.114" - wire $and$libresoc.v:121423$4549_Y - attribute \src "libresoc.v:121425.18-121425.110" - wire $and$libresoc.v:121425$4551_Y - attribute \src "libresoc.v:121426.17-121426.112" - wire $and$libresoc.v:121426$4552_Y - attribute \src "libresoc.v:121427.17-121427.114" - wire $and$libresoc.v:121427$4553_Y - attribute \src "libresoc.v:121408.18-121408.126" - wire $eq$libresoc.v:121408$4534_Y - attribute \src "libresoc.v:121409.18-121409.126" - wire $eq$libresoc.v:121409$4535_Y - attribute \src "libresoc.v:121411.18-121411.110" - wire $eq$libresoc.v:121411$4537_Y - attribute \src "libresoc.v:121412.18-121412.110" - wire $eq$libresoc.v:121412$4538_Y - attribute \src "libresoc.v:121414.18-121414.112" - wire $eq$libresoc.v:121414$4540_Y - attribute \src "libresoc.v:121415.17-121415.130" - wire $eq$libresoc.v:121415$4541_Y - attribute \src "libresoc.v:121417.18-121417.110" - wire $eq$libresoc.v:121417$4543_Y - attribute \src "libresoc.v:121419.18-121419.131" - wire $eq$libresoc.v:121419$4545_Y - attribute \src "libresoc.v:121422.18-121422.131" - wire $eq$libresoc.v:121422$4548_Y - attribute \src "libresoc.v:121428.17-121428.130" - wire $eq$libresoc.v:121428$4554_Y - attribute \src "libresoc.v:121406.18-121406.110" - wire $not$libresoc.v:121406$4532_Y - attribute \src "libresoc.v:121424.18-121424.110" - wire $not$libresoc.v:121424$4550_Y - attribute \src "libresoc.v:121410.18-121410.110" - wire $or$libresoc.v:121410$4536_Y - attribute \src "libresoc.v:121413.18-121413.110" - wire $or$libresoc.v:121413$4539_Y - attribute \src "libresoc.v:121416.18-121416.110" - wire $or$libresoc.v:121416$4542_Y - attribute \src "libresoc.v:121418.18-121418.110" - wire $or$libresoc.v:121418$4544_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "libresoc.v:121102.18-121102.113" + wire $and$libresoc.v:121102$4515_Y + attribute \src "libresoc.v:121104.18-121104.110" + wire $and$libresoc.v:121104$4517_Y + attribute \src "libresoc.v:121117.18-121117.114" + wire $and$libresoc.v:121117$4530_Y + attribute \src "libresoc.v:121118.18-121118.116" + wire $and$libresoc.v:121118$4531_Y + attribute \src "libresoc.v:121120.18-121120.114" + wire $and$libresoc.v:121120$4533_Y + attribute \src "libresoc.v:121122.18-121122.110" + wire $and$libresoc.v:121122$4535_Y + attribute \src "libresoc.v:121123.17-121123.112" + wire $and$libresoc.v:121123$4536_Y + attribute \src "libresoc.v:121124.17-121124.114" + wire $and$libresoc.v:121124$4537_Y + attribute \src "libresoc.v:121105.18-121105.126" + wire $eq$libresoc.v:121105$4518_Y + attribute \src "libresoc.v:121106.18-121106.126" + wire $eq$libresoc.v:121106$4519_Y + attribute \src "libresoc.v:121108.18-121108.110" + wire $eq$libresoc.v:121108$4521_Y + attribute \src "libresoc.v:121109.18-121109.110" + wire $eq$libresoc.v:121109$4522_Y + attribute \src "libresoc.v:121111.18-121111.112" + wire $eq$libresoc.v:121111$4524_Y + attribute \src "libresoc.v:121112.17-121112.130" + wire $eq$libresoc.v:121112$4525_Y + attribute \src "libresoc.v:121114.18-121114.110" + wire $eq$libresoc.v:121114$4527_Y + attribute \src "libresoc.v:121116.18-121116.131" + wire $eq$libresoc.v:121116$4529_Y + attribute \src "libresoc.v:121119.18-121119.131" + wire $eq$libresoc.v:121119$4532_Y + attribute \src "libresoc.v:121125.17-121125.130" + wire $eq$libresoc.v:121125$4538_Y + attribute \src "libresoc.v:121103.18-121103.110" + wire $not$libresoc.v:121103$4516_Y + attribute \src "libresoc.v:121121.18-121121.110" + wire $not$libresoc.v:121121$4534_Y + attribute \src "libresoc.v:121107.18-121107.110" + wire $or$libresoc.v:121107$4520_Y + attribute \src "libresoc.v:121110.18-121110.110" + wire $or$libresoc.v:121110$4523_Y + attribute \src "libresoc.v:121113.18-121113.110" + wire $or$libresoc.v:121113$4526_Y + attribute \src "libresoc.v:121115.18-121115.110" + wire $or$libresoc.v:121115$4528_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 19 \ALU__data_len @@ -188820,7 +188354,7 @@ module \dec_ALU wire \dec_ALU_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -188828,13 +188362,13 @@ module \dec_ALU attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire \dec_ai_sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -188851,48 +188385,48 @@ module \dec_ALU attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:120972.7-120972.15" + attribute \src "libresoc.v:120669.7-120669.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire input 2 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121405$4531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:121102$4515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188900,10 +188434,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:121405$4531_Y + connect \Y $and$libresoc.v:121102$4515_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121407$4533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:121104$4517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188911,10 +188445,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:121407$4533_Y + connect \Y $and$libresoc.v:121104$4517_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121420$4546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:121117$4530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188922,10 +188456,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:121420$4546_Y + connect \Y $and$libresoc.v:121117$4530_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121421$4547 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:121118$4531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188933,10 +188467,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121421$4547_Y + connect \Y $and$libresoc.v:121118$4531_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121423$4549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:121120$4533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188944,10 +188478,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:121423$4549_Y + connect \Y $and$libresoc.v:121120$4533_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121425$4551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:121122$4535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188955,10 +188489,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:121425$4551_Y + connect \Y $and$libresoc.v:121122$4535_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121426$4552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:121123$4536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188966,10 +188500,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:121426$4552_Y + connect \Y $and$libresoc.v:121123$4536_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121427$4553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:121124$4537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188977,10 +188511,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121427$4553_Y + connect \Y $and$libresoc.v:121124$4537_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:121408$4534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" + cell $eq $eq$libresoc.v:121105$4518 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188988,10 +188522,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:121408$4534_Y + connect \Y $eq$libresoc.v:121105$4518_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:121409$4535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $eq $eq$libresoc.v:121106$4519 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188999,10 +188533,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:121409$4535_Y + connect \Y $eq$libresoc.v:121106$4519_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121411$4537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:121108$4521 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189010,10 +188544,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:121411$4537_Y + connect \Y $eq$libresoc.v:121108$4521_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121412$4538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:121109$4522 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189021,10 +188555,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:121412$4538_Y + connect \Y $eq$libresoc.v:121109$4522_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121414$4540 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:121111$4524 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189032,10 +188566,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:121414$4540_Y + connect \Y $eq$libresoc.v:121111$4524_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:121415$4541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:121112$4525 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189043,10 +188577,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121415$4541_Y + connect \Y $eq$libresoc.v:121112$4525_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:121417$4543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $eq $eq$libresoc.v:121114$4527 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189054,10 +188588,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:121417$4543_Y + connect \Y $eq$libresoc.v:121114$4527_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:121419$4545 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:121116$4529 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189065,10 +188599,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121419$4545_Y + connect \Y $eq$libresoc.v:121116$4529_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:121422$4548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:121119$4532 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189076,10 +188610,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121422$4548_Y + connect \Y $eq$libresoc.v:121119$4532_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:121428$4554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:121125$4538 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189087,26 +188621,26 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121428$4554_Y + connect \Y $eq$libresoc.v:121125$4538_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:121406$4532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:121103$4516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121406$4532_Y + connect \Y $not$libresoc.v:121103$4516_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:121424$4550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:121121$4534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121424$4550_Y + connect \Y $not$libresoc.v:121121$4534_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:121410$4536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $or $or$libresoc.v:121107$4520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189114,10 +188648,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:121410$4536_Y + connect \Y $or$libresoc.v:121107$4520_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:121413$4539 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:121110$4523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189125,10 +188659,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:121413$4539_Y + connect \Y $or$libresoc.v:121110$4523_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:121416$4542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:121113$4526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189136,10 +188670,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:121416$4542_Y + connect \Y $or$libresoc.v:121113$4526_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:121418$4544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $or $or$libresoc.v:121115$4528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189147,10 +188681,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:121418$4544_Y + connect \Y $or$libresoc.v:121115$4528_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121429.7-121457.4" + attribute \src "libresoc.v:121126.7-121154.4" cell \dec \dec connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS @@ -189181,7 +188715,7 @@ module \dec_ALU connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121458.10-121463.4" + attribute \src "libresoc.v:121155.10-121160.4" cell \dec_ai \dec_ai connect \ALU_RA \dec_ALU_RA connect \immz_out \dec_ai_immz_out @@ -189189,7 +188723,7 @@ module \dec_ALU connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:121464.10-121475.4" + attribute \src "libresoc.v:121161.10-121172.4" cell \dec_bi \dec_bi connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS @@ -189203,7 +188737,7 @@ module \dec_ALU connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121476.10-121482.4" + attribute \src "libresoc.v:121173.10-121179.4" cell \dec_oe \dec_oe connect \ALU_OE \dec_ALU_OE connect \ALU_internal_op \dec_ALU_internal_op @@ -189212,33 +188746,33 @@ module \dec_ALU connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121483.10-121488.4" + attribute \src "libresoc.v:121180.10-121185.4" cell \dec_rc \dec_rc connect \ALU_Rc \dec_ALU_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:120972.7-120972.20" - process $proc$libresoc.v:120972$4558 + attribute \src "libresoc.v:120669.7-120669.20" + process $proc$libresoc.v:120669$4542 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121489.3-121503.6" - process $proc$libresoc.v:121489$4555 + attribute \src "libresoc.v:121186.3-121200.6" + process $proc$libresoc.v:121186$4539 assign { } { } assign { } { } assign $0\ALU__write_cr0[0:0] $1\ALU__write_cr0[0:0] - attribute \src "libresoc.v:121490.5-121490.29" + attribute \src "libresoc.v:121187.5-121187.29" switch \initial - attribute \src "libresoc.v:121490.9-121490.17" + attribute \src "libresoc.v:121187.9-121187.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" switch \dec_ALU_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -189254,18 +188788,18 @@ module \dec_ALU sync always update \ALU__write_cr0 $0\ALU__write_cr0[0:0] end - attribute \src "libresoc.v:121504.3-121516.6" - process $proc$libresoc.v:121504$4556 + attribute \src "libresoc.v:121201.3-121213.6" + process $proc$libresoc.v:121201$4540 assign { } { } assign { } { } assign $0\ALU__insn_type[6:0] $1\ALU__insn_type[6:0] - attribute \src "libresoc.v:121505.5-121505.29" + attribute \src "libresoc.v:121202.5-121202.29" switch \initial - attribute \src "libresoc.v:121505.9-121505.17" + attribute \src "libresoc.v:121202.9-121202.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -189281,17 +188815,17 @@ module \dec_ALU sync always update \ALU__insn_type $0\ALU__insn_type[6:0] end - attribute \src "libresoc.v:121517.3-121531.6" - process $proc$libresoc.v:121517$4557 + attribute \src "libresoc.v:121214.3-121228.6" + process $proc$libresoc.v:121214$4541 assign { } { } assign $0\ALU__fn_unit[13:0] $1\ALU__fn_unit[13:0] - attribute \src "libresoc.v:121518.5-121518.29" + attribute \src "libresoc.v:121215.5-121215.29" switch \initial - attribute \src "libresoc.v:121518.9-121518.17" + attribute \src "libresoc.v:121215.9-121215.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -189309,30 +188843,30 @@ module \dec_ALU sync always update \ALU__fn_unit $0\ALU__fn_unit[13:0] end - connect \$10 $and$libresoc.v:121405$4531_Y - connect \$12 $not$libresoc.v:121406$4532_Y - connect \$14 $and$libresoc.v:121407$4533_Y - connect \$16 $eq$libresoc.v:121408$4534_Y - connect \$18 $eq$libresoc.v:121409$4535_Y - connect \$20 $or$libresoc.v:121410$4536_Y - connect \$22 $eq$libresoc.v:121411$4537_Y - connect \$24 $eq$libresoc.v:121412$4538_Y - connect \$26 $or$libresoc.v:121413$4539_Y - connect \$28 $eq$libresoc.v:121414$4540_Y - connect \$2 $eq$libresoc.v:121415$4541_Y - connect \$30 $or$libresoc.v:121416$4542_Y - connect \$32 $eq$libresoc.v:121417$4543_Y - connect \$34 $or$libresoc.v:121418$4544_Y - connect \$36 $eq$libresoc.v:121419$4545_Y - connect \$38 $and$libresoc.v:121420$4546_Y - connect \$40 $and$libresoc.v:121421$4547_Y - connect \$42 $eq$libresoc.v:121422$4548_Y - connect \$44 $and$libresoc.v:121423$4549_Y - connect \$46 $not$libresoc.v:121424$4550_Y - connect \$48 $and$libresoc.v:121425$4551_Y - connect \$4 $and$libresoc.v:121426$4552_Y - connect \$6 $and$libresoc.v:121427$4553_Y - connect \$8 $eq$libresoc.v:121428$4554_Y + connect \$10 $and$libresoc.v:121102$4515_Y + connect \$12 $not$libresoc.v:121103$4516_Y + connect \$14 $and$libresoc.v:121104$4517_Y + connect \$16 $eq$libresoc.v:121105$4518_Y + connect \$18 $eq$libresoc.v:121106$4519_Y + connect \$20 $or$libresoc.v:121107$4520_Y + connect \$22 $eq$libresoc.v:121108$4521_Y + connect \$24 $eq$libresoc.v:121109$4522_Y + connect \$26 $or$libresoc.v:121110$4523_Y + connect \$28 $eq$libresoc.v:121111$4524_Y + connect \$2 $eq$libresoc.v:121112$4525_Y + connect \$30 $or$libresoc.v:121113$4526_Y + connect \$32 $eq$libresoc.v:121114$4527_Y + connect \$34 $or$libresoc.v:121115$4528_Y + connect \$36 $eq$libresoc.v:121116$4529_Y + connect \$38 $and$libresoc.v:121117$4530_Y + connect \$40 $and$libresoc.v:121118$4531_Y + connect \$42 $eq$libresoc.v:121119$4532_Y + connect \$44 $and$libresoc.v:121120$4533_Y + connect \$46 $not$libresoc.v:121121$4534_Y + connect \$48 $and$libresoc.v:121122$4535_Y + connect \$4 $and$libresoc.v:121123$4536_Y + connect \$6 $and$libresoc.v:121124$4537_Y + connect \$8 $eq$libresoc.v:121125$4538_Y connect \ALU__is_signed \dec_ALU_sgn connect \ALU__is_32bit \dec_ALU_is_32b connect \ALU__output_carry \dec_ALU_cry_out @@ -189356,120 +188890,120 @@ module \dec_ALU connect \insn_in \dec_opcode_in connect \ALU__insn \dec_opcode_in end -attribute \src "libresoc.v:121558.1-122038.10" +attribute \src "libresoc.v:121255.1-121735.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" attribute \generator "nMigen" module \dec_BRANCH - attribute \src "libresoc.v:121988.3-122002.6" + attribute \src "libresoc.v:121685.3-121699.6" wire width 14 $0\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:122013.3-122025.6" + attribute \src "libresoc.v:121710.3-121722.6" wire width 7 $0\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:122003.3-122012.6" + attribute \src "libresoc.v:121700.3-121709.6" wire $0\BRANCH__lk[0:0] - attribute \src "libresoc.v:121559.7-121559.20" + attribute \src "libresoc.v:121256.7-121256.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121988.3-122002.6" + attribute \src "libresoc.v:121685.3-121699.6" wire width 14 $1\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:122013.3-122025.6" + attribute \src "libresoc.v:121710.3-121722.6" wire width 7 $1\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:122003.3-122012.6" + attribute \src "libresoc.v:121700.3-121709.6" wire $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:121920.18-121920.113" - wire $and$libresoc.v:121920$4559_Y - attribute \src "libresoc.v:121922.18-121922.110" - wire $and$libresoc.v:121922$4561_Y - attribute \src "libresoc.v:121935.18-121935.114" - wire $and$libresoc.v:121935$4574_Y - attribute \src "libresoc.v:121936.18-121936.116" - wire $and$libresoc.v:121936$4575_Y - attribute \src "libresoc.v:121938.18-121938.114" - wire $and$libresoc.v:121938$4577_Y - attribute \src "libresoc.v:121940.18-121940.110" - wire $and$libresoc.v:121940$4579_Y - attribute \src "libresoc.v:121941.17-121941.112" - wire $and$libresoc.v:121941$4580_Y - attribute \src "libresoc.v:121942.17-121942.114" - wire $and$libresoc.v:121942$4581_Y - attribute \src "libresoc.v:121923.18-121923.129" - wire $eq$libresoc.v:121923$4562_Y - attribute \src "libresoc.v:121924.18-121924.129" - wire $eq$libresoc.v:121924$4563_Y - attribute \src "libresoc.v:121926.18-121926.110" - wire $eq$libresoc.v:121926$4565_Y - attribute \src "libresoc.v:121927.18-121927.110" - wire $eq$libresoc.v:121927$4566_Y - attribute \src "libresoc.v:121929.18-121929.112" - wire $eq$libresoc.v:121929$4568_Y - attribute \src "libresoc.v:121930.17-121930.133" - wire $eq$libresoc.v:121930$4569_Y - attribute \src "libresoc.v:121932.18-121932.110" - wire $eq$libresoc.v:121932$4571_Y - attribute \src "libresoc.v:121934.18-121934.134" - wire $eq$libresoc.v:121934$4573_Y - attribute \src "libresoc.v:121937.18-121937.134" - wire $eq$libresoc.v:121937$4576_Y - attribute \src "libresoc.v:121943.17-121943.133" - wire $eq$libresoc.v:121943$4582_Y - attribute \src "libresoc.v:121921.18-121921.110" - wire $not$libresoc.v:121921$4560_Y - attribute \src "libresoc.v:121939.18-121939.110" - wire $not$libresoc.v:121939$4578_Y - attribute \src "libresoc.v:121925.18-121925.110" - wire $or$libresoc.v:121925$4564_Y - attribute \src "libresoc.v:121928.18-121928.110" - wire $or$libresoc.v:121928$4567_Y - attribute \src "libresoc.v:121931.18-121931.110" - wire $or$libresoc.v:121931$4570_Y - attribute \src "libresoc.v:121933.18-121933.110" - wire $or$libresoc.v:121933$4572_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "libresoc.v:121617.18-121617.113" + wire $and$libresoc.v:121617$4543_Y + attribute \src "libresoc.v:121619.18-121619.110" + wire $and$libresoc.v:121619$4545_Y + attribute \src "libresoc.v:121632.18-121632.114" + wire $and$libresoc.v:121632$4558_Y + attribute \src "libresoc.v:121633.18-121633.116" + wire $and$libresoc.v:121633$4559_Y + attribute \src "libresoc.v:121635.18-121635.114" + wire $and$libresoc.v:121635$4561_Y + attribute \src "libresoc.v:121637.18-121637.110" + wire $and$libresoc.v:121637$4563_Y + attribute \src "libresoc.v:121638.17-121638.112" + wire $and$libresoc.v:121638$4564_Y + attribute \src "libresoc.v:121639.17-121639.114" + wire $and$libresoc.v:121639$4565_Y + attribute \src "libresoc.v:121620.18-121620.129" + wire $eq$libresoc.v:121620$4546_Y + attribute \src "libresoc.v:121621.18-121621.129" + wire $eq$libresoc.v:121621$4547_Y + attribute \src "libresoc.v:121623.18-121623.110" + wire $eq$libresoc.v:121623$4549_Y + attribute \src "libresoc.v:121624.18-121624.110" + wire $eq$libresoc.v:121624$4550_Y + attribute \src "libresoc.v:121626.18-121626.112" + wire $eq$libresoc.v:121626$4552_Y + attribute \src "libresoc.v:121627.17-121627.133" + wire $eq$libresoc.v:121627$4553_Y + attribute \src "libresoc.v:121629.18-121629.110" + wire $eq$libresoc.v:121629$4555_Y + attribute \src "libresoc.v:121631.18-121631.134" + wire $eq$libresoc.v:121631$4557_Y + attribute \src "libresoc.v:121634.18-121634.134" + wire $eq$libresoc.v:121634$4560_Y + attribute \src "libresoc.v:121640.17-121640.133" + wire $eq$libresoc.v:121640$4566_Y + attribute \src "libresoc.v:121618.18-121618.110" + wire $not$libresoc.v:121618$4544_Y + attribute \src "libresoc.v:121636.18-121636.110" + wire $not$libresoc.v:121636$4562_Y + attribute \src "libresoc.v:121622.18-121622.110" + wire $or$libresoc.v:121622$4548_Y + attribute \src "libresoc.v:121625.18-121625.110" + wire $or$libresoc.v:121625$4551_Y + attribute \src "libresoc.v:121628.18-121628.110" + wire $or$libresoc.v:121628$4554_Y + attribute \src "libresoc.v:121630.18-121630.110" + wire $or$libresoc.v:121630$4556_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 3 \BRANCH__cia @@ -189733,9 +189267,9 @@ module \dec_BRANCH wire width 2 \dec_BRANCH_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -189752,13 +189286,13 @@ module \dec_BRANCH attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 \dec_bi_sel_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in @@ -189766,24 +189300,24 @@ module \dec_BRANCH attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:121559.7-121559.15" + attribute \src "libresoc.v:121256.7-121256.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 1 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121920$4559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:121617$4543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189791,10 +189325,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:121920$4559_Y + connect \Y $and$libresoc.v:121617$4543_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121922$4561 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:121619$4545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189802,10 +189336,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:121922$4561_Y + connect \Y $and$libresoc.v:121619$4545_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121935$4574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:121632$4558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189813,10 +189347,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:121935$4574_Y + connect \Y $and$libresoc.v:121632$4558_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121936$4575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:121633$4559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189824,10 +189358,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121936$4575_Y + connect \Y $and$libresoc.v:121633$4559_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121938$4577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:121635$4561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189835,10 +189369,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:121938$4577_Y + connect \Y $and$libresoc.v:121635$4561_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121940$4579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:121637$4563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189846,10 +189380,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:121940$4579_Y + connect \Y $and$libresoc.v:121637$4563_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121941$4580 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:121638$4564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189857,10 +189391,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:121941$4580_Y + connect \Y $and$libresoc.v:121638$4564_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121942$4581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:121639$4565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189868,10 +189402,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121942$4581_Y + connect \Y $and$libresoc.v:121639$4565_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:121923$4562 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" + cell $eq $eq$libresoc.v:121620$4546 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -189879,10 +189413,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:121923$4562_Y + connect \Y $eq$libresoc.v:121620$4546_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:121924$4563 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $eq $eq$libresoc.v:121621$4547 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -189890,10 +189424,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:121924$4563_Y + connect \Y $eq$libresoc.v:121621$4547_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121926$4565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:121623$4549 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189901,10 +189435,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:121926$4565_Y + connect \Y $eq$libresoc.v:121623$4549_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121927$4566 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:121624$4550 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189912,10 +189446,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:121927$4566_Y + connect \Y $eq$libresoc.v:121624$4550_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121929$4568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:121626$4552 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189923,10 +189457,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:121929$4568_Y + connect \Y $eq$libresoc.v:121626$4552_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:121930$4569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:121627$4553 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189934,10 +189468,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121930$4569_Y + connect \Y $eq$libresoc.v:121627$4553_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:121932$4571 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $eq $eq$libresoc.v:121629$4555 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189945,10 +189479,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:121932$4571_Y + connect \Y $eq$libresoc.v:121629$4555_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:121934$4573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:121631$4557 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189956,10 +189490,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121934$4573_Y + connect \Y $eq$libresoc.v:121631$4557_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:121937$4576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:121634$4560 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189967,10 +189501,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121937$4576_Y + connect \Y $eq$libresoc.v:121634$4560_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:121943$4582 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:121640$4566 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189978,26 +189512,26 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121943$4582_Y + connect \Y $eq$libresoc.v:121640$4566_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:121921$4560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:121618$4544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121921$4560_Y + connect \Y $not$libresoc.v:121618$4544_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:121939$4578 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:121636$4562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121939$4578_Y + connect \Y $not$libresoc.v:121636$4562_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:121925$4564 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $or $or$libresoc.v:121622$4548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190005,10 +189539,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:121925$4564_Y + connect \Y $or$libresoc.v:121622$4548_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:121928$4567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:121625$4551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190016,10 +189550,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:121928$4567_Y + connect \Y $or$libresoc.v:121625$4551_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:121931$4570 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:121628$4554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190027,10 +189561,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:121931$4570_Y + connect \Y $or$libresoc.v:121628$4554_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:121933$4572 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $or $or$libresoc.v:121630$4556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190038,10 +189572,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:121933$4572_Y + connect \Y $or$libresoc.v:121630$4556_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121944.13-121966.4" + attribute \src "libresoc.v:121641.13-121663.4" cell \dec$141 \dec connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS @@ -190066,7 +189600,7 @@ module \dec_BRANCH connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121967.16-121978.4" + attribute \src "libresoc.v:121664.16-121675.4" cell \dec_bi$144 \dec_bi connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS @@ -190080,37 +189614,37 @@ module \dec_BRANCH connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121979.16-121983.4" + attribute \src "libresoc.v:121676.16-121680.4" cell \dec_oe$143 \dec_oe connect \BRANCH_OE \dec_BRANCH_OE connect \BRANCH_internal_op \dec_BRANCH_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121984.16-121987.4" + attribute \src "libresoc.v:121681.16-121684.4" cell \dec_rc$142 \dec_rc connect \BRANCH_Rc \dec_BRANCH_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:121559.7-121559.20" - process $proc$libresoc.v:121559$4586 + attribute \src "libresoc.v:121256.7-121256.20" + process $proc$libresoc.v:121256$4570 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121988.3-122002.6" - process $proc$libresoc.v:121988$4583 + attribute \src "libresoc.v:121685.3-121699.6" + process $proc$libresoc.v:121685$4567 assign { } { } assign $0\BRANCH__fn_unit[13:0] $1\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:121989.5-121989.29" + attribute \src "libresoc.v:121686.5-121686.29" switch \initial - attribute \src "libresoc.v:121989.9-121989.17" + attribute \src "libresoc.v:121686.9-121686.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -190128,18 +189662,18 @@ module \dec_BRANCH sync always update \BRANCH__fn_unit $0\BRANCH__fn_unit[13:0] end - attribute \src "libresoc.v:122003.3-122012.6" - process $proc$libresoc.v:122003$4584 + attribute \src "libresoc.v:121700.3-121709.6" + process $proc$libresoc.v:121700$4568 assign { } { } assign { } { } assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:122004.5-122004.29" + attribute \src "libresoc.v:121701.5-121701.29" switch \initial - attribute \src "libresoc.v:122004.9-122004.17" + attribute \src "libresoc.v:121701.9-121701.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:870" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" switch \dec_BRANCH_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -190151,18 +189685,18 @@ module \dec_BRANCH sync always update \BRANCH__lk $0\BRANCH__lk[0:0] end - attribute \src "libresoc.v:122013.3-122025.6" - process $proc$libresoc.v:122013$4585 + attribute \src "libresoc.v:121710.3-121722.6" + process $proc$libresoc.v:121710$4569 assign { } { } assign { } { } assign $0\BRANCH__insn_type[6:0] $1\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:122014.5-122014.29" + attribute \src "libresoc.v:121711.5-121711.29" switch \initial - attribute \src "libresoc.v:122014.9-122014.17" + attribute \src "libresoc.v:121711.9-121711.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -190178,30 +189712,30 @@ module \dec_BRANCH sync always update \BRANCH__insn_type $0\BRANCH__insn_type[6:0] end - connect \$10 $and$libresoc.v:121920$4559_Y - connect \$12 $not$libresoc.v:121921$4560_Y - connect \$14 $and$libresoc.v:121922$4561_Y - connect \$16 $eq$libresoc.v:121923$4562_Y - connect \$18 $eq$libresoc.v:121924$4563_Y - connect \$20 $or$libresoc.v:121925$4564_Y - connect \$22 $eq$libresoc.v:121926$4565_Y - connect \$24 $eq$libresoc.v:121927$4566_Y - connect \$26 $or$libresoc.v:121928$4567_Y - connect \$28 $eq$libresoc.v:121929$4568_Y - connect \$2 $eq$libresoc.v:121930$4569_Y - connect \$30 $or$libresoc.v:121931$4570_Y - connect \$32 $eq$libresoc.v:121932$4571_Y - connect \$34 $or$libresoc.v:121933$4572_Y - connect \$36 $eq$libresoc.v:121934$4573_Y - connect \$38 $and$libresoc.v:121935$4574_Y - connect \$40 $and$libresoc.v:121936$4575_Y - connect \$42 $eq$libresoc.v:121937$4576_Y - connect \$44 $and$libresoc.v:121938$4577_Y - connect \$46 $not$libresoc.v:121939$4578_Y - connect \$48 $and$libresoc.v:121940$4579_Y - connect \$4 $and$libresoc.v:121941$4580_Y - connect \$6 $and$libresoc.v:121942$4581_Y - connect \$8 $eq$libresoc.v:121943$4582_Y + connect \$10 $and$libresoc.v:121617$4543_Y + connect \$12 $not$libresoc.v:121618$4544_Y + connect \$14 $and$libresoc.v:121619$4545_Y + connect \$16 $eq$libresoc.v:121620$4546_Y + connect \$18 $eq$libresoc.v:121621$4547_Y + connect \$20 $or$libresoc.v:121622$4548_Y + connect \$22 $eq$libresoc.v:121623$4549_Y + connect \$24 $eq$libresoc.v:121624$4550_Y + connect \$26 $or$libresoc.v:121625$4551_Y + connect \$28 $eq$libresoc.v:121626$4552_Y + connect \$2 $eq$libresoc.v:121627$4553_Y + connect \$30 $or$libresoc.v:121628$4554_Y + connect \$32 $eq$libresoc.v:121629$4555_Y + connect \$34 $or$libresoc.v:121630$4556_Y + connect \$36 $eq$libresoc.v:121631$4557_Y + connect \$38 $and$libresoc.v:121632$4558_Y + connect \$40 $and$libresoc.v:121633$4559_Y + connect \$42 $eq$libresoc.v:121634$4560_Y + connect \$44 $and$libresoc.v:121635$4561_Y + connect \$46 $not$libresoc.v:121636$4562_Y + connect \$48 $and$libresoc.v:121637$4563_Y + connect \$4 $and$libresoc.v:121638$4564_Y + connect \$6 $and$libresoc.v:121639$4565_Y + connect \$8 $eq$libresoc.v:121640$4566_Y connect \BRANCH__is_32bit \dec_BRANCH_is_32b connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_BRANCH_in2_sel @@ -190215,116 +189749,116 @@ module \dec_BRANCH connect \insn_in \dec_opcode_in connect \BRANCH__insn \dec_opcode_in end -attribute \src "libresoc.v:122042.1-122414.10" +attribute \src "libresoc.v:121739.1-122111.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR" attribute \generator "nMigen" module \dec_CR - attribute \src "libresoc.v:122391.3-122405.6" + attribute \src "libresoc.v:122088.3-122102.6" wire width 14 $0\CR__fn_unit[13:0] - attribute \src "libresoc.v:122378.3-122390.6" + attribute \src "libresoc.v:122075.3-122087.6" wire width 7 $0\CR__insn_type[6:0] - attribute \src "libresoc.v:122043.7-122043.20" + attribute \src "libresoc.v:121740.7-121740.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122391.3-122405.6" + attribute \src "libresoc.v:122088.3-122102.6" wire width 14 $1\CR__fn_unit[13:0] - attribute \src "libresoc.v:122378.3-122390.6" + attribute \src "libresoc.v:122075.3-122087.6" wire width 7 $1\CR__insn_type[6:0] - attribute \src "libresoc.v:122333.18-122333.113" - wire $and$libresoc.v:122333$4587_Y - attribute \src "libresoc.v:122335.18-122335.110" - wire $and$libresoc.v:122335$4589_Y - attribute \src "libresoc.v:122348.18-122348.114" - wire $and$libresoc.v:122348$4602_Y - attribute \src "libresoc.v:122349.18-122349.116" - wire $and$libresoc.v:122349$4603_Y - attribute \src "libresoc.v:122351.18-122351.114" - wire $and$libresoc.v:122351$4605_Y - attribute \src "libresoc.v:122353.18-122353.110" - wire $and$libresoc.v:122353$4607_Y - attribute \src "libresoc.v:122354.17-122354.112" - wire $and$libresoc.v:122354$4608_Y - attribute \src "libresoc.v:122355.17-122355.114" - wire $and$libresoc.v:122355$4609_Y - attribute \src "libresoc.v:122336.18-122336.125" - wire $eq$libresoc.v:122336$4590_Y - attribute \src "libresoc.v:122337.18-122337.125" - wire $eq$libresoc.v:122337$4591_Y - attribute \src "libresoc.v:122339.18-122339.110" - wire $eq$libresoc.v:122339$4593_Y - attribute \src "libresoc.v:122340.18-122340.110" - wire $eq$libresoc.v:122340$4594_Y - attribute \src "libresoc.v:122342.18-122342.112" - wire $eq$libresoc.v:122342$4596_Y - attribute \src "libresoc.v:122343.17-122343.129" - wire $eq$libresoc.v:122343$4597_Y - attribute \src "libresoc.v:122345.18-122345.110" - wire $eq$libresoc.v:122345$4599_Y - attribute \src "libresoc.v:122347.18-122347.130" - wire $eq$libresoc.v:122347$4601_Y - attribute \src "libresoc.v:122350.18-122350.130" - wire $eq$libresoc.v:122350$4604_Y - attribute \src "libresoc.v:122356.17-122356.129" - wire $eq$libresoc.v:122356$4610_Y - attribute \src "libresoc.v:122334.18-122334.110" - wire $not$libresoc.v:122334$4588_Y - attribute \src "libresoc.v:122352.18-122352.110" - wire $not$libresoc.v:122352$4606_Y - attribute \src "libresoc.v:122338.18-122338.110" - wire $or$libresoc.v:122338$4592_Y - attribute \src "libresoc.v:122341.18-122341.110" - wire $or$libresoc.v:122341$4595_Y - attribute \src "libresoc.v:122344.18-122344.110" - wire $or$libresoc.v:122344$4598_Y - attribute \src "libresoc.v:122346.18-122346.110" - wire $or$libresoc.v:122346$4600_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "libresoc.v:122030.18-122030.113" + wire $and$libresoc.v:122030$4571_Y + attribute \src "libresoc.v:122032.18-122032.110" + wire $and$libresoc.v:122032$4573_Y + attribute \src "libresoc.v:122045.18-122045.114" + wire $and$libresoc.v:122045$4586_Y + attribute \src "libresoc.v:122046.18-122046.116" + wire $and$libresoc.v:122046$4587_Y + attribute \src "libresoc.v:122048.18-122048.114" + wire $and$libresoc.v:122048$4589_Y + attribute \src "libresoc.v:122050.18-122050.110" + wire $and$libresoc.v:122050$4591_Y + attribute \src "libresoc.v:122051.17-122051.112" + wire $and$libresoc.v:122051$4592_Y + attribute \src "libresoc.v:122052.17-122052.114" + wire $and$libresoc.v:122052$4593_Y + attribute \src "libresoc.v:122033.18-122033.125" + wire $eq$libresoc.v:122033$4574_Y + attribute \src "libresoc.v:122034.18-122034.125" + wire $eq$libresoc.v:122034$4575_Y + attribute \src "libresoc.v:122036.18-122036.110" + wire $eq$libresoc.v:122036$4577_Y + attribute \src "libresoc.v:122037.18-122037.110" + wire $eq$libresoc.v:122037$4578_Y + attribute \src "libresoc.v:122039.18-122039.112" + wire $eq$libresoc.v:122039$4580_Y + attribute \src "libresoc.v:122040.17-122040.129" + wire $eq$libresoc.v:122040$4581_Y + attribute \src "libresoc.v:122042.18-122042.110" + wire $eq$libresoc.v:122042$4583_Y + attribute \src "libresoc.v:122044.18-122044.130" + wire $eq$libresoc.v:122044$4585_Y + attribute \src "libresoc.v:122047.18-122047.130" + wire $eq$libresoc.v:122047$4588_Y + attribute \src "libresoc.v:122053.17-122053.129" + wire $eq$libresoc.v:122053$4594_Y + attribute \src "libresoc.v:122031.18-122031.110" + wire $not$libresoc.v:122031$4572_Y + attribute \src "libresoc.v:122049.18-122049.110" + wire $not$libresoc.v:122049$4590_Y + attribute \src "libresoc.v:122035.18-122035.110" + wire $or$libresoc.v:122035$4576_Y + attribute \src "libresoc.v:122038.18-122038.110" + wire $or$libresoc.v:122038$4579_Y + attribute \src "libresoc.v:122041.18-122041.110" + wire $or$libresoc.v:122041$4582_Y + attribute \src "libresoc.v:122043.18-122043.110" + wire $or$libresoc.v:122043$4584_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -190543,7 +190077,7 @@ module \dec_CR attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in @@ -190551,24 +190085,24 @@ module \dec_CR attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:122043.7-122043.15" + attribute \src "libresoc.v:121740.7-121740.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 5 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122333$4587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:122030$4571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190576,10 +190110,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:122333$4587_Y + connect \Y $and$libresoc.v:122030$4571_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122335$4589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:122032$4573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190587,10 +190121,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:122335$4589_Y + connect \Y $and$libresoc.v:122032$4573_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122348$4602 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:122045$4586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190598,10 +190132,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:122348$4602_Y + connect \Y $and$libresoc.v:122045$4586_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122349$4603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:122046$4587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190609,10 +190143,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122349$4603_Y + connect \Y $and$libresoc.v:122046$4587_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122351$4605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:122048$4589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190620,10 +190154,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:122351$4605_Y + connect \Y $and$libresoc.v:122048$4589_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122353$4607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:122050$4591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190631,10 +190165,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:122353$4607_Y + connect \Y $and$libresoc.v:122050$4591_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122354$4608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:122051$4592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190642,10 +190176,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:122354$4608_Y + connect \Y $and$libresoc.v:122051$4592_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122355$4609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:122052$4593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190653,10 +190187,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122355$4609_Y + connect \Y $and$libresoc.v:122052$4593_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:122336$4590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" + cell $eq $eq$libresoc.v:122033$4574 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190664,10 +190198,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:122336$4590_Y + connect \Y $eq$libresoc.v:122033$4574_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:122337$4591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $eq $eq$libresoc.v:122034$4575 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190675,10 +190209,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:122337$4591_Y + connect \Y $eq$libresoc.v:122034$4575_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122339$4593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:122036$4577 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190686,10 +190220,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:122339$4593_Y + connect \Y $eq$libresoc.v:122036$4577_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122340$4594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:122037$4578 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190697,10 +190231,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:122340$4594_Y + connect \Y $eq$libresoc.v:122037$4578_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122342$4596 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:122039$4580 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190708,10 +190242,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:122342$4596_Y + connect \Y $eq$libresoc.v:122039$4580_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:122343$4597 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:122040$4581 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190719,10 +190253,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122343$4597_Y + connect \Y $eq$libresoc.v:122040$4581_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:122345$4599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $eq $eq$libresoc.v:122042$4583 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190730,10 +190264,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:122345$4599_Y + connect \Y $eq$libresoc.v:122042$4583_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:122347$4601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:122044$4585 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190741,10 +190275,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122347$4601_Y + connect \Y $eq$libresoc.v:122044$4585_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:122350$4604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:122047$4588 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190752,10 +190286,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122350$4604_Y + connect \Y $eq$libresoc.v:122047$4588_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:122356$4610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:122053$4594 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190763,26 +190297,26 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122356$4610_Y + connect \Y $eq$libresoc.v:122053$4594_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:122334$4588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:122031$4572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122334$4588_Y + connect \Y $not$libresoc.v:122031$4572_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:122352$4606 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:122049$4590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122352$4606_Y + connect \Y $not$libresoc.v:122049$4590_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:122338$4592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $or $or$libresoc.v:122035$4576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190790,10 +190324,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:122338$4592_Y + connect \Y $or$libresoc.v:122035$4576_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:122341$4595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:122038$4579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190801,10 +190335,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:122341$4595_Y + connect \Y $or$libresoc.v:122038$4579_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:122344$4598 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:122041$4582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190812,10 +190346,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:122344$4598_Y + connect \Y $or$libresoc.v:122041$4582_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:122346$4600 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $or $or$libresoc.v:122043$4584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190823,10 +190357,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:122346$4600_Y + connect \Y $or$libresoc.v:122043$4584_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:122357.13-122368.4" + attribute \src "libresoc.v:122054.13-122065.4" cell \dec$138 \dec connect \CR_OE \dec_CR_OE connect \CR_Rc \dec_CR_Rc @@ -190840,38 +190374,38 @@ module \dec_CR connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122369.16-122373.4" + attribute \src "libresoc.v:122066.16-122070.4" cell \dec_oe$140 \dec_oe connect \CR_OE \dec_CR_OE connect \CR_internal_op \dec_CR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122374.16-122377.4" + attribute \src "libresoc.v:122071.16-122074.4" cell \dec_rc$139 \dec_rc connect \CR_Rc \dec_CR_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:122043.7-122043.20" - process $proc$libresoc.v:122043$4613 + attribute \src "libresoc.v:121740.7-121740.20" + process $proc$libresoc.v:121740$4597 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122378.3-122390.6" - process $proc$libresoc.v:122378$4611 + attribute \src "libresoc.v:122075.3-122087.6" + process $proc$libresoc.v:122075$4595 assign { } { } assign { } { } assign $0\CR__insn_type[6:0] $1\CR__insn_type[6:0] - attribute \src "libresoc.v:122379.5-122379.29" + attribute \src "libresoc.v:122076.5-122076.29" switch \initial - attribute \src "libresoc.v:122379.9-122379.17" + attribute \src "libresoc.v:122076.9-122076.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -190887,17 +190421,17 @@ module \dec_CR sync always update \CR__insn_type $0\CR__insn_type[6:0] end - attribute \src "libresoc.v:122391.3-122405.6" - process $proc$libresoc.v:122391$4612 + attribute \src "libresoc.v:122088.3-122102.6" + process $proc$libresoc.v:122088$4596 assign { } { } assign $0\CR__fn_unit[13:0] $1\CR__fn_unit[13:0] - attribute \src "libresoc.v:122392.5-122392.29" + attribute \src "libresoc.v:122089.5-122089.29" switch \initial - attribute \src "libresoc.v:122392.9-122392.17" + attribute \src "libresoc.v:122089.9-122089.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -190915,30 +190449,30 @@ module \dec_CR sync always update \CR__fn_unit $0\CR__fn_unit[13:0] end - connect \$10 $and$libresoc.v:122333$4587_Y - connect \$12 $not$libresoc.v:122334$4588_Y - connect \$14 $and$libresoc.v:122335$4589_Y - connect \$16 $eq$libresoc.v:122336$4590_Y - connect \$18 $eq$libresoc.v:122337$4591_Y - connect \$20 $or$libresoc.v:122338$4592_Y - connect \$22 $eq$libresoc.v:122339$4593_Y - connect \$24 $eq$libresoc.v:122340$4594_Y - connect \$26 $or$libresoc.v:122341$4595_Y - connect \$28 $eq$libresoc.v:122342$4596_Y - connect \$2 $eq$libresoc.v:122343$4597_Y - connect \$30 $or$libresoc.v:122344$4598_Y - connect \$32 $eq$libresoc.v:122345$4599_Y - connect \$34 $or$libresoc.v:122346$4600_Y - connect \$36 $eq$libresoc.v:122347$4601_Y - connect \$38 $and$libresoc.v:122348$4602_Y - connect \$40 $and$libresoc.v:122349$4603_Y - connect \$42 $eq$libresoc.v:122350$4604_Y - connect \$44 $and$libresoc.v:122351$4605_Y - connect \$46 $not$libresoc.v:122352$4606_Y - connect \$48 $and$libresoc.v:122353$4607_Y - connect \$4 $and$libresoc.v:122354$4608_Y - connect \$6 $and$libresoc.v:122355$4609_Y - connect \$8 $eq$libresoc.v:122356$4610_Y + connect \$10 $and$libresoc.v:122030$4571_Y + connect \$12 $not$libresoc.v:122031$4572_Y + connect \$14 $and$libresoc.v:122032$4573_Y + connect \$16 $eq$libresoc.v:122033$4574_Y + connect \$18 $eq$libresoc.v:122034$4575_Y + connect \$20 $or$libresoc.v:122035$4576_Y + connect \$22 $eq$libresoc.v:122036$4577_Y + connect \$24 $eq$libresoc.v:122037$4578_Y + connect \$26 $or$libresoc.v:122038$4579_Y + connect \$28 $eq$libresoc.v:122039$4580_Y + connect \$2 $eq$libresoc.v:122040$4581_Y + connect \$30 $or$libresoc.v:122041$4582_Y + connect \$32 $eq$libresoc.v:122042$4583_Y + connect \$34 $or$libresoc.v:122043$4584_Y + connect \$36 $eq$libresoc.v:122044$4585_Y + connect \$38 $and$libresoc.v:122045$4586_Y + connect \$40 $and$libresoc.v:122046$4587_Y + connect \$42 $eq$libresoc.v:122047$4588_Y + connect \$44 $and$libresoc.v:122048$4589_Y + connect \$46 $not$libresoc.v:122049$4590_Y + connect \$48 $and$libresoc.v:122050$4591_Y + connect \$4 $and$libresoc.v:122051$4592_Y + connect \$6 $and$libresoc.v:122052$4593_Y + connect \$8 $eq$libresoc.v:122053$4594_Y connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_CR_SPR [4:0] \dec_CR_SPR [9:5] } @@ -190948,120 +190482,120 @@ module \dec_CR connect \insn_in \dec_opcode_in connect \CR__insn \dec_opcode_in end -attribute \src "libresoc.v:122418.1-123001.10" +attribute \src "libresoc.v:122115.1-122698.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV" attribute \generator "nMigen" module \dec_DIV - attribute \src "libresoc.v:122964.3-122978.6" + attribute \src "libresoc.v:122661.3-122675.6" wire width 14 $0\DIV__fn_unit[13:0] - attribute \src "libresoc.v:122951.3-122963.6" + attribute \src "libresoc.v:122648.3-122660.6" wire width 7 $0\DIV__insn_type[6:0] - attribute \src "libresoc.v:122936.3-122950.6" + attribute \src "libresoc.v:122633.3-122647.6" wire $0\DIV__write_cr0[0:0] - attribute \src "libresoc.v:122419.7-122419.20" + attribute \src "libresoc.v:122116.7-122116.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122964.3-122978.6" + attribute \src "libresoc.v:122661.3-122675.6" wire width 14 $1\DIV__fn_unit[13:0] - attribute \src "libresoc.v:122951.3-122963.6" + attribute \src "libresoc.v:122648.3-122660.6" wire width 7 $1\DIV__insn_type[6:0] - attribute \src "libresoc.v:122936.3-122950.6" + attribute \src "libresoc.v:122633.3-122647.6" wire $1\DIV__write_cr0[0:0] - attribute \src "libresoc.v:122852.18-122852.113" - wire $and$libresoc.v:122852$4614_Y - attribute \src "libresoc.v:122854.18-122854.110" - wire $and$libresoc.v:122854$4616_Y - attribute \src "libresoc.v:122867.18-122867.114" - wire $and$libresoc.v:122867$4629_Y - attribute \src "libresoc.v:122868.18-122868.116" - wire $and$libresoc.v:122868$4630_Y - attribute \src "libresoc.v:122870.18-122870.114" - wire $and$libresoc.v:122870$4632_Y - attribute \src "libresoc.v:122872.18-122872.110" - wire $and$libresoc.v:122872$4634_Y - attribute \src "libresoc.v:122873.17-122873.112" - wire $and$libresoc.v:122873$4635_Y - attribute \src "libresoc.v:122874.17-122874.114" - wire $and$libresoc.v:122874$4636_Y - attribute \src "libresoc.v:122855.18-122855.126" - wire $eq$libresoc.v:122855$4617_Y - attribute \src "libresoc.v:122856.18-122856.126" - wire $eq$libresoc.v:122856$4618_Y - attribute \src "libresoc.v:122858.18-122858.110" - wire $eq$libresoc.v:122858$4620_Y - attribute \src "libresoc.v:122859.18-122859.110" - wire $eq$libresoc.v:122859$4621_Y - attribute \src "libresoc.v:122861.18-122861.112" - wire $eq$libresoc.v:122861$4623_Y - attribute \src "libresoc.v:122862.17-122862.130" - wire $eq$libresoc.v:122862$4624_Y - attribute \src "libresoc.v:122864.18-122864.110" - wire $eq$libresoc.v:122864$4626_Y - attribute \src "libresoc.v:122866.18-122866.131" - wire $eq$libresoc.v:122866$4628_Y - attribute \src "libresoc.v:122869.18-122869.131" - wire $eq$libresoc.v:122869$4631_Y - attribute \src "libresoc.v:122875.17-122875.130" - wire $eq$libresoc.v:122875$4637_Y - attribute \src "libresoc.v:122853.18-122853.110" - wire $not$libresoc.v:122853$4615_Y - attribute \src "libresoc.v:122871.18-122871.110" - wire $not$libresoc.v:122871$4633_Y - attribute \src "libresoc.v:122857.18-122857.110" - wire $or$libresoc.v:122857$4619_Y - attribute \src "libresoc.v:122860.18-122860.110" - wire $or$libresoc.v:122860$4622_Y - attribute \src "libresoc.v:122863.18-122863.110" - wire $or$libresoc.v:122863$4625_Y - attribute \src "libresoc.v:122865.18-122865.110" - wire $or$libresoc.v:122865$4627_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "libresoc.v:122549.18-122549.113" + wire $and$libresoc.v:122549$4598_Y + attribute \src "libresoc.v:122551.18-122551.110" + wire $and$libresoc.v:122551$4600_Y + attribute \src "libresoc.v:122564.18-122564.114" + wire $and$libresoc.v:122564$4613_Y + attribute \src "libresoc.v:122565.18-122565.116" + wire $and$libresoc.v:122565$4614_Y + attribute \src "libresoc.v:122567.18-122567.114" + wire $and$libresoc.v:122567$4616_Y + attribute \src "libresoc.v:122569.18-122569.110" + wire $and$libresoc.v:122569$4618_Y + attribute \src "libresoc.v:122570.17-122570.112" + wire $and$libresoc.v:122570$4619_Y + attribute \src "libresoc.v:122571.17-122571.114" + wire $and$libresoc.v:122571$4620_Y + attribute \src "libresoc.v:122552.18-122552.126" + wire $eq$libresoc.v:122552$4601_Y + attribute \src "libresoc.v:122553.18-122553.126" + wire $eq$libresoc.v:122553$4602_Y + attribute \src "libresoc.v:122555.18-122555.110" + wire $eq$libresoc.v:122555$4604_Y + attribute \src "libresoc.v:122556.18-122556.110" + wire $eq$libresoc.v:122556$4605_Y + attribute \src "libresoc.v:122558.18-122558.112" + wire $eq$libresoc.v:122558$4607_Y + attribute \src "libresoc.v:122559.17-122559.130" + wire $eq$libresoc.v:122559$4608_Y + attribute \src "libresoc.v:122561.18-122561.110" + wire $eq$libresoc.v:122561$4610_Y + attribute \src "libresoc.v:122563.18-122563.131" + wire $eq$libresoc.v:122563$4612_Y + attribute \src "libresoc.v:122566.18-122566.131" + wire $eq$libresoc.v:122566$4615_Y + attribute \src "libresoc.v:122572.17-122572.130" + wire $eq$libresoc.v:122572$4621_Y + attribute \src "libresoc.v:122550.18-122550.110" + wire $not$libresoc.v:122550$4599_Y + attribute \src "libresoc.v:122568.18-122568.110" + wire $not$libresoc.v:122568$4617_Y + attribute \src "libresoc.v:122554.18-122554.110" + wire $or$libresoc.v:122554$4603_Y + attribute \src "libresoc.v:122557.18-122557.110" + wire $or$libresoc.v:122557$4606_Y + attribute \src "libresoc.v:122560.18-122560.110" + wire $or$libresoc.v:122560$4609_Y + attribute \src "libresoc.v:122562.18-122562.110" + wire $or$libresoc.v:122562$4611_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 19 \DIV__data_len @@ -191375,7 +190909,7 @@ module \dec_DIV wire \dec_DIV_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -191383,13 +190917,13 @@ module \dec_DIV attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire \dec_ai_sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -191406,48 +190940,48 @@ module \dec_DIV attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:122419.7-122419.15" + attribute \src "libresoc.v:122116.7-122116.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire input 2 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122852$4614 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:122549$4598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191455,10 +190989,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:122852$4614_Y + connect \Y $and$libresoc.v:122549$4598_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122854$4616 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:122551$4600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191466,10 +191000,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:122854$4616_Y + connect \Y $and$libresoc.v:122551$4600_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122867$4629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:122564$4613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191477,10 +191011,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:122867$4629_Y + connect \Y $and$libresoc.v:122564$4613_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122868$4630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:122565$4614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191488,10 +191022,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122868$4630_Y + connect \Y $and$libresoc.v:122565$4614_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122870$4632 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:122567$4616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191499,10 +191033,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:122870$4632_Y + connect \Y $and$libresoc.v:122567$4616_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122872$4634 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:122569$4618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191510,10 +191044,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:122872$4634_Y + connect \Y $and$libresoc.v:122569$4618_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122873$4635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:122570$4619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191521,10 +191055,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:122873$4635_Y + connect \Y $and$libresoc.v:122570$4619_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122874$4636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:122571$4620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191532,10 +191066,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122874$4636_Y + connect \Y $and$libresoc.v:122571$4620_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:122855$4617 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" + cell $eq $eq$libresoc.v:122552$4601 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191543,10 +191077,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:122855$4617_Y + connect \Y $eq$libresoc.v:122552$4601_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:122856$4618 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $eq $eq$libresoc.v:122553$4602 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191554,10 +191088,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:122856$4618_Y + connect \Y $eq$libresoc.v:122553$4602_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122858$4620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:122555$4604 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191565,10 +191099,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:122858$4620_Y + connect \Y $eq$libresoc.v:122555$4604_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122859$4621 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:122556$4605 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191576,10 +191110,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:122859$4621_Y + connect \Y $eq$libresoc.v:122556$4605_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122861$4623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:122558$4607 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191587,10 +191121,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:122861$4623_Y + connect \Y $eq$libresoc.v:122558$4607_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:122862$4624 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:122559$4608 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191598,10 +191132,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122862$4624_Y + connect \Y $eq$libresoc.v:122559$4608_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:122864$4626 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $eq $eq$libresoc.v:122561$4610 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191609,10 +191143,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:122864$4626_Y + connect \Y $eq$libresoc.v:122561$4610_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:122866$4628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:122563$4612 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191620,10 +191154,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122866$4628_Y + connect \Y $eq$libresoc.v:122563$4612_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:122869$4631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:122566$4615 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191631,10 +191165,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122869$4631_Y + connect \Y $eq$libresoc.v:122566$4615_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:122875$4637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:122572$4621 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191642,26 +191176,26 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122875$4637_Y + connect \Y $eq$libresoc.v:122572$4621_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:122853$4615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:122550$4599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122853$4615_Y + connect \Y $not$libresoc.v:122550$4599_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:122871$4633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:122568$4617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122871$4633_Y + connect \Y $not$libresoc.v:122568$4617_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:122857$4619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $or $or$libresoc.v:122554$4603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191669,10 +191203,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:122857$4619_Y + connect \Y $or$libresoc.v:122554$4603_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:122860$4622 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:122557$4606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191680,10 +191214,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:122860$4622_Y + connect \Y $or$libresoc.v:122557$4606_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:122863$4625 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:122560$4609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191691,10 +191225,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:122863$4625_Y + connect \Y $or$libresoc.v:122560$4609_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:122865$4627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $or $or$libresoc.v:122562$4611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191702,10 +191236,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:122865$4627_Y + connect \Y $or$libresoc.v:122562$4611_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:122876.13-122904.4" + attribute \src "libresoc.v:122573.13-122601.4" cell \dec$153 \dec connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS @@ -191736,7 +191270,7 @@ module \dec_DIV connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122905.16-122910.4" + attribute \src "libresoc.v:122602.16-122607.4" cell \dec_ai$156 \dec_ai connect \DIV_RA \dec_DIV_RA connect \immz_out \dec_ai_immz_out @@ -191744,7 +191278,7 @@ module \dec_DIV connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:122911.16-122922.4" + attribute \src "libresoc.v:122608.16-122619.4" cell \dec_bi$157 \dec_bi connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS @@ -191758,7 +191292,7 @@ module \dec_DIV connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122923.16-122929.4" + attribute \src "libresoc.v:122620.16-122626.4" cell \dec_oe$155 \dec_oe connect \DIV_OE \dec_DIV_OE connect \DIV_internal_op \dec_DIV_internal_op @@ -191767,33 +191301,33 @@ module \dec_DIV connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122930.16-122935.4" + attribute \src "libresoc.v:122627.16-122632.4" cell \dec_rc$154 \dec_rc connect \DIV_Rc \dec_DIV_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:122419.7-122419.20" - process $proc$libresoc.v:122419$4641 + attribute \src "libresoc.v:122116.7-122116.20" + process $proc$libresoc.v:122116$4625 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122936.3-122950.6" - process $proc$libresoc.v:122936$4638 + attribute \src "libresoc.v:122633.3-122647.6" + process $proc$libresoc.v:122633$4622 assign { } { } assign { } { } assign $0\DIV__write_cr0[0:0] $1\DIV__write_cr0[0:0] - attribute \src "libresoc.v:122937.5-122937.29" + attribute \src "libresoc.v:122634.5-122634.29" switch \initial - attribute \src "libresoc.v:122937.9-122937.17" + attribute \src "libresoc.v:122634.9-122634.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" switch \dec_DIV_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -191809,18 +191343,18 @@ module \dec_DIV sync always update \DIV__write_cr0 $0\DIV__write_cr0[0:0] end - attribute \src "libresoc.v:122951.3-122963.6" - process $proc$libresoc.v:122951$4639 + attribute \src "libresoc.v:122648.3-122660.6" + process $proc$libresoc.v:122648$4623 assign { } { } assign { } { } assign $0\DIV__insn_type[6:0] $1\DIV__insn_type[6:0] - attribute \src "libresoc.v:122952.5-122952.29" + attribute \src "libresoc.v:122649.5-122649.29" switch \initial - attribute \src "libresoc.v:122952.9-122952.17" + attribute \src "libresoc.v:122649.9-122649.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -191836,17 +191370,17 @@ module \dec_DIV sync always update \DIV__insn_type $0\DIV__insn_type[6:0] end - attribute \src "libresoc.v:122964.3-122978.6" - process $proc$libresoc.v:122964$4640 + attribute \src "libresoc.v:122661.3-122675.6" + process $proc$libresoc.v:122661$4624 assign { } { } assign $0\DIV__fn_unit[13:0] $1\DIV__fn_unit[13:0] - attribute \src "libresoc.v:122965.5-122965.29" + attribute \src "libresoc.v:122662.5-122662.29" switch \initial - attribute \src "libresoc.v:122965.9-122965.17" + attribute \src "libresoc.v:122662.9-122662.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -191864,30 +191398,30 @@ module \dec_DIV sync always update \DIV__fn_unit $0\DIV__fn_unit[13:0] end - connect \$10 $and$libresoc.v:122852$4614_Y - connect \$12 $not$libresoc.v:122853$4615_Y - connect \$14 $and$libresoc.v:122854$4616_Y - connect \$16 $eq$libresoc.v:122855$4617_Y - connect \$18 $eq$libresoc.v:122856$4618_Y - connect \$20 $or$libresoc.v:122857$4619_Y - connect \$22 $eq$libresoc.v:122858$4620_Y - connect \$24 $eq$libresoc.v:122859$4621_Y - connect \$26 $or$libresoc.v:122860$4622_Y - connect \$28 $eq$libresoc.v:122861$4623_Y - connect \$2 $eq$libresoc.v:122862$4624_Y - connect \$30 $or$libresoc.v:122863$4625_Y - connect \$32 $eq$libresoc.v:122864$4626_Y - connect \$34 $or$libresoc.v:122865$4627_Y - connect \$36 $eq$libresoc.v:122866$4628_Y - connect \$38 $and$libresoc.v:122867$4629_Y - connect \$40 $and$libresoc.v:122868$4630_Y - connect \$42 $eq$libresoc.v:122869$4631_Y - connect \$44 $and$libresoc.v:122870$4632_Y - connect \$46 $not$libresoc.v:122871$4633_Y - connect \$48 $and$libresoc.v:122872$4634_Y - connect \$4 $and$libresoc.v:122873$4635_Y - connect \$6 $and$libresoc.v:122874$4636_Y - connect \$8 $eq$libresoc.v:122875$4637_Y + connect \$10 $and$libresoc.v:122549$4598_Y + connect \$12 $not$libresoc.v:122550$4599_Y + connect \$14 $and$libresoc.v:122551$4600_Y + connect \$16 $eq$libresoc.v:122552$4601_Y + connect \$18 $eq$libresoc.v:122553$4602_Y + connect \$20 $or$libresoc.v:122554$4603_Y + connect \$22 $eq$libresoc.v:122555$4604_Y + connect \$24 $eq$libresoc.v:122556$4605_Y + connect \$26 $or$libresoc.v:122557$4606_Y + connect \$28 $eq$libresoc.v:122558$4607_Y + connect \$2 $eq$libresoc.v:122559$4608_Y + connect \$30 $or$libresoc.v:122560$4609_Y + connect \$32 $eq$libresoc.v:122561$4610_Y + connect \$34 $or$libresoc.v:122562$4611_Y + connect \$36 $eq$libresoc.v:122563$4612_Y + connect \$38 $and$libresoc.v:122564$4613_Y + connect \$40 $and$libresoc.v:122565$4614_Y + connect \$42 $eq$libresoc.v:122566$4615_Y + connect \$44 $and$libresoc.v:122567$4616_Y + connect \$46 $not$libresoc.v:122568$4617_Y + connect \$48 $and$libresoc.v:122569$4618_Y + connect \$4 $and$libresoc.v:122570$4619_Y + connect \$6 $and$libresoc.v:122571$4620_Y + connect \$8 $eq$libresoc.v:122572$4621_Y connect \DIV__is_signed \dec_DIV_sgn connect \DIV__is_32bit \dec_DIV_is_32b connect \DIV__output_carry \dec_DIV_cry_out @@ -191911,116 +191445,116 @@ module \dec_DIV connect \insn_in \dec_opcode_in connect \DIV__insn \dec_opcode_in end -attribute \src "libresoc.v:123005.1-123566.10" +attribute \src "libresoc.v:122702.1-123263.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" attribute \generator "nMigen" module \dec_LDST - attribute \src "libresoc.v:123530.3-123544.6" + attribute \src "libresoc.v:123227.3-123241.6" wire width 14 $0\LDST__fn_unit[13:0] - attribute \src "libresoc.v:123517.3-123529.6" + attribute \src "libresoc.v:123214.3-123226.6" wire width 7 $0\LDST__insn_type[6:0] - attribute \src "libresoc.v:123006.7-123006.20" + attribute \src "libresoc.v:122703.7-122703.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123530.3-123544.6" + attribute \src "libresoc.v:123227.3-123241.6" wire width 14 $1\LDST__fn_unit[13:0] - attribute \src "libresoc.v:123517.3-123529.6" + attribute \src "libresoc.v:123214.3-123226.6" wire width 7 $1\LDST__insn_type[6:0] - attribute \src "libresoc.v:123434.18-123434.113" - wire $and$libresoc.v:123434$4642_Y - attribute \src "libresoc.v:123436.18-123436.110" - wire $and$libresoc.v:123436$4644_Y - attribute \src "libresoc.v:123449.18-123449.114" - wire $and$libresoc.v:123449$4657_Y - attribute \src "libresoc.v:123450.18-123450.116" - wire $and$libresoc.v:123450$4658_Y - attribute \src "libresoc.v:123452.18-123452.114" - wire $and$libresoc.v:123452$4660_Y - attribute \src "libresoc.v:123454.18-123454.110" - wire $and$libresoc.v:123454$4662_Y - attribute \src "libresoc.v:123455.17-123455.112" - wire $and$libresoc.v:123455$4663_Y - attribute \src "libresoc.v:123456.17-123456.114" - wire $and$libresoc.v:123456$4664_Y - attribute \src "libresoc.v:123437.18-123437.127" - wire $eq$libresoc.v:123437$4645_Y - attribute \src "libresoc.v:123438.18-123438.127" - wire $eq$libresoc.v:123438$4646_Y - attribute \src "libresoc.v:123440.18-123440.110" - wire $eq$libresoc.v:123440$4648_Y - attribute \src "libresoc.v:123441.18-123441.110" - wire $eq$libresoc.v:123441$4649_Y - attribute \src "libresoc.v:123443.18-123443.112" - wire $eq$libresoc.v:123443$4651_Y - attribute \src "libresoc.v:123444.17-123444.131" - wire $eq$libresoc.v:123444$4652_Y - attribute \src "libresoc.v:123446.18-123446.110" - wire $eq$libresoc.v:123446$4654_Y - attribute \src "libresoc.v:123448.18-123448.132" - wire $eq$libresoc.v:123448$4656_Y - attribute \src "libresoc.v:123451.18-123451.132" - wire $eq$libresoc.v:123451$4659_Y - attribute \src "libresoc.v:123457.17-123457.131" - wire $eq$libresoc.v:123457$4665_Y - attribute \src "libresoc.v:123435.18-123435.110" - wire $not$libresoc.v:123435$4643_Y - attribute \src "libresoc.v:123453.18-123453.110" - wire $not$libresoc.v:123453$4661_Y - attribute \src "libresoc.v:123439.18-123439.110" - wire $or$libresoc.v:123439$4647_Y - attribute \src "libresoc.v:123442.18-123442.110" - wire $or$libresoc.v:123442$4650_Y - attribute \src "libresoc.v:123445.18-123445.110" - wire $or$libresoc.v:123445$4653_Y - attribute \src "libresoc.v:123447.18-123447.110" - wire $or$libresoc.v:123447$4655_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "libresoc.v:123131.18-123131.113" + wire $and$libresoc.v:123131$4626_Y + attribute \src "libresoc.v:123133.18-123133.110" + wire $and$libresoc.v:123133$4628_Y + attribute \src "libresoc.v:123146.18-123146.114" + wire $and$libresoc.v:123146$4641_Y + attribute \src "libresoc.v:123147.18-123147.116" + wire $and$libresoc.v:123147$4642_Y + attribute \src "libresoc.v:123149.18-123149.114" + wire $and$libresoc.v:123149$4644_Y + attribute \src "libresoc.v:123151.18-123151.110" + wire $and$libresoc.v:123151$4646_Y + attribute \src "libresoc.v:123152.17-123152.112" + wire $and$libresoc.v:123152$4647_Y + attribute \src "libresoc.v:123153.17-123153.114" + wire $and$libresoc.v:123153$4648_Y + attribute \src "libresoc.v:123134.18-123134.127" + wire $eq$libresoc.v:123134$4629_Y + attribute \src "libresoc.v:123135.18-123135.127" + wire $eq$libresoc.v:123135$4630_Y + attribute \src "libresoc.v:123137.18-123137.110" + wire $eq$libresoc.v:123137$4632_Y + attribute \src "libresoc.v:123138.18-123138.110" + wire $eq$libresoc.v:123138$4633_Y + attribute \src "libresoc.v:123140.18-123140.112" + wire $eq$libresoc.v:123140$4635_Y + attribute \src "libresoc.v:123141.17-123141.131" + wire $eq$libresoc.v:123141$4636_Y + attribute \src "libresoc.v:123143.18-123143.110" + wire $eq$libresoc.v:123143$4638_Y + attribute \src "libresoc.v:123145.18-123145.132" + wire $eq$libresoc.v:123145$4640_Y + attribute \src "libresoc.v:123148.18-123148.132" + wire $eq$libresoc.v:123148$4643_Y + attribute \src "libresoc.v:123154.17-123154.131" + wire $eq$libresoc.v:123154$4649_Y + attribute \src "libresoc.v:123132.18-123132.110" + wire $not$libresoc.v:123132$4627_Y + attribute \src "libresoc.v:123150.18-123150.110" + wire $not$libresoc.v:123150$4645_Y + attribute \src "libresoc.v:123136.18-123136.110" + wire $or$libresoc.v:123136$4631_Y + attribute \src "libresoc.v:123139.18-123139.110" + wire $or$libresoc.v:123139$4634_Y + attribute \src "libresoc.v:123142.18-123142.110" + wire $or$libresoc.v:123142$4637_Y + attribute \src "libresoc.v:123144.18-123144.110" + wire $or$libresoc.v:123144$4639_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 15 \LDST__byte_reverse @@ -192330,7 +191864,7 @@ module \dec_LDST attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -192338,13 +191872,13 @@ module \dec_LDST attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire \dec_ai_sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -192361,48 +191895,48 @@ module \dec_LDST attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:123006.7-123006.15" + attribute \src "libresoc.v:122703.7-122703.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 19 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire input 2 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:123434$4642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:123131$4626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192410,10 +191944,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:123434$4642_Y + connect \Y $and$libresoc.v:123131$4626_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:123436$4644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:123133$4628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192421,10 +191955,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:123436$4644_Y + connect \Y $and$libresoc.v:123133$4628_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:123449$4657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:123146$4641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192432,10 +191966,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:123449$4657_Y + connect \Y $and$libresoc.v:123146$4641_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:123450$4658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:123147$4642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192443,10 +191977,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123450$4658_Y + connect \Y $and$libresoc.v:123147$4642_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:123452$4660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:123149$4644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192454,10 +191988,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:123452$4660_Y + connect \Y $and$libresoc.v:123149$4644_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:123454$4662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:123151$4646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192465,10 +191999,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:123454$4662_Y + connect \Y $and$libresoc.v:123151$4646_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:123455$4663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:123152$4647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192476,10 +192010,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:123455$4663_Y + connect \Y $and$libresoc.v:123152$4647_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:123456$4664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:123153$4648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192487,10 +192021,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123456$4664_Y + connect \Y $and$libresoc.v:123153$4648_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:123437$4645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" + cell $eq $eq$libresoc.v:123134$4629 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192498,10 +192032,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:123437$4645_Y + connect \Y $eq$libresoc.v:123134$4629_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:123438$4646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $eq $eq$libresoc.v:123135$4630 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192509,10 +192043,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:123438$4646_Y + connect \Y $eq$libresoc.v:123135$4630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:123440$4648 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:123137$4632 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192520,10 +192054,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:123440$4648_Y + connect \Y $eq$libresoc.v:123137$4632_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:123441$4649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:123138$4633 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192531,10 +192065,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:123441$4649_Y + connect \Y $eq$libresoc.v:123138$4633_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:123443$4651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:123140$4635 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192542,10 +192076,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:123443$4651_Y + connect \Y $eq$libresoc.v:123140$4635_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:123444$4652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:123141$4636 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192553,10 +192087,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123444$4652_Y + connect \Y $eq$libresoc.v:123141$4636_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:123446$4654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $eq $eq$libresoc.v:123143$4638 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192564,10 +192098,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:123446$4654_Y + connect \Y $eq$libresoc.v:123143$4638_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:123448$4656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:123145$4640 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192575,10 +192109,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123448$4656_Y + connect \Y $eq$libresoc.v:123145$4640_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:123451$4659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:123148$4643 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192586,10 +192120,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123451$4659_Y + connect \Y $eq$libresoc.v:123148$4643_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:123457$4665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:123154$4649 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192597,26 +192131,26 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123457$4665_Y + connect \Y $eq$libresoc.v:123154$4649_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:123435$4643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:123132$4627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123435$4643_Y + connect \Y $not$libresoc.v:123132$4627_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:123453$4661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:123150$4645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123453$4661_Y + connect \Y $not$libresoc.v:123150$4645_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:123439$4647 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $or $or$libresoc.v:123136$4631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192624,10 +192158,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:123439$4647_Y + connect \Y $or$libresoc.v:123136$4631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:123442$4650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:123139$4634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192635,10 +192169,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:123442$4650_Y + connect \Y $or$libresoc.v:123139$4634_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:123445$4653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:123142$4637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192646,10 +192180,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:123445$4653_Y + connect \Y $or$libresoc.v:123142$4637_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:123447$4655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $or $or$libresoc.v:123144$4639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192657,10 +192191,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:123447$4655_Y + connect \Y $or$libresoc.v:123144$4639_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:123458.13-123485.4" + attribute \src "libresoc.v:123155.13-123182.4" cell \dec$166 \dec connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS @@ -192690,7 +192224,7 @@ module \dec_LDST connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123486.16-123491.4" + attribute \src "libresoc.v:123183.16-123188.4" cell \dec_ai$169 \dec_ai connect \LDST_RA \dec_LDST_RA connect \immz_out \dec_ai_immz_out @@ -192698,7 +192232,7 @@ module \dec_LDST connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:123492.16-123503.4" + attribute \src "libresoc.v:123189.16-123200.4" cell \dec_bi$170 \dec_bi connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS @@ -192712,7 +192246,7 @@ module \dec_LDST connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123504.16-123510.4" + attribute \src "libresoc.v:123201.16-123207.4" cell \dec_oe$168 \dec_oe connect \LDST_OE \dec_LDST_OE connect \LDST_internal_op \dec_LDST_internal_op @@ -192721,33 +192255,33 @@ module \dec_LDST connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123511.16-123516.4" + attribute \src "libresoc.v:123208.16-123213.4" cell \dec_rc$167 \dec_rc connect \LDST_Rc \dec_LDST_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:123006.7-123006.20" - process $proc$libresoc.v:123006$4668 + attribute \src "libresoc.v:122703.7-122703.20" + process $proc$libresoc.v:122703$4652 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123517.3-123529.6" - process $proc$libresoc.v:123517$4666 + attribute \src "libresoc.v:123214.3-123226.6" + process $proc$libresoc.v:123214$4650 assign { } { } assign { } { } assign $0\LDST__insn_type[6:0] $1\LDST__insn_type[6:0] - attribute \src "libresoc.v:123518.5-123518.29" + attribute \src "libresoc.v:123215.5-123215.29" switch \initial - attribute \src "libresoc.v:123518.9-123518.17" + attribute \src "libresoc.v:123215.9-123215.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -192763,17 +192297,17 @@ module \dec_LDST sync always update \LDST__insn_type $0\LDST__insn_type[6:0] end - attribute \src "libresoc.v:123530.3-123544.6" - process $proc$libresoc.v:123530$4667 + attribute \src "libresoc.v:123227.3-123241.6" + process $proc$libresoc.v:123227$4651 assign { } { } assign $0\LDST__fn_unit[13:0] $1\LDST__fn_unit[13:0] - attribute \src "libresoc.v:123531.5-123531.29" + attribute \src "libresoc.v:123228.5-123228.29" switch \initial - attribute \src "libresoc.v:123531.9-123531.17" + attribute \src "libresoc.v:123228.9-123228.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -192791,30 +192325,30 @@ module \dec_LDST sync always update \LDST__fn_unit $0\LDST__fn_unit[13:0] end - connect \$10 $and$libresoc.v:123434$4642_Y - connect \$12 $not$libresoc.v:123435$4643_Y - connect \$14 $and$libresoc.v:123436$4644_Y - connect \$16 $eq$libresoc.v:123437$4645_Y - connect \$18 $eq$libresoc.v:123438$4646_Y - connect \$20 $or$libresoc.v:123439$4647_Y - connect \$22 $eq$libresoc.v:123440$4648_Y - connect \$24 $eq$libresoc.v:123441$4649_Y - connect \$26 $or$libresoc.v:123442$4650_Y - connect \$28 $eq$libresoc.v:123443$4651_Y - connect \$2 $eq$libresoc.v:123444$4652_Y - connect \$30 $or$libresoc.v:123445$4653_Y - connect \$32 $eq$libresoc.v:123446$4654_Y - connect \$34 $or$libresoc.v:123447$4655_Y - connect \$36 $eq$libresoc.v:123448$4656_Y - connect \$38 $and$libresoc.v:123449$4657_Y - connect \$40 $and$libresoc.v:123450$4658_Y - connect \$42 $eq$libresoc.v:123451$4659_Y - connect \$44 $and$libresoc.v:123452$4660_Y - connect \$46 $not$libresoc.v:123453$4661_Y - connect \$48 $and$libresoc.v:123454$4662_Y - connect \$4 $and$libresoc.v:123455$4663_Y - connect \$6 $and$libresoc.v:123456$4664_Y - connect \$8 $eq$libresoc.v:123457$4665_Y + connect \$10 $and$libresoc.v:123131$4626_Y + connect \$12 $not$libresoc.v:123132$4627_Y + connect \$14 $and$libresoc.v:123133$4628_Y + connect \$16 $eq$libresoc.v:123134$4629_Y + connect \$18 $eq$libresoc.v:123135$4630_Y + connect \$20 $or$libresoc.v:123136$4631_Y + connect \$22 $eq$libresoc.v:123137$4632_Y + connect \$24 $eq$libresoc.v:123138$4633_Y + connect \$26 $or$libresoc.v:123139$4634_Y + connect \$28 $eq$libresoc.v:123140$4635_Y + connect \$2 $eq$libresoc.v:123141$4636_Y + connect \$30 $or$libresoc.v:123142$4637_Y + connect \$32 $eq$libresoc.v:123143$4638_Y + connect \$34 $or$libresoc.v:123144$4639_Y + connect \$36 $eq$libresoc.v:123145$4640_Y + connect \$38 $and$libresoc.v:123146$4641_Y + connect \$40 $and$libresoc.v:123147$4642_Y + connect \$42 $eq$libresoc.v:123148$4643_Y + connect \$44 $and$libresoc.v:123149$4644_Y + connect \$46 $not$libresoc.v:123150$4645_Y + connect \$48 $and$libresoc.v:123151$4646_Y + connect \$4 $and$libresoc.v:123152$4647_Y + connect \$6 $and$libresoc.v:123153$4648_Y + connect \$8 $eq$libresoc.v:123154$4649_Y connect \LDST__ldst_mode \dec_LDST_upd connect \LDST__sign_extend \dec_LDST_sgn_ext connect \LDST__byte_reverse \dec_LDST_br @@ -192837,120 +192371,120 @@ module \dec_LDST connect \insn_in \dec_opcode_in connect \LDST__insn \dec_opcode_in end -attribute \src "libresoc.v:123570.1-124153.10" +attribute \src "libresoc.v:123267.1-123850.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL" attribute \generator "nMigen" module \dec_LOGICAL - attribute \src "libresoc.v:124116.3-124130.6" + attribute \src "libresoc.v:123813.3-123827.6" wire width 14 $0\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:124103.3-124115.6" + attribute \src "libresoc.v:123800.3-123812.6" wire width 7 $0\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:124088.3-124102.6" + attribute \src "libresoc.v:123785.3-123799.6" wire $0\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:123571.7-123571.20" + attribute \src "libresoc.v:123268.7-123268.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124116.3-124130.6" + attribute \src "libresoc.v:123813.3-123827.6" wire width 14 $1\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:124103.3-124115.6" + attribute \src "libresoc.v:123800.3-123812.6" wire width 7 $1\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:124088.3-124102.6" + attribute \src "libresoc.v:123785.3-123799.6" wire $1\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:124004.18-124004.113" - wire $and$libresoc.v:124004$4669_Y - attribute \src "libresoc.v:124006.18-124006.110" - wire $and$libresoc.v:124006$4671_Y - attribute \src "libresoc.v:124019.18-124019.114" - wire $and$libresoc.v:124019$4684_Y - attribute \src "libresoc.v:124020.18-124020.116" - wire $and$libresoc.v:124020$4685_Y - attribute \src "libresoc.v:124022.18-124022.114" - wire $and$libresoc.v:124022$4687_Y - attribute \src "libresoc.v:124024.18-124024.110" - wire $and$libresoc.v:124024$4689_Y - attribute \src "libresoc.v:124025.17-124025.112" - wire $and$libresoc.v:124025$4690_Y - attribute \src "libresoc.v:124026.17-124026.114" - wire $and$libresoc.v:124026$4691_Y - attribute \src "libresoc.v:124007.18-124007.130" - wire $eq$libresoc.v:124007$4672_Y - attribute \src "libresoc.v:124008.18-124008.130" - wire $eq$libresoc.v:124008$4673_Y - attribute \src "libresoc.v:124010.18-124010.110" - wire $eq$libresoc.v:124010$4675_Y - attribute \src "libresoc.v:124011.18-124011.110" - wire $eq$libresoc.v:124011$4676_Y - attribute \src "libresoc.v:124013.18-124013.112" - wire $eq$libresoc.v:124013$4678_Y - attribute \src "libresoc.v:124014.17-124014.134" - wire $eq$libresoc.v:124014$4679_Y - attribute \src "libresoc.v:124016.18-124016.110" - wire $eq$libresoc.v:124016$4681_Y - attribute \src "libresoc.v:124018.18-124018.135" - wire $eq$libresoc.v:124018$4683_Y - attribute \src "libresoc.v:124021.18-124021.135" - wire $eq$libresoc.v:124021$4686_Y - attribute \src "libresoc.v:124027.17-124027.134" - wire $eq$libresoc.v:124027$4692_Y - attribute \src "libresoc.v:124005.18-124005.110" - wire $not$libresoc.v:124005$4670_Y - attribute \src "libresoc.v:124023.18-124023.110" - wire $not$libresoc.v:124023$4688_Y - attribute \src "libresoc.v:124009.18-124009.110" - wire $or$libresoc.v:124009$4674_Y - attribute \src "libresoc.v:124012.18-124012.110" - wire $or$libresoc.v:124012$4677_Y - attribute \src "libresoc.v:124015.18-124015.110" - wire $or$libresoc.v:124015$4680_Y - attribute \src "libresoc.v:124017.18-124017.110" - wire $or$libresoc.v:124017$4682_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "libresoc.v:123701.18-123701.113" + wire $and$libresoc.v:123701$4653_Y + attribute \src "libresoc.v:123703.18-123703.110" + wire $and$libresoc.v:123703$4655_Y + attribute \src "libresoc.v:123716.18-123716.114" + wire $and$libresoc.v:123716$4668_Y + attribute \src "libresoc.v:123717.18-123717.116" + wire $and$libresoc.v:123717$4669_Y + attribute \src "libresoc.v:123719.18-123719.114" + wire $and$libresoc.v:123719$4671_Y + attribute \src "libresoc.v:123721.18-123721.110" + wire $and$libresoc.v:123721$4673_Y + attribute \src "libresoc.v:123722.17-123722.112" + wire $and$libresoc.v:123722$4674_Y + attribute \src "libresoc.v:123723.17-123723.114" + wire $and$libresoc.v:123723$4675_Y + attribute \src "libresoc.v:123704.18-123704.130" + wire $eq$libresoc.v:123704$4656_Y + attribute \src "libresoc.v:123705.18-123705.130" + wire $eq$libresoc.v:123705$4657_Y + attribute \src "libresoc.v:123707.18-123707.110" + wire $eq$libresoc.v:123707$4659_Y + attribute \src "libresoc.v:123708.18-123708.110" + wire $eq$libresoc.v:123708$4660_Y + attribute \src "libresoc.v:123710.18-123710.112" + wire $eq$libresoc.v:123710$4662_Y + attribute \src "libresoc.v:123711.17-123711.134" + wire $eq$libresoc.v:123711$4663_Y + attribute \src "libresoc.v:123713.18-123713.110" + wire $eq$libresoc.v:123713$4665_Y + attribute \src "libresoc.v:123715.18-123715.135" + wire $eq$libresoc.v:123715$4667_Y + attribute \src "libresoc.v:123718.18-123718.135" + wire $eq$libresoc.v:123718$4670_Y + attribute \src "libresoc.v:123724.17-123724.134" + wire $eq$libresoc.v:123724$4676_Y + attribute \src "libresoc.v:123702.18-123702.110" + wire $not$libresoc.v:123702$4654_Y + attribute \src "libresoc.v:123720.18-123720.110" + wire $not$libresoc.v:123720$4672_Y + attribute \src "libresoc.v:123706.18-123706.110" + wire $or$libresoc.v:123706$4658_Y + attribute \src "libresoc.v:123709.18-123709.110" + wire $or$libresoc.v:123709$4661_Y + attribute \src "libresoc.v:123712.18-123712.110" + wire $or$libresoc.v:123712$4664_Y + attribute \src "libresoc.v:123714.18-123714.110" + wire $or$libresoc.v:123714$4666_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 19 \LOGICAL__data_len @@ -193264,7 +192798,7 @@ module \dec_LOGICAL wire \dec_LOGICAL_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -193272,13 +192806,13 @@ module \dec_LOGICAL attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire \dec_ai_sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -193295,48 +192829,48 @@ module \dec_LOGICAL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:123571.7-123571.15" + attribute \src "libresoc.v:123268.7-123268.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire input 2 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124004$4669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:123701$4653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193344,10 +192878,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:124004$4669_Y + connect \Y $and$libresoc.v:123701$4653_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124006$4671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:123703$4655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193355,10 +192889,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:124006$4671_Y + connect \Y $and$libresoc.v:123703$4655_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124019$4684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:123716$4668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193366,10 +192900,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:124019$4684_Y + connect \Y $and$libresoc.v:123716$4668_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124020$4685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:123717$4669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193377,10 +192911,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:124020$4685_Y + connect \Y $and$libresoc.v:123717$4669_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124022$4687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:123719$4671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193388,10 +192922,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:124022$4687_Y + connect \Y $and$libresoc.v:123719$4671_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124024$4689 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:123721$4673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193399,10 +192933,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:124024$4689_Y + connect \Y $and$libresoc.v:123721$4673_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124025$4690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:123722$4674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193410,10 +192944,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:124025$4690_Y + connect \Y $and$libresoc.v:123722$4674_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124026$4691 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:123723$4675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193421,10 +192955,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:124026$4691_Y + connect \Y $and$libresoc.v:123723$4675_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:124007$4672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" + cell $eq $eq$libresoc.v:123704$4656 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -193432,10 +192966,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:124007$4672_Y + connect \Y $eq$libresoc.v:123704$4656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:124008$4673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $eq $eq$libresoc.v:123705$4657 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -193443,10 +192977,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:124008$4673_Y + connect \Y $eq$libresoc.v:123705$4657_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:124010$4675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:123707$4659 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193454,10 +192988,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:124010$4675_Y + connect \Y $eq$libresoc.v:123707$4659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:124011$4676 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:123708$4660 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193465,10 +192999,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:124011$4676_Y + connect \Y $eq$libresoc.v:123708$4660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:124013$4678 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:123710$4662 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193476,10 +193010,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:124013$4678_Y + connect \Y $eq$libresoc.v:123710$4662_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:124014$4679 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:123711$4663 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193487,10 +193021,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:124014$4679_Y + connect \Y $eq$libresoc.v:123711$4663_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:124016$4681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $eq $eq$libresoc.v:123713$4665 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193498,10 +193032,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:124016$4681_Y + connect \Y $eq$libresoc.v:123713$4665_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:124018$4683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:123715$4667 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193509,10 +193043,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:124018$4683_Y + connect \Y $eq$libresoc.v:123715$4667_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:124021$4686 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:123718$4670 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193520,10 +193054,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:124021$4686_Y + connect \Y $eq$libresoc.v:123718$4670_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:124027$4692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:123724$4676 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193531,26 +193065,26 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:124027$4692_Y + connect \Y $eq$libresoc.v:123724$4676_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:124005$4670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:123702$4654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:124005$4670_Y + connect \Y $not$libresoc.v:123702$4654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:124023$4688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:123720$4672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:124023$4688_Y + connect \Y $not$libresoc.v:123720$4672_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:124009$4674 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $or $or$libresoc.v:123706$4658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193558,10 +193092,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:124009$4674_Y + connect \Y $or$libresoc.v:123706$4658_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:124012$4677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:123709$4661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193569,10 +193103,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:124012$4677_Y + connect \Y $or$libresoc.v:123709$4661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:124015$4680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:123712$4664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193580,10 +193114,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:124015$4680_Y + connect \Y $or$libresoc.v:123712$4664_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:124017$4682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $or $or$libresoc.v:123714$4666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193591,10 +193125,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:124017$4682_Y + connect \Y $or$libresoc.v:123714$4666_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:124028.13-124056.4" + attribute \src "libresoc.v:123725.13-123753.4" cell \dec$145 \dec connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS @@ -193625,7 +193159,7 @@ module \dec_LOGICAL connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124057.16-124062.4" + attribute \src "libresoc.v:123754.16-123759.4" cell \dec_ai$148 \dec_ai connect \LOGICAL_RA \dec_LOGICAL_RA connect \immz_out \dec_ai_immz_out @@ -193633,7 +193167,7 @@ module \dec_LOGICAL connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:124063.16-124074.4" + attribute \src "libresoc.v:123760.16-123771.4" cell \dec_bi$149 \dec_bi connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS @@ -193647,7 +193181,7 @@ module \dec_LOGICAL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124075.16-124081.4" + attribute \src "libresoc.v:123772.16-123778.4" cell \dec_oe$147 \dec_oe connect \LOGICAL_OE \dec_LOGICAL_OE connect \LOGICAL_internal_op \dec_LOGICAL_internal_op @@ -193656,33 +193190,33 @@ module \dec_LOGICAL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124082.16-124087.4" + attribute \src "libresoc.v:123779.16-123784.4" cell \dec_rc$146 \dec_rc connect \LOGICAL_Rc \dec_LOGICAL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:123571.7-123571.20" - process $proc$libresoc.v:123571$4696 + attribute \src "libresoc.v:123268.7-123268.20" + process $proc$libresoc.v:123268$4680 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124088.3-124102.6" - process $proc$libresoc.v:124088$4693 + attribute \src "libresoc.v:123785.3-123799.6" + process $proc$libresoc.v:123785$4677 assign { } { } assign { } { } assign $0\LOGICAL__write_cr0[0:0] $1\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:124089.5-124089.29" + attribute \src "libresoc.v:123786.5-123786.29" switch \initial - attribute \src "libresoc.v:124089.9-124089.17" + attribute \src "libresoc.v:123786.9-123786.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" switch \dec_LOGICAL_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -193698,18 +193232,18 @@ module \dec_LOGICAL sync always update \LOGICAL__write_cr0 $0\LOGICAL__write_cr0[0:0] end - attribute \src "libresoc.v:124103.3-124115.6" - process $proc$libresoc.v:124103$4694 + attribute \src "libresoc.v:123800.3-123812.6" + process $proc$libresoc.v:123800$4678 assign { } { } assign { } { } assign $0\LOGICAL__insn_type[6:0] $1\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:124104.5-124104.29" + attribute \src "libresoc.v:123801.5-123801.29" switch \initial - attribute \src "libresoc.v:124104.9-124104.17" + attribute \src "libresoc.v:123801.9-123801.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -193725,17 +193259,17 @@ module \dec_LOGICAL sync always update \LOGICAL__insn_type $0\LOGICAL__insn_type[6:0] end - attribute \src "libresoc.v:124116.3-124130.6" - process $proc$libresoc.v:124116$4695 + attribute \src "libresoc.v:123813.3-123827.6" + process $proc$libresoc.v:123813$4679 assign { } { } assign $0\LOGICAL__fn_unit[13:0] $1\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:124117.5-124117.29" + attribute \src "libresoc.v:123814.5-123814.29" switch \initial - attribute \src "libresoc.v:124117.9-124117.17" + attribute \src "libresoc.v:123814.9-123814.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -193753,30 +193287,30 @@ module \dec_LOGICAL sync always update \LOGICAL__fn_unit $0\LOGICAL__fn_unit[13:0] end - connect \$10 $and$libresoc.v:124004$4669_Y - connect \$12 $not$libresoc.v:124005$4670_Y - connect \$14 $and$libresoc.v:124006$4671_Y - connect \$16 $eq$libresoc.v:124007$4672_Y - connect \$18 $eq$libresoc.v:124008$4673_Y - connect \$20 $or$libresoc.v:124009$4674_Y - connect \$22 $eq$libresoc.v:124010$4675_Y - connect \$24 $eq$libresoc.v:124011$4676_Y - connect \$26 $or$libresoc.v:124012$4677_Y - connect \$28 $eq$libresoc.v:124013$4678_Y - connect \$2 $eq$libresoc.v:124014$4679_Y - connect \$30 $or$libresoc.v:124015$4680_Y - connect \$32 $eq$libresoc.v:124016$4681_Y - connect \$34 $or$libresoc.v:124017$4682_Y - connect \$36 $eq$libresoc.v:124018$4683_Y - connect \$38 $and$libresoc.v:124019$4684_Y - connect \$40 $and$libresoc.v:124020$4685_Y - connect \$42 $eq$libresoc.v:124021$4686_Y - connect \$44 $and$libresoc.v:124022$4687_Y - connect \$46 $not$libresoc.v:124023$4688_Y - connect \$48 $and$libresoc.v:124024$4689_Y - connect \$4 $and$libresoc.v:124025$4690_Y - connect \$6 $and$libresoc.v:124026$4691_Y - connect \$8 $eq$libresoc.v:124027$4692_Y + connect \$10 $and$libresoc.v:123701$4653_Y + connect \$12 $not$libresoc.v:123702$4654_Y + connect \$14 $and$libresoc.v:123703$4655_Y + connect \$16 $eq$libresoc.v:123704$4656_Y + connect \$18 $eq$libresoc.v:123705$4657_Y + connect \$20 $or$libresoc.v:123706$4658_Y + connect \$22 $eq$libresoc.v:123707$4659_Y + connect \$24 $eq$libresoc.v:123708$4660_Y + connect \$26 $or$libresoc.v:123709$4661_Y + connect \$28 $eq$libresoc.v:123710$4662_Y + connect \$2 $eq$libresoc.v:123711$4663_Y + connect \$30 $or$libresoc.v:123712$4664_Y + connect \$32 $eq$libresoc.v:123713$4665_Y + connect \$34 $or$libresoc.v:123714$4666_Y + connect \$36 $eq$libresoc.v:123715$4667_Y + connect \$38 $and$libresoc.v:123716$4668_Y + connect \$40 $and$libresoc.v:123717$4669_Y + connect \$42 $eq$libresoc.v:123718$4670_Y + connect \$44 $and$libresoc.v:123719$4671_Y + connect \$46 $not$libresoc.v:123720$4672_Y + connect \$48 $and$libresoc.v:123721$4673_Y + connect \$4 $and$libresoc.v:123722$4674_Y + connect \$6 $and$libresoc.v:123723$4675_Y + connect \$8 $eq$libresoc.v:123724$4676_Y connect \LOGICAL__is_signed \dec_LOGICAL_sgn connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b connect \LOGICAL__output_carry \dec_LOGICAL_cry_out @@ -193800,120 +193334,120 @@ module \dec_LOGICAL connect \insn_in \dec_opcode_in connect \LOGICAL__insn \dec_opcode_in end -attribute \src "libresoc.v:124157.1-124659.10" +attribute \src "libresoc.v:123854.1-124356.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL" attribute \generator "nMigen" module \dec_MUL - attribute \src "libresoc.v:124630.3-124644.6" + attribute \src "libresoc.v:124327.3-124341.6" wire width 14 $0\MUL__fn_unit[13:0] - attribute \src "libresoc.v:124617.3-124629.6" + attribute \src "libresoc.v:124314.3-124326.6" wire width 7 $0\MUL__insn_type[6:0] - attribute \src "libresoc.v:124602.3-124616.6" + attribute \src "libresoc.v:124299.3-124313.6" wire $0\MUL__write_cr0[0:0] - attribute \src "libresoc.v:124158.7-124158.20" + attribute \src "libresoc.v:123855.7-123855.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124630.3-124644.6" + attribute \src "libresoc.v:124327.3-124341.6" wire width 14 $1\MUL__fn_unit[13:0] - attribute \src "libresoc.v:124617.3-124629.6" + attribute \src "libresoc.v:124314.3-124326.6" wire width 7 $1\MUL__insn_type[6:0] - attribute \src "libresoc.v:124602.3-124616.6" + attribute \src "libresoc.v:124299.3-124313.6" wire $1\MUL__write_cr0[0:0] - attribute \src "libresoc.v:124531.18-124531.113" - wire $and$libresoc.v:124531$4697_Y - attribute \src "libresoc.v:124533.18-124533.110" - wire $and$libresoc.v:124533$4699_Y - attribute \src "libresoc.v:124546.18-124546.114" - wire $and$libresoc.v:124546$4712_Y - attribute \src "libresoc.v:124547.18-124547.116" - wire $and$libresoc.v:124547$4713_Y - attribute \src "libresoc.v:124549.18-124549.114" - wire $and$libresoc.v:124549$4715_Y - attribute \src "libresoc.v:124551.18-124551.110" - wire $and$libresoc.v:124551$4717_Y - attribute \src "libresoc.v:124552.17-124552.112" - wire $and$libresoc.v:124552$4718_Y - attribute \src "libresoc.v:124553.17-124553.114" - wire $and$libresoc.v:124553$4719_Y - attribute \src "libresoc.v:124534.18-124534.126" - wire $eq$libresoc.v:124534$4700_Y - attribute \src "libresoc.v:124535.18-124535.126" - wire $eq$libresoc.v:124535$4701_Y - attribute \src "libresoc.v:124537.18-124537.110" - wire $eq$libresoc.v:124537$4703_Y - attribute \src "libresoc.v:124538.18-124538.110" - wire $eq$libresoc.v:124538$4704_Y - attribute \src "libresoc.v:124540.18-124540.112" - wire $eq$libresoc.v:124540$4706_Y - attribute \src "libresoc.v:124541.17-124541.130" - wire $eq$libresoc.v:124541$4707_Y - attribute \src "libresoc.v:124543.18-124543.110" - wire $eq$libresoc.v:124543$4709_Y - attribute \src "libresoc.v:124545.18-124545.131" - wire $eq$libresoc.v:124545$4711_Y - attribute \src "libresoc.v:124548.18-124548.131" - wire $eq$libresoc.v:124548$4714_Y - attribute \src "libresoc.v:124554.17-124554.130" - wire $eq$libresoc.v:124554$4720_Y - attribute \src "libresoc.v:124532.18-124532.110" - wire $not$libresoc.v:124532$4698_Y - attribute \src "libresoc.v:124550.18-124550.110" - wire $not$libresoc.v:124550$4716_Y - attribute \src "libresoc.v:124536.18-124536.110" - wire $or$libresoc.v:124536$4702_Y - attribute \src "libresoc.v:124539.18-124539.110" - wire $or$libresoc.v:124539$4705_Y - attribute \src "libresoc.v:124542.18-124542.110" - wire $or$libresoc.v:124542$4708_Y - attribute \src "libresoc.v:124544.18-124544.110" - wire $or$libresoc.v:124544$4710_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "libresoc.v:124228.18-124228.113" + wire $and$libresoc.v:124228$4681_Y + attribute \src "libresoc.v:124230.18-124230.110" + wire $and$libresoc.v:124230$4683_Y + attribute \src "libresoc.v:124243.18-124243.114" + wire $and$libresoc.v:124243$4696_Y + attribute \src "libresoc.v:124244.18-124244.116" + wire $and$libresoc.v:124244$4697_Y + attribute \src "libresoc.v:124246.18-124246.114" + wire $and$libresoc.v:124246$4699_Y + attribute \src "libresoc.v:124248.18-124248.110" + wire $and$libresoc.v:124248$4701_Y + attribute \src "libresoc.v:124249.17-124249.112" + wire $and$libresoc.v:124249$4702_Y + attribute \src "libresoc.v:124250.17-124250.114" + wire $and$libresoc.v:124250$4703_Y + attribute \src "libresoc.v:124231.18-124231.126" + wire $eq$libresoc.v:124231$4684_Y + attribute \src "libresoc.v:124232.18-124232.126" + wire $eq$libresoc.v:124232$4685_Y + attribute \src "libresoc.v:124234.18-124234.110" + wire $eq$libresoc.v:124234$4687_Y + attribute \src "libresoc.v:124235.18-124235.110" + wire $eq$libresoc.v:124235$4688_Y + attribute \src "libresoc.v:124237.18-124237.112" + wire $eq$libresoc.v:124237$4690_Y + attribute \src "libresoc.v:124238.17-124238.130" + wire $eq$libresoc.v:124238$4691_Y + attribute \src "libresoc.v:124240.18-124240.110" + wire $eq$libresoc.v:124240$4693_Y + attribute \src "libresoc.v:124242.18-124242.131" + wire $eq$libresoc.v:124242$4695_Y + attribute \src "libresoc.v:124245.18-124245.131" + wire $eq$libresoc.v:124245$4698_Y + attribute \src "libresoc.v:124251.17-124251.130" + wire $eq$libresoc.v:124251$4704_Y + attribute \src "libresoc.v:124229.18-124229.110" + wire $not$libresoc.v:124229$4682_Y + attribute \src "libresoc.v:124247.18-124247.110" + wire $not$libresoc.v:124247$4700_Y + attribute \src "libresoc.v:124233.18-124233.110" + wire $or$libresoc.v:124233$4686_Y + attribute \src "libresoc.v:124236.18-124236.110" + wire $or$libresoc.v:124236$4689_Y + attribute \src "libresoc.v:124239.18-124239.110" + wire $or$libresoc.v:124239$4692_Y + attribute \src "libresoc.v:124241.18-124241.110" + wire $or$libresoc.v:124241$4694_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -194181,9 +193715,9 @@ module \dec_MUL wire \dec_MUL_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -194200,46 +193734,46 @@ module \dec_MUL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:124158.7-124158.15" + attribute \src "libresoc.v:123855.7-123855.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 14 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124531$4697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:124228$4681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194247,10 +193781,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:124531$4697_Y + connect \Y $and$libresoc.v:124228$4681_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124533$4699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:124230$4683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194258,10 +193792,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:124533$4699_Y + connect \Y $and$libresoc.v:124230$4683_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124546$4712 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:124243$4696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194269,10 +193803,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:124546$4712_Y + connect \Y $and$libresoc.v:124243$4696_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124547$4713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:124244$4697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194280,10 +193814,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:124547$4713_Y + connect \Y $and$libresoc.v:124244$4697_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124549$4715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:124246$4699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194291,10 +193825,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:124549$4715_Y + connect \Y $and$libresoc.v:124246$4699_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124551$4717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:124248$4701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194302,10 +193836,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:124551$4717_Y + connect \Y $and$libresoc.v:124248$4701_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124552$4718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:124249$4702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194313,10 +193847,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:124552$4718_Y + connect \Y $and$libresoc.v:124249$4702_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124553$4719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:124250$4703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194324,10 +193858,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:124553$4719_Y + connect \Y $and$libresoc.v:124250$4703_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:124534$4700 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" + cell $eq $eq$libresoc.v:124231$4684 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -194335,10 +193869,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:124534$4700_Y + connect \Y $eq$libresoc.v:124231$4684_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:124535$4701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $eq $eq$libresoc.v:124232$4685 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -194346,10 +193880,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:124535$4701_Y + connect \Y $eq$libresoc.v:124232$4685_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:124537$4703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:124234$4687 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -194357,10 +193891,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:124537$4703_Y + connect \Y $eq$libresoc.v:124234$4687_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:124538$4704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:124235$4688 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -194368,10 +193902,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:124538$4704_Y + connect \Y $eq$libresoc.v:124235$4688_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:124540$4706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:124237$4690 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -194379,10 +193913,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:124540$4706_Y + connect \Y $eq$libresoc.v:124237$4690_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:124541$4707 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:124238$4691 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194390,10 +193924,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:124541$4707_Y + connect \Y $eq$libresoc.v:124238$4691_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:124543$4709 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $eq $eq$libresoc.v:124240$4693 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -194401,10 +193935,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:124543$4709_Y + connect \Y $eq$libresoc.v:124240$4693_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:124545$4711 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:124242$4695 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194412,10 +193946,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:124545$4711_Y + connect \Y $eq$libresoc.v:124242$4695_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:124548$4714 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:124245$4698 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194423,10 +193957,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:124548$4714_Y + connect \Y $eq$libresoc.v:124245$4698_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:124554$4720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:124251$4704 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194434,26 +193968,26 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:124554$4720_Y + connect \Y $eq$libresoc.v:124251$4704_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:124532$4698 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:124229$4682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:124532$4698_Y + connect \Y $not$libresoc.v:124229$4682_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:124550$4716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:124247$4700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:124550$4716_Y + connect \Y $not$libresoc.v:124247$4700_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:124536$4702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $or $or$libresoc.v:124233$4686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194461,10 +193995,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:124536$4702_Y + connect \Y $or$libresoc.v:124233$4686_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:124539$4705 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:124236$4689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194472,10 +194006,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:124539$4705_Y + connect \Y $or$libresoc.v:124236$4689_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:124542$4708 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:124239$4692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194483,10 +194017,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:124542$4708_Y + connect \Y $or$libresoc.v:124239$4692_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:124544$4710 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $or $or$libresoc.v:124241$4694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194494,10 +194028,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:124544$4710_Y + connect \Y $or$libresoc.v:124241$4694_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:124555.13-124576.4" + attribute \src "libresoc.v:124252.13-124273.4" cell \dec$158 \dec connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS @@ -194521,7 +194055,7 @@ module \dec_MUL connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124577.16-124588.4" + attribute \src "libresoc.v:124274.16-124285.4" cell \dec_bi$161 \dec_bi connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS @@ -194535,7 +194069,7 @@ module \dec_MUL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124589.16-124595.4" + attribute \src "libresoc.v:124286.16-124292.4" cell \dec_oe$160 \dec_oe connect \MUL_OE \dec_MUL_OE connect \MUL_internal_op \dec_MUL_internal_op @@ -194544,33 +194078,33 @@ module \dec_MUL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124596.16-124601.4" + attribute \src "libresoc.v:124293.16-124298.4" cell \dec_rc$159 \dec_rc connect \MUL_Rc \dec_MUL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:124158.7-124158.20" - process $proc$libresoc.v:124158$4724 + attribute \src "libresoc.v:123855.7-123855.20" + process $proc$libresoc.v:123855$4708 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124602.3-124616.6" - process $proc$libresoc.v:124602$4721 + attribute \src "libresoc.v:124299.3-124313.6" + process $proc$libresoc.v:124299$4705 assign { } { } assign { } { } assign $0\MUL__write_cr0[0:0] $1\MUL__write_cr0[0:0] - attribute \src "libresoc.v:124603.5-124603.29" + attribute \src "libresoc.v:124300.5-124300.29" switch \initial - attribute \src "libresoc.v:124603.9-124603.17" + attribute \src "libresoc.v:124300.9-124300.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" switch \dec_MUL_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -194586,18 +194120,18 @@ module \dec_MUL sync always update \MUL__write_cr0 $0\MUL__write_cr0[0:0] end - attribute \src "libresoc.v:124617.3-124629.6" - process $proc$libresoc.v:124617$4722 + attribute \src "libresoc.v:124314.3-124326.6" + process $proc$libresoc.v:124314$4706 assign { } { } assign { } { } assign $0\MUL__insn_type[6:0] $1\MUL__insn_type[6:0] - attribute \src "libresoc.v:124618.5-124618.29" + attribute \src "libresoc.v:124315.5-124315.29" switch \initial - attribute \src "libresoc.v:124618.9-124618.17" + attribute \src "libresoc.v:124315.9-124315.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -194613,17 +194147,17 @@ module \dec_MUL sync always update \MUL__insn_type $0\MUL__insn_type[6:0] end - attribute \src "libresoc.v:124630.3-124644.6" - process $proc$libresoc.v:124630$4723 + attribute \src "libresoc.v:124327.3-124341.6" + process $proc$libresoc.v:124327$4707 assign { } { } assign $0\MUL__fn_unit[13:0] $1\MUL__fn_unit[13:0] - attribute \src "libresoc.v:124631.5-124631.29" + attribute \src "libresoc.v:124328.5-124328.29" switch \initial - attribute \src "libresoc.v:124631.9-124631.17" + attribute \src "libresoc.v:124328.9-124328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -194641,30 +194175,30 @@ module \dec_MUL sync always update \MUL__fn_unit $0\MUL__fn_unit[13:0] end - connect \$10 $and$libresoc.v:124531$4697_Y - connect \$12 $not$libresoc.v:124532$4698_Y - connect \$14 $and$libresoc.v:124533$4699_Y - connect \$16 $eq$libresoc.v:124534$4700_Y - connect \$18 $eq$libresoc.v:124535$4701_Y - connect \$20 $or$libresoc.v:124536$4702_Y - connect \$22 $eq$libresoc.v:124537$4703_Y - connect \$24 $eq$libresoc.v:124538$4704_Y - connect \$26 $or$libresoc.v:124539$4705_Y - connect \$28 $eq$libresoc.v:124540$4706_Y - connect \$2 $eq$libresoc.v:124541$4707_Y - connect \$30 $or$libresoc.v:124542$4708_Y - connect \$32 $eq$libresoc.v:124543$4709_Y - connect \$34 $or$libresoc.v:124544$4710_Y - connect \$36 $eq$libresoc.v:124545$4711_Y - connect \$38 $and$libresoc.v:124546$4712_Y - connect \$40 $and$libresoc.v:124547$4713_Y - connect \$42 $eq$libresoc.v:124548$4714_Y - connect \$44 $and$libresoc.v:124549$4715_Y - connect \$46 $not$libresoc.v:124550$4716_Y - connect \$48 $and$libresoc.v:124551$4717_Y - connect \$4 $and$libresoc.v:124552$4718_Y - connect \$6 $and$libresoc.v:124553$4719_Y - connect \$8 $eq$libresoc.v:124554$4720_Y + connect \$10 $and$libresoc.v:124228$4681_Y + connect \$12 $not$libresoc.v:124229$4682_Y + connect \$14 $and$libresoc.v:124230$4683_Y + connect \$16 $eq$libresoc.v:124231$4684_Y + connect \$18 $eq$libresoc.v:124232$4685_Y + connect \$20 $or$libresoc.v:124233$4686_Y + connect \$22 $eq$libresoc.v:124234$4687_Y + connect \$24 $eq$libresoc.v:124235$4688_Y + connect \$26 $or$libresoc.v:124236$4689_Y + connect \$28 $eq$libresoc.v:124237$4690_Y + connect \$2 $eq$libresoc.v:124238$4691_Y + connect \$30 $or$libresoc.v:124239$4692_Y + connect \$32 $eq$libresoc.v:124240$4693_Y + connect \$34 $or$libresoc.v:124241$4694_Y + connect \$36 $eq$libresoc.v:124242$4695_Y + connect \$38 $and$libresoc.v:124243$4696_Y + connect \$40 $and$libresoc.v:124244$4697_Y + connect \$42 $eq$libresoc.v:124245$4698_Y + connect \$44 $and$libresoc.v:124246$4699_Y + connect \$46 $not$libresoc.v:124247$4700_Y + connect \$48 $and$libresoc.v:124248$4701_Y + connect \$4 $and$libresoc.v:124249$4702_Y + connect \$6 $and$libresoc.v:124250$4703_Y + connect \$8 $eq$libresoc.v:124251$4704_Y connect \MUL__is_signed \dec_MUL_sgn connect \MUL__is_32bit \dec_MUL_is_32b connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } @@ -194680,120 +194214,120 @@ module \dec_MUL connect \insn_in \dec_opcode_in connect \MUL__insn \dec_opcode_in end -attribute \src "libresoc.v:124663.1-125209.10" +attribute \src "libresoc.v:124360.1-124906.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" attribute \generator "nMigen" module \dec_SHIFT_ROT - attribute \src "libresoc.v:125175.3-125189.6" + attribute \src "libresoc.v:124872.3-124886.6" wire width 14 $0\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:125162.3-125174.6" + attribute \src "libresoc.v:124859.3-124871.6" wire width 7 $0\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:125147.3-125161.6" + attribute \src "libresoc.v:124844.3-124858.6" wire $0\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:124664.7-124664.20" + attribute \src "libresoc.v:124361.7-124361.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125175.3-125189.6" + attribute \src "libresoc.v:124872.3-124886.6" wire width 14 $1\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:125162.3-125174.6" + attribute \src "libresoc.v:124859.3-124871.6" wire width 7 $1\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:125147.3-125161.6" + attribute \src "libresoc.v:124844.3-124858.6" wire $1\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:125072.18-125072.113" - wire $and$libresoc.v:125072$4725_Y - attribute \src "libresoc.v:125074.18-125074.110" - wire $and$libresoc.v:125074$4727_Y - attribute \src "libresoc.v:125087.18-125087.114" - wire $and$libresoc.v:125087$4740_Y - attribute \src "libresoc.v:125088.18-125088.116" - wire $and$libresoc.v:125088$4741_Y - attribute \src "libresoc.v:125090.18-125090.114" - wire $and$libresoc.v:125090$4743_Y - attribute \src "libresoc.v:125092.18-125092.110" - wire $and$libresoc.v:125092$4745_Y - attribute \src "libresoc.v:125093.17-125093.112" - wire $and$libresoc.v:125093$4746_Y - attribute \src "libresoc.v:125094.17-125094.114" - wire $and$libresoc.v:125094$4747_Y - attribute \src "libresoc.v:125075.18-125075.132" - wire $eq$libresoc.v:125075$4728_Y - attribute \src "libresoc.v:125076.18-125076.132" - wire $eq$libresoc.v:125076$4729_Y - attribute \src "libresoc.v:125078.18-125078.110" - wire $eq$libresoc.v:125078$4731_Y - attribute \src "libresoc.v:125079.18-125079.110" - wire $eq$libresoc.v:125079$4732_Y - attribute \src "libresoc.v:125081.18-125081.112" - wire $eq$libresoc.v:125081$4734_Y - attribute \src "libresoc.v:125082.17-125082.136" - wire $eq$libresoc.v:125082$4735_Y - attribute \src "libresoc.v:125084.18-125084.110" - wire $eq$libresoc.v:125084$4737_Y - attribute \src "libresoc.v:125086.18-125086.137" - wire $eq$libresoc.v:125086$4739_Y - attribute \src "libresoc.v:125089.18-125089.137" - wire $eq$libresoc.v:125089$4742_Y - attribute \src "libresoc.v:125095.17-125095.136" - wire $eq$libresoc.v:125095$4748_Y - attribute \src "libresoc.v:125073.18-125073.110" - wire $not$libresoc.v:125073$4726_Y - attribute \src "libresoc.v:125091.18-125091.110" - wire $not$libresoc.v:125091$4744_Y - attribute \src "libresoc.v:125077.18-125077.110" - wire $or$libresoc.v:125077$4730_Y - attribute \src "libresoc.v:125080.18-125080.110" - wire $or$libresoc.v:125080$4733_Y - attribute \src "libresoc.v:125083.18-125083.110" - wire $or$libresoc.v:125083$4736_Y - attribute \src "libresoc.v:125085.18-125085.110" - wire $or$libresoc.v:125085$4738_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "libresoc.v:124769.18-124769.113" + wire $and$libresoc.v:124769$4709_Y + attribute \src "libresoc.v:124771.18-124771.110" + wire $and$libresoc.v:124771$4711_Y + attribute \src "libresoc.v:124784.18-124784.114" + wire $and$libresoc.v:124784$4724_Y + attribute \src "libresoc.v:124785.18-124785.116" + wire $and$libresoc.v:124785$4725_Y + attribute \src "libresoc.v:124787.18-124787.114" + wire $and$libresoc.v:124787$4727_Y + attribute \src "libresoc.v:124789.18-124789.110" + wire $and$libresoc.v:124789$4729_Y + attribute \src "libresoc.v:124790.17-124790.112" + wire $and$libresoc.v:124790$4730_Y + attribute \src "libresoc.v:124791.17-124791.114" + wire $and$libresoc.v:124791$4731_Y + attribute \src "libresoc.v:124772.18-124772.132" + wire $eq$libresoc.v:124772$4712_Y + attribute \src "libresoc.v:124773.18-124773.132" + wire $eq$libresoc.v:124773$4713_Y + attribute \src "libresoc.v:124775.18-124775.110" + wire $eq$libresoc.v:124775$4715_Y + attribute \src "libresoc.v:124776.18-124776.110" + wire $eq$libresoc.v:124776$4716_Y + attribute \src "libresoc.v:124778.18-124778.112" + wire $eq$libresoc.v:124778$4718_Y + attribute \src "libresoc.v:124779.17-124779.136" + wire $eq$libresoc.v:124779$4719_Y + attribute \src "libresoc.v:124781.18-124781.110" + wire $eq$libresoc.v:124781$4721_Y + attribute \src "libresoc.v:124783.18-124783.137" + wire $eq$libresoc.v:124783$4723_Y + attribute \src "libresoc.v:124786.18-124786.137" + wire $eq$libresoc.v:124786$4726_Y + attribute \src "libresoc.v:124792.17-124792.136" + wire $eq$libresoc.v:124792$4732_Y + attribute \src "libresoc.v:124770.18-124770.110" + wire $not$libresoc.v:124770$4710_Y + attribute \src "libresoc.v:124788.18-124788.110" + wire $not$libresoc.v:124788$4728_Y + attribute \src "libresoc.v:124774.18-124774.110" + wire $or$libresoc.v:124774$4714_Y + attribute \src "libresoc.v:124777.18-124777.110" + wire $or$libresoc.v:124777$4717_Y + attribute \src "libresoc.v:124780.18-124780.110" + wire $or$libresoc.v:124780$4720_Y + attribute \src "libresoc.v:124782.18-124782.110" + wire $or$libresoc.v:124782$4722_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -195096,9 +194630,9 @@ module \dec_SHIFT_ROT wire \dec_SHIFT_ROT_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -195115,46 +194649,46 @@ module \dec_SHIFT_ROT attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:124664.7-124664.15" + attribute \src "libresoc.v:124361.7-124361.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 19 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125072$4725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:124769$4709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195162,10 +194696,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:125072$4725_Y + connect \Y $and$libresoc.v:124769$4709_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125074$4727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:124771$4711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195173,10 +194707,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:125074$4727_Y + connect \Y $and$libresoc.v:124771$4711_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125087$4740 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:124784$4724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195184,10 +194718,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:125087$4740_Y + connect \Y $and$libresoc.v:124784$4724_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125088$4741 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:124785$4725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195195,10 +194729,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:125088$4741_Y + connect \Y $and$libresoc.v:124785$4725_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125090$4743 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:124787$4727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195206,10 +194740,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:125090$4743_Y + connect \Y $and$libresoc.v:124787$4727_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125092$4745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:124789$4729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195217,10 +194751,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:125092$4745_Y + connect \Y $and$libresoc.v:124789$4729_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125093$4746 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:124790$4730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195228,10 +194762,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:125093$4746_Y + connect \Y $and$libresoc.v:124790$4730_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125094$4747 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:124791$4731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195239,10 +194773,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:125094$4747_Y + connect \Y $and$libresoc.v:124791$4731_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:125075$4728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" + cell $eq $eq$libresoc.v:124772$4712 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -195250,10 +194784,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:125075$4728_Y + connect \Y $eq$libresoc.v:124772$4712_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:125076$4729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $eq $eq$libresoc.v:124773$4713 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -195261,10 +194795,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:125076$4729_Y + connect \Y $eq$libresoc.v:124773$4713_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:125078$4731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:124775$4715 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195272,10 +194806,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:125078$4731_Y + connect \Y $eq$libresoc.v:124775$4715_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:125079$4732 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:124776$4716 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195283,10 +194817,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:125079$4732_Y + connect \Y $eq$libresoc.v:124776$4716_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:125081$4734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:124778$4718 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195294,10 +194828,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:125081$4734_Y + connect \Y $eq$libresoc.v:124778$4718_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:125082$4735 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:124779$4719 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195305,10 +194839,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:125082$4735_Y + connect \Y $eq$libresoc.v:124779$4719_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:125084$4737 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $eq $eq$libresoc.v:124781$4721 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195316,10 +194850,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:125084$4737_Y + connect \Y $eq$libresoc.v:124781$4721_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:125086$4739 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:124783$4723 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195327,10 +194861,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:125086$4739_Y + connect \Y $eq$libresoc.v:124783$4723_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:125089$4742 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:124786$4726 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195338,10 +194872,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:125089$4742_Y + connect \Y $eq$libresoc.v:124786$4726_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:125095$4748 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:124792$4732 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195349,26 +194883,26 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:125095$4748_Y + connect \Y $eq$libresoc.v:124792$4732_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:125073$4726 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:124770$4710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:125073$4726_Y + connect \Y $not$libresoc.v:124770$4710_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:125091$4744 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:124788$4728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:125091$4744_Y + connect \Y $not$libresoc.v:124788$4728_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:125077$4730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $or $or$libresoc.v:124774$4714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195376,10 +194910,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:125077$4730_Y + connect \Y $or$libresoc.v:124774$4714_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:125080$4733 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:124777$4717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195387,10 +194921,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:125080$4733_Y + connect \Y $or$libresoc.v:124777$4717_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:125083$4736 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:124780$4720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195398,10 +194932,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:125083$4736_Y + connect \Y $or$libresoc.v:124780$4720_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:125085$4738 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $or $or$libresoc.v:124782$4722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195409,10 +194943,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:125085$4738_Y + connect \Y $or$libresoc.v:124782$4722_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:125096.13-125121.4" + attribute \src "libresoc.v:124793.13-124818.4" cell \dec$162 \dec connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS @@ -195440,7 +194974,7 @@ module \dec_SHIFT_ROT connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125122.16-125133.4" + attribute \src "libresoc.v:124819.16-124830.4" cell \dec_bi$165 \dec_bi connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS @@ -195454,7 +194988,7 @@ module \dec_SHIFT_ROT connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125134.16-125140.4" + attribute \src "libresoc.v:124831.16-124837.4" cell \dec_oe$164 \dec_oe connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op @@ -195463,33 +194997,33 @@ module \dec_SHIFT_ROT connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125141.16-125146.4" + attribute \src "libresoc.v:124838.16-124843.4" cell \dec_rc$163 \dec_rc connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:124664.7-124664.20" - process $proc$libresoc.v:124664$4752 + attribute \src "libresoc.v:124361.7-124361.20" + process $proc$libresoc.v:124361$4736 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125147.3-125161.6" - process $proc$libresoc.v:125147$4749 + attribute \src "libresoc.v:124844.3-124858.6" + process $proc$libresoc.v:124844$4733 assign { } { } assign { } { } assign $0\SHIFT_ROT__write_cr0[0:0] $1\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:125148.5-125148.29" + attribute \src "libresoc.v:124845.5-124845.29" switch \initial - attribute \src "libresoc.v:125148.9-125148.17" + attribute \src "libresoc.v:124845.9-124845.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" switch \dec_SHIFT_ROT_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -195505,18 +195039,18 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__write_cr0 $0\SHIFT_ROT__write_cr0[0:0] end - attribute \src "libresoc.v:125162.3-125174.6" - process $proc$libresoc.v:125162$4750 + attribute \src "libresoc.v:124859.3-124871.6" + process $proc$libresoc.v:124859$4734 assign { } { } assign { } { } assign $0\SHIFT_ROT__insn_type[6:0] $1\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:125163.5-125163.29" + attribute \src "libresoc.v:124860.5-124860.29" switch \initial - attribute \src "libresoc.v:125163.9-125163.17" + attribute \src "libresoc.v:124860.9-124860.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -195532,17 +195066,17 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__insn_type $0\SHIFT_ROT__insn_type[6:0] end - attribute \src "libresoc.v:125175.3-125189.6" - process $proc$libresoc.v:125175$4751 + attribute \src "libresoc.v:124872.3-124886.6" + process $proc$libresoc.v:124872$4735 assign { } { } assign $0\SHIFT_ROT__fn_unit[13:0] $1\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:125176.5-125176.29" + attribute \src "libresoc.v:124873.5-124873.29" switch \initial - attribute \src "libresoc.v:125176.9-125176.17" + attribute \src "libresoc.v:124873.9-124873.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -195560,30 +195094,30 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__fn_unit $0\SHIFT_ROT__fn_unit[13:0] end - connect \$10 $and$libresoc.v:125072$4725_Y - connect \$12 $not$libresoc.v:125073$4726_Y - connect \$14 $and$libresoc.v:125074$4727_Y - connect \$16 $eq$libresoc.v:125075$4728_Y - connect \$18 $eq$libresoc.v:125076$4729_Y - connect \$20 $or$libresoc.v:125077$4730_Y - connect \$22 $eq$libresoc.v:125078$4731_Y - connect \$24 $eq$libresoc.v:125079$4732_Y - connect \$26 $or$libresoc.v:125080$4733_Y - connect \$28 $eq$libresoc.v:125081$4734_Y - connect \$2 $eq$libresoc.v:125082$4735_Y - connect \$30 $or$libresoc.v:125083$4736_Y - connect \$32 $eq$libresoc.v:125084$4737_Y - connect \$34 $or$libresoc.v:125085$4738_Y - connect \$36 $eq$libresoc.v:125086$4739_Y - connect \$38 $and$libresoc.v:125087$4740_Y - connect \$40 $and$libresoc.v:125088$4741_Y - connect \$42 $eq$libresoc.v:125089$4742_Y - connect \$44 $and$libresoc.v:125090$4743_Y - connect \$46 $not$libresoc.v:125091$4744_Y - connect \$48 $and$libresoc.v:125092$4745_Y - connect \$4 $and$libresoc.v:125093$4746_Y - connect \$6 $and$libresoc.v:125094$4747_Y - connect \$8 $eq$libresoc.v:125095$4748_Y + connect \$10 $and$libresoc.v:124769$4709_Y + connect \$12 $not$libresoc.v:124770$4710_Y + connect \$14 $and$libresoc.v:124771$4711_Y + connect \$16 $eq$libresoc.v:124772$4712_Y + connect \$18 $eq$libresoc.v:124773$4713_Y + connect \$20 $or$libresoc.v:124774$4714_Y + connect \$22 $eq$libresoc.v:124775$4715_Y + connect \$24 $eq$libresoc.v:124776$4716_Y + connect \$26 $or$libresoc.v:124777$4717_Y + connect \$28 $eq$libresoc.v:124778$4718_Y + connect \$2 $eq$libresoc.v:124779$4719_Y + connect \$30 $or$libresoc.v:124780$4720_Y + connect \$32 $eq$libresoc.v:124781$4721_Y + connect \$34 $or$libresoc.v:124782$4722_Y + connect \$36 $eq$libresoc.v:124783$4723_Y + connect \$38 $and$libresoc.v:124784$4724_Y + connect \$40 $and$libresoc.v:124785$4725_Y + connect \$42 $eq$libresoc.v:124786$4726_Y + connect \$44 $and$libresoc.v:124787$4727_Y + connect \$46 $not$libresoc.v:124788$4728_Y + connect \$48 $and$libresoc.v:124789$4729_Y + connect \$4 $and$libresoc.v:124790$4730_Y + connect \$6 $and$libresoc.v:124791$4731_Y + connect \$8 $eq$libresoc.v:124792$4732_Y connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out @@ -195604,116 +195138,116 @@ module \dec_SHIFT_ROT connect \insn_in \dec_opcode_in connect \SHIFT_ROT__insn \dec_opcode_in end -attribute \src "libresoc.v:125213.1-125591.10" +attribute \src "libresoc.v:124910.1-125288.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" attribute \generator "nMigen" module \dec_SPR - attribute \src "libresoc.v:125567.3-125581.6" + attribute \src "libresoc.v:125264.3-125278.6" wire width 14 $0\SPR__fn_unit[13:0] - attribute \src "libresoc.v:125554.3-125566.6" + attribute \src "libresoc.v:125251.3-125263.6" wire width 7 $0\SPR__insn_type[6:0] - attribute \src "libresoc.v:125214.7-125214.20" + attribute \src "libresoc.v:124911.7-124911.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125567.3-125581.6" + attribute \src "libresoc.v:125264.3-125278.6" wire width 14 $1\SPR__fn_unit[13:0] - attribute \src "libresoc.v:125554.3-125566.6" + attribute \src "libresoc.v:125251.3-125263.6" wire width 7 $1\SPR__insn_type[6:0] - attribute \src "libresoc.v:125508.18-125508.113" - wire $and$libresoc.v:125508$4753_Y - attribute \src "libresoc.v:125510.18-125510.110" - wire $and$libresoc.v:125510$4755_Y - attribute \src "libresoc.v:125523.18-125523.114" - wire $and$libresoc.v:125523$4768_Y - attribute \src "libresoc.v:125524.18-125524.116" - wire $and$libresoc.v:125524$4769_Y - attribute \src "libresoc.v:125526.18-125526.114" - wire $and$libresoc.v:125526$4771_Y - attribute \src "libresoc.v:125528.18-125528.110" - wire $and$libresoc.v:125528$4773_Y - attribute \src "libresoc.v:125529.17-125529.112" - wire $and$libresoc.v:125529$4774_Y - attribute \src "libresoc.v:125530.17-125530.114" - wire $and$libresoc.v:125530$4775_Y - attribute \src "libresoc.v:125511.18-125511.126" - wire $eq$libresoc.v:125511$4756_Y - attribute \src "libresoc.v:125512.18-125512.126" - wire $eq$libresoc.v:125512$4757_Y - attribute \src "libresoc.v:125514.18-125514.110" - wire $eq$libresoc.v:125514$4759_Y - attribute \src "libresoc.v:125515.18-125515.110" - wire $eq$libresoc.v:125515$4760_Y - attribute \src "libresoc.v:125517.18-125517.112" - wire $eq$libresoc.v:125517$4762_Y - attribute \src "libresoc.v:125518.17-125518.130" - wire $eq$libresoc.v:125518$4763_Y - attribute \src "libresoc.v:125520.18-125520.110" - wire $eq$libresoc.v:125520$4765_Y - attribute \src "libresoc.v:125522.18-125522.131" - wire $eq$libresoc.v:125522$4767_Y - attribute \src "libresoc.v:125525.18-125525.131" - wire $eq$libresoc.v:125525$4770_Y - attribute \src "libresoc.v:125531.17-125531.130" - wire $eq$libresoc.v:125531$4776_Y - attribute \src "libresoc.v:125509.18-125509.110" - wire $not$libresoc.v:125509$4754_Y - attribute \src "libresoc.v:125527.18-125527.110" - wire $not$libresoc.v:125527$4772_Y - attribute \src "libresoc.v:125513.18-125513.110" - wire $or$libresoc.v:125513$4758_Y - attribute \src "libresoc.v:125516.18-125516.110" - wire $or$libresoc.v:125516$4761_Y - attribute \src "libresoc.v:125519.18-125519.110" - wire $or$libresoc.v:125519$4764_Y - attribute \src "libresoc.v:125521.18-125521.110" - wire $or$libresoc.v:125521$4766_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "libresoc.v:125205.18-125205.113" + wire $and$libresoc.v:125205$4737_Y + attribute \src "libresoc.v:125207.18-125207.110" + wire $and$libresoc.v:125207$4739_Y + attribute \src "libresoc.v:125220.18-125220.114" + wire $and$libresoc.v:125220$4752_Y + attribute \src "libresoc.v:125221.18-125221.116" + wire $and$libresoc.v:125221$4753_Y + attribute \src "libresoc.v:125223.18-125223.114" + wire $and$libresoc.v:125223$4755_Y + attribute \src "libresoc.v:125225.18-125225.110" + wire $and$libresoc.v:125225$4757_Y + attribute \src "libresoc.v:125226.17-125226.112" + wire $and$libresoc.v:125226$4758_Y + attribute \src "libresoc.v:125227.17-125227.114" + wire $and$libresoc.v:125227$4759_Y + attribute \src "libresoc.v:125208.18-125208.126" + wire $eq$libresoc.v:125208$4740_Y + attribute \src "libresoc.v:125209.18-125209.126" + wire $eq$libresoc.v:125209$4741_Y + attribute \src "libresoc.v:125211.18-125211.110" + wire $eq$libresoc.v:125211$4743_Y + attribute \src "libresoc.v:125212.18-125212.110" + wire $eq$libresoc.v:125212$4744_Y + attribute \src "libresoc.v:125214.18-125214.112" + wire $eq$libresoc.v:125214$4746_Y + attribute \src "libresoc.v:125215.17-125215.130" + wire $eq$libresoc.v:125215$4747_Y + attribute \src "libresoc.v:125217.18-125217.110" + wire $eq$libresoc.v:125217$4749_Y + attribute \src "libresoc.v:125219.18-125219.131" + wire $eq$libresoc.v:125219$4751_Y + attribute \src "libresoc.v:125222.18-125222.131" + wire $eq$libresoc.v:125222$4754_Y + attribute \src "libresoc.v:125228.17-125228.130" + wire $eq$libresoc.v:125228$4760_Y + attribute \src "libresoc.v:125206.18-125206.110" + wire $not$libresoc.v:125206$4738_Y + attribute \src "libresoc.v:125224.18-125224.110" + wire $not$libresoc.v:125224$4756_Y + attribute \src "libresoc.v:125210.18-125210.110" + wire $or$libresoc.v:125210$4742_Y + attribute \src "libresoc.v:125213.18-125213.110" + wire $or$libresoc.v:125213$4745_Y + attribute \src "libresoc.v:125216.18-125216.110" + wire $or$libresoc.v:125216$4748_Y + attribute \src "libresoc.v:125218.18-125218.110" + wire $or$libresoc.v:125218$4750_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -195936,7 +195470,7 @@ module \dec_SPR attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in @@ -195944,24 +195478,24 @@ module \dec_SPR attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:125214.7-125214.15" + attribute \src "libresoc.v:124911.7-124911.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 6 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125508$4753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:125205$4737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195969,10 +195503,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:125508$4753_Y + connect \Y $and$libresoc.v:125205$4737_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125510$4755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:125207$4739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195980,10 +195514,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:125510$4755_Y + connect \Y $and$libresoc.v:125207$4739_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125523$4768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:125220$4752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195991,10 +195525,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:125523$4768_Y + connect \Y $and$libresoc.v:125220$4752_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125524$4769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:125221$4753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196002,10 +195536,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:125524$4769_Y + connect \Y $and$libresoc.v:125221$4753_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125526$4771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:125223$4755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196013,10 +195547,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:125526$4771_Y + connect \Y $and$libresoc.v:125223$4755_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125528$4773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $and $and$libresoc.v:125225$4757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196024,10 +195558,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:125528$4773_Y + connect \Y $and$libresoc.v:125225$4757_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125529$4774 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:125226$4758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196035,10 +195569,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:125529$4774_Y + connect \Y $and$libresoc.v:125226$4758_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125530$4775 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $and $and$libresoc.v:125227$4759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196046,10 +195580,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:125530$4775_Y + connect \Y $and$libresoc.v:125227$4759_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:125511$4756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" + cell $eq $eq$libresoc.v:125208$4740 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -196057,10 +195591,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:125511$4756_Y + connect \Y $eq$libresoc.v:125208$4740_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:125512$4757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $eq $eq$libresoc.v:125209$4741 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -196068,10 +195602,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:125512$4757_Y + connect \Y $eq$libresoc.v:125209$4741_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:125514$4759 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:125211$4743 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -196079,10 +195613,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:125514$4759_Y + connect \Y $eq$libresoc.v:125211$4743_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:125515$4760 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:125212$4744 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -196090,10 +195624,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:125515$4760_Y + connect \Y $eq$libresoc.v:125212$4744_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:125517$4762 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $eq $eq$libresoc.v:125214$4746 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -196101,10 +195635,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:125517$4762_Y + connect \Y $eq$libresoc.v:125214$4746_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:125518$4763 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:125215$4747 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196112,10 +195646,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:125518$4763_Y + connect \Y $eq$libresoc.v:125215$4747_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:125520$4765 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $eq $eq$libresoc.v:125217$4749 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -196123,10 +195657,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:125520$4765_Y + connect \Y $eq$libresoc.v:125217$4749_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:125522$4767 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + cell $eq $eq$libresoc.v:125219$4751 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196134,10 +195668,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:125522$4767_Y + connect \Y $eq$libresoc.v:125219$4751_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:125525$4770 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:125222$4754 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196145,10 +195679,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:125525$4770_Y + connect \Y $eq$libresoc.v:125222$4754_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:125531$4776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $eq $eq$libresoc.v:125228$4760 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196156,26 +195690,26 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:125531$4776_Y + connect \Y $eq$libresoc.v:125228$4760_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:125509$4754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:125206$4738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:125509$4754_Y + connect \Y $not$libresoc.v:125206$4738_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:125527$4772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" + cell $not $not$libresoc.v:125224$4756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:125527$4772_Y + connect \Y $not$libresoc.v:125224$4756_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:125513$4758 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + cell $or $or$libresoc.v:125210$4742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196183,10 +195717,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:125513$4758_Y + connect \Y $or$libresoc.v:125210$4742_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:125516$4761 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:125213$4745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196194,10 +195728,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:125516$4761_Y + connect \Y $or$libresoc.v:125213$4745_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:125519$4764 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" + cell $or $or$libresoc.v:125216$4748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196205,10 +195739,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:125519$4764_Y + connect \Y $or$libresoc.v:125216$4748_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:125521$4766 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" + cell $or $or$libresoc.v:125218$4750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196216,10 +195750,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:125521$4766_Y + connect \Y $or$libresoc.v:125218$4750_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:125532.13-125544.4" + attribute \src "libresoc.v:125229.13-125241.4" cell \dec$150 \dec connect \SPR_OE \dec_SPR_OE connect \SPR_Rc \dec_SPR_Rc @@ -196234,38 +195768,38 @@ module \dec_SPR connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125545.16-125549.4" + attribute \src "libresoc.v:125242.16-125246.4" cell \dec_oe$152 \dec_oe connect \SPR_OE \dec_SPR_OE connect \SPR_internal_op \dec_SPR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125550.16-125553.4" + attribute \src "libresoc.v:125247.16-125250.4" cell \dec_rc$151 \dec_rc connect \SPR_Rc \dec_SPR_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:125214.7-125214.20" - process $proc$libresoc.v:125214$4779 + attribute \src "libresoc.v:124911.7-124911.20" + process $proc$libresoc.v:124911$4763 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125554.3-125566.6" - process $proc$libresoc.v:125554$4777 + attribute \src "libresoc.v:125251.3-125263.6" + process $proc$libresoc.v:125251$4761 assign { } { } assign { } { } assign $0\SPR__insn_type[6:0] $1\SPR__insn_type[6:0] - attribute \src "libresoc.v:125555.5-125555.29" + attribute \src "libresoc.v:125252.5-125252.29" switch \initial - attribute \src "libresoc.v:125555.9-125555.17" + attribute \src "libresoc.v:125252.9-125252.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -196281,17 +195815,17 @@ module \dec_SPR sync always update \SPR__insn_type $0\SPR__insn_type[6:0] end - attribute \src "libresoc.v:125567.3-125581.6" - process $proc$libresoc.v:125567$4778 + attribute \src "libresoc.v:125264.3-125278.6" + process $proc$libresoc.v:125264$4762 assign { } { } assign $0\SPR__fn_unit[13:0] $1\SPR__fn_unit[13:0] - attribute \src "libresoc.v:125568.5-125568.29" + attribute \src "libresoc.v:125265.5-125265.29" switch \initial - attribute \src "libresoc.v:125568.9-125568.17" + attribute \src "libresoc.v:125265.9-125265.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -196309,30 +195843,30 @@ module \dec_SPR sync always update \SPR__fn_unit $0\SPR__fn_unit[13:0] end - connect \$10 $and$libresoc.v:125508$4753_Y - connect \$12 $not$libresoc.v:125509$4754_Y - connect \$14 $and$libresoc.v:125510$4755_Y - connect \$16 $eq$libresoc.v:125511$4756_Y - connect \$18 $eq$libresoc.v:125512$4757_Y - connect \$20 $or$libresoc.v:125513$4758_Y - connect \$22 $eq$libresoc.v:125514$4759_Y - connect \$24 $eq$libresoc.v:125515$4760_Y - connect \$26 $or$libresoc.v:125516$4761_Y - connect \$28 $eq$libresoc.v:125517$4762_Y - connect \$2 $eq$libresoc.v:125518$4763_Y - connect \$30 $or$libresoc.v:125519$4764_Y - connect \$32 $eq$libresoc.v:125520$4765_Y - connect \$34 $or$libresoc.v:125521$4766_Y - connect \$36 $eq$libresoc.v:125522$4767_Y - connect \$38 $and$libresoc.v:125523$4768_Y - connect \$40 $and$libresoc.v:125524$4769_Y - connect \$42 $eq$libresoc.v:125525$4770_Y - connect \$44 $and$libresoc.v:125526$4771_Y - connect \$46 $not$libresoc.v:125527$4772_Y - connect \$48 $and$libresoc.v:125528$4773_Y - connect \$4 $and$libresoc.v:125529$4774_Y - connect \$6 $and$libresoc.v:125530$4775_Y - connect \$8 $eq$libresoc.v:125531$4776_Y + connect \$10 $and$libresoc.v:125205$4737_Y + connect \$12 $not$libresoc.v:125206$4738_Y + connect \$14 $and$libresoc.v:125207$4739_Y + connect \$16 $eq$libresoc.v:125208$4740_Y + connect \$18 $eq$libresoc.v:125209$4741_Y + connect \$20 $or$libresoc.v:125210$4742_Y + connect \$22 $eq$libresoc.v:125211$4743_Y + connect \$24 $eq$libresoc.v:125212$4744_Y + connect \$26 $or$libresoc.v:125213$4745_Y + connect \$28 $eq$libresoc.v:125214$4746_Y + connect \$2 $eq$libresoc.v:125215$4747_Y + connect \$30 $or$libresoc.v:125216$4748_Y + connect \$32 $eq$libresoc.v:125217$4749_Y + connect \$34 $or$libresoc.v:125218$4750_Y + connect \$36 $eq$libresoc.v:125219$4751_Y + connect \$38 $and$libresoc.v:125220$4752_Y + connect \$40 $and$libresoc.v:125221$4753_Y + connect \$42 $eq$libresoc.v:125222$4754_Y + connect \$44 $and$libresoc.v:125223$4755_Y + connect \$46 $not$libresoc.v:125224$4756_Y + connect \$48 $and$libresoc.v:125225$4757_Y + connect \$4 $and$libresoc.v:125226$4758_Y + connect \$6 $and$libresoc.v:125227$4759_Y + connect \$8 $eq$libresoc.v:125228$4760_Y connect \SPR__is_32bit \dec_SPR_is_32b connect \is_mmu_spr \$34 connect \is_spr_mv \$20 @@ -196343,132 +195877,132 @@ module \dec_SPR connect \insn_in \dec_opcode_in connect \SPR__insn \dec_opcode_in end -attribute \src "libresoc.v:125595.1-126124.10" +attribute \src "libresoc.v:125292.1-125845.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" attribute \generator "nMigen" module \dec_a - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:125749.3-125784.6" wire width 3 $0\fast_a[2:0] - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:125749.3-125784.6" wire $0\fast_a_ok[0:0] - attribute \src "libresoc.v:125596.7-125596.20" + attribute \src "libresoc.v:125293.7-125293.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126020.3-126035.6" + attribute \src "libresoc.v:125717.3-125732.6" wire width 5 $0\reg_a[4:0] - attribute \src "libresoc.v:126036.3-126051.6" + attribute \src "libresoc.v:125733.3-125748.6" wire $0\reg_a_ok[0:0] - attribute \src "libresoc.v:126088.3-126098.6" + attribute \src "libresoc.v:125785.3-125803.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:126110.3-126121.6" + attribute \src "libresoc.v:125823.3-125842.6" wire width 10 $0\spr_a[9:0] - attribute \src "libresoc.v:126110.3-126121.6" + attribute \src "libresoc.v:125823.3-125842.6" wire $0\spr_a_ok[0:0] - attribute \src "libresoc.v:126099.3-126109.6" + attribute \src "libresoc.v:125804.3-125822.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:125749.3-125784.6" wire width 3 $1\fast_a[2:0] - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:125749.3-125784.6" wire $1\fast_a_ok[0:0] - attribute \src "libresoc.v:126020.3-126035.6" + attribute \src "libresoc.v:125717.3-125732.6" wire width 5 $1\reg_a[4:0] - attribute \src "libresoc.v:126036.3-126051.6" + attribute \src "libresoc.v:125733.3-125748.6" wire $1\reg_a_ok[0:0] - attribute \src "libresoc.v:126088.3-126098.6" + attribute \src "libresoc.v:125785.3-125803.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:126110.3-126121.6" + attribute \src "libresoc.v:125823.3-125842.6" wire width 10 $1\spr_a[9:0] - attribute \src "libresoc.v:126110.3-126121.6" + attribute \src "libresoc.v:125823.3-125842.6" wire $1\spr_a_ok[0:0] - attribute \src "libresoc.v:126099.3-126109.6" + attribute \src "libresoc.v:125804.3-125822.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:125749.3-125784.6" wire width 3 $2\fast_a[2:0] - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:125749.3-125784.6" wire $2\fast_a_ok[0:0] - attribute \src "libresoc.v:126020.3-126035.6" + attribute \src "libresoc.v:125717.3-125732.6" wire width 5 $2\reg_a[4:0] - attribute \src "libresoc.v:126036.3-126051.6" + attribute \src "libresoc.v:125733.3-125748.6" wire $2\reg_a_ok[0:0] - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:125749.3-125784.6" wire width 3 $3\fast_a[2:0] - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:125749.3-125784.6" wire $3\fast_a_ok[0:0] - attribute \src "libresoc.v:125995.18-125995.108" - wire $and$libresoc.v:125995$4781_Y - attribute \src "libresoc.v:126004.18-126004.110" - wire $and$libresoc.v:126004$4790_Y - attribute \src "libresoc.v:126009.18-126009.113" - wire $and$libresoc.v:126009$4795_Y - attribute \src "libresoc.v:125997.18-125997.112" - wire $eq$libresoc.v:125997$4783_Y - attribute \src "libresoc.v:125998.18-125998.112" - wire $eq$libresoc.v:125998$4784_Y - attribute \src "libresoc.v:125999.17-125999.111" - wire $eq$libresoc.v:125999$4785_Y - attribute \src "libresoc.v:126000.18-126000.112" - wire $eq$libresoc.v:126000$4786_Y - attribute \src "libresoc.v:126006.18-126006.112" - wire $eq$libresoc.v:126006$4792_Y - attribute \src "libresoc.v:126010.17-126010.111" - wire $eq$libresoc.v:126010$4796_Y - attribute \src "libresoc.v:126001.18-126001.109" - wire $ne$libresoc.v:126001$4787_Y - attribute \src "libresoc.v:126002.18-126002.111" - wire $ne$libresoc.v:126002$4788_Y - attribute \src "libresoc.v:126011.17-126011.108" - wire $ne$libresoc.v:126011$4797_Y - attribute \src "libresoc.v:126012.17-126012.110" - wire $ne$libresoc.v:126012$4798_Y - attribute \src "libresoc.v:126007.18-126007.105" - wire $not$libresoc.v:126007$4793_Y - attribute \src "libresoc.v:126008.18-126008.108" - wire $not$libresoc.v:126008$4794_Y - attribute \src "libresoc.v:125994.17-125994.107" - wire $or$libresoc.v:125994$4780_Y - attribute \src "libresoc.v:125996.18-125996.109" - wire $or$libresoc.v:125996$4782_Y - attribute \src "libresoc.v:126003.18-126003.110" - wire $or$libresoc.v:126003$4789_Y - attribute \src "libresoc.v:126005.18-126005.110" - wire $or$libresoc.v:126005$4791_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + attribute \src "libresoc.v:125692.18-125692.108" + wire $and$libresoc.v:125692$4765_Y + attribute \src "libresoc.v:125701.18-125701.110" + wire $and$libresoc.v:125701$4774_Y + attribute \src "libresoc.v:125706.18-125706.113" + wire $and$libresoc.v:125706$4779_Y + attribute \src "libresoc.v:125694.18-125694.112" + wire $eq$libresoc.v:125694$4767_Y + attribute \src "libresoc.v:125695.18-125695.112" + wire $eq$libresoc.v:125695$4768_Y + attribute \src "libresoc.v:125696.17-125696.111" + wire $eq$libresoc.v:125696$4769_Y + attribute \src "libresoc.v:125697.18-125697.112" + wire $eq$libresoc.v:125697$4770_Y + attribute \src "libresoc.v:125703.18-125703.112" + wire $eq$libresoc.v:125703$4776_Y + attribute \src "libresoc.v:125707.17-125707.111" + wire $eq$libresoc.v:125707$4780_Y + attribute \src "libresoc.v:125698.18-125698.109" + wire $ne$libresoc.v:125698$4771_Y + attribute \src "libresoc.v:125699.18-125699.111" + wire $ne$libresoc.v:125699$4772_Y + attribute \src "libresoc.v:125708.17-125708.108" + wire $ne$libresoc.v:125708$4781_Y + attribute \src "libresoc.v:125709.17-125709.110" + wire $ne$libresoc.v:125709$4782_Y + attribute \src "libresoc.v:125704.18-125704.105" + wire $not$libresoc.v:125704$4777_Y + attribute \src "libresoc.v:125705.18-125705.108" + wire $not$libresoc.v:125705$4778_Y + attribute \src "libresoc.v:125691.17-125691.107" + wire $or$libresoc.v:125691$4764_Y + attribute \src "libresoc.v:125693.18-125693.109" + wire $or$libresoc.v:125693$4766_Y + attribute \src "libresoc.v:125700.18-125700.110" + wire $or$libresoc.v:125700$4773_Y + attribute \src "libresoc.v:125702.18-125702.110" + wire $or$libresoc.v:125702$4775_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 12 \BO @@ -196480,11 +196014,11 @@ module \dec_a wire width 10 input 1 \SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 input 13 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 8 \fast_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 9 \fast_a_ok - attribute \src "libresoc.v:125596.7-125596.15" + attribute \src "libresoc.v:125293.7-125293.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -196563,13 +196097,13 @@ module \dec_a attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 14 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" wire width 5 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 output 4 \reg_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \reg_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" wire width 5 \rs attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -196577,9 +196111,9 @@ module \dec_a attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:145" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -196695,15 +196229,15 @@ module \dec_a attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 output 6 \spr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 7 \spr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \sprmap_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \sprmap_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" wire width 10 \sprmap_spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -196819,14 +196353,14 @@ module \dec_a attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \sprmap_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" wire input 2 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $and $and$libresoc.v:125995$4781 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + cell $and $and$libresoc.v:125692$4765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196834,10 +196368,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$3 connect \B \$9 - connect \Y $and$libresoc.v:125995$4781_Y + connect \Y $and$libresoc.v:125692$4765_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $and $and$libresoc.v:126004$4790 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + cell $and $and$libresoc.v:125701$4774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196845,10 +196379,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$19 connect \B \$25 - connect \Y $and$libresoc.v:126004$4790_Y + connect \Y $and$libresoc.v:125701$4774_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - cell $and $and$libresoc.v:126009$4795 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" + cell $and $and$libresoc.v:125706$4779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196856,10 +196390,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \XL_XO [9] connect \B \$35 - connect \Y $and$libresoc.v:126009$4795_Y + connect \Y $and$libresoc.v:125706$4779_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" - cell $eq $eq$libresoc.v:125997$4783 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" + cell $eq $eq$libresoc.v:125694$4767 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196867,10 +196401,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:125997$4783_Y + connect \Y $eq$libresoc.v:125694$4767_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - cell $eq $eq$libresoc.v:125998$4784 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" + cell $eq $eq$libresoc.v:125695$4768 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196878,10 +196412,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:125998$4784_Y + connect \Y $eq$libresoc.v:125695$4768_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - cell $eq $eq$libresoc.v:125999$4785 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" + cell $eq $eq$libresoc.v:125696$4769 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196889,10 +196423,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:125999$4785_Y + connect \Y $eq$libresoc.v:125696$4769_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $eq $eq$libresoc.v:126000$4786 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" + cell $eq $eq$libresoc.v:125697$4770 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196900,10 +196434,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126000$4786_Y + connect \Y $eq$libresoc.v:125697$4770_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" - cell $eq $eq$libresoc.v:126006$4792 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" + cell $eq $eq$libresoc.v:125703$4776 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196911,10 +196445,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:126006$4792_Y + connect \Y $eq$libresoc.v:125703$4776_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $eq $eq$libresoc.v:126010$4796 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" + cell $eq $eq$libresoc.v:125707$4780 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196922,10 +196456,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126010$4796_Y + connect \Y $eq$libresoc.v:125707$4780_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $ne $ne$libresoc.v:126001$4787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + cell $ne $ne$libresoc.v:125698$4771 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -196933,10 +196467,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:126001$4787_Y + connect \Y $ne$libresoc.v:125698$4771_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $ne $ne$libresoc.v:126002$4788 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + cell $ne $ne$libresoc.v:125699$4772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196944,10 +196478,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $ne$libresoc.v:126002$4788_Y + connect \Y $ne$libresoc.v:125699$4772_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $ne $ne$libresoc.v:126011$4797 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + cell $ne $ne$libresoc.v:125708$4781 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -196955,10 +196489,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:126011$4797_Y + connect \Y $ne$libresoc.v:125708$4781_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $ne $ne$libresoc.v:126012$4798 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + cell $ne $ne$libresoc.v:125709$4782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196966,26 +196500,26 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $ne$libresoc.v:126012$4798_Y + connect \Y $ne$libresoc.v:125709$4782_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" - cell $not $not$libresoc.v:126007$4793 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + cell $not $not$libresoc.v:125704$4777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:126007$4793_Y + connect \Y $not$libresoc.v:125704$4777_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - cell $not $not$libresoc.v:126008$4794 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" + cell $not $not$libresoc.v:125705$4778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [5] - connect \Y $not$libresoc.v:126008$4794_Y + connect \Y $not$libresoc.v:125705$4778_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $or $or$libresoc.v:125994$4780 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + cell $or $or$libresoc.v:125691$4764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196993,10 +196527,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $or$libresoc.v:125994$4780_Y + connect \Y $or$libresoc.v:125691$4764_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $or $or$libresoc.v:125996$4782 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + cell $or $or$libresoc.v:125693$4766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197004,10 +196538,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$1 connect \B \$11 - connect \Y $or$libresoc.v:125996$4782_Y + connect \Y $or$libresoc.v:125693$4766_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $or $or$libresoc.v:126003$4789 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + cell $or $or$libresoc.v:125700$4773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197015,10 +196549,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$21 connect \B \$23 - connect \Y $or$libresoc.v:126003$4789_Y + connect \Y $or$libresoc.v:125700$4773_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $or $or$libresoc.v:126005$4791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + cell $or $or$libresoc.v:125702$4775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197026,10 +196560,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$17 connect \B \$27 - connect \Y $or$libresoc.v:126005$4791_Y + connect \Y $or$libresoc.v:125702$4775_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:126013.10-126019.4" + attribute \src "libresoc.v:125710.10-125716.4" cell \sprmap \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok @@ -197037,27 +196571,27 @@ module \dec_a connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:125596.7-125596.20" - process $proc$libresoc.v:125596$4805 + attribute \src "libresoc.v:125293.7-125293.20" + process $proc$libresoc.v:125293$4789 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126020.3-126035.6" - process $proc$libresoc.v:126020$4799 + attribute \src "libresoc.v:125717.3-125732.6" + process $proc$libresoc.v:125717$4783 assign { } { } assign { } { } assign { } { } assign $0\reg_a[4:0] $2\reg_a[4:0] - attribute \src "libresoc.v:126021.5-126021.29" + attribute \src "libresoc.v:125718.5-125718.29" switch \initial - attribute \src "libresoc.v:126021.9-126021.17" + attribute \src "libresoc.v:125718.9-125718.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -197066,7 +196600,7 @@ module \dec_a case assign $1\reg_a[4:0] 5'00000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -197078,19 +196612,19 @@ module \dec_a sync always update \reg_a $0\reg_a[4:0] end - attribute \src "libresoc.v:126036.3-126051.6" - process $proc$libresoc.v:126036$4800 + attribute \src "libresoc.v:125733.3-125748.6" + process $proc$libresoc.v:125733$4784 assign { } { } assign { } { } assign { } { } assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] - attribute \src "libresoc.v:126037.5-126037.29" + attribute \src "libresoc.v:125734.5-125734.29" switch \initial - attribute \src "libresoc.v:126037.9-126037.17" + attribute \src "libresoc.v:125734.9-125734.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -197099,7 +196633,7 @@ module \dec_a case assign $1\reg_a_ok[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -197111,21 +196645,21 @@ module \dec_a sync always update \reg_a_ok $0\reg_a_ok[0:0] end - attribute \src "libresoc.v:126052.3-126087.6" - process $proc$libresoc.v:126052$4801 + attribute \src "libresoc.v:125749.3-125784.6" + process $proc$libresoc.v:125749$4785 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast_a[2:0] $1\fast_a[2:0] assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] - attribute \src "libresoc.v:126053.5-126053.29" + attribute \src "libresoc.v:125750.5-125750.29" switch \initial - attribute \src "libresoc.v:126053.9-126053.17" + attribute \src "libresoc.v:125750.9-125750.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 @@ -197133,7 +196667,7 @@ module \dec_a assign { } { } assign $1\fast_a[2:0] $2\fast_a[2:0] assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" switch \$33 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -197151,7 +196685,7 @@ module \dec_a assign { } { } assign $1\fast_a[2:0] $3\fast_a[2:0] assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" switch \$37 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -197176,20 +196710,26 @@ module \dec_a update \fast_a $0\fast_a[2:0] update \fast_a_ok $0\fast_a_ok[0:0] end - attribute \src "libresoc.v:126088.3-126098.6" - process $proc$libresoc.v:126088$4802 + attribute \src "libresoc.v:125785.3-125803.6" + process $proc$libresoc.v:125785$4786 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:126089.5-126089.29" + attribute \src "libresoc.v:125786.5-125786.29" switch \initial - attribute \src "libresoc.v:126089.9-126089.17" + attribute \src "libresoc.v:125786.9-125786.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" switch \internal_op attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign $1\spr[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign $1\spr[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0101110 assign { } { } assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } @@ -197199,20 +196739,26 @@ module \dec_a sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:126099.3-126109.6" - process $proc$libresoc.v:126099$4803 + attribute \src "libresoc.v:125804.3-125822.6" + process $proc$libresoc.v:125804$4787 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:126100.5-126100.29" + attribute \src "libresoc.v:125805.5-125805.29" switch \initial - attribute \src "libresoc.v:126100.9-126100.17" + attribute \src "libresoc.v:125805.9-125805.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" switch \internal_op attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign $1\sprmap_spr_i[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign $1\sprmap_spr_i[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0101110 assign { } { } assign $1\sprmap_spr_i[9:0] \spr @@ -197222,23 +196768,31 @@ module \dec_a sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:126110.3-126121.6" - process $proc$libresoc.v:126110$4804 + attribute \src "libresoc.v:125823.3-125842.6" + process $proc$libresoc.v:125823$4788 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_a[9:0] $1\spr_a[9:0] assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] - attribute \src "libresoc.v:126111.5-126111.29" + attribute \src "libresoc.v:125824.5-125824.29" switch \initial - attribute \src "libresoc.v:126111.9-126111.17" + attribute \src "libresoc.v:125824.9-125824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" switch \internal_op attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign $1\spr_a[9:0] 10'0000000000 + assign $1\spr_a_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign $1\spr_a[9:0] 10'0000000000 + assign $1\spr_a_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0101110 assign { } { } assign { } { } @@ -197251,66 +196805,66 @@ module \dec_a update \spr_a $0\spr_a[9:0] update \spr_a_ok $0\spr_a_ok[0:0] end - connect \$9 $or$libresoc.v:125994$4780_Y - connect \$11 $and$libresoc.v:125995$4781_Y - connect \$13 $or$libresoc.v:125996$4782_Y - connect \$15 $eq$libresoc.v:125997$4783_Y - connect \$17 $eq$libresoc.v:125998$4784_Y - connect \$1 $eq$libresoc.v:125999$4785_Y - connect \$19 $eq$libresoc.v:126000$4786_Y - connect \$21 $ne$libresoc.v:126001$4787_Y - connect \$23 $ne$libresoc.v:126002$4788_Y - connect \$25 $or$libresoc.v:126003$4789_Y - connect \$27 $and$libresoc.v:126004$4790_Y - connect \$29 $or$libresoc.v:126005$4791_Y - connect \$31 $eq$libresoc.v:126006$4792_Y - connect \$33 $not$libresoc.v:126007$4793_Y - connect \$35 $not$libresoc.v:126008$4794_Y - connect \$37 $and$libresoc.v:126009$4795_Y - connect \$3 $eq$libresoc.v:126010$4796_Y - connect \$5 $ne$libresoc.v:126011$4797_Y - connect \$7 $ne$libresoc.v:126012$4798_Y + connect \$9 $or$libresoc.v:125691$4764_Y + connect \$11 $and$libresoc.v:125692$4765_Y + connect \$13 $or$libresoc.v:125693$4766_Y + connect \$15 $eq$libresoc.v:125694$4767_Y + connect \$17 $eq$libresoc.v:125695$4768_Y + connect \$1 $eq$libresoc.v:125696$4769_Y + connect \$19 $eq$libresoc.v:125697$4770_Y + connect \$21 $ne$libresoc.v:125698$4771_Y + connect \$23 $ne$libresoc.v:125699$4772_Y + connect \$25 $or$libresoc.v:125700$4773_Y + connect \$27 $and$libresoc.v:125701$4774_Y + connect \$29 $or$libresoc.v:125702$4775_Y + connect \$31 $eq$libresoc.v:125703$4776_Y + connect \$33 $not$libresoc.v:125704$4777_Y + connect \$35 $not$libresoc.v:125705$4778_Y + connect \$37 $and$libresoc.v:125706$4779_Y + connect \$3 $eq$libresoc.v:125707$4780_Y + connect \$5 $ne$libresoc.v:125708$4781_Y + connect \$7 $ne$libresoc.v:125709$4782_Y connect \rs \RS connect \ra \RA end -attribute \src "libresoc.v:126128.1-126173.10" +attribute \src "libresoc.v:125849.1-125894.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_ai" attribute \generator "nMigen" module \dec_ai - attribute \src "libresoc.v:126162.3-126171.6" + attribute \src "libresoc.v:125883.3-125892.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:126129.7-126129.20" + attribute \src "libresoc.v:125850.7-125850.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126162.3-126171.6" + attribute \src "libresoc.v:125883.3-125892.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:126157.17-126157.107" - wire $and$libresoc.v:126157$4806_Y - attribute \src "libresoc.v:126160.17-126160.107" - wire $and$libresoc.v:126160$4809_Y - attribute \src "libresoc.v:126158.17-126158.111" - wire $eq$libresoc.v:126158$4807_Y - attribute \src "libresoc.v:126159.17-126159.108" - wire $eq$libresoc.v:126159$4808_Y - attribute \src "libresoc.v:126161.17-126161.110" - wire $eq$libresoc.v:126161$4810_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "libresoc.v:125878.17-125878.107" + wire $and$libresoc.v:125878$4790_Y + attribute \src "libresoc.v:125881.17-125881.107" + wire $and$libresoc.v:125881$4793_Y + attribute \src "libresoc.v:125879.17-125879.111" + wire $eq$libresoc.v:125879$4791_Y + attribute \src "libresoc.v:125880.17-125880.108" + wire $eq$libresoc.v:125880$4792_Y + attribute \src "libresoc.v:125882.17-125882.110" + wire $eq$libresoc.v:125882$4794_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire output 2 \immz_out - attribute \src "libresoc.v:126129.7-126129.15" + attribute \src "libresoc.v:125850.7-125850.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -197318,12 +196872,12 @@ module \dec_ai attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire input 4 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $and $and$libresoc.v:126157$4806 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + cell $and $and$libresoc.v:125878$4790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197331,10 +196885,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:126157$4806_Y + connect \Y $and$libresoc.v:125878$4790_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:126160$4809 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + cell $and $and$libresoc.v:125881$4793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197342,10 +196896,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:126160$4809_Y + connect \Y $and$libresoc.v:125881$4793_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126158$4807 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + cell $eq $eq$libresoc.v:125879$4791 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -197353,10 +196907,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126158$4807_Y + connect \Y $eq$libresoc.v:125879$4791_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126159$4808 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + cell $eq $eq$libresoc.v:125880$4792 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -197364,10 +196918,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:126159$4808_Y + connect \Y $eq$libresoc.v:125880$4792_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $eq $eq$libresoc.v:126161$4810 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + cell $eq $eq$libresoc.v:125882$4794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197375,28 +196929,28 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:126161$4810_Y + connect \Y $eq$libresoc.v:125882$4794_Y end - attribute \src "libresoc.v:126129.7-126129.20" - process $proc$libresoc.v:126129$4812 + attribute \src "libresoc.v:125850.7-125850.20" + process $proc$libresoc.v:125850$4796 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126162.3-126171.6" - process $proc$libresoc.v:126162$4811 + attribute \src "libresoc.v:125883.3-125892.6" + process $proc$libresoc.v:125883$4795 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:126163.5-126163.29" + attribute \src "libresoc.v:125884.5-125884.29" switch \initial - attribute \src "libresoc.v:126163.9-126163.17" + attribute \src "libresoc.v:125884.9-125884.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -197408,51 +196962,51 @@ module \dec_ai sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:126157$4806_Y - connect \$1 $eq$libresoc.v:126158$4807_Y - connect \$3 $eq$libresoc.v:126159$4808_Y - connect \$5 $and$libresoc.v:126160$4809_Y - connect \$7 $eq$libresoc.v:126161$4810_Y + connect \$9 $and$libresoc.v:125878$4790_Y + connect \$1 $eq$libresoc.v:125879$4791_Y + connect \$3 $eq$libresoc.v:125880$4792_Y + connect \$5 $and$libresoc.v:125881$4793_Y + connect \$7 $eq$libresoc.v:125882$4794_Y connect \ra \ALU_RA end -attribute \src "libresoc.v:126177.1-126222.10" +attribute \src "libresoc.v:125898.1-125943.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_ai" attribute \generator "nMigen" module \dec_ai$148 - attribute \src "libresoc.v:126211.3-126220.6" + attribute \src "libresoc.v:125932.3-125941.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:126178.7-126178.20" + attribute \src "libresoc.v:125899.7-125899.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126211.3-126220.6" + attribute \src "libresoc.v:125932.3-125941.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:126206.17-126206.107" - wire $and$libresoc.v:126206$4813_Y - attribute \src "libresoc.v:126209.17-126209.107" - wire $and$libresoc.v:126209$4816_Y - attribute \src "libresoc.v:126207.17-126207.111" - wire $eq$libresoc.v:126207$4814_Y - attribute \src "libresoc.v:126208.17-126208.108" - wire $eq$libresoc.v:126208$4815_Y - attribute \src "libresoc.v:126210.17-126210.110" - wire $eq$libresoc.v:126210$4817_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "libresoc.v:125927.17-125927.107" + wire $and$libresoc.v:125927$4797_Y + attribute \src "libresoc.v:125930.17-125930.107" + wire $and$libresoc.v:125930$4800_Y + attribute \src "libresoc.v:125928.17-125928.111" + wire $eq$libresoc.v:125928$4798_Y + attribute \src "libresoc.v:125929.17-125929.108" + wire $eq$libresoc.v:125929$4799_Y + attribute \src "libresoc.v:125931.17-125931.110" + wire $eq$libresoc.v:125931$4801_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire output 2 \immz_out - attribute \src "libresoc.v:126178.7-126178.15" + attribute \src "libresoc.v:125899.7-125899.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -197460,12 +197014,12 @@ module \dec_ai$148 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire input 4 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $and $and$libresoc.v:126206$4813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + cell $and $and$libresoc.v:125927$4797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197473,10 +197027,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:126206$4813_Y + connect \Y $and$libresoc.v:125927$4797_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:126209$4816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + cell $and $and$libresoc.v:125930$4800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197484,10 +197038,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:126209$4816_Y + connect \Y $and$libresoc.v:125930$4800_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126207$4814 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + cell $eq $eq$libresoc.v:125928$4798 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -197495,10 +197049,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126207$4814_Y + connect \Y $eq$libresoc.v:125928$4798_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126208$4815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + cell $eq $eq$libresoc.v:125929$4799 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -197506,10 +197060,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:126208$4815_Y + connect \Y $eq$libresoc.v:125929$4799_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $eq $eq$libresoc.v:126210$4817 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + cell $eq $eq$libresoc.v:125931$4801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197517,28 +197071,28 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:126210$4817_Y + connect \Y $eq$libresoc.v:125931$4801_Y end - attribute \src "libresoc.v:126178.7-126178.20" - process $proc$libresoc.v:126178$4819 + attribute \src "libresoc.v:125899.7-125899.20" + process $proc$libresoc.v:125899$4803 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126211.3-126220.6" - process $proc$libresoc.v:126211$4818 + attribute \src "libresoc.v:125932.3-125941.6" + process $proc$libresoc.v:125932$4802 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:126212.5-126212.29" + attribute \src "libresoc.v:125933.5-125933.29" switch \initial - attribute \src "libresoc.v:126212.9-126212.17" + attribute \src "libresoc.v:125933.9-125933.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -197550,51 +197104,51 @@ module \dec_ai$148 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:126206$4813_Y - connect \$1 $eq$libresoc.v:126207$4814_Y - connect \$3 $eq$libresoc.v:126208$4815_Y - connect \$5 $and$libresoc.v:126209$4816_Y - connect \$7 $eq$libresoc.v:126210$4817_Y + connect \$9 $and$libresoc.v:125927$4797_Y + connect \$1 $eq$libresoc.v:125928$4798_Y + connect \$3 $eq$libresoc.v:125929$4799_Y + connect \$5 $and$libresoc.v:125930$4800_Y + connect \$7 $eq$libresoc.v:125931$4801_Y connect \ra \LOGICAL_RA end -attribute \src "libresoc.v:126226.1-126271.10" +attribute \src "libresoc.v:125947.1-125992.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_ai" attribute \generator "nMigen" module \dec_ai$156 - attribute \src "libresoc.v:126260.3-126269.6" + attribute \src "libresoc.v:125981.3-125990.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:126227.7-126227.20" + attribute \src "libresoc.v:125948.7-125948.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126260.3-126269.6" + attribute \src "libresoc.v:125981.3-125990.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:126255.17-126255.107" - wire $and$libresoc.v:126255$4820_Y - attribute \src "libresoc.v:126258.17-126258.107" - wire $and$libresoc.v:126258$4823_Y - attribute \src "libresoc.v:126256.17-126256.111" - wire $eq$libresoc.v:126256$4821_Y - attribute \src "libresoc.v:126257.17-126257.108" - wire $eq$libresoc.v:126257$4822_Y - attribute \src "libresoc.v:126259.17-126259.110" - wire $eq$libresoc.v:126259$4824_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "libresoc.v:125976.17-125976.107" + wire $and$libresoc.v:125976$4804_Y + attribute \src "libresoc.v:125979.17-125979.107" + wire $and$libresoc.v:125979$4807_Y + attribute \src "libresoc.v:125977.17-125977.111" + wire $eq$libresoc.v:125977$4805_Y + attribute \src "libresoc.v:125978.17-125978.108" + wire $eq$libresoc.v:125978$4806_Y + attribute \src "libresoc.v:125980.17-125980.110" + wire $eq$libresoc.v:125980$4808_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire output 2 \immz_out - attribute \src "libresoc.v:126227.7-126227.15" + attribute \src "libresoc.v:125948.7-125948.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -197602,12 +197156,12 @@ module \dec_ai$156 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire input 4 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $and $and$libresoc.v:126255$4820 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + cell $and $and$libresoc.v:125976$4804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197615,10 +197169,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:126255$4820_Y + connect \Y $and$libresoc.v:125976$4804_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:126258$4823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + cell $and $and$libresoc.v:125979$4807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197626,10 +197180,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:126258$4823_Y + connect \Y $and$libresoc.v:125979$4807_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126256$4821 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + cell $eq $eq$libresoc.v:125977$4805 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -197637,10 +197191,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126256$4821_Y + connect \Y $eq$libresoc.v:125977$4805_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126257$4822 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + cell $eq $eq$libresoc.v:125978$4806 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -197648,10 +197202,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:126257$4822_Y + connect \Y $eq$libresoc.v:125978$4806_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $eq $eq$libresoc.v:126259$4824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + cell $eq $eq$libresoc.v:125980$4808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197659,28 +197213,28 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:126259$4824_Y + connect \Y $eq$libresoc.v:125980$4808_Y end - attribute \src "libresoc.v:126227.7-126227.20" - process $proc$libresoc.v:126227$4826 + attribute \src "libresoc.v:125948.7-125948.20" + process $proc$libresoc.v:125948$4810 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126260.3-126269.6" - process $proc$libresoc.v:126260$4825 + attribute \src "libresoc.v:125981.3-125990.6" + process $proc$libresoc.v:125981$4809 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:126261.5-126261.29" + attribute \src "libresoc.v:125982.5-125982.29" switch \initial - attribute \src "libresoc.v:126261.9-126261.17" + attribute \src "libresoc.v:125982.9-125982.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -197692,51 +197246,51 @@ module \dec_ai$156 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:126255$4820_Y - connect \$1 $eq$libresoc.v:126256$4821_Y - connect \$3 $eq$libresoc.v:126257$4822_Y - connect \$5 $and$libresoc.v:126258$4823_Y - connect \$7 $eq$libresoc.v:126259$4824_Y + connect \$9 $and$libresoc.v:125976$4804_Y + connect \$1 $eq$libresoc.v:125977$4805_Y + connect \$3 $eq$libresoc.v:125978$4806_Y + connect \$5 $and$libresoc.v:125979$4807_Y + connect \$7 $eq$libresoc.v:125980$4808_Y connect \ra \DIV_RA end -attribute \src "libresoc.v:126275.1-126320.10" +attribute \src "libresoc.v:125996.1-126041.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_ai" attribute \generator "nMigen" module \dec_ai$169 - attribute \src "libresoc.v:126309.3-126318.6" + attribute \src "libresoc.v:126030.3-126039.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:126276.7-126276.20" + attribute \src "libresoc.v:125997.7-125997.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126309.3-126318.6" + attribute \src "libresoc.v:126030.3-126039.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:126304.17-126304.107" - wire $and$libresoc.v:126304$4827_Y - attribute \src "libresoc.v:126307.17-126307.107" - wire $and$libresoc.v:126307$4830_Y - attribute \src "libresoc.v:126305.17-126305.111" - wire $eq$libresoc.v:126305$4828_Y - attribute \src "libresoc.v:126306.17-126306.108" - wire $eq$libresoc.v:126306$4829_Y - attribute \src "libresoc.v:126308.17-126308.110" - wire $eq$libresoc.v:126308$4831_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "libresoc.v:126025.17-126025.107" + wire $and$libresoc.v:126025$4811_Y + attribute \src "libresoc.v:126028.17-126028.107" + wire $and$libresoc.v:126028$4814_Y + attribute \src "libresoc.v:126026.17-126026.111" + wire $eq$libresoc.v:126026$4812_Y + attribute \src "libresoc.v:126027.17-126027.108" + wire $eq$libresoc.v:126027$4813_Y + attribute \src "libresoc.v:126029.17-126029.110" + wire $eq$libresoc.v:126029$4815_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire output 2 \immz_out - attribute \src "libresoc.v:126276.7-126276.15" + attribute \src "libresoc.v:125997.7-125997.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -197744,12 +197298,12 @@ module \dec_ai$169 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire input 4 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $and $and$libresoc.v:126304$4827 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + cell $and $and$libresoc.v:126025$4811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197757,10 +197311,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:126304$4827_Y + connect \Y $and$libresoc.v:126025$4811_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:126307$4830 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + cell $and $and$libresoc.v:126028$4814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197768,10 +197322,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:126307$4830_Y + connect \Y $and$libresoc.v:126028$4814_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126305$4828 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + cell $eq $eq$libresoc.v:126026$4812 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -197779,10 +197333,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126305$4828_Y + connect \Y $eq$libresoc.v:126026$4812_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126306$4829 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + cell $eq $eq$libresoc.v:126027$4813 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -197790,10 +197344,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:126306$4829_Y + connect \Y $eq$libresoc.v:126027$4813_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $eq $eq$libresoc.v:126308$4831 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + cell $eq $eq$libresoc.v:126029$4815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197801,28 +197355,28 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:126308$4831_Y + connect \Y $eq$libresoc.v:126029$4815_Y end - attribute \src "libresoc.v:126276.7-126276.20" - process $proc$libresoc.v:126276$4833 + attribute \src "libresoc.v:125997.7-125997.20" + process $proc$libresoc.v:125997$4817 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126309.3-126318.6" - process $proc$libresoc.v:126309$4832 + attribute \src "libresoc.v:126030.3-126039.6" + process $proc$libresoc.v:126030$4816 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:126310.5-126310.29" + attribute \src "libresoc.v:126031.5-126031.29" switch \initial - attribute \src "libresoc.v:126310.9-126310.17" + attribute \src "libresoc.v:126031.9-126031.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -197834,67 +197388,67 @@ module \dec_ai$169 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:126304$4827_Y - connect \$1 $eq$libresoc.v:126305$4828_Y - connect \$3 $eq$libresoc.v:126306$4829_Y - connect \$5 $and$libresoc.v:126307$4830_Y - connect \$7 $eq$libresoc.v:126308$4831_Y + connect \$9 $and$libresoc.v:126025$4811_Y + connect \$1 $eq$libresoc.v:126026$4812_Y + connect \$3 $eq$libresoc.v:126027$4813_Y + connect \$5 $and$libresoc.v:126028$4814_Y + connect \$7 $eq$libresoc.v:126029$4815_Y connect \ra \LDST_RA end -attribute \src "libresoc.v:126324.1-126522.10" +attribute \src "libresoc.v:126045.1-126243.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b" attribute \generator "nMigen" module \dec_b - attribute \src "libresoc.v:126486.3-126503.6" + attribute \src "libresoc.v:126207.3-126224.6" wire width 3 $0\fast_b[2:0] - attribute \src "libresoc.v:126504.3-126521.6" + attribute \src "libresoc.v:126225.3-126242.6" wire $0\fast_b_ok[0:0] - attribute \src "libresoc.v:126325.7-126325.20" + attribute \src "libresoc.v:126046.7-126046.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126456.3-126470.6" + attribute \src "libresoc.v:126177.3-126191.6" wire width 7 $0\reg_b[6:0] - attribute \src "libresoc.v:126471.3-126485.6" + attribute \src "libresoc.v:126192.3-126206.6" wire $0\reg_b_ok[0:0] - attribute \src "libresoc.v:126486.3-126503.6" + attribute \src "libresoc.v:126207.3-126224.6" wire width 3 $1\fast_b[2:0] - attribute \src "libresoc.v:126504.3-126521.6" + attribute \src "libresoc.v:126225.3-126242.6" wire $1\fast_b_ok[0:0] - attribute \src "libresoc.v:126456.3-126470.6" + attribute \src "libresoc.v:126177.3-126191.6" wire width 7 $1\reg_b[6:0] - attribute \src "libresoc.v:126471.3-126485.6" + attribute \src "libresoc.v:126192.3-126206.6" wire $1\reg_b_ok[0:0] - attribute \src "libresoc.v:126486.3-126503.6" + attribute \src "libresoc.v:126207.3-126224.6" wire width 3 $2\fast_b[2:0] - attribute \src "libresoc.v:126504.3-126521.6" + attribute \src "libresoc.v:126225.3-126242.6" wire $2\fast_b_ok[0:0] - attribute \src "libresoc.v:126450.17-126450.117" - wire $eq$libresoc.v:126450$4834_Y - attribute \src "libresoc.v:126454.17-126454.117" - wire $eq$libresoc.v:126454$4840_Y - attribute \src "libresoc.v:126452.17-126452.100" - wire width 7 $extend$libresoc.v:126452$4836_Y - attribute \src "libresoc.v:126453.17-126453.100" - wire width 7 $extend$libresoc.v:126453$4838_Y - attribute \src "libresoc.v:126451.18-126451.108" - wire $not$libresoc.v:126451$4835_Y - attribute \src "libresoc.v:126455.17-126455.107" - wire $not$libresoc.v:126455$4841_Y - attribute \src "libresoc.v:126452.17-126452.100" - wire width 7 $pos$libresoc.v:126452$4837_Y - attribute \src "libresoc.v:126453.17-126453.100" - wire width 7 $pos$libresoc.v:126453$4839_Y + attribute \src "libresoc.v:126171.17-126171.117" + wire $eq$libresoc.v:126171$4818_Y + attribute \src "libresoc.v:126175.17-126175.117" + wire $eq$libresoc.v:126175$4824_Y + attribute \src "libresoc.v:126173.17-126173.100" + wire width 7 $extend$libresoc.v:126173$4820_Y + attribute \src "libresoc.v:126174.17-126174.100" + wire width 7 $extend$libresoc.v:126174$4822_Y + attribute \src "libresoc.v:126172.18-126172.108" + wire $not$libresoc.v:126172$4819_Y + attribute \src "libresoc.v:126176.17-126176.107" + wire $not$libresoc.v:126176$4825_Y + attribute \src "libresoc.v:126173.17-126173.100" + wire width 7 $pos$libresoc.v:126173$4821_Y + attribute \src "libresoc.v:126174.17-126174.100" + wire width 7 $pos$libresoc.v:126174$4823_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 7 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 7 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 7 \RB @@ -197902,11 +197456,11 @@ module \dec_b wire width 5 input 6 \RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 input 8 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 4 \fast_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \fast_b_ok - attribute \src "libresoc.v:126325.7-126325.15" + attribute \src "libresoc.v:126046.7-126046.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -197985,9 +197539,9 @@ module \dec_b attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 9 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 2 \reg_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \reg_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -198004,10 +197558,10 @@ module \dec_b attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" wire width 4 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" - cell $eq $eq$libresoc.v:126450$4834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + cell $eq $eq$libresoc.v:126171$4818 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -198015,10 +197569,10 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:126450$4834_Y + connect \Y $eq$libresoc.v:126171$4818_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" - cell $eq $eq$libresoc.v:126454$4840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + cell $eq $eq$libresoc.v:126175$4824 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -198026,76 +197580,76 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:126454$4840_Y + connect \Y $eq$libresoc.v:126175$4824_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126452$4836 + cell $pos $extend$libresoc.v:126173$4820 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RB - connect \Y $extend$libresoc.v:126452$4836_Y + connect \Y $extend$libresoc.v:126173$4820_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126453$4838 + cell $pos $extend$libresoc.v:126174$4822 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RS - connect \Y $extend$libresoc.v:126453$4838_Y + connect \Y $extend$libresoc.v:126174$4822_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" - cell $not $not$libresoc.v:126451$4835 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" + cell $not $not$libresoc.v:126172$4819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:126451$4835_Y + connect \Y $not$libresoc.v:126172$4819_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" - cell $not $not$libresoc.v:126455$4841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" + cell $not $not$libresoc.v:126176$4825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:126455$4841_Y + connect \Y $not$libresoc.v:126176$4825_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126452$4837 + cell $pos $pos$libresoc.v:126173$4821 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:126452$4836_Y - connect \Y $pos$libresoc.v:126452$4837_Y + connect \A $extend$libresoc.v:126173$4820_Y + connect \Y $pos$libresoc.v:126173$4821_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126453$4839 + cell $pos $pos$libresoc.v:126174$4823 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:126453$4838_Y - connect \Y $pos$libresoc.v:126453$4839_Y + connect \A $extend$libresoc.v:126174$4822_Y + connect \Y $pos$libresoc.v:126174$4823_Y end - attribute \src "libresoc.v:126325.7-126325.20" - process $proc$libresoc.v:126325$4846 + attribute \src "libresoc.v:126046.7-126046.20" + process $proc$libresoc.v:126046$4830 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126456.3-126470.6" - process $proc$libresoc.v:126456$4842 + attribute \src "libresoc.v:126177.3-126191.6" + process $proc$libresoc.v:126177$4826 assign { } { } assign { } { } assign $0\reg_b[6:0] $1\reg_b[6:0] - attribute \src "libresoc.v:126457.5-126457.29" + attribute \src "libresoc.v:126178.5-126178.29" switch \initial - attribute \src "libresoc.v:126457.9-126457.17" + attribute \src "libresoc.v:126178.9-126178.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -198111,18 +197665,18 @@ module \dec_b sync always update \reg_b $0\reg_b[6:0] end - attribute \src "libresoc.v:126471.3-126485.6" - process $proc$libresoc.v:126471$4843 + attribute \src "libresoc.v:126192.3-126206.6" + process $proc$libresoc.v:126192$4827 assign { } { } assign { } { } assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] - attribute \src "libresoc.v:126472.5-126472.29" + attribute \src "libresoc.v:126193.5-126193.29" switch \initial - attribute \src "libresoc.v:126472.9-126472.17" + attribute \src "libresoc.v:126193.9-126193.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -198138,24 +197692,24 @@ module \dec_b sync always update \reg_b_ok $0\reg_b_ok[0:0] end - attribute \src "libresoc.v:126486.3-126503.6" - process $proc$libresoc.v:126486$4844 + attribute \src "libresoc.v:126207.3-126224.6" + process $proc$libresoc.v:126207$4828 assign { } { } assign { } { } assign $0\fast_b[2:0] $1\fast_b[2:0] - attribute \src "libresoc.v:126487.5-126487.29" + attribute \src "libresoc.v:126208.5-126208.29" switch \initial - attribute \src "libresoc.v:126487.9-126487.17" + attribute \src "libresoc.v:126208.9-126208.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast_b[2:0] $2\fast_b[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" switch { \XL_XO [5] \$7 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -198174,24 +197728,24 @@ module \dec_b sync always update \fast_b $0\fast_b[2:0] end - attribute \src "libresoc.v:126504.3-126521.6" - process $proc$libresoc.v:126504$4845 + attribute \src "libresoc.v:126225.3-126242.6" + process $proc$libresoc.v:126225$4829 assign { } { } assign { } { } assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] - attribute \src "libresoc.v:126505.5-126505.29" + attribute \src "libresoc.v:126226.5-126226.29" switch \initial - attribute \src "libresoc.v:126505.9-126505.17" + attribute \src "libresoc.v:126226.9-126226.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" switch { \XL_XO [5] \$11 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -198210,103 +197764,103 @@ module \dec_b sync always update \fast_b_ok $0\fast_b_ok[0:0] end - connect \$9 $eq$libresoc.v:126450$4834_Y - connect \$11 $not$libresoc.v:126451$4835_Y - connect \$1 $pos$libresoc.v:126452$4837_Y - connect \$3 $pos$libresoc.v:126453$4839_Y - connect \$5 $eq$libresoc.v:126454$4840_Y - connect \$7 $not$libresoc.v:126455$4841_Y + connect \$9 $eq$libresoc.v:126171$4818_Y + connect \$11 $not$libresoc.v:126172$4819_Y + connect \$1 $pos$libresoc.v:126173$4821_Y + connect \$3 $pos$libresoc.v:126174$4823_Y + connect \$5 $eq$libresoc.v:126175$4824_Y + connect \$7 $not$libresoc.v:126176$4825_Y end -attribute \src "libresoc.v:126526.1-126779.10" +attribute \src "libresoc.v:126247.1-126584.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi" attribute \generator "nMigen" module \dec_bi - attribute \src "libresoc.v:126753.3-126763.6" + attribute \src "libresoc.v:126514.3-126544.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:126764.3-126774.6" + attribute \src "libresoc.v:126545.3-126579.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:126615.3-126661.6" + attribute \src "libresoc.v:126336.3-126382.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:126662.3-126708.6" + attribute \src "libresoc.v:126383.3-126429.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:126527.7-126527.20" + attribute \src "libresoc.v:126248.7-126248.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126742.3-126752.6" + attribute \src "libresoc.v:126487.3-126513.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:126709.3-126719.6" + attribute \src "libresoc.v:126430.3-126444.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:126720.3-126730.6" + attribute \src "libresoc.v:126445.3-126463.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:126731.3-126741.6" + attribute \src "libresoc.v:126464.3-126486.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:126753.3-126763.6" + attribute \src "libresoc.v:126514.3-126544.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:126764.3-126774.6" + attribute \src "libresoc.v:126545.3-126579.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:126615.3-126661.6" + attribute \src "libresoc.v:126336.3-126382.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:126662.3-126708.6" + attribute \src "libresoc.v:126383.3-126429.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126742.3-126752.6" + attribute \src "libresoc.v:126487.3-126513.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:126709.3-126719.6" + attribute \src "libresoc.v:126430.3-126444.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:126720.3-126730.6" + attribute \src "libresoc.v:126445.3-126463.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:126731.3-126741.6" + attribute \src "libresoc.v:126464.3-126486.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:126605.17-126605.104" - wire width 64 $extend$libresoc.v:126605$4847_Y - attribute \src "libresoc.v:126606.18-126606.107" - wire width 64 $extend$libresoc.v:126606$4849_Y - attribute \src "libresoc.v:126609.17-126609.104" - wire width 64 $extend$libresoc.v:126609$4853_Y - attribute \src "libresoc.v:126613.17-126613.102" - wire width 64 $extend$libresoc.v:126613$4858_Y - attribute \src "libresoc.v:126605.17-126605.104" - wire width 64 $pos$libresoc.v:126605$4848_Y - attribute \src "libresoc.v:126606.18-126606.107" - wire width 64 $pos$libresoc.v:126606$4850_Y - attribute \src "libresoc.v:126609.17-126609.104" - wire width 64 $pos$libresoc.v:126609$4854_Y - attribute \src "libresoc.v:126613.17-126613.102" - wire width 64 $pos$libresoc.v:126613$4859_Y - attribute \src "libresoc.v:126607.18-126607.114" - wire width 47 $sshl$libresoc.v:126607$4851_Y - attribute \src "libresoc.v:126608.18-126608.113" - wire width 27 $sshl$libresoc.v:126608$4852_Y - attribute \src "libresoc.v:126610.18-126610.113" - wire width 17 $sshl$libresoc.v:126610$4855_Y - attribute \src "libresoc.v:126611.18-126611.113" - wire width 17 $sshl$libresoc.v:126611$4856_Y - attribute \src "libresoc.v:126612.17-126612.109" - wire width 47 $sshl$libresoc.v:126612$4857_Y + attribute \src "libresoc.v:126326.17-126326.104" + wire width 64 $extend$libresoc.v:126326$4831_Y + attribute \src "libresoc.v:126327.18-126327.107" + wire width 64 $extend$libresoc.v:126327$4833_Y + attribute \src "libresoc.v:126330.17-126330.104" + wire width 64 $extend$libresoc.v:126330$4837_Y + attribute \src "libresoc.v:126334.17-126334.102" + wire width 64 $extend$libresoc.v:126334$4842_Y + attribute \src "libresoc.v:126326.17-126326.104" + wire width 64 $pos$libresoc.v:126326$4832_Y + attribute \src "libresoc.v:126327.18-126327.107" + wire width 64 $pos$libresoc.v:126327$4834_Y + attribute \src "libresoc.v:126330.17-126330.104" + wire width 64 $pos$libresoc.v:126330$4838_Y + attribute \src "libresoc.v:126334.17-126334.102" + wire width 64 $pos$libresoc.v:126334$4843_Y + attribute \src "libresoc.v:126328.18-126328.114" + wire width 47 $sshl$libresoc.v:126328$4835_Y + attribute \src "libresoc.v:126329.18-126329.113" + wire width 27 $sshl$libresoc.v:126329$4836_Y + attribute \src "libresoc.v:126331.18-126331.113" + wire width 17 $sshl$libresoc.v:126331$4839_Y + attribute \src "libresoc.v:126332.18-126332.113" + wire width 17 $sshl$libresoc.v:126332$4840_Y + attribute \src "libresoc.v:126333.17-126333.109" + wire width 47 $sshl$libresoc.v:126333$4841_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 @@ -198324,17 +197878,17 @@ module \dec_bi wire width 16 input 4 \ALU_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok - attribute \src "libresoc.v:126527.7-126527.15" + attribute \src "libresoc.v:126248.7-126248.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -198351,80 +197905,80 @@ module \dec_bi attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126605$4847 + cell $pos $extend$libresoc.v:126326$4831 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \ALU_sh - connect \Y $extend$libresoc.v:126605$4847_Y + connect \Y $extend$libresoc.v:126326$4831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126606$4849 + cell $pos $extend$libresoc.v:126327$4833 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \ALU_SH32 - connect \Y $extend$libresoc.v:126606$4849_Y + connect \Y $extend$libresoc.v:126327$4833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126609$4853 + cell $pos $extend$libresoc.v:126330$4837 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \ALU_UI - connect \Y $extend$libresoc.v:126609$4853_Y + connect \Y $extend$libresoc.v:126330$4837_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $extend$libresoc.v:126613$4858 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $pos $extend$libresoc.v:126334$4842 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:126613$4858_Y + connect \Y $extend$libresoc.v:126334$4842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126605$4848 + cell $pos $pos$libresoc.v:126326$4832 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126605$4847_Y - connect \Y $pos$libresoc.v:126605$4848_Y + connect \A $extend$libresoc.v:126326$4831_Y + connect \Y $pos$libresoc.v:126326$4832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126606$4850 + cell $pos $pos$libresoc.v:126327$4834 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126606$4849_Y - connect \Y $pos$libresoc.v:126606$4850_Y + connect \A $extend$libresoc.v:126327$4833_Y + connect \Y $pos$libresoc.v:126327$4834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126609$4854 + cell $pos $pos$libresoc.v:126330$4838 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126609$4853_Y - connect \Y $pos$libresoc.v:126609$4854_Y + connect \A $extend$libresoc.v:126330$4837_Y + connect \Y $pos$libresoc.v:126330$4838_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $pos$libresoc.v:126613$4859 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $pos $pos$libresoc.v:126334$4843 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126613$4858_Y - connect \Y $pos$libresoc.v:126613$4859_Y + connect \A $extend$libresoc.v:126334$4842_Y + connect \Y $pos$libresoc.v:126334$4843_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:126607$4851 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" + cell $sshl $sshl$libresoc.v:126328$4835 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198432,10 +197986,10 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ALU_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:126607$4851_Y + connect \Y $sshl$libresoc.v:126328$4835_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:126608$4852 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" + cell $sshl $sshl$libresoc.v:126329$4836 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -198443,10 +197997,10 @@ module \dec_bi parameter \Y_WIDTH 27 connect \A \ALU_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:126608$4852_Y + connect \Y $sshl$libresoc.v:126329$4836_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:126610$4855 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" + cell $sshl $sshl$libresoc.v:126331$4839 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198454,10 +198008,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:126610$4855_Y + connect \Y $sshl$libresoc.v:126331$4839_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" - cell $sshl $sshl$libresoc.v:126611$4856 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" + cell $sshl $sshl$libresoc.v:126332$4840 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198465,10 +198019,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:126611$4856_Y + connect \Y $sshl$libresoc.v:126332$4840_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $sshl $sshl$libresoc.v:126612$4857 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $sshl $sshl$libresoc.v:126333$4841 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198476,28 +198030,28 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:126612$4857_Y + connect \Y $sshl$libresoc.v:126333$4841_Y end - attribute \src "libresoc.v:126527.7-126527.20" - process $proc$libresoc.v:126527$4868 + attribute \src "libresoc.v:126248.7-126248.20" + process $proc$libresoc.v:126248$4852 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126615.3-126661.6" - process $proc$libresoc.v:126615$4860 + attribute \src "libresoc.v:126336.3-126382.6" + process $proc$libresoc.v:126336$4844 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:126616.5-126616.29" + attribute \src "libresoc.v:126337.5-126337.29" switch \initial - attribute \src "libresoc.v:126616.9-126616.17" + attribute \src "libresoc.v:126337.9-126337.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -198545,18 +198099,18 @@ module \dec_bi sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:126662.3-126708.6" - process $proc$libresoc.v:126662$4861 + attribute \src "libresoc.v:126383.3-126429.6" + process $proc$libresoc.v:126383$4845 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126663.5-126663.29" + attribute \src "libresoc.v:126384.5-126384.29" switch \initial - attribute \src "libresoc.v:126663.9-126663.17" + attribute \src "libresoc.v:126384.9-126384.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -198604,20 +198158,23 @@ module \dec_bi sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:126709.3-126719.6" - process $proc$libresoc.v:126709$4862 + attribute \src "libresoc.v:126430.3-126444.6" + process $proc$libresoc.v:126430$4846 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:126710.5-126710.29" + attribute \src "libresoc.v:126431.5-126431.29" switch \initial - attribute \src "libresoc.v:126710.9-126710.17" + attribute \src "libresoc.v:126431.9-126431.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \ALU_SI @@ -198627,20 +198184,26 @@ module \dec_bi sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:126720.3-126730.6" - process $proc$libresoc.v:126720$4863 + attribute \src "libresoc.v:126445.3-126463.6" + process $proc$libresoc.v:126445$4847 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:126721.5-126721.29" + attribute \src "libresoc.v:126446.5-126446.29" switch \initial - attribute \src "libresoc.v:126721.9-126721.17" + attribute \src "libresoc.v:126446.9-126446.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] @@ -198650,20 +198213,29 @@ module \dec_bi sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:126731.3-126741.6" - process $proc$libresoc.v:126731$4864 + attribute \src "libresoc.v:126464.3-126486.6" + process $proc$libresoc.v:126464$4848 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:126732.5-126732.29" + attribute \src "libresoc.v:126465.5-126465.29" switch \initial - attribute \src "libresoc.v:126732.9-126732.17" + attribute \src "libresoc.v:126465.9-126465.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \ALU_UI @@ -198673,20 +198245,32 @@ module \dec_bi sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:126742.3-126752.6" - process $proc$libresoc.v:126742$4865 + attribute \src "libresoc.v:126487.3-126513.6" + process $proc$libresoc.v:126487$4849 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:126743.5-126743.29" + attribute \src "libresoc.v:126488.5-126488.29" switch \initial - attribute \src "libresoc.v:126743.9-126743.17" + attribute \src "libresoc.v:126488.9-126488.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] @@ -198696,20 +198280,35 @@ module \dec_bi sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:126753.3-126763.6" - process $proc$libresoc.v:126753$4866 + attribute \src "libresoc.v:126514.3-126544.6" + process $proc$libresoc.v:126514$4850 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:126754.5-126754.29" + attribute \src "libresoc.v:126515.5-126515.29" switch \initial - attribute \src "libresoc.v:126754.9-126754.17" + attribute \src "libresoc.v:126515.9-126515.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] @@ -198719,20 +198318,38 @@ module \dec_bi sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:126764.3-126774.6" - process $proc$libresoc.v:126764$4867 + attribute \src "libresoc.v:126545.3-126579.6" + process $proc$libresoc.v:126545$4851 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:126765.5-126765.29" + attribute \src "libresoc.v:126546.5-126546.29" switch \initial - attribute \src "libresoc.v:126765.9-126765.17" + attribute \src "libresoc.v:126546.9-126546.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] @@ -198742,111 +198359,111 @@ module \dec_bi sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:126605$4848_Y - connect \$11 $pos$libresoc.v:126606$4850_Y - connect \$14 $sshl$libresoc.v:126607$4851_Y - connect \$17 $sshl$libresoc.v:126608$4852_Y - connect \$1 $pos$libresoc.v:126609$4854_Y - connect \$20 $sshl$libresoc.v:126610$4855_Y - connect \$23 $sshl$libresoc.v:126611$4856_Y - connect \$4 $sshl$libresoc.v:126612$4857_Y - connect \$3 $pos$libresoc.v:126613$4859_Y + connect \$9 $pos$libresoc.v:126326$4832_Y + connect \$11 $pos$libresoc.v:126327$4834_Y + connect \$14 $sshl$libresoc.v:126328$4835_Y + connect \$17 $sshl$libresoc.v:126329$4836_Y + connect \$1 $pos$libresoc.v:126330$4838_Y + connect \$20 $sshl$libresoc.v:126331$4839_Y + connect \$23 $sshl$libresoc.v:126332$4840_Y + connect \$4 $sshl$libresoc.v:126333$4841_Y + connect \$3 $pos$libresoc.v:126334$4843_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:126783.1-127036.10" +attribute \src "libresoc.v:126588.1-126925.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi" attribute \generator "nMigen" module \dec_bi$144 - attribute \src "libresoc.v:127010.3-127020.6" + attribute \src "libresoc.v:126855.3-126885.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:127021.3-127031.6" + attribute \src "libresoc.v:126886.3-126920.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:126872.3-126918.6" + attribute \src "libresoc.v:126677.3-126723.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:126919.3-126965.6" + attribute \src "libresoc.v:126724.3-126770.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:126784.7-126784.20" + attribute \src "libresoc.v:126589.7-126589.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126999.3-127009.6" + attribute \src "libresoc.v:126828.3-126854.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:126966.3-126976.6" + attribute \src "libresoc.v:126771.3-126785.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:126977.3-126987.6" + attribute \src "libresoc.v:126786.3-126804.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:126988.3-126998.6" + attribute \src "libresoc.v:126805.3-126827.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:127010.3-127020.6" + attribute \src "libresoc.v:126855.3-126885.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:127021.3-127031.6" + attribute \src "libresoc.v:126886.3-126920.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:126872.3-126918.6" + attribute \src "libresoc.v:126677.3-126723.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:126919.3-126965.6" + attribute \src "libresoc.v:126724.3-126770.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126999.3-127009.6" + attribute \src "libresoc.v:126828.3-126854.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:126966.3-126976.6" + attribute \src "libresoc.v:126771.3-126785.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:126977.3-126987.6" + attribute \src "libresoc.v:126786.3-126804.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:126988.3-126998.6" + attribute \src "libresoc.v:126805.3-126827.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:126862.17-126862.107" - wire width 64 $extend$libresoc.v:126862$4869_Y - attribute \src "libresoc.v:126863.18-126863.110" - wire width 64 $extend$libresoc.v:126863$4871_Y - attribute \src "libresoc.v:126866.17-126866.107" - wire width 64 $extend$libresoc.v:126866$4875_Y - attribute \src "libresoc.v:126870.17-126870.102" - wire width 64 $extend$libresoc.v:126870$4880_Y - attribute \src "libresoc.v:126862.17-126862.107" - wire width 64 $pos$libresoc.v:126862$4870_Y - attribute \src "libresoc.v:126863.18-126863.110" - wire width 64 $pos$libresoc.v:126863$4872_Y - attribute \src "libresoc.v:126866.17-126866.107" - wire width 64 $pos$libresoc.v:126866$4876_Y - attribute \src "libresoc.v:126870.17-126870.102" - wire width 64 $pos$libresoc.v:126870$4881_Y - attribute \src "libresoc.v:126864.18-126864.117" - wire width 47 $sshl$libresoc.v:126864$4873_Y - attribute \src "libresoc.v:126865.18-126865.116" - wire width 27 $sshl$libresoc.v:126865$4874_Y - attribute \src "libresoc.v:126867.18-126867.116" - wire width 17 $sshl$libresoc.v:126867$4877_Y - attribute \src "libresoc.v:126868.18-126868.116" - wire width 17 $sshl$libresoc.v:126868$4878_Y - attribute \src "libresoc.v:126869.17-126869.109" - wire width 47 $sshl$libresoc.v:126869$4879_Y + attribute \src "libresoc.v:126667.17-126667.107" + wire width 64 $extend$libresoc.v:126667$4853_Y + attribute \src "libresoc.v:126668.18-126668.110" + wire width 64 $extend$libresoc.v:126668$4855_Y + attribute \src "libresoc.v:126671.17-126671.107" + wire width 64 $extend$libresoc.v:126671$4859_Y + attribute \src "libresoc.v:126675.17-126675.102" + wire width 64 $extend$libresoc.v:126675$4864_Y + attribute \src "libresoc.v:126667.17-126667.107" + wire width 64 $pos$libresoc.v:126667$4854_Y + attribute \src "libresoc.v:126668.18-126668.110" + wire width 64 $pos$libresoc.v:126668$4856_Y + attribute \src "libresoc.v:126671.17-126671.107" + wire width 64 $pos$libresoc.v:126671$4860_Y + attribute \src "libresoc.v:126675.17-126675.102" + wire width 64 $pos$libresoc.v:126675$4865_Y + attribute \src "libresoc.v:126669.18-126669.117" + wire width 47 $sshl$libresoc.v:126669$4857_Y + attribute \src "libresoc.v:126670.18-126670.116" + wire width 27 $sshl$libresoc.v:126670$4858_Y + attribute \src "libresoc.v:126672.18-126672.116" + wire width 17 $sshl$libresoc.v:126672$4861_Y + attribute \src "libresoc.v:126673.18-126673.116" + wire width 17 $sshl$libresoc.v:126673$4862_Y + attribute \src "libresoc.v:126674.17-126674.109" + wire width 47 $sshl$libresoc.v:126674$4863_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 @@ -198864,17 +198481,17 @@ module \dec_bi$144 wire width 16 input 4 \BRANCH_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok - attribute \src "libresoc.v:126784.7-126784.15" + attribute \src "libresoc.v:126589.7-126589.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -198891,80 +198508,80 @@ module \dec_bi$144 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126862$4869 + cell $pos $extend$libresoc.v:126667$4853 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \BRANCH_sh - connect \Y $extend$libresoc.v:126862$4869_Y + connect \Y $extend$libresoc.v:126667$4853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126863$4871 + cell $pos $extend$libresoc.v:126668$4855 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \BRANCH_SH32 - connect \Y $extend$libresoc.v:126863$4871_Y + connect \Y $extend$libresoc.v:126668$4855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126866$4875 + cell $pos $extend$libresoc.v:126671$4859 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \BRANCH_UI - connect \Y $extend$libresoc.v:126866$4875_Y + connect \Y $extend$libresoc.v:126671$4859_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $extend$libresoc.v:126870$4880 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $pos $extend$libresoc.v:126675$4864 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:126870$4880_Y + connect \Y $extend$libresoc.v:126675$4864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126862$4870 + cell $pos $pos$libresoc.v:126667$4854 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126862$4869_Y - connect \Y $pos$libresoc.v:126862$4870_Y + connect \A $extend$libresoc.v:126667$4853_Y + connect \Y $pos$libresoc.v:126667$4854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126863$4872 + cell $pos $pos$libresoc.v:126668$4856 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126863$4871_Y - connect \Y $pos$libresoc.v:126863$4872_Y + connect \A $extend$libresoc.v:126668$4855_Y + connect \Y $pos$libresoc.v:126668$4856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126866$4876 + cell $pos $pos$libresoc.v:126671$4860 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126866$4875_Y - connect \Y $pos$libresoc.v:126866$4876_Y + connect \A $extend$libresoc.v:126671$4859_Y + connect \Y $pos$libresoc.v:126671$4860_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $pos$libresoc.v:126870$4881 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $pos $pos$libresoc.v:126675$4865 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126870$4880_Y - connect \Y $pos$libresoc.v:126870$4881_Y + connect \A $extend$libresoc.v:126675$4864_Y + connect \Y $pos$libresoc.v:126675$4865_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:126864$4873 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" + cell $sshl $sshl$libresoc.v:126669$4857 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198972,10 +198589,10 @@ module \dec_bi$144 parameter \Y_WIDTH 47 connect \A \BRANCH_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:126864$4873_Y + connect \Y $sshl$libresoc.v:126669$4857_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:126865$4874 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" + cell $sshl $sshl$libresoc.v:126670$4858 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -198983,10 +198600,10 @@ module \dec_bi$144 parameter \Y_WIDTH 27 connect \A \BRANCH_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:126865$4874_Y + connect \Y $sshl$libresoc.v:126670$4858_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:126867$4877 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" + cell $sshl $sshl$libresoc.v:126672$4861 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198994,10 +198611,10 @@ module \dec_bi$144 parameter \Y_WIDTH 17 connect \A \BRANCH_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:126867$4877_Y + connect \Y $sshl$libresoc.v:126672$4861_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" - cell $sshl $sshl$libresoc.v:126868$4878 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" + cell $sshl $sshl$libresoc.v:126673$4862 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -199005,10 +198622,10 @@ module \dec_bi$144 parameter \Y_WIDTH 17 connect \A \BRANCH_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:126868$4878_Y + connect \Y $sshl$libresoc.v:126673$4862_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $sshl $sshl$libresoc.v:126869$4879 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $sshl $sshl$libresoc.v:126674$4863 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -199016,28 +198633,28 @@ module \dec_bi$144 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:126869$4879_Y + connect \Y $sshl$libresoc.v:126674$4863_Y end - attribute \src "libresoc.v:126784.7-126784.20" - process $proc$libresoc.v:126784$4890 + attribute \src "libresoc.v:126589.7-126589.20" + process $proc$libresoc.v:126589$4874 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126872.3-126918.6" - process $proc$libresoc.v:126872$4882 + attribute \src "libresoc.v:126677.3-126723.6" + process $proc$libresoc.v:126677$4866 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:126873.5-126873.29" + attribute \src "libresoc.v:126678.5-126678.29" switch \initial - attribute \src "libresoc.v:126873.9-126873.17" + attribute \src "libresoc.v:126678.9-126678.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -199085,18 +198702,18 @@ module \dec_bi$144 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:126919.3-126965.6" - process $proc$libresoc.v:126919$4883 + attribute \src "libresoc.v:126724.3-126770.6" + process $proc$libresoc.v:126724$4867 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126920.5-126920.29" + attribute \src "libresoc.v:126725.5-126725.29" switch \initial - attribute \src "libresoc.v:126920.9-126920.17" + attribute \src "libresoc.v:126725.9-126725.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -199144,20 +198761,23 @@ module \dec_bi$144 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:126966.3-126976.6" - process $proc$libresoc.v:126966$4884 + attribute \src "libresoc.v:126771.3-126785.6" + process $proc$libresoc.v:126771$4868 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:126967.5-126967.29" + attribute \src "libresoc.v:126772.5-126772.29" switch \initial - attribute \src "libresoc.v:126967.9-126967.17" + attribute \src "libresoc.v:126772.9-126772.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \BRANCH_SI @@ -199167,20 +198787,26 @@ module \dec_bi$144 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:126977.3-126987.6" - process $proc$libresoc.v:126977$4885 + attribute \src "libresoc.v:126786.3-126804.6" + process $proc$libresoc.v:126786$4869 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:126978.5-126978.29" + attribute \src "libresoc.v:126787.5-126787.29" switch \initial - attribute \src "libresoc.v:126978.9-126978.17" + attribute \src "libresoc.v:126787.9-126787.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] @@ -199190,20 +198816,29 @@ module \dec_bi$144 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:126988.3-126998.6" - process $proc$libresoc.v:126988$4886 + attribute \src "libresoc.v:126805.3-126827.6" + process $proc$libresoc.v:126805$4870 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:126989.5-126989.29" + attribute \src "libresoc.v:126806.5-126806.29" switch \initial - attribute \src "libresoc.v:126989.9-126989.17" + attribute \src "libresoc.v:126806.9-126806.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \BRANCH_UI @@ -199213,20 +198848,32 @@ module \dec_bi$144 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:126999.3-127009.6" - process $proc$libresoc.v:126999$4887 + attribute \src "libresoc.v:126828.3-126854.6" + process $proc$libresoc.v:126828$4871 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:127000.5-127000.29" + attribute \src "libresoc.v:126829.5-126829.29" switch \initial - attribute \src "libresoc.v:127000.9-127000.17" + attribute \src "libresoc.v:126829.9-126829.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] @@ -199236,20 +198883,35 @@ module \dec_bi$144 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:127010.3-127020.6" - process $proc$libresoc.v:127010$4888 + attribute \src "libresoc.v:126855.3-126885.6" + process $proc$libresoc.v:126855$4872 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:127011.5-127011.29" + attribute \src "libresoc.v:126856.5-126856.29" switch \initial - attribute \src "libresoc.v:127011.9-127011.17" + attribute \src "libresoc.v:126856.9-126856.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] @@ -199259,20 +198921,38 @@ module \dec_bi$144 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:127021.3-127031.6" - process $proc$libresoc.v:127021$4889 + attribute \src "libresoc.v:126886.3-126920.6" + process $proc$libresoc.v:126886$4873 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:127022.5-127022.29" + attribute \src "libresoc.v:126887.5-126887.29" switch \initial - attribute \src "libresoc.v:127022.9-127022.17" + attribute \src "libresoc.v:126887.9-126887.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] @@ -199282,111 +198962,111 @@ module \dec_bi$144 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:126862$4870_Y - connect \$11 $pos$libresoc.v:126863$4872_Y - connect \$14 $sshl$libresoc.v:126864$4873_Y - connect \$17 $sshl$libresoc.v:126865$4874_Y - connect \$1 $pos$libresoc.v:126866$4876_Y - connect \$20 $sshl$libresoc.v:126867$4877_Y - connect \$23 $sshl$libresoc.v:126868$4878_Y - connect \$4 $sshl$libresoc.v:126869$4879_Y - connect \$3 $pos$libresoc.v:126870$4881_Y + connect \$9 $pos$libresoc.v:126667$4854_Y + connect \$11 $pos$libresoc.v:126668$4856_Y + connect \$14 $sshl$libresoc.v:126669$4857_Y + connect \$17 $sshl$libresoc.v:126670$4858_Y + connect \$1 $pos$libresoc.v:126671$4860_Y + connect \$20 $sshl$libresoc.v:126672$4861_Y + connect \$23 $sshl$libresoc.v:126673$4862_Y + connect \$4 $sshl$libresoc.v:126674$4863_Y + connect \$3 $pos$libresoc.v:126675$4865_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:127040.1-127293.10" +attribute \src "libresoc.v:126929.1-127266.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi" attribute \generator "nMigen" module \dec_bi$149 - attribute \src "libresoc.v:127267.3-127277.6" + attribute \src "libresoc.v:127196.3-127226.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:127278.3-127288.6" + attribute \src "libresoc.v:127227.3-127261.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:127129.3-127175.6" + attribute \src "libresoc.v:127018.3-127064.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:127176.3-127222.6" + attribute \src "libresoc.v:127065.3-127111.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:127041.7-127041.20" + attribute \src "libresoc.v:126930.7-126930.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127256.3-127266.6" + attribute \src "libresoc.v:127169.3-127195.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:127223.3-127233.6" + attribute \src "libresoc.v:127112.3-127126.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:127234.3-127244.6" + attribute \src "libresoc.v:127127.3-127145.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:127245.3-127255.6" + attribute \src "libresoc.v:127146.3-127168.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:127267.3-127277.6" + attribute \src "libresoc.v:127196.3-127226.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:127278.3-127288.6" + attribute \src "libresoc.v:127227.3-127261.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:127129.3-127175.6" + attribute \src "libresoc.v:127018.3-127064.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:127176.3-127222.6" + attribute \src "libresoc.v:127065.3-127111.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127256.3-127266.6" + attribute \src "libresoc.v:127169.3-127195.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:127223.3-127233.6" + attribute \src "libresoc.v:127112.3-127126.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:127234.3-127244.6" + attribute \src "libresoc.v:127127.3-127145.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:127245.3-127255.6" + attribute \src "libresoc.v:127146.3-127168.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:127119.17-127119.108" - wire width 64 $extend$libresoc.v:127119$4891_Y - attribute \src "libresoc.v:127120.18-127120.111" - wire width 64 $extend$libresoc.v:127120$4893_Y - attribute \src "libresoc.v:127123.17-127123.108" - wire width 64 $extend$libresoc.v:127123$4897_Y - attribute \src "libresoc.v:127127.17-127127.102" - wire width 64 $extend$libresoc.v:127127$4902_Y - attribute \src "libresoc.v:127119.17-127119.108" - wire width 64 $pos$libresoc.v:127119$4892_Y - attribute \src "libresoc.v:127120.18-127120.111" - wire width 64 $pos$libresoc.v:127120$4894_Y - attribute \src "libresoc.v:127123.17-127123.108" - wire width 64 $pos$libresoc.v:127123$4898_Y - attribute \src "libresoc.v:127127.17-127127.102" - wire width 64 $pos$libresoc.v:127127$4903_Y - attribute \src "libresoc.v:127121.18-127121.118" - wire width 47 $sshl$libresoc.v:127121$4895_Y - attribute \src "libresoc.v:127122.18-127122.117" - wire width 27 $sshl$libresoc.v:127122$4896_Y - attribute \src "libresoc.v:127124.18-127124.117" - wire width 17 $sshl$libresoc.v:127124$4899_Y - attribute \src "libresoc.v:127125.18-127125.117" - wire width 17 $sshl$libresoc.v:127125$4900_Y - attribute \src "libresoc.v:127126.17-127126.109" - wire width 47 $sshl$libresoc.v:127126$4901_Y + attribute \src "libresoc.v:127008.17-127008.108" + wire width 64 $extend$libresoc.v:127008$4875_Y + attribute \src "libresoc.v:127009.18-127009.111" + wire width 64 $extend$libresoc.v:127009$4877_Y + attribute \src "libresoc.v:127012.17-127012.108" + wire width 64 $extend$libresoc.v:127012$4881_Y + attribute \src "libresoc.v:127016.17-127016.102" + wire width 64 $extend$libresoc.v:127016$4886_Y + attribute \src "libresoc.v:127008.17-127008.108" + wire width 64 $pos$libresoc.v:127008$4876_Y + attribute \src "libresoc.v:127009.18-127009.111" + wire width 64 $pos$libresoc.v:127009$4878_Y + attribute \src "libresoc.v:127012.17-127012.108" + wire width 64 $pos$libresoc.v:127012$4882_Y + attribute \src "libresoc.v:127016.17-127016.102" + wire width 64 $pos$libresoc.v:127016$4887_Y + attribute \src "libresoc.v:127010.18-127010.118" + wire width 47 $sshl$libresoc.v:127010$4879_Y + attribute \src "libresoc.v:127011.18-127011.117" + wire width 27 $sshl$libresoc.v:127011$4880_Y + attribute \src "libresoc.v:127013.18-127013.117" + wire width 17 $sshl$libresoc.v:127013$4883_Y + attribute \src "libresoc.v:127014.18-127014.117" + wire width 17 $sshl$libresoc.v:127014$4884_Y + attribute \src "libresoc.v:127015.17-127015.109" + wire width 47 $sshl$libresoc.v:127015$4885_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 @@ -199404,17 +199084,17 @@ module \dec_bi$149 wire width 16 input 4 \LOGICAL_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok - attribute \src "libresoc.v:127041.7-127041.15" + attribute \src "libresoc.v:126930.7-126930.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -199431,80 +199111,80 @@ module \dec_bi$149 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127119$4891 + cell $pos $extend$libresoc.v:127008$4875 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LOGICAL_sh - connect \Y $extend$libresoc.v:127119$4891_Y + connect \Y $extend$libresoc.v:127008$4875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127120$4893 + cell $pos $extend$libresoc.v:127009$4877 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LOGICAL_SH32 - connect \Y $extend$libresoc.v:127120$4893_Y + connect \Y $extend$libresoc.v:127009$4877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127123$4897 + cell $pos $extend$libresoc.v:127012$4881 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LOGICAL_UI - connect \Y $extend$libresoc.v:127123$4897_Y + connect \Y $extend$libresoc.v:127012$4881_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $extend$libresoc.v:127127$4902 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $pos $extend$libresoc.v:127016$4886 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:127127$4902_Y + connect \Y $extend$libresoc.v:127016$4886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127119$4892 + cell $pos $pos$libresoc.v:127008$4876 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127119$4891_Y - connect \Y $pos$libresoc.v:127119$4892_Y + connect \A $extend$libresoc.v:127008$4875_Y + connect \Y $pos$libresoc.v:127008$4876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127120$4894 + cell $pos $pos$libresoc.v:127009$4878 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127120$4893_Y - connect \Y $pos$libresoc.v:127120$4894_Y + connect \A $extend$libresoc.v:127009$4877_Y + connect \Y $pos$libresoc.v:127009$4878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127123$4898 + cell $pos $pos$libresoc.v:127012$4882 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127123$4897_Y - connect \Y $pos$libresoc.v:127123$4898_Y + connect \A $extend$libresoc.v:127012$4881_Y + connect \Y $pos$libresoc.v:127012$4882_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $pos$libresoc.v:127127$4903 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $pos $pos$libresoc.v:127016$4887 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127127$4902_Y - connect \Y $pos$libresoc.v:127127$4903_Y + connect \A $extend$libresoc.v:127016$4886_Y + connect \Y $pos$libresoc.v:127016$4887_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:127121$4895 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" + cell $sshl $sshl$libresoc.v:127010$4879 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -199512,10 +199192,10 @@ module \dec_bi$149 parameter \Y_WIDTH 47 connect \A \LOGICAL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:127121$4895_Y + connect \Y $sshl$libresoc.v:127010$4879_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:127122$4896 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" + cell $sshl $sshl$libresoc.v:127011$4880 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -199523,10 +199203,10 @@ module \dec_bi$149 parameter \Y_WIDTH 27 connect \A \LOGICAL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:127122$4896_Y + connect \Y $sshl$libresoc.v:127011$4880_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:127124$4899 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" + cell $sshl $sshl$libresoc.v:127013$4883 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -199534,10 +199214,10 @@ module \dec_bi$149 parameter \Y_WIDTH 17 connect \A \LOGICAL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:127124$4899_Y + connect \Y $sshl$libresoc.v:127013$4883_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" - cell $sshl $sshl$libresoc.v:127125$4900 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" + cell $sshl $sshl$libresoc.v:127014$4884 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -199545,10 +199225,10 @@ module \dec_bi$149 parameter \Y_WIDTH 17 connect \A \LOGICAL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:127125$4900_Y + connect \Y $sshl$libresoc.v:127014$4884_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $sshl $sshl$libresoc.v:127126$4901 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $sshl $sshl$libresoc.v:127015$4885 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -199556,28 +199236,28 @@ module \dec_bi$149 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:127126$4901_Y + connect \Y $sshl$libresoc.v:127015$4885_Y end - attribute \src "libresoc.v:127041.7-127041.20" - process $proc$libresoc.v:127041$4912 + attribute \src "libresoc.v:126930.7-126930.20" + process $proc$libresoc.v:126930$4896 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127129.3-127175.6" - process $proc$libresoc.v:127129$4904 + attribute \src "libresoc.v:127018.3-127064.6" + process $proc$libresoc.v:127018$4888 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:127130.5-127130.29" + attribute \src "libresoc.v:127019.5-127019.29" switch \initial - attribute \src "libresoc.v:127130.9-127130.17" + attribute \src "libresoc.v:127019.9-127019.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -199625,18 +199305,18 @@ module \dec_bi$149 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:127176.3-127222.6" - process $proc$libresoc.v:127176$4905 + attribute \src "libresoc.v:127065.3-127111.6" + process $proc$libresoc.v:127065$4889 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127177.5-127177.29" + attribute \src "libresoc.v:127066.5-127066.29" switch \initial - attribute \src "libresoc.v:127177.9-127177.17" + attribute \src "libresoc.v:127066.9-127066.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -199684,20 +199364,23 @@ module \dec_bi$149 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:127223.3-127233.6" - process $proc$libresoc.v:127223$4906 + attribute \src "libresoc.v:127112.3-127126.6" + process $proc$libresoc.v:127112$4890 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:127224.5-127224.29" + attribute \src "libresoc.v:127113.5-127113.29" switch \initial - attribute \src "libresoc.v:127224.9-127224.17" + attribute \src "libresoc.v:127113.9-127113.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \LOGICAL_SI @@ -199707,20 +199390,26 @@ module \dec_bi$149 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:127234.3-127244.6" - process $proc$libresoc.v:127234$4907 + attribute \src "libresoc.v:127127.3-127145.6" + process $proc$libresoc.v:127127$4891 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:127235.5-127235.29" + attribute \src "libresoc.v:127128.5-127128.29" switch \initial - attribute \src "libresoc.v:127235.9-127235.17" + attribute \src "libresoc.v:127128.9-127128.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] @@ -199730,20 +199419,29 @@ module \dec_bi$149 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:127245.3-127255.6" - process $proc$libresoc.v:127245$4908 + attribute \src "libresoc.v:127146.3-127168.6" + process $proc$libresoc.v:127146$4892 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:127246.5-127246.29" + attribute \src "libresoc.v:127147.5-127147.29" switch \initial - attribute \src "libresoc.v:127246.9-127246.17" + attribute \src "libresoc.v:127147.9-127147.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \LOGICAL_UI @@ -199753,20 +199451,32 @@ module \dec_bi$149 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:127256.3-127266.6" - process $proc$libresoc.v:127256$4909 + attribute \src "libresoc.v:127169.3-127195.6" + process $proc$libresoc.v:127169$4893 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:127257.5-127257.29" + attribute \src "libresoc.v:127170.5-127170.29" switch \initial - attribute \src "libresoc.v:127257.9-127257.17" + attribute \src "libresoc.v:127170.9-127170.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] @@ -199776,20 +199486,35 @@ module \dec_bi$149 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:127267.3-127277.6" - process $proc$libresoc.v:127267$4910 + attribute \src "libresoc.v:127196.3-127226.6" + process $proc$libresoc.v:127196$4894 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:127268.5-127268.29" + attribute \src "libresoc.v:127197.5-127197.29" switch \initial - attribute \src "libresoc.v:127268.9-127268.17" + attribute \src "libresoc.v:127197.9-127197.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] @@ -199799,20 +199524,38 @@ module \dec_bi$149 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:127278.3-127288.6" - process $proc$libresoc.v:127278$4911 + attribute \src "libresoc.v:127227.3-127261.6" + process $proc$libresoc.v:127227$4895 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:127279.5-127279.29" + attribute \src "libresoc.v:127228.5-127228.29" switch \initial - attribute \src "libresoc.v:127279.9-127279.17" + attribute \src "libresoc.v:127228.9-127228.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] @@ -199822,111 +199565,111 @@ module \dec_bi$149 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:127119$4892_Y - connect \$11 $pos$libresoc.v:127120$4894_Y - connect \$14 $sshl$libresoc.v:127121$4895_Y - connect \$17 $sshl$libresoc.v:127122$4896_Y - connect \$1 $pos$libresoc.v:127123$4898_Y - connect \$20 $sshl$libresoc.v:127124$4899_Y - connect \$23 $sshl$libresoc.v:127125$4900_Y - connect \$4 $sshl$libresoc.v:127126$4901_Y - connect \$3 $pos$libresoc.v:127127$4903_Y + connect \$9 $pos$libresoc.v:127008$4876_Y + connect \$11 $pos$libresoc.v:127009$4878_Y + connect \$14 $sshl$libresoc.v:127010$4879_Y + connect \$17 $sshl$libresoc.v:127011$4880_Y + connect \$1 $pos$libresoc.v:127012$4882_Y + connect \$20 $sshl$libresoc.v:127013$4883_Y + connect \$23 $sshl$libresoc.v:127014$4884_Y + connect \$4 $sshl$libresoc.v:127015$4885_Y + connect \$3 $pos$libresoc.v:127016$4887_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:127297.1-127550.10" +attribute \src "libresoc.v:127270.1-127607.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi" attribute \generator "nMigen" module \dec_bi$157 - attribute \src "libresoc.v:127524.3-127534.6" + attribute \src "libresoc.v:127537.3-127567.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:127535.3-127545.6" + attribute \src "libresoc.v:127568.3-127602.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:127386.3-127432.6" + attribute \src "libresoc.v:127359.3-127405.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:127433.3-127479.6" + attribute \src "libresoc.v:127406.3-127452.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:127298.7-127298.20" + attribute \src "libresoc.v:127271.7-127271.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127513.3-127523.6" + attribute \src "libresoc.v:127510.3-127536.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:127480.3-127490.6" + attribute \src "libresoc.v:127453.3-127467.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:127491.3-127501.6" + attribute \src "libresoc.v:127468.3-127486.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:127502.3-127512.6" + attribute \src "libresoc.v:127487.3-127509.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:127524.3-127534.6" + attribute \src "libresoc.v:127537.3-127567.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:127535.3-127545.6" + attribute \src "libresoc.v:127568.3-127602.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:127386.3-127432.6" + attribute \src "libresoc.v:127359.3-127405.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:127433.3-127479.6" + attribute \src "libresoc.v:127406.3-127452.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127513.3-127523.6" + attribute \src "libresoc.v:127510.3-127536.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:127480.3-127490.6" + attribute \src "libresoc.v:127453.3-127467.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:127491.3-127501.6" + attribute \src "libresoc.v:127468.3-127486.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:127502.3-127512.6" + attribute \src "libresoc.v:127487.3-127509.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:127376.17-127376.104" - wire width 64 $extend$libresoc.v:127376$4913_Y - attribute \src "libresoc.v:127377.18-127377.107" - wire width 64 $extend$libresoc.v:127377$4915_Y - attribute \src "libresoc.v:127380.17-127380.104" - wire width 64 $extend$libresoc.v:127380$4919_Y - attribute \src "libresoc.v:127384.17-127384.102" - wire width 64 $extend$libresoc.v:127384$4924_Y - attribute \src "libresoc.v:127376.17-127376.104" - wire width 64 $pos$libresoc.v:127376$4914_Y - attribute \src "libresoc.v:127377.18-127377.107" - wire width 64 $pos$libresoc.v:127377$4916_Y - attribute \src "libresoc.v:127380.17-127380.104" - wire width 64 $pos$libresoc.v:127380$4920_Y - attribute \src "libresoc.v:127384.17-127384.102" - wire width 64 $pos$libresoc.v:127384$4925_Y - attribute \src "libresoc.v:127378.18-127378.114" - wire width 47 $sshl$libresoc.v:127378$4917_Y - attribute \src "libresoc.v:127379.18-127379.113" - wire width 27 $sshl$libresoc.v:127379$4918_Y - attribute \src "libresoc.v:127381.18-127381.113" - wire width 17 $sshl$libresoc.v:127381$4921_Y - attribute \src "libresoc.v:127382.18-127382.113" - wire width 17 $sshl$libresoc.v:127382$4922_Y - attribute \src "libresoc.v:127383.17-127383.109" - wire width 47 $sshl$libresoc.v:127383$4923_Y + attribute \src "libresoc.v:127349.17-127349.104" + wire width 64 $extend$libresoc.v:127349$4897_Y + attribute \src "libresoc.v:127350.18-127350.107" + wire width 64 $extend$libresoc.v:127350$4899_Y + attribute \src "libresoc.v:127353.17-127353.104" + wire width 64 $extend$libresoc.v:127353$4903_Y + attribute \src "libresoc.v:127357.17-127357.102" + wire width 64 $extend$libresoc.v:127357$4908_Y + attribute \src "libresoc.v:127349.17-127349.104" + wire width 64 $pos$libresoc.v:127349$4898_Y + attribute \src "libresoc.v:127350.18-127350.107" + wire width 64 $pos$libresoc.v:127350$4900_Y + attribute \src "libresoc.v:127353.17-127353.104" + wire width 64 $pos$libresoc.v:127353$4904_Y + attribute \src "libresoc.v:127357.17-127357.102" + wire width 64 $pos$libresoc.v:127357$4909_Y + attribute \src "libresoc.v:127351.18-127351.114" + wire width 47 $sshl$libresoc.v:127351$4901_Y + attribute \src "libresoc.v:127352.18-127352.113" + wire width 27 $sshl$libresoc.v:127352$4902_Y + attribute \src "libresoc.v:127354.18-127354.113" + wire width 17 $sshl$libresoc.v:127354$4905_Y + attribute \src "libresoc.v:127355.18-127355.113" + wire width 17 $sshl$libresoc.v:127355$4906_Y + attribute \src "libresoc.v:127356.17-127356.109" + wire width 47 $sshl$libresoc.v:127356$4907_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 @@ -199944,17 +199687,17 @@ module \dec_bi$157 wire width 16 input 4 \DIV_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok - attribute \src "libresoc.v:127298.7-127298.15" + attribute \src "libresoc.v:127271.7-127271.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -199971,80 +199714,80 @@ module \dec_bi$157 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127376$4913 + cell $pos $extend$libresoc.v:127349$4897 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \DIV_sh - connect \Y $extend$libresoc.v:127376$4913_Y + connect \Y $extend$libresoc.v:127349$4897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127377$4915 + cell $pos $extend$libresoc.v:127350$4899 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \DIV_SH32 - connect \Y $extend$libresoc.v:127377$4915_Y + connect \Y $extend$libresoc.v:127350$4899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127380$4919 + cell $pos $extend$libresoc.v:127353$4903 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \DIV_UI - connect \Y $extend$libresoc.v:127380$4919_Y + connect \Y $extend$libresoc.v:127353$4903_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $extend$libresoc.v:127384$4924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $pos $extend$libresoc.v:127357$4908 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:127384$4924_Y + connect \Y $extend$libresoc.v:127357$4908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127376$4914 + cell $pos $pos$libresoc.v:127349$4898 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127376$4913_Y - connect \Y $pos$libresoc.v:127376$4914_Y + connect \A $extend$libresoc.v:127349$4897_Y + connect \Y $pos$libresoc.v:127349$4898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127377$4916 + cell $pos $pos$libresoc.v:127350$4900 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127377$4915_Y - connect \Y $pos$libresoc.v:127377$4916_Y + connect \A $extend$libresoc.v:127350$4899_Y + connect \Y $pos$libresoc.v:127350$4900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127380$4920 + cell $pos $pos$libresoc.v:127353$4904 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127380$4919_Y - connect \Y $pos$libresoc.v:127380$4920_Y + connect \A $extend$libresoc.v:127353$4903_Y + connect \Y $pos$libresoc.v:127353$4904_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $pos$libresoc.v:127384$4925 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $pos $pos$libresoc.v:127357$4909 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127384$4924_Y - connect \Y $pos$libresoc.v:127384$4925_Y + connect \A $extend$libresoc.v:127357$4908_Y + connect \Y $pos$libresoc.v:127357$4909_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:127378$4917 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" + cell $sshl $sshl$libresoc.v:127351$4901 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -200052,10 +199795,10 @@ module \dec_bi$157 parameter \Y_WIDTH 47 connect \A \DIV_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:127378$4917_Y + connect \Y $sshl$libresoc.v:127351$4901_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:127379$4918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" + cell $sshl $sshl$libresoc.v:127352$4902 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -200063,10 +199806,10 @@ module \dec_bi$157 parameter \Y_WIDTH 27 connect \A \DIV_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:127379$4918_Y + connect \Y $sshl$libresoc.v:127352$4902_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:127381$4921 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" + cell $sshl $sshl$libresoc.v:127354$4905 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -200074,10 +199817,10 @@ module \dec_bi$157 parameter \Y_WIDTH 17 connect \A \DIV_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:127381$4921_Y + connect \Y $sshl$libresoc.v:127354$4905_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" - cell $sshl $sshl$libresoc.v:127382$4922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" + cell $sshl $sshl$libresoc.v:127355$4906 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -200085,10 +199828,10 @@ module \dec_bi$157 parameter \Y_WIDTH 17 connect \A \DIV_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:127382$4922_Y + connect \Y $sshl$libresoc.v:127355$4906_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $sshl $sshl$libresoc.v:127383$4923 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $sshl $sshl$libresoc.v:127356$4907 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -200096,28 +199839,28 @@ module \dec_bi$157 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:127383$4923_Y + connect \Y $sshl$libresoc.v:127356$4907_Y end - attribute \src "libresoc.v:127298.7-127298.20" - process $proc$libresoc.v:127298$4934 + attribute \src "libresoc.v:127271.7-127271.20" + process $proc$libresoc.v:127271$4918 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127386.3-127432.6" - process $proc$libresoc.v:127386$4926 + attribute \src "libresoc.v:127359.3-127405.6" + process $proc$libresoc.v:127359$4910 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:127387.5-127387.29" + attribute \src "libresoc.v:127360.5-127360.29" switch \initial - attribute \src "libresoc.v:127387.9-127387.17" + attribute \src "libresoc.v:127360.9-127360.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -200165,18 +199908,18 @@ module \dec_bi$157 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:127433.3-127479.6" - process $proc$libresoc.v:127433$4927 + attribute \src "libresoc.v:127406.3-127452.6" + process $proc$libresoc.v:127406$4911 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127434.5-127434.29" + attribute \src "libresoc.v:127407.5-127407.29" switch \initial - attribute \src "libresoc.v:127434.9-127434.17" + attribute \src "libresoc.v:127407.9-127407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -200224,20 +199967,23 @@ module \dec_bi$157 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:127480.3-127490.6" - process $proc$libresoc.v:127480$4928 + attribute \src "libresoc.v:127453.3-127467.6" + process $proc$libresoc.v:127453$4912 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:127481.5-127481.29" + attribute \src "libresoc.v:127454.5-127454.29" switch \initial - attribute \src "libresoc.v:127481.9-127481.17" + attribute \src "libresoc.v:127454.9-127454.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \DIV_SI @@ -200247,20 +199993,26 @@ module \dec_bi$157 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:127491.3-127501.6" - process $proc$libresoc.v:127491$4929 + attribute \src "libresoc.v:127468.3-127486.6" + process $proc$libresoc.v:127468$4913 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:127492.5-127492.29" + attribute \src "libresoc.v:127469.5-127469.29" switch \initial - attribute \src "libresoc.v:127492.9-127492.17" + attribute \src "libresoc.v:127469.9-127469.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] @@ -200270,20 +200022,29 @@ module \dec_bi$157 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:127502.3-127512.6" - process $proc$libresoc.v:127502$4930 + attribute \src "libresoc.v:127487.3-127509.6" + process $proc$libresoc.v:127487$4914 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:127503.5-127503.29" + attribute \src "libresoc.v:127488.5-127488.29" switch \initial - attribute \src "libresoc.v:127503.9-127503.17" + attribute \src "libresoc.v:127488.9-127488.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \DIV_UI @@ -200293,20 +200054,32 @@ module \dec_bi$157 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:127513.3-127523.6" - process $proc$libresoc.v:127513$4931 + attribute \src "libresoc.v:127510.3-127536.6" + process $proc$libresoc.v:127510$4915 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:127514.5-127514.29" + attribute \src "libresoc.v:127511.5-127511.29" switch \initial - attribute \src "libresoc.v:127514.9-127514.17" + attribute \src "libresoc.v:127511.9-127511.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] @@ -200316,20 +200089,35 @@ module \dec_bi$157 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:127524.3-127534.6" - process $proc$libresoc.v:127524$4932 + attribute \src "libresoc.v:127537.3-127567.6" + process $proc$libresoc.v:127537$4916 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:127525.5-127525.29" + attribute \src "libresoc.v:127538.5-127538.29" switch \initial - attribute \src "libresoc.v:127525.9-127525.17" + attribute \src "libresoc.v:127538.9-127538.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] @@ -200339,20 +200127,38 @@ module \dec_bi$157 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:127535.3-127545.6" - process $proc$libresoc.v:127535$4933 + attribute \src "libresoc.v:127568.3-127602.6" + process $proc$libresoc.v:127568$4917 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:127536.5-127536.29" + attribute \src "libresoc.v:127569.5-127569.29" switch \initial - attribute \src "libresoc.v:127536.9-127536.17" + attribute \src "libresoc.v:127569.9-127569.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] @@ -200362,111 +200168,111 @@ module \dec_bi$157 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:127376$4914_Y - connect \$11 $pos$libresoc.v:127377$4916_Y - connect \$14 $sshl$libresoc.v:127378$4917_Y - connect \$17 $sshl$libresoc.v:127379$4918_Y - connect \$1 $pos$libresoc.v:127380$4920_Y - connect \$20 $sshl$libresoc.v:127381$4921_Y - connect \$23 $sshl$libresoc.v:127382$4922_Y - connect \$4 $sshl$libresoc.v:127383$4923_Y - connect \$3 $pos$libresoc.v:127384$4925_Y + connect \$9 $pos$libresoc.v:127349$4898_Y + connect \$11 $pos$libresoc.v:127350$4900_Y + connect \$14 $sshl$libresoc.v:127351$4901_Y + connect \$17 $sshl$libresoc.v:127352$4902_Y + connect \$1 $pos$libresoc.v:127353$4904_Y + connect \$20 $sshl$libresoc.v:127354$4905_Y + connect \$23 $sshl$libresoc.v:127355$4906_Y + connect \$4 $sshl$libresoc.v:127356$4907_Y + connect \$3 $pos$libresoc.v:127357$4909_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:127554.1-127807.10" +attribute \src "libresoc.v:127611.1-127948.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" attribute \generator "nMigen" module \dec_bi$161 - attribute \src "libresoc.v:127781.3-127791.6" + attribute \src "libresoc.v:127878.3-127908.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:127792.3-127802.6" + attribute \src "libresoc.v:127909.3-127943.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:127643.3-127689.6" + attribute \src "libresoc.v:127700.3-127746.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:127690.3-127736.6" + attribute \src "libresoc.v:127747.3-127793.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:127555.7-127555.20" + attribute \src "libresoc.v:127612.7-127612.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127770.3-127780.6" + attribute \src "libresoc.v:127851.3-127877.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:127737.3-127747.6" + attribute \src "libresoc.v:127794.3-127808.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:127748.3-127758.6" + attribute \src "libresoc.v:127809.3-127827.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:127759.3-127769.6" + attribute \src "libresoc.v:127828.3-127850.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:127781.3-127791.6" + attribute \src "libresoc.v:127878.3-127908.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:127792.3-127802.6" + attribute \src "libresoc.v:127909.3-127943.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:127643.3-127689.6" + attribute \src "libresoc.v:127700.3-127746.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:127690.3-127736.6" + attribute \src "libresoc.v:127747.3-127793.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127770.3-127780.6" + attribute \src "libresoc.v:127851.3-127877.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:127737.3-127747.6" + attribute \src "libresoc.v:127794.3-127808.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:127748.3-127758.6" + attribute \src "libresoc.v:127809.3-127827.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:127759.3-127769.6" + attribute \src "libresoc.v:127828.3-127850.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:127633.17-127633.104" - wire width 64 $extend$libresoc.v:127633$4935_Y - attribute \src "libresoc.v:127634.18-127634.107" - wire width 64 $extend$libresoc.v:127634$4937_Y - attribute \src "libresoc.v:127637.17-127637.104" - wire width 64 $extend$libresoc.v:127637$4941_Y - attribute \src "libresoc.v:127641.17-127641.102" - wire width 64 $extend$libresoc.v:127641$4946_Y - attribute \src "libresoc.v:127633.17-127633.104" - wire width 64 $pos$libresoc.v:127633$4936_Y - attribute \src "libresoc.v:127634.18-127634.107" - wire width 64 $pos$libresoc.v:127634$4938_Y - attribute \src "libresoc.v:127637.17-127637.104" - wire width 64 $pos$libresoc.v:127637$4942_Y - attribute \src "libresoc.v:127641.17-127641.102" - wire width 64 $pos$libresoc.v:127641$4947_Y - attribute \src "libresoc.v:127635.18-127635.114" - wire width 47 $sshl$libresoc.v:127635$4939_Y - attribute \src "libresoc.v:127636.18-127636.113" - wire width 27 $sshl$libresoc.v:127636$4940_Y - attribute \src "libresoc.v:127638.18-127638.113" - wire width 17 $sshl$libresoc.v:127638$4943_Y - attribute \src "libresoc.v:127639.18-127639.113" - wire width 17 $sshl$libresoc.v:127639$4944_Y - attribute \src "libresoc.v:127640.17-127640.109" - wire width 47 $sshl$libresoc.v:127640$4945_Y + attribute \src "libresoc.v:127690.17-127690.104" + wire width 64 $extend$libresoc.v:127690$4919_Y + attribute \src "libresoc.v:127691.18-127691.107" + wire width 64 $extend$libresoc.v:127691$4921_Y + attribute \src "libresoc.v:127694.17-127694.104" + wire width 64 $extend$libresoc.v:127694$4925_Y + attribute \src "libresoc.v:127698.17-127698.102" + wire width 64 $extend$libresoc.v:127698$4930_Y + attribute \src "libresoc.v:127690.17-127690.104" + wire width 64 $pos$libresoc.v:127690$4920_Y + attribute \src "libresoc.v:127691.18-127691.107" + wire width 64 $pos$libresoc.v:127691$4922_Y + attribute \src "libresoc.v:127694.17-127694.104" + wire width 64 $pos$libresoc.v:127694$4926_Y + attribute \src "libresoc.v:127698.17-127698.102" + wire width 64 $pos$libresoc.v:127698$4931_Y + attribute \src "libresoc.v:127692.18-127692.114" + wire width 47 $sshl$libresoc.v:127692$4923_Y + attribute \src "libresoc.v:127693.18-127693.113" + wire width 27 $sshl$libresoc.v:127693$4924_Y + attribute \src "libresoc.v:127695.18-127695.113" + wire width 17 $sshl$libresoc.v:127695$4927_Y + attribute \src "libresoc.v:127696.18-127696.113" + wire width 17 $sshl$libresoc.v:127696$4928_Y + attribute \src "libresoc.v:127697.17-127697.109" + wire width 47 $sshl$libresoc.v:127697$4929_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 @@ -200484,17 +200290,17 @@ module \dec_bi$161 wire width 16 input 4 \MUL_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok - attribute \src "libresoc.v:127555.7-127555.15" + attribute \src "libresoc.v:127612.7-127612.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -200511,80 +200317,80 @@ module \dec_bi$161 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127633$4935 + cell $pos $extend$libresoc.v:127690$4919 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \MUL_sh - connect \Y $extend$libresoc.v:127633$4935_Y + connect \Y $extend$libresoc.v:127690$4919_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127634$4937 + cell $pos $extend$libresoc.v:127691$4921 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \MUL_SH32 - connect \Y $extend$libresoc.v:127634$4937_Y + connect \Y $extend$libresoc.v:127691$4921_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127637$4941 + cell $pos $extend$libresoc.v:127694$4925 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \MUL_UI - connect \Y $extend$libresoc.v:127637$4941_Y + connect \Y $extend$libresoc.v:127694$4925_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $extend$libresoc.v:127641$4946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $pos $extend$libresoc.v:127698$4930 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:127641$4946_Y + connect \Y $extend$libresoc.v:127698$4930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127633$4936 + cell $pos $pos$libresoc.v:127690$4920 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127633$4935_Y - connect \Y $pos$libresoc.v:127633$4936_Y + connect \A $extend$libresoc.v:127690$4919_Y + connect \Y $pos$libresoc.v:127690$4920_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127634$4938 + cell $pos $pos$libresoc.v:127691$4922 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127634$4937_Y - connect \Y $pos$libresoc.v:127634$4938_Y + connect \A $extend$libresoc.v:127691$4921_Y + connect \Y $pos$libresoc.v:127691$4922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127637$4942 + cell $pos $pos$libresoc.v:127694$4926 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127637$4941_Y - connect \Y $pos$libresoc.v:127637$4942_Y + connect \A $extend$libresoc.v:127694$4925_Y + connect \Y $pos$libresoc.v:127694$4926_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $pos$libresoc.v:127641$4947 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $pos $pos$libresoc.v:127698$4931 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127641$4946_Y - connect \Y $pos$libresoc.v:127641$4947_Y + connect \A $extend$libresoc.v:127698$4930_Y + connect \Y $pos$libresoc.v:127698$4931_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:127635$4939 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" + cell $sshl $sshl$libresoc.v:127692$4923 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -200592,10 +200398,10 @@ module \dec_bi$161 parameter \Y_WIDTH 47 connect \A \MUL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:127635$4939_Y + connect \Y $sshl$libresoc.v:127692$4923_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:127636$4940 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" + cell $sshl $sshl$libresoc.v:127693$4924 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -200603,10 +200409,10 @@ module \dec_bi$161 parameter \Y_WIDTH 27 connect \A \MUL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:127636$4940_Y + connect \Y $sshl$libresoc.v:127693$4924_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:127638$4943 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" + cell $sshl $sshl$libresoc.v:127695$4927 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -200614,10 +200420,10 @@ module \dec_bi$161 parameter \Y_WIDTH 17 connect \A \MUL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:127638$4943_Y + connect \Y $sshl$libresoc.v:127695$4927_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" - cell $sshl $sshl$libresoc.v:127639$4944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" + cell $sshl $sshl$libresoc.v:127696$4928 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -200625,10 +200431,10 @@ module \dec_bi$161 parameter \Y_WIDTH 17 connect \A \MUL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:127639$4944_Y + connect \Y $sshl$libresoc.v:127696$4928_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $sshl $sshl$libresoc.v:127640$4945 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $sshl $sshl$libresoc.v:127697$4929 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -200636,28 +200442,28 @@ module \dec_bi$161 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:127640$4945_Y + connect \Y $sshl$libresoc.v:127697$4929_Y end - attribute \src "libresoc.v:127555.7-127555.20" - process $proc$libresoc.v:127555$4956 + attribute \src "libresoc.v:127612.7-127612.20" + process $proc$libresoc.v:127612$4940 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127643.3-127689.6" - process $proc$libresoc.v:127643$4948 + attribute \src "libresoc.v:127700.3-127746.6" + process $proc$libresoc.v:127700$4932 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:127644.5-127644.29" + attribute \src "libresoc.v:127701.5-127701.29" switch \initial - attribute \src "libresoc.v:127644.9-127644.17" + attribute \src "libresoc.v:127701.9-127701.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -200705,18 +200511,18 @@ module \dec_bi$161 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:127690.3-127736.6" - process $proc$libresoc.v:127690$4949 + attribute \src "libresoc.v:127747.3-127793.6" + process $proc$libresoc.v:127747$4933 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127691.5-127691.29" + attribute \src "libresoc.v:127748.5-127748.29" switch \initial - attribute \src "libresoc.v:127691.9-127691.17" + attribute \src "libresoc.v:127748.9-127748.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -200764,20 +200570,23 @@ module \dec_bi$161 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:127737.3-127747.6" - process $proc$libresoc.v:127737$4950 + attribute \src "libresoc.v:127794.3-127808.6" + process $proc$libresoc.v:127794$4934 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:127738.5-127738.29" + attribute \src "libresoc.v:127795.5-127795.29" switch \initial - attribute \src "libresoc.v:127738.9-127738.17" + attribute \src "libresoc.v:127795.9-127795.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \MUL_SI @@ -200787,20 +200596,26 @@ module \dec_bi$161 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:127748.3-127758.6" - process $proc$libresoc.v:127748$4951 + attribute \src "libresoc.v:127809.3-127827.6" + process $proc$libresoc.v:127809$4935 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:127749.5-127749.29" + attribute \src "libresoc.v:127810.5-127810.29" switch \initial - attribute \src "libresoc.v:127749.9-127749.17" + attribute \src "libresoc.v:127810.9-127810.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] @@ -200810,20 +200625,29 @@ module \dec_bi$161 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:127759.3-127769.6" - process $proc$libresoc.v:127759$4952 + attribute \src "libresoc.v:127828.3-127850.6" + process $proc$libresoc.v:127828$4936 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:127760.5-127760.29" + attribute \src "libresoc.v:127829.5-127829.29" switch \initial - attribute \src "libresoc.v:127760.9-127760.17" + attribute \src "libresoc.v:127829.9-127829.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \MUL_UI @@ -200833,20 +200657,32 @@ module \dec_bi$161 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:127770.3-127780.6" - process $proc$libresoc.v:127770$4953 + attribute \src "libresoc.v:127851.3-127877.6" + process $proc$libresoc.v:127851$4937 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:127771.5-127771.29" + attribute \src "libresoc.v:127852.5-127852.29" switch \initial - attribute \src "libresoc.v:127771.9-127771.17" + attribute \src "libresoc.v:127852.9-127852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] @@ -200856,20 +200692,35 @@ module \dec_bi$161 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:127781.3-127791.6" - process $proc$libresoc.v:127781$4954 + attribute \src "libresoc.v:127878.3-127908.6" + process $proc$libresoc.v:127878$4938 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:127782.5-127782.29" + attribute \src "libresoc.v:127879.5-127879.29" switch \initial - attribute \src "libresoc.v:127782.9-127782.17" + attribute \src "libresoc.v:127879.9-127879.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] @@ -200879,20 +200730,38 @@ module \dec_bi$161 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:127792.3-127802.6" - process $proc$libresoc.v:127792$4955 + attribute \src "libresoc.v:127909.3-127943.6" + process $proc$libresoc.v:127909$4939 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:127793.5-127793.29" + attribute \src "libresoc.v:127910.5-127910.29" switch \initial - attribute \src "libresoc.v:127793.9-127793.17" + attribute \src "libresoc.v:127910.9-127910.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] @@ -200902,111 +200771,111 @@ module \dec_bi$161 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:127633$4936_Y - connect \$11 $pos$libresoc.v:127634$4938_Y - connect \$14 $sshl$libresoc.v:127635$4939_Y - connect \$17 $sshl$libresoc.v:127636$4940_Y - connect \$1 $pos$libresoc.v:127637$4942_Y - connect \$20 $sshl$libresoc.v:127638$4943_Y - connect \$23 $sshl$libresoc.v:127639$4944_Y - connect \$4 $sshl$libresoc.v:127640$4945_Y - connect \$3 $pos$libresoc.v:127641$4947_Y + connect \$9 $pos$libresoc.v:127690$4920_Y + connect \$11 $pos$libresoc.v:127691$4922_Y + connect \$14 $sshl$libresoc.v:127692$4923_Y + connect \$17 $sshl$libresoc.v:127693$4924_Y + connect \$1 $pos$libresoc.v:127694$4926_Y + connect \$20 $sshl$libresoc.v:127695$4927_Y + connect \$23 $sshl$libresoc.v:127696$4928_Y + connect \$4 $sshl$libresoc.v:127697$4929_Y + connect \$3 $pos$libresoc.v:127698$4931_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:127811.1-128064.10" +attribute \src "libresoc.v:127952.1-128289.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" attribute \generator "nMigen" module \dec_bi$165 - attribute \src "libresoc.v:128038.3-128048.6" + attribute \src "libresoc.v:128219.3-128249.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:128049.3-128059.6" + attribute \src "libresoc.v:128250.3-128284.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:127900.3-127946.6" + attribute \src "libresoc.v:128041.3-128087.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:127947.3-127993.6" + attribute \src "libresoc.v:128088.3-128134.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:127812.7-127812.20" + attribute \src "libresoc.v:127953.7-127953.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128027.3-128037.6" + attribute \src "libresoc.v:128192.3-128218.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:127994.3-128004.6" + attribute \src "libresoc.v:128135.3-128149.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:128005.3-128015.6" + attribute \src "libresoc.v:128150.3-128168.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:128016.3-128026.6" + attribute \src "libresoc.v:128169.3-128191.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:128038.3-128048.6" + attribute \src "libresoc.v:128219.3-128249.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:128049.3-128059.6" + attribute \src "libresoc.v:128250.3-128284.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:127900.3-127946.6" + attribute \src "libresoc.v:128041.3-128087.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:127947.3-127993.6" + attribute \src "libresoc.v:128088.3-128134.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:128027.3-128037.6" + attribute \src "libresoc.v:128192.3-128218.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:127994.3-128004.6" + attribute \src "libresoc.v:128135.3-128149.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:128005.3-128015.6" + attribute \src "libresoc.v:128150.3-128168.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:128016.3-128026.6" + attribute \src "libresoc.v:128169.3-128191.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:127890.17-127890.110" - wire width 64 $extend$libresoc.v:127890$4957_Y - attribute \src "libresoc.v:127891.18-127891.113" - wire width 64 $extend$libresoc.v:127891$4959_Y - attribute \src "libresoc.v:127894.17-127894.110" - wire width 64 $extend$libresoc.v:127894$4963_Y - attribute \src "libresoc.v:127898.17-127898.102" - wire width 64 $extend$libresoc.v:127898$4968_Y - attribute \src "libresoc.v:127890.17-127890.110" - wire width 64 $pos$libresoc.v:127890$4958_Y - attribute \src "libresoc.v:127891.18-127891.113" - wire width 64 $pos$libresoc.v:127891$4960_Y - attribute \src "libresoc.v:127894.17-127894.110" - wire width 64 $pos$libresoc.v:127894$4964_Y - attribute \src "libresoc.v:127898.17-127898.102" - wire width 64 $pos$libresoc.v:127898$4969_Y - attribute \src "libresoc.v:127892.18-127892.120" - wire width 47 $sshl$libresoc.v:127892$4961_Y - attribute \src "libresoc.v:127893.18-127893.119" - wire width 27 $sshl$libresoc.v:127893$4962_Y - attribute \src "libresoc.v:127895.18-127895.119" - wire width 17 $sshl$libresoc.v:127895$4965_Y - attribute \src "libresoc.v:127896.18-127896.119" - wire width 17 $sshl$libresoc.v:127896$4966_Y - attribute \src "libresoc.v:127897.17-127897.109" - wire width 47 $sshl$libresoc.v:127897$4967_Y + attribute \src "libresoc.v:128031.17-128031.110" + wire width 64 $extend$libresoc.v:128031$4941_Y + attribute \src "libresoc.v:128032.18-128032.113" + wire width 64 $extend$libresoc.v:128032$4943_Y + attribute \src "libresoc.v:128035.17-128035.110" + wire width 64 $extend$libresoc.v:128035$4947_Y + attribute \src "libresoc.v:128039.17-128039.102" + wire width 64 $extend$libresoc.v:128039$4952_Y + attribute \src "libresoc.v:128031.17-128031.110" + wire width 64 $pos$libresoc.v:128031$4942_Y + attribute \src "libresoc.v:128032.18-128032.113" + wire width 64 $pos$libresoc.v:128032$4944_Y + attribute \src "libresoc.v:128035.17-128035.110" + wire width 64 $pos$libresoc.v:128035$4948_Y + attribute \src "libresoc.v:128039.17-128039.102" + wire width 64 $pos$libresoc.v:128039$4953_Y + attribute \src "libresoc.v:128033.18-128033.120" + wire width 47 $sshl$libresoc.v:128033$4945_Y + attribute \src "libresoc.v:128034.18-128034.119" + wire width 27 $sshl$libresoc.v:128034$4946_Y + attribute \src "libresoc.v:128036.18-128036.119" + wire width 17 $sshl$libresoc.v:128036$4949_Y + attribute \src "libresoc.v:128037.18-128037.119" + wire width 17 $sshl$libresoc.v:128037$4950_Y + attribute \src "libresoc.v:128038.17-128038.109" + wire width 47 $sshl$libresoc.v:128038$4951_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 @@ -201024,17 +200893,17 @@ module \dec_bi$165 wire width 16 input 4 \SHIFT_ROT_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok - attribute \src "libresoc.v:127812.7-127812.15" + attribute \src "libresoc.v:127953.7-127953.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -201051,80 +200920,80 @@ module \dec_bi$165 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127890$4957 + cell $pos $extend$libresoc.v:128031$4941 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_sh - connect \Y $extend$libresoc.v:127890$4957_Y + connect \Y $extend$libresoc.v:128031$4941_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127891$4959 + cell $pos $extend$libresoc.v:128032$4943 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_SH32 - connect \Y $extend$libresoc.v:127891$4959_Y + connect \Y $extend$libresoc.v:128032$4943_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127894$4963 + cell $pos $extend$libresoc.v:128035$4947 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_UI - connect \Y $extend$libresoc.v:127894$4963_Y + connect \Y $extend$libresoc.v:128035$4947_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $extend$libresoc.v:127898$4968 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $pos $extend$libresoc.v:128039$4952 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:127898$4968_Y + connect \Y $extend$libresoc.v:128039$4952_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127890$4958 + cell $pos $pos$libresoc.v:128031$4942 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127890$4957_Y - connect \Y $pos$libresoc.v:127890$4958_Y + connect \A $extend$libresoc.v:128031$4941_Y + connect \Y $pos$libresoc.v:128031$4942_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127891$4960 + cell $pos $pos$libresoc.v:128032$4944 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127891$4959_Y - connect \Y $pos$libresoc.v:127891$4960_Y + connect \A $extend$libresoc.v:128032$4943_Y + connect \Y $pos$libresoc.v:128032$4944_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127894$4964 + cell $pos $pos$libresoc.v:128035$4948 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127894$4963_Y - connect \Y $pos$libresoc.v:127894$4964_Y + connect \A $extend$libresoc.v:128035$4947_Y + connect \Y $pos$libresoc.v:128035$4948_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $pos$libresoc.v:127898$4969 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $pos $pos$libresoc.v:128039$4953 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127898$4968_Y - connect \Y $pos$libresoc.v:127898$4969_Y + connect \A $extend$libresoc.v:128039$4952_Y + connect \Y $pos$libresoc.v:128039$4953_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:127892$4961 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" + cell $sshl $sshl$libresoc.v:128033$4945 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -201132,10 +201001,10 @@ module \dec_bi$165 parameter \Y_WIDTH 47 connect \A \SHIFT_ROT_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:127892$4961_Y + connect \Y $sshl$libresoc.v:128033$4945_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:127893$4962 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" + cell $sshl $sshl$libresoc.v:128034$4946 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -201143,10 +201012,10 @@ module \dec_bi$165 parameter \Y_WIDTH 27 connect \A \SHIFT_ROT_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:127893$4962_Y + connect \Y $sshl$libresoc.v:128034$4946_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:127895$4965 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" + cell $sshl $sshl$libresoc.v:128036$4949 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -201154,10 +201023,10 @@ module \dec_bi$165 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:127895$4965_Y + connect \Y $sshl$libresoc.v:128036$4949_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" - cell $sshl $sshl$libresoc.v:127896$4966 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" + cell $sshl $sshl$libresoc.v:128037$4950 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -201165,10 +201034,10 @@ module \dec_bi$165 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:127896$4966_Y + connect \Y $sshl$libresoc.v:128037$4950_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $sshl $sshl$libresoc.v:127897$4967 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $sshl $sshl$libresoc.v:128038$4951 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -201176,28 +201045,28 @@ module \dec_bi$165 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:127897$4967_Y + connect \Y $sshl$libresoc.v:128038$4951_Y end - attribute \src "libresoc.v:127812.7-127812.20" - process $proc$libresoc.v:127812$4978 + attribute \src "libresoc.v:127953.7-127953.20" + process $proc$libresoc.v:127953$4962 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127900.3-127946.6" - process $proc$libresoc.v:127900$4970 + attribute \src "libresoc.v:128041.3-128087.6" + process $proc$libresoc.v:128041$4954 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:127901.5-127901.29" + attribute \src "libresoc.v:128042.5-128042.29" switch \initial - attribute \src "libresoc.v:127901.9-127901.17" + attribute \src "libresoc.v:128042.9-128042.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -201245,18 +201114,18 @@ module \dec_bi$165 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:127947.3-127993.6" - process $proc$libresoc.v:127947$4971 + attribute \src "libresoc.v:128088.3-128134.6" + process $proc$libresoc.v:128088$4955 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127948.5-127948.29" + attribute \src "libresoc.v:128089.5-128089.29" switch \initial - attribute \src "libresoc.v:127948.9-127948.17" + attribute \src "libresoc.v:128089.9-128089.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -201304,20 +201173,23 @@ module \dec_bi$165 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:127994.3-128004.6" - process $proc$libresoc.v:127994$4972 + attribute \src "libresoc.v:128135.3-128149.6" + process $proc$libresoc.v:128135$4956 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:127995.5-127995.29" + attribute \src "libresoc.v:128136.5-128136.29" switch \initial - attribute \src "libresoc.v:127995.9-127995.17" + attribute \src "libresoc.v:128136.9-128136.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \SHIFT_ROT_SI @@ -201327,20 +201199,26 @@ module \dec_bi$165 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:128005.3-128015.6" - process $proc$libresoc.v:128005$4973 + attribute \src "libresoc.v:128150.3-128168.6" + process $proc$libresoc.v:128150$4957 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:128006.5-128006.29" + attribute \src "libresoc.v:128151.5-128151.29" switch \initial - attribute \src "libresoc.v:128006.9-128006.17" + attribute \src "libresoc.v:128151.9-128151.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] @@ -201350,20 +201228,29 @@ module \dec_bi$165 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:128016.3-128026.6" - process $proc$libresoc.v:128016$4974 + attribute \src "libresoc.v:128169.3-128191.6" + process $proc$libresoc.v:128169$4958 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:128017.5-128017.29" + attribute \src "libresoc.v:128170.5-128170.29" switch \initial - attribute \src "libresoc.v:128017.9-128017.17" + attribute \src "libresoc.v:128170.9-128170.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \SHIFT_ROT_UI @@ -201373,20 +201260,32 @@ module \dec_bi$165 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:128027.3-128037.6" - process $proc$libresoc.v:128027$4975 + attribute \src "libresoc.v:128192.3-128218.6" + process $proc$libresoc.v:128192$4959 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:128028.5-128028.29" + attribute \src "libresoc.v:128193.5-128193.29" switch \initial - attribute \src "libresoc.v:128028.9-128028.17" + attribute \src "libresoc.v:128193.9-128193.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] @@ -201396,20 +201295,35 @@ module \dec_bi$165 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:128038.3-128048.6" - process $proc$libresoc.v:128038$4976 + attribute \src "libresoc.v:128219.3-128249.6" + process $proc$libresoc.v:128219$4960 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:128039.5-128039.29" + attribute \src "libresoc.v:128220.5-128220.29" switch \initial - attribute \src "libresoc.v:128039.9-128039.17" + attribute \src "libresoc.v:128220.9-128220.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] @@ -201419,20 +201333,38 @@ module \dec_bi$165 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:128049.3-128059.6" - process $proc$libresoc.v:128049$4977 + attribute \src "libresoc.v:128250.3-128284.6" + process $proc$libresoc.v:128250$4961 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:128050.5-128050.29" + attribute \src "libresoc.v:128251.5-128251.29" switch \initial - attribute \src "libresoc.v:128050.9-128050.17" + attribute \src "libresoc.v:128251.9-128251.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] @@ -201442,111 +201374,111 @@ module \dec_bi$165 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:127890$4958_Y - connect \$11 $pos$libresoc.v:127891$4960_Y - connect \$14 $sshl$libresoc.v:127892$4961_Y - connect \$17 $sshl$libresoc.v:127893$4962_Y - connect \$1 $pos$libresoc.v:127894$4964_Y - connect \$20 $sshl$libresoc.v:127895$4965_Y - connect \$23 $sshl$libresoc.v:127896$4966_Y - connect \$4 $sshl$libresoc.v:127897$4967_Y - connect \$3 $pos$libresoc.v:127898$4969_Y + connect \$9 $pos$libresoc.v:128031$4942_Y + connect \$11 $pos$libresoc.v:128032$4944_Y + connect \$14 $sshl$libresoc.v:128033$4945_Y + connect \$17 $sshl$libresoc.v:128034$4946_Y + connect \$1 $pos$libresoc.v:128035$4948_Y + connect \$20 $sshl$libresoc.v:128036$4949_Y + connect \$23 $sshl$libresoc.v:128037$4950_Y + connect \$4 $sshl$libresoc.v:128038$4951_Y + connect \$3 $pos$libresoc.v:128039$4953_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:128068.1-128321.10" +attribute \src "libresoc.v:128293.1-128630.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_bi" attribute \generator "nMigen" module \dec_bi$170 - attribute \src "libresoc.v:128295.3-128305.6" + attribute \src "libresoc.v:128560.3-128590.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:128306.3-128316.6" + attribute \src "libresoc.v:128591.3-128625.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:128157.3-128203.6" + attribute \src "libresoc.v:128382.3-128428.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:128204.3-128250.6" + attribute \src "libresoc.v:128429.3-128475.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:128069.7-128069.20" + attribute \src "libresoc.v:128294.7-128294.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128284.3-128294.6" + attribute \src "libresoc.v:128533.3-128559.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:128251.3-128261.6" + attribute \src "libresoc.v:128476.3-128490.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:128262.3-128272.6" + attribute \src "libresoc.v:128491.3-128509.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:128273.3-128283.6" + attribute \src "libresoc.v:128510.3-128532.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:128295.3-128305.6" + attribute \src "libresoc.v:128560.3-128590.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:128306.3-128316.6" + attribute \src "libresoc.v:128591.3-128625.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:128157.3-128203.6" + attribute \src "libresoc.v:128382.3-128428.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:128204.3-128250.6" + attribute \src "libresoc.v:128429.3-128475.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:128284.3-128294.6" + attribute \src "libresoc.v:128533.3-128559.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:128251.3-128261.6" + attribute \src "libresoc.v:128476.3-128490.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:128262.3-128272.6" + attribute \src "libresoc.v:128491.3-128509.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:128273.3-128283.6" + attribute \src "libresoc.v:128510.3-128532.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:128147.17-128147.105" - wire width 64 $extend$libresoc.v:128147$4979_Y - attribute \src "libresoc.v:128148.18-128148.108" - wire width 64 $extend$libresoc.v:128148$4981_Y - attribute \src "libresoc.v:128151.17-128151.105" - wire width 64 $extend$libresoc.v:128151$4985_Y - attribute \src "libresoc.v:128155.17-128155.102" - wire width 64 $extend$libresoc.v:128155$4990_Y - attribute \src "libresoc.v:128147.17-128147.105" - wire width 64 $pos$libresoc.v:128147$4980_Y - attribute \src "libresoc.v:128148.18-128148.108" - wire width 64 $pos$libresoc.v:128148$4982_Y - attribute \src "libresoc.v:128151.17-128151.105" - wire width 64 $pos$libresoc.v:128151$4986_Y - attribute \src "libresoc.v:128155.17-128155.102" - wire width 64 $pos$libresoc.v:128155$4991_Y - attribute \src "libresoc.v:128149.18-128149.115" - wire width 47 $sshl$libresoc.v:128149$4983_Y - attribute \src "libresoc.v:128150.18-128150.114" - wire width 27 $sshl$libresoc.v:128150$4984_Y - attribute \src "libresoc.v:128152.18-128152.114" - wire width 17 $sshl$libresoc.v:128152$4987_Y - attribute \src "libresoc.v:128153.18-128153.114" - wire width 17 $sshl$libresoc.v:128153$4988_Y - attribute \src "libresoc.v:128154.17-128154.109" - wire width 47 $sshl$libresoc.v:128154$4989_Y + attribute \src "libresoc.v:128372.17-128372.105" + wire width 64 $extend$libresoc.v:128372$4963_Y + attribute \src "libresoc.v:128373.18-128373.108" + wire width 64 $extend$libresoc.v:128373$4965_Y + attribute \src "libresoc.v:128376.17-128376.105" + wire width 64 $extend$libresoc.v:128376$4969_Y + attribute \src "libresoc.v:128380.17-128380.102" + wire width 64 $extend$libresoc.v:128380$4974_Y + attribute \src "libresoc.v:128372.17-128372.105" + wire width 64 $pos$libresoc.v:128372$4964_Y + attribute \src "libresoc.v:128373.18-128373.108" + wire width 64 $pos$libresoc.v:128373$4966_Y + attribute \src "libresoc.v:128376.17-128376.105" + wire width 64 $pos$libresoc.v:128376$4970_Y + attribute \src "libresoc.v:128380.17-128380.102" + wire width 64 $pos$libresoc.v:128380$4975_Y + attribute \src "libresoc.v:128374.18-128374.115" + wire width 47 $sshl$libresoc.v:128374$4967_Y + attribute \src "libresoc.v:128375.18-128375.114" + wire width 27 $sshl$libresoc.v:128375$4968_Y + attribute \src "libresoc.v:128377.18-128377.114" + wire width 17 $sshl$libresoc.v:128377$4971_Y + attribute \src "libresoc.v:128378.18-128378.114" + wire width 17 $sshl$libresoc.v:128378$4972_Y + attribute \src "libresoc.v:128379.17-128379.109" + wire width 47 $sshl$libresoc.v:128379$4973_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 @@ -201564,17 +201496,17 @@ module \dec_bi$170 wire width 16 input 4 \LDST_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \LDST_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok - attribute \src "libresoc.v:128069.7-128069.15" + attribute \src "libresoc.v:128294.7-128294.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -201591,80 +201523,80 @@ module \dec_bi$170 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:128147$4979 + cell $pos $extend$libresoc.v:128372$4963 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LDST_sh - connect \Y $extend$libresoc.v:128147$4979_Y + connect \Y $extend$libresoc.v:128372$4963_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:128148$4981 + cell $pos $extend$libresoc.v:128373$4965 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LDST_SH32 - connect \Y $extend$libresoc.v:128148$4981_Y + connect \Y $extend$libresoc.v:128373$4965_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:128151$4985 + cell $pos $extend$libresoc.v:128376$4969 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LDST_UI - connect \Y $extend$libresoc.v:128151$4985_Y + connect \Y $extend$libresoc.v:128376$4969_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $extend$libresoc.v:128155$4990 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $pos $extend$libresoc.v:128380$4974 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:128155$4990_Y + connect \Y $extend$libresoc.v:128380$4974_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:128147$4980 + cell $pos $pos$libresoc.v:128372$4964 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128147$4979_Y - connect \Y $pos$libresoc.v:128147$4980_Y + connect \A $extend$libresoc.v:128372$4963_Y + connect \Y $pos$libresoc.v:128372$4964_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:128148$4982 + cell $pos $pos$libresoc.v:128373$4966 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128148$4981_Y - connect \Y $pos$libresoc.v:128148$4982_Y + connect \A $extend$libresoc.v:128373$4965_Y + connect \Y $pos$libresoc.v:128373$4966_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:128151$4986 + cell $pos $pos$libresoc.v:128376$4970 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128151$4985_Y - connect \Y $pos$libresoc.v:128151$4986_Y + connect \A $extend$libresoc.v:128376$4969_Y + connect \Y $pos$libresoc.v:128376$4970_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $pos$libresoc.v:128155$4991 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $pos $pos$libresoc.v:128380$4975 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128155$4990_Y - connect \Y $pos$libresoc.v:128155$4991_Y + connect \A $extend$libresoc.v:128380$4974_Y + connect \Y $pos$libresoc.v:128380$4975_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:128149$4983 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" + cell $sshl $sshl$libresoc.v:128374$4967 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -201672,10 +201604,10 @@ module \dec_bi$170 parameter \Y_WIDTH 47 connect \A \LDST_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:128149$4983_Y + connect \Y $sshl$libresoc.v:128374$4967_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:128150$4984 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" + cell $sshl $sshl$libresoc.v:128375$4968 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -201683,10 +201615,10 @@ module \dec_bi$170 parameter \Y_WIDTH 27 connect \A \LDST_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:128150$4984_Y + connect \Y $sshl$libresoc.v:128375$4968_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:128152$4987 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" + cell $sshl $sshl$libresoc.v:128377$4971 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -201694,10 +201626,10 @@ module \dec_bi$170 parameter \Y_WIDTH 17 connect \A \LDST_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:128152$4987_Y + connect \Y $sshl$libresoc.v:128377$4971_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" - cell $sshl $sshl$libresoc.v:128153$4988 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" + cell $sshl $sshl$libresoc.v:128378$4972 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -201705,10 +201637,10 @@ module \dec_bi$170 parameter \Y_WIDTH 17 connect \A \LDST_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:128153$4988_Y + connect \Y $sshl$libresoc.v:128378$4972_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $sshl $sshl$libresoc.v:128154$4989 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + cell $sshl $sshl$libresoc.v:128379$4973 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -201716,28 +201648,28 @@ module \dec_bi$170 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:128154$4989_Y + connect \Y $sshl$libresoc.v:128379$4973_Y end - attribute \src "libresoc.v:128069.7-128069.20" - process $proc$libresoc.v:128069$5000 + attribute \src "libresoc.v:128294.7-128294.20" + process $proc$libresoc.v:128294$4984 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128157.3-128203.6" - process $proc$libresoc.v:128157$4992 + attribute \src "libresoc.v:128382.3-128428.6" + process $proc$libresoc.v:128382$4976 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:128158.5-128158.29" + attribute \src "libresoc.v:128383.5-128383.29" switch \initial - attribute \src "libresoc.v:128158.9-128158.17" + attribute \src "libresoc.v:128383.9-128383.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -201785,18 +201717,18 @@ module \dec_bi$170 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:128204.3-128250.6" - process $proc$libresoc.v:128204$4993 + attribute \src "libresoc.v:128429.3-128475.6" + process $proc$libresoc.v:128429$4977 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:128205.5-128205.29" + attribute \src "libresoc.v:128430.5-128430.29" switch \initial - attribute \src "libresoc.v:128205.9-128205.17" + attribute \src "libresoc.v:128430.9-128430.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -201844,20 +201776,23 @@ module \dec_bi$170 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:128251.3-128261.6" - process $proc$libresoc.v:128251$4994 + attribute \src "libresoc.v:128476.3-128490.6" + process $proc$libresoc.v:128476$4978 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:128252.5-128252.29" + attribute \src "libresoc.v:128477.5-128477.29" switch \initial - attribute \src "libresoc.v:128252.9-128252.17" + attribute \src "libresoc.v:128477.9-128477.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \LDST_SI @@ -201867,20 +201802,26 @@ module \dec_bi$170 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:128262.3-128272.6" - process $proc$libresoc.v:128262$4995 + attribute \src "libresoc.v:128491.3-128509.6" + process $proc$libresoc.v:128491$4979 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:128263.5-128263.29" + attribute \src "libresoc.v:128492.5-128492.29" switch \initial - attribute \src "libresoc.v:128263.9-128263.17" + attribute \src "libresoc.v:128492.9-128492.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] @@ -201890,20 +201831,29 @@ module \dec_bi$170 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:128273.3-128283.6" - process $proc$libresoc.v:128273$4996 + attribute \src "libresoc.v:128510.3-128532.6" + process $proc$libresoc.v:128510$4980 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:128274.5-128274.29" + attribute \src "libresoc.v:128511.5-128511.29" switch \initial - attribute \src "libresoc.v:128274.9-128274.17" + attribute \src "libresoc.v:128511.9-128511.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \LDST_UI @@ -201913,20 +201863,32 @@ module \dec_bi$170 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:128284.3-128294.6" - process $proc$libresoc.v:128284$4997 + attribute \src "libresoc.v:128533.3-128559.6" + process $proc$libresoc.v:128533$4981 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:128285.5-128285.29" + attribute \src "libresoc.v:128534.5-128534.29" switch \initial - attribute \src "libresoc.v:128285.9-128285.17" + attribute \src "libresoc.v:128534.9-128534.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] @@ -201936,20 +201898,35 @@ module \dec_bi$170 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:128295.3-128305.6" - process $proc$libresoc.v:128295$4998 + attribute \src "libresoc.v:128560.3-128590.6" + process $proc$libresoc.v:128560$4982 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:128296.5-128296.29" + attribute \src "libresoc.v:128561.5-128561.29" switch \initial - attribute \src "libresoc.v:128296.9-128296.17" + attribute \src "libresoc.v:128561.9-128561.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] @@ -201959,20 +201936,38 @@ module \dec_bi$170 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:128306.3-128316.6" - process $proc$libresoc.v:128306$4999 + attribute \src "libresoc.v:128591.3-128625.6" + process $proc$libresoc.v:128591$4983 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:128307.5-128307.29" + attribute \src "libresoc.v:128592.5-128592.29" switch \initial - attribute \src "libresoc.v:128307.9-128307.17" + attribute \src "libresoc.v:128592.9-128592.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] @@ -201982,72 +201977,72 @@ module \dec_bi$170 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:128147$4980_Y - connect \$11 $pos$libresoc.v:128148$4982_Y - connect \$14 $sshl$libresoc.v:128149$4983_Y - connect \$17 $sshl$libresoc.v:128150$4984_Y - connect \$1 $pos$libresoc.v:128151$4986_Y - connect \$20 $sshl$libresoc.v:128152$4987_Y - connect \$23 $sshl$libresoc.v:128153$4988_Y - connect \$4 $sshl$libresoc.v:128154$4989_Y - connect \$3 $pos$libresoc.v:128155$4991_Y + connect \$9 $pos$libresoc.v:128372$4964_Y + connect \$11 $pos$libresoc.v:128373$4966_Y + connect \$14 $sshl$libresoc.v:128374$4967_Y + connect \$17 $sshl$libresoc.v:128375$4968_Y + connect \$1 $pos$libresoc.v:128376$4970_Y + connect \$20 $sshl$libresoc.v:128377$4971_Y + connect \$23 $sshl$libresoc.v:128378$4972_Y + connect \$4 $sshl$libresoc.v:128379$4973_Y + connect \$3 $pos$libresoc.v:128380$4975_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:128325.1-128373.10" +attribute \src "libresoc.v:128634.1-128682.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" attribute \generator "nMigen" module \dec_c - attribute \src "libresoc.v:128326.7-128326.20" + attribute \src "libresoc.v:128635.7-128635.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128343.3-128357.6" + attribute \src "libresoc.v:128652.3-128666.6" wire width 5 $0\reg_c[4:0] - attribute \src "libresoc.v:128358.3-128372.6" + attribute \src "libresoc.v:128667.3-128681.6" wire $0\reg_c_ok[0:0] - attribute \src "libresoc.v:128343.3-128357.6" + attribute \src "libresoc.v:128652.3-128666.6" wire width 5 $1\reg_c[4:0] - attribute \src "libresoc.v:128358.3-128372.6" + attribute \src "libresoc.v:128667.3-128681.6" wire $1\reg_c_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 4 \RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \RS - attribute \src "libresoc.v:128326.7-128326.15" + attribute \src "libresoc.v:128635.7-128635.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 output 1 \reg_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \reg_c_ok attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:128326.7-128326.20" - process $proc$libresoc.v:128326$5003 + attribute \src "libresoc.v:128635.7-128635.20" + process $proc$libresoc.v:128635$4987 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128343.3-128357.6" - process $proc$libresoc.v:128343$5001 + attribute \src "libresoc.v:128652.3-128666.6" + process $proc$libresoc.v:128652$4985 assign { } { } assign { } { } assign $0\reg_c[4:0] $1\reg_c[4:0] - attribute \src "libresoc.v:128344.5-128344.29" + attribute \src "libresoc.v:128653.5-128653.29" switch \initial - attribute \src "libresoc.v:128344.9-128344.17" + attribute \src "libresoc.v:128653.9-128653.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202063,18 +202058,18 @@ module \dec_c sync always update \reg_c $0\reg_c[4:0] end - attribute \src "libresoc.v:128358.3-128372.6" - process $proc$libresoc.v:128358$5002 + attribute \src "libresoc.v:128667.3-128681.6" + process $proc$libresoc.v:128667$4986 assign { } { } assign { } { } assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] - attribute \src "libresoc.v:128359.5-128359.29" + attribute \src "libresoc.v:128668.5-128668.29" switch \initial - attribute \src "libresoc.v:128359.9-128359.17" + attribute \src "libresoc.v:128668.9-128668.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202091,76 +202086,76 @@ module \dec_c update \reg_c_ok $0\reg_c_ok[0:0] end end -attribute \src "libresoc.v:128377.1-128709.10" +attribute \src "libresoc.v:128686.1-129222.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" attribute \generator "nMigen" module \dec_cr_in - attribute \src "libresoc.v:128629.3-128659.6" + attribute \src "libresoc.v:129042.3-129076.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:128660.3-128670.6" + attribute \src "libresoc.v:129077.3-129107.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128562.3-128572.6" + attribute \src "libresoc.v:128875.3-128905.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128671.3-128681.6" + attribute \src "libresoc.v:129108.3-129138.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128592.3-128602.6" + attribute \src "libresoc.v:128953.3-128983.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128531.3-128561.6" + attribute \src "libresoc.v:128840.3-128874.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128573.3-128591.6" + attribute \src "libresoc.v:128906.3-128952.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:128603.3-128613.6" + attribute \src "libresoc.v:128984.3-129022.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128378.7-128378.20" + attribute \src "libresoc.v:128687.7-128687.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128682.3-128692.6" + attribute \src "libresoc.v:129139.3-129177.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:128693.3-128708.6" + attribute \src "libresoc.v:129178.3-129221.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:128614.3-128628.6" + attribute \src "libresoc.v:129023.3-129041.6" wire width 2 $0\sv_override[1:0] - attribute \src "libresoc.v:128629.3-128659.6" + attribute \src "libresoc.v:129042.3-129076.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:128660.3-128670.6" + attribute \src "libresoc.v:129077.3-129107.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128562.3-128572.6" + attribute \src "libresoc.v:128875.3-128905.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128671.3-128681.6" + attribute \src "libresoc.v:129108.3-129138.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128592.3-128602.6" + attribute \src "libresoc.v:128953.3-128983.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128531.3-128561.6" + attribute \src "libresoc.v:128840.3-128874.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128573.3-128591.6" + attribute \src "libresoc.v:128906.3-128952.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:128603.3-128613.6" + attribute \src "libresoc.v:128984.3-129022.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128682.3-128692.6" + attribute \src "libresoc.v:129139.3-129177.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:128693.3-128708.6" + attribute \src "libresoc.v:129178.3-129221.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:128614.3-128628.6" + attribute \src "libresoc.v:129023.3-129041.6" wire width 2 $1\sv_override[1:0] - attribute \src "libresoc.v:128573.3-128591.6" + attribute \src "libresoc.v:128906.3-128952.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:128693.3-128708.6" + attribute \src "libresoc.v:129178.3-129221.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:128524.17-128524.112" - wire $and$libresoc.v:128524$5005_Y - attribute \src "libresoc.v:128526.17-128526.112" - wire $and$libresoc.v:128526$5007_Y - attribute \src "libresoc.v:128523.17-128523.117" - wire $eq$libresoc.v:128523$5004_Y - attribute \src "libresoc.v:128525.17-128525.117" - wire $eq$libresoc.v:128525$5006_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \src "libresoc.v:128833.17-128833.112" + wire $and$libresoc.v:128833$4989_Y + attribute \src "libresoc.v:128835.17-128835.112" + wire $and$libresoc.v:128835$4991_Y + attribute \src "libresoc.v:128832.17-128832.117" + wire $eq$libresoc.v:128832$4988_Y + attribute \src "libresoc.v:128834.17-128834.117" + wire $eq$libresoc.v:128834$4990_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 12 \BA @@ -202176,25 +202171,25 @@ module \dec_cr_in wire width 8 input 14 \FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 input 17 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 5 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 7 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 8 \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 9 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 10 \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 6 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 output 3 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \cr_fxm_ok - attribute \src "libresoc.v:128378.7-128378.15" + attribute \src "libresoc.v:128687.7-128687.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" wire width 32 input 1 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -202273,7 +202268,7 @@ module \dec_cr_in attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 18 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:573" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 \ppick_i @@ -202288,12 +202283,12 @@ module \dec_cr_in attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" wire width 3 input 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" wire width 2 \sv_override - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - cell $and $and$libresoc.v:128524$5005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" + cell $and $and$libresoc.v:128833$4989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202301,10 +202296,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:128524$5005_Y + connect \Y $and$libresoc.v:128833$4989_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - cell $and $and$libresoc.v:128526$5007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" + cell $and $and$libresoc.v:128835$4991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202312,10 +202307,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:128526$5007_Y + connect \Y $and$libresoc.v:128835$4991_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - cell $eq $eq$libresoc.v:128523$5004 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" + cell $eq $eq$libresoc.v:128832$4988 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -202323,10 +202318,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:128523$5004_Y + connect \Y $eq$libresoc.v:128832$4988_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - cell $eq $eq$libresoc.v:128525$5006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" + cell $eq $eq$libresoc.v:128834$4990 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -202334,36 +202329,39 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:128525$5006_Y + connect \Y $eq$libresoc.v:128834$4990_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:128527.9-128530.4" + attribute \src "libresoc.v:128836.9-128839.4" cell \ppick \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:128378.7-128378.20" - process $proc$libresoc.v:128378$5019 + attribute \src "libresoc.v:128687.7-128687.20" + process $proc$libresoc.v:128687$5003 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128531.3-128561.6" - process $proc$libresoc.v:128531$5008 + attribute \src "libresoc.v:128840.3-128874.6" + process $proc$libresoc.v:128840$4992 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128532.5-128532.29" + attribute \src "libresoc.v:128841.5-128841.29" switch \initial - attribute \src "libresoc.v:128532.9-128532.17" + attribute \src "libresoc.v:128841.9-128841.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 @@ -202393,20 +202391,35 @@ module \dec_cr_in sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:128562.3-128572.6" - process $proc$libresoc.v:128562$5009 + attribute \src "libresoc.v:128875.3-128905.6" + process $proc$libresoc.v:128875$4993 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128563.5-128563.29" + attribute \src "libresoc.v:128876.5-128876.29" switch \initial - attribute \src "libresoc.v:128563.9-128563.17" + attribute \src "libresoc.v:128876.9-128876.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield_b_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_bitfield_b_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\cr_bitfield_b_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_bitfield_b_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_bitfield_b_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_bitfield_b_ok[0:0] 1'1 @@ -202416,24 +202429,45 @@ module \dec_cr_in sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:128573.3-128591.6" - process $proc$libresoc.v:128573$5010 + attribute \src "libresoc.v:128906.3-128952.6" + process $proc$libresoc.v:128906$4994 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:128574.5-128574.29" + attribute \src "libresoc.v:128907.5-128907.29" switch \initial - attribute \src "libresoc.v:128574.9-128574.17" + attribute \src "libresoc.v:128907.9-128907.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -202450,20 +202484,35 @@ module \dec_cr_in sync always update \cr_fxm $0\cr_fxm[7:0] end - attribute \src "libresoc.v:128592.3-128602.6" - process $proc$libresoc.v:128592$5011 + attribute \src "libresoc.v:128953.3-128983.6" + process $proc$libresoc.v:128953$4995 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128593.5-128593.29" + attribute \src "libresoc.v:128954.5-128954.29" switch \initial - attribute \src "libresoc.v:128593.9-128593.17" + attribute \src "libresoc.v:128954.9-128954.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_bitfield_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\cr_bitfield_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_bitfield_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_bitfield_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_bitfield_o_ok[0:0] 1'1 @@ -202473,20 +202522,41 @@ module \dec_cr_in sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:128603.3-128613.6" - process $proc$libresoc.v:128603$5012 + attribute \src "libresoc.v:128984.3-129022.6" + process $proc$libresoc.v:128984$4996 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128604.5-128604.29" + attribute \src "libresoc.v:128985.5-128985.29" switch \initial - attribute \src "libresoc.v:128604.9-128604.17" + attribute \src "libresoc.v:128985.9-128985.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm_ok[0:0] 1'1 @@ -202496,20 +202566,23 @@ module \dec_cr_in sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:128614.3-128628.6" - process $proc$libresoc.v:128614$5013 + attribute \src "libresoc.v:129023.3-129041.6" + process $proc$libresoc.v:129023$4997 assign { } { } assign { } { } assign $0\sv_override[1:0] $1\sv_override[1:0] - attribute \src "libresoc.v:128615.5-128615.29" + attribute \src "libresoc.v:129024.5-129024.29" switch \initial - attribute \src "libresoc.v:128615.9-128615.17" + attribute \src "libresoc.v:129024.9-129024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\sv_override[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\sv_override[1:0] 2'01 @@ -202523,20 +202596,23 @@ module \dec_cr_in sync always update \sv_override $0\sv_override[1:0] end - attribute \src "libresoc.v:128629.3-128659.6" - process $proc$libresoc.v:128629$5014 + attribute \src "libresoc.v:129042.3-129076.6" + process $proc$libresoc.v:129042$4998 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:128630.5-128630.29" + attribute \src "libresoc.v:129043.5-129043.29" switch \initial - attribute \src "libresoc.v:128630.9-128630.17" + attribute \src "libresoc.v:129043.9-129043.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield[2:0] 3'000 @@ -202566,20 +202642,35 @@ module \dec_cr_in sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:128660.3-128670.6" - process $proc$libresoc.v:128660$5015 + attribute \src "libresoc.v:129077.3-129107.6" + process $proc$libresoc.v:129077$4999 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128661.5-128661.29" + attribute \src "libresoc.v:129078.5-129078.29" switch \initial - attribute \src "libresoc.v:128661.9-128661.17" + attribute \src "libresoc.v:129078.9-129078.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield_b[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_bitfield_b[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\cr_bitfield_b[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_bitfield_b[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_bitfield_b[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_bitfield_b[2:0] \BB [4:2] @@ -202589,20 +202680,35 @@ module \dec_cr_in sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:128671.3-128681.6" - process $proc$libresoc.v:128671$5016 + attribute \src "libresoc.v:129108.3-129138.6" + process $proc$libresoc.v:129108$5000 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128672.5-128672.29" + attribute \src "libresoc.v:129109.5-129109.29" switch \initial - attribute \src "libresoc.v:128672.9-128672.17" + attribute \src "libresoc.v:129109.9-129109.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_bitfield_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\cr_bitfield_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_bitfield_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_bitfield_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_bitfield_o[2:0] \BT [4:2] @@ -202612,20 +202718,41 @@ module \dec_cr_in sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:128682.3-128692.6" - process $proc$libresoc.v:128682$5017 + attribute \src "libresoc.v:129139.3-129177.6" + process $proc$libresoc.v:129139$5001 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:128683.5-128683.29" + attribute \src "libresoc.v:129140.5-129140.29" switch \initial - attribute \src "libresoc.v:128683.9-128683.17" + attribute \src "libresoc.v:129140.9-129140.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\move_one[0:0] \insn_in [20] @@ -202635,24 +202762,45 @@ module \dec_cr_in sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:128693.3-128708.6" - process $proc$libresoc.v:128693$5018 + attribute \src "libresoc.v:129178.3-129221.6" + process $proc$libresoc.v:129178$5002 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:128694.5-128694.29" + attribute \src "libresoc.v:129179.5-129179.29" switch \initial - attribute \src "libresoc.v:128694.9-128694.17" + attribute \src "libresoc.v:129179.9-129179.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -202667,63 +202815,63 @@ module \dec_cr_in sync always update \ppick_i $0\ppick_i[7:0] end - connect \$1 $eq$libresoc.v:128523$5004_Y - connect \$3 $and$libresoc.v:128524$5005_Y - connect \$5 $eq$libresoc.v:128525$5006_Y - connect \$7 $and$libresoc.v:128526$5007_Y + connect \$1 $eq$libresoc.v:128832$4988_Y + connect \$3 $and$libresoc.v:128833$4989_Y + connect \$5 $eq$libresoc.v:128834$4990_Y + connect \$7 $and$libresoc.v:128835$4991_Y end -attribute \src "libresoc.v:128713.1-128983.10" +attribute \src "libresoc.v:129226.1-129588.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" attribute \generator "nMigen" module \dec_cr_out - attribute \src "libresoc.v:128893.3-128915.6" + attribute \src "libresoc.v:129434.3-129460.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:128844.3-128866.6" + attribute \src "libresoc.v:129357.3-129383.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128948.3-128982.6" + attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:128867.3-128877.6" + attribute \src "libresoc.v:129384.3-129414.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128714.7-128714.20" + attribute \src "libresoc.v:129227.7-129227.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128916.3-128926.6" + attribute \src "libresoc.v:129461.3-129491.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:128927.3-128947.6" + attribute \src "libresoc.v:129492.3-129532.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:128878.3-128892.6" + attribute \src "libresoc.v:129415.3-129433.6" wire width 2 $0\sv_override[1:0] - attribute \src "libresoc.v:128893.3-128915.6" + attribute \src "libresoc.v:129434.3-129460.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:128844.3-128866.6" + attribute \src "libresoc.v:129357.3-129383.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128948.3-128982.6" + attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:128867.3-128877.6" + attribute \src "libresoc.v:129384.3-129414.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128916.3-128926.6" + attribute \src "libresoc.v:129461.3-129491.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:128927.3-128947.6" + attribute \src "libresoc.v:129492.3-129532.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:128878.3-128892.6" + attribute \src "libresoc.v:129415.3-129433.6" wire width 2 $1\sv_override[1:0] - attribute \src "libresoc.v:128948.3-128982.6" + attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:128927.3-128947.6" + attribute \src "libresoc.v:129492.3-129532.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:128948.3-128982.6" + attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:128927.3-128947.6" + attribute \src "libresoc.v:129492.3-129532.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:128948.3-128982.6" + attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:128837.17-128837.117" - wire $eq$libresoc.v:128837$5020_Y - attribute \src "libresoc.v:128838.17-128838.117" - wire $eq$libresoc.v:128838$5021_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + attribute \src "libresoc.v:129350.17-129350.117" + wire $eq$libresoc.v:129350$5004_Y + attribute \src "libresoc.v:129351.17-129351.117" + wire $eq$libresoc.v:129351$5005_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 input 8 \FXM @@ -202731,17 +202879,17 @@ module \dec_cr_out wire width 5 input 10 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 input 9 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 6 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 7 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 output 4 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \cr_fxm_ok - attribute \src "libresoc.v:128714.7-128714.15" + attribute \src "libresoc.v:129227.7-129227.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:597" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" wire width 32 input 1 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -202820,7 +202968,7 @@ module \dec_cr_out attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 11 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:638" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:659" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \ppick_en_o @@ -202828,7 +202976,7 @@ module \dec_cr_out wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" wire input 3 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -202837,12 +202985,12 @@ module \dec_cr_out attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:617" wire width 3 input 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:600" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:621" wire width 2 \sv_override - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" - cell $eq $eq$libresoc.v:128837$5020 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" + cell $eq $eq$libresoc.v:129350$5004 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -202850,10 +202998,10 @@ module \dec_cr_out parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:128837$5020_Y + connect \Y $eq$libresoc.v:129350$5004_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" - cell $eq $eq$libresoc.v:128838$5021 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" + cell $eq $eq$libresoc.v:129351$5005 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -202861,37 +203009,40 @@ module \dec_cr_out parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:128838$5021_Y + connect \Y $eq$libresoc.v:129351$5005_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:128839.15-128843.4" + attribute \src "libresoc.v:129352.15-129356.4" cell \ppick$175 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:128714.7-128714.20" - process $proc$libresoc.v:128714$5029 + attribute \src "libresoc.v:129227.7-129227.20" + process $proc$libresoc.v:129227$5013 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128844.3-128866.6" - process $proc$libresoc.v:128844$5022 + attribute \src "libresoc.v:129357.3-129383.6" + process $proc$libresoc.v:129357$5006 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128845.5-128845.29" + attribute \src "libresoc.v:129358.5-129358.29" switch \initial - attribute \src "libresoc.v:128845.9-128845.17" + attribute \src "libresoc.v:129358.9-129358.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield_ok[0:0] \rc_in @@ -202913,20 +203064,35 @@ module \dec_cr_out sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:128867.3-128877.6" - process $proc$libresoc.v:128867$5023 + attribute \src "libresoc.v:129384.3-129414.6" + process $proc$libresoc.v:129384$5007 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128868.5-128868.29" + attribute \src "libresoc.v:129385.5-129385.29" switch \initial - attribute \src "libresoc.v:128868.9-128868.17" + attribute \src "libresoc.v:129385.9-129385.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm_ok[0:0] 1'1 @@ -202936,20 +203102,23 @@ module \dec_cr_out sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:128878.3-128892.6" - process $proc$libresoc.v:128878$5024 + attribute \src "libresoc.v:129415.3-129433.6" + process $proc$libresoc.v:129415$5008 assign { } { } assign { } { } assign $0\sv_override[1:0] $1\sv_override[1:0] - attribute \src "libresoc.v:128879.5-128879.29" + attribute \src "libresoc.v:129416.5-129416.29" switch \initial - attribute \src "libresoc.v:128879.9-128879.17" + attribute \src "libresoc.v:129416.9-129416.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\sv_override[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\sv_override[1:0] 2'01 @@ -202963,20 +203132,23 @@ module \dec_cr_out sync always update \sv_override $0\sv_override[1:0] end - attribute \src "libresoc.v:128893.3-128915.6" - process $proc$libresoc.v:128893$5025 + attribute \src "libresoc.v:129434.3-129460.6" + process $proc$libresoc.v:129434$5009 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:128894.5-128894.29" + attribute \src "libresoc.v:129435.5-129435.29" switch \initial - attribute \src "libresoc.v:128894.9-128894.17" + attribute \src "libresoc.v:129435.9-129435.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield[2:0] 3'000 @@ -202998,20 +203170,35 @@ module \dec_cr_out sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:128916.3-128926.6" - process $proc$libresoc.v:128916$5026 + attribute \src "libresoc.v:129461.3-129491.6" + process $proc$libresoc.v:129461$5010 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:128917.5-128917.29" + attribute \src "libresoc.v:129462.5-129462.29" switch \initial - attribute \src "libresoc.v:128917.9-128917.17" + attribute \src "libresoc.v:129462.9-129462.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\move_one[0:0] \insn_in [20] @@ -203021,30 +203208,45 @@ module \dec_cr_out sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:128927.3-128947.6" - process $proc$libresoc.v:128927$5027 + attribute \src "libresoc.v:129492.3-129532.6" + process $proc$libresoc.v:129492$5011 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:128928.5-128928.29" + attribute \src "libresoc.v:129493.5-129493.29" switch \initial - attribute \src "libresoc.v:128928.9-128928.17" + attribute \src "libresoc.v:129493.9-129493.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -203062,36 +203264,51 @@ module \dec_cr_out sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:128948.3-128982.6" - process $proc$libresoc.v:128948$5028 + attribute \src "libresoc.v:129533.3-129587.6" + process $proc$libresoc.v:129533$5012 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:128949.5-128949.29" + attribute \src "libresoc.v:129534.5-129534.29" switch \initial - attribute \src "libresoc.v:128949.9-128949.17" + attribute \src "libresoc.v:129534.9-129534.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:644" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -203118,81 +203335,81 @@ module \dec_cr_out sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:128837$5020_Y - connect \$3 $eq$libresoc.v:128838$5021_Y + connect \$1 $eq$libresoc.v:129350$5004_Y + connect \$3 $eq$libresoc.v:129351$5005_Y end -attribute \src "libresoc.v:128987.1-129472.10" +attribute \src "libresoc.v:129592.1-130109.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o" attribute \generator "nMigen" module \dec_o - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130062.3-130108.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:128988.7-128988.20" + attribute \src "libresoc.v:129593.7-129593.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129359.3-129373.6" + attribute \src "libresoc.v:129964.3-129978.6" wire width 5 $0\reg_o[4:0] - attribute \src "libresoc.v:129374.3-129388.6" + attribute \src "libresoc.v:129979.3-129993.6" wire $0\reg_o_ok[0:0] - attribute \src "libresoc.v:129389.3-129399.6" + attribute \src "libresoc.v:129994.3-130012.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:129416.3-129432.6" + attribute \src "libresoc.v:130037.3-130061.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:129416.3-129432.6" + attribute \src "libresoc.v:130037.3-130061.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:129400.3-129415.6" + attribute \src "libresoc.v:130013.3-130036.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130062.3-130108.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:129359.3-129373.6" + attribute \src "libresoc.v:129964.3-129978.6" wire width 5 $1\reg_o[4:0] - attribute \src "libresoc.v:129374.3-129388.6" + attribute \src "libresoc.v:129979.3-129993.6" wire $1\reg_o_ok[0:0] - attribute \src "libresoc.v:129389.3-129399.6" + attribute \src "libresoc.v:129994.3-130012.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:129416.3-129432.6" + attribute \src "libresoc.v:130037.3-130061.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:129416.3-129432.6" + attribute \src "libresoc.v:130037.3-130061.6" wire $1\spr_o_ok[0:0] - attribute \src "libresoc.v:129400.3-129415.6" + attribute \src "libresoc.v:130013.3-130036.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $2\fast_o[2:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130062.3-130108.6" wire $2\fast_o_ok[0:0] - attribute \src "libresoc.v:129416.3-129432.6" + attribute \src "libresoc.v:130037.3-130061.6" wire width 10 $2\spr_o[9:0] - attribute \src "libresoc.v:129416.3-129432.6" + attribute \src "libresoc.v:130037.3-130061.6" wire $2\spr_o_ok[0:0] - attribute \src "libresoc.v:129400.3-129415.6" + attribute \src "libresoc.v:130013.3-130036.6" wire width 10 $2\sprmap_spr_i[9:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $3\fast_o[2:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130062.3-130108.6" wire $3\fast_o_ok[0:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $4\fast_o[2:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130062.3-130108.6" wire $4\fast_o_ok[0:0] - attribute \src "libresoc.v:129348.17-129348.117" - wire $eq$libresoc.v:129348$5030_Y - attribute \src "libresoc.v:129349.17-129349.117" - wire $eq$libresoc.v:129349$5031_Y - attribute \src "libresoc.v:129350.17-129350.117" - wire $eq$libresoc.v:129350$5032_Y - attribute \src "libresoc.v:129351.17-129351.104" - wire $not$libresoc.v:129351$5033_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + attribute \src "libresoc.v:129953.17-129953.117" + wire $eq$libresoc.v:129953$5014_Y + attribute \src "libresoc.v:129954.17-129954.117" + wire $eq$libresoc.v:129954$5015_Y + attribute \src "libresoc.v:129955.17-129955.117" + wire $eq$libresoc.v:129955$5016_Y + attribute \src "libresoc.v:129956.17-129956.104" + wire $not$libresoc.v:129956$5017_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 11 \BO @@ -203202,11 +203419,11 @@ module \dec_o wire width 5 input 9 \RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 input 1 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 7 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 8 \fast_o_ok - attribute \src "libresoc.v:128988.7-128988.15" + attribute \src "libresoc.v:129593.7-129593.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -203285,9 +203502,9 @@ module \dec_o attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 12 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 output 3 \reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \reg_o_ok attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -203295,9 +203512,9 @@ module \dec_o attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" wire width 3 input 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -203413,15 +203630,15 @@ module \dec_o attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 output 5 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 6 \spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \sprmap_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \sprmap_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" wire width 10 \sprmap_spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -203537,12 +203754,12 @@ module \dec_o attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \sprmap_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" - cell $eq $eq$libresoc.v:129348$5030 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" + cell $eq $eq$libresoc.v:129953$5014 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -203550,10 +203767,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:129348$5030_Y + connect \Y $eq$libresoc.v:129953$5014_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" - cell $eq $eq$libresoc.v:129349$5031 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" + cell $eq $eq$libresoc.v:129954$5015 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -203561,10 +203778,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:129349$5031_Y + connect \Y $eq$libresoc.v:129954$5015_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" - cell $eq $eq$libresoc.v:129350$5032 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" + cell $eq $eq$libresoc.v:129955$5016 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -203572,18 +203789,18 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:129350$5032_Y + connect \Y $eq$libresoc.v:129955$5016_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" - cell $not $not$libresoc.v:129351$5033 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" + cell $not $not$libresoc.v:129956$5017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:129351$5033_Y + connect \Y $not$libresoc.v:129956$5017_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:129352.16-129358.4" + attribute \src "libresoc.v:129957.16-129963.4" cell \sprmap$174 \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok @@ -203591,26 +203808,26 @@ module \dec_o connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:128988.7-128988.20" - process $proc$libresoc.v:128988$5040 + attribute \src "libresoc.v:129593.7-129593.20" + process $proc$libresoc.v:129593$5024 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129359.3-129373.6" - process $proc$libresoc.v:129359$5034 + attribute \src "libresoc.v:129964.3-129978.6" + process $proc$libresoc.v:129964$5018 assign { } { } assign { } { } assign $0\reg_o[4:0] $1\reg_o[4:0] - attribute \src "libresoc.v:129360.5-129360.29" + attribute \src "libresoc.v:129965.5-129965.29" switch \initial - attribute \src "libresoc.v:129360.9-129360.17" + attribute \src "libresoc.v:129965.9-129965.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -203626,18 +203843,18 @@ module \dec_o sync always update \reg_o $0\reg_o[4:0] end - attribute \src "libresoc.v:129374.3-129388.6" - process $proc$libresoc.v:129374$5035 + attribute \src "libresoc.v:129979.3-129993.6" + process $proc$libresoc.v:129979$5019 assign { } { } assign { } { } assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:129375.5-129375.29" + attribute \src "libresoc.v:129980.5-129980.29" switch \initial - attribute \src "libresoc.v:129375.9-129375.17" + attribute \src "libresoc.v:129980.9-129980.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -203653,20 +203870,26 @@ module \dec_o sync always update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "libresoc.v:129389.3-129399.6" - process $proc$libresoc.v:129389$5036 + attribute \src "libresoc.v:129994.3-130012.6" + process $proc$libresoc.v:129994$5020 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:129390.5-129390.29" + attribute \src "libresoc.v:129995.5-129995.29" switch \initial - attribute \src "libresoc.v:129390.9-129390.17" + attribute \src "libresoc.v:129995.9-129995.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\spr[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\spr[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } @@ -203676,24 +203899,30 @@ module \dec_o sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:129400.3-129415.6" - process $proc$libresoc.v:129400$5037 + attribute \src "libresoc.v:130013.3-130036.6" + process $proc$libresoc.v:130013$5021 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:129401.5-129401.29" + attribute \src "libresoc.v:130014.5-130014.29" switch \initial - attribute \src "libresoc.v:129401.9-129401.17" + attribute \src "libresoc.v:130014.9-130014.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\sprmap_spr_i[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\sprmap_spr_i[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -203708,29 +203937,37 @@ module \dec_o sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:129416.3-129432.6" - process $proc$libresoc.v:129416$5038 + attribute \src "libresoc.v:130037.3-130061.6" + process $proc$libresoc.v:130037$5022 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:129417.5-129417.29" + attribute \src "libresoc.v:130038.5-130038.29" switch \initial - attribute \src "libresoc.v:129417.9-129417.17" + attribute \src "libresoc.v:130038.9-130038.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\spr_o[9:0] 10'0000000000 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\spr_o[9:0] 10'0000000000 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign { } { } assign $1\spr_o[9:0] $2\spr_o[9:0] assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -203749,8 +203986,8 @@ module \dec_o update \spr_o $0\spr_o[9:0] update \spr_o_ok $0\spr_o_ok[0:0] end - attribute \src "libresoc.v:129433.3-129471.6" - process $proc$libresoc.v:129433$5039 + attribute \src "libresoc.v:130062.3-130108.6" + process $proc$libresoc.v:130062$5023 assign { } { } assign { } { } assign { } { } @@ -203759,21 +203996,29 @@ module \dec_o assign { } { } assign $0\fast_o[2:0] $3\fast_o[2:0] assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] - attribute \src "libresoc.v:129434.5-129434.29" + attribute \src "libresoc.v:130063.5-130063.29" switch \initial - attribute \src "libresoc.v:129434.9-129434.17" + attribute \src "libresoc.v:130063.9-130063.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\fast_o[2:0] 3'000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\fast_o[2:0] 3'000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign { } { } assign $1\fast_o[2:0] $2\fast_o[2:0] assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -203788,7 +204033,7 @@ module \dec_o assign $1\fast_o[2:0] 3'000 assign $1\fast_o_ok[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:361" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:382" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0001000 @@ -203796,7 +204041,7 @@ module \dec_o assign { } { } assign $3\fast_o[2:0] $4\fast_o[2:0] assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -203822,53 +204067,53 @@ module \dec_o update \fast_o $0\fast_o[2:0] update \fast_o_ok $0\fast_o_ok[0:0] end - connect \$1 $eq$libresoc.v:129348$5030_Y - connect \$3 $eq$libresoc.v:129349$5031_Y - connect \$5 $eq$libresoc.v:129350$5032_Y - connect \$7 $not$libresoc.v:129351$5033_Y + connect \$1 $eq$libresoc.v:129953$5014_Y + connect \$3 $eq$libresoc.v:129954$5015_Y + connect \$5 $eq$libresoc.v:129955$5016_Y + connect \$7 $not$libresoc.v:129956$5017_Y end -attribute \src "libresoc.v:129476.1-129644.10" +attribute \src "libresoc.v:130113.1-130281.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" attribute \generator "nMigen" module \dec_o2 - attribute \src "libresoc.v:129604.3-129623.6" + attribute \src "libresoc.v:130241.3-130260.6" wire width 3 $0\fast_o2[2:0] - attribute \src "libresoc.v:129624.3-129643.6" + attribute \src "libresoc.v:130261.3-130280.6" wire $0\fast_o2_ok[0:0] - attribute \src "libresoc.v:129477.7-129477.20" + attribute \src "libresoc.v:130114.7-130114.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129584.3-129593.6" + attribute \src "libresoc.v:130221.3-130230.6" wire width 5 $0\reg_o2[4:0] - attribute \src "libresoc.v:129594.3-129603.6" + attribute \src "libresoc.v:130231.3-130240.6" wire $0\reg_o2_ok[0:0] - attribute \src "libresoc.v:129604.3-129623.6" + attribute \src "libresoc.v:130241.3-130260.6" wire width 3 $1\fast_o2[2:0] - attribute \src "libresoc.v:129624.3-129643.6" + attribute \src "libresoc.v:130261.3-130280.6" wire $1\fast_o2_ok[0:0] - attribute \src "libresoc.v:129584.3-129593.6" + attribute \src "libresoc.v:130221.3-130230.6" wire width 5 $1\reg_o2[4:0] - attribute \src "libresoc.v:129594.3-129603.6" + attribute \src "libresoc.v:130231.3-130240.6" wire $1\reg_o2_ok[0:0] - attribute \src "libresoc.v:129604.3-129623.6" + attribute \src "libresoc.v:130241.3-130260.6" wire width 3 $2\fast_o2[2:0] - attribute \src "libresoc.v:129624.3-129643.6" + attribute \src "libresoc.v:130261.3-130280.6" wire $2\fast_o2_ok[0:0] - attribute \src "libresoc.v:129582.17-129582.108" - wire $eq$libresoc.v:129582$5041_Y - attribute \src "libresoc.v:129583.17-129583.108" - wire $eq$libresoc.v:129583$5042_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" + attribute \src "libresoc.v:130219.17-130219.108" + wire $eq$libresoc.v:130219$5025_Y + attribute \src "libresoc.v:130220.17-130220.108" + wire $eq$libresoc.v:130220$5026_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 7 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 4 \fast_o2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \fast_o2_ok - attribute \src "libresoc.v:129477.7-129477.15" + attribute \src "libresoc.v:130114.7-130114.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -203947,11 +204192,11 @@ module \dec_o2 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 8 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" wire input 1 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 output 2 \reg_o2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \reg_o2_ok attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" @@ -203960,8 +204205,8 @@ module \dec_o2 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 input 6 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" - cell $eq $eq$libresoc.v:129582$5041 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" + cell $eq $eq$libresoc.v:130219$5025 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -203969,10 +204214,10 @@ module \dec_o2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 - connect \Y $eq$libresoc.v:129582$5041_Y + connect \Y $eq$libresoc.v:130219$5025_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" - cell $eq $eq$libresoc.v:129583$5042 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" + cell $eq $eq$libresoc.v:130220$5026 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -203980,28 +204225,28 @@ module \dec_o2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 - connect \Y $eq$libresoc.v:129583$5042_Y + connect \Y $eq$libresoc.v:130220$5026_Y end - attribute \src "libresoc.v:129477.7-129477.20" - process $proc$libresoc.v:129477$5047 + attribute \src "libresoc.v:130114.7-130114.20" + process $proc$libresoc.v:130114$5031 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129584.3-129593.6" - process $proc$libresoc.v:129584$5043 + attribute \src "libresoc.v:130221.3-130230.6" + process $proc$libresoc.v:130221$5027 assign { } { } assign { } { } assign $0\reg_o2[4:0] $1\reg_o2[4:0] - attribute \src "libresoc.v:129585.5-129585.29" + attribute \src "libresoc.v:130222.5-130222.29" switch \initial - attribute \src "libresoc.v:129585.9-129585.17" + attribute \src "libresoc.v:130222.9-130222.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -204013,18 +204258,18 @@ module \dec_o2 sync always update \reg_o2 $0\reg_o2[4:0] end - attribute \src "libresoc.v:129594.3-129603.6" - process $proc$libresoc.v:129594$5044 + attribute \src "libresoc.v:130231.3-130240.6" + process $proc$libresoc.v:130231$5028 assign { } { } assign { } { } assign $0\reg_o2_ok[0:0] $1\reg_o2_ok[0:0] - attribute \src "libresoc.v:129595.5-129595.29" + attribute \src "libresoc.v:130232.5-130232.29" switch \initial - attribute \src "libresoc.v:129595.9-129595.17" + attribute \src "libresoc.v:130232.9-130232.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -204036,24 +204281,24 @@ module \dec_o2 sync always update \reg_o2_ok $0\reg_o2_ok[0:0] end - attribute \src "libresoc.v:129604.3-129623.6" - process $proc$libresoc.v:129604$5045 + attribute \src "libresoc.v:130241.3-130260.6" + process $proc$libresoc.v:130241$5029 assign { } { } assign { } { } assign $0\fast_o2[2:0] $1\fast_o2[2:0] - attribute \src "libresoc.v:129605.5-129605.29" + attribute \src "libresoc.v:130242.5-130242.29" switch \initial - attribute \src "libresoc.v:129605.9-129605.17" + attribute \src "libresoc.v:130242.9-130242.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:438" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } assign $1\fast_o2[2:0] $2\fast_o2[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:421" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -204072,24 +204317,24 @@ module \dec_o2 sync always update \fast_o2 $0\fast_o2[2:0] end - attribute \src "libresoc.v:129624.3-129643.6" - process $proc$libresoc.v:129624$5046 + attribute \src "libresoc.v:130261.3-130280.6" + process $proc$libresoc.v:130261$5030 assign { } { } assign { } { } assign $0\fast_o2_ok[0:0] $1\fast_o2_ok[0:0] - attribute \src "libresoc.v:129625.5-129625.29" + attribute \src "libresoc.v:130262.5-130262.29" switch \initial - attribute \src "libresoc.v:129625.9-129625.17" + attribute \src "libresoc.v:130262.9-130262.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:438" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } assign $1\fast_o2_ok[0:0] $2\fast_o2_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:421" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -204108,27 +204353,27 @@ module \dec_o2 sync always update \fast_o2_ok $0\fast_o2_ok[0:0] end - connect \$1 $eq$libresoc.v:129582$5041_Y - connect \$3 $eq$libresoc.v:129583$5042_Y + connect \$1 $eq$libresoc.v:130219$5025_Y + connect \$3 $eq$libresoc.v:130220$5026_Y end -attribute \src "libresoc.v:129648.1-129783.10" +attribute \src "libresoc.v:130285.1-130420.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" attribute \generator "nMigen" module \dec_oe - attribute \src "libresoc.v:129649.7-129649.20" + attribute \src "libresoc.v:130286.7-130286.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129741.3-129761.6" + attribute \src "libresoc.v:130378.3-130398.6" wire $0\oe[0:0] - attribute \src "libresoc.v:129762.3-129782.6" + attribute \src "libresoc.v:130399.3-130419.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:129741.3-129761.6" + attribute \src "libresoc.v:130378.3-130398.6" wire $1\oe[0:0] - attribute \src "libresoc.v:129762.3-129782.6" + attribute \src "libresoc.v:130399.3-130419.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:129741.3-129761.6" + attribute \src "libresoc.v:130378.3-130398.6" wire $2\oe[0:0] - attribute \src "libresoc.v:129762.3-129782.6" + attribute \src "libresoc.v:130399.3-130419.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \ALU_OE @@ -204209,38 +204454,38 @@ module \dec_oe attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \ALU_internal_op - attribute \src "libresoc.v:129649.7-129649.15" + attribute \src "libresoc.v:130286.7-130286.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:129649.7-129649.20" - process $proc$libresoc.v:129649$5050 + attribute \src "libresoc.v:130286.7-130286.20" + process $proc$libresoc.v:130286$5034 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129741.3-129761.6" - process $proc$libresoc.v:129741$5048 + attribute \src "libresoc.v:130378.3-130398.6" + process $proc$libresoc.v:130378$5032 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:129742.5-129742.29" + attribute \src "libresoc.v:130379.5-130379.29" switch \initial - attribute \src "libresoc.v:129742.9-129742.17" + attribute \src "libresoc.v:130379.9-130379.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -204249,7 +204494,7 @@ module \dec_oe case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204262,18 +204507,18 @@ module \dec_oe sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:129762.3-129782.6" - process $proc$libresoc.v:129762$5049 + attribute \src "libresoc.v:130399.3-130419.6" + process $proc$libresoc.v:130399$5033 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:129763.5-129763.29" + attribute \src "libresoc.v:130400.5-130400.29" switch \initial - attribute \src "libresoc.v:129763.9-129763.17" + attribute \src "libresoc.v:130400.9-130400.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -204282,7 +204527,7 @@ module \dec_oe case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204296,24 +204541,24 @@ module \dec_oe update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:129787.1-129920.10" +attribute \src "libresoc.v:130424.1-130557.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" attribute \generator "nMigen" module \dec_oe$140 - attribute \src "libresoc.v:129788.7-129788.20" + attribute \src "libresoc.v:130425.7-130425.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129878.3-129898.6" + attribute \src "libresoc.v:130515.3-130535.6" wire $0\oe[0:0] - attribute \src "libresoc.v:129899.3-129919.6" + attribute \src "libresoc.v:130536.3-130556.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:129878.3-129898.6" + attribute \src "libresoc.v:130515.3-130535.6" wire $1\oe[0:0] - attribute \src "libresoc.v:129899.3-129919.6" + attribute \src "libresoc.v:130536.3-130556.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:129878.3-129898.6" + attribute \src "libresoc.v:130515.3-130535.6" wire $2\oe[0:0] - attribute \src "libresoc.v:129899.3-129919.6" + attribute \src "libresoc.v:130536.3-130556.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \CR_OE @@ -204394,38 +204639,38 @@ module \dec_oe$140 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \CR_internal_op - attribute \src "libresoc.v:129788.7-129788.15" + attribute \src "libresoc.v:130425.7-130425.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:129788.7-129788.20" - process $proc$libresoc.v:129788$5053 + attribute \src "libresoc.v:130425.7-130425.20" + process $proc$libresoc.v:130425$5037 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129878.3-129898.6" - process $proc$libresoc.v:129878$5051 + attribute \src "libresoc.v:130515.3-130535.6" + process $proc$libresoc.v:130515$5035 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:129879.5-129879.29" + attribute \src "libresoc.v:130516.5-130516.29" switch \initial - attribute \src "libresoc.v:129879.9-129879.17" + attribute \src "libresoc.v:130516.9-130516.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -204434,7 +204679,7 @@ module \dec_oe$140 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204447,18 +204692,18 @@ module \dec_oe$140 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:129899.3-129919.6" - process $proc$libresoc.v:129899$5052 + attribute \src "libresoc.v:130536.3-130556.6" + process $proc$libresoc.v:130536$5036 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:129900.5-129900.29" + attribute \src "libresoc.v:130537.5-130537.29" switch \initial - attribute \src "libresoc.v:129900.9-129900.17" + attribute \src "libresoc.v:130537.9-130537.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -204467,7 +204712,7 @@ module \dec_oe$140 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204481,24 +204726,24 @@ module \dec_oe$140 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:129924.1-130057.10" +attribute \src "libresoc.v:130561.1-130694.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" attribute \generator "nMigen" module \dec_oe$143 - attribute \src "libresoc.v:129925.7-129925.20" + attribute \src "libresoc.v:130562.7-130562.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130015.3-130035.6" + attribute \src "libresoc.v:130652.3-130672.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130036.3-130056.6" + attribute \src "libresoc.v:130673.3-130693.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130015.3-130035.6" + attribute \src "libresoc.v:130652.3-130672.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130036.3-130056.6" + attribute \src "libresoc.v:130673.3-130693.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130015.3-130035.6" + attribute \src "libresoc.v:130652.3-130672.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130036.3-130056.6" + attribute \src "libresoc.v:130673.3-130693.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \BRANCH_OE @@ -204579,38 +204824,38 @@ module \dec_oe$143 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \BRANCH_internal_op - attribute \src "libresoc.v:129925.7-129925.15" + attribute \src "libresoc.v:130562.7-130562.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:129925.7-129925.20" - process $proc$libresoc.v:129925$5056 + attribute \src "libresoc.v:130562.7-130562.20" + process $proc$libresoc.v:130562$5040 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130015.3-130035.6" - process $proc$libresoc.v:130015$5054 + attribute \src "libresoc.v:130652.3-130672.6" + process $proc$libresoc.v:130652$5038 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130016.5-130016.29" + attribute \src "libresoc.v:130653.5-130653.29" switch \initial - attribute \src "libresoc.v:130016.9-130016.17" + attribute \src "libresoc.v:130653.9-130653.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -204619,7 +204864,7 @@ module \dec_oe$143 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204632,18 +204877,18 @@ module \dec_oe$143 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130036.3-130056.6" - process $proc$libresoc.v:130036$5055 + attribute \src "libresoc.v:130673.3-130693.6" + process $proc$libresoc.v:130673$5039 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130037.5-130037.29" + attribute \src "libresoc.v:130674.5-130674.29" switch \initial - attribute \src "libresoc.v:130037.9-130037.17" + attribute \src "libresoc.v:130674.9-130674.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -204652,7 +204897,7 @@ module \dec_oe$143 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204666,24 +204911,24 @@ module \dec_oe$143 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130061.1-130196.10" +attribute \src "libresoc.v:130698.1-130833.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" attribute \generator "nMigen" module \dec_oe$147 - attribute \src "libresoc.v:130062.7-130062.20" + attribute \src "libresoc.v:130699.7-130699.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130154.3-130174.6" + attribute \src "libresoc.v:130791.3-130811.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130175.3-130195.6" + attribute \src "libresoc.v:130812.3-130832.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130154.3-130174.6" + attribute \src "libresoc.v:130791.3-130811.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130175.3-130195.6" + attribute \src "libresoc.v:130812.3-130832.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130154.3-130174.6" + attribute \src "libresoc.v:130791.3-130811.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130175.3-130195.6" + attribute \src "libresoc.v:130812.3-130832.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \LOGICAL_OE @@ -204764,38 +205009,38 @@ module \dec_oe$147 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \LOGICAL_internal_op - attribute \src "libresoc.v:130062.7-130062.15" + attribute \src "libresoc.v:130699.7-130699.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:130062.7-130062.20" - process $proc$libresoc.v:130062$5059 + attribute \src "libresoc.v:130699.7-130699.20" + process $proc$libresoc.v:130699$5043 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130154.3-130174.6" - process $proc$libresoc.v:130154$5057 + attribute \src "libresoc.v:130791.3-130811.6" + process $proc$libresoc.v:130791$5041 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130155.5-130155.29" + attribute \src "libresoc.v:130792.5-130792.29" switch \initial - attribute \src "libresoc.v:130155.9-130155.17" + attribute \src "libresoc.v:130792.9-130792.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -204804,7 +205049,7 @@ module \dec_oe$147 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204817,18 +205062,18 @@ module \dec_oe$147 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130175.3-130195.6" - process $proc$libresoc.v:130175$5058 + attribute \src "libresoc.v:130812.3-130832.6" + process $proc$libresoc.v:130812$5042 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130176.5-130176.29" + attribute \src "libresoc.v:130813.5-130813.29" switch \initial - attribute \src "libresoc.v:130176.9-130176.17" + attribute \src "libresoc.v:130813.9-130813.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -204837,7 +205082,7 @@ module \dec_oe$147 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204851,24 +205096,24 @@ module \dec_oe$147 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130200.1-130333.10" +attribute \src "libresoc.v:130837.1-130970.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" attribute \generator "nMigen" module \dec_oe$152 - attribute \src "libresoc.v:130201.7-130201.20" + attribute \src "libresoc.v:130838.7-130838.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130291.3-130311.6" + attribute \src "libresoc.v:130928.3-130948.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130312.3-130332.6" + attribute \src "libresoc.v:130949.3-130969.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130291.3-130311.6" + attribute \src "libresoc.v:130928.3-130948.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130312.3-130332.6" + attribute \src "libresoc.v:130949.3-130969.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130291.3-130311.6" + attribute \src "libresoc.v:130928.3-130948.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130312.3-130332.6" + attribute \src "libresoc.v:130949.3-130969.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \SPR_OE @@ -204949,38 +205194,38 @@ module \dec_oe$152 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \SPR_internal_op - attribute \src "libresoc.v:130201.7-130201.15" + attribute \src "libresoc.v:130838.7-130838.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:130201.7-130201.20" - process $proc$libresoc.v:130201$5062 + attribute \src "libresoc.v:130838.7-130838.20" + process $proc$libresoc.v:130838$5046 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130291.3-130311.6" - process $proc$libresoc.v:130291$5060 + attribute \src "libresoc.v:130928.3-130948.6" + process $proc$libresoc.v:130928$5044 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130292.5-130292.29" + attribute \src "libresoc.v:130929.5-130929.29" switch \initial - attribute \src "libresoc.v:130292.9-130292.17" + attribute \src "libresoc.v:130929.9-130929.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -204989,7 +205234,7 @@ module \dec_oe$152 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -205002,18 +205247,18 @@ module \dec_oe$152 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130312.3-130332.6" - process $proc$libresoc.v:130312$5061 + attribute \src "libresoc.v:130949.3-130969.6" + process $proc$libresoc.v:130949$5045 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130313.5-130313.29" + attribute \src "libresoc.v:130950.5-130950.29" switch \initial - attribute \src "libresoc.v:130313.9-130313.17" + attribute \src "libresoc.v:130950.9-130950.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -205022,7 +205267,7 @@ module \dec_oe$152 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -205036,24 +205281,24 @@ module \dec_oe$152 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130337.1-130472.10" +attribute \src "libresoc.v:130974.1-131109.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" attribute \generator "nMigen" module \dec_oe$155 - attribute \src "libresoc.v:130338.7-130338.20" + attribute \src "libresoc.v:130975.7-130975.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130430.3-130450.6" + attribute \src "libresoc.v:131067.3-131087.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130451.3-130471.6" + attribute \src "libresoc.v:131088.3-131108.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130430.3-130450.6" + attribute \src "libresoc.v:131067.3-131087.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130451.3-130471.6" + attribute \src "libresoc.v:131088.3-131108.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130430.3-130450.6" + attribute \src "libresoc.v:131067.3-131087.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130451.3-130471.6" + attribute \src "libresoc.v:131088.3-131108.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \DIV_OE @@ -205134,38 +205379,38 @@ module \dec_oe$155 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \DIV_internal_op - attribute \src "libresoc.v:130338.7-130338.15" + attribute \src "libresoc.v:130975.7-130975.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:130338.7-130338.20" - process $proc$libresoc.v:130338$5065 + attribute \src "libresoc.v:130975.7-130975.20" + process $proc$libresoc.v:130975$5049 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130430.3-130450.6" - process $proc$libresoc.v:130430$5063 + attribute \src "libresoc.v:131067.3-131087.6" + process $proc$libresoc.v:131067$5047 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130431.5-130431.29" + attribute \src "libresoc.v:131068.5-131068.29" switch \initial - attribute \src "libresoc.v:130431.9-130431.17" + attribute \src "libresoc.v:131068.9-131068.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -205174,7 +205419,7 @@ module \dec_oe$155 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -205187,18 +205432,18 @@ module \dec_oe$155 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130451.3-130471.6" - process $proc$libresoc.v:130451$5064 + attribute \src "libresoc.v:131088.3-131108.6" + process $proc$libresoc.v:131088$5048 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130452.5-130452.29" + attribute \src "libresoc.v:131089.5-131089.29" switch \initial - attribute \src "libresoc.v:130452.9-130452.17" + attribute \src "libresoc.v:131089.9-131089.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -205207,7 +205452,7 @@ module \dec_oe$155 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -205221,24 +205466,24 @@ module \dec_oe$155 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130476.1-130611.10" +attribute \src "libresoc.v:131113.1-131248.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" attribute \generator "nMigen" module \dec_oe$160 - attribute \src "libresoc.v:130477.7-130477.20" + attribute \src "libresoc.v:131114.7-131114.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130569.3-130589.6" + attribute \src "libresoc.v:131206.3-131226.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130590.3-130610.6" + attribute \src "libresoc.v:131227.3-131247.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130569.3-130589.6" + attribute \src "libresoc.v:131206.3-131226.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130590.3-130610.6" + attribute \src "libresoc.v:131227.3-131247.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130569.3-130589.6" + attribute \src "libresoc.v:131206.3-131226.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130590.3-130610.6" + attribute \src "libresoc.v:131227.3-131247.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \MUL_OE @@ -205319,38 +205564,38 @@ module \dec_oe$160 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \MUL_internal_op - attribute \src "libresoc.v:130477.7-130477.15" + attribute \src "libresoc.v:131114.7-131114.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:130477.7-130477.20" - process $proc$libresoc.v:130477$5068 + attribute \src "libresoc.v:131114.7-131114.20" + process $proc$libresoc.v:131114$5052 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130569.3-130589.6" - process $proc$libresoc.v:130569$5066 + attribute \src "libresoc.v:131206.3-131226.6" + process $proc$libresoc.v:131206$5050 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130570.5-130570.29" + attribute \src "libresoc.v:131207.5-131207.29" switch \initial - attribute \src "libresoc.v:130570.9-130570.17" + attribute \src "libresoc.v:131207.9-131207.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -205359,7 +205604,7 @@ module \dec_oe$160 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -205372,18 +205617,18 @@ module \dec_oe$160 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130590.3-130610.6" - process $proc$libresoc.v:130590$5067 + attribute \src "libresoc.v:131227.3-131247.6" + process $proc$libresoc.v:131227$5051 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130591.5-130591.29" + attribute \src "libresoc.v:131228.5-131228.29" switch \initial - attribute \src "libresoc.v:130591.9-130591.17" + attribute \src "libresoc.v:131228.9-131228.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -205392,7 +205637,7 @@ module \dec_oe$160 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -205406,24 +205651,24 @@ module \dec_oe$160 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130615.1-130750.10" +attribute \src "libresoc.v:131252.1-131387.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" attribute \generator "nMigen" module \dec_oe$164 - attribute \src "libresoc.v:130616.7-130616.20" + attribute \src "libresoc.v:131253.7-131253.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130708.3-130728.6" + attribute \src "libresoc.v:131345.3-131365.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130729.3-130749.6" + attribute \src "libresoc.v:131366.3-131386.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130708.3-130728.6" + attribute \src "libresoc.v:131345.3-131365.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130729.3-130749.6" + attribute \src "libresoc.v:131366.3-131386.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130708.3-130728.6" + attribute \src "libresoc.v:131345.3-131365.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130729.3-130749.6" + attribute \src "libresoc.v:131366.3-131386.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \SHIFT_ROT_OE @@ -205504,38 +205749,38 @@ module \dec_oe$164 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \SHIFT_ROT_internal_op - attribute \src "libresoc.v:130616.7-130616.15" + attribute \src "libresoc.v:131253.7-131253.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:130616.7-130616.20" - process $proc$libresoc.v:130616$5071 + attribute \src "libresoc.v:131253.7-131253.20" + process $proc$libresoc.v:131253$5055 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130708.3-130728.6" - process $proc$libresoc.v:130708$5069 + attribute \src "libresoc.v:131345.3-131365.6" + process $proc$libresoc.v:131345$5053 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130709.5-130709.29" + attribute \src "libresoc.v:131346.5-131346.29" switch \initial - attribute \src "libresoc.v:130709.9-130709.17" + attribute \src "libresoc.v:131346.9-131346.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -205544,7 +205789,7 @@ module \dec_oe$164 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -205557,18 +205802,18 @@ module \dec_oe$164 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130729.3-130749.6" - process $proc$libresoc.v:130729$5070 + attribute \src "libresoc.v:131366.3-131386.6" + process $proc$libresoc.v:131366$5054 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130730.5-130730.29" + attribute \src "libresoc.v:131367.5-131367.29" switch \initial - attribute \src "libresoc.v:130730.9-130730.17" + attribute \src "libresoc.v:131367.9-131367.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -205577,7 +205822,7 @@ module \dec_oe$164 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -205591,24 +205836,24 @@ module \dec_oe$164 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130754.1-130889.10" +attribute \src "libresoc.v:131391.1-131526.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" attribute \generator "nMigen" module \dec_oe$168 - attribute \src "libresoc.v:130755.7-130755.20" + attribute \src "libresoc.v:131392.7-131392.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130847.3-130867.6" + attribute \src "libresoc.v:131484.3-131504.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130868.3-130888.6" + attribute \src "libresoc.v:131505.3-131525.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130847.3-130867.6" + attribute \src "libresoc.v:131484.3-131504.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130868.3-130888.6" + attribute \src "libresoc.v:131505.3-131525.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130847.3-130867.6" + attribute \src "libresoc.v:131484.3-131504.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130868.3-130888.6" + attribute \src "libresoc.v:131505.3-131525.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \LDST_OE @@ -205689,38 +205934,38 @@ module \dec_oe$168 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \LDST_internal_op - attribute \src "libresoc.v:130755.7-130755.15" + attribute \src "libresoc.v:131392.7-131392.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:130755.7-130755.20" - process $proc$libresoc.v:130755$5074 + attribute \src "libresoc.v:131392.7-131392.20" + process $proc$libresoc.v:131392$5058 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130847.3-130867.6" - process $proc$libresoc.v:130847$5072 + attribute \src "libresoc.v:131484.3-131504.6" + process $proc$libresoc.v:131484$5056 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130848.5-130848.29" + attribute \src "libresoc.v:131485.5-131485.29" switch \initial - attribute \src "libresoc.v:130848.9-130848.17" + attribute \src "libresoc.v:131485.9-131485.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -205729,7 +205974,7 @@ module \dec_oe$168 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -205742,18 +205987,18 @@ module \dec_oe$168 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130868.3-130888.6" - process $proc$libresoc.v:130868$5073 + attribute \src "libresoc.v:131505.3-131525.6" + process $proc$libresoc.v:131505$5057 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130869.5-130869.29" + attribute \src "libresoc.v:131506.5-131506.29" switch \initial - attribute \src "libresoc.v:130869.9-130869.17" + attribute \src "libresoc.v:131506.9-131506.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -205762,7 +206007,7 @@ module \dec_oe$168 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -205776,28 +206021,28 @@ module \dec_oe$168 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130893.1-131028.10" +attribute \src "libresoc.v:131530.1-131665.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" attribute \generator "nMigen" module \dec_oe$173 - attribute \src "libresoc.v:130894.7-130894.20" + attribute \src "libresoc.v:131531.7-131531.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130986.3-131006.6" + attribute \src "libresoc.v:131623.3-131643.6" wire $0\oe[0:0] - attribute \src "libresoc.v:131007.3-131027.6" + attribute \src "libresoc.v:131644.3-131664.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130986.3-131006.6" + attribute \src "libresoc.v:131623.3-131643.6" wire $1\oe[0:0] - attribute \src "libresoc.v:131007.3-131027.6" + attribute \src "libresoc.v:131644.3-131664.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130986.3-131006.6" + attribute \src "libresoc.v:131623.3-131643.6" wire $2\oe[0:0] - attribute \src "libresoc.v:131007.3-131027.6" + attribute \src "libresoc.v:131644.3-131664.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \OE - attribute \src "libresoc.v:130894.7-130894.15" + attribute \src "libresoc.v:131531.7-131531.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -205876,36 +206121,36 @@ module \dec_oe$173 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:130894.7-130894.20" - process $proc$libresoc.v:130894$5077 + attribute \src "libresoc.v:131531.7-131531.20" + process $proc$libresoc.v:131531$5061 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130986.3-131006.6" - process $proc$libresoc.v:130986$5075 + attribute \src "libresoc.v:131623.3-131643.6" + process $proc$libresoc.v:131623$5059 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130987.5-130987.29" + attribute \src "libresoc.v:131624.5-131624.29" switch \initial - attribute \src "libresoc.v:130987.9-130987.17" + attribute \src "libresoc.v:131624.9-131624.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -205914,7 +206159,7 @@ module \dec_oe$173 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -205927,18 +206172,18 @@ module \dec_oe$173 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:131007.3-131027.6" - process $proc$libresoc.v:131007$5076 + attribute \src "libresoc.v:131644.3-131664.6" + process $proc$libresoc.v:131644$5060 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:131008.5-131008.29" + attribute \src "libresoc.v:131645.5-131645.29" switch \initial - attribute \src "libresoc.v:131008.9-131008.17" + attribute \src "libresoc.v:131645.9-131645.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -205947,7 +206192,7 @@ module \dec_oe$173 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -205961,55 +206206,55 @@ module \dec_oe$173 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:131032.1-131086.10" +attribute \src "libresoc.v:131669.1-131723.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" attribute \generator "nMigen" module \dec_rc - attribute \src "libresoc.v:131033.7-131033.20" + attribute \src "libresoc.v:131670.7-131670.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131048.3-131066.6" + attribute \src "libresoc.v:131685.3-131703.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131067.3-131085.6" + attribute \src "libresoc.v:131704.3-131722.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131048.3-131066.6" + attribute \src "libresoc.v:131685.3-131703.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131067.3-131085.6" + attribute \src "libresoc.v:131704.3-131722.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \ALU_Rc - attribute \src "libresoc.v:131033.7-131033.15" + attribute \src "libresoc.v:131670.7-131670.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131033.7-131033.20" - process $proc$libresoc.v:131033$5080 + attribute \src "libresoc.v:131670.7-131670.20" + process $proc$libresoc.v:131670$5064 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131048.3-131066.6" - process $proc$libresoc.v:131048$5078 + attribute \src "libresoc.v:131685.3-131703.6" + process $proc$libresoc.v:131685$5062 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131049.5-131049.29" + attribute \src "libresoc.v:131686.5-131686.29" switch \initial - attribute \src "libresoc.v:131049.9-131049.17" + attribute \src "libresoc.v:131686.9-131686.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206029,18 +206274,18 @@ module \dec_rc sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131067.3-131085.6" - process $proc$libresoc.v:131067$5079 + attribute \src "libresoc.v:131704.3-131722.6" + process $proc$libresoc.v:131704$5063 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131068.5-131068.29" + attribute \src "libresoc.v:131705.5-131705.29" switch \initial - attribute \src "libresoc.v:131068.9-131068.17" + attribute \src "libresoc.v:131705.9-131705.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206061,55 +206306,55 @@ module \dec_rc update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131090.1-131142.10" +attribute \src "libresoc.v:131727.1-131779.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" attribute \generator "nMigen" module \dec_rc$139 - attribute \src "libresoc.v:131091.7-131091.20" + attribute \src "libresoc.v:131728.7-131728.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131104.3-131122.6" + attribute \src "libresoc.v:131741.3-131759.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131123.3-131141.6" + attribute \src "libresoc.v:131760.3-131778.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131104.3-131122.6" + attribute \src "libresoc.v:131741.3-131759.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131123.3-131141.6" + attribute \src "libresoc.v:131760.3-131778.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \CR_Rc - attribute \src "libresoc.v:131091.7-131091.15" + attribute \src "libresoc.v:131728.7-131728.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:131091.7-131091.20" - process $proc$libresoc.v:131091$5083 + attribute \src "libresoc.v:131728.7-131728.20" + process $proc$libresoc.v:131728$5067 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131104.3-131122.6" - process $proc$libresoc.v:131104$5081 + attribute \src "libresoc.v:131741.3-131759.6" + process $proc$libresoc.v:131741$5065 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131105.5-131105.29" + attribute \src "libresoc.v:131742.5-131742.29" switch \initial - attribute \src "libresoc.v:131105.9-131105.17" + attribute \src "libresoc.v:131742.9-131742.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206129,18 +206374,18 @@ module \dec_rc$139 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131123.3-131141.6" - process $proc$libresoc.v:131123$5082 + attribute \src "libresoc.v:131760.3-131778.6" + process $proc$libresoc.v:131760$5066 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131124.5-131124.29" + attribute \src "libresoc.v:131761.5-131761.29" switch \initial - attribute \src "libresoc.v:131124.9-131124.17" + attribute \src "libresoc.v:131761.9-131761.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206161,55 +206406,55 @@ module \dec_rc$139 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131146.1-131198.10" +attribute \src "libresoc.v:131783.1-131835.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" attribute \generator "nMigen" module \dec_rc$142 - attribute \src "libresoc.v:131147.7-131147.20" + attribute \src "libresoc.v:131784.7-131784.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131160.3-131178.6" + attribute \src "libresoc.v:131797.3-131815.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131179.3-131197.6" + attribute \src "libresoc.v:131816.3-131834.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131160.3-131178.6" + attribute \src "libresoc.v:131797.3-131815.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131179.3-131197.6" + attribute \src "libresoc.v:131816.3-131834.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \BRANCH_Rc - attribute \src "libresoc.v:131147.7-131147.15" + attribute \src "libresoc.v:131784.7-131784.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:131147.7-131147.20" - process $proc$libresoc.v:131147$5086 + attribute \src "libresoc.v:131784.7-131784.20" + process $proc$libresoc.v:131784$5070 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131160.3-131178.6" - process $proc$libresoc.v:131160$5084 + attribute \src "libresoc.v:131797.3-131815.6" + process $proc$libresoc.v:131797$5068 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131161.5-131161.29" + attribute \src "libresoc.v:131798.5-131798.29" switch \initial - attribute \src "libresoc.v:131161.9-131161.17" + attribute \src "libresoc.v:131798.9-131798.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206229,18 +206474,18 @@ module \dec_rc$142 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131179.3-131197.6" - process $proc$libresoc.v:131179$5085 + attribute \src "libresoc.v:131816.3-131834.6" + process $proc$libresoc.v:131816$5069 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131180.5-131180.29" + attribute \src "libresoc.v:131817.5-131817.29" switch \initial - attribute \src "libresoc.v:131180.9-131180.17" + attribute \src "libresoc.v:131817.9-131817.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206261,55 +206506,55 @@ module \dec_rc$142 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131202.1-131256.10" +attribute \src "libresoc.v:131839.1-131893.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" attribute \generator "nMigen" module \dec_rc$146 - attribute \src "libresoc.v:131203.7-131203.20" + attribute \src "libresoc.v:131840.7-131840.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131218.3-131236.6" + attribute \src "libresoc.v:131855.3-131873.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131237.3-131255.6" + attribute \src "libresoc.v:131874.3-131892.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131218.3-131236.6" + attribute \src "libresoc.v:131855.3-131873.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131237.3-131255.6" + attribute \src "libresoc.v:131874.3-131892.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \LOGICAL_Rc - attribute \src "libresoc.v:131203.7-131203.15" + attribute \src "libresoc.v:131840.7-131840.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131203.7-131203.20" - process $proc$libresoc.v:131203$5089 + attribute \src "libresoc.v:131840.7-131840.20" + process $proc$libresoc.v:131840$5073 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131218.3-131236.6" - process $proc$libresoc.v:131218$5087 + attribute \src "libresoc.v:131855.3-131873.6" + process $proc$libresoc.v:131855$5071 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131219.5-131219.29" + attribute \src "libresoc.v:131856.5-131856.29" switch \initial - attribute \src "libresoc.v:131219.9-131219.17" + attribute \src "libresoc.v:131856.9-131856.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206329,18 +206574,18 @@ module \dec_rc$146 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131237.3-131255.6" - process $proc$libresoc.v:131237$5088 + attribute \src "libresoc.v:131874.3-131892.6" + process $proc$libresoc.v:131874$5072 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131238.5-131238.29" + attribute \src "libresoc.v:131875.5-131875.29" switch \initial - attribute \src "libresoc.v:131238.9-131238.17" + attribute \src "libresoc.v:131875.9-131875.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206361,55 +206606,55 @@ module \dec_rc$146 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131260.1-131312.10" +attribute \src "libresoc.v:131897.1-131949.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" attribute \generator "nMigen" module \dec_rc$151 - attribute \src "libresoc.v:131261.7-131261.20" + attribute \src "libresoc.v:131898.7-131898.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131274.3-131292.6" + attribute \src "libresoc.v:131911.3-131929.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131293.3-131311.6" + attribute \src "libresoc.v:131930.3-131948.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131274.3-131292.6" + attribute \src "libresoc.v:131911.3-131929.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131293.3-131311.6" + attribute \src "libresoc.v:131930.3-131948.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \SPR_Rc - attribute \src "libresoc.v:131261.7-131261.15" + attribute \src "libresoc.v:131898.7-131898.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:131261.7-131261.20" - process $proc$libresoc.v:131261$5092 + attribute \src "libresoc.v:131898.7-131898.20" + process $proc$libresoc.v:131898$5076 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131274.3-131292.6" - process $proc$libresoc.v:131274$5090 + attribute \src "libresoc.v:131911.3-131929.6" + process $proc$libresoc.v:131911$5074 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131275.5-131275.29" + attribute \src "libresoc.v:131912.5-131912.29" switch \initial - attribute \src "libresoc.v:131275.9-131275.17" + attribute \src "libresoc.v:131912.9-131912.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206429,18 +206674,18 @@ module \dec_rc$151 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131293.3-131311.6" - process $proc$libresoc.v:131293$5091 + attribute \src "libresoc.v:131930.3-131948.6" + process $proc$libresoc.v:131930$5075 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131294.5-131294.29" + attribute \src "libresoc.v:131931.5-131931.29" switch \initial - attribute \src "libresoc.v:131294.9-131294.17" + attribute \src "libresoc.v:131931.9-131931.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206461,55 +206706,55 @@ module \dec_rc$151 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131316.1-131370.10" +attribute \src "libresoc.v:131953.1-132007.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" attribute \generator "nMigen" module \dec_rc$154 - attribute \src "libresoc.v:131317.7-131317.20" + attribute \src "libresoc.v:131954.7-131954.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131332.3-131350.6" + attribute \src "libresoc.v:131969.3-131987.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131351.3-131369.6" + attribute \src "libresoc.v:131988.3-132006.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131332.3-131350.6" + attribute \src "libresoc.v:131969.3-131987.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131351.3-131369.6" + attribute \src "libresoc.v:131988.3-132006.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \DIV_Rc - attribute \src "libresoc.v:131317.7-131317.15" + attribute \src "libresoc.v:131954.7-131954.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131317.7-131317.20" - process $proc$libresoc.v:131317$5095 + attribute \src "libresoc.v:131954.7-131954.20" + process $proc$libresoc.v:131954$5079 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131332.3-131350.6" - process $proc$libresoc.v:131332$5093 + attribute \src "libresoc.v:131969.3-131987.6" + process $proc$libresoc.v:131969$5077 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131333.5-131333.29" + attribute \src "libresoc.v:131970.5-131970.29" switch \initial - attribute \src "libresoc.v:131333.9-131333.17" + attribute \src "libresoc.v:131970.9-131970.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206529,18 +206774,18 @@ module \dec_rc$154 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131351.3-131369.6" - process $proc$libresoc.v:131351$5094 + attribute \src "libresoc.v:131988.3-132006.6" + process $proc$libresoc.v:131988$5078 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131352.5-131352.29" + attribute \src "libresoc.v:131989.5-131989.29" switch \initial - attribute \src "libresoc.v:131352.9-131352.17" + attribute \src "libresoc.v:131989.9-131989.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206561,55 +206806,55 @@ module \dec_rc$154 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131374.1-131428.10" +attribute \src "libresoc.v:132011.1-132065.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" attribute \generator "nMigen" module \dec_rc$159 - attribute \src "libresoc.v:131375.7-131375.20" + attribute \src "libresoc.v:132012.7-132012.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131390.3-131408.6" + attribute \src "libresoc.v:132027.3-132045.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131409.3-131427.6" + attribute \src "libresoc.v:132046.3-132064.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131390.3-131408.6" + attribute \src "libresoc.v:132027.3-132045.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131409.3-131427.6" + attribute \src "libresoc.v:132046.3-132064.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \MUL_Rc - attribute \src "libresoc.v:131375.7-131375.15" + attribute \src "libresoc.v:132012.7-132012.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131375.7-131375.20" - process $proc$libresoc.v:131375$5098 + attribute \src "libresoc.v:132012.7-132012.20" + process $proc$libresoc.v:132012$5082 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131390.3-131408.6" - process $proc$libresoc.v:131390$5096 + attribute \src "libresoc.v:132027.3-132045.6" + process $proc$libresoc.v:132027$5080 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131391.5-131391.29" + attribute \src "libresoc.v:132028.5-132028.29" switch \initial - attribute \src "libresoc.v:131391.9-131391.17" + attribute \src "libresoc.v:132028.9-132028.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206629,18 +206874,18 @@ module \dec_rc$159 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131409.3-131427.6" - process $proc$libresoc.v:131409$5097 + attribute \src "libresoc.v:132046.3-132064.6" + process $proc$libresoc.v:132046$5081 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131410.5-131410.29" + attribute \src "libresoc.v:132047.5-132047.29" switch \initial - attribute \src "libresoc.v:131410.9-131410.17" + attribute \src "libresoc.v:132047.9-132047.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206661,55 +206906,55 @@ module \dec_rc$159 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131432.1-131486.10" +attribute \src "libresoc.v:132069.1-132123.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" attribute \generator "nMigen" module \dec_rc$163 - attribute \src "libresoc.v:131433.7-131433.20" + attribute \src "libresoc.v:132070.7-132070.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131448.3-131466.6" + attribute \src "libresoc.v:132085.3-132103.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131467.3-131485.6" + attribute \src "libresoc.v:132104.3-132122.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131448.3-131466.6" + attribute \src "libresoc.v:132085.3-132103.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131467.3-131485.6" + attribute \src "libresoc.v:132104.3-132122.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \SHIFT_ROT_Rc - attribute \src "libresoc.v:131433.7-131433.15" + attribute \src "libresoc.v:132070.7-132070.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131433.7-131433.20" - process $proc$libresoc.v:131433$5101 + attribute \src "libresoc.v:132070.7-132070.20" + process $proc$libresoc.v:132070$5085 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131448.3-131466.6" - process $proc$libresoc.v:131448$5099 + attribute \src "libresoc.v:132085.3-132103.6" + process $proc$libresoc.v:132085$5083 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131449.5-131449.29" + attribute \src "libresoc.v:132086.5-132086.29" switch \initial - attribute \src "libresoc.v:131449.9-131449.17" + attribute \src "libresoc.v:132086.9-132086.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206729,18 +206974,18 @@ module \dec_rc$163 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131467.3-131485.6" - process $proc$libresoc.v:131467$5100 + attribute \src "libresoc.v:132104.3-132122.6" + process $proc$libresoc.v:132104$5084 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131468.5-131468.29" + attribute \src "libresoc.v:132105.5-132105.29" switch \initial - attribute \src "libresoc.v:131468.9-131468.17" + attribute \src "libresoc.v:132105.9-132105.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206761,55 +207006,55 @@ module \dec_rc$163 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131490.1-131544.10" +attribute \src "libresoc.v:132127.1-132181.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" attribute \generator "nMigen" module \dec_rc$167 - attribute \src "libresoc.v:131491.7-131491.20" + attribute \src "libresoc.v:132128.7-132128.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131506.3-131524.6" + attribute \src "libresoc.v:132143.3-132161.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131525.3-131543.6" + attribute \src "libresoc.v:132162.3-132180.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131506.3-131524.6" + attribute \src "libresoc.v:132143.3-132161.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131525.3-131543.6" + attribute \src "libresoc.v:132162.3-132180.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \LDST_Rc - attribute \src "libresoc.v:131491.7-131491.15" + attribute \src "libresoc.v:132128.7-132128.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131491.7-131491.20" - process $proc$libresoc.v:131491$5104 + attribute \src "libresoc.v:132128.7-132128.20" + process $proc$libresoc.v:132128$5088 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131506.3-131524.6" - process $proc$libresoc.v:131506$5102 + attribute \src "libresoc.v:132143.3-132161.6" + process $proc$libresoc.v:132143$5086 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131507.5-131507.29" + attribute \src "libresoc.v:132144.5-132144.29" switch \initial - attribute \src "libresoc.v:131507.9-131507.17" + attribute \src "libresoc.v:132144.9-132144.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206829,18 +207074,18 @@ module \dec_rc$167 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131525.3-131543.6" - process $proc$libresoc.v:131525$5103 + attribute \src "libresoc.v:132162.3-132180.6" + process $proc$libresoc.v:132162$5087 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131526.5-131526.29" + attribute \src "libresoc.v:132163.5-132163.29" switch \initial - attribute \src "libresoc.v:131526.9-131526.17" + attribute \src "libresoc.v:132163.9-132163.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206861,55 +207106,55 @@ module \dec_rc$167 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131548.1-131602.10" +attribute \src "libresoc.v:132185.1-132239.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" attribute \generator "nMigen" module \dec_rc$172 - attribute \src "libresoc.v:131549.7-131549.20" + attribute \src "libresoc.v:132186.7-132186.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131564.3-131582.6" + attribute \src "libresoc.v:132201.3-132219.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131583.3-131601.6" + attribute \src "libresoc.v:132220.3-132238.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131564.3-131582.6" + attribute \src "libresoc.v:132201.3-132219.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131583.3-131601.6" + attribute \src "libresoc.v:132220.3-132238.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \Rc - attribute \src "libresoc.v:131549.7-131549.15" + attribute \src "libresoc.v:132186.7-132186.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131549.7-131549.20" - process $proc$libresoc.v:131549$5107 + attribute \src "libresoc.v:132186.7-132186.20" + process $proc$libresoc.v:132186$5091 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131564.3-131582.6" - process $proc$libresoc.v:131564$5105 + attribute \src "libresoc.v:132201.3-132219.6" + process $proc$libresoc.v:132201$5089 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131565.5-131565.29" + attribute \src "libresoc.v:132202.5-132202.29" switch \initial - attribute \src "libresoc.v:131565.9-131565.17" + attribute \src "libresoc.v:132202.9-132202.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206929,18 +207174,18 @@ module \dec_rc$172 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131583.3-131601.6" - process $proc$libresoc.v:131583$5106 + attribute \src "libresoc.v:132220.3-132238.6" + process $proc$libresoc.v:132220$5090 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131584.5-131584.29" + attribute \src "libresoc.v:132221.5-132221.29" switch \initial - attribute \src "libresoc.v:131584.9-131584.17" + attribute \src "libresoc.v:132221.9-132221.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -206961,539 +207206,539 @@ module \dec_rc$172 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131606.1-132850.10" +attribute \src "libresoc.v:132243.1-133487.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" attribute \generator "nMigen" module \div0 - attribute \src "libresoc.v:132407.3-132408.25" + attribute \src "libresoc.v:133044.3-133045.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5247 - attribute \src "libresoc.v:132379.3-132380.75" + attribute \src "libresoc.v:133231.3-133269.6" + wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5231 + attribute \src "libresoc.v:133016.3-133017.75" wire width 4 $0\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire width 14 $0\alu_div0_logical_op__fn_unit$next[13:0]$5248 - attribute \src "libresoc.v:132349.3-132350.73" + attribute \src "libresoc.v:133231.3-133269.6" + wire width 14 $0\alu_div0_logical_op__fn_unit$next[13:0]$5232 + attribute \src "libresoc.v:132986.3-132987.73" wire width 14 $0\alu_div0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249 - attribute \src "libresoc.v:132351.3-132352.87" + attribute \src "libresoc.v:133231.3-133269.6" + wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5233 + attribute \src "libresoc.v:132988.3-132989.87" wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250 - attribute \src "libresoc.v:132353.3-132354.83" + attribute \src "libresoc.v:133231.3-133269.6" + wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5234 + attribute \src "libresoc.v:132990.3-132991.83" wire $0\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5251 - attribute \src "libresoc.v:132367.3-132368.81" + attribute \src "libresoc.v:133231.3-133269.6" + wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5235 + attribute \src "libresoc.v:133004.3-133005.81" wire width 2 $0\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5252 - attribute \src "libresoc.v:132381.3-132382.67" + attribute \src "libresoc.v:133231.3-133269.6" + wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5236 + attribute \src "libresoc.v:133018.3-133019.67" wire width 32 $0\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5253 - attribute \src "libresoc.v:132347.3-132348.77" + attribute \src "libresoc.v:133231.3-133269.6" + wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5237 + attribute \src "libresoc.v:132984.3-132985.77" wire width 7 $0\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $0\alu_div0_logical_op__invert_in$next[0:0]$5254 - attribute \src "libresoc.v:132363.3-132364.77" + attribute \src "libresoc.v:133231.3-133269.6" + wire $0\alu_div0_logical_op__invert_in$next[0:0]$5238 + attribute \src "libresoc.v:133000.3-133001.77" wire $0\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $0\alu_div0_logical_op__invert_out$next[0:0]$5255 - attribute \src "libresoc.v:132369.3-132370.79" + attribute \src "libresoc.v:133231.3-133269.6" + wire $0\alu_div0_logical_op__invert_out$next[0:0]$5239 + attribute \src "libresoc.v:133006.3-133007.79" wire $0\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5256 - attribute \src "libresoc.v:132375.3-132376.75" + attribute \src "libresoc.v:133231.3-133269.6" + wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5240 + attribute \src "libresoc.v:133012.3-133013.75" wire $0\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $0\alu_div0_logical_op__is_signed$next[0:0]$5257 - attribute \src "libresoc.v:132377.3-132378.77" + attribute \src "libresoc.v:133231.3-133269.6" + wire $0\alu_div0_logical_op__is_signed$next[0:0]$5241 + attribute \src "libresoc.v:133014.3-133015.77" wire $0\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5258 - attribute \src "libresoc.v:132359.3-132360.71" + attribute \src "libresoc.v:133231.3-133269.6" + wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5242 + attribute \src "libresoc.v:132996.3-132997.71" wire $0\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 - attribute \src "libresoc.v:132361.3-132362.71" + attribute \src "libresoc.v:133231.3-133269.6" + wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5243 + attribute \src "libresoc.v:132998.3-132999.71" wire $0\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $0\alu_div0_logical_op__output_carry$next[0:0]$5260 - attribute \src "libresoc.v:132373.3-132374.83" + attribute \src "libresoc.v:133231.3-133269.6" + wire $0\alu_div0_logical_op__output_carry$next[0:0]$5244 + attribute \src "libresoc.v:133010.3-133011.83" wire $0\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 - attribute \src "libresoc.v:132357.3-132358.71" + attribute \src "libresoc.v:133231.3-133269.6" + wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5245 + attribute \src "libresoc.v:132994.3-132995.71" wire $0\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 - attribute \src "libresoc.v:132355.3-132356.71" + attribute \src "libresoc.v:133231.3-133269.6" + wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5246 + attribute \src "libresoc.v:132992.3-132993.71" wire $0\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 - attribute \src "libresoc.v:132371.3-132372.77" + attribute \src "libresoc.v:133231.3-133269.6" + wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5247 + attribute \src "libresoc.v:133008.3-133009.77" wire $0\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $0\alu_div0_logical_op__zero_a$next[0:0]$5264 - attribute \src "libresoc.v:132365.3-132366.71" + attribute \src "libresoc.v:133231.3-133269.6" + wire $0\alu_div0_logical_op__zero_a$next[0:0]$5248 + attribute \src "libresoc.v:133002.3-133003.71" wire $0\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:132405.3-132406.40" + attribute \src "libresoc.v:133042.3-133043.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:132760.3-132768.6" - wire $0\alu_l_r_alu$next[0:0]$5334 - attribute \src "libresoc.v:132321.3-132322.39" + attribute \src "libresoc.v:133397.3-133405.6" + wire $0\alu_l_r_alu$next[0:0]$5318 + attribute \src "libresoc.v:132958.3-132959.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:132751.3-132759.6" - wire $0\alui_l_r_alui$next[0:0]$5331 - attribute \src "libresoc.v:132323.3-132324.43" + attribute \src "libresoc.v:133388.3-133396.6" + wire $0\alui_l_r_alui$next[0:0]$5315 + attribute \src "libresoc.v:132960.3-132961.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:132633.3-132654.6" - wire width 64 $0\data_r0__o$next[63:0]$5290 - attribute \src "libresoc.v:132343.3-132344.37" + attribute \src "libresoc.v:133270.3-133291.6" + wire width 64 $0\data_r0__o$next[63:0]$5274 + attribute \src "libresoc.v:132980.3-132981.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:132633.3-132654.6" - wire $0\data_r0__o_ok$next[0:0]$5291 - attribute \src "libresoc.v:132345.3-132346.43" + attribute \src "libresoc.v:133270.3-133291.6" + wire $0\data_r0__o_ok$next[0:0]$5275 + attribute \src "libresoc.v:132982.3-132983.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:132655.3-132676.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$5298 - attribute \src "libresoc.v:132339.3-132340.43" + attribute \src "libresoc.v:133292.3-133313.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$5282 + attribute \src "libresoc.v:132976.3-132977.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:132655.3-132676.6" - wire $0\data_r1__cr_a_ok$next[0:0]$5299 - attribute \src "libresoc.v:132341.3-132342.49" + attribute \src "libresoc.v:133292.3-133313.6" + wire $0\data_r1__cr_a_ok$next[0:0]$5283 + attribute \src "libresoc.v:132978.3-132979.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:132677.3-132698.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$5306 - attribute \src "libresoc.v:132335.3-132336.47" + attribute \src "libresoc.v:133314.3-133335.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$5290 + attribute \src "libresoc.v:132972.3-132973.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:132677.3-132698.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$5307 - attribute \src "libresoc.v:132337.3-132338.53" + attribute \src "libresoc.v:133314.3-133335.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$5291 + attribute \src "libresoc.v:132974.3-132975.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:132699.3-132720.6" - wire $0\data_r3__xer_so$next[0:0]$5314 - attribute \src "libresoc.v:132331.3-132332.47" + attribute \src "libresoc.v:133336.3-133357.6" + wire $0\data_r3__xer_so$next[0:0]$5298 + attribute \src "libresoc.v:132968.3-132969.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:132699.3-132720.6" - wire $0\data_r3__xer_so_ok$next[0:0]$5315 - attribute \src "libresoc.v:132333.3-132334.53" + attribute \src "libresoc.v:133336.3-133357.6" + wire $0\data_r3__xer_so_ok$next[0:0]$5299 + attribute \src "libresoc.v:132970.3-132971.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:132769.3-132778.6" + attribute \src "libresoc.v:133406.3-133415.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:132779.3-132788.6" + attribute \src "libresoc.v:133416.3-133425.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:132789.3-132798.6" + attribute \src "libresoc.v:133426.3-133435.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:132799.3-132808.6" + attribute \src "libresoc.v:133436.3-133445.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:131607.7-131607.20" + attribute \src "libresoc.v:132244.7-132244.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132549.3-132557.6" - wire $0\opc_l_r_opc$next[0:0]$5232 - attribute \src "libresoc.v:132391.3-132392.39" + attribute \src "libresoc.v:133186.3-133194.6" + wire $0\opc_l_r_opc$next[0:0]$5216 + attribute \src "libresoc.v:133028.3-133029.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:132540.3-132548.6" - wire $0\opc_l_s_opc$next[0:0]$5229 - attribute \src "libresoc.v:132393.3-132394.39" + attribute \src "libresoc.v:133177.3-133185.6" + wire $0\opc_l_s_opc$next[0:0]$5213 + attribute \src "libresoc.v:133030.3-133031.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:132809.3-132817.6" - wire width 4 $0\prev_wr_go$next[3:0]$5341 - attribute \src "libresoc.v:132403.3-132404.37" + attribute \src "libresoc.v:133446.3-133454.6" + wire width 4 $0\prev_wr_go$next[3:0]$5325 + attribute \src "libresoc.v:133040.3-133041.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:132494.3-132503.6" + attribute \src "libresoc.v:133131.3-133140.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:132585.3-132593.6" - wire width 4 $0\req_l_r_req$next[3:0]$5244 - attribute \src "libresoc.v:132383.3-132384.39" + attribute \src "libresoc.v:133222.3-133230.6" + wire width 4 $0\req_l_r_req$next[3:0]$5228 + attribute \src "libresoc.v:133020.3-133021.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:132576.3-132584.6" - wire width 4 $0\req_l_s_req$next[3:0]$5241 - attribute \src "libresoc.v:132385.3-132386.39" + attribute \src "libresoc.v:133213.3-133221.6" + wire width 4 $0\req_l_s_req$next[3:0]$5225 + attribute \src "libresoc.v:133022.3-133023.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:132513.3-132521.6" - wire $0\rok_l_r_rdok$next[0:0]$5220 - attribute \src "libresoc.v:132399.3-132400.41" + attribute \src "libresoc.v:133150.3-133158.6" + wire $0\rok_l_r_rdok$next[0:0]$5204 + attribute \src "libresoc.v:133036.3-133037.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:132504.3-132512.6" - wire $0\rok_l_s_rdok$next[0:0]$5217 - attribute \src "libresoc.v:132401.3-132402.41" + attribute \src "libresoc.v:133141.3-133149.6" + wire $0\rok_l_s_rdok$next[0:0]$5201 + attribute \src "libresoc.v:133038.3-133039.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:132531.3-132539.6" - wire $0\rst_l_r_rst$next[0:0]$5226 - attribute \src "libresoc.v:132395.3-132396.39" + attribute \src "libresoc.v:133168.3-133176.6" + wire $0\rst_l_r_rst$next[0:0]$5210 + attribute \src "libresoc.v:133032.3-133033.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:132522.3-132530.6" - wire $0\rst_l_s_rst$next[0:0]$5223 - attribute \src "libresoc.v:132397.3-132398.39" + attribute \src "libresoc.v:133159.3-133167.6" + wire $0\rst_l_s_rst$next[0:0]$5207 + attribute \src "libresoc.v:133034.3-133035.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:132567.3-132575.6" - wire width 3 $0\src_l_r_src$next[2:0]$5238 - attribute \src "libresoc.v:132387.3-132388.39" + attribute \src "libresoc.v:133204.3-133212.6" + wire width 3 $0\src_l_r_src$next[2:0]$5222 + attribute \src "libresoc.v:133024.3-133025.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:132558.3-132566.6" - wire width 3 $0\src_l_s_src$next[2:0]$5235 - attribute \src "libresoc.v:132389.3-132390.39" + attribute \src "libresoc.v:133195.3-133203.6" + wire width 3 $0\src_l_s_src$next[2:0]$5219 + attribute \src "libresoc.v:133026.3-133027.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:132721.3-132730.6" - wire width 64 $0\src_r0$next[63:0]$5322 - attribute \src "libresoc.v:132329.3-132330.29" + attribute \src "libresoc.v:133358.3-133367.6" + wire width 64 $0\src_r0$next[63:0]$5306 + attribute \src "libresoc.v:132966.3-132967.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:132731.3-132740.6" - wire width 64 $0\src_r1$next[63:0]$5325 - attribute \src "libresoc.v:132327.3-132328.29" + attribute \src "libresoc.v:133368.3-133377.6" + wire width 64 $0\src_r1$next[63:0]$5309 + attribute \src "libresoc.v:132964.3-132965.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:132741.3-132750.6" - wire $0\src_r2$next[0:0]$5328 - attribute \src "libresoc.v:132325.3-132326.29" + attribute \src "libresoc.v:133378.3-133387.6" + wire $0\src_r2$next[0:0]$5312 + attribute \src "libresoc.v:132962.3-132963.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:131737.7-131737.24" + attribute \src "libresoc.v:132374.7-132374.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5265 - attribute \src "libresoc.v:131747.13-131747.49" + attribute \src "libresoc.v:133231.3-133269.6" + wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5249 + attribute \src "libresoc.v:132384.13-132384.49" wire width 4 $1\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire width 14 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 - attribute \src "libresoc.v:131766.14-131766.53" + attribute \src "libresoc.v:133231.3-133269.6" + wire width 14 $1\alu_div0_logical_op__fn_unit$next[13:0]$5250 + attribute \src "libresoc.v:132403.14-132403.53" wire width 14 $1\alu_div0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 - attribute \src "libresoc.v:131770.14-131770.72" + attribute \src "libresoc.v:133231.3-133269.6" + wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5251 + attribute \src "libresoc.v:132407.14-132407.72" wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 - attribute \src "libresoc.v:131774.7-131774.47" + attribute \src "libresoc.v:133231.3-133269.6" + wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5252 + attribute \src "libresoc.v:132411.7-132411.47" wire $1\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5269 - attribute \src "libresoc.v:131782.13-131782.52" + attribute \src "libresoc.v:133231.3-133269.6" + wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5253 + attribute \src "libresoc.v:132419.13-132419.52" wire width 2 $1\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5270 - attribute \src "libresoc.v:131786.14-131786.47" + attribute \src "libresoc.v:133231.3-133269.6" + wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5254 + attribute \src "libresoc.v:132423.14-132423.47" wire width 32 $1\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5271 - attribute \src "libresoc.v:131865.13-131865.51" + attribute \src "libresoc.v:133231.3-133269.6" + wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5255 + attribute \src "libresoc.v:132502.13-132502.51" wire width 7 $1\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $1\alu_div0_logical_op__invert_in$next[0:0]$5272 - attribute \src "libresoc.v:131869.7-131869.44" + attribute \src "libresoc.v:133231.3-133269.6" + wire $1\alu_div0_logical_op__invert_in$next[0:0]$5256 + attribute \src "libresoc.v:132506.7-132506.44" wire $1\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $1\alu_div0_logical_op__invert_out$next[0:0]$5273 - attribute \src "libresoc.v:131873.7-131873.45" + attribute \src "libresoc.v:133231.3-133269.6" + wire $1\alu_div0_logical_op__invert_out$next[0:0]$5257 + attribute \src "libresoc.v:132510.7-132510.45" wire $1\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 - attribute \src "libresoc.v:131877.7-131877.43" + attribute \src "libresoc.v:133231.3-133269.6" + wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5258 + attribute \src "libresoc.v:132514.7-132514.43" wire $1\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $1\alu_div0_logical_op__is_signed$next[0:0]$5275 - attribute \src "libresoc.v:131881.7-131881.44" + attribute \src "libresoc.v:133231.3-133269.6" + wire $1\alu_div0_logical_op__is_signed$next[0:0]$5259 + attribute \src "libresoc.v:132518.7-132518.44" wire $1\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 - attribute \src "libresoc.v:131885.7-131885.41" + attribute \src "libresoc.v:133231.3-133269.6" + wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5260 + attribute \src "libresoc.v:132522.7-132522.41" wire $1\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 - attribute \src "libresoc.v:131889.7-131889.41" + attribute \src "libresoc.v:133231.3-133269.6" + wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5261 + attribute \src "libresoc.v:132526.7-132526.41" wire $1\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $1\alu_div0_logical_op__output_carry$next[0:0]$5278 - attribute \src "libresoc.v:131893.7-131893.47" + attribute \src "libresoc.v:133231.3-133269.6" + wire $1\alu_div0_logical_op__output_carry$next[0:0]$5262 + attribute \src "libresoc.v:132530.7-132530.47" wire $1\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 - attribute \src "libresoc.v:131897.7-131897.41" + attribute \src "libresoc.v:133231.3-133269.6" + wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5263 + attribute \src "libresoc.v:132534.7-132534.41" wire $1\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 - attribute \src "libresoc.v:131901.7-131901.41" + attribute \src "libresoc.v:133231.3-133269.6" + wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5264 + attribute \src "libresoc.v:132538.7-132538.41" wire $1\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 - attribute \src "libresoc.v:131905.7-131905.44" + attribute \src "libresoc.v:133231.3-133269.6" + wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5265 + attribute \src "libresoc.v:132542.7-132542.44" wire $1\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire $1\alu_div0_logical_op__zero_a$next[0:0]$5282 - attribute \src "libresoc.v:131909.7-131909.41" + attribute \src "libresoc.v:133231.3-133269.6" + wire $1\alu_div0_logical_op__zero_a$next[0:0]$5266 + attribute \src "libresoc.v:132546.7-132546.41" wire $1\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:131935.7-131935.26" + attribute \src "libresoc.v:132572.7-132572.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:132760.3-132768.6" - wire $1\alu_l_r_alu$next[0:0]$5335 - attribute \src "libresoc.v:131943.7-131943.25" + attribute \src "libresoc.v:133397.3-133405.6" + wire $1\alu_l_r_alu$next[0:0]$5319 + attribute \src "libresoc.v:132580.7-132580.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:132751.3-132759.6" - wire $1\alui_l_r_alui$next[0:0]$5332 - attribute \src "libresoc.v:131955.7-131955.27" + attribute \src "libresoc.v:133388.3-133396.6" + wire $1\alui_l_r_alui$next[0:0]$5316 + attribute \src "libresoc.v:132592.7-132592.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:132633.3-132654.6" - wire width 64 $1\data_r0__o$next[63:0]$5292 - attribute \src "libresoc.v:131989.14-131989.47" + attribute \src "libresoc.v:133270.3-133291.6" + wire width 64 $1\data_r0__o$next[63:0]$5276 + attribute \src "libresoc.v:132626.14-132626.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:132633.3-132654.6" - wire $1\data_r0__o_ok$next[0:0]$5293 - attribute \src "libresoc.v:131993.7-131993.27" + attribute \src "libresoc.v:133270.3-133291.6" + wire $1\data_r0__o_ok$next[0:0]$5277 + attribute \src "libresoc.v:132630.7-132630.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:132655.3-132676.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$5300 - attribute \src "libresoc.v:131997.13-131997.33" + attribute \src "libresoc.v:133292.3-133313.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$5284 + attribute \src "libresoc.v:132634.13-132634.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:132655.3-132676.6" - wire $1\data_r1__cr_a_ok$next[0:0]$5301 - attribute \src "libresoc.v:132001.7-132001.30" + attribute \src "libresoc.v:133292.3-133313.6" + wire $1\data_r1__cr_a_ok$next[0:0]$5285 + attribute \src "libresoc.v:132638.7-132638.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:132677.3-132698.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$5308 - attribute \src "libresoc.v:132005.13-132005.35" + attribute \src "libresoc.v:133314.3-133335.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$5292 + attribute \src "libresoc.v:132642.13-132642.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:132677.3-132698.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$5309 - attribute \src "libresoc.v:132009.7-132009.32" + attribute \src "libresoc.v:133314.3-133335.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$5293 + attribute \src "libresoc.v:132646.7-132646.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:132699.3-132720.6" - wire $1\data_r3__xer_so$next[0:0]$5316 - attribute \src "libresoc.v:132013.7-132013.29" + attribute \src "libresoc.v:133336.3-133357.6" + wire $1\data_r3__xer_so$next[0:0]$5300 + attribute \src "libresoc.v:132650.7-132650.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:132699.3-132720.6" - wire $1\data_r3__xer_so_ok$next[0:0]$5317 - attribute \src "libresoc.v:132017.7-132017.32" + attribute \src "libresoc.v:133336.3-133357.6" + wire $1\data_r3__xer_so_ok$next[0:0]$5301 + attribute \src "libresoc.v:132654.7-132654.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:132769.3-132778.6" + attribute \src "libresoc.v:133406.3-133415.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:132779.3-132788.6" + attribute \src "libresoc.v:133416.3-133425.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:132789.3-132798.6" + attribute \src "libresoc.v:133426.3-133435.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:132799.3-132808.6" + attribute \src "libresoc.v:133436.3-133445.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:132549.3-132557.6" - wire $1\opc_l_r_opc$next[0:0]$5233 - attribute \src "libresoc.v:132037.7-132037.25" + attribute \src "libresoc.v:133186.3-133194.6" + wire $1\opc_l_r_opc$next[0:0]$5217 + attribute \src "libresoc.v:132674.7-132674.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:132540.3-132548.6" - wire $1\opc_l_s_opc$next[0:0]$5230 - attribute \src "libresoc.v:132041.7-132041.25" + attribute \src "libresoc.v:133177.3-133185.6" + wire $1\opc_l_s_opc$next[0:0]$5214 + attribute \src "libresoc.v:132678.7-132678.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:132809.3-132817.6" - wire width 4 $1\prev_wr_go$next[3:0]$5342 - attribute \src "libresoc.v:132175.13-132175.30" + attribute \src "libresoc.v:133446.3-133454.6" + wire width 4 $1\prev_wr_go$next[3:0]$5326 + attribute \src "libresoc.v:132812.13-132812.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:132494.3-132503.6" + attribute \src "libresoc.v:133131.3-133140.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:132585.3-132593.6" - wire width 4 $1\req_l_r_req$next[3:0]$5245 - attribute \src "libresoc.v:132183.13-132183.31" + attribute \src "libresoc.v:133222.3-133230.6" + wire width 4 $1\req_l_r_req$next[3:0]$5229 + attribute \src "libresoc.v:132820.13-132820.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:132576.3-132584.6" - wire width 4 $1\req_l_s_req$next[3:0]$5242 - attribute \src "libresoc.v:132187.13-132187.31" + attribute \src "libresoc.v:133213.3-133221.6" + wire width 4 $1\req_l_s_req$next[3:0]$5226 + attribute \src "libresoc.v:132824.13-132824.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:132513.3-132521.6" - wire $1\rok_l_r_rdok$next[0:0]$5221 - attribute \src "libresoc.v:132199.7-132199.26" + attribute \src "libresoc.v:133150.3-133158.6" + wire $1\rok_l_r_rdok$next[0:0]$5205 + attribute \src "libresoc.v:132836.7-132836.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:132504.3-132512.6" - wire $1\rok_l_s_rdok$next[0:0]$5218 - attribute \src "libresoc.v:132203.7-132203.26" + attribute \src "libresoc.v:133141.3-133149.6" + wire $1\rok_l_s_rdok$next[0:0]$5202 + attribute \src "libresoc.v:132840.7-132840.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:132531.3-132539.6" - wire $1\rst_l_r_rst$next[0:0]$5227 - attribute \src "libresoc.v:132207.7-132207.25" + attribute \src "libresoc.v:133168.3-133176.6" + wire $1\rst_l_r_rst$next[0:0]$5211 + attribute \src "libresoc.v:132844.7-132844.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:132522.3-132530.6" - wire $1\rst_l_s_rst$next[0:0]$5224 - attribute \src "libresoc.v:132211.7-132211.25" + attribute \src "libresoc.v:133159.3-133167.6" + wire $1\rst_l_s_rst$next[0:0]$5208 + attribute \src "libresoc.v:132848.7-132848.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:132567.3-132575.6" - wire width 3 $1\src_l_r_src$next[2:0]$5239 - attribute \src "libresoc.v:132225.13-132225.31" + attribute \src "libresoc.v:133204.3-133212.6" + wire width 3 $1\src_l_r_src$next[2:0]$5223 + attribute \src "libresoc.v:132862.13-132862.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:132558.3-132566.6" - wire width 3 $1\src_l_s_src$next[2:0]$5236 - attribute \src "libresoc.v:132229.13-132229.31" + attribute \src "libresoc.v:133195.3-133203.6" + wire width 3 $1\src_l_s_src$next[2:0]$5220 + attribute \src "libresoc.v:132866.13-132866.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:132721.3-132730.6" - wire width 64 $1\src_r0$next[63:0]$5323 - attribute \src "libresoc.v:132237.14-132237.43" + attribute \src "libresoc.v:133358.3-133367.6" + wire width 64 $1\src_r0$next[63:0]$5307 + attribute \src "libresoc.v:132874.14-132874.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:132731.3-132740.6" - wire width 64 $1\src_r1$next[63:0]$5326 - attribute \src "libresoc.v:132241.14-132241.43" + attribute \src "libresoc.v:133368.3-133377.6" + wire width 64 $1\src_r1$next[63:0]$5310 + attribute \src "libresoc.v:132878.14-132878.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:132741.3-132750.6" - wire $1\src_r2$next[0:0]$5329 - attribute \src "libresoc.v:132245.7-132245.20" + attribute \src "libresoc.v:133378.3-133387.6" + wire $1\src_r2$next[0:0]$5313 + attribute \src "libresoc.v:132882.7-132882.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:132594.3-132632.6" - wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 - attribute \src "libresoc.v:132594.3-132632.6" - wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 - attribute \src "libresoc.v:132594.3-132632.6" - wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 - attribute \src "libresoc.v:132594.3-132632.6" - wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 - attribute \src "libresoc.v:132594.3-132632.6" - wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 - attribute \src "libresoc.v:132594.3-132632.6" - wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 - attribute \src "libresoc.v:132633.3-132654.6" - wire width 64 $2\data_r0__o$next[63:0]$5294 - attribute \src "libresoc.v:132633.3-132654.6" - wire $2\data_r0__o_ok$next[0:0]$5295 - attribute \src "libresoc.v:132655.3-132676.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$5302 - attribute \src "libresoc.v:132655.3-132676.6" - wire $2\data_r1__cr_a_ok$next[0:0]$5303 - attribute \src "libresoc.v:132677.3-132698.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$5310 - attribute \src "libresoc.v:132677.3-132698.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$5311 - attribute \src "libresoc.v:132699.3-132720.6" - wire $2\data_r3__xer_so$next[0:0]$5318 - attribute \src "libresoc.v:132699.3-132720.6" - wire $2\data_r3__xer_so_ok$next[0:0]$5319 - attribute \src "libresoc.v:132633.3-132654.6" - wire $3\data_r0__o_ok$next[0:0]$5296 - attribute \src "libresoc.v:132655.3-132676.6" - wire $3\data_r1__cr_a_ok$next[0:0]$5304 - attribute \src "libresoc.v:132677.3-132698.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$5312 - attribute \src "libresoc.v:132699.3-132720.6" - wire $3\data_r3__xer_so_ok$next[0:0]$5320 - attribute \src "libresoc.v:132260.19-132260.133" - wire width 3 $and$libresoc.v:132260$5110_Y - attribute \src "libresoc.v:132262.19-132262.115" - wire width 3 $and$libresoc.v:132262$5112_Y - attribute \src "libresoc.v:132263.18-132263.110" - wire $and$libresoc.v:132263$5113_Y - attribute \src "libresoc.v:132264.19-132264.125" - wire $and$libresoc.v:132264$5114_Y - attribute \src "libresoc.v:132265.19-132265.125" - wire $and$libresoc.v:132265$5115_Y - attribute \src "libresoc.v:132266.19-132266.125" - wire $and$libresoc.v:132266$5116_Y - attribute \src "libresoc.v:132267.19-132267.125" - wire $and$libresoc.v:132267$5117_Y - attribute \src "libresoc.v:132268.19-132268.149" - wire width 4 $and$libresoc.v:132268$5118_Y - attribute \src "libresoc.v:132269.19-132269.121" - wire width 4 $and$libresoc.v:132269$5119_Y - attribute \src "libresoc.v:132270.19-132270.127" - wire $and$libresoc.v:132270$5120_Y - attribute \src "libresoc.v:132271.19-132271.127" - wire $and$libresoc.v:132271$5121_Y - attribute \src "libresoc.v:132272.19-132272.127" - wire $and$libresoc.v:132272$5122_Y - attribute \src "libresoc.v:132273.19-132273.127" - wire $and$libresoc.v:132273$5123_Y - attribute \src "libresoc.v:132275.18-132275.98" - wire $and$libresoc.v:132275$5125_Y - attribute \src "libresoc.v:132277.18-132277.100" - wire $and$libresoc.v:132277$5127_Y - attribute \src "libresoc.v:132278.18-132278.160" - wire width 4 $and$libresoc.v:132278$5128_Y - attribute \src "libresoc.v:132280.18-132280.119" - wire width 4 $and$libresoc.v:132280$5130_Y - attribute \src "libresoc.v:132283.17-132283.123" - wire $and$libresoc.v:132283$5133_Y - attribute \src "libresoc.v:132284.18-132284.116" - wire $and$libresoc.v:132284$5134_Y - attribute \src "libresoc.v:132289.18-132289.113" - wire $and$libresoc.v:132289$5139_Y - attribute \src "libresoc.v:132290.18-132290.125" - wire width 4 $and$libresoc.v:132290$5140_Y - attribute \src "libresoc.v:132292.18-132292.112" - wire $and$libresoc.v:132292$5142_Y - attribute \src "libresoc.v:132294.18-132294.126" - wire $and$libresoc.v:132294$5144_Y - attribute \src "libresoc.v:132295.18-132295.126" - wire $and$libresoc.v:132295$5145_Y - attribute \src "libresoc.v:132296.18-132296.117" - wire $and$libresoc.v:132296$5146_Y - attribute \src "libresoc.v:132302.18-132302.130" - wire $and$libresoc.v:132302$5152_Y - attribute \src "libresoc.v:132303.18-132303.124" - wire width 4 $and$libresoc.v:132303$5153_Y - attribute \src "libresoc.v:132305.18-132305.116" - wire $and$libresoc.v:132305$5155_Y - attribute \src "libresoc.v:132306.18-132306.119" - wire $and$libresoc.v:132306$5156_Y - attribute \src "libresoc.v:132307.18-132307.121" - wire $and$libresoc.v:132307$5157_Y - attribute \src "libresoc.v:132308.18-132308.121" - wire $and$libresoc.v:132308$5158_Y - attribute \src "libresoc.v:132318.18-132318.134" - wire $and$libresoc.v:132318$5168_Y - attribute \src "libresoc.v:132319.18-132319.132" - wire $and$libresoc.v:132319$5169_Y - attribute \src "libresoc.v:132320.18-132320.149" - wire width 3 $and$libresoc.v:132320$5170_Y - attribute \src "libresoc.v:132291.18-132291.113" - wire $eq$libresoc.v:132291$5141_Y - attribute \src "libresoc.v:132293.18-132293.119" - wire $eq$libresoc.v:132293$5143_Y - attribute \src "libresoc.v:132258.19-132258.130" - wire $not$libresoc.v:132258$5108_Y - attribute \src "libresoc.v:132259.19-132259.136" - wire $not$libresoc.v:132259$5109_Y - attribute \src "libresoc.v:132261.19-132261.115" - wire width 3 $not$libresoc.v:132261$5111_Y - attribute \src "libresoc.v:132274.18-132274.97" - wire $not$libresoc.v:132274$5124_Y - attribute \src "libresoc.v:132276.18-132276.99" - wire $not$libresoc.v:132276$5126_Y - attribute \src "libresoc.v:132279.18-132279.113" - wire width 4 $not$libresoc.v:132279$5129_Y - attribute \src "libresoc.v:132282.18-132282.106" - wire $not$libresoc.v:132282$5132_Y - attribute \src "libresoc.v:132288.18-132288.120" - wire $not$libresoc.v:132288$5138_Y - attribute \src "libresoc.v:132299.17-132299.113" - wire width 3 $not$libresoc.v:132299$5149_Y - attribute \src "libresoc.v:132287.18-132287.112" - wire $or$libresoc.v:132287$5137_Y - attribute \src "libresoc.v:132297.18-132297.122" - wire $or$libresoc.v:132297$5147_Y - attribute \src "libresoc.v:132298.18-132298.124" - wire $or$libresoc.v:132298$5148_Y - attribute \src "libresoc.v:132300.18-132300.168" - wire width 4 $or$libresoc.v:132300$5150_Y - attribute \src "libresoc.v:132301.18-132301.155" - wire width 3 $or$libresoc.v:132301$5151_Y - attribute \src "libresoc.v:132304.18-132304.120" - wire width 4 $or$libresoc.v:132304$5154_Y - attribute \src "libresoc.v:132310.17-132310.117" - wire width 3 $or$libresoc.v:132310$5160_Y - attribute \src "libresoc.v:132315.17-132315.104" - wire $reduce_and$libresoc.v:132315$5165_Y - attribute \src "libresoc.v:132281.18-132281.106" - wire $reduce_or$libresoc.v:132281$5131_Y - attribute \src "libresoc.v:132285.18-132285.113" - wire $reduce_or$libresoc.v:132285$5135_Y - attribute \src "libresoc.v:132286.18-132286.112" - wire $reduce_or$libresoc.v:132286$5136_Y - attribute \src "libresoc.v:132309.18-132309.158" - wire $ternary$libresoc.v:132309$5159_Y - attribute \src "libresoc.v:132311.18-132311.159" - wire width 64 $ternary$libresoc.v:132311$5161_Y - attribute \src "libresoc.v:132312.18-132312.164" - wire $ternary$libresoc.v:132312$5162_Y - attribute \src "libresoc.v:132313.18-132313.180" - wire width 64 $ternary$libresoc.v:132313$5163_Y - attribute \src "libresoc.v:132314.18-132314.115" - wire width 64 $ternary$libresoc.v:132314$5164_Y - attribute \src "libresoc.v:132316.18-132316.125" - wire width 64 $ternary$libresoc.v:132316$5166_Y - attribute \src "libresoc.v:132317.18-132317.118" - wire $ternary$libresoc.v:132317$5167_Y + attribute \src "libresoc.v:133231.3-133269.6" + wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5267 + attribute \src "libresoc.v:133231.3-133269.6" + wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 + attribute \src "libresoc.v:133231.3-133269.6" + wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5269 + attribute \src "libresoc.v:133231.3-133269.6" + wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5270 + attribute \src "libresoc.v:133231.3-133269.6" + wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5271 + attribute \src "libresoc.v:133231.3-133269.6" + wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5272 + attribute \src "libresoc.v:133270.3-133291.6" + wire width 64 $2\data_r0__o$next[63:0]$5278 + attribute \src "libresoc.v:133270.3-133291.6" + wire $2\data_r0__o_ok$next[0:0]$5279 + attribute \src "libresoc.v:133292.3-133313.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$5286 + attribute \src "libresoc.v:133292.3-133313.6" + wire $2\data_r1__cr_a_ok$next[0:0]$5287 + attribute \src "libresoc.v:133314.3-133335.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$5294 + attribute \src "libresoc.v:133314.3-133335.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$5295 + attribute \src "libresoc.v:133336.3-133357.6" + wire $2\data_r3__xer_so$next[0:0]$5302 + attribute \src "libresoc.v:133336.3-133357.6" + wire $2\data_r3__xer_so_ok$next[0:0]$5303 + attribute \src "libresoc.v:133270.3-133291.6" + wire $3\data_r0__o_ok$next[0:0]$5280 + attribute \src "libresoc.v:133292.3-133313.6" + wire $3\data_r1__cr_a_ok$next[0:0]$5288 + attribute \src "libresoc.v:133314.3-133335.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$5296 + attribute \src "libresoc.v:133336.3-133357.6" + wire $3\data_r3__xer_so_ok$next[0:0]$5304 + attribute \src "libresoc.v:132897.19-132897.133" + wire width 3 $and$libresoc.v:132897$5094_Y + attribute \src "libresoc.v:132899.19-132899.115" + wire width 3 $and$libresoc.v:132899$5096_Y + attribute \src "libresoc.v:132900.18-132900.110" + wire $and$libresoc.v:132900$5097_Y + attribute \src "libresoc.v:132901.19-132901.125" + wire $and$libresoc.v:132901$5098_Y + attribute \src "libresoc.v:132902.19-132902.125" + wire $and$libresoc.v:132902$5099_Y + attribute \src "libresoc.v:132903.19-132903.125" + wire $and$libresoc.v:132903$5100_Y + attribute \src "libresoc.v:132904.19-132904.125" + wire $and$libresoc.v:132904$5101_Y + attribute \src "libresoc.v:132905.19-132905.149" + wire width 4 $and$libresoc.v:132905$5102_Y + attribute \src "libresoc.v:132906.19-132906.121" + wire width 4 $and$libresoc.v:132906$5103_Y + attribute \src "libresoc.v:132907.19-132907.127" + wire $and$libresoc.v:132907$5104_Y + attribute \src "libresoc.v:132908.19-132908.127" + wire $and$libresoc.v:132908$5105_Y + attribute \src "libresoc.v:132909.19-132909.127" + wire $and$libresoc.v:132909$5106_Y + attribute \src "libresoc.v:132910.19-132910.127" + wire $and$libresoc.v:132910$5107_Y + attribute \src "libresoc.v:132912.18-132912.98" + wire $and$libresoc.v:132912$5109_Y + attribute \src "libresoc.v:132914.18-132914.100" + wire $and$libresoc.v:132914$5111_Y + attribute \src "libresoc.v:132915.18-132915.160" + wire width 4 $and$libresoc.v:132915$5112_Y + attribute \src "libresoc.v:132917.18-132917.119" + wire width 4 $and$libresoc.v:132917$5114_Y + attribute \src "libresoc.v:132920.17-132920.123" + wire $and$libresoc.v:132920$5117_Y + attribute \src "libresoc.v:132921.18-132921.116" + wire $and$libresoc.v:132921$5118_Y + attribute \src "libresoc.v:132926.18-132926.113" + wire $and$libresoc.v:132926$5123_Y + attribute \src "libresoc.v:132927.18-132927.125" + wire width 4 $and$libresoc.v:132927$5124_Y + attribute \src "libresoc.v:132929.18-132929.112" + wire $and$libresoc.v:132929$5126_Y + attribute \src "libresoc.v:132931.18-132931.126" + wire $and$libresoc.v:132931$5128_Y + attribute \src "libresoc.v:132932.18-132932.126" + wire $and$libresoc.v:132932$5129_Y + attribute \src "libresoc.v:132933.18-132933.117" + wire $and$libresoc.v:132933$5130_Y + attribute \src "libresoc.v:132939.18-132939.130" + wire $and$libresoc.v:132939$5136_Y + attribute \src "libresoc.v:132940.18-132940.124" + wire width 4 $and$libresoc.v:132940$5137_Y + attribute \src "libresoc.v:132942.18-132942.116" + wire $and$libresoc.v:132942$5139_Y + attribute \src "libresoc.v:132943.18-132943.119" + wire $and$libresoc.v:132943$5140_Y + attribute \src "libresoc.v:132944.18-132944.121" + wire $and$libresoc.v:132944$5141_Y + attribute \src "libresoc.v:132945.18-132945.121" + wire $and$libresoc.v:132945$5142_Y + attribute \src "libresoc.v:132955.18-132955.134" + wire $and$libresoc.v:132955$5152_Y + attribute \src "libresoc.v:132956.18-132956.132" + wire $and$libresoc.v:132956$5153_Y + attribute \src "libresoc.v:132957.18-132957.149" + wire width 3 $and$libresoc.v:132957$5154_Y + attribute \src "libresoc.v:132928.18-132928.113" + wire $eq$libresoc.v:132928$5125_Y + attribute \src "libresoc.v:132930.18-132930.119" + wire $eq$libresoc.v:132930$5127_Y + attribute \src "libresoc.v:132895.19-132895.130" + wire $not$libresoc.v:132895$5092_Y + attribute \src "libresoc.v:132896.19-132896.136" + wire $not$libresoc.v:132896$5093_Y + attribute \src "libresoc.v:132898.19-132898.115" + wire width 3 $not$libresoc.v:132898$5095_Y + attribute \src "libresoc.v:132911.18-132911.97" + wire $not$libresoc.v:132911$5108_Y + attribute \src "libresoc.v:132913.18-132913.99" + wire $not$libresoc.v:132913$5110_Y + attribute \src "libresoc.v:132916.18-132916.113" + wire width 4 $not$libresoc.v:132916$5113_Y + attribute \src "libresoc.v:132919.18-132919.106" + wire $not$libresoc.v:132919$5116_Y + attribute \src "libresoc.v:132925.18-132925.120" + wire $not$libresoc.v:132925$5122_Y + attribute \src "libresoc.v:132936.17-132936.113" + wire width 3 $not$libresoc.v:132936$5133_Y + attribute \src "libresoc.v:132924.18-132924.112" + wire $or$libresoc.v:132924$5121_Y + attribute \src "libresoc.v:132934.18-132934.122" + wire $or$libresoc.v:132934$5131_Y + attribute \src "libresoc.v:132935.18-132935.124" + wire $or$libresoc.v:132935$5132_Y + attribute \src "libresoc.v:132937.18-132937.168" + wire width 4 $or$libresoc.v:132937$5134_Y + attribute \src "libresoc.v:132938.18-132938.155" + wire width 3 $or$libresoc.v:132938$5135_Y + attribute \src "libresoc.v:132941.18-132941.120" + wire width 4 $or$libresoc.v:132941$5138_Y + attribute \src "libresoc.v:132947.17-132947.117" + wire width 3 $or$libresoc.v:132947$5144_Y + attribute \src "libresoc.v:132952.17-132952.104" + wire $reduce_and$libresoc.v:132952$5149_Y + attribute \src "libresoc.v:132918.18-132918.106" + wire $reduce_or$libresoc.v:132918$5115_Y + attribute \src "libresoc.v:132922.18-132922.113" + wire $reduce_or$libresoc.v:132922$5119_Y + attribute \src "libresoc.v:132923.18-132923.112" + wire $reduce_or$libresoc.v:132923$5120_Y + attribute \src "libresoc.v:132946.18-132946.158" + wire $ternary$libresoc.v:132946$5143_Y + attribute \src "libresoc.v:132948.18-132948.159" + wire width 64 $ternary$libresoc.v:132948$5145_Y + attribute \src "libresoc.v:132949.18-132949.164" + wire $ternary$libresoc.v:132949$5146_Y + attribute \src "libresoc.v:132950.18-132950.180" + wire width 64 $ternary$libresoc.v:132950$5147_Y + attribute \src "libresoc.v:132951.18-132951.115" + wire width 64 $ternary$libresoc.v:132951$5148_Y + attribute \src "libresoc.v:132953.18-132953.125" + wire width 64 $ternary$libresoc.v:132953$5150_Y + attribute \src "libresoc.v:132954.18-132954.118" + wire $ternary$libresoc.v:132954$5151_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" @@ -207630,7 +207875,7 @@ module \div0 wire \all_rd_pulse attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \alu_div0_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_div0_logical_op__data_len @@ -207802,7 +208047,7 @@ module \div0 wire \alu_div0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_div0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_div0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_div0_p_ready_o @@ -207812,9 +208057,9 @@ module \div0 wire width 64 \alu_div0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_div0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \alu_div0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \alu_div0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_div0_xer_so$1 @@ -207846,11 +208091,11 @@ module \div0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 32 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 21 \cu_busy_o @@ -207914,9 +208159,9 @@ module \div0 wire width 2 output 35 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 37 \dest4_o - attribute \src "libresoc.v:131607.7-131607.15" + attribute \src "libresoc.v:132244.7-132244.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc @@ -208101,9 +208346,9 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 25 \src1_i + wire width 64 input 26 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 26 \src2_i + wire width 64 input 25 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 27 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" @@ -208138,12 +208383,12 @@ module \div0 wire \src_sel$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 34 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 36 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:132260$5110 + cell $and $and$libresoc.v:132897$5094 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -208151,10 +208396,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$98 connect \B { 1'1 \$102 \$100 } - connect \Y $and$libresoc.v:132260$5110_Y + connect \Y $and$libresoc.v:132897$5094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:132262$5112 + cell $and $and$libresoc.v:132899$5096 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -208162,10 +208407,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:132262$5112_Y + connect \Y $and$libresoc.v:132899$5096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:132263$5113 + cell $and $and$libresoc.v:132900$5097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208173,10 +208418,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:132263$5113_Y + connect \Y $and$libresoc.v:132900$5097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:132264$5114 + cell $and $and$libresoc.v:132901$5098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208184,10 +208429,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:132264$5114_Y + connect \Y $and$libresoc.v:132901$5098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:132265$5115 + cell $and $and$libresoc.v:132902$5099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208195,10 +208440,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:132265$5115_Y + connect \Y $and$libresoc.v:132902$5099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:132266$5116 + cell $and $and$libresoc.v:132903$5100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208206,10 +208451,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:132266$5116_Y + connect \Y $and$libresoc.v:132903$5100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:132267$5117 + cell $and $and$libresoc.v:132904$5101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208217,10 +208462,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:132267$5117_Y + connect \Y $and$libresoc.v:132904$5101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:132268$5118 + cell $and $and$libresoc.v:132905$5102 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208228,10 +208473,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 } - connect \Y $and$libresoc.v:132268$5118_Y + connect \Y $and$libresoc.v:132905$5102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:132269$5119 + cell $and $and$libresoc.v:132906$5103 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208239,10 +208484,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \$118 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:132269$5119_Y + connect \Y $and$libresoc.v:132906$5103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:132270$5120 + cell $and $and$libresoc.v:132907$5104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208250,10 +208495,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:132270$5120_Y + connect \Y $and$libresoc.v:132907$5104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:132271$5121 + cell $and $and$libresoc.v:132908$5105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208261,10 +208506,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:132271$5121_Y + connect \Y $and$libresoc.v:132908$5105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:132272$5122 + cell $and $and$libresoc.v:132909$5106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208272,10 +208517,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:132272$5122_Y + connect \Y $and$libresoc.v:132909$5106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:132273$5123 + cell $and $and$libresoc.v:132910$5107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208283,10 +208528,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:132273$5123_Y + connect \Y $and$libresoc.v:132910$5107_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:132275$5125 + cell $and $and$libresoc.v:132912$5109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208294,10 +208539,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:132275$5125_Y + connect \Y $and$libresoc.v:132912$5109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:132277$5127 + cell $and $and$libresoc.v:132914$5111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208305,10 +208550,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:132277$5127_Y + connect \Y $and$libresoc.v:132914$5111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:132278$5128 + cell $and $and$libresoc.v:132915$5112 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208316,10 +208561,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:132278$5128_Y + connect \Y $and$libresoc.v:132915$5112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:132280$5130 + cell $and $and$libresoc.v:132917$5114 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208327,10 +208572,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:132280$5130_Y + connect \Y $and$libresoc.v:132917$5114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:132283$5133 + cell $and $and$libresoc.v:132920$5117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208338,10 +208583,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:132283$5133_Y + connect \Y $and$libresoc.v:132920$5117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:132284$5134 + cell $and $and$libresoc.v:132921$5118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208349,10 +208594,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:132284$5134_Y + connect \Y $and$libresoc.v:132921$5118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:132289$5139 + cell $and $and$libresoc.v:132926$5123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208360,10 +208605,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:132289$5139_Y + connect \Y $and$libresoc.v:132926$5123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:132290$5140 + cell $and $and$libresoc.v:132927$5124 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208371,10 +208616,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:132290$5140_Y + connect \Y $and$libresoc.v:132927$5124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:132292$5142 + cell $and $and$libresoc.v:132929$5126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208382,10 +208627,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:132292$5142_Y + connect \Y $and$libresoc.v:132929$5126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:132294$5144 + cell $and $and$libresoc.v:132931$5128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208393,10 +208638,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_div0_n_ready_i - connect \Y $and$libresoc.v:132294$5144_Y + connect \Y $and$libresoc.v:132931$5128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:132295$5145 + cell $and $and$libresoc.v:132932$5129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208404,10 +208649,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_div0_n_valid_o - connect \Y $and$libresoc.v:132295$5145_Y + connect \Y $and$libresoc.v:132932$5129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:132296$5146 + cell $and $and$libresoc.v:132933$5130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208415,10 +208660,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:132296$5146_Y + connect \Y $and$libresoc.v:132933$5130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:132302$5152 + cell $and $and$libresoc.v:132939$5136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208426,10 +208671,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:132302$5152_Y + connect \Y $and$libresoc.v:132939$5136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:132303$5153 + cell $and $and$libresoc.v:132940$5137 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208437,10 +208682,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:132303$5153_Y + connect \Y $and$libresoc.v:132940$5137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:132305$5155 + cell $and $and$libresoc.v:132942$5139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208448,10 +208693,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:132305$5155_Y + connect \Y $and$libresoc.v:132942$5139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:132306$5156 + cell $and $and$libresoc.v:132943$5140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208459,10 +208704,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:132306$5156_Y + connect \Y $and$libresoc.v:132943$5140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:132307$5157 + cell $and $and$libresoc.v:132944$5141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208470,10 +208715,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:132307$5157_Y + connect \Y $and$libresoc.v:132944$5141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:132308$5158 + cell $and $and$libresoc.v:132945$5142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208481,10 +208726,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:132308$5158_Y + connect \Y $and$libresoc.v:132945$5142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:132318$5168 + cell $and $and$libresoc.v:132955$5152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208492,10 +208737,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:132318$5168_Y + connect \Y $and$libresoc.v:132955$5152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:132319$5169 + cell $and $and$libresoc.v:132956$5153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208503,10 +208748,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:132319$5169_Y + connect \Y $and$libresoc.v:132956$5153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:132320$5170 + cell $and $and$libresoc.v:132957$5154 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -208514,10 +208759,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:132320$5170_Y + connect \Y $and$libresoc.v:132957$5154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:132291$5141 + cell $eq $eq$libresoc.v:132928$5125 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208525,10 +208770,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:132291$5141_Y + connect \Y $eq$libresoc.v:132928$5125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:132293$5143 + cell $eq $eq$libresoc.v:132930$5127 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208536,82 +208781,82 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:132293$5143_Y + connect \Y $eq$libresoc.v:132930$5127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:132258$5108 + cell $not $not$libresoc.v:132895$5092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__zero_a - connect \Y $not$libresoc.v:132258$5108_Y + connect \Y $not$libresoc.v:132895$5092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:132259$5109 + cell $not $not$libresoc.v:132896$5093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:132259$5109_Y + connect \Y $not$libresoc.v:132896$5093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:132261$5111 + cell $not $not$libresoc.v:132898$5095 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:132261$5111_Y + connect \Y $not$libresoc.v:132898$5095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:132274$5124 + cell $not $not$libresoc.v:132911$5108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:132274$5124_Y + connect \Y $not$libresoc.v:132911$5108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:132276$5126 + cell $not $not$libresoc.v:132913$5110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:132276$5126_Y + connect \Y $not$libresoc.v:132913$5110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:132279$5129 + cell $not $not$libresoc.v:132916$5113 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:132279$5129_Y + connect \Y $not$libresoc.v:132916$5113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:132282$5132 + cell $not $not$libresoc.v:132919$5116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:132282$5132_Y + connect \Y $not$libresoc.v:132919$5116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:132288$5138 + cell $not $not$libresoc.v:132925$5122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_n_ready_i - connect \Y $not$libresoc.v:132288$5138_Y + connect \Y $not$libresoc.v:132925$5122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:132299$5149 + cell $not $not$libresoc.v:132936$5133 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:132299$5149_Y + connect \Y $not$libresoc.v:132936$5133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:132287$5137 + cell $or $or$libresoc.v:132924$5121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208619,10 +208864,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:132287$5137_Y + connect \Y $or$libresoc.v:132924$5121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:132297$5147 + cell $or $or$libresoc.v:132934$5131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208630,10 +208875,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:132297$5147_Y + connect \Y $or$libresoc.v:132934$5131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:132298$5148 + cell $or $or$libresoc.v:132935$5132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208641,10 +208886,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:132298$5148_Y + connect \Y $or$libresoc.v:132935$5132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:132300$5150 + cell $or $or$libresoc.v:132937$5134 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208652,10 +208897,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:132300$5150_Y + connect \Y $or$libresoc.v:132937$5134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:132301$5151 + cell $or $or$libresoc.v:132938$5135 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -208663,10 +208908,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:132301$5151_Y + connect \Y $or$libresoc.v:132938$5135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:132304$5154 + cell $or $or$libresoc.v:132941$5138 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208674,10 +208919,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:132304$5154_Y + connect \Y $or$libresoc.v:132941$5138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:132310$5160 + cell $or $or$libresoc.v:132947$5144 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -208685,98 +208930,98 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:132310$5160_Y + connect \Y $or$libresoc.v:132947$5144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:132315$5165 + cell $reduce_and $reduce_and$libresoc.v:132952$5149 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:132315$5165_Y + connect \Y $reduce_and$libresoc.v:132952$5149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:132281$5131 + cell $reduce_or $reduce_or$libresoc.v:132918$5115 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:132281$5131_Y + connect \Y $reduce_or$libresoc.v:132918$5115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:132285$5135 + cell $reduce_or $reduce_or$libresoc.v:132922$5119 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:132285$5135_Y + connect \Y $reduce_or$libresoc.v:132922$5119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:132286$5136 + cell $reduce_or $reduce_or$libresoc.v:132923$5120 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:132286$5136_Y + connect \Y $reduce_or$libresoc.v:132923$5120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:132309$5159 + cell $mux $ternary$libresoc.v:132946$5143 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:132309$5159_Y + connect \Y $ternary$libresoc.v:132946$5143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:132311$5161 + cell $mux $ternary$libresoc.v:132948$5145 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:132311$5161_Y + connect \Y $ternary$libresoc.v:132948$5145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:132312$5162 + cell $mux $ternary$libresoc.v:132949$5146 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:132312$5162_Y + connect \Y $ternary$libresoc.v:132949$5146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:132313$5163 + cell $mux $ternary$libresoc.v:132950$5147 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_div0_logical_op__imm_data__data connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:132313$5163_Y + connect \Y $ternary$libresoc.v:132950$5147_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:132314$5164 + cell $mux $ternary$libresoc.v:132951$5148 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:132314$5164_Y + connect \Y $ternary$libresoc.v:132951$5148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:132316$5166 + cell $mux $ternary$libresoc.v:132953$5150 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$85 connect \S \src_sel$82 - connect \Y $ternary$libresoc.v:132316$5166_Y + connect \Y $ternary$libresoc.v:132953$5150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:132317$5167 + cell $mux $ternary$libresoc.v:132954$5151 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:132317$5167_Y + connect \Y $ternary$libresoc.v:132954$5151_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:132409.12-132445.4" + attribute \src "libresoc.v:133046.12-133082.4" cell \alu_div0 \alu_div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208815,7 +209060,7 @@ module \div0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:132446.14-132452.4" + attribute \src "libresoc.v:133083.14-133089.4" cell \alu_l$90 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208824,7 +209069,7 @@ module \div0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:132453.15-132459.4" + attribute \src "libresoc.v:133090.15-133096.4" cell \alui_l$89 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208833,7 +209078,7 @@ module \div0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:132460.14-132466.4" + attribute \src "libresoc.v:133097.14-133103.4" cell \opc_l$85 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208842,7 +209087,7 @@ module \div0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:132467.14-132473.4" + attribute \src "libresoc.v:133104.14-133110.4" cell \req_l$86 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208851,7 +209096,7 @@ module \div0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:132474.14-132480.4" + attribute \src "libresoc.v:133111.14-133117.4" cell \rok_l$88 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208860,7 +209105,7 @@ module \div0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:132481.14-132486.4" + attribute \src "libresoc.v:133118.14-133123.4" cell \rst_l$87 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208868,7 +209113,7 @@ module \div0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:132487.14-132493.4" + attribute \src "libresoc.v:133124.14-133130.4" cell \src_l$84 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208876,682 +209121,682 @@ module \div0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:131607.7-131607.20" - process $proc$libresoc.v:131607$5343 + attribute \src "libresoc.v:132244.7-132244.20" + process $proc$libresoc.v:132244$5327 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131737.7-131737.24" - process $proc$libresoc.v:131737$5344 + attribute \src "libresoc.v:132374.7-132374.24" + process $proc$libresoc.v:132374$5328 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:131747.13-131747.49" - process $proc$libresoc.v:131747$5345 + attribute \src "libresoc.v:132384.13-132384.49" + process $proc$libresoc.v:132384$5329 assign { } { } assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:131766.14-131766.53" - process $proc$libresoc.v:131766$5346 + attribute \src "libresoc.v:132403.14-132403.53" + process $proc$libresoc.v:132403$5330 assign { } { } assign $1\alu_div0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:131770.14-131770.72" - process $proc$libresoc.v:131770$5347 + attribute \src "libresoc.v:132407.14-132407.72" + process $proc$libresoc.v:132407$5331 assign { } { } assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:131774.7-131774.47" - process $proc$libresoc.v:131774$5348 + attribute \src "libresoc.v:132411.7-132411.47" + process $proc$libresoc.v:132411$5332 assign { } { } assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:131782.13-131782.52" - process $proc$libresoc.v:131782$5349 + attribute \src "libresoc.v:132419.13-132419.52" + process $proc$libresoc.v:132419$5333 assign { } { } assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:131786.14-131786.47" - process $proc$libresoc.v:131786$5350 + attribute \src "libresoc.v:132423.14-132423.47" + process $proc$libresoc.v:132423$5334 assign { } { } assign $1\alu_div0_logical_op__insn[31:0] 0 sync always sync init update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:131865.13-131865.51" - process $proc$libresoc.v:131865$5351 + attribute \src "libresoc.v:132502.13-132502.51" + process $proc$libresoc.v:132502$5335 assign { } { } assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:131869.7-131869.44" - process $proc$libresoc.v:131869$5352 + attribute \src "libresoc.v:132506.7-132506.44" + process $proc$libresoc.v:132506$5336 assign { } { } assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:131873.7-131873.45" - process $proc$libresoc.v:131873$5353 + attribute \src "libresoc.v:132510.7-132510.45" + process $proc$libresoc.v:132510$5337 assign { } { } assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:131877.7-131877.43" - process $proc$libresoc.v:131877$5354 + attribute \src "libresoc.v:132514.7-132514.43" + process $proc$libresoc.v:132514$5338 assign { } { } assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:131881.7-131881.44" - process $proc$libresoc.v:131881$5355 + attribute \src "libresoc.v:132518.7-132518.44" + process $proc$libresoc.v:132518$5339 assign { } { } assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:131885.7-131885.41" - process $proc$libresoc.v:131885$5356 + attribute \src "libresoc.v:132522.7-132522.41" + process $proc$libresoc.v:132522$5340 assign { } { } assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:131889.7-131889.41" - process $proc$libresoc.v:131889$5357 + attribute \src "libresoc.v:132526.7-132526.41" + process $proc$libresoc.v:132526$5341 assign { } { } assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:131893.7-131893.47" - process $proc$libresoc.v:131893$5358 + attribute \src "libresoc.v:132530.7-132530.47" + process $proc$libresoc.v:132530$5342 assign { } { } assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:131897.7-131897.41" - process $proc$libresoc.v:131897$5359 + attribute \src "libresoc.v:132534.7-132534.41" + process $proc$libresoc.v:132534$5343 assign { } { } assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:131901.7-131901.41" - process $proc$libresoc.v:131901$5360 + attribute \src "libresoc.v:132538.7-132538.41" + process $proc$libresoc.v:132538$5344 assign { } { } assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:131905.7-131905.44" - process $proc$libresoc.v:131905$5361 + attribute \src "libresoc.v:132542.7-132542.44" + process $proc$libresoc.v:132542$5345 assign { } { } assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:131909.7-131909.41" - process $proc$libresoc.v:131909$5362 + attribute \src "libresoc.v:132546.7-132546.41" + process $proc$libresoc.v:132546$5346 assign { } { } assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:131935.7-131935.26" - process $proc$libresoc.v:131935$5363 + attribute \src "libresoc.v:132572.7-132572.26" + process $proc$libresoc.v:132572$5347 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:131943.7-131943.25" - process $proc$libresoc.v:131943$5364 + attribute \src "libresoc.v:132580.7-132580.25" + process $proc$libresoc.v:132580$5348 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:131955.7-131955.27" - process $proc$libresoc.v:131955$5365 + attribute \src "libresoc.v:132592.7-132592.27" + process $proc$libresoc.v:132592$5349 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:131989.14-131989.47" - process $proc$libresoc.v:131989$5366 + attribute \src "libresoc.v:132626.14-132626.47" + process $proc$libresoc.v:132626$5350 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:131993.7-131993.27" - process $proc$libresoc.v:131993$5367 + attribute \src "libresoc.v:132630.7-132630.27" + process $proc$libresoc.v:132630$5351 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:131997.13-131997.33" - process $proc$libresoc.v:131997$5368 + attribute \src "libresoc.v:132634.13-132634.33" + process $proc$libresoc.v:132634$5352 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:132001.7-132001.30" - process $proc$libresoc.v:132001$5369 + attribute \src "libresoc.v:132638.7-132638.30" + process $proc$libresoc.v:132638$5353 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:132005.13-132005.35" - process $proc$libresoc.v:132005$5370 + attribute \src "libresoc.v:132642.13-132642.35" + process $proc$libresoc.v:132642$5354 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:132009.7-132009.32" - process $proc$libresoc.v:132009$5371 + attribute \src "libresoc.v:132646.7-132646.32" + process $proc$libresoc.v:132646$5355 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:132013.7-132013.29" - process $proc$libresoc.v:132013$5372 + attribute \src "libresoc.v:132650.7-132650.29" + process $proc$libresoc.v:132650$5356 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:132017.7-132017.32" - process $proc$libresoc.v:132017$5373 + attribute \src "libresoc.v:132654.7-132654.32" + process $proc$libresoc.v:132654$5357 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:132037.7-132037.25" - process $proc$libresoc.v:132037$5374 + attribute \src "libresoc.v:132674.7-132674.25" + process $proc$libresoc.v:132674$5358 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:132041.7-132041.25" - process $proc$libresoc.v:132041$5375 + attribute \src "libresoc.v:132678.7-132678.25" + process $proc$libresoc.v:132678$5359 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:132175.13-132175.30" - process $proc$libresoc.v:132175$5376 + attribute \src "libresoc.v:132812.13-132812.30" + process $proc$libresoc.v:132812$5360 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:132183.13-132183.31" - process $proc$libresoc.v:132183$5377 + attribute \src "libresoc.v:132820.13-132820.31" + process $proc$libresoc.v:132820$5361 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:132187.13-132187.31" - process $proc$libresoc.v:132187$5378 + attribute \src "libresoc.v:132824.13-132824.31" + process $proc$libresoc.v:132824$5362 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:132199.7-132199.26" - process $proc$libresoc.v:132199$5379 + attribute \src "libresoc.v:132836.7-132836.26" + process $proc$libresoc.v:132836$5363 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:132203.7-132203.26" - process $proc$libresoc.v:132203$5380 + attribute \src "libresoc.v:132840.7-132840.26" + process $proc$libresoc.v:132840$5364 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:132207.7-132207.25" - process $proc$libresoc.v:132207$5381 + attribute \src "libresoc.v:132844.7-132844.25" + process $proc$libresoc.v:132844$5365 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:132211.7-132211.25" - process $proc$libresoc.v:132211$5382 + attribute \src "libresoc.v:132848.7-132848.25" + process $proc$libresoc.v:132848$5366 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:132225.13-132225.31" - process $proc$libresoc.v:132225$5383 + attribute \src "libresoc.v:132862.13-132862.31" + process $proc$libresoc.v:132862$5367 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:132229.13-132229.31" - process $proc$libresoc.v:132229$5384 + attribute \src "libresoc.v:132866.13-132866.31" + process $proc$libresoc.v:132866$5368 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:132237.14-132237.43" - process $proc$libresoc.v:132237$5385 + attribute \src "libresoc.v:132874.14-132874.43" + process $proc$libresoc.v:132874$5369 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:132241.14-132241.43" - process $proc$libresoc.v:132241$5386 + attribute \src "libresoc.v:132878.14-132878.43" + process $proc$libresoc.v:132878$5370 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:132245.7-132245.20" - process $proc$libresoc.v:132245$5387 + attribute \src "libresoc.v:132882.7-132882.20" + process $proc$libresoc.v:132882$5371 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:132321.3-132322.39" - process $proc$libresoc.v:132321$5171 + attribute \src "libresoc.v:132958.3-132959.39" + process $proc$libresoc.v:132958$5155 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:132323.3-132324.43" - process $proc$libresoc.v:132323$5172 + attribute \src "libresoc.v:132960.3-132961.43" + process $proc$libresoc.v:132960$5156 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:132325.3-132326.29" - process $proc$libresoc.v:132325$5173 + attribute \src "libresoc.v:132962.3-132963.29" + process $proc$libresoc.v:132962$5157 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:132327.3-132328.29" - process $proc$libresoc.v:132327$5174 + attribute \src "libresoc.v:132964.3-132965.29" + process $proc$libresoc.v:132964$5158 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:132329.3-132330.29" - process $proc$libresoc.v:132329$5175 + attribute \src "libresoc.v:132966.3-132967.29" + process $proc$libresoc.v:132966$5159 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:132331.3-132332.47" - process $proc$libresoc.v:132331$5176 + attribute \src "libresoc.v:132968.3-132969.47" + process $proc$libresoc.v:132968$5160 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:132333.3-132334.53" - process $proc$libresoc.v:132333$5177 + attribute \src "libresoc.v:132970.3-132971.53" + process $proc$libresoc.v:132970$5161 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:132335.3-132336.47" - process $proc$libresoc.v:132335$5178 + attribute \src "libresoc.v:132972.3-132973.47" + process $proc$libresoc.v:132972$5162 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:132337.3-132338.53" - process $proc$libresoc.v:132337$5179 + attribute \src "libresoc.v:132974.3-132975.53" + process $proc$libresoc.v:132974$5163 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:132339.3-132340.43" - process $proc$libresoc.v:132339$5180 + attribute \src "libresoc.v:132976.3-132977.43" + process $proc$libresoc.v:132976$5164 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:132341.3-132342.49" - process $proc$libresoc.v:132341$5181 + attribute \src "libresoc.v:132978.3-132979.49" + process $proc$libresoc.v:132978$5165 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:132343.3-132344.37" - process $proc$libresoc.v:132343$5182 + attribute \src "libresoc.v:132980.3-132981.37" + process $proc$libresoc.v:132980$5166 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:132345.3-132346.43" - process $proc$libresoc.v:132345$5183 + attribute \src "libresoc.v:132982.3-132983.43" + process $proc$libresoc.v:132982$5167 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:132347.3-132348.77" - process $proc$libresoc.v:132347$5184 + attribute \src "libresoc.v:132984.3-132985.77" + process $proc$libresoc.v:132984$5168 assign { } { } assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:132349.3-132350.73" - process $proc$libresoc.v:132349$5185 + attribute \src "libresoc.v:132986.3-132987.73" + process $proc$libresoc.v:132986$5169 assign { } { } assign $0\alu_div0_logical_op__fn_unit[13:0] \alu_div0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:132351.3-132352.87" - process $proc$libresoc.v:132351$5186 + attribute \src "libresoc.v:132988.3-132989.87" + process $proc$libresoc.v:132988$5170 assign { } { } assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:132353.3-132354.83" - process $proc$libresoc.v:132353$5187 + attribute \src "libresoc.v:132990.3-132991.83" + process $proc$libresoc.v:132990$5171 assign { } { } assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:132355.3-132356.71" - process $proc$libresoc.v:132355$5188 + attribute \src "libresoc.v:132992.3-132993.71" + process $proc$libresoc.v:132992$5172 assign { } { } assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:132357.3-132358.71" - process $proc$libresoc.v:132357$5189 + attribute \src "libresoc.v:132994.3-132995.71" + process $proc$libresoc.v:132994$5173 assign { } { } assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:132359.3-132360.71" - process $proc$libresoc.v:132359$5190 + attribute \src "libresoc.v:132996.3-132997.71" + process $proc$libresoc.v:132996$5174 assign { } { } assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:132361.3-132362.71" - process $proc$libresoc.v:132361$5191 + attribute \src "libresoc.v:132998.3-132999.71" + process $proc$libresoc.v:132998$5175 assign { } { } assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:132363.3-132364.77" - process $proc$libresoc.v:132363$5192 + attribute \src "libresoc.v:133000.3-133001.77" + process $proc$libresoc.v:133000$5176 assign { } { } assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:132365.3-132366.71" - process $proc$libresoc.v:132365$5193 + attribute \src "libresoc.v:133002.3-133003.71" + process $proc$libresoc.v:133002$5177 assign { } { } assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:132367.3-132368.81" - process $proc$libresoc.v:132367$5194 + attribute \src "libresoc.v:133004.3-133005.81" + process $proc$libresoc.v:133004$5178 assign { } { } assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:132369.3-132370.79" - process $proc$libresoc.v:132369$5195 + attribute \src "libresoc.v:133006.3-133007.79" + process $proc$libresoc.v:133006$5179 assign { } { } assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:132371.3-132372.77" - process $proc$libresoc.v:132371$5196 + attribute \src "libresoc.v:133008.3-133009.77" + process $proc$libresoc.v:133008$5180 assign { } { } assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:132373.3-132374.83" - process $proc$libresoc.v:132373$5197 + attribute \src "libresoc.v:133010.3-133011.83" + process $proc$libresoc.v:133010$5181 assign { } { } assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:132375.3-132376.75" - process $proc$libresoc.v:132375$5198 + attribute \src "libresoc.v:133012.3-133013.75" + process $proc$libresoc.v:133012$5182 assign { } { } assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:132377.3-132378.77" - process $proc$libresoc.v:132377$5199 + attribute \src "libresoc.v:133014.3-133015.77" + process $proc$libresoc.v:133014$5183 assign { } { } assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:132379.3-132380.75" - process $proc$libresoc.v:132379$5200 + attribute \src "libresoc.v:133016.3-133017.75" + process $proc$libresoc.v:133016$5184 assign { } { } assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next sync posedge \coresync_clk update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:132381.3-132382.67" - process $proc$libresoc.v:132381$5201 + attribute \src "libresoc.v:133018.3-133019.67" + process $proc$libresoc.v:133018$5185 assign { } { } assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next sync posedge \coresync_clk update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:132383.3-132384.39" - process $proc$libresoc.v:132383$5202 + attribute \src "libresoc.v:133020.3-133021.39" + process $proc$libresoc.v:133020$5186 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:132385.3-132386.39" - process $proc$libresoc.v:132385$5203 + attribute \src "libresoc.v:133022.3-133023.39" + process $proc$libresoc.v:133022$5187 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:132387.3-132388.39" - process $proc$libresoc.v:132387$5204 + attribute \src "libresoc.v:133024.3-133025.39" + process $proc$libresoc.v:133024$5188 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:132389.3-132390.39" - process $proc$libresoc.v:132389$5205 + attribute \src "libresoc.v:133026.3-133027.39" + process $proc$libresoc.v:133026$5189 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:132391.3-132392.39" - process $proc$libresoc.v:132391$5206 + attribute \src "libresoc.v:133028.3-133029.39" + process $proc$libresoc.v:133028$5190 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:132393.3-132394.39" - process $proc$libresoc.v:132393$5207 + attribute \src "libresoc.v:133030.3-133031.39" + process $proc$libresoc.v:133030$5191 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:132395.3-132396.39" - process $proc$libresoc.v:132395$5208 + attribute \src "libresoc.v:133032.3-133033.39" + process $proc$libresoc.v:133032$5192 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:132397.3-132398.39" - process $proc$libresoc.v:132397$5209 + attribute \src "libresoc.v:133034.3-133035.39" + process $proc$libresoc.v:133034$5193 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:132399.3-132400.41" - process $proc$libresoc.v:132399$5210 + attribute \src "libresoc.v:133036.3-133037.41" + process $proc$libresoc.v:133036$5194 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:132401.3-132402.41" - process $proc$libresoc.v:132401$5211 + attribute \src "libresoc.v:133038.3-133039.41" + process $proc$libresoc.v:133038$5195 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:132403.3-132404.37" - process $proc$libresoc.v:132403$5212 + attribute \src "libresoc.v:133040.3-133041.37" + process $proc$libresoc.v:133040$5196 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:132405.3-132406.40" - process $proc$libresoc.v:132405$5213 + attribute \src "libresoc.v:133042.3-133043.40" + process $proc$libresoc.v:133042$5197 assign { } { } assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:132407.3-132408.25" - process $proc$libresoc.v:132407$5214 + attribute \src "libresoc.v:133044.3-133045.25" + process $proc$libresoc.v:133044$5198 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:132494.3-132503.6" - process $proc$libresoc.v:132494$5215 + attribute \src "libresoc.v:133131.3-133140.6" + process $proc$libresoc.v:133131$5199 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:132495.5-132495.29" + attribute \src "libresoc.v:133132.5-133132.29" switch \initial - attribute \src "libresoc.v:132495.9-132495.17" + attribute \src "libresoc.v:133132.9-133132.17" case 1'1 case end @@ -209567,14 +209812,14 @@ module \div0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:132504.3-132512.6" - process $proc$libresoc.v:132504$5216 + attribute \src "libresoc.v:133141.3-133149.6" + process $proc$libresoc.v:133141$5200 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$5217 $1\rok_l_s_rdok$next[0:0]$5218 - attribute \src "libresoc.v:132505.5-132505.29" + assign $0\rok_l_s_rdok$next[0:0]$5201 $1\rok_l_s_rdok$next[0:0]$5202 + attribute \src "libresoc.v:133142.5-133142.29" switch \initial - attribute \src "libresoc.v:132505.9-132505.17" + attribute \src "libresoc.v:133142.9-133142.17" case 1'1 case end @@ -209583,21 +209828,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$5218 1'0 + assign $1\rok_l_s_rdok$next[0:0]$5202 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$5218 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$5202 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5217 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5201 end - attribute \src "libresoc.v:132513.3-132521.6" - process $proc$libresoc.v:132513$5219 + attribute \src "libresoc.v:133150.3-133158.6" + process $proc$libresoc.v:133150$5203 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$5220 $1\rok_l_r_rdok$next[0:0]$5221 - attribute \src "libresoc.v:132514.5-132514.29" + assign $0\rok_l_r_rdok$next[0:0]$5204 $1\rok_l_r_rdok$next[0:0]$5205 + attribute \src "libresoc.v:133151.5-133151.29" switch \initial - attribute \src "libresoc.v:132514.9-132514.17" + attribute \src "libresoc.v:133151.9-133151.17" case 1'1 case end @@ -209606,21 +209851,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$5221 1'1 + assign $1\rok_l_r_rdok$next[0:0]$5205 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$5221 \$64 + assign $1\rok_l_r_rdok$next[0:0]$5205 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5220 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5204 end - attribute \src "libresoc.v:132522.3-132530.6" - process $proc$libresoc.v:132522$5222 + attribute \src "libresoc.v:133159.3-133167.6" + process $proc$libresoc.v:133159$5206 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$5223 $1\rst_l_s_rst$next[0:0]$5224 - attribute \src "libresoc.v:132523.5-132523.29" + assign $0\rst_l_s_rst$next[0:0]$5207 $1\rst_l_s_rst$next[0:0]$5208 + attribute \src "libresoc.v:133160.5-133160.29" switch \initial - attribute \src "libresoc.v:132523.9-132523.17" + attribute \src "libresoc.v:133160.9-133160.17" case 1'1 case end @@ -209629,21 +209874,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$5224 1'0 + assign $1\rst_l_s_rst$next[0:0]$5208 1'0 case - assign $1\rst_l_s_rst$next[0:0]$5224 \all_rd + assign $1\rst_l_s_rst$next[0:0]$5208 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5223 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5207 end - attribute \src "libresoc.v:132531.3-132539.6" - process $proc$libresoc.v:132531$5225 + attribute \src "libresoc.v:133168.3-133176.6" + process $proc$libresoc.v:133168$5209 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$5226 $1\rst_l_r_rst$next[0:0]$5227 - attribute \src "libresoc.v:132532.5-132532.29" + assign $0\rst_l_r_rst$next[0:0]$5210 $1\rst_l_r_rst$next[0:0]$5211 + attribute \src "libresoc.v:133169.5-133169.29" switch \initial - attribute \src "libresoc.v:132532.9-132532.17" + attribute \src "libresoc.v:133169.9-133169.17" case 1'1 case end @@ -209652,21 +209897,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$5227 1'1 + assign $1\rst_l_r_rst$next[0:0]$5211 1'1 case - assign $1\rst_l_r_rst$next[0:0]$5227 \rst_r + assign $1\rst_l_r_rst$next[0:0]$5211 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5226 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5210 end - attribute \src "libresoc.v:132540.3-132548.6" - process $proc$libresoc.v:132540$5228 + attribute \src "libresoc.v:133177.3-133185.6" + process $proc$libresoc.v:133177$5212 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$5229 $1\opc_l_s_opc$next[0:0]$5230 - attribute \src "libresoc.v:132541.5-132541.29" + assign $0\opc_l_s_opc$next[0:0]$5213 $1\opc_l_s_opc$next[0:0]$5214 + attribute \src "libresoc.v:133178.5-133178.29" switch \initial - attribute \src "libresoc.v:132541.9-132541.17" + attribute \src "libresoc.v:133178.9-133178.17" case 1'1 case end @@ -209675,21 +209920,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$5230 1'0 + assign $1\opc_l_s_opc$next[0:0]$5214 1'0 case - assign $1\opc_l_s_opc$next[0:0]$5230 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$5214 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5229 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5213 end - attribute \src "libresoc.v:132549.3-132557.6" - process $proc$libresoc.v:132549$5231 + attribute \src "libresoc.v:133186.3-133194.6" + process $proc$libresoc.v:133186$5215 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$5232 $1\opc_l_r_opc$next[0:0]$5233 - attribute \src "libresoc.v:132550.5-132550.29" + assign $0\opc_l_r_opc$next[0:0]$5216 $1\opc_l_r_opc$next[0:0]$5217 + attribute \src "libresoc.v:133187.5-133187.29" switch \initial - attribute \src "libresoc.v:132550.9-132550.17" + attribute \src "libresoc.v:133187.9-133187.17" case 1'1 case end @@ -209698,21 +209943,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$5233 1'1 + assign $1\opc_l_r_opc$next[0:0]$5217 1'1 case - assign $1\opc_l_r_opc$next[0:0]$5233 \req_done + assign $1\opc_l_r_opc$next[0:0]$5217 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5232 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5216 end - attribute \src "libresoc.v:132558.3-132566.6" - process $proc$libresoc.v:132558$5234 + attribute \src "libresoc.v:133195.3-133203.6" + process $proc$libresoc.v:133195$5218 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$5235 $1\src_l_s_src$next[2:0]$5236 - attribute \src "libresoc.v:132559.5-132559.29" + assign $0\src_l_s_src$next[2:0]$5219 $1\src_l_s_src$next[2:0]$5220 + attribute \src "libresoc.v:133196.5-133196.29" switch \initial - attribute \src "libresoc.v:132559.9-132559.17" + attribute \src "libresoc.v:133196.9-133196.17" case 1'1 case end @@ -209721,21 +209966,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$5236 3'000 + assign $1\src_l_s_src$next[2:0]$5220 3'000 case - assign $1\src_l_s_src$next[2:0]$5236 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$5220 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5235 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5219 end - attribute \src "libresoc.v:132567.3-132575.6" - process $proc$libresoc.v:132567$5237 + attribute \src "libresoc.v:133204.3-133212.6" + process $proc$libresoc.v:133204$5221 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$5238 $1\src_l_r_src$next[2:0]$5239 - attribute \src "libresoc.v:132568.5-132568.29" + assign $0\src_l_r_src$next[2:0]$5222 $1\src_l_r_src$next[2:0]$5223 + attribute \src "libresoc.v:133205.5-133205.29" switch \initial - attribute \src "libresoc.v:132568.9-132568.17" + attribute \src "libresoc.v:133205.9-133205.17" case 1'1 case end @@ -209744,21 +209989,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$5239 3'111 + assign $1\src_l_r_src$next[2:0]$5223 3'111 case - assign $1\src_l_r_src$next[2:0]$5239 \reset_r + assign $1\src_l_r_src$next[2:0]$5223 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5238 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5222 end - attribute \src "libresoc.v:132576.3-132584.6" - process $proc$libresoc.v:132576$5240 + attribute \src "libresoc.v:133213.3-133221.6" + process $proc$libresoc.v:133213$5224 assign { } { } assign { } { } - assign $0\req_l_s_req$next[3:0]$5241 $1\req_l_s_req$next[3:0]$5242 - attribute \src "libresoc.v:132577.5-132577.29" + assign $0\req_l_s_req$next[3:0]$5225 $1\req_l_s_req$next[3:0]$5226 + attribute \src "libresoc.v:133214.5-133214.29" switch \initial - attribute \src "libresoc.v:132577.9-132577.17" + attribute \src "libresoc.v:133214.9-133214.17" case 1'1 case end @@ -209767,21 +210012,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[3:0]$5242 4'0000 + assign $1\req_l_s_req$next[3:0]$5226 4'0000 case - assign $1\req_l_s_req$next[3:0]$5242 \$66 + assign $1\req_l_s_req$next[3:0]$5226 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5241 + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5225 end - attribute \src "libresoc.v:132585.3-132593.6" - process $proc$libresoc.v:132585$5243 + attribute \src "libresoc.v:133222.3-133230.6" + process $proc$libresoc.v:133222$5227 assign { } { } assign { } { } - assign $0\req_l_r_req$next[3:0]$5244 $1\req_l_r_req$next[3:0]$5245 - attribute \src "libresoc.v:132586.5-132586.29" + assign $0\req_l_r_req$next[3:0]$5228 $1\req_l_r_req$next[3:0]$5229 + attribute \src "libresoc.v:133223.5-133223.29" switch \initial - attribute \src "libresoc.v:132586.9-132586.17" + attribute \src "libresoc.v:133223.9-133223.17" case 1'1 case end @@ -209790,15 +210035,15 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[3:0]$5245 4'1111 + assign $1\req_l_r_req$next[3:0]$5229 4'1111 case - assign $1\req_l_r_req$next[3:0]$5245 \$68 + assign $1\req_l_r_req$next[3:0]$5229 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5244 + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5228 end - attribute \src "libresoc.v:132594.3-132632.6" - process $proc$libresoc.v:132594$5246 + attribute \src "libresoc.v:133231.3-133269.6" + process $proc$libresoc.v:133231$5230 assign { } { } assign { } { } assign { } { } @@ -209835,33 +210080,33 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign $0\alu_div0_logical_op__data_len$next[3:0]$5247 $1\alu_div0_logical_op__data_len$next[3:0]$5265 - assign $0\alu_div0_logical_op__fn_unit$next[13:0]$5248 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 + assign $0\alu_div0_logical_op__data_len$next[3:0]$5231 $1\alu_div0_logical_op__data_len$next[3:0]$5249 + assign $0\alu_div0_logical_op__fn_unit$next[13:0]$5232 $1\alu_div0_logical_op__fn_unit$next[13:0]$5250 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__input_carry$next[1:0]$5251 $1\alu_div0_logical_op__input_carry$next[1:0]$5269 - assign $0\alu_div0_logical_op__insn$next[31:0]$5252 $1\alu_div0_logical_op__insn$next[31:0]$5270 - assign $0\alu_div0_logical_op__insn_type$next[6:0]$5253 $1\alu_div0_logical_op__insn_type$next[6:0]$5271 - assign $0\alu_div0_logical_op__invert_in$next[0:0]$5254 $1\alu_div0_logical_op__invert_in$next[0:0]$5272 - assign $0\alu_div0_logical_op__invert_out$next[0:0]$5255 $1\alu_div0_logical_op__invert_out$next[0:0]$5273 - assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5256 $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 - assign $0\alu_div0_logical_op__is_signed$next[0:0]$5257 $1\alu_div0_logical_op__is_signed$next[0:0]$5275 + assign $0\alu_div0_logical_op__input_carry$next[1:0]$5235 $1\alu_div0_logical_op__input_carry$next[1:0]$5253 + assign $0\alu_div0_logical_op__insn$next[31:0]$5236 $1\alu_div0_logical_op__insn$next[31:0]$5254 + assign $0\alu_div0_logical_op__insn_type$next[6:0]$5237 $1\alu_div0_logical_op__insn_type$next[6:0]$5255 + assign $0\alu_div0_logical_op__invert_in$next[0:0]$5238 $1\alu_div0_logical_op__invert_in$next[0:0]$5256 + assign $0\alu_div0_logical_op__invert_out$next[0:0]$5239 $1\alu_div0_logical_op__invert_out$next[0:0]$5257 + assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5240 $1\alu_div0_logical_op__is_32bit$next[0:0]$5258 + assign $0\alu_div0_logical_op__is_signed$next[0:0]$5241 $1\alu_div0_logical_op__is_signed$next[0:0]$5259 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__output_carry$next[0:0]$5260 $1\alu_div0_logical_op__output_carry$next[0:0]$5278 + assign $0\alu_div0_logical_op__output_carry$next[0:0]$5244 $1\alu_div0_logical_op__output_carry$next[0:0]$5262 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 - assign $0\alu_div0_logical_op__zero_a$next[0:0]$5264 $1\alu_div0_logical_op__zero_a$next[0:0]$5282 - assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 - assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 - assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5258 $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 - assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 - assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 - assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 - attribute \src "libresoc.v:132595.5-132595.29" + assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5247 $1\alu_div0_logical_op__write_cr0$next[0:0]$5265 + assign $0\alu_div0_logical_op__zero_a$next[0:0]$5248 $1\alu_div0_logical_op__zero_a$next[0:0]$5266 + assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5233 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5267 + assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5234 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 + assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5242 $2\alu_div0_logical_op__oe__oe$next[0:0]$5269 + assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5243 $2\alu_div0_logical_op__oe__ok$next[0:0]$5270 + assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5245 $2\alu_div0_logical_op__rc__ok$next[0:0]$5271 + assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5246 $2\alu_div0_logical_op__rc__rc$next[0:0]$5272 + attribute \src "libresoc.v:133232.5-133232.29" switch \initial - attribute \src "libresoc.v:132595.9-132595.17" + attribute \src "libresoc.v:133232.9-133232.17" case 1'1 case end @@ -209887,26 +210132,26 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_div0_logical_op__insn$next[31:0]$5270 $1\alu_div0_logical_op__data_len$next[3:0]$5265 $1\alu_div0_logical_op__is_signed$next[0:0]$5275 $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 $1\alu_div0_logical_op__output_carry$next[0:0]$5278 $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 $1\alu_div0_logical_op__invert_out$next[0:0]$5273 $1\alu_div0_logical_op__input_carry$next[1:0]$5269 $1\alu_div0_logical_op__zero_a$next[0:0]$5282 $1\alu_div0_logical_op__invert_in$next[0:0]$5272 $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 $1\alu_div0_logical_op__insn_type$next[6:0]$5271 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } + assign { $1\alu_div0_logical_op__insn$next[31:0]$5254 $1\alu_div0_logical_op__data_len$next[3:0]$5249 $1\alu_div0_logical_op__is_signed$next[0:0]$5259 $1\alu_div0_logical_op__is_32bit$next[0:0]$5258 $1\alu_div0_logical_op__output_carry$next[0:0]$5262 $1\alu_div0_logical_op__write_cr0$next[0:0]$5265 $1\alu_div0_logical_op__invert_out$next[0:0]$5257 $1\alu_div0_logical_op__input_carry$next[1:0]$5253 $1\alu_div0_logical_op__zero_a$next[0:0]$5266 $1\alu_div0_logical_op__invert_in$next[0:0]$5256 $1\alu_div0_logical_op__oe__ok$next[0:0]$5261 $1\alu_div0_logical_op__oe__oe$next[0:0]$5260 $1\alu_div0_logical_op__rc__ok$next[0:0]$5263 $1\alu_div0_logical_op__rc__rc$next[0:0]$5264 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5252 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5251 $1\alu_div0_logical_op__fn_unit$next[13:0]$5250 $1\alu_div0_logical_op__insn_type$next[6:0]$5255 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } case - assign $1\alu_div0_logical_op__data_len$next[3:0]$5265 \alu_div0_logical_op__data_len - assign $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 \alu_div0_logical_op__fn_unit - assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 \alu_div0_logical_op__imm_data__data - assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 \alu_div0_logical_op__imm_data__ok - assign $1\alu_div0_logical_op__input_carry$next[1:0]$5269 \alu_div0_logical_op__input_carry - assign $1\alu_div0_logical_op__insn$next[31:0]$5270 \alu_div0_logical_op__insn - assign $1\alu_div0_logical_op__insn_type$next[6:0]$5271 \alu_div0_logical_op__insn_type - assign $1\alu_div0_logical_op__invert_in$next[0:0]$5272 \alu_div0_logical_op__invert_in - assign $1\alu_div0_logical_op__invert_out$next[0:0]$5273 \alu_div0_logical_op__invert_out - assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 \alu_div0_logical_op__is_32bit - assign $1\alu_div0_logical_op__is_signed$next[0:0]$5275 \alu_div0_logical_op__is_signed - assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 \alu_div0_logical_op__oe__oe - assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 \alu_div0_logical_op__oe__ok - assign $1\alu_div0_logical_op__output_carry$next[0:0]$5278 \alu_div0_logical_op__output_carry - assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 \alu_div0_logical_op__rc__ok - assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 \alu_div0_logical_op__rc__rc - assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 \alu_div0_logical_op__write_cr0 - assign $1\alu_div0_logical_op__zero_a$next[0:0]$5282 \alu_div0_logical_op__zero_a + assign $1\alu_div0_logical_op__data_len$next[3:0]$5249 \alu_div0_logical_op__data_len + assign $1\alu_div0_logical_op__fn_unit$next[13:0]$5250 \alu_div0_logical_op__fn_unit + assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5251 \alu_div0_logical_op__imm_data__data + assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5252 \alu_div0_logical_op__imm_data__ok + assign $1\alu_div0_logical_op__input_carry$next[1:0]$5253 \alu_div0_logical_op__input_carry + assign $1\alu_div0_logical_op__insn$next[31:0]$5254 \alu_div0_logical_op__insn + assign $1\alu_div0_logical_op__insn_type$next[6:0]$5255 \alu_div0_logical_op__insn_type + assign $1\alu_div0_logical_op__invert_in$next[0:0]$5256 \alu_div0_logical_op__invert_in + assign $1\alu_div0_logical_op__invert_out$next[0:0]$5257 \alu_div0_logical_op__invert_out + assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5258 \alu_div0_logical_op__is_32bit + assign $1\alu_div0_logical_op__is_signed$next[0:0]$5259 \alu_div0_logical_op__is_signed + assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5260 \alu_div0_logical_op__oe__oe + assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5261 \alu_div0_logical_op__oe__ok + assign $1\alu_div0_logical_op__output_carry$next[0:0]$5262 \alu_div0_logical_op__output_carry + assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5263 \alu_div0_logical_op__rc__ok + assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5264 \alu_div0_logical_op__rc__rc + assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5265 \alu_div0_logical_op__write_cr0 + assign $1\alu_div0_logical_op__zero_a$next[0:0]$5266 \alu_div0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -209918,54 +210163,54 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 1'0 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 1'0 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 1'0 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 1'0 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 1'0 + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5267 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 1'0 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5272 1'0 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5271 1'0 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5269 1'0 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5270 1'0 case - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5267 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5251 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5252 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5269 $1\alu_div0_logical_op__oe__oe$next[0:0]$5260 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5270 $1\alu_div0_logical_op__oe__ok$next[0:0]$5261 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5271 $1\alu_div0_logical_op__rc__ok$next[0:0]$5263 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5272 $1\alu_div0_logical_op__rc__rc$next[0:0]$5264 end sync always - update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5247 - update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[13:0]$5248 - update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249 - update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250 - update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5251 - update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5252 - update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5253 - update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5254 - update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5255 - update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5256 - update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5257 - update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5258 - update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 - update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5260 - update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 - update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 - update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 - update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5264 + update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5231 + update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[13:0]$5232 + update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5233 + update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5234 + update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5235 + update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5236 + update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5237 + update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5238 + update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5239 + update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5240 + update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5241 + update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5242 + update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5243 + update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5244 + update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5245 + update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5246 + update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5247 + update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5248 end - attribute \src "libresoc.v:132633.3-132654.6" - process $proc$libresoc.v:132633$5289 + attribute \src "libresoc.v:133270.3-133291.6" + process $proc$libresoc.v:133270$5273 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$5290 $2\data_r0__o$next[63:0]$5294 + assign $0\data_r0__o$next[63:0]$5274 $2\data_r0__o$next[63:0]$5278 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$5291 $3\data_r0__o_ok$next[0:0]$5296 - attribute \src "libresoc.v:132634.5-132634.29" + assign $0\data_r0__o_ok$next[0:0]$5275 $3\data_r0__o_ok$next[0:0]$5280 + attribute \src "libresoc.v:133271.5-133271.29" switch \initial - attribute \src "libresoc.v:132634.9-132634.17" + attribute \src "libresoc.v:133271.9-133271.17" case 1'1 case end @@ -209975,10 +210220,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$5293 $1\data_r0__o$next[63:0]$5292 } { \o_ok \alu_div0_o } + assign { $1\data_r0__o_ok$next[0:0]$5277 $1\data_r0__o$next[63:0]$5276 } { \o_ok \alu_div0_o } case - assign $1\data_r0__o$next[63:0]$5292 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$5293 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$5276 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$5277 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -209986,38 +210231,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$5295 $2\data_r0__o$next[63:0]$5294 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$5279 $2\data_r0__o$next[63:0]$5278 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$5294 $1\data_r0__o$next[63:0]$5292 - assign $2\data_r0__o_ok$next[0:0]$5295 $1\data_r0__o_ok$next[0:0]$5293 + assign $2\data_r0__o$next[63:0]$5278 $1\data_r0__o$next[63:0]$5276 + assign $2\data_r0__o_ok$next[0:0]$5279 $1\data_r0__o_ok$next[0:0]$5277 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$5296 1'0 + assign $3\data_r0__o_ok$next[0:0]$5280 1'0 case - assign $3\data_r0__o_ok$next[0:0]$5296 $2\data_r0__o_ok$next[0:0]$5295 + assign $3\data_r0__o_ok$next[0:0]$5280 $2\data_r0__o_ok$next[0:0]$5279 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$5290 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5291 + update \data_r0__o$next $0\data_r0__o$next[63:0]$5274 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5275 end - attribute \src "libresoc.v:132655.3-132676.6" - process $proc$libresoc.v:132655$5297 + attribute \src "libresoc.v:133292.3-133313.6" + process $proc$libresoc.v:133292$5281 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$5298 $2\data_r1__cr_a$next[3:0]$5302 + assign $0\data_r1__cr_a$next[3:0]$5282 $2\data_r1__cr_a$next[3:0]$5286 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$5299 $3\data_r1__cr_a_ok$next[0:0]$5304 - attribute \src "libresoc.v:132656.5-132656.29" + assign $0\data_r1__cr_a_ok$next[0:0]$5283 $3\data_r1__cr_a_ok$next[0:0]$5288 + attribute \src "libresoc.v:133293.5-133293.29" switch \initial - attribute \src "libresoc.v:132656.9-132656.17" + attribute \src "libresoc.v:133293.9-133293.17" case 1'1 case end @@ -210027,10 +210272,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$5301 $1\data_r1__cr_a$next[3:0]$5300 } { \cr_a_ok \alu_div0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$5285 $1\data_r1__cr_a$next[3:0]$5284 } { \cr_a_ok \alu_div0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$5300 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$5301 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$5284 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$5285 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -210038,38 +210283,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$5303 $2\data_r1__cr_a$next[3:0]$5302 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$5287 $2\data_r1__cr_a$next[3:0]$5286 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$5302 $1\data_r1__cr_a$next[3:0]$5300 - assign $2\data_r1__cr_a_ok$next[0:0]$5303 $1\data_r1__cr_a_ok$next[0:0]$5301 + assign $2\data_r1__cr_a$next[3:0]$5286 $1\data_r1__cr_a$next[3:0]$5284 + assign $2\data_r1__cr_a_ok$next[0:0]$5287 $1\data_r1__cr_a_ok$next[0:0]$5285 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$5304 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$5288 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$5304 $2\data_r1__cr_a_ok$next[0:0]$5303 + assign $3\data_r1__cr_a_ok$next[0:0]$5288 $2\data_r1__cr_a_ok$next[0:0]$5287 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5298 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5299 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5282 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5283 end - attribute \src "libresoc.v:132677.3-132698.6" - process $proc$libresoc.v:132677$5305 + attribute \src "libresoc.v:133314.3-133335.6" + process $proc$libresoc.v:133314$5289 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$5306 $2\data_r2__xer_ov$next[1:0]$5310 + assign $0\data_r2__xer_ov$next[1:0]$5290 $2\data_r2__xer_ov$next[1:0]$5294 assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$5307 $3\data_r2__xer_ov_ok$next[0:0]$5312 - attribute \src "libresoc.v:132678.5-132678.29" + assign $0\data_r2__xer_ov_ok$next[0:0]$5291 $3\data_r2__xer_ov_ok$next[0:0]$5296 + attribute \src "libresoc.v:133315.5-133315.29" switch \initial - attribute \src "libresoc.v:132678.9-132678.17" + attribute \src "libresoc.v:133315.9-133315.17" case 1'1 case end @@ -210079,10 +210324,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$5309 $1\data_r2__xer_ov$next[1:0]$5308 } { \xer_ov_ok \alu_div0_xer_ov } + assign { $1\data_r2__xer_ov_ok$next[0:0]$5293 $1\data_r2__xer_ov$next[1:0]$5292 } { \xer_ov_ok \alu_div0_xer_ov } case - assign $1\data_r2__xer_ov$next[1:0]$5308 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$5309 \data_r2__xer_ov_ok + assign $1\data_r2__xer_ov$next[1:0]$5292 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$5293 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -210090,38 +210335,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$5311 $2\data_r2__xer_ov$next[1:0]$5310 } 3'000 + assign { $2\data_r2__xer_ov_ok$next[0:0]$5295 $2\data_r2__xer_ov$next[1:0]$5294 } 3'000 case - assign $2\data_r2__xer_ov$next[1:0]$5310 $1\data_r2__xer_ov$next[1:0]$5308 - assign $2\data_r2__xer_ov_ok$next[0:0]$5311 $1\data_r2__xer_ov_ok$next[0:0]$5309 + assign $2\data_r2__xer_ov$next[1:0]$5294 $1\data_r2__xer_ov$next[1:0]$5292 + assign $2\data_r2__xer_ov_ok$next[0:0]$5295 $1\data_r2__xer_ov_ok$next[0:0]$5293 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$5312 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$5296 1'0 case - assign $3\data_r2__xer_ov_ok$next[0:0]$5312 $2\data_r2__xer_ov_ok$next[0:0]$5311 + assign $3\data_r2__xer_ov_ok$next[0:0]$5296 $2\data_r2__xer_ov_ok$next[0:0]$5295 end sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5306 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5307 + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5290 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5291 end - attribute \src "libresoc.v:132699.3-132720.6" - process $proc$libresoc.v:132699$5313 + attribute \src "libresoc.v:133336.3-133357.6" + process $proc$libresoc.v:133336$5297 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$5314 $2\data_r3__xer_so$next[0:0]$5318 + assign $0\data_r3__xer_so$next[0:0]$5298 $2\data_r3__xer_so$next[0:0]$5302 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$5315 $3\data_r3__xer_so_ok$next[0:0]$5320 - attribute \src "libresoc.v:132700.5-132700.29" + assign $0\data_r3__xer_so_ok$next[0:0]$5299 $3\data_r3__xer_so_ok$next[0:0]$5304 + attribute \src "libresoc.v:133337.5-133337.29" switch \initial - attribute \src "libresoc.v:132700.9-132700.17" + attribute \src "libresoc.v:133337.9-133337.17" case 1'1 case end @@ -210131,10 +210376,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$5317 $1\data_r3__xer_so$next[0:0]$5316 } { \xer_so_ok \alu_div0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$5301 $1\data_r3__xer_so$next[0:0]$5300 } { \xer_so_ok \alu_div0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$5316 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$5317 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$5300 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$5301 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -210142,32 +210387,32 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$5319 $2\data_r3__xer_so$next[0:0]$5318 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$5303 $2\data_r3__xer_so$next[0:0]$5302 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$5318 $1\data_r3__xer_so$next[0:0]$5316 - assign $2\data_r3__xer_so_ok$next[0:0]$5319 $1\data_r3__xer_so_ok$next[0:0]$5317 + assign $2\data_r3__xer_so$next[0:0]$5302 $1\data_r3__xer_so$next[0:0]$5300 + assign $2\data_r3__xer_so_ok$next[0:0]$5303 $1\data_r3__xer_so_ok$next[0:0]$5301 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$5320 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$5304 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$5320 $2\data_r3__xer_so_ok$next[0:0]$5319 + assign $3\data_r3__xer_so_ok$next[0:0]$5304 $2\data_r3__xer_so_ok$next[0:0]$5303 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5314 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5315 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5298 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5299 end - attribute \src "libresoc.v:132721.3-132730.6" - process $proc$libresoc.v:132721$5321 + attribute \src "libresoc.v:133358.3-133367.6" + process $proc$libresoc.v:133358$5305 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$5322 $1\src_r0$next[63:0]$5323 - attribute \src "libresoc.v:132722.5-132722.29" + assign $0\src_r0$next[63:0]$5306 $1\src_r0$next[63:0]$5307 + attribute \src "libresoc.v:133359.5-133359.29" switch \initial - attribute \src "libresoc.v:132722.9-132722.17" + attribute \src "libresoc.v:133359.9-133359.17" case 1'1 case end @@ -210176,21 +210421,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$5323 \src_or_imm + assign $1\src_r0$next[63:0]$5307 \src_or_imm case - assign $1\src_r0$next[63:0]$5323 \src_r0 + assign $1\src_r0$next[63:0]$5307 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$5322 + update \src_r0$next $0\src_r0$next[63:0]$5306 end - attribute \src "libresoc.v:132731.3-132740.6" - process $proc$libresoc.v:132731$5324 + attribute \src "libresoc.v:133368.3-133377.6" + process $proc$libresoc.v:133368$5308 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$5325 $1\src_r1$next[63:0]$5326 - attribute \src "libresoc.v:132732.5-132732.29" + assign $0\src_r1$next[63:0]$5309 $1\src_r1$next[63:0]$5310 + attribute \src "libresoc.v:133369.5-133369.29" switch \initial - attribute \src "libresoc.v:132732.9-132732.17" + attribute \src "libresoc.v:133369.9-133369.17" case 1'1 case end @@ -210199,21 +210444,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$5326 \src_or_imm$85 + assign $1\src_r1$next[63:0]$5310 \src_or_imm$85 case - assign $1\src_r1$next[63:0]$5326 \src_r1 + assign $1\src_r1$next[63:0]$5310 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$5325 + update \src_r1$next $0\src_r1$next[63:0]$5309 end - attribute \src "libresoc.v:132741.3-132750.6" - process $proc$libresoc.v:132741$5327 + attribute \src "libresoc.v:133378.3-133387.6" + process $proc$libresoc.v:133378$5311 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$5328 $1\src_r2$next[0:0]$5329 - attribute \src "libresoc.v:132742.5-132742.29" + assign $0\src_r2$next[0:0]$5312 $1\src_r2$next[0:0]$5313 + attribute \src "libresoc.v:133379.5-133379.29" switch \initial - attribute \src "libresoc.v:132742.9-132742.17" + attribute \src "libresoc.v:133379.9-133379.17" case 1'1 case end @@ -210222,21 +210467,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$5329 \src3_i + assign $1\src_r2$next[0:0]$5313 \src3_i case - assign $1\src_r2$next[0:0]$5329 \src_r2 + assign $1\src_r2$next[0:0]$5313 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$5328 + update \src_r2$next $0\src_r2$next[0:0]$5312 end - attribute \src "libresoc.v:132751.3-132759.6" - process $proc$libresoc.v:132751$5330 + attribute \src "libresoc.v:133388.3-133396.6" + process $proc$libresoc.v:133388$5314 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$5331 $1\alui_l_r_alui$next[0:0]$5332 - attribute \src "libresoc.v:132752.5-132752.29" + assign $0\alui_l_r_alui$next[0:0]$5315 $1\alui_l_r_alui$next[0:0]$5316 + attribute \src "libresoc.v:133389.5-133389.29" switch \initial - attribute \src "libresoc.v:132752.9-132752.17" + attribute \src "libresoc.v:133389.9-133389.17" case 1'1 case end @@ -210245,21 +210490,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$5332 1'1 + assign $1\alui_l_r_alui$next[0:0]$5316 1'1 case - assign $1\alui_l_r_alui$next[0:0]$5332 \$94 + assign $1\alui_l_r_alui$next[0:0]$5316 \$94 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5331 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5315 end - attribute \src "libresoc.v:132760.3-132768.6" - process $proc$libresoc.v:132760$5333 + attribute \src "libresoc.v:133397.3-133405.6" + process $proc$libresoc.v:133397$5317 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$5334 $1\alu_l_r_alu$next[0:0]$5335 - attribute \src "libresoc.v:132761.5-132761.29" + assign $0\alu_l_r_alu$next[0:0]$5318 $1\alu_l_r_alu$next[0:0]$5319 + attribute \src "libresoc.v:133398.5-133398.29" switch \initial - attribute \src "libresoc.v:132761.9-132761.17" + attribute \src "libresoc.v:133398.9-133398.17" case 1'1 case end @@ -210268,21 +210513,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$5335 1'1 + assign $1\alu_l_r_alu$next[0:0]$5319 1'1 case - assign $1\alu_l_r_alu$next[0:0]$5335 \$96 + assign $1\alu_l_r_alu$next[0:0]$5319 \$96 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5334 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5318 end - attribute \src "libresoc.v:132769.3-132778.6" - process $proc$libresoc.v:132769$5336 + attribute \src "libresoc.v:133406.3-133415.6" + process $proc$libresoc.v:133406$5320 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:132770.5-132770.29" + attribute \src "libresoc.v:133407.5-133407.29" switch \initial - attribute \src "libresoc.v:132770.9-132770.17" + attribute \src "libresoc.v:133407.9-133407.17" case 1'1 case end @@ -210298,14 +210543,14 @@ module \div0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:132779.3-132788.6" - process $proc$libresoc.v:132779$5337 + attribute \src "libresoc.v:133416.3-133425.6" + process $proc$libresoc.v:133416$5321 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:132780.5-132780.29" + attribute \src "libresoc.v:133417.5-133417.29" switch \initial - attribute \src "libresoc.v:132780.9-132780.17" + attribute \src "libresoc.v:133417.9-133417.17" case 1'1 case end @@ -210321,14 +210566,14 @@ module \div0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:132789.3-132798.6" - process $proc$libresoc.v:132789$5338 + attribute \src "libresoc.v:133426.3-133435.6" + process $proc$libresoc.v:133426$5322 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:132790.5-132790.29" + attribute \src "libresoc.v:133427.5-133427.29" switch \initial - attribute \src "libresoc.v:132790.9-132790.17" + attribute \src "libresoc.v:133427.9-133427.17" case 1'1 case end @@ -210344,14 +210589,14 @@ module \div0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:132799.3-132808.6" - process $proc$libresoc.v:132799$5339 + attribute \src "libresoc.v:133436.3-133445.6" + process $proc$libresoc.v:133436$5323 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:132800.5-132800.29" + attribute \src "libresoc.v:133437.5-133437.29" switch \initial - attribute \src "libresoc.v:132800.9-132800.17" + attribute \src "libresoc.v:133437.9-133437.17" case 1'1 case end @@ -210367,14 +210612,14 @@ module \div0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:132809.3-132817.6" - process $proc$libresoc.v:132809$5340 + attribute \src "libresoc.v:133446.3-133454.6" + process $proc$libresoc.v:133446$5324 assign { } { } assign { } { } - assign $0\prev_wr_go$next[3:0]$5341 $1\prev_wr_go$next[3:0]$5342 - attribute \src "libresoc.v:132810.5-132810.29" + assign $0\prev_wr_go$next[3:0]$5325 $1\prev_wr_go$next[3:0]$5326 + attribute \src "libresoc.v:133447.5-133447.29" switch \initial - attribute \src "libresoc.v:132810.9-132810.17" + attribute \src "libresoc.v:133447.9-133447.17" case 1'1 case end @@ -210383,76 +210628,76 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[3:0]$5342 4'0000 - case - assign $1\prev_wr_go$next[3:0]$5342 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5341 - end - connect \$100 $not$libresoc.v:132258$5108_Y - connect \$102 $not$libresoc.v:132259$5109_Y - connect \$104 $and$libresoc.v:132260$5110_Y - connect \$106 $not$libresoc.v:132261$5111_Y - connect \$108 $and$libresoc.v:132262$5112_Y - connect \$10 $and$libresoc.v:132263$5113_Y - connect \$110 $and$libresoc.v:132264$5114_Y - connect \$112 $and$libresoc.v:132265$5115_Y - connect \$114 $and$libresoc.v:132266$5116_Y - connect \$116 $and$libresoc.v:132267$5117_Y - connect \$118 $and$libresoc.v:132268$5118_Y - connect \$120 $and$libresoc.v:132269$5119_Y - connect \$122 $and$libresoc.v:132270$5120_Y - connect \$124 $and$libresoc.v:132271$5121_Y - connect \$126 $and$libresoc.v:132272$5122_Y - connect \$128 $and$libresoc.v:132273$5123_Y - connect \$12 $not$libresoc.v:132274$5124_Y - connect \$14 $and$libresoc.v:132275$5125_Y - connect \$16 $not$libresoc.v:132276$5126_Y - connect \$18 $and$libresoc.v:132277$5127_Y - connect \$20 $and$libresoc.v:132278$5128_Y - connect \$24 $not$libresoc.v:132279$5129_Y - connect \$26 $and$libresoc.v:132280$5130_Y - connect \$23 $reduce_or$libresoc.v:132281$5131_Y - connect \$22 $not$libresoc.v:132282$5132_Y - connect \$2 $and$libresoc.v:132283$5133_Y - connect \$30 $and$libresoc.v:132284$5134_Y - connect \$32 $reduce_or$libresoc.v:132285$5135_Y - connect \$34 $reduce_or$libresoc.v:132286$5136_Y - connect \$36 $or$libresoc.v:132287$5137_Y - connect \$38 $not$libresoc.v:132288$5138_Y - connect \$40 $and$libresoc.v:132289$5139_Y - connect \$42 $and$libresoc.v:132290$5140_Y - connect \$44 $eq$libresoc.v:132291$5141_Y - connect \$46 $and$libresoc.v:132292$5142_Y - connect \$48 $eq$libresoc.v:132293$5143_Y - connect \$50 $and$libresoc.v:132294$5144_Y - connect \$52 $and$libresoc.v:132295$5145_Y - connect \$54 $and$libresoc.v:132296$5146_Y - connect \$56 $or$libresoc.v:132297$5147_Y - connect \$58 $or$libresoc.v:132298$5148_Y - connect \$5 $not$libresoc.v:132299$5149_Y - connect \$60 $or$libresoc.v:132300$5150_Y - connect \$62 $or$libresoc.v:132301$5151_Y - connect \$64 $and$libresoc.v:132302$5152_Y - connect \$66 $and$libresoc.v:132303$5153_Y - connect \$68 $or$libresoc.v:132304$5154_Y - connect \$70 $and$libresoc.v:132305$5155_Y - connect \$72 $and$libresoc.v:132306$5156_Y - connect \$74 $and$libresoc.v:132307$5157_Y - connect \$76 $and$libresoc.v:132308$5158_Y - connect \$78 $ternary$libresoc.v:132309$5159_Y - connect \$7 $or$libresoc.v:132310$5160_Y - connect \$80 $ternary$libresoc.v:132311$5161_Y - connect \$83 $ternary$libresoc.v:132312$5162_Y - connect \$86 $ternary$libresoc.v:132313$5163_Y - connect \$88 $ternary$libresoc.v:132314$5164_Y - connect \$4 $reduce_and$libresoc.v:132315$5165_Y - connect \$90 $ternary$libresoc.v:132316$5166_Y - connect \$92 $ternary$libresoc.v:132317$5167_Y - connect \$94 $and$libresoc.v:132318$5168_Y - connect \$96 $and$libresoc.v:132319$5169_Y - connect \$98 $and$libresoc.v:132320$5170_Y + assign $1\prev_wr_go$next[3:0]$5326 4'0000 + case + assign $1\prev_wr_go$next[3:0]$5326 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5325 + end + connect \$100 $not$libresoc.v:132895$5092_Y + connect \$102 $not$libresoc.v:132896$5093_Y + connect \$104 $and$libresoc.v:132897$5094_Y + connect \$106 $not$libresoc.v:132898$5095_Y + connect \$108 $and$libresoc.v:132899$5096_Y + connect \$10 $and$libresoc.v:132900$5097_Y + connect \$110 $and$libresoc.v:132901$5098_Y + connect \$112 $and$libresoc.v:132902$5099_Y + connect \$114 $and$libresoc.v:132903$5100_Y + connect \$116 $and$libresoc.v:132904$5101_Y + connect \$118 $and$libresoc.v:132905$5102_Y + connect \$120 $and$libresoc.v:132906$5103_Y + connect \$122 $and$libresoc.v:132907$5104_Y + connect \$124 $and$libresoc.v:132908$5105_Y + connect \$126 $and$libresoc.v:132909$5106_Y + connect \$128 $and$libresoc.v:132910$5107_Y + connect \$12 $not$libresoc.v:132911$5108_Y + connect \$14 $and$libresoc.v:132912$5109_Y + connect \$16 $not$libresoc.v:132913$5110_Y + connect \$18 $and$libresoc.v:132914$5111_Y + connect \$20 $and$libresoc.v:132915$5112_Y + connect \$24 $not$libresoc.v:132916$5113_Y + connect \$26 $and$libresoc.v:132917$5114_Y + connect \$23 $reduce_or$libresoc.v:132918$5115_Y + connect \$22 $not$libresoc.v:132919$5116_Y + connect \$2 $and$libresoc.v:132920$5117_Y + connect \$30 $and$libresoc.v:132921$5118_Y + connect \$32 $reduce_or$libresoc.v:132922$5119_Y + connect \$34 $reduce_or$libresoc.v:132923$5120_Y + connect \$36 $or$libresoc.v:132924$5121_Y + connect \$38 $not$libresoc.v:132925$5122_Y + connect \$40 $and$libresoc.v:132926$5123_Y + connect \$42 $and$libresoc.v:132927$5124_Y + connect \$44 $eq$libresoc.v:132928$5125_Y + connect \$46 $and$libresoc.v:132929$5126_Y + connect \$48 $eq$libresoc.v:132930$5127_Y + connect \$50 $and$libresoc.v:132931$5128_Y + connect \$52 $and$libresoc.v:132932$5129_Y + connect \$54 $and$libresoc.v:132933$5130_Y + connect \$56 $or$libresoc.v:132934$5131_Y + connect \$58 $or$libresoc.v:132935$5132_Y + connect \$5 $not$libresoc.v:132936$5133_Y + connect \$60 $or$libresoc.v:132937$5134_Y + connect \$62 $or$libresoc.v:132938$5135_Y + connect \$64 $and$libresoc.v:132939$5136_Y + connect \$66 $and$libresoc.v:132940$5137_Y + connect \$68 $or$libresoc.v:132941$5138_Y + connect \$70 $and$libresoc.v:132942$5139_Y + connect \$72 $and$libresoc.v:132943$5140_Y + connect \$74 $and$libresoc.v:132944$5141_Y + connect \$76 $and$libresoc.v:132945$5142_Y + connect \$78 $ternary$libresoc.v:132946$5143_Y + connect \$7 $or$libresoc.v:132947$5144_Y + connect \$80 $ternary$libresoc.v:132948$5145_Y + connect \$83 $ternary$libresoc.v:132949$5146_Y + connect \$86 $ternary$libresoc.v:132950$5147_Y + connect \$88 $ternary$libresoc.v:132951$5148_Y + connect \$4 $reduce_and$libresoc.v:132952$5149_Y + connect \$90 $ternary$libresoc.v:132953$5150_Y + connect \$92 $ternary$libresoc.v:132954$5151_Y + connect \$94 $and$libresoc.v:132955$5152_Y + connect \$96 $and$libresoc.v:132956$5153_Y + connect \$98 $and$libresoc.v:132957$5154_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$120 @@ -210486,7 +210731,7 @@ module \div0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:132854.1-132863.10" +attribute \src "libresoc.v:133491.1-133500.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" attribute \generator "nMigen" @@ -210500,37 +210745,37 @@ module \div_state_init connect \o_dividend_quotient \dividend connect \o_q_bits_known 7'0000000 end -attribute \src "libresoc.v:132867.1-132949.10" +attribute \src "libresoc.v:133504.1-133586.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" attribute \generator "nMigen" module \div_state_next - attribute \src "libresoc.v:132868.7-132868.20" + attribute \src "libresoc.v:133505.7-133505.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132933.3-132944.6" + attribute \src "libresoc.v:133570.3-133581.6" wire width 128 $0\o_dividend_quotient[127:0] - attribute \src "libresoc.v:132921.3-132932.6" + attribute \src "libresoc.v:133558.3-133569.6" wire width 7 $0\o_q_bits_known[6:0] - attribute \src "libresoc.v:132909.3-132920.6" + attribute \src "libresoc.v:133546.3-133557.6" wire width 128 $0\value[127:0] - attribute \src "libresoc.v:132933.3-132944.6" + attribute \src "libresoc.v:133570.3-133581.6" wire width 128 $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:132921.3-132932.6" + attribute \src "libresoc.v:133558.3-133569.6" wire width 7 $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:132909.3-132920.6" + attribute \src "libresoc.v:133546.3-133557.6" wire width 128 $1\value[127:0] - attribute \src "libresoc.v:132903.18-132903.106" - wire width 8 $add$libresoc.v:132903$5388_Y - attribute \src "libresoc.v:132904.18-132904.109" - wire $ge$libresoc.v:132904$5389_Y - attribute \src "libresoc.v:132908.17-132908.108" - wire $ge$libresoc.v:132908$5393_Y - attribute \src "libresoc.v:132907.17-132907.101" - wire $not$libresoc.v:132907$5392_Y - attribute \src "libresoc.v:132905.17-132905.101" - wire width 127 $sshl$libresoc.v:132905$5390_Y - attribute \src "libresoc.v:132906.17-132906.109" - wire width 129 $sub$libresoc.v:132906$5391_Y + attribute \src "libresoc.v:133540.18-133540.106" + wire width 8 $add$libresoc.v:133540$5372_Y + attribute \src "libresoc.v:133541.18-133541.109" + wire $ge$libresoc.v:133541$5373_Y + attribute \src "libresoc.v:133545.17-133545.108" + wire $ge$libresoc.v:133545$5377_Y + attribute \src "libresoc.v:133544.17-133544.101" + wire $not$libresoc.v:133544$5376_Y + attribute \src "libresoc.v:133542.17-133542.101" + wire width 127 $sshl$libresoc.v:133542$5374_Y + attribute \src "libresoc.v:133543.17-133543.109" + wire width 129 $sub$libresoc.v:133543$5375_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" wire width 129 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" @@ -210555,7 +210800,7 @@ module \div_state_next wire width 128 input 3 \i_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 input 2 \i_q_bits_known - attribute \src "libresoc.v:132868.7-132868.15" + attribute \src "libresoc.v:133505.7-133505.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" wire \next_quotient_bit @@ -210566,7 +210811,7 @@ module \div_state_next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" wire width 128 \value attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" - cell $add $add$libresoc.v:132903$5388 + cell $add $add$libresoc.v:133540$5372 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -210574,10 +210819,10 @@ module \div_state_next parameter \Y_WIDTH 8 connect \A \i_q_bits_known connect \B 1'1 - connect \Y $add$libresoc.v:132903$5388_Y + connect \Y $add$libresoc.v:133540$5372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:132904$5389 + cell $ge $ge$libresoc.v:133541$5373 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -210585,10 +210830,10 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $ge$libresoc.v:132904$5389_Y + connect \Y $ge$libresoc.v:133541$5373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:132908$5393 + cell $ge $ge$libresoc.v:133545$5377 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -210596,18 +210841,18 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $ge$libresoc.v:132908$5393_Y + connect \Y $ge$libresoc.v:133545$5377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" - cell $not $not$libresoc.v:132907$5392 + cell $not $not$libresoc.v:133544$5376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \difference [127] - connect \Y $not$libresoc.v:132907$5392_Y + connect \Y $not$libresoc.v:133544$5376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sshl $sshl$libresoc.v:132905$5390 + cell $sshl $sshl$libresoc.v:133542$5374 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -210615,10 +210860,10 @@ module \div_state_next parameter \Y_WIDTH 127 connect \A \divisor connect \B 6'111111 - connect \Y $sshl$libresoc.v:132905$5390_Y + connect \Y $sshl$libresoc.v:133542$5374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sub $sub$libresoc.v:132906$5391 + cell $sub $sub$libresoc.v:133543$5375 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -210626,23 +210871,23 @@ module \div_state_next parameter \Y_WIDTH 129 connect \A \i_dividend_quotient connect \B \$2 - connect \Y $sub$libresoc.v:132906$5391_Y + connect \Y $sub$libresoc.v:133543$5375_Y end - attribute \src "libresoc.v:132868.7-132868.20" - process $proc$libresoc.v:132868$5397 + attribute \src "libresoc.v:133505.7-133505.20" + process $proc$libresoc.v:133505$5381 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132909.3-132920.6" - process $proc$libresoc.v:132909$5394 + attribute \src "libresoc.v:133546.3-133557.6" + process $proc$libresoc.v:133546$5378 assign { } { } assign $0\value[127:0] $1\value[127:0] - attribute \src "libresoc.v:132910.5-132910.29" + attribute \src "libresoc.v:133547.5-133547.29" switch \initial - attribute \src "libresoc.v:132910.9-132910.17" + attribute \src "libresoc.v:133547.9-133547.17" case 1'1 case end @@ -210660,13 +210905,13 @@ module \div_state_next sync always update \value $0\value[127:0] end - attribute \src "libresoc.v:132921.3-132932.6" - process $proc$libresoc.v:132921$5395 + attribute \src "libresoc.v:133558.3-133569.6" + process $proc$libresoc.v:133558$5379 assign { } { } assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:132922.5-132922.29" + attribute \src "libresoc.v:133559.5-133559.29" switch \initial - attribute \src "libresoc.v:132922.9-132922.17" + attribute \src "libresoc.v:133559.9-133559.17" case 1'1 case end @@ -210684,13 +210929,13 @@ module \div_state_next sync always update \o_q_bits_known $0\o_q_bits_known[6:0] end - attribute \src "libresoc.v:132933.3-132944.6" - process $proc$libresoc.v:132933$5396 + attribute \src "libresoc.v:133570.3-133581.6" + process $proc$libresoc.v:133570$5380 assign { } { } assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:132934.5-132934.29" + attribute \src "libresoc.v:133571.5-133571.29" switch \initial - attribute \src "libresoc.v:132934.9-132934.17" + attribute \src "libresoc.v:133571.9-133571.17" case 1'1 case end @@ -210708,18 +210953,18 @@ module \div_state_next sync always update \o_dividend_quotient $0\o_dividend_quotient[127:0] end - connect \$11 $add$libresoc.v:132903$5388_Y - connect \$13 $ge$libresoc.v:132904$5389_Y - connect \$2 $sshl$libresoc.v:132905$5390_Y - connect \$4 $sub$libresoc.v:132906$5391_Y - connect \$6 $not$libresoc.v:132907$5392_Y - connect \$8 $ge$libresoc.v:132908$5393_Y + connect \$11 $add$libresoc.v:133540$5372_Y + connect \$13 $ge$libresoc.v:133541$5373_Y + connect \$2 $sshl$libresoc.v:133542$5374_Y + connect \$4 $sub$libresoc.v:133543$5375_Y + connect \$6 $not$libresoc.v:133544$5376_Y + connect \$8 $ge$libresoc.v:133545$5377_Y connect \$1 \$4 connect \$10 \$11 connect \next_quotient_bit \$6 connect \difference \$4 [127:0] end -attribute \src "libresoc.v:132953.1-133196.10" +attribute \src "libresoc.v:133590.1-133833.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" attribute \generator "nMigen" @@ -210967,102 +211212,96 @@ module \dummy connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:133200.1-133371.10" +attribute \src "libresoc.v:133837.1-133968.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fast" attribute \generator "nMigen" module \fast - attribute \src "libresoc.v:133295.3-133301.6" - wire width 3 $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 - attribute \src "libresoc.v:133295.3-133301.6" - wire width 64 $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 - attribute \src "libresoc.v:133295.3-133301.6" - wire width 64 $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 - attribute \src "libresoc.v:133295.3-133301.6" - wire width 3 $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 - attribute \src "libresoc.v:133295.3-133301.6" - wire width 64 $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 - attribute \src "libresoc.v:133295.3-133301.6" - wire width 64 $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 - attribute \src "libresoc.v:133295.3-133301.6" + attribute \src "libresoc.v:133910.3-133915.6" + wire width 3 $0$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5393 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $0$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5394 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $0$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5395 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 3 $0$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5396 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $0$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5397 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $0$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5398 + attribute \src "libresoc.v:133910.3-133915.6" wire width 3 $0\_0_[2:0] - attribute \src "libresoc.v:133295.3-133301.6" + attribute \src "libresoc.v:133910.3-133915.6" wire width 3 $0\_1_[2:0] - attribute \src "libresoc.v:133295.3-133301.6" - wire width 3 $0\_2_[2:0] - attribute \src "libresoc.v:133201.7-133201.20" + attribute \src "libresoc.v:133838.7-133838.20" wire $0\initial[0:0] - attribute \src "libresoc.v:133352.3-133361.6" + attribute \src "libresoc.v:133950.3-133959.6" wire width 64 $0\issue__data_o[63:0] - attribute \src "libresoc.v:133324.3-133332.6" - wire $0\ren_delay$10$next[0:0]$5428 - attribute \src "libresoc.v:133277.3-133278.43" - wire $0\ren_delay$10[0:0]$5411 - attribute \src "libresoc.v:133252.7-133252.28" - wire $0\ren_delay$10[0:0]$5448 - attribute \src "libresoc.v:133343.3-133351.6" - wire $0\ren_delay$11$next[0:0]$5432 - attribute \src "libresoc.v:133275.3-133276.43" - wire $0\ren_delay$11[0:0]$5409 - attribute \src "libresoc.v:133256.7-133256.28" - wire $0\ren_delay$11[0:0]$5450 - attribute \src "libresoc.v:133305.3-133313.6" - wire $0\ren_delay$next[0:0]$5424 - attribute \src "libresoc.v:133279.3-133280.35" + attribute \src "libresoc.v:133941.3-133949.6" + wire $0\ren_delay$8$next[0:0]$5415 + attribute \src "libresoc.v:133918.3-133919.41" + wire $0\ren_delay$8[0:0]$5408 + attribute \src "libresoc.v:133885.7-133885.27" + wire $0\ren_delay$8[0:0]$5429 + attribute \src "libresoc.v:133922.3-133930.6" + wire $0\ren_delay$next[0:0]$5411 + attribute \src "libresoc.v:133920.3-133921.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:133314.3-133323.6" + attribute \src "libresoc.v:133931.3-133940.6" wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:133333.3-133342.6" - wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:133352.3-133361.6" + attribute \src "libresoc.v:133910.3-133915.6" + wire width 3 $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 3 $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 + attribute \src "libresoc.v:133910.3-133915.6" + wire width 64 $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 + attribute \src "libresoc.v:133950.3-133959.6" wire width 64 $1\issue__data_o[63:0] - attribute \src "libresoc.v:133324.3-133332.6" - wire $1\ren_delay$10$next[0:0]$5429 - attribute \src "libresoc.v:133343.3-133351.6" - wire $1\ren_delay$11$next[0:0]$5433 - attribute \src "libresoc.v:133305.3-133313.6" - wire $1\ren_delay$next[0:0]$5425 - attribute \src "libresoc.v:133250.7-133250.23" + attribute \src "libresoc.v:133941.3-133949.6" + wire $1\ren_delay$8$next[0:0]$5416 + attribute \src "libresoc.v:133922.3-133930.6" + wire $1\ren_delay$next[0:0]$5412 + attribute \src "libresoc.v:133883.7-133883.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:133314.3-133323.6" + attribute \src "libresoc.v:133931.3-133940.6" wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:133333.3-133342.6" - wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:133302.26-133302.32" - wire width 64 $memrd$\memory$libresoc.v:133302$5420_DATA - attribute \src "libresoc.v:133303.30-133303.36" - wire width 64 $memrd$\memory$libresoc.v:133303$5421_DATA - attribute \src "libresoc.v:133304.30-133304.36" - wire width 64 $memrd$\memory$libresoc.v:133304$5422_DATA + attribute \src "libresoc.v:133916.26-133916.32" + wire width 64 $memrd$\memory$libresoc.v:133916$5405_DATA + attribute \src "libresoc.v:133917.30-133917.36" + wire width 64 $memrd$\memory$libresoc.v:133917$5406_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:133299$5406_ADDR + wire width 3 $memwr$\memory$libresoc.v:133913$5390_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:133299$5406_DATA + wire width 64 $memwr$\memory$libresoc.v:133913$5390_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:133299$5406_EN + wire width 64 $memwr$\memory$libresoc.v:133913$5390_EN attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:133300$5407_ADDR + wire width 3 $memwr$\memory$libresoc.v:133914$5391_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:133300$5407_DATA + wire width 64 $memwr$\memory$libresoc.v:133914$5391_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:133300$5407_EN - attribute \src "libresoc.v:133292.13-133292.16" + wire width 64 $memwr$\memory$libresoc.v:133914$5391_EN + attribute \src "libresoc.v:133908.13-133908.16" wire width 3 \_0_ - attribute \src "libresoc.v:133293.13-133293.16" + attribute \src "libresoc.v:133909.13-133909.16" wire width 3 \_1_ - attribute \src "libresoc.v:133294.13-133294.16" - wire width 3 \_2_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" - wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" + wire input 14 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 15 \dest1__addr + wire width 3 input 12 \dest1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 input 14 \dest1__data_i + wire width 64 input 11 \dest1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 16 \dest1__wen - attribute \src "libresoc.v:133201.7-133201.15" + wire input 13 \dest1__wen + attribute \src "libresoc.v:133838.7-133838.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \issue__addr @@ -211081,35 +211320,27 @@ module \fast attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 3 \memory_r_addr$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 3 \memory_r_addr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 3 \memory_w_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 3 \memory_w_addr$8 + wire width 3 \memory_w_addr$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 64 \memory_w_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data$9 + wire width 64 \memory_w_data$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire \memory_w_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire \memory_w_en$7 + wire \memory_w_en$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10 + wire \ren_delay$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$11$next + wire \ren_delay$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" @@ -211118,96 +211349,90 @@ module \fast wire width 64 output 8 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 12 \src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 11 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \src2__ren - attribute \src "libresoc.v:133281.14-133281.20" + attribute \src "libresoc.v:133897.14-133897.20" memory width 64 size 8 \memory - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5435 + attribute \src "libresoc.v:133899.5-133899.37" + cell $meminit $meminit$\memory$libresoc.v:133899$5418 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5435 + parameter \PRIORITY 5418 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5436 + attribute \src "libresoc.v:133900.5-133900.37" + cell $meminit $meminit$\memory$libresoc.v:133900$5419 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5436 + parameter \PRIORITY 5419 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5437 + attribute \src "libresoc.v:133901.5-133901.37" + cell $meminit $meminit$\memory$libresoc.v:133901$5420 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5437 + parameter \PRIORITY 5420 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5438 + attribute \src "libresoc.v:133902.5-133902.37" + cell $meminit $meminit$\memory$libresoc.v:133902$5421 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5438 + parameter \PRIORITY 5421 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5439 + attribute \src "libresoc.v:133903.5-133903.37" + cell $meminit $meminit$\memory$libresoc.v:133903$5422 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5439 + parameter \PRIORITY 5422 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5440 + attribute \src "libresoc.v:133904.5-133904.37" + cell $meminit $meminit$\memory$libresoc.v:133904$5423 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5440 + parameter \PRIORITY 5423 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5441 + attribute \src "libresoc.v:133905.5-133905.37" + cell $meminit $meminit$\memory$libresoc.v:133905$5424 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5441 + parameter \PRIORITY 5424 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5442 + attribute \src "libresoc.v:133906.5-133906.37" + cell $meminit $meminit$\memory$libresoc.v:133906$5425 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5442 + parameter \PRIORITY 5425 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:133302.26-133302.32" - cell $memrd $memrd$\memory$libresoc.v:133302$5420 + attribute \src "libresoc.v:133916.26-133916.32" + cell $memrd $memrd$\memory$libresoc.v:133916$5405 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -211216,11 +211441,11 @@ module \fast parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:133302$5420_DATA + connect \DATA $memrd$\memory$libresoc.v:133916$5405_DATA connect \EN 1'x end - attribute \src "libresoc.v:133303.30-133303.36" - cell $memrd $memrd$\memory$libresoc.v:133303$5421 + attribute \src "libresoc.v:133917.30-133917.36" + cell $memrd $memrd$\memory$libresoc.v:133917$5406 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -211229,108 +211454,44 @@ module \fast parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:133303$5421_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:133304.30-133304.36" - cell $memrd $memrd$\memory$libresoc.v:133304$5422 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_2_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:133304$5422_DATA + connect \DATA $memrd$\memory$libresoc.v:133917$5406_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5443 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 5443 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:133299$5406_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:133299$5406_DATA - connect \EN $memwr$\memory$libresoc.v:133299$5406_EN - end - attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5444 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 5444 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:133300$5407_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:133300$5407_DATA - connect \EN $memwr$\memory$libresoc.v:133300$5407_EN - end - attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5451 + process $proc$libresoc.v:0$5430 sync always sync init end - attribute \src "libresoc.v:133201.7-133201.20" - process $proc$libresoc.v:133201$5445 + attribute \src "libresoc.v:133838.7-133838.20" + process $proc$libresoc.v:133838$5426 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:133250.7-133250.23" - process $proc$libresoc.v:133250$5446 + attribute \src "libresoc.v:133883.7-133883.23" + process $proc$libresoc.v:133883$5427 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:133252.7-133252.28" - process $proc$libresoc.v:133252$5447 + attribute \src "libresoc.v:133885.7-133885.27" + process $proc$libresoc.v:133885$5428 assign { } { } - assign $0\ren_delay$10[0:0]$5448 1'0 + assign $0\ren_delay$8[0:0]$5429 1'0 sync always sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5448 + update \ren_delay$8 $0\ren_delay$8[0:0]$5429 end - attribute \src "libresoc.v:133256.7-133256.28" - process $proc$libresoc.v:133256$5449 + attribute \src "libresoc.v:133910.3-133915.6" + process $proc$libresoc.v:133910$5392 assign { } { } - assign $0\ren_delay$11[0:0]$5450 1'0 - sync always - sync init - update \ren_delay$11 $0\ren_delay$11[0:0]$5450 - end - attribute \src "libresoc.v:133275.3-133276.43" - process $proc$libresoc.v:133275$5408 assign { } { } - assign $0\ren_delay$11[0:0]$5409 \ren_delay$11$next - sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[0:0]$5409 - end - attribute \src "libresoc.v:133277.3-133278.43" - process $proc$libresoc.v:133277$5410 assign { } { } - assign $0\ren_delay$10[0:0]$5411 \ren_delay$10$next - sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5411 - end - attribute \src "libresoc.v:133279.3-133280.35" - process $proc$libresoc.v:133279$5412 assign { } { } - assign $0\ren_delay[0:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[0:0] - end - attribute \src "libresoc.v:133295.3-133301.6" - process $proc$libresoc.v:133295$5413 assign { } { } assign { } { } assign { } { } @@ -211340,52 +211501,81 @@ module \fast assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 3'xxx - assign $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 3'xxx - assign $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\_0_[2:0] \src1__addr - assign $0\_1_[2:0] \src2__addr - assign $0\_2_[2:0] \issue__addr - attribute \src "libresoc.v:133299.5-133299.62" - switch \issue__wen - attribute \src "libresoc.v:133299.9-133299.19" + assign { } { } + assign $0\_0_[2:0] \memory_r_addr + assign $0\_1_[2:0] \memory_r_addr$3 + assign $0$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5393 $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 + assign $0$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5394 $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 + assign $0$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5395 $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 + assign $0$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5396 $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 + assign $0$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5397 $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 + assign $0$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5398 $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 + attribute \src "libresoc.v:133913.5-133913.61" + switch \memory_w_en + attribute \src "libresoc.v:133913.9-133913.20" case 1'1 - assign $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 \issue__addr$1 - assign $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 \issue__data_i - assign $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 64'1111111111111111111111111111111111111111111111111111111111111111 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 \memory_w_addr + assign $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 \memory_w_data + assign $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 64'1111111111111111111111111111111111111111111111111111111111111111 case + assign $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 3'xxx + assign $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:133300.5-133300.58" - switch \dest1__wen - attribute \src "libresoc.v:133300.9-133300.19" + attribute \src "libresoc.v:133914.5-133914.73" + switch \memory_w_en$5 + attribute \src "libresoc.v:133914.9-133914.23" case 1'1 - assign $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 \dest1__addr - assign $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 64'1111111111111111111111111111111111111111111111111111111111111111 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 \memory_w_addr$6 + assign $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 \memory_w_data$7 + assign $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 64'1111111111111111111111111111111111111111111111111111111111111111 case + assign $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 3'xxx + assign $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 64'0000000000000000000000000000000000000000000000000000000000000000 end sync posedge \coresync_clk update \_0_ $0\_0_[2:0] update \_1_ $0\_1_[2:0] - update \_2_ $0\_2_[2:0] - update $memwr$\memory$libresoc.v:133299$5406_ADDR $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 - update $memwr$\memory$libresoc.v:133299$5406_DATA $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 - update $memwr$\memory$libresoc.v:133299$5406_EN $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 - update $memwr$\memory$libresoc.v:133300$5407_ADDR $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 - update $memwr$\memory$libresoc.v:133300$5407_DATA $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 - update $memwr$\memory$libresoc.v:133300$5407_EN $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 + update $memwr$\memory$libresoc.v:133913$5390_ADDR $0$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5393 + update $memwr$\memory$libresoc.v:133913$5390_DATA $0$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5394 + update $memwr$\memory$libresoc.v:133913$5390_EN $0$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5395 + update $memwr$\memory$libresoc.v:133914$5391_ADDR $0$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5396 + update $memwr$\memory$libresoc.v:133914$5391_DATA $0$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5397 + update $memwr$\memory$libresoc.v:133914$5391_EN $0$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5398 + attribute \src "libresoc.v:133913.22-133913.60" + memwr \memory $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 0' + attribute \src "libresoc.v:133914.26-133914.71" + memwr \memory $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 1'1 + end + attribute \src "libresoc.v:133918.3-133919.41" + process $proc$libresoc.v:133918$5407 + assign { } { } + assign $0\ren_delay$8[0:0]$5408 \ren_delay$8$next + sync posedge \coresync_clk + update \ren_delay$8 $0\ren_delay$8[0:0]$5408 + end + attribute \src "libresoc.v:133920.3-133921.35" + process $proc$libresoc.v:133920$5409 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:133305.3-133313.6" - process $proc$libresoc.v:133305$5423 + attribute \src "libresoc.v:133922.3-133930.6" + process $proc$libresoc.v:133922$5410 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$5424 $1\ren_delay$next[0:0]$5425 - attribute \src "libresoc.v:133306.5-133306.29" + assign $0\ren_delay$next[0:0]$5411 $1\ren_delay$next[0:0]$5412 + attribute \src "libresoc.v:133923.5-133923.29" switch \initial - attribute \src "libresoc.v:133306.9-133306.17" + attribute \src "libresoc.v:133923.9-133923.17" case 1'1 case end @@ -211394,21 +211584,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$5425 1'0 + assign $1\ren_delay$next[0:0]$5412 1'0 case - assign $1\ren_delay$next[0:0]$5425 \src1__ren + assign $1\ren_delay$next[0:0]$5412 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5424 + update \ren_delay$next $0\ren_delay$next[0:0]$5411 end - attribute \src "libresoc.v:133314.3-133323.6" - process $proc$libresoc.v:133314$5426 + attribute \src "libresoc.v:133931.3-133940.6" + process $proc$libresoc.v:133931$5413 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:133315.5-133315.29" + attribute \src "libresoc.v:133932.5-133932.29" switch \initial - attribute \src "libresoc.v:133315.9-133315.17" + attribute \src "libresoc.v:133932.9-133932.17" case 1'1 case end @@ -211424,14 +211614,14 @@ module \fast sync always update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:133324.3-133332.6" - process $proc$libresoc.v:133324$5427 + attribute \src "libresoc.v:133941.3-133949.6" + process $proc$libresoc.v:133941$5414 assign { } { } assign { } { } - assign $0\ren_delay$10$next[0:0]$5428 $1\ren_delay$10$next[0:0]$5429 - attribute \src "libresoc.v:133325.5-133325.29" + assign $0\ren_delay$8$next[0:0]$5415 $1\ren_delay$8$next[0:0]$5416 + attribute \src "libresoc.v:133942.5-133942.29" switch \initial - attribute \src "libresoc.v:133325.9-133325.17" + attribute \src "libresoc.v:133942.9-133942.17" case 1'1 case end @@ -211440,115 +211630,67 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$10$next[0:0]$5429 1'0 - case - assign $1\ren_delay$10$next[0:0]$5429 \src2__ren - end - sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5428 - end - attribute \src "libresoc.v:133333.3-133342.6" - process $proc$libresoc.v:133333$5430 - assign { } { } - assign { } { } - assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:133334.5-133334.29" - switch \initial - attribute \src "libresoc.v:133334.9-133334.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$10 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src2__data_o[63:0] \memory_r_data$4 + assign $1\ren_delay$8$next[0:0]$5416 1'0 case - assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ren_delay$8$next[0:0]$5416 \issue__ren end sync always - update \src2__data_o $0\src2__data_o[63:0] + update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5415 end - attribute \src "libresoc.v:133343.3-133351.6" - process $proc$libresoc.v:133343$5431 - assign { } { } - assign { } { } - assign $0\ren_delay$11$next[0:0]$5432 $1\ren_delay$11$next[0:0]$5433 - attribute \src "libresoc.v:133344.5-133344.29" - switch \initial - attribute \src "libresoc.v:133344.9-133344.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$11$next[0:0]$5433 1'0 - case - assign $1\ren_delay$11$next[0:0]$5433 \issue__ren - end - sync always - update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5432 - end - attribute \src "libresoc.v:133352.3-133361.6" - process $proc$libresoc.v:133352$5434 + attribute \src "libresoc.v:133950.3-133959.6" + process $proc$libresoc.v:133950$5417 assign { } { } assign { } { } assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] - attribute \src "libresoc.v:133353.5-133353.29" + attribute \src "libresoc.v:133951.5-133951.29" switch \initial - attribute \src "libresoc.v:133353.9-133353.17" + attribute \src "libresoc.v:133951.9-133951.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$11 + switch \ren_delay$8 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\issue__data_o[63:0] \memory_r_data$6 + assign $1\issue__data_o[63:0] \memory_r_data$4 case assign $1\issue__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \issue__data_o $0\issue__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:133302$5420_DATA - connect \memory_r_data$4 $memrd$\memory$libresoc.v:133303$5421_DATA - connect \memory_r_data$6 $memrd$\memory$libresoc.v:133304$5422_DATA - connect \memory_w_data$9 \issue__data_i - connect \memory_w_en$7 \issue__wen - connect \memory_w_addr$8 \issue__addr$1 + connect \memory_r_data $memrd$\memory$libresoc.v:133916$5405_DATA + connect \memory_r_data$4 $memrd$\memory$libresoc.v:133917$5406_DATA + connect \memory_w_data$7 \issue__data_i + connect \memory_w_en$5 \issue__wen + connect \memory_w_addr$6 \issue__addr$1 connect \memory_w_data \dest1__data_i connect \memory_w_en \dest1__wen connect \memory_w_addr \dest1__addr - connect \memory_r_addr$5 \issue__addr - connect \memory_r_addr$3 \src2__addr + connect \memory_r_addr$3 \issue__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:133375.1-135325.10" +attribute \src "libresoc.v:133972.1-135922.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus" attribute \generator "nMigen" module \fus - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 330 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 257 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 258 \cr_a_ok$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 259 \cr_a_ok$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 260 \cr_a_ok$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 261 \cr_a_ok$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 262 \cr_a_ok$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 3 \cu_ad__go_i @@ -211603,15 +211745,15 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 169 \cu_rd__go_i$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 172 \cu_rd__go_i$38 + wire width 3 input 172 \cu_rd__go_i$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 175 \cu_rd__go_i$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 178 \cu_rd__go_i$44 + wire width 5 input 178 \cu_rd__go_i$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 181 \cu_rd__go_i$47 + wire width 3 input 181 \cu_rd__go_i$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 184 \cu_rd__go_i$50 + wire width 6 input 190 \cu_rd__go_i$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 209 \cu_rd__go_i$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" @@ -211623,15 +211765,15 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 168 \cu_rd__rel_o$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 171 \cu_rd__rel_o$37 + wire width 3 output 171 \cu_rd__rel_o$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 174 \cu_rd__rel_o$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 177 \cu_rd__rel_o$43 + wire width 5 output 177 \cu_rd__rel_o$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 180 \cu_rd__rel_o$46 + wire width 3 output 180 \cu_rd__rel_o$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 183 \cu_rd__rel_o$49 + wire width 6 output 189 \cu_rd__rel_o$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 208 \cu_rd__rel_o$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" @@ -211768,23 +211910,23 @@ module \fus wire width 64 output 308 \dest5_o$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 273 \dest6_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 254 \ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 291 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 294 \fast1_ok$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 295 \fast1_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 296 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 297 \fast2_ok$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 255 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 96 output 315 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 316 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire input 325 \ldst_port0_addr_ok_o @@ -211812,37 +211954,37 @@ module \fus wire output 312 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire output 313 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 326 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 327 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 328 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 329 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 307 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 303 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 304 \nia_ok$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 253 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 219 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 222 \o_ok$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 225 \o_ok$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 228 \o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 231 \o_ok$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 234 \o_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 237 \o_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 240 \o_ok$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 22 \oper_i_alu_alu0__data_len @@ -213011,52 +213153,52 @@ module \fus wire input 153 \oper_i_ldst_ldst0__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 144 \oper_i_ldst_ldst0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 309 \spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 161 \src1_i + wire width 64 input 185 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 164 \src1_i$30 + wire width 64 input 186 \src1_i$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 167 \src1_i$33 + wire width 64 input 187 \src1_i$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 170 \src1_i$36 + wire width 64 input 188 \src1_i$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 173 \src1_i$39 + wire width 64 input 191 \src1_i$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 176 \src1_i$42 + wire width 64 input 192 \src1_i$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 179 \src1_i$45 + wire width 64 input 193 \src1_i$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 182 \src1_i$48 + wire width 64 input 194 \src1_i$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 185 \src1_i$51 + wire width 64 input 195 \src1_i$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 213 \src1_i$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 186 \src2_i + wire width 64 input 161 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 187 \src2_i$52 + wire width 64 input 164 \src2_i$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 188 \src2_i$53 + wire width 64 input 167 \src2_i$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 189 \src2_i$54 + wire width 64 input 170 \src2_i$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 190 \src2_i$55 + wire width 64 input 173 \src2_i$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 191 \src2_i$56 + wire width 64 input 176 \src2_i$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 192 \src2_i$57 + wire width 64 input 179 \src2_i$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 193 \src2_i$58 + wire width 64 input 182 \src2_i$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 216 \src2_i$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 218 \src2_i$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 194 \src3_i + wire width 64 input 183 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 195 \src3_i$59 + wire width 64 input 184 \src3_i$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 196 \src3_i$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" @@ -213093,30 +213235,30 @@ module \fus wire width 2 input 203 \src6_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 input 212 \src6_i$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 269 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 270 \xer_ca_ok$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 271 \xer_ca_ok$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 275 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 276 \xer_ov_ok$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 277 \xer_ov_ok$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 278 \xer_ov_ok$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 283 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 284 \xer_so_ok$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 285 \xer_so_ok$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 286 \xer_so_ok$131 attribute \module_not_derived 1 - attribute \src "libresoc.v:134957.8-134999.4" + attribute \src "libresoc.v:135554.8-135596.4" cell \alu0 \alu0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213161,7 +213303,7 @@ module \fus connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:135000.11-135027.4" + attribute \src "libresoc.v:135597.11-135624.4" cell \branch0 \branch0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213191,7 +213333,7 @@ module \fus connect \src3_i \src3_i$71 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135028.7-135053.4" + attribute \src "libresoc.v:135625.7-135650.4" cell \cr0 \cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213211,23 +213353,23 @@ module \fus connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type - connect \src1_i \src1_i$30 - connect \src2_i \src2_i$52 + connect \src1_i \src1_i$50 + connect \src2_i \src2_i$30 connect \src3_i \src3_i$67 connect \src4_i \src4_i$68 connect \src5_i \src5_i$72 connect \src6_i \src6_i$73 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135054.8-135093.4" + attribute \src "libresoc.v:135651.8-135690.4" cell \div0 \div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a_ok \cr_a_ok$112 connect \cu_busy_o \cu_busy_o$17 connect \cu_issue_i \cu_issue_i$16 - connect \cu_rd__go_i \cu_rd__go_i$41 - connect \cu_rd__rel_o \cu_rd__rel_o$40 + connect \cu_rd__go_i \cu_rd__go_i$38 + connect \cu_rd__rel_o \cu_rd__rel_o$37 connect \cu_rdmaskn_i \cu_rdmaskn_i$18 connect \cu_wr__go_i \cu_wr__go_i$94 connect \cu_wr__rel_o \cu_wr__rel_o$93 @@ -213254,14 +213396,14 @@ module \fus connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0 connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a - connect \src1_i \src1_i$42 - connect \src2_i \src2_i$55 + connect \src1_i \src1_i$56 + connect \src2_i \src2_i$39 connect \src3_i \src3_i$62 connect \xer_ov_ok \xer_ov_ok$125 connect \xer_so_ok \xer_so_ok$130 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135094.9-135148.4" + attribute \src "libresoc.v:135691.9-135745.4" cell \ldst0 \ldst0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213269,8 +213411,8 @@ module \fus connect \cu_ad__rel_o \cu_ad__rel_o connect \cu_busy_o \cu_busy_o$26 connect \cu_issue_i \cu_issue_i$25 - connect \cu_rd__go_i \cu_rd__go_i$50 - connect \cu_rd__rel_o \cu_rd__rel_o$49 + connect \cu_rd__go_i \cu_rd__go_i$47 + connect \cu_rd__rel_o \cu_rd__rel_o$46 connect \cu_rdmaskn_i \cu_rdmaskn_i$27 connect \cu_st__go_i \cu_st__go_i connect \cu_st__rel_o \cu_st__rel_o @@ -213313,12 +213455,12 @@ module \fus connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a - connect \src1_i \src1_i$51 - connect \src2_i \src2_i$58 - connect \src3_i \src3_i$59 + connect \src1_i \src1_i$59 + connect \src2_i \src2_i$48 + connect \src3_i \src3_i$49 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135149.12-135184.4" + attribute \src "libresoc.v:135746.12-135781.4" cell \logical0 \logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213351,20 +213493,20 @@ module \fus connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0 connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a - connect \src1_i \src1_i$36 - connect \src2_i \src2_i$54 + connect \src1_i \src1_i$52 + connect \src2_i \src2_i$36 connect \src3_i \src3_i$61 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135185.8-135218.4" + attribute \src "libresoc.v:135782.8-135815.4" cell \mul0 \mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a_ok \cr_a_ok$113 connect \cu_busy_o \cu_busy_o$20 connect \cu_issue_i \cu_issue_i$19 - connect \cu_rd__go_i \cu_rd__go_i$44 - connect \cu_rd__rel_o \cu_rd__rel_o$43 + connect \cu_rd__go_i \cu_rd__go_i$41 + connect \cu_rd__rel_o \cu_rd__rel_o$40 connect \cu_rdmaskn_i \cu_rdmaskn_i$21 connect \cu_wr__go_i \cu_wr__go_i$97 connect \cu_wr__rel_o \cu_wr__rel_o$96 @@ -213385,22 +213527,22 @@ module \fus connect \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__ok connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 - connect \src1_i \src1_i$45 - connect \src2_i \src2_i$56 + connect \src1_i \src1_i$57 + connect \src2_i \src2_i$42 connect \src3_i \src3_i$63 connect \xer_ov_ok \xer_ov_ok$126 connect \xer_so_ok \xer_so_ok$131 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135219.13-135257.4" + attribute \src "libresoc.v:135816.13-135854.4" cell \shiftrot0 \shiftrot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a_ok \cr_a_ok$114 connect \cu_busy_o \cu_busy_o$23 connect \cu_issue_i \cu_issue_i$22 - connect \cu_rd__go_i \cu_rd__go_i$47 - connect \cu_rd__rel_o \cu_rd__rel_o$46 + connect \cu_rd__go_i \cu_rd__go_i$44 + connect \cu_rd__rel_o \cu_rd__rel_o$43 connect \cu_rdmaskn_i \cu_rdmaskn_i$24 connect \cu_wr__go_i \cu_wr__go_i$100 connect \cu_wr__rel_o \cu_wr__rel_o$99 @@ -213425,22 +213567,22 @@ module \fus connect \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__ok connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc connect \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__write_cr0 - connect \src1_i \src1_i$48 - connect \src2_i \src2_i$57 + connect \src1_i \src1_i$58 + connect \src2_i \src2_i$45 connect \src3_i \src3_i connect \src4_i \src4_i$64 connect \src5_i \src5_i connect \xer_ca_ok \xer_ca_ok$121 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135258.8-135290.4" + attribute \src "libresoc.v:135855.8-135887.4" cell \spr0 \spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cu_busy_o \cu_busy_o$14 connect \cu_issue_i \cu_issue_i$13 - connect \cu_rd__go_i \cu_rd__go_i$38 - connect \cu_rd__rel_o \cu_rd__rel_o$37 + connect \cu_rd__go_i \cu_rd__go_i$54 + connect \cu_rd__rel_o \cu_rd__rel_o$53 connect \cu_rdmaskn_i \cu_rdmaskn_i$15 connect \cu_wr__go_i \cu_wr__go_i$91 connect \cu_wr__rel_o \cu_wr__rel_o$90 @@ -213457,7 +213599,7 @@ module \fus connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit connect \spr1_ok \spr1_ok - connect \src1_i \src1_i$39 + connect \src1_i \src1_i$55 connect \src2_i \src2_i$79 connect \src3_i \src3_i$76 connect \src4_i \src4_i @@ -213468,7 +213610,7 @@ module \fus connect \xer_so_ok \xer_so_ok$129 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135291.9-135324.4" + attribute \src "libresoc.v:135888.9-135921.4" cell \trap0 \trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213498,43 +213640,43 @@ module \fus connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype - connect \src1_i \src1_i$33 - connect \src2_i \src2_i$53 + connect \src1_i \src1_i$51 + connect \src2_i \src2_i$33 connect \src3_i \src3_i$75 connect \src4_i \src4_i$78 end end -attribute \src "libresoc.v:135329.1-135387.10" +attribute \src "libresoc.v:135926.1-135984.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" attribute \generator "nMigen" module \idx_l - attribute \src "libresoc.v:135330.7-135330.20" + attribute \src "libresoc.v:135927.7-135927.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135375.3-135383.6" - wire $0\q_int$next[0:0]$5462 - attribute \src "libresoc.v:135373.3-135374.27" + attribute \src "libresoc.v:135972.3-135980.6" + wire $0\q_int$next[0:0]$5441 + attribute \src "libresoc.v:135970.3-135971.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:135375.3-135383.6" - wire $1\q_int$next[0:0]$5463 - attribute \src "libresoc.v:135354.7-135354.19" + attribute \src "libresoc.v:135972.3-135980.6" + wire $1\q_int$next[0:0]$5442 + attribute \src "libresoc.v:135951.7-135951.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:135365.17-135365.96" - wire $and$libresoc.v:135365$5452_Y - attribute \src "libresoc.v:135370.17-135370.96" - wire $and$libresoc.v:135370$5457_Y - attribute \src "libresoc.v:135367.18-135367.95" - wire $not$libresoc.v:135367$5454_Y - attribute \src "libresoc.v:135369.17-135369.94" - wire $not$libresoc.v:135369$5456_Y - attribute \src "libresoc.v:135372.17-135372.94" - wire $not$libresoc.v:135372$5459_Y - attribute \src "libresoc.v:135366.18-135366.100" - wire $or$libresoc.v:135366$5453_Y - attribute \src "libresoc.v:135368.18-135368.101" - wire $or$libresoc.v:135368$5455_Y - attribute \src "libresoc.v:135371.17-135371.99" - wire $or$libresoc.v:135371$5458_Y + attribute \src "libresoc.v:135962.17-135962.96" + wire $and$libresoc.v:135962$5431_Y + attribute \src "libresoc.v:135967.17-135967.96" + wire $and$libresoc.v:135967$5436_Y + attribute \src "libresoc.v:135964.18-135964.95" + wire $not$libresoc.v:135964$5433_Y + attribute \src "libresoc.v:135966.17-135966.94" + wire $not$libresoc.v:135966$5435_Y + attribute \src "libresoc.v:135969.17-135969.94" + wire $not$libresoc.v:135969$5438_Y + attribute \src "libresoc.v:135963.18-135963.100" + wire $or$libresoc.v:135963$5432_Y + attribute \src "libresoc.v:135965.18-135965.101" + wire $or$libresoc.v:135965$5434_Y + attribute \src "libresoc.v:135968.17-135968.99" + wire $or$libresoc.v:135968$5437_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -213551,11 +213693,11 @@ module \idx_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:135330.7-135330.15" + attribute \src "libresoc.v:135927.7-135927.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_idx_l @@ -213572,7 +213714,7 @@ module \idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:135365$5452 + cell $and $and$libresoc.v:135962$5431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213580,10 +213722,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:135365$5452_Y + connect \Y $and$libresoc.v:135962$5431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:135370$5457 + cell $and $and$libresoc.v:135967$5436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213591,34 +213733,34 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:135370$5457_Y + connect \Y $and$libresoc.v:135967$5436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:135367$5454 + cell $not $not$libresoc.v:135964$5433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_idx_l - connect \Y $not$libresoc.v:135367$5454_Y + connect \Y $not$libresoc.v:135964$5433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:135369$5456 + cell $not $not$libresoc.v:135966$5435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:135369$5456_Y + connect \Y $not$libresoc.v:135966$5435_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:135372$5459 + cell $not $not$libresoc.v:135969$5438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:135372$5459_Y + connect \Y $not$libresoc.v:135969$5438_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:135366$5453 + cell $or $or$libresoc.v:135963$5432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213626,10 +213768,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_idx_l - connect \Y $or$libresoc.v:135366$5453_Y + connect \Y $or$libresoc.v:135963$5432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:135368$5455 + cell $or $or$libresoc.v:135965$5434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213637,10 +213779,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_idx_l connect \B \q_int - connect \Y $or$libresoc.v:135368$5455_Y + connect \Y $or$libresoc.v:135965$5434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:135371$5458 + cell $or $or$libresoc.v:135968$5437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213648,39 +213790,39 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_idx_l - connect \Y $or$libresoc.v:135371$5458_Y + connect \Y $or$libresoc.v:135968$5437_Y end - attribute \src "libresoc.v:135330.7-135330.20" - process $proc$libresoc.v:135330$5464 + attribute \src "libresoc.v:135927.7-135927.20" + process $proc$libresoc.v:135927$5443 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135354.7-135354.19" - process $proc$libresoc.v:135354$5465 + attribute \src "libresoc.v:135951.7-135951.19" + process $proc$libresoc.v:135951$5444 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:135373.3-135374.27" - process $proc$libresoc.v:135373$5460 + attribute \src "libresoc.v:135970.3-135971.27" + process $proc$libresoc.v:135970$5439 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:135375.3-135383.6" - process $proc$libresoc.v:135375$5461 + attribute \src "libresoc.v:135972.3-135980.6" + process $proc$libresoc.v:135972$5440 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$5462 $1\q_int$next[0:0]$5463 - attribute \src "libresoc.v:135376.5-135376.29" + assign $0\q_int$next[0:0]$5441 $1\q_int$next[0:0]$5442 + attribute \src "libresoc.v:135973.5-135973.29" switch \initial - attribute \src "libresoc.v:135376.9-135376.17" + attribute \src "libresoc.v:135973.9-135973.17" case 1'1 case end @@ -213689,192 +213831,192 @@ module \idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$5463 1'0 + assign $1\q_int$next[0:0]$5442 1'0 case - assign $1\q_int$next[0:0]$5463 \$5 + assign $1\q_int$next[0:0]$5442 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$5462 + update \q_int$next $0\q_int$next[0:0]$5441 end - connect \$9 $and$libresoc.v:135365$5452_Y - connect \$11 $or$libresoc.v:135366$5453_Y - connect \$13 $not$libresoc.v:135367$5454_Y - connect \$15 $or$libresoc.v:135368$5455_Y - connect \$1 $not$libresoc.v:135369$5456_Y - connect \$3 $and$libresoc.v:135370$5457_Y - connect \$5 $or$libresoc.v:135371$5458_Y - connect \$7 $not$libresoc.v:135372$5459_Y + connect \$9 $and$libresoc.v:135962$5431_Y + connect \$11 $or$libresoc.v:135963$5432_Y + connect \$13 $not$libresoc.v:135964$5433_Y + connect \$15 $or$libresoc.v:135965$5434_Y + connect \$1 $not$libresoc.v:135966$5435_Y + connect \$3 $and$libresoc.v:135967$5436_Y + connect \$5 $or$libresoc.v:135968$5437_Y + connect \$7 $not$libresoc.v:135969$5438_Y connect \qlq_idx_l \$15 connect \qn_idx_l \$13 connect \q_idx_l \$11 end -attribute \src "libresoc.v:135391.1-135770.10" +attribute \src "libresoc.v:135988.1-136367.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.imem" attribute \generator "nMigen" module \imem - attribute \src "libresoc.v:135722.3-135731.6" + attribute \src "libresoc.v:136319.3-136328.6" wire $0\a_busy_o[0:0] - attribute \src "libresoc.v:135702.3-135721.6" - wire width 45 $0\f_badaddr_o$next[44:0]$5534 - attribute \src "libresoc.v:135533.3-135534.39" + attribute \src "libresoc.v:136299.3-136318.6" + wire width 45 $0\f_badaddr_o$next[44:0]$5513 + attribute \src "libresoc.v:136130.3-136131.39" wire width 45 $0\f_badaddr_o[44:0] - attribute \src "libresoc.v:135732.3-135749.6" + attribute \src "libresoc.v:136329.3-136346.6" wire $0\f_busy_o[0:0] - attribute \src "libresoc.v:135679.3-135701.6" - wire $0\f_fetch_err_o$next[0:0]$5529 - attribute \src "libresoc.v:135535.3-135536.43" + attribute \src "libresoc.v:136276.3-136298.6" + wire $0\f_fetch_err_o$next[0:0]$5508 + attribute \src "libresoc.v:136132.3-136133.43" wire $0\f_fetch_err_o[0:0] - attribute \src "libresoc.v:135750.3-135767.6" + attribute \src "libresoc.v:136347.3-136364.6" wire width 64 $0\f_instr_o[63:0] - attribute \src "libresoc.v:135656.3-135678.6" - wire width 45 $0\ibus__adr$next[44:0]$5524 - attribute \src "libresoc.v:135537.3-135538.35" + attribute \src "libresoc.v:136253.3-136275.6" + wire width 45 $0\ibus__adr$next[44:0]$5503 + attribute \src "libresoc.v:136134.3-136135.35" wire width 45 $0\ibus__adr[44:0] - attribute \src "libresoc.v:135547.3-135574.6" - wire $0\ibus__cyc$next[0:0]$5500 - attribute \src "libresoc.v:135545.3-135546.35" + attribute \src "libresoc.v:136144.3-136171.6" + wire $0\ibus__cyc$next[0:0]$5479 + attribute \src "libresoc.v:136142.3-136143.35" wire $0\ibus__cyc[0:0] - attribute \src "libresoc.v:135603.3-135630.6" - wire width 8 $0\ibus__sel$next[7:0]$5512 - attribute \src "libresoc.v:135541.3-135542.35" + attribute \src "libresoc.v:136200.3-136227.6" + wire width 8 $0\ibus__sel$next[7:0]$5491 + attribute \src "libresoc.v:136138.3-136139.35" wire width 8 $0\ibus__sel[7:0] - attribute \src "libresoc.v:135575.3-135602.6" - wire $0\ibus__stb$next[0:0]$5506 - attribute \src "libresoc.v:135543.3-135544.35" + attribute \src "libresoc.v:136172.3-136199.6" + wire $0\ibus__stb$next[0:0]$5485 + attribute \src "libresoc.v:136140.3-136141.35" wire $0\ibus__stb[0:0] - attribute \src "libresoc.v:135631.3-135655.6" - wire width 64 $0\ibus_rdata$next[63:0]$5518 - attribute \src "libresoc.v:135539.3-135540.37" + attribute \src "libresoc.v:136228.3-136252.6" + wire width 64 $0\ibus_rdata$next[63:0]$5497 + attribute \src "libresoc.v:136136.3-136137.37" wire width 64 $0\ibus_rdata[63:0] - attribute \src "libresoc.v:135392.7-135392.20" + attribute \src "libresoc.v:135989.7-135989.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135722.3-135731.6" + attribute \src "libresoc.v:136319.3-136328.6" wire $1\a_busy_o[0:0] - attribute \src "libresoc.v:135702.3-135721.6" - wire width 45 $1\f_badaddr_o$next[44:0]$5535 - attribute \src "libresoc.v:135456.14-135456.44" + attribute \src "libresoc.v:136299.3-136318.6" + wire width 45 $1\f_badaddr_o$next[44:0]$5514 + attribute \src "libresoc.v:136053.14-136053.44" wire width 45 $1\f_badaddr_o[44:0] - attribute \src "libresoc.v:135732.3-135749.6" + attribute \src "libresoc.v:136329.3-136346.6" wire $1\f_busy_o[0:0] - attribute \src "libresoc.v:135679.3-135701.6" - wire $1\f_fetch_err_o$next[0:0]$5530 - attribute \src "libresoc.v:135463.7-135463.27" + attribute \src "libresoc.v:136276.3-136298.6" + wire $1\f_fetch_err_o$next[0:0]$5509 + attribute \src "libresoc.v:136060.7-136060.27" wire $1\f_fetch_err_o[0:0] - attribute \src "libresoc.v:135750.3-135767.6" + attribute \src "libresoc.v:136347.3-136364.6" wire width 64 $1\f_instr_o[63:0] - attribute \src "libresoc.v:135656.3-135678.6" - wire width 45 $1\ibus__adr$next[44:0]$5525 - attribute \src "libresoc.v:135477.14-135477.42" + attribute \src "libresoc.v:136253.3-136275.6" + wire width 45 $1\ibus__adr$next[44:0]$5504 + attribute \src "libresoc.v:136074.14-136074.42" wire width 45 $1\ibus__adr[44:0] - attribute \src "libresoc.v:135547.3-135574.6" - wire $1\ibus__cyc$next[0:0]$5501 - attribute \src "libresoc.v:135482.7-135482.23" + attribute \src "libresoc.v:136144.3-136171.6" + wire $1\ibus__cyc$next[0:0]$5480 + attribute \src "libresoc.v:136079.7-136079.23" wire $1\ibus__cyc[0:0] - attribute \src "libresoc.v:135603.3-135630.6" - wire width 8 $1\ibus__sel$next[7:0]$5513 - attribute \src "libresoc.v:135491.13-135491.30" + attribute \src "libresoc.v:136200.3-136227.6" + wire width 8 $1\ibus__sel$next[7:0]$5492 + attribute \src "libresoc.v:136088.13-136088.30" wire width 8 $1\ibus__sel[7:0] - attribute \src "libresoc.v:135575.3-135602.6" - wire $1\ibus__stb$next[0:0]$5507 - attribute \src "libresoc.v:135496.7-135496.23" + attribute \src "libresoc.v:136172.3-136199.6" + wire $1\ibus__stb$next[0:0]$5486 + attribute \src "libresoc.v:136093.7-136093.23" wire $1\ibus__stb[0:0] - attribute \src "libresoc.v:135631.3-135655.6" - wire width 64 $1\ibus_rdata$next[63:0]$5519 - attribute \src "libresoc.v:135500.14-135500.47" + attribute \src "libresoc.v:136228.3-136252.6" + wire width 64 $1\ibus_rdata$next[63:0]$5498 + attribute \src "libresoc.v:136097.14-136097.47" wire width 64 $1\ibus_rdata[63:0] - attribute \src "libresoc.v:135702.3-135721.6" - wire width 45 $2\f_badaddr_o$next[44:0]$5536 - attribute \src "libresoc.v:135732.3-135749.6" + attribute \src "libresoc.v:136299.3-136318.6" + wire width 45 $2\f_badaddr_o$next[44:0]$5515 + attribute \src "libresoc.v:136329.3-136346.6" wire $2\f_busy_o[0:0] - attribute \src "libresoc.v:135679.3-135701.6" - wire $2\f_fetch_err_o$next[0:0]$5531 - attribute \src "libresoc.v:135750.3-135767.6" + attribute \src "libresoc.v:136276.3-136298.6" + wire $2\f_fetch_err_o$next[0:0]$5510 + attribute \src "libresoc.v:136347.3-136364.6" wire width 64 $2\f_instr_o[63:0] - attribute \src "libresoc.v:135656.3-135678.6" - wire width 45 $2\ibus__adr$next[44:0]$5526 - attribute \src "libresoc.v:135547.3-135574.6" - wire $2\ibus__cyc$next[0:0]$5502 - attribute \src "libresoc.v:135603.3-135630.6" - wire width 8 $2\ibus__sel$next[7:0]$5514 - attribute \src "libresoc.v:135575.3-135602.6" - wire $2\ibus__stb$next[0:0]$5508 - attribute \src "libresoc.v:135631.3-135655.6" - wire width 64 $2\ibus_rdata$next[63:0]$5520 - attribute \src "libresoc.v:135702.3-135721.6" - wire width 45 $3\f_badaddr_o$next[44:0]$5537 - attribute \src "libresoc.v:135679.3-135701.6" - wire $3\f_fetch_err_o$next[0:0]$5532 - attribute \src "libresoc.v:135656.3-135678.6" - wire width 45 $3\ibus__adr$next[44:0]$5527 - attribute \src "libresoc.v:135547.3-135574.6" - wire $3\ibus__cyc$next[0:0]$5503 - attribute \src "libresoc.v:135603.3-135630.6" - wire width 8 $3\ibus__sel$next[7:0]$5515 - attribute \src "libresoc.v:135575.3-135602.6" - wire $3\ibus__stb$next[0:0]$5509 - attribute \src "libresoc.v:135631.3-135655.6" - wire width 64 $3\ibus_rdata$next[63:0]$5521 - attribute \src "libresoc.v:135547.3-135574.6" - wire $4\ibus__cyc$next[0:0]$5504 - attribute \src "libresoc.v:135603.3-135630.6" - wire width 8 $4\ibus__sel$next[7:0]$5516 - attribute \src "libresoc.v:135575.3-135602.6" - wire $4\ibus__stb$next[0:0]$5510 - attribute \src "libresoc.v:135631.3-135655.6" - wire width 64 $4\ibus_rdata$next[63:0]$5522 - attribute \src "libresoc.v:135509.18-135509.110" - wire $and$libresoc.v:135509$5468_Y - attribute \src "libresoc.v:135515.18-135515.110" - wire $and$libresoc.v:135515$5474_Y - attribute \src "libresoc.v:135520.18-135520.110" - wire $and$libresoc.v:135520$5479_Y - attribute \src "libresoc.v:135523.17-135523.108" - wire $and$libresoc.v:135523$5482_Y - attribute \src "libresoc.v:135526.18-135526.110" - wire $and$libresoc.v:135526$5485_Y - attribute \src "libresoc.v:135527.18-135527.115" - wire $and$libresoc.v:135527$5486_Y - attribute \src "libresoc.v:135529.18-135529.115" - wire $and$libresoc.v:135529$5488_Y - attribute \src "libresoc.v:135508.18-135508.105" - wire $not$libresoc.v:135508$5467_Y - attribute \src "libresoc.v:135511.18-135511.105" - wire $not$libresoc.v:135511$5470_Y - attribute \src "libresoc.v:135512.17-135512.104" - wire $not$libresoc.v:135512$5471_Y - attribute \src "libresoc.v:135514.18-135514.105" - wire $not$libresoc.v:135514$5473_Y - attribute \src "libresoc.v:135517.18-135517.105" - wire $not$libresoc.v:135517$5476_Y - attribute \src "libresoc.v:135519.18-135519.105" - wire $not$libresoc.v:135519$5478_Y - attribute \src "libresoc.v:135522.18-135522.105" - wire $not$libresoc.v:135522$5481_Y - attribute \src "libresoc.v:135525.18-135525.105" - wire $not$libresoc.v:135525$5484_Y - attribute \src "libresoc.v:135528.18-135528.105" - wire $not$libresoc.v:135528$5487_Y - attribute \src "libresoc.v:135530.18-135530.105" - wire $not$libresoc.v:135530$5489_Y - attribute \src "libresoc.v:135532.17-135532.104" - wire $not$libresoc.v:135532$5491_Y - attribute \src "libresoc.v:135507.17-135507.103" - wire $or$libresoc.v:135507$5466_Y - attribute \src "libresoc.v:135510.18-135510.115" - wire $or$libresoc.v:135510$5469_Y - attribute \src "libresoc.v:135513.18-135513.106" - wire $or$libresoc.v:135513$5472_Y - attribute \src "libresoc.v:135516.18-135516.115" - wire $or$libresoc.v:135516$5475_Y - attribute \src "libresoc.v:135518.18-135518.106" - wire $or$libresoc.v:135518$5477_Y - attribute \src "libresoc.v:135521.18-135521.115" - wire $or$libresoc.v:135521$5480_Y - attribute \src "libresoc.v:135524.18-135524.106" - wire $or$libresoc.v:135524$5483_Y - attribute \src "libresoc.v:135531.17-135531.114" - wire $or$libresoc.v:135531$5490_Y + attribute \src "libresoc.v:136253.3-136275.6" + wire width 45 $2\ibus__adr$next[44:0]$5505 + attribute \src "libresoc.v:136144.3-136171.6" + wire $2\ibus__cyc$next[0:0]$5481 + attribute \src "libresoc.v:136200.3-136227.6" + wire width 8 $2\ibus__sel$next[7:0]$5493 + attribute \src "libresoc.v:136172.3-136199.6" + wire $2\ibus__stb$next[0:0]$5487 + attribute \src "libresoc.v:136228.3-136252.6" + wire width 64 $2\ibus_rdata$next[63:0]$5499 + attribute \src "libresoc.v:136299.3-136318.6" + wire width 45 $3\f_badaddr_o$next[44:0]$5516 + attribute \src "libresoc.v:136276.3-136298.6" + wire $3\f_fetch_err_o$next[0:0]$5511 + attribute \src "libresoc.v:136253.3-136275.6" + wire width 45 $3\ibus__adr$next[44:0]$5506 + attribute \src "libresoc.v:136144.3-136171.6" + wire $3\ibus__cyc$next[0:0]$5482 + attribute \src "libresoc.v:136200.3-136227.6" + wire width 8 $3\ibus__sel$next[7:0]$5494 + attribute \src "libresoc.v:136172.3-136199.6" + wire $3\ibus__stb$next[0:0]$5488 + attribute \src "libresoc.v:136228.3-136252.6" + wire width 64 $3\ibus_rdata$next[63:0]$5500 + attribute \src "libresoc.v:136144.3-136171.6" + wire $4\ibus__cyc$next[0:0]$5483 + attribute \src "libresoc.v:136200.3-136227.6" + wire width 8 $4\ibus__sel$next[7:0]$5495 + attribute \src "libresoc.v:136172.3-136199.6" + wire $4\ibus__stb$next[0:0]$5489 + attribute \src "libresoc.v:136228.3-136252.6" + wire width 64 $4\ibus_rdata$next[63:0]$5501 + attribute \src "libresoc.v:136106.18-136106.110" + wire $and$libresoc.v:136106$5447_Y + attribute \src "libresoc.v:136112.18-136112.110" + wire $and$libresoc.v:136112$5453_Y + attribute \src "libresoc.v:136117.18-136117.110" + wire $and$libresoc.v:136117$5458_Y + attribute \src "libresoc.v:136120.17-136120.108" + wire $and$libresoc.v:136120$5461_Y + attribute \src "libresoc.v:136123.18-136123.110" + wire $and$libresoc.v:136123$5464_Y + attribute \src "libresoc.v:136124.18-136124.115" + wire $and$libresoc.v:136124$5465_Y + attribute \src "libresoc.v:136126.18-136126.115" + wire $and$libresoc.v:136126$5467_Y + attribute \src "libresoc.v:136105.18-136105.105" + wire $not$libresoc.v:136105$5446_Y + attribute \src "libresoc.v:136108.18-136108.105" + wire $not$libresoc.v:136108$5449_Y + attribute \src "libresoc.v:136109.17-136109.104" + wire $not$libresoc.v:136109$5450_Y + attribute \src "libresoc.v:136111.18-136111.105" + wire $not$libresoc.v:136111$5452_Y + attribute \src "libresoc.v:136114.18-136114.105" + wire $not$libresoc.v:136114$5455_Y + attribute \src "libresoc.v:136116.18-136116.105" + wire $not$libresoc.v:136116$5457_Y + attribute \src "libresoc.v:136119.18-136119.105" + wire $not$libresoc.v:136119$5460_Y + attribute \src "libresoc.v:136122.18-136122.105" + wire $not$libresoc.v:136122$5463_Y + attribute \src "libresoc.v:136125.18-136125.105" + wire $not$libresoc.v:136125$5466_Y + attribute \src "libresoc.v:136127.18-136127.105" + wire $not$libresoc.v:136127$5468_Y + attribute \src "libresoc.v:136129.17-136129.104" + wire $not$libresoc.v:136129$5470_Y + attribute \src "libresoc.v:136104.17-136104.103" + wire $or$libresoc.v:136104$5445_Y + attribute \src "libresoc.v:136107.18-136107.115" + wire $or$libresoc.v:136107$5448_Y + attribute \src "libresoc.v:136110.18-136110.106" + wire $or$libresoc.v:136110$5451_Y + attribute \src "libresoc.v:136113.18-136113.115" + wire $or$libresoc.v:136113$5454_Y + attribute \src "libresoc.v:136115.18-136115.106" + wire $or$libresoc.v:136115$5456_Y + attribute \src "libresoc.v:136118.18-136118.115" + wire $or$libresoc.v:136118$5459_Y + attribute \src "libresoc.v:136121.18-136121.106" + wire $or$libresoc.v:136121$5462_Y + attribute \src "libresoc.v:136128.17-136128.114" + wire $or$libresoc.v:136128$5469_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" @@ -213935,7 +214077,7 @@ module \imem wire \a_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" wire input 3 \a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 15 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" wire width 45 \f_badaddr_o @@ -213979,14 +214121,14 @@ module \imem wire width 64 \ibus_rdata attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" wire width 64 \ibus_rdata$next - attribute \src "libresoc.v:135392.7-135392.15" + attribute \src "libresoc.v:135989.7-135989.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire input 7 \wb_icache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:135509$5468 + cell $and $and$libresoc.v:136106$5447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213994,10 +214136,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$11 - connect \Y $and$libresoc.v:135509$5468_Y + connect \Y $and$libresoc.v:136106$5447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:135515$5474 + cell $and $and$libresoc.v:136112$5453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214005,10 +214147,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$21 - connect \Y $and$libresoc.v:135515$5474_Y + connect \Y $and$libresoc.v:136112$5453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:135520$5479 + cell $and $and$libresoc.v:136117$5458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214016,10 +214158,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$31 - connect \Y $and$libresoc.v:135520$5479_Y + connect \Y $and$libresoc.v:136117$5458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:135523$5482 + cell $and $and$libresoc.v:136120$5461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214027,10 +214169,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$1 - connect \Y $and$libresoc.v:135523$5482_Y + connect \Y $and$libresoc.v:136120$5461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:135526$5485 + cell $and $and$libresoc.v:136123$5464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214038,10 +214180,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$41 - connect \Y $and$libresoc.v:135526$5485_Y + connect \Y $and$libresoc.v:136123$5464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:135527$5486 + cell $and $and$libresoc.v:136124$5465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214049,10 +214191,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:135527$5486_Y + connect \Y $and$libresoc.v:136124$5465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:135529$5488 + cell $and $and$libresoc.v:136126$5467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214060,98 +214202,98 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:135529$5488_Y + connect \Y $and$libresoc.v:136126$5467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:135508$5467 + cell $not $not$libresoc.v:136105$5446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:135508$5467_Y + connect \Y $not$libresoc.v:136105$5446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:135511$5470 + cell $not $not$libresoc.v:136108$5449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:135511$5470_Y + connect \Y $not$libresoc.v:136108$5449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:135512$5471 + cell $not $not$libresoc.v:136109$5450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:135512$5471_Y + connect \Y $not$libresoc.v:136109$5450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:135514$5473 + cell $not $not$libresoc.v:136111$5452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:135514$5473_Y + connect \Y $not$libresoc.v:136111$5452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:135517$5476 + cell $not $not$libresoc.v:136114$5455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:135517$5476_Y + connect \Y $not$libresoc.v:136114$5455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:135519$5478 + cell $not $not$libresoc.v:136116$5457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:135519$5478_Y + connect \Y $not$libresoc.v:136116$5457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:135522$5481 + cell $not $not$libresoc.v:136119$5460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:135522$5481_Y + connect \Y $not$libresoc.v:136119$5460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:135525$5484 + cell $not $not$libresoc.v:136122$5463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:135525$5484_Y + connect \Y $not$libresoc.v:136122$5463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:135528$5487 + cell $not $not$libresoc.v:136125$5466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:135528$5487_Y + connect \Y $not$libresoc.v:136125$5466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:135530$5489 + cell $not $not$libresoc.v:136127$5468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:135530$5489_Y + connect \Y $not$libresoc.v:136127$5468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:135532$5491 + cell $not $not$libresoc.v:136129$5470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:135532$5491_Y + connect \Y $not$libresoc.v:136129$5470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135507$5466 + cell $or $or$libresoc.v:136104$5445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214159,10 +214301,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $or$libresoc.v:135507$5466_Y + connect \Y $or$libresoc.v:136104$5445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135510$5469 + cell $or $or$libresoc.v:136107$5448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214170,10 +214312,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:135510$5469_Y + connect \Y $or$libresoc.v:136107$5448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135513$5472 + cell $or $or$libresoc.v:136110$5451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214181,10 +214323,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$15 connect \B \$17 - connect \Y $or$libresoc.v:135513$5472_Y + connect \Y $or$libresoc.v:136110$5451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135516$5475 + cell $or $or$libresoc.v:136113$5454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214192,10 +214334,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:135516$5475_Y + connect \Y $or$libresoc.v:136113$5454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135518$5477 + cell $or $or$libresoc.v:136115$5456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214203,10 +214345,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$25 connect \B \$27 - connect \Y $or$libresoc.v:135518$5477_Y + connect \Y $or$libresoc.v:136115$5456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135521$5480 + cell $or $or$libresoc.v:136118$5459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214214,10 +214356,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:135521$5480_Y + connect \Y $or$libresoc.v:136118$5459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135524$5483 + cell $or $or$libresoc.v:136121$5462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214225,10 +214367,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$35 connect \B \$37 - connect \Y $or$libresoc.v:135524$5483_Y + connect \Y $or$libresoc.v:136121$5462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135531$5490 + cell $or $or$libresoc.v:136128$5469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214236,130 +214378,130 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:135531$5490_Y + connect \Y $or$libresoc.v:136128$5469_Y end - attribute \src "libresoc.v:135392.7-135392.20" - process $proc$libresoc.v:135392$5541 + attribute \src "libresoc.v:135989.7-135989.20" + process $proc$libresoc.v:135989$5520 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135456.14-135456.44" - process $proc$libresoc.v:135456$5542 + attribute \src "libresoc.v:136053.14-136053.44" + process $proc$libresoc.v:136053$5521 assign { } { } assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \f_badaddr_o $1\f_badaddr_o[44:0] end - attribute \src "libresoc.v:135463.7-135463.27" - process $proc$libresoc.v:135463$5543 + attribute \src "libresoc.v:136060.7-136060.27" + process $proc$libresoc.v:136060$5522 assign { } { } assign $1\f_fetch_err_o[0:0] 1'0 sync always sync init update \f_fetch_err_o $1\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:135477.14-135477.42" - process $proc$libresoc.v:135477$5544 + attribute \src "libresoc.v:136074.14-136074.42" + process $proc$libresoc.v:136074$5523 assign { } { } assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \ibus__adr $1\ibus__adr[44:0] end - attribute \src "libresoc.v:135482.7-135482.23" - process $proc$libresoc.v:135482$5545 + attribute \src "libresoc.v:136079.7-136079.23" + process $proc$libresoc.v:136079$5524 assign { } { } assign $1\ibus__cyc[0:0] 1'0 sync always sync init update \ibus__cyc $1\ibus__cyc[0:0] end - attribute \src "libresoc.v:135491.13-135491.30" - process $proc$libresoc.v:135491$5546 + attribute \src "libresoc.v:136088.13-136088.30" + process $proc$libresoc.v:136088$5525 assign { } { } assign $1\ibus__sel[7:0] 8'00000000 sync always sync init update \ibus__sel $1\ibus__sel[7:0] end - attribute \src "libresoc.v:135496.7-135496.23" - process $proc$libresoc.v:135496$5547 + attribute \src "libresoc.v:136093.7-136093.23" + process $proc$libresoc.v:136093$5526 assign { } { } assign $1\ibus__stb[0:0] 1'0 sync always sync init update \ibus__stb $1\ibus__stb[0:0] end - attribute \src "libresoc.v:135500.14-135500.47" - process $proc$libresoc.v:135500$5548 + attribute \src "libresoc.v:136097.14-136097.47" + process $proc$libresoc.v:136097$5527 assign { } { } assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ibus_rdata $1\ibus_rdata[63:0] end - attribute \src "libresoc.v:135533.3-135534.39" - process $proc$libresoc.v:135533$5492 + attribute \src "libresoc.v:136130.3-136131.39" + process $proc$libresoc.v:136130$5471 assign { } { } assign $0\f_badaddr_o[44:0] \f_badaddr_o$next sync posedge \clk update \f_badaddr_o $0\f_badaddr_o[44:0] end - attribute \src "libresoc.v:135535.3-135536.43" - process $proc$libresoc.v:135535$5493 + attribute \src "libresoc.v:136132.3-136133.43" + process $proc$libresoc.v:136132$5472 assign { } { } assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next sync posedge \clk update \f_fetch_err_o $0\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:135537.3-135538.35" - process $proc$libresoc.v:135537$5494 + attribute \src "libresoc.v:136134.3-136135.35" + process $proc$libresoc.v:136134$5473 assign { } { } assign $0\ibus__adr[44:0] \ibus__adr$next sync posedge \clk update \ibus__adr $0\ibus__adr[44:0] end - attribute \src "libresoc.v:135539.3-135540.37" - process $proc$libresoc.v:135539$5495 + attribute \src "libresoc.v:136136.3-136137.37" + process $proc$libresoc.v:136136$5474 assign { } { } assign $0\ibus_rdata[63:0] \ibus_rdata$next sync posedge \clk update \ibus_rdata $0\ibus_rdata[63:0] end - attribute \src "libresoc.v:135541.3-135542.35" - process $proc$libresoc.v:135541$5496 + attribute \src "libresoc.v:136138.3-136139.35" + process $proc$libresoc.v:136138$5475 assign { } { } assign $0\ibus__sel[7:0] \ibus__sel$next sync posedge \clk update \ibus__sel $0\ibus__sel[7:0] end - attribute \src "libresoc.v:135543.3-135544.35" - process $proc$libresoc.v:135543$5497 + attribute \src "libresoc.v:136140.3-136141.35" + process $proc$libresoc.v:136140$5476 assign { } { } assign $0\ibus__stb[0:0] \ibus__stb$next sync posedge \clk update \ibus__stb $0\ibus__stb[0:0] end - attribute \src "libresoc.v:135545.3-135546.35" - process $proc$libresoc.v:135545$5498 + attribute \src "libresoc.v:136142.3-136143.35" + process $proc$libresoc.v:136142$5477 assign { } { } assign $0\ibus__cyc[0:0] \ibus__cyc$next sync posedge \clk update \ibus__cyc $0\ibus__cyc[0:0] end - attribute \src "libresoc.v:135547.3-135574.6" - process $proc$libresoc.v:135547$5499 + attribute \src "libresoc.v:136144.3-136171.6" + process $proc$libresoc.v:136144$5478 assign { } { } assign { } { } assign { } { } - assign $0\ibus__cyc$next[0:0]$5500 $4\ibus__cyc$next[0:0]$5504 - attribute \src "libresoc.v:135548.5-135548.29" + assign $0\ibus__cyc$next[0:0]$5479 $4\ibus__cyc$next[0:0]$5483 + attribute \src "libresoc.v:136145.5-136145.29" switch \initial - attribute \src "libresoc.v:135548.9-135548.17" + attribute \src "libresoc.v:136145.9-136145.17" case 1'1 case end @@ -214368,53 +214510,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__cyc$next[0:0]$5501 $2\ibus__cyc$next[0:0]$5502 + assign $1\ibus__cyc$next[0:0]$5480 $2\ibus__cyc$next[0:0]$5481 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$3 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__cyc$next[0:0]$5502 $3\ibus__cyc$next[0:0]$5503 + assign $2\ibus__cyc$next[0:0]$5481 $3\ibus__cyc$next[0:0]$5482 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__cyc$next[0:0]$5503 1'0 + assign $3\ibus__cyc$next[0:0]$5482 1'0 case - assign $3\ibus__cyc$next[0:0]$5503 \ibus__cyc + assign $3\ibus__cyc$next[0:0]$5482 \ibus__cyc end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__cyc$next[0:0]$5502 1'1 + assign $2\ibus__cyc$next[0:0]$5481 1'1 case - assign $2\ibus__cyc$next[0:0]$5502 \ibus__cyc + assign $2\ibus__cyc$next[0:0]$5481 \ibus__cyc end case - assign $1\ibus__cyc$next[0:0]$5501 \ibus__cyc + assign $1\ibus__cyc$next[0:0]$5480 \ibus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__cyc$next[0:0]$5504 1'0 + assign $4\ibus__cyc$next[0:0]$5483 1'0 case - assign $4\ibus__cyc$next[0:0]$5504 $1\ibus__cyc$next[0:0]$5501 + assign $4\ibus__cyc$next[0:0]$5483 $1\ibus__cyc$next[0:0]$5480 end sync always - update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5500 + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5479 end - attribute \src "libresoc.v:135575.3-135602.6" - process $proc$libresoc.v:135575$5505 + attribute \src "libresoc.v:136172.3-136199.6" + process $proc$libresoc.v:136172$5484 assign { } { } assign { } { } assign { } { } - assign $0\ibus__stb$next[0:0]$5506 $4\ibus__stb$next[0:0]$5510 - attribute \src "libresoc.v:135576.5-135576.29" + assign $0\ibus__stb$next[0:0]$5485 $4\ibus__stb$next[0:0]$5489 + attribute \src "libresoc.v:136173.5-136173.29" switch \initial - attribute \src "libresoc.v:135576.9-135576.17" + attribute \src "libresoc.v:136173.9-136173.17" case 1'1 case end @@ -214423,53 +214565,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__stb$next[0:0]$5507 $2\ibus__stb$next[0:0]$5508 + assign $1\ibus__stb$next[0:0]$5486 $2\ibus__stb$next[0:0]$5487 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$13 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__stb$next[0:0]$5508 $3\ibus__stb$next[0:0]$5509 + assign $2\ibus__stb$next[0:0]$5487 $3\ibus__stb$next[0:0]$5488 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__stb$next[0:0]$5509 1'0 + assign $3\ibus__stb$next[0:0]$5488 1'0 case - assign $3\ibus__stb$next[0:0]$5509 \ibus__stb + assign $3\ibus__stb$next[0:0]$5488 \ibus__stb end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__stb$next[0:0]$5508 1'1 + assign $2\ibus__stb$next[0:0]$5487 1'1 case - assign $2\ibus__stb$next[0:0]$5508 \ibus__stb + assign $2\ibus__stb$next[0:0]$5487 \ibus__stb end case - assign $1\ibus__stb$next[0:0]$5507 \ibus__stb + assign $1\ibus__stb$next[0:0]$5486 \ibus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__stb$next[0:0]$5510 1'0 + assign $4\ibus__stb$next[0:0]$5489 1'0 case - assign $4\ibus__stb$next[0:0]$5510 $1\ibus__stb$next[0:0]$5507 + assign $4\ibus__stb$next[0:0]$5489 $1\ibus__stb$next[0:0]$5486 end sync always - update \ibus__stb$next $0\ibus__stb$next[0:0]$5506 + update \ibus__stb$next $0\ibus__stb$next[0:0]$5485 end - attribute \src "libresoc.v:135603.3-135630.6" - process $proc$libresoc.v:135603$5511 + attribute \src "libresoc.v:136200.3-136227.6" + process $proc$libresoc.v:136200$5490 assign { } { } assign { } { } assign { } { } - assign $0\ibus__sel$next[7:0]$5512 $4\ibus__sel$next[7:0]$5516 - attribute \src "libresoc.v:135604.5-135604.29" + assign $0\ibus__sel$next[7:0]$5491 $4\ibus__sel$next[7:0]$5495 + attribute \src "libresoc.v:136201.5-136201.29" switch \initial - attribute \src "libresoc.v:135604.9-135604.17" + attribute \src "libresoc.v:136201.9-136201.17" case 1'1 case end @@ -214478,53 +214620,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__sel$next[7:0]$5513 $2\ibus__sel$next[7:0]$5514 + assign $1\ibus__sel$next[7:0]$5492 $2\ibus__sel$next[7:0]$5493 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$23 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__sel$next[7:0]$5514 $3\ibus__sel$next[7:0]$5515 + assign $2\ibus__sel$next[7:0]$5493 $3\ibus__sel$next[7:0]$5494 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__sel$next[7:0]$5515 8'00000000 + assign $3\ibus__sel$next[7:0]$5494 8'00000000 case - assign $3\ibus__sel$next[7:0]$5515 \ibus__sel + assign $3\ibus__sel$next[7:0]$5494 \ibus__sel end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__sel$next[7:0]$5514 8'11111111 + assign $2\ibus__sel$next[7:0]$5493 8'11111111 case - assign $2\ibus__sel$next[7:0]$5514 \ibus__sel + assign $2\ibus__sel$next[7:0]$5493 \ibus__sel end case - assign $1\ibus__sel$next[7:0]$5513 \ibus__sel + assign $1\ibus__sel$next[7:0]$5492 \ibus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__sel$next[7:0]$5516 8'00000000 + assign $4\ibus__sel$next[7:0]$5495 8'00000000 case - assign $4\ibus__sel$next[7:0]$5516 $1\ibus__sel$next[7:0]$5513 + assign $4\ibus__sel$next[7:0]$5495 $1\ibus__sel$next[7:0]$5492 end sync always - update \ibus__sel$next $0\ibus__sel$next[7:0]$5512 + update \ibus__sel$next $0\ibus__sel$next[7:0]$5491 end - attribute \src "libresoc.v:135631.3-135655.6" - process $proc$libresoc.v:135631$5517 + attribute \src "libresoc.v:136228.3-136252.6" + process $proc$libresoc.v:136228$5496 assign { } { } assign { } { } assign { } { } - assign $0\ibus_rdata$next[63:0]$5518 $4\ibus_rdata$next[63:0]$5522 - attribute \src "libresoc.v:135632.5-135632.29" + assign $0\ibus_rdata$next[63:0]$5497 $4\ibus_rdata$next[63:0]$5501 + attribute \src "libresoc.v:136229.5-136229.29" switch \initial - attribute \src "libresoc.v:135632.9-135632.17" + attribute \src "libresoc.v:136229.9-136229.17" case 1'1 case end @@ -214533,49 +214675,49 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus_rdata$next[63:0]$5519 $2\ibus_rdata$next[63:0]$5520 + assign $1\ibus_rdata$next[63:0]$5498 $2\ibus_rdata$next[63:0]$5499 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$33 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus_rdata$next[63:0]$5520 $3\ibus_rdata$next[63:0]$5521 + assign $2\ibus_rdata$next[63:0]$5499 $3\ibus_rdata$next[63:0]$5500 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus_rdata$next[63:0]$5521 \ibus__dat_r + assign $3\ibus_rdata$next[63:0]$5500 \ibus__dat_r case - assign $3\ibus_rdata$next[63:0]$5521 \ibus_rdata + assign $3\ibus_rdata$next[63:0]$5500 \ibus_rdata end case - assign $2\ibus_rdata$next[63:0]$5520 \ibus_rdata + assign $2\ibus_rdata$next[63:0]$5499 \ibus_rdata end case - assign $1\ibus_rdata$next[63:0]$5519 \ibus_rdata + assign $1\ibus_rdata$next[63:0]$5498 \ibus_rdata end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus_rdata$next[63:0]$5522 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\ibus_rdata$next[63:0]$5501 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\ibus_rdata$next[63:0]$5522 $1\ibus_rdata$next[63:0]$5519 + assign $4\ibus_rdata$next[63:0]$5501 $1\ibus_rdata$next[63:0]$5498 end sync always - update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5518 + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5497 end - attribute \src "libresoc.v:135656.3-135678.6" - process $proc$libresoc.v:135656$5523 + attribute \src "libresoc.v:136253.3-136275.6" + process $proc$libresoc.v:136253$5502 assign { } { } assign { } { } assign { } { } - assign $0\ibus__adr$next[44:0]$5524 $3\ibus__adr$next[44:0]$5527 - attribute \src "libresoc.v:135657.5-135657.29" + assign $0\ibus__adr$next[44:0]$5503 $3\ibus__adr$next[44:0]$5506 + attribute \src "libresoc.v:136254.5-136254.29" switch \initial - attribute \src "libresoc.v:135657.9-135657.17" + attribute \src "libresoc.v:136254.9-136254.17" case 1'1 case end @@ -214584,43 +214726,43 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__adr$next[44:0]$5525 $2\ibus__adr$next[44:0]$5526 + assign $1\ibus__adr$next[44:0]$5504 $2\ibus__adr$next[44:0]$5505 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$43 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\ibus__adr$next[44:0]$5526 \ibus__adr + assign $2\ibus__adr$next[44:0]$5505 \ibus__adr attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__adr$next[44:0]$5526 \a_pc_i [47:3] + assign $2\ibus__adr$next[44:0]$5505 \a_pc_i [47:3] case - assign $2\ibus__adr$next[44:0]$5526 \ibus__adr + assign $2\ibus__adr$next[44:0]$5505 \ibus__adr end case - assign $1\ibus__adr$next[44:0]$5525 \ibus__adr + assign $1\ibus__adr$next[44:0]$5504 \ibus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__adr$next[44:0]$5527 45'000000000000000000000000000000000000000000000 + assign $3\ibus__adr$next[44:0]$5506 45'000000000000000000000000000000000000000000000 case - assign $3\ibus__adr$next[44:0]$5527 $1\ibus__adr$next[44:0]$5525 + assign $3\ibus__adr$next[44:0]$5506 $1\ibus__adr$next[44:0]$5504 end sync always - update \ibus__adr$next $0\ibus__adr$next[44:0]$5524 + update \ibus__adr$next $0\ibus__adr$next[44:0]$5503 end - attribute \src "libresoc.v:135679.3-135701.6" - process $proc$libresoc.v:135679$5528 + attribute \src "libresoc.v:136276.3-136298.6" + process $proc$libresoc.v:136276$5507 assign { } { } assign { } { } assign { } { } - assign $0\f_fetch_err_o$next[0:0]$5529 $3\f_fetch_err_o$next[0:0]$5532 - attribute \src "libresoc.v:135680.5-135680.29" + assign $0\f_fetch_err_o$next[0:0]$5508 $3\f_fetch_err_o$next[0:0]$5511 + attribute \src "libresoc.v:136277.5-136277.29" switch \initial - attribute \src "libresoc.v:135680.9-135680.17" + attribute \src "libresoc.v:136277.9-136277.17" case 1'1 case end @@ -214629,44 +214771,44 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_fetch_err_o$next[0:0]$5530 $2\f_fetch_err_o$next[0:0]$5531 + assign $1\f_fetch_err_o$next[0:0]$5509 $2\f_fetch_err_o$next[0:0]$5510 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" switch { \$47 \$45 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5531 1'1 + assign $2\f_fetch_err_o$next[0:0]$5510 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5531 1'0 + assign $2\f_fetch_err_o$next[0:0]$5510 1'0 case - assign $2\f_fetch_err_o$next[0:0]$5531 \f_fetch_err_o + assign $2\f_fetch_err_o$next[0:0]$5510 \f_fetch_err_o end case - assign $1\f_fetch_err_o$next[0:0]$5530 \f_fetch_err_o + assign $1\f_fetch_err_o$next[0:0]$5509 \f_fetch_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\f_fetch_err_o$next[0:0]$5532 1'0 + assign $3\f_fetch_err_o$next[0:0]$5511 1'0 case - assign $3\f_fetch_err_o$next[0:0]$5532 $1\f_fetch_err_o$next[0:0]$5530 + assign $3\f_fetch_err_o$next[0:0]$5511 $1\f_fetch_err_o$next[0:0]$5509 end sync always - update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5529 + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5508 end - attribute \src "libresoc.v:135702.3-135721.6" - process $proc$libresoc.v:135702$5533 + attribute \src "libresoc.v:136299.3-136318.6" + process $proc$libresoc.v:136299$5512 assign { } { } assign { } { } assign { } { } - assign $0\f_badaddr_o$next[44:0]$5534 $3\f_badaddr_o$next[44:0]$5537 - attribute \src "libresoc.v:135703.5-135703.29" + assign $0\f_badaddr_o$next[44:0]$5513 $3\f_badaddr_o$next[44:0]$5516 + attribute \src "libresoc.v:136300.5-136300.29" switch \initial - attribute \src "libresoc.v:135703.9-135703.17" + attribute \src "libresoc.v:136300.9-136300.17" case 1'1 case end @@ -214675,39 +214817,39 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_badaddr_o$next[44:0]$5535 $2\f_badaddr_o$next[44:0]$5536 + assign $1\f_badaddr_o$next[44:0]$5514 $2\f_badaddr_o$next[44:0]$5515 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" switch { \$51 \$49 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\f_badaddr_o$next[44:0]$5536 \ibus__adr + assign $2\f_badaddr_o$next[44:0]$5515 \ibus__adr case - assign $2\f_badaddr_o$next[44:0]$5536 \f_badaddr_o + assign $2\f_badaddr_o$next[44:0]$5515 \f_badaddr_o end case - assign $1\f_badaddr_o$next[44:0]$5535 \f_badaddr_o + assign $1\f_badaddr_o$next[44:0]$5514 \f_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\f_badaddr_o$next[44:0]$5537 45'000000000000000000000000000000000000000000000 + assign $3\f_badaddr_o$next[44:0]$5516 45'000000000000000000000000000000000000000000000 case - assign $3\f_badaddr_o$next[44:0]$5537 $1\f_badaddr_o$next[44:0]$5535 + assign $3\f_badaddr_o$next[44:0]$5516 $1\f_badaddr_o$next[44:0]$5514 end sync always - update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5534 + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5513 end - attribute \src "libresoc.v:135722.3-135731.6" - process $proc$libresoc.v:135722$5538 + attribute \src "libresoc.v:136319.3-136328.6" + process $proc$libresoc.v:136319$5517 assign { } { } assign { } { } assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] - attribute \src "libresoc.v:135723.5-135723.29" + attribute \src "libresoc.v:136320.5-136320.29" switch \initial - attribute \src "libresoc.v:135723.9-135723.17" + attribute \src "libresoc.v:136320.9-136320.17" case 1'1 case end @@ -214723,14 +214865,14 @@ module \imem sync always update \a_busy_o $0\a_busy_o[0:0] end - attribute \src "libresoc.v:135732.3-135749.6" - process $proc$libresoc.v:135732$5539 + attribute \src "libresoc.v:136329.3-136346.6" + process $proc$libresoc.v:136329$5518 assign { } { } assign { } { } assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] - attribute \src "libresoc.v:135733.5-135733.29" + attribute \src "libresoc.v:136330.5-136330.29" switch \initial - attribute \src "libresoc.v:135733.9-135733.17" + attribute \src "libresoc.v:136330.9-136330.17" case 1'1 case end @@ -214757,14 +214899,14 @@ module \imem sync always update \f_busy_o $0\f_busy_o[0:0] end - attribute \src "libresoc.v:135750.3-135767.6" - process $proc$libresoc.v:135750$5540 + attribute \src "libresoc.v:136347.3-136364.6" + process $proc$libresoc.v:136347$5519 assign { } { } assign { } { } assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] - attribute \src "libresoc.v:135751.5-135751.29" + attribute \src "libresoc.v:136348.5-136348.29" switch \initial - attribute \src "libresoc.v:135751.9-135751.17" + attribute \src "libresoc.v:136348.9-136348.17" case 1'1 case end @@ -214790,52 +214932,52 @@ module \imem sync always update \f_instr_o $0\f_instr_o[63:0] end - connect \$9 $or$libresoc.v:135507$5466_Y - connect \$11 $not$libresoc.v:135508$5467_Y - connect \$13 $and$libresoc.v:135509$5468_Y - connect \$15 $or$libresoc.v:135510$5469_Y - connect \$17 $not$libresoc.v:135511$5470_Y - connect \$1 $not$libresoc.v:135512$5471_Y - connect \$19 $or$libresoc.v:135513$5472_Y - connect \$21 $not$libresoc.v:135514$5473_Y - connect \$23 $and$libresoc.v:135515$5474_Y - connect \$25 $or$libresoc.v:135516$5475_Y - connect \$27 $not$libresoc.v:135517$5476_Y - connect \$29 $or$libresoc.v:135518$5477_Y - connect \$31 $not$libresoc.v:135519$5478_Y - connect \$33 $and$libresoc.v:135520$5479_Y - connect \$35 $or$libresoc.v:135521$5480_Y - connect \$37 $not$libresoc.v:135522$5481_Y - connect \$3 $and$libresoc.v:135523$5482_Y - connect \$39 $or$libresoc.v:135524$5483_Y - connect \$41 $not$libresoc.v:135525$5484_Y - connect \$43 $and$libresoc.v:135526$5485_Y - connect \$45 $and$libresoc.v:135527$5486_Y - connect \$47 $not$libresoc.v:135528$5487_Y - connect \$49 $and$libresoc.v:135529$5488_Y - connect \$51 $not$libresoc.v:135530$5489_Y - connect \$5 $or$libresoc.v:135531$5490_Y - connect \$7 $not$libresoc.v:135532$5491_Y + connect \$9 $or$libresoc.v:136104$5445_Y + connect \$11 $not$libresoc.v:136105$5446_Y + connect \$13 $and$libresoc.v:136106$5447_Y + connect \$15 $or$libresoc.v:136107$5448_Y + connect \$17 $not$libresoc.v:136108$5449_Y + connect \$1 $not$libresoc.v:136109$5450_Y + connect \$19 $or$libresoc.v:136110$5451_Y + connect \$21 $not$libresoc.v:136111$5452_Y + connect \$23 $and$libresoc.v:136112$5453_Y + connect \$25 $or$libresoc.v:136113$5454_Y + connect \$27 $not$libresoc.v:136114$5455_Y + connect \$29 $or$libresoc.v:136115$5456_Y + connect \$31 $not$libresoc.v:136116$5457_Y + connect \$33 $and$libresoc.v:136117$5458_Y + connect \$35 $or$libresoc.v:136118$5459_Y + connect \$37 $not$libresoc.v:136119$5460_Y + connect \$3 $and$libresoc.v:136120$5461_Y + connect \$39 $or$libresoc.v:136121$5462_Y + connect \$41 $not$libresoc.v:136122$5463_Y + connect \$43 $and$libresoc.v:136123$5464_Y + connect \$45 $and$libresoc.v:136124$5465_Y + connect \$47 $not$libresoc.v:136125$5466_Y + connect \$49 $and$libresoc.v:136126$5467_Y + connect \$51 $not$libresoc.v:136127$5468_Y + connect \$5 $or$libresoc.v:136128$5469_Y + connect \$7 $not$libresoc.v:136129$5470_Y connect \a_stall_i 1'0 connect \f_stall_i 1'0 end -attribute \src "libresoc.v:135774.1-136101.10" +attribute \src "libresoc.v:136371.1-136698.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" attribute \generator "nMigen" module \input - attribute \src "libresoc.v:136064.3-136075.6" + attribute \src "libresoc.v:136661.3-136672.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:135775.7-135775.20" + attribute \src "libresoc.v:136372.7-136372.20" wire $0\initial[0:0] - attribute \src "libresoc.v:136076.3-136094.6" - wire width 2 $0\xer_ca$23[1:0]$5552 - attribute \src "libresoc.v:136064.3-136075.6" + attribute \src "libresoc.v:136673.3-136691.6" + wire width 2 $0\xer_ca$23[1:0]$5531 + attribute \src "libresoc.v:136661.3-136672.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:136076.3-136094.6" - wire width 2 $1\xer_ca$23[1:0]$5553 - attribute \src "libresoc.v:136063.18-136063.100" - wire width 64 $not$libresoc.v:136063$5549_Y + attribute \src "libresoc.v:136673.3-136691.6" + wire width 2 $1\xer_ca$23[1:0]$5532 + attribute \src "libresoc.v:136660.18-136660.100" + wire width 64 $not$libresoc.v:136660$5528_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" @@ -215102,7 +215244,7 @@ module \input wire output 33 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:135775.7-135775.15" + attribute \src "libresoc.v:136372.7-136372.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid @@ -215125,28 +215267,28 @@ module \input attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:136063$5549 + cell $not $not$libresoc.v:136660$5528 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:136063$5549_Y + connect \Y $not$libresoc.v:136660$5528_Y end - attribute \src "libresoc.v:135775.7-135775.20" - process $proc$libresoc.v:135775$5554 + attribute \src "libresoc.v:136372.7-136372.20" + process $proc$libresoc.v:136372$5533 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:136064.3-136075.6" - process $proc$libresoc.v:136064$5550 + attribute \src "libresoc.v:136661.3-136672.6" + process $proc$libresoc.v:136661$5529 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:136065.5-136065.29" + attribute \src "libresoc.v:136662.5-136662.29" switch \initial - attribute \src "libresoc.v:136065.9-136065.17" + attribute \src "libresoc.v:136662.9-136662.17" case 1'1 case end @@ -215164,14 +215306,14 @@ module \input sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:136076.3-136094.6" - process $proc$libresoc.v:136076$5551 + attribute \src "libresoc.v:136673.3-136691.6" + process $proc$libresoc.v:136673$5530 assign { } { } assign { } { } - assign $0\xer_ca$23[1:0]$5552 $1\xer_ca$23[1:0]$5553 - attribute \src "libresoc.v:136077.5-136077.29" + assign $0\xer_ca$23[1:0]$5531 $1\xer_ca$23[1:0]$5532 + attribute \src "libresoc.v:136674.5-136674.29" switch \initial - attribute \src "libresoc.v:136077.9-136077.17" + attribute \src "libresoc.v:136674.9-136674.17" case 1'1 case end @@ -215180,22 +215322,22 @@ module \input attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\xer_ca$23[1:0]$5553 2'00 + assign $1\xer_ca$23[1:0]$5532 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\xer_ca$23[1:0]$5553 2'11 + assign $1\xer_ca$23[1:0]$5532 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\xer_ca$23[1:0]$5553 \xer_ca + assign $1\xer_ca$23[1:0]$5532 \xer_ca case - assign $1\xer_ca$23[1:0]$5553 2'00 + assign $1\xer_ca$23[1:0]$5532 2'00 end sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5552 + update \xer_ca$23 $0\xer_ca$23[1:0]$5531 end - connect \$24 $not$libresoc.v:136063$5549_Y + connect \$24 $not$libresoc.v:136660$5528_Y connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -215203,30 +215345,30 @@ module \input connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:136105.1-136433.10" +attribute \src "libresoc.v:136702.1-137030.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" attribute \generator "nMigen" module \input$113 - attribute \src "libresoc.v:136395.3-136406.6" + attribute \src "libresoc.v:136992.3-137003.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:136106.7-136106.20" + attribute \src "libresoc.v:136703.7-136703.20" wire $0\initial[0:0] - attribute \src "libresoc.v:136407.3-136425.6" - wire width 2 $0\xer_ca$23[1:0]$5558 - attribute \src "libresoc.v:136395.3-136406.6" + attribute \src "libresoc.v:137004.3-137022.6" + wire width 2 $0\xer_ca$23[1:0]$5537 + attribute \src "libresoc.v:136992.3-137003.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:136407.3-136425.6" - wire width 2 $1\xer_ca$23[1:0]$5559 - attribute \src "libresoc.v:136394.18-136394.100" - wire width 64 $not$libresoc.v:136394$5555_Y + attribute \src "libresoc.v:137004.3-137022.6" + wire width 2 $1\xer_ca$23[1:0]$5538 + attribute \src "libresoc.v:136991.18-136991.100" + wire width 64 $not$libresoc.v:136991$5534_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:136106.7-136106.15" + attribute \src "libresoc.v:136703.7-136703.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid @@ -215509,28 +215651,28 @@ module \input$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:136394$5555 + cell $not $not$libresoc.v:136991$5534 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:136394$5555_Y + connect \Y $not$libresoc.v:136991$5534_Y end - attribute \src "libresoc.v:136106.7-136106.20" - process $proc$libresoc.v:136106$5560 + attribute \src "libresoc.v:136703.7-136703.20" + process $proc$libresoc.v:136703$5539 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:136395.3-136406.6" - process $proc$libresoc.v:136395$5556 + attribute \src "libresoc.v:136992.3-137003.6" + process $proc$libresoc.v:136992$5535 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:136396.5-136396.29" + attribute \src "libresoc.v:136993.5-136993.29" switch \initial - attribute \src "libresoc.v:136396.9-136396.17" + attribute \src "libresoc.v:136993.9-136993.17" case 1'1 case end @@ -215548,14 +215690,14 @@ module \input$113 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:136407.3-136425.6" - process $proc$libresoc.v:136407$5557 + attribute \src "libresoc.v:137004.3-137022.6" + process $proc$libresoc.v:137004$5536 assign { } { } assign { } { } - assign $0\xer_ca$23[1:0]$5558 $1\xer_ca$23[1:0]$5559 - attribute \src "libresoc.v:136408.5-136408.29" + assign $0\xer_ca$23[1:0]$5537 $1\xer_ca$23[1:0]$5538 + attribute \src "libresoc.v:137005.5-137005.29" switch \initial - attribute \src "libresoc.v:136408.9-136408.17" + attribute \src "libresoc.v:137005.9-137005.17" case 1'1 case end @@ -215564,22 +215706,22 @@ module \input$113 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\xer_ca$23[1:0]$5559 2'00 + assign $1\xer_ca$23[1:0]$5538 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\xer_ca$23[1:0]$5559 2'11 + assign $1\xer_ca$23[1:0]$5538 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\xer_ca$23[1:0]$5559 \xer_ca + assign $1\xer_ca$23[1:0]$5538 \xer_ca case - assign $1\xer_ca$23[1:0]$5559 2'00 + assign $1\xer_ca$23[1:0]$5538 2'00 end sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5558 + update \xer_ca$23 $0\xer_ca$23[1:0]$5537 end - connect \$24 $not$libresoc.v:136394$5555_Y + connect \$24 $not$libresoc.v:136991$5534_Y connect \rc$21 \rc connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid @@ -215588,26 +215730,26 @@ module \input$113 connect \b \rb connect \ra$19 \a end -attribute \src "libresoc.v:136437.1-136740.10" +attribute \src "libresoc.v:137034.1-137337.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" attribute \generator "nMigen" module \input$50 - attribute \src "libresoc.v:136722.3-136733.6" + attribute \src "libresoc.v:137319.3-137330.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:136438.7-136438.20" + attribute \src "libresoc.v:137035.7-137035.20" wire $0\initial[0:0] - attribute \src "libresoc.v:136722.3-136733.6" + attribute \src "libresoc.v:137319.3-137330.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:136721.18-136721.100" - wire width 64 $not$libresoc.v:136721$5561_Y + attribute \src "libresoc.v:137318.18-137318.100" + wire width 64 $not$libresoc.v:137318$5540_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:136438.7-136438.15" + attribute \src "libresoc.v:137035.7-137035.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -215886,28 +216028,28 @@ module \input$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - cell $not $not$libresoc.v:136721$5561 + cell $not $not$libresoc.v:137318$5540 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rb - connect \Y $not$libresoc.v:136721$5561_Y + connect \Y $not$libresoc.v:137318$5540_Y end - attribute \src "libresoc.v:136438.7-136438.20" - process $proc$libresoc.v:136438$5563 + attribute \src "libresoc.v:137035.7-137035.20" + process $proc$libresoc.v:137035$5542 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:136722.3-136733.6" - process $proc$libresoc.v:136722$5562 + attribute \src "libresoc.v:137319.3-137330.6" + process $proc$libresoc.v:137319$5541 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:136723.5-136723.29" + attribute \src "libresoc.v:137320.5-137320.29" switch \initial - attribute \src "libresoc.v:136723.9-136723.17" + attribute \src "libresoc.v:137320.9-137320.17" case 1'1 case end @@ -215925,7 +216067,7 @@ module \input$50 sync always update \b $0\b[63:0] end - connect \$23 $not$libresoc.v:136721$5561_Y + connect \$23 $not$libresoc.v:137318$5540_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -215933,26 +216075,26 @@ module \input$50 connect \ra$20 \a connect \a \ra end -attribute \src "libresoc.v:136744.1-137047.10" +attribute \src "libresoc.v:137341.1-137644.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" attribute \generator "nMigen" module \input$78 - attribute \src "libresoc.v:137029.3-137040.6" + attribute \src "libresoc.v:137626.3-137637.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:136745.7-136745.20" + attribute \src "libresoc.v:137342.7-137342.20" wire $0\initial[0:0] - attribute \src "libresoc.v:137029.3-137040.6" + attribute \src "libresoc.v:137626.3-137637.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:137028.18-137028.100" - wire width 64 $not$libresoc.v:137028$5564_Y + attribute \src "libresoc.v:137625.18-137625.100" + wire width 64 $not$libresoc.v:137625$5543_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:136745.7-136745.15" + attribute \src "libresoc.v:137342.7-137342.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -216231,28 +216373,28 @@ module \input$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:137028$5564 + cell $not $not$libresoc.v:137625$5543 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:137028$5564_Y + connect \Y $not$libresoc.v:137625$5543_Y end - attribute \src "libresoc.v:136745.7-136745.20" - process $proc$libresoc.v:136745$5566 + attribute \src "libresoc.v:137342.7-137342.20" + process $proc$libresoc.v:137342$5545 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137029.3-137040.6" - process $proc$libresoc.v:137029$5565 + attribute \src "libresoc.v:137626.3-137637.6" + process $proc$libresoc.v:137626$5544 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:137030.5-137030.29" + attribute \src "libresoc.v:137627.5-137627.29" switch \initial - attribute \src "libresoc.v:137030.9-137030.17" + attribute \src "libresoc.v:137627.9-137627.17" case 1'1 case end @@ -216270,7 +216412,7 @@ module \input$78 sync always update \a $0\a[63:0] end - connect \$23 $not$libresoc.v:137028$5564_Y + connect \$23 $not$libresoc.v:137625$5543_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -216278,7 +216420,7 @@ module \input$78 connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:137051.1-137307.10" +attribute \src "libresoc.v:137648.1-137904.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" attribute \generator "nMigen" @@ -216539,527 +216681,437 @@ module \input$95 connect \ra$14 \a connect \a \ra end -attribute \src "libresoc.v:137311.1-137571.10" +attribute \src "libresoc.v:137908.1-138047.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.int" attribute \generator "nMigen" module \int - attribute \src "libresoc.v:137453.3-137460.6" - wire width 5 $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 - attribute \src "libresoc.v:137453.3-137460.6" - wire width 64 $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 - attribute \src "libresoc.v:137453.3-137460.6" - wire width 64 $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 - attribute \src "libresoc.v:137453.3-137460.6" + attribute \src "libresoc.v:137993.3-137997.6" + wire width 5 $0$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5580 + attribute \src "libresoc.v:137993.3-137997.6" + wire width 64 $0$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5581 + attribute \src "libresoc.v:137993.3-137997.6" + wire width 64 $0$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5582 + attribute \src "libresoc.v:137993.3-137997.6" wire width 5 $0\_0_[4:0] - attribute \src "libresoc.v:137453.3-137460.6" + attribute \src "libresoc.v:137993.3-137997.6" wire width 5 $0\_1_[4:0] - attribute \src "libresoc.v:137453.3-137460.6" - wire width 5 $0\_2_[4:0] - attribute \src "libresoc.v:137453.3-137460.6" - wire width 5 $0\_3_[4:0] - attribute \src "libresoc.v:137453.3-137460.6" - wire width 5 $0\_4_[4:0] - attribute \src "libresoc.v:137503.3-137512.6" + attribute \src "libresoc.v:138013.3-138022.6" wire width 64 $0\dmi__data_o[63:0] - attribute \src "libresoc.v:137312.7-137312.20" + attribute \src "libresoc.v:137909.7-137909.20" wire $0\initial[0:0] - attribute \src "libresoc.v:137484.3-137493.6" - wire width 64 $0\pred__data_o[63:0] - attribute \src "libresoc.v:137523.3-137531.6" - wire $0\ren_delay$10$next[0:0]$5631 - attribute \src "libresoc.v:137409.3-137410.43" - wire $0\ren_delay$10[0:0]$5607 - attribute \src "libresoc.v:137365.7-137365.28" - wire $0\ren_delay$10[0:0]$5674 - attribute \src "libresoc.v:137542.3-137550.6" - wire $0\ren_delay$11$next[0:0]$5635 - attribute \src "libresoc.v:137407.3-137408.43" - wire $0\ren_delay$11[0:0]$5605 - attribute \src "libresoc.v:137369.7-137369.28" - wire $0\ren_delay$11[0:0]$5676 - attribute \src "libresoc.v:137475.3-137483.6" - wire $0\ren_delay$12$next[0:0]$5622 - attribute \src "libresoc.v:137405.3-137406.43" - wire $0\ren_delay$12[0:0]$5603 - attribute \src "libresoc.v:137373.7-137373.28" - wire $0\ren_delay$12[0:0]$5678 - attribute \src "libresoc.v:137494.3-137502.6" - wire $0\ren_delay$13$next[0:0]$5626 - attribute \src "libresoc.v:137403.3-137404.43" - wire $0\ren_delay$13[0:0]$5601 - attribute \src "libresoc.v:137377.7-137377.28" - wire $0\ren_delay$13[0:0]$5680 - attribute \src "libresoc.v:137466.3-137474.6" - wire $0\ren_delay$next[0:0]$5619 - attribute \src "libresoc.v:137411.3-137412.35" + attribute \src "libresoc.v:138023.3-138031.6" + wire $0\ren_delay$4$next[0:0]$5596 + attribute \src "libresoc.v:138000.3-138001.41" + wire $0\ren_delay$4[0:0]$5589 + attribute \src "libresoc.v:137944.7-137944.27" + wire $0\ren_delay$4[0:0]$5634 + attribute \src "libresoc.v:138004.3-138012.6" + wire $0\ren_delay$next[0:0]$5592 + attribute \src "libresoc.v:138002.3-138003.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:137513.3-137522.6" - wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:137532.3-137541.6" - wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:137551.3-137560.6" - wire width 64 $0\src3__data_o[63:0] - attribute \src "libresoc.v:137503.3-137512.6" + attribute \src "libresoc.v:138032.3-138041.6" + wire width 64 $0\src__data_o[63:0] + attribute \src "libresoc.v:137993.3-137997.6" + wire width 5 $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 + attribute \src "libresoc.v:137993.3-137997.6" + wire width 64 $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 + attribute \src "libresoc.v:137993.3-137997.6" + wire width 64 $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 + attribute \src "libresoc.v:138013.3-138022.6" wire width 64 $1\dmi__data_o[63:0] - attribute \src "libresoc.v:137484.3-137493.6" - wire width 64 $1\pred__data_o[63:0] - attribute \src "libresoc.v:137523.3-137531.6" - wire $1\ren_delay$10$next[0:0]$5632 - attribute \src "libresoc.v:137542.3-137550.6" - wire $1\ren_delay$11$next[0:0]$5636 - attribute \src "libresoc.v:137475.3-137483.6" - wire $1\ren_delay$12$next[0:0]$5623 - attribute \src "libresoc.v:137494.3-137502.6" - wire $1\ren_delay$13$next[0:0]$5627 - attribute \src "libresoc.v:137466.3-137474.6" - wire $1\ren_delay$next[0:0]$5620 - attribute \src "libresoc.v:137363.7-137363.23" + attribute \src "libresoc.v:138023.3-138031.6" + wire $1\ren_delay$4$next[0:0]$5597 + attribute \src "libresoc.v:138004.3-138012.6" + wire $1\ren_delay$next[0:0]$5593 + attribute \src "libresoc.v:137942.7-137942.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:137513.3-137522.6" - wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:137532.3-137541.6" - wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:137551.3-137560.6" - wire width 64 $1\src3__data_o[63:0] - attribute \src "libresoc.v:137461.26-137461.32" - wire width 64 $memrd$\memory$libresoc.v:137461$5613_DATA - attribute \src "libresoc.v:137462.30-137462.36" - wire width 64 $memrd$\memory$libresoc.v:137462$5614_DATA - attribute \src "libresoc.v:137463.30-137463.36" - wire width 64 $memrd$\memory$libresoc.v:137463$5615_DATA - attribute \src "libresoc.v:137464.30-137464.36" - wire width 64 $memrd$\memory$libresoc.v:137464$5616_DATA - attribute \src "libresoc.v:137465.30-137465.36" - wire width 64 $memrd$\memory$libresoc.v:137465$5617_DATA + attribute \src "libresoc.v:138032.3-138041.6" + wire width 64 $1\src__data_o[63:0] + attribute \src "libresoc.v:137998.26-137998.32" + wire width 64 $memrd$\memory$libresoc.v:137998$5586_DATA + attribute \src "libresoc.v:137999.30-137999.36" + wire width 64 $memrd$\memory$libresoc.v:137999$5587_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 5 $memwr$\memory$libresoc.v:137459$5599_ADDR + wire width 5 $memwr$\memory$libresoc.v:137996$5578_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:137459$5599_DATA + wire width 64 $memwr$\memory$libresoc.v:137996$5578_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:137459$5599_EN - attribute \src "libresoc.v:137448.13-137448.16" + wire width 64 $memwr$\memory$libresoc.v:137996$5578_EN + attribute \src "libresoc.v:137991.13-137991.16" wire width 5 \_0_ - attribute \src "libresoc.v:137449.13-137449.16" + attribute \src "libresoc.v:137992.13-137992.16" wire width 5 \_1_ - attribute \src "libresoc.v:137450.13-137450.16" - wire width 5 \_2_ - attribute \src "libresoc.v:137451.13-137451.16" - wire width 5 \_3_ - attribute \src "libresoc.v:137452.13-137452.16" - wire width 5 \_4_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" - wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" + wire input 11 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 input 15 \dest1__addr + wire width 5 input 9 \dest1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 input 14 \dest1__data_i + wire width 64 input 8 \dest1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 16 \dest1__wen + wire input 10 \dest1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 2 \dmi__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 4 \dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 3 \dmi__ren - attribute \src "libresoc.v:137312.7-137312.15" + attribute \src "libresoc.v:137909.7-137909.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 5 \memory_w_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 64 \memory_w_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire \memory_w_en - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 \pred__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \pred__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire \pred__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10$next + wire \ren_delay$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$13$next + wire \ren_delay$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 input 6 \src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 5 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 7 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 input 9 \src2__addr + wire width 5 input 6 \src__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 8 \src2__data_o + wire width 64 output 5 \src__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 input 12 \src3__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 11 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \src3__ren - attribute \src "libresoc.v:137413.14-137413.20" + wire input 7 \src__ren + attribute \src "libresoc.v:137956.14-137956.20" memory width 64 size 32 \memory - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5638 + attribute \src "libresoc.v:137958.5-137958.37" + cell $meminit $meminit$\memory$libresoc.v:137958$5599 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5638 + parameter \PRIORITY 5599 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5639 + attribute \src "libresoc.v:137959.5-137959.37" + cell $meminit $meminit$\memory$libresoc.v:137959$5600 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5639 + parameter \PRIORITY 5600 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5640 + attribute \src "libresoc.v:137960.5-137960.37" + cell $meminit $meminit$\memory$libresoc.v:137960$5601 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5640 + parameter \PRIORITY 5601 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5641 + attribute \src "libresoc.v:137961.5-137961.37" + cell $meminit $meminit$\memory$libresoc.v:137961$5602 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5641 + parameter \PRIORITY 5602 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5642 + attribute \src "libresoc.v:137962.5-137962.37" + cell $meminit $meminit$\memory$libresoc.v:137962$5603 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5642 + parameter \PRIORITY 5603 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5643 + attribute \src "libresoc.v:137963.5-137963.37" + cell $meminit $meminit$\memory$libresoc.v:137963$5604 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5643 + parameter \PRIORITY 5604 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5644 + attribute \src "libresoc.v:137964.5-137964.37" + cell $meminit $meminit$\memory$libresoc.v:137964$5605 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5644 + parameter \PRIORITY 5605 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5645 + attribute \src "libresoc.v:137965.5-137965.37" + cell $meminit $meminit$\memory$libresoc.v:137965$5606 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5645 + parameter \PRIORITY 5606 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5646 + attribute \src "libresoc.v:137966.5-137966.37" + cell $meminit $meminit$\memory$libresoc.v:137966$5607 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5646 + parameter \PRIORITY 5607 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5647 + attribute \src "libresoc.v:137967.5-137967.37" + cell $meminit $meminit$\memory$libresoc.v:137967$5608 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5647 + parameter \PRIORITY 5608 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5648 + attribute \src "libresoc.v:137968.5-137968.38" + cell $meminit $meminit$\memory$libresoc.v:137968$5609 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5648 + parameter \PRIORITY 5609 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5649 + attribute \src "libresoc.v:137969.5-137969.38" + cell $meminit $meminit$\memory$libresoc.v:137969$5610 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5649 + parameter \PRIORITY 5610 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5650 + attribute \src "libresoc.v:137970.5-137970.38" + cell $meminit $meminit$\memory$libresoc.v:137970$5611 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5650 + parameter \PRIORITY 5611 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5651 + attribute \src "libresoc.v:137971.5-137971.38" + cell $meminit $meminit$\memory$libresoc.v:137971$5612 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5651 + parameter \PRIORITY 5612 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5652 + attribute \src "libresoc.v:137972.5-137972.38" + cell $meminit $meminit$\memory$libresoc.v:137972$5613 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5652 + parameter \PRIORITY 5613 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5653 + attribute \src "libresoc.v:137973.5-137973.38" + cell $meminit $meminit$\memory$libresoc.v:137973$5614 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5653 + parameter \PRIORITY 5614 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5654 + attribute \src "libresoc.v:137974.5-137974.38" + cell $meminit $meminit$\memory$libresoc.v:137974$5615 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5654 + parameter \PRIORITY 5615 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5655 + attribute \src "libresoc.v:137975.5-137975.38" + cell $meminit $meminit$\memory$libresoc.v:137975$5616 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5655 + parameter \PRIORITY 5616 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5656 + attribute \src "libresoc.v:137976.5-137976.38" + cell $meminit $meminit$\memory$libresoc.v:137976$5617 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5656 + parameter \PRIORITY 5617 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5657 + attribute \src "libresoc.v:137977.5-137977.38" + cell $meminit $meminit$\memory$libresoc.v:137977$5618 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5657 + parameter \PRIORITY 5618 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5658 + attribute \src "libresoc.v:137978.5-137978.38" + cell $meminit $meminit$\memory$libresoc.v:137978$5619 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5658 + parameter \PRIORITY 5619 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5659 + attribute \src "libresoc.v:137979.5-137979.38" + cell $meminit $meminit$\memory$libresoc.v:137979$5620 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5659 + parameter \PRIORITY 5620 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5660 + attribute \src "libresoc.v:137980.5-137980.38" + cell $meminit $meminit$\memory$libresoc.v:137980$5621 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5660 + parameter \PRIORITY 5621 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5661 + attribute \src "libresoc.v:137981.5-137981.38" + cell $meminit $meminit$\memory$libresoc.v:137981$5622 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5661 + parameter \PRIORITY 5622 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5662 + attribute \src "libresoc.v:137982.5-137982.38" + cell $meminit $meminit$\memory$libresoc.v:137982$5623 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5662 + parameter \PRIORITY 5623 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5663 + attribute \src "libresoc.v:137983.5-137983.38" + cell $meminit $meminit$\memory$libresoc.v:137983$5624 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5663 + parameter \PRIORITY 5624 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5664 + attribute \src "libresoc.v:137984.5-137984.38" + cell $meminit $meminit$\memory$libresoc.v:137984$5625 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5664 + parameter \PRIORITY 5625 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5665 + attribute \src "libresoc.v:137985.5-137985.38" + cell $meminit $meminit$\memory$libresoc.v:137985$5626 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5665 + parameter \PRIORITY 5626 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5666 + attribute \src "libresoc.v:137986.5-137986.38" + cell $meminit $meminit$\memory$libresoc.v:137986$5627 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5666 + parameter \PRIORITY 5627 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5667 + attribute \src "libresoc.v:137987.5-137987.38" + cell $meminit $meminit$\memory$libresoc.v:137987$5628 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5667 + parameter \PRIORITY 5628 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5668 + attribute \src "libresoc.v:137988.5-137988.38" + cell $meminit $meminit$\memory$libresoc.v:137988$5629 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5668 + parameter \PRIORITY 5629 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5669 + attribute \src "libresoc.v:137989.5-137989.38" + cell $meminit $meminit$\memory$libresoc.v:137989$5630 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5669 + parameter \PRIORITY 5630 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:137461.26-137461.32" - cell $memrd $memrd$\memory$libresoc.v:137461$5613 + attribute \src "libresoc.v:137998.26-137998.32" + cell $memrd $memrd$\memory$libresoc.v:137998$5586 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -217068,11 +217120,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:137461$5613_DATA + connect \DATA $memrd$\memory$libresoc.v:137998$5586_DATA connect \EN 1'x end - attribute \src "libresoc.v:137462.30-137462.36" - cell $memrd $memrd$\memory$libresoc.v:137462$5614 + attribute \src "libresoc.v:137999.30-137999.36" + cell $memrd $memrd$\memory$libresoc.v:137999$5587 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -217081,217 +217133,145 @@ module \int parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:137462$5614_DATA + connect \DATA $memrd$\memory$libresoc.v:137999$5587_DATA connect \EN 1'x end - attribute \src "libresoc.v:137463.30-137463.36" - cell $memrd $memrd$\memory$libresoc.v:137463$5615 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_2_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:137463$5615_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:137464.30-137464.36" - cell $memrd $memrd$\memory$libresoc.v:137464$5616 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_3_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:137464$5616_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:137465.30-137465.36" - cell $memrd $memrd$\memory$libresoc.v:137465$5617 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_4_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:137465$5617_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5670 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 5670 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:137459$5599_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:137459$5599_DATA - connect \EN $memwr$\memory$libresoc.v:137459$5599_EN - end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5681 + process $proc$libresoc.v:0$5635 sync always sync init end - attribute \src "libresoc.v:137312.7-137312.20" - process $proc$libresoc.v:137312$5671 + attribute \src "libresoc.v:137909.7-137909.20" + process $proc$libresoc.v:137909$5631 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137363.7-137363.23" - process $proc$libresoc.v:137363$5672 + attribute \src "libresoc.v:137942.7-137942.23" + process $proc$libresoc.v:137942$5632 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:137365.7-137365.28" - process $proc$libresoc.v:137365$5673 + attribute \src "libresoc.v:137944.7-137944.27" + process $proc$libresoc.v:137944$5633 assign { } { } - assign $0\ren_delay$10[0:0]$5674 1'0 + assign $0\ren_delay$4[0:0]$5634 1'0 sync always sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5674 + update \ren_delay$4 $0\ren_delay$4[0:0]$5634 end - attribute \src "libresoc.v:137369.7-137369.28" - process $proc$libresoc.v:137369$5675 + attribute \src "libresoc.v:137993.3-137997.6" + process $proc$libresoc.v:137993$5579 + assign { } { } + assign { } { } assign { } { } - assign $0\ren_delay$11[0:0]$5676 1'0 - sync always - sync init - update \ren_delay$11 $0\ren_delay$11[0:0]$5676 - end - attribute \src "libresoc.v:137373.7-137373.28" - process $proc$libresoc.v:137373$5677 assign { } { } - assign $0\ren_delay$12[0:0]$5678 1'0 - sync always - sync init - update \ren_delay$12 $0\ren_delay$12[0:0]$5678 - end - attribute \src "libresoc.v:137377.7-137377.28" - process $proc$libresoc.v:137377$5679 assign { } { } - assign $0\ren_delay$13[0:0]$5680 1'0 - sync always - sync init - update \ren_delay$13 $0\ren_delay$13[0:0]$5680 - end - attribute \src "libresoc.v:137403.3-137404.43" - process $proc$libresoc.v:137403$5600 assign { } { } - assign $0\ren_delay$13[0:0]$5601 \ren_delay$13$next - sync posedge \coresync_clk - update \ren_delay$13 $0\ren_delay$13[0:0]$5601 - end - attribute \src "libresoc.v:137405.3-137406.43" - process $proc$libresoc.v:137405$5602 assign { } { } - assign $0\ren_delay$12[0:0]$5603 \ren_delay$12$next - sync posedge \coresync_clk - update \ren_delay$12 $0\ren_delay$12[0:0]$5603 - end - attribute \src "libresoc.v:137407.3-137408.43" - process $proc$libresoc.v:137407$5604 assign { } { } - assign $0\ren_delay$11[0:0]$5605 \ren_delay$11$next + assign $0\_0_[4:0] \memory_r_addr + assign $0\_1_[4:0] \memory_r_addr$2 + assign $0$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5580 $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 + assign $0$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5581 $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 + assign $0$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5582 $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 + attribute \src "libresoc.v:137996.5-137996.61" + switch \memory_w_en + attribute \src "libresoc.v:137996.9-137996.20" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 \memory_w_addr + assign $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 \memory_w_data + assign $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 64'1111111111111111111111111111111111111111111111111111111111111111 + case + assign $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 5'xxxxx + assign $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 64'0000000000000000000000000000000000000000000000000000000000000000 + end sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[0:0]$5605 + update \_0_ $0\_0_[4:0] + update \_1_ $0\_1_[4:0] + update $memwr$\memory$libresoc.v:137996$5578_ADDR $0$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5580 + update $memwr$\memory$libresoc.v:137996$5578_DATA $0$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5581 + update $memwr$\memory$libresoc.v:137996$5578_EN $0$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5582 + attribute \src "libresoc.v:137996.22-137996.60" + memwr \memory $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 0' end - attribute \src "libresoc.v:137409.3-137410.43" - process $proc$libresoc.v:137409$5606 + attribute \src "libresoc.v:138000.3-138001.41" + process $proc$libresoc.v:138000$5588 assign { } { } - assign $0\ren_delay$10[0:0]$5607 \ren_delay$10$next + assign $0\ren_delay$4[0:0]$5589 \ren_delay$4$next sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5607 + update \ren_delay$4 $0\ren_delay$4[0:0]$5589 end - attribute \src "libresoc.v:137411.3-137412.35" - process $proc$libresoc.v:137411$5608 + attribute \src "libresoc.v:138002.3-138003.35" + process $proc$libresoc.v:138002$5590 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:137453.3-137460.6" - process $proc$libresoc.v:137453$5609 - assign { } { } + attribute \src "libresoc.v:138004.3-138012.6" + process $proc$libresoc.v:138004$5591 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 5'xxxxx - assign $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\_0_[4:0] \src1__addr - assign $0\_1_[4:0] \src2__addr - assign $0\_2_[4:0] \src3__addr - assign $0\_3_[4:0] 5'00000 - assign $0\_4_[4:0] \dmi__addr - attribute \src "libresoc.v:137459.5-137459.58" - switch \dest1__wen - attribute \src "libresoc.v:137459.9-137459.19" + assign $0\ren_delay$next[0:0]$5592 $1\ren_delay$next[0:0]$5593 + attribute \src "libresoc.v:138005.5-138005.29" + switch \initial + attribute \src "libresoc.v:138005.9-138005.17" case 1'1 - assign $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 \dest1__addr - assign $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 64'1111111111111111111111111111111111111111111111111111111111111111 case end - sync posedge \coresync_clk - update \_0_ $0\_0_[4:0] - update \_1_ $0\_1_[4:0] - update \_2_ $0\_2_[4:0] - update \_3_ $0\_3_[4:0] - update \_4_ $0\_4_[4:0] - update $memwr$\memory$libresoc.v:137459$5599_ADDR $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 - update $memwr$\memory$libresoc.v:137459$5599_DATA $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 - update $memwr$\memory$libresoc.v:137459$5599_EN $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$5593 1'0 + case + assign $1\ren_delay$next[0:0]$5593 \dmi__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$5592 end - attribute \src "libresoc.v:137466.3-137474.6" - process $proc$libresoc.v:137466$5618 + attribute \src "libresoc.v:138013.3-138022.6" + process $proc$libresoc.v:138013$5594 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$5619 $1\ren_delay$next[0:0]$5620 - attribute \src "libresoc.v:137467.5-137467.29" + assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] + attribute \src "libresoc.v:138014.5-138014.29" switch \initial - attribute \src "libresoc.v:137467.9-137467.17" + attribute \src "libresoc.v:138014.9-138014.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$5620 1'0 + assign $1\dmi__data_o[63:0] \memory_r_data case - assign $1\ren_delay$next[0:0]$5620 \src1__ren + assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5619 + update \dmi__data_o $0\dmi__data_o[63:0] end - attribute \src "libresoc.v:137475.3-137483.6" - process $proc$libresoc.v:137475$5621 + attribute \src "libresoc.v:138023.3-138031.6" + process $proc$libresoc.v:138023$5595 assign { } { } assign { } { } - assign $0\ren_delay$12$next[0:0]$5622 $1\ren_delay$12$next[0:0]$5623 - attribute \src "libresoc.v:137476.5-137476.29" + assign $0\ren_delay$4$next[0:0]$5596 $1\ren_delay$4$next[0:0]$5597 + attribute \src "libresoc.v:138024.5-138024.29" switch \initial - attribute \src "libresoc.v:137476.9-137476.17" + attribute \src "libresoc.v:138024.9-138024.17" case 1'1 case end @@ -217300,1128 +217280,915 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$12$next[0:0]$5623 1'0 + assign $1\ren_delay$4$next[0:0]$5597 1'0 case - assign $1\ren_delay$12$next[0:0]$5623 \pred__ren + assign $1\ren_delay$4$next[0:0]$5597 \src__ren end sync always - update \ren_delay$12$next $0\ren_delay$12$next[0:0]$5622 + update \ren_delay$4$next $0\ren_delay$4$next[0:0]$5596 end - attribute \src "libresoc.v:137484.3-137493.6" - process $proc$libresoc.v:137484$5624 + attribute \src "libresoc.v:138032.3-138041.6" + process $proc$libresoc.v:138032$5598 assign { } { } assign { } { } - assign $0\pred__data_o[63:0] $1\pred__data_o[63:0] - attribute \src "libresoc.v:137485.5-137485.29" + assign $0\src__data_o[63:0] $1\src__data_o[63:0] + attribute \src "libresoc.v:138033.5-138033.29" switch \initial - attribute \src "libresoc.v:137485.9-137485.17" + attribute \src "libresoc.v:138033.9-138033.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$12 + switch \ren_delay$4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\pred__data_o[63:0] \memory_r_data$7 + assign $1\src__data_o[63:0] \memory_r_data$3 case - assign $1\pred__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\src__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \pred__data_o $0\pred__data_o[63:0] + update \src__data_o $0\src__data_o[63:0] end - attribute \src "libresoc.v:137494.3-137502.6" - process $proc$libresoc.v:137494$5625 - assign { } { } - assign { } { } - assign $0\ren_delay$13$next[0:0]$5626 $1\ren_delay$13$next[0:0]$5627 - attribute \src "libresoc.v:137495.5-137495.29" - switch \initial - attribute \src "libresoc.v:137495.9-137495.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$13$next[0:0]$5627 1'0 - case - assign $1\ren_delay$13$next[0:0]$5627 \dmi__ren - end - sync always - update \ren_delay$13$next $0\ren_delay$13$next[0:0]$5626 - end - attribute \src "libresoc.v:137503.3-137512.6" - process $proc$libresoc.v:137503$5628 - assign { } { } - assign { } { } - assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] - attribute \src "libresoc.v:137504.5-137504.29" - switch \initial - attribute \src "libresoc.v:137504.9-137504.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$13 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi__data_o[63:0] \memory_r_data$9 - case - assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dmi__data_o $0\dmi__data_o[63:0] - end - attribute \src "libresoc.v:137513.3-137522.6" - process $proc$libresoc.v:137513$5629 - assign { } { } - assign { } { } - assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:137514.5-137514.29" - switch \initial - attribute \src "libresoc.v:137514.9-137514.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src1__data_o[63:0] \memory_r_data - case - assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src1__data_o $0\src1__data_o[63:0] - end - attribute \src "libresoc.v:137523.3-137531.6" - process $proc$libresoc.v:137523$5630 - assign { } { } - assign { } { } - assign $0\ren_delay$10$next[0:0]$5631 $1\ren_delay$10$next[0:0]$5632 - attribute \src "libresoc.v:137524.5-137524.29" - switch \initial - attribute \src "libresoc.v:137524.9-137524.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$10$next[0:0]$5632 1'0 - case - assign $1\ren_delay$10$next[0:0]$5632 \src2__ren - end - sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5631 - end - attribute \src "libresoc.v:137532.3-137541.6" - process $proc$libresoc.v:137532$5633 - assign { } { } - assign { } { } - assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:137533.5-137533.29" - switch \initial - attribute \src "libresoc.v:137533.9-137533.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$10 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src2__data_o[63:0] \memory_r_data$3 - case - assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src2__data_o $0\src2__data_o[63:0] - end - attribute \src "libresoc.v:137542.3-137550.6" - process $proc$libresoc.v:137542$5634 - assign { } { } - assign { } { } - assign $0\ren_delay$11$next[0:0]$5635 $1\ren_delay$11$next[0:0]$5636 - attribute \src "libresoc.v:137543.5-137543.29" - switch \initial - attribute \src "libresoc.v:137543.9-137543.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$11$next[0:0]$5636 1'0 - case - assign $1\ren_delay$11$next[0:0]$5636 \src3__ren - end - sync always - update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5635 - end - attribute \src "libresoc.v:137551.3-137560.6" - process $proc$libresoc.v:137551$5637 - assign { } { } - assign { } { } - assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] - attribute \src "libresoc.v:137552.5-137552.29" - switch \initial - attribute \src "libresoc.v:137552.9-137552.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$11 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src3__data_o[63:0] \memory_r_data$5 - case - assign $1\src3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src3__data_o $0\src3__data_o[63:0] - end - connect \memory_r_data $memrd$\memory$libresoc.v:137461$5613_DATA - connect \memory_r_data$3 $memrd$\memory$libresoc.v:137462$5614_DATA - connect \memory_r_data$5 $memrd$\memory$libresoc.v:137463$5615_DATA - connect \memory_r_data$7 $memrd$\memory$libresoc.v:137464$5616_DATA - connect \memory_r_data$9 $memrd$\memory$libresoc.v:137465$5617_DATA - connect \pred__addr 5'00000 - connect \pred__ren 1'0 + connect \memory_r_data $memrd$\memory$libresoc.v:137998$5586_DATA + connect \memory_r_data$3 $memrd$\memory$libresoc.v:137999$5587_DATA connect \memory_w_data \dest1__data_i connect \memory_w_en \dest1__wen connect \memory_w_addr \dest1__addr - connect \memory_r_addr$8 \dmi__addr - connect \memory_r_addr$6 5'00000 - connect \memory_r_addr$4 \src3__addr - connect \memory_r_addr$2 \src2__addr - connect \memory_r_addr \src1__addr + connect \memory_r_addr$2 \src__addr + connect \memory_r_addr \dmi__addr end -attribute \src "libresoc.v:137575.1-140282.10" +attribute \src "libresoc.v:138051.1-140622.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag" attribute \generator "nMigen" module \jtag - attribute \src "libresoc.v:139714.3-139740.6" + attribute \src "libresoc.v:140036.3-140062.6" wire $0\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:139362.3-139377.6" + attribute \src "libresoc.v:139684.3-139699.6" wire $0\TAP_tdo[0:0] - attribute \src "libresoc.v:139875.3-139907.6" - wire width 4 $0\dmi0__addr_i$next[3:0]$6091 - attribute \src "libresoc.v:139265.3-139266.41" + attribute \src "libresoc.v:140217.3-140261.6" + wire width 4 $0\dmi0__addr_i$next[3:0]$6023 + attribute \src "libresoc.v:139587.3-139588.41" wire width 4 $0\dmi0__addr_i[3:0] - attribute \src "libresoc.v:139961.3-139987.6" - wire width 64 $0\dmi0__din$next[63:0]$6104 - attribute \src "libresoc.v:139261.3-139262.35" + attribute \src "libresoc.v:140315.3-140341.6" + wire width 64 $0\dmi0__din$next[63:0]$6036 + attribute \src "libresoc.v:139583.3-139584.35" wire width 64 $0\dmi0__din[63:0] - attribute \src "libresoc.v:139564.3-139580.6" - wire $0\dmi0_addrsr__oe$next[0:0]$6028 - attribute \src "libresoc.v:139293.3-139294.47" + attribute \src "libresoc.v:139886.3-139902.6" + wire $0\dmi0_addrsr__oe$next[0:0]$5960 + attribute \src "libresoc.v:139615.3-139616.47" wire $0\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:139581.3-139601.6" - wire width 8 $0\dmi0_addrsr_reg$next[7:0]$6032 - attribute \src "libresoc.v:139291.3-139292.47" + attribute \src "libresoc.v:139903.3-139923.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5964 + attribute \src "libresoc.v:139613.3-139614.47" wire width 8 $0\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:139546.3-139554.6" - wire $0\dmi0_addrsr_update_core$next[0:0]$6022 - attribute \src "libresoc.v:139297.3-139298.63" + attribute \src "libresoc.v:139868.3-139876.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$5954 + attribute \src "libresoc.v:139619.3-139620.63" wire $0\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:139555.3-139563.6" - wire $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 - attribute \src "libresoc.v:139295.3-139296.73" + attribute \src "libresoc.v:139877.3-139885.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5957 + attribute \src "libresoc.v:139617.3-139618.73" wire $0\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:139988.3-140008.6" - wire width 64 $0\dmi0_datasr__i$next[63:0]$6109 - attribute \src "libresoc.v:139259.3-139260.45" + attribute \src "libresoc.v:140342.3-140370.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$6041 + attribute \src "libresoc.v:139581.3-139582.45" wire width 64 $0\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:139620.3-139636.6" - wire width 2 $0\dmi0_datasr__oe$next[1:0]$6043 - attribute \src "libresoc.v:139285.3-139286.47" + attribute \src "libresoc.v:139942.3-139958.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$5975 + attribute \src "libresoc.v:139607.3-139608.47" wire width 2 $0\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:139637.3-139657.6" - wire width 64 $0\dmi0_datasr_reg$next[63:0]$6047 - attribute \src "libresoc.v:139283.3-139284.47" + attribute \src "libresoc.v:139959.3-139979.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$5979 + attribute \src "libresoc.v:139605.3-139606.47" wire width 64 $0\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:139602.3-139610.6" - wire $0\dmi0_datasr_update_core$next[0:0]$6037 - attribute \src "libresoc.v:139289.3-139290.63" + attribute \src "libresoc.v:139924.3-139932.6" + wire $0\dmi0_datasr_update_core$next[0:0]$5969 + attribute \src "libresoc.v:139611.3-139612.63" wire $0\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:139611.3-139619.6" - wire $0\dmi0_datasr_update_core_prev$next[0:0]$6040 - attribute \src "libresoc.v:139287.3-139288.73" + attribute \src "libresoc.v:139933.3-139941.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$5972 + attribute \src "libresoc.v:139609.3-139610.73" wire $0\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:139908.3-139960.6" - wire width 3 $0\fsm_state$499$next[2:0]$6097 - attribute \src "libresoc.v:139263.3-139264.45" - wire width 3 $0\fsm_state$499[2:0]$5943 - attribute \src "libresoc.v:138217.13-138217.35" - wire width 3 $0\fsm_state$499[2:0]$6146 - attribute \src "libresoc.v:139774.3-139826.6" - wire width 3 $0\fsm_state$next[2:0]$6074 - attribute \src "libresoc.v:139271.3-139272.35" + attribute \src "libresoc.v:140262.3-140314.6" + wire width 3 $0\fsm_state$455$next[2:0]$6029 + attribute \src "libresoc.v:139585.3-139586.45" + wire width 3 $0\fsm_state$455[2:0]$5875 + attribute \src "libresoc.v:138649.13-138649.35" + wire width 3 $0\fsm_state$455[2:0]$6078 + attribute \src "libresoc.v:140108.3-140160.6" + wire width 3 $0\fsm_state$next[2:0]$6006 + attribute \src "libresoc.v:139593.3-139594.35" wire width 3 $0\fsm_state[2:0] - attribute \src "libresoc.v:137576.7-137576.20" + attribute \src "libresoc.v:138052.7-138052.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140058.3-140078.6" - wire width 152 $0\io_bd$next[151:0]$6129 - attribute \src "libresoc.v:139323.3-139324.27" - wire width 152 $0\io_bd[151:0] - attribute \src "libresoc.v:140040.3-140057.6" - wire width 152 $0\io_sr$next[151:0]$6125 - attribute \src "libresoc.v:139325.3-139326.27" - wire width 152 $0\io_sr[151:0] - attribute \src "libresoc.v:139741.3-139773.6" - wire width 29 $0\jtag_wb__adr$next[28:0]$6068 - attribute \src "libresoc.v:139273.3-139274.41" + attribute \src "libresoc.v:140420.3-140440.6" + wire width 130 $0\io_bd$next[129:0]$6061 + attribute \src "libresoc.v:139645.3-139646.27" + wire width 130 $0\io_bd[129:0] + attribute \src "libresoc.v:140402.3-140419.6" + wire width 130 $0\io_sr$next[129:0]$6057 + attribute \src "libresoc.v:139647.3-139648.27" + wire width 130 $0\io_sr[129:0] + attribute \src "libresoc.v:140063.3-140107.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$6000 + attribute \src "libresoc.v:139595.3-139596.41" wire width 29 $0\jtag_wb__adr[28:0] - attribute \src "libresoc.v:139827.3-139853.6" - wire width 64 $0\jtag_wb__dat_w$next[63:0]$6081 - attribute \src "libresoc.v:139269.3-139270.45" + attribute \src "libresoc.v:140161.3-140187.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$6013 + attribute \src "libresoc.v:139591.3-139592.45" wire width 64 $0\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:139452.3-139468.6" - wire $0\jtag_wb_addrsr__oe$next[0:0]$5998 - attribute \src "libresoc.v:139309.3-139310.53" + attribute \src "libresoc.v:139774.3-139790.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$5930 + attribute \src "libresoc.v:139631.3-139632.53" wire $0\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:139469.3-139489.6" - wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$6002 - attribute \src "libresoc.v:139307.3-139308.53" + attribute \src "libresoc.v:139791.3-139811.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5934 + attribute \src "libresoc.v:139629.3-139630.53" wire width 29 $0\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:139434.3-139442.6" - wire $0\jtag_wb_addrsr_update_core$next[0:0]$5992 - attribute \src "libresoc.v:139313.3-139314.69" + attribute \src "libresoc.v:139756.3-139764.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$5924 + attribute \src "libresoc.v:139635.3-139636.69" wire $0\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:139443.3-139451.6" - wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 - attribute \src "libresoc.v:139311.3-139312.79" + attribute \src "libresoc.v:139765.3-139773.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5927 + attribute \src "libresoc.v:139633.3-139634.79" wire $0\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:139854.3-139874.6" - wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6086 - attribute \src "libresoc.v:139267.3-139268.51" + attribute \src "libresoc.v:140188.3-140216.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6018 + attribute \src "libresoc.v:139589.3-139590.51" wire width 64 $0\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:139508.3-139524.6" - wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$6013 - attribute \src "libresoc.v:139301.3-139302.53" + attribute \src "libresoc.v:139830.3-139846.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5945 + attribute \src "libresoc.v:139623.3-139624.53" wire width 2 $0\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:139525.3-139545.6" - wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$6017 - attribute \src "libresoc.v:139299.3-139300.53" + attribute \src "libresoc.v:139847.3-139867.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5949 + attribute \src "libresoc.v:139621.3-139622.53" wire width 64 $0\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:139490.3-139498.6" - wire $0\jtag_wb_datasr_update_core$next[0:0]$6007 - attribute \src "libresoc.v:139305.3-139306.69" + attribute \src "libresoc.v:139812.3-139820.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$5939 + attribute \src "libresoc.v:139627.3-139628.69" wire $0\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:139499.3-139507.6" - wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 - attribute \src "libresoc.v:139303.3-139304.79" + attribute \src "libresoc.v:139821.3-139829.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5942 + attribute \src "libresoc.v:139625.3-139626.79" wire $0\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:139396.3-139412.6" - wire $0\sr0__oe$next[0:0]$5983 - attribute \src "libresoc.v:139317.3-139318.31" + attribute \src "libresoc.v:139718.3-139734.6" + wire $0\sr0__oe$next[0:0]$5915 + attribute \src "libresoc.v:139639.3-139640.31" wire $0\sr0__oe[0:0] - attribute \src "libresoc.v:139413.3-139433.6" - wire width 3 $0\sr0_reg$next[2:0]$5987 - attribute \src "libresoc.v:139315.3-139316.31" + attribute \src "libresoc.v:139735.3-139755.6" + wire width 3 $0\sr0_reg$next[2:0]$5919 + attribute \src "libresoc.v:139637.3-139638.31" wire width 3 $0\sr0_reg[2:0] - attribute \src "libresoc.v:139378.3-139386.6" - wire $0\sr0_update_core$next[0:0]$5977 - attribute \src "libresoc.v:139321.3-139322.47" + attribute \src "libresoc.v:139700.3-139708.6" + wire $0\sr0_update_core$next[0:0]$5909 + attribute \src "libresoc.v:139643.3-139644.47" wire $0\sr0_update_core[0:0] - attribute \src "libresoc.v:139387.3-139395.6" - wire $0\sr0_update_core_prev$next[0:0]$5980 - attribute \src "libresoc.v:139319.3-139320.57" + attribute \src "libresoc.v:139709.3-139717.6" + wire $0\sr0_update_core_prev$next[0:0]$5912 + attribute \src "libresoc.v:139641.3-139642.57" wire $0\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:140030.3-140039.6" + attribute \src "libresoc.v:140392.3-140401.6" wire width 3 $0\sr5__i[2:0] - attribute \src "libresoc.v:139676.3-139692.6" - wire $0\sr5__oe$next[0:0]$6058 - attribute \src "libresoc.v:139277.3-139278.31" + attribute \src "libresoc.v:139998.3-140014.6" + wire $0\sr5__oe$next[0:0]$5990 + attribute \src "libresoc.v:139599.3-139600.31" wire $0\sr5__oe[0:0] - attribute \src "libresoc.v:139693.3-139713.6" - wire width 3 $0\sr5_reg$next[2:0]$6062 - attribute \src "libresoc.v:139275.3-139276.31" + attribute \src "libresoc.v:140015.3-140035.6" + wire width 3 $0\sr5_reg$next[2:0]$5994 + attribute \src "libresoc.v:139597.3-139598.31" wire width 3 $0\sr5_reg[2:0] - attribute \src "libresoc.v:139658.3-139666.6" - wire $0\sr5_update_core$next[0:0]$6052 - attribute \src "libresoc.v:139281.3-139282.47" + attribute \src "libresoc.v:139980.3-139988.6" + wire $0\sr5_update_core$next[0:0]$5984 + attribute \src "libresoc.v:139603.3-139604.47" wire $0\sr5_update_core[0:0] - attribute \src "libresoc.v:139667.3-139675.6" - wire $0\sr5_update_core_prev$next[0:0]$6055 - attribute \src "libresoc.v:139279.3-139280.57" + attribute \src "libresoc.v:139989.3-139997.6" + wire $0\sr5_update_core_prev$next[0:0]$5987 + attribute \src "libresoc.v:139601.3-139602.57" wire $0\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:140009.3-140029.6" - wire $0\wb_dcache_en$next[0:0]$6114 - attribute \src "libresoc.v:139255.3-139256.41" + attribute \src "libresoc.v:140371.3-140391.6" + wire $0\wb_dcache_en$next[0:0]$6046 + attribute \src "libresoc.v:139577.3-139578.41" wire $0\wb_dcache_en[0:0] - attribute \src "libresoc.v:140009.3-140029.6" - wire $0\wb_icache_en$next[0:0]$6115 - attribute \src "libresoc.v:139253.3-139254.41" + attribute \src "libresoc.v:140371.3-140391.6" + wire $0\wb_icache_en$next[0:0]$6047 + attribute \src "libresoc.v:139575.3-139576.41" wire $0\wb_icache_en[0:0] - attribute \src "libresoc.v:140009.3-140029.6" - wire $0\wb_sram_en$next[0:0]$6116 - attribute \src "libresoc.v:139257.3-139258.37" + attribute \src "libresoc.v:140371.3-140391.6" + wire $0\wb_sram_en$next[0:0]$6048 + attribute \src "libresoc.v:139579.3-139580.37" wire $0\wb_sram_en[0:0] - attribute \src "libresoc.v:139714.3-139740.6" + attribute \src "libresoc.v:140036.3-140062.6" wire $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:139362.3-139377.6" + attribute \src "libresoc.v:139684.3-139699.6" wire $1\TAP_tdo[0:0] - attribute \src "libresoc.v:139875.3-139907.6" - wire width 4 $1\dmi0__addr_i$next[3:0]$6092 - attribute \src "libresoc.v:138130.13-138130.32" + attribute \src "libresoc.v:140217.3-140261.6" + wire width 4 $1\dmi0__addr_i$next[3:0]$6024 + attribute \src "libresoc.v:138562.13-138562.32" wire width 4 $1\dmi0__addr_i[3:0] - attribute \src "libresoc.v:139961.3-139987.6" - wire width 64 $1\dmi0__din$next[63:0]$6105 - attribute \src "libresoc.v:138135.14-138135.46" + attribute \src "libresoc.v:140315.3-140341.6" + wire width 64 $1\dmi0__din$next[63:0]$6037 + attribute \src "libresoc.v:138567.14-138567.46" wire width 64 $1\dmi0__din[63:0] - attribute \src "libresoc.v:139564.3-139580.6" - wire $1\dmi0_addrsr__oe$next[0:0]$6029 - attribute \src "libresoc.v:138149.7-138149.29" + attribute \src "libresoc.v:139886.3-139902.6" + wire $1\dmi0_addrsr__oe$next[0:0]$5961 + attribute \src "libresoc.v:138581.7-138581.29" wire $1\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:139581.3-139601.6" - wire width 8 $1\dmi0_addrsr_reg$next[7:0]$6033 - attribute \src "libresoc.v:138157.13-138157.36" + attribute \src "libresoc.v:139903.3-139923.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5965 + attribute \src "libresoc.v:138589.13-138589.36" wire width 8 $1\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:139546.3-139554.6" - wire $1\dmi0_addrsr_update_core$next[0:0]$6023 - attribute \src "libresoc.v:138165.7-138165.37" + attribute \src "libresoc.v:139868.3-139876.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$5955 + attribute \src "libresoc.v:138597.7-138597.37" wire $1\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:139555.3-139563.6" - wire $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 - attribute \src "libresoc.v:138169.7-138169.42" + attribute \src "libresoc.v:139877.3-139885.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5958 + attribute \src "libresoc.v:138601.7-138601.42" wire $1\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:139988.3-140008.6" - wire width 64 $1\dmi0_datasr__i$next[63:0]$6110 - attribute \src "libresoc.v:138173.14-138173.51" + attribute \src "libresoc.v:140342.3-140370.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$6042 + attribute \src "libresoc.v:138605.14-138605.51" wire width 64 $1\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:139620.3-139636.6" - wire width 2 $1\dmi0_datasr__oe$next[1:0]$6044 - attribute \src "libresoc.v:138179.13-138179.35" + attribute \src "libresoc.v:139942.3-139958.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$5976 + attribute \src "libresoc.v:138611.13-138611.35" wire width 2 $1\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:139637.3-139657.6" - wire width 64 $1\dmi0_datasr_reg$next[63:0]$6048 - attribute \src "libresoc.v:138187.14-138187.52" + attribute \src "libresoc.v:139959.3-139979.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$5980 + attribute \src "libresoc.v:138619.14-138619.52" wire width 64 $1\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:139602.3-139610.6" - wire $1\dmi0_datasr_update_core$next[0:0]$6038 - attribute \src "libresoc.v:138195.7-138195.37" + attribute \src "libresoc.v:139924.3-139932.6" + wire $1\dmi0_datasr_update_core$next[0:0]$5970 + attribute \src "libresoc.v:138627.7-138627.37" wire $1\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:139611.3-139619.6" - wire $1\dmi0_datasr_update_core_prev$next[0:0]$6041 - attribute \src "libresoc.v:138199.7-138199.42" + attribute \src "libresoc.v:139933.3-139941.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$5973 + attribute \src "libresoc.v:138631.7-138631.42" wire $1\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:139908.3-139960.6" - wire width 3 $1\fsm_state$499$next[2:0]$6098 - attribute \src "libresoc.v:139774.3-139826.6" - wire width 3 $1\fsm_state$next[2:0]$6075 - attribute \src "libresoc.v:138215.13-138215.29" + attribute \src "libresoc.v:140262.3-140314.6" + wire width 3 $1\fsm_state$455$next[2:0]$6030 + attribute \src "libresoc.v:140108.3-140160.6" + wire width 3 $1\fsm_state$next[2:0]$6007 + attribute \src "libresoc.v:138647.13-138647.29" wire width 3 $1\fsm_state[2:0] - attribute \src "libresoc.v:140058.3-140078.6" - wire width 152 $1\io_bd$next[151:0]$6130 - attribute \src "libresoc.v:138415.15-138415.66" - wire width 152 $1\io_bd[151:0] - attribute \src "libresoc.v:140040.3-140057.6" - wire width 152 $1\io_sr$next[151:0]$6126 - attribute \src "libresoc.v:138427.15-138427.66" - wire width 152 $1\io_sr[151:0] - attribute \src "libresoc.v:139741.3-139773.6" - wire width 29 $1\jtag_wb__adr$next[28:0]$6069 - attribute \src "libresoc.v:138436.14-138436.41" + attribute \src "libresoc.v:140420.3-140440.6" + wire width 130 $1\io_bd$next[129:0]$6062 + attribute \src "libresoc.v:138847.15-138847.61" + wire width 130 $1\io_bd[129:0] + attribute \src "libresoc.v:140402.3-140419.6" + wire width 130 $1\io_sr$next[129:0]$6058 + attribute \src "libresoc.v:138859.15-138859.61" + wire width 130 $1\io_sr[129:0] + attribute \src "libresoc.v:140063.3-140107.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$6001 + attribute \src "libresoc.v:138868.14-138868.41" wire width 29 $1\jtag_wb__adr[28:0] - attribute \src "libresoc.v:139827.3-139853.6" - wire width 64 $1\jtag_wb__dat_w$next[63:0]$6082 - attribute \src "libresoc.v:138445.14-138445.51" + attribute \src "libresoc.v:140161.3-140187.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$6014 + attribute \src "libresoc.v:138877.14-138877.51" wire width 64 $1\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:139452.3-139468.6" - wire $1\jtag_wb_addrsr__oe$next[0:0]$5999 - attribute \src "libresoc.v:138459.7-138459.32" + attribute \src "libresoc.v:139774.3-139790.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$5931 + attribute \src "libresoc.v:138891.7-138891.32" wire $1\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:139469.3-139489.6" - wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$6003 - attribute \src "libresoc.v:138467.14-138467.47" + attribute \src "libresoc.v:139791.3-139811.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5935 + attribute \src "libresoc.v:138899.14-138899.47" wire width 29 $1\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:139434.3-139442.6" - wire $1\jtag_wb_addrsr_update_core$next[0:0]$5993 - attribute \src "libresoc.v:138475.7-138475.40" + attribute \src "libresoc.v:139756.3-139764.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$5925 + attribute \src "libresoc.v:138907.7-138907.40" wire $1\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:139443.3-139451.6" - wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 - attribute \src "libresoc.v:138479.7-138479.45" + attribute \src "libresoc.v:139765.3-139773.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5928 + attribute \src "libresoc.v:138911.7-138911.45" wire $1\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:139854.3-139874.6" - wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6087 - attribute \src "libresoc.v:138483.14-138483.54" + attribute \src "libresoc.v:140188.3-140216.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6019 + attribute \src "libresoc.v:138915.14-138915.54" wire width 64 $1\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:139508.3-139524.6" - wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$6014 - attribute \src "libresoc.v:138489.13-138489.38" + attribute \src "libresoc.v:139830.3-139846.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5946 + attribute \src "libresoc.v:138921.13-138921.38" wire width 2 $1\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:139525.3-139545.6" - wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$6018 - attribute \src "libresoc.v:138497.14-138497.55" + attribute \src "libresoc.v:139847.3-139867.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5950 + attribute \src "libresoc.v:138929.14-138929.55" wire width 64 $1\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:139490.3-139498.6" - wire $1\jtag_wb_datasr_update_core$next[0:0]$6008 - attribute \src "libresoc.v:138505.7-138505.40" + attribute \src "libresoc.v:139812.3-139820.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$5940 + attribute \src "libresoc.v:138937.7-138937.40" wire $1\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:139499.3-139507.6" - wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 - attribute \src "libresoc.v:138509.7-138509.45" + attribute \src "libresoc.v:139821.3-139829.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5943 + attribute \src "libresoc.v:138941.7-138941.45" wire $1\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:139396.3-139412.6" - wire $1\sr0__oe$next[0:0]$5984 - attribute \src "libresoc.v:138931.7-138931.21" + attribute \src "libresoc.v:139718.3-139734.6" + wire $1\sr0__oe$next[0:0]$5916 + attribute \src "libresoc.v:139275.7-139275.21" wire $1\sr0__oe[0:0] - attribute \src "libresoc.v:139413.3-139433.6" - wire width 3 $1\sr0_reg$next[2:0]$5988 - attribute \src "libresoc.v:138939.13-138939.27" + attribute \src "libresoc.v:139735.3-139755.6" + wire width 3 $1\sr0_reg$next[2:0]$5920 + attribute \src "libresoc.v:139283.13-139283.27" wire width 3 $1\sr0_reg[2:0] - attribute \src "libresoc.v:139378.3-139386.6" - wire $1\sr0_update_core$next[0:0]$5978 - attribute \src "libresoc.v:138947.7-138947.29" + attribute \src "libresoc.v:139700.3-139708.6" + wire $1\sr0_update_core$next[0:0]$5910 + attribute \src "libresoc.v:139291.7-139291.29" wire $1\sr0_update_core[0:0] - attribute \src "libresoc.v:139387.3-139395.6" - wire $1\sr0_update_core_prev$next[0:0]$5981 - attribute \src "libresoc.v:138951.7-138951.34" + attribute \src "libresoc.v:139709.3-139717.6" + wire $1\sr0_update_core_prev$next[0:0]$5913 + attribute \src "libresoc.v:139295.7-139295.34" wire $1\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:140030.3-140039.6" + attribute \src "libresoc.v:140392.3-140401.6" wire width 3 $1\sr5__i[2:0] - attribute \src "libresoc.v:139676.3-139692.6" - wire $1\sr5__oe$next[0:0]$6059 - attribute \src "libresoc.v:138961.7-138961.21" + attribute \src "libresoc.v:139998.3-140014.6" + wire $1\sr5__oe$next[0:0]$5991 + attribute \src "libresoc.v:139305.7-139305.21" wire $1\sr5__oe[0:0] - attribute \src "libresoc.v:139693.3-139713.6" - wire width 3 $1\sr5_reg$next[2:0]$6063 - attribute \src "libresoc.v:138969.13-138969.27" + attribute \src "libresoc.v:140015.3-140035.6" + wire width 3 $1\sr5_reg$next[2:0]$5995 + attribute \src "libresoc.v:139313.13-139313.27" wire width 3 $1\sr5_reg[2:0] - attribute \src "libresoc.v:139658.3-139666.6" - wire $1\sr5_update_core$next[0:0]$6053 - attribute \src "libresoc.v:138977.7-138977.29" + attribute \src "libresoc.v:139980.3-139988.6" + wire $1\sr5_update_core$next[0:0]$5985 + attribute \src "libresoc.v:139321.7-139321.29" wire $1\sr5_update_core[0:0] - attribute \src "libresoc.v:139667.3-139675.6" - wire $1\sr5_update_core_prev$next[0:0]$6056 - attribute \src "libresoc.v:138981.7-138981.34" + attribute \src "libresoc.v:139989.3-139997.6" + wire $1\sr5_update_core_prev$next[0:0]$5988 + attribute \src "libresoc.v:139325.7-139325.34" wire $1\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:140009.3-140029.6" - wire $1\wb_dcache_en$next[0:0]$6117 - attribute \src "libresoc.v:138986.7-138986.26" + attribute \src "libresoc.v:140371.3-140391.6" + wire $1\wb_dcache_en$next[0:0]$6049 + attribute \src "libresoc.v:139330.7-139330.26" wire $1\wb_dcache_en[0:0] - attribute \src "libresoc.v:140009.3-140029.6" - wire $1\wb_icache_en$next[0:0]$6118 - attribute \src "libresoc.v:138991.7-138991.26" + attribute \src "libresoc.v:140371.3-140391.6" + wire $1\wb_icache_en$next[0:0]$6050 + attribute \src "libresoc.v:139335.7-139335.26" wire $1\wb_icache_en[0:0] - attribute \src "libresoc.v:140009.3-140029.6" - wire $1\wb_sram_en$next[0:0]$6119 - attribute \src "libresoc.v:138996.7-138996.24" + attribute \src "libresoc.v:140371.3-140391.6" + wire $1\wb_sram_en$next[0:0]$6051 + attribute \src "libresoc.v:139340.7-139340.24" wire $1\wb_sram_en[0:0] - attribute \src "libresoc.v:139875.3-139907.6" - wire width 4 $2\dmi0__addr_i$next[3:0]$6093 - attribute \src "libresoc.v:139961.3-139987.6" - wire width 64 $2\dmi0__din$next[63:0]$6106 - attribute \src "libresoc.v:139564.3-139580.6" - wire $2\dmi0_addrsr__oe$next[0:0]$6030 - attribute \src "libresoc.v:139581.3-139601.6" - wire width 8 $2\dmi0_addrsr_reg$next[7:0]$6034 - attribute \src "libresoc.v:139988.3-140008.6" - wire width 64 $2\dmi0_datasr__i$next[63:0]$6111 - attribute \src "libresoc.v:139620.3-139636.6" - wire width 2 $2\dmi0_datasr__oe$next[1:0]$6045 - attribute \src "libresoc.v:139637.3-139657.6" - wire width 64 $2\dmi0_datasr_reg$next[63:0]$6049 - attribute \src "libresoc.v:139908.3-139960.6" - wire width 3 $2\fsm_state$499$next[2:0]$6099 - attribute \src "libresoc.v:139774.3-139826.6" - wire width 3 $2\fsm_state$next[2:0]$6076 - attribute \src "libresoc.v:140058.3-140078.6" - wire width 152 $2\io_bd$next[151:0]$6131 - attribute \src "libresoc.v:140040.3-140057.6" - wire width 152 $2\io_sr$next[151:0]$6127 - attribute \src "libresoc.v:139741.3-139773.6" - wire width 29 $2\jtag_wb__adr$next[28:0]$6070 - attribute \src "libresoc.v:139827.3-139853.6" - wire width 64 $2\jtag_wb__dat_w$next[63:0]$6083 - attribute \src "libresoc.v:139452.3-139468.6" - wire $2\jtag_wb_addrsr__oe$next[0:0]$6000 - attribute \src "libresoc.v:139469.3-139489.6" - wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$6004 - attribute \src "libresoc.v:139854.3-139874.6" - wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6088 - attribute \src "libresoc.v:139508.3-139524.6" - wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$6015 - attribute \src "libresoc.v:139525.3-139545.6" - wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$6019 - attribute \src "libresoc.v:139396.3-139412.6" - wire $2\sr0__oe$next[0:0]$5985 - attribute \src "libresoc.v:139413.3-139433.6" - wire width 3 $2\sr0_reg$next[2:0]$5989 - attribute \src "libresoc.v:139676.3-139692.6" - wire $2\sr5__oe$next[0:0]$6060 - attribute \src "libresoc.v:139693.3-139713.6" - wire width 3 $2\sr5_reg$next[2:0]$6064 - attribute \src "libresoc.v:140009.3-140029.6" - wire $2\wb_dcache_en$next[0:0]$6120 - attribute \src "libresoc.v:140009.3-140029.6" - wire $2\wb_icache_en$next[0:0]$6121 - attribute \src "libresoc.v:140009.3-140029.6" - wire $2\wb_sram_en$next[0:0]$6122 - attribute \src "libresoc.v:139875.3-139907.6" - wire width 4 $3\dmi0__addr_i$next[3:0]$6094 - attribute \src "libresoc.v:139961.3-139987.6" - wire width 64 $3\dmi0__din$next[63:0]$6107 - attribute \src "libresoc.v:139581.3-139601.6" - wire width 8 $3\dmi0_addrsr_reg$next[7:0]$6035 - attribute \src "libresoc.v:139988.3-140008.6" - wire width 64 $3\dmi0_datasr__i$next[63:0]$6112 - attribute \src "libresoc.v:139637.3-139657.6" - wire width 64 $3\dmi0_datasr_reg$next[63:0]$6050 - attribute \src "libresoc.v:139908.3-139960.6" - wire width 3 $3\fsm_state$499$next[2:0]$6100 - attribute \src "libresoc.v:139774.3-139826.6" - wire width 3 $3\fsm_state$next[2:0]$6077 - attribute \src "libresoc.v:139741.3-139773.6" - wire width 29 $3\jtag_wb__adr$next[28:0]$6071 - attribute \src "libresoc.v:139827.3-139853.6" - wire width 64 $3\jtag_wb__dat_w$next[63:0]$6084 - attribute \src "libresoc.v:139469.3-139489.6" - wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$6005 - attribute \src "libresoc.v:139854.3-139874.6" - wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6089 - attribute \src "libresoc.v:139525.3-139545.6" - wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$6020 - attribute \src "libresoc.v:139413.3-139433.6" - wire width 3 $3\sr0_reg$next[2:0]$5990 - attribute \src "libresoc.v:139693.3-139713.6" - wire width 3 $3\sr5_reg$next[2:0]$6065 - attribute \src "libresoc.v:139875.3-139907.6" - wire width 4 $4\dmi0__addr_i$next[3:0]$6095 - attribute \src "libresoc.v:139908.3-139960.6" - wire width 3 $4\fsm_state$499$next[2:0]$6101 - attribute \src "libresoc.v:139774.3-139826.6" - wire width 3 $4\fsm_state$next[2:0]$6078 - attribute \src "libresoc.v:139741.3-139773.6" - wire width 29 $4\jtag_wb__adr$next[28:0]$6072 - attribute \src "libresoc.v:139908.3-139960.6" - wire width 3 $5\fsm_state$499$next[2:0]$6102 - attribute \src "libresoc.v:139774.3-139826.6" - wire width 3 $5\fsm_state$next[2:0]$6079 - attribute \src "libresoc.v:139217.19-139217.112" - wire width 30 $add$libresoc.v:139217$5900_Y - attribute \src "libresoc.v:139218.19-139218.112" - wire width 30 $add$libresoc.v:139218$5901_Y - attribute \src "libresoc.v:139225.19-139225.112" - wire width 5 $add$libresoc.v:139225$5909_Y - attribute \src "libresoc.v:139226.19-139226.112" - wire width 5 $add$libresoc.v:139226$5910_Y - attribute \src "libresoc.v:139043.18-139043.112" - wire $and$libresoc.v:139043$5726_Y - attribute \src "libresoc.v:139110.18-139110.108" - wire $and$libresoc.v:139110$5793_Y - attribute \src "libresoc.v:139121.18-139121.110" - wire $and$libresoc.v:139121$5804_Y - attribute \src "libresoc.v:139147.19-139147.110" - wire $and$libresoc.v:139147$5830_Y - attribute \src "libresoc.v:139150.19-139150.114" - wire $and$libresoc.v:139150$5833_Y - attribute \src "libresoc.v:139152.19-139152.112" - wire $and$libresoc.v:139152$5835_Y - attribute \src "libresoc.v:139155.19-139155.113" - wire $and$libresoc.v:139155$5838_Y - attribute \src "libresoc.v:139157.19-139157.121" - wire $and$libresoc.v:139157$5840_Y - attribute \src "libresoc.v:139160.19-139160.114" - wire $and$libresoc.v:139160$5843_Y - attribute \src "libresoc.v:139162.19-139162.112" - wire $and$libresoc.v:139162$5845_Y - attribute \src "libresoc.v:139164.19-139164.113" - wire $and$libresoc.v:139164$5847_Y - attribute \src "libresoc.v:139168.19-139168.132" - wire $and$libresoc.v:139168$5851_Y - attribute \src "libresoc.v:139172.19-139172.114" - wire $and$libresoc.v:139172$5855_Y - attribute \src "libresoc.v:139174.19-139174.112" - wire $and$libresoc.v:139174$5857_Y - attribute \src "libresoc.v:139176.19-139176.113" - wire $and$libresoc.v:139176$5859_Y - attribute \src "libresoc.v:139179.19-139179.132" - wire $and$libresoc.v:139179$5862_Y - attribute \src "libresoc.v:139182.19-139182.114" - wire $and$libresoc.v:139182$5865_Y - attribute \src "libresoc.v:139184.19-139184.112" - wire $and$libresoc.v:139184$5867_Y - attribute \src "libresoc.v:139186.19-139186.113" - wire $and$libresoc.v:139186$5869_Y - attribute \src "libresoc.v:139188.18-139188.108" - wire $and$libresoc.v:139188$5871_Y - attribute \src "libresoc.v:139189.19-139189.129" - wire $and$libresoc.v:139189$5872_Y - attribute \src "libresoc.v:139193.19-139193.114" - wire $and$libresoc.v:139193$5876_Y - attribute \src "libresoc.v:139195.19-139195.112" - wire $and$libresoc.v:139195$5878_Y - attribute \src "libresoc.v:139197.19-139197.113" - wire $and$libresoc.v:139197$5880_Y - attribute \src "libresoc.v:139199.18-139199.111" - wire $and$libresoc.v:139199$5882_Y - attribute \src "libresoc.v:139200.19-139200.129" - wire $and$libresoc.v:139200$5883_Y - attribute \src "libresoc.v:139203.19-139203.114" - wire $and$libresoc.v:139203$5886_Y - attribute \src "libresoc.v:139205.19-139205.112" - wire $and$libresoc.v:139205$5888_Y - attribute \src "libresoc.v:139207.19-139207.113" - wire $and$libresoc.v:139207$5890_Y - attribute \src "libresoc.v:139209.19-139209.121" - wire $and$libresoc.v:139209$5892_Y - attribute \src "libresoc.v:139242.17-139242.106" - wire $and$libresoc.v:139242$5926_Y - attribute \src "libresoc.v:138999.17-138999.110" - wire $eq$libresoc.v:138999$5682_Y - attribute \src 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$eq$libresoc.v:139148$5831_Y - attribute \src "libresoc.v:139158.19-139158.112" - wire $eq$libresoc.v:139158$5841_Y - attribute \src "libresoc.v:139165.17-139165.110" - wire $eq$libresoc.v:139165$5848_Y - attribute \src "libresoc.v:139166.18-139166.111" - wire $eq$libresoc.v:139166$5849_Y - attribute \src "libresoc.v:139169.19-139169.112" - wire $eq$libresoc.v:139169$5852_Y - attribute \src "libresoc.v:139170.19-139170.112" - wire $eq$libresoc.v:139170$5853_Y - attribute \src "libresoc.v:139180.19-139180.112" - wire $eq$libresoc.v:139180$5863_Y - attribute \src "libresoc.v:139190.19-139190.112" - wire $eq$libresoc.v:139190$5873_Y - attribute \src "libresoc.v:139191.19-139191.112" - wire $eq$libresoc.v:139191$5874_Y - attribute \src "libresoc.v:139201.19-139201.112" - wire $eq$libresoc.v:139201$5884_Y - attribute \src "libresoc.v:139210.18-139210.111" - wire $eq$libresoc.v:139210$5893_Y - attribute \src "libresoc.v:139211.19-139211.110" - wire $eq$libresoc.v:139211$5894_Y - attribute \src "libresoc.v:139213.19-139213.110" - wire $eq$libresoc.v:139213$5896_Y - attribute \src "libresoc.v:139214.19-139214.110" - wire $eq$libresoc.v:139214$5897_Y - attribute \src "libresoc.v:139216.19-139216.110" - wire $eq$libresoc.v:139216$5899_Y - attribute \src "libresoc.v:139220.18-139220.111" - wire $eq$libresoc.v:139220$5904_Y - attribute \src "libresoc.v:139221.19-139221.116" - wire $eq$libresoc.v:139221$5905_Y - attribute \src "libresoc.v:139222.19-139222.116" - wire $eq$libresoc.v:139222$5906_Y - attribute \src "libresoc.v:139224.19-139224.116" - wire $eq$libresoc.v:139224$5908_Y - attribute \src "libresoc.v:139219.19-139219.106" - wire width 8 $extend$libresoc.v:139219$5902_Y - attribute \src "libresoc.v:139149.19-139149.109" - wire $ne$libresoc.v:139149$5832_Y - attribute \src "libresoc.v:139151.19-139151.109" - wire $ne$libresoc.v:139151$5834_Y - attribute \src "libresoc.v:139153.19-139153.109" - wire $ne$libresoc.v:139153$5836_Y - attribute \src "libresoc.v:139159.19-139159.120" - wire $ne$libresoc.v:139159$5842_Y - attribute \src "libresoc.v:139161.19-139161.120" - wire $ne$libresoc.v:139161$5844_Y - attribute \src "libresoc.v:139163.19-139163.120" - wire $ne$libresoc.v:139163$5846_Y - attribute \src "libresoc.v:139171.19-139171.120" - wire $ne$libresoc.v:139171$5854_Y - attribute \src "libresoc.v:139173.19-139173.120" - wire $ne$libresoc.v:139173$5856_Y - attribute \src "libresoc.v:139175.19-139175.120" - wire $ne$libresoc.v:139175$5858_Y - attribute \src "libresoc.v:139181.19-139181.117" - wire $ne$libresoc.v:139181$5864_Y - attribute \src "libresoc.v:139183.19-139183.117" - wire $ne$libresoc.v:139183$5866_Y - attribute \src "libresoc.v:139185.19-139185.117" - wire $ne$libresoc.v:139185$5868_Y - attribute \src "libresoc.v:139192.19-139192.117" - wire $ne$libresoc.v:139192$5875_Y - attribute \src "libresoc.v:139194.19-139194.117" - wire $ne$libresoc.v:139194$5877_Y - attribute \src "libresoc.v:139196.19-139196.117" - wire $ne$libresoc.v:139196$5879_Y - attribute \src "libresoc.v:139202.19-139202.109" - wire $ne$libresoc.v:139202$5885_Y - attribute \src "libresoc.v:139204.19-139204.109" - wire $ne$libresoc.v:139204$5887_Y - attribute \src "libresoc.v:139206.19-139206.109" - wire $ne$libresoc.v:139206$5889_Y - attribute \src "libresoc.v:139156.19-139156.110" - wire $not$libresoc.v:139156$5839_Y - attribute \src "libresoc.v:139167.19-139167.121" - wire $not$libresoc.v:139167$5850_Y - attribute \src "libresoc.v:139178.19-139178.121" - wire $not$libresoc.v:139178$5861_Y - attribute \src "libresoc.v:139187.19-139187.118" - wire $not$libresoc.v:139187$5870_Y - attribute \src "libresoc.v:139198.19-139198.118" - wire $not$libresoc.v:139198$5881_Y - attribute \src "libresoc.v:139208.19-139208.110" - wire $not$libresoc.v:139208$5891_Y - attribute \src "libresoc.v:139212.19-139212.100" - wire $not$libresoc.v:139212$5895_Y - attribute \src "libresoc.v:139032.18-139032.104" - wire $or$libresoc.v:139032$5715_Y - attribute \src "libresoc.v:139077.18-139077.104" - wire $or$libresoc.v:139077$5760_Y - attribute \src "libresoc.v:139099.18-139099.104" - wire $or$libresoc.v:139099$5782_Y - attribute \src "libresoc.v:139144.19-139144.107" - wire $or$libresoc.v:139144$5827_Y - attribute \src "libresoc.v:139146.19-139146.107" - wire $or$libresoc.v:139146$5829_Y - attribute \src "libresoc.v:139154.18-139154.104" - wire $or$libresoc.v:139154$5837_Y - attribute \src "libresoc.v:139177.18-139177.104" - wire $or$libresoc.v:139177$5860_Y - attribute \src "libresoc.v:139215.19-139215.107" - wire $or$libresoc.v:139215$5898_Y - attribute \src "libresoc.v:139223.19-139223.107" - wire $or$libresoc.v:139223$5907_Y - attribute \src "libresoc.v:139231.17-139231.101" - wire $or$libresoc.v:139231$5915_Y - attribute \src "libresoc.v:139219.19-139219.106" - wire width 8 $pos$libresoc.v:139219$5903_Y - attribute \src "libresoc.v:139000.18-139000.133" - wire $ternary$libresoc.v:139000$5683_Y - attribute \src "libresoc.v:139001.19-139001.133" - wire $ternary$libresoc.v:139001$5684_Y - attribute \src "libresoc.v:139002.19-139002.134" - wire $ternary$libresoc.v:139002$5685_Y - attribute \src "libresoc.v:139003.19-139003.133" - wire $ternary$libresoc.v:139003$5686_Y - attribute \src "libresoc.v:139004.19-139004.132" - wire $ternary$libresoc.v:139004$5687_Y - attribute \src "libresoc.v:139005.19-139005.133" - wire $ternary$libresoc.v:139005$5688_Y - attribute \src "libresoc.v:139006.19-139006.133" - wire $ternary$libresoc.v:139006$5689_Y - attribute \src "libresoc.v:139007.19-139007.132" - wire $ternary$libresoc.v:139007$5690_Y - attribute \src "libresoc.v:139008.19-139008.133" - wire $ternary$libresoc.v:139008$5691_Y - attribute \src "libresoc.v:139009.19-139009.133" - wire $ternary$libresoc.v:139009$5692_Y - attribute \src "libresoc.v:139011.19-139011.132" - wire $ternary$libresoc.v:139011$5694_Y - attribute \src "libresoc.v:139012.19-139012.133" - wire $ternary$libresoc.v:139012$5695_Y - attribute \src "libresoc.v:139013.19-139013.133" - wire $ternary$libresoc.v:139013$5696_Y - attribute \src "libresoc.v:139014.19-139014.132" - wire $ternary$libresoc.v:139014$5697_Y - attribute \src "libresoc.v:139015.19-139015.133" - wire $ternary$libresoc.v:139015$5698_Y - attribute \src "libresoc.v:139016.19-139016.133" - wire $ternary$libresoc.v:139016$5699_Y - attribute \src "libresoc.v:139017.19-139017.132" - wire $ternary$libresoc.v:139017$5700_Y - attribute \src "libresoc.v:139018.19-139018.133" - wire $ternary$libresoc.v:139018$5701_Y - attribute \src "libresoc.v:139019.19-139019.133" - wire $ternary$libresoc.v:139019$5702_Y - attribute \src "libresoc.v:139020.19-139020.132" - wire $ternary$libresoc.v:139020$5703_Y - attribute \src "libresoc.v:139022.19-139022.133" - wire $ternary$libresoc.v:139022$5705_Y - attribute \src "libresoc.v:139023.19-139023.133" - wire $ternary$libresoc.v:139023$5706_Y - attribute \src "libresoc.v:139024.19-139024.132" - wire $ternary$libresoc.v:139024$5707_Y - attribute \src "libresoc.v:139025.19-139025.133" - wire $ternary$libresoc.v:139025$5708_Y - attribute \src "libresoc.v:139026.19-139026.133" - wire $ternary$libresoc.v:139026$5709_Y - attribute \src "libresoc.v:139027.19-139027.132" - wire $ternary$libresoc.v:139027$5710_Y - attribute \src "libresoc.v:139028.19-139028.133" - wire $ternary$libresoc.v:139028$5711_Y - attribute \src "libresoc.v:139029.19-139029.134" - wire $ternary$libresoc.v:139029$5712_Y - attribute \src "libresoc.v:139030.19-139030.135" - wire $ternary$libresoc.v:139030$5713_Y - attribute \src "libresoc.v:139031.19-139031.135" - wire $ternary$libresoc.v:139031$5714_Y - attribute \src "libresoc.v:139033.19-139033.136" - wire $ternary$libresoc.v:139033$5716_Y - attribute \src "libresoc.v:139034.19-139034.134" - wire $ternary$libresoc.v:139034$5717_Y - attribute \src "libresoc.v:139035.19-139035.135" - wire $ternary$libresoc.v:139035$5718_Y - attribute \src "libresoc.v:139036.19-139036.135" - wire $ternary$libresoc.v:139036$5719_Y - attribute \src "libresoc.v:139037.19-139037.136" - wire $ternary$libresoc.v:139037$5720_Y - attribute \src "libresoc.v:139038.19-139038.134" - wire $ternary$libresoc.v:139038$5721_Y - attribute \src "libresoc.v:139039.19-139039.133" - wire $ternary$libresoc.v:139039$5722_Y - attribute \src "libresoc.v:139040.19-139040.134" - wire $ternary$libresoc.v:139040$5723_Y - attribute \src "libresoc.v:139041.19-139041.133" - wire $ternary$libresoc.v:139041$5724_Y - attribute \src "libresoc.v:139042.19-139042.130" - wire $ternary$libresoc.v:139042$5725_Y - attribute \src "libresoc.v:139044.19-139044.130" - wire $ternary$libresoc.v:139044$5727_Y - attribute \src "libresoc.v:139045.19-139045.133" - wire $ternary$libresoc.v:139045$5728_Y - attribute \src "libresoc.v:139046.19-139046.132" - wire $ternary$libresoc.v:139046$5729_Y - attribute \src "libresoc.v:139047.19-139047.133" - wire $ternary$libresoc.v:139047$5730_Y - attribute \src "libresoc.v:139048.19-139048.132" - wire $ternary$libresoc.v:139048$5731_Y - attribute \src "libresoc.v:139049.19-139049.135" - wire $ternary$libresoc.v:139049$5732_Y - attribute \src "libresoc.v:139050.19-139050.134" - wire $ternary$libresoc.v:139050$5733_Y - attribute \src "libresoc.v:139051.19-139051.135" - wire $ternary$libresoc.v:139051$5734_Y - attribute \src "libresoc.v:139052.19-139052.135" - wire $ternary$libresoc.v:139052$5735_Y - attribute \src "libresoc.v:139053.19-139053.134" - wire $ternary$libresoc.v:139053$5736_Y - attribute \src "libresoc.v:139056.19-139056.135" - wire $ternary$libresoc.v:139056$5739_Y - attribute \src "libresoc.v:139057.19-139057.135" - wire $ternary$libresoc.v:139057$5740_Y - attribute \src "libresoc.v:139058.19-139058.134" - wire $ternary$libresoc.v:139058$5741_Y - attribute \src "libresoc.v:139059.19-139059.135" - wire $ternary$libresoc.v:139059$5742_Y - attribute \src "libresoc.v:139060.19-139060.135" - wire $ternary$libresoc.v:139060$5743_Y - attribute \src "libresoc.v:139061.19-139061.134" - wire $ternary$libresoc.v:139061$5744_Y - attribute \src "libresoc.v:139062.19-139062.135" - wire $ternary$libresoc.v:139062$5745_Y - attribute \src "libresoc.v:139063.19-139063.133" - wire $ternary$libresoc.v:139063$5746_Y - attribute \src "libresoc.v:139064.19-139064.134" - wire $ternary$libresoc.v:139064$5747_Y - attribute \src "libresoc.v:139065.19-139065.133" - wire $ternary$libresoc.v:139065$5748_Y - attribute \src "libresoc.v:139067.19-139067.134" - wire $ternary$libresoc.v:139067$5750_Y - attribute \src "libresoc.v:139068.19-139068.134" - wire $ternary$libresoc.v:139068$5751_Y - attribute \src "libresoc.v:139069.19-139069.133" - wire $ternary$libresoc.v:139069$5752_Y - attribute \src "libresoc.v:139070.19-139070.134" - wire $ternary$libresoc.v:139070$5753_Y - attribute \src "libresoc.v:139071.19-139071.134" - wire $ternary$libresoc.v:139071$5754_Y - attribute \src "libresoc.v:139072.19-139072.133" - wire $ternary$libresoc.v:139072$5755_Y - attribute \src "libresoc.v:139073.19-139073.134" - wire $ternary$libresoc.v:139073$5756_Y - attribute \src "libresoc.v:139074.19-139074.134" - wire $ternary$libresoc.v:139074$5757_Y - attribute \src "libresoc.v:139075.19-139075.133" - wire $ternary$libresoc.v:139075$5758_Y - attribute \src "libresoc.v:139076.19-139076.134" - wire $ternary$libresoc.v:139076$5759_Y - attribute \src "libresoc.v:139078.19-139078.134" - wire $ternary$libresoc.v:139078$5761_Y - attribute \src "libresoc.v:139079.19-139079.133" - wire $ternary$libresoc.v:139079$5762_Y - attribute \src "libresoc.v:139080.19-139080.134" - wire $ternary$libresoc.v:139080$5763_Y - attribute \src "libresoc.v:139081.19-139081.134" - wire $ternary$libresoc.v:139081$5764_Y - attribute \src "libresoc.v:139082.19-139082.133" - wire $ternary$libresoc.v:139082$5765_Y - attribute \src "libresoc.v:139083.19-139083.134" - wire $ternary$libresoc.v:139083$5766_Y - attribute \src "libresoc.v:139084.19-139084.135" - wire $ternary$libresoc.v:139084$5767_Y - attribute \src "libresoc.v:139085.19-139085.134" - wire $ternary$libresoc.v:139085$5768_Y - attribute \src "libresoc.v:139086.19-139086.135" - wire $ternary$libresoc.v:139086$5769_Y - attribute \src "libresoc.v:139087.19-139087.135" - wire $ternary$libresoc.v:139087$5770_Y - attribute \src "libresoc.v:139089.19-139089.134" - wire $ternary$libresoc.v:139089$5772_Y - attribute \src "libresoc.v:139090.19-139090.135" - wire $ternary$libresoc.v:139090$5773_Y - attribute \src "libresoc.v:139091.19-139091.133" - wire $ternary$libresoc.v:139091$5774_Y - attribute \src "libresoc.v:139092.19-139092.133" - wire $ternary$libresoc.v:139092$5775_Y - attribute \src "libresoc.v:139093.19-139093.133" - wire $ternary$libresoc.v:139093$5776_Y - attribute \src "libresoc.v:139094.19-139094.133" - wire $ternary$libresoc.v:139094$5777_Y - attribute \src "libresoc.v:139095.19-139095.133" - wire $ternary$libresoc.v:139095$5778_Y - attribute \src "libresoc.v:139096.19-139096.133" - wire $ternary$libresoc.v:139096$5779_Y - attribute \src "libresoc.v:139097.19-139097.133" - wire $ternary$libresoc.v:139097$5780_Y - attribute \src "libresoc.v:139098.19-139098.133" - wire $ternary$libresoc.v:139098$5781_Y - attribute \src "libresoc.v:139100.19-139100.133" - wire $ternary$libresoc.v:139100$5783_Y - attribute \src "libresoc.v:139101.19-139101.133" - wire $ternary$libresoc.v:139101$5784_Y - attribute \src "libresoc.v:139102.19-139102.134" - wire $ternary$libresoc.v:139102$5785_Y - attribute \src "libresoc.v:139103.19-139103.134" - wire $ternary$libresoc.v:139103$5786_Y - attribute \src "libresoc.v:139104.19-139104.135" - wire $ternary$libresoc.v:139104$5787_Y - attribute \src "libresoc.v:139105.19-139105.133" - wire $ternary$libresoc.v:139105$5788_Y - attribute \src "libresoc.v:139106.19-139106.135" - wire $ternary$libresoc.v:139106$5789_Y - attribute \src "libresoc.v:139107.19-139107.135" - wire $ternary$libresoc.v:139107$5790_Y - attribute \src "libresoc.v:139108.19-139108.134" - wire $ternary$libresoc.v:139108$5791_Y - attribute \src "libresoc.v:139109.19-139109.134" - wire $ternary$libresoc.v:139109$5792_Y - attribute \src "libresoc.v:139111.19-139111.134" - wire $ternary$libresoc.v:139111$5794_Y - attribute \src "libresoc.v:139112.19-139112.134" - wire $ternary$libresoc.v:139112$5795_Y - attribute \src "libresoc.v:139113.19-139113.134" - wire $ternary$libresoc.v:139113$5796_Y - attribute \src "libresoc.v:139114.19-139114.134" - wire $ternary$libresoc.v:139114$5797_Y - attribute \src "libresoc.v:139115.19-139115.135" - wire $ternary$libresoc.v:139115$5798_Y - attribute \src "libresoc.v:139116.19-139116.134" - wire $ternary$libresoc.v:139116$5799_Y - attribute \src "libresoc.v:139117.19-139117.135" - wire $ternary$libresoc.v:139117$5800_Y - attribute \src "libresoc.v:139118.19-139118.135" - wire $ternary$libresoc.v:139118$5801_Y - attribute \src "libresoc.v:139119.19-139119.134" - wire $ternary$libresoc.v:139119$5802_Y - attribute \src "libresoc.v:139120.19-139120.135" - wire $ternary$libresoc.v:139120$5803_Y - attribute \src "libresoc.v:139122.19-139122.136" - wire $ternary$libresoc.v:139122$5805_Y - attribute \src "libresoc.v:139123.19-139123.135" - wire $ternary$libresoc.v:139123$5806_Y - attribute \src "libresoc.v:139124.19-139124.136" - wire $ternary$libresoc.v:139124$5807_Y - attribute \src "libresoc.v:139125.19-139125.136" - wire $ternary$libresoc.v:139125$5808_Y - attribute \src "libresoc.v:139126.19-139126.135" - wire $ternary$libresoc.v:139126$5809_Y - attribute \src "libresoc.v:139127.19-139127.136" - wire $ternary$libresoc.v:139127$5810_Y - attribute \src "libresoc.v:139128.19-139128.136" - wire $ternary$libresoc.v:139128$5811_Y - attribute \src "libresoc.v:139129.19-139129.135" - wire $ternary$libresoc.v:139129$5812_Y - attribute \src "libresoc.v:139130.19-139130.136" - wire $ternary$libresoc.v:139130$5813_Y - attribute \src "libresoc.v:139131.19-139131.136" - wire $ternary$libresoc.v:139131$5814_Y - attribute \src "libresoc.v:139133.19-139133.135" - wire $ternary$libresoc.v:139133$5816_Y - attribute \src "libresoc.v:139134.19-139134.136" - wire $ternary$libresoc.v:139134$5817_Y - attribute \src "libresoc.v:139135.19-139135.136" - wire $ternary$libresoc.v:139135$5818_Y - attribute \src "libresoc.v:139136.19-139136.135" - wire $ternary$libresoc.v:139136$5819_Y - attribute \src "libresoc.v:139137.19-139137.136" - wire $ternary$libresoc.v:139137$5820_Y - attribute \src "libresoc.v:139138.19-139138.136" - wire $ternary$libresoc.v:139138$5821_Y - attribute \src "libresoc.v:139139.19-139139.135" - wire $ternary$libresoc.v:139139$5822_Y - attribute \src "libresoc.v:139140.19-139140.136" - wire $ternary$libresoc.v:139140$5823_Y - attribute \src "libresoc.v:139227.18-139227.130" - wire $ternary$libresoc.v:139227$5911_Y - attribute \src "libresoc.v:139228.18-139228.130" - wire $ternary$libresoc.v:139228$5912_Y - attribute \src "libresoc.v:139229.18-139229.130" - wire $ternary$libresoc.v:139229$5913_Y - attribute \src "libresoc.v:139230.18-139230.131" - wire $ternary$libresoc.v:139230$5914_Y - attribute \src "libresoc.v:139232.18-139232.130" - wire $ternary$libresoc.v:139232$5916_Y - attribute \src "libresoc.v:139233.18-139233.131" - wire $ternary$libresoc.v:139233$5917_Y - attribute \src "libresoc.v:139234.18-139234.131" - wire $ternary$libresoc.v:139234$5918_Y - attribute \src "libresoc.v:139235.18-139235.130" - wire $ternary$libresoc.v:139235$5919_Y - attribute \src "libresoc.v:139236.18-139236.131" - wire $ternary$libresoc.v:139236$5920_Y - attribute \src "libresoc.v:139237.18-139237.132" - wire $ternary$libresoc.v:139237$5921_Y - attribute \src "libresoc.v:139238.18-139238.132" - wire $ternary$libresoc.v:139238$5922_Y - attribute \src "libresoc.v:139239.18-139239.133" - wire $ternary$libresoc.v:139239$5923_Y - attribute \src "libresoc.v:139240.18-139240.133" - wire $ternary$libresoc.v:139240$5924_Y - attribute \src "libresoc.v:139241.18-139241.132" - wire $ternary$libresoc.v:139241$5925_Y - attribute \src "libresoc.v:139243.18-139243.133" - wire $ternary$libresoc.v:139243$5927_Y - attribute \src "libresoc.v:139244.18-139244.133" - wire $ternary$libresoc.v:139244$5928_Y - attribute \src "libresoc.v:139245.18-139245.132" - wire $ternary$libresoc.v:139245$5929_Y - attribute \src "libresoc.v:139246.18-139246.133" - wire $ternary$libresoc.v:139246$5930_Y - attribute \src "libresoc.v:139247.18-139247.133" - wire $ternary$libresoc.v:139247$5931_Y - attribute \src "libresoc.v:139248.18-139248.132" - wire $ternary$libresoc.v:139248$5932_Y - attribute \src "libresoc.v:139249.18-139249.133" - wire $ternary$libresoc.v:139249$5933_Y - attribute \src "libresoc.v:139250.18-139250.133" - wire $ternary$libresoc.v:139250$5934_Y - attribute \src "libresoc.v:139251.18-139251.132" - wire $ternary$libresoc.v:139251$5935_Y - attribute \src "libresoc.v:139252.18-139252.133" - wire $ternary$libresoc.v:139252$5936_Y + attribute \src "libresoc.v:140217.3-140261.6" + wire width 4 $2\dmi0__addr_i$next[3:0]$6025 + attribute \src "libresoc.v:140315.3-140341.6" + wire width 64 $2\dmi0__din$next[63:0]$6038 + attribute \src "libresoc.v:139886.3-139902.6" + wire $2\dmi0_addrsr__oe$next[0:0]$5962 + attribute \src "libresoc.v:139903.3-139923.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$5966 + attribute \src "libresoc.v:140342.3-140370.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$6043 + attribute \src "libresoc.v:139942.3-139958.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$5977 + attribute \src "libresoc.v:139959.3-139979.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$5981 + attribute \src "libresoc.v:140262.3-140314.6" + wire width 3 $2\fsm_state$455$next[2:0]$6031 + attribute \src "libresoc.v:140108.3-140160.6" + wire width 3 $2\fsm_state$next[2:0]$6008 + attribute \src "libresoc.v:140420.3-140440.6" + wire width 130 $2\io_bd$next[129:0]$6063 + attribute \src "libresoc.v:140402.3-140419.6" + wire width 130 $2\io_sr$next[129:0]$6059 + attribute \src "libresoc.v:140063.3-140107.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$6002 + attribute \src "libresoc.v:140161.3-140187.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$6015 + attribute \src "libresoc.v:139774.3-139790.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$5932 + attribute \src "libresoc.v:139791.3-139811.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5936 + attribute \src "libresoc.v:140188.3-140216.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6020 + attribute \src "libresoc.v:139830.3-139846.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5947 + attribute \src "libresoc.v:139847.3-139867.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$5951 + attribute \src "libresoc.v:139718.3-139734.6" + wire $2\sr0__oe$next[0:0]$5917 + attribute \src "libresoc.v:139735.3-139755.6" + wire width 3 $2\sr0_reg$next[2:0]$5921 + attribute \src "libresoc.v:139998.3-140014.6" + wire $2\sr5__oe$next[0:0]$5992 + attribute \src "libresoc.v:140015.3-140035.6" + wire width 3 $2\sr5_reg$next[2:0]$5996 + attribute \src "libresoc.v:140371.3-140391.6" + wire $2\wb_dcache_en$next[0:0]$6052 + attribute \src "libresoc.v:140371.3-140391.6" + wire $2\wb_icache_en$next[0:0]$6053 + attribute \src "libresoc.v:140371.3-140391.6" + wire $2\wb_sram_en$next[0:0]$6054 + attribute \src "libresoc.v:140217.3-140261.6" + wire width 4 $3\dmi0__addr_i$next[3:0]$6026 + attribute \src "libresoc.v:140315.3-140341.6" + wire width 64 $3\dmi0__din$next[63:0]$6039 + attribute \src "libresoc.v:139903.3-139923.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$5967 + attribute \src "libresoc.v:140342.3-140370.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$6044 + attribute \src "libresoc.v:139959.3-139979.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$5982 + attribute \src "libresoc.v:140262.3-140314.6" + wire width 3 $3\fsm_state$455$next[2:0]$6032 + attribute \src "libresoc.v:140108.3-140160.6" + wire width 3 $3\fsm_state$next[2:0]$6009 + attribute \src "libresoc.v:140063.3-140107.6" + wire width 29 $3\jtag_wb__adr$next[28:0]$6003 + attribute \src "libresoc.v:140161.3-140187.6" + wire width 64 $3\jtag_wb__dat_w$next[63:0]$6016 + attribute \src "libresoc.v:139791.3-139811.6" + wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5937 + attribute \src "libresoc.v:140188.3-140216.6" + wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6021 + attribute \src "libresoc.v:139847.3-139867.6" + wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$5952 + attribute \src "libresoc.v:139735.3-139755.6" + wire width 3 $3\sr0_reg$next[2:0]$5922 + attribute \src "libresoc.v:140015.3-140035.6" + wire width 3 $3\sr5_reg$next[2:0]$5997 + attribute \src "libresoc.v:140217.3-140261.6" + wire width 4 $4\dmi0__addr_i$next[3:0]$6027 + attribute \src "libresoc.v:140262.3-140314.6" + wire width 3 $4\fsm_state$455$next[2:0]$6033 + attribute \src "libresoc.v:140108.3-140160.6" + wire width 3 $4\fsm_state$next[2:0]$6010 + attribute \src "libresoc.v:140063.3-140107.6" + wire width 29 $4\jtag_wb__adr$next[28:0]$6004 + attribute \src "libresoc.v:140262.3-140314.6" + wire width 3 $5\fsm_state$455$next[2:0]$6034 + attribute \src "libresoc.v:140108.3-140160.6" + wire width 3 $5\fsm_state$next[2:0]$6011 + attribute \src "libresoc.v:139537.19-139537.112" + wire width 30 $add$libresoc.v:139537$5830_Y + attribute \src "libresoc.v:139538.19-139538.112" + wire width 30 $add$libresoc.v:139538$5831_Y + attribute \src "libresoc.v:139545.19-139545.112" + wire width 5 $add$libresoc.v:139545$5839_Y + attribute \src "libresoc.v:139546.19-139546.112" + wire width 5 $add$libresoc.v:139546$5840_Y + attribute \src "libresoc.v:139387.18-139387.112" + wire $and$libresoc.v:139387$5680_Y + attribute \src "libresoc.v:139454.18-139454.108" + wire $and$libresoc.v:139454$5747_Y + attribute \src "libresoc.v:139465.18-139465.110" + wire $and$libresoc.v:139465$5758_Y + attribute \src "libresoc.v:139467.19-139467.110" + wire $and$libresoc.v:139467$5760_Y + attribute \src "libresoc.v:139470.19-139470.114" + wire $and$libresoc.v:139470$5763_Y + attribute \src "libresoc.v:139472.19-139472.112" + wire $and$libresoc.v:139472$5765_Y + attribute \src "libresoc.v:139474.19-139474.113" + wire $and$libresoc.v:139474$5767_Y + attribute \src "libresoc.v:139477.19-139477.121" + wire $and$libresoc.v:139477$5770_Y + attribute \src "libresoc.v:139480.19-139480.114" + wire $and$libresoc.v:139480$5773_Y + attribute \src "libresoc.v:139482.19-139482.112" + wire $and$libresoc.v:139482$5775_Y + attribute \src "libresoc.v:139484.19-139484.113" + wire $and$libresoc.v:139484$5777_Y + attribute \src "libresoc.v:139486.19-139486.132" + wire $and$libresoc.v:139486$5779_Y + attribute \src "libresoc.v:139491.19-139491.114" + wire $and$libresoc.v:139491$5784_Y + attribute \src "libresoc.v:139493.19-139493.112" + wire $and$libresoc.v:139493$5786_Y + attribute \src "libresoc.v:139495.19-139495.113" + wire $and$libresoc.v:139495$5788_Y + attribute \src "libresoc.v:139497.19-139497.132" + wire $and$libresoc.v:139497$5790_Y + attribute \src "libresoc.v:139501.19-139501.114" + wire $and$libresoc.v:139501$5794_Y + attribute \src "libresoc.v:139503.19-139503.112" + wire $and$libresoc.v:139503$5796_Y + attribute \src "libresoc.v:139505.19-139505.113" + wire $and$libresoc.v:139505$5798_Y + attribute \src "libresoc.v:139507.19-139507.129" + wire $and$libresoc.v:139507$5800_Y + attribute \src "libresoc.v:139513.19-139513.114" + wire $and$libresoc.v:139513$5806_Y + attribute \src "libresoc.v:139515.19-139515.112" + wire $and$libresoc.v:139515$5808_Y + attribute \src "libresoc.v:139517.19-139517.113" + wire $and$libresoc.v:139517$5810_Y + attribute \src "libresoc.v:139519.19-139519.129" + wire $and$libresoc.v:139519$5812_Y + attribute \src "libresoc.v:139523.19-139523.114" + wire $and$libresoc.v:139523$5816_Y + attribute \src "libresoc.v:139525.19-139525.112" + wire $and$libresoc.v:139525$5818_Y + attribute \src "libresoc.v:139527.19-139527.113" + wire $and$libresoc.v:139527$5820_Y + attribute \src "libresoc.v:139529.19-139529.121" + wire $and$libresoc.v:139529$5822_Y + attribute \src "libresoc.v:139532.18-139532.108" + wire $and$libresoc.v:139532$5825_Y + attribute \src "libresoc.v:139542.18-139542.111" + wire $and$libresoc.v:139542$5836_Y + attribute \src "libresoc.v:139564.17-139564.106" + wire $and$libresoc.v:139564$5858_Y + attribute \src "libresoc.v:139343.17-139343.110" + wire $eq$libresoc.v:139343$5636_Y + attribute \src "libresoc.v:139354.18-139354.111" + wire $eq$libresoc.v:139354$5647_Y + attribute \src "libresoc.v:139365.18-139365.111" + wire $eq$libresoc.v:139365$5658_Y + attribute \src "libresoc.v:139398.17-139398.110" + wire $eq$libresoc.v:139398$5691_Y + attribute \src "libresoc.v:139399.18-139399.111" + wire $eq$libresoc.v:139399$5692_Y + attribute \src "libresoc.v:139410.18-139410.111" + wire $eq$libresoc.v:139410$5703_Y + attribute \src "libresoc.v:139432.18-139432.111" + wire $eq$libresoc.v:139432$5725_Y + attribute \src "libresoc.v:139461.19-139461.112" + wire $eq$libresoc.v:139461$5754_Y + attribute \src "libresoc.v:139462.19-139462.112" + wire $eq$libresoc.v:139462$5755_Y + attribute \src "libresoc.v:139464.19-139464.112" + wire $eq$libresoc.v:139464$5757_Y + attribute \src "libresoc.v:139468.19-139468.112" + wire $eq$libresoc.v:139468$5761_Y + attribute \src "libresoc.v:139476.18-139476.111" + wire $eq$libresoc.v:139476$5769_Y + attribute \src "libresoc.v:139478.19-139478.112" + wire $eq$libresoc.v:139478$5771_Y + attribute \src "libresoc.v:139487.18-139487.111" + wire $eq$libresoc.v:139487$5780_Y + attribute \src "libresoc.v:139488.19-139488.112" + wire $eq$libresoc.v:139488$5781_Y + attribute \src "libresoc.v:139489.19-139489.112" + wire $eq$libresoc.v:139489$5782_Y + attribute \src "libresoc.v:139499.19-139499.112" + wire $eq$libresoc.v:139499$5792_Y + attribute \src "libresoc.v:139508.19-139508.112" + wire $eq$libresoc.v:139508$5801_Y + attribute \src "libresoc.v:139509.17-139509.110" + wire $eq$libresoc.v:139509$5802_Y + attribute \src "libresoc.v:139510.18-139510.111" + wire $eq$libresoc.v:139510$5803_Y + attribute \src "libresoc.v:139511.19-139511.112" + wire $eq$libresoc.v:139511$5804_Y + attribute \src "libresoc.v:139520.19-139520.112" + wire $eq$libresoc.v:139520$5813_Y + attribute \src "libresoc.v:139530.19-139530.110" + wire $eq$libresoc.v:139530$5823_Y + attribute \src "libresoc.v:139533.19-139533.110" + wire $eq$libresoc.v:139533$5826_Y + attribute \src "libresoc.v:139534.19-139534.110" + wire $eq$libresoc.v:139534$5827_Y + attribute \src "libresoc.v:139536.19-139536.110" + wire $eq$libresoc.v:139536$5829_Y + attribute \src "libresoc.v:139540.19-139540.116" + wire $eq$libresoc.v:139540$5834_Y + attribute \src "libresoc.v:139541.19-139541.116" + wire $eq$libresoc.v:139541$5835_Y + attribute \src "libresoc.v:139544.19-139544.116" + wire $eq$libresoc.v:139544$5838_Y + attribute \src "libresoc.v:139547.18-139547.111" + wire $eq$libresoc.v:139547$5841_Y + attribute \src "libresoc.v:139548.18-139548.111" + wire $eq$libresoc.v:139548$5842_Y + attribute \src "libresoc.v:139539.19-139539.106" + wire width 8 $extend$libresoc.v:139539$5832_Y + attribute \src "libresoc.v:139469.19-139469.109" + wire $ne$libresoc.v:139469$5762_Y + attribute \src "libresoc.v:139471.19-139471.109" + wire $ne$libresoc.v:139471$5764_Y + attribute \src "libresoc.v:139473.19-139473.109" + wire $ne$libresoc.v:139473$5766_Y + attribute \src "libresoc.v:139479.19-139479.120" + wire $ne$libresoc.v:139479$5772_Y + attribute \src "libresoc.v:139481.19-139481.120" + wire $ne$libresoc.v:139481$5774_Y + attribute \src "libresoc.v:139483.19-139483.120" + wire $ne$libresoc.v:139483$5776_Y + attribute \src "libresoc.v:139490.19-139490.120" + wire $ne$libresoc.v:139490$5783_Y + attribute \src "libresoc.v:139492.19-139492.120" + wire $ne$libresoc.v:139492$5785_Y + attribute \src "libresoc.v:139494.19-139494.120" + wire $ne$libresoc.v:139494$5787_Y + attribute \src "libresoc.v:139500.19-139500.117" + wire $ne$libresoc.v:139500$5793_Y + attribute \src "libresoc.v:139502.19-139502.117" + wire $ne$libresoc.v:139502$5795_Y + attribute \src "libresoc.v:139504.19-139504.117" + wire $ne$libresoc.v:139504$5797_Y + attribute \src "libresoc.v:139512.19-139512.117" + wire $ne$libresoc.v:139512$5805_Y + attribute \src "libresoc.v:139514.19-139514.117" + wire $ne$libresoc.v:139514$5807_Y + attribute \src "libresoc.v:139516.19-139516.117" + wire $ne$libresoc.v:139516$5809_Y + attribute \src "libresoc.v:139522.19-139522.109" + wire $ne$libresoc.v:139522$5815_Y + attribute \src "libresoc.v:139524.19-139524.109" + wire $ne$libresoc.v:139524$5817_Y + attribute \src "libresoc.v:139526.19-139526.109" + wire $ne$libresoc.v:139526$5819_Y + attribute \src "libresoc.v:139475.19-139475.110" + wire $not$libresoc.v:139475$5768_Y + attribute \src "libresoc.v:139485.19-139485.121" + wire $not$libresoc.v:139485$5778_Y + attribute \src "libresoc.v:139496.19-139496.121" + wire $not$libresoc.v:139496$5789_Y + attribute \src "libresoc.v:139506.19-139506.118" + wire $not$libresoc.v:139506$5799_Y + attribute \src "libresoc.v:139518.19-139518.118" + wire $not$libresoc.v:139518$5811_Y + attribute \src "libresoc.v:139528.19-139528.110" + wire $not$libresoc.v:139528$5821_Y + attribute \src "libresoc.v:139531.19-139531.100" + wire $not$libresoc.v:139531$5824_Y + attribute \src "libresoc.v:139376.18-139376.104" + wire $or$libresoc.v:139376$5669_Y + attribute \src "libresoc.v:139421.18-139421.104" + wire $or$libresoc.v:139421$5714_Y + attribute \src "libresoc.v:139443.18-139443.104" + wire $or$libresoc.v:139443$5736_Y + attribute \src "libresoc.v:139463.19-139463.107" + wire $or$libresoc.v:139463$5756_Y + attribute \src "libresoc.v:139466.19-139466.107" + wire $or$libresoc.v:139466$5759_Y + attribute \src "libresoc.v:139498.18-139498.104" + wire $or$libresoc.v:139498$5791_Y + attribute \src "libresoc.v:139521.18-139521.104" + wire $or$libresoc.v:139521$5814_Y + attribute \src "libresoc.v:139535.19-139535.107" + wire $or$libresoc.v:139535$5828_Y + attribute \src "libresoc.v:139543.19-139543.107" + wire $or$libresoc.v:139543$5837_Y + attribute \src "libresoc.v:139553.17-139553.101" + wire $or$libresoc.v:139553$5847_Y + attribute \src "libresoc.v:139539.19-139539.106" + wire width 8 $pos$libresoc.v:139539$5833_Y + attribute \src "libresoc.v:139344.18-139344.133" + wire $ternary$libresoc.v:139344$5637_Y + attribute \src "libresoc.v:139345.19-139345.133" + wire $ternary$libresoc.v:139345$5638_Y + attribute \src "libresoc.v:139346.19-139346.134" + wire $ternary$libresoc.v:139346$5639_Y + attribute \src "libresoc.v:139347.19-139347.133" + wire $ternary$libresoc.v:139347$5640_Y + attribute \src "libresoc.v:139348.19-139348.132" + wire $ternary$libresoc.v:139348$5641_Y + attribute \src "libresoc.v:139349.19-139349.133" + wire $ternary$libresoc.v:139349$5642_Y + attribute \src "libresoc.v:139350.19-139350.133" + wire $ternary$libresoc.v:139350$5643_Y + attribute \src "libresoc.v:139351.19-139351.132" + wire $ternary$libresoc.v:139351$5644_Y + attribute \src "libresoc.v:139352.19-139352.133" + wire $ternary$libresoc.v:139352$5645_Y + attribute \src "libresoc.v:139353.19-139353.133" + wire $ternary$libresoc.v:139353$5646_Y + attribute \src "libresoc.v:139355.19-139355.132" + wire $ternary$libresoc.v:139355$5648_Y + attribute \src "libresoc.v:139356.19-139356.133" + wire $ternary$libresoc.v:139356$5649_Y + attribute \src "libresoc.v:139357.19-139357.133" + wire $ternary$libresoc.v:139357$5650_Y + attribute \src "libresoc.v:139358.19-139358.132" + wire $ternary$libresoc.v:139358$5651_Y + attribute \src "libresoc.v:139359.19-139359.133" + wire $ternary$libresoc.v:139359$5652_Y + attribute \src "libresoc.v:139360.19-139360.133" + wire $ternary$libresoc.v:139360$5653_Y + attribute \src "libresoc.v:139361.19-139361.132" + wire $ternary$libresoc.v:139361$5654_Y + attribute \src "libresoc.v:139362.19-139362.133" + wire $ternary$libresoc.v:139362$5655_Y + attribute \src "libresoc.v:139363.19-139363.133" + wire $ternary$libresoc.v:139363$5656_Y + attribute \src "libresoc.v:139364.19-139364.132" + wire $ternary$libresoc.v:139364$5657_Y + attribute \src "libresoc.v:139366.19-139366.133" + wire $ternary$libresoc.v:139366$5659_Y + attribute \src "libresoc.v:139367.19-139367.133" + wire $ternary$libresoc.v:139367$5660_Y + attribute \src "libresoc.v:139368.19-139368.132" + wire $ternary$libresoc.v:139368$5661_Y + attribute \src "libresoc.v:139369.19-139369.133" + wire $ternary$libresoc.v:139369$5662_Y + attribute \src "libresoc.v:139370.19-139370.133" + wire $ternary$libresoc.v:139370$5663_Y + attribute \src "libresoc.v:139371.19-139371.132" + wire $ternary$libresoc.v:139371$5664_Y + attribute \src "libresoc.v:139372.19-139372.133" + wire $ternary$libresoc.v:139372$5665_Y + attribute \src "libresoc.v:139373.19-139373.134" + wire $ternary$libresoc.v:139373$5666_Y + attribute \src "libresoc.v:139374.19-139374.135" + wire $ternary$libresoc.v:139374$5667_Y + attribute \src "libresoc.v:139375.19-139375.135" + wire $ternary$libresoc.v:139375$5668_Y + attribute \src "libresoc.v:139377.19-139377.136" + wire $ternary$libresoc.v:139377$5670_Y + attribute \src "libresoc.v:139378.19-139378.134" + wire $ternary$libresoc.v:139378$5671_Y + attribute \src "libresoc.v:139379.19-139379.133" + wire $ternary$libresoc.v:139379$5672_Y + attribute \src "libresoc.v:139380.19-139380.134" + wire $ternary$libresoc.v:139380$5673_Y + attribute \src "libresoc.v:139381.19-139381.133" + wire $ternary$libresoc.v:139381$5674_Y + attribute \src "libresoc.v:139382.19-139382.133" + wire $ternary$libresoc.v:139382$5675_Y + attribute \src "libresoc.v:139383.19-139383.134" + wire $ternary$libresoc.v:139383$5676_Y + attribute \src "libresoc.v:139384.19-139384.133" + wire $ternary$libresoc.v:139384$5677_Y + attribute \src "libresoc.v:139385.19-139385.134" + wire $ternary$libresoc.v:139385$5678_Y + attribute \src "libresoc.v:139386.19-139386.134" + wire $ternary$libresoc.v:139386$5679_Y + attribute \src "libresoc.v:139388.19-139388.133" + wire $ternary$libresoc.v:139388$5681_Y + attribute \src "libresoc.v:139389.19-139389.134" + wire $ternary$libresoc.v:139389$5682_Y + attribute \src "libresoc.v:139390.19-139390.134" + wire $ternary$libresoc.v:139390$5683_Y + attribute \src "libresoc.v:139391.19-139391.133" + wire $ternary$libresoc.v:139391$5684_Y + attribute \src "libresoc.v:139392.19-139392.134" + wire $ternary$libresoc.v:139392$5685_Y + attribute \src "libresoc.v:139393.19-139393.134" + wire $ternary$libresoc.v:139393$5686_Y + attribute \src "libresoc.v:139394.19-139394.133" + wire $ternary$libresoc.v:139394$5687_Y + attribute \src "libresoc.v:139395.19-139395.134" + wire $ternary$libresoc.v:139395$5688_Y + attribute \src "libresoc.v:139396.19-139396.134" + wire $ternary$libresoc.v:139396$5689_Y + attribute \src "libresoc.v:139397.19-139397.133" + wire $ternary$libresoc.v:139397$5690_Y + attribute \src "libresoc.v:139400.19-139400.134" + wire $ternary$libresoc.v:139400$5693_Y + attribute \src "libresoc.v:139401.19-139401.134" + wire $ternary$libresoc.v:139401$5694_Y + attribute \src "libresoc.v:139402.19-139402.133" + wire $ternary$libresoc.v:139402$5695_Y + attribute \src "libresoc.v:139403.19-139403.134" + wire $ternary$libresoc.v:139403$5696_Y + attribute \src "libresoc.v:139404.19-139404.134" + wire $ternary$libresoc.v:139404$5697_Y + attribute \src "libresoc.v:139405.19-139405.133" + wire $ternary$libresoc.v:139405$5698_Y + attribute \src "libresoc.v:139406.19-139406.134" + wire $ternary$libresoc.v:139406$5699_Y + attribute \src "libresoc.v:139407.19-139407.134" + wire $ternary$libresoc.v:139407$5700_Y + attribute \src "libresoc.v:139408.19-139408.133" + wire $ternary$libresoc.v:139408$5701_Y + attribute \src "libresoc.v:139409.19-139409.134" + wire $ternary$libresoc.v:139409$5702_Y + attribute \src "libresoc.v:139411.19-139411.132" + wire $ternary$libresoc.v:139411$5704_Y + attribute \src "libresoc.v:139412.19-139412.132" + wire $ternary$libresoc.v:139412$5705_Y + attribute \src "libresoc.v:139413.19-139413.132" + wire $ternary$libresoc.v:139413$5706_Y + attribute \src "libresoc.v:139414.19-139414.132" + wire $ternary$libresoc.v:139414$5707_Y + attribute \src "libresoc.v:139415.19-139415.132" + wire $ternary$libresoc.v:139415$5708_Y + attribute \src "libresoc.v:139416.19-139416.132" + wire $ternary$libresoc.v:139416$5709_Y + attribute \src "libresoc.v:139417.19-139417.132" + wire $ternary$libresoc.v:139417$5710_Y + attribute \src "libresoc.v:139418.19-139418.132" + wire $ternary$libresoc.v:139418$5711_Y + attribute \src "libresoc.v:139419.19-139419.132" + wire $ternary$libresoc.v:139419$5712_Y + attribute \src "libresoc.v:139420.19-139420.132" + wire $ternary$libresoc.v:139420$5713_Y + attribute \src "libresoc.v:139422.19-139422.133" + wire $ternary$libresoc.v:139422$5715_Y + attribute \src "libresoc.v:139423.19-139423.133" + wire $ternary$libresoc.v:139423$5716_Y + attribute \src "libresoc.v:139424.19-139424.134" + wire $ternary$libresoc.v:139424$5717_Y + attribute \src "libresoc.v:139425.19-139425.132" + wire $ternary$libresoc.v:139425$5718_Y + attribute \src "libresoc.v:139426.19-139426.134" + wire $ternary$libresoc.v:139426$5719_Y + attribute \src "libresoc.v:139427.19-139427.134" + wire $ternary$libresoc.v:139427$5720_Y + attribute \src "libresoc.v:139428.19-139428.134" + wire $ternary$libresoc.v:139428$5721_Y + attribute \src "libresoc.v:139429.19-139429.134" + wire $ternary$libresoc.v:139429$5722_Y + attribute \src "libresoc.v:139430.19-139430.134" + wire $ternary$libresoc.v:139430$5723_Y + attribute \src "libresoc.v:139431.19-139431.134" + wire $ternary$libresoc.v:139431$5724_Y + attribute \src "libresoc.v:139433.19-139433.134" + wire $ternary$libresoc.v:139433$5726_Y + attribute \src "libresoc.v:139434.19-139434.134" + wire $ternary$libresoc.v:139434$5727_Y + attribute \src "libresoc.v:139435.19-139435.135" + wire $ternary$libresoc.v:139435$5728_Y + attribute \src "libresoc.v:139436.19-139436.134" + wire $ternary$libresoc.v:139436$5729_Y + attribute \src "libresoc.v:139437.19-139437.135" + wire $ternary$libresoc.v:139437$5730_Y + attribute \src "libresoc.v:139438.19-139438.135" + wire $ternary$libresoc.v:139438$5731_Y + attribute \src "libresoc.v:139439.19-139439.134" + wire $ternary$libresoc.v:139439$5732_Y + attribute \src "libresoc.v:139440.19-139440.135" + wire $ternary$libresoc.v:139440$5733_Y + attribute \src "libresoc.v:139441.19-139441.136" + wire $ternary$libresoc.v:139441$5734_Y + attribute \src "libresoc.v:139442.19-139442.135" + wire $ternary$libresoc.v:139442$5735_Y + attribute \src "libresoc.v:139444.19-139444.136" + wire $ternary$libresoc.v:139444$5737_Y + attribute \src "libresoc.v:139445.19-139445.136" + wire $ternary$libresoc.v:139445$5738_Y + attribute \src "libresoc.v:139446.19-139446.135" + wire $ternary$libresoc.v:139446$5739_Y + attribute \src "libresoc.v:139447.19-139447.136" + wire $ternary$libresoc.v:139447$5740_Y + attribute \src "libresoc.v:139448.19-139448.136" + wire $ternary$libresoc.v:139448$5741_Y + attribute \src "libresoc.v:139449.19-139449.135" + wire $ternary$libresoc.v:139449$5742_Y + attribute \src "libresoc.v:139450.19-139450.136" + wire $ternary$libresoc.v:139450$5743_Y + attribute \src "libresoc.v:139451.19-139451.136" + wire $ternary$libresoc.v:139451$5744_Y + attribute \src "libresoc.v:139452.19-139452.135" + wire $ternary$libresoc.v:139452$5745_Y + attribute \src "libresoc.v:139453.19-139453.136" + wire $ternary$libresoc.v:139453$5746_Y + attribute \src "libresoc.v:139455.19-139455.136" + wire $ternary$libresoc.v:139455$5748_Y + attribute \src "libresoc.v:139456.19-139456.135" + wire $ternary$libresoc.v:139456$5749_Y + attribute \src "libresoc.v:139457.19-139457.136" + wire $ternary$libresoc.v:139457$5750_Y + attribute \src "libresoc.v:139458.19-139458.136" + wire $ternary$libresoc.v:139458$5751_Y + attribute \src "libresoc.v:139459.19-139459.135" + wire $ternary$libresoc.v:139459$5752_Y + attribute \src "libresoc.v:139460.19-139460.136" + wire $ternary$libresoc.v:139460$5753_Y + attribute \src "libresoc.v:139549.18-139549.130" + wire $ternary$libresoc.v:139549$5843_Y + attribute \src "libresoc.v:139550.18-139550.130" + wire $ternary$libresoc.v:139550$5844_Y + attribute \src "libresoc.v:139551.18-139551.130" + wire $ternary$libresoc.v:139551$5845_Y + attribute \src "libresoc.v:139552.18-139552.131" + wire $ternary$libresoc.v:139552$5846_Y + attribute \src "libresoc.v:139554.18-139554.130" + wire $ternary$libresoc.v:139554$5848_Y + attribute \src "libresoc.v:139555.18-139555.131" + wire $ternary$libresoc.v:139555$5849_Y + attribute \src "libresoc.v:139556.18-139556.131" + wire $ternary$libresoc.v:139556$5850_Y + attribute \src "libresoc.v:139557.18-139557.130" + wire $ternary$libresoc.v:139557$5851_Y + attribute \src "libresoc.v:139558.18-139558.131" + wire $ternary$libresoc.v:139558$5852_Y + attribute \src "libresoc.v:139559.18-139559.132" + wire $ternary$libresoc.v:139559$5853_Y + attribute \src "libresoc.v:139560.18-139560.132" + wire $ternary$libresoc.v:139560$5854_Y + attribute \src "libresoc.v:139561.18-139561.133" + wire $ternary$libresoc.v:139561$5855_Y + attribute \src "libresoc.v:139562.18-139562.133" + wire $ternary$libresoc.v:139562$5856_Y + attribute \src "libresoc.v:139563.18-139563.132" + wire $ternary$libresoc.v:139563$5857_Y + attribute \src "libresoc.v:139565.18-139565.133" + wire $ternary$libresoc.v:139565$5859_Y + attribute \src "libresoc.v:139566.18-139566.133" + wire $ternary$libresoc.v:139566$5860_Y + attribute \src "libresoc.v:139567.18-139567.132" + wire $ternary$libresoc.v:139567$5861_Y + attribute \src "libresoc.v:139568.18-139568.133" + wire $ternary$libresoc.v:139568$5862_Y + attribute \src "libresoc.v:139569.18-139569.133" + wire $ternary$libresoc.v:139569$5863_Y + attribute \src "libresoc.v:139570.18-139570.132" + wire $ternary$libresoc.v:139570$5864_Y + attribute \src "libresoc.v:139571.18-139571.133" + wire $ternary$libresoc.v:139571$5865_Y + attribute \src "libresoc.v:139572.18-139572.133" + wire $ternary$libresoc.v:139572$5866_Y + attribute \src "libresoc.v:139573.18-139573.132" + wire $ternary$libresoc.v:139573$5867_Y + attribute \src "libresoc.v:139574.18-139574.133" + wire $ternary$libresoc.v:139574$5868_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" @@ -218490,35 +218257,35 @@ module \jtag wire \$157 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$159 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$161 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$163 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$165 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$167 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$169 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" wire \$17 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$171 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$173 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$175 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$177 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$179 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$181 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$183 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$185 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$187 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$189 @@ -218548,344 +218315,300 @@ module \jtag wire \$21 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$211 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$213 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$215 + wire \$213 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$217 + wire \$215 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$217 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$219 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$221 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$223 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$225 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$227 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$229 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$231 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$233 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$235 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$237 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$239 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$241 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$243 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$245 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$247 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$249 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$25 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$251 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$253 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$255 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$257 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$259 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$261 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$261 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$263 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$265 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$267 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$269 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$27 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$271 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$273 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$275 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$277 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$279 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$281 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$283 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$285 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$287 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$289 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$291 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$293 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$295 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$297 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$299 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$301 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$303 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$305 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$307 + wire \$305 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$307 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$309 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" wire \$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$311 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$313 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$315 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$317 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$319 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$321 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$323 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$325 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$327 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$329 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$33 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$331 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$333 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$335 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$337 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$339 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$341 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$343 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$345 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$347 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$349 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$35 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$351 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$353 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$355 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$357 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$359 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$361 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$363 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$365 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$367 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$369 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$37 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$371 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$373 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$375 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$377 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$379 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$381 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$383 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$385 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$387 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$389 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$39 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$391 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$393 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$395 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$397 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$399 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$401 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$403 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$405 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$407 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$409 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$41 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$411 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$413 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$415 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$417 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$419 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$421 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$423 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$425 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$427 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$429 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$43 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$431 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$433 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$435 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$437 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$439 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$441 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$443 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$445 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$447 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$449 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$451 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$453 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$455 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$457 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$459 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$461 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$463 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$465 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$467 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$469 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$471 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$473 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$475 + wire \$431 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$477 + wire \$433 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - wire \$479 + wire \$435 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - wire \$480 + wire \$436 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$483 + wire \$439 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$485 + wire \$441 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$487 + wire \$443 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - wire \$489 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - wire \$49 + wire \$445 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - wire width 30 \$491 + wire width 30 \$447 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - wire width 30 \$492 + wire width 30 \$448 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + wire \$45 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - wire width 30 \$494 + wire width 30 \$450 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - wire width 30 \$495 + wire width 30 \$451 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 8 \$497 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - wire \$5 + wire width 8 \$453 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$500 + wire \$456 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$502 + wire \$458 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$504 + wire \$460 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - wire \$506 + wire \$462 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - wire width 5 \$508 + wire width 5 \$464 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - wire width 5 \$509 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$51 + wire width 5 \$465 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - wire width 5 \$511 + wire width 5 \$467 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - wire width 5 \$512 + wire width 5 \$468 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$51 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$53 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" @@ -218939,13 +218662,13 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 325 \TAP_bus__tck + wire input 281 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 163 \TAP_bus__tdi + wire input 141 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 316 \TAP_bus__tdo + wire output 272 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 326 \TAP_bus__tms + wire input 282 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" wire \TAP_tdo attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" @@ -218968,8 +218691,8 @@ module \jtag wire width 4 \_irblock_ir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" wire \_irblock_tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 327 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" + wire input 283 \clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire input 6 \dmi0__ack_o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" @@ -219045,27 +218768,27 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_datasr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 164 \eint_0__core__i + wire output 142 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 11 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 165 \eint_1__core__i + wire output 143 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 12 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 166 \eint_2__core__i + wire output 144 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 13 \eint_2__pad__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire width 3 \fsm_state$499 + wire width 3 \fsm_state$455 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire width 3 \fsm_state$499$next + wire width 3 \fsm_state$455$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \gpio_e10__core__i + wire output 151 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 21 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219073,11 +218796,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 20 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \gpio_e10__pad__o + wire output 152 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \gpio_e10__pad__oe + wire output 153 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 176 \gpio_e11__core__i + wire output 154 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 24 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219085,11 +218808,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 23 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \gpio_e11__pad__o + wire output 155 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \gpio_e11__pad__oe + wire output 156 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \gpio_e12__core__i + wire output 157 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 27 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219097,11 +218820,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 26 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_e12__pad__o + wire output 158 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_e12__pad__oe + wire output 159 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e13__core__i + wire output 160 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 30 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219109,11 +218832,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 29 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e13__pad__o + wire output 161 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e13__pad__oe + wire output 162 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e14__core__i + wire output 163 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 33 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219121,11 +218844,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 32 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e14__pad__o + wire output 164 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e14__pad__oe + wire output 165 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e15__core__i + wire output 166 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 36 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219133,11 +218856,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 35 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e15__pad__o + wire output 167 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e15__pad__oe + wire output 168 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \gpio_e8__core__i + wire output 145 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 15 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219145,11 +218868,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 14 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \gpio_e8__pad__o + wire output 146 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \gpio_e8__pad__oe + wire output 147 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 170 \gpio_e9__core__i + wire output 148 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 18 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219157,11 +218880,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 17 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 171 \gpio_e9__pad__o + wire output 149 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 172 \gpio_e9__pad__oe + wire output 150 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_s0__core__i + wire output 169 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 39 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219169,11 +218892,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 38 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_s0__pad__o + wire output 170 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_s0__pad__oe + wire output 171 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_s1__core__i + wire output 172 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 42 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219181,11 +218904,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 41 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_s1__pad__o + wire output 173 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_s1__pad__oe + wire output 174 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_s2__core__i + wire output 175 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 45 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219193,11 +218916,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 44 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_s2__pad__o + wire output 176 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_s2__pad__oe + wire output 177 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_s3__core__i + wire output 178 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 48 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219205,11 +218928,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 47 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_s3__pad__o + wire output 179 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_s3__pad__oe + wire output 180 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_s4__core__i + wire output 181 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 51 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219217,11 +218940,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 50 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_s4__pad__o + wire output 182 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_s4__pad__oe + wire output 183 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s5__core__i + wire output 184 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 54 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219229,11 +218952,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 53 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s5__pad__o + wire output 185 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s5__pad__oe + wire output 186 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s6__core__i + wire output 187 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 57 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219241,11 +218964,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 56 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s6__pad__o + wire output 188 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s6__pad__oe + wire output 189 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s7__core__i + wire output 190 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 60 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219253,15 +218976,15 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 59 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s7__pad__o + wire output 191 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s7__pad__oe - attribute \src "libresoc.v:137576.7-137576.15" + wire output 192 \gpio_s7__pad__oe + attribute \src "libresoc.v:138052.7-138052.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" - wire width 152 \io_bd + wire width 130 \io_bd attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" - wire width 152 \io_bd$next + wire width 130 \io_bd$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" wire \io_bd2core attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" @@ -219271,31 +218994,31 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" wire \io_shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire width 152 \io_sr + wire width 130 \io_sr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire width 152 \io_sr$next + wire width 130 \io_sr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" wire \io_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 323 \jtag_wb__ack + wire input 279 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 317 \jtag_wb__adr + wire width 29 output 273 \jtag_wb__adr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 29 \jtag_wb__adr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 319 \jtag_wb__cyc + wire output 275 \jtag_wb__cyc attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 324 \jtag_wb__dat_r + wire width 64 input 280 \jtag_wb__dat_r attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 322 \jtag_wb__dat_w + wire width 64 output 278 \jtag_wb__dat_w attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 \jtag_wb__dat_w$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 318 \jtag_wb__sel + wire output 274 \jtag_wb__sel attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 320 \jtag_wb__stb + wire output 276 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 321 \jtag_wb__we + wire output 277 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire width 29 \jtag_wb_addrsr__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" @@ -219357,51 +219080,35 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 62 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \mspi0_clk__pad__o + wire output 193 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 63 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \mspi0_cs_n__pad__o + wire output 194 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \mspi0_miso__core__i + wire output 196 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 65 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 64 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \mspi0_mosi__pad__o + wire output 195 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 66 \mspi1_clk__core__o + wire input 69 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \mspi1_clk__pad__o + wire output 200 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 67 \mspi1_cs_n__core__o + wire output 197 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \mspi1_cs_n__pad__o + wire input 67 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \mspi1_miso__core__i + wire input 68 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \mspi1_miso__pad__i + wire input 66 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \mspi1_mosi__core__o + wire output 198 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 73 \mtwi_scl__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \mtwi_scl__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \mtwi_sda__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 71 \mtwi_sda__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 72 \mtwi_sda__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \mtwi_sda__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \mtwi_sda__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \mtwi_sda__pad__oe + wire output 199 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" wire \negjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" @@ -219410,364 +219117,292 @@ module \jtag wire \posjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \pwm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \pwm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \pwm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 79 \sd0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sd0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \sd0_cmd__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 77 \sd0_cmd__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 78 \sd0_cmd__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \sd0_cmd__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sd0_cmd__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \sd0_cmd__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \sd0_data0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \sd0_data0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \sd0_data0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \sd0_data0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sd0_data0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \sd0_data0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sd0_data1__core__i + wire input 95 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 84 \sd0_data1__core__o + wire output 226 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 85 \sd0_data1__core__oe + wire input 113 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 83 \sd0_data1__pad__i + wire output 244 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \sd0_data1__pad__o + wire input 114 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sd0_data1__pad__oe + wire output 245 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \sd0_data2__core__i + wire input 115 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \sd0_data2__core__o + wire output 246 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \sd0_data2__core__oe + wire input 96 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \sd0_data2__pad__i + wire output 227 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sd0_data2__pad__o + wire input 97 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \sd0_data2__pad__oe + wire output 228 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sd0_data3__core__i + wire input 98 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 90 \sd0_data3__core__o + wire output 229 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 91 \sd0_data3__core__oe + wire input 99 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 89 \sd0_data3__pad__i + wire output 230 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sd0_data3__pad__o + wire input 100 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_data3__pad__oe + wire output 231 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \sdr_a_0__core__o + wire input 101 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_a_0__pad__o + wire output 232 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \sdr_a_10__core__o + wire input 102 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_a_10__pad__o + wire output 233 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \sdr_a_11__core__o + wire input 103 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_a_11__pad__o + wire output 234 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_a_12__core__o + wire input 104 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_a_12__pad__o + wire output 235 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \sdr_a_1__core__o + wire input 105 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_a_1__pad__o + wire output 236 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 119 \sdr_a_2__core__o + wire input 106 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_a_2__pad__o + wire output 237 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 120 \sdr_a_3__core__o + wire input 110 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_a_3__pad__o + wire output 241 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \sdr_a_4__core__o + wire input 108 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_a_4__pad__o + wire output 239 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 122 \sdr_a_5__core__o + wire input 107 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_a_5__pad__o + wire output 238 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \sdr_a_6__core__o + wire input 112 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_a_6__pad__o + wire output 243 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 124 \sdr_a_7__core__o + wire input 70 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_a_7__pad__o + wire output 201 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \sdr_a_8__core__o + wire input 116 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_a_8__pad__o + wire output 247 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 126 \sdr_a_9__core__o + wire output 202 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_a_9__pad__o + wire input 72 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 127 \sdr_ba_0__core__o + wire input 73 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_ba_0__pad__o + wire input 71 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \sdr_ba_1__core__o + wire output 203 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_ba_1__pad__o + wire output 204 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \sdr_cas_n__core__o + wire output 254 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_cas_n__pad__o + wire input 124 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \sdr_cke__core__o + wire input 125 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_cke__pad__o + wire input 123 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \sdr_clock__core__o + wire output 255 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_clock__pad__o + wire output 256 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 134 \sdr_cs_n__core__o + wire output 257 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_cs_n__pad__o + wire input 127 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \sdr_dm_0__core__o + wire input 128 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sdr_dm_0__pad__o + wire input 126 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_dm_1__core__o + wire output 258 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_dm_1__pad__o + wire output 259 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sdr_dq_0__core__i + wire output 260 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \sdr_dq_0__core__o + wire input 130 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 95 \sdr_dq_0__core__oe + wire input 131 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \sdr_dq_0__pad__i + wire input 129 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sdr_dq_0__pad__o + wire output 261 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_dq_0__pad__oe + wire output 262 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_dq_10__core__i + wire output 263 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_dq_10__core__o + wire input 133 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_dq_10__core__oe + wire input 134 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_dq_10__pad__i + wire input 132 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_dq_10__pad__o + wire output 264 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_dq_10__pad__oe + wire output 265 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_11__core__i + wire output 266 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_dq_11__core__o + wire input 136 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_dq_11__core__oe + wire input 137 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_dq_11__pad__i + wire input 135 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_11__pad__o + wire output 267 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_11__pad__oe + wire output 268 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dq_12__core__i + wire output 269 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_12__core__o + wire input 139 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_12__core__oe + wire input 140 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dq_12__pad__i + wire input 138 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_12__pad__o + wire output 270 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dq_12__pad__oe + wire output 271 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_13__core__i + wire output 205 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_13__core__o + wire input 75 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_13__core__oe + wire input 76 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_13__pad__i + wire input 74 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_13__pad__o + wire output 206 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_13__pad__oe + wire output 207 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_14__core__i + wire output 208 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_14__core__o + wire input 78 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_14__core__oe + wire input 79 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_14__pad__i + wire input 77 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_14__pad__o + wire output 209 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_14__pad__oe + wire output 210 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_15__core__i + wire output 211 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_15__core__o + wire input 81 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_15__core__oe + wire input 82 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_15__pad__i + wire input 80 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_15__pad__o + wire output 212 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_15__pad__oe + wire output 213 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sdr_dq_1__core__i + wire output 214 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 97 \sdr_dq_1__core__o + wire input 84 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \sdr_dq_1__core__oe + wire input 85 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 96 \sdr_dq_1__pad__i + wire input 83 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_dq_1__pad__o + wire output 215 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sdr_dq_1__pad__oe + wire output 216 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_dq_2__core__i + wire output 217 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \sdr_dq_2__core__o + wire input 87 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 101 \sdr_dq_2__core__oe + wire input 88 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \sdr_dq_2__pad__i + wire input 86 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sdr_dq_2__pad__o + wire output 218 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_dq_2__pad__oe + wire output 219 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sdr_dq_3__core__i + wire output 220 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 103 \sdr_dq_3__core__o + wire input 90 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \sdr_dq_3__core__oe + wire input 91 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 102 \sdr_dq_3__pad__i + wire input 89 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_dq_3__pad__o + wire output 221 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sdr_dq_3__pad__oe + wire output 222 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_dq_4__core__i + wire output 223 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \sdr_dq_4__core__o + wire input 93 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 107 \sdr_dq_4__core__oe + wire input 94 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \sdr_dq_4__pad__i + wire input 92 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_4__pad__o + wire output 224 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_4__pad__oe + wire output 225 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_5__core__i + wire output 248 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 109 \sdr_dq_5__core__o + wire input 118 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \sdr_dq_5__core__oe + wire input 119 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 108 \sdr_dq_5__pad__i + wire input 117 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_5__pad__o + wire output 249 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_5__pad__oe + wire output 250 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_6__core__i + wire output 251 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \sdr_dq_6__core__o + wire input 121 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 113 \sdr_dq_6__core__oe + wire input 122 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \sdr_dq_6__pad__i + wire input 120 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_6__pad__o + wire output 252 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_6__pad__oe + wire output 253 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_7__core__i + wire input 109 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 115 \sdr_dq_7__core__o + wire output 240 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \sdr_dq_7__core__oe + wire input 111 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 114 \sdr_dq_7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_dq_8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_dq_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_dq_8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_dq_8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_dq_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_dq_8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_dq_9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_dq_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_dq_9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_dq_9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_dq_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \sdr_ras_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_ras_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \sdr_we_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_we_n__pad__o + wire output 242 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire width 3 \sr0__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" @@ -219839,7 +219474,7 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" wire \wb_sram_en$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - cell $add $add$libresoc.v:139217$5900 + cell $add $add$libresoc.v:139537$5830 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -219847,10 +219482,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:139217$5900_Y + connect \Y $add$libresoc.v:139537$5830_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - cell $add $add$libresoc.v:139218$5901 + cell $add $add$libresoc.v:139538$5831 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -219858,10 +219493,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:139218$5901_Y + connect \Y $add$libresoc.v:139538$5831_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - cell $add $add$libresoc.v:139225$5909 + cell $add $add$libresoc.v:139545$5839 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -219869,10 +219504,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:139225$5909_Y + connect \Y $add$libresoc.v:139545$5839_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - cell $add $add$libresoc.v:139226$5910 + cell $add $add$libresoc.v:139546$5840 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -219880,10 +219515,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:139226$5910_Y + connect \Y $add$libresoc.v:139546$5840_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - cell $and $and$libresoc.v:139043$5726 + cell $and $and$libresoc.v:139387$5680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219891,10 +219526,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$15 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139043$5726_Y + connect \Y $and$libresoc.v:139387$5680_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:139110$5793 + cell $and $and$libresoc.v:139454$5747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219902,10 +219537,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$27 - connect \Y $and$libresoc.v:139110$5793_Y + connect \Y $and$libresoc.v:139454$5747_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" - cell $and $and$libresoc.v:139121$5804 + cell $and $and$libresoc.v:139465$5758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219913,307 +219548,307 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$29 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139121$5804_Y + connect \Y $and$libresoc.v:139465$5758_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:139147$5830 + cell $and $and$libresoc.v:139467$5760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_fsm_isdr - connect \B \$363 - connect \Y $and$libresoc.v:139147$5830_Y + connect \B \$319 + connect \Y $and$libresoc.v:139467$5760_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139150$5833 + cell $and $and$libresoc.v:139470$5763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$369 + connect \A \$325 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139150$5833_Y + connect \Y $and$libresoc.v:139470$5763_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139152$5835 + cell $and $and$libresoc.v:139472$5765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$373 + connect \A \$329 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139152$5835_Y + connect \Y $and$libresoc.v:139472$5765_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139155$5838 + cell $and $and$libresoc.v:139474$5767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$377 + connect \A \$333 connect \B \_fsm_update - connect \Y $and$libresoc.v:139155$5838_Y + connect \Y $and$libresoc.v:139474$5767_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139157$5840 + cell $and $and$libresoc.v:139477$5770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core_prev - connect \B \$381 - connect \Y $and$libresoc.v:139157$5840_Y + connect \B \$337 + connect \Y $and$libresoc.v:139477$5770_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139160$5843 + cell $and $and$libresoc.v:139480$5773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$387 + connect \A \$343 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139160$5843_Y + connect \Y $and$libresoc.v:139480$5773_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139162$5845 + cell $and $and$libresoc.v:139482$5775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$391 + connect \A \$347 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139162$5845_Y + connect \Y $and$libresoc.v:139482$5775_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139164$5847 + cell $and $and$libresoc.v:139484$5777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$395 + connect \A \$351 connect \B \_fsm_update - connect \Y $and$libresoc.v:139164$5847_Y + connect \Y $and$libresoc.v:139484$5777_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139168$5851 + cell $and $and$libresoc.v:139486$5779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core_prev - connect \B \$399 - connect \Y $and$libresoc.v:139168$5851_Y + connect \B \$355 + connect \Y $and$libresoc.v:139486$5779_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139172$5855 + cell $and $and$libresoc.v:139491$5784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$407 + connect \A \$363 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139172$5855_Y + connect \Y $and$libresoc.v:139491$5784_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139174$5857 + cell $and $and$libresoc.v:139493$5786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$411 + connect \A \$367 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139174$5857_Y + connect \Y $and$libresoc.v:139493$5786_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139176$5859 + cell $and $and$libresoc.v:139495$5788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$415 + connect \A \$371 connect \B \_fsm_update - connect \Y $and$libresoc.v:139176$5859_Y + connect \Y $and$libresoc.v:139495$5788_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139179$5862 + cell $and $and$libresoc.v:139497$5790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core_prev - connect \B \$419 - connect \Y $and$libresoc.v:139179$5862_Y + connect \B \$375 + connect \Y $and$libresoc.v:139497$5790_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139182$5865 + cell $and $and$libresoc.v:139501$5794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$425 + connect \A \$381 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139182$5865_Y + connect \Y $and$libresoc.v:139501$5794_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139184$5867 + cell $and $and$libresoc.v:139503$5796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$429 + connect \A \$385 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139184$5867_Y + connect \Y $and$libresoc.v:139503$5796_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139186$5869 + cell $and $and$libresoc.v:139505$5798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$433 + connect \A \$389 connect \B \_fsm_update - connect \Y $and$libresoc.v:139186$5869_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:139188$5871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$41 - connect \Y $and$libresoc.v:139188$5871_Y + connect \Y $and$libresoc.v:139505$5798_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139189$5872 + cell $and $and$libresoc.v:139507$5800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core_prev - connect \B \$437 - connect \Y $and$libresoc.v:139189$5872_Y + connect \B \$393 + connect \Y $and$libresoc.v:139507$5800_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139193$5876 + cell $and $and$libresoc.v:139513$5806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$445 + connect \A \$401 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139193$5876_Y + connect \Y $and$libresoc.v:139513$5806_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139195$5878 + cell $and $and$libresoc.v:139515$5808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$449 + connect \A \$405 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139195$5878_Y + connect \Y $and$libresoc.v:139515$5808_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139197$5880 + cell $and $and$libresoc.v:139517$5810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$453 + connect \A \$409 connect \B \_fsm_update - connect \Y $and$libresoc.v:139197$5880_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - cell $and $and$libresoc.v:139199$5882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$43 - connect \B \_fsm_update - connect \Y $and$libresoc.v:139199$5882_Y + connect \Y $and$libresoc.v:139517$5810_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139200$5883 + cell $and $and$libresoc.v:139519$5812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core_prev - connect \B \$457 - connect \Y $and$libresoc.v:139200$5883_Y + connect \B \$413 + connect \Y $and$libresoc.v:139519$5812_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139203$5886 + cell $and $and$libresoc.v:139523$5816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$463 + connect \A \$419 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139203$5886_Y + connect \Y $and$libresoc.v:139523$5816_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139205$5888 + cell $and $and$libresoc.v:139525$5818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$467 + connect \A \$423 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139205$5888_Y + connect \Y $and$libresoc.v:139525$5818_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139207$5890 + cell $and $and$libresoc.v:139527$5820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$471 + connect \A \$427 connect \B \_fsm_update - connect \Y $and$libresoc.v:139207$5890_Y + connect \Y $and$libresoc.v:139527$5820_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139209$5892 + cell $and $and$libresoc.v:139529$5822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_update_core_prev - connect \B \$475 - connect \Y $and$libresoc.v:139209$5892_Y + connect \B \$431 + connect \Y $and$libresoc.v:139529$5822_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:139532$5825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$41 + connect \Y $and$libresoc.v:139532$5825_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + cell $and $and$libresoc.v:139542$5836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B \_fsm_update + connect \Y $and$libresoc.v:139542$5836_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $and $and$libresoc.v:139242$5926 + cell $and $and$libresoc.v:139564$5858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220221,10 +219856,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$5 - connect \Y $and$libresoc.v:139242$5926_Y + connect \Y $and$libresoc.v:139564$5858_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:138999$5682 + cell $eq $eq$libresoc.v:139343$5636 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220232,10 +219867,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 - connect \Y $eq$libresoc.v:138999$5682_Y + connect \Y $eq$libresoc.v:139343$5636_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139010$5693 + cell $eq $eq$libresoc.v:139354$5647 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220243,10 +219878,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139010$5693_Y + connect \Y $eq$libresoc.v:139354$5647_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139021$5704 + cell $eq $eq$libresoc.v:139365$5658 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220254,10 +219889,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139021$5704_Y + connect \Y $eq$libresoc.v:139365$5658_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:139054$5737 + cell $eq $eq$libresoc.v:139398$5691 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220265,10 +219900,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'1 - connect \Y $eq$libresoc.v:139054$5737_Y + connect \Y $eq$libresoc.v:139398$5691_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139055$5738 + cell $eq $eq$libresoc.v:139399$5692 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220276,10 +219911,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139055$5738_Y + connect \Y $eq$libresoc.v:139399$5692_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139066$5749 + cell $eq $eq$libresoc.v:139410$5703 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220287,10 +219922,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139066$5749_Y + connect \Y $eq$libresoc.v:139410$5703_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:139088$5771 + cell $eq $eq$libresoc.v:139432$5725 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220298,10 +219933,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139088$5771_Y + connect \Y $eq$libresoc.v:139432$5725_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139132$5815 + cell $eq $eq$libresoc.v:139461$5754 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220309,32 +219944,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139132$5815_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139141$5824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:139141$5824_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139142$5825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:139142$5825_Y + connect \Y $eq$libresoc.v:139461$5754_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139143$5826 + cell $eq $eq$libresoc.v:139462$5755 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220342,10 +219955,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139143$5826_Y + connect \Y $eq$libresoc.v:139462$5755_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:139145$5828 + cell $eq $eq$libresoc.v:139464$5757 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220353,10 +219966,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139145$5828_Y + connect \Y $eq$libresoc.v:139464$5757_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139148$5831 + cell $eq $eq$libresoc.v:139468$5761 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220364,32 +219977,32 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'100 - connect \Y $eq$libresoc.v:139148$5831_Y + connect \Y $eq$libresoc.v:139468$5761_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139158$5841 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:139476$5769 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 3'101 - connect \Y $eq$libresoc.v:139158$5841_Y + connect \B 1'0 + connect \Y $eq$libresoc.v:139476$5769_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:139165$5848 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:139478$5771 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:139165$5848_Y + connect \B 3'101 + connect \Y $eq$libresoc.v:139478$5771_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:139166$5849 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:139487$5780 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220397,10 +220010,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139166$5849_Y + connect \Y $eq$libresoc.v:139487$5780_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139169$5852 + cell $eq $eq$libresoc.v:139488$5781 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220408,10 +220021,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'110 - connect \Y $eq$libresoc.v:139169$5852_Y + connect \Y $eq$libresoc.v:139488$5781_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139170$5853 + cell $eq $eq$libresoc.v:139489$5782 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220419,10 +220032,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'111 - connect \Y $eq$libresoc.v:139170$5853_Y + connect \Y $eq$libresoc.v:139489$5782_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139180$5863 + cell $eq $eq$libresoc.v:139499$5792 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220430,10 +220043,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1000 - connect \Y $eq$libresoc.v:139180$5863_Y + connect \Y $eq$libresoc.v:139499$5792_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139190$5873 + cell $eq $eq$libresoc.v:139508$5801 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220441,43 +220054,54 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1001 - connect \Y $eq$libresoc.v:139190$5873_Y + connect \Y $eq$libresoc.v:139508$5801_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139191$5874 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $eq $eq$libresoc.v:139509$5802 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 4'1010 - connect \Y $eq$libresoc.v:139191$5874_Y + connect \B 4'1111 + connect \Y $eq$libresoc.v:139509$5802_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + cell $eq $eq$libresoc.v:139510$5803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:139510$5803_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139201$5884 + cell $eq $eq$libresoc.v:139511$5804 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 4'1011 - connect \Y $eq$libresoc.v:139201$5884_Y + connect \B 4'1010 + connect \Y $eq$libresoc.v:139511$5804_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - cell $eq $eq$libresoc.v:139210$5893 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:139520$5813 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:139210$5893_Y + connect \B 4'1011 + connect \Y $eq$libresoc.v:139520$5813_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $eq $eq$libresoc.v:139211$5894 + cell $eq $eq$libresoc.v:139530$5823 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220485,10 +220109,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'0 - connect \Y $eq$libresoc.v:139211$5894_Y + connect \Y $eq$libresoc.v:139530$5823_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:139213$5896 + cell $eq $eq$libresoc.v:139533$5826 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220496,10 +220120,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'1 - connect \Y $eq$libresoc.v:139213$5896_Y + connect \Y $eq$libresoc.v:139533$5826_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:139214$5897 + cell $eq $eq$libresoc.v:139534$5827 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220507,10 +220131,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:139214$5897_Y + connect \Y $eq$libresoc.v:139534$5827_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - cell $eq $eq$libresoc.v:139216$5899 + cell $eq $eq$libresoc.v:139536$5829 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220518,62 +220142,73 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:139216$5899_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - cell $eq $eq$libresoc.v:139220$5904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:139220$5904_Y + connect \Y $eq$libresoc.v:139536$5829_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:139221$5905 + cell $eq $eq$libresoc.v:139540$5834 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fsm_state$499 + connect \A \fsm_state$455 connect \B 1'1 - connect \Y $eq$libresoc.v:139221$5905_Y + connect \Y $eq$libresoc.v:139540$5834_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:139222$5906 + cell $eq $eq$libresoc.v:139541$5835 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \fsm_state$499 + connect \A \fsm_state$455 connect \B 2'10 - connect \Y $eq$libresoc.v:139222$5906_Y + connect \Y $eq$libresoc.v:139541$5835_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - cell $eq $eq$libresoc.v:139224$5908 + cell $eq $eq$libresoc.v:139544$5838 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \fsm_state$499 + connect \A \fsm_state$455 connect \B 2'10 - connect \Y $eq$libresoc.v:139224$5908_Y + connect \Y $eq$libresoc.v:139544$5838_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" + cell $eq $eq$libresoc.v:139547$5841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:139547$5841_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" + cell $eq $eq$libresoc.v:139548$5842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:139548$5842_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $extend$libresoc.v:139219$5902 + cell $pos $extend$libresoc.v:139539$5832 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \dmi0__addr_i - connect \Y $extend$libresoc.v:139219$5902_Y + connect \Y $extend$libresoc.v:139539$5832_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139149$5832 + cell $ne $ne$libresoc.v:139469$5762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220581,10 +220216,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139149$5832_Y + connect \Y $ne$libresoc.v:139469$5762_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139151$5834 + cell $ne $ne$libresoc.v:139471$5764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220592,10 +220227,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139151$5834_Y + connect \Y $ne$libresoc.v:139471$5764_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139153$5836 + cell $ne $ne$libresoc.v:139473$5766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220603,10 +220238,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139153$5836_Y + connect \Y $ne$libresoc.v:139473$5766_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139159$5842 + cell $ne $ne$libresoc.v:139479$5772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220614,10 +220249,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139159$5842_Y + connect \Y $ne$libresoc.v:139479$5772_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139161$5844 + cell $ne $ne$libresoc.v:139481$5774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220625,10 +220260,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139161$5844_Y + connect \Y $ne$libresoc.v:139481$5774_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139163$5846 + cell $ne $ne$libresoc.v:139483$5776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220636,10 +220271,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139163$5846_Y + connect \Y $ne$libresoc.v:139483$5776_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139171$5854 + cell $ne $ne$libresoc.v:139490$5783 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220647,10 +220282,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139171$5854_Y + connect \Y $ne$libresoc.v:139490$5783_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139173$5856 + cell $ne $ne$libresoc.v:139492$5785 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220658,10 +220293,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139173$5856_Y + connect \Y $ne$libresoc.v:139492$5785_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139175$5858 + cell $ne $ne$libresoc.v:139494$5787 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220669,10 +220304,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139175$5858_Y + connect \Y $ne$libresoc.v:139494$5787_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139181$5864 + cell $ne $ne$libresoc.v:139500$5793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220680,10 +220315,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139181$5864_Y + connect \Y $ne$libresoc.v:139500$5793_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139183$5866 + cell $ne $ne$libresoc.v:139502$5795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220691,10 +220326,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139183$5866_Y + connect \Y $ne$libresoc.v:139502$5795_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139185$5868 + cell $ne $ne$libresoc.v:139504$5797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220702,10 +220337,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139185$5868_Y + connect \Y $ne$libresoc.v:139504$5797_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139192$5875 + cell $ne $ne$libresoc.v:139512$5805 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220713,10 +220348,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139192$5875_Y + connect \Y $ne$libresoc.v:139512$5805_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139194$5877 + cell $ne $ne$libresoc.v:139514$5807 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220724,10 +220359,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139194$5877_Y + connect \Y $ne$libresoc.v:139514$5807_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139196$5879 + cell $ne $ne$libresoc.v:139516$5809 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220735,10 +220370,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139196$5879_Y + connect \Y $ne$libresoc.v:139516$5809_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139202$5885 + cell $ne $ne$libresoc.v:139522$5815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220746,10 +220381,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139202$5885_Y + connect \Y $ne$libresoc.v:139522$5815_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139204$5887 + cell $ne $ne$libresoc.v:139524$5817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220757,10 +220392,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139204$5887_Y + connect \Y $ne$libresoc.v:139524$5817_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139206$5889 + cell $ne $ne$libresoc.v:139526$5819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220768,66 +220403,66 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139206$5889_Y + connect \Y $ne$libresoc.v:139526$5819_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139156$5839 + cell $not $not$libresoc.v:139475$5768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core - connect \Y $not$libresoc.v:139156$5839_Y + connect \Y $not$libresoc.v:139475$5768_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139167$5850 + cell $not $not$libresoc.v:139485$5778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core - connect \Y $not$libresoc.v:139167$5850_Y + connect \Y $not$libresoc.v:139485$5778_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139178$5861 + cell $not $not$libresoc.v:139496$5789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core - connect \Y $not$libresoc.v:139178$5861_Y + connect \Y $not$libresoc.v:139496$5789_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139187$5870 + cell $not $not$libresoc.v:139506$5799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core - connect \Y $not$libresoc.v:139187$5870_Y + connect \Y $not$libresoc.v:139506$5799_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139198$5881 + cell $not $not$libresoc.v:139518$5811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core - connect \Y $not$libresoc.v:139198$5881_Y + connect \Y $not$libresoc.v:139518$5811_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139208$5891 + cell $not $not$libresoc.v:139528$5821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_update_core - connect \Y $not$libresoc.v:139208$5891_Y + connect \Y $not$libresoc.v:139528$5821_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $not $not$libresoc.v:139212$5895 + cell $not $not$libresoc.v:139531$5824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$480 - connect \Y $not$libresoc.v:139212$5895_Y + connect \A \$436 + connect \Y $not$libresoc.v:139531$5824_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139032$5715 + cell $or $or$libresoc.v:139376$5669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220835,10 +220470,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$11 connect \B \$13 - connect \Y $or$libresoc.v:139032$5715_Y + connect \Y $or$libresoc.v:139376$5669_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139077$5760 + cell $or $or$libresoc.v:139421$5714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220846,10 +220481,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$19 connect \B \$21 - connect \Y $or$libresoc.v:139077$5760_Y + connect \Y $or$libresoc.v:139421$5714_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:139099$5782 + cell $or $or$libresoc.v:139443$5736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220857,32 +220492,32 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:139099$5782_Y + connect \Y $or$libresoc.v:139443$5736_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139144$5827 + cell $or $or$libresoc.v:139463$5756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$355 - connect \B \$357 - connect \Y $or$libresoc.v:139144$5827_Y + connect \A \$311 + connect \B \$313 + connect \Y $or$libresoc.v:139463$5756_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:139146$5829 + cell $or $or$libresoc.v:139466$5759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$359 - connect \B \$361 - connect \Y $or$libresoc.v:139146$5829_Y + connect \A \$315 + connect \B \$317 + connect \Y $or$libresoc.v:139466$5759_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139154$5837 + cell $or $or$libresoc.v:139498$5791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220890,10 +220525,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:139154$5837_Y + connect \Y $or$libresoc.v:139498$5791_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:139177$5860 + cell $or $or$libresoc.v:139521$5814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220901,32 +220536,32 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:139177$5860_Y + connect \Y $or$libresoc.v:139521$5814_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $or $or$libresoc.v:139215$5898 + cell $or $or$libresoc.v:139535$5828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$483 - connect \B \$485 - connect \Y $or$libresoc.v:139215$5898_Y + connect \A \$439 + connect \B \$441 + connect \Y $or$libresoc.v:139535$5828_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $or $or$libresoc.v:139223$5907 + cell $or $or$libresoc.v:139543$5837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$500 - connect \B \$502 - connect \Y $or$libresoc.v:139223$5907_Y + connect \A \$456 + connect \B \$458 + connect \Y $or$libresoc.v:139543$5837_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $or $or$libresoc.v:139231$5915 + cell $or $or$libresoc.v:139553$5847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220934,1234 +220569,1058 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $or$libresoc.v:139231$5915_Y + connect \Y $or$libresoc.v:139553$5847_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $pos$libresoc.v:139219$5903 + cell $pos $pos$libresoc.v:139539$5833 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:139219$5902_Y - connect \Y $pos$libresoc.v:139219$5903_Y + connect \A $extend$libresoc.v:139539$5832_Y + connect \Y $pos$libresoc.v:139539$5833_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139000$5683 + cell $mux $ternary$libresoc.v:139344$5637 parameter \WIDTH 1 connect \A \gpio_e15__pad__i connect \B \io_bd [24] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139000$5683_Y + connect \Y $ternary$libresoc.v:139344$5637_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139001$5684 + cell $mux $ternary$libresoc.v:139345$5638 parameter \WIDTH 1 connect \A \gpio_e15__core__o connect \B \io_bd [25] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139001$5684_Y + connect \Y $ternary$libresoc.v:139345$5638_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139002$5685 + cell $mux $ternary$libresoc.v:139346$5639 parameter \WIDTH 1 connect \A \gpio_e15__core__oe connect \B \io_bd [26] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139002$5685_Y + connect \Y $ternary$libresoc.v:139346$5639_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139003$5686 + cell $mux $ternary$libresoc.v:139347$5640 parameter \WIDTH 1 connect \A \gpio_s0__pad__i connect \B \io_bd [27] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139003$5686_Y + connect \Y $ternary$libresoc.v:139347$5640_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139004$5687 + cell $mux $ternary$libresoc.v:139348$5641 parameter \WIDTH 1 connect \A \gpio_s0__core__o connect \B \io_bd [28] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139004$5687_Y + connect \Y $ternary$libresoc.v:139348$5641_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139005$5688 + cell $mux $ternary$libresoc.v:139349$5642 parameter \WIDTH 1 connect \A \gpio_s0__core__oe connect \B \io_bd [29] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139005$5688_Y + connect \Y $ternary$libresoc.v:139349$5642_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139006$5689 + cell $mux $ternary$libresoc.v:139350$5643 parameter \WIDTH 1 connect \A \gpio_s1__pad__i connect \B \io_bd [30] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139006$5689_Y + connect \Y $ternary$libresoc.v:139350$5643_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139007$5690 + cell $mux $ternary$libresoc.v:139351$5644 parameter \WIDTH 1 connect \A \gpio_s1__core__o connect \B \io_bd [31] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139007$5690_Y + connect \Y $ternary$libresoc.v:139351$5644_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139008$5691 + cell $mux $ternary$libresoc.v:139352$5645 parameter \WIDTH 1 connect \A \gpio_s1__core__oe connect \B \io_bd [32] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139008$5691_Y + connect \Y $ternary$libresoc.v:139352$5645_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139009$5692 + cell $mux $ternary$libresoc.v:139353$5646 parameter \WIDTH 1 connect \A \gpio_s2__pad__i connect \B \io_bd [33] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139009$5692_Y + connect \Y $ternary$libresoc.v:139353$5646_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139011$5694 + cell $mux $ternary$libresoc.v:139355$5648 parameter \WIDTH 1 connect \A \gpio_s2__core__o connect \B \io_bd [34] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139011$5694_Y + connect \Y $ternary$libresoc.v:139355$5648_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139012$5695 + cell $mux $ternary$libresoc.v:139356$5649 parameter \WIDTH 1 connect \A \gpio_s2__core__oe connect \B \io_bd [35] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139012$5695_Y + connect \Y $ternary$libresoc.v:139356$5649_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139013$5696 + cell $mux $ternary$libresoc.v:139357$5650 parameter \WIDTH 1 connect \A \gpio_s3__pad__i connect \B \io_bd [36] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139013$5696_Y + connect \Y $ternary$libresoc.v:139357$5650_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139014$5697 + cell $mux $ternary$libresoc.v:139358$5651 parameter \WIDTH 1 connect \A \gpio_s3__core__o connect \B \io_bd [37] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139014$5697_Y + connect \Y $ternary$libresoc.v:139358$5651_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139015$5698 + cell $mux $ternary$libresoc.v:139359$5652 parameter \WIDTH 1 connect \A \gpio_s3__core__oe connect \B \io_bd [38] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139015$5698_Y + connect \Y $ternary$libresoc.v:139359$5652_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139016$5699 + cell $mux $ternary$libresoc.v:139360$5653 parameter \WIDTH 1 connect \A \gpio_s4__pad__i connect \B \io_bd [39] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139016$5699_Y + connect \Y $ternary$libresoc.v:139360$5653_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139017$5700 + cell $mux $ternary$libresoc.v:139361$5654 parameter \WIDTH 1 connect \A \gpio_s4__core__o connect \B \io_bd [40] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139017$5700_Y + connect \Y $ternary$libresoc.v:139361$5654_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139018$5701 + cell $mux $ternary$libresoc.v:139362$5655 parameter \WIDTH 1 connect \A \gpio_s4__core__oe connect \B \io_bd [41] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139018$5701_Y + connect \Y $ternary$libresoc.v:139362$5655_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139019$5702 + cell $mux $ternary$libresoc.v:139363$5656 parameter \WIDTH 1 connect \A \gpio_s5__pad__i connect \B \io_bd [42] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139019$5702_Y + connect \Y $ternary$libresoc.v:139363$5656_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139020$5703 + cell $mux $ternary$libresoc.v:139364$5657 parameter \WIDTH 1 connect \A \gpio_s5__core__o connect \B \io_bd [43] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139020$5703_Y + connect \Y $ternary$libresoc.v:139364$5657_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139022$5705 + cell $mux $ternary$libresoc.v:139366$5659 parameter \WIDTH 1 connect \A \gpio_s5__core__oe connect \B \io_bd [44] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139022$5705_Y + connect \Y $ternary$libresoc.v:139366$5659_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139023$5706 + cell $mux $ternary$libresoc.v:139367$5660 parameter \WIDTH 1 connect \A \gpio_s6__pad__i connect \B \io_bd [45] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139023$5706_Y + connect \Y $ternary$libresoc.v:139367$5660_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139024$5707 + cell $mux $ternary$libresoc.v:139368$5661 parameter \WIDTH 1 connect \A \gpio_s6__core__o connect \B \io_bd [46] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139024$5707_Y + connect \Y $ternary$libresoc.v:139368$5661_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139025$5708 + cell $mux $ternary$libresoc.v:139369$5662 parameter \WIDTH 1 connect \A \gpio_s6__core__oe connect \B \io_bd [47] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139025$5708_Y + connect \Y $ternary$libresoc.v:139369$5662_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139026$5709 + cell $mux $ternary$libresoc.v:139370$5663 parameter \WIDTH 1 connect \A \gpio_s7__pad__i connect \B \io_bd [48] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139026$5709_Y + connect \Y $ternary$libresoc.v:139370$5663_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139027$5710 + cell $mux $ternary$libresoc.v:139371$5664 parameter \WIDTH 1 connect \A \gpio_s7__core__o connect \B \io_bd [49] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139027$5710_Y + connect \Y $ternary$libresoc.v:139371$5664_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139028$5711 + cell $mux $ternary$libresoc.v:139372$5665 parameter \WIDTH 1 connect \A \gpio_s7__core__oe connect \B \io_bd [50] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139028$5711_Y + connect \Y $ternary$libresoc.v:139372$5665_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139029$5712 + cell $mux $ternary$libresoc.v:139373$5666 parameter \WIDTH 1 connect \A \mspi0_clk__core__o connect \B \io_bd [51] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139029$5712_Y + connect \Y $ternary$libresoc.v:139373$5666_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139030$5713 + cell $mux $ternary$libresoc.v:139374$5667 parameter \WIDTH 1 connect \A \mspi0_cs_n__core__o connect \B \io_bd [52] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139030$5713_Y + connect \Y $ternary$libresoc.v:139374$5667_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139031$5714 + cell $mux $ternary$libresoc.v:139375$5668 parameter \WIDTH 1 connect \A \mspi0_mosi__core__o connect \B \io_bd [53] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139031$5714_Y + connect \Y $ternary$libresoc.v:139375$5668_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139033$5716 + cell $mux $ternary$libresoc.v:139377$5670 parameter \WIDTH 1 connect \A \mspi0_miso__pad__i connect \B \io_bd [54] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139033$5716_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139034$5717 - parameter \WIDTH 1 - connect \A \mspi1_clk__core__o - connect \B \io_bd [55] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139034$5717_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139035$5718 - parameter \WIDTH 1 - connect \A \mspi1_cs_n__core__o - connect \B \io_bd [56] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139035$5718_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139036$5719 - parameter \WIDTH 1 - connect \A \mspi1_mosi__core__o - connect \B \io_bd [57] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139036$5719_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139037$5720 - parameter \WIDTH 1 - connect \A \mspi1_miso__pad__i - connect \B \io_bd [58] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139037$5720_Y + connect \Y $ternary$libresoc.v:139377$5670_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139038$5721 + cell $mux $ternary$libresoc.v:139378$5671 parameter \WIDTH 1 connect \A \mtwi_sda__pad__i - connect \B \io_bd [59] + connect \B \io_bd [55] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139038$5721_Y + connect \Y $ternary$libresoc.v:139378$5671_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139039$5722 + cell $mux $ternary$libresoc.v:139379$5672 parameter \WIDTH 1 connect \A \mtwi_sda__core__o - connect \B \io_bd [60] + connect \B \io_bd [56] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139039$5722_Y + connect \Y $ternary$libresoc.v:139379$5672_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139040$5723 + cell $mux $ternary$libresoc.v:139380$5673 parameter \WIDTH 1 connect \A \mtwi_sda__core__oe - connect \B \io_bd [61] + connect \B \io_bd [57] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139040$5723_Y + connect \Y $ternary$libresoc.v:139380$5673_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139041$5724 + cell $mux $ternary$libresoc.v:139381$5674 parameter \WIDTH 1 connect \A \mtwi_scl__core__o - connect \B \io_bd [62] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139041$5724_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139042$5725 - parameter \WIDTH 1 - connect \A \pwm_0__core__o - connect \B \io_bd [63] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139042$5725_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139044$5727 - parameter \WIDTH 1 - connect \A \pwm_1__core__o - connect \B \io_bd [64] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139044$5727_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139045$5728 - parameter \WIDTH 1 - connect \A \sd0_cmd__pad__i - connect \B \io_bd [65] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139045$5728_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139046$5729 - parameter \WIDTH 1 - connect \A \sd0_cmd__core__o - connect \B \io_bd [66] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139046$5729_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139047$5730 - parameter \WIDTH 1 - connect \A \sd0_cmd__core__oe - connect \B \io_bd [67] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139047$5730_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139048$5731 - parameter \WIDTH 1 - connect \A \sd0_clk__core__o - connect \B \io_bd [68] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139048$5731_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139049$5732 - parameter \WIDTH 1 - connect \A \sd0_data0__pad__i - connect \B \io_bd [69] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139049$5732_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139050$5733 - parameter \WIDTH 1 - connect \A \sd0_data0__core__o - connect \B \io_bd [70] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139050$5733_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139051$5734 - parameter \WIDTH 1 - connect \A \sd0_data0__core__oe - connect \B \io_bd [71] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139051$5734_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139052$5735 - parameter \WIDTH 1 - connect \A \sd0_data1__pad__i - connect \B \io_bd [72] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139052$5735_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139053$5736 - parameter \WIDTH 1 - connect \A \sd0_data1__core__o - connect \B \io_bd [73] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139053$5736_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139056$5739 - parameter \WIDTH 1 - connect \A \sd0_data1__core__oe - connect \B \io_bd [74] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139056$5739_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139057$5740 - parameter \WIDTH 1 - connect \A \sd0_data2__pad__i - connect \B \io_bd [75] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139057$5740_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139058$5741 - parameter \WIDTH 1 - connect \A \sd0_data2__core__o - connect \B \io_bd [76] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139058$5741_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139059$5742 - parameter \WIDTH 1 - connect \A \sd0_data2__core__oe - connect \B \io_bd [77] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139059$5742_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139060$5743 - parameter \WIDTH 1 - connect \A \sd0_data3__pad__i - connect \B \io_bd [78] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139060$5743_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139061$5744 - parameter \WIDTH 1 - connect \A \sd0_data3__core__o - connect \B \io_bd [79] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139061$5744_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139062$5745 - parameter \WIDTH 1 - connect \A \sd0_data3__core__oe - connect \B \io_bd [80] + connect \B \io_bd [58] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139062$5745_Y + connect \Y $ternary$libresoc.v:139381$5674_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139063$5746 + cell $mux $ternary$libresoc.v:139382$5675 parameter \WIDTH 1 connect \A \sdr_dm_0__core__o - connect \B \io_bd [81] + connect \B \io_bd [59] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139063$5746_Y + connect \Y $ternary$libresoc.v:139382$5675_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139064$5747 + cell $mux $ternary$libresoc.v:139383$5676 parameter \WIDTH 1 connect \A \sdr_dq_0__pad__i - connect \B \io_bd [82] + connect \B \io_bd [60] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139064$5747_Y + connect \Y $ternary$libresoc.v:139383$5676_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139065$5748 + cell $mux $ternary$libresoc.v:139384$5677 parameter \WIDTH 1 connect \A \sdr_dq_0__core__o - connect \B \io_bd [83] + connect \B \io_bd [61] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139065$5748_Y + connect \Y $ternary$libresoc.v:139384$5677_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139067$5750 + cell $mux $ternary$libresoc.v:139385$5678 parameter \WIDTH 1 connect \A \sdr_dq_0__core__oe - connect \B \io_bd [84] + connect \B \io_bd [62] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139067$5750_Y + connect \Y $ternary$libresoc.v:139385$5678_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139068$5751 + cell $mux $ternary$libresoc.v:139386$5679 parameter \WIDTH 1 connect \A \sdr_dq_1__pad__i - connect \B \io_bd [85] + connect \B \io_bd [63] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139068$5751_Y + connect \Y $ternary$libresoc.v:139386$5679_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139069$5752 + cell $mux $ternary$libresoc.v:139388$5681 parameter \WIDTH 1 connect \A \sdr_dq_1__core__o - connect \B \io_bd [86] + connect \B \io_bd [64] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139069$5752_Y + connect \Y $ternary$libresoc.v:139388$5681_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139070$5753 + cell $mux $ternary$libresoc.v:139389$5682 parameter \WIDTH 1 connect \A \sdr_dq_1__core__oe - connect \B \io_bd [87] + connect \B \io_bd [65] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139070$5753_Y + connect \Y $ternary$libresoc.v:139389$5682_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139071$5754 + cell $mux $ternary$libresoc.v:139390$5683 parameter \WIDTH 1 connect \A \sdr_dq_2__pad__i - connect \B \io_bd [88] + connect \B \io_bd [66] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139071$5754_Y + connect \Y $ternary$libresoc.v:139390$5683_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139072$5755 + cell $mux $ternary$libresoc.v:139391$5684 parameter \WIDTH 1 connect \A \sdr_dq_2__core__o - connect \B \io_bd [89] + connect \B \io_bd [67] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139072$5755_Y + connect \Y $ternary$libresoc.v:139391$5684_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139073$5756 + cell $mux $ternary$libresoc.v:139392$5685 parameter \WIDTH 1 connect \A \sdr_dq_2__core__oe - connect \B \io_bd [90] + connect \B \io_bd [68] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139073$5756_Y + connect \Y $ternary$libresoc.v:139392$5685_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139074$5757 + cell $mux $ternary$libresoc.v:139393$5686 parameter \WIDTH 1 connect \A \sdr_dq_3__pad__i - connect \B \io_bd [91] + connect \B \io_bd [69] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139074$5757_Y + connect \Y $ternary$libresoc.v:139393$5686_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139075$5758 + cell $mux $ternary$libresoc.v:139394$5687 parameter \WIDTH 1 connect \A \sdr_dq_3__core__o - connect \B \io_bd [92] + connect \B \io_bd [70] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139075$5758_Y + connect \Y $ternary$libresoc.v:139394$5687_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139076$5759 + cell $mux $ternary$libresoc.v:139395$5688 parameter \WIDTH 1 connect \A \sdr_dq_3__core__oe - connect \B \io_bd [93] + connect \B \io_bd [71] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139076$5759_Y + connect \Y $ternary$libresoc.v:139395$5688_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139078$5761 + cell $mux $ternary$libresoc.v:139396$5689 parameter \WIDTH 1 connect \A \sdr_dq_4__pad__i - connect \B \io_bd [94] + connect \B \io_bd [72] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139078$5761_Y + connect \Y $ternary$libresoc.v:139396$5689_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139079$5762 + cell $mux $ternary$libresoc.v:139397$5690 parameter \WIDTH 1 connect \A \sdr_dq_4__core__o - connect \B \io_bd [95] + connect \B \io_bd [73] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139079$5762_Y + connect \Y $ternary$libresoc.v:139397$5690_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139080$5763 + cell $mux $ternary$libresoc.v:139400$5693 parameter \WIDTH 1 connect \A \sdr_dq_4__core__oe - connect \B \io_bd [96] + connect \B \io_bd [74] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139080$5763_Y + connect \Y $ternary$libresoc.v:139400$5693_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139081$5764 + cell $mux $ternary$libresoc.v:139401$5694 parameter \WIDTH 1 connect \A \sdr_dq_5__pad__i - connect \B \io_bd [97] + connect \B \io_bd [75] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139081$5764_Y + connect \Y $ternary$libresoc.v:139401$5694_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139082$5765 + cell $mux $ternary$libresoc.v:139402$5695 parameter \WIDTH 1 connect \A \sdr_dq_5__core__o - connect \B \io_bd [98] + connect \B \io_bd [76] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139082$5765_Y + connect \Y $ternary$libresoc.v:139402$5695_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139083$5766 + cell $mux $ternary$libresoc.v:139403$5696 parameter \WIDTH 1 connect \A \sdr_dq_5__core__oe - connect \B \io_bd [99] + connect \B \io_bd [77] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139083$5766_Y + connect \Y $ternary$libresoc.v:139403$5696_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139084$5767 + cell $mux $ternary$libresoc.v:139404$5697 parameter \WIDTH 1 connect \A \sdr_dq_6__pad__i - connect \B \io_bd [100] + connect \B \io_bd [78] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139084$5767_Y + connect \Y $ternary$libresoc.v:139404$5697_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139085$5768 + cell $mux $ternary$libresoc.v:139405$5698 parameter \WIDTH 1 connect \A \sdr_dq_6__core__o - connect \B \io_bd [101] + connect \B \io_bd [79] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139085$5768_Y + connect \Y $ternary$libresoc.v:139405$5698_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139086$5769 + cell $mux $ternary$libresoc.v:139406$5699 parameter \WIDTH 1 connect \A \sdr_dq_6__core__oe - connect \B \io_bd [102] + connect \B \io_bd [80] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139086$5769_Y + connect \Y $ternary$libresoc.v:139406$5699_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139087$5770 + cell $mux $ternary$libresoc.v:139407$5700 parameter \WIDTH 1 connect \A \sdr_dq_7__pad__i - connect \B \io_bd [103] + connect \B \io_bd [81] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139087$5770_Y + connect \Y $ternary$libresoc.v:139407$5700_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139089$5772 + cell $mux $ternary$libresoc.v:139408$5701 parameter \WIDTH 1 connect \A \sdr_dq_7__core__o - connect \B \io_bd [104] + connect \B \io_bd [82] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139089$5772_Y + connect \Y $ternary$libresoc.v:139408$5701_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139090$5773 + cell $mux $ternary$libresoc.v:139409$5702 parameter \WIDTH 1 connect \A \sdr_dq_7__core__oe - connect \B \io_bd [105] + connect \B \io_bd [83] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139090$5773_Y + connect \Y $ternary$libresoc.v:139409$5702_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139091$5774 + cell $mux $ternary$libresoc.v:139411$5704 parameter \WIDTH 1 connect \A \sdr_a_0__core__o - connect \B \io_bd [106] + connect \B \io_bd [84] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139091$5774_Y + connect \Y $ternary$libresoc.v:139411$5704_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139092$5775 + cell $mux $ternary$libresoc.v:139412$5705 parameter \WIDTH 1 connect \A \sdr_a_1__core__o - connect \B \io_bd [107] + connect \B \io_bd [85] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139092$5775_Y + connect \Y $ternary$libresoc.v:139412$5705_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139093$5776 + cell $mux $ternary$libresoc.v:139413$5706 parameter \WIDTH 1 connect \A \sdr_a_2__core__o - connect \B \io_bd [108] + connect \B \io_bd [86] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139093$5776_Y + connect \Y $ternary$libresoc.v:139413$5706_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139094$5777 + cell $mux $ternary$libresoc.v:139414$5707 parameter \WIDTH 1 connect \A \sdr_a_3__core__o - connect \B \io_bd [109] + connect \B \io_bd [87] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139094$5777_Y + connect \Y $ternary$libresoc.v:139414$5707_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139095$5778 + cell $mux $ternary$libresoc.v:139415$5708 parameter \WIDTH 1 connect \A \sdr_a_4__core__o - connect \B \io_bd [110] + connect \B \io_bd [88] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139095$5778_Y + connect \Y $ternary$libresoc.v:139415$5708_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139096$5779 + cell $mux $ternary$libresoc.v:139416$5709 parameter \WIDTH 1 connect \A \sdr_a_5__core__o - connect \B \io_bd [111] + connect \B \io_bd [89] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139096$5779_Y + connect \Y $ternary$libresoc.v:139416$5709_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139097$5780 + cell $mux $ternary$libresoc.v:139417$5710 parameter \WIDTH 1 connect \A \sdr_a_6__core__o - connect \B \io_bd [112] + connect \B \io_bd [90] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139097$5780_Y + connect \Y $ternary$libresoc.v:139417$5710_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139098$5781 + cell $mux $ternary$libresoc.v:139418$5711 parameter \WIDTH 1 connect \A \sdr_a_7__core__o - connect \B \io_bd [113] + connect \B \io_bd [91] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139098$5781_Y + connect \Y $ternary$libresoc.v:139418$5711_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139100$5783 + cell $mux $ternary$libresoc.v:139419$5712 parameter \WIDTH 1 connect \A \sdr_a_8__core__o - connect \B \io_bd [114] + connect \B \io_bd [92] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139100$5783_Y + connect \Y $ternary$libresoc.v:139419$5712_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139101$5784 + cell $mux $ternary$libresoc.v:139420$5713 parameter \WIDTH 1 connect \A \sdr_a_9__core__o - connect \B \io_bd [115] + connect \B \io_bd [93] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139101$5784_Y + connect \Y $ternary$libresoc.v:139420$5713_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139102$5785 + cell $mux $ternary$libresoc.v:139422$5715 parameter \WIDTH 1 connect \A \sdr_ba_0__core__o - connect \B \io_bd [116] + connect \B \io_bd [94] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139102$5785_Y + connect \Y $ternary$libresoc.v:139422$5715_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139103$5786 + cell $mux $ternary$libresoc.v:139423$5716 parameter \WIDTH 1 connect \A \sdr_ba_1__core__o - connect \B \io_bd [117] + connect \B \io_bd [95] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139103$5786_Y + connect \Y $ternary$libresoc.v:139423$5716_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139104$5787 + cell $mux $ternary$libresoc.v:139424$5717 parameter \WIDTH 1 connect \A \sdr_clock__core__o - connect \B \io_bd [118] + connect \B \io_bd [96] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139104$5787_Y + connect \Y $ternary$libresoc.v:139424$5717_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139105$5788 + cell $mux $ternary$libresoc.v:139425$5718 parameter \WIDTH 1 connect \A \sdr_cke__core__o - connect \B \io_bd [119] + connect \B \io_bd [97] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139105$5788_Y + connect \Y $ternary$libresoc.v:139425$5718_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139106$5789 + cell $mux $ternary$libresoc.v:139426$5719 parameter \WIDTH 1 connect \A \sdr_ras_n__core__o - connect \B \io_bd [120] + connect \B \io_bd [98] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139106$5789_Y + connect \Y $ternary$libresoc.v:139426$5719_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139107$5790 + cell $mux $ternary$libresoc.v:139427$5720 parameter \WIDTH 1 connect \A \sdr_cas_n__core__o - connect \B \io_bd [121] + connect \B \io_bd [99] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139107$5790_Y + connect \Y $ternary$libresoc.v:139427$5720_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139108$5791 + cell $mux $ternary$libresoc.v:139428$5721 parameter \WIDTH 1 connect \A \sdr_we_n__core__o - connect \B \io_bd [122] + connect \B \io_bd [100] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139108$5791_Y + connect \Y $ternary$libresoc.v:139428$5721_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139109$5792 + cell $mux $ternary$libresoc.v:139429$5722 parameter \WIDTH 1 connect \A \sdr_cs_n__core__o - connect \B \io_bd [123] + connect \B \io_bd [101] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139109$5792_Y + connect \Y $ternary$libresoc.v:139429$5722_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139111$5794 + cell $mux $ternary$libresoc.v:139430$5723 parameter \WIDTH 1 connect \A \sdr_a_10__core__o - connect \B \io_bd [124] + connect \B \io_bd [102] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139111$5794_Y + connect \Y $ternary$libresoc.v:139430$5723_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139112$5795 + cell $mux $ternary$libresoc.v:139431$5724 parameter \WIDTH 1 connect \A \sdr_a_11__core__o - connect \B \io_bd [125] + connect \B \io_bd [103] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139112$5795_Y + connect \Y $ternary$libresoc.v:139431$5724_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139113$5796 + cell $mux $ternary$libresoc.v:139433$5726 parameter \WIDTH 1 connect \A \sdr_a_12__core__o - connect \B \io_bd [126] + connect \B \io_bd [104] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139113$5796_Y + connect \Y $ternary$libresoc.v:139433$5726_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139114$5797 + cell $mux $ternary$libresoc.v:139434$5727 parameter \WIDTH 1 connect \A \sdr_dm_1__core__o - connect \B \io_bd [127] + connect \B \io_bd [105] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139114$5797_Y + connect \Y $ternary$libresoc.v:139434$5727_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139115$5798 + cell $mux $ternary$libresoc.v:139435$5728 parameter \WIDTH 1 connect \A \sdr_dq_8__pad__i - connect \B \io_bd [128] + connect \B \io_bd [106] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139115$5798_Y + connect \Y $ternary$libresoc.v:139435$5728_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139116$5799 + cell $mux $ternary$libresoc.v:139436$5729 parameter \WIDTH 1 connect \A \sdr_dq_8__core__o - connect \B \io_bd [129] + connect \B \io_bd [107] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139116$5799_Y + connect \Y $ternary$libresoc.v:139436$5729_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139117$5800 + cell $mux $ternary$libresoc.v:139437$5730 parameter \WIDTH 1 connect \A \sdr_dq_8__core__oe - connect \B \io_bd [130] + connect \B \io_bd [108] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139117$5800_Y + connect \Y $ternary$libresoc.v:139437$5730_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139118$5801 + cell $mux $ternary$libresoc.v:139438$5731 parameter \WIDTH 1 connect \A \sdr_dq_9__pad__i - connect \B \io_bd [131] + connect \B \io_bd [109] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139118$5801_Y + connect \Y $ternary$libresoc.v:139438$5731_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139119$5802 + cell $mux $ternary$libresoc.v:139439$5732 parameter \WIDTH 1 connect \A \sdr_dq_9__core__o - connect \B \io_bd [132] + connect \B \io_bd [110] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139119$5802_Y + connect \Y $ternary$libresoc.v:139439$5732_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139120$5803 + cell $mux $ternary$libresoc.v:139440$5733 parameter \WIDTH 1 connect \A \sdr_dq_9__core__oe - connect \B \io_bd [133] + connect \B \io_bd [111] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139120$5803_Y + connect \Y $ternary$libresoc.v:139440$5733_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139122$5805 + cell $mux $ternary$libresoc.v:139441$5734 parameter \WIDTH 1 connect \A \sdr_dq_10__pad__i - connect \B \io_bd [134] + connect \B \io_bd [112] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139122$5805_Y + connect \Y $ternary$libresoc.v:139441$5734_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139123$5806 + cell $mux $ternary$libresoc.v:139442$5735 parameter \WIDTH 1 connect \A \sdr_dq_10__core__o - connect \B \io_bd [135] + connect \B \io_bd [113] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139123$5806_Y + connect \Y $ternary$libresoc.v:139442$5735_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139124$5807 + cell $mux $ternary$libresoc.v:139444$5737 parameter \WIDTH 1 connect \A \sdr_dq_10__core__oe - connect \B \io_bd [136] + connect \B \io_bd [114] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139124$5807_Y + connect \Y $ternary$libresoc.v:139444$5737_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139125$5808 + cell $mux $ternary$libresoc.v:139445$5738 parameter \WIDTH 1 connect \A \sdr_dq_11__pad__i - connect \B \io_bd [137] + connect \B \io_bd [115] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139125$5808_Y + connect \Y $ternary$libresoc.v:139445$5738_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139126$5809 + cell $mux $ternary$libresoc.v:139446$5739 parameter \WIDTH 1 connect \A \sdr_dq_11__core__o - connect \B \io_bd [138] + connect \B \io_bd [116] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139126$5809_Y + connect \Y $ternary$libresoc.v:139446$5739_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139127$5810 + cell $mux $ternary$libresoc.v:139447$5740 parameter \WIDTH 1 connect \A \sdr_dq_11__core__oe - connect \B \io_bd [139] + connect \B \io_bd [117] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139127$5810_Y + connect \Y $ternary$libresoc.v:139447$5740_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139128$5811 + cell $mux $ternary$libresoc.v:139448$5741 parameter \WIDTH 1 connect \A \sdr_dq_12__pad__i - connect \B \io_bd [140] + connect \B \io_bd [118] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139128$5811_Y + connect \Y $ternary$libresoc.v:139448$5741_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139129$5812 + cell $mux $ternary$libresoc.v:139449$5742 parameter \WIDTH 1 connect \A \sdr_dq_12__core__o - connect \B \io_bd [141] + connect \B \io_bd [119] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139129$5812_Y + connect \Y $ternary$libresoc.v:139449$5742_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139130$5813 + cell $mux $ternary$libresoc.v:139450$5743 parameter \WIDTH 1 connect \A \sdr_dq_12__core__oe - connect \B \io_bd [142] + connect \B \io_bd [120] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139130$5813_Y + connect \Y $ternary$libresoc.v:139450$5743_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139131$5814 + cell $mux $ternary$libresoc.v:139451$5744 parameter \WIDTH 1 connect \A \sdr_dq_13__pad__i - connect \B \io_bd [143] + connect \B \io_bd [121] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139131$5814_Y + connect \Y $ternary$libresoc.v:139451$5744_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139133$5816 + cell $mux $ternary$libresoc.v:139452$5745 parameter \WIDTH 1 connect \A \sdr_dq_13__core__o - connect \B \io_bd [144] + connect \B \io_bd [122] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139133$5816_Y + connect \Y $ternary$libresoc.v:139452$5745_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139134$5817 + cell $mux $ternary$libresoc.v:139453$5746 parameter \WIDTH 1 connect \A \sdr_dq_13__core__oe - connect \B \io_bd [145] + connect \B \io_bd [123] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139134$5817_Y + connect \Y $ternary$libresoc.v:139453$5746_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139135$5818 + cell $mux $ternary$libresoc.v:139455$5748 parameter \WIDTH 1 connect \A \sdr_dq_14__pad__i - connect \B \io_bd [146] + connect \B \io_bd [124] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139135$5818_Y + connect \Y $ternary$libresoc.v:139455$5748_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139136$5819 + cell $mux $ternary$libresoc.v:139456$5749 parameter \WIDTH 1 connect \A \sdr_dq_14__core__o - connect \B \io_bd [147] + connect \B \io_bd [125] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139136$5819_Y + connect \Y $ternary$libresoc.v:139456$5749_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139137$5820 + cell $mux $ternary$libresoc.v:139457$5750 parameter \WIDTH 1 connect \A \sdr_dq_14__core__oe - connect \B \io_bd [148] + connect \B \io_bd [126] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139137$5820_Y + connect \Y $ternary$libresoc.v:139457$5750_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139138$5821 + cell $mux $ternary$libresoc.v:139458$5751 parameter \WIDTH 1 connect \A \sdr_dq_15__pad__i - connect \B \io_bd [149] + connect \B \io_bd [127] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139138$5821_Y + connect \Y $ternary$libresoc.v:139458$5751_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139139$5822 + cell $mux $ternary$libresoc.v:139459$5752 parameter \WIDTH 1 connect \A \sdr_dq_15__core__o - connect \B \io_bd [150] + connect \B \io_bd [128] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139139$5822_Y + connect \Y $ternary$libresoc.v:139459$5752_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139140$5823 + cell $mux $ternary$libresoc.v:139460$5753 parameter \WIDTH 1 connect \A \sdr_dq_15__core__oe - connect \B \io_bd [151] + connect \B \io_bd [129] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139140$5823_Y + connect \Y $ternary$libresoc.v:139460$5753_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139227$5911 + cell $mux $ternary$libresoc.v:139549$5843 parameter \WIDTH 1 connect \A \eint_0__pad__i connect \B \io_bd [0] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139227$5911_Y + connect \Y $ternary$libresoc.v:139549$5843_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139228$5912 + cell $mux $ternary$libresoc.v:139550$5844 parameter \WIDTH 1 connect \A \eint_1__pad__i connect \B \io_bd [1] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139228$5912_Y + connect \Y $ternary$libresoc.v:139550$5844_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139229$5913 + cell $mux $ternary$libresoc.v:139551$5845 parameter \WIDTH 1 connect \A \eint_2__pad__i connect \B \io_bd [2] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139229$5913_Y + connect \Y $ternary$libresoc.v:139551$5845_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139230$5914 + cell $mux $ternary$libresoc.v:139552$5846 parameter \WIDTH 1 connect \A \gpio_e8__pad__i connect \B \io_bd [3] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139230$5914_Y + connect \Y $ternary$libresoc.v:139552$5846_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139232$5916 + cell $mux $ternary$libresoc.v:139554$5848 parameter \WIDTH 1 connect \A \gpio_e8__core__o connect \B \io_bd [4] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139232$5916_Y + connect \Y $ternary$libresoc.v:139554$5848_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139233$5917 + cell $mux $ternary$libresoc.v:139555$5849 parameter \WIDTH 1 connect \A \gpio_e8__core__oe connect \B \io_bd [5] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139233$5917_Y + connect \Y $ternary$libresoc.v:139555$5849_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139234$5918 + cell $mux $ternary$libresoc.v:139556$5850 parameter \WIDTH 1 connect \A \gpio_e9__pad__i connect \B \io_bd [6] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139234$5918_Y + connect \Y $ternary$libresoc.v:139556$5850_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139235$5919 + cell $mux $ternary$libresoc.v:139557$5851 parameter \WIDTH 1 connect \A \gpio_e9__core__o connect \B \io_bd [7] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139235$5919_Y + connect \Y $ternary$libresoc.v:139557$5851_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139236$5920 + cell $mux $ternary$libresoc.v:139558$5852 parameter \WIDTH 1 connect \A \gpio_e9__core__oe connect \B \io_bd [8] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139236$5920_Y + connect \Y $ternary$libresoc.v:139558$5852_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139237$5921 + cell $mux $ternary$libresoc.v:139559$5853 parameter \WIDTH 1 connect \A \gpio_e10__pad__i connect \B \io_bd [9] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139237$5921_Y + connect \Y $ternary$libresoc.v:139559$5853_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139238$5922 + cell $mux $ternary$libresoc.v:139560$5854 parameter \WIDTH 1 connect \A \gpio_e10__core__o connect \B \io_bd [10] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139238$5922_Y + connect \Y $ternary$libresoc.v:139560$5854_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139239$5923 + cell $mux $ternary$libresoc.v:139561$5855 parameter \WIDTH 1 connect \A \gpio_e10__core__oe connect \B \io_bd [11] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139239$5923_Y + connect \Y $ternary$libresoc.v:139561$5855_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139240$5924 + cell $mux $ternary$libresoc.v:139562$5856 parameter \WIDTH 1 connect \A \gpio_e11__pad__i connect \B \io_bd [12] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139240$5924_Y + connect \Y $ternary$libresoc.v:139562$5856_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139241$5925 + cell $mux $ternary$libresoc.v:139563$5857 parameter \WIDTH 1 connect \A \gpio_e11__core__o connect \B \io_bd [13] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139241$5925_Y + connect \Y $ternary$libresoc.v:139563$5857_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139243$5927 + cell $mux $ternary$libresoc.v:139565$5859 parameter \WIDTH 1 connect \A \gpio_e11__core__oe connect \B \io_bd [14] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139243$5927_Y + connect \Y $ternary$libresoc.v:139565$5859_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139244$5928 + cell $mux $ternary$libresoc.v:139566$5860 parameter \WIDTH 1 connect \A \gpio_e12__pad__i connect \B \io_bd [15] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139244$5928_Y + connect \Y $ternary$libresoc.v:139566$5860_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139245$5929 + cell $mux $ternary$libresoc.v:139567$5861 parameter \WIDTH 1 connect \A \gpio_e12__core__o connect \B \io_bd [16] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139245$5929_Y + connect \Y $ternary$libresoc.v:139567$5861_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139246$5930 + cell $mux $ternary$libresoc.v:139568$5862 parameter \WIDTH 1 connect \A \gpio_e12__core__oe connect \B \io_bd [17] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139246$5930_Y + connect \Y $ternary$libresoc.v:139568$5862_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139247$5931 + cell $mux $ternary$libresoc.v:139569$5863 parameter \WIDTH 1 connect \A \gpio_e13__pad__i connect \B \io_bd [18] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139247$5931_Y + connect \Y $ternary$libresoc.v:139569$5863_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139248$5932 + cell $mux $ternary$libresoc.v:139570$5864 parameter \WIDTH 1 connect \A \gpio_e13__core__o connect \B \io_bd [19] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139248$5932_Y + connect \Y $ternary$libresoc.v:139570$5864_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139249$5933 + cell $mux $ternary$libresoc.v:139571$5865 parameter \WIDTH 1 connect \A \gpio_e13__core__oe connect \B \io_bd [20] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139249$5933_Y + connect \Y $ternary$libresoc.v:139571$5865_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139250$5934 + cell $mux $ternary$libresoc.v:139572$5866 parameter \WIDTH 1 connect \A \gpio_e14__pad__i connect \B \io_bd [21] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139250$5934_Y + connect \Y $ternary$libresoc.v:139572$5866_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139251$5935 + cell $mux $ternary$libresoc.v:139573$5867 parameter \WIDTH 1 connect \A \gpio_e14__core__o connect \B \io_bd [22] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139251$5935_Y + connect \Y $ternary$libresoc.v:139573$5867_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139252$5936 + cell $mux $ternary$libresoc.v:139574$5868 parameter \WIDTH 1 connect \A \gpio_e14__core__oe connect \B \io_bd [23] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139252$5936_Y + connect \Y $ternary$libresoc.v:139574$5868_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:139327.8-139339.4" + attribute \src "libresoc.v:139649.8-139661.4" cell \_fsm \_fsm connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tms \TAP_bus__tms @@ -222176,7 +221635,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:139340.12-139350.4" + attribute \src "libresoc.v:139662.12-139672.4" cell \_idblock \_idblock connect \TAP_bus__tdi \TAP_bus__tdi connect \TAP_id_tdo \_idblock_TAP_id_tdo @@ -222189,7 +221648,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:139351.12-139361.4" + attribute \src "libresoc.v:139673.12-139683.4" cell \_irblock \_irblock connect \TAP_bus__tdi \TAP_bus__tdi connect \capture \_fsm_capture @@ -222201,582 +221660,582 @@ module \jtag connect \tdo \_irblock_tdo connect \update \_fsm_update end - attribute \src "libresoc.v:137576.7-137576.20" - process $proc$libresoc.v:137576$6132 + attribute \src "libresoc.v:138052.7-138052.20" + process $proc$libresoc.v:138052$6064 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:138130.13-138130.32" - process $proc$libresoc.v:138130$6133 + attribute \src "libresoc.v:138562.13-138562.32" + process $proc$libresoc.v:138562$6065 assign { } { } assign $1\dmi0__addr_i[3:0] 4'0000 sync always sync init update \dmi0__addr_i $1\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:138135.14-138135.46" - process $proc$libresoc.v:138135$6134 + attribute \src "libresoc.v:138567.14-138567.46" + process $proc$libresoc.v:138567$6066 assign { } { } assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0__din $1\dmi0__din[63:0] end - attribute \src "libresoc.v:138149.7-138149.29" - process $proc$libresoc.v:138149$6135 + attribute \src "libresoc.v:138581.7-138581.29" + process $proc$libresoc.v:138581$6067 assign { } { } assign $1\dmi0_addrsr__oe[0:0] 1'0 sync always sync init update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:138157.13-138157.36" - process $proc$libresoc.v:138157$6136 + attribute \src "libresoc.v:138589.13-138589.36" + process $proc$libresoc.v:138589$6068 assign { } { } assign $1\dmi0_addrsr_reg[7:0] 8'00000000 sync always sync init update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:138165.7-138165.37" - process $proc$libresoc.v:138165$6137 + attribute \src "libresoc.v:138597.7-138597.37" + process $proc$libresoc.v:138597$6069 assign { } { } assign $1\dmi0_addrsr_update_core[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:138169.7-138169.42" - process $proc$libresoc.v:138169$6138 + attribute \src "libresoc.v:138601.7-138601.42" + process $proc$libresoc.v:138601$6070 assign { } { } assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:138173.14-138173.51" - process $proc$libresoc.v:138173$6139 + attribute \src "libresoc.v:138605.14-138605.51" + process $proc$libresoc.v:138605$6071 assign { } { } assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:138179.13-138179.35" - process $proc$libresoc.v:138179$6140 + attribute \src "libresoc.v:138611.13-138611.35" + process $proc$libresoc.v:138611$6072 assign { } { } assign $1\dmi0_datasr__oe[1:0] 2'00 sync always sync init update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:138187.14-138187.52" - process $proc$libresoc.v:138187$6141 + attribute \src "libresoc.v:138619.14-138619.52" + process $proc$libresoc.v:138619$6073 assign { } { } assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:138195.7-138195.37" - process $proc$libresoc.v:138195$6142 + attribute \src "libresoc.v:138627.7-138627.37" + process $proc$libresoc.v:138627$6074 assign { } { } assign $1\dmi0_datasr_update_core[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:138199.7-138199.42" - process $proc$libresoc.v:138199$6143 + attribute \src "libresoc.v:138631.7-138631.42" + process $proc$libresoc.v:138631$6075 assign { } { } assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:138215.13-138215.29" - process $proc$libresoc.v:138215$6144 + attribute \src "libresoc.v:138647.13-138647.29" + process $proc$libresoc.v:138647$6076 assign { } { } assign $1\fsm_state[2:0] 3'000 sync always sync init update \fsm_state $1\fsm_state[2:0] end - attribute \src "libresoc.v:138217.13-138217.35" - process $proc$libresoc.v:138217$6145 + attribute \src "libresoc.v:138649.13-138649.35" + process $proc$libresoc.v:138649$6077 assign { } { } - assign $0\fsm_state$499[2:0]$6146 3'000 + assign $0\fsm_state$455[2:0]$6078 3'000 sync always sync init - update \fsm_state$499 $0\fsm_state$499[2:0]$6146 + update \fsm_state$455 $0\fsm_state$455[2:0]$6078 end - attribute \src "libresoc.v:138415.15-138415.66" - process $proc$libresoc.v:138415$6147 + attribute \src "libresoc.v:138847.15-138847.61" + process $proc$libresoc.v:138847$6079 assign { } { } - assign $1\io_bd[151:0] 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\io_bd[129:0] 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \io_bd $1\io_bd[151:0] + update \io_bd $1\io_bd[129:0] end - attribute \src "libresoc.v:138427.15-138427.66" - process $proc$libresoc.v:138427$6148 + attribute \src "libresoc.v:138859.15-138859.61" + process $proc$libresoc.v:138859$6080 assign { } { } - assign $1\io_sr[151:0] 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\io_sr[129:0] 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \io_sr $1\io_sr[151:0] + update \io_sr $1\io_sr[129:0] end - attribute \src "libresoc.v:138436.14-138436.41" - process $proc$libresoc.v:138436$6149 + attribute \src "libresoc.v:138868.14-138868.41" + process $proc$libresoc.v:138868$6081 assign { } { } assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb__adr $1\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:138445.14-138445.51" - process $proc$libresoc.v:138445$6150 + attribute \src "libresoc.v:138877.14-138877.51" + process $proc$libresoc.v:138877$6082 assign { } { } assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:138459.7-138459.32" - process $proc$libresoc.v:138459$6151 + attribute \src "libresoc.v:138891.7-138891.32" + process $proc$libresoc.v:138891$6083 assign { } { } assign $1\jtag_wb_addrsr__oe[0:0] 1'0 sync always sync init update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:138467.14-138467.47" - process $proc$libresoc.v:138467$6152 + attribute \src "libresoc.v:138899.14-138899.47" + process $proc$libresoc.v:138899$6084 assign { } { } assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:138475.7-138475.40" - process $proc$libresoc.v:138475$6153 + attribute \src "libresoc.v:138907.7-138907.40" + process $proc$libresoc.v:138907$6085 assign { } { } assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:138479.7-138479.45" - process $proc$libresoc.v:138479$6154 + attribute \src "libresoc.v:138911.7-138911.45" + process $proc$libresoc.v:138911$6086 assign { } { } assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:138483.14-138483.54" - process $proc$libresoc.v:138483$6155 + attribute \src "libresoc.v:138915.14-138915.54" + process $proc$libresoc.v:138915$6087 assign { } { } assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:138489.13-138489.38" - process $proc$libresoc.v:138489$6156 + attribute \src "libresoc.v:138921.13-138921.38" + process $proc$libresoc.v:138921$6088 assign { } { } assign $1\jtag_wb_datasr__oe[1:0] 2'00 sync always sync init update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:138497.14-138497.55" - process $proc$libresoc.v:138497$6157 + attribute \src "libresoc.v:138929.14-138929.55" + process $proc$libresoc.v:138929$6089 assign { } { } assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:138505.7-138505.40" - process $proc$libresoc.v:138505$6158 + attribute \src "libresoc.v:138937.7-138937.40" + process $proc$libresoc.v:138937$6090 assign { } { } assign $1\jtag_wb_datasr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:138509.7-138509.45" - process $proc$libresoc.v:138509$6159 + attribute \src "libresoc.v:138941.7-138941.45" + process $proc$libresoc.v:138941$6091 assign { } { } assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:138931.7-138931.21" - process $proc$libresoc.v:138931$6160 + attribute \src "libresoc.v:139275.7-139275.21" + process $proc$libresoc.v:139275$6092 assign { } { } assign $1\sr0__oe[0:0] 1'0 sync always sync init update \sr0__oe $1\sr0__oe[0:0] end - attribute \src "libresoc.v:138939.13-138939.27" - process $proc$libresoc.v:138939$6161 + attribute \src "libresoc.v:139283.13-139283.27" + process $proc$libresoc.v:139283$6093 assign { } { } assign $1\sr0_reg[2:0] 3'000 sync always sync init update \sr0_reg $1\sr0_reg[2:0] end - attribute \src "libresoc.v:138947.7-138947.29" - process $proc$libresoc.v:138947$6162 + attribute \src "libresoc.v:139291.7-139291.29" + process $proc$libresoc.v:139291$6094 assign { } { } assign $1\sr0_update_core[0:0] 1'0 sync always sync init update \sr0_update_core $1\sr0_update_core[0:0] end - attribute \src "libresoc.v:138951.7-138951.34" - process $proc$libresoc.v:138951$6163 + attribute \src "libresoc.v:139295.7-139295.34" + process $proc$libresoc.v:139295$6095 assign { } { } assign $1\sr0_update_core_prev[0:0] 1'0 sync always sync init update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:138961.7-138961.21" - process $proc$libresoc.v:138961$6164 + attribute \src "libresoc.v:139305.7-139305.21" + process $proc$libresoc.v:139305$6096 assign { } { } assign $1\sr5__oe[0:0] 1'0 sync always sync init update \sr5__oe $1\sr5__oe[0:0] end - attribute \src "libresoc.v:138969.13-138969.27" - process $proc$libresoc.v:138969$6165 + attribute \src "libresoc.v:139313.13-139313.27" + process $proc$libresoc.v:139313$6097 assign { } { } assign $1\sr5_reg[2:0] 3'000 sync always sync init update \sr5_reg $1\sr5_reg[2:0] end - attribute \src "libresoc.v:138977.7-138977.29" - process $proc$libresoc.v:138977$6166 + attribute \src "libresoc.v:139321.7-139321.29" + process $proc$libresoc.v:139321$6098 assign { } { } assign $1\sr5_update_core[0:0] 1'0 sync always sync init update \sr5_update_core $1\sr5_update_core[0:0] end - attribute \src "libresoc.v:138981.7-138981.34" - process $proc$libresoc.v:138981$6167 + attribute \src "libresoc.v:139325.7-139325.34" + process $proc$libresoc.v:139325$6099 assign { } { } assign $1\sr5_update_core_prev[0:0] 1'0 sync always sync init update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:138986.7-138986.26" - process $proc$libresoc.v:138986$6168 + attribute \src "libresoc.v:139330.7-139330.26" + process $proc$libresoc.v:139330$6100 assign { } { } assign $1\wb_dcache_en[0:0] 1'1 sync always sync init update \wb_dcache_en $1\wb_dcache_en[0:0] end - attribute \src "libresoc.v:138991.7-138991.26" - process $proc$libresoc.v:138991$6169 + attribute \src "libresoc.v:139335.7-139335.26" + process $proc$libresoc.v:139335$6101 assign { } { } assign $1\wb_icache_en[0:0] 1'1 sync always sync init update \wb_icache_en $1\wb_icache_en[0:0] end - attribute \src "libresoc.v:138996.7-138996.24" - process $proc$libresoc.v:138996$6170 + attribute \src "libresoc.v:139340.7-139340.24" + process $proc$libresoc.v:139340$6102 assign { } { } assign $1\wb_sram_en[0:0] 1'1 sync always sync init update \wb_sram_en $1\wb_sram_en[0:0] end - attribute \src "libresoc.v:139253.3-139254.41" - process $proc$libresoc.v:139253$5937 + attribute \src "libresoc.v:139575.3-139576.41" + process $proc$libresoc.v:139575$5869 assign { } { } assign $0\wb_icache_en[0:0] \wb_icache_en$next sync posedge \clk update \wb_icache_en $0\wb_icache_en[0:0] end - attribute \src "libresoc.v:139255.3-139256.41" - process $proc$libresoc.v:139255$5938 + attribute \src "libresoc.v:139577.3-139578.41" + process $proc$libresoc.v:139577$5870 assign { } { } assign $0\wb_dcache_en[0:0] \wb_dcache_en$next sync posedge \clk update \wb_dcache_en $0\wb_dcache_en[0:0] end - attribute \src "libresoc.v:139257.3-139258.37" - process $proc$libresoc.v:139257$5939 + attribute \src "libresoc.v:139579.3-139580.37" + process $proc$libresoc.v:139579$5871 assign { } { } assign $0\wb_sram_en[0:0] \wb_sram_en$next sync posedge \clk update \wb_sram_en $0\wb_sram_en[0:0] end - attribute \src "libresoc.v:139259.3-139260.45" - process $proc$libresoc.v:139259$5940 + attribute \src "libresoc.v:139581.3-139582.45" + process $proc$libresoc.v:139581$5872 assign { } { } assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next sync posedge \clk update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:139261.3-139262.35" - process $proc$libresoc.v:139261$5941 + attribute \src "libresoc.v:139583.3-139584.35" + process $proc$libresoc.v:139583$5873 assign { } { } assign $0\dmi0__din[63:0] \dmi0__din$next sync posedge \clk update \dmi0__din $0\dmi0__din[63:0] end - attribute \src "libresoc.v:139263.3-139264.45" - process $proc$libresoc.v:139263$5942 + attribute \src "libresoc.v:139585.3-139586.45" + process $proc$libresoc.v:139585$5874 assign { } { } - assign $0\fsm_state$499[2:0]$5943 \fsm_state$499$next + assign $0\fsm_state$455[2:0]$5875 \fsm_state$455$next sync posedge \clk - update \fsm_state$499 $0\fsm_state$499[2:0]$5943 + update \fsm_state$455 $0\fsm_state$455[2:0]$5875 end - attribute \src "libresoc.v:139265.3-139266.41" - process $proc$libresoc.v:139265$5944 + attribute \src "libresoc.v:139587.3-139588.41" + process $proc$libresoc.v:139587$5876 assign { } { } assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next sync posedge \clk update \dmi0__addr_i $0\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:139267.3-139268.51" - process $proc$libresoc.v:139267$5945 + attribute \src "libresoc.v:139589.3-139590.51" + process $proc$libresoc.v:139589$5877 assign { } { } assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next sync posedge \clk update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:139269.3-139270.45" - process $proc$libresoc.v:139269$5946 + attribute \src "libresoc.v:139591.3-139592.45" + process $proc$libresoc.v:139591$5878 assign { } { } assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next sync posedge \clk update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:139271.3-139272.35" - process $proc$libresoc.v:139271$5947 + attribute \src "libresoc.v:139593.3-139594.35" + process $proc$libresoc.v:139593$5879 assign { } { } assign $0\fsm_state[2:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[2:0] end - attribute \src "libresoc.v:139273.3-139274.41" - process $proc$libresoc.v:139273$5948 + attribute \src "libresoc.v:139595.3-139596.41" + process $proc$libresoc.v:139595$5880 assign { } { } assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next sync posedge \clk update \jtag_wb__adr $0\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:139275.3-139276.31" - process $proc$libresoc.v:139275$5949 + attribute \src "libresoc.v:139597.3-139598.31" + process $proc$libresoc.v:139597$5881 assign { } { } assign $0\sr5_reg[2:0] \sr5_reg$next sync posedge \posjtag_clk update \sr5_reg $0\sr5_reg[2:0] end - attribute \src "libresoc.v:139277.3-139278.31" - process $proc$libresoc.v:139277$5950 + attribute \src "libresoc.v:139599.3-139600.31" + process $proc$libresoc.v:139599$5882 assign { } { } assign $0\sr5__oe[0:0] \sr5__oe$next sync posedge \clk update \sr5__oe $0\sr5__oe[0:0] end - attribute \src "libresoc.v:139279.3-139280.57" - process $proc$libresoc.v:139279$5951 + attribute \src "libresoc.v:139601.3-139602.57" + process $proc$libresoc.v:139601$5883 assign { } { } assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next sync posedge \clk update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:139281.3-139282.47" - process $proc$libresoc.v:139281$5952 + attribute \src "libresoc.v:139603.3-139604.47" + process $proc$libresoc.v:139603$5884 assign { } { } assign $0\sr5_update_core[0:0] \sr5_update_core$next sync posedge \clk update \sr5_update_core $0\sr5_update_core[0:0] end - attribute \src "libresoc.v:139283.3-139284.47" - process $proc$libresoc.v:139283$5953 + attribute \src "libresoc.v:139605.3-139606.47" + process $proc$libresoc.v:139605$5885 assign { } { } assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next sync posedge \posjtag_clk update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:139285.3-139286.47" - process $proc$libresoc.v:139285$5954 + attribute \src "libresoc.v:139607.3-139608.47" + process $proc$libresoc.v:139607$5886 assign { } { } assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next sync posedge \clk update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:139287.3-139288.73" - process $proc$libresoc.v:139287$5955 + attribute \src "libresoc.v:139609.3-139610.73" + process $proc$libresoc.v:139609$5887 assign { } { } assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next sync posedge \clk update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:139289.3-139290.63" - process $proc$libresoc.v:139289$5956 + attribute \src "libresoc.v:139611.3-139612.63" + process $proc$libresoc.v:139611$5888 assign { } { } assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next sync posedge \clk update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:139291.3-139292.47" - process $proc$libresoc.v:139291$5957 + attribute \src "libresoc.v:139613.3-139614.47" + process $proc$libresoc.v:139613$5889 assign { } { } assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next sync posedge \posjtag_clk update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:139293.3-139294.47" - process $proc$libresoc.v:139293$5958 + attribute \src "libresoc.v:139615.3-139616.47" + process $proc$libresoc.v:139615$5890 assign { } { } assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next sync posedge \clk update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:139295.3-139296.73" - process $proc$libresoc.v:139295$5959 + attribute \src "libresoc.v:139617.3-139618.73" + process $proc$libresoc.v:139617$5891 assign { } { } assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next sync posedge \clk update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:139297.3-139298.63" - process $proc$libresoc.v:139297$5960 + attribute \src "libresoc.v:139619.3-139620.63" + process $proc$libresoc.v:139619$5892 assign { } { } assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next sync posedge \clk update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:139299.3-139300.53" - process $proc$libresoc.v:139299$5961 + attribute \src "libresoc.v:139621.3-139622.53" + process $proc$libresoc.v:139621$5893 assign { } { } assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next sync posedge \posjtag_clk update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:139301.3-139302.53" - process $proc$libresoc.v:139301$5962 + attribute \src "libresoc.v:139623.3-139624.53" + process $proc$libresoc.v:139623$5894 assign { } { } assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next sync posedge \clk update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:139303.3-139304.79" - process $proc$libresoc.v:139303$5963 + attribute \src "libresoc.v:139625.3-139626.79" + process $proc$libresoc.v:139625$5895 assign { } { } assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next sync posedge \clk update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:139305.3-139306.69" - process $proc$libresoc.v:139305$5964 + attribute \src "libresoc.v:139627.3-139628.69" + process $proc$libresoc.v:139627$5896 assign { } { } assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next sync posedge \clk update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:139307.3-139308.53" - process $proc$libresoc.v:139307$5965 + attribute \src "libresoc.v:139629.3-139630.53" + process $proc$libresoc.v:139629$5897 assign { } { } assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next sync posedge \posjtag_clk update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:139309.3-139310.53" - process $proc$libresoc.v:139309$5966 + attribute \src "libresoc.v:139631.3-139632.53" + process $proc$libresoc.v:139631$5898 assign { } { } assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next sync posedge \clk update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:139311.3-139312.79" - process $proc$libresoc.v:139311$5967 + attribute \src "libresoc.v:139633.3-139634.79" + process $proc$libresoc.v:139633$5899 assign { } { } assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next sync posedge \clk update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:139313.3-139314.69" - process $proc$libresoc.v:139313$5968 + attribute \src "libresoc.v:139635.3-139636.69" + process $proc$libresoc.v:139635$5900 assign { } { } assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next sync posedge \clk update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:139315.3-139316.31" - process $proc$libresoc.v:139315$5969 + attribute \src "libresoc.v:139637.3-139638.31" + process $proc$libresoc.v:139637$5901 assign { } { } assign $0\sr0_reg[2:0] \sr0_reg$next sync posedge \posjtag_clk update \sr0_reg $0\sr0_reg[2:0] end - attribute \src "libresoc.v:139317.3-139318.31" - process $proc$libresoc.v:139317$5970 + attribute \src "libresoc.v:139639.3-139640.31" + process $proc$libresoc.v:139639$5902 assign { } { } assign $0\sr0__oe[0:0] \sr0__oe$next sync posedge \clk update \sr0__oe $0\sr0__oe[0:0] end - attribute \src "libresoc.v:139319.3-139320.57" - process $proc$libresoc.v:139319$5971 + attribute \src "libresoc.v:139641.3-139642.57" + process $proc$libresoc.v:139641$5903 assign { } { } assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next sync posedge \clk update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:139321.3-139322.47" - process $proc$libresoc.v:139321$5972 + attribute \src "libresoc.v:139643.3-139644.47" + process $proc$libresoc.v:139643$5904 assign { } { } assign $0\sr0_update_core[0:0] \sr0_update_core$next sync posedge \clk update \sr0_update_core $0\sr0_update_core[0:0] end - attribute \src "libresoc.v:139323.3-139324.27" - process $proc$libresoc.v:139323$5973 + attribute \src "libresoc.v:139645.3-139646.27" + process $proc$libresoc.v:139645$5905 assign { } { } - assign $0\io_bd[151:0] \io_bd$next + assign $0\io_bd[129:0] \io_bd$next sync negedge \negjtag_clk - update \io_bd $0\io_bd[151:0] + update \io_bd $0\io_bd[129:0] end - attribute \src "libresoc.v:139325.3-139326.27" - process $proc$libresoc.v:139325$5974 + attribute \src "libresoc.v:139647.3-139648.27" + process $proc$libresoc.v:139647$5906 assign { } { } - assign $0\io_sr[151:0] \io_sr$next + assign $0\io_sr[129:0] \io_sr$next sync posedge \posjtag_clk - update \io_sr $0\io_sr[151:0] + update \io_sr $0\io_sr[129:0] end - attribute \src "libresoc.v:139362.3-139377.6" - process $proc$libresoc.v:139362$5975 + attribute \src "libresoc.v:139684.3-139699.6" + process $proc$libresoc.v:139684$5907 assign { } { } assign { } { } assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] - attribute \src "libresoc.v:139363.5-139363.29" + attribute \src "libresoc.v:139685.5-139685.29" switch \initial - attribute \src "libresoc.v:139363.9-139363.17" + attribute \src "libresoc.v:139685.9-139685.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" - switch { \$365 \_idblock_select_id \_fsm_isir } + switch { \$321 \_idblock_select_id \_fsm_isir } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } @@ -222788,21 +222247,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $1\TAP_tdo[0:0] \io_sr [151] + assign $1\TAP_tdo[0:0] \io_sr [129] case assign $1\TAP_tdo[0:0] 1'0 end sync always update \TAP_tdo $0\TAP_tdo[0:0] end - attribute \src "libresoc.v:139378.3-139386.6" - process $proc$libresoc.v:139378$5976 + attribute \src "libresoc.v:139700.3-139708.6" + process $proc$libresoc.v:139700$5908 assign { } { } assign { } { } - assign $0\sr0_update_core$next[0:0]$5977 $1\sr0_update_core$next[0:0]$5978 - attribute \src "libresoc.v:139379.5-139379.29" + assign $0\sr0_update_core$next[0:0]$5909 $1\sr0_update_core$next[0:0]$5910 + attribute \src "libresoc.v:139701.5-139701.29" switch \initial - attribute \src "libresoc.v:139379.9-139379.17" + attribute \src "libresoc.v:139701.9-139701.17" case 1'1 case end @@ -222811,21 +222270,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core$next[0:0]$5978 1'0 + assign $1\sr0_update_core$next[0:0]$5910 1'0 case - assign $1\sr0_update_core$next[0:0]$5978 \sr0_update + assign $1\sr0_update_core$next[0:0]$5910 \sr0_update end sync always - update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5977 + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5909 end - attribute \src "libresoc.v:139387.3-139395.6" - process $proc$libresoc.v:139387$5979 + attribute \src "libresoc.v:139709.3-139717.6" + process $proc$libresoc.v:139709$5911 assign { } { } assign { } { } - assign $0\sr0_update_core_prev$next[0:0]$5980 $1\sr0_update_core_prev$next[0:0]$5981 - attribute \src "libresoc.v:139388.5-139388.29" + assign $0\sr0_update_core_prev$next[0:0]$5912 $1\sr0_update_core_prev$next[0:0]$5913 + attribute \src "libresoc.v:139710.5-139710.29" switch \initial - attribute \src "libresoc.v:139388.9-139388.17" + attribute \src "libresoc.v:139710.9-139710.17" case 1'1 case end @@ -222834,57 +222293,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core_prev$next[0:0]$5981 1'0 + assign $1\sr0_update_core_prev$next[0:0]$5913 1'0 case - assign $1\sr0_update_core_prev$next[0:0]$5981 \sr0_update_core + assign $1\sr0_update_core_prev$next[0:0]$5913 \sr0_update_core end sync always - update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5980 + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5912 end - attribute \src "libresoc.v:139396.3-139412.6" - process $proc$libresoc.v:139396$5982 + attribute \src "libresoc.v:139718.3-139734.6" + process $proc$libresoc.v:139718$5914 assign { } { } assign { } { } - assign $0\sr0__oe$next[0:0]$5983 $2\sr0__oe$next[0:0]$5985 - attribute \src "libresoc.v:139397.5-139397.29" + assign $0\sr0__oe$next[0:0]$5915 $2\sr0__oe$next[0:0]$5917 + attribute \src "libresoc.v:139719.5-139719.29" switch \initial - attribute \src "libresoc.v:139397.9-139397.17" + attribute \src "libresoc.v:139719.9-139719.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$383 + switch \$339 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0__oe$next[0:0]$5984 \sr0_isir + assign $1\sr0__oe$next[0:0]$5916 \sr0_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\sr0__oe$next[0:0]$5984 1'0 + assign $1\sr0__oe$next[0:0]$5916 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0__oe$next[0:0]$5985 1'0 + assign $2\sr0__oe$next[0:0]$5917 1'0 case - assign $2\sr0__oe$next[0:0]$5985 $1\sr0__oe$next[0:0]$5984 + assign $2\sr0__oe$next[0:0]$5917 $1\sr0__oe$next[0:0]$5916 end sync always - update \sr0__oe$next $0\sr0__oe$next[0:0]$5983 + update \sr0__oe$next $0\sr0__oe$next[0:0]$5915 end - attribute \src "libresoc.v:139413.3-139433.6" - process $proc$libresoc.v:139413$5986 + attribute \src "libresoc.v:139735.3-139755.6" + process $proc$libresoc.v:139735$5918 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sr0_reg$next[2:0]$5987 $3\sr0_reg$next[2:0]$5990 - attribute \src "libresoc.v:139414.5-139414.29" + assign $0\sr0_reg$next[2:0]$5919 $3\sr0_reg$next[2:0]$5922 + attribute \src "libresoc.v:139736.5-139736.29" switch \initial - attribute \src "libresoc.v:139414.9-139414.17" + attribute \src "libresoc.v:139736.9-139736.17" case 1'1 case end @@ -222893,39 +222352,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_reg$next[2:0]$5988 { \TAP_bus__tdi \sr0_reg [2:1] } + assign $1\sr0_reg$next[2:0]$5920 { \TAP_bus__tdi \sr0_reg [2:1] } case - assign $1\sr0_reg$next[2:0]$5988 \sr0_reg + assign $1\sr0_reg$next[2:0]$5920 \sr0_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \sr0_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0_reg$next[2:0]$5989 \sr0__i + assign $2\sr0_reg$next[2:0]$5921 \sr0__i case - assign $2\sr0_reg$next[2:0]$5989 $1\sr0_reg$next[2:0]$5988 + assign $2\sr0_reg$next[2:0]$5921 $1\sr0_reg$next[2:0]$5920 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr0_reg$next[2:0]$5990 3'000 + assign $3\sr0_reg$next[2:0]$5922 3'000 case - assign $3\sr0_reg$next[2:0]$5990 $2\sr0_reg$next[2:0]$5989 + assign $3\sr0_reg$next[2:0]$5922 $2\sr0_reg$next[2:0]$5921 end sync always - update \sr0_reg$next $0\sr0_reg$next[2:0]$5987 + update \sr0_reg$next $0\sr0_reg$next[2:0]$5919 end - attribute \src "libresoc.v:139434.3-139442.6" - process $proc$libresoc.v:139434$5991 + attribute \src "libresoc.v:139756.3-139764.6" + process $proc$libresoc.v:139756$5923 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core$next[0:0]$5992 $1\jtag_wb_addrsr_update_core$next[0:0]$5993 - attribute \src "libresoc.v:139435.5-139435.29" + assign $0\jtag_wb_addrsr_update_core$next[0:0]$5924 $1\jtag_wb_addrsr_update_core$next[0:0]$5925 + attribute \src "libresoc.v:139757.5-139757.29" switch \initial - attribute \src "libresoc.v:139435.9-139435.17" + attribute \src "libresoc.v:139757.9-139757.17" case 1'1 case end @@ -222934,21 +222393,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5993 1'0 + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5925 1'0 case - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5993 \jtag_wb_addrsr_update + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5925 \jtag_wb_addrsr_update end sync always - update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5992 + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5924 end - attribute \src "libresoc.v:139443.3-139451.6" - process $proc$libresoc.v:139443$5994 + attribute \src "libresoc.v:139765.3-139773.6" + process $proc$libresoc.v:139765$5926 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 - attribute \src "libresoc.v:139444.5-139444.29" + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5927 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5928 + attribute \src "libresoc.v:139766.5-139766.29" switch \initial - attribute \src "libresoc.v:139444.9-139444.17" + attribute \src "libresoc.v:139766.9-139766.17" case 1'1 case end @@ -222957,57 +222416,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 1'0 + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5928 1'0 case - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 \jtag_wb_addrsr_update_core + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5928 \jtag_wb_addrsr_update_core end sync always - update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5927 end - attribute \src "libresoc.v:139452.3-139468.6" - process $proc$libresoc.v:139452$5997 + attribute \src "libresoc.v:139774.3-139790.6" + process $proc$libresoc.v:139774$5929 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr__oe$next[0:0]$5998 $2\jtag_wb_addrsr__oe$next[0:0]$6000 - attribute \src "libresoc.v:139453.5-139453.29" + assign $0\jtag_wb_addrsr__oe$next[0:0]$5930 $2\jtag_wb_addrsr__oe$next[0:0]$5932 + attribute \src "libresoc.v:139775.5-139775.29" switch \initial - attribute \src "libresoc.v:139453.9-139453.17" + attribute \src "libresoc.v:139775.9-139775.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$401 + switch \$357 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5999 \jtag_wb_addrsr_isir + assign $1\jtag_wb_addrsr__oe$next[0:0]$5931 \jtag_wb_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5999 1'0 + assign $1\jtag_wb_addrsr__oe$next[0:0]$5931 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr__oe$next[0:0]$6000 1'0 + assign $2\jtag_wb_addrsr__oe$next[0:0]$5932 1'0 case - assign $2\jtag_wb_addrsr__oe$next[0:0]$6000 $1\jtag_wb_addrsr__oe$next[0:0]$5999 + assign $2\jtag_wb_addrsr__oe$next[0:0]$5932 $1\jtag_wb_addrsr__oe$next[0:0]$5931 end sync always - update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5998 + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5930 end - attribute \src "libresoc.v:139469.3-139489.6" - process $proc$libresoc.v:139469$6001 + attribute \src "libresoc.v:139791.3-139811.6" + process $proc$libresoc.v:139791$5933 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_reg$next[28:0]$6002 $3\jtag_wb_addrsr_reg$next[28:0]$6005 - attribute \src "libresoc.v:139470.5-139470.29" + assign $0\jtag_wb_addrsr_reg$next[28:0]$5934 $3\jtag_wb_addrsr_reg$next[28:0]$5937 + attribute \src "libresoc.v:139792.5-139792.29" switch \initial - attribute \src "libresoc.v:139470.9-139470.17" + attribute \src "libresoc.v:139792.9-139792.17" case 1'1 case end @@ -223016,39 +222475,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_reg$next[28:0]$6003 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + assign $1\jtag_wb_addrsr_reg$next[28:0]$5935 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } case - assign $1\jtag_wb_addrsr_reg$next[28:0]$6003 \jtag_wb_addrsr_reg + assign $1\jtag_wb_addrsr_reg$next[28:0]$5935 \jtag_wb_addrsr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \jtag_wb_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr_reg$next[28:0]$6004 \jtag_wb_addrsr__i + assign $2\jtag_wb_addrsr_reg$next[28:0]$5936 \jtag_wb_addrsr__i case - assign $2\jtag_wb_addrsr_reg$next[28:0]$6004 $1\jtag_wb_addrsr_reg$next[28:0]$6003 + assign $2\jtag_wb_addrsr_reg$next[28:0]$5936 $1\jtag_wb_addrsr_reg$next[28:0]$5935 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_addrsr_reg$next[28:0]$6005 29'00000000000000000000000000000 + assign $3\jtag_wb_addrsr_reg$next[28:0]$5937 29'00000000000000000000000000000 case - assign $3\jtag_wb_addrsr_reg$next[28:0]$6005 $2\jtag_wb_addrsr_reg$next[28:0]$6004 + assign $3\jtag_wb_addrsr_reg$next[28:0]$5937 $2\jtag_wb_addrsr_reg$next[28:0]$5936 end sync always - update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$6002 + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5934 end - attribute \src "libresoc.v:139490.3-139498.6" - process $proc$libresoc.v:139490$6006 + attribute \src "libresoc.v:139812.3-139820.6" + process $proc$libresoc.v:139812$5938 assign { } { } assign { } { } - assign $0\jtag_wb_datasr_update_core$next[0:0]$6007 $1\jtag_wb_datasr_update_core$next[0:0]$6008 - attribute \src "libresoc.v:139491.5-139491.29" + assign $0\jtag_wb_datasr_update_core$next[0:0]$5939 $1\jtag_wb_datasr_update_core$next[0:0]$5940 + attribute \src "libresoc.v:139813.5-139813.29" switch \initial - attribute \src "libresoc.v:139491.9-139491.17" + attribute \src "libresoc.v:139813.9-139813.17" case 1'1 case end @@ -223057,21 +222516,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_update_core$next[0:0]$6008 1'0 + assign $1\jtag_wb_datasr_update_core$next[0:0]$5940 1'0 case - assign $1\jtag_wb_datasr_update_core$next[0:0]$6008 \jtag_wb_datasr_update + assign $1\jtag_wb_datasr_update_core$next[0:0]$5940 \jtag_wb_datasr_update end sync always - update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$6007 + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5939 end - attribute \src "libresoc.v:139499.3-139507.6" - process $proc$libresoc.v:139499$6009 + attribute \src "libresoc.v:139821.3-139829.6" + process $proc$libresoc.v:139821$5941 assign { } { } assign { } { } - assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 - attribute \src "libresoc.v:139500.5-139500.29" + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5942 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5943 + attribute \src "libresoc.v:139822.5-139822.29" switch \initial - attribute \src "libresoc.v:139500.9-139500.17" + attribute \src "libresoc.v:139822.9-139822.17" case 1'1 case end @@ -223080,57 +222539,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 1'0 + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5943 1'0 case - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 \jtag_wb_datasr_update_core + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5943 \jtag_wb_datasr_update_core end sync always - update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5942 end - attribute \src "libresoc.v:139508.3-139524.6" - process $proc$libresoc.v:139508$6012 + attribute \src "libresoc.v:139830.3-139846.6" + process $proc$libresoc.v:139830$5944 assign { } { } assign { } { } - assign $0\jtag_wb_datasr__oe$next[1:0]$6013 $2\jtag_wb_datasr__oe$next[1:0]$6015 - attribute \src "libresoc.v:139509.5-139509.29" + assign $0\jtag_wb_datasr__oe$next[1:0]$5945 $2\jtag_wb_datasr__oe$next[1:0]$5947 + attribute \src "libresoc.v:139831.5-139831.29" switch \initial - attribute \src "libresoc.v:139509.9-139509.17" + attribute \src "libresoc.v:139831.9-139831.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$421 + switch \$377 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$6014 \jtag_wb_datasr_isir + assign $1\jtag_wb_datasr__oe$next[1:0]$5946 \jtag_wb_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$6014 2'00 + assign $1\jtag_wb_datasr__oe$next[1:0]$5946 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr__oe$next[1:0]$6015 2'00 + assign $2\jtag_wb_datasr__oe$next[1:0]$5947 2'00 case - assign $2\jtag_wb_datasr__oe$next[1:0]$6015 $1\jtag_wb_datasr__oe$next[1:0]$6014 + assign $2\jtag_wb_datasr__oe$next[1:0]$5947 $1\jtag_wb_datasr__oe$next[1:0]$5946 end sync always - update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$6013 + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5945 end - attribute \src "libresoc.v:139525.3-139545.6" - process $proc$libresoc.v:139525$6016 + attribute \src "libresoc.v:139847.3-139867.6" + process $proc$libresoc.v:139847$5948 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr_reg$next[63:0]$6017 $3\jtag_wb_datasr_reg$next[63:0]$6020 - attribute \src "libresoc.v:139526.5-139526.29" + assign $0\jtag_wb_datasr_reg$next[63:0]$5949 $3\jtag_wb_datasr_reg$next[63:0]$5952 + attribute \src "libresoc.v:139848.5-139848.29" switch \initial - attribute \src "libresoc.v:139526.9-139526.17" + attribute \src "libresoc.v:139848.9-139848.17" case 1'1 case end @@ -223139,39 +222598,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_reg$next[63:0]$6018 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + assign $1\jtag_wb_datasr_reg$next[63:0]$5950 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } case - assign $1\jtag_wb_datasr_reg$next[63:0]$6018 \jtag_wb_datasr_reg + assign $1\jtag_wb_datasr_reg$next[63:0]$5950 \jtag_wb_datasr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \jtag_wb_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr_reg$next[63:0]$6019 \jtag_wb_datasr__i + assign $2\jtag_wb_datasr_reg$next[63:0]$5951 \jtag_wb_datasr__i case - assign $2\jtag_wb_datasr_reg$next[63:0]$6019 $1\jtag_wb_datasr_reg$next[63:0]$6018 + assign $2\jtag_wb_datasr_reg$next[63:0]$5951 $1\jtag_wb_datasr_reg$next[63:0]$5950 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr_reg$next[63:0]$6020 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_datasr_reg$next[63:0]$5952 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb_datasr_reg$next[63:0]$6020 $2\jtag_wb_datasr_reg$next[63:0]$6019 + assign $3\jtag_wb_datasr_reg$next[63:0]$5952 $2\jtag_wb_datasr_reg$next[63:0]$5951 end sync always - update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$6017 + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5949 end - attribute \src "libresoc.v:139546.3-139554.6" - process $proc$libresoc.v:139546$6021 + attribute \src "libresoc.v:139868.3-139876.6" + process $proc$libresoc.v:139868$5953 assign { } { } assign { } { } - assign $0\dmi0_addrsr_update_core$next[0:0]$6022 $1\dmi0_addrsr_update_core$next[0:0]$6023 - attribute \src "libresoc.v:139547.5-139547.29" + assign $0\dmi0_addrsr_update_core$next[0:0]$5954 $1\dmi0_addrsr_update_core$next[0:0]$5955 + attribute \src "libresoc.v:139869.5-139869.29" switch \initial - attribute \src "libresoc.v:139547.9-139547.17" + attribute \src "libresoc.v:139869.9-139869.17" case 1'1 case end @@ -223180,21 +222639,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_update_core$next[0:0]$6023 1'0 + assign $1\dmi0_addrsr_update_core$next[0:0]$5955 1'0 case - assign $1\dmi0_addrsr_update_core$next[0:0]$6023 \dmi0_addrsr_update + assign $1\dmi0_addrsr_update_core$next[0:0]$5955 \dmi0_addrsr_update end sync always - update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$6022 + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5954 end - attribute \src "libresoc.v:139555.3-139563.6" - process $proc$libresoc.v:139555$6024 + attribute \src "libresoc.v:139877.3-139885.6" + process $proc$libresoc.v:139877$5956 assign { } { } assign { } { } - assign $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 - attribute \src "libresoc.v:139556.5-139556.29" + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5957 $1\dmi0_addrsr_update_core_prev$next[0:0]$5958 + attribute \src "libresoc.v:139878.5-139878.29" switch \initial - attribute \src "libresoc.v:139556.9-139556.17" + attribute \src "libresoc.v:139878.9-139878.17" case 1'1 case end @@ -223203,57 +222662,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 1'0 + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5958 1'0 case - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 \dmi0_addrsr_update_core + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5958 \dmi0_addrsr_update_core end sync always - update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5957 end - attribute \src "libresoc.v:139564.3-139580.6" - process $proc$libresoc.v:139564$6027 + attribute \src "libresoc.v:139886.3-139902.6" + process $proc$libresoc.v:139886$5959 assign { } { } assign { } { } - assign $0\dmi0_addrsr__oe$next[0:0]$6028 $2\dmi0_addrsr__oe$next[0:0]$6030 - attribute \src "libresoc.v:139565.5-139565.29" + assign $0\dmi0_addrsr__oe$next[0:0]$5960 $2\dmi0_addrsr__oe$next[0:0]$5962 + attribute \src "libresoc.v:139887.5-139887.29" switch \initial - attribute \src "libresoc.v:139565.9-139565.17" + attribute \src "libresoc.v:139887.9-139887.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$439 + switch \$395 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$6029 \dmi0_addrsr_isir + assign $1\dmi0_addrsr__oe$next[0:0]$5961 \dmi0_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$6029 1'0 + assign $1\dmi0_addrsr__oe$next[0:0]$5961 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_addrsr__oe$next[0:0]$6030 1'0 + assign $2\dmi0_addrsr__oe$next[0:0]$5962 1'0 case - assign $2\dmi0_addrsr__oe$next[0:0]$6030 $1\dmi0_addrsr__oe$next[0:0]$6029 + assign $2\dmi0_addrsr__oe$next[0:0]$5962 $1\dmi0_addrsr__oe$next[0:0]$5961 end sync always - update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$6028 + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5960 end - attribute \src "libresoc.v:139581.3-139601.6" - process $proc$libresoc.v:139581$6031 + attribute \src "libresoc.v:139903.3-139923.6" + process $proc$libresoc.v:139903$5963 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\dmi0_addrsr_reg$next[7:0]$6032 $3\dmi0_addrsr_reg$next[7:0]$6035 - attribute \src "libresoc.v:139582.5-139582.29" + assign $0\dmi0_addrsr_reg$next[7:0]$5964 $3\dmi0_addrsr_reg$next[7:0]$5967 + attribute \src "libresoc.v:139904.5-139904.29" switch \initial - attribute \src "libresoc.v:139582.9-139582.17" + attribute \src "libresoc.v:139904.9-139904.17" case 1'1 case end @@ -223262,39 +222721,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_reg$next[7:0]$6033 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + assign $1\dmi0_addrsr_reg$next[7:0]$5965 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } case - assign $1\dmi0_addrsr_reg$next[7:0]$6033 \dmi0_addrsr_reg + assign $1\dmi0_addrsr_reg$next[7:0]$5965 \dmi0_addrsr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \dmi0_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_addrsr_reg$next[7:0]$6034 \dmi0_addrsr__i + assign $2\dmi0_addrsr_reg$next[7:0]$5966 \dmi0_addrsr__i case - assign $2\dmi0_addrsr_reg$next[7:0]$6034 $1\dmi0_addrsr_reg$next[7:0]$6033 + assign $2\dmi0_addrsr_reg$next[7:0]$5966 $1\dmi0_addrsr_reg$next[7:0]$5965 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_addrsr_reg$next[7:0]$6035 8'00000000 + assign $3\dmi0_addrsr_reg$next[7:0]$5967 8'00000000 case - assign $3\dmi0_addrsr_reg$next[7:0]$6035 $2\dmi0_addrsr_reg$next[7:0]$6034 + assign $3\dmi0_addrsr_reg$next[7:0]$5967 $2\dmi0_addrsr_reg$next[7:0]$5966 end sync always - update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$6032 + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5964 end - attribute \src "libresoc.v:139602.3-139610.6" - process $proc$libresoc.v:139602$6036 + attribute \src "libresoc.v:139924.3-139932.6" + process $proc$libresoc.v:139924$5968 assign { } { } assign { } { } - assign $0\dmi0_datasr_update_core$next[0:0]$6037 $1\dmi0_datasr_update_core$next[0:0]$6038 - attribute \src "libresoc.v:139603.5-139603.29" + assign $0\dmi0_datasr_update_core$next[0:0]$5969 $1\dmi0_datasr_update_core$next[0:0]$5970 + attribute \src "libresoc.v:139925.5-139925.29" switch \initial - attribute \src "libresoc.v:139603.9-139603.17" + attribute \src "libresoc.v:139925.9-139925.17" case 1'1 case end @@ -223303,21 +222762,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_update_core$next[0:0]$6038 1'0 + assign $1\dmi0_datasr_update_core$next[0:0]$5970 1'0 case - assign $1\dmi0_datasr_update_core$next[0:0]$6038 \dmi0_datasr_update + assign $1\dmi0_datasr_update_core$next[0:0]$5970 \dmi0_datasr_update end sync always - update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$6037 + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5969 end - attribute \src "libresoc.v:139611.3-139619.6" - process $proc$libresoc.v:139611$6039 + attribute \src "libresoc.v:139933.3-139941.6" + process $proc$libresoc.v:139933$5971 assign { } { } assign { } { } - assign $0\dmi0_datasr_update_core_prev$next[0:0]$6040 $1\dmi0_datasr_update_core_prev$next[0:0]$6041 - attribute \src "libresoc.v:139612.5-139612.29" + assign $0\dmi0_datasr_update_core_prev$next[0:0]$5972 $1\dmi0_datasr_update_core_prev$next[0:0]$5973 + attribute \src "libresoc.v:139934.5-139934.29" switch \initial - attribute \src "libresoc.v:139612.9-139612.17" + attribute \src "libresoc.v:139934.9-139934.17" case 1'1 case end @@ -223326,57 +222785,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_update_core_prev$next[0:0]$6041 1'0 + assign $1\dmi0_datasr_update_core_prev$next[0:0]$5973 1'0 case - assign $1\dmi0_datasr_update_core_prev$next[0:0]$6041 \dmi0_datasr_update_core + assign $1\dmi0_datasr_update_core_prev$next[0:0]$5973 \dmi0_datasr_update_core end sync always - update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$6040 + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5972 end - attribute \src "libresoc.v:139620.3-139636.6" - process $proc$libresoc.v:139620$6042 + attribute \src "libresoc.v:139942.3-139958.6" + process $proc$libresoc.v:139942$5974 assign { } { } assign { } { } - assign $0\dmi0_datasr__oe$next[1:0]$6043 $2\dmi0_datasr__oe$next[1:0]$6045 - attribute \src "libresoc.v:139621.5-139621.29" + assign $0\dmi0_datasr__oe$next[1:0]$5975 $2\dmi0_datasr__oe$next[1:0]$5977 + attribute \src "libresoc.v:139943.5-139943.29" switch \initial - attribute \src "libresoc.v:139621.9-139621.17" + attribute \src "libresoc.v:139943.9-139943.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$459 + switch \$415 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$6044 \dmi0_datasr_isir + assign $1\dmi0_datasr__oe$next[1:0]$5976 \dmi0_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$6044 2'00 + assign $1\dmi0_datasr__oe$next[1:0]$5976 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr__oe$next[1:0]$6045 2'00 + assign $2\dmi0_datasr__oe$next[1:0]$5977 2'00 case - assign $2\dmi0_datasr__oe$next[1:0]$6045 $1\dmi0_datasr__oe$next[1:0]$6044 + assign $2\dmi0_datasr__oe$next[1:0]$5977 $1\dmi0_datasr__oe$next[1:0]$5976 end sync always - update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$6043 + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5975 end - attribute \src "libresoc.v:139637.3-139657.6" - process $proc$libresoc.v:139637$6046 + attribute \src "libresoc.v:139959.3-139979.6" + process $proc$libresoc.v:139959$5978 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\dmi0_datasr_reg$next[63:0]$6047 $3\dmi0_datasr_reg$next[63:0]$6050 - attribute \src "libresoc.v:139638.5-139638.29" + assign $0\dmi0_datasr_reg$next[63:0]$5979 $3\dmi0_datasr_reg$next[63:0]$5982 + attribute \src "libresoc.v:139960.5-139960.29" switch \initial - attribute \src "libresoc.v:139638.9-139638.17" + attribute \src "libresoc.v:139960.9-139960.17" case 1'1 case end @@ -223385,39 +222844,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_reg$next[63:0]$6048 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } + assign $1\dmi0_datasr_reg$next[63:0]$5980 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } case - assign $1\dmi0_datasr_reg$next[63:0]$6048 \dmi0_datasr_reg + assign $1\dmi0_datasr_reg$next[63:0]$5980 \dmi0_datasr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \dmi0_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr_reg$next[63:0]$6049 \dmi0_datasr__i + assign $2\dmi0_datasr_reg$next[63:0]$5981 \dmi0_datasr__i case - assign $2\dmi0_datasr_reg$next[63:0]$6049 $1\dmi0_datasr_reg$next[63:0]$6048 + assign $2\dmi0_datasr_reg$next[63:0]$5981 $1\dmi0_datasr_reg$next[63:0]$5980 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr_reg$next[63:0]$6050 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0_datasr_reg$next[63:0]$5982 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0_datasr_reg$next[63:0]$6050 $2\dmi0_datasr_reg$next[63:0]$6049 + assign $3\dmi0_datasr_reg$next[63:0]$5982 $2\dmi0_datasr_reg$next[63:0]$5981 end sync always - update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$6047 + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5979 end - attribute \src "libresoc.v:139658.3-139666.6" - process $proc$libresoc.v:139658$6051 + attribute \src "libresoc.v:139980.3-139988.6" + process $proc$libresoc.v:139980$5983 assign { } { } assign { } { } - assign $0\sr5_update_core$next[0:0]$6052 $1\sr5_update_core$next[0:0]$6053 - attribute \src "libresoc.v:139659.5-139659.29" + assign $0\sr5_update_core$next[0:0]$5984 $1\sr5_update_core$next[0:0]$5985 + attribute \src "libresoc.v:139981.5-139981.29" switch \initial - attribute \src "libresoc.v:139659.9-139659.17" + attribute \src "libresoc.v:139981.9-139981.17" case 1'1 case end @@ -223426,21 +222885,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_update_core$next[0:0]$6053 1'0 + assign $1\sr5_update_core$next[0:0]$5985 1'0 case - assign $1\sr5_update_core$next[0:0]$6053 \sr5_update + assign $1\sr5_update_core$next[0:0]$5985 \sr5_update end sync always - update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6052 + update \sr5_update_core$next $0\sr5_update_core$next[0:0]$5984 end - attribute \src "libresoc.v:139667.3-139675.6" - process $proc$libresoc.v:139667$6054 + attribute \src "libresoc.v:139989.3-139997.6" + process $proc$libresoc.v:139989$5986 assign { } { } assign { } { } - assign $0\sr5_update_core_prev$next[0:0]$6055 $1\sr5_update_core_prev$next[0:0]$6056 - attribute \src "libresoc.v:139668.5-139668.29" + assign $0\sr5_update_core_prev$next[0:0]$5987 $1\sr5_update_core_prev$next[0:0]$5988 + attribute \src "libresoc.v:139990.5-139990.29" switch \initial - attribute \src "libresoc.v:139668.9-139668.17" + attribute \src "libresoc.v:139990.9-139990.17" case 1'1 case end @@ -223449,57 +222908,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_update_core_prev$next[0:0]$6056 1'0 + assign $1\sr5_update_core_prev$next[0:0]$5988 1'0 case - assign $1\sr5_update_core_prev$next[0:0]$6056 \sr5_update_core + assign $1\sr5_update_core_prev$next[0:0]$5988 \sr5_update_core end sync always - update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6055 + update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$5987 end - attribute \src "libresoc.v:139676.3-139692.6" - process $proc$libresoc.v:139676$6057 + attribute \src "libresoc.v:139998.3-140014.6" + process $proc$libresoc.v:139998$5989 assign { } { } assign { } { } - assign $0\sr5__oe$next[0:0]$6058 $2\sr5__oe$next[0:0]$6060 - attribute \src "libresoc.v:139677.5-139677.29" + assign $0\sr5__oe$next[0:0]$5990 $2\sr5__oe$next[0:0]$5992 + attribute \src "libresoc.v:139999.5-139999.29" switch \initial - attribute \src "libresoc.v:139677.9-139677.17" + attribute \src "libresoc.v:139999.9-139999.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$477 + switch \$433 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5__oe$next[0:0]$6059 \sr5_isir + assign $1\sr5__oe$next[0:0]$5991 \sr5_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\sr5__oe$next[0:0]$6059 1'0 + assign $1\sr5__oe$next[0:0]$5991 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr5__oe$next[0:0]$6060 1'0 + assign $2\sr5__oe$next[0:0]$5992 1'0 case - assign $2\sr5__oe$next[0:0]$6060 $1\sr5__oe$next[0:0]$6059 + assign $2\sr5__oe$next[0:0]$5992 $1\sr5__oe$next[0:0]$5991 end sync always - update \sr5__oe$next $0\sr5__oe$next[0:0]$6058 + update \sr5__oe$next $0\sr5__oe$next[0:0]$5990 end - attribute \src "libresoc.v:139693.3-139713.6" - process $proc$libresoc.v:139693$6061 + attribute \src "libresoc.v:140015.3-140035.6" + process $proc$libresoc.v:140015$5993 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sr5_reg$next[2:0]$6062 $3\sr5_reg$next[2:0]$6065 - attribute \src "libresoc.v:139694.5-139694.29" + assign $0\sr5_reg$next[2:0]$5994 $3\sr5_reg$next[2:0]$5997 + attribute \src "libresoc.v:140016.5-140016.29" switch \initial - attribute \src "libresoc.v:139694.9-139694.17" + attribute \src "libresoc.v:140016.9-140016.17" case 1'1 case end @@ -223508,38 +222967,38 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_reg$next[2:0]$6063 { \TAP_bus__tdi \sr5_reg [2:1] } + assign $1\sr5_reg$next[2:0]$5995 { \TAP_bus__tdi \sr5_reg [2:1] } case - assign $1\sr5_reg$next[2:0]$6063 \sr5_reg + assign $1\sr5_reg$next[2:0]$5995 \sr5_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \sr5_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr5_reg$next[2:0]$6064 \sr5__i + assign $2\sr5_reg$next[2:0]$5996 \sr5__i case - assign $2\sr5_reg$next[2:0]$6064 $1\sr5_reg$next[2:0]$6063 + assign $2\sr5_reg$next[2:0]$5996 $1\sr5_reg$next[2:0]$5995 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr5_reg$next[2:0]$6065 3'000 + assign $3\sr5_reg$next[2:0]$5997 3'000 case - assign $3\sr5_reg$next[2:0]$6065 $2\sr5_reg$next[2:0]$6064 + assign $3\sr5_reg$next[2:0]$5997 $2\sr5_reg$next[2:0]$5996 end sync always - update \sr5_reg$next $0\sr5_reg$next[2:0]$6062 + update \sr5_reg$next $0\sr5_reg$next[2:0]$5994 end - attribute \src "libresoc.v:139714.3-139740.6" - process $proc$libresoc.v:139714$6066 + attribute \src "libresoc.v:140036.3-140062.6" + process $proc$libresoc.v:140036$5998 assign { } { } assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:139715.5-139715.29" + attribute \src "libresoc.v:140037.5-140037.29" switch \initial - attribute \src "libresoc.v:139715.9-139715.17" + attribute \src "libresoc.v:140037.9-140037.17" case 1'1 case end @@ -223577,15 +223036,15 @@ module \jtag sync always update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] end - attribute \src "libresoc.v:139741.3-139773.6" - process $proc$libresoc.v:139741$6067 + attribute \src "libresoc.v:140063.3-140107.6" + process $proc$libresoc.v:140063$5999 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb__adr$next[28:0]$6068 $4\jtag_wb__adr$next[28:0]$6072 - attribute \src "libresoc.v:139742.5-139742.29" + assign $0\jtag_wb__adr$next[28:0]$6000 $4\jtag_wb__adr$next[28:0]$6004 + attribute \src "libresoc.v:140064.5-140064.29" switch \initial - attribute \src "libresoc.v:139742.9-139742.17" + attribute \src "libresoc.v:140064.9-140064.17" case 1'1 case end @@ -223594,57 +223053,66 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\jtag_wb__adr$next[28:0]$6069 $2\jtag_wb__adr$next[28:0]$6070 + assign $1\jtag_wb__adr$next[28:0]$6001 $2\jtag_wb__adr$next[28:0]$6002 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\jtag_wb__adr$next[28:0]$6070 \jtag_wb_addrsr__o + assign $2\jtag_wb__adr$next[28:0]$6002 \jtag_wb_addrsr__o attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\jtag_wb__adr$next[28:0]$6070 \$491 [28:0] + assign $2\jtag_wb__adr$next[28:0]$6002 \$447 [28:0] case - assign $2\jtag_wb__adr$next[28:0]$6070 \jtag_wb__adr + assign $2\jtag_wb__adr$next[28:0]$6002 \jtag_wb__adr end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\jtag_wb__adr$next[28:0]$6001 \jtag_wb__adr + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\jtag_wb__adr$next[28:0]$6001 \jtag_wb__adr + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\jtag_wb__adr$next[28:0]$6001 \jtag_wb__adr + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\jtag_wb__adr$next[28:0]$6069 $3\jtag_wb__adr$next[28:0]$6071 + assign $1\jtag_wb__adr$next[28:0]$6001 $3\jtag_wb__adr$next[28:0]$6003 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb__adr$next[28:0]$6071 \$494 [28:0] + assign $3\jtag_wb__adr$next[28:0]$6003 \$450 [28:0] case - assign $3\jtag_wb__adr$next[28:0]$6071 \jtag_wb__adr + assign $3\jtag_wb__adr$next[28:0]$6003 \jtag_wb__adr end case - assign $1\jtag_wb__adr$next[28:0]$6069 \jtag_wb__adr + assign $1\jtag_wb__adr$next[28:0]$6001 \jtag_wb__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\jtag_wb__adr$next[28:0]$6072 29'00000000000000000000000000000 + assign $4\jtag_wb__adr$next[28:0]$6004 29'00000000000000000000000000000 case - assign $4\jtag_wb__adr$next[28:0]$6072 $1\jtag_wb__adr$next[28:0]$6069 + assign $4\jtag_wb__adr$next[28:0]$6004 $1\jtag_wb__adr$next[28:0]$6001 end sync always - update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6068 + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6000 end - attribute \src "libresoc.v:139774.3-139826.6" - process $proc$libresoc.v:139774$6073 + attribute \src "libresoc.v:140108.3-140160.6" + process $proc$libresoc.v:140108$6005 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[2:0]$6074 $5\fsm_state$next[2:0]$6079 - attribute \src "libresoc.v:139775.5-139775.29" + assign $0\fsm_state$next[2:0]$6006 $5\fsm_state$next[2:0]$6011 + attribute \src "libresoc.v:140109.5-140109.29" switch \initial - attribute \src "libresoc.v:139775.9-139775.17" + attribute \src "libresoc.v:140109.9-140109.17" case 1'1 case end @@ -223653,82 +223121,82 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\fsm_state$next[2:0]$6075 $2\fsm_state$next[2:0]$6076 + assign $1\fsm_state$next[2:0]$6007 $2\fsm_state$next[2:0]$6008 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\fsm_state$next[2:0]$6076 3'001 + assign $2\fsm_state$next[2:0]$6008 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\fsm_state$next[2:0]$6076 3'001 + assign $2\fsm_state$next[2:0]$6008 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\fsm_state$next[2:0]$6076 3'010 + assign $2\fsm_state$next[2:0]$6008 3'010 case - assign $2\fsm_state$next[2:0]$6076 \fsm_state + assign $2\fsm_state$next[2:0]$6008 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\fsm_state$next[2:0]$6075 3'011 + assign $1\fsm_state$next[2:0]$6007 3'011 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\fsm_state$next[2:0]$6075 $3\fsm_state$next[2:0]$6077 + assign $1\fsm_state$next[2:0]$6007 $3\fsm_state$next[2:0]$6009 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[2:0]$6077 3'000 + assign $3\fsm_state$next[2:0]$6009 3'000 case - assign $3\fsm_state$next[2:0]$6077 \fsm_state + assign $3\fsm_state$next[2:0]$6009 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\fsm_state$next[2:0]$6075 3'100 + assign $1\fsm_state$next[2:0]$6007 3'100 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\fsm_state$next[2:0]$6075 $4\fsm_state$next[2:0]$6078 + assign $1\fsm_state$next[2:0]$6007 $4\fsm_state$next[2:0]$6010 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[2:0]$6078 3'001 + assign $4\fsm_state$next[2:0]$6010 3'001 case - assign $4\fsm_state$next[2:0]$6078 \fsm_state + assign $4\fsm_state$next[2:0]$6010 \fsm_state end case - assign $1\fsm_state$next[2:0]$6075 \fsm_state + assign $1\fsm_state$next[2:0]$6007 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[2:0]$6079 3'000 + assign $5\fsm_state$next[2:0]$6011 3'000 case - assign $5\fsm_state$next[2:0]$6079 $1\fsm_state$next[2:0]$6075 + assign $5\fsm_state$next[2:0]$6011 $1\fsm_state$next[2:0]$6007 end sync always - update \fsm_state$next $0\fsm_state$next[2:0]$6074 + update \fsm_state$next $0\fsm_state$next[2:0]$6006 end - attribute \src "libresoc.v:139827.3-139853.6" - process $proc$libresoc.v:139827$6080 + attribute \src "libresoc.v:140161.3-140187.6" + process $proc$libresoc.v:140161$6012 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb__dat_w$next[63:0]$6081 $3\jtag_wb__dat_w$next[63:0]$6084 - attribute \src "libresoc.v:139828.5-139828.29" + assign $0\jtag_wb__dat_w$next[63:0]$6013 $3\jtag_wb__dat_w$next[63:0]$6016 + attribute \src "libresoc.v:140162.5-140162.29" switch \initial - attribute \src "libresoc.v:139828.9-139828.17" + attribute \src "libresoc.v:140162.9-140162.17" case 1'1 case end @@ -223737,314 +223205,335 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\jtag_wb__dat_w$next[63:0]$6082 $2\jtag_wb__dat_w$next[63:0]$6083 + assign $1\jtag_wb__dat_w$next[63:0]$6014 $2\jtag_wb__dat_w$next[63:0]$6015 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6015 \jtag_wb__dat_w attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6015 \jtag_wb__dat_w attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb_datasr__o + assign $2\jtag_wb__dat_w$next[63:0]$6015 \jtag_wb_datasr__o case - assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6015 \jtag_wb__dat_w end case - assign $1\jtag_wb__dat_w$next[63:0]$6082 \jtag_wb__dat_w + assign $1\jtag_wb__dat_w$next[63:0]$6014 \jtag_wb__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb__dat_w$next[63:0]$6084 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb__dat_w$next[63:0]$6016 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb__dat_w$next[63:0]$6084 $1\jtag_wb__dat_w$next[63:0]$6082 + assign $3\jtag_wb__dat_w$next[63:0]$6016 $1\jtag_wb__dat_w$next[63:0]$6014 end sync always - update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6081 + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6013 end - attribute \src "libresoc.v:139854.3-139874.6" - process $proc$libresoc.v:139854$6085 + attribute \src "libresoc.v:140188.3-140216.6" + process $proc$libresoc.v:140188$6017 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr__i$next[63:0]$6086 $3\jtag_wb_datasr__i$next[63:0]$6089 - attribute \src "libresoc.v:139855.5-139855.29" + assign $0\jtag_wb_datasr__i$next[63:0]$6018 $3\jtag_wb_datasr__i$next[63:0]$6021 + attribute \src "libresoc.v:140189.5-140189.29" switch \initial - attribute \src "libresoc.v:139855.9-139855.17" + attribute \src "libresoc.v:140189.9-140189.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\jtag_wb_datasr__i$next[63:0]$6019 \jtag_wb_datasr__i + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\jtag_wb_datasr__i$next[63:0]$6019 \jtag_wb_datasr__i + attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\jtag_wb_datasr__i$next[63:0]$6087 $2\jtag_wb_datasr__i$next[63:0]$6088 + assign $1\jtag_wb_datasr__i$next[63:0]$6019 $2\jtag_wb_datasr__i$next[63:0]$6020 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr__i$next[63:0]$6088 \jtag_wb__dat_r + assign $2\jtag_wb_datasr__i$next[63:0]$6020 \jtag_wb__dat_r case - assign $2\jtag_wb_datasr__i$next[63:0]$6088 \jtag_wb_datasr__i + assign $2\jtag_wb_datasr__i$next[63:0]$6020 \jtag_wb_datasr__i end case - assign $1\jtag_wb_datasr__i$next[63:0]$6087 \jtag_wb_datasr__i + assign $1\jtag_wb_datasr__i$next[63:0]$6019 \jtag_wb_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr__i$next[63:0]$6089 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_datasr__i$next[63:0]$6021 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb_datasr__i$next[63:0]$6089 $1\jtag_wb_datasr__i$next[63:0]$6087 + assign $3\jtag_wb_datasr__i$next[63:0]$6021 $1\jtag_wb_datasr__i$next[63:0]$6019 end sync always - update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6086 + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6018 end - attribute \src "libresoc.v:139875.3-139907.6" - process $proc$libresoc.v:139875$6090 + attribute \src "libresoc.v:140217.3-140261.6" + process $proc$libresoc.v:140217$6022 assign { } { } assign { } { } assign { } { } - assign $0\dmi0__addr_i$next[3:0]$6091 $4\dmi0__addr_i$next[3:0]$6095 - attribute \src "libresoc.v:139876.5-139876.29" + assign $0\dmi0__addr_i$next[3:0]$6023 $4\dmi0__addr_i$next[3:0]$6027 + attribute \src "libresoc.v:140218.5-140218.29" switch \initial - attribute \src "libresoc.v:139876.9-139876.17" + attribute \src "libresoc.v:140218.9-140218.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$499 + switch \fsm_state$455 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\dmi0__addr_i$next[3:0]$6092 $2\dmi0__addr_i$next[3:0]$6093 + assign $1\dmi0__addr_i$next[3:0]$6024 $2\dmi0__addr_i$next[3:0]$6025 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\dmi0__addr_i$next[3:0]$6093 \dmi0_addrsr__o [3:0] + assign $2\dmi0__addr_i$next[3:0]$6025 \dmi0_addrsr__o [3:0] attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\dmi0__addr_i$next[3:0]$6093 \$508 [3:0] + assign $2\dmi0__addr_i$next[3:0]$6025 \$464 [3:0] case - assign $2\dmi0__addr_i$next[3:0]$6093 \dmi0__addr_i + assign $2\dmi0__addr_i$next[3:0]$6025 \dmi0__addr_i end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\dmi0__addr_i$next[3:0]$6024 \dmi0__addr_i + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\dmi0__addr_i$next[3:0]$6024 \dmi0__addr_i + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\dmi0__addr_i$next[3:0]$6024 \dmi0__addr_i + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\dmi0__addr_i$next[3:0]$6092 $3\dmi0__addr_i$next[3:0]$6094 + assign $1\dmi0__addr_i$next[3:0]$6024 $3\dmi0__addr_i$next[3:0]$6026 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0__addr_i$next[3:0]$6094 \$511 [3:0] + assign $3\dmi0__addr_i$next[3:0]$6026 \$467 [3:0] case - assign $3\dmi0__addr_i$next[3:0]$6094 \dmi0__addr_i + assign $3\dmi0__addr_i$next[3:0]$6026 \dmi0__addr_i end case - assign $1\dmi0__addr_i$next[3:0]$6092 \dmi0__addr_i + assign $1\dmi0__addr_i$next[3:0]$6024 \dmi0__addr_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dmi0__addr_i$next[3:0]$6095 4'0000 + assign $4\dmi0__addr_i$next[3:0]$6027 4'0000 case - assign $4\dmi0__addr_i$next[3:0]$6095 $1\dmi0__addr_i$next[3:0]$6092 + assign $4\dmi0__addr_i$next[3:0]$6027 $1\dmi0__addr_i$next[3:0]$6024 end sync always - update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6091 + update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6023 end - attribute \src "libresoc.v:139908.3-139960.6" - process $proc$libresoc.v:139908$6096 + attribute \src "libresoc.v:140262.3-140314.6" + process $proc$libresoc.v:140262$6028 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$499$next[2:0]$6097 $5\fsm_state$499$next[2:0]$6102 - attribute \src "libresoc.v:139909.5-139909.29" + assign $0\fsm_state$455$next[2:0]$6029 $5\fsm_state$455$next[2:0]$6034 + attribute \src "libresoc.v:140263.5-140263.29" switch \initial - attribute \src "libresoc.v:139909.9-139909.17" + attribute \src "libresoc.v:140263.9-140263.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$499 + switch \fsm_state$455 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\fsm_state$499$next[2:0]$6098 $2\fsm_state$499$next[2:0]$6099 + assign $1\fsm_state$455$next[2:0]$6030 $2\fsm_state$455$next[2:0]$6031 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\fsm_state$499$next[2:0]$6099 3'001 + assign $2\fsm_state$455$next[2:0]$6031 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\fsm_state$499$next[2:0]$6099 3'001 + assign $2\fsm_state$455$next[2:0]$6031 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\fsm_state$499$next[2:0]$6099 3'010 + assign $2\fsm_state$455$next[2:0]$6031 3'010 case - assign $2\fsm_state$499$next[2:0]$6099 \fsm_state$499 + assign $2\fsm_state$455$next[2:0]$6031 \fsm_state$455 end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\fsm_state$499$next[2:0]$6098 3'011 + assign $1\fsm_state$455$next[2:0]$6030 3'011 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\fsm_state$499$next[2:0]$6098 $3\fsm_state$499$next[2:0]$6100 + assign $1\fsm_state$455$next[2:0]$6030 $3\fsm_state$455$next[2:0]$6032 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$499$next[2:0]$6100 3'000 + assign $3\fsm_state$455$next[2:0]$6032 3'000 case - assign $3\fsm_state$499$next[2:0]$6100 \fsm_state$499 + assign $3\fsm_state$455$next[2:0]$6032 \fsm_state$455 end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\fsm_state$499$next[2:0]$6098 3'100 + assign $1\fsm_state$455$next[2:0]$6030 3'100 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\fsm_state$499$next[2:0]$6098 $4\fsm_state$499$next[2:0]$6101 + assign $1\fsm_state$455$next[2:0]$6030 $4\fsm_state$455$next[2:0]$6033 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$499$next[2:0]$6101 3'001 + assign $4\fsm_state$455$next[2:0]$6033 3'001 case - assign $4\fsm_state$499$next[2:0]$6101 \fsm_state$499 + assign $4\fsm_state$455$next[2:0]$6033 \fsm_state$455 end case - assign $1\fsm_state$499$next[2:0]$6098 \fsm_state$499 + assign $1\fsm_state$455$next[2:0]$6030 \fsm_state$455 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$499$next[2:0]$6102 3'000 + assign $5\fsm_state$455$next[2:0]$6034 3'000 case - assign $5\fsm_state$499$next[2:0]$6102 $1\fsm_state$499$next[2:0]$6098 + assign $5\fsm_state$455$next[2:0]$6034 $1\fsm_state$455$next[2:0]$6030 end sync always - update \fsm_state$499$next $0\fsm_state$499$next[2:0]$6097 + update \fsm_state$455$next $0\fsm_state$455$next[2:0]$6029 end - attribute \src "libresoc.v:139961.3-139987.6" - process $proc$libresoc.v:139961$6103 + attribute \src "libresoc.v:140315.3-140341.6" + process $proc$libresoc.v:140315$6035 assign { } { } assign { } { } assign { } { } - assign $0\dmi0__din$next[63:0]$6104 $3\dmi0__din$next[63:0]$6107 - attribute \src "libresoc.v:139962.5-139962.29" + assign $0\dmi0__din$next[63:0]$6036 $3\dmi0__din$next[63:0]$6039 + attribute \src "libresoc.v:140316.5-140316.29" switch \initial - attribute \src "libresoc.v:139962.9-139962.17" + attribute \src "libresoc.v:140316.9-140316.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$499 + switch \fsm_state$455 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\dmi0__din$next[63:0]$6105 $2\dmi0__din$next[63:0]$6106 + assign $1\dmi0__din$next[63:0]$6037 $2\dmi0__din$next[63:0]$6038 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $2\dmi0__din$next[63:0]$6106 \dmi0__din + assign $2\dmi0__din$next[63:0]$6038 \dmi0__din attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $2\dmi0__din$next[63:0]$6106 \dmi0__din + assign $2\dmi0__din$next[63:0]$6038 \dmi0__din attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\dmi0__din$next[63:0]$6106 \dmi0_datasr__o + assign $2\dmi0__din$next[63:0]$6038 \dmi0_datasr__o case - assign $2\dmi0__din$next[63:0]$6106 \dmi0__din + assign $2\dmi0__din$next[63:0]$6038 \dmi0__din end case - assign $1\dmi0__din$next[63:0]$6105 \dmi0__din + assign $1\dmi0__din$next[63:0]$6037 \dmi0__din end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0__din$next[63:0]$6107 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0__din$next[63:0]$6039 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0__din$next[63:0]$6107 $1\dmi0__din$next[63:0]$6105 + assign $3\dmi0__din$next[63:0]$6039 $1\dmi0__din$next[63:0]$6037 end sync always - update \dmi0__din$next $0\dmi0__din$next[63:0]$6104 + update \dmi0__din$next $0\dmi0__din$next[63:0]$6036 end - attribute \src "libresoc.v:139988.3-140008.6" - process $proc$libresoc.v:139988$6108 + attribute \src "libresoc.v:140342.3-140370.6" + process $proc$libresoc.v:140342$6040 assign { } { } assign { } { } assign { } { } - assign $0\dmi0_datasr__i$next[63:0]$6109 $3\dmi0_datasr__i$next[63:0]$6112 - attribute \src "libresoc.v:139989.5-139989.29" + assign $0\dmi0_datasr__i$next[63:0]$6041 $3\dmi0_datasr__i$next[63:0]$6044 + attribute \src "libresoc.v:140343.5-140343.29" switch \initial - attribute \src "libresoc.v:139989.9-139989.17" + attribute \src "libresoc.v:140343.9-140343.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$499 + switch \fsm_state$455 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\dmi0_datasr__i$next[63:0]$6042 \dmi0_datasr__i + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\dmi0_datasr__i$next[63:0]$6042 \dmi0_datasr__i attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\dmi0_datasr__i$next[63:0]$6110 $2\dmi0_datasr__i$next[63:0]$6111 + assign $1\dmi0_datasr__i$next[63:0]$6042 $2\dmi0_datasr__i$next[63:0]$6043 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr__i$next[63:0]$6111 \dmi0__dout + assign $2\dmi0_datasr__i$next[63:0]$6043 \dmi0__dout case - assign $2\dmi0_datasr__i$next[63:0]$6111 \dmi0_datasr__i + assign $2\dmi0_datasr__i$next[63:0]$6043 \dmi0_datasr__i end case - assign $1\dmi0_datasr__i$next[63:0]$6110 \dmi0_datasr__i + assign $1\dmi0_datasr__i$next[63:0]$6042 \dmi0_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr__i$next[63:0]$6112 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0_datasr__i$next[63:0]$6044 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0_datasr__i$next[63:0]$6112 $1\dmi0_datasr__i$next[63:0]$6110 + assign $3\dmi0_datasr__i$next[63:0]$6044 $1\dmi0_datasr__i$next[63:0]$6042 end sync always - update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6109 + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6041 end - attribute \src "libresoc.v:140009.3-140029.6" - process $proc$libresoc.v:140009$6113 + attribute \src "libresoc.v:140371.3-140391.6" + process $proc$libresoc.v:140371$6045 assign { } { } assign { } { } assign { } { } @@ -224054,12 +223543,12 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign $0\wb_dcache_en$next[0:0]$6114 $2\wb_dcache_en$next[0:0]$6120 - assign $0\wb_icache_en$next[0:0]$6115 $2\wb_icache_en$next[0:0]$6121 - assign $0\wb_sram_en$next[0:0]$6116 $2\wb_sram_en$next[0:0]$6122 - attribute \src "libresoc.v:140010.5-140010.29" + assign $0\wb_dcache_en$next[0:0]$6046 $2\wb_dcache_en$next[0:0]$6052 + assign $0\wb_icache_en$next[0:0]$6047 $2\wb_icache_en$next[0:0]$6053 + assign $0\wb_sram_en$next[0:0]$6048 $2\wb_sram_en$next[0:0]$6054 + attribute \src "libresoc.v:140372.5-140372.29" switch \initial - attribute \src "libresoc.v:140010.9-140010.17" + attribute \src "libresoc.v:140372.9-140372.17" case 1'1 case end @@ -224070,11 +223559,11 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign { $1\wb_sram_en$next[0:0]$6119 $1\wb_dcache_en$next[0:0]$6117 $1\wb_icache_en$next[0:0]$6118 } \sr5__o + assign { $1\wb_sram_en$next[0:0]$6051 $1\wb_dcache_en$next[0:0]$6049 $1\wb_icache_en$next[0:0]$6050 } \sr5__o case - assign $1\wb_dcache_en$next[0:0]$6117 \wb_dcache_en - assign $1\wb_icache_en$next[0:0]$6118 \wb_icache_en - assign $1\wb_sram_en$next[0:0]$6119 \wb_sram_en + assign $1\wb_dcache_en$next[0:0]$6049 \wb_dcache_en + assign $1\wb_icache_en$next[0:0]$6050 \wb_icache_en + assign $1\wb_sram_en$next[0:0]$6051 \wb_sram_en end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -224083,27 +223572,27 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign $2\wb_icache_en$next[0:0]$6121 1'1 - assign $2\wb_dcache_en$next[0:0]$6120 1'1 - assign $2\wb_sram_en$next[0:0]$6122 1'1 + assign $2\wb_icache_en$next[0:0]$6053 1'1 + assign $2\wb_dcache_en$next[0:0]$6052 1'1 + assign $2\wb_sram_en$next[0:0]$6054 1'1 case - assign $2\wb_dcache_en$next[0:0]$6120 $1\wb_dcache_en$next[0:0]$6117 - assign $2\wb_icache_en$next[0:0]$6121 $1\wb_icache_en$next[0:0]$6118 - assign $2\wb_sram_en$next[0:0]$6122 $1\wb_sram_en$next[0:0]$6119 + assign $2\wb_dcache_en$next[0:0]$6052 $1\wb_dcache_en$next[0:0]$6049 + assign $2\wb_icache_en$next[0:0]$6053 $1\wb_icache_en$next[0:0]$6050 + assign $2\wb_sram_en$next[0:0]$6054 $1\wb_sram_en$next[0:0]$6051 end sync always - update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6114 - update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6115 - update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6116 + update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6046 + update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6047 + update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6048 end - attribute \src "libresoc.v:140030.3-140039.6" - process $proc$libresoc.v:140030$6123 + attribute \src "libresoc.v:140392.3-140401.6" + process $proc$libresoc.v:140392$6055 assign { } { } assign { } { } assign $0\sr5__i[2:0] $1\sr5__i[2:0] - attribute \src "libresoc.v:140031.5-140031.29" + attribute \src "libresoc.v:140393.5-140393.29" switch \initial - attribute \src "libresoc.v:140031.9-140031.17" + attribute \src "libresoc.v:140393.9-140393.17" case 1'1 case end @@ -224119,15 +223608,15 @@ module \jtag sync always update \sr5__i $0\sr5__i[2:0] end - attribute \src "libresoc.v:140040.3-140057.6" - process $proc$libresoc.v:140040$6124 + attribute \src "libresoc.v:140402.3-140419.6" + process $proc$libresoc.v:140402$6056 assign { } { } assign { } { } assign { } { } - assign $0\io_sr$next[151:0]$6125 $2\io_sr$next[151:0]$6127 - attribute \src "libresoc.v:140041.5-140041.29" + assign $0\io_sr$next[129:0]$6057 $2\io_sr$next[129:0]$6059 + attribute \src "libresoc.v:140403.5-140403.29" switch \initial - attribute \src "libresoc.v:140041.9-140041.17" + attribute \src "libresoc.v:140403.9-140403.17" case 1'1 case end @@ -224136,35 +223625,35 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $1\io_sr$next[151:0]$6126 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__o \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + assign $1\io_sr$next[129:0]$6058 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__o \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $1\io_sr$next[151:0]$6126 { \io_sr [150:0] \TAP_bus__tdi } + assign $1\io_sr$next[129:0]$6058 { \io_sr [128:0] \TAP_bus__tdi } case - assign $1\io_sr$next[151:0]$6126 \io_sr + assign $1\io_sr$next[129:0]$6058 \io_sr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_sr$next[151:0]$6127 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $2\io_sr$next[129:0]$6059 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $2\io_sr$next[151:0]$6127 $1\io_sr$next[151:0]$6126 + assign $2\io_sr$next[129:0]$6059 $1\io_sr$next[129:0]$6058 end sync always - update \io_sr$next $0\io_sr$next[151:0]$6125 + update \io_sr$next $0\io_sr$next[129:0]$6057 end - attribute \src "libresoc.v:140058.3-140078.6" - process $proc$libresoc.v:140058$6128 + attribute \src "libresoc.v:140420.3-140440.6" + process $proc$libresoc.v:140420$6060 assign { } { } assign { } { } assign { } { } - assign $0\io_bd$next[151:0]$6129 $2\io_bd$next[151:0]$6131 - attribute \src "libresoc.v:140059.5-140059.29" + assign $0\io_bd$next[129:0]$6061 $2\io_bd$next[129:0]$6063 + attribute \src "libresoc.v:140421.5-140421.29" switch \initial - attribute \src "libresoc.v:140059.9-140059.17" + attribute \src "libresoc.v:140421.9-140421.17" case 1'1 case end @@ -224172,424 +223661,380 @@ module \jtag switch { \io_update \io_shift \io_capture } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $1\io_bd$next[151:0]$6130 \io_bd + assign $1\io_bd$next[129:0]$6062 \io_bd attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $1\io_bd$next[151:0]$6130 \io_bd + assign $1\io_bd$next[129:0]$6062 \io_bd attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $1\io_bd$next[151:0]$6130 \io_sr + assign $1\io_bd$next[129:0]$6062 \io_sr case - assign $1\io_bd$next[151:0]$6130 \io_bd + assign $1\io_bd$next[129:0]$6062 \io_bd end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \negjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_bd$next[151:0]$6131 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\io_bd$next[151:0]$6131 $1\io_bd$next[151:0]$6130 - end - sync always - update \io_bd$next $0\io_bd$next[151:0]$6129 - end - connect \$9 $eq$libresoc.v:138999$5682_Y - connect \$99 $ternary$libresoc.v:139000$5683_Y - connect \$101 $ternary$libresoc.v:139001$5684_Y - connect \$103 $ternary$libresoc.v:139002$5685_Y - connect \$105 $ternary$libresoc.v:139003$5686_Y - connect \$107 $ternary$libresoc.v:139004$5687_Y - connect \$109 $ternary$libresoc.v:139005$5688_Y - connect \$111 $ternary$libresoc.v:139006$5689_Y - connect \$113 $ternary$libresoc.v:139007$5690_Y - connect \$115 $ternary$libresoc.v:139008$5691_Y - connect \$117 $ternary$libresoc.v:139009$5692_Y - connect \$11 $eq$libresoc.v:139010$5693_Y - connect \$119 $ternary$libresoc.v:139011$5694_Y - connect \$121 $ternary$libresoc.v:139012$5695_Y - connect \$123 $ternary$libresoc.v:139013$5696_Y - connect \$125 $ternary$libresoc.v:139014$5697_Y - connect \$127 $ternary$libresoc.v:139015$5698_Y - connect \$129 $ternary$libresoc.v:139016$5699_Y - connect \$131 $ternary$libresoc.v:139017$5700_Y - connect \$133 $ternary$libresoc.v:139018$5701_Y - connect \$135 $ternary$libresoc.v:139019$5702_Y - connect \$137 $ternary$libresoc.v:139020$5703_Y - connect \$13 $eq$libresoc.v:139021$5704_Y - connect \$139 $ternary$libresoc.v:139022$5705_Y - connect \$141 $ternary$libresoc.v:139023$5706_Y - connect \$143 $ternary$libresoc.v:139024$5707_Y - connect \$145 $ternary$libresoc.v:139025$5708_Y - connect \$147 $ternary$libresoc.v:139026$5709_Y - connect \$149 $ternary$libresoc.v:139027$5710_Y - connect \$151 $ternary$libresoc.v:139028$5711_Y - connect \$153 $ternary$libresoc.v:139029$5712_Y - connect \$155 $ternary$libresoc.v:139030$5713_Y - connect \$157 $ternary$libresoc.v:139031$5714_Y - connect \$15 $or$libresoc.v:139032$5715_Y - connect \$159 $ternary$libresoc.v:139033$5716_Y - connect \$161 $ternary$libresoc.v:139034$5717_Y - connect \$163 $ternary$libresoc.v:139035$5718_Y - connect \$165 $ternary$libresoc.v:139036$5719_Y - connect \$167 $ternary$libresoc.v:139037$5720_Y - connect \$169 $ternary$libresoc.v:139038$5721_Y - connect \$171 $ternary$libresoc.v:139039$5722_Y - connect \$173 $ternary$libresoc.v:139040$5723_Y - connect \$175 $ternary$libresoc.v:139041$5724_Y - connect \$177 $ternary$libresoc.v:139042$5725_Y - connect \$17 $and$libresoc.v:139043$5726_Y - connect \$179 $ternary$libresoc.v:139044$5727_Y - connect \$181 $ternary$libresoc.v:139045$5728_Y - connect \$183 $ternary$libresoc.v:139046$5729_Y - connect \$185 $ternary$libresoc.v:139047$5730_Y - connect \$187 $ternary$libresoc.v:139048$5731_Y - connect \$189 $ternary$libresoc.v:139049$5732_Y - connect \$191 $ternary$libresoc.v:139050$5733_Y - connect \$193 $ternary$libresoc.v:139051$5734_Y - connect \$195 $ternary$libresoc.v:139052$5735_Y - connect \$197 $ternary$libresoc.v:139053$5736_Y - connect \$1 $eq$libresoc.v:139054$5737_Y - connect \$19 $eq$libresoc.v:139055$5738_Y - connect \$199 $ternary$libresoc.v:139056$5739_Y - connect \$201 $ternary$libresoc.v:139057$5740_Y - connect \$203 $ternary$libresoc.v:139058$5741_Y - connect \$205 $ternary$libresoc.v:139059$5742_Y - connect \$207 $ternary$libresoc.v:139060$5743_Y - connect \$209 $ternary$libresoc.v:139061$5744_Y - connect \$211 $ternary$libresoc.v:139062$5745_Y - connect \$213 $ternary$libresoc.v:139063$5746_Y - connect \$215 $ternary$libresoc.v:139064$5747_Y - connect \$217 $ternary$libresoc.v:139065$5748_Y - connect \$21 $eq$libresoc.v:139066$5749_Y - connect \$219 $ternary$libresoc.v:139067$5750_Y - connect \$221 $ternary$libresoc.v:139068$5751_Y - connect \$223 $ternary$libresoc.v:139069$5752_Y - connect \$225 $ternary$libresoc.v:139070$5753_Y - connect \$227 $ternary$libresoc.v:139071$5754_Y - connect \$229 $ternary$libresoc.v:139072$5755_Y - connect \$231 $ternary$libresoc.v:139073$5756_Y - connect \$233 $ternary$libresoc.v:139074$5757_Y - connect \$235 $ternary$libresoc.v:139075$5758_Y - connect \$237 $ternary$libresoc.v:139076$5759_Y - connect \$23 $or$libresoc.v:139077$5760_Y - connect \$239 $ternary$libresoc.v:139078$5761_Y - connect \$241 $ternary$libresoc.v:139079$5762_Y - connect \$243 $ternary$libresoc.v:139080$5763_Y - connect \$245 $ternary$libresoc.v:139081$5764_Y - connect \$247 $ternary$libresoc.v:139082$5765_Y - connect \$249 $ternary$libresoc.v:139083$5766_Y - connect \$251 $ternary$libresoc.v:139084$5767_Y - connect \$253 $ternary$libresoc.v:139085$5768_Y - connect \$255 $ternary$libresoc.v:139086$5769_Y - connect \$257 $ternary$libresoc.v:139087$5770_Y - connect \$25 $eq$libresoc.v:139088$5771_Y - connect \$259 $ternary$libresoc.v:139089$5772_Y - connect \$261 $ternary$libresoc.v:139090$5773_Y - connect \$263 $ternary$libresoc.v:139091$5774_Y - connect \$265 $ternary$libresoc.v:139092$5775_Y - connect \$267 $ternary$libresoc.v:139093$5776_Y - connect \$269 $ternary$libresoc.v:139094$5777_Y - connect \$271 $ternary$libresoc.v:139095$5778_Y - connect \$273 $ternary$libresoc.v:139096$5779_Y - connect \$275 $ternary$libresoc.v:139097$5780_Y - connect \$277 $ternary$libresoc.v:139098$5781_Y - connect \$27 $or$libresoc.v:139099$5782_Y - connect \$279 $ternary$libresoc.v:139100$5783_Y - connect \$281 $ternary$libresoc.v:139101$5784_Y - connect \$283 $ternary$libresoc.v:139102$5785_Y - connect \$285 $ternary$libresoc.v:139103$5786_Y - connect \$287 $ternary$libresoc.v:139104$5787_Y - connect \$289 $ternary$libresoc.v:139105$5788_Y - connect \$291 $ternary$libresoc.v:139106$5789_Y - connect \$293 $ternary$libresoc.v:139107$5790_Y - connect \$295 $ternary$libresoc.v:139108$5791_Y - connect \$297 $ternary$libresoc.v:139109$5792_Y - connect \$29 $and$libresoc.v:139110$5793_Y - connect \$299 $ternary$libresoc.v:139111$5794_Y - connect \$301 $ternary$libresoc.v:139112$5795_Y - connect \$303 $ternary$libresoc.v:139113$5796_Y - connect \$305 $ternary$libresoc.v:139114$5797_Y - connect \$307 $ternary$libresoc.v:139115$5798_Y - connect \$309 $ternary$libresoc.v:139116$5799_Y - connect \$311 $ternary$libresoc.v:139117$5800_Y - connect \$313 $ternary$libresoc.v:139118$5801_Y - connect \$315 $ternary$libresoc.v:139119$5802_Y - connect \$317 $ternary$libresoc.v:139120$5803_Y - connect \$31 $and$libresoc.v:139121$5804_Y - connect \$319 $ternary$libresoc.v:139122$5805_Y - connect \$321 $ternary$libresoc.v:139123$5806_Y - connect \$323 $ternary$libresoc.v:139124$5807_Y - connect \$325 $ternary$libresoc.v:139125$5808_Y - connect \$327 $ternary$libresoc.v:139126$5809_Y - connect \$329 $ternary$libresoc.v:139127$5810_Y - connect \$331 $ternary$libresoc.v:139128$5811_Y - connect \$333 $ternary$libresoc.v:139129$5812_Y - connect \$335 $ternary$libresoc.v:139130$5813_Y - connect \$337 $ternary$libresoc.v:139131$5814_Y - connect \$33 $eq$libresoc.v:139132$5815_Y - connect \$339 $ternary$libresoc.v:139133$5816_Y - connect \$341 $ternary$libresoc.v:139134$5817_Y - connect \$343 $ternary$libresoc.v:139135$5818_Y - connect \$345 $ternary$libresoc.v:139136$5819_Y - connect \$347 $ternary$libresoc.v:139137$5820_Y - connect \$349 $ternary$libresoc.v:139138$5821_Y - connect \$351 $ternary$libresoc.v:139139$5822_Y - connect \$353 $ternary$libresoc.v:139140$5823_Y - connect \$355 $eq$libresoc.v:139141$5824_Y - connect \$357 $eq$libresoc.v:139142$5825_Y - connect \$35 $eq$libresoc.v:139143$5826_Y - connect \$359 $or$libresoc.v:139144$5827_Y - connect \$361 $eq$libresoc.v:139145$5828_Y - connect \$363 $or$libresoc.v:139146$5829_Y - connect \$365 $and$libresoc.v:139147$5830_Y - connect \$367 $eq$libresoc.v:139148$5831_Y - connect \$369 $ne$libresoc.v:139149$5832_Y - connect \$371 $and$libresoc.v:139150$5833_Y - connect \$373 $ne$libresoc.v:139151$5834_Y - connect \$375 $and$libresoc.v:139152$5835_Y - connect \$377 $ne$libresoc.v:139153$5836_Y - connect \$37 $or$libresoc.v:139154$5837_Y - connect \$379 $and$libresoc.v:139155$5838_Y - connect \$381 $not$libresoc.v:139156$5839_Y - connect \$383 $and$libresoc.v:139157$5840_Y - connect \$385 $eq$libresoc.v:139158$5841_Y - connect \$387 $ne$libresoc.v:139159$5842_Y - connect \$389 $and$libresoc.v:139160$5843_Y - connect \$391 $ne$libresoc.v:139161$5844_Y - connect \$393 $and$libresoc.v:139162$5845_Y - connect \$395 $ne$libresoc.v:139163$5846_Y - connect \$397 $and$libresoc.v:139164$5847_Y - connect \$3 $eq$libresoc.v:139165$5848_Y - connect \$39 $eq$libresoc.v:139166$5849_Y - connect \$399 $not$libresoc.v:139167$5850_Y - connect \$401 $and$libresoc.v:139168$5851_Y - connect \$403 $eq$libresoc.v:139169$5852_Y - connect \$405 $eq$libresoc.v:139170$5853_Y - connect \$407 $ne$libresoc.v:139171$5854_Y - connect \$409 $and$libresoc.v:139172$5855_Y - connect \$411 $ne$libresoc.v:139173$5856_Y - connect \$413 $and$libresoc.v:139174$5857_Y - connect \$415 $ne$libresoc.v:139175$5858_Y - connect \$417 $and$libresoc.v:139176$5859_Y - connect \$41 $or$libresoc.v:139177$5860_Y - connect \$419 $not$libresoc.v:139178$5861_Y - connect \$421 $and$libresoc.v:139179$5862_Y - connect \$423 $eq$libresoc.v:139180$5863_Y - connect \$425 $ne$libresoc.v:139181$5864_Y - connect \$427 $and$libresoc.v:139182$5865_Y - connect \$429 $ne$libresoc.v:139183$5866_Y - connect \$431 $and$libresoc.v:139184$5867_Y - connect \$433 $ne$libresoc.v:139185$5868_Y - connect \$435 $and$libresoc.v:139186$5869_Y - connect \$437 $not$libresoc.v:139187$5870_Y - connect \$43 $and$libresoc.v:139188$5871_Y - connect \$439 $and$libresoc.v:139189$5872_Y - connect \$441 $eq$libresoc.v:139190$5873_Y - connect \$443 $eq$libresoc.v:139191$5874_Y - connect \$445 $ne$libresoc.v:139192$5875_Y - connect \$447 $and$libresoc.v:139193$5876_Y - connect \$449 $ne$libresoc.v:139194$5877_Y - connect \$451 $and$libresoc.v:139195$5878_Y - connect \$453 $ne$libresoc.v:139196$5879_Y - connect \$455 $and$libresoc.v:139197$5880_Y - connect \$457 $not$libresoc.v:139198$5881_Y - connect \$45 $and$libresoc.v:139199$5882_Y - connect \$459 $and$libresoc.v:139200$5883_Y - connect \$461 $eq$libresoc.v:139201$5884_Y - connect \$463 $ne$libresoc.v:139202$5885_Y - connect \$465 $and$libresoc.v:139203$5886_Y - connect \$467 $ne$libresoc.v:139204$5887_Y - connect \$469 $and$libresoc.v:139205$5888_Y - connect \$471 $ne$libresoc.v:139206$5889_Y - connect \$473 $and$libresoc.v:139207$5890_Y - connect \$475 $not$libresoc.v:139208$5891_Y - connect \$477 $and$libresoc.v:139209$5892_Y - connect \$47 $eq$libresoc.v:139210$5893_Y - connect \$480 $eq$libresoc.v:139211$5894_Y - connect \$479 $not$libresoc.v:139212$5895_Y - connect \$483 $eq$libresoc.v:139213$5896_Y - connect \$485 $eq$libresoc.v:139214$5897_Y - connect \$487 $or$libresoc.v:139215$5898_Y - connect \$489 $eq$libresoc.v:139216$5899_Y - connect \$492 $add$libresoc.v:139217$5900_Y - connect \$495 $add$libresoc.v:139218$5901_Y - connect \$497 $pos$libresoc.v:139219$5903_Y - connect \$49 $eq$libresoc.v:139220$5904_Y - connect \$500 $eq$libresoc.v:139221$5905_Y - connect \$502 $eq$libresoc.v:139222$5906_Y - connect \$504 $or$libresoc.v:139223$5907_Y - connect \$506 $eq$libresoc.v:139224$5908_Y - connect \$509 $add$libresoc.v:139225$5909_Y - connect \$512 $add$libresoc.v:139226$5910_Y - connect \$51 $ternary$libresoc.v:139227$5911_Y - connect \$53 $ternary$libresoc.v:139228$5912_Y - connect \$55 $ternary$libresoc.v:139229$5913_Y - connect \$57 $ternary$libresoc.v:139230$5914_Y - connect \$5 $or$libresoc.v:139231$5915_Y - connect \$59 $ternary$libresoc.v:139232$5916_Y - connect \$61 $ternary$libresoc.v:139233$5917_Y - connect \$63 $ternary$libresoc.v:139234$5918_Y - connect \$65 $ternary$libresoc.v:139235$5919_Y - connect \$67 $ternary$libresoc.v:139236$5920_Y - connect \$69 $ternary$libresoc.v:139237$5921_Y - connect \$71 $ternary$libresoc.v:139238$5922_Y - connect \$73 $ternary$libresoc.v:139239$5923_Y - connect \$75 $ternary$libresoc.v:139240$5924_Y - connect \$77 $ternary$libresoc.v:139241$5925_Y - connect \$7 $and$libresoc.v:139242$5926_Y - connect \$79 $ternary$libresoc.v:139243$5927_Y - connect \$81 $ternary$libresoc.v:139244$5928_Y - connect \$83 $ternary$libresoc.v:139245$5929_Y - connect \$85 $ternary$libresoc.v:139246$5930_Y - connect \$87 $ternary$libresoc.v:139247$5931_Y - connect \$89 $ternary$libresoc.v:139248$5932_Y - connect \$91 $ternary$libresoc.v:139249$5933_Y - connect \$93 $ternary$libresoc.v:139250$5934_Y - connect \$95 $ternary$libresoc.v:139251$5935_Y - connect \$97 $ternary$libresoc.v:139252$5936_Y - connect \$491 \$492 - connect \$494 \$495 - connect \$508 \$509 - connect \$511 \$512 + assign $2\io_bd$next[129:0]$6063 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[129:0]$6063 $1\io_bd$next[129:0]$6062 + end + sync always + update \io_bd$next $0\io_bd$next[129:0]$6061 + end + connect \$9 $eq$libresoc.v:139343$5636_Y + connect \$99 $ternary$libresoc.v:139344$5637_Y + connect \$101 $ternary$libresoc.v:139345$5638_Y + connect \$103 $ternary$libresoc.v:139346$5639_Y + connect \$105 $ternary$libresoc.v:139347$5640_Y + connect \$107 $ternary$libresoc.v:139348$5641_Y + connect \$109 $ternary$libresoc.v:139349$5642_Y + connect \$111 $ternary$libresoc.v:139350$5643_Y + connect \$113 $ternary$libresoc.v:139351$5644_Y + connect \$115 $ternary$libresoc.v:139352$5645_Y + connect \$117 $ternary$libresoc.v:139353$5646_Y + connect \$11 $eq$libresoc.v:139354$5647_Y + connect \$119 $ternary$libresoc.v:139355$5648_Y + connect \$121 $ternary$libresoc.v:139356$5649_Y + connect \$123 $ternary$libresoc.v:139357$5650_Y + connect \$125 $ternary$libresoc.v:139358$5651_Y + connect \$127 $ternary$libresoc.v:139359$5652_Y + connect \$129 $ternary$libresoc.v:139360$5653_Y + connect \$131 $ternary$libresoc.v:139361$5654_Y + connect \$133 $ternary$libresoc.v:139362$5655_Y + connect \$135 $ternary$libresoc.v:139363$5656_Y + connect \$137 $ternary$libresoc.v:139364$5657_Y + connect \$13 $eq$libresoc.v:139365$5658_Y + connect \$139 $ternary$libresoc.v:139366$5659_Y + connect \$141 $ternary$libresoc.v:139367$5660_Y + connect \$143 $ternary$libresoc.v:139368$5661_Y + connect \$145 $ternary$libresoc.v:139369$5662_Y + connect \$147 $ternary$libresoc.v:139370$5663_Y + connect \$149 $ternary$libresoc.v:139371$5664_Y + connect \$151 $ternary$libresoc.v:139372$5665_Y + connect \$153 $ternary$libresoc.v:139373$5666_Y + connect \$155 $ternary$libresoc.v:139374$5667_Y + connect \$157 $ternary$libresoc.v:139375$5668_Y + connect \$15 $or$libresoc.v:139376$5669_Y + connect \$159 $ternary$libresoc.v:139377$5670_Y + connect \$161 $ternary$libresoc.v:139378$5671_Y + connect \$163 $ternary$libresoc.v:139379$5672_Y + connect \$165 $ternary$libresoc.v:139380$5673_Y + connect \$167 $ternary$libresoc.v:139381$5674_Y + connect \$169 $ternary$libresoc.v:139382$5675_Y + connect \$171 $ternary$libresoc.v:139383$5676_Y + connect \$173 $ternary$libresoc.v:139384$5677_Y + connect \$175 $ternary$libresoc.v:139385$5678_Y + connect \$177 $ternary$libresoc.v:139386$5679_Y + connect \$17 $and$libresoc.v:139387$5680_Y + connect \$179 $ternary$libresoc.v:139388$5681_Y + connect \$181 $ternary$libresoc.v:139389$5682_Y + connect \$183 $ternary$libresoc.v:139390$5683_Y + connect \$185 $ternary$libresoc.v:139391$5684_Y + connect \$187 $ternary$libresoc.v:139392$5685_Y + connect \$189 $ternary$libresoc.v:139393$5686_Y + connect \$191 $ternary$libresoc.v:139394$5687_Y + connect \$193 $ternary$libresoc.v:139395$5688_Y + connect \$195 $ternary$libresoc.v:139396$5689_Y + connect \$197 $ternary$libresoc.v:139397$5690_Y + connect \$1 $eq$libresoc.v:139398$5691_Y + connect \$19 $eq$libresoc.v:139399$5692_Y + connect \$199 $ternary$libresoc.v:139400$5693_Y + connect \$201 $ternary$libresoc.v:139401$5694_Y + connect \$203 $ternary$libresoc.v:139402$5695_Y + connect \$205 $ternary$libresoc.v:139403$5696_Y + connect \$207 $ternary$libresoc.v:139404$5697_Y + connect \$209 $ternary$libresoc.v:139405$5698_Y + connect \$211 $ternary$libresoc.v:139406$5699_Y + connect \$213 $ternary$libresoc.v:139407$5700_Y + connect \$215 $ternary$libresoc.v:139408$5701_Y + connect \$217 $ternary$libresoc.v:139409$5702_Y + connect \$21 $eq$libresoc.v:139410$5703_Y + connect \$219 $ternary$libresoc.v:139411$5704_Y + connect \$221 $ternary$libresoc.v:139412$5705_Y + connect \$223 $ternary$libresoc.v:139413$5706_Y + connect \$225 $ternary$libresoc.v:139414$5707_Y + connect \$227 $ternary$libresoc.v:139415$5708_Y + connect \$229 $ternary$libresoc.v:139416$5709_Y + connect \$231 $ternary$libresoc.v:139417$5710_Y + connect \$233 $ternary$libresoc.v:139418$5711_Y + connect \$235 $ternary$libresoc.v:139419$5712_Y + connect \$237 $ternary$libresoc.v:139420$5713_Y + connect \$23 $or$libresoc.v:139421$5714_Y + connect \$239 $ternary$libresoc.v:139422$5715_Y + connect \$241 $ternary$libresoc.v:139423$5716_Y + connect \$243 $ternary$libresoc.v:139424$5717_Y + connect \$245 $ternary$libresoc.v:139425$5718_Y + connect \$247 $ternary$libresoc.v:139426$5719_Y + connect \$249 $ternary$libresoc.v:139427$5720_Y + connect \$251 $ternary$libresoc.v:139428$5721_Y + connect \$253 $ternary$libresoc.v:139429$5722_Y + connect \$255 $ternary$libresoc.v:139430$5723_Y + connect \$257 $ternary$libresoc.v:139431$5724_Y + connect \$25 $eq$libresoc.v:139432$5725_Y + connect \$259 $ternary$libresoc.v:139433$5726_Y + connect \$261 $ternary$libresoc.v:139434$5727_Y + connect \$263 $ternary$libresoc.v:139435$5728_Y + connect \$265 $ternary$libresoc.v:139436$5729_Y + connect \$267 $ternary$libresoc.v:139437$5730_Y + connect \$269 $ternary$libresoc.v:139438$5731_Y + connect \$271 $ternary$libresoc.v:139439$5732_Y + connect \$273 $ternary$libresoc.v:139440$5733_Y + connect \$275 $ternary$libresoc.v:139441$5734_Y + connect \$277 $ternary$libresoc.v:139442$5735_Y + connect \$27 $or$libresoc.v:139443$5736_Y + connect \$279 $ternary$libresoc.v:139444$5737_Y + connect \$281 $ternary$libresoc.v:139445$5738_Y + connect \$283 $ternary$libresoc.v:139446$5739_Y + connect \$285 $ternary$libresoc.v:139447$5740_Y + connect \$287 $ternary$libresoc.v:139448$5741_Y + connect \$289 $ternary$libresoc.v:139449$5742_Y + connect \$291 $ternary$libresoc.v:139450$5743_Y + connect \$293 $ternary$libresoc.v:139451$5744_Y + connect \$295 $ternary$libresoc.v:139452$5745_Y + connect \$297 $ternary$libresoc.v:139453$5746_Y + connect \$29 $and$libresoc.v:139454$5747_Y + connect \$299 $ternary$libresoc.v:139455$5748_Y + connect \$301 $ternary$libresoc.v:139456$5749_Y + connect \$303 $ternary$libresoc.v:139457$5750_Y + connect \$305 $ternary$libresoc.v:139458$5751_Y + connect \$307 $ternary$libresoc.v:139459$5752_Y + connect \$309 $ternary$libresoc.v:139460$5753_Y + connect \$311 $eq$libresoc.v:139461$5754_Y + connect \$313 $eq$libresoc.v:139462$5755_Y + connect \$315 $or$libresoc.v:139463$5756_Y + connect \$317 $eq$libresoc.v:139464$5757_Y + connect \$31 $and$libresoc.v:139465$5758_Y + connect \$319 $or$libresoc.v:139466$5759_Y + connect \$321 $and$libresoc.v:139467$5760_Y + connect \$323 $eq$libresoc.v:139468$5761_Y + connect \$325 $ne$libresoc.v:139469$5762_Y + connect \$327 $and$libresoc.v:139470$5763_Y + connect \$329 $ne$libresoc.v:139471$5764_Y + connect \$331 $and$libresoc.v:139472$5765_Y + connect \$333 $ne$libresoc.v:139473$5766_Y + connect \$335 $and$libresoc.v:139474$5767_Y + connect \$337 $not$libresoc.v:139475$5768_Y + connect \$33 $eq$libresoc.v:139476$5769_Y + connect \$339 $and$libresoc.v:139477$5770_Y + connect \$341 $eq$libresoc.v:139478$5771_Y + connect \$343 $ne$libresoc.v:139479$5772_Y + connect \$345 $and$libresoc.v:139480$5773_Y + connect \$347 $ne$libresoc.v:139481$5774_Y + connect \$349 $and$libresoc.v:139482$5775_Y + connect \$351 $ne$libresoc.v:139483$5776_Y + connect \$353 $and$libresoc.v:139484$5777_Y + connect \$355 $not$libresoc.v:139485$5778_Y + connect \$357 $and$libresoc.v:139486$5779_Y + connect \$35 $eq$libresoc.v:139487$5780_Y + connect \$359 $eq$libresoc.v:139488$5781_Y + connect \$361 $eq$libresoc.v:139489$5782_Y + connect \$363 $ne$libresoc.v:139490$5783_Y + connect \$365 $and$libresoc.v:139491$5784_Y + connect \$367 $ne$libresoc.v:139492$5785_Y + connect \$369 $and$libresoc.v:139493$5786_Y + connect \$371 $ne$libresoc.v:139494$5787_Y + connect \$373 $and$libresoc.v:139495$5788_Y + connect \$375 $not$libresoc.v:139496$5789_Y + connect \$377 $and$libresoc.v:139497$5790_Y + connect \$37 $or$libresoc.v:139498$5791_Y + connect \$379 $eq$libresoc.v:139499$5792_Y + connect \$381 $ne$libresoc.v:139500$5793_Y + connect \$383 $and$libresoc.v:139501$5794_Y + connect \$385 $ne$libresoc.v:139502$5795_Y + connect \$387 $and$libresoc.v:139503$5796_Y + connect \$389 $ne$libresoc.v:139504$5797_Y + connect \$391 $and$libresoc.v:139505$5798_Y + connect \$393 $not$libresoc.v:139506$5799_Y + connect \$395 $and$libresoc.v:139507$5800_Y + connect \$397 $eq$libresoc.v:139508$5801_Y + connect \$3 $eq$libresoc.v:139509$5802_Y + connect \$39 $eq$libresoc.v:139510$5803_Y + connect \$399 $eq$libresoc.v:139511$5804_Y + connect \$401 $ne$libresoc.v:139512$5805_Y + connect \$403 $and$libresoc.v:139513$5806_Y + connect \$405 $ne$libresoc.v:139514$5807_Y + connect \$407 $and$libresoc.v:139515$5808_Y + connect \$409 $ne$libresoc.v:139516$5809_Y + connect \$411 $and$libresoc.v:139517$5810_Y + connect \$413 $not$libresoc.v:139518$5811_Y + connect \$415 $and$libresoc.v:139519$5812_Y + connect \$417 $eq$libresoc.v:139520$5813_Y + connect \$41 $or$libresoc.v:139521$5814_Y + connect \$419 $ne$libresoc.v:139522$5815_Y + connect \$421 $and$libresoc.v:139523$5816_Y + connect \$423 $ne$libresoc.v:139524$5817_Y + connect \$425 $and$libresoc.v:139525$5818_Y + connect \$427 $ne$libresoc.v:139526$5819_Y + connect \$429 $and$libresoc.v:139527$5820_Y + connect \$431 $not$libresoc.v:139528$5821_Y + connect \$433 $and$libresoc.v:139529$5822_Y + connect \$436 $eq$libresoc.v:139530$5823_Y + connect \$435 $not$libresoc.v:139531$5824_Y + connect \$43 $and$libresoc.v:139532$5825_Y + connect \$439 $eq$libresoc.v:139533$5826_Y + connect \$441 $eq$libresoc.v:139534$5827_Y + connect \$443 $or$libresoc.v:139535$5828_Y + connect \$445 $eq$libresoc.v:139536$5829_Y + connect \$448 $add$libresoc.v:139537$5830_Y + connect \$451 $add$libresoc.v:139538$5831_Y + connect \$453 $pos$libresoc.v:139539$5833_Y + connect \$456 $eq$libresoc.v:139540$5834_Y + connect \$458 $eq$libresoc.v:139541$5835_Y + connect \$45 $and$libresoc.v:139542$5836_Y + connect \$460 $or$libresoc.v:139543$5837_Y + connect \$462 $eq$libresoc.v:139544$5838_Y + connect \$465 $add$libresoc.v:139545$5839_Y + connect \$468 $add$libresoc.v:139546$5840_Y + connect \$47 $eq$libresoc.v:139547$5841_Y + connect \$49 $eq$libresoc.v:139548$5842_Y + connect \$51 $ternary$libresoc.v:139549$5843_Y + connect \$53 $ternary$libresoc.v:139550$5844_Y + connect \$55 $ternary$libresoc.v:139551$5845_Y + connect \$57 $ternary$libresoc.v:139552$5846_Y + connect \$5 $or$libresoc.v:139553$5847_Y + connect \$59 $ternary$libresoc.v:139554$5848_Y + connect \$61 $ternary$libresoc.v:139555$5849_Y + connect \$63 $ternary$libresoc.v:139556$5850_Y + connect \$65 $ternary$libresoc.v:139557$5851_Y + connect \$67 $ternary$libresoc.v:139558$5852_Y + connect \$69 $ternary$libresoc.v:139559$5853_Y + connect \$71 $ternary$libresoc.v:139560$5854_Y + connect \$73 $ternary$libresoc.v:139561$5855_Y + connect \$75 $ternary$libresoc.v:139562$5856_Y + connect \$77 $ternary$libresoc.v:139563$5857_Y + connect \$7 $and$libresoc.v:139564$5858_Y + connect \$79 $ternary$libresoc.v:139565$5859_Y + connect \$81 $ternary$libresoc.v:139566$5860_Y + connect \$83 $ternary$libresoc.v:139567$5861_Y + connect \$85 $ternary$libresoc.v:139568$5862_Y + connect \$87 $ternary$libresoc.v:139569$5863_Y + connect \$89 $ternary$libresoc.v:139570$5864_Y + connect \$91 $ternary$libresoc.v:139571$5865_Y + connect \$93 $ternary$libresoc.v:139572$5866_Y + connect \$95 $ternary$libresoc.v:139573$5867_Y + connect \$97 $ternary$libresoc.v:139574$5868_Y + connect \$447 \$448 + connect \$450 \$451 + connect \$464 \$465 + connect \$467 \$468 connect \sr5__ie 1'0 connect \sr0__i \sr0__o - connect \dmi0__we_i \$506 - connect \dmi0__req_i \$504 - connect \dmi0_addrsr__i \$497 - connect \jtag_wb__we \$489 - connect \jtag_wb__stb \$487 - connect \jtag_wb__cyc \$479 + connect \dmi0__we_i \$462 + connect \dmi0__req_i \$460 + connect \dmi0_addrsr__i \$453 + connect \jtag_wb__we \$445 + connect \jtag_wb__stb \$443 + connect \jtag_wb__cyc \$435 connect \jtag_wb__sel 1'1 connect \jtag_wb_addrsr__i \jtag_wb__adr - connect \sr5_update \$473 - connect \sr5_shift \$469 - connect \sr5_capture \$465 - connect \sr5_isir \$461 + connect \sr5_update \$429 + connect \sr5_shift \$425 + connect \sr5_capture \$421 + connect \sr5_isir \$417 connect \sr5__o \sr5_reg - connect \dmi0_datasr_update \$455 - connect \dmi0_datasr_shift \$451 - connect \dmi0_datasr_capture \$447 - connect \dmi0_datasr_isir { \$443 \$441 } + connect \dmi0_datasr_update \$411 + connect \dmi0_datasr_shift \$407 + connect \dmi0_datasr_capture \$403 + connect \dmi0_datasr_isir { \$399 \$397 } connect \dmi0_datasr__o \dmi0_datasr_reg - connect \dmi0_addrsr_update \$435 - connect \dmi0_addrsr_shift \$431 - connect \dmi0_addrsr_capture \$427 - connect \dmi0_addrsr_isir \$423 + connect \dmi0_addrsr_update \$391 + connect \dmi0_addrsr_shift \$387 + connect \dmi0_addrsr_capture \$383 + connect \dmi0_addrsr_isir \$379 connect \dmi0_addrsr__o \dmi0_addrsr_reg - connect \jtag_wb_datasr_update \$417 - connect \jtag_wb_datasr_shift \$413 - connect \jtag_wb_datasr_capture \$409 - connect \jtag_wb_datasr_isir { \$405 \$403 } + connect \jtag_wb_datasr_update \$373 + connect \jtag_wb_datasr_shift \$369 + connect \jtag_wb_datasr_capture \$365 + connect \jtag_wb_datasr_isir { \$361 \$359 } connect \jtag_wb_datasr__o \jtag_wb_datasr_reg - connect \jtag_wb_addrsr_update \$397 - connect \jtag_wb_addrsr_shift \$393 - connect \jtag_wb_addrsr_capture \$389 - connect \jtag_wb_addrsr_isir \$385 + connect \jtag_wb_addrsr_update \$353 + connect \jtag_wb_addrsr_shift \$349 + connect \jtag_wb_addrsr_capture \$345 + connect \jtag_wb_addrsr_isir \$341 connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg - connect \sr0_update \$379 - connect \sr0_shift \$375 - connect \sr0_capture \$371 - connect \sr0_isir \$367 + connect \sr0_update \$335 + connect \sr0_shift \$331 + connect \sr0_capture \$327 + connect \sr0_isir \$323 connect \sr0__o \sr0_reg - connect \sdr_dq_15__pad__oe \$353 - connect \sdr_dq_15__pad__o \$351 - connect \sdr_dq_15__core__i \$349 - connect \sdr_dq_14__pad__oe \$347 - connect \sdr_dq_14__pad__o \$345 - connect \sdr_dq_14__core__i \$343 - connect \sdr_dq_13__pad__oe \$341 - connect \sdr_dq_13__pad__o \$339 - connect \sdr_dq_13__core__i \$337 - connect \sdr_dq_12__pad__oe \$335 - connect \sdr_dq_12__pad__o \$333 - connect \sdr_dq_12__core__i \$331 - connect \sdr_dq_11__pad__oe \$329 - connect \sdr_dq_11__pad__o \$327 - connect \sdr_dq_11__core__i \$325 - connect \sdr_dq_10__pad__oe \$323 - connect \sdr_dq_10__pad__o \$321 - connect \sdr_dq_10__core__i \$319 - connect \sdr_dq_9__pad__oe \$317 - connect \sdr_dq_9__pad__o \$315 - connect \sdr_dq_9__core__i \$313 - connect \sdr_dq_8__pad__oe \$311 - connect \sdr_dq_8__pad__o \$309 - connect \sdr_dq_8__core__i \$307 - connect \sdr_dm_1__pad__o \$305 - connect \sdr_a_12__pad__o \$303 - connect \sdr_a_11__pad__o \$301 - connect \sdr_a_10__pad__o \$299 - connect \sdr_cs_n__pad__o \$297 - connect \sdr_we_n__pad__o \$295 - connect \sdr_cas_n__pad__o \$293 - connect \sdr_ras_n__pad__o \$291 - connect \sdr_cke__pad__o \$289 - connect \sdr_clock__pad__o \$287 - connect \sdr_ba_1__pad__o \$285 - connect \sdr_ba_0__pad__o \$283 - connect \sdr_a_9__pad__o \$281 - connect \sdr_a_8__pad__o \$279 - connect \sdr_a_7__pad__o \$277 - connect \sdr_a_6__pad__o \$275 - connect \sdr_a_5__pad__o \$273 - connect \sdr_a_4__pad__o \$271 - connect \sdr_a_3__pad__o \$269 - connect \sdr_a_2__pad__o \$267 - connect \sdr_a_1__pad__o \$265 - connect \sdr_a_0__pad__o \$263 - connect \sdr_dq_7__pad__oe \$261 - connect \sdr_dq_7__pad__o \$259 - connect \sdr_dq_7__core__i \$257 - connect \sdr_dq_6__pad__oe \$255 - connect \sdr_dq_6__pad__o \$253 - connect \sdr_dq_6__core__i \$251 - connect \sdr_dq_5__pad__oe \$249 - connect \sdr_dq_5__pad__o \$247 - connect \sdr_dq_5__core__i \$245 - connect \sdr_dq_4__pad__oe \$243 - connect \sdr_dq_4__pad__o \$241 - connect \sdr_dq_4__core__i \$239 - connect \sdr_dq_3__pad__oe \$237 - connect \sdr_dq_3__pad__o \$235 - connect \sdr_dq_3__core__i \$233 - connect \sdr_dq_2__pad__oe \$231 - connect \sdr_dq_2__pad__o \$229 - connect \sdr_dq_2__core__i \$227 - connect \sdr_dq_1__pad__oe \$225 - connect \sdr_dq_1__pad__o \$223 - connect \sdr_dq_1__core__i \$221 - connect \sdr_dq_0__pad__oe \$219 - connect \sdr_dq_0__pad__o \$217 - connect \sdr_dq_0__core__i \$215 - connect \sdr_dm_0__pad__o \$213 - connect \sd0_data3__pad__oe \$211 - connect \sd0_data3__pad__o \$209 - connect \sd0_data3__core__i \$207 - connect \sd0_data2__pad__oe \$205 - connect \sd0_data2__pad__o \$203 - connect \sd0_data2__core__i \$201 - connect \sd0_data1__pad__oe \$199 - connect \sd0_data1__pad__o \$197 - connect \sd0_data1__core__i \$195 - connect \sd0_data0__pad__oe \$193 - connect \sd0_data0__pad__o \$191 - connect \sd0_data0__core__i \$189 - connect \sd0_clk__pad__o \$187 - connect \sd0_cmd__pad__oe \$185 - connect \sd0_cmd__pad__o \$183 - connect \sd0_cmd__core__i \$181 - connect \pwm_1__pad__o \$179 - connect \pwm_0__pad__o \$177 - connect \mtwi_scl__pad__o \$175 - connect \mtwi_sda__pad__oe \$173 - connect \mtwi_sda__pad__o \$171 - connect \mtwi_sda__core__i \$169 - connect \mspi1_miso__core__i \$167 - connect \mspi1_mosi__pad__o \$165 - connect \mspi1_cs_n__pad__o \$163 - connect \mspi1_clk__pad__o \$161 + connect \sdr_dq_15__pad__oe \$309 + connect \sdr_dq_15__pad__o \$307 + connect \sdr_dq_15__core__i \$305 + connect \sdr_dq_14__pad__oe \$303 + connect \sdr_dq_14__pad__o \$301 + connect \sdr_dq_14__core__i \$299 + connect \sdr_dq_13__pad__oe \$297 + connect \sdr_dq_13__pad__o \$295 + connect \sdr_dq_13__core__i \$293 + connect \sdr_dq_12__pad__oe \$291 + connect \sdr_dq_12__pad__o \$289 + connect \sdr_dq_12__core__i \$287 + connect \sdr_dq_11__pad__oe \$285 + connect \sdr_dq_11__pad__o \$283 + connect \sdr_dq_11__core__i \$281 + connect \sdr_dq_10__pad__oe \$279 + connect \sdr_dq_10__pad__o \$277 + connect \sdr_dq_10__core__i \$275 + connect \sdr_dq_9__pad__oe \$273 + connect \sdr_dq_9__pad__o \$271 + connect \sdr_dq_9__core__i \$269 + connect \sdr_dq_8__pad__oe \$267 + connect \sdr_dq_8__pad__o \$265 + connect \sdr_dq_8__core__i \$263 + connect \sdr_dm_1__pad__o \$261 + connect \sdr_a_12__pad__o \$259 + connect \sdr_a_11__pad__o \$257 + connect \sdr_a_10__pad__o \$255 + connect \sdr_cs_n__pad__o \$253 + connect \sdr_we_n__pad__o \$251 + connect \sdr_cas_n__pad__o \$249 + connect \sdr_ras_n__pad__o \$247 + connect \sdr_cke__pad__o \$245 + connect \sdr_clock__pad__o \$243 + connect \sdr_ba_1__pad__o \$241 + connect \sdr_ba_0__pad__o \$239 + connect \sdr_a_9__pad__o \$237 + connect \sdr_a_8__pad__o \$235 + connect \sdr_a_7__pad__o \$233 + connect \sdr_a_6__pad__o \$231 + connect \sdr_a_5__pad__o \$229 + connect \sdr_a_4__pad__o \$227 + connect \sdr_a_3__pad__o \$225 + connect \sdr_a_2__pad__o \$223 + connect \sdr_a_1__pad__o \$221 + connect \sdr_a_0__pad__o \$219 + connect \sdr_dq_7__pad__oe \$217 + connect \sdr_dq_7__pad__o \$215 + connect \sdr_dq_7__core__i \$213 + connect \sdr_dq_6__pad__oe \$211 + connect \sdr_dq_6__pad__o \$209 + connect \sdr_dq_6__core__i \$207 + connect \sdr_dq_5__pad__oe \$205 + connect \sdr_dq_5__pad__o \$203 + connect \sdr_dq_5__core__i \$201 + connect \sdr_dq_4__pad__oe \$199 + connect \sdr_dq_4__pad__o \$197 + connect \sdr_dq_4__core__i \$195 + connect \sdr_dq_3__pad__oe \$193 + connect \sdr_dq_3__pad__o \$191 + connect \sdr_dq_3__core__i \$189 + connect \sdr_dq_2__pad__oe \$187 + connect \sdr_dq_2__pad__o \$185 + connect \sdr_dq_2__core__i \$183 + connect \sdr_dq_1__pad__oe \$181 + connect \sdr_dq_1__pad__o \$179 + connect \sdr_dq_1__core__i \$177 + connect \sdr_dq_0__pad__oe \$175 + connect \sdr_dq_0__pad__o \$173 + connect \sdr_dq_0__core__i \$171 + connect \sdr_dm_0__pad__o \$169 + connect \mtwi_scl__pad__o \$167 + connect \mtwi_sda__pad__oe \$165 + connect \mtwi_sda__pad__o \$163 + connect \mtwi_sda__core__i \$161 connect \mspi0_miso__core__i \$159 connect \mspi0_mosi__pad__o \$157 connect \mspi0_cs_n__pad__o \$155 @@ -224653,14 +224098,14 @@ module \jtag connect \_idblock_id_bypass \$9 connect \_idblock_select_id \$7 end -attribute \src "libresoc.v:140286.1-140475.10" +attribute \src "libresoc.v:140626.1-140815.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0" attribute \generator "nMigen" module \l0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 23 \dbus__ack @@ -224680,9 +224125,9 @@ module \l0 wire output 25 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 29 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 96 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 7 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire output 16 \ldst_port0_addr_ok_o @@ -224710,17 +224155,17 @@ module \l0 wire input 3 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire input 4 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 17 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 18 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 19 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 20 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 48 \pimem_ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pimem_ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire \pimem_ldst_port0_addr_ok_o @@ -224734,13 +224179,13 @@ module \l0 wire \pimem_ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire \pimem_ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pimem_ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pimem_ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pimem_ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pimem_ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" wire width 64 \pimem_m_ld_data_o @@ -224763,7 +224208,7 @@ module \l0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 21 \wb_dcache_en attribute \module_not_derived 1 - attribute \src "libresoc.v:140391.12-140425.4" + attribute \src "libresoc.v:140731.12-140765.4" cell \l0$130 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -224800,7 +224245,7 @@ module \l0 connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:140426.9-140448.4" + attribute \src "libresoc.v:140766.9-140788.4" cell \lsmem \lsmem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -224825,7 +224270,7 @@ module \l0 connect \x_valid_i \pimem_x_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:140449.9-140473.4" + attribute \src "libresoc.v:140789.9-140813.4" cell \pimem \pimem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -224853,145 +224298,145 @@ module \l0 end connect \pimem_ldst_port0_exc_$signal 1'0 end -attribute \src "libresoc.v:140479.1-140887.10" +attribute \src "libresoc.v:140819.1-141227.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" attribute \generator "nMigen" module \l0$130 - attribute \src "libresoc.v:140742.3-140756.6" - wire $0\idx_l$23$next[0:0]$6210 - attribute \src "libresoc.v:140642.3-140643.35" - wire $0\idx_l$23[0:0]$6177 - attribute \src "libresoc.v:140500.7-140500.24" - wire $0\idx_l$23[0:0]$6232 - attribute \src "libresoc.v:140797.3-140806.6" + attribute \src "libresoc.v:141082.3-141096.6" + wire $0\idx_l$23$next[0:0]$6142 + attribute \src "libresoc.v:140982.3-140983.35" + wire $0\idx_l$23[0:0]$6109 + attribute \src "libresoc.v:140840.7-140840.24" + wire $0\idx_l$23[0:0]$6164 + attribute \src "libresoc.v:141137.3-141146.6" wire $0\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:140787.3-140796.6" + attribute \src "libresoc.v:141127.3-141136.6" wire $0\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:140480.7-140480.20" + attribute \src "libresoc.v:140820.7-140820.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140663.3-140672.6" - wire width 48 $0\ldst_port0_addr_i$12[47:0]$6179 - attribute \src "libresoc.v:140673.3-140682.6" - wire $0\ldst_port0_addr_i_ok$13[0:0]$6182 - attribute \src "libresoc.v:140715.3-140724.6" + attribute \src "libresoc.v:141003.3-141012.6" + wire width 48 $0\ldst_port0_addr_i$12[47:0]$6111 + attribute \src "libresoc.v:141013.3-141022.6" + wire $0\ldst_port0_addr_i_ok$13[0:0]$6114 + attribute \src "libresoc.v:141055.3-141064.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:140705.3-140714.6" + attribute \src "libresoc.v:141045.3-141054.6" wire $0\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:140777.3-140786.6" + attribute \src "libresoc.v:141117.3-141126.6" wire $0\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:140852.3-140861.6" - wire width 4 $0\ldst_port0_data_len$11[3:0]$6227 - attribute \src "libresoc.v:140725.3-140741.6" - wire $0\ldst_port0_exc_$signal$1[0:0]$6194 - attribute \src "libresoc.v:140725.3-140741.6" - wire $0\ldst_port0_exc_$signal$2[0:0]$6195 - attribute \src "libresoc.v:140725.3-140741.6" - wire $0\ldst_port0_exc_$signal$3[0:0]$6196 - attribute \src "libresoc.v:140725.3-140741.6" - wire $0\ldst_port0_exc_$signal$4[0:0]$6197 - attribute \src "libresoc.v:140725.3-140741.6" - wire $0\ldst_port0_exc_$signal$5[0:0]$6198 - attribute \src "libresoc.v:140725.3-140741.6" - wire $0\ldst_port0_exc_$signal$6[0:0]$6199 - attribute \src "libresoc.v:140725.3-140741.6" - wire $0\ldst_port0_exc_$signal$7[0:0]$6200 - attribute \src "libresoc.v:140725.3-140741.6" - wire $0\ldst_port0_exc_$signal[0:0]$6193 - attribute \src "libresoc.v:140862.3-140871.6" + attribute \src "libresoc.v:141192.3-141201.6" + wire width 4 $0\ldst_port0_data_len$11[3:0]$6159 + attribute \src "libresoc.v:141065.3-141081.6" + wire $0\ldst_port0_exc_$signal$1[0:0]$6126 + attribute \src "libresoc.v:141065.3-141081.6" + wire $0\ldst_port0_exc_$signal$2[0:0]$6127 + attribute \src "libresoc.v:141065.3-141081.6" + wire $0\ldst_port0_exc_$signal$3[0:0]$6128 + attribute \src "libresoc.v:141065.3-141081.6" + wire $0\ldst_port0_exc_$signal$4[0:0]$6129 + attribute \src "libresoc.v:141065.3-141081.6" + wire $0\ldst_port0_exc_$signal$5[0:0]$6130 + attribute \src "libresoc.v:141065.3-141081.6" + wire $0\ldst_port0_exc_$signal$6[0:0]$6131 + attribute \src "libresoc.v:141065.3-141081.6" + wire $0\ldst_port0_exc_$signal$7[0:0]$6132 + attribute \src "libresoc.v:141065.3-141081.6" + wire $0\ldst_port0_exc_$signal[0:0]$6125 + attribute \src "libresoc.v:141202.3-141211.6" wire $0\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:140832.3-140841.6" - wire $0\ldst_port0_is_ld_i$8[0:0]$6221 - attribute \src "libresoc.v:140842.3-140851.6" - wire $0\ldst_port0_is_st_i$9[0:0]$6224 - attribute \src "libresoc.v:140694.3-140704.6" + attribute \src "libresoc.v:141172.3-141181.6" + wire $0\ldst_port0_is_ld_i$8[0:0]$6153 + attribute \src "libresoc.v:141182.3-141191.6" + wire $0\ldst_port0_is_st_i$9[0:0]$6156 + attribute \src "libresoc.v:141034.3-141044.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:140694.3-140704.6" + attribute \src "libresoc.v:141034.3-141044.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:140767.3-140776.6" + attribute \src "libresoc.v:141107.3-141116.6" wire $0\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:140757.3-140766.6" + attribute \src "libresoc.v:141097.3-141106.6" wire $0\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:140683.3-140693.6" - wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6185 - attribute \src "libresoc.v:140683.3-140693.6" - wire $0\ldst_port0_st_data_i_ok$17[0:0]$6186 - attribute \src "libresoc.v:140640.3-140641.36" + attribute \src "libresoc.v:141023.3-141033.6" + wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6117 + attribute \src "libresoc.v:141023.3-141033.6" + wire $0\ldst_port0_st_data_i_ok$17[0:0]$6118 + attribute \src "libresoc.v:140980.3-140981.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:140822.3-140831.6" + attribute \src "libresoc.v:141162.3-141171.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:140807.3-140821.6" + attribute \src "libresoc.v:141147.3-141161.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:140742.3-140756.6" - wire $1\idx_l$23$next[0:0]$6211 - attribute \src "libresoc.v:140797.3-140806.6" + attribute \src "libresoc.v:141082.3-141096.6" + wire $1\idx_l$23$next[0:0]$6143 + attribute \src "libresoc.v:141137.3-141146.6" wire $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:140787.3-140796.6" + attribute \src "libresoc.v:141127.3-141136.6" wire $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:140663.3-140672.6" - wire width 48 $1\ldst_port0_addr_i$12[47:0]$6180 - attribute \src "libresoc.v:140673.3-140682.6" - wire $1\ldst_port0_addr_i_ok$13[0:0]$6183 - attribute \src "libresoc.v:140715.3-140724.6" + attribute \src "libresoc.v:141003.3-141012.6" + wire width 48 $1\ldst_port0_addr_i$12[47:0]$6112 + attribute \src "libresoc.v:141013.3-141022.6" + wire $1\ldst_port0_addr_i_ok$13[0:0]$6115 + attribute \src "libresoc.v:141055.3-141064.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:140705.3-140714.6" + attribute \src "libresoc.v:141045.3-141054.6" wire $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:140777.3-140786.6" + attribute \src "libresoc.v:141117.3-141126.6" wire $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:140852.3-140861.6" - wire width 4 $1\ldst_port0_data_len$11[3:0]$6228 - attribute \src "libresoc.v:140725.3-140741.6" - wire $1\ldst_port0_exc_$signal$1[0:0]$6202 - attribute \src "libresoc.v:140725.3-140741.6" - wire $1\ldst_port0_exc_$signal$2[0:0]$6203 - attribute \src "libresoc.v:140725.3-140741.6" - wire $1\ldst_port0_exc_$signal$3[0:0]$6204 - attribute \src "libresoc.v:140725.3-140741.6" - wire $1\ldst_port0_exc_$signal$4[0:0]$6205 - attribute \src "libresoc.v:140725.3-140741.6" - wire $1\ldst_port0_exc_$signal$5[0:0]$6206 - attribute \src "libresoc.v:140725.3-140741.6" - wire $1\ldst_port0_exc_$signal$6[0:0]$6207 - attribute \src "libresoc.v:140725.3-140741.6" - wire $1\ldst_port0_exc_$signal$7[0:0]$6208 - attribute \src "libresoc.v:140725.3-140741.6" - wire $1\ldst_port0_exc_$signal[0:0]$6201 - attribute \src "libresoc.v:140862.3-140871.6" + attribute \src "libresoc.v:141192.3-141201.6" + wire width 4 $1\ldst_port0_data_len$11[3:0]$6160 + attribute \src "libresoc.v:141065.3-141081.6" + wire $1\ldst_port0_exc_$signal$1[0:0]$6134 + attribute \src "libresoc.v:141065.3-141081.6" + wire $1\ldst_port0_exc_$signal$2[0:0]$6135 + attribute \src "libresoc.v:141065.3-141081.6" + wire $1\ldst_port0_exc_$signal$3[0:0]$6136 + attribute \src "libresoc.v:141065.3-141081.6" + wire $1\ldst_port0_exc_$signal$4[0:0]$6137 + attribute \src "libresoc.v:141065.3-141081.6" + wire $1\ldst_port0_exc_$signal$5[0:0]$6138 + attribute \src "libresoc.v:141065.3-141081.6" + wire $1\ldst_port0_exc_$signal$6[0:0]$6139 + attribute \src "libresoc.v:141065.3-141081.6" + wire $1\ldst_port0_exc_$signal$7[0:0]$6140 + attribute \src "libresoc.v:141065.3-141081.6" + wire $1\ldst_port0_exc_$signal[0:0]$6133 + attribute \src "libresoc.v:141202.3-141211.6" wire $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:140832.3-140841.6" - wire $1\ldst_port0_is_ld_i$8[0:0]$6222 - attribute \src "libresoc.v:140842.3-140851.6" - wire $1\ldst_port0_is_st_i$9[0:0]$6225 - attribute \src "libresoc.v:140694.3-140704.6" + attribute \src "libresoc.v:141172.3-141181.6" + wire $1\ldst_port0_is_ld_i$8[0:0]$6154 + attribute \src "libresoc.v:141182.3-141191.6" + wire $1\ldst_port0_is_st_i$9[0:0]$6157 + attribute \src "libresoc.v:141034.3-141044.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:140694.3-140704.6" + attribute \src "libresoc.v:141034.3-141044.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:140767.3-140776.6" + attribute \src "libresoc.v:141107.3-141116.6" wire $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:140757.3-140766.6" + attribute \src "libresoc.v:141097.3-141106.6" wire $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:140683.3-140693.6" - wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6187 - attribute \src "libresoc.v:140683.3-140693.6" - wire $1\ldst_port0_st_data_i_ok$17[0:0]$6188 - attribute \src "libresoc.v:140627.7-140627.25" + attribute \src "libresoc.v:141023.3-141033.6" + wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6119 + attribute \src "libresoc.v:141023.3-141033.6" + wire $1\ldst_port0_st_data_i_ok$17[0:0]$6120 + attribute \src "libresoc.v:140967.7-140967.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:140822.3-140831.6" + attribute \src "libresoc.v:141162.3-141171.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:140807.3-140821.6" + attribute \src "libresoc.v:141147.3-141161.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:140742.3-140756.6" - wire $2\idx_l$23$next[0:0]$6212 - attribute \src "libresoc.v:140807.3-140821.6" + attribute \src "libresoc.v:141082.3-141096.6" + wire $2\idx_l$23$next[0:0]$6144 + attribute \src "libresoc.v:141147.3-141161.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:140638.18-140638.103" - wire $not$libresoc.v:140638$6173_Y - attribute \src "libresoc.v:140639.18-140639.118" - wire $not$libresoc.v:140639$6174_Y - attribute \src "libresoc.v:140636.18-140636.134" - wire $or$libresoc.v:140636$6171_Y - attribute \src "libresoc.v:140637.18-140637.120" - wire $ternary$libresoc.v:140637$6172_Y + attribute \src "libresoc.v:140978.18-140978.103" + wire $not$libresoc.v:140978$6105_Y + attribute \src "libresoc.v:140979.18-140979.118" + wire $not$libresoc.v:140979$6106_Y + attribute \src "libresoc.v:140976.18-140976.134" + wire $or$libresoc.v:140976$6103_Y + attribute \src "libresoc.v:140977.18-140977.120" + wire $ternary$libresoc.v:140977$6104_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" @@ -225006,9 +224451,9 @@ module \l0$130 wire width 96 \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" wire width 96 \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \idx_l$23 @@ -225020,15 +224465,15 @@ module \l0$130 wire \idx_l_r_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \idx_l_s_idx_l - attribute \src "libresoc.v:140480.7-140480.15" + attribute \src "libresoc.v:140820.7-140820.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 96 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 48 output 25 \ldst_port0_addr_i$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 26 \ldst_port0_addr_i_ok$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire output 16 \ldst_port0_addr_ok_o @@ -225090,13 +224535,13 @@ module \l0$130 wire input 4 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire output 22 \ldst_port0_is_st_i$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 17 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 28 \ldst_port0_ld_data_o$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 18 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 29 \ldst_port0_ld_data_o_ok$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" wire \ldst_port0_ldst_error @@ -225106,13 +224551,13 @@ module \l0$130 wire \ldst_port0_mmu_done attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" wire \ldst_port0_mmu_done$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 19 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 31 \ldst_port0_st_data_i$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 20 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 30 \ldst_port0_st_data_i_ok$17 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" wire \pick_i @@ -225131,23 +224576,23 @@ module \l0$130 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - cell $not $not$libresoc.v:140638$6173 + cell $not $not$libresoc.v:140978$6105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pick_n - connect \Y $not$libresoc.v:140638$6173_Y + connect \Y $not$libresoc.v:140978$6105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - cell $not $not$libresoc.v:140639$6174 + cell $not $not$libresoc.v:140979$6106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o$10 - connect \Y $not$libresoc.v:140639$6174_Y + connect \Y $not$libresoc.v:140979$6106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - cell $or $or$libresoc.v:140636$6171 + cell $or $or$libresoc.v:140976$6103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225155,18 +224600,18 @@ module \l0$130 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:140636$6171_Y + connect \Y $or$libresoc.v:140976$6103_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:140637$6172 + cell $mux $ternary$libresoc.v:140977$6104 parameter \WIDTH 1 connect \A \idx_l$23 connect \B \pick_o connect \S \idx_l_q_idx_l - connect \Y $ternary$libresoc.v:140637$6172_Y + connect \Y $ternary$libresoc.v:140977$6104_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:140644.9-140650.4" + attribute \src "libresoc.v:140984.9-140990.4" cell \idx_l \idx_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225175,14 +224620,14 @@ module \l0$130 connect \s_idx_l \idx_l_s_idx_l end attribute \module_not_derived 1 - attribute \src "libresoc.v:140651.8-140655.4" + attribute \src "libresoc.v:140991.8-140995.4" cell \pick \pick connect \i \pick_i connect \n \pick_n connect \o \pick_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:140656.17-140662.4" + attribute \src "libresoc.v:140996.17-141002.4" cell \reset_l$131 \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225190,52 +224635,52 @@ module \l0$130 connect \r_reset \reset_l_r_reset connect \s_reset \reset_l_s_reset end - attribute \src "libresoc.v:140480.7-140480.20" - process $proc$libresoc.v:140480$6230 + attribute \src "libresoc.v:140820.7-140820.20" + process $proc$libresoc.v:140820$6162 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:140500.7-140500.24" - process $proc$libresoc.v:140500$6231 + attribute \src "libresoc.v:140840.7-140840.24" + process $proc$libresoc.v:140840$6163 assign { } { } - assign $0\idx_l$23[0:0]$6232 1'0 + assign $0\idx_l$23[0:0]$6164 1'0 sync always sync init - update \idx_l$23 $0\idx_l$23[0:0]$6232 + update \idx_l$23 $0\idx_l$23[0:0]$6164 end - attribute \src "libresoc.v:140627.7-140627.25" - process $proc$libresoc.v:140627$6233 + attribute \src "libresoc.v:140967.7-140967.25" + process $proc$libresoc.v:140967$6165 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:140640.3-140641.36" - process $proc$libresoc.v:140640$6175 + attribute \src "libresoc.v:140980.3-140981.36" + process $proc$libresoc.v:140980$6107 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:140642.3-140643.35" - process $proc$libresoc.v:140642$6176 + attribute \src "libresoc.v:140982.3-140983.35" + process $proc$libresoc.v:140982$6108 assign { } { } - assign $0\idx_l$23[0:0]$6177 \idx_l$23$next + assign $0\idx_l$23[0:0]$6109 \idx_l$23$next sync posedge \coresync_clk - update \idx_l$23 $0\idx_l$23[0:0]$6177 + update \idx_l$23 $0\idx_l$23[0:0]$6109 end - attribute \src "libresoc.v:140663.3-140672.6" - process $proc$libresoc.v:140663$6178 + attribute \src "libresoc.v:141003.3-141012.6" + process $proc$libresoc.v:141003$6110 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i$12[47:0]$6179 $1\ldst_port0_addr_i$12[47:0]$6180 - attribute \src "libresoc.v:140664.5-140664.29" + assign $0\ldst_port0_addr_i$12[47:0]$6111 $1\ldst_port0_addr_i$12[47:0]$6112 + attribute \src "libresoc.v:141004.5-141004.29" switch \initial - attribute \src "libresoc.v:140664.9-140664.17" + attribute \src "libresoc.v:141004.9-141004.17" case 1'1 case end @@ -225244,21 +224689,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i$12[47:0]$6180 \$32 [47:0] + assign $1\ldst_port0_addr_i$12[47:0]$6112 \$32 [47:0] case - assign $1\ldst_port0_addr_i$12[47:0]$6180 48'000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_addr_i$12[47:0]$6112 48'000000000000000000000000000000000000000000000000 end sync always - update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6179 + update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6111 end - attribute \src "libresoc.v:140673.3-140682.6" - process $proc$libresoc.v:140673$6181 + attribute \src "libresoc.v:141013.3-141022.6" + process $proc$libresoc.v:141013$6113 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$13[0:0]$6182 $1\ldst_port0_addr_i_ok$13[0:0]$6183 - attribute \src "libresoc.v:140674.5-140674.29" + assign $0\ldst_port0_addr_i_ok$13[0:0]$6114 $1\ldst_port0_addr_i_ok$13[0:0]$6115 + attribute \src "libresoc.v:141014.5-141014.29" switch \initial - attribute \src "libresoc.v:140674.9-140674.17" + attribute \src "libresoc.v:141014.9-141014.17" case 1'1 case end @@ -225267,24 +224712,24 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$13[0:0]$6183 \ldst_port0_addr_i_ok + assign $1\ldst_port0_addr_i_ok$13[0:0]$6115 \ldst_port0_addr_i_ok case - assign $1\ldst_port0_addr_i_ok$13[0:0]$6183 1'0 + assign $1\ldst_port0_addr_i_ok$13[0:0]$6115 1'0 end sync always - update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6182 + update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6114 end - attribute \src "libresoc.v:140683.3-140693.6" - process $proc$libresoc.v:140683$6184 + attribute \src "libresoc.v:141023.3-141033.6" + process $proc$libresoc.v:141023$6116 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_st_data_i$18[63:0]$6185 $1\ldst_port0_st_data_i$18[63:0]$6187 - assign $0\ldst_port0_st_data_i_ok$17[0:0]$6186 $1\ldst_port0_st_data_i_ok$17[0:0]$6188 - attribute \src "libresoc.v:140684.5-140684.29" + assign $0\ldst_port0_st_data_i$18[63:0]$6117 $1\ldst_port0_st_data_i$18[63:0]$6119 + assign $0\ldst_port0_st_data_i_ok$17[0:0]$6118 $1\ldst_port0_st_data_i_ok$17[0:0]$6120 + attribute \src "libresoc.v:141024.5-141024.29" switch \initial - attribute \src "libresoc.v:140684.9-140684.17" + attribute \src "libresoc.v:141024.9-141024.17" case 1'1 case end @@ -225294,26 +224739,26 @@ module \l0$130 case 1'1 assign { } { } assign { } { } - assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6188 $1\ldst_port0_st_data_i$18[63:0]$6187 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } + assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6120 $1\ldst_port0_st_data_i$18[63:0]$6119 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } case - assign $1\ldst_port0_st_data_i$18[63:0]$6187 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\ldst_port0_st_data_i_ok$17[0:0]$6188 1'0 + assign $1\ldst_port0_st_data_i$18[63:0]$6119 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_st_data_i_ok$17[0:0]$6120 1'0 end sync always - update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6185 - update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6186 + update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6117 + update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6118 end - attribute \src "libresoc.v:140694.3-140704.6" - process $proc$libresoc.v:140694$6189 + attribute \src "libresoc.v:141034.3-141044.6" + process $proc$libresoc.v:141034$6121 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:140695.5-140695.29" + attribute \src "libresoc.v:141035.5-141035.29" switch \initial - attribute \src "libresoc.v:140695.9-140695.17" + attribute \src "libresoc.v:141035.9-141035.17" case 1'1 case end @@ -225332,14 +224777,14 @@ module \l0$130 update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:140705.3-140714.6" - process $proc$libresoc.v:140705$6190 + attribute \src "libresoc.v:141045.3-141054.6" + process $proc$libresoc.v:141045$6122 assign { } { } assign { } { } assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:140706.5-140706.29" + attribute \src "libresoc.v:141046.5-141046.29" switch \initial - attribute \src "libresoc.v:140706.9-140706.17" + attribute \src "libresoc.v:141046.9-141046.17" case 1'1 case end @@ -225355,14 +224800,14 @@ module \l0$130 sync always update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] end - attribute \src "libresoc.v:140715.3-140724.6" - process $proc$libresoc.v:140715$6191 + attribute \src "libresoc.v:141055.3-141064.6" + process $proc$libresoc.v:141055$6123 assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:140716.5-140716.29" + attribute \src "libresoc.v:141056.5-141056.29" switch \initial - attribute \src "libresoc.v:140716.9-140716.17" + attribute \src "libresoc.v:141056.9-141056.17" case 1'1 case end @@ -225378,8 +224823,8 @@ module \l0$130 sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:140725.3-140741.6" - process $proc$libresoc.v:140725$6192 + attribute \src "libresoc.v:141065.3-141081.6" + process $proc$libresoc.v:141065$6124 assign { } { } assign { } { } assign { } { } @@ -225396,17 +224841,17 @@ module \l0$130 assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_exc_$signal[0:0]$6193 $1\ldst_port0_exc_$signal[0:0]$6201 - assign $0\ldst_port0_exc_$signal$1[0:0]$6194 $1\ldst_port0_exc_$signal$1[0:0]$6202 - assign $0\ldst_port0_exc_$signal$2[0:0]$6195 $1\ldst_port0_exc_$signal$2[0:0]$6203 - assign $0\ldst_port0_exc_$signal$3[0:0]$6196 $1\ldst_port0_exc_$signal$3[0:0]$6204 - assign $0\ldst_port0_exc_$signal$4[0:0]$6197 $1\ldst_port0_exc_$signal$4[0:0]$6205 - assign $0\ldst_port0_exc_$signal$5[0:0]$6198 $1\ldst_port0_exc_$signal$5[0:0]$6206 - assign $0\ldst_port0_exc_$signal$6[0:0]$6199 $1\ldst_port0_exc_$signal$6[0:0]$6207 - assign $0\ldst_port0_exc_$signal$7[0:0]$6200 $1\ldst_port0_exc_$signal$7[0:0]$6208 - attribute \src "libresoc.v:140726.5-140726.29" + assign $0\ldst_port0_exc_$signal[0:0]$6125 $1\ldst_port0_exc_$signal[0:0]$6133 + assign $0\ldst_port0_exc_$signal$1[0:0]$6126 $1\ldst_port0_exc_$signal$1[0:0]$6134 + assign $0\ldst_port0_exc_$signal$2[0:0]$6127 $1\ldst_port0_exc_$signal$2[0:0]$6135 + assign $0\ldst_port0_exc_$signal$3[0:0]$6128 $1\ldst_port0_exc_$signal$3[0:0]$6136 + assign $0\ldst_port0_exc_$signal$4[0:0]$6129 $1\ldst_port0_exc_$signal$4[0:0]$6137 + assign $0\ldst_port0_exc_$signal$5[0:0]$6130 $1\ldst_port0_exc_$signal$5[0:0]$6138 + assign $0\ldst_port0_exc_$signal$6[0:0]$6131 $1\ldst_port0_exc_$signal$6[0:0]$6139 + assign $0\ldst_port0_exc_$signal$7[0:0]$6132 $1\ldst_port0_exc_$signal$7[0:0]$6140 + attribute \src "libresoc.v:141066.5-141066.29" switch \initial - attribute \src "libresoc.v:140726.9-140726.17" + attribute \src "libresoc.v:141066.9-141066.17" case 1'1 case end @@ -225422,36 +224867,36 @@ module \l0$130 assign { } { } assign { } { } assign { } { } - assign { $1\ldst_port0_exc_$signal$7[0:0]$6208 $1\ldst_port0_exc_$signal$6[0:0]$6207 $1\ldst_port0_exc_$signal$5[0:0]$6206 $1\ldst_port0_exc_$signal$4[0:0]$6205 $1\ldst_port0_exc_$signal$3[0:0]$6204 $1\ldst_port0_exc_$signal$2[0:0]$6203 $1\ldst_port0_exc_$signal$1[0:0]$6202 $1\ldst_port0_exc_$signal[0:0]$6201 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } + assign { $1\ldst_port0_exc_$signal$7[0:0]$6140 $1\ldst_port0_exc_$signal$6[0:0]$6139 $1\ldst_port0_exc_$signal$5[0:0]$6138 $1\ldst_port0_exc_$signal$4[0:0]$6137 $1\ldst_port0_exc_$signal$3[0:0]$6136 $1\ldst_port0_exc_$signal$2[0:0]$6135 $1\ldst_port0_exc_$signal$1[0:0]$6134 $1\ldst_port0_exc_$signal[0:0]$6133 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } case - assign $1\ldst_port0_exc_$signal[0:0]$6201 1'0 - assign $1\ldst_port0_exc_$signal$1[0:0]$6202 1'0 - assign $1\ldst_port0_exc_$signal$2[0:0]$6203 1'0 - assign $1\ldst_port0_exc_$signal$3[0:0]$6204 1'0 - assign $1\ldst_port0_exc_$signal$4[0:0]$6205 1'0 - assign $1\ldst_port0_exc_$signal$5[0:0]$6206 1'0 - assign $1\ldst_port0_exc_$signal$6[0:0]$6207 1'0 - assign $1\ldst_port0_exc_$signal$7[0:0]$6208 1'0 + assign $1\ldst_port0_exc_$signal[0:0]$6133 1'0 + assign $1\ldst_port0_exc_$signal$1[0:0]$6134 1'0 + assign $1\ldst_port0_exc_$signal$2[0:0]$6135 1'0 + assign $1\ldst_port0_exc_$signal$3[0:0]$6136 1'0 + assign $1\ldst_port0_exc_$signal$4[0:0]$6137 1'0 + assign $1\ldst_port0_exc_$signal$5[0:0]$6138 1'0 + assign $1\ldst_port0_exc_$signal$6[0:0]$6139 1'0 + assign $1\ldst_port0_exc_$signal$7[0:0]$6140 1'0 end sync always - update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6193 - update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6194 - update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6195 - update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6196 - update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6197 - update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6198 - update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6199 - update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6200 + update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6125 + update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6126 + update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6127 + update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6128 + update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6129 + update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6130 + update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6131 + update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6132 end - attribute \src "libresoc.v:140742.3-140756.6" - process $proc$libresoc.v:140742$6209 + attribute \src "libresoc.v:141082.3-141096.6" + process $proc$libresoc.v:141082$6141 assign { } { } assign { } { } assign { } { } - assign $0\idx_l$23$next[0:0]$6210 $2\idx_l$23$next[0:0]$6212 - attribute \src "libresoc.v:140743.5-140743.29" + assign $0\idx_l$23$next[0:0]$6142 $2\idx_l$23$next[0:0]$6144 + attribute \src "libresoc.v:141083.5-141083.29" switch \initial - attribute \src "libresoc.v:140743.9-140743.17" + attribute \src "libresoc.v:141083.9-141083.17" case 1'1 case end @@ -225460,30 +224905,30 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\idx_l$23$next[0:0]$6211 \pick_o + assign $1\idx_l$23$next[0:0]$6143 \pick_o case - assign $1\idx_l$23$next[0:0]$6211 \idx_l$23 + assign $1\idx_l$23$next[0:0]$6143 \idx_l$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\idx_l$23$next[0:0]$6212 1'0 + assign $2\idx_l$23$next[0:0]$6144 1'0 case - assign $2\idx_l$23$next[0:0]$6212 $1\idx_l$23$next[0:0]$6211 + assign $2\idx_l$23$next[0:0]$6144 $1\idx_l$23$next[0:0]$6143 end sync always - update \idx_l$23$next $0\idx_l$23$next[0:0]$6210 + update \idx_l$23$next $0\idx_l$23$next[0:0]$6142 end - attribute \src "libresoc.v:140757.3-140766.6" - process $proc$libresoc.v:140757$6213 + attribute \src "libresoc.v:141097.3-141106.6" + process $proc$libresoc.v:141097$6145 assign { } { } assign { } { } assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:140758.5-140758.29" + attribute \src "libresoc.v:141098.5-141098.29" switch \initial - attribute \src "libresoc.v:140758.9-140758.17" + attribute \src "libresoc.v:141098.9-141098.17" case 1'1 case end @@ -225499,14 +224944,14 @@ module \l0$130 sync always update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] end - attribute \src "libresoc.v:140767.3-140776.6" - process $proc$libresoc.v:140767$6214 + attribute \src "libresoc.v:141107.3-141116.6" + process $proc$libresoc.v:141107$6146 assign { } { } assign { } { } assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:140768.5-140768.29" + attribute \src "libresoc.v:141108.5-141108.29" switch \initial - attribute \src "libresoc.v:140768.9-140768.17" + attribute \src "libresoc.v:141108.9-141108.17" case 1'1 case end @@ -225522,14 +224967,14 @@ module \l0$130 sync always update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] end - attribute \src "libresoc.v:140777.3-140786.6" - process $proc$libresoc.v:140777$6215 + attribute \src "libresoc.v:141117.3-141126.6" + process $proc$libresoc.v:141117$6147 assign { } { } assign { } { } assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:140778.5-140778.29" + attribute \src "libresoc.v:141118.5-141118.29" switch \initial - attribute \src "libresoc.v:140778.9-140778.17" + attribute \src "libresoc.v:141118.9-141118.17" case 1'1 case end @@ -225545,14 +224990,14 @@ module \l0$130 sync always update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] end - attribute \src "libresoc.v:140787.3-140796.6" - process $proc$libresoc.v:140787$6216 + attribute \src "libresoc.v:141127.3-141136.6" + process $proc$libresoc.v:141127$6148 assign { } { } assign { } { } assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:140788.5-140788.29" + attribute \src "libresoc.v:141128.5-141128.29" switch \initial - attribute \src "libresoc.v:140788.9-140788.17" + attribute \src "libresoc.v:141128.9-141128.17" case 1'1 case end @@ -225568,14 +225013,14 @@ module \l0$130 sync always update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] end - attribute \src "libresoc.v:140797.3-140806.6" - process $proc$libresoc.v:140797$6217 + attribute \src "libresoc.v:141137.3-141146.6" + process $proc$libresoc.v:141137$6149 assign { } { } assign { } { } assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:140798.5-140798.29" + attribute \src "libresoc.v:141138.5-141138.29" switch \initial - attribute \src "libresoc.v:140798.9-140798.17" + attribute \src "libresoc.v:141138.9-141138.17" case 1'1 case end @@ -225591,14 +225036,14 @@ module \l0$130 sync always update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] end - attribute \src "libresoc.v:140807.3-140821.6" - process $proc$libresoc.v:140807$6218 + attribute \src "libresoc.v:141147.3-141161.6" + process $proc$libresoc.v:141147$6150 assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:140808.5-140808.29" + attribute \src "libresoc.v:141148.5-141148.29" switch \initial - attribute \src "libresoc.v:140808.9-140808.17" + attribute \src "libresoc.v:141148.9-141148.17" case 1'1 case end @@ -225623,14 +225068,14 @@ module \l0$130 sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:140822.3-140831.6" - process $proc$libresoc.v:140822$6219 + attribute \src "libresoc.v:141162.3-141171.6" + process $proc$libresoc.v:141162$6151 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:140823.5-140823.29" + attribute \src "libresoc.v:141163.5-141163.29" switch \initial - attribute \src "libresoc.v:140823.9-140823.17" + attribute \src "libresoc.v:141163.9-141163.17" case 1'1 case end @@ -225646,14 +225091,14 @@ module \l0$130 sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:140832.3-140841.6" - process $proc$libresoc.v:140832$6220 + attribute \src "libresoc.v:141172.3-141181.6" + process $proc$libresoc.v:141172$6152 assign { } { } assign { } { } - assign $0\ldst_port0_is_ld_i$8[0:0]$6221 $1\ldst_port0_is_ld_i$8[0:0]$6222 - attribute \src "libresoc.v:140833.5-140833.29" + assign $0\ldst_port0_is_ld_i$8[0:0]$6153 $1\ldst_port0_is_ld_i$8[0:0]$6154 + attribute \src "libresoc.v:141173.5-141173.29" switch \initial - attribute \src "libresoc.v:140833.9-140833.17" + attribute \src "libresoc.v:141173.9-141173.17" case 1'1 case end @@ -225662,21 +225107,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_ld_i$8[0:0]$6222 \ldst_port0_is_ld_i + assign $1\ldst_port0_is_ld_i$8[0:0]$6154 \ldst_port0_is_ld_i case - assign $1\ldst_port0_is_ld_i$8[0:0]$6222 1'0 + assign $1\ldst_port0_is_ld_i$8[0:0]$6154 1'0 end sync always - update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6221 + update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6153 end - attribute \src "libresoc.v:140842.3-140851.6" - process $proc$libresoc.v:140842$6223 + attribute \src "libresoc.v:141182.3-141191.6" + process $proc$libresoc.v:141182$6155 assign { } { } assign { } { } - assign $0\ldst_port0_is_st_i$9[0:0]$6224 $1\ldst_port0_is_st_i$9[0:0]$6225 - attribute \src "libresoc.v:140843.5-140843.29" + assign $0\ldst_port0_is_st_i$9[0:0]$6156 $1\ldst_port0_is_st_i$9[0:0]$6157 + attribute \src "libresoc.v:141183.5-141183.29" switch \initial - attribute \src "libresoc.v:140843.9-140843.17" + attribute \src "libresoc.v:141183.9-141183.17" case 1'1 case end @@ -225685,21 +225130,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_st_i$9[0:0]$6225 \ldst_port0_is_st_i + assign $1\ldst_port0_is_st_i$9[0:0]$6157 \ldst_port0_is_st_i case - assign $1\ldst_port0_is_st_i$9[0:0]$6225 1'0 + assign $1\ldst_port0_is_st_i$9[0:0]$6157 1'0 end sync always - update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6224 + update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6156 end - attribute \src "libresoc.v:140852.3-140861.6" - process $proc$libresoc.v:140852$6226 + attribute \src "libresoc.v:141192.3-141201.6" + process $proc$libresoc.v:141192$6158 assign { } { } assign { } { } - assign $0\ldst_port0_data_len$11[3:0]$6227 $1\ldst_port0_data_len$11[3:0]$6228 - attribute \src "libresoc.v:140853.5-140853.29" + assign $0\ldst_port0_data_len$11[3:0]$6159 $1\ldst_port0_data_len$11[3:0]$6160 + attribute \src "libresoc.v:141193.5-141193.29" switch \initial - attribute \src "libresoc.v:140853.9-140853.17" + attribute \src "libresoc.v:141193.9-141193.17" case 1'1 case end @@ -225708,21 +225153,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_data_len$11[3:0]$6228 \ldst_port0_data_len + assign $1\ldst_port0_data_len$11[3:0]$6160 \ldst_port0_data_len case - assign $1\ldst_port0_data_len$11[3:0]$6228 4'0000 + assign $1\ldst_port0_data_len$11[3:0]$6160 4'0000 end sync always - update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6227 + update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6159 end - attribute \src "libresoc.v:140862.3-140871.6" - process $proc$libresoc.v:140862$6229 + attribute \src "libresoc.v:141202.3-141211.6" + process $proc$libresoc.v:141202$6161 assign { } { } assign { } { } assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:140863.5-140863.29" + attribute \src "libresoc.v:141203.5-141203.29" switch \initial - attribute \src "libresoc.v:140863.9-140863.17" + attribute \src "libresoc.v:141203.9-141203.17" case 1'1 case end @@ -225738,10 +225183,10 @@ module \l0$130 sync always update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] end - connect \$20 $or$libresoc.v:140636$6171_Y - connect \$24 $ternary$libresoc.v:140637$6172_Y - connect \$26 $not$libresoc.v:140638$6173_Y - connect \$28 $not$libresoc.v:140639$6174_Y + connect \$20 $or$libresoc.v:140976$6103_Y + connect \$24 $ternary$libresoc.v:140977$6104_Y + connect \$26 $not$libresoc.v:140978$6105_Y + connect \$28 $not$libresoc.v:140979$6106_Y connect \$22 \$24 connect \$32 \ldst_port0_addr_i connect \ldst_port0_go_die_i$30 1'0 @@ -225758,37 +225203,37 @@ module \l0$130 connect \reset_delay$next \reset_l_q_reset connect \pick_i \$20 end -attribute \src "libresoc.v:140891.1-140949.10" +attribute \src "libresoc.v:141231.1-141289.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" attribute \generator "nMigen" module \ld_active - attribute \src "libresoc.v:140892.7-140892.20" + attribute \src "libresoc.v:141232.7-141232.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140937.3-140945.6" - wire $0\q_int$next[0:0]$6244 - attribute \src "libresoc.v:140935.3-140936.27" + attribute \src "libresoc.v:141277.3-141285.6" + wire $0\q_int$next[0:0]$6176 + attribute \src "libresoc.v:141275.3-141276.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:140937.3-140945.6" - wire $1\q_int$next[0:0]$6245 - attribute \src "libresoc.v:140914.7-140914.19" + attribute \src "libresoc.v:141277.3-141285.6" + wire $1\q_int$next[0:0]$6177 + attribute \src "libresoc.v:141254.7-141254.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:140927.17-140927.96" - wire $and$libresoc.v:140927$6234_Y - attribute \src "libresoc.v:140932.17-140932.96" - wire $and$libresoc.v:140932$6239_Y - attribute \src "libresoc.v:140929.18-140929.99" - wire $not$libresoc.v:140929$6236_Y - attribute \src "libresoc.v:140931.17-140931.98" - wire $not$libresoc.v:140931$6238_Y - attribute \src "libresoc.v:140934.17-140934.98" - wire $not$libresoc.v:140934$6241_Y - attribute \src "libresoc.v:140928.18-140928.104" - wire $or$libresoc.v:140928$6235_Y - attribute \src "libresoc.v:140930.18-140930.105" - wire $or$libresoc.v:140930$6237_Y - attribute \src "libresoc.v:140933.17-140933.103" - wire $or$libresoc.v:140933$6240_Y + attribute \src "libresoc.v:141267.17-141267.96" + wire $and$libresoc.v:141267$6166_Y + attribute \src "libresoc.v:141272.17-141272.96" + wire $and$libresoc.v:141272$6171_Y + attribute \src "libresoc.v:141269.18-141269.99" + wire $not$libresoc.v:141269$6168_Y + attribute \src "libresoc.v:141271.17-141271.98" + wire $not$libresoc.v:141271$6170_Y + attribute \src "libresoc.v:141274.17-141274.98" + wire $not$libresoc.v:141274$6173_Y + attribute \src "libresoc.v:141268.18-141268.104" + wire $or$libresoc.v:141268$6167_Y + attribute \src "libresoc.v:141270.18-141270.105" + wire $or$libresoc.v:141270$6169_Y + attribute \src "libresoc.v:141273.17-141273.103" + wire $or$libresoc.v:141273$6172_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -225805,11 +225250,11 @@ module \ld_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:140892.7-140892.15" + attribute \src "libresoc.v:141232.7-141232.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -225826,7 +225271,7 @@ module \ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:140927$6234 + cell $and $and$libresoc.v:141267$6166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225834,10 +225279,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:140927$6234_Y + connect \Y $and$libresoc.v:141267$6166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:140932$6239 + cell $and $and$libresoc.v:141272$6171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225845,34 +225290,34 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:140932$6239_Y + connect \Y $and$libresoc.v:141272$6171_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:140929$6236 + cell $not $not$libresoc.v:141269$6168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_ld_active - connect \Y $not$libresoc.v:140929$6236_Y + connect \Y $not$libresoc.v:141269$6168_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:140931$6238 + cell $not $not$libresoc.v:141271$6170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:140931$6238_Y + connect \Y $not$libresoc.v:141271$6170_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:140934$6241 + cell $not $not$libresoc.v:141274$6173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:140934$6241_Y + connect \Y $not$libresoc.v:141274$6173_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:140928$6235 + cell $or $or$libresoc.v:141268$6167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225880,10 +225325,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_ld_active - connect \Y $or$libresoc.v:140928$6235_Y + connect \Y $or$libresoc.v:141268$6167_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:140930$6237 + cell $or $or$libresoc.v:141270$6169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225891,10 +225336,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_ld_active connect \B \q_int - connect \Y $or$libresoc.v:140930$6237_Y + connect \Y $or$libresoc.v:141270$6169_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:140933$6240 + cell $or $or$libresoc.v:141273$6172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225902,39 +225347,39 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_ld_active - connect \Y $or$libresoc.v:140933$6240_Y + connect \Y $or$libresoc.v:141273$6172_Y end - attribute \src "libresoc.v:140892.7-140892.20" - process $proc$libresoc.v:140892$6246 + attribute \src "libresoc.v:141232.7-141232.20" + process $proc$libresoc.v:141232$6178 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:140914.7-140914.19" - process $proc$libresoc.v:140914$6247 + attribute \src "libresoc.v:141254.7-141254.19" + process $proc$libresoc.v:141254$6179 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:140935.3-140936.27" - process $proc$libresoc.v:140935$6242 + attribute \src "libresoc.v:141275.3-141276.27" + process $proc$libresoc.v:141275$6174 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:140937.3-140945.6" - process $proc$libresoc.v:140937$6243 + attribute \src "libresoc.v:141277.3-141285.6" + process $proc$libresoc.v:141277$6175 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$6244 $1\q_int$next[0:0]$6245 - attribute \src "libresoc.v:140938.5-140938.29" + assign $0\q_int$next[0:0]$6176 $1\q_int$next[0:0]$6177 + attribute \src "libresoc.v:141278.5-141278.29" switch \initial - attribute \src "libresoc.v:140938.9-140938.17" + attribute \src "libresoc.v:141278.9-141278.17" case 1'1 case end @@ -225943,572 +225388,572 @@ module \ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6245 1'0 + assign $1\q_int$next[0:0]$6177 1'0 case - assign $1\q_int$next[0:0]$6245 \$5 + assign $1\q_int$next[0:0]$6177 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$6244 + update \q_int$next $0\q_int$next[0:0]$6176 end - connect \$9 $and$libresoc.v:140927$6234_Y - connect \$11 $or$libresoc.v:140928$6235_Y - connect \$13 $not$libresoc.v:140929$6236_Y - connect \$15 $or$libresoc.v:140930$6237_Y - connect \$1 $not$libresoc.v:140931$6238_Y - connect \$3 $and$libresoc.v:140932$6239_Y - connect \$5 $or$libresoc.v:140933$6240_Y - connect \$7 $not$libresoc.v:140934$6241_Y + connect \$9 $and$libresoc.v:141267$6166_Y + connect \$11 $or$libresoc.v:141268$6167_Y + connect \$13 $not$libresoc.v:141269$6168_Y + connect \$15 $or$libresoc.v:141270$6169_Y + connect \$1 $not$libresoc.v:141271$6170_Y + connect \$3 $and$libresoc.v:141272$6171_Y + connect \$5 $or$libresoc.v:141273$6172_Y + connect \$7 $not$libresoc.v:141274$6173_Y connect \qlq_ld_active \$15 connect \qn_ld_active \$13 connect \q_ld_active \$11 end -attribute \src "libresoc.v:140953.1-142316.10" +attribute \src "libresoc.v:141293.1-142656.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" attribute \generator "nMigen" module \ldst0 - attribute \src "libresoc.v:141971.3-141979.6" - wire $0\adr_l_r_adr$next[0:0]$6390 - attribute \src "libresoc.v:141853.3-141854.39" + attribute \src "libresoc.v:142311.3-142319.6" + wire $0\adr_l_r_adr$next[0:0]$6322 + attribute \src "libresoc.v:142193.3-142194.39" wire $0\adr_l_r_adr[0:0] - attribute \src "libresoc.v:141799.3-141800.21" + attribute \src "libresoc.v:142139.3-142140.21" wire $0\alu_ok[0:0] - attribute \src "libresoc.v:142136.3-142145.6" + attribute \src "libresoc.v:142476.3-142485.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:142146.3-142155.6" + attribute \src "libresoc.v:142486.3-142495.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:142126.3-142135.6" - wire width 64 $0\ea_r$next[63:0]$6478 - attribute \src "libresoc.v:141801.3-141802.25" + attribute \src "libresoc.v:142466.3-142475.6" + wire width 64 $0\ea_r$next[63:0]$6410 + attribute \src "libresoc.v:142141.3-142142.25" wire width 64 $0\ea_r[63:0] - attribute \src "libresoc.v:140954.7-140954.20" + attribute \src "libresoc.v:141294.7-141294.20" wire $0\initial[0:0] - attribute \src "libresoc.v:142201.3-142220.6" + attribute \src "libresoc.v:142541.3-142560.6" wire width 64 $0\ldd_o[63:0] - attribute \src "libresoc.v:142165.3-142188.6" + attribute \src "libresoc.v:142505.3-142528.6" wire width 64 $0\lddata_r[63:0] - attribute \src "libresoc.v:142068.3-142077.6" - wire width 64 $0\ldo_r$next[63:0]$6463 - attribute \src "libresoc.v:141809.3-141810.27" + attribute \src "libresoc.v:142408.3-142417.6" + wire width 64 $0\ldo_r$next[63:0]$6395 + attribute \src "libresoc.v:142149.3-142150.27" wire width 64 $0\ldo_r[63:0] - attribute \src "libresoc.v:141797.3-141798.33" + attribute \src "libresoc.v:142137.3-142138.33" wire width 96 $0\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:142156.3-142164.6" - wire $0\ldst_port0_addr_i_ok$next[0:0]$6483 - attribute \src "libresoc.v:141795.3-141796.57" + attribute \src "libresoc.v:142496.3-142504.6" + wire $0\ldst_port0_addr_i_ok$next[0:0]$6415 + attribute \src "libresoc.v:142135.3-142136.57" wire $0\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:142245.3-142256.6" + attribute \src "libresoc.v:142585.3-142596.6" wire width 64 $0\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:142016.3-142024.6" - wire $0\lsd_l_r_lsd$next[0:0]$6405 - attribute \src "libresoc.v:141843.3-141844.39" + attribute \src "libresoc.v:142356.3-142364.6" + wire $0\lsd_l_r_lsd$next[0:0]$6337 + attribute \src "libresoc.v:142183.3-142184.39" wire $0\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:141944.3-141952.6" - wire $0\opc_l_r_opc$next[0:0]$6381 - attribute \src "libresoc.v:141859.3-141860.39" + attribute \src "libresoc.v:142284.3-142292.6" + wire $0\opc_l_r_opc$next[0:0]$6313 + attribute \src "libresoc.v:142199.3-142200.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:141935.3-141943.6" - wire $0\opc_l_s_opc$next[0:0]$6378 - attribute \src "libresoc.v:141861.3-141862.39" + attribute \src "libresoc.v:142275.3-142283.6" + wire $0\opc_l_s_opc$next[0:0]$6310 + attribute \src "libresoc.v:142201.3-142202.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $0\oper_r__byte_reverse$next[0:0]$6408 - attribute \src "libresoc.v:141835.3-141836.57" + attribute \src "libresoc.v:142365.3-142407.6" + wire $0\oper_r__byte_reverse$next[0:0]$6340 + attribute \src "libresoc.v:142175.3-142176.57" wire $0\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire width 4 $0\oper_r__data_len$next[3:0]$6409 - attribute \src "libresoc.v:141833.3-141834.49" + attribute \src "libresoc.v:142365.3-142407.6" + wire width 4 $0\oper_r__data_len$next[3:0]$6341 + attribute \src "libresoc.v:142173.3-142174.49" wire width 4 $0\oper_r__data_len[3:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire width 14 $0\oper_r__fn_unit$next[13:0]$6410 - attribute \src "libresoc.v:141813.3-141814.47" + attribute \src "libresoc.v:142365.3-142407.6" + wire width 14 $0\oper_r__fn_unit$next[13:0]$6342 + attribute \src "libresoc.v:142153.3-142154.47" wire width 14 $0\oper_r__fn_unit[13:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire width 64 $0\oper_r__imm_data__data$next[63:0]$6411 - attribute \src "libresoc.v:141815.3-141816.61" + attribute \src "libresoc.v:142365.3-142407.6" + wire width 64 $0\oper_r__imm_data__data$next[63:0]$6343 + attribute \src "libresoc.v:142155.3-142156.61" wire width 64 $0\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $0\oper_r__imm_data__ok$next[0:0]$6412 - attribute \src "libresoc.v:141817.3-141818.57" + attribute \src "libresoc.v:142365.3-142407.6" + wire $0\oper_r__imm_data__ok$next[0:0]$6344 + attribute \src "libresoc.v:142157.3-142158.57" wire $0\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire width 32 $0\oper_r__insn$next[31:0]$6413 - attribute \src "libresoc.v:141841.3-141842.41" + attribute \src "libresoc.v:142365.3-142407.6" + wire width 32 $0\oper_r__insn$next[31:0]$6345 + attribute \src "libresoc.v:142181.3-142182.41" wire width 32 $0\oper_r__insn[31:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire width 7 $0\oper_r__insn_type$next[6:0]$6414 - attribute \src "libresoc.v:141811.3-141812.51" + attribute \src "libresoc.v:142365.3-142407.6" + wire width 7 $0\oper_r__insn_type$next[6:0]$6346 + attribute \src "libresoc.v:142151.3-142152.51" wire width 7 $0\oper_r__insn_type[6:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $0\oper_r__is_32bit$next[0:0]$6415 - attribute \src "libresoc.v:141829.3-141830.49" + attribute \src "libresoc.v:142365.3-142407.6" + wire $0\oper_r__is_32bit$next[0:0]$6347 + attribute \src "libresoc.v:142169.3-142170.49" wire $0\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $0\oper_r__is_signed$next[0:0]$6416 - attribute \src "libresoc.v:141831.3-141832.51" + attribute \src "libresoc.v:142365.3-142407.6" + wire $0\oper_r__is_signed$next[0:0]$6348 + attribute \src "libresoc.v:142171.3-142172.51" wire $0\oper_r__is_signed[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire width 2 $0\oper_r__ldst_mode$next[1:0]$6417 - attribute \src "libresoc.v:141839.3-141840.51" + attribute \src "libresoc.v:142365.3-142407.6" + wire width 2 $0\oper_r__ldst_mode$next[1:0]$6349 + attribute \src "libresoc.v:142179.3-142180.51" wire width 2 $0\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $0\oper_r__oe__oe$next[0:0]$6418 - attribute \src "libresoc.v:141825.3-141826.45" + attribute \src "libresoc.v:142365.3-142407.6" + wire $0\oper_r__oe__oe$next[0:0]$6350 + attribute \src "libresoc.v:142165.3-142166.45" wire $0\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $0\oper_r__oe__ok$next[0:0]$6419 - attribute \src "libresoc.v:141827.3-141828.45" + attribute \src "libresoc.v:142365.3-142407.6" + wire $0\oper_r__oe__ok$next[0:0]$6351 + attribute \src "libresoc.v:142167.3-142168.45" wire $0\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $0\oper_r__rc__ok$next[0:0]$6420 - attribute \src "libresoc.v:141823.3-141824.45" + attribute \src "libresoc.v:142365.3-142407.6" + wire $0\oper_r__rc__ok$next[0:0]$6352 + attribute \src "libresoc.v:142163.3-142164.45" wire $0\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $0\oper_r__rc__rc$next[0:0]$6421 - attribute \src "libresoc.v:141821.3-141822.45" + attribute \src "libresoc.v:142365.3-142407.6" + wire $0\oper_r__rc__rc$next[0:0]$6353 + attribute \src "libresoc.v:142161.3-142162.45" wire $0\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $0\oper_r__sign_extend$next[0:0]$6422 - attribute \src "libresoc.v:141837.3-141838.55" + attribute \src "libresoc.v:142365.3-142407.6" + wire $0\oper_r__sign_extend$next[0:0]$6354 + attribute \src "libresoc.v:142177.3-142178.55" wire $0\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $0\oper_r__zero_a$next[0:0]$6423 - attribute \src "libresoc.v:141819.3-141820.45" + attribute \src "libresoc.v:142365.3-142407.6" + wire $0\oper_r__zero_a$next[0:0]$6355 + attribute \src "libresoc.v:142159.3-142160.45" wire $0\oper_r__zero_a[0:0] - attribute \src "libresoc.v:141863.3-141864.28" + attribute \src "libresoc.v:142203.3-142204.28" wire $0\p_st_go[0:0] - attribute \src "libresoc.v:142189.3-142200.6" + attribute \src "libresoc.v:142529.3-142540.6" wire width 64 $0\revnorev[63:0] - attribute \src "libresoc.v:141962.3-141970.6" - wire width 3 $0\src_l_r_src$next[2:0]$6387 - attribute \src "libresoc.v:141855.3-141856.39" + attribute \src "libresoc.v:142302.3-142310.6" + wire width 3 $0\src_l_r_src$next[2:0]$6319 + attribute \src "libresoc.v:142195.3-142196.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:141953.3-141961.6" - wire width 3 $0\src_l_s_src$next[2:0]$6384 - attribute \src "libresoc.v:141857.3-141858.39" + attribute \src "libresoc.v:142293.3-142301.6" + wire width 3 $0\src_l_s_src$next[2:0]$6316 + attribute \src "libresoc.v:142197.3-142198.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:142078.3-142093.6" - wire width 64 $0\src_r0$next[63:0]$6466 - attribute \src "libresoc.v:141807.3-141808.29" + attribute \src "libresoc.v:142418.3-142433.6" + wire width 64 $0\src_r0$next[63:0]$6398 + attribute \src "libresoc.v:142147.3-142148.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:142094.3-142109.6" - wire width 64 $0\src_r1$next[63:0]$6470 - attribute \src "libresoc.v:141805.3-141806.29" + attribute \src "libresoc.v:142434.3-142449.6" + wire width 64 $0\src_r1$next[63:0]$6402 + attribute \src "libresoc.v:142145.3-142146.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:142110.3-142125.6" - wire width 64 $0\src_r2$next[63:0]$6474 - attribute \src "libresoc.v:141803.3-141804.29" + attribute \src "libresoc.v:142450.3-142465.6" + wire width 64 $0\src_r2$next[63:0]$6406 + attribute \src "libresoc.v:142143.3-142144.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:142221.3-142244.6" + attribute \src "libresoc.v:142561.3-142584.6" wire width 64 $0\stdata_r[63:0] - attribute \src "libresoc.v:142007.3-142015.6" - wire $0\sto_l_r_sto$next[0:0]$6402 - attribute \src "libresoc.v:141845.3-141846.39" + attribute \src "libresoc.v:142347.3-142355.6" + wire $0\sto_l_r_sto$next[0:0]$6334 + attribute \src "libresoc.v:142185.3-142186.39" wire $0\sto_l_r_sto[0:0] - attribute \src "libresoc.v:141998.3-142006.6" - wire $0\upd_l_r_upd$next[0:0]$6399 - attribute \src "libresoc.v:141847.3-141848.39" + attribute \src "libresoc.v:142338.3-142346.6" + wire $0\upd_l_r_upd$next[0:0]$6331 + attribute \src "libresoc.v:142187.3-142188.39" wire $0\upd_l_r_upd[0:0] - attribute \src "libresoc.v:141989.3-141997.6" - wire $0\upd_l_s_upd$next[0:0]$6396 - attribute \src "libresoc.v:141849.3-141850.39" + attribute \src "libresoc.v:142329.3-142337.6" + wire $0\upd_l_s_upd$next[0:0]$6328 + attribute \src "libresoc.v:142189.3-142190.39" wire $0\upd_l_s_upd[0:0] - attribute \src "libresoc.v:141980.3-141988.6" - wire $0\wri_l_r_wri$next[0:0]$6393 - attribute \src "libresoc.v:141851.3-141852.39" + attribute \src "libresoc.v:142320.3-142328.6" + wire $0\wri_l_r_wri$next[0:0]$6325 + attribute \src "libresoc.v:142191.3-142192.39" wire $0\wri_l_r_wri[0:0] - attribute \src "libresoc.v:141971.3-141979.6" - wire $1\adr_l_r_adr$next[0:0]$6391 - attribute \src "libresoc.v:141150.7-141150.25" + attribute \src "libresoc.v:142311.3-142319.6" + wire $1\adr_l_r_adr$next[0:0]$6323 + attribute \src "libresoc.v:141490.7-141490.25" wire $1\adr_l_r_adr[0:0] - attribute \src "libresoc.v:141164.7-141164.20" + attribute \src "libresoc.v:141504.7-141504.20" wire $1\alu_ok[0:0] - attribute \src "libresoc.v:142136.3-142145.6" + attribute \src "libresoc.v:142476.3-142485.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:142146.3-142155.6" + attribute \src "libresoc.v:142486.3-142495.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:142126.3-142135.6" - wire width 64 $1\ea_r$next[63:0]$6479 - attribute \src "libresoc.v:141210.14-141210.41" + attribute \src "libresoc.v:142466.3-142475.6" + wire width 64 $1\ea_r$next[63:0]$6411 + attribute \src "libresoc.v:141550.14-141550.41" wire width 64 $1\ea_r[63:0] - attribute \src "libresoc.v:142201.3-142220.6" + attribute \src "libresoc.v:142541.3-142560.6" wire width 64 $1\ldd_o[63:0] - attribute \src "libresoc.v:142165.3-142188.6" + attribute \src "libresoc.v:142505.3-142528.6" wire width 64 $1\lddata_r[63:0] - attribute \src "libresoc.v:142068.3-142077.6" - wire width 64 $1\ldo_r$next[63:0]$6464 - attribute \src "libresoc.v:141240.14-141240.42" + attribute \src "libresoc.v:142408.3-142417.6" + wire width 64 $1\ldo_r$next[63:0]$6396 + attribute \src "libresoc.v:141580.14-141580.42" wire width 64 $1\ldo_r[63:0] - attribute \src "libresoc.v:141245.14-141245.62" + attribute \src "libresoc.v:141585.14-141585.62" wire width 96 $1\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:142156.3-142164.6" - wire $1\ldst_port0_addr_i_ok$next[0:0]$6484 - attribute \src "libresoc.v:141250.7-141250.34" + attribute \src "libresoc.v:142496.3-142504.6" + wire $1\ldst_port0_addr_i_ok$next[0:0]$6416 + attribute \src "libresoc.v:141590.7-141590.34" wire $1\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:142245.3-142256.6" + attribute \src "libresoc.v:142585.3-142596.6" wire width 64 $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:142016.3-142024.6" - wire $1\lsd_l_r_lsd$next[0:0]$6406 - attribute \src "libresoc.v:141299.7-141299.25" + attribute \src "libresoc.v:142356.3-142364.6" + wire $1\lsd_l_r_lsd$next[0:0]$6338 + attribute \src "libresoc.v:141639.7-141639.25" wire $1\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:141944.3-141952.6" - wire $1\opc_l_r_opc$next[0:0]$6382 - attribute \src "libresoc.v:141313.7-141313.25" + attribute \src "libresoc.v:142284.3-142292.6" + wire $1\opc_l_r_opc$next[0:0]$6314 + attribute \src "libresoc.v:141653.7-141653.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:141935.3-141943.6" - wire $1\opc_l_s_opc$next[0:0]$6379 - attribute \src "libresoc.v:141317.7-141317.25" + attribute \src "libresoc.v:142275.3-142283.6" + wire $1\opc_l_s_opc$next[0:0]$6311 + attribute \src "libresoc.v:141657.7-141657.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $1\oper_r__byte_reverse$next[0:0]$6424 - attribute \src "libresoc.v:141448.7-141448.34" + attribute \src "libresoc.v:142365.3-142407.6" + wire $1\oper_r__byte_reverse$next[0:0]$6356 + attribute \src "libresoc.v:141788.7-141788.34" wire $1\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire width 4 $1\oper_r__data_len$next[3:0]$6425 - attribute \src "libresoc.v:141452.13-141452.36" + attribute \src "libresoc.v:142365.3-142407.6" + wire width 4 $1\oper_r__data_len$next[3:0]$6357 + attribute \src "libresoc.v:141792.13-141792.36" wire width 4 $1\oper_r__data_len[3:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire width 14 $1\oper_r__fn_unit$next[13:0]$6426 - attribute \src "libresoc.v:141471.14-141471.40" + attribute \src "libresoc.v:142365.3-142407.6" + wire width 14 $1\oper_r__fn_unit$next[13:0]$6358 + attribute \src "libresoc.v:141811.14-141811.40" wire width 14 $1\oper_r__fn_unit[13:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire width 64 $1\oper_r__imm_data__data$next[63:0]$6427 - attribute \src "libresoc.v:141475.14-141475.59" + attribute \src "libresoc.v:142365.3-142407.6" + wire width 64 $1\oper_r__imm_data__data$next[63:0]$6359 + attribute \src "libresoc.v:141815.14-141815.59" wire width 64 $1\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $1\oper_r__imm_data__ok$next[0:0]$6428 - attribute \src "libresoc.v:141479.7-141479.34" + attribute \src "libresoc.v:142365.3-142407.6" + wire $1\oper_r__imm_data__ok$next[0:0]$6360 + attribute \src "libresoc.v:141819.7-141819.34" wire $1\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire width 32 $1\oper_r__insn$next[31:0]$6429 - attribute \src "libresoc.v:141483.14-141483.34" + attribute \src "libresoc.v:142365.3-142407.6" + wire width 32 $1\oper_r__insn$next[31:0]$6361 + attribute \src "libresoc.v:141823.14-141823.34" wire width 32 $1\oper_r__insn[31:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire width 7 $1\oper_r__insn_type$next[6:0]$6430 - attribute \src "libresoc.v:141562.13-141562.38" + attribute \src "libresoc.v:142365.3-142407.6" + wire width 7 $1\oper_r__insn_type$next[6:0]$6362 + attribute \src "libresoc.v:141902.13-141902.38" wire width 7 $1\oper_r__insn_type[6:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $1\oper_r__is_32bit$next[0:0]$6431 - attribute \src "libresoc.v:141566.7-141566.30" + attribute \src "libresoc.v:142365.3-142407.6" + wire $1\oper_r__is_32bit$next[0:0]$6363 + attribute \src "libresoc.v:141906.7-141906.30" wire $1\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $1\oper_r__is_signed$next[0:0]$6432 - attribute \src "libresoc.v:141570.7-141570.31" + attribute \src "libresoc.v:142365.3-142407.6" + wire $1\oper_r__is_signed$next[0:0]$6364 + attribute \src "libresoc.v:141910.7-141910.31" wire $1\oper_r__is_signed[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire width 2 $1\oper_r__ldst_mode$next[1:0]$6433 - attribute \src "libresoc.v:141579.13-141579.37" + attribute \src "libresoc.v:142365.3-142407.6" + wire width 2 $1\oper_r__ldst_mode$next[1:0]$6365 + attribute \src "libresoc.v:141919.13-141919.37" wire width 2 $1\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $1\oper_r__oe__oe$next[0:0]$6434 - attribute \src "libresoc.v:141583.7-141583.28" + attribute \src "libresoc.v:142365.3-142407.6" + wire $1\oper_r__oe__oe$next[0:0]$6366 + attribute \src "libresoc.v:141923.7-141923.28" wire $1\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $1\oper_r__oe__ok$next[0:0]$6435 - attribute \src "libresoc.v:141587.7-141587.28" + attribute \src "libresoc.v:142365.3-142407.6" + wire $1\oper_r__oe__ok$next[0:0]$6367 + attribute \src "libresoc.v:141927.7-141927.28" wire $1\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $1\oper_r__rc__ok$next[0:0]$6436 - attribute \src "libresoc.v:141591.7-141591.28" + attribute \src "libresoc.v:142365.3-142407.6" + wire $1\oper_r__rc__ok$next[0:0]$6368 + attribute \src "libresoc.v:141931.7-141931.28" wire $1\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $1\oper_r__rc__rc$next[0:0]$6437 - attribute \src "libresoc.v:141595.7-141595.28" + attribute \src "libresoc.v:142365.3-142407.6" + wire $1\oper_r__rc__rc$next[0:0]$6369 + attribute \src "libresoc.v:141935.7-141935.28" wire $1\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $1\oper_r__sign_extend$next[0:0]$6438 - attribute \src "libresoc.v:141599.7-141599.33" + attribute \src "libresoc.v:142365.3-142407.6" + wire $1\oper_r__sign_extend$next[0:0]$6370 + attribute \src "libresoc.v:141939.7-141939.33" wire $1\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $1\oper_r__zero_a$next[0:0]$6439 - attribute \src "libresoc.v:141603.7-141603.28" + attribute \src "libresoc.v:142365.3-142407.6" + wire $1\oper_r__zero_a$next[0:0]$6371 + attribute \src "libresoc.v:141943.7-141943.28" wire $1\oper_r__zero_a[0:0] - attribute \src "libresoc.v:141607.7-141607.21" + attribute \src "libresoc.v:141947.7-141947.21" wire $1\p_st_go[0:0] - attribute \src "libresoc.v:142189.3-142200.6" + attribute \src "libresoc.v:142529.3-142540.6" wire width 64 $1\revnorev[63:0] - attribute \src "libresoc.v:141962.3-141970.6" - wire width 3 $1\src_l_r_src$next[2:0]$6388 - attribute \src "libresoc.v:141649.13-141649.31" + attribute \src "libresoc.v:142302.3-142310.6" + wire width 3 $1\src_l_r_src$next[2:0]$6320 + attribute \src "libresoc.v:141989.13-141989.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:141953.3-141961.6" - wire width 3 $1\src_l_s_src$next[2:0]$6385 - attribute \src "libresoc.v:141653.13-141653.31" + attribute \src "libresoc.v:142293.3-142301.6" + wire width 3 $1\src_l_s_src$next[2:0]$6317 + attribute \src "libresoc.v:141993.13-141993.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:142078.3-142093.6" - wire width 64 $1\src_r0$next[63:0]$6467 - attribute \src "libresoc.v:141657.14-141657.43" + attribute \src "libresoc.v:142418.3-142433.6" + wire width 64 $1\src_r0$next[63:0]$6399 + attribute \src "libresoc.v:141997.14-141997.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:142094.3-142109.6" - wire width 64 $1\src_r1$next[63:0]$6471 - attribute \src "libresoc.v:141661.14-141661.43" + attribute \src "libresoc.v:142434.3-142449.6" + wire width 64 $1\src_r1$next[63:0]$6403 + attribute \src "libresoc.v:142001.14-142001.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:142110.3-142125.6" - wire width 64 $1\src_r2$next[63:0]$6475 - attribute \src "libresoc.v:141665.14-141665.43" + attribute \src "libresoc.v:142450.3-142465.6" + wire width 64 $1\src_r2$next[63:0]$6407 + attribute \src "libresoc.v:142005.14-142005.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:142221.3-142244.6" + attribute \src "libresoc.v:142561.3-142584.6" wire width 64 $1\stdata_r[63:0] - attribute \src "libresoc.v:142007.3-142015.6" - wire $1\sto_l_r_sto$next[0:0]$6403 - attribute \src "libresoc.v:141675.7-141675.25" + attribute \src "libresoc.v:142347.3-142355.6" + wire $1\sto_l_r_sto$next[0:0]$6335 + attribute \src "libresoc.v:142015.7-142015.25" wire $1\sto_l_r_sto[0:0] - attribute \src "libresoc.v:141998.3-142006.6" - wire $1\upd_l_r_upd$next[0:0]$6400 - attribute \src "libresoc.v:141685.7-141685.25" + attribute \src "libresoc.v:142338.3-142346.6" + wire $1\upd_l_r_upd$next[0:0]$6332 + attribute \src "libresoc.v:142025.7-142025.25" wire $1\upd_l_r_upd[0:0] - attribute \src "libresoc.v:141989.3-141997.6" - wire $1\upd_l_s_upd$next[0:0]$6397 - attribute \src "libresoc.v:141689.7-141689.25" + attribute \src "libresoc.v:142329.3-142337.6" + wire $1\upd_l_s_upd$next[0:0]$6329 + attribute \src "libresoc.v:142029.7-142029.25" wire $1\upd_l_s_upd[0:0] - attribute \src "libresoc.v:141980.3-141988.6" - wire $1\wri_l_r_wri$next[0:0]$6394 - attribute \src "libresoc.v:141699.7-141699.25" + attribute \src "libresoc.v:142320.3-142328.6" + wire $1\wri_l_r_wri$next[0:0]$6326 + attribute \src "libresoc.v:142039.7-142039.25" wire $1\wri_l_r_wri[0:0] - attribute \src "libresoc.v:142201.3-142220.6" + attribute \src "libresoc.v:142541.3-142560.6" wire width 64 $2\ldd_o[63:0] - attribute \src "libresoc.v:142165.3-142188.6" + attribute \src "libresoc.v:142505.3-142528.6" wire width 64 $2\lddata_r[63:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire $2\oper_r__byte_reverse$next[0:0]$6440 - attribute \src "libresoc.v:142025.3-142067.6" - wire width 4 $2\oper_r__data_len$next[3:0]$6441 - attribute \src "libresoc.v:142025.3-142067.6" - wire width 14 $2\oper_r__fn_unit$next[13:0]$6442 - attribute \src "libresoc.v:142025.3-142067.6" - wire width 64 $2\oper_r__imm_data__data$next[63:0]$6443 - attribute \src "libresoc.v:142025.3-142067.6" - wire $2\oper_r__imm_data__ok$next[0:0]$6444 - attribute \src "libresoc.v:142025.3-142067.6" - wire width 32 $2\oper_r__insn$next[31:0]$6445 - attribute \src "libresoc.v:142025.3-142067.6" - wire width 7 $2\oper_r__insn_type$next[6:0]$6446 - attribute \src "libresoc.v:142025.3-142067.6" - wire $2\oper_r__is_32bit$next[0:0]$6447 - attribute \src "libresoc.v:142025.3-142067.6" - wire $2\oper_r__is_signed$next[0:0]$6448 - attribute \src "libresoc.v:142025.3-142067.6" - wire width 2 $2\oper_r__ldst_mode$next[1:0]$6449 - attribute \src "libresoc.v:142025.3-142067.6" - wire $2\oper_r__oe__oe$next[0:0]$6450 - attribute \src "libresoc.v:142025.3-142067.6" - wire $2\oper_r__oe__ok$next[0:0]$6451 - attribute \src "libresoc.v:142025.3-142067.6" - wire $2\oper_r__rc__ok$next[0:0]$6452 - attribute \src "libresoc.v:142025.3-142067.6" - wire $2\oper_r__rc__rc$next[0:0]$6453 - attribute \src "libresoc.v:142025.3-142067.6" - wire $2\oper_r__sign_extend$next[0:0]$6454 - attribute \src "libresoc.v:142025.3-142067.6" - wire $2\oper_r__zero_a$next[0:0]$6455 - attribute \src "libresoc.v:142078.3-142093.6" - wire width 64 $2\src_r0$next[63:0]$6468 - attribute \src "libresoc.v:142094.3-142109.6" - wire width 64 $2\src_r1$next[63:0]$6472 - attribute \src "libresoc.v:142110.3-142125.6" - wire width 64 $2\src_r2$next[63:0]$6476 - attribute \src "libresoc.v:142221.3-142244.6" + attribute \src "libresoc.v:142365.3-142407.6" + wire $2\oper_r__byte_reverse$next[0:0]$6372 + attribute \src "libresoc.v:142365.3-142407.6" + wire width 4 $2\oper_r__data_len$next[3:0]$6373 + attribute \src "libresoc.v:142365.3-142407.6" + wire width 14 $2\oper_r__fn_unit$next[13:0]$6374 + attribute \src "libresoc.v:142365.3-142407.6" + wire width 64 $2\oper_r__imm_data__data$next[63:0]$6375 + attribute \src "libresoc.v:142365.3-142407.6" + wire $2\oper_r__imm_data__ok$next[0:0]$6376 + attribute \src "libresoc.v:142365.3-142407.6" + wire width 32 $2\oper_r__insn$next[31:0]$6377 + attribute \src "libresoc.v:142365.3-142407.6" + wire width 7 $2\oper_r__insn_type$next[6:0]$6378 + attribute \src "libresoc.v:142365.3-142407.6" + wire $2\oper_r__is_32bit$next[0:0]$6379 + attribute \src "libresoc.v:142365.3-142407.6" + wire $2\oper_r__is_signed$next[0:0]$6380 + attribute \src "libresoc.v:142365.3-142407.6" + wire width 2 $2\oper_r__ldst_mode$next[1:0]$6381 + attribute \src "libresoc.v:142365.3-142407.6" + wire $2\oper_r__oe__oe$next[0:0]$6382 + attribute \src "libresoc.v:142365.3-142407.6" + wire $2\oper_r__oe__ok$next[0:0]$6383 + attribute \src "libresoc.v:142365.3-142407.6" + wire $2\oper_r__rc__ok$next[0:0]$6384 + attribute \src "libresoc.v:142365.3-142407.6" + wire $2\oper_r__rc__rc$next[0:0]$6385 + attribute \src "libresoc.v:142365.3-142407.6" + wire $2\oper_r__sign_extend$next[0:0]$6386 + attribute \src "libresoc.v:142365.3-142407.6" + wire $2\oper_r__zero_a$next[0:0]$6387 + attribute \src "libresoc.v:142418.3-142433.6" + wire width 64 $2\src_r0$next[63:0]$6400 + attribute \src "libresoc.v:142434.3-142449.6" + wire width 64 $2\src_r1$next[63:0]$6404 + attribute \src "libresoc.v:142450.3-142465.6" + wire width 64 $2\src_r2$next[63:0]$6408 + attribute \src "libresoc.v:142561.3-142584.6" wire width 64 $2\stdata_r[63:0] - attribute \src "libresoc.v:142025.3-142067.6" - wire width 64 $3\oper_r__imm_data__data$next[63:0]$6456 - attribute \src "libresoc.v:142025.3-142067.6" - wire $3\oper_r__imm_data__ok$next[0:0]$6457 - attribute \src "libresoc.v:142025.3-142067.6" - wire $3\oper_r__oe__oe$next[0:0]$6458 - attribute \src "libresoc.v:142025.3-142067.6" - wire $3\oper_r__oe__ok$next[0:0]$6459 - attribute \src "libresoc.v:142025.3-142067.6" - wire $3\oper_r__rc__ok$next[0:0]$6460 - attribute \src "libresoc.v:142025.3-142067.6" - wire $3\oper_r__rc__rc$next[0:0]$6461 - attribute \src "libresoc.v:141781.18-141781.124" - wire width 65 $add$libresoc.v:141781$6328_Y - attribute \src "libresoc.v:141704.19-141704.118" - wire $and$libresoc.v:141704$6248_Y - attribute \src "libresoc.v:141705.19-141705.125" - wire $and$libresoc.v:141705$6249_Y - attribute \src "libresoc.v:141706.19-141706.120" - wire $and$libresoc.v:141706$6250_Y - attribute \src "libresoc.v:141707.19-141707.125" - wire $and$libresoc.v:141707$6251_Y - attribute \src "libresoc.v:141708.19-141708.118" - wire $and$libresoc.v:141708$6252_Y - attribute \src "libresoc.v:141710.19-141710.119" - wire $and$libresoc.v:141710$6254_Y - attribute \src "libresoc.v:141711.19-141711.123" - wire $and$libresoc.v:141711$6255_Y - attribute \src "libresoc.v:141712.19-141712.123" - wire $and$libresoc.v:141712$6256_Y - attribute \src "libresoc.v:141713.19-141713.120" - wire $and$libresoc.v:141713$6257_Y - attribute \src "libresoc.v:141714.19-141714.123" - wire $and$libresoc.v:141714$6258_Y - attribute \src "libresoc.v:141715.19-141715.119" - wire $and$libresoc.v:141715$6259_Y - attribute \src "libresoc.v:141716.19-141716.123" - wire $and$libresoc.v:141716$6260_Y - attribute \src "libresoc.v:141717.19-141717.125" - wire $and$libresoc.v:141717$6261_Y - attribute \src "libresoc.v:141719.19-141719.116" - wire $and$libresoc.v:141719$6263_Y - attribute \src "libresoc.v:141721.19-141721.120" - wire $and$libresoc.v:141721$6265_Y - attribute \src "libresoc.v:141722.19-141722.123" - wire $and$libresoc.v:141722$6266_Y - attribute \src "libresoc.v:141726.19-141726.125" - wire $and$libresoc.v:141726$6270_Y - attribute \src "libresoc.v:141727.19-141727.123" - wire $and$libresoc.v:141727$6271_Y - attribute \src "libresoc.v:141732.19-141732.116" - wire $and$libresoc.v:141732$6276_Y - attribute \src "libresoc.v:141734.19-141734.116" - wire $and$libresoc.v:141734$6278_Y - attribute \src "libresoc.v:141737.19-141737.118" - wire $and$libresoc.v:141737$6281_Y - attribute \src "libresoc.v:141739.19-141739.125" - wire $and$libresoc.v:141739$6283_Y - attribute \src "libresoc.v:141742.19-141742.160" - wire width 3 $and$libresoc.v:141742$6286_Y - attribute \src "libresoc.v:141743.19-141743.122" - wire $and$libresoc.v:141743$6287_Y - attribute \src "libresoc.v:141744.19-141744.122" - wire $and$libresoc.v:141744$6288_Y - attribute \src "libresoc.v:141746.19-141746.122" - wire $and$libresoc.v:141746$6291_Y - attribute \src "libresoc.v:141758.18-141758.123" - wire $and$libresoc.v:141758$6305_Y - attribute \src "libresoc.v:141759.18-141759.123" - wire $and$libresoc.v:141759$6306_Y - attribute \src "libresoc.v:141761.18-141761.114" - wire $and$libresoc.v:141761$6308_Y - attribute \src "libresoc.v:141763.18-141763.113" - wire $and$libresoc.v:141763$6310_Y - attribute \src "libresoc.v:141766.18-141766.113" - wire $and$libresoc.v:141766$6313_Y - attribute \src "libresoc.v:141770.18-141770.113" - wire $and$libresoc.v:141770$6317_Y - attribute \src "libresoc.v:141773.18-141773.119" - wire $and$libresoc.v:141773$6320_Y - attribute \src "libresoc.v:141782.18-141782.150" - wire width 3 $and$libresoc.v:141782$6329_Y - attribute \src "libresoc.v:141784.18-141784.113" - wire width 3 $and$libresoc.v:141784$6331_Y - attribute \src "libresoc.v:141786.18-141786.113" - wire width 3 $and$libresoc.v:141786$6333_Y - attribute \src "libresoc.v:141787.18-141787.127" - wire $and$libresoc.v:141787$6334_Y - attribute \src "libresoc.v:141788.18-141788.117" - wire $and$libresoc.v:141788$6335_Y - attribute \src "libresoc.v:141793.18-141793.117" - wire $and$libresoc.v:141793$6340_Y - attribute \src "libresoc.v:141718.19-141718.127" - wire $eq$libresoc.v:141718$6262_Y - attribute \src "libresoc.v:141738.19-141738.127" - wire $eq$libresoc.v:141738$6282_Y - attribute \src "libresoc.v:141740.19-141740.127" - wire $eq$libresoc.v:141740$6284_Y - attribute \src "libresoc.v:141751.19-141751.126" - wire $eq$libresoc.v:141751$6297_Y - attribute \src "libresoc.v:141756.18-141756.127" - wire $eq$libresoc.v:141756$6303_Y - attribute \src "libresoc.v:141757.18-141757.127" - wire $eq$libresoc.v:141757$6304_Y - attribute \src "libresoc.v:141765.18-141765.126" - wire $eq$libresoc.v:141765$6312_Y - attribute \src "libresoc.v:141769.18-141769.126" - wire $eq$libresoc.v:141769$6316_Y - attribute \src "libresoc.v:141745.19-141745.110" - wire width 96 $extend$libresoc.v:141745$6289_Y - attribute \src "libresoc.v:141747.19-141747.116" - wire width 64 $extend$libresoc.v:141747$6292_Y - attribute \src "libresoc.v:141752.19-141752.102" - wire width 64 $extend$libresoc.v:141752$6298_Y - attribute \src "libresoc.v:141730.19-141730.109" - wire $not$libresoc.v:141730$6274_Y - attribute \src "libresoc.v:141735.19-141735.121" - wire $not$libresoc.v:141735$6279_Y - attribute \src "libresoc.v:141760.18-141760.112" - wire $not$libresoc.v:141760$6307_Y - attribute \src "libresoc.v:141762.18-141762.110" - wire $not$libresoc.v:141762$6309_Y - attribute \src "libresoc.v:141764.18-141764.120" - wire $not$libresoc.v:141764$6311_Y - attribute \src "libresoc.v:141768.18-141768.120" - wire $not$libresoc.v:141768$6315_Y - attribute \src "libresoc.v:141783.18-141783.143" - wire width 2 $not$libresoc.v:141783$6330_Y - attribute \src "libresoc.v:141785.18-141785.115" - wire width 3 $not$libresoc.v:141785$6332_Y - attribute \src "libresoc.v:141792.18-141792.107" - wire $not$libresoc.v:141792$6339_Y - attribute \src "libresoc.v:141794.18-141794.118" - wire $not$libresoc.v:141794$6341_Y - attribute \src "libresoc.v:141709.18-141709.124" - wire $or$libresoc.v:141709$6253_Y - attribute \src "libresoc.v:141720.18-141720.129" - wire $or$libresoc.v:141720$6264_Y - attribute \src "libresoc.v:141723.19-141723.123" - wire $or$libresoc.v:141723$6267_Y - attribute \src "libresoc.v:141724.19-141724.125" - wire $or$libresoc.v:141724$6268_Y - attribute \src "libresoc.v:141725.19-141725.125" - wire $or$libresoc.v:141725$6269_Y - attribute \src "libresoc.v:141728.19-141728.132" - wire $or$libresoc.v:141728$6272_Y - attribute \src "libresoc.v:141729.19-141729.126" - wire $or$libresoc.v:141729$6273_Y - attribute \src "libresoc.v:141731.18-141731.129" - wire $or$libresoc.v:141731$6275_Y - attribute \src "libresoc.v:141733.19-141733.125" - wire $or$libresoc.v:141733$6277_Y - attribute \src "libresoc.v:141736.19-141736.119" - wire $or$libresoc.v:141736$6280_Y - attribute \src "libresoc.v:141741.18-141741.126" - wire $or$libresoc.v:141741$6285_Y - attribute \src "libresoc.v:141749.18-141749.156" - wire width 3 $or$libresoc.v:141749$6295_Y - attribute \src "libresoc.v:141755.18-141755.126" - wire $or$libresoc.v:141755$6302_Y - attribute \src "libresoc.v:141767.18-141767.116" - wire $or$libresoc.v:141767$6314_Y - attribute \src "libresoc.v:141771.18-141771.116" - wire $or$libresoc.v:141771$6318_Y - attribute \src "libresoc.v:141772.18-141772.127" - wire width 2 $or$libresoc.v:141772$6319_Y - attribute \src "libresoc.v:141774.18-141774.118" - wire $or$libresoc.v:141774$6321_Y - attribute \src "libresoc.v:141775.18-141775.118" - wire $or$libresoc.v:141775$6322_Y - attribute \src "libresoc.v:141776.18-141776.114" - wire $or$libresoc.v:141776$6323_Y - attribute \src "libresoc.v:141789.17-141789.124" - wire $or$libresoc.v:141789$6336_Y - attribute \src "libresoc.v:141790.18-141790.132" - wire $or$libresoc.v:141790$6337_Y - attribute \src "libresoc.v:141791.18-141791.134" - wire $or$libresoc.v:141791$6338_Y - attribute \src "libresoc.v:141745.19-141745.110" - wire width 96 $pos$libresoc.v:141745$6290_Y - attribute \src "libresoc.v:141747.19-141747.116" - wire width 64 $pos$libresoc.v:141747$6293_Y - attribute \src "libresoc.v:141748.19-141748.148" - wire width 64 $pos$libresoc.v:141748$6294_Y - attribute \src "libresoc.v:141750.19-141750.206" - wire width 64 $pos$libresoc.v:141750$6296_Y - attribute \src "libresoc.v:141752.19-141752.102" - wire width 64 $pos$libresoc.v:141752$6299_Y - attribute \src "libresoc.v:141753.19-141753.120" - wire width 64 $pos$libresoc.v:141753$6300_Y - attribute \src "libresoc.v:141754.19-141754.150" - wire width 64 $pos$libresoc.v:141754$6301_Y - attribute \src "libresoc.v:141777.18-141777.107" - wire width 64 $ternary$libresoc.v:141777$6324_Y - attribute \src "libresoc.v:141778.18-141778.112" - wire width 64 $ternary$libresoc.v:141778$6325_Y - attribute \src "libresoc.v:141779.18-141779.147" - wire width 64 $ternary$libresoc.v:141779$6326_Y - attribute \src "libresoc.v:141780.18-141780.155" - wire width 64 $ternary$libresoc.v:141780$6327_Y + attribute \src "libresoc.v:142365.3-142407.6" + wire width 64 $3\oper_r__imm_data__data$next[63:0]$6388 + attribute \src "libresoc.v:142365.3-142407.6" + wire $3\oper_r__imm_data__ok$next[0:0]$6389 + attribute \src "libresoc.v:142365.3-142407.6" + wire $3\oper_r__oe__oe$next[0:0]$6390 + attribute \src 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wire $or$libresoc.v:142107$6246_Y + attribute \src "libresoc.v:142111.18-142111.116" + wire $or$libresoc.v:142111$6250_Y + attribute \src "libresoc.v:142112.18-142112.127" + wire width 2 $or$libresoc.v:142112$6251_Y + attribute \src "libresoc.v:142114.18-142114.118" + wire $or$libresoc.v:142114$6253_Y + attribute \src "libresoc.v:142115.18-142115.118" + wire $or$libresoc.v:142115$6254_Y + attribute \src "libresoc.v:142116.18-142116.114" + wire $or$libresoc.v:142116$6255_Y + attribute \src "libresoc.v:142129.17-142129.124" + wire $or$libresoc.v:142129$6268_Y + attribute \src "libresoc.v:142130.18-142130.132" + wire $or$libresoc.v:142130$6269_Y + attribute \src "libresoc.v:142131.18-142131.134" + wire $or$libresoc.v:142131$6270_Y + attribute \src "libresoc.v:142085.19-142085.110" + wire width 96 $pos$libresoc.v:142085$6222_Y + attribute \src "libresoc.v:142087.19-142087.116" + wire width 64 $pos$libresoc.v:142087$6225_Y + attribute \src "libresoc.v:142088.19-142088.148" + wire width 64 $pos$libresoc.v:142088$6226_Y + attribute \src "libresoc.v:142090.19-142090.206" + wire width 64 $pos$libresoc.v:142090$6228_Y + attribute \src "libresoc.v:142092.19-142092.102" + wire width 64 $pos$libresoc.v:142092$6231_Y + attribute \src "libresoc.v:142093.19-142093.120" + wire width 64 $pos$libresoc.v:142093$6232_Y + attribute \src "libresoc.v:142094.19-142094.150" + wire width 64 $pos$libresoc.v:142094$6233_Y + attribute \src "libresoc.v:142117.18-142117.107" + wire width 64 $ternary$libresoc.v:142117$6256_Y + attribute \src "libresoc.v:142118.18-142118.112" + wire width 64 $ternary$libresoc.v:142118$6257_Y + attribute \src "libresoc.v:142119.18-142119.147" + wire width 64 $ternary$libresoc.v:142119$6258_Y + attribute \src "libresoc.v:142120.18-142120.155" + wire width 64 $ternary$libresoc.v:142120$6259_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" @@ -226723,9 +226168,9 @@ module \ldst0 wire \alu_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" wire \alu_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 3 \cu_ad__go_i @@ -226761,7 +226206,7 @@ module \ldst0 wire width 64 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 33 \ea attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \ea_r @@ -226783,7 +226228,7 @@ module \ldst0 wire \exc_$signal$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$185 - attribute \src "libresoc.v:140954.7-140954.15" + attribute \src "libresoc.v:141294.7-141294.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" wire \ld_o @@ -226799,13 +226244,13 @@ module \ldst0 wire width 64 \ldo_r attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \ldo_r$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 96 output 38 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 96 \ldst_port0_addr_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 39 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \ldst_port0_addr_i_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire input 48 \ldst_port0_addr_ok_o @@ -226833,13 +226278,13 @@ module \ldst0 wire output 35 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire output 36 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 49 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 50 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 51 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 52 \ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" wire \load_mem_o @@ -226857,7 +226302,7 @@ module \ldst0 wire \lsd_l_r_lsd$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \lsd_l_s_lsd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 32 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" wire \op_is_ld @@ -227190,15 +226635,15 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 27 \src1_i + wire width 64 input 29 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" wire width 64 \src1_or_z attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 28 \src2_i + wire width 64 input 27 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" wire width 64 \src2_or_imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 29 \src3_i + wire width 64 input 28 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" @@ -227258,7 +226703,7 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \wri_l_s_wri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" - cell $add $add$libresoc.v:141781$6328 + cell $add $add$libresoc.v:142121$6260 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -227266,10 +226711,10 @@ module \ldst0 parameter \Y_WIDTH 65 connect \A \src1_or_z connect \B \src2_or_imm - connect \Y $add$libresoc.v:141781$6328_Y + connect \Y $add$libresoc.v:142121$6260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $and $and$libresoc.v:141704$6248 + cell $and $and$libresoc.v:142044$6180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227277,10 +226722,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \$98 - connect \Y $and$libresoc.v:141704$6248_Y + connect \Y $and$libresoc.v:142044$6180_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:141705$6249 + cell $and $and$libresoc.v:142045$6181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227288,10 +226733,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \adr_l_q_adr - connect \Y $and$libresoc.v:141705$6249_Y + connect \Y $and$libresoc.v:142045$6181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:141706$6250 + cell $and $and$libresoc.v:142046$6182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227299,10 +226744,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$102 connect \B \cu_busy_o - connect \Y $and$libresoc.v:141706$6250_Y + connect \Y $and$libresoc.v:142046$6182_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:141707$6251 + cell $and $and$libresoc.v:142047$6183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227310,10 +226755,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \sto_l_q_sto connect \B \cu_busy_o - connect \Y $and$libresoc.v:141707$6251_Y + connect \Y $and$libresoc.v:142047$6183_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:141708$6252 + cell $and $and$libresoc.v:142048$6184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227321,10 +226766,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$106 connect \B \rd_done - connect \Y $and$libresoc.v:141708$6252_Y + connect \Y $and$libresoc.v:142048$6184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:141710$6254 + cell $and $and$libresoc.v:142050$6186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227332,10 +226777,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$108 connect \B \op_is_st - connect \Y $and$libresoc.v:141710$6254_Y + connect \Y $and$libresoc.v:142050$6186_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - cell $and $and$libresoc.v:141711$6255 + cell $and $and$libresoc.v:142051$6187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227343,10 +226788,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$110 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141711$6255_Y + connect \Y $and$libresoc.v:142051$6187_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141712$6256 + cell $and $and$libresoc.v:142052$6188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227354,10 +226799,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rd_done connect \B \wri_l_q_wri - connect \Y $and$libresoc.v:141712$6256_Y + connect \Y $and$libresoc.v:142052$6188_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141713$6257 + cell $and $and$libresoc.v:142053$6189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227365,10 +226810,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$114 connect \B \cu_busy_o - connect \Y $and$libresoc.v:141713$6257_Y + connect \Y $and$libresoc.v:142053$6189_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141714$6258 + cell $and $and$libresoc.v:142054$6190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227376,10 +226821,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$116 connect \B \lod_l_qn_lod - connect \Y $and$libresoc.v:141714$6258_Y + connect \Y $and$libresoc.v:142054$6190_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141715$6259 + cell $and $and$libresoc.v:142055$6191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227387,10 +226832,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$118 connect \B \op_is_ld - connect \Y $and$libresoc.v:141715$6259_Y + connect \Y $and$libresoc.v:142055$6191_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141716$6260 + cell $and $and$libresoc.v:142056$6192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227398,10 +226843,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$120 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141716$6260_Y + connect \Y $and$libresoc.v:142056$6192_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:141717$6261 + cell $and $and$libresoc.v:142057$6193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227409,10 +226854,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \upd_l_q_upd connect \B \cu_busy_o - connect \Y $and$libresoc.v:141717$6261_Y + connect \Y $and$libresoc.v:142057$6193_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:141719$6263 + cell $and $and$libresoc.v:142059$6195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227420,10 +226865,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$124 connect \B \$126 - connect \Y $and$libresoc.v:141719$6263_Y + connect \Y $and$libresoc.v:142059$6195_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:141721$6265 + cell $and $and$libresoc.v:142061$6197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227431,10 +226876,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$128 connect \B \alu_valid - connect \Y $and$libresoc.v:141721$6265_Y + connect \Y $and$libresoc.v:142061$6197_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:141722$6266 + cell $and $and$libresoc.v:142062$6198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227442,10 +226887,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$130 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141722$6266_Y + connect \Y $and$libresoc.v:142062$6198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:141726$6270 + cell $and $and$libresoc.v:142066$6202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227453,10 +226898,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rst_l_q_rst connect \B \cu_busy_o - connect \Y $and$libresoc.v:141726$6270_Y + connect \Y $and$libresoc.v:142066$6202_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:141727$6271 + cell $and $and$libresoc.v:142067$6203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227464,10 +226909,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$140 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141727$6271_Y + connect \Y $and$libresoc.v:142067$6203_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:141732$6276 + cell $and $and$libresoc.v:142072$6208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227475,10 +226920,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$142 connect \B \$144 - connect \Y $and$libresoc.v:141732$6276_Y + connect \Y $and$libresoc.v:142072$6208_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $and $and$libresoc.v:141734$6278 + cell $and $and$libresoc.v:142074$6210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227486,10 +226931,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$150 connect \B \$152 - connect \Y $and$libresoc.v:141734$6278_Y + connect \Y $and$libresoc.v:142074$6210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $and $and$libresoc.v:141737$6281 + cell $and $and$libresoc.v:142077$6213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227497,10 +226942,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$158 - connect \Y $and$libresoc.v:141737$6281_Y + connect \Y $and$libresoc.v:142077$6213_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" - cell $and $and$libresoc.v:141739$6283 + cell $and $and$libresoc.v:142079$6215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227508,10 +226953,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$162 connect \B \cu_wr__go_i [1] - connect \Y $and$libresoc.v:141739$6283_Y + connect \Y $and$libresoc.v:142079$6215_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" - cell $and $and$libresoc.v:141742$6286 + cell $and $and$libresoc.v:142082$6218 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227519,10 +226964,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } connect \B { 1'0 \$167 \op_is_ld } - connect \Y $and$libresoc.v:141742$6286_Y + connect \Y $and$libresoc.v:142082$6218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" - cell $and $and$libresoc.v:141743$6287 + cell $and $and$libresoc.v:142083$6219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227530,10 +226975,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_busy_o - connect \Y $and$libresoc.v:141743$6287_Y + connect \Y $and$libresoc.v:142083$6219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" - cell $and $and$libresoc.v:141744$6288 + cell $and $and$libresoc.v:142084$6220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227541,10 +226986,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_busy_o - connect \Y $and$libresoc.v:141744$6288_Y + connect \Y $and$libresoc.v:142084$6220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" - cell $and $and$libresoc.v:141746$6291 + cell $and $and$libresoc.v:142086$6223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227552,10 +226997,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \lsd_l_q_lsd - connect \Y $and$libresoc.v:141746$6291_Y + connect \Y $and$libresoc.v:142086$6223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" - cell $and $and$libresoc.v:141758$6305 + cell $and $and$libresoc.v:142098$6237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227563,10 +227008,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_ad__go_i - connect \Y $and$libresoc.v:141758$6305_Y + connect \Y $and$libresoc.v:142098$6237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" - cell $and $and$libresoc.v:141759$6306 + cell $and $and$libresoc.v:142099$6238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227574,10 +227019,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_st__go_i - connect \Y $and$libresoc.v:141759$6306_Y + connect \Y $and$libresoc.v:142099$6238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:141761$6308 + cell $and $and$libresoc.v:142101$6240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227585,10 +227030,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \$30 - connect \Y $and$libresoc.v:141761$6308_Y + connect \Y $and$libresoc.v:142101$6240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:141763$6310 + cell $and $and$libresoc.v:142103$6242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227596,10 +227041,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $and$libresoc.v:141763$6310_Y + connect \Y $and$libresoc.v:142103$6242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:141766$6313 + cell $and $and$libresoc.v:142106$6245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227607,10 +227052,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$41 - connect \Y $and$libresoc.v:141766$6313_Y + connect \Y $and$libresoc.v:142106$6245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:141770$6317 + cell $and $and$libresoc.v:142110$6249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227618,10 +227063,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \$49 - connect \Y $and$libresoc.v:141770$6317_Y + connect \Y $and$libresoc.v:142110$6249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" - cell $and $and$libresoc.v:141773$6320 + cell $and $and$libresoc.v:142113$6252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227629,10 +227074,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \addr_ok connect \B \op_is_st - connect \Y $and$libresoc.v:141773$6320_Y + connect \Y $and$libresoc.v:142113$6252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:141782$6329 + cell $and $and$libresoc.v:142122$6261 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227640,10 +227085,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:141782$6329_Y + connect \Y $and$libresoc.v:142122$6261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:141784$6331 + cell $and $and$libresoc.v:142124$6263 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227651,10 +227096,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$76 connect \B \$78 - connect \Y $and$libresoc.v:141784$6331_Y + connect \Y $and$libresoc.v:142124$6263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:141786$6333 + cell $and $and$libresoc.v:142126$6265 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227662,10 +227107,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$80 connect \B \$82 - connect \Y $and$libresoc.v:141786$6333_Y + connect \Y $and$libresoc.v:142126$6265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:141787$6334 + cell $and $and$libresoc.v:142127$6266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227673,10 +227118,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \src_l_q_src [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:141787$6334_Y + connect \Y $and$libresoc.v:142127$6266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:141788$6335 + cell $and $and$libresoc.v:142128$6267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227684,10 +227129,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$86 connect \B \op_is_st - connect \Y $and$libresoc.v:141788$6335_Y + connect \Y $and$libresoc.v:142128$6267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $and $and$libresoc.v:141793$6340 + cell $and $and$libresoc.v:142133$6272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227695,10 +227140,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$92 - connect \Y $and$libresoc.v:141793$6340_Y + connect \Y $and$libresoc.v:142133$6272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141718$6262 + cell $eq $eq$libresoc.v:142058$6194 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227706,10 +227151,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141718$6262_Y + connect \Y $eq$libresoc.v:142058$6194_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141738$6282 + cell $eq $eq$libresoc.v:142078$6214 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227717,10 +227162,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141738$6282_Y + connect \Y $eq$libresoc.v:142078$6214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141740$6284 + cell $eq $eq$libresoc.v:142080$6216 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227728,10 +227173,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141740$6284_Y + connect \Y $eq$libresoc.v:142080$6216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" - cell $eq $eq$libresoc.v:141751$6297 + cell $eq $eq$libresoc.v:142091$6229 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -227739,10 +227184,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:141751$6297_Y + connect \Y $eq$libresoc.v:142091$6229_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - cell $eq $eq$libresoc.v:141756$6303 + cell $eq $eq$libresoc.v:142096$6235 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227750,10 +227195,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100110 - connect \Y $eq$libresoc.v:141756$6303_Y + connect \Y $eq$libresoc.v:142096$6235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$libresoc.v:141757$6304 + cell $eq $eq$libresoc.v:142097$6236 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227761,10 +227206,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100101 - connect \Y $eq$libresoc.v:141757$6304_Y + connect \Y $eq$libresoc.v:142097$6236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141765$6312 + cell $eq $eq$libresoc.v:142105$6244 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227772,10 +227217,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141765$6312_Y + connect \Y $eq$libresoc.v:142105$6244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141769$6316 + cell $eq $eq$libresoc.v:142109$6248 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227783,114 +227228,114 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141769$6316_Y + connect \Y $eq$libresoc.v:142109$6248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $extend$libresoc.v:141745$6289 + cell $pos $extend$libresoc.v:142085$6221 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 96 connect \A \addr_r - connect \Y $extend$libresoc.v:141745$6289_Y + connect \Y $extend$libresoc.v:142085$6221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $extend$libresoc.v:141747$6292 + cell $pos $extend$libresoc.v:142087$6224 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \ldst_port0_ld_data_o [7:0] - connect \Y $extend$libresoc.v:141747$6292_Y + connect \Y $extend$libresoc.v:142087$6224_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $extend$libresoc.v:141752$6298 + cell $pos $extend$libresoc.v:142092$6230 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \src_r2 [7:0] - connect \Y $extend$libresoc.v:141752$6298_Y + connect \Y $extend$libresoc.v:142092$6230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $not $not$libresoc.v:141730$6274 + cell $not $not$libresoc.v:142070$6206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$147 - connect \Y $not$libresoc.v:141730$6274_Y + connect \Y $not$libresoc.v:142070$6206_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $not $not$libresoc.v:141735$6279 + cell $not $not$libresoc.v:142075$6211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:141735$6279_Y + connect \Y $not$libresoc.v:142075$6211_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:141760$6307 + cell $not $not$libresoc.v:142100$6239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_valid - connect \Y $not$libresoc.v:141760$6307_Y + connect \Y $not$libresoc.v:142100$6239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:141762$6309 + cell $not $not$libresoc.v:142102$6241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rda_any - connect \Y $not$libresoc.v:141762$6309_Y + connect \Y $not$libresoc.v:142102$6241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:141764$6311 + cell $not $not$libresoc.v:142104$6243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:141764$6311_Y + connect \Y $not$libresoc.v:142104$6243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:141768$6315 + cell $not $not$libresoc.v:142108$6247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:141768$6315_Y + connect \Y $not$libresoc.v:142108$6247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:141783$6330 + cell $not $not$libresoc.v:142123$6262 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A { \oper_r__imm_data__ok \oper_r__zero_a } - connect \Y $not$libresoc.v:141783$6330_Y + connect \Y $not$libresoc.v:142123$6262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:141785$6332 + cell $not $not$libresoc.v:142125$6264 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:141785$6332_Y + connect \Y $not$libresoc.v:142125$6264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $not $not$libresoc.v:141792$6339 + cell $not $not$libresoc.v:142132$6271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$93 - connect \Y $not$libresoc.v:141792$6339_Y + connect \Y $not$libresoc.v:142132$6271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $not $not$libresoc.v:141794$6341 + cell $not $not$libresoc.v:142134$6273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [2] - connect \Y $not$libresoc.v:141794$6341_Y + connect \Y $not$libresoc.v:142134$6273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - cell $or $or$libresoc.v:141709$6253 + cell $or $or$libresoc.v:142049$6185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227898,10 +227343,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_done_o connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141709$6253_Y + connect \Y $or$libresoc.v:142049$6185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - cell $or $or$libresoc.v:141720$6264 + cell $or $or$libresoc.v:142060$6196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227909,10 +227354,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141720$6264_Y + connect \Y $or$libresoc.v:142060$6196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:141723$6267 + cell $or $or$libresoc.v:142063$6199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227920,10 +227365,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \p_st_go - connect \Y $or$libresoc.v:141723$6267_Y + connect \Y $or$libresoc.v:142063$6199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:141724$6268 + cell $or $or$libresoc.v:142064$6200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227931,10 +227376,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$134 connect \B \cu_wr__go_i [0] - connect \Y $or$libresoc.v:141724$6268_Y + connect \Y $or$libresoc.v:142064$6200_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:141725$6269 + cell $or $or$libresoc.v:142065$6201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227942,10 +227387,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$136 connect \B \cu_wr__go_i [1] - connect \Y $or$libresoc.v:141725$6269_Y + connect \Y $or$libresoc.v:142065$6201_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:141728$6272 + cell $or $or$libresoc.v:142068$6204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227953,10 +227398,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o connect \B \cu_wr__rel_o [0] - connect \Y $or$libresoc.v:141728$6272_Y + connect \Y $or$libresoc.v:142068$6204_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:141729$6273 + cell $or $or$libresoc.v:142069$6205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227964,10 +227409,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$145 connect \B \cu_wr__rel_o [1] - connect \Y $or$libresoc.v:141729$6273_Y + connect \Y $or$libresoc.v:142069$6205_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - cell $or $or$libresoc.v:141731$6275 + cell $or $or$libresoc.v:142071$6207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227975,10 +227420,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141731$6275_Y + connect \Y $or$libresoc.v:142071$6207_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $or $or$libresoc.v:141733$6277 + cell $or $or$libresoc.v:142073$6209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227986,10 +227431,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \lod_l_qn_lod connect \B \op_is_st - connect \Y $or$libresoc.v:141733$6277_Y + connect \Y $or$libresoc.v:142073$6209_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $or $or$libresoc.v:141736$6280 + cell $or $or$libresoc.v:142076$6212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227997,10 +227442,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$156 connect \B \op_is_ld - connect \Y $or$libresoc.v:141736$6280_Y + connect \Y $or$libresoc.v:142076$6212_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - cell $or $or$libresoc.v:141741$6285 + cell $or $or$libresoc.v:142081$6217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228008,10 +227453,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141741$6285_Y + connect \Y $or$libresoc.v:142081$6217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" - cell $or $or$libresoc.v:141749$6295 + cell $or $or$libresoc.v:142089$6227 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -228019,10 +227464,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:141749$6295_Y + connect \Y $or$libresoc.v:142089$6227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" - cell $or $or$libresoc.v:141755$6302 + cell $or $or$libresoc.v:142095$6234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228030,10 +227475,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_ad__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141755$6302_Y + connect \Y $or$libresoc.v:142095$6234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:141767$6314 + cell $or $or$libresoc.v:142107$6246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228041,10 +227486,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$43 - connect \Y $or$libresoc.v:141767$6314_Y + connect \Y $or$libresoc.v:142107$6246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:141771$6318 + cell $or $or$libresoc.v:142111$6250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228052,10 +227497,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$51 - connect \Y $or$libresoc.v:141771$6318_Y + connect \Y $or$libresoc.v:142111$6250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" - cell $or $or$libresoc.v:141772$6319 + cell $or $or$libresoc.v:142112$6251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228063,10 +227508,10 @@ module \ldst0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B { \$45 \$53 } - connect \Y $or$libresoc.v:141772$6319_Y + connect \Y $or$libresoc.v:142112$6251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" - cell $or $or$libresoc.v:141774$6321 + cell $or $or$libresoc.v:142114$6253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228074,10 +227519,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:141774$6321_Y + connect \Y $or$libresoc.v:142114$6253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:141775$6322 + cell $or $or$libresoc.v:142115$6254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228085,10 +227530,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:141775$6322_Y + connect \Y $or$libresoc.v:142115$6254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:141776$6323 + cell $or $or$libresoc.v:142116$6255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228096,10 +227541,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$61 connect \B \ld_ok - connect \Y $or$libresoc.v:141776$6323_Y + connect \Y $or$libresoc.v:142116$6255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - cell $or $or$libresoc.v:141789$6336 + cell $or $or$libresoc.v:142129$6268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228107,10 +227552,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141789$6336_Y + connect \Y $or$libresoc.v:142129$6268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" - cell $or $or$libresoc.v:141790$6337 + cell $or $or$libresoc.v:142130$6269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228118,10 +227563,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__go_i [0] connect \B \cu_rd__go_i [1] - connect \Y $or$libresoc.v:141790$6337_Y + connect \Y $or$libresoc.v:142130$6269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $or $or$libresoc.v:141791$6338 + cell $or $or$libresoc.v:142131$6270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228129,98 +227574,98 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [0] connect \B \cu_rd__rel_o [1] - connect \Y $or$libresoc.v:141791$6338_Y + connect \Y $or$libresoc.v:142131$6270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $pos$libresoc.v:141745$6290 + cell $pos $pos$libresoc.v:142085$6222 parameter \A_SIGNED 0 parameter \A_WIDTH 96 parameter \Y_WIDTH 96 - connect \A $extend$libresoc.v:141745$6289_Y - connect \Y $pos$libresoc.v:141745$6290_Y + connect \A $extend$libresoc.v:142085$6221_Y + connect \Y $pos$libresoc.v:142085$6222_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141747$6293 + cell $pos $pos$libresoc.v:142087$6225 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:141747$6292_Y - connect \Y $pos$libresoc.v:141747$6293_Y + connect \A $extend$libresoc.v:142087$6224_Y + connect \Y $pos$libresoc.v:142087$6225_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141748$6294 + cell $pos $pos$libresoc.v:142088$6226 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } - connect \Y $pos$libresoc.v:141748$6294_Y + connect \Y $pos$libresoc.v:142088$6226_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141750$6296 + cell $pos $pos$libresoc.v:142090$6228 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } - connect \Y $pos$libresoc.v:141750$6296_Y + connect \Y $pos$libresoc.v:142090$6228_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141752$6299 + cell $pos $pos$libresoc.v:142092$6231 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:141752$6298_Y - connect \Y $pos$libresoc.v:141752$6299_Y + connect \A $extend$libresoc.v:142092$6230_Y + connect \Y $pos$libresoc.v:142092$6231_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141753$6300 + cell $pos $pos$libresoc.v:142093$6232 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } - connect \Y $pos$libresoc.v:141753$6300_Y + connect \Y $pos$libresoc.v:142093$6232_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141754$6301 + cell $pos $pos$libresoc.v:142094$6233 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } - connect \Y $pos$libresoc.v:141754$6301_Y + connect \Y $pos$libresoc.v:142094$6233_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:141777$6324 + cell $mux $ternary$libresoc.v:142117$6256 parameter \WIDTH 64 connect \A \ldo_r connect \B \ldd_o connect \S \ld_ok - connect \Y $ternary$libresoc.v:141777$6324_Y + connect \Y $ternary$libresoc.v:142117$6256_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:141778$6325 + cell $mux $ternary$libresoc.v:142118$6257 parameter \WIDTH 64 connect \A \ea_r connect \B \alu_o connect \S \alu_l_q_alu - connect \Y $ternary$libresoc.v:141778$6325_Y + connect \Y $ternary$libresoc.v:142118$6257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" - cell $mux $ternary$libresoc.v:141779$6326 + cell $mux $ternary$libresoc.v:142119$6258 parameter \WIDTH 64 connect \A \src_r0 connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \oper_r__zero_a - connect \Y $ternary$libresoc.v:141779$6326_Y + connect \Y $ternary$libresoc.v:142119$6258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" - cell $mux $ternary$libresoc.v:141780$6327 + cell $mux $ternary$libresoc.v:142120$6259 parameter \WIDTH 64 connect \A \src_r1 connect \B \oper_r__imm_data__data connect \S \oper_r__imm_data__ok - connect \Y $ternary$libresoc.v:141780$6327_Y + connect \Y $ternary$libresoc.v:142120$6259_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:141865.9-141871.4" + attribute \src "libresoc.v:142205.9-142211.4" cell \adr_l \adr_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228229,7 +227674,7 @@ module \ldst0 connect \s_adr \adr_l_s_adr end attribute \module_not_derived 1 - attribute \src "libresoc.v:141872.15-141878.4" + attribute \src "libresoc.v:142212.15-142218.4" cell \alu_l$128 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228238,7 +227683,7 @@ module \ldst0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:141879.9-141885.4" + attribute \src "libresoc.v:142219.9-142225.4" cell \lod_l \lod_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228247,7 +227692,7 @@ module \ldst0 connect \s_lod \lod_l_s_lod end attribute \module_not_derived 1 - attribute \src "libresoc.v:141886.9-141892.4" + attribute \src "libresoc.v:142226.9-142232.4" cell \lsd_l \lsd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228256,7 +227701,7 @@ module \ldst0 connect \s_lsd \lsd_l_s_lsd end attribute \module_not_derived 1 - attribute \src "libresoc.v:141893.15-141899.4" + attribute \src "libresoc.v:142233.15-142239.4" cell \opc_l$126 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228265,7 +227710,7 @@ module \ldst0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:141900.15-141906.4" + attribute \src "libresoc.v:142240.15-142246.4" cell \rst_l$129 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228274,7 +227719,7 @@ module \ldst0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:141907.15-141913.4" + attribute \src "libresoc.v:142247.15-142253.4" cell \src_l$127 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228283,7 +227728,7 @@ module \ldst0 connect \s_src \src_l_s_src end attribute \module_not_derived 1 - attribute \src "libresoc.v:141914.9-141920.4" + attribute \src "libresoc.v:142254.9-142260.4" cell \sto_l \sto_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228292,7 +227737,7 @@ module \ldst0 connect \s_sto \sto_l_s_sto end attribute \module_not_derived 1 - attribute \src "libresoc.v:141921.9-141927.4" + attribute \src "libresoc.v:142261.9-142267.4" cell \upd_l \upd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228301,7 +227746,7 @@ module \ldst0 connect \s_upd \upd_l_s_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:141928.9-141934.4" + attribute \src "libresoc.v:142268.9-142274.4" cell \wri_l \wri_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228309,547 +227754,547 @@ module \ldst0 connect \r_wri \wri_l_r_wri connect \s_wri \wri_l_s_wri end - attribute \src "libresoc.v:140954.7-140954.20" - process $proc$libresoc.v:140954$6490 + attribute \src "libresoc.v:141294.7-141294.20" + process $proc$libresoc.v:141294$6422 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:141150.7-141150.25" - process $proc$libresoc.v:141150$6491 + attribute \src "libresoc.v:141490.7-141490.25" + process $proc$libresoc.v:141490$6423 assign { } { } assign $1\adr_l_r_adr[0:0] 1'1 sync always sync init update \adr_l_r_adr $1\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:141164.7-141164.20" - process $proc$libresoc.v:141164$6492 + attribute \src "libresoc.v:141504.7-141504.20" + process $proc$libresoc.v:141504$6424 assign { } { } assign $1\alu_ok[0:0] 1'0 sync always sync init update \alu_ok $1\alu_ok[0:0] end - attribute \src "libresoc.v:141210.14-141210.41" - process $proc$libresoc.v:141210$6493 + attribute \src "libresoc.v:141550.14-141550.41" + process $proc$libresoc.v:141550$6425 assign { } { } assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ea_r $1\ea_r[63:0] end - attribute \src "libresoc.v:141240.14-141240.42" - process $proc$libresoc.v:141240$6494 + attribute \src "libresoc.v:141580.14-141580.42" + process $proc$libresoc.v:141580$6426 assign { } { } assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldo_r $1\ldo_r[63:0] end - attribute \src "libresoc.v:141245.14-141245.62" - process $proc$libresoc.v:141245$6495 + attribute \src "libresoc.v:141585.14-141585.62" + process $proc$libresoc.v:141585$6427 assign { } { } assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:141250.7-141250.34" - process $proc$libresoc.v:141250$6496 + attribute \src "libresoc.v:141590.7-141590.34" + process $proc$libresoc.v:141590$6428 assign { } { } assign $1\ldst_port0_addr_i_ok[0:0] 1'0 sync always sync init update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:141299.7-141299.25" - process $proc$libresoc.v:141299$6497 + attribute \src "libresoc.v:141639.7-141639.25" + process $proc$libresoc.v:141639$6429 assign { } { } assign $1\lsd_l_r_lsd[0:0] 1'1 sync always sync init update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:141313.7-141313.25" - process $proc$libresoc.v:141313$6498 + attribute \src "libresoc.v:141653.7-141653.25" + process $proc$libresoc.v:141653$6430 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:141317.7-141317.25" - process $proc$libresoc.v:141317$6499 + attribute \src "libresoc.v:141657.7-141657.25" + process $proc$libresoc.v:141657$6431 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:141448.7-141448.34" - process $proc$libresoc.v:141448$6500 + attribute \src "libresoc.v:141788.7-141788.34" + process $proc$libresoc.v:141788$6432 assign { } { } assign $1\oper_r__byte_reverse[0:0] 1'0 sync always sync init update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:141452.13-141452.36" - process $proc$libresoc.v:141452$6501 + attribute \src "libresoc.v:141792.13-141792.36" + process $proc$libresoc.v:141792$6433 assign { } { } assign $1\oper_r__data_len[3:0] 4'0000 sync always sync init update \oper_r__data_len $1\oper_r__data_len[3:0] end - attribute \src "libresoc.v:141471.14-141471.40" - process $proc$libresoc.v:141471$6502 + attribute \src "libresoc.v:141811.14-141811.40" + process $proc$libresoc.v:141811$6434 assign { } { } assign $1\oper_r__fn_unit[13:0] 14'00000000000000 sync always sync init update \oper_r__fn_unit $1\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:141475.14-141475.59" - process $proc$libresoc.v:141475$6503 + attribute \src "libresoc.v:141815.14-141815.59" + process $proc$libresoc.v:141815$6435 assign { } { } assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:141479.7-141479.34" - process $proc$libresoc.v:141479$6504 + attribute \src "libresoc.v:141819.7-141819.34" + process $proc$libresoc.v:141819$6436 assign { } { } assign $1\oper_r__imm_data__ok[0:0] 1'0 sync always sync init update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:141483.14-141483.34" - process $proc$libresoc.v:141483$6505 + attribute \src "libresoc.v:141823.14-141823.34" + process $proc$libresoc.v:141823$6437 assign { } { } assign $1\oper_r__insn[31:0] 0 sync always sync init update \oper_r__insn $1\oper_r__insn[31:0] end - attribute \src "libresoc.v:141562.13-141562.38" - process $proc$libresoc.v:141562$6506 + attribute \src "libresoc.v:141902.13-141902.38" + process $proc$libresoc.v:141902$6438 assign { } { } assign $1\oper_r__insn_type[6:0] 7'0000000 sync always sync init update \oper_r__insn_type $1\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:141566.7-141566.30" - process $proc$libresoc.v:141566$6507 + attribute \src "libresoc.v:141906.7-141906.30" + process $proc$libresoc.v:141906$6439 assign { } { } assign $1\oper_r__is_32bit[0:0] 1'0 sync always sync init update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:141570.7-141570.31" - process $proc$libresoc.v:141570$6508 + attribute \src "libresoc.v:141910.7-141910.31" + process $proc$libresoc.v:141910$6440 assign { } { } assign $1\oper_r__is_signed[0:0] 1'0 sync always sync init update \oper_r__is_signed $1\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:141579.13-141579.37" - process $proc$libresoc.v:141579$6509 + attribute \src "libresoc.v:141919.13-141919.37" + process $proc$libresoc.v:141919$6441 assign { } { } assign $1\oper_r__ldst_mode[1:0] 2'00 sync always sync init update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:141583.7-141583.28" - process $proc$libresoc.v:141583$6510 + attribute \src "libresoc.v:141923.7-141923.28" + process $proc$libresoc.v:141923$6442 assign { } { } assign $1\oper_r__oe__oe[0:0] 1'0 sync always sync init update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:141587.7-141587.28" - process $proc$libresoc.v:141587$6511 + attribute \src "libresoc.v:141927.7-141927.28" + process $proc$libresoc.v:141927$6443 assign { } { } assign $1\oper_r__oe__ok[0:0] 1'0 sync always sync init update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:141591.7-141591.28" - process $proc$libresoc.v:141591$6512 + attribute \src "libresoc.v:141931.7-141931.28" + process $proc$libresoc.v:141931$6444 assign { } { } assign $1\oper_r__rc__ok[0:0] 1'0 sync always sync init update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:141595.7-141595.28" - process $proc$libresoc.v:141595$6513 + attribute \src "libresoc.v:141935.7-141935.28" + process $proc$libresoc.v:141935$6445 assign { } { } assign $1\oper_r__rc__rc[0:0] 1'0 sync always sync init update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:141599.7-141599.33" - process $proc$libresoc.v:141599$6514 + attribute \src "libresoc.v:141939.7-141939.33" + process $proc$libresoc.v:141939$6446 assign { } { } assign $1\oper_r__sign_extend[0:0] 1'0 sync always sync init update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:141603.7-141603.28" - process $proc$libresoc.v:141603$6515 + attribute \src "libresoc.v:141943.7-141943.28" + process $proc$libresoc.v:141943$6447 assign { } { } assign $1\oper_r__zero_a[0:0] 1'0 sync always sync init update \oper_r__zero_a $1\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:141607.7-141607.21" - process $proc$libresoc.v:141607$6516 + attribute \src "libresoc.v:141947.7-141947.21" + process $proc$libresoc.v:141947$6448 assign { } { } assign $1\p_st_go[0:0] 1'0 sync always sync init update \p_st_go $1\p_st_go[0:0] end - attribute \src "libresoc.v:141649.13-141649.31" - process $proc$libresoc.v:141649$6517 + attribute \src "libresoc.v:141989.13-141989.31" + process $proc$libresoc.v:141989$6449 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:141653.13-141653.31" - process $proc$libresoc.v:141653$6518 + attribute \src "libresoc.v:141993.13-141993.31" + process $proc$libresoc.v:141993$6450 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:141657.14-141657.43" - process $proc$libresoc.v:141657$6519 + attribute \src "libresoc.v:141997.14-141997.43" + process $proc$libresoc.v:141997$6451 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:141661.14-141661.43" - process $proc$libresoc.v:141661$6520 + attribute \src "libresoc.v:142001.14-142001.43" + process $proc$libresoc.v:142001$6452 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:141665.14-141665.43" - process $proc$libresoc.v:141665$6521 + attribute \src "libresoc.v:142005.14-142005.43" + process $proc$libresoc.v:142005$6453 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:141675.7-141675.25" - process $proc$libresoc.v:141675$6522 + attribute \src "libresoc.v:142015.7-142015.25" + process $proc$libresoc.v:142015$6454 assign { } { } assign $1\sto_l_r_sto[0:0] 1'1 sync always sync init update \sto_l_r_sto $1\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:141685.7-141685.25" - process $proc$libresoc.v:141685$6523 + attribute \src "libresoc.v:142025.7-142025.25" + process $proc$libresoc.v:142025$6455 assign { } { } assign $1\upd_l_r_upd[0:0] 1'1 sync always sync init update \upd_l_r_upd $1\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:141689.7-141689.25" - process $proc$libresoc.v:141689$6524 + attribute \src "libresoc.v:142029.7-142029.25" + process $proc$libresoc.v:142029$6456 assign { } { } assign $1\upd_l_s_upd[0:0] 1'0 sync always sync init update \upd_l_s_upd $1\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:141699.7-141699.25" - process $proc$libresoc.v:141699$6525 + attribute \src "libresoc.v:142039.7-142039.25" + process $proc$libresoc.v:142039$6457 assign { } { } assign $1\wri_l_r_wri[0:0] 1'1 sync always sync init update \wri_l_r_wri $1\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:141795.3-141796.57" - process $proc$libresoc.v:141795$6342 + attribute \src "libresoc.v:142135.3-142136.57" + process $proc$libresoc.v:142135$6274 assign { } { } assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next sync posedge \coresync_clk update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:141797.3-141798.33" - process $proc$libresoc.v:141797$6343 + attribute \src "libresoc.v:142137.3-142138.33" + process $proc$libresoc.v:142137$6275 assign { } { } assign $0\ldst_port0_addr_i[95:0] \$175 sync posedge \coresync_clk update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:141799.3-141800.21" - process $proc$libresoc.v:141799$6344 + attribute \src "libresoc.v:142139.3-142140.21" + process $proc$libresoc.v:142139$6276 assign { } { } assign $0\alu_ok[0:0] \$96 sync posedge \coresync_clk update \alu_ok $0\alu_ok[0:0] end - attribute \src "libresoc.v:141801.3-141802.25" - process $proc$libresoc.v:141801$6345 + attribute \src "libresoc.v:142141.3-142142.25" + process $proc$libresoc.v:142141$6277 assign { } { } assign $0\ea_r[63:0] \ea_r$next sync posedge \coresync_clk update \ea_r $0\ea_r[63:0] end - attribute \src "libresoc.v:141803.3-141804.29" - process $proc$libresoc.v:141803$6346 + attribute \src "libresoc.v:142143.3-142144.29" + process $proc$libresoc.v:142143$6278 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:141805.3-141806.29" - process $proc$libresoc.v:141805$6347 + attribute \src "libresoc.v:142145.3-142146.29" + process $proc$libresoc.v:142145$6279 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:141807.3-141808.29" - process $proc$libresoc.v:141807$6348 + attribute \src "libresoc.v:142147.3-142148.29" + process $proc$libresoc.v:142147$6280 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:141809.3-141810.27" - process $proc$libresoc.v:141809$6349 + attribute \src "libresoc.v:142149.3-142150.27" + process $proc$libresoc.v:142149$6281 assign { } { } assign $0\ldo_r[63:0] \ldo_r$next sync posedge \coresync_clk update \ldo_r $0\ldo_r[63:0] end - attribute \src "libresoc.v:141811.3-141812.51" - process $proc$libresoc.v:141811$6350 + attribute \src "libresoc.v:142151.3-142152.51" + process $proc$libresoc.v:142151$6282 assign { } { } assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next sync posedge \coresync_clk update \oper_r__insn_type $0\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:141813.3-141814.47" - process $proc$libresoc.v:141813$6351 + attribute \src "libresoc.v:142153.3-142154.47" + process $proc$libresoc.v:142153$6283 assign { } { } assign $0\oper_r__fn_unit[13:0] \oper_r__fn_unit$next sync posedge \coresync_clk update \oper_r__fn_unit $0\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:141815.3-141816.61" - process $proc$libresoc.v:141815$6352 + attribute \src "libresoc.v:142155.3-142156.61" + process $proc$libresoc.v:142155$6284 assign { } { } assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next sync posedge \coresync_clk update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:141817.3-141818.57" - process $proc$libresoc.v:141817$6353 + attribute \src "libresoc.v:142157.3-142158.57" + process $proc$libresoc.v:142157$6285 assign { } { } assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next sync posedge \coresync_clk update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:141819.3-141820.45" - process $proc$libresoc.v:141819$6354 + attribute \src "libresoc.v:142159.3-142160.45" + process $proc$libresoc.v:142159$6286 assign { } { } assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next sync posedge \coresync_clk update \oper_r__zero_a $0\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:141821.3-141822.45" - process $proc$libresoc.v:141821$6355 + attribute \src "libresoc.v:142161.3-142162.45" + process $proc$libresoc.v:142161$6287 assign { } { } assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next sync posedge \coresync_clk update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:141823.3-141824.45" - process $proc$libresoc.v:141823$6356 + attribute \src "libresoc.v:142163.3-142164.45" + process $proc$libresoc.v:142163$6288 assign { } { } assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next sync posedge \coresync_clk update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:141825.3-141826.45" - process $proc$libresoc.v:141825$6357 + attribute \src "libresoc.v:142165.3-142166.45" + process $proc$libresoc.v:142165$6289 assign { } { } assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next sync posedge \coresync_clk update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:141827.3-141828.45" - process $proc$libresoc.v:141827$6358 + attribute \src "libresoc.v:142167.3-142168.45" + process $proc$libresoc.v:142167$6290 assign { } { } assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next sync posedge \coresync_clk update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:141829.3-141830.49" - process $proc$libresoc.v:141829$6359 + attribute \src "libresoc.v:142169.3-142170.49" + process $proc$libresoc.v:142169$6291 assign { } { } assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next sync posedge \coresync_clk update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:141831.3-141832.51" - process $proc$libresoc.v:141831$6360 + attribute \src "libresoc.v:142171.3-142172.51" + process $proc$libresoc.v:142171$6292 assign { } { } assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next sync posedge \coresync_clk update \oper_r__is_signed $0\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:141833.3-141834.49" - process $proc$libresoc.v:141833$6361 + attribute \src "libresoc.v:142173.3-142174.49" + process $proc$libresoc.v:142173$6293 assign { } { } assign $0\oper_r__data_len[3:0] \oper_r__data_len$next sync posedge \coresync_clk update \oper_r__data_len $0\oper_r__data_len[3:0] end - attribute \src "libresoc.v:141835.3-141836.57" - process $proc$libresoc.v:141835$6362 + attribute \src "libresoc.v:142175.3-142176.57" + process $proc$libresoc.v:142175$6294 assign { } { } assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next sync posedge \coresync_clk update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:141837.3-141838.55" - process $proc$libresoc.v:141837$6363 + attribute \src "libresoc.v:142177.3-142178.55" + process $proc$libresoc.v:142177$6295 assign { } { } assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next sync posedge \coresync_clk update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:141839.3-141840.51" - process $proc$libresoc.v:141839$6364 + attribute \src "libresoc.v:142179.3-142180.51" + process $proc$libresoc.v:142179$6296 assign { } { } assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next sync posedge \coresync_clk update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:141841.3-141842.41" - process $proc$libresoc.v:141841$6365 + attribute \src "libresoc.v:142181.3-142182.41" + process $proc$libresoc.v:142181$6297 assign { } { } assign $0\oper_r__insn[31:0] \oper_r__insn$next sync posedge \coresync_clk update \oper_r__insn $0\oper_r__insn[31:0] end - attribute \src "libresoc.v:141843.3-141844.39" - process $proc$libresoc.v:141843$6366 + attribute \src "libresoc.v:142183.3-142184.39" + process $proc$libresoc.v:142183$6298 assign { } { } assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next sync posedge \coresync_clk update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:141845.3-141846.39" - process $proc$libresoc.v:141845$6367 + attribute \src "libresoc.v:142185.3-142186.39" + process $proc$libresoc.v:142185$6299 assign { } { } assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next sync posedge \coresync_clk update \sto_l_r_sto $0\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:141847.3-141848.39" - process $proc$libresoc.v:141847$6368 + attribute \src "libresoc.v:142187.3-142188.39" + process $proc$libresoc.v:142187$6300 assign { } { } assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next sync posedge \coresync_clk update \upd_l_r_upd $0\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:141849.3-141850.39" - process $proc$libresoc.v:141849$6369 + attribute \src "libresoc.v:142189.3-142190.39" + process $proc$libresoc.v:142189$6301 assign { } { } assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next sync posedge \coresync_clk update \upd_l_s_upd $0\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:141851.3-141852.39" - process $proc$libresoc.v:141851$6370 + attribute \src "libresoc.v:142191.3-142192.39" + process $proc$libresoc.v:142191$6302 assign { } { } assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next sync posedge \coresync_clk update \wri_l_r_wri $0\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:141853.3-141854.39" - process $proc$libresoc.v:141853$6371 + attribute \src "libresoc.v:142193.3-142194.39" + process $proc$libresoc.v:142193$6303 assign { } { } assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next sync posedge \coresync_clk update \adr_l_r_adr $0\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:141855.3-141856.39" - process $proc$libresoc.v:141855$6372 + attribute \src "libresoc.v:142195.3-142196.39" + process $proc$libresoc.v:142195$6304 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:141857.3-141858.39" - process $proc$libresoc.v:141857$6373 + attribute \src "libresoc.v:142197.3-142198.39" + process $proc$libresoc.v:142197$6305 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:141859.3-141860.39" - process $proc$libresoc.v:141859$6374 + attribute \src "libresoc.v:142199.3-142200.39" + process $proc$libresoc.v:142199$6306 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:141861.3-141862.39" - process $proc$libresoc.v:141861$6375 + attribute \src "libresoc.v:142201.3-142202.39" + process $proc$libresoc.v:142201$6307 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:141863.3-141864.28" - process $proc$libresoc.v:141863$6376 + attribute \src "libresoc.v:142203.3-142204.28" + process $proc$libresoc.v:142203$6308 assign { } { } assign $0\p_st_go[0:0] \cu_st__go_i sync posedge \coresync_clk update \p_st_go $0\p_st_go[0:0] end - attribute \src "libresoc.v:141935.3-141943.6" - process $proc$libresoc.v:141935$6377 + attribute \src "libresoc.v:142275.3-142283.6" + process $proc$libresoc.v:142275$6309 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6378 $1\opc_l_s_opc$next[0:0]$6379 - attribute \src "libresoc.v:141936.5-141936.29" + assign $0\opc_l_s_opc$next[0:0]$6310 $1\opc_l_s_opc$next[0:0]$6311 + attribute \src "libresoc.v:142276.5-142276.29" switch \initial - attribute \src "libresoc.v:141936.9-141936.17" + attribute \src "libresoc.v:142276.9-142276.17" case 1'1 case end @@ -228858,21 +228303,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6379 1'0 + assign $1\opc_l_s_opc$next[0:0]$6311 1'0 case - assign $1\opc_l_s_opc$next[0:0]$6379 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$6311 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6378 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6310 end - attribute \src "libresoc.v:141944.3-141952.6" - process $proc$libresoc.v:141944$6380 + attribute \src "libresoc.v:142284.3-142292.6" + process $proc$libresoc.v:142284$6312 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6381 $1\opc_l_r_opc$next[0:0]$6382 - attribute \src "libresoc.v:141945.5-141945.29" + assign $0\opc_l_r_opc$next[0:0]$6313 $1\opc_l_r_opc$next[0:0]$6314 + attribute \src "libresoc.v:142285.5-142285.29" switch \initial - attribute \src "libresoc.v:141945.9-141945.17" + attribute \src "libresoc.v:142285.9-142285.17" case 1'1 case end @@ -228881,21 +228326,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6382 1'1 + assign $1\opc_l_r_opc$next[0:0]$6314 1'1 case - assign $1\opc_l_r_opc$next[0:0]$6382 \reset_o + assign $1\opc_l_r_opc$next[0:0]$6314 \reset_o end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6381 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6313 end - attribute \src "libresoc.v:141953.3-141961.6" - process $proc$libresoc.v:141953$6383 + attribute \src "libresoc.v:142293.3-142301.6" + process $proc$libresoc.v:142293$6315 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$6384 $1\src_l_s_src$next[2:0]$6385 - attribute \src "libresoc.v:141954.5-141954.29" + assign $0\src_l_s_src$next[2:0]$6316 $1\src_l_s_src$next[2:0]$6317 + attribute \src "libresoc.v:142294.5-142294.29" switch \initial - attribute \src "libresoc.v:141954.9-141954.17" + attribute \src "libresoc.v:142294.9-142294.17" case 1'1 case end @@ -228904,21 +228349,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$6385 3'000 + assign $1\src_l_s_src$next[2:0]$6317 3'000 case - assign $1\src_l_s_src$next[2:0]$6385 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$6317 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6384 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6316 end - attribute \src "libresoc.v:141962.3-141970.6" - process $proc$libresoc.v:141962$6386 + attribute \src "libresoc.v:142302.3-142310.6" + process $proc$libresoc.v:142302$6318 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$6387 $1\src_l_r_src$next[2:0]$6388 - attribute \src "libresoc.v:141963.5-141963.29" + assign $0\src_l_r_src$next[2:0]$6319 $1\src_l_r_src$next[2:0]$6320 + attribute \src "libresoc.v:142303.5-142303.29" switch \initial - attribute \src "libresoc.v:141963.9-141963.17" + attribute \src "libresoc.v:142303.9-142303.17" case 1'1 case end @@ -228927,21 +228372,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$6388 3'111 + assign $1\src_l_r_src$next[2:0]$6320 3'111 case - assign $1\src_l_r_src$next[2:0]$6388 \reset_r + assign $1\src_l_r_src$next[2:0]$6320 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6387 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6319 end - attribute \src "libresoc.v:141971.3-141979.6" - process $proc$libresoc.v:141971$6389 + attribute \src "libresoc.v:142311.3-142319.6" + process $proc$libresoc.v:142311$6321 assign { } { } assign { } { } - assign $0\adr_l_r_adr$next[0:0]$6390 $1\adr_l_r_adr$next[0:0]$6391 - attribute \src "libresoc.v:141972.5-141972.29" + assign $0\adr_l_r_adr$next[0:0]$6322 $1\adr_l_r_adr$next[0:0]$6323 + attribute \src "libresoc.v:142312.5-142312.29" switch \initial - attribute \src "libresoc.v:141972.9-141972.17" + attribute \src "libresoc.v:142312.9-142312.17" case 1'1 case end @@ -228950,21 +228395,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adr_l_r_adr$next[0:0]$6391 1'1 + assign $1\adr_l_r_adr$next[0:0]$6323 1'1 case - assign $1\adr_l_r_adr$next[0:0]$6391 \reset_a + assign $1\adr_l_r_adr$next[0:0]$6323 \reset_a end sync always - update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6390 + update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6322 end - attribute \src "libresoc.v:141980.3-141988.6" - process $proc$libresoc.v:141980$6392 + attribute \src "libresoc.v:142320.3-142328.6" + process $proc$libresoc.v:142320$6324 assign { } { } assign { } { } - assign $0\wri_l_r_wri$next[0:0]$6393 $1\wri_l_r_wri$next[0:0]$6394 - attribute \src "libresoc.v:141981.5-141981.29" + assign $0\wri_l_r_wri$next[0:0]$6325 $1\wri_l_r_wri$next[0:0]$6326 + attribute \src "libresoc.v:142321.5-142321.29" switch \initial - attribute \src "libresoc.v:141981.9-141981.17" + attribute \src "libresoc.v:142321.9-142321.17" case 1'1 case end @@ -228973,21 +228418,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wri_l_r_wri$next[0:0]$6394 1'1 + assign $1\wri_l_r_wri$next[0:0]$6326 1'1 case - assign $1\wri_l_r_wri$next[0:0]$6394 \$38 [0] + assign $1\wri_l_r_wri$next[0:0]$6326 \$38 [0] end sync always - update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6393 + update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6325 end - attribute \src "libresoc.v:141989.3-141997.6" - process $proc$libresoc.v:141989$6395 + attribute \src "libresoc.v:142329.3-142337.6" + process $proc$libresoc.v:142329$6327 assign { } { } assign { } { } - assign $0\upd_l_s_upd$next[0:0]$6396 $1\upd_l_s_upd$next[0:0]$6397 - attribute \src "libresoc.v:141990.5-141990.29" + assign $0\upd_l_s_upd$next[0:0]$6328 $1\upd_l_s_upd$next[0:0]$6329 + attribute \src "libresoc.v:142330.5-142330.29" switch \initial - attribute \src "libresoc.v:141990.9-141990.17" + attribute \src "libresoc.v:142330.9-142330.17" case 1'1 case end @@ -228996,21 +228441,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_s_upd$next[0:0]$6397 1'0 + assign $1\upd_l_s_upd$next[0:0]$6329 1'0 case - assign $1\upd_l_s_upd$next[0:0]$6397 \reset_i + assign $1\upd_l_s_upd$next[0:0]$6329 \reset_i end sync always - update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6396 + update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6328 end - attribute \src "libresoc.v:141998.3-142006.6" - process $proc$libresoc.v:141998$6398 + attribute \src "libresoc.v:142338.3-142346.6" + process $proc$libresoc.v:142338$6330 assign { } { } assign { } { } - assign $0\upd_l_r_upd$next[0:0]$6399 $1\upd_l_r_upd$next[0:0]$6400 - attribute \src "libresoc.v:141999.5-141999.29" + assign $0\upd_l_r_upd$next[0:0]$6331 $1\upd_l_r_upd$next[0:0]$6332 + attribute \src "libresoc.v:142339.5-142339.29" switch \initial - attribute \src "libresoc.v:141999.9-141999.17" + attribute \src "libresoc.v:142339.9-142339.17" case 1'1 case end @@ -229019,21 +228464,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_r_upd$next[0:0]$6400 1'1 + assign $1\upd_l_r_upd$next[0:0]$6332 1'1 case - assign $1\upd_l_r_upd$next[0:0]$6400 \reset_u + assign $1\upd_l_r_upd$next[0:0]$6332 \reset_u end sync always - update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6399 + update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6331 end - attribute \src "libresoc.v:142007.3-142015.6" - process $proc$libresoc.v:142007$6401 + attribute \src "libresoc.v:142347.3-142355.6" + process $proc$libresoc.v:142347$6333 assign { } { } assign { } { } - assign $0\sto_l_r_sto$next[0:0]$6402 $1\sto_l_r_sto$next[0:0]$6403 - attribute \src "libresoc.v:142008.5-142008.29" + assign $0\sto_l_r_sto$next[0:0]$6334 $1\sto_l_r_sto$next[0:0]$6335 + attribute \src "libresoc.v:142348.5-142348.29" switch \initial - attribute \src "libresoc.v:142008.9-142008.17" + attribute \src "libresoc.v:142348.9-142348.17" case 1'1 case end @@ -229042,21 +228487,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sto_l_r_sto$next[0:0]$6403 1'1 + assign $1\sto_l_r_sto$next[0:0]$6335 1'1 case - assign $1\sto_l_r_sto$next[0:0]$6403 \$59 + assign $1\sto_l_r_sto$next[0:0]$6335 \$59 end sync always - update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6402 + update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6334 end - attribute \src "libresoc.v:142016.3-142024.6" - process $proc$libresoc.v:142016$6404 + attribute \src "libresoc.v:142356.3-142364.6" + process $proc$libresoc.v:142356$6336 assign { } { } assign { } { } - assign $0\lsd_l_r_lsd$next[0:0]$6405 $1\lsd_l_r_lsd$next[0:0]$6406 - attribute \src "libresoc.v:142017.5-142017.29" + assign $0\lsd_l_r_lsd$next[0:0]$6337 $1\lsd_l_r_lsd$next[0:0]$6338 + attribute \src "libresoc.v:142357.5-142357.29" switch \initial - attribute \src "libresoc.v:142017.9-142017.17" + attribute \src "libresoc.v:142357.9-142357.17" case 1'1 case end @@ -229065,15 +228510,15 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsd_l_r_lsd$next[0:0]$6406 1'1 + assign $1\lsd_l_r_lsd$next[0:0]$6338 1'1 case - assign $1\lsd_l_r_lsd$next[0:0]$6406 \$63 + assign $1\lsd_l_r_lsd$next[0:0]$6338 \$63 end sync always - update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6405 + update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6337 end - attribute \src "libresoc.v:142025.3-142067.6" - process $proc$libresoc.v:142025$6407 + attribute \src "libresoc.v:142365.3-142407.6" + process $proc$libresoc.v:142365$6339 assign { } { } assign { } { } assign { } { } @@ -229122,31 +228567,31 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $0\oper_r__byte_reverse$next[0:0]$6408 $2\oper_r__byte_reverse$next[0:0]$6440 - assign $0\oper_r__data_len$next[3:0]$6409 $2\oper_r__data_len$next[3:0]$6441 - assign $0\oper_r__fn_unit$next[13:0]$6410 $2\oper_r__fn_unit$next[13:0]$6442 + assign $0\oper_r__byte_reverse$next[0:0]$6340 $2\oper_r__byte_reverse$next[0:0]$6372 + assign $0\oper_r__data_len$next[3:0]$6341 $2\oper_r__data_len$next[3:0]$6373 + assign $0\oper_r__fn_unit$next[13:0]$6342 $2\oper_r__fn_unit$next[13:0]$6374 assign { } { } assign { } { } - assign $0\oper_r__insn$next[31:0]$6413 $2\oper_r__insn$next[31:0]$6445 - assign $0\oper_r__insn_type$next[6:0]$6414 $2\oper_r__insn_type$next[6:0]$6446 - assign $0\oper_r__is_32bit$next[0:0]$6415 $2\oper_r__is_32bit$next[0:0]$6447 - assign $0\oper_r__is_signed$next[0:0]$6416 $2\oper_r__is_signed$next[0:0]$6448 - assign $0\oper_r__ldst_mode$next[1:0]$6417 $2\oper_r__ldst_mode$next[1:0]$6449 + assign $0\oper_r__insn$next[31:0]$6345 $2\oper_r__insn$next[31:0]$6377 + assign $0\oper_r__insn_type$next[6:0]$6346 $2\oper_r__insn_type$next[6:0]$6378 + assign $0\oper_r__is_32bit$next[0:0]$6347 $2\oper_r__is_32bit$next[0:0]$6379 + assign $0\oper_r__is_signed$next[0:0]$6348 $2\oper_r__is_signed$next[0:0]$6380 + assign $0\oper_r__ldst_mode$next[1:0]$6349 $2\oper_r__ldst_mode$next[1:0]$6381 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\oper_r__sign_extend$next[0:0]$6422 $2\oper_r__sign_extend$next[0:0]$6454 - assign $0\oper_r__zero_a$next[0:0]$6423 $2\oper_r__zero_a$next[0:0]$6455 - assign $0\oper_r__imm_data__data$next[63:0]$6411 $3\oper_r__imm_data__data$next[63:0]$6456 - assign $0\oper_r__imm_data__ok$next[0:0]$6412 $3\oper_r__imm_data__ok$next[0:0]$6457 - assign $0\oper_r__oe__oe$next[0:0]$6418 $3\oper_r__oe__oe$next[0:0]$6458 - assign $0\oper_r__oe__ok$next[0:0]$6419 $3\oper_r__oe__ok$next[0:0]$6459 - assign $0\oper_r__rc__ok$next[0:0]$6420 $3\oper_r__rc__ok$next[0:0]$6460 - assign $0\oper_r__rc__rc$next[0:0]$6421 $3\oper_r__rc__rc$next[0:0]$6461 - attribute \src "libresoc.v:142026.5-142026.29" + assign $0\oper_r__sign_extend$next[0:0]$6354 $2\oper_r__sign_extend$next[0:0]$6386 + assign $0\oper_r__zero_a$next[0:0]$6355 $2\oper_r__zero_a$next[0:0]$6387 + assign $0\oper_r__imm_data__data$next[63:0]$6343 $3\oper_r__imm_data__data$next[63:0]$6388 + assign $0\oper_r__imm_data__ok$next[0:0]$6344 $3\oper_r__imm_data__ok$next[0:0]$6389 + assign $0\oper_r__oe__oe$next[0:0]$6350 $3\oper_r__oe__oe$next[0:0]$6390 + assign $0\oper_r__oe__ok$next[0:0]$6351 $3\oper_r__oe__ok$next[0:0]$6391 + assign $0\oper_r__rc__ok$next[0:0]$6352 $3\oper_r__rc__ok$next[0:0]$6392 + assign $0\oper_r__rc__rc$next[0:0]$6353 $3\oper_r__rc__rc$next[0:0]$6393 + attribute \src "libresoc.v:142366.5-142366.29" switch \initial - attribute \src "libresoc.v:142026.9-142026.17" + attribute \src "libresoc.v:142366.9-142366.17" case 1'1 case end @@ -229170,24 +228615,24 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { $1\oper_r__insn$next[31:0]$6429 $1\oper_r__ldst_mode$next[1:0]$6433 $1\oper_r__sign_extend$next[0:0]$6438 $1\oper_r__byte_reverse$next[0:0]$6424 $1\oper_r__data_len$next[3:0]$6425 $1\oper_r__is_signed$next[0:0]$6432 $1\oper_r__is_32bit$next[0:0]$6431 $1\oper_r__oe__ok$next[0:0]$6435 $1\oper_r__oe__oe$next[0:0]$6434 $1\oper_r__rc__ok$next[0:0]$6436 $1\oper_r__rc__rc$next[0:0]$6437 $1\oper_r__zero_a$next[0:0]$6439 $1\oper_r__imm_data__ok$next[0:0]$6428 $1\oper_r__imm_data__data$next[63:0]$6427 $1\oper_r__fn_unit$next[13:0]$6426 $1\oper_r__insn_type$next[6:0]$6430 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } + assign { $1\oper_r__insn$next[31:0]$6361 $1\oper_r__ldst_mode$next[1:0]$6365 $1\oper_r__sign_extend$next[0:0]$6370 $1\oper_r__byte_reverse$next[0:0]$6356 $1\oper_r__data_len$next[3:0]$6357 $1\oper_r__is_signed$next[0:0]$6364 $1\oper_r__is_32bit$next[0:0]$6363 $1\oper_r__oe__ok$next[0:0]$6367 $1\oper_r__oe__oe$next[0:0]$6366 $1\oper_r__rc__ok$next[0:0]$6368 $1\oper_r__rc__rc$next[0:0]$6369 $1\oper_r__zero_a$next[0:0]$6371 $1\oper_r__imm_data__ok$next[0:0]$6360 $1\oper_r__imm_data__data$next[63:0]$6359 $1\oper_r__fn_unit$next[13:0]$6358 $1\oper_r__insn_type$next[6:0]$6362 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } case - assign $1\oper_r__byte_reverse$next[0:0]$6424 \oper_r__byte_reverse - assign $1\oper_r__data_len$next[3:0]$6425 \oper_r__data_len - assign $1\oper_r__fn_unit$next[13:0]$6426 \oper_r__fn_unit - assign $1\oper_r__imm_data__data$next[63:0]$6427 \oper_r__imm_data__data - assign $1\oper_r__imm_data__ok$next[0:0]$6428 \oper_r__imm_data__ok - assign $1\oper_r__insn$next[31:0]$6429 \oper_r__insn - assign $1\oper_r__insn_type$next[6:0]$6430 \oper_r__insn_type - assign $1\oper_r__is_32bit$next[0:0]$6431 \oper_r__is_32bit - assign $1\oper_r__is_signed$next[0:0]$6432 \oper_r__is_signed - assign $1\oper_r__ldst_mode$next[1:0]$6433 \oper_r__ldst_mode - assign $1\oper_r__oe__oe$next[0:0]$6434 \oper_r__oe__oe - assign $1\oper_r__oe__ok$next[0:0]$6435 \oper_r__oe__ok - assign $1\oper_r__rc__ok$next[0:0]$6436 \oper_r__rc__ok - assign $1\oper_r__rc__rc$next[0:0]$6437 \oper_r__rc__rc - assign $1\oper_r__sign_extend$next[0:0]$6438 \oper_r__sign_extend - assign $1\oper_r__zero_a$next[0:0]$6439 \oper_r__zero_a + assign $1\oper_r__byte_reverse$next[0:0]$6356 \oper_r__byte_reverse + assign $1\oper_r__data_len$next[3:0]$6357 \oper_r__data_len + assign $1\oper_r__fn_unit$next[13:0]$6358 \oper_r__fn_unit + assign $1\oper_r__imm_data__data$next[63:0]$6359 \oper_r__imm_data__data + assign $1\oper_r__imm_data__ok$next[0:0]$6360 \oper_r__imm_data__ok + assign $1\oper_r__insn$next[31:0]$6361 \oper_r__insn + assign $1\oper_r__insn_type$next[6:0]$6362 \oper_r__insn_type + assign $1\oper_r__is_32bit$next[0:0]$6363 \oper_r__is_32bit + assign $1\oper_r__is_signed$next[0:0]$6364 \oper_r__is_signed + assign $1\oper_r__ldst_mode$next[1:0]$6365 \oper_r__ldst_mode + assign $1\oper_r__oe__oe$next[0:0]$6366 \oper_r__oe__oe + assign $1\oper_r__oe__ok$next[0:0]$6367 \oper_r__oe__ok + assign $1\oper_r__rc__ok$next[0:0]$6368 \oper_r__rc__ok + assign $1\oper_r__rc__rc$next[0:0]$6369 \oper_r__rc__rc + assign $1\oper_r__sign_extend$next[0:0]$6370 \oper_r__sign_extend + assign $1\oper_r__zero_a$next[0:0]$6371 \oper_r__zero_a end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" switch \cu_done_o @@ -229209,24 +228654,24 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { $2\oper_r__insn$next[31:0]$6445 $2\oper_r__ldst_mode$next[1:0]$6449 $2\oper_r__sign_extend$next[0:0]$6454 $2\oper_r__byte_reverse$next[0:0]$6440 $2\oper_r__data_len$next[3:0]$6441 $2\oper_r__is_signed$next[0:0]$6448 $2\oper_r__is_32bit$next[0:0]$6447 $2\oper_r__oe__ok$next[0:0]$6451 $2\oper_r__oe__oe$next[0:0]$6450 $2\oper_r__rc__ok$next[0:0]$6452 $2\oper_r__rc__rc$next[0:0]$6453 $2\oper_r__zero_a$next[0:0]$6455 $2\oper_r__imm_data__ok$next[0:0]$6444 $2\oper_r__imm_data__data$next[63:0]$6443 $2\oper_r__fn_unit$next[13:0]$6442 $2\oper_r__insn_type$next[6:0]$6446 } 133'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $2\oper_r__insn$next[31:0]$6377 $2\oper_r__ldst_mode$next[1:0]$6381 $2\oper_r__sign_extend$next[0:0]$6386 $2\oper_r__byte_reverse$next[0:0]$6372 $2\oper_r__data_len$next[3:0]$6373 $2\oper_r__is_signed$next[0:0]$6380 $2\oper_r__is_32bit$next[0:0]$6379 $2\oper_r__oe__ok$next[0:0]$6383 $2\oper_r__oe__oe$next[0:0]$6382 $2\oper_r__rc__ok$next[0:0]$6384 $2\oper_r__rc__rc$next[0:0]$6385 $2\oper_r__zero_a$next[0:0]$6387 $2\oper_r__imm_data__ok$next[0:0]$6376 $2\oper_r__imm_data__data$next[63:0]$6375 $2\oper_r__fn_unit$next[13:0]$6374 $2\oper_r__insn_type$next[6:0]$6378 } 133'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $2\oper_r__byte_reverse$next[0:0]$6440 $1\oper_r__byte_reverse$next[0:0]$6424 - assign $2\oper_r__data_len$next[3:0]$6441 $1\oper_r__data_len$next[3:0]$6425 - assign $2\oper_r__fn_unit$next[13:0]$6442 $1\oper_r__fn_unit$next[13:0]$6426 - assign $2\oper_r__imm_data__data$next[63:0]$6443 $1\oper_r__imm_data__data$next[63:0]$6427 - assign $2\oper_r__imm_data__ok$next[0:0]$6444 $1\oper_r__imm_data__ok$next[0:0]$6428 - assign $2\oper_r__insn$next[31:0]$6445 $1\oper_r__insn$next[31:0]$6429 - assign $2\oper_r__insn_type$next[6:0]$6446 $1\oper_r__insn_type$next[6:0]$6430 - assign $2\oper_r__is_32bit$next[0:0]$6447 $1\oper_r__is_32bit$next[0:0]$6431 - assign $2\oper_r__is_signed$next[0:0]$6448 $1\oper_r__is_signed$next[0:0]$6432 - assign $2\oper_r__ldst_mode$next[1:0]$6449 $1\oper_r__ldst_mode$next[1:0]$6433 - assign $2\oper_r__oe__oe$next[0:0]$6450 $1\oper_r__oe__oe$next[0:0]$6434 - assign $2\oper_r__oe__ok$next[0:0]$6451 $1\oper_r__oe__ok$next[0:0]$6435 - assign $2\oper_r__rc__ok$next[0:0]$6452 $1\oper_r__rc__ok$next[0:0]$6436 - assign $2\oper_r__rc__rc$next[0:0]$6453 $1\oper_r__rc__rc$next[0:0]$6437 - assign $2\oper_r__sign_extend$next[0:0]$6454 $1\oper_r__sign_extend$next[0:0]$6438 - assign $2\oper_r__zero_a$next[0:0]$6455 $1\oper_r__zero_a$next[0:0]$6439 + assign $2\oper_r__byte_reverse$next[0:0]$6372 $1\oper_r__byte_reverse$next[0:0]$6356 + assign $2\oper_r__data_len$next[3:0]$6373 $1\oper_r__data_len$next[3:0]$6357 + assign $2\oper_r__fn_unit$next[13:0]$6374 $1\oper_r__fn_unit$next[13:0]$6358 + assign $2\oper_r__imm_data__data$next[63:0]$6375 $1\oper_r__imm_data__data$next[63:0]$6359 + assign $2\oper_r__imm_data__ok$next[0:0]$6376 $1\oper_r__imm_data__ok$next[0:0]$6360 + assign $2\oper_r__insn$next[31:0]$6377 $1\oper_r__insn$next[31:0]$6361 + assign $2\oper_r__insn_type$next[6:0]$6378 $1\oper_r__insn_type$next[6:0]$6362 + assign $2\oper_r__is_32bit$next[0:0]$6379 $1\oper_r__is_32bit$next[0:0]$6363 + assign $2\oper_r__is_signed$next[0:0]$6380 $1\oper_r__is_signed$next[0:0]$6364 + assign $2\oper_r__ldst_mode$next[1:0]$6381 $1\oper_r__ldst_mode$next[1:0]$6365 + assign $2\oper_r__oe__oe$next[0:0]$6382 $1\oper_r__oe__oe$next[0:0]$6366 + assign $2\oper_r__oe__ok$next[0:0]$6383 $1\oper_r__oe__ok$next[0:0]$6367 + assign $2\oper_r__rc__ok$next[0:0]$6384 $1\oper_r__rc__ok$next[0:0]$6368 + assign $2\oper_r__rc__rc$next[0:0]$6385 $1\oper_r__rc__rc$next[0:0]$6369 + assign $2\oper_r__sign_extend$next[0:0]$6386 $1\oper_r__sign_extend$next[0:0]$6370 + assign $2\oper_r__zero_a$next[0:0]$6387 $1\oper_r__zero_a$next[0:0]$6371 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -229238,46 +228683,46 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $3\oper_r__imm_data__data$next[63:0]$6456 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\oper_r__imm_data__ok$next[0:0]$6457 1'0 - assign $3\oper_r__rc__rc$next[0:0]$6461 1'0 - assign $3\oper_r__rc__ok$next[0:0]$6460 1'0 - assign $3\oper_r__oe__oe$next[0:0]$6458 1'0 - assign $3\oper_r__oe__ok$next[0:0]$6459 1'0 + assign $3\oper_r__imm_data__data$next[63:0]$6388 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\oper_r__imm_data__ok$next[0:0]$6389 1'0 + assign $3\oper_r__rc__rc$next[0:0]$6393 1'0 + assign $3\oper_r__rc__ok$next[0:0]$6392 1'0 + assign $3\oper_r__oe__oe$next[0:0]$6390 1'0 + assign $3\oper_r__oe__ok$next[0:0]$6391 1'0 case - assign $3\oper_r__imm_data__data$next[63:0]$6456 $2\oper_r__imm_data__data$next[63:0]$6443 - assign $3\oper_r__imm_data__ok$next[0:0]$6457 $2\oper_r__imm_data__ok$next[0:0]$6444 - assign $3\oper_r__oe__oe$next[0:0]$6458 $2\oper_r__oe__oe$next[0:0]$6450 - assign $3\oper_r__oe__ok$next[0:0]$6459 $2\oper_r__oe__ok$next[0:0]$6451 - assign $3\oper_r__rc__ok$next[0:0]$6460 $2\oper_r__rc__ok$next[0:0]$6452 - assign $3\oper_r__rc__rc$next[0:0]$6461 $2\oper_r__rc__rc$next[0:0]$6453 + assign $3\oper_r__imm_data__data$next[63:0]$6388 $2\oper_r__imm_data__data$next[63:0]$6375 + assign $3\oper_r__imm_data__ok$next[0:0]$6389 $2\oper_r__imm_data__ok$next[0:0]$6376 + assign $3\oper_r__oe__oe$next[0:0]$6390 $2\oper_r__oe__oe$next[0:0]$6382 + assign $3\oper_r__oe__ok$next[0:0]$6391 $2\oper_r__oe__ok$next[0:0]$6383 + assign $3\oper_r__rc__ok$next[0:0]$6392 $2\oper_r__rc__ok$next[0:0]$6384 + assign $3\oper_r__rc__rc$next[0:0]$6393 $2\oper_r__rc__rc$next[0:0]$6385 end sync always - update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6408 - update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6409 - update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[13:0]$6410 - update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6411 - update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6412 - update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6413 - update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6414 - update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6415 - update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6416 - update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6417 - update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6418 - update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6419 - update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6420 - update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6421 - update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6422 - update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6423 + update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6340 + update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6341 + update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[13:0]$6342 + update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6343 + update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6344 + update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6345 + update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6346 + update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6347 + update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6348 + update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6349 + update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6350 + update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6351 + update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6352 + update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6353 + update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6354 + update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6355 end - attribute \src "libresoc.v:142068.3-142077.6" - process $proc$libresoc.v:142068$6462 + attribute \src "libresoc.v:142408.3-142417.6" + process $proc$libresoc.v:142408$6394 assign { } { } assign { } { } - assign $0\ldo_r$next[63:0]$6463 $1\ldo_r$next[63:0]$6464 - attribute \src "libresoc.v:142069.5-142069.29" + assign $0\ldo_r$next[63:0]$6395 $1\ldo_r$next[63:0]$6396 + attribute \src "libresoc.v:142409.5-142409.29" switch \initial - attribute \src "libresoc.v:142069.9-142069.17" + attribute \src "libresoc.v:142409.9-142409.17" case 1'1 case end @@ -229286,22 +228731,22 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldo_r$next[63:0]$6464 \ldd_o + assign $1\ldo_r$next[63:0]$6396 \ldd_o case - assign $1\ldo_r$next[63:0]$6464 \ldo_r + assign $1\ldo_r$next[63:0]$6396 \ldo_r end sync always - update \ldo_r$next $0\ldo_r$next[63:0]$6463 + update \ldo_r$next $0\ldo_r$next[63:0]$6395 end - attribute \src "libresoc.v:142078.3-142093.6" - process $proc$libresoc.v:142078$6465 + attribute \src "libresoc.v:142418.3-142433.6" + process $proc$libresoc.v:142418$6397 assign { } { } assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$6466 $2\src_r0$next[63:0]$6468 - attribute \src "libresoc.v:142079.5-142079.29" + assign $0\src_r0$next[63:0]$6398 $2\src_r0$next[63:0]$6400 + attribute \src "libresoc.v:142419.5-142419.29" switch \initial - attribute \src "libresoc.v:142079.9-142079.17" + attribute \src "libresoc.v:142419.9-142419.17" case 1'1 case end @@ -229310,31 +228755,31 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$6467 \src1_i + assign $1\src_r0$next[63:0]$6399 \src1_i case - assign $1\src_r0$next[63:0]$6467 \src_r0 + assign $1\src_r0$next[63:0]$6399 \src_r0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r0$next[63:0]$6468 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r0$next[63:0]$6400 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r0$next[63:0]$6468 $1\src_r0$next[63:0]$6467 + assign $2\src_r0$next[63:0]$6400 $1\src_r0$next[63:0]$6399 end sync always - update \src_r0$next $0\src_r0$next[63:0]$6466 + update \src_r0$next $0\src_r0$next[63:0]$6398 end - attribute \src "libresoc.v:142094.3-142109.6" - process $proc$libresoc.v:142094$6469 + attribute \src "libresoc.v:142434.3-142449.6" + process $proc$libresoc.v:142434$6401 assign { } { } assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$6470 $2\src_r1$next[63:0]$6472 - attribute \src "libresoc.v:142095.5-142095.29" + assign $0\src_r1$next[63:0]$6402 $2\src_r1$next[63:0]$6404 + attribute \src "libresoc.v:142435.5-142435.29" switch \initial - attribute \src "libresoc.v:142095.9-142095.17" + attribute \src "libresoc.v:142435.9-142435.17" case 1'1 case end @@ -229343,31 +228788,31 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$6471 \src2_i + assign $1\src_r1$next[63:0]$6403 \src2_i case - assign $1\src_r1$next[63:0]$6471 \src_r1 + assign $1\src_r1$next[63:0]$6403 \src_r1 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r1$next[63:0]$6472 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r1$next[63:0]$6404 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r1$next[63:0]$6472 $1\src_r1$next[63:0]$6471 + assign $2\src_r1$next[63:0]$6404 $1\src_r1$next[63:0]$6403 end sync always - update \src_r1$next $0\src_r1$next[63:0]$6470 + update \src_r1$next $0\src_r1$next[63:0]$6402 end - attribute \src "libresoc.v:142110.3-142125.6" - process $proc$libresoc.v:142110$6473 + attribute \src "libresoc.v:142450.3-142465.6" + process $proc$libresoc.v:142450$6405 assign { } { } assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$6474 $2\src_r2$next[63:0]$6476 - attribute \src "libresoc.v:142111.5-142111.29" + assign $0\src_r2$next[63:0]$6406 $2\src_r2$next[63:0]$6408 + attribute \src "libresoc.v:142451.5-142451.29" switch \initial - attribute \src "libresoc.v:142111.9-142111.17" + attribute \src "libresoc.v:142451.9-142451.17" case 1'1 case end @@ -229376,30 +228821,30 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$6475 \src3_i + assign $1\src_r2$next[63:0]$6407 \src3_i case - assign $1\src_r2$next[63:0]$6475 \src_r2 + assign $1\src_r2$next[63:0]$6407 \src_r2 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r2$next[63:0]$6476 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r2$next[63:0]$6408 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r2$next[63:0]$6476 $1\src_r2$next[63:0]$6475 + assign $2\src_r2$next[63:0]$6408 $1\src_r2$next[63:0]$6407 end sync always - update \src_r2$next $0\src_r2$next[63:0]$6474 + update \src_r2$next $0\src_r2$next[63:0]$6406 end - attribute \src "libresoc.v:142126.3-142135.6" - process $proc$libresoc.v:142126$6477 + attribute \src "libresoc.v:142466.3-142475.6" + process $proc$libresoc.v:142466$6409 assign { } { } assign { } { } - assign $0\ea_r$next[63:0]$6478 $1\ea_r$next[63:0]$6479 - attribute \src "libresoc.v:142127.5-142127.29" + assign $0\ea_r$next[63:0]$6410 $1\ea_r$next[63:0]$6411 + attribute \src "libresoc.v:142467.5-142467.29" switch \initial - attribute \src "libresoc.v:142127.9-142127.17" + attribute \src "libresoc.v:142467.9-142467.17" case 1'1 case end @@ -229408,21 +228853,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ea_r$next[63:0]$6479 \alu_o + assign $1\ea_r$next[63:0]$6411 \alu_o case - assign $1\ea_r$next[63:0]$6479 \ea_r + assign $1\ea_r$next[63:0]$6411 \ea_r end sync always - update \ea_r$next $0\ea_r$next[63:0]$6478 + update \ea_r$next $0\ea_r$next[63:0]$6410 end - attribute \src "libresoc.v:142136.3-142145.6" - process $proc$libresoc.v:142136$6480 + attribute \src "libresoc.v:142476.3-142485.6" + process $proc$libresoc.v:142476$6412 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:142137.5-142137.29" + attribute \src "libresoc.v:142477.5-142477.29" switch \initial - attribute \src "libresoc.v:142137.9-142137.17" + attribute \src "libresoc.v:142477.9-142477.17" case 1'1 case end @@ -229438,14 +228883,14 @@ module \ldst0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:142146.3-142155.6" - process $proc$libresoc.v:142146$6481 + attribute \src "libresoc.v:142486.3-142495.6" + process $proc$libresoc.v:142486$6413 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:142147.5-142147.29" + attribute \src "libresoc.v:142487.5-142487.29" switch \initial - attribute \src "libresoc.v:142147.9-142147.17" + attribute \src "libresoc.v:142487.9-142487.17" case 1'1 case end @@ -229461,14 +228906,14 @@ module \ldst0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:142156.3-142164.6" - process $proc$libresoc.v:142156$6482 + attribute \src "libresoc.v:142496.3-142504.6" + process $proc$libresoc.v:142496$6414 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$next[0:0]$6483 $1\ldst_port0_addr_i_ok$next[0:0]$6484 - attribute \src "libresoc.v:142157.5-142157.29" + assign $0\ldst_port0_addr_i_ok$next[0:0]$6415 $1\ldst_port0_addr_i_ok$next[0:0]$6416 + attribute \src "libresoc.v:142497.5-142497.29" switch \initial - attribute \src "libresoc.v:142157.9-142157.17" + attribute \src "libresoc.v:142497.9-142497.17" case 1'1 case end @@ -229477,21 +228922,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$next[0:0]$6484 1'0 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6416 1'0 case - assign $1\ldst_port0_addr_i_ok$next[0:0]$6484 \$177 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6416 \$177 end sync always - update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6483 + update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6415 end - attribute \src "libresoc.v:142165.3-142188.6" - process $proc$libresoc.v:142165$6485 + attribute \src "libresoc.v:142505.3-142528.6" + process $proc$libresoc.v:142505$6417 assign { } { } assign { } { } assign $0\lddata_r[63:0] $1\lddata_r[63:0] - attribute \src "libresoc.v:142166.5-142166.29" + attribute \src "libresoc.v:142506.5-142506.29" switch \initial - attribute \src "libresoc.v:142166.9-142166.17" + attribute \src "libresoc.v:142506.9-142506.17" case 1'1 case end @@ -229528,13 +228973,13 @@ module \ldst0 sync always update \lddata_r $0\lddata_r[63:0] end - attribute \src "libresoc.v:142189.3-142200.6" - process $proc$libresoc.v:142189$6486 + attribute \src "libresoc.v:142529.3-142540.6" + process $proc$libresoc.v:142529$6418 assign { } { } assign $0\revnorev[63:0] $1\revnorev[63:0] - attribute \src "libresoc.v:142190.5-142190.29" + attribute \src "libresoc.v:142530.5-142530.29" switch \initial - attribute \src "libresoc.v:142190.9-142190.17" + attribute \src "libresoc.v:142530.9-142530.17" case 1'1 case end @@ -229552,13 +228997,13 @@ module \ldst0 sync always update \revnorev $0\revnorev[63:0] end - attribute \src "libresoc.v:142201.3-142220.6" - process $proc$libresoc.v:142201$6487 + attribute \src "libresoc.v:142541.3-142560.6" + process $proc$libresoc.v:142541$6419 assign { } { } assign $0\ldd_o[63:0] $1\ldd_o[63:0] - attribute \src "libresoc.v:142202.5-142202.29" + attribute \src "libresoc.v:142542.5-142542.29" switch \initial - attribute \src "libresoc.v:142202.9-142202.17" + attribute \src "libresoc.v:142542.9-142542.17" case 1'1 case end @@ -229587,14 +229032,14 @@ module \ldst0 sync always update \ldd_o $0\ldd_o[63:0] end - attribute \src "libresoc.v:142221.3-142244.6" - process $proc$libresoc.v:142221$6488 + attribute \src "libresoc.v:142561.3-142584.6" + process $proc$libresoc.v:142561$6420 assign { } { } assign { } { } assign $0\stdata_r[63:0] $1\stdata_r[63:0] - attribute \src "libresoc.v:142222.5-142222.29" + attribute \src "libresoc.v:142562.5-142562.29" switch \initial - attribute \src "libresoc.v:142222.9-142222.17" + attribute \src "libresoc.v:142562.9-142562.17" case 1'1 case end @@ -229631,13 +229076,13 @@ module \ldst0 sync always update \stdata_r $0\stdata_r[63:0] end - attribute \src "libresoc.v:142245.3-142256.6" - process $proc$libresoc.v:142245$6489 + attribute \src "libresoc.v:142585.3-142596.6" + process $proc$libresoc.v:142585$6421 assign { } { } assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:142246.5-142246.29" + attribute \src "libresoc.v:142586.5-142586.29" switch \initial - attribute \src "libresoc.v:142246.9-142246.17" + attribute \src "libresoc.v:142586.9-142586.17" case 1'1 case end @@ -229655,97 +229100,97 @@ module \ldst0 sync always update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] end - connect \$100 $and$libresoc.v:141704$6248_Y - connect \$102 $and$libresoc.v:141705$6249_Y - connect \$104 $and$libresoc.v:141706$6250_Y - connect \$106 $and$libresoc.v:141707$6251_Y - connect \$108 $and$libresoc.v:141708$6252_Y - connect \$10 $or$libresoc.v:141709$6253_Y - connect \$110 $and$libresoc.v:141710$6254_Y - connect \$112 $and$libresoc.v:141711$6255_Y - connect \$114 $and$libresoc.v:141712$6256_Y - connect \$116 $and$libresoc.v:141713$6257_Y - connect \$118 $and$libresoc.v:141714$6258_Y - connect \$120 $and$libresoc.v:141715$6259_Y - connect \$122 $and$libresoc.v:141716$6260_Y - connect \$124 $and$libresoc.v:141717$6261_Y - connect \$126 $eq$libresoc.v:141718$6262_Y - connect \$128 $and$libresoc.v:141719$6263_Y - connect \$12 $or$libresoc.v:141720$6264_Y - connect \$130 $and$libresoc.v:141721$6265_Y - connect \$132 $and$libresoc.v:141722$6266_Y - connect \$134 $or$libresoc.v:141723$6267_Y - connect \$136 $or$libresoc.v:141724$6268_Y - connect \$138 $or$libresoc.v:141725$6269_Y - connect \$140 $and$libresoc.v:141726$6270_Y - connect \$142 $and$libresoc.v:141727$6271_Y - connect \$145 $or$libresoc.v:141728$6272_Y - connect \$147 $or$libresoc.v:141729$6273_Y - connect \$144 $not$libresoc.v:141730$6274_Y - connect \$14 $or$libresoc.v:141731$6275_Y - connect \$150 $and$libresoc.v:141732$6276_Y - connect \$152 $or$libresoc.v:141733$6277_Y - connect \$154 $and$libresoc.v:141734$6278_Y - connect \$156 $not$libresoc.v:141735$6279_Y - connect \$158 $or$libresoc.v:141736$6280_Y - connect \$160 $and$libresoc.v:141737$6281_Y - connect \$162 $eq$libresoc.v:141738$6282_Y - connect \$164 $and$libresoc.v:141739$6283_Y - connect \$167 $eq$libresoc.v:141740$6284_Y - connect \$16 $or$libresoc.v:141741$6285_Y - connect \$169 $and$libresoc.v:141742$6286_Y - connect \$171 $and$libresoc.v:141743$6287_Y - connect \$173 $and$libresoc.v:141744$6288_Y - connect \$175 $pos$libresoc.v:141745$6290_Y - connect \$177 $and$libresoc.v:141746$6291_Y - connect \$186 $pos$libresoc.v:141747$6293_Y - connect \$188 $pos$libresoc.v:141748$6294_Y - connect \$18 $or$libresoc.v:141749$6295_Y - connect \$190 $pos$libresoc.v:141750$6296_Y - connect \$192 $eq$libresoc.v:141751$6297_Y - connect \$194 $pos$libresoc.v:141752$6299_Y - connect \$196 $pos$libresoc.v:141753$6300_Y - connect \$198 $pos$libresoc.v:141754$6301_Y - connect \$20 $or$libresoc.v:141755$6302_Y - connect \$22 $eq$libresoc.v:141756$6303_Y - connect \$24 $eq$libresoc.v:141757$6304_Y - connect \$26 $and$libresoc.v:141758$6305_Y - connect \$28 $and$libresoc.v:141759$6306_Y - connect \$30 $not$libresoc.v:141760$6307_Y - connect \$32 $and$libresoc.v:141761$6308_Y - connect \$34 $not$libresoc.v:141762$6309_Y - connect \$36 $and$libresoc.v:141763$6310_Y - connect \$39 $not$libresoc.v:141764$6311_Y - connect \$41 $eq$libresoc.v:141765$6312_Y - connect \$43 $and$libresoc.v:141766$6313_Y - connect \$45 $or$libresoc.v:141767$6314_Y - connect \$47 $not$libresoc.v:141768$6315_Y - connect \$49 $eq$libresoc.v:141769$6316_Y - connect \$51 $and$libresoc.v:141770$6317_Y - connect \$53 $or$libresoc.v:141771$6318_Y - connect \$55 $or$libresoc.v:141772$6319_Y - connect \$57 $and$libresoc.v:141773$6320_Y - connect \$59 $or$libresoc.v:141774$6321_Y - connect \$61 $or$libresoc.v:141775$6322_Y - connect \$63 $or$libresoc.v:141776$6323_Y - connect \$65 $ternary$libresoc.v:141777$6324_Y - connect \$67 $ternary$libresoc.v:141778$6325_Y - connect \$69 $ternary$libresoc.v:141779$6326_Y - connect \$71 $ternary$libresoc.v:141780$6327_Y - connect \$74 $add$libresoc.v:141781$6328_Y - connect \$76 $and$libresoc.v:141782$6329_Y - connect \$78 $not$libresoc.v:141783$6330_Y - connect \$80 $and$libresoc.v:141784$6331_Y - connect \$82 $not$libresoc.v:141785$6332_Y - connect \$84 $and$libresoc.v:141786$6333_Y - connect \$86 $and$libresoc.v:141787$6334_Y - connect \$88 $and$libresoc.v:141788$6335_Y - connect \$8 $or$libresoc.v:141789$6336_Y - connect \$90 $or$libresoc.v:141790$6337_Y - connect \$93 $or$libresoc.v:141791$6338_Y - connect \$92 $not$libresoc.v:141792$6339_Y - connect \$96 $and$libresoc.v:141793$6340_Y - connect \$98 $not$libresoc.v:141794$6341_Y + connect \$100 $and$libresoc.v:142044$6180_Y + connect \$102 $and$libresoc.v:142045$6181_Y + connect \$104 $and$libresoc.v:142046$6182_Y + connect \$106 $and$libresoc.v:142047$6183_Y + connect \$108 $and$libresoc.v:142048$6184_Y + connect \$10 $or$libresoc.v:142049$6185_Y + connect \$110 $and$libresoc.v:142050$6186_Y + connect \$112 $and$libresoc.v:142051$6187_Y + connect \$114 $and$libresoc.v:142052$6188_Y + connect \$116 $and$libresoc.v:142053$6189_Y + connect \$118 $and$libresoc.v:142054$6190_Y + connect \$120 $and$libresoc.v:142055$6191_Y + connect \$122 $and$libresoc.v:142056$6192_Y + connect \$124 $and$libresoc.v:142057$6193_Y + connect \$126 $eq$libresoc.v:142058$6194_Y + connect \$128 $and$libresoc.v:142059$6195_Y + connect \$12 $or$libresoc.v:142060$6196_Y + connect \$130 $and$libresoc.v:142061$6197_Y + connect \$132 $and$libresoc.v:142062$6198_Y + connect \$134 $or$libresoc.v:142063$6199_Y + connect \$136 $or$libresoc.v:142064$6200_Y + connect \$138 $or$libresoc.v:142065$6201_Y + connect \$140 $and$libresoc.v:142066$6202_Y + connect \$142 $and$libresoc.v:142067$6203_Y + connect \$145 $or$libresoc.v:142068$6204_Y + connect \$147 $or$libresoc.v:142069$6205_Y + connect \$144 $not$libresoc.v:142070$6206_Y + connect \$14 $or$libresoc.v:142071$6207_Y + connect \$150 $and$libresoc.v:142072$6208_Y + connect \$152 $or$libresoc.v:142073$6209_Y + connect \$154 $and$libresoc.v:142074$6210_Y + connect \$156 $not$libresoc.v:142075$6211_Y + connect \$158 $or$libresoc.v:142076$6212_Y + connect \$160 $and$libresoc.v:142077$6213_Y + connect \$162 $eq$libresoc.v:142078$6214_Y + connect \$164 $and$libresoc.v:142079$6215_Y + connect \$167 $eq$libresoc.v:142080$6216_Y + connect \$16 $or$libresoc.v:142081$6217_Y + connect \$169 $and$libresoc.v:142082$6218_Y + connect \$171 $and$libresoc.v:142083$6219_Y + connect \$173 $and$libresoc.v:142084$6220_Y + connect \$175 $pos$libresoc.v:142085$6222_Y + connect \$177 $and$libresoc.v:142086$6223_Y + connect \$186 $pos$libresoc.v:142087$6225_Y + connect \$188 $pos$libresoc.v:142088$6226_Y + connect \$18 $or$libresoc.v:142089$6227_Y + connect \$190 $pos$libresoc.v:142090$6228_Y + connect \$192 $eq$libresoc.v:142091$6229_Y + connect \$194 $pos$libresoc.v:142092$6231_Y + connect \$196 $pos$libresoc.v:142093$6232_Y + connect \$198 $pos$libresoc.v:142094$6233_Y + connect \$20 $or$libresoc.v:142095$6234_Y + connect \$22 $eq$libresoc.v:142096$6235_Y + connect \$24 $eq$libresoc.v:142097$6236_Y + connect \$26 $and$libresoc.v:142098$6237_Y + connect \$28 $and$libresoc.v:142099$6238_Y + connect \$30 $not$libresoc.v:142100$6239_Y + connect \$32 $and$libresoc.v:142101$6240_Y + connect \$34 $not$libresoc.v:142102$6241_Y + connect \$36 $and$libresoc.v:142103$6242_Y + connect \$39 $not$libresoc.v:142104$6243_Y + connect \$41 $eq$libresoc.v:142105$6244_Y + connect \$43 $and$libresoc.v:142106$6245_Y + connect \$45 $or$libresoc.v:142107$6246_Y + connect \$47 $not$libresoc.v:142108$6247_Y + connect \$49 $eq$libresoc.v:142109$6248_Y + connect \$51 $and$libresoc.v:142110$6249_Y + connect \$53 $or$libresoc.v:142111$6250_Y + connect \$55 $or$libresoc.v:142112$6251_Y + connect \$57 $and$libresoc.v:142113$6252_Y + connect \$59 $or$libresoc.v:142114$6253_Y + connect \$61 $or$libresoc.v:142115$6254_Y + connect \$63 $or$libresoc.v:142116$6255_Y + connect \$65 $ternary$libresoc.v:142117$6256_Y + connect \$67 $ternary$libresoc.v:142118$6257_Y + connect \$69 $ternary$libresoc.v:142119$6258_Y + connect \$71 $ternary$libresoc.v:142120$6259_Y + connect \$74 $add$libresoc.v:142121$6260_Y + connect \$76 $and$libresoc.v:142122$6261_Y + connect \$78 $not$libresoc.v:142123$6262_Y + connect \$80 $and$libresoc.v:142124$6263_Y + connect \$82 $not$libresoc.v:142125$6264_Y + connect \$84 $and$libresoc.v:142126$6265_Y + connect \$86 $and$libresoc.v:142127$6266_Y + connect \$88 $and$libresoc.v:142128$6267_Y + connect \$8 $or$libresoc.v:142129$6268_Y + connect \$90 $or$libresoc.v:142130$6269_Y + connect \$93 $or$libresoc.v:142131$6270_Y + connect \$92 $not$libresoc.v:142132$6271_Y + connect \$96 $and$libresoc.v:142133$6272_Y + connect \$98 $not$libresoc.v:142134$6273_Y connect \$38 \$55 connect \$73 \$74 connect \$166 \$169 @@ -229806,271 +229251,271 @@ module \ldst0 connect \reset_o \$10 connect \reset_i \$8 end -attribute \src "libresoc.v:142320.1-142907.10" +attribute \src "libresoc.v:142660.1-143247.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" attribute \generator "nMigen" module \left_mask - attribute \src "libresoc.v:142321.7-142321.20" + attribute \src "libresoc.v:142661.7-142661.20" wire $0\initial[0:0] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $10\mask[9:9] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $11\mask[10:10] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $12\mask[11:11] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $13\mask[12:12] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $14\mask[13:13] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $15\mask[14:14] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $16\mask[15:15] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $17\mask[16:16] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $18\mask[17:17] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $19\mask[18:18] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $1\mask[0:0] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $20\mask[19:19] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $21\mask[20:20] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $22\mask[21:21] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $23\mask[22:22] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $24\mask[23:23] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $25\mask[24:24] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $26\mask[25:25] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $27\mask[26:26] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $28\mask[27:27] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $29\mask[28:28] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $2\mask[1:1] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $30\mask[29:29] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $31\mask[30:30] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $32\mask[31:31] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $33\mask[32:32] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $34\mask[33:33] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $35\mask[34:34] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $36\mask[35:35] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $37\mask[36:36] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $38\mask[37:37] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $39\mask[38:38] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $3\mask[2:2] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $40\mask[39:39] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $41\mask[40:40] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $42\mask[41:41] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $43\mask[42:42] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $44\mask[43:43] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $45\mask[44:44] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $46\mask[45:45] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $47\mask[46:46] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $48\mask[47:47] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $49\mask[48:48] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $4\mask[3:3] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $50\mask[49:49] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $51\mask[50:50] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $52\mask[51:51] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $53\mask[52:52] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $54\mask[53:53] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $55\mask[54:54] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $56\mask[55:55] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $57\mask[56:56] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $58\mask[57:57] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $59\mask[58:58] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $5\mask[4:4] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $60\mask[59:59] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $61\mask[60:60] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $62\mask[61:61] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $63\mask[62:62] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $64\mask[63:63] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $6\mask[5:5] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $7\mask[6:6] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $8\mask[7:7] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142859.3-143246.6" wire $9\mask[8:8] - attribute \src "libresoc.v:142455.17-142455.96" - wire $gt$libresoc.v:142455$6526_Y - attribute \src "libresoc.v:142456.18-142456.98" - wire $gt$libresoc.v:142456$6527_Y - attribute \src "libresoc.v:142457.19-142457.99" - wire $gt$libresoc.v:142457$6528_Y - attribute \src "libresoc.v:142458.19-142458.99" - wire $gt$libresoc.v:142458$6529_Y - attribute \src "libresoc.v:142459.19-142459.99" - wire $gt$libresoc.v:142459$6530_Y - attribute \src "libresoc.v:142460.19-142460.99" - wire $gt$libresoc.v:142460$6531_Y - attribute \src "libresoc.v:142461.19-142461.99" - wire $gt$libresoc.v:142461$6532_Y - attribute \src "libresoc.v:142462.19-142462.99" - wire $gt$libresoc.v:142462$6533_Y - attribute \src "libresoc.v:142463.19-142463.99" - wire $gt$libresoc.v:142463$6534_Y - attribute \src "libresoc.v:142464.19-142464.99" - wire $gt$libresoc.v:142464$6535_Y - attribute \src "libresoc.v:142465.19-142465.99" - wire $gt$libresoc.v:142465$6536_Y - attribute \src "libresoc.v:142466.18-142466.97" - wire $gt$libresoc.v:142466$6537_Y - attribute \src "libresoc.v:142467.19-142467.99" - wire $gt$libresoc.v:142467$6538_Y - attribute \src "libresoc.v:142468.19-142468.99" - wire $gt$libresoc.v:142468$6539_Y - attribute \src "libresoc.v:142469.19-142469.99" - wire $gt$libresoc.v:142469$6540_Y - attribute \src "libresoc.v:142470.19-142470.99" - wire $gt$libresoc.v:142470$6541_Y - attribute \src "libresoc.v:142471.19-142471.99" - wire $gt$libresoc.v:142471$6542_Y - attribute \src "libresoc.v:142472.18-142472.97" - wire $gt$libresoc.v:142472$6543_Y - attribute \src "libresoc.v:142473.18-142473.97" - wire $gt$libresoc.v:142473$6544_Y - attribute \src "libresoc.v:142474.18-142474.97" - wire $gt$libresoc.v:142474$6545_Y - attribute \src "libresoc.v:142475.17-142475.96" - wire $gt$libresoc.v:142475$6546_Y - attribute \src "libresoc.v:142476.18-142476.97" - wire $gt$libresoc.v:142476$6547_Y - attribute \src "libresoc.v:142477.18-142477.97" - wire $gt$libresoc.v:142477$6548_Y - attribute \src "libresoc.v:142478.18-142478.97" - wire $gt$libresoc.v:142478$6549_Y - attribute \src "libresoc.v:142479.18-142479.97" - wire $gt$libresoc.v:142479$6550_Y - attribute \src "libresoc.v:142480.18-142480.97" - wire $gt$libresoc.v:142480$6551_Y - attribute \src "libresoc.v:142481.18-142481.97" - wire $gt$libresoc.v:142481$6552_Y - attribute \src "libresoc.v:142482.18-142482.97" - wire $gt$libresoc.v:142482$6553_Y - attribute \src "libresoc.v:142483.18-142483.98" - wire $gt$libresoc.v:142483$6554_Y - attribute \src "libresoc.v:142484.18-142484.98" - wire $gt$libresoc.v:142484$6555_Y - attribute \src "libresoc.v:142485.18-142485.98" - wire $gt$libresoc.v:142485$6556_Y - attribute \src "libresoc.v:142486.17-142486.96" - wire $gt$libresoc.v:142486$6557_Y - attribute \src "libresoc.v:142487.18-142487.98" - wire $gt$libresoc.v:142487$6558_Y - attribute \src "libresoc.v:142488.18-142488.98" - wire $gt$libresoc.v:142488$6559_Y - attribute \src "libresoc.v:142489.18-142489.98" - wire $gt$libresoc.v:142489$6560_Y - attribute \src "libresoc.v:142490.18-142490.98" - wire $gt$libresoc.v:142490$6561_Y - attribute \src "libresoc.v:142491.18-142491.98" - wire $gt$libresoc.v:142491$6562_Y - attribute \src "libresoc.v:142492.18-142492.98" - wire $gt$libresoc.v:142492$6563_Y - attribute \src "libresoc.v:142493.18-142493.98" - wire $gt$libresoc.v:142493$6564_Y - attribute \src "libresoc.v:142494.18-142494.98" - wire $gt$libresoc.v:142494$6565_Y - attribute \src "libresoc.v:142495.18-142495.98" - wire $gt$libresoc.v:142495$6566_Y - attribute \src "libresoc.v:142496.18-142496.98" - wire $gt$libresoc.v:142496$6567_Y - attribute \src "libresoc.v:142497.17-142497.96" - wire $gt$libresoc.v:142497$6568_Y - attribute \src "libresoc.v:142498.18-142498.98" - wire $gt$libresoc.v:142498$6569_Y - attribute \src "libresoc.v:142499.18-142499.98" - wire $gt$libresoc.v:142499$6570_Y - attribute \src "libresoc.v:142500.18-142500.98" - wire $gt$libresoc.v:142500$6571_Y - attribute \src "libresoc.v:142501.18-142501.98" - wire $gt$libresoc.v:142501$6572_Y - attribute \src "libresoc.v:142502.18-142502.98" - wire $gt$libresoc.v:142502$6573_Y - attribute \src "libresoc.v:142503.18-142503.98" - wire $gt$libresoc.v:142503$6574_Y - attribute \src "libresoc.v:142504.18-142504.98" - wire $gt$libresoc.v:142504$6575_Y - attribute \src "libresoc.v:142505.18-142505.98" - wire $gt$libresoc.v:142505$6576_Y - attribute \src "libresoc.v:142506.18-142506.98" - wire $gt$libresoc.v:142506$6577_Y - attribute \src "libresoc.v:142507.18-142507.98" - wire $gt$libresoc.v:142507$6578_Y - attribute \src "libresoc.v:142508.17-142508.96" - wire $gt$libresoc.v:142508$6579_Y - attribute \src "libresoc.v:142509.18-142509.98" - wire $gt$libresoc.v:142509$6580_Y - attribute \src "libresoc.v:142510.18-142510.98" - wire $gt$libresoc.v:142510$6581_Y - attribute \src "libresoc.v:142511.18-142511.98" - wire $gt$libresoc.v:142511$6582_Y - attribute \src "libresoc.v:142512.18-142512.98" - wire $gt$libresoc.v:142512$6583_Y - attribute \src "libresoc.v:142513.18-142513.98" - wire $gt$libresoc.v:142513$6584_Y - attribute \src "libresoc.v:142514.18-142514.98" - wire $gt$libresoc.v:142514$6585_Y - attribute \src "libresoc.v:142515.18-142515.98" - wire $gt$libresoc.v:142515$6586_Y - attribute \src "libresoc.v:142516.18-142516.98" - wire $gt$libresoc.v:142516$6587_Y - attribute \src "libresoc.v:142517.18-142517.98" - wire $gt$libresoc.v:142517$6588_Y - attribute \src "libresoc.v:142518.18-142518.98" - wire $gt$libresoc.v:142518$6589_Y + attribute \src "libresoc.v:142795.17-142795.96" + wire $gt$libresoc.v:142795$6458_Y + attribute \src "libresoc.v:142796.18-142796.98" + wire $gt$libresoc.v:142796$6459_Y + attribute \src "libresoc.v:142797.19-142797.99" + wire $gt$libresoc.v:142797$6460_Y + attribute \src "libresoc.v:142798.19-142798.99" + wire $gt$libresoc.v:142798$6461_Y + attribute \src "libresoc.v:142799.19-142799.99" + wire $gt$libresoc.v:142799$6462_Y + attribute \src "libresoc.v:142800.19-142800.99" + wire $gt$libresoc.v:142800$6463_Y + attribute \src "libresoc.v:142801.19-142801.99" + wire $gt$libresoc.v:142801$6464_Y + attribute \src "libresoc.v:142802.19-142802.99" + wire $gt$libresoc.v:142802$6465_Y + attribute \src "libresoc.v:142803.19-142803.99" + wire $gt$libresoc.v:142803$6466_Y + attribute \src "libresoc.v:142804.19-142804.99" + wire $gt$libresoc.v:142804$6467_Y + attribute \src "libresoc.v:142805.19-142805.99" + wire $gt$libresoc.v:142805$6468_Y + attribute \src "libresoc.v:142806.18-142806.97" + wire $gt$libresoc.v:142806$6469_Y + attribute \src "libresoc.v:142807.19-142807.99" + wire $gt$libresoc.v:142807$6470_Y + attribute \src "libresoc.v:142808.19-142808.99" + wire $gt$libresoc.v:142808$6471_Y + attribute \src "libresoc.v:142809.19-142809.99" + wire $gt$libresoc.v:142809$6472_Y + attribute \src "libresoc.v:142810.19-142810.99" + wire $gt$libresoc.v:142810$6473_Y + attribute \src "libresoc.v:142811.19-142811.99" + wire $gt$libresoc.v:142811$6474_Y + attribute \src "libresoc.v:142812.18-142812.97" + wire $gt$libresoc.v:142812$6475_Y + attribute \src "libresoc.v:142813.18-142813.97" + wire $gt$libresoc.v:142813$6476_Y + attribute \src "libresoc.v:142814.18-142814.97" + wire $gt$libresoc.v:142814$6477_Y + attribute \src "libresoc.v:142815.17-142815.96" + wire $gt$libresoc.v:142815$6478_Y + attribute \src "libresoc.v:142816.18-142816.97" + wire $gt$libresoc.v:142816$6479_Y + attribute \src "libresoc.v:142817.18-142817.97" + wire $gt$libresoc.v:142817$6480_Y + attribute \src "libresoc.v:142818.18-142818.97" + wire $gt$libresoc.v:142818$6481_Y + attribute \src "libresoc.v:142819.18-142819.97" + wire $gt$libresoc.v:142819$6482_Y + attribute \src "libresoc.v:142820.18-142820.97" + wire $gt$libresoc.v:142820$6483_Y + attribute \src "libresoc.v:142821.18-142821.97" + wire $gt$libresoc.v:142821$6484_Y + attribute \src "libresoc.v:142822.18-142822.97" + wire $gt$libresoc.v:142822$6485_Y + attribute \src "libresoc.v:142823.18-142823.98" + wire $gt$libresoc.v:142823$6486_Y + attribute \src "libresoc.v:142824.18-142824.98" + wire $gt$libresoc.v:142824$6487_Y + attribute \src "libresoc.v:142825.18-142825.98" + wire $gt$libresoc.v:142825$6488_Y + attribute \src "libresoc.v:142826.17-142826.96" + wire $gt$libresoc.v:142826$6489_Y + attribute \src "libresoc.v:142827.18-142827.98" + wire $gt$libresoc.v:142827$6490_Y + attribute \src "libresoc.v:142828.18-142828.98" + wire $gt$libresoc.v:142828$6491_Y + attribute \src "libresoc.v:142829.18-142829.98" + wire $gt$libresoc.v:142829$6492_Y + attribute \src "libresoc.v:142830.18-142830.98" + wire $gt$libresoc.v:142830$6493_Y + attribute \src "libresoc.v:142831.18-142831.98" + wire $gt$libresoc.v:142831$6494_Y + attribute \src "libresoc.v:142832.18-142832.98" + wire $gt$libresoc.v:142832$6495_Y + attribute \src "libresoc.v:142833.18-142833.98" + wire $gt$libresoc.v:142833$6496_Y + attribute \src "libresoc.v:142834.18-142834.98" + wire $gt$libresoc.v:142834$6497_Y + attribute \src "libresoc.v:142835.18-142835.98" + wire $gt$libresoc.v:142835$6498_Y + attribute \src "libresoc.v:142836.18-142836.98" + wire $gt$libresoc.v:142836$6499_Y + attribute \src "libresoc.v:142837.17-142837.96" + wire $gt$libresoc.v:142837$6500_Y + attribute \src "libresoc.v:142838.18-142838.98" + wire $gt$libresoc.v:142838$6501_Y + attribute \src "libresoc.v:142839.18-142839.98" + wire $gt$libresoc.v:142839$6502_Y + attribute \src "libresoc.v:142840.18-142840.98" + wire $gt$libresoc.v:142840$6503_Y + attribute \src "libresoc.v:142841.18-142841.98" + wire $gt$libresoc.v:142841$6504_Y + attribute \src "libresoc.v:142842.18-142842.98" + wire $gt$libresoc.v:142842$6505_Y + attribute \src "libresoc.v:142843.18-142843.98" + wire $gt$libresoc.v:142843$6506_Y + attribute \src "libresoc.v:142844.18-142844.98" + wire $gt$libresoc.v:142844$6507_Y + attribute \src "libresoc.v:142845.18-142845.98" + wire $gt$libresoc.v:142845$6508_Y + attribute \src "libresoc.v:142846.18-142846.98" + wire $gt$libresoc.v:142846$6509_Y + attribute \src "libresoc.v:142847.18-142847.98" + wire $gt$libresoc.v:142847$6510_Y + attribute \src "libresoc.v:142848.17-142848.96" + wire $gt$libresoc.v:142848$6511_Y + attribute \src "libresoc.v:142849.18-142849.98" + wire $gt$libresoc.v:142849$6512_Y + attribute \src "libresoc.v:142850.18-142850.98" + wire $gt$libresoc.v:142850$6513_Y + attribute \src "libresoc.v:142851.18-142851.98" + wire $gt$libresoc.v:142851$6514_Y + attribute \src "libresoc.v:142852.18-142852.98" + wire $gt$libresoc.v:142852$6515_Y + attribute \src "libresoc.v:142853.18-142853.98" + wire $gt$libresoc.v:142853$6516_Y + attribute \src "libresoc.v:142854.18-142854.98" + wire $gt$libresoc.v:142854$6517_Y + attribute \src "libresoc.v:142855.18-142855.98" + wire $gt$libresoc.v:142855$6518_Y + attribute \src "libresoc.v:142856.18-142856.98" + wire $gt$libresoc.v:142856$6519_Y + attribute \src "libresoc.v:142857.18-142857.98" + wire $gt$libresoc.v:142857$6520_Y + attribute \src "libresoc.v:142858.18-142858.98" + wire $gt$libresoc.v:142858$6521_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -230199,14 +229644,14 @@ module \left_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:142321.7-142321.15" + attribute \src "libresoc.v:142661.7-142661.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142455$6526 + cell $gt $gt$libresoc.v:142795$6458 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230214,10 +229659,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:142455$6526_Y + connect \Y $gt$libresoc.v:142795$6458_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142456$6527 + cell $gt $gt$libresoc.v:142796$6459 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230225,10 +229670,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:142456$6527_Y + connect \Y $gt$libresoc.v:142796$6459_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142457$6528 + cell $gt $gt$libresoc.v:142797$6460 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230236,10 +229681,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:142457$6528_Y + connect \Y $gt$libresoc.v:142797$6460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142458$6529 + cell $gt $gt$libresoc.v:142798$6461 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230247,10 +229692,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:142458$6529_Y + connect \Y $gt$libresoc.v:142798$6461_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142459$6530 + cell $gt $gt$libresoc.v:142799$6462 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230258,10 +229703,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:142459$6530_Y + connect \Y $gt$libresoc.v:142799$6462_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142460$6531 + cell $gt $gt$libresoc.v:142800$6463 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230269,10 +229714,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:142460$6531_Y + connect \Y $gt$libresoc.v:142800$6463_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142461$6532 + cell $gt $gt$libresoc.v:142801$6464 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230280,10 +229725,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:142461$6532_Y + connect \Y $gt$libresoc.v:142801$6464_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142462$6533 + cell $gt $gt$libresoc.v:142802$6465 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230291,10 +229736,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:142462$6533_Y + connect \Y $gt$libresoc.v:142802$6465_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142463$6534 + cell $gt $gt$libresoc.v:142803$6466 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230302,10 +229747,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:142463$6534_Y + connect \Y $gt$libresoc.v:142803$6466_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142464$6535 + cell $gt $gt$libresoc.v:142804$6467 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230313,10 +229758,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:142464$6535_Y + connect \Y $gt$libresoc.v:142804$6467_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142465$6536 + cell $gt $gt$libresoc.v:142805$6468 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230324,10 +229769,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:142465$6536_Y + connect \Y $gt$libresoc.v:142805$6468_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142466$6537 + cell $gt $gt$libresoc.v:142806$6469 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230335,10 +229780,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:142466$6537_Y + connect \Y $gt$libresoc.v:142806$6469_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142467$6538 + cell $gt $gt$libresoc.v:142807$6470 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230346,10 +229791,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:142467$6538_Y + connect \Y $gt$libresoc.v:142807$6470_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142468$6539 + cell $gt $gt$libresoc.v:142808$6471 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230357,10 +229802,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:142468$6539_Y + connect \Y $gt$libresoc.v:142808$6471_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142469$6540 + cell $gt $gt$libresoc.v:142809$6472 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230368,10 +229813,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:142469$6540_Y + connect \Y $gt$libresoc.v:142809$6472_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142470$6541 + cell $gt $gt$libresoc.v:142810$6473 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230379,10 +229824,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:142470$6541_Y + connect \Y $gt$libresoc.v:142810$6473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142471$6542 + cell $gt $gt$libresoc.v:142811$6474 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230390,10 +229835,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:142471$6542_Y + connect \Y $gt$libresoc.v:142811$6474_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142472$6543 + cell $gt $gt$libresoc.v:142812$6475 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230401,10 +229846,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:142472$6543_Y + connect \Y $gt$libresoc.v:142812$6475_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142473$6544 + cell $gt $gt$libresoc.v:142813$6476 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230412,10 +229857,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:142473$6544_Y + connect \Y $gt$libresoc.v:142813$6476_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142474$6545 + cell $gt $gt$libresoc.v:142814$6477 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230423,10 +229868,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:142474$6545_Y + connect \Y $gt$libresoc.v:142814$6477_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142475$6546 + cell $gt $gt$libresoc.v:142815$6478 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230434,10 +229879,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:142475$6546_Y + connect \Y $gt$libresoc.v:142815$6478_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142476$6547 + cell $gt $gt$libresoc.v:142816$6479 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230445,10 +229890,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:142476$6547_Y + connect \Y $gt$libresoc.v:142816$6479_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142477$6548 + cell $gt $gt$libresoc.v:142817$6480 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230456,10 +229901,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:142477$6548_Y + connect \Y $gt$libresoc.v:142817$6480_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142478$6549 + cell $gt $gt$libresoc.v:142818$6481 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230467,10 +229912,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:142478$6549_Y + connect \Y $gt$libresoc.v:142818$6481_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142479$6550 + cell $gt $gt$libresoc.v:142819$6482 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230478,10 +229923,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:142479$6550_Y + connect \Y $gt$libresoc.v:142819$6482_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142480$6551 + cell $gt $gt$libresoc.v:142820$6483 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230489,10 +229934,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:142480$6551_Y + connect \Y $gt$libresoc.v:142820$6483_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142481$6552 + cell $gt $gt$libresoc.v:142821$6484 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230500,10 +229945,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:142481$6552_Y + connect \Y $gt$libresoc.v:142821$6484_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142482$6553 + cell $gt $gt$libresoc.v:142822$6485 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230511,10 +229956,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:142482$6553_Y + connect \Y $gt$libresoc.v:142822$6485_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142483$6554 + cell $gt $gt$libresoc.v:142823$6486 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230522,10 +229967,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:142483$6554_Y + connect \Y $gt$libresoc.v:142823$6486_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142484$6555 + cell $gt $gt$libresoc.v:142824$6487 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230533,10 +229978,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:142484$6555_Y + connect \Y $gt$libresoc.v:142824$6487_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142485$6556 + cell $gt $gt$libresoc.v:142825$6488 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230544,10 +229989,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:142485$6556_Y + connect \Y $gt$libresoc.v:142825$6488_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142486$6557 + cell $gt $gt$libresoc.v:142826$6489 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230555,10 +230000,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:142486$6557_Y + connect \Y $gt$libresoc.v:142826$6489_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142487$6558 + cell $gt $gt$libresoc.v:142827$6490 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230566,10 +230011,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:142487$6558_Y + connect \Y $gt$libresoc.v:142827$6490_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142488$6559 + cell $gt $gt$libresoc.v:142828$6491 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230577,10 +230022,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:142488$6559_Y + connect \Y $gt$libresoc.v:142828$6491_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142489$6560 + cell $gt $gt$libresoc.v:142829$6492 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230588,10 +230033,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:142489$6560_Y + connect \Y $gt$libresoc.v:142829$6492_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142490$6561 + cell $gt $gt$libresoc.v:142830$6493 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230599,10 +230044,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:142490$6561_Y + connect \Y $gt$libresoc.v:142830$6493_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142491$6562 + cell $gt $gt$libresoc.v:142831$6494 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230610,10 +230055,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:142491$6562_Y + connect \Y $gt$libresoc.v:142831$6494_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142492$6563 + cell $gt $gt$libresoc.v:142832$6495 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230621,10 +230066,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:142492$6563_Y + connect \Y $gt$libresoc.v:142832$6495_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142493$6564 + cell $gt $gt$libresoc.v:142833$6496 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230632,10 +230077,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:142493$6564_Y + connect \Y $gt$libresoc.v:142833$6496_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142494$6565 + cell $gt $gt$libresoc.v:142834$6497 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230643,10 +230088,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:142494$6565_Y + connect \Y $gt$libresoc.v:142834$6497_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142495$6566 + cell $gt $gt$libresoc.v:142835$6498 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230654,10 +230099,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:142495$6566_Y + connect \Y $gt$libresoc.v:142835$6498_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142496$6567 + cell $gt $gt$libresoc.v:142836$6499 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230665,10 +230110,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:142496$6567_Y + connect \Y $gt$libresoc.v:142836$6499_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142497$6568 + cell $gt $gt$libresoc.v:142837$6500 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230676,10 +230121,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:142497$6568_Y + connect \Y $gt$libresoc.v:142837$6500_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142498$6569 + cell $gt $gt$libresoc.v:142838$6501 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230687,10 +230132,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:142498$6569_Y + connect \Y $gt$libresoc.v:142838$6501_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142499$6570 + cell $gt $gt$libresoc.v:142839$6502 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230698,10 +230143,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:142499$6570_Y + connect \Y $gt$libresoc.v:142839$6502_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142500$6571 + cell $gt $gt$libresoc.v:142840$6503 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230709,10 +230154,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:142500$6571_Y + connect \Y $gt$libresoc.v:142840$6503_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142501$6572 + cell $gt $gt$libresoc.v:142841$6504 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230720,10 +230165,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:142501$6572_Y + connect \Y $gt$libresoc.v:142841$6504_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142502$6573 + cell $gt $gt$libresoc.v:142842$6505 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230731,10 +230176,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:142502$6573_Y + connect \Y $gt$libresoc.v:142842$6505_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142503$6574 + cell $gt $gt$libresoc.v:142843$6506 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230742,10 +230187,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:142503$6574_Y + connect \Y $gt$libresoc.v:142843$6506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142504$6575 + cell $gt $gt$libresoc.v:142844$6507 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230753,10 +230198,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:142504$6575_Y + connect \Y $gt$libresoc.v:142844$6507_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142505$6576 + cell $gt $gt$libresoc.v:142845$6508 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230764,10 +230209,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:142505$6576_Y + connect \Y $gt$libresoc.v:142845$6508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142506$6577 + cell $gt $gt$libresoc.v:142846$6509 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230775,10 +230220,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:142506$6577_Y + connect \Y $gt$libresoc.v:142846$6509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142507$6578 + cell $gt $gt$libresoc.v:142847$6510 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230786,10 +230231,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:142507$6578_Y + connect \Y $gt$libresoc.v:142847$6510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142508$6579 + cell $gt $gt$libresoc.v:142848$6511 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230797,10 +230242,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:142508$6579_Y + connect \Y $gt$libresoc.v:142848$6511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142509$6580 + cell $gt $gt$libresoc.v:142849$6512 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230808,10 +230253,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:142509$6580_Y + connect \Y $gt$libresoc.v:142849$6512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142510$6581 + cell $gt $gt$libresoc.v:142850$6513 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230819,10 +230264,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:142510$6581_Y + connect \Y $gt$libresoc.v:142850$6513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142511$6582 + cell $gt $gt$libresoc.v:142851$6514 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230830,10 +230275,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:142511$6582_Y + connect \Y $gt$libresoc.v:142851$6514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142512$6583 + cell $gt $gt$libresoc.v:142852$6515 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230841,10 +230286,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:142512$6583_Y + connect \Y $gt$libresoc.v:142852$6515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142513$6584 + cell $gt $gt$libresoc.v:142853$6516 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230852,10 +230297,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:142513$6584_Y + connect \Y $gt$libresoc.v:142853$6516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142514$6585 + cell $gt $gt$libresoc.v:142854$6517 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230863,10 +230308,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:142514$6585_Y + connect \Y $gt$libresoc.v:142854$6517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142515$6586 + cell $gt $gt$libresoc.v:142855$6518 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230874,10 +230319,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:142515$6586_Y + connect \Y $gt$libresoc.v:142855$6518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142516$6587 + cell $gt $gt$libresoc.v:142856$6519 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230885,10 +230330,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:142516$6587_Y + connect \Y $gt$libresoc.v:142856$6519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142517$6588 + cell $gt $gt$libresoc.v:142857$6520 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230896,10 +230341,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:142517$6588_Y + connect \Y $gt$libresoc.v:142857$6520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142518$6589 + cell $gt $gt$libresoc.v:142858$6521 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230907,18 +230352,18 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:142518$6589_Y + connect \Y $gt$libresoc.v:142858$6521_Y end - attribute \src "libresoc.v:142321.7-142321.20" - process $proc$libresoc.v:142321$6591 + attribute \src "libresoc.v:142661.7-142661.20" + process $proc$libresoc.v:142661$6523 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:142519.3-142906.6" - process $proc$libresoc.v:142519$6590 + attribute \src "libresoc.v:142859.3-143246.6" + process $proc$libresoc.v:142859$6522 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -230985,9 +230430,9 @@ module \left_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:142520.5-142520.29" + attribute \src "libresoc.v:142860.5-142860.29" switch \initial - attribute \src "libresoc.v:142520.9-142520.17" + attribute \src "libresoc.v:142860.9-142860.17" case 1'1 case end @@ -231570,86 +231015,86 @@ module \left_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:142455$6526_Y - connect \$99 $gt$libresoc.v:142456$6527_Y - connect \$101 $gt$libresoc.v:142457$6528_Y - connect \$103 $gt$libresoc.v:142458$6529_Y - connect \$105 $gt$libresoc.v:142459$6530_Y - connect \$107 $gt$libresoc.v:142460$6531_Y - connect \$109 $gt$libresoc.v:142461$6532_Y - connect \$111 $gt$libresoc.v:142462$6533_Y - connect \$113 $gt$libresoc.v:142463$6534_Y - connect \$115 $gt$libresoc.v:142464$6535_Y - connect \$117 $gt$libresoc.v:142465$6536_Y - connect \$11 $gt$libresoc.v:142466$6537_Y - connect \$119 $gt$libresoc.v:142467$6538_Y - connect \$121 $gt$libresoc.v:142468$6539_Y - connect \$123 $gt$libresoc.v:142469$6540_Y - connect \$125 $gt$libresoc.v:142470$6541_Y - connect \$127 $gt$libresoc.v:142471$6542_Y - connect \$13 $gt$libresoc.v:142472$6543_Y - connect \$15 $gt$libresoc.v:142473$6544_Y - connect \$17 $gt$libresoc.v:142474$6545_Y - connect \$1 $gt$libresoc.v:142475$6546_Y - connect \$19 $gt$libresoc.v:142476$6547_Y - connect \$21 $gt$libresoc.v:142477$6548_Y - connect \$23 $gt$libresoc.v:142478$6549_Y - connect \$25 $gt$libresoc.v:142479$6550_Y - connect \$27 $gt$libresoc.v:142480$6551_Y - connect \$29 $gt$libresoc.v:142481$6552_Y - connect \$31 $gt$libresoc.v:142482$6553_Y - connect \$33 $gt$libresoc.v:142483$6554_Y - connect \$35 $gt$libresoc.v:142484$6555_Y - connect \$37 $gt$libresoc.v:142485$6556_Y - connect \$3 $gt$libresoc.v:142486$6557_Y - connect \$39 $gt$libresoc.v:142487$6558_Y - connect \$41 $gt$libresoc.v:142488$6559_Y - connect \$43 $gt$libresoc.v:142489$6560_Y - connect \$45 $gt$libresoc.v:142490$6561_Y - connect \$47 $gt$libresoc.v:142491$6562_Y - connect \$49 $gt$libresoc.v:142492$6563_Y - connect \$51 $gt$libresoc.v:142493$6564_Y - connect \$53 $gt$libresoc.v:142494$6565_Y - connect \$55 $gt$libresoc.v:142495$6566_Y - connect \$57 $gt$libresoc.v:142496$6567_Y - connect \$5 $gt$libresoc.v:142497$6568_Y - connect \$59 $gt$libresoc.v:142498$6569_Y - connect \$61 $gt$libresoc.v:142499$6570_Y - connect \$63 $gt$libresoc.v:142500$6571_Y - connect \$65 $gt$libresoc.v:142501$6572_Y - connect \$67 $gt$libresoc.v:142502$6573_Y - connect \$69 $gt$libresoc.v:142503$6574_Y - connect \$71 $gt$libresoc.v:142504$6575_Y - connect \$73 $gt$libresoc.v:142505$6576_Y - connect \$75 $gt$libresoc.v:142506$6577_Y - connect \$77 $gt$libresoc.v:142507$6578_Y - connect \$7 $gt$libresoc.v:142508$6579_Y - connect \$79 $gt$libresoc.v:142509$6580_Y - connect \$81 $gt$libresoc.v:142510$6581_Y - connect \$83 $gt$libresoc.v:142511$6582_Y - connect \$85 $gt$libresoc.v:142512$6583_Y - connect \$87 $gt$libresoc.v:142513$6584_Y - connect \$89 $gt$libresoc.v:142514$6585_Y - connect \$91 $gt$libresoc.v:142515$6586_Y - connect \$93 $gt$libresoc.v:142516$6587_Y - connect \$95 $gt$libresoc.v:142517$6588_Y - connect \$97 $gt$libresoc.v:142518$6589_Y + connect \$9 $gt$libresoc.v:142795$6458_Y + connect \$99 $gt$libresoc.v:142796$6459_Y + connect \$101 $gt$libresoc.v:142797$6460_Y + connect \$103 $gt$libresoc.v:142798$6461_Y + connect \$105 $gt$libresoc.v:142799$6462_Y + connect \$107 $gt$libresoc.v:142800$6463_Y + connect \$109 $gt$libresoc.v:142801$6464_Y + connect \$111 $gt$libresoc.v:142802$6465_Y + connect \$113 $gt$libresoc.v:142803$6466_Y + connect \$115 $gt$libresoc.v:142804$6467_Y + connect \$117 $gt$libresoc.v:142805$6468_Y + connect \$11 $gt$libresoc.v:142806$6469_Y + connect \$119 $gt$libresoc.v:142807$6470_Y + connect \$121 $gt$libresoc.v:142808$6471_Y + connect \$123 $gt$libresoc.v:142809$6472_Y + connect \$125 $gt$libresoc.v:142810$6473_Y + connect \$127 $gt$libresoc.v:142811$6474_Y + connect \$13 $gt$libresoc.v:142812$6475_Y + connect \$15 $gt$libresoc.v:142813$6476_Y + connect \$17 $gt$libresoc.v:142814$6477_Y + connect \$1 $gt$libresoc.v:142815$6478_Y + connect \$19 $gt$libresoc.v:142816$6479_Y + connect \$21 $gt$libresoc.v:142817$6480_Y + connect \$23 $gt$libresoc.v:142818$6481_Y + connect \$25 $gt$libresoc.v:142819$6482_Y + connect \$27 $gt$libresoc.v:142820$6483_Y + connect \$29 $gt$libresoc.v:142821$6484_Y + connect \$31 $gt$libresoc.v:142822$6485_Y + connect \$33 $gt$libresoc.v:142823$6486_Y + connect \$35 $gt$libresoc.v:142824$6487_Y + connect \$37 $gt$libresoc.v:142825$6488_Y + connect \$3 $gt$libresoc.v:142826$6489_Y + connect \$39 $gt$libresoc.v:142827$6490_Y + connect \$41 $gt$libresoc.v:142828$6491_Y + connect \$43 $gt$libresoc.v:142829$6492_Y + connect \$45 $gt$libresoc.v:142830$6493_Y + connect \$47 $gt$libresoc.v:142831$6494_Y + connect \$49 $gt$libresoc.v:142832$6495_Y + connect \$51 $gt$libresoc.v:142833$6496_Y + connect \$53 $gt$libresoc.v:142834$6497_Y + connect \$55 $gt$libresoc.v:142835$6498_Y + connect \$57 $gt$libresoc.v:142836$6499_Y + connect \$5 $gt$libresoc.v:142837$6500_Y + connect \$59 $gt$libresoc.v:142838$6501_Y + connect \$61 $gt$libresoc.v:142839$6502_Y + connect \$63 $gt$libresoc.v:142840$6503_Y + connect \$65 $gt$libresoc.v:142841$6504_Y + connect \$67 $gt$libresoc.v:142842$6505_Y + connect \$69 $gt$libresoc.v:142843$6506_Y + connect \$71 $gt$libresoc.v:142844$6507_Y + connect \$73 $gt$libresoc.v:142845$6508_Y + connect \$75 $gt$libresoc.v:142846$6509_Y + connect \$77 $gt$libresoc.v:142847$6510_Y + connect \$7 $gt$libresoc.v:142848$6511_Y + connect \$79 $gt$libresoc.v:142849$6512_Y + connect \$81 $gt$libresoc.v:142850$6513_Y + connect \$83 $gt$libresoc.v:142851$6514_Y + connect \$85 $gt$libresoc.v:142852$6515_Y + connect \$87 $gt$libresoc.v:142853$6516_Y + connect \$89 $gt$libresoc.v:142854$6517_Y + connect \$91 $gt$libresoc.v:142855$6518_Y + connect \$93 $gt$libresoc.v:142856$6519_Y + connect \$95 $gt$libresoc.v:142857$6520_Y + connect \$97 $gt$libresoc.v:142858$6521_Y end -attribute \src "libresoc.v:142911.1-142940.10" +attribute \src "libresoc.v:143251.1-143280.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" attribute \generator "nMigen" module \lenexp - attribute \src "libresoc.v:142935.17-142935.101" - wire width 64 $extend$libresoc.v:142935$6595_Y - attribute \src "libresoc.v:142935.17-142935.101" - wire width 64 $pos$libresoc.v:142935$6596_Y - attribute \src "libresoc.v:142932.17-142932.111" - wire width 20 $sshl$libresoc.v:142932$6592_Y - attribute \src "libresoc.v:142934.17-142934.113" - wire width 32 $sshl$libresoc.v:142934$6594_Y - attribute \src "libresoc.v:142933.17-142933.107" - wire width 21 $sub$libresoc.v:142933$6593_Y + attribute \src "libresoc.v:143275.17-143275.101" + wire width 64 $extend$libresoc.v:143275$6527_Y + attribute \src "libresoc.v:143275.17-143275.101" + wire width 64 $pos$libresoc.v:143275$6528_Y + attribute \src "libresoc.v:143272.17-143272.111" + wire width 20 $sshl$libresoc.v:143272$6524_Y + attribute \src "libresoc.v:143274.17-143274.113" + wire width 32 $sshl$libresoc.v:143274$6526_Y + attribute \src "libresoc.v:143273.17-143273.107" + wire width 21 $sub$libresoc.v:143273$6525_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" wire width 21 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" @@ -231671,23 +231116,23 @@ module \lenexp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" wire width 176 output 3 \rexp_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $extend$libresoc.v:142935$6595 + cell $pos $extend$libresoc.v:143275$6527 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$7 - connect \Y $extend$libresoc.v:142935$6595_Y + connect \Y $extend$libresoc.v:143275$6527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $pos$libresoc.v:142935$6596 + cell $pos $pos$libresoc.v:143275$6528 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:142935$6595_Y - connect \Y $pos$libresoc.v:142935$6596_Y + connect \A $extend$libresoc.v:143275$6527_Y + connect \Y $pos$libresoc.v:143275$6528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sshl $sshl$libresoc.v:142932$6592 + cell $sshl $sshl$libresoc.v:143272$6524 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -231695,10 +231140,10 @@ module \lenexp parameter \Y_WIDTH 20 connect \A 5'00001 connect \B \len_i - connect \Y $sshl$libresoc.v:142932$6592_Y + connect \Y $sshl$libresoc.v:143272$6524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $sshl $sshl$libresoc.v:142934$6594 + cell $sshl $sshl$libresoc.v:143274$6526 parameter \A_SIGNED 0 parameter \A_WIDTH 17 parameter \B_SIGNED 0 @@ -231706,10 +231151,10 @@ module \lenexp parameter \Y_WIDTH 32 connect \A \binlen connect \B \addr_i - connect \Y $sshl$libresoc.v:142934$6594_Y + connect \Y $sshl$libresoc.v:143274$6526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sub $sub$libresoc.v:142933$6593 + cell $sub $sub$libresoc.v:143273$6525 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -231717,48 +231162,48 @@ module \lenexp parameter \Y_WIDTH 21 connect \A \$2 connect \B 1'1 - connect \Y $sub$libresoc.v:142933$6593_Y + connect \Y $sub$libresoc.v:143273$6525_Y end - connect \$2 $sshl$libresoc.v:142932$6592_Y - connect \$4 $sub$libresoc.v:142933$6593_Y - connect \$7 $sshl$libresoc.v:142934$6594_Y - connect \$6 $pos$libresoc.v:142935$6596_Y + connect \$2 $sshl$libresoc.v:143272$6524_Y + connect \$4 $sub$libresoc.v:143273$6525_Y + connect \$7 $sshl$libresoc.v:143274$6526_Y + connect \$6 $pos$libresoc.v:143275$6528_Y connect \$1 \$4 connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } connect \lexp_o \$6 connect \binlen \$4 [16:0] end -attribute \src "libresoc.v:142944.1-143002.10" +attribute \src "libresoc.v:143284.1-143342.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" attribute \generator "nMigen" module \lod_l - attribute \src "libresoc.v:142945.7-142945.20" + attribute \src "libresoc.v:143285.7-143285.20" wire $0\initial[0:0] - attribute \src "libresoc.v:142990.3-142998.6" - wire $0\q_int$next[0:0]$6607 - attribute \src "libresoc.v:142988.3-142989.27" + attribute \src "libresoc.v:143330.3-143338.6" + wire $0\q_int$next[0:0]$6539 + attribute \src "libresoc.v:143328.3-143329.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:142990.3-142998.6" - wire $1\q_int$next[0:0]$6608 - attribute \src "libresoc.v:142967.7-142967.19" + attribute \src "libresoc.v:143330.3-143338.6" + wire $1\q_int$next[0:0]$6540 + attribute \src "libresoc.v:143307.7-143307.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:142980.17-142980.96" - wire $and$libresoc.v:142980$6597_Y - attribute \src "libresoc.v:142985.17-142985.96" - wire $and$libresoc.v:142985$6602_Y - attribute \src "libresoc.v:142982.18-142982.93" - wire $not$libresoc.v:142982$6599_Y - attribute \src "libresoc.v:142984.17-142984.92" - wire $not$libresoc.v:142984$6601_Y - attribute \src "libresoc.v:142987.17-142987.92" - wire $not$libresoc.v:142987$6604_Y - attribute \src "libresoc.v:142981.18-142981.98" - wire $or$libresoc.v:142981$6598_Y - attribute \src "libresoc.v:142983.18-142983.99" - wire $or$libresoc.v:142983$6600_Y - attribute \src "libresoc.v:142986.17-142986.97" - wire $or$libresoc.v:142986$6603_Y + attribute \src "libresoc.v:143320.17-143320.96" + wire $and$libresoc.v:143320$6529_Y + attribute \src "libresoc.v:143325.17-143325.96" + wire $and$libresoc.v:143325$6534_Y + attribute \src "libresoc.v:143322.18-143322.93" + wire $not$libresoc.v:143322$6531_Y + attribute \src "libresoc.v:143324.17-143324.92" + wire $not$libresoc.v:143324$6533_Y + attribute \src "libresoc.v:143327.17-143327.92" + wire $not$libresoc.v:143327$6536_Y + attribute \src "libresoc.v:143321.18-143321.98" + wire $or$libresoc.v:143321$6530_Y + attribute \src "libresoc.v:143323.18-143323.99" + wire $or$libresoc.v:143323$6532_Y + attribute \src "libresoc.v:143326.17-143326.97" + wire $or$libresoc.v:143326$6535_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -231775,11 +231220,11 @@ module \lod_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:142945.7-142945.15" + attribute \src "libresoc.v:143285.7-143285.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -231796,7 +231241,7 @@ module \lod_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:142980$6597 + cell $and $and$libresoc.v:143320$6529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231804,10 +231249,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:142980$6597_Y + connect \Y $and$libresoc.v:143320$6529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:142985$6602 + cell $and $and$libresoc.v:143325$6534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231815,34 +231260,34 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:142985$6602_Y + connect \Y $and$libresoc.v:143325$6534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:142982$6599 + cell $not $not$libresoc.v:143322$6531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lod - connect \Y $not$libresoc.v:142982$6599_Y + connect \Y $not$libresoc.v:143322$6531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:142984$6601 + cell $not $not$libresoc.v:143324$6533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:142984$6601_Y + connect \Y $not$libresoc.v:143324$6533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:142987$6604 + cell $not $not$libresoc.v:143327$6536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:142987$6604_Y + connect \Y $not$libresoc.v:143327$6536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:142981$6598 + cell $or $or$libresoc.v:143321$6530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231850,10 +231295,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lod - connect \Y $or$libresoc.v:142981$6598_Y + connect \Y $or$libresoc.v:143321$6530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:142983$6600 + cell $or $or$libresoc.v:143323$6532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231861,10 +231306,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_lod connect \B \q_int - connect \Y $or$libresoc.v:142983$6600_Y + connect \Y $or$libresoc.v:143323$6532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:142986$6603 + cell $or $or$libresoc.v:143326$6535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231872,39 +231317,39 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lod - connect \Y $or$libresoc.v:142986$6603_Y + connect \Y $or$libresoc.v:143326$6535_Y end - attribute \src "libresoc.v:142945.7-142945.20" - process $proc$libresoc.v:142945$6609 + attribute \src "libresoc.v:143285.7-143285.20" + process $proc$libresoc.v:143285$6541 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:142967.7-142967.19" - process $proc$libresoc.v:142967$6610 + attribute \src "libresoc.v:143307.7-143307.19" + process $proc$libresoc.v:143307$6542 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:142988.3-142989.27" - process $proc$libresoc.v:142988$6605 + attribute \src "libresoc.v:143328.3-143329.27" + process $proc$libresoc.v:143328$6537 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:142990.3-142998.6" - process $proc$libresoc.v:142990$6606 + attribute \src "libresoc.v:143330.3-143338.6" + process $proc$libresoc.v:143330$6538 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$6607 $1\q_int$next[0:0]$6608 - attribute \src "libresoc.v:142991.5-142991.29" + assign $0\q_int$next[0:0]$6539 $1\q_int$next[0:0]$6540 + attribute \src "libresoc.v:143331.5-143331.29" switch \initial - attribute \src "libresoc.v:142991.9-142991.17" + attribute \src "libresoc.v:143331.9-143331.17" case 1'1 case end @@ -231913,494 +231358,494 @@ module \lod_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6608 1'0 + assign $1\q_int$next[0:0]$6540 1'0 case - assign $1\q_int$next[0:0]$6608 \$5 + assign $1\q_int$next[0:0]$6540 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$6607 + update \q_int$next $0\q_int$next[0:0]$6539 end - connect \$9 $and$libresoc.v:142980$6597_Y - connect \$11 $or$libresoc.v:142981$6598_Y - connect \$13 $not$libresoc.v:142982$6599_Y - connect \$15 $or$libresoc.v:142983$6600_Y - connect \$1 $not$libresoc.v:142984$6601_Y - connect \$3 $and$libresoc.v:142985$6602_Y - connect \$5 $or$libresoc.v:142986$6603_Y - connect \$7 $not$libresoc.v:142987$6604_Y + connect \$9 $and$libresoc.v:143320$6529_Y + connect \$11 $or$libresoc.v:143321$6530_Y + connect \$13 $not$libresoc.v:143322$6531_Y + connect \$15 $or$libresoc.v:143323$6532_Y + connect \$1 $not$libresoc.v:143324$6533_Y + connect \$3 $and$libresoc.v:143325$6534_Y + connect \$5 $or$libresoc.v:143326$6535_Y + connect \$7 $not$libresoc.v:143327$6536_Y connect \qlq_lod \$15 connect \qn_lod \$13 connect \q_lod \$11 end -attribute \src "libresoc.v:143006.1-144126.10" +attribute \src "libresoc.v:143346.1-144466.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" attribute \generator "nMigen" module \logical0 - attribute \src "libresoc.v:143751.3-143752.24" + attribute \src "libresoc.v:144091.3-144092.24" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:143749.3-143750.44" + attribute \src "libresoc.v:144089.3-144090.44" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:144056.3-144064.6" - wire $0\alu_l_r_alu$next[0:0]$6811 - attribute \src "libresoc.v:143673.3-143674.39" + attribute \src "libresoc.v:144396.3-144404.6" + wire $0\alu_l_r_alu$next[0:0]$6743 + attribute \src "libresoc.v:144013.3-144014.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6740 - attribute \src "libresoc.v:143723.3-143724.83" + attribute \src "libresoc.v:144274.3-144312.6" + wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6672 + attribute \src "libresoc.v:144063.3-144064.83" wire width 4 $0\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 - attribute \src "libresoc.v:143693.3-143694.81" + attribute \src "libresoc.v:144274.3-144312.6" + wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6673 + attribute \src "libresoc.v:144033.3-144034.81" wire width 14 $0\alu_logical0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 - attribute \src "libresoc.v:143695.3-143696.95" + attribute \src "libresoc.v:144274.3-144312.6" + wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6674 + attribute \src "libresoc.v:144035.3-144036.95" wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 - attribute \src "libresoc.v:143697.3-143698.91" + attribute \src "libresoc.v:144274.3-144312.6" + wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6675 + attribute \src "libresoc.v:144037.3-144038.91" wire $0\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 - attribute \src "libresoc.v:143711.3-143712.89" + attribute \src "libresoc.v:144274.3-144312.6" + wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6676 + attribute \src "libresoc.v:144051.3-144052.89" wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6745 - attribute \src "libresoc.v:143725.3-143726.75" + attribute \src "libresoc.v:144274.3-144312.6" + wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6677 + attribute \src "libresoc.v:144065.3-144066.75" wire width 32 $0\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 - attribute \src "libresoc.v:143691.3-143692.85" + attribute \src "libresoc.v:144274.3-144312.6" + wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6678 + attribute \src "libresoc.v:144031.3-144032.85" wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 - attribute \src "libresoc.v:143707.3-143708.85" + attribute \src "libresoc.v:144274.3-144312.6" + wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6679 + attribute \src "libresoc.v:144047.3-144048.85" wire $0\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 - attribute \src "libresoc.v:143713.3-143714.87" + attribute \src "libresoc.v:144274.3-144312.6" + wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6680 + attribute \src "libresoc.v:144053.3-144054.87" wire $0\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 - attribute \src "libresoc.v:143719.3-143720.83" + attribute \src "libresoc.v:144274.3-144312.6" + wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6681 + attribute \src "libresoc.v:144059.3-144060.83" wire $0\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 - attribute \src "libresoc.v:143721.3-143722.85" + attribute \src "libresoc.v:144274.3-144312.6" + wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6682 + attribute \src "libresoc.v:144061.3-144062.85" wire $0\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 - attribute \src "libresoc.v:143703.3-143704.79" + attribute \src "libresoc.v:144274.3-144312.6" + wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6683 + attribute \src "libresoc.v:144043.3-144044.79" wire $0\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 - attribute \src "libresoc.v:143705.3-143706.79" + attribute \src "libresoc.v:144274.3-144312.6" + wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6684 + attribute \src "libresoc.v:144045.3-144046.79" wire $0\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 - attribute \src "libresoc.v:143717.3-143718.91" + attribute \src "libresoc.v:144274.3-144312.6" + wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6685 + attribute \src "libresoc.v:144057.3-144058.91" wire $0\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 - attribute \src "libresoc.v:143701.3-143702.79" + attribute \src "libresoc.v:144274.3-144312.6" + wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6686 + attribute \src "libresoc.v:144041.3-144042.79" wire $0\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 - attribute \src "libresoc.v:143699.3-143700.79" + attribute \src "libresoc.v:144274.3-144312.6" + wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6687 + attribute \src "libresoc.v:144039.3-144040.79" wire $0\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 - attribute \src "libresoc.v:143715.3-143716.85" + attribute \src "libresoc.v:144274.3-144312.6" + wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6688 + attribute \src "libresoc.v:144055.3-144056.85" wire $0\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 - attribute \src "libresoc.v:143709.3-143710.79" + attribute \src "libresoc.v:144274.3-144312.6" + wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6689 + attribute \src "libresoc.v:144049.3-144050.79" wire $0\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:144047.3-144055.6" - wire $0\alui_l_r_alui$next[0:0]$6808 - attribute \src "libresoc.v:143675.3-143676.43" + attribute \src "libresoc.v:144387.3-144395.6" + wire $0\alui_l_r_alui$next[0:0]$6740 + attribute \src "libresoc.v:144015.3-144016.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:143973.3-143994.6" - wire width 64 $0\data_r0__o$next[63:0]$6783 - attribute \src "libresoc.v:143687.3-143688.37" + attribute \src "libresoc.v:144313.3-144334.6" + wire width 64 $0\data_r0__o$next[63:0]$6715 + attribute \src "libresoc.v:144027.3-144028.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:143973.3-143994.6" - wire $0\data_r0__o_ok$next[0:0]$6784 - attribute \src "libresoc.v:143689.3-143690.43" + attribute \src "libresoc.v:144313.3-144334.6" + wire $0\data_r0__o_ok$next[0:0]$6716 + attribute \src "libresoc.v:144029.3-144030.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:143995.3-144016.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$6791 - attribute \src "libresoc.v:143683.3-143684.43" + attribute \src "libresoc.v:144335.3-144356.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$6723 + attribute \src "libresoc.v:144023.3-144024.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:143995.3-144016.6" - wire $0\data_r1__cr_a_ok$next[0:0]$6792 - attribute \src "libresoc.v:143685.3-143686.49" + attribute \src "libresoc.v:144335.3-144356.6" + wire $0\data_r1__cr_a_ok$next[0:0]$6724 + attribute \src "libresoc.v:144025.3-144026.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:144065.3-144074.6" + attribute \src "libresoc.v:144405.3-144414.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:144075.3-144084.6" + attribute \src "libresoc.v:144415.3-144424.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:143007.7-143007.20" + attribute \src "libresoc.v:143347.7-143347.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143889.3-143897.6" - wire $0\opc_l_r_opc$next[0:0]$6725 - attribute \src "libresoc.v:143735.3-143736.39" + attribute \src "libresoc.v:144229.3-144237.6" + wire $0\opc_l_r_opc$next[0:0]$6657 + attribute \src "libresoc.v:144075.3-144076.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:143880.3-143888.6" - wire $0\opc_l_s_opc$next[0:0]$6722 - attribute \src "libresoc.v:143737.3-143738.39" + attribute \src "libresoc.v:144220.3-144228.6" + wire $0\opc_l_s_opc$next[0:0]$6654 + attribute \src "libresoc.v:144077.3-144078.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:144085.3-144093.6" - wire width 2 $0\prev_wr_go$next[1:0]$6816 - attribute \src "libresoc.v:143747.3-143748.37" + attribute \src "libresoc.v:144425.3-144433.6" + wire width 2 $0\prev_wr_go$next[1:0]$6748 + attribute \src "libresoc.v:144087.3-144088.37" wire width 2 $0\prev_wr_go[1:0] - attribute \src "libresoc.v:143834.3-143843.6" + attribute \src "libresoc.v:144174.3-144183.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:143925.3-143933.6" - wire width 2 $0\req_l_r_req$next[1:0]$6737 - attribute \src "libresoc.v:143727.3-143728.39" + attribute \src "libresoc.v:144265.3-144273.6" + wire width 2 $0\req_l_r_req$next[1:0]$6669 + attribute \src "libresoc.v:144067.3-144068.39" wire width 2 $0\req_l_r_req[1:0] - attribute \src "libresoc.v:143916.3-143924.6" - wire width 2 $0\req_l_s_req$next[1:0]$6734 - attribute \src "libresoc.v:143729.3-143730.39" + attribute \src "libresoc.v:144256.3-144264.6" + wire width 2 $0\req_l_s_req$next[1:0]$6666 + attribute \src "libresoc.v:144069.3-144070.39" wire width 2 $0\req_l_s_req[1:0] - attribute \src "libresoc.v:143853.3-143861.6" - wire $0\rok_l_r_rdok$next[0:0]$6713 - attribute \src "libresoc.v:143743.3-143744.41" + attribute \src "libresoc.v:144193.3-144201.6" + wire $0\rok_l_r_rdok$next[0:0]$6645 + attribute \src "libresoc.v:144083.3-144084.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:143844.3-143852.6" - wire $0\rok_l_s_rdok$next[0:0]$6710 - attribute \src "libresoc.v:143745.3-143746.41" + attribute \src "libresoc.v:144184.3-144192.6" + wire $0\rok_l_s_rdok$next[0:0]$6642 + attribute \src "libresoc.v:144085.3-144086.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:143871.3-143879.6" - wire $0\rst_l_r_rst$next[0:0]$6719 - attribute \src "libresoc.v:143739.3-143740.39" + attribute \src "libresoc.v:144211.3-144219.6" + wire $0\rst_l_r_rst$next[0:0]$6651 + attribute \src "libresoc.v:144079.3-144080.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:143862.3-143870.6" - wire $0\rst_l_s_rst$next[0:0]$6716 - attribute \src "libresoc.v:143741.3-143742.39" + attribute \src "libresoc.v:144202.3-144210.6" + wire $0\rst_l_s_rst$next[0:0]$6648 + attribute \src "libresoc.v:144081.3-144082.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:143907.3-143915.6" - wire width 3 $0\src_l_r_src$next[2:0]$6731 - attribute \src "libresoc.v:143731.3-143732.39" + attribute \src "libresoc.v:144247.3-144255.6" + wire width 3 $0\src_l_r_src$next[2:0]$6663 + attribute \src "libresoc.v:144071.3-144072.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:143898.3-143906.6" - wire width 3 $0\src_l_s_src$next[2:0]$6728 - attribute \src "libresoc.v:143733.3-143734.39" + attribute \src "libresoc.v:144238.3-144246.6" + wire width 3 $0\src_l_s_src$next[2:0]$6660 + attribute \src "libresoc.v:144073.3-144074.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:144017.3-144026.6" - wire width 64 $0\src_r0$next[63:0]$6799 - attribute \src "libresoc.v:143681.3-143682.29" + attribute \src "libresoc.v:144357.3-144366.6" + wire width 64 $0\src_r0$next[63:0]$6731 + attribute \src "libresoc.v:144021.3-144022.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:144027.3-144036.6" - wire width 64 $0\src_r1$next[63:0]$6802 - attribute \src "libresoc.v:143679.3-143680.29" + attribute \src "libresoc.v:144367.3-144376.6" + wire width 64 $0\src_r1$next[63:0]$6734 + attribute \src "libresoc.v:144019.3-144020.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:144037.3-144046.6" - wire $0\src_r2$next[0:0]$6805 - attribute \src "libresoc.v:143677.3-143678.29" + attribute \src "libresoc.v:144377.3-144386.6" + wire $0\src_r2$next[0:0]$6737 + attribute \src "libresoc.v:144017.3-144018.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:143125.7-143125.24" + attribute \src "libresoc.v:143465.7-143465.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:143135.7-143135.26" + attribute \src "libresoc.v:143475.7-143475.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:144056.3-144064.6" - wire $1\alu_l_r_alu$next[0:0]$6812 - attribute \src "libresoc.v:143143.7-143143.25" + attribute \src "libresoc.v:144396.3-144404.6" + wire $1\alu_l_r_alu$next[0:0]$6744 + attribute \src "libresoc.v:143483.7-143483.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 - attribute \src "libresoc.v:143151.13-143151.53" + attribute \src "libresoc.v:144274.3-144312.6" + wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6690 + attribute \src "libresoc.v:143491.13-143491.53" wire width 4 $1\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 - attribute \src "libresoc.v:143170.14-143170.57" + attribute \src "libresoc.v:144274.3-144312.6" + wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6691 + attribute \src "libresoc.v:143510.14-143510.57" wire width 14 $1\alu_logical0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 - attribute \src "libresoc.v:143174.14-143174.76" + attribute \src "libresoc.v:144274.3-144312.6" + wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6692 + attribute \src "libresoc.v:143514.14-143514.76" wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 - attribute \src "libresoc.v:143178.7-143178.51" + attribute \src "libresoc.v:144274.3-144312.6" + wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6693 + attribute \src "libresoc.v:143518.7-143518.51" wire $1\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 - attribute \src "libresoc.v:143186.13-143186.56" + attribute \src "libresoc.v:144274.3-144312.6" + wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6694 + attribute \src "libresoc.v:143526.13-143526.56" wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6763 - attribute \src "libresoc.v:143190.14-143190.51" + attribute \src "libresoc.v:144274.3-144312.6" + wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6695 + attribute \src "libresoc.v:143530.14-143530.51" wire width 32 $1\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 - attribute \src "libresoc.v:143269.13-143269.55" + attribute \src "libresoc.v:144274.3-144312.6" + wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6696 + attribute \src "libresoc.v:143609.13-143609.55" wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 - attribute \src "libresoc.v:143273.7-143273.48" + attribute \src "libresoc.v:144274.3-144312.6" + wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6697 + attribute \src "libresoc.v:143613.7-143613.48" wire $1\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 - attribute \src "libresoc.v:143277.7-143277.49" + attribute \src "libresoc.v:144274.3-144312.6" + wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6698 + attribute \src "libresoc.v:143617.7-143617.49" wire $1\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 - attribute \src "libresoc.v:143281.7-143281.47" + attribute \src "libresoc.v:144274.3-144312.6" + wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6699 + attribute \src "libresoc.v:143621.7-143621.47" wire $1\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 - attribute \src "libresoc.v:143285.7-143285.48" + attribute \src "libresoc.v:144274.3-144312.6" + wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6700 + attribute \src "libresoc.v:143625.7-143625.48" wire $1\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 - attribute \src "libresoc.v:143289.7-143289.45" + attribute \src "libresoc.v:144274.3-144312.6" + wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6701 + attribute \src "libresoc.v:143629.7-143629.45" wire $1\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 - attribute \src "libresoc.v:143293.7-143293.45" + attribute \src "libresoc.v:144274.3-144312.6" + wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6702 + attribute \src "libresoc.v:143633.7-143633.45" wire $1\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 - attribute \src "libresoc.v:143297.7-143297.51" + attribute \src "libresoc.v:144274.3-144312.6" + wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6703 + attribute \src "libresoc.v:143637.7-143637.51" wire $1\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 - attribute \src "libresoc.v:143301.7-143301.45" + attribute \src "libresoc.v:144274.3-144312.6" + wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6704 + attribute \src "libresoc.v:143641.7-143641.45" wire $1\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 - attribute \src "libresoc.v:143305.7-143305.45" + attribute \src "libresoc.v:144274.3-144312.6" + wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6705 + attribute \src "libresoc.v:143645.7-143645.45" wire $1\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 - attribute \src "libresoc.v:143309.7-143309.48" + attribute \src "libresoc.v:144274.3-144312.6" + wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6706 + attribute \src "libresoc.v:143649.7-143649.48" wire $1\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 - attribute \src "libresoc.v:143313.7-143313.45" + attribute \src "libresoc.v:144274.3-144312.6" + wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6707 + attribute \src "libresoc.v:143653.7-143653.45" wire $1\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:144047.3-144055.6" - wire $1\alui_l_r_alui$next[0:0]$6809 - attribute \src "libresoc.v:143339.7-143339.27" + attribute \src "libresoc.v:144387.3-144395.6" + wire $1\alui_l_r_alui$next[0:0]$6741 + attribute \src "libresoc.v:143679.7-143679.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:143973.3-143994.6" - wire width 64 $1\data_r0__o$next[63:0]$6785 - attribute \src "libresoc.v:143373.14-143373.47" + attribute \src "libresoc.v:144313.3-144334.6" + wire width 64 $1\data_r0__o$next[63:0]$6717 + attribute \src "libresoc.v:143713.14-143713.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:143973.3-143994.6" - wire $1\data_r0__o_ok$next[0:0]$6786 - attribute \src "libresoc.v:143377.7-143377.27" + attribute \src "libresoc.v:144313.3-144334.6" + wire $1\data_r0__o_ok$next[0:0]$6718 + attribute \src "libresoc.v:143717.7-143717.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:143995.3-144016.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$6793 - attribute \src "libresoc.v:143381.13-143381.33" + attribute \src "libresoc.v:144335.3-144356.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$6725 + attribute \src "libresoc.v:143721.13-143721.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:143995.3-144016.6" - wire $1\data_r1__cr_a_ok$next[0:0]$6794 - attribute \src "libresoc.v:143385.7-143385.30" + attribute \src "libresoc.v:144335.3-144356.6" + wire $1\data_r1__cr_a_ok$next[0:0]$6726 + attribute \src "libresoc.v:143725.7-143725.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:144065.3-144074.6" + attribute \src "libresoc.v:144405.3-144414.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:144075.3-144084.6" + attribute \src "libresoc.v:144415.3-144424.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:143889.3-143897.6" - wire $1\opc_l_r_opc$next[0:0]$6726 - attribute \src "libresoc.v:143399.7-143399.25" + attribute \src "libresoc.v:144229.3-144237.6" + wire $1\opc_l_r_opc$next[0:0]$6658 + attribute \src "libresoc.v:143739.7-143739.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:143880.3-143888.6" - wire $1\opc_l_s_opc$next[0:0]$6723 - attribute \src "libresoc.v:143403.7-143403.25" + attribute \src "libresoc.v:144220.3-144228.6" + wire $1\opc_l_s_opc$next[0:0]$6655 + attribute \src "libresoc.v:143743.7-143743.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:144085.3-144093.6" - wire width 2 $1\prev_wr_go$next[1:0]$6817 - attribute \src "libresoc.v:143537.13-143537.30" + attribute \src "libresoc.v:144425.3-144433.6" + wire width 2 $1\prev_wr_go$next[1:0]$6749 + attribute \src "libresoc.v:143877.13-143877.30" wire width 2 $1\prev_wr_go[1:0] - attribute \src "libresoc.v:143834.3-143843.6" + attribute \src "libresoc.v:144174.3-144183.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:143925.3-143933.6" - wire width 2 $1\req_l_r_req$next[1:0]$6738 - attribute \src "libresoc.v:143545.13-143545.31" + attribute \src "libresoc.v:144265.3-144273.6" + wire width 2 $1\req_l_r_req$next[1:0]$6670 + attribute \src "libresoc.v:143885.13-143885.31" wire width 2 $1\req_l_r_req[1:0] - attribute \src "libresoc.v:143916.3-143924.6" - wire width 2 $1\req_l_s_req$next[1:0]$6735 - attribute \src "libresoc.v:143549.13-143549.31" + attribute \src "libresoc.v:144256.3-144264.6" + wire width 2 $1\req_l_s_req$next[1:0]$6667 + attribute \src "libresoc.v:143889.13-143889.31" wire width 2 $1\req_l_s_req[1:0] - attribute \src "libresoc.v:143853.3-143861.6" - wire $1\rok_l_r_rdok$next[0:0]$6714 - attribute \src "libresoc.v:143561.7-143561.26" + attribute \src "libresoc.v:144193.3-144201.6" + wire $1\rok_l_r_rdok$next[0:0]$6646 + attribute \src "libresoc.v:143901.7-143901.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:143844.3-143852.6" - wire $1\rok_l_s_rdok$next[0:0]$6711 - attribute \src "libresoc.v:143565.7-143565.26" + attribute \src "libresoc.v:144184.3-144192.6" + wire $1\rok_l_s_rdok$next[0:0]$6643 + attribute \src "libresoc.v:143905.7-143905.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:143871.3-143879.6" - wire $1\rst_l_r_rst$next[0:0]$6720 - attribute \src "libresoc.v:143569.7-143569.25" + attribute \src "libresoc.v:144211.3-144219.6" + wire $1\rst_l_r_rst$next[0:0]$6652 + attribute \src "libresoc.v:143909.7-143909.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:143862.3-143870.6" - wire $1\rst_l_s_rst$next[0:0]$6717 - attribute \src "libresoc.v:143573.7-143573.25" + attribute \src "libresoc.v:144202.3-144210.6" + wire $1\rst_l_s_rst$next[0:0]$6649 + attribute \src "libresoc.v:143913.7-143913.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:143907.3-143915.6" - wire width 3 $1\src_l_r_src$next[2:0]$6732 - attribute \src "libresoc.v:143587.13-143587.31" + attribute \src "libresoc.v:144247.3-144255.6" + wire width 3 $1\src_l_r_src$next[2:0]$6664 + attribute \src "libresoc.v:143927.13-143927.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:143898.3-143906.6" - wire width 3 $1\src_l_s_src$next[2:0]$6729 - attribute \src "libresoc.v:143591.13-143591.31" + attribute \src "libresoc.v:144238.3-144246.6" + wire width 3 $1\src_l_s_src$next[2:0]$6661 + attribute \src "libresoc.v:143931.13-143931.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:144017.3-144026.6" - wire width 64 $1\src_r0$next[63:0]$6800 - attribute \src "libresoc.v:143599.14-143599.43" + attribute \src "libresoc.v:144357.3-144366.6" + wire width 64 $1\src_r0$next[63:0]$6732 + attribute \src "libresoc.v:143939.14-143939.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:144027.3-144036.6" - wire width 64 $1\src_r1$next[63:0]$6803 - attribute \src "libresoc.v:143603.14-143603.43" + attribute \src "libresoc.v:144367.3-144376.6" + wire width 64 $1\src_r1$next[63:0]$6735 + attribute \src "libresoc.v:143943.14-143943.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:144037.3-144046.6" - wire $1\src_r2$next[0:0]$6806 - attribute \src "libresoc.v:143607.7-143607.20" + attribute \src "libresoc.v:144377.3-144386.6" + wire $1\src_r2$next[0:0]$6738 + attribute \src "libresoc.v:143947.7-143947.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:143934.3-143972.6" - wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 - attribute \src "libresoc.v:143934.3-143972.6" - wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 - attribute \src "libresoc.v:143934.3-143972.6" - wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 - attribute \src "libresoc.v:143934.3-143972.6" - wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 - attribute \src "libresoc.v:143934.3-143972.6" - wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 - attribute \src "libresoc.v:143934.3-143972.6" - wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 - attribute \src "libresoc.v:143973.3-143994.6" - wire width 64 $2\data_r0__o$next[63:0]$6787 - attribute \src "libresoc.v:143973.3-143994.6" - wire $2\data_r0__o_ok$next[0:0]$6788 - attribute \src "libresoc.v:143995.3-144016.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$6795 - attribute \src "libresoc.v:143995.3-144016.6" - wire $2\data_r1__cr_a_ok$next[0:0]$6796 - attribute \src "libresoc.v:143973.3-143994.6" - wire $3\data_r0__o_ok$next[0:0]$6789 - attribute \src "libresoc.v:143995.3-144016.6" - wire $3\data_r1__cr_a_ok$next[0:0]$6797 - attribute \src "libresoc.v:143616.17-143616.109" - wire $and$libresoc.v:143616$6611_Y - attribute \src "libresoc.v:143617.18-143617.130" - wire width 3 $and$libresoc.v:143617$6612_Y - attribute \src "libresoc.v:143619.19-143619.114" - wire width 3 $and$libresoc.v:143619$6614_Y - attribute \src "libresoc.v:143620.19-143620.125" - wire $and$libresoc.v:143620$6615_Y - attribute \src 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"libresoc.v:143641.18-143641.113" - wire $and$libresoc.v:143641$6636_Y - attribute \src "libresoc.v:143642.18-143642.125" - wire width 2 $and$libresoc.v:143642$6637_Y - attribute \src "libresoc.v:143644.18-143644.112" - wire $and$libresoc.v:143644$6639_Y - attribute \src "libresoc.v:143647.18-143647.130" - wire $and$libresoc.v:143647$6642_Y - attribute \src "libresoc.v:143648.18-143648.130" - wire $and$libresoc.v:143648$6643_Y - attribute \src "libresoc.v:143649.18-143649.117" - wire $and$libresoc.v:143649$6644_Y - attribute \src "libresoc.v:143654.18-143654.134" - wire $and$libresoc.v:143654$6649_Y - attribute \src "libresoc.v:143655.18-143655.124" - wire width 2 $and$libresoc.v:143655$6650_Y - attribute \src "libresoc.v:143658.18-143658.116" - wire $and$libresoc.v:143658$6653_Y - attribute \src "libresoc.v:143659.18-143659.119" - wire $and$libresoc.v:143659$6654_Y - attribute \src "libresoc.v:143668.18-143668.138" - wire $and$libresoc.v:143668$6663_Y - attribute \src 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"libresoc.v:143993.18-143993.155" + wire width 3 $or$libresoc.v:143993$6580_Y + attribute \src "libresoc.v:143996.18-143996.120" + wire width 2 $or$libresoc.v:143996$6583_Y + attribute \src "libresoc.v:143997.17-143997.117" + wire width 3 $or$libresoc.v:143997$6584_Y + attribute \src "libresoc.v:144003.17-144003.104" + wire $reduce_and$libresoc.v:144003$6590_Y + attribute \src "libresoc.v:143974.18-143974.106" + wire $reduce_or$libresoc.v:143974$6561_Y + attribute \src "libresoc.v:143977.18-143977.113" + wire $reduce_or$libresoc.v:143977$6564_Y + attribute \src "libresoc.v:143978.18-143978.112" + wire $reduce_or$libresoc.v:143978$6565_Y + attribute \src "libresoc.v:144000.18-144000.162" + wire $ternary$libresoc.v:144000$6587_Y + attribute \src "libresoc.v:144001.18-144001.163" + wire width 64 $ternary$libresoc.v:144001$6588_Y + attribute \src "libresoc.v:144002.18-144002.168" + wire $ternary$libresoc.v:144002$6589_Y + attribute \src "libresoc.v:144004.18-144004.188" + wire width 64 $ternary$libresoc.v:144004$6591_Y + attribute \src "libresoc.v:144005.18-144005.115" + wire width 64 $ternary$libresoc.v:144005$6592_Y + attribute \src "libresoc.v:144006.18-144006.125" + wire width 64 $ternary$libresoc.v:144006$6593_Y + attribute \src "libresoc.v:144007.18-144007.118" + wire $ternary$libresoc.v:144007$6594_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -232541,7 +231986,7 @@ module \logical0 wire \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \alu_logical0_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_logical0_logical_op__data_len @@ -232713,7 +232158,7 @@ module \logical0 wire \alu_logical0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_logical0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_logical0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_logical0_p_ready_o @@ -232737,11 +232182,11 @@ module \logical0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 32 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 21 \cu_busy_o @@ -232785,9 +232230,9 @@ module \logical0 wire width 64 output 31 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 33 \dest2_o - attribute \src "libresoc.v:143007.7-143007.15" + attribute \src "libresoc.v:143347.7-143347.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc @@ -232972,9 +232417,9 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 25 \src1_i + wire width 64 input 26 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 26 \src2_i + wire width 64 input 25 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 27 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" @@ -233010,7 +232455,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:143616$6611 + cell $and $and$libresoc.v:143956$6543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233018,10 +232463,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:143616$6611_Y + connect \Y $and$libresoc.v:143956$6543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:143617$6612 + cell $and $and$libresoc.v:143957$6544 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233029,10 +232474,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$93 connect \B { 1'1 \$97 \$95 } - connect \Y $and$libresoc.v:143617$6612_Y + connect \Y $and$libresoc.v:143957$6544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:143619$6614 + cell $and $and$libresoc.v:143959$6546 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233040,10 +232485,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$99 connect \B \$101 - connect \Y $and$libresoc.v:143619$6614_Y + connect \Y $and$libresoc.v:143959$6546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:143620$6615 + cell $and $and$libresoc.v:143960$6547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233051,10 +232496,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:143620$6615_Y + connect \Y $and$libresoc.v:143960$6547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:143621$6616 + cell $and $and$libresoc.v:143961$6548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233062,10 +232507,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:143621$6616_Y + connect \Y $and$libresoc.v:143961$6548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:143622$6617 + cell $and $and$libresoc.v:143962$6549 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233073,10 +232518,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B { \$105 \$107 } - connect \Y $and$libresoc.v:143622$6617_Y + connect \Y $and$libresoc.v:143962$6549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:143623$6618 + cell $and $and$libresoc.v:143963$6550 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233084,10 +232529,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \$109 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:143623$6618_Y + connect \Y $and$libresoc.v:143963$6550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:143624$6619 + cell $and $and$libresoc.v:143964$6551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233095,10 +232540,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:143624$6619_Y + connect \Y $and$libresoc.v:143964$6551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:143625$6620 + cell $and $and$libresoc.v:143965$6552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233106,10 +232551,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:143625$6620_Y + connect \Y $and$libresoc.v:143965$6552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:143627$6622 + cell $and $and$libresoc.v:143967$6554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233117,10 +232562,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$11 - connect \Y $and$libresoc.v:143627$6622_Y + connect \Y $and$libresoc.v:143967$6554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:143629$6624 + cell $and $and$libresoc.v:143969$6556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233128,10 +232573,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$15 - connect \Y $and$libresoc.v:143629$6624_Y + connect \Y $and$libresoc.v:143969$6556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:143630$6625 + cell $and $and$libresoc.v:143970$6557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233139,10 +232584,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:143630$6625_Y + connect \Y $and$libresoc.v:143970$6557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:143631$6626 + cell $and $and$libresoc.v:143971$6558 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233150,10 +232595,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:143631$6626_Y + connect \Y $and$libresoc.v:143971$6558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:143633$6628 + cell $and $and$libresoc.v:143973$6560 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233161,10 +232606,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__rel_o connect \B \$23 - connect \Y $and$libresoc.v:143633$6628_Y + connect \Y $and$libresoc.v:143973$6560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:143636$6631 + cell $and $and$libresoc.v:143976$6563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233172,10 +232617,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$21 - connect \Y $and$libresoc.v:143636$6631_Y + connect \Y $and$libresoc.v:143976$6563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:143641$6636 + cell $and $and$libresoc.v:143981$6568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233183,10 +232628,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$37 - connect \Y $and$libresoc.v:143641$6636_Y + connect \Y $and$libresoc.v:143981$6568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:143642$6637 + cell $and $and$libresoc.v:143982$6569 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233194,10 +232639,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:143642$6637_Y + connect \Y $and$libresoc.v:143982$6569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:143644$6639 + cell $and $and$libresoc.v:143984$6571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233205,10 +232650,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$43 - connect \Y $and$libresoc.v:143644$6639_Y + connect \Y $and$libresoc.v:143984$6571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:143647$6642 + cell $and $and$libresoc.v:143987$6574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233216,10 +232661,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \alu_logical0_n_ready_i - connect \Y $and$libresoc.v:143647$6642_Y + connect \Y $and$libresoc.v:143987$6574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:143648$6643 + cell $and $and$libresoc.v:143988$6575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233227,10 +232672,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_logical0_n_valid_o - connect \Y $and$libresoc.v:143648$6643_Y + connect \Y $and$libresoc.v:143988$6575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:143649$6644 + cell $and $and$libresoc.v:143989$6576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233238,10 +232683,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \cu_busy_o - connect \Y $and$libresoc.v:143649$6644_Y + connect \Y $and$libresoc.v:143989$6576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:143654$6649 + cell $and $and$libresoc.v:143994$6581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233249,10 +232694,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:143654$6649_Y + connect \Y $and$libresoc.v:143994$6581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:143655$6650 + cell $and $and$libresoc.v:143995$6582 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233260,10 +232705,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:143655$6650_Y + connect \Y $and$libresoc.v:143995$6582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:143658$6653 + cell $and $and$libresoc.v:143998$6585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233271,10 +232716,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:143658$6653_Y + connect \Y $and$libresoc.v:143998$6585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:143659$6654 + cell $and $and$libresoc.v:143999$6586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233282,10 +232727,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:143659$6654_Y + connect \Y $and$libresoc.v:143999$6586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:143668$6663 + cell $and $and$libresoc.v:144008$6595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233293,10 +232738,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:143668$6663_Y + connect \Y $and$libresoc.v:144008$6595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:143669$6664 + cell $and $and$libresoc.v:144009$6596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233304,10 +232749,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:143669$6664_Y + connect \Y $and$libresoc.v:144009$6596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:143670$6665 + cell $and $and$libresoc.v:144010$6597 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233315,10 +232760,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:143670$6665_Y + connect \Y $and$libresoc.v:144010$6597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:143643$6638 + cell $eq $eq$libresoc.v:143983$6570 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233326,10 +232771,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$41 connect \B 1'0 - connect \Y $eq$libresoc.v:143643$6638_Y + connect \Y $eq$libresoc.v:143983$6570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:143645$6640 + cell $eq $eq$libresoc.v:143985$6572 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233337,82 +232782,82 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:143645$6640_Y + connect \Y $eq$libresoc.v:143985$6572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:143618$6613 + cell $not $not$libresoc.v:143958$6545 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:143618$6613_Y + connect \Y $not$libresoc.v:143958$6545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:143626$6621 + cell $not $not$libresoc.v:143966$6553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:143626$6621_Y + connect \Y $not$libresoc.v:143966$6553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:143628$6623 + cell $not $not$libresoc.v:143968$6555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:143628$6623_Y + connect \Y $not$libresoc.v:143968$6555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:143632$6627 + cell $not $not$libresoc.v:143972$6559 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:143632$6627_Y + connect \Y $not$libresoc.v:143972$6559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:143635$6630 + cell $not $not$libresoc.v:143975$6562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 - connect \Y $not$libresoc.v:143635$6630_Y + connect \Y $not$libresoc.v:143975$6562_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:143640$6635 + cell $not $not$libresoc.v:143980$6567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_ready_i - connect \Y $not$libresoc.v:143640$6635_Y + connect \Y $not$libresoc.v:143980$6567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:143646$6641 + cell $not $not$libresoc.v:143986$6573 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:143646$6641_Y + connect \Y $not$libresoc.v:143986$6573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:143671$6666 + cell $not $not$libresoc.v:144011$6598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__zero_a - connect \Y $not$libresoc.v:143671$6666_Y + connect \Y $not$libresoc.v:144011$6598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:143672$6667 + cell $not $not$libresoc.v:144012$6599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:143672$6667_Y + connect \Y $not$libresoc.v:144012$6599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:143639$6634 + cell $or $or$libresoc.v:143979$6566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233420,10 +232865,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $or$libresoc.v:143639$6634_Y + connect \Y $or$libresoc.v:143979$6566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:143650$6645 + cell $or $or$libresoc.v:143990$6577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233431,10 +232876,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:143650$6645_Y + connect \Y $or$libresoc.v:143990$6577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:143651$6646 + cell $or $or$libresoc.v:143991$6578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233442,10 +232887,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:143651$6646_Y + connect \Y $or$libresoc.v:143991$6578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:143652$6647 + cell $or $or$libresoc.v:143992$6579 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233453,10 +232898,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:143652$6647_Y + connect \Y $or$libresoc.v:143992$6579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:143653$6648 + cell $or $or$libresoc.v:143993$6580 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233464,10 +232909,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:143653$6648_Y + connect \Y $or$libresoc.v:143993$6580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:143656$6651 + cell $or $or$libresoc.v:143996$6583 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233475,10 +232920,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:143656$6651_Y + connect \Y $or$libresoc.v:143996$6583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:143657$6652 + cell $or $or$libresoc.v:143997$6584 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233486,98 +232931,98 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$4 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:143657$6652_Y + connect \Y $or$libresoc.v:143997$6584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:143663$6658 + cell $reduce_and $reduce_and$libresoc.v:144003$6590 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$6 - connect \Y $reduce_and$libresoc.v:143663$6658_Y + connect \Y $reduce_and$libresoc.v:144003$6590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:143634$6629 + cell $reduce_or $reduce_or$libresoc.v:143974$6561 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \$25 - connect \Y $reduce_or$libresoc.v:143634$6629_Y + connect \Y $reduce_or$libresoc.v:143974$6561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:143637$6632 + cell $reduce_or $reduce_or$libresoc.v:143977$6564 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:143637$6632_Y + connect \Y $reduce_or$libresoc.v:143977$6564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:143638$6633 + cell $reduce_or $reduce_or$libresoc.v:143978$6565 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:143638$6633_Y + connect \Y $reduce_or$libresoc.v:143978$6565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:143660$6655 + cell $mux $ternary$libresoc.v:144000$6587 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:143660$6655_Y + connect \Y $ternary$libresoc.v:144000$6587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:143661$6656 + cell $mux $ternary$libresoc.v:144001$6588 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:143661$6656_Y + connect \Y $ternary$libresoc.v:144001$6588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:143662$6657 + cell $mux $ternary$libresoc.v:144002$6589 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:143662$6657_Y + connect \Y $ternary$libresoc.v:144002$6589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:143664$6659 + cell $mux $ternary$libresoc.v:144004$6591 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_logical0_logical_op__imm_data__data connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:143664$6659_Y + connect \Y $ternary$libresoc.v:144004$6591_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:143665$6660 + cell $mux $ternary$libresoc.v:144005$6592 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:143665$6660_Y + connect \Y $ternary$libresoc.v:144005$6592_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:143666$6661 + cell $mux $ternary$libresoc.v:144006$6593 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$80 connect \S \src_sel$77 - connect \Y $ternary$libresoc.v:143666$6661_Y + connect \Y $ternary$libresoc.v:144006$6593_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:143667$6662 + cell $mux $ternary$libresoc.v:144007$6594 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:143667$6662_Y + connect \Y $ternary$libresoc.v:144007$6594_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:143753.14-143759.4" + attribute \src "libresoc.v:144093.14-144099.4" cell \alu_l$61 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233586,7 +233031,7 @@ module \logical0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:143760.16-143792.4" + attribute \src "libresoc.v:144100.16-144132.4" cell \alu_logical0 \alu_logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233621,7 +233066,7 @@ module \logical0 connect \xer_so \alu_logical0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:143793.15-143799.4" + attribute \src "libresoc.v:144133.15-144139.4" cell \alui_l$60 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233630,7 +233075,7 @@ module \logical0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:143800.14-143806.4" + attribute \src "libresoc.v:144140.14-144146.4" cell \opc_l$56 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233639,7 +233084,7 @@ module \logical0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:143807.14-143813.4" + attribute \src "libresoc.v:144147.14-144153.4" cell \req_l$57 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233648,7 +233093,7 @@ module \logical0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:143814.14-143820.4" + attribute \src "libresoc.v:144154.14-144160.4" cell \rok_l$59 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233657,7 +233102,7 @@ module \logical0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:143821.14-143826.4" + attribute \src "libresoc.v:144161.14-144166.4" cell \rst_l$58 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233665,7 +233110,7 @@ module \logical0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:143827.14-143833.4" + attribute \src "libresoc.v:144167.14-144173.4" cell \src_l$55 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233673,622 +233118,622 @@ module \logical0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:143007.7-143007.20" - process $proc$libresoc.v:143007$6818 + attribute \src "libresoc.v:143347.7-143347.20" + process $proc$libresoc.v:143347$6750 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143125.7-143125.24" - process $proc$libresoc.v:143125$6819 + attribute \src "libresoc.v:143465.7-143465.24" + process $proc$libresoc.v:143465$6751 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:143135.7-143135.26" - process $proc$libresoc.v:143135$6820 + attribute \src "libresoc.v:143475.7-143475.26" + process $proc$libresoc.v:143475$6752 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:143143.7-143143.25" - process $proc$libresoc.v:143143$6821 + attribute \src "libresoc.v:143483.7-143483.25" + process $proc$libresoc.v:143483$6753 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:143151.13-143151.53" - process $proc$libresoc.v:143151$6822 + attribute \src "libresoc.v:143491.13-143491.53" + process $proc$libresoc.v:143491$6754 assign { } { } assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:143170.14-143170.57" - process $proc$libresoc.v:143170$6823 + attribute \src "libresoc.v:143510.14-143510.57" + process $proc$libresoc.v:143510$6755 assign { } { } assign $1\alu_logical0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:143174.14-143174.76" - process $proc$libresoc.v:143174$6824 + attribute \src "libresoc.v:143514.14-143514.76" + process $proc$libresoc.v:143514$6756 assign { } { } assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:143178.7-143178.51" - process $proc$libresoc.v:143178$6825 + attribute \src "libresoc.v:143518.7-143518.51" + process $proc$libresoc.v:143518$6757 assign { } { } assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:143186.13-143186.56" - process $proc$libresoc.v:143186$6826 + attribute \src "libresoc.v:143526.13-143526.56" + process $proc$libresoc.v:143526$6758 assign { } { } assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:143190.14-143190.51" - process $proc$libresoc.v:143190$6827 + attribute \src "libresoc.v:143530.14-143530.51" + process $proc$libresoc.v:143530$6759 assign { } { } assign $1\alu_logical0_logical_op__insn[31:0] 0 sync always sync init update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:143269.13-143269.55" - process $proc$libresoc.v:143269$6828 + attribute \src "libresoc.v:143609.13-143609.55" + process $proc$libresoc.v:143609$6760 assign { } { } assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:143273.7-143273.48" - process $proc$libresoc.v:143273$6829 + attribute \src "libresoc.v:143613.7-143613.48" + process $proc$libresoc.v:143613$6761 assign { } { } assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:143277.7-143277.49" - process $proc$libresoc.v:143277$6830 + attribute \src "libresoc.v:143617.7-143617.49" + process $proc$libresoc.v:143617$6762 assign { } { } assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:143281.7-143281.47" - process $proc$libresoc.v:143281$6831 + attribute \src "libresoc.v:143621.7-143621.47" + process $proc$libresoc.v:143621$6763 assign { } { } assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:143285.7-143285.48" - process $proc$libresoc.v:143285$6832 + attribute \src "libresoc.v:143625.7-143625.48" + process $proc$libresoc.v:143625$6764 assign { } { } assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:143289.7-143289.45" - process $proc$libresoc.v:143289$6833 + attribute \src "libresoc.v:143629.7-143629.45" + process $proc$libresoc.v:143629$6765 assign { } { } assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:143293.7-143293.45" - process $proc$libresoc.v:143293$6834 + attribute \src "libresoc.v:143633.7-143633.45" + process $proc$libresoc.v:143633$6766 assign { } { } assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:143297.7-143297.51" - process $proc$libresoc.v:143297$6835 + attribute \src "libresoc.v:143637.7-143637.51" + process $proc$libresoc.v:143637$6767 assign { } { } assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:143301.7-143301.45" - process $proc$libresoc.v:143301$6836 + attribute \src "libresoc.v:143641.7-143641.45" + process $proc$libresoc.v:143641$6768 assign { } { } assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:143305.7-143305.45" - process $proc$libresoc.v:143305$6837 + attribute \src "libresoc.v:143645.7-143645.45" + process $proc$libresoc.v:143645$6769 assign { } { } assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:143309.7-143309.48" - process $proc$libresoc.v:143309$6838 + attribute \src "libresoc.v:143649.7-143649.48" + process $proc$libresoc.v:143649$6770 assign { } { } assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:143313.7-143313.45" - process $proc$libresoc.v:143313$6839 + attribute \src "libresoc.v:143653.7-143653.45" + process $proc$libresoc.v:143653$6771 assign { } { } assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:143339.7-143339.27" - process $proc$libresoc.v:143339$6840 + attribute \src "libresoc.v:143679.7-143679.27" + process $proc$libresoc.v:143679$6772 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:143373.14-143373.47" - process $proc$libresoc.v:143373$6841 + attribute \src "libresoc.v:143713.14-143713.47" + process $proc$libresoc.v:143713$6773 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:143377.7-143377.27" - process $proc$libresoc.v:143377$6842 + attribute \src "libresoc.v:143717.7-143717.27" + process $proc$libresoc.v:143717$6774 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:143381.13-143381.33" - process $proc$libresoc.v:143381$6843 + attribute \src "libresoc.v:143721.13-143721.33" + process $proc$libresoc.v:143721$6775 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:143385.7-143385.30" - process $proc$libresoc.v:143385$6844 + attribute \src "libresoc.v:143725.7-143725.30" + process $proc$libresoc.v:143725$6776 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:143399.7-143399.25" - process $proc$libresoc.v:143399$6845 + attribute \src "libresoc.v:143739.7-143739.25" + process $proc$libresoc.v:143739$6777 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:143403.7-143403.25" - process $proc$libresoc.v:143403$6846 + attribute \src "libresoc.v:143743.7-143743.25" + process $proc$libresoc.v:143743$6778 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:143537.13-143537.30" - process $proc$libresoc.v:143537$6847 + attribute \src "libresoc.v:143877.13-143877.30" + process $proc$libresoc.v:143877$6779 assign { } { } assign $1\prev_wr_go[1:0] 2'00 sync always sync init update \prev_wr_go $1\prev_wr_go[1:0] end - attribute \src "libresoc.v:143545.13-143545.31" - process $proc$libresoc.v:143545$6848 + attribute \src "libresoc.v:143885.13-143885.31" + process $proc$libresoc.v:143885$6780 assign { } { } assign $1\req_l_r_req[1:0] 2'11 sync always sync init update \req_l_r_req $1\req_l_r_req[1:0] end - attribute \src "libresoc.v:143549.13-143549.31" - process $proc$libresoc.v:143549$6849 + attribute \src "libresoc.v:143889.13-143889.31" + process $proc$libresoc.v:143889$6781 assign { } { } assign $1\req_l_s_req[1:0] 2'00 sync always sync init update \req_l_s_req $1\req_l_s_req[1:0] end - attribute \src "libresoc.v:143561.7-143561.26" - process $proc$libresoc.v:143561$6850 + attribute \src "libresoc.v:143901.7-143901.26" + process $proc$libresoc.v:143901$6782 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:143565.7-143565.26" - process $proc$libresoc.v:143565$6851 + attribute \src "libresoc.v:143905.7-143905.26" + process $proc$libresoc.v:143905$6783 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:143569.7-143569.25" - process $proc$libresoc.v:143569$6852 + attribute \src "libresoc.v:143909.7-143909.25" + process $proc$libresoc.v:143909$6784 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:143573.7-143573.25" - process $proc$libresoc.v:143573$6853 + attribute \src "libresoc.v:143913.7-143913.25" + process $proc$libresoc.v:143913$6785 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:143587.13-143587.31" - process $proc$libresoc.v:143587$6854 + attribute \src "libresoc.v:143927.13-143927.31" + process $proc$libresoc.v:143927$6786 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:143591.13-143591.31" - process $proc$libresoc.v:143591$6855 + attribute \src "libresoc.v:143931.13-143931.31" + process $proc$libresoc.v:143931$6787 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:143599.14-143599.43" - process $proc$libresoc.v:143599$6856 + attribute \src "libresoc.v:143939.14-143939.43" + process $proc$libresoc.v:143939$6788 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:143603.14-143603.43" - process $proc$libresoc.v:143603$6857 + attribute \src "libresoc.v:143943.14-143943.43" + process $proc$libresoc.v:143943$6789 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:143607.7-143607.20" - process $proc$libresoc.v:143607$6858 + attribute \src "libresoc.v:143947.7-143947.20" + process $proc$libresoc.v:143947$6790 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:143673.3-143674.39" - process $proc$libresoc.v:143673$6668 + attribute \src "libresoc.v:144013.3-144014.39" + process $proc$libresoc.v:144013$6600 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:143675.3-143676.43" - process $proc$libresoc.v:143675$6669 + attribute \src "libresoc.v:144015.3-144016.43" + process $proc$libresoc.v:144015$6601 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:143677.3-143678.29" - process $proc$libresoc.v:143677$6670 + attribute \src "libresoc.v:144017.3-144018.29" + process $proc$libresoc.v:144017$6602 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:143679.3-143680.29" - process $proc$libresoc.v:143679$6671 + attribute \src "libresoc.v:144019.3-144020.29" + process $proc$libresoc.v:144019$6603 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:143681.3-143682.29" - process $proc$libresoc.v:143681$6672 + attribute \src "libresoc.v:144021.3-144022.29" + process $proc$libresoc.v:144021$6604 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:143683.3-143684.43" - process $proc$libresoc.v:143683$6673 + attribute \src "libresoc.v:144023.3-144024.43" + process $proc$libresoc.v:144023$6605 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:143685.3-143686.49" - process $proc$libresoc.v:143685$6674 + attribute \src "libresoc.v:144025.3-144026.49" + process $proc$libresoc.v:144025$6606 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:143687.3-143688.37" - process $proc$libresoc.v:143687$6675 + attribute \src "libresoc.v:144027.3-144028.37" + process $proc$libresoc.v:144027$6607 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:143689.3-143690.43" - process $proc$libresoc.v:143689$6676 + attribute \src "libresoc.v:144029.3-144030.43" + process $proc$libresoc.v:144029$6608 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:143691.3-143692.85" - process $proc$libresoc.v:143691$6677 + attribute \src "libresoc.v:144031.3-144032.85" + process $proc$libresoc.v:144031$6609 assign { } { } assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:143693.3-143694.81" - process $proc$libresoc.v:143693$6678 + attribute \src "libresoc.v:144033.3-144034.81" + process $proc$libresoc.v:144033$6610 assign { } { } assign $0\alu_logical0_logical_op__fn_unit[13:0] \alu_logical0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:143695.3-143696.95" - process $proc$libresoc.v:143695$6679 + attribute \src "libresoc.v:144035.3-144036.95" + process $proc$libresoc.v:144035$6611 assign { } { } assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:143697.3-143698.91" - process $proc$libresoc.v:143697$6680 + attribute \src "libresoc.v:144037.3-144038.91" + process $proc$libresoc.v:144037$6612 assign { } { } assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:143699.3-143700.79" - process $proc$libresoc.v:143699$6681 + attribute \src "libresoc.v:144039.3-144040.79" + process $proc$libresoc.v:144039$6613 assign { } { } assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:143701.3-143702.79" - process $proc$libresoc.v:143701$6682 + attribute \src "libresoc.v:144041.3-144042.79" + process $proc$libresoc.v:144041$6614 assign { } { } assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:143703.3-143704.79" - process $proc$libresoc.v:143703$6683 + attribute \src "libresoc.v:144043.3-144044.79" + process $proc$libresoc.v:144043$6615 assign { } { } assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:143705.3-143706.79" - process $proc$libresoc.v:143705$6684 + attribute \src "libresoc.v:144045.3-144046.79" + process $proc$libresoc.v:144045$6616 assign { } { } assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:143707.3-143708.85" - process $proc$libresoc.v:143707$6685 + attribute \src "libresoc.v:144047.3-144048.85" + process $proc$libresoc.v:144047$6617 assign { } { } assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:143709.3-143710.79" - process $proc$libresoc.v:143709$6686 + attribute \src "libresoc.v:144049.3-144050.79" + process $proc$libresoc.v:144049$6618 assign { } { } assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:143711.3-143712.89" - process $proc$libresoc.v:143711$6687 + attribute \src "libresoc.v:144051.3-144052.89" + process $proc$libresoc.v:144051$6619 assign { } { } assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:143713.3-143714.87" - process $proc$libresoc.v:143713$6688 + attribute \src "libresoc.v:144053.3-144054.87" + process $proc$libresoc.v:144053$6620 assign { } { } assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:143715.3-143716.85" - process $proc$libresoc.v:143715$6689 + attribute \src "libresoc.v:144055.3-144056.85" + process $proc$libresoc.v:144055$6621 assign { } { } assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:143717.3-143718.91" - process $proc$libresoc.v:143717$6690 + attribute \src "libresoc.v:144057.3-144058.91" + process $proc$libresoc.v:144057$6622 assign { } { } assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:143719.3-143720.83" - process $proc$libresoc.v:143719$6691 + attribute \src "libresoc.v:144059.3-144060.83" + process $proc$libresoc.v:144059$6623 assign { } { } assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:143721.3-143722.85" - process $proc$libresoc.v:143721$6692 + attribute \src "libresoc.v:144061.3-144062.85" + process $proc$libresoc.v:144061$6624 assign { } { } assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:143723.3-143724.83" - process $proc$libresoc.v:143723$6693 + attribute \src "libresoc.v:144063.3-144064.83" + process $proc$libresoc.v:144063$6625 assign { } { } assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next sync posedge \coresync_clk update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:143725.3-143726.75" - process $proc$libresoc.v:143725$6694 + attribute \src "libresoc.v:144065.3-144066.75" + process $proc$libresoc.v:144065$6626 assign { } { } assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:143727.3-143728.39" - process $proc$libresoc.v:143727$6695 + attribute \src "libresoc.v:144067.3-144068.39" + process $proc$libresoc.v:144067$6627 assign { } { } assign $0\req_l_r_req[1:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[1:0] end - attribute \src "libresoc.v:143729.3-143730.39" - process $proc$libresoc.v:143729$6696 + attribute \src "libresoc.v:144069.3-144070.39" + process $proc$libresoc.v:144069$6628 assign { } { } assign $0\req_l_s_req[1:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[1:0] end - attribute \src "libresoc.v:143731.3-143732.39" - process $proc$libresoc.v:143731$6697 + attribute \src "libresoc.v:144071.3-144072.39" + process $proc$libresoc.v:144071$6629 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:143733.3-143734.39" - process $proc$libresoc.v:143733$6698 + attribute \src "libresoc.v:144073.3-144074.39" + process $proc$libresoc.v:144073$6630 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:143735.3-143736.39" - process $proc$libresoc.v:143735$6699 + attribute \src "libresoc.v:144075.3-144076.39" + process $proc$libresoc.v:144075$6631 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:143737.3-143738.39" - process $proc$libresoc.v:143737$6700 + attribute \src "libresoc.v:144077.3-144078.39" + process $proc$libresoc.v:144077$6632 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:143739.3-143740.39" - process $proc$libresoc.v:143739$6701 + attribute \src "libresoc.v:144079.3-144080.39" + process $proc$libresoc.v:144079$6633 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:143741.3-143742.39" - process $proc$libresoc.v:143741$6702 + attribute \src "libresoc.v:144081.3-144082.39" + process $proc$libresoc.v:144081$6634 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:143743.3-143744.41" - process $proc$libresoc.v:143743$6703 + attribute \src "libresoc.v:144083.3-144084.41" + process $proc$libresoc.v:144083$6635 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:143745.3-143746.41" - process $proc$libresoc.v:143745$6704 + attribute \src "libresoc.v:144085.3-144086.41" + process $proc$libresoc.v:144085$6636 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:143747.3-143748.37" - process $proc$libresoc.v:143747$6705 + attribute \src "libresoc.v:144087.3-144088.37" + process $proc$libresoc.v:144087$6637 assign { } { } assign $0\prev_wr_go[1:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[1:0] end - attribute \src "libresoc.v:143749.3-143750.44" - process $proc$libresoc.v:143749$6706 + attribute \src "libresoc.v:144089.3-144090.44" + process $proc$libresoc.v:144089$6638 assign { } { } assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:143751.3-143752.24" - process $proc$libresoc.v:143751$6707 + attribute \src "libresoc.v:144091.3-144092.24" + process $proc$libresoc.v:144091$6639 assign { } { } assign $0\all_rd_dly[0:0] \$9 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:143834.3-143843.6" - process $proc$libresoc.v:143834$6708 + attribute \src "libresoc.v:144174.3-144183.6" + process $proc$libresoc.v:144174$6640 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:143835.5-143835.29" + attribute \src "libresoc.v:144175.5-144175.29" switch \initial - attribute \src "libresoc.v:143835.9-143835.17" + attribute \src "libresoc.v:144175.9-144175.17" case 1'1 case end @@ -234304,14 +233749,14 @@ module \logical0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:143844.3-143852.6" - process $proc$libresoc.v:143844$6709 + attribute \src "libresoc.v:144184.3-144192.6" + process $proc$libresoc.v:144184$6641 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$6710 $1\rok_l_s_rdok$next[0:0]$6711 - attribute \src "libresoc.v:143845.5-143845.29" + assign $0\rok_l_s_rdok$next[0:0]$6642 $1\rok_l_s_rdok$next[0:0]$6643 + attribute \src "libresoc.v:144185.5-144185.29" switch \initial - attribute \src "libresoc.v:143845.9-143845.17" + attribute \src "libresoc.v:144185.9-144185.17" case 1'1 case end @@ -234320,21 +233765,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$6711 1'0 + assign $1\rok_l_s_rdok$next[0:0]$6643 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$6711 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$6643 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6710 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6642 end - attribute \src "libresoc.v:143853.3-143861.6" - process $proc$libresoc.v:143853$6712 + attribute \src "libresoc.v:144193.3-144201.6" + process $proc$libresoc.v:144193$6644 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$6713 $1\rok_l_r_rdok$next[0:0]$6714 - attribute \src "libresoc.v:143854.5-143854.29" + assign $0\rok_l_r_rdok$next[0:0]$6645 $1\rok_l_r_rdok$next[0:0]$6646 + attribute \src "libresoc.v:144194.5-144194.29" switch \initial - attribute \src "libresoc.v:143854.9-143854.17" + attribute \src "libresoc.v:144194.9-144194.17" case 1'1 case end @@ -234343,21 +233788,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$6714 1'1 + assign $1\rok_l_r_rdok$next[0:0]$6646 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$6714 \$63 + assign $1\rok_l_r_rdok$next[0:0]$6646 \$63 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6713 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6645 end - attribute \src "libresoc.v:143862.3-143870.6" - process $proc$libresoc.v:143862$6715 + attribute \src "libresoc.v:144202.3-144210.6" + process $proc$libresoc.v:144202$6647 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$6716 $1\rst_l_s_rst$next[0:0]$6717 - attribute \src "libresoc.v:143863.5-143863.29" + assign $0\rst_l_s_rst$next[0:0]$6648 $1\rst_l_s_rst$next[0:0]$6649 + attribute \src "libresoc.v:144203.5-144203.29" switch \initial - attribute \src "libresoc.v:143863.9-143863.17" + attribute \src "libresoc.v:144203.9-144203.17" case 1'1 case end @@ -234366,21 +233811,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$6717 1'0 + assign $1\rst_l_s_rst$next[0:0]$6649 1'0 case - assign $1\rst_l_s_rst$next[0:0]$6717 \all_rd + assign $1\rst_l_s_rst$next[0:0]$6649 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6716 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6648 end - attribute \src "libresoc.v:143871.3-143879.6" - process $proc$libresoc.v:143871$6718 + attribute \src "libresoc.v:144211.3-144219.6" + process $proc$libresoc.v:144211$6650 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$6719 $1\rst_l_r_rst$next[0:0]$6720 - attribute \src "libresoc.v:143872.5-143872.29" + assign $0\rst_l_r_rst$next[0:0]$6651 $1\rst_l_r_rst$next[0:0]$6652 + attribute \src "libresoc.v:144212.5-144212.29" switch \initial - attribute \src "libresoc.v:143872.9-143872.17" + attribute \src "libresoc.v:144212.9-144212.17" case 1'1 case end @@ -234389,21 +233834,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$6720 1'1 + assign $1\rst_l_r_rst$next[0:0]$6652 1'1 case - assign $1\rst_l_r_rst$next[0:0]$6720 \rst_r + assign $1\rst_l_r_rst$next[0:0]$6652 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6719 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6651 end - attribute \src "libresoc.v:143880.3-143888.6" - process $proc$libresoc.v:143880$6721 + attribute \src "libresoc.v:144220.3-144228.6" + process $proc$libresoc.v:144220$6653 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6722 $1\opc_l_s_opc$next[0:0]$6723 - attribute \src "libresoc.v:143881.5-143881.29" + assign $0\opc_l_s_opc$next[0:0]$6654 $1\opc_l_s_opc$next[0:0]$6655 + attribute \src "libresoc.v:144221.5-144221.29" switch \initial - attribute \src "libresoc.v:143881.9-143881.17" + attribute \src "libresoc.v:144221.9-144221.17" case 1'1 case end @@ -234412,21 +233857,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6723 1'0 + assign $1\opc_l_s_opc$next[0:0]$6655 1'0 case - assign $1\opc_l_s_opc$next[0:0]$6723 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$6655 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6722 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6654 end - attribute \src "libresoc.v:143889.3-143897.6" - process $proc$libresoc.v:143889$6724 + attribute \src "libresoc.v:144229.3-144237.6" + process $proc$libresoc.v:144229$6656 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6725 $1\opc_l_r_opc$next[0:0]$6726 - attribute \src "libresoc.v:143890.5-143890.29" + assign $0\opc_l_r_opc$next[0:0]$6657 $1\opc_l_r_opc$next[0:0]$6658 + attribute \src "libresoc.v:144230.5-144230.29" switch \initial - attribute \src "libresoc.v:143890.9-143890.17" + attribute \src "libresoc.v:144230.9-144230.17" case 1'1 case end @@ -234435,21 +233880,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6726 1'1 + assign $1\opc_l_r_opc$next[0:0]$6658 1'1 case - assign $1\opc_l_r_opc$next[0:0]$6726 \req_done + assign $1\opc_l_r_opc$next[0:0]$6658 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6725 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6657 end - attribute \src "libresoc.v:143898.3-143906.6" - process $proc$libresoc.v:143898$6727 + attribute \src "libresoc.v:144238.3-144246.6" + process $proc$libresoc.v:144238$6659 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$6728 $1\src_l_s_src$next[2:0]$6729 - attribute \src "libresoc.v:143899.5-143899.29" + assign $0\src_l_s_src$next[2:0]$6660 $1\src_l_s_src$next[2:0]$6661 + attribute \src "libresoc.v:144239.5-144239.29" switch \initial - attribute \src "libresoc.v:143899.9-143899.17" + attribute \src "libresoc.v:144239.9-144239.17" case 1'1 case end @@ -234458,21 +233903,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$6729 3'000 + assign $1\src_l_s_src$next[2:0]$6661 3'000 case - assign $1\src_l_s_src$next[2:0]$6729 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$6661 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6728 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6660 end - attribute \src "libresoc.v:143907.3-143915.6" - process $proc$libresoc.v:143907$6730 + attribute \src "libresoc.v:144247.3-144255.6" + process $proc$libresoc.v:144247$6662 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$6731 $1\src_l_r_src$next[2:0]$6732 - attribute \src "libresoc.v:143908.5-143908.29" + assign $0\src_l_r_src$next[2:0]$6663 $1\src_l_r_src$next[2:0]$6664 + attribute \src "libresoc.v:144248.5-144248.29" switch \initial - attribute \src "libresoc.v:143908.9-143908.17" + attribute \src "libresoc.v:144248.9-144248.17" case 1'1 case end @@ -234481,21 +233926,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$6732 3'111 + assign $1\src_l_r_src$next[2:0]$6664 3'111 case - assign $1\src_l_r_src$next[2:0]$6732 \reset_r + assign $1\src_l_r_src$next[2:0]$6664 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6731 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6663 end - attribute \src "libresoc.v:143916.3-143924.6" - process $proc$libresoc.v:143916$6733 + attribute \src "libresoc.v:144256.3-144264.6" + process $proc$libresoc.v:144256$6665 assign { } { } assign { } { } - assign $0\req_l_s_req$next[1:0]$6734 $1\req_l_s_req$next[1:0]$6735 - attribute \src "libresoc.v:143917.5-143917.29" + assign $0\req_l_s_req$next[1:0]$6666 $1\req_l_s_req$next[1:0]$6667 + attribute \src "libresoc.v:144257.5-144257.29" switch \initial - attribute \src "libresoc.v:143917.9-143917.17" + attribute \src "libresoc.v:144257.9-144257.17" case 1'1 case end @@ -234504,21 +233949,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[1:0]$6735 2'00 + assign $1\req_l_s_req$next[1:0]$6667 2'00 case - assign $1\req_l_s_req$next[1:0]$6735 \$65 + assign $1\req_l_s_req$next[1:0]$6667 \$65 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6734 + update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6666 end - attribute \src "libresoc.v:143925.3-143933.6" - process $proc$libresoc.v:143925$6736 + attribute \src "libresoc.v:144265.3-144273.6" + process $proc$libresoc.v:144265$6668 assign { } { } assign { } { } - assign $0\req_l_r_req$next[1:0]$6737 $1\req_l_r_req$next[1:0]$6738 - attribute \src "libresoc.v:143926.5-143926.29" + assign $0\req_l_r_req$next[1:0]$6669 $1\req_l_r_req$next[1:0]$6670 + attribute \src "libresoc.v:144266.5-144266.29" switch \initial - attribute \src "libresoc.v:143926.9-143926.17" + attribute \src "libresoc.v:144266.9-144266.17" case 1'1 case end @@ -234527,15 +233972,15 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[1:0]$6738 2'11 + assign $1\req_l_r_req$next[1:0]$6670 2'11 case - assign $1\req_l_r_req$next[1:0]$6738 \$67 + assign $1\req_l_r_req$next[1:0]$6670 \$67 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6737 + update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6669 end - attribute \src "libresoc.v:143934.3-143972.6" - process $proc$libresoc.v:143934$6739 + attribute \src "libresoc.v:144274.3-144312.6" + process $proc$libresoc.v:144274$6671 assign { } { } assign { } { } assign { } { } @@ -234572,33 +234017,33 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__data_len$next[3:0]$6740 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 - assign $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 + assign $0\alu_logical0_logical_op__data_len$next[3:0]$6672 $1\alu_logical0_logical_op__data_len$next[3:0]$6690 + assign $0\alu_logical0_logical_op__fn_unit$next[13:0]$6673 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6691 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 - assign $0\alu_logical0_logical_op__insn$next[31:0]$6745 $1\alu_logical0_logical_op__insn$next[31:0]$6763 - assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 - assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 - assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 - assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 - assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 + assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6676 $1\alu_logical0_logical_op__input_carry$next[1:0]$6694 + assign $0\alu_logical0_logical_op__insn$next[31:0]$6677 $1\alu_logical0_logical_op__insn$next[31:0]$6695 + assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6678 $1\alu_logical0_logical_op__insn_type$next[6:0]$6696 + assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6679 $1\alu_logical0_logical_op__invert_in$next[0:0]$6697 + assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6680 $1\alu_logical0_logical_op__invert_out$next[0:0]$6698 + assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6681 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6699 + assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6682 $1\alu_logical0_logical_op__is_signed$next[0:0]$6700 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 + assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6685 $1\alu_logical0_logical_op__output_carry$next[0:0]$6703 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 - assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 - assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 - assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 - assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 - assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 - assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 - assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 - attribute \src "libresoc.v:143935.5-143935.29" + assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6688 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6706 + assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6689 $1\alu_logical0_logical_op__zero_a$next[0:0]$6707 + assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6674 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6708 + assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6675 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6709 + assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6683 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6710 + assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6684 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6711 + assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6686 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6712 + assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6687 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6713 + attribute \src "libresoc.v:144275.5-144275.29" switch \initial - attribute \src "libresoc.v:143935.9-143935.17" + attribute \src "libresoc.v:144275.9-144275.17" case 1'1 case end @@ -234624,26 +234069,26 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_logical0_logical_op__insn$next[31:0]$6763 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } + assign { $1\alu_logical0_logical_op__insn$next[31:0]$6695 $1\alu_logical0_logical_op__data_len$next[3:0]$6690 $1\alu_logical0_logical_op__is_signed$next[0:0]$6700 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6699 $1\alu_logical0_logical_op__output_carry$next[0:0]$6703 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6706 $1\alu_logical0_logical_op__invert_out$next[0:0]$6698 $1\alu_logical0_logical_op__input_carry$next[1:0]$6694 $1\alu_logical0_logical_op__zero_a$next[0:0]$6707 $1\alu_logical0_logical_op__invert_in$next[0:0]$6697 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6702 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6701 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6704 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6705 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6693 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6692 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6691 $1\alu_logical0_logical_op__insn_type$next[6:0]$6696 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } case - assign $1\alu_logical0_logical_op__data_len$next[3:0]$6758 \alu_logical0_logical_op__data_len - assign $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 \alu_logical0_logical_op__fn_unit - assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 \alu_logical0_logical_op__imm_data__data - assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 \alu_logical0_logical_op__imm_data__ok - assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 \alu_logical0_logical_op__input_carry - assign $1\alu_logical0_logical_op__insn$next[31:0]$6763 \alu_logical0_logical_op__insn - assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 \alu_logical0_logical_op__insn_type - assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 \alu_logical0_logical_op__invert_in - assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 \alu_logical0_logical_op__invert_out - assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 \alu_logical0_logical_op__is_32bit - assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 \alu_logical0_logical_op__is_signed - assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 \alu_logical0_logical_op__oe__oe - assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 \alu_logical0_logical_op__oe__ok - assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 \alu_logical0_logical_op__output_carry - assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 \alu_logical0_logical_op__rc__ok - assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 \alu_logical0_logical_op__rc__rc - assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 \alu_logical0_logical_op__write_cr0 - assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 \alu_logical0_logical_op__zero_a + assign $1\alu_logical0_logical_op__data_len$next[3:0]$6690 \alu_logical0_logical_op__data_len + assign $1\alu_logical0_logical_op__fn_unit$next[13:0]$6691 \alu_logical0_logical_op__fn_unit + assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6692 \alu_logical0_logical_op__imm_data__data + assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6693 \alu_logical0_logical_op__imm_data__ok + assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6694 \alu_logical0_logical_op__input_carry + assign $1\alu_logical0_logical_op__insn$next[31:0]$6695 \alu_logical0_logical_op__insn + assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6696 \alu_logical0_logical_op__insn_type + assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6697 \alu_logical0_logical_op__invert_in + assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6698 \alu_logical0_logical_op__invert_out + assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6699 \alu_logical0_logical_op__is_32bit + assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6700 \alu_logical0_logical_op__is_signed + assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6701 \alu_logical0_logical_op__oe__oe + assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6702 \alu_logical0_logical_op__oe__ok + assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6703 \alu_logical0_logical_op__output_carry + assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6704 \alu_logical0_logical_op__rc__ok + assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6705 \alu_logical0_logical_op__rc__rc + assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6706 \alu_logical0_logical_op__write_cr0 + assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6707 \alu_logical0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -234655,54 +234100,54 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 1'0 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 1'0 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 1'0 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 1'0 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 1'0 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6708 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6709 1'0 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6713 1'0 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6712 1'0 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6710 1'0 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6711 1'0 case - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6708 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6692 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6709 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6693 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6710 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6701 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6711 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6702 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6712 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6704 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6713 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6705 end sync always - update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6740 - update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 - update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 - update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 - update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 - update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6745 - update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 - update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 - update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 - update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 - update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 - update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 - update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 - update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 - update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 - update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 - update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 - update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 + update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6672 + update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[13:0]$6673 + update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6674 + update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6675 + update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6676 + update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6677 + update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6678 + update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6679 + update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6680 + update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6681 + update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6682 + update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6683 + update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6684 + update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6685 + update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6686 + update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6687 + update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6688 + update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6689 end - attribute \src "libresoc.v:143973.3-143994.6" - process $proc$libresoc.v:143973$6782 + attribute \src "libresoc.v:144313.3-144334.6" + process $proc$libresoc.v:144313$6714 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$6783 $2\data_r0__o$next[63:0]$6787 + assign $0\data_r0__o$next[63:0]$6715 $2\data_r0__o$next[63:0]$6719 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$6784 $3\data_r0__o_ok$next[0:0]$6789 - attribute \src "libresoc.v:143974.5-143974.29" + assign $0\data_r0__o_ok$next[0:0]$6716 $3\data_r0__o_ok$next[0:0]$6721 + attribute \src "libresoc.v:144314.5-144314.29" switch \initial - attribute \src "libresoc.v:143974.9-143974.17" + attribute \src "libresoc.v:144314.9-144314.17" case 1'1 case end @@ -234712,10 +234157,10 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$6786 $1\data_r0__o$next[63:0]$6785 } { \o_ok \alu_logical0_o } + assign { $1\data_r0__o_ok$next[0:0]$6718 $1\data_r0__o$next[63:0]$6717 } { \o_ok \alu_logical0_o } case - assign $1\data_r0__o$next[63:0]$6785 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$6786 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$6717 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$6718 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -234723,38 +234168,38 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$6788 $2\data_r0__o$next[63:0]$6787 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$6720 $2\data_r0__o$next[63:0]$6719 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$6787 $1\data_r0__o$next[63:0]$6785 - assign $2\data_r0__o_ok$next[0:0]$6788 $1\data_r0__o_ok$next[0:0]$6786 + assign $2\data_r0__o$next[63:0]$6719 $1\data_r0__o$next[63:0]$6717 + assign $2\data_r0__o_ok$next[0:0]$6720 $1\data_r0__o_ok$next[0:0]$6718 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$6789 1'0 + assign $3\data_r0__o_ok$next[0:0]$6721 1'0 case - assign $3\data_r0__o_ok$next[0:0]$6789 $2\data_r0__o_ok$next[0:0]$6788 + assign $3\data_r0__o_ok$next[0:0]$6721 $2\data_r0__o_ok$next[0:0]$6720 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$6783 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6784 + update \data_r0__o$next $0\data_r0__o$next[63:0]$6715 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6716 end - attribute \src "libresoc.v:143995.3-144016.6" - process $proc$libresoc.v:143995$6790 + attribute \src "libresoc.v:144335.3-144356.6" + process $proc$libresoc.v:144335$6722 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$6791 $2\data_r1__cr_a$next[3:0]$6795 + assign $0\data_r1__cr_a$next[3:0]$6723 $2\data_r1__cr_a$next[3:0]$6727 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$6792 $3\data_r1__cr_a_ok$next[0:0]$6797 - attribute \src "libresoc.v:143996.5-143996.29" + assign $0\data_r1__cr_a_ok$next[0:0]$6724 $3\data_r1__cr_a_ok$next[0:0]$6729 + attribute \src "libresoc.v:144336.5-144336.29" switch \initial - attribute \src "libresoc.v:143996.9-143996.17" + attribute \src "libresoc.v:144336.9-144336.17" case 1'1 case end @@ -234764,10 +234209,10 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$6794 $1\data_r1__cr_a$next[3:0]$6793 } { \cr_a_ok \alu_logical0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$6726 $1\data_r1__cr_a$next[3:0]$6725 } { \cr_a_ok \alu_logical0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$6793 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$6794 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$6725 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$6726 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -234775,32 +234220,32 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$6796 $2\data_r1__cr_a$next[3:0]$6795 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$6728 $2\data_r1__cr_a$next[3:0]$6727 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$6795 $1\data_r1__cr_a$next[3:0]$6793 - assign $2\data_r1__cr_a_ok$next[0:0]$6796 $1\data_r1__cr_a_ok$next[0:0]$6794 + assign $2\data_r1__cr_a$next[3:0]$6727 $1\data_r1__cr_a$next[3:0]$6725 + assign $2\data_r1__cr_a_ok$next[0:0]$6728 $1\data_r1__cr_a_ok$next[0:0]$6726 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$6797 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$6729 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$6797 $2\data_r1__cr_a_ok$next[0:0]$6796 + assign $3\data_r1__cr_a_ok$next[0:0]$6729 $2\data_r1__cr_a_ok$next[0:0]$6728 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6791 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6792 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6723 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6724 end - attribute \src "libresoc.v:144017.3-144026.6" - process $proc$libresoc.v:144017$6798 + attribute \src "libresoc.v:144357.3-144366.6" + process $proc$libresoc.v:144357$6730 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$6799 $1\src_r0$next[63:0]$6800 - attribute \src "libresoc.v:144018.5-144018.29" + assign $0\src_r0$next[63:0]$6731 $1\src_r0$next[63:0]$6732 + attribute \src "libresoc.v:144358.5-144358.29" switch \initial - attribute \src "libresoc.v:144018.9-144018.17" + attribute \src "libresoc.v:144358.9-144358.17" case 1'1 case end @@ -234809,21 +234254,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$6800 \src_or_imm + assign $1\src_r0$next[63:0]$6732 \src_or_imm case - assign $1\src_r0$next[63:0]$6800 \src_r0 + assign $1\src_r0$next[63:0]$6732 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$6799 + update \src_r0$next $0\src_r0$next[63:0]$6731 end - attribute \src "libresoc.v:144027.3-144036.6" - process $proc$libresoc.v:144027$6801 + attribute \src "libresoc.v:144367.3-144376.6" + process $proc$libresoc.v:144367$6733 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$6802 $1\src_r1$next[63:0]$6803 - attribute \src "libresoc.v:144028.5-144028.29" + assign $0\src_r1$next[63:0]$6734 $1\src_r1$next[63:0]$6735 + attribute \src "libresoc.v:144368.5-144368.29" switch \initial - attribute \src "libresoc.v:144028.9-144028.17" + attribute \src "libresoc.v:144368.9-144368.17" case 1'1 case end @@ -234832,21 +234277,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$6803 \src_or_imm$80 + assign $1\src_r1$next[63:0]$6735 \src_or_imm$80 case - assign $1\src_r1$next[63:0]$6803 \src_r1 + assign $1\src_r1$next[63:0]$6735 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$6802 + update \src_r1$next $0\src_r1$next[63:0]$6734 end - attribute \src "libresoc.v:144037.3-144046.6" - process $proc$libresoc.v:144037$6804 + attribute \src "libresoc.v:144377.3-144386.6" + process $proc$libresoc.v:144377$6736 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$6805 $1\src_r2$next[0:0]$6806 - attribute \src "libresoc.v:144038.5-144038.29" + assign $0\src_r2$next[0:0]$6737 $1\src_r2$next[0:0]$6738 + attribute \src "libresoc.v:144378.5-144378.29" switch \initial - attribute \src "libresoc.v:144038.9-144038.17" + attribute \src "libresoc.v:144378.9-144378.17" case 1'1 case end @@ -234855,21 +234300,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$6806 \src3_i + assign $1\src_r2$next[0:0]$6738 \src3_i case - assign $1\src_r2$next[0:0]$6806 \src_r2 + assign $1\src_r2$next[0:0]$6738 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$6805 + update \src_r2$next $0\src_r2$next[0:0]$6737 end - attribute \src "libresoc.v:144047.3-144055.6" - process $proc$libresoc.v:144047$6807 + attribute \src "libresoc.v:144387.3-144395.6" + process $proc$libresoc.v:144387$6739 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$6808 $1\alui_l_r_alui$next[0:0]$6809 - attribute \src "libresoc.v:144048.5-144048.29" + assign $0\alui_l_r_alui$next[0:0]$6740 $1\alui_l_r_alui$next[0:0]$6741 + attribute \src "libresoc.v:144388.5-144388.29" switch \initial - attribute \src "libresoc.v:144048.9-144048.17" + attribute \src "libresoc.v:144388.9-144388.17" case 1'1 case end @@ -234878,21 +234323,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$6809 1'1 + assign $1\alui_l_r_alui$next[0:0]$6741 1'1 case - assign $1\alui_l_r_alui$next[0:0]$6809 \$89 + assign $1\alui_l_r_alui$next[0:0]$6741 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6808 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6740 end - attribute \src "libresoc.v:144056.3-144064.6" - process $proc$libresoc.v:144056$6810 + attribute \src "libresoc.v:144396.3-144404.6" + process $proc$libresoc.v:144396$6742 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$6811 $1\alu_l_r_alu$next[0:0]$6812 - attribute \src "libresoc.v:144057.5-144057.29" + assign $0\alu_l_r_alu$next[0:0]$6743 $1\alu_l_r_alu$next[0:0]$6744 + attribute \src "libresoc.v:144397.5-144397.29" switch \initial - attribute \src "libresoc.v:144057.9-144057.17" + attribute \src "libresoc.v:144397.9-144397.17" case 1'1 case end @@ -234901,21 +234346,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$6812 1'1 + assign $1\alu_l_r_alu$next[0:0]$6744 1'1 case - assign $1\alu_l_r_alu$next[0:0]$6812 \$91 + assign $1\alu_l_r_alu$next[0:0]$6744 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6811 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6743 end - attribute \src "libresoc.v:144065.3-144074.6" - process $proc$libresoc.v:144065$6813 + attribute \src "libresoc.v:144405.3-144414.6" + process $proc$libresoc.v:144405$6745 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:144066.5-144066.29" + attribute \src "libresoc.v:144406.5-144406.29" switch \initial - attribute \src "libresoc.v:144066.9-144066.17" + attribute \src "libresoc.v:144406.9-144406.17" case 1'1 case end @@ -234931,14 +234376,14 @@ module \logical0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:144075.3-144084.6" - process $proc$libresoc.v:144075$6814 + attribute \src "libresoc.v:144415.3-144424.6" + process $proc$libresoc.v:144415$6746 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:144076.5-144076.29" + attribute \src "libresoc.v:144416.5-144416.29" switch \initial - attribute \src "libresoc.v:144076.9-144076.17" + attribute \src "libresoc.v:144416.9-144416.17" case 1'1 case end @@ -234954,14 +234399,14 @@ module \logical0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:144085.3-144093.6" - process $proc$libresoc.v:144085$6815 + attribute \src "libresoc.v:144425.3-144433.6" + process $proc$libresoc.v:144425$6747 assign { } { } assign { } { } - assign $0\prev_wr_go$next[1:0]$6816 $1\prev_wr_go$next[1:0]$6817 - attribute \src "libresoc.v:144086.5-144086.29" + assign $0\prev_wr_go$next[1:0]$6748 $1\prev_wr_go$next[1:0]$6749 + attribute \src "libresoc.v:144426.5-144426.29" switch \initial - attribute \src "libresoc.v:144086.9-144086.17" + attribute \src "libresoc.v:144426.9-144426.17" case 1'1 case end @@ -234970,70 +234415,70 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[1:0]$6817 2'00 - case - assign $1\prev_wr_go$next[1:0]$6817 \$19 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6816 - end - connect \$9 $and$libresoc.v:143616$6611_Y - connect \$99 $and$libresoc.v:143617$6612_Y - connect \$101 $not$libresoc.v:143618$6613_Y - connect \$103 $and$libresoc.v:143619$6614_Y - connect \$105 $and$libresoc.v:143620$6615_Y - connect \$107 $and$libresoc.v:143621$6616_Y - connect \$109 $and$libresoc.v:143622$6617_Y - connect \$111 $and$libresoc.v:143623$6618_Y - connect \$113 $and$libresoc.v:143624$6619_Y - connect \$115 $and$libresoc.v:143625$6620_Y - connect \$11 $not$libresoc.v:143626$6621_Y - connect \$13 $and$libresoc.v:143627$6622_Y - connect \$15 $not$libresoc.v:143628$6623_Y - connect \$17 $and$libresoc.v:143629$6624_Y - connect \$1 $and$libresoc.v:143630$6625_Y - connect \$19 $and$libresoc.v:143631$6626_Y - connect \$23 $not$libresoc.v:143632$6627_Y - connect \$25 $and$libresoc.v:143633$6628_Y - connect \$22 $reduce_or$libresoc.v:143634$6629_Y - connect \$21 $not$libresoc.v:143635$6630_Y - connect \$29 $and$libresoc.v:143636$6631_Y - connect \$31 $reduce_or$libresoc.v:143637$6632_Y - connect \$33 $reduce_or$libresoc.v:143638$6633_Y - connect \$35 $or$libresoc.v:143639$6634_Y - connect \$37 $not$libresoc.v:143640$6635_Y - connect \$39 $and$libresoc.v:143641$6636_Y - connect \$41 $and$libresoc.v:143642$6637_Y - connect \$43 $eq$libresoc.v:143643$6638_Y - connect \$45 $and$libresoc.v:143644$6639_Y - connect \$47 $eq$libresoc.v:143645$6640_Y - connect \$4 $not$libresoc.v:143646$6641_Y - connect \$49 $and$libresoc.v:143647$6642_Y - connect \$51 $and$libresoc.v:143648$6643_Y - connect \$53 $and$libresoc.v:143649$6644_Y - connect \$55 $or$libresoc.v:143650$6645_Y - connect \$57 $or$libresoc.v:143651$6646_Y - connect \$59 $or$libresoc.v:143652$6647_Y - connect \$61 $or$libresoc.v:143653$6648_Y - connect \$63 $and$libresoc.v:143654$6649_Y - connect \$65 $and$libresoc.v:143655$6650_Y - connect \$67 $or$libresoc.v:143656$6651_Y - connect \$6 $or$libresoc.v:143657$6652_Y - connect \$69 $and$libresoc.v:143658$6653_Y - connect \$71 $and$libresoc.v:143659$6654_Y - connect \$73 $ternary$libresoc.v:143660$6655_Y - connect \$75 $ternary$libresoc.v:143661$6656_Y - connect \$78 $ternary$libresoc.v:143662$6657_Y - connect \$3 $reduce_and$libresoc.v:143663$6658_Y - connect \$81 $ternary$libresoc.v:143664$6659_Y - connect \$83 $ternary$libresoc.v:143665$6660_Y - connect \$85 $ternary$libresoc.v:143666$6661_Y - connect \$87 $ternary$libresoc.v:143667$6662_Y - connect \$89 $and$libresoc.v:143668$6663_Y - connect \$91 $and$libresoc.v:143669$6664_Y - connect \$93 $and$libresoc.v:143670$6665_Y - connect \$95 $not$libresoc.v:143671$6666_Y - connect \$97 $not$libresoc.v:143672$6667_Y + assign $1\prev_wr_go$next[1:0]$6749 2'00 + case + assign $1\prev_wr_go$next[1:0]$6749 \$19 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6748 + end + connect \$9 $and$libresoc.v:143956$6543_Y + connect \$99 $and$libresoc.v:143957$6544_Y + connect \$101 $not$libresoc.v:143958$6545_Y + connect \$103 $and$libresoc.v:143959$6546_Y + connect \$105 $and$libresoc.v:143960$6547_Y + connect \$107 $and$libresoc.v:143961$6548_Y + connect \$109 $and$libresoc.v:143962$6549_Y + connect \$111 $and$libresoc.v:143963$6550_Y + connect \$113 $and$libresoc.v:143964$6551_Y + connect \$115 $and$libresoc.v:143965$6552_Y + connect \$11 $not$libresoc.v:143966$6553_Y + connect \$13 $and$libresoc.v:143967$6554_Y + connect \$15 $not$libresoc.v:143968$6555_Y + connect \$17 $and$libresoc.v:143969$6556_Y + connect \$1 $and$libresoc.v:143970$6557_Y + connect \$19 $and$libresoc.v:143971$6558_Y + connect \$23 $not$libresoc.v:143972$6559_Y + connect \$25 $and$libresoc.v:143973$6560_Y + connect \$22 $reduce_or$libresoc.v:143974$6561_Y + connect \$21 $not$libresoc.v:143975$6562_Y + connect \$29 $and$libresoc.v:143976$6563_Y + connect \$31 $reduce_or$libresoc.v:143977$6564_Y + connect \$33 $reduce_or$libresoc.v:143978$6565_Y + connect \$35 $or$libresoc.v:143979$6566_Y + connect \$37 $not$libresoc.v:143980$6567_Y + connect \$39 $and$libresoc.v:143981$6568_Y + connect \$41 $and$libresoc.v:143982$6569_Y + connect \$43 $eq$libresoc.v:143983$6570_Y + connect \$45 $and$libresoc.v:143984$6571_Y + connect \$47 $eq$libresoc.v:143985$6572_Y + connect \$4 $not$libresoc.v:143986$6573_Y + connect \$49 $and$libresoc.v:143987$6574_Y + connect \$51 $and$libresoc.v:143988$6575_Y + connect \$53 $and$libresoc.v:143989$6576_Y + connect \$55 $or$libresoc.v:143990$6577_Y + connect \$57 $or$libresoc.v:143991$6578_Y + connect \$59 $or$libresoc.v:143992$6579_Y + connect \$61 $or$libresoc.v:143993$6580_Y + connect \$63 $and$libresoc.v:143994$6581_Y + connect \$65 $and$libresoc.v:143995$6582_Y + connect \$67 $or$libresoc.v:143996$6583_Y + connect \$6 $or$libresoc.v:143997$6584_Y + connect \$69 $and$libresoc.v:143998$6585_Y + connect \$71 $and$libresoc.v:143999$6586_Y + connect \$73 $ternary$libresoc.v:144000$6587_Y + connect \$75 $ternary$libresoc.v:144001$6588_Y + connect \$78 $ternary$libresoc.v:144002$6589_Y + connect \$3 $reduce_and$libresoc.v:144003$6590_Y + connect \$81 $ternary$libresoc.v:144004$6591_Y + connect \$83 $ternary$libresoc.v:144005$6592_Y + connect \$85 $ternary$libresoc.v:144006$6593_Y + connect \$87 $ternary$libresoc.v:144007$6594_Y + connect \$89 $and$libresoc.v:144008$6595_Y + connect \$91 $and$libresoc.v:144009$6596_Y + connect \$93 $and$libresoc.v:144010$6597_Y + connect \$95 $not$libresoc.v:144011$6598_Y + connect \$97 $not$libresoc.v:144012$6599_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$111 @@ -235067,266 +234512,266 @@ module \logical0 connect \all_rd_dly$next \all_rd connect \all_rd \$9 end -attribute \src "libresoc.v:144130.1-145521.10" +attribute \src "libresoc.v:144470.1-145861.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" attribute \generator "nMigen" module \logical_pipe1 - attribute \src "libresoc.v:145460.3-145478.6" - wire width 4 $0\cr_a$next[3:0]$6943 - attribute \src "libresoc.v:145220.3-145221.25" + attribute \src "libresoc.v:145800.3-145818.6" + wire width 4 $0\cr_a$next[3:0]$6875 + attribute \src "libresoc.v:145560.3-145561.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:145460.3-145478.6" - wire $0\cr_a_ok$next[0:0]$6944 - attribute \src "libresoc.v:145222.3-145223.31" + attribute \src "libresoc.v:145800.3-145818.6" + wire $0\cr_a_ok$next[0:0]$6876 + attribute \src "libresoc.v:145562.3-145563.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:144131.7-144131.20" + attribute \src "libresoc.v:144471.7-144471.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire width 4 $0\logical_op__data_len$next[3:0]$6894 - attribute \src "libresoc.v:145260.3-145261.57" + attribute \src "libresoc.v:145739.3-145780.6" + wire width 4 $0\logical_op__data_len$next[3:0]$6826 + attribute \src "libresoc.v:145600.3-145601.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire width 14 $0\logical_op__fn_unit$next[13:0]$6895 - attribute \src "libresoc.v:145230.3-145231.55" + attribute \src "libresoc.v:145739.3-145780.6" + wire width 14 $0\logical_op__fn_unit$next[13:0]$6827 + attribute \src "libresoc.v:145570.3-145571.55" wire width 14 $0\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$6896 - attribute \src "libresoc.v:145232.3-145233.69" + attribute \src "libresoc.v:145739.3-145780.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$6828 + attribute \src "libresoc.v:145572.3-145573.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $0\logical_op__imm_data__ok$next[0:0]$6897 - attribute \src "libresoc.v:145234.3-145235.65" + attribute \src "libresoc.v:145739.3-145780.6" + wire $0\logical_op__imm_data__ok$next[0:0]$6829 + attribute \src "libresoc.v:145574.3-145575.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$6898 - attribute \src "libresoc.v:145248.3-145249.63" + attribute \src "libresoc.v:145739.3-145780.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$6830 + attribute \src "libresoc.v:145588.3-145589.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire width 32 $0\logical_op__insn$next[31:0]$6899 - attribute \src "libresoc.v:145262.3-145263.49" + attribute \src "libresoc.v:145739.3-145780.6" + wire width 32 $0\logical_op__insn$next[31:0]$6831 + attribute \src "libresoc.v:145602.3-145603.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$6900 - attribute \src "libresoc.v:145228.3-145229.59" + attribute \src "libresoc.v:145739.3-145780.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$6832 + attribute \src "libresoc.v:145568.3-145569.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $0\logical_op__invert_in$next[0:0]$6901 - attribute \src "libresoc.v:145244.3-145245.59" + attribute \src "libresoc.v:145739.3-145780.6" + wire $0\logical_op__invert_in$next[0:0]$6833 + attribute \src "libresoc.v:145584.3-145585.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $0\logical_op__invert_out$next[0:0]$6902 - attribute \src "libresoc.v:145250.3-145251.61" + attribute \src "libresoc.v:145739.3-145780.6" + wire $0\logical_op__invert_out$next[0:0]$6834 + attribute \src "libresoc.v:145590.3-145591.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $0\logical_op__is_32bit$next[0:0]$6903 - attribute \src "libresoc.v:145256.3-145257.57" + attribute \src "libresoc.v:145739.3-145780.6" + wire $0\logical_op__is_32bit$next[0:0]$6835 + attribute \src "libresoc.v:145596.3-145597.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $0\logical_op__is_signed$next[0:0]$6904 - attribute \src "libresoc.v:145258.3-145259.59" + attribute \src "libresoc.v:145739.3-145780.6" + wire $0\logical_op__is_signed$next[0:0]$6836 + attribute \src "libresoc.v:145598.3-145599.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $0\logical_op__oe__oe$next[0:0]$6905 - attribute \src "libresoc.v:145240.3-145241.53" + attribute \src "libresoc.v:145739.3-145780.6" + wire $0\logical_op__oe__oe$next[0:0]$6837 + attribute \src "libresoc.v:145580.3-145581.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $0\logical_op__oe__ok$next[0:0]$6906 - attribute \src "libresoc.v:145242.3-145243.53" + attribute \src "libresoc.v:145739.3-145780.6" + wire $0\logical_op__oe__ok$next[0:0]$6838 + attribute \src "libresoc.v:145582.3-145583.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $0\logical_op__output_carry$next[0:0]$6907 - attribute \src "libresoc.v:145254.3-145255.65" + attribute \src "libresoc.v:145739.3-145780.6" + wire $0\logical_op__output_carry$next[0:0]$6839 + attribute \src "libresoc.v:145594.3-145595.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $0\logical_op__rc__ok$next[0:0]$6908 - attribute \src "libresoc.v:145238.3-145239.53" + attribute \src "libresoc.v:145739.3-145780.6" + wire $0\logical_op__rc__ok$next[0:0]$6840 + attribute \src "libresoc.v:145578.3-145579.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $0\logical_op__rc__rc$next[0:0]$6909 - attribute \src "libresoc.v:145236.3-145237.53" + attribute \src "libresoc.v:145739.3-145780.6" + wire $0\logical_op__rc__rc$next[0:0]$6841 + attribute \src "libresoc.v:145576.3-145577.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $0\logical_op__write_cr0$next[0:0]$6910 - attribute \src "libresoc.v:145252.3-145253.59" + attribute \src "libresoc.v:145739.3-145780.6" + wire $0\logical_op__write_cr0$next[0:0]$6842 + attribute \src "libresoc.v:145592.3-145593.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $0\logical_op__zero_a$next[0:0]$6911 - attribute \src "libresoc.v:145246.3-145247.53" + attribute \src "libresoc.v:145739.3-145780.6" + wire $0\logical_op__zero_a$next[0:0]$6843 + attribute \src "libresoc.v:145586.3-145587.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:145386.3-145398.6" - wire width 2 $0\muxid$next[1:0]$6891 - attribute \src "libresoc.v:145264.3-145265.27" + attribute \src "libresoc.v:145726.3-145738.6" + wire width 2 $0\muxid$next[1:0]$6823 + attribute \src "libresoc.v:145604.3-145605.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:145441.3-145459.6" - wire width 64 $0\o$next[63:0]$6937 - attribute \src "libresoc.v:145224.3-145225.19" + attribute \src "libresoc.v:145781.3-145799.6" + wire width 64 $0\o$next[63:0]$6869 + attribute \src "libresoc.v:145564.3-145565.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:145441.3-145459.6" - wire $0\o_ok$next[0:0]$6938 - attribute \src "libresoc.v:145226.3-145227.25" + attribute \src "libresoc.v:145781.3-145799.6" + wire $0\o_ok$next[0:0]$6870 + attribute \src "libresoc.v:145566.3-145567.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:145368.3-145385.6" - wire $0\r_busy$next[0:0]$6887 - attribute \src "libresoc.v:145266.3-145267.29" + attribute \src "libresoc.v:145708.3-145725.6" + wire $0\r_busy$next[0:0]$6819 + attribute \src "libresoc.v:145606.3-145607.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:145479.3-145497.6" - wire $0\xer_so$next[0:0]$6949 - attribute \src "libresoc.v:145216.3-145217.29" + attribute \src "libresoc.v:145819.3-145837.6" + wire $0\xer_so$next[0:0]$6881 + attribute \src "libresoc.v:145556.3-145557.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:145479.3-145497.6" - wire $0\xer_so_ok$next[0:0]$6950 - attribute \src "libresoc.v:145218.3-145219.35" + attribute \src "libresoc.v:145819.3-145837.6" + wire $0\xer_so_ok$next[0:0]$6882 + attribute \src "libresoc.v:145558.3-145559.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:145460.3-145478.6" - wire width 4 $1\cr_a$next[3:0]$6945 - attribute \src "libresoc.v:144140.13-144140.24" + attribute \src "libresoc.v:145800.3-145818.6" + wire width 4 $1\cr_a$next[3:0]$6877 + attribute \src "libresoc.v:144480.13-144480.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:145460.3-145478.6" - wire $1\cr_a_ok$next[0:0]$6946 - attribute \src "libresoc.v:144149.7-144149.21" + attribute \src "libresoc.v:145800.3-145818.6" + wire $1\cr_a_ok$next[0:0]$6878 + attribute \src "libresoc.v:144489.7-144489.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire width 4 $1\logical_op__data_len$next[3:0]$6912 - attribute \src "libresoc.v:144434.13-144434.40" + attribute \src "libresoc.v:145739.3-145780.6" + wire width 4 $1\logical_op__data_len$next[3:0]$6844 + attribute \src "libresoc.v:144774.13-144774.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire width 14 $1\logical_op__fn_unit$next[13:0]$6913 - attribute \src "libresoc.v:144458.14-144458.44" + attribute \src "libresoc.v:145739.3-145780.6" + wire width 14 $1\logical_op__fn_unit$next[13:0]$6845 + attribute \src "libresoc.v:144798.14-144798.44" wire width 14 $1\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$6914 - attribute \src "libresoc.v:144497.14-144497.63" + attribute \src "libresoc.v:145739.3-145780.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$6846 + attribute \src "libresoc.v:144837.14-144837.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $1\logical_op__imm_data__ok$next[0:0]$6915 - attribute \src "libresoc.v:144506.7-144506.38" + attribute \src "libresoc.v:145739.3-145780.6" + wire $1\logical_op__imm_data__ok$next[0:0]$6847 + attribute \src "libresoc.v:144846.7-144846.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$6916 - attribute \src "libresoc.v:144519.13-144519.43" + attribute \src "libresoc.v:145739.3-145780.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$6848 + attribute \src "libresoc.v:144859.13-144859.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire width 32 $1\logical_op__insn$next[31:0]$6917 - attribute \src "libresoc.v:144536.14-144536.38" + attribute \src "libresoc.v:145739.3-145780.6" + wire width 32 $1\logical_op__insn$next[31:0]$6849 + attribute \src "libresoc.v:144876.14-144876.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$6918 - attribute \src "libresoc.v:144620.13-144620.42" + attribute \src "libresoc.v:145739.3-145780.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$6850 + attribute \src "libresoc.v:144960.13-144960.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $1\logical_op__invert_in$next[0:0]$6919 - attribute \src "libresoc.v:144779.7-144779.35" + attribute \src "libresoc.v:145739.3-145780.6" + wire $1\logical_op__invert_in$next[0:0]$6851 + attribute \src "libresoc.v:145119.7-145119.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $1\logical_op__invert_out$next[0:0]$6920 - attribute \src "libresoc.v:144788.7-144788.36" + attribute \src "libresoc.v:145739.3-145780.6" + wire $1\logical_op__invert_out$next[0:0]$6852 + attribute \src "libresoc.v:145128.7-145128.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $1\logical_op__is_32bit$next[0:0]$6921 - attribute \src "libresoc.v:144797.7-144797.34" + attribute \src "libresoc.v:145739.3-145780.6" + wire $1\logical_op__is_32bit$next[0:0]$6853 + attribute \src "libresoc.v:145137.7-145137.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $1\logical_op__is_signed$next[0:0]$6922 - attribute \src "libresoc.v:144806.7-144806.35" + attribute \src "libresoc.v:145739.3-145780.6" + wire $1\logical_op__is_signed$next[0:0]$6854 + attribute \src "libresoc.v:145146.7-145146.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $1\logical_op__oe__oe$next[0:0]$6923 - attribute \src "libresoc.v:144815.7-144815.32" + attribute \src "libresoc.v:145739.3-145780.6" + wire $1\logical_op__oe__oe$next[0:0]$6855 + attribute \src "libresoc.v:145155.7-145155.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $1\logical_op__oe__ok$next[0:0]$6924 - attribute \src "libresoc.v:144824.7-144824.32" + attribute \src "libresoc.v:145739.3-145780.6" + wire $1\logical_op__oe__ok$next[0:0]$6856 + attribute \src "libresoc.v:145164.7-145164.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $1\logical_op__output_carry$next[0:0]$6925 - attribute \src "libresoc.v:144833.7-144833.38" + attribute \src "libresoc.v:145739.3-145780.6" + wire $1\logical_op__output_carry$next[0:0]$6857 + attribute \src "libresoc.v:145173.7-145173.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $1\logical_op__rc__ok$next[0:0]$6926 - attribute \src "libresoc.v:144842.7-144842.32" + attribute \src "libresoc.v:145739.3-145780.6" + wire $1\logical_op__rc__ok$next[0:0]$6858 + attribute \src "libresoc.v:145182.7-145182.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $1\logical_op__rc__rc$next[0:0]$6927 - attribute \src "libresoc.v:144851.7-144851.32" + attribute \src "libresoc.v:145739.3-145780.6" + wire $1\logical_op__rc__rc$next[0:0]$6859 + attribute \src "libresoc.v:145191.7-145191.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $1\logical_op__write_cr0$next[0:0]$6928 - attribute \src "libresoc.v:144860.7-144860.35" + attribute \src "libresoc.v:145739.3-145780.6" + wire $1\logical_op__write_cr0$next[0:0]$6860 + attribute \src "libresoc.v:145200.7-145200.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:145399.3-145440.6" - wire $1\logical_op__zero_a$next[0:0]$6929 - attribute \src "libresoc.v:144869.7-144869.32" + attribute \src "libresoc.v:145739.3-145780.6" + wire $1\logical_op__zero_a$next[0:0]$6861 + attribute \src "libresoc.v:145209.7-145209.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:145386.3-145398.6" - wire width 2 $1\muxid$next[1:0]$6892 - attribute \src "libresoc.v:145154.13-145154.25" + attribute \src "libresoc.v:145726.3-145738.6" + wire width 2 $1\muxid$next[1:0]$6824 + attribute \src "libresoc.v:145494.13-145494.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:145441.3-145459.6" - wire width 64 $1\o$next[63:0]$6939 - attribute \src "libresoc.v:145169.14-145169.38" + attribute \src "libresoc.v:145781.3-145799.6" + wire width 64 $1\o$next[63:0]$6871 + attribute \src "libresoc.v:145509.14-145509.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:145441.3-145459.6" - wire $1\o_ok$next[0:0]$6940 - attribute \src "libresoc.v:145176.7-145176.18" + attribute \src "libresoc.v:145781.3-145799.6" + wire $1\o_ok$next[0:0]$6872 + attribute \src "libresoc.v:145516.7-145516.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:145368.3-145385.6" - wire $1\r_busy$next[0:0]$6888 - attribute \src "libresoc.v:145190.7-145190.20" + attribute \src "libresoc.v:145708.3-145725.6" + wire $1\r_busy$next[0:0]$6820 + attribute \src "libresoc.v:145530.7-145530.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:145479.3-145497.6" - wire $1\xer_so$next[0:0]$6951 - attribute \src "libresoc.v:145199.7-145199.20" + attribute \src "libresoc.v:145819.3-145837.6" + wire $1\xer_so$next[0:0]$6883 + attribute \src "libresoc.v:145539.7-145539.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:145479.3-145497.6" - wire $1\xer_so_ok$next[0:0]$6952 - attribute \src "libresoc.v:145208.7-145208.23" + attribute \src "libresoc.v:145819.3-145837.6" + wire $1\xer_so_ok$next[0:0]$6884 + attribute \src "libresoc.v:145548.7-145548.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:145460.3-145478.6" - wire $2\cr_a_ok$next[0:0]$6947 - attribute \src "libresoc.v:145399.3-145440.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$6930 - attribute \src "libresoc.v:145399.3-145440.6" - wire $2\logical_op__imm_data__ok$next[0:0]$6931 - attribute \src "libresoc.v:145399.3-145440.6" - wire $2\logical_op__oe__oe$next[0:0]$6932 - attribute \src "libresoc.v:145399.3-145440.6" - wire $2\logical_op__oe__ok$next[0:0]$6933 - attribute \src "libresoc.v:145399.3-145440.6" - wire $2\logical_op__rc__ok$next[0:0]$6934 - attribute \src "libresoc.v:145399.3-145440.6" - wire $2\logical_op__rc__rc$next[0:0]$6935 - attribute \src "libresoc.v:145441.3-145459.6" - wire $2\o_ok$next[0:0]$6941 - attribute \src "libresoc.v:145368.3-145385.6" - wire $2\r_busy$next[0:0]$6889 - attribute \src "libresoc.v:145479.3-145497.6" - wire $2\xer_so_ok$next[0:0]$6953 - attribute \src "libresoc.v:145215.18-145215.118" - wire $and$libresoc.v:145215$6859_Y + attribute \src "libresoc.v:145800.3-145818.6" + wire $2\cr_a_ok$next[0:0]$6879 + attribute \src "libresoc.v:145739.3-145780.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$6862 + attribute \src "libresoc.v:145739.3-145780.6" + wire $2\logical_op__imm_data__ok$next[0:0]$6863 + attribute \src "libresoc.v:145739.3-145780.6" + wire $2\logical_op__oe__oe$next[0:0]$6864 + attribute \src "libresoc.v:145739.3-145780.6" + wire $2\logical_op__oe__ok$next[0:0]$6865 + attribute \src "libresoc.v:145739.3-145780.6" + wire $2\logical_op__rc__ok$next[0:0]$6866 + attribute \src "libresoc.v:145739.3-145780.6" + wire $2\logical_op__rc__rc$next[0:0]$6867 + attribute \src "libresoc.v:145781.3-145799.6" + wire $2\o_ok$next[0:0]$6873 + attribute \src "libresoc.v:145708.3-145725.6" + wire $2\r_busy$next[0:0]$6821 + attribute \src "libresoc.v:145819.3-145837.6" + wire $2\xer_so_ok$next[0:0]$6885 + attribute \src "libresoc.v:145555.18-145555.118" + wire $and$libresoc.v:145555$6791_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next - attribute \src "libresoc.v:144131.7-144131.15" + attribute \src "libresoc.v:144471.7-144471.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len @@ -236294,9 +235739,9 @@ module \logical_pipe1 wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_ra @@ -236304,7 +235749,7 @@ module \logical_pipe1 wire width 64 \main_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_xer_so$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid @@ -236320,17 +235765,17 @@ module \logical_pipe1 wire input 3 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 30 \p_ready_o @@ -236348,24 +235793,24 @@ module \logical_pipe1 wire width 64 input 50 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 51 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 52 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:145215$6859 + cell $and $and$libresoc.v:145555$6791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236373,10 +235818,10 @@ module \logical_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$63 connect \B \p_ready_o - connect \Y $and$libresoc.v:145215$6859_Y + connect \Y $and$libresoc.v:145555$6791_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:145268.14-145313.4" + attribute \src "libresoc.v:145608.14-145653.4" cell \input$50 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$38 @@ -236424,7 +235869,7 @@ module \logical_pipe1 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:145314.13-145359.4" + attribute \src "libresoc.v:145654.13-145699.4" cell \main$51 \main connect \logical_op__data_len \main_logical_op__data_len connect \logical_op__data_len$18 \main_logical_op__data_len$60 @@ -236472,424 +235917,424 @@ module \logical_pipe1 connect \xer_so$20 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:145360.10-145363.4" + attribute \src "libresoc.v:145700.10-145703.4" cell \n$49 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:145364.10-145367.4" + attribute \src "libresoc.v:145704.10-145707.4" cell \p$48 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:144131.7-144131.20" - process $proc$libresoc.v:144131$6954 + attribute \src "libresoc.v:144471.7-144471.20" + process $proc$libresoc.v:144471$6886 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:144140.13-144140.24" - process $proc$libresoc.v:144140$6955 + attribute \src "libresoc.v:144480.13-144480.24" + process $proc$libresoc.v:144480$6887 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:144149.7-144149.21" - process $proc$libresoc.v:144149$6956 + attribute \src "libresoc.v:144489.7-144489.21" + process $proc$libresoc.v:144489$6888 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:144434.13-144434.40" - process $proc$libresoc.v:144434$6957 + attribute \src "libresoc.v:144774.13-144774.40" + process $proc$libresoc.v:144774$6889 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:144458.14-144458.44" - process $proc$libresoc.v:144458$6958 + attribute \src "libresoc.v:144798.14-144798.44" + process $proc$libresoc.v:144798$6890 assign { } { } assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:144497.14-144497.63" - process $proc$libresoc.v:144497$6959 + attribute \src "libresoc.v:144837.14-144837.63" + process $proc$libresoc.v:144837$6891 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:144506.7-144506.38" - process $proc$libresoc.v:144506$6960 + attribute \src "libresoc.v:144846.7-144846.38" + process $proc$libresoc.v:144846$6892 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:144519.13-144519.43" - process $proc$libresoc.v:144519$6961 + attribute \src "libresoc.v:144859.13-144859.43" + process $proc$libresoc.v:144859$6893 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:144536.14-144536.38" - process $proc$libresoc.v:144536$6962 + attribute \src "libresoc.v:144876.14-144876.38" + process $proc$libresoc.v:144876$6894 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:144620.13-144620.42" - process $proc$libresoc.v:144620$6963 + attribute \src "libresoc.v:144960.13-144960.42" + process $proc$libresoc.v:144960$6895 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:144779.7-144779.35" - process $proc$libresoc.v:144779$6964 + attribute \src "libresoc.v:145119.7-145119.35" + process $proc$libresoc.v:145119$6896 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:144788.7-144788.36" - process $proc$libresoc.v:144788$6965 + attribute \src "libresoc.v:145128.7-145128.36" + process $proc$libresoc.v:145128$6897 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:144797.7-144797.34" - process $proc$libresoc.v:144797$6966 + attribute \src "libresoc.v:145137.7-145137.34" + process $proc$libresoc.v:145137$6898 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:144806.7-144806.35" - process $proc$libresoc.v:144806$6967 + attribute \src "libresoc.v:145146.7-145146.35" + process $proc$libresoc.v:145146$6899 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:144815.7-144815.32" - process $proc$libresoc.v:144815$6968 + attribute \src "libresoc.v:145155.7-145155.32" + process $proc$libresoc.v:145155$6900 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:144824.7-144824.32" - process $proc$libresoc.v:144824$6969 + attribute \src "libresoc.v:145164.7-145164.32" + process $proc$libresoc.v:145164$6901 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:144833.7-144833.38" - process $proc$libresoc.v:144833$6970 + attribute \src "libresoc.v:145173.7-145173.38" + process $proc$libresoc.v:145173$6902 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:144842.7-144842.32" - process $proc$libresoc.v:144842$6971 + attribute \src "libresoc.v:145182.7-145182.32" + process $proc$libresoc.v:145182$6903 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:144851.7-144851.32" - process $proc$libresoc.v:144851$6972 + attribute \src "libresoc.v:145191.7-145191.32" + process $proc$libresoc.v:145191$6904 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:144860.7-144860.35" - process $proc$libresoc.v:144860$6973 + attribute \src "libresoc.v:145200.7-145200.35" + process $proc$libresoc.v:145200$6905 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:144869.7-144869.32" - process $proc$libresoc.v:144869$6974 + attribute \src "libresoc.v:145209.7-145209.32" + process $proc$libresoc.v:145209$6906 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:145154.13-145154.25" - process $proc$libresoc.v:145154$6975 + attribute \src "libresoc.v:145494.13-145494.25" + process $proc$libresoc.v:145494$6907 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:145169.14-145169.38" - process $proc$libresoc.v:145169$6976 + attribute \src "libresoc.v:145509.14-145509.38" + process $proc$libresoc.v:145509$6908 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:145176.7-145176.18" - process $proc$libresoc.v:145176$6977 + attribute \src "libresoc.v:145516.7-145516.18" + process $proc$libresoc.v:145516$6909 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:145190.7-145190.20" - process $proc$libresoc.v:145190$6978 + attribute \src "libresoc.v:145530.7-145530.20" + process $proc$libresoc.v:145530$6910 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:145199.7-145199.20" - process $proc$libresoc.v:145199$6979 + attribute \src "libresoc.v:145539.7-145539.20" + process $proc$libresoc.v:145539$6911 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:145208.7-145208.23" - process $proc$libresoc.v:145208$6980 + attribute \src "libresoc.v:145548.7-145548.23" + process $proc$libresoc.v:145548$6912 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:145216.3-145217.29" - process $proc$libresoc.v:145216$6860 + attribute \src "libresoc.v:145556.3-145557.29" + process $proc$libresoc.v:145556$6792 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:145218.3-145219.35" - process $proc$libresoc.v:145218$6861 + attribute \src "libresoc.v:145558.3-145559.35" + process $proc$libresoc.v:145558$6793 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:145220.3-145221.25" - process $proc$libresoc.v:145220$6862 + attribute \src "libresoc.v:145560.3-145561.25" + process $proc$libresoc.v:145560$6794 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:145222.3-145223.31" - process $proc$libresoc.v:145222$6863 + attribute \src "libresoc.v:145562.3-145563.31" + process $proc$libresoc.v:145562$6795 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:145224.3-145225.19" - process $proc$libresoc.v:145224$6864 + attribute \src "libresoc.v:145564.3-145565.19" + process $proc$libresoc.v:145564$6796 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:145226.3-145227.25" - process $proc$libresoc.v:145226$6865 + attribute \src "libresoc.v:145566.3-145567.25" + process $proc$libresoc.v:145566$6797 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:145228.3-145229.59" - process $proc$libresoc.v:145228$6866 + attribute \src "libresoc.v:145568.3-145569.59" + process $proc$libresoc.v:145568$6798 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:145230.3-145231.55" - process $proc$libresoc.v:145230$6867 + attribute \src "libresoc.v:145570.3-145571.55" + process $proc$libresoc.v:145570$6799 assign { } { } assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:145232.3-145233.69" - process $proc$libresoc.v:145232$6868 + attribute \src "libresoc.v:145572.3-145573.69" + process $proc$libresoc.v:145572$6800 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:145234.3-145235.65" - process $proc$libresoc.v:145234$6869 + attribute \src "libresoc.v:145574.3-145575.65" + process $proc$libresoc.v:145574$6801 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:145236.3-145237.53" - process $proc$libresoc.v:145236$6870 + attribute \src "libresoc.v:145576.3-145577.53" + process $proc$libresoc.v:145576$6802 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:145238.3-145239.53" - process $proc$libresoc.v:145238$6871 + attribute \src "libresoc.v:145578.3-145579.53" + process $proc$libresoc.v:145578$6803 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:145240.3-145241.53" - process $proc$libresoc.v:145240$6872 + attribute \src "libresoc.v:145580.3-145581.53" + process $proc$libresoc.v:145580$6804 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:145242.3-145243.53" - process $proc$libresoc.v:145242$6873 + attribute \src "libresoc.v:145582.3-145583.53" + process $proc$libresoc.v:145582$6805 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:145244.3-145245.59" - process $proc$libresoc.v:145244$6874 + attribute \src "libresoc.v:145584.3-145585.59" + process $proc$libresoc.v:145584$6806 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:145246.3-145247.53" - process $proc$libresoc.v:145246$6875 + attribute \src "libresoc.v:145586.3-145587.53" + process $proc$libresoc.v:145586$6807 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:145248.3-145249.63" - process $proc$libresoc.v:145248$6876 + attribute \src "libresoc.v:145588.3-145589.63" + process $proc$libresoc.v:145588$6808 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:145250.3-145251.61" - process $proc$libresoc.v:145250$6877 + attribute \src "libresoc.v:145590.3-145591.61" + process $proc$libresoc.v:145590$6809 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:145252.3-145253.59" - process $proc$libresoc.v:145252$6878 + attribute \src "libresoc.v:145592.3-145593.59" + process $proc$libresoc.v:145592$6810 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:145254.3-145255.65" - process $proc$libresoc.v:145254$6879 + attribute \src "libresoc.v:145594.3-145595.65" + process $proc$libresoc.v:145594$6811 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:145256.3-145257.57" - process $proc$libresoc.v:145256$6880 + attribute \src "libresoc.v:145596.3-145597.57" + process $proc$libresoc.v:145596$6812 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:145258.3-145259.59" - process $proc$libresoc.v:145258$6881 + attribute \src "libresoc.v:145598.3-145599.59" + process $proc$libresoc.v:145598$6813 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:145260.3-145261.57" - process $proc$libresoc.v:145260$6882 + attribute \src "libresoc.v:145600.3-145601.57" + process $proc$libresoc.v:145600$6814 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:145262.3-145263.49" - process $proc$libresoc.v:145262$6883 + attribute \src "libresoc.v:145602.3-145603.49" + process $proc$libresoc.v:145602$6815 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:145264.3-145265.27" - process $proc$libresoc.v:145264$6884 + attribute \src "libresoc.v:145604.3-145605.27" + process $proc$libresoc.v:145604$6816 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:145266.3-145267.29" - process $proc$libresoc.v:145266$6885 + attribute \src "libresoc.v:145606.3-145607.29" + process $proc$libresoc.v:145606$6817 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:145368.3-145385.6" - process $proc$libresoc.v:145368$6886 + attribute \src "libresoc.v:145708.3-145725.6" + process $proc$libresoc.v:145708$6818 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$6887 $2\r_busy$next[0:0]$6889 - attribute \src "libresoc.v:145369.5-145369.29" + assign $0\r_busy$next[0:0]$6819 $2\r_busy$next[0:0]$6821 + attribute \src "libresoc.v:145709.5-145709.29" switch \initial - attribute \src "libresoc.v:145369.9-145369.17" + attribute \src "libresoc.v:145709.9-145709.17" case 1'1 case end @@ -236898,34 +236343,34 @@ module \logical_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$6888 1'1 + assign $1\r_busy$next[0:0]$6820 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$6888 1'0 + assign $1\r_busy$next[0:0]$6820 1'0 case - assign $1\r_busy$next[0:0]$6888 \r_busy + assign $1\r_busy$next[0:0]$6820 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$6889 1'0 + assign $2\r_busy$next[0:0]$6821 1'0 case - assign $2\r_busy$next[0:0]$6889 $1\r_busy$next[0:0]$6888 + assign $2\r_busy$next[0:0]$6821 $1\r_busy$next[0:0]$6820 end sync always - update \r_busy$next $0\r_busy$next[0:0]$6887 + update \r_busy$next $0\r_busy$next[0:0]$6819 end - attribute \src "libresoc.v:145386.3-145398.6" - process $proc$libresoc.v:145386$6890 + attribute \src "libresoc.v:145726.3-145738.6" + process $proc$libresoc.v:145726$6822 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$6891 $1\muxid$next[1:0]$6892 - attribute \src "libresoc.v:145387.5-145387.29" + assign $0\muxid$next[1:0]$6823 $1\muxid$next[1:0]$6824 + attribute \src "libresoc.v:145727.5-145727.29" switch \initial - attribute \src "libresoc.v:145387.9-145387.17" + attribute \src "libresoc.v:145727.9-145727.17" case 1'1 case end @@ -236934,19 +236379,19 @@ module \logical_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$6892 \muxid$66 + assign $1\muxid$next[1:0]$6824 \muxid$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$6892 \muxid$66 + assign $1\muxid$next[1:0]$6824 \muxid$66 case - assign $1\muxid$next[1:0]$6892 \muxid + assign $1\muxid$next[1:0]$6824 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$6891 + update \muxid$next $0\muxid$next[1:0]$6823 end - attribute \src "libresoc.v:145399.3-145440.6" - process $proc$libresoc.v:145399$6893 + attribute \src "libresoc.v:145739.3-145780.6" + process $proc$libresoc.v:145739$6825 assign { } { } assign { } { } assign { } { } @@ -236983,33 +236428,33 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$next[3:0]$6894 $1\logical_op__data_len$next[3:0]$6912 - assign $0\logical_op__fn_unit$next[13:0]$6895 $1\logical_op__fn_unit$next[13:0]$6913 + assign $0\logical_op__data_len$next[3:0]$6826 $1\logical_op__data_len$next[3:0]$6844 + assign $0\logical_op__fn_unit$next[13:0]$6827 $1\logical_op__fn_unit$next[13:0]$6845 assign { } { } assign { } { } - assign $0\logical_op__input_carry$next[1:0]$6898 $1\logical_op__input_carry$next[1:0]$6916 - assign $0\logical_op__insn$next[31:0]$6899 $1\logical_op__insn$next[31:0]$6917 - assign $0\logical_op__insn_type$next[6:0]$6900 $1\logical_op__insn_type$next[6:0]$6918 - assign $0\logical_op__invert_in$next[0:0]$6901 $1\logical_op__invert_in$next[0:0]$6919 - assign $0\logical_op__invert_out$next[0:0]$6902 $1\logical_op__invert_out$next[0:0]$6920 - assign $0\logical_op__is_32bit$next[0:0]$6903 $1\logical_op__is_32bit$next[0:0]$6921 - assign $0\logical_op__is_signed$next[0:0]$6904 $1\logical_op__is_signed$next[0:0]$6922 + assign $0\logical_op__input_carry$next[1:0]$6830 $1\logical_op__input_carry$next[1:0]$6848 + assign $0\logical_op__insn$next[31:0]$6831 $1\logical_op__insn$next[31:0]$6849 + assign $0\logical_op__insn_type$next[6:0]$6832 $1\logical_op__insn_type$next[6:0]$6850 + assign $0\logical_op__invert_in$next[0:0]$6833 $1\logical_op__invert_in$next[0:0]$6851 + assign $0\logical_op__invert_out$next[0:0]$6834 $1\logical_op__invert_out$next[0:0]$6852 + assign $0\logical_op__is_32bit$next[0:0]$6835 $1\logical_op__is_32bit$next[0:0]$6853 + assign $0\logical_op__is_signed$next[0:0]$6836 $1\logical_op__is_signed$next[0:0]$6854 assign { } { } assign { } { } - assign $0\logical_op__output_carry$next[0:0]$6907 $1\logical_op__output_carry$next[0:0]$6925 + assign $0\logical_op__output_carry$next[0:0]$6839 $1\logical_op__output_carry$next[0:0]$6857 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$6910 $1\logical_op__write_cr0$next[0:0]$6928 - assign $0\logical_op__zero_a$next[0:0]$6911 $1\logical_op__zero_a$next[0:0]$6929 - assign $0\logical_op__imm_data__data$next[63:0]$6896 $2\logical_op__imm_data__data$next[63:0]$6930 - assign $0\logical_op__imm_data__ok$next[0:0]$6897 $2\logical_op__imm_data__ok$next[0:0]$6931 - assign $0\logical_op__oe__oe$next[0:0]$6905 $2\logical_op__oe__oe$next[0:0]$6932 - assign $0\logical_op__oe__ok$next[0:0]$6906 $2\logical_op__oe__ok$next[0:0]$6933 - assign $0\logical_op__rc__ok$next[0:0]$6908 $2\logical_op__rc__ok$next[0:0]$6934 - assign $0\logical_op__rc__rc$next[0:0]$6909 $2\logical_op__rc__rc$next[0:0]$6935 - attribute \src "libresoc.v:145400.5-145400.29" + assign $0\logical_op__write_cr0$next[0:0]$6842 $1\logical_op__write_cr0$next[0:0]$6860 + assign $0\logical_op__zero_a$next[0:0]$6843 $1\logical_op__zero_a$next[0:0]$6861 + assign $0\logical_op__imm_data__data$next[63:0]$6828 $2\logical_op__imm_data__data$next[63:0]$6862 + assign $0\logical_op__imm_data__ok$next[0:0]$6829 $2\logical_op__imm_data__ok$next[0:0]$6863 + assign $0\logical_op__oe__oe$next[0:0]$6837 $2\logical_op__oe__oe$next[0:0]$6864 + assign $0\logical_op__oe__ok$next[0:0]$6838 $2\logical_op__oe__ok$next[0:0]$6865 + assign $0\logical_op__rc__ok$next[0:0]$6840 $2\logical_op__rc__ok$next[0:0]$6866 + assign $0\logical_op__rc__rc$next[0:0]$6841 $2\logical_op__rc__rc$next[0:0]$6867 + attribute \src "libresoc.v:145740.5-145740.29" switch \initial - attribute \src "libresoc.v:145400.9-145400.17" + attribute \src "libresoc.v:145740.9-145740.17" case 1'1 case end @@ -237035,7 +236480,7 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$6917 $1\logical_op__data_len$next[3:0]$6912 $1\logical_op__is_signed$next[0:0]$6922 $1\logical_op__is_32bit$next[0:0]$6921 $1\logical_op__output_carry$next[0:0]$6925 $1\logical_op__write_cr0$next[0:0]$6928 $1\logical_op__invert_out$next[0:0]$6920 $1\logical_op__input_carry$next[1:0]$6916 $1\logical_op__zero_a$next[0:0]$6929 $1\logical_op__invert_in$next[0:0]$6919 $1\logical_op__oe__ok$next[0:0]$6924 $1\logical_op__oe__oe$next[0:0]$6923 $1\logical_op__rc__ok$next[0:0]$6926 $1\logical_op__rc__rc$next[0:0]$6927 $1\logical_op__imm_data__ok$next[0:0]$6915 $1\logical_op__imm_data__data$next[63:0]$6914 $1\logical_op__fn_unit$next[13:0]$6913 $1\logical_op__insn_type$next[6:0]$6918 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + assign { $1\logical_op__insn$next[31:0]$6849 $1\logical_op__data_len$next[3:0]$6844 $1\logical_op__is_signed$next[0:0]$6854 $1\logical_op__is_32bit$next[0:0]$6853 $1\logical_op__output_carry$next[0:0]$6857 $1\logical_op__write_cr0$next[0:0]$6860 $1\logical_op__invert_out$next[0:0]$6852 $1\logical_op__input_carry$next[1:0]$6848 $1\logical_op__zero_a$next[0:0]$6861 $1\logical_op__invert_in$next[0:0]$6851 $1\logical_op__oe__ok$next[0:0]$6856 $1\logical_op__oe__oe$next[0:0]$6855 $1\logical_op__rc__ok$next[0:0]$6858 $1\logical_op__rc__rc$next[0:0]$6859 $1\logical_op__imm_data__ok$next[0:0]$6847 $1\logical_op__imm_data__data$next[63:0]$6846 $1\logical_op__fn_unit$next[13:0]$6845 $1\logical_op__insn_type$next[6:0]$6850 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -237056,26 +236501,26 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$6917 $1\logical_op__data_len$next[3:0]$6912 $1\logical_op__is_signed$next[0:0]$6922 $1\logical_op__is_32bit$next[0:0]$6921 $1\logical_op__output_carry$next[0:0]$6925 $1\logical_op__write_cr0$next[0:0]$6928 $1\logical_op__invert_out$next[0:0]$6920 $1\logical_op__input_carry$next[1:0]$6916 $1\logical_op__zero_a$next[0:0]$6929 $1\logical_op__invert_in$next[0:0]$6919 $1\logical_op__oe__ok$next[0:0]$6924 $1\logical_op__oe__oe$next[0:0]$6923 $1\logical_op__rc__ok$next[0:0]$6926 $1\logical_op__rc__rc$next[0:0]$6927 $1\logical_op__imm_data__ok$next[0:0]$6915 $1\logical_op__imm_data__data$next[63:0]$6914 $1\logical_op__fn_unit$next[13:0]$6913 $1\logical_op__insn_type$next[6:0]$6918 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + assign { $1\logical_op__insn$next[31:0]$6849 $1\logical_op__data_len$next[3:0]$6844 $1\logical_op__is_signed$next[0:0]$6854 $1\logical_op__is_32bit$next[0:0]$6853 $1\logical_op__output_carry$next[0:0]$6857 $1\logical_op__write_cr0$next[0:0]$6860 $1\logical_op__invert_out$next[0:0]$6852 $1\logical_op__input_carry$next[1:0]$6848 $1\logical_op__zero_a$next[0:0]$6861 $1\logical_op__invert_in$next[0:0]$6851 $1\logical_op__oe__ok$next[0:0]$6856 $1\logical_op__oe__oe$next[0:0]$6855 $1\logical_op__rc__ok$next[0:0]$6858 $1\logical_op__rc__rc$next[0:0]$6859 $1\logical_op__imm_data__ok$next[0:0]$6847 $1\logical_op__imm_data__data$next[63:0]$6846 $1\logical_op__fn_unit$next[13:0]$6845 $1\logical_op__insn_type$next[6:0]$6850 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } case - assign $1\logical_op__data_len$next[3:0]$6912 \logical_op__data_len - assign $1\logical_op__fn_unit$next[13:0]$6913 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$6914 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$6915 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$6916 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$6917 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$6918 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$6919 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$6920 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$6921 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$6922 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$6923 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$6924 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$6925 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$6926 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$6927 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$6928 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$6929 \logical_op__zero_a + assign $1\logical_op__data_len$next[3:0]$6844 \logical_op__data_len + assign $1\logical_op__fn_unit$next[13:0]$6845 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$6846 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$6847 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$6848 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$6849 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$6850 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$6851 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$6852 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$6853 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$6854 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$6855 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$6856 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$6857 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$6858 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$6859 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$6860 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$6861 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -237087,52 +236532,52 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$6930 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$6931 1'0 - assign $2\logical_op__rc__rc$next[0:0]$6935 1'0 - assign $2\logical_op__rc__ok$next[0:0]$6934 1'0 - assign $2\logical_op__oe__oe$next[0:0]$6932 1'0 - assign $2\logical_op__oe__ok$next[0:0]$6933 1'0 + assign $2\logical_op__imm_data__data$next[63:0]$6862 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$6863 1'0 + assign $2\logical_op__rc__rc$next[0:0]$6867 1'0 + assign $2\logical_op__rc__ok$next[0:0]$6866 1'0 + assign $2\logical_op__oe__oe$next[0:0]$6864 1'0 + assign $2\logical_op__oe__ok$next[0:0]$6865 1'0 case - assign $2\logical_op__imm_data__data$next[63:0]$6930 $1\logical_op__imm_data__data$next[63:0]$6914 - assign $2\logical_op__imm_data__ok$next[0:0]$6931 $1\logical_op__imm_data__ok$next[0:0]$6915 - assign $2\logical_op__oe__oe$next[0:0]$6932 $1\logical_op__oe__oe$next[0:0]$6923 - assign $2\logical_op__oe__ok$next[0:0]$6933 $1\logical_op__oe__ok$next[0:0]$6924 - assign $2\logical_op__rc__ok$next[0:0]$6934 $1\logical_op__rc__ok$next[0:0]$6926 - assign $2\logical_op__rc__rc$next[0:0]$6935 $1\logical_op__rc__rc$next[0:0]$6927 + assign $2\logical_op__imm_data__data$next[63:0]$6862 $1\logical_op__imm_data__data$next[63:0]$6846 + assign $2\logical_op__imm_data__ok$next[0:0]$6863 $1\logical_op__imm_data__ok$next[0:0]$6847 + assign $2\logical_op__oe__oe$next[0:0]$6864 $1\logical_op__oe__oe$next[0:0]$6855 + assign $2\logical_op__oe__ok$next[0:0]$6865 $1\logical_op__oe__ok$next[0:0]$6856 + assign $2\logical_op__rc__ok$next[0:0]$6866 $1\logical_op__rc__ok$next[0:0]$6858 + assign $2\logical_op__rc__rc$next[0:0]$6867 $1\logical_op__rc__rc$next[0:0]$6859 end sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6894 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$6895 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6896 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6897 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6898 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6899 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6900 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6901 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6902 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6903 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6904 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6905 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6906 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6907 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6908 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6909 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6910 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6911 + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6826 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$6827 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6828 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6829 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6830 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6831 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6832 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6833 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6834 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6835 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6836 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6837 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6838 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6839 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6840 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6841 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6842 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6843 end - attribute \src "libresoc.v:145441.3-145459.6" - process $proc$libresoc.v:145441$6936 + attribute \src "libresoc.v:145781.3-145799.6" + process $proc$libresoc.v:145781$6868 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$6937 $1\o$next[63:0]$6939 + assign $0\o$next[63:0]$6869 $1\o$next[63:0]$6871 assign { } { } - assign $0\o_ok$next[0:0]$6938 $2\o_ok$next[0:0]$6941 - attribute \src "libresoc.v:145442.5-145442.29" + assign $0\o_ok$next[0:0]$6870 $2\o_ok$next[0:0]$6873 + attribute \src "libresoc.v:145782.5-145782.29" switch \initial - attribute \src "libresoc.v:145442.9-145442.17" + attribute \src "libresoc.v:145782.9-145782.17" case 1'1 case end @@ -237142,41 +236587,41 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$6940 $1\o$next[63:0]$6939 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$6872 $1\o$next[63:0]$6871 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$6940 $1\o$next[63:0]$6939 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$6872 $1\o$next[63:0]$6871 } { \o_ok$86 \o$85 } case - assign $1\o$next[63:0]$6939 \o - assign $1\o_ok$next[0:0]$6940 \o_ok + assign $1\o$next[63:0]$6871 \o + assign $1\o_ok$next[0:0]$6872 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$6941 1'0 + assign $2\o_ok$next[0:0]$6873 1'0 case - assign $2\o_ok$next[0:0]$6941 $1\o_ok$next[0:0]$6940 + assign $2\o_ok$next[0:0]$6873 $1\o_ok$next[0:0]$6872 end sync always - update \o$next $0\o$next[63:0]$6937 - update \o_ok$next $0\o_ok$next[0:0]$6938 + update \o$next $0\o$next[63:0]$6869 + update \o_ok$next $0\o_ok$next[0:0]$6870 end - attribute \src "libresoc.v:145460.3-145478.6" - process $proc$libresoc.v:145460$6942 + attribute \src "libresoc.v:145800.3-145818.6" + process $proc$libresoc.v:145800$6874 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$6943 $1\cr_a$next[3:0]$6945 + assign $0\cr_a$next[3:0]$6875 $1\cr_a$next[3:0]$6877 assign { } { } - assign $0\cr_a_ok$next[0:0]$6944 $2\cr_a_ok$next[0:0]$6947 - attribute \src "libresoc.v:145461.5-145461.29" + assign $0\cr_a_ok$next[0:0]$6876 $2\cr_a_ok$next[0:0]$6879 + attribute \src "libresoc.v:145801.5-145801.29" switch \initial - attribute \src "libresoc.v:145461.9-145461.17" + attribute \src "libresoc.v:145801.9-145801.17" case 1'1 case end @@ -237186,41 +236631,41 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$6946 $1\cr_a$next[3:0]$6945 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$6878 $1\cr_a$next[3:0]$6877 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$6946 $1\cr_a$next[3:0]$6945 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$6878 $1\cr_a$next[3:0]$6877 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\cr_a$next[3:0]$6945 \cr_a - assign $1\cr_a_ok$next[0:0]$6946 \cr_a_ok + assign $1\cr_a$next[3:0]$6877 \cr_a + assign $1\cr_a_ok$next[0:0]$6878 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$6947 1'0 + assign $2\cr_a_ok$next[0:0]$6879 1'0 case - assign $2\cr_a_ok$next[0:0]$6947 $1\cr_a_ok$next[0:0]$6946 + assign $2\cr_a_ok$next[0:0]$6879 $1\cr_a_ok$next[0:0]$6878 end sync always - update \cr_a$next $0\cr_a$next[3:0]$6943 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6944 + update \cr_a$next $0\cr_a$next[3:0]$6875 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6876 end - attribute \src "libresoc.v:145479.3-145497.6" - process $proc$libresoc.v:145479$6948 + attribute \src "libresoc.v:145819.3-145837.6" + process $proc$libresoc.v:145819$6880 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$6949 $1\xer_so$next[0:0]$6951 + assign $0\xer_so$next[0:0]$6881 $1\xer_so$next[0:0]$6883 assign { } { } - assign $0\xer_so_ok$next[0:0]$6950 $2\xer_so_ok$next[0:0]$6953 - attribute \src "libresoc.v:145480.5-145480.29" + assign $0\xer_so_ok$next[0:0]$6882 $2\xer_so_ok$next[0:0]$6885 + attribute \src "libresoc.v:145820.5-145820.29" switch \initial - attribute \src "libresoc.v:145480.9-145480.17" + attribute \src "libresoc.v:145820.9-145820.17" case 1'1 case end @@ -237230,30 +236675,30 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$6952 $1\xer_so$next[0:0]$6951 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$6884 $1\xer_so$next[0:0]$6883 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$6952 $1\xer_so$next[0:0]$6951 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$6884 $1\xer_so$next[0:0]$6883 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_so$next[0:0]$6951 \xer_so - assign $1\xer_so_ok$next[0:0]$6952 \xer_so_ok + assign $1\xer_so$next[0:0]$6883 \xer_so + assign $1\xer_so_ok$next[0:0]$6884 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$6953 1'0 + assign $2\xer_so_ok$next[0:0]$6885 1'0 case - assign $2\xer_so_ok$next[0:0]$6953 $1\xer_so_ok$next[0:0]$6952 + assign $2\xer_so_ok$next[0:0]$6885 $1\xer_so_ok$next[0:0]$6884 end sync always - update \xer_so$next $0\xer_so$next[0:0]$6949 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6950 + update \xer_so$next $0\xer_so$next[0:0]$6881 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6882 end - connect \$64 $and$libresoc.v:145215$6859_Y + connect \$64 $and$libresoc.v:145555$6791_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -237278,250 +236723,250 @@ module \logical_pipe1 connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:145525.1-146558.10" +attribute \src "libresoc.v:145865.1-146898.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" attribute \generator "nMigen" module \logical_pipe2 - attribute \src "libresoc.v:146525.3-146543.6" - wire width 4 $0\cr_a$22$next[3:0]$7086 - attribute \src "libresoc.v:146329.3-146330.33" - wire width 4 $0\cr_a$22[3:0]$6983 - attribute \src "libresoc.v:145537.13-145537.29" - wire width 4 $0\cr_a$22[3:0]$7093 - attribute \src "libresoc.v:146525.3-146543.6" - wire $0\cr_a_ok$23$next[0:0]$7087 - attribute \src "libresoc.v:146331.3-146332.39" - wire $0\cr_a_ok$23[0:0]$6985 - attribute \src "libresoc.v:145546.7-145546.26" - wire $0\cr_a_ok$23[0:0]$7095 - attribute \src "libresoc.v:145526.7-145526.20" + attribute \src "libresoc.v:146865.3-146883.6" + wire width 4 $0\cr_a$22$next[3:0]$7018 + attribute \src "libresoc.v:146669.3-146670.33" + wire width 4 $0\cr_a$22[3:0]$6915 + attribute \src "libresoc.v:145877.13-145877.29" + wire width 4 $0\cr_a$22[3:0]$7025 + attribute \src "libresoc.v:146865.3-146883.6" + wire $0\cr_a_ok$23$next[0:0]$7019 + attribute \src "libresoc.v:146671.3-146672.39" + wire $0\cr_a_ok$23[0:0]$6917 + attribute \src "libresoc.v:145886.7-145886.26" + wire $0\cr_a_ok$23[0:0]$7027 + attribute \src "libresoc.v:145866.7-145866.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146464.3-146505.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$7037 - attribute \src "libresoc.v:146369.3-146370.65" - wire width 4 $0\logical_op__data_len$18[3:0]$7023 - attribute \src "libresoc.v:145557.13-145557.45" - wire width 4 $0\logical_op__data_len$18[3:0]$7097 - attribute \src "libresoc.v:146464.3-146505.6" - wire width 14 $0\logical_op__fn_unit$3$next[13:0]$7038 - attribute \src "libresoc.v:146339.3-146340.61" - wire width 14 $0\logical_op__fn_unit$3[13:0]$6993 - attribute \src "libresoc.v:145596.14-145596.48" - wire width 14 $0\logical_op__fn_unit$3[13:0]$7099 - attribute \src "libresoc.v:146464.3-146505.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$7039 - attribute \src "libresoc.v:146341.3-146342.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$6995 - attribute \src "libresoc.v:145620.14-145620.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$7101 - attribute \src "libresoc.v:146464.3-146505.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$7040 - attribute \src "libresoc.v:146343.3-146344.71" - wire $0\logical_op__imm_data__ok$5[0:0]$6997 - attribute \src "libresoc.v:145629.7-145629.42" - wire $0\logical_op__imm_data__ok$5[0:0]$7103 - attribute \src "libresoc.v:146464.3-146505.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$7041 - attribute \src "libresoc.v:146357.3-146358.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$7011 - attribute \src "libresoc.v:145646.13-145646.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$7105 - attribute \src "libresoc.v:146464.3-146505.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$7042 - attribute \src "libresoc.v:146371.3-146372.57" - wire width 32 $0\logical_op__insn$19[31:0]$7025 - attribute \src "libresoc.v:145659.14-145659.43" - wire width 32 $0\logical_op__insn$19[31:0]$7107 - attribute \src "libresoc.v:146464.3-146505.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$7043 - attribute \src "libresoc.v:146337.3-146338.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$6991 - attribute \src "libresoc.v:145818.13-145818.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$7109 - attribute \src "libresoc.v:146464.3-146505.6" - wire $0\logical_op__invert_in$10$next[0:0]$7044 - attribute \src "libresoc.v:146353.3-146354.67" - wire $0\logical_op__invert_in$10[0:0]$7007 - attribute \src "libresoc.v:145902.7-145902.40" - wire $0\logical_op__invert_in$10[0:0]$7111 - attribute \src "libresoc.v:146464.3-146505.6" - wire $0\logical_op__invert_out$13$next[0:0]$7045 - attribute \src "libresoc.v:146359.3-146360.69" - wire $0\logical_op__invert_out$13[0:0]$7013 - attribute \src "libresoc.v:145911.7-145911.41" - wire $0\logical_op__invert_out$13[0:0]$7113 - attribute \src "libresoc.v:146464.3-146505.6" - wire $0\logical_op__is_32bit$16$next[0:0]$7046 - attribute \src "libresoc.v:146365.3-146366.65" - wire $0\logical_op__is_32bit$16[0:0]$7019 - attribute \src "libresoc.v:145920.7-145920.39" - wire $0\logical_op__is_32bit$16[0:0]$7115 - attribute \src "libresoc.v:146464.3-146505.6" - wire $0\logical_op__is_signed$17$next[0:0]$7047 - attribute \src "libresoc.v:146367.3-146368.67" - wire $0\logical_op__is_signed$17[0:0]$7021 - attribute \src "libresoc.v:145929.7-145929.40" - wire $0\logical_op__is_signed$17[0:0]$7117 - attribute \src "libresoc.v:146464.3-146505.6" - wire $0\logical_op__oe__oe$8$next[0:0]$7048 - attribute \src "libresoc.v:146349.3-146350.59" - wire $0\logical_op__oe__oe$8[0:0]$7003 - attribute \src "libresoc.v:145940.7-145940.36" - wire $0\logical_op__oe__oe$8[0:0]$7119 - attribute \src "libresoc.v:146464.3-146505.6" - wire $0\logical_op__oe__ok$9$next[0:0]$7049 - attribute \src "libresoc.v:146351.3-146352.59" - wire $0\logical_op__oe__ok$9[0:0]$7005 - attribute \src "libresoc.v:145949.7-145949.36" - wire $0\logical_op__oe__ok$9[0:0]$7121 - attribute \src "libresoc.v:146464.3-146505.6" - wire $0\logical_op__output_carry$15$next[0:0]$7050 - attribute \src "libresoc.v:146363.3-146364.73" - wire $0\logical_op__output_carry$15[0:0]$7017 - attribute \src "libresoc.v:145956.7-145956.43" - wire $0\logical_op__output_carry$15[0:0]$7123 - attribute \src "libresoc.v:146464.3-146505.6" - wire $0\logical_op__rc__ok$7$next[0:0]$7051 - attribute \src "libresoc.v:146347.3-146348.59" - wire $0\logical_op__rc__ok$7[0:0]$7001 - attribute \src "libresoc.v:145967.7-145967.36" - wire $0\logical_op__rc__ok$7[0:0]$7125 - attribute \src "libresoc.v:146464.3-146505.6" - wire $0\logical_op__rc__rc$6$next[0:0]$7052 - attribute \src "libresoc.v:146345.3-146346.59" - wire $0\logical_op__rc__rc$6[0:0]$6999 - attribute \src "libresoc.v:145976.7-145976.36" - wire $0\logical_op__rc__rc$6[0:0]$7127 - attribute \src "libresoc.v:146464.3-146505.6" - wire $0\logical_op__write_cr0$14$next[0:0]$7053 - attribute \src "libresoc.v:146361.3-146362.67" - wire $0\logical_op__write_cr0$14[0:0]$7015 - attribute \src "libresoc.v:145983.7-145983.40" - wire $0\logical_op__write_cr0$14[0:0]$7129 - attribute \src "libresoc.v:146464.3-146505.6" - wire $0\logical_op__zero_a$11$next[0:0]$7054 - attribute \src "libresoc.v:146355.3-146356.61" - wire $0\logical_op__zero_a$11[0:0]$7009 - attribute \src "libresoc.v:145992.7-145992.37" - wire $0\logical_op__zero_a$11[0:0]$7131 - attribute \src "libresoc.v:146451.3-146463.6" - wire width 2 $0\muxid$1$next[1:0]$7034 - attribute \src "libresoc.v:146373.3-146374.33" - wire width 2 $0\muxid$1[1:0]$7027 - attribute \src "libresoc.v:146001.13-146001.29" - wire width 2 $0\muxid$1[1:0]$7133 - attribute \src "libresoc.v:146506.3-146524.6" - wire width 64 $0\o$20$next[63:0]$7080 - attribute \src "libresoc.v:146333.3-146334.27" - wire width 64 $0\o$20[63:0]$6987 - attribute \src "libresoc.v:146016.14-146016.43" - wire width 64 $0\o$20[63:0]$7135 - attribute \src "libresoc.v:146506.3-146524.6" - wire $0\o_ok$21$next[0:0]$7081 - attribute \src "libresoc.v:146335.3-146336.33" - wire $0\o_ok$21[0:0]$6989 - attribute \src "libresoc.v:146025.7-146025.23" - wire $0\o_ok$21[0:0]$7137 - attribute \src "libresoc.v:146433.3-146450.6" - wire $0\r_busy$next[0:0]$7030 - attribute \src "libresoc.v:146375.3-146376.29" + attribute \src "libresoc.v:146804.3-146845.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$6969 + attribute \src "libresoc.v:146709.3-146710.65" + wire width 4 $0\logical_op__data_len$18[3:0]$6955 + attribute \src "libresoc.v:145897.13-145897.45" + wire width 4 $0\logical_op__data_len$18[3:0]$7029 + attribute \src "libresoc.v:146804.3-146845.6" + wire width 14 $0\logical_op__fn_unit$3$next[13:0]$6970 + attribute \src "libresoc.v:146679.3-146680.61" + wire width 14 $0\logical_op__fn_unit$3[13:0]$6925 + attribute \src "libresoc.v:145936.14-145936.48" + wire width 14 $0\logical_op__fn_unit$3[13:0]$7031 + attribute \src "libresoc.v:146804.3-146845.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6971 + attribute \src "libresoc.v:146681.3-146682.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6927 + attribute \src "libresoc.v:145960.14-145960.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$7033 + attribute \src "libresoc.v:146804.3-146845.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$6972 + attribute \src "libresoc.v:146683.3-146684.71" + wire $0\logical_op__imm_data__ok$5[0:0]$6929 + attribute \src "libresoc.v:145969.7-145969.42" + wire $0\logical_op__imm_data__ok$5[0:0]$7035 + attribute \src "libresoc.v:146804.3-146845.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$6973 + attribute \src "libresoc.v:146697.3-146698.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$6943 + attribute \src "libresoc.v:145986.13-145986.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$7037 + attribute \src "libresoc.v:146804.3-146845.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$6974 + attribute \src "libresoc.v:146711.3-146712.57" + wire width 32 $0\logical_op__insn$19[31:0]$6957 + attribute \src "libresoc.v:145999.14-145999.43" + wire width 32 $0\logical_op__insn$19[31:0]$7039 + attribute \src "libresoc.v:146804.3-146845.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$6975 + attribute \src "libresoc.v:146677.3-146678.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$6923 + attribute \src "libresoc.v:146158.13-146158.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$7041 + attribute \src "libresoc.v:146804.3-146845.6" + wire $0\logical_op__invert_in$10$next[0:0]$6976 + attribute \src "libresoc.v:146693.3-146694.67" + wire $0\logical_op__invert_in$10[0:0]$6939 + attribute \src "libresoc.v:146242.7-146242.40" + wire $0\logical_op__invert_in$10[0:0]$7043 + attribute \src "libresoc.v:146804.3-146845.6" + wire $0\logical_op__invert_out$13$next[0:0]$6977 + attribute \src "libresoc.v:146699.3-146700.69" + wire $0\logical_op__invert_out$13[0:0]$6945 + attribute \src "libresoc.v:146251.7-146251.41" + wire $0\logical_op__invert_out$13[0:0]$7045 + attribute \src "libresoc.v:146804.3-146845.6" + wire $0\logical_op__is_32bit$16$next[0:0]$6978 + attribute \src "libresoc.v:146705.3-146706.65" + wire $0\logical_op__is_32bit$16[0:0]$6951 + attribute \src "libresoc.v:146260.7-146260.39" + wire $0\logical_op__is_32bit$16[0:0]$7047 + attribute \src "libresoc.v:146804.3-146845.6" + wire $0\logical_op__is_signed$17$next[0:0]$6979 + attribute \src "libresoc.v:146707.3-146708.67" + wire $0\logical_op__is_signed$17[0:0]$6953 + attribute \src "libresoc.v:146269.7-146269.40" + wire $0\logical_op__is_signed$17[0:0]$7049 + attribute \src "libresoc.v:146804.3-146845.6" + wire $0\logical_op__oe__oe$8$next[0:0]$6980 + attribute \src "libresoc.v:146689.3-146690.59" + wire $0\logical_op__oe__oe$8[0:0]$6935 + attribute \src "libresoc.v:146280.7-146280.36" + wire $0\logical_op__oe__oe$8[0:0]$7051 + attribute \src "libresoc.v:146804.3-146845.6" + wire $0\logical_op__oe__ok$9$next[0:0]$6981 + attribute \src "libresoc.v:146691.3-146692.59" + wire $0\logical_op__oe__ok$9[0:0]$6937 + attribute \src "libresoc.v:146289.7-146289.36" + wire $0\logical_op__oe__ok$9[0:0]$7053 + attribute \src "libresoc.v:146804.3-146845.6" + wire $0\logical_op__output_carry$15$next[0:0]$6982 + attribute \src "libresoc.v:146703.3-146704.73" + wire $0\logical_op__output_carry$15[0:0]$6949 + attribute \src "libresoc.v:146296.7-146296.43" + wire $0\logical_op__output_carry$15[0:0]$7055 + attribute \src "libresoc.v:146804.3-146845.6" + wire $0\logical_op__rc__ok$7$next[0:0]$6983 + attribute \src "libresoc.v:146687.3-146688.59" + wire $0\logical_op__rc__ok$7[0:0]$6933 + attribute \src "libresoc.v:146307.7-146307.36" + wire $0\logical_op__rc__ok$7[0:0]$7057 + attribute \src "libresoc.v:146804.3-146845.6" + wire $0\logical_op__rc__rc$6$next[0:0]$6984 + attribute \src "libresoc.v:146685.3-146686.59" + wire $0\logical_op__rc__rc$6[0:0]$6931 + attribute \src "libresoc.v:146316.7-146316.36" + wire $0\logical_op__rc__rc$6[0:0]$7059 + attribute \src "libresoc.v:146804.3-146845.6" + wire $0\logical_op__write_cr0$14$next[0:0]$6985 + attribute \src "libresoc.v:146701.3-146702.67" + wire $0\logical_op__write_cr0$14[0:0]$6947 + attribute \src "libresoc.v:146323.7-146323.40" + wire $0\logical_op__write_cr0$14[0:0]$7061 + attribute \src "libresoc.v:146804.3-146845.6" + wire $0\logical_op__zero_a$11$next[0:0]$6986 + attribute \src "libresoc.v:146695.3-146696.61" + wire $0\logical_op__zero_a$11[0:0]$6941 + attribute \src "libresoc.v:146332.7-146332.37" + wire $0\logical_op__zero_a$11[0:0]$7063 + attribute \src "libresoc.v:146791.3-146803.6" + wire width 2 $0\muxid$1$next[1:0]$6966 + attribute \src "libresoc.v:146713.3-146714.33" + wire width 2 $0\muxid$1[1:0]$6959 + attribute \src "libresoc.v:146341.13-146341.29" + wire width 2 $0\muxid$1[1:0]$7065 + attribute \src "libresoc.v:146846.3-146864.6" + wire width 64 $0\o$20$next[63:0]$7012 + attribute \src "libresoc.v:146673.3-146674.27" + wire width 64 $0\o$20[63:0]$6919 + attribute \src "libresoc.v:146356.14-146356.43" + wire width 64 $0\o$20[63:0]$7067 + attribute \src "libresoc.v:146846.3-146864.6" + wire $0\o_ok$21$next[0:0]$7013 + attribute \src "libresoc.v:146675.3-146676.33" + wire $0\o_ok$21[0:0]$6921 + attribute \src "libresoc.v:146365.7-146365.23" + wire $0\o_ok$21[0:0]$7069 + attribute \src "libresoc.v:146773.3-146790.6" + wire $0\r_busy$next[0:0]$6962 + attribute \src "libresoc.v:146715.3-146716.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:146525.3-146543.6" - wire width 4 $1\cr_a$22$next[3:0]$7088 - attribute \src "libresoc.v:146525.3-146543.6" - wire $1\cr_a_ok$23$next[0:0]$7089 - attribute \src "libresoc.v:146464.3-146505.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$7055 - attribute \src "libresoc.v:146464.3-146505.6" - wire width 14 $1\logical_op__fn_unit$3$next[13:0]$7056 - attribute \src "libresoc.v:146464.3-146505.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7057 - attribute \src "libresoc.v:146464.3-146505.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$7058 - attribute \src "libresoc.v:146464.3-146505.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$7059 - attribute \src "libresoc.v:146464.3-146505.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$7060 - attribute \src "libresoc.v:146464.3-146505.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$7061 - attribute \src "libresoc.v:146464.3-146505.6" - wire $1\logical_op__invert_in$10$next[0:0]$7062 - attribute \src "libresoc.v:146464.3-146505.6" - wire $1\logical_op__invert_out$13$next[0:0]$7063 - attribute \src "libresoc.v:146464.3-146505.6" - wire $1\logical_op__is_32bit$16$next[0:0]$7064 - attribute \src "libresoc.v:146464.3-146505.6" - wire $1\logical_op__is_signed$17$next[0:0]$7065 - attribute \src "libresoc.v:146464.3-146505.6" - wire $1\logical_op__oe__oe$8$next[0:0]$7066 - attribute \src "libresoc.v:146464.3-146505.6" - wire $1\logical_op__oe__ok$9$next[0:0]$7067 - attribute \src "libresoc.v:146464.3-146505.6" - wire $1\logical_op__output_carry$15$next[0:0]$7068 - attribute \src "libresoc.v:146464.3-146505.6" - wire $1\logical_op__rc__ok$7$next[0:0]$7069 - attribute \src "libresoc.v:146464.3-146505.6" - wire $1\logical_op__rc__rc$6$next[0:0]$7070 - attribute \src "libresoc.v:146464.3-146505.6" - wire $1\logical_op__write_cr0$14$next[0:0]$7071 - attribute \src "libresoc.v:146464.3-146505.6" - wire $1\logical_op__zero_a$11$next[0:0]$7072 - attribute \src "libresoc.v:146451.3-146463.6" - wire width 2 $1\muxid$1$next[1:0]$7035 - attribute \src "libresoc.v:146506.3-146524.6" - wire width 64 $1\o$20$next[63:0]$7082 - attribute \src "libresoc.v:146506.3-146524.6" - wire $1\o_ok$21$next[0:0]$7083 - attribute \src "libresoc.v:146433.3-146450.6" - wire $1\r_busy$next[0:0]$7031 - attribute \src "libresoc.v:146319.7-146319.20" + attribute \src "libresoc.v:146865.3-146883.6" + wire width 4 $1\cr_a$22$next[3:0]$7020 + attribute \src "libresoc.v:146865.3-146883.6" + wire $1\cr_a_ok$23$next[0:0]$7021 + attribute \src "libresoc.v:146804.3-146845.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$6987 + attribute \src "libresoc.v:146804.3-146845.6" + wire width 14 $1\logical_op__fn_unit$3$next[13:0]$6988 + attribute \src "libresoc.v:146804.3-146845.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$6989 + attribute \src "libresoc.v:146804.3-146845.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$6990 + attribute \src "libresoc.v:146804.3-146845.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$6991 + attribute \src "libresoc.v:146804.3-146845.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$6992 + attribute \src "libresoc.v:146804.3-146845.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$6993 + attribute \src "libresoc.v:146804.3-146845.6" + wire $1\logical_op__invert_in$10$next[0:0]$6994 + attribute \src "libresoc.v:146804.3-146845.6" + wire $1\logical_op__invert_out$13$next[0:0]$6995 + attribute \src "libresoc.v:146804.3-146845.6" + wire $1\logical_op__is_32bit$16$next[0:0]$6996 + attribute \src "libresoc.v:146804.3-146845.6" + wire $1\logical_op__is_signed$17$next[0:0]$6997 + attribute \src "libresoc.v:146804.3-146845.6" + wire $1\logical_op__oe__oe$8$next[0:0]$6998 + attribute \src "libresoc.v:146804.3-146845.6" + wire $1\logical_op__oe__ok$9$next[0:0]$6999 + attribute \src "libresoc.v:146804.3-146845.6" + wire $1\logical_op__output_carry$15$next[0:0]$7000 + attribute \src "libresoc.v:146804.3-146845.6" + wire $1\logical_op__rc__ok$7$next[0:0]$7001 + attribute \src "libresoc.v:146804.3-146845.6" + wire $1\logical_op__rc__rc$6$next[0:0]$7002 + attribute \src "libresoc.v:146804.3-146845.6" + wire $1\logical_op__write_cr0$14$next[0:0]$7003 + attribute \src "libresoc.v:146804.3-146845.6" + wire $1\logical_op__zero_a$11$next[0:0]$7004 + attribute \src "libresoc.v:146791.3-146803.6" + wire width 2 $1\muxid$1$next[1:0]$6967 + attribute \src "libresoc.v:146846.3-146864.6" + wire width 64 $1\o$20$next[63:0]$7014 + attribute \src "libresoc.v:146846.3-146864.6" + wire $1\o_ok$21$next[0:0]$7015 + attribute \src "libresoc.v:146773.3-146790.6" + wire $1\r_busy$next[0:0]$6963 + attribute \src "libresoc.v:146659.7-146659.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:146525.3-146543.6" - wire $2\cr_a_ok$23$next[0:0]$7090 - attribute \src "libresoc.v:146464.3-146505.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7073 - attribute \src "libresoc.v:146464.3-146505.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$7074 - attribute \src "libresoc.v:146464.3-146505.6" - wire $2\logical_op__oe__oe$8$next[0:0]$7075 - attribute \src "libresoc.v:146464.3-146505.6" - wire $2\logical_op__oe__ok$9$next[0:0]$7076 - attribute \src "libresoc.v:146464.3-146505.6" - wire $2\logical_op__rc__ok$7$next[0:0]$7077 - attribute \src "libresoc.v:146464.3-146505.6" - wire $2\logical_op__rc__rc$6$next[0:0]$7078 - attribute \src "libresoc.v:146506.3-146524.6" - wire $2\o_ok$21$next[0:0]$7084 - attribute \src "libresoc.v:146433.3-146450.6" - wire $2\r_busy$next[0:0]$7032 - attribute \src "libresoc.v:146328.18-146328.118" - wire $and$libresoc.v:146328$6981_Y + attribute \src "libresoc.v:146865.3-146883.6" + wire $2\cr_a_ok$23$next[0:0]$7022 + attribute \src "libresoc.v:146804.3-146845.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7005 + attribute \src "libresoc.v:146804.3-146845.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$7006 + attribute \src "libresoc.v:146804.3-146845.6" + wire $2\logical_op__oe__oe$8$next[0:0]$7007 + attribute \src "libresoc.v:146804.3-146845.6" + wire $2\logical_op__oe__ok$9$next[0:0]$7008 + attribute \src "libresoc.v:146804.3-146845.6" + wire $2\logical_op__rc__ok$7$next[0:0]$7009 + attribute \src "libresoc.v:146804.3-146845.6" + wire $2\logical_op__rc__rc$6$next[0:0]$7010 + attribute \src "libresoc.v:146846.3-146864.6" + wire $2\o_ok$21$next[0:0]$7016 + attribute \src "libresoc.v:146773.3-146790.6" + wire $2\r_busy$next[0:0]$6964 + attribute \src "libresoc.v:146668.18-146668.118" + wire $and$libresoc.v:146668$6913_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 54 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 52 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 53 \cr_a_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$73 - attribute \src "libresoc.v:145526.7-145526.15" + attribute \src "libresoc.v:145866.7-145866.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -237963,27 +237408,27 @@ module \logical_pipe2 wire input 30 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 29 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 50 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 51 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_logical_op__data_len @@ -238249,15 +237694,15 @@ module \logical_pipe2 wire width 2 \output_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o @@ -238271,14 +237716,14 @@ module \logical_pipe2 wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 27 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 28 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:146328$6981 + cell $and $and$libresoc.v:146668$6913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238286,16 +237731,16 @@ module \logical_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$48 connect \B \p_ready_o - connect \Y $and$libresoc.v:146328$6981_Y + connect \Y $and$libresoc.v:146668$6913_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:146377.10-146380.4" + attribute \src "libresoc.v:146717.10-146720.4" cell \n$53 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:146381.15-146428.4" + attribute \src "libresoc.v:146721.15-146768.4" cell \output$54 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$45 @@ -238345,388 +237790,388 @@ module \logical_pipe2 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:146429.10-146432.4" + attribute \src "libresoc.v:146769.10-146772.4" cell \p$52 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:145526.7-145526.20" - process $proc$libresoc.v:145526$7091 + attribute \src "libresoc.v:145866.7-145866.20" + process $proc$libresoc.v:145866$7023 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:145537.13-145537.29" - process $proc$libresoc.v:145537$7092 + attribute \src "libresoc.v:145877.13-145877.29" + process $proc$libresoc.v:145877$7024 assign { } { } - assign $0\cr_a$22[3:0]$7093 4'0000 + assign $0\cr_a$22[3:0]$7025 4'0000 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$7093 + update \cr_a$22 $0\cr_a$22[3:0]$7025 end - attribute \src "libresoc.v:145546.7-145546.26" - process $proc$libresoc.v:145546$7094 + attribute \src "libresoc.v:145886.7-145886.26" + process $proc$libresoc.v:145886$7026 assign { } { } - assign $0\cr_a_ok$23[0:0]$7095 1'0 + assign $0\cr_a_ok$23[0:0]$7027 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7095 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7027 end - attribute \src "libresoc.v:145557.13-145557.45" - process $proc$libresoc.v:145557$7096 + attribute \src "libresoc.v:145897.13-145897.45" + process $proc$libresoc.v:145897$7028 assign { } { } - assign $0\logical_op__data_len$18[3:0]$7097 4'0000 + assign $0\logical_op__data_len$18[3:0]$7029 4'0000 sync always sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7097 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7029 end - attribute \src "libresoc.v:145596.14-145596.48" - process $proc$libresoc.v:145596$7098 + attribute \src "libresoc.v:145936.14-145936.48" + process $proc$libresoc.v:145936$7030 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$7099 14'00000000000000 + assign $0\logical_op__fn_unit$3[13:0]$7031 14'00000000000000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7099 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7031 end - attribute \src "libresoc.v:145620.14-145620.67" - process $proc$libresoc.v:145620$7100 + attribute \src "libresoc.v:145960.14-145960.67" + process $proc$libresoc.v:145960$7032 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$7101 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$4[63:0]$7033 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7101 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7033 end - attribute \src "libresoc.v:145629.7-145629.42" - process $proc$libresoc.v:145629$7102 + attribute \src "libresoc.v:145969.7-145969.42" + process $proc$libresoc.v:145969$7034 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$7103 1'0 + assign $0\logical_op__imm_data__ok$5[0:0]$7035 1'0 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7103 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7035 end - attribute \src "libresoc.v:145646.13-145646.48" - process $proc$libresoc.v:145646$7104 + attribute \src "libresoc.v:145986.13-145986.48" + process $proc$libresoc.v:145986$7036 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$7105 2'00 + assign $0\logical_op__input_carry$12[1:0]$7037 2'00 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7105 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7037 end - attribute \src "libresoc.v:145659.14-145659.43" - process $proc$libresoc.v:145659$7106 + attribute \src "libresoc.v:145999.14-145999.43" + process $proc$libresoc.v:145999$7038 assign { } { } - assign $0\logical_op__insn$19[31:0]$7107 0 + assign $0\logical_op__insn$19[31:0]$7039 0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7107 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7039 end - attribute \src "libresoc.v:145818.13-145818.46" - process $proc$libresoc.v:145818$7108 + attribute \src "libresoc.v:146158.13-146158.46" + process $proc$libresoc.v:146158$7040 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$7109 7'0000000 + assign $0\logical_op__insn_type$2[6:0]$7041 7'0000000 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7109 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7041 end - attribute \src "libresoc.v:145902.7-145902.40" - process $proc$libresoc.v:145902$7110 + attribute \src "libresoc.v:146242.7-146242.40" + process $proc$libresoc.v:146242$7042 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$7111 1'0 + assign $0\logical_op__invert_in$10[0:0]$7043 1'0 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7111 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7043 end - attribute \src "libresoc.v:145911.7-145911.41" - process $proc$libresoc.v:145911$7112 + attribute \src "libresoc.v:146251.7-146251.41" + process $proc$libresoc.v:146251$7044 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$7113 1'0 + assign $0\logical_op__invert_out$13[0:0]$7045 1'0 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7113 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7045 end - attribute \src "libresoc.v:145920.7-145920.39" - process $proc$libresoc.v:145920$7114 + attribute \src "libresoc.v:146260.7-146260.39" + process $proc$libresoc.v:146260$7046 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$7115 1'0 + assign $0\logical_op__is_32bit$16[0:0]$7047 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7115 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7047 end - attribute \src "libresoc.v:145929.7-145929.40" - process $proc$libresoc.v:145929$7116 + attribute \src "libresoc.v:146269.7-146269.40" + process $proc$libresoc.v:146269$7048 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$7117 1'0 + assign $0\logical_op__is_signed$17[0:0]$7049 1'0 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7117 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7049 end - attribute \src "libresoc.v:145940.7-145940.36" - process $proc$libresoc.v:145940$7118 + attribute \src "libresoc.v:146280.7-146280.36" + process $proc$libresoc.v:146280$7050 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$7119 1'0 + assign $0\logical_op__oe__oe$8[0:0]$7051 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7119 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7051 end - attribute \src "libresoc.v:145949.7-145949.36" - process $proc$libresoc.v:145949$7120 + attribute \src "libresoc.v:146289.7-146289.36" + process $proc$libresoc.v:146289$7052 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$7121 1'0 + assign $0\logical_op__oe__ok$9[0:0]$7053 1'0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7121 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7053 end - attribute \src "libresoc.v:145956.7-145956.43" - process $proc$libresoc.v:145956$7122 + attribute \src "libresoc.v:146296.7-146296.43" + process $proc$libresoc.v:146296$7054 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$7123 1'0 + assign $0\logical_op__output_carry$15[0:0]$7055 1'0 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7123 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7055 end - attribute \src "libresoc.v:145967.7-145967.36" - process $proc$libresoc.v:145967$7124 + attribute \src "libresoc.v:146307.7-146307.36" + process $proc$libresoc.v:146307$7056 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$7125 1'0 + assign $0\logical_op__rc__ok$7[0:0]$7057 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7125 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7057 end - attribute \src "libresoc.v:145976.7-145976.36" - process $proc$libresoc.v:145976$7126 + attribute \src "libresoc.v:146316.7-146316.36" + process $proc$libresoc.v:146316$7058 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$7127 1'0 + assign $0\logical_op__rc__rc$6[0:0]$7059 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7127 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7059 end - attribute \src "libresoc.v:145983.7-145983.40" - process $proc$libresoc.v:145983$7128 + attribute \src "libresoc.v:146323.7-146323.40" + process $proc$libresoc.v:146323$7060 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$7129 1'0 + assign $0\logical_op__write_cr0$14[0:0]$7061 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7129 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7061 end - attribute \src "libresoc.v:145992.7-145992.37" - process $proc$libresoc.v:145992$7130 + attribute \src "libresoc.v:146332.7-146332.37" + process $proc$libresoc.v:146332$7062 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$7131 1'0 + assign $0\logical_op__zero_a$11[0:0]$7063 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7131 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7063 end - attribute \src "libresoc.v:146001.13-146001.29" - process $proc$libresoc.v:146001$7132 + attribute \src "libresoc.v:146341.13-146341.29" + process $proc$libresoc.v:146341$7064 assign { } { } - assign $0\muxid$1[1:0]$7133 2'00 + assign $0\muxid$1[1:0]$7065 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$7133 + update \muxid$1 $0\muxid$1[1:0]$7065 end - attribute \src "libresoc.v:146016.14-146016.43" - process $proc$libresoc.v:146016$7134 + attribute \src "libresoc.v:146356.14-146356.43" + process $proc$libresoc.v:146356$7066 assign { } { } - assign $0\o$20[63:0]$7135 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$20[63:0]$7067 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$20 $0\o$20[63:0]$7135 + update \o$20 $0\o$20[63:0]$7067 end - attribute \src "libresoc.v:146025.7-146025.23" - process $proc$libresoc.v:146025$7136 + attribute \src "libresoc.v:146365.7-146365.23" + process $proc$libresoc.v:146365$7068 assign { } { } - assign $0\o_ok$21[0:0]$7137 1'0 + assign $0\o_ok$21[0:0]$7069 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$7137 + update \o_ok$21 $0\o_ok$21[0:0]$7069 end - attribute \src "libresoc.v:146319.7-146319.20" - process $proc$libresoc.v:146319$7138 + attribute \src "libresoc.v:146659.7-146659.20" + process $proc$libresoc.v:146659$7070 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:146329.3-146330.33" - process $proc$libresoc.v:146329$6982 + attribute \src "libresoc.v:146669.3-146670.33" + process $proc$libresoc.v:146669$6914 assign { } { } - assign $0\cr_a$22[3:0]$6983 \cr_a$22$next + assign $0\cr_a$22[3:0]$6915 \cr_a$22$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$6983 + update \cr_a$22 $0\cr_a$22[3:0]$6915 end - attribute \src "libresoc.v:146331.3-146332.39" - process $proc$libresoc.v:146331$6984 + attribute \src "libresoc.v:146671.3-146672.39" + process $proc$libresoc.v:146671$6916 assign { } { } - assign $0\cr_a_ok$23[0:0]$6985 \cr_a_ok$23$next + assign $0\cr_a_ok$23[0:0]$6917 \cr_a_ok$23$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6985 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6917 end - attribute \src "libresoc.v:146333.3-146334.27" - process $proc$libresoc.v:146333$6986 + attribute \src "libresoc.v:146673.3-146674.27" + process $proc$libresoc.v:146673$6918 assign { } { } - assign $0\o$20[63:0]$6987 \o$20$next + assign $0\o$20[63:0]$6919 \o$20$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$6987 + update \o$20 $0\o$20[63:0]$6919 end - attribute \src "libresoc.v:146335.3-146336.33" - process $proc$libresoc.v:146335$6988 + attribute \src "libresoc.v:146675.3-146676.33" + process $proc$libresoc.v:146675$6920 assign { } { } - assign $0\o_ok$21[0:0]$6989 \o_ok$21$next + assign $0\o_ok$21[0:0]$6921 \o_ok$21$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$6989 + update \o_ok$21 $0\o_ok$21[0:0]$6921 end - attribute \src "libresoc.v:146337.3-146338.65" - process $proc$libresoc.v:146337$6990 + attribute \src "libresoc.v:146677.3-146678.65" + process $proc$libresoc.v:146677$6922 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$6991 \logical_op__insn_type$2$next + assign $0\logical_op__insn_type$2[6:0]$6923 \logical_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6991 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6923 end - attribute \src "libresoc.v:146339.3-146340.61" - process $proc$libresoc.v:146339$6992 + attribute \src "libresoc.v:146679.3-146680.61" + process $proc$libresoc.v:146679$6924 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$6993 \logical_op__fn_unit$3$next + assign $0\logical_op__fn_unit$3[13:0]$6925 \logical_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6993 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6925 end - attribute \src "libresoc.v:146341.3-146342.75" - process $proc$libresoc.v:146341$6994 + attribute \src "libresoc.v:146681.3-146682.75" + process $proc$libresoc.v:146681$6926 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$6995 \logical_op__imm_data__data$4$next + assign $0\logical_op__imm_data__data$4[63:0]$6927 \logical_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6995 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6927 end - attribute \src "libresoc.v:146343.3-146344.71" - process $proc$libresoc.v:146343$6996 + attribute \src "libresoc.v:146683.3-146684.71" + process $proc$libresoc.v:146683$6928 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$6997 \logical_op__imm_data__ok$5$next + assign $0\logical_op__imm_data__ok$5[0:0]$6929 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6997 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6929 end - attribute \src "libresoc.v:146345.3-146346.59" - process $proc$libresoc.v:146345$6998 + attribute \src "libresoc.v:146685.3-146686.59" + process $proc$libresoc.v:146685$6930 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$6999 \logical_op__rc__rc$6$next + assign $0\logical_op__rc__rc$6[0:0]$6931 \logical_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6999 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6931 end - attribute \src "libresoc.v:146347.3-146348.59" - process $proc$libresoc.v:146347$7000 + attribute \src "libresoc.v:146687.3-146688.59" + process $proc$libresoc.v:146687$6932 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$7001 \logical_op__rc__ok$7$next + assign $0\logical_op__rc__ok$7[0:0]$6933 \logical_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7001 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6933 end - attribute \src "libresoc.v:146349.3-146350.59" - process $proc$libresoc.v:146349$7002 + attribute \src "libresoc.v:146689.3-146690.59" + process $proc$libresoc.v:146689$6934 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$7003 \logical_op__oe__oe$8$next + assign $0\logical_op__oe__oe$8[0:0]$6935 \logical_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7003 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6935 end - attribute \src "libresoc.v:146351.3-146352.59" - process $proc$libresoc.v:146351$7004 + attribute \src "libresoc.v:146691.3-146692.59" + process $proc$libresoc.v:146691$6936 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$7005 \logical_op__oe__ok$9$next + assign $0\logical_op__oe__ok$9[0:0]$6937 \logical_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7005 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6937 end - attribute \src "libresoc.v:146353.3-146354.67" - process $proc$libresoc.v:146353$7006 + attribute \src "libresoc.v:146693.3-146694.67" + process $proc$libresoc.v:146693$6938 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$7007 \logical_op__invert_in$10$next + assign $0\logical_op__invert_in$10[0:0]$6939 \logical_op__invert_in$10$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7007 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6939 end - attribute \src "libresoc.v:146355.3-146356.61" - process $proc$libresoc.v:146355$7008 + attribute \src "libresoc.v:146695.3-146696.61" + process $proc$libresoc.v:146695$6940 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$7009 \logical_op__zero_a$11$next + assign $0\logical_op__zero_a$11[0:0]$6941 \logical_op__zero_a$11$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7009 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6941 end - attribute \src "libresoc.v:146357.3-146358.71" - process $proc$libresoc.v:146357$7010 + attribute \src "libresoc.v:146697.3-146698.71" + process $proc$libresoc.v:146697$6942 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$7011 \logical_op__input_carry$12$next + assign $0\logical_op__input_carry$12[1:0]$6943 \logical_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7011 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6943 end - attribute \src "libresoc.v:146359.3-146360.69" - process $proc$libresoc.v:146359$7012 + attribute \src "libresoc.v:146699.3-146700.69" + process $proc$libresoc.v:146699$6944 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$7013 \logical_op__invert_out$13$next + assign $0\logical_op__invert_out$13[0:0]$6945 \logical_op__invert_out$13$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7013 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6945 end - attribute \src "libresoc.v:146361.3-146362.67" - process $proc$libresoc.v:146361$7014 + attribute \src "libresoc.v:146701.3-146702.67" + process $proc$libresoc.v:146701$6946 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$7015 \logical_op__write_cr0$14$next + assign $0\logical_op__write_cr0$14[0:0]$6947 \logical_op__write_cr0$14$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7015 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6947 end - attribute \src "libresoc.v:146363.3-146364.73" - process $proc$libresoc.v:146363$7016 + attribute \src "libresoc.v:146703.3-146704.73" + process $proc$libresoc.v:146703$6948 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$7017 \logical_op__output_carry$15$next + assign $0\logical_op__output_carry$15[0:0]$6949 \logical_op__output_carry$15$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7017 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6949 end - attribute \src "libresoc.v:146365.3-146366.65" - process $proc$libresoc.v:146365$7018 + attribute \src "libresoc.v:146705.3-146706.65" + process $proc$libresoc.v:146705$6950 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$7019 \logical_op__is_32bit$16$next + assign $0\logical_op__is_32bit$16[0:0]$6951 \logical_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7019 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6951 end - attribute \src "libresoc.v:146367.3-146368.67" - process $proc$libresoc.v:146367$7020 + attribute \src "libresoc.v:146707.3-146708.67" + process $proc$libresoc.v:146707$6952 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$7021 \logical_op__is_signed$17$next + assign $0\logical_op__is_signed$17[0:0]$6953 \logical_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7021 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6953 end - attribute \src "libresoc.v:146369.3-146370.65" - process $proc$libresoc.v:146369$7022 + attribute \src "libresoc.v:146709.3-146710.65" + process $proc$libresoc.v:146709$6954 assign { } { } - assign $0\logical_op__data_len$18[3:0]$7023 \logical_op__data_len$18$next + assign $0\logical_op__data_len$18[3:0]$6955 \logical_op__data_len$18$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7023 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6955 end - attribute \src "libresoc.v:146371.3-146372.57" - process $proc$libresoc.v:146371$7024 + attribute \src "libresoc.v:146711.3-146712.57" + process $proc$libresoc.v:146711$6956 assign { } { } - assign $0\logical_op__insn$19[31:0]$7025 \logical_op__insn$19$next + assign $0\logical_op__insn$19[31:0]$6957 \logical_op__insn$19$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7025 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6957 end - attribute \src "libresoc.v:146373.3-146374.33" - process $proc$libresoc.v:146373$7026 + attribute \src "libresoc.v:146713.3-146714.33" + process $proc$libresoc.v:146713$6958 assign { } { } - assign $0\muxid$1[1:0]$7027 \muxid$1$next + assign $0\muxid$1[1:0]$6959 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7027 + update \muxid$1 $0\muxid$1[1:0]$6959 end - attribute \src "libresoc.v:146375.3-146376.29" - process $proc$libresoc.v:146375$7028 + attribute \src "libresoc.v:146715.3-146716.29" + process $proc$libresoc.v:146715$6960 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:146433.3-146450.6" - process $proc$libresoc.v:146433$7029 + attribute \src "libresoc.v:146773.3-146790.6" + process $proc$libresoc.v:146773$6961 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7030 $2\r_busy$next[0:0]$7032 - attribute \src "libresoc.v:146434.5-146434.29" + assign $0\r_busy$next[0:0]$6962 $2\r_busy$next[0:0]$6964 + attribute \src "libresoc.v:146774.5-146774.29" switch \initial - attribute \src "libresoc.v:146434.9-146434.17" + attribute \src "libresoc.v:146774.9-146774.17" case 1'1 case end @@ -238735,34 +238180,34 @@ module \logical_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$7031 1'1 + assign $1\r_busy$next[0:0]$6963 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$7031 1'0 + assign $1\r_busy$next[0:0]$6963 1'0 case - assign $1\r_busy$next[0:0]$7031 \r_busy + assign $1\r_busy$next[0:0]$6963 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$7032 1'0 + assign $2\r_busy$next[0:0]$6964 1'0 case - assign $2\r_busy$next[0:0]$7032 $1\r_busy$next[0:0]$7031 + assign $2\r_busy$next[0:0]$6964 $1\r_busy$next[0:0]$6963 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7030 + update \r_busy$next $0\r_busy$next[0:0]$6962 end - attribute \src "libresoc.v:146451.3-146463.6" - process $proc$libresoc.v:146451$7033 + attribute \src "libresoc.v:146791.3-146803.6" + process $proc$libresoc.v:146791$6965 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$7034 $1\muxid$1$next[1:0]$7035 - attribute \src "libresoc.v:146452.5-146452.29" + assign $0\muxid$1$next[1:0]$6966 $1\muxid$1$next[1:0]$6967 + attribute \src "libresoc.v:146792.5-146792.29" switch \initial - attribute \src "libresoc.v:146452.9-146452.17" + attribute \src "libresoc.v:146792.9-146792.17" case 1'1 case end @@ -238771,19 +238216,19 @@ module \logical_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$7035 \muxid$51 + assign $1\muxid$1$next[1:0]$6967 \muxid$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$7035 \muxid$51 + assign $1\muxid$1$next[1:0]$6967 \muxid$51 case - assign $1\muxid$1$next[1:0]$7035 \muxid$1 + assign $1\muxid$1$next[1:0]$6967 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7034 + update \muxid$1$next $0\muxid$1$next[1:0]$6966 end - attribute \src "libresoc.v:146464.3-146505.6" - process $proc$libresoc.v:146464$7036 + attribute \src "libresoc.v:146804.3-146845.6" + process $proc$libresoc.v:146804$6968 assign { } { } assign { } { } assign { } { } @@ -238820,33 +238265,33 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$7037 $1\logical_op__data_len$18$next[3:0]$7055 - assign $0\logical_op__fn_unit$3$next[13:0]$7038 $1\logical_op__fn_unit$3$next[13:0]$7056 + assign $0\logical_op__data_len$18$next[3:0]$6969 $1\logical_op__data_len$18$next[3:0]$6987 + assign $0\logical_op__fn_unit$3$next[13:0]$6970 $1\logical_op__fn_unit$3$next[13:0]$6988 assign { } { } assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$7041 $1\logical_op__input_carry$12$next[1:0]$7059 - assign $0\logical_op__insn$19$next[31:0]$7042 $1\logical_op__insn$19$next[31:0]$7060 - assign $0\logical_op__insn_type$2$next[6:0]$7043 $1\logical_op__insn_type$2$next[6:0]$7061 - assign $0\logical_op__invert_in$10$next[0:0]$7044 $1\logical_op__invert_in$10$next[0:0]$7062 - assign $0\logical_op__invert_out$13$next[0:0]$7045 $1\logical_op__invert_out$13$next[0:0]$7063 - assign $0\logical_op__is_32bit$16$next[0:0]$7046 $1\logical_op__is_32bit$16$next[0:0]$7064 - assign $0\logical_op__is_signed$17$next[0:0]$7047 $1\logical_op__is_signed$17$next[0:0]$7065 + assign $0\logical_op__input_carry$12$next[1:0]$6973 $1\logical_op__input_carry$12$next[1:0]$6991 + assign $0\logical_op__insn$19$next[31:0]$6974 $1\logical_op__insn$19$next[31:0]$6992 + assign $0\logical_op__insn_type$2$next[6:0]$6975 $1\logical_op__insn_type$2$next[6:0]$6993 + assign $0\logical_op__invert_in$10$next[0:0]$6976 $1\logical_op__invert_in$10$next[0:0]$6994 + assign $0\logical_op__invert_out$13$next[0:0]$6977 $1\logical_op__invert_out$13$next[0:0]$6995 + assign $0\logical_op__is_32bit$16$next[0:0]$6978 $1\logical_op__is_32bit$16$next[0:0]$6996 + assign $0\logical_op__is_signed$17$next[0:0]$6979 $1\logical_op__is_signed$17$next[0:0]$6997 assign { } { } assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$7050 $1\logical_op__output_carry$15$next[0:0]$7068 + assign $0\logical_op__output_carry$15$next[0:0]$6982 $1\logical_op__output_carry$15$next[0:0]$7000 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$7053 $1\logical_op__write_cr0$14$next[0:0]$7071 - assign $0\logical_op__zero_a$11$next[0:0]$7054 $1\logical_op__zero_a$11$next[0:0]$7072 - assign $0\logical_op__imm_data__data$4$next[63:0]$7039 $2\logical_op__imm_data__data$4$next[63:0]$7073 - assign $0\logical_op__imm_data__ok$5$next[0:0]$7040 $2\logical_op__imm_data__ok$5$next[0:0]$7074 - assign $0\logical_op__oe__oe$8$next[0:0]$7048 $2\logical_op__oe__oe$8$next[0:0]$7075 - assign $0\logical_op__oe__ok$9$next[0:0]$7049 $2\logical_op__oe__ok$9$next[0:0]$7076 - assign $0\logical_op__rc__ok$7$next[0:0]$7051 $2\logical_op__rc__ok$7$next[0:0]$7077 - assign $0\logical_op__rc__rc$6$next[0:0]$7052 $2\logical_op__rc__rc$6$next[0:0]$7078 - attribute \src "libresoc.v:146465.5-146465.29" + assign $0\logical_op__write_cr0$14$next[0:0]$6985 $1\logical_op__write_cr0$14$next[0:0]$7003 + assign $0\logical_op__zero_a$11$next[0:0]$6986 $1\logical_op__zero_a$11$next[0:0]$7004 + assign $0\logical_op__imm_data__data$4$next[63:0]$6971 $2\logical_op__imm_data__data$4$next[63:0]$7005 + assign $0\logical_op__imm_data__ok$5$next[0:0]$6972 $2\logical_op__imm_data__ok$5$next[0:0]$7006 + assign $0\logical_op__oe__oe$8$next[0:0]$6980 $2\logical_op__oe__oe$8$next[0:0]$7007 + assign $0\logical_op__oe__ok$9$next[0:0]$6981 $2\logical_op__oe__ok$9$next[0:0]$7008 + assign $0\logical_op__rc__ok$7$next[0:0]$6983 $2\logical_op__rc__ok$7$next[0:0]$7009 + assign $0\logical_op__rc__rc$6$next[0:0]$6984 $2\logical_op__rc__rc$6$next[0:0]$7010 + attribute \src "libresoc.v:146805.5-146805.29" switch \initial - attribute \src "libresoc.v:146465.9-146465.17" + attribute \src "libresoc.v:146805.9-146805.17" case 1'1 case end @@ -238872,7 +238317,7 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$7060 $1\logical_op__data_len$18$next[3:0]$7055 $1\logical_op__is_signed$17$next[0:0]$7065 $1\logical_op__is_32bit$16$next[0:0]$7064 $1\logical_op__output_carry$15$next[0:0]$7068 $1\logical_op__write_cr0$14$next[0:0]$7071 $1\logical_op__invert_out$13$next[0:0]$7063 $1\logical_op__input_carry$12$next[1:0]$7059 $1\logical_op__zero_a$11$next[0:0]$7072 $1\logical_op__invert_in$10$next[0:0]$7062 $1\logical_op__oe__ok$9$next[0:0]$7067 $1\logical_op__oe__oe$8$next[0:0]$7066 $1\logical_op__rc__ok$7$next[0:0]$7069 $1\logical_op__rc__rc$6$next[0:0]$7070 $1\logical_op__imm_data__ok$5$next[0:0]$7058 $1\logical_op__imm_data__data$4$next[63:0]$7057 $1\logical_op__fn_unit$3$next[13:0]$7056 $1\logical_op__insn_type$2$next[6:0]$7061 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + assign { $1\logical_op__insn$19$next[31:0]$6992 $1\logical_op__data_len$18$next[3:0]$6987 $1\logical_op__is_signed$17$next[0:0]$6997 $1\logical_op__is_32bit$16$next[0:0]$6996 $1\logical_op__output_carry$15$next[0:0]$7000 $1\logical_op__write_cr0$14$next[0:0]$7003 $1\logical_op__invert_out$13$next[0:0]$6995 $1\logical_op__input_carry$12$next[1:0]$6991 $1\logical_op__zero_a$11$next[0:0]$7004 $1\logical_op__invert_in$10$next[0:0]$6994 $1\logical_op__oe__ok$9$next[0:0]$6999 $1\logical_op__oe__oe$8$next[0:0]$6998 $1\logical_op__rc__ok$7$next[0:0]$7001 $1\logical_op__rc__rc$6$next[0:0]$7002 $1\logical_op__imm_data__ok$5$next[0:0]$6990 $1\logical_op__imm_data__data$4$next[63:0]$6989 $1\logical_op__fn_unit$3$next[13:0]$6988 $1\logical_op__insn_type$2$next[6:0]$6993 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -238893,26 +238338,26 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$7060 $1\logical_op__data_len$18$next[3:0]$7055 $1\logical_op__is_signed$17$next[0:0]$7065 $1\logical_op__is_32bit$16$next[0:0]$7064 $1\logical_op__output_carry$15$next[0:0]$7068 $1\logical_op__write_cr0$14$next[0:0]$7071 $1\logical_op__invert_out$13$next[0:0]$7063 $1\logical_op__input_carry$12$next[1:0]$7059 $1\logical_op__zero_a$11$next[0:0]$7072 $1\logical_op__invert_in$10$next[0:0]$7062 $1\logical_op__oe__ok$9$next[0:0]$7067 $1\logical_op__oe__oe$8$next[0:0]$7066 $1\logical_op__rc__ok$7$next[0:0]$7069 $1\logical_op__rc__rc$6$next[0:0]$7070 $1\logical_op__imm_data__ok$5$next[0:0]$7058 $1\logical_op__imm_data__data$4$next[63:0]$7057 $1\logical_op__fn_unit$3$next[13:0]$7056 $1\logical_op__insn_type$2$next[6:0]$7061 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + assign { $1\logical_op__insn$19$next[31:0]$6992 $1\logical_op__data_len$18$next[3:0]$6987 $1\logical_op__is_signed$17$next[0:0]$6997 $1\logical_op__is_32bit$16$next[0:0]$6996 $1\logical_op__output_carry$15$next[0:0]$7000 $1\logical_op__write_cr0$14$next[0:0]$7003 $1\logical_op__invert_out$13$next[0:0]$6995 $1\logical_op__input_carry$12$next[1:0]$6991 $1\logical_op__zero_a$11$next[0:0]$7004 $1\logical_op__invert_in$10$next[0:0]$6994 $1\logical_op__oe__ok$9$next[0:0]$6999 $1\logical_op__oe__oe$8$next[0:0]$6998 $1\logical_op__rc__ok$7$next[0:0]$7001 $1\logical_op__rc__rc$6$next[0:0]$7002 $1\logical_op__imm_data__ok$5$next[0:0]$6990 $1\logical_op__imm_data__data$4$next[63:0]$6989 $1\logical_op__fn_unit$3$next[13:0]$6988 $1\logical_op__insn_type$2$next[6:0]$6993 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } case - assign $1\logical_op__data_len$18$next[3:0]$7055 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[13:0]$7056 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$7057 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$7058 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$7059 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$7060 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$7061 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$7062 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$7063 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$7064 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$7065 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$7066 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$7067 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$7068 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$7069 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$7070 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$7071 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$7072 \logical_op__zero_a$11 + assign $1\logical_op__data_len$18$next[3:0]$6987 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[13:0]$6988 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$6989 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$6990 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$6991 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$6992 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$6993 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$6994 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$6995 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$6996 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$6997 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$6998 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$6999 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$7000 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$7001 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$7002 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$7003 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$7004 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -238924,52 +238369,52 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$7073 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$7074 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$7078 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$7077 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$7075 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$7076 1'0 + assign $2\logical_op__imm_data__data$4$next[63:0]$7005 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7006 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$7010 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$7009 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$7007 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$7008 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$7073 $1\logical_op__imm_data__data$4$next[63:0]$7057 - assign $2\logical_op__imm_data__ok$5$next[0:0]$7074 $1\logical_op__imm_data__ok$5$next[0:0]$7058 - assign $2\logical_op__oe__oe$8$next[0:0]$7075 $1\logical_op__oe__oe$8$next[0:0]$7066 - assign $2\logical_op__oe__ok$9$next[0:0]$7076 $1\logical_op__oe__ok$9$next[0:0]$7067 - assign $2\logical_op__rc__ok$7$next[0:0]$7077 $1\logical_op__rc__ok$7$next[0:0]$7069 - assign $2\logical_op__rc__rc$6$next[0:0]$7078 $1\logical_op__rc__rc$6$next[0:0]$7070 + assign $2\logical_op__imm_data__data$4$next[63:0]$7005 $1\logical_op__imm_data__data$4$next[63:0]$6989 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7006 $1\logical_op__imm_data__ok$5$next[0:0]$6990 + assign $2\logical_op__oe__oe$8$next[0:0]$7007 $1\logical_op__oe__oe$8$next[0:0]$6998 + assign $2\logical_op__oe__ok$9$next[0:0]$7008 $1\logical_op__oe__ok$9$next[0:0]$6999 + assign $2\logical_op__rc__ok$7$next[0:0]$7009 $1\logical_op__rc__ok$7$next[0:0]$7001 + assign $2\logical_op__rc__rc$6$next[0:0]$7010 $1\logical_op__rc__rc$6$next[0:0]$7002 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$7037 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$7038 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$7039 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$7040 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$7041 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$7042 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$7043 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$7044 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$7045 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$7046 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$7047 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7048 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7049 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7050 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7051 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7052 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7053 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7054 + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6969 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$6970 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6971 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6972 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6973 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6974 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6975 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6976 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6977 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6978 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6979 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$6980 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$6981 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$6982 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$6983 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$6984 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$6985 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$6986 end - attribute \src "libresoc.v:146506.3-146524.6" - process $proc$libresoc.v:146506$7079 + attribute \src "libresoc.v:146846.3-146864.6" + process $proc$libresoc.v:146846$7011 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$20$next[63:0]$7080 $1\o$20$next[63:0]$7082 + assign $0\o$20$next[63:0]$7012 $1\o$20$next[63:0]$7014 assign { } { } - assign $0\o_ok$21$next[0:0]$7081 $2\o_ok$21$next[0:0]$7084 - attribute \src "libresoc.v:146507.5-146507.29" + assign $0\o_ok$21$next[0:0]$7013 $2\o_ok$21$next[0:0]$7016 + attribute \src "libresoc.v:146847.5-146847.29" switch \initial - attribute \src "libresoc.v:146507.9-146507.17" + attribute \src "libresoc.v:146847.9-146847.17" case 1'1 case end @@ -238979,41 +238424,41 @@ module \logical_pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$7083 $1\o$20$next[63:0]$7082 } { \o_ok$71 \o$70 } + assign { $1\o_ok$21$next[0:0]$7015 $1\o$20$next[63:0]$7014 } { \o_ok$71 \o$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$7083 $1\o$20$next[63:0]$7082 } { \o_ok$71 \o$70 } + assign { $1\o_ok$21$next[0:0]$7015 $1\o$20$next[63:0]$7014 } { \o_ok$71 \o$70 } case - assign $1\o$20$next[63:0]$7082 \o$20 - assign $1\o_ok$21$next[0:0]$7083 \o_ok$21 + assign $1\o$20$next[63:0]$7014 \o$20 + assign $1\o_ok$21$next[0:0]$7015 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$7084 1'0 + assign $2\o_ok$21$next[0:0]$7016 1'0 case - assign $2\o_ok$21$next[0:0]$7084 $1\o_ok$21$next[0:0]$7083 + assign $2\o_ok$21$next[0:0]$7016 $1\o_ok$21$next[0:0]$7015 end sync always - update \o$20$next $0\o$20$next[63:0]$7080 - update \o_ok$21$next $0\o_ok$21$next[0:0]$7081 + update \o$20$next $0\o$20$next[63:0]$7012 + update \o_ok$21$next $0\o_ok$21$next[0:0]$7013 end - attribute \src "libresoc.v:146525.3-146543.6" - process $proc$libresoc.v:146525$7085 + attribute \src "libresoc.v:146865.3-146883.6" + process $proc$libresoc.v:146865$7017 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$22$next[3:0]$7086 $1\cr_a$22$next[3:0]$7088 + assign $0\cr_a$22$next[3:0]$7018 $1\cr_a$22$next[3:0]$7020 assign { } { } - assign $0\cr_a_ok$23$next[0:0]$7087 $2\cr_a_ok$23$next[0:0]$7090 - attribute \src "libresoc.v:146526.5-146526.29" + assign $0\cr_a_ok$23$next[0:0]$7019 $2\cr_a_ok$23$next[0:0]$7022 + attribute \src "libresoc.v:146866.5-146866.29" switch \initial - attribute \src "libresoc.v:146526.9-146526.17" + attribute \src "libresoc.v:146866.9-146866.17" case 1'1 case end @@ -239023,30 +238468,30 @@ module \logical_pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$7089 $1\cr_a$22$next[3:0]$7088 } { \cr_a_ok$73 \cr_a$72 } + assign { $1\cr_a_ok$23$next[0:0]$7021 $1\cr_a$22$next[3:0]$7020 } { \cr_a_ok$73 \cr_a$72 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$7089 $1\cr_a$22$next[3:0]$7088 } { \cr_a_ok$73 \cr_a$72 } + assign { $1\cr_a_ok$23$next[0:0]$7021 $1\cr_a$22$next[3:0]$7020 } { \cr_a_ok$73 \cr_a$72 } case - assign $1\cr_a$22$next[3:0]$7088 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$7089 \cr_a_ok$23 + assign $1\cr_a$22$next[3:0]$7020 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$7021 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$7090 1'0 + assign $2\cr_a_ok$23$next[0:0]$7022 1'0 case - assign $2\cr_a_ok$23$next[0:0]$7090 $1\cr_a_ok$23$next[0:0]$7089 + assign $2\cr_a_ok$23$next[0:0]$7022 $1\cr_a_ok$23$next[0:0]$7021 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$7086 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7087 + update \cr_a$22$next $0\cr_a$22$next[3:0]$7018 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7019 end - connect \$49 $and$libresoc.v:146328$6981_Y + connect \$49 $and$libresoc.v:146668$6913_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } @@ -239062,51940 +238507,23412 @@ module \logical_pipe2 connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_muxid \muxid end -attribute \src "ls180.v:4.1-11017.10" +attribute \src "ls180.v:4.1-5951.10" attribute \cells_not_processed 1 -module \ls180 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 - attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 - attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 - attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 - attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 - attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 - attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 - attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 - attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 - attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 - attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 - attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 - attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 - attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 - attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 - attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 - attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 - attribute \src "ls180.v:10465.1-10483.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 - attribute \src "ls180.v:10493.1-10497.4" - wire width 3 $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 - attribute \src "ls180.v:10493.1-10497.4" - wire width 25 $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 - attribute \src "ls180.v:10493.1-10497.4" - wire width 25 $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 - attribute \src "ls180.v:10507.1-10511.4" - wire width 3 $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 - attribute \src "ls180.v:10507.1-10511.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 - attribute \src "ls180.v:10507.1-10511.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 - attribute \src "ls180.v:10521.1-10525.4" - wire width 3 $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 - attribute \src "ls180.v:10521.1-10525.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 - attribute \src "ls180.v:10521.1-10525.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 - attribute \src "ls180.v:10535.1-10539.4" - wire width 3 $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 - attribute \src "ls180.v:10535.1-10539.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 - attribute \src "ls180.v:10535.1-10539.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 - attribute \src "ls180.v:10550.1-10554.4" - wire width 4 $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 - attribute \src "ls180.v:10550.1-10554.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 - attribute \src "ls180.v:10550.1-10554.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 - attribute \src "ls180.v:10567.1-10571.4" - wire width 4 $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 - attribute \src "ls180.v:10567.1-10571.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 - attribute \src "ls180.v:10567.1-10571.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 - attribute \src "ls180.v:10583.1-10587.4" - wire width 5 $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 - attribute \src "ls180.v:10583.1-10587.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 - attribute \src "ls180.v:10583.1-10587.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 - attribute \src "ls180.v:10597.1-10601.4" - wire width 5 $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 - attribute \src "ls180.v:10597.1-10601.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 - attribute \src "ls180.v:10597.1-10601.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 - attribute \src "ls180.v:3402.1-3495.4" - wire width 3 $0\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:3559.1-3652.4" - wire width 3 $0\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:3716.1-3809.4" - wire width 3 $0\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:3873.1-3966.4" - wire width 3 $0\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:6791.1-6807.4" - wire $0\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:7012.1-7028.4" - wire $0\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:7029.1-7045.4" - wire $0\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:7097.1-7104.4" - wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:7105.1-7112.4" - wire $0\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:7113.1-7120.4" - wire $0\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:7121.1-7128.4" - wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:7129.1-7136.4" - wire $0\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:7137.1-7144.4" - wire $0\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:7145.1-7152.4" - wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:7153.1-7160.4" - wire $0\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:6808.1-6824.4" - wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7161.1-7168.4" - wire $0\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:7169.1-7176.4" - wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:7177.1-7184.4" - wire $0\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:7185.1-7192.4" - wire $0\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:7193.1-7212.4" - wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:7213.1-7232.4" - wire width 64 $0\builder_comb_rhs_array_muxed25[63:0] - attribute \src "ls180.v:7233.1-7252.4" - wire width 8 $0\builder_comb_rhs_array_muxed26[7:0] - attribute \src "ls180.v:7253.1-7272.4" - wire $0\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:7273.1-7292.4" - wire $0\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:7293.1-7312.4" - wire $0\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:6825.1-6841.4" - wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:7313.1-7332.4" - wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:7333.1-7352.4" - wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:6842.1-6858.4" - wire $0\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:6859.1-6875.4" - wire $0\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:6876.1-6892.4" - wire $0\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:6944.1-6960.4" - wire $0\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:6961.1-6977.4" - wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:6978.1-6994.4" - wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:6995.1-7011.4" - wire $0\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:6893.1-6909.4" - wire $0\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:6910.1-6926.4" - wire $0\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:6927.1-6943.4" - wire $0\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:7046.1-7062.4" - wire $0\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:7063.1-7079.4" - wire $0\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:7080.1-7096.4" - wire $0\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\builder_converter0_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_converter0_state[0:0] - attribute \src "ls180.v:2966.1-3012.4" - wire $0\builder_converter1_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_converter1_state[0:0] - attribute \src "ls180.v:3026.1-3072.4" - wire $0\builder_converter2_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_converter2_state[0:0] - attribute \src "ls180.v:4219.1-4265.4" - wire $0\builder_converter_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_converter_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 20 $0\builder_count[19:0] - attribute \src "ls180.v:6031.1-6042.4" - wire $0\builder_error[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\builder_grant[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 14 $0\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:5848.1-5884.4" - wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:5848.1-5884.4" - wire $0\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1993.5-1993.55" - wire $0\builder_libresocsim_converted_interface_ack[0:0] - attribute \src "ls180.v:1989.12-1989.65" - wire width 64 $0\builder_libresocsim_converted_interface_dat_r[63:0] - attribute \src "ls180.v:1997.5-1997.55" - wire $0\builder_libresocsim_converted_interface_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:5848.1-5884.4" - wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:5848.1-5884.4" - wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_libresocsim_we[0:0] - attribute \src "ls180.v:5848.1-5884.4" - wire $0\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:5848.1-5884.4" - wire $0\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:5848.1-5884.4" - wire $0\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1979.12-1979.52" - wire width 30 $0\builder_libresocsim_wishbone_adr[29:0] - attribute \src "ls180.v:1983.5-1983.44" - wire $0\builder_libresocsim_wishbone_cyc[0:0] - attribute \src "ls180.v:5848.1-5884.4" - wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1980.12-1980.54" - wire width 32 $0\builder_libresocsim_wishbone_dat_w[31:0] - attribute \src "ls180.v:1982.11-1982.50" - wire width 4 $0\builder_libresocsim_wishbone_sel[3:0] - attribute \src "ls180.v:1984.5-1984.44" - wire $0\builder_libresocsim_wishbone_stb[0:0] - attribute \src "ls180.v:1986.5-1986.43" - wire $0\builder_libresocsim_wishbone_we[0:0] - attribute \src "ls180.v:1878.5-1878.27" - wire $0\builder_locked0[0:0] - attribute \src "ls180.v:1879.5-1879.27" - wire $0\builder_locked1[0:0] - attribute \src "ls180.v:1880.5-1880.27" - wire $0\builder_locked2[0:0] - attribute \src "ls180.v:1881.5-1881.27" - wire $0\builder_locked3[0:0] - attribute \src "ls180.v:4091.1-4163.4" - wire width 3 $0\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\builder_multiplexer_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:5848.1-5884.4" - wire width 2 $0\builder_next_state[1:0] - attribute \src "ls180.v:3308.1-3338.4" - wire width 2 $0\builder_refresher_next_state[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\builder_refresher_state[1:0] - attribute \src "ls180.v:5646.1-5685.4" - wire width 2 $0\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:5213.1-5292.4" - wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire width 3 $0\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:5705.1-5742.4" - wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:5743.1-5779.4" - wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:4888.1-4960.4" - wire width 3 $0\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:4733.1-4826.4" - wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:4623.1-4699.4" - wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:4860.1-4887.4" - wire $0\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:4994.1-5095.4" - wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:4589.1-4622.4" - wire $0\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:6031.1-6042.4" - wire $0\builder_shared_ack[0:0] - attribute \src "ls180.v:6031.1-6042.4" - wire width 32 $0\builder_shared_dat_r[31:0] - attribute \src "ls180.v:5909.1-5924.4" - wire width 13 $0\builder_slave_sel[12:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 13 $0\builder_slave_sel_r[12:0] - attribute \src "ls180.v:4420.1-4468.4" - wire width 2 $0\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\builder_spimaster0_state[1:0] - attribute \src "ls180.v:4479.1-4527.4" - wire width 2 $0\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\builder_spimaster1_state[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\builder_state[1:0] - attribute \src "ls180.v:7472.1-7500.4" - wire $0\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:7501.1-7529.4" - wire $0\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:7353.1-7369.4" - wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:7370.1-7386.4" - wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7387.1-7403.4" - wire $0\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:7404.1-7420.4" - wire $0\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:7421.1-7437.4" - wire $0\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:7438.1-7454.4" - wire $0\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:7455.1-7471.4" - wire $0\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:4399.1-4403.4" - wire width 16 $0\gpio_o[15:0] - attribute \src "ls180.v:4404.1-4408.4" - wire width 16 $0\gpio_oe[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_cmd_consumed[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_converter0_counter[0:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\main_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\main_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 64 $0\main_converter0_dat_r[63:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\main_converter0_skip[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_converter1_counter[0:0] - attribute \src "ls180.v:2966.1-3012.4" - wire $0\main_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:2966.1-3012.4" - wire $0\main_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 64 $0\main_converter1_dat_r[63:0] - attribute \src "ls180.v:2966.1-3012.4" - wire $0\main_converter1_skip[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_converter_counter[0:0] - attribute \src "ls180.v:4219.1-4265.4" - wire $0\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:4219.1-4265.4" - wire $0\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_converter_dat_r[31:0] - attribute \src "ls180.v:4219.1-4265.4" - wire $0\main_converter_skip[0:0] - attribute \src "ls180.v:7633.1-7703.4" - wire width 16 $0\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 24 $0\main_dummy[23:0] - attribute \src "ls180.v:1085.12-1085.53" - wire width 16 $0\main_gpiotristateasic0_oe_storage[15:0] - attribute \src "ls180.v:1087.12-1087.54" - wire width 16 $0\main_gpiotristateasic0_out_storage[15:0] - attribute \src "ls180.v:7587.1-7597.4" - wire width 16 $0\main_gpiotristateasic0_status[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_gpiotristateasic1_oe_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_gpiotristateasic1_oe_storage[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_gpiotristateasic1_out_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_gpiotristateasic1_out_storage[15:0] - attribute \src "ls180.v:7598.1-7608.4" - wire width 16 $0\main_gpiotristateasic1_status[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_i2c_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_i2c_storage[2:0] - attribute \src "ls180.v:7629.1-7631.4" - wire $0\main_int_rst[0:0] - attribute \src "ls180.v:1666.11-1666.41" - wire width 2 $0\main_interface0_bus_bte[1:0] - attribute \src "ls180.v:1665.11-1665.41" - wire width 3 $0\main_interface0_bus_cti[2:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\main_interface0_converted_interface_ack[0:0] - attribute \src "ls180.v:319.5-319.51" - wire $0\main_interface0_converted_interface_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_interface0_ram_bus_ack[0:0] - attribute \src "ls180.v:259.5-259.39" - wire $0\main_interface0_ram_bus_err[0:0] - attribute \src "ls180.v:5705.1-5742.4" - wire width 32 $0\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1757.11-1757.41" - wire width 2 $0\main_interface1_bus_bte[1:0] - attribute \src "ls180.v:1756.11-1756.41" - wire width 3 $0\main_interface1_bus_cti[2:0] - attribute \src "ls180.v:5705.1-5742.4" - wire $0\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1749.12-1749.45" - wire width 64 $0\main_interface1_bus_dat_w[63:0] - attribute \src "ls180.v:5705.1-5742.4" - wire width 8 $0\main_interface1_bus_sel[7:0] - attribute \src "ls180.v:5705.1-5742.4" - wire $0\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:5705.1-5742.4" - wire $0\main_interface1_bus_we[0:0] - attribute \src "ls180.v:2966.1-3012.4" - wire $0\main_interface1_converted_interface_ack[0:0] - attribute \src "ls180.v:334.5-334.51" - wire $0\main_interface1_converted_interface_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_interface1_ram_bus_ack[0:0] - attribute \src "ls180.v:274.5-274.39" - wire $0\main_interface1_ram_bus_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_interface2_ram_bus_ack[0:0] - attribute \src "ls180.v:289.5-289.39" - wire $0\main_interface2_ram_bus_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_interface3_ram_bus_ack[0:0] - attribute \src "ls180.v:304.5-304.39" - wire $0\main_interface3_ram_bus_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:171.12-171.74" - wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - attribute \src "ls180.v:175.5-175.69" - wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - attribute \src "ls180.v:201.5-201.72" - wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - attribute \src "ls180.v:204.11-204.79" - wire width 4 $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - attribute \src "ls180.v:189.12-189.78" - wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] - attribute \src "ls180.v:75.11-75.52" - wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] - attribute \src "ls180.v:74.11-74.52" - wire width 3 $0\main_libresocsim_libresoc_dbus_cti[2:0] - attribute \src "ls180.v:86.11-86.52" - wire width 2 $0\main_libresocsim_libresoc_ibus_bte[1:0] - attribute \src "ls180.v:85.11-85.52" - wire width 3 $0\main_libresocsim_libresoc_ibus_cti[2:0] - attribute \src "ls180.v:2887.1-2892.4" - wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:115.11-115.55" - wire width 2 $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] - attribute \src "ls180.v:114.11-114.55" - wire width 3 $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] - attribute \src "ls180.v:2906.1-2952.4" - wire width 30 $0\main_libresocsim_libresoc_xics_icp_adr[29:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] - attribute \src "ls180.v:2894.1-2904.4" - wire width 32 $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] - attribute \src "ls180.v:2906.1-2952.4" - wire width 4 $0\main_libresocsim_libresoc_xics_icp_sel[3:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\main_libresocsim_libresoc_xics_icp_stb[0:0] - attribute \src "ls180.v:2906.1-2952.4" - wire $0\main_libresocsim_libresoc_xics_icp_we[0:0] - attribute \src "ls180.v:2966.1-3012.4" - wire width 30 $0\main_libresocsim_libresoc_xics_ics_adr[29:0] - attribute \src "ls180.v:2966.1-3012.4" - wire $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] - attribute \src "ls180.v:2954.1-2964.4" - wire width 32 $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] - attribute \src "ls180.v:2966.1-3012.4" - wire width 4 $0\main_libresocsim_libresoc_xics_ics_sel[3:0] - attribute \src "ls180.v:2966.1-3012.4" - wire $0\main_libresocsim_libresoc_xics_ics_stb[0:0] - attribute \src "ls180.v:2966.1-3012.4" - wire $0\main_libresocsim_libresoc_xics_ics_we[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:217.5-217.40" - wire $0\main_libresocsim_ram_bus_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_libresocsim_value[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:3075.1-3085.4" - wire width 8 $0\main_libresocsim_we[7:0] - attribute \src "ls180.v:3091.1-3096.4" - wire $0\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:4219.1-4265.4" - wire width 30 $0\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:4219.1-4265.4" - wire $0\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:4207.1-4217.4" - wire width 16 $0\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:4219.1-4265.4" - wire width 2 $0\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:4219.1-4265.4" - wire $0\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:4219.1-4265.4" - wire $0\main_litedram_wb_we[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_pwm0_counter[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_pwm0_period_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_pwm0_width_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_pwm1_counter[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_pwm1_period_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_pwm1_width_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_rddata_en[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdblock2mem_converter_demux[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 64 $0\main_sdblock2mem_converter_source_payload_data[63:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 6 $0\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1690.5-1690.41" - wire $0\main_sdblock2mem_fifo_replace[0:0] - attribute \src "ls180.v:5613.1-5620.4" - wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:5646.1-5685.4" - wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:5646.1-5685.4" - wire width 64 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] - attribute \src "ls180.v:5646.1-5685.4" - wire $0\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:5646.1-5685.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:5646.1-5685.4" - wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:5646.1-5685.4" - wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:5646.1-5685.4" - wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 10 $0\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:5395.1-5585.4" - wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 128 $0\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:5395.1-5585.4" - wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1499.5-1499.34" - wire $0\main_sdcore_cmd_send_w[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:5301.1-5308.4" - wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:5357.1-5364.4" - wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:5311.1-5318.4" - wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:5367.1-5374.4" - wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:5321.1-5328.4" - wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:5377.1-5384.4" - wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:5331.1-5338.4" - wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:5387.1-5394.4" - wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:5346.1-5353.4" - wire $0\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1605.5-1605.50" - wire $0\main_sdcore_crc16_checker_source_first[0:0] - attribute \src "ls180.v:5340.1-5345.4" - wire $0\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:5293.1-5298.4" - wire $0\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:5213.1-5292.4" - wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:5213.1-5292.4" - wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:5175.1-5182.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:5185.1-5192.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:5195.1-5202.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:5205.1-5212.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:5213.1-5292.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:5213.1-5292.4" - wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:5213.1-5292.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:5213.1-5292.4" - wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:5213.1-5292.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:5213.1-5292.4" - wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:5213.1-5292.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:5213.1-5292.4" - wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:5213.1-5292.4" - wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1562.5-1562.51" - wire $0\main_sdcore_crc16_inserter_source_first[0:0] - attribute \src "ls180.v:5213.1-5292.4" - wire $0\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:5213.1-5292.4" - wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:5213.1-5292.4" - wire $0\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:5153.1-5160.4" - wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_sdcore_data_count[31:0] - attribute \src "ls180.v:5395.1-5585.4" - wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdcore_data_done[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdcore_data_error[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdmem2block_converter_mux[2:0] - attribute \src "ls180.v:5791.1-5819.4" - wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 64 $0\main_sdmem2block_dma_data[63:0] - attribute \src "ls180.v:5705.1-5742.4" - wire width 64 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - attribute \src "ls180.v:5705.1-5742.4" - wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:5743.1-5779.4" - wire $0\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:5743.1-5779.4" - wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:5743.1-5779.4" - wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:5743.1-5779.4" - wire $0\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:5743.1-5779.4" - wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:5705.1-5742.4" - wire $0\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:5743.1-5779.4" - wire $0\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1770.5-1770.45" - wire $0\main_sdmem2block_dma_source_first[0:0] - attribute \src "ls180.v:5705.1-5742.4" - wire $0\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:5705.1-5742.4" - wire width 64 $0\main_sdmem2block_dma_source_payload_data[63:0] - attribute \src "ls180.v:5705.1-5742.4" - wire $0\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 5 $0\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 6 $0\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 5 $0\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1826.5-1826.41" - wire $0\main_sdmem2block_fifo_replace[0:0] - attribute \src "ls180.v:5833.1-5840.4" - wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:4559.1-4587.4" - wire $0\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 9 $0\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 9 $0\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1291.5-1291.53" - wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - attribute \src "ls180.v:1292.5-1292.52" - wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1272.5-1272.46" - wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:4733.1-4826.4" - wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:4733.1-4826.4" - wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:4733.1-4826.4" - wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:4733.1-4826.4" - wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:4733.1-4826.4" - wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1245.5-1245.49" - wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1246.5-1246.48" - wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1247.5-1247.55" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1249.5-1249.57" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1250.5-1250.58" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1252.11-1252.64" - wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1253.5-1253.59" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4733.1-4826.4" - wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4733.1-4826.4" - wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4733.1-4826.4" - wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1258.11-1258.57" - wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1259.5-1259.52" - wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:4733.1-4826.4" - wire $0\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:4733.1-4826.4" - wire $0\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:4733.1-4826.4" - wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:4733.1-4826.4" - wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:4733.1-4826.4" - wire $0\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:4733.1-4826.4" - wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:4733.1-4826.4" - wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:4623.1-4699.4" - wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:4623.1-4699.4" - wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:4623.1-4699.4" - wire $0\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:4623.1-4699.4" - wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4623.1-4699.4" - wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4623.1-4699.4" - wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1235.11-1235.57" - wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1236.5-1236.52" - wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:4623.1-4699.4" - wire $0\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 10 $0\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:4994.1-5095.4" - wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:4994.1-5095.4" - wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1447.5-1447.55" - wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] - attribute \src "ls180.v:1448.5-1448.54" - wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1428.5-1428.48" - wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:4994.1-5095.4" - wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:4994.1-5095.4" - wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:4994.1-5095.4" - wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1399.5-1399.50" - wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1400.5-1400.49" - wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1401.5-1401.56" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1403.5-1403.58" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1404.5-1404.59" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1406.11-1406.65" - wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1407.5-1407.60" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4994.1-5095.4" - wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1410.5-1410.51" - wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1411.5-1411.52" - wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1412.11-1412.58" - wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1413.5-1413.53" - wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:4994.1-5095.4" - wire $0\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1420.5-1420.41" - wire $0\main_sdphy_datar_source_first[0:0] - attribute \src "ls180.v:4994.1-5095.4" - wire $0\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:4994.1-5095.4" - wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:4994.1-5095.4" - wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:4994.1-5095.4" - wire $0\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:4994.1-5095.4" - wire $0\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:4994.1-5095.4" - wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:4994.1-5095.4" - wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:4888.1-4960.4" - wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:4888.1-4960.4" - wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1369.5-1369.54" - wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - attribute \src "ls180.v:1370.5-1370.53" - wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1350.5-1350.47" - wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:4860.1-4887.4" - wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:4860.1-4887.4" - wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:4860.1-4887.4" - wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:4860.1-4887.4" - wire $0\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1337.5-1337.50" - wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1338.5-1338.49" - wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1339.5-1339.56" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1340.5-1340.58" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - attribute \src "ls180.v:1341.5-1341.58" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1342.5-1342.59" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1343.11-1343.65" - wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - attribute \src "ls180.v:1344.11-1344.65" - wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1345.5-1345.60" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:1335.5-1335.50" - wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - attribute \src "ls180.v:4888.1-4960.4" - wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1324.5-1324.51" - wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1325.5-1325.52" - wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4888.1-4960.4" - wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4888.1-4960.4" - wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:4888.1-4960.4" - wire $0\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:5395.1-5585.4" - wire $0\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:4888.1-4960.4" - wire $0\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:4888.1-4960.4" - wire $0\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:4860.1-4887.4" - wire $0\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_sdphy_init_count[7:0] - attribute \src "ls180.v:4589.1-4622.4" - wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:4589.1-4622.4" - wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1217.5-1217.40" - wire $0\main_sdphy_init_initialize_w[0:0] - attribute \src "ls180.v:4589.1-4622.4" - wire $0\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4589.1-4622.4" - wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4589.1-4622.4" - wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4589.1-4622.4" - wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4589.1-4622.4" - wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:7633.1-7703.4" - wire $0\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:7633.1-7703.4" - wire width 4 $0\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_address_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 13 $0\main_sdram_address_storage[12:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:3364.1-3371.4" - wire $0\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:539.5-539.64" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:522.5-522.67" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:523.5-523.66" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3386.1-3393.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3353.1-3360.4" - wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:3402.1-3495.4" - wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:3402.1-3495.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3402.1-3495.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3402.1-3495.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3402.1-3495.4" - wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:3402.1-3495.4" - wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:4051.1-4059.4" - wire $0\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:3402.1-3495.4" - wire $0\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:3402.1-3495.4" - wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:3402.1-3495.4" - wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:3402.1-3495.4" - wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 13 $0\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:3402.1-3495.4" - wire $0\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:3402.1-3495.4" - wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3402.1-3495.4" - wire $0\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:581.32-581.76" - wire $0\main_sdram_bankmachine0_trascon_ready[0:0] - attribute \src "ls180.v:579.32-579.75" - wire $0\main_sdram_bankmachine0_trccon_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:3521.1-3528.4" - wire $0\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:621.5-621.64" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:604.5-604.67" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:605.5-605.66" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3543.1-3550.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3510.1-3517.4" - wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:3559.1-3652.4" - wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:3559.1-3652.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3559.1-3652.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3559.1-3652.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3559.1-3652.4" - wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:3559.1-3652.4" - wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:4060.1-4068.4" - wire $0\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:3559.1-3652.4" - wire $0\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:3559.1-3652.4" - wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:3559.1-3652.4" - wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:3559.1-3652.4" - wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 13 $0\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:3559.1-3652.4" - wire $0\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:3559.1-3652.4" - wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3559.1-3652.4" - wire $0\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:663.32-663.76" - wire $0\main_sdram_bankmachine1_trascon_ready[0:0] - attribute \src "ls180.v:661.32-661.75" - wire $0\main_sdram_bankmachine1_trccon_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:3678.1-3685.4" - wire $0\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:703.5-703.64" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:686.5-686.67" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:687.5-687.66" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3700.1-3707.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3667.1-3674.4" - wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:3716.1-3809.4" - wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:3716.1-3809.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3716.1-3809.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3716.1-3809.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3716.1-3809.4" - wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:3716.1-3809.4" - wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:4069.1-4077.4" - wire $0\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:3716.1-3809.4" - wire $0\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:3716.1-3809.4" - wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:3716.1-3809.4" - wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:3716.1-3809.4" - wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 13 $0\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:3716.1-3809.4" - wire $0\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:3716.1-3809.4" - wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3716.1-3809.4" - wire $0\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:745.32-745.76" - wire $0\main_sdram_bankmachine2_trascon_ready[0:0] - attribute \src "ls180.v:743.32-743.75" - wire $0\main_sdram_bankmachine2_trccon_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:3835.1-3842.4" - wire $0\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:785.5-785.64" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:768.5-768.67" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:769.5-769.66" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3857.1-3864.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3824.1-3831.4" - wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:3873.1-3966.4" - wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:3873.1-3966.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3873.1-3966.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3873.1-3966.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3873.1-3966.4" - wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:3873.1-3966.4" - wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:4078.1-4086.4" - wire $0\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:3873.1-3966.4" - wire $0\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:3873.1-3966.4" - wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:3873.1-3966.4" - wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:3873.1-3966.4" - wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 13 $0\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:3873.1-3966.4" - wire $0\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:3873.1-3966.4" - wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3873.1-3966.4" - wire $0\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:827.32-827.76" - wire $0\main_sdram_bankmachine3_trascon_ready[0:0] - attribute \src "ls180.v:825.32-825.75" - wire $0\main_sdram_bankmachine3_trccon_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:4000.1-4005.4" - wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:4006.1-4011.4" - wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:4012.1-4017.4" - wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:835.5-835.43" - wire $0\main_sdram_choose_cmd_cmd_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:3986.1-3992.4" - wire width 4 $0\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:833.5-833.48" - wire $0\main_sdram_choose_cmd_want_activates[0:0] - attribute \src "ls180.v:832.5-832.43" - wire $0\main_sdram_choose_cmd_want_cmds[0:0] - attribute \src "ls180.v:830.5-830.44" - wire $0\main_sdram_choose_cmd_want_reads[0:0] - attribute \src "ls180.v:831.5-831.45" - wire $0\main_sdram_choose_cmd_want_writes[0:0] - attribute \src "ls180.v:4033.1-4038.4" - wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:4039.1-4044.4" - wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:4045.1-4050.4" - wire $0\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:4091.1-4163.4" - wire $0\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:4019.1-4025.4" - wire width 4 $0\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:4091.1-4163.4" - wire $0\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:4091.1-4163.4" - wire $0\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:4091.1-4163.4" - wire $0\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:3308.1-3338.4" - wire $0\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 13 $0\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:483.5-483.42" - wire $0\main_sdram_cmd_payload_is_read[0:0] - attribute \src "ls180.v:484.5-484.43" - wire $0\main_sdram_cmd_payload_is_write[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:4091.1-4163.4" - wire $0\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:3308.1-3338.4" - wire $0\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:419.5-419.38" - wire $0\main_sdram_command_issue_w[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_command_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 6 $0\main_sdram_command_storage[5:0] - attribute \src "ls180.v:468.5-468.35" - wire $0\main_sdram_dfi_p0_act_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 13 $0\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:4091.1-4163.4" - wire $0\main_sdram_en0[0:0] - attribute \src "ls180.v:4091.1-4163.4" - wire $0\main_sdram_en1[0:0] - attribute \src "ls180.v:4187.1-4200.4" - wire width 16 $0\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:4187.1-4200.4" - wire width 2 $0\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:369.5-369.36" - wire $0\main_sdram_inti_p0_act_n[0:0] - attribute \src "ls180.v:3249.1-3265.4" - wire $0\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:3249.1-3265.4" - wire $0\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:3249.1-3265.4" - wire $0\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" - wire width 16 $0\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:3191.1-3245.4" - wire $0\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:3249.1-3265.4" - wire $0\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" - wire $0\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" - wire width 13 $0\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:3191.1-3245.4" - wire width 2 $0\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:3191.1-3245.4" - wire $0\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" - wire $0\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:3191.1-3245.4" - wire $0\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" - wire $0\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:3191.1-3245.4" - wire $0\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" - wire $0\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:3191.1-3245.4" - wire $0\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" - wire $0\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" - wire width 16 $0\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:3191.1-3245.4" - wire $0\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:3191.1-3245.4" - wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:866.12-866.36" - wire width 13 $0\main_sdram_nop_a[12:0] - attribute \src "ls180.v:867.11-867.35" - wire width 2 $0\main_sdram_nop_ba[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:3308.1-3338.4" - wire $0\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:3191.1-3245.4" - wire width 16 $0\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:3191.1-3245.4" - wire $0\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdram_status[15:0] - attribute \src "ls180.v:869.5-869.31" - wire $0\main_sdram_steerer0[0:0] - attribute \src "ls180.v:870.5-870.31" - wire $0\main_sdram_steerer1[0:0] - attribute \src "ls180.v:4091.1-4163.4" - wire width 2 $0\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_sdram_storage[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:874.32-874.63" - wire $0\main_sdram_tfawcon_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 5 $0\main_sdram_time0[4:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_sdram_time1[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 10 $0\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:872.32-872.63" - wire $0\main_sdram_trrdcon_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:3026.1-3072.4" - wire $0\main_socbushandler_converted_interface_ack[0:0] - attribute \src "ls180.v:921.5-921.54" - wire $0\main_socbushandler_converted_interface_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_socbushandler_counter[0:0] - attribute \src "ls180.v:3026.1-3072.4" - wire $0\main_socbushandler_counter_converter2_next_value[0:0] - attribute \src "ls180.v:3026.1-3072.4" - wire $0\main_socbushandler_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 64 $0\main_socbushandler_dat_r[63:0] - attribute \src "ls180.v:3026.1-3072.4" - wire $0\main_socbushandler_skip[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_spimaster11_storage[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_spimaster12_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_spimaster16_storage[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_spimaster17_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_spimaster1_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_spimaster1_storage[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_spimaster21_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_spimaster22_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_spimaster23_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_spimaster24_re[0:0] - attribute \src "ls180.v:4420.1-4468.4" - wire $0\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:4420.1-4468.4" - wire $0\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_spimaster27_count[2:0] - attribute \src "ls180.v:4420.1-4468.4" - wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:4420.1-4468.4" - wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:4420.1-4468.4" - wire $0\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:4420.1-4468.4" - wire $0\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:4420.1-4468.4" - wire $0\main_spimaster2_done[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:4420.1-4468.4" - wire $0\main_spimaster3_irq[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_spimaster5_miso[7:0] - attribute \src "ls180.v:1108.12-1108.47" - wire width 16 $0\main_spimaster8_clk_divider[15:0] - attribute \src "ls180.v:6556.1-6561.4" - wire $0\main_spimaster9_start[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:4479.1-4527.4" - wire $0\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 16 $0\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_spisdcard_count[2:0] - attribute \src "ls180.v:4479.1-4527.4" - wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:4479.1-4527.4" - wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:4479.1-4527.4" - wire $0\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:4479.1-4527.4" - wire $0\main_spisdcard_done0[0:0] - attribute \src "ls180.v:4479.1-4527.4" - wire $0\main_spisdcard_irq[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_spisdcard_miso[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:4479.1-4527.4" - wire $0\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:4479.1-4527.4" - wire $0\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 3 $0\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:6602.1-6607.4" - wire $0\main_spisdcard_start1[0:0] - attribute \src "ls180.v:3100.1-3110.4" - wire width 8 $0\main_sram0_we[7:0] - attribute \src "ls180.v:3114.1-3124.4" - wire width 8 $0\main_sram1_we[7:0] - attribute \src "ls180.v:3128.1-3138.4" - wire width 8 $0\main_sram2_we[7:0] - attribute \src "ls180.v:3142.1-3152.4" - wire width 8 $0\main_sram3_we[7:0] - attribute \src "ls180.v:4327.1-4331.4" - wire width 2 $0\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:4316.1-4320.4" - wire width 2 $0\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_phy_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:957.5-957.38" - wire $0\main_uart_phy_source_first[0:0] - attribute \src "ls180.v:958.5-958.37" - wire $0\main_uart_phy_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 32 $0\main_uart_phy_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 8 $0\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:1084.5-1084.27" - wire $0\main_uart_reset[0:0] - attribute \src "ls180.v:4321.1-4326.4" - wire $0\main_uart_rx_clear[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 5 $0\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:1066.5-1066.37" - wire $0\main_uart_rx_fifo_replace[0:0] - attribute \src "ls180.v:4379.1-4386.4" - wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_rx_pending[0:0] - attribute \src "ls180.v:4310.1-4315.4" - wire $0\main_uart_tx_clear[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 5 $0\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 4 $0\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:1029.5-1029.37" - wire $0\main_uart_tx_fifo_replace[0:0] - attribute \src "ls180.v:1012.5-1012.40" - wire $0\main_uart_tx_fifo_sink_first[0:0] - attribute \src "ls180.v:1013.5-1013.39" - wire $0\main_uart_tx_fifo_sink_last[0:0] - attribute \src "ls180.v:4349.1-4356.4" - wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_uart_tx_pending[0:0] - attribute \src "ls180.v:4219.1-4265.4" - wire $0\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:3026.1-3072.4" - wire width 30 $0\main_wb_sdram_adr[29:0] - attribute \src "ls180.v:3026.1-3072.4" - wire $0\main_wb_sdram_cyc[0:0] - attribute \src "ls180.v:3014.1-3024.4" - wire width 32 $0\main_wb_sdram_dat_w[31:0] - attribute \src "ls180.v:3026.1-3072.4" - wire width 4 $0\main_wb_sdram_sel[3:0] - attribute \src "ls180.v:3026.1-3072.4" - wire $0\main_wb_sdram_stb[0:0] - attribute \src "ls180.v:3026.1-3072.4" - wire $0\main_wb_sdram_we[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_wdata_consumed[0:0] - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0\memadr[5:0] - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0\memadr_1[5:0] - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0\memadr_2[5:0] - attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0\memadr_3[5:0] - attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0\memadr_4[5:0] - attribute \src "ls180.v:10493.1-10497.4" +module \ls180sram4k + attribute \src "ls180.v:5495.1-5505.4" + wire width 7 $0$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1435 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $0$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1436 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $0$memwr$\mem$ls180.v:5497$1_EN[31:0]$1437 + attribute \src "ls180.v:5495.1-5505.4" + wire width 7 $0$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1438 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $0$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1439 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $0$memwr$\mem$ls180.v:5499$2_EN[31:0]$1440 + attribute \src "ls180.v:5495.1-5505.4" + wire width 7 $0$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1441 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $0$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1442 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $0$memwr$\mem$ls180.v:5501$3_EN[31:0]$1443 + attribute \src "ls180.v:5495.1-5505.4" + wire width 7 $0$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1444 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $0$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1445 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $0$memwr$\mem$ls180.v:5503$4_EN[31:0]$1446 + attribute \src "ls180.v:5515.1-5525.4" + wire width 5 $0$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1461 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1462 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1463 + attribute \src "ls180.v:5515.1-5525.4" + wire width 5 $0$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1464 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1465 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1466 + attribute \src "ls180.v:5515.1-5525.4" + wire width 5 $0$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1467 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1468 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1469 + attribute \src "ls180.v:5515.1-5525.4" + wire width 5 $0$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1470 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1471 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $0$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1472 + attribute \src "ls180.v:5535.1-5539.4" + wire width 3 $0$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1487 + attribute \src "ls180.v:5535.1-5539.4" + wire width 25 $0$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1488 + attribute \src "ls180.v:5535.1-5539.4" + wire width 25 $0$memwr$\storage$ls180.v:5537$9_EN[24:0]$1489 + attribute \src "ls180.v:5549.1-5553.4" + wire width 3 $0$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1497 + attribute \src "ls180.v:5549.1-5553.4" + wire width 25 $0$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1498 + attribute \src "ls180.v:5549.1-5553.4" + wire width 25 $0$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1499 + attribute \src "ls180.v:5563.1-5567.4" + wire width 3 $0$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1507 + attribute \src "ls180.v:5563.1-5567.4" + wire width 25 $0$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1508 + attribute \src "ls180.v:5563.1-5567.4" + wire width 25 $0$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1509 + attribute \src "ls180.v:5577.1-5581.4" + wire width 3 $0$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1517 + attribute \src "ls180.v:5577.1-5581.4" + wire width 25 $0$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1518 + attribute \src "ls180.v:5577.1-5581.4" + wire width 25 $0$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1519 + attribute \src "ls180.v:5592.1-5596.4" + wire width 4 $0$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1527 + attribute \src "ls180.v:5592.1-5596.4" + wire width 10 $0$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1528 + attribute \src "ls180.v:5592.1-5596.4" + wire width 10 $0$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1529 + attribute \src "ls180.v:5609.1-5613.4" + wire width 4 $0$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1537 + attribute \src "ls180.v:5609.1-5613.4" + wire width 10 $0$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1538 + attribute \src "ls180.v:5609.1-5613.4" + wire width 10 $0$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1539 + attribute \src "ls180.v:3949.1-3965.4" + wire width 2 $0\array_muxed0[1:0] + attribute \src "ls180.v:3966.1-3982.4" + wire width 13 $0\array_muxed1[12:0] + attribute \src "ls180.v:3983.1-3999.4" + wire $0\array_muxed2[0:0] + attribute \src "ls180.v:4000.1-4016.4" + wire $0\array_muxed3[0:0] + attribute \src "ls180.v:4017.1-4033.4" + wire $0\array_muxed4[0:0] + attribute \src "ls180.v:4034.1-4050.4" + wire $0\array_muxed5[0:0] + attribute \src "ls180.v:4051.1-4067.4" + wire $0\array_muxed6[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\cmd_consumed[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\converter_counter[0:0] + attribute \src "ls180.v:2795.1-2841.4" + wire $0\converter_counter_subfragments_next_value[0:0] + attribute \src "ls180.v:2795.1-2841.4" + wire $0\converter_counter_subfragments_next_value_ce[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 32 $0\converter_dat_r[31:0] + attribute \src "ls180.v:2795.1-2841.4" + wire $0\converter_skip[0:0] + attribute \src "ls180.v:4178.1-4283.4" + wire width 16 $0\dfi_p0_rddata[15:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 36 $0\dummy[35:0] + attribute \src "ls180.v:1499.1-1504.4" + wire width 3 $0\eint_tmp[2:0] + attribute \src "ls180.v:2903.1-2907.4" + wire width 2 $0\eventmanager_pending_w[1:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\eventmanager_re[0:0] + attribute \src "ls180.v:2892.1-2896.4" + wire width 2 $0\eventmanager_status_w[1:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 2 $0\eventmanager_storage[1:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\gpio0_oe_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\gpio0_oe_storage[7:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\gpio0_out_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\gpio0_out_storage[7:0] + attribute \src "ls180.v:2971.1-2981.4" + wire width 8 $0\gpio0_pads_gpio0i[7:0] + attribute \src "ls180.v:4178.1-4283.4" + wire width 8 $0\gpio0_pads_gpio0o[7:0] + attribute \src "ls180.v:4178.1-4283.4" + wire width 8 $0\gpio0_pads_gpio0oe[7:0] + attribute \src "ls180.v:4178.1-4283.4" + wire width 8 $0\gpio0_status[7:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\gpio1_oe_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\gpio1_oe_storage[7:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\gpio1_out_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\gpio1_out_storage[7:0] + attribute \src "ls180.v:2982.1-2992.4" + wire width 8 $0\gpio1_pads_gpio1i[7:0] + attribute \src "ls180.v:4178.1-4283.4" + wire width 8 $0\gpio1_pads_gpio1o[7:0] + attribute \src "ls180.v:4178.1-4283.4" + wire width 8 $0\gpio1_pads_gpio1oe[7:0] + attribute \src "ls180.v:4178.1-4283.4" + wire width 8 $0\gpio1_status[7:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\i2c_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\i2c_storage[2:0] + attribute \src "ls180.v:4174.1-4176.4" + wire $0\int_rst[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 32 $0\libresocsim_bus_errors[31:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_converter0_counter[0:0] + attribute \src "ls180.v:1532.1-1578.4" + wire $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] + attribute \src "ls180.v:1532.1-1578.4" + wire $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 64 $0\libresocsim_converter0_dat_r[63:0] + attribute \src "ls180.v:1532.1-1578.4" + wire $0\libresocsim_converter0_skip[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_converter1_counter[0:0] + attribute \src "ls180.v:1592.1-1638.4" + wire $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] + attribute \src "ls180.v:1592.1-1638.4" + wire $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 64 $0\libresocsim_converter1_dat_r[63:0] + attribute \src "ls180.v:1592.1-1638.4" + wire $0\libresocsim_converter1_skip[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_converter2_counter[0:0] + attribute \src "ls180.v:1652.1-1698.4" + wire $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] + attribute \src "ls180.v:1652.1-1698.4" + wire $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 64 $0\libresocsim_converter2_dat_r[63:0] + attribute \src "ls180.v:1652.1-1698.4" + wire $0\libresocsim_converter2_skip[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 20 $0\libresocsim_count[19:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_en_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_en_storage[0:0] + attribute \src "ls180.v:3149.1-3160.4" + wire $0\libresocsim_error[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 2 $0\libresocsim_grant[1:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\libresocsim_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1532.1-1578.4" + wire width 30 $0\libresocsim_interface0_converted_interface_adr[29:0] + attribute \src "ls180.v:152.11-152.64" + wire width 2 $0\libresocsim_interface0_converted_interface_bte[1:0] + attribute \src "ls180.v:151.11-151.64" + wire width 3 $0\libresocsim_interface0_converted_interface_cti[2:0] + attribute \src "ls180.v:1532.1-1578.4" + wire $0\libresocsim_interface0_converted_interface_cyc[0:0] + attribute \src "ls180.v:1520.1-1530.4" + wire width 32 $0\libresocsim_interface0_converted_interface_dat_w[31:0] + attribute \src "ls180.v:1532.1-1578.4" + wire width 4 $0\libresocsim_interface0_converted_interface_sel[3:0] + attribute \src "ls180.v:1532.1-1578.4" + wire $0\libresocsim_interface0_converted_interface_stb[0:0] + attribute \src "ls180.v:1532.1-1578.4" + wire $0\libresocsim_interface0_converted_interface_we[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\libresocsim_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1592.1-1638.4" + wire width 30 $0\libresocsim_interface1_converted_interface_adr[29:0] + attribute \src "ls180.v:167.11-167.64" + wire width 2 $0\libresocsim_interface1_converted_interface_bte[1:0] + attribute \src "ls180.v:166.11-166.64" + wire width 3 $0\libresocsim_interface1_converted_interface_cti[2:0] + attribute \src "ls180.v:1592.1-1638.4" + wire $0\libresocsim_interface1_converted_interface_cyc[0:0] + attribute \src "ls180.v:1580.1-1590.4" + wire width 32 $0\libresocsim_interface1_converted_interface_dat_w[31:0] + attribute \src "ls180.v:1592.1-1638.4" + wire width 4 $0\libresocsim_interface1_converted_interface_sel[3:0] + attribute \src "ls180.v:1592.1-1638.4" + wire $0\libresocsim_interface1_converted_interface_stb[0:0] + attribute \src "ls180.v:1592.1-1638.4" + wire $0\libresocsim_interface1_converted_interface_we[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\libresocsim_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1652.1-1698.4" + wire width 30 $0\libresocsim_interface2_converted_interface_adr[29:0] + attribute \src "ls180.v:182.11-182.64" + wire width 2 $0\libresocsim_interface2_converted_interface_bte[1:0] + attribute \src "ls180.v:181.11-181.64" + wire width 3 $0\libresocsim_interface2_converted_interface_cti[2:0] + attribute \src "ls180.v:1652.1-1698.4" + wire $0\libresocsim_interface2_converted_interface_cyc[0:0] + attribute \src "ls180.v:1640.1-1650.4" + wire width 32 $0\libresocsim_interface2_converted_interface_dat_w[31:0] + attribute \src "ls180.v:1652.1-1698.4" + wire width 4 $0\libresocsim_interface2_converted_interface_sel[3:0] + attribute \src "ls180.v:1652.1-1698.4" + wire $0\libresocsim_interface2_converted_interface_stb[0:0] + attribute \src "ls180.v:1652.1-1698.4" + wire $0\libresocsim_interface2_converted_interface_we[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\libresocsim_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\libresocsim_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\libresocsim_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\libresocsim_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\libresocsim_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2993.1-3011.4" + wire width 16 $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] + attribute \src "ls180.v:3012.1-3030.4" + wire width 16 $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] + attribute \src "ls180.v:4178.1-4283.4" + wire width 13 $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] + attribute \src "ls180.v:4178.1-4283.4" + wire width 2 $0\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] + attribute \src "ls180.v:4178.1-4283.4" + wire $0\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] + attribute \src "ls180.v:4178.1-4283.4" + wire $0\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] + attribute \src "ls180.v:4178.1-4283.4" + wire $0\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] + attribute \src "ls180.v:4178.1-4283.4" + wire $0\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] + attribute \src "ls180.v:4178.1-4283.4" + wire width 2 $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] + attribute \src "ls180.v:4178.1-4283.4" + wire width 16 $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] + attribute \src "ls180.v:4178.1-4283.4" + wire $0\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] + attribute \src "ls180.v:4178.1-4283.4" + wire $0\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] + attribute \src "ls180.v:4178.1-4283.4" + wire $0\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] + attribute \src "ls180.v:124.5-124.64" + wire $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] + attribute \src "ls180.v:126.5-126.65" + wire $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] + attribute \src "ls180.v:125.5-125.65" + wire $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] + attribute \src "ls180.v:116.5-116.58" + wire $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] + attribute \src "ls180.v:1592.1-1638.4" + wire $0\libresocsim_libresoc_dbus_ack[0:0] + attribute \src "ls180.v:64.5-64.41" + wire $0\libresocsim_libresoc_dbus_err[0:0] + attribute \src "ls180.v:1532.1-1578.4" + wire $0\libresocsim_libresoc_ibus_ack[0:0] + attribute \src "ls180.v:73.5-73.41" + wire $0\libresocsim_libresoc_ibus_err[0:0] + attribute \src "ls180.v:1511.1-1518.4" + wire width 16 $0\libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:1652.1-1698.4" + wire $0\libresocsim_libresoc_jtag_wb_ack[0:0] + attribute \src "ls180.v:104.5-104.44" + wire $0\libresocsim_libresoc_jtag_wb_err[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 14 $0\libresocsim_libresocsim_adr[13:0] + attribute \src "ls180.v:3035.1-3071.4" + wire width 14 $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] + attribute \src "ls180.v:3035.1-3071.4" + wire $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\libresocsim_libresocsim_dat_w[7:0] + attribute \src "ls180.v:3035.1-3071.4" + wire width 8 $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] + attribute \src "ls180.v:3035.1-3071.4" + wire $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_libresocsim_we[0:0] + attribute \src "ls180.v:3035.1-3071.4" + wire $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] + attribute \src "ls180.v:3035.1-3071.4" + wire $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] + attribute \src "ls180.v:3035.1-3071.4" + wire $0\libresocsim_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:3035.1-3071.4" + wire width 32 $0\libresocsim_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1071.5-1071.48" + wire $0\libresocsim_libresocsim_wishbone_err[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_load_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 32 $0\libresocsim_load_storage[31:0] + attribute \src "ls180.v:3035.1-3071.4" + wire width 2 $0\libresocsim_next_state[1:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:198.5-198.35" + wire $0\libresocsim_ram_bus_err[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_reload_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 32 $0\libresocsim_reload_storage[31:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_reset_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_reset_storage[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_scratch_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 32 $0\libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:3149.1-3160.4" + wire $0\libresocsim_shared_ack[0:0] + attribute \src "ls180.v:3149.1-3160.4" + wire width 32 $0\libresocsim_shared_dat_r[31:0] + attribute \src "ls180.v:3090.1-3098.4" + wire width 6 $0\libresocsim_slave_sel[5:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 6 $0\libresocsim_slave_sel_r[5:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 2 $0\libresocsim_state[1:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_update_value_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 32 $0\libresocsim_value[31:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 32 $0\libresocsim_value_status[31:0] + attribute \src "ls180.v:1701.1-1707.4" + wire width 4 $0\libresocsim_we[3:0] + attribute \src "ls180.v:1713.1-1718.4" + wire $0\libresocsim_zero_clear[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\libresocsim_zero_pending[0:0] + attribute \src "ls180.v:2795.1-2841.4" + wire width 30 $0\litedram_wb_adr[29:0] + attribute \src "ls180.v:2795.1-2841.4" + wire $0\litedram_wb_cyc[0:0] + attribute \src "ls180.v:2783.1-2793.4" + wire width 16 $0\litedram_wb_dat_w[15:0] + attribute \src "ls180.v:2795.1-2841.4" + wire width 2 $0\litedram_wb_sel[1:0] + attribute \src "ls180.v:2795.1-2841.4" + wire $0\litedram_wb_stb[0:0] + attribute \src "ls180.v:2795.1-2841.4" + wire $0\litedram_wb_we[0:0] + attribute \src "ls180.v:5495.1-5505.4" + wire width 7 $0\memadr[6:0] + attribute \src "ls180.v:5515.1-5525.4" + wire width 5 $0\memadr_1[4:0] + attribute \src "ls180.v:5535.1-5539.4" wire width 25 $0\memdat[24:0] - attribute \src "ls180.v:10507.1-10511.4" + attribute \src "ls180.v:5549.1-5553.4" wire width 25 $0\memdat_1[24:0] - attribute \src "ls180.v:10521.1-10525.4" + attribute \src "ls180.v:5563.1-5567.4" wire width 25 $0\memdat_2[24:0] - attribute \src "ls180.v:10535.1-10539.4" + attribute \src "ls180.v:5577.1-5581.4" wire width 25 $0\memdat_3[24:0] - attribute \src "ls180.v:10550.1-10554.4" + attribute \src "ls180.v:5592.1-5596.4" wire width 10 $0\memdat_4[9:0] - attribute \src "ls180.v:10556.1-10559.4" + attribute \src "ls180.v:5598.1-5601.4" wire width 10 $0\memdat_5[9:0] - attribute \src "ls180.v:10567.1-10571.4" + attribute \src "ls180.v:5609.1-5613.4" wire width 10 $0\memdat_6[9:0] - attribute \src "ls180.v:10573.1-10576.4" + attribute \src "ls180.v:5615.1-5618.4" wire width 10 $0\memdat_7[9:0] - attribute \src "ls180.v:10583.1-10587.4" - wire width 10 $0\memdat_8[9:0] - attribute \src "ls180.v:10597.1-10601.4" - wire width 10 $0\memdat_9[9:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 2 $0\pwm[1:0] - attribute \src "ls180.v:7633.1-7703.4" - wire $0\sdcard_clk[0:0] - attribute \src "ls180.v:7633.1-7703.4" - wire $0\sdcard_cmd_o[0:0] - attribute \src "ls180.v:7633.1-7703.4" - wire $0\sdcard_cmd_oe[0:0] - attribute \src "ls180.v:7633.1-7703.4" - wire width 4 $0\sdcard_data_o[3:0] - attribute \src "ls180.v:7633.1-7703.4" - wire $0\sdcard_data_oe[0:0] - attribute \src "ls180.v:7633.1-7703.4" - wire width 13 $0\sdram_a[12:0] - attribute \src "ls180.v:7633.1-7703.4" - wire width 2 $0\sdram_ba[1:0] - attribute \src "ls180.v:7633.1-7703.4" - wire $0\sdram_cas_n[0:0] - attribute \src "ls180.v:7633.1-7703.4" - wire $0\sdram_cke[0:0] - attribute \src "ls180.v:7633.1-7703.4" - wire $0\sdram_clock[0:0] - attribute \src "ls180.v:7633.1-7703.4" - wire $0\sdram_cs_n[0:0] - attribute \src "ls180.v:7633.1-7703.4" - wire width 2 $0\sdram_dm[1:0] - attribute \src "ls180.v:7633.1-7703.4" - wire width 16 $0\sdram_dq_o[15:0] - attribute \src "ls180.v:7633.1-7703.4" - wire $0\sdram_dq_oe[0:0] - attribute \src "ls180.v:7633.1-7703.4" - wire $0\sdram_ras_n[0:0] - attribute \src "ls180.v:7633.1-7703.4" - wire $0\sdram_we_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\spimaster_clk[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\spimaster_cs_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\spimaster_mosi[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\spisdcard_clk[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\spisdcard_cs_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\spisdcard_mosi[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\uart_tx[0:0] - attribute \src "ls180.v:1857.11-1857.49" - wire width 3 $1\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:1856.11-1856.44" - wire width 3 $1\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:1859.11-1859.49" - wire width 3 $1\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:1858.11-1858.44" - wire width 3 $1\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:1861.11-1861.49" - wire width 3 $1\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:1860.11-1860.44" - wire width 3 $1\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:1863.11-1863.49" - wire width 3 $1\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:1862.11-1862.44" - wire width 3 $1\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:2716.5-2716.41" - wire $1\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:2729.5-2729.42" - wire $1\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:2730.5-2730.42" - wire $1\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:2734.12-2734.50" - wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:2735.5-2735.42" - wire $1\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:2736.5-2736.42" - wire $1\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:2737.12-2737.50" - wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:2738.5-2738.42" - wire $1\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:2739.5-2739.42" - wire $1\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:2740.12-2740.50" - wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:2741.5-2741.42" - wire $1\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:2717.12-2717.49" - wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2742.5-2742.42" - wire $1\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:2743.12-2743.50" - wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:2744.5-2744.42" - wire $1\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:2745.5-2745.42" - wire $1\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:2746.12-2746.50" - wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:2747.12-2747.50" - wire width 64 $1\builder_comb_rhs_array_muxed25[63:0] - attribute \src "ls180.v:2748.11-2748.48" - wire width 8 $1\builder_comb_rhs_array_muxed26[7:0] - attribute \src "ls180.v:2749.5-2749.42" - wire $1\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:2750.5-2750.42" - wire $1\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:2751.5-2751.42" - wire $1\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:2718.11-2718.47" - wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:2752.11-2752.48" - wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:2753.11-2753.48" - wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:2719.5-2719.41" - wire $1\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2720.5-2720.41" - wire $1\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2721.5-2721.41" - wire $1\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2725.5-2725.41" - wire $1\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:2726.12-2726.49" - wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:2727.11-2727.47" - wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:2728.5-2728.41" - wire $1\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:2722.5-2722.39" - wire $1\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:2723.5-2723.39" - wire $1\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:2724.5-2724.39" - wire $1\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:2731.5-2731.39" - wire $1\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:2732.5-2732.39" - wire $1\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:2733.5-2733.39" - wire $1\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:1843.5-1843.41" - wire $1\builder_converter0_next_state[0:0] - attribute \src "ls180.v:1842.5-1842.36" - wire $1\builder_converter0_state[0:0] - attribute \src "ls180.v:1847.5-1847.41" - wire $1\builder_converter1_next_state[0:0] - attribute \src "ls180.v:1846.5-1846.36" - wire $1\builder_converter1_state[0:0] - attribute \src "ls180.v:1851.5-1851.41" - wire $1\builder_converter2_next_state[0:0] - attribute \src "ls180.v:1850.5-1850.36" - wire $1\builder_converter2_state[0:0] - attribute \src "ls180.v:1888.5-1888.40" - wire $1\builder_converter_next_state[0:0] - attribute \src "ls180.v:1887.5-1887.35" - wire $1\builder_converter_state[0:0] - attribute \src "ls180.v:2016.12-2016.39" - wire width 20 $1\builder_count[19:0] - attribute \src "ls180.v:2013.5-2013.25" - wire $1\builder_error[0:0] - attribute \src "ls180.v:2010.11-2010.31" - wire width 3 $1\builder_grant[2:0] - attribute \src "ls180.v:2020.11-2020.51" - wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2522.11-2522.52" - wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2555.11-2555.52" - wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2596.11-2596.52" - wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2661.11-2661.52" - wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2686.11-2686.52" - wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2061.11-2061.51" - wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2090.11-2090.51" - wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2103.11-2103.51" - wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2144.11-2144.51" - wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2185.11-2185.51" - wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2250.11-2250.51" - wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2383.11-2383.51" - wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2464.11-2464.51" - wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2481.11-2481.51" - wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1975.12-1975.43" - wire width 14 $1\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:2712.12-2712.55" - wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:2713.5-2713.50" - wire $1\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1977.11-1977.43" - wire width 8 $1\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:2710.11-2710.55" - wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:2711.5-2711.52" - wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:1976.5-1976.34" - wire $1\builder_libresocsim_we[0:0] - attribute \src "ls180.v:2714.5-2714.46" - wire $1\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:2715.5-2715.49" - wire $1\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:1985.5-1985.44" - wire $1\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1981.12-1981.54" - wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1865.11-1865.48" - wire width 3 $1\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:1864.11-1864.43" - wire width 3 $1\builder_multiplexer_state[2:0] - attribute \src "ls180.v:2819.32-2819.66" - wire $1\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:2820.32-2820.66" - wire $1\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:2839.32-2839.67" - wire $1\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:2840.32-2840.67" - wire $1\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:2841.32-2841.67" - wire $1\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:2842.32-2842.67" - wire $1\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:2843.32-2843.67" - wire $1\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:2844.32-2844.67" - wire $1\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:2845.32-2845.67" - wire $1\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:2846.32-2846.67" - wire $1\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:2847.32-2847.67" - wire $1\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:2848.32-2848.67" - wire $1\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:2849.32-2849.67" - wire $1\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:2850.32-2850.67" - wire $1\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:2851.32-2851.67" - wire $1\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:2852.32-2852.67" - wire $1\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:2821.32-2821.66" - wire $1\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:2822.32-2822.66" - wire $1\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:2823.32-2823.66" - wire $1\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:2824.32-2824.66" - wire $1\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:2825.32-2825.66" - wire $1\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:2826.32-2826.66" - wire $1\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:2827.32-2827.66" - wire $1\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:2828.32-2828.66" - wire $1\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:2829.32-2829.66" - wire $1\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:2830.32-2830.66" - wire $1\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:2831.32-2831.66" - wire $1\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:2832.32-2832.66" - wire $1\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:2833.32-2833.66" - wire $1\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:2834.32-2834.66" - wire $1\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:2835.32-2835.66" - wire $1\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:2836.32-2836.66" - wire $1\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:2837.32-2837.66" - wire $1\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:2838.32-2838.66" - wire $1\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:1883.5-1883.43" - wire $1\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:1884.5-1884.43" - wire $1\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:1885.5-1885.43" - wire $1\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:1886.5-1886.43" - wire $1\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:1882.5-1882.42" - wire $1\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:2709.11-2709.36" - wire width 2 $1\builder_next_state[1:0] - attribute \src "ls180.v:1855.11-1855.46" - wire width 2 $1\builder_refresher_next_state[1:0] - attribute \src "ls180.v:1854.11-1854.41" - wire width 2 $1\builder_refresher_state[1:0] - attribute \src "ls180.v:1964.11-1964.51" - wire width 2 $1\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:1963.11-1963.46" - wire width 2 $1\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:1932.5-1932.57" - wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:1931.5-1931.52" - wire $1\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:1944.11-1944.47" - wire width 3 $1\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:1943.11-1943.42" - wire width 3 $1\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:1968.5-1968.49" - wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:1967.5-1967.44" - wire $1\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:1972.11-1972.65" - wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:1971.11-1971.60" - wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:1920.11-1920.46" - wire width 3 $1\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:1919.11-1919.41" - wire width 3 $1\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:1908.11-1908.52" - wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:1907.11-1907.47" - wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:1904.11-1904.52" - wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:1903.11-1903.47" - wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:1916.5-1916.46" - wire $1\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:1915.5-1915.41" - wire $1\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:1924.11-1924.53" - wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:1923.11-1923.48" - wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:1900.5-1900.46" - wire $1\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:1899.5-1899.41" - wire $1\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:2004.5-2004.30" - wire $1\builder_shared_ack[0:0] - attribute \src "ls180.v:2000.12-2000.40" - wire width 32 $1\builder_shared_dat_r[31:0] - attribute \src "ls180.v:2011.12-2011.37" - wire width 13 $1\builder_slave_sel[12:0] - attribute \src "ls180.v:2012.12-2012.39" - wire width 13 $1\builder_slave_sel_r[12:0] - attribute \src "ls180.v:1892.11-1892.47" - wire width 2 $1\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:1891.11-1891.42" - wire width 2 $1\builder_spimaster0_state[1:0] - attribute \src "ls180.v:1896.11-1896.47" - wire width 2 $1\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:1895.11-1895.42" - wire width 2 $1\builder_spimaster1_state[1:0] - attribute \src "ls180.v:2708.11-2708.31" - wire width 2 $1\builder_state[1:0] - attribute \src "ls180.v:2761.5-2761.39" - wire $1\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:2762.5-2762.39" - wire $1\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:2754.11-2754.47" - wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:2755.12-2755.49" - wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2756.5-2756.41" - wire $1\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:2757.5-2757.41" - wire $1\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2758.5-2758.41" - wire $1\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2759.5-2759.41" - wire $1\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2760.5-2760.41" - wire $1\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:938.5-938.29" - wire $1\main_cmd_consumed[0:0] - attribute \src "ls180.v:321.5-321.35" - wire $1\main_converter0_counter[0:0] - attribute \src "ls180.v:1844.5-1844.57" - wire $1\main_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:1845.5-1845.60" - wire $1\main_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:323.12-323.41" - wire width 64 $1\main_converter0_dat_r[63:0] - attribute \src "ls180.v:320.5-320.32" - wire $1\main_converter0_skip[0:0] - attribute \src "ls180.v:336.5-336.35" - wire $1\main_converter1_counter[0:0] - attribute \src "ls180.v:1848.5-1848.57" - wire $1\main_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:1849.5-1849.60" - wire $1\main_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:338.12-338.41" - wire width 64 $1\main_converter1_dat_r[63:0] - attribute \src "ls180.v:335.5-335.32" - wire $1\main_converter1_skip[0:0] - attribute \src "ls180.v:935.5-935.34" - wire $1\main_converter_counter[0:0] - attribute \src "ls180.v:1889.5-1889.55" - wire $1\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:1890.5-1890.58" - wire $1\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:937.12-937.40" - wire width 32 $1\main_converter_dat_r[31:0] - attribute \src "ls180.v:934.5-934.31" - wire $1\main_converter_skip[0:0] - attribute \src "ls180.v:357.12-357.38" - wire width 16 $1\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:358.5-358.36" - wire $1\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:1175.12-1175.30" - wire width 24 $1\main_dummy[23:0] - attribute \src "ls180.v:1086.12-1086.49" - wire width 16 $1\main_gpiotristateasic0_status[15:0] - attribute \src "ls180.v:1092.5-1092.40" - wire $1\main_gpiotristateasic1_oe_re[0:0] - attribute \src "ls180.v:1091.12-1091.53" - wire width 16 $1\main_gpiotristateasic1_oe_storage[15:0] - attribute \src "ls180.v:1096.5-1096.41" - wire $1\main_gpiotristateasic1_out_re[0:0] - attribute \src "ls180.v:1095.12-1095.54" - wire width 16 $1\main_gpiotristateasic1_out_storage[15:0] - attribute \src "ls180.v:1093.12-1093.49" - wire width 16 $1\main_gpiotristateasic1_status[15:0] - attribute \src "ls180.v:1200.5-1200.23" - wire $1\main_i2c_re[0:0] - attribute \src "ls180.v:1199.11-1199.34" - wire width 3 $1\main_i2c_storage[2:0] - attribute \src "ls180.v:342.5-342.24" - wire $1\main_int_rst[0:0] - attribute \src "ls180.v:315.5-315.51" - wire $1\main_interface0_converted_interface_ack[0:0] - attribute \src "ls180.v:255.5-255.39" - wire $1\main_interface0_ram_bus_ack[0:0] - attribute \src "ls180.v:1748.12-1748.43" - wire width 32 $1\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1752.5-1752.35" - wire $1\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1751.11-1751.41" - wire width 8 $1\main_interface1_bus_sel[7:0] - attribute \src "ls180.v:1753.5-1753.35" - wire $1\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:1755.5-1755.34" - wire $1\main_interface1_bus_we[0:0] - attribute \src "ls180.v:330.5-330.51" - wire $1\main_interface1_converted_interface_ack[0:0] - attribute \src "ls180.v:270.5-270.39" - wire $1\main_interface1_ram_bus_ack[0:0] - attribute \src "ls180.v:285.5-285.39" - wire $1\main_interface2_ram_bus_ack[0:0] - attribute \src "ls180.v:300.5-300.39" - wire $1\main_interface3_ram_bus_ack[0:0] - attribute \src "ls180.v:63.12-63.47" - wire width 32 $1\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:227.5-227.34" - wire $1\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:226.5-226.39" - wire $1\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:247.5-247.44" - wire $1\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:246.5-246.49" - wire $1\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:65.12-65.55" - wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:88.12-88.58" - wire width 30 $1\main_libresocsim_libresoc_xics_icp_adr[29:0] - attribute \src "ls180.v:92.5-92.50" - wire $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] - attribute \src "ls180.v:89.12-89.60" - wire width 32 $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] - attribute \src "ls180.v:91.11-91.56" - wire width 4 $1\main_libresocsim_libresoc_xics_icp_sel[3:0] - attribute \src "ls180.v:93.5-93.50" - wire $1\main_libresocsim_libresoc_xics_icp_stb[0:0] - attribute \src "ls180.v:95.5-95.49" - wire $1\main_libresocsim_libresoc_xics_icp_we[0:0] - attribute \src "ls180.v:97.12-97.58" - wire width 30 $1\main_libresocsim_libresoc_xics_ics_adr[29:0] - attribute \src "ls180.v:101.5-101.50" - wire $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] - attribute \src "ls180.v:98.12-98.60" - wire width 32 $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] - attribute \src "ls180.v:100.11-100.56" - wire width 4 $1\main_libresocsim_libresoc_xics_ics_sel[3:0] - attribute \src "ls180.v:102.5-102.50" - wire $1\main_libresocsim_libresoc_xics_ics_stb[0:0] - attribute \src "ls180.v:104.5-104.49" - wire $1\main_libresocsim_libresoc_xics_ics_we[0:0] - attribute \src "ls180.v:223.5-223.36" - wire $1\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:222.12-222.49" - wire width 32 $1\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:213.5-213.40" - wire $1\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:225.5-225.38" - wire $1\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:224.12-224.51" - wire width 32 $1\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:56.5-56.37" - wire $1\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:55.5-55.42" - wire $1\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:58.5-58.39" - wire $1\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:57.12-57.60" - wire width 32 $1\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:229.5-229.44" - wire $1\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:228.5-228.49" - wire $1\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:248.12-248.42" - wire width 32 $1\main_libresocsim_value[31:0] - attribute \src "ls180.v:230.12-230.49" - wire width 32 $1\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:220.11-220.37" - wire width 8 $1\main_libresocsim_we[7:0] - attribute \src "ls180.v:236.5-236.39" - wire $1\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:237.5-237.45" - wire $1\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:234.5-234.41" - wire $1\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:926.12-926.40" - wire width 30 $1\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:930.5-930.32" - wire $1\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:927.12-927.42" - wire width 16 $1\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:929.11-929.38" - wire width 2 $1\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:931.5-931.32" - wire $1\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:933.5-933.31" - wire $1\main_litedram_wb_we[0:0] - attribute \src "ls180.v:1179.12-1179.37" - wire width 32 $1\main_pwm0_counter[31:0] - attribute \src "ls180.v:1181.5-1181.31" - wire $1\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:1180.5-1180.36" - wire $1\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:1185.5-1185.31" - wire $1\main_pwm0_period_re[0:0] - attribute \src "ls180.v:1184.12-1184.44" - wire width 32 $1\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:1183.5-1183.30" - wire $1\main_pwm0_width_re[0:0] - attribute \src "ls180.v:1182.12-1182.43" - wire width 32 $1\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:1189.12-1189.37" - wire width 32 $1\main_pwm1_counter[31:0] - attribute \src "ls180.v:1191.5-1191.31" - wire $1\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:1190.5-1190.36" - wire $1\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:1195.5-1195.31" - wire $1\main_pwm1_period_re[0:0] - attribute \src "ls180.v:1194.12-1194.44" - wire width 32 $1\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:1193.5-1193.30" - wire $1\main_pwm1_width_re[0:0] - attribute \src "ls180.v:1192.12-1192.43" - wire width 32 $1\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:359.11-359.32" - wire width 3 $1\main_rddata_en[2:0] - attribute \src "ls180.v:1717.11-1717.50" - wire width 3 $1\main_sdblock2mem_converter_demux[2:0] - attribute \src "ls180.v:1713.5-1713.51" - wire $1\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:1714.5-1714.50" - wire $1\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:1715.12-1715.66" - wire width 64 $1\main_sdblock2mem_converter_source_payload_data[63:0] - attribute \src "ls180.v:1716.11-1716.77" - wire width 4 $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1719.5-1719.49" - wire $1\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:1692.11-1692.47" - wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:1689.11-1689.45" - wire width 6 $1\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:1691.11-1691.47" - wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1693.11-1693.50" - wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1727.12-1727.62" - wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:1728.12-1728.60" - wire width 64 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] - attribute \src "ls180.v:1725.5-1725.45" - wire $1\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:1735.5-1735.54" - wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:1734.12-1734.67" - wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:1739.5-1739.56" - wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:1738.5-1738.61" - wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:1737.5-1737.56" - wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:1736.12-1736.69" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:1743.5-1743.54" - wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:1742.5-1742.59" - wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:1745.12-1745.61" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:1965.12-1965.87" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:1966.5-1966.82" - wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:1730.5-1730.57" - wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:1740.5-1740.53" - wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:1509.5-1509.38" - wire $1\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:1508.12-1508.51" - wire width 32 $1\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:1507.5-1507.39" - wire $1\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:1506.11-1506.51" - wire width 10 $1\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:1493.5-1493.39" - wire $1\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:1492.12-1492.52" - wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:1495.5-1495.38" - wire $1\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:1494.12-1494.51" - wire width 32 $1\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:1648.11-1648.39" - wire width 3 $1\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:1949.11-1949.62" - wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:1950.5-1950.59" - wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:1649.5-1649.32" - wire $1\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:1945.5-1945.55" - wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:1946.5-1946.58" - wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:1650.5-1650.33" - wire $1\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:1953.5-1953.56" - wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:1954.5-1954.59" - wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:1500.13-1500.53" - wire width 128 $1\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:1961.13-1961.76" - wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:1962.5-1962.69" - wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1651.5-1651.35" - wire $1\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:1955.5-1955.58" - wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:1956.5-1956.61" - wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:1609.11-1609.47" - wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:1615.5-1615.46" - wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:1614.12-1614.54" - wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:1610.12-1610.58" - wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:1622.5-1622.46" - wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:1621.12-1621.54" - wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:1617.12-1617.58" - wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:1629.5-1629.46" - wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:1628.12-1628.54" - wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:1624.12-1624.58" - wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:1636.5-1636.46" - wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:1635.12-1635.54" - wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:1631.12-1631.58" - wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:1638.12-1638.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:1639.12-1639.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:1640.12-1640.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:1641.12-1641.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:1643.12-1643.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:1644.12-1644.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:1645.12-1645.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:1646.12-1646.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:1600.5-1600.48" - wire $1\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:1601.5-1601.47" - wire $1\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:1602.11-1602.61" - wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:1599.5-1599.48" - wire $1\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:1598.5-1598.48" - wire $1\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1603.5-1603.50" - wire $1\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:1608.11-1608.47" - wire width 8 $1\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:1642.5-1642.43" - wire $1\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:1565.11-1565.48" - wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:1941.11-1941.87" - wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:1942.5-1942.84" - wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:1570.12-1570.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:1566.12-1566.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:1577.12-1577.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:1573.12-1573.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:1584.12-1584.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:1580.12-1580.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:1591.12-1591.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:1587.12-1587.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:1594.12-1594.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:1933.12-1933.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:1934.5-1934.88" - wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:1595.12-1595.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:1935.12-1935.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:1936.5-1936.88" - wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:1596.12-1596.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:1937.12-1937.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:1938.5-1938.88" - wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:1597.12-1597.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:1939.12-1939.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:1940.5-1940.88" - wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:1556.5-1556.49" - wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1563.5-1563.50" - wire $1\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:1564.11-1564.64" - wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:1561.5-1561.51" - wire $1\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:1560.5-1560.51" - wire $1\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:1552.11-1552.47" - wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:1510.11-1510.51" - wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:1653.12-1653.42" - wire width 32 $1\main_sdcore_data_count[31:0] - attribute \src "ls180.v:1951.12-1951.65" - wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:1952.5-1952.60" - wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:1654.5-1654.33" - wire $1\main_sdcore_data_done[0:0] - attribute \src "ls180.v:1947.5-1947.56" - wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:1948.5-1948.59" - wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:1655.5-1655.34" - wire $1\main_sdcore_data_error[0:0] - attribute \src "ls180.v:1957.5-1957.57" - wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:1958.5-1958.60" - wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:1656.5-1656.36" - wire $1\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:1959.5-1959.59" - wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:1960.5-1960.62" - wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:1801.11-1801.48" - wire width 3 $1\main_sdmem2block_converter_mux[2:0] - attribute \src "ls180.v:1799.11-1799.64" - wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:1775.5-1775.40" - wire $1\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:1774.12-1774.53" - wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:1773.12-1773.45" - wire width 64 $1\main_sdmem2block_dma_data[63:0] - attribute \src "ls180.v:1969.12-1969.75" - wire width 64 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - attribute \src "ls180.v:1970.5-1970.70" - wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1780.5-1780.44" - wire $1\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:1779.5-1779.42" - wire $1\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:1778.5-1778.47" - wire $1\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:1777.5-1777.42" - wire $1\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:1776.12-1776.55" - wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:1783.5-1783.40" - wire $1\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:1782.5-1782.45" - wire $1\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:1787.12-1787.47" - wire width 32 $1\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:1973.12-1973.87" - wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:1974.5-1974.82" - wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:1766.5-1766.42" - wire $1\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:1767.12-1767.61" - wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:1765.5-1765.43" - wire $1\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:1764.5-1764.43" - wire $1\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1771.5-1771.44" - wire $1\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:1772.12-1772.60" - wire width 64 $1\main_sdmem2block_dma_source_payload_data[63:0] - attribute \src "ls180.v:1768.5-1768.45" - wire $1\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:1828.11-1828.47" - wire width 5 $1\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:1825.11-1825.45" - wire width 6 $1\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:1827.11-1827.47" - wire width 5 $1\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1829.11-1829.50" - wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1209.5-1209.35" - wire $1\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:1212.5-1212.35" - wire $1\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:1213.5-1213.36" - wire $1\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:1211.11-1211.41" - wire width 9 $1\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:1207.5-1207.33" - wire $1\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:1206.11-1206.46" - wire width 9 $1\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:1315.5-1315.49" - wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:1316.5-1316.48" - wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:1317.11-1317.62" - wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1313.5-1313.49" - wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:1300.11-1300.54" - wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1296.5-1296.55" - wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:1297.5-1297.54" - wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:1298.11-1298.68" - wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1299.11-1299.81" - wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1302.5-1302.53" - wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1318.5-1318.38" - wire $1\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:1913.5-1913.66" - wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:1914.5-1914.69" - wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:1288.5-1288.36" - wire $1\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:1283.5-1283.53" - wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:1270.11-1270.39" - wire width 8 $1\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:1909.11-1909.67" - wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:1910.5-1910.64" - wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1255.5-1255.48" - wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1256.5-1256.50" - wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1257.5-1257.51" - wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1262.5-1262.37" - wire $1\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:1263.11-1263.53" - wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:1261.5-1261.38" - wire $1\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:1260.5-1260.38" - wire $1\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:1266.5-1266.39" - wire $1\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:1267.11-1267.53" - wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:1268.11-1268.55" - wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:1265.5-1265.40" - wire $1\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:1264.5-1264.40" - wire $1\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:1269.12-1269.48" - wire width 32 $1\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:1911.12-1911.71" - wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:1912.5-1912.66" - wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:1242.11-1242.39" - wire width 8 $1\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:1905.11-1905.66" - wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:1906.5-1906.63" - wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:1241.5-1241.32" - wire $1\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:1232.5-1232.48" - wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1233.5-1233.50" - wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1234.5-1234.51" - wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1239.5-1239.37" - wire $1\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:1240.11-1240.51" - wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:1238.5-1238.38" - wire $1\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:1237.5-1237.38" - wire $1\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:1426.11-1426.41" - wire width 10 $1\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:1925.11-1925.70" - wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:1926.5-1926.66" - wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:1471.5-1471.51" - wire $1\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:1472.5-1472.50" - wire $1\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:1473.11-1473.64" - wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:1469.5-1469.51" - wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:1456.5-1456.50" - wire $1\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1452.5-1452.57" - wire $1\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:1453.5-1453.56" - wire $1\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:1454.11-1454.70" - wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:1455.11-1455.83" - wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:1458.5-1458.55" - wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1474.5-1474.40" - wire $1\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:1929.5-1929.69" - wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:1930.5-1930.72" - wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:1444.5-1444.38" - wire $1\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:1439.5-1439.55" - wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1409.5-1409.49" - wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1416.5-1416.38" - wire $1\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:1417.11-1417.61" - wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:1415.5-1415.39" - wire $1\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:1414.5-1414.39" - wire $1\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1421.5-1421.40" - wire $1\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:1422.11-1422.54" - wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:1423.11-1423.56" - wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:1419.5-1419.41" - wire $1\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:1418.5-1418.41" - wire $1\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:1424.5-1424.33" - wire $1\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:1425.12-1425.49" - wire width 32 $1\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:1927.12-1927.73" - wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:1928.5-1928.68" - wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:1334.11-1334.40" - wire width 8 $1\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:1921.11-1921.61" - wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:1922.5-1922.58" - wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1393.5-1393.50" - wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:1394.5-1394.49" - wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:1395.11-1395.63" - wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1391.5-1391.50" - wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:1378.11-1378.55" - wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1374.5-1374.56" - wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:1375.5-1375.55" - wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:1376.11-1376.69" - wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1377.11-1377.82" - wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1380.5-1380.54" - wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1396.5-1396.39" - wire $1\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:1917.5-1917.66" - wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:1918.5-1918.69" - wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:1366.5-1366.37" - wire $1\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:1361.5-1361.54" - wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:1348.5-1348.34" - wire $1\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1323.5-1323.49" - wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1326.11-1326.58" - wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1327.5-1327.53" - wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1330.5-1330.39" - wire $1\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:1331.5-1331.38" - wire $1\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:1332.11-1332.52" - wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:1329.5-1329.39" - wire $1\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:1328.5-1328.39" - wire $1\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:1346.5-1346.34" - wire $1\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:1333.5-1333.33" - wire $1\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:1347.5-1347.34" - wire $1\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:1227.11-1227.39" - wire width 8 $1\main_sdphy_init_count[7:0] - attribute \src "ls180.v:1901.11-1901.66" - wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:1902.5-1902.63" - wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1222.5-1222.48" - wire $1\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1223.5-1223.50" - wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1224.5-1224.51" - wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1225.11-1225.57" - wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1226.5-1226.52" - wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1476.5-1476.35" - wire $1\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:1479.11-1479.42" - wire width 4 $1\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:421.5-421.33" - wire $1\main_sdram_address_re[0:0] - attribute \src "ls180.v:420.12-420.46" - wire width 13 $1\main_sdram_address_storage[12:0] - attribute \src "ls180.v:423.5-423.34" - wire $1\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:422.11-422.45" - wire width 2 $1\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:519.5-519.50" - wire $1\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:541.11-541.70" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:538.11-538.68" - wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:540.11-540.70" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:542.11-542.73" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:565.5-565.59" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:566.5-566.58" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:568.12-568.74" - wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:567.5-567.64" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:563.5-563.59" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:511.12-511.57" - wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:513.5-513.51" - wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:516.5-516.54" - wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:517.5-517.55" - wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:518.5-518.56" - wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:514.5-514.51" - wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:515.5-515.50" - wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:510.5-510.45" - wire $1\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:509.5-509.45" - wire $1\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:508.5-508.47" - wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\ram_bus_ram_bus_ack[0:0] + attribute \src "ls180.v:240.5-240.31" + wire $0\ram_bus_ram_bus_err[0:0] + attribute \src "ls180.v:1722.1-1728.4" + wire width 4 $0\ram_we[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\rddata_en[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\regs0[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\regs1[0:0] + attribute \src "ls180.v:978.5-978.17" + wire $0\reset[0:0] + attribute \src "ls180.v:3435.1-3451.4" + wire $0\rhs_array_muxed0[0:0] + attribute \src "ls180.v:3656.1-3672.4" + wire $0\rhs_array_muxed10[0:0] + attribute \src "ls180.v:3673.1-3689.4" + wire $0\rhs_array_muxed11[0:0] + attribute \src "ls180.v:3741.1-3748.4" + wire width 22 $0\rhs_array_muxed12[21:0] + attribute \src "ls180.v:3749.1-3756.4" + wire $0\rhs_array_muxed13[0:0] + attribute \src "ls180.v:3757.1-3764.4" + wire $0\rhs_array_muxed14[0:0] + attribute \src "ls180.v:3765.1-3772.4" + wire width 22 $0\rhs_array_muxed15[21:0] + attribute \src "ls180.v:3773.1-3780.4" + wire $0\rhs_array_muxed16[0:0] + attribute \src "ls180.v:3781.1-3788.4" + wire $0\rhs_array_muxed17[0:0] + attribute \src "ls180.v:3789.1-3796.4" + wire width 22 $0\rhs_array_muxed18[21:0] + attribute \src "ls180.v:3797.1-3804.4" + wire $0\rhs_array_muxed19[0:0] + attribute \src "ls180.v:3452.1-3468.4" + wire width 13 $0\rhs_array_muxed1[12:0] + attribute \src "ls180.v:3805.1-3812.4" + wire $0\rhs_array_muxed20[0:0] + attribute \src "ls180.v:3813.1-3820.4" + wire width 22 $0\rhs_array_muxed21[21:0] + attribute \src "ls180.v:3821.1-3828.4" + wire $0\rhs_array_muxed22[0:0] + attribute \src "ls180.v:3829.1-3836.4" + wire $0\rhs_array_muxed23[0:0] + attribute \src "ls180.v:3837.1-3850.4" + wire width 30 $0\rhs_array_muxed24[29:0] + attribute \src "ls180.v:3851.1-3864.4" + wire width 32 $0\rhs_array_muxed25[31:0] + attribute \src "ls180.v:3865.1-3878.4" + wire width 4 $0\rhs_array_muxed26[3:0] + attribute \src "ls180.v:3879.1-3892.4" + wire $0\rhs_array_muxed27[0:0] + attribute \src "ls180.v:3893.1-3906.4" + wire $0\rhs_array_muxed28[0:0] + attribute \src "ls180.v:3907.1-3920.4" + wire $0\rhs_array_muxed29[0:0] + attribute \src "ls180.v:3469.1-3485.4" + wire width 2 $0\rhs_array_muxed2[1:0] + attribute \src "ls180.v:3921.1-3934.4" + wire width 3 $0\rhs_array_muxed30[2:0] + attribute \src "ls180.v:3935.1-3948.4" + wire width 2 $0\rhs_array_muxed31[1:0] + attribute \src "ls180.v:3486.1-3502.4" + wire $0\rhs_array_muxed3[0:0] + attribute \src "ls180.v:3503.1-3519.4" + wire $0\rhs_array_muxed4[0:0] + attribute \src "ls180.v:3520.1-3536.4" + wire $0\rhs_array_muxed5[0:0] + attribute \src "ls180.v:3588.1-3604.4" + wire $0\rhs_array_muxed6[0:0] + attribute \src "ls180.v:3605.1-3621.4" + wire width 13 $0\rhs_array_muxed7[12:0] + attribute \src "ls180.v:3622.1-3638.4" + wire width 2 $0\rhs_array_muxed8[1:0] + attribute \src "ls180.v:3639.1-3655.4" + wire $0\rhs_array_muxed9[0:0] + attribute \src "ls180.v:2897.1-2902.4" + wire $0\rx_clear[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 4 $0\rx_fifo_consume[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 5 $0\rx_fifo_level0[4:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 4 $0\rx_fifo_produce[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\rx_fifo_readable[0:0] + attribute \src "ls180.v:960.5-960.27" + wire $0\rx_fifo_replace[0:0] + attribute \src "ls180.v:2955.1-2962.4" + wire width 4 $0\rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\rx_old_trigger[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\rx_pending[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_address_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 13 $0\sdram_address_storage[12:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_baddress_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 2 $0\sdram_baddress_storage[1:0] + attribute \src "ls180.v:1940.1-1947.4" + wire $0\sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 4 $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:445.5-445.59" + wire $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:428.5-428.62" + wire $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:429.5-429.61" + wire $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:1962.1-1969.4" + wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 22 $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:1929.1-1936.4" + wire width 13 $0\sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:1978.1-2071.4" + wire $0\sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:1978.1-2071.4" + wire $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:1978.1-2071.4" + wire $0\sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:1978.1-2071.4" + wire $0\sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:1978.1-2071.4" + wire $0\sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:1978.1-2071.4" + wire $0\sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:2627.1-2635.4" + wire $0\sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:1978.1-2071.4" + wire $0\sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:1978.1-2071.4" + wire $0\sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:1978.1-2071.4" + wire $0\sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:1978.1-2071.4" + wire $0\sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 13 $0\sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:1978.1-2071.4" + wire $0\sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:1978.1-2071.4" + wire $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:1978.1-2071.4" + wire $0\sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:487.32-487.71" + wire $0\sdram_bankmachine0_trascon_ready[0:0] + attribute \src "ls180.v:485.32-485.70" + wire $0\sdram_bankmachine0_trccon_ready[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:2097.1-2104.4" + wire $0\sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 4 $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:527.5-527.59" + wire $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:510.5-510.62" + wire $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:511.5-511.61" + wire $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:2119.1-2126.4" + wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 22 $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:2086.1-2093.4" + wire width 13 $0\sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:2135.1-2228.4" + wire $0\sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:2135.1-2228.4" + wire $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:2135.1-2228.4" + wire $0\sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:2135.1-2228.4" + wire $0\sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:2135.1-2228.4" + wire $0\sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:2135.1-2228.4" + wire $0\sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:2636.1-2644.4" + wire $0\sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:2135.1-2228.4" + wire $0\sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:2135.1-2228.4" + wire $0\sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:2135.1-2228.4" + wire $0\sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:2135.1-2228.4" + wire $0\sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 13 $0\sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:2135.1-2228.4" + wire $0\sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:2135.1-2228.4" + wire $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:2135.1-2228.4" + wire $0\sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:569.32-569.71" + wire $0\sdram_bankmachine1_trascon_ready[0:0] + attribute \src "ls180.v:567.32-567.70" + wire $0\sdram_bankmachine1_trccon_ready[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:2254.1-2261.4" + wire $0\sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 4 $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:609.5-609.59" + wire $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:592.5-592.62" + wire $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:593.5-593.61" + wire $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:2276.1-2283.4" + wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 22 $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:2243.1-2250.4" + wire width 13 $0\sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:2292.1-2385.4" + wire $0\sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:2292.1-2385.4" + wire $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:2292.1-2385.4" + wire $0\sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:2292.1-2385.4" + wire $0\sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:2292.1-2385.4" + wire $0\sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:2292.1-2385.4" + wire $0\sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:2645.1-2653.4" + wire $0\sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:2292.1-2385.4" + wire $0\sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:2292.1-2385.4" + wire $0\sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:2292.1-2385.4" + wire $0\sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:2292.1-2385.4" + wire $0\sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 13 $0\sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:2292.1-2385.4" + wire $0\sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:2292.1-2385.4" + wire $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:2292.1-2385.4" + wire $0\sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:651.32-651.71" + wire $0\sdram_bankmachine2_trascon_ready[0:0] + attribute \src "ls180.v:649.32-649.70" + wire $0\sdram_bankmachine2_trccon_ready[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:2411.1-2418.4" + wire $0\sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 4 $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:691.5-691.59" + wire $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:674.5-674.62" + wire $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:675.5-675.61" + wire $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:2433.1-2440.4" + wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 22 $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:2400.1-2407.4" + wire width 13 $0\sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:2449.1-2542.4" + wire $0\sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:2449.1-2542.4" + wire $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:2449.1-2542.4" + wire $0\sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:2449.1-2542.4" + wire $0\sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:2449.1-2542.4" + wire $0\sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:2449.1-2542.4" + wire $0\sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:2654.1-2662.4" + wire $0\sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:2449.1-2542.4" + wire $0\sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:2449.1-2542.4" + wire $0\sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:2449.1-2542.4" + wire $0\sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:2449.1-2542.4" + wire $0\sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 13 $0\sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:2449.1-2542.4" + wire $0\sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:2449.1-2542.4" + wire $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:2449.1-2542.4" + wire $0\sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:733.32-733.71" + wire $0\sdram_bankmachine3_trascon_ready[0:0] + attribute \src "ls180.v:731.32-731.70" + wire $0\sdram_bankmachine3_trccon_ready[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:2576.1-2581.4" + wire $0\sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:2582.1-2587.4" + wire $0\sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:2588.1-2593.4" + wire $0\sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:741.5-741.38" + wire $0\sdram_choose_cmd_cmd_ready[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 2 $0\sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:2562.1-2568.4" + wire width 4 $0\sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:739.5-739.43" + wire $0\sdram_choose_cmd_want_activates[0:0] + attribute \src "ls180.v:738.5-738.38" + wire $0\sdram_choose_cmd_want_cmds[0:0] + attribute \src "ls180.v:736.5-736.39" + wire $0\sdram_choose_cmd_want_reads[0:0] + attribute \src "ls180.v:737.5-737.40" + wire $0\sdram_choose_cmd_want_writes[0:0] + attribute \src "ls180.v:2609.1-2614.4" + wire $0\sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:2615.1-2620.4" + wire $0\sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:2621.1-2626.4" + wire $0\sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:2667.1-2739.4" + wire $0\sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 2 $0\sdram_choose_req_grant[1:0] + attribute \src "ls180.v:2595.1-2601.4" + wire width 4 $0\sdram_choose_req_valids[3:0] + attribute \src "ls180.v:2667.1-2739.4" + wire $0\sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:2667.1-2739.4" + wire $0\sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:2667.1-2739.4" + wire $0\sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:1884.1-1914.4" + wire $0\sdram_cmd_last[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 13 $0\sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 2 $0\sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:389.5-389.37" + wire $0\sdram_cmd_payload_is_read[0:0] + attribute \src "ls180.v:390.5-390.38" + wire $0\sdram_cmd_payload_is_write[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:2667.1-2739.4" + wire $0\sdram_cmd_ready[0:0] + attribute \src "ls180.v:1884.1-1914.4" + wire $0\sdram_cmd_valid[0:0] + attribute \src "ls180.v:325.5-325.33" + wire $0\sdram_command_issue_w[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_command_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 6 $0\sdram_command_storage[5:0] + attribute \src "ls180.v:374.5-374.30" + wire $0\sdram_dfi_p0_act_n[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 13 $0\sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 2 $0\sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:2667.1-2739.4" + wire $0\sdram_en0[0:0] + attribute \src "ls180.v:2667.1-2739.4" + wire $0\sdram_en1[0:0] + attribute \src "ls180.v:2763.1-2776.4" + wire width 16 $0\sdram_interface_wdata[15:0] + attribute \src "ls180.v:2763.1-2776.4" + wire width 2 $0\sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:275.5-275.31" + wire $0\sdram_inti_p0_act_n[0:0] + attribute \src "ls180.v:1825.1-1841.4" + wire $0\sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:1825.1-1841.4" + wire $0\sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:1825.1-1841.4" + wire $0\sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:1767.1-1821.4" + wire width 16 $0\sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:1767.1-1821.4" + wire $0\sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:1825.1-1841.4" + wire $0\sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:1767.1-1821.4" + wire $0\sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:1767.1-1821.4" + wire width 13 $0\sdram_master_p0_address[12:0] + attribute \src "ls180.v:1767.1-1821.4" + wire width 2 $0\sdram_master_p0_bank[1:0] + attribute \src "ls180.v:1767.1-1821.4" + wire $0\sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:1767.1-1821.4" + wire $0\sdram_master_p0_cke[0:0] + attribute \src "ls180.v:1767.1-1821.4" + wire $0\sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:1767.1-1821.4" + wire $0\sdram_master_p0_odt[0:0] + attribute \src "ls180.v:1767.1-1821.4" + wire $0\sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:1767.1-1821.4" + wire $0\sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:1767.1-1821.4" + wire $0\sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:1767.1-1821.4" + wire $0\sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:1767.1-1821.4" + wire width 16 $0\sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:1767.1-1821.4" + wire $0\sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:1767.1-1821.4" + wire width 2 $0\sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:772.12-772.31" + wire width 13 $0\sdram_nop_a[12:0] + attribute \src "ls180.v:773.11-773.30" + wire width 2 $0\sdram_nop_ba[1:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_postponer_count[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_postponer_req_o[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_sequencer_count[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 4 $0\sdram_sequencer_counter[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_sequencer_done1[0:0] + attribute \src "ls180.v:1884.1-1914.4" + wire $0\sdram_sequencer_start0[0:0] + attribute \src "ls180.v:1767.1-1821.4" + wire width 16 $0\sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:1767.1-1821.4" + wire $0\sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 16 $0\sdram_status[15:0] + attribute \src "ls180.v:775.5-775.26" + wire $0\sdram_steerer0[0:0] + attribute \src "ls180.v:776.5-776.26" + wire $0\sdram_steerer1[0:0] + attribute \src "ls180.v:2667.1-2739.4" + wire width 2 $0\sdram_steerer_sel[1:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 4 $0\sdram_storage[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_tccdcon_count[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:780.32-780.58" + wire $0\sdram_tfawcon_ready[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 5 $0\sdram_time0[4:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 4 $0\sdram_time1[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 10 $0\sdram_timer_count1[9:0] + attribute \src "ls180.v:778.32-778.58" + wire $0\sdram_trrdcon_ready[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\sdram_twtrcon_count[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\sdram_wrdata_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 16 $0\sdram_wrdata_storage[15:0] + attribute \src "ls180.v:1978.1-2071.4" + wire width 3 $0\subfragments_bankmachine0_next_state[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\subfragments_bankmachine0_state[2:0] + attribute \src "ls180.v:2135.1-2228.4" + wire width 3 $0\subfragments_bankmachine1_next_state[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\subfragments_bankmachine1_state[2:0] + attribute \src "ls180.v:2292.1-2385.4" + wire width 3 $0\subfragments_bankmachine2_next_state[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\subfragments_bankmachine2_state[2:0] + attribute \src "ls180.v:2449.1-2542.4" + wire width 3 $0\subfragments_bankmachine3_next_state[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\subfragments_bankmachine3_state[2:0] + attribute \src "ls180.v:1532.1-1578.4" + wire $0\subfragments_converter0_next_state[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\subfragments_converter0_state[0:0] + attribute \src "ls180.v:1592.1-1638.4" + wire $0\subfragments_converter1_next_state[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\subfragments_converter1_state[0:0] + attribute \src "ls180.v:1652.1-1698.4" + wire $0\subfragments_converter2_next_state[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\subfragments_converter2_state[0:0] + attribute \src "ls180.v:1044.5-1044.32" + wire $0\subfragments_locked0[0:0] + attribute \src "ls180.v:1045.5-1045.32" + wire $0\subfragments_locked1[0:0] + attribute \src "ls180.v:1046.5-1046.32" + wire $0\subfragments_locked2[0:0] + attribute \src "ls180.v:1047.5-1047.32" + wire $0\subfragments_locked3[0:0] + attribute \src "ls180.v:2667.1-2739.4" + wire width 3 $0\subfragments_multiplexer_next_state[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 3 $0\subfragments_multiplexer_state[2:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\subfragments_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\subfragments_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\subfragments_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\subfragments_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\subfragments_new_master_wdata_ready[0:0] + attribute \src "ls180.v:2795.1-2841.4" + wire $0\subfragments_next_state[0:0] + attribute \src "ls180.v:1884.1-1914.4" + wire width 2 $0\subfragments_refresher_next_state[1:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 2 $0\subfragments_refresher_state[1:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\subfragments_state[0:0] + attribute \src "ls180.v:3537.1-3553.4" + wire $0\t_array_muxed0[0:0] + attribute \src "ls180.v:3554.1-3570.4" + wire $0\t_array_muxed1[0:0] + attribute \src "ls180.v:3571.1-3587.4" + wire $0\t_array_muxed2[0:0] + attribute \src "ls180.v:3690.1-3706.4" + wire $0\t_array_muxed3[0:0] + attribute \src "ls180.v:3707.1-3723.4" + wire $0\t_array_muxed4[0:0] + attribute \src "ls180.v:3724.1-3740.4" + wire $0\t_array_muxed5[0:0] + attribute \src "ls180.v:2886.1-2891.4" + wire $0\tx_clear[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 4 $0\tx_fifo_consume[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 5 $0\tx_fifo_level0[4:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 4 $0\tx_fifo_produce[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\tx_fifo_readable[0:0] + attribute \src "ls180.v:923.5-923.27" + wire $0\tx_fifo_replace[0:0] + attribute \src "ls180.v:906.5-906.30" + wire $0\tx_fifo_sink_first[0:0] + attribute \src "ls180.v:907.5-907.29" + wire $0\tx_fifo_sink_last[0:0] + attribute \src "ls180.v:2925.1-2932.4" + wire width 4 $0\tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\tx_old_trigger[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\tx_pending[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 32 $0\uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 32 $0\uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\uart_phy_re[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 4 $0\uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\uart_phy_rx_busy[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\uart_phy_rx_r[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\uart_phy_rx_reg[7:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\uart_phy_sink_ready[0:0] + attribute \src "ls180.v:851.5-851.33" + wire $0\uart_phy_source_first[0:0] + attribute \src "ls180.v:852.5-852.32" + wire $0\uart_phy_source_last[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\uart_phy_source_valid[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 32 $0\uart_phy_storage[31:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 4 $0\uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\uart_phy_tx_busy[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire width 8 $0\uart_phy_tx_reg[7:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:2795.1-2841.4" + wire $0\wb_sdram_ack[0:0] + attribute \src "ls180.v:819.5-819.24" + wire $0\wb_sdram_err[0:0] + attribute \src "ls180.v:4285.1-5491.4" + wire $0\wdata_consumed[0:0] + attribute \src "ls180.v:5495.1-5505.4" + wire width 7 $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449 + attribute \src "ls180.v:5495.1-5505.4" + wire width 7 $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452 + attribute \src "ls180.v:5495.1-5505.4" + wire width 7 $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455 + attribute \src "ls180.v:5495.1-5505.4" + wire width 7 $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457 + attribute \src "ls180.v:5495.1-5505.4" + wire width 32 $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458 + attribute \src "ls180.v:5515.1-5525.4" + wire width 5 $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475 + attribute \src "ls180.v:5515.1-5525.4" + wire width 5 $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478 + attribute \src "ls180.v:5515.1-5525.4" + wire width 5 $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481 + attribute \src "ls180.v:5515.1-5525.4" + wire width 5 $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483 + attribute \src "ls180.v:5515.1-5525.4" + wire width 32 $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484 + attribute \src "ls180.v:5535.1-5539.4" + wire width 3 $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490 + attribute \src "ls180.v:5535.1-5539.4" + wire width 25 $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491 + attribute \src "ls180.v:5535.1-5539.4" + wire width 25 $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492 + attribute \src "ls180.v:5549.1-5553.4" + wire width 3 $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500 + attribute \src "ls180.v:5549.1-5553.4" + wire width 25 $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501 + attribute \src "ls180.v:5549.1-5553.4" + wire width 25 $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502 + attribute \src "ls180.v:5563.1-5567.4" + wire width 3 $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510 + attribute \src "ls180.v:5563.1-5567.4" + wire width 25 $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511 + attribute \src "ls180.v:5563.1-5567.4" + wire width 25 $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512 + attribute \src "ls180.v:5577.1-5581.4" + wire width 3 $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520 + attribute \src "ls180.v:5577.1-5581.4" + wire width 25 $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521 + attribute \src "ls180.v:5577.1-5581.4" + wire width 25 $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522 + attribute \src "ls180.v:5592.1-5596.4" + wire width 4 $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530 + attribute \src "ls180.v:5592.1-5596.4" + wire width 10 $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531 + attribute \src "ls180.v:5592.1-5596.4" + wire width 10 $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532 + attribute \src "ls180.v:5609.1-5613.4" + wire width 4 $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540 + attribute \src "ls180.v:5609.1-5613.4" + wire width 10 $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541 + attribute \src "ls180.v:5609.1-5613.4" + wire width 10 $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542 + attribute \src "ls180.v:1381.11-1381.30" + wire width 2 $1\array_muxed0[1:0] + attribute \src "ls180.v:1382.12-1382.32" + wire width 13 $1\array_muxed1[12:0] + attribute \src "ls180.v:1383.5-1383.24" + wire $1\array_muxed2[0:0] + attribute \src "ls180.v:1384.5-1384.24" + wire $1\array_muxed3[0:0] + attribute \src "ls180.v:1385.5-1385.24" + wire $1\array_muxed4[0:0] + attribute \src "ls180.v:1386.5-1386.24" + wire $1\array_muxed5[0:0] + attribute \src "ls180.v:1387.5-1387.24" + wire $1\array_muxed6[0:0] + attribute \src "ls180.v:832.5-832.24" + wire $1\cmd_consumed[0:0] + attribute \src "ls180.v:829.5-829.29" + wire $1\converter_counter[0:0] + attribute \src "ls180.v:1055.5-1055.53" + wire $1\converter_counter_subfragments_next_value[0:0] + attribute \src "ls180.v:1056.5-1056.56" + wire $1\converter_counter_subfragments_next_value_ce[0:0] + attribute \src "ls180.v:831.12-831.35" + wire width 32 $1\converter_dat_r[31:0] + attribute \src "ls180.v:828.5-828.26" + wire $1\converter_skip[0:0] + attribute \src "ls180.v:263.12-263.33" + wire width 16 $1\dfi_p0_rddata[15:0] + attribute \src "ls180.v:264.5-264.31" + wire $1\dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:999.12-999.25" + wire width 36 $1\dummy[35:0] + attribute \src "ls180.v:997.11-997.26" + wire width 3 $1\eint_tmp[2:0] + attribute \src "ls180.v:887.11-887.40" + wire width 2 $1\eventmanager_pending_w[1:0] + attribute \src "ls180.v:889.5-889.27" + wire $1\eventmanager_re[0:0] + attribute \src "ls180.v:883.11-883.39" + wire width 2 $1\eventmanager_status_w[1:0] + attribute \src "ls180.v:888.11-888.38" + wire width 2 $1\eventmanager_storage[1:0] + attribute \src "ls180.v:980.5-980.23" + wire $1\gpio0_oe_re[0:0] + attribute \src "ls180.v:979.11-979.34" + wire width 8 $1\gpio0_oe_storage[7:0] + attribute \src "ls180.v:984.5-984.24" + wire $1\gpio0_out_re[0:0] + attribute \src "ls180.v:983.11-983.35" + wire width 8 $1\gpio0_out_storage[7:0] + attribute \src "ls180.v:985.11-985.35" + wire width 8 $1\gpio0_pads_gpio0i[7:0] + attribute \src "ls180.v:986.11-986.35" + wire width 8 $1\gpio0_pads_gpio0o[7:0] + attribute \src "ls180.v:987.11-987.36" + wire width 8 $1\gpio0_pads_gpio0oe[7:0] + attribute \src "ls180.v:981.11-981.30" + wire width 8 $1\gpio0_status[7:0] + attribute \src "ls180.v:989.5-989.23" + wire $1\gpio1_oe_re[0:0] + attribute \src "ls180.v:988.11-988.34" + wire width 8 $1\gpio1_oe_storage[7:0] + attribute \src "ls180.v:993.5-993.24" + wire $1\gpio1_out_re[0:0] + attribute \src "ls180.v:992.11-992.35" + wire width 8 $1\gpio1_out_storage[7:0] + attribute \src "ls180.v:994.11-994.35" + wire width 8 $1\gpio1_pads_gpio1i[7:0] + attribute \src "ls180.v:995.11-995.35" + wire width 8 $1\gpio1_pads_gpio1o[7:0] + attribute \src "ls180.v:996.11-996.36" + wire width 8 $1\gpio1_pads_gpio1oe[7:0] + attribute \src "ls180.v:990.11-990.30" + wire width 8 $1\gpio1_status[7:0] + attribute \src "ls180.v:1004.5-1004.18" + wire $1\i2c_re[0:0] + attribute \src "ls180.v:1003.11-1003.29" + wire width 3 $1\i2c_storage[2:0] + attribute \src "ls180.v:248.5-248.19" + wire $1\int_rst[0:0] + attribute \src "ls180.v:53.12-53.42" + wire width 32 $1\libresocsim_bus_errors[31:0] + attribute \src "ls180.v:155.5-155.42" + wire $1\libresocsim_converter0_counter[0:0] + attribute \src "ls180.v:1010.5-1010.77" + wire $1\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] + attribute \src "ls180.v:1011.5-1011.80" + wire $1\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] + attribute \src "ls180.v:157.12-157.48" + wire width 64 $1\libresocsim_converter0_dat_r[63:0] + attribute \src "ls180.v:154.5-154.39" + wire $1\libresocsim_converter0_skip[0:0] + attribute \src "ls180.v:170.5-170.42" + wire $1\libresocsim_converter1_counter[0:0] + attribute \src "ls180.v:1014.5-1014.77" + wire $1\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] + attribute \src "ls180.v:1015.5-1015.80" + wire $1\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] + attribute \src "ls180.v:172.12-172.48" + wire width 64 $1\libresocsim_converter1_dat_r[63:0] + attribute \src "ls180.v:169.5-169.39" + wire $1\libresocsim_converter1_skip[0:0] + attribute \src "ls180.v:185.5-185.42" + wire $1\libresocsim_converter2_counter[0:0] + attribute \src "ls180.v:1018.5-1018.77" + wire $1\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] + attribute \src "ls180.v:1019.5-1019.80" + wire $1\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] + attribute \src "ls180.v:187.12-187.48" + wire width 64 $1\libresocsim_converter2_dat_r[63:0] + attribute \src "ls180.v:184.5-184.39" + wire $1\libresocsim_converter2_skip[0:0] + attribute \src "ls180.v:1090.12-1090.43" + wire width 20 $1\libresocsim_count[19:0] + attribute \src "ls180.v:208.5-208.29" + wire $1\libresocsim_en_re[0:0] + attribute \src "ls180.v:207.5-207.34" + wire $1\libresocsim_en_storage[0:0] + attribute \src "ls180.v:1087.5-1087.29" + wire $1\libresocsim_error[0:0] + attribute \src "ls180.v:228.5-228.39" + wire $1\libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:227.5-227.44" + wire $1\libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:1084.11-1084.35" + wire width 2 $1\libresocsim_grant[1:0] + attribute \src "ls180.v:1094.11-1094.55" + wire width 8 $1\libresocsim_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:143.12-143.66" + wire width 30 $1\libresocsim_interface0_converted_interface_adr[29:0] + attribute \src "ls180.v:147.5-147.58" + wire $1\libresocsim_interface0_converted_interface_cyc[0:0] + attribute \src "ls180.v:144.12-144.68" + wire width 32 $1\libresocsim_interface0_converted_interface_dat_w[31:0] + attribute \src "ls180.v:146.11-146.64" + wire width 4 $1\libresocsim_interface0_converted_interface_sel[3:0] + attribute \src "ls180.v:148.5-148.58" + wire $1\libresocsim_interface0_converted_interface_stb[0:0] + attribute \src "ls180.v:150.5-150.57" + wire $1\libresocsim_interface0_converted_interface_we[0:0] + attribute \src "ls180.v:1135.11-1135.55" + wire width 8 $1\libresocsim_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:158.12-158.66" + wire width 30 $1\libresocsim_interface1_converted_interface_adr[29:0] + attribute \src "ls180.v:162.5-162.58" + wire $1\libresocsim_interface1_converted_interface_cyc[0:0] + attribute \src "ls180.v:159.12-159.68" + wire width 32 $1\libresocsim_interface1_converted_interface_dat_w[31:0] + attribute \src "ls180.v:161.11-161.64" + wire width 4 $1\libresocsim_interface1_converted_interface_sel[3:0] + attribute \src "ls180.v:163.5-163.58" + wire $1\libresocsim_interface1_converted_interface_stb[0:0] + attribute \src "ls180.v:165.5-165.57" + wire $1\libresocsim_interface1_converted_interface_we[0:0] + attribute \src "ls180.v:1152.11-1152.55" + wire width 8 $1\libresocsim_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:173.12-173.66" + wire width 30 $1\libresocsim_interface2_converted_interface_adr[29:0] + attribute \src "ls180.v:177.5-177.58" + wire $1\libresocsim_interface2_converted_interface_cyc[0:0] + attribute \src "ls180.v:174.12-174.68" + wire width 32 $1\libresocsim_interface2_converted_interface_dat_w[31:0] + attribute \src "ls180.v:176.11-176.64" + wire width 4 $1\libresocsim_interface2_converted_interface_sel[3:0] + attribute \src "ls180.v:178.5-178.58" + wire $1\libresocsim_interface2_converted_interface_stb[0:0] + attribute \src "ls180.v:180.5-180.57" + wire $1\libresocsim_interface2_converted_interface_we[0:0] + attribute \src "ls180.v:1169.11-1169.55" + wire width 8 $1\libresocsim_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1182.11-1182.55" + wire width 8 $1\libresocsim_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1223.11-1223.55" + wire width 8 $1\libresocsim_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1288.11-1288.55" + wire width 8 $1\libresocsim_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1313.11-1313.55" + wire width 8 $1\libresocsim_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:122.12-122.65" + wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] + attribute \src "ls180.v:123.12-123.66" + wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] + attribute \src "ls180.v:128.12-128.66" + wire width 13 $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] + attribute \src "ls180.v:137.11-137.65" + wire width 2 $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] + attribute \src "ls180.v:134.5-134.62" + wire $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] + attribute \src "ls180.v:136.5-136.60" + wire $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] + attribute \src "ls180.v:139.5-139.62" + wire $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] + attribute \src "ls180.v:135.5-135.61" + wire $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] + attribute \src "ls180.v:138.11-138.65" + wire width 2 $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] + attribute \src "ls180.v:130.12-130.69" + wire width 16 $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] + attribute \src "ls180.v:131.5-131.62" + wire $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] + attribute \src "ls180.v:133.5-133.62" + wire $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] + attribute \src "ls180.v:132.5-132.61" + wire $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] + attribute \src "ls180.v:115.5-115.58" + wire $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] + attribute \src "ls180.v:62.5-62.41" + wire $1\libresocsim_libresoc_dbus_ack[0:0] + attribute \src "ls180.v:71.5-71.41" + wire $1\libresocsim_libresoc_ibus_ack[0:0] + attribute \src "ls180.v:55.12-55.50" + wire width 16 $1\libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:102.5-102.44" + wire $1\libresocsim_libresoc_jtag_wb_ack[0:0] + attribute \src "ls180.v:1057.12-1057.47" + wire width 14 $1\libresocsim_libresocsim_adr[13:0] + attribute \src "ls180.v:1339.12-1339.71" + wire width 14 $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] + attribute \src "ls180.v:1340.5-1340.66" + wire $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] + attribute \src "ls180.v:1059.11-1059.47" + wire width 8 $1\libresocsim_libresocsim_dat_w[7:0] + attribute \src "ls180.v:1337.11-1337.71" + wire width 8 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] + attribute \src "ls180.v:1338.5-1338.68" + wire $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] + attribute \src "ls180.v:1058.5-1058.38" + wire $1\libresocsim_libresocsim_we[0:0] + attribute \src "ls180.v:1341.5-1341.62" + wire $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] + attribute \src "ls180.v:1342.5-1342.65" + wire $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] + attribute \src "ls180.v:1067.5-1067.48" + wire $1\libresocsim_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:1063.12-1063.58" + wire width 32 $1\libresocsim_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:204.5-204.31" + wire $1\libresocsim_load_re[0:0] + attribute \src "ls180.v:203.12-203.44" + wire width 32 $1\libresocsim_load_storage[31:0] + attribute \src "ls180.v:1336.11-1336.40" + wire width 2 $1\libresocsim_next_state[1:0] + attribute \src "ls180.v:194.5-194.35" + wire $1\libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:206.5-206.33" + wire $1\libresocsim_reload_re[0:0] + attribute \src "ls180.v:205.12-205.46" + wire width 32 $1\libresocsim_reload_storage[31:0] + attribute \src "ls180.v:46.5-46.32" + wire $1\libresocsim_reset_re[0:0] + attribute \src "ls180.v:45.5-45.37" + wire $1\libresocsim_reset_storage[0:0] + attribute \src "ls180.v:48.5-48.34" + wire $1\libresocsim_scratch_re[0:0] + attribute \src "ls180.v:47.12-47.55" + wire width 32 $1\libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:1078.5-1078.34" + wire $1\libresocsim_shared_ack[0:0] + attribute \src "ls180.v:1074.12-1074.44" + wire width 32 $1\libresocsim_shared_dat_r[31:0] + attribute \src "ls180.v:1085.11-1085.39" + wire width 6 $1\libresocsim_slave_sel[5:0] + attribute \src "ls180.v:1086.11-1086.41" + wire width 6 $1\libresocsim_slave_sel_r[5:0] + attribute \src "ls180.v:1335.11-1335.35" + wire width 2 $1\libresocsim_state[1:0] + attribute \src "ls180.v:210.5-210.39" + wire $1\libresocsim_update_value_re[0:0] + attribute \src "ls180.v:209.5-209.44" + wire $1\libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:229.12-229.37" + wire width 32 $1\libresocsim_value[31:0] + attribute \src "ls180.v:211.12-211.44" + wire width 32 $1\libresocsim_value_status[31:0] + attribute \src "ls180.v:201.11-201.32" + wire width 4 $1\libresocsim_we[3:0] + attribute \src "ls180.v:217.5-217.34" + wire $1\libresocsim_zero_clear[0:0] + attribute \src "ls180.v:218.5-218.40" + wire $1\libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:215.5-215.36" + wire $1\libresocsim_zero_pending[0:0] + attribute \src "ls180.v:820.12-820.35" + wire width 30 $1\litedram_wb_adr[29:0] + attribute \src "ls180.v:824.5-824.27" + wire $1\litedram_wb_cyc[0:0] + attribute \src "ls180.v:821.12-821.37" + wire width 16 $1\litedram_wb_dat_w[15:0] + attribute \src "ls180.v:823.11-823.33" + wire width 2 $1\litedram_wb_sel[1:0] + attribute \src "ls180.v:825.5-825.27" + wire $1\litedram_wb_stb[0:0] + attribute \src "ls180.v:827.5-827.26" + wire $1\litedram_wb_we[0:0] + attribute \src "ls180.v:236.5-236.31" + wire $1\ram_bus_ram_bus_ack[0:0] + attribute \src "ls180.v:243.11-243.24" + wire width 4 $1\ram_we[3:0] + attribute \src "ls180.v:265.11-265.27" + wire width 3 $1\rddata_en[2:0] + attribute \src "ls180.v:1444.32-1444.44" + wire $1\regs0[0:0] + attribute \src "ls180.v:1445.32-1445.44" + wire $1\regs1[0:0] + attribute \src "ls180.v:1343.5-1343.28" + wire $1\rhs_array_muxed0[0:0] + attribute \src "ls180.v:1356.5-1356.29" + wire $1\rhs_array_muxed10[0:0] + attribute \src "ls180.v:1357.5-1357.29" + wire $1\rhs_array_muxed11[0:0] + attribute \src "ls180.v:1361.12-1361.37" + wire width 22 $1\rhs_array_muxed12[21:0] + attribute \src "ls180.v:1362.5-1362.29" + wire $1\rhs_array_muxed13[0:0] + attribute \src "ls180.v:1363.5-1363.29" + wire $1\rhs_array_muxed14[0:0] + attribute \src "ls180.v:1364.12-1364.37" + wire width 22 $1\rhs_array_muxed15[21:0] + attribute \src "ls180.v:1365.5-1365.29" + wire $1\rhs_array_muxed16[0:0] + attribute \src "ls180.v:1366.5-1366.29" + wire $1\rhs_array_muxed17[0:0] + attribute \src "ls180.v:1367.12-1367.37" + wire width 22 $1\rhs_array_muxed18[21:0] + attribute \src "ls180.v:1368.5-1368.29" + wire $1\rhs_array_muxed19[0:0] + attribute \src "ls180.v:1344.12-1344.36" + wire width 13 $1\rhs_array_muxed1[12:0] + attribute \src "ls180.v:1369.5-1369.29" + wire $1\rhs_array_muxed20[0:0] + attribute \src "ls180.v:1370.12-1370.37" + wire width 22 $1\rhs_array_muxed21[21:0] + attribute \src "ls180.v:1371.5-1371.29" + wire $1\rhs_array_muxed22[0:0] + attribute \src "ls180.v:1372.5-1372.29" + wire $1\rhs_array_muxed23[0:0] + attribute \src "ls180.v:1373.12-1373.37" + wire width 30 $1\rhs_array_muxed24[29:0] + attribute \src "ls180.v:1374.12-1374.37" + wire width 32 $1\rhs_array_muxed25[31:0] + attribute \src "ls180.v:1375.11-1375.35" + wire width 4 $1\rhs_array_muxed26[3:0] + attribute \src "ls180.v:1376.5-1376.29" + wire $1\rhs_array_muxed27[0:0] + attribute \src "ls180.v:1377.5-1377.29" + wire $1\rhs_array_muxed28[0:0] + attribute \src "ls180.v:1378.5-1378.29" + wire $1\rhs_array_muxed29[0:0] + attribute \src "ls180.v:1345.11-1345.34" + wire width 2 $1\rhs_array_muxed2[1:0] + attribute \src "ls180.v:1379.11-1379.35" + wire width 3 $1\rhs_array_muxed30[2:0] + attribute \src "ls180.v:1380.11-1380.35" + wire width 2 $1\rhs_array_muxed31[1:0] + attribute \src "ls180.v:1346.5-1346.28" + wire $1\rhs_array_muxed3[0:0] + attribute \src "ls180.v:1347.5-1347.28" + wire $1\rhs_array_muxed4[0:0] + attribute \src "ls180.v:1348.5-1348.28" + wire $1\rhs_array_muxed5[0:0] + attribute \src "ls180.v:1352.5-1352.28" + wire $1\rhs_array_muxed6[0:0] + attribute \src "ls180.v:1353.12-1353.36" + wire width 13 $1\rhs_array_muxed7[12:0] + attribute \src "ls180.v:1354.11-1354.34" + wire width 2 $1\rhs_array_muxed8[1:0] + attribute \src "ls180.v:1355.5-1355.28" + wire $1\rhs_array_muxed9[0:0] + attribute \src "ls180.v:878.5-878.20" + wire $1\rx_clear[0:0] + attribute \src "ls180.v:962.11-962.33" + wire width 4 $1\rx_fifo_consume[3:0] + attribute \src "ls180.v:959.11-959.32" + wire width 5 $1\rx_fifo_level0[4:0] + attribute \src "ls180.v:961.11-961.33" + wire width 4 $1\rx_fifo_produce[3:0] + attribute \src "ls180.v:952.5-952.28" + wire $1\rx_fifo_readable[0:0] + attribute \src "ls180.v:963.11-963.36" + wire width 4 $1\rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:879.5-879.26" + wire $1\rx_old_trigger[0:0] + attribute \src "ls180.v:876.5-876.22" + wire $1\rx_pending[0:0] + attribute \src "ls180.v:327.5-327.28" + wire $1\sdram_address_re[0:0] + attribute \src "ls180.v:326.12-326.41" + wire width 13 $1\sdram_address_storage[12:0] + attribute \src "ls180.v:329.5-329.29" + wire $1\sdram_baddress_re[0:0] + attribute \src "ls180.v:328.11-328.40" + wire width 2 $1\sdram_baddress_storage[1:0] + attribute \src "ls180.v:425.5-425.45" + wire $1\sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:447.11-447.65" + wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:444.11-444.63" + wire width 4 $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:446.11-446.65" + wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:448.11-448.68" + wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:471.5-471.54" + wire $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:472.5-472.53" + wire $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:474.12-474.69" + wire width 22 $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:473.5-473.59" + wire $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:469.5-469.54" + wire $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:417.12-417.52" + wire width 13 $1\sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:419.5-419.46" + wire $1\sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:422.5-422.49" + wire $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:423.5-423.50" + wire $1\sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:424.5-424.51" + wire $1\sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:420.5-420.46" + wire $1\sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:421.5-421.45" + wire $1\sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:416.5-416.40" + wire $1\sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:415.5-415.40" + wire $1\sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:414.5-414.42" + wire $1\sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:412.5-412.46" + wire $1\sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:411.5-411.46" + wire $1\sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:475.12-475.42" + wire width 13 $1\sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:479.5-479.40" + wire $1\sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:480.5-480.49" + wire $1\sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:478.5-478.39" + wire $1\sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:476.5-476.41" + wire $1\sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:483.11-483.50" + wire width 3 $1\sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:482.32-482.71" + wire $1\sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:507.5-507.45" + wire $1\sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:529.11-529.65" + wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:526.11-526.63" + wire width 4 $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:528.11-528.65" + wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:530.11-530.68" + wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:553.5-553.54" + wire $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:554.5-554.53" + wire $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:556.12-556.69" + wire width 22 $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:555.5-555.59" + wire $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:551.5-551.54" + wire $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:499.12-499.52" + wire width 13 $1\sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:501.5-501.46" + wire $1\sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:504.5-504.49" + wire $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:505.5-505.50" + wire $1\sdram_bankmachine1_cmd_payload_is_read[0:0] attribute \src "ls180.v:506.5-506.51" - wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:505.5-505.51" - wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:569.12-569.47" - wire width 13 $1\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:573.5-573.45" - wire $1\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:574.5-574.54" - wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:572.5-572.44" - wire $1\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:570.5-570.46" - wire $1\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:577.11-577.55" - wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:576.32-576.76" - wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:601.5-601.50" - wire $1\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:623.11-623.70" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:620.11-620.68" - wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:622.11-622.70" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:624.11-624.73" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:647.5-647.59" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:648.5-648.58" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:650.12-650.74" - wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:649.5-649.64" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:645.5-645.59" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:593.12-593.57" - wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:595.5-595.51" - wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:598.5-598.54" - wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:599.5-599.55" - wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:600.5-600.56" - wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:596.5-596.51" - wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:597.5-597.50" - wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:592.5-592.45" - wire $1\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:591.5-591.45" - wire $1\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:590.5-590.47" - wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] + wire $1\sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:502.5-502.46" + wire $1\sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:503.5-503.45" + wire $1\sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:498.5-498.40" + wire $1\sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:497.5-497.40" + wire $1\sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:496.5-496.42" + wire $1\sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:494.5-494.46" + wire $1\sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:493.5-493.46" + wire $1\sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:557.12-557.42" + wire width 13 $1\sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:561.5-561.40" + wire $1\sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:562.5-562.49" + wire $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:560.5-560.39" + wire $1\sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:558.5-558.41" + wire $1\sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:565.11-565.50" + wire width 3 $1\sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:564.32-564.71" + wire $1\sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:589.5-589.45" + wire $1\sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:611.11-611.65" + wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:608.11-608.63" + wire width 4 $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:610.11-610.65" + wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:612.11-612.68" + wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:635.5-635.54" + wire $1\sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:636.5-636.53" + wire $1\sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:638.12-638.69" + wire width 22 $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:637.5-637.59" + wire $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:633.5-633.54" + wire $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:581.12-581.52" + wire width 13 $1\sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:583.5-583.46" + wire $1\sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:586.5-586.49" + wire $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:587.5-587.50" + wire $1\sdram_bankmachine2_cmd_payload_is_read[0:0] attribute \src "ls180.v:588.5-588.51" - wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:587.5-587.51" - wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:651.12-651.47" - wire width 13 $1\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:655.5-655.45" - wire $1\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:656.5-656.54" - wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:654.5-654.44" - wire $1\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:652.5-652.46" - wire $1\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:659.11-659.55" - wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:658.32-658.76" - wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:683.5-683.50" - wire $1\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:705.11-705.70" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:702.11-702.68" - wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:704.11-704.70" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:706.11-706.73" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:729.5-729.59" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:730.5-730.58" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:732.12-732.74" - wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:731.5-731.64" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:727.5-727.59" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:675.12-675.57" - wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:677.5-677.51" - wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:680.5-680.54" - wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:681.5-681.55" - wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:682.5-682.56" - wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:678.5-678.51" - wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:679.5-679.50" - wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:674.5-674.45" - wire $1\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:673.5-673.45" - wire $1\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:672.5-672.47" - wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] + wire $1\sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:584.5-584.46" + wire $1\sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:585.5-585.45" + wire $1\sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:580.5-580.40" + wire $1\sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:579.5-579.40" + wire $1\sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:578.5-578.42" + wire $1\sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:576.5-576.46" + wire $1\sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:575.5-575.46" + wire $1\sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:639.12-639.42" + wire width 13 $1\sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:643.5-643.40" + wire $1\sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:644.5-644.49" + wire $1\sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:642.5-642.39" + wire $1\sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:640.5-640.41" + wire $1\sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:647.11-647.50" + wire width 3 $1\sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:646.32-646.71" + wire $1\sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:671.5-671.45" + wire $1\sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:693.11-693.65" + wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:690.11-690.63" + wire width 4 $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:692.11-692.65" + wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:694.11-694.68" + wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:717.5-717.54" + wire $1\sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:718.5-718.53" + wire $1\sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:720.12-720.69" + wire width 22 $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:719.5-719.59" + wire $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:715.5-715.54" + wire $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:663.12-663.52" + wire width 13 $1\sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:665.5-665.46" + wire $1\sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:668.5-668.49" + wire $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:669.5-669.50" + wire $1\sdram_bankmachine3_cmd_payload_is_read[0:0] attribute \src "ls180.v:670.5-670.51" - wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:669.5-669.51" - wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:733.12-733.47" - wire width 13 $1\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:737.5-737.45" - wire $1\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:738.5-738.54" - wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:736.5-736.44" - wire $1\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:734.5-734.46" - wire $1\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:741.11-741.55" - wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:740.32-740.76" - wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:765.5-765.50" - wire $1\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:787.11-787.70" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:784.11-784.68" - wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:786.11-786.70" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:788.11-788.73" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:811.5-811.59" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:812.5-812.58" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:814.12-814.74" - wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:813.5-813.64" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:809.5-809.59" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:757.12-757.57" - wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:759.5-759.51" - wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:762.5-762.54" - wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:763.5-763.55" - wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:764.5-764.56" - wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:760.5-760.51" - wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:761.5-761.50" - wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:756.5-756.45" - wire $1\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:755.5-755.45" - wire $1\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:754.5-754.47" - wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:752.5-752.51" - wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:751.5-751.51" - wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:815.12-815.47" - wire width 13 $1\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:819.5-819.45" - wire $1\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:820.5-820.54" - wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:818.5-818.44" - wire $1\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:816.5-816.46" - wire $1\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:823.11-823.55" - wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:822.32-822.76" - wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:838.5-838.49" - wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:839.5-839.49" - wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:840.5-840.48" - wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:846.11-846.45" - wire width 2 $1\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:844.11-844.46" - wire width 4 $1\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:856.5-856.49" - wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:857.5-857.49" - wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:858.5-858.48" - wire $1\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:853.5-853.43" - wire $1\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:864.11-864.45" - wire width 2 $1\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:862.11-862.46" - wire width 4 $1\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:851.5-851.48" - wire $1\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:848.5-848.44" - wire $1\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:849.5-849.45" - wire $1\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:477.5-477.31" - wire $1\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:478.12-478.44" - wire width 13 $1\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:479.11-479.43" - wire width 2 $1\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:480.5-480.38" - wire $1\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:481.5-481.38" - wire $1\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:482.5-482.37" - wire $1\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:476.5-476.32" - wire $1\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:475.5-475.32" - wire $1\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:415.5-415.33" - wire $1\main_sdram_command_re[0:0] - attribute \src "ls180.v:414.11-414.44" - wire width 6 $1\main_sdram_command_storage[5:0] - attribute \src "ls180.v:459.12-459.45" - wire width 13 $1\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:460.11-460.40" - wire width 2 $1\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:461.5-461.35" - wire $1\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:462.5-462.34" - wire $1\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:463.5-463.35" - wire $1\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:472.5-472.39" - wire $1\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:464.5-464.34" - wire $1\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:470.5-470.39" - wire $1\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:883.5-883.26" - wire $1\main_sdram_en0[0:0] - attribute \src "ls180.v:886.5-886.26" - wire $1\main_sdram_en1[0:0] - attribute \src "ls180.v:456.12-456.46" - wire width 16 $1\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:457.11-457.47" - wire width 2 $1\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:362.5-362.36" - wire $1\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:363.5-363.35" - wire $1\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:364.5-364.36" - wire $1\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:374.12-374.45" - wire width 16 $1\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:375.5-375.43" - wire $1\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:365.5-365.35" - wire $1\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:401.5-401.38" - wire $1\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:392.12-392.48" - wire width 13 $1\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:393.11-393.43" - wire width 2 $1\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:394.5-394.38" - wire $1\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:398.5-398.36" - wire $1\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:395.5-395.37" - wire $1\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:399.5-399.36" - wire $1\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:396.5-396.38" - wire $1\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:405.5-405.42" - wire $1\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:400.5-400.40" - wire $1\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:397.5-397.37" - wire $1\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:402.12-402.47" - wire width 16 $1\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:403.5-403.42" - wire $1\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:404.11-404.50" - wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:493.5-493.38" - wire $1\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:492.5-492.38" - wire $1\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:413.5-413.25" - wire $1\main_sdram_re[0:0] - attribute \src "ls180.v:499.5-499.38" - wire $1\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:498.11-498.46" - wire width 4 $1\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:497.5-497.38" - wire $1\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:494.5-494.39" - wire $1\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:390.12-390.46" - wire width 16 $1\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:391.5-391.44" - wire $1\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:426.12-426.37" - wire width 16 $1\main_sdram_status[15:0] - attribute \src "ls180.v:868.11-868.40" - wire width 2 $1\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:412.11-412.36" - wire width 4 $1\main_sdram_storage[3:0] - attribute \src "ls180.v:877.5-877.36" - wire $1\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:876.32-876.63" - wire $1\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:885.11-885.34" - wire width 5 $1\main_sdram_time0[4:0] - attribute \src "ls180.v:888.11-888.34" - wire width 4 $1\main_sdram_time1[3:0] - attribute \src "ls180.v:490.11-490.44" - wire width 10 $1\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:880.11-880.42" - wire width 3 $1\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:879.32-879.63" - wire $1\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:425.5-425.32" - wire $1\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:424.12-424.45" - wire width 16 $1\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:917.5-917.54" - wire $1\main_socbushandler_converted_interface_ack[0:0] - attribute \src "ls180.v:923.5-923.38" - wire $1\main_socbushandler_counter[0:0] - attribute \src "ls180.v:1852.5-1852.60" - wire $1\main_socbushandler_counter_converter2_next_value[0:0] - attribute \src "ls180.v:1853.5-1853.63" - wire $1\main_socbushandler_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:925.12-925.44" - wire width 64 $1\main_socbushandler_dat_r[63:0] - attribute \src "ls180.v:922.5-922.35" - wire $1\main_socbushandler_skip[0:0] - attribute \src "ls180.v:1111.12-1111.44" - wire width 16 $1\main_spimaster11_storage[15:0] - attribute \src "ls180.v:1112.5-1112.31" - wire $1\main_spimaster12_re[0:0] - attribute \src "ls180.v:1116.11-1116.42" - wire width 8 $1\main_spimaster16_storage[7:0] - attribute \src "ls180.v:1117.5-1117.31" - wire $1\main_spimaster17_re[0:0] - attribute \src "ls180.v:1173.5-1173.30" - wire $1\main_spimaster1_re[0:0] - attribute \src "ls180.v:1172.12-1172.45" - wire width 16 $1\main_spimaster1_storage[15:0] - attribute \src "ls180.v:1121.5-1121.36" - wire $1\main_spimaster21_storage[0:0] - attribute \src "ls180.v:1122.5-1122.31" - wire $1\main_spimaster22_re[0:0] - attribute \src "ls180.v:1123.5-1123.36" - wire $1\main_spimaster23_storage[0:0] - attribute \src "ls180.v:1124.5-1124.31" - wire $1\main_spimaster24_re[0:0] - attribute \src "ls180.v:1125.5-1125.39" - wire $1\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:1126.5-1126.38" - wire $1\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:1127.11-1127.40" - wire width 3 $1\main_spimaster27_count[2:0] - attribute \src "ls180.v:1893.11-1893.62" - wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:1894.5-1894.59" - wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:1128.5-1128.39" - wire $1\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:1129.5-1129.39" - wire $1\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:1102.5-1102.32" - wire $1\main_spimaster2_done[0:0] - attribute \src "ls180.v:1130.12-1130.48" - wire width 16 $1\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:1133.11-1133.44" - wire width 8 $1\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:1134.11-1134.43" - wire width 3 $1\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:1135.11-1135.44" - wire width 8 $1\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:1103.5-1103.31" - wire $1\main_spimaster3_irq[0:0] - attribute \src "ls180.v:1105.11-1105.38" - wire width 8 $1\main_spimaster5_miso[7:0] - attribute \src "ls180.v:1109.5-1109.33" - wire $1\main_spimaster9_start[0:0] - attribute \src "ls180.v:1166.12-1166.47" - wire width 16 $1\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:1161.5-1161.37" - wire $1\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:1148.5-1148.37" - wire $1\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:1147.12-1147.50" - wire width 16 $1\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:1163.11-1163.38" - wire width 3 $1\main_spisdcard_count[2:0] - attribute \src "ls180.v:1897.11-1897.60" - wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:1898.5-1898.57" - wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:1162.5-1162.36" - wire $1\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:1158.5-1158.32" - wire $1\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:1157.5-1157.37" - wire $1\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:1138.5-1138.32" - wire $1\main_spisdcard_done0[0:0] - attribute \src "ls180.v:1139.5-1139.30" - wire $1\main_spisdcard_irq[0:0] - attribute \src "ls180.v:1160.5-1160.38" - wire $1\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:1159.5-1159.43" - wire $1\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:1141.11-1141.37" - wire width 8 $1\main_spisdcard_miso[7:0] - attribute \src "ls180.v:1171.11-1171.42" - wire width 8 $1\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:1165.5-1165.37" - wire $1\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:1169.11-1169.42" - wire width 8 $1\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:1164.5-1164.37" - wire $1\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:1153.5-1153.34" - wire $1\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:1170.11-1170.41" - wire width 3 $1\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:1152.11-1152.45" - wire width 8 $1\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:1145.5-1145.33" - wire $1\main_spisdcard_start1[0:0] - attribute \src "ls180.v:262.11-262.31" - wire width 8 $1\main_sram0_we[7:0] - attribute \src "ls180.v:277.11-277.31" - wire width 8 $1\main_sram1_we[7:0] - attribute \src "ls180.v:292.11-292.31" - wire width 8 $1\main_sram2_we[7:0] - attribute \src "ls180.v:307.11-307.31" - wire width 8 $1\main_sram3_we[7:0] - attribute \src "ls180.v:993.11-993.50" - wire width 2 $1\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:995.5-995.37" - wire $1\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:989.11-989.49" - wire width 2 $1\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:994.11-994.48" - wire width 2 $1\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:961.12-961.54" - wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:951.12-951.54" - wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:944.5-944.28" - wire $1\main_uart_phy_re[0:0] - attribute \src "ls180.v:965.11-965.43" - wire width 4 $1\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:966.5-966.33" - wire $1\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:963.5-963.30" - wire $1\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:964.11-964.38" - wire width 8 $1\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:946.5-946.36" - wire $1\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:959.11-959.51" - wire width 8 $1\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:955.5-955.38" - wire $1\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:943.12-943.47" - wire width 32 $1\main_uart_phy_storage[31:0] - attribute \src "ls180.v:953.11-953.43" - wire width 4 $1\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:954.5-954.33" - wire $1\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:952.11-952.38" - wire width 8 $1\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:960.5-960.39" - wire $1\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:950.5-950.39" - wire $1\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:984.5-984.30" - wire $1\main_uart_rx_clear[0:0] - attribute \src "ls180.v:1068.11-1068.43" - wire width 4 $1\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:1065.11-1065.42" - wire width 5 $1\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:1067.11-1067.43" - wire width 4 $1\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:1058.5-1058.38" - wire $1\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:1069.11-1069.46" - wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:985.5-985.36" - wire $1\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:982.5-982.32" - wire $1\main_uart_rx_pending[0:0] - attribute \src "ls180.v:979.5-979.30" - wire $1\main_uart_tx_clear[0:0] - attribute \src "ls180.v:1031.11-1031.43" - wire width 4 $1\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:1028.11-1028.42" - wire width 5 $1\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:1030.11-1030.43" - wire width 4 $1\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:1021.5-1021.38" - wire $1\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:1032.11-1032.46" - wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:980.5-980.36" - wire $1\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:977.5-977.32" - wire $1\main_uart_tx_pending[0:0] - attribute \src "ls180.v:909.5-909.29" - wire $1\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:903.12-903.37" - wire width 30 $1\main_wb_sdram_adr[29:0] - attribute \src "ls180.v:907.5-907.29" - wire $1\main_wb_sdram_cyc[0:0] - attribute \src "ls180.v:904.12-904.39" - wire width 32 $1\main_wb_sdram_dat_w[31:0] - attribute \src "ls180.v:906.11-906.35" - wire width 4 $1\main_wb_sdram_sel[3:0] - attribute \src "ls180.v:908.5-908.29" - wire $1\main_wb_sdram_stb[0:0] - attribute \src "ls180.v:910.5-910.28" - wire $1\main_wb_sdram_we[0:0] - attribute \src "ls180.v:939.5-939.31" - wire $1\main_wdata_consumed[0:0] - attribute \src "ls180.v:2935.56-2935.86" - wire $add$ls180.v:2935$58_Y - attribute \src "ls180.v:2995.56-2995.86" - wire $add$ls180.v:2995$69_Y - attribute \src "ls180.v:3055.59-3055.92" - wire $add$ls180.v:3055$80_Y - attribute \src "ls180.v:4248.54-4248.83" - wire $add$ls180.v:4248$685_Y - attribute \src "ls180.v:4348.36-4348.89" - wire width 5 $add$ls180.v:4348$731_Y - attribute \src "ls180.v:4378.36-4378.89" - wire width 5 $add$ls180.v:4378$742_Y - attribute \src "ls180.v:4444.54-4444.83" - wire width 3 $add$ls180.v:4444$757_Y - attribute \src "ls180.v:4503.52-4503.79" - wire width 3 $add$ls180.v:4503$765_Y - attribute \src "ls180.v:4607.58-4607.86" - wire width 8 $add$ls180.v:4607$793_Y - attribute \src "ls180.v:4664.58-4664.86" - wire width 8 $add$ls180.v:4664$796_Y - attribute \src "ls180.v:4681.58-4681.86" - wire width 8 $add$ls180.v:4681$798_Y - attribute \src "ls180.v:4774.59-4774.87" - wire width 8 $add$ls180.v:4774$815_Y - attribute \src "ls180.v:4799.59-4799.87" - wire width 8 $add$ls180.v:4799$818_Y - attribute \src "ls180.v:4921.53-4921.82" - wire width 8 $add$ls180.v:4921$835_Y - attribute \src "ls180.v:5032.65-5032.114" - wire width 10 $add$ls180.v:5032$849_Y - attribute \src "ls180.v:5037.62-5037.91" - wire width 10 $add$ls180.v:5037$852_Y - attribute \src "ls180.v:5063.61-5063.90" - wire width 10 $add$ls180.v:5063$855_Y - attribute \src "ls180.v:5267.80-5267.117" - wire width 3 $add$ls180.v:5267$1040_Y - attribute \src "ls180.v:5461.54-5461.82" - wire width 3 $add$ls180.v:5461$1115_Y - attribute \src "ls180.v:5513.55-5513.84" - wire width 32 $add$ls180.v:5513$1125_Y - attribute \src "ls180.v:5539.57-5539.86" - wire width 32 $add$ls180.v:5539$1133_Y - attribute \src "ls180.v:5660.51-5660.134" - wire width 32 $add$ls180.v:5660$1149_Y - attribute \src "ls180.v:5663.77-5663.125" - wire width 32 $add$ls180.v:5663$1151_Y - attribute \src "ls180.v:5756.50-5756.105" - wire width 32 $add$ls180.v:5756$1160_Y - attribute \src "ls180.v:5758.77-5758.111" - wire width 32 $add$ls180.v:5758$1161_Y - attribute \src "ls180.v:7765.36-7765.70" - wire width 32 $add$ls180.v:7765$2604_Y - attribute \src "ls180.v:7866.37-7866.72" - wire width 4 $add$ls180.v:7866$2637_Y - attribute \src "ls180.v:7883.60-7883.119" - wire width 3 $add$ls180.v:7883$2641_Y - attribute \src "ls180.v:7886.60-7886.119" - wire width 3 $add$ls180.v:7886$2642_Y - attribute \src "ls180.v:7890.59-7890.116" - wire width 4 $add$ls180.v:7890$2647_Y - attribute \src "ls180.v:7929.60-7929.119" - wire width 3 $add$ls180.v:7929$2657_Y - attribute \src "ls180.v:7932.60-7932.119" - wire width 3 $add$ls180.v:7932$2658_Y - attribute \src "ls180.v:7936.59-7936.116" - wire width 4 $add$ls180.v:7936$2663_Y - attribute \src "ls180.v:7975.60-7975.119" - wire width 3 $add$ls180.v:7975$2673_Y - attribute \src "ls180.v:7978.60-7978.119" - wire width 3 $add$ls180.v:7978$2674_Y - attribute \src "ls180.v:7982.59-7982.116" - wire width 4 $add$ls180.v:7982$2679_Y - attribute \src "ls180.v:8021.60-8021.119" - wire width 3 $add$ls180.v:8021$2689_Y - attribute \src "ls180.v:8024.60-8024.119" - wire width 3 $add$ls180.v:8024$2690_Y - attribute \src "ls180.v:8028.59-8028.116" - wire width 4 $add$ls180.v:8028$2695_Y - attribute \src "ls180.v:8258.34-8258.66" - wire width 4 $add$ls180.v:8258$2749_Y - attribute \src "ls180.v:8274.73-8274.131" - wire width 33 $add$ls180.v:8274$2752_Y - attribute \src "ls180.v:8287.34-8287.66" - wire width 4 $add$ls180.v:8287$2756_Y - attribute \src "ls180.v:8306.73-8306.131" - wire width 33 $add$ls180.v:8306$2759_Y - attribute \src "ls180.v:8332.33-8332.65" - wire width 4 $add$ls180.v:8332$2767_Y - attribute \src "ls180.v:8335.33-8335.65" - wire width 4 $add$ls180.v:8335$2768_Y - attribute \src "ls180.v:8339.33-8339.64" - wire width 5 $add$ls180.v:8339$2773_Y - attribute \src "ls180.v:8354.33-8354.65" - wire width 4 $add$ls180.v:8354$2778_Y - attribute \src "ls180.v:8357.33-8357.65" - wire width 4 $add$ls180.v:8357$2779_Y - attribute \src "ls180.v:8361.33-8361.64" - wire width 5 $add$ls180.v:8361$2784_Y - attribute \src "ls180.v:8382.35-8382.70" - wire width 16 $add$ls180.v:8382$2786_Y - attribute \src "ls180.v:8417.34-8417.68" - wire width 16 $add$ls180.v:8417$2791_Y - attribute \src "ls180.v:8453.25-8453.49" - wire width 32 $add$ls180.v:8453$2796_Y - attribute \src "ls180.v:8467.25-8467.49" - wire width 32 $add$ls180.v:8467$2800_Y - attribute \src "ls180.v:8481.31-8481.61" - wire width 9 $add$ls180.v:8481$2805_Y - attribute \src "ls180.v:8504.45-8504.88" - wire width 3 $add$ls180.v:8504$2809_Y - attribute \src "ls180.v:8550.71-8550.114" - wire width 4 $add$ls180.v:8550$2815_Y - attribute \src "ls180.v:8585.46-8585.90" - wire width 3 $add$ls180.v:8585$2821_Y - attribute \src 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"ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10451$31_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10451$31_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10451$31_EN - attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10453$32_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10453$32_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10453$32_EN - attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10467$33_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10467$33_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10467$33_EN - attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10469$34_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10469$34_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10469$34_EN + wire $1\sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:666.5-666.46" + wire $1\sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:667.5-667.45" + wire $1\sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:662.5-662.40" + wire $1\sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:661.5-661.40" + wire $1\sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:660.5-660.42" + wire $1\sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:658.5-658.46" + wire $1\sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:657.5-657.46" + wire $1\sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:721.12-721.42" + wire width 13 $1\sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:725.5-725.40" + wire $1\sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:726.5-726.49" + wire $1\sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:724.5-724.39" + wire $1\sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:722.5-722.41" + wire $1\sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:729.11-729.50" + wire width 3 $1\sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:728.32-728.71" + wire $1\sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:744.5-744.44" + wire $1\sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:745.5-745.44" + wire $1\sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:746.5-746.43" + wire $1\sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:752.11-752.40" + wire width 2 $1\sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:750.11-750.41" + wire width 4 $1\sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:762.5-762.44" + wire $1\sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:763.5-763.44" + wire $1\sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:764.5-764.43" + wire $1\sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:759.5-759.38" + wire $1\sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:770.11-770.40" + wire width 2 $1\sdram_choose_req_grant[1:0] + attribute \src "ls180.v:768.11-768.41" + wire width 4 $1\sdram_choose_req_valids[3:0] + attribute \src "ls180.v:757.5-757.43" + wire $1\sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:754.5-754.39" + wire $1\sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:755.5-755.40" + wire $1\sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:383.5-383.26" + wire $1\sdram_cmd_last[0:0] + attribute \src "ls180.v:384.12-384.39" + wire width 13 $1\sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:385.11-385.38" + wire width 2 $1\sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:386.5-386.33" + wire $1\sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:387.5-387.33" + wire $1\sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:388.5-388.32" + wire $1\sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:382.5-382.27" + wire $1\sdram_cmd_ready[0:0] + attribute \src "ls180.v:381.5-381.27" + wire $1\sdram_cmd_valid[0:0] + attribute \src "ls180.v:321.5-321.28" + wire $1\sdram_command_re[0:0] + attribute \src "ls180.v:320.11-320.39" + wire width 6 $1\sdram_command_storage[5:0] + attribute \src "ls180.v:365.12-365.40" + wire width 13 $1\sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:366.11-366.35" + wire width 2 $1\sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:367.5-367.30" + wire $1\sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:368.5-368.29" + wire $1\sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:369.5-369.30" + wire $1\sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:378.5-378.34" + wire $1\sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:370.5-370.29" + wire $1\sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:376.5-376.34" + wire $1\sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:789.5-789.21" + wire $1\sdram_en0[0:0] + attribute \src "ls180.v:792.5-792.21" + wire $1\sdram_en1[0:0] + attribute \src "ls180.v:362.12-362.41" + wire width 16 $1\sdram_interface_wdata[15:0] + attribute \src "ls180.v:363.11-363.42" + wire width 2 $1\sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:268.5-268.31" + wire $1\sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:269.5-269.30" + wire $1\sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:270.5-270.31" + wire $1\sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:280.12-280.40" + wire width 16 $1\sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:281.5-281.38" + wire $1\sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:271.5-271.30" + wire $1\sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:307.5-307.33" + wire $1\sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:298.12-298.43" + wire width 13 $1\sdram_master_p0_address[12:0] + attribute \src "ls180.v:299.11-299.38" + wire width 2 $1\sdram_master_p0_bank[1:0] + attribute \src "ls180.v:300.5-300.33" + wire $1\sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:304.5-304.31" + wire $1\sdram_master_p0_cke[0:0] + attribute \src "ls180.v:301.5-301.32" + wire $1\sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:305.5-305.31" + wire $1\sdram_master_p0_odt[0:0] + attribute \src "ls180.v:302.5-302.33" + wire $1\sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:311.5-311.37" + wire $1\sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:306.5-306.35" + wire $1\sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:303.5-303.32" + wire $1\sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:308.12-308.42" + wire width 16 $1\sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:309.5-309.37" + wire $1\sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:310.11-310.45" + wire width 2 $1\sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:399.5-399.33" + wire $1\sdram_postponer_count[0:0] + attribute \src "ls180.v:398.5-398.33" + wire $1\sdram_postponer_req_o[0:0] + attribute \src "ls180.v:319.5-319.20" + wire $1\sdram_re[0:0] + attribute \src "ls180.v:405.5-405.33" + wire $1\sdram_sequencer_count[0:0] + attribute \src "ls180.v:404.11-404.41" + wire width 4 $1\sdram_sequencer_counter[3:0] + attribute \src "ls180.v:403.5-403.33" + wire $1\sdram_sequencer_done1[0:0] + attribute \src "ls180.v:400.5-400.34" + wire $1\sdram_sequencer_start0[0:0] + attribute \src "ls180.v:296.12-296.41" + wire width 16 $1\sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:297.5-297.39" + wire $1\sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:332.12-332.32" + wire width 16 $1\sdram_status[15:0] + attribute \src "ls180.v:774.11-774.35" + wire width 2 $1\sdram_steerer_sel[1:0] + attribute \src "ls180.v:318.11-318.31" + wire width 4 $1\sdram_storage[3:0] + attribute \src "ls180.v:783.5-783.31" + wire $1\sdram_tccdcon_count[0:0] + attribute \src "ls180.v:782.32-782.58" + wire $1\sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:791.11-791.29" + wire width 5 $1\sdram_time0[4:0] + attribute \src "ls180.v:794.11-794.29" + wire width 4 $1\sdram_time1[3:0] + attribute \src "ls180.v:396.11-396.39" + wire width 10 $1\sdram_timer_count1[9:0] + attribute \src "ls180.v:786.11-786.37" + wire width 3 $1\sdram_twtrcon_count[2:0] + attribute \src "ls180.v:785.32-785.58" + wire $1\sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:331.5-331.27" + wire $1\sdram_wrdata_re[0:0] + attribute \src "ls180.v:330.12-330.40" + wire width 16 $1\sdram_wrdata_storage[15:0] + attribute \src "ls180.v:1023.11-1023.54" + wire width 3 $1\subfragments_bankmachine0_next_state[2:0] + attribute \src "ls180.v:1022.11-1022.49" + wire width 3 $1\subfragments_bankmachine0_state[2:0] + attribute \src "ls180.v:1025.11-1025.54" + wire width 3 $1\subfragments_bankmachine1_next_state[2:0] + attribute \src "ls180.v:1024.11-1024.49" + wire width 3 $1\subfragments_bankmachine1_state[2:0] + attribute \src "ls180.v:1027.11-1027.54" + wire width 3 $1\subfragments_bankmachine2_next_state[2:0] + attribute \src "ls180.v:1026.11-1026.49" + wire width 3 $1\subfragments_bankmachine2_state[2:0] + attribute \src "ls180.v:1029.11-1029.54" + wire width 3 $1\subfragments_bankmachine3_next_state[2:0] + attribute \src "ls180.v:1028.11-1028.49" + wire width 3 $1\subfragments_bankmachine3_state[2:0] + attribute \src "ls180.v:1009.5-1009.46" + wire $1\subfragments_converter0_next_state[0:0] + attribute \src "ls180.v:1008.5-1008.41" + wire $1\subfragments_converter0_state[0:0] + attribute \src "ls180.v:1013.5-1013.46" + wire $1\subfragments_converter1_next_state[0:0] + attribute \src "ls180.v:1012.5-1012.41" + wire $1\subfragments_converter1_state[0:0] + attribute \src "ls180.v:1017.5-1017.46" + wire $1\subfragments_converter2_next_state[0:0] + attribute \src "ls180.v:1016.5-1016.41" + wire $1\subfragments_converter2_state[0:0] + attribute \src "ls180.v:1031.11-1031.53" + wire width 3 $1\subfragments_multiplexer_next_state[2:0] + attribute \src "ls180.v:1030.11-1030.48" + wire width 3 $1\subfragments_multiplexer_state[2:0] + attribute \src "ls180.v:1049.5-1049.48" + wire $1\subfragments_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:1050.5-1050.48" + wire $1\subfragments_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:1051.5-1051.48" + wire $1\subfragments_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:1052.5-1052.48" + wire $1\subfragments_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:1048.5-1048.47" + wire $1\subfragments_new_master_wdata_ready[0:0] + attribute \src "ls180.v:1054.5-1054.35" + wire $1\subfragments_next_state[0:0] + attribute \src "ls180.v:1021.11-1021.51" + wire width 2 $1\subfragments_refresher_next_state[1:0] + attribute \src "ls180.v:1020.11-1020.46" + wire width 2 $1\subfragments_refresher_state[1:0] + attribute \src "ls180.v:1053.5-1053.30" + wire $1\subfragments_state[0:0] + attribute \src "ls180.v:1349.5-1349.26" + wire $1\t_array_muxed0[0:0] + attribute \src "ls180.v:1350.5-1350.26" + wire $1\t_array_muxed1[0:0] + attribute \src "ls180.v:1351.5-1351.26" + wire $1\t_array_muxed2[0:0] + attribute \src "ls180.v:1358.5-1358.26" + wire $1\t_array_muxed3[0:0] + attribute \src "ls180.v:1359.5-1359.26" + wire $1\t_array_muxed4[0:0] + attribute \src "ls180.v:1360.5-1360.26" + wire $1\t_array_muxed5[0:0] + attribute \src "ls180.v:873.5-873.20" + wire $1\tx_clear[0:0] + attribute \src "ls180.v:925.11-925.33" + wire width 4 $1\tx_fifo_consume[3:0] + attribute \src "ls180.v:922.11-922.32" + wire width 5 $1\tx_fifo_level0[4:0] + attribute \src "ls180.v:924.11-924.33" + wire width 4 $1\tx_fifo_produce[3:0] + attribute \src "ls180.v:915.5-915.28" + wire $1\tx_fifo_readable[0:0] + attribute \src "ls180.v:926.11-926.36" + wire width 4 $1\tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:874.5-874.26" + wire $1\tx_old_trigger[0:0] + attribute \src "ls180.v:871.5-871.22" + wire $1\tx_pending[0:0] + attribute \src "ls180.v:855.12-855.49" + wire width 32 $1\uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:845.12-845.49" + wire width 32 $1\uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:838.5-838.23" + wire $1\uart_phy_re[0:0] + attribute \src "ls180.v:859.11-859.38" + wire width 4 $1\uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:860.5-860.28" + wire $1\uart_phy_rx_busy[0:0] + attribute \src "ls180.v:857.5-857.25" + wire $1\uart_phy_rx_r[0:0] + attribute \src "ls180.v:858.11-858.33" + wire width 8 $1\uart_phy_rx_reg[7:0] + attribute \src "ls180.v:840.5-840.31" + wire $1\uart_phy_sink_ready[0:0] + attribute \src "ls180.v:853.11-853.46" + wire width 8 $1\uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:849.5-849.33" + wire $1\uart_phy_source_valid[0:0] + attribute \src "ls180.v:837.12-837.42" + wire width 32 $1\uart_phy_storage[31:0] + attribute \src "ls180.v:847.11-847.38" + wire width 4 $1\uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:848.5-848.28" + wire $1\uart_phy_tx_busy[0:0] + attribute \src "ls180.v:846.11-846.33" + wire width 8 $1\uart_phy_tx_reg[7:0] + attribute \src "ls180.v:854.5-854.34" + wire $1\uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:844.5-844.34" + wire $1\uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:815.5-815.24" + wire $1\wb_sdram_ack[0:0] + attribute \src "ls180.v:833.5-833.26" + wire $1\wdata_consumed[0:0] + attribute \src "ls180.v:1561.76-1561.113" + wire $add$ls180.v:1561$25_Y + attribute \src "ls180.v:1621.76-1621.113" + wire $add$ls180.v:1621$36_Y + attribute \src "ls180.v:1681.76-1681.113" + wire $add$ls180.v:1681$47_Y + attribute \src "ls180.v:2824.52-2824.76" + wire $add$ls180.v:2824$553_Y + attribute \src "ls180.v:2924.26-2924.59" + wire width 5 $add$ls180.v:2924$599_Y + attribute \src "ls180.v:2954.26-2954.59" + wire width 5 $add$ls180.v:2954$610_Y + attribute \src "ls180.v:4357.31-4357.60" + wire width 32 $add$ls180.v:4357$1256_Y + attribute \src "ls180.v:4446.32-4446.62" + wire width 4 $add$ls180.v:4446$1280_Y + attribute \src "ls180.v:4463.55-4463.109" + wire width 3 $add$ls180.v:4463$1284_Y + attribute \src "ls180.v:4466.55-4466.109" + wire width 3 $add$ls180.v:4466$1285_Y + attribute \src "ls180.v:4470.54-4470.106" + wire width 4 $add$ls180.v:4470$1290_Y + attribute \src "ls180.v:4509.55-4509.109" + wire width 3 $add$ls180.v:4509$1300_Y + attribute \src "ls180.v:4512.55-4512.109" + wire width 3 $add$ls180.v:4512$1301_Y + attribute \src "ls180.v:4516.54-4516.106" + wire width 4 $add$ls180.v:4516$1306_Y + attribute \src "ls180.v:4555.55-4555.109" + wire width 3 $add$ls180.v:4555$1316_Y + attribute \src "ls180.v:4558.55-4558.109" + wire width 3 $add$ls180.v:4558$1317_Y + attribute \src "ls180.v:4562.54-4562.106" + wire width 4 $add$ls180.v:4562$1322_Y + attribute \src "ls180.v:4601.55-4601.109" + wire width 3 $add$ls180.v:4601$1332_Y + attribute \src "ls180.v:4604.55-4604.109" + wire width 3 $add$ls180.v:4604$1333_Y + attribute \src "ls180.v:4608.54-4608.106" + wire width 4 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"ls180.v:3216.106-3216.154" + wire $eq$ls180.v:3216$765_Y + attribute \src "ls180.v:3217.109-3217.157" + wire $eq$ls180.v:3217$769_Y + attribute \src "ls180.v:3219.105-3219.153" + wire $eq$ls180.v:3219$772_Y + attribute \src "ls180.v:3220.108-3220.156" + wire $eq$ls180.v:3220$776_Y + attribute \src "ls180.v:3222.107-3222.155" + wire $eq$ls180.v:3222$779_Y + attribute \src "ls180.v:3223.110-3223.158" + wire $eq$ls180.v:3223$783_Y + attribute \src "ls180.v:3228.36-3228.85" + wire $eq$ls180.v:3228$785_Y + attribute \src "ls180.v:3230.105-3230.151" + wire $eq$ls180.v:3230$787_Y + attribute \src "ls180.v:3231.108-3231.154" + wire $eq$ls180.v:3231$791_Y + attribute \src "ls180.v:3233.104-3233.150" + wire $eq$ls180.v:3233$794_Y + attribute \src "ls180.v:3234.107-3234.153" + wire $eq$ls180.v:3234$798_Y + attribute \src "ls180.v:3242.36-3242.85" + wire $eq$ls180.v:3242$800_Y + attribute \src "ls180.v:3244.116-3244.164" + wire $eq$ls180.v:3244$802_Y + attribute \src "ls180.v:3245.119-3245.167" + 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attribute \src "ls180.v:3299.111-3299.159" + wire $eq$ls180.v:3299$898_Y + attribute \src "ls180.v:3301.110-3301.158" + wire $eq$ls180.v:3301$901_Y + attribute \src "ls180.v:3302.113-3302.161" + wire $eq$ls180.v:3302$905_Y + attribute \src "ls180.v:3304.110-3304.158" + wire $eq$ls180.v:3304$908_Y + attribute \src "ls180.v:3305.113-3305.161" + wire $eq$ls180.v:3305$912_Y + attribute \src "ls180.v:3307.110-3307.158" + wire $eq$ls180.v:3307$915_Y + attribute \src "ls180.v:3308.113-3308.161" + wire $eq$ls180.v:3308$919_Y + attribute \src "ls180.v:3310.110-3310.158" + wire $eq$ls180.v:3310$922_Y + attribute \src "ls180.v:3311.113-3311.161" + wire $eq$ls180.v:3311$926_Y + attribute \src "ls180.v:3313.106-3313.154" + wire $eq$ls180.v:3313$929_Y + attribute \src "ls180.v:3314.109-3314.157" + wire $eq$ls180.v:3314$933_Y + attribute \src "ls180.v:3316.116-3316.164" + wire $eq$ls180.v:3316$936_Y + attribute \src "ls180.v:3317.119-3317.167" + wire $eq$ls180.v:3317$940_Y + attribute \src "ls180.v:3319.109-3319.158" + wire $eq$ls180.v:3319$943_Y + attribute \src "ls180.v:3320.112-3320.161" + wire $eq$ls180.v:3320$947_Y + attribute \src "ls180.v:3322.109-3322.158" + wire $eq$ls180.v:3322$950_Y + attribute \src "ls180.v:3323.112-3323.161" + wire $eq$ls180.v:3323$954_Y + attribute \src "ls180.v:3325.109-3325.158" + wire $eq$ls180.v:3325$957_Y + attribute \src "ls180.v:3326.112-3326.161" + wire $eq$ls180.v:3326$961_Y + attribute \src "ls180.v:3328.109-3328.158" + wire $eq$ls180.v:3328$964_Y + attribute \src "ls180.v:3329.112-3329.161" + wire $eq$ls180.v:3329$968_Y + attribute \src "ls180.v:3331.113-3331.162" + wire $eq$ls180.v:3331$971_Y + attribute \src "ls180.v:3332.116-3332.165" + wire $eq$ls180.v:3332$975_Y + attribute \src "ls180.v:3334.114-3334.163" + wire $eq$ls180.v:3334$978_Y + attribute \src "ls180.v:3335.117-3335.166" + wire $eq$ls180.v:3335$982_Y + attribute \src "ls180.v:3337.113-3337.162" + wire $eq$ls180.v:3337$985_Y + attribute \src "ls180.v:3338.116-3338.165" + wire $eq$ls180.v:3338$989_Y + attribute \src "ls180.v:3355.36-3355.85" + wire $eq$ls180.v:3355$991_Y + attribute \src "ls180.v:3357.86-3357.134" + wire $eq$ls180.v:3357$993_Y + attribute \src "ls180.v:3358.89-3358.137" + wire $eq$ls180.v:3358$997_Y + attribute \src "ls180.v:3360.109-3360.157" + wire $eq$ls180.v:3360$1000_Y + attribute \src "ls180.v:3361.112-3361.160" + wire $eq$ls180.v:3361$1004_Y + attribute \src "ls180.v:3363.110-3363.158" + wire $eq$ls180.v:3363$1007_Y + attribute \src "ls180.v:3364.113-3364.161" + wire $eq$ls180.v:3364$1011_Y + attribute \src "ls180.v:3366.101-3366.149" + wire $eq$ls180.v:3366$1014_Y + attribute \src "ls180.v:3367.104-3367.152" + wire $eq$ls180.v:3367$1018_Y + attribute \src "ls180.v:3369.102-3369.150" + wire $eq$ls180.v:3369$1021_Y + attribute \src "ls180.v:3370.105-3370.153" + wire $eq$ls180.v:3370$1025_Y + attribute \src "ls180.v:3372.113-3372.161" + wire $eq$ls180.v:3372$1028_Y + attribute \src "ls180.v:3373.116-3373.164" + wire $eq$ls180.v:3373$1032_Y + attribute \src "ls180.v:3375.110-3375.158" + wire $eq$ls180.v:3375$1035_Y + attribute \src "ls180.v:3376.113-3376.161" + wire $eq$ls180.v:3376$1039_Y + attribute \src "ls180.v:3378.109-3378.157" + wire $eq$ls180.v:3378$1042_Y + attribute \src "ls180.v:3379.112-3379.160" + wire $eq$ls180.v:3379$1046_Y + attribute \src "ls180.v:3389.36-3389.85" + wire $eq$ls180.v:3389$1048_Y + attribute \src "ls180.v:3391.115-3391.163" + wire $eq$ls180.v:3391$1050_Y + attribute \src "ls180.v:3392.118-3392.166" + wire $eq$ls180.v:3392$1054_Y + attribute \src "ls180.v:3394.115-3394.163" + wire $eq$ls180.v:3394$1057_Y + attribute \src "ls180.v:3395.118-3395.166" + wire $eq$ls180.v:3395$1061_Y + attribute \src "ls180.v:3397.115-3397.163" + wire $eq$ls180.v:3397$1064_Y + attribute \src "ls180.v:3398.118-3398.166" + wire $eq$ls180.v:3398$1068_Y + attribute \src "ls180.v:3400.115-3400.163" + wire $eq$ls180.v:3400$1071_Y + attribute \src "ls180.v:3401.118-3401.166" + wire $eq$ls180.v:3401$1075_Y + attribute \src "ls180.v:3761.28-3761.63" + wire $eq$ls180.v:3761$1105_Y + attribute \src "ls180.v:3761.126-3761.164" + wire $eq$ls180.v:3761$1106_Y + attribute \src "ls180.v:3761.201-3761.239" + wire $eq$ls180.v:3761$1109_Y + attribute \src "ls180.v:3761.276-3761.314" + wire $eq$ls180.v:3761$1112_Y + attribute \src "ls180.v:3785.28-3785.63" + wire $eq$ls180.v:3785$1121_Y + attribute \src "ls180.v:3785.126-3785.164" + wire $eq$ls180.v:3785$1122_Y + attribute \src "ls180.v:3785.201-3785.239" + wire $eq$ls180.v:3785$1125_Y + attribute \src "ls180.v:3785.276-3785.314" + wire $eq$ls180.v:3785$1128_Y + attribute \src "ls180.v:3809.28-3809.63" + wire $eq$ls180.v:3809$1137_Y + attribute \src "ls180.v:3809.126-3809.164" + wire $eq$ls180.v:3809$1138_Y + attribute \src "ls180.v:3809.201-3809.239" + wire $eq$ls180.v:3809$1141_Y + attribute \src "ls180.v:3809.276-3809.314" + wire $eq$ls180.v:3809$1144_Y + attribute \src "ls180.v:3833.28-3833.63" + wire $eq$ls180.v:3833$1153_Y + attribute \src "ls180.v:3833.126-3833.164" + wire $eq$ls180.v:3833$1154_Y + attribute \src "ls180.v:3833.201-3833.239" + wire $eq$ls180.v:3833$1157_Y + attribute \src "ls180.v:3833.276-3833.314" + wire $eq$ls180.v:3833$1160_Y + attribute \src "ls180.v:4365.8-4365.33" + wire $eq$ls180.v:4365$1260_Y + attribute \src "ls180.v:4400.8-4400.37" + wire $eq$ls180.v:4400$1271_Y + attribute \src "ls180.v:4420.33-4420.64" + wire $eq$ls180.v:4420$1274_Y + attribute \src "ls180.v:4427.7-4427.38" + wire $eq$ls180.v:4427$1276_Y + attribute \src "ls180.v:4434.7-4434.38" + wire $eq$ls180.v:4434$1277_Y + attribute \src "ls180.v:4442.7-4442.38" + wire $eq$ls180.v:4442$1278_Y + attribute \src "ls180.v:4494.9-4494.49" + wire $eq$ls180.v:4494$1296_Y + attribute \src "ls180.v:4540.9-4540.49" + wire $eq$ls180.v:4540$1312_Y + attribute \src "ls180.v:4586.9-4586.49" + wire $eq$ls180.v:4586$1328_Y + attribute \src "ls180.v:4632.9-4632.49" + wire $eq$ls180.v:4632$1344_Y + attribute \src "ls180.v:4782.9-4782.36" + wire $eq$ls180.v:4782$1356_Y + attribute \src "ls180.v:4797.9-4797.36" + wire $eq$ls180.v:4797$1359_Y + attribute \src "ls180.v:4803.54-4803.92" + wire $eq$ls180.v:4803$1360_Y + attribute \src "ls180.v:4803.136-4803.174" + wire $eq$ls180.v:4803$1363_Y + attribute \src "ls180.v:4803.218-4803.256" + wire $eq$ls180.v:4803$1366_Y + attribute \src "ls180.v:4803.300-4803.338" + wire $eq$ls180.v:4803$1369_Y + attribute \src "ls180.v:4804.55-4804.93" + wire $eq$ls180.v:4804$1372_Y + attribute \src "ls180.v:4804.137-4804.175" + wire $eq$ls180.v:4804$1375_Y + attribute \src "ls180.v:4804.219-4804.257" + wire $eq$ls180.v:4804$1378_Y + attribute \src "ls180.v:4804.301-4804.339" + wire $eq$ls180.v:4804$1381_Y + attribute \src "ls180.v:4839.9-4839.37" + wire $eq$ls180.v:4839$1393_Y + attribute \src "ls180.v:4842.10-4842.38" + wire $eq$ls180.v:4842$1394_Y + attribute \src "ls180.v:4868.9-4868.37" + wire $eq$ls180.v:4868$1400_Y + attribute \src "ls180.v:4873.10-4873.38" + wire $eq$ls180.v:4873$1401_Y + attribute \src "ls180.v:5507.28-5507.31" + wire width 32 $memrd$\mem$ls180.v:5507$1459_DATA + attribute \src "ls180.v:5527.20-5527.25" + wire width 32 $memrd$\mem_1$ls180.v:5527$1485_DATA + attribute \src "ls180.v:5538.12-5538.19" + wire width 25 $memrd$\storage$ls180.v:5538$1493_DATA + attribute \src "ls180.v:5545.63-5545.70" + wire width 25 $memrd$\storage$ls180.v:5545$1495_DATA + attribute \src "ls180.v:5552.14-5552.23" + wire width 25 $memrd$\storage_1$ls180.v:5552$1503_DATA + attribute \src "ls180.v:5559.63-5559.72" + wire width 25 $memrd$\storage_1$ls180.v:5559$1505_DATA + attribute \src "ls180.v:5566.14-5566.23" + wire width 25 $memrd$\storage_2$ls180.v:5566$1513_DATA + attribute \src "ls180.v:5573.63-5573.72" + wire width 25 $memrd$\storage_2$ls180.v:5573$1515_DATA + attribute \src "ls180.v:5580.14-5580.23" + wire width 25 $memrd$\storage_3$ls180.v:5580$1523_DATA + attribute \src "ls180.v:5587.63-5587.72" + wire width 25 $memrd$\storage_3$ls180.v:5587$1525_DATA + attribute \src "ls180.v:5595.14-5595.23" + wire width 10 $memrd$\storage_4$ls180.v:5595$1533_DATA + attribute \src "ls180.v:5600.15-5600.24" + wire width 10 $memrd$\storage_4$ls180.v:5600$1535_DATA + attribute \src "ls180.v:5612.14-5612.23" + wire width 10 $memrd$\storage_5$ls180.v:5612$1543_DATA + attribute \src "ls180.v:5617.15-5617.24" + wire width 10 $memrd$\storage_5$ls180.v:5617$1545_DATA attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10471$35_ADDR + wire width 7 $memwr$\mem$ls180.v:5497$1_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10471$35_DATA + wire width 32 $memwr$\mem$ls180.v:5497$1_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10471$35_EN + wire width 32 $memwr$\mem$ls180.v:5497$1_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10473$36_ADDR + wire width 7 $memwr$\mem$ls180.v:5499$2_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10473$36_DATA + wire width 32 $memwr$\mem$ls180.v:5499$2_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10473$36_EN + wire width 32 $memwr$\mem$ls180.v:5499$2_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10475$37_ADDR + wire width 7 $memwr$\mem$ls180.v:5501$3_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10475$37_DATA + wire width 32 $memwr$\mem$ls180.v:5501$3_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10475$37_EN + wire width 32 $memwr$\mem$ls180.v:5501$3_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10477$38_ADDR + wire width 7 $memwr$\mem$ls180.v:5503$4_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10477$38_DATA + wire width 32 $memwr$\mem$ls180.v:5503$4_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10477$38_EN + wire width 32 $memwr$\mem$ls180.v:5503$4_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10479$39_ADDR + wire width 5 $memwr$\mem_1$ls180.v:5517$5_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10479$39_DATA + wire width 32 $memwr$\mem_1$ls180.v:5517$5_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10479$39_EN + wire width 32 $memwr$\mem_1$ls180.v:5517$5_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10481$40_ADDR + wire width 5 $memwr$\mem_1$ls180.v:5519$6_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10481$40_DATA + wire width 32 $memwr$\mem_1$ls180.v:5519$6_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10481$40_EN + wire width 32 $memwr$\mem_1$ls180.v:5519$6_EN attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage$ls180.v:10495$41_ADDR + wire width 5 $memwr$\mem_1$ls180.v:5521$7_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage$ls180.v:10495$41_DATA + wire width 32 $memwr$\mem_1$ls180.v:5521$7_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage$ls180.v:10495$41_EN + wire width 32 $memwr$\mem_1$ls180.v:5521$7_EN attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_1$ls180.v:10509$42_ADDR + wire width 5 $memwr$\mem_1$ls180.v:5523$8_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_1$ls180.v:10509$42_DATA + wire width 32 $memwr$\mem_1$ls180.v:5523$8_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_1$ls180.v:10509$42_EN + wire width 32 $memwr$\mem_1$ls180.v:5523$8_EN attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_2$ls180.v:10523$43_ADDR + wire width 3 $memwr$\storage$ls180.v:5537$9_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_2$ls180.v:10523$43_DATA + wire width 25 $memwr$\storage$ls180.v:5537$9_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_2$ls180.v:10523$43_EN + wire width 25 $memwr$\storage$ls180.v:5537$9_EN attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_3$ls180.v:10537$44_ADDR + wire width 3 $memwr$\storage_1$ls180.v:5551$10_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_3$ls180.v:10537$44_DATA + wire width 25 $memwr$\storage_1$ls180.v:5551$10_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_3$ls180.v:10537$44_EN + wire width 25 $memwr$\storage_1$ls180.v:5551$10_EN attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\storage_4$ls180.v:10552$45_ADDR + wire width 3 $memwr$\storage_2$ls180.v:5565$11_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_4$ls180.v:10552$45_DATA + wire width 25 $memwr$\storage_2$ls180.v:5565$11_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_4$ls180.v:10552$45_EN + wire width 25 $memwr$\storage_2$ls180.v:5565$11_EN attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\storage_5$ls180.v:10569$46_ADDR + wire width 3 $memwr$\storage_3$ls180.v:5579$12_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_5$ls180.v:10569$46_DATA + wire width 25 $memwr$\storage_3$ls180.v:5579$12_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_5$ls180.v:10569$46_EN + wire width 25 $memwr$\storage_3$ls180.v:5579$12_EN attribute \src "ls180.v:0.0-0.0" - wire width 5 $memwr$\storage_6$ls180.v:10585$47_ADDR + wire width 4 $memwr$\storage_4$ls180.v:5594$13_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_6$ls180.v:10585$47_DATA + wire width 10 $memwr$\storage_4$ls180.v:5594$13_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_6$ls180.v:10585$47_EN + wire width 10 $memwr$\storage_4$ls180.v:5594$13_EN attribute \src "ls180.v:0.0-0.0" - wire width 5 $memwr$\storage_7$ls180.v:10599$48_ADDR + wire width 4 $memwr$\storage_5$ls180.v:5611$14_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_7$ls180.v:10599$48_DATA + wire width 10 $memwr$\storage_5$ls180.v:5611$14_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_7$ls180.v:10599$48_EN - attribute \src "ls180.v:3089.41-3089.71" - wire $ne$ls180.v:3089$108_Y - attribute \src "ls180.v:3306.70-3306.104" - wire $ne$ls180.v:3306$222_Y - attribute \src "ls180.v:3367.8-3367.142" - wire $ne$ls180.v:3367$241_Y - attribute \src "ls180.v:3399.75-3399.133" - wire $ne$ls180.v:3399$248_Y - attribute \src "ls180.v:3400.75-3400.133" - wire $ne$ls180.v:3400$249_Y - attribute \src "ls180.v:3524.8-3524.142" - wire $ne$ls180.v:3524$271_Y - attribute \src "ls180.v:3556.75-3556.133" - wire $ne$ls180.v:3556$278_Y - attribute \src "ls180.v:3557.75-3557.133" - wire $ne$ls180.v:3557$279_Y - attribute \src "ls180.v:3681.8-3681.142" - wire $ne$ls180.v:3681$301_Y - attribute \src "ls180.v:3713.75-3713.133" - wire $ne$ls180.v:3713$308_Y - attribute \src "ls180.v:3714.75-3714.133" - wire $ne$ls180.v:3714$309_Y - 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$xor$ls180.v:5149$968_Y - attribute \src "ls180.v:5149.205-5149.277" - wire $xor$ls180.v:5149$969_Y - attribute \src "ls180.v:5149.164-5149.278" - wire $xor$ls180.v:5149$970_Y - attribute \src "ls180.v:5150.360-5150.432" - wire $xor$ls180.v:5150$971_Y - attribute \src "ls180.v:5150.205-5150.277" - wire $xor$ls180.v:5150$972_Y - attribute \src "ls180.v:5150.164-5150.278" - wire $xor$ls180.v:5150$973_Y - attribute \src "ls180.v:5151.360-5151.432" - wire $xor$ls180.v:5151$974_Y - attribute \src "ls180.v:5151.205-5151.277" - wire $xor$ls180.v:5151$975_Y - attribute \src "ls180.v:5151.164-5151.278" - wire $xor$ls180.v:5151$976_Y - attribute \src "ls180.v:5152.360-5152.432" - wire $xor$ls180.v:5152$977_Y - attribute \src "ls180.v:5152.205-5152.277" - wire $xor$ls180.v:5152$978_Y - attribute \src "ls180.v:5152.164-5152.278" - wire $xor$ls180.v:5152$979_Y - attribute \src "ls180.v:5173.899-5173.983" - wire $xor$ls180.v:5173$993_Y - attribute \src "ls180.v:5173.634-5173.718" - wire $xor$ls180.v:5173$994_Y - attribute \src "ls180.v:5173.588-5173.719" - wire $xor$ls180.v:5173$995_Y - attribute \src "ls180.v:5173.234-5173.318" - wire $xor$ls180.v:5173$996_Y - attribute \src "ls180.v:5173.187-5173.319" - wire $xor$ls180.v:5173$997_Y - attribute \src "ls180.v:5174.588-5174.719" - wire $xor$ls180.v:5174$1000_Y - attribute \src "ls180.v:5174.234-5174.318" - wire $xor$ls180.v:5174$1001_Y - attribute \src "ls180.v:5174.187-5174.319" - wire $xor$ls180.v:5174$1002_Y - attribute \src "ls180.v:5174.899-5174.983" - wire $xor$ls180.v:5174$998_Y - attribute \src "ls180.v:5174.634-5174.718" - wire $xor$ls180.v:5174$999_Y - attribute \src "ls180.v:5183.899-5183.983" - wire $xor$ls180.v:5183$1004_Y - attribute \src "ls180.v:5183.634-5183.718" - wire $xor$ls180.v:5183$1005_Y - attribute \src "ls180.v:5183.588-5183.719" - wire $xor$ls180.v:5183$1006_Y - attribute \src "ls180.v:5183.234-5183.318" - wire $xor$ls180.v:5183$1007_Y - attribute \src "ls180.v:5183.187-5183.319" - wire $xor$ls180.v:5183$1008_Y - attribute \src "ls180.v:5184.899-5184.983" - wire $xor$ls180.v:5184$1009_Y - attribute \src "ls180.v:5184.634-5184.718" - wire $xor$ls180.v:5184$1010_Y - attribute \src "ls180.v:5184.588-5184.719" - wire $xor$ls180.v:5184$1011_Y - attribute \src "ls180.v:5184.234-5184.318" - wire $xor$ls180.v:5184$1012_Y - attribute \src "ls180.v:5184.187-5184.319" - wire $xor$ls180.v:5184$1013_Y - attribute \src "ls180.v:5193.899-5193.983" - wire $xor$ls180.v:5193$1015_Y - attribute \src "ls180.v:5193.634-5193.718" - wire $xor$ls180.v:5193$1016_Y - attribute \src "ls180.v:5193.588-5193.719" - wire $xor$ls180.v:5193$1017_Y - attribute \src "ls180.v:5193.234-5193.318" - wire $xor$ls180.v:5193$1018_Y - attribute \src "ls180.v:5193.187-5193.319" - wire $xor$ls180.v:5193$1019_Y - attribute \src "ls180.v:5194.899-5194.983" - wire $xor$ls180.v:5194$1020_Y - attribute \src "ls180.v:5194.634-5194.718" - wire $xor$ls180.v:5194$1021_Y - attribute \src "ls180.v:5194.588-5194.719" - wire $xor$ls180.v:5194$1022_Y - attribute \src "ls180.v:5194.234-5194.318" - wire $xor$ls180.v:5194$1023_Y - attribute \src "ls180.v:5194.187-5194.319" - wire $xor$ls180.v:5194$1024_Y - attribute \src "ls180.v:5203.899-5203.983" - wire $xor$ls180.v:5203$1026_Y - attribute \src "ls180.v:5203.634-5203.718" - wire $xor$ls180.v:5203$1027_Y - attribute \src "ls180.v:5203.588-5203.719" - wire $xor$ls180.v:5203$1028_Y - attribute \src "ls180.v:5203.234-5203.318" - wire $xor$ls180.v:5203$1029_Y - attribute \src "ls180.v:5203.187-5203.319" - wire $xor$ls180.v:5203$1030_Y - attribute \src "ls180.v:5204.899-5204.983" - wire $xor$ls180.v:5204$1031_Y - attribute \src "ls180.v:5204.634-5204.718" - wire $xor$ls180.v:5204$1032_Y - attribute \src "ls180.v:5204.588-5204.719" - wire $xor$ls180.v:5204$1033_Y - attribute \src "ls180.v:5204.234-5204.318" - wire $xor$ls180.v:5204$1034_Y - attribute \src "ls180.v:5204.187-5204.319" - wire $xor$ls180.v:5204$1035_Y - attribute \src "ls180.v:5355.879-5355.961" - wire $xor$ls180.v:5355$1068_Y - attribute \src "ls180.v:5355.620-5355.702" - wire $xor$ls180.v:5355$1069_Y - attribute \src "ls180.v:5355.575-5355.703" - wire $xor$ls180.v:5355$1070_Y - attribute \src "ls180.v:5355.229-5355.311" - wire $xor$ls180.v:5355$1071_Y - attribute \src "ls180.v:5355.183-5355.312" - wire $xor$ls180.v:5355$1072_Y - attribute \src "ls180.v:5356.879-5356.961" - wire $xor$ls180.v:5356$1073_Y - attribute \src "ls180.v:5356.620-5356.702" - wire $xor$ls180.v:5356$1074_Y - attribute \src "ls180.v:5356.575-5356.703" - wire $xor$ls180.v:5356$1075_Y - attribute \src "ls180.v:5356.229-5356.311" - wire $xor$ls180.v:5356$1076_Y - attribute \src "ls180.v:5356.183-5356.312" - wire $xor$ls180.v:5356$1077_Y - attribute \src "ls180.v:5365.879-5365.961" - wire $xor$ls180.v:5365$1079_Y - attribute \src "ls180.v:5365.620-5365.702" - wire $xor$ls180.v:5365$1080_Y - attribute \src "ls180.v:5365.575-5365.703" - wire $xor$ls180.v:5365$1081_Y - attribute \src "ls180.v:5365.229-5365.311" - wire $xor$ls180.v:5365$1082_Y - attribute \src "ls180.v:5365.183-5365.312" - wire $xor$ls180.v:5365$1083_Y - attribute \src "ls180.v:5366.879-5366.961" - wire $xor$ls180.v:5366$1084_Y - attribute \src "ls180.v:5366.620-5366.702" - wire $xor$ls180.v:5366$1085_Y - attribute \src "ls180.v:5366.575-5366.703" - wire $xor$ls180.v:5366$1086_Y - attribute \src "ls180.v:5366.229-5366.311" - wire $xor$ls180.v:5366$1087_Y - attribute \src "ls180.v:5366.183-5366.312" - wire $xor$ls180.v:5366$1088_Y - attribute \src "ls180.v:5375.879-5375.961" - wire $xor$ls180.v:5375$1090_Y - attribute \src "ls180.v:5375.620-5375.702" - wire $xor$ls180.v:5375$1091_Y - attribute \src "ls180.v:5375.575-5375.703" - wire $xor$ls180.v:5375$1092_Y - attribute \src "ls180.v:5375.229-5375.311" - wire $xor$ls180.v:5375$1093_Y - attribute \src "ls180.v:5375.183-5375.312" - wire $xor$ls180.v:5375$1094_Y - attribute \src "ls180.v:5376.879-5376.961" - wire $xor$ls180.v:5376$1095_Y - attribute \src "ls180.v:5376.620-5376.702" - wire $xor$ls180.v:5376$1096_Y - attribute \src "ls180.v:5376.575-5376.703" - wire $xor$ls180.v:5376$1097_Y - attribute \src "ls180.v:5376.229-5376.311" - wire $xor$ls180.v:5376$1098_Y - attribute \src "ls180.v:5376.183-5376.312" - wire $xor$ls180.v:5376$1099_Y - attribute \src "ls180.v:5385.879-5385.961" - wire $xor$ls180.v:5385$1101_Y - attribute \src "ls180.v:5385.620-5385.702" - wire $xor$ls180.v:5385$1102_Y - attribute \src "ls180.v:5385.575-5385.703" - wire $xor$ls180.v:5385$1103_Y - attribute \src "ls180.v:5385.229-5385.311" - wire $xor$ls180.v:5385$1104_Y - attribute \src "ls180.v:5385.183-5385.312" - wire $xor$ls180.v:5385$1105_Y - attribute \src "ls180.v:5386.879-5386.961" - wire $xor$ls180.v:5386$1106_Y - attribute \src "ls180.v:5386.620-5386.702" - wire $xor$ls180.v:5386$1107_Y - attribute \src "ls180.v:5386.575-5386.703" - wire $xor$ls180.v:5386$1108_Y - attribute \src "ls180.v:5386.229-5386.311" - wire $xor$ls180.v:5386$1109_Y - attribute \src "ls180.v:5386.183-5386.312" - wire $xor$ls180.v:5386$1110_Y - attribute \src "ls180.v:1857.11-1857.42" - wire width 3 \builder_bankmachine0_next_state - attribute \src "ls180.v:1856.11-1856.37" - wire width 3 \builder_bankmachine0_state - attribute \src "ls180.v:1859.11-1859.42" - wire width 3 \builder_bankmachine1_next_state - attribute \src "ls180.v:1858.11-1858.37" - wire width 3 \builder_bankmachine1_state - attribute \src "ls180.v:1861.11-1861.42" - wire width 3 \builder_bankmachine2_next_state - attribute \src "ls180.v:1860.11-1860.37" - wire width 3 \builder_bankmachine2_state - attribute \src "ls180.v:1863.11-1863.42" - wire width 3 \builder_bankmachine3_next_state - attribute \src "ls180.v:1862.11-1862.37" - wire width 3 \builder_bankmachine3_state - attribute \src "ls180.v:2716.5-2716.34" - wire \builder_comb_rhs_array_muxed0 - attribute \src "ls180.v:2717.12-2717.41" - wire width 13 \builder_comb_rhs_array_muxed1 - attribute \src "ls180.v:2729.5-2729.35" - wire \builder_comb_rhs_array_muxed10 - attribute \src "ls180.v:2730.5-2730.35" - wire \builder_comb_rhs_array_muxed11 - attribute \src "ls180.v:2734.12-2734.42" - wire width 22 \builder_comb_rhs_array_muxed12 - attribute \src "ls180.v:2735.5-2735.35" - wire \builder_comb_rhs_array_muxed13 - attribute \src "ls180.v:2736.5-2736.35" - wire \builder_comb_rhs_array_muxed14 - attribute \src "ls180.v:2737.12-2737.42" - wire width 22 \builder_comb_rhs_array_muxed15 - attribute \src "ls180.v:2738.5-2738.35" - wire \builder_comb_rhs_array_muxed16 - attribute \src "ls180.v:2739.5-2739.35" - wire \builder_comb_rhs_array_muxed17 - attribute \src "ls180.v:2740.12-2740.42" - wire width 22 \builder_comb_rhs_array_muxed18 - attribute \src "ls180.v:2741.5-2741.35" - wire \builder_comb_rhs_array_muxed19 - attribute \src "ls180.v:2718.11-2718.40" - wire width 2 \builder_comb_rhs_array_muxed2 - attribute \src "ls180.v:2742.5-2742.35" - wire \builder_comb_rhs_array_muxed20 - attribute \src "ls180.v:2743.12-2743.42" - wire width 22 \builder_comb_rhs_array_muxed21 - attribute \src "ls180.v:2744.5-2744.35" - wire \builder_comb_rhs_array_muxed22 - attribute \src "ls180.v:2745.5-2745.35" - wire \builder_comb_rhs_array_muxed23 - attribute \src "ls180.v:2746.12-2746.42" - wire width 32 \builder_comb_rhs_array_muxed24 - attribute \src "ls180.v:2747.12-2747.42" - wire width 64 \builder_comb_rhs_array_muxed25 - attribute \src "ls180.v:2748.11-2748.41" - wire width 8 \builder_comb_rhs_array_muxed26 - attribute \src "ls180.v:2749.5-2749.35" - wire \builder_comb_rhs_array_muxed27 - attribute \src "ls180.v:2750.5-2750.35" - wire \builder_comb_rhs_array_muxed28 - attribute \src "ls180.v:2751.5-2751.35" - wire \builder_comb_rhs_array_muxed29 - attribute \src "ls180.v:2719.5-2719.34" - wire \builder_comb_rhs_array_muxed3 - attribute \src "ls180.v:2752.11-2752.41" - wire width 3 \builder_comb_rhs_array_muxed30 - attribute \src "ls180.v:2753.11-2753.41" - wire width 2 \builder_comb_rhs_array_muxed31 - attribute \src "ls180.v:2720.5-2720.34" - wire \builder_comb_rhs_array_muxed4 - attribute \src "ls180.v:2721.5-2721.34" - wire \builder_comb_rhs_array_muxed5 - attribute \src "ls180.v:2725.5-2725.34" - wire \builder_comb_rhs_array_muxed6 - attribute \src "ls180.v:2726.12-2726.41" - wire width 13 \builder_comb_rhs_array_muxed7 - attribute \src "ls180.v:2727.11-2727.40" - wire width 2 \builder_comb_rhs_array_muxed8 - attribute \src "ls180.v:2728.5-2728.34" - wire \builder_comb_rhs_array_muxed9 - attribute \src "ls180.v:2722.5-2722.32" - wire \builder_comb_t_array_muxed0 - attribute \src "ls180.v:2723.5-2723.32" - wire \builder_comb_t_array_muxed1 - attribute \src "ls180.v:2724.5-2724.32" - wire \builder_comb_t_array_muxed2 - attribute \src "ls180.v:2731.5-2731.32" - wire \builder_comb_t_array_muxed3 - attribute \src "ls180.v:2732.5-2732.32" - wire \builder_comb_t_array_muxed4 - attribute \src "ls180.v:2733.5-2733.32" - wire \builder_comb_t_array_muxed5 - attribute \src "ls180.v:1843.5-1843.34" - wire \builder_converter0_next_state - attribute \src "ls180.v:1842.5-1842.29" - wire \builder_converter0_state - attribute \src "ls180.v:1847.5-1847.34" - wire \builder_converter1_next_state - attribute \src "ls180.v:1846.5-1846.29" - wire \builder_converter1_state - attribute \src "ls180.v:1851.5-1851.34" - wire \builder_converter2_next_state - attribute \src "ls180.v:1850.5-1850.29" - wire \builder_converter2_state - attribute \src "ls180.v:1888.5-1888.33" - wire \builder_converter_next_state - attribute \src "ls180.v:1887.5-1887.28" - wire \builder_converter_state - attribute \src "ls180.v:2016.12-2016.25" - wire width 20 \builder_count - attribute \src "ls180.v:2704.13-2704.41" - wire width 14 \builder_csr_interconnect_adr - attribute \src "ls180.v:2707.12-2707.42" - wire width 8 \builder_csr_interconnect_dat_r - attribute \src "ls180.v:2706.12-2706.42" - wire width 8 \builder_csr_interconnect_dat_w - attribute \src "ls180.v:2705.6-2705.33" - wire \builder_csr_interconnect_we - attribute \src "ls180.v:2054.12-2054.42" - wire width 8 \builder_csrbank0_bus_errors0_r - attribute \src "ls180.v:2053.6-2053.37" - wire \builder_csrbank0_bus_errors0_re - attribute \src "ls180.v:2056.12-2056.42" - wire width 8 \builder_csrbank0_bus_errors0_w - attribute \src "ls180.v:2055.6-2055.37" - wire \builder_csrbank0_bus_errors0_we - attribute \src "ls180.v:2050.12-2050.42" - wire width 8 \builder_csrbank0_bus_errors1_r - attribute \src "ls180.v:2049.6-2049.37" - wire \builder_csrbank0_bus_errors1_re - attribute \src "ls180.v:2052.12-2052.42" - wire width 8 \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:2051.6-2051.37" - wire \builder_csrbank0_bus_errors1_we - attribute \src "ls180.v:2046.12-2046.42" - wire width 8 \builder_csrbank0_bus_errors2_r - attribute \src "ls180.v:2045.6-2045.37" - wire \builder_csrbank0_bus_errors2_re - attribute \src "ls180.v:2048.12-2048.42" - wire width 8 \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:2047.6-2047.37" - wire \builder_csrbank0_bus_errors2_we - attribute \src "ls180.v:2042.12-2042.42" - wire width 8 \builder_csrbank0_bus_errors3_r - attribute \src "ls180.v:2041.6-2041.37" - wire \builder_csrbank0_bus_errors3_re - attribute \src "ls180.v:2044.12-2044.42" - wire width 8 \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:2043.6-2043.37" - wire \builder_csrbank0_bus_errors3_we - attribute \src "ls180.v:2022.6-2022.31" - wire \builder_csrbank0_reset0_r - attribute \src "ls180.v:2021.6-2021.32" - wire \builder_csrbank0_reset0_re - attribute \src "ls180.v:2024.6-2024.31" - wire \builder_csrbank0_reset0_w - attribute \src "ls180.v:2023.6-2023.32" - wire \builder_csrbank0_reset0_we - attribute \src "ls180.v:2038.12-2038.39" - wire width 8 \builder_csrbank0_scratch0_r - attribute \src "ls180.v:2037.6-2037.34" - wire \builder_csrbank0_scratch0_re - attribute \src "ls180.v:2040.12-2040.39" - wire width 8 \builder_csrbank0_scratch0_w - attribute \src "ls180.v:2039.6-2039.34" - wire \builder_csrbank0_scratch0_we - attribute \src "ls180.v:2034.12-2034.39" - wire width 8 \builder_csrbank0_scratch1_r - attribute \src "ls180.v:2033.6-2033.34" - wire \builder_csrbank0_scratch1_re - attribute \src "ls180.v:2036.12-2036.39" - wire width 8 \builder_csrbank0_scratch1_w - attribute \src "ls180.v:2035.6-2035.34" - wire \builder_csrbank0_scratch1_we - attribute \src "ls180.v:2030.12-2030.39" - wire width 8 \builder_csrbank0_scratch2_r - attribute \src "ls180.v:2029.6-2029.34" - wire \builder_csrbank0_scratch2_re - attribute \src "ls180.v:2032.12-2032.39" - wire width 8 \builder_csrbank0_scratch2_w - attribute \src "ls180.v:2031.6-2031.34" - wire \builder_csrbank0_scratch2_we - attribute \src "ls180.v:2026.12-2026.39" - wire width 8 \builder_csrbank0_scratch3_r - attribute \src "ls180.v:2025.6-2025.34" - wire \builder_csrbank0_scratch3_re - attribute \src "ls180.v:2028.12-2028.39" - wire width 8 \builder_csrbank0_scratch3_w - attribute \src "ls180.v:2027.6-2027.34" - wire \builder_csrbank0_scratch3_we - attribute \src "ls180.v:2057.6-2057.26" - wire \builder_csrbank0_sel - attribute \src "ls180.v:2528.12-2528.40" - wire width 8 \builder_csrbank10_control0_r - attribute \src "ls180.v:2527.6-2527.35" - wire \builder_csrbank10_control0_re - attribute \src "ls180.v:2530.12-2530.40" - wire width 8 \builder_csrbank10_control0_w - attribute \src "ls180.v:2529.6-2529.35" - wire \builder_csrbank10_control0_we - attribute \src "ls180.v:2524.12-2524.40" - wire width 8 \builder_csrbank10_control1_r - attribute \src "ls180.v:2523.6-2523.35" - wire \builder_csrbank10_control1_re - attribute \src "ls180.v:2526.12-2526.40" - wire width 8 \builder_csrbank10_control1_w - attribute \src "ls180.v:2525.6-2525.35" - wire \builder_csrbank10_control1_we - attribute \src "ls180.v:2544.6-2544.29" - wire \builder_csrbank10_cs0_r - attribute \src "ls180.v:2543.6-2543.30" - wire \builder_csrbank10_cs0_re - attribute \src "ls180.v:2546.6-2546.29" - wire \builder_csrbank10_cs0_w - attribute \src "ls180.v:2545.6-2545.30" - wire \builder_csrbank10_cs0_we - attribute \src "ls180.v:2548.6-2548.35" - wire \builder_csrbank10_loopback0_r - attribute \src "ls180.v:2547.6-2547.36" - wire \builder_csrbank10_loopback0_re - attribute \src "ls180.v:2550.6-2550.35" - wire \builder_csrbank10_loopback0_w - attribute \src "ls180.v:2549.6-2549.36" - wire \builder_csrbank10_loopback0_we - attribute \src "ls180.v:2540.12-2540.36" - wire width 8 \builder_csrbank10_miso_r - attribute \src "ls180.v:2539.6-2539.31" - wire \builder_csrbank10_miso_re - attribute \src "ls180.v:2542.12-2542.36" - wire width 8 \builder_csrbank10_miso_w - attribute \src "ls180.v:2541.6-2541.31" - wire \builder_csrbank10_miso_we - attribute \src "ls180.v:2536.12-2536.37" - wire width 8 \builder_csrbank10_mosi0_r - attribute \src "ls180.v:2535.6-2535.32" - wire \builder_csrbank10_mosi0_re - attribute \src "ls180.v:2538.12-2538.37" - wire width 8 \builder_csrbank10_mosi0_w - attribute \src "ls180.v:2537.6-2537.32" - wire \builder_csrbank10_mosi0_we - attribute \src "ls180.v:2551.6-2551.27" - wire \builder_csrbank10_sel - attribute \src "ls180.v:2532.6-2532.32" - wire \builder_csrbank10_status_r - attribute \src "ls180.v:2531.6-2531.33" - wire \builder_csrbank10_status_re - attribute \src "ls180.v:2534.6-2534.32" - wire \builder_csrbank10_status_w - attribute \src "ls180.v:2533.6-2533.33" - wire \builder_csrbank10_status_we - attribute \src "ls180.v:2589.12-2589.44" - wire width 8 \builder_csrbank11_clk_divider0_r - attribute \src "ls180.v:2588.6-2588.39" - wire \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:2591.12-2591.44" - wire width 8 \builder_csrbank11_clk_divider0_w - attribute \src "ls180.v:2590.6-2590.39" - wire \builder_csrbank11_clk_divider0_we - attribute \src "ls180.v:2585.12-2585.44" - wire width 8 \builder_csrbank11_clk_divider1_r - attribute \src "ls180.v:2584.6-2584.39" - wire \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:2587.12-2587.44" - wire width 8 \builder_csrbank11_clk_divider1_w - attribute \src "ls180.v:2586.6-2586.39" - wire \builder_csrbank11_clk_divider1_we - attribute \src "ls180.v:2561.12-2561.40" - wire width 8 \builder_csrbank11_control0_r - attribute \src "ls180.v:2560.6-2560.35" - wire \builder_csrbank11_control0_re - attribute \src "ls180.v:2563.12-2563.40" - wire width 8 \builder_csrbank11_control0_w - attribute \src "ls180.v:2562.6-2562.35" - wire \builder_csrbank11_control0_we - attribute \src "ls180.v:2557.12-2557.40" - wire width 8 \builder_csrbank11_control1_r - attribute \src "ls180.v:2556.6-2556.35" - wire \builder_csrbank11_control1_re - attribute \src "ls180.v:2559.12-2559.40" - wire width 8 \builder_csrbank11_control1_w - attribute \src "ls180.v:2558.6-2558.35" - wire \builder_csrbank11_control1_we - attribute \src "ls180.v:2577.6-2577.29" - wire \builder_csrbank11_cs0_r - attribute \src "ls180.v:2576.6-2576.30" - wire \builder_csrbank11_cs0_re - attribute \src "ls180.v:2579.6-2579.29" - wire \builder_csrbank11_cs0_w - attribute \src "ls180.v:2578.6-2578.30" - wire \builder_csrbank11_cs0_we - attribute \src "ls180.v:2581.6-2581.35" - wire \builder_csrbank11_loopback0_r - attribute \src "ls180.v:2580.6-2580.36" - wire \builder_csrbank11_loopback0_re - attribute \src "ls180.v:2583.6-2583.35" - wire \builder_csrbank11_loopback0_w - attribute \src "ls180.v:2582.6-2582.36" - wire \builder_csrbank11_loopback0_we - attribute \src "ls180.v:2573.12-2573.36" - wire width 8 \builder_csrbank11_miso_r - attribute \src "ls180.v:2572.6-2572.31" - wire \builder_csrbank11_miso_re - attribute \src "ls180.v:2575.12-2575.36" - wire width 8 \builder_csrbank11_miso_w - attribute \src "ls180.v:2574.6-2574.31" - wire \builder_csrbank11_miso_we - attribute \src "ls180.v:2569.12-2569.37" - wire width 8 \builder_csrbank11_mosi0_r - attribute \src "ls180.v:2568.6-2568.32" - wire \builder_csrbank11_mosi0_re - attribute \src "ls180.v:2571.12-2571.37" - wire width 8 \builder_csrbank11_mosi0_w - attribute \src "ls180.v:2570.6-2570.32" - wire \builder_csrbank11_mosi0_we - attribute \src "ls180.v:2592.6-2592.27" - wire \builder_csrbank11_sel - attribute \src "ls180.v:2565.6-2565.32" - wire \builder_csrbank11_status_r - attribute \src "ls180.v:2564.6-2564.33" - wire \builder_csrbank11_status_re - attribute \src "ls180.v:2567.6-2567.32" - wire \builder_csrbank11_status_w - attribute \src "ls180.v:2566.6-2566.33" - wire \builder_csrbank11_status_we - attribute \src "ls180.v:2630.6-2630.29" - wire \builder_csrbank12_en0_r - attribute \src "ls180.v:2629.6-2629.30" - wire \builder_csrbank12_en0_re - attribute \src "ls180.v:2632.6-2632.29" - wire \builder_csrbank12_en0_w - attribute \src "ls180.v:2631.6-2631.30" - wire \builder_csrbank12_en0_we - attribute \src "ls180.v:2654.6-2654.36" - wire \builder_csrbank12_ev_enable0_r - attribute \src "ls180.v:2653.6-2653.37" - wire \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:2656.6-2656.36" - wire \builder_csrbank12_ev_enable0_w - attribute \src "ls180.v:2655.6-2655.37" - wire \builder_csrbank12_ev_enable0_we - attribute \src "ls180.v:2610.12-2610.37" - wire width 8 \builder_csrbank12_load0_r - attribute \src "ls180.v:2609.6-2609.32" - wire \builder_csrbank12_load0_re - attribute \src "ls180.v:2612.12-2612.37" - wire width 8 \builder_csrbank12_load0_w - attribute \src "ls180.v:2611.6-2611.32" - wire \builder_csrbank12_load0_we - attribute \src "ls180.v:2606.12-2606.37" - wire width 8 \builder_csrbank12_load1_r - attribute \src "ls180.v:2605.6-2605.32" - wire \builder_csrbank12_load1_re - attribute \src "ls180.v:2608.12-2608.37" - wire width 8 \builder_csrbank12_load1_w - attribute \src "ls180.v:2607.6-2607.32" - wire \builder_csrbank12_load1_we - attribute \src "ls180.v:2602.12-2602.37" - wire width 8 \builder_csrbank12_load2_r - attribute \src "ls180.v:2601.6-2601.32" - wire \builder_csrbank12_load2_re - attribute \src "ls180.v:2604.12-2604.37" - wire width 8 \builder_csrbank12_load2_w - attribute \src "ls180.v:2603.6-2603.32" - wire \builder_csrbank12_load2_we - attribute \src "ls180.v:2598.12-2598.37" - wire width 8 \builder_csrbank12_load3_r - attribute \src "ls180.v:2597.6-2597.32" - wire \builder_csrbank12_load3_re - attribute \src "ls180.v:2600.12-2600.37" - wire width 8 \builder_csrbank12_load3_w - attribute \src "ls180.v:2599.6-2599.32" - wire \builder_csrbank12_load3_we - attribute \src "ls180.v:2626.12-2626.39" - wire width 8 \builder_csrbank12_reload0_r - attribute \src "ls180.v:2625.6-2625.34" - wire \builder_csrbank12_reload0_re - attribute \src "ls180.v:2628.12-2628.39" - wire width 8 \builder_csrbank12_reload0_w - attribute \src "ls180.v:2627.6-2627.34" - wire \builder_csrbank12_reload0_we - attribute \src "ls180.v:2622.12-2622.39" - wire width 8 \builder_csrbank12_reload1_r - attribute \src "ls180.v:2621.6-2621.34" - wire \builder_csrbank12_reload1_re - attribute \src "ls180.v:2624.12-2624.39" - wire width 8 \builder_csrbank12_reload1_w - attribute \src "ls180.v:2623.6-2623.34" - wire \builder_csrbank12_reload1_we - attribute \src "ls180.v:2618.12-2618.39" - wire width 8 \builder_csrbank12_reload2_r - attribute \src "ls180.v:2617.6-2617.34" - wire \builder_csrbank12_reload2_re - attribute \src "ls180.v:2620.12-2620.39" - wire width 8 \builder_csrbank12_reload2_w - attribute \src "ls180.v:2619.6-2619.34" - wire \builder_csrbank12_reload2_we - attribute \src "ls180.v:2614.12-2614.39" - wire width 8 \builder_csrbank12_reload3_r - attribute \src "ls180.v:2613.6-2613.34" - wire \builder_csrbank12_reload3_re - attribute \src "ls180.v:2616.12-2616.39" - wire width 8 \builder_csrbank12_reload3_w - attribute \src "ls180.v:2615.6-2615.34" - wire \builder_csrbank12_reload3_we - attribute \src "ls180.v:2657.6-2657.27" - wire \builder_csrbank12_sel - attribute \src "ls180.v:2634.6-2634.39" - wire \builder_csrbank12_update_value0_r - attribute \src "ls180.v:2633.6-2633.40" - wire \builder_csrbank12_update_value0_re - attribute \src "ls180.v:2636.6-2636.39" - wire \builder_csrbank12_update_value0_w - attribute \src "ls180.v:2635.6-2635.40" - wire \builder_csrbank12_update_value0_we - attribute \src "ls180.v:2650.12-2650.38" - wire width 8 \builder_csrbank12_value0_r - attribute \src "ls180.v:2649.6-2649.33" - wire \builder_csrbank12_value0_re - attribute \src "ls180.v:2652.12-2652.38" - wire width 8 \builder_csrbank12_value0_w - attribute \src "ls180.v:2651.6-2651.33" - wire \builder_csrbank12_value0_we - attribute \src "ls180.v:2646.12-2646.38" - wire width 8 \builder_csrbank12_value1_r - attribute \src "ls180.v:2645.6-2645.33" - wire \builder_csrbank12_value1_re - attribute \src "ls180.v:2648.12-2648.38" - wire width 8 \builder_csrbank12_value1_w - attribute \src "ls180.v:2647.6-2647.33" - wire \builder_csrbank12_value1_we - attribute \src "ls180.v:2642.12-2642.38" - wire width 8 \builder_csrbank12_value2_r - attribute \src "ls180.v:2641.6-2641.33" - wire \builder_csrbank12_value2_re - attribute \src "ls180.v:2644.12-2644.38" - wire width 8 \builder_csrbank12_value2_w - attribute \src "ls180.v:2643.6-2643.33" - wire \builder_csrbank12_value2_we - attribute \src "ls180.v:2638.12-2638.38" - wire width 8 \builder_csrbank12_value3_r - attribute \src "ls180.v:2637.6-2637.33" - wire \builder_csrbank12_value3_re - attribute \src "ls180.v:2640.12-2640.38" - wire width 8 \builder_csrbank12_value3_w - attribute \src "ls180.v:2639.6-2639.33" - wire \builder_csrbank12_value3_we - attribute \src "ls180.v:2671.12-2671.42" - wire width 2 \builder_csrbank13_ev_enable0_r - attribute \src "ls180.v:2670.6-2670.37" - wire \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:2673.12-2673.42" - wire width 2 \builder_csrbank13_ev_enable0_w - attribute \src "ls180.v:2672.6-2672.37" - wire \builder_csrbank13_ev_enable0_we - attribute \src "ls180.v:2667.6-2667.33" - wire \builder_csrbank13_rxempty_r - attribute \src "ls180.v:2666.6-2666.34" - wire \builder_csrbank13_rxempty_re - attribute \src "ls180.v:2669.6-2669.33" - wire \builder_csrbank13_rxempty_w - attribute \src "ls180.v:2668.6-2668.34" - wire \builder_csrbank13_rxempty_we - attribute \src "ls180.v:2679.6-2679.32" - wire \builder_csrbank13_rxfull_r - attribute \src "ls180.v:2678.6-2678.33" - wire \builder_csrbank13_rxfull_re - attribute \src "ls180.v:2681.6-2681.32" - wire \builder_csrbank13_rxfull_w - attribute \src "ls180.v:2680.6-2680.33" - wire \builder_csrbank13_rxfull_we - attribute \src "ls180.v:2682.6-2682.27" - wire \builder_csrbank13_sel - attribute \src "ls180.v:2675.6-2675.33" - wire \builder_csrbank13_txempty_r - attribute \src "ls180.v:2674.6-2674.34" - wire \builder_csrbank13_txempty_re - attribute \src "ls180.v:2677.6-2677.33" - wire \builder_csrbank13_txempty_w - attribute \src "ls180.v:2676.6-2676.34" - wire \builder_csrbank13_txempty_we - attribute \src "ls180.v:2663.6-2663.32" - wire \builder_csrbank13_txfull_r - attribute \src "ls180.v:2662.6-2662.33" - wire \builder_csrbank13_txfull_re - attribute \src "ls180.v:2665.6-2665.32" - wire \builder_csrbank13_txfull_w - attribute \src "ls180.v:2664.6-2664.33" - wire \builder_csrbank13_txfull_we - attribute \src "ls180.v:2703.6-2703.27" - wire \builder_csrbank14_sel - attribute \src "ls180.v:2700.12-2700.44" - wire width 8 \builder_csrbank14_tuning_word0_r - attribute \src "ls180.v:2699.6-2699.39" - wire \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:2702.12-2702.44" - wire width 8 \builder_csrbank14_tuning_word0_w - attribute \src "ls180.v:2701.6-2701.39" - wire \builder_csrbank14_tuning_word0_we - attribute \src "ls180.v:2696.12-2696.44" - wire width 8 \builder_csrbank14_tuning_word1_r - attribute \src "ls180.v:2695.6-2695.39" - wire \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:2698.12-2698.44" - wire width 8 \builder_csrbank14_tuning_word1_w - attribute \src "ls180.v:2697.6-2697.39" - wire \builder_csrbank14_tuning_word1_we - attribute \src "ls180.v:2692.12-2692.44" - wire width 8 \builder_csrbank14_tuning_word2_r - attribute \src "ls180.v:2691.6-2691.39" - wire \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:2694.12-2694.44" - wire width 8 \builder_csrbank14_tuning_word2_w - attribute \src "ls180.v:2693.6-2693.39" - wire \builder_csrbank14_tuning_word2_we - attribute \src "ls180.v:2688.12-2688.44" - wire width 8 \builder_csrbank14_tuning_word3_r - attribute \src "ls180.v:2687.6-2687.39" - wire \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:2690.12-2690.44" - wire width 8 \builder_csrbank14_tuning_word3_w - attribute \src "ls180.v:2689.6-2689.39" - wire \builder_csrbank14_tuning_word3_we - attribute \src "ls180.v:2075.12-2075.34" - wire width 8 \builder_csrbank1_in0_r - attribute \src "ls180.v:2074.6-2074.29" - wire \builder_csrbank1_in0_re - attribute \src "ls180.v:2077.12-2077.34" - wire width 8 \builder_csrbank1_in0_w - attribute \src "ls180.v:2076.6-2076.29" - wire \builder_csrbank1_in0_we - attribute \src "ls180.v:2071.12-2071.34" - wire width 8 \builder_csrbank1_in1_r - attribute \src "ls180.v:2070.6-2070.29" - wire \builder_csrbank1_in1_re - attribute \src "ls180.v:2073.12-2073.34" - wire width 8 \builder_csrbank1_in1_w - attribute \src "ls180.v:2072.6-2072.29" - wire \builder_csrbank1_in1_we - attribute \src "ls180.v:2067.12-2067.34" - wire width 8 \builder_csrbank1_oe0_r - attribute \src "ls180.v:2066.6-2066.29" - wire \builder_csrbank1_oe0_re - attribute \src "ls180.v:2069.12-2069.34" - wire width 8 \builder_csrbank1_oe0_w - attribute \src "ls180.v:2068.6-2068.29" - wire \builder_csrbank1_oe0_we - attribute \src "ls180.v:2063.12-2063.34" - wire width 8 \builder_csrbank1_oe1_r - attribute \src "ls180.v:2062.6-2062.29" - wire \builder_csrbank1_oe1_re - attribute \src "ls180.v:2065.12-2065.34" - wire width 8 \builder_csrbank1_oe1_w - attribute \src "ls180.v:2064.6-2064.29" - wire \builder_csrbank1_oe1_we - attribute \src "ls180.v:2083.12-2083.35" - wire width 8 \builder_csrbank1_out0_r - attribute \src "ls180.v:2082.6-2082.30" - wire \builder_csrbank1_out0_re - attribute \src "ls180.v:2085.12-2085.35" - wire width 8 \builder_csrbank1_out0_w - attribute \src "ls180.v:2084.6-2084.30" - wire \builder_csrbank1_out0_we - attribute \src "ls180.v:2079.12-2079.35" - wire width 8 \builder_csrbank1_out1_r - attribute \src "ls180.v:2078.6-2078.30" - wire \builder_csrbank1_out1_re - attribute \src "ls180.v:2081.12-2081.35" - wire width 8 \builder_csrbank1_out1_w - attribute \src "ls180.v:2080.6-2080.30" - wire \builder_csrbank1_out1_we - attribute \src "ls180.v:2086.6-2086.26" - wire \builder_csrbank1_sel - attribute \src "ls180.v:2096.6-2096.26" - wire \builder_csrbank2_r_r - attribute \src "ls180.v:2095.6-2095.27" - wire \builder_csrbank2_r_re - attribute \src "ls180.v:2098.6-2098.26" - wire \builder_csrbank2_r_w - attribute \src "ls180.v:2097.6-2097.27" - wire \builder_csrbank2_r_we - attribute \src "ls180.v:2099.6-2099.26" - wire \builder_csrbank2_sel - attribute \src "ls180.v:2092.12-2092.33" - wire width 3 \builder_csrbank2_w0_r - attribute \src "ls180.v:2091.6-2091.28" - wire \builder_csrbank2_w0_re - attribute \src "ls180.v:2094.12-2094.33" - wire width 3 \builder_csrbank2_w0_w - attribute \src "ls180.v:2093.6-2093.28" - wire \builder_csrbank2_w0_we - attribute \src "ls180.v:2105.6-2105.32" - wire \builder_csrbank3_enable0_r - attribute \src "ls180.v:2104.6-2104.33" - wire \builder_csrbank3_enable0_re - attribute \src "ls180.v:2107.6-2107.32" - wire \builder_csrbank3_enable0_w - attribute \src "ls180.v:2106.6-2106.33" - wire \builder_csrbank3_enable0_we - attribute \src "ls180.v:2137.12-2137.38" - wire width 8 \builder_csrbank3_period0_r - attribute \src "ls180.v:2136.6-2136.33" - wire \builder_csrbank3_period0_re - attribute \src "ls180.v:2139.12-2139.38" - wire width 8 \builder_csrbank3_period0_w - attribute \src "ls180.v:2138.6-2138.33" - wire \builder_csrbank3_period0_we - attribute \src "ls180.v:2133.12-2133.38" - wire width 8 \builder_csrbank3_period1_r - attribute \src "ls180.v:2132.6-2132.33" - wire \builder_csrbank3_period1_re - attribute \src "ls180.v:2135.12-2135.38" - wire width 8 \builder_csrbank3_period1_w - attribute \src "ls180.v:2134.6-2134.33" - wire \builder_csrbank3_period1_we - attribute \src "ls180.v:2129.12-2129.38" - wire width 8 \builder_csrbank3_period2_r - attribute \src "ls180.v:2128.6-2128.33" - wire \builder_csrbank3_period2_re - attribute \src "ls180.v:2131.12-2131.38" - wire width 8 \builder_csrbank3_period2_w - attribute \src "ls180.v:2130.6-2130.33" - wire \builder_csrbank3_period2_we - attribute \src "ls180.v:2125.12-2125.38" - wire width 8 \builder_csrbank3_period3_r - attribute \src "ls180.v:2124.6-2124.33" - wire \builder_csrbank3_period3_re - attribute \src "ls180.v:2127.12-2127.38" - wire width 8 \builder_csrbank3_period3_w - attribute \src "ls180.v:2126.6-2126.33" - wire \builder_csrbank3_period3_we - attribute \src "ls180.v:2140.6-2140.26" - wire \builder_csrbank3_sel - attribute \src "ls180.v:2121.12-2121.37" - wire width 8 \builder_csrbank3_width0_r - attribute \src "ls180.v:2120.6-2120.32" - wire \builder_csrbank3_width0_re - attribute \src "ls180.v:2123.12-2123.37" - wire width 8 \builder_csrbank3_width0_w - attribute \src "ls180.v:2122.6-2122.32" - wire \builder_csrbank3_width0_we - attribute \src "ls180.v:2117.12-2117.37" - wire width 8 \builder_csrbank3_width1_r - attribute \src "ls180.v:2116.6-2116.32" - wire \builder_csrbank3_width1_re - attribute \src "ls180.v:2119.12-2119.37" - wire width 8 \builder_csrbank3_width1_w - attribute \src "ls180.v:2118.6-2118.32" - wire \builder_csrbank3_width1_we - attribute \src "ls180.v:2113.12-2113.37" - wire width 8 \builder_csrbank3_width2_r - attribute \src "ls180.v:2112.6-2112.32" - wire \builder_csrbank3_width2_re - attribute \src "ls180.v:2115.12-2115.37" - wire width 8 \builder_csrbank3_width2_w - attribute \src "ls180.v:2114.6-2114.32" - wire \builder_csrbank3_width2_we - attribute \src "ls180.v:2109.12-2109.37" - wire width 8 \builder_csrbank3_width3_r - attribute \src "ls180.v:2108.6-2108.32" - wire \builder_csrbank3_width3_re - attribute \src "ls180.v:2111.12-2111.37" - wire width 8 \builder_csrbank3_width3_w - attribute \src "ls180.v:2110.6-2110.32" - wire \builder_csrbank3_width3_we - attribute \src "ls180.v:2146.6-2146.32" - wire \builder_csrbank4_enable0_r - attribute \src "ls180.v:2145.6-2145.33" - wire \builder_csrbank4_enable0_re - attribute \src "ls180.v:2148.6-2148.32" - wire \builder_csrbank4_enable0_w - attribute \src "ls180.v:2147.6-2147.33" - wire \builder_csrbank4_enable0_we - attribute \src "ls180.v:2178.12-2178.38" - wire width 8 \builder_csrbank4_period0_r - attribute \src "ls180.v:2177.6-2177.33" - wire \builder_csrbank4_period0_re - attribute \src "ls180.v:2180.12-2180.38" - wire width 8 \builder_csrbank4_period0_w - attribute \src "ls180.v:2179.6-2179.33" - wire \builder_csrbank4_period0_we - attribute \src "ls180.v:2174.12-2174.38" - wire width 8 \builder_csrbank4_period1_r - attribute \src "ls180.v:2173.6-2173.33" - wire \builder_csrbank4_period1_re - attribute \src "ls180.v:2176.12-2176.38" - wire width 8 \builder_csrbank4_period1_w - attribute \src "ls180.v:2175.6-2175.33" - wire \builder_csrbank4_period1_we - attribute \src "ls180.v:2170.12-2170.38" - wire width 8 \builder_csrbank4_period2_r - attribute \src "ls180.v:2169.6-2169.33" - wire \builder_csrbank4_period2_re - attribute \src "ls180.v:2172.12-2172.38" - wire width 8 \builder_csrbank4_period2_w - attribute \src "ls180.v:2171.6-2171.33" - wire \builder_csrbank4_period2_we - attribute \src "ls180.v:2166.12-2166.38" - wire width 8 \builder_csrbank4_period3_r - attribute \src "ls180.v:2165.6-2165.33" - wire \builder_csrbank4_period3_re - attribute \src "ls180.v:2168.12-2168.38" - wire width 8 \builder_csrbank4_period3_w - attribute \src "ls180.v:2167.6-2167.33" - wire \builder_csrbank4_period3_we - attribute \src "ls180.v:2181.6-2181.26" - wire \builder_csrbank4_sel - attribute \src "ls180.v:2162.12-2162.37" - wire width 8 \builder_csrbank4_width0_r - attribute \src "ls180.v:2161.6-2161.32" - wire \builder_csrbank4_width0_re - attribute \src "ls180.v:2164.12-2164.37" - wire width 8 \builder_csrbank4_width0_w - attribute \src "ls180.v:2163.6-2163.32" - wire \builder_csrbank4_width0_we - attribute \src "ls180.v:2158.12-2158.37" - wire width 8 \builder_csrbank4_width1_r - attribute \src "ls180.v:2157.6-2157.32" - wire \builder_csrbank4_width1_re - attribute \src "ls180.v:2160.12-2160.37" - wire width 8 \builder_csrbank4_width1_w - attribute \src "ls180.v:2159.6-2159.32" - wire \builder_csrbank4_width1_we - attribute \src "ls180.v:2154.12-2154.37" - wire width 8 \builder_csrbank4_width2_r - attribute \src "ls180.v:2153.6-2153.32" - wire \builder_csrbank4_width2_re - attribute \src "ls180.v:2156.12-2156.37" - wire width 8 \builder_csrbank4_width2_w - attribute \src "ls180.v:2155.6-2155.32" - wire \builder_csrbank4_width2_we - attribute \src "ls180.v:2150.12-2150.37" - wire width 8 \builder_csrbank4_width3_r - attribute \src "ls180.v:2149.6-2149.32" - wire \builder_csrbank4_width3_re - attribute \src "ls180.v:2152.12-2152.37" - wire width 8 \builder_csrbank4_width3_w - attribute \src "ls180.v:2151.6-2151.32" - wire \builder_csrbank4_width3_we - attribute \src "ls180.v:2215.12-2215.40" - wire width 8 \builder_csrbank5_dma_base0_r - attribute \src "ls180.v:2214.6-2214.35" - wire \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:2217.12-2217.40" - wire width 8 \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:2216.6-2216.35" - wire \builder_csrbank5_dma_base0_we - attribute \src "ls180.v:2211.12-2211.40" - wire width 8 \builder_csrbank5_dma_base1_r - attribute \src "ls180.v:2210.6-2210.35" - wire \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:2213.12-2213.40" - wire width 8 \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:2212.6-2212.35" - wire \builder_csrbank5_dma_base1_we - attribute \src "ls180.v:2207.12-2207.40" - wire width 8 \builder_csrbank5_dma_base2_r - attribute \src "ls180.v:2206.6-2206.35" - wire \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:2209.12-2209.40" - wire width 8 \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:2208.6-2208.35" - wire \builder_csrbank5_dma_base2_we - attribute \src "ls180.v:2203.12-2203.40" - wire width 8 \builder_csrbank5_dma_base3_r - attribute \src "ls180.v:2202.6-2202.35" - wire \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:2205.12-2205.40" - wire width 8 \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:2204.6-2204.35" - wire \builder_csrbank5_dma_base3_we - attribute \src "ls180.v:2199.12-2199.40" - wire width 8 \builder_csrbank5_dma_base4_r - attribute \src "ls180.v:2198.6-2198.35" - wire \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:2201.12-2201.40" - wire width 8 \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:2200.6-2200.35" - wire \builder_csrbank5_dma_base4_we - attribute \src "ls180.v:2195.12-2195.40" - wire width 8 \builder_csrbank5_dma_base5_r - attribute \src "ls180.v:2194.6-2194.35" - wire \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:2197.12-2197.40" - wire width 8 \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:2196.6-2196.35" - wire \builder_csrbank5_dma_base5_we - attribute \src "ls180.v:2191.12-2191.40" - wire width 8 \builder_csrbank5_dma_base6_r - attribute \src "ls180.v:2190.6-2190.35" - wire \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:2193.12-2193.40" - wire width 8 \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:2192.6-2192.35" - wire \builder_csrbank5_dma_base6_we - attribute \src "ls180.v:2187.12-2187.40" - wire width 8 \builder_csrbank5_dma_base7_r - attribute \src "ls180.v:2186.6-2186.35" - wire \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:2189.12-2189.40" - wire width 8 \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:2188.6-2188.35" - wire \builder_csrbank5_dma_base7_we - attribute \src "ls180.v:2239.6-2239.33" - wire \builder_csrbank5_dma_done_r - attribute \src "ls180.v:2238.6-2238.34" - wire \builder_csrbank5_dma_done_re - attribute \src "ls180.v:2241.6-2241.33" - wire \builder_csrbank5_dma_done_w - attribute \src "ls180.v:2240.6-2240.34" - wire \builder_csrbank5_dma_done_we - attribute \src "ls180.v:2235.6-2235.36" - wire \builder_csrbank5_dma_enable0_r - attribute \src "ls180.v:2234.6-2234.37" - wire \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:2237.6-2237.36" - wire \builder_csrbank5_dma_enable0_w - attribute \src "ls180.v:2236.6-2236.37" - wire \builder_csrbank5_dma_enable0_we - attribute \src "ls180.v:2231.12-2231.42" - wire width 8 \builder_csrbank5_dma_length0_r - attribute \src "ls180.v:2230.6-2230.37" - wire \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:2233.12-2233.42" - wire width 8 \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:2232.6-2232.37" - wire \builder_csrbank5_dma_length0_we - attribute \src "ls180.v:2227.12-2227.42" - wire width 8 \builder_csrbank5_dma_length1_r - attribute \src "ls180.v:2226.6-2226.37" - wire \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:2229.12-2229.42" - wire width 8 \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:2228.6-2228.37" - wire \builder_csrbank5_dma_length1_we - attribute \src "ls180.v:2223.12-2223.42" - wire width 8 \builder_csrbank5_dma_length2_r - attribute \src "ls180.v:2222.6-2222.37" - wire \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:2225.12-2225.42" - wire width 8 \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:2224.6-2224.37" - wire \builder_csrbank5_dma_length2_we - attribute \src "ls180.v:2219.12-2219.42" - wire width 8 \builder_csrbank5_dma_length3_r - attribute \src "ls180.v:2218.6-2218.37" - wire \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:2221.12-2221.42" - wire width 8 \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:2220.6-2220.37" - wire \builder_csrbank5_dma_length3_we - attribute \src "ls180.v:2243.6-2243.34" - wire \builder_csrbank5_dma_loop0_r - attribute \src "ls180.v:2242.6-2242.35" - wire \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:2245.6-2245.34" - wire \builder_csrbank5_dma_loop0_w - attribute \src "ls180.v:2244.6-2244.35" - wire \builder_csrbank5_dma_loop0_we - attribute \src "ls180.v:2246.6-2246.26" - wire \builder_csrbank5_sel - attribute \src "ls180.v:2376.12-2376.43" - wire width 8 \builder_csrbank6_block_count0_r - attribute \src "ls180.v:2375.6-2375.38" - wire \builder_csrbank6_block_count0_re - attribute \src "ls180.v:2378.12-2378.43" - wire width 8 \builder_csrbank6_block_count0_w - attribute \src "ls180.v:2377.6-2377.38" - wire \builder_csrbank6_block_count0_we - attribute \src "ls180.v:2372.12-2372.43" - wire width 8 \builder_csrbank6_block_count1_r - attribute \src "ls180.v:2371.6-2371.38" - wire \builder_csrbank6_block_count1_re - attribute \src "ls180.v:2374.12-2374.43" - wire width 8 \builder_csrbank6_block_count1_w - attribute \src "ls180.v:2373.6-2373.38" - wire \builder_csrbank6_block_count1_we - attribute \src "ls180.v:2368.12-2368.43" - wire width 8 \builder_csrbank6_block_count2_r - attribute \src "ls180.v:2367.6-2367.38" - wire \builder_csrbank6_block_count2_re - attribute \src "ls180.v:2370.12-2370.43" - wire width 8 \builder_csrbank6_block_count2_w - attribute \src "ls180.v:2369.6-2369.38" - wire \builder_csrbank6_block_count2_we - attribute \src "ls180.v:2364.12-2364.43" - wire width 8 \builder_csrbank6_block_count3_r - attribute \src "ls180.v:2363.6-2363.38" - wire \builder_csrbank6_block_count3_re - attribute \src "ls180.v:2366.12-2366.43" - wire width 8 \builder_csrbank6_block_count3_w - attribute \src "ls180.v:2365.6-2365.38" - wire \builder_csrbank6_block_count3_we - attribute \src "ls180.v:2360.12-2360.44" - wire width 8 \builder_csrbank6_block_length0_r - attribute \src "ls180.v:2359.6-2359.39" - wire \builder_csrbank6_block_length0_re - attribute \src "ls180.v:2362.12-2362.44" - wire width 8 \builder_csrbank6_block_length0_w - attribute \src "ls180.v:2361.6-2361.39" - wire \builder_csrbank6_block_length0_we - attribute \src "ls180.v:2356.12-2356.44" - wire width 2 \builder_csrbank6_block_length1_r - attribute \src "ls180.v:2355.6-2355.39" - wire \builder_csrbank6_block_length1_re - attribute \src "ls180.v:2358.12-2358.44" - wire width 2 \builder_csrbank6_block_length1_w - attribute \src "ls180.v:2357.6-2357.39" - wire \builder_csrbank6_block_length1_we - attribute \src "ls180.v:2264.12-2264.44" - wire width 8 \builder_csrbank6_cmd_argument0_r - attribute \src "ls180.v:2263.6-2263.39" - wire \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:2266.12-2266.44" - wire width 8 \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:2265.6-2265.39" - wire \builder_csrbank6_cmd_argument0_we - attribute \src "ls180.v:2260.12-2260.44" - wire width 8 \builder_csrbank6_cmd_argument1_r - attribute \src "ls180.v:2259.6-2259.39" - wire \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:2262.12-2262.44" - wire width 8 \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:2261.6-2261.39" - wire \builder_csrbank6_cmd_argument1_we - attribute \src "ls180.v:2256.12-2256.44" - wire width 8 \builder_csrbank6_cmd_argument2_r - attribute \src "ls180.v:2255.6-2255.39" - wire \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:2258.12-2258.44" - wire width 8 \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:2257.6-2257.39" - wire \builder_csrbank6_cmd_argument2_we - attribute \src "ls180.v:2252.12-2252.44" - wire width 8 \builder_csrbank6_cmd_argument3_r - attribute \src "ls180.v:2251.6-2251.39" - wire \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:2254.12-2254.44" - wire width 8 \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:2253.6-2253.39" - wire \builder_csrbank6_cmd_argument3_we - attribute \src "ls180.v:2280.12-2280.43" - wire width 8 \builder_csrbank6_cmd_command0_r - attribute \src "ls180.v:2279.6-2279.38" - wire \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:2282.12-2282.43" - wire width 8 \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:2281.6-2281.38" - wire \builder_csrbank6_cmd_command0_we - attribute \src "ls180.v:2276.12-2276.43" - wire width 8 \builder_csrbank6_cmd_command1_r - attribute \src "ls180.v:2275.6-2275.38" - wire \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:2278.12-2278.43" - wire width 8 \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:2277.6-2277.38" - wire \builder_csrbank6_cmd_command1_we - attribute \src "ls180.v:2272.12-2272.43" - wire width 8 \builder_csrbank6_cmd_command2_r - attribute \src "ls180.v:2271.6-2271.38" - wire \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:2274.12-2274.43" - wire width 8 \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:2273.6-2273.38" - wire \builder_csrbank6_cmd_command2_we - attribute \src "ls180.v:2268.12-2268.43" - wire width 8 \builder_csrbank6_cmd_command3_r - attribute \src "ls180.v:2267.6-2267.38" - wire \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:2270.12-2270.43" - wire width 8 \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:2269.6-2269.38" - wire \builder_csrbank6_cmd_command3_we - attribute \src "ls180.v:2348.12-2348.40" - wire width 4 \builder_csrbank6_cmd_event_r - attribute \src "ls180.v:2347.6-2347.35" - wire \builder_csrbank6_cmd_event_re - attribute \src "ls180.v:2350.12-2350.40" - wire width 4 \builder_csrbank6_cmd_event_w - attribute \src "ls180.v:2349.6-2349.35" - wire \builder_csrbank6_cmd_event_we - attribute \src "ls180.v:2344.12-2344.44" - wire width 8 \builder_csrbank6_cmd_response0_r - attribute \src "ls180.v:2343.6-2343.39" - wire \builder_csrbank6_cmd_response0_re - attribute \src "ls180.v:2346.12-2346.44" - wire width 8 \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:2345.6-2345.39" - wire \builder_csrbank6_cmd_response0_we - attribute \src "ls180.v:2304.12-2304.45" - wire width 8 \builder_csrbank6_cmd_response10_r - attribute \src "ls180.v:2303.6-2303.40" - wire \builder_csrbank6_cmd_response10_re - attribute \src "ls180.v:2306.12-2306.45" - wire width 8 \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:2305.6-2305.40" - wire \builder_csrbank6_cmd_response10_we - attribute \src "ls180.v:2300.12-2300.45" - wire width 8 \builder_csrbank6_cmd_response11_r - attribute \src "ls180.v:2299.6-2299.40" - wire \builder_csrbank6_cmd_response11_re - attribute \src "ls180.v:2302.12-2302.45" - wire width 8 \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:2301.6-2301.40" - wire \builder_csrbank6_cmd_response11_we - attribute \src "ls180.v:2296.12-2296.45" - wire width 8 \builder_csrbank6_cmd_response12_r - attribute \src "ls180.v:2295.6-2295.40" - wire \builder_csrbank6_cmd_response12_re - attribute \src "ls180.v:2298.12-2298.45" - wire width 8 \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:2297.6-2297.40" - wire \builder_csrbank6_cmd_response12_we - attribute \src "ls180.v:2292.12-2292.45" - wire width 8 \builder_csrbank6_cmd_response13_r - attribute \src "ls180.v:2291.6-2291.40" - wire \builder_csrbank6_cmd_response13_re - attribute \src "ls180.v:2294.12-2294.45" - wire width 8 \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:2293.6-2293.40" - wire \builder_csrbank6_cmd_response13_we - attribute \src "ls180.v:2288.12-2288.45" - wire width 8 \builder_csrbank6_cmd_response14_r - attribute \src "ls180.v:2287.6-2287.40" - wire \builder_csrbank6_cmd_response14_re - attribute \src "ls180.v:2290.12-2290.45" - wire width 8 \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:2289.6-2289.40" - wire \builder_csrbank6_cmd_response14_we - attribute \src "ls180.v:2284.12-2284.45" - wire width 8 \builder_csrbank6_cmd_response15_r - attribute \src "ls180.v:2283.6-2283.40" - wire \builder_csrbank6_cmd_response15_re - attribute \src "ls180.v:2286.12-2286.45" - wire width 8 \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:2285.6-2285.40" - wire \builder_csrbank6_cmd_response15_we - attribute \src "ls180.v:2340.12-2340.44" - wire width 8 \builder_csrbank6_cmd_response1_r - attribute \src "ls180.v:2339.6-2339.39" - wire \builder_csrbank6_cmd_response1_re - attribute \src "ls180.v:2342.12-2342.44" - wire width 8 \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:2341.6-2341.39" - wire \builder_csrbank6_cmd_response1_we - attribute \src "ls180.v:2336.12-2336.44" - wire width 8 \builder_csrbank6_cmd_response2_r - attribute \src "ls180.v:2335.6-2335.39" - wire \builder_csrbank6_cmd_response2_re - attribute \src "ls180.v:2338.12-2338.44" - wire width 8 \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:2337.6-2337.39" - wire \builder_csrbank6_cmd_response2_we - attribute \src "ls180.v:2332.12-2332.44" - wire width 8 \builder_csrbank6_cmd_response3_r - attribute \src "ls180.v:2331.6-2331.39" - wire \builder_csrbank6_cmd_response3_re - attribute \src "ls180.v:2334.12-2334.44" - wire width 8 \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:2333.6-2333.39" - wire \builder_csrbank6_cmd_response3_we - attribute \src "ls180.v:2328.12-2328.44" - wire width 8 \builder_csrbank6_cmd_response4_r - attribute \src "ls180.v:2327.6-2327.39" - wire \builder_csrbank6_cmd_response4_re - attribute \src "ls180.v:2330.12-2330.44" - wire width 8 \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:2329.6-2329.39" - wire \builder_csrbank6_cmd_response4_we - attribute \src "ls180.v:2324.12-2324.44" - wire width 8 \builder_csrbank6_cmd_response5_r - attribute \src "ls180.v:2323.6-2323.39" - wire \builder_csrbank6_cmd_response5_re - attribute \src "ls180.v:2326.12-2326.44" - wire width 8 \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:2325.6-2325.39" - wire \builder_csrbank6_cmd_response5_we - attribute \src "ls180.v:2320.12-2320.44" - wire width 8 \builder_csrbank6_cmd_response6_r - attribute \src "ls180.v:2319.6-2319.39" - wire \builder_csrbank6_cmd_response6_re - attribute \src "ls180.v:2322.12-2322.44" - wire width 8 \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:2321.6-2321.39" - wire \builder_csrbank6_cmd_response6_we - attribute \src "ls180.v:2316.12-2316.44" - wire width 8 \builder_csrbank6_cmd_response7_r - attribute \src "ls180.v:2315.6-2315.39" - wire \builder_csrbank6_cmd_response7_re - attribute \src "ls180.v:2318.12-2318.44" - wire width 8 \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:2317.6-2317.39" - wire \builder_csrbank6_cmd_response7_we - attribute \src "ls180.v:2312.12-2312.44" - wire width 8 \builder_csrbank6_cmd_response8_r - attribute \src "ls180.v:2311.6-2311.39" - wire \builder_csrbank6_cmd_response8_re - attribute \src "ls180.v:2314.12-2314.44" - wire width 8 \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:2313.6-2313.39" - wire \builder_csrbank6_cmd_response8_we - attribute \src "ls180.v:2308.12-2308.44" - wire width 8 \builder_csrbank6_cmd_response9_r - attribute \src "ls180.v:2307.6-2307.39" - wire \builder_csrbank6_cmd_response9_re - attribute \src "ls180.v:2310.12-2310.44" - wire width 8 \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:2309.6-2309.39" - wire \builder_csrbank6_cmd_response9_we - attribute \src "ls180.v:2352.12-2352.41" - wire width 4 \builder_csrbank6_data_event_r - attribute \src "ls180.v:2351.6-2351.36" - wire \builder_csrbank6_data_event_re - attribute \src "ls180.v:2354.12-2354.41" - wire width 4 \builder_csrbank6_data_event_w - attribute \src "ls180.v:2353.6-2353.36" - wire \builder_csrbank6_data_event_we - attribute \src "ls180.v:2379.6-2379.26" - wire \builder_csrbank6_sel - attribute \src "ls180.v:2413.12-2413.40" - wire width 8 \builder_csrbank7_dma_base0_r - attribute \src "ls180.v:2412.6-2412.35" - wire \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:2415.12-2415.40" - wire width 8 \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:2414.6-2414.35" - wire \builder_csrbank7_dma_base0_we - attribute \src "ls180.v:2409.12-2409.40" - wire width 8 \builder_csrbank7_dma_base1_r - attribute \src "ls180.v:2408.6-2408.35" - wire \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:2411.12-2411.40" - wire width 8 \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:2410.6-2410.35" - wire \builder_csrbank7_dma_base1_we - attribute \src "ls180.v:2405.12-2405.40" - wire width 8 \builder_csrbank7_dma_base2_r - attribute \src "ls180.v:2404.6-2404.35" - wire \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:2407.12-2407.40" - wire width 8 \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:2406.6-2406.35" - wire \builder_csrbank7_dma_base2_we - attribute \src "ls180.v:2401.12-2401.40" - wire width 8 \builder_csrbank7_dma_base3_r - attribute \src "ls180.v:2400.6-2400.35" - wire \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:2403.12-2403.40" - wire width 8 \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:2402.6-2402.35" - wire \builder_csrbank7_dma_base3_we - attribute \src "ls180.v:2397.12-2397.40" - wire width 8 \builder_csrbank7_dma_base4_r - attribute \src "ls180.v:2396.6-2396.35" - wire \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:2399.12-2399.40" - wire width 8 \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:2398.6-2398.35" - wire \builder_csrbank7_dma_base4_we - attribute \src "ls180.v:2393.12-2393.40" - wire width 8 \builder_csrbank7_dma_base5_r - attribute \src "ls180.v:2392.6-2392.35" - wire \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:2395.12-2395.40" - wire width 8 \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:2394.6-2394.35" - wire \builder_csrbank7_dma_base5_we - attribute \src "ls180.v:2389.12-2389.40" - wire width 8 \builder_csrbank7_dma_base6_r - attribute \src "ls180.v:2388.6-2388.35" - wire \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:2391.12-2391.40" - wire width 8 \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:2390.6-2390.35" - wire \builder_csrbank7_dma_base6_we - attribute \src "ls180.v:2385.12-2385.40" - wire width 8 \builder_csrbank7_dma_base7_r - attribute \src "ls180.v:2384.6-2384.35" - wire \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:2387.12-2387.40" - wire width 8 \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:2386.6-2386.35" - wire \builder_csrbank7_dma_base7_we - attribute \src "ls180.v:2437.6-2437.33" - wire \builder_csrbank7_dma_done_r - attribute \src "ls180.v:2436.6-2436.34" - wire \builder_csrbank7_dma_done_re - attribute \src "ls180.v:2439.6-2439.33" - wire \builder_csrbank7_dma_done_w - attribute \src "ls180.v:2438.6-2438.34" - wire \builder_csrbank7_dma_done_we - attribute \src "ls180.v:2433.6-2433.36" - wire \builder_csrbank7_dma_enable0_r - attribute \src "ls180.v:2432.6-2432.37" - wire \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:2435.6-2435.36" - wire \builder_csrbank7_dma_enable0_w - attribute \src "ls180.v:2434.6-2434.37" - wire \builder_csrbank7_dma_enable0_we - attribute \src "ls180.v:2429.12-2429.42" - wire width 8 \builder_csrbank7_dma_length0_r - attribute \src "ls180.v:2428.6-2428.37" - wire \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:2431.12-2431.42" - wire width 8 \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:2430.6-2430.37" - wire \builder_csrbank7_dma_length0_we - attribute \src "ls180.v:2425.12-2425.42" - wire width 8 \builder_csrbank7_dma_length1_r - attribute \src "ls180.v:2424.6-2424.37" - wire \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:2427.12-2427.42" - wire width 8 \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:2426.6-2426.37" - wire \builder_csrbank7_dma_length1_we - attribute \src "ls180.v:2421.12-2421.42" - wire width 8 \builder_csrbank7_dma_length2_r - attribute \src "ls180.v:2420.6-2420.37" - wire \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:2423.12-2423.42" - wire width 8 \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:2422.6-2422.37" - wire \builder_csrbank7_dma_length2_we - attribute \src "ls180.v:2417.12-2417.42" - wire width 8 \builder_csrbank7_dma_length3_r - attribute \src "ls180.v:2416.6-2416.37" - wire \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:2419.12-2419.42" - wire width 8 \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:2418.6-2418.37" - wire \builder_csrbank7_dma_length3_we - attribute \src "ls180.v:2441.6-2441.34" - wire \builder_csrbank7_dma_loop0_r - attribute \src "ls180.v:2440.6-2440.35" - wire \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:2443.6-2443.34" - wire \builder_csrbank7_dma_loop0_w - attribute \src "ls180.v:2442.6-2442.35" - wire \builder_csrbank7_dma_loop0_we - attribute \src "ls180.v:2457.12-2457.42" - wire width 8 \builder_csrbank7_dma_offset0_r - attribute \src "ls180.v:2456.6-2456.37" - wire \builder_csrbank7_dma_offset0_re - attribute \src "ls180.v:2459.12-2459.42" - wire width 8 \builder_csrbank7_dma_offset0_w - attribute \src "ls180.v:2458.6-2458.37" - wire \builder_csrbank7_dma_offset0_we - attribute \src "ls180.v:2453.12-2453.42" - wire width 8 \builder_csrbank7_dma_offset1_r - attribute \src "ls180.v:2452.6-2452.37" - wire \builder_csrbank7_dma_offset1_re - attribute \src "ls180.v:2455.12-2455.42" - wire width 8 \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:2454.6-2454.37" - wire \builder_csrbank7_dma_offset1_we - attribute \src "ls180.v:2449.12-2449.42" - wire width 8 \builder_csrbank7_dma_offset2_r - attribute \src "ls180.v:2448.6-2448.37" - wire \builder_csrbank7_dma_offset2_re - attribute \src "ls180.v:2451.12-2451.42" - wire width 8 \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:2450.6-2450.37" - wire \builder_csrbank7_dma_offset2_we - attribute \src "ls180.v:2445.12-2445.42" - wire width 8 \builder_csrbank7_dma_offset3_r - attribute \src "ls180.v:2444.6-2444.37" - wire \builder_csrbank7_dma_offset3_re - attribute \src "ls180.v:2447.12-2447.42" - wire width 8 \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:2446.6-2446.37" - wire \builder_csrbank7_dma_offset3_we - attribute \src "ls180.v:2460.6-2460.26" - wire \builder_csrbank7_sel - attribute \src "ls180.v:2466.6-2466.36" - wire \builder_csrbank8_card_detect_r - attribute \src "ls180.v:2465.6-2465.37" - wire \builder_csrbank8_card_detect_re - attribute \src "ls180.v:2468.6-2468.36" - wire \builder_csrbank8_card_detect_w - attribute \src "ls180.v:2467.6-2467.37" - wire \builder_csrbank8_card_detect_we - attribute \src "ls180.v:2474.12-2474.47" - wire width 8 \builder_csrbank8_clocker_divider0_r - attribute \src "ls180.v:2473.6-2473.42" - wire \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:2476.12-2476.47" - wire width 8 \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:2475.6-2475.42" - wire \builder_csrbank8_clocker_divider0_we - attribute \src "ls180.v:2470.6-2470.41" - wire \builder_csrbank8_clocker_divider1_r - attribute \src "ls180.v:2469.6-2469.42" - wire \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:2472.6-2472.41" - wire \builder_csrbank8_clocker_divider1_w - attribute \src "ls180.v:2471.6-2471.42" - wire \builder_csrbank8_clocker_divider1_we - attribute \src "ls180.v:2477.6-2477.26" - wire \builder_csrbank8_sel - attribute \src "ls180.v:2483.12-2483.44" - wire width 4 \builder_csrbank9_dfii_control0_r - attribute \src "ls180.v:2482.6-2482.39" - wire \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:2485.12-2485.44" - wire width 4 \builder_csrbank9_dfii_control0_w - attribute \src "ls180.v:2484.6-2484.39" - wire \builder_csrbank9_dfii_control0_we - attribute \src "ls180.v:2495.12-2495.48" - wire width 8 \builder_csrbank9_dfii_pi0_address0_r - attribute \src "ls180.v:2494.6-2494.43" - wire \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:2497.12-2497.48" - wire width 8 \builder_csrbank9_dfii_pi0_address0_w - attribute \src "ls180.v:2496.6-2496.43" - wire \builder_csrbank9_dfii_pi0_address0_we - attribute \src "ls180.v:2491.12-2491.48" - wire width 5 \builder_csrbank9_dfii_pi0_address1_r - attribute \src "ls180.v:2490.6-2490.43" - wire \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:2493.12-2493.48" - wire width 5 \builder_csrbank9_dfii_pi0_address1_w - attribute \src "ls180.v:2492.6-2492.43" - wire \builder_csrbank9_dfii_pi0_address1_we - attribute \src "ls180.v:2499.12-2499.49" - wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r - attribute \src "ls180.v:2498.6-2498.44" - wire \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:2501.12-2501.49" - wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w - attribute \src "ls180.v:2500.6-2500.44" - wire \builder_csrbank9_dfii_pi0_baddress0_we - attribute \src "ls180.v:2487.12-2487.48" - wire width 6 \builder_csrbank9_dfii_pi0_command0_r - attribute \src "ls180.v:2486.6-2486.43" - wire \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:2489.12-2489.48" - wire width 6 \builder_csrbank9_dfii_pi0_command0_w - attribute \src "ls180.v:2488.6-2488.43" - wire \builder_csrbank9_dfii_pi0_command0_we - attribute \src "ls180.v:2515.12-2515.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r - attribute \src "ls180.v:2514.6-2514.42" - wire \builder_csrbank9_dfii_pi0_rddata0_re - attribute \src "ls180.v:2517.12-2517.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w - attribute \src "ls180.v:2516.6-2516.42" - wire \builder_csrbank9_dfii_pi0_rddata0_we - attribute \src "ls180.v:2511.12-2511.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r - attribute \src "ls180.v:2510.6-2510.42" - wire \builder_csrbank9_dfii_pi0_rddata1_re - attribute \src "ls180.v:2513.12-2513.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w - attribute \src "ls180.v:2512.6-2512.42" - wire \builder_csrbank9_dfii_pi0_rddata1_we - attribute \src "ls180.v:2507.12-2507.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r - attribute \src "ls180.v:2506.6-2506.42" - wire \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:2509.12-2509.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w - attribute \src "ls180.v:2508.6-2508.42" - wire \builder_csrbank9_dfii_pi0_wrdata0_we - attribute \src "ls180.v:2503.12-2503.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r - attribute \src "ls180.v:2502.6-2502.42" - wire \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:2505.12-2505.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w - attribute \src "ls180.v:2504.6-2504.42" - wire \builder_csrbank9_dfii_pi0_wrdata1_we - attribute \src "ls180.v:2518.6-2518.26" - wire \builder_csrbank9_sel - attribute \src "ls180.v:2015.6-2015.18" - wire \builder_done - attribute \src "ls180.v:2013.5-2013.18" - wire \builder_error - attribute \src "ls180.v:2010.11-2010.24" - wire width 3 \builder_grant - attribute \src "ls180.v:2017.13-2017.44" - wire width 14 \builder_interface0_bank_bus_adr - attribute \src "ls180.v:2020.11-2020.44" - wire width 8 \builder_interface0_bank_bus_dat_r - attribute \src "ls180.v:2019.12-2019.45" - wire width 8 \builder_interface0_bank_bus_dat_w - attribute \src "ls180.v:2018.6-2018.36" - wire \builder_interface0_bank_bus_we - attribute \src "ls180.v:2519.13-2519.45" - wire width 14 \builder_interface10_bank_bus_adr - attribute \src "ls180.v:2522.11-2522.45" - wire width 8 \builder_interface10_bank_bus_dat_r - attribute \src "ls180.v:2521.12-2521.46" - wire width 8 \builder_interface10_bank_bus_dat_w - attribute \src "ls180.v:2520.6-2520.37" - wire \builder_interface10_bank_bus_we - attribute \src "ls180.v:2552.13-2552.45" - wire width 14 \builder_interface11_bank_bus_adr - attribute \src "ls180.v:2555.11-2555.45" - wire width 8 \builder_interface11_bank_bus_dat_r - attribute \src "ls180.v:2554.12-2554.46" - wire width 8 \builder_interface11_bank_bus_dat_w - attribute \src "ls180.v:2553.6-2553.37" - wire \builder_interface11_bank_bus_we - attribute \src "ls180.v:2593.13-2593.45" - wire width 14 \builder_interface12_bank_bus_adr - attribute \src "ls180.v:2596.11-2596.45" - wire width 8 \builder_interface12_bank_bus_dat_r - attribute \src "ls180.v:2595.12-2595.46" - wire width 8 \builder_interface12_bank_bus_dat_w - attribute \src "ls180.v:2594.6-2594.37" - wire \builder_interface12_bank_bus_we - attribute \src "ls180.v:2658.13-2658.45" - wire width 14 \builder_interface13_bank_bus_adr - attribute \src "ls180.v:2661.11-2661.45" - wire width 8 \builder_interface13_bank_bus_dat_r - attribute \src "ls180.v:2660.12-2660.46" - wire width 8 \builder_interface13_bank_bus_dat_w - attribute \src "ls180.v:2659.6-2659.37" - wire \builder_interface13_bank_bus_we - attribute \src "ls180.v:2683.13-2683.45" - wire width 14 \builder_interface14_bank_bus_adr - attribute \src "ls180.v:2686.11-2686.45" - wire width 8 \builder_interface14_bank_bus_dat_r - attribute \src "ls180.v:2685.12-2685.46" - wire width 8 \builder_interface14_bank_bus_dat_w - attribute \src "ls180.v:2684.6-2684.37" - wire \builder_interface14_bank_bus_we - attribute \src "ls180.v:2058.13-2058.44" - wire width 14 \builder_interface1_bank_bus_adr - attribute \src "ls180.v:2061.11-2061.44" - wire width 8 \builder_interface1_bank_bus_dat_r - attribute \src "ls180.v:2060.12-2060.45" - wire width 8 \builder_interface1_bank_bus_dat_w - attribute \src "ls180.v:2059.6-2059.36" - wire \builder_interface1_bank_bus_we - attribute \src "ls180.v:2087.13-2087.44" - wire width 14 \builder_interface2_bank_bus_adr - attribute \src "ls180.v:2090.11-2090.44" - wire width 8 \builder_interface2_bank_bus_dat_r - attribute \src "ls180.v:2089.12-2089.45" - wire width 8 \builder_interface2_bank_bus_dat_w - attribute \src "ls180.v:2088.6-2088.36" - wire \builder_interface2_bank_bus_we - attribute \src "ls180.v:2100.13-2100.44" - wire width 14 \builder_interface3_bank_bus_adr - attribute \src "ls180.v:2103.11-2103.44" - wire width 8 \builder_interface3_bank_bus_dat_r - attribute \src "ls180.v:2102.12-2102.45" - wire width 8 \builder_interface3_bank_bus_dat_w - attribute \src "ls180.v:2101.6-2101.36" - wire \builder_interface3_bank_bus_we - attribute \src "ls180.v:2141.13-2141.44" - wire width 14 \builder_interface4_bank_bus_adr - attribute \src "ls180.v:2144.11-2144.44" - wire width 8 \builder_interface4_bank_bus_dat_r - attribute \src "ls180.v:2143.12-2143.45" - wire width 8 \builder_interface4_bank_bus_dat_w - attribute \src "ls180.v:2142.6-2142.36" - wire \builder_interface4_bank_bus_we - attribute \src "ls180.v:2182.13-2182.44" - wire width 14 \builder_interface5_bank_bus_adr - attribute \src "ls180.v:2185.11-2185.44" - wire width 8 \builder_interface5_bank_bus_dat_r - attribute \src "ls180.v:2184.12-2184.45" - wire width 8 \builder_interface5_bank_bus_dat_w - attribute \src "ls180.v:2183.6-2183.36" - wire \builder_interface5_bank_bus_we - attribute \src "ls180.v:2247.13-2247.44" - wire width 14 \builder_interface6_bank_bus_adr - attribute \src "ls180.v:2250.11-2250.44" - wire width 8 \builder_interface6_bank_bus_dat_r - attribute \src "ls180.v:2249.12-2249.45" - wire width 8 \builder_interface6_bank_bus_dat_w - attribute \src "ls180.v:2248.6-2248.36" - wire \builder_interface6_bank_bus_we - attribute \src "ls180.v:2380.13-2380.44" - wire width 14 \builder_interface7_bank_bus_adr - attribute \src "ls180.v:2383.11-2383.44" - wire width 8 \builder_interface7_bank_bus_dat_r - attribute \src "ls180.v:2382.12-2382.45" - wire width 8 \builder_interface7_bank_bus_dat_w - attribute \src "ls180.v:2381.6-2381.36" - wire \builder_interface7_bank_bus_we - attribute \src "ls180.v:2461.13-2461.44" - wire width 14 \builder_interface8_bank_bus_adr - attribute \src "ls180.v:2464.11-2464.44" - wire width 8 \builder_interface8_bank_bus_dat_r - attribute \src "ls180.v:2463.12-2463.45" - wire width 8 \builder_interface8_bank_bus_dat_w - attribute \src "ls180.v:2462.6-2462.36" - wire \builder_interface8_bank_bus_we - attribute \src "ls180.v:2478.13-2478.44" - wire width 14 \builder_interface9_bank_bus_adr - attribute \src "ls180.v:2481.11-2481.44" - wire width 8 \builder_interface9_bank_bus_dat_r - attribute \src "ls180.v:2480.12-2480.45" - wire width 8 \builder_interface9_bank_bus_dat_w - attribute \src "ls180.v:2479.6-2479.36" - wire \builder_interface9_bank_bus_we - attribute \src "ls180.v:1975.12-1975.35" - wire width 14 \builder_libresocsim_adr - attribute \src "ls180.v:2712.12-2712.47" - wire width 14 \builder_libresocsim_adr_next_value1 - attribute \src "ls180.v:2713.5-2713.43" - wire \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:1993.5-1993.48" - wire \builder_libresocsim_converted_interface_ack - attribute \src "ls180.v:1987.13-1987.56" - wire width 30 \builder_libresocsim_converted_interface_adr - attribute \src "ls180.v:1996.12-1996.55" - wire width 2 \builder_libresocsim_converted_interface_bte - attribute \src "ls180.v:1995.12-1995.55" - wire width 3 \builder_libresocsim_converted_interface_cti - attribute \src "ls180.v:1991.6-1991.49" - wire \builder_libresocsim_converted_interface_cyc - attribute \src "ls180.v:1989.12-1989.57" - wire width 64 \builder_libresocsim_converted_interface_dat_r - attribute \src "ls180.v:1988.13-1988.58" - wire width 64 \builder_libresocsim_converted_interface_dat_w - attribute \src "ls180.v:1997.5-1997.48" - wire \builder_libresocsim_converted_interface_err - attribute \src "ls180.v:1990.12-1990.55" - wire width 8 \builder_libresocsim_converted_interface_sel - attribute \src "ls180.v:1992.6-1992.49" - wire \builder_libresocsim_converted_interface_stb - attribute \src "ls180.v:1994.6-1994.48" - wire \builder_libresocsim_converted_interface_we - attribute \src "ls180.v:1978.12-1978.37" - wire width 8 \builder_libresocsim_dat_r - attribute \src "ls180.v:1977.11-1977.36" - wire width 8 \builder_libresocsim_dat_w - attribute \src "ls180.v:2710.11-2710.48" - wire width 8 \builder_libresocsim_dat_w_next_value0 - attribute \src "ls180.v:2711.5-2711.45" - wire \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:1976.5-1976.27" - wire \builder_libresocsim_we - attribute \src "ls180.v:2714.5-2714.39" - wire \builder_libresocsim_we_next_value2 - attribute \src "ls180.v:2715.5-2715.42" - wire \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:1985.5-1985.37" - wire \builder_libresocsim_wishbone_ack - attribute \src "ls180.v:1979.12-1979.44" - wire width 30 \builder_libresocsim_wishbone_adr - attribute \src "ls180.v:1983.5-1983.37" - wire \builder_libresocsim_wishbone_cyc - attribute \src "ls180.v:1981.12-1981.46" - wire width 32 \builder_libresocsim_wishbone_dat_r - attribute \src "ls180.v:1980.12-1980.46" - wire width 32 \builder_libresocsim_wishbone_dat_w - attribute \src "ls180.v:1982.11-1982.43" - wire width 4 \builder_libresocsim_wishbone_sel - attribute \src "ls180.v:1984.5-1984.37" - wire \builder_libresocsim_wishbone_stb - attribute \src "ls180.v:1986.5-1986.36" - wire \builder_libresocsim_wishbone_we - attribute \src "ls180.v:1878.5-1878.20" - wire \builder_locked0 - attribute \src "ls180.v:1879.5-1879.20" - wire \builder_locked1 - attribute \src "ls180.v:1880.5-1880.20" - wire \builder_locked2 - attribute \src "ls180.v:1881.5-1881.20" - wire \builder_locked3 - attribute \src "ls180.v:1865.11-1865.41" - wire width 3 \builder_multiplexer_next_state - attribute \src "ls180.v:1864.11-1864.36" - wire width 3 \builder_multiplexer_state - attribute \no_retiming "true" - attribute \src "ls180.v:2819.32-2819.59" - wire \builder_multiregimpl0_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2820.32-2820.59" - wire \builder_multiregimpl0_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2839.32-2839.60" - wire \builder_multiregimpl10_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2840.32-2840.60" - wire \builder_multiregimpl10_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2841.32-2841.60" - wire \builder_multiregimpl11_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2842.32-2842.60" - wire \builder_multiregimpl11_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2843.32-2843.60" - wire \builder_multiregimpl12_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2844.32-2844.60" - wire \builder_multiregimpl12_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2845.32-2845.60" - wire \builder_multiregimpl13_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2846.32-2846.60" - wire \builder_multiregimpl13_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2847.32-2847.60" - wire \builder_multiregimpl14_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2848.32-2848.60" - wire \builder_multiregimpl14_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2849.32-2849.60" - wire \builder_multiregimpl15_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2850.32-2850.60" - wire \builder_multiregimpl15_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2851.32-2851.60" - wire \builder_multiregimpl16_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2852.32-2852.60" - wire \builder_multiregimpl16_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2821.32-2821.59" - wire \builder_multiregimpl1_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2822.32-2822.59" - wire \builder_multiregimpl1_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2823.32-2823.59" - wire \builder_multiregimpl2_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2824.32-2824.59" - wire \builder_multiregimpl2_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2825.32-2825.59" - wire \builder_multiregimpl3_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2826.32-2826.59" - wire \builder_multiregimpl3_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2827.32-2827.59" - wire \builder_multiregimpl4_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2828.32-2828.59" - wire \builder_multiregimpl4_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2829.32-2829.59" - wire \builder_multiregimpl5_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2830.32-2830.59" - wire \builder_multiregimpl5_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2831.32-2831.59" - wire \builder_multiregimpl6_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2832.32-2832.59" - wire \builder_multiregimpl6_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2833.32-2833.59" - wire \builder_multiregimpl7_regs0 + wire width 10 $memwr$\storage_5$ls180.v:5611$14_EN + attribute \src "ls180.v:1711.36-1711.61" + wire $ne$ls180.v:1711$63_Y + attribute \src "ls180.v:1882.60-1882.89" + wire $ne$ls180.v:1882$90_Y + attribute \src "ls180.v:1943.8-1943.132" + wire $ne$ls180.v:1943$109_Y + attribute \src "ls180.v:1975.70-1975.123" + wire $ne$ls180.v:1975$116_Y + attribute \src "ls180.v:1976.70-1976.123" + wire $ne$ls180.v:1976$117_Y + attribute \src "ls180.v:2100.8-2100.132" + wire $ne$ls180.v:2100$139_Y + attribute \src "ls180.v:2132.70-2132.123" + wire $ne$ls180.v:2132$146_Y + attribute \src "ls180.v:2133.70-2133.123" + wire $ne$ls180.v:2133$147_Y + attribute \src "ls180.v:2257.8-2257.132" + wire $ne$ls180.v:2257$169_Y + attribute \src "ls180.v:2289.70-2289.123" + wire $ne$ls180.v:2289$176_Y + attribute \src "ls180.v:2290.70-2290.123" + wire $ne$ls180.v:2290$177_Y + attribute \src "ls180.v:2414.8-2414.132" + wire $ne$ls180.v:2414$199_Y + attribute \src "ls180.v:2446.70-2446.123" + wire $ne$ls180.v:2446$206_Y + attribute \src "ls180.v:2447.70-2447.123" + wire $ne$ls180.v:2447$207_Y + attribute \src "ls180.v:2939.37-2939.60" + wire $ne$ls180.v:2939$605_Y + attribute \src "ls180.v:2940.37-2940.59" + wire $ne$ls180.v:2940$606_Y + attribute \src "ls180.v:2969.37-2969.60" + wire $ne$ls180.v:2969$616_Y + attribute \src "ls180.v:2970.37-2970.59" + wire $ne$ls180.v:2970$617_Y + attribute \src "ls180.v:3065.99-3065.143" + wire $ne$ls180.v:3065$624_Y + attribute \src "ls180.v:4355.7-4355.47" + wire $ne$ls180.v:4355$1255_Y + attribute \src "ls180.v:4409.9-4409.38" + wire $ne$ls180.v:4409$1272_Y + attribute \src "ls180.v:4445.8-4445.39" + wire $ne$ls180.v:4445$1279_Y + attribute \src "ls180.v:1519.40-1519.70" + wire $not$ls180.v:1519$17_Y + attribute \src "ls180.v:1558.56-1558.84" + wire $not$ls180.v:1558$22_Y + attribute \src "ls180.v:1559.56-1559.84" + wire $not$ls180.v:1559$23_Y + attribute \src "ls180.v:1579.40-1579.70" + wire $not$ls180.v:1579$28_Y + attribute \src "ls180.v:1618.56-1618.84" + wire $not$ls180.v:1618$33_Y + attribute \src "ls180.v:1619.56-1619.84" + wire $not$ls180.v:1619$34_Y + attribute \src "ls180.v:1639.40-1639.73" + wire $not$ls180.v:1639$39_Y + attribute \src "ls180.v:1678.56-1678.84" + wire $not$ls180.v:1678$44_Y + attribute \src "ls180.v:1679.56-1679.84" + wire $not$ls180.v:1679$45_Y + attribute \src "ls180.v:1831.29-1831.54" + wire $not$ls180.v:1831$82_Y + attribute \src "ls180.v:1832.26-1832.51" + wire $not$ls180.v:1832$83_Y + attribute \src "ls180.v:1833.27-1833.52" + wire $not$ls180.v:1833$84_Y + attribute \src "ls180.v:1834.27-1834.52" + wire $not$ls180.v:1834$85_Y + attribute \src "ls180.v:1876.28-1876.46" + wire $not$ls180.v:1876$88_Y + attribute \src "ls180.v:1977.53-1977.96" + wire $not$ls180.v:1977$118_Y + attribute \src "ls180.v:2031.9-2031.40" + wire $not$ls180.v:2031$123_Y + attribute \src "ls180.v:2134.53-2134.96" + wire $not$ls180.v:2134$148_Y + attribute \src "ls180.v:2188.9-2188.40" + wire $not$ls180.v:2188$153_Y + attribute \src "ls180.v:2291.53-2291.96" + wire $not$ls180.v:2291$178_Y + attribute \src "ls180.v:2345.9-2345.40" + wire $not$ls180.v:2345$183_Y + attribute \src "ls180.v:2448.53-2448.96" + wire $not$ls180.v:2448$208_Y + attribute \src "ls180.v:2502.9-2502.40" + wire $not$ls180.v:2502$213_Y + attribute \src "ls180.v:2544.129-2544.162" + wire $not$ls180.v:2544$216_Y + attribute \src "ls180.v:2544.168-2544.200" + wire $not$ls180.v:2544$218_Y + attribute \src "ls180.v:2545.129-2545.162" + wire $not$ls180.v:2545$222_Y + attribute \src "ls180.v:2545.168-2545.200" + wire $not$ls180.v:2545$224_Y + attribute \src "ls180.v:2561.38-2561.63" + wire width 2 $not$ls180.v:2561$252_Y + attribute \src "ls180.v:2564.180-2564.215" + wire $not$ls180.v:2564$255_Y + attribute \src "ls180.v:2564.221-2564.255" + wire $not$ls180.v:2564$257_Y + attribute \src "ls180.v:2564.139-2564.257" + wire $not$ls180.v:2564$259_Y + attribute \src "ls180.v:2565.180-2565.215" + wire $not$ls180.v:2565$268_Y + attribute \src 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$sub$ls180.v:4923$1417_Y + attribute \src "ls180.v:4945.23-4945.44" + wire width 5 $sub$ls180.v:4945$1428_Y + attribute \src "ls180.v:5010.26-5010.50" + wire width 20 $sub$ls180.v:5010$1433_Y + attribute \src "ls180.v:834.6-834.13" + wire \ack_cmd + attribute \src "ls180.v:836.6-836.15" + wire \ack_rdata + attribute \src "ls180.v:835.6-835.15" + wire \ack_wdata + attribute \src "ls180.v:1381.11-1381.23" + wire width 2 \array_muxed0 + attribute \src "ls180.v:1382.12-1382.24" + wire width 13 \array_muxed1 + attribute \src "ls180.v:1383.5-1383.17" + wire \array_muxed2 + attribute \src "ls180.v:1384.5-1384.17" + wire \array_muxed3 + attribute \src "ls180.v:1385.5-1385.17" + wire \array_muxed4 + attribute \src "ls180.v:1386.5-1386.17" + wire \array_muxed5 + attribute \src "ls180.v:1387.5-1387.17" + wire \array_muxed6 + attribute \src "ls180.v:832.5-832.17" + wire \cmd_consumed + attribute \src "ls180.v:829.5-829.22" + wire \converter_counter + attribute \src "ls180.v:1055.5-1055.46" + wire \converter_counter_subfragments_next_value + attribute \src "ls180.v:1056.5-1056.49" + wire \converter_counter_subfragments_next_value_ce + attribute \src "ls180.v:831.12-831.27" + wire width 32 \converter_dat_r + attribute \src "ls180.v:830.6-830.21" + wire \converter_reset + attribute \src "ls180.v:828.5-828.19" + wire \converter_skip + attribute \src "ls180.v:258.6-258.18" + wire \dfi_p0_act_n + attribute \src "ls180.v:249.13-249.27" + wire width 13 \dfi_p0_address + attribute \src "ls180.v:250.12-250.23" + wire width 2 \dfi_p0_bank + attribute \src "ls180.v:251.6-251.18" + wire \dfi_p0_cas_n + attribute \src "ls180.v:255.6-255.16" + wire \dfi_p0_cke + attribute \src "ls180.v:252.6-252.17" + wire \dfi_p0_cs_n + attribute \src "ls180.v:256.6-256.16" + wire \dfi_p0_odt + attribute \src "ls180.v:253.6-253.18" + wire \dfi_p0_ras_n + attribute \src "ls180.v:263.12-263.25" + wire width 16 \dfi_p0_rddata + attribute \src "ls180.v:262.6-262.22" + wire \dfi_p0_rddata_en + attribute \src "ls180.v:264.5-264.24" + wire \dfi_p0_rddata_valid + attribute \src "ls180.v:257.6-257.20" + wire \dfi_p0_reset_n + attribute \src "ls180.v:254.6-254.17" + wire \dfi_p0_we_n + attribute \src "ls180.v:259.13-259.26" + wire width 16 \dfi_p0_wrdata + attribute \src "ls180.v:260.6-260.22" + wire \dfi_p0_wrdata_en + attribute \src "ls180.v:261.12-261.30" + wire width 2 \dfi_p0_wrdata_mask + attribute \src "ls180.v:999.12-999.17" + wire width 36 \dummy + attribute \src "ls180.v:30.13-30.19" + wire input 26 \eint_0 + attribute \src "ls180.v:31.13-31.19" + wire input 27 \eint_1 + attribute \src "ls180.v:32.13-32.19" + wire input 28 \eint_2 + attribute \src "ls180.v:997.11-997.19" + wire width 3 \eint_tmp + attribute \src "ls180.v:885.12-885.34" + wire width 2 \eventmanager_pending_r + attribute \src "ls180.v:884.6-884.29" + wire \eventmanager_pending_re + attribute \src "ls180.v:887.11-887.33" + wire width 2 \eventmanager_pending_w + attribute \src "ls180.v:886.6-886.29" + wire \eventmanager_pending_we + attribute \src "ls180.v:889.5-889.20" + wire \eventmanager_re + attribute \src "ls180.v:881.12-881.33" + wire width 2 \eventmanager_status_r + attribute \src "ls180.v:880.6-880.28" + wire \eventmanager_status_re + attribute \src "ls180.v:883.11-883.32" + wire width 2 \eventmanager_status_w + attribute \src "ls180.v:882.6-882.28" + wire \eventmanager_status_we + attribute \src "ls180.v:888.11-888.31" + wire width 2 \eventmanager_storage + attribute \src "ls180.v:980.5-980.16" + wire \gpio0_oe_re + attribute \src "ls180.v:979.11-979.27" + wire width 8 \gpio0_oe_storage + attribute \src "ls180.v:984.5-984.17" + wire \gpio0_out_re + attribute \src "ls180.v:983.11-983.28" + wire width 8 \gpio0_out_storage + attribute \src "ls180.v:985.11-985.28" + wire width 8 \gpio0_pads_gpio0i + attribute \src "ls180.v:986.11-986.28" + wire width 8 \gpio0_pads_gpio0o + attribute \src "ls180.v:987.11-987.29" + wire width 8 \gpio0_pads_gpio0oe + attribute \src "ls180.v:981.11-981.23" + wire width 8 \gpio0_status + attribute \src "ls180.v:982.6-982.14" + wire \gpio0_we + attribute \src "ls180.v:989.5-989.16" + wire \gpio1_oe_re + attribute \src "ls180.v:988.11-988.27" + wire width 8 \gpio1_oe_storage + attribute \src "ls180.v:993.5-993.17" + wire \gpio1_out_re + attribute \src "ls180.v:992.11-992.28" + wire width 8 \gpio1_out_storage + attribute \src "ls180.v:994.11-994.28" + wire width 8 \gpio1_pads_gpio1i + attribute \src "ls180.v:995.11-995.28" + wire width 8 \gpio1_pads_gpio1o + attribute \src "ls180.v:996.11-996.29" + wire width 8 \gpio1_pads_gpio1oe + attribute \src "ls180.v:990.11-990.23" + wire width 8 \gpio1_status + attribute \src "ls180.v:991.6-991.14" + wire \gpio1_we + attribute \src "ls180.v:11.20-11.26" + wire width 16 input 7 \gpio_i + attribute \src "ls180.v:12.21-12.27" + wire width 16 output 8 \gpio_o + attribute \src "ls180.v:13.21-13.28" + wire width 16 output 9 \gpio_oe + attribute \src "ls180.v:1001.6-1001.12" + wire \i2c_oe + attribute \src "ls180.v:1004.5-1004.11" + wire \i2c_re + attribute \src "ls180.v:7.14-7.21" + wire output 3 \i2c_scl + attribute \src "ls180.v:1000.6-1000.15" + wire \i2c_scl_1 + attribute \src "ls180.v:1002.6-1002.14" + wire \i2c_sda0 + attribute \src "ls180.v:1005.6-1005.14" + wire \i2c_sda1 + attribute \src "ls180.v:8.13-8.22" + wire input 4 \i2c_sda_i + attribute \src "ls180.v:9.14-9.23" + wire output 5 \i2c_sda_o + attribute \src "ls180.v:10.14-10.24" + wire output 6 \i2c_sda_oe + attribute \src "ls180.v:1006.6-1006.16" + wire \i2c_status + attribute \src "ls180.v:1003.11-1003.22" + wire width 3 \i2c_storage + attribute \src "ls180.v:1007.6-1007.12" + wire \i2c_we + attribute \src "ls180.v:248.5-248.12" + wire \int_rst + attribute \src "ls180.v:869.6-869.9" + wire \irq + attribute \src "ls180.v:39.13-39.21" + wire input 35 \jtag_tck + attribute \src "ls180.v:40.13-40.21" + wire input 36 \jtag_tdi + attribute \src "ls180.v:41.14-41.22" + wire output 37 \jtag_tdo + attribute \src "ls180.v:38.13-38.21" + wire input 34 \jtag_tms + attribute \src "ls180.v:199.12-199.27" + wire width 7 \libresocsim_adr + attribute \src "ls180.v:52.6-52.27" + wire \libresocsim_bus_error + attribute \src "ls180.v:53.12-53.34" + wire width 32 \libresocsim_bus_errors + attribute \src "ls180.v:49.13-49.42" + wire width 32 \libresocsim_bus_errors_status + attribute \src "ls180.v:50.6-50.31" + wire \libresocsim_bus_errors_we + attribute \src "ls180.v:155.5-155.35" + wire \libresocsim_converter0_counter + attribute \src "ls180.v:1010.5-1010.70" + wire \libresocsim_converter0_counter_subfragments_converter0_next_value + attribute \src "ls180.v:1011.5-1011.73" + wire \libresocsim_converter0_counter_subfragments_converter0_next_value_ce + attribute \src "ls180.v:157.12-157.40" + wire width 64 \libresocsim_converter0_dat_r + attribute \src "ls180.v:156.6-156.34" + wire \libresocsim_converter0_reset + attribute \src "ls180.v:154.5-154.32" + wire \libresocsim_converter0_skip + attribute \src "ls180.v:170.5-170.35" + wire \libresocsim_converter1_counter + attribute \src "ls180.v:1014.5-1014.70" + wire \libresocsim_converter1_counter_subfragments_converter1_next_value + attribute \src "ls180.v:1015.5-1015.73" + wire \libresocsim_converter1_counter_subfragments_converter1_next_value_ce + attribute \src "ls180.v:172.12-172.40" + wire width 64 \libresocsim_converter1_dat_r + attribute \src "ls180.v:171.6-171.34" + wire \libresocsim_converter1_reset + attribute \src "ls180.v:169.5-169.32" + wire \libresocsim_converter1_skip + attribute \src "ls180.v:185.5-185.35" + wire \libresocsim_converter2_counter + attribute \src "ls180.v:1018.5-1018.70" + wire \libresocsim_converter2_counter_subfragments_converter2_next_value + attribute \src "ls180.v:1019.5-1019.73" + wire \libresocsim_converter2_counter_subfragments_converter2_next_value_ce + attribute \src "ls180.v:187.12-187.40" + wire width 64 \libresocsim_converter2_dat_r + attribute \src "ls180.v:186.6-186.34" + wire \libresocsim_converter2_reset + attribute \src "ls180.v:184.5-184.32" + wire \libresocsim_converter2_skip + attribute \src "ls180.v:1090.12-1090.29" + wire width 20 \libresocsim_count + attribute \src "ls180.v:1331.13-1331.45" + wire width 14 \libresocsim_csr_interconnect_adr + attribute \src "ls180.v:1334.12-1334.46" + wire width 8 \libresocsim_csr_interconnect_dat_r + attribute \src "ls180.v:1333.12-1333.46" + wire width 8 \libresocsim_csr_interconnect_dat_w + attribute \src "ls180.v:1332.6-1332.37" + wire \libresocsim_csr_interconnect_we + attribute \src "ls180.v:1128.12-1128.46" + wire width 8 \libresocsim_csrbank0_bus_errors0_r + attribute \src "ls180.v:1127.6-1127.41" + wire \libresocsim_csrbank0_bus_errors0_re + attribute \src "ls180.v:1130.12-1130.46" + wire width 8 \libresocsim_csrbank0_bus_errors0_w + attribute \src "ls180.v:1129.6-1129.41" + wire \libresocsim_csrbank0_bus_errors0_we + attribute \src "ls180.v:1124.12-1124.46" + wire width 8 \libresocsim_csrbank0_bus_errors1_r + attribute \src "ls180.v:1123.6-1123.41" + wire \libresocsim_csrbank0_bus_errors1_re + attribute \src "ls180.v:1126.12-1126.46" + wire width 8 \libresocsim_csrbank0_bus_errors1_w + attribute \src "ls180.v:1125.6-1125.41" + wire \libresocsim_csrbank0_bus_errors1_we + attribute \src "ls180.v:1120.12-1120.46" + wire width 8 \libresocsim_csrbank0_bus_errors2_r + attribute \src "ls180.v:1119.6-1119.41" + wire \libresocsim_csrbank0_bus_errors2_re + attribute \src "ls180.v:1122.12-1122.46" + wire width 8 \libresocsim_csrbank0_bus_errors2_w + attribute \src "ls180.v:1121.6-1121.41" + wire \libresocsim_csrbank0_bus_errors2_we + attribute \src "ls180.v:1116.12-1116.46" + wire width 8 \libresocsim_csrbank0_bus_errors3_r + attribute \src "ls180.v:1115.6-1115.41" + wire \libresocsim_csrbank0_bus_errors3_re + attribute \src "ls180.v:1118.12-1118.46" + wire width 8 \libresocsim_csrbank0_bus_errors3_w + attribute \src "ls180.v:1117.6-1117.41" + wire \libresocsim_csrbank0_bus_errors3_we + attribute \src "ls180.v:1096.6-1096.35" + wire \libresocsim_csrbank0_reset0_r + attribute \src "ls180.v:1095.6-1095.36" + wire \libresocsim_csrbank0_reset0_re + attribute \src "ls180.v:1098.6-1098.35" + wire \libresocsim_csrbank0_reset0_w + attribute \src "ls180.v:1097.6-1097.36" + wire \libresocsim_csrbank0_reset0_we + attribute \src "ls180.v:1112.12-1112.43" + wire width 8 \libresocsim_csrbank0_scratch0_r + attribute \src "ls180.v:1111.6-1111.38" + wire \libresocsim_csrbank0_scratch0_re + attribute \src "ls180.v:1114.12-1114.43" + wire width 8 \libresocsim_csrbank0_scratch0_w + attribute \src "ls180.v:1113.6-1113.38" + wire \libresocsim_csrbank0_scratch0_we + attribute \src "ls180.v:1108.12-1108.43" + wire width 8 \libresocsim_csrbank0_scratch1_r + attribute \src "ls180.v:1107.6-1107.38" + wire \libresocsim_csrbank0_scratch1_re + attribute \src "ls180.v:1110.12-1110.43" + wire width 8 \libresocsim_csrbank0_scratch1_w + attribute \src "ls180.v:1109.6-1109.38" + wire \libresocsim_csrbank0_scratch1_we + attribute \src "ls180.v:1104.12-1104.43" + wire width 8 \libresocsim_csrbank0_scratch2_r + attribute \src "ls180.v:1103.6-1103.38" + wire \libresocsim_csrbank0_scratch2_re + attribute \src "ls180.v:1106.12-1106.43" + wire width 8 \libresocsim_csrbank0_scratch2_w + attribute \src "ls180.v:1105.6-1105.38" + wire \libresocsim_csrbank0_scratch2_we + attribute \src "ls180.v:1100.12-1100.43" + wire width 8 \libresocsim_csrbank0_scratch3_r + attribute \src "ls180.v:1099.6-1099.38" + wire \libresocsim_csrbank0_scratch3_re + attribute \src "ls180.v:1102.12-1102.43" + wire width 8 \libresocsim_csrbank0_scratch3_w + attribute \src "ls180.v:1101.6-1101.38" + wire \libresocsim_csrbank0_scratch3_we + attribute \src "ls180.v:1131.6-1131.30" + wire \libresocsim_csrbank0_sel + attribute \src "ls180.v:1141.12-1141.37" + wire width 8 \libresocsim_csrbank1_in_r + attribute \src "ls180.v:1140.6-1140.32" + wire \libresocsim_csrbank1_in_re + attribute \src "ls180.v:1143.12-1143.37" + wire width 8 \libresocsim_csrbank1_in_w + attribute \src "ls180.v:1142.6-1142.32" + wire \libresocsim_csrbank1_in_we + attribute \src "ls180.v:1137.12-1137.38" + wire width 8 \libresocsim_csrbank1_oe0_r + attribute \src "ls180.v:1136.6-1136.33" + wire \libresocsim_csrbank1_oe0_re + attribute \src "ls180.v:1139.12-1139.38" + wire width 8 \libresocsim_csrbank1_oe0_w + attribute \src "ls180.v:1138.6-1138.33" + wire \libresocsim_csrbank1_oe0_we + attribute \src "ls180.v:1145.12-1145.39" + wire width 8 \libresocsim_csrbank1_out0_r + attribute \src "ls180.v:1144.6-1144.34" + wire \libresocsim_csrbank1_out0_re + attribute \src "ls180.v:1147.12-1147.39" + wire width 8 \libresocsim_csrbank1_out0_w + attribute \src "ls180.v:1146.6-1146.34" + wire \libresocsim_csrbank1_out0_we + attribute \src "ls180.v:1148.6-1148.30" + wire \libresocsim_csrbank1_sel + attribute \src "ls180.v:1158.12-1158.37" + wire width 8 \libresocsim_csrbank2_in_r + attribute \src "ls180.v:1157.6-1157.32" + wire \libresocsim_csrbank2_in_re + attribute \src "ls180.v:1160.12-1160.37" + wire width 8 \libresocsim_csrbank2_in_w + attribute \src "ls180.v:1159.6-1159.32" + wire \libresocsim_csrbank2_in_we + attribute \src "ls180.v:1154.12-1154.38" + wire width 8 \libresocsim_csrbank2_oe0_r + attribute \src "ls180.v:1153.6-1153.33" + wire \libresocsim_csrbank2_oe0_re + attribute \src "ls180.v:1156.12-1156.38" + wire width 8 \libresocsim_csrbank2_oe0_w + attribute \src "ls180.v:1155.6-1155.33" + wire \libresocsim_csrbank2_oe0_we + attribute \src "ls180.v:1162.12-1162.39" + wire width 8 \libresocsim_csrbank2_out0_r + attribute \src "ls180.v:1161.6-1161.34" + wire \libresocsim_csrbank2_out0_re + attribute \src "ls180.v:1164.12-1164.39" + wire width 8 \libresocsim_csrbank2_out0_w + attribute \src "ls180.v:1163.6-1163.34" + wire \libresocsim_csrbank2_out0_we + attribute \src "ls180.v:1165.6-1165.30" + wire \libresocsim_csrbank2_sel + attribute \src "ls180.v:1175.6-1175.30" + wire \libresocsim_csrbank3_r_r + attribute \src "ls180.v:1174.6-1174.31" + wire \libresocsim_csrbank3_r_re + attribute \src "ls180.v:1177.6-1177.30" + wire \libresocsim_csrbank3_r_w + attribute \src "ls180.v:1176.6-1176.31" + wire \libresocsim_csrbank3_r_we + attribute \src "ls180.v:1178.6-1178.30" + wire \libresocsim_csrbank3_sel + attribute \src "ls180.v:1171.12-1171.37" + wire width 3 \libresocsim_csrbank3_w0_r + attribute \src "ls180.v:1170.6-1170.32" + wire \libresocsim_csrbank3_w0_re + attribute \src "ls180.v:1173.12-1173.37" + wire width 3 \libresocsim_csrbank3_w0_w + attribute \src "ls180.v:1172.6-1172.32" + wire \libresocsim_csrbank3_w0_we + attribute \src "ls180.v:1184.12-1184.48" + wire width 4 \libresocsim_csrbank4_dfii_control0_r + attribute \src "ls180.v:1183.6-1183.43" + wire \libresocsim_csrbank4_dfii_control0_re + attribute \src "ls180.v:1186.12-1186.48" + wire width 4 \libresocsim_csrbank4_dfii_control0_w + attribute \src "ls180.v:1185.6-1185.43" + wire \libresocsim_csrbank4_dfii_control0_we + attribute \src "ls180.v:1196.12-1196.52" + wire width 8 \libresocsim_csrbank4_dfii_pi0_address0_r + attribute \src "ls180.v:1195.6-1195.47" + wire \libresocsim_csrbank4_dfii_pi0_address0_re + attribute \src "ls180.v:1198.12-1198.52" + wire width 8 \libresocsim_csrbank4_dfii_pi0_address0_w + attribute \src "ls180.v:1197.6-1197.47" + wire \libresocsim_csrbank4_dfii_pi0_address0_we + attribute \src "ls180.v:1192.12-1192.52" + wire width 5 \libresocsim_csrbank4_dfii_pi0_address1_r + attribute \src "ls180.v:1191.6-1191.47" + wire \libresocsim_csrbank4_dfii_pi0_address1_re + attribute \src "ls180.v:1194.12-1194.52" + wire width 5 \libresocsim_csrbank4_dfii_pi0_address1_w + attribute \src "ls180.v:1193.6-1193.47" + wire \libresocsim_csrbank4_dfii_pi0_address1_we + attribute \src "ls180.v:1200.12-1200.53" + wire width 2 \libresocsim_csrbank4_dfii_pi0_baddress0_r + attribute \src "ls180.v:1199.6-1199.48" + wire \libresocsim_csrbank4_dfii_pi0_baddress0_re + attribute \src "ls180.v:1202.12-1202.53" + wire width 2 \libresocsim_csrbank4_dfii_pi0_baddress0_w + attribute \src "ls180.v:1201.6-1201.48" + wire \libresocsim_csrbank4_dfii_pi0_baddress0_we + attribute \src "ls180.v:1188.12-1188.52" + wire width 6 \libresocsim_csrbank4_dfii_pi0_command0_r + attribute \src "ls180.v:1187.6-1187.47" + wire \libresocsim_csrbank4_dfii_pi0_command0_re + attribute \src "ls180.v:1190.12-1190.52" + wire width 6 \libresocsim_csrbank4_dfii_pi0_command0_w + attribute \src "ls180.v:1189.6-1189.47" + wire \libresocsim_csrbank4_dfii_pi0_command0_we + attribute \src "ls180.v:1216.12-1216.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata0_r + attribute \src "ls180.v:1215.6-1215.46" + wire \libresocsim_csrbank4_dfii_pi0_rddata0_re + attribute \src "ls180.v:1218.12-1218.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata0_w + attribute \src "ls180.v:1217.6-1217.46" + wire \libresocsim_csrbank4_dfii_pi0_rddata0_we + attribute \src "ls180.v:1212.12-1212.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata1_r + attribute \src "ls180.v:1211.6-1211.46" + wire \libresocsim_csrbank4_dfii_pi0_rddata1_re + attribute \src "ls180.v:1214.12-1214.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata1_w + attribute \src "ls180.v:1213.6-1213.46" + wire \libresocsim_csrbank4_dfii_pi0_rddata1_we + attribute \src "ls180.v:1208.12-1208.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata0_r + attribute \src "ls180.v:1207.6-1207.46" + wire \libresocsim_csrbank4_dfii_pi0_wrdata0_re + attribute \src "ls180.v:1210.12-1210.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata0_w + attribute \src "ls180.v:1209.6-1209.46" + wire \libresocsim_csrbank4_dfii_pi0_wrdata0_we + attribute \src "ls180.v:1204.12-1204.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata1_r + attribute \src "ls180.v:1203.6-1203.46" + wire \libresocsim_csrbank4_dfii_pi0_wrdata1_re + attribute \src "ls180.v:1206.12-1206.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata1_w + attribute \src "ls180.v:1205.6-1205.46" + wire \libresocsim_csrbank4_dfii_pi0_wrdata1_we + attribute \src "ls180.v:1219.6-1219.30" + wire \libresocsim_csrbank4_sel + attribute \src "ls180.v:1257.6-1257.32" + wire \libresocsim_csrbank5_en0_r + attribute \src "ls180.v:1256.6-1256.33" + wire \libresocsim_csrbank5_en0_re + attribute \src "ls180.v:1259.6-1259.32" + wire \libresocsim_csrbank5_en0_w + attribute \src "ls180.v:1258.6-1258.33" + wire \libresocsim_csrbank5_en0_we + attribute \src "ls180.v:1281.6-1281.39" + wire \libresocsim_csrbank5_ev_enable0_r + attribute \src "ls180.v:1280.6-1280.40" + wire \libresocsim_csrbank5_ev_enable0_re + attribute \src "ls180.v:1283.6-1283.39" + wire \libresocsim_csrbank5_ev_enable0_w + attribute \src "ls180.v:1282.6-1282.40" + wire \libresocsim_csrbank5_ev_enable0_we + attribute \src "ls180.v:1237.12-1237.40" + wire width 8 \libresocsim_csrbank5_load0_r + attribute \src "ls180.v:1236.6-1236.35" + wire \libresocsim_csrbank5_load0_re + attribute \src "ls180.v:1239.12-1239.40" + wire width 8 \libresocsim_csrbank5_load0_w + attribute \src "ls180.v:1238.6-1238.35" + wire \libresocsim_csrbank5_load0_we + attribute \src "ls180.v:1233.12-1233.40" + wire width 8 \libresocsim_csrbank5_load1_r + attribute \src "ls180.v:1232.6-1232.35" + wire \libresocsim_csrbank5_load1_re + attribute \src "ls180.v:1235.12-1235.40" + wire width 8 \libresocsim_csrbank5_load1_w + attribute \src "ls180.v:1234.6-1234.35" + wire \libresocsim_csrbank5_load1_we + attribute \src "ls180.v:1229.12-1229.40" + wire width 8 \libresocsim_csrbank5_load2_r + attribute \src "ls180.v:1228.6-1228.35" + wire \libresocsim_csrbank5_load2_re + attribute \src "ls180.v:1231.12-1231.40" + wire width 8 \libresocsim_csrbank5_load2_w + attribute \src "ls180.v:1230.6-1230.35" + wire \libresocsim_csrbank5_load2_we + attribute \src "ls180.v:1225.12-1225.40" + wire width 8 \libresocsim_csrbank5_load3_r + attribute \src "ls180.v:1224.6-1224.35" + wire \libresocsim_csrbank5_load3_re + attribute \src "ls180.v:1227.12-1227.40" + wire width 8 \libresocsim_csrbank5_load3_w + attribute \src "ls180.v:1226.6-1226.35" + wire \libresocsim_csrbank5_load3_we + attribute \src "ls180.v:1253.12-1253.42" + wire width 8 \libresocsim_csrbank5_reload0_r + attribute \src "ls180.v:1252.6-1252.37" + wire \libresocsim_csrbank5_reload0_re + attribute \src "ls180.v:1255.12-1255.42" + wire width 8 \libresocsim_csrbank5_reload0_w + attribute \src "ls180.v:1254.6-1254.37" + wire \libresocsim_csrbank5_reload0_we + attribute \src "ls180.v:1249.12-1249.42" + wire width 8 \libresocsim_csrbank5_reload1_r + attribute \src "ls180.v:1248.6-1248.37" + wire \libresocsim_csrbank5_reload1_re + attribute \src "ls180.v:1251.12-1251.42" + wire width 8 \libresocsim_csrbank5_reload1_w + attribute \src "ls180.v:1250.6-1250.37" + wire \libresocsim_csrbank5_reload1_we + attribute \src "ls180.v:1245.12-1245.42" + wire width 8 \libresocsim_csrbank5_reload2_r + attribute \src "ls180.v:1244.6-1244.37" + wire \libresocsim_csrbank5_reload2_re + attribute \src "ls180.v:1247.12-1247.42" + wire width 8 \libresocsim_csrbank5_reload2_w + attribute \src "ls180.v:1246.6-1246.37" + wire \libresocsim_csrbank5_reload2_we + attribute \src "ls180.v:1241.12-1241.42" + wire width 8 \libresocsim_csrbank5_reload3_r + attribute \src "ls180.v:1240.6-1240.37" + wire \libresocsim_csrbank5_reload3_re + attribute \src "ls180.v:1243.12-1243.42" + wire width 8 \libresocsim_csrbank5_reload3_w + attribute \src "ls180.v:1242.6-1242.37" + wire \libresocsim_csrbank5_reload3_we + attribute \src "ls180.v:1284.6-1284.30" + wire \libresocsim_csrbank5_sel + attribute \src "ls180.v:1261.6-1261.42" + wire \libresocsim_csrbank5_update_value0_r + attribute \src "ls180.v:1260.6-1260.43" + wire \libresocsim_csrbank5_update_value0_re + attribute \src "ls180.v:1263.6-1263.42" + wire \libresocsim_csrbank5_update_value0_w + attribute \src "ls180.v:1262.6-1262.43" + wire \libresocsim_csrbank5_update_value0_we + attribute \src "ls180.v:1277.12-1277.41" + wire width 8 \libresocsim_csrbank5_value0_r + attribute \src "ls180.v:1276.6-1276.36" + wire \libresocsim_csrbank5_value0_re + attribute \src "ls180.v:1279.12-1279.41" + wire width 8 \libresocsim_csrbank5_value0_w + attribute \src "ls180.v:1278.6-1278.36" + wire \libresocsim_csrbank5_value0_we + attribute \src "ls180.v:1273.12-1273.41" + wire width 8 \libresocsim_csrbank5_value1_r + attribute \src "ls180.v:1272.6-1272.36" + wire \libresocsim_csrbank5_value1_re + attribute \src "ls180.v:1275.12-1275.41" + wire width 8 \libresocsim_csrbank5_value1_w + attribute \src "ls180.v:1274.6-1274.36" + wire \libresocsim_csrbank5_value1_we + attribute \src "ls180.v:1269.12-1269.41" + wire width 8 \libresocsim_csrbank5_value2_r + attribute \src "ls180.v:1268.6-1268.36" + wire \libresocsim_csrbank5_value2_re + attribute \src "ls180.v:1271.12-1271.41" + wire width 8 \libresocsim_csrbank5_value2_w + attribute \src "ls180.v:1270.6-1270.36" + wire \libresocsim_csrbank5_value2_we + attribute \src "ls180.v:1265.12-1265.41" + wire width 8 \libresocsim_csrbank5_value3_r + attribute \src "ls180.v:1264.6-1264.36" + wire \libresocsim_csrbank5_value3_re + attribute \src "ls180.v:1267.12-1267.41" + wire width 8 \libresocsim_csrbank5_value3_w + attribute \src "ls180.v:1266.6-1266.36" + wire \libresocsim_csrbank5_value3_we + attribute \src "ls180.v:1298.12-1298.45" + wire width 2 \libresocsim_csrbank6_ev_enable0_r + attribute \src "ls180.v:1297.6-1297.40" + wire \libresocsim_csrbank6_ev_enable0_re + attribute \src "ls180.v:1300.12-1300.45" + wire width 2 \libresocsim_csrbank6_ev_enable0_w + attribute \src "ls180.v:1299.6-1299.40" + wire \libresocsim_csrbank6_ev_enable0_we + attribute \src "ls180.v:1294.6-1294.36" + wire \libresocsim_csrbank6_rxempty_r + attribute \src "ls180.v:1293.6-1293.37" + wire \libresocsim_csrbank6_rxempty_re + attribute \src "ls180.v:1296.6-1296.36" + wire \libresocsim_csrbank6_rxempty_w + attribute \src "ls180.v:1295.6-1295.37" + wire \libresocsim_csrbank6_rxempty_we + attribute \src "ls180.v:1306.6-1306.35" + wire \libresocsim_csrbank6_rxfull_r + attribute \src "ls180.v:1305.6-1305.36" + wire \libresocsim_csrbank6_rxfull_re + attribute \src "ls180.v:1308.6-1308.35" + wire \libresocsim_csrbank6_rxfull_w + attribute \src "ls180.v:1307.6-1307.36" + wire \libresocsim_csrbank6_rxfull_we + attribute \src "ls180.v:1309.6-1309.30" + wire \libresocsim_csrbank6_sel + attribute \src "ls180.v:1302.6-1302.36" + wire \libresocsim_csrbank6_txempty_r + attribute \src "ls180.v:1301.6-1301.37" + wire \libresocsim_csrbank6_txempty_re + attribute \src "ls180.v:1304.6-1304.36" + wire \libresocsim_csrbank6_txempty_w + attribute \src "ls180.v:1303.6-1303.37" + wire \libresocsim_csrbank6_txempty_we + attribute \src "ls180.v:1290.6-1290.35" + wire \libresocsim_csrbank6_txfull_r + attribute \src "ls180.v:1289.6-1289.36" + wire \libresocsim_csrbank6_txfull_re + attribute \src "ls180.v:1292.6-1292.35" + wire \libresocsim_csrbank6_txfull_w + attribute \src "ls180.v:1291.6-1291.36" + wire \libresocsim_csrbank6_txfull_we + attribute \src "ls180.v:1330.6-1330.30" + wire \libresocsim_csrbank7_sel + attribute \src "ls180.v:1327.12-1327.47" + wire width 8 \libresocsim_csrbank7_tuning_word0_r + attribute \src "ls180.v:1326.6-1326.42" + wire \libresocsim_csrbank7_tuning_word0_re + attribute \src "ls180.v:1329.12-1329.47" + wire width 8 \libresocsim_csrbank7_tuning_word0_w + attribute \src "ls180.v:1328.6-1328.42" + wire \libresocsim_csrbank7_tuning_word0_we + attribute \src "ls180.v:1323.12-1323.47" + wire width 8 \libresocsim_csrbank7_tuning_word1_r + attribute \src "ls180.v:1322.6-1322.42" + wire \libresocsim_csrbank7_tuning_word1_re + attribute \src "ls180.v:1325.12-1325.47" + wire width 8 \libresocsim_csrbank7_tuning_word1_w + attribute \src "ls180.v:1324.6-1324.42" + wire \libresocsim_csrbank7_tuning_word1_we + attribute \src "ls180.v:1319.12-1319.47" + wire width 8 \libresocsim_csrbank7_tuning_word2_r + attribute \src "ls180.v:1318.6-1318.42" + wire \libresocsim_csrbank7_tuning_word2_re + attribute \src "ls180.v:1321.12-1321.47" + wire width 8 \libresocsim_csrbank7_tuning_word2_w + attribute \src "ls180.v:1320.6-1320.42" + wire \libresocsim_csrbank7_tuning_word2_we + attribute \src "ls180.v:1315.12-1315.47" + wire width 8 \libresocsim_csrbank7_tuning_word3_r + attribute \src "ls180.v:1314.6-1314.42" + wire \libresocsim_csrbank7_tuning_word3_re + attribute \src "ls180.v:1317.12-1317.47" + wire width 8 \libresocsim_csrbank7_tuning_word3_w + attribute \src "ls180.v:1316.6-1316.42" + wire \libresocsim_csrbank7_tuning_word3_we + attribute \src "ls180.v:200.13-200.30" + wire width 32 \libresocsim_dat_r + attribute \src "ls180.v:202.13-202.30" + wire width 32 \libresocsim_dat_w + attribute \src "ls180.v:1089.6-1089.22" + wire \libresocsim_done + attribute \src "ls180.v:208.5-208.22" + wire \libresocsim_en_re + attribute \src "ls180.v:207.5-207.27" + wire \libresocsim_en_storage + attribute \src "ls180.v:1087.5-1087.22" + wire \libresocsim_error + attribute \src "ls180.v:224.6-224.40" + wire \libresocsim_eventmanager_pending_r + attribute \src "ls180.v:223.6-223.41" + wire \libresocsim_eventmanager_pending_re + attribute \src "ls180.v:226.6-226.40" + wire \libresocsim_eventmanager_pending_w + attribute \src "ls180.v:225.6-225.41" + wire \libresocsim_eventmanager_pending_we + attribute \src "ls180.v:228.5-228.32" + wire \libresocsim_eventmanager_re + attribute \src "ls180.v:220.6-220.39" + wire \libresocsim_eventmanager_status_r + attribute \src "ls180.v:219.6-219.40" + wire \libresocsim_eventmanager_status_re + attribute \src "ls180.v:222.6-222.39" + wire \libresocsim_eventmanager_status_w + attribute \src "ls180.v:221.6-221.40" + wire \libresocsim_eventmanager_status_we + attribute \src "ls180.v:227.5-227.37" + wire \libresocsim_eventmanager_storage + attribute \src "ls180.v:1084.11-1084.28" + wire width 2 \libresocsim_grant + attribute \src "ls180.v:1091.13-1091.48" + wire width 14 \libresocsim_interface0_bank_bus_adr + attribute \src "ls180.v:1094.11-1094.48" + wire width 8 \libresocsim_interface0_bank_bus_dat_r + attribute \src "ls180.v:1093.12-1093.49" + wire width 8 \libresocsim_interface0_bank_bus_dat_w + attribute \src "ls180.v:1092.6-1092.40" + wire \libresocsim_interface0_bank_bus_we + attribute \src "ls180.v:149.6-149.52" + wire \libresocsim_interface0_converted_interface_ack + attribute \src "ls180.v:143.12-143.58" + wire width 30 \libresocsim_interface0_converted_interface_adr + attribute \src "ls180.v:152.11-152.57" + wire width 2 \libresocsim_interface0_converted_interface_bte + attribute \src "ls180.v:151.11-151.57" + wire width 3 \libresocsim_interface0_converted_interface_cti + attribute \src "ls180.v:147.5-147.51" + wire \libresocsim_interface0_converted_interface_cyc + attribute \src "ls180.v:145.13-145.61" + wire width 32 \libresocsim_interface0_converted_interface_dat_r + attribute \src "ls180.v:144.12-144.60" + wire width 32 \libresocsim_interface0_converted_interface_dat_w + attribute \src "ls180.v:153.6-153.52" + wire \libresocsim_interface0_converted_interface_err + attribute \src "ls180.v:146.11-146.57" + wire width 4 \libresocsim_interface0_converted_interface_sel + attribute \src "ls180.v:148.5-148.51" + wire \libresocsim_interface0_converted_interface_stb + attribute \src "ls180.v:150.5-150.50" + wire \libresocsim_interface0_converted_interface_we + attribute \src "ls180.v:1132.13-1132.48" + wire width 14 \libresocsim_interface1_bank_bus_adr + attribute \src "ls180.v:1135.11-1135.48" + wire width 8 \libresocsim_interface1_bank_bus_dat_r + attribute \src "ls180.v:1134.12-1134.49" + wire width 8 \libresocsim_interface1_bank_bus_dat_w + attribute \src "ls180.v:1133.6-1133.40" + wire \libresocsim_interface1_bank_bus_we + attribute \src "ls180.v:164.6-164.52" + wire \libresocsim_interface1_converted_interface_ack + attribute \src "ls180.v:158.12-158.58" + wire width 30 \libresocsim_interface1_converted_interface_adr + attribute \src "ls180.v:167.11-167.57" + wire width 2 \libresocsim_interface1_converted_interface_bte + attribute \src "ls180.v:166.11-166.57" + wire width 3 \libresocsim_interface1_converted_interface_cti + attribute \src "ls180.v:162.5-162.51" + wire \libresocsim_interface1_converted_interface_cyc + attribute \src "ls180.v:160.13-160.61" + wire width 32 \libresocsim_interface1_converted_interface_dat_r + attribute \src "ls180.v:159.12-159.60" + wire width 32 \libresocsim_interface1_converted_interface_dat_w + attribute \src "ls180.v:168.6-168.52" + wire \libresocsim_interface1_converted_interface_err + attribute \src "ls180.v:161.11-161.57" + wire width 4 \libresocsim_interface1_converted_interface_sel + attribute \src "ls180.v:163.5-163.51" + wire \libresocsim_interface1_converted_interface_stb + attribute \src "ls180.v:165.5-165.50" + wire \libresocsim_interface1_converted_interface_we + attribute \src "ls180.v:1149.13-1149.48" + wire width 14 \libresocsim_interface2_bank_bus_adr + attribute \src "ls180.v:1152.11-1152.48" + wire width 8 \libresocsim_interface2_bank_bus_dat_r + attribute \src "ls180.v:1151.12-1151.49" + wire width 8 \libresocsim_interface2_bank_bus_dat_w + attribute \src "ls180.v:1150.6-1150.40" + wire \libresocsim_interface2_bank_bus_we + attribute \src "ls180.v:179.6-179.52" + wire \libresocsim_interface2_converted_interface_ack + attribute \src "ls180.v:173.12-173.58" + wire width 30 \libresocsim_interface2_converted_interface_adr + attribute \src "ls180.v:182.11-182.57" + wire width 2 \libresocsim_interface2_converted_interface_bte + attribute \src "ls180.v:181.11-181.57" + wire width 3 \libresocsim_interface2_converted_interface_cti + attribute \src "ls180.v:177.5-177.51" + wire \libresocsim_interface2_converted_interface_cyc + attribute \src "ls180.v:175.13-175.61" + wire width 32 \libresocsim_interface2_converted_interface_dat_r + attribute \src "ls180.v:174.12-174.60" + wire width 32 \libresocsim_interface2_converted_interface_dat_w + attribute \src "ls180.v:183.6-183.52" + wire \libresocsim_interface2_converted_interface_err + attribute \src "ls180.v:176.11-176.57" + wire width 4 \libresocsim_interface2_converted_interface_sel + attribute \src "ls180.v:178.5-178.51" + wire \libresocsim_interface2_converted_interface_stb + attribute \src "ls180.v:180.5-180.50" + wire \libresocsim_interface2_converted_interface_we + attribute \src "ls180.v:1166.13-1166.48" + wire width 14 \libresocsim_interface3_bank_bus_adr + attribute \src "ls180.v:1169.11-1169.48" + wire width 8 \libresocsim_interface3_bank_bus_dat_r + attribute \src "ls180.v:1168.12-1168.49" + wire width 8 \libresocsim_interface3_bank_bus_dat_w + attribute \src "ls180.v:1167.6-1167.40" + wire \libresocsim_interface3_bank_bus_we + attribute \src "ls180.v:1179.13-1179.48" + wire width 14 \libresocsim_interface4_bank_bus_adr + attribute \src "ls180.v:1182.11-1182.48" + wire width 8 \libresocsim_interface4_bank_bus_dat_r + attribute \src "ls180.v:1181.12-1181.49" + wire width 8 \libresocsim_interface4_bank_bus_dat_w + attribute \src "ls180.v:1180.6-1180.40" + wire \libresocsim_interface4_bank_bus_we + attribute \src "ls180.v:1220.13-1220.48" + wire width 14 \libresocsim_interface5_bank_bus_adr + attribute \src "ls180.v:1223.11-1223.48" + wire width 8 \libresocsim_interface5_bank_bus_dat_r + attribute \src "ls180.v:1222.12-1222.49" + wire width 8 \libresocsim_interface5_bank_bus_dat_w + attribute \src "ls180.v:1221.6-1221.40" + wire \libresocsim_interface5_bank_bus_we + attribute \src "ls180.v:1285.13-1285.48" + wire width 14 \libresocsim_interface6_bank_bus_adr + attribute \src "ls180.v:1288.11-1288.48" + wire width 8 \libresocsim_interface6_bank_bus_dat_r + attribute \src "ls180.v:1287.12-1287.49" + wire width 8 \libresocsim_interface6_bank_bus_dat_w + attribute \src "ls180.v:1286.6-1286.40" + wire \libresocsim_interface6_bank_bus_we + attribute \src "ls180.v:1310.13-1310.48" + wire width 14 \libresocsim_interface7_bank_bus_adr + attribute \src "ls180.v:1313.11-1313.48" + wire width 8 \libresocsim_interface7_bank_bus_dat_r + attribute \src "ls180.v:1312.12-1312.49" + wire width 8 \libresocsim_interface7_bank_bus_dat_w + attribute \src "ls180.v:1311.6-1311.40" + wire \libresocsim_interface7_bank_bus_we + attribute \src "ls180.v:213.6-213.21" + wire \libresocsim_irq + attribute \src "ls180.v:109.6-109.27" + wire \libresocsim_libresoc0 + attribute \src "ls180.v:110.6-110.27" + wire \libresocsim_libresoc1 + attribute \src "ls180.v:111.13-111.34" + wire width 64 \libresocsim_libresoc2 + attribute \src "ls180.v:113.12-113.40" + wire width 2 \libresocsim_libresoc_clk_sel + attribute \src "ls180.v:140.6-140.51" + wire \libresocsim_libresoc_constraintmanager_eint_0 + attribute \src "ls180.v:141.6-141.51" + wire \libresocsim_libresoc_constraintmanager_eint_1 + attribute \src "ls180.v:142.6-142.51" + wire \libresocsim_libresoc_constraintmanager_eint_2 + attribute \src "ls180.v:121.13-121.58" + wire width 16 \libresocsim_libresoc_constraintmanager_gpio_i + attribute \src "ls180.v:122.12-122.57" + wire width 16 \libresocsim_libresoc_constraintmanager_gpio_o + attribute \src "ls180.v:123.12-123.58" + wire width 16 \libresocsim_libresoc_constraintmanager_gpio_oe + attribute \src "ls180.v:117.6-117.52" + wire \libresocsim_libresoc_constraintmanager_i2c_scl + attribute \src "ls180.v:118.6-118.54" + wire \libresocsim_libresoc_constraintmanager_i2c_sda_i + attribute \src "ls180.v:119.6-119.54" + wire \libresocsim_libresoc_constraintmanager_i2c_sda_o + attribute \src "ls180.v:120.6-120.55" + wire \libresocsim_libresoc_constraintmanager_i2c_sda_oe + attribute \src "ls180.v:128.12-128.58" + wire width 13 \libresocsim_libresoc_constraintmanager_sdram_a + attribute \src "ls180.v:137.11-137.58" + wire width 2 \libresocsim_libresoc_constraintmanager_sdram_ba + attribute \src "ls180.v:134.5-134.55" + wire \libresocsim_libresoc_constraintmanager_sdram_cas_n + attribute \src "ls180.v:136.5-136.53" + wire \libresocsim_libresoc_constraintmanager_sdram_cke + attribute \src "ls180.v:139.5-139.55" + wire \libresocsim_libresoc_constraintmanager_sdram_clock + attribute \src "ls180.v:135.5-135.54" + wire \libresocsim_libresoc_constraintmanager_sdram_cs_n + attribute \src "ls180.v:138.11-138.58" + wire width 2 \libresocsim_libresoc_constraintmanager_sdram_dm + attribute \src "ls180.v:129.13-129.62" + wire width 16 \libresocsim_libresoc_constraintmanager_sdram_dq_i + attribute \src "ls180.v:130.12-130.61" + wire width 16 \libresocsim_libresoc_constraintmanager_sdram_dq_o + attribute \src "ls180.v:131.5-131.55" + wire \libresocsim_libresoc_constraintmanager_sdram_dq_oe + attribute \src "ls180.v:133.5-133.55" + wire \libresocsim_libresoc_constraintmanager_sdram_ras_n + attribute \src "ls180.v:132.5-132.54" + wire \libresocsim_libresoc_constraintmanager_sdram_we_n + attribute \src "ls180.v:124.5-124.57" + wire \libresocsim_libresoc_constraintmanager_spimaster_clk + attribute \src "ls180.v:126.5-126.58" + wire \libresocsim_libresoc_constraintmanager_spimaster_cs_n + attribute \src "ls180.v:127.6-127.59" + wire \libresocsim_libresoc_constraintmanager_spimaster_miso + attribute \src "ls180.v:125.5-125.58" + wire \libresocsim_libresoc_constraintmanager_spimaster_mosi + attribute \src "ls180.v:116.5-116.51" + wire \libresocsim_libresoc_constraintmanager_uart_rx + attribute \src "ls180.v:115.5-115.51" + wire \libresocsim_libresoc_constraintmanager_uart_tx + attribute \src "ls180.v:62.5-62.34" + wire \libresocsim_libresoc_dbus_ack + attribute \src "ls180.v:56.13-56.42" + wire width 29 \libresocsim_libresoc_dbus_adr + attribute \src "ls180.v:60.6-60.35" + wire \libresocsim_libresoc_dbus_cyc + attribute \src "ls180.v:58.13-58.44" + wire width 64 \libresocsim_libresoc_dbus_dat_r + attribute \src "ls180.v:57.13-57.44" + wire width 64 \libresocsim_libresoc_dbus_dat_w + attribute \src "ls180.v:64.5-64.34" + wire \libresocsim_libresoc_dbus_err + attribute \src "ls180.v:59.12-59.41" + wire width 8 \libresocsim_libresoc_dbus_sel + attribute \src "ls180.v:61.6-61.35" + wire \libresocsim_libresoc_dbus_stb + attribute \src "ls180.v:63.6-63.34" + wire \libresocsim_libresoc_dbus_we + attribute \src "ls180.v:71.5-71.34" + wire \libresocsim_libresoc_ibus_ack + attribute \src "ls180.v:65.13-65.42" + wire width 29 \libresocsim_libresoc_ibus_adr + attribute \src "ls180.v:69.6-69.35" + wire \libresocsim_libresoc_ibus_cyc + attribute \src "ls180.v:67.13-67.44" + wire width 64 \libresocsim_libresoc_ibus_dat_r + attribute \src "ls180.v:66.13-66.44" + wire width 64 \libresocsim_libresoc_ibus_dat_w + attribute \src "ls180.v:73.5-73.34" + wire \libresocsim_libresoc_ibus_err + attribute \src "ls180.v:68.12-68.41" + wire width 8 \libresocsim_libresoc_ibus_sel + attribute \src "ls180.v:70.6-70.35" + wire \libresocsim_libresoc_ibus_stb + attribute \src "ls180.v:72.6-72.34" + wire \libresocsim_libresoc_ibus_we + attribute \src "ls180.v:55.12-55.42" + wire width 16 \libresocsim_libresoc_interrupt + attribute \src "ls180.v:105.6-105.35" + wire \libresocsim_libresoc_jtag_tck + attribute \src "ls180.v:107.6-107.35" + wire \libresocsim_libresoc_jtag_tdi + attribute \src "ls180.v:108.6-108.35" + wire \libresocsim_libresoc_jtag_tdo + attribute \src "ls180.v:106.6-106.35" + wire \libresocsim_libresoc_jtag_tms + attribute \src "ls180.v:102.5-102.37" + wire \libresocsim_libresoc_jtag_wb_ack + attribute \src "ls180.v:96.13-96.45" + wire width 29 \libresocsim_libresoc_jtag_wb_adr + attribute \src "ls180.v:100.6-100.38" + wire \libresocsim_libresoc_jtag_wb_cyc + attribute \src "ls180.v:98.13-98.47" + wire width 64 \libresocsim_libresoc_jtag_wb_dat_r + attribute \src "ls180.v:97.13-97.47" + wire width 64 \libresocsim_libresoc_jtag_wb_dat_w + attribute \src "ls180.v:104.5-104.37" + wire \libresocsim_libresoc_jtag_wb_err + attribute \src "ls180.v:99.12-99.44" + wire width 8 \libresocsim_libresoc_jtag_wb_sel + attribute \src "ls180.v:101.6-101.38" + wire \libresocsim_libresoc_jtag_wb_stb + attribute \src "ls180.v:103.6-103.37" + wire \libresocsim_libresoc_jtag_wb_we + attribute \src "ls180.v:112.6-112.35" + wire \libresocsim_libresoc_pll_18_o + attribute \src "ls180.v:114.6-114.36" + wire \libresocsim_libresoc_pll_lck_o + attribute \src "ls180.v:54.6-54.32" + wire \libresocsim_libresoc_reset + attribute \src "ls180.v:80.6-80.39" + wire \libresocsim_libresoc_xics_icp_ack + attribute \src "ls180.v:74.13-74.46" + wire width 30 \libresocsim_libresoc_xics_icp_adr + attribute \src "ls180.v:83.12-83.45" + wire width 2 \libresocsim_libresoc_xics_icp_bte + attribute \src "ls180.v:82.12-82.45" + wire width 3 \libresocsim_libresoc_xics_icp_cti + attribute \src "ls180.v:78.6-78.39" + wire \libresocsim_libresoc_xics_icp_cyc + attribute \src "ls180.v:76.13-76.48" + wire width 32 \libresocsim_libresoc_xics_icp_dat_r + attribute \src "ls180.v:75.13-75.48" + wire width 32 \libresocsim_libresoc_xics_icp_dat_w + attribute \src "ls180.v:84.6-84.39" + wire \libresocsim_libresoc_xics_icp_err + attribute \src "ls180.v:77.12-77.45" + wire width 4 \libresocsim_libresoc_xics_icp_sel + attribute \src "ls180.v:79.6-79.39" + wire \libresocsim_libresoc_xics_icp_stb + attribute \src "ls180.v:81.6-81.38" + wire \libresocsim_libresoc_xics_icp_we + attribute \src "ls180.v:91.6-91.39" + wire \libresocsim_libresoc_xics_ics_ack + attribute \src "ls180.v:85.13-85.46" + wire width 30 \libresocsim_libresoc_xics_ics_adr + attribute \src "ls180.v:94.12-94.45" + wire width 2 \libresocsim_libresoc_xics_ics_bte + attribute \src "ls180.v:93.12-93.45" + wire width 3 \libresocsim_libresoc_xics_ics_cti + attribute \src "ls180.v:89.6-89.39" + wire \libresocsim_libresoc_xics_ics_cyc + attribute \src "ls180.v:87.13-87.48" + wire width 32 \libresocsim_libresoc_xics_ics_dat_r + attribute \src "ls180.v:86.13-86.48" + wire width 32 \libresocsim_libresoc_xics_ics_dat_w + attribute \src "ls180.v:95.6-95.39" + wire \libresocsim_libresoc_xics_ics_err + attribute \src "ls180.v:88.12-88.45" + wire width 4 \libresocsim_libresoc_xics_ics_sel + attribute \src "ls180.v:90.6-90.39" + wire \libresocsim_libresoc_xics_ics_stb + attribute \src "ls180.v:92.6-92.38" + wire \libresocsim_libresoc_xics_ics_we + attribute \src "ls180.v:1057.12-1057.39" + wire width 14 \libresocsim_libresocsim_adr + attribute \src "ls180.v:1339.12-1339.63" + wire width 14 \libresocsim_libresocsim_adr_libresocsim_next_value1 + attribute \src "ls180.v:1340.5-1340.59" + wire \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 + attribute \src "ls180.v:1060.12-1060.41" + wire width 8 \libresocsim_libresocsim_dat_r + attribute \src "ls180.v:1059.11-1059.40" + wire width 8 \libresocsim_libresocsim_dat_w + attribute \src "ls180.v:1337.11-1337.64" + wire width 8 \libresocsim_libresocsim_dat_w_libresocsim_next_value0 + attribute \src "ls180.v:1338.5-1338.61" + wire \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 + attribute \src "ls180.v:1058.5-1058.31" + wire \libresocsim_libresocsim_we + attribute \src "ls180.v:1341.5-1341.55" + wire \libresocsim_libresocsim_we_libresocsim_next_value2 + attribute \src "ls180.v:1342.5-1342.58" + wire \libresocsim_libresocsim_we_libresocsim_next_value_ce2 + attribute \src "ls180.v:1067.5-1067.41" + wire \libresocsim_libresocsim_wishbone_ack + attribute \src "ls180.v:1061.13-1061.49" + wire width 30 \libresocsim_libresocsim_wishbone_adr + attribute \src "ls180.v:1070.12-1070.48" + wire width 2 \libresocsim_libresocsim_wishbone_bte + attribute \src "ls180.v:1069.12-1069.48" + wire width 3 \libresocsim_libresocsim_wishbone_cti + attribute \src "ls180.v:1065.6-1065.42" + wire \libresocsim_libresocsim_wishbone_cyc + attribute \src "ls180.v:1063.12-1063.50" + wire width 32 \libresocsim_libresocsim_wishbone_dat_r + attribute \src "ls180.v:1062.13-1062.51" + wire width 32 \libresocsim_libresocsim_wishbone_dat_w + attribute \src "ls180.v:1071.5-1071.41" + wire \libresocsim_libresocsim_wishbone_err + attribute \src "ls180.v:1064.12-1064.48" + wire width 4 \libresocsim_libresocsim_wishbone_sel + attribute \src "ls180.v:1066.6-1066.42" + wire \libresocsim_libresocsim_wishbone_stb + attribute \src "ls180.v:1068.6-1068.41" + wire \libresocsim_libresocsim_wishbone_we + attribute \src "ls180.v:204.5-204.24" + wire \libresocsim_load_re + attribute \src "ls180.v:203.12-203.36" + wire width 32 \libresocsim_load_storage + attribute \src "ls180.v:1336.11-1336.33" + wire width 2 \libresocsim_next_state + attribute \src "ls180.v:194.5-194.28" + wire \libresocsim_ram_bus_ack + attribute \src "ls180.v:188.13-188.36" + wire width 30 \libresocsim_ram_bus_adr + attribute \src "ls180.v:197.12-197.35" + wire width 2 \libresocsim_ram_bus_bte + attribute \src "ls180.v:196.12-196.35" + wire width 3 \libresocsim_ram_bus_cti + attribute \src "ls180.v:192.6-192.29" + wire \libresocsim_ram_bus_cyc + attribute \src "ls180.v:190.13-190.38" + wire width 32 \libresocsim_ram_bus_dat_r + attribute \src "ls180.v:189.13-189.38" + wire width 32 \libresocsim_ram_bus_dat_w + attribute \src "ls180.v:198.5-198.28" + wire \libresocsim_ram_bus_err + attribute \src "ls180.v:191.12-191.35" + wire width 4 \libresocsim_ram_bus_sel + attribute \src "ls180.v:193.6-193.29" + wire \libresocsim_ram_bus_stb + attribute \src "ls180.v:195.6-195.28" + wire \libresocsim_ram_bus_we + attribute \src "ls180.v:206.5-206.26" + wire \libresocsim_reload_re + attribute \src "ls180.v:205.12-205.38" + wire width 32 \libresocsim_reload_storage + attribute \src "ls180.v:1083.12-1083.31" + wire width 3 \libresocsim_request + attribute \src "ls180.v:51.6-51.23" + wire \libresocsim_reset + attribute \src "ls180.v:46.5-46.25" + wire \libresocsim_reset_re + attribute \src "ls180.v:45.5-45.30" + wire \libresocsim_reset_storage + attribute \src "ls180.v:48.5-48.27" + wire \libresocsim_scratch_re + attribute \src "ls180.v:47.12-47.39" + wire width 32 \libresocsim_scratch_storage + attribute \src "ls180.v:1078.5-1078.27" + wire \libresocsim_shared_ack + attribute \src "ls180.v:1072.13-1072.35" + wire width 30 \libresocsim_shared_adr + attribute \src "ls180.v:1081.12-1081.34" + wire width 2 \libresocsim_shared_bte + attribute \src "ls180.v:1080.12-1080.34" + wire width 3 \libresocsim_shared_cti + attribute \src "ls180.v:1076.6-1076.28" + wire \libresocsim_shared_cyc + attribute \src "ls180.v:1074.12-1074.36" + wire width 32 \libresocsim_shared_dat_r + attribute \src "ls180.v:1073.13-1073.37" + wire width 32 \libresocsim_shared_dat_w + attribute \src "ls180.v:1082.6-1082.28" + wire \libresocsim_shared_err + attribute \src "ls180.v:1075.12-1075.34" + wire width 4 \libresocsim_shared_sel + attribute \src "ls180.v:1077.6-1077.28" + wire \libresocsim_shared_stb + attribute \src "ls180.v:1079.6-1079.27" + wire \libresocsim_shared_we + attribute \src "ls180.v:1085.11-1085.32" + wire width 6 \libresocsim_slave_sel + attribute \src "ls180.v:1086.11-1086.34" + wire width 6 \libresocsim_slave_sel_r + attribute \src "ls180.v:1335.11-1335.28" + wire width 2 \libresocsim_state + attribute \src "ls180.v:210.5-210.32" + wire \libresocsim_update_value_re + attribute \src "ls180.v:209.5-209.37" + wire \libresocsim_update_value_storage + attribute \src "ls180.v:229.12-229.29" + wire width 32 \libresocsim_value + attribute \src "ls180.v:211.12-211.36" + wire width 32 \libresocsim_value_status + attribute \src "ls180.v:212.6-212.26" + wire \libresocsim_value_we + attribute \src "ls180.v:1088.6-1088.22" + wire \libresocsim_wait + attribute \src "ls180.v:201.11-201.25" + wire width 4 \libresocsim_we + attribute \src "ls180.v:217.5-217.27" + wire \libresocsim_zero_clear + attribute \src "ls180.v:218.5-218.33" + wire \libresocsim_zero_old_trigger + attribute \src "ls180.v:215.5-215.29" + wire \libresocsim_zero_pending + attribute \src "ls180.v:214.6-214.29" + wire \libresocsim_zero_status + attribute \src "ls180.v:216.6-216.30" + wire \libresocsim_zero_trigger + attribute \src "ls180.v:826.6-826.21" + wire \litedram_wb_ack + attribute \src "ls180.v:820.12-820.27" + wire width 30 \litedram_wb_adr + attribute \src "ls180.v:824.5-824.20" + wire \litedram_wb_cyc + attribute \src "ls180.v:822.13-822.30" + wire width 16 \litedram_wb_dat_r + attribute \src "ls180.v:821.12-821.29" + wire width 16 \litedram_wb_dat_w + attribute \src "ls180.v:823.11-823.26" + wire width 2 \litedram_wb_sel + attribute \src "ls180.v:825.5-825.20" + wire \litedram_wb_stb + attribute \src "ls180.v:827.5-827.19" + wire \litedram_wb_we + attribute \src "ls180.v:5494.11-5494.17" + wire width 7 \memadr + attribute \src "ls180.v:5514.11-5514.19" + wire width 5 \memadr_1 + attribute \src "ls180.v:5534.12-5534.18" + wire width 25 \memdat + attribute \src "ls180.v:5548.12-5548.20" + wire width 25 \memdat_1 + attribute \src "ls180.v:5562.12-5562.20" + wire width 25 \memdat_2 + attribute \src "ls180.v:5576.12-5576.20" + wire width 25 \memdat_3 + attribute \src "ls180.v:5590.11-5590.19" + wire width 10 \memdat_4 + attribute \src "ls180.v:5591.11-5591.19" + wire width 10 \memdat_5 + attribute \src "ls180.v:5607.11-5607.19" + wire width 10 \memdat_6 + attribute \src "ls180.v:5608.11-5608.19" + wire width 10 \memdat_7 + attribute \src "ls180.v:42.20-42.22" + wire width 36 input 38 \nc + attribute \src "ls180.v:998.13-998.17" + wire width 36 \nc_1 + attribute \src "ls180.v:247.6-247.13" + wire \por_clk + attribute \src "ls180.v:799.6-799.19" + wire \port_cmd_last + attribute \src "ls180.v:801.13-801.34" + wire width 24 \port_cmd_payload_addr + attribute \src "ls180.v:800.6-800.25" + wire \port_cmd_payload_we + attribute \src "ls180.v:798.6-798.20" + wire \port_cmd_ready + attribute \src "ls180.v:797.6-797.20" + wire \port_cmd_valid + attribute \src "ls180.v:796.6-796.16" + wire \port_flush + attribute \src "ls180.v:808.13-808.36" + wire width 16 \port_rdata_payload_data + attribute \src "ls180.v:807.6-807.22" + wire \port_rdata_ready + attribute \src "ls180.v:806.6-806.22" + wire \port_rdata_valid + attribute \src "ls180.v:804.13-804.36" + wire width 16 \port_wdata_payload_data + attribute \src "ls180.v:805.12-805.33" + wire width 2 \port_wdata_payload_we + attribute \src "ls180.v:803.6-803.22" + wire \port_wdata_ready + attribute \src "ls180.v:802.6-802.22" + wire \port_wdata_valid + attribute \src "ls180.v:241.12-241.19" + wire width 5 \ram_adr + attribute \src "ls180.v:236.5-236.24" + wire \ram_bus_ram_bus_ack + attribute \src "ls180.v:230.13-230.32" + wire width 30 \ram_bus_ram_bus_adr + attribute \src "ls180.v:239.12-239.31" + wire width 2 \ram_bus_ram_bus_bte + attribute \src "ls180.v:238.12-238.31" + wire width 3 \ram_bus_ram_bus_cti + attribute \src "ls180.v:234.6-234.25" + wire \ram_bus_ram_bus_cyc + attribute \src "ls180.v:232.13-232.34" + wire width 32 \ram_bus_ram_bus_dat_r + attribute \src "ls180.v:231.13-231.34" + wire width 32 \ram_bus_ram_bus_dat_w + attribute \src "ls180.v:240.5-240.24" + wire \ram_bus_ram_bus_err + attribute \src "ls180.v:233.12-233.31" + wire width 4 \ram_bus_ram_bus_sel + attribute \src "ls180.v:235.6-235.25" + wire \ram_bus_ram_bus_stb + attribute \src "ls180.v:237.6-237.24" + wire \ram_bus_ram_bus_we + attribute \src "ls180.v:242.13-242.22" + wire width 32 \ram_dat_r + attribute \src "ls180.v:244.13-244.22" + wire width 32 \ram_dat_w + attribute \src "ls180.v:243.11-243.17" + wire width 4 \ram_we + attribute \src "ls180.v:265.11-265.20" + wire width 3 \rddata_en attribute \no_retiming "true" - attribute \src "ls180.v:2834.32-2834.59" - wire \builder_multiregimpl7_regs1 + attribute \src "ls180.v:1444.32-1444.37" + wire \regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2835.32-2835.59" - wire \builder_multiregimpl8_regs0 + attribute \src "ls180.v:1445.32-1445.37" + wire \regs1 + attribute \src "ls180.v:978.5-978.10" + wire \reset + attribute \src "ls180.v:1343.5-1343.21" + wire \rhs_array_muxed0 + attribute \src "ls180.v:1344.12-1344.28" + wire width 13 \rhs_array_muxed1 + attribute \src "ls180.v:1356.5-1356.22" + wire \rhs_array_muxed10 + attribute \src "ls180.v:1357.5-1357.22" + wire \rhs_array_muxed11 + attribute \src "ls180.v:1361.12-1361.29" + wire width 22 \rhs_array_muxed12 + attribute \src "ls180.v:1362.5-1362.22" + wire \rhs_array_muxed13 + attribute \src "ls180.v:1363.5-1363.22" + wire \rhs_array_muxed14 + attribute \src "ls180.v:1364.12-1364.29" + wire width 22 \rhs_array_muxed15 + attribute \src "ls180.v:1365.5-1365.22" + wire \rhs_array_muxed16 + attribute \src "ls180.v:1366.5-1366.22" + wire \rhs_array_muxed17 + attribute \src "ls180.v:1367.12-1367.29" + wire width 22 \rhs_array_muxed18 + attribute \src "ls180.v:1368.5-1368.22" + wire \rhs_array_muxed19 + attribute \src "ls180.v:1345.11-1345.27" + wire width 2 \rhs_array_muxed2 + attribute \src "ls180.v:1369.5-1369.22" + wire \rhs_array_muxed20 + attribute \src "ls180.v:1370.12-1370.29" + wire width 22 \rhs_array_muxed21 + attribute \src "ls180.v:1371.5-1371.22" + wire \rhs_array_muxed22 + attribute \src "ls180.v:1372.5-1372.22" + wire \rhs_array_muxed23 + attribute \src "ls180.v:1373.12-1373.29" + wire width 30 \rhs_array_muxed24 + attribute \src "ls180.v:1374.12-1374.29" + wire width 32 \rhs_array_muxed25 + attribute \src "ls180.v:1375.11-1375.28" + wire width 4 \rhs_array_muxed26 + attribute \src "ls180.v:1376.5-1376.22" + wire \rhs_array_muxed27 + attribute \src "ls180.v:1377.5-1377.22" + wire \rhs_array_muxed28 + attribute \src "ls180.v:1378.5-1378.22" + wire \rhs_array_muxed29 + attribute \src "ls180.v:1346.5-1346.21" + wire \rhs_array_muxed3 + attribute \src "ls180.v:1379.11-1379.28" + wire width 3 \rhs_array_muxed30 + attribute \src "ls180.v:1380.11-1380.28" + wire width 2 \rhs_array_muxed31 + attribute \src "ls180.v:1347.5-1347.21" + wire \rhs_array_muxed4 + attribute \src "ls180.v:1348.5-1348.21" + wire \rhs_array_muxed5 + attribute \src "ls180.v:1352.5-1352.21" + wire \rhs_array_muxed6 + attribute \src "ls180.v:1353.12-1353.28" + wire width 13 \rhs_array_muxed7 + attribute \src "ls180.v:1354.11-1354.27" + wire width 2 \rhs_array_muxed8 + attribute \src "ls180.v:1355.5-1355.21" + wire \rhs_array_muxed9 + attribute \src "ls180.v:878.5-878.13" + wire \rx_clear + attribute \src "ls180.v:962.11-962.26" + wire width 4 \rx_fifo_consume + attribute \src "ls180.v:967.6-967.21" + wire \rx_fifo_do_read + attribute \src "ls180.v:973.6-973.27" + wire \rx_fifo_fifo_in_first + attribute \src "ls180.v:974.6-974.26" + wire \rx_fifo_fifo_in_last + attribute \src "ls180.v:972.12-972.40" + wire width 8 \rx_fifo_fifo_in_payload_data + attribute \src "ls180.v:976.6-976.28" + wire \rx_fifo_fifo_out_first + attribute \src "ls180.v:977.6-977.27" + wire \rx_fifo_fifo_out_last + attribute \src "ls180.v:975.12-975.41" + wire width 8 \rx_fifo_fifo_out_payload_data + attribute \src "ls180.v:959.11-959.25" + wire width 5 \rx_fifo_level0 + attribute \src "ls180.v:971.12-971.26" + wire width 5 \rx_fifo_level1 + attribute \src "ls180.v:961.11-961.26" + wire width 4 \rx_fifo_produce + attribute \src "ls180.v:968.12-968.30" + wire width 4 \rx_fifo_rdport_adr + attribute \src "ls180.v:969.12-969.32" + wire width 10 \rx_fifo_rdport_dat_r + attribute \src "ls180.v:970.6-970.23" + wire \rx_fifo_rdport_re + attribute \src "ls180.v:951.6-951.16" + wire \rx_fifo_re + attribute \src "ls180.v:952.5-952.21" + wire \rx_fifo_readable + attribute \src "ls180.v:960.5-960.20" + wire \rx_fifo_replace + attribute \src "ls180.v:943.6-943.24" + wire \rx_fifo_sink_first + attribute \src "ls180.v:944.6-944.23" + wire \rx_fifo_sink_last + attribute \src "ls180.v:945.12-945.37" + wire width 8 \rx_fifo_sink_payload_data + attribute \src "ls180.v:942.6-942.24" + wire \rx_fifo_sink_ready + attribute \src "ls180.v:941.6-941.24" + wire \rx_fifo_sink_valid + attribute \src "ls180.v:948.6-948.26" + wire \rx_fifo_source_first + attribute \src "ls180.v:949.6-949.25" + wire \rx_fifo_source_last + attribute \src "ls180.v:950.12-950.39" + wire width 8 \rx_fifo_source_payload_data + attribute \src "ls180.v:947.6-947.26" + wire \rx_fifo_source_ready + attribute \src "ls180.v:946.6-946.26" + wire \rx_fifo_source_valid + attribute \src "ls180.v:957.12-957.32" + wire width 10 \rx_fifo_syncfifo_din + attribute \src "ls180.v:958.12-958.33" + wire width 10 \rx_fifo_syncfifo_dout + attribute \src "ls180.v:955.6-955.25" + wire \rx_fifo_syncfifo_re + attribute \src "ls180.v:956.6-956.31" + wire \rx_fifo_syncfifo_readable + attribute \src "ls180.v:953.6-953.25" + wire \rx_fifo_syncfifo_we + attribute \src "ls180.v:954.6-954.31" + wire \rx_fifo_syncfifo_writable + attribute \src "ls180.v:963.11-963.29" + wire width 4 \rx_fifo_wrport_adr + attribute \src "ls180.v:964.12-964.32" + wire width 10 \rx_fifo_wrport_dat_r + attribute \src "ls180.v:966.12-966.32" + wire width 10 \rx_fifo_wrport_dat_w + attribute \src "ls180.v:965.6-965.23" + wire \rx_fifo_wrport_we + attribute \src "ls180.v:879.5-879.19" + wire \rx_old_trigger + attribute \src "ls180.v:876.5-876.15" + wire \rx_pending + attribute \src "ls180.v:875.6-875.15" + wire \rx_status + attribute \src "ls180.v:877.6-877.16" + wire \rx_trigger + attribute \src "ls180.v:867.6-867.20" + wire \rxempty_status + attribute \src "ls180.v:868.6-868.16" + wire \rxempty_we + attribute \src "ls180.v:892.6-892.19" + wire \rxfull_status + attribute \src "ls180.v:893.6-893.15" + wire \rxfull_we + attribute \src "ls180.v:862.12-862.18" + wire width 8 \rxtx_r + attribute \src "ls180.v:861.6-861.13" + wire \rxtx_re + attribute \src "ls180.v:864.12-864.18" + wire width 8 \rxtx_w + attribute \src "ls180.v:863.6-863.13" + wire \rxtx_we + attribute \src "ls180.v:18.21-18.28" + wire width 13 output 14 \sdram_a + attribute \src "ls180.v:327.5-327.21" + wire \sdram_address_re + attribute \src "ls180.v:326.12-326.33" + wire width 13 \sdram_address_storage + attribute \src "ls180.v:27.20-27.28" + wire width 2 output 23 \sdram_ba + attribute \src "ls180.v:329.5-329.22" + wire \sdram_baddress_re + attribute \src "ls180.v:328.11-328.33" + wire width 2 \sdram_baddress_storage + attribute \src "ls180.v:425.5-425.38" + wire \sdram_bankmachine0_auto_precharge + attribute \src "ls180.v:447.11-447.58" + wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_consume + attribute \src "ls180.v:452.6-452.53" + wire \sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:457.6-457.59" + wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:458.6-458.58" + wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:456.13-456.73" + wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:455.6-455.64" + wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:461.6-461.60" + wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:462.6-462.59" + wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:460.13-460.74" + wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:459.6-459.65" + wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:444.11-444.56" + wire width 4 \sdram_bankmachine0_cmd_buffer_lookahead_level + attribute \src "ls180.v:446.11-446.58" + wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_produce + attribute \src "ls180.v:453.12-453.62" + wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:454.13-454.65" + wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:445.5-445.52" + wire \sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:428.5-428.55" + wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:429.5-429.54" + wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:431.13-431.70" + wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:430.6-430.61" + wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:427.6-427.56" + wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:426.6-426.56" + wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:434.6-434.58" + wire \sdram_bankmachine0_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:435.6-435.57" + wire \sdram_bankmachine0_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:437.13-437.72" + wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:436.6-436.63" + wire \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:433.6-433.58" + wire \sdram_bankmachine0_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:432.6-432.58" + wire \sdram_bankmachine0_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:442.13-442.66" + wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + attribute \src "ls180.v:443.13-443.67" + wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + attribute \src "ls180.v:440.6-440.58" + wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + attribute \src "ls180.v:441.6-441.64" + wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + attribute \src "ls180.v:438.6-438.58" + wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + attribute \src "ls180.v:439.6-439.64" + wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + attribute \src "ls180.v:448.11-448.61" + wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:449.13-449.65" + wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:451.13-451.65" + wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:450.6-450.55" + wire \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:465.6-465.46" + wire \sdram_bankmachine0_cmd_buffer_sink_first + attribute \src "ls180.v:466.6-466.45" + wire \sdram_bankmachine0_cmd_buffer_sink_last + attribute \src "ls180.v:468.13-468.60" + wire width 22 \sdram_bankmachine0_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:467.6-467.51" + wire \sdram_bankmachine0_cmd_buffer_sink_payload_we + attribute \src "ls180.v:464.6-464.46" + wire \sdram_bankmachine0_cmd_buffer_sink_ready + attribute \src "ls180.v:463.6-463.46" + wire \sdram_bankmachine0_cmd_buffer_sink_valid + attribute \src "ls180.v:471.5-471.47" + wire \sdram_bankmachine0_cmd_buffer_source_first + attribute \src "ls180.v:472.5-472.46" + wire \sdram_bankmachine0_cmd_buffer_source_last + attribute \src "ls180.v:474.12-474.61" + wire width 22 \sdram_bankmachine0_cmd_buffer_source_payload_addr + attribute \src "ls180.v:473.5-473.52" + wire \sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:470.6-470.48" + wire \sdram_bankmachine0_cmd_buffer_source_ready + attribute \src "ls180.v:469.5-469.47" + wire \sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:417.12-417.44" + wire width 13 \sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:418.12-418.45" + wire width 2 \sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:419.5-419.39" + wire \sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:422.5-422.42" + wire \sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:423.5-423.43" + wire \sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:424.5-424.44" + wire \sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:420.5-420.39" + wire \sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:421.5-421.38" + wire \sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:416.5-416.33" + wire \sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:415.5-415.33" + wire \sdram_bankmachine0_cmd_valid + attribute \src "ls180.v:414.5-414.35" + wire \sdram_bankmachine0_refresh_gnt + attribute \src "ls180.v:413.6-413.36" + wire \sdram_bankmachine0_refresh_req + attribute \src "ls180.v:409.13-409.40" + wire width 22 \sdram_bankmachine0_req_addr + attribute \src "ls180.v:410.6-410.33" + wire \sdram_bankmachine0_req_lock + attribute \src "ls180.v:412.5-412.39" + wire \sdram_bankmachine0_req_rdata_valid + attribute \src "ls180.v:407.6-407.34" + wire \sdram_bankmachine0_req_ready + attribute \src "ls180.v:406.6-406.34" + wire \sdram_bankmachine0_req_valid + attribute \src "ls180.v:411.5-411.39" + wire \sdram_bankmachine0_req_wdata_ready + attribute \src "ls180.v:408.6-408.31" + wire \sdram_bankmachine0_req_we + attribute \src "ls180.v:475.12-475.34" + wire width 13 \sdram_bankmachine0_row + attribute \src "ls180.v:479.5-479.33" + wire \sdram_bankmachine0_row_close + attribute \src "ls180.v:480.5-480.42" + wire \sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:477.6-477.32" + wire \sdram_bankmachine0_row_hit + attribute \src "ls180.v:478.5-478.32" + wire \sdram_bankmachine0_row_open + attribute \src "ls180.v:476.5-476.34" + wire \sdram_bankmachine0_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:2836.32-2836.59" - wire \builder_multiregimpl8_regs1 + attribute \src "ls180.v:487.32-487.64" + wire \sdram_bankmachine0_trascon_ready + attribute \src "ls180.v:486.6-486.38" + wire \sdram_bankmachine0_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:2837.32-2837.59" - wire \builder_multiregimpl9_regs0 + attribute \src "ls180.v:485.32-485.63" + wire \sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:484.6-484.37" + wire \sdram_bankmachine0_trccon_valid + attribute \src "ls180.v:483.11-483.43" + wire width 3 \sdram_bankmachine0_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:2838.32-2838.59" - wire \builder_multiregimpl9_regs1 - attribute \src "ls180.v:1883.5-1883.36" - wire \builder_new_master_rdata_valid0 - attribute \src "ls180.v:1884.5-1884.36" - wire \builder_new_master_rdata_valid1 - attribute \src "ls180.v:1885.5-1885.36" - wire \builder_new_master_rdata_valid2 - attribute \src "ls180.v:1886.5-1886.36" - wire \builder_new_master_rdata_valid3 - attribute \src "ls180.v:1882.5-1882.35" - wire \builder_new_master_wdata_ready - attribute \src "ls180.v:2709.11-2709.29" - wire width 2 \builder_next_state - attribute \src "ls180.v:1855.11-1855.39" - wire width 2 \builder_refresher_next_state - attribute \src "ls180.v:1854.11-1854.34" - wire width 2 \builder_refresher_state - attribute \src "ls180.v:2009.12-2009.27" - wire width 5 \builder_request - attribute \src "ls180.v:1868.6-1868.28" - wire \builder_roundrobin0_ce - attribute \src "ls180.v:1867.6-1867.31" - wire \builder_roundrobin0_grant - attribute \src "ls180.v:1866.6-1866.33" - wire \builder_roundrobin0_request - attribute \src "ls180.v:1871.6-1871.28" - wire \builder_roundrobin1_ce - attribute \src "ls180.v:1870.6-1870.31" - wire \builder_roundrobin1_grant - attribute \src "ls180.v:1869.6-1869.33" - wire \builder_roundrobin1_request - attribute \src "ls180.v:1874.6-1874.28" - wire \builder_roundrobin2_ce - attribute \src "ls180.v:1873.6-1873.31" - wire \builder_roundrobin2_grant - attribute \src "ls180.v:1872.6-1872.33" - wire \builder_roundrobin2_request - attribute \src "ls180.v:1877.6-1877.28" - wire \builder_roundrobin3_ce - attribute \src "ls180.v:1876.6-1876.31" - wire \builder_roundrobin3_grant - attribute \src "ls180.v:1875.6-1875.33" - wire \builder_roundrobin3_request - attribute \src "ls180.v:1964.11-1964.44" - wire width 2 \builder_sdblock2memdma_next_state - attribute \src "ls180.v:1963.11-1963.39" - wire width 2 \builder_sdblock2memdma_state - attribute \src "ls180.v:1932.5-1932.50" - wire \builder_sdcore_crcupstreaminserter_next_state - attribute \src "ls180.v:1931.5-1931.45" - wire \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:1944.11-1944.40" - wire width 3 \builder_sdcore_fsm_next_state - attribute \src "ls180.v:1943.11-1943.35" - wire width 3 \builder_sdcore_fsm_state - attribute \src "ls180.v:1968.5-1968.42" - wire \builder_sdmem2blockdma_fsm_next_state - attribute \src "ls180.v:1967.5-1967.37" - wire \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:1972.11-1972.58" - wire width 2 \builder_sdmem2blockdma_resetinserter_next_state - attribute \src "ls180.v:1971.11-1971.53" - wire width 2 \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:1920.11-1920.39" - wire width 3 \builder_sdphy_fsm_next_state - attribute \src "ls180.v:1919.11-1919.34" - wire width 3 \builder_sdphy_fsm_state - attribute \src "ls180.v:1908.11-1908.45" - wire width 3 \builder_sdphy_sdphycmdr_next_state - attribute \src "ls180.v:1907.11-1907.40" - wire width 3 \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:1904.11-1904.45" - wire width 2 \builder_sdphy_sdphycmdw_next_state - attribute \src "ls180.v:1903.11-1903.40" - wire width 2 \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:1916.5-1916.39" - wire \builder_sdphy_sdphycrcr_next_state - attribute \src "ls180.v:1915.5-1915.34" - wire \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:1924.11-1924.46" - wire width 3 \builder_sdphy_sdphydatar_next_state - attribute \src "ls180.v:1923.11-1923.41" - wire width 3 \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:1900.5-1900.39" - wire \builder_sdphy_sdphyinit_next_state - attribute \src "ls180.v:1899.5-1899.34" - wire \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:2004.5-2004.23" - wire \builder_shared_ack - attribute \src "ls180.v:1998.13-1998.31" - wire width 30 \builder_shared_adr - attribute \src "ls180.v:2007.12-2007.30" - wire width 2 \builder_shared_bte - attribute \src "ls180.v:2006.12-2006.30" - wire width 3 \builder_shared_cti - attribute \src "ls180.v:2002.6-2002.24" - wire \builder_shared_cyc - attribute \src "ls180.v:2000.12-2000.32" - wire width 32 \builder_shared_dat_r - attribute \src "ls180.v:1999.13-1999.33" - wire width 32 \builder_shared_dat_w - attribute \src "ls180.v:2008.6-2008.24" - wire \builder_shared_err - attribute \src "ls180.v:2001.12-2001.30" - wire width 4 \builder_shared_sel - attribute \src "ls180.v:2003.6-2003.24" - wire \builder_shared_stb - attribute \src "ls180.v:2005.6-2005.23" - wire \builder_shared_we - attribute \src "ls180.v:2011.12-2011.29" - wire width 13 \builder_slave_sel - attribute \src "ls180.v:2012.12-2012.31" - wire width 13 \builder_slave_sel_r - attribute \src "ls180.v:1892.11-1892.40" - wire width 2 \builder_spimaster0_next_state - attribute \src "ls180.v:1891.11-1891.35" - wire width 2 \builder_spimaster0_state - attribute \src "ls180.v:1896.11-1896.40" - wire width 2 \builder_spimaster1_next_state - attribute \src "ls180.v:1895.11-1895.35" - wire width 2 \builder_spimaster1_state - attribute \src "ls180.v:2708.11-2708.24" - wire width 2 \builder_state - attribute \src "ls180.v:2761.5-2761.32" - wire \builder_sync_f_array_muxed0 - attribute \src "ls180.v:2762.5-2762.32" - wire \builder_sync_f_array_muxed1 - attribute \src "ls180.v:2754.11-2754.40" - wire width 2 \builder_sync_rhs_array_muxed0 - attribute \src "ls180.v:2755.12-2755.41" - wire width 13 \builder_sync_rhs_array_muxed1 - attribute \src "ls180.v:2756.5-2756.34" - wire \builder_sync_rhs_array_muxed2 - attribute \src "ls180.v:2757.5-2757.34" - wire \builder_sync_rhs_array_muxed3 - attribute \src "ls180.v:2758.5-2758.34" - wire \builder_sync_rhs_array_muxed4 - attribute \src "ls180.v:2759.5-2759.34" - wire \builder_sync_rhs_array_muxed5 - attribute \src "ls180.v:2760.5-2760.34" - wire \builder_sync_rhs_array_muxed6 - attribute \src "ls180.v:2014.6-2014.18" - wire \builder_wait - attribute \src "ls180.v:16.19-16.23" - wire width 3 input 12 \eint - attribute \src "ls180.v:182.12-182.18" - wire width 3 \eint_1 - attribute \src "ls180.v:5.21-5.27" - wire width 16 output 1 \gpio_i - attribute \src "ls180.v:6.20-6.26" - wire width 16 output 2 \gpio_o - attribute \src "ls180.v:7.20-7.27" - wire width 16 output 3 \gpio_oe - attribute \src "ls180.v:8.14-8.21" - wire output 4 \i2c_scl - attribute \src "ls180.v:9.14-9.23" - wire output 5 \i2c_sda_i - attribute \src "ls180.v:10.14-10.23" - wire output 6 \i2c_sda_o - attribute \src "ls180.v:11.14-11.24" - wire output 7 \i2c_sda_oe - attribute \src "ls180.v:49.13-49.21" - wire input 45 \jtag_tck - attribute \src "ls180.v:50.13-50.21" - wire input 46 \jtag_tdi - attribute \src "ls180.v:51.14-51.22" - wire output 47 \jtag_tdo - attribute \src "ls180.v:48.13-48.21" - wire input 44 \jtag_tms - attribute \src "ls180.v:940.6-940.18" - wire \main_ack_cmd - attribute \src "ls180.v:942.6-942.20" - wire \main_ack_rdata - attribute \src "ls180.v:941.6-941.20" - wire \main_ack_wdata - attribute \src "ls180.v:938.5-938.22" - wire \main_cmd_consumed - attribute \src "ls180.v:321.5-321.28" - wire \main_converter0_counter - attribute \src "ls180.v:1844.5-1844.50" - wire \main_converter0_counter_converter0_next_value - attribute \src "ls180.v:1845.5-1845.53" - wire \main_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:323.12-323.33" - wire width 64 \main_converter0_dat_r - attribute \src "ls180.v:322.6-322.27" - wire \main_converter0_reset - attribute \src "ls180.v:320.5-320.25" - wire \main_converter0_skip - attribute \src "ls180.v:336.5-336.28" - wire \main_converter1_counter - attribute \src "ls180.v:1848.5-1848.50" - wire \main_converter1_counter_converter1_next_value - attribute \src "ls180.v:1849.5-1849.53" - wire \main_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:338.12-338.33" - wire width 64 \main_converter1_dat_r - attribute \src "ls180.v:337.6-337.27" - wire \main_converter1_reset - attribute \src "ls180.v:335.5-335.25" - wire \main_converter1_skip - attribute \src "ls180.v:935.5-935.27" - wire \main_converter_counter - attribute \src "ls180.v:1889.5-1889.48" - wire \main_converter_counter_converter_next_value - attribute \src "ls180.v:1890.5-1890.51" - wire \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:937.12-937.32" - wire width 32 \main_converter_dat_r - attribute \src "ls180.v:936.6-936.26" - wire \main_converter_reset - attribute \src "ls180.v:934.5-934.24" - wire \main_converter_skip - attribute \src "ls180.v:352.6-352.23" - wire \main_dfi_p0_act_n - attribute \src "ls180.v:343.13-343.32" - wire width 13 \main_dfi_p0_address - attribute \src "ls180.v:344.12-344.28" - wire width 2 \main_dfi_p0_bank - attribute \src "ls180.v:345.6-345.23" - wire \main_dfi_p0_cas_n - attribute \src "ls180.v:349.6-349.21" - wire \main_dfi_p0_cke - attribute \src "ls180.v:346.6-346.22" - wire \main_dfi_p0_cs_n - attribute \src "ls180.v:350.6-350.21" - wire \main_dfi_p0_odt - attribute \src "ls180.v:347.6-347.23" - wire \main_dfi_p0_ras_n - attribute \src "ls180.v:357.12-357.30" - wire width 16 \main_dfi_p0_rddata - attribute \src "ls180.v:356.6-356.27" - wire \main_dfi_p0_rddata_en - attribute \src "ls180.v:358.5-358.29" - wire \main_dfi_p0_rddata_valid - attribute \src "ls180.v:351.6-351.25" - wire \main_dfi_p0_reset_n - attribute \src "ls180.v:348.6-348.22" - wire \main_dfi_p0_we_n - attribute \src "ls180.v:353.13-353.31" - wire width 16 \main_dfi_p0_wrdata - attribute \src "ls180.v:354.6-354.27" - wire \main_dfi_p0_wrdata_en - attribute \src "ls180.v:355.12-355.35" - wire width 2 \main_dfi_p0_wrdata_mask - attribute \src "ls180.v:1175.12-1175.22" - wire width 24 \main_dummy - attribute \src "ls180.v:1085.12-1085.45" - wire width 16 \main_gpiotristateasic0_oe_storage - attribute \src "ls180.v:1087.12-1087.46" - wire width 16 \main_gpiotristateasic0_out_storage - attribute \src "ls180.v:1088.13-1088.42" - wire width 16 \main_gpiotristateasic0_pads_i - attribute \src "ls180.v:1089.13-1089.42" - wire width 16 \main_gpiotristateasic0_pads_o - attribute \src "ls180.v:1090.13-1090.43" - wire width 16 \main_gpiotristateasic0_pads_oe - attribute \src "ls180.v:1086.12-1086.41" - wire width 16 \main_gpiotristateasic0_status - attribute \src "ls180.v:1092.5-1092.33" - wire \main_gpiotristateasic1_oe_re - attribute \src "ls180.v:1091.12-1091.45" - wire width 16 \main_gpiotristateasic1_oe_storage - attribute \src "ls180.v:1096.5-1096.34" - wire \main_gpiotristateasic1_out_re - attribute \src "ls180.v:1095.12-1095.46" - wire width 16 \main_gpiotristateasic1_out_storage - attribute \src "ls180.v:1097.13-1097.42" - wire width 16 \main_gpiotristateasic1_pads_i - attribute \src "ls180.v:1098.13-1098.42" - wire width 16 \main_gpiotristateasic1_pads_o - attribute \src "ls180.v:1099.13-1099.43" - wire width 16 \main_gpiotristateasic1_pads_oe - attribute \src "ls180.v:1093.12-1093.41" - wire width 16 \main_gpiotristateasic1_status - attribute \src "ls180.v:1094.6-1094.31" - wire \main_gpiotristateasic1_we - attribute \src "ls180.v:1197.6-1197.17" - wire \main_i2c_oe - attribute \src "ls180.v:1200.5-1200.16" - wire \main_i2c_re - attribute \src "ls180.v:1196.6-1196.18" - wire \main_i2c_scl - attribute \src "ls180.v:1198.6-1198.19" - wire \main_i2c_sda0 - attribute \src "ls180.v:1201.6-1201.19" - wire \main_i2c_sda1 - attribute \src "ls180.v:1202.6-1202.21" - wire \main_i2c_status - attribute \src "ls180.v:1199.11-1199.27" - wire width 3 \main_i2c_storage - attribute \src "ls180.v:1203.6-1203.17" - wire \main_i2c_we - attribute \src "ls180.v:342.5-342.17" - wire \main_int_rst - attribute \src "ls180.v:1663.6-1663.29" - wire \main_interface0_bus_ack - attribute \src "ls180.v:1657.13-1657.36" - wire width 32 \main_interface0_bus_adr - attribute \src "ls180.v:1666.11-1666.34" - wire width 2 \main_interface0_bus_bte - attribute \src "ls180.v:1665.11-1665.34" - wire width 3 \main_interface0_bus_cti - attribute \src "ls180.v:1661.6-1661.29" - wire \main_interface0_bus_cyc - attribute \src "ls180.v:1659.13-1659.38" - wire width 64 \main_interface0_bus_dat_r - attribute \src "ls180.v:1658.13-1658.38" - wire width 64 \main_interface0_bus_dat_w - attribute \src "ls180.v:1667.6-1667.29" - wire \main_interface0_bus_err - attribute \src "ls180.v:1660.12-1660.35" - wire width 8 \main_interface0_bus_sel - attribute \src "ls180.v:1662.6-1662.29" - wire \main_interface0_bus_stb - attribute \src "ls180.v:1664.6-1664.28" - wire \main_interface0_bus_we - attribute \src "ls180.v:315.5-315.44" - wire \main_interface0_converted_interface_ack - attribute \src "ls180.v:309.13-309.52" - wire width 30 \main_interface0_converted_interface_adr - attribute \src "ls180.v:318.12-318.51" - wire width 2 \main_interface0_converted_interface_bte - attribute \src "ls180.v:317.12-317.51" - wire width 3 \main_interface0_converted_interface_cti - attribute \src "ls180.v:313.6-313.45" - wire \main_interface0_converted_interface_cyc - attribute \src "ls180.v:311.13-311.54" - wire width 64 \main_interface0_converted_interface_dat_r - attribute \src "ls180.v:310.13-310.54" - wire width 64 \main_interface0_converted_interface_dat_w - attribute \src "ls180.v:319.5-319.44" - wire \main_interface0_converted_interface_err - attribute \src "ls180.v:312.12-312.51" - wire width 8 \main_interface0_converted_interface_sel - attribute \src "ls180.v:314.6-314.45" - wire \main_interface0_converted_interface_stb - attribute \src "ls180.v:316.6-316.44" - wire \main_interface0_converted_interface_we - attribute \src "ls180.v:255.5-255.32" - wire \main_interface0_ram_bus_ack - attribute \src "ls180.v:249.13-249.40" - wire width 30 \main_interface0_ram_bus_adr - attribute \src "ls180.v:258.12-258.39" - wire width 2 \main_interface0_ram_bus_bte - attribute \src "ls180.v:257.12-257.39" - wire width 3 \main_interface0_ram_bus_cti - attribute \src "ls180.v:253.6-253.33" - wire \main_interface0_ram_bus_cyc - attribute \src "ls180.v:251.13-251.42" - wire width 64 \main_interface0_ram_bus_dat_r - attribute \src "ls180.v:250.13-250.42" - wire width 64 \main_interface0_ram_bus_dat_w - attribute \src "ls180.v:259.5-259.32" - wire \main_interface0_ram_bus_err - attribute \src "ls180.v:252.12-252.39" - wire width 8 \main_interface0_ram_bus_sel - attribute \src "ls180.v:254.6-254.33" - wire \main_interface0_ram_bus_stb - attribute \src "ls180.v:256.6-256.32" - wire \main_interface0_ram_bus_we - attribute \src "ls180.v:1754.6-1754.29" - wire \main_interface1_bus_ack - attribute \src "ls180.v:1748.12-1748.35" - wire width 32 \main_interface1_bus_adr - attribute \src "ls180.v:1757.11-1757.34" - wire width 2 \main_interface1_bus_bte - attribute \src "ls180.v:1756.11-1756.34" - wire width 3 \main_interface1_bus_cti - attribute \src "ls180.v:1752.5-1752.28" - wire \main_interface1_bus_cyc - attribute \src "ls180.v:1750.13-1750.38" - wire width 64 \main_interface1_bus_dat_r - attribute \src "ls180.v:1749.12-1749.37" - wire width 64 \main_interface1_bus_dat_w - attribute \src "ls180.v:1758.6-1758.29" - wire \main_interface1_bus_err - attribute \src "ls180.v:1751.11-1751.34" - wire width 8 \main_interface1_bus_sel - attribute \src "ls180.v:1753.5-1753.28" - wire \main_interface1_bus_stb - attribute \src "ls180.v:1755.5-1755.27" - wire \main_interface1_bus_we - attribute \src "ls180.v:330.5-330.44" - wire \main_interface1_converted_interface_ack - attribute \src "ls180.v:324.13-324.52" - wire width 30 \main_interface1_converted_interface_adr - attribute \src "ls180.v:333.12-333.51" - wire width 2 \main_interface1_converted_interface_bte - attribute \src "ls180.v:332.12-332.51" - wire width 3 \main_interface1_converted_interface_cti - attribute \src "ls180.v:328.6-328.45" - wire \main_interface1_converted_interface_cyc - attribute \src "ls180.v:326.13-326.54" - wire width 64 \main_interface1_converted_interface_dat_r - attribute \src "ls180.v:325.13-325.54" - wire width 64 \main_interface1_converted_interface_dat_w - attribute \src "ls180.v:334.5-334.44" - wire \main_interface1_converted_interface_err - attribute \src "ls180.v:327.12-327.51" - wire width 8 \main_interface1_converted_interface_sel - attribute \src "ls180.v:329.6-329.45" - wire \main_interface1_converted_interface_stb - attribute \src "ls180.v:331.6-331.44" - wire \main_interface1_converted_interface_we - attribute \src "ls180.v:270.5-270.32" - wire \main_interface1_ram_bus_ack - attribute \src "ls180.v:264.13-264.40" - wire width 30 \main_interface1_ram_bus_adr - attribute \src "ls180.v:273.12-273.39" - wire width 2 \main_interface1_ram_bus_bte - attribute \src "ls180.v:272.12-272.39" - wire width 3 \main_interface1_ram_bus_cti - attribute \src "ls180.v:268.6-268.33" - wire \main_interface1_ram_bus_cyc - attribute \src "ls180.v:266.13-266.42" - wire width 64 \main_interface1_ram_bus_dat_r - attribute \src "ls180.v:265.13-265.42" - wire width 64 \main_interface1_ram_bus_dat_w - attribute \src "ls180.v:274.5-274.32" - wire \main_interface1_ram_bus_err - attribute \src "ls180.v:267.12-267.39" - wire width 8 \main_interface1_ram_bus_sel - attribute \src "ls180.v:269.6-269.33" - wire \main_interface1_ram_bus_stb - attribute \src "ls180.v:271.6-271.32" - wire \main_interface1_ram_bus_we - attribute \src "ls180.v:285.5-285.32" - wire \main_interface2_ram_bus_ack - attribute \src "ls180.v:279.13-279.40" - wire width 30 \main_interface2_ram_bus_adr - attribute \src "ls180.v:288.12-288.39" - wire width 2 \main_interface2_ram_bus_bte - attribute \src "ls180.v:287.12-287.39" - wire width 3 \main_interface2_ram_bus_cti - attribute \src "ls180.v:283.6-283.33" - wire \main_interface2_ram_bus_cyc - attribute \src "ls180.v:281.13-281.42" - wire width 64 \main_interface2_ram_bus_dat_r - attribute \src "ls180.v:280.13-280.42" - wire width 64 \main_interface2_ram_bus_dat_w - attribute \src "ls180.v:289.5-289.32" - wire \main_interface2_ram_bus_err - attribute \src "ls180.v:282.12-282.39" - wire width 8 \main_interface2_ram_bus_sel - attribute \src "ls180.v:284.6-284.33" - wire \main_interface2_ram_bus_stb - attribute \src "ls180.v:286.6-286.32" - wire \main_interface2_ram_bus_we - attribute \src "ls180.v:300.5-300.32" - wire \main_interface3_ram_bus_ack - attribute \src "ls180.v:294.13-294.40" - wire width 30 \main_interface3_ram_bus_adr - attribute \src "ls180.v:303.12-303.39" - wire width 2 \main_interface3_ram_bus_bte - attribute \src "ls180.v:302.12-302.39" - wire width 3 \main_interface3_ram_bus_cti - attribute \src "ls180.v:298.6-298.33" - wire \main_interface3_ram_bus_cyc - attribute \src "ls180.v:296.13-296.42" - wire width 64 \main_interface3_ram_bus_dat_r - attribute \src "ls180.v:295.13-295.42" - wire width 64 \main_interface3_ram_bus_dat_w - attribute \src "ls180.v:304.5-304.32" - wire \main_interface3_ram_bus_err - attribute \src "ls180.v:297.12-297.39" - wire width 8 \main_interface3_ram_bus_sel - attribute \src "ls180.v:299.6-299.33" - wire \main_interface3_ram_bus_stb - attribute \src "ls180.v:301.6-301.32" - wire \main_interface3_ram_bus_we - attribute \src "ls180.v:218.12-218.32" - wire width 6 \main_libresocsim_adr - attribute \src "ls180.v:62.6-62.32" - wire \main_libresocsim_bus_error - attribute \src "ls180.v:63.12-63.39" - wire width 32 \main_libresocsim_bus_errors - attribute \src "ls180.v:59.13-59.47" - wire width 32 \main_libresocsim_bus_errors_status - attribute \src "ls180.v:60.6-60.36" - wire \main_libresocsim_bus_errors_we - attribute \src "ls180.v:219.13-219.35" - wire width 64 \main_libresocsim_dat_r - attribute \src "ls180.v:221.13-221.35" - wire width 64 \main_libresocsim_dat_w - attribute \src "ls180.v:227.5-227.27" - wire \main_libresocsim_en_re - attribute \src "ls180.v:226.5-226.32" - wire \main_libresocsim_en_storage - attribute \src "ls180.v:243.6-243.45" - wire \main_libresocsim_eventmanager_pending_r - attribute \src "ls180.v:242.6-242.46" - wire \main_libresocsim_eventmanager_pending_re - attribute \src "ls180.v:245.6-245.45" - wire \main_libresocsim_eventmanager_pending_w - attribute \src "ls180.v:244.6-244.46" - wire \main_libresocsim_eventmanager_pending_we - attribute \src "ls180.v:247.5-247.37" - wire \main_libresocsim_eventmanager_re - attribute \src "ls180.v:239.6-239.44" - wire \main_libresocsim_eventmanager_status_r - attribute \src "ls180.v:238.6-238.45" - wire \main_libresocsim_eventmanager_status_re - attribute \src "ls180.v:241.6-241.44" - wire \main_libresocsim_eventmanager_status_w - attribute \src "ls180.v:240.6-240.45" - wire \main_libresocsim_eventmanager_status_we - attribute \src "ls180.v:246.5-246.42" - wire \main_libresocsim_eventmanager_storage - attribute \src "ls180.v:232.6-232.26" - wire \main_libresocsim_irq - attribute \src "ls180.v:165.6-165.32" - wire \main_libresocsim_libresoc0 - attribute \src "ls180.v:166.6-166.32" - wire \main_libresocsim_libresoc1 - attribute \src "ls180.v:167.13-167.39" - wire width 64 \main_libresocsim_libresoc2 - attribute \src "ls180.v:169.12-169.45" - wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:171.12-171.66" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:172.13-172.67" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:173.13-173.68" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:174.6-174.61" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:175.5-175.62" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:176.6-176.63" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:177.6-177.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:200.6-200.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:201.5-201.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:202.6-202.66" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:203.6-203.67" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:204.11-204.72" - wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i - attribute \src "ls180.v:205.12-205.73" - wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o - attribute \src "ls180.v:206.6-206.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - attribute \src "ls180.v:188.13-188.68" - wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:197.12-197.68" - wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:194.6-194.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:196.6-196.63" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:195.6-195.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:198.12-198.68" - wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:189.12-189.70" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:190.13-190.71" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:191.6-191.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:193.6-193.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:192.6-192.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:184.6-184.67" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:186.6-186.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:187.6-187.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:185.6-185.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:178.6-178.67" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:180.6-180.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:181.6-181.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:179.6-179.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi - attribute \src "ls180.v:72.6-72.40" - wire \main_libresocsim_libresoc_dbus_ack - attribute \src "ls180.v:66.13-66.47" - wire width 29 \main_libresocsim_libresoc_dbus_adr - attribute \src "ls180.v:75.11-75.45" - wire width 2 \main_libresocsim_libresoc_dbus_bte - attribute \src "ls180.v:74.11-74.45" - wire width 3 \main_libresocsim_libresoc_dbus_cti - attribute \src "ls180.v:70.6-70.40" - wire \main_libresocsim_libresoc_dbus_cyc - attribute \src "ls180.v:68.13-68.49" - wire width 64 \main_libresocsim_libresoc_dbus_dat_r - attribute \src "ls180.v:67.13-67.49" - wire width 64 \main_libresocsim_libresoc_dbus_dat_w - attribute \src "ls180.v:76.6-76.40" - wire \main_libresocsim_libresoc_dbus_err - attribute \src "ls180.v:69.12-69.46" - wire width 8 \main_libresocsim_libresoc_dbus_sel - attribute \src "ls180.v:71.6-71.40" - wire \main_libresocsim_libresoc_dbus_stb - attribute \src "ls180.v:73.6-73.39" - wire \main_libresocsim_libresoc_dbus_we - attribute \src "ls180.v:83.6-83.40" - wire \main_libresocsim_libresoc_ibus_ack - attribute \src "ls180.v:77.13-77.47" - wire width 29 \main_libresocsim_libresoc_ibus_adr - attribute \src "ls180.v:86.11-86.45" - wire width 2 \main_libresocsim_libresoc_ibus_bte - attribute \src "ls180.v:85.11-85.45" - wire width 3 \main_libresocsim_libresoc_ibus_cti - attribute \src "ls180.v:81.6-81.40" - wire \main_libresocsim_libresoc_ibus_cyc - attribute \src "ls180.v:79.13-79.49" - wire width 64 \main_libresocsim_libresoc_ibus_dat_r - attribute \src "ls180.v:78.13-78.49" - wire width 64 \main_libresocsim_libresoc_ibus_dat_w - attribute \src "ls180.v:87.6-87.40" - wire \main_libresocsim_libresoc_ibus_err - attribute \src "ls180.v:80.12-80.46" - wire width 8 \main_libresocsim_libresoc_ibus_sel - attribute \src "ls180.v:82.6-82.40" - wire \main_libresocsim_libresoc_ibus_stb - attribute \src "ls180.v:84.6-84.39" - wire \main_libresocsim_libresoc_ibus_we - attribute \src "ls180.v:123.6-123.46" - wire \main_libresocsim_libresoc_interface0_ack - attribute \src "ls180.v:117.13-117.53" - wire width 29 \main_libresocsim_libresoc_interface0_adr - attribute \src "ls180.v:126.12-126.52" - wire width 2 \main_libresocsim_libresoc_interface0_bte - attribute \src "ls180.v:125.12-125.52" - wire width 3 \main_libresocsim_libresoc_interface0_cti - attribute \src "ls180.v:121.6-121.46" - wire \main_libresocsim_libresoc_interface0_cyc - attribute \src "ls180.v:119.13-119.55" - wire width 64 \main_libresocsim_libresoc_interface0_dat_r - attribute \src "ls180.v:118.13-118.55" - wire width 64 \main_libresocsim_libresoc_interface0_dat_w - attribute \src "ls180.v:127.6-127.46" - wire \main_libresocsim_libresoc_interface0_err - attribute \src "ls180.v:120.12-120.52" - wire width 8 \main_libresocsim_libresoc_interface0_sel - attribute \src "ls180.v:122.6-122.46" - wire \main_libresocsim_libresoc_interface0_stb - attribute \src "ls180.v:124.6-124.45" - wire \main_libresocsim_libresoc_interface0_we - attribute \src "ls180.v:134.6-134.46" - wire \main_libresocsim_libresoc_interface1_ack - attribute \src "ls180.v:128.13-128.53" - wire width 29 \main_libresocsim_libresoc_interface1_adr - attribute \src "ls180.v:137.12-137.52" - wire width 2 \main_libresocsim_libresoc_interface1_bte - attribute \src "ls180.v:136.12-136.52" - wire width 3 \main_libresocsim_libresoc_interface1_cti - attribute \src "ls180.v:132.6-132.46" - wire \main_libresocsim_libresoc_interface1_cyc - attribute \src "ls180.v:130.13-130.55" - wire width 64 \main_libresocsim_libresoc_interface1_dat_r - attribute \src "ls180.v:129.13-129.55" - wire width 64 \main_libresocsim_libresoc_interface1_dat_w - attribute \src "ls180.v:138.6-138.46" - wire \main_libresocsim_libresoc_interface1_err - attribute \src "ls180.v:131.12-131.52" - wire width 8 \main_libresocsim_libresoc_interface1_sel - attribute \src "ls180.v:133.6-133.46" - wire \main_libresocsim_libresoc_interface1_stb - attribute \src "ls180.v:135.6-135.45" - wire \main_libresocsim_libresoc_interface1_we - attribute \src "ls180.v:145.6-145.46" - wire \main_libresocsim_libresoc_interface2_ack - attribute \src "ls180.v:139.13-139.53" - wire width 29 \main_libresocsim_libresoc_interface2_adr - attribute \src "ls180.v:148.12-148.52" - wire width 2 \main_libresocsim_libresoc_interface2_bte - attribute \src "ls180.v:147.12-147.52" - wire width 3 \main_libresocsim_libresoc_interface2_cti - attribute \src "ls180.v:143.6-143.46" - wire \main_libresocsim_libresoc_interface2_cyc - attribute \src "ls180.v:141.13-141.55" - wire width 64 \main_libresocsim_libresoc_interface2_dat_r - attribute \src "ls180.v:140.13-140.55" - wire width 64 \main_libresocsim_libresoc_interface2_dat_w - attribute \src "ls180.v:149.6-149.46" - wire \main_libresocsim_libresoc_interface2_err - attribute \src "ls180.v:142.12-142.52" - wire width 8 \main_libresocsim_libresoc_interface2_sel - attribute \src "ls180.v:144.6-144.46" - wire \main_libresocsim_libresoc_interface2_stb - attribute \src "ls180.v:146.6-146.45" - wire \main_libresocsim_libresoc_interface2_we - attribute \src "ls180.v:156.6-156.46" - wire \main_libresocsim_libresoc_interface3_ack - attribute \src "ls180.v:150.13-150.53" - wire width 29 \main_libresocsim_libresoc_interface3_adr - attribute \src "ls180.v:159.12-159.52" - wire width 2 \main_libresocsim_libresoc_interface3_bte - attribute \src "ls180.v:158.12-158.52" - wire width 3 \main_libresocsim_libresoc_interface3_cti - attribute \src "ls180.v:154.6-154.46" - wire \main_libresocsim_libresoc_interface3_cyc - attribute \src "ls180.v:152.13-152.55" - wire width 64 \main_libresocsim_libresoc_interface3_dat_r - attribute \src "ls180.v:151.13-151.55" - wire width 64 \main_libresocsim_libresoc_interface3_dat_w - attribute \src "ls180.v:160.6-160.46" - wire \main_libresocsim_libresoc_interface3_err - attribute \src "ls180.v:153.12-153.52" - wire width 8 \main_libresocsim_libresoc_interface3_sel - attribute \src "ls180.v:155.6-155.46" - wire \main_libresocsim_libresoc_interface3_stb - attribute \src "ls180.v:157.6-157.45" - wire \main_libresocsim_libresoc_interface3_we - attribute \src "ls180.v:65.12-65.47" - wire width 16 \main_libresocsim_libresoc_interrupt - attribute \src "ls180.v:161.6-161.40" - wire \main_libresocsim_libresoc_jtag_tck - attribute \src "ls180.v:163.6-163.40" - wire \main_libresocsim_libresoc_jtag_tdi - attribute \src "ls180.v:164.6-164.40" - wire \main_libresocsim_libresoc_jtag_tdo - attribute \src "ls180.v:162.6-162.40" - wire \main_libresocsim_libresoc_jtag_tms - attribute \src "ls180.v:112.6-112.43" - wire \main_libresocsim_libresoc_jtag_wb_ack - attribute \src "ls180.v:106.13-106.50" - wire width 29 \main_libresocsim_libresoc_jtag_wb_adr - attribute \src "ls180.v:115.11-115.48" - wire width 2 \main_libresocsim_libresoc_jtag_wb_bte - attribute \src "ls180.v:114.11-114.48" - wire width 3 \main_libresocsim_libresoc_jtag_wb_cti - attribute \src "ls180.v:110.6-110.43" - wire \main_libresocsim_libresoc_jtag_wb_cyc - attribute \src "ls180.v:108.13-108.52" - wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r - attribute \src "ls180.v:107.13-107.52" - wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w - attribute \src "ls180.v:116.6-116.43" - wire \main_libresocsim_libresoc_jtag_wb_err - attribute \src "ls180.v:109.12-109.49" - wire width 8 \main_libresocsim_libresoc_jtag_wb_sel - attribute \src "ls180.v:111.6-111.43" - wire \main_libresocsim_libresoc_jtag_wb_stb - attribute \src "ls180.v:113.6-113.42" - wire \main_libresocsim_libresoc_jtag_wb_we - attribute \src "ls180.v:168.6-168.40" - wire \main_libresocsim_libresoc_pll_18_o - attribute \src "ls180.v:170.6-170.41" - wire \main_libresocsim_libresoc_pll_lck_o - attribute \src "ls180.v:64.6-64.37" - wire \main_libresocsim_libresoc_reset - attribute \src "ls180.v:94.6-94.44" - wire \main_libresocsim_libresoc_xics_icp_ack - attribute \src "ls180.v:88.12-88.50" - wire width 30 \main_libresocsim_libresoc_xics_icp_adr - attribute \src "ls180.v:92.5-92.43" - wire \main_libresocsim_libresoc_xics_icp_cyc - attribute \src "ls180.v:90.13-90.53" - wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r - attribute \src "ls180.v:89.12-89.52" - wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w - attribute \src "ls180.v:96.6-96.44" - wire \main_libresocsim_libresoc_xics_icp_err - attribute \src "ls180.v:91.11-91.49" - wire width 4 \main_libresocsim_libresoc_xics_icp_sel - attribute \src "ls180.v:93.5-93.43" - wire \main_libresocsim_libresoc_xics_icp_stb - attribute \src "ls180.v:95.5-95.42" - wire \main_libresocsim_libresoc_xics_icp_we - attribute \src "ls180.v:103.6-103.44" - wire \main_libresocsim_libresoc_xics_ics_ack - attribute \src "ls180.v:97.12-97.50" - wire width 30 \main_libresocsim_libresoc_xics_ics_adr - attribute \src "ls180.v:101.5-101.43" - wire \main_libresocsim_libresoc_xics_ics_cyc - attribute \src "ls180.v:99.13-99.53" - wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r - attribute \src "ls180.v:98.12-98.52" - wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w - attribute \src "ls180.v:105.6-105.44" - wire \main_libresocsim_libresoc_xics_ics_err - attribute \src "ls180.v:100.11-100.49" - wire width 4 \main_libresocsim_libresoc_xics_ics_sel - attribute \src "ls180.v:102.5-102.43" - wire \main_libresocsim_libresoc_xics_ics_stb - attribute \src "ls180.v:104.5-104.42" - wire \main_libresocsim_libresoc_xics_ics_we - attribute \src "ls180.v:223.5-223.29" - wire \main_libresocsim_load_re - attribute \src "ls180.v:222.12-222.41" - wire width 32 \main_libresocsim_load_storage - attribute \src "ls180.v:213.5-213.33" - wire \main_libresocsim_ram_bus_ack - attribute \src "ls180.v:207.13-207.41" - wire width 30 \main_libresocsim_ram_bus_adr - attribute \src "ls180.v:216.12-216.40" - wire width 2 \main_libresocsim_ram_bus_bte - attribute \src "ls180.v:215.12-215.40" - wire width 3 \main_libresocsim_ram_bus_cti - attribute \src "ls180.v:211.6-211.34" - wire \main_libresocsim_ram_bus_cyc - attribute \src "ls180.v:209.13-209.43" - wire width 64 \main_libresocsim_ram_bus_dat_r - attribute \src "ls180.v:208.13-208.43" - wire width 64 \main_libresocsim_ram_bus_dat_w - attribute \src "ls180.v:217.5-217.33" - wire \main_libresocsim_ram_bus_err - attribute \src "ls180.v:210.12-210.40" - wire width 8 \main_libresocsim_ram_bus_sel - attribute \src "ls180.v:212.6-212.34" - wire \main_libresocsim_ram_bus_stb - attribute \src "ls180.v:214.6-214.33" - wire \main_libresocsim_ram_bus_we - attribute \src "ls180.v:225.5-225.31" - wire \main_libresocsim_reload_re - attribute \src "ls180.v:224.12-224.43" - wire width 32 \main_libresocsim_reload_storage - attribute \src "ls180.v:61.6-61.28" - wire \main_libresocsim_reset - attribute \src "ls180.v:56.5-56.30" - wire \main_libresocsim_reset_re - attribute \src "ls180.v:55.5-55.35" - wire \main_libresocsim_reset_storage - attribute \src "ls180.v:58.5-58.32" - wire \main_libresocsim_scratch_re - attribute \src "ls180.v:57.12-57.44" - wire width 32 \main_libresocsim_scratch_storage - attribute \src "ls180.v:229.5-229.37" - wire \main_libresocsim_update_value_re - attribute \src "ls180.v:228.5-228.42" - wire \main_libresocsim_update_value_storage - attribute \src "ls180.v:248.12-248.34" - wire width 32 \main_libresocsim_value - attribute \src "ls180.v:230.12-230.41" - wire width 32 \main_libresocsim_value_status - attribute \src "ls180.v:231.6-231.31" - wire \main_libresocsim_value_we - attribute \src "ls180.v:220.11-220.30" - wire width 8 \main_libresocsim_we - attribute \src "ls180.v:236.5-236.32" - wire \main_libresocsim_zero_clear - attribute \src "ls180.v:237.5-237.38" - wire \main_libresocsim_zero_old_trigger - attribute \src "ls180.v:234.5-234.34" - wire \main_libresocsim_zero_pending - attribute \src "ls180.v:233.6-233.34" - wire \main_libresocsim_zero_status - attribute \src "ls180.v:235.6-235.35" - wire \main_libresocsim_zero_trigger - attribute \src "ls180.v:932.6-932.26" - wire \main_litedram_wb_ack - attribute \src "ls180.v:926.12-926.32" - wire width 30 \main_litedram_wb_adr - attribute \src "ls180.v:930.5-930.25" - wire \main_litedram_wb_cyc - attribute \src "ls180.v:928.13-928.35" - wire width 16 \main_litedram_wb_dat_r - attribute \src "ls180.v:927.12-927.34" - wire width 16 \main_litedram_wb_dat_w - attribute \src "ls180.v:929.11-929.31" - wire width 2 \main_litedram_wb_sel - attribute \src "ls180.v:931.5-931.25" - wire \main_litedram_wb_stb - attribute \src "ls180.v:933.5-933.24" - wire \main_litedram_wb_we - attribute \src "ls180.v:1174.13-1174.20" - wire width 24 \main_nc - attribute \src "ls180.v:893.6-893.24" - wire \main_port_cmd_last - attribute \src "ls180.v:895.13-895.39" - wire width 24 \main_port_cmd_payload_addr - attribute \src "ls180.v:894.6-894.30" - wire \main_port_cmd_payload_we - attribute \src "ls180.v:892.6-892.25" - wire \main_port_cmd_ready - attribute \src "ls180.v:891.6-891.25" - wire \main_port_cmd_valid - attribute \src "ls180.v:890.6-890.21" - wire \main_port_flush - attribute \src "ls180.v:902.13-902.41" - wire width 16 \main_port_rdata_payload_data - attribute \src "ls180.v:901.6-901.27" - wire \main_port_rdata_ready - attribute \src "ls180.v:900.6-900.27" - wire \main_port_rdata_valid - attribute \src "ls180.v:898.13-898.41" - wire width 16 \main_port_wdata_payload_data - attribute \src "ls180.v:899.12-899.38" - wire width 2 \main_port_wdata_payload_we - attribute \src "ls180.v:897.6-897.27" - wire \main_port_wdata_ready - attribute \src "ls180.v:896.6-896.27" - wire \main_port_wdata_valid - attribute \src "ls180.v:1179.12-1179.29" - wire width 32 \main_pwm0_counter - attribute \src "ls180.v:1176.6-1176.22" - wire \main_pwm0_enable - attribute \src "ls180.v:1181.5-1181.24" - wire \main_pwm0_enable_re - attribute \src "ls180.v:1180.5-1180.29" - wire \main_pwm0_enable_storage - attribute \src "ls180.v:1178.13-1178.29" - wire width 32 \main_pwm0_period - attribute \src "ls180.v:1185.5-1185.24" - wire \main_pwm0_period_re - attribute \src "ls180.v:1184.12-1184.36" - wire width 32 \main_pwm0_period_storage - attribute \src "ls180.v:1177.13-1177.28" - wire width 32 \main_pwm0_width - attribute \src "ls180.v:1183.5-1183.23" - wire \main_pwm0_width_re - attribute \src "ls180.v:1182.12-1182.35" - wire width 32 \main_pwm0_width_storage - attribute \src "ls180.v:1189.12-1189.29" - wire width 32 \main_pwm1_counter - attribute \src "ls180.v:1186.6-1186.22" - wire \main_pwm1_enable - attribute \src "ls180.v:1191.5-1191.24" - wire \main_pwm1_enable_re - attribute \src "ls180.v:1190.5-1190.29" - wire \main_pwm1_enable_storage - attribute \src "ls180.v:1188.13-1188.29" - wire width 32 \main_pwm1_period - attribute \src "ls180.v:1195.5-1195.24" - wire \main_pwm1_period_re - attribute \src "ls180.v:1194.12-1194.36" - wire width 32 \main_pwm1_period_storage - attribute \src "ls180.v:1187.13-1187.28" - wire width 32 \main_pwm1_width - attribute \src "ls180.v:1193.5-1193.23" - wire \main_pwm1_width_re - attribute \src "ls180.v:1192.12-1192.35" - wire width 32 \main_pwm1_width_storage - attribute \src "ls180.v:359.11-359.25" - wire width 3 \main_rddata_en - attribute \src "ls180.v:1717.11-1717.43" - wire width 3 \main_sdblock2mem_converter_demux - attribute \src "ls180.v:1718.6-1718.42" - wire \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:1708.6-1708.43" - wire \main_sdblock2mem_converter_sink_first - attribute \src "ls180.v:1709.6-1709.42" - wire \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:1710.12-1710.56" - wire width 8 \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:1707.6-1707.43" - wire \main_sdblock2mem_converter_sink_ready - attribute \src "ls180.v:1706.6-1706.43" - wire \main_sdblock2mem_converter_sink_valid - attribute \src "ls180.v:1713.5-1713.44" - wire \main_sdblock2mem_converter_source_first - attribute \src "ls180.v:1714.5-1714.43" - wire \main_sdblock2mem_converter_source_last - attribute \src "ls180.v:1715.12-1715.58" - wire width 64 \main_sdblock2mem_converter_source_payload_data - attribute \src "ls180.v:1716.11-1716.70" - wire width 4 \main_sdblock2mem_converter_source_payload_valid_token_count - attribute \src "ls180.v:1712.6-1712.45" - wire \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:1711.6-1711.45" - wire \main_sdblock2mem_converter_source_valid - attribute \src "ls180.v:1719.5-1719.42" - wire \main_sdblock2mem_converter_strobe_all - attribute \src "ls180.v:1692.11-1692.40" - wire width 5 \main_sdblock2mem_fifo_consume - attribute \src "ls180.v:1697.6-1697.35" - wire \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:1701.6-1701.41" - wire \main_sdblock2mem_fifo_fifo_in_first - attribute \src "ls180.v:1702.6-1702.40" - wire \main_sdblock2mem_fifo_fifo_in_last - attribute \src "ls180.v:1700.12-1700.54" - wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data - attribute \src "ls180.v:1704.6-1704.42" - wire \main_sdblock2mem_fifo_fifo_out_first - attribute \src "ls180.v:1705.6-1705.41" - wire \main_sdblock2mem_fifo_fifo_out_last - attribute \src "ls180.v:1703.12-1703.55" - wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data - attribute \src "ls180.v:1689.11-1689.38" - wire width 6 \main_sdblock2mem_fifo_level - attribute \src "ls180.v:1691.11-1691.40" - wire width 5 \main_sdblock2mem_fifo_produce - attribute \src "ls180.v:1698.12-1698.44" - wire width 5 \main_sdblock2mem_fifo_rdport_adr - attribute \src "ls180.v:1699.12-1699.46" - wire width 10 \main_sdblock2mem_fifo_rdport_dat_r - attribute \src "ls180.v:1690.5-1690.34" - wire \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:1675.6-1675.38" - wire \main_sdblock2mem_fifo_sink_first - attribute \src "ls180.v:1676.6-1676.37" - wire \main_sdblock2mem_fifo_sink_last - attribute \src "ls180.v:1677.12-1677.51" - wire width 8 \main_sdblock2mem_fifo_sink_payload_data - attribute \src "ls180.v:1674.6-1674.38" - wire \main_sdblock2mem_fifo_sink_ready - attribute \src "ls180.v:1673.6-1673.38" - wire \main_sdblock2mem_fifo_sink_valid - attribute \src "ls180.v:1680.6-1680.40" - wire \main_sdblock2mem_fifo_source_first - attribute \src "ls180.v:1681.6-1681.39" - wire \main_sdblock2mem_fifo_source_last - attribute \src "ls180.v:1682.12-1682.53" - wire width 8 \main_sdblock2mem_fifo_source_payload_data - attribute \src "ls180.v:1679.6-1679.40" - wire \main_sdblock2mem_fifo_source_ready - attribute \src "ls180.v:1678.6-1678.40" - wire \main_sdblock2mem_fifo_source_valid - attribute \src "ls180.v:1687.12-1687.46" - wire width 10 \main_sdblock2mem_fifo_syncfifo_din - attribute \src "ls180.v:1688.12-1688.47" - wire width 10 \main_sdblock2mem_fifo_syncfifo_dout - attribute \src "ls180.v:1685.6-1685.39" - wire \main_sdblock2mem_fifo_syncfifo_re - attribute \src "ls180.v:1686.6-1686.45" - wire \main_sdblock2mem_fifo_syncfifo_readable - attribute \src "ls180.v:1683.6-1683.39" - wire \main_sdblock2mem_fifo_syncfifo_we - attribute \src "ls180.v:1684.6-1684.45" - wire \main_sdblock2mem_fifo_syncfifo_writable - attribute \src "ls180.v:1693.11-1693.43" - wire width 5 \main_sdblock2mem_fifo_wrport_adr - attribute \src "ls180.v:1694.12-1694.46" - wire width 10 \main_sdblock2mem_fifo_wrport_dat_r - attribute \src "ls180.v:1696.12-1696.46" - wire width 10 \main_sdblock2mem_fifo_wrport_dat_w - attribute \src "ls180.v:1695.6-1695.37" - wire \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:1670.6-1670.38" - wire \main_sdblock2mem_sink_sink_first - attribute \src "ls180.v:1671.6-1671.37" - wire \main_sdblock2mem_sink_sink_last - attribute \src "ls180.v:1727.12-1727.54" - wire width 32 \main_sdblock2mem_sink_sink_payload_address - attribute \src "ls180.v:1672.12-1672.52" - wire width 8 \main_sdblock2mem_sink_sink_payload_data0 - attribute \src "ls180.v:1728.12-1728.52" - wire width 64 \main_sdblock2mem_sink_sink_payload_data1 - attribute \src "ls180.v:1669.6-1669.39" - wire \main_sdblock2mem_sink_sink_ready0 - attribute \src "ls180.v:1726.6-1726.39" - wire \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:1668.6-1668.39" - wire \main_sdblock2mem_sink_sink_valid0 - attribute \src "ls180.v:1725.5-1725.38" - wire \main_sdblock2mem_sink_sink_valid1 - attribute \src "ls180.v:1722.6-1722.42" - wire \main_sdblock2mem_source_source_first - attribute \src "ls180.v:1723.6-1723.41" - wire \main_sdblock2mem_source_source_last - attribute \src "ls180.v:1724.13-1724.56" - wire width 64 \main_sdblock2mem_source_source_payload_data - attribute \src "ls180.v:1721.6-1721.42" - wire \main_sdblock2mem_source_source_ready - attribute \src "ls180.v:1720.6-1720.42" - wire \main_sdblock2mem_source_source_valid - attribute \src "ls180.v:1744.13-1744.52" - wire width 32 \main_sdblock2mem_wishbonedmawriter_base - attribute \src "ls180.v:1735.5-1735.47" - wire \main_sdblock2mem_wishbonedmawriter_base_re - attribute \src "ls180.v:1734.12-1734.59" - wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage - attribute \src "ls180.v:1739.5-1739.49" - wire \main_sdblock2mem_wishbonedmawriter_enable_re - attribute \src "ls180.v:1738.5-1738.54" - wire \main_sdblock2mem_wishbonedmawriter_enable_storage - attribute \src "ls180.v:1746.13-1746.54" - wire width 32 \main_sdblock2mem_wishbonedmawriter_length - attribute \src "ls180.v:1737.5-1737.49" - wire \main_sdblock2mem_wishbonedmawriter_length_re - attribute \src "ls180.v:1736.12-1736.61" - wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage - attribute \src "ls180.v:1743.5-1743.47" - wire \main_sdblock2mem_wishbonedmawriter_loop_re - attribute \src "ls180.v:1742.5-1742.52" - wire \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:1745.12-1745.53" - wire width 32 \main_sdblock2mem_wishbonedmawriter_offset - attribute \src "ls180.v:1965.12-1965.79" - wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - attribute \src "ls180.v:1966.5-1966.75" - wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:1747.6-1747.46" - wire \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:1731.6-1731.51" - wire \main_sdblock2mem_wishbonedmawriter_sink_first - attribute \src "ls180.v:1732.6-1732.50" - wire \main_sdblock2mem_wishbonedmawriter_sink_last - attribute \src "ls180.v:1733.13-1733.65" - wire width 64 \main_sdblock2mem_wishbonedmawriter_sink_payload_data - attribute \src "ls180.v:1730.5-1730.50" - wire \main_sdblock2mem_wishbonedmawriter_sink_ready - attribute \src "ls180.v:1729.6-1729.51" - wire \main_sdblock2mem_wishbonedmawriter_sink_valid - attribute \src "ls180.v:1740.5-1740.46" - wire \main_sdblock2mem_wishbonedmawriter_status - attribute \src "ls180.v:1741.6-1741.43" - wire \main_sdblock2mem_wishbonedmawriter_we - attribute \src "ls180.v:1509.5-1509.31" - wire \main_sdcore_block_count_re - attribute \src "ls180.v:1508.12-1508.43" - wire width 32 \main_sdcore_block_count_storage - attribute \src "ls180.v:1507.5-1507.32" - wire \main_sdcore_block_length_re - attribute \src "ls180.v:1506.11-1506.43" - wire width 10 \main_sdcore_block_length_storage - attribute \src "ls180.v:1493.5-1493.32" - wire \main_sdcore_cmd_argument_re - attribute \src "ls180.v:1492.12-1492.44" - wire width 32 \main_sdcore_cmd_argument_storage - attribute \src "ls180.v:1495.5-1495.31" - wire \main_sdcore_cmd_command_re - attribute \src "ls180.v:1494.12-1494.43" - wire width 32 \main_sdcore_cmd_command_storage - attribute \src "ls180.v:1648.11-1648.32" - wire width 3 \main_sdcore_cmd_count - attribute \src "ls180.v:1949.11-1949.55" - wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 - attribute \src "ls180.v:1950.5-1950.52" - wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:1649.5-1649.25" - wire \main_sdcore_cmd_done - attribute \src "ls180.v:1945.5-1945.48" - wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 - attribute \src "ls180.v:1946.5-1946.51" - wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:1650.5-1650.26" - wire \main_sdcore_cmd_error - attribute \src "ls180.v:1953.5-1953.49" - wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 - attribute \src "ls180.v:1954.5-1954.52" - wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:1502.12-1502.40" - wire width 4 \main_sdcore_cmd_event_status - attribute \src "ls180.v:1503.6-1503.30" - wire \main_sdcore_cmd_event_we - attribute \src "ls180.v:1500.13-1500.44" - wire width 128 \main_sdcore_cmd_response_status - attribute \src "ls180.v:1961.13-1961.67" - wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - attribute \src "ls180.v:1962.5-1962.62" - wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:1501.6-1501.33" - wire \main_sdcore_cmd_response_we - attribute \src "ls180.v:1497.6-1497.28" - wire \main_sdcore_cmd_send_r - attribute \src "ls180.v:1496.6-1496.29" - wire \main_sdcore_cmd_send_re - attribute \src "ls180.v:1499.5-1499.27" - wire \main_sdcore_cmd_send_w - attribute \src "ls180.v:1498.6-1498.29" - wire \main_sdcore_cmd_send_we - attribute \src "ls180.v:1651.5-1651.28" - wire \main_sdcore_cmd_timeout - attribute \src "ls180.v:1955.5-1955.51" - wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - attribute \src "ls180.v:1956.5-1956.54" - wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:1647.12-1647.32" - wire width 2 \main_sdcore_cmd_type - attribute \src "ls180.v:1609.11-1609.40" - wire width 4 \main_sdcore_crc16_checker_cnt - attribute \src "ls180.v:1615.5-1615.39" - wire \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:1614.12-1614.46" - wire width 16 \main_sdcore_crc16_checker_crc0_crc - attribute \src "ls180.v:1610.12-1610.50" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 - attribute \src "ls180.v:1611.13-1611.51" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 - attribute \src "ls180.v:1612.13-1612.51" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:1616.6-1616.43" - wire \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:1613.12-1613.46" - wire width 2 \main_sdcore_crc16_checker_crc0_val - attribute \src "ls180.v:1622.5-1622.39" - wire \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:1621.12-1621.46" - wire width 16 \main_sdcore_crc16_checker_crc1_crc - attribute \src "ls180.v:1617.12-1617.50" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 - attribute \src "ls180.v:1618.13-1618.51" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 - attribute \src "ls180.v:1619.13-1619.51" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:1623.6-1623.43" - wire \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:1620.12-1620.46" - wire width 2 \main_sdcore_crc16_checker_crc1_val - attribute \src "ls180.v:1629.5-1629.39" - wire \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:1628.12-1628.46" - wire width 16 \main_sdcore_crc16_checker_crc2_crc - attribute \src "ls180.v:1624.12-1624.50" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 - attribute \src "ls180.v:1625.13-1625.51" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 - attribute \src "ls180.v:1626.13-1626.51" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:1630.6-1630.43" - wire \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:1627.12-1627.46" - wire width 2 \main_sdcore_crc16_checker_crc2_val - attribute \src "ls180.v:1636.5-1636.39" - wire \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:1635.12-1635.46" - wire width 16 \main_sdcore_crc16_checker_crc3_crc - attribute \src "ls180.v:1631.12-1631.50" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 - attribute \src "ls180.v:1632.13-1632.51" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 - attribute \src "ls180.v:1633.13-1633.51" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:1637.6-1637.43" - wire \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:1634.12-1634.46" - wire width 2 \main_sdcore_crc16_checker_crc3_val - attribute \src "ls180.v:1638.12-1638.45" - wire width 16 \main_sdcore_crc16_checker_crctmp0 - attribute \src "ls180.v:1639.12-1639.45" - wire width 16 \main_sdcore_crc16_checker_crctmp1 - attribute \src "ls180.v:1640.12-1640.45" - wire width 16 \main_sdcore_crc16_checker_crctmp2 - attribute \src "ls180.v:1641.12-1641.45" - wire width 16 \main_sdcore_crc16_checker_crctmp3 - attribute \src "ls180.v:1643.12-1643.43" - wire width 16 \main_sdcore_crc16_checker_fifo0 - attribute \src "ls180.v:1644.12-1644.43" - wire width 16 \main_sdcore_crc16_checker_fifo1 - attribute \src "ls180.v:1645.12-1645.43" - wire width 16 \main_sdcore_crc16_checker_fifo2 - attribute \src "ls180.v:1646.12-1646.43" - wire width 16 \main_sdcore_crc16_checker_fifo3 - attribute \src "ls180.v:1600.5-1600.41" - wire \main_sdcore_crc16_checker_sink_first - attribute \src "ls180.v:1601.5-1601.40" - wire \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:1602.11-1602.54" - wire width 8 \main_sdcore_crc16_checker_sink_payload_data - attribute \src "ls180.v:1599.5-1599.41" - wire \main_sdcore_crc16_checker_sink_ready - attribute \src "ls180.v:1598.5-1598.41" - wire \main_sdcore_crc16_checker_sink_valid - attribute \src "ls180.v:1605.5-1605.43" - wire \main_sdcore_crc16_checker_source_first - attribute \src "ls180.v:1606.6-1606.43" - wire \main_sdcore_crc16_checker_source_last - attribute \src "ls180.v:1607.12-1607.57" - wire width 8 \main_sdcore_crc16_checker_source_payload_data - attribute \src "ls180.v:1604.6-1604.44" - wire \main_sdcore_crc16_checker_source_ready - attribute \src "ls180.v:1603.5-1603.43" - wire \main_sdcore_crc16_checker_source_valid - attribute \src "ls180.v:1608.11-1608.40" - wire width 8 \main_sdcore_crc16_checker_val - attribute \src "ls180.v:1642.5-1642.36" - wire \main_sdcore_crc16_checker_valid - attribute \src "ls180.v:1565.11-1565.41" - wire width 3 \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:1941.11-1941.80" - wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - attribute \src "ls180.v:1942.5-1942.77" - wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:1571.6-1571.41" - wire \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:1570.12-1570.47" - wire width 16 \main_sdcore_crc16_inserter_crc0_crc - attribute \src "ls180.v:1566.12-1566.51" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 - attribute \src "ls180.v:1567.13-1567.52" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 - attribute \src "ls180.v:1568.13-1568.52" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:1572.6-1572.44" - wire \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:1569.12-1569.47" - wire width 2 \main_sdcore_crc16_inserter_crc0_val - attribute \src "ls180.v:1578.6-1578.41" - wire \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:1577.12-1577.47" - wire width 16 \main_sdcore_crc16_inserter_crc1_crc - attribute \src "ls180.v:1573.12-1573.51" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 - attribute \src "ls180.v:1574.13-1574.52" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 - attribute \src "ls180.v:1575.13-1575.52" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:1579.6-1579.44" - wire \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:1576.12-1576.47" - wire width 2 \main_sdcore_crc16_inserter_crc1_val - attribute \src "ls180.v:1585.6-1585.41" - wire \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:1584.12-1584.47" - wire width 16 \main_sdcore_crc16_inserter_crc2_crc - attribute \src "ls180.v:1580.12-1580.51" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 - attribute \src "ls180.v:1581.13-1581.52" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 - attribute \src "ls180.v:1582.13-1582.52" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:1586.6-1586.44" - wire \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:1583.12-1583.47" - wire width 2 \main_sdcore_crc16_inserter_crc2_val - attribute \src "ls180.v:1592.6-1592.41" - wire \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:1591.12-1591.47" - wire width 16 \main_sdcore_crc16_inserter_crc3_crc - attribute \src "ls180.v:1587.12-1587.51" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 - attribute \src "ls180.v:1588.13-1588.52" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 - attribute \src "ls180.v:1589.13-1589.52" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:1593.6-1593.44" - wire \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:1590.12-1590.47" - wire width 2 \main_sdcore_crc16_inserter_crc3_val - attribute \src "ls180.v:1594.12-1594.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp0 - attribute \src "ls180.v:1933.12-1933.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - attribute \src "ls180.v:1934.5-1934.81" - wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:1595.12-1595.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp1 - attribute \src "ls180.v:1935.12-1935.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - attribute \src "ls180.v:1936.5-1936.81" - wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:1596.12-1596.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp2 - attribute \src "ls180.v:1937.12-1937.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - attribute \src "ls180.v:1938.5-1938.81" - wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:1597.12-1597.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp3 - attribute \src "ls180.v:1939.12-1939.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - attribute \src "ls180.v:1940.5-1940.81" - wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:1557.6-1557.43" - wire \main_sdcore_crc16_inserter_sink_first - attribute \src "ls180.v:1558.6-1558.42" - wire \main_sdcore_crc16_inserter_sink_last - attribute \src "ls180.v:1559.12-1559.56" - wire width 8 \main_sdcore_crc16_inserter_sink_payload_data - attribute \src "ls180.v:1556.5-1556.42" - wire \main_sdcore_crc16_inserter_sink_ready - attribute \src "ls180.v:1555.6-1555.43" - wire \main_sdcore_crc16_inserter_sink_valid - attribute \src "ls180.v:1562.5-1562.44" - wire \main_sdcore_crc16_inserter_source_first - attribute \src "ls180.v:1563.5-1563.43" - wire \main_sdcore_crc16_inserter_source_last - attribute \src "ls180.v:1564.11-1564.57" - wire width 8 \main_sdcore_crc16_inserter_source_payload_data - attribute \src "ls180.v:1561.5-1561.44" - wire \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:1560.5-1560.44" - wire \main_sdcore_crc16_inserter_source_valid - attribute \src "ls180.v:1553.6-1553.35" - wire \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:1552.11-1552.40" - wire width 7 \main_sdcore_crc7_inserter_crc - attribute \src "ls180.v:1510.11-1510.44" - wire width 7 \main_sdcore_crc7_inserter_crcreg0 - attribute \src "ls180.v:1511.12-1511.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg1 - attribute \src "ls180.v:1520.12-1520.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg10 - attribute \src "ls180.v:1521.12-1521.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg11 - attribute \src "ls180.v:1522.12-1522.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg12 - attribute \src "ls180.v:1523.12-1523.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg13 - attribute \src "ls180.v:1524.12-1524.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg14 - attribute \src "ls180.v:1525.12-1525.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg15 - attribute \src "ls180.v:1526.12-1526.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg16 - attribute \src "ls180.v:1527.12-1527.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg17 - attribute \src "ls180.v:1528.12-1528.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg18 - attribute \src "ls180.v:1529.12-1529.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg19 - attribute \src "ls180.v:1512.12-1512.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg2 - attribute \src "ls180.v:1530.12-1530.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg20 - attribute \src "ls180.v:1531.12-1531.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg21 - attribute \src "ls180.v:1532.12-1532.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg22 - attribute \src "ls180.v:1533.12-1533.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg23 - attribute \src "ls180.v:1534.12-1534.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg24 - attribute \src "ls180.v:1535.12-1535.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg25 - attribute \src "ls180.v:1536.12-1536.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg26 - attribute \src "ls180.v:1537.12-1537.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg27 - attribute \src "ls180.v:1538.12-1538.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg28 - attribute \src "ls180.v:1539.12-1539.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg29 - attribute \src "ls180.v:1513.12-1513.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg3 - attribute \src "ls180.v:1540.12-1540.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg30 - attribute \src "ls180.v:1541.12-1541.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg31 - attribute \src "ls180.v:1542.12-1542.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg32 - attribute \src "ls180.v:1543.12-1543.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg33 - attribute \src "ls180.v:1544.12-1544.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg34 - attribute \src "ls180.v:1545.12-1545.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg35 - attribute \src "ls180.v:1546.12-1546.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg36 - attribute \src "ls180.v:1547.12-1547.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg37 - attribute \src "ls180.v:1548.12-1548.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg38 - attribute \src "ls180.v:1549.12-1549.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg39 - attribute \src "ls180.v:1514.12-1514.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg4 - attribute \src "ls180.v:1550.12-1550.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:1515.12-1515.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg5 - attribute \src "ls180.v:1516.12-1516.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg6 - attribute \src "ls180.v:1517.12-1517.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg7 - attribute \src "ls180.v:1518.12-1518.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg8 - attribute \src "ls180.v:1519.12-1519.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg9 - attribute \src "ls180.v:1554.6-1554.38" - wire \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:1551.13-1551.42" - wire width 40 \main_sdcore_crc7_inserter_val - attribute \src "ls180.v:1653.12-1653.34" - wire width 32 \main_sdcore_data_count - attribute \src "ls180.v:1951.12-1951.57" - wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 - attribute \src "ls180.v:1952.5-1952.53" - wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:1654.5-1654.26" - wire \main_sdcore_data_done - attribute \src "ls180.v:1947.5-1947.49" - wire \main_sdcore_data_done_sdcore_fsm_next_value1 - attribute \src "ls180.v:1948.5-1948.52" - wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:1655.5-1655.27" - wire \main_sdcore_data_error - attribute \src "ls180.v:1957.5-1957.50" - wire \main_sdcore_data_error_sdcore_fsm_next_value6 - attribute \src "ls180.v:1958.5-1958.53" - wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:1504.12-1504.41" - wire width 4 \main_sdcore_data_event_status - attribute \src "ls180.v:1505.6-1505.31" - wire \main_sdcore_data_event_we - attribute \src "ls180.v:1656.5-1656.29" - wire \main_sdcore_data_timeout - attribute \src "ls180.v:1959.5-1959.52" - wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 - attribute \src "ls180.v:1960.5-1960.55" - wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:1652.12-1652.33" - wire width 2 \main_sdcore_data_type - attribute \src "ls180.v:1484.6-1484.33" - wire \main_sdcore_sink_sink_first - attribute \src "ls180.v:1485.6-1485.32" - wire \main_sdcore_sink_sink_last - attribute \src "ls180.v:1486.12-1486.46" - wire width 8 \main_sdcore_sink_sink_payload_data - attribute \src "ls180.v:1483.6-1483.33" - wire \main_sdcore_sink_sink_ready - attribute \src "ls180.v:1482.6-1482.33" - wire \main_sdcore_sink_sink_valid - attribute \src "ls180.v:1489.6-1489.37" - wire \main_sdcore_source_source_first - attribute \src "ls180.v:1490.6-1490.36" - wire \main_sdcore_source_source_last - attribute \src "ls180.v:1491.12-1491.50" - wire width 8 \main_sdcore_source_source_payload_data - attribute \src "ls180.v:1488.6-1488.37" - wire \main_sdcore_source_source_ready - attribute \src "ls180.v:1487.6-1487.37" - wire \main_sdcore_source_source_valid - attribute \src "ls180.v:1802.6-1802.38" - wire \main_sdmem2block_converter_first - attribute \src "ls180.v:1803.6-1803.37" - wire \main_sdmem2block_converter_last - attribute \src "ls180.v:1801.11-1801.41" - wire width 3 \main_sdmem2block_converter_mux - attribute \src "ls180.v:1792.6-1792.43" - wire \main_sdmem2block_converter_sink_first - attribute \src "ls180.v:1793.6-1793.42" - wire \main_sdmem2block_converter_sink_last - attribute \src "ls180.v:1794.13-1794.57" - wire width 64 \main_sdmem2block_converter_sink_payload_data - attribute \src "ls180.v:1791.6-1791.43" - wire \main_sdmem2block_converter_sink_ready - attribute \src "ls180.v:1790.6-1790.43" - wire \main_sdmem2block_converter_sink_valid - attribute \src "ls180.v:1797.6-1797.45" - wire \main_sdmem2block_converter_source_first - attribute \src "ls180.v:1798.6-1798.44" - wire \main_sdmem2block_converter_source_last - attribute \src "ls180.v:1799.11-1799.57" - wire width 8 \main_sdmem2block_converter_source_payload_data - attribute \src "ls180.v:1800.6-1800.65" - wire \main_sdmem2block_converter_source_payload_valid_token_count - attribute \src "ls180.v:1796.6-1796.45" - wire \main_sdmem2block_converter_source_ready - attribute \src "ls180.v:1795.6-1795.45" - wire \main_sdmem2block_converter_source_valid - attribute \src "ls180.v:1786.13-1786.38" - wire width 32 \main_sdmem2block_dma_base - attribute \src "ls180.v:1775.5-1775.33" - wire \main_sdmem2block_dma_base_re - attribute \src "ls180.v:1774.12-1774.45" - wire width 64 \main_sdmem2block_dma_base_storage - attribute \src "ls180.v:1773.12-1773.37" - wire width 64 \main_sdmem2block_dma_data - attribute \src "ls180.v:1969.12-1969.67" - wire width 64 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - attribute \src "ls180.v:1970.5-1970.63" - wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:1780.5-1780.37" - wire \main_sdmem2block_dma_done_status - attribute \src "ls180.v:1781.6-1781.34" - wire \main_sdmem2block_dma_done_we - attribute \src "ls180.v:1779.5-1779.35" - wire \main_sdmem2block_dma_enable_re - attribute \src "ls180.v:1778.5-1778.40" - wire \main_sdmem2block_dma_enable_storage - attribute \src "ls180.v:1788.13-1788.40" - wire width 32 \main_sdmem2block_dma_length - attribute \src "ls180.v:1777.5-1777.35" - wire \main_sdmem2block_dma_length_re - attribute \src "ls180.v:1776.12-1776.47" - wire width 32 \main_sdmem2block_dma_length_storage - attribute \src "ls180.v:1783.5-1783.33" - wire \main_sdmem2block_dma_loop_re - attribute \src "ls180.v:1782.5-1782.38" - wire \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:1787.12-1787.39" - wire width 32 \main_sdmem2block_dma_offset - attribute \src "ls180.v:1973.12-1973.79" - wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - attribute \src "ls180.v:1974.5-1974.75" - wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:1784.13-1784.47" - wire width 32 \main_sdmem2block_dma_offset_status - attribute \src "ls180.v:1785.6-1785.36" - wire \main_sdmem2block_dma_offset_we - attribute \src "ls180.v:1789.6-1789.32" - wire \main_sdmem2block_dma_reset - attribute \src "ls180.v:1766.5-1766.35" - wire \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:1767.12-1767.53" - wire width 32 \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:1765.5-1765.36" - wire \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:1764.5-1764.36" - wire \main_sdmem2block_dma_sink_valid - attribute \src "ls180.v:1770.5-1770.38" - wire \main_sdmem2block_dma_source_first - attribute \src "ls180.v:1771.5-1771.37" - wire \main_sdmem2block_dma_source_last - attribute \src "ls180.v:1772.12-1772.52" - wire width 64 \main_sdmem2block_dma_source_payload_data - attribute \src "ls180.v:1769.6-1769.39" - wire \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:1768.5-1768.38" - wire \main_sdmem2block_dma_source_valid - attribute \src "ls180.v:1828.11-1828.40" - wire width 5 \main_sdmem2block_fifo_consume - attribute \src "ls180.v:1833.6-1833.35" - wire \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:1837.6-1837.41" - wire \main_sdmem2block_fifo_fifo_in_first - attribute \src "ls180.v:1838.6-1838.40" - wire \main_sdmem2block_fifo_fifo_in_last - attribute \src "ls180.v:1836.12-1836.54" - wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data - attribute \src "ls180.v:1840.6-1840.42" - wire \main_sdmem2block_fifo_fifo_out_first - attribute \src "ls180.v:1841.6-1841.41" - wire \main_sdmem2block_fifo_fifo_out_last - attribute \src "ls180.v:1839.12-1839.55" - wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data - attribute \src "ls180.v:1825.11-1825.38" - wire width 6 \main_sdmem2block_fifo_level - attribute \src "ls180.v:1827.11-1827.40" - wire width 5 \main_sdmem2block_fifo_produce - attribute \src "ls180.v:1834.12-1834.44" - wire width 5 \main_sdmem2block_fifo_rdport_adr - attribute \src "ls180.v:1835.12-1835.46" - wire width 10 \main_sdmem2block_fifo_rdport_dat_r - attribute \src "ls180.v:1826.5-1826.34" - wire \main_sdmem2block_fifo_replace - attribute \src "ls180.v:1811.6-1811.38" - wire \main_sdmem2block_fifo_sink_first - attribute \src "ls180.v:1812.6-1812.37" - wire \main_sdmem2block_fifo_sink_last - attribute \src "ls180.v:1813.12-1813.51" - wire width 8 \main_sdmem2block_fifo_sink_payload_data - attribute \src "ls180.v:1810.6-1810.38" - wire \main_sdmem2block_fifo_sink_ready - attribute \src "ls180.v:1809.6-1809.38" - wire \main_sdmem2block_fifo_sink_valid - attribute \src "ls180.v:1816.6-1816.40" - wire \main_sdmem2block_fifo_source_first - attribute \src "ls180.v:1817.6-1817.39" - wire \main_sdmem2block_fifo_source_last - attribute \src "ls180.v:1818.12-1818.53" - wire width 8 \main_sdmem2block_fifo_source_payload_data - attribute \src "ls180.v:1815.6-1815.40" - wire \main_sdmem2block_fifo_source_ready - attribute \src "ls180.v:1814.6-1814.40" - wire \main_sdmem2block_fifo_source_valid - attribute \src "ls180.v:1823.12-1823.46" - wire width 10 \main_sdmem2block_fifo_syncfifo_din - attribute \src "ls180.v:1824.12-1824.47" - wire width 10 \main_sdmem2block_fifo_syncfifo_dout - attribute \src "ls180.v:1821.6-1821.39" - wire \main_sdmem2block_fifo_syncfifo_re - attribute \src "ls180.v:1822.6-1822.45" - wire \main_sdmem2block_fifo_syncfifo_readable - attribute \src "ls180.v:1819.6-1819.39" - wire \main_sdmem2block_fifo_syncfifo_we - attribute \src "ls180.v:1820.6-1820.45" - wire \main_sdmem2block_fifo_syncfifo_writable - attribute \src "ls180.v:1829.11-1829.43" - wire width 5 \main_sdmem2block_fifo_wrport_adr - attribute \src "ls180.v:1830.12-1830.46" - wire width 10 \main_sdmem2block_fifo_wrport_dat_r - attribute \src "ls180.v:1832.12-1832.46" - wire width 10 \main_sdmem2block_fifo_wrport_dat_w - attribute \src "ls180.v:1831.6-1831.37" - wire \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:1761.6-1761.43" - wire \main_sdmem2block_source_source_first0 - attribute \src "ls180.v:1806.6-1806.43" - wire \main_sdmem2block_source_source_first1 - attribute \src "ls180.v:1762.6-1762.42" - wire \main_sdmem2block_source_source_last0 - attribute \src "ls180.v:1807.6-1807.42" - wire \main_sdmem2block_source_source_last1 - attribute \src "ls180.v:1763.12-1763.56" - wire width 8 \main_sdmem2block_source_source_payload_data0 - attribute \src "ls180.v:1808.12-1808.56" - wire width 8 \main_sdmem2block_source_source_payload_data1 - attribute \src "ls180.v:1760.6-1760.43" - wire \main_sdmem2block_source_source_ready0 - attribute \src "ls180.v:1805.6-1805.43" - wire \main_sdmem2block_source_source_ready1 - attribute \src "ls180.v:1759.6-1759.43" - wire \main_sdmem2block_source_source_valid0 - attribute \src "ls180.v:1804.6-1804.43" - wire \main_sdmem2block_source_source_valid1 - attribute \src "ls180.v:1210.6-1210.27" - wire \main_sdphy_clocker_ce - attribute \src "ls180.v:1209.5-1209.28" - wire \main_sdphy_clocker_clk0 - attribute \src "ls180.v:1212.5-1212.28" - wire \main_sdphy_clocker_clk1 - attribute \src "ls180.v:1213.5-1213.29" - wire \main_sdphy_clocker_clk_d - attribute \src "ls180.v:1211.11-1211.34" - wire width 9 \main_sdphy_clocker_clks - attribute \src "ls180.v:1207.5-1207.26" - wire \main_sdphy_clocker_re - attribute \src "ls180.v:1208.6-1208.29" - wire \main_sdphy_clocker_stop - attribute \src "ls180.v:1206.11-1206.37" - wire width 9 \main_sdphy_clocker_storage - attribute \src "ls180.v:1310.6-1310.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_first - attribute \src "ls180.v:1311.6-1311.40" - wire \main_sdphy_cmdr_cmdr_buf_sink_last - attribute \src "ls180.v:1312.12-1312.54" - wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data - attribute \src "ls180.v:1309.6-1309.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_ready - attribute \src "ls180.v:1308.6-1308.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_valid - attribute \src "ls180.v:1315.5-1315.42" - wire \main_sdphy_cmdr_cmdr_buf_source_first - attribute \src "ls180.v:1316.5-1316.41" - wire \main_sdphy_cmdr_cmdr_buf_source_last - attribute \src "ls180.v:1317.11-1317.55" - wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data - attribute \src "ls180.v:1314.6-1314.43" - wire \main_sdphy_cmdr_cmdr_buf_source_ready - attribute \src "ls180.v:1313.5-1313.42" - wire \main_sdphy_cmdr_cmdr_buf_source_valid - attribute \src "ls180.v:1300.11-1300.47" - wire width 3 \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:1301.6-1301.46" - wire \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:1291.5-1291.46" - wire \main_sdphy_cmdr_cmdr_converter_sink_first - attribute \src "ls180.v:1292.5-1292.45" - wire \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:1293.6-1293.54" - wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:1290.6-1290.47" - wire \main_sdphy_cmdr_cmdr_converter_sink_ready - attribute \src "ls180.v:1289.6-1289.47" - wire \main_sdphy_cmdr_cmdr_converter_sink_valid - attribute \src "ls180.v:1296.5-1296.48" - wire \main_sdphy_cmdr_cmdr_converter_source_first - attribute \src "ls180.v:1297.5-1297.47" - wire \main_sdphy_cmdr_cmdr_converter_source_last - attribute \src "ls180.v:1298.11-1298.61" - wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data - attribute \src "ls180.v:1299.11-1299.74" - wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1295.6-1295.49" - wire \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:1294.6-1294.49" - wire \main_sdphy_cmdr_cmdr_converter_source_valid - attribute \src "ls180.v:1302.5-1302.46" - wire \main_sdphy_cmdr_cmdr_converter_strobe_all - attribute \src "ls180.v:1273.6-1273.40" - wire \main_sdphy_cmdr_cmdr_pads_in_first - attribute \src "ls180.v:1274.6-1274.39" - wire \main_sdphy_cmdr_cmdr_pads_in_last - attribute \src "ls180.v:1275.6-1275.46" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk - attribute \src "ls180.v:1276.6-1276.48" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - attribute \src "ls180.v:1277.6-1277.48" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o - attribute \src "ls180.v:1278.6-1278.49" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1279.12-1279.55" - wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i - attribute \src "ls180.v:1280.12-1280.55" - wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o - attribute \src "ls180.v:1281.6-1281.50" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe - attribute \src "ls180.v:1272.5-1272.39" - wire \main_sdphy_cmdr_cmdr_pads_in_ready - attribute \src "ls180.v:1271.6-1271.40" - wire \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:1318.5-1318.31" - wire \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:1913.5-1913.59" - wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - attribute \src "ls180.v:1914.5-1914.62" - wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:1288.5-1288.29" - wire \main_sdphy_cmdr_cmdr_run - attribute \src "ls180.v:1284.6-1284.47" - wire \main_sdphy_cmdr_cmdr_source_source_first0 - attribute \src "ls180.v:1305.6-1305.47" - wire \main_sdphy_cmdr_cmdr_source_source_first1 - attribute \src "ls180.v:1285.6-1285.46" - wire \main_sdphy_cmdr_cmdr_source_source_last0 - attribute \src "ls180.v:1306.6-1306.46" - wire \main_sdphy_cmdr_cmdr_source_source_last1 - attribute \src "ls180.v:1286.12-1286.60" - wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 - attribute \src "ls180.v:1307.12-1307.60" - wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 - attribute \src "ls180.v:1283.5-1283.46" - wire \main_sdphy_cmdr_cmdr_source_source_ready0 - attribute \src "ls180.v:1304.6-1304.47" - wire \main_sdphy_cmdr_cmdr_source_source_ready1 - attribute \src "ls180.v:1282.6-1282.47" - wire \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:1303.6-1303.47" - wire \main_sdphy_cmdr_cmdr_source_source_valid1 - attribute \src "ls180.v:1287.6-1287.32" - wire \main_sdphy_cmdr_cmdr_start - attribute \src "ls180.v:1270.11-1270.32" - wire width 8 \main_sdphy_cmdr_count - attribute \src "ls180.v:1909.11-1909.60" - wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - attribute \src "ls180.v:1910.5-1910.57" - wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:1245.5-1245.42" - wire \main_sdphy_cmdr_pads_in_pads_in_first - attribute \src "ls180.v:1246.5-1246.41" - wire \main_sdphy_cmdr_pads_in_pads_in_last - attribute \src "ls180.v:1247.5-1247.48" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1248.6-1248.51" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1249.5-1249.50" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1250.5-1250.51" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1251.12-1251.58" - wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1252.11-1252.57" - wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1253.5-1253.52" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1244.6-1244.43" - wire \main_sdphy_cmdr_pads_in_pads_in_ready - attribute \src "ls180.v:1243.6-1243.43" - wire \main_sdphy_cmdr_pads_in_pads_in_valid - attribute \src "ls180.v:1255.5-1255.41" - wire \main_sdphy_cmdr_pads_out_payload_clk - attribute \src "ls180.v:1256.5-1256.43" - wire \main_sdphy_cmdr_pads_out_payload_cmd_o - attribute \src "ls180.v:1257.5-1257.44" - wire \main_sdphy_cmdr_pads_out_payload_cmd_oe - attribute \src "ls180.v:1258.11-1258.50" - wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o - attribute \src "ls180.v:1259.5-1259.45" - wire \main_sdphy_cmdr_pads_out_payload_data_oe - attribute \src "ls180.v:1254.6-1254.36" - wire \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:1262.5-1262.30" - wire \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:1263.11-1263.46" - wire width 8 \main_sdphy_cmdr_sink_payload_length - attribute \src "ls180.v:1261.5-1261.31" - wire \main_sdphy_cmdr_sink_ready - attribute \src "ls180.v:1260.5-1260.31" - wire \main_sdphy_cmdr_sink_valid - attribute \src "ls180.v:1266.5-1266.32" - wire \main_sdphy_cmdr_source_last - attribute \src "ls180.v:1267.11-1267.46" - wire width 8 \main_sdphy_cmdr_source_payload_data - attribute \src "ls180.v:1268.11-1268.48" - wire width 3 \main_sdphy_cmdr_source_payload_status - attribute \src "ls180.v:1265.5-1265.33" - wire \main_sdphy_cmdr_source_ready - attribute \src "ls180.v:1264.5-1264.33" - wire \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:1269.12-1269.35" - wire width 32 \main_sdphy_cmdr_timeout - attribute \src "ls180.v:1911.12-1911.63" - wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - attribute \src "ls180.v:1912.5-1912.59" - wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:1242.11-1242.32" - wire width 8 \main_sdphy_cmdw_count - attribute \src "ls180.v:1905.11-1905.59" - wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - attribute \src "ls180.v:1906.5-1906.56" - wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:1241.5-1241.25" - wire \main_sdphy_cmdw_done - attribute \src "ls180.v:1229.6-1229.43" - wire \main_sdphy_cmdw_pads_in_payload_cmd_i - attribute \src "ls180.v:1230.12-1230.50" - wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i - attribute \src "ls180.v:1228.6-1228.35" - wire \main_sdphy_cmdw_pads_in_valid - attribute \src "ls180.v:1232.5-1232.41" - wire \main_sdphy_cmdw_pads_out_payload_clk - attribute \src "ls180.v:1233.5-1233.43" - wire \main_sdphy_cmdw_pads_out_payload_cmd_o - attribute \src "ls180.v:1234.5-1234.44" - wire \main_sdphy_cmdw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1235.11-1235.50" - wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o - attribute \src "ls180.v:1236.5-1236.45" - wire \main_sdphy_cmdw_pads_out_payload_data_oe - attribute \src "ls180.v:1231.6-1231.36" - wire \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:1239.5-1239.30" - wire \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:1240.11-1240.44" - wire width 8 \main_sdphy_cmdw_sink_payload_data - attribute \src "ls180.v:1238.5-1238.31" - wire \main_sdphy_cmdw_sink_ready - attribute \src "ls180.v:1237.5-1237.31" - wire \main_sdphy_cmdw_sink_valid - attribute \src "ls180.v:1426.11-1426.33" - wire width 10 \main_sdphy_datar_count - attribute \src "ls180.v:1925.11-1925.62" - wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - attribute \src "ls180.v:1926.5-1926.59" - wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:1466.6-1466.43" - wire \main_sdphy_datar_datar_buf_sink_first - attribute \src "ls180.v:1467.6-1467.42" - wire \main_sdphy_datar_datar_buf_sink_last - attribute \src "ls180.v:1468.12-1468.56" - wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data - attribute \src "ls180.v:1465.6-1465.43" - wire \main_sdphy_datar_datar_buf_sink_ready - attribute \src "ls180.v:1464.6-1464.43" - wire \main_sdphy_datar_datar_buf_sink_valid - attribute \src "ls180.v:1471.5-1471.44" - wire \main_sdphy_datar_datar_buf_source_first - attribute \src "ls180.v:1472.5-1472.43" - wire \main_sdphy_datar_datar_buf_source_last - attribute \src "ls180.v:1473.11-1473.57" - wire width 8 \main_sdphy_datar_datar_buf_source_payload_data - attribute \src "ls180.v:1470.6-1470.45" - wire \main_sdphy_datar_datar_buf_source_ready - attribute \src "ls180.v:1469.5-1469.44" - wire \main_sdphy_datar_datar_buf_source_valid - attribute \src "ls180.v:1456.5-1456.43" - wire \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:1457.6-1457.48" - wire \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:1447.5-1447.48" - wire \main_sdphy_datar_datar_converter_sink_first - attribute \src "ls180.v:1448.5-1448.47" - wire \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:1449.12-1449.62" - wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:1446.6-1446.49" - wire \main_sdphy_datar_datar_converter_sink_ready - attribute \src "ls180.v:1445.6-1445.49" - wire \main_sdphy_datar_datar_converter_sink_valid - attribute \src "ls180.v:1452.5-1452.50" - wire \main_sdphy_datar_datar_converter_source_first - attribute \src "ls180.v:1453.5-1453.49" - wire \main_sdphy_datar_datar_converter_source_last - attribute \src "ls180.v:1454.11-1454.63" - wire width 8 \main_sdphy_datar_datar_converter_source_payload_data - attribute \src "ls180.v:1455.11-1455.76" - wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count - attribute \src "ls180.v:1451.6-1451.51" - wire \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:1450.6-1450.51" - wire \main_sdphy_datar_datar_converter_source_valid - attribute \src "ls180.v:1458.5-1458.48" - wire \main_sdphy_datar_datar_converter_strobe_all - attribute \src "ls180.v:1429.6-1429.42" - wire \main_sdphy_datar_datar_pads_in_first - attribute \src "ls180.v:1430.6-1430.41" - wire \main_sdphy_datar_datar_pads_in_last - attribute \src "ls180.v:1431.6-1431.48" - wire \main_sdphy_datar_datar_pads_in_payload_clk - attribute \src "ls180.v:1432.6-1432.50" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_i - attribute \src "ls180.v:1433.6-1433.50" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_o - attribute \src "ls180.v:1434.6-1434.51" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe - attribute \src "ls180.v:1435.12-1435.57" - wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i - attribute \src "ls180.v:1436.12-1436.57" - wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o - attribute \src "ls180.v:1437.6-1437.52" - wire \main_sdphy_datar_datar_pads_in_payload_data_oe - attribute \src "ls180.v:1428.5-1428.41" - wire \main_sdphy_datar_datar_pads_in_ready - attribute \src "ls180.v:1427.6-1427.42" - wire \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:1474.5-1474.33" - wire \main_sdphy_datar_datar_reset - attribute \src "ls180.v:1929.5-1929.62" - wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - attribute \src "ls180.v:1930.5-1930.65" - wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:1444.5-1444.31" - wire \main_sdphy_datar_datar_run - attribute \src "ls180.v:1440.6-1440.49" - wire \main_sdphy_datar_datar_source_source_first0 - attribute \src "ls180.v:1461.6-1461.49" - wire \main_sdphy_datar_datar_source_source_first1 - attribute \src "ls180.v:1441.6-1441.48" - wire \main_sdphy_datar_datar_source_source_last0 - attribute \src "ls180.v:1462.6-1462.48" - wire \main_sdphy_datar_datar_source_source_last1 - attribute \src "ls180.v:1442.12-1442.62" - wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 - attribute \src "ls180.v:1463.12-1463.62" - wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 - attribute \src "ls180.v:1439.5-1439.48" - wire \main_sdphy_datar_datar_source_source_ready0 - attribute \src "ls180.v:1460.6-1460.49" - wire \main_sdphy_datar_datar_source_source_ready1 - attribute \src "ls180.v:1438.6-1438.49" - wire \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:1459.6-1459.49" - wire \main_sdphy_datar_datar_source_source_valid1 - attribute \src "ls180.v:1443.6-1443.34" - wire \main_sdphy_datar_datar_start - attribute \src "ls180.v:1399.5-1399.43" - wire \main_sdphy_datar_pads_in_pads_in_first - attribute \src "ls180.v:1400.5-1400.42" - wire \main_sdphy_datar_pads_in_pads_in_last - attribute \src "ls180.v:1401.5-1401.49" - wire \main_sdphy_datar_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1402.6-1402.52" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1403.5-1403.51" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1404.5-1404.52" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1405.12-1405.59" - wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1406.11-1406.58" - wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1407.5-1407.53" - wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1398.6-1398.44" - wire \main_sdphy_datar_pads_in_pads_in_ready - attribute \src "ls180.v:1397.6-1397.44" - wire \main_sdphy_datar_pads_in_pads_in_valid - attribute \src "ls180.v:1409.5-1409.42" - wire \main_sdphy_datar_pads_out_payload_clk - attribute \src "ls180.v:1410.5-1410.44" - wire \main_sdphy_datar_pads_out_payload_cmd_o - attribute \src "ls180.v:1411.5-1411.45" - wire \main_sdphy_datar_pads_out_payload_cmd_oe - attribute \src "ls180.v:1412.11-1412.51" - wire width 4 \main_sdphy_datar_pads_out_payload_data_o - attribute \src "ls180.v:1413.5-1413.46" - wire \main_sdphy_datar_pads_out_payload_data_oe - attribute \src "ls180.v:1408.6-1408.37" - wire \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:1416.5-1416.31" - wire \main_sdphy_datar_sink_last - attribute \src "ls180.v:1417.11-1417.53" - wire width 10 \main_sdphy_datar_sink_payload_block_length - attribute \src "ls180.v:1415.5-1415.32" - wire \main_sdphy_datar_sink_ready - attribute \src "ls180.v:1414.5-1414.32" - wire \main_sdphy_datar_sink_valid - attribute \src "ls180.v:1420.5-1420.34" - wire \main_sdphy_datar_source_first - attribute \src "ls180.v:1421.5-1421.33" - wire \main_sdphy_datar_source_last - attribute \src "ls180.v:1422.11-1422.47" - wire width 8 \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:1423.11-1423.49" - wire width 3 \main_sdphy_datar_source_payload_status - attribute \src "ls180.v:1419.5-1419.34" - wire \main_sdphy_datar_source_ready - attribute \src "ls180.v:1418.5-1418.34" - wire \main_sdphy_datar_source_valid - attribute \src "ls180.v:1424.5-1424.26" - wire \main_sdphy_datar_stop - attribute \src "ls180.v:1425.12-1425.36" - wire width 32 \main_sdphy_datar_timeout - attribute \src "ls180.v:1927.12-1927.65" - wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - attribute \src "ls180.v:1928.5-1928.61" - wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:1334.11-1334.33" - wire width 8 \main_sdphy_dataw_count - attribute \src "ls180.v:1921.11-1921.54" - wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value - attribute \src "ls180.v:1922.5-1922.51" - wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:1388.6-1388.42" - wire \main_sdphy_dataw_crcr_buf_sink_first - attribute \src "ls180.v:1389.6-1389.41" - wire \main_sdphy_dataw_crcr_buf_sink_last - attribute \src "ls180.v:1390.12-1390.55" - wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data - attribute \src "ls180.v:1387.6-1387.42" - wire \main_sdphy_dataw_crcr_buf_sink_ready - attribute \src "ls180.v:1386.6-1386.42" - wire \main_sdphy_dataw_crcr_buf_sink_valid - attribute \src "ls180.v:1393.5-1393.43" - wire \main_sdphy_dataw_crcr_buf_source_first - attribute \src "ls180.v:1394.5-1394.42" - wire \main_sdphy_dataw_crcr_buf_source_last - attribute \src "ls180.v:1395.11-1395.56" - wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data - attribute \src "ls180.v:1392.6-1392.44" - wire \main_sdphy_dataw_crcr_buf_source_ready - attribute \src "ls180.v:1391.5-1391.43" - wire \main_sdphy_dataw_crcr_buf_source_valid - attribute \src "ls180.v:1378.11-1378.48" - wire width 3 \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:1379.6-1379.47" - wire \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:1369.5-1369.47" - wire \main_sdphy_dataw_crcr_converter_sink_first - attribute \src "ls180.v:1370.5-1370.46" - wire \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:1371.6-1371.55" - wire \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:1368.6-1368.48" - wire \main_sdphy_dataw_crcr_converter_sink_ready - attribute \src "ls180.v:1367.6-1367.48" - wire \main_sdphy_dataw_crcr_converter_sink_valid - attribute \src "ls180.v:1374.5-1374.49" - wire \main_sdphy_dataw_crcr_converter_source_first - attribute \src "ls180.v:1375.5-1375.48" - wire \main_sdphy_dataw_crcr_converter_source_last - attribute \src "ls180.v:1376.11-1376.62" - wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data - attribute \src "ls180.v:1377.11-1377.75" - wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1373.6-1373.50" - wire \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:1372.6-1372.50" - wire \main_sdphy_dataw_crcr_converter_source_valid - attribute \src "ls180.v:1380.5-1380.47" - wire \main_sdphy_dataw_crcr_converter_strobe_all - attribute \src "ls180.v:1351.6-1351.41" - wire \main_sdphy_dataw_crcr_pads_in_first - attribute \src "ls180.v:1352.6-1352.40" - wire \main_sdphy_dataw_crcr_pads_in_last - attribute \src "ls180.v:1353.6-1353.47" - wire \main_sdphy_dataw_crcr_pads_in_payload_clk - attribute \src "ls180.v:1354.6-1354.49" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i - attribute \src "ls180.v:1355.6-1355.49" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o - attribute \src "ls180.v:1356.6-1356.50" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1357.12-1357.56" - wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i - attribute \src "ls180.v:1358.12-1358.56" - wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o - attribute \src "ls180.v:1359.6-1359.51" - wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe - attribute \src "ls180.v:1350.5-1350.40" - wire \main_sdphy_dataw_crcr_pads_in_ready - attribute \src "ls180.v:1349.6-1349.41" - wire \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:1396.5-1396.32" - wire \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:1917.5-1917.59" - wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - attribute \src "ls180.v:1918.5-1918.62" - wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:1366.5-1366.30" - wire \main_sdphy_dataw_crcr_run - attribute \src "ls180.v:1362.6-1362.48" - wire \main_sdphy_dataw_crcr_source_source_first0 - attribute \src "ls180.v:1383.6-1383.48" - wire \main_sdphy_dataw_crcr_source_source_first1 - attribute \src "ls180.v:1363.6-1363.47" - wire \main_sdphy_dataw_crcr_source_source_last0 - attribute \src "ls180.v:1384.6-1384.47" - wire \main_sdphy_dataw_crcr_source_source_last1 - attribute \src "ls180.v:1364.12-1364.61" - wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 - attribute \src "ls180.v:1385.12-1385.61" - wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 - attribute \src "ls180.v:1361.5-1361.47" - wire \main_sdphy_dataw_crcr_source_source_ready0 - attribute \src "ls180.v:1382.6-1382.48" - wire \main_sdphy_dataw_crcr_source_source_ready1 - attribute \src "ls180.v:1360.6-1360.48" - wire \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:1381.6-1381.48" - wire \main_sdphy_dataw_crcr_source_source_valid1 - attribute \src "ls180.v:1365.6-1365.33" - wire \main_sdphy_dataw_crcr_start - attribute \src "ls180.v:1348.5-1348.27" - wire \main_sdphy_dataw_error - attribute \src "ls180.v:1337.5-1337.43" - wire \main_sdphy_dataw_pads_in_pads_in_first - attribute \src "ls180.v:1338.5-1338.42" - wire \main_sdphy_dataw_pads_in_pads_in_last - attribute \src "ls180.v:1339.5-1339.49" - wire \main_sdphy_dataw_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1340.5-1340.51" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1341.5-1341.51" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1342.5-1342.52" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1343.11-1343.58" - wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1344.11-1344.58" - wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1345.5-1345.53" - wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1336.6-1336.44" - wire \main_sdphy_dataw_pads_in_pads_in_ready - attribute \src "ls180.v:1335.5-1335.43" - wire \main_sdphy_dataw_pads_in_pads_in_valid - attribute \src "ls180.v:1320.6-1320.44" - wire \main_sdphy_dataw_pads_in_payload_cmd_i - attribute \src "ls180.v:1321.12-1321.51" - wire width 4 \main_sdphy_dataw_pads_in_payload_data_i - attribute \src "ls180.v:1319.6-1319.36" - wire \main_sdphy_dataw_pads_in_valid - attribute \src "ls180.v:1323.5-1323.42" - wire \main_sdphy_dataw_pads_out_payload_clk - attribute \src "ls180.v:1324.5-1324.44" - wire \main_sdphy_dataw_pads_out_payload_cmd_o - attribute \src "ls180.v:1325.5-1325.45" - wire \main_sdphy_dataw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1326.11-1326.51" - wire width 4 \main_sdphy_dataw_pads_out_payload_data_o - attribute \src "ls180.v:1327.5-1327.46" - wire \main_sdphy_dataw_pads_out_payload_data_oe - attribute \src "ls180.v:1322.6-1322.37" - wire \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:1330.5-1330.32" - wire \main_sdphy_dataw_sink_first - attribute \src "ls180.v:1331.5-1331.31" - wire \main_sdphy_dataw_sink_last - attribute \src "ls180.v:1332.11-1332.45" - wire width 8 \main_sdphy_dataw_sink_payload_data - attribute \src "ls180.v:1329.5-1329.32" - wire \main_sdphy_dataw_sink_ready - attribute \src "ls180.v:1328.5-1328.32" - wire \main_sdphy_dataw_sink_valid - attribute \src "ls180.v:1346.5-1346.27" - wire \main_sdphy_dataw_start - attribute \src "ls180.v:1333.5-1333.26" - wire \main_sdphy_dataw_stop - attribute \src "ls180.v:1347.5-1347.27" - wire \main_sdphy_dataw_valid - attribute \src "ls180.v:1227.11-1227.32" - wire width 8 \main_sdphy_init_count - attribute \src "ls180.v:1901.11-1901.59" - wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value - attribute \src "ls180.v:1902.5-1902.56" - wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:1215.6-1215.34" - wire \main_sdphy_init_initialize_r - attribute \src "ls180.v:1214.6-1214.35" - wire \main_sdphy_init_initialize_re - attribute \src "ls180.v:1217.5-1217.33" - wire \main_sdphy_init_initialize_w - attribute \src "ls180.v:1216.6-1216.35" - wire \main_sdphy_init_initialize_we - attribute \src "ls180.v:1219.6-1219.43" - wire \main_sdphy_init_pads_in_payload_cmd_i - attribute \src "ls180.v:1220.12-1220.50" - wire width 4 \main_sdphy_init_pads_in_payload_data_i - attribute \src "ls180.v:1218.6-1218.35" - wire \main_sdphy_init_pads_in_valid - attribute \src "ls180.v:1222.5-1222.41" - wire \main_sdphy_init_pads_out_payload_clk - attribute \src "ls180.v:1223.5-1223.43" - wire \main_sdphy_init_pads_out_payload_cmd_o - attribute \src "ls180.v:1224.5-1224.44" - wire \main_sdphy_init_pads_out_payload_cmd_oe - attribute \src "ls180.v:1225.11-1225.50" - wire width 4 \main_sdphy_init_pads_out_payload_data_o - attribute \src "ls180.v:1226.5-1226.45" - wire \main_sdphy_init_pads_out_payload_data_oe - attribute \src "ls180.v:1221.6-1221.36" - wire \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:1475.6-1475.27" - wire \main_sdphy_sdpads_clk - attribute \src "ls180.v:1476.5-1476.28" - wire \main_sdphy_sdpads_cmd_i - attribute \src "ls180.v:1477.6-1477.29" - wire \main_sdphy_sdpads_cmd_o - attribute \src "ls180.v:1478.6-1478.30" - wire \main_sdphy_sdpads_cmd_oe - attribute \src "ls180.v:1479.11-1479.35" - wire width 4 \main_sdphy_sdpads_data_i - attribute \src "ls180.v:1480.12-1480.36" - wire width 4 \main_sdphy_sdpads_data_o - attribute \src "ls180.v:1481.6-1481.31" - wire \main_sdphy_sdpads_data_oe - attribute \src "ls180.v:1204.6-1204.23" - wire \main_sdphy_status - attribute \src "ls180.v:1205.6-1205.19" - wire \main_sdphy_we - attribute \src "ls180.v:421.5-421.26" - wire \main_sdram_address_re - attribute \src "ls180.v:420.12-420.38" - wire width 13 \main_sdram_address_storage - attribute \src "ls180.v:423.5-423.27" - wire \main_sdram_baddress_re - attribute \src "ls180.v:422.11-422.38" - wire width 2 \main_sdram_baddress_storage - attribute \src "ls180.v:519.5-519.43" - wire \main_sdram_bankmachine0_auto_precharge - attribute \src "ls180.v:541.11-541.63" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - attribute \src "ls180.v:546.6-546.58" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:551.6-551.64" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:552.6-552.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:550.13-550.78" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:549.6-549.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:555.6-555.65" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:556.6-556.64" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:554.13-554.79" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:553.6-553.70" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:538.11-538.61" - wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level - attribute \src "ls180.v:540.11-540.63" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - attribute \src "ls180.v:547.12-547.67" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:548.13-548.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:539.5-539.57" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:522.5-522.60" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:523.5-523.59" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:525.13-525.75" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:524.6-524.66" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:521.6-521.61" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:520.6-520.61" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:528.6-528.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:529.6-529.62" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:531.13-531.77" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:530.6-530.68" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:527.6-527.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:526.6-526.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:536.13-536.71" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - attribute \src "ls180.v:537.13-537.72" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - attribute \src "ls180.v:534.6-534.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - attribute \src "ls180.v:535.6-535.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - attribute \src "ls180.v:532.6-532.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - attribute \src "ls180.v:533.6-533.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - attribute \src "ls180.v:542.11-542.66" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:543.13-543.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:545.13-545.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:544.6-544.60" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:559.6-559.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_first - attribute \src "ls180.v:560.6-560.50" - wire \main_sdram_bankmachine0_cmd_buffer_sink_last - attribute \src "ls180.v:562.13-562.65" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:561.6-561.56" - wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - attribute \src "ls180.v:558.6-558.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_ready - attribute \src "ls180.v:557.6-557.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_valid - attribute \src "ls180.v:565.5-565.52" - wire \main_sdram_bankmachine0_cmd_buffer_source_first - attribute \src "ls180.v:566.5-566.51" - wire \main_sdram_bankmachine0_cmd_buffer_source_last - attribute \src "ls180.v:568.12-568.66" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - attribute \src "ls180.v:567.5-567.57" - wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:564.6-564.53" - wire \main_sdram_bankmachine0_cmd_buffer_source_ready - attribute \src "ls180.v:563.5-563.52" - wire \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:511.12-511.49" - wire width 13 \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:512.12-512.50" - wire width 2 \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:513.5-513.44" - wire \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:516.5-516.47" - wire \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:517.5-517.48" - wire \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:518.5-518.49" - wire \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:514.5-514.44" - wire \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:515.5-515.43" - wire \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:510.5-510.38" - wire \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:509.5-509.38" - wire \main_sdram_bankmachine0_cmd_valid - attribute \src "ls180.v:508.5-508.40" - wire \main_sdram_bankmachine0_refresh_gnt - attribute \src "ls180.v:507.6-507.41" - wire \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:503.13-503.45" - wire width 22 \main_sdram_bankmachine0_req_addr - attribute \src "ls180.v:504.6-504.38" - wire \main_sdram_bankmachine0_req_lock + attribute \src "ls180.v:482.32-482.64" + wire \sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:481.6-481.38" + wire \sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:507.5-507.38" + wire \sdram_bankmachine1_auto_precharge + attribute \src "ls180.v:529.11-529.58" + wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_consume + attribute \src "ls180.v:534.6-534.53" + wire \sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:539.6-539.59" + wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:540.6-540.58" + wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:538.13-538.73" + wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:537.6-537.64" + wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:543.6-543.60" + wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:544.6-544.59" + wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:542.13-542.74" + wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:541.6-541.65" + wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:526.11-526.56" + wire width 4 \sdram_bankmachine1_cmd_buffer_lookahead_level + attribute \src "ls180.v:528.11-528.58" + wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_produce + attribute \src "ls180.v:535.12-535.62" + wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:536.13-536.65" + wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:527.5-527.52" + wire \sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:510.5-510.55" + wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:511.5-511.54" + wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:513.13-513.70" + wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:512.6-512.61" + wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:509.6-509.56" + wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:508.6-508.56" + wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:516.6-516.58" + wire \sdram_bankmachine1_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:517.6-517.57" + wire \sdram_bankmachine1_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:519.13-519.72" + wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:518.6-518.63" + wire \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:515.6-515.58" + wire \sdram_bankmachine1_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:514.6-514.58" + wire \sdram_bankmachine1_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:524.13-524.66" + wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + attribute \src "ls180.v:525.13-525.67" + wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + attribute \src "ls180.v:522.6-522.58" + wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + attribute \src "ls180.v:523.6-523.64" + wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + attribute \src "ls180.v:520.6-520.58" + wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + attribute \src "ls180.v:521.6-521.64" + wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + attribute \src "ls180.v:530.11-530.61" + wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:531.13-531.65" + wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:533.13-533.65" + wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:532.6-532.55" + wire \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:547.6-547.46" + wire \sdram_bankmachine1_cmd_buffer_sink_first + attribute \src "ls180.v:548.6-548.45" + wire \sdram_bankmachine1_cmd_buffer_sink_last + attribute \src "ls180.v:550.13-550.60" + wire width 22 \sdram_bankmachine1_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:549.6-549.51" + wire \sdram_bankmachine1_cmd_buffer_sink_payload_we + attribute \src "ls180.v:546.6-546.46" + wire \sdram_bankmachine1_cmd_buffer_sink_ready + attribute \src "ls180.v:545.6-545.46" + wire \sdram_bankmachine1_cmd_buffer_sink_valid + attribute \src "ls180.v:553.5-553.47" + wire \sdram_bankmachine1_cmd_buffer_source_first + attribute \src "ls180.v:554.5-554.46" + wire \sdram_bankmachine1_cmd_buffer_source_last + attribute \src "ls180.v:556.12-556.61" + wire width 22 \sdram_bankmachine1_cmd_buffer_source_payload_addr + attribute \src "ls180.v:555.5-555.52" + wire \sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:552.6-552.48" + wire \sdram_bankmachine1_cmd_buffer_source_ready + attribute \src "ls180.v:551.5-551.47" + wire \sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:499.12-499.44" + wire width 13 \sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:500.12-500.45" + wire width 2 \sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:501.5-501.39" + wire \sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:504.5-504.42" + wire \sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:505.5-505.43" + wire \sdram_bankmachine1_cmd_payload_is_read attribute \src "ls180.v:506.5-506.44" - wire \main_sdram_bankmachine0_req_rdata_valid - attribute \src "ls180.v:501.6-501.39" - wire \main_sdram_bankmachine0_req_ready - attribute \src "ls180.v:500.6-500.39" - wire \main_sdram_bankmachine0_req_valid - attribute \src "ls180.v:505.5-505.44" - wire \main_sdram_bankmachine0_req_wdata_ready - attribute \src "ls180.v:502.6-502.36" - wire \main_sdram_bankmachine0_req_we - attribute \src "ls180.v:569.12-569.39" - wire width 13 \main_sdram_bankmachine0_row - attribute \src "ls180.v:573.5-573.38" - wire \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:574.5-574.47" - wire \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:571.6-571.37" - wire \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:572.5-572.37" - wire \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:570.5-570.39" - wire \main_sdram_bankmachine0_row_opened + wire \sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:502.5-502.39" + wire \sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:503.5-503.38" + wire \sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:498.5-498.33" + wire \sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:497.5-497.33" + wire \sdram_bankmachine1_cmd_valid + attribute \src "ls180.v:496.5-496.35" + wire \sdram_bankmachine1_refresh_gnt + attribute \src "ls180.v:495.6-495.36" + wire \sdram_bankmachine1_refresh_req + attribute \src "ls180.v:491.13-491.40" + wire width 22 \sdram_bankmachine1_req_addr + attribute \src "ls180.v:492.6-492.33" + wire \sdram_bankmachine1_req_lock + attribute \src "ls180.v:494.5-494.39" + wire \sdram_bankmachine1_req_rdata_valid + attribute \src "ls180.v:489.6-489.34" + wire \sdram_bankmachine1_req_ready + attribute \src "ls180.v:488.6-488.34" + wire \sdram_bankmachine1_req_valid + attribute \src "ls180.v:493.5-493.39" + wire \sdram_bankmachine1_req_wdata_ready + attribute \src "ls180.v:490.6-490.31" + wire \sdram_bankmachine1_req_we + attribute \src "ls180.v:557.12-557.34" + wire width 13 \sdram_bankmachine1_row + attribute \src "ls180.v:561.5-561.33" + wire \sdram_bankmachine1_row_close + attribute \src "ls180.v:562.5-562.42" + wire \sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:559.6-559.32" + wire \sdram_bankmachine1_row_hit + attribute \src "ls180.v:560.5-560.32" + wire \sdram_bankmachine1_row_open + attribute \src "ls180.v:558.5-558.34" + wire \sdram_bankmachine1_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:581.32-581.69" - wire \main_sdram_bankmachine0_trascon_ready - attribute \src "ls180.v:580.6-580.43" - wire \main_sdram_bankmachine0_trascon_valid + attribute \src "ls180.v:569.32-569.64" + wire \sdram_bankmachine1_trascon_ready + attribute \src "ls180.v:568.6-568.38" + wire \sdram_bankmachine1_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:579.32-579.68" - wire \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:578.6-578.42" - wire \main_sdram_bankmachine0_trccon_valid - attribute \src "ls180.v:577.11-577.48" - wire width 3 \main_sdram_bankmachine0_twtpcon_count + attribute \src "ls180.v:567.32-567.63" + wire \sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:566.6-566.37" + wire \sdram_bankmachine1_trccon_valid + attribute \src "ls180.v:565.11-565.43" + wire width 3 \sdram_bankmachine1_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:576.32-576.69" - wire \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:575.6-575.43" - wire \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:601.5-601.43" - wire \main_sdram_bankmachine1_auto_precharge - attribute \src "ls180.v:623.11-623.63" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - attribute \src "ls180.v:628.6-628.58" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:633.6-633.64" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:634.6-634.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:632.13-632.78" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:631.6-631.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:637.6-637.65" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:638.6-638.64" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:636.13-636.79" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:635.6-635.70" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:620.11-620.61" - wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level - attribute \src "ls180.v:622.11-622.63" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - attribute \src "ls180.v:629.12-629.67" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:630.13-630.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:621.5-621.57" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:604.5-604.60" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:605.5-605.59" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:607.13-607.75" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:606.6-606.66" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:603.6-603.61" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:602.6-602.61" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:610.6-610.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:611.6-611.62" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:613.13-613.77" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:612.6-612.68" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:609.6-609.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:608.6-608.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:618.13-618.71" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - attribute \src "ls180.v:619.13-619.72" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - attribute \src "ls180.v:616.6-616.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - attribute \src "ls180.v:617.6-617.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - attribute \src "ls180.v:614.6-614.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - attribute \src "ls180.v:615.6-615.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - attribute \src "ls180.v:624.11-624.66" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:625.13-625.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:627.13-627.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:626.6-626.60" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:641.6-641.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_first - attribute \src "ls180.v:642.6-642.50" - wire \main_sdram_bankmachine1_cmd_buffer_sink_last - attribute \src "ls180.v:644.13-644.65" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:643.6-643.56" - wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - attribute \src "ls180.v:640.6-640.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_ready - attribute \src "ls180.v:639.6-639.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_valid - attribute \src "ls180.v:647.5-647.52" - wire \main_sdram_bankmachine1_cmd_buffer_source_first - attribute \src "ls180.v:648.5-648.51" - wire \main_sdram_bankmachine1_cmd_buffer_source_last - attribute \src "ls180.v:650.12-650.66" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - attribute \src "ls180.v:649.5-649.57" - wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:646.6-646.53" - wire \main_sdram_bankmachine1_cmd_buffer_source_ready - attribute \src "ls180.v:645.5-645.52" - wire \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:593.12-593.49" - wire width 13 \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:594.12-594.50" - wire width 2 \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:595.5-595.44" - wire \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:598.5-598.47" - wire \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:599.5-599.48" - wire \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:600.5-600.49" - wire \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:596.5-596.44" - wire \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:597.5-597.43" - wire \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:592.5-592.38" - wire \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:591.5-591.38" - wire \main_sdram_bankmachine1_cmd_valid - attribute \src "ls180.v:590.5-590.40" - wire \main_sdram_bankmachine1_refresh_gnt - attribute \src "ls180.v:589.6-589.41" - wire \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:585.13-585.45" - wire width 22 \main_sdram_bankmachine1_req_addr - attribute \src "ls180.v:586.6-586.38" - wire \main_sdram_bankmachine1_req_lock + attribute \src "ls180.v:564.32-564.64" + wire \sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:563.6-563.38" + wire \sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:589.5-589.38" + wire \sdram_bankmachine2_auto_precharge + attribute \src "ls180.v:611.11-611.58" + wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_consume + attribute \src "ls180.v:616.6-616.53" + wire \sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:621.6-621.59" + wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:622.6-622.58" + wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:620.13-620.73" + wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:619.6-619.64" + wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:625.6-625.60" + wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:626.6-626.59" + wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:624.13-624.74" + wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:623.6-623.65" + wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:608.11-608.56" + wire width 4 \sdram_bankmachine2_cmd_buffer_lookahead_level + attribute \src "ls180.v:610.11-610.58" + wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_produce + attribute \src "ls180.v:617.12-617.62" + wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:618.13-618.65" + wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:609.5-609.52" + wire \sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:592.5-592.55" + wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:593.5-593.54" + wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:595.13-595.70" + wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:594.6-594.61" + wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:591.6-591.56" + wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:590.6-590.56" + wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:598.6-598.58" + wire \sdram_bankmachine2_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:599.6-599.57" + wire \sdram_bankmachine2_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:601.13-601.72" + wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:600.6-600.63" + wire \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:597.6-597.58" + wire \sdram_bankmachine2_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:596.6-596.58" + wire \sdram_bankmachine2_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:606.13-606.66" + wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + attribute \src "ls180.v:607.13-607.67" + wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + attribute \src "ls180.v:604.6-604.58" + wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + attribute \src "ls180.v:605.6-605.64" + wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + attribute \src "ls180.v:602.6-602.58" + wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + attribute \src "ls180.v:603.6-603.64" + wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + attribute \src "ls180.v:612.11-612.61" + wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:613.13-613.65" + wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:615.13-615.65" + wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:614.6-614.55" + wire \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:629.6-629.46" + wire \sdram_bankmachine2_cmd_buffer_sink_first + attribute \src "ls180.v:630.6-630.45" + wire \sdram_bankmachine2_cmd_buffer_sink_last + attribute \src "ls180.v:632.13-632.60" + wire width 22 \sdram_bankmachine2_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:631.6-631.51" + wire \sdram_bankmachine2_cmd_buffer_sink_payload_we + attribute \src "ls180.v:628.6-628.46" + wire \sdram_bankmachine2_cmd_buffer_sink_ready + attribute \src "ls180.v:627.6-627.46" + wire \sdram_bankmachine2_cmd_buffer_sink_valid + attribute \src "ls180.v:635.5-635.47" + wire \sdram_bankmachine2_cmd_buffer_source_first + attribute \src "ls180.v:636.5-636.46" + wire \sdram_bankmachine2_cmd_buffer_source_last + attribute \src "ls180.v:638.12-638.61" + wire width 22 \sdram_bankmachine2_cmd_buffer_source_payload_addr + attribute \src "ls180.v:637.5-637.52" + wire \sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:634.6-634.48" + wire \sdram_bankmachine2_cmd_buffer_source_ready + attribute \src "ls180.v:633.5-633.47" + wire \sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:581.12-581.44" + wire width 13 \sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:582.12-582.45" + wire width 2 \sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:583.5-583.39" + wire \sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:586.5-586.42" + wire \sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:587.5-587.43" + wire \sdram_bankmachine2_cmd_payload_is_read attribute \src "ls180.v:588.5-588.44" - wire \main_sdram_bankmachine1_req_rdata_valid - attribute \src "ls180.v:583.6-583.39" - wire \main_sdram_bankmachine1_req_ready - attribute \src "ls180.v:582.6-582.39" - wire \main_sdram_bankmachine1_req_valid - attribute \src "ls180.v:587.5-587.44" - wire \main_sdram_bankmachine1_req_wdata_ready - attribute \src "ls180.v:584.6-584.36" - wire \main_sdram_bankmachine1_req_we - attribute \src "ls180.v:651.12-651.39" - wire width 13 \main_sdram_bankmachine1_row - attribute \src "ls180.v:655.5-655.38" - wire \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:656.5-656.47" - wire \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:653.6-653.37" - wire \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:654.5-654.37" - wire \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:652.5-652.39" - wire \main_sdram_bankmachine1_row_opened + wire \sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:584.5-584.39" + wire \sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:585.5-585.38" + wire \sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:580.5-580.33" + wire \sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:579.5-579.33" + wire \sdram_bankmachine2_cmd_valid + attribute \src "ls180.v:578.5-578.35" + wire \sdram_bankmachine2_refresh_gnt + attribute \src "ls180.v:577.6-577.36" + wire \sdram_bankmachine2_refresh_req + attribute \src "ls180.v:573.13-573.40" + wire width 22 \sdram_bankmachine2_req_addr + attribute \src "ls180.v:574.6-574.33" + wire \sdram_bankmachine2_req_lock + attribute \src "ls180.v:576.5-576.39" + wire \sdram_bankmachine2_req_rdata_valid + attribute \src "ls180.v:571.6-571.34" + wire \sdram_bankmachine2_req_ready + attribute \src "ls180.v:570.6-570.34" + wire \sdram_bankmachine2_req_valid + attribute \src "ls180.v:575.5-575.39" + wire \sdram_bankmachine2_req_wdata_ready + attribute \src "ls180.v:572.6-572.31" + wire \sdram_bankmachine2_req_we + attribute \src "ls180.v:639.12-639.34" + wire width 13 \sdram_bankmachine2_row + attribute \src "ls180.v:643.5-643.33" + wire \sdram_bankmachine2_row_close + attribute \src "ls180.v:644.5-644.42" + wire \sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:641.6-641.32" + wire \sdram_bankmachine2_row_hit + attribute \src "ls180.v:642.5-642.32" + wire \sdram_bankmachine2_row_open + attribute \src "ls180.v:640.5-640.34" + wire \sdram_bankmachine2_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:663.32-663.69" - wire \main_sdram_bankmachine1_trascon_ready - attribute \src "ls180.v:662.6-662.43" - wire \main_sdram_bankmachine1_trascon_valid + attribute \src "ls180.v:651.32-651.64" + wire \sdram_bankmachine2_trascon_ready + attribute \src "ls180.v:650.6-650.38" + wire \sdram_bankmachine2_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:661.32-661.68" - wire \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:660.6-660.42" - wire \main_sdram_bankmachine1_trccon_valid - attribute \src "ls180.v:659.11-659.48" - wire width 3 \main_sdram_bankmachine1_twtpcon_count + attribute \src "ls180.v:649.32-649.63" + wire \sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:648.6-648.37" + wire \sdram_bankmachine2_trccon_valid + attribute \src "ls180.v:647.11-647.43" + wire width 3 \sdram_bankmachine2_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:658.32-658.69" - wire \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:657.6-657.43" - wire \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:683.5-683.43" - wire \main_sdram_bankmachine2_auto_precharge - attribute \src "ls180.v:705.11-705.63" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - attribute \src "ls180.v:710.6-710.58" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:715.6-715.64" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:716.6-716.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:714.13-714.78" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:713.6-713.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:719.6-719.65" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:720.6-720.64" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:718.13-718.79" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:717.6-717.70" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:702.11-702.61" - wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level - attribute \src "ls180.v:704.11-704.63" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - attribute \src "ls180.v:711.12-711.67" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:712.13-712.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:703.5-703.57" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:686.5-686.60" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:687.5-687.59" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:689.13-689.75" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:688.6-688.66" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:685.6-685.61" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:684.6-684.61" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:692.6-692.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:693.6-693.62" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:695.13-695.77" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:694.6-694.68" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:691.6-691.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:690.6-690.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:700.13-700.71" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - attribute \src "ls180.v:701.13-701.72" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - attribute \src "ls180.v:698.6-698.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - attribute \src "ls180.v:699.6-699.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - attribute \src "ls180.v:696.6-696.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - attribute \src "ls180.v:697.6-697.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - attribute \src "ls180.v:706.11-706.66" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:707.13-707.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:709.13-709.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:708.6-708.60" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:723.6-723.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_first - attribute \src "ls180.v:724.6-724.50" - wire \main_sdram_bankmachine2_cmd_buffer_sink_last - attribute \src "ls180.v:726.13-726.65" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:725.6-725.56" - wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - attribute \src "ls180.v:722.6-722.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_ready - attribute \src "ls180.v:721.6-721.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_valid - attribute \src "ls180.v:729.5-729.52" - wire \main_sdram_bankmachine2_cmd_buffer_source_first - attribute \src "ls180.v:730.5-730.51" - wire \main_sdram_bankmachine2_cmd_buffer_source_last - attribute \src "ls180.v:732.12-732.66" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - attribute \src "ls180.v:731.5-731.57" - wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:728.6-728.53" - wire \main_sdram_bankmachine2_cmd_buffer_source_ready - attribute \src "ls180.v:727.5-727.52" - wire \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:675.12-675.49" - wire width 13 \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:676.12-676.50" - wire width 2 \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:677.5-677.44" - wire \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:680.5-680.47" - wire \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:681.5-681.48" - wire \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:682.5-682.49" - wire \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:678.5-678.44" - wire \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:679.5-679.43" - wire \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:674.5-674.38" - wire \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:673.5-673.38" - wire \main_sdram_bankmachine2_cmd_valid - attribute \src "ls180.v:672.5-672.40" - wire \main_sdram_bankmachine2_refresh_gnt - attribute \src "ls180.v:671.6-671.41" - wire \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:667.13-667.45" - wire width 22 \main_sdram_bankmachine2_req_addr - attribute \src "ls180.v:668.6-668.38" - wire \main_sdram_bankmachine2_req_lock + attribute \src "ls180.v:646.32-646.64" + wire \sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:645.6-645.38" + wire \sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:671.5-671.38" + wire \sdram_bankmachine3_auto_precharge + attribute \src "ls180.v:693.11-693.58" + wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_consume + attribute \src "ls180.v:698.6-698.53" + wire \sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:703.6-703.59" + wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:704.6-704.58" + wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:702.13-702.73" + wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:701.6-701.64" + wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:707.6-707.60" + wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:708.6-708.59" + wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:706.13-706.74" + wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:705.6-705.65" + wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:690.11-690.56" + wire width 4 \sdram_bankmachine3_cmd_buffer_lookahead_level + attribute \src "ls180.v:692.11-692.58" + wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_produce + attribute \src "ls180.v:699.12-699.62" + wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:700.13-700.65" + wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:691.5-691.52" + wire \sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:674.5-674.55" + wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:675.5-675.54" + wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:677.13-677.70" + wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:676.6-676.61" + wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:673.6-673.56" + wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:672.6-672.56" + wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:680.6-680.58" + wire \sdram_bankmachine3_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:681.6-681.57" + wire \sdram_bankmachine3_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:683.13-683.72" + wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:682.6-682.63" + wire \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:679.6-679.58" + wire \sdram_bankmachine3_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:678.6-678.58" + wire \sdram_bankmachine3_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:688.13-688.66" + wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + attribute \src "ls180.v:689.13-689.67" + wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + attribute \src "ls180.v:686.6-686.58" + wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + attribute \src "ls180.v:687.6-687.64" + wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + attribute \src "ls180.v:684.6-684.58" + wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + attribute \src "ls180.v:685.6-685.64" + wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + attribute \src "ls180.v:694.11-694.61" + wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:695.13-695.65" + wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:697.13-697.65" + wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:696.6-696.55" + wire \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:711.6-711.46" + wire \sdram_bankmachine3_cmd_buffer_sink_first + attribute \src "ls180.v:712.6-712.45" + wire \sdram_bankmachine3_cmd_buffer_sink_last + attribute \src "ls180.v:714.13-714.60" + wire width 22 \sdram_bankmachine3_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:713.6-713.51" + wire \sdram_bankmachine3_cmd_buffer_sink_payload_we + attribute \src "ls180.v:710.6-710.46" + wire \sdram_bankmachine3_cmd_buffer_sink_ready + attribute \src "ls180.v:709.6-709.46" + wire \sdram_bankmachine3_cmd_buffer_sink_valid + attribute \src "ls180.v:717.5-717.47" + wire \sdram_bankmachine3_cmd_buffer_source_first + attribute \src "ls180.v:718.5-718.46" + wire \sdram_bankmachine3_cmd_buffer_source_last + attribute \src "ls180.v:720.12-720.61" + wire width 22 \sdram_bankmachine3_cmd_buffer_source_payload_addr + attribute \src "ls180.v:719.5-719.52" + wire \sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:716.6-716.48" + wire \sdram_bankmachine3_cmd_buffer_source_ready + attribute \src "ls180.v:715.5-715.47" + wire \sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:663.12-663.44" + wire width 13 \sdram_bankmachine3_cmd_payload_a + attribute \src "ls180.v:664.12-664.45" + wire width 2 \sdram_bankmachine3_cmd_payload_ba + attribute \src "ls180.v:665.5-665.39" + wire \sdram_bankmachine3_cmd_payload_cas + attribute \src "ls180.v:668.5-668.42" + wire \sdram_bankmachine3_cmd_payload_is_cmd + attribute \src "ls180.v:669.5-669.43" + wire \sdram_bankmachine3_cmd_payload_is_read attribute \src "ls180.v:670.5-670.44" - wire \main_sdram_bankmachine2_req_rdata_valid - attribute \src "ls180.v:665.6-665.39" - wire \main_sdram_bankmachine2_req_ready - attribute \src "ls180.v:664.6-664.39" - wire \main_sdram_bankmachine2_req_valid - attribute \src "ls180.v:669.5-669.44" - wire \main_sdram_bankmachine2_req_wdata_ready - attribute \src "ls180.v:666.6-666.36" - wire \main_sdram_bankmachine2_req_we - attribute \src "ls180.v:733.12-733.39" - wire width 13 \main_sdram_bankmachine2_row - attribute \src "ls180.v:737.5-737.38" - wire \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:738.5-738.47" - wire \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:735.6-735.37" - wire \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:736.5-736.37" - wire \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:734.5-734.39" - wire \main_sdram_bankmachine2_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:745.32-745.69" - wire \main_sdram_bankmachine2_trascon_ready - attribute \src "ls180.v:744.6-744.43" - wire \main_sdram_bankmachine2_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:743.32-743.68" - wire \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:742.6-742.42" - wire \main_sdram_bankmachine2_trccon_valid - attribute \src "ls180.v:741.11-741.48" - wire width 3 \main_sdram_bankmachine2_twtpcon_count + wire \sdram_bankmachine3_cmd_payload_is_write + attribute \src "ls180.v:666.5-666.39" + wire \sdram_bankmachine3_cmd_payload_ras + attribute \src "ls180.v:667.5-667.38" + wire \sdram_bankmachine3_cmd_payload_we + attribute \src "ls180.v:662.5-662.33" + wire \sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:661.5-661.33" + wire \sdram_bankmachine3_cmd_valid + attribute \src "ls180.v:660.5-660.35" + wire \sdram_bankmachine3_refresh_gnt + attribute \src "ls180.v:659.6-659.36" + wire \sdram_bankmachine3_refresh_req + attribute \src "ls180.v:655.13-655.40" + wire width 22 \sdram_bankmachine3_req_addr + attribute \src "ls180.v:656.6-656.33" + wire \sdram_bankmachine3_req_lock + attribute \src "ls180.v:658.5-658.39" + wire \sdram_bankmachine3_req_rdata_valid + attribute \src "ls180.v:653.6-653.34" + wire \sdram_bankmachine3_req_ready + attribute \src "ls180.v:652.6-652.34" + wire \sdram_bankmachine3_req_valid + attribute \src "ls180.v:657.5-657.39" + wire \sdram_bankmachine3_req_wdata_ready + attribute \src "ls180.v:654.6-654.31" + wire \sdram_bankmachine3_req_we + attribute \src "ls180.v:721.12-721.34" + wire width 13 \sdram_bankmachine3_row + attribute \src "ls180.v:725.5-725.33" + wire \sdram_bankmachine3_row_close + attribute \src "ls180.v:726.5-726.42" + wire \sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:723.6-723.32" + wire \sdram_bankmachine3_row_hit + attribute \src "ls180.v:724.5-724.32" + wire \sdram_bankmachine3_row_open + attribute \src "ls180.v:722.5-722.34" + wire \sdram_bankmachine3_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:740.32-740.69" - wire \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:739.6-739.43" - wire \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:765.5-765.43" - wire \main_sdram_bankmachine3_auto_precharge - attribute \src "ls180.v:787.11-787.63" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - attribute \src "ls180.v:792.6-792.58" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:797.6-797.64" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:798.6-798.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:796.13-796.78" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:795.6-795.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:801.6-801.65" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:802.6-802.64" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:800.13-800.79" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:799.6-799.70" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:784.11-784.61" - wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level - attribute \src "ls180.v:786.11-786.63" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - attribute \src "ls180.v:793.12-793.67" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:794.13-794.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:785.5-785.57" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:768.5-768.60" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:769.5-769.59" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:771.13-771.75" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:770.6-770.66" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:767.6-767.61" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:766.6-766.61" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:774.6-774.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:775.6-775.62" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:777.13-777.77" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:776.6-776.68" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:773.6-773.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:772.6-772.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:782.13-782.71" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - attribute \src "ls180.v:783.13-783.72" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - attribute \src "ls180.v:780.6-780.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - attribute \src "ls180.v:781.6-781.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - attribute \src "ls180.v:778.6-778.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - attribute \src "ls180.v:779.6-779.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - attribute \src "ls180.v:788.11-788.66" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:789.13-789.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:791.13-791.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:790.6-790.60" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:805.6-805.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_first - attribute \src "ls180.v:806.6-806.50" - wire \main_sdram_bankmachine3_cmd_buffer_sink_last - attribute \src "ls180.v:808.13-808.65" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:807.6-807.56" - wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - attribute \src "ls180.v:804.6-804.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_ready - attribute \src "ls180.v:803.6-803.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_valid - attribute \src "ls180.v:811.5-811.52" - wire \main_sdram_bankmachine3_cmd_buffer_source_first - attribute \src "ls180.v:812.5-812.51" - wire \main_sdram_bankmachine3_cmd_buffer_source_last - attribute \src "ls180.v:814.12-814.66" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - attribute \src "ls180.v:813.5-813.57" - wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:810.6-810.53" - wire \main_sdram_bankmachine3_cmd_buffer_source_ready - attribute \src "ls180.v:809.5-809.52" - wire \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:757.12-757.49" - wire width 13 \main_sdram_bankmachine3_cmd_payload_a - attribute \src "ls180.v:758.12-758.50" - wire width 2 \main_sdram_bankmachine3_cmd_payload_ba - attribute \src "ls180.v:759.5-759.44" - wire \main_sdram_bankmachine3_cmd_payload_cas - attribute \src "ls180.v:762.5-762.47" - wire \main_sdram_bankmachine3_cmd_payload_is_cmd - attribute \src "ls180.v:763.5-763.48" - wire \main_sdram_bankmachine3_cmd_payload_is_read - attribute \src "ls180.v:764.5-764.49" - wire \main_sdram_bankmachine3_cmd_payload_is_write - attribute \src "ls180.v:760.5-760.44" - wire \main_sdram_bankmachine3_cmd_payload_ras - attribute \src "ls180.v:761.5-761.43" - wire \main_sdram_bankmachine3_cmd_payload_we - attribute \src "ls180.v:756.5-756.38" - wire \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:755.5-755.38" - wire \main_sdram_bankmachine3_cmd_valid - attribute \src "ls180.v:754.5-754.40" - wire \main_sdram_bankmachine3_refresh_gnt - attribute \src "ls180.v:753.6-753.41" - wire \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:749.13-749.45" - wire width 22 \main_sdram_bankmachine3_req_addr - attribute \src "ls180.v:750.6-750.38" - wire \main_sdram_bankmachine3_req_lock - attribute \src "ls180.v:752.5-752.44" - wire \main_sdram_bankmachine3_req_rdata_valid - attribute \src "ls180.v:747.6-747.39" - wire \main_sdram_bankmachine3_req_ready - attribute \src "ls180.v:746.6-746.39" - wire \main_sdram_bankmachine3_req_valid - attribute \src "ls180.v:751.5-751.44" - wire \main_sdram_bankmachine3_req_wdata_ready - attribute \src "ls180.v:748.6-748.36" - wire \main_sdram_bankmachine3_req_we - attribute \src "ls180.v:815.12-815.39" - wire width 13 \main_sdram_bankmachine3_row - attribute \src "ls180.v:819.5-819.38" - wire \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:820.5-820.47" - wire \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:817.6-817.37" - wire \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:818.5-818.37" - wire \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:816.5-816.39" - wire \main_sdram_bankmachine3_row_opened + attribute \src "ls180.v:733.32-733.64" + wire \sdram_bankmachine3_trascon_ready + attribute \src "ls180.v:732.6-732.38" + wire \sdram_bankmachine3_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:827.32-827.69" - wire \main_sdram_bankmachine3_trascon_ready - attribute \src "ls180.v:826.6-826.43" - wire \main_sdram_bankmachine3_trascon_valid + attribute \src "ls180.v:731.32-731.63" + wire \sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:730.6-730.37" + wire \sdram_bankmachine3_trccon_valid + attribute \src "ls180.v:729.11-729.43" + wire width 3 \sdram_bankmachine3_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:825.32-825.68" - wire \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:824.6-824.42" - wire \main_sdram_bankmachine3_trccon_valid - attribute \src "ls180.v:823.11-823.48" - wire width 3 \main_sdram_bankmachine3_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:822.32-822.69" - wire \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:821.6-821.43" - wire \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:829.6-829.28" - wire \main_sdram_cas_allowed - attribute \src "ls180.v:847.6-847.30" - wire \main_sdram_choose_cmd_ce - attribute \src "ls180.v:836.13-836.48" - wire width 13 \main_sdram_choose_cmd_cmd_payload_a - attribute \src "ls180.v:837.12-837.48" - wire width 2 \main_sdram_choose_cmd_cmd_payload_ba - attribute \src "ls180.v:838.5-838.42" - wire \main_sdram_choose_cmd_cmd_payload_cas - attribute \src "ls180.v:841.6-841.46" - wire \main_sdram_choose_cmd_cmd_payload_is_cmd - attribute \src "ls180.v:842.6-842.47" - wire \main_sdram_choose_cmd_cmd_payload_is_read - attribute \src "ls180.v:843.6-843.48" - wire \main_sdram_choose_cmd_cmd_payload_is_write - attribute \src "ls180.v:839.5-839.42" - wire \main_sdram_choose_cmd_cmd_payload_ras - attribute \src "ls180.v:840.5-840.41" - wire \main_sdram_choose_cmd_cmd_payload_we - attribute \src "ls180.v:835.5-835.36" - wire \main_sdram_choose_cmd_cmd_ready - attribute \src "ls180.v:834.6-834.37" - wire \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:846.11-846.38" - wire width 2 \main_sdram_choose_cmd_grant - attribute \src "ls180.v:845.12-845.41" - wire width 4 \main_sdram_choose_cmd_request - attribute \src "ls180.v:844.11-844.39" - wire width 4 \main_sdram_choose_cmd_valids - attribute \src "ls180.v:833.5-833.41" - wire \main_sdram_choose_cmd_want_activates - attribute \src "ls180.v:832.5-832.36" - wire \main_sdram_choose_cmd_want_cmds - attribute \src "ls180.v:830.5-830.37" - wire \main_sdram_choose_cmd_want_reads - attribute \src "ls180.v:831.5-831.38" - wire \main_sdram_choose_cmd_want_writes - attribute \src "ls180.v:865.6-865.30" - wire \main_sdram_choose_req_ce - attribute \src "ls180.v:854.13-854.48" - wire width 13 \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:855.12-855.48" - wire width 2 \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:856.5-856.42" - wire \main_sdram_choose_req_cmd_payload_cas - attribute \src "ls180.v:859.6-859.46" - wire \main_sdram_choose_req_cmd_payload_is_cmd - attribute \src "ls180.v:860.6-860.47" - wire \main_sdram_choose_req_cmd_payload_is_read - attribute \src "ls180.v:861.6-861.48" - wire \main_sdram_choose_req_cmd_payload_is_write - attribute \src "ls180.v:857.5-857.42" - wire \main_sdram_choose_req_cmd_payload_ras - attribute \src "ls180.v:858.5-858.41" - wire \main_sdram_choose_req_cmd_payload_we - attribute \src "ls180.v:853.5-853.36" - wire \main_sdram_choose_req_cmd_ready - attribute \src "ls180.v:852.6-852.37" - wire \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:864.11-864.38" - wire width 2 \main_sdram_choose_req_grant - attribute \src "ls180.v:863.12-863.41" - wire width 4 \main_sdram_choose_req_request - attribute \src "ls180.v:862.11-862.39" - wire width 4 \main_sdram_choose_req_valids - attribute \src "ls180.v:851.5-851.41" - wire \main_sdram_choose_req_want_activates - attribute \src "ls180.v:850.6-850.37" - wire \main_sdram_choose_req_want_cmds - attribute \src "ls180.v:848.5-848.37" - wire \main_sdram_choose_req_want_reads - attribute \src "ls180.v:849.5-849.38" - wire \main_sdram_choose_req_want_writes - attribute \src "ls180.v:409.6-409.20" - wire \main_sdram_cke - attribute \src "ls180.v:477.5-477.24" - wire \main_sdram_cmd_last - attribute \src "ls180.v:478.12-478.36" - wire width 13 \main_sdram_cmd_payload_a - attribute \src "ls180.v:479.11-479.36" - wire width 2 \main_sdram_cmd_payload_ba - attribute \src "ls180.v:480.5-480.31" - wire \main_sdram_cmd_payload_cas - attribute \src "ls180.v:483.5-483.35" - wire \main_sdram_cmd_payload_is_read - attribute \src "ls180.v:484.5-484.36" - wire \main_sdram_cmd_payload_is_write - attribute \src "ls180.v:481.5-481.31" - wire \main_sdram_cmd_payload_ras - attribute \src "ls180.v:482.5-482.30" - wire \main_sdram_cmd_payload_we - attribute \src "ls180.v:476.5-476.25" - wire \main_sdram_cmd_ready - attribute \src "ls180.v:475.5-475.25" - wire \main_sdram_cmd_valid - attribute \src "ls180.v:417.6-417.32" - wire \main_sdram_command_issue_r - attribute \src "ls180.v:416.6-416.33" - wire \main_sdram_command_issue_re - attribute \src "ls180.v:419.5-419.31" - wire \main_sdram_command_issue_w - attribute \src "ls180.v:418.6-418.33" - wire \main_sdram_command_issue_we - attribute \src "ls180.v:415.5-415.26" - wire \main_sdram_command_re - attribute \src "ls180.v:414.11-414.37" - wire width 6 \main_sdram_command_storage - attribute \src "ls180.v:468.5-468.28" - wire \main_sdram_dfi_p0_act_n - attribute \src "ls180.v:459.12-459.37" - wire width 13 \main_sdram_dfi_p0_address - attribute \src "ls180.v:460.11-460.33" - wire width 2 \main_sdram_dfi_p0_bank - attribute \src "ls180.v:461.5-461.28" - wire \main_sdram_dfi_p0_cas_n - attribute \src "ls180.v:465.6-465.27" - wire \main_sdram_dfi_p0_cke - attribute \src "ls180.v:462.5-462.27" - wire \main_sdram_dfi_p0_cs_n - attribute \src "ls180.v:466.6-466.27" - wire \main_sdram_dfi_p0_odt - attribute \src "ls180.v:463.5-463.28" - wire \main_sdram_dfi_p0_ras_n - attribute \src "ls180.v:473.13-473.37" - wire width 16 \main_sdram_dfi_p0_rddata - attribute \src "ls180.v:472.5-472.32" - wire \main_sdram_dfi_p0_rddata_en - attribute \src "ls180.v:474.6-474.36" - wire \main_sdram_dfi_p0_rddata_valid - attribute \src "ls180.v:467.6-467.31" - wire \main_sdram_dfi_p0_reset_n - attribute \src "ls180.v:464.5-464.27" - wire \main_sdram_dfi_p0_we_n - attribute \src "ls180.v:469.13-469.37" - wire width 16 \main_sdram_dfi_p0_wrdata - attribute \src "ls180.v:470.5-470.32" - wire \main_sdram_dfi_p0_wrdata_en - attribute \src "ls180.v:471.12-471.41" - wire width 2 \main_sdram_dfi_p0_wrdata_mask - attribute \src "ls180.v:883.5-883.19" - wire \main_sdram_en0 - attribute \src "ls180.v:886.5-886.19" - wire \main_sdram_en1 - attribute \src "ls180.v:889.6-889.30" - wire \main_sdram_go_to_refresh - attribute \src "ls180.v:431.13-431.44" - wire width 22 \main_sdram_interface_bank0_addr - attribute \src "ls180.v:432.6-432.37" - wire \main_sdram_interface_bank0_lock - attribute \src "ls180.v:434.6-434.44" - wire \main_sdram_interface_bank0_rdata_valid - attribute \src "ls180.v:429.6-429.38" - wire \main_sdram_interface_bank0_ready - attribute \src "ls180.v:428.6-428.38" - wire \main_sdram_interface_bank0_valid - attribute \src "ls180.v:433.6-433.44" - wire \main_sdram_interface_bank0_wdata_ready - attribute \src "ls180.v:430.6-430.35" - wire \main_sdram_interface_bank0_we - attribute \src "ls180.v:438.13-438.44" - wire width 22 \main_sdram_interface_bank1_addr - attribute \src "ls180.v:439.6-439.37" - wire \main_sdram_interface_bank1_lock - attribute \src "ls180.v:441.6-441.44" - wire \main_sdram_interface_bank1_rdata_valid - attribute \src "ls180.v:436.6-436.38" - wire \main_sdram_interface_bank1_ready - attribute \src "ls180.v:435.6-435.38" - wire \main_sdram_interface_bank1_valid - attribute \src "ls180.v:440.6-440.44" - wire \main_sdram_interface_bank1_wdata_ready - attribute \src "ls180.v:437.6-437.35" - wire \main_sdram_interface_bank1_we - attribute \src "ls180.v:445.13-445.44" - wire width 22 \main_sdram_interface_bank2_addr - attribute \src "ls180.v:446.6-446.37" - wire \main_sdram_interface_bank2_lock - attribute \src "ls180.v:448.6-448.44" - wire \main_sdram_interface_bank2_rdata_valid - attribute \src "ls180.v:443.6-443.38" - wire \main_sdram_interface_bank2_ready - attribute \src "ls180.v:442.6-442.38" - wire \main_sdram_interface_bank2_valid - attribute \src "ls180.v:447.6-447.44" - wire \main_sdram_interface_bank2_wdata_ready - attribute \src "ls180.v:444.6-444.35" - wire \main_sdram_interface_bank2_we - attribute \src "ls180.v:452.13-452.44" - wire width 22 \main_sdram_interface_bank3_addr - attribute \src "ls180.v:453.6-453.37" - wire \main_sdram_interface_bank3_lock - attribute \src "ls180.v:455.6-455.44" - wire \main_sdram_interface_bank3_rdata_valid - attribute \src "ls180.v:450.6-450.38" - wire \main_sdram_interface_bank3_ready - attribute \src "ls180.v:449.6-449.38" - wire \main_sdram_interface_bank3_valid - attribute \src "ls180.v:454.6-454.44" - wire \main_sdram_interface_bank3_wdata_ready - attribute \src "ls180.v:451.6-451.35" - wire \main_sdram_interface_bank3_we - attribute \src "ls180.v:458.13-458.39" - wire width 16 \main_sdram_interface_rdata - attribute \src "ls180.v:456.12-456.38" - wire width 16 \main_sdram_interface_wdata - attribute \src "ls180.v:457.11-457.40" - wire width 2 \main_sdram_interface_wdata_we - attribute \src "ls180.v:369.5-369.29" - wire \main_sdram_inti_p0_act_n - attribute \src "ls180.v:360.13-360.39" - wire width 13 \main_sdram_inti_p0_address - attribute \src "ls180.v:361.12-361.35" - wire width 2 \main_sdram_inti_p0_bank - attribute \src "ls180.v:362.5-362.29" - wire \main_sdram_inti_p0_cas_n - attribute \src "ls180.v:366.6-366.28" - wire \main_sdram_inti_p0_cke - attribute \src "ls180.v:363.5-363.28" - wire \main_sdram_inti_p0_cs_n - attribute \src "ls180.v:367.6-367.28" - wire \main_sdram_inti_p0_odt - attribute \src "ls180.v:364.5-364.29" - wire \main_sdram_inti_p0_ras_n - attribute \src "ls180.v:374.12-374.37" - wire width 16 \main_sdram_inti_p0_rddata - attribute \src "ls180.v:373.6-373.34" - wire \main_sdram_inti_p0_rddata_en - attribute \src "ls180.v:375.5-375.36" - wire \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:368.6-368.32" - wire \main_sdram_inti_p0_reset_n - attribute \src "ls180.v:365.5-365.28" - wire \main_sdram_inti_p0_we_n - attribute \src "ls180.v:370.13-370.38" - wire width 16 \main_sdram_inti_p0_wrdata - attribute \src "ls180.v:371.6-371.34" - wire \main_sdram_inti_p0_wrdata_en - attribute \src "ls180.v:372.12-372.42" - wire width 2 \main_sdram_inti_p0_wrdata_mask - attribute \src "ls180.v:401.5-401.31" - wire \main_sdram_master_p0_act_n - attribute \src "ls180.v:392.12-392.40" - wire width 13 \main_sdram_master_p0_address - attribute \src "ls180.v:393.11-393.36" - wire width 2 \main_sdram_master_p0_bank - attribute \src "ls180.v:394.5-394.31" - wire \main_sdram_master_p0_cas_n - attribute \src "ls180.v:398.5-398.29" - wire \main_sdram_master_p0_cke - attribute \src "ls180.v:395.5-395.30" - wire \main_sdram_master_p0_cs_n - attribute \src "ls180.v:399.5-399.29" - wire \main_sdram_master_p0_odt - attribute \src "ls180.v:396.5-396.31" - wire \main_sdram_master_p0_ras_n - attribute \src "ls180.v:406.13-406.40" - wire width 16 \main_sdram_master_p0_rddata - attribute \src "ls180.v:405.5-405.35" - wire \main_sdram_master_p0_rddata_en - attribute \src "ls180.v:407.6-407.39" - wire \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:400.5-400.33" - wire \main_sdram_master_p0_reset_n - attribute \src "ls180.v:397.5-397.30" - wire \main_sdram_master_p0_we_n - attribute \src "ls180.v:402.12-402.39" - wire width 16 \main_sdram_master_p0_wrdata - attribute \src "ls180.v:403.5-403.35" - wire \main_sdram_master_p0_wrdata_en - attribute \src "ls180.v:404.11-404.43" - wire width 2 \main_sdram_master_p0_wrdata_mask - attribute \src "ls180.v:884.6-884.26" - wire \main_sdram_max_time0 - attribute \src "ls180.v:887.6-887.26" - wire \main_sdram_max_time1 - attribute \src "ls180.v:866.12-866.28" - wire width 13 \main_sdram_nop_a - attribute \src "ls180.v:867.11-867.28" - wire width 2 \main_sdram_nop_ba - attribute \src "ls180.v:410.6-410.20" - wire \main_sdram_odt - attribute \src "ls180.v:493.5-493.31" - wire \main_sdram_postponer_count - attribute \src "ls180.v:491.6-491.32" - wire \main_sdram_postponer_req_i - attribute \src "ls180.v:492.5-492.31" - wire \main_sdram_postponer_req_o - attribute \src "ls180.v:828.6-828.28" - wire \main_sdram_ras_allowed - attribute \src "ls180.v:413.5-413.18" - wire \main_sdram_re - attribute \src "ls180.v:881.6-881.31" - wire \main_sdram_read_available - attribute \src "ls180.v:411.6-411.24" - wire \main_sdram_reset_n - attribute \src "ls180.v:408.6-408.20" - wire \main_sdram_sel - attribute \src "ls180.v:499.5-499.31" - wire \main_sdram_sequencer_count - attribute \src "ls180.v:498.11-498.39" - wire width 4 \main_sdram_sequencer_counter - attribute \src "ls180.v:495.6-495.32" - wire \main_sdram_sequencer_done0 - attribute \src "ls180.v:497.5-497.31" - wire \main_sdram_sequencer_done1 - attribute \src "ls180.v:494.5-494.32" - wire \main_sdram_sequencer_start0 - attribute \src "ls180.v:496.6-496.33" - wire \main_sdram_sequencer_start1 - attribute \src "ls180.v:385.6-385.31" - wire \main_sdram_slave_p0_act_n - attribute \src "ls180.v:376.13-376.40" - wire width 13 \main_sdram_slave_p0_address - attribute \src "ls180.v:377.12-377.36" - wire width 2 \main_sdram_slave_p0_bank - attribute \src "ls180.v:378.6-378.31" - wire \main_sdram_slave_p0_cas_n - attribute \src "ls180.v:382.6-382.29" - wire \main_sdram_slave_p0_cke - attribute \src "ls180.v:379.6-379.30" - wire \main_sdram_slave_p0_cs_n - attribute \src "ls180.v:383.6-383.29" - wire \main_sdram_slave_p0_odt + attribute \src "ls180.v:728.32-728.64" + wire \sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:727.6-727.38" + wire \sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:735.6-735.23" + wire \sdram_cas_allowed + attribute \src "ls180.v:24.14-24.25" + wire output 20 \sdram_cas_n + attribute \src "ls180.v:753.6-753.25" + wire \sdram_choose_cmd_ce + attribute \src "ls180.v:742.13-742.43" + wire width 13 \sdram_choose_cmd_cmd_payload_a + attribute \src "ls180.v:743.12-743.43" + wire width 2 \sdram_choose_cmd_cmd_payload_ba + attribute \src "ls180.v:744.5-744.37" + wire \sdram_choose_cmd_cmd_payload_cas + attribute \src "ls180.v:747.6-747.41" + wire \sdram_choose_cmd_cmd_payload_is_cmd + attribute \src "ls180.v:748.6-748.42" + wire \sdram_choose_cmd_cmd_payload_is_read + attribute \src "ls180.v:749.6-749.43" + wire \sdram_choose_cmd_cmd_payload_is_write + attribute \src "ls180.v:745.5-745.37" + wire \sdram_choose_cmd_cmd_payload_ras + attribute \src "ls180.v:746.5-746.36" + wire \sdram_choose_cmd_cmd_payload_we + attribute \src "ls180.v:741.5-741.31" + wire \sdram_choose_cmd_cmd_ready + attribute \src "ls180.v:740.6-740.32" + wire \sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:752.11-752.33" + wire width 2 \sdram_choose_cmd_grant + attribute \src "ls180.v:751.12-751.36" + wire width 4 \sdram_choose_cmd_request + attribute \src "ls180.v:750.11-750.34" + wire width 4 \sdram_choose_cmd_valids + attribute \src "ls180.v:739.5-739.36" + wire \sdram_choose_cmd_want_activates + attribute \src "ls180.v:738.5-738.31" + wire \sdram_choose_cmd_want_cmds + attribute \src "ls180.v:736.5-736.32" + wire \sdram_choose_cmd_want_reads + attribute \src "ls180.v:737.5-737.33" + wire \sdram_choose_cmd_want_writes + attribute \src "ls180.v:771.6-771.25" + wire \sdram_choose_req_ce + attribute \src "ls180.v:760.13-760.43" + wire width 13 \sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:761.12-761.43" + wire width 2 \sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:762.5-762.37" + wire \sdram_choose_req_cmd_payload_cas + attribute \src "ls180.v:765.6-765.41" + wire \sdram_choose_req_cmd_payload_is_cmd + attribute \src "ls180.v:766.6-766.42" + wire \sdram_choose_req_cmd_payload_is_read + attribute \src "ls180.v:767.6-767.43" + wire \sdram_choose_req_cmd_payload_is_write + attribute \src "ls180.v:763.5-763.37" + wire \sdram_choose_req_cmd_payload_ras + attribute \src "ls180.v:764.5-764.36" + wire \sdram_choose_req_cmd_payload_we + attribute \src "ls180.v:759.5-759.31" + wire \sdram_choose_req_cmd_ready + attribute \src "ls180.v:758.6-758.32" + wire \sdram_choose_req_cmd_valid + attribute \src "ls180.v:770.11-770.33" + wire width 2 \sdram_choose_req_grant + attribute \src "ls180.v:769.12-769.36" + wire width 4 \sdram_choose_req_request + attribute \src "ls180.v:768.11-768.34" + wire width 4 \sdram_choose_req_valids + attribute \src "ls180.v:757.5-757.36" + wire \sdram_choose_req_want_activates + attribute \src "ls180.v:756.6-756.32" + wire \sdram_choose_req_want_cmds + attribute \src "ls180.v:754.5-754.32" + wire \sdram_choose_req_want_reads + attribute \src "ls180.v:755.5-755.33" + wire \sdram_choose_req_want_writes + attribute \src "ls180.v:26.14-26.23" + wire output 22 \sdram_cke + attribute \src "ls180.v:315.6-315.17" + wire \sdram_cke_1 + attribute \src "ls180.v:29.14-29.25" + wire output 25 \sdram_clock + attribute \src "ls180.v:383.5-383.19" + wire \sdram_cmd_last + attribute \src "ls180.v:384.12-384.31" + wire width 13 \sdram_cmd_payload_a + attribute \src "ls180.v:385.11-385.31" + wire width 2 \sdram_cmd_payload_ba + attribute \src "ls180.v:386.5-386.26" + wire \sdram_cmd_payload_cas + attribute \src "ls180.v:389.5-389.30" + wire \sdram_cmd_payload_is_read + attribute \src "ls180.v:390.5-390.31" + wire \sdram_cmd_payload_is_write + attribute \src "ls180.v:387.5-387.26" + wire \sdram_cmd_payload_ras + attribute \src "ls180.v:388.5-388.25" + wire \sdram_cmd_payload_we + attribute \src "ls180.v:382.5-382.20" + wire \sdram_cmd_ready + attribute \src "ls180.v:381.5-381.20" + wire \sdram_cmd_valid + attribute \src "ls180.v:323.6-323.27" + wire \sdram_command_issue_r + attribute \src "ls180.v:322.6-322.28" + wire \sdram_command_issue_re + attribute \src "ls180.v:325.5-325.26" + wire \sdram_command_issue_w + attribute \src "ls180.v:324.6-324.28" + wire \sdram_command_issue_we + attribute \src "ls180.v:321.5-321.21" + wire \sdram_command_re + attribute \src "ls180.v:320.11-320.32" + wire width 6 \sdram_command_storage + attribute \src "ls180.v:25.14-25.24" + wire output 21 \sdram_cs_n + attribute \src "ls180.v:374.5-374.23" + wire \sdram_dfi_p0_act_n + attribute \src "ls180.v:365.12-365.32" + wire width 13 \sdram_dfi_p0_address + attribute \src "ls180.v:366.11-366.28" + wire width 2 \sdram_dfi_p0_bank + attribute \src "ls180.v:367.5-367.23" + wire \sdram_dfi_p0_cas_n + attribute \src "ls180.v:371.6-371.22" + wire \sdram_dfi_p0_cke + attribute \src "ls180.v:368.5-368.22" + wire \sdram_dfi_p0_cs_n + attribute \src "ls180.v:372.6-372.22" + wire \sdram_dfi_p0_odt + attribute \src "ls180.v:369.5-369.23" + wire \sdram_dfi_p0_ras_n + attribute \src "ls180.v:379.13-379.32" + wire width 16 \sdram_dfi_p0_rddata + attribute \src "ls180.v:378.5-378.27" + wire \sdram_dfi_p0_rddata_en attribute \src "ls180.v:380.6-380.31" - wire \main_sdram_slave_p0_ras_n - attribute \src "ls180.v:390.12-390.38" - wire width 16 \main_sdram_slave_p0_rddata - attribute \src "ls180.v:389.6-389.35" - wire \main_sdram_slave_p0_rddata_en - attribute \src "ls180.v:391.5-391.37" - wire \main_sdram_slave_p0_rddata_valid - attribute \src "ls180.v:384.6-384.33" - wire \main_sdram_slave_p0_reset_n - attribute \src "ls180.v:381.6-381.30" - wire \main_sdram_slave_p0_we_n - attribute \src "ls180.v:386.13-386.39" - wire width 16 \main_sdram_slave_p0_wrdata - attribute \src "ls180.v:387.6-387.35" - wire \main_sdram_slave_p0_wrdata_en - attribute \src "ls180.v:388.12-388.43" - wire width 2 \main_sdram_slave_p0_wrdata_mask - attribute \src "ls180.v:426.12-426.29" - wire width 16 \main_sdram_status - attribute \src "ls180.v:869.5-869.24" - wire \main_sdram_steerer0 - attribute \src "ls180.v:870.5-870.24" - wire \main_sdram_steerer1 - attribute \src "ls180.v:868.11-868.33" - wire width 2 \main_sdram_steerer_sel - attribute \src "ls180.v:412.11-412.29" - wire width 4 \main_sdram_storage - attribute \src "ls180.v:877.5-877.29" - wire \main_sdram_tccdcon_count + wire \sdram_dfi_p0_rddata_valid + attribute \src "ls180.v:373.6-373.26" + wire \sdram_dfi_p0_reset_n + attribute \src "ls180.v:370.5-370.22" + wire \sdram_dfi_p0_we_n + attribute \src "ls180.v:375.13-375.32" + wire width 16 \sdram_dfi_p0_wrdata + attribute \src "ls180.v:376.5-376.27" + wire \sdram_dfi_p0_wrdata_en + attribute \src "ls180.v:377.12-377.36" + wire width 2 \sdram_dfi_p0_wrdata_mask + attribute \src "ls180.v:28.20-28.28" + wire width 2 output 24 \sdram_dm + attribute \src "ls180.v:19.20-19.30" + wire width 16 input 15 \sdram_dq_i + attribute \src "ls180.v:20.21-20.31" + wire width 16 output 16 \sdram_dq_o + attribute \src "ls180.v:21.14-21.25" + wire output 17 \sdram_dq_oe + attribute \src "ls180.v:789.5-789.14" + wire \sdram_en0 + attribute \src "ls180.v:792.5-792.14" + wire \sdram_en1 + attribute \src "ls180.v:795.6-795.25" + wire \sdram_go_to_refresh + attribute \src "ls180.v:337.13-337.39" + wire width 22 \sdram_interface_bank0_addr + attribute \src "ls180.v:338.6-338.32" + wire \sdram_interface_bank0_lock + attribute \src "ls180.v:340.6-340.39" + wire \sdram_interface_bank0_rdata_valid + attribute \src "ls180.v:335.6-335.33" + wire \sdram_interface_bank0_ready + attribute \src "ls180.v:334.6-334.33" + wire \sdram_interface_bank0_valid + attribute \src "ls180.v:339.6-339.39" + wire \sdram_interface_bank0_wdata_ready + attribute \src "ls180.v:336.6-336.30" + wire \sdram_interface_bank0_we + attribute \src "ls180.v:344.13-344.39" + wire width 22 \sdram_interface_bank1_addr + attribute \src "ls180.v:345.6-345.32" + wire \sdram_interface_bank1_lock + attribute \src "ls180.v:347.6-347.39" + wire \sdram_interface_bank1_rdata_valid + attribute \src "ls180.v:342.6-342.33" + wire \sdram_interface_bank1_ready + attribute \src "ls180.v:341.6-341.33" + wire \sdram_interface_bank1_valid + attribute \src "ls180.v:346.6-346.39" + wire \sdram_interface_bank1_wdata_ready + attribute \src "ls180.v:343.6-343.30" + wire \sdram_interface_bank1_we + attribute \src "ls180.v:351.13-351.39" + wire width 22 \sdram_interface_bank2_addr + attribute \src "ls180.v:352.6-352.32" + wire \sdram_interface_bank2_lock + attribute \src "ls180.v:354.6-354.39" + wire \sdram_interface_bank2_rdata_valid + attribute \src "ls180.v:349.6-349.33" + wire \sdram_interface_bank2_ready + attribute \src "ls180.v:348.6-348.33" + wire \sdram_interface_bank2_valid + attribute \src "ls180.v:353.6-353.39" + wire \sdram_interface_bank2_wdata_ready + attribute \src "ls180.v:350.6-350.30" + wire \sdram_interface_bank2_we + attribute \src "ls180.v:358.13-358.39" + wire width 22 \sdram_interface_bank3_addr + attribute \src "ls180.v:359.6-359.32" + wire \sdram_interface_bank3_lock + attribute \src "ls180.v:361.6-361.39" + wire \sdram_interface_bank3_rdata_valid + attribute \src "ls180.v:356.6-356.33" + wire \sdram_interface_bank3_ready + attribute \src "ls180.v:355.6-355.33" + wire \sdram_interface_bank3_valid + attribute \src "ls180.v:360.6-360.39" + wire \sdram_interface_bank3_wdata_ready + attribute \src "ls180.v:357.6-357.30" + wire \sdram_interface_bank3_we + attribute \src "ls180.v:364.13-364.34" + wire width 16 \sdram_interface_rdata + attribute \src "ls180.v:362.12-362.33" + wire width 16 \sdram_interface_wdata + attribute \src "ls180.v:363.11-363.35" + wire width 2 \sdram_interface_wdata_we + attribute \src "ls180.v:275.5-275.24" + wire \sdram_inti_p0_act_n + attribute \src "ls180.v:266.13-266.34" + wire width 13 \sdram_inti_p0_address + attribute \src "ls180.v:267.12-267.30" + wire width 2 \sdram_inti_p0_bank + attribute \src "ls180.v:268.5-268.24" + wire \sdram_inti_p0_cas_n + attribute \src "ls180.v:272.6-272.23" + wire \sdram_inti_p0_cke + attribute \src "ls180.v:269.5-269.23" + wire \sdram_inti_p0_cs_n + attribute \src "ls180.v:273.6-273.23" + wire \sdram_inti_p0_odt + attribute \src "ls180.v:270.5-270.24" + wire \sdram_inti_p0_ras_n + attribute \src "ls180.v:280.12-280.32" + wire width 16 \sdram_inti_p0_rddata + attribute \src "ls180.v:279.6-279.29" + wire \sdram_inti_p0_rddata_en + attribute \src "ls180.v:281.5-281.31" + wire \sdram_inti_p0_rddata_valid + attribute \src "ls180.v:274.6-274.27" + wire \sdram_inti_p0_reset_n + attribute \src "ls180.v:271.5-271.23" + wire \sdram_inti_p0_we_n + attribute \src "ls180.v:276.13-276.33" + wire width 16 \sdram_inti_p0_wrdata + attribute \src "ls180.v:277.6-277.29" + wire \sdram_inti_p0_wrdata_en + attribute \src "ls180.v:278.12-278.37" + wire width 2 \sdram_inti_p0_wrdata_mask + attribute \src "ls180.v:307.5-307.26" + wire \sdram_master_p0_act_n + attribute \src "ls180.v:298.12-298.35" + wire width 13 \sdram_master_p0_address + attribute \src "ls180.v:299.11-299.31" + wire width 2 \sdram_master_p0_bank + attribute \src "ls180.v:300.5-300.26" + wire \sdram_master_p0_cas_n + attribute \src "ls180.v:304.5-304.24" + wire \sdram_master_p0_cke + attribute \src "ls180.v:301.5-301.25" + wire \sdram_master_p0_cs_n + attribute \src "ls180.v:305.5-305.24" + wire \sdram_master_p0_odt + attribute \src "ls180.v:302.5-302.26" + wire \sdram_master_p0_ras_n + attribute \src "ls180.v:312.13-312.35" + wire width 16 \sdram_master_p0_rddata + attribute \src "ls180.v:311.5-311.30" + wire \sdram_master_p0_rddata_en + attribute \src "ls180.v:313.6-313.34" + wire \sdram_master_p0_rddata_valid + attribute \src "ls180.v:306.5-306.28" + wire \sdram_master_p0_reset_n + attribute \src "ls180.v:303.5-303.25" + wire \sdram_master_p0_we_n + attribute \src "ls180.v:308.12-308.34" + wire width 16 \sdram_master_p0_wrdata + attribute \src "ls180.v:309.5-309.30" + wire \sdram_master_p0_wrdata_en + attribute \src "ls180.v:310.11-310.38" + wire width 2 \sdram_master_p0_wrdata_mask + attribute \src "ls180.v:790.6-790.21" + wire \sdram_max_time0 + attribute \src "ls180.v:793.6-793.21" + wire \sdram_max_time1 + attribute \src "ls180.v:772.12-772.23" + wire width 13 \sdram_nop_a + attribute \src "ls180.v:773.11-773.23" + wire width 2 \sdram_nop_ba + attribute \src "ls180.v:316.6-316.15" + wire \sdram_odt + attribute \src "ls180.v:399.5-399.26" + wire \sdram_postponer_count + attribute \src "ls180.v:397.6-397.27" + wire \sdram_postponer_req_i + attribute \src "ls180.v:398.5-398.26" + wire \sdram_postponer_req_o + attribute \src "ls180.v:734.6-734.23" + wire \sdram_ras_allowed + attribute \src "ls180.v:23.14-23.25" + wire output 19 \sdram_ras_n + attribute \src "ls180.v:319.5-319.13" + wire \sdram_re + attribute \src "ls180.v:787.6-787.26" + wire \sdram_read_available + attribute \src "ls180.v:317.6-317.19" + wire \sdram_reset_n + attribute \src "ls180.v:314.6-314.15" + wire \sdram_sel + attribute \src "ls180.v:405.5-405.26" + wire \sdram_sequencer_count + attribute \src "ls180.v:404.11-404.34" + wire width 4 \sdram_sequencer_counter + attribute \src "ls180.v:401.6-401.27" + wire \sdram_sequencer_done0 + attribute \src "ls180.v:403.5-403.26" + wire \sdram_sequencer_done1 + attribute \src "ls180.v:400.5-400.27" + wire \sdram_sequencer_start0 + attribute \src "ls180.v:402.6-402.28" + wire \sdram_sequencer_start1 + attribute \src "ls180.v:291.6-291.26" + wire \sdram_slave_p0_act_n + attribute \src "ls180.v:282.13-282.35" + wire width 13 \sdram_slave_p0_address + attribute \src "ls180.v:283.12-283.31" + wire width 2 \sdram_slave_p0_bank + attribute \src "ls180.v:284.6-284.26" + wire \sdram_slave_p0_cas_n + attribute \src "ls180.v:288.6-288.24" + wire \sdram_slave_p0_cke + attribute \src "ls180.v:285.6-285.25" + wire \sdram_slave_p0_cs_n + attribute \src "ls180.v:289.6-289.24" + wire \sdram_slave_p0_odt + attribute \src "ls180.v:286.6-286.26" + wire \sdram_slave_p0_ras_n + attribute \src "ls180.v:296.12-296.33" + wire width 16 \sdram_slave_p0_rddata + attribute \src "ls180.v:295.6-295.30" + wire \sdram_slave_p0_rddata_en + attribute \src "ls180.v:297.5-297.32" + wire \sdram_slave_p0_rddata_valid + attribute \src "ls180.v:290.6-290.28" + wire \sdram_slave_p0_reset_n + attribute \src "ls180.v:287.6-287.25" + wire \sdram_slave_p0_we_n + attribute \src "ls180.v:292.13-292.34" + wire width 16 \sdram_slave_p0_wrdata + attribute \src "ls180.v:293.6-293.30" + wire \sdram_slave_p0_wrdata_en + attribute \src "ls180.v:294.12-294.38" + wire width 2 \sdram_slave_p0_wrdata_mask + attribute \src "ls180.v:332.12-332.24" + wire width 16 \sdram_status + attribute \src "ls180.v:775.5-775.19" + wire \sdram_steerer0 + attribute \src "ls180.v:776.5-776.19" + wire \sdram_steerer1 + attribute \src "ls180.v:774.11-774.28" + wire width 2 \sdram_steerer_sel + attribute \src "ls180.v:318.11-318.24" + wire width 4 \sdram_storage + attribute \src "ls180.v:783.5-783.24" + wire \sdram_tccdcon_count attribute \no_retiming "true" - attribute \src "ls180.v:876.32-876.56" - wire \main_sdram_tccdcon_ready - attribute \src "ls180.v:875.6-875.30" - wire \main_sdram_tccdcon_valid + attribute \src "ls180.v:782.32-782.51" + wire \sdram_tccdcon_ready + attribute \src "ls180.v:781.6-781.25" + wire \sdram_tccdcon_valid attribute \no_retiming "true" - attribute \src "ls180.v:874.32-874.56" - wire \main_sdram_tfawcon_ready - attribute \src "ls180.v:873.6-873.30" - wire \main_sdram_tfawcon_valid - attribute \src "ls180.v:885.11-885.27" - wire width 5 \main_sdram_time0 - attribute \src "ls180.v:888.11-888.27" - wire width 4 \main_sdram_time1 - attribute \src "ls180.v:488.12-488.35" - wire width 10 \main_sdram_timer_count0 - attribute \src "ls180.v:490.11-490.34" - wire width 10 \main_sdram_timer_count1 - attribute \src "ls180.v:487.6-487.28" - wire \main_sdram_timer_done0 - attribute \src "ls180.v:489.6-489.28" - wire \main_sdram_timer_done1 - attribute \src "ls180.v:486.6-486.27" - wire \main_sdram_timer_wait + attribute \src "ls180.v:780.32-780.51" + wire \sdram_tfawcon_ready + attribute \src "ls180.v:779.6-779.25" + wire \sdram_tfawcon_valid + attribute \src "ls180.v:791.11-791.22" + wire width 5 \sdram_time0 + attribute \src "ls180.v:794.11-794.22" + wire width 4 \sdram_time1 + attribute \src "ls180.v:394.12-394.30" + wire width 10 \sdram_timer_count0 + attribute \src "ls180.v:396.11-396.29" + wire width 10 \sdram_timer_count1 + attribute \src "ls180.v:393.6-393.23" + wire \sdram_timer_done0 + attribute \src "ls180.v:395.6-395.23" + wire \sdram_timer_done1 + attribute \src "ls180.v:392.6-392.22" + wire \sdram_timer_wait attribute \no_retiming "true" - attribute \src "ls180.v:872.32-872.56" - wire \main_sdram_trrdcon_ready - attribute \src "ls180.v:871.6-871.30" - wire \main_sdram_trrdcon_valid - attribute \src "ls180.v:880.11-880.35" - wire width 3 \main_sdram_twtrcon_count + attribute \src "ls180.v:778.32-778.51" + wire \sdram_trrdcon_ready + attribute \src "ls180.v:777.6-777.25" + wire \sdram_trrdcon_valid + attribute \src "ls180.v:786.11-786.30" + wire width 3 \sdram_twtrcon_count attribute \no_retiming "true" - attribute \src "ls180.v:879.32-879.56" - wire \main_sdram_twtrcon_ready - attribute \src "ls180.v:878.6-878.30" - wire \main_sdram_twtrcon_valid - attribute \src "ls180.v:485.6-485.30" - wire \main_sdram_wants_refresh - attribute \src "ls180.v:427.6-427.19" - wire \main_sdram_we - attribute \src "ls180.v:425.5-425.25" - wire \main_sdram_wrdata_re - attribute \src "ls180.v:424.12-424.37" - wire width 16 \main_sdram_wrdata_storage - attribute \src "ls180.v:882.6-882.32" - wire \main_sdram_write_available - attribute \src "ls180.v:917.5-917.47" - wire \main_socbushandler_converted_interface_ack - attribute \src "ls180.v:911.13-911.55" - wire width 30 \main_socbushandler_converted_interface_adr - attribute \src "ls180.v:920.12-920.54" - wire width 2 \main_socbushandler_converted_interface_bte - attribute \src "ls180.v:919.12-919.54" - wire width 3 \main_socbushandler_converted_interface_cti - attribute \src "ls180.v:915.6-915.48" - wire \main_socbushandler_converted_interface_cyc - attribute \src "ls180.v:913.13-913.57" - wire width 64 \main_socbushandler_converted_interface_dat_r - attribute \src "ls180.v:912.13-912.57" - wire width 64 \main_socbushandler_converted_interface_dat_w - attribute \src "ls180.v:921.5-921.47" - wire \main_socbushandler_converted_interface_err - attribute \src "ls180.v:914.12-914.54" - wire width 8 \main_socbushandler_converted_interface_sel - attribute \src "ls180.v:916.6-916.48" - wire \main_socbushandler_converted_interface_stb - attribute \src "ls180.v:918.6-918.47" - wire \main_socbushandler_converted_interface_we - attribute \src "ls180.v:923.5-923.31" - wire \main_socbushandler_counter - attribute \src "ls180.v:1852.5-1852.53" - wire \main_socbushandler_counter_converter2_next_value - attribute \src "ls180.v:1853.5-1853.56" - wire \main_socbushandler_counter_converter2_next_value_ce - attribute \src "ls180.v:925.12-925.36" - wire width 64 \main_socbushandler_dat_r - attribute \src "ls180.v:924.6-924.30" - wire \main_socbushandler_reset - attribute \src "ls180.v:922.5-922.28" - wire \main_socbushandler_skip - attribute \src "ls180.v:1100.6-1100.27" - wire \main_spimaster0_start - attribute \src "ls180.v:1110.12-1110.35" - wire width 8 \main_spimaster10_length - attribute \src "ls180.v:1111.12-1111.36" - wire width 16 \main_spimaster11_storage - attribute \src "ls180.v:1112.5-1112.24" - wire \main_spimaster12_re - attribute \src "ls180.v:1113.6-1113.27" - wire \main_spimaster13_done - attribute \src "ls180.v:1114.6-1114.29" - wire \main_spimaster14_status - attribute \src "ls180.v:1115.6-1115.25" - wire \main_spimaster15_we - attribute \src "ls180.v:1116.11-1116.35" - wire width 8 \main_spimaster16_storage - attribute \src "ls180.v:1117.5-1117.24" - wire \main_spimaster17_re - attribute \src "ls180.v:1118.12-1118.35" - wire width 8 \main_spimaster18_status - attribute \src "ls180.v:1119.6-1119.25" - wire \main_spimaster19_we - attribute \src "ls180.v:1101.12-1101.34" - wire width 8 \main_spimaster1_length - attribute \src "ls180.v:1173.5-1173.23" - wire \main_spimaster1_re - attribute \src "ls180.v:1172.12-1172.35" - wire width 16 \main_spimaster1_storage - attribute \src "ls180.v:1120.6-1120.26" - wire \main_spimaster20_sel - attribute \src "ls180.v:1121.5-1121.29" - wire \main_spimaster21_storage - attribute \src "ls180.v:1122.5-1122.24" - wire \main_spimaster22_re - attribute \src "ls180.v:1123.5-1123.29" - wire \main_spimaster23_storage - attribute \src "ls180.v:1124.5-1124.24" - wire \main_spimaster24_re - attribute \src "ls180.v:1125.5-1125.32" - wire \main_spimaster25_clk_enable - attribute \src "ls180.v:1126.5-1126.31" - wire \main_spimaster26_cs_enable - attribute \src "ls180.v:1127.11-1127.33" - wire width 3 \main_spimaster27_count - attribute \src "ls180.v:1893.11-1893.55" - wire width 3 \main_spimaster27_count_spimaster0_next_value - attribute \src "ls180.v:1894.5-1894.52" - wire \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:1128.5-1128.32" - wire \main_spimaster28_mosi_latch - attribute \src "ls180.v:1129.5-1129.32" - wire \main_spimaster29_miso_latch - attribute \src "ls180.v:1102.5-1102.25" - wire \main_spimaster2_done - attribute \src "ls180.v:1130.12-1130.40" - wire width 16 \main_spimaster30_clk_divider - attribute \src "ls180.v:1131.6-1131.31" - wire \main_spimaster31_clk_rise - attribute \src "ls180.v:1132.6-1132.31" - wire \main_spimaster32_clk_fall - attribute \src "ls180.v:1133.11-1133.37" - wire width 8 \main_spimaster33_mosi_data - attribute \src "ls180.v:1134.11-1134.36" - wire width 3 \main_spimaster34_mosi_sel - attribute \src "ls180.v:1135.11-1135.37" - wire width 8 \main_spimaster35_miso_data - attribute \src "ls180.v:1103.5-1103.24" - wire \main_spimaster3_irq - attribute \src "ls180.v:1104.12-1104.32" - wire width 8 \main_spimaster4_mosi - attribute \src "ls180.v:1105.11-1105.31" - wire width 8 \main_spimaster5_miso - attribute \src "ls180.v:1106.6-1106.24" - wire \main_spimaster6_cs - attribute \src "ls180.v:1107.6-1107.30" - wire \main_spimaster7_loopback - attribute \src "ls180.v:1108.12-1108.39" - wire width 16 \main_spimaster8_clk_divider - attribute \src "ls180.v:1109.5-1109.26" - wire \main_spimaster9_start - attribute \src "ls180.v:1144.13-1144.40" - wire width 16 \main_spisdcard_clk_divider0 - attribute \src "ls180.v:1166.12-1166.39" - wire width 16 \main_spisdcard_clk_divider1 - attribute \src "ls180.v:1161.5-1161.30" - wire \main_spisdcard_clk_enable - attribute \src "ls180.v:1168.6-1168.29" - wire \main_spisdcard_clk_fall - attribute \src "ls180.v:1167.6-1167.29" - wire \main_spisdcard_clk_rise - attribute \src "ls180.v:1148.5-1148.30" - wire \main_spisdcard_control_re - attribute \src "ls180.v:1147.12-1147.42" - wire width 16 \main_spisdcard_control_storage - attribute \src "ls180.v:1163.11-1163.31" - wire width 3 \main_spisdcard_count - attribute \src "ls180.v:1897.11-1897.53" - wire width 3 \main_spisdcard_count_spimaster1_next_value - attribute \src "ls180.v:1898.5-1898.50" - wire \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:1142.6-1142.23" - wire \main_spisdcard_cs - attribute \src "ls180.v:1162.5-1162.29" - wire \main_spisdcard_cs_enable - attribute \src "ls180.v:1158.5-1158.25" - wire \main_spisdcard_cs_re - attribute \src "ls180.v:1157.5-1157.30" - wire \main_spisdcard_cs_storage - attribute \src "ls180.v:1138.5-1138.25" - wire \main_spisdcard_done0 - attribute \src "ls180.v:1149.6-1149.26" - wire \main_spisdcard_done1 - attribute \src "ls180.v:1139.5-1139.23" - wire \main_spisdcard_irq - attribute \src "ls180.v:1137.12-1137.34" - wire width 8 \main_spisdcard_length0 - attribute \src "ls180.v:1146.12-1146.34" - wire width 8 \main_spisdcard_length1 - attribute \src "ls180.v:1143.6-1143.29" - wire \main_spisdcard_loopback - attribute \src "ls180.v:1160.5-1160.31" - wire \main_spisdcard_loopback_re - attribute \src "ls180.v:1159.5-1159.36" - wire \main_spisdcard_loopback_storage - attribute \src "ls180.v:1141.11-1141.30" - wire width 8 \main_spisdcard_miso - attribute \src "ls180.v:1171.11-1171.35" - wire width 8 \main_spisdcard_miso_data - attribute \src "ls180.v:1165.5-1165.30" - wire \main_spisdcard_miso_latch - attribute \src "ls180.v:1154.12-1154.38" - wire width 8 \main_spisdcard_miso_status - attribute \src "ls180.v:1155.6-1155.28" - wire \main_spisdcard_miso_we - attribute \src "ls180.v:1140.12-1140.31" - wire width 8 \main_spisdcard_mosi - attribute \src "ls180.v:1169.11-1169.35" - wire width 8 \main_spisdcard_mosi_data - attribute \src "ls180.v:1164.5-1164.30" - wire \main_spisdcard_mosi_latch - attribute \src "ls180.v:1153.5-1153.27" - wire \main_spisdcard_mosi_re - attribute \src "ls180.v:1170.11-1170.34" - wire width 3 \main_spisdcard_mosi_sel - attribute \src "ls180.v:1152.11-1152.38" - wire width 8 \main_spisdcard_mosi_storage - attribute \src "ls180.v:1156.6-1156.24" - wire \main_spisdcard_sel - attribute \src "ls180.v:1136.6-1136.27" - wire \main_spisdcard_start0 - attribute \src "ls180.v:1145.5-1145.26" - wire \main_spisdcard_start1 - attribute \src "ls180.v:1150.6-1150.34" - wire \main_spisdcard_status_status - attribute \src "ls180.v:1151.6-1151.30" - wire \main_spisdcard_status_we - attribute \src "ls180.v:260.12-260.26" - wire width 6 \main_sram0_adr - attribute \src "ls180.v:261.13-261.29" - wire width 64 \main_sram0_dat_r - attribute \src "ls180.v:263.13-263.29" - wire width 64 \main_sram0_dat_w - attribute \src "ls180.v:262.11-262.24" - wire width 8 \main_sram0_we - attribute \src "ls180.v:275.12-275.26" - wire width 6 \main_sram1_adr - attribute \src "ls180.v:276.13-276.29" - wire width 64 \main_sram1_dat_r - attribute \src "ls180.v:278.13-278.29" - wire width 64 \main_sram1_dat_w - attribute \src "ls180.v:277.11-277.24" - wire width 8 \main_sram1_we - attribute \src "ls180.v:290.12-290.26" - wire width 6 \main_sram2_adr - attribute \src "ls180.v:291.13-291.29" - wire width 64 \main_sram2_dat_r - attribute \src "ls180.v:293.13-293.29" - wire width 64 \main_sram2_dat_w - attribute \src "ls180.v:292.11-292.24" - wire width 8 \main_sram2_we - attribute \src "ls180.v:305.12-305.26" - wire width 6 \main_sram3_adr - attribute \src "ls180.v:306.13-306.29" - wire width 64 \main_sram3_dat_r - attribute \src "ls180.v:308.13-308.29" - wire width 64 \main_sram3_dat_w - attribute \src "ls180.v:307.11-307.24" - wire width 8 \main_sram3_we - attribute \src "ls180.v:991.12-991.44" - wire width 2 \main_uart_eventmanager_pending_r - attribute \src "ls180.v:990.6-990.39" - wire \main_uart_eventmanager_pending_re - attribute \src "ls180.v:993.11-993.43" - wire width 2 \main_uart_eventmanager_pending_w - attribute \src "ls180.v:992.6-992.39" - wire \main_uart_eventmanager_pending_we - attribute \src "ls180.v:995.5-995.30" - wire \main_uart_eventmanager_re - attribute \src "ls180.v:987.12-987.43" - wire width 2 \main_uart_eventmanager_status_r - attribute \src "ls180.v:986.6-986.38" - wire \main_uart_eventmanager_status_re - attribute \src "ls180.v:989.11-989.42" - wire width 2 \main_uart_eventmanager_status_w - attribute \src "ls180.v:988.6-988.38" - wire \main_uart_eventmanager_status_we - attribute \src "ls180.v:994.11-994.41" - wire width 2 \main_uart_eventmanager_storage - attribute \src "ls180.v:975.6-975.19" - wire \main_uart_irq - attribute \src "ls180.v:961.12-961.46" - wire width 32 \main_uart_phy_phase_accumulator_rx - attribute \src "ls180.v:951.12-951.46" - wire width 32 \main_uart_phy_phase_accumulator_tx - attribute \src "ls180.v:944.5-944.21" - wire \main_uart_phy_re - attribute \src "ls180.v:962.6-962.22" - wire \main_uart_phy_rx - attribute \src "ls180.v:965.11-965.36" - wire width 4 \main_uart_phy_rx_bitcount - attribute \src "ls180.v:966.5-966.26" - wire \main_uart_phy_rx_busy - attribute \src "ls180.v:963.5-963.23" - wire \main_uart_phy_rx_r - attribute \src "ls180.v:964.11-964.31" - wire width 8 \main_uart_phy_rx_reg - attribute \src "ls180.v:947.6-947.30" - wire \main_uart_phy_sink_first - attribute \src "ls180.v:948.6-948.29" - wire \main_uart_phy_sink_last - attribute \src "ls180.v:949.12-949.43" - wire width 8 \main_uart_phy_sink_payload_data - attribute \src "ls180.v:946.5-946.29" - wire \main_uart_phy_sink_ready - attribute \src "ls180.v:945.6-945.30" - wire \main_uart_phy_sink_valid - attribute \src "ls180.v:957.5-957.31" - wire \main_uart_phy_source_first - attribute \src "ls180.v:958.5-958.30" - wire \main_uart_phy_source_last - attribute \src "ls180.v:959.11-959.44" - wire width 8 \main_uart_phy_source_payload_data - attribute \src "ls180.v:956.6-956.32" - wire \main_uart_phy_source_ready - attribute \src "ls180.v:955.5-955.31" - wire \main_uart_phy_source_valid - attribute \src "ls180.v:943.12-943.33" - wire width 32 \main_uart_phy_storage - attribute \src "ls180.v:953.11-953.36" - wire width 4 \main_uart_phy_tx_bitcount - attribute \src "ls180.v:954.5-954.26" - wire \main_uart_phy_tx_busy - attribute \src "ls180.v:952.11-952.31" - wire width 8 \main_uart_phy_tx_reg - attribute \src "ls180.v:960.5-960.32" - wire \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:950.5-950.32" - wire \main_uart_phy_uart_clk_txen - attribute \src "ls180.v:1084.5-1084.20" - wire \main_uart_reset - attribute \src "ls180.v:984.5-984.23" - wire \main_uart_rx_clear - attribute \src "ls180.v:1068.11-1068.36" - wire width 4 \main_uart_rx_fifo_consume - attribute \src "ls180.v:1073.6-1073.31" - wire \main_uart_rx_fifo_do_read - attribute \src "ls180.v:1079.6-1079.37" - wire \main_uart_rx_fifo_fifo_in_first - attribute \src "ls180.v:1080.6-1080.36" - wire \main_uart_rx_fifo_fifo_in_last - attribute \src "ls180.v:1078.12-1078.50" - wire width 8 \main_uart_rx_fifo_fifo_in_payload_data - attribute \src "ls180.v:1082.6-1082.38" - wire \main_uart_rx_fifo_fifo_out_first - attribute \src "ls180.v:1083.6-1083.37" - wire \main_uart_rx_fifo_fifo_out_last - attribute \src "ls180.v:1081.12-1081.51" - wire width 8 \main_uart_rx_fifo_fifo_out_payload_data - attribute \src "ls180.v:1065.11-1065.35" - wire width 5 \main_uart_rx_fifo_level0 - attribute \src "ls180.v:1077.12-1077.36" - wire width 5 \main_uart_rx_fifo_level1 - attribute \src "ls180.v:1067.11-1067.36" - wire width 4 \main_uart_rx_fifo_produce - attribute \src "ls180.v:1074.12-1074.40" - wire width 4 \main_uart_rx_fifo_rdport_adr - attribute \src "ls180.v:1075.12-1075.42" - wire width 10 \main_uart_rx_fifo_rdport_dat_r - attribute \src "ls180.v:1076.6-1076.33" - wire \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:1057.6-1057.26" - wire \main_uart_rx_fifo_re - attribute \src "ls180.v:1058.5-1058.31" - wire \main_uart_rx_fifo_readable - attribute \src "ls180.v:1066.5-1066.30" - wire \main_uart_rx_fifo_replace - attribute \src "ls180.v:1049.6-1049.34" - wire \main_uart_rx_fifo_sink_first - attribute \src "ls180.v:1050.6-1050.33" - wire \main_uart_rx_fifo_sink_last - attribute \src "ls180.v:1051.12-1051.47" - wire width 8 \main_uart_rx_fifo_sink_payload_data - attribute \src "ls180.v:1048.6-1048.34" - wire \main_uart_rx_fifo_sink_ready - attribute \src "ls180.v:1047.6-1047.34" - wire \main_uart_rx_fifo_sink_valid - attribute \src "ls180.v:1054.6-1054.36" - wire \main_uart_rx_fifo_source_first - attribute \src "ls180.v:1055.6-1055.35" - wire \main_uart_rx_fifo_source_last - attribute \src "ls180.v:1056.12-1056.49" - wire width 8 \main_uart_rx_fifo_source_payload_data - attribute \src "ls180.v:1053.6-1053.36" - wire \main_uart_rx_fifo_source_ready - attribute \src "ls180.v:1052.6-1052.36" - wire \main_uart_rx_fifo_source_valid - attribute \src "ls180.v:1063.12-1063.42" - wire width 10 \main_uart_rx_fifo_syncfifo_din - attribute \src "ls180.v:1064.12-1064.43" - wire width 10 \main_uart_rx_fifo_syncfifo_dout - attribute \src "ls180.v:1061.6-1061.35" - wire \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:1062.6-1062.41" - wire \main_uart_rx_fifo_syncfifo_readable - attribute \src "ls180.v:1059.6-1059.35" - wire \main_uart_rx_fifo_syncfifo_we - attribute \src "ls180.v:1060.6-1060.41" - wire \main_uart_rx_fifo_syncfifo_writable - attribute \src "ls180.v:1069.11-1069.39" - wire width 4 \main_uart_rx_fifo_wrport_adr - attribute \src "ls180.v:1070.12-1070.42" - wire width 10 \main_uart_rx_fifo_wrport_dat_r - attribute \src "ls180.v:1072.12-1072.42" - wire width 10 \main_uart_rx_fifo_wrport_dat_w - attribute \src "ls180.v:1071.6-1071.33" - wire \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:985.5-985.29" - wire \main_uart_rx_old_trigger - attribute \src "ls180.v:982.5-982.25" - wire \main_uart_rx_pending - attribute \src "ls180.v:981.6-981.25" - wire \main_uart_rx_status - attribute \src "ls180.v:983.6-983.26" - wire \main_uart_rx_trigger - attribute \src "ls180.v:973.6-973.30" - wire \main_uart_rxempty_status - attribute \src "ls180.v:974.6-974.26" - wire \main_uart_rxempty_we - attribute \src "ls180.v:998.6-998.29" - wire \main_uart_rxfull_status - attribute \src "ls180.v:999.6-999.25" - wire \main_uart_rxfull_we - attribute \src "ls180.v:968.12-968.28" - wire width 8 \main_uart_rxtx_r - attribute \src "ls180.v:967.6-967.23" - wire \main_uart_rxtx_re - attribute \src "ls180.v:970.12-970.28" - wire width 8 \main_uart_rxtx_w - attribute \src "ls180.v:969.6-969.23" - wire \main_uart_rxtx_we - attribute \src "ls180.v:979.5-979.23" - wire \main_uart_tx_clear - attribute \src "ls180.v:1031.11-1031.36" - wire width 4 \main_uart_tx_fifo_consume - attribute \src "ls180.v:1036.6-1036.31" - wire \main_uart_tx_fifo_do_read - attribute \src "ls180.v:1042.6-1042.37" - wire \main_uart_tx_fifo_fifo_in_first - attribute \src "ls180.v:1043.6-1043.36" - wire \main_uart_tx_fifo_fifo_in_last - attribute \src "ls180.v:1041.12-1041.50" - wire width 8 \main_uart_tx_fifo_fifo_in_payload_data - attribute \src "ls180.v:1045.6-1045.38" - wire \main_uart_tx_fifo_fifo_out_first - attribute \src "ls180.v:1046.6-1046.37" - wire \main_uart_tx_fifo_fifo_out_last - attribute \src "ls180.v:1044.12-1044.51" - wire width 8 \main_uart_tx_fifo_fifo_out_payload_data - attribute \src "ls180.v:1028.11-1028.35" - wire width 5 \main_uart_tx_fifo_level0 - attribute \src "ls180.v:1040.12-1040.36" - wire width 5 \main_uart_tx_fifo_level1 - attribute \src "ls180.v:1030.11-1030.36" - wire width 4 \main_uart_tx_fifo_produce - attribute \src "ls180.v:1037.12-1037.40" - wire width 4 \main_uart_tx_fifo_rdport_adr - attribute \src "ls180.v:1038.12-1038.42" - wire width 10 \main_uart_tx_fifo_rdport_dat_r - attribute \src "ls180.v:1039.6-1039.33" - wire \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:1020.6-1020.26" - wire \main_uart_tx_fifo_re - attribute \src "ls180.v:1021.5-1021.31" - wire \main_uart_tx_fifo_readable - attribute \src "ls180.v:1029.5-1029.30" - wire \main_uart_tx_fifo_replace - attribute \src "ls180.v:1012.5-1012.33" - wire \main_uart_tx_fifo_sink_first - attribute \src "ls180.v:1013.5-1013.32" - wire \main_uart_tx_fifo_sink_last - attribute \src "ls180.v:1014.12-1014.47" - wire width 8 \main_uart_tx_fifo_sink_payload_data - attribute \src "ls180.v:1011.6-1011.34" - wire \main_uart_tx_fifo_sink_ready - attribute \src "ls180.v:1010.6-1010.34" - wire \main_uart_tx_fifo_sink_valid - attribute \src "ls180.v:1017.6-1017.36" - wire \main_uart_tx_fifo_source_first - attribute \src "ls180.v:1018.6-1018.35" - wire \main_uart_tx_fifo_source_last - attribute \src "ls180.v:1019.12-1019.49" - wire width 8 \main_uart_tx_fifo_source_payload_data - attribute \src "ls180.v:1016.6-1016.36" - wire \main_uart_tx_fifo_source_ready - attribute \src "ls180.v:1015.6-1015.36" - wire \main_uart_tx_fifo_source_valid - attribute \src "ls180.v:1026.12-1026.42" - wire width 10 \main_uart_tx_fifo_syncfifo_din - attribute \src "ls180.v:1027.12-1027.43" - wire width 10 \main_uart_tx_fifo_syncfifo_dout - attribute \src "ls180.v:1024.6-1024.35" - wire \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:1025.6-1025.41" - wire \main_uart_tx_fifo_syncfifo_readable - attribute \src "ls180.v:1022.6-1022.35" - wire \main_uart_tx_fifo_syncfifo_we - attribute \src "ls180.v:1023.6-1023.41" - wire \main_uart_tx_fifo_syncfifo_writable - attribute \src "ls180.v:1032.11-1032.39" - wire width 4 \main_uart_tx_fifo_wrport_adr - attribute \src "ls180.v:1033.12-1033.42" - wire width 10 \main_uart_tx_fifo_wrport_dat_r - attribute \src "ls180.v:1035.12-1035.42" - wire width 10 \main_uart_tx_fifo_wrport_dat_w - attribute \src "ls180.v:1034.6-1034.33" - wire \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:980.5-980.29" - wire \main_uart_tx_old_trigger - attribute \src "ls180.v:977.5-977.25" - wire \main_uart_tx_pending - attribute \src "ls180.v:976.6-976.25" - wire \main_uart_tx_status - attribute \src "ls180.v:978.6-978.26" - wire \main_uart_tx_trigger - attribute \src "ls180.v:996.6-996.30" - wire \main_uart_txempty_status - attribute \src "ls180.v:997.6-997.26" - wire \main_uart_txempty_we - attribute \src "ls180.v:971.6-971.29" - wire \main_uart_txfull_status - attribute \src "ls180.v:972.6-972.25" - wire \main_uart_txfull_we - attribute \src "ls180.v:1002.6-1002.31" - wire \main_uart_uart_sink_first - attribute \src "ls180.v:1003.6-1003.30" - wire \main_uart_uart_sink_last - attribute \src "ls180.v:1004.12-1004.44" - wire width 8 \main_uart_uart_sink_payload_data - attribute \src "ls180.v:1001.6-1001.31" - wire \main_uart_uart_sink_ready - attribute \src "ls180.v:1000.6-1000.31" - wire \main_uart_uart_sink_valid - attribute \src "ls180.v:1007.6-1007.33" - wire \main_uart_uart_source_first - attribute \src "ls180.v:1008.6-1008.32" - wire \main_uart_uart_source_last - attribute \src "ls180.v:1009.12-1009.46" - wire width 8 \main_uart_uart_source_payload_data - attribute \src "ls180.v:1006.6-1006.33" - wire \main_uart_uart_source_ready - attribute \src "ls180.v:1005.6-1005.33" - wire \main_uart_uart_source_valid - attribute \src "ls180.v:909.5-909.22" - wire \main_wb_sdram_ack - attribute \src "ls180.v:903.12-903.29" - wire width 30 \main_wb_sdram_adr - attribute \src "ls180.v:907.5-907.22" - wire \main_wb_sdram_cyc - attribute \src "ls180.v:905.13-905.32" - wire width 32 \main_wb_sdram_dat_r - attribute \src "ls180.v:904.12-904.31" - wire width 32 \main_wb_sdram_dat_w - attribute \src "ls180.v:906.11-906.28" - wire width 4 \main_wb_sdram_sel - attribute \src "ls180.v:908.5-908.22" - wire \main_wb_sdram_stb - attribute \src "ls180.v:910.5-910.21" - wire \main_wb_sdram_we - attribute \src "ls180.v:939.5-939.24" - wire \main_wdata_consumed - attribute \src "ls180.v:10352.11-10352.17" - wire width 6 \memadr - attribute \src "ls180.v:10380.11-10380.19" - wire width 6 \memadr_1 - attribute \src "ls180.v:10408.11-10408.19" - wire width 6 \memadr_2 - attribute \src "ls180.v:10436.11-10436.19" - wire width 6 \memadr_3 - attribute \src "ls180.v:10464.11-10464.19" - wire width 6 \memadr_4 - attribute \src "ls180.v:10492.12-10492.18" - wire width 25 \memdat - attribute \src "ls180.v:10506.12-10506.20" - wire width 25 \memdat_1 - attribute \src "ls180.v:10520.12-10520.20" - wire width 25 \memdat_2 - attribute \src "ls180.v:10534.12-10534.20" - wire width 25 \memdat_3 - attribute \src "ls180.v:10548.11-10548.19" - wire width 10 \memdat_4 - attribute \src "ls180.v:10549.11-10549.19" - wire width 10 \memdat_5 - attribute \src "ls180.v:10565.11-10565.19" - wire width 10 \memdat_6 - attribute \src "ls180.v:10566.11-10566.19" - wire width 10 \memdat_7 - attribute \src "ls180.v:10582.11-10582.19" - wire width 10 \memdat_8 - attribute \src "ls180.v:10596.11-10596.19" - wire width 10 \memdat_9 - attribute \src "ls180.v:52.20-52.22" - wire width 24 input 48 \nc - attribute \src "ls180.v:341.6-341.13" - wire \por_clk - attribute \src "ls180.v:17.19-17.22" - wire width 2 output 13 \pwm - attribute \src "ls180.v:183.12-183.17" - wire width 2 \pwm_1 - attribute \src "ls180.v:36.13-36.23" - wire output 32 \sdcard_clk - attribute \src "ls180.v:37.14-37.26" - wire output 33 \sdcard_cmd_i - attribute \src "ls180.v:38.13-38.25" - wire output 34 \sdcard_cmd_o - attribute \src "ls180.v:39.13-39.26" - wire output 35 \sdcard_cmd_oe - attribute \src "ls180.v:40.20-40.33" - wire width 4 output 36 \sdcard_data_i - attribute \src "ls180.v:41.19-41.32" - wire width 4 output 37 \sdcard_data_o - attribute \src "ls180.v:42.13-42.27" - wire output 38 \sdcard_data_oe - attribute \src "ls180.v:22.20-22.27" - wire width 13 output 18 \sdram_a - attribute \src "ls180.v:31.19-31.27" - wire width 2 output 27 \sdram_ba - attribute \src "ls180.v:28.13-28.24" - wire output 24 \sdram_cas_n - attribute \src "ls180.v:30.13-30.22" - wire output 26 \sdram_cke - attribute \src "ls180.v:33.13-33.24" - wire output 29 \sdram_clock - attribute \src "ls180.v:199.6-199.19" - wire \sdram_clock_1 - attribute \src "ls180.v:29.13-29.23" - wire output 25 \sdram_cs_n - attribute \src "ls180.v:32.19-32.27" - wire width 2 output 28 \sdram_dm - attribute \src "ls180.v:23.21-23.31" - wire width 16 output 19 \sdram_dq_i - attribute \src "ls180.v:24.20-24.30" - wire width 16 output 20 \sdram_dq_o - attribute \src "ls180.v:25.13-25.24" - wire output 21 \sdram_dq_oe - attribute \src "ls180.v:27.13-27.24" - wire output 23 \sdram_ras_n - attribute \src "ls180.v:26.13-26.23" - wire output 22 \sdram_we_n - attribute \src "ls180.v:2763.6-2763.15" + attribute \src "ls180.v:785.32-785.51" + wire \sdram_twtrcon_ready + attribute \src "ls180.v:784.6-784.25" + wire \sdram_twtrcon_valid + attribute \src "ls180.v:391.6-391.25" + wire \sdram_wants_refresh + attribute \src "ls180.v:333.6-333.14" + wire \sdram_we + attribute \src "ls180.v:22.14-22.24" + wire output 18 \sdram_we_n + attribute \src "ls180.v:331.5-331.20" + wire \sdram_wrdata_re + attribute \src "ls180.v:330.12-330.32" + wire width 16 \sdram_wrdata_storage + attribute \src "ls180.v:788.6-788.27" + wire \sdram_write_available + attribute \src "ls180.v:1388.6-1388.15" wire \sdrio_clk - attribute \src "ls180.v:2764.6-2764.17" + attribute \src "ls180.v:1389.6-1389.17" wire \sdrio_clk_1 - attribute \src "ls180.v:2773.6-2773.18" + attribute \src "ls180.v:1398.6-1398.18" wire \sdrio_clk_10 - attribute \src "ls180.v:2774.6-2774.18" + attribute \src "ls180.v:1490.6-1490.19" + wire \sdrio_clk_100 + attribute \src "ls180.v:1491.6-1491.19" + wire \sdrio_clk_101 + attribute \src "ls180.v:1492.6-1492.19" + wire \sdrio_clk_102 + attribute \src "ls180.v:1493.6-1493.19" + wire \sdrio_clk_103 + attribute \src "ls180.v:1399.6-1399.18" wire \sdrio_clk_11 - attribute \src "ls180.v:2775.6-2775.18" + attribute \src "ls180.v:1400.6-1400.18" wire \sdrio_clk_12 - attribute \src "ls180.v:2776.6-2776.18" + attribute \src "ls180.v:1401.6-1401.18" wire \sdrio_clk_13 - attribute \src "ls180.v:2777.6-2777.18" + attribute \src "ls180.v:1402.6-1402.18" wire \sdrio_clk_14 - attribute \src "ls180.v:2778.6-2778.18" + attribute \src "ls180.v:1403.6-1403.18" wire \sdrio_clk_15 - attribute \src "ls180.v:2779.6-2779.18" + attribute \src "ls180.v:1404.6-1404.18" wire \sdrio_clk_16 - attribute \src "ls180.v:2780.6-2780.18" + attribute \src "ls180.v:1405.6-1405.18" wire \sdrio_clk_17 - attribute \src "ls180.v:2781.6-2781.18" + attribute \src "ls180.v:1406.6-1406.18" wire \sdrio_clk_18 - attribute \src "ls180.v:2782.6-2782.18" + attribute \src "ls180.v:1407.6-1407.18" wire \sdrio_clk_19 - attribute \src "ls180.v:2765.6-2765.17" + attribute \src "ls180.v:1390.6-1390.17" wire \sdrio_clk_2 - attribute \src "ls180.v:2783.6-2783.18" + attribute \src "ls180.v:1408.6-1408.18" wire \sdrio_clk_20 - attribute \src "ls180.v:2784.6-2784.18" + attribute \src "ls180.v:1409.6-1409.18" wire \sdrio_clk_21 - attribute \src "ls180.v:2785.6-2785.18" + attribute \src "ls180.v:1410.6-1410.18" wire \sdrio_clk_22 - attribute \src "ls180.v:2786.6-2786.18" + attribute \src "ls180.v:1411.6-1411.18" wire \sdrio_clk_23 - attribute \src "ls180.v:2787.6-2787.18" + attribute \src "ls180.v:1412.6-1412.18" wire \sdrio_clk_24 - attribute \src "ls180.v:2788.6-2788.18" + attribute \src "ls180.v:1413.6-1413.18" wire \sdrio_clk_25 - attribute \src "ls180.v:2789.6-2789.18" + attribute \src "ls180.v:1414.6-1414.18" wire \sdrio_clk_26 - attribute \src "ls180.v:2790.6-2790.18" + attribute \src "ls180.v:1415.6-1415.18" wire \sdrio_clk_27 - attribute \src "ls180.v:2791.6-2791.18" + attribute \src "ls180.v:1416.6-1416.18" wire \sdrio_clk_28 - attribute \src "ls180.v:2792.6-2792.18" + attribute \src "ls180.v:1417.6-1417.18" wire \sdrio_clk_29 - attribute \src "ls180.v:2766.6-2766.17" + attribute \src "ls180.v:1391.6-1391.17" wire \sdrio_clk_3 - attribute \src "ls180.v:2793.6-2793.18" + attribute \src "ls180.v:1418.6-1418.18" wire \sdrio_clk_30 - attribute \src "ls180.v:2794.6-2794.18" + attribute \src "ls180.v:1419.6-1419.18" wire \sdrio_clk_31 - attribute \src "ls180.v:2795.6-2795.18" + attribute \src "ls180.v:1420.6-1420.18" wire \sdrio_clk_32 - attribute \src "ls180.v:2796.6-2796.18" + attribute \src "ls180.v:1421.6-1421.18" wire \sdrio_clk_33 - attribute \src "ls180.v:2797.6-2797.18" + attribute \src "ls180.v:1422.6-1422.18" wire \sdrio_clk_34 - attribute \src "ls180.v:2798.6-2798.18" + attribute \src "ls180.v:1423.6-1423.18" wire \sdrio_clk_35 - attribute \src "ls180.v:2799.6-2799.18" + attribute \src "ls180.v:1424.6-1424.18" wire \sdrio_clk_36 - attribute \src "ls180.v:2800.6-2800.18" + attribute \src "ls180.v:1425.6-1425.18" wire \sdrio_clk_37 - attribute \src "ls180.v:2801.6-2801.18" + attribute \src "ls180.v:1426.6-1426.18" wire \sdrio_clk_38 - attribute \src "ls180.v:2802.6-2802.18" + attribute \src "ls180.v:1427.6-1427.18" wire \sdrio_clk_39 - attribute \src "ls180.v:2767.6-2767.17" + attribute \src "ls180.v:1392.6-1392.17" wire \sdrio_clk_4 - attribute \src "ls180.v:2803.6-2803.18" + attribute \src "ls180.v:1428.6-1428.18" wire \sdrio_clk_40 - attribute \src "ls180.v:2804.6-2804.18" + attribute \src "ls180.v:1429.6-1429.18" wire \sdrio_clk_41 - attribute \src "ls180.v:2805.6-2805.18" + attribute \src "ls180.v:1430.6-1430.18" wire \sdrio_clk_42 - attribute \src "ls180.v:2806.6-2806.18" + attribute \src "ls180.v:1431.6-1431.18" wire \sdrio_clk_43 - attribute \src "ls180.v:2807.6-2807.18" + attribute \src "ls180.v:1432.6-1432.18" wire \sdrio_clk_44 - attribute \src "ls180.v:2808.6-2808.18" + attribute \src "ls180.v:1433.6-1433.18" wire \sdrio_clk_45 - attribute \src "ls180.v:2809.6-2809.18" + attribute \src "ls180.v:1434.6-1434.18" wire \sdrio_clk_46 - attribute \src "ls180.v:2810.6-2810.18" + attribute \src "ls180.v:1435.6-1435.18" wire \sdrio_clk_47 - attribute \src "ls180.v:2811.6-2811.18" + attribute \src "ls180.v:1436.6-1436.18" wire \sdrio_clk_48 - attribute \src "ls180.v:2812.6-2812.18" + attribute \src "ls180.v:1437.6-1437.18" wire \sdrio_clk_49 - attribute \src "ls180.v:2768.6-2768.17" + attribute \src "ls180.v:1393.6-1393.17" wire \sdrio_clk_5 - attribute \src "ls180.v:2813.6-2813.18" + attribute \src "ls180.v:1438.6-1438.18" wire \sdrio_clk_50 - attribute \src "ls180.v:2814.6-2814.18" + attribute \src "ls180.v:1439.6-1439.18" wire \sdrio_clk_51 - attribute \src "ls180.v:2815.6-2815.18" + attribute \src "ls180.v:1440.6-1440.18" wire \sdrio_clk_52 - attribute \src "ls180.v:2816.6-2816.18" + attribute \src "ls180.v:1441.6-1441.18" wire \sdrio_clk_53 - attribute \src "ls180.v:2817.6-2817.18" + attribute \src "ls180.v:1442.6-1442.18" wire \sdrio_clk_54 - attribute \src "ls180.v:2818.6-2818.18" + attribute \src "ls180.v:1443.6-1443.18" wire \sdrio_clk_55 - attribute \src "ls180.v:2853.6-2853.18" + attribute \src "ls180.v:1446.6-1446.18" wire \sdrio_clk_56 - attribute \src "ls180.v:2854.6-2854.18" + attribute \src "ls180.v:1447.6-1447.18" wire \sdrio_clk_57 - attribute \src "ls180.v:2855.6-2855.18" + attribute \src "ls180.v:1448.6-1448.18" wire \sdrio_clk_58 - attribute \src "ls180.v:2856.6-2856.18" + attribute \src "ls180.v:1449.6-1449.18" wire \sdrio_clk_59 - attribute \src "ls180.v:2769.6-2769.17" + attribute \src "ls180.v:1394.6-1394.17" wire \sdrio_clk_6 - attribute \src "ls180.v:2857.6-2857.18" + attribute \src "ls180.v:1450.6-1450.18" wire \sdrio_clk_60 - attribute \src "ls180.v:2858.6-2858.18" + attribute \src "ls180.v:1451.6-1451.18" wire \sdrio_clk_61 - attribute \src "ls180.v:2859.6-2859.18" + attribute \src "ls180.v:1452.6-1452.18" wire \sdrio_clk_62 - attribute \src "ls180.v:2860.6-2860.18" + attribute \src "ls180.v:1453.6-1453.18" wire \sdrio_clk_63 - attribute \src "ls180.v:2861.6-2861.18" + attribute \src "ls180.v:1454.6-1454.18" wire \sdrio_clk_64 - attribute \src "ls180.v:2862.6-2862.18" + attribute \src "ls180.v:1455.6-1455.18" wire \sdrio_clk_65 - attribute \src "ls180.v:2863.6-2863.18" + attribute \src "ls180.v:1456.6-1456.18" wire \sdrio_clk_66 - attribute \src "ls180.v:2864.6-2864.18" + attribute \src "ls180.v:1457.6-1457.18" wire \sdrio_clk_67 - attribute \src "ls180.v:2865.6-2865.18" + attribute \src "ls180.v:1458.6-1458.18" wire \sdrio_clk_68 - attribute \src "ls180.v:2770.6-2770.17" + attribute \src "ls180.v:1459.6-1459.18" + wire \sdrio_clk_69 + attribute \src "ls180.v:1395.6-1395.17" wire \sdrio_clk_7 - attribute \src "ls180.v:2771.6-2771.17" + attribute \src "ls180.v:1460.6-1460.18" + wire \sdrio_clk_70 + attribute \src "ls180.v:1461.6-1461.18" + wire \sdrio_clk_71 + attribute \src "ls180.v:1462.6-1462.18" + wire \sdrio_clk_72 + attribute \src "ls180.v:1463.6-1463.18" + wire \sdrio_clk_73 + attribute \src "ls180.v:1464.6-1464.18" + wire \sdrio_clk_74 + attribute \src "ls180.v:1465.6-1465.18" + wire \sdrio_clk_75 + attribute \src "ls180.v:1466.6-1466.18" + wire \sdrio_clk_76 + attribute \src "ls180.v:1467.6-1467.18" + wire \sdrio_clk_77 + attribute \src "ls180.v:1468.6-1468.18" + wire \sdrio_clk_78 + attribute \src "ls180.v:1469.6-1469.18" + wire \sdrio_clk_79 + attribute \src "ls180.v:1396.6-1396.17" wire \sdrio_clk_8 - attribute \src "ls180.v:2772.6-2772.17" + attribute \src "ls180.v:1470.6-1470.18" + wire \sdrio_clk_80 + attribute \src "ls180.v:1471.6-1471.18" + wire \sdrio_clk_81 + attribute \src "ls180.v:1472.6-1472.18" + wire \sdrio_clk_82 + attribute \src "ls180.v:1473.6-1473.18" + wire \sdrio_clk_83 + attribute \src "ls180.v:1474.6-1474.18" + wire \sdrio_clk_84 + attribute \src "ls180.v:1475.6-1475.18" + wire \sdrio_clk_85 + attribute \src "ls180.v:1476.6-1476.18" + wire \sdrio_clk_86 + attribute \src "ls180.v:1477.6-1477.18" + wire \sdrio_clk_87 + attribute \src "ls180.v:1478.6-1478.18" + wire \sdrio_clk_88 + attribute \src "ls180.v:1479.6-1479.18" + wire \sdrio_clk_89 + attribute \src "ls180.v:1397.6-1397.17" wire \sdrio_clk_9 - attribute \src "ls180.v:18.13-18.26" - wire output 14 \spimaster_clk - attribute \src "ls180.v:20.13-20.27" - wire output 16 \spimaster_cs_n - attribute \src "ls180.v:21.13-21.27" - wire input 17 \spimaster_miso - attribute \src "ls180.v:19.13-19.27" - wire output 15 \spimaster_mosi - attribute \src "ls180.v:12.13-12.26" - wire output 8 \spisdcard_clk - attribute \src "ls180.v:14.13-14.27" - wire output 10 \spisdcard_cs_n - attribute \src "ls180.v:15.13-15.27" - wire input 11 \spisdcard_miso - attribute \src "ls180.v:13.13-13.27" - wire output 9 \spisdcard_mosi - attribute \src "ls180.v:43.13-43.20" - wire input 39 \sys_clk - attribute \src "ls180.v:339.6-339.15" + attribute \src "ls180.v:1480.6-1480.18" + wire \sdrio_clk_90 + attribute \src "ls180.v:1481.6-1481.18" + wire \sdrio_clk_91 + attribute \src "ls180.v:1482.6-1482.18" + wire \sdrio_clk_92 + attribute \src "ls180.v:1483.6-1483.18" + wire \sdrio_clk_93 + attribute \src "ls180.v:1484.6-1484.18" + wire \sdrio_clk_94 + attribute \src "ls180.v:1485.6-1485.18" + wire \sdrio_clk_95 + attribute \src "ls180.v:1486.6-1486.18" + wire \sdrio_clk_96 + attribute \src "ls180.v:1487.6-1487.18" + wire \sdrio_clk_97 + attribute \src "ls180.v:1488.6-1488.18" + wire \sdrio_clk_98 + attribute \src "ls180.v:1489.6-1489.18" + wire \sdrio_clk_99 + attribute \src "ls180.v:14.14-14.27" + wire output 10 \spimaster_clk + attribute \src "ls180.v:16.14-16.28" + wire output 12 \spimaster_cs_n + attribute \src "ls180.v:17.13-17.27" + wire input 13 \spimaster_miso + attribute \src "ls180.v:15.14-15.28" + wire output 11 \spimaster_mosi + attribute \src "ls180.v:1023.11-1023.47" + wire width 3 \subfragments_bankmachine0_next_state + attribute \src "ls180.v:1022.11-1022.42" + wire width 3 \subfragments_bankmachine0_state + attribute \src "ls180.v:1025.11-1025.47" + wire width 3 \subfragments_bankmachine1_next_state + attribute \src "ls180.v:1024.11-1024.42" + wire width 3 \subfragments_bankmachine1_state + attribute \src "ls180.v:1027.11-1027.47" + wire width 3 \subfragments_bankmachine2_next_state + attribute \src "ls180.v:1026.11-1026.42" + wire width 3 \subfragments_bankmachine2_state + attribute \src "ls180.v:1029.11-1029.47" + wire width 3 \subfragments_bankmachine3_next_state + attribute \src "ls180.v:1028.11-1028.42" + wire width 3 \subfragments_bankmachine3_state + attribute \src "ls180.v:1009.5-1009.39" + wire \subfragments_converter0_next_state + attribute \src "ls180.v:1008.5-1008.34" + wire \subfragments_converter0_state + attribute \src "ls180.v:1013.5-1013.39" + wire \subfragments_converter1_next_state + attribute \src "ls180.v:1012.5-1012.34" + wire \subfragments_converter1_state + attribute \src "ls180.v:1017.5-1017.39" + wire \subfragments_converter2_next_state + attribute \src "ls180.v:1016.5-1016.34" + wire \subfragments_converter2_state + attribute \src "ls180.v:1044.5-1044.25" + wire \subfragments_locked0 + attribute \src "ls180.v:1045.5-1045.25" + wire \subfragments_locked1 + attribute \src "ls180.v:1046.5-1046.25" + wire \subfragments_locked2 + attribute \src "ls180.v:1047.5-1047.25" + wire \subfragments_locked3 + attribute \src "ls180.v:1031.11-1031.46" + wire width 3 \subfragments_multiplexer_next_state + attribute \src "ls180.v:1030.11-1030.41" + wire width 3 \subfragments_multiplexer_state + attribute \src "ls180.v:1049.5-1049.41" + wire \subfragments_new_master_rdata_valid0 + attribute \src "ls180.v:1050.5-1050.41" + wire \subfragments_new_master_rdata_valid1 + attribute \src "ls180.v:1051.5-1051.41" + wire \subfragments_new_master_rdata_valid2 + attribute \src "ls180.v:1052.5-1052.41" + wire \subfragments_new_master_rdata_valid3 + attribute \src "ls180.v:1048.5-1048.40" + wire \subfragments_new_master_wdata_ready + attribute \src "ls180.v:1054.5-1054.28" + wire \subfragments_next_state + attribute \src "ls180.v:1021.11-1021.44" + wire width 2 \subfragments_refresher_next_state + attribute \src "ls180.v:1020.11-1020.39" + wire width 2 \subfragments_refresher_state + attribute \src "ls180.v:1034.6-1034.33" + wire \subfragments_roundrobin0_ce + attribute \src "ls180.v:1033.6-1033.36" + wire \subfragments_roundrobin0_grant + attribute \src "ls180.v:1032.6-1032.38" + wire \subfragments_roundrobin0_request + attribute \src "ls180.v:1037.6-1037.33" + wire \subfragments_roundrobin1_ce + attribute \src "ls180.v:1036.6-1036.36" + wire \subfragments_roundrobin1_grant + attribute \src "ls180.v:1035.6-1035.38" + wire \subfragments_roundrobin1_request + attribute \src "ls180.v:1040.6-1040.33" + wire \subfragments_roundrobin2_ce + attribute \src "ls180.v:1039.6-1039.36" + wire \subfragments_roundrobin2_grant + attribute \src "ls180.v:1038.6-1038.38" + wire \subfragments_roundrobin2_request + attribute \src "ls180.v:1043.6-1043.33" + wire \subfragments_roundrobin3_ce + attribute \src "ls180.v:1042.6-1042.36" + wire \subfragments_roundrobin3_grant + attribute \src "ls180.v:1041.6-1041.38" + wire \subfragments_roundrobin3_request + attribute \src "ls180.v:1053.5-1053.23" + wire \subfragments_state + attribute \src "ls180.v:33.13-33.20" + wire input 29 \sys_clk + attribute \src "ls180.v:245.6-245.15" wire \sys_clk_1 - attribute \src "ls180.v:45.19-45.31" - wire width 2 input 41 \sys_clksel_i - attribute \src "ls180.v:46.14-46.26" - wire output 42 \sys_pll_18_o - attribute \src "ls180.v:47.14-47.27" - wire output 43 \sys_pll_lck_o - attribute \src "ls180.v:44.13-44.20" - wire input 40 \sys_rst - attribute \src "ls180.v:340.6-340.15" - wire \sys_rst_1 - attribute \src "ls180.v:35.13-35.20" - wire input 31 \uart_rx + attribute \src "ls180.v:35.19-35.31" + wire width 2 input 31 \sys_clksel_i + attribute \src "ls180.v:36.14-36.26" + wire output 32 \sys_pll_18_o + attribute \src "ls180.v:37.14-37.27" + wire output 33 \sys_pll_lck_o attribute \src "ls180.v:34.13-34.20" - wire output 30 \uart_tx - attribute \src "ls180.v:10351.12-10351.15" - memory width 64 size 64 \mem - attribute \src "ls180.v:10379.12-10379.17" - memory width 64 size 64 \mem_1 - attribute \src "ls180.v:10407.12-10407.17" - memory width 64 size 64 \mem_2 - attribute \src "ls180.v:10435.12-10435.17" - memory width 64 size 64 \mem_3 - attribute \src "ls180.v:10463.12-10463.17" - memory width 64 size 64 \mem_4 - attribute \src "ls180.v:10491.12-10491.19" + wire input 30 \sys_rst + attribute \src "ls180.v:246.6-246.15" + wire \sys_rst_1 + attribute \src "ls180.v:1349.5-1349.19" + wire \t_array_muxed0 + attribute \src "ls180.v:1350.5-1350.19" + wire \t_array_muxed1 + attribute \src "ls180.v:1351.5-1351.19" + wire \t_array_muxed2 + attribute \src "ls180.v:1358.5-1358.19" + wire \t_array_muxed3 + attribute \src "ls180.v:1359.5-1359.19" + wire \t_array_muxed4 + attribute \src "ls180.v:1360.5-1360.19" + wire \t_array_muxed5 + attribute \src "ls180.v:873.5-873.13" + wire \tx_clear + attribute \src "ls180.v:925.11-925.26" + wire width 4 \tx_fifo_consume + attribute \src "ls180.v:930.6-930.21" + wire \tx_fifo_do_read + attribute \src "ls180.v:936.6-936.27" + wire \tx_fifo_fifo_in_first + attribute \src "ls180.v:937.6-937.26" + wire \tx_fifo_fifo_in_last + attribute \src "ls180.v:935.12-935.40" + wire width 8 \tx_fifo_fifo_in_payload_data + attribute \src "ls180.v:939.6-939.28" + wire \tx_fifo_fifo_out_first + attribute \src "ls180.v:940.6-940.27" + wire \tx_fifo_fifo_out_last + attribute \src "ls180.v:938.12-938.41" + wire width 8 \tx_fifo_fifo_out_payload_data + attribute \src "ls180.v:922.11-922.25" + wire width 5 \tx_fifo_level0 + attribute \src "ls180.v:934.12-934.26" + wire width 5 \tx_fifo_level1 + attribute \src "ls180.v:924.11-924.26" + wire width 4 \tx_fifo_produce + attribute \src "ls180.v:931.12-931.30" + wire width 4 \tx_fifo_rdport_adr + attribute \src "ls180.v:932.12-932.32" + wire width 10 \tx_fifo_rdport_dat_r + attribute \src "ls180.v:933.6-933.23" + wire \tx_fifo_rdport_re + attribute \src "ls180.v:914.6-914.16" + wire \tx_fifo_re + attribute \src "ls180.v:915.5-915.21" + wire \tx_fifo_readable + attribute \src "ls180.v:923.5-923.20" + wire \tx_fifo_replace + attribute \src "ls180.v:906.5-906.23" + wire \tx_fifo_sink_first + attribute \src "ls180.v:907.5-907.22" + wire \tx_fifo_sink_last + attribute \src "ls180.v:908.12-908.37" + wire width 8 \tx_fifo_sink_payload_data + attribute \src "ls180.v:905.6-905.24" + wire \tx_fifo_sink_ready + attribute \src "ls180.v:904.6-904.24" + wire \tx_fifo_sink_valid + attribute \src "ls180.v:911.6-911.26" + wire \tx_fifo_source_first + attribute \src "ls180.v:912.6-912.25" + wire \tx_fifo_source_last + attribute \src "ls180.v:913.12-913.39" + wire width 8 \tx_fifo_source_payload_data + attribute \src "ls180.v:910.6-910.26" + wire \tx_fifo_source_ready + attribute \src "ls180.v:909.6-909.26" + wire \tx_fifo_source_valid + attribute \src "ls180.v:920.12-920.32" + wire width 10 \tx_fifo_syncfifo_din + attribute \src "ls180.v:921.12-921.33" + wire width 10 \tx_fifo_syncfifo_dout + attribute \src "ls180.v:918.6-918.25" + wire \tx_fifo_syncfifo_re + attribute \src "ls180.v:919.6-919.31" + wire \tx_fifo_syncfifo_readable + attribute \src "ls180.v:916.6-916.25" + wire \tx_fifo_syncfifo_we + attribute \src "ls180.v:917.6-917.31" + wire \tx_fifo_syncfifo_writable + attribute \src "ls180.v:926.11-926.29" + wire width 4 \tx_fifo_wrport_adr + attribute \src "ls180.v:927.12-927.32" + wire width 10 \tx_fifo_wrport_dat_r + attribute \src "ls180.v:929.12-929.32" + wire width 10 \tx_fifo_wrport_dat_w + attribute \src "ls180.v:928.6-928.23" + wire \tx_fifo_wrport_we + attribute \src "ls180.v:874.5-874.19" + wire \tx_old_trigger + attribute \src "ls180.v:871.5-871.15" + wire \tx_pending + attribute \src "ls180.v:870.6-870.15" + wire \tx_status + attribute \src "ls180.v:872.6-872.16" + wire \tx_trigger + attribute \src "ls180.v:890.6-890.20" + wire \txempty_status + attribute \src "ls180.v:891.6-891.16" + wire \txempty_we + attribute \src "ls180.v:865.6-865.19" + wire \txfull_status + attribute \src "ls180.v:866.6-866.15" + wire \txfull_we + attribute \src "ls180.v:855.12-855.41" + wire width 32 \uart_phy_phase_accumulator_rx + attribute \src "ls180.v:845.12-845.41" + wire width 32 \uart_phy_phase_accumulator_tx + attribute \src "ls180.v:838.5-838.16" + wire \uart_phy_re + attribute \src "ls180.v:856.6-856.17" + wire \uart_phy_rx + attribute \src "ls180.v:859.11-859.31" + wire width 4 \uart_phy_rx_bitcount + attribute \src "ls180.v:860.5-860.21" + wire \uart_phy_rx_busy + attribute \src "ls180.v:857.5-857.18" + wire \uart_phy_rx_r + attribute \src "ls180.v:858.11-858.26" + wire width 8 \uart_phy_rx_reg + attribute \src "ls180.v:841.6-841.25" + wire \uart_phy_sink_first + attribute \src "ls180.v:842.6-842.24" + wire \uart_phy_sink_last + attribute \src "ls180.v:843.12-843.38" + wire width 8 \uart_phy_sink_payload_data + attribute \src "ls180.v:840.5-840.24" + wire \uart_phy_sink_ready + attribute \src "ls180.v:839.6-839.25" + wire \uart_phy_sink_valid + attribute \src "ls180.v:851.5-851.26" + wire \uart_phy_source_first + attribute \src "ls180.v:852.5-852.25" + wire \uart_phy_source_last + attribute \src "ls180.v:853.11-853.39" + wire width 8 \uart_phy_source_payload_data + attribute \src "ls180.v:850.6-850.27" + wire \uart_phy_source_ready + attribute \src "ls180.v:849.5-849.26" + wire \uart_phy_source_valid + attribute \src "ls180.v:837.12-837.28" + wire width 32 \uart_phy_storage + attribute \src "ls180.v:847.11-847.31" + wire width 4 \uart_phy_tx_bitcount + attribute \src "ls180.v:848.5-848.21" + wire \uart_phy_tx_busy + attribute \src "ls180.v:846.11-846.26" + wire width 8 \uart_phy_tx_reg + attribute \src "ls180.v:854.5-854.27" + wire \uart_phy_uart_clk_rxen + attribute \src "ls180.v:844.5-844.27" + wire \uart_phy_uart_clk_txen + attribute \src "ls180.v:6.13-6.20" + wire input 2 \uart_rx + attribute \src "ls180.v:896.6-896.21" + wire \uart_sink_first + attribute \src "ls180.v:897.6-897.20" + wire \uart_sink_last + attribute \src "ls180.v:898.12-898.34" + wire width 8 \uart_sink_payload_data + attribute \src "ls180.v:895.6-895.21" + wire \uart_sink_ready + attribute \src "ls180.v:894.6-894.21" + wire \uart_sink_valid + attribute \src "ls180.v:901.6-901.23" + wire \uart_source_first + attribute \src "ls180.v:902.6-902.22" + wire \uart_source_last + attribute \src "ls180.v:903.12-903.36" + wire width 8 \uart_source_payload_data + attribute \src "ls180.v:900.6-900.23" + wire \uart_source_ready + attribute \src "ls180.v:899.6-899.23" + wire \uart_source_valid + attribute \src "ls180.v:5.13-5.20" + wire input 1 \uart_tx + attribute \src "ls180.v:815.5-815.17" + wire \wb_sdram_ack + attribute \src "ls180.v:809.13-809.25" + wire width 30 \wb_sdram_adr + attribute \src "ls180.v:818.12-818.24" + wire width 2 \wb_sdram_bte + attribute \src "ls180.v:817.12-817.24" + wire width 3 \wb_sdram_cti + attribute \src "ls180.v:813.6-813.18" + wire \wb_sdram_cyc + attribute \src "ls180.v:811.13-811.27" + wire width 32 \wb_sdram_dat_r + attribute \src "ls180.v:810.13-810.27" + wire width 32 \wb_sdram_dat_w + attribute \src "ls180.v:819.5-819.17" + wire \wb_sdram_err + attribute \src "ls180.v:812.12-812.24" + wire width 4 \wb_sdram_sel + attribute \src "ls180.v:814.6-814.18" + wire \wb_sdram_stb + attribute \src "ls180.v:816.6-816.17" + wire \wb_sdram_we + attribute \src "ls180.v:833.5-833.19" + wire \wdata_consumed + attribute \src "ls180.v:5493.12-5493.15" + memory width 32 size 128 \mem + attribute \src "ls180.v:5513.12-5513.17" + memory width 32 size 32 \mem_1 + attribute \src "ls180.v:5533.12-5533.19" memory width 25 size 8 \storage - attribute \src "ls180.v:10505.12-10505.21" + attribute \src "ls180.v:5547.12-5547.21" memory width 25 size 8 \storage_1 - attribute \src "ls180.v:10519.12-10519.21" + attribute \src "ls180.v:5561.12-5561.21" memory width 25 size 8 \storage_2 - attribute \src "ls180.v:10533.12-10533.21" + attribute \src "ls180.v:5575.12-5575.21" memory width 25 size 8 \storage_3 - attribute \src "ls180.v:10547.11-10547.20" + attribute \src "ls180.v:5589.11-5589.20" memory width 10 size 16 \storage_4 - attribute \src "ls180.v:10564.11-10564.20" + attribute \src "ls180.v:5606.11-5606.20" memory width 10 size 16 \storage_5 - attribute \src "ls180.v:10581.11-10581.20" - memory width 10 size 32 \storage_6 - attribute \src "ls180.v:10595.11-10595.20" - memory width 10 size 32 \storage_7 - attribute \src "ls180.v:2935.56-2935.86" - cell $add $add$ls180.v:2935$58 + attribute \src "ls180.v:1561.76-1561.113" + cell $add $add$ls180.v:1561$25 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_converter0_counter + connect \A \libresocsim_converter0_counter connect \B 1'1 - connect \Y $add$ls180.v:2935$58_Y + connect \Y $add$ls180.v:1561$25_Y end - attribute \src "ls180.v:2995.56-2995.86" - cell $add $add$ls180.v:2995$69 + attribute \src "ls180.v:1621.76-1621.113" + cell $add $add$ls180.v:1621$36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_converter1_counter + connect \A \libresocsim_converter1_counter connect \B 1'1 - connect \Y $add$ls180.v:2995$69_Y + connect \Y $add$ls180.v:1621$36_Y end - attribute \src "ls180.v:3055.59-3055.92" - cell $add $add$ls180.v:3055$80 + attribute \src "ls180.v:1681.76-1681.113" + cell $add $add$ls180.v:1681$47 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_socbushandler_counter + connect \A \libresocsim_converter2_counter connect \B 1'1 - connect \Y $add$ls180.v:3055$80_Y + connect \Y $add$ls180.v:1681$47_Y end - attribute \src "ls180.v:4248.54-4248.83" - cell $add $add$ls180.v:4248$685 + attribute \src "ls180.v:2824.52-2824.76" + cell $add $add$ls180.v:2824$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_converter_counter + connect \A \converter_counter connect \B 1'1 - connect \Y $add$ls180.v:4248$685_Y + connect \Y $add$ls180.v:2824$553_Y end - attribute \src "ls180.v:4348.36-4348.89" - cell $add $add$ls180.v:4348$731 + attribute \src "ls180.v:2924.26-2924.59" + cell $add $add$ls180.v:2924$599 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 - connect \B \main_uart_tx_fifo_readable - connect \Y $add$ls180.v:4348$731_Y + connect \A \tx_fifo_level0 + connect \B \tx_fifo_readable + connect \Y $add$ls180.v:2924$599_Y end - attribute \src "ls180.v:4378.36-4378.89" - cell $add $add$ls180.v:4378$742 + attribute \src "ls180.v:2954.26-2954.59" + cell $add $add$ls180.v:2954$610 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 - connect \B \main_uart_rx_fifo_readable - connect \Y $add$ls180.v:4378$742_Y - end - attribute \src "ls180.v:4444.54-4444.83" - cell $add $add$ls180.v:4444$757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spimaster27_count - connect \B 1'1 - connect \Y $add$ls180.v:4444$757_Y + connect \A \rx_fifo_level0 + connect \B \rx_fifo_readable + connect \Y $add$ls180.v:2954$610_Y end - attribute \src "ls180.v:4503.52-4503.79" - cell $add $add$ls180.v:4503$765 + attribute \src "ls180.v:4357.31-4357.60" + cell $add $add$ls180.v:4357$1256 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spisdcard_count - connect \B 1'1 - connect \Y $add$ls180.v:4503$765_Y - end - attribute \src "ls180.v:4607.58-4607.86" - cell $add $add$ls180.v:4607$793 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_init_count - connect \B 1'1 - connect \Y $add$ls180.v:4607$793_Y - end - attribute \src "ls180.v:4664.58-4664.86" - cell $add $add$ls180.v:4664$796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdw_count - connect \B 1'1 - connect \Y $add$ls180.v:4664$796_Y - end - attribute \src "ls180.v:4681.58-4681.86" - cell $add $add$ls180.v:4681$798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdw_count - connect \B 1'1 - connect \Y $add$ls180.v:4681$798_Y - end - attribute \src "ls180.v:4774.59-4774.87" - cell $add $add$ls180.v:4774$815 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_count + parameter \Y_WIDTH 32 + connect \A \libresocsim_bus_errors connect \B 1'1 - connect \Y $add$ls180.v:4774$815_Y + connect \Y $add$ls180.v:4357$1256_Y end - attribute \src "ls180.v:4799.59-4799.87" - cell $add $add$ls180.v:4799$818 + attribute \src "ls180.v:4446.32-4446.62" + cell $add $add$ls180.v:4446$1280 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_count + parameter \Y_WIDTH 4 + connect \A \sdram_sequencer_counter connect \B 1'1 - connect \Y $add$ls180.v:4799$818_Y + connect \Y $add$ls180.v:4446$1280_Y end - attribute \src "ls180.v:4921.53-4921.82" - cell $add $add$ls180.v:4921$835 + attribute \src "ls180.v:4463.55-4463.109" + cell $add $add$ls180.v:4463$1284 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_dataw_count + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:4921$835_Y + connect \Y $add$ls180.v:4463$1284_Y end - attribute \src "ls180.v:5032.65-5032.114" - cell $add $add$ls180.v:5032$849 + attribute \src "ls180.v:4466.55-4466.109" + cell $add $add$ls180.v:4466$1285 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_sink_payload_block_length - connect \B 4'1000 - connect \Y $add$ls180.v:5032$849_Y - end - attribute \src "ls180.v:5037.62-5037.91" - cell $add $add$ls180.v:5037$852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_count + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:5037$852_Y + connect \Y $add$ls180.v:4466$1285_Y end - attribute \src "ls180.v:5063.61-5063.90" - cell $add $add$ls180.v:5063$855 + attribute \src "ls180.v:4470.54-4470.106" + cell $add $add$ls180.v:4470$1290 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_count + parameter \Y_WIDTH 4 + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:5063$855_Y + connect \Y $add$ls180.v:4470$1290_Y end - attribute \src "ls180.v:5267.80-5267.117" - cell $add $add$ls180.v:5267$1040 + attribute \src "ls180.v:4509.55-4509.109" + cell $add $add$ls180.v:4509$1300 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \main_sdcore_crc16_inserter_cnt + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:5267$1040_Y + connect \Y $add$ls180.v:4509$1300_Y end - attribute \src "ls180.v:5461.54-5461.82" - cell $add $add$ls180.v:5461$1115 + attribute \src "ls180.v:4512.55-4512.109" + cell $add $add$ls180.v:4512$1301 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \main_sdcore_cmd_count + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:5461$1115_Y + connect \Y $add$ls180.v:4512$1301_Y end - attribute \src "ls180.v:5513.55-5513.84" - cell $add $add$ls180.v:5513$1125 + attribute \src "ls180.v:4516.54-4516.106" + cell $add $add$ls180.v:4516$1306 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_data_count - connect \B 1'1 - connect \Y $add$ls180.v:5513$1125_Y - end - attribute \src "ls180.v:5539.57-5539.86" - cell $add $add$ls180.v:5539$1133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_data_count - connect \B 1'1 - connect \Y $add$ls180.v:5539$1133_Y - end - attribute \src "ls180.v:5660.51-5660.134" - cell $add $add$ls180.v:5660$1149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_base - connect \B \main_sdblock2mem_wishbonedmawriter_offset - connect \Y $add$ls180.v:5660$1149_Y - end - attribute \src "ls180.v:5663.77-5663.125" - cell $add $add$ls180.v:5663$1151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_offset + parameter \Y_WIDTH 4 + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:5663$1151_Y - end - attribute \src "ls180.v:5756.50-5756.105" - cell $add $add$ls180.v:5756$1160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_base - connect \B \main_sdmem2block_dma_offset - connect \Y $add$ls180.v:5756$1160_Y + connect \Y $add$ls180.v:4516$1306_Y end - attribute \src "ls180.v:5758.77-5758.111" - cell $add $add$ls180.v:5758$1161 + attribute \src "ls180.v:4555.55-4555.109" + cell $add $add$ls180.v:4555$1316 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_offset + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:5758$1161_Y + connect \Y $add$ls180.v:4555$1316_Y end - attribute \src "ls180.v:7765.36-7765.70" - cell $add $add$ls180.v:7765$2604 + attribute \src "ls180.v:4558.55-4558.109" + cell $add $add$ls180.v:4558$1317 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_libresocsim_bus_errors + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7765$2604_Y + connect \Y $add$ls180.v:4558$1317_Y end - attribute \src "ls180.v:7866.37-7866.72" - cell $add $add$ls180.v:7866$2637 + attribute \src "ls180.v:4562.54-4562.106" + cell $add $add$ls180.v:4562$1322 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_sdram_sequencer_counter + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7866$2637_Y + connect \Y $add$ls180.v:4562$1322_Y end - attribute \src "ls180.v:7883.60-7883.119" - cell $add $add$ls180.v:7883$2641 + attribute \src "ls180.v:4601.55-4601.109" + cell $add $add$ls180.v:4601$1332 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7883$2641_Y + connect \Y $add$ls180.v:4601$1332_Y end - attribute \src "ls180.v:7886.60-7886.119" - cell $add $add$ls180.v:7886$2642 + attribute \src "ls180.v:4604.55-4604.109" + cell $add $add$ls180.v:4604$1333 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7886$2642_Y + connect \Y $add$ls180.v:4604$1333_Y end - attribute \src "ls180.v:7890.59-7890.116" - cell $add $add$ls180.v:7890$2647 + attribute \src "ls180.v:4608.54-4608.106" + cell $add $add$ls180.v:4608$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7890$2647_Y + connect \Y $add$ls180.v:4608$1338_Y end - attribute \src "ls180.v:7929.60-7929.119" - cell $add $add$ls180.v:7929$2657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7929$2657_Y - end - attribute \src "ls180.v:7932.60-7932.119" - cell $add $add$ls180.v:7932$2658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7932$2658_Y - end - attribute \src "ls180.v:7936.59-7936.116" - cell $add $add$ls180.v:7936$2663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7936$2663_Y - end - attribute \src "ls180.v:7975.60-7975.119" - cell $add $add$ls180.v:7975$2673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7975$2673_Y - end - attribute \src "ls180.v:7978.60-7978.119" - cell $add $add$ls180.v:7978$2674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7978$2674_Y - end - attribute \src "ls180.v:7982.59-7982.116" - cell $add $add$ls180.v:7982$2679 + attribute \src "ls180.v:4838.29-4838.56" + cell $add $add$ls180.v:4838$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \A \uart_phy_tx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:7982$2679_Y + connect \Y $add$ls180.v:4838$1392_Y end - attribute \src "ls180.v:8021.60-8021.119" - cell $add $add$ls180.v:8021$2689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:8021$2689_Y - end - attribute \src "ls180.v:8024.60-8024.119" - cell $add $add$ls180.v:8024$2690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:8024$2690_Y - end - attribute \src "ls180.v:8028.59-8028.116" - cell $add $add$ls180.v:8028$2695 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:8028$2695_Y - end - attribute \src "ls180.v:8258.34-8258.66" - cell $add $add$ls180.v:8258$2749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_phy_tx_bitcount - connect \B 1'1 - connect \Y $add$ls180.v:8258$2749_Y - end - attribute \src "ls180.v:8274.73-8274.131" - cell $add $add$ls180.v:8274$2752 + attribute \src "ls180.v:4854.63-4854.111" + cell $add $add$ls180.v:4854$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 33 - connect \A \main_uart_phy_phase_accumulator_tx - connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8274$2752_Y + connect \A \uart_phy_phase_accumulator_tx + connect \B \uart_phy_storage + connect \Y $add$ls180.v:4854$1395_Y end - attribute \src "ls180.v:8287.34-8287.66" - cell $add $add$ls180.v:8287$2756 + attribute \src "ls180.v:4867.29-4867.56" + cell $add $add$ls180.v:4867$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_uart_phy_rx_bitcount + connect \A \uart_phy_rx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8287$2756_Y + connect \Y $add$ls180.v:4867$1399_Y end - attribute \src "ls180.v:8306.73-8306.131" - cell $add $add$ls180.v:8306$2759 + attribute \src "ls180.v:4886.63-4886.111" + cell $add $add$ls180.v:4886$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 33 - connect \A \main_uart_phy_phase_accumulator_rx - connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8306$2759_Y + connect \A \uart_phy_phase_accumulator_rx + connect \B \uart_phy_storage + connect \Y $add$ls180.v:4886$1402_Y end - attribute \src "ls180.v:8332.33-8332.65" - cell $add $add$ls180.v:8332$2767 + attribute \src "ls180.v:4912.23-4912.45" + cell $add $add$ls180.v:4912$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_produce + connect \A \tx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8332$2767_Y + connect \Y $add$ls180.v:4912$1410_Y end - attribute \src "ls180.v:8335.33-8335.65" - cell $add $add$ls180.v:8335$2768 + attribute \src "ls180.v:4915.23-4915.45" + cell $add $add$ls180.v:4915$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_consume + connect \A \tx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8335$2768_Y + connect \Y $add$ls180.v:4915$1411_Y end - attribute \src "ls180.v:8339.33-8339.64" - cell $add $add$ls180.v:8339$2773 + attribute \src "ls180.v:4919.23-4919.44" + cell $add $add$ls180.v:4919$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 + connect \A \tx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8339$2773_Y + connect \Y $add$ls180.v:4919$1416_Y end - attribute \src "ls180.v:8354.33-8354.65" - cell $add $add$ls180.v:8354$2778 + attribute \src "ls180.v:4934.23-4934.45" + cell $add $add$ls180.v:4934$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_produce + connect \A \rx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8354$2778_Y + connect \Y $add$ls180.v:4934$1421_Y end - attribute \src "ls180.v:8357.33-8357.65" - cell $add $add$ls180.v:8357$2779 + attribute \src "ls180.v:4937.23-4937.45" + cell $add $add$ls180.v:4937$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_consume + connect \A \rx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8357$2779_Y + connect \Y $add$ls180.v:4937$1422_Y end - attribute \src "ls180.v:8361.33-8361.64" - cell $add $add$ls180.v:8361$2784 + attribute \src "ls180.v:4941.23-4941.44" + cell $add $add$ls180.v:4941$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 + connect \A \rx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8361$2784_Y + connect \Y $add$ls180.v:4941$1427_Y end - attribute \src "ls180.v:8382.35-8382.70" - cell $add $add$ls180.v:8382$2786 + attribute \src "ls180.v:1555.9-1555.70" + cell $and $and$ls180.v:1555$20 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spimaster30_clk_divider - connect \B 1'1 - connect \Y $add$ls180.v:8382$2786_Y + parameter \Y_WIDTH 1 + connect \A \libresocsim_libresoc_ibus_stb + connect \B \libresocsim_libresoc_ibus_cyc + connect \Y $and$ls180.v:1555$20_Y end - attribute \src "ls180.v:8417.34-8417.68" - cell $add $add$ls180.v:8417$2791 + attribute \src "ls180.v:1573.9-1573.70" + cell $and $and$ls180.v:1573$27 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spisdcard_clk_divider1 - connect \B 1'1 - connect \Y $add$ls180.v:8417$2791_Y + parameter \Y_WIDTH 1 + connect \A \libresocsim_libresoc_ibus_stb + connect \B \libresocsim_libresoc_ibus_cyc + connect \Y $and$ls180.v:1573$27_Y end - attribute \src "ls180.v:8453.25-8453.49" - cell $add $add$ls180.v:8453$2796 + attribute \src "ls180.v:1615.9-1615.70" + cell $and $and$ls180.v:1615$31 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm0_counter - connect \B 1'1 - connect \Y $add$ls180.v:8453$2796_Y + parameter \Y_WIDTH 1 + connect \A \libresocsim_libresoc_dbus_stb + connect \B \libresocsim_libresoc_dbus_cyc + connect \Y $and$ls180.v:1615$31_Y end - attribute \src "ls180.v:8467.25-8467.49" - cell $add $add$ls180.v:8467$2800 + attribute \src "ls180.v:1633.9-1633.70" + cell $and $and$ls180.v:1633$38 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm1_counter - connect \B 1'1 - connect \Y $add$ls180.v:8467$2800_Y + parameter \Y_WIDTH 1 + connect \A \libresocsim_libresoc_dbus_stb + connect \B \libresocsim_libresoc_dbus_cyc + connect \Y $and$ls180.v:1633$38_Y end - attribute \src "ls180.v:8481.31-8481.61" - cell $add $add$ls180.v:8481$2805 + attribute \src "ls180.v:1675.9-1675.76" + cell $and $and$ls180.v:1675$42 parameter \A_SIGNED 0 - parameter \A_WIDTH 9 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 9 - connect \A \main_sdphy_clocker_clks - connect \B 1'1 - connect \Y $add$ls180.v:8481$2805_Y + parameter \Y_WIDTH 1 + connect \A \libresocsim_libresoc_jtag_wb_stb + connect \B \libresocsim_libresoc_jtag_wb_cyc + connect \Y $and$ls180.v:1675$42_Y end - attribute \src "ls180.v:8504.45-8504.88" - cell $add $add$ls180.v:8504$2809 + attribute \src "ls180.v:1693.9-1693.76" + cell $and $and$ls180.v:1693$49 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8504$2809_Y + parameter \Y_WIDTH 1 + connect \A \libresocsim_libresoc_jtag_wb_stb + connect \B \libresocsim_libresoc_jtag_wb_cyc + connect \Y $and$ls180.v:1693$49_Y end - attribute \src "ls180.v:8550.71-8550.114" - cell $add $add$ls180.v:8550$2815 + attribute \src "ls180.v:1703.26-1703.75" + cell $and $and$ls180.v:1703$51 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8550$2815_Y + parameter \Y_WIDTH 1 + connect \A \libresocsim_ram_bus_cyc + connect \B \libresocsim_ram_bus_stb + connect \Y $and$ls180.v:1703$51_Y end - attribute \src "ls180.v:8585.46-8585.90" - cell $add $add$ls180.v:8585$2821 + attribute \src "ls180.v:1703.25-1703.101" + cell $and $and$ls180.v:1703$52 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8585$2821_Y + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:1703$51_Y + connect \B \libresocsim_ram_bus_we + connect \Y $and$ls180.v:1703$52_Y end - attribute \src "ls180.v:8631.72-8631.116" - cell $add $add$ls180.v:8631$2827 + attribute \src "ls180.v:1703.24-1703.131" + cell $and $and$ls180.v:1703$53 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8631$2827_Y + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:1703$52_Y + connect \B \libresocsim_ram_bus_sel [0] + connect \Y $and$ls180.v:1703$53_Y end - attribute \src "ls180.v:8664.47-8664.92" - cell $add $add$ls180.v:8664$2833 + attribute \src "ls180.v:1704.26-1704.75" + cell $and $and$ls180.v:1704$54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8664$2833_Y + connect \A \libresocsim_ram_bus_cyc + connect \B \libresocsim_ram_bus_stb + connect \Y $and$ls180.v:1704$54_Y end - attribute \src "ls180.v:8692.73-8692.118" - cell $add $add$ls180.v:8692$2839 + attribute \src "ls180.v:1704.25-1704.101" + cell $and $and$ls180.v:1704$55 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8692$2839_Y + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:1704$54_Y + connect \B \libresocsim_ram_bus_we + connect \Y $and$ls180.v:1704$55_Y end - attribute \src "ls180.v:8804.39-8804.75" - cell $add $add$ls180.v:8804$2852 + attribute \src "ls180.v:1704.24-1704.131" + cell $and $and$ls180.v:1704$56 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 1'1 - connect \Y $add$ls180.v:8804$2852_Y + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:1704$55_Y + connect \B \libresocsim_ram_bus_sel [1] + connect \Y $and$ls180.v:1704$56_Y end - attribute \src "ls180.v:8865.37-8865.73" - cell $add $add$ls180.v:8865$2856 + attribute \src "ls180.v:1705.26-1705.75" + cell $and $and$ls180.v:1705$57 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8865$2856_Y + parameter \Y_WIDTH 1 + connect \A \libresocsim_ram_bus_cyc + connect \B \libresocsim_ram_bus_stb + connect \Y $and$ls180.v:1705$57_Y end - attribute \src "ls180.v:8868.37-8868.73" - cell $add $add$ls180.v:8868$2857 + attribute \src "ls180.v:1705.25-1705.101" + cell $and $and$ls180.v:1705$58 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8868$2857_Y + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:1705$57_Y + connect \B \libresocsim_ram_bus_we + connect \Y $and$ls180.v:1705$58_Y end - attribute \src "ls180.v:8872.36-8872.70" - cell $add $add$ls180.v:8872$2862 + attribute \src "ls180.v:1705.24-1705.131" + cell $and $and$ls180.v:1705$59 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'1 - connect \Y $add$ls180.v:8872$2862_Y + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:1705$58_Y + connect \B \libresocsim_ram_bus_sel [2] + connect \Y $and$ls180.v:1705$59_Y end - attribute \src "ls180.v:8887.41-8887.80" - cell $add $add$ls180.v:8887$2866 + attribute \src "ls180.v:1706.26-1706.75" + cell $and $and$ls180.v:1706$60 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdblock2mem_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8887$2866_Y + parameter \Y_WIDTH 1 + connect \A \libresocsim_ram_bus_cyc + connect \B \libresocsim_ram_bus_stb + connect \Y $and$ls180.v:1706$60_Y end - attribute \src "ls180.v:8933.67-8933.106" - cell $add $add$ls180.v:8933$2872 + attribute \src "ls180.v:1706.25-1706.101" + cell $and $and$ls180.v:1706$61 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdblock2mem_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8933$2872_Y + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:1706$60_Y + connect \B \libresocsim_ram_bus_we + connect \Y $and$ls180.v:1706$61_Y end - attribute \src "ls180.v:8959.39-8959.76" - cell $add $add$ls180.v:8959$2874 + attribute \src "ls180.v:1706.24-1706.131" + cell $and $and$ls180.v:1706$62 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdmem2block_converter_mux - connect \B 1'1 - connect \Y $add$ls180.v:8959$2874_Y + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:1706$61_Y + connect \B \libresocsim_ram_bus_sel [3] + connect \Y $and$ls180.v:1706$62_Y end - attribute \src "ls180.v:8963.37-8963.73" - cell $add $add$ls180.v:8963$2878 + attribute \src "ls180.v:1715.7-1715.79" + cell $and $and$ls180.v:1715$65 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8963$2878_Y + parameter \Y_WIDTH 1 + connect \A \libresocsim_eventmanager_pending_re + connect \B \libresocsim_eventmanager_pending_r + connect \Y $and$ls180.v:1715$65_Y end - attribute \src "ls180.v:8966.37-8966.73" - cell $add $add$ls180.v:8966$2879 + attribute \src "ls180.v:1720.27-1720.96" + cell $and $and$ls180.v:1720$66 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8966$2879_Y + parameter \Y_WIDTH 1 + connect \A \libresocsim_eventmanager_pending_w + connect \B \libresocsim_eventmanager_storage + connect \Y $and$ls180.v:1720$66_Y end - attribute \src "ls180.v:8970.36-8970.70" - cell $add $add$ls180.v:8970$2884 + attribute \src "ls180.v:1724.18-1724.59" + cell $and $and$ls180.v:1724$68 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdmem2block_fifo_level - connect \B 1'1 - connect \Y $add$ls180.v:8970$2884_Y + parameter \Y_WIDTH 1 + connect \A \ram_bus_ram_bus_cyc + connect \B \ram_bus_ram_bus_stb + connect \Y $and$ls180.v:1724$68_Y end - attribute \src "ls180.v:2929.9-2929.90" - cell $and $and$ls180.v:2929$53 + attribute \src "ls180.v:1724.17-1724.81" + cell $and $and$ls180.v:1724$69 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface0_converted_interface_stb - connect \B \main_interface0_converted_interface_cyc - connect \Y $and$ls180.v:2929$53_Y + connect \A $and$ls180.v:1724$68_Y + connect \B \ram_bus_ram_bus_we + connect \Y $and$ls180.v:1724$69_Y end - attribute \src "ls180.v:2947.9-2947.90" - cell $and $and$ls180.v:2947$60 + attribute \src "ls180.v:1724.16-1724.107" + cell $and $and$ls180.v:1724$70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface0_converted_interface_stb - connect \B \main_interface0_converted_interface_cyc - connect \Y $and$ls180.v:2947$60_Y + connect \A $and$ls180.v:1724$69_Y + connect \B \ram_bus_ram_bus_sel [0] + connect \Y $and$ls180.v:1724$70_Y end - attribute \src "ls180.v:2989.9-2989.90" - cell $and $and$ls180.v:2989$64 + attribute \src "ls180.v:1725.18-1725.59" + cell $and $and$ls180.v:1725$71 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_converted_interface_stb - connect \B \main_interface1_converted_interface_cyc - connect \Y $and$ls180.v:2989$64_Y + connect \A \ram_bus_ram_bus_cyc + connect \B \ram_bus_ram_bus_stb + connect \Y $and$ls180.v:1725$71_Y end - attribute \src "ls180.v:3007.9-3007.90" - cell $and $and$ls180.v:3007$71 + attribute \src "ls180.v:1725.17-1725.81" + cell $and $and$ls180.v:1725$72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_converted_interface_stb - connect \B \main_interface1_converted_interface_cyc - connect \Y $and$ls180.v:3007$71_Y + connect \A $and$ls180.v:1725$71_Y + connect \B \ram_bus_ram_bus_we + connect \Y $and$ls180.v:1725$72_Y end - attribute \src "ls180.v:3049.9-3049.96" - cell $and $and$ls180.v:3049$75 + attribute \src "ls180.v:1725.16-1725.107" + cell $and $and$ls180.v:1725$73 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_socbushandler_converted_interface_stb - connect \B \main_socbushandler_converted_interface_cyc - connect \Y $and$ls180.v:3049$75_Y + connect \A $and$ls180.v:1725$72_Y + connect \B \ram_bus_ram_bus_sel [1] + connect \Y $and$ls180.v:1725$73_Y end - attribute \src "ls180.v:3067.9-3067.96" - cell $and $and$ls180.v:3067$82 + attribute \src "ls180.v:1726.18-1726.59" + cell $and $and$ls180.v:1726$74 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_socbushandler_converted_interface_stb - connect \B \main_socbushandler_converted_interface_cyc - connect \Y $and$ls180.v:3067$82_Y + connect \A \ram_bus_ram_bus_cyc + connect \B \ram_bus_ram_bus_stb + connect \Y $and$ls180.v:1726$74_Y end - attribute \src "ls180.v:3077.31-3077.90" - cell $and $and$ls180.v:3077$84 + attribute \src "ls180.v:1726.17-1726.81" + cell $and $and$ls180.v:1726$75 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3077$84_Y + connect \A $and$ls180.v:1726$74_Y + connect \B \ram_bus_ram_bus_we + connect \Y $and$ls180.v:1726$75_Y end - attribute \src "ls180.v:3077.30-3077.121" - cell $and $and$ls180.v:3077$85 + attribute \src "ls180.v:1726.16-1726.107" + cell $and $and$ls180.v:1726$76 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3077$84_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3077$85_Y + connect \A $and$ls180.v:1726$75_Y + connect \B \ram_bus_ram_bus_sel [2] + connect \Y $and$ls180.v:1726$76_Y end - attribute \src "ls180.v:3077.29-3077.156" - cell $and $and$ls180.v:3077$86 + attribute \src "ls180.v:1727.18-1727.59" + cell $and $and$ls180.v:1727$77 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3077$85_Y - connect \B \main_libresocsim_ram_bus_sel [0] - connect \Y $and$ls180.v:3077$86_Y + connect \A \ram_bus_ram_bus_cyc + connect \B \ram_bus_ram_bus_stb + connect \Y $and$ls180.v:1727$77_Y end - attribute \src "ls180.v:3078.31-3078.90" - cell $and $and$ls180.v:3078$87 + attribute \src "ls180.v:1727.17-1727.81" + cell $and $and$ls180.v:1727$78 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3078$87_Y + connect \A $and$ls180.v:1727$77_Y + connect \B \ram_bus_ram_bus_we + connect \Y $and$ls180.v:1727$78_Y end - attribute \src "ls180.v:3078.30-3078.121" - cell $and $and$ls180.v:3078$88 + attribute \src "ls180.v:1727.16-1727.107" + cell $and $and$ls180.v:1727$79 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3078$87_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3078$88_Y + connect \A $and$ls180.v:1727$78_Y + connect \B \ram_bus_ram_bus_sel [3] + connect \Y $and$ls180.v:1727$79_Y end - attribute \src "ls180.v:3078.29-3078.156" - cell $and $and$ls180.v:3078$89 + attribute \src "ls180.v:1844.35-1844.84" + cell $and $and$ls180.v:1844$86 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3078$88_Y - connect \B \main_libresocsim_ram_bus_sel [1] - connect \Y $and$ls180.v:3078$89_Y + connect \A \sdram_command_issue_re + connect \B \sdram_command_storage [4] + connect \Y $and$ls180.v:1844$86_Y end - attribute \src "ls180.v:3079.31-3079.90" - cell $and $and$ls180.v:3079$90 + attribute \src "ls180.v:1845.35-1845.84" + cell $and $and$ls180.v:1845$87 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3079$90_Y + connect \A \sdram_command_issue_re + connect \B \sdram_command_storage [5] + connect \Y $and$ls180.v:1845$87_Y end - attribute \src "ls180.v:3079.30-3079.121" - cell $and $and$ls180.v:3079$91 + attribute \src "ls180.v:1883.33-1883.88" + cell $and $and$ls180.v:1883$93 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3079$90_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3079$91_Y + connect \A \sdram_sequencer_done1 + connect \B $eq$ls180.v:1883$92_Y + connect \Y $and$ls180.v:1883$93_Y end - attribute \src "ls180.v:3079.29-3079.156" - cell $and $and$ls180.v:3079$92 + attribute \src "ls180.v:1937.45-1937.104" + cell $and $and$ls180.v:1937$101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3079$91_Y - connect \B \main_libresocsim_ram_bus_sel [2] - connect \Y $and$ls180.v:3079$92_Y + connect \A \sdram_bankmachine0_cmd_valid + connect \B \sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:1937$101_Y end - attribute \src "ls180.v:3080.31-3080.90" - cell $and $and$ls180.v:3080$93 + attribute \src "ls180.v:1937.44-1937.147" + cell $and $and$ls180.v:1937$102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3080$93_Y + connect \A $and$ls180.v:1937$101_Y + connect \B \sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:1937$102_Y end - attribute \src "ls180.v:3080.30-3080.121" - cell $and $and$ls180.v:3080$94 + attribute \src "ls180.v:1938.44-1938.103" + cell $and $and$ls180.v:1938$103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3080$93_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3080$94_Y + connect \A \sdram_bankmachine0_cmd_valid + connect \B \sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:1938$103_Y end - attribute \src "ls180.v:3080.29-3080.156" - cell $and $and$ls180.v:3080$95 + attribute \src "ls180.v:1938.43-1938.134" + cell $and $and$ls180.v:1938$104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3080$94_Y - connect \B \main_libresocsim_ram_bus_sel [3] - connect \Y $and$ls180.v:3080$95_Y + connect \A $and$ls180.v:1938$103_Y + connect \B \sdram_bankmachine0_row_open + connect \Y $and$ls180.v:1938$104_Y end - attribute \src "ls180.v:3081.31-3081.90" - cell $and $and$ls180.v:3081$96 + attribute \src "ls180.v:1939.45-1939.104" + cell $and $and$ls180.v:1939$105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3081$96_Y + connect \A \sdram_bankmachine0_cmd_valid + connect \B \sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:1939$105_Y end - attribute \src "ls180.v:3081.30-3081.121" - cell $and $and$ls180.v:3081$97 + attribute \src "ls180.v:1939.44-1939.135" + cell $and $and$ls180.v:1939$106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3081$96_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3081$97_Y + connect \A $and$ls180.v:1939$105_Y + connect \B \sdram_bankmachine0_row_open + connect \Y $and$ls180.v:1939$106_Y end - attribute \src "ls180.v:3081.29-3081.156" - cell $and $and$ls180.v:3081$98 + attribute \src "ls180.v:1942.7-1942.104" + cell $and $and$ls180.v:1942$108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3081$97_Y - connect \B \main_libresocsim_ram_bus_sel [4] - connect \Y $and$ls180.v:3081$98_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $and$ls180.v:1942$108_Y end - attribute \src "ls180.v:3082.30-3082.121" - cell $and $and$ls180.v:3082$100 + attribute \src "ls180.v:1971.61-1971.226" + cell $and $and$ls180.v:1971$114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3082$99_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3082$100_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B $or$ls180.v:1971$113_Y + connect \Y $and$ls180.v:1971$114_Y end - attribute \src "ls180.v:3082.29-3082.156" - cell $and $and$ls180.v:3082$101 + attribute \src "ls180.v:1972.59-1972.172" + cell $and $and$ls180.v:1972$115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3082$100_Y - connect \B \main_libresocsim_ram_bus_sel [5] - connect \Y $and$ls180.v:3082$101_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + connect \Y $and$ls180.v:1972$115_Y end - attribute \src "ls180.v:3082.31-3082.90" - cell $and $and$ls180.v:3082$99 + attribute \src "ls180.v:1996.9-1996.76" + cell $and $and$ls180.v:1996$121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3082$99_Y + connect \A \sdram_bankmachine0_twtpcon_ready + connect \B \sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:1996$121_Y end - attribute \src "ls180.v:3083.31-3083.90" - cell $and $and$ls180.v:3083$102 + attribute \src "ls180.v:2008.9-2008.76" + cell $and $and$ls180.v:2008$122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3083$102_Y + connect \A \sdram_bankmachine0_twtpcon_ready + connect \B \sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:2008$122_Y end - attribute \src "ls180.v:3083.30-3083.121" - cell $and $and$ls180.v:3083$103 + attribute \src "ls180.v:2058.13-2058.77" + cell $and $and$ls180.v:2058$124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3083$102_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3083$103_Y + connect \A \sdram_bankmachine0_cmd_ready + connect \B \sdram_bankmachine0_auto_precharge + connect \Y $and$ls180.v:2058$124_Y end - attribute \src "ls180.v:3083.29-3083.156" - cell $and $and$ls180.v:3083$104 + attribute \src "ls180.v:2094.45-2094.104" + cell $and $and$ls180.v:2094$131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3083$103_Y - connect \B \main_libresocsim_ram_bus_sel [6] - connect \Y $and$ls180.v:3083$104_Y + connect \A \sdram_bankmachine1_cmd_valid + connect \B \sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:2094$131_Y end - attribute \src "ls180.v:3084.31-3084.90" - cell $and $and$ls180.v:3084$105 + attribute \src "ls180.v:2094.44-2094.147" + cell $and $and$ls180.v:2094$132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3084$105_Y + connect \A $and$ls180.v:2094$131_Y + connect \B \sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:2094$132_Y end - attribute \src "ls180.v:3084.30-3084.121" - cell $and $and$ls180.v:3084$106 + attribute \src "ls180.v:2095.44-2095.103" + cell $and $and$ls180.v:2095$133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3084$105_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3084$106_Y + connect \A \sdram_bankmachine1_cmd_valid + connect \B \sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:2095$133_Y end - attribute \src "ls180.v:3084.29-3084.156" - cell $and $and$ls180.v:3084$107 + attribute \src "ls180.v:2095.43-2095.134" + cell $and $and$ls180.v:2095$134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3084$106_Y - connect \B \main_libresocsim_ram_bus_sel [7] - connect \Y $and$ls180.v:3084$107_Y + connect \A $and$ls180.v:2095$133_Y + connect \B \sdram_bankmachine1_row_open + connect \Y $and$ls180.v:2095$134_Y end - attribute \src "ls180.v:3093.7-3093.89" - cell $and $and$ls180.v:3093$110 + attribute \src "ls180.v:2096.45-2096.104" + cell $and $and$ls180.v:2096$135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_eventmanager_pending_re - connect \B \main_libresocsim_eventmanager_pending_r - connect \Y $and$ls180.v:3093$110_Y + connect \A \sdram_bankmachine1_cmd_valid + connect \B \sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:2096$135_Y end - attribute \src "ls180.v:3098.32-3098.111" - cell $and $and$ls180.v:3098$111 + attribute \src "ls180.v:2096.44-2096.135" + cell $and $and$ls180.v:2096$136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_eventmanager_pending_w - connect \B \main_libresocsim_eventmanager_storage - connect \Y $and$ls180.v:3098$111_Y + connect \A $and$ls180.v:2096$135_Y + connect \B \sdram_bankmachine1_row_open + connect \Y $and$ls180.v:2096$136_Y end - attribute \src "ls180.v:3102.25-3102.82" - cell $and $and$ls180.v:3102$113 + attribute \src "ls180.v:2099.7-2099.104" + cell $and $and$ls180.v:2099$138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3102$113_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $and$ls180.v:2099$138_Y end - attribute \src "ls180.v:3102.24-3102.112" - cell $and $and$ls180.v:3102$114 + attribute \src "ls180.v:2128.61-2128.226" + cell $and $and$ls180.v:2128$144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3102$113_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3102$114_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B $or$ls180.v:2128$143_Y + connect \Y $and$ls180.v:2128$144_Y end - attribute \src "ls180.v:3102.23-3102.146" - cell $and $and$ls180.v:3102$115 + attribute \src "ls180.v:2129.59-2129.172" + cell $and $and$ls180.v:2129$145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3102$114_Y - connect \B \main_interface0_ram_bus_sel [0] - connect \Y $and$ls180.v:3102$115_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + connect \Y $and$ls180.v:2129$145_Y end - attribute \src "ls180.v:3103.25-3103.82" - cell $and $and$ls180.v:3103$116 + attribute \src "ls180.v:2153.9-2153.76" + cell $and $and$ls180.v:2153$151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3103$116_Y + connect \A \sdram_bankmachine1_twtpcon_ready + connect \B \sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:2153$151_Y end - attribute \src "ls180.v:3103.24-3103.112" - cell $and $and$ls180.v:3103$117 + attribute \src "ls180.v:2165.9-2165.76" + cell $and $and$ls180.v:2165$152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3103$116_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3103$117_Y + connect \A \sdram_bankmachine1_twtpcon_ready + connect \B \sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:2165$152_Y end - attribute \src "ls180.v:3103.23-3103.146" - cell $and $and$ls180.v:3103$118 + attribute \src "ls180.v:2215.13-2215.77" + cell $and $and$ls180.v:2215$154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3103$117_Y - connect \B \main_interface0_ram_bus_sel [1] - connect \Y $and$ls180.v:3103$118_Y + connect \A \sdram_bankmachine1_cmd_ready + connect \B \sdram_bankmachine1_auto_precharge + connect \Y $and$ls180.v:2215$154_Y end - attribute \src "ls180.v:3104.25-3104.82" - cell $and $and$ls180.v:3104$119 + attribute \src "ls180.v:2251.45-2251.104" + cell $and $and$ls180.v:2251$161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3104$119_Y + connect \A \sdram_bankmachine2_cmd_valid + connect \B \sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:2251$161_Y end - attribute \src "ls180.v:3104.24-3104.112" - cell $and $and$ls180.v:3104$120 + attribute \src "ls180.v:2251.44-2251.147" + cell $and $and$ls180.v:2251$162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3104$119_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3104$120_Y + connect \A $and$ls180.v:2251$161_Y + connect \B \sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:2251$162_Y end - attribute \src "ls180.v:3104.23-3104.146" - cell $and $and$ls180.v:3104$121 + attribute \src "ls180.v:2252.44-2252.103" + cell $and $and$ls180.v:2252$163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3104$120_Y - connect \B \main_interface0_ram_bus_sel [2] - connect \Y $and$ls180.v:3104$121_Y + connect \A \sdram_bankmachine2_cmd_valid + connect \B \sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:2252$163_Y end - attribute \src "ls180.v:3105.25-3105.82" - cell $and $and$ls180.v:3105$122 + attribute \src "ls180.v:2252.43-2252.134" + cell $and $and$ls180.v:2252$164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3105$122_Y + connect \A $and$ls180.v:2252$163_Y + connect \B \sdram_bankmachine2_row_open + connect \Y $and$ls180.v:2252$164_Y end - attribute \src "ls180.v:3105.24-3105.112" - cell $and $and$ls180.v:3105$123 + attribute \src "ls180.v:2253.45-2253.104" + cell $and $and$ls180.v:2253$165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3105$122_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3105$123_Y + connect \A \sdram_bankmachine2_cmd_valid + connect \B \sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:2253$165_Y end - attribute \src "ls180.v:3105.23-3105.146" - cell $and $and$ls180.v:3105$124 + attribute \src "ls180.v:2253.44-2253.135" + cell $and $and$ls180.v:2253$166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3105$123_Y - connect \B \main_interface0_ram_bus_sel [3] - connect \Y $and$ls180.v:3105$124_Y + connect \A $and$ls180.v:2253$165_Y + connect \B \sdram_bankmachine2_row_open + connect \Y $and$ls180.v:2253$166_Y end - attribute \src "ls180.v:3106.25-3106.82" - cell $and $and$ls180.v:3106$125 + attribute \src "ls180.v:2256.7-2256.104" + cell $and $and$ls180.v:2256$168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3106$125_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $and$ls180.v:2256$168_Y end - attribute \src "ls180.v:3106.24-3106.112" - cell $and $and$ls180.v:3106$126 + attribute \src "ls180.v:2285.61-2285.226" + cell $and $and$ls180.v:2285$174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3106$125_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3106$126_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B $or$ls180.v:2285$173_Y + connect \Y $and$ls180.v:2285$174_Y end - attribute \src "ls180.v:3106.23-3106.146" - cell $and $and$ls180.v:3106$127 + attribute \src "ls180.v:2286.59-2286.172" + cell $and $and$ls180.v:2286$175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3106$126_Y - connect \B \main_interface0_ram_bus_sel [4] - connect \Y $and$ls180.v:3106$127_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + connect \Y $and$ls180.v:2286$175_Y end - attribute \src "ls180.v:3107.25-3107.82" - cell $and $and$ls180.v:3107$128 + attribute \src "ls180.v:2310.9-2310.76" + cell $and $and$ls180.v:2310$181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3107$128_Y + connect \A \sdram_bankmachine2_twtpcon_ready + connect \B \sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:2310$181_Y end - attribute \src "ls180.v:3107.24-3107.112" - cell $and $and$ls180.v:3107$129 + attribute \src "ls180.v:2322.9-2322.76" + cell $and $and$ls180.v:2322$182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3107$128_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3107$129_Y + connect \A \sdram_bankmachine2_twtpcon_ready + connect \B \sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:2322$182_Y end - attribute \src "ls180.v:3107.23-3107.146" - cell $and $and$ls180.v:3107$130 + attribute \src "ls180.v:2372.13-2372.77" + cell $and $and$ls180.v:2372$184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3107$129_Y - connect \B \main_interface0_ram_bus_sel [5] - connect \Y $and$ls180.v:3107$130_Y + connect \A \sdram_bankmachine2_cmd_ready + connect \B \sdram_bankmachine2_auto_precharge + connect \Y $and$ls180.v:2372$184_Y end - attribute \src "ls180.v:3108.25-3108.82" - cell $and $and$ls180.v:3108$131 + attribute \src "ls180.v:2408.45-2408.104" + cell $and $and$ls180.v:2408$191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3108$131_Y + connect \A \sdram_bankmachine3_cmd_valid + connect \B \sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:2408$191_Y end - attribute \src "ls180.v:3108.24-3108.112" - cell $and $and$ls180.v:3108$132 + attribute \src "ls180.v:2408.44-2408.147" + cell $and $and$ls180.v:2408$192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3108$131_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3108$132_Y + connect \A $and$ls180.v:2408$191_Y + connect \B \sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:2408$192_Y end - attribute \src "ls180.v:3108.23-3108.146" - cell $and $and$ls180.v:3108$133 + attribute \src "ls180.v:2409.44-2409.103" + cell $and $and$ls180.v:2409$193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3108$132_Y - connect \B \main_interface0_ram_bus_sel [6] - connect \Y $and$ls180.v:3108$133_Y + connect \A \sdram_bankmachine3_cmd_valid + connect \B \sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:2409$193_Y end - attribute \src "ls180.v:3109.25-3109.82" - cell $and $and$ls180.v:3109$134 + attribute \src "ls180.v:2409.43-2409.134" + cell $and $and$ls180.v:2409$194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3109$134_Y + connect \A $and$ls180.v:2409$193_Y + connect \B \sdram_bankmachine3_row_open + connect \Y $and$ls180.v:2409$194_Y end - attribute \src "ls180.v:3109.24-3109.112" - cell $and $and$ls180.v:3109$135 + attribute \src "ls180.v:2410.45-2410.104" + cell $and $and$ls180.v:2410$195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3109$134_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3109$135_Y + connect \A \sdram_bankmachine3_cmd_valid + connect \B \sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:2410$195_Y end - attribute \src "ls180.v:3109.23-3109.146" - cell $and $and$ls180.v:3109$136 + attribute \src "ls180.v:2410.44-2410.135" + cell $and $and$ls180.v:2410$196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3109$135_Y - connect \B \main_interface0_ram_bus_sel [7] - connect \Y $and$ls180.v:3109$136_Y + connect \A $and$ls180.v:2410$195_Y + connect \B \sdram_bankmachine3_row_open + connect \Y $and$ls180.v:2410$196_Y end - attribute \src "ls180.v:3116.25-3116.82" - cell $and $and$ls180.v:3116$138 + attribute \src "ls180.v:2413.7-2413.104" + cell $and $and$ls180.v:2413$198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3116$138_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $and$ls180.v:2413$198_Y end - attribute \src "ls180.v:3116.24-3116.112" - cell $and $and$ls180.v:3116$139 + attribute \src "ls180.v:2442.61-2442.226" + cell $and $and$ls180.v:2442$204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3116$138_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3116$139_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B $or$ls180.v:2442$203_Y + connect \Y $and$ls180.v:2442$204_Y end - attribute \src "ls180.v:3116.23-3116.146" - cell $and $and$ls180.v:3116$140 + attribute \src "ls180.v:2443.59-2443.172" + cell $and $and$ls180.v:2443$205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3116$139_Y - connect \B \main_interface1_ram_bus_sel [0] - connect \Y $and$ls180.v:3116$140_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + connect \Y $and$ls180.v:2443$205_Y end - attribute \src "ls180.v:3117.25-3117.82" - cell $and $and$ls180.v:3117$141 + attribute \src "ls180.v:2467.9-2467.76" + cell $and $and$ls180.v:2467$211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3117$141_Y + connect \A \sdram_bankmachine3_twtpcon_ready + connect \B \sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:2467$211_Y end - attribute \src "ls180.v:3117.24-3117.112" - cell $and $and$ls180.v:3117$142 + attribute \src "ls180.v:2479.9-2479.76" + cell $and $and$ls180.v:2479$212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3117$141_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3117$142_Y + connect \A \sdram_bankmachine3_twtpcon_ready + connect \B \sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:2479$212_Y end - attribute \src "ls180.v:3117.23-3117.146" - cell $and $and$ls180.v:3117$143 + attribute \src "ls180.v:2529.13-2529.77" + cell $and $and$ls180.v:2529$214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3117$142_Y - connect \B \main_interface1_ram_bus_sel [1] - connect \Y $and$ls180.v:3117$143_Y + connect \A \sdram_bankmachine3_cmd_ready + connect \B \sdram_bankmachine3_auto_precharge + connect \Y $and$ls180.v:2529$214_Y end - attribute \src "ls180.v:3118.25-3118.82" - cell $and $and$ls180.v:3118$144 + attribute \src "ls180.v:2544.32-2544.87" + cell $and $and$ls180.v:2544$215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3118$144_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2544$215_Y end - attribute \src "ls180.v:3118.24-3118.112" - cell $and $and$ls180.v:3118$145 + attribute \src "ls180.v:2544.93-2544.163" + cell $and $and$ls180.v:2544$217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3118$144_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3118$145_Y + connect \A \sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:2544$216_Y + connect \Y $and$ls180.v:2544$217_Y end - attribute \src "ls180.v:3118.23-3118.146" - cell $and $and$ls180.v:3118$146 + attribute \src "ls180.v:2544.92-2544.201" + cell $and $and$ls180.v:2544$219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3118$145_Y - connect \B \main_interface1_ram_bus_sel [2] - connect \Y $and$ls180.v:3118$146_Y + connect \A $and$ls180.v:2544$217_Y + connect \B $not$ls180.v:2544$218_Y + connect \Y $and$ls180.v:2544$219_Y end - attribute \src "ls180.v:3119.25-3119.82" - cell $and $and$ls180.v:3119$147 + attribute \src "ls180.v:2544.31-2544.202" + cell $and $and$ls180.v:2544$220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3119$147_Y + connect \A $and$ls180.v:2544$215_Y + connect \B $and$ls180.v:2544$219_Y + connect \Y $and$ls180.v:2544$220_Y end - attribute \src "ls180.v:3119.24-3119.112" - cell $and $and$ls180.v:3119$148 + attribute \src "ls180.v:2545.32-2545.87" + cell $and $and$ls180.v:2545$221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3119$147_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3119$148_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2545$221_Y end - attribute \src "ls180.v:3119.23-3119.146" - cell $and $and$ls180.v:3119$149 + attribute \src "ls180.v:2545.93-2545.163" + cell $and $and$ls180.v:2545$223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3119$148_Y - connect \B \main_interface1_ram_bus_sel [3] - connect \Y $and$ls180.v:3119$149_Y + connect \A \sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:2545$222_Y + connect \Y $and$ls180.v:2545$223_Y end - attribute \src "ls180.v:3120.25-3120.82" - cell $and $and$ls180.v:3120$150 + attribute \src "ls180.v:2545.92-2545.201" + cell $and $and$ls180.v:2545$225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3120$150_Y + connect \A $and$ls180.v:2545$223_Y + connect \B $not$ls180.v:2545$224_Y + connect \Y $and$ls180.v:2545$225_Y end - attribute \src "ls180.v:3120.24-3120.112" - cell $and $and$ls180.v:3120$151 + attribute \src "ls180.v:2545.31-2545.202" + cell $and $and$ls180.v:2545$226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3120$150_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3120$151_Y + connect \A $and$ls180.v:2545$221_Y + connect \B $and$ls180.v:2545$225_Y + connect \Y $and$ls180.v:2545$226_Y end - attribute \src "ls180.v:3120.23-3120.146" - cell $and $and$ls180.v:3120$152 + attribute \src "ls180.v:2546.29-2546.70" + cell $and $and$ls180.v:2546$227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3120$151_Y - connect \B \main_interface1_ram_bus_sel [4] - connect \Y $and$ls180.v:3120$152_Y + connect \A \sdram_trrdcon_ready + connect \B \sdram_tfawcon_ready + connect \Y $and$ls180.v:2546$227_Y end - attribute \src "ls180.v:3121.25-3121.82" - cell $and $and$ls180.v:3121$153 + attribute \src "ls180.v:2547.32-2547.87" + cell $and $and$ls180.v:2547$228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3121$153_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2547$228_Y end - attribute \src "ls180.v:3121.24-3121.112" - cell $and $and$ls180.v:3121$154 + attribute \src "ls180.v:2547.31-2547.169" + cell $and $and$ls180.v:2547$230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3121$153_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3121$154_Y + connect \A $and$ls180.v:2547$228_Y + connect \B $or$ls180.v:2547$229_Y + connect \Y $and$ls180.v:2547$230_Y end - attribute \src "ls180.v:3121.23-3121.146" - cell $and $and$ls180.v:3121$155 + attribute \src "ls180.v:2549.32-2549.87" + cell $and $and$ls180.v:2549$231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3121$154_Y - connect \B \main_interface1_ram_bus_sel [5] - connect \Y $and$ls180.v:3121$155_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2549$231_Y end - attribute \src "ls180.v:3122.25-3122.82" - cell $and $and$ls180.v:3122$156 + attribute \src "ls180.v:2549.31-2549.128" + cell $and $and$ls180.v:2549$232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3122$156_Y + connect \A $and$ls180.v:2549$231_Y + connect \B \sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:2549$232_Y end - attribute \src "ls180.v:3122.24-3122.112" - cell $and $and$ls180.v:3122$157 + attribute \src "ls180.v:2550.35-2550.104" + cell $and $and$ls180.v:2550$233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3122$156_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3122$157_Y + connect \A \sdram_bankmachine0_cmd_valid + connect \B \sdram_bankmachine0_cmd_payload_is_read + connect \Y $and$ls180.v:2550$233_Y end - attribute \src "ls180.v:3122.23-3122.146" - cell $and $and$ls180.v:3122$158 + attribute \src "ls180.v:2550.109-2550.178" + cell $and $and$ls180.v:2550$234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3122$157_Y - connect \B \main_interface1_ram_bus_sel [6] - connect \Y $and$ls180.v:3122$158_Y + connect \A \sdram_bankmachine1_cmd_valid + connect \B \sdram_bankmachine1_cmd_payload_is_read + connect \Y $and$ls180.v:2550$234_Y end - attribute \src "ls180.v:3123.25-3123.82" - cell $and $and$ls180.v:3123$159 + attribute \src "ls180.v:2550.184-2550.253" + cell $and $and$ls180.v:2550$236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3123$159_Y + connect \A \sdram_bankmachine2_cmd_valid + connect \B \sdram_bankmachine2_cmd_payload_is_read + connect \Y $and$ls180.v:2550$236_Y end - attribute \src "ls180.v:3123.24-3123.112" - cell $and $and$ls180.v:3123$160 + attribute \src "ls180.v:2550.259-2550.328" + cell $and $and$ls180.v:2550$238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3123$159_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3123$160_Y + connect \A \sdram_bankmachine3_cmd_valid + connect \B \sdram_bankmachine3_cmd_payload_is_read + connect \Y $and$ls180.v:2550$238_Y end - attribute \src "ls180.v:3123.23-3123.146" - cell $and $and$ls180.v:3123$161 + attribute \src "ls180.v:2551.36-2551.106" + cell $and $and$ls180.v:2551$240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3123$160_Y - connect \B \main_interface1_ram_bus_sel [7] - connect \Y $and$ls180.v:3123$161_Y + connect \A \sdram_bankmachine0_cmd_valid + connect \B \sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:2551$240_Y end - attribute \src "ls180.v:3130.25-3130.82" - cell $and $and$ls180.v:3130$163 + attribute \src "ls180.v:2551.111-2551.181" + cell $and $and$ls180.v:2551$241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3130$163_Y + connect \A \sdram_bankmachine1_cmd_valid + connect \B \sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:2551$241_Y end - attribute \src "ls180.v:3130.24-3130.112" - cell $and $and$ls180.v:3130$164 + attribute \src "ls180.v:2551.187-2551.257" + cell $and $and$ls180.v:2551$243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3130$163_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3130$164_Y + connect \A \sdram_bankmachine2_cmd_valid + connect \B \sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:2551$243_Y end - attribute \src "ls180.v:3130.23-3130.146" - cell $and $and$ls180.v:3130$165 + attribute \src "ls180.v:2551.263-2551.333" + cell $and $and$ls180.v:2551$245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3130$164_Y - connect \B \main_interface2_ram_bus_sel [0] - connect \Y $and$ls180.v:3130$165_Y + connect \A \sdram_bankmachine3_cmd_valid + connect \B \sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:2551$245_Y end - attribute \src "ls180.v:3131.25-3131.82" - cell $and $and$ls180.v:3131$166 + attribute \src "ls180.v:2558.33-2558.96" + cell $and $and$ls180.v:2558$249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3131$166_Y + connect \A \sdram_bankmachine0_refresh_gnt + connect \B \sdram_bankmachine1_refresh_gnt + connect \Y $and$ls180.v:2558$249_Y end - attribute \src "ls180.v:3131.24-3131.112" - cell $and $and$ls180.v:3131$167 + attribute \src "ls180.v:2558.32-2558.130" + cell $and $and$ls180.v:2558$250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3131$166_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3131$167_Y + connect \A $and$ls180.v:2558$249_Y + connect \B \sdram_bankmachine2_refresh_gnt + connect \Y $and$ls180.v:2558$250_Y end - attribute \src "ls180.v:3131.23-3131.146" - cell $and $and$ls180.v:3131$168 + attribute \src "ls180.v:2558.31-2558.164" + cell $and $and$ls180.v:2558$251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3131$167_Y - connect \B \main_interface2_ram_bus_sel [1] - connect \Y $and$ls180.v:3131$168_Y + connect \A $and$ls180.v:2558$250_Y + connect \B \sdram_bankmachine3_refresh_gnt + connect \Y $and$ls180.v:2558$251_Y end - attribute \src "ls180.v:3132.25-3132.82" - cell $and $and$ls180.v:3132$169 + attribute \src "ls180.v:2564.67-2564.133" + cell $and $and$ls180.v:2564$254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3132$169_Y + connect \A \sdram_bankmachine0_cmd_payload_is_cmd + connect \B \sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:2564$254_Y end - attribute \src "ls180.v:3132.24-3132.112" - cell $and $and$ls180.v:3132$170 + attribute \src "ls180.v:2564.142-2564.216" + cell $and $and$ls180.v:2564$256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3132$169_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3132$170_Y + connect \A \sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:2564$255_Y + connect \Y $and$ls180.v:2564$256_Y end - attribute \src "ls180.v:3132.23-3132.146" - cell $and $and$ls180.v:3132$171 + attribute \src "ls180.v:2564.141-2564.256" + cell $and $and$ls180.v:2564$258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3132$170_Y - connect \B \main_interface2_ram_bus_sel [2] - connect \Y $and$ls180.v:3132$171_Y + connect \A $and$ls180.v:2564$256_Y + connect \B $not$ls180.v:2564$257_Y + connect \Y $and$ls180.v:2564$258_Y end - attribute \src "ls180.v:3133.25-3133.82" - cell $and $and$ls180.v:3133$172 + attribute \src "ls180.v:2564.66-2564.293" + cell $and $and$ls180.v:2564$261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3133$172_Y + connect \A $and$ls180.v:2564$254_Y + connect \B $or$ls180.v:2564$260_Y + connect \Y $and$ls180.v:2564$261_Y end - attribute \src "ls180.v:3133.24-3133.112" - cell $and $and$ls180.v:3133$173 + attribute \src "ls180.v:2564.298-2564.445" + cell $and $and$ls180.v:2564$264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3133$172_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3133$173_Y + connect \A $eq$ls180.v:2564$262_Y + connect \B $eq$ls180.v:2564$263_Y + connect \Y $and$ls180.v:2564$264_Y end - attribute \src "ls180.v:3133.23-3133.146" - cell $and $and$ls180.v:3133$174 + attribute \src "ls180.v:2564.33-2564.447" + cell $and $and$ls180.v:2564$266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3133$173_Y - connect \B \main_interface2_ram_bus_sel [3] - connect \Y $and$ls180.v:3133$174_Y + connect \A \sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:2564$265_Y + connect \Y $and$ls180.v:2564$266_Y end - attribute \src "ls180.v:3134.25-3134.82" - cell $and $and$ls180.v:3134$175 + attribute \src "ls180.v:2565.67-2565.133" + cell $and $and$ls180.v:2565$267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3134$175_Y + connect \A \sdram_bankmachine1_cmd_payload_is_cmd + connect \B \sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:2565$267_Y end - attribute \src "ls180.v:3134.24-3134.112" - cell $and $and$ls180.v:3134$176 + attribute \src "ls180.v:2565.142-2565.216" + cell $and $and$ls180.v:2565$269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3134$175_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3134$176_Y + connect \A \sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:2565$268_Y + connect \Y $and$ls180.v:2565$269_Y end - attribute \src "ls180.v:3134.23-3134.146" - cell $and $and$ls180.v:3134$177 + attribute \src "ls180.v:2565.141-2565.256" + cell $and $and$ls180.v:2565$271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3134$176_Y - connect \B \main_interface2_ram_bus_sel [4] - connect \Y $and$ls180.v:3134$177_Y + connect \A $and$ls180.v:2565$269_Y + connect \B $not$ls180.v:2565$270_Y + connect \Y $and$ls180.v:2565$271_Y end - attribute \src "ls180.v:3135.25-3135.82" - cell $and $and$ls180.v:3135$178 + attribute \src "ls180.v:2565.66-2565.293" + cell $and $and$ls180.v:2565$274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3135$178_Y + connect \A $and$ls180.v:2565$267_Y + connect \B $or$ls180.v:2565$273_Y + connect \Y $and$ls180.v:2565$274_Y end - attribute \src "ls180.v:3135.24-3135.112" - cell $and $and$ls180.v:3135$179 + attribute \src "ls180.v:2565.298-2565.445" + cell $and $and$ls180.v:2565$277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3135$178_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3135$179_Y + connect \A $eq$ls180.v:2565$275_Y + connect \B $eq$ls180.v:2565$276_Y + connect \Y $and$ls180.v:2565$277_Y end - attribute \src "ls180.v:3135.23-3135.146" - cell $and $and$ls180.v:3135$180 + attribute \src "ls180.v:2565.33-2565.447" + cell $and $and$ls180.v:2565$279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3135$179_Y - connect \B \main_interface2_ram_bus_sel [5] - connect \Y $and$ls180.v:3135$180_Y + connect \A \sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:2565$278_Y + connect \Y $and$ls180.v:2565$279_Y end - attribute \src "ls180.v:3136.25-3136.82" - cell $and $and$ls180.v:3136$181 + attribute \src "ls180.v:2566.67-2566.133" + cell $and $and$ls180.v:2566$280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3136$181_Y + connect \A \sdram_bankmachine2_cmd_payload_is_cmd + connect \B \sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:2566$280_Y end - attribute \src "ls180.v:3136.24-3136.112" - cell $and $and$ls180.v:3136$182 + attribute \src "ls180.v:2566.142-2566.216" + cell $and $and$ls180.v:2566$282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3136$181_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3136$182_Y + connect \A \sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:2566$281_Y + connect \Y $and$ls180.v:2566$282_Y end - attribute \src "ls180.v:3136.23-3136.146" - cell $and $and$ls180.v:3136$183 + attribute \src "ls180.v:2566.141-2566.256" + cell $and $and$ls180.v:2566$284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3136$182_Y - connect \B \main_interface2_ram_bus_sel [6] - connect \Y $and$ls180.v:3136$183_Y + connect \A $and$ls180.v:2566$282_Y + connect \B $not$ls180.v:2566$283_Y + connect \Y $and$ls180.v:2566$284_Y end - attribute \src "ls180.v:3137.25-3137.82" - cell $and $and$ls180.v:3137$184 + attribute \src "ls180.v:2566.66-2566.293" + cell $and $and$ls180.v:2566$287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3137$184_Y + connect \A $and$ls180.v:2566$280_Y + connect \B $or$ls180.v:2566$286_Y + connect \Y $and$ls180.v:2566$287_Y end - attribute \src "ls180.v:3137.24-3137.112" - cell $and $and$ls180.v:3137$185 + attribute \src "ls180.v:2566.298-2566.445" + cell $and $and$ls180.v:2566$290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3137$184_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3137$185_Y + connect \A $eq$ls180.v:2566$288_Y + connect \B $eq$ls180.v:2566$289_Y + connect \Y $and$ls180.v:2566$290_Y end - attribute \src "ls180.v:3137.23-3137.146" - cell $and $and$ls180.v:3137$186 + attribute \src "ls180.v:2566.33-2566.447" + cell $and $and$ls180.v:2566$292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3137$185_Y - connect \B \main_interface2_ram_bus_sel [7] - connect \Y $and$ls180.v:3137$186_Y + connect \A \sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:2566$291_Y + connect \Y $and$ls180.v:2566$292_Y end - attribute \src "ls180.v:3144.25-3144.82" - cell $and $and$ls180.v:3144$188 + attribute \src "ls180.v:2567.67-2567.133" + cell $and $and$ls180.v:2567$293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3144$188_Y + connect \A \sdram_bankmachine3_cmd_payload_is_cmd + connect \B \sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:2567$293_Y end - attribute \src "ls180.v:3144.24-3144.112" - cell $and $and$ls180.v:3144$189 + attribute \src "ls180.v:2567.142-2567.216" + cell $and $and$ls180.v:2567$295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3144$188_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3144$189_Y + connect \A \sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:2567$294_Y + connect \Y $and$ls180.v:2567$295_Y end - attribute \src "ls180.v:3144.23-3144.146" - cell $and $and$ls180.v:3144$190 + attribute \src "ls180.v:2567.141-2567.256" + cell $and $and$ls180.v:2567$297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3144$189_Y - connect \B \main_interface3_ram_bus_sel [0] - connect \Y $and$ls180.v:3144$190_Y + connect \A $and$ls180.v:2567$295_Y + connect \B $not$ls180.v:2567$296_Y + connect \Y $and$ls180.v:2567$297_Y end - attribute \src "ls180.v:3145.25-3145.82" - cell $and $and$ls180.v:3145$191 + attribute \src "ls180.v:2567.66-2567.293" + cell $and $and$ls180.v:2567$300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3145$191_Y + connect \A $and$ls180.v:2567$293_Y + connect \B $or$ls180.v:2567$299_Y + connect \Y $and$ls180.v:2567$300_Y end - attribute \src "ls180.v:3145.24-3145.112" - cell $and $and$ls180.v:3145$192 + attribute \src "ls180.v:2567.298-2567.445" + cell $and $and$ls180.v:2567$303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3145$191_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3145$192_Y + connect \A $eq$ls180.v:2567$301_Y + connect \B $eq$ls180.v:2567$302_Y + connect \Y $and$ls180.v:2567$303_Y end - attribute \src "ls180.v:3145.23-3145.146" - cell $and $and$ls180.v:3145$193 + attribute \src "ls180.v:2567.33-2567.447" + cell $and $and$ls180.v:2567$305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3145$192_Y - connect \B \main_interface3_ram_bus_sel [1] - connect \Y $and$ls180.v:3145$193_Y + connect \A \sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:2567$304_Y + connect \Y $and$ls180.v:2567$305_Y end - attribute \src "ls180.v:3146.25-3146.82" - cell $and $and$ls180.v:3146$194 + attribute \src "ls180.v:2597.67-2597.133" + cell $and $and$ls180.v:2597$312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3146$194_Y + connect \A \sdram_bankmachine0_cmd_payload_is_cmd + connect \B \sdram_choose_req_want_cmds + connect \Y $and$ls180.v:2597$312_Y end - attribute \src "ls180.v:3146.24-3146.112" - cell $and $and$ls180.v:3146$195 + attribute \src "ls180.v:2597.142-2597.216" + cell $and $and$ls180.v:2597$314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3146$194_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3146$195_Y + connect \A \sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:2597$313_Y + connect \Y $and$ls180.v:2597$314_Y end - attribute \src "ls180.v:3146.23-3146.146" - cell $and $and$ls180.v:3146$196 + attribute \src "ls180.v:2597.141-2597.256" + cell $and $and$ls180.v:2597$316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3146$195_Y - connect \B \main_interface3_ram_bus_sel [2] - connect \Y $and$ls180.v:3146$196_Y + connect \A $and$ls180.v:2597$314_Y + connect \B $not$ls180.v:2597$315_Y + connect \Y $and$ls180.v:2597$316_Y end - attribute \src "ls180.v:3147.25-3147.82" - cell $and $and$ls180.v:3147$197 + attribute \src "ls180.v:2597.66-2597.293" + cell $and $and$ls180.v:2597$319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3147$197_Y + connect \A $and$ls180.v:2597$312_Y + connect \B $or$ls180.v:2597$318_Y + connect \Y $and$ls180.v:2597$319_Y end - attribute \src "ls180.v:3147.24-3147.112" - cell $and $and$ls180.v:3147$198 + attribute \src "ls180.v:2597.298-2597.445" + cell $and $and$ls180.v:2597$322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3147$197_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3147$198_Y + connect \A $eq$ls180.v:2597$320_Y + connect \B $eq$ls180.v:2597$321_Y + connect \Y $and$ls180.v:2597$322_Y end - attribute \src "ls180.v:3147.23-3147.146" - cell $and $and$ls180.v:3147$199 + attribute \src "ls180.v:2597.33-2597.447" + cell $and $and$ls180.v:2597$324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3147$198_Y - connect \B \main_interface3_ram_bus_sel [3] - connect \Y $and$ls180.v:3147$199_Y + connect \A \sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:2597$323_Y + connect \Y $and$ls180.v:2597$324_Y end - attribute \src "ls180.v:3148.25-3148.82" - cell $and $and$ls180.v:3148$200 + attribute \src "ls180.v:2598.67-2598.133" + cell $and $and$ls180.v:2598$325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3148$200_Y + connect \A \sdram_bankmachine1_cmd_payload_is_cmd + connect \B \sdram_choose_req_want_cmds + connect \Y $and$ls180.v:2598$325_Y end - attribute \src "ls180.v:3148.24-3148.112" - cell $and $and$ls180.v:3148$201 + attribute \src "ls180.v:2598.142-2598.216" + cell $and $and$ls180.v:2598$327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3148$200_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3148$201_Y + connect \A \sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:2598$326_Y + connect \Y $and$ls180.v:2598$327_Y end - attribute \src "ls180.v:3148.23-3148.146" - cell $and $and$ls180.v:3148$202 + attribute \src "ls180.v:2598.141-2598.256" + cell $and $and$ls180.v:2598$329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3148$201_Y - connect \B \main_interface3_ram_bus_sel [4] - connect \Y $and$ls180.v:3148$202_Y + connect \A $and$ls180.v:2598$327_Y + connect \B $not$ls180.v:2598$328_Y + connect \Y $and$ls180.v:2598$329_Y end - attribute \src "ls180.v:3149.25-3149.82" - cell $and $and$ls180.v:3149$203 + attribute \src "ls180.v:2598.66-2598.293" + cell $and $and$ls180.v:2598$332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3149$203_Y + connect \A $and$ls180.v:2598$325_Y + connect \B $or$ls180.v:2598$331_Y + connect \Y $and$ls180.v:2598$332_Y end - attribute \src "ls180.v:3149.24-3149.112" - cell $and $and$ls180.v:3149$204 + attribute \src "ls180.v:2598.298-2598.445" + cell $and $and$ls180.v:2598$335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3149$203_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3149$204_Y + connect \A $eq$ls180.v:2598$333_Y + connect \B $eq$ls180.v:2598$334_Y + connect \Y $and$ls180.v:2598$335_Y end - attribute \src "ls180.v:3149.23-3149.146" - cell $and $and$ls180.v:3149$205 + attribute \src "ls180.v:2598.33-2598.447" + cell $and $and$ls180.v:2598$337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3149$204_Y - connect \B \main_interface3_ram_bus_sel [5] - connect \Y $and$ls180.v:3149$205_Y + connect \A \sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:2598$336_Y + connect \Y $and$ls180.v:2598$337_Y end - attribute \src "ls180.v:3150.25-3150.82" - cell $and $and$ls180.v:3150$206 + attribute \src "ls180.v:2599.67-2599.133" + cell $and $and$ls180.v:2599$338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3150$206_Y + connect \A \sdram_bankmachine2_cmd_payload_is_cmd + connect \B \sdram_choose_req_want_cmds + connect \Y $and$ls180.v:2599$338_Y end - attribute \src "ls180.v:3150.24-3150.112" - cell $and $and$ls180.v:3150$207 + attribute \src "ls180.v:2599.142-2599.216" + cell $and $and$ls180.v:2599$340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3150$206_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3150$207_Y + connect \A \sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:2599$339_Y + connect \Y $and$ls180.v:2599$340_Y end - attribute \src "ls180.v:3150.23-3150.146" - cell $and $and$ls180.v:3150$208 + attribute \src "ls180.v:2599.141-2599.256" + cell $and $and$ls180.v:2599$342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3150$207_Y - connect \B \main_interface3_ram_bus_sel [6] - connect \Y $and$ls180.v:3150$208_Y + connect \A $and$ls180.v:2599$340_Y + connect \B $not$ls180.v:2599$341_Y + connect \Y $and$ls180.v:2599$342_Y end - attribute \src "ls180.v:3151.25-3151.82" - cell $and $and$ls180.v:3151$209 + attribute \src "ls180.v:2599.66-2599.293" + cell $and $and$ls180.v:2599$345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3151$209_Y + connect \A $and$ls180.v:2599$338_Y + connect \B $or$ls180.v:2599$344_Y + connect \Y $and$ls180.v:2599$345_Y end - attribute \src "ls180.v:3151.24-3151.112" - cell $and $and$ls180.v:3151$210 + attribute \src "ls180.v:2599.298-2599.445" + cell $and $and$ls180.v:2599$348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3151$209_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3151$210_Y + connect \A $eq$ls180.v:2599$346_Y + connect \B $eq$ls180.v:2599$347_Y + connect \Y $and$ls180.v:2599$348_Y end - attribute \src "ls180.v:3151.23-3151.146" - cell $and $and$ls180.v:3151$211 + attribute \src "ls180.v:2599.33-2599.447" + cell $and $and$ls180.v:2599$350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3151$210_Y - connect \B \main_interface3_ram_bus_sel [7] - connect \Y $and$ls180.v:3151$211_Y + connect \A \sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:2599$349_Y + connect \Y $and$ls180.v:2599$350_Y end - attribute \src "ls180.v:3268.40-3268.99" - cell $and $and$ls180.v:3268$218 + attribute \src "ls180.v:2600.67-2600.133" + cell $and $and$ls180.v:2600$351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_command_issue_re - connect \B \main_sdram_command_storage [4] - connect \Y $and$ls180.v:3268$218_Y + connect \A \sdram_bankmachine3_cmd_payload_is_cmd + connect \B \sdram_choose_req_want_cmds + connect \Y $and$ls180.v:2600$351_Y end - attribute \src "ls180.v:3269.40-3269.99" - cell $and $and$ls180.v:3269$219 + attribute \src "ls180.v:2600.142-2600.216" + cell $and $and$ls180.v:2600$353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_command_issue_re - connect \B \main_sdram_command_storage [5] - connect \Y $and$ls180.v:3269$219_Y + connect \A \sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:2600$352_Y + connect \Y $and$ls180.v:2600$353_Y end - attribute \src "ls180.v:3307.38-3307.103" - cell $and $and$ls180.v:3307$225 + attribute \src "ls180.v:2600.141-2600.256" + cell $and $and$ls180.v:2600$355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_done1 - connect \B $eq$ls180.v:3307$224_Y - connect \Y $and$ls180.v:3307$225_Y + connect \A $and$ls180.v:2600$353_Y + connect \B $not$ls180.v:2600$354_Y + connect \Y $and$ls180.v:2600$355_Y end - attribute \src "ls180.v:3361.50-3361.119" - cell $and $and$ls180.v:3361$233 + attribute \src "ls180.v:2600.66-2600.293" + cell $and $and$ls180.v:2600$358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3361$233_Y + connect \A $and$ls180.v:2600$351_Y + connect \B $or$ls180.v:2600$357_Y + connect \Y $and$ls180.v:2600$358_Y end - attribute \src "ls180.v:3361.49-3361.167" - cell $and $and$ls180.v:3361$234 + attribute \src "ls180.v:2600.298-2600.445" + cell $and $and$ls180.v:2600$361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3361$233_Y - connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3361$234_Y + connect \A $eq$ls180.v:2600$359_Y + connect \B $eq$ls180.v:2600$360_Y + connect \Y $and$ls180.v:2600$361_Y end - attribute \src "ls180.v:3362.49-3362.118" - cell $and $and$ls180.v:3362$235 + attribute \src "ls180.v:2600.33-2600.447" + cell $and $and$ls180.v:2600$363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3362$235_Y + connect \A \sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:2600$362_Y + connect \Y $and$ls180.v:2600$363_Y end - attribute \src "ls180.v:3362.48-3362.154" - cell $and $and$ls180.v:3362$236 + attribute \src "ls180.v:2629.8-2629.63" + cell $and $and$ls180.v:2629$368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3362$235_Y - connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3362$236_Y + connect \A \sdram_choose_cmd_cmd_valid + connect \B \sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:2629$368_Y end - attribute \src "ls180.v:3363.50-3363.119" - cell $and $and$ls180.v:3363$237 + attribute \src "ls180.v:2629.7-2629.99" + cell $and $and$ls180.v:2629$370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3363$237_Y + connect \A $and$ls180.v:2629$368_Y + connect \B $eq$ls180.v:2629$369_Y + connect \Y $and$ls180.v:2629$370_Y end - attribute \src "ls180.v:3363.49-3363.155" - cell $and $and$ls180.v:3363$238 + attribute \src "ls180.v:2632.8-2632.63" + cell $and $and$ls180.v:2632$371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3363$237_Y - connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3363$238_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2632$371_Y end - attribute \src "ls180.v:3366.7-3366.114" - cell $and $and$ls180.v:3366$240 + attribute \src "ls180.v:2632.7-2632.99" + cell $and $and$ls180.v:2632$373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $and$ls180.v:3366$240_Y + connect \A $and$ls180.v:2632$371_Y + connect \B $eq$ls180.v:2632$372_Y + connect \Y $and$ls180.v:2632$373_Y end - attribute \src "ls180.v:3395.66-3395.246" - cell $and $and$ls180.v:3395$246 + attribute \src "ls180.v:2638.8-2638.63" + cell $and $and$ls180.v:2638$375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B $or$ls180.v:3395$245_Y - connect \Y $and$ls180.v:3395$246_Y + connect \A \sdram_choose_cmd_cmd_valid + connect \B \sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:2638$375_Y end - attribute \src "ls180.v:3396.64-3396.187" - cell $and $and$ls180.v:3396$247 + attribute \src "ls180.v:2638.7-2638.99" + cell $and $and$ls180.v:2638$377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - connect \Y $and$ls180.v:3396$247_Y + connect \A $and$ls180.v:2638$375_Y + connect \B $eq$ls180.v:2638$376_Y + connect \Y $and$ls180.v:2638$377_Y end - attribute \src "ls180.v:3420.9-3420.86" - cell $and $and$ls180.v:3420$253 + attribute \src "ls180.v:2641.8-2641.63" + cell $and $and$ls180.v:2641$378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3420$253_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2641$378_Y end - attribute \src "ls180.v:3432.9-3432.86" - cell $and $and$ls180.v:3432$254 + attribute \src "ls180.v:2641.7-2641.99" + cell $and $and$ls180.v:2641$380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3432$254_Y + connect \A $and$ls180.v:2641$378_Y + connect \B $eq$ls180.v:2641$379_Y + connect \Y $and$ls180.v:2641$380_Y end - attribute \src "ls180.v:3482.13-3482.87" - cell $and $and$ls180.v:3482$256 + attribute \src "ls180.v:2647.8-2647.63" + cell $and $and$ls180.v:2647$382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_ready - connect \B \main_sdram_bankmachine0_auto_precharge - connect \Y $and$ls180.v:3482$256_Y + connect \A \sdram_choose_cmd_cmd_valid + connect \B \sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:2647$382_Y end - attribute \src "ls180.v:3518.50-3518.119" - cell $and $and$ls180.v:3518$263 + attribute \src "ls180.v:2647.7-2647.99" + cell $and $and$ls180.v:2647$384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3518$263_Y + connect \A $and$ls180.v:2647$382_Y + connect \B $eq$ls180.v:2647$383_Y + connect \Y $and$ls180.v:2647$384_Y end - attribute \src "ls180.v:3518.49-3518.167" - cell $and $and$ls180.v:3518$264 + attribute \src "ls180.v:2650.8-2650.63" + cell $and $and$ls180.v:2650$385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3518$263_Y - connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3518$264_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2650$385_Y end - attribute \src "ls180.v:3519.49-3519.118" - cell $and $and$ls180.v:3519$265 + attribute \src "ls180.v:2650.7-2650.99" + cell $and $and$ls180.v:2650$387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3519$265_Y + connect \A $and$ls180.v:2650$385_Y + connect \B $eq$ls180.v:2650$386_Y + connect \Y $and$ls180.v:2650$387_Y end - attribute \src "ls180.v:3519.48-3519.154" - cell $and $and$ls180.v:3519$266 + attribute \src "ls180.v:2656.8-2656.63" + cell $and $and$ls180.v:2656$389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3519$265_Y - connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3519$266_Y + connect \A \sdram_choose_cmd_cmd_valid + connect \B \sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:2656$389_Y end - attribute \src "ls180.v:3520.50-3520.119" - cell $and $and$ls180.v:3520$267 + attribute \src "ls180.v:2656.7-2656.99" + cell $and $and$ls180.v:2656$391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3520$267_Y + connect \A $and$ls180.v:2656$389_Y + connect \B $eq$ls180.v:2656$390_Y + connect \Y $and$ls180.v:2656$391_Y end - attribute \src "ls180.v:3520.49-3520.155" - cell $and $and$ls180.v:3520$268 + attribute \src "ls180.v:2659.8-2659.63" + cell $and $and$ls180.v:2659$392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3520$267_Y - connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3520$268_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2659$392_Y end - attribute \src "ls180.v:3523.7-3523.114" - cell $and $and$ls180.v:3523$270 + attribute \src "ls180.v:2659.7-2659.99" + cell $and $and$ls180.v:2659$394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $and$ls180.v:3523$270_Y + connect \A $and$ls180.v:2659$392_Y + connect \B $eq$ls180.v:2659$393_Y + connect \Y $and$ls180.v:2659$394_Y end - attribute \src "ls180.v:3552.66-3552.246" - cell $and $and$ls180.v:3552$276 + attribute \src "ls180.v:2684.61-2684.131" + cell $and $and$ls180.v:2684$399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B $or$ls180.v:3552$275_Y - connect \Y $and$ls180.v:3552$276_Y + connect \A \sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:2684$398_Y + connect \Y $and$ls180.v:2684$399_Y end - attribute \src "ls180.v:3553.64-3553.187" - cell $and $and$ls180.v:3553$277 + attribute \src "ls180.v:2684.60-2684.169" + cell $and $and$ls180.v:2684$401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - connect \Y $and$ls180.v:3553$277_Y + connect \A $and$ls180.v:2684$399_Y + connect \B $not$ls180.v:2684$400_Y + connect \Y $and$ls180.v:2684$401_Y end - attribute \src "ls180.v:3577.9-3577.86" - cell $and $and$ls180.v:3577$283 + attribute \src "ls180.v:2684.36-2684.192" + cell $and $and$ls180.v:2684$404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3577$283_Y + connect \A \sdram_cas_allowed + connect \B $or$ls180.v:2684$403_Y + connect \Y $and$ls180.v:2684$404_Y end - attribute \src "ls180.v:3589.9-3589.86" - cell $and $and$ls180.v:3589$284 + attribute \src "ls180.v:2722.61-2722.131" + cell $and $and$ls180.v:2722$408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3589$284_Y + connect \A \sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:2722$407_Y + connect \Y $and$ls180.v:2722$408_Y end - attribute \src "ls180.v:3639.13-3639.87" - cell $and $and$ls180.v:3639$286 + attribute \src "ls180.v:2722.60-2722.169" + cell $and $and$ls180.v:2722$410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_ready - connect \B \main_sdram_bankmachine1_auto_precharge - connect \Y $and$ls180.v:3639$286_Y + connect \A $and$ls180.v:2722$408_Y + connect \B $not$ls180.v:2722$409_Y + connect \Y $and$ls180.v:2722$410_Y end - attribute \src "ls180.v:3675.50-3675.119" - cell $and $and$ls180.v:3675$293 + attribute \src "ls180.v:2722.36-2722.192" + cell $and $and$ls180.v:2722$413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3675$293_Y + connect \A \sdram_cas_allowed + connect \B $or$ls180.v:2722$412_Y + connect \Y $and$ls180.v:2722$413_Y end - attribute \src "ls180.v:3675.49-3675.167" - cell $and $and$ls180.v:3675$294 + attribute \src "ls180.v:2740.115-2740.184" + cell $and $and$ls180.v:2740$418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3675$293_Y - connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3675$294_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:2740$417_Y + connect \Y $and$ls180.v:2740$418_Y end - attribute \src "ls180.v:3676.49-3676.118" - cell $and $and$ls180.v:3676$295 + attribute \src "ls180.v:2740.190-2740.259" + cell $and $and$ls180.v:2740$421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3676$295_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:2740$420_Y + connect \Y $and$ls180.v:2740$421_Y end - attribute \src "ls180.v:3676.48-3676.154" - cell $and $and$ls180.v:3676$296 + attribute \src "ls180.v:2740.265-2740.334" + cell $and $and$ls180.v:2740$424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3676$295_Y - connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3676$296_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:2740$423_Y + connect \Y $and$ls180.v:2740$424_Y end - attribute \src "ls180.v:3677.50-3677.119" - cell $and $and$ls180.v:3677$297 + attribute \src "ls180.v:2740.46-2740.337" + cell $and $and$ls180.v:2740$427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3677$297_Y + connect \A $eq$ls180.v:2740$416_Y + connect \B $not$ls180.v:2740$426_Y + connect \Y $and$ls180.v:2740$427_Y end - attribute \src "ls180.v:3677.49-3677.155" - cell $and $and$ls180.v:3677$298 + attribute \src "ls180.v:2740.45-2740.355" + cell $and $and$ls180.v:2740$428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3677$297_Y - connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3677$298_Y + connect \A $and$ls180.v:2740$427_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:2740$428_Y end - attribute \src "ls180.v:3680.7-3680.114" - cell $and $and$ls180.v:3680$300 + attribute \src "ls180.v:2741.39-2741.101" + cell $and $and$ls180.v:2741$431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $and$ls180.v:3680$300_Y + connect \A $not$ls180.v:2741$429_Y + connect \B $not$ls180.v:2741$430_Y + connect \Y $and$ls180.v:2741$431_Y end - attribute \src "ls180.v:3709.66-3709.246" - cell $and $and$ls180.v:3709$306 + attribute \src "ls180.v:2745.115-2745.184" + cell $and $and$ls180.v:2745$434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B $or$ls180.v:3709$305_Y - connect \Y $and$ls180.v:3709$306_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:2745$433_Y + connect \Y $and$ls180.v:2745$434_Y end - attribute \src "ls180.v:3710.64-3710.187" - cell $and $and$ls180.v:3710$307 + attribute \src "ls180.v:2745.190-2745.259" + cell $and $and$ls180.v:2745$437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - connect \Y $and$ls180.v:3710$307_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:2745$436_Y + connect \Y $and$ls180.v:2745$437_Y end - attribute \src "ls180.v:3734.9-3734.86" - cell $and $and$ls180.v:3734$313 + attribute \src "ls180.v:2745.265-2745.334" + cell $and $and$ls180.v:2745$440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3734$313_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:2745$439_Y + connect \Y $and$ls180.v:2745$440_Y end - attribute \src "ls180.v:3746.9-3746.86" - cell $and $and$ls180.v:3746$314 + attribute \src "ls180.v:2745.46-2745.337" + cell $and $and$ls180.v:2745$443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3746$314_Y + connect \A $eq$ls180.v:2745$432_Y + connect \B $not$ls180.v:2745$442_Y + connect \Y $and$ls180.v:2745$443_Y end - attribute \src "ls180.v:3796.13-3796.87" - cell $and $and$ls180.v:3796$316 + attribute \src "ls180.v:2745.45-2745.355" + cell $and $and$ls180.v:2745$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_ready - connect \B \main_sdram_bankmachine2_auto_precharge - connect \Y $and$ls180.v:3796$316_Y + connect \A $and$ls180.v:2745$443_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:2745$444_Y end - attribute \src "ls180.v:3832.50-3832.119" - cell $and $and$ls180.v:3832$323 + attribute \src "ls180.v:2746.39-2746.101" + cell $and $and$ls180.v:2746$447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3832$323_Y + connect \A $not$ls180.v:2746$445_Y + connect \B $not$ls180.v:2746$446_Y + connect \Y $and$ls180.v:2746$447_Y end - attribute \src "ls180.v:3832.49-3832.167" - cell $and $and$ls180.v:3832$324 + attribute \src "ls180.v:2750.115-2750.184" + cell $and $and$ls180.v:2750$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3832$323_Y - connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3832$324_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:2750$449_Y + connect \Y $and$ls180.v:2750$450_Y end - attribute \src "ls180.v:3833.49-3833.118" - cell $and $and$ls180.v:3833$325 + attribute \src "ls180.v:2750.190-2750.259" + cell $and $and$ls180.v:2750$453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3833$325_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:2750$452_Y + connect \Y $and$ls180.v:2750$453_Y end - attribute \src "ls180.v:3833.48-3833.154" - cell $and $and$ls180.v:3833$326 + attribute \src "ls180.v:2750.265-2750.334" + cell $and $and$ls180.v:2750$456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3833$325_Y - connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3833$326_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:2750$455_Y + connect \Y $and$ls180.v:2750$456_Y end - attribute \src "ls180.v:3834.50-3834.119" - cell $and $and$ls180.v:3834$327 + attribute \src "ls180.v:2750.46-2750.337" + cell $and $and$ls180.v:2750$459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3834$327_Y + connect \A $eq$ls180.v:2750$448_Y + connect \B $not$ls180.v:2750$458_Y + connect \Y $and$ls180.v:2750$459_Y end - attribute \src "ls180.v:3834.49-3834.155" - cell $and $and$ls180.v:3834$328 + attribute \src "ls180.v:2750.45-2750.355" + cell $and $and$ls180.v:2750$460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3834$327_Y - connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3834$328_Y + connect \A $and$ls180.v:2750$459_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:2750$460_Y end - attribute \src "ls180.v:3837.7-3837.114" - cell $and $and$ls180.v:3837$330 + attribute \src "ls180.v:2751.39-2751.101" + cell $and $and$ls180.v:2751$463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $and$ls180.v:3837$330_Y + connect \A $not$ls180.v:2751$461_Y + connect \B $not$ls180.v:2751$462_Y + connect \Y $and$ls180.v:2751$463_Y end - attribute \src "ls180.v:3866.66-3866.246" - cell $and $and$ls180.v:3866$336 + attribute \src "ls180.v:2755.115-2755.184" + cell $and $and$ls180.v:2755$466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B $or$ls180.v:3866$335_Y - connect \Y $and$ls180.v:3866$336_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:2755$465_Y + connect \Y $and$ls180.v:2755$466_Y end - attribute \src "ls180.v:3867.64-3867.187" - cell $and $and$ls180.v:3867$337 + attribute \src "ls180.v:2755.190-2755.259" + cell $and $and$ls180.v:2755$469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - connect \Y $and$ls180.v:3867$337_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:2755$468_Y + connect \Y $and$ls180.v:2755$469_Y end - attribute \src "ls180.v:3891.9-3891.86" - cell $and $and$ls180.v:3891$343 + attribute \src "ls180.v:2755.265-2755.334" + cell $and $and$ls180.v:2755$472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3891$343_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:2755$471_Y + connect \Y $and$ls180.v:2755$472_Y end - attribute \src "ls180.v:3903.9-3903.86" - cell $and $and$ls180.v:3903$344 + attribute \src "ls180.v:2755.46-2755.337" + cell $and $and$ls180.v:2755$475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3903$344_Y + connect \A $eq$ls180.v:2755$464_Y + connect \B $not$ls180.v:2755$474_Y + connect \Y $and$ls180.v:2755$475_Y end - attribute \src "ls180.v:3953.13-3953.87" - cell $and $and$ls180.v:3953$346 + attribute \src "ls180.v:2755.45-2755.355" + cell $and $and$ls180.v:2755$476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_ready - connect \B \main_sdram_bankmachine3_auto_precharge - connect \Y $and$ls180.v:3953$346_Y + connect \A $and$ls180.v:2755$475_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:2755$476_Y end - attribute \src "ls180.v:3968.37-3968.102" - cell $and $and$ls180.v:3968$347 + attribute \src "ls180.v:2756.39-2756.101" + cell $and $and$ls180.v:2756$479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3968$347_Y + connect \A $not$ls180.v:2756$477_Y + connect \B $not$ls180.v:2756$478_Y + connect \Y $and$ls180.v:2756$479_Y end - attribute \src "ls180.v:3968.108-3968.188" - cell $and $and$ls180.v:3968$349 + attribute \src "ls180.v:2760.151-2760.220" + cell $and $and$ls180.v:2760$483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3968$348_Y - connect \Y $and$ls180.v:3968$349_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:2760$482_Y + connect \Y $and$ls180.v:2760$483_Y end - attribute \src "ls180.v:3968.107-3968.231" - cell $and $and$ls180.v:3968$351 + attribute \src "ls180.v:2760.226-2760.295" + cell $and $and$ls180.v:2760$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3968$349_Y - connect \B $not$ls180.v:3968$350_Y - connect \Y $and$ls180.v:3968$351_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:2760$485_Y + connect \Y $and$ls180.v:2760$486_Y end - attribute \src "ls180.v:3968.36-3968.232" - cell $and $and$ls180.v:3968$352 + attribute \src "ls180.v:2760.301-2760.370" + cell $and $and$ls180.v:2760$489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3968$347_Y - connect \B $and$ls180.v:3968$351_Y - connect \Y $and$ls180.v:3968$352_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:2760$488_Y + connect \Y $and$ls180.v:2760$489_Y end - attribute \src "ls180.v:3969.37-3969.102" - cell $and $and$ls180.v:3969$353 + attribute \src "ls180.v:2760.82-2760.373" + cell $and $and$ls180.v:2760$492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3969$353_Y + connect \A $eq$ls180.v:2760$481_Y + connect \B $not$ls180.v:2760$491_Y + connect \Y $and$ls180.v:2760$492_Y end - attribute \src "ls180.v:3969.108-3969.188" - cell $and $and$ls180.v:3969$355 + attribute \src "ls180.v:2760.38-2760.374" + cell $and $and$ls180.v:2760$493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3969$354_Y - connect \Y $and$ls180.v:3969$355_Y + connect \A $eq$ls180.v:2760$480_Y + connect \B $and$ls180.v:2760$492_Y + connect \Y $and$ls180.v:2760$493_Y end - attribute \src "ls180.v:3969.107-3969.231" - cell $and $and$ls180.v:3969$357 + attribute \src "ls180.v:2760.37-2760.405" + cell $and $and$ls180.v:2760$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3969$355_Y - connect \B $not$ls180.v:3969$356_Y - connect \Y $and$ls180.v:3969$357_Y + connect \A $and$ls180.v:2760$493_Y + connect \B \sdram_interface_bank0_ready + connect \Y $and$ls180.v:2760$494_Y end - attribute \src "ls180.v:3969.36-3969.232" - cell $and $and$ls180.v:3969$358 + attribute \src "ls180.v:2760.525-2760.594" + cell $and $and$ls180.v:2760$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3969$353_Y - connect \B $and$ls180.v:3969$357_Y - connect \Y $and$ls180.v:3969$358_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:2760$498_Y + connect \Y $and$ls180.v:2760$499_Y end - attribute \src "ls180.v:3970.34-3970.85" - cell $and $and$ls180.v:3970$359 + attribute \src "ls180.v:2760.600-2760.669" + cell $and $and$ls180.v:2760$502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_trrdcon_ready - connect \B \main_sdram_tfawcon_ready - connect \Y $and$ls180.v:3970$359_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:2760$501_Y + connect \Y $and$ls180.v:2760$502_Y end - attribute \src "ls180.v:3971.37-3971.102" - cell $and $and$ls180.v:3971$360 + attribute \src "ls180.v:2760.675-2760.744" + cell $and $and$ls180.v:2760$505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3971$360_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:2760$504_Y + connect \Y $and$ls180.v:2760$505_Y end - attribute \src "ls180.v:3971.36-3971.194" - cell $and $and$ls180.v:3971$362 + attribute \src "ls180.v:2760.456-2760.747" + cell $and $and$ls180.v:2760$508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3971$360_Y - connect \B $or$ls180.v:3971$361_Y - connect \Y $and$ls180.v:3971$362_Y + connect \A $eq$ls180.v:2760$497_Y + connect \B $not$ls180.v:2760$507_Y + connect \Y $and$ls180.v:2760$508_Y end - attribute \src "ls180.v:3973.37-3973.102" - cell $and $and$ls180.v:3973$363 + attribute \src "ls180.v:2760.412-2760.748" + cell $and $and$ls180.v:2760$509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3973$363_Y + connect \A $eq$ls180.v:2760$496_Y + connect \B $and$ls180.v:2760$508_Y + connect \Y $and$ls180.v:2760$509_Y end - attribute \src "ls180.v:3973.36-3973.148" - cell $and $and$ls180.v:3973$364 + attribute \src "ls180.v:2760.411-2760.779" + cell $and $and$ls180.v:2760$510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3973$363_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:3973$364_Y + connect \A $and$ls180.v:2760$509_Y + connect \B \sdram_interface_bank1_ready + connect \Y $and$ls180.v:2760$510_Y end - attribute \src "ls180.v:3974.40-3974.119" - cell $and $and$ls180.v:3974$365 + attribute \src "ls180.v:2760.899-2760.968" + cell $and $and$ls180.v:2760$515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_payload_is_read - connect \Y $and$ls180.v:3974$365_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:2760$514_Y + connect \Y $and$ls180.v:2760$515_Y end - attribute \src "ls180.v:3974.124-3974.203" - cell $and $and$ls180.v:3974$366 + attribute \src "ls180.v:2760.974-2760.1043" + cell $and $and$ls180.v:2760$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_payload_is_read - connect \Y $and$ls180.v:3974$366_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:2760$517_Y + connect \Y $and$ls180.v:2760$518_Y end - attribute \src "ls180.v:3974.209-3974.288" - cell $and $and$ls180.v:3974$368 + attribute \src "ls180.v:2760.1049-2760.1118" + cell $and $and$ls180.v:2760$521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_payload_is_read - connect \Y $and$ls180.v:3974$368_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:2760$520_Y + connect \Y $and$ls180.v:2760$521_Y end - attribute \src "ls180.v:3974.294-3974.373" - cell $and $and$ls180.v:3974$370 + attribute \src "ls180.v:2760.830-2760.1121" + cell $and $and$ls180.v:2760$524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_payload_is_read - connect \Y $and$ls180.v:3974$370_Y + connect \A $eq$ls180.v:2760$513_Y + connect \B $not$ls180.v:2760$523_Y + connect \Y $and$ls180.v:2760$524_Y end - attribute \src "ls180.v:3975.41-3975.121" - cell $and $and$ls180.v:3975$372 + attribute \src "ls180.v:2760.786-2760.1122" + cell $and $and$ls180.v:2760$525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3975$372_Y + connect \A $eq$ls180.v:2760$512_Y + connect \B $and$ls180.v:2760$524_Y + connect \Y $and$ls180.v:2760$525_Y end - attribute \src "ls180.v:3975.126-3975.206" - cell $and $and$ls180.v:3975$373 + attribute \src "ls180.v:2760.785-2760.1153" + cell $and $and$ls180.v:2760$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3975$373_Y + connect \A $and$ls180.v:2760$525_Y + connect \B \sdram_interface_bank2_ready + connect \Y $and$ls180.v:2760$526_Y end - attribute \src "ls180.v:3975.212-3975.292" - cell $and $and$ls180.v:3975$375 + attribute \src "ls180.v:2760.1273-2760.1342" + cell $and $and$ls180.v:2760$531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3975$375_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:2760$530_Y + connect \Y $and$ls180.v:2760$531_Y end - attribute \src "ls180.v:3975.298-3975.378" - cell $and $and$ls180.v:3975$377 + attribute \src "ls180.v:2760.1348-2760.1417" + cell $and $and$ls180.v:2760$534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3975$377_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:2760$533_Y + connect \Y $and$ls180.v:2760$534_Y end - attribute \src "ls180.v:3982.38-3982.111" - cell $and $and$ls180.v:3982$381 + attribute \src "ls180.v:2760.1423-2760.1492" + cell $and $and$ls180.v:2760$537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_refresh_gnt - connect \B \main_sdram_bankmachine1_refresh_gnt - connect \Y $and$ls180.v:3982$381_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:2760$536_Y + connect \Y $and$ls180.v:2760$537_Y end - attribute \src "ls180.v:3982.37-3982.150" - cell $and $and$ls180.v:3982$382 + attribute \src "ls180.v:2760.1204-2760.1495" + cell $and $and$ls180.v:2760$540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3982$381_Y - connect \B \main_sdram_bankmachine2_refresh_gnt - connect \Y $and$ls180.v:3982$382_Y + connect \A $eq$ls180.v:2760$529_Y + connect \B $not$ls180.v:2760$539_Y + connect \Y $and$ls180.v:2760$540_Y end - attribute \src "ls180.v:3982.36-3982.189" - cell $and $and$ls180.v:3982$383 + attribute \src "ls180.v:2760.1160-2760.1496" + cell $and $and$ls180.v:2760$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3982$382_Y - connect \B \main_sdram_bankmachine3_refresh_gnt - connect \Y $and$ls180.v:3982$383_Y + connect \A $eq$ls180.v:2760$528_Y + connect \B $and$ls180.v:2760$540_Y + connect \Y $and$ls180.v:2760$541_Y end - attribute \src "ls180.v:3988.77-3988.153" - cell $and $and$ls180.v:3988$386 + attribute \src "ls180.v:2760.1159-2760.1527" + cell $and $and$ls180.v:2760$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3988$386_Y + connect \A $and$ls180.v:2760$541_Y + connect \B \sdram_interface_bank3_ready + connect \Y $and$ls180.v:2760$542_Y end - attribute \src "ls180.v:3988.162-3988.246" - cell $and $and$ls180.v:3988$388 + attribute \src "ls180.v:2818.9-2818.36" + cell $and $and$ls180.v:2818$548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3988$387_Y - connect \Y $and$ls180.v:3988$388_Y + connect \A \wb_sdram_stb + connect \B \wb_sdram_cyc + connect \Y $and$ls180.v:2818$548_Y end - attribute \src "ls180.v:3988.161-3988.291" - cell $and $and$ls180.v:3988$390 + attribute \src "ls180.v:2836.9-2836.36" + cell $and $and$ls180.v:2836$555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$388_Y - connect \B $not$ls180.v:3988$389_Y - connect \Y $and$ls180.v:3988$390_Y + connect \A \wb_sdram_stb + connect \B \wb_sdram_cyc + connect \Y $and$ls180.v:2836$555_Y end - attribute \src "ls180.v:3988.76-3988.333" - cell $and $and$ls180.v:3988$393 + attribute \src "ls180.v:2849.27-2849.60" + cell $and $and$ls180.v:2849$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$386_Y - connect \B $or$ls180.v:3988$392_Y - connect \Y $and$ls180.v:3988$393_Y + connect \A \litedram_wb_cyc + connect \B \litedram_wb_stb + connect \Y $and$ls180.v:2849$559_Y end - attribute \src "ls180.v:3988.338-3988.505" - cell $and $and$ls180.v:3988$396 + attribute \src "ls180.v:2849.26-2849.79" + cell $and $and$ls180.v:2849$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3988$394_Y - connect \B $eq$ls180.v:3988$395_Y - connect \Y $and$ls180.v:3988$396_Y + connect \A $and$ls180.v:2849$559_Y + connect \B $not$ls180.v:2849$560_Y + connect \Y $and$ls180.v:2849$561_Y end - attribute \src "ls180.v:3988.38-3988.507" - cell $and $and$ls180.v:3988$398 + attribute \src "ls180.v:2850.29-2850.82" + cell $and $and$ls180.v:2850$563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3988$397_Y - connect \Y $and$ls180.v:3988$398_Y + connect \A $or$ls180.v:2850$562_Y + connect \B \port_cmd_payload_we + connect \Y $and$ls180.v:2850$563_Y end - attribute \src "ls180.v:3989.77-3989.153" - cell $and $and$ls180.v:3989$399 + attribute \src "ls180.v:2850.28-2850.103" + cell $and $and$ls180.v:2850$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3989$399_Y + connect \A $and$ls180.v:2850$563_Y + connect \B $not$ls180.v:2850$564_Y + connect \Y $and$ls180.v:2850$565_Y end - attribute \src "ls180.v:3989.162-3989.246" - cell $and $and$ls180.v:3989$401 + attribute \src "ls180.v:2851.28-2851.84" + cell $and $and$ls180.v:2851$568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3989$400_Y - connect \Y $and$ls180.v:3989$401_Y + connect \A $or$ls180.v:2851$566_Y + connect \B $not$ls180.v:2851$567_Y + connect \Y $and$ls180.v:2851$568_Y end - attribute \src "ls180.v:3989.161-3989.291" - cell $and $and$ls180.v:3989$403 + attribute \src "ls180.v:2852.39-2852.65" + cell $and $and$ls180.v:2852$569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3989$401_Y - connect \B $not$ls180.v:3989$402_Y - connect \Y $and$ls180.v:3989$403_Y + connect \A \litedram_wb_we + connect \B \ack_wdata + connect \Y $and$ls180.v:2852$569_Y end - attribute \src "ls180.v:3989.76-3989.333" - cell $and $and$ls180.v:3989$406 + attribute \src "ls180.v:2852.70-2852.99" + cell $and $and$ls180.v:2852$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3989$399_Y - connect \B $or$ls180.v:3989$405_Y - connect \Y $and$ls180.v:3989$406_Y + connect \A $not$ls180.v:2852$570_Y + connect \B \ack_rdata + connect \Y $and$ls180.v:2852$571_Y end - attribute \src "ls180.v:3989.338-3989.505" - cell $and $and$ls180.v:3989$409 + attribute \src "ls180.v:2852.27-2852.101" + cell $and $and$ls180.v:2852$573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3989$407_Y - connect \B $eq$ls180.v:3989$408_Y - connect \Y $and$ls180.v:3989$409_Y + connect \A \ack_cmd + connect \B $or$ls180.v:2852$572_Y + connect \Y $and$ls180.v:2852$573_Y end - attribute \src "ls180.v:3989.38-3989.507" - cell $and $and$ls180.v:3989$411 + attribute \src "ls180.v:2853.20-2853.51" + cell $and $and$ls180.v:2853$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3989$410_Y - connect \Y $and$ls180.v:3989$411_Y + connect \A \port_cmd_valid + connect \B \port_cmd_ready + connect \Y $and$ls180.v:2853$574_Y end - attribute \src "ls180.v:3990.77-3990.153" - cell $and $and$ls180.v:3990$412 + attribute \src "ls180.v:2854.22-2854.57" + cell $and $and$ls180.v:2854$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3990$412_Y + connect \A \port_wdata_valid + connect \B \port_wdata_ready + connect \Y $and$ls180.v:2854$576_Y end - attribute \src "ls180.v:3990.162-3990.246" - cell $and $and$ls180.v:3990$414 + attribute \src "ls180.v:2855.21-2855.56" + cell $and $and$ls180.v:2855$578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3990$413_Y - connect \Y $and$ls180.v:3990$414_Y + connect \A \port_rdata_valid + connect \B \port_rdata_ready + connect \Y $and$ls180.v:2855$578_Y end - attribute \src "ls180.v:3990.161-3990.291" - cell $and $and$ls180.v:3990$416 + attribute \src "ls180.v:2884.44-2884.58" + cell $and $and$ls180.v:2884$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3990$414_Y - connect \B $not$ls180.v:3990$415_Y - connect \Y $and$ls180.v:3990$416_Y + connect \A 1'0 + connect \B \rxtx_we + connect \Y $and$ls180.v:2884$584_Y end - attribute \src "ls180.v:3990.76-3990.333" - cell $and $and$ls180.v:3990$419 + attribute \src "ls180.v:2888.7-2888.58" + cell $and $and$ls180.v:2888$588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3990$412_Y - connect \B $or$ls180.v:3990$418_Y - connect \Y $and$ls180.v:3990$419_Y + connect \A \eventmanager_pending_re + connect \B \eventmanager_pending_r [0] + connect \Y $and$ls180.v:2888$588_Y end - attribute \src "ls180.v:3990.338-3990.505" - cell $and $and$ls180.v:3990$422 + attribute \src "ls180.v:2899.7-2899.58" + cell $and $and$ls180.v:2899$591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3990$420_Y - connect \B $eq$ls180.v:3990$421_Y - connect \Y $and$ls180.v:3990$422_Y + connect \A \eventmanager_pending_re + connect \B \eventmanager_pending_r [1] + connect \Y $and$ls180.v:2899$591_Y end - attribute \src "ls180.v:3990.38-3990.507" - cell $and $and$ls180.v:3990$424 + attribute \src "ls180.v:2908.16-2908.67" + cell $and $and$ls180.v:2908$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3990$423_Y - connect \Y $and$ls180.v:3990$424_Y + connect \A \eventmanager_pending_w [0] + connect \B \eventmanager_storage [0] + connect \Y $and$ls180.v:2908$593_Y end - attribute \src "ls180.v:3991.77-3991.153" - cell $and $and$ls180.v:3991$425 + attribute \src "ls180.v:2908.72-2908.123" + cell $and $and$ls180.v:2908$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3991$425_Y + connect \A \eventmanager_pending_w [1] + connect \B \eventmanager_storage [1] + connect \Y $and$ls180.v:2908$594_Y end - attribute \src "ls180.v:3991.162-3991.246" - cell $and $and$ls180.v:3991$427 + attribute \src "ls180.v:2923.31-2923.93" + cell $and $and$ls180.v:2923$598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3991$426_Y - connect \Y $and$ls180.v:3991$427_Y + connect \A \tx_fifo_syncfifo_readable + connect \B $or$ls180.v:2923$597_Y + connect \Y $and$ls180.v:2923$598_Y end - attribute \src "ls180.v:3991.161-3991.291" - cell $and $and$ls180.v:3991$429 + attribute \src "ls180.v:2934.29-2934.96" + cell $and $and$ls180.v:2934$603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3991$427_Y - connect \B $not$ls180.v:3991$428_Y - connect \Y $and$ls180.v:3991$429_Y + connect \A \tx_fifo_syncfifo_we + connect \B $or$ls180.v:2934$602_Y + connect \Y $and$ls180.v:2934$603_Y end - attribute \src "ls180.v:3991.76-3991.333" - cell $and $and$ls180.v:3991$432 + attribute \src "ls180.v:2935.27-2935.74" + cell $and $and$ls180.v:2935$604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3991$425_Y - connect \B $or$ls180.v:3991$431_Y - connect \Y $and$ls180.v:3991$432_Y + connect \A \tx_fifo_syncfifo_readable + connect \B \tx_fifo_syncfifo_re + connect \Y $and$ls180.v:2935$604_Y end - attribute \src "ls180.v:3991.338-3991.505" - cell $and $and$ls180.v:3991$435 + attribute \src "ls180.v:2953.31-2953.93" + cell $and $and$ls180.v:2953$609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3991$433_Y - connect \B $eq$ls180.v:3991$434_Y - connect \Y $and$ls180.v:3991$435_Y + connect \A \rx_fifo_syncfifo_readable + connect \B $or$ls180.v:2953$608_Y + connect \Y $and$ls180.v:2953$609_Y end - attribute \src "ls180.v:3991.38-3991.507" - cell $and $and$ls180.v:3991$437 + attribute \src "ls180.v:2964.29-2964.96" + cell $and $and$ls180.v:2964$614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3991$436_Y - connect \Y $and$ls180.v:3991$437_Y + connect \A \rx_fifo_syncfifo_we + connect \B $or$ls180.v:2964$613_Y + connect \Y $and$ls180.v:2964$614_Y end - attribute \src "ls180.v:4021.77-4021.153" - cell $and $and$ls180.v:4021$444 + attribute \src "ls180.v:2965.27-2965.74" + cell $and $and$ls180.v:2965$615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4021$444_Y + connect \A \rx_fifo_syncfifo_readable + connect \B \rx_fifo_syncfifo_re + connect \Y $and$ls180.v:2965$615_Y end - attribute \src "ls180.v:4021.162-4021.246" - cell $and $and$ls180.v:4021$446 + attribute \src "ls180.v:3062.9-3062.84" + cell $and $and$ls180.v:3062$623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:4021$445_Y - connect \Y $and$ls180.v:4021$446_Y + connect \A \libresocsim_libresocsim_wishbone_cyc + connect \B \libresocsim_libresocsim_wishbone_stb + connect \Y $and$ls180.v:3062$623_Y end - attribute \src "ls180.v:4021.161-4021.291" - cell $and $and$ls180.v:4021$448 + attribute \src "ls180.v:3065.60-3065.144" + cell $and $and$ls180.v:3065$625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$446_Y - connect \B $not$ls180.v:4021$447_Y - connect \Y $and$ls180.v:4021$448_Y + connect \A \libresocsim_libresocsim_wishbone_we + connect \B $ne$ls180.v:3065$624_Y + connect \Y $and$ls180.v:3065$625_Y end - attribute \src "ls180.v:4021.76-4021.333" - cell $and $and$ls180.v:4021$451 + attribute \src "ls180.v:3083.58-3083.110" + cell $and $and$ls180.v:3083$627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$444_Y - connect \B $or$ls180.v:4021$450_Y - connect \Y $and$ls180.v:4021$451_Y + connect \A \libresocsim_shared_ack + connect \B $eq$ls180.v:3083$626_Y + connect \Y $and$ls180.v:3083$627_Y end - attribute \src "ls180.v:4021.338-4021.505" - cell $and $and$ls180.v:4021$454 + attribute \src "ls180.v:3084.58-3084.110" + cell $and $and$ls180.v:3084$629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4021$452_Y - connect \B $eq$ls180.v:4021$453_Y - connect \Y $and$ls180.v:4021$454_Y + connect \A \libresocsim_shared_ack + connect \B $eq$ls180.v:3084$628_Y + connect \Y $and$ls180.v:3084$629_Y end - attribute \src "ls180.v:4021.38-4021.507" - cell $and $and$ls180.v:4021$456 + attribute \src "ls180.v:3085.58-3085.110" + cell $and $and$ls180.v:3085$631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:4021$455_Y - connect \Y $and$ls180.v:4021$456_Y + connect \A \libresocsim_shared_ack + connect \B $eq$ls180.v:3085$630_Y + connect \Y $and$ls180.v:3085$631_Y end - attribute \src "ls180.v:4022.77-4022.153" - cell $and $and$ls180.v:4022$457 + attribute \src "ls180.v:3086.58-3086.110" + cell $and $and$ls180.v:3086$633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4022$457_Y + connect \A \libresocsim_shared_err + connect \B $eq$ls180.v:3086$632_Y + connect \Y $and$ls180.v:3086$633_Y end - attribute \src "ls180.v:4022.162-4022.246" - cell $and $and$ls180.v:4022$459 + attribute \src "ls180.v:3087.58-3087.110" + cell $and $and$ls180.v:3087$635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:4022$458_Y - connect \Y $and$ls180.v:4022$459_Y + connect \A \libresocsim_shared_err + connect \B $eq$ls180.v:3087$634_Y + connect \Y $and$ls180.v:3087$635_Y end - attribute \src "ls180.v:4022.161-4022.291" - cell $and $and$ls180.v:4022$461 + attribute \src "ls180.v:3088.58-3088.110" + cell $and $and$ls180.v:3088$637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4022$459_Y - connect \B $not$ls180.v:4022$460_Y - connect \Y $and$ls180.v:4022$461_Y + connect \A \libresocsim_shared_err + connect \B $eq$ls180.v:3088$636_Y + connect \Y $and$ls180.v:3088$637_Y end - attribute \src "ls180.v:4022.76-4022.333" - cell $and $and$ls180.v:4022$464 + attribute \src "ls180.v:3141.35-3141.84" + cell $and $and$ls180.v:3141$645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4022$457_Y - connect \B $or$ls180.v:4022$463_Y - connect \Y $and$ls180.v:4022$464_Y + connect \A \libresocsim_shared_cyc + connect \B \libresocsim_slave_sel [0] + connect \Y $and$ls180.v:3141$645_Y end - attribute \src "ls180.v:4022.338-4022.505" - cell $and $and$ls180.v:4022$467 + attribute \src "ls180.v:3142.31-3142.80" + cell $and $and$ls180.v:3142$646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4022$465_Y - connect \B $eq$ls180.v:4022$466_Y - connect \Y $and$ls180.v:4022$467_Y + connect \A \libresocsim_shared_cyc + connect \B \libresocsim_slave_sel [1] + connect \Y $and$ls180.v:3142$646_Y end - attribute \src "ls180.v:4022.38-4022.507" - cell $and $and$ls180.v:4022$469 + attribute \src "ls180.v:3143.45-3143.94" + cell $and $and$ls180.v:3143$647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:4022$468_Y - connect \Y $and$ls180.v:4022$469_Y + connect \A \libresocsim_shared_cyc + connect \B \libresocsim_slave_sel [2] + connect \Y $and$ls180.v:3143$647_Y end - attribute \src "ls180.v:4023.77-4023.153" - cell $and $and$ls180.v:4023$470 + attribute \src "ls180.v:3144.45-3144.94" + cell $and $and$ls180.v:3144$648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4023$470_Y + connect \A \libresocsim_shared_cyc + connect \B \libresocsim_slave_sel [3] + connect \Y $and$ls180.v:3144$648_Y end - attribute \src "ls180.v:4023.162-4023.246" - cell $and $and$ls180.v:4023$472 + attribute \src "ls180.v:3145.24-3145.73" + cell $and $and$ls180.v:3145$649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:4023$471_Y - connect \Y $and$ls180.v:4023$472_Y + connect \A \libresocsim_shared_cyc + connect \B \libresocsim_slave_sel [4] + connect \Y $and$ls180.v:3145$649_Y end - attribute \src "ls180.v:4023.161-4023.291" - cell $and $and$ls180.v:4023$474 + attribute \src "ls180.v:3146.48-3146.97" + cell $and $and$ls180.v:3146$650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4023$472_Y - connect \B $not$ls180.v:4023$473_Y - connect \Y $and$ls180.v:4023$474_Y + connect \A \libresocsim_shared_cyc + connect \B \libresocsim_slave_sel [5] + connect \Y $and$ls180.v:3146$650_Y end - attribute \src "ls180.v:4023.76-4023.333" - cell $and $and$ls180.v:4023$477 + attribute \src "ls180.v:3148.29-3148.76" + cell $and $and$ls180.v:3148$656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4023$470_Y - connect \B $or$ls180.v:4023$476_Y - connect \Y $and$ls180.v:4023$477_Y + connect \A \libresocsim_shared_stb + connect \B \libresocsim_shared_cyc + connect \Y $and$ls180.v:3148$656_Y end - attribute \src "ls180.v:4023.338-4023.505" - cell $and $and$ls180.v:4023$480 + attribute \src "ls180.v:3148.28-3148.105" + cell $and $and$ls180.v:3148$658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4023$478_Y - connect \B $eq$ls180.v:4023$479_Y - connect \Y $and$ls180.v:4023$480_Y + connect \A $and$ls180.v:3148$656_Y + connect \B $not$ls180.v:3148$657_Y + connect \Y $and$ls180.v:3148$658_Y end - attribute \src "ls180.v:4023.38-4023.507" - cell $and $and$ls180.v:4023$482 + attribute \src "ls180.v:3154.36-3154.96" + cell $and $and$ls180.v:3154$665 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:4023$481_Y - connect \Y $and$ls180.v:4023$482_Y + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] } + connect \B \libresocsim_ram_bus_dat_r + connect \Y $and$ls180.v:3154$665_Y end - attribute \src "ls180.v:4024.77-4024.153" - cell $and $and$ls180.v:4024$483 + attribute \src "ls180.v:3154.101-3154.157" + cell $and $and$ls180.v:3154$666 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4024$483_Y + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] } + connect \B \ram_bus_ram_bus_dat_r + connect \Y $and$ls180.v:3154$666_Y end - attribute \src "ls180.v:4024.162-4024.246" - cell $and $and$ls180.v:4024$485 + attribute \src "ls180.v:3154.163-3154.233" + cell $and $and$ls180.v:3154$668 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:4024$484_Y - connect \Y $and$ls180.v:4024$485_Y + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] } + connect \B \libresocsim_libresoc_xics_icp_dat_r + connect \Y $and$ls180.v:3154$668_Y end - attribute \src "ls180.v:4024.161-4024.291" - cell $and $and$ls180.v:4024$487 + attribute \src "ls180.v:3154.239-3154.309" + cell $and $and$ls180.v:3154$670 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4024$485_Y - connect \B $not$ls180.v:4024$486_Y - connect \Y $and$ls180.v:4024$487_Y + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] } + connect \B \libresocsim_libresoc_xics_ics_dat_r + connect \Y $and$ls180.v:3154$670_Y end - attribute \src "ls180.v:4024.76-4024.333" - cell $and $and$ls180.v:4024$490 + attribute \src "ls180.v:3154.315-3154.364" + cell $and $and$ls180.v:3154$672 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4024$483_Y - connect \B $or$ls180.v:4024$489_Y - connect \Y $and$ls180.v:4024$490_Y + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] } + connect \B \wb_sdram_dat_r + connect \Y $and$ls180.v:3154$672_Y end - attribute \src "ls180.v:4024.338-4024.505" - cell $and $and$ls180.v:4024$493 + attribute \src "ls180.v:3154.370-3154.443" + cell $and $and$ls180.v:3154$674 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4024$491_Y - connect \B $eq$ls180.v:4024$492_Y - connect \Y $and$ls180.v:4024$493_Y + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] } + connect \B \libresocsim_libresocsim_wishbone_dat_r + connect \Y $and$ls180.v:3154$674_Y end - attribute \src "ls180.v:4024.38-4024.507" - cell $and $and$ls180.v:4024$495 + attribute \src "ls180.v:3164.43-3164.104" + cell $and $and$ls180.v:3164$678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:4024$494_Y - connect \Y $and$ls180.v:4024$495_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3164$678_Y end - attribute \src "ls180.v:4053.8-4053.73" - cell $and $and$ls180.v:4053$500 + attribute \src "ls180.v:3164.42-3164.158" + cell $and $and$ls180.v:3164$680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4053$500_Y + connect \A $and$ls180.v:3164$678_Y + connect \B $eq$ls180.v:3164$679_Y + connect \Y $and$ls180.v:3164$680_Y end - attribute \src "ls180.v:4053.7-4053.114" - cell $and $and$ls180.v:4053$502 + attribute \src "ls180.v:3165.43-3165.107" + cell $and $and$ls180.v:3165$682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4053$500_Y - connect \B $eq$ls180.v:4053$501_Y - connect \Y $and$ls180.v:4053$502_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3165$681_Y + connect \Y $and$ls180.v:3165$682_Y end - attribute \src "ls180.v:4056.8-4056.73" - cell $and $and$ls180.v:4056$503 + attribute \src "ls180.v:3165.42-3165.161" + cell $and $and$ls180.v:3165$684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4056$503_Y + connect \A $and$ls180.v:3165$682_Y + connect \B $eq$ls180.v:3165$683_Y + connect \Y $and$ls180.v:3165$684_Y end - attribute \src "ls180.v:4056.7-4056.114" - cell $and $and$ls180.v:4056$505 + attribute \src "ls180.v:3167.45-3167.106" + cell $and $and$ls180.v:3167$685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4056$503_Y - connect \B $eq$ls180.v:4056$504_Y - connect \Y $and$ls180.v:4056$505_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3167$685_Y end - attribute \src "ls180.v:4062.8-4062.73" - cell $and $and$ls180.v:4062$507 + attribute \src "ls180.v:3167.44-3167.160" + cell $and $and$ls180.v:3167$687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4062$507_Y + connect \A $and$ls180.v:3167$685_Y + connect \B $eq$ls180.v:3167$686_Y + connect \Y $and$ls180.v:3167$687_Y end - attribute \src "ls180.v:4062.7-4062.114" - cell $and $and$ls180.v:4062$509 + attribute \src "ls180.v:3168.45-3168.109" + cell $and $and$ls180.v:3168$689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4062$507_Y - connect \B $eq$ls180.v:4062$508_Y - connect \Y $and$ls180.v:4062$509_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3168$688_Y + connect \Y $and$ls180.v:3168$689_Y end - attribute \src "ls180.v:4065.8-4065.73" - cell $and $and$ls180.v:4065$510 + attribute \src "ls180.v:3168.44-3168.163" + cell $and $and$ls180.v:3168$691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4065$510_Y + connect \A $and$ls180.v:3168$689_Y + connect \B $eq$ls180.v:3168$690_Y + connect \Y $and$ls180.v:3168$691_Y end - attribute \src "ls180.v:4065.7-4065.114" - cell $and $and$ls180.v:4065$512 + attribute \src "ls180.v:3170.45-3170.106" + cell $and $and$ls180.v:3170$692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4065$510_Y - connect \B $eq$ls180.v:4065$511_Y - connect \Y $and$ls180.v:4065$512_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3170$692_Y end - attribute \src "ls180.v:4071.8-4071.73" - cell $and $and$ls180.v:4071$514 + attribute \src "ls180.v:3170.44-3170.160" + cell $and $and$ls180.v:3170$694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4071$514_Y + connect \A $and$ls180.v:3170$692_Y + connect \B $eq$ls180.v:3170$693_Y + connect \Y $and$ls180.v:3170$694_Y end - attribute \src "ls180.v:4071.7-4071.114" - cell $and $and$ls180.v:4071$516 + attribute \src "ls180.v:3171.45-3171.109" + cell $and $and$ls180.v:3171$696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4071$514_Y - connect \B $eq$ls180.v:4071$515_Y - connect \Y $and$ls180.v:4071$516_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3171$695_Y + connect \Y $and$ls180.v:3171$696_Y end - attribute \src "ls180.v:4074.8-4074.73" - cell $and $and$ls180.v:4074$517 + attribute \src "ls180.v:3171.44-3171.163" + cell $and $and$ls180.v:3171$698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4074$517_Y + connect \A $and$ls180.v:3171$696_Y + connect \B $eq$ls180.v:3171$697_Y + connect \Y $and$ls180.v:3171$698_Y end - attribute \src "ls180.v:4074.7-4074.114" - cell $and $and$ls180.v:4074$519 + attribute \src "ls180.v:3173.45-3173.106" + cell $and $and$ls180.v:3173$699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4074$517_Y - connect \B $eq$ls180.v:4074$518_Y - connect \Y $and$ls180.v:4074$519_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3173$699_Y end - attribute \src "ls180.v:4080.8-4080.73" - cell $and $and$ls180.v:4080$521 + attribute \src "ls180.v:3173.44-3173.160" + cell $and $and$ls180.v:3173$701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4080$521_Y + connect \A $and$ls180.v:3173$699_Y + connect \B $eq$ls180.v:3173$700_Y + connect \Y $and$ls180.v:3173$701_Y end - attribute \src "ls180.v:4080.7-4080.114" - cell $and $and$ls180.v:4080$523 + attribute \src "ls180.v:3174.45-3174.109" + cell $and $and$ls180.v:3174$703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4080$521_Y - connect \B $eq$ls180.v:4080$522_Y - connect \Y $and$ls180.v:4080$523_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3174$702_Y + connect \Y $and$ls180.v:3174$703_Y end - attribute \src "ls180.v:4083.8-4083.73" - cell $and $and$ls180.v:4083$524 + attribute \src "ls180.v:3174.44-3174.163" + cell $and $and$ls180.v:3174$705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4083$524_Y + connect \A $and$ls180.v:3174$703_Y + connect \B $eq$ls180.v:3174$704_Y + connect \Y $and$ls180.v:3174$705_Y end - attribute \src "ls180.v:4083.7-4083.114" - cell $and $and$ls180.v:4083$526 + attribute \src "ls180.v:3176.45-3176.106" + cell $and $and$ls180.v:3176$706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4083$524_Y - connect \B $eq$ls180.v:4083$525_Y - connect \Y $and$ls180.v:4083$526_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3176$706_Y end - attribute \src "ls180.v:4108.71-4108.151" - cell $and $and$ls180.v:4108$531 + attribute \src "ls180.v:3176.44-3176.160" + cell $and $and$ls180.v:3176$708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:4108$530_Y - connect \Y $and$ls180.v:4108$531_Y + connect \A $and$ls180.v:3176$706_Y + connect \B $eq$ls180.v:3176$707_Y + connect \Y $and$ls180.v:3176$708_Y end - attribute \src "ls180.v:4108.70-4108.194" - cell $and $and$ls180.v:4108$533 + attribute \src "ls180.v:3177.45-3177.109" + cell $and $and$ls180.v:3177$710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4108$531_Y - connect \B $not$ls180.v:4108$532_Y - connect \Y $and$ls180.v:4108$533_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3177$709_Y + connect \Y $and$ls180.v:3177$710_Y end - attribute \src "ls180.v:4108.41-4108.222" - cell $and $and$ls180.v:4108$536 + attribute \src "ls180.v:3177.44-3177.163" + cell $and $and$ls180.v:3177$712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:4108$535_Y - connect \Y $and$ls180.v:4108$536_Y + connect \A $and$ls180.v:3177$710_Y + connect \B $eq$ls180.v:3177$711_Y + connect \Y $and$ls180.v:3177$712_Y end - attribute \src "ls180.v:4146.71-4146.151" - cell $and $and$ls180.v:4146$540 + attribute \src "ls180.v:3179.48-3179.109" + cell $and $and$ls180.v:3179$713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:4146$539_Y - connect \Y $and$ls180.v:4146$540_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3179$713_Y end - attribute \src "ls180.v:4146.70-4146.194" - cell $and $and$ls180.v:4146$542 + attribute \src "ls180.v:3179.47-3179.163" + cell $and $and$ls180.v:3179$715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4146$540_Y - connect \B $not$ls180.v:4146$541_Y - connect \Y $and$ls180.v:4146$542_Y + connect \A $and$ls180.v:3179$713_Y + connect \B $eq$ls180.v:3179$714_Y + connect \Y $and$ls180.v:3179$715_Y end - attribute \src "ls180.v:4146.41-4146.222" - cell $and $and$ls180.v:4146$545 + attribute \src "ls180.v:3180.48-3180.112" + cell $and $and$ls180.v:3180$717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:4146$544_Y - connect \Y $and$ls180.v:4146$545_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3180$716_Y + connect \Y $and$ls180.v:3180$717_Y end - attribute \src "ls180.v:4164.110-4164.179" - cell $and $and$ls180.v:4164$550 + attribute \src "ls180.v:3180.47-3180.166" + cell $and $and$ls180.v:3180$719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4164$549_Y - connect \Y $and$ls180.v:4164$550_Y + connect \A $and$ls180.v:3180$717_Y + connect \B $eq$ls180.v:3180$718_Y + connect \Y $and$ls180.v:3180$719_Y end - attribute \src "ls180.v:4164.185-4164.254" - cell $and $and$ls180.v:4164$553 + attribute \src "ls180.v:3182.48-3182.109" + cell $and $and$ls180.v:3182$720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4164$552_Y - connect \Y $and$ls180.v:4164$553_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3182$720_Y end - attribute \src "ls180.v:4164.260-4164.329" - cell $and $and$ls180.v:4164$556 + attribute \src "ls180.v:3182.47-3182.163" + cell $and $and$ls180.v:3182$722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4164$555_Y - connect \Y $and$ls180.v:4164$556_Y + connect \A $and$ls180.v:3182$720_Y + connect \B $eq$ls180.v:3182$721_Y + connect \Y $and$ls180.v:3182$722_Y end - attribute \src "ls180.v:4164.41-4164.332" - cell $and $and$ls180.v:4164$559 + attribute \src "ls180.v:3183.48-3183.112" + cell $and $and$ls180.v:3183$724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4164$548_Y - connect \B $not$ls180.v:4164$558_Y - connect \Y $and$ls180.v:4164$559_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3183$723_Y + connect \Y $and$ls180.v:3183$724_Y end - attribute \src "ls180.v:4164.40-4164.355" - cell $and $and$ls180.v:4164$560 + attribute \src "ls180.v:3183.47-3183.166" + cell $and $and$ls180.v:3183$726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4164$559_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4164$560_Y + connect \A $and$ls180.v:3183$724_Y + connect \B $eq$ls180.v:3183$725_Y + connect \Y $and$ls180.v:3183$726_Y end - attribute \src "ls180.v:4165.34-4165.106" - cell $and $and$ls180.v:4165$563 + attribute \src "ls180.v:3185.48-3185.109" + cell $and $and$ls180.v:3185$727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4165$561_Y - connect \B $not$ls180.v:4165$562_Y - connect \Y $and$ls180.v:4165$563_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3185$727_Y end - attribute \src "ls180.v:4169.110-4169.179" - cell $and $and$ls180.v:4169$566 + attribute \src "ls180.v:3185.47-3185.163" + cell $and $and$ls180.v:3185$729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4169$565_Y - connect \Y $and$ls180.v:4169$566_Y + connect \A $and$ls180.v:3185$727_Y + connect \B $eq$ls180.v:3185$728_Y + connect \Y $and$ls180.v:3185$729_Y end - attribute \src "ls180.v:4169.185-4169.254" - cell $and $and$ls180.v:4169$569 + attribute \src "ls180.v:3186.48-3186.112" + cell $and $and$ls180.v:3186$731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4169$568_Y - connect \Y $and$ls180.v:4169$569_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3186$730_Y + connect \Y $and$ls180.v:3186$731_Y end - attribute \src "ls180.v:4169.260-4169.329" - cell $and $and$ls180.v:4169$572 + attribute \src "ls180.v:3186.47-3186.166" + cell $and $and$ls180.v:3186$733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4169$571_Y - connect \Y $and$ls180.v:4169$572_Y + connect \A $and$ls180.v:3186$731_Y + connect \B $eq$ls180.v:3186$732_Y + connect \Y $and$ls180.v:3186$733_Y end - attribute \src "ls180.v:4169.41-4169.332" - cell $and $and$ls180.v:4169$575 + attribute \src "ls180.v:3188.48-3188.109" + cell $and $and$ls180.v:3188$734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4169$564_Y - connect \B $not$ls180.v:4169$574_Y - connect \Y $and$ls180.v:4169$575_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3188$734_Y end - attribute \src "ls180.v:4169.40-4169.355" - cell $and $and$ls180.v:4169$576 + attribute \src "ls180.v:3188.47-3188.163" + cell $and $and$ls180.v:3188$736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4169$575_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4169$576_Y + connect \A $and$ls180.v:3188$734_Y + connect \B $eq$ls180.v:3188$735_Y + connect \Y $and$ls180.v:3188$736_Y end - attribute \src "ls180.v:4170.34-4170.106" - cell $and $and$ls180.v:4170$579 + attribute \src "ls180.v:3189.48-3189.112" + cell $and $and$ls180.v:3189$738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4170$577_Y - connect \B $not$ls180.v:4170$578_Y - connect \Y $and$ls180.v:4170$579_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3189$737_Y + connect \Y $and$ls180.v:3189$738_Y end - attribute \src "ls180.v:4174.110-4174.179" - cell $and $and$ls180.v:4174$582 + attribute \src "ls180.v:3189.47-3189.166" + cell $and $and$ls180.v:3189$740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4174$581_Y - connect \Y $and$ls180.v:4174$582_Y + connect \A $and$ls180.v:3189$738_Y + connect \B $eq$ls180.v:3189$739_Y + connect \Y $and$ls180.v:3189$740_Y end - attribute \src "ls180.v:4174.185-4174.254" - cell $and $and$ls180.v:4174$585 + attribute \src "ls180.v:3202.40-3202.101" + cell $and $and$ls180.v:3202$742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4174$584_Y - connect \Y $and$ls180.v:4174$585_Y + connect \A \libresocsim_csrbank1_sel + connect \B \libresocsim_interface1_bank_bus_we + connect \Y $and$ls180.v:3202$742_Y end - attribute \src "ls180.v:4174.260-4174.329" - cell $and $and$ls180.v:4174$588 + attribute \src "ls180.v:3202.39-3202.155" + cell $and $and$ls180.v:3202$744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4174$587_Y - connect \Y $and$ls180.v:4174$588_Y + connect \A $and$ls180.v:3202$742_Y + connect \B $eq$ls180.v:3202$743_Y + connect \Y $and$ls180.v:3202$744_Y end - attribute \src "ls180.v:4174.41-4174.332" - cell $and $and$ls180.v:4174$591 + attribute \src "ls180.v:3203.40-3203.104" + cell $and $and$ls180.v:3203$746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4174$580_Y - connect \B $not$ls180.v:4174$590_Y - connect \Y $and$ls180.v:4174$591_Y + connect \A \libresocsim_csrbank1_sel + connect \B $not$ls180.v:3203$745_Y + connect \Y $and$ls180.v:3203$746_Y end - attribute \src "ls180.v:4174.40-4174.355" - cell $and $and$ls180.v:4174$592 + attribute \src "ls180.v:3203.39-3203.158" + cell $and $and$ls180.v:3203$748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4174$591_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4174$592_Y + connect \A $and$ls180.v:3203$746_Y + connect \B $eq$ls180.v:3203$747_Y + connect \Y $and$ls180.v:3203$748_Y end - attribute \src "ls180.v:4175.34-4175.106" - cell $and $and$ls180.v:4175$595 + attribute \src "ls180.v:3205.39-3205.100" + cell $and $and$ls180.v:3205$749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4175$593_Y - connect \B $not$ls180.v:4175$594_Y - connect \Y $and$ls180.v:4175$595_Y + connect \A \libresocsim_csrbank1_sel + connect \B \libresocsim_interface1_bank_bus_we + connect \Y $and$ls180.v:3205$749_Y end - attribute \src "ls180.v:4179.110-4179.179" - cell $and $and$ls180.v:4179$598 + attribute \src "ls180.v:3205.38-3205.154" + cell $and $and$ls180.v:3205$751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4179$597_Y - connect \Y $and$ls180.v:4179$598_Y + connect \A $and$ls180.v:3205$749_Y + connect \B $eq$ls180.v:3205$750_Y + connect \Y $and$ls180.v:3205$751_Y end - attribute \src "ls180.v:4179.185-4179.254" - cell $and $and$ls180.v:4179$601 + attribute \src "ls180.v:3206.39-3206.103" + cell $and $and$ls180.v:3206$753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4179$600_Y - connect \Y $and$ls180.v:4179$601_Y + connect \A \libresocsim_csrbank1_sel + connect \B $not$ls180.v:3206$752_Y + connect \Y $and$ls180.v:3206$753_Y end - attribute \src "ls180.v:4179.260-4179.329" - cell $and $and$ls180.v:4179$604 + attribute \src "ls180.v:3206.38-3206.157" + cell $and $and$ls180.v:3206$755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4179$603_Y - connect \Y $and$ls180.v:4179$604_Y + connect \A $and$ls180.v:3206$753_Y + connect \B $eq$ls180.v:3206$754_Y + connect \Y $and$ls180.v:3206$755_Y end - attribute \src "ls180.v:4179.41-4179.332" - cell $and $and$ls180.v:4179$607 + attribute \src "ls180.v:3208.41-3208.102" + cell $and $and$ls180.v:3208$756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4179$596_Y - connect \B $not$ls180.v:4179$606_Y - connect \Y $and$ls180.v:4179$607_Y + connect \A \libresocsim_csrbank1_sel + connect \B \libresocsim_interface1_bank_bus_we + connect \Y $and$ls180.v:3208$756_Y end - attribute \src "ls180.v:4179.40-4179.355" - cell $and $and$ls180.v:4179$608 + attribute \src "ls180.v:3208.40-3208.156" + cell $and $and$ls180.v:3208$758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4179$607_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4179$608_Y + connect \A $and$ls180.v:3208$756_Y + connect \B $eq$ls180.v:3208$757_Y + connect \Y $and$ls180.v:3208$758_Y end - attribute \src "ls180.v:4180.34-4180.106" - cell $and $and$ls180.v:4180$611 + attribute \src "ls180.v:3209.41-3209.105" + cell $and $and$ls180.v:3209$760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4180$609_Y - connect \B $not$ls180.v:4180$610_Y - connect \Y $and$ls180.v:4180$611_Y + connect \A \libresocsim_csrbank1_sel + connect \B $not$ls180.v:3209$759_Y + connect \Y $and$ls180.v:3209$760_Y end - attribute \src "ls180.v:4184.151-4184.220" - cell $and $and$ls180.v:4184$615 + attribute \src "ls180.v:3209.40-3209.159" + cell $and $and$ls180.v:3209$762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4184$614_Y - connect \Y $and$ls180.v:4184$615_Y + connect \A $and$ls180.v:3209$760_Y + connect \B $eq$ls180.v:3209$761_Y + connect \Y $and$ls180.v:3209$762_Y end - attribute \src "ls180.v:4184.226-4184.295" - cell $and $and$ls180.v:4184$618 + attribute \src "ls180.v:3216.40-3216.101" + cell $and $and$ls180.v:3216$764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4184$617_Y - connect \Y $and$ls180.v:4184$618_Y + connect \A \libresocsim_csrbank2_sel + connect \B \libresocsim_interface2_bank_bus_we + connect \Y $and$ls180.v:3216$764_Y end - attribute \src "ls180.v:4184.301-4184.370" - cell $and $and$ls180.v:4184$621 + attribute \src "ls180.v:3216.39-3216.155" + cell $and $and$ls180.v:3216$766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4184$620_Y - connect \Y $and$ls180.v:4184$621_Y + connect \A $and$ls180.v:3216$764_Y + connect \B $eq$ls180.v:3216$765_Y + connect \Y $and$ls180.v:3216$766_Y end - attribute \src "ls180.v:4184.82-4184.373" - cell $and $and$ls180.v:4184$624 + attribute \src "ls180.v:3217.40-3217.104" + cell $and $and$ls180.v:3217$768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$613_Y - connect \B $not$ls180.v:4184$623_Y - connect \Y $and$ls180.v:4184$624_Y + connect \A \libresocsim_csrbank2_sel + connect \B $not$ls180.v:3217$767_Y + connect \Y $and$ls180.v:3217$768_Y end - attribute \src "ls180.v:4184.43-4184.374" - cell $and $and$ls180.v:4184$625 + attribute \src "ls180.v:3217.39-3217.158" + cell $and $and$ls180.v:3217$770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$612_Y - connect \B $and$ls180.v:4184$624_Y - connect \Y $and$ls180.v:4184$625_Y + connect \A $and$ls180.v:3217$768_Y + connect \B $eq$ls180.v:3217$769_Y + connect \Y $and$ls180.v:3217$770_Y end - attribute \src "ls180.v:4184.42-4184.410" - cell $and $and$ls180.v:4184$626 + attribute \src "ls180.v:3219.39-3219.100" + cell $and $and$ls180.v:3219$771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4184$625_Y - connect \B \main_sdram_interface_bank0_ready - connect \Y $and$ls180.v:4184$626_Y + connect \A \libresocsim_csrbank2_sel + connect \B \libresocsim_interface2_bank_bus_we + connect \Y $and$ls180.v:3219$771_Y end - attribute \src "ls180.v:4184.525-4184.594" - cell $and $and$ls180.v:4184$631 + attribute \src "ls180.v:3219.38-3219.154" + cell $and $and$ls180.v:3219$773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4184$630_Y - connect \Y $and$ls180.v:4184$631_Y + connect \A $and$ls180.v:3219$771_Y + connect \B $eq$ls180.v:3219$772_Y + connect \Y $and$ls180.v:3219$773_Y end - attribute \src "ls180.v:4184.600-4184.669" - cell $and $and$ls180.v:4184$634 + attribute \src "ls180.v:3220.39-3220.103" + cell $and $and$ls180.v:3220$775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4184$633_Y - connect \Y $and$ls180.v:4184$634_Y + connect \A \libresocsim_csrbank2_sel + connect \B $not$ls180.v:3220$774_Y + connect \Y $and$ls180.v:3220$775_Y end - attribute \src "ls180.v:4184.675-4184.744" - cell $and $and$ls180.v:4184$637 + attribute \src "ls180.v:3220.38-3220.157" + cell $and $and$ls180.v:3220$777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4184$636_Y - connect \Y $and$ls180.v:4184$637_Y + connect \A $and$ls180.v:3220$775_Y + connect \B $eq$ls180.v:3220$776_Y + connect \Y $and$ls180.v:3220$777_Y end - attribute \src "ls180.v:4184.456-4184.747" - cell $and $and$ls180.v:4184$640 + attribute \src "ls180.v:3222.41-3222.102" + cell $and $and$ls180.v:3222$778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$629_Y - connect \B $not$ls180.v:4184$639_Y - connect \Y $and$ls180.v:4184$640_Y + connect \A \libresocsim_csrbank2_sel + connect \B \libresocsim_interface2_bank_bus_we + connect \Y $and$ls180.v:3222$778_Y end - attribute \src "ls180.v:4184.417-4184.748" - cell $and $and$ls180.v:4184$641 + attribute \src "ls180.v:3222.40-3222.156" + cell $and $and$ls180.v:3222$780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$628_Y - connect \B $and$ls180.v:4184$640_Y - connect \Y $and$ls180.v:4184$641_Y + connect \A $and$ls180.v:3222$778_Y + connect \B $eq$ls180.v:3222$779_Y + connect \Y $and$ls180.v:3222$780_Y end - attribute \src "ls180.v:4184.416-4184.784" - cell $and $and$ls180.v:4184$642 + attribute \src "ls180.v:3223.41-3223.105" + cell $and $and$ls180.v:3223$782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4184$641_Y - connect \B \main_sdram_interface_bank1_ready - connect \Y $and$ls180.v:4184$642_Y + connect \A \libresocsim_csrbank2_sel + connect \B $not$ls180.v:3223$781_Y + connect \Y $and$ls180.v:3223$782_Y end - attribute \src "ls180.v:4184.899-4184.968" - cell $and $and$ls180.v:4184$647 + attribute \src "ls180.v:3223.40-3223.159" + cell $and $and$ls180.v:3223$784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4184$646_Y - connect \Y $and$ls180.v:4184$647_Y + connect \A $and$ls180.v:3223$782_Y + connect \B $eq$ls180.v:3223$783_Y + connect \Y $and$ls180.v:3223$784_Y end - attribute \src "ls180.v:4184.974-4184.1043" - cell $and $and$ls180.v:4184$650 + attribute \src "ls180.v:3230.39-3230.100" + cell $and $and$ls180.v:3230$786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4184$649_Y - connect \Y $and$ls180.v:4184$650_Y + connect \A \libresocsim_csrbank3_sel + connect \B \libresocsim_interface3_bank_bus_we + connect \Y $and$ls180.v:3230$786_Y end - attribute \src "ls180.v:4184.1049-4184.1118" - cell $and $and$ls180.v:4184$653 + attribute \src "ls180.v:3230.38-3230.152" + cell $and $and$ls180.v:3230$788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4184$652_Y - connect \Y $and$ls180.v:4184$653_Y + connect \A $and$ls180.v:3230$786_Y + connect \B $eq$ls180.v:3230$787_Y + connect \Y $and$ls180.v:3230$788_Y end - attribute \src "ls180.v:4184.830-4184.1121" - cell $and $and$ls180.v:4184$656 + attribute \src "ls180.v:3231.39-3231.103" + cell $and $and$ls180.v:3231$790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$645_Y - connect \B $not$ls180.v:4184$655_Y - connect \Y $and$ls180.v:4184$656_Y + connect \A \libresocsim_csrbank3_sel + connect \B $not$ls180.v:3231$789_Y + connect \Y $and$ls180.v:3231$790_Y end - attribute \src "ls180.v:4184.791-4184.1122" - cell $and $and$ls180.v:4184$657 + attribute \src "ls180.v:3231.38-3231.155" + cell $and $and$ls180.v:3231$792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$644_Y - connect \B $and$ls180.v:4184$656_Y - connect \Y $and$ls180.v:4184$657_Y + connect \A $and$ls180.v:3231$790_Y + connect \B $eq$ls180.v:3231$791_Y + connect \Y $and$ls180.v:3231$792_Y end - attribute \src "ls180.v:4184.790-4184.1158" - cell $and $and$ls180.v:4184$658 + attribute \src "ls180.v:3233.38-3233.99" + cell $and $and$ls180.v:3233$793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4184$657_Y - connect \B \main_sdram_interface_bank2_ready - connect \Y $and$ls180.v:4184$658_Y + connect \A \libresocsim_csrbank3_sel + connect \B \libresocsim_interface3_bank_bus_we + connect \Y $and$ls180.v:3233$793_Y end - attribute \src "ls180.v:4184.1273-4184.1342" - cell $and $and$ls180.v:4184$663 + attribute \src "ls180.v:3233.37-3233.151" + cell $and $and$ls180.v:3233$795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4184$662_Y - connect \Y $and$ls180.v:4184$663_Y + connect \A $and$ls180.v:3233$793_Y + connect \B $eq$ls180.v:3233$794_Y + connect \Y $and$ls180.v:3233$795_Y end - attribute \src "ls180.v:4184.1348-4184.1417" - cell $and $and$ls180.v:4184$666 + attribute \src "ls180.v:3234.38-3234.102" + cell $and $and$ls180.v:3234$797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4184$665_Y - connect \Y $and$ls180.v:4184$666_Y + connect \A \libresocsim_csrbank3_sel + connect \B $not$ls180.v:3234$796_Y + connect \Y $and$ls180.v:3234$797_Y end - attribute \src "ls180.v:4184.1423-4184.1492" - cell $and $and$ls180.v:4184$669 + attribute \src "ls180.v:3234.37-3234.154" + cell $and $and$ls180.v:3234$799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4184$668_Y - connect \Y $and$ls180.v:4184$669_Y + connect \A $and$ls180.v:3234$797_Y + connect \B $eq$ls180.v:3234$798_Y + connect \Y $and$ls180.v:3234$799_Y end - attribute \src "ls180.v:4184.1204-4184.1495" - cell $and $and$ls180.v:4184$672 + attribute \src "ls180.v:3244.50-3244.111" + cell $and $and$ls180.v:3244$801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$661_Y - connect \B $not$ls180.v:4184$671_Y - connect \Y $and$ls180.v:4184$672_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3244$801_Y end - attribute \src "ls180.v:4184.1165-4184.1496" - cell $and $and$ls180.v:4184$673 + attribute \src "ls180.v:3244.49-3244.165" + cell $and $and$ls180.v:3244$803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$660_Y - connect \B $and$ls180.v:4184$672_Y - connect \Y $and$ls180.v:4184$673_Y + connect \A $and$ls180.v:3244$801_Y + connect \B $eq$ls180.v:3244$802_Y + connect \Y $and$ls180.v:3244$803_Y end - attribute \src "ls180.v:4184.1164-4184.1532" - cell $and $and$ls180.v:4184$674 + attribute \src "ls180.v:3245.50-3245.114" + cell $and $and$ls180.v:3245$805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4184$673_Y - connect \B \main_sdram_interface_bank3_ready - connect \Y $and$ls180.v:4184$674_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3245$804_Y + connect \Y $and$ls180.v:3245$805_Y end - attribute \src "ls180.v:4242.9-4242.46" - cell $and $and$ls180.v:4242$680 + attribute \src "ls180.v:3245.49-3245.168" + cell $and $and$ls180.v:3245$807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_stb - connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4242$680_Y + connect \A $and$ls180.v:3245$805_Y + connect \B $eq$ls180.v:3245$806_Y + connect \Y $and$ls180.v:3245$807_Y end - attribute \src "ls180.v:4260.9-4260.46" - cell $and $and$ls180.v:4260$687 + attribute \src "ls180.v:3247.54-3247.115" + cell $and $and$ls180.v:3247$808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_stb - connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4260$687_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3247$808_Y end - attribute \src "ls180.v:4273.32-4273.75" - cell $and $and$ls180.v:4273$691 + attribute \src "ls180.v:3247.53-3247.169" + cell $and $and$ls180.v:3247$810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_cyc - connect \B \main_litedram_wb_stb - connect \Y $and$ls180.v:4273$691_Y + connect \A $and$ls180.v:3247$808_Y + connect \B $eq$ls180.v:3247$809_Y + connect \Y $and$ls180.v:3247$810_Y end - attribute \src "ls180.v:4273.31-4273.99" - cell $and $and$ls180.v:4273$693 + attribute \src "ls180.v:3248.54-3248.118" + cell $and $and$ls180.v:3248$812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4273$691_Y - connect \B $not$ls180.v:4273$692_Y - connect \Y $and$ls180.v:4273$693_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3248$811_Y + connect \Y $and$ls180.v:3248$812_Y end - attribute \src "ls180.v:4274.34-4274.102" - cell $and $and$ls180.v:4274$695 + attribute \src "ls180.v:3248.53-3248.172" + cell $and $and$ls180.v:3248$814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4274$694_Y - connect \B \main_port_cmd_payload_we - connect \Y $and$ls180.v:4274$695_Y + connect \A $and$ls180.v:3248$812_Y + connect \B $eq$ls180.v:3248$813_Y + connect \Y $and$ls180.v:3248$814_Y end - attribute \src "ls180.v:4274.33-4274.128" - cell $and $and$ls180.v:4274$697 + attribute \src "ls180.v:3250.35-3250.96" + cell $and $and$ls180.v:3250$815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4274$695_Y - connect \B $not$ls180.v:4274$696_Y - connect \Y $and$ls180.v:4274$697_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3250$815_Y end - attribute \src "ls180.v:4275.33-4275.104" - cell $and $and$ls180.v:4275$700 + attribute \src "ls180.v:3250.34-3250.150" + cell $and $and$ls180.v:3250$817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4275$698_Y - connect \B $not$ls180.v:4275$699_Y - connect \Y $and$ls180.v:4275$700_Y + connect \A $and$ls180.v:3250$815_Y + connect \B $eq$ls180.v:3250$816_Y + connect \Y $and$ls180.v:3250$817_Y end - attribute \src "ls180.v:4276.49-4276.85" - cell $and $and$ls180.v:4276$701 + attribute \src "ls180.v:3251.35-3251.99" + cell $and $and$ls180.v:3251$819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \B \main_ack_wdata - connect \Y $and$ls180.v:4276$701_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3251$818_Y + connect \Y $and$ls180.v:3251$819_Y end - attribute \src "ls180.v:4276.90-4276.129" - cell $and $and$ls180.v:4276$703 + attribute \src "ls180.v:3251.34-3251.153" + cell $and $and$ls180.v:3251$821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4276$702_Y - connect \B \main_ack_rdata - connect \Y $and$ls180.v:4276$703_Y + connect \A $and$ls180.v:3251$819_Y + connect \B $eq$ls180.v:3251$820_Y + connect \Y $and$ls180.v:3251$821_Y end - attribute \src "ls180.v:4276.32-4276.131" - cell $and $and$ls180.v:4276$705 + attribute \src "ls180.v:3253.54-3253.115" + cell $and $and$ls180.v:3253$822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_ack_cmd - connect \B $or$ls180.v:4276$704_Y - connect \Y $and$ls180.v:4276$705_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3253$822_Y end - attribute \src "ls180.v:4277.25-4277.66" - cell $and $and$ls180.v:4277$706 + attribute \src "ls180.v:3253.53-3253.169" + cell $and $and$ls180.v:3253$824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:4277$706_Y + connect \A $and$ls180.v:3253$822_Y + connect \B $eq$ls180.v:3253$823_Y + connect \Y $and$ls180.v:3253$824_Y end - attribute \src "ls180.v:4278.27-4278.72" - cell $and $and$ls180.v:4278$708 + attribute \src "ls180.v:3254.54-3254.118" + cell $and $and$ls180.v:3254$826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_wdata_valid - connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:4278$708_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3254$825_Y + connect \Y $and$ls180.v:3254$826_Y end - attribute \src "ls180.v:4279.26-4279.71" - cell $and $and$ls180.v:4279$710 + attribute \src "ls180.v:3254.53-3254.172" + cell $and $and$ls180.v:3254$828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_rdata_valid - connect \B \main_port_rdata_ready - connect \Y $and$ls180.v:4279$710_Y + connect \A $and$ls180.v:3254$826_Y + connect \B $eq$ls180.v:3254$827_Y + connect \Y $and$ls180.v:3254$828_Y end - attribute \src "ls180.v:4308.64-4308.88" - cell $and $and$ls180.v:4308$716 + attribute \src "ls180.v:3256.54-3256.115" + cell $and $and$ls180.v:3256$829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B \main_uart_rxtx_we - connect \Y $and$ls180.v:4308$716_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3256$829_Y end - attribute \src "ls180.v:4312.7-4312.78" - cell $and $and$ls180.v:4312$720 + attribute \src "ls180.v:3256.53-3256.169" + cell $and $and$ls180.v:3256$831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_re - connect \B \main_uart_eventmanager_pending_r [0] - connect \Y $and$ls180.v:4312$720_Y + connect \A $and$ls180.v:3256$829_Y + connect \B $eq$ls180.v:3256$830_Y + connect \Y $and$ls180.v:3256$831_Y end - attribute \src "ls180.v:4323.7-4323.78" - cell $and $and$ls180.v:4323$723 + attribute \src "ls180.v:3257.54-3257.118" + cell $and $and$ls180.v:3257$833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_re - connect \B \main_uart_eventmanager_pending_r [1] - connect \Y $and$ls180.v:4323$723_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3257$832_Y + connect \Y $and$ls180.v:3257$833_Y end - attribute \src "ls180.v:4332.26-4332.97" - cell $and $and$ls180.v:4332$725 + attribute \src "ls180.v:3257.53-3257.172" + cell $and $and$ls180.v:3257$835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_w [0] - connect \B \main_uart_eventmanager_storage [0] - connect \Y $and$ls180.v:4332$725_Y + connect \A $and$ls180.v:3257$833_Y + connect \B $eq$ls180.v:3257$834_Y + connect \Y $and$ls180.v:3257$835_Y end - attribute \src "ls180.v:4332.102-4332.173" - cell $and $and$ls180.v:4332$726 + attribute \src "ls180.v:3259.55-3259.116" + cell $and $and$ls180.v:3259$836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_w [1] - connect \B \main_uart_eventmanager_storage [1] - connect \Y $and$ls180.v:4332$726_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3259$836_Y end - attribute \src "ls180.v:4347.41-4347.133" - cell $and $and$ls180.v:4347$730 + attribute \src "ls180.v:3259.54-3259.170" + cell $and $and$ls180.v:3259$838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B $or$ls180.v:4347$729_Y - connect \Y $and$ls180.v:4347$730_Y + connect \A $and$ls180.v:3259$836_Y + connect \B $eq$ls180.v:3259$837_Y + connect \Y $and$ls180.v:3259$838_Y end - attribute \src "ls180.v:4358.39-4358.136" - cell $and $and$ls180.v:4358$735 + attribute \src "ls180.v:3260.55-3260.119" + cell $and $and$ls180.v:3260$840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B $or$ls180.v:4358$734_Y - connect \Y $and$ls180.v:4358$735_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3260$839_Y + connect \Y $and$ls180.v:3260$840_Y end - attribute \src "ls180.v:4359.37-4359.104" - cell $and $and$ls180.v:4359$736 + attribute \src "ls180.v:3260.54-3260.173" + cell $and $and$ls180.v:3260$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B \main_uart_tx_fifo_syncfifo_re - connect \Y $and$ls180.v:4359$736_Y + connect \A $and$ls180.v:3260$840_Y + connect \B $eq$ls180.v:3260$841_Y + connect \Y $and$ls180.v:3260$842_Y end - attribute \src "ls180.v:4377.41-4377.133" - cell $and $and$ls180.v:4377$741 + attribute \src "ls180.v:3262.53-3262.114" + cell $and $and$ls180.v:3262$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B $or$ls180.v:4377$740_Y - connect \Y $and$ls180.v:4377$741_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3262$843_Y end - attribute \src "ls180.v:4388.39-4388.136" - cell $and $and$ls180.v:4388$746 + attribute \src "ls180.v:3262.52-3262.168" + cell $and $and$ls180.v:3262$845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B $or$ls180.v:4388$745_Y - connect \Y $and$ls180.v:4388$746_Y + connect \A $and$ls180.v:3262$843_Y + connect \B $eq$ls180.v:3262$844_Y + connect \Y $and$ls180.v:3262$845_Y end - attribute \src "ls180.v:4389.37-4389.104" - cell $and $and$ls180.v:4389$747 + attribute \src "ls180.v:3263.53-3263.117" + cell $and $and$ls180.v:3263$847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B \main_uart_rx_fifo_syncfifo_re - connect \Y $and$ls180.v:4389$747_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3263$846_Y + connect \Y $and$ls180.v:3263$847_Y end - attribute \src "ls180.v:4588.33-4588.86" - cell $and $and$ls180.v:4588$791 + attribute \src "ls180.v:3263.52-3263.171" + cell $and $and$ls180.v:3263$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk1 - connect \B $not$ls180.v:4588$790_Y - connect \Y $and$ls180.v:4588$791_Y + connect \A $and$ls180.v:3263$847_Y + connect \B $eq$ls180.v:3263$848_Y + connect \Y $and$ls180.v:3263$849_Y end - attribute \src "ls180.v:4692.9-4692.68" - cell $and $and$ls180.v:4692$800 + attribute \src "ls180.v:3265.53-3265.114" + cell $and $and$ls180.v:3265$850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_sink_valid - connect \B \main_sdphy_cmdw_pads_out_ready - connect \Y $and$ls180.v:4692$800_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3265$850_Y end - attribute \src "ls180.v:4712.53-4712.145" - cell $and $and$ls180.v:4712$803 + attribute \src "ls180.v:3265.52-3265.168" + cell $and $and$ls180.v:3265$852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_pads_in_valid - connect \B $or$ls180.v:4712$802_Y - connect \Y $and$ls180.v:4712$803_Y + connect \A $and$ls180.v:3265$850_Y + connect \B $eq$ls180.v:3265$851_Y + connect \Y $and$ls180.v:3265$852_Y end - attribute \src "ls180.v:4731.52-4731.137" - cell $and $and$ls180.v:4731$806 + attribute \src "ls180.v:3266.53-3266.117" + cell $and $and$ls180.v:3266$854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:4731$806_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3266$853_Y + connect \Y $and$ls180.v:3266$854_Y end - attribute \src "ls180.v:4772.9-4772.68" - cell $and $and$ls180.v:4772$814 + attribute \src "ls180.v:3266.52-3266.171" + cell $and $and$ls180.v:3266$856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_valid - connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4772$814_Y + connect \A $and$ls180.v:3266$854_Y + connect \B $eq$ls180.v:3266$855_Y + connect \Y $and$ls180.v:3266$856_Y end - attribute \src "ls180.v:4810.9-4810.68" - cell $and $and$ls180.v:4810$820 + attribute \src "ls180.v:3268.53-3268.114" + cell $and $and$ls180.v:3268$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_valid - connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4810$820_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3268$857_Y end - attribute \src "ls180.v:4819.10-4819.69" - cell $and $and$ls180.v:4819$821 + attribute \src "ls180.v:3268.52-3268.168" + cell $and $and$ls180.v:3268$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_sink_valid - connect \B \main_sdphy_cmdr_pads_out_ready - connect \Y $and$ls180.v:4819$821_Y + connect \A $and$ls180.v:3268$857_Y + connect \B $eq$ls180.v:3268$858_Y + connect \Y $and$ls180.v:3268$859_Y end - attribute \src "ls180.v:4819.9-4819.93" - cell $and $and$ls180.v:4819$822 + attribute \src "ls180.v:3269.53-3269.117" + cell $and $and$ls180.v:3269$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4819$821_Y - connect \B \main_sdphy_cmdw_done - connect \Y $and$ls180.v:4819$822_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3269$860_Y + connect \Y $and$ls180.v:3269$861_Y end - attribute \src "ls180.v:4839.54-4839.117" - cell $and $and$ls180.v:4839$824 + attribute \src "ls180.v:3269.52-3269.171" + cell $and $and$ls180.v:3269$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_pads_in_valid - connect \B \main_sdphy_dataw_crcr_run - connect \Y $and$ls180.v:4839$824_Y + connect \A $and$ls180.v:3269$861_Y + connect \B $eq$ls180.v:3269$862_Y + connect \Y $and$ls180.v:3269$863_Y end - attribute \src "ls180.v:4858.53-4858.140" - cell $and $and$ls180.v:4858$827 + attribute \src "ls180.v:3271.53-3271.114" + cell $and $and$ls180.v:3271$864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:4858$827_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3271$864_Y end - attribute \src "ls180.v:4955.9-4955.70" - cell $and $and$ls180.v:4955$837 + attribute \src "ls180.v:3271.52-3271.168" + cell $and $and$ls180.v:3271$866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \B \main_sdphy_dataw_pads_out_ready - connect \Y $and$ls180.v:4955$837_Y + connect \A $and$ls180.v:3271$864_Y + connect \B $eq$ls180.v:3271$865_Y + connect \Y $and$ls180.v:3271$866_Y end - attribute \src "ls180.v:4973.55-4973.120" - cell $and $and$ls180.v:4973$839 + attribute \src "ls180.v:3272.53-3272.117" + cell $and $and$ls180.v:3272$868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_pads_in_valid - connect \B \main_sdphy_datar_datar_run - connect \Y $and$ls180.v:4973$839_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3272$867_Y + connect \Y $and$ls180.v:3272$868_Y end - attribute \src "ls180.v:4992.54-4992.143" - cell $and $and$ls180.v:4992$842 + attribute \src "ls180.v:3272.52-3272.171" + cell $and $and$ls180.v:3272$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:4992$842_Y + connect \A $and$ls180.v:3272$868_Y + connect \B $eq$ls180.v:3272$869_Y + connect \Y $and$ls180.v:3272$870_Y end - attribute \src "ls180.v:5074.9-5074.70" - cell $and $and$ls180.v:5074$857 + attribute \src "ls180.v:3289.42-3289.103" + cell $and $and$ls180.v:3289$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_valid - connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5074$857_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3289$872_Y end - attribute \src "ls180.v:5081.9-5081.70" - cell $and $and$ls180.v:5081$858 + attribute \src "ls180.v:3289.41-3289.157" + cell $and $and$ls180.v:3289$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_sink_valid - connect \B \main_sdphy_datar_pads_out_ready - connect \Y $and$ls180.v:5081$858_Y + connect \A $and$ls180.v:3289$872_Y + connect \B $eq$ls180.v:3289$873_Y + connect \Y $and$ls180.v:3289$874_Y end - attribute \src "ls180.v:5162.48-5162.124" - cell $and $and$ls180.v:5162$981 + attribute \src "ls180.v:3290.42-3290.106" + cell $and $and$ls180.v:3290$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5162$981_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3290$875_Y + connect \Y $and$ls180.v:3290$876_Y end - attribute \src "ls180.v:5162.47-5162.165" - cell $and $and$ls180.v:5162$982 + attribute \src "ls180.v:3290.41-3290.160" + cell $and $and$ls180.v:3290$878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5162$981_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5162$982_Y + connect \A $and$ls180.v:3290$876_Y + connect \B $eq$ls180.v:3290$877_Y + connect \Y $and$ls180.v:3290$878_Y end - attribute \src "ls180.v:5163.50-5163.127" - cell $and $and$ls180.v:5163$983 + attribute \src "ls180.v:3292.42-3292.103" + cell $and $and$ls180.v:3292$879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5163$983_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3292$879_Y end - attribute \src "ls180.v:5165.48-5165.124" - cell $and $and$ls180.v:5165$984 + attribute \src "ls180.v:3292.41-3292.157" + cell $and $and$ls180.v:3292$881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5165$984_Y + connect \A $and$ls180.v:3292$879_Y + connect \B $eq$ls180.v:3292$880_Y + connect \Y $and$ls180.v:3292$881_Y end - attribute \src "ls180.v:5165.47-5165.165" - cell $and $and$ls180.v:5165$985 + attribute \src "ls180.v:3293.42-3293.106" + cell $and $and$ls180.v:3293$883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5165$984_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5165$985_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3293$882_Y + connect \Y $and$ls180.v:3293$883_Y end - attribute \src "ls180.v:5166.50-5166.127" - cell $and $and$ls180.v:5166$986 + attribute \src "ls180.v:3293.41-3293.160" + cell $and $and$ls180.v:3293$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5166$986_Y + connect \A $and$ls180.v:3293$883_Y + connect \B $eq$ls180.v:3293$884_Y + connect \Y $and$ls180.v:3293$885_Y end - attribute \src "ls180.v:5168.48-5168.124" - cell $and $and$ls180.v:5168$987 + attribute \src "ls180.v:3295.42-3295.103" + cell $and $and$ls180.v:3295$886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5168$987_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3295$886_Y end - attribute \src "ls180.v:5168.47-5168.165" - cell $and $and$ls180.v:5168$988 + attribute \src "ls180.v:3295.41-3295.157" + cell $and $and$ls180.v:3295$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5168$987_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5168$988_Y + connect \A $and$ls180.v:3295$886_Y + connect \B $eq$ls180.v:3295$887_Y + connect \Y $and$ls180.v:3295$888_Y end - attribute \src "ls180.v:5169.50-5169.127" - cell $and $and$ls180.v:5169$989 + attribute \src "ls180.v:3296.42-3296.106" + cell $and $and$ls180.v:3296$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5169$989_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3296$889_Y + connect \Y $and$ls180.v:3296$890_Y end - attribute \src "ls180.v:5171.48-5171.124" - cell $and $and$ls180.v:5171$990 + attribute \src "ls180.v:3296.41-3296.160" + cell $and $and$ls180.v:3296$892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5171$990_Y + connect \A $and$ls180.v:3296$890_Y + connect \B $eq$ls180.v:3296$891_Y + connect \Y $and$ls180.v:3296$892_Y end - attribute \src "ls180.v:5171.47-5171.165" - cell $and $and$ls180.v:5171$991 + attribute \src "ls180.v:3298.42-3298.103" + cell $and $and$ls180.v:3298$893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5171$990_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5171$991_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3298$893_Y end - attribute \src "ls180.v:5172.50-5172.127" - cell $and $and$ls180.v:5172$992 + attribute \src "ls180.v:3298.41-3298.157" + cell $and $and$ls180.v:3298$895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5172$992_Y + connect \A $and$ls180.v:3298$893_Y + connect \B $eq$ls180.v:3298$894_Y + connect \Y $and$ls180.v:3298$895_Y end - attribute \src "ls180.v:5285.10-5285.86" - cell $and $and$ls180.v:5285$1041 + attribute \src "ls180.v:3299.42-3299.106" + cell $and $and$ls180.v:3299$897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_last - connect \Y $and$ls180.v:5285$1041_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3299$896_Y + connect \Y $and$ls180.v:3299$897_Y end - attribute \src "ls180.v:5285.9-5285.127" - cell $and $and$ls180.v:5285$1042 + attribute \src "ls180.v:3299.41-3299.160" + cell $and $and$ls180.v:3299$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5285$1041_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5285$1042_Y + connect \A $and$ls180.v:3299$897_Y + connect \B $eq$ls180.v:3299$898_Y + connect \Y $and$ls180.v:3299$899_Y end - attribute \src "ls180.v:5295.9-5295.152" - cell $and $and$ls180.v:5295$1046 + attribute \src "ls180.v:3301.44-3301.105" + cell $and $and$ls180.v:3301$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:5295$1044_Y - connect \B $eq$ls180.v:5295$1045_Y - connect \Y $and$ls180.v:5295$1046_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3301$900_Y end - attribute \src "ls180.v:5295.8-5295.226" - cell $and $and$ls180.v:5295$1048 + attribute \src "ls180.v:3301.43-3301.159" + cell $and $and$ls180.v:3301$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5295$1046_Y - connect \B $eq$ls180.v:5295$1047_Y - connect \Y $and$ls180.v:5295$1048_Y + connect \A $and$ls180.v:3301$900_Y + connect \B $eq$ls180.v:3301$901_Y + connect \Y $and$ls180.v:3301$902_Y end - attribute \src "ls180.v:5295.7-5295.300" - cell $and $and$ls180.v:5295$1050 + attribute \src "ls180.v:3302.44-3302.108" + cell $and $and$ls180.v:3302$904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5295$1048_Y - connect \B $eq$ls180.v:5295$1049_Y - connect \Y $and$ls180.v:5295$1050_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3302$903_Y + connect \Y $and$ls180.v:3302$904_Y end - attribute \src "ls180.v:5300.49-5300.124" - cell $and $and$ls180.v:5300$1051 + attribute \src "ls180.v:3302.43-3302.162" + cell $and $and$ls180.v:3302$906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5300$1051_Y + connect \A $and$ls180.v:3302$904_Y + connect \B $eq$ls180.v:3302$905_Y + connect \Y $and$ls180.v:3302$906_Y end - attribute \src "ls180.v:5310.49-5310.124" - cell $and $and$ls180.v:5310$1054 + attribute \src "ls180.v:3304.44-3304.105" + cell $and $and$ls180.v:3304$907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5310$1054_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3304$907_Y end - attribute \src "ls180.v:5320.49-5320.124" - cell $and $and$ls180.v:5320$1057 + attribute \src "ls180.v:3304.43-3304.159" + cell $and $and$ls180.v:3304$909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5320$1057_Y + connect \A $and$ls180.v:3304$907_Y + connect \B $eq$ls180.v:3304$908_Y + connect \Y $and$ls180.v:3304$909_Y end - attribute \src "ls180.v:5330.49-5330.124" - cell $and $and$ls180.v:5330$1060 + attribute \src "ls180.v:3305.44-3305.108" + cell $and $and$ls180.v:3305$911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5330$1060_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3305$910_Y + connect \Y $and$ls180.v:3305$911_Y end - attribute \src "ls180.v:5342.7-5342.84" - cell $and $and$ls180.v:5342$1065 + attribute \src "ls180.v:3305.43-3305.162" + cell $and $and$ls180.v:3305$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B $gt$ls180.v:5342$1064_Y - connect \Y $and$ls180.v:5342$1065_Y + connect \A $and$ls180.v:3305$911_Y + connect \B $eq$ls180.v:3305$912_Y + connect \Y $and$ls180.v:3305$913_Y end - attribute \src "ls180.v:5460.9-5460.64" - cell $and $and$ls180.v:5460$1114 + attribute \src "ls180.v:3307.44-3307.105" + cell $and $and$ls180.v:3307$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_sink_valid - connect \B \main_sdphy_cmdw_sink_ready - connect \Y $and$ls180.v:5460$1114_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3307$914_Y end - attribute \src "ls180.v:5512.10-5512.66" - cell $and $and$ls180.v:5512$1123 + attribute \src "ls180.v:3307.43-3307.159" + cell $and $and$ls180.v:3307$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \B \main_sdphy_dataw_sink_last - connect \Y $and$ls180.v:5512$1123_Y + connect \A $and$ls180.v:3307$914_Y + connect \B $eq$ls180.v:3307$915_Y + connect \Y $and$ls180.v:3307$916_Y end - attribute \src "ls180.v:5512.9-5512.97" - cell $and $and$ls180.v:5512$1124 + attribute \src "ls180.v:3308.44-3308.108" + cell $and $and$ls180.v:3308$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5512$1123_Y - connect \B \main_sdphy_dataw_sink_ready - connect \Y $and$ls180.v:5512$1124_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3308$917_Y + connect \Y $and$ls180.v:3308$918_Y end - attribute \src "ls180.v:5538.11-5538.71" - cell $and $and$ls180.v:5538$1132 + attribute \src "ls180.v:3308.43-3308.162" + cell $and $and$ls180.v:3308$920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_last - connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5538$1132_Y + connect \A $and$ls180.v:3308$918_Y + connect \B $eq$ls180.v:3308$919_Y + connect \Y $and$ls180.v:3308$920_Y end - attribute \src "ls180.v:5622.43-5622.152" - cell $and $and$ls180.v:5622$1140 + attribute \src "ls180.v:3310.44-3310.105" + cell $and $and$ls180.v:3310$921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B $or$ls180.v:5622$1139_Y - connect \Y $and$ls180.v:5622$1140_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3310$921_Y end - attribute \src "ls180.v:5623.41-5623.116" - cell $and $and$ls180.v:5623$1141 + attribute \src "ls180.v:3310.43-3310.159" + cell $and $and$ls180.v:3310$923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_readable - connect \B \main_sdblock2mem_fifo_syncfifo_re - connect \Y $and$ls180.v:5623$1141_Y + connect \A $and$ls180.v:3310$921_Y + connect \B $eq$ls180.v:3310$922_Y + connect \Y $and$ls180.v:3310$923_Y end - attribute \src "ls180.v:5635.48-5635.125" - cell $and $and$ls180.v:5635$1146 + attribute \src "ls180.v:3311.44-3311.108" + cell $and $and$ls180.v:3311$925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:5635$1146_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3311$924_Y + connect \Y $and$ls180.v:3311$925_Y end - attribute \src "ls180.v:5662.9-5662.102" - cell $and $and$ls180.v:5662$1150 + attribute \src "ls180.v:3311.43-3311.162" + cell $and $and$ls180.v:3311$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid - connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \Y $and$ls180.v:5662$1150_Y + connect \A $and$ls180.v:3311$925_Y + connect \B $eq$ls180.v:3311$926_Y + connect \Y $and$ls180.v:3311$927_Y end - attribute \src "ls180.v:5735.9-5735.58" - cell $and $and$ls180.v:5735$1156 + attribute \src "ls180.v:3313.40-3313.101" + cell $and $and$ls180.v:3313$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_bus_stb - connect \B \main_interface1_bus_ack - connect \Y $and$ls180.v:5735$1156_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3313$928_Y end - attribute \src "ls180.v:5788.51-5788.123" - cell $and $and$ls180.v:5788$1164 + attribute \src "ls180.v:3313.39-3313.155" + cell $and $and$ls180.v:3313$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_sink_first - connect \B \main_sdmem2block_converter_first - connect \Y $and$ls180.v:5788$1164_Y + connect \A $and$ls180.v:3313$928_Y + connect \B $eq$ls180.v:3313$929_Y + connect \Y $and$ls180.v:3313$930_Y end - attribute \src "ls180.v:5789.50-5789.120" - cell $and $and$ls180.v:5789$1165 + attribute \src "ls180.v:3314.40-3314.104" + cell $and $and$ls180.v:3314$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_sink_last - connect \B \main_sdmem2block_converter_last - connect \Y $and$ls180.v:5789$1165_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3314$931_Y + connect \Y $and$ls180.v:3314$932_Y end - attribute \src "ls180.v:5790.49-5790.122" - cell $and $and$ls180.v:5790$1166 + attribute \src "ls180.v:3314.39-3314.158" + cell $and $and$ls180.v:3314$934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_last - connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:5790$1166_Y + connect \A $and$ls180.v:3314$932_Y + connect \B $eq$ls180.v:3314$933_Y + connect \Y $and$ls180.v:3314$934_Y end - attribute \src "ls180.v:5842.43-5842.152" - cell $and $and$ls180.v:5842$1171 + attribute \src "ls180.v:3316.50-3316.111" + cell $and $and$ls180.v:3316$935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B $or$ls180.v:5842$1170_Y - connect \Y $and$ls180.v:5842$1171_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3316$935_Y end - attribute \src "ls180.v:5843.41-5843.116" - cell $and $and$ls180.v:5843$1172 + attribute \src "ls180.v:3316.49-3316.165" + cell $and $and$ls180.v:3316$937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_readable - connect \B \main_sdmem2block_fifo_syncfifo_re - connect \Y $and$ls180.v:5843$1172_Y + connect \A $and$ls180.v:3316$935_Y + connect \B $eq$ls180.v:3316$936_Y + connect \Y $and$ls180.v:3316$937_Y end - attribute \src "ls180.v:5875.9-5875.76" - cell $and $and$ls180.v:5875$1176 + attribute \src "ls180.v:3317.50-3317.114" + cell $and $and$ls180.v:3317$939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_cyc - connect \B \builder_libresocsim_wishbone_stb - connect \Y $and$ls180.v:5875$1176_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3317$938_Y + connect \Y $and$ls180.v:3317$939_Y end - attribute \src "ls180.v:5878.44-5878.120" - cell $and $and$ls180.v:5878$1178 + attribute \src "ls180.v:3317.49-3317.168" + cell $and $and$ls180.v:3317$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_we - connect \B $ne$ls180.v:5878$1177_Y - connect \Y $and$ls180.v:5878$1178_Y + connect \A $and$ls180.v:3317$939_Y + connect \B $eq$ls180.v:3317$940_Y + connect \Y $and$ls180.v:3317$941_Y end - attribute \src "ls180.v:5898.46-5898.90" - cell $and $and$ls180.v:5898$1180 + attribute \src "ls180.v:3319.43-3319.104" + cell $and $and$ls180.v:3319$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5898$1179_Y - connect \Y $and$ls180.v:5898$1180_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3319$942_Y end - attribute \src "ls180.v:5899.46-5899.90" - cell $and $and$ls180.v:5899$1182 + attribute \src "ls180.v:3319.42-3319.159" + cell $and $and$ls180.v:3319$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5899$1181_Y - connect \Y $and$ls180.v:5899$1182_Y + connect \A $and$ls180.v:3319$942_Y + connect \B $eq$ls180.v:3319$943_Y + connect \Y $and$ls180.v:3319$944_Y end - attribute \src "ls180.v:5900.49-5900.93" - cell $and $and$ls180.v:5900$1184 + attribute \src "ls180.v:3320.43-3320.107" + cell $and $and$ls180.v:3320$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5900$1183_Y - connect \Y $and$ls180.v:5900$1184_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3320$945_Y + connect \Y $and$ls180.v:3320$946_Y end - attribute \src "ls180.v:5901.35-5901.79" - cell $and $and$ls180.v:5901$1186 + attribute \src "ls180.v:3320.42-3320.162" + cell $and $and$ls180.v:3320$948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5901$1185_Y - connect \Y $and$ls180.v:5901$1186_Y + connect \A $and$ls180.v:3320$946_Y + connect \B $eq$ls180.v:3320$947_Y + connect \Y $and$ls180.v:3320$948_Y end - attribute \src "ls180.v:5902.35-5902.79" - cell $and $and$ls180.v:5902$1188 + attribute \src "ls180.v:3322.43-3322.104" + cell $and $and$ls180.v:3322$949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5902$1187_Y - connect \Y $and$ls180.v:5902$1188_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3322$949_Y end - attribute \src "ls180.v:5903.46-5903.90" - cell $and $and$ls180.v:5903$1190 + attribute \src "ls180.v:3322.42-3322.159" + cell $and $and$ls180.v:3322$951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5903$1189_Y - connect \Y $and$ls180.v:5903$1190_Y + connect \A $and$ls180.v:3322$949_Y + connect \B $eq$ls180.v:3322$950_Y + connect \Y $and$ls180.v:3322$951_Y end - attribute \src "ls180.v:5904.46-5904.90" - cell $and $and$ls180.v:5904$1192 + attribute \src "ls180.v:3323.43-3323.107" + cell $and $and$ls180.v:3323$953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5904$1191_Y - connect \Y $and$ls180.v:5904$1192_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3323$952_Y + connect \Y $and$ls180.v:3323$953_Y end - attribute \src "ls180.v:5905.49-5905.93" - cell $and $and$ls180.v:5905$1194 + attribute \src "ls180.v:3323.42-3323.162" + cell $and $and$ls180.v:3323$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5905$1193_Y - connect \Y $and$ls180.v:5905$1194_Y + connect \A $and$ls180.v:3323$953_Y + connect \B $eq$ls180.v:3323$954_Y + connect \Y $and$ls180.v:3323$955_Y end - attribute \src "ls180.v:5906.35-5906.79" - cell $and $and$ls180.v:5906$1196 + attribute \src "ls180.v:3325.43-3325.104" + cell $and $and$ls180.v:3325$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5906$1195_Y - connect \Y $and$ls180.v:5906$1196_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3325$956_Y end - attribute \src "ls180.v:5907.35-5907.79" - cell $and $and$ls180.v:5907$1198 + attribute \src "ls180.v:3325.42-3325.159" + cell $and $and$ls180.v:3325$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5907$1197_Y - connect \Y $and$ls180.v:5907$1198_Y + connect \A $and$ls180.v:3325$956_Y + connect \B $eq$ls180.v:3325$957_Y + connect \Y $and$ls180.v:3325$958_Y end - attribute \src "ls180.v:6016.40-6016.81" - cell $and $and$ls180.v:6016$1213 + attribute \src "ls180.v:3326.43-3326.107" + cell $and $and$ls180.v:3326$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [0] - connect \Y $and$ls180.v:6016$1213_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3326$959_Y + connect \Y $and$ls180.v:3326$960_Y end - attribute \src "ls180.v:6017.39-6017.80" - cell $and $and$ls180.v:6017$1214 + attribute \src "ls180.v:3326.42-3326.162" + cell $and $and$ls180.v:3326$962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [1] - connect \Y $and$ls180.v:6017$1214_Y + connect \A $and$ls180.v:3326$960_Y + connect \B $eq$ls180.v:3326$961_Y + connect \Y $and$ls180.v:3326$962_Y end - attribute \src "ls180.v:6018.39-6018.80" - cell $and $and$ls180.v:6018$1215 + attribute \src "ls180.v:3328.43-3328.104" + cell $and $and$ls180.v:3328$963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [2] - connect \Y $and$ls180.v:6018$1215_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3328$963_Y end - attribute \src "ls180.v:6019.39-6019.80" - cell $and $and$ls180.v:6019$1216 + attribute \src "ls180.v:3328.42-3328.159" + cell $and $and$ls180.v:3328$965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [3] - connect \Y $and$ls180.v:6019$1216_Y + connect \A $and$ls180.v:3328$963_Y + connect \B $eq$ls180.v:3328$964_Y + connect \Y $and$ls180.v:3328$965_Y end - attribute \src "ls180.v:6020.39-6020.80" - cell $and $and$ls180.v:6020$1217 + attribute \src "ls180.v:3329.43-3329.107" + cell $and $and$ls180.v:3329$967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [4] - connect \Y $and$ls180.v:6020$1217_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3329$966_Y + connect \Y $and$ls180.v:3329$967_Y end - attribute \src "ls180.v:6021.51-6021.92" - cell $and $and$ls180.v:6021$1218 + attribute \src "ls180.v:3329.42-3329.162" + cell $and $and$ls180.v:3329$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [5] - connect \Y $and$ls180.v:6021$1218_Y + connect \A $and$ls180.v:3329$967_Y + connect \B $eq$ls180.v:3329$968_Y + connect \Y $and$ls180.v:3329$969_Y end - attribute \src "ls180.v:6022.51-6022.92" - cell $and $and$ls180.v:6022$1219 + attribute \src "ls180.v:3331.47-3331.108" + cell $and $and$ls180.v:3331$970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [6] - connect \Y $and$ls180.v:6022$1219_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3331$970_Y end - attribute \src "ls180.v:6023.52-6023.93" - cell $and $and$ls180.v:6023$1220 + attribute \src "ls180.v:3331.46-3331.163" + cell $and $and$ls180.v:3331$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [7] - connect \Y $and$ls180.v:6023$1220_Y + connect \A $and$ls180.v:3331$970_Y + connect \B $eq$ls180.v:3331$971_Y + connect \Y $and$ls180.v:3331$972_Y end - attribute \src "ls180.v:6024.52-6024.93" - cell $and $and$ls180.v:6024$1221 + attribute \src "ls180.v:3332.47-3332.111" + cell $and $and$ls180.v:3332$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [8] - connect \Y $and$ls180.v:6024$1221_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3332$973_Y + connect \Y $and$ls180.v:3332$974_Y end - attribute \src "ls180.v:6025.52-6025.93" - cell $and $and$ls180.v:6025$1222 + attribute \src "ls180.v:3332.46-3332.166" + cell $and $and$ls180.v:3332$976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [9] - connect \Y $and$ls180.v:6025$1222_Y + connect \A $and$ls180.v:3332$974_Y + connect \B $eq$ls180.v:3332$975_Y + connect \Y $and$ls180.v:3332$976_Y end - attribute \src "ls180.v:6026.52-6026.94" - cell $and $and$ls180.v:6026$1223 + attribute \src "ls180.v:3334.48-3334.109" + cell $and $and$ls180.v:3334$977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [10] - connect \Y $and$ls180.v:6026$1223_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3334$977_Y end - attribute \src "ls180.v:6027.54-6027.96" - cell $and $and$ls180.v:6027$1224 + attribute \src "ls180.v:3334.47-3334.164" + cell $and $and$ls180.v:3334$979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [11] - connect \Y $and$ls180.v:6027$1224_Y + connect \A $and$ls180.v:3334$977_Y + connect \B $eq$ls180.v:3334$978_Y + connect \Y $and$ls180.v:3334$979_Y end - attribute \src "ls180.v:6028.55-6028.97" - cell $and $and$ls180.v:6028$1225 + attribute \src "ls180.v:3335.48-3335.112" + cell $and $and$ls180.v:3335$981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [12] - connect \Y $and$ls180.v:6028$1225_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3335$980_Y + connect \Y $and$ls180.v:3335$981_Y end - attribute \src "ls180.v:6030.25-6030.64" - cell $and $and$ls180.v:6030$1238 + attribute \src "ls180.v:3335.47-3335.167" + cell $and $and$ls180.v:3335$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_stb - connect \B \builder_shared_cyc - connect \Y $and$ls180.v:6030$1238_Y + connect \A $and$ls180.v:3335$981_Y + connect \B $eq$ls180.v:3335$982_Y + connect \Y $and$ls180.v:3335$983_Y end - attribute \src "ls180.v:6030.24-6030.89" - cell $and $and$ls180.v:6030$1240 + attribute \src "ls180.v:3337.47-3337.108" + cell $and $and$ls180.v:3337$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6030$1238_Y - connect \B $not$ls180.v:6030$1239_Y - connect \Y $and$ls180.v:6030$1240_Y - end - attribute \src "ls180.v:6036.39-6036.100" - cell $and $and$ls180.v:6036$1254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } - connect \B \main_libresocsim_ram_bus_dat_r - connect \Y $and$ls180.v:6036$1254_Y - end - attribute \src "ls180.v:6036.105-6036.165" - cell $and $and$ls180.v:6036$1255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } - connect \B \main_interface0_ram_bus_dat_r - connect \Y $and$ls180.v:6036$1255_Y - end - attribute \src "ls180.v:6036.171-6036.231" - cell $and $and$ls180.v:6036$1257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } - connect \B \main_interface1_ram_bus_dat_r - connect \Y $and$ls180.v:6036$1257_Y - end - attribute \src "ls180.v:6036.237-6036.297" - cell $and $and$ls180.v:6036$1259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } - connect \B \main_interface2_ram_bus_dat_r - connect \Y $and$ls180.v:6036$1259_Y - end - attribute \src "ls180.v:6036.303-6036.363" - cell $and $and$ls180.v:6036$1261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } - connect \B \main_interface3_ram_bus_dat_r - connect \Y $and$ls180.v:6036$1261_Y - end - attribute \src "ls180.v:6036.369-6036.441" - cell $and $and$ls180.v:6036$1263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] } - connect \B \main_interface0_converted_interface_dat_r - connect \Y $and$ls180.v:6036$1263_Y - end - attribute \src "ls180.v:6036.447-6036.519" - cell $and $and$ls180.v:6036$1265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] } - connect \B \main_interface1_converted_interface_dat_r - connect \Y $and$ls180.v:6036$1265_Y - end - attribute \src "ls180.v:6036.525-6036.598" - cell $and $and$ls180.v:6036$1267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] } - connect \B \main_libresocsim_libresoc_interface0_dat_r - connect \Y $and$ls180.v:6036$1267_Y - end - attribute \src "ls180.v:6036.604-6036.677" - cell $and $and$ls180.v:6036$1269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] } - connect \B \main_libresocsim_libresoc_interface1_dat_r - connect \Y $and$ls180.v:6036$1269_Y - end - attribute \src "ls180.v:6036.683-6036.756" - cell $and $and$ls180.v:6036$1271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] } - connect \B \main_libresocsim_libresoc_interface2_dat_r - connect \Y $and$ls180.v:6036$1271_Y - end - attribute \src "ls180.v:6036.762-6036.836" - cell $and $and$ls180.v:6036$1273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] } - connect \B \main_libresocsim_libresoc_interface3_dat_r - connect \Y $and$ls180.v:6036$1273_Y - end - attribute \src "ls180.v:6036.842-6036.918" - cell $and $and$ls180.v:6036$1275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] } - connect \B \main_socbushandler_converted_interface_dat_r - connect \Y $and$ls180.v:6036$1275_Y - end - attribute \src "ls180.v:6036.924-6036.1001" - cell $and $and$ls180.v:6036$1277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] } - connect \B \builder_libresocsim_converted_interface_dat_r - connect \Y $and$ls180.v:6036$1277_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3337$984_Y end - attribute \src "ls180.v:6046.39-6046.92" - cell $and $and$ls180.v:6046$1281 + attribute \src "ls180.v:3337.46-3337.163" + cell $and $and$ls180.v:3337$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6046$1281_Y + connect \A $and$ls180.v:3337$984_Y + connect \B $eq$ls180.v:3337$985_Y + connect \Y $and$ls180.v:3337$986_Y end - attribute \src "ls180.v:6046.38-6046.142" - cell $and $and$ls180.v:6046$1283 + attribute \src "ls180.v:3338.47-3338.111" + cell $and $and$ls180.v:3338$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6046$1281_Y - connect \B $eq$ls180.v:6046$1282_Y - connect \Y $and$ls180.v:6046$1283_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3338$987_Y + connect \Y $and$ls180.v:3338$988_Y end - attribute \src "ls180.v:6047.39-6047.95" - cell $and $and$ls180.v:6047$1285 + attribute \src "ls180.v:3338.46-3338.166" + cell $and $and$ls180.v:3338$990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6047$1284_Y - connect \Y $and$ls180.v:6047$1285_Y + connect \A $and$ls180.v:3338$988_Y + connect \B $eq$ls180.v:3338$989_Y + connect \Y $and$ls180.v:3338$990_Y end - attribute \src "ls180.v:6047.38-6047.145" - cell $and $and$ls180.v:6047$1287 + attribute \src "ls180.v:3357.20-3357.81" + cell $and $and$ls180.v:3357$992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6047$1285_Y - connect \B $eq$ls180.v:6047$1286_Y - connect \Y $and$ls180.v:6047$1287_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3357$992_Y end - attribute \src "ls180.v:6049.41-6049.94" - cell $and $and$ls180.v:6049$1288 + attribute \src "ls180.v:3357.19-3357.135" + cell $and $and$ls180.v:3357$994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6049$1288_Y + connect \A $and$ls180.v:3357$992_Y + connect \B $eq$ls180.v:3357$993_Y + connect \Y $and$ls180.v:3357$994_Y end - attribute \src "ls180.v:6049.40-6049.144" - cell $and $and$ls180.v:6049$1290 + attribute \src "ls180.v:3358.20-3358.84" + cell $and $and$ls180.v:3358$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6049$1288_Y - connect \B $eq$ls180.v:6049$1289_Y - connect \Y $and$ls180.v:6049$1290_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3358$995_Y + connect \Y $and$ls180.v:3358$996_Y end - attribute \src "ls180.v:6050.41-6050.97" - cell $and $and$ls180.v:6050$1292 + attribute \src "ls180.v:3358.19-3358.138" + cell $and $and$ls180.v:3358$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6050$1291_Y - connect \Y $and$ls180.v:6050$1292_Y + connect \A $and$ls180.v:3358$996_Y + connect \B $eq$ls180.v:3358$997_Y + connect \Y $and$ls180.v:3358$998_Y end - attribute \src "ls180.v:6050.40-6050.147" - cell $and $and$ls180.v:6050$1294 + attribute \src "ls180.v:3360.42-3360.158" + cell $and $and$ls180.v:3360$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6050$1292_Y - connect \B $eq$ls180.v:6050$1293_Y - connect \Y $and$ls180.v:6050$1294_Y + connect \A $and$ls180.v:3360$999_Y + connect \B $eq$ls180.v:3360$1000_Y + connect \Y $and$ls180.v:3360$1001_Y end - attribute \src "ls180.v:6052.41-6052.94" - cell $and $and$ls180.v:6052$1295 + attribute \src "ls180.v:3360.43-3360.104" + cell $and $and$ls180.v:3360$999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6052$1295_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3360$999_Y end - attribute \src "ls180.v:6052.40-6052.144" - cell $and $and$ls180.v:6052$1297 + attribute \src "ls180.v:3361.43-3361.107" + cell $and $and$ls180.v:3361$1003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6052$1295_Y - connect \B $eq$ls180.v:6052$1296_Y - connect \Y $and$ls180.v:6052$1297_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3361$1002_Y + connect \Y $and$ls180.v:3361$1003_Y end - attribute \src "ls180.v:6053.41-6053.97" - cell $and $and$ls180.v:6053$1299 + attribute \src "ls180.v:3361.42-3361.161" + cell $and $and$ls180.v:3361$1005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6053$1298_Y - connect \Y $and$ls180.v:6053$1299_Y + connect \A $and$ls180.v:3361$1003_Y + connect \B $eq$ls180.v:3361$1004_Y + connect \Y $and$ls180.v:3361$1005_Y end - attribute \src "ls180.v:6053.40-6053.147" - cell $and $and$ls180.v:6053$1301 + attribute \src "ls180.v:3363.44-3363.105" + cell $and $and$ls180.v:3363$1006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6053$1299_Y - connect \B $eq$ls180.v:6053$1300_Y - connect \Y $and$ls180.v:6053$1301_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3363$1006_Y end - attribute \src "ls180.v:6055.41-6055.94" - cell $and $and$ls180.v:6055$1302 + attribute \src "ls180.v:3363.43-3363.159" + cell $and $and$ls180.v:3363$1008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6055$1302_Y + connect \A $and$ls180.v:3363$1006_Y + connect \B $eq$ls180.v:3363$1007_Y + connect \Y $and$ls180.v:3363$1008_Y end - attribute \src "ls180.v:6055.40-6055.144" - cell $and $and$ls180.v:6055$1304 + attribute \src "ls180.v:3364.44-3364.108" + cell $and $and$ls180.v:3364$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6055$1302_Y - connect \B $eq$ls180.v:6055$1303_Y - connect \Y $and$ls180.v:6055$1304_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3364$1009_Y + connect \Y $and$ls180.v:3364$1010_Y end - attribute \src "ls180.v:6056.41-6056.97" - cell $and $and$ls180.v:6056$1306 + attribute \src "ls180.v:3364.43-3364.162" + cell $and $and$ls180.v:3364$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6056$1305_Y - connect \Y $and$ls180.v:6056$1306_Y + connect \A $and$ls180.v:3364$1010_Y + connect \B $eq$ls180.v:3364$1011_Y + connect \Y $and$ls180.v:3364$1012_Y end - attribute \src "ls180.v:6056.40-6056.147" - cell $and $and$ls180.v:6056$1308 + attribute \src "ls180.v:3366.35-3366.96" + cell $and $and$ls180.v:3366$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6056$1306_Y - connect \B $eq$ls180.v:6056$1307_Y - connect \Y $and$ls180.v:6056$1308_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3366$1013_Y end - attribute \src "ls180.v:6058.41-6058.94" - cell $and $and$ls180.v:6058$1309 + attribute \src "ls180.v:3366.34-3366.150" + cell $and $and$ls180.v:3366$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6058$1309_Y + connect \A $and$ls180.v:3366$1013_Y + connect \B $eq$ls180.v:3366$1014_Y + connect \Y $and$ls180.v:3366$1015_Y end - attribute \src "ls180.v:6058.40-6058.144" - cell $and $and$ls180.v:6058$1311 + attribute \src "ls180.v:3367.35-3367.99" + cell $and $and$ls180.v:3367$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6058$1309_Y - connect \B $eq$ls180.v:6058$1310_Y - connect \Y $and$ls180.v:6058$1311_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3367$1016_Y + connect \Y $and$ls180.v:3367$1017_Y end - attribute \src "ls180.v:6059.41-6059.97" - cell $and $and$ls180.v:6059$1313 + attribute \src "ls180.v:3367.34-3367.153" + cell $and $and$ls180.v:3367$1019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6059$1312_Y - connect \Y $and$ls180.v:6059$1313_Y + connect \A $and$ls180.v:3367$1017_Y + connect \B $eq$ls180.v:3367$1018_Y + connect \Y $and$ls180.v:3367$1019_Y end - attribute \src "ls180.v:6059.40-6059.147" - cell $and $and$ls180.v:6059$1315 + attribute \src "ls180.v:3369.36-3369.97" + cell $and $and$ls180.v:3369$1020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6059$1313_Y - connect \B $eq$ls180.v:6059$1314_Y - connect \Y $and$ls180.v:6059$1315_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3369$1020_Y end - attribute \src "ls180.v:6061.44-6061.97" - cell $and $and$ls180.v:6061$1316 + attribute \src "ls180.v:3369.35-3369.151" + cell $and $and$ls180.v:3369$1022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6061$1316_Y + connect \A $and$ls180.v:3369$1020_Y + connect \B $eq$ls180.v:3369$1021_Y + connect \Y $and$ls180.v:3369$1022_Y end - attribute \src "ls180.v:6061.43-6061.147" - cell $and $and$ls180.v:6061$1318 + attribute \src "ls180.v:3370.36-3370.100" + cell $and $and$ls180.v:3370$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6061$1316_Y - connect \B $eq$ls180.v:6061$1317_Y - connect \Y $and$ls180.v:6061$1318_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3370$1023_Y + connect \Y $and$ls180.v:3370$1024_Y end - attribute \src "ls180.v:6062.44-6062.100" - cell $and $and$ls180.v:6062$1320 + attribute \src "ls180.v:3370.35-3370.154" + cell $and $and$ls180.v:3370$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6062$1319_Y - connect \Y $and$ls180.v:6062$1320_Y + connect \A $and$ls180.v:3370$1024_Y + connect \B $eq$ls180.v:3370$1025_Y + connect \Y $and$ls180.v:3370$1026_Y end - attribute \src "ls180.v:6062.43-6062.150" - cell $and $and$ls180.v:6062$1322 + attribute \src "ls180.v:3372.47-3372.108" + cell $and $and$ls180.v:3372$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6062$1320_Y - connect \B $eq$ls180.v:6062$1321_Y - connect \Y $and$ls180.v:6062$1322_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3372$1027_Y end - attribute \src "ls180.v:6064.44-6064.97" - cell $and $and$ls180.v:6064$1323 + attribute \src "ls180.v:3372.46-3372.162" + cell $and $and$ls180.v:3372$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6064$1323_Y + connect \A $and$ls180.v:3372$1027_Y + connect \B $eq$ls180.v:3372$1028_Y + connect \Y $and$ls180.v:3372$1029_Y end - attribute \src "ls180.v:6064.43-6064.147" - cell $and $and$ls180.v:6064$1325 + attribute \src "ls180.v:3373.47-3373.111" + cell $and $and$ls180.v:3373$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6064$1323_Y - connect \B $eq$ls180.v:6064$1324_Y - connect \Y $and$ls180.v:6064$1325_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3373$1030_Y + connect \Y $and$ls180.v:3373$1031_Y end - attribute \src "ls180.v:6065.44-6065.100" - cell $and $and$ls180.v:6065$1327 + attribute \src "ls180.v:3373.46-3373.165" + cell $and $and$ls180.v:3373$1033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6065$1326_Y - connect \Y $and$ls180.v:6065$1327_Y + connect \A $and$ls180.v:3373$1031_Y + connect \B $eq$ls180.v:3373$1032_Y + connect \Y $and$ls180.v:3373$1033_Y end - attribute \src "ls180.v:6065.43-6065.150" - cell $and $and$ls180.v:6065$1329 + attribute \src "ls180.v:3375.44-3375.105" + cell $and $and$ls180.v:3375$1034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6065$1327_Y - connect \B $eq$ls180.v:6065$1328_Y - connect \Y $and$ls180.v:6065$1329_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3375$1034_Y end - attribute \src "ls180.v:6067.44-6067.97" - cell $and $and$ls180.v:6067$1330 + attribute \src "ls180.v:3375.43-3375.159" + cell $and $and$ls180.v:3375$1036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6067$1330_Y + connect \A $and$ls180.v:3375$1034_Y + connect \B $eq$ls180.v:3375$1035_Y + connect \Y $and$ls180.v:3375$1036_Y end - attribute \src "ls180.v:6067.43-6067.147" - cell $and $and$ls180.v:6067$1332 + attribute \src "ls180.v:3376.44-3376.108" + cell $and $and$ls180.v:3376$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6067$1330_Y - connect \B $eq$ls180.v:6067$1331_Y - connect \Y $and$ls180.v:6067$1332_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3376$1037_Y + connect \Y $and$ls180.v:3376$1038_Y end - attribute \src "ls180.v:6068.44-6068.100" - cell $and $and$ls180.v:6068$1334 + attribute \src "ls180.v:3376.43-3376.162" + cell $and $and$ls180.v:3376$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6068$1333_Y - connect \Y $and$ls180.v:6068$1334_Y + connect \A $and$ls180.v:3376$1038_Y + connect \B $eq$ls180.v:3376$1039_Y + connect \Y $and$ls180.v:3376$1040_Y end - attribute \src "ls180.v:6068.43-6068.150" - cell $and $and$ls180.v:6068$1336 + attribute \src "ls180.v:3378.43-3378.104" + cell $and $and$ls180.v:3378$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6068$1334_Y - connect \B $eq$ls180.v:6068$1335_Y - connect \Y $and$ls180.v:6068$1336_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3378$1041_Y end - attribute \src "ls180.v:6070.44-6070.97" - cell $and $and$ls180.v:6070$1337 + attribute \src "ls180.v:3378.42-3378.158" + cell $and $and$ls180.v:3378$1043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6070$1337_Y + connect \A $and$ls180.v:3378$1041_Y + connect \B $eq$ls180.v:3378$1042_Y + connect \Y $and$ls180.v:3378$1043_Y end - attribute \src "ls180.v:6070.43-6070.147" - cell $and $and$ls180.v:6070$1339 + attribute \src "ls180.v:3379.43-3379.107" + cell $and $and$ls180.v:3379$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6070$1337_Y - connect \B $eq$ls180.v:6070$1338_Y - connect \Y $and$ls180.v:6070$1339_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3379$1044_Y + connect \Y $and$ls180.v:3379$1045_Y end - attribute \src "ls180.v:6071.44-6071.100" - cell $and $and$ls180.v:6071$1341 + attribute \src "ls180.v:3379.42-3379.161" + cell $and $and$ls180.v:3379$1047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6071$1340_Y - connect \Y $and$ls180.v:6071$1341_Y + connect \A $and$ls180.v:3379$1045_Y + connect \B $eq$ls180.v:3379$1046_Y + connect \Y $and$ls180.v:3379$1047_Y end - attribute \src "ls180.v:6071.43-6071.150" - cell $and $and$ls180.v:6071$1343 + attribute \src "ls180.v:3391.49-3391.110" + cell $and $and$ls180.v:3391$1049 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6071$1341_Y - connect \B $eq$ls180.v:6071$1342_Y - connect \Y $and$ls180.v:6071$1343_Y + connect \A \libresocsim_csrbank7_sel + connect \B \libresocsim_interface7_bank_bus_we + connect \Y $and$ls180.v:3391$1049_Y end - attribute \src "ls180.v:6084.36-6084.89" - cell $and $and$ls180.v:6084$1345 + attribute \src "ls180.v:3391.48-3391.164" + cell $and $and$ls180.v:3391$1051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6084$1345_Y + connect \A $and$ls180.v:3391$1049_Y + connect \B $eq$ls180.v:3391$1050_Y + connect \Y $and$ls180.v:3391$1051_Y end - attribute \src "ls180.v:6084.35-6084.139" - cell $and $and$ls180.v:6084$1347 + attribute \src "ls180.v:3392.49-3392.113" + cell $and $and$ls180.v:3392$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6084$1345_Y - connect \B $eq$ls180.v:6084$1346_Y - connect \Y $and$ls180.v:6084$1347_Y + connect \A \libresocsim_csrbank7_sel + connect \B $not$ls180.v:3392$1052_Y + connect \Y $and$ls180.v:3392$1053_Y end - attribute \src "ls180.v:6085.36-6085.92" - cell $and $and$ls180.v:6085$1349 + attribute \src "ls180.v:3392.48-3392.167" + cell $and $and$ls180.v:3392$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6085$1348_Y - connect \Y $and$ls180.v:6085$1349_Y + connect \A $and$ls180.v:3392$1053_Y + connect \B $eq$ls180.v:3392$1054_Y + connect \Y $and$ls180.v:3392$1055_Y end - attribute \src "ls180.v:6085.35-6085.142" - cell $and $and$ls180.v:6085$1351 + attribute \src "ls180.v:3394.49-3394.110" + cell $and $and$ls180.v:3394$1056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6085$1349_Y - connect \B $eq$ls180.v:6085$1350_Y - connect \Y $and$ls180.v:6085$1351_Y + connect \A \libresocsim_csrbank7_sel + connect \B \libresocsim_interface7_bank_bus_we + connect \Y $and$ls180.v:3394$1056_Y end - attribute \src "ls180.v:6087.36-6087.89" - cell $and $and$ls180.v:6087$1352 + attribute \src "ls180.v:3394.48-3394.164" + cell $and $and$ls180.v:3394$1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6087$1352_Y + connect \A $and$ls180.v:3394$1056_Y + connect \B $eq$ls180.v:3394$1057_Y + connect \Y $and$ls180.v:3394$1058_Y end - attribute \src "ls180.v:6087.35-6087.139" - cell $and $and$ls180.v:6087$1354 + attribute \src "ls180.v:3395.49-3395.113" + cell $and $and$ls180.v:3395$1060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6087$1352_Y - connect \B $eq$ls180.v:6087$1353_Y - connect \Y $and$ls180.v:6087$1354_Y + connect \A \libresocsim_csrbank7_sel + connect \B $not$ls180.v:3395$1059_Y + connect \Y $and$ls180.v:3395$1060_Y end - attribute \src "ls180.v:6088.36-6088.92" - cell $and $and$ls180.v:6088$1356 + attribute \src "ls180.v:3395.48-3395.167" + cell $and $and$ls180.v:3395$1062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6088$1355_Y - connect \Y $and$ls180.v:6088$1356_Y + connect \A $and$ls180.v:3395$1060_Y + connect \B $eq$ls180.v:3395$1061_Y + connect \Y $and$ls180.v:3395$1062_Y end - attribute \src "ls180.v:6088.35-6088.142" - cell $and $and$ls180.v:6088$1358 + attribute \src "ls180.v:3397.49-3397.110" + cell $and $and$ls180.v:3397$1063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6088$1356_Y - connect \B $eq$ls180.v:6088$1357_Y - connect \Y $and$ls180.v:6088$1358_Y + connect \A \libresocsim_csrbank7_sel + connect \B \libresocsim_interface7_bank_bus_we + connect \Y $and$ls180.v:3397$1063_Y end - attribute \src "ls180.v:6090.36-6090.89" - cell $and $and$ls180.v:6090$1359 + attribute \src "ls180.v:3397.48-3397.164" + cell $and $and$ls180.v:3397$1065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6090$1359_Y + connect \A $and$ls180.v:3397$1063_Y + connect \B $eq$ls180.v:3397$1064_Y + connect \Y $and$ls180.v:3397$1065_Y end - attribute \src "ls180.v:6090.35-6090.139" - cell $and $and$ls180.v:6090$1361 + attribute \src "ls180.v:3398.49-3398.113" + cell $and $and$ls180.v:3398$1067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6090$1359_Y - connect \B $eq$ls180.v:6090$1360_Y - connect \Y $and$ls180.v:6090$1361_Y + connect \A \libresocsim_csrbank7_sel + connect \B $not$ls180.v:3398$1066_Y + connect \Y $and$ls180.v:3398$1067_Y end - attribute \src "ls180.v:6091.36-6091.92" - cell $and $and$ls180.v:6091$1363 + attribute \src "ls180.v:3398.48-3398.167" + cell $and $and$ls180.v:3398$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6091$1362_Y - connect \Y $and$ls180.v:6091$1363_Y + connect \A $and$ls180.v:3398$1067_Y + connect \B $eq$ls180.v:3398$1068_Y + connect \Y $and$ls180.v:3398$1069_Y end - attribute \src "ls180.v:6091.35-6091.142" - cell $and $and$ls180.v:6091$1365 + attribute \src "ls180.v:3400.49-3400.110" + cell $and $and$ls180.v:3400$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6091$1363_Y - connect \B $eq$ls180.v:6091$1364_Y - connect \Y $and$ls180.v:6091$1365_Y + connect \A \libresocsim_csrbank7_sel + connect \B \libresocsim_interface7_bank_bus_we + connect \Y $and$ls180.v:3400$1070_Y end - attribute \src "ls180.v:6093.36-6093.89" - cell $and $and$ls180.v:6093$1366 + attribute \src "ls180.v:3400.48-3400.164" + cell $and $and$ls180.v:3400$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6093$1366_Y + connect \A $and$ls180.v:3400$1070_Y + connect \B $eq$ls180.v:3400$1071_Y + connect \Y $and$ls180.v:3400$1072_Y end - attribute \src "ls180.v:6093.35-6093.139" - cell $and $and$ls180.v:6093$1368 + attribute \src "ls180.v:3401.49-3401.113" + cell $and $and$ls180.v:3401$1074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6093$1366_Y - connect \B $eq$ls180.v:6093$1367_Y - connect \Y $and$ls180.v:6093$1368_Y + connect \A \libresocsim_csrbank7_sel + connect \B $not$ls180.v:3401$1073_Y + connect \Y $and$ls180.v:3401$1074_Y end - attribute \src "ls180.v:6094.36-6094.92" - cell $and $and$ls180.v:6094$1370 + attribute \src "ls180.v:3401.48-3401.167" + cell $and $and$ls180.v:3401$1076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6094$1369_Y - connect \Y $and$ls180.v:6094$1370_Y + connect \A $and$ls180.v:3401$1074_Y + connect \B $eq$ls180.v:3401$1075_Y + connect \Y $and$ls180.v:3401$1076_Y end - attribute \src "ls180.v:6094.35-6094.142" - cell $and $and$ls180.v:6094$1372 + attribute \src "ls180.v:3761.96-3761.165" + cell $and $and$ls180.v:3761$1107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6094$1370_Y - connect \B $eq$ls180.v:6094$1371_Y - connect \Y $and$ls180.v:6094$1372_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:3761$1106_Y + connect \Y $and$ls180.v:3761$1107_Y end - attribute \src "ls180.v:6096.37-6096.90" - cell $and $and$ls180.v:6096$1373 + attribute \src "ls180.v:3761.171-3761.240" + cell $and $and$ls180.v:3761$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6096$1373_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:3761$1109_Y + connect \Y $and$ls180.v:3761$1110_Y end - attribute \src "ls180.v:6096.36-6096.140" - cell $and $and$ls180.v:6096$1375 + attribute \src "ls180.v:3761.246-3761.315" + cell $and $and$ls180.v:3761$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6096$1373_Y - connect \B $eq$ls180.v:6096$1374_Y - connect \Y $and$ls180.v:6096$1375_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:3761$1112_Y + connect \Y $and$ls180.v:3761$1113_Y end - attribute \src "ls180.v:6097.37-6097.93" - cell $and $and$ls180.v:6097$1377 + attribute \src "ls180.v:3761.27-3761.318" + cell $and $and$ls180.v:3761$1116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6097$1376_Y - connect \Y $and$ls180.v:6097$1377_Y + connect \A $eq$ls180.v:3761$1105_Y + connect \B $not$ls180.v:3761$1115_Y + connect \Y $and$ls180.v:3761$1116_Y end - attribute \src "ls180.v:6097.36-6097.143" - cell $and $and$ls180.v:6097$1379 + attribute \src "ls180.v:3761.26-3761.336" + cell $and $and$ls180.v:3761$1117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6097$1377_Y - connect \B $eq$ls180.v:6097$1378_Y - connect \Y $and$ls180.v:6097$1379_Y + connect \A $and$ls180.v:3761$1116_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:3761$1117_Y end - attribute \src "ls180.v:6099.37-6099.90" - cell $and $and$ls180.v:6099$1380 + attribute \src "ls180.v:3785.96-3785.165" + cell $and $and$ls180.v:3785$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6099$1380_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:3785$1122_Y + connect \Y $and$ls180.v:3785$1123_Y end - attribute \src "ls180.v:6099.36-6099.140" - cell $and $and$ls180.v:6099$1382 + attribute \src "ls180.v:3785.171-3785.240" + cell $and $and$ls180.v:3785$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6099$1380_Y - connect \B $eq$ls180.v:6099$1381_Y - connect \Y $and$ls180.v:6099$1382_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:3785$1125_Y + connect \Y $and$ls180.v:3785$1126_Y end - attribute \src "ls180.v:6100.37-6100.93" - cell $and $and$ls180.v:6100$1384 + attribute \src "ls180.v:3785.246-3785.315" + cell $and $and$ls180.v:3785$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6100$1383_Y - connect \Y $and$ls180.v:6100$1384_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:3785$1128_Y + connect \Y $and$ls180.v:3785$1129_Y end - attribute \src "ls180.v:6100.36-6100.143" - cell $and $and$ls180.v:6100$1386 + attribute \src "ls180.v:3785.27-3785.318" + cell $and $and$ls180.v:3785$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6100$1384_Y - connect \B $eq$ls180.v:6100$1385_Y - connect \Y $and$ls180.v:6100$1386_Y + connect \A $eq$ls180.v:3785$1121_Y + connect \B $not$ls180.v:3785$1131_Y + connect \Y $and$ls180.v:3785$1132_Y end - attribute \src "ls180.v:6110.35-6110.88" - cell $and $and$ls180.v:6110$1388 + attribute \src "ls180.v:3785.26-3785.336" + cell $and $and$ls180.v:3785$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:6110$1388_Y + connect \A $and$ls180.v:3785$1132_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:3785$1133_Y end - attribute \src "ls180.v:6110.34-6110.136" - cell $and $and$ls180.v:6110$1390 + attribute \src "ls180.v:3809.96-3809.165" + cell $and $and$ls180.v:3809$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6110$1388_Y - connect \B $eq$ls180.v:6110$1389_Y - connect \Y $and$ls180.v:6110$1390_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:3809$1138_Y + connect \Y $and$ls180.v:3809$1139_Y end - attribute \src "ls180.v:6111.35-6111.91" - cell $and $and$ls180.v:6111$1392 + attribute \src "ls180.v:3809.171-3809.240" + cell $and $and$ls180.v:3809$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:6111$1391_Y - connect \Y $and$ls180.v:6111$1392_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:3809$1141_Y + connect \Y $and$ls180.v:3809$1142_Y end - attribute \src "ls180.v:6111.34-6111.139" - cell $and $and$ls180.v:6111$1394 + attribute \src "ls180.v:3809.246-3809.315" + cell $and $and$ls180.v:3809$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6111$1392_Y - connect \B $eq$ls180.v:6111$1393_Y - connect \Y $and$ls180.v:6111$1394_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:3809$1144_Y + connect \Y $and$ls180.v:3809$1145_Y end - attribute \src "ls180.v:6113.34-6113.87" - cell $and $and$ls180.v:6113$1395 + attribute \src "ls180.v:3809.27-3809.318" + cell $and $and$ls180.v:3809$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:6113$1395_Y + connect \A $eq$ls180.v:3809$1137_Y + connect \B $not$ls180.v:3809$1147_Y + connect \Y $and$ls180.v:3809$1148_Y end - attribute \src "ls180.v:6113.33-6113.135" - cell $and $and$ls180.v:6113$1397 + attribute \src "ls180.v:3809.26-3809.336" + cell $and $and$ls180.v:3809$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6113$1395_Y - connect \B $eq$ls180.v:6113$1396_Y - connect \Y $and$ls180.v:6113$1397_Y + connect \A $and$ls180.v:3809$1148_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:3809$1149_Y end - attribute \src "ls180.v:6114.34-6114.90" - cell $and $and$ls180.v:6114$1399 + attribute \src "ls180.v:3833.96-3833.165" + cell $and $and$ls180.v:3833$1155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:6114$1398_Y - connect \Y $and$ls180.v:6114$1399_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:3833$1154_Y + connect \Y $and$ls180.v:3833$1155_Y end - attribute \src "ls180.v:6114.33-6114.138" - cell $and $and$ls180.v:6114$1401 + attribute \src "ls180.v:3833.171-3833.240" + cell $and $and$ls180.v:3833$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6114$1399_Y - connect \B $eq$ls180.v:6114$1400_Y - connect \Y $and$ls180.v:6114$1401_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:3833$1157_Y + connect \Y $and$ls180.v:3833$1158_Y end - attribute \src "ls180.v:6124.40-6124.93" - cell $and $and$ls180.v:6124$1403 + attribute \src "ls180.v:3833.246-3833.315" + cell $and $and$ls180.v:3833$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6124$1403_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:3833$1160_Y + connect \Y $and$ls180.v:3833$1161_Y end - attribute \src "ls180.v:6124.39-6124.143" - cell $and $and$ls180.v:6124$1405 + attribute \src "ls180.v:3833.27-3833.318" + cell $and $and$ls180.v:3833$1164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6124$1403_Y - connect \B $eq$ls180.v:6124$1404_Y - connect \Y $and$ls180.v:6124$1405_Y + connect \A $eq$ls180.v:3833$1153_Y + connect \B $not$ls180.v:3833$1163_Y + connect \Y $and$ls180.v:3833$1164_Y end - attribute \src "ls180.v:6125.40-6125.96" - cell $and $and$ls180.v:6125$1407 + attribute \src "ls180.v:3833.26-3833.336" + cell $and $and$ls180.v:3833$1165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6125$1406_Y - connect \Y $and$ls180.v:6125$1407_Y + connect \A $and$ls180.v:3833$1164_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:3833$1165_Y end - attribute \src "ls180.v:6125.39-6125.146" - cell $and $and$ls180.v:6125$1409 + attribute \src "ls180.v:3990.22-3990.77" + cell $and $and$ls180.v:3990$1177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6125$1407_Y - connect \B $eq$ls180.v:6125$1408_Y - connect \Y $and$ls180.v:6125$1409_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3990$1177_Y end - attribute \src "ls180.v:6127.39-6127.92" - cell $and $and$ls180.v:6127$1410 + attribute \src "ls180.v:3990.21-3990.113" + cell $and $and$ls180.v:3990$1178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6127$1410_Y + connect \A $and$ls180.v:3990$1177_Y + connect \B \sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:3990$1178_Y end - attribute \src "ls180.v:6127.38-6127.142" - cell $and $and$ls180.v:6127$1412 + attribute \src "ls180.v:3993.22-3993.77" + cell $and $and$ls180.v:3993$1179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6127$1410_Y - connect \B $eq$ls180.v:6127$1411_Y - connect \Y $and$ls180.v:6127$1412_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3993$1179_Y end - attribute \src "ls180.v:6128.39-6128.95" - cell $and $and$ls180.v:6128$1414 + attribute \src "ls180.v:3993.21-3993.113" + cell $and $and$ls180.v:3993$1180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6128$1413_Y - connect \Y $and$ls180.v:6128$1414_Y + connect \A $and$ls180.v:3993$1179_Y + connect \B \sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:3993$1180_Y end - attribute \src "ls180.v:6128.38-6128.145" - cell $and $and$ls180.v:6128$1416 + attribute \src "ls180.v:3996.22-3996.55" + cell $and $and$ls180.v:3996$1181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6128$1414_Y - connect \B $eq$ls180.v:6128$1415_Y - connect \Y $and$ls180.v:6128$1416_Y + connect \A \sdram_cmd_valid + connect \B \sdram_cmd_ready + connect \Y $and$ls180.v:3996$1181_Y end - attribute \src "ls180.v:6130.39-6130.92" - cell $and $and$ls180.v:6130$1417 + attribute \src "ls180.v:3996.21-3996.80" + cell $and $and$ls180.v:3996$1182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6130$1417_Y + connect \A $and$ls180.v:3996$1181_Y + connect \B \sdram_cmd_payload_cas + connect \Y $and$ls180.v:3996$1182_Y end - attribute \src "ls180.v:6130.38-6130.142" - cell $and $and$ls180.v:6130$1419 + attribute \src "ls180.v:4007.22-4007.77" + cell $and $and$ls180.v:4007$1184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6130$1417_Y - connect \B $eq$ls180.v:6130$1418_Y - connect \Y $and$ls180.v:6130$1419_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4007$1184_Y end - attribute \src "ls180.v:6131.39-6131.95" - cell $and $and$ls180.v:6131$1421 + attribute \src "ls180.v:4007.21-4007.113" + cell $and $and$ls180.v:4007$1185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6131$1420_Y - connect \Y $and$ls180.v:6131$1421_Y + connect \A $and$ls180.v:4007$1184_Y + connect \B \sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:4007$1185_Y end - attribute \src "ls180.v:6131.38-6131.145" - cell $and $and$ls180.v:6131$1423 + attribute \src "ls180.v:4010.22-4010.77" + cell $and $and$ls180.v:4010$1186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6131$1421_Y - connect \B $eq$ls180.v:6131$1422_Y - connect \Y $and$ls180.v:6131$1423_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4010$1186_Y end - attribute \src "ls180.v:6133.39-6133.92" - cell $and $and$ls180.v:6133$1424 + attribute \src "ls180.v:4010.21-4010.113" + cell $and $and$ls180.v:4010$1187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6133$1424_Y + connect \A $and$ls180.v:4010$1186_Y + connect \B \sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:4010$1187_Y end - attribute \src "ls180.v:6133.38-6133.142" - cell $and $and$ls180.v:6133$1426 + attribute \src "ls180.v:4013.22-4013.55" + cell $and $and$ls180.v:4013$1188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6133$1424_Y - connect \B $eq$ls180.v:6133$1425_Y - connect \Y $and$ls180.v:6133$1426_Y + connect \A \sdram_cmd_valid + connect \B \sdram_cmd_ready + connect \Y $and$ls180.v:4013$1188_Y end - attribute \src "ls180.v:6134.39-6134.95" - cell $and $and$ls180.v:6134$1428 + attribute \src "ls180.v:4013.21-4013.80" + cell $and $and$ls180.v:4013$1189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6134$1427_Y - connect \Y $and$ls180.v:6134$1428_Y + connect \A $and$ls180.v:4013$1188_Y + connect \B \sdram_cmd_payload_ras + connect \Y $and$ls180.v:4013$1189_Y end - attribute \src "ls180.v:6134.38-6134.145" - cell $and $and$ls180.v:6134$1430 + attribute \src "ls180.v:4024.22-4024.77" + cell $and $and$ls180.v:4024$1191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6134$1428_Y - connect \B $eq$ls180.v:6134$1429_Y - connect \Y $and$ls180.v:6134$1430_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4024$1191_Y end - attribute \src "ls180.v:6136.39-6136.92" - cell $and $and$ls180.v:6136$1431 + attribute \src "ls180.v:4024.21-4024.112" + cell $and $and$ls180.v:4024$1192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6136$1431_Y + connect \A $and$ls180.v:4024$1191_Y + connect \B \sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:4024$1192_Y end - attribute \src "ls180.v:6136.38-6136.142" - cell $and $and$ls180.v:6136$1433 + attribute \src "ls180.v:4027.22-4027.77" + cell $and $and$ls180.v:4027$1193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6136$1431_Y - connect \B $eq$ls180.v:6136$1432_Y - connect \Y $and$ls180.v:6136$1433_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4027$1193_Y end - attribute \src "ls180.v:6137.39-6137.95" - cell $and $and$ls180.v:6137$1435 + attribute \src "ls180.v:4027.21-4027.112" + cell $and $and$ls180.v:4027$1194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6137$1434_Y - connect \Y $and$ls180.v:6137$1435_Y + connect \A $and$ls180.v:4027$1193_Y + connect \B \sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:4027$1194_Y end - attribute \src "ls180.v:6137.38-6137.145" - cell $and $and$ls180.v:6137$1437 + attribute \src "ls180.v:4030.22-4030.55" + cell $and $and$ls180.v:4030$1195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6137$1435_Y - connect \B $eq$ls180.v:6137$1436_Y - connect \Y $and$ls180.v:6137$1437_Y + connect \A \sdram_cmd_valid + connect \B \sdram_cmd_ready + connect \Y $and$ls180.v:4030$1195_Y end - attribute \src "ls180.v:6139.40-6139.93" - cell $and $and$ls180.v:6139$1438 + attribute \src "ls180.v:4030.21-4030.79" + cell $and $and$ls180.v:4030$1196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6139$1438_Y + connect \A $and$ls180.v:4030$1195_Y + connect \B \sdram_cmd_payload_we + connect \Y $and$ls180.v:4030$1196_Y end - attribute \src "ls180.v:6139.39-6139.143" - cell $and $and$ls180.v:6139$1440 + attribute \src "ls180.v:4041.22-4041.77" + cell $and $and$ls180.v:4041$1198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6139$1438_Y - connect \B $eq$ls180.v:6139$1439_Y - connect \Y $and$ls180.v:6139$1440_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4041$1198_Y end - attribute \src "ls180.v:6140.40-6140.96" - cell $and $and$ls180.v:6140$1442 + attribute \src "ls180.v:4041.21-4041.117" + cell $and $and$ls180.v:4041$1199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6140$1441_Y - connect \Y $and$ls180.v:6140$1442_Y + connect \A $and$ls180.v:4041$1198_Y + connect \B \sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:4041$1199_Y end - attribute \src "ls180.v:6140.39-6140.146" - cell $and $and$ls180.v:6140$1444 + attribute \src "ls180.v:4044.22-4044.77" + cell $and $and$ls180.v:4044$1200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6140$1442_Y - connect \B $eq$ls180.v:6140$1443_Y - connect \Y $and$ls180.v:6140$1444_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4044$1200_Y end - attribute \src "ls180.v:6142.40-6142.93" - cell $and $and$ls180.v:6142$1445 + attribute \src "ls180.v:4044.21-4044.117" + cell $and $and$ls180.v:4044$1201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6142$1445_Y + connect \A $and$ls180.v:4044$1200_Y + connect \B \sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:4044$1201_Y end - attribute \src "ls180.v:6142.39-6142.143" - cell $and $and$ls180.v:6142$1447 + attribute \src "ls180.v:4047.22-4047.55" + cell $and $and$ls180.v:4047$1202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6142$1445_Y - connect \B $eq$ls180.v:6142$1446_Y - connect \Y $and$ls180.v:6142$1447_Y + connect \A \sdram_cmd_valid + connect \B \sdram_cmd_ready + connect \Y $and$ls180.v:4047$1202_Y end - attribute \src "ls180.v:6143.40-6143.96" - cell $and $and$ls180.v:6143$1449 + attribute \src "ls180.v:4047.21-4047.84" + cell $and $and$ls180.v:4047$1203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6143$1448_Y - connect \Y $and$ls180.v:6143$1449_Y + connect \A $and$ls180.v:4047$1202_Y + connect \B \sdram_cmd_payload_is_read + connect \Y $and$ls180.v:4047$1203_Y end - attribute \src "ls180.v:6143.39-6143.146" - cell $and $and$ls180.v:6143$1451 + attribute \src "ls180.v:4058.22-4058.77" + cell $and $and$ls180.v:4058$1205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6143$1449_Y - connect \B $eq$ls180.v:6143$1450_Y - connect \Y $and$ls180.v:6143$1451_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4058$1205_Y end - attribute \src "ls180.v:6145.40-6145.93" - cell $and $and$ls180.v:6145$1452 + attribute \src "ls180.v:4058.21-4058.118" + cell $and $and$ls180.v:4058$1206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6145$1452_Y + connect \A $and$ls180.v:4058$1205_Y + connect \B \sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:4058$1206_Y end - attribute \src "ls180.v:6145.39-6145.143" - cell $and $and$ls180.v:6145$1454 + attribute \src "ls180.v:4061.22-4061.77" + cell $and $and$ls180.v:4061$1207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6145$1452_Y - connect \B $eq$ls180.v:6145$1453_Y - connect \Y $and$ls180.v:6145$1454_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4061$1207_Y end - attribute \src "ls180.v:6146.40-6146.96" - cell $and $and$ls180.v:6146$1456 + attribute \src "ls180.v:4061.21-4061.118" + cell $and $and$ls180.v:4061$1208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6146$1455_Y - connect \Y $and$ls180.v:6146$1456_Y + connect \A $and$ls180.v:4061$1207_Y + connect \B \sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:4061$1208_Y end - attribute \src "ls180.v:6146.39-6146.146" - cell $and $and$ls180.v:6146$1458 + attribute \src "ls180.v:4064.22-4064.55" + cell $and $and$ls180.v:4064$1209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6146$1456_Y - connect \B $eq$ls180.v:6146$1457_Y - connect \Y $and$ls180.v:6146$1458_Y + connect \A \sdram_cmd_valid + connect \B \sdram_cmd_ready + connect \Y $and$ls180.v:4064$1209_Y end - attribute \src "ls180.v:6148.40-6148.93" - cell $and $and$ls180.v:6148$1459 + attribute \src "ls180.v:4064.21-4064.85" + cell $and $and$ls180.v:4064$1210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6148$1459_Y + connect \A $and$ls180.v:4064$1209_Y + connect \B \sdram_cmd_payload_is_write + connect \Y $and$ls180.v:4064$1210_Y end - attribute \src "ls180.v:6148.39-6148.143" - cell $and $and$ls180.v:6148$1461 + attribute \src "ls180.v:4232.57-4232.97" + cell $and $and$ls180.v:4232$1213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6148$1459_Y - connect \B $eq$ls180.v:6148$1460_Y - connect \Y $and$ls180.v:6148$1461_Y + connect \A \dfi_p0_wrdata_en + connect \B \dfi_p0_wrdata_mask [0] + connect \Y $and$ls180.v:4232$1213_Y end - attribute \src "ls180.v:6149.40-6149.96" - cell $and $and$ls180.v:6149$1463 + attribute \src "ls180.v:4233.57-4233.97" + cell $and $and$ls180.v:4233$1214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6149$1462_Y - connect \Y $and$ls180.v:6149$1463_Y + connect \A \dfi_p0_wrdata_en + connect \B \dfi_p0_wrdata_mask [1] + connect \Y $and$ls180.v:4233$1214_Y end - attribute \src "ls180.v:6149.39-6149.146" - cell $and $and$ls180.v:6149$1465 + attribute \src "ls180.v:4361.8-4361.57" + cell $and $and$ls180.v:4361$1257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6149$1463_Y - connect \B $eq$ls180.v:6149$1464_Y - connect \Y $and$ls180.v:6149$1465_Y + connect \A \libresocsim_ram_bus_cyc + connect \B \libresocsim_ram_bus_stb + connect \Y $and$ls180.v:4361$1257_Y end - attribute \src "ls180.v:6161.40-6161.93" - cell $and $and$ls180.v:6161$1467 + attribute \src "ls180.v:4361.7-4361.87" + cell $and $and$ls180.v:4361$1259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6161$1467_Y + connect \A $and$ls180.v:4361$1257_Y + connect \B $not$ls180.v:4361$1258_Y + connect \Y $and$ls180.v:4361$1259_Y end - attribute \src "ls180.v:6161.39-6161.143" - cell $and $and$ls180.v:6161$1469 + attribute \src "ls180.v:4380.7-4380.65" + cell $and $and$ls180.v:4380$1263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6161$1467_Y - connect \B $eq$ls180.v:6161$1468_Y - connect \Y $and$ls180.v:6161$1469_Y + connect \A $not$ls180.v:4380$1262_Y + connect \B \libresocsim_zero_old_trigger + connect \Y $and$ls180.v:4380$1263_Y end - attribute \src "ls180.v:6162.40-6162.96" - cell $and $and$ls180.v:6162$1471 + attribute \src "ls180.v:4384.8-4384.49" + cell $and $and$ls180.v:4384$1264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6162$1470_Y - connect \Y $and$ls180.v:6162$1471_Y + connect \A \ram_bus_ram_bus_cyc + connect \B \ram_bus_ram_bus_stb + connect \Y $and$ls180.v:4384$1264_Y end - attribute \src "ls180.v:6162.39-6162.146" - cell $and $and$ls180.v:6162$1473 + attribute \src "ls180.v:4384.7-4384.75" + cell $and $and$ls180.v:4384$1266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6162$1471_Y - connect \B $eq$ls180.v:6162$1472_Y - connect \Y $and$ls180.v:6162$1473_Y + connect \A $and$ls180.v:4384$1264_Y + connect \B $not$ls180.v:4384$1265_Y + connect \Y $and$ls180.v:4384$1266_Y end - attribute \src "ls180.v:6164.39-6164.92" - cell $and $and$ls180.v:6164$1474 + attribute \src "ls180.v:4392.7-4392.46" + cell $and $and$ls180.v:4392$1268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6164$1474_Y + connect \A \sdram_timer_wait + connect \B $not$ls180.v:4392$1267_Y + connect \Y $and$ls180.v:4392$1268_Y end - attribute \src "ls180.v:6164.38-6164.142" - cell $and $and$ls180.v:6164$1476 + attribute \src "ls180.v:4420.7-4420.65" + cell $and $and$ls180.v:4420$1275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6164$1474_Y - connect \B $eq$ls180.v:6164$1475_Y - connect \Y $and$ls180.v:6164$1476_Y + connect \A \sdram_sequencer_start1 + connect \B $eq$ls180.v:4420$1274_Y + connect \Y $and$ls180.v:4420$1275_Y end - attribute \src "ls180.v:6165.39-6165.95" - cell $and $and$ls180.v:6165$1478 + attribute \src "ls180.v:4462.8-4462.121" + cell $and $and$ls180.v:4462$1281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6165$1477_Y - connect \Y $and$ls180.v:6165$1478_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:4462$1281_Y end - attribute \src "ls180.v:6165.38-6165.145" - cell $and $and$ls180.v:6165$1480 + attribute \src "ls180.v:4462.7-4462.175" + cell $and $and$ls180.v:4462$1283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6165$1478_Y - connect \B $eq$ls180.v:6165$1479_Y - connect \Y $and$ls180.v:6165$1480_Y + connect \A $and$ls180.v:4462$1281_Y + connect \B $not$ls180.v:4462$1282_Y + connect \Y $and$ls180.v:4462$1283_Y end - attribute \src "ls180.v:6167.39-6167.92" - cell $and $and$ls180.v:6167$1481 + attribute \src "ls180.v:4468.8-4468.121" + cell $and $and$ls180.v:4468$1286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6167$1481_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:4468$1286_Y end - attribute \src "ls180.v:6167.38-6167.142" - cell $and $and$ls180.v:6167$1483 + attribute \src "ls180.v:4468.7-4468.175" + cell $and $and$ls180.v:4468$1288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6167$1481_Y - connect \B $eq$ls180.v:6167$1482_Y - connect \Y $and$ls180.v:6167$1483_Y + connect \A $and$ls180.v:4468$1286_Y + connect \B $not$ls180.v:4468$1287_Y + connect \Y $and$ls180.v:4468$1288_Y end - attribute \src "ls180.v:6168.39-6168.95" - cell $and $and$ls180.v:6168$1485 + attribute \src "ls180.v:4508.8-4508.121" + cell $and $and$ls180.v:4508$1297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6168$1484_Y - connect \Y $and$ls180.v:6168$1485_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:4508$1297_Y end - attribute \src "ls180.v:6168.38-6168.145" - cell $and $and$ls180.v:6168$1487 + attribute \src "ls180.v:4508.7-4508.175" + cell $and $and$ls180.v:4508$1299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6168$1485_Y - connect \B $eq$ls180.v:6168$1486_Y - connect \Y $and$ls180.v:6168$1487_Y + connect \A $and$ls180.v:4508$1297_Y + connect \B $not$ls180.v:4508$1298_Y + connect \Y $and$ls180.v:4508$1299_Y end - attribute \src "ls180.v:6170.39-6170.92" - cell $and $and$ls180.v:6170$1488 + attribute \src "ls180.v:4514.8-4514.121" + cell $and $and$ls180.v:4514$1302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6170$1488_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:4514$1302_Y end - attribute \src "ls180.v:6170.38-6170.142" - cell $and $and$ls180.v:6170$1490 + attribute \src "ls180.v:4514.7-4514.175" + cell $and $and$ls180.v:4514$1304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6170$1488_Y - connect \B $eq$ls180.v:6170$1489_Y - connect \Y $and$ls180.v:6170$1490_Y + connect \A $and$ls180.v:4514$1302_Y + connect \B $not$ls180.v:4514$1303_Y + connect \Y $and$ls180.v:4514$1304_Y end - attribute \src "ls180.v:6171.39-6171.95" - cell $and $and$ls180.v:6171$1492 + attribute \src "ls180.v:4554.8-4554.121" + cell $and $and$ls180.v:4554$1313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6171$1491_Y - connect \Y $and$ls180.v:6171$1492_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:4554$1313_Y end - attribute \src "ls180.v:6171.38-6171.145" - cell $and $and$ls180.v:6171$1494 + attribute \src "ls180.v:4554.7-4554.175" + cell $and $and$ls180.v:4554$1315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6171$1492_Y - connect \B $eq$ls180.v:6171$1493_Y - connect \Y $and$ls180.v:6171$1494_Y + connect \A $and$ls180.v:4554$1313_Y + connect \B $not$ls180.v:4554$1314_Y + connect \Y $and$ls180.v:4554$1315_Y end - attribute \src "ls180.v:6173.39-6173.92" - cell $and $and$ls180.v:6173$1495 + attribute \src "ls180.v:4560.8-4560.121" + cell $and $and$ls180.v:4560$1318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6173$1495_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:4560$1318_Y end - attribute \src "ls180.v:6173.38-6173.142" - cell $and $and$ls180.v:6173$1497 + attribute \src "ls180.v:4560.7-4560.175" + cell $and $and$ls180.v:4560$1320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6173$1495_Y - connect \B $eq$ls180.v:6173$1496_Y - connect \Y $and$ls180.v:6173$1497_Y + connect \A $and$ls180.v:4560$1318_Y + connect \B $not$ls180.v:4560$1319_Y + connect \Y $and$ls180.v:4560$1320_Y end - attribute \src "ls180.v:6174.39-6174.95" - cell $and $and$ls180.v:6174$1499 + attribute \src "ls180.v:4600.8-4600.121" + cell $and $and$ls180.v:4600$1329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6174$1498_Y - connect \Y $and$ls180.v:6174$1499_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:4600$1329_Y end - attribute \src "ls180.v:6174.38-6174.145" - cell $and $and$ls180.v:6174$1501 + attribute \src "ls180.v:4600.7-4600.175" + cell $and $and$ls180.v:4600$1331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6174$1499_Y - connect \B $eq$ls180.v:6174$1500_Y - connect \Y $and$ls180.v:6174$1501_Y + connect \A $and$ls180.v:4600$1329_Y + connect \B $not$ls180.v:4600$1330_Y + connect \Y $and$ls180.v:4600$1331_Y end - attribute \src "ls180.v:6176.40-6176.93" - cell $and $and$ls180.v:6176$1502 + attribute \src "ls180.v:4606.8-4606.121" + cell $and $and$ls180.v:4606$1334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6176$1502_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:4606$1334_Y end - attribute \src "ls180.v:6176.39-6176.143" - cell $and $and$ls180.v:6176$1504 + attribute \src "ls180.v:4606.7-4606.175" + cell $and $and$ls180.v:4606$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6176$1502_Y - connect \B $eq$ls180.v:6176$1503_Y - connect \Y $and$ls180.v:6176$1504_Y + connect \A $and$ls180.v:4606$1334_Y + connect \B $not$ls180.v:4606$1335_Y + connect \Y $and$ls180.v:4606$1336_Y end - attribute \src "ls180.v:6177.40-6177.96" - cell $and $and$ls180.v:6177$1506 + attribute \src "ls180.v:4803.53-4803.129" + cell $and $and$ls180.v:4803$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6177$1505_Y - connect \Y $and$ls180.v:6177$1506_Y + connect \A $eq$ls180.v:4803$1360_Y + connect \B \sdram_interface_bank0_wdata_ready + connect \Y $and$ls180.v:4803$1361_Y end - attribute \src "ls180.v:6177.39-6177.146" - cell $and $and$ls180.v:6177$1508 + attribute \src "ls180.v:4803.135-4803.211" + cell $and $and$ls180.v:4803$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6177$1506_Y - connect \B $eq$ls180.v:6177$1507_Y - connect \Y $and$ls180.v:6177$1508_Y + connect \A $eq$ls180.v:4803$1363_Y + connect \B \sdram_interface_bank1_wdata_ready + connect \Y $and$ls180.v:4803$1364_Y end - attribute \src "ls180.v:6179.40-6179.93" - cell $and $and$ls180.v:6179$1509 + attribute \src "ls180.v:4803.217-4803.293" + cell $and $and$ls180.v:4803$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6179$1509_Y + connect \A $eq$ls180.v:4803$1366_Y + connect \B \sdram_interface_bank2_wdata_ready + connect \Y $and$ls180.v:4803$1367_Y end - attribute \src "ls180.v:6179.39-6179.143" - cell $and $and$ls180.v:6179$1511 + attribute \src "ls180.v:4803.299-4803.375" + cell $and $and$ls180.v:4803$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6179$1509_Y - connect \B $eq$ls180.v:6179$1510_Y - connect \Y $and$ls180.v:6179$1511_Y + connect \A $eq$ls180.v:4803$1369_Y + connect \B \sdram_interface_bank3_wdata_ready + connect \Y $and$ls180.v:4803$1370_Y end - attribute \src "ls180.v:6180.40-6180.96" - cell $and $and$ls180.v:6180$1513 + attribute \src "ls180.v:4804.54-4804.130" + cell $and $and$ls180.v:4804$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6180$1512_Y - connect \Y $and$ls180.v:6180$1513_Y + connect \A $eq$ls180.v:4804$1372_Y + connect \B \sdram_interface_bank0_rdata_valid + connect \Y $and$ls180.v:4804$1373_Y end - attribute \src "ls180.v:6180.39-6180.146" - cell $and $and$ls180.v:6180$1515 + attribute \src "ls180.v:4804.136-4804.212" + cell $and $and$ls180.v:4804$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6180$1513_Y - connect \B $eq$ls180.v:6180$1514_Y - connect \Y $and$ls180.v:6180$1515_Y + connect \A $eq$ls180.v:4804$1375_Y + connect \B \sdram_interface_bank1_rdata_valid + connect \Y $and$ls180.v:4804$1376_Y end - attribute \src "ls180.v:6182.40-6182.93" - cell $and $and$ls180.v:6182$1516 + attribute \src "ls180.v:4804.218-4804.294" + cell $and $and$ls180.v:4804$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6182$1516_Y + connect \A $eq$ls180.v:4804$1378_Y + connect \B \sdram_interface_bank2_rdata_valid + connect \Y $and$ls180.v:4804$1379_Y end - attribute \src "ls180.v:6182.39-6182.143" - cell $and $and$ls180.v:6182$1518 + attribute \src "ls180.v:4804.300-4804.376" + cell $and $and$ls180.v:4804$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6182$1516_Y - connect \B $eq$ls180.v:6182$1517_Y - connect \Y $and$ls180.v:6182$1518_Y + connect \A $eq$ls180.v:4804$1381_Y + connect \B \sdram_interface_bank3_rdata_valid + connect \Y $and$ls180.v:4804$1382_Y end - attribute \src "ls180.v:6183.40-6183.96" - cell $and $and$ls180.v:6183$1520 + attribute \src "ls180.v:4823.8-4823.39" + cell $and $and$ls180.v:4823$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6183$1519_Y - connect \Y $and$ls180.v:6183$1520_Y + connect \A \port_cmd_valid + connect \B \port_cmd_ready + connect \Y $and$ls180.v:4823$1385_Y end - attribute \src "ls180.v:6183.39-6183.146" - cell $and $and$ls180.v:6183$1522 + attribute \src "ls180.v:4826.8-4826.43" + cell $and $and$ls180.v:4826$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6183$1520_Y - connect \B $eq$ls180.v:6183$1521_Y - connect \Y $and$ls180.v:6183$1522_Y + connect \A \port_wdata_valid + connect \B \port_wdata_ready + connect \Y $and$ls180.v:4826$1386_Y end - attribute \src "ls180.v:6185.40-6185.93" - cell $and $and$ls180.v:6185$1523 + attribute \src "ls180.v:4831.8-4831.49" + cell $and $and$ls180.v:4831$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6185$1523_Y + connect \A \uart_phy_sink_valid + connect \B $not$ls180.v:4831$1387_Y + connect \Y $and$ls180.v:4831$1388_Y end - attribute \src "ls180.v:6185.39-6185.143" - cell $and $and$ls180.v:6185$1525 + attribute \src "ls180.v:4831.7-4831.75" + cell $and $and$ls180.v:4831$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6185$1523_Y - connect \B $eq$ls180.v:6185$1524_Y - connect \Y $and$ls180.v:6185$1525_Y + connect \A $and$ls180.v:4831$1388_Y + connect \B $not$ls180.v:4831$1389_Y + connect \Y $and$ls180.v:4831$1390_Y end - attribute \src "ls180.v:6186.40-6186.96" - cell $and $and$ls180.v:6186$1527 + attribute \src "ls180.v:4837.8-4837.49" + cell $and $and$ls180.v:4837$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6186$1526_Y - connect \Y $and$ls180.v:6186$1527_Y + connect \A \uart_phy_uart_clk_txen + connect \B \uart_phy_tx_busy + connect \Y $and$ls180.v:4837$1391_Y end - attribute \src "ls180.v:6186.39-6186.146" - cell $and $and$ls180.v:6186$1529 + attribute \src "ls180.v:4861.8-4861.38" + cell $and $and$ls180.v:4861$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6186$1527_Y - connect \B $eq$ls180.v:6186$1528_Y - connect \Y $and$ls180.v:6186$1529_Y + connect \A $not$ls180.v:4861$1397_Y + connect \B \uart_phy_rx_r + connect \Y $and$ls180.v:4861$1398_Y end - attribute \src "ls180.v:6198.42-6198.95" - cell $and $and$ls180.v:6198$1531 + attribute \src "ls180.v:4894.7-4894.37" + cell $and $and$ls180.v:4894$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6198$1531_Y + connect \A $not$ls180.v:4894$1403_Y + connect \B \tx_old_trigger + connect \Y $and$ls180.v:4894$1404_Y end - attribute \src "ls180.v:6198.41-6198.145" - cell $and $and$ls180.v:6198$1533 + attribute \src "ls180.v:4901.7-4901.37" + cell $and $and$ls180.v:4901$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6198$1531_Y - connect \B $eq$ls180.v:6198$1532_Y - connect \Y $and$ls180.v:6198$1533_Y + connect \A $not$ls180.v:4901$1405_Y + connect \B \rx_old_trigger + connect \Y $and$ls180.v:4901$1406_Y end - attribute \src "ls180.v:6199.42-6199.98" - cell $and $and$ls180.v:6199$1535 + attribute \src "ls180.v:4911.8-4911.55" + cell $and $and$ls180.v:4911$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6199$1534_Y - connect \Y $and$ls180.v:6199$1535_Y + connect \A \tx_fifo_syncfifo_we + connect \B \tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:4911$1407_Y end - attribute \src "ls180.v:6199.41-6199.148" - cell $and $and$ls180.v:6199$1537 + attribute \src "ls180.v:4911.7-4911.77" + cell $and $and$ls180.v:4911$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6199$1535_Y - connect \B $eq$ls180.v:6199$1536_Y - connect \Y $and$ls180.v:6199$1537_Y + connect \A $and$ls180.v:4911$1407_Y + connect \B $not$ls180.v:4911$1408_Y + connect \Y $and$ls180.v:4911$1409_Y end - attribute \src "ls180.v:6201.42-6201.95" - cell $and $and$ls180.v:6201$1538 + attribute \src "ls180.v:4917.8-4917.55" + cell $and $and$ls180.v:4917$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6201$1538_Y + connect \A \tx_fifo_syncfifo_we + connect \B \tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:4917$1412_Y end - attribute \src "ls180.v:6201.41-6201.145" - cell $and $and$ls180.v:6201$1540 + attribute \src "ls180.v:4917.7-4917.77" + cell $and $and$ls180.v:4917$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6201$1538_Y - connect \B $eq$ls180.v:6201$1539_Y - connect \Y $and$ls180.v:6201$1540_Y + connect \A $and$ls180.v:4917$1412_Y + connect \B $not$ls180.v:4917$1413_Y + connect \Y $and$ls180.v:4917$1414_Y end - attribute \src "ls180.v:6202.42-6202.98" - cell $and $and$ls180.v:6202$1542 + attribute \src "ls180.v:4933.8-4933.55" + cell $and $and$ls180.v:4933$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6202$1541_Y - connect \Y $and$ls180.v:6202$1542_Y + connect \A \rx_fifo_syncfifo_we + connect \B \rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:4933$1418_Y end - attribute \src "ls180.v:6202.41-6202.148" - cell $and $and$ls180.v:6202$1544 + attribute \src "ls180.v:4933.7-4933.77" + cell $and $and$ls180.v:4933$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6202$1542_Y - connect \B $eq$ls180.v:6202$1543_Y - connect \Y $and$ls180.v:6202$1544_Y + connect \A $and$ls180.v:4933$1418_Y + connect \B $not$ls180.v:4933$1419_Y + connect \Y $and$ls180.v:4933$1420_Y end - attribute \src "ls180.v:6204.42-6204.95" - cell $and $and$ls180.v:6204$1545 + attribute \src "ls180.v:4939.8-4939.55" + cell $and $and$ls180.v:4939$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6204$1545_Y + connect \A \rx_fifo_syncfifo_we + connect \B \rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:4939$1423_Y end - attribute \src "ls180.v:6204.41-6204.145" - cell $and $and$ls180.v:6204$1547 + attribute \src "ls180.v:4939.7-4939.77" + cell $and $and$ls180.v:4939$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6204$1545_Y - connect \B $eq$ls180.v:6204$1546_Y - connect \Y $and$ls180.v:6204$1547_Y + connect \A $and$ls180.v:4939$1423_Y + connect \B $not$ls180.v:4939$1424_Y + connect \Y $and$ls180.v:4939$1425_Y end - attribute \src "ls180.v:6205.42-6205.98" - cell $and $and$ls180.v:6205$1549 + attribute \src "ls180.v:1556.37-1556.91" + cell $eq $eq$ls180.v:1556$21 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6205$1548_Y - connect \Y $and$ls180.v:6205$1549_Y + connect \A \libresocsim_interface0_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:1556$21_Y end - attribute \src "ls180.v:6205.41-6205.148" - cell $and $and$ls180.v:6205$1551 + attribute \src "ls180.v:1563.11-1563.49" + cell $eq $eq$ls180.v:1563$26 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6205$1549_Y - connect \B $eq$ls180.v:6205$1550_Y - connect \Y $and$ls180.v:6205$1551_Y + connect \A \libresocsim_converter0_counter + connect \B 1'1 + connect \Y $eq$ls180.v:1563$26_Y end - attribute \src "ls180.v:6207.42-6207.95" - cell $and $and$ls180.v:6207$1552 + attribute \src "ls180.v:1616.37-1616.91" + cell $eq $eq$ls180.v:1616$32 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6207$1552_Y + connect \A \libresocsim_interface1_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:1616$32_Y end - attribute \src "ls180.v:6207.41-6207.145" - cell $and $and$ls180.v:6207$1554 + attribute \src "ls180.v:1623.11-1623.49" + cell $eq $eq$ls180.v:1623$37 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6207$1552_Y - connect \B $eq$ls180.v:6207$1553_Y - connect \Y $and$ls180.v:6207$1554_Y + connect \A \libresocsim_converter1_counter + connect \B 1'1 + connect \Y $eq$ls180.v:1623$37_Y end - attribute \src "ls180.v:6208.42-6208.98" - cell $and $and$ls180.v:6208$1556 + attribute \src "ls180.v:1676.37-1676.91" + cell $eq $eq$ls180.v:1676$43 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6208$1555_Y - connect \Y $and$ls180.v:6208$1556_Y + connect \A \libresocsim_interface2_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:1676$43_Y end - attribute \src "ls180.v:6208.41-6208.148" - cell $and $and$ls180.v:6208$1558 + attribute \src "ls180.v:1683.11-1683.49" + cell $eq $eq$ls180.v:1683$48 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6208$1556_Y - connect \B $eq$ls180.v:6208$1557_Y - connect \Y $and$ls180.v:6208$1558_Y + connect \A \libresocsim_converter2_counter + connect \B 1'1 + connect \Y $eq$ls180.v:1683$48_Y end - attribute \src "ls180.v:6210.42-6210.95" - cell $and $and$ls180.v:6210$1559 + attribute \src "ls180.v:1879.29-1879.55" + cell $eq $eq$ls180.v:1879$89 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6210$1559_Y + connect \A \sdram_timer_count1 + connect \B 1'0 + connect \Y $eq$ls180.v:1879$89_Y end - attribute \src "ls180.v:6210.41-6210.145" - cell $and $and$ls180.v:6210$1561 + attribute \src "ls180.v:1883.58-1883.87" + cell $eq $eq$ls180.v:1883$92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6210$1559_Y - connect \B $eq$ls180.v:6210$1560_Y - connect \Y $and$ls180.v:6210$1561_Y + connect \A \sdram_sequencer_count + connect \B 1'0 + connect \Y $eq$ls180.v:1883$92_Y end - attribute \src "ls180.v:6211.42-6211.98" - cell $and $and$ls180.v:6211$1563 + attribute \src "ls180.v:1927.38-1927.119" + cell $eq $eq$ls180.v:1927$97 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6211$1562_Y - connect \Y $and$ls180.v:6211$1563_Y + connect \A \sdram_bankmachine0_row + connect \B \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:1927$97_Y end - attribute \src "ls180.v:6211.41-6211.148" - cell $and $and$ls180.v:6211$1565 + attribute \src "ls180.v:1944.42-1944.78" + cell $eq $eq$ls180.v:1944$110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6211$1563_Y - connect \B $eq$ls180.v:6211$1564_Y - connect \Y $and$ls180.v:6211$1565_Y + connect \A \sdram_bankmachine0_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:1944$110_Y end - attribute \src "ls180.v:6213.42-6213.95" - cell $and $and$ls180.v:6213$1566 + attribute \src "ls180.v:2084.38-2084.119" + cell $eq $eq$ls180.v:2084$127 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6213$1566_Y + connect \A \sdram_bankmachine1_row + connect \B \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:2084$127_Y end - attribute \src "ls180.v:6213.41-6213.145" - cell $and $and$ls180.v:6213$1568 + attribute \src "ls180.v:2101.42-2101.78" + cell $eq $eq$ls180.v:2101$140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6213$1566_Y - connect \B $eq$ls180.v:6213$1567_Y - connect \Y $and$ls180.v:6213$1568_Y + connect \A \sdram_bankmachine1_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:2101$140_Y end - attribute \src "ls180.v:6214.42-6214.98" - cell $and $and$ls180.v:6214$1570 + attribute \src "ls180.v:2241.38-2241.119" + cell $eq $eq$ls180.v:2241$157 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6214$1569_Y - connect \Y $and$ls180.v:6214$1570_Y + connect \A \sdram_bankmachine2_row + connect \B \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:2241$157_Y end - attribute \src "ls180.v:6214.41-6214.148" - cell $and $and$ls180.v:6214$1572 + attribute \src "ls180.v:2258.42-2258.78" + cell $eq $eq$ls180.v:2258$170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6214$1570_Y - connect \B $eq$ls180.v:6214$1571_Y - connect \Y $and$ls180.v:6214$1572_Y + connect \A \sdram_bankmachine2_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:2258$170_Y end - attribute \src "ls180.v:6216.42-6216.95" - cell $and $and$ls180.v:6216$1573 + attribute \src "ls180.v:2398.38-2398.119" + cell $eq $eq$ls180.v:2398$187 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6216$1573_Y + connect \A \sdram_bankmachine3_row + connect \B \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:2398$187_Y end - attribute \src "ls180.v:6216.41-6216.145" - cell $and $and$ls180.v:6216$1575 + attribute \src "ls180.v:2415.42-2415.78" + cell $eq $eq$ls180.v:2415$200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6216$1573_Y - connect \B $eq$ls180.v:6216$1574_Y - connect \Y $and$ls180.v:6216$1575_Y + connect \A \sdram_bankmachine3_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:2415$200_Y end - attribute \src "ls180.v:6217.42-6217.98" - cell $and $and$ls180.v:6217$1577 + attribute \src "ls180.v:2552.27-2552.46" + cell $eq $eq$ls180.v:2552$247 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6217$1576_Y - connect \Y $and$ls180.v:6217$1577_Y + connect \A \sdram_time0 + connect \B 1'0 + connect \Y $eq$ls180.v:2552$247_Y end - attribute \src "ls180.v:6217.41-6217.148" - cell $and $and$ls180.v:6217$1579 + attribute \src "ls180.v:2553.27-2553.46" + cell $eq $eq$ls180.v:2553$248 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6217$1577_Y - connect \B $eq$ls180.v:6217$1578_Y - connect \Y $and$ls180.v:6217$1579_Y + connect \A \sdram_time1 + connect \B 1'0 + connect \Y $eq$ls180.v:2553$248_Y end - attribute \src "ls180.v:6219.42-6219.95" - cell $and $and$ls180.v:6219$1580 + attribute \src "ls180.v:2564.299-2564.368" + cell $eq $eq$ls180.v:2564$262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6219$1580_Y + connect \A \sdram_bankmachine0_cmd_payload_is_read + connect \B \sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:2564$262_Y end - attribute \src "ls180.v:6219.41-6219.145" - cell $and $and$ls180.v:6219$1582 + attribute \src "ls180.v:2564.373-2564.444" + cell $eq $eq$ls180.v:2564$263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6219$1580_Y - connect \B $eq$ls180.v:6219$1581_Y - connect \Y $and$ls180.v:6219$1582_Y + connect \A \sdram_bankmachine0_cmd_payload_is_write + connect \B \sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:2564$263_Y end - attribute \src "ls180.v:6220.42-6220.98" - cell $and $and$ls180.v:6220$1584 + attribute \src "ls180.v:2565.299-2565.368" + cell $eq $eq$ls180.v:2565$275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6220$1583_Y - connect \Y $and$ls180.v:6220$1584_Y + connect \A \sdram_bankmachine1_cmd_payload_is_read + connect \B \sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:2565$275_Y end - attribute \src "ls180.v:6220.41-6220.148" - cell $and $and$ls180.v:6220$1586 + attribute \src "ls180.v:2565.373-2565.444" + cell $eq $eq$ls180.v:2565$276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6220$1584_Y - connect \B $eq$ls180.v:6220$1585_Y - connect \Y $and$ls180.v:6220$1586_Y + connect \A \sdram_bankmachine1_cmd_payload_is_write + connect \B \sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:2565$276_Y end - attribute \src "ls180.v:6222.44-6222.97" - cell $and $and$ls180.v:6222$1587 + attribute \src "ls180.v:2566.299-2566.368" + cell $eq $eq$ls180.v:2566$288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6222$1587_Y + connect \A \sdram_bankmachine2_cmd_payload_is_read + connect \B \sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:2566$288_Y end - attribute \src "ls180.v:6222.43-6222.147" - cell $and $and$ls180.v:6222$1589 + attribute \src "ls180.v:2566.373-2566.444" + cell $eq $eq$ls180.v:2566$289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6222$1587_Y - connect \B $eq$ls180.v:6222$1588_Y - connect \Y $and$ls180.v:6222$1589_Y + connect \A \sdram_bankmachine2_cmd_payload_is_write + connect \B \sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:2566$289_Y end - attribute \src "ls180.v:6223.44-6223.100" - cell $and $and$ls180.v:6223$1591 + attribute \src "ls180.v:2567.299-2567.368" + cell $eq $eq$ls180.v:2567$301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6223$1590_Y - connect \Y $and$ls180.v:6223$1591_Y + connect \A \sdram_bankmachine3_cmd_payload_is_read + connect \B \sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:2567$301_Y end - attribute \src "ls180.v:6223.43-6223.150" - cell $and $and$ls180.v:6223$1593 + attribute \src "ls180.v:2567.373-2567.444" + cell $eq $eq$ls180.v:2567$302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6223$1591_Y - connect \B $eq$ls180.v:6223$1592_Y - connect \Y $and$ls180.v:6223$1593_Y + connect \A \sdram_bankmachine3_cmd_payload_is_write + connect \B \sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:2567$302_Y end - attribute \src "ls180.v:6225.44-6225.97" - cell $and $and$ls180.v:6225$1594 + attribute \src "ls180.v:2597.299-2597.368" + cell $eq $eq$ls180.v:2597$320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6225$1594_Y + connect \A \sdram_bankmachine0_cmd_payload_is_read + connect \B \sdram_choose_req_want_reads + connect \Y $eq$ls180.v:2597$320_Y end - attribute \src "ls180.v:6225.43-6225.147" - cell $and $and$ls180.v:6225$1596 + attribute \src "ls180.v:2597.373-2597.444" + cell $eq $eq$ls180.v:2597$321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6225$1594_Y - connect \B $eq$ls180.v:6225$1595_Y - connect \Y $and$ls180.v:6225$1596_Y + connect \A \sdram_bankmachine0_cmd_payload_is_write + connect \B \sdram_choose_req_want_writes + connect \Y $eq$ls180.v:2597$321_Y end - attribute \src "ls180.v:6226.44-6226.100" - cell $and $and$ls180.v:6226$1598 + attribute \src "ls180.v:2598.299-2598.368" + cell $eq $eq$ls180.v:2598$333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6226$1597_Y - connect \Y $and$ls180.v:6226$1598_Y + connect \A \sdram_bankmachine1_cmd_payload_is_read + connect \B \sdram_choose_req_want_reads + connect \Y $eq$ls180.v:2598$333_Y end - attribute \src "ls180.v:6226.43-6226.150" - cell $and $and$ls180.v:6226$1600 + attribute \src "ls180.v:2598.373-2598.444" + cell $eq $eq$ls180.v:2598$334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6226$1598_Y - connect \B $eq$ls180.v:6226$1599_Y - connect \Y $and$ls180.v:6226$1600_Y + connect \A \sdram_bankmachine1_cmd_payload_is_write + connect \B \sdram_choose_req_want_writes + connect \Y $eq$ls180.v:2598$334_Y end - attribute \src "ls180.v:6228.44-6228.97" - cell $and $and$ls180.v:6228$1601 + attribute \src "ls180.v:2599.299-2599.368" + cell $eq $eq$ls180.v:2599$346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6228$1601_Y + connect \A \sdram_bankmachine2_cmd_payload_is_read + connect \B \sdram_choose_req_want_reads + connect \Y $eq$ls180.v:2599$346_Y end - attribute \src "ls180.v:6228.43-6228.148" - cell $and $and$ls180.v:6228$1603 + attribute \src "ls180.v:2599.373-2599.444" + cell $eq $eq$ls180.v:2599$347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6228$1601_Y - connect \B $eq$ls180.v:6228$1602_Y - connect \Y $and$ls180.v:6228$1603_Y + connect \A \sdram_bankmachine2_cmd_payload_is_write + connect \B \sdram_choose_req_want_writes + connect \Y $eq$ls180.v:2599$347_Y end - attribute \src "ls180.v:6229.44-6229.100" - cell $and $and$ls180.v:6229$1605 + attribute \src "ls180.v:2600.299-2600.368" + cell $eq $eq$ls180.v:2600$359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6229$1604_Y - connect \Y $and$ls180.v:6229$1605_Y + connect \A \sdram_bankmachine3_cmd_payload_is_read + connect \B \sdram_choose_req_want_reads + connect \Y $eq$ls180.v:2600$359_Y end - attribute \src "ls180.v:6229.43-6229.151" - cell $and $and$ls180.v:6229$1607 + attribute \src "ls180.v:2600.373-2600.444" + cell $eq $eq$ls180.v:2600$360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6229$1605_Y - connect \B $eq$ls180.v:6229$1606_Y - connect \Y $and$ls180.v:6229$1607_Y + connect \A \sdram_bankmachine3_cmd_payload_is_write + connect \B \sdram_choose_req_want_writes + connect \Y $eq$ls180.v:2600$360_Y end - attribute \src "ls180.v:6231.44-6231.97" - cell $and $and$ls180.v:6231$1608 + attribute \src "ls180.v:2629.68-2629.98" + cell $eq $eq$ls180.v:2629$369 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6231$1608_Y + connect \A \sdram_choose_cmd_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2629$369_Y end - attribute \src "ls180.v:6231.43-6231.148" - cell $and $and$ls180.v:6231$1610 + attribute \src "ls180.v:2632.68-2632.98" + cell $eq $eq$ls180.v:2632$372 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6231$1608_Y - connect \B $eq$ls180.v:6231$1609_Y - connect \Y $and$ls180.v:6231$1610_Y + connect \A \sdram_choose_req_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2632$372_Y end - attribute \src "ls180.v:6232.44-6232.100" - cell $and $and$ls180.v:6232$1612 + attribute \src "ls180.v:2638.68-2638.98" + cell $eq $eq$ls180.v:2638$376 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6232$1611_Y - connect \Y $and$ls180.v:6232$1612_Y + connect \A \sdram_choose_cmd_grant + connect \B 1'1 + connect \Y $eq$ls180.v:2638$376_Y end - attribute \src "ls180.v:6232.43-6232.151" - cell $and $and$ls180.v:6232$1614 + attribute \src "ls180.v:2641.68-2641.98" + cell $eq $eq$ls180.v:2641$379 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6232$1612_Y - connect \B $eq$ls180.v:6232$1613_Y - connect \Y $and$ls180.v:6232$1614_Y + connect \A \sdram_choose_req_grant + connect \B 1'1 + connect \Y $eq$ls180.v:2641$379_Y end - attribute \src "ls180.v:6234.44-6234.97" - cell $and $and$ls180.v:6234$1615 + attribute \src "ls180.v:2647.68-2647.98" + cell $eq $eq$ls180.v:2647$383 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6234$1615_Y + connect \A \sdram_choose_cmd_grant + connect \B 2'10 + connect \Y $eq$ls180.v:2647$383_Y end - attribute \src "ls180.v:6234.43-6234.148" - cell $and $and$ls180.v:6234$1617 + attribute \src "ls180.v:2650.68-2650.98" + cell $eq $eq$ls180.v:2650$386 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6234$1615_Y - connect \B $eq$ls180.v:6234$1616_Y - connect \Y $and$ls180.v:6234$1617_Y + connect \A \sdram_choose_req_grant + connect \B 2'10 + connect \Y $eq$ls180.v:2650$386_Y end - attribute \src "ls180.v:6235.44-6235.100" - cell $and $and$ls180.v:6235$1619 + attribute \src "ls180.v:2656.68-2656.98" + cell $eq $eq$ls180.v:2656$390 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6235$1618_Y - connect \Y $and$ls180.v:6235$1619_Y + connect \A \sdram_choose_cmd_grant + connect \B 2'11 + connect \Y $eq$ls180.v:2656$390_Y end - attribute \src "ls180.v:6235.43-6235.151" - cell $and $and$ls180.v:6235$1621 + attribute \src "ls180.v:2659.68-2659.98" + cell $eq $eq$ls180.v:2659$393 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6235$1619_Y - connect \B $eq$ls180.v:6235$1620_Y - connect \Y $and$ls180.v:6235$1621_Y + connect \A \sdram_choose_req_grant + connect \B 2'11 + connect \Y $eq$ls180.v:2659$393_Y end - attribute \src "ls180.v:6237.41-6237.94" - cell $and $and$ls180.v:6237$1622 + attribute \src "ls180.v:2740.47-2740.82" + cell $eq $eq$ls180.v:2740$416 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6237$1622_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:2740$416_Y end - attribute \src "ls180.v:6237.40-6237.145" - cell $and $and$ls180.v:6237$1624 + attribute \src "ls180.v:2740.145-2740.183" + cell $eq $eq$ls180.v:2740$417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6237$1622_Y - connect \B $eq$ls180.v:6237$1623_Y - connect \Y $and$ls180.v:6237$1624_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2740$417_Y end - attribute \src "ls180.v:6238.41-6238.97" - cell $and $and$ls180.v:6238$1626 + attribute \src "ls180.v:2740.220-2740.258" + cell $eq $eq$ls180.v:2740$420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6238$1625_Y - connect \Y $and$ls180.v:6238$1626_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2740$420_Y end - attribute \src "ls180.v:6238.40-6238.148" - cell $and $and$ls180.v:6238$1628 + attribute \src "ls180.v:2740.295-2740.333" + cell $eq $eq$ls180.v:2740$423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6238$1626_Y - connect \B $eq$ls180.v:6238$1627_Y - connect \Y $and$ls180.v:6238$1628_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2740$423_Y end - attribute \src "ls180.v:6240.42-6240.95" - cell $and $and$ls180.v:6240$1629 + attribute \src "ls180.v:2745.47-2745.82" + cell $eq $eq$ls180.v:2745$432 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6240$1629_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:2745$432_Y end - attribute \src "ls180.v:6240.41-6240.146" - cell $and $and$ls180.v:6240$1631 + attribute \src "ls180.v:2745.145-2745.183" + cell $eq $eq$ls180.v:2745$433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6240$1629_Y - connect \B $eq$ls180.v:6240$1630_Y - connect \Y $and$ls180.v:6240$1631_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2745$433_Y end - attribute \src "ls180.v:6241.42-6241.98" - cell $and $and$ls180.v:6241$1633 + attribute \src "ls180.v:2745.220-2745.258" + cell $eq $eq$ls180.v:2745$436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6241$1632_Y - connect \Y $and$ls180.v:6241$1633_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2745$436_Y end - attribute \src "ls180.v:6241.41-6241.149" - cell $and $and$ls180.v:6241$1635 + attribute \src "ls180.v:2745.295-2745.333" + cell $eq $eq$ls180.v:2745$439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6241$1633_Y - connect \B $eq$ls180.v:6241$1634_Y - connect \Y $and$ls180.v:6241$1635_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2745$439_Y end - attribute \src "ls180.v:6260.46-6260.99" - cell $and $and$ls180.v:6260$1637 + attribute \src "ls180.v:2750.47-2750.82" + cell $eq $eq$ls180.v:2750$448 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6260$1637_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:2750$448_Y end - attribute \src "ls180.v:6260.45-6260.149" - cell $and $and$ls180.v:6260$1639 + attribute \src "ls180.v:2750.145-2750.183" + cell $eq $eq$ls180.v:2750$449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6260$1637_Y - connect \B $eq$ls180.v:6260$1638_Y - connect \Y $and$ls180.v:6260$1639_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2750$449_Y end - attribute \src "ls180.v:6261.46-6261.102" - cell $and $and$ls180.v:6261$1641 + attribute \src "ls180.v:2750.220-2750.258" + cell $eq $eq$ls180.v:2750$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6261$1640_Y - connect \Y $and$ls180.v:6261$1641_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2750$452_Y end - attribute \src "ls180.v:6261.45-6261.152" - cell $and $and$ls180.v:6261$1643 + attribute \src "ls180.v:2750.295-2750.333" + cell $eq $eq$ls180.v:2750$455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6261$1641_Y - connect \B $eq$ls180.v:6261$1642_Y - connect \Y $and$ls180.v:6261$1643_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2750$455_Y end - attribute \src "ls180.v:6263.46-6263.99" - cell $and $and$ls180.v:6263$1644 + attribute \src "ls180.v:2755.47-2755.82" + cell $eq $eq$ls180.v:2755$464 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6263$1644_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:2755$464_Y end - attribute \src "ls180.v:6263.45-6263.149" - cell $and $and$ls180.v:6263$1646 + attribute \src "ls180.v:2755.145-2755.183" + cell $eq $eq$ls180.v:2755$465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6263$1644_Y - connect \B $eq$ls180.v:6263$1645_Y - connect \Y $and$ls180.v:6263$1646_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2755$465_Y end - attribute \src "ls180.v:6264.46-6264.102" - cell $and $and$ls180.v:6264$1648 + attribute \src "ls180.v:2755.220-2755.258" + cell $eq $eq$ls180.v:2755$468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6264$1647_Y - connect \Y $and$ls180.v:6264$1648_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2755$468_Y end - attribute \src "ls180.v:6264.45-6264.152" - cell $and $and$ls180.v:6264$1650 + attribute \src "ls180.v:2755.295-2755.333" + cell $eq $eq$ls180.v:2755$471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6264$1648_Y - connect \B $eq$ls180.v:6264$1649_Y - connect \Y $and$ls180.v:6264$1650_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2755$471_Y end - attribute \src "ls180.v:6266.46-6266.99" - cell $and $and$ls180.v:6266$1651 + attribute \src "ls180.v:2760.39-2760.77" + cell $eq $eq$ls180.v:2760$480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6266$1651_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$480_Y end - attribute \src "ls180.v:6266.45-6266.149" - cell $and $and$ls180.v:6266$1653 + attribute \src "ls180.v:2760.83-2760.118" + cell $eq $eq$ls180.v:2760$481 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6266$1651_Y - connect \B $eq$ls180.v:6266$1652_Y - connect \Y $and$ls180.v:6266$1653_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:2760$481_Y end - attribute \src "ls180.v:6267.46-6267.102" - cell $and $and$ls180.v:6267$1655 + attribute \src "ls180.v:2760.181-2760.219" + cell $eq $eq$ls180.v:2760$482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6267$1654_Y - connect \Y $and$ls180.v:6267$1655_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$482_Y end - attribute \src "ls180.v:6267.45-6267.152" - cell $and $and$ls180.v:6267$1657 + attribute \src "ls180.v:2760.256-2760.294" + cell $eq $eq$ls180.v:2760$485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6267$1655_Y - connect \B $eq$ls180.v:6267$1656_Y - connect \Y $and$ls180.v:6267$1657_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$485_Y end - attribute \src "ls180.v:6269.46-6269.99" - cell $and $and$ls180.v:6269$1658 + attribute \src "ls180.v:2760.331-2760.369" + cell $eq $eq$ls180.v:2760$488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6269$1658_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$488_Y end - attribute \src "ls180.v:6269.45-6269.149" - cell $and $and$ls180.v:6269$1660 + attribute \src "ls180.v:2760.413-2760.451" + cell $eq $eq$ls180.v:2760$496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6269$1658_Y - connect \B $eq$ls180.v:6269$1659_Y - connect \Y $and$ls180.v:6269$1660_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$496_Y end - attribute \src "ls180.v:6270.46-6270.102" - cell $and $and$ls180.v:6270$1662 + attribute \src "ls180.v:2760.457-2760.492" + cell $eq $eq$ls180.v:2760$497 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6270$1661_Y - connect \Y $and$ls180.v:6270$1662_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:2760$497_Y end - attribute \src "ls180.v:6270.45-6270.152" - cell $and $and$ls180.v:6270$1664 + attribute \src "ls180.v:2760.555-2760.593" + cell $eq $eq$ls180.v:2760$498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6270$1662_Y - connect \B $eq$ls180.v:6270$1663_Y - connect \Y $and$ls180.v:6270$1664_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$498_Y end - attribute \src "ls180.v:6272.45-6272.98" - cell $and $and$ls180.v:6272$1665 + attribute \src "ls180.v:2760.630-2760.668" + cell $eq $eq$ls180.v:2760$501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6272$1665_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$501_Y end - attribute \src "ls180.v:6272.44-6272.148" - cell $and $and$ls180.v:6272$1667 + attribute \src "ls180.v:2760.705-2760.743" + cell $eq $eq$ls180.v:2760$504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6272$1665_Y - connect \B $eq$ls180.v:6272$1666_Y - connect \Y $and$ls180.v:6272$1667_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$504_Y end - attribute \src "ls180.v:6273.45-6273.101" - cell $and $and$ls180.v:6273$1669 + attribute \src "ls180.v:2760.787-2760.825" + cell $eq $eq$ls180.v:2760$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6273$1668_Y - connect \Y $and$ls180.v:6273$1669_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$512_Y end - attribute \src "ls180.v:6273.44-6273.151" - cell $and $and$ls180.v:6273$1671 + attribute \src "ls180.v:2760.831-2760.866" + cell $eq $eq$ls180.v:2760$513 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6273$1669_Y - connect \B $eq$ls180.v:6273$1670_Y - connect \Y $and$ls180.v:6273$1671_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:2760$513_Y end - attribute \src "ls180.v:6275.45-6275.98" - cell $and $and$ls180.v:6275$1672 + attribute \src "ls180.v:2760.929-2760.967" + cell $eq $eq$ls180.v:2760$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6275$1672_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$514_Y end - attribute \src "ls180.v:6275.44-6275.148" - cell $and $and$ls180.v:6275$1674 + attribute \src "ls180.v:2760.1004-2760.1042" + cell $eq $eq$ls180.v:2760$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6275$1672_Y - connect \B $eq$ls180.v:6275$1673_Y - connect \Y $and$ls180.v:6275$1674_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$517_Y end - attribute \src "ls180.v:6276.45-6276.101" - cell $and $and$ls180.v:6276$1676 + attribute \src "ls180.v:2760.1079-2760.1117" + cell $eq $eq$ls180.v:2760$520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6276$1675_Y - connect \Y $and$ls180.v:6276$1676_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$520_Y end - attribute \src "ls180.v:6276.44-6276.151" - cell $and $and$ls180.v:6276$1678 + attribute \src "ls180.v:2760.1161-2760.1199" + cell $eq $eq$ls180.v:2760$528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6276$1676_Y - connect \B $eq$ls180.v:6276$1677_Y - connect \Y $and$ls180.v:6276$1678_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$528_Y end - attribute \src "ls180.v:6278.45-6278.98" - cell $and $and$ls180.v:6278$1679 + attribute \src "ls180.v:2760.1205-2760.1240" + cell $eq $eq$ls180.v:2760$529 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6278$1679_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:2760$529_Y end - attribute \src "ls180.v:6278.44-6278.148" - cell $and $and$ls180.v:6278$1681 + attribute \src "ls180.v:2760.1303-2760.1341" + cell $eq $eq$ls180.v:2760$530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6278$1679_Y - connect \B $eq$ls180.v:6278$1680_Y - connect \Y $and$ls180.v:6278$1681_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$530_Y end - attribute \src "ls180.v:6279.45-6279.101" - cell $and $and$ls180.v:6279$1683 + attribute \src "ls180.v:2760.1378-2760.1416" + cell $eq $eq$ls180.v:2760$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6279$1682_Y - connect \Y $and$ls180.v:6279$1683_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$533_Y end - attribute \src "ls180.v:6279.44-6279.151" - cell $and $and$ls180.v:6279$1685 + attribute \src "ls180.v:2760.1453-2760.1491" + cell $eq $eq$ls180.v:2760$536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6279$1683_Y - connect \B $eq$ls180.v:6279$1684_Y - connect \Y $and$ls180.v:6279$1685_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2760$536_Y end - attribute \src "ls180.v:6281.45-6281.98" - cell $and $and$ls180.v:6281$1686 + attribute \src "ls180.v:2819.24-2819.47" + cell $eq $eq$ls180.v:2819$549 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6281$1686_Y + connect \A \litedram_wb_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2819$549_Y end - attribute \src "ls180.v:6281.44-6281.148" - cell $and $and$ls180.v:6281$1688 + attribute \src "ls180.v:2826.11-2826.36" + cell $eq $eq$ls180.v:2826$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6281$1686_Y - connect \B $eq$ls180.v:6281$1687_Y - connect \Y $and$ls180.v:6281$1688_Y + connect \A \converter_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2826$554_Y end - attribute \src "ls180.v:6282.45-6282.101" - cell $and $and$ls180.v:6282$1690 + attribute \src "ls180.v:3083.84-3083.109" + cell $eq $eq$ls180.v:3083$626 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6282$1689_Y - connect \Y $and$ls180.v:6282$1690_Y + connect \A \libresocsim_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3083$626_Y end - attribute \src "ls180.v:6282.44-6282.151" - cell $and $and$ls180.v:6282$1692 + attribute \src "ls180.v:3084.84-3084.109" + cell $eq $eq$ls180.v:3084$628 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6282$1690_Y - connect \B $eq$ls180.v:6282$1691_Y - connect \Y $and$ls180.v:6282$1692_Y + connect \A \libresocsim_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3084$628_Y end - attribute \src "ls180.v:6284.36-6284.89" - cell $and $and$ls180.v:6284$1693 + attribute \src "ls180.v:3085.84-3085.109" + cell $eq $eq$ls180.v:3085$630 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6284$1693_Y + connect \A \libresocsim_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3085$630_Y end - attribute \src "ls180.v:6284.35-6284.139" - cell $and $and$ls180.v:6284$1695 + attribute \src "ls180.v:3086.84-3086.109" + cell $eq $eq$ls180.v:3086$632 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6284$1693_Y - connect \B $eq$ls180.v:6284$1694_Y - connect \Y $and$ls180.v:6284$1695_Y + connect \A \libresocsim_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3086$632_Y end - attribute \src "ls180.v:6285.36-6285.92" - cell $and $and$ls180.v:6285$1697 + attribute \src "ls180.v:3087.84-3087.109" + cell $eq $eq$ls180.v:3087$634 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6285$1696_Y - connect \Y $and$ls180.v:6285$1697_Y + connect \A \libresocsim_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3087$634_Y end - attribute \src "ls180.v:6285.35-6285.142" - cell $and $and$ls180.v:6285$1699 + attribute \src "ls180.v:3088.84-3088.109" + cell $eq $eq$ls180.v:3088$636 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6285$1697_Y - connect \B $eq$ls180.v:6285$1698_Y - connect \Y $and$ls180.v:6285$1699_Y + connect \A \libresocsim_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3088$636_Y end - attribute \src "ls180.v:6287.47-6287.100" - cell $and $and$ls180.v:6287$1700 + attribute \src "ls180.v:3092.31-3092.67" + cell $eq $eq$ls180.v:3092$639 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 23 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6287$1700_Y + connect \A \libresocsim_shared_adr [29:7] + connect \B 1'0 + connect \Y $eq$ls180.v:3092$639_Y end - attribute \src "ls180.v:6287.46-6287.150" - cell $and $and$ls180.v:6287$1702 + attribute \src "ls180.v:3093.31-3093.68" + cell $eq $eq$ls180.v:3093$640 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 25 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6287$1700_Y - connect \B $eq$ls180.v:6287$1701_Y - connect \Y $and$ls180.v:6287$1702_Y + connect \A \libresocsim_shared_adr [29:5] + connect \B 4'1110 + connect \Y $eq$ls180.v:3093$640_Y end - attribute \src "ls180.v:6288.47-6288.103" - cell $and $and$ls180.v:6288$1704 + attribute \src "ls180.v:3094.31-3094.76" + cell $eq $eq$ls180.v:3094$641 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 27 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 27 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6288$1703_Y - connect \Y $and$ls180.v:6288$1704_Y + connect \A \libresocsim_shared_adr [29:3] + connect \B 27'110000000000000100000000000 + connect \Y $eq$ls180.v:3094$641_Y end - attribute \src "ls180.v:6288.46-6288.153" - cell $and $and$ls180.v:6288$1706 + attribute \src "ls180.v:3095.31-3095.74" + cell $eq $eq$ls180.v:3095$642 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 20 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 20 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6288$1704_Y - connect \B $eq$ls180.v:6288$1705_Y - connect \Y $and$ls180.v:6288$1706_Y + connect \A \libresocsim_shared_adr [29:10] + connect \B 20'11000000000000010001 + connect \Y $eq$ls180.v:3095$642_Y end - attribute \src "ls180.v:6290.47-6290.100" - cell $and $and$ls180.v:6290$1707 + attribute \src "ls180.v:3096.31-3096.69" + cell $eq $eq$ls180.v:3096$643 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6290$1707_Y + connect \A \libresocsim_shared_adr [29:23] + connect \B 7'1001000 + connect \Y $eq$ls180.v:3096$643_Y end - attribute \src "ls180.v:6290.46-6290.151" - cell $and $and$ls180.v:6290$1709 + attribute \src "ls180.v:3097.31-3097.73" + cell $eq $eq$ls180.v:3097$644 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 16 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 16 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6290$1707_Y - connect \B $eq$ls180.v:6290$1708_Y - connect \Y $and$ls180.v:6290$1709_Y + connect \A \libresocsim_shared_adr [29:14] + connect \B 16'1100000000000000 + connect \Y $eq$ls180.v:3097$644_Y end - attribute \src "ls180.v:6291.47-6291.103" - cell $and $and$ls180.v:6291$1711 + attribute \src "ls180.v:3161.28-3161.53" + cell $eq $eq$ls180.v:3161$676 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 20 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6291$1710_Y - connect \Y $and$ls180.v:6291$1711_Y + connect \A \libresocsim_count + connect \B 1'0 + connect \Y $eq$ls180.v:3161$676_Y end - attribute \src "ls180.v:6291.46-6291.154" - cell $and $and$ls180.v:6291$1713 + attribute \src "ls180.v:3162.36-3162.85" + cell $eq $eq$ls180.v:3162$677 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6291$1711_Y - connect \B $eq$ls180.v:6291$1712_Y - connect \Y $and$ls180.v:6291$1713_Y + connect \A \libresocsim_interface0_bank_bus_adr [13:9] + connect \B 1'0 + connect \Y $eq$ls180.v:3162$677_Y end - attribute \src "ls180.v:6293.47-6293.100" - cell $and $and$ls180.v:6293$1714 + attribute \src "ls180.v:3164.109-3164.157" + cell $eq $eq$ls180.v:3164$679 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6293$1714_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3164$679_Y end - attribute \src "ls180.v:6293.46-6293.151" - cell $and $and$ls180.v:6293$1716 + attribute \src "ls180.v:3165.112-3165.160" + cell $eq $eq$ls180.v:3165$683 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6293$1714_Y - connect \B $eq$ls180.v:6293$1715_Y - connect \Y $and$ls180.v:6293$1716_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3165$683_Y end - attribute \src "ls180.v:6294.47-6294.103" - cell $and $and$ls180.v:6294$1718 + attribute \src "ls180.v:3167.111-3167.159" + cell $eq $eq$ls180.v:3167$686 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6294$1717_Y - connect \Y $and$ls180.v:6294$1718_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3167$686_Y end - attribute \src "ls180.v:6294.46-6294.154" - cell $and $and$ls180.v:6294$1720 + attribute \src "ls180.v:3168.114-3168.162" + cell $eq $eq$ls180.v:3168$690 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6294$1718_Y - connect \B $eq$ls180.v:6294$1719_Y - connect \Y $and$ls180.v:6294$1720_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3168$690_Y end - attribute \src "ls180.v:6296.47-6296.100" - cell $and $and$ls180.v:6296$1721 + attribute \src "ls180.v:3170.111-3170.159" + cell $eq $eq$ls180.v:3170$693 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6296$1721_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3170$693_Y end - attribute \src "ls180.v:6296.46-6296.151" - cell $and $and$ls180.v:6296$1723 + attribute \src "ls180.v:3171.114-3171.162" + cell $eq $eq$ls180.v:3171$697 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6296$1721_Y - connect \B $eq$ls180.v:6296$1722_Y - connect \Y $and$ls180.v:6296$1723_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3171$697_Y end - attribute \src "ls180.v:6297.47-6297.103" - cell $and $and$ls180.v:6297$1725 + attribute \src "ls180.v:3173.111-3173.159" + cell $eq $eq$ls180.v:3173$700 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6297$1724_Y - connect \Y $and$ls180.v:6297$1725_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3173$700_Y end - attribute \src "ls180.v:6297.46-6297.154" - cell $and $and$ls180.v:6297$1727 + attribute \src "ls180.v:3174.114-3174.162" + cell $eq $eq$ls180.v:3174$704 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6297$1725_Y - connect \B $eq$ls180.v:6297$1726_Y - connect \Y $and$ls180.v:6297$1727_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3174$704_Y end - attribute \src "ls180.v:6299.47-6299.100" - cell $and $and$ls180.v:6299$1728 + attribute \src "ls180.v:3176.111-3176.159" + cell $eq $eq$ls180.v:3176$707 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6299$1728_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3176$707_Y end - attribute \src "ls180.v:6299.46-6299.151" - cell $and $and$ls180.v:6299$1730 + attribute \src "ls180.v:3177.114-3177.162" + cell $eq $eq$ls180.v:3177$711 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6299$1728_Y - connect \B $eq$ls180.v:6299$1729_Y - connect \Y $and$ls180.v:6299$1730_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3177$711_Y end - attribute \src "ls180.v:6300.47-6300.103" - cell $and $and$ls180.v:6300$1732 + attribute \src "ls180.v:3179.114-3179.162" + cell $eq $eq$ls180.v:3179$714 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6300$1731_Y - connect \Y $and$ls180.v:6300$1732_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3179$714_Y end - attribute \src "ls180.v:6300.46-6300.154" - cell $and $and$ls180.v:6300$1734 + attribute \src "ls180.v:3180.117-3180.165" + cell $eq $eq$ls180.v:3180$718 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6300$1732_Y - connect \B $eq$ls180.v:6300$1733_Y - connect \Y $and$ls180.v:6300$1734_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3180$718_Y end - attribute \src "ls180.v:6302.47-6302.100" - cell $and $and$ls180.v:6302$1735 + attribute \src "ls180.v:3182.114-3182.162" + cell $eq $eq$ls180.v:3182$721 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6302$1735_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3182$721_Y end - attribute \src "ls180.v:6302.46-6302.151" - cell $and $and$ls180.v:6302$1737 + attribute \src "ls180.v:3183.117-3183.165" + cell $eq $eq$ls180.v:3183$725 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6302$1735_Y - connect \B $eq$ls180.v:6302$1736_Y - connect \Y $and$ls180.v:6302$1737_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3183$725_Y end - attribute \src "ls180.v:6303.47-6303.103" - cell $and $and$ls180.v:6303$1739 + attribute \src "ls180.v:3185.114-3185.162" + cell $eq $eq$ls180.v:3185$728 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6303$1738_Y - connect \Y $and$ls180.v:6303$1739_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3185$728_Y end - attribute \src "ls180.v:6303.46-6303.154" - cell $and $and$ls180.v:6303$1741 + attribute \src "ls180.v:3186.117-3186.165" + cell $eq $eq$ls180.v:3186$732 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6303$1739_Y - connect \B $eq$ls180.v:6303$1740_Y - connect \Y $and$ls180.v:6303$1741_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3186$732_Y end - attribute \src "ls180.v:6305.46-6305.99" - cell $and $and$ls180.v:6305$1742 + attribute \src "ls180.v:3188.114-3188.162" + cell $eq $eq$ls180.v:3188$735 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6305$1742_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:3188$735_Y end - attribute \src "ls180.v:6305.45-6305.150" - cell $and $and$ls180.v:6305$1744 + attribute \src "ls180.v:3189.117-3189.165" + cell $eq $eq$ls180.v:3189$739 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6305$1742_Y - connect \B $eq$ls180.v:6305$1743_Y - connect \Y $and$ls180.v:6305$1744_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:3189$739_Y end - attribute \src "ls180.v:6306.46-6306.102" - cell $and $and$ls180.v:6306$1746 + attribute \src "ls180.v:3200.36-3200.85" + cell $eq $eq$ls180.v:3200$741 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6306$1745_Y - connect \Y $and$ls180.v:6306$1746_Y + connect \A \libresocsim_interface1_bank_bus_adr [13:9] + connect \B 3'110 + connect \Y $eq$ls180.v:3200$741_Y end - attribute \src "ls180.v:6306.45-6306.153" - cell $and $and$ls180.v:6306$1748 + attribute \src "ls180.v:3202.106-3202.154" + cell $eq $eq$ls180.v:3202$743 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6306$1746_Y - connect \B $eq$ls180.v:6306$1747_Y - connect \Y $and$ls180.v:6306$1748_Y + connect \A \libresocsim_interface1_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3202$743_Y end - attribute \src "ls180.v:6308.46-6308.99" - cell $and $and$ls180.v:6308$1749 + attribute \src "ls180.v:3203.109-3203.157" + cell $eq $eq$ls180.v:3203$747 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6308$1749_Y + connect \A \libresocsim_interface1_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3203$747_Y end - attribute \src "ls180.v:6308.45-6308.150" - cell $and $and$ls180.v:6308$1751 + attribute \src "ls180.v:3205.105-3205.153" + cell $eq $eq$ls180.v:3205$750 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6308$1749_Y - connect \B $eq$ls180.v:6308$1750_Y - connect \Y $and$ls180.v:6308$1751_Y + connect \A \libresocsim_interface1_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3205$750_Y end - attribute \src "ls180.v:6309.46-6309.102" - cell $and $and$ls180.v:6309$1753 + attribute \src "ls180.v:3206.108-3206.156" + cell $eq $eq$ls180.v:3206$754 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6309$1752_Y - connect \Y $and$ls180.v:6309$1753_Y + connect \A \libresocsim_interface1_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3206$754_Y end - attribute \src "ls180.v:6309.45-6309.153" - cell $and $and$ls180.v:6309$1755 + attribute \src "ls180.v:3208.107-3208.155" + cell $eq $eq$ls180.v:3208$757 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6309$1753_Y - connect \B $eq$ls180.v:6309$1754_Y - connect \Y $and$ls180.v:6309$1755_Y + connect \A \libresocsim_interface1_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3208$757_Y end - attribute \src "ls180.v:6311.46-6311.99" - cell $and $and$ls180.v:6311$1756 + attribute \src "ls180.v:3209.110-3209.158" + cell $eq $eq$ls180.v:3209$761 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6311$1756_Y + connect \A \libresocsim_interface1_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3209$761_Y end - attribute \src "ls180.v:6311.45-6311.150" - cell $and $and$ls180.v:6311$1758 + attribute \src "ls180.v:3214.36-3214.85" + cell $eq $eq$ls180.v:3214$763 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6311$1756_Y - connect \B $eq$ls180.v:6311$1757_Y - connect \Y $and$ls180.v:6311$1758_Y + connect \A \libresocsim_interface2_bank_bus_adr [13:9] + connect \B 3'111 + connect \Y $eq$ls180.v:3214$763_Y end - attribute \src "ls180.v:6312.46-6312.102" - cell $and $and$ls180.v:6312$1760 + attribute \src "ls180.v:3216.106-3216.154" + cell $eq $eq$ls180.v:3216$765 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6312$1759_Y - connect \Y $and$ls180.v:6312$1760_Y + connect \A \libresocsim_interface2_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3216$765_Y end - attribute \src "ls180.v:6312.45-6312.153" - cell $and $and$ls180.v:6312$1762 + attribute \src "ls180.v:3217.109-3217.157" + cell $eq $eq$ls180.v:3217$769 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6312$1760_Y - connect \B $eq$ls180.v:6312$1761_Y - connect \Y $and$ls180.v:6312$1762_Y + connect \A \libresocsim_interface2_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3217$769_Y end - attribute \src "ls180.v:6314.46-6314.99" - cell $and $and$ls180.v:6314$1763 + attribute \src "ls180.v:3219.105-3219.153" + cell $eq $eq$ls180.v:3219$772 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6314$1763_Y + connect \A \libresocsim_interface2_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3219$772_Y end - attribute \src "ls180.v:6314.45-6314.150" - cell $and $and$ls180.v:6314$1765 + attribute \src "ls180.v:3220.108-3220.156" + cell $eq $eq$ls180.v:3220$776 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6314$1763_Y - connect \B $eq$ls180.v:6314$1764_Y - connect \Y $and$ls180.v:6314$1765_Y + connect \A \libresocsim_interface2_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3220$776_Y end - attribute \src "ls180.v:6315.46-6315.102" - cell $and $and$ls180.v:6315$1767 + attribute \src "ls180.v:3222.107-3222.155" + cell $eq $eq$ls180.v:3222$779 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6315$1766_Y - connect \Y $and$ls180.v:6315$1767_Y + connect \A \libresocsim_interface2_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3222$779_Y end - attribute \src "ls180.v:6315.45-6315.153" - cell $and $and$ls180.v:6315$1769 + attribute \src "ls180.v:3223.110-3223.158" + cell $eq $eq$ls180.v:3223$783 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6315$1767_Y - connect \B $eq$ls180.v:6315$1768_Y - connect \Y $and$ls180.v:6315$1769_Y + connect \A \libresocsim_interface2_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3223$783_Y end - attribute \src "ls180.v:6317.46-6317.99" - cell $and $and$ls180.v:6317$1770 + attribute \src "ls180.v:3228.36-3228.85" + cell $eq $eq$ls180.v:3228$785 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6317$1770_Y + connect \A \libresocsim_interface3_bank_bus_adr [13:9] + connect \B 4'1000 + connect \Y $eq$ls180.v:3228$785_Y end - attribute \src "ls180.v:6317.45-6317.150" - cell $and $and$ls180.v:6317$1772 + attribute \src "ls180.v:3230.105-3230.151" + cell $eq $eq$ls180.v:3230$787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6317$1770_Y - connect \B $eq$ls180.v:6317$1771_Y - connect \Y $and$ls180.v:6317$1772_Y + connect \A \libresocsim_interface3_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:3230$787_Y end - attribute \src "ls180.v:6318.46-6318.102" - cell $and $and$ls180.v:6318$1774 + attribute \src "ls180.v:3231.108-3231.154" + cell $eq $eq$ls180.v:3231$791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6318$1773_Y - connect \Y $and$ls180.v:6318$1774_Y + connect \A \libresocsim_interface3_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:3231$791_Y end - attribute \src "ls180.v:6318.45-6318.153" - cell $and $and$ls180.v:6318$1776 + attribute \src "ls180.v:3233.104-3233.150" + cell $eq $eq$ls180.v:3233$794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6318$1774_Y - connect \B $eq$ls180.v:6318$1775_Y - connect \Y $and$ls180.v:6318$1776_Y + connect \A \libresocsim_interface3_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:3233$794_Y end - attribute \src "ls180.v:6320.46-6320.99" - cell $and $and$ls180.v:6320$1777 + attribute \src "ls180.v:3234.107-3234.153" + cell $eq $eq$ls180.v:3234$798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6320$1777_Y + connect \A \libresocsim_interface3_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:3234$798_Y end - attribute \src "ls180.v:6320.45-6320.150" - cell $and $and$ls180.v:6320$1779 + attribute \src "ls180.v:3242.36-3242.85" + cell $eq $eq$ls180.v:3242$800 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6320$1777_Y - connect \B $eq$ls180.v:6320$1778_Y - connect \Y $and$ls180.v:6320$1779_Y + connect \A \libresocsim_interface4_bank_bus_adr [13:9] + connect \B 2'11 + connect \Y $eq$ls180.v:3242$800_Y end - attribute \src "ls180.v:6321.46-6321.102" - cell $and $and$ls180.v:6321$1781 + attribute \src "ls180.v:3244.116-3244.164" + cell $eq $eq$ls180.v:3244$802 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6321$1780_Y - connect \Y $and$ls180.v:6321$1781_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3244$802_Y end - attribute \src "ls180.v:6321.45-6321.153" - cell $and $and$ls180.v:6321$1783 + attribute \src "ls180.v:3245.119-3245.167" + cell $eq $eq$ls180.v:3245$806 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6321$1781_Y - connect \B $eq$ls180.v:6321$1782_Y - connect \Y $and$ls180.v:6321$1783_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3245$806_Y end - attribute \src "ls180.v:6323.46-6323.99" - cell $and $and$ls180.v:6323$1784 + attribute \src "ls180.v:3247.120-3247.168" + cell $eq $eq$ls180.v:3247$809 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6323$1784_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3247$809_Y end - attribute \src "ls180.v:6323.45-6323.150" - cell $and $and$ls180.v:6323$1786 + attribute \src "ls180.v:3248.123-3248.171" + cell $eq $eq$ls180.v:3248$813 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6323$1784_Y - connect \B $eq$ls180.v:6323$1785_Y - connect \Y $and$ls180.v:6323$1786_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3248$813_Y end - attribute \src "ls180.v:6324.46-6324.102" - cell $and $and$ls180.v:6324$1788 + attribute \src "ls180.v:3250.101-3250.149" + cell $eq $eq$ls180.v:3250$816 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6324$1787_Y - connect \Y $and$ls180.v:6324$1788_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3250$816_Y end - attribute \src "ls180.v:6324.45-6324.153" - cell $and $and$ls180.v:6324$1790 + attribute \src "ls180.v:3251.104-3251.152" + cell $eq $eq$ls180.v:3251$820 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6324$1788_Y - connect \B $eq$ls180.v:6324$1789_Y - connect \Y $and$ls180.v:6324$1790_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3251$820_Y end - attribute \src "ls180.v:6326.46-6326.99" - cell $and $and$ls180.v:6326$1791 + attribute \src "ls180.v:3253.120-3253.168" + cell $eq $eq$ls180.v:3253$823 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6326$1791_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3253$823_Y end - attribute \src "ls180.v:6326.45-6326.150" - cell $and $and$ls180.v:6326$1793 + attribute \src "ls180.v:3254.123-3254.171" + cell $eq $eq$ls180.v:3254$827 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6326$1791_Y - connect \B $eq$ls180.v:6326$1792_Y - connect \Y $and$ls180.v:6326$1793_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3254$827_Y end - attribute \src "ls180.v:6327.46-6327.102" - cell $and $and$ls180.v:6327$1795 + attribute \src "ls180.v:3256.120-3256.168" + cell $eq $eq$ls180.v:3256$830 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6327$1794_Y - connect \Y $and$ls180.v:6327$1795_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3256$830_Y end - attribute \src "ls180.v:6327.45-6327.153" - cell $and $and$ls180.v:6327$1797 + attribute \src "ls180.v:3257.123-3257.171" + cell $eq $eq$ls180.v:3257$834 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6327$1795_Y - connect \B $eq$ls180.v:6327$1796_Y - connect \Y $and$ls180.v:6327$1797_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3257$834_Y end - attribute \src "ls180.v:6329.46-6329.99" - cell $and $and$ls180.v:6329$1798 + attribute \src "ls180.v:3259.121-3259.169" + cell $eq $eq$ls180.v:3259$837 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6329$1798_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3259$837_Y end - attribute \src "ls180.v:6329.45-6329.150" - cell $and $and$ls180.v:6329$1800 + attribute \src "ls180.v:3260.124-3260.172" + cell $eq $eq$ls180.v:3260$841 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6329$1798_Y - connect \B $eq$ls180.v:6329$1799_Y - connect \Y $and$ls180.v:6329$1800_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3260$841_Y end - attribute \src "ls180.v:6330.46-6330.102" - cell $and $and$ls180.v:6330$1802 + attribute \src "ls180.v:3262.119-3262.167" + cell $eq $eq$ls180.v:3262$844 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6330$1801_Y - connect \Y $and$ls180.v:6330$1802_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3262$844_Y end - attribute \src "ls180.v:6330.45-6330.153" - cell $and $and$ls180.v:6330$1804 + attribute \src "ls180.v:3263.122-3263.170" + cell $eq $eq$ls180.v:3263$848 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6330$1802_Y - connect \B $eq$ls180.v:6330$1803_Y - connect \Y $and$ls180.v:6330$1804_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3263$848_Y end - attribute \src "ls180.v:6332.46-6332.99" - cell $and $and$ls180.v:6332$1805 + attribute \src "ls180.v:3265.119-3265.167" + cell $eq $eq$ls180.v:3265$851 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6332$1805_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3265$851_Y end - attribute \src "ls180.v:6332.45-6332.150" - cell $and $and$ls180.v:6332$1807 + attribute \src "ls180.v:3266.122-3266.170" + cell $eq $eq$ls180.v:3266$855 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6332$1805_Y - connect \B $eq$ls180.v:6332$1806_Y - connect \Y $and$ls180.v:6332$1807_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3266$855_Y end - attribute \src "ls180.v:6333.46-6333.102" - cell $and $and$ls180.v:6333$1809 + attribute \src "ls180.v:3268.119-3268.167" + cell $eq $eq$ls180.v:3268$858 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6333$1808_Y - connect \Y $and$ls180.v:6333$1809_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:3268$858_Y end - attribute \src "ls180.v:6333.45-6333.153" - cell $and $and$ls180.v:6333$1811 + attribute \src "ls180.v:3269.122-3269.170" + cell $eq $eq$ls180.v:3269$862 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6333$1809_Y - connect \B $eq$ls180.v:6333$1810_Y - connect \Y $and$ls180.v:6333$1811_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:3269$862_Y end - attribute \src "ls180.v:6335.42-6335.95" - cell $and $and$ls180.v:6335$1812 + attribute \src "ls180.v:3271.119-3271.167" + cell $eq $eq$ls180.v:3271$865 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6335$1812_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:3271$865_Y end - attribute \src "ls180.v:6335.41-6335.146" - cell $and $and$ls180.v:6335$1814 + attribute \src "ls180.v:3272.122-3272.170" + cell $eq $eq$ls180.v:3272$869 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6335$1812_Y - connect \B $eq$ls180.v:6335$1813_Y - connect \Y $and$ls180.v:6335$1814_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:3272$869_Y end - attribute \src "ls180.v:6336.42-6336.98" - cell $and $and$ls180.v:6336$1816 + attribute \src "ls180.v:3287.36-3287.85" + cell $eq $eq$ls180.v:3287$871 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6336$1815_Y - connect \Y $and$ls180.v:6336$1816_Y + connect \A \libresocsim_interface5_bank_bus_adr [13:9] + connect \B 2'10 + connect \Y $eq$ls180.v:3287$871_Y end - attribute \src "ls180.v:6336.41-6336.149" - cell $and $and$ls180.v:6336$1818 + attribute \src "ls180.v:3289.108-3289.156" + cell $eq $eq$ls180.v:3289$873 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6336$1816_Y - connect \B $eq$ls180.v:6336$1817_Y - connect \Y $and$ls180.v:6336$1818_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3289$873_Y end - attribute \src "ls180.v:6338.43-6338.96" - cell $and $and$ls180.v:6338$1819 + attribute \src "ls180.v:3290.111-3290.159" + cell $eq $eq$ls180.v:3290$877 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6338$1819_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3290$877_Y end - attribute \src "ls180.v:6338.42-6338.147" - cell $and $and$ls180.v:6338$1821 + attribute \src "ls180.v:3292.108-3292.156" + cell $eq $eq$ls180.v:3292$880 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6338$1819_Y - connect \B $eq$ls180.v:6338$1820_Y - connect \Y $and$ls180.v:6338$1821_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3292$880_Y end - attribute \src "ls180.v:6339.43-6339.99" - cell $and $and$ls180.v:6339$1823 + attribute \src "ls180.v:3293.111-3293.159" + cell $eq $eq$ls180.v:3293$884 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6339$1822_Y - connect \Y $and$ls180.v:6339$1823_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3293$884_Y end - attribute \src "ls180.v:6339.42-6339.150" - cell $and $and$ls180.v:6339$1825 + attribute \src "ls180.v:3295.108-3295.156" + cell $eq $eq$ls180.v:3295$887 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6339$1823_Y - connect \B $eq$ls180.v:6339$1824_Y - connect \Y $and$ls180.v:6339$1825_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3295$887_Y end - attribute \src "ls180.v:6341.46-6341.99" - cell $and $and$ls180.v:6341$1826 + attribute \src "ls180.v:3296.111-3296.159" + cell $eq $eq$ls180.v:3296$891 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6341$1826_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3296$891_Y end - attribute \src "ls180.v:6341.45-6341.150" - cell $and $and$ls180.v:6341$1828 + attribute \src "ls180.v:3298.108-3298.156" + cell $eq $eq$ls180.v:3298$894 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6341$1826_Y - connect \B $eq$ls180.v:6341$1827_Y - connect \Y $and$ls180.v:6341$1828_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3298$894_Y end - attribute \src "ls180.v:6342.46-6342.102" - cell $and $and$ls180.v:6342$1830 + attribute \src "ls180.v:3299.111-3299.159" + cell $eq $eq$ls180.v:3299$898 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6342$1829_Y - connect \Y $and$ls180.v:6342$1830_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3299$898_Y end - attribute \src "ls180.v:6342.45-6342.153" - cell $and $and$ls180.v:6342$1832 + attribute \src "ls180.v:3301.110-3301.158" + cell $eq $eq$ls180.v:3301$901 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6342$1830_Y - connect \B $eq$ls180.v:6342$1831_Y - connect \Y $and$ls180.v:6342$1832_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3301$901_Y end - attribute \src "ls180.v:6344.46-6344.99" - cell $and $and$ls180.v:6344$1833 + attribute \src "ls180.v:3302.113-3302.161" + cell $eq $eq$ls180.v:3302$905 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6344$1833_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3302$905_Y end - attribute \src "ls180.v:6344.45-6344.150" - cell $and $and$ls180.v:6344$1835 + attribute \src "ls180.v:3304.110-3304.158" + cell $eq $eq$ls180.v:3304$908 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6344$1833_Y - connect \B $eq$ls180.v:6344$1834_Y - connect \Y $and$ls180.v:6344$1835_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3304$908_Y end - attribute \src "ls180.v:6345.46-6345.102" - cell $and $and$ls180.v:6345$1837 + attribute \src "ls180.v:3305.113-3305.161" + cell $eq $eq$ls180.v:3305$912 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6345$1836_Y - connect \Y $and$ls180.v:6345$1837_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3305$912_Y end - attribute \src "ls180.v:6345.45-6345.153" - cell $and $and$ls180.v:6345$1839 + attribute \src "ls180.v:3307.110-3307.158" + cell $eq $eq$ls180.v:3307$915 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6345$1837_Y - connect \B $eq$ls180.v:6345$1838_Y - connect \Y $and$ls180.v:6345$1839_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3307$915_Y end - attribute \src "ls180.v:6347.45-6347.98" - cell $and $and$ls180.v:6347$1840 + attribute \src "ls180.v:3308.113-3308.161" + cell $eq $eq$ls180.v:3308$919 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6347$1840_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3308$919_Y end - attribute \src "ls180.v:6347.44-6347.149" - cell $and $and$ls180.v:6347$1842 + attribute \src "ls180.v:3310.110-3310.158" + cell $eq $eq$ls180.v:3310$922 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6347$1840_Y - connect \B $eq$ls180.v:6347$1841_Y - connect \Y $and$ls180.v:6347$1842_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3310$922_Y end - attribute \src "ls180.v:6348.45-6348.101" - cell $and $and$ls180.v:6348$1844 + attribute \src "ls180.v:3311.113-3311.161" + cell $eq $eq$ls180.v:3311$926 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6348$1843_Y - connect \Y $and$ls180.v:6348$1844_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3311$926_Y end - attribute \src "ls180.v:6348.44-6348.152" - cell $and $and$ls180.v:6348$1846 + attribute \src "ls180.v:3313.106-3313.154" + cell $eq $eq$ls180.v:3313$929 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6348$1844_Y - connect \B $eq$ls180.v:6348$1845_Y - connect \Y $and$ls180.v:6348$1846_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:3313$929_Y end - attribute \src "ls180.v:6350.45-6350.98" - cell $and $and$ls180.v:6350$1847 + attribute \src "ls180.v:3314.109-3314.157" + cell $eq $eq$ls180.v:3314$933 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6350$1847_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:3314$933_Y end - attribute \src "ls180.v:6350.44-6350.149" - cell $and $and$ls180.v:6350$1849 + attribute \src "ls180.v:3316.116-3316.164" + cell $eq $eq$ls180.v:3316$936 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6350$1847_Y - connect \B $eq$ls180.v:6350$1848_Y - connect \Y $and$ls180.v:6350$1849_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:3316$936_Y end - attribute \src "ls180.v:6351.45-6351.101" - cell $and $and$ls180.v:6351$1851 + attribute \src "ls180.v:3317.119-3317.167" + cell $eq $eq$ls180.v:3317$940 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6351$1850_Y - connect \Y $and$ls180.v:6351$1851_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:3317$940_Y end - attribute \src "ls180.v:6351.44-6351.152" - cell $and $and$ls180.v:6351$1853 + attribute \src "ls180.v:3319.109-3319.158" + cell $eq $eq$ls180.v:3319$943 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6351$1851_Y - connect \B $eq$ls180.v:6351$1852_Y - connect \Y $and$ls180.v:6351$1853_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:3319$943_Y end - attribute \src "ls180.v:6353.45-6353.98" - cell $and $and$ls180.v:6353$1854 + attribute \src "ls180.v:3320.112-3320.161" + cell $eq $eq$ls180.v:3320$947 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6353$1854_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:3320$947_Y end - attribute \src "ls180.v:6353.44-6353.149" - cell $and $and$ls180.v:6353$1856 + attribute \src "ls180.v:3322.109-3322.158" + cell $eq $eq$ls180.v:3322$950 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6353$1854_Y - connect \B $eq$ls180.v:6353$1855_Y - connect \Y $and$ls180.v:6353$1856_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:3322$950_Y end - attribute \src "ls180.v:6354.45-6354.101" - cell $and $and$ls180.v:6354$1858 + attribute \src "ls180.v:3323.112-3323.161" + cell $eq $eq$ls180.v:3323$954 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6354$1857_Y - connect \Y $and$ls180.v:6354$1858_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:3323$954_Y end - attribute \src "ls180.v:6354.44-6354.152" - cell $and $and$ls180.v:6354$1860 + attribute \src "ls180.v:3325.109-3325.158" + cell $eq $eq$ls180.v:3325$957 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6354$1858_Y - connect \B $eq$ls180.v:6354$1859_Y - connect \Y $and$ls180.v:6354$1860_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:3325$957_Y end - attribute \src "ls180.v:6356.45-6356.98" - cell $and $and$ls180.v:6356$1861 + attribute \src "ls180.v:3326.112-3326.161" + cell $eq $eq$ls180.v:3326$961 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6356$1861_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:3326$961_Y end - attribute \src "ls180.v:6356.44-6356.149" - cell $and $and$ls180.v:6356$1863 + attribute \src "ls180.v:3328.109-3328.158" + cell $eq $eq$ls180.v:3328$964 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6356$1861_Y - connect \B $eq$ls180.v:6356$1862_Y - connect \Y $and$ls180.v:6356$1863_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:3328$964_Y end - attribute \src "ls180.v:6357.45-6357.101" - cell $and $and$ls180.v:6357$1865 + attribute \src "ls180.v:3329.112-3329.161" + cell $eq $eq$ls180.v:3329$968 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6357$1864_Y - connect \Y $and$ls180.v:6357$1865_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:3329$968_Y end - attribute \src "ls180.v:6357.44-6357.152" - cell $and $and$ls180.v:6357$1867 + attribute \src "ls180.v:3331.113-3331.162" + cell $eq $eq$ls180.v:3331$971 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6357$1865_Y - connect \B $eq$ls180.v:6357$1866_Y - connect \Y $and$ls180.v:6357$1867_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:3331$971_Y end - attribute \src "ls180.v:6395.42-6395.95" - cell $and $and$ls180.v:6395$1869 + attribute \src "ls180.v:3332.116-3332.165" + cell $eq $eq$ls180.v:3332$975 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6395$1869_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:3332$975_Y end - attribute \src "ls180.v:6395.41-6395.145" - cell $and $and$ls180.v:6395$1871 + attribute \src "ls180.v:3334.114-3334.163" + cell $eq $eq$ls180.v:3334$978 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6395$1869_Y - connect \B $eq$ls180.v:6395$1870_Y - connect \Y $and$ls180.v:6395$1871_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:3334$978_Y end - attribute \src "ls180.v:6396.42-6396.98" - cell $and $and$ls180.v:6396$1873 + attribute \src "ls180.v:3335.117-3335.166" + cell $eq $eq$ls180.v:3335$982 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6396$1872_Y - connect \Y $and$ls180.v:6396$1873_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:3335$982_Y end - attribute \src "ls180.v:6396.41-6396.148" - cell $and $and$ls180.v:6396$1875 + attribute \src "ls180.v:3337.113-3337.162" + cell $eq $eq$ls180.v:3337$985 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6396$1873_Y - connect \B $eq$ls180.v:6396$1874_Y - connect \Y $and$ls180.v:6396$1875_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:3337$985_Y end - attribute \src "ls180.v:6398.42-6398.95" - cell $and $and$ls180.v:6398$1876 + attribute \src "ls180.v:3338.116-3338.165" + cell $eq $eq$ls180.v:3338$989 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6398$1876_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:3338$989_Y end - attribute \src "ls180.v:6398.41-6398.145" - cell $and $and$ls180.v:6398$1878 + attribute \src "ls180.v:3355.36-3355.85" + cell $eq $eq$ls180.v:3355$991 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6398$1876_Y - connect \B $eq$ls180.v:6398$1877_Y - connect \Y $and$ls180.v:6398$1878_Y + connect \A \libresocsim_interface6_bank_bus_adr [13:9] + connect \B 3'101 + connect \Y $eq$ls180.v:3355$991_Y end - attribute \src "ls180.v:6399.42-6399.98" - cell $and $and$ls180.v:6399$1880 + attribute \src "ls180.v:3357.86-3357.134" + cell $eq $eq$ls180.v:3357$993 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6399$1879_Y - connect \Y $and$ls180.v:6399$1880_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3357$993_Y end - attribute \src "ls180.v:6399.41-6399.148" - cell $and $and$ls180.v:6399$1882 + attribute \src "ls180.v:3358.89-3358.137" + cell $eq $eq$ls180.v:3358$997 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6399$1880_Y - connect \B $eq$ls180.v:6399$1881_Y - connect \Y $and$ls180.v:6399$1882_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3358$997_Y end - attribute \src "ls180.v:6401.42-6401.95" - cell $and $and$ls180.v:6401$1883 + attribute \src "ls180.v:3360.109-3360.157" + cell $eq $eq$ls180.v:3360$1000 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6401$1883_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3360$1000_Y end - attribute \src "ls180.v:6401.41-6401.145" - cell $and $and$ls180.v:6401$1885 + attribute \src "ls180.v:3361.112-3361.160" + cell $eq $eq$ls180.v:3361$1004 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6401$1883_Y - connect \B $eq$ls180.v:6401$1884_Y - connect \Y $and$ls180.v:6401$1885_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3361$1004_Y end - attribute \src "ls180.v:6402.42-6402.98" - cell $and $and$ls180.v:6402$1887 + attribute \src "ls180.v:3363.110-3363.158" + cell $eq $eq$ls180.v:3363$1007 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6402$1886_Y - connect \Y $and$ls180.v:6402$1887_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3363$1007_Y end - attribute \src "ls180.v:6402.41-6402.148" - cell $and $and$ls180.v:6402$1889 + attribute \src "ls180.v:3364.113-3364.161" + cell $eq $eq$ls180.v:3364$1011 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6402$1887_Y - connect \B $eq$ls180.v:6402$1888_Y - connect \Y $and$ls180.v:6402$1889_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3364$1011_Y end - attribute \src "ls180.v:6404.42-6404.95" - cell $and $and$ls180.v:6404$1890 + attribute \src "ls180.v:3366.101-3366.149" + cell $eq $eq$ls180.v:3366$1014 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6404$1890_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3366$1014_Y end - attribute \src "ls180.v:6404.41-6404.145" - cell $and $and$ls180.v:6404$1892 + attribute \src "ls180.v:3367.104-3367.152" + cell $eq $eq$ls180.v:3367$1018 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6404$1890_Y - connect \B $eq$ls180.v:6404$1891_Y - connect \Y $and$ls180.v:6404$1892_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3367$1018_Y end - attribute \src "ls180.v:6405.42-6405.98" - cell $and $and$ls180.v:6405$1894 + attribute \src "ls180.v:3369.102-3369.150" + cell $eq $eq$ls180.v:3369$1021 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6405$1893_Y - connect \Y $and$ls180.v:6405$1894_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3369$1021_Y end - attribute \src "ls180.v:6405.41-6405.148" - cell $and $and$ls180.v:6405$1896 + attribute \src "ls180.v:3370.105-3370.153" + cell $eq $eq$ls180.v:3370$1025 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6405$1894_Y - connect \B $eq$ls180.v:6405$1895_Y - connect \Y $and$ls180.v:6405$1896_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3370$1025_Y end - attribute \src "ls180.v:6407.42-6407.95" - cell $and $and$ls180.v:6407$1897 + attribute \src "ls180.v:3372.113-3372.161" + cell $eq $eq$ls180.v:3372$1028 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6407$1897_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3372$1028_Y end - attribute \src "ls180.v:6407.41-6407.145" - cell $and $and$ls180.v:6407$1899 + attribute \src "ls180.v:3373.116-3373.164" + cell $eq $eq$ls180.v:3373$1032 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6407$1897_Y - connect \B $eq$ls180.v:6407$1898_Y - connect \Y $and$ls180.v:6407$1899_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3373$1032_Y end - attribute \src "ls180.v:6408.42-6408.98" - cell $and $and$ls180.v:6408$1901 + attribute \src "ls180.v:3375.110-3375.158" + cell $eq $eq$ls180.v:3375$1035 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6408$1900_Y - connect \Y $and$ls180.v:6408$1901_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3375$1035_Y end - attribute \src "ls180.v:6408.41-6408.148" - cell $and $and$ls180.v:6408$1903 + attribute \src "ls180.v:3376.113-3376.161" + cell $eq $eq$ls180.v:3376$1039 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6408$1901_Y - connect \B $eq$ls180.v:6408$1902_Y - connect \Y $and$ls180.v:6408$1903_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3376$1039_Y end - attribute \src "ls180.v:6410.42-6410.95" - cell $and $and$ls180.v:6410$1904 + attribute \src "ls180.v:3378.109-3378.157" + cell $eq $eq$ls180.v:3378$1042 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6410$1904_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3378$1042_Y end - attribute \src "ls180.v:6410.41-6410.145" - cell $and $and$ls180.v:6410$1906 + attribute \src "ls180.v:3379.112-3379.160" + cell $eq $eq$ls180.v:3379$1046 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6410$1904_Y - connect \B $eq$ls180.v:6410$1905_Y - connect \Y $and$ls180.v:6410$1906_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3379$1046_Y end - attribute \src "ls180.v:6411.42-6411.98" - cell $and $and$ls180.v:6411$1908 + attribute \src "ls180.v:3389.36-3389.85" + cell $eq $eq$ls180.v:3389$1048 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6411$1907_Y - connect \Y $and$ls180.v:6411$1908_Y + connect \A \libresocsim_interface7_bank_bus_adr [13:9] + connect \B 3'100 + connect \Y $eq$ls180.v:3389$1048_Y end - attribute \src "ls180.v:6411.41-6411.148" - cell $and $and$ls180.v:6411$1910 + attribute \src "ls180.v:3391.115-3391.163" + cell $eq $eq$ls180.v:3391$1050 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6411$1908_Y - connect \B $eq$ls180.v:6411$1909_Y - connect \Y $and$ls180.v:6411$1910_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3391$1050_Y end - attribute \src "ls180.v:6413.42-6413.95" - cell $and $and$ls180.v:6413$1911 + attribute \src "ls180.v:3392.118-3392.166" + cell $eq $eq$ls180.v:3392$1054 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6413$1911_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3392$1054_Y end - attribute \src "ls180.v:6413.41-6413.145" - cell $and $and$ls180.v:6413$1913 + attribute \src "ls180.v:3394.115-3394.163" + cell $eq $eq$ls180.v:3394$1057 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6413$1911_Y - connect \B $eq$ls180.v:6413$1912_Y - connect \Y $and$ls180.v:6413$1913_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3394$1057_Y end - attribute \src "ls180.v:6414.42-6414.98" - cell $and $and$ls180.v:6414$1915 + attribute \src "ls180.v:3395.118-3395.166" + cell $eq $eq$ls180.v:3395$1061 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6414$1914_Y - connect \Y $and$ls180.v:6414$1915_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3395$1061_Y end - attribute \src "ls180.v:6414.41-6414.148" - cell $and $and$ls180.v:6414$1917 + attribute \src "ls180.v:3397.115-3397.163" + cell $eq $eq$ls180.v:3397$1064 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6414$1915_Y - connect \B $eq$ls180.v:6414$1916_Y - connect \Y $and$ls180.v:6414$1917_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3397$1064_Y end - attribute \src "ls180.v:6416.42-6416.95" - cell $and $and$ls180.v:6416$1918 + attribute \src "ls180.v:3398.118-3398.166" + cell $eq $eq$ls180.v:3398$1068 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6416$1918_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3398$1068_Y end - attribute \src "ls180.v:6416.41-6416.145" - cell $and $and$ls180.v:6416$1920 + attribute \src "ls180.v:3400.115-3400.163" + cell $eq $eq$ls180.v:3400$1071 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6416$1918_Y - connect \B $eq$ls180.v:6416$1919_Y - connect \Y $and$ls180.v:6416$1920_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3400$1071_Y end - attribute \src "ls180.v:6417.42-6417.98" - cell $and $and$ls180.v:6417$1922 + attribute \src "ls180.v:3401.118-3401.166" + cell $eq $eq$ls180.v:3401$1075 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6417$1921_Y - connect \Y $and$ls180.v:6417$1922_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3401$1075_Y end - attribute \src "ls180.v:6417.41-6417.148" - cell $and $and$ls180.v:6417$1924 + attribute \src "ls180.v:3761.28-3761.63" + cell $eq $eq$ls180.v:3761$1105 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6417$1922_Y - connect \B $eq$ls180.v:6417$1923_Y - connect \Y $and$ls180.v:6417$1924_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:3761$1105_Y end - attribute \src "ls180.v:6419.44-6419.97" - cell $and $and$ls180.v:6419$1925 + attribute \src "ls180.v:3761.126-3761.164" + cell $eq $eq$ls180.v:3761$1106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6419$1925_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3761$1106_Y end - attribute \src "ls180.v:6419.43-6419.147" - cell $and $and$ls180.v:6419$1927 + attribute \src "ls180.v:3761.201-3761.239" + cell $eq $eq$ls180.v:3761$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6419$1925_Y - connect \B $eq$ls180.v:6419$1926_Y - connect \Y $and$ls180.v:6419$1927_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3761$1109_Y end - attribute \src "ls180.v:6420.44-6420.100" - cell $and $and$ls180.v:6420$1929 + attribute \src "ls180.v:3761.276-3761.314" + cell $eq $eq$ls180.v:3761$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6420$1928_Y - connect \Y $and$ls180.v:6420$1929_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3761$1112_Y end - attribute \src "ls180.v:6420.43-6420.150" - cell $and $and$ls180.v:6420$1931 + attribute \src "ls180.v:3785.28-3785.63" + cell $eq $eq$ls180.v:3785$1121 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6420$1929_Y - connect \B $eq$ls180.v:6420$1930_Y - connect \Y $and$ls180.v:6420$1931_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:3785$1121_Y end - attribute \src "ls180.v:6422.44-6422.97" - cell $and $and$ls180.v:6422$1932 + attribute \src "ls180.v:3785.126-3785.164" + cell $eq $eq$ls180.v:3785$1122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6422$1932_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3785$1122_Y end - attribute \src "ls180.v:6422.43-6422.147" - cell $and $and$ls180.v:6422$1934 + attribute \src "ls180.v:3785.201-3785.239" + cell $eq $eq$ls180.v:3785$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6422$1932_Y - connect \B $eq$ls180.v:6422$1933_Y - connect \Y $and$ls180.v:6422$1934_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3785$1125_Y end - attribute \src "ls180.v:6423.44-6423.100" - cell $and $and$ls180.v:6423$1936 + attribute \src "ls180.v:3785.276-3785.314" + cell $eq $eq$ls180.v:3785$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6423$1935_Y - connect \Y $and$ls180.v:6423$1936_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3785$1128_Y end - attribute \src "ls180.v:6423.43-6423.150" - cell $and $and$ls180.v:6423$1938 + attribute \src "ls180.v:3809.28-3809.63" + cell $eq $eq$ls180.v:3809$1137 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6423$1936_Y - connect \B $eq$ls180.v:6423$1937_Y - connect \Y $and$ls180.v:6423$1938_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:3809$1137_Y end - attribute \src "ls180.v:6425.44-6425.97" - cell $and $and$ls180.v:6425$1939 + attribute \src "ls180.v:3809.126-3809.164" + cell $eq $eq$ls180.v:3809$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6425$1939_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3809$1138_Y end - attribute \src "ls180.v:6425.43-6425.148" - cell $and $and$ls180.v:6425$1941 + attribute \src "ls180.v:3809.201-3809.239" + cell $eq $eq$ls180.v:3809$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6425$1939_Y - connect \B $eq$ls180.v:6425$1940_Y - connect \Y $and$ls180.v:6425$1941_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3809$1141_Y end - attribute \src "ls180.v:6426.44-6426.100" - cell $and $and$ls180.v:6426$1943 + attribute \src "ls180.v:3809.276-3809.314" + cell $eq $eq$ls180.v:3809$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6426$1942_Y - connect \Y $and$ls180.v:6426$1943_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3809$1144_Y end - attribute \src "ls180.v:6426.43-6426.151" - cell $and $and$ls180.v:6426$1945 + attribute \src "ls180.v:3833.28-3833.63" + cell $eq $eq$ls180.v:3833$1153 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6426$1943_Y - connect \B $eq$ls180.v:6426$1944_Y - connect \Y $and$ls180.v:6426$1945_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:3833$1153_Y end - attribute \src "ls180.v:6428.44-6428.97" - cell $and $and$ls180.v:6428$1946 + attribute \src "ls180.v:3833.126-3833.164" + cell $eq $eq$ls180.v:3833$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6428$1946_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3833$1154_Y end - attribute \src "ls180.v:6428.43-6428.148" - cell $and $and$ls180.v:6428$1948 + attribute \src "ls180.v:3833.201-3833.239" + cell $eq $eq$ls180.v:3833$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6428$1946_Y - connect \B $eq$ls180.v:6428$1947_Y - connect \Y $and$ls180.v:6428$1948_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3833$1157_Y end - attribute \src "ls180.v:6429.44-6429.100" - cell $and $and$ls180.v:6429$1950 + attribute \src "ls180.v:3833.276-3833.314" + cell $eq $eq$ls180.v:3833$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6429$1949_Y - connect \Y $and$ls180.v:6429$1950_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3833$1160_Y end - attribute \src "ls180.v:6429.43-6429.151" - cell $and $and$ls180.v:6429$1952 + attribute \src "ls180.v:4365.8-4365.33" + cell $eq $eq$ls180.v:4365$1260 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6429$1950_Y - connect \B $eq$ls180.v:6429$1951_Y - connect \Y $and$ls180.v:6429$1952_Y + connect \A \libresocsim_value + connect \B 1'0 + connect \Y $eq$ls180.v:4365$1260_Y end - attribute \src "ls180.v:6431.44-6431.97" - cell $and $and$ls180.v:6431$1953 + attribute \src "ls180.v:4400.8-4400.37" + cell $eq $eq$ls180.v:4400$1271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6431$1953_Y + connect \A \sdram_postponer_count + connect \B 1'0 + connect \Y $eq$ls180.v:4400$1271_Y end - attribute \src "ls180.v:6431.43-6431.148" - cell $and $and$ls180.v:6431$1955 + attribute \src "ls180.v:4420.33-4420.64" + cell $eq $eq$ls180.v:4420$1274 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6431$1953_Y - connect \B $eq$ls180.v:6431$1954_Y - connect \Y $and$ls180.v:6431$1955_Y + connect \A \sdram_sequencer_counter + connect \B 1'0 + connect \Y $eq$ls180.v:4420$1274_Y end - attribute \src "ls180.v:6432.44-6432.100" - cell $and $and$ls180.v:6432$1957 + attribute \src "ls180.v:4427.7-4427.38" + cell $eq $eq$ls180.v:4427$1276 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6432$1956_Y - connect \Y $and$ls180.v:6432$1957_Y + connect \A \sdram_sequencer_counter + connect \B 2'10 + connect \Y $eq$ls180.v:4427$1276_Y end - attribute \src "ls180.v:6432.43-6432.151" - cell $and $and$ls180.v:6432$1959 + attribute \src "ls180.v:4434.7-4434.38" + cell $eq $eq$ls180.v:4434$1277 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6432$1957_Y - connect \B $eq$ls180.v:6432$1958_Y - connect \Y $and$ls180.v:6432$1959_Y + connect \A \sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:4434$1277_Y end - attribute \src "ls180.v:6434.41-6434.94" - cell $and $and$ls180.v:6434$1960 + attribute \src "ls180.v:4442.7-4442.38" + cell $eq $eq$ls180.v:4442$1278 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6434$1960_Y + connect \A \sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:4442$1278_Y end - attribute \src "ls180.v:6434.40-6434.145" - cell $and $and$ls180.v:6434$1962 + attribute \src "ls180.v:4494.9-4494.49" + cell $eq $eq$ls180.v:4494$1296 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6434$1960_Y - connect \B $eq$ls180.v:6434$1961_Y - connect \Y $and$ls180.v:6434$1962_Y + connect \A \sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:4494$1296_Y end - attribute \src "ls180.v:6435.41-6435.97" - cell $and $and$ls180.v:6435$1964 + attribute \src "ls180.v:4540.9-4540.49" + cell $eq $eq$ls180.v:4540$1312 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6435$1963_Y - connect \Y $and$ls180.v:6435$1964_Y + connect \A \sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:4540$1312_Y end - attribute \src "ls180.v:6435.40-6435.148" - cell $and $and$ls180.v:6435$1966 + attribute \src "ls180.v:4586.9-4586.49" + cell $eq $eq$ls180.v:4586$1328 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6435$1964_Y - connect \B $eq$ls180.v:6435$1965_Y - connect \Y $and$ls180.v:6435$1966_Y + connect \A \sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:4586$1328_Y end - attribute \src "ls180.v:6437.42-6437.95" - cell $and $and$ls180.v:6437$1967 + attribute \src "ls180.v:4632.9-4632.49" + cell $eq $eq$ls180.v:4632$1344 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6437$1967_Y + connect \A \sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:4632$1344_Y end - attribute \src "ls180.v:6437.41-6437.146" - cell $and $and$ls180.v:6437$1969 + attribute \src "ls180.v:4782.9-4782.36" + cell $eq $eq$ls180.v:4782$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6437$1967_Y - connect \B $eq$ls180.v:6437$1968_Y - connect \Y $and$ls180.v:6437$1969_Y + connect \A \sdram_tccdcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:4782$1356_Y end - attribute \src "ls180.v:6438.42-6438.98" - cell $and $and$ls180.v:6438$1971 + attribute \src "ls180.v:4797.9-4797.36" + cell $eq $eq$ls180.v:4797$1359 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6438$1970_Y - connect \Y $and$ls180.v:6438$1971_Y + connect \A \sdram_twtrcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:4797$1359_Y end - attribute \src "ls180.v:6438.41-6438.149" - cell $and $and$ls180.v:6438$1973 + attribute \src "ls180.v:4803.54-4803.92" + cell $eq $eq$ls180.v:4803$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6438$1971_Y - connect \B $eq$ls180.v:6438$1972_Y - connect \Y $and$ls180.v:6438$1973_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4803$1360_Y end - attribute \src "ls180.v:6440.44-6440.97" - cell $and $and$ls180.v:6440$1974 + attribute \src "ls180.v:4803.136-4803.174" + cell $eq $eq$ls180.v:4803$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6440$1974_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4803$1363_Y end - attribute \src "ls180.v:6440.43-6440.148" - cell $and $and$ls180.v:6440$1976 + attribute \src "ls180.v:4803.218-4803.256" + cell $eq $eq$ls180.v:4803$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6440$1974_Y - connect \B $eq$ls180.v:6440$1975_Y - connect \Y $and$ls180.v:6440$1976_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4803$1366_Y end - attribute \src "ls180.v:6441.44-6441.100" - cell $and $and$ls180.v:6441$1978 + attribute \src "ls180.v:4803.300-4803.338" + cell $eq $eq$ls180.v:4803$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6441$1977_Y - connect \Y $and$ls180.v:6441$1978_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4803$1369_Y end - attribute \src "ls180.v:6441.43-6441.151" - cell $and $and$ls180.v:6441$1980 + attribute \src "ls180.v:4804.55-4804.93" + cell $eq $eq$ls180.v:4804$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6441$1978_Y - connect \B $eq$ls180.v:6441$1979_Y - connect \Y $and$ls180.v:6441$1980_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4804$1372_Y end - attribute \src "ls180.v:6443.44-6443.97" - cell $and $and$ls180.v:6443$1981 + attribute \src "ls180.v:4804.137-4804.175" + cell $eq $eq$ls180.v:4804$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6443$1981_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4804$1375_Y end - attribute \src "ls180.v:6443.43-6443.148" - cell $and $and$ls180.v:6443$1983 + attribute \src "ls180.v:4804.219-4804.257" + cell $eq $eq$ls180.v:4804$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6443$1981_Y - connect \B $eq$ls180.v:6443$1982_Y - connect \Y $and$ls180.v:6443$1983_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4804$1378_Y end - attribute \src "ls180.v:6444.44-6444.100" - cell $and $and$ls180.v:6444$1985 + attribute \src "ls180.v:4804.301-4804.339" + cell $eq $eq$ls180.v:4804$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6444$1984_Y - connect \Y $and$ls180.v:6444$1985_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4804$1381_Y end - attribute \src "ls180.v:6444.43-6444.151" - cell $and $and$ls180.v:6444$1987 + attribute \src "ls180.v:4839.9-4839.37" + cell $eq $eq$ls180.v:4839$1393 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6444$1985_Y - connect \B $eq$ls180.v:6444$1986_Y - connect \Y $and$ls180.v:6444$1987_Y + connect \A \uart_phy_tx_bitcount + connect \B 4'1000 + connect \Y $eq$ls180.v:4839$1393_Y end - attribute \src "ls180.v:6446.44-6446.97" - cell $and $and$ls180.v:6446$1988 + attribute \src "ls180.v:4842.10-4842.38" + cell $eq $eq$ls180.v:4842$1394 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6446$1988_Y + connect \A \uart_phy_tx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:4842$1394_Y end - attribute \src "ls180.v:6446.43-6446.148" - cell $and $and$ls180.v:6446$1990 + attribute \src "ls180.v:4868.9-4868.37" + cell $eq $eq$ls180.v:4868$1400 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6446$1988_Y - connect \B $eq$ls180.v:6446$1989_Y - connect \Y $and$ls180.v:6446$1990_Y + connect \A \uart_phy_rx_bitcount + connect \B 1'0 + connect \Y $eq$ls180.v:4868$1400_Y end - attribute \src "ls180.v:6447.44-6447.100" - cell $and $and$ls180.v:6447$1992 + attribute \src "ls180.v:4873.10-4873.38" + cell $eq $eq$ls180.v:4873$1401 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6447$1991_Y - connect \Y $and$ls180.v:6447$1992_Y + connect \A \uart_phy_rx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:4873$1401_Y + end + attribute \src "ls180.v:5507.28-5507.31" + cell $memrd $memrd$\mem$ls180.v:5507$1459 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \TRANSPARENT 0 + parameter \WIDTH 32 + connect \ADDR \memadr + connect \CLK 1'x + connect \DATA $memrd$\mem$ls180.v:5507$1459_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5527.20-5527.25" + cell $memrd $memrd$\mem_1$ls180.v:5527$1485 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 32 + connect \ADDR \memadr_1 + connect \CLK 1'x + connect \DATA $memrd$\mem_1$ls180.v:5527$1485_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5538.12-5538.19" + cell $memrd $memrd$\storage$ls180.v:5538$1493 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:5538$1493_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5545.63-5545.70" + cell $memrd $memrd$\storage$ls180.v:5545$1495 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:5545$1495_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5552.14-5552.23" + cell $memrd $memrd$\storage_1$ls180.v:5552$1503 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:5552$1503_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5559.63-5559.72" + cell $memrd $memrd$\storage_1$ls180.v:5559$1505 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:5559$1505_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5566.14-5566.23" + cell $memrd $memrd$\storage_2$ls180.v:5566$1513 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:5566$1513_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5573.63-5573.72" + cell $memrd $memrd$\storage_2$ls180.v:5573$1515 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:5573$1515_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5580.14-5580.23" + cell $memrd $memrd$\storage_3$ls180.v:5580$1523 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:5580$1523_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5587.63-5587.72" + cell $memrd $memrd$\storage_3$ls180.v:5587$1525 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:5587$1525_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5595.14-5595.23" + cell $memrd $memrd$\storage_4$ls180.v:5595$1533 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \tx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:5595$1533_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5600.15-5600.24" + cell $memrd $memrd$\storage_4$ls180.v:5600$1535 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \tx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:5600$1535_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5612.14-5612.23" + cell $memrd $memrd$\storage_5$ls180.v:5612$1543 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \rx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:5612$1543_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5617.15-5617.24" + cell $memrd $memrd$\storage_5$ls180.v:5617$1545 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \rx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:5617$1545_DATA + connect \EN 1'x end - attribute \src "ls180.v:6447.43-6447.151" - cell $and $and$ls180.v:6447$1994 + attribute \src "ls180.v:1711.36-1711.61" + cell $ne $ne$ls180.v:1711$63 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6447$1992_Y - connect \B $eq$ls180.v:6447$1993_Y - connect \Y $and$ls180.v:6447$1994_Y + connect \A \libresocsim_value + connect \B 1'0 + connect \Y $ne$ls180.v:1711$63_Y end - attribute \src "ls180.v:6449.44-6449.97" - cell $and $and$ls180.v:6449$1995 + attribute \src "ls180.v:1882.60-1882.89" + cell $ne $ne$ls180.v:1882$90 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6449$1995_Y + connect \A \sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:1882$90_Y end - attribute \src "ls180.v:6449.43-6449.148" - cell $and $and$ls180.v:6449$1997 + attribute \src "ls180.v:1943.8-1943.132" + cell $ne $ne$ls180.v:1943$109 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6449$1995_Y - connect \B $eq$ls180.v:6449$1996_Y - connect \Y $and$ls180.v:6449$1997_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:1943$109_Y end - attribute \src "ls180.v:6450.44-6450.100" - cell $and $and$ls180.v:6450$1999 + attribute \src "ls180.v:1975.70-1975.123" + cell $ne $ne$ls180.v:1975$116 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6450$1998_Y - connect \Y $and$ls180.v:6450$1999_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:1975$116_Y end - attribute \src "ls180.v:6450.43-6450.151" - cell $and $and$ls180.v:6450$2001 + attribute \src "ls180.v:1976.70-1976.123" + cell $ne $ne$ls180.v:1976$117 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6450$1999_Y - connect \B $eq$ls180.v:6450$2000_Y - connect \Y $and$ls180.v:6450$2001_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:1976$117_Y end - attribute \src "ls180.v:6474.44-6474.97" - cell $and $and$ls180.v:6474$2003 + attribute \src "ls180.v:2100.8-2100.132" + cell $ne $ne$ls180.v:2100$139 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6474$2003_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:2100$139_Y end - attribute \src "ls180.v:6474.43-6474.147" - cell $and $and$ls180.v:6474$2005 + attribute \src "ls180.v:2132.70-2132.123" + cell $ne $ne$ls180.v:2132$146 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6474$2003_Y - connect \B $eq$ls180.v:6474$2004_Y - connect \Y $and$ls180.v:6474$2005_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:2132$146_Y end - attribute \src "ls180.v:6475.44-6475.100" - cell $and $and$ls180.v:6475$2007 + attribute \src "ls180.v:2133.70-2133.123" + cell $ne $ne$ls180.v:2133$147 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6475$2006_Y - connect \Y $and$ls180.v:6475$2007_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:2133$147_Y end - attribute \src "ls180.v:6475.43-6475.150" - cell $and $and$ls180.v:6475$2009 + attribute \src "ls180.v:2257.8-2257.132" + cell $ne $ne$ls180.v:2257$169 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6475$2007_Y - connect \B $eq$ls180.v:6475$2008_Y - connect \Y $and$ls180.v:6475$2009_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:2257$169_Y end - attribute \src "ls180.v:6477.49-6477.102" - cell $and $and$ls180.v:6477$2010 + attribute \src "ls180.v:2289.70-2289.123" + cell $ne $ne$ls180.v:2289$176 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6477$2010_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:2289$176_Y end - attribute \src "ls180.v:6477.48-6477.152" - cell $and $and$ls180.v:6477$2012 + attribute \src "ls180.v:2290.70-2290.123" + cell $ne $ne$ls180.v:2290$177 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6477$2010_Y - connect \B $eq$ls180.v:6477$2011_Y - connect \Y $and$ls180.v:6477$2012_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:2290$177_Y end - attribute \src "ls180.v:6478.49-6478.105" - cell $and $and$ls180.v:6478$2014 + attribute \src "ls180.v:2414.8-2414.132" + cell $ne $ne$ls180.v:2414$199 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6478$2013_Y - connect \Y $and$ls180.v:6478$2014_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:2414$199_Y end - attribute \src "ls180.v:6478.48-6478.155" - cell $and $and$ls180.v:6478$2016 + attribute \src "ls180.v:2446.70-2446.123" + cell $ne $ne$ls180.v:2446$206 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6478$2014_Y - connect \B $eq$ls180.v:6478$2015_Y - connect \Y $and$ls180.v:6478$2016_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:2446$206_Y end - attribute \src "ls180.v:6480.49-6480.102" - cell $and $and$ls180.v:6480$2017 + attribute \src "ls180.v:2447.70-2447.123" + cell $ne $ne$ls180.v:2447$207 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6480$2017_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:2447$207_Y end - attribute \src "ls180.v:6480.48-6480.152" - cell $and $and$ls180.v:6480$2019 + attribute \src "ls180.v:2939.37-2939.60" + cell $ne $ne$ls180.v:2939$605 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6480$2017_Y - connect \B $eq$ls180.v:6480$2018_Y - connect \Y $and$ls180.v:6480$2019_Y + connect \A \tx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:2939$605_Y end - attribute \src "ls180.v:6481.49-6481.105" - cell $and $and$ls180.v:6481$2021 + attribute \src "ls180.v:2940.37-2940.59" + cell $ne $ne$ls180.v:2940$606 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6481$2020_Y - connect \Y $and$ls180.v:6481$2021_Y + connect \A \tx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:2940$606_Y end - attribute \src "ls180.v:6481.48-6481.155" - cell $and $and$ls180.v:6481$2023 + attribute \src "ls180.v:2969.37-2969.60" + cell $ne $ne$ls180.v:2969$616 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6481$2021_Y - connect \B $eq$ls180.v:6481$2022_Y - connect \Y $and$ls180.v:6481$2023_Y + connect \A \rx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:2969$616_Y end - attribute \src "ls180.v:6483.42-6483.95" - cell $and $and$ls180.v:6483$2024 + attribute \src "ls180.v:2970.37-2970.59" + cell $ne $ne$ls180.v:2970$617 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6483$2024_Y + connect \A \rx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:2970$617_Y end - attribute \src "ls180.v:6483.41-6483.145" - cell $and $and$ls180.v:6483$2026 + attribute \src "ls180.v:3065.99-3065.143" + cell $ne $ne$ls180.v:3065$624 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6483$2024_Y - connect \B $eq$ls180.v:6483$2025_Y - connect \Y $and$ls180.v:6483$2026_Y + connect \A \libresocsim_libresocsim_wishbone_sel + connect \B 1'0 + connect \Y $ne$ls180.v:3065$624_Y end - attribute \src "ls180.v:6484.42-6484.98" - cell $and $and$ls180.v:6484$2028 + attribute \src "ls180.v:4355.7-4355.47" + cell $ne $ne$ls180.v:4355$1255 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 32 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6484$2027_Y - connect \Y $and$ls180.v:6484$2028_Y + connect \A \libresocsim_bus_errors + connect \B 32'11111111111111111111111111111111 + connect \Y $ne$ls180.v:4355$1255_Y end - attribute \src "ls180.v:6484.41-6484.148" - cell $and $and$ls180.v:6484$2030 + attribute \src "ls180.v:4409.9-4409.38" + cell $ne $ne$ls180.v:4409$1272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6484$2028_Y - connect \B $eq$ls180.v:6484$2029_Y - connect \Y $and$ls180.v:6484$2030_Y + connect \A \sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:4409$1272_Y end - attribute \src "ls180.v:6491.46-6491.99" - cell $and $and$ls180.v:6491$2032 + attribute \src "ls180.v:4445.8-4445.39" + cell $ne $ne$ls180.v:4445$1279 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6491$2032_Y + connect \A \sdram_sequencer_counter + connect \B 1'0 + connect \Y $ne$ls180.v:4445$1279_Y end - attribute \src "ls180.v:6491.45-6491.149" - cell $and $and$ls180.v:6491$2034 + attribute \src "ls180.v:1519.40-1519.70" + cell $not $not$ls180.v:1519$17 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6491$2032_Y - connect \B $eq$ls180.v:6491$2033_Y - connect \Y $and$ls180.v:6491$2034_Y + connect \A \libresocsim_libresoc_ibus_cyc + connect \Y $not$ls180.v:1519$17_Y end - attribute \src "ls180.v:6492.46-6492.102" - cell $and $and$ls180.v:6492$2036 + attribute \src "ls180.v:1558.56-1558.84" + cell $not $not$ls180.v:1558$22 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6492$2035_Y - connect \Y $and$ls180.v:6492$2036_Y + connect \A \libresocsim_converter0_skip + connect \Y $not$ls180.v:1558$22_Y end - attribute \src "ls180.v:6492.45-6492.152" - cell $and $and$ls180.v:6492$2038 + attribute \src "ls180.v:1559.56-1559.84" + cell $not $not$ls180.v:1559$23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6492$2036_Y - connect \B $eq$ls180.v:6492$2037_Y - connect \Y $and$ls180.v:6492$2038_Y + connect \A \libresocsim_converter0_skip + connect \Y $not$ls180.v:1559$23_Y end - attribute \src "ls180.v:6494.50-6494.103" - cell $and $and$ls180.v:6494$2039 + attribute \src "ls180.v:1579.40-1579.70" + cell $not $not$ls180.v:1579$28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6494$2039_Y + connect \A \libresocsim_libresoc_dbus_cyc + connect \Y $not$ls180.v:1579$28_Y end - attribute \src "ls180.v:6494.49-6494.153" - cell $and $and$ls180.v:6494$2041 + attribute \src "ls180.v:1618.56-1618.84" + cell $not $not$ls180.v:1618$33 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6494$2039_Y - connect \B $eq$ls180.v:6494$2040_Y - connect \Y $and$ls180.v:6494$2041_Y + connect \A \libresocsim_converter1_skip + connect \Y $not$ls180.v:1618$33_Y end - attribute \src "ls180.v:6495.50-6495.106" - cell $and $and$ls180.v:6495$2043 + attribute \src "ls180.v:1619.56-1619.84" + cell $not $not$ls180.v:1619$34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6495$2042_Y - connect \Y $and$ls180.v:6495$2043_Y + connect \A \libresocsim_converter1_skip + connect \Y $not$ls180.v:1619$34_Y end - attribute \src "ls180.v:6495.49-6495.156" - cell $and $and$ls180.v:6495$2045 + attribute \src "ls180.v:1639.40-1639.73" + cell $not $not$ls180.v:1639$39 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6495$2043_Y - connect \B $eq$ls180.v:6495$2044_Y - connect \Y $and$ls180.v:6495$2045_Y + connect \A \libresocsim_libresoc_jtag_wb_cyc + connect \Y $not$ls180.v:1639$39_Y end - attribute \src "ls180.v:6497.40-6497.93" - cell $and $and$ls180.v:6497$2046 + attribute \src "ls180.v:1678.56-1678.84" + cell $not $not$ls180.v:1678$44 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6497$2046_Y + connect \A \libresocsim_converter2_skip + connect \Y $not$ls180.v:1678$44_Y end - attribute \src "ls180.v:6497.39-6497.143" - cell $and $and$ls180.v:6497$2048 + attribute \src "ls180.v:1679.56-1679.84" + cell $not $not$ls180.v:1679$45 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6497$2046_Y - connect \B $eq$ls180.v:6497$2047_Y - connect \Y $and$ls180.v:6497$2048_Y + connect \A \libresocsim_converter2_skip + connect \Y $not$ls180.v:1679$45_Y end - attribute \src "ls180.v:6498.40-6498.96" - cell $and $and$ls180.v:6498$2050 + attribute \src "ls180.v:1831.29-1831.54" + cell $not $not$ls180.v:1831$82 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6498$2049_Y - connect \Y $and$ls180.v:6498$2050_Y + connect \A \sdram_command_storage [0] + connect \Y $not$ls180.v:1831$82_Y end - attribute \src "ls180.v:6498.39-6498.146" - cell $and $and$ls180.v:6498$2052 + attribute \src "ls180.v:1832.26-1832.51" + cell $not $not$ls180.v:1832$83 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6498$2050_Y - connect \B $eq$ls180.v:6498$2051_Y - connect \Y $and$ls180.v:6498$2052_Y + connect \A \sdram_command_storage [1] + connect \Y $not$ls180.v:1832$83_Y end - attribute \src "ls180.v:6500.50-6500.103" - cell $and $and$ls180.v:6500$2053 + attribute \src "ls180.v:1833.27-1833.52" + cell $not $not$ls180.v:1833$84 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6500$2053_Y + connect \A \sdram_command_storage [2] + connect \Y $not$ls180.v:1833$84_Y end - attribute \src "ls180.v:6500.49-6500.153" - cell $and $and$ls180.v:6500$2055 + attribute \src "ls180.v:1834.27-1834.52" + cell $not $not$ls180.v:1834$85 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6500$2053_Y - connect \B $eq$ls180.v:6500$2054_Y - connect \Y $and$ls180.v:6500$2055_Y + connect \A \sdram_command_storage [3] + connect \Y $not$ls180.v:1834$85_Y end - attribute \src "ls180.v:6501.50-6501.106" - cell $and $and$ls180.v:6501$2057 + attribute \src "ls180.v:1876.28-1876.46" + cell $not $not$ls180.v:1876$88 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6501$2056_Y - connect \Y $and$ls180.v:6501$2057_Y + connect \A \sdram_timer_done0 + connect \Y $not$ls180.v:1876$88_Y end - attribute \src "ls180.v:6501.49-6501.156" - cell $and $and$ls180.v:6501$2059 + attribute \src "ls180.v:1977.53-1977.96" + cell $not $not$ls180.v:1977$118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6501$2057_Y - connect \B $eq$ls180.v:6501$2058_Y - connect \Y $and$ls180.v:6501$2059_Y + connect \A \sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:1977$118_Y end - attribute \src "ls180.v:6503.50-6503.103" - cell $and $and$ls180.v:6503$2060 + attribute \src "ls180.v:2031.9-2031.40" + cell $not $not$ls180.v:2031$123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6503$2060_Y + connect \A \sdram_bankmachine0_refresh_req + connect \Y $not$ls180.v:2031$123_Y end - attribute \src "ls180.v:6503.49-6503.153" - cell $and $and$ls180.v:6503$2062 + attribute \src "ls180.v:2134.53-2134.96" + cell $not $not$ls180.v:2134$148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6503$2060_Y - connect \B $eq$ls180.v:6503$2061_Y - connect \Y $and$ls180.v:6503$2062_Y + connect \A \sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:2134$148_Y end - attribute \src "ls180.v:6504.50-6504.106" - cell $and $and$ls180.v:6504$2064 + attribute \src "ls180.v:2188.9-2188.40" + cell $not $not$ls180.v:2188$153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6504$2063_Y - connect \Y $and$ls180.v:6504$2064_Y + connect \A \sdram_bankmachine1_refresh_req + connect \Y $not$ls180.v:2188$153_Y end - attribute \src "ls180.v:6504.49-6504.156" - cell $and $and$ls180.v:6504$2066 + attribute \src "ls180.v:2291.53-2291.96" + cell $not $not$ls180.v:2291$178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6504$2064_Y - connect \B $eq$ls180.v:6504$2065_Y - connect \Y $and$ls180.v:6504$2066_Y + connect \A \sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:2291$178_Y end - attribute \src "ls180.v:6506.51-6506.104" - cell $and $and$ls180.v:6506$2067 + attribute \src "ls180.v:2345.9-2345.40" + cell $not $not$ls180.v:2345$183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6506$2067_Y + connect \A \sdram_bankmachine2_refresh_req + connect \Y $not$ls180.v:2345$183_Y end - attribute \src "ls180.v:6506.50-6506.154" - cell $and $and$ls180.v:6506$2069 + attribute \src "ls180.v:2448.53-2448.96" + cell $not $not$ls180.v:2448$208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6506$2067_Y - connect \B $eq$ls180.v:6506$2068_Y - connect \Y $and$ls180.v:6506$2069_Y + connect \A \sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:2448$208_Y end - attribute \src "ls180.v:6507.51-6507.107" - cell $and $and$ls180.v:6507$2071 + attribute \src "ls180.v:2502.9-2502.40" + cell $not $not$ls180.v:2502$213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6507$2070_Y - connect \Y $and$ls180.v:6507$2071_Y + connect \A \sdram_bankmachine3_refresh_req + connect \Y $not$ls180.v:2502$213_Y end - attribute \src "ls180.v:6507.50-6507.157" - cell $and $and$ls180.v:6507$2073 + attribute \src "ls180.v:2544.129-2544.162" + cell $not $not$ls180.v:2544$216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6507$2071_Y - connect \B $eq$ls180.v:6507$2072_Y - connect \Y $and$ls180.v:6507$2073_Y + connect \A \sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:2544$216_Y end - attribute \src "ls180.v:6509.49-6509.102" - cell $and $and$ls180.v:6509$2074 + attribute \src "ls180.v:2544.168-2544.200" + cell $not $not$ls180.v:2544$218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6509$2074_Y + connect \A \sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:2544$218_Y end - attribute \src "ls180.v:6509.48-6509.152" - cell $and $and$ls180.v:6509$2076 + attribute \src "ls180.v:2545.129-2545.162" + cell $not $not$ls180.v:2545$222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6509$2074_Y - connect \B $eq$ls180.v:6509$2075_Y - connect \Y $and$ls180.v:6509$2076_Y + connect \A \sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:2545$222_Y end - attribute \src "ls180.v:6510.49-6510.105" - cell $and $and$ls180.v:6510$2078 + attribute \src "ls180.v:2545.168-2545.200" + cell $not $not$ls180.v:2545$224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6510$2077_Y - connect \Y $and$ls180.v:6510$2078_Y + connect \A \sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:2545$224_Y + end + attribute \src "ls180.v:2561.38-2561.63" + cell $not $not$ls180.v:2561$252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \sdram_interface_wdata_we + connect \Y $not$ls180.v:2561$252_Y end - attribute \src "ls180.v:6510.48-6510.155" - cell $and $and$ls180.v:6510$2080 + attribute \src "ls180.v:2564.180-2564.215" + cell $not $not$ls180.v:2564$255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6510$2078_Y - connect \B $eq$ls180.v:6510$2079_Y - connect \Y $and$ls180.v:6510$2080_Y + connect \A \sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:2564$255_Y end - attribute \src "ls180.v:6512.49-6512.102" - cell $and $and$ls180.v:6512$2081 + attribute \src "ls180.v:2564.221-2564.255" + cell $not $not$ls180.v:2564$257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6512$2081_Y + connect \A \sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:2564$257_Y end - attribute \src "ls180.v:6512.48-6512.152" - cell $and $and$ls180.v:6512$2083 + attribute \src "ls180.v:2564.139-2564.257" + cell $not $not$ls180.v:2564$259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6512$2081_Y - connect \B $eq$ls180.v:6512$2082_Y - connect \Y $and$ls180.v:6512$2083_Y + connect \A $and$ls180.v:2564$258_Y + connect \Y $not$ls180.v:2564$259_Y end - attribute \src "ls180.v:6513.49-6513.105" - cell $and $and$ls180.v:6513$2085 + attribute \src "ls180.v:2565.180-2565.215" + cell $not $not$ls180.v:2565$268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6513$2084_Y - connect \Y $and$ls180.v:6513$2085_Y + connect \A \sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:2565$268_Y end - attribute \src "ls180.v:6513.48-6513.155" - cell $and $and$ls180.v:6513$2087 + attribute \src "ls180.v:2565.221-2565.255" + cell $not $not$ls180.v:2565$270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6513$2085_Y - connect \B $eq$ls180.v:6513$2086_Y - connect \Y $and$ls180.v:6513$2087_Y + connect \A \sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:2565$270_Y end - attribute \src "ls180.v:6515.49-6515.102" - cell $and $and$ls180.v:6515$2088 + attribute \src "ls180.v:2565.139-2565.257" + cell $not $not$ls180.v:2565$272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6515$2088_Y + connect \A $and$ls180.v:2565$271_Y + connect \Y $not$ls180.v:2565$272_Y end - attribute \src "ls180.v:6515.48-6515.152" - cell $and $and$ls180.v:6515$2090 + attribute \src "ls180.v:2566.180-2566.215" + cell $not $not$ls180.v:2566$281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6515$2088_Y - connect \B $eq$ls180.v:6515$2089_Y - connect \Y $and$ls180.v:6515$2090_Y + connect \A \sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:2566$281_Y end - attribute \src "ls180.v:6516.49-6516.105" - cell $and $and$ls180.v:6516$2092 + attribute \src "ls180.v:2566.221-2566.255" + cell $not $not$ls180.v:2566$283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6516$2091_Y - connect \Y $and$ls180.v:6516$2092_Y + connect \A \sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:2566$283_Y end - attribute \src "ls180.v:6516.48-6516.155" - cell $and $and$ls180.v:6516$2094 + attribute \src "ls180.v:2566.139-2566.257" + cell $not $not$ls180.v:2566$285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6516$2092_Y - connect \B $eq$ls180.v:6516$2093_Y - connect \Y $and$ls180.v:6516$2094_Y + connect \A $and$ls180.v:2566$284_Y + connect \Y $not$ls180.v:2566$285_Y end - attribute \src "ls180.v:6518.49-6518.102" - cell $and $and$ls180.v:6518$2095 + attribute \src "ls180.v:2567.180-2567.215" + cell $not $not$ls180.v:2567$294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6518$2095_Y + connect \A \sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:2567$294_Y end - attribute \src "ls180.v:6518.48-6518.152" - cell $and $and$ls180.v:6518$2097 + attribute \src "ls180.v:2567.221-2567.255" + cell $not $not$ls180.v:2567$296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6518$2095_Y - connect \B $eq$ls180.v:6518$2096_Y - connect \Y $and$ls180.v:6518$2097_Y + connect \A \sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:2567$296_Y end - attribute \src "ls180.v:6519.49-6519.105" - cell $and $and$ls180.v:6519$2099 + attribute \src "ls180.v:2567.139-2567.257" + cell $not $not$ls180.v:2567$298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6519$2098_Y - connect \Y $and$ls180.v:6519$2099_Y + connect \A $and$ls180.v:2567$297_Y + connect \Y $not$ls180.v:2567$298_Y end - attribute \src "ls180.v:6519.48-6519.155" - cell $and $and$ls180.v:6519$2101 + attribute \src "ls180.v:2594.61-2594.88" + cell $not $not$ls180.v:2594$309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6519$2099_Y - connect \B $eq$ls180.v:6519$2100_Y - connect \Y $and$ls180.v:6519$2101_Y + connect \A \sdram_choose_cmd_cmd_valid + connect \Y $not$ls180.v:2594$309_Y end - attribute \src "ls180.v:6536.42-6536.97" - cell $and $and$ls180.v:6536$2103 + attribute \src "ls180.v:2597.180-2597.215" + cell $not $not$ls180.v:2597$313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6536$2103_Y + connect \A \sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:2597$313_Y end - attribute \src "ls180.v:6536.41-6536.148" - cell $and $and$ls180.v:6536$2105 + attribute \src "ls180.v:2597.221-2597.255" + cell $not $not$ls180.v:2597$315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6536$2103_Y - connect \B $eq$ls180.v:6536$2104_Y - connect \Y $and$ls180.v:6536$2105_Y + connect \A \sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:2597$315_Y end - attribute \src "ls180.v:6537.42-6537.100" - cell $and $and$ls180.v:6537$2107 + attribute \src "ls180.v:2597.139-2597.257" + cell $not $not$ls180.v:2597$317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6537$2106_Y - connect \Y $and$ls180.v:6537$2107_Y + connect \A $and$ls180.v:2597$316_Y + connect \Y $not$ls180.v:2597$317_Y end - attribute \src "ls180.v:6537.41-6537.151" - cell $and $and$ls180.v:6537$2109 + attribute \src "ls180.v:2598.180-2598.215" + cell $not $not$ls180.v:2598$326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6537$2107_Y - connect \B $eq$ls180.v:6537$2108_Y - connect \Y $and$ls180.v:6537$2109_Y + connect \A \sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:2598$326_Y end - attribute \src "ls180.v:6539.42-6539.97" - cell $and $and$ls180.v:6539$2110 + attribute \src "ls180.v:2598.221-2598.255" + cell $not $not$ls180.v:2598$328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6539$2110_Y + connect \A \sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:2598$328_Y end - attribute \src "ls180.v:6539.41-6539.148" - cell $and $and$ls180.v:6539$2112 + attribute \src "ls180.v:2598.139-2598.257" + cell $not $not$ls180.v:2598$330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6539$2110_Y - connect \B $eq$ls180.v:6539$2111_Y - connect \Y $and$ls180.v:6539$2112_Y + connect \A $and$ls180.v:2598$329_Y + connect \Y $not$ls180.v:2598$330_Y end - attribute \src "ls180.v:6540.42-6540.100" - cell $and $and$ls180.v:6540$2114 + attribute \src "ls180.v:2599.180-2599.215" + cell $not $not$ls180.v:2599$339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6540$2113_Y - connect \Y $and$ls180.v:6540$2114_Y + connect \A \sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:2599$339_Y end - attribute \src "ls180.v:6540.41-6540.151" - cell $and $and$ls180.v:6540$2116 + attribute \src "ls180.v:2599.221-2599.255" + cell $not $not$ls180.v:2599$341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6540$2114_Y - connect \B $eq$ls180.v:6540$2115_Y - connect \Y $and$ls180.v:6540$2116_Y + connect \A \sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:2599$341_Y end - attribute \src "ls180.v:6542.40-6542.95" - cell $and $and$ls180.v:6542$2117 + attribute \src "ls180.v:2599.139-2599.257" + cell $not $not$ls180.v:2599$343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6542$2117_Y + connect \A $and$ls180.v:2599$342_Y + connect \Y $not$ls180.v:2599$343_Y end - attribute \src "ls180.v:6542.39-6542.146" - cell $and $and$ls180.v:6542$2119 + attribute \src "ls180.v:2600.180-2600.215" + cell $not $not$ls180.v:2600$352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6542$2117_Y - connect \B $eq$ls180.v:6542$2118_Y - connect \Y $and$ls180.v:6542$2119_Y + connect \A \sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:2600$352_Y end - attribute \src "ls180.v:6543.40-6543.98" - cell $and $and$ls180.v:6543$2121 + attribute \src "ls180.v:2600.221-2600.255" + cell $not $not$ls180.v:2600$354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6543$2120_Y - connect \Y $and$ls180.v:6543$2121_Y + connect \A \sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:2600$354_Y end - attribute \src "ls180.v:6543.39-6543.149" - cell $and $and$ls180.v:6543$2123 + attribute \src "ls180.v:2600.139-2600.257" + cell $not $not$ls180.v:2600$356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6543$2121_Y - connect \B $eq$ls180.v:6543$2122_Y - connect \Y $and$ls180.v:6543$2123_Y + connect \A $and$ls180.v:2600$355_Y + connect \Y $not$ls180.v:2600$356_Y end - attribute \src "ls180.v:6545.39-6545.94" - cell $and $and$ls180.v:6545$2124 + attribute \src "ls180.v:2663.61-2663.88" + cell $not $not$ls180.v:2663$395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6545$2124_Y + connect \A \sdram_choose_req_cmd_valid + connect \Y $not$ls180.v:2663$395_Y end - attribute \src "ls180.v:6545.38-6545.145" - cell $and $and$ls180.v:6545$2126 + attribute \src "ls180.v:2684.97-2684.130" + cell $not $not$ls180.v:2684$398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6545$2124_Y - connect \B $eq$ls180.v:6545$2125_Y - connect \Y $and$ls180.v:6545$2126_Y + connect \A \sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:2684$398_Y end - attribute \src "ls180.v:6546.39-6546.97" - cell $and $and$ls180.v:6546$2128 + attribute \src "ls180.v:2684.136-2684.168" + cell $not $not$ls180.v:2684$400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6546$2127_Y - connect \Y $and$ls180.v:6546$2128_Y + connect \A \sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:2684$400_Y end - attribute \src "ls180.v:6546.38-6546.148" - cell $and $and$ls180.v:6546$2130 + attribute \src "ls180.v:2684.58-2684.170" + cell $not $not$ls180.v:2684$402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6546$2128_Y - connect \B $eq$ls180.v:6546$2129_Y - connect \Y $and$ls180.v:6546$2130_Y + connect \A $and$ls180.v:2684$401_Y + connect \Y $not$ls180.v:2684$402_Y end - attribute \src "ls180.v:6548.38-6548.93" - cell $and $and$ls180.v:6548$2131 + attribute \src "ls180.v:2692.11-2692.33" + cell $not $not$ls180.v:2692$405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6548$2131_Y + connect \A \sdram_write_available + connect \Y $not$ls180.v:2692$405_Y end - attribute \src "ls180.v:6548.37-6548.144" - cell $and $and$ls180.v:6548$2133 + attribute \src "ls180.v:2722.97-2722.130" + cell $not $not$ls180.v:2722$407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6548$2131_Y - connect \B $eq$ls180.v:6548$2132_Y - connect \Y $and$ls180.v:6548$2133_Y + connect \A \sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:2722$407_Y end - attribute \src "ls180.v:6549.38-6549.96" - cell $and $and$ls180.v:6549$2135 + attribute \src "ls180.v:2722.136-2722.168" + cell $not $not$ls180.v:2722$409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6549$2134_Y - connect \Y $and$ls180.v:6549$2135_Y + connect \A \sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:2722$409_Y end - attribute \src "ls180.v:6549.37-6549.147" - cell $and $and$ls180.v:6549$2137 + attribute \src "ls180.v:2722.58-2722.170" + cell $not $not$ls180.v:2722$411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6549$2135_Y - connect \B $eq$ls180.v:6549$2136_Y - connect \Y $and$ls180.v:6549$2137_Y + connect \A $and$ls180.v:2722$410_Y + connect \Y $not$ls180.v:2722$411_Y end - attribute \src "ls180.v:6551.37-6551.92" - cell $and $and$ls180.v:6551$2138 + attribute \src "ls180.v:2730.11-2730.32" + cell $not $not$ls180.v:2730$414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6551$2138_Y + connect \A \sdram_read_available + connect \Y $not$ls180.v:2730$414_Y end - attribute \src "ls180.v:6551.36-6551.143" - cell $and $and$ls180.v:6551$2140 + attribute \src "ls180.v:2740.87-2740.336" + cell $not $not$ls180.v:2740$426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6551$2138_Y - connect \B $eq$ls180.v:6551$2139_Y - connect \Y $and$ls180.v:6551$2140_Y + connect \A $or$ls180.v:2740$425_Y + connect \Y $not$ls180.v:2740$426_Y end - attribute \src "ls180.v:6552.37-6552.95" - cell $and $and$ls180.v:6552$2142 + attribute \src "ls180.v:2741.40-2741.68" + cell $not $not$ls180.v:2741$429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6552$2141_Y - connect \Y $and$ls180.v:6552$2142_Y + connect \A \sdram_interface_bank0_valid + connect \Y $not$ls180.v:2741$429_Y end - attribute \src "ls180.v:6552.36-6552.146" - cell $and $and$ls180.v:6552$2144 + attribute \src "ls180.v:2741.73-2741.100" + cell $not $not$ls180.v:2741$430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6552$2142_Y - connect \B $eq$ls180.v:6552$2143_Y - connect \Y $and$ls180.v:6552$2144_Y + connect \A \sdram_interface_bank0_lock + connect \Y $not$ls180.v:2741$430_Y end - attribute \src "ls180.v:6554.43-6554.98" - cell $and $and$ls180.v:6554$2145 + attribute \src "ls180.v:2745.87-2745.336" + cell $not $not$ls180.v:2745$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6554$2145_Y + connect \A $or$ls180.v:2745$441_Y + connect \Y $not$ls180.v:2745$442_Y end - attribute \src "ls180.v:6554.42-6554.149" - cell $and $and$ls180.v:6554$2147 + attribute \src "ls180.v:2746.40-2746.68" + cell $not $not$ls180.v:2746$445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6554$2145_Y - connect \B $eq$ls180.v:6554$2146_Y - connect \Y $and$ls180.v:6554$2147_Y + connect \A \sdram_interface_bank1_valid + connect \Y $not$ls180.v:2746$445_Y end - attribute \src "ls180.v:6555.43-6555.101" - cell $and $and$ls180.v:6555$2149 + attribute \src "ls180.v:2746.73-2746.100" + cell $not $not$ls180.v:2746$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6555$2148_Y - connect \Y $and$ls180.v:6555$2149_Y + connect \A \sdram_interface_bank1_lock + connect \Y $not$ls180.v:2746$446_Y end - attribute \src "ls180.v:6555.42-6555.152" - cell $and $and$ls180.v:6555$2151 + attribute \src "ls180.v:2750.87-2750.336" + cell $not $not$ls180.v:2750$458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6555$2149_Y - connect \B $eq$ls180.v:6555$2150_Y - connect \Y $and$ls180.v:6555$2151_Y + connect \A $or$ls180.v:2750$457_Y + connect \Y $not$ls180.v:2750$458_Y end - attribute \src "ls180.v:6576.42-6576.97" - cell $and $and$ls180.v:6576$2154 + attribute \src "ls180.v:2751.40-2751.68" + cell $not $not$ls180.v:2751$461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6576$2154_Y + connect \A \sdram_interface_bank2_valid + connect \Y $not$ls180.v:2751$461_Y end - attribute \src "ls180.v:6576.41-6576.148" - cell $and $and$ls180.v:6576$2156 + attribute \src "ls180.v:2751.73-2751.100" + cell $not $not$ls180.v:2751$462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6576$2154_Y - connect \B $eq$ls180.v:6576$2155_Y - connect \Y $and$ls180.v:6576$2156_Y + connect \A \sdram_interface_bank2_lock + connect \Y $not$ls180.v:2751$462_Y end - attribute \src "ls180.v:6577.42-6577.100" - cell $and $and$ls180.v:6577$2158 + attribute \src "ls180.v:2755.87-2755.336" + cell $not $not$ls180.v:2755$474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6577$2157_Y - connect \Y $and$ls180.v:6577$2158_Y + connect \A $or$ls180.v:2755$473_Y + connect \Y $not$ls180.v:2755$474_Y end - attribute \src "ls180.v:6577.41-6577.151" - cell $and $and$ls180.v:6577$2160 + attribute \src "ls180.v:2756.40-2756.68" + cell $not $not$ls180.v:2756$477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6577$2158_Y - connect \B $eq$ls180.v:6577$2159_Y - connect \Y $and$ls180.v:6577$2160_Y + connect \A \sdram_interface_bank3_valid + connect \Y $not$ls180.v:2756$477_Y end - attribute \src "ls180.v:6579.42-6579.97" - cell $and $and$ls180.v:6579$2161 + attribute \src "ls180.v:2756.73-2756.100" + cell $not $not$ls180.v:2756$478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6579$2161_Y + connect \A \sdram_interface_bank3_lock + connect \Y $not$ls180.v:2756$478_Y end - attribute \src "ls180.v:6579.41-6579.148" - cell $and $and$ls180.v:6579$2163 + attribute \src "ls180.v:2760.123-2760.372" + cell $not $not$ls180.v:2760$491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6579$2161_Y - connect \B $eq$ls180.v:6579$2162_Y - connect \Y $and$ls180.v:6579$2163_Y + connect \A $or$ls180.v:2760$490_Y + connect \Y $not$ls180.v:2760$491_Y end - attribute \src "ls180.v:6580.42-6580.100" - cell $and $and$ls180.v:6580$2165 + attribute \src "ls180.v:2760.497-2760.746" + cell $not $not$ls180.v:2760$507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6580$2164_Y - connect \Y $and$ls180.v:6580$2165_Y + connect \A $or$ls180.v:2760$506_Y + connect \Y $not$ls180.v:2760$507_Y end - attribute \src "ls180.v:6580.41-6580.151" - cell $and $and$ls180.v:6580$2167 + attribute \src "ls180.v:2760.871-2760.1120" + cell $not $not$ls180.v:2760$523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6580$2165_Y - connect \B $eq$ls180.v:6580$2166_Y - connect \Y $and$ls180.v:6580$2167_Y + connect \A $or$ls180.v:2760$522_Y + connect \Y $not$ls180.v:2760$523_Y end - attribute \src "ls180.v:6582.40-6582.95" - cell $and $and$ls180.v:6582$2168 + attribute \src "ls180.v:2760.1245-2760.1494" + cell $not $not$ls180.v:2760$539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6582$2168_Y + connect \A $or$ls180.v:2760$538_Y + connect \Y $not$ls180.v:2760$539_Y end - attribute \src "ls180.v:6582.39-6582.146" - cell $and $and$ls180.v:6582$2170 + attribute \src "ls180.v:2782.27-2782.40" + cell $not $not$ls180.v:2782$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6582$2168_Y - connect \B $eq$ls180.v:6582$2169_Y - connect \Y $and$ls180.v:6582$2170_Y + connect \A \wb_sdram_cyc + connect \Y $not$ls180.v:2782$545_Y end - attribute \src "ls180.v:6583.40-6583.98" - cell $and $and$ls180.v:6583$2172 + attribute \src "ls180.v:2821.25-2821.40" + cell $not $not$ls180.v:2821$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6583$2171_Y - connect \Y $and$ls180.v:6583$2172_Y + connect \A \converter_skip + connect \Y $not$ls180.v:2821$550_Y end - attribute \src "ls180.v:6583.39-6583.149" - cell $and $and$ls180.v:6583$2174 + attribute \src "ls180.v:2822.25-2822.40" + cell $not $not$ls180.v:2822$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6583$2172_Y - connect \B $eq$ls180.v:6583$2173_Y - connect \Y $and$ls180.v:6583$2174_Y + connect \A \converter_skip + connect \Y $not$ls180.v:2822$551_Y end - attribute \src "ls180.v:6585.39-6585.94" - cell $and $and$ls180.v:6585$2175 + attribute \src "ls180.v:2847.22-2847.38" + cell $not $not$ls180.v:2847$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6585$2175_Y + connect \A \litedram_wb_cyc + connect \Y $not$ls180.v:2847$557_Y end - attribute \src "ls180.v:6585.38-6585.145" - cell $and $and$ls180.v:6585$2177 + attribute \src "ls180.v:2848.25-2848.40" + cell $not $not$ls180.v:2848$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6585$2175_Y - connect \B $eq$ls180.v:6585$2176_Y - connect \Y $and$ls180.v:6585$2177_Y + connect \A \litedram_wb_we + connect \Y $not$ls180.v:2848$558_Y end - attribute \src "ls180.v:6586.39-6586.97" - cell $and $and$ls180.v:6586$2179 + attribute \src "ls180.v:2849.65-2849.78" + cell $not $not$ls180.v:2849$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6586$2178_Y - connect \Y $and$ls180.v:6586$2179_Y + connect \A \cmd_consumed + connect \Y $not$ls180.v:2849$560_Y end - attribute \src "ls180.v:6586.38-6586.148" - cell $and $and$ls180.v:6586$2181 + attribute \src "ls180.v:2850.87-2850.102" + cell $not $not$ls180.v:2850$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6586$2179_Y - connect \B $eq$ls180.v:6586$2180_Y - connect \Y $and$ls180.v:6586$2181_Y + connect \A \wdata_consumed + connect \Y $not$ls180.v:2850$564_Y end - attribute \src "ls180.v:6588.38-6588.93" - cell $and $and$ls180.v:6588$2182 + attribute \src "ls180.v:2851.63-2851.83" + cell $not $not$ls180.v:2851$567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6588$2182_Y + connect \A \port_cmd_payload_we + connect \Y $not$ls180.v:2851$567_Y end - attribute \src "ls180.v:6588.37-6588.144" - cell $and $and$ls180.v:6588$2184 + attribute \src "ls180.v:2852.71-2852.86" + cell $not $not$ls180.v:2852$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6588$2182_Y - connect \B $eq$ls180.v:6588$2183_Y - connect \Y $and$ls180.v:6588$2184_Y + connect \A \litedram_wb_we + connect \Y $not$ls180.v:2852$570_Y end - attribute \src "ls180.v:6589.38-6589.96" - cell $and $and$ls180.v:6589$2186 + attribute \src "ls180.v:2868.25-2868.44" + cell $not $not$ls180.v:2868$579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6589$2185_Y - connect \Y $and$ls180.v:6589$2186_Y + connect \A \tx_fifo_sink_ready + connect \Y $not$ls180.v:2868$579_Y end - attribute \src "ls180.v:6589.37-6589.147" - cell $and $and$ls180.v:6589$2188 + attribute \src "ls180.v:2869.26-2869.47" + cell $not $not$ls180.v:2869$580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6589$2186_Y - connect \B $eq$ls180.v:6589$2187_Y - connect \Y $and$ls180.v:6589$2188_Y + connect \A \tx_fifo_source_valid + connect \Y $not$ls180.v:2869$580_Y end - attribute \src "ls180.v:6591.37-6591.92" - cell $and $and$ls180.v:6591$2189 + attribute \src "ls180.v:2875.22-2875.41" + cell $not $not$ls180.v:2875$581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6591$2189_Y + connect \A \tx_fifo_sink_ready + connect \Y $not$ls180.v:2875$581_Y end - attribute \src "ls180.v:6591.36-6591.143" - cell $and $and$ls180.v:6591$2191 + attribute \src "ls180.v:2881.26-2881.47" + cell $not $not$ls180.v:2881$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6591$2189_Y - connect \B $eq$ls180.v:6591$2190_Y - connect \Y $and$ls180.v:6591$2191_Y + connect \A \rx_fifo_source_valid + connect \Y $not$ls180.v:2881$582_Y end - attribute \src "ls180.v:6592.37-6592.95" - cell $and $and$ls180.v:6592$2193 + attribute \src "ls180.v:2882.25-2882.44" + cell $not $not$ls180.v:2882$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6592$2192_Y - connect \Y $and$ls180.v:6592$2193_Y + connect \A \rx_fifo_sink_ready + connect \Y $not$ls180.v:2882$583_Y end - attribute \src "ls180.v:6592.36-6592.146" - cell $and $and$ls180.v:6592$2195 + attribute \src "ls180.v:2885.22-2885.43" + cell $not $not$ls180.v:2885$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6592$2193_Y - connect \B $eq$ls180.v:6592$2194_Y - connect \Y $and$ls180.v:6592$2195_Y + connect \A \rx_fifo_source_valid + connect \Y $not$ls180.v:2885$586_Y end - attribute \src "ls180.v:6594.43-6594.98" - cell $and $and$ls180.v:6594$2196 + attribute \src "ls180.v:2923.61-2923.78" + cell $not $not$ls180.v:2923$596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6594$2196_Y + connect \A \tx_fifo_readable + connect \Y $not$ls180.v:2923$596_Y end - attribute \src "ls180.v:6594.42-6594.149" - cell $and $and$ls180.v:6594$2198 + attribute \src "ls180.v:2953.61-2953.78" + cell $not $not$ls180.v:2953$607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6594$2196_Y - connect \B $eq$ls180.v:6594$2197_Y - connect \Y $and$ls180.v:6594$2198_Y + connect \A \rx_fifo_readable + connect \Y $not$ls180.v:2953$607_Y end - attribute \src "ls180.v:6595.43-6595.101" - cell $and $and$ls180.v:6595$2200 + attribute \src "ls180.v:3148.81-3148.104" + cell $not $not$ls180.v:3148$657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6595$2199_Y - connect \Y $and$ls180.v:6595$2200_Y + connect \A \libresocsim_shared_ack + connect \Y $not$ls180.v:3148$657_Y end - attribute \src "ls180.v:6595.42-6595.152" - cell $and $and$ls180.v:6595$2202 + attribute \src "ls180.v:3165.71-3165.106" + cell $not $not$ls180.v:3165$681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6595$2200_Y - connect \B $eq$ls180.v:6595$2201_Y - connect \Y $and$ls180.v:6595$2202_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3165$681_Y end - attribute \src "ls180.v:6597.46-6597.101" - cell $and $and$ls180.v:6597$2203 + attribute \src "ls180.v:3168.73-3168.108" + cell $not $not$ls180.v:3168$688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6597$2203_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3168$688_Y end - attribute \src "ls180.v:6597.45-6597.152" - cell $and $and$ls180.v:6597$2205 + attribute \src "ls180.v:3171.73-3171.108" + cell $not $not$ls180.v:3171$695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6597$2203_Y - connect \B $eq$ls180.v:6597$2204_Y - connect \Y $and$ls180.v:6597$2205_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3171$695_Y end - attribute \src "ls180.v:6598.46-6598.104" - cell $and $and$ls180.v:6598$2207 + attribute \src "ls180.v:3174.73-3174.108" + cell $not $not$ls180.v:3174$702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6598$2206_Y - connect \Y $and$ls180.v:6598$2207_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3174$702_Y end - attribute \src "ls180.v:6598.45-6598.155" - cell $and $and$ls180.v:6598$2209 + attribute \src "ls180.v:3177.73-3177.108" + cell $not $not$ls180.v:3177$709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6598$2207_Y - connect \B $eq$ls180.v:6598$2208_Y - connect \Y $and$ls180.v:6598$2209_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3177$709_Y end - attribute \src "ls180.v:6600.46-6600.101" - cell $and $and$ls180.v:6600$2210 + attribute \src "ls180.v:3180.76-3180.111" + cell $not $not$ls180.v:3180$716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6600$2210_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3180$716_Y end - attribute \src "ls180.v:6600.45-6600.152" - cell $and $and$ls180.v:6600$2212 + attribute \src "ls180.v:3183.76-3183.111" + cell $not $not$ls180.v:3183$723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6600$2210_Y - connect \B $eq$ls180.v:6600$2211_Y - connect \Y $and$ls180.v:6600$2212_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3183$723_Y end - attribute \src "ls180.v:6601.46-6601.104" - cell $and $and$ls180.v:6601$2214 + attribute \src "ls180.v:3186.76-3186.111" + cell $not $not$ls180.v:3186$730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6601$2213_Y - connect \Y $and$ls180.v:6601$2214_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3186$730_Y end - attribute \src "ls180.v:6601.45-6601.155" - cell $and $and$ls180.v:6601$2216 + attribute \src "ls180.v:3189.76-3189.111" + cell $not $not$ls180.v:3189$737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6601$2214_Y - connect \B $eq$ls180.v:6601$2215_Y - connect \Y $and$ls180.v:6601$2216_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3189$737_Y end - attribute \src "ls180.v:6624.39-6624.94" - cell $and $and$ls180.v:6624$2219 + attribute \src "ls180.v:3203.68-3203.103" + cell $not $not$ls180.v:3203$745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6624$2219_Y + connect \A \libresocsim_interface1_bank_bus_we + connect \Y $not$ls180.v:3203$745_Y end - attribute \src "ls180.v:6624.38-6624.145" - cell $and $and$ls180.v:6624$2221 + attribute \src "ls180.v:3206.67-3206.102" + cell $not $not$ls180.v:3206$752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6624$2219_Y - connect \B $eq$ls180.v:6624$2220_Y - connect \Y $and$ls180.v:6624$2221_Y + connect \A \libresocsim_interface1_bank_bus_we + connect \Y $not$ls180.v:3206$752_Y end - attribute \src "ls180.v:6625.39-6625.97" - cell $and $and$ls180.v:6625$2223 + attribute \src "ls180.v:3209.69-3209.104" + cell $not $not$ls180.v:3209$759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6625$2222_Y - connect \Y $and$ls180.v:6625$2223_Y + connect \A \libresocsim_interface1_bank_bus_we + connect \Y $not$ls180.v:3209$759_Y end - attribute \src "ls180.v:6625.38-6625.148" - cell $and $and$ls180.v:6625$2225 + attribute \src "ls180.v:3217.68-3217.103" + cell $not $not$ls180.v:3217$767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6625$2223_Y - connect \B $eq$ls180.v:6625$2224_Y - connect \Y $and$ls180.v:6625$2225_Y + connect \A \libresocsim_interface2_bank_bus_we + connect \Y $not$ls180.v:3217$767_Y end - attribute \src "ls180.v:6627.39-6627.94" - cell $and $and$ls180.v:6627$2226 + attribute \src "ls180.v:3220.67-3220.102" + cell $not $not$ls180.v:3220$774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6627$2226_Y + connect \A \libresocsim_interface2_bank_bus_we + connect \Y $not$ls180.v:3220$774_Y end - attribute \src "ls180.v:6627.38-6627.145" - cell $and $and$ls180.v:6627$2228 + attribute \src "ls180.v:3223.69-3223.104" + cell $not $not$ls180.v:3223$781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6627$2226_Y - connect \B $eq$ls180.v:6627$2227_Y - connect \Y $and$ls180.v:6627$2228_Y + connect \A \libresocsim_interface2_bank_bus_we + connect \Y $not$ls180.v:3223$781_Y end - attribute \src "ls180.v:6628.39-6628.97" - cell $and $and$ls180.v:6628$2230 + attribute \src "ls180.v:3231.67-3231.102" + cell $not $not$ls180.v:3231$789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6628$2229_Y - connect \Y $and$ls180.v:6628$2230_Y + connect \A \libresocsim_interface3_bank_bus_we + connect \Y $not$ls180.v:3231$789_Y end - attribute \src "ls180.v:6628.38-6628.148" - cell $and $and$ls180.v:6628$2232 + attribute \src "ls180.v:3234.66-3234.101" + cell $not $not$ls180.v:3234$796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6628$2230_Y - connect \B $eq$ls180.v:6628$2231_Y - connect \Y $and$ls180.v:6628$2232_Y + connect \A \libresocsim_interface3_bank_bus_we + connect \Y $not$ls180.v:3234$796_Y end - attribute \src "ls180.v:6630.39-6630.94" - cell $and $and$ls180.v:6630$2233 + attribute \src "ls180.v:3245.78-3245.113" + cell $not $not$ls180.v:3245$804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6630$2233_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3245$804_Y end - attribute \src "ls180.v:6630.38-6630.145" - cell $and $and$ls180.v:6630$2235 + attribute \src "ls180.v:3248.82-3248.117" + cell $not $not$ls180.v:3248$811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6630$2233_Y - connect \B $eq$ls180.v:6630$2234_Y - connect \Y $and$ls180.v:6630$2235_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3248$811_Y end - attribute \src "ls180.v:6631.39-6631.97" - cell $and $and$ls180.v:6631$2237 + attribute \src "ls180.v:3251.63-3251.98" + cell $not $not$ls180.v:3251$818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6631$2236_Y - connect \Y $and$ls180.v:6631$2237_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3251$818_Y end - attribute \src "ls180.v:6631.38-6631.148" - cell $and $and$ls180.v:6631$2239 + attribute \src "ls180.v:3254.82-3254.117" + cell $not $not$ls180.v:3254$825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6631$2237_Y - connect \B $eq$ls180.v:6631$2238_Y - connect \Y $and$ls180.v:6631$2239_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3254$825_Y end - attribute \src "ls180.v:6633.39-6633.94" - cell $and $and$ls180.v:6633$2240 + attribute \src "ls180.v:3257.82-3257.117" + cell $not $not$ls180.v:3257$832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6633$2240_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3257$832_Y end - attribute \src "ls180.v:6633.38-6633.145" - cell $and $and$ls180.v:6633$2242 + attribute \src "ls180.v:3260.83-3260.118" + cell $not $not$ls180.v:3260$839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6633$2240_Y - connect \B $eq$ls180.v:6633$2241_Y - connect \Y $and$ls180.v:6633$2242_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3260$839_Y end - attribute \src "ls180.v:6634.39-6634.97" - cell $and $and$ls180.v:6634$2244 + attribute \src "ls180.v:3263.81-3263.116" + cell $not $not$ls180.v:3263$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6634$2243_Y - connect \Y $and$ls180.v:6634$2244_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3263$846_Y end - attribute \src "ls180.v:6634.38-6634.148" - cell $and $and$ls180.v:6634$2246 + attribute \src "ls180.v:3266.81-3266.116" + cell $not $not$ls180.v:3266$853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6634$2244_Y - connect \B $eq$ls180.v:6634$2245_Y - connect \Y $and$ls180.v:6634$2246_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3266$853_Y end - attribute \src "ls180.v:6636.41-6636.96" - cell $and $and$ls180.v:6636$2247 + attribute \src "ls180.v:3269.81-3269.116" + cell $not $not$ls180.v:3269$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6636$2247_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3269$860_Y end - attribute \src "ls180.v:6636.40-6636.147" - cell $and $and$ls180.v:6636$2249 + attribute \src "ls180.v:3272.81-3272.116" + cell $not $not$ls180.v:3272$867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6636$2247_Y - connect \B $eq$ls180.v:6636$2248_Y - connect \Y $and$ls180.v:6636$2249_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3272$867_Y end - attribute \src "ls180.v:6637.41-6637.99" - cell $and $and$ls180.v:6637$2251 + attribute \src "ls180.v:3290.70-3290.105" + cell $not $not$ls180.v:3290$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6637$2250_Y - connect \Y $and$ls180.v:6637$2251_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3290$875_Y end - attribute \src "ls180.v:6637.40-6637.150" - cell $and $and$ls180.v:6637$2253 + attribute \src "ls180.v:3293.70-3293.105" + cell $not $not$ls180.v:3293$882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6637$2251_Y - connect \B $eq$ls180.v:6637$2252_Y - connect \Y $and$ls180.v:6637$2253_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3293$882_Y end - attribute \src "ls180.v:6639.41-6639.96" - cell $and $and$ls180.v:6639$2254 + attribute \src "ls180.v:3296.70-3296.105" + cell $not $not$ls180.v:3296$889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6639$2254_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3296$889_Y end - attribute \src "ls180.v:6639.40-6639.147" - cell $and $and$ls180.v:6639$2256 + attribute \src "ls180.v:3299.70-3299.105" + cell $not $not$ls180.v:3299$896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6639$2254_Y - connect \B $eq$ls180.v:6639$2255_Y - connect \Y $and$ls180.v:6639$2256_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3299$896_Y end - attribute \src "ls180.v:6640.41-6640.99" - cell $and $and$ls180.v:6640$2258 + attribute \src "ls180.v:3302.72-3302.107" + cell $not $not$ls180.v:3302$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6640$2257_Y - connect \Y $and$ls180.v:6640$2258_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3302$903_Y end - attribute \src "ls180.v:6640.40-6640.150" - cell $and $and$ls180.v:6640$2260 + attribute \src "ls180.v:3305.72-3305.107" + cell $not $not$ls180.v:3305$910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6640$2258_Y - connect \B $eq$ls180.v:6640$2259_Y - connect \Y $and$ls180.v:6640$2260_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3305$910_Y end - attribute \src "ls180.v:6642.41-6642.96" - cell $and $and$ls180.v:6642$2261 + attribute \src "ls180.v:3308.72-3308.107" + cell $not $not$ls180.v:3308$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6642$2261_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3308$917_Y end - attribute \src "ls180.v:6642.40-6642.147" - cell $and $and$ls180.v:6642$2263 + attribute \src "ls180.v:3311.72-3311.107" + cell $not $not$ls180.v:3311$924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6642$2261_Y - connect \B $eq$ls180.v:6642$2262_Y - connect \Y $and$ls180.v:6642$2263_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3311$924_Y end - attribute \src "ls180.v:6643.41-6643.99" - cell $and $and$ls180.v:6643$2265 + attribute \src "ls180.v:3314.68-3314.103" + cell $not $not$ls180.v:3314$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6643$2264_Y - connect \Y $and$ls180.v:6643$2265_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3314$931_Y end - attribute \src "ls180.v:6643.40-6643.150" - cell $and $and$ls180.v:6643$2267 + attribute \src "ls180.v:3317.78-3317.113" + cell $not $not$ls180.v:3317$938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6643$2265_Y - connect \B $eq$ls180.v:6643$2266_Y - connect \Y $and$ls180.v:6643$2267_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3317$938_Y end - attribute \src "ls180.v:6645.41-6645.96" - cell $and $and$ls180.v:6645$2268 + attribute \src "ls180.v:3320.71-3320.106" + cell $not $not$ls180.v:3320$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6645$2268_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3320$945_Y end - attribute \src "ls180.v:6645.40-6645.147" - cell $and $and$ls180.v:6645$2270 + attribute \src "ls180.v:3323.71-3323.106" + cell $not $not$ls180.v:3323$952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6645$2268_Y - connect \B $eq$ls180.v:6645$2269_Y - connect \Y $and$ls180.v:6645$2270_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3323$952_Y end - attribute \src "ls180.v:6646.41-6646.99" - cell $and $and$ls180.v:6646$2272 + attribute \src "ls180.v:3326.71-3326.106" + cell $not $not$ls180.v:3326$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6646$2271_Y - connect \Y $and$ls180.v:6646$2272_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3326$959_Y end - attribute \src "ls180.v:6646.40-6646.150" - cell $and $and$ls180.v:6646$2274 + attribute \src "ls180.v:3329.71-3329.106" + cell $not $not$ls180.v:3329$966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6646$2272_Y - connect \B $eq$ls180.v:6646$2273_Y - connect \Y $and$ls180.v:6646$2274_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3329$966_Y end - attribute \src "ls180.v:6648.37-6648.92" - cell $and $and$ls180.v:6648$2275 + attribute \src "ls180.v:3332.75-3332.110" + cell $not $not$ls180.v:3332$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6648$2275_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3332$973_Y end - attribute \src "ls180.v:6648.36-6648.143" - cell $and $and$ls180.v:6648$2277 + attribute \src "ls180.v:3335.76-3335.111" + cell $not $not$ls180.v:3335$980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6648$2275_Y - connect \B $eq$ls180.v:6648$2276_Y - connect \Y $and$ls180.v:6648$2277_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3335$980_Y end - attribute \src "ls180.v:6649.37-6649.95" - cell $and $and$ls180.v:6649$2279 + attribute \src "ls180.v:3338.75-3338.110" + cell $not $not$ls180.v:3338$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6649$2278_Y - connect \Y $and$ls180.v:6649$2279_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3338$987_Y end - attribute \src "ls180.v:6649.36-6649.146" - cell $and $and$ls180.v:6649$2281 + attribute \src "ls180.v:3358.48-3358.83" + cell $not $not$ls180.v:3358$995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6649$2279_Y - connect \B $eq$ls180.v:6649$2280_Y - connect \Y $and$ls180.v:6649$2281_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3358$995_Y end - attribute \src "ls180.v:6651.47-6651.102" - cell $and $and$ls180.v:6651$2282 + attribute \src "ls180.v:3361.71-3361.106" + cell $not $not$ls180.v:3361$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6651$2282_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3361$1002_Y end - attribute \src "ls180.v:6651.46-6651.153" - cell $and $and$ls180.v:6651$2284 + attribute \src "ls180.v:3364.72-3364.107" + cell $not $not$ls180.v:3364$1009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6651$2282_Y - connect \B $eq$ls180.v:6651$2283_Y - connect \Y $and$ls180.v:6651$2284_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3364$1009_Y end - attribute \src "ls180.v:6652.47-6652.105" - cell $and $and$ls180.v:6652$2286 + attribute \src "ls180.v:3367.63-3367.98" + cell $not $not$ls180.v:3367$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6652$2285_Y - connect \Y $and$ls180.v:6652$2286_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3367$1016_Y end - attribute \src "ls180.v:6652.46-6652.156" - cell $and $and$ls180.v:6652$2288 + attribute \src "ls180.v:3370.64-3370.99" + cell $not $not$ls180.v:3370$1023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6652$2286_Y - connect \B $eq$ls180.v:6652$2287_Y - connect \Y $and$ls180.v:6652$2288_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3370$1023_Y end - attribute \src "ls180.v:6654.40-6654.95" - cell $and $and$ls180.v:6654$2289 + attribute \src "ls180.v:3373.75-3373.110" + cell $not $not$ls180.v:3373$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6654$2289_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3373$1030_Y end - attribute \src "ls180.v:6654.39-6654.147" - cell $and $and$ls180.v:6654$2291 + attribute \src "ls180.v:3376.72-3376.107" + cell $not $not$ls180.v:3376$1037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6654$2289_Y - connect \B $eq$ls180.v:6654$2290_Y - connect \Y $and$ls180.v:6654$2291_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3376$1037_Y end - attribute \src "ls180.v:6655.40-6655.98" - cell $and $and$ls180.v:6655$2293 + attribute \src "ls180.v:3379.71-3379.106" + cell $not $not$ls180.v:3379$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6655$2292_Y - connect \Y $and$ls180.v:6655$2293_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3379$1044_Y end - attribute \src "ls180.v:6655.39-6655.150" - cell $and $and$ls180.v:6655$2295 + attribute \src "ls180.v:3392.77-3392.112" + cell $not $not$ls180.v:3392$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6655$2293_Y - connect \B $eq$ls180.v:6655$2294_Y - connect \Y $and$ls180.v:6655$2295_Y + connect \A \libresocsim_interface7_bank_bus_we + connect \Y $not$ls180.v:3392$1052_Y end - attribute \src "ls180.v:6657.40-6657.95" - cell $and $and$ls180.v:6657$2296 + attribute \src "ls180.v:3395.77-3395.112" + cell $not $not$ls180.v:3395$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6657$2296_Y + connect \A \libresocsim_interface7_bank_bus_we + connect \Y $not$ls180.v:3395$1059_Y end - attribute \src "ls180.v:6657.39-6657.147" - cell $and $and$ls180.v:6657$2298 + attribute \src "ls180.v:3398.77-3398.112" + cell $not $not$ls180.v:3398$1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6657$2296_Y - connect \B $eq$ls180.v:6657$2297_Y - connect \Y $and$ls180.v:6657$2298_Y + connect \A \libresocsim_interface7_bank_bus_we + connect \Y $not$ls180.v:3398$1066_Y end - attribute \src "ls180.v:6658.40-6658.98" - cell $and $and$ls180.v:6658$2300 + attribute \src "ls180.v:3401.77-3401.112" + cell $not $not$ls180.v:3401$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6658$2299_Y - connect \Y $and$ls180.v:6658$2300_Y + connect \A \libresocsim_interface7_bank_bus_we + connect \Y $not$ls180.v:3401$1073_Y end - attribute \src "ls180.v:6658.39-6658.150" - cell $and $and$ls180.v:6658$2302 + attribute \src "ls180.v:3761.68-3761.317" + cell $not $not$ls180.v:3761$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6658$2300_Y - connect \B $eq$ls180.v:6658$2301_Y - connect \Y $and$ls180.v:6658$2302_Y + connect \A $or$ls180.v:3761$1114_Y + connect \Y $not$ls180.v:3761$1115_Y end - attribute \src "ls180.v:6660.40-6660.95" - cell $and $and$ls180.v:6660$2303 + attribute \src "ls180.v:3785.68-3785.317" + cell $not $not$ls180.v:3785$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6660$2303_Y + connect \A $or$ls180.v:3785$1130_Y + connect \Y $not$ls180.v:3785$1131_Y end - attribute \src "ls180.v:6660.39-6660.147" - cell $and $and$ls180.v:6660$2305 + attribute \src "ls180.v:3809.68-3809.317" + cell $not $not$ls180.v:3809$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6660$2303_Y - connect \B $eq$ls180.v:6660$2304_Y - connect \Y $and$ls180.v:6660$2305_Y + connect \A $or$ls180.v:3809$1146_Y + connect \Y $not$ls180.v:3809$1147_Y end - attribute \src "ls180.v:6661.40-6661.98" - cell $and $and$ls180.v:6661$2307 + attribute \src "ls180.v:3833.68-3833.317" + cell $not $not$ls180.v:3833$1163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6661$2306_Y - connect \Y $and$ls180.v:6661$2307_Y + connect \A $or$ls180.v:3833$1162_Y + connect \Y $not$ls180.v:3833$1163_Y end - attribute \src "ls180.v:6661.39-6661.150" - cell $and $and$ls180.v:6661$2309 + attribute \src "ls180.v:4361.62-4361.86" + cell $not $not$ls180.v:4361$1258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6661$2307_Y - connect \B $eq$ls180.v:6661$2308_Y - connect \Y $and$ls180.v:6661$2309_Y + connect \A \libresocsim_ram_bus_ack + connect \Y $not$ls180.v:4361$1258_Y end - attribute \src "ls180.v:6663.40-6663.95" - cell $and $and$ls180.v:6663$2310 + attribute \src "ls180.v:4380.8-4380.33" + cell $not $not$ls180.v:4380$1262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6663$2310_Y + connect \A \libresocsim_zero_trigger + connect \Y $not$ls180.v:4380$1262_Y end - attribute \src "ls180.v:6663.39-6663.147" - cell $and $and$ls180.v:6663$2312 + attribute \src "ls180.v:4384.54-4384.74" + cell $not $not$ls180.v:4384$1265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6663$2310_Y - connect \B $eq$ls180.v:6663$2311_Y - connect \Y $and$ls180.v:6663$2312_Y + connect \A \ram_bus_ram_bus_ack + connect \Y $not$ls180.v:4384$1265_Y end - attribute \src "ls180.v:6664.40-6664.98" - cell $and $and$ls180.v:6664$2314 + attribute \src "ls180.v:4392.27-4392.45" + cell $not $not$ls180.v:4392$1267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6664$2313_Y - connect \Y $and$ls180.v:6664$2314_Y + connect \A \sdram_timer_done0 + connect \Y $not$ls180.v:4392$1267_Y end - attribute \src "ls180.v:6664.39-6664.150" - cell $and $and$ls180.v:6664$2316 + attribute \src "ls180.v:4462.126-4462.174" + cell $not $not$ls180.v:4462$1282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6664$2314_Y - connect \B $eq$ls180.v:6664$2315_Y - connect \Y $and$ls180.v:6664$2316_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4462$1282_Y end - attribute \src "ls180.v:6666.52-6666.107" - cell $and $and$ls180.v:6666$2317 + attribute \src "ls180.v:4468.126-4468.174" + cell $not $not$ls180.v:4468$1287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6666$2317_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4468$1287_Y end - attribute \src "ls180.v:6666.51-6666.159" - cell $and $and$ls180.v:6666$2319 + attribute \src "ls180.v:4469.8-4469.56" + cell $not $not$ls180.v:4469$1289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6666$2317_Y - connect \B $eq$ls180.v:6666$2318_Y - connect \Y $and$ls180.v:6666$2319_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:4469$1289_Y end - attribute \src "ls180.v:6667.52-6667.110" - cell $and $and$ls180.v:6667$2321 + attribute \src "ls180.v:4477.8-4477.51" + cell $not $not$ls180.v:4477$1292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6667$2320_Y - connect \Y $and$ls180.v:6667$2321_Y + connect \A \sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:4477$1292_Y end - attribute \src "ls180.v:6667.51-6667.162" - cell $and $and$ls180.v:6667$2323 + attribute \src "ls180.v:4492.8-4492.41" + cell $not $not$ls180.v:4492$1294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6667$2321_Y - connect \B $eq$ls180.v:6667$2322_Y - connect \Y $and$ls180.v:6667$2323_Y + connect \A \sdram_bankmachine0_twtpcon_ready + connect \Y $not$ls180.v:4492$1294_Y end - attribute \src "ls180.v:6669.53-6669.108" - cell $and $and$ls180.v:6669$2324 + attribute \src "ls180.v:4508.126-4508.174" + cell $not $not$ls180.v:4508$1298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6669$2324_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4508$1298_Y end - attribute \src "ls180.v:6669.52-6669.160" - cell $and $and$ls180.v:6669$2326 + attribute \src "ls180.v:4514.126-4514.174" + cell $not $not$ls180.v:4514$1303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6669$2324_Y - connect \B $eq$ls180.v:6669$2325_Y - connect \Y $and$ls180.v:6669$2326_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4514$1303_Y end - attribute \src "ls180.v:6670.53-6670.111" - cell $and $and$ls180.v:6670$2328 + attribute \src "ls180.v:4515.8-4515.56" + cell $not $not$ls180.v:4515$1305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6670$2327_Y - connect \Y $and$ls180.v:6670$2328_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:4515$1305_Y end - attribute \src "ls180.v:6670.52-6670.163" - cell $and $and$ls180.v:6670$2330 + attribute \src "ls180.v:4523.8-4523.51" + cell $not $not$ls180.v:4523$1308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6670$2328_Y - connect \B $eq$ls180.v:6670$2329_Y - connect \Y $and$ls180.v:6670$2330_Y + connect \A \sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:4523$1308_Y end - attribute \src "ls180.v:6672.44-6672.99" - cell $and $and$ls180.v:6672$2331 + attribute \src "ls180.v:4538.8-4538.41" + cell $not $not$ls180.v:4538$1310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6672$2331_Y + connect \A \sdram_bankmachine1_twtpcon_ready + connect \Y $not$ls180.v:4538$1310_Y end - attribute \src "ls180.v:6672.43-6672.151" - cell $and $and$ls180.v:6672$2333 + attribute \src "ls180.v:4554.126-4554.174" + cell $not $not$ls180.v:4554$1314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6672$2331_Y - connect \B $eq$ls180.v:6672$2332_Y - connect \Y $and$ls180.v:6672$2333_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4554$1314_Y end - attribute \src "ls180.v:6673.44-6673.102" - cell $and $and$ls180.v:6673$2335 + attribute \src "ls180.v:4560.126-4560.174" + cell $not $not$ls180.v:4560$1319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6673$2334_Y - connect \Y $and$ls180.v:6673$2335_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4560$1319_Y end - attribute \src "ls180.v:6673.43-6673.154" - cell $and $and$ls180.v:6673$2337 + attribute \src "ls180.v:4561.8-4561.56" + cell $not $not$ls180.v:4561$1321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6673$2335_Y - connect \B $eq$ls180.v:6673$2336_Y - connect \Y $and$ls180.v:6673$2337_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:4561$1321_Y end - attribute \src "ls180.v:6692.30-6692.85" - cell $and $and$ls180.v:6692$2339 + attribute \src "ls180.v:4569.8-4569.51" + cell $not $not$ls180.v:4569$1324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6692$2339_Y + connect \A \sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:4569$1324_Y end - attribute \src "ls180.v:6692.29-6692.136" - cell $and $and$ls180.v:6692$2341 + attribute \src "ls180.v:4584.8-4584.41" + cell $not $not$ls180.v:4584$1326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6692$2339_Y - connect \B $eq$ls180.v:6692$2340_Y - connect \Y $and$ls180.v:6692$2341_Y + connect \A \sdram_bankmachine2_twtpcon_ready + connect \Y $not$ls180.v:4584$1326_Y end - attribute \src "ls180.v:6693.30-6693.88" - cell $and $and$ls180.v:6693$2343 + attribute \src "ls180.v:4600.126-4600.174" + cell $not $not$ls180.v:4600$1330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6693$2342_Y - connect \Y $and$ls180.v:6693$2343_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4600$1330_Y end - attribute \src "ls180.v:6693.29-6693.139" - cell $and $and$ls180.v:6693$2345 + attribute \src "ls180.v:4606.126-4606.174" + cell $not $not$ls180.v:4606$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6693$2343_Y - connect \B $eq$ls180.v:6693$2344_Y - connect \Y $and$ls180.v:6693$2345_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4606$1335_Y end - attribute \src "ls180.v:6695.40-6695.95" - cell $and $and$ls180.v:6695$2346 + attribute \src "ls180.v:4607.8-4607.56" + cell $not $not$ls180.v:4607$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6695$2346_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:4607$1337_Y end - attribute \src "ls180.v:6695.39-6695.146" - cell $and $and$ls180.v:6695$2348 + attribute \src "ls180.v:4615.8-4615.51" + cell $not $not$ls180.v:4615$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6695$2346_Y - connect \B $eq$ls180.v:6695$2347_Y - connect \Y $and$ls180.v:6695$2348_Y + connect \A \sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:4615$1340_Y end - attribute \src "ls180.v:6696.40-6696.98" - cell $and $and$ls180.v:6696$2350 + attribute \src "ls180.v:4630.8-4630.41" + cell $not $not$ls180.v:4630$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6696$2349_Y - connect \Y $and$ls180.v:6696$2350_Y + connect \A \sdram_bankmachine3_twtpcon_ready + connect \Y $not$ls180.v:4630$1342_Y end - attribute \src "ls180.v:6696.39-6696.149" - cell $and $and$ls180.v:6696$2352 + attribute \src "ls180.v:4638.7-4638.17" + cell $not $not$ls180.v:4638$1345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6696$2350_Y - connect \B $eq$ls180.v:6696$2351_Y - connect \Y $and$ls180.v:6696$2352_Y + connect \A \sdram_en0 + connect \Y $not$ls180.v:4638$1345_Y end - attribute \src "ls180.v:6698.41-6698.96" - cell $and $and$ls180.v:6698$2353 + attribute \src "ls180.v:4641.8-4641.24" + cell $not $not$ls180.v:4641$1346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6698$2353_Y + connect \A \sdram_max_time0 + connect \Y $not$ls180.v:4641$1346_Y end - attribute \src "ls180.v:6698.40-6698.147" - cell $and $and$ls180.v:6698$2355 + attribute \src "ls180.v:4645.7-4645.17" + cell $not $not$ls180.v:4645$1348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6698$2353_Y - connect \B $eq$ls180.v:6698$2354_Y - connect \Y $and$ls180.v:6698$2355_Y + connect \A \sdram_en1 + connect \Y $not$ls180.v:4645$1348_Y end - attribute \src "ls180.v:6699.41-6699.99" - cell $and $and$ls180.v:6699$2357 + attribute \src "ls180.v:4648.8-4648.24" + cell $not $not$ls180.v:4648$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6699$2356_Y - connect \Y $and$ls180.v:6699$2357_Y + connect \A \sdram_max_time1 + connect \Y $not$ls180.v:4648$1349_Y end - attribute \src "ls180.v:6699.40-6699.150" - cell $and $and$ls180.v:6699$2359 + attribute \src "ls180.v:4767.25-4767.38" + cell $not $not$ls180.v:4767$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6699$2357_Y - connect \B $eq$ls180.v:6699$2358_Y - connect \Y $and$ls180.v:6699$2359_Y + connect \A \array_muxed2 + connect \Y $not$ls180.v:4767$1351_Y end - attribute \src "ls180.v:6701.45-6701.100" - cell $and $and$ls180.v:6701$2360 + attribute \src "ls180.v:4768.25-4768.38" + cell $not $not$ls180.v:4768$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6701$2360_Y + connect \A \array_muxed3 + connect \Y $not$ls180.v:4768$1352_Y end - attribute \src "ls180.v:6701.44-6701.151" - cell $and $and$ls180.v:6701$2362 + attribute \src "ls180.v:4769.24-4769.37" + cell $not $not$ls180.v:4769$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6701$2360_Y - connect \B $eq$ls180.v:6701$2361_Y - connect \Y $and$ls180.v:6701$2362_Y + connect \A \array_muxed4 + connect \Y $not$ls180.v:4769$1353_Y end - attribute \src "ls180.v:6702.45-6702.103" - cell $and $and$ls180.v:6702$2364 + attribute \src "ls180.v:4780.8-4780.28" + cell $not $not$ls180.v:4780$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6702$2363_Y - connect \Y $and$ls180.v:6702$2364_Y + connect \A \sdram_tccdcon_ready + connect \Y $not$ls180.v:4780$1354_Y end - attribute \src "ls180.v:6702.44-6702.154" - cell $and $and$ls180.v:6702$2366 + attribute \src "ls180.v:4795.8-4795.28" + cell $not $not$ls180.v:4795$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6702$2364_Y - connect \B $eq$ls180.v:6702$2365_Y - connect \Y $and$ls180.v:6702$2366_Y + connect \A \sdram_twtrcon_ready + connect \Y $not$ls180.v:4795$1357_Y end - attribute \src "ls180.v:6704.46-6704.101" - cell $and $and$ls180.v:6704$2367 + attribute \src "ls180.v:4831.31-4831.48" + cell $not $not$ls180.v:4831$1387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6704$2367_Y + connect \A \uart_phy_tx_busy + connect \Y $not$ls180.v:4831$1387_Y end - attribute \src "ls180.v:6704.45-6704.152" - cell $and $and$ls180.v:6704$2369 + attribute \src "ls180.v:4831.54-4831.74" + cell $not $not$ls180.v:4831$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6704$2367_Y - connect \B $eq$ls180.v:6704$2368_Y - connect \Y $and$ls180.v:6704$2369_Y + connect \A \uart_phy_sink_ready + connect \Y $not$ls180.v:4831$1389_Y end - attribute \src "ls180.v:6705.46-6705.104" - cell $and $and$ls180.v:6705$2371 + attribute \src "ls180.v:4860.7-4860.24" + cell $not $not$ls180.v:4860$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6705$2370_Y - connect \Y $and$ls180.v:6705$2371_Y + connect \A \uart_phy_rx_busy + connect \Y $not$ls180.v:4860$1396_Y end - attribute \src "ls180.v:6705.45-6705.155" - cell $and $and$ls180.v:6705$2373 + attribute \src "ls180.v:4861.9-4861.21" + cell $not $not$ls180.v:4861$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6705$2371_Y - connect \B $eq$ls180.v:6705$2372_Y - connect \Y $and$ls180.v:6705$2373_Y + connect \A \uart_phy_rx + connect \Y $not$ls180.v:4861$1397_Y end - attribute \src "ls180.v:6707.44-6707.99" - cell $and $and$ls180.v:6707$2374 + attribute \src "ls180.v:4894.8-4894.19" + cell $not $not$ls180.v:4894$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6707$2374_Y + connect \A \tx_trigger + connect \Y $not$ls180.v:4894$1403_Y end - attribute \src "ls180.v:6707.43-6707.150" - cell $and $and$ls180.v:6707$2376 + attribute \src "ls180.v:4901.8-4901.19" + cell $not $not$ls180.v:4901$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6707$2374_Y - connect \B $eq$ls180.v:6707$2375_Y - connect \Y $and$ls180.v:6707$2376_Y + connect \A \rx_trigger + connect \Y $not$ls180.v:4901$1405_Y end - attribute \src "ls180.v:6708.44-6708.102" - cell $and $and$ls180.v:6708$2378 + attribute \src "ls180.v:4911.60-4911.76" + cell $not $not$ls180.v:4911$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6708$2377_Y - connect \Y $and$ls180.v:6708$2378_Y + connect \A \tx_fifo_replace + connect \Y $not$ls180.v:4911$1408_Y end - attribute \src "ls180.v:6708.43-6708.153" - cell $and $and$ls180.v:6708$2380 + attribute \src "ls180.v:4917.60-4917.76" + cell $not $not$ls180.v:4917$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6708$2378_Y - connect \B $eq$ls180.v:6708$2379_Y - connect \Y $and$ls180.v:6708$2380_Y + connect \A \tx_fifo_replace + connect \Y $not$ls180.v:4917$1413_Y end - attribute \src "ls180.v:6710.41-6710.96" - cell $and $and$ls180.v:6710$2381 + attribute \src "ls180.v:4918.8-4918.24" + cell $not $not$ls180.v:4918$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6710$2381_Y + connect \A \tx_fifo_do_read + connect \Y $not$ls180.v:4918$1415_Y end - attribute \src "ls180.v:6710.40-6710.147" - cell $and $and$ls180.v:6710$2383 + attribute \src "ls180.v:4933.60-4933.76" + cell $not $not$ls180.v:4933$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6710$2381_Y - connect \B $eq$ls180.v:6710$2382_Y - connect \Y $and$ls180.v:6710$2383_Y + connect \A \rx_fifo_replace + connect \Y $not$ls180.v:4933$1419_Y end - attribute \src "ls180.v:6711.41-6711.99" - cell $and $and$ls180.v:6711$2385 + attribute \src "ls180.v:4939.60-4939.76" + cell $not $not$ls180.v:4939$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6711$2384_Y - connect \Y $and$ls180.v:6711$2385_Y + connect \A \rx_fifo_replace + connect \Y $not$ls180.v:4939$1424_Y end - attribute \src "ls180.v:6711.40-6711.150" - cell $and $and$ls180.v:6711$2387 + attribute \src "ls180.v:4940.8-4940.24" + cell $not $not$ls180.v:4940$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6711$2385_Y - connect \B $eq$ls180.v:6711$2386_Y - connect \Y $and$ls180.v:6711$2387_Y + connect \A \rx_fifo_do_read + connect \Y $not$ls180.v:4940$1426_Y end - attribute \src "ls180.v:6713.40-6713.95" - cell $and $and$ls180.v:6713$2388 + attribute \src "ls180.v:4974.9-4974.32" + cell $not $not$ls180.v:4974$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6713$2388_Y + connect \A \libresocsim_request [0] + connect \Y $not$ls180.v:4974$1429_Y end - attribute \src "ls180.v:6713.39-6713.146" - cell $and $and$ls180.v:6713$2390 + attribute \src "ls180.v:4985.9-4985.32" + cell $not $not$ls180.v:4985$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6713$2388_Y - connect \B $eq$ls180.v:6713$2389_Y - connect \Y $and$ls180.v:6713$2390_Y + connect \A \libresocsim_request [1] + connect \Y $not$ls180.v:4985$1430_Y end - attribute \src "ls180.v:6714.40-6714.98" - cell $and $and$ls180.v:6714$2392 + attribute \src "ls180.v:4996.9-4996.32" + cell $not $not$ls180.v:4996$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6714$2391_Y - connect \Y $and$ls180.v:6714$2392_Y + connect \A \libresocsim_request [2] + connect \Y $not$ls180.v:4996$1431_Y end - attribute \src "ls180.v:6714.39-6714.149" - cell $and $and$ls180.v:6714$2394 + attribute \src "ls180.v:5009.8-5009.25" + cell $not $not$ls180.v:5009$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6714$2392_Y - connect \B $eq$ls180.v:6714$2393_Y - connect \Y $and$ls180.v:6714$2394_Y + connect \A \libresocsim_done + connect \Y $not$ls180.v:5009$1432_Y end - attribute \src "ls180.v:6726.46-6726.101" - cell $and $and$ls180.v:6726$2396 + attribute \src "ls180.v:1560.10-1560.86" + cell $or $or$ls180.v:1560$24 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6726$2396_Y + connect \A \libresocsim_interface0_converted_interface_ack + connect \B \libresocsim_converter0_skip + connect \Y $or$ls180.v:1560$24_Y end - attribute \src "ls180.v:6726.45-6726.152" - cell $and $and$ls180.v:6726$2398 + attribute \src "ls180.v:1620.10-1620.86" + cell $or $or$ls180.v:1620$35 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6726$2396_Y - connect \B $eq$ls180.v:6726$2397_Y - connect \Y $and$ls180.v:6726$2398_Y + connect \A \libresocsim_interface1_converted_interface_ack + connect \B \libresocsim_converter1_skip + connect \Y $or$ls180.v:1620$35_Y end - attribute \src "ls180.v:6727.46-6727.104" - cell $and $and$ls180.v:6727$2400 + attribute \src "ls180.v:1680.10-1680.86" + cell $or $or$ls180.v:1680$46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6727$2399_Y - connect \Y $and$ls180.v:6727$2400_Y + connect \A \libresocsim_interface2_converted_interface_ack + connect \B \libresocsim_converter2_skip + connect \Y $or$ls180.v:1680$46_Y end - attribute \src "ls180.v:6727.45-6727.155" - cell $and $and$ls180.v:6727$2402 + attribute \src "ls180.v:1882.34-1882.90" + cell $or $or$ls180.v:1882$91 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6727$2400_Y - connect \B $eq$ls180.v:6727$2401_Y - connect \Y $and$ls180.v:6727$2402_Y + connect \A \sdram_sequencer_start0 + connect \B $ne$ls180.v:1882$90_Y + connect \Y $or$ls180.v:1882$91_Y end - attribute \src "ls180.v:6729.46-6729.101" - cell $and $and$ls180.v:6729$2403 + attribute \src "ls180.v:1925.54-1925.125" + cell $or $or$ls180.v:1925$95 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6729$2403_Y + connect \A \sdram_bankmachine0_req_wdata_ready + connect \B \sdram_bankmachine0_req_rdata_valid + connect \Y $or$ls180.v:1925$95_Y end - attribute \src "ls180.v:6729.45-6729.152" - cell $and $and$ls180.v:6729$2405 + attribute \src "ls180.v:1926.39-1926.136" + cell $or $or$ls180.v:1926$96 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6729$2403_Y - connect \B $eq$ls180.v:6729$2404_Y - connect \Y $and$ls180.v:6729$2405_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $or$ls180.v:1926$96_Y end - attribute \src "ls180.v:6730.46-6730.104" - cell $and $and$ls180.v:6730$2407 + attribute \src "ls180.v:1934.40-1934.155" + cell $or $or$ls180.v:1934$100 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6730$2406_Y - connect \Y $and$ls180.v:6730$2407_Y + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:1934$99_Y + connect \B { 4'0000 \sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:1934$100_Y end - attribute \src "ls180.v:6730.45-6730.155" - cell $and $and$ls180.v:6730$2409 + attribute \src "ls180.v:1971.117-1971.225" + cell $or $or$ls180.v:1971$113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6730$2407_Y - connect \B $eq$ls180.v:6730$2408_Y - connect \Y $and$ls180.v:6730$2409_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \B \sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:1971$113_Y end - attribute \src "ls180.v:6732.46-6732.101" - cell $and $and$ls180.v:6732$2410 + attribute \src "ls180.v:1977.52-1977.142" + cell $or $or$ls180.v:1977$119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6732$2410_Y + connect \A $not$ls180.v:1977$118_Y + connect \B \sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:1977$119_Y end - attribute \src "ls180.v:6732.45-6732.152" - cell $and $and$ls180.v:6732$2412 + attribute \src "ls180.v:2082.54-2082.125" + cell $or $or$ls180.v:2082$125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6732$2410_Y - connect \B $eq$ls180.v:6732$2411_Y - connect \Y $and$ls180.v:6732$2412_Y + connect \A \sdram_bankmachine1_req_wdata_ready + connect \B \sdram_bankmachine1_req_rdata_valid + connect \Y $or$ls180.v:2082$125_Y end - attribute \src "ls180.v:6733.46-6733.104" - cell $and $and$ls180.v:6733$2414 + attribute \src "ls180.v:2083.39-2083.136" + cell $or $or$ls180.v:2083$126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6733$2413_Y - connect \Y $and$ls180.v:6733$2414_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $or$ls180.v:2083$126_Y end - attribute \src "ls180.v:6733.45-6733.155" - cell $and $and$ls180.v:6733$2416 + attribute \src "ls180.v:2091.40-2091.155" + cell $or $or$ls180.v:2091$130 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6733$2414_Y - connect \B $eq$ls180.v:6733$2415_Y - connect \Y $and$ls180.v:6733$2416_Y + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:2091$129_Y + connect \B { 4'0000 \sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:2091$130_Y end - attribute \src "ls180.v:6735.46-6735.101" - cell $and $and$ls180.v:6735$2417 + attribute \src "ls180.v:2128.117-2128.225" + cell $or $or$ls180.v:2128$143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6735$2417_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \B \sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:2128$143_Y end - attribute \src "ls180.v:6735.45-6735.152" - cell $and $and$ls180.v:6735$2419 + attribute \src "ls180.v:2134.52-2134.142" + cell $or $or$ls180.v:2134$149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6735$2417_Y - connect \B $eq$ls180.v:6735$2418_Y - connect \Y $and$ls180.v:6735$2419_Y + connect \A $not$ls180.v:2134$148_Y + connect \B \sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:2134$149_Y end - attribute \src "ls180.v:6736.46-6736.104" - cell $and $and$ls180.v:6736$2421 + attribute \src "ls180.v:2239.54-2239.125" + cell $or $or$ls180.v:2239$155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6736$2420_Y - connect \Y $and$ls180.v:6736$2421_Y + connect \A \sdram_bankmachine2_req_wdata_ready + connect \B \sdram_bankmachine2_req_rdata_valid + connect \Y $or$ls180.v:2239$155_Y end - attribute \src "ls180.v:6736.45-6736.155" - cell $and $and$ls180.v:6736$2423 + attribute \src "ls180.v:2240.39-2240.136" + cell $or $or$ls180.v:2240$156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6736$2421_Y - connect \B $eq$ls180.v:6736$2422_Y - connect \Y $and$ls180.v:6736$2423_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $or$ls180.v:2240$156_Y end - attribute \src "ls180.v:7117.109-7117.178" - cell $and $and$ls180.v:7117$2461 + attribute \src "ls180.v:2248.40-2248.155" + cell $or $or$ls180.v:2248$160 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:7117$2460_Y - connect \Y $and$ls180.v:7117$2461_Y + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:2248$159_Y + connect \B { 4'0000 \sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:2248$160_Y end - attribute \src "ls180.v:7117.184-7117.253" - cell $and $and$ls180.v:7117$2464 + attribute \src "ls180.v:2285.117-2285.225" + cell $or $or$ls180.v:2285$173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:7117$2463_Y - connect \Y $and$ls180.v:7117$2464_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \B \sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:2285$173_Y end - attribute \src "ls180.v:7117.259-7117.328" - cell $and $and$ls180.v:7117$2467 + attribute \src "ls180.v:2291.52-2291.142" + cell $or $or$ls180.v:2291$179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:7117$2466_Y - connect \Y $and$ls180.v:7117$2467_Y + connect \A $not$ls180.v:2291$178_Y + connect \B \sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:2291$179_Y end - attribute \src "ls180.v:7117.40-7117.331" - cell $and $and$ls180.v:7117$2470 + attribute \src "ls180.v:2396.54-2396.125" + cell $or $or$ls180.v:2396$185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7117$2459_Y - connect \B $not$ls180.v:7117$2469_Y - connect \Y $and$ls180.v:7117$2470_Y + connect \A \sdram_bankmachine3_req_wdata_ready + connect \B \sdram_bankmachine3_req_rdata_valid + connect \Y $or$ls180.v:2396$185_Y end - attribute \src "ls180.v:7117.39-7117.354" - cell $and $and$ls180.v:7117$2471 + attribute \src "ls180.v:2397.39-2397.136" + cell $or $or$ls180.v:2397$186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7117$2470_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7117$2471_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $or$ls180.v:2397$186_Y end - attribute \src "ls180.v:7141.109-7141.178" - cell $and $and$ls180.v:7141$2477 + attribute \src "ls180.v:2405.40-2405.155" + cell $or $or$ls180.v:2405$190 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:7141$2476_Y - connect \Y $and$ls180.v:7141$2477_Y + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:2405$189_Y + connect \B { 4'0000 \sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:2405$190_Y end - attribute \src "ls180.v:7141.184-7141.253" - cell $and $and$ls180.v:7141$2480 + attribute \src "ls180.v:2442.117-2442.225" + cell $or $or$ls180.v:2442$203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:7141$2479_Y - connect \Y $and$ls180.v:7141$2480_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \B \sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:2442$203_Y end - attribute \src "ls180.v:7141.259-7141.328" - cell $and $and$ls180.v:7141$2483 + attribute \src "ls180.v:2448.52-2448.142" + cell $or $or$ls180.v:2448$209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:7141$2482_Y - connect \Y $and$ls180.v:7141$2483_Y + connect \A $not$ls180.v:2448$208_Y + connect \B \sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:2448$209_Y end - attribute \src "ls180.v:7141.40-7141.331" - cell $and $and$ls180.v:7141$2486 + attribute \src "ls180.v:2547.92-2547.168" + cell $or $or$ls180.v:2547$229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7141$2475_Y - connect \B $not$ls180.v:7141$2485_Y - connect \Y $and$ls180.v:7141$2486_Y + connect \A \sdram_choose_req_cmd_payload_is_write + connect \B \sdram_choose_req_cmd_payload_is_read + connect \Y $or$ls180.v:2547$229_Y end - attribute \src "ls180.v:7141.39-7141.354" - cell $and $and$ls180.v:7141$2487 + attribute \src "ls180.v:2550.34-2550.179" + cell $or $or$ls180.v:2550$235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7141$2486_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7141$2487_Y + connect \A $and$ls180.v:2550$233_Y + connect \B $and$ls180.v:2550$234_Y + connect \Y $or$ls180.v:2550$235_Y end - attribute \src "ls180.v:7165.109-7165.178" - cell $and $and$ls180.v:7165$2493 + attribute \src "ls180.v:2550.33-2550.254" + cell $or $or$ls180.v:2550$237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:7165$2492_Y - connect \Y $and$ls180.v:7165$2493_Y + connect \A $or$ls180.v:2550$235_Y + connect \B $and$ls180.v:2550$236_Y + connect \Y $or$ls180.v:2550$237_Y end - attribute \src "ls180.v:7165.184-7165.253" - cell $and $and$ls180.v:7165$2496 + attribute \src "ls180.v:2550.32-2550.329" + cell $or $or$ls180.v:2550$239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:7165$2495_Y - connect \Y $and$ls180.v:7165$2496_Y + connect \A $or$ls180.v:2550$237_Y + connect \B $and$ls180.v:2550$238_Y + connect \Y $or$ls180.v:2550$239_Y end - attribute \src "ls180.v:7165.259-7165.328" - cell $and $and$ls180.v:7165$2499 + attribute \src "ls180.v:2551.35-2551.182" + cell $or $or$ls180.v:2551$242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:7165$2498_Y - connect \Y $and$ls180.v:7165$2499_Y + connect \A $and$ls180.v:2551$240_Y + connect \B $and$ls180.v:2551$241_Y + connect \Y $or$ls180.v:2551$242_Y end - attribute \src "ls180.v:7165.40-7165.331" - cell $and $and$ls180.v:7165$2502 + attribute \src "ls180.v:2551.34-2551.258" + cell $or $or$ls180.v:2551$244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7165$2491_Y - connect \B $not$ls180.v:7165$2501_Y - connect \Y $and$ls180.v:7165$2502_Y + connect \A $or$ls180.v:2551$242_Y + connect \B $and$ls180.v:2551$243_Y + connect \Y $or$ls180.v:2551$244_Y end - attribute \src "ls180.v:7165.39-7165.354" - cell $and $and$ls180.v:7165$2503 + attribute \src "ls180.v:2551.33-2551.334" + cell $or $or$ls180.v:2551$246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7165$2502_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7165$2503_Y + connect \A $or$ls180.v:2551$244_Y + connect \B $and$ls180.v:2551$245_Y + connect \Y $or$ls180.v:2551$246_Y end - attribute \src "ls180.v:7189.109-7189.178" - cell $and $and$ls180.v:7189$2509 + attribute \src "ls180.v:2564.138-2564.292" + cell $or $or$ls180.v:2564$260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:7189$2508_Y - connect \Y $and$ls180.v:7189$2509_Y + connect \A $not$ls180.v:2564$259_Y + connect \B \sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:2564$260_Y end - attribute \src "ls180.v:7189.184-7189.253" - cell $and $and$ls180.v:7189$2512 + attribute \src "ls180.v:2564.65-2564.446" + cell $or $or$ls180.v:2564$265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:7189$2511_Y - connect \Y $and$ls180.v:7189$2512_Y + connect \A $and$ls180.v:2564$261_Y + connect \B $and$ls180.v:2564$264_Y + connect \Y $or$ls180.v:2564$265_Y end - attribute \src "ls180.v:7189.259-7189.328" - cell $and $and$ls180.v:7189$2515 + attribute \src "ls180.v:2565.138-2565.292" + cell $or $or$ls180.v:2565$273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:7189$2514_Y - connect \Y $and$ls180.v:7189$2515_Y + connect \A $not$ls180.v:2565$272_Y + connect \B \sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:2565$273_Y end - attribute \src "ls180.v:7189.40-7189.331" - cell $and $and$ls180.v:7189$2518 + attribute \src "ls180.v:2565.65-2565.446" + cell $or $or$ls180.v:2565$278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7189$2507_Y - connect \B $not$ls180.v:7189$2517_Y - connect \Y $and$ls180.v:7189$2518_Y + connect \A $and$ls180.v:2565$274_Y + connect \B $and$ls180.v:2565$277_Y + connect \Y $or$ls180.v:2565$278_Y end - attribute \src "ls180.v:7189.39-7189.354" - cell $and $and$ls180.v:7189$2519 + attribute \src "ls180.v:2566.138-2566.292" + cell $or $or$ls180.v:2566$286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7189$2518_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7189$2519_Y + connect \A $not$ls180.v:2566$285_Y + connect \B \sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:2566$286_Y end - attribute \src "ls180.v:7394.39-7394.104" - cell $and $and$ls180.v:7394$2531 + attribute \src "ls180.v:2566.65-2566.446" + cell $or $or$ls180.v:2566$291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7394$2531_Y + connect \A $and$ls180.v:2566$287_Y + connect \B $and$ls180.v:2566$290_Y + connect \Y $or$ls180.v:2566$291_Y end - attribute \src "ls180.v:7394.38-7394.145" - cell $and $and$ls180.v:7394$2532 + attribute \src "ls180.v:2567.138-2567.292" + cell $or $or$ls180.v:2567$299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7394$2531_Y - connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7394$2532_Y + connect \A $not$ls180.v:2567$298_Y + connect \B \sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:2567$299_Y end - attribute \src "ls180.v:7397.39-7397.104" - cell $and $and$ls180.v:7397$2533 + attribute \src "ls180.v:2567.65-2567.446" + cell $or $or$ls180.v:2567$304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7397$2533_Y + connect \A $and$ls180.v:2567$300_Y + connect \B $and$ls180.v:2567$303_Y + connect \Y $or$ls180.v:2567$304_Y end - attribute \src "ls180.v:7397.38-7397.145" - cell $and $and$ls180.v:7397$2534 + attribute \src "ls180.v:2594.31-2594.89" + cell $or $or$ls180.v:2594$310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7397$2533_Y - connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7397$2534_Y + connect \A \sdram_choose_cmd_cmd_ready + connect \B $not$ls180.v:2594$309_Y + connect \Y $or$ls180.v:2594$310_Y end - attribute \src "ls180.v:7400.39-7400.82" - cell $and $and$ls180.v:7400$2535 + attribute \src "ls180.v:2597.138-2597.292" + cell $or $or$ls180.v:2597$318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7400$2535_Y + connect \A $not$ls180.v:2597$317_Y + connect \B \sdram_choose_req_want_activates + connect \Y $or$ls180.v:2597$318_Y end - attribute \src "ls180.v:7400.38-7400.112" - cell $and $and$ls180.v:7400$2536 + attribute \src "ls180.v:2597.65-2597.446" + cell $or $or$ls180.v:2597$323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7400$2535_Y - connect \B \main_sdram_cmd_payload_cas - connect \Y $and$ls180.v:7400$2536_Y + connect \A $and$ls180.v:2597$319_Y + connect \B $and$ls180.v:2597$322_Y + connect \Y $or$ls180.v:2597$323_Y end - attribute \src "ls180.v:7411.39-7411.104" - cell $and $and$ls180.v:7411$2538 + attribute \src "ls180.v:2598.138-2598.292" + cell $or $or$ls180.v:2598$331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7411$2538_Y + connect \A $not$ls180.v:2598$330_Y + connect \B \sdram_choose_req_want_activates + connect \Y $or$ls180.v:2598$331_Y end - attribute \src "ls180.v:7411.38-7411.145" - cell $and $and$ls180.v:7411$2539 + attribute \src "ls180.v:2598.65-2598.446" + cell $or $or$ls180.v:2598$336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7411$2538_Y - connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7411$2539_Y + connect \A $and$ls180.v:2598$332_Y + connect \B $and$ls180.v:2598$335_Y + connect \Y $or$ls180.v:2598$336_Y end - attribute \src "ls180.v:7414.39-7414.104" - cell $and $and$ls180.v:7414$2540 + attribute \src "ls180.v:2599.138-2599.292" + cell $or $or$ls180.v:2599$344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7414$2540_Y + connect \A $not$ls180.v:2599$343_Y + connect \B \sdram_choose_req_want_activates + connect \Y $or$ls180.v:2599$344_Y end - attribute \src "ls180.v:7414.38-7414.145" - cell $and $and$ls180.v:7414$2541 + attribute \src "ls180.v:2599.65-2599.446" + cell $or $or$ls180.v:2599$349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7414$2540_Y - connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7414$2541_Y + connect \A $and$ls180.v:2599$345_Y + connect \B $and$ls180.v:2599$348_Y + connect \Y $or$ls180.v:2599$349_Y end - attribute \src "ls180.v:7417.39-7417.82" - cell $and $and$ls180.v:7417$2542 + attribute \src "ls180.v:2600.138-2600.292" + cell $or $or$ls180.v:2600$357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7417$2542_Y + connect \A $not$ls180.v:2600$356_Y + connect \B \sdram_choose_req_want_activates + connect \Y $or$ls180.v:2600$357_Y end - attribute \src "ls180.v:7417.38-7417.112" - cell $and $and$ls180.v:7417$2543 + attribute \src "ls180.v:2600.65-2600.446" + cell $or $or$ls180.v:2600$362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7417$2542_Y - connect \B \main_sdram_cmd_payload_ras - connect \Y $and$ls180.v:7417$2543_Y + connect \A $and$ls180.v:2600$358_Y + connect \B $and$ls180.v:2600$361_Y + connect \Y $or$ls180.v:2600$362_Y end - attribute \src "ls180.v:7428.39-7428.104" - cell $and $and$ls180.v:7428$2545 + attribute \src "ls180.v:2663.31-2663.89" + cell $or $or$ls180.v:2663$396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7428$2545_Y + connect \A \sdram_choose_req_cmd_ready + connect \B $not$ls180.v:2663$395_Y + connect \Y $or$ls180.v:2663$396_Y end - attribute \src "ls180.v:7428.38-7428.144" - cell $and $and$ls180.v:7428$2546 + attribute \src "ls180.v:2684.57-2684.191" + cell $or $or$ls180.v:2684$403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7428$2545_Y - connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7428$2546_Y + connect \A $not$ls180.v:2684$402_Y + connect \B \sdram_ras_allowed + connect \Y $or$ls180.v:2684$403_Y end - attribute \src "ls180.v:7431.39-7431.104" - cell $and $and$ls180.v:7431$2547 + attribute \src "ls180.v:2692.10-2692.52" + cell $or $or$ls180.v:2692$406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7431$2547_Y + connect \A $not$ls180.v:2692$405_Y + connect \B \sdram_max_time1 + connect \Y $or$ls180.v:2692$406_Y end - attribute \src "ls180.v:7431.38-7431.144" - cell $and $and$ls180.v:7431$2548 + attribute \src "ls180.v:2722.57-2722.191" + cell $or $or$ls180.v:2722$412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7431$2547_Y - connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7431$2548_Y + connect \A $not$ls180.v:2722$411_Y + connect \B \sdram_ras_allowed + connect \Y $or$ls180.v:2722$412_Y end - attribute \src "ls180.v:7434.39-7434.82" - cell $and $and$ls180.v:7434$2549 + attribute \src "ls180.v:2730.10-2730.51" + cell $or $or$ls180.v:2730$415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7434$2549_Y + connect \A $not$ls180.v:2730$414_Y + connect \B \sdram_max_time0 + connect \Y $or$ls180.v:2730$415_Y end - attribute \src "ls180.v:7434.38-7434.111" - cell $and $and$ls180.v:7434$2550 + attribute \src "ls180.v:2740.91-2740.185" + cell $or $or$ls180.v:2740$419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7434$2549_Y - connect \B \main_sdram_cmd_payload_we - connect \Y $and$ls180.v:7434$2550_Y + connect \A \subfragments_locked0 + connect \B $and$ls180.v:2740$418_Y + connect \Y $or$ls180.v:2740$419_Y end - attribute \src "ls180.v:7445.39-7445.104" - cell $and $and$ls180.v:7445$2552 + attribute \src "ls180.v:2740.90-2740.260" + cell $or $or$ls180.v:2740$422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7445$2552_Y + connect \A $or$ls180.v:2740$419_Y + connect \B $and$ls180.v:2740$421_Y + connect \Y $or$ls180.v:2740$422_Y end - attribute \src "ls180.v:7445.38-7445.149" - cell $and $and$ls180.v:7445$2553 + attribute \src "ls180.v:2740.89-2740.335" + cell $or $or$ls180.v:2740$425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7445$2552_Y - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7445$2553_Y + connect \A $or$ls180.v:2740$422_Y + connect \B $and$ls180.v:2740$424_Y + connect \Y $or$ls180.v:2740$425_Y end - attribute \src "ls180.v:7448.39-7448.104" - cell $and $and$ls180.v:7448$2554 + attribute \src "ls180.v:2745.91-2745.185" + cell $or $or$ls180.v:2745$435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7448$2554_Y + connect \A \subfragments_locked1 + connect \B $and$ls180.v:2745$434_Y + connect \Y $or$ls180.v:2745$435_Y end - attribute \src "ls180.v:7448.38-7448.149" - cell $and $and$ls180.v:7448$2555 + attribute \src "ls180.v:2745.90-2745.260" + cell $or $or$ls180.v:2745$438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7448$2554_Y - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7448$2555_Y + connect \A $or$ls180.v:2745$435_Y + connect \B $and$ls180.v:2745$437_Y + connect \Y $or$ls180.v:2745$438_Y end - attribute \src "ls180.v:7451.39-7451.82" - cell $and $and$ls180.v:7451$2556 + attribute \src "ls180.v:2745.89-2745.335" + cell $or $or$ls180.v:2745$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7451$2556_Y + connect \A $or$ls180.v:2745$438_Y + connect \B $and$ls180.v:2745$440_Y + connect \Y $or$ls180.v:2745$441_Y end - attribute \src "ls180.v:7451.38-7451.116" - cell $and $and$ls180.v:7451$2557 + attribute \src "ls180.v:2750.91-2750.185" + cell $or $or$ls180.v:2750$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7451$2556_Y - connect \B \main_sdram_cmd_payload_is_read - connect \Y $and$ls180.v:7451$2557_Y + connect \A \subfragments_locked2 + connect \B $and$ls180.v:2750$450_Y + connect \Y $or$ls180.v:2750$451_Y end - attribute \src "ls180.v:7462.39-7462.104" - cell $and $and$ls180.v:7462$2559 + attribute \src "ls180.v:2750.90-2750.260" + cell $or $or$ls180.v:2750$454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7462$2559_Y + connect \A $or$ls180.v:2750$451_Y + connect \B $and$ls180.v:2750$453_Y + connect \Y $or$ls180.v:2750$454_Y end - attribute \src "ls180.v:7462.38-7462.150" - cell $and $and$ls180.v:7462$2560 + attribute \src "ls180.v:2750.89-2750.335" + cell $or $or$ls180.v:2750$457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7462$2559_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7462$2560_Y + connect \A $or$ls180.v:2750$454_Y + connect \B $and$ls180.v:2750$456_Y + connect \Y $or$ls180.v:2750$457_Y end - attribute \src "ls180.v:7465.39-7465.104" - cell $and $and$ls180.v:7465$2561 + attribute \src "ls180.v:2755.91-2755.185" + cell $or $or$ls180.v:2755$467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7465$2561_Y + connect \A \subfragments_locked3 + connect \B $and$ls180.v:2755$466_Y + connect \Y $or$ls180.v:2755$467_Y end - attribute \src "ls180.v:7465.38-7465.150" - cell $and $and$ls180.v:7465$2562 + attribute \src "ls180.v:2755.90-2755.260" + cell $or $or$ls180.v:2755$470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7465$2561_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7465$2562_Y + connect \A $or$ls180.v:2755$467_Y + connect \B $and$ls180.v:2755$469_Y + connect \Y $or$ls180.v:2755$470_Y end - attribute \src "ls180.v:7468.39-7468.82" - cell $and $and$ls180.v:7468$2563 + attribute \src "ls180.v:2755.89-2755.335" + cell $or $or$ls180.v:2755$473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7468$2563_Y + connect \A $or$ls180.v:2755$470_Y + connect \B $and$ls180.v:2755$472_Y + connect \Y $or$ls180.v:2755$473_Y end - attribute \src "ls180.v:7468.38-7468.117" - cell $and $and$ls180.v:7468$2564 + attribute \src "ls180.v:2760.127-2760.221" + cell $or $or$ls180.v:2760$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7468$2563_Y - connect \B \main_sdram_cmd_payload_is_write - connect \Y $and$ls180.v:7468$2564_Y + connect \A \subfragments_locked0 + connect \B $and$ls180.v:2760$483_Y + connect \Y $or$ls180.v:2760$484_Y end - attribute \src "ls180.v:7687.18-7687.68" - cell $and $and$ls180.v:7687$2571 + attribute \src "ls180.v:2760.126-2760.296" + cell $or $or$ls180.v:2760$487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_dfi_p0_wrdata_en - connect \B \main_dfi_p0_wrdata_mask [0] - connect \Y $and$ls180.v:7687$2571_Y + connect \A $or$ls180.v:2760$484_Y + connect \B $and$ls180.v:2760$486_Y + connect \Y $or$ls180.v:2760$487_Y end - attribute \src "ls180.v:7688.18-7688.68" - cell $and $and$ls180.v:7688$2572 + attribute \src "ls180.v:2760.125-2760.371" + cell $or $or$ls180.v:2760$490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_dfi_p0_wrdata_en - connect \B \main_dfi_p0_wrdata_mask [1] - connect \Y $and$ls180.v:7688$2572_Y + connect \A $or$ls180.v:2760$487_Y + connect \B $and$ls180.v:2760$489_Y + connect \Y $or$ls180.v:2760$490_Y end - attribute \src "ls180.v:7690.17-7690.67" - cell $and $and$ls180.v:7690$2574 + attribute \src "ls180.v:2760.29-2760.406" + cell $or $or$ls180.v:2760$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7690$2573_Y - connect \B \main_sdphy_sdpads_clk - connect \Y $and$ls180.v:7690$2574_Y + connect \A 1'0 + connect \B $and$ls180.v:2760$494_Y + connect \Y $or$ls180.v:2760$495_Y end - attribute \src "ls180.v:7769.8-7769.67" - cell $and $and$ls180.v:7769$2605 + attribute \src "ls180.v:2760.501-2760.595" + cell $or $or$ls180.v:2760$500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7769$2605_Y + connect \A \subfragments_locked1 + connect \B $and$ls180.v:2760$499_Y + connect \Y $or$ls180.v:2760$500_Y end - attribute \src "ls180.v:7769.7-7769.102" - cell $and $and$ls180.v:7769$2607 + attribute \src "ls180.v:2760.500-2760.670" + cell $or $or$ls180.v:2760$503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7769$2605_Y - connect \B $not$ls180.v:7769$2606_Y - connect \Y $and$ls180.v:7769$2607_Y + connect \A $or$ls180.v:2760$500_Y + connect \B $and$ls180.v:2760$502_Y + connect \Y $or$ls180.v:2760$503_Y end - attribute \src "ls180.v:7788.7-7788.75" - cell $and $and$ls180.v:7788$2611 + attribute \src "ls180.v:2760.499-2760.745" + cell $or $or$ls180.v:2760$506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7788$2610_Y - connect \B \main_libresocsim_zero_old_trigger - connect \Y $and$ls180.v:7788$2611_Y + connect \A $or$ls180.v:2760$503_Y + connect \B $and$ls180.v:2760$505_Y + connect \Y $or$ls180.v:2760$506_Y end - attribute \src "ls180.v:7792.8-7792.65" - cell $and $and$ls180.v:7792$2612 + attribute \src "ls180.v:2760.28-2760.780" + cell $or $or$ls180.v:2760$511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:7792$2612_Y + connect \A $or$ls180.v:2760$495_Y + connect \B $and$ls180.v:2760$510_Y + connect \Y $or$ls180.v:2760$511_Y end - attribute \src "ls180.v:7792.7-7792.99" - cell $and $and$ls180.v:7792$2614 + attribute \src "ls180.v:2760.875-2760.969" + cell $or $or$ls180.v:2760$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7792$2612_Y - connect \B $not$ls180.v:7792$2613_Y - connect \Y $and$ls180.v:7792$2614_Y + connect \A \subfragments_locked2 + connect \B $and$ls180.v:2760$515_Y + connect \Y $or$ls180.v:2760$516_Y end - attribute \src "ls180.v:7796.8-7796.65" - cell $and $and$ls180.v:7796$2615 + attribute \src "ls180.v:2760.874-2760.1044" + cell $or $or$ls180.v:2760$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:7796$2615_Y + connect \A $or$ls180.v:2760$516_Y + connect \B $and$ls180.v:2760$518_Y + connect \Y $or$ls180.v:2760$519_Y end - attribute \src "ls180.v:7796.7-7796.99" - cell $and $and$ls180.v:7796$2617 + attribute \src "ls180.v:2760.873-2760.1119" + cell $or $or$ls180.v:2760$522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7796$2615_Y - connect \B $not$ls180.v:7796$2616_Y - connect \Y $and$ls180.v:7796$2617_Y + connect \A $or$ls180.v:2760$519_Y + connect \B $and$ls180.v:2760$521_Y + connect \Y $or$ls180.v:2760$522_Y end - attribute \src "ls180.v:7800.8-7800.65" - cell $and $and$ls180.v:7800$2618 + attribute \src "ls180.v:2760.27-2760.1154" + cell $or $or$ls180.v:2760$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:7800$2618_Y + connect \A $or$ls180.v:2760$511_Y + connect \B $and$ls180.v:2760$526_Y + connect \Y $or$ls180.v:2760$527_Y end - attribute \src "ls180.v:7800.7-7800.99" - cell $and $and$ls180.v:7800$2620 + attribute \src "ls180.v:2760.1249-2760.1343" + cell $or $or$ls180.v:2760$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7800$2618_Y - connect \B $not$ls180.v:7800$2619_Y - connect \Y $and$ls180.v:7800$2620_Y + connect \A \subfragments_locked3 + connect \B $and$ls180.v:2760$531_Y + connect \Y $or$ls180.v:2760$532_Y end - attribute \src "ls180.v:7804.8-7804.65" - cell $and $and$ls180.v:7804$2621 + attribute \src "ls180.v:2760.1248-2760.1418" + cell $or $or$ls180.v:2760$535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:7804$2621_Y + connect \A $or$ls180.v:2760$532_Y + connect \B $and$ls180.v:2760$534_Y + connect \Y $or$ls180.v:2760$535_Y end - attribute \src "ls180.v:7804.7-7804.99" - cell $and $and$ls180.v:7804$2623 + attribute \src "ls180.v:2760.1247-2760.1493" + cell $or $or$ls180.v:2760$538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7804$2621_Y - connect \B $not$ls180.v:7804$2622_Y - connect \Y $and$ls180.v:7804$2623_Y + connect \A $or$ls180.v:2760$535_Y + connect \B $and$ls180.v:2760$537_Y + connect \Y $or$ls180.v:2760$538_Y end - attribute \src "ls180.v:7812.7-7812.56" - cell $and $and$ls180.v:7812$2625 + attribute \src "ls180.v:2760.26-2760.1528" + cell $or $or$ls180.v:2760$543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7812$2624_Y - connect \Y $and$ls180.v:7812$2625_Y + connect \A $or$ls180.v:2760$527_Y + connect \B $and$ls180.v:2760$542_Y + connect \Y $or$ls180.v:2760$543_Y end - attribute \src "ls180.v:7840.7-7840.75" - cell $and $and$ls180.v:7840$2632 + attribute \src "ls180.v:2823.10-2823.42" + cell $or $or$ls180.v:2823$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7840$2631_Y - connect \Y $and$ls180.v:7840$2632_Y + connect \A \litedram_wb_ack + connect \B \converter_skip + connect \Y $or$ls180.v:2823$552_Y end - attribute \src "ls180.v:7882.8-7882.131" - cell $and $and$ls180.v:7882$2638 + attribute \src "ls180.v:2850.30-2850.59" + cell $or $or$ls180.v:2850$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7882$2638_Y + connect \A \port_cmd_valid + connect \B \cmd_consumed + connect \Y $or$ls180.v:2850$562_Y end - attribute \src "ls180.v:7882.7-7882.190" - cell $and $and$ls180.v:7882$2640 + attribute \src "ls180.v:2851.29-2851.58" + cell $or $or$ls180.v:2851$566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7882$2638_Y - connect \B $not$ls180.v:7882$2639_Y - connect \Y $and$ls180.v:7882$2640_Y + connect \A \port_cmd_valid + connect \B \cmd_consumed + connect \Y $or$ls180.v:2851$566_Y end - attribute \src "ls180.v:7888.8-7888.131" - cell $and $and$ls180.v:7888$2643 + attribute \src "ls180.v:2852.38-2852.100" + cell $or $or$ls180.v:2852$572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7888$2643_Y + connect \A $and$ls180.v:2852$569_Y + connect \B $and$ls180.v:2852$571_Y + connect \Y $or$ls180.v:2852$572_Y end - attribute \src "ls180.v:7888.7-7888.190" - cell $and $and$ls180.v:7888$2645 + attribute \src "ls180.v:2853.19-2853.67" + cell $or $or$ls180.v:2853$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7888$2643_Y - connect \B $not$ls180.v:7888$2644_Y - connect \Y $and$ls180.v:7888$2645_Y + connect \A $and$ls180.v:2853$574_Y + connect \B \cmd_consumed + connect \Y $or$ls180.v:2853$575_Y end - attribute \src "ls180.v:7928.8-7928.131" - cell $and $and$ls180.v:7928$2654 + attribute \src "ls180.v:2854.21-2854.75" + cell $or $or$ls180.v:2854$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7928$2654_Y + connect \A $and$ls180.v:2854$576_Y + connect \B \wdata_consumed + connect \Y $or$ls180.v:2854$577_Y end - attribute \src "ls180.v:7928.7-7928.190" - cell $and $and$ls180.v:7928$2656 + attribute \src "ls180.v:2884.32-2884.59" + cell $or $or$ls180.v:2884$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7928$2654_Y - connect \B $not$ls180.v:7928$2655_Y - connect \Y $and$ls180.v:7928$2656_Y + connect \A \rx_clear + connect \B $and$ls180.v:2884$584_Y + connect \Y $or$ls180.v:2884$585_Y end - attribute \src "ls180.v:7934.8-7934.131" - cell $and $and$ls180.v:7934$2659 + attribute \src "ls180.v:2908.15-2908.124" + cell $or $or$ls180.v:2908$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7934$2659_Y + connect \A $and$ls180.v:2908$593_Y + connect \B $and$ls180.v:2908$594_Y + connect \Y $or$ls180.v:2908$595_Y end - attribute \src "ls180.v:7934.7-7934.190" - cell $and $and$ls180.v:7934$2661 + attribute \src "ls180.v:2923.60-2923.92" + cell $or $or$ls180.v:2923$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7934$2659_Y - connect \B $not$ls180.v:7934$2660_Y - connect \Y $and$ls180.v:7934$2661_Y + connect \A $not$ls180.v:2923$596_Y + connect \B \tx_fifo_re + connect \Y $or$ls180.v:2923$597_Y end - attribute \src "ls180.v:7974.8-7974.131" - cell $and $and$ls180.v:7974$2670 + attribute \src "ls180.v:2934.52-2934.95" + cell $or $or$ls180.v:2934$602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7974$2670_Y + connect \A \tx_fifo_syncfifo_writable + connect \B \tx_fifo_replace + connect \Y $or$ls180.v:2934$602_Y end - attribute \src "ls180.v:7974.7-7974.190" - cell $and $and$ls180.v:7974$2672 + attribute \src "ls180.v:2953.60-2953.92" + cell $or $or$ls180.v:2953$608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7974$2670_Y - connect \B $not$ls180.v:7974$2671_Y - connect \Y $and$ls180.v:7974$2672_Y + connect \A $not$ls180.v:2953$607_Y + connect \B \rx_fifo_re + connect \Y $or$ls180.v:2953$608_Y end - attribute \src "ls180.v:7980.8-7980.131" - cell $and $and$ls180.v:7980$2675 + attribute \src "ls180.v:2964.52-2964.95" + cell $or $or$ls180.v:2964$613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7980$2675_Y + connect \A \rx_fifo_syncfifo_writable + connect \B \rx_fifo_replace + connect \Y $or$ls180.v:2964$613_Y end - attribute \src "ls180.v:7980.7-7980.190" - cell $and $and$ls180.v:7980$2677 + attribute \src "ls180.v:3147.38-3147.83" + cell $or $or$ls180.v:3147$651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7980$2675_Y - connect \B $not$ls180.v:7980$2676_Y - connect \Y $and$ls180.v:7980$2677_Y + connect \A \libresocsim_ram_bus_err + connect \B \ram_bus_ram_bus_err + connect \Y $or$ls180.v:3147$651_Y end - attribute \src "ls180.v:8020.8-8020.131" - cell $and $and$ls180.v:8020$2686 + attribute \src "ls180.v:3147.37-3147.120" + cell $or $or$ls180.v:3147$652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:8020$2686_Y + connect \A $or$ls180.v:3147$651_Y + connect \B \libresocsim_libresoc_xics_icp_err + connect \Y $or$ls180.v:3147$652_Y end - attribute \src "ls180.v:8020.7-8020.190" - cell $and $and$ls180.v:8020$2688 + attribute \src "ls180.v:3147.36-3147.157" + cell $or $or$ls180.v:3147$653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8020$2686_Y - connect \B $not$ls180.v:8020$2687_Y - connect \Y $and$ls180.v:8020$2688_Y + connect \A $or$ls180.v:3147$652_Y + connect \B \libresocsim_libresoc_xics_ics_err + connect \Y $or$ls180.v:3147$653_Y end - attribute \src "ls180.v:8026.8-8026.131" - cell $and $and$ls180.v:8026$2691 + attribute \src "ls180.v:3147.35-3147.173" + cell $or $or$ls180.v:3147$654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:8026$2691_Y + connect \A $or$ls180.v:3147$653_Y + connect \B \wb_sdram_err + connect \Y $or$ls180.v:3147$654_Y end - attribute \src "ls180.v:8026.7-8026.190" - cell $and $and$ls180.v:8026$2693 + attribute \src "ls180.v:3147.34-3147.213" + cell $or $or$ls180.v:3147$655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8026$2691_Y - connect \B $not$ls180.v:8026$2692_Y - connect \Y $and$ls180.v:8026$2693_Y + connect \A $or$ls180.v:3147$654_Y + connect \B \libresocsim_libresocsim_wishbone_err + connect \Y $or$ls180.v:3147$655_Y end - attribute \src "ls180.v:8223.48-8223.124" - cell $and $and$ls180.v:8223$2718 + attribute \src "ls180.v:3153.33-3153.78" + cell $or $or$ls180.v:3153$660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2717_Y - connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:8223$2718_Y + connect \A \libresocsim_ram_bus_ack + connect \B \ram_bus_ram_bus_ack + connect \Y $or$ls180.v:3153$660_Y end - attribute \src "ls180.v:8223.130-8223.206" - cell $and $and$ls180.v:8223$2721 + attribute \src "ls180.v:3153.32-3153.115" + cell $or $or$ls180.v:3153$661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2720_Y - connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:8223$2721_Y + connect \A $or$ls180.v:3153$660_Y + connect \B \libresocsim_libresoc_xics_icp_ack + connect \Y $or$ls180.v:3153$661_Y end - attribute \src "ls180.v:8223.212-8223.288" - cell $and $and$ls180.v:8223$2724 + attribute \src "ls180.v:3153.31-3153.152" + cell $or $or$ls180.v:3153$662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2723_Y - connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:8223$2724_Y + connect \A $or$ls180.v:3153$661_Y + connect \B \libresocsim_libresoc_xics_ics_ack + connect \Y $or$ls180.v:3153$662_Y end - attribute \src "ls180.v:8223.294-8223.370" - cell $and $and$ls180.v:8223$2727 + attribute \src "ls180.v:3153.30-3153.168" + cell $or $or$ls180.v:3153$663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2726_Y - connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:8223$2727_Y + connect \A $or$ls180.v:3153$662_Y + connect \B \wb_sdram_ack + connect \Y $or$ls180.v:3153$663_Y end - attribute \src "ls180.v:8224.49-8224.125" - cell $and $and$ls180.v:8224$2730 + attribute \src "ls180.v:3153.29-3153.208" + cell $or $or$ls180.v:3153$664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2729_Y - connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:8224$2730_Y + connect \A $or$ls180.v:3153$663_Y + connect \B \libresocsim_libresocsim_wishbone_ack + connect \Y $or$ls180.v:3153$664_Y end - attribute \src "ls180.v:8224.131-8224.207" - cell $and $and$ls180.v:8224$2733 + attribute \src "ls180.v:3154.35-3154.158" + cell $or $or$ls180.v:3154$667 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2732_Y - connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:8224$2733_Y + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $and$ls180.v:3154$665_Y + connect \B $and$ls180.v:3154$666_Y + connect \Y $or$ls180.v:3154$667_Y end - attribute \src "ls180.v:8224.213-8224.289" - cell $and $and$ls180.v:8224$2736 + attribute \src "ls180.v:3154.34-3154.234" + cell $or $or$ls180.v:3154$669 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2735_Y - connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:8224$2736_Y + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:3154$667_Y + connect \B $and$ls180.v:3154$668_Y + connect \Y $or$ls180.v:3154$669_Y end - attribute \src "ls180.v:8224.295-8224.371" - cell $and $and$ls180.v:8224$2739 + attribute \src "ls180.v:3154.33-3154.310" + cell $or $or$ls180.v:3154$671 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2738_Y - connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:8224$2739_Y + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:3154$669_Y + connect \B $and$ls180.v:3154$670_Y + connect \Y $or$ls180.v:3154$671_Y end - attribute \src "ls180.v:8243.8-8243.49" - cell $and $and$ls180.v:8243$2742 + attribute \src "ls180.v:3154.32-3154.365" + cell $or $or$ls180.v:3154$673 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:8243$2742_Y + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:3154$671_Y + connect \B $and$ls180.v:3154$672_Y + connect \Y $or$ls180.v:3154$673_Y end - attribute \src "ls180.v:8246.8-8246.53" - cell $and $and$ls180.v:8246$2743 + attribute \src "ls180.v:3154.31-3154.444" + cell $or $or$ls180.v:3154$675 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_wdata_valid - connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:8246$2743_Y + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:3154$673_Y + connect \B $and$ls180.v:3154$674_Y + connect \Y $or$ls180.v:3154$675_Y end - attribute \src "ls180.v:8251.8-8251.59" - cell $and $and$ls180.v:8251$2745 + attribute \src "ls180.v:3434.52-3434.129" + cell $or $or$ls180.v:3434$1077 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_sink_valid - connect \B $not$ls180.v:8251$2744_Y - connect \Y $and$ls180.v:8251$2745_Y + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \libresocsim_interface0_bank_bus_dat_r + connect \B \libresocsim_interface1_bank_bus_dat_r + connect \Y $or$ls180.v:3434$1077_Y end - attribute \src "ls180.v:8251.7-8251.90" - cell $and $and$ls180.v:8251$2747 + attribute \src "ls180.v:3434.51-3434.170" + cell $or $or$ls180.v:3434$1078 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8251$2745_Y - connect \B $not$ls180.v:8251$2746_Y - connect \Y $and$ls180.v:8251$2747_Y + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:3434$1077_Y + connect \B \libresocsim_interface2_bank_bus_dat_r + connect \Y $or$ls180.v:3434$1078_Y end - attribute \src "ls180.v:8257.8-8257.59" - cell $and $and$ls180.v:8257$2748 + attribute \src "ls180.v:3434.50-3434.211" + cell $or $or$ls180.v:3434$1079 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_uart_clk_txen - connect \B \main_uart_phy_tx_busy - connect \Y $and$ls180.v:8257$2748_Y + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:3434$1078_Y + connect \B \libresocsim_interface3_bank_bus_dat_r + connect \Y $or$ls180.v:3434$1079_Y end - attribute \src "ls180.v:8281.8-8281.48" - cell $and $and$ls180.v:8281$2755 + attribute \src "ls180.v:3434.49-3434.252" + cell $or $or$ls180.v:3434$1080 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8281$2754_Y - connect \B \main_uart_phy_rx_r - connect \Y $and$ls180.v:8281$2755_Y + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:3434$1079_Y + connect \B \libresocsim_interface4_bank_bus_dat_r + connect \Y $or$ls180.v:3434$1080_Y end - attribute \src "ls180.v:8314.7-8314.57" - cell $and $and$ls180.v:8314$2761 + attribute \src "ls180.v:3434.48-3434.293" + cell $or $or$ls180.v:3434$1081 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8314$2760_Y - connect \B \main_uart_tx_old_trigger - connect \Y $and$ls180.v:8314$2761_Y + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:3434$1080_Y + connect \B \libresocsim_interface5_bank_bus_dat_r + connect \Y $or$ls180.v:3434$1081_Y end - attribute \src "ls180.v:8321.7-8321.57" - cell $and $and$ls180.v:8321$2763 + attribute \src "ls180.v:3434.47-3434.334" + cell $or $or$ls180.v:3434$1082 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8321$2762_Y - connect \B \main_uart_rx_old_trigger - connect \Y $and$ls180.v:8321$2763_Y + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:3434$1081_Y + connect \B \libresocsim_interface6_bank_bus_dat_r + connect \Y $or$ls180.v:3434$1082_Y end - attribute \src "ls180.v:8331.8-8331.75" - cell $and $and$ls180.v:8331$2764 + attribute \src "ls180.v:3434.46-3434.375" + cell $or $or$ls180.v:3434$1083 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8331$2764_Y + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:3434$1082_Y + connect \B \libresocsim_interface7_bank_bus_dat_r + connect \Y $or$ls180.v:3434$1083_Y end - attribute \src "ls180.v:8331.7-8331.107" - cell $and $and$ls180.v:8331$2766 + attribute \src "ls180.v:3761.72-3761.166" + cell $or $or$ls180.v:3761$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8331$2764_Y - connect \B $not$ls180.v:8331$2765_Y - connect \Y $and$ls180.v:8331$2766_Y + connect \A \subfragments_locked0 + connect \B $and$ls180.v:3761$1107_Y + connect \Y $or$ls180.v:3761$1108_Y end - attribute \src "ls180.v:8337.8-8337.75" - cell $and $and$ls180.v:8337$2769 + attribute \src "ls180.v:3761.71-3761.241" + cell $or $or$ls180.v:3761$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8337$2769_Y + connect \A $or$ls180.v:3761$1108_Y + connect \B $and$ls180.v:3761$1110_Y + connect \Y $or$ls180.v:3761$1111_Y end - attribute \src "ls180.v:8337.7-8337.107" - cell $and $and$ls180.v:8337$2771 + attribute \src "ls180.v:3761.70-3761.316" + cell $or $or$ls180.v:3761$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8337$2769_Y - connect \B $not$ls180.v:8337$2770_Y - connect \Y $and$ls180.v:8337$2771_Y + connect \A $or$ls180.v:3761$1111_Y + connect \B $and$ls180.v:3761$1113_Y + connect \Y $or$ls180.v:3761$1114_Y end - attribute \src "ls180.v:8353.8-8353.75" - cell $and $and$ls180.v:8353$2775 + attribute \src "ls180.v:3785.72-3785.166" + cell $or $or$ls180.v:3785$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8353$2775_Y + connect \A \subfragments_locked1 + connect \B $and$ls180.v:3785$1123_Y + connect \Y $or$ls180.v:3785$1124_Y end - attribute \src "ls180.v:8353.7-8353.107" - cell $and $and$ls180.v:8353$2777 + attribute \src "ls180.v:3785.71-3785.241" + cell $or $or$ls180.v:3785$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8353$2775_Y - connect \B $not$ls180.v:8353$2776_Y - connect \Y $and$ls180.v:8353$2777_Y + connect \A $or$ls180.v:3785$1124_Y + connect \B $and$ls180.v:3785$1126_Y + connect \Y $or$ls180.v:3785$1127_Y end - attribute \src "ls180.v:8359.8-8359.75" - cell $and $and$ls180.v:8359$2780 + attribute \src "ls180.v:3785.70-3785.316" + cell $or $or$ls180.v:3785$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8359$2780_Y + connect \A $or$ls180.v:3785$1127_Y + connect \B $and$ls180.v:3785$1129_Y + connect \Y $or$ls180.v:3785$1130_Y end - attribute \src "ls180.v:8359.7-8359.107" - cell $and $and$ls180.v:8359$2782 + attribute \src "ls180.v:3809.72-3809.166" + cell $or $or$ls180.v:3809$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8359$2780_Y - connect \B $not$ls180.v:8359$2781_Y - connect \Y $and$ls180.v:8359$2782_Y + connect \A \subfragments_locked2 + connect \B $and$ls180.v:3809$1139_Y + connect \Y $or$ls180.v:3809$1140_Y end - attribute \src "ls180.v:8507.7-8507.96" - cell $and $and$ls180.v:8507$2810 + attribute \src "ls180.v:3809.71-3809.241" + cell $or $or$ls180.v:3809$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_source_valid - connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:8507$2810_Y + connect \A $or$ls180.v:3809$1140_Y + connect \B $and$ls180.v:3809$1142_Y + connect \Y $or$ls180.v:3809$1143_Y end - attribute \src "ls180.v:8508.8-8508.93" - cell $and $and$ls180.v:8508$2811 + attribute \src "ls180.v:3809.70-3809.316" + cell $or $or$ls180.v:3809$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8508$2811_Y + connect \A $or$ls180.v:3809$1143_Y + connect \B $and$ls180.v:3809$1145_Y + connect \Y $or$ls180.v:3809$1146_Y end - attribute \src "ls180.v:8516.8-8516.93" - cell $and $and$ls180.v:8516$2812 + attribute \src "ls180.v:3833.72-3833.166" + cell $or $or$ls180.v:3833$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8516$2812_Y + connect \A \subfragments_locked3 + connect \B $and$ls180.v:3833$1155_Y + connect \Y $or$ls180.v:3833$1156_Y end - attribute \src "ls180.v:8588.7-8588.98" - cell $and $and$ls180.v:8588$2822 + attribute \src "ls180.v:3833.71-3833.241" + cell $or $or$ls180.v:3833$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_source_valid - connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:8588$2822_Y + connect \A $or$ls180.v:3833$1156_Y + connect \B $and$ls180.v:3833$1158_Y + connect \Y $or$ls180.v:3833$1159_Y end - attribute \src "ls180.v:8589.8-8589.95" - cell $and $and$ls180.v:8589$2823 + attribute \src "ls180.v:3833.70-3833.316" + cell $or $or$ls180.v:3833$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8589$2823_Y + connect \A $or$ls180.v:3833$1159_Y + connect \B $and$ls180.v:3833$1161_Y + connect \Y $or$ls180.v:3833$1162_Y end - attribute \src "ls180.v:8597.8-8597.95" - cell $and $and$ls180.v:8597$2824 + attribute \src "ls180.v:4286.15-4286.58" + cell $or $or$ls180.v:4286$1216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8597$2824_Y + connect \A \nc_1 [0] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4286$1216_Y end - attribute \src "ls180.v:8667.7-8667.100" - cell $and $and$ls180.v:8667$2834 + attribute \src "ls180.v:4287.15-4287.58" + cell $or $or$ls180.v:4287$1217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_source_valid - connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $and$ls180.v:8667$2834_Y + connect \A \nc_1 [1] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4287$1217_Y end - attribute \src "ls180.v:8668.8-8668.97" - cell $and $and$ls180.v:8668$2835 + attribute \src "ls180.v:4288.15-4288.58" + cell $or $or$ls180.v:4288$1218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8668$2835_Y + connect \A \nc_1 [2] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4288$1218_Y end - attribute \src "ls180.v:8676.8-8676.97" - cell $and $and$ls180.v:8676$2836 + attribute \src "ls180.v:4289.15-4289.58" + cell $or $or$ls180.v:4289$1219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8676$2836_Y + connect \A \nc_1 [3] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4289$1219_Y end - attribute \src "ls180.v:8767.7-8767.82" - cell $and $and$ls180.v:8767$2842 + attribute \src "ls180.v:4290.15-4290.58" + cell $or $or$ls180.v:4290$1220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8767$2842_Y + connect \A \nc_1 [4] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4290$1220_Y end - attribute \src "ls180.v:8770.7-8770.82" - cell $and $and$ls180.v:8770$2843 + attribute \src "ls180.v:4291.15-4291.58" + cell $or $or$ls180.v:4291$1221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8770$2843_Y + connect \A \nc_1 [5] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4291$1221_Y end - attribute \src "ls180.v:8773.7-8773.82" - cell $and $and$ls180.v:8773$2844 + attribute \src "ls180.v:4292.15-4292.58" + cell $or $or$ls180.v:4292$1222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8773$2844_Y + connect \A \nc_1 [6] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4292$1222_Y end - attribute \src "ls180.v:8776.7-8776.82" - cell $and $and$ls180.v:8776$2845 + attribute \src "ls180.v:4293.15-4293.58" + cell $or $or$ls180.v:4293$1223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8776$2845_Y + connect \A \nc_1 [7] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4293$1223_Y end - attribute \src "ls180.v:8779.7-8779.82" - cell $and $and$ls180.v:8779$2846 + attribute \src "ls180.v:4294.15-4294.58" + cell $or $or$ls180.v:4294$1224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8779$2846_Y + connect \A \nc_1 [8] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4294$1224_Y end - attribute \src "ls180.v:8784.7-8784.82" - cell $and $and$ls180.v:8784$2847 + attribute \src "ls180.v:4295.15-4295.58" + cell $or $or$ls180.v:4295$1225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8784$2847_Y + connect \A \nc_1 [9] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4295$1225_Y end - attribute \src "ls180.v:8789.7-8789.82" - cell $and $and$ls180.v:8789$2848 + attribute \src "ls180.v:4296.16-4296.60" + cell $or $or$ls180.v:4296$1226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8789$2848_Y + connect \A \nc_1 [10] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4296$1226_Y end - attribute \src "ls180.v:8794.7-8794.82" - cell $and $and$ls180.v:8794$2849 + attribute \src "ls180.v:4297.16-4297.60" + cell $or $or$ls180.v:4297$1227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8794$2849_Y + connect \A \nc_1 [11] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4297$1227_Y end - attribute \src "ls180.v:8799.7-8799.82" - cell $and $and$ls180.v:8799$2850 + attribute \src "ls180.v:4298.16-4298.60" + cell $or $or$ls180.v:4298$1228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8799$2850_Y + connect \A \nc_1 [12] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4298$1228_Y end - attribute \src "ls180.v:8864.8-8864.83" - cell $and $and$ls180.v:8864$2853 + attribute \src "ls180.v:4299.16-4299.60" + cell $or $or$ls180.v:4299$1229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8864$2853_Y + connect \A \nc_1 [13] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4299$1229_Y end - attribute \src "ls180.v:8864.7-8864.119" - cell $and $and$ls180.v:8864$2855 + attribute \src "ls180.v:4300.16-4300.60" + cell $or $or$ls180.v:4300$1230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8864$2853_Y - connect \B $not$ls180.v:8864$2854_Y - connect \Y $and$ls180.v:8864$2855_Y + connect \A \nc_1 [14] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4300$1230_Y end - attribute \src "ls180.v:8870.8-8870.83" - cell $and $and$ls180.v:8870$2858 + attribute \src "ls180.v:4301.16-4301.60" + cell $or $or$ls180.v:4301$1231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8870$2858_Y + connect \A \nc_1 [15] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4301$1231_Y end - attribute \src "ls180.v:8870.7-8870.119" - cell $and $and$ls180.v:8870$2860 + attribute \src "ls180.v:4302.16-4302.60" + cell $or $or$ls180.v:4302$1232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8870$2858_Y - connect \B $not$ls180.v:8870$2859_Y - connect \Y $and$ls180.v:8870$2860_Y + connect \A \nc_1 [16] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4302$1232_Y end - attribute \src "ls180.v:8890.7-8890.88" - cell $and $and$ls180.v:8890$2867 + attribute \src "ls180.v:4303.16-4303.60" + cell $or $or$ls180.v:4303$1233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_source_valid - connect \B \main_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8890$2867_Y + connect \A \nc_1 [17] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4303$1233_Y end - attribute \src "ls180.v:8891.8-8891.85" - cell $and $and$ls180.v:8891$2868 + attribute \src "ls180.v:4304.16-4304.60" + cell $or $or$ls180.v:4304$1234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8891$2868_Y + connect \A \nc_1 [18] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4304$1234_Y end - attribute \src "ls180.v:8899.8-8899.85" - cell $and $and$ls180.v:8899$2869 + attribute \src "ls180.v:4305.16-4305.60" + cell $or $or$ls180.v:4305$1235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8899$2869_Y + connect \A \nc_1 [19] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4305$1235_Y end - attribute \src "ls180.v:8955.7-8955.88" - cell $and $and$ls180.v:8955$2873 + attribute \src "ls180.v:4306.16-4306.60" + cell $or $or$ls180.v:4306$1236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_source_valid - connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8955$2873_Y + connect \A \nc_1 [20] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4306$1236_Y end - attribute \src "ls180.v:8962.8-8962.83" - cell $and $and$ls180.v:8962$2875 + attribute \src "ls180.v:4307.16-4307.60" + cell $or $or$ls180.v:4307$1237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8962$2875_Y + connect \A \nc_1 [21] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4307$1237_Y end - attribute \src "ls180.v:8962.7-8962.119" - cell $and $and$ls180.v:8962$2877 + attribute \src "ls180.v:4308.16-4308.60" + cell $or $or$ls180.v:4308$1238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8962$2875_Y - connect \B $not$ls180.v:8962$2876_Y - connect \Y $and$ls180.v:8962$2877_Y + connect \A \nc_1 [22] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4308$1238_Y end - attribute \src "ls180.v:8968.8-8968.83" - cell $and $and$ls180.v:8968$2880 + attribute \src "ls180.v:4309.16-4309.60" + cell $or $or$ls180.v:4309$1239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8968$2880_Y + connect \A \nc_1 [23] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4309$1239_Y end - attribute \src "ls180.v:8968.7-8968.119" - cell $and $and$ls180.v:8968$2882 + attribute \src "ls180.v:4310.16-4310.60" + cell $or $or$ls180.v:4310$1240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8968$2880_Y - connect \B $not$ls180.v:8968$2881_Y - connect \Y $and$ls180.v:8968$2882_Y + connect \A \nc_1 [24] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4310$1240_Y end - attribute \src "ls180.v:2930.30-2930.76" - cell $eq $eq$ls180.v:2930$54 + attribute \src "ls180.v:4311.16-4311.60" + cell $or $or$ls180.v:4311$1241 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_icp_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2930$54_Y + connect \A \nc_1 [25] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4311$1241_Y end - attribute \src "ls180.v:2937.11-2937.42" - cell $eq $eq$ls180.v:2937$59 + attribute \src "ls180.v:4312.16-4312.60" + cell $or $or$ls180.v:4312$1242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_converter0_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2937$59_Y + connect \A \nc_1 [26] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4312$1242_Y end - attribute \src "ls180.v:2990.30-2990.76" - cell $eq $eq$ls180.v:2990$65 + attribute \src "ls180.v:4313.16-4313.60" + cell $or $or$ls180.v:4313$1243 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_ics_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2990$65_Y + connect \A \nc_1 [27] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4313$1243_Y end - attribute \src "ls180.v:2997.11-2997.42" - cell $eq $eq$ls180.v:2997$70 + attribute \src "ls180.v:4314.16-4314.60" + cell $or $or$ls180.v:4314$1244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_converter1_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2997$70_Y + connect \A \nc_1 [28] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4314$1244_Y end - attribute \src "ls180.v:3050.33-3050.58" - cell $eq $eq$ls180.v:3050$76 + attribute \src "ls180.v:4315.16-4315.60" + cell $or $or$ls180.v:4315$1245 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_sel - connect \B 1'0 - connect \Y $eq$ls180.v:3050$76_Y + connect \A \nc_1 [29] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4315$1245_Y end - attribute \src "ls180.v:3057.11-3057.45" - cell $eq $eq$ls180.v:3057$81 + attribute \src "ls180.v:4316.16-4316.60" + cell $or $or$ls180.v:4316$1246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_socbushandler_counter - connect \B 1'1 - connect \Y $eq$ls180.v:3057$81_Y + connect \A \nc_1 [30] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4316$1246_Y end - attribute \src "ls180.v:3303.34-3303.65" - cell $eq $eq$ls180.v:3303$221 + attribute \src "ls180.v:4317.16-4317.60" + cell $or $or$ls180.v:4317$1247 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_count1 - connect \B 1'0 - connect \Y $eq$ls180.v:3303$221_Y + connect \A \nc_1 [31] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4317$1247_Y end - attribute \src "ls180.v:3307.68-3307.102" - cell $eq $eq$ls180.v:3307$224 + attribute \src "ls180.v:4318.16-4318.60" + cell $or $or$ls180.v:4318$1248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $eq$ls180.v:3307$224_Y - end - attribute \src "ls180.v:3351.43-3351.134" - cell $eq $eq$ls180.v:3351$229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_row - connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3351$229_Y + connect \A \nc_1 [32] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4318$1248_Y end - attribute \src "ls180.v:3368.47-3368.88" - cell $eq $eq$ls180.v:3368$242 + attribute \src "ls180.v:4319.16-4319.60" + cell $or $or$ls180.v:4319$1249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3368$242_Y - end - attribute \src "ls180.v:3508.43-3508.134" - cell $eq $eq$ls180.v:3508$259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_row - connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3508$259_Y + connect \A \nc_1 [33] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4319$1249_Y end - attribute \src "ls180.v:3525.47-3525.88" - cell $eq $eq$ls180.v:3525$272 + attribute \src "ls180.v:4320.16-4320.60" + cell $or $or$ls180.v:4320$1250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3525$272_Y - end - attribute \src "ls180.v:3665.43-3665.134" - cell $eq $eq$ls180.v:3665$289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_row - connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3665$289_Y + connect \A \nc_1 [34] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4320$1250_Y end - attribute \src "ls180.v:3682.47-3682.88" - cell $eq $eq$ls180.v:3682$302 + attribute \src "ls180.v:4321.16-4321.60" + cell $or $or$ls180.v:4321$1251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3682$302_Y - end - attribute \src "ls180.v:3822.43-3822.134" - cell $eq $eq$ls180.v:3822$319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_row - connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3822$319_Y + connect \A \nc_1 [35] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4321$1251_Y end - attribute \src "ls180.v:3839.47-3839.88" - cell $eq $eq$ls180.v:3839$332 + attribute \src "ls180.v:4322.7-4322.83" + cell $or $or$ls180.v:4322$1252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3839$332_Y + connect \A \libresocsim_interface0_converted_interface_ack + connect \B \libresocsim_converter0_skip + connect \Y $or$ls180.v:4322$1252_Y end - attribute \src "ls180.v:3976.32-3976.56" - cell $eq $eq$ls180.v:3976$379 + attribute \src "ls180.v:4333.7-4333.83" + cell $or $or$ls180.v:4333$1253 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_time0 - connect \B 1'0 - connect \Y $eq$ls180.v:3976$379_Y + connect \A \libresocsim_interface1_converted_interface_ack + connect \B \libresocsim_converter1_skip + connect \Y $or$ls180.v:4333$1253_Y end - attribute \src "ls180.v:3977.32-3977.56" - cell $eq $eq$ls180.v:3977$380 + attribute \src "ls180.v:4344.7-4344.83" + cell $or $or$ls180.v:4344$1254 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_time1 - connect \B 1'0 - connect \Y $eq$ls180.v:3977$380_Y + connect \A \libresocsim_interface2_converted_interface_ack + connect \B \libresocsim_converter2_skip + connect \Y $or$ls180.v:4344$1254_Y end - attribute \src "ls180.v:3988.339-3988.418" - cell $eq $eq$ls180.v:3988$394 + attribute \src "ls180.v:4477.7-4477.97" + cell $or $or$ls180.v:4477$1293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3988$394_Y + connect \A $not$ls180.v:4477$1292_Y + connect \B \sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:4477$1293_Y end - attribute \src "ls180.v:3988.423-3988.504" - cell $eq $eq$ls180.v:3988$395 + attribute \src "ls180.v:4523.7-4523.97" + cell $or $or$ls180.v:4523$1309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3988$395_Y + connect \A $not$ls180.v:4523$1308_Y + connect \B \sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:4523$1309_Y end - attribute \src "ls180.v:3989.339-3989.418" - cell $eq $eq$ls180.v:3989$407 + attribute \src "ls180.v:4569.7-4569.97" + cell $or $or$ls180.v:4569$1325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3989$407_Y + connect \A $not$ls180.v:4569$1324_Y + connect \B \sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:4569$1325_Y end - attribute \src "ls180.v:3989.423-3989.504" - cell $eq $eq$ls180.v:3989$408 + attribute \src "ls180.v:4615.7-4615.97" + cell $or $or$ls180.v:4615$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3989$408_Y + connect \A $not$ls180.v:4615$1340_Y + connect \B \sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:4615$1341_Y end - attribute \src "ls180.v:3990.339-3990.418" - cell $eq $eq$ls180.v:3990$420 + attribute \src "ls180.v:4803.45-4803.130" + cell $or $or$ls180.v:4803$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3990$420_Y + connect \A 1'0 + connect \B $and$ls180.v:4803$1361_Y + connect \Y $or$ls180.v:4803$1362_Y end - attribute \src "ls180.v:3990.423-3990.504" - cell $eq $eq$ls180.v:3990$421 + attribute \src "ls180.v:4803.44-4803.212" + cell $or $or$ls180.v:4803$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3990$421_Y + connect \A $or$ls180.v:4803$1362_Y + connect \B $and$ls180.v:4803$1364_Y + connect \Y $or$ls180.v:4803$1365_Y end - attribute \src "ls180.v:3991.339-3991.418" - cell $eq $eq$ls180.v:3991$433 + attribute \src "ls180.v:4803.43-4803.294" + cell $or $or$ls180.v:4803$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3991$433_Y + connect \A $or$ls180.v:4803$1365_Y + connect \B $and$ls180.v:4803$1367_Y + connect \Y $or$ls180.v:4803$1368_Y end - attribute \src "ls180.v:3991.423-3991.504" - cell $eq $eq$ls180.v:3991$434 + attribute \src "ls180.v:4803.42-4803.376" + cell $or $or$ls180.v:4803$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3991$434_Y + connect \A $or$ls180.v:4803$1368_Y + connect \B $and$ls180.v:4803$1370_Y + connect \Y $or$ls180.v:4803$1371_Y end - attribute \src "ls180.v:4021.339-4021.418" - cell $eq $eq$ls180.v:4021$452 + attribute \src "ls180.v:4804.46-4804.131" + cell $or $or$ls180.v:4804$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4021$452_Y + connect \A 1'0 + connect \B $and$ls180.v:4804$1373_Y + connect \Y $or$ls180.v:4804$1374_Y end - attribute \src "ls180.v:4021.423-4021.504" - cell $eq $eq$ls180.v:4021$453 + attribute \src "ls180.v:4804.45-4804.213" + cell $or $or$ls180.v:4804$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4021$453_Y + connect \A $or$ls180.v:4804$1374_Y + connect \B $and$ls180.v:4804$1376_Y + connect \Y $or$ls180.v:4804$1377_Y end - attribute \src "ls180.v:4022.339-4022.418" - cell $eq $eq$ls180.v:4022$465 + attribute \src "ls180.v:4804.44-4804.295" + cell $or $or$ls180.v:4804$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4022$465_Y + connect \A $or$ls180.v:4804$1377_Y + connect \B $and$ls180.v:4804$1379_Y + connect \Y $or$ls180.v:4804$1380_Y end - attribute \src "ls180.v:4022.423-4022.504" - cell $eq $eq$ls180.v:4022$466 + attribute \src "ls180.v:4804.43-4804.377" + cell $or $or$ls180.v:4804$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4022$466_Y + connect \A $or$ls180.v:4804$1380_Y + connect \B $and$ls180.v:4804$1382_Y + connect \Y $or$ls180.v:4804$1383_Y end - attribute \src "ls180.v:4023.339-4023.418" - cell $eq $eq$ls180.v:4023$478 + attribute \src "ls180.v:4808.7-4808.39" + cell $or $or$ls180.v:4808$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4023$478_Y + connect \A \litedram_wb_ack + connect \B \converter_skip + connect \Y $or$ls180.v:4808$1384_Y end - attribute \src "ls180.v:4023.423-4023.504" - cell $eq $eq$ls180.v:4023$479 + attribute \src "ls180.v:5717.8-5717.46" + cell $or $or$ls180.v:5717$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4023$479_Y + connect \A \sys_rst_1 + connect \B \libresocsim_libresoc_reset + connect \Y $or$ls180.v:5717$1546_Y end - attribute \src "ls180.v:4024.339-4024.418" - cell $eq $eq$ls180.v:4024$491 + attribute \src "ls180.v:1934.41-1934.84" + cell $sshl $sshl$ls180.v:1934$99 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4024$491_Y + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \sdram_bankmachine0_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:1934$99_Y end - attribute \src "ls180.v:4024.423-4024.504" - cell $eq $eq$ls180.v:4024$492 + attribute \src "ls180.v:2091.41-2091.84" + cell $sshl $sshl$ls180.v:2091$129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4024$492_Y + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \sdram_bankmachine1_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:2091$129_Y end - attribute \src "ls180.v:4053.78-4053.113" - cell $eq $eq$ls180.v:4053$501 + attribute \src "ls180.v:2248.41-2248.84" + cell $sshl $sshl$ls180.v:2248$159 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$501_Y + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \sdram_bankmachine2_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:2248$159_Y end - attribute \src "ls180.v:4056.78-4056.113" - cell $eq $eq$ls180.v:4056$504 + attribute \src "ls180.v:2405.41-2405.84" + cell $sshl $sshl$ls180.v:2405$189 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4056$504_Y + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \sdram_bankmachine3_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:2405$189_Y end - attribute \src "ls180.v:4062.78-4062.113" - cell $eq $eq$ls180.v:4062$508 + attribute \src "ls180.v:1965.58-1965.112" + cell $sub $sub$ls180.v:1965$112 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $eq$ls180.v:4062$508_Y + connect \Y $sub$ls180.v:1965$112_Y end - attribute \src "ls180.v:4065.78-4065.113" - cell $eq $eq$ls180.v:4065$511 + attribute \src "ls180.v:2122.58-2122.112" + cell $sub $sub$ls180.v:2122$142 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $eq$ls180.v:4065$511_Y - end - attribute \src "ls180.v:4071.78-4071.113" - cell $eq $eq$ls180.v:4071$515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 2'10 - connect \Y $eq$ls180.v:4071$515_Y - end - attribute \src "ls180.v:4074.78-4074.113" - cell $eq $eq$ls180.v:4074$518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 2'10 - connect \Y $eq$ls180.v:4074$518_Y - end - attribute \src "ls180.v:4080.78-4080.113" - cell $eq $eq$ls180.v:4080$522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 2'11 - connect \Y $eq$ls180.v:4080$522_Y - end - attribute \src "ls180.v:4083.78-4083.113" - cell $eq $eq$ls180.v:4083$525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 2'11 - connect \Y $eq$ls180.v:4083$525_Y + connect \Y $sub$ls180.v:2122$142_Y end - attribute \src "ls180.v:4164.42-4164.82" - cell $eq $eq$ls180.v:4164$548 + attribute \src "ls180.v:2279.58-2279.112" + cell $sub $sub$ls180.v:2279$172 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:4164$548_Y + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:2279$172_Y end - attribute \src "ls180.v:4164.145-4164.178" - cell $eq $eq$ls180.v:4164$549 + attribute \src "ls180.v:2436.58-2436.112" + cell $sub $sub$ls180.v:2436$202 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4164$549_Y + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:2436$202_Y end - attribute \src "ls180.v:4164.220-4164.253" - cell $eq $eq$ls180.v:4164$552 + attribute \src "ls180.v:2842.33-2842.65" + cell $sub $sub$ls180.v:2842$556 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 30 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4164$552_Y + parameter \B_WIDTH 31 + parameter \Y_WIDTH 31 + connect \A \litedram_wb_adr + connect \B 31'1001000000000000000000000000000 + connect \Y $sub$ls180.v:2842$556_Y end - attribute \src "ls180.v:4164.295-4164.328" - cell $eq $eq$ls180.v:4164$555 + attribute \src "ls180.v:2928.26-2928.48" + cell $sub $sub$ls180.v:2928$601 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4164$555_Y + parameter \Y_WIDTH 4 + connect \A \tx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:2928$601_Y end - attribute \src "ls180.v:4169.42-4169.82" - cell $eq $eq$ls180.v:4169$564 + attribute \src "ls180.v:2958.26-2958.48" + cell $sub $sub$ls180.v:2958$612 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] + parameter \Y_WIDTH 4 + connect \A \rx_fifo_produce connect \B 1'1 - connect \Y $eq$ls180.v:4169$564_Y + connect \Y $sub$ls180.v:2958$612_Y end - attribute \src "ls180.v:4169.145-4169.178" - cell $eq $eq$ls180.v:4169$565 + attribute \src "ls180.v:4368.26-4368.50" + cell $sub $sub$ls180.v:4368$1261 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4169$565_Y + parameter \Y_WIDTH 32 + connect \A \libresocsim_value + connect \B 1'1 + connect \Y $sub$ls180.v:4368$1261_Y end - attribute \src "ls180.v:4169.220-4169.253" - cell $eq $eq$ls180.v:4169$568 + attribute \src "ls180.v:4393.26-4393.51" + cell $sub $sub$ls180.v:4393$1269 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4169$568_Y + parameter \Y_WIDTH 10 + connect \A \sdram_timer_count1 + connect \B 1'1 + connect \Y $sub$ls180.v:4393$1269_Y end - attribute \src "ls180.v:4169.295-4169.328" - cell $eq $eq$ls180.v:4169$571 + attribute \src "ls180.v:4399.29-4399.57" + cell $sub $sub$ls180.v:4399$1270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4169$571_Y - end - attribute \src "ls180.v:4174.42-4174.82" - cell $eq $eq$ls180.v:4174$580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:4174$580_Y + connect \A \sdram_postponer_count + connect \B 1'1 + connect \Y $sub$ls180.v:4399$1270_Y end - attribute \src "ls180.v:4174.145-4174.178" - cell $eq $eq$ls180.v:4174$581 + attribute \src "ls180.v:4410.31-4410.59" + cell $sub $sub$ls180.v:4410$1273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4174$581_Y + connect \A \sdram_sequencer_count + connect \B 1'1 + connect \Y $sub$ls180.v:4410$1273_Y end - attribute \src "ls180.v:4174.220-4174.253" - cell $eq $eq$ls180.v:4174$584 + attribute \src "ls180.v:4474.54-4474.106" + cell $sub $sub$ls180.v:4474$1291 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4174$584_Y + parameter \Y_WIDTH 4 + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:4474$1291_Y end - attribute \src "ls180.v:4174.295-4174.328" - cell $eq $eq$ls180.v:4174$587 + attribute \src "ls180.v:4493.41-4493.80" + cell $sub $sub$ls180.v:4493$1295 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4174$587_Y - end - attribute \src "ls180.v:4179.42-4179.82" - cell $eq $eq$ls180.v:4179$596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:4179$596_Y + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:4493$1295_Y end - attribute \src "ls180.v:4179.145-4179.178" - cell $eq $eq$ls180.v:4179$597 + attribute \src "ls180.v:4520.54-4520.106" + cell $sub $sub$ls180.v:4520$1307 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4179$597_Y + parameter \Y_WIDTH 4 + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:4520$1307_Y end - attribute \src "ls180.v:4179.220-4179.253" - cell $eq $eq$ls180.v:4179$600 + attribute \src "ls180.v:4539.41-4539.80" + cell $sub $sub$ls180.v:4539$1311 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4179$600_Y + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:4539$1311_Y end - attribute \src "ls180.v:4179.295-4179.328" - cell $eq $eq$ls180.v:4179$603 + attribute \src "ls180.v:4566.54-4566.106" + cell $sub $sub$ls180.v:4566$1323 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4179$603_Y + parameter \Y_WIDTH 4 + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:4566$1323_Y end - attribute \src "ls180.v:4184.44-4184.77" - cell $eq $eq$ls180.v:4184$612 + attribute \src "ls180.v:4585.41-4585.80" + cell $sub $sub$ls180.v:4585$1327 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$612_Y + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:4585$1327_Y end - attribute \src "ls180.v:4184.83-4184.123" - cell $eq $eq$ls180.v:4184$613 + attribute \src "ls180.v:4612.54-4612.106" + cell $sub $sub$ls180.v:4612$1339 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:4184$613_Y + parameter \Y_WIDTH 4 + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:4612$1339_Y end - attribute \src "ls180.v:4184.186-4184.219" - cell $eq $eq$ls180.v:4184$614 + attribute \src "ls180.v:4631.41-4631.80" + cell $sub $sub$ls180.v:4631$1343 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$614_Y + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:4631$1343_Y end - attribute \src "ls180.v:4184.261-4184.294" - cell $eq $eq$ls180.v:4184$617 + attribute \src "ls180.v:4642.20-4642.38" + cell $sub $sub$ls180.v:4642$1347 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$617_Y + parameter \Y_WIDTH 5 + connect \A \sdram_time0 + connect \B 1'1 + connect \Y $sub$ls180.v:4642$1347_Y end - attribute \src "ls180.v:4184.336-4184.369" - cell $eq $eq$ls180.v:4184$620 + attribute \src "ls180.v:4649.20-4649.38" + cell $sub $sub$ls180.v:4649$1350 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$620_Y + parameter \Y_WIDTH 4 + connect \A \sdram_time1 + connect \B 1'1 + connect \Y $sub$ls180.v:4649$1350_Y end - attribute \src "ls180.v:4184.418-4184.451" - cell $eq $eq$ls180.v:4184$628 + attribute \src "ls180.v:4781.28-4781.54" + cell $sub $sub$ls180.v:4781$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$628_Y + connect \A \sdram_tccdcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:4781$1355_Y end - attribute \src "ls180.v:4184.457-4184.497" - cell $eq $eq$ls180.v:4184$629 + attribute \src "ls180.v:4796.28-4796.54" + cell $sub $sub$ls180.v:4796$1358 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] + parameter \Y_WIDTH 3 + connect \A \sdram_twtrcon_count connect \B 1'1 - connect \Y $eq$ls180.v:4184$629_Y + connect \Y $sub$ls180.v:4796$1358_Y end - attribute \src "ls180.v:4184.560-4184.593" - cell $eq $eq$ls180.v:4184$630 + attribute \src "ls180.v:4923.23-4923.44" + cell $sub $sub$ls180.v:4923$1417 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$630_Y + parameter \Y_WIDTH 5 + connect \A \tx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:4923$1417_Y end - attribute \src "ls180.v:4184.635-4184.668" - cell $eq $eq$ls180.v:4184$633 + attribute \src "ls180.v:4945.23-4945.44" + cell $sub $sub$ls180.v:4945$1428 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$633_Y + parameter \Y_WIDTH 5 + connect \A \rx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:4945$1428_Y end - attribute \src "ls180.v:4184.710-4184.743" - cell $eq $eq$ls180.v:4184$636 + attribute \src "ls180.v:5010.26-5010.50" + cell $sub $sub$ls180.v:5010$1433 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 20 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$636_Y + parameter \Y_WIDTH 20 + connect \A \libresocsim_count + connect \B 1'1 + connect \Y $sub$ls180.v:5010$1433_Y end - attribute \src "ls180.v:4184.792-4184.825" - cell $eq $eq$ls180.v:4184$644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$644_Y + attribute \module_not_derived 1 + attribute \src "ls180.v:5623.13-5949.2" + cell \test_issuer \test_issuer + connect \TAP_bus__tck \libresocsim_libresoc_jtag_tck + connect \TAP_bus__tdi \libresocsim_libresoc_jtag_tdi + connect \TAP_bus__tdo \libresocsim_libresoc_jtag_tdo + connect \TAP_bus__tms \libresocsim_libresoc_jtag_tms + connect \busy_o \libresocsim_libresoc0 + connect \clk \sys_clk_1 + connect \clk_sel_i \libresocsim_libresoc_clk_sel + connect \core_bigendian_i 1'0 + connect \dbus__ack \libresocsim_libresoc_dbus_ack + connect \dbus__adr \libresocsim_libresoc_dbus_adr + connect \dbus__bte 1'0 + connect \dbus__cti 1'0 + connect \dbus__cyc \libresocsim_libresoc_dbus_cyc + connect \dbus__dat_r \libresocsim_libresoc_dbus_dat_r + connect \dbus__dat_w \libresocsim_libresoc_dbus_dat_w + connect \dbus__err \libresocsim_libresoc_dbus_err + connect \dbus__sel \libresocsim_libresoc_dbus_sel + connect \dbus__stb \libresocsim_libresoc_dbus_stb + connect \dbus__we \libresocsim_libresoc_dbus_we + connect \eint_0__core__i \libresocsim_libresoc_constraintmanager_eint_0 + connect \eint_0__pad__i \eint_0 + connect \eint_1__core__i \libresocsim_libresoc_constraintmanager_eint_1 + connect \eint_1__pad__i \eint_1 + connect \eint_2__core__i \libresocsim_libresoc_constraintmanager_eint_2 + connect \eint_2__pad__i \eint_2 + connect \gpio_e10__core__i \libresocsim_libresoc_constraintmanager_gpio_i [10] + connect \gpio_e10__core__o \libresocsim_libresoc_constraintmanager_gpio_o [10] + connect \gpio_e10__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [10] + connect \gpio_e10__pad__i \gpio_i [10] + connect \gpio_e10__pad__o \gpio_o [10] + connect \gpio_e10__pad__oe \gpio_oe [10] + connect \gpio_e11__core__i \libresocsim_libresoc_constraintmanager_gpio_i [11] + connect \gpio_e11__core__o \libresocsim_libresoc_constraintmanager_gpio_o [11] + connect \gpio_e11__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [11] + connect \gpio_e11__pad__i \gpio_i [11] + connect \gpio_e11__pad__o \gpio_o [11] + connect \gpio_e11__pad__oe \gpio_oe [11] + connect \gpio_e12__core__i \libresocsim_libresoc_constraintmanager_gpio_i [12] + connect \gpio_e12__core__o \libresocsim_libresoc_constraintmanager_gpio_o [12] + connect \gpio_e12__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [12] + connect \gpio_e12__pad__i \gpio_i [12] + connect \gpio_e12__pad__o \gpio_o [12] + connect \gpio_e12__pad__oe \gpio_oe [12] + connect \gpio_e13__core__i \libresocsim_libresoc_constraintmanager_gpio_i [13] + connect \gpio_e13__core__o \libresocsim_libresoc_constraintmanager_gpio_o [13] + connect \gpio_e13__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [13] + connect \gpio_e13__pad__i \gpio_i [13] + connect \gpio_e13__pad__o \gpio_o [13] + connect \gpio_e13__pad__oe \gpio_oe [13] + connect \gpio_e14__core__i \libresocsim_libresoc_constraintmanager_gpio_i [14] + connect \gpio_e14__core__o \libresocsim_libresoc_constraintmanager_gpio_o [14] + connect \gpio_e14__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [14] + connect \gpio_e14__pad__i \gpio_i [14] + connect \gpio_e14__pad__o \gpio_o [14] + connect \gpio_e14__pad__oe \gpio_oe [14] + connect \gpio_e15__core__i \libresocsim_libresoc_constraintmanager_gpio_i [15] + connect \gpio_e15__core__o \libresocsim_libresoc_constraintmanager_gpio_o [15] + connect \gpio_e15__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [15] + connect \gpio_e15__pad__i \gpio_i [15] + connect \gpio_e15__pad__o \gpio_o [15] + connect \gpio_e15__pad__oe \gpio_oe [15] + connect \gpio_e8__core__i \libresocsim_libresoc_constraintmanager_gpio_i [8] + connect \gpio_e8__core__o \libresocsim_libresoc_constraintmanager_gpio_o [8] + connect \gpio_e8__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [8] + connect \gpio_e8__pad__i \gpio_i [8] + connect \gpio_e8__pad__o \gpio_o [8] + connect \gpio_e8__pad__oe \gpio_oe [8] + connect \gpio_e9__core__i \libresocsim_libresoc_constraintmanager_gpio_i [9] + connect \gpio_e9__core__o \libresocsim_libresoc_constraintmanager_gpio_o [9] + connect \gpio_e9__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [9] + connect \gpio_e9__pad__i \gpio_i [9] + connect \gpio_e9__pad__o \gpio_o [9] + connect \gpio_e9__pad__oe \gpio_oe [9] + connect \gpio_s0__core__i \libresocsim_libresoc_constraintmanager_gpio_i [0] + connect \gpio_s0__core__o \libresocsim_libresoc_constraintmanager_gpio_o [0] + connect \gpio_s0__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [0] + connect \gpio_s0__pad__i \gpio_i [0] + connect \gpio_s0__pad__o \gpio_o [0] + connect \gpio_s0__pad__oe \gpio_oe [0] + connect \gpio_s1__core__i \libresocsim_libresoc_constraintmanager_gpio_i [1] + connect \gpio_s1__core__o \libresocsim_libresoc_constraintmanager_gpio_o [1] + connect \gpio_s1__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [1] + connect \gpio_s1__pad__i \gpio_i [1] + connect \gpio_s1__pad__o \gpio_o [1] + connect \gpio_s1__pad__oe \gpio_oe [1] + connect \gpio_s2__core__i \libresocsim_libresoc_constraintmanager_gpio_i [2] + connect \gpio_s2__core__o \libresocsim_libresoc_constraintmanager_gpio_o [2] + connect \gpio_s2__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [2] + connect \gpio_s2__pad__i \gpio_i [2] + connect \gpio_s2__pad__o \gpio_o [2] + connect \gpio_s2__pad__oe \gpio_oe [2] + connect \gpio_s3__core__i \libresocsim_libresoc_constraintmanager_gpio_i [3] + connect \gpio_s3__core__o \libresocsim_libresoc_constraintmanager_gpio_o [3] + connect \gpio_s3__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [3] + connect \gpio_s3__pad__i \gpio_i [3] + connect \gpio_s3__pad__o \gpio_o [3] + connect \gpio_s3__pad__oe \gpio_oe [3] + connect \gpio_s4__core__i \libresocsim_libresoc_constraintmanager_gpio_i [4] + connect \gpio_s4__core__o \libresocsim_libresoc_constraintmanager_gpio_o [4] + connect \gpio_s4__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [4] + connect \gpio_s4__pad__i \gpio_i [4] + connect \gpio_s4__pad__o \gpio_o [4] + connect \gpio_s4__pad__oe \gpio_oe [4] + connect \gpio_s5__core__i \libresocsim_libresoc_constraintmanager_gpio_i [5] + connect \gpio_s5__core__o \libresocsim_libresoc_constraintmanager_gpio_o [5] + connect \gpio_s5__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [5] + connect \gpio_s5__pad__i \gpio_i [5] + connect \gpio_s5__pad__o \gpio_o [5] + connect \gpio_s5__pad__oe \gpio_oe [5] + connect \gpio_s6__core__i \libresocsim_libresoc_constraintmanager_gpio_i [6] + connect \gpio_s6__core__o \libresocsim_libresoc_constraintmanager_gpio_o [6] + connect \gpio_s6__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [6] + connect \gpio_s6__pad__i \gpio_i [6] + connect \gpio_s6__pad__o \gpio_o [6] + connect \gpio_s6__pad__oe \gpio_oe [6] + connect \gpio_s7__core__i \libresocsim_libresoc_constraintmanager_gpio_i [7] + connect \gpio_s7__core__o \libresocsim_libresoc_constraintmanager_gpio_o [7] + connect \gpio_s7__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [7] + connect \gpio_s7__pad__i \gpio_i [7] + connect \gpio_s7__pad__o \gpio_o [7] + connect \gpio_s7__pad__oe \gpio_oe [7] + connect \ibus__ack \libresocsim_libresoc_ibus_ack + connect \ibus__adr \libresocsim_libresoc_ibus_adr + connect \ibus__bte 1'0 + connect \ibus__cti 1'0 + connect \ibus__cyc \libresocsim_libresoc_ibus_cyc + connect \ibus__dat_r \libresocsim_libresoc_ibus_dat_r + connect \ibus__dat_w \libresocsim_libresoc_ibus_dat_w + connect \ibus__err \libresocsim_libresoc_ibus_err + connect \ibus__sel \libresocsim_libresoc_ibus_sel + connect \ibus__stb \libresocsim_libresoc_ibus_stb + connect \ibus__we \libresocsim_libresoc_ibus_we + connect \icp_wb__ack \libresocsim_libresoc_xics_icp_ack + connect \icp_wb__adr \libresocsim_libresoc_xics_icp_adr + connect \icp_wb__cyc \libresocsim_libresoc_xics_icp_cyc + connect \icp_wb__dat_r \libresocsim_libresoc_xics_icp_dat_r + connect \icp_wb__dat_w \libresocsim_libresoc_xics_icp_dat_w + connect \icp_wb__err \libresocsim_libresoc_xics_icp_err + connect \icp_wb__sel \libresocsim_libresoc_xics_icp_sel + connect \icp_wb__stb \libresocsim_libresoc_xics_icp_stb + connect \icp_wb__we \libresocsim_libresoc_xics_icp_we + connect \ics_wb__ack \libresocsim_libresoc_xics_ics_ack + connect \ics_wb__adr \libresocsim_libresoc_xics_ics_adr + connect \ics_wb__cyc \libresocsim_libresoc_xics_ics_cyc + connect \ics_wb__dat_r \libresocsim_libresoc_xics_ics_dat_r + connect \ics_wb__dat_w \libresocsim_libresoc_xics_ics_dat_w + connect \ics_wb__err \libresocsim_libresoc_xics_ics_err + connect \ics_wb__sel \libresocsim_libresoc_xics_ics_sel + connect \ics_wb__stb \libresocsim_libresoc_xics_ics_stb + connect \ics_wb__we \libresocsim_libresoc_xics_ics_we + connect \int_level_i \libresocsim_libresoc_interrupt + connect \jtag_wb__ack \libresocsim_libresoc_jtag_wb_ack + connect \jtag_wb__adr \libresocsim_libresoc_jtag_wb_adr + connect \jtag_wb__cyc \libresocsim_libresoc_jtag_wb_cyc + connect \jtag_wb__dat_r \libresocsim_libresoc_jtag_wb_dat_r + connect \jtag_wb__dat_w \libresocsim_libresoc_jtag_wb_dat_w + connect \jtag_wb__err \libresocsim_libresoc_jtag_wb_err + connect \jtag_wb__sel \libresocsim_libresoc_jtag_wb_sel + connect \jtag_wb__stb \libresocsim_libresoc_jtag_wb_stb + connect \jtag_wb__we \libresocsim_libresoc_jtag_wb_we + connect \memerr_o \libresocsim_libresoc1 + connect \mspi0_clk__core__o \libresocsim_libresoc_constraintmanager_spimaster_clk + connect \mspi0_clk__pad__o \spimaster_clk + connect \mspi0_cs_n__core__o \libresocsim_libresoc_constraintmanager_spimaster_cs_n + connect \mspi0_cs_n__pad__o \spimaster_cs_n + connect \mspi0_miso__core__i \libresocsim_libresoc_constraintmanager_spimaster_miso + connect \mspi0_miso__pad__i \spimaster_miso + connect \mspi0_mosi__core__o \libresocsim_libresoc_constraintmanager_spimaster_mosi + connect \mspi0_mosi__pad__o \spimaster_mosi + connect \mtwi_scl__core__o \libresocsim_libresoc_constraintmanager_i2c_scl + connect \mtwi_scl__pad__o \i2c_scl + connect \mtwi_sda__core__i \libresocsim_libresoc_constraintmanager_i2c_sda_i + connect \mtwi_sda__core__o \libresocsim_libresoc_constraintmanager_i2c_sda_o + connect \mtwi_sda__core__oe \libresocsim_libresoc_constraintmanager_i2c_sda_oe + connect \mtwi_sda__pad__i \i2c_sda_i + connect \mtwi_sda__pad__o \i2c_sda_o + connect \mtwi_sda__pad__oe \i2c_sda_oe + connect \pc_i 1'0 + connect \pc_i_ok 1'0 + connect \pc_o \libresocsim_libresoc2 + connect \pll_18_o \libresocsim_libresoc_pll_18_o + connect \pll_lck_o \libresocsim_libresoc_pll_lck_o + connect \rst $or$ls180.v:5717$1546_Y + connect \sdr_a_0__core__o \libresocsim_libresoc_constraintmanager_sdram_a [0] + connect \sdr_a_0__pad__o \sdram_a [0] + connect \sdr_a_10__core__o \libresocsim_libresoc_constraintmanager_sdram_a [10] + connect \sdr_a_10__pad__o \sdram_a [10] + connect \sdr_a_11__core__o \libresocsim_libresoc_constraintmanager_sdram_a [11] + connect \sdr_a_11__pad__o \sdram_a [11] + connect \sdr_a_12__core__o \libresocsim_libresoc_constraintmanager_sdram_a [12] + connect \sdr_a_12__pad__o \sdram_a [12] + connect \sdr_a_1__core__o \libresocsim_libresoc_constraintmanager_sdram_a [1] + connect \sdr_a_1__pad__o \sdram_a [1] + connect \sdr_a_2__core__o \libresocsim_libresoc_constraintmanager_sdram_a [2] + connect \sdr_a_2__pad__o \sdram_a [2] + connect \sdr_a_3__core__o \libresocsim_libresoc_constraintmanager_sdram_a [3] + connect \sdr_a_3__pad__o \sdram_a [3] + connect \sdr_a_4__core__o \libresocsim_libresoc_constraintmanager_sdram_a [4] + connect \sdr_a_4__pad__o \sdram_a [4] + connect \sdr_a_5__core__o \libresocsim_libresoc_constraintmanager_sdram_a [5] + connect \sdr_a_5__pad__o \sdram_a [5] + connect \sdr_a_6__core__o \libresocsim_libresoc_constraintmanager_sdram_a [6] + connect \sdr_a_6__pad__o \sdram_a [6] + connect \sdr_a_7__core__o \libresocsim_libresoc_constraintmanager_sdram_a [7] + connect \sdr_a_7__pad__o \sdram_a [7] + connect \sdr_a_8__core__o \libresocsim_libresoc_constraintmanager_sdram_a [8] + connect \sdr_a_8__pad__o \sdram_a [8] + connect \sdr_a_9__core__o \libresocsim_libresoc_constraintmanager_sdram_a [9] + connect \sdr_a_9__pad__o \sdram_a [9] + connect \sdr_ba_0__core__o \libresocsim_libresoc_constraintmanager_sdram_ba [0] + connect \sdr_ba_0__pad__o \sdram_ba [0] + connect \sdr_ba_1__core__o \libresocsim_libresoc_constraintmanager_sdram_ba [1] + connect \sdr_ba_1__pad__o \sdram_ba [1] + connect \sdr_cas_n__core__o \libresocsim_libresoc_constraintmanager_sdram_cas_n + connect \sdr_cas_n__pad__o \sdram_cas_n + connect \sdr_cke__core__o \libresocsim_libresoc_constraintmanager_sdram_cke + connect \sdr_cke__pad__o \sdram_cke + connect \sdr_clock__core__o \libresocsim_libresoc_constraintmanager_sdram_clock + connect \sdr_clock__pad__o \sdram_clock + connect \sdr_cs_n__core__o \libresocsim_libresoc_constraintmanager_sdram_cs_n + connect \sdr_cs_n__pad__o \sdram_cs_n + connect \sdr_dm_0__core__o \libresocsim_libresoc_constraintmanager_sdram_dm [0] + connect \sdr_dm_0__pad__o \sdram_dm [0] + connect \sdr_dm_1__core__o \libresocsim_libresoc_constraintmanager_sdram_dm [1] + connect \sdr_dm_1__pad__o \sdram_dm [1] + connect \sdr_dq_0__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [0] + connect \sdr_dq_0__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [0] + connect \sdr_dq_0__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_0__pad__i \sdram_dq_i [0] + connect \sdr_dq_0__pad__o \sdram_dq_o [0] + connect \sdr_dq_0__pad__oe \sdram_dq_oe + connect \sdr_dq_10__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [10] + connect \sdr_dq_10__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [10] + connect \sdr_dq_10__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_10__pad__i \sdram_dq_i [10] + connect \sdr_dq_10__pad__o \sdram_dq_o [10] + connect \sdr_dq_10__pad__oe \sdram_dq_oe + connect \sdr_dq_11__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [11] + connect \sdr_dq_11__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [11] + connect \sdr_dq_11__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_11__pad__i \sdram_dq_i [11] + connect \sdr_dq_11__pad__o \sdram_dq_o [11] + connect \sdr_dq_11__pad__oe \sdram_dq_oe + connect \sdr_dq_12__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [12] + connect \sdr_dq_12__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [12] + connect \sdr_dq_12__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_12__pad__i \sdram_dq_i [12] + connect \sdr_dq_12__pad__o \sdram_dq_o [12] + connect \sdr_dq_12__pad__oe \sdram_dq_oe + connect \sdr_dq_13__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [13] + connect \sdr_dq_13__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [13] + connect \sdr_dq_13__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_13__pad__i \sdram_dq_i [13] + connect \sdr_dq_13__pad__o \sdram_dq_o [13] + connect \sdr_dq_13__pad__oe \sdram_dq_oe + connect \sdr_dq_14__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [14] + connect \sdr_dq_14__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [14] + connect \sdr_dq_14__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_14__pad__i \sdram_dq_i [14] + connect \sdr_dq_14__pad__o \sdram_dq_o [14] + connect \sdr_dq_14__pad__oe \sdram_dq_oe + connect \sdr_dq_15__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [15] + connect \sdr_dq_15__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [15] + connect \sdr_dq_15__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_15__pad__i \sdram_dq_i [15] + connect \sdr_dq_15__pad__o \sdram_dq_o [15] + connect \sdr_dq_15__pad__oe \sdram_dq_oe + connect \sdr_dq_1__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [1] + connect \sdr_dq_1__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [1] + connect \sdr_dq_1__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_1__pad__i \sdram_dq_i [1] + connect \sdr_dq_1__pad__o \sdram_dq_o [1] + connect \sdr_dq_1__pad__oe \sdram_dq_oe + connect \sdr_dq_2__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [2] + connect \sdr_dq_2__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [2] + connect \sdr_dq_2__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_2__pad__i \sdram_dq_i [2] + connect \sdr_dq_2__pad__o \sdram_dq_o [2] + connect \sdr_dq_2__pad__oe \sdram_dq_oe + connect \sdr_dq_3__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [3] + connect \sdr_dq_3__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [3] + connect \sdr_dq_3__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_3__pad__i \sdram_dq_i [3] + connect \sdr_dq_3__pad__o \sdram_dq_o [3] + connect \sdr_dq_3__pad__oe \sdram_dq_oe + connect \sdr_dq_4__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [4] + connect \sdr_dq_4__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [4] + connect \sdr_dq_4__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_4__pad__i \sdram_dq_i [4] + connect \sdr_dq_4__pad__o \sdram_dq_o [4] + connect \sdr_dq_4__pad__oe \sdram_dq_oe + connect \sdr_dq_5__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [5] + connect \sdr_dq_5__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [5] + connect \sdr_dq_5__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_5__pad__i \sdram_dq_i [5] + connect \sdr_dq_5__pad__o \sdram_dq_o [5] + connect \sdr_dq_5__pad__oe \sdram_dq_oe + connect \sdr_dq_6__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [6] + connect \sdr_dq_6__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [6] + connect \sdr_dq_6__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_6__pad__i \sdram_dq_i [6] + connect \sdr_dq_6__pad__o \sdram_dq_o [6] + connect \sdr_dq_6__pad__oe \sdram_dq_oe + connect \sdr_dq_7__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [7] + connect \sdr_dq_7__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [7] + connect \sdr_dq_7__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_7__pad__i \sdram_dq_i [7] + connect \sdr_dq_7__pad__o \sdram_dq_o [7] + connect \sdr_dq_7__pad__oe \sdram_dq_oe + connect \sdr_dq_8__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [8] + connect \sdr_dq_8__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [8] + connect \sdr_dq_8__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_8__pad__i \sdram_dq_i [8] + connect \sdr_dq_8__pad__o \sdram_dq_o [8] + connect \sdr_dq_8__pad__oe \sdram_dq_oe + connect \sdr_dq_9__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [9] + connect \sdr_dq_9__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [9] + connect \sdr_dq_9__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe + connect \sdr_dq_9__pad__i \sdram_dq_i [9] + connect \sdr_dq_9__pad__o \sdram_dq_o [9] + connect \sdr_dq_9__pad__oe \sdram_dq_oe + connect \sdr_ras_n__core__o \libresocsim_libresoc_constraintmanager_sdram_ras_n + connect \sdr_ras_n__pad__o \sdram_ras_n + connect \sdr_we_n__core__o \libresocsim_libresoc_constraintmanager_sdram_we_n + connect \sdr_we_n__pad__o \sdram_we_n end - attribute \src "ls180.v:4184.831-4184.871" - cell $eq $eq$ls180.v:4184$645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:4184$645_Y + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$2057 + sync always + sync init end - attribute \src "ls180.v:4184.934-4184.967" - cell $eq $eq$ls180.v:4184$646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$646_Y + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$2058 + sync always + sync init end - attribute \src "ls180.v:4184.1009-4184.1042" - cell $eq $eq$ls180.v:4184$649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$649_Y + attribute \src "ls180.v:1003.11-1003.29" + process $proc$ls180.v:1003$1942 + assign { } { } + assign $1\i2c_storage[2:0] 3'000 + sync always + sync init + update \i2c_storage $1\i2c_storage[2:0] end - attribute \src "ls180.v:4184.1084-4184.1117" - cell $eq $eq$ls180.v:4184$652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$652_Y + attribute \src "ls180.v:1004.5-1004.18" + process $proc$ls180.v:1004$1943 + assign { } { } + assign $1\i2c_re[0:0] 1'0 + sync always + sync init + update \i2c_re $1\i2c_re[0:0] end - attribute \src "ls180.v:4184.1166-4184.1199" - cell $eq $eq$ls180.v:4184$660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$660_Y + attribute \src "ls180.v:1008.5-1008.41" + process $proc$ls180.v:1008$1944 + assign { } { } + assign $1\subfragments_converter0_state[0:0] 1'0 + sync always + sync init + update \subfragments_converter0_state $1\subfragments_converter0_state[0:0] end - attribute \src "ls180.v:4184.1205-4184.1245" - cell $eq $eq$ls180.v:4184$661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:4184$661_Y + attribute \src "ls180.v:1009.5-1009.46" + process $proc$ls180.v:1009$1945 + assign { } { } + assign $1\subfragments_converter0_next_state[0:0] 1'0 + sync always + sync init + update \subfragments_converter0_next_state $1\subfragments_converter0_next_state[0:0] end - attribute \src "ls180.v:4184.1308-4184.1341" - cell $eq $eq$ls180.v:4184$662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$662_Y + attribute \src "ls180.v:1010.5-1010.77" + process $proc$ls180.v:1010$1946 + assign { } { } + assign $1\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] 1'0 + sync always + sync init + update \libresocsim_converter0_counter_subfragments_converter0_next_value $1\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] end - attribute \src "ls180.v:4184.1383-4184.1416" - cell $eq $eq$ls180.v:4184$665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$665_Y + attribute \src "ls180.v:1011.5-1011.80" + process $proc$ls180.v:1011$1947 + assign { } { } + assign $1\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0 + sync always + sync init + update \libresocsim_converter0_counter_subfragments_converter0_next_value_ce $1\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:4184.1458-4184.1491" - cell $eq $eq$ls180.v:4184$668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4184$668_Y + attribute \src "ls180.v:1012.5-1012.41" + process $proc$ls180.v:1012$1948 + assign { } { } + assign $1\subfragments_converter1_state[0:0] 1'0 + sync always + sync init + update \subfragments_converter1_state $1\subfragments_converter1_state[0:0] end - attribute \src "ls180.v:4243.29-4243.57" - cell $eq $eq$ls180.v:4243$681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_sel - connect \B 1'0 - connect \Y $eq$ls180.v:4243$681_Y + attribute \src "ls180.v:1013.5-1013.46" + process $proc$ls180.v:1013$1949 + assign { } { } + assign $1\subfragments_converter1_next_state[0:0] 1'0 + sync always + sync init + update \subfragments_converter1_next_state $1\subfragments_converter1_next_state[0:0] end - attribute \src "ls180.v:4250.11-4250.41" - cell $eq $eq$ls180.v:4250$686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_counter - connect \B 1'1 - connect \Y $eq$ls180.v:4250$686_Y + attribute \src "ls180.v:1014.5-1014.77" + process $proc$ls180.v:1014$1950 + assign { } { } + assign $1\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] 1'0 + sync always + sync init + update \libresocsim_converter1_counter_subfragments_converter1_next_value $1\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] end - attribute \src "ls180.v:4418.37-4418.111" - cell $eq $eq$ls180.v:4418$753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4418$752_Y - connect \Y $eq$ls180.v:4418$753_Y + attribute \src "ls180.v:1015.5-1015.80" + process $proc$ls180.v:1015$1951 + assign { } { } + assign $1\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0 + sync always + sync init + update \libresocsim_converter1_counter_subfragments_converter1_next_value_ce $1\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:4419.37-4419.105" - cell $eq $eq$ls180.v:4419$755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4419$754_Y - connect \Y $eq$ls180.v:4419$755_Y + attribute \src "ls180.v:1016.5-1016.41" + process $proc$ls180.v:1016$1952 + assign { } { } + assign $1\subfragments_converter2_state[0:0] 1'0 + sync always + sync init + update \subfragments_converter2_state $1\subfragments_converter2_state[0:0] end - attribute \src "ls180.v:4446.10-4446.67" - cell $eq $eq$ls180.v:4446$759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_spimaster27_count - connect \B $sub$ls180.v:4446$758_Y - connect \Y $eq$ls180.v:4446$759_Y + attribute \src "ls180.v:1017.5-1017.46" + process $proc$ls180.v:1017$1953 + assign { } { } + assign $1\subfragments_converter2_next_state[0:0] 1'0 + sync always + sync init + update \subfragments_converter2_next_state $1\subfragments_converter2_next_state[0:0] end - attribute \src "ls180.v:4476.35-4476.108" - cell $eq $eq$ls180.v:4476$761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4476$760_Y - connect \Y $eq$ls180.v:4476$761_Y + attribute \src "ls180.v:1018.5-1018.77" + process $proc$ls180.v:1018$1954 + assign { } { } + assign $1\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] 1'0 + sync always + sync init + update \libresocsim_converter2_counter_subfragments_converter2_next_value $1\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] end - attribute \src "ls180.v:4477.35-4477.102" - cell $eq $eq$ls180.v:4477$763 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4477$762_Y - connect \Y $eq$ls180.v:4477$763_Y + attribute \src "ls180.v:1019.5-1019.80" + process $proc$ls180.v:1019$1955 + assign { } { } + assign $1\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'0 + sync always + sync init + update \libresocsim_converter2_counter_subfragments_converter2_next_value_ce $1\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:4505.10-4505.65" - cell $eq $eq$ls180.v:4505$767 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_count - connect \B $sub$ls180.v:4505$766_Y - connect \Y $eq$ls180.v:4505$767_Y + attribute \src "ls180.v:102.5-102.44" + process $proc$ls180.v:102$1557 + assign { } { } + assign $1\libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + sync always + sync init + update \libresocsim_libresoc_jtag_wb_ack $1\libresocsim_libresoc_jtag_wb_ack[0:0] end - attribute \src "ls180.v:4609.10-4609.40" - cell $eq $eq$ls180.v:4609$794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_count - connect \B 7'1001111 - connect \Y $eq$ls180.v:4609$794_Y + attribute \src "ls180.v:1020.11-1020.46" + process $proc$ls180.v:1020$1956 + assign { } { } + assign $1\subfragments_refresher_state[1:0] 2'00 + sync always + sync init + update \subfragments_refresher_state $1\subfragments_refresher_state[1:0] end - attribute \src "ls180.v:4666.10-4666.39" - cell $eq $eq$ls180.v:4666$797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_count - connect \B 3'111 - connect \Y $eq$ls180.v:4666$797_Y + attribute \src "ls180.v:1021.11-1021.51" + process $proc$ls180.v:1021$1957 + assign { } { } + assign $1\subfragments_refresher_next_state[1:0] 2'00 + sync always + sync init + update \subfragments_refresher_next_state $1\subfragments_refresher_next_state[1:0] end - attribute \src "ls180.v:4683.10-4683.39" - cell $eq $eq$ls180.v:4683$799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_count - connect \B 3'111 - connect \Y $eq$ls180.v:4683$799_Y + attribute \src "ls180.v:1022.11-1022.49" + process $proc$ls180.v:1022$1958 + assign { } { } + assign $1\subfragments_bankmachine0_state[2:0] 3'000 + sync always + sync init + update \subfragments_bankmachine0_state $1\subfragments_bankmachine0_state[2:0] end - attribute \src "ls180.v:4711.38-4711.88" - cell $eq $eq$ls180.v:4711$801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - connect \B 1'0 - connect \Y $eq$ls180.v:4711$801_Y + attribute \src "ls180.v:1023.11-1023.54" + process $proc$ls180.v:1023$1959 + assign { } { } + assign $1\subfragments_bankmachine0_next_state[2:0] 3'000 + sync always + sync init + update \subfragments_bankmachine0_next_state $1\subfragments_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:4761.9-4761.40" - cell $eq $eq$ls180.v:4761$811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4761$811_Y + attribute \src "ls180.v:1024.11-1024.49" + process $proc$ls180.v:1024$1960 + assign { } { } + assign $1\subfragments_bankmachine1_state[2:0] 3'000 + sync always + sync init + update \subfragments_bankmachine1_state $1\subfragments_bankmachine1_state[2:0] end - attribute \src "ls180.v:4770.36-4770.105" - cell $eq $eq$ls180.v:4770$813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_count - connect \B $sub$ls180.v:4770$812_Y - connect \Y $eq$ls180.v:4770$813_Y + attribute \src "ls180.v:1025.11-1025.54" + process $proc$ls180.v:1025$1961 + assign { } { } + assign $1\subfragments_bankmachine1_next_state[2:0] 3'000 + sync always + sync init + update \subfragments_bankmachine1_next_state $1\subfragments_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:4789.9-4789.40" - cell $eq $eq$ls180.v:4789$817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4789$817_Y + attribute \src "ls180.v:1026.11-1026.49" + process $proc$ls180.v:1026$1962 + assign { } { } + assign $1\subfragments_bankmachine2_state[2:0] 3'000 + sync always + sync init + update \subfragments_bankmachine2_state $1\subfragments_bankmachine2_state[2:0] end - attribute \src "ls180.v:4801.10-4801.39" - cell $eq $eq$ls180.v:4801$819 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_count - connect \B 3'111 - connect \Y $eq$ls180.v:4801$819_Y + attribute \src "ls180.v:1027.11-1027.54" + process $proc$ls180.v:1027$1963 + assign { } { } + assign $1\subfragments_bankmachine2_next_state[2:0] 3'000 + sync always + sync init + update \subfragments_bankmachine2_next_state $1\subfragments_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:4838.39-4838.94" - cell $eq $eq$ls180.v:4838$823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] - connect \B 1'0 - connect \Y $eq$ls180.v:4838$823_Y + attribute \src "ls180.v:1028.11-1028.49" + process $proc$ls180.v:1028$1964 + assign { } { } + assign $1\subfragments_bankmachine3_state[2:0] 3'000 + sync always + sync init + update \subfragments_bankmachine3_state $1\subfragments_bankmachine3_state[2:0] end - attribute \src "ls180.v:4875.32-4875.89" - cell $eq $eq$ls180.v:4875$832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 - connect \B 3'101 - connect \Y $eq$ls180.v:4875$832_Y + attribute \src "ls180.v:1029.11-1029.54" + process $proc$ls180.v:1029$1965 + assign { } { } + assign $1\subfragments_bankmachine3_next_state[2:0] 3'000 + sync always + sync init + update \subfragments_bankmachine3_next_state $1\subfragments_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:4923.10-4923.40" - cell $eq $eq$ls180.v:4923$836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_count - connect \B 1'1 - connect \Y $eq$ls180.v:4923$836_Y + attribute \src "ls180.v:1030.11-1030.48" + process $proc$ls180.v:1030$1966 + assign { } { } + assign $1\subfragments_multiplexer_state[2:0] 3'000 + sync always + sync init + update \subfragments_multiplexer_state $1\subfragments_multiplexer_state[2:0] end - attribute \src "ls180.v:4972.40-4972.98" - cell $eq $eq$ls180.v:4972$838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_pads_in_payload_data_i - connect \B 1'0 - connect \Y $eq$ls180.v:4972$838_Y + attribute \src "ls180.v:1031.11-1031.53" + process $proc$ls180.v:1031$1967 + assign { } { } + assign $1\subfragments_multiplexer_next_state[2:0] 3'000 + sync always + sync init + update \subfragments_multiplexer_next_state $1\subfragments_multiplexer_next_state[2:0] end - attribute \src "ls180.v:5023.9-5023.41" - cell $eq $eq$ls180.v:5023$848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:5023$848_Y + attribute \src "ls180.v:104.5-104.44" + process $proc$ls180.v:104$1558 + assign { } { } + assign $0\libresocsim_libresoc_jtag_wb_err[0:0] 1'0 + sync always + update \libresocsim_libresoc_jtag_wb_err $0\libresocsim_libresoc_jtag_wb_err[0:0] + sync init end - attribute \src "ls180.v:5032.37-5032.123" - cell $eq $eq$ls180.v:5032$851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_count - connect \B $sub$ls180.v:5032$850_Y - connect \Y $eq$ls180.v:5032$851_Y + attribute \src "ls180.v:1044.5-1044.32" + process $proc$ls180.v:1044$1968 + assign { } { } + assign $0\subfragments_locked0[0:0] 1'0 + sync always + update \subfragments_locked0 $0\subfragments_locked0[0:0] + sync init end - attribute \src "ls180.v:5055.9-5055.41" - cell $eq $eq$ls180.v:5055$854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:5055$854_Y + attribute \src "ls180.v:1045.5-1045.32" + process $proc$ls180.v:1045$1969 + assign { } { } + assign $0\subfragments_locked1[0:0] 1'0 + sync always + update \subfragments_locked1 $0\subfragments_locked1[0:0] + sync init end - attribute \src "ls180.v:5065.10-5065.41" - cell $eq $eq$ls180.v:5065$856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_count - connect \B 6'100111 - connect \Y $eq$ls180.v:5065$856_Y + attribute \src "ls180.v:1046.5-1046.32" + process $proc$ls180.v:1046$1970 + assign { } { } + assign $0\subfragments_locked2[0:0] 1'0 + sync always + update \subfragments_locked2 $0\subfragments_locked2[0:0] + sync init end - attribute \src "ls180.v:5234.9-5234.47" - cell $eq $eq$ls180.v:5234$1038 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5234$1038_Y + attribute \src "ls180.v:1047.5-1047.32" + process $proc$ls180.v:1047$1971 + assign { } { } + assign $0\subfragments_locked3[0:0] 1'0 + sync always + update \subfragments_locked3 $0\subfragments_locked3[0:0] + sync init end - attribute \src "ls180.v:5264.10-5264.48" - cell $eq $eq$ls180.v:5264$1039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5264$1039_Y + attribute \src "ls180.v:1048.5-1048.47" + process $proc$ls180.v:1048$1972 + assign { } { } + assign $1\subfragments_new_master_wdata_ready[0:0] 1'0 + sync always + sync init + update \subfragments_new_master_wdata_ready $1\subfragments_new_master_wdata_ready[0:0] end - attribute \src "ls180.v:5295.10-5295.78" - cell $eq $eq$ls180.v:5295$1044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo0 - connect \B \main_sdcore_crc16_checker_crctmp0 - connect \Y $eq$ls180.v:5295$1044_Y + attribute \src "ls180.v:1049.5-1049.48" + process $proc$ls180.v:1049$1973 + assign { } { } + assign $1\subfragments_new_master_rdata_valid0[0:0] 1'0 + sync always + sync init + update \subfragments_new_master_rdata_valid0 $1\subfragments_new_master_rdata_valid0[0:0] end - attribute \src "ls180.v:5295.83-5295.151" - cell $eq $eq$ls180.v:5295$1045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo1 - connect \B \main_sdcore_crc16_checker_crctmp1 - connect \Y $eq$ls180.v:5295$1045_Y + attribute \src "ls180.v:1050.5-1050.48" + process $proc$ls180.v:1050$1974 + assign { } { } + assign $1\subfragments_new_master_rdata_valid1[0:0] 1'0 + sync always + sync init + update \subfragments_new_master_rdata_valid1 $1\subfragments_new_master_rdata_valid1[0:0] end - attribute \src "ls180.v:5295.157-5295.225" - cell $eq $eq$ls180.v:5295$1047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo2 - connect \B \main_sdcore_crc16_checker_crctmp2 - connect \Y $eq$ls180.v:5295$1047_Y + attribute \src "ls180.v:1051.5-1051.48" + process $proc$ls180.v:1051$1975 + assign { } { } + assign $1\subfragments_new_master_rdata_valid2[0:0] 1'0 + sync always + sync init + update \subfragments_new_master_rdata_valid2 $1\subfragments_new_master_rdata_valid2[0:0] end - attribute \src "ls180.v:5295.231-5295.299" - cell $eq $eq$ls180.v:5295$1049 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo3 - connect \B \main_sdcore_crc16_checker_crctmp3 - connect \Y $eq$ls180.v:5295$1049_Y + attribute \src "ls180.v:1052.5-1052.48" + process $proc$ls180.v:1052$1976 + assign { } { } + assign $1\subfragments_new_master_rdata_valid3[0:0] 1'0 + sync always + sync init + update \subfragments_new_master_rdata_valid3 $1\subfragments_new_master_rdata_valid3[0:0] end - attribute \src "ls180.v:5303.7-5303.44" - cell $eq $eq$ls180.v:5303$1053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5303$1053_Y + attribute \src "ls180.v:1053.5-1053.30" + process $proc$ls180.v:1053$1977 + assign { } { } + assign $1\subfragments_state[0:0] 1'0 + sync always + sync init + update \subfragments_state $1\subfragments_state[0:0] end - attribute \src "ls180.v:5313.7-5313.44" - cell $eq $eq$ls180.v:5313$1056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5313$1056_Y + attribute \src "ls180.v:1054.5-1054.35" + process $proc$ls180.v:1054$1978 + assign { } { } + assign $1\subfragments_next_state[0:0] 1'0 + sync always + sync init + update \subfragments_next_state $1\subfragments_next_state[0:0] end - attribute \src "ls180.v:5323.7-5323.44" - cell $eq $eq$ls180.v:5323$1059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5323$1059_Y + attribute \src "ls180.v:1055.5-1055.53" + process $proc$ls180.v:1055$1979 + assign { } { } + assign $1\converter_counter_subfragments_next_value[0:0] 1'0 + sync always + sync init + update \converter_counter_subfragments_next_value $1\converter_counter_subfragments_next_value[0:0] end - attribute \src "ls180.v:5333.7-5333.44" - cell $eq $eq$ls180.v:5333$1062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5333$1062_Y + attribute \src "ls180.v:1056.5-1056.56" + process $proc$ls180.v:1056$1980 + assign { } { } + assign $1\converter_counter_subfragments_next_value_ce[0:0] 1'0 + sync always + sync init + update \converter_counter_subfragments_next_value_ce $1\converter_counter_subfragments_next_value_ce[0:0] end - attribute \src "ls180.v:5457.36-5457.64" - cell $eq $eq$ls180.v:5457$1113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 1'0 - connect \Y $eq$ls180.v:5457$1113_Y + attribute \src "ls180.v:1057.12-1057.47" + process $proc$ls180.v:1057$1981 + assign { } { } + assign $1\libresocsim_libresocsim_adr[13:0] 14'00000000000000 + sync always + sync init + update \libresocsim_libresocsim_adr $1\libresocsim_libresocsim_adr[13:0] end - attribute \src "ls180.v:5463.10-5463.39" - cell $eq $eq$ls180.v:5463$1116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_count - connect \B 3'101 - connect \Y $eq$ls180.v:5463$1116_Y + attribute \src "ls180.v:1058.5-1058.38" + process $proc$ls180.v:1058$1982 + assign { } { } + assign $1\libresocsim_libresocsim_we[0:0] 1'0 + sync always + sync init + update \libresocsim_libresocsim_we $1\libresocsim_libresocsim_we[0:0] end - attribute \src "ls180.v:5464.11-5464.39" - cell $eq $eq$ls180.v:5464$1117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 1'0 - connect \Y $eq$ls180.v:5464$1117_Y + attribute \src "ls180.v:1059.11-1059.47" + process $proc$ls180.v:1059$1983 + assign { } { } + assign $1\libresocsim_libresocsim_dat_w[7:0] 8'00000000 + sync always + sync init + update \libresocsim_libresocsim_dat_w $1\libresocsim_libresocsim_dat_w[7:0] end - attribute \src "ls180.v:5476.34-5476.63" - cell $eq $eq$ls180.v:5476$1118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 1'0 - connect \Y $eq$ls180.v:5476$1118_Y + attribute \src "ls180.v:1063.12-1063.58" + process $proc$ls180.v:1063$1984 + assign { } { } + assign $1\libresocsim_libresocsim_wishbone_dat_r[31:0] 0 + sync always + sync init + update \libresocsim_libresocsim_wishbone_dat_r $1\libresocsim_libresocsim_wishbone_dat_r[31:0] end - attribute \src "ls180.v:5477.9-5477.37" - cell $eq $eq$ls180.v:5477$1119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 2'10 - connect \Y $eq$ls180.v:5477$1119_Y + attribute \src "ls180.v:1067.5-1067.48" + process $proc$ls180.v:1067$1985 + assign { } { } + assign $1\libresocsim_libresocsim_wishbone_ack[0:0] 1'0 + sync always + sync init + update \libresocsim_libresocsim_wishbone_ack $1\libresocsim_libresocsim_wishbone_ack[0:0] end - attribute \src "ls180.v:5484.10-5484.55" - cell $eq $eq$ls180.v:5484$1120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_payload_status - connect \B 1'1 - connect \Y $eq$ls180.v:5484$1120_Y + attribute \src "ls180.v:1071.5-1071.48" + process $proc$ls180.v:1071$1986 + assign { } { } + assign $0\libresocsim_libresocsim_wishbone_err[0:0] 1'0 + sync always + update \libresocsim_libresocsim_wishbone_err $0\libresocsim_libresocsim_wishbone_err[0:0] + sync init end - attribute \src "ls180.v:5490.12-5490.41" - cell $eq $eq$ls180.v:5490$1121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 2'10 - connect \Y $eq$ls180.v:5490$1121_Y + attribute \src "ls180.v:1074.12-1074.44" + process $proc$ls180.v:1074$1987 + assign { } { } + assign $1\libresocsim_shared_dat_r[31:0] 0 + sync always + sync init + update \libresocsim_shared_dat_r $1\libresocsim_shared_dat_r[31:0] end - attribute \src "ls180.v:5493.13-5493.42" - cell $eq $eq$ls180.v:5493$1122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 1'1 - connect \Y $eq$ls180.v:5493$1122_Y + attribute \src "ls180.v:1078.5-1078.34" + process $proc$ls180.v:1078$1988 + assign { } { } + assign $1\libresocsim_shared_ack[0:0] 1'0 + sync always + sync init + update \libresocsim_shared_ack $1\libresocsim_shared_ack[0:0] end - attribute \src "ls180.v:5515.10-5515.76" - cell $eq $eq$ls180.v:5515$1127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5515$1126_Y - connect \Y $eq$ls180.v:5515$1127_Y + attribute \src "ls180.v:1084.11-1084.35" + process $proc$ls180.v:1084$1989 + assign { } { } + assign $1\libresocsim_grant[1:0] 2'00 + sync always + sync init + update \libresocsim_grant $1\libresocsim_grant[1:0] end - attribute \src "ls180.v:5530.35-5530.101" - cell $eq $eq$ls180.v:5530$1130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5530$1129_Y - connect \Y $eq$ls180.v:5530$1130_Y + attribute \src "ls180.v:1085.11-1085.39" + process $proc$ls180.v:1085$1990 + assign { } { } + assign $1\libresocsim_slave_sel[5:0] 6'000000 + sync always + sync init + update \libresocsim_slave_sel $1\libresocsim_slave_sel[5:0] end - attribute \src "ls180.v:5532.10-5532.56" - cell $eq $eq$ls180.v:5532$1131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 1'0 - connect \Y $eq$ls180.v:5532$1131_Y + attribute \src "ls180.v:1086.11-1086.41" + process $proc$ls180.v:1086$1991 + assign { } { } + assign $1\libresocsim_slave_sel_r[5:0] 6'000000 + sync always + sync init + update \libresocsim_slave_sel_r $1\libresocsim_slave_sel_r[5:0] end - attribute \src "ls180.v:5541.12-5541.78" - cell $eq $eq$ls180.v:5541$1135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5541$1134_Y - connect \Y $eq$ls180.v:5541$1135_Y + attribute \src "ls180.v:1087.5-1087.29" + process $proc$ls180.v:1087$1992 + assign { } { } + assign $1\libresocsim_error[0:0] 1'0 + sync always + sync init + update \libresocsim_error $1\libresocsim_error[0:0] end - attribute \src "ls180.v:5548.11-5548.57" - cell $eq $eq$ls180.v:5548$1136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 1'1 - connect \Y $eq$ls180.v:5548$1136_Y + attribute \src "ls180.v:1090.12-1090.43" + process $proc$ls180.v:1090$1993 + assign { } { } + assign $1\libresocsim_count[19:0] 20'11110100001001000000 + sync always + sync init + update \libresocsim_count $1\libresocsim_count[19:0] end - attribute \src "ls180.v:5665.10-5665.105" - cell $eq $eq$ls180.v:5665$1153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B $sub$ls180.v:5665$1152_Y - connect \Y $eq$ls180.v:5665$1153_Y + attribute \src "ls180.v:1094.11-1094.55" + process $proc$ls180.v:1094$1994 + assign { } { } + assign $1\libresocsim_interface0_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \libresocsim_interface0_bank_bus_dat_r $1\libresocsim_interface0_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:5755.39-5755.106" - cell $eq $eq$ls180.v:5755$1159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_dma_offset - connect \B $sub$ls180.v:5755$1158_Y - connect \Y $eq$ls180.v:5755$1159_Y + attribute \src "ls180.v:1135.11-1135.55" + process $proc$ls180.v:1135$1995 + assign { } { } + assign $1\libresocsim_interface1_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \libresocsim_interface1_bank_bus_dat_r $1\libresocsim_interface1_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:5785.44-5785.82" - cell $eq $eq$ls180.v:5785$1162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_mux - connect \B 1'0 - connect \Y $eq$ls180.v:5785$1162_Y + attribute \src "ls180.v:115.5-115.58" + process $proc$ls180.v:115$1559 + assign { } { } + assign $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1 + sync always + sync init + update \libresocsim_libresoc_constraintmanager_uart_tx $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] end - attribute \src "ls180.v:5786.43-5786.81" - cell $eq $eq$ls180.v:5786$1163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_mux - connect \B 3'111 - connect \Y $eq$ls180.v:5786$1163_Y + attribute \src "ls180.v:1152.11-1152.55" + process $proc$ls180.v:1152$1996 + assign { } { } + assign $1\libresocsim_interface2_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \libresocsim_interface2_bank_bus_dat_r $1\libresocsim_interface2_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:5898.68-5898.89" - cell $eq $eq$ls180.v:5898$1179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'0 - connect \Y $eq$ls180.v:5898$1179_Y + attribute \src "ls180.v:116.5-116.58" + process $proc$ls180.v:116$1560 + assign { } { } + assign $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] 1'0 + sync always + update \libresocsim_libresoc_constraintmanager_uart_rx $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] + sync init end - attribute \src "ls180.v:5899.68-5899.89" - cell $eq $eq$ls180.v:5899$1181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'1 - connect \Y $eq$ls180.v:5899$1181_Y + attribute \src "ls180.v:1169.11-1169.55" + process $proc$ls180.v:1169$1997 + assign { } { } + assign $1\libresocsim_interface3_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \libresocsim_interface3_bank_bus_dat_r $1\libresocsim_interface3_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:5900.71-5900.92" - cell $eq $eq$ls180.v:5900$1183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'10 - connect \Y $eq$ls180.v:5900$1183_Y + attribute \src "ls180.v:1182.11-1182.55" + process $proc$ls180.v:1182$1998 + assign { } { } + assign $1\libresocsim_interface4_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \libresocsim_interface4_bank_bus_dat_r $1\libresocsim_interface4_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:5901.57-5901.78" - cell $eq $eq$ls180.v:5901$1185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'11 - connect \Y $eq$ls180.v:5901$1185_Y + attribute \src "ls180.v:122.12-122.65" + process $proc$ls180.v:122$1561 + assign { } { } + assign $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_libresoc_constraintmanager_gpio_o $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] end - attribute \src "ls180.v:5902.57-5902.78" - cell $eq $eq$ls180.v:5902$1187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 3'100 - connect \Y $eq$ls180.v:5902$1187_Y + attribute \src "ls180.v:1223.11-1223.55" + process $proc$ls180.v:1223$1999 + assign { } { } + assign $1\libresocsim_interface5_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \libresocsim_interface5_bank_bus_dat_r $1\libresocsim_interface5_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:5903.68-5903.89" - cell $eq $eq$ls180.v:5903$1189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'0 - connect \Y $eq$ls180.v:5903$1189_Y + attribute \src "ls180.v:123.12-123.66" + process $proc$ls180.v:123$1562 + assign { } { } + assign $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_libresoc_constraintmanager_gpio_oe $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] end - attribute \src "ls180.v:5904.68-5904.89" - cell $eq $eq$ls180.v:5904$1191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'1 - connect \Y $eq$ls180.v:5904$1191_Y + attribute \src "ls180.v:124.5-124.64" + process $proc$ls180.v:124$1563 + assign { } { } + assign $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] 1'0 + sync always + update \libresocsim_libresoc_constraintmanager_spimaster_clk $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] + sync init end - attribute \src "ls180.v:5905.71-5905.92" - cell $eq $eq$ls180.v:5905$1193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'10 - connect \Y $eq$ls180.v:5905$1193_Y + attribute \src "ls180.v:125.5-125.65" + process $proc$ls180.v:125$1564 + assign { } { } + assign $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] 1'0 + sync always + update \libresocsim_libresoc_constraintmanager_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] + sync init end - attribute \src "ls180.v:5906.57-5906.78" - cell $eq $eq$ls180.v:5906$1195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'11 - connect \Y $eq$ls180.v:5906$1195_Y + attribute \src "ls180.v:126.5-126.65" + process $proc$ls180.v:126$1565 + assign { } { } + assign $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] 1'0 + sync always + update \libresocsim_libresoc_constraintmanager_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] + sync init end - attribute \src "ls180.v:5907.57-5907.78" - cell $eq $eq$ls180.v:5907$1197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 3'100 - connect \Y $eq$ls180.v:5907$1197_Y + attribute \src "ls180.v:128.12-128.66" + process $proc$ls180.v:128$1566 + assign { } { } + assign $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] 13'0000000000000 + sync always + sync init + update \libresocsim_libresoc_constraintmanager_sdram_a $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] end - attribute \src "ls180.v:5911.27-5911.59" - cell $eq $eq$ls180.v:5911$1200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 1'0 - connect \Y $eq$ls180.v:5911$1200_Y + attribute \src "ls180.v:1288.11-1288.55" + process $proc$ls180.v:1288$2000 + assign { } { } + assign $1\libresocsim_interface6_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \libresocsim_interface6_bank_bus_dat_r $1\libresocsim_interface6_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:5912.27-5912.59" - cell $eq $eq$ls180.v:5912$1201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 1'1 - connect \Y $eq$ls180.v:5912$1201_Y + attribute \src "ls180.v:130.12-130.69" + process $proc$ls180.v:130$1567 + assign { } { } + assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_libresoc_constraintmanager_sdram_dq_o $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] end - attribute \src "ls180.v:5913.27-5913.59" - cell $eq $eq$ls180.v:5913$1202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 2'10 - connect \Y $eq$ls180.v:5913$1202_Y + attribute \src "ls180.v:131.5-131.62" + process $proc$ls180.v:131$1568 + assign { } { } + assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] 1'0 + sync always + sync init + update \libresocsim_libresoc_constraintmanager_sdram_dq_oe $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] end - attribute \src "ls180.v:5914.27-5914.59" - cell $eq $eq$ls180.v:5914$1203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 2'11 - connect \Y $eq$ls180.v:5914$1203_Y + attribute \src "ls180.v:1313.11-1313.55" + process $proc$ls180.v:1313$2001 + assign { } { } + assign $1\libresocsim_interface7_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \libresocsim_interface7_bank_bus_dat_r $1\libresocsim_interface7_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:5915.27-5915.59" - cell $eq $eq$ls180.v:5915$1204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 3'100 - connect \Y $eq$ls180.v:5915$1204_Y - end - attribute \src "ls180.v:5916.27-5916.68" - cell $eq $eq$ls180.v:5916$1205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 28 - parameter \B_SIGNED 0 - parameter \B_WIDTH 27 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:2] - connect \B 27'110000000000000100000000000 - connect \Y $eq$ls180.v:5916$1205_Y - end - attribute \src "ls180.v:5917.27-5917.65" - cell $eq $eq$ls180.v:5917$1206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 21 - parameter \B_SIGNED 0 - parameter \B_WIDTH 20 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 20'11000000000000010001 - connect \Y $eq$ls180.v:5917$1206_Y - end - attribute \src "ls180.v:5918.27-5918.59" - cell $eq $eq$ls180.v:5918$1207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 21 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 1'1 - connect \Y $eq$ls180.v:5918$1207_Y - end - attribute \src "ls180.v:5919.27-5919.59" - cell $eq $eq$ls180.v:5919$1208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 21 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 2'10 - connect \Y $eq$ls180.v:5919$1208_Y - end - attribute \src "ls180.v:5920.27-5920.59" - cell $eq $eq$ls180.v:5920$1209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 21 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 2'11 - connect \Y $eq$ls180.v:5920$1209_Y - end - attribute \src "ls180.v:5921.28-5921.60" - cell $eq $eq$ls180.v:5921$1210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 21 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 3'100 - connect \Y $eq$ls180.v:5921$1210_Y - end - attribute \src "ls180.v:5922.28-5922.62" - cell $eq $eq$ls180.v:5922$1211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:22] - connect \B 7'1001000 - connect \Y $eq$ls180.v:5922$1211_Y - end - attribute \src "ls180.v:5923.28-5923.66" - cell $eq $eq$ls180.v:5923$1212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 17 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:13] - connect \B 16'1100000000000000 - connect \Y $eq$ls180.v:5923$1212_Y - end - attribute \src "ls180.v:6043.24-6043.45" - cell $eq $eq$ls180.v:6043$1279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_count - connect \B 1'0 - connect \Y $eq$ls180.v:6043$1279_Y - end - attribute \src "ls180.v:6044.32-6044.77" - cell $eq $eq$ls180.v:6044$1280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [13:8] - connect \B 1'0 - connect \Y $eq$ls180.v:6044$1280_Y - end - attribute \src "ls180.v:6046.97-6046.141" - cell $eq $eq$ls180.v:6046$1282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6046$1282_Y - end - attribute \src "ls180.v:6047.100-6047.144" - cell $eq $eq$ls180.v:6047$1286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6047$1286_Y - end - attribute \src "ls180.v:6049.99-6049.143" - cell $eq $eq$ls180.v:6049$1289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6049$1289_Y - end - attribute \src "ls180.v:6050.102-6050.146" - cell $eq $eq$ls180.v:6050$1293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6050$1293_Y - end - attribute \src "ls180.v:6052.99-6052.143" - cell $eq $eq$ls180.v:6052$1296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6052$1296_Y - end - attribute \src "ls180.v:6053.102-6053.146" - cell $eq $eq$ls180.v:6053$1300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6053$1300_Y - end - attribute \src "ls180.v:6055.99-6055.143" - cell $eq $eq$ls180.v:6055$1303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6055$1303_Y - end - attribute \src "ls180.v:6056.102-6056.146" - cell $eq $eq$ls180.v:6056$1307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6056$1307_Y - end - attribute \src "ls180.v:6058.99-6058.143" - cell $eq $eq$ls180.v:6058$1310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6058$1310_Y - end - attribute \src "ls180.v:6059.102-6059.146" - cell $eq $eq$ls180.v:6059$1314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6059$1314_Y - end - attribute \src "ls180.v:6061.102-6061.146" - cell $eq $eq$ls180.v:6061$1317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6061$1317_Y - end - attribute \src "ls180.v:6062.105-6062.149" - cell $eq $eq$ls180.v:6062$1321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6062$1321_Y - end - attribute \src "ls180.v:6064.102-6064.146" - cell $eq $eq$ls180.v:6064$1324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6064$1324_Y - end - attribute \src "ls180.v:6065.105-6065.149" - cell $eq $eq$ls180.v:6065$1328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6065$1328_Y - end - attribute \src "ls180.v:6067.102-6067.146" - cell $eq $eq$ls180.v:6067$1331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6067$1331_Y - end - attribute \src "ls180.v:6068.105-6068.149" - cell $eq $eq$ls180.v:6068$1335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6068$1335_Y - end - attribute \src "ls180.v:6070.102-6070.146" - cell $eq $eq$ls180.v:6070$1338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6070$1338_Y - end - attribute \src "ls180.v:6071.105-6071.149" - cell $eq $eq$ls180.v:6071$1342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6071$1342_Y - end - attribute \src "ls180.v:6082.32-6082.77" - cell $eq $eq$ls180.v:6082$1344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [13:8] - connect \B 3'110 - connect \Y $eq$ls180.v:6082$1344_Y - end - attribute \src "ls180.v:6084.94-6084.138" - cell $eq $eq$ls180.v:6084$1346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6084$1346_Y - end - attribute \src "ls180.v:6085.97-6085.141" - cell $eq $eq$ls180.v:6085$1350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6085$1350_Y - end - attribute \src "ls180.v:6087.94-6087.138" - cell $eq $eq$ls180.v:6087$1353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6087$1353_Y - end - attribute \src "ls180.v:6088.97-6088.141" - cell $eq $eq$ls180.v:6088$1357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6088$1357_Y - end - attribute \src "ls180.v:6090.94-6090.138" - cell $eq $eq$ls180.v:6090$1360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6090$1360_Y - end - attribute \src "ls180.v:6091.97-6091.141" - cell $eq $eq$ls180.v:6091$1364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6091$1364_Y - end - attribute \src "ls180.v:6093.94-6093.138" - cell $eq $eq$ls180.v:6093$1367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6093$1367_Y - end - attribute \src "ls180.v:6094.97-6094.141" - cell $eq $eq$ls180.v:6094$1371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6094$1371_Y - end - attribute \src "ls180.v:6096.95-6096.139" - cell $eq $eq$ls180.v:6096$1374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6096$1374_Y - end - attribute \src "ls180.v:6097.98-6097.142" - cell $eq $eq$ls180.v:6097$1378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6097$1378_Y - end - attribute \src "ls180.v:6099.95-6099.139" - cell $eq $eq$ls180.v:6099$1381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6099$1381_Y - end - attribute \src "ls180.v:6100.98-6100.142" - cell $eq $eq$ls180.v:6100$1385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6100$1385_Y - end - attribute \src "ls180.v:6108.32-6108.78" - cell $eq $eq$ls180.v:6108$1387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [13:8] - connect \B 4'1100 - connect \Y $eq$ls180.v:6108$1387_Y - end - attribute \src "ls180.v:6110.93-6110.135" - cell $eq $eq$ls180.v:6110$1389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'0 - connect \Y $eq$ls180.v:6110$1389_Y - end - attribute \src "ls180.v:6111.96-6111.138" - cell $eq $eq$ls180.v:6111$1393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'0 - connect \Y $eq$ls180.v:6111$1393_Y - end - attribute \src "ls180.v:6113.92-6113.134" - cell $eq $eq$ls180.v:6113$1396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'1 - connect \Y $eq$ls180.v:6113$1396_Y - end - attribute \src "ls180.v:6114.95-6114.137" - cell $eq $eq$ls180.v:6114$1400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'1 - connect \Y $eq$ls180.v:6114$1400_Y - end - attribute \src "ls180.v:6122.32-6122.78" - cell $eq $eq$ls180.v:6122$1402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [13:8] - connect \B 4'1010 - connect \Y $eq$ls180.v:6122$1402_Y - end - attribute \src "ls180.v:6124.98-6124.142" - cell $eq $eq$ls180.v:6124$1404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6124$1404_Y - end - attribute \src "ls180.v:6125.101-6125.145" - cell $eq $eq$ls180.v:6125$1408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6125$1408_Y - end - attribute \src "ls180.v:6127.97-6127.141" - cell $eq $eq$ls180.v:6127$1411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6127$1411_Y - end - attribute \src "ls180.v:6128.100-6128.144" - cell $eq $eq$ls180.v:6128$1415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6128$1415_Y - end - attribute \src "ls180.v:6130.97-6130.141" - cell $eq $eq$ls180.v:6130$1418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6130$1418_Y - end - attribute \src "ls180.v:6131.100-6131.144" - cell $eq $eq$ls180.v:6131$1422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6131$1422_Y - end - attribute \src "ls180.v:6133.97-6133.141" - cell $eq $eq$ls180.v:6133$1425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6133$1425_Y - end - attribute \src "ls180.v:6134.100-6134.144" - cell $eq $eq$ls180.v:6134$1429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6134$1429_Y - end - attribute \src "ls180.v:6136.97-6136.141" - cell $eq $eq$ls180.v:6136$1432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6136$1432_Y - end - attribute \src "ls180.v:6137.100-6137.144" - cell $eq $eq$ls180.v:6137$1436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6137$1436_Y - end - attribute \src "ls180.v:6139.98-6139.142" - cell $eq $eq$ls180.v:6139$1439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6139$1439_Y - end - attribute \src "ls180.v:6140.101-6140.145" - cell $eq $eq$ls180.v:6140$1443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6140$1443_Y - end - attribute \src "ls180.v:6142.98-6142.142" - cell $eq $eq$ls180.v:6142$1446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6142$1446_Y - end - attribute \src "ls180.v:6143.101-6143.145" - cell $eq $eq$ls180.v:6143$1450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6143$1450_Y - end - attribute \src "ls180.v:6145.98-6145.142" - cell $eq $eq$ls180.v:6145$1453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6145$1453_Y - end - attribute \src "ls180.v:6146.101-6146.145" - cell $eq $eq$ls180.v:6146$1457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6146$1457_Y - end - attribute \src "ls180.v:6148.98-6148.142" - cell $eq $eq$ls180.v:6148$1460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6148$1460_Y - end - attribute \src "ls180.v:6149.101-6149.145" - cell $eq $eq$ls180.v:6149$1464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6149$1464_Y - end - attribute \src "ls180.v:6159.32-6159.78" - cell $eq $eq$ls180.v:6159$1466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [13:8] - connect \B 4'1011 - connect \Y $eq$ls180.v:6159$1466_Y - end - attribute \src "ls180.v:6161.98-6161.142" - cell $eq $eq$ls180.v:6161$1468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6161$1468_Y - end - attribute \src "ls180.v:6162.101-6162.145" - cell $eq $eq$ls180.v:6162$1472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6162$1472_Y - end - attribute \src "ls180.v:6164.97-6164.141" - cell $eq $eq$ls180.v:6164$1475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6164$1475_Y - end - attribute \src "ls180.v:6165.100-6165.144" - cell $eq $eq$ls180.v:6165$1479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6165$1479_Y - end - attribute \src "ls180.v:6167.97-6167.141" - cell $eq $eq$ls180.v:6167$1482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6167$1482_Y - end - attribute \src "ls180.v:6168.100-6168.144" - cell $eq $eq$ls180.v:6168$1486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6168$1486_Y - end - attribute \src "ls180.v:6170.97-6170.141" - cell $eq $eq$ls180.v:6170$1489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6170$1489_Y - end - attribute \src "ls180.v:6171.100-6171.144" - cell $eq $eq$ls180.v:6171$1493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6171$1493_Y - end - attribute \src "ls180.v:6173.97-6173.141" - cell $eq $eq$ls180.v:6173$1496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6173$1496_Y - end - attribute \src "ls180.v:6174.100-6174.144" - cell $eq $eq$ls180.v:6174$1500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6174$1500_Y - end - attribute \src "ls180.v:6176.98-6176.142" - cell $eq $eq$ls180.v:6176$1503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6176$1503_Y - end - attribute \src "ls180.v:6177.101-6177.145" - cell $eq $eq$ls180.v:6177$1507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6177$1507_Y - end - attribute \src "ls180.v:6179.98-6179.142" - cell $eq $eq$ls180.v:6179$1510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6179$1510_Y - end - attribute \src "ls180.v:6180.101-6180.145" - cell $eq $eq$ls180.v:6180$1514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6180$1514_Y - end - attribute \src "ls180.v:6182.98-6182.142" - cell $eq $eq$ls180.v:6182$1517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6182$1517_Y - end - attribute \src "ls180.v:6183.101-6183.145" - cell $eq $eq$ls180.v:6183$1521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6183$1521_Y - end - attribute \src "ls180.v:6185.98-6185.142" - cell $eq $eq$ls180.v:6185$1524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6185$1524_Y - end - attribute \src "ls180.v:6186.101-6186.145" - cell $eq $eq$ls180.v:6186$1528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6186$1528_Y - end - attribute \src "ls180.v:6196.32-6196.78" - cell $eq $eq$ls180.v:6196$1530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [13:8] - connect \B 4'1111 - connect \Y $eq$ls180.v:6196$1530_Y - end - attribute \src "ls180.v:6198.100-6198.144" - cell $eq $eq$ls180.v:6198$1532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6198$1532_Y - end - attribute \src "ls180.v:6199.103-6199.147" - cell $eq $eq$ls180.v:6199$1536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6199$1536_Y - end - attribute \src "ls180.v:6201.100-6201.144" - cell $eq $eq$ls180.v:6201$1539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6201$1539_Y - end - attribute \src "ls180.v:6202.103-6202.147" - cell $eq $eq$ls180.v:6202$1543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6202$1543_Y - end - attribute \src "ls180.v:6204.100-6204.144" - cell $eq $eq$ls180.v:6204$1546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6204$1546_Y - end - attribute \src "ls180.v:6205.103-6205.147" - cell $eq $eq$ls180.v:6205$1550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6205$1550_Y - end - attribute \src "ls180.v:6207.100-6207.144" - cell $eq $eq$ls180.v:6207$1553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6207$1553_Y - end - attribute \src "ls180.v:6208.103-6208.147" - cell $eq $eq$ls180.v:6208$1557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6208$1557_Y - end - attribute \src "ls180.v:6210.100-6210.144" - cell $eq $eq$ls180.v:6210$1560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6210$1560_Y - end - attribute \src "ls180.v:6211.103-6211.147" - cell $eq $eq$ls180.v:6211$1564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6211$1564_Y - end - attribute \src "ls180.v:6213.100-6213.144" - cell $eq $eq$ls180.v:6213$1567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6213$1567_Y - end - attribute \src "ls180.v:6214.103-6214.147" - cell $eq $eq$ls180.v:6214$1571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6214$1571_Y - end - attribute \src "ls180.v:6216.100-6216.144" - cell $eq $eq$ls180.v:6216$1574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6216$1574_Y - end - attribute \src "ls180.v:6217.103-6217.147" - cell $eq $eq$ls180.v:6217$1578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6217$1578_Y - end - attribute \src "ls180.v:6219.100-6219.144" - cell $eq $eq$ls180.v:6219$1581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6219$1581_Y - end - attribute \src "ls180.v:6220.103-6220.147" - cell $eq $eq$ls180.v:6220$1585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6220$1585_Y - end - attribute \src "ls180.v:6222.102-6222.146" - cell $eq $eq$ls180.v:6222$1588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6222$1588_Y - end - attribute \src "ls180.v:6223.105-6223.149" - cell $eq $eq$ls180.v:6223$1592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6223$1592_Y - end - attribute \src "ls180.v:6225.102-6225.146" - cell $eq $eq$ls180.v:6225$1595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6225$1595_Y - end - attribute \src "ls180.v:6226.105-6226.149" - cell $eq $eq$ls180.v:6226$1599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6226$1599_Y - end - attribute \src "ls180.v:6228.102-6228.147" - cell $eq $eq$ls180.v:6228$1602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6228$1602_Y - end - attribute \src "ls180.v:6229.105-6229.150" - cell $eq $eq$ls180.v:6229$1606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6229$1606_Y - end - attribute \src "ls180.v:6231.102-6231.147" - cell $eq $eq$ls180.v:6231$1609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6231$1609_Y - end - attribute \src "ls180.v:6232.105-6232.150" - cell $eq $eq$ls180.v:6232$1613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6232$1613_Y - end - attribute \src "ls180.v:6234.102-6234.147" - cell $eq $eq$ls180.v:6234$1616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6234$1616_Y - end - attribute \src "ls180.v:6235.105-6235.150" - cell $eq $eq$ls180.v:6235$1620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6235$1620_Y - end - attribute \src "ls180.v:6237.99-6237.144" - cell $eq $eq$ls180.v:6237$1623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6237$1623_Y - end - attribute \src "ls180.v:6238.102-6238.147" - cell $eq $eq$ls180.v:6238$1627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6238$1627_Y - end - attribute \src "ls180.v:6240.100-6240.145" - cell $eq $eq$ls180.v:6240$1630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6240$1630_Y - end - attribute \src "ls180.v:6241.103-6241.148" - cell $eq $eq$ls180.v:6241$1634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6241$1634_Y - end - attribute \src "ls180.v:6258.32-6258.78" - cell $eq $eq$ls180.v:6258$1636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [13:8] - connect \B 4'1110 - connect \Y $eq$ls180.v:6258$1636_Y - end - attribute \src "ls180.v:6260.104-6260.148" - cell $eq $eq$ls180.v:6260$1638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6260$1638_Y - end - attribute \src "ls180.v:6261.107-6261.151" - cell $eq $eq$ls180.v:6261$1642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6261$1642_Y - end - attribute \src "ls180.v:6263.104-6263.148" - cell $eq $eq$ls180.v:6263$1645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6263$1645_Y - end - attribute \src "ls180.v:6264.107-6264.151" - cell $eq $eq$ls180.v:6264$1649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6264$1649_Y - end - attribute \src "ls180.v:6266.104-6266.148" - cell $eq $eq$ls180.v:6266$1652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6266$1652_Y - end - attribute \src "ls180.v:6267.107-6267.151" - cell $eq $eq$ls180.v:6267$1656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6267$1656_Y - end - attribute \src "ls180.v:6269.104-6269.148" - cell $eq $eq$ls180.v:6269$1659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6269$1659_Y - end - attribute \src "ls180.v:6270.107-6270.151" - cell $eq $eq$ls180.v:6270$1663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6270$1663_Y - end - attribute \src "ls180.v:6272.103-6272.147" - cell $eq $eq$ls180.v:6272$1666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6272$1666_Y - end - attribute \src "ls180.v:6273.106-6273.150" - cell $eq $eq$ls180.v:6273$1670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6273$1670_Y - end - attribute \src "ls180.v:6275.103-6275.147" - cell $eq $eq$ls180.v:6275$1673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6275$1673_Y - end - attribute \src "ls180.v:6276.106-6276.150" - cell $eq $eq$ls180.v:6276$1677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6276$1677_Y - end - attribute \src "ls180.v:6278.103-6278.147" - cell $eq $eq$ls180.v:6278$1680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6278$1680_Y - end - attribute \src "ls180.v:6279.106-6279.150" - cell $eq $eq$ls180.v:6279$1684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6279$1684_Y - end - attribute \src "ls180.v:6281.103-6281.147" - cell $eq $eq$ls180.v:6281$1687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6281$1687_Y - end - attribute \src "ls180.v:6282.106-6282.150" - cell $eq $eq$ls180.v:6282$1691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6282$1691_Y - end - attribute \src "ls180.v:6284.94-6284.138" - cell $eq $eq$ls180.v:6284$1694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6284$1694_Y - end - attribute \src "ls180.v:6285.97-6285.141" - cell $eq $eq$ls180.v:6285$1698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6285$1698_Y - end - attribute \src "ls180.v:6287.105-6287.149" - cell $eq $eq$ls180.v:6287$1701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6287$1701_Y - end - attribute \src "ls180.v:6288.108-6288.152" - cell $eq $eq$ls180.v:6288$1705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6288$1705_Y - end - attribute \src "ls180.v:6290.105-6290.150" - cell $eq $eq$ls180.v:6290$1708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6290$1708_Y - end - attribute \src "ls180.v:6291.108-6291.153" - cell $eq $eq$ls180.v:6291$1712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6291$1712_Y - end - attribute \src "ls180.v:6293.105-6293.150" - cell $eq $eq$ls180.v:6293$1715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6293$1715_Y - end - attribute \src "ls180.v:6294.108-6294.153" - cell $eq $eq$ls180.v:6294$1719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6294$1719_Y - end - attribute \src "ls180.v:6296.105-6296.150" - cell $eq $eq$ls180.v:6296$1722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6296$1722_Y - end - attribute \src "ls180.v:6297.108-6297.153" - cell $eq $eq$ls180.v:6297$1726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6297$1726_Y - end - attribute \src "ls180.v:6299.105-6299.150" - cell $eq $eq$ls180.v:6299$1729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6299$1729_Y - end - attribute \src "ls180.v:6300.108-6300.153" - cell $eq $eq$ls180.v:6300$1733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6300$1733_Y - end - attribute \src "ls180.v:6302.105-6302.150" - cell $eq $eq$ls180.v:6302$1736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6302$1736_Y - end - attribute \src "ls180.v:6303.108-6303.153" - cell $eq $eq$ls180.v:6303$1740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6303$1740_Y - end - attribute \src "ls180.v:6305.104-6305.149" - cell $eq $eq$ls180.v:6305$1743 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6305$1743_Y - end - attribute \src "ls180.v:6306.107-6306.152" - cell $eq $eq$ls180.v:6306$1747 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6306$1747_Y - end - attribute \src "ls180.v:6308.104-6308.149" - cell $eq $eq$ls180.v:6308$1750 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6308$1750_Y - end - attribute \src "ls180.v:6309.107-6309.152" - cell $eq $eq$ls180.v:6309$1754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6309$1754_Y - end - attribute \src "ls180.v:6311.104-6311.149" - cell $eq $eq$ls180.v:6311$1757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6311$1757_Y - end - attribute \src "ls180.v:6312.107-6312.152" - cell $eq $eq$ls180.v:6312$1761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6312$1761_Y - end - attribute \src "ls180.v:6314.104-6314.149" - cell $eq $eq$ls180.v:6314$1764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6314$1764_Y - end - attribute \src "ls180.v:6315.107-6315.152" - cell $eq $eq$ls180.v:6315$1768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6315$1768_Y - end - attribute \src "ls180.v:6317.104-6317.149" - cell $eq $eq$ls180.v:6317$1771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10011 - connect \Y $eq$ls180.v:6317$1771_Y - end - attribute \src "ls180.v:6318.107-6318.152" - cell $eq $eq$ls180.v:6318$1775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10011 - connect \Y $eq$ls180.v:6318$1775_Y - end - attribute \src "ls180.v:6320.104-6320.149" - cell $eq $eq$ls180.v:6320$1778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10100 - connect \Y $eq$ls180.v:6320$1778_Y - end - attribute \src "ls180.v:6321.107-6321.152" - cell $eq $eq$ls180.v:6321$1782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10100 - connect \Y $eq$ls180.v:6321$1782_Y - end - attribute \src "ls180.v:6323.104-6323.149" - cell $eq $eq$ls180.v:6323$1785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10101 - connect \Y $eq$ls180.v:6323$1785_Y - end - attribute \src "ls180.v:6324.107-6324.152" - cell $eq $eq$ls180.v:6324$1789 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10101 - connect \Y $eq$ls180.v:6324$1789_Y - end - attribute \src "ls180.v:6326.104-6326.149" - cell $eq $eq$ls180.v:6326$1792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10110 - connect \Y $eq$ls180.v:6326$1792_Y - end - attribute \src "ls180.v:6327.107-6327.152" - cell $eq $eq$ls180.v:6327$1796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10110 - connect \Y $eq$ls180.v:6327$1796_Y - end - attribute \src "ls180.v:6329.104-6329.149" - cell $eq $eq$ls180.v:6329$1799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10111 - connect \Y $eq$ls180.v:6329$1799_Y - end - attribute \src "ls180.v:6330.107-6330.152" - cell $eq $eq$ls180.v:6330$1803 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10111 - connect \Y $eq$ls180.v:6330$1803_Y - end - attribute \src "ls180.v:6332.104-6332.149" - cell $eq $eq$ls180.v:6332$1806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11000 - connect \Y $eq$ls180.v:6332$1806_Y - end - attribute \src "ls180.v:6333.107-6333.152" - cell $eq $eq$ls180.v:6333$1810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11000 - connect \Y $eq$ls180.v:6333$1810_Y - end - attribute \src "ls180.v:6335.100-6335.145" - cell $eq $eq$ls180.v:6335$1813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11001 - connect \Y $eq$ls180.v:6335$1813_Y - end - attribute \src "ls180.v:6336.103-6336.148" - cell $eq $eq$ls180.v:6336$1817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11001 - connect \Y $eq$ls180.v:6336$1817_Y - end - attribute \src "ls180.v:6338.101-6338.146" - cell $eq $eq$ls180.v:6338$1820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11010 - connect \Y $eq$ls180.v:6338$1820_Y - end - attribute \src "ls180.v:6339.104-6339.149" - cell $eq $eq$ls180.v:6339$1824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11010 - connect \Y $eq$ls180.v:6339$1824_Y - end - attribute \src "ls180.v:6341.104-6341.149" - cell $eq $eq$ls180.v:6341$1827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11011 - connect \Y $eq$ls180.v:6341$1827_Y - end - attribute \src "ls180.v:6342.107-6342.152" - cell $eq $eq$ls180.v:6342$1831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11011 - connect \Y $eq$ls180.v:6342$1831_Y - end - attribute \src "ls180.v:6344.104-6344.149" - cell $eq $eq$ls180.v:6344$1834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11100 - connect \Y $eq$ls180.v:6344$1834_Y - end - attribute \src "ls180.v:6345.107-6345.152" - cell $eq $eq$ls180.v:6345$1838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11100 - connect \Y $eq$ls180.v:6345$1838_Y - end - attribute \src "ls180.v:6347.103-6347.148" - cell $eq $eq$ls180.v:6347$1841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11101 - connect \Y $eq$ls180.v:6347$1841_Y - end - attribute \src "ls180.v:6348.106-6348.151" - cell $eq $eq$ls180.v:6348$1845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11101 - connect \Y $eq$ls180.v:6348$1845_Y - end - attribute \src "ls180.v:6350.103-6350.148" - cell $eq $eq$ls180.v:6350$1848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11110 - connect \Y $eq$ls180.v:6350$1848_Y - end - attribute \src "ls180.v:6351.106-6351.151" - cell $eq $eq$ls180.v:6351$1852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11110 - connect \Y $eq$ls180.v:6351$1852_Y - end - attribute \src "ls180.v:6353.103-6353.148" - cell $eq $eq$ls180.v:6353$1855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11111 - connect \Y $eq$ls180.v:6353$1855_Y - end - attribute \src "ls180.v:6354.106-6354.151" - cell $eq $eq$ls180.v:6354$1859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11111 - connect \Y $eq$ls180.v:6354$1859_Y - end - attribute \src "ls180.v:6356.103-6356.148" - cell $eq $eq$ls180.v:6356$1862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 6'100000 - connect \Y $eq$ls180.v:6356$1862_Y - end - attribute \src "ls180.v:6357.106-6357.151" - cell $eq $eq$ls180.v:6357$1866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 6'100000 - connect \Y $eq$ls180.v:6357$1866_Y - end - attribute \src "ls180.v:6393.32-6393.78" - cell $eq $eq$ls180.v:6393$1868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [13:8] - connect \B 5'10000 - connect \Y $eq$ls180.v:6393$1868_Y - end - attribute \src "ls180.v:6395.100-6395.144" - cell $eq $eq$ls180.v:6395$1870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6395$1870_Y - end - attribute \src "ls180.v:6396.103-6396.147" - cell $eq $eq$ls180.v:6396$1874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6396$1874_Y - end - attribute \src "ls180.v:6398.100-6398.144" - cell $eq $eq$ls180.v:6398$1877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6398$1877_Y - end - attribute \src "ls180.v:6399.103-6399.147" - cell $eq $eq$ls180.v:6399$1881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6399$1881_Y - end - attribute \src "ls180.v:6401.100-6401.144" - cell $eq $eq$ls180.v:6401$1884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6401$1884_Y - end - attribute \src "ls180.v:6402.103-6402.147" - cell $eq $eq$ls180.v:6402$1888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6402$1888_Y - end - attribute \src "ls180.v:6404.100-6404.144" - cell $eq $eq$ls180.v:6404$1891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6404$1891_Y - end - attribute \src "ls180.v:6405.103-6405.147" - cell $eq $eq$ls180.v:6405$1895 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6405$1895_Y - end - attribute \src "ls180.v:6407.100-6407.144" - cell $eq $eq$ls180.v:6407$1898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6407$1898_Y - end - attribute \src "ls180.v:6408.103-6408.147" - cell $eq $eq$ls180.v:6408$1902 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6408$1902_Y - end - attribute \src "ls180.v:6410.100-6410.144" - cell $eq $eq$ls180.v:6410$1905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6410$1905_Y - end - attribute \src "ls180.v:6411.103-6411.147" - cell $eq $eq$ls180.v:6411$1909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6411$1909_Y - end - attribute \src "ls180.v:6413.100-6413.144" - cell $eq $eq$ls180.v:6413$1912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6413$1912_Y - end - attribute \src "ls180.v:6414.103-6414.147" - cell $eq $eq$ls180.v:6414$1916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6414$1916_Y - end - attribute \src "ls180.v:6416.100-6416.144" - cell $eq $eq$ls180.v:6416$1919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6416$1919_Y - end - attribute \src "ls180.v:6417.103-6417.147" - cell $eq $eq$ls180.v:6417$1923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6417$1923_Y - end - attribute \src "ls180.v:6419.102-6419.146" - cell $eq $eq$ls180.v:6419$1926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6419$1926_Y - end - attribute \src "ls180.v:6420.105-6420.149" - cell $eq $eq$ls180.v:6420$1930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6420$1930_Y - end - attribute \src "ls180.v:6422.102-6422.146" - cell $eq $eq$ls180.v:6422$1933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6422$1933_Y - end - attribute \src "ls180.v:6423.105-6423.149" - cell $eq $eq$ls180.v:6423$1937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6423$1937_Y - end - attribute \src "ls180.v:6425.102-6425.147" - cell $eq $eq$ls180.v:6425$1940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6425$1940_Y - end - attribute \src "ls180.v:6426.105-6426.150" - cell $eq $eq$ls180.v:6426$1944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6426$1944_Y - end - attribute \src "ls180.v:6428.102-6428.147" - cell $eq $eq$ls180.v:6428$1947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6428$1947_Y - end - attribute \src "ls180.v:6429.105-6429.150" - cell $eq $eq$ls180.v:6429$1951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6429$1951_Y - end - attribute \src "ls180.v:6431.102-6431.147" - cell $eq $eq$ls180.v:6431$1954 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6431$1954_Y - end - attribute \src "ls180.v:6432.105-6432.150" - cell $eq $eq$ls180.v:6432$1958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6432$1958_Y - end - attribute \src "ls180.v:6434.99-6434.144" - cell $eq $eq$ls180.v:6434$1961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6434$1961_Y - end - attribute \src "ls180.v:6435.102-6435.147" - cell $eq $eq$ls180.v:6435$1965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6435$1965_Y - end - attribute \src "ls180.v:6437.100-6437.145" - cell $eq $eq$ls180.v:6437$1968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6437$1968_Y - end - attribute \src "ls180.v:6438.103-6438.148" - cell $eq $eq$ls180.v:6438$1972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6438$1972_Y - end - attribute \src "ls180.v:6440.102-6440.147" - cell $eq $eq$ls180.v:6440$1975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6440$1975_Y - end - attribute \src "ls180.v:6441.105-6441.150" - cell $eq $eq$ls180.v:6441$1979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6441$1979_Y - end - attribute \src "ls180.v:6443.102-6443.147" - cell $eq $eq$ls180.v:6443$1982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6443$1982_Y - end - attribute \src "ls180.v:6444.105-6444.150" - cell $eq $eq$ls180.v:6444$1986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6444$1986_Y - end - attribute \src "ls180.v:6446.102-6446.147" - cell $eq $eq$ls180.v:6446$1989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6446$1989_Y - end - attribute \src "ls180.v:6447.105-6447.150" - cell $eq $eq$ls180.v:6447$1993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6447$1993_Y - end - attribute \src "ls180.v:6449.102-6449.147" - cell $eq $eq$ls180.v:6449$1996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6449$1996_Y - end - attribute \src "ls180.v:6450.105-6450.150" - cell $eq $eq$ls180.v:6450$2000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6450$2000_Y - end - attribute \src "ls180.v:6472.32-6472.78" - cell $eq $eq$ls180.v:6472$2002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [13:8] - connect \B 4'1101 - connect \Y $eq$ls180.v:6472$2002_Y - end - attribute \src "ls180.v:6474.102-6474.146" - cell $eq $eq$ls180.v:6474$2004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6474$2004_Y - end - attribute \src "ls180.v:6475.105-6475.149" - cell $eq $eq$ls180.v:6475$2008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6475$2008_Y - end - attribute \src "ls180.v:6477.107-6477.151" - cell $eq $eq$ls180.v:6477$2011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6477$2011_Y - end - attribute \src "ls180.v:6478.110-6478.154" - cell $eq $eq$ls180.v:6478$2015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6478$2015_Y - end - attribute \src "ls180.v:6480.107-6480.151" - cell $eq $eq$ls180.v:6480$2018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6480$2018_Y - end - attribute \src "ls180.v:6481.110-6481.154" - cell $eq $eq$ls180.v:6481$2022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6481$2022_Y - end - attribute \src "ls180.v:6483.100-6483.144" - cell $eq $eq$ls180.v:6483$2025 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6483$2025_Y - end - attribute \src "ls180.v:6484.103-6484.147" - cell $eq $eq$ls180.v:6484$2029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6484$2029_Y - end - attribute \src "ls180.v:6489.32-6489.77" - cell $eq $eq$ls180.v:6489$2031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [13:8] - connect \B 2'11 - connect \Y $eq$ls180.v:6489$2031_Y - end - attribute \src "ls180.v:6491.104-6491.148" - cell $eq $eq$ls180.v:6491$2033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6491$2033_Y - end - attribute \src "ls180.v:6492.107-6492.151" - cell $eq $eq$ls180.v:6492$2037 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6492$2037_Y - end - attribute \src "ls180.v:6494.108-6494.152" - cell $eq $eq$ls180.v:6494$2040 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6494$2040_Y - end - attribute \src "ls180.v:6495.111-6495.155" - cell $eq $eq$ls180.v:6495$2044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6495$2044_Y - end - attribute \src "ls180.v:6497.98-6497.142" - cell $eq $eq$ls180.v:6497$2047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6497$2047_Y - end - attribute \src "ls180.v:6498.101-6498.145" - cell $eq $eq$ls180.v:6498$2051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6498$2051_Y - end - attribute \src "ls180.v:6500.108-6500.152" - cell $eq $eq$ls180.v:6500$2054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6500$2054_Y - end - attribute \src "ls180.v:6501.111-6501.155" - cell $eq $eq$ls180.v:6501$2058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6501$2058_Y - end - attribute \src "ls180.v:6503.108-6503.152" - cell $eq $eq$ls180.v:6503$2061 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6503$2061_Y - end - attribute \src "ls180.v:6504.111-6504.155" - cell $eq $eq$ls180.v:6504$2065 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6504$2065_Y - end - attribute \src "ls180.v:6506.109-6506.153" - cell $eq $eq$ls180.v:6506$2068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6506$2068_Y - end - attribute \src "ls180.v:6507.112-6507.156" - cell $eq $eq$ls180.v:6507$2072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6507$2072_Y - end - attribute \src "ls180.v:6509.107-6509.151" - cell $eq $eq$ls180.v:6509$2075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6509$2075_Y - end - attribute \src "ls180.v:6510.110-6510.154" - cell $eq $eq$ls180.v:6510$2079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6510$2079_Y - end - attribute \src "ls180.v:6512.107-6512.151" - cell $eq $eq$ls180.v:6512$2082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6512$2082_Y - end - attribute \src "ls180.v:6513.110-6513.154" - cell $eq $eq$ls180.v:6513$2086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6513$2086_Y - end - attribute \src "ls180.v:6515.107-6515.151" - cell $eq $eq$ls180.v:6515$2089 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6515$2089_Y - end - attribute \src "ls180.v:6516.110-6516.154" - cell $eq $eq$ls180.v:6516$2093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6516$2093_Y - end - attribute \src "ls180.v:6518.107-6518.151" - cell $eq $eq$ls180.v:6518$2096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6518$2096_Y - end - attribute \src "ls180.v:6519.110-6519.154" - cell $eq $eq$ls180.v:6519$2100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6519$2100_Y - end - attribute \src "ls180.v:6534.33-6534.79" - cell $eq $eq$ls180.v:6534$2102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [13:8] - connect \B 4'1000 - connect \Y $eq$ls180.v:6534$2102_Y - end - attribute \src "ls180.v:6536.102-6536.147" - cell $eq $eq$ls180.v:6536$2104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6536$2104_Y - end - attribute \src "ls180.v:6537.105-6537.150" - cell $eq $eq$ls180.v:6537$2108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6537$2108_Y - end - attribute \src "ls180.v:6539.102-6539.147" - cell $eq $eq$ls180.v:6539$2111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6539$2111_Y - end - attribute \src "ls180.v:6540.105-6540.150" - cell $eq $eq$ls180.v:6540$2115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6540$2115_Y - end - attribute \src "ls180.v:6542.100-6542.145" - cell $eq $eq$ls180.v:6542$2118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6542$2118_Y - end - attribute \src "ls180.v:6543.103-6543.148" - cell $eq $eq$ls180.v:6543$2122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6543$2122_Y - end - attribute \src "ls180.v:6545.99-6545.144" - cell $eq $eq$ls180.v:6545$2125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6545$2125_Y - end - attribute \src "ls180.v:6546.102-6546.147" - cell $eq $eq$ls180.v:6546$2129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6546$2129_Y - end - attribute \src "ls180.v:6548.98-6548.143" - cell $eq $eq$ls180.v:6548$2132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6548$2132_Y - end - attribute \src "ls180.v:6549.101-6549.146" - cell $eq $eq$ls180.v:6549$2136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6549$2136_Y - end - attribute \src "ls180.v:6551.97-6551.142" - cell $eq $eq$ls180.v:6551$2139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6551$2139_Y - end - attribute \src "ls180.v:6552.100-6552.145" - cell $eq $eq$ls180.v:6552$2143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6552$2143_Y - end - attribute \src "ls180.v:6554.103-6554.148" - cell $eq $eq$ls180.v:6554$2146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6554$2146_Y - end - attribute \src "ls180.v:6555.106-6555.151" - cell $eq $eq$ls180.v:6555$2150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6555$2150_Y - end - attribute \src "ls180.v:6574.33-6574.79" - cell $eq $eq$ls180.v:6574$2153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [13:8] - connect \B 4'1001 - connect \Y $eq$ls180.v:6574$2153_Y - end - attribute \src "ls180.v:6576.102-6576.147" - cell $eq $eq$ls180.v:6576$2155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6576$2155_Y - end - attribute \src "ls180.v:6577.105-6577.150" - cell $eq $eq$ls180.v:6577$2159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6577$2159_Y - end - attribute \src "ls180.v:6579.102-6579.147" - cell $eq $eq$ls180.v:6579$2162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6579$2162_Y - end - attribute \src "ls180.v:6580.105-6580.150" - cell $eq $eq$ls180.v:6580$2166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6580$2166_Y - end - attribute \src "ls180.v:6582.100-6582.145" - cell $eq $eq$ls180.v:6582$2169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6582$2169_Y - end - attribute \src "ls180.v:6583.103-6583.148" - cell $eq $eq$ls180.v:6583$2173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6583$2173_Y - end - attribute \src "ls180.v:6585.99-6585.144" - cell $eq $eq$ls180.v:6585$2176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6585$2176_Y - end - attribute \src "ls180.v:6586.102-6586.147" - cell $eq $eq$ls180.v:6586$2180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6586$2180_Y - end - attribute \src "ls180.v:6588.98-6588.143" - cell $eq $eq$ls180.v:6588$2183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6588$2183_Y - end - attribute \src "ls180.v:6589.101-6589.146" - cell $eq $eq$ls180.v:6589$2187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6589$2187_Y - end - attribute \src "ls180.v:6591.97-6591.142" - cell $eq $eq$ls180.v:6591$2190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6591$2190_Y - end - attribute \src "ls180.v:6592.100-6592.145" - cell $eq $eq$ls180.v:6592$2194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6592$2194_Y - end - attribute \src "ls180.v:6594.103-6594.148" - cell $eq $eq$ls180.v:6594$2197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6594$2197_Y - end - attribute \src "ls180.v:6595.106-6595.151" - cell $eq $eq$ls180.v:6595$2201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6595$2201_Y - end - attribute \src "ls180.v:6597.106-6597.151" - cell $eq $eq$ls180.v:6597$2204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6597$2204_Y - end - attribute \src "ls180.v:6598.109-6598.154" - cell $eq $eq$ls180.v:6598$2208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6598$2208_Y - end - attribute \src "ls180.v:6600.106-6600.151" - cell $eq $eq$ls180.v:6600$2211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6600$2211_Y - end - attribute \src "ls180.v:6601.109-6601.154" - cell $eq $eq$ls180.v:6601$2215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6601$2215_Y - end - attribute \src "ls180.v:6622.33-6622.79" - cell $eq $eq$ls180.v:6622$2218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [13:8] - connect \B 2'10 - connect \Y $eq$ls180.v:6622$2218_Y - end - attribute \src "ls180.v:6624.99-6624.144" - cell $eq $eq$ls180.v:6624$2220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6624$2220_Y - end - attribute \src "ls180.v:6625.102-6625.147" - cell $eq $eq$ls180.v:6625$2224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6625$2224_Y - end - attribute \src "ls180.v:6627.99-6627.144" - cell $eq $eq$ls180.v:6627$2227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6627$2227_Y - end - attribute \src "ls180.v:6628.102-6628.147" - cell $eq $eq$ls180.v:6628$2231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6628$2231_Y - end - attribute \src "ls180.v:6630.99-6630.144" - cell $eq $eq$ls180.v:6630$2234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6630$2234_Y - end - attribute \src "ls180.v:6631.102-6631.147" - cell $eq $eq$ls180.v:6631$2238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6631$2238_Y - end - attribute \src "ls180.v:6633.99-6633.144" - cell $eq $eq$ls180.v:6633$2241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6633$2241_Y - end - attribute \src "ls180.v:6634.102-6634.147" - cell $eq $eq$ls180.v:6634$2245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6634$2245_Y - end - attribute \src "ls180.v:6636.101-6636.146" - cell $eq $eq$ls180.v:6636$2248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6636$2248_Y - end - attribute \src "ls180.v:6637.104-6637.149" - cell $eq $eq$ls180.v:6637$2252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6637$2252_Y - end - attribute \src "ls180.v:6639.101-6639.146" - cell $eq $eq$ls180.v:6639$2255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6639$2255_Y - end - attribute \src "ls180.v:6640.104-6640.149" - cell $eq $eq$ls180.v:6640$2259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6640$2259_Y - end - attribute \src "ls180.v:6642.101-6642.146" - cell $eq $eq$ls180.v:6642$2262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6642$2262_Y - end - attribute \src "ls180.v:6643.104-6643.149" - cell $eq $eq$ls180.v:6643$2266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6643$2266_Y - end - attribute \src "ls180.v:6645.101-6645.146" - cell $eq $eq$ls180.v:6645$2269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6645$2269_Y - end - attribute \src "ls180.v:6646.104-6646.149" - cell $eq $eq$ls180.v:6646$2273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6646$2273_Y - end - attribute \src "ls180.v:6648.97-6648.142" - cell $eq $eq$ls180.v:6648$2276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6648$2276_Y - end - attribute \src "ls180.v:6649.100-6649.145" - cell $eq $eq$ls180.v:6649$2280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6649$2280_Y - end - attribute \src "ls180.v:6651.107-6651.152" - cell $eq $eq$ls180.v:6651$2283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6651$2283_Y - end - attribute \src "ls180.v:6652.110-6652.155" - cell $eq $eq$ls180.v:6652$2287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6652$2287_Y - end - attribute \src "ls180.v:6654.100-6654.146" - cell $eq $eq$ls180.v:6654$2290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6654$2290_Y - end - attribute \src "ls180.v:6655.103-6655.149" - cell $eq $eq$ls180.v:6655$2294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6655$2294_Y - end - attribute \src "ls180.v:6657.100-6657.146" - cell $eq $eq$ls180.v:6657$2297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6657$2297_Y - end - attribute \src "ls180.v:6658.103-6658.149" - cell $eq $eq$ls180.v:6658$2301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6658$2301_Y - end - attribute \src "ls180.v:6660.100-6660.146" - cell $eq $eq$ls180.v:6660$2304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6660$2304_Y - end - attribute \src "ls180.v:6661.103-6661.149" - cell $eq $eq$ls180.v:6661$2308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6661$2308_Y - end - attribute \src "ls180.v:6663.100-6663.146" - cell $eq $eq$ls180.v:6663$2311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6663$2311_Y - end - attribute \src "ls180.v:6664.103-6664.149" - cell $eq $eq$ls180.v:6664$2315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6664$2315_Y - end - attribute \src "ls180.v:6666.112-6666.158" - cell $eq $eq$ls180.v:6666$2318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6666$2318_Y - end - attribute \src "ls180.v:6667.115-6667.161" - cell $eq $eq$ls180.v:6667$2322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6667$2322_Y - end - attribute \src "ls180.v:6669.113-6669.159" - cell $eq $eq$ls180.v:6669$2325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6669$2325_Y - end - attribute \src "ls180.v:6670.116-6670.162" - cell $eq $eq$ls180.v:6670$2329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6670$2329_Y - end - attribute \src "ls180.v:6672.104-6672.150" - cell $eq $eq$ls180.v:6672$2332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6672$2332_Y - end - attribute \src "ls180.v:6673.107-6673.153" - cell $eq $eq$ls180.v:6673$2336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6673$2336_Y - end - attribute \src "ls180.v:6690.33-6690.79" - cell $eq $eq$ls180.v:6690$2338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [13:8] - connect \B 3'101 - connect \Y $eq$ls180.v:6690$2338_Y - end - attribute \src "ls180.v:6692.90-6692.135" - cell $eq $eq$ls180.v:6692$2340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6692$2340_Y - end - attribute \src "ls180.v:6693.93-6693.138" - cell $eq $eq$ls180.v:6693$2344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6693$2344_Y - end - attribute \src "ls180.v:6695.100-6695.145" - cell $eq $eq$ls180.v:6695$2347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6695$2347_Y - end - attribute \src "ls180.v:6696.103-6696.148" - cell $eq $eq$ls180.v:6696$2351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6696$2351_Y - end - attribute \src "ls180.v:6698.101-6698.146" - cell $eq $eq$ls180.v:6698$2354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6698$2354_Y - end - attribute \src "ls180.v:6699.104-6699.149" - cell $eq $eq$ls180.v:6699$2358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6699$2358_Y - end - attribute \src "ls180.v:6701.105-6701.150" - cell $eq $eq$ls180.v:6701$2361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6701$2361_Y - end - attribute \src "ls180.v:6702.108-6702.153" - cell $eq $eq$ls180.v:6702$2365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6702$2365_Y - end - attribute \src "ls180.v:6704.106-6704.151" - cell $eq $eq$ls180.v:6704$2368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6704$2368_Y - end - attribute \src "ls180.v:6705.109-6705.154" - cell $eq $eq$ls180.v:6705$2372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6705$2372_Y - end - attribute \src "ls180.v:6707.104-6707.149" - cell $eq $eq$ls180.v:6707$2375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6707$2375_Y - end - attribute \src "ls180.v:6708.107-6708.152" - cell $eq $eq$ls180.v:6708$2379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6708$2379_Y - end - attribute \src "ls180.v:6710.101-6710.146" - cell $eq $eq$ls180.v:6710$2382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6710$2382_Y - end - attribute \src "ls180.v:6711.104-6711.149" - cell $eq $eq$ls180.v:6711$2386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6711$2386_Y - end - attribute \src "ls180.v:6713.100-6713.145" - cell $eq $eq$ls180.v:6713$2389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6713$2389_Y - end - attribute \src "ls180.v:6714.103-6714.148" - cell $eq $eq$ls180.v:6714$2393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6714$2393_Y - end - attribute \src "ls180.v:6724.33-6724.79" - cell $eq $eq$ls180.v:6724$2395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [13:8] - connect \B 3'100 - connect \Y $eq$ls180.v:6724$2395_Y - end - attribute \src "ls180.v:6726.106-6726.151" - cell $eq $eq$ls180.v:6726$2397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6726$2397_Y - end - attribute \src "ls180.v:6727.109-6727.154" - cell $eq $eq$ls180.v:6727$2401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6727$2401_Y - end - attribute \src "ls180.v:6729.106-6729.151" - cell $eq $eq$ls180.v:6729$2404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6729$2404_Y - end - attribute \src "ls180.v:6730.109-6730.154" - cell $eq $eq$ls180.v:6730$2408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6730$2408_Y - end - attribute \src "ls180.v:6732.106-6732.151" - cell $eq $eq$ls180.v:6732$2411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6732$2411_Y - end - attribute \src "ls180.v:6733.109-6733.154" - cell $eq $eq$ls180.v:6733$2415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6733$2415_Y - end - attribute \src "ls180.v:6735.106-6735.151" - cell $eq $eq$ls180.v:6735$2418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6735$2418_Y - end - attribute \src "ls180.v:6736.109-6736.154" - cell $eq $eq$ls180.v:6736$2422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6736$2422_Y - end - attribute \src "ls180.v:7117.41-7117.81" - cell $eq $eq$ls180.v:7117$2459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:7117$2459_Y - end - attribute \src "ls180.v:7117.144-7117.177" - cell $eq $eq$ls180.v:7117$2460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7117$2460_Y - end - attribute \src "ls180.v:7117.219-7117.252" - cell $eq $eq$ls180.v:7117$2463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7117$2463_Y - end - attribute \src "ls180.v:7117.294-7117.327" - cell $eq $eq$ls180.v:7117$2466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7117$2466_Y - end - attribute \src "ls180.v:7141.41-7141.81" - cell $eq $eq$ls180.v:7141$2475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:7141$2475_Y - end - attribute \src "ls180.v:7141.144-7141.177" - cell $eq $eq$ls180.v:7141$2476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7141$2476_Y - end - attribute \src "ls180.v:7141.219-7141.252" - cell $eq $eq$ls180.v:7141$2479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7141$2479_Y - end - attribute \src "ls180.v:7141.294-7141.327" - cell $eq $eq$ls180.v:7141$2482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7141$2482_Y - end - attribute \src "ls180.v:7165.41-7165.81" - cell $eq $eq$ls180.v:7165$2491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:7165$2491_Y - end - attribute \src "ls180.v:7165.144-7165.177" - cell $eq $eq$ls180.v:7165$2492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7165$2492_Y - end - attribute \src "ls180.v:7165.219-7165.252" - cell $eq $eq$ls180.v:7165$2495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7165$2495_Y - end - attribute \src "ls180.v:7165.294-7165.327" - cell $eq $eq$ls180.v:7165$2498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7165$2498_Y - end - attribute \src "ls180.v:7189.41-7189.81" - cell $eq $eq$ls180.v:7189$2507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:7189$2507_Y - end - attribute \src "ls180.v:7189.144-7189.177" - cell $eq $eq$ls180.v:7189$2508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7189$2508_Y - end - attribute \src "ls180.v:7189.219-7189.252" - cell $eq $eq$ls180.v:7189$2511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7189$2511_Y - end - attribute \src "ls180.v:7189.294-7189.327" - cell $eq $eq$ls180.v:7189$2514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7189$2514_Y - end - attribute \src "ls180.v:7773.8-7773.38" - cell $eq $eq$ls180.v:7773$2608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_value - connect \B 1'0 - connect \Y $eq$ls180.v:7773$2608_Y - end - attribute \src "ls180.v:7820.8-7820.42" - cell $eq $eq$ls180.v:7820$2628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_postponer_count - connect \B 1'0 - connect \Y $eq$ls180.v:7820$2628_Y - end - attribute \src "ls180.v:7840.38-7840.74" - cell $eq $eq$ls180.v:7840$2631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 1'0 - connect \Y $eq$ls180.v:7840$2631_Y - end - attribute \src "ls180.v:7847.7-7847.43" - cell $eq $eq$ls180.v:7847$2633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 2'10 - connect \Y $eq$ls180.v:7847$2633_Y - end - attribute \src "ls180.v:7854.7-7854.43" - cell $eq $eq$ls180.v:7854$2634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 4'1000 - connect \Y $eq$ls180.v:7854$2634_Y - end - attribute \src "ls180.v:7862.7-7862.43" - cell $eq $eq$ls180.v:7862$2635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 4'1000 - connect \Y $eq$ls180.v:7862$2635_Y - end - attribute \src "ls180.v:7914.9-7914.54" - cell $eq $eq$ls180.v:7914$2653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7914$2653_Y - end - attribute \src "ls180.v:7960.9-7960.54" - cell $eq $eq$ls180.v:7960$2669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7960$2669_Y - end - attribute \src "ls180.v:8006.9-8006.54" - cell $eq $eq$ls180.v:8006$2685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:8006$2685_Y - end - attribute \src "ls180.v:8052.9-8052.54" - cell $eq $eq$ls180.v:8052$2701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:8052$2701_Y - end - attribute \src "ls180.v:8202.9-8202.41" - cell $eq $eq$ls180.v:8202$2713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:8202$2713_Y - end - attribute \src "ls180.v:8217.9-8217.41" - cell $eq $eq$ls180.v:8217$2716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_twtrcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:8217$2716_Y - end - attribute \src "ls180.v:8223.49-8223.82" - cell $eq $eq$ls180.v:8223$2717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8223$2717_Y - end - attribute \src "ls180.v:8223.131-8223.164" - cell $eq $eq$ls180.v:8223$2720 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8223$2720_Y - end - attribute \src "ls180.v:8223.213-8223.246" - cell $eq $eq$ls180.v:8223$2723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8223$2723_Y - end - attribute \src "ls180.v:8223.295-8223.328" - cell $eq $eq$ls180.v:8223$2726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8223$2726_Y - end - attribute \src "ls180.v:8224.50-8224.83" - cell $eq $eq$ls180.v:8224$2729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8224$2729_Y - end - attribute \src "ls180.v:8224.132-8224.165" - cell $eq $eq$ls180.v:8224$2732 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8224$2732_Y - end - attribute \src "ls180.v:8224.214-8224.247" - cell $eq $eq$ls180.v:8224$2735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8224$2735_Y - end - attribute \src "ls180.v:8224.296-8224.329" - cell $eq $eq$ls180.v:8224$2738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8224$2738_Y - end - attribute \src "ls180.v:8259.9-8259.42" - cell $eq $eq$ls180.v:8259$2750 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_bitcount - connect \B 4'1000 - connect \Y $eq$ls180.v:8259$2750_Y - end - attribute \src "ls180.v:8262.10-8262.43" - cell $eq $eq$ls180.v:8262$2751 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_bitcount - connect \B 4'1001 - connect \Y $eq$ls180.v:8262$2751_Y - end - attribute \src "ls180.v:8288.9-8288.42" - cell $eq $eq$ls180.v:8288$2757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_bitcount - connect \B 1'0 - connect \Y $eq$ls180.v:8288$2757_Y - end - attribute \src "ls180.v:8293.10-8293.43" - cell $eq $eq$ls180.v:8293$2758 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_bitcount - connect \B 4'1001 - connect \Y $eq$ls180.v:8293$2758_Y - end - attribute \src "ls180.v:8500.9-8500.53" - cell $eq $eq$ls180.v:8500$2807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:8500$2807_Y - end - attribute \src "ls180.v:8581.9-8581.54" - cell $eq $eq$ls180.v:8581$2819 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:8581$2819_Y - end - attribute \src "ls180.v:8660.9-8660.55" - cell $eq $eq$ls180.v:8660$2831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $eq$ls180.v:8660$2831_Y - end - attribute \src "ls180.v:8883.9-8883.49" - cell $eq $eq$ls180.v:8883$2864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:8883$2864_Y - end - attribute \src "ls180.v:8459.8-8459.54" - cell $ge $ge$ls180.v:8459$2799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm0_counter - connect \B $sub$ls180.v:8459$2798_Y - connect \Y $ge$ls180.v:8459$2799_Y - end - attribute \src "ls180.v:8473.8-8473.54" - cell $ge $ge$ls180.v:8473$2803 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm1_counter - connect \B $sub$ls180.v:8473$2802_Y - connect \Y $ge$ls180.v:8473$2803_Y - end - attribute \src "ls180.v:5342.47-5342.83" - cell $gt $gt$ls180.v:5342$1064 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $gt$ls180.v:5342$1064_Y - end - attribute \src "ls180.v:5348.7-5348.43" - cell $lt $lt$ls180.v:5348$1067 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 4'1000 - connect \Y $lt$ls180.v:5348$1067_Y - end - attribute \src "ls180.v:8454.8-8454.43" - cell $lt $lt$ls180.v:8454$2797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm0_counter - connect \B \main_pwm0_width - connect \Y $lt$ls180.v:8454$2797_Y - end - attribute \src "ls180.v:8468.8-8468.43" - cell $lt $lt$ls180.v:8468$2801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm1_counter - connect \B \main_pwm1_width - connect \Y $lt$ls180.v:8468$2801_Y - end - attribute \src "ls180.v:10373.33-10373.36" - cell $memrd $memrd$\mem$ls180.v:10373$2918 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr - connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:10373$2918_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10401.27-10401.32" - cell $memrd $memrd$\mem_1$ls180.v:10401$2944 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr_1 - connect \CLK 1'x - connect \DATA $memrd$\mem_1$ls180.v:10401$2944_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10429.27-10429.32" - cell $memrd $memrd$\mem_2$ls180.v:10429$2970 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr_2 - connect \CLK 1'x - connect \DATA $memrd$\mem_2$ls180.v:10429$2970_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10457.27-10457.32" - cell $memrd $memrd$\mem_3$ls180.v:10457$2996 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr_3 - connect \CLK 1'x - connect \DATA $memrd$\mem_3$ls180.v:10457$2996_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10485.27-10485.32" - cell $memrd $memrd$\mem_4$ls180.v:10485$3022 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr_4 - connect \CLK 1'x - connect \DATA $memrd$\mem_4$ls180.v:10485$3022_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10496.12-10496.19" - cell $memrd $memrd$\storage$ls180.v:10496$3027 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10496$3027_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10503.68-10503.75" - cell $memrd $memrd$\storage$ls180.v:10503$3029 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10503$3029_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10510.14-10510.23" - cell $memrd $memrd$\storage_1$ls180.v:10510$3034 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10510$3034_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10517.68-10517.77" - cell $memrd $memrd$\storage_1$ls180.v:10517$3036 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10517$3036_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10524.14-10524.23" - cell $memrd $memrd$\storage_2$ls180.v:10524$3041 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10524$3041_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10531.68-10531.77" - cell $memrd $memrd$\storage_2$ls180.v:10531$3043 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10531$3043_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10538.14-10538.23" - cell $memrd $memrd$\storage_3$ls180.v:10538$3048 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10538$3048_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10545.68-10545.77" - cell $memrd $memrd$\storage_3$ls180.v:10545$3050 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10545$3050_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10553.14-10553.23" - cell $memrd $memrd$\storage_4$ls180.v:10553$3055 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_tx_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10553$3055_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10558.15-10558.24" - cell $memrd $memrd$\storage_4$ls180.v:10558$3057 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_tx_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10558$3057_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10570.14-10570.23" - cell $memrd $memrd$\storage_5$ls180.v:10570$3062 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_rx_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10570$3062_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10575.15-10575.24" - cell $memrd $memrd$\storage_5$ls180.v:10575$3064 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_rx_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10575$3064_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10586.14-10586.23" - cell $memrd $memrd$\storage_6$ls180.v:10586$3069 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdblock2mem_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10586$3069_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10593.45-10593.54" - cell $memrd $memrd$\storage_6$ls180.v:10593$3071 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdblock2mem_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10593$3071_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10600.14-10600.23" - cell $memrd $memrd$\storage_7$ls180.v:10600$3076 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdmem2block_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10600$3076_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10607.45-10607.54" - cell $memrd $memrd$\storage_7$ls180.v:10607$3078 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdmem2block_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10607$3078_DATA - connect \EN 1'x - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3080 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3080 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10355$1_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10355$1_DATA - connect \EN $memwr$\mem$ls180.v:10355$1_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3081 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3081 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10357$2_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10357$2_DATA - connect \EN $memwr$\mem$ls180.v:10357$2_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3082 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3082 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10359$3_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10359$3_DATA - connect \EN $memwr$\mem$ls180.v:10359$3_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3083 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3083 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10361$4_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10361$4_DATA - connect \EN $memwr$\mem$ls180.v:10361$4_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3084 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3084 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10363$5_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10363$5_DATA - connect \EN $memwr$\mem$ls180.v:10363$5_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3085 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3085 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10365$6_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10365$6_DATA - connect \EN $memwr$\mem$ls180.v:10365$6_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3086 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3086 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10367$7_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10367$7_DATA - connect \EN $memwr$\mem$ls180.v:10367$7_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3087 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3087 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10369$8_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10369$8_DATA - connect \EN $memwr$\mem$ls180.v:10369$8_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3088 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3088 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10383$9_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10383$9_DATA - connect \EN $memwr$\mem_1$ls180.v:10383$9_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3089 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3089 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10385$10_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10385$10_DATA - connect \EN $memwr$\mem_1$ls180.v:10385$10_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3090 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3090 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10387$11_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10387$11_DATA - connect \EN $memwr$\mem_1$ls180.v:10387$11_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3091 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3091 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10389$12_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10389$12_DATA - connect \EN $memwr$\mem_1$ls180.v:10389$12_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3092 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3092 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10391$13_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10391$13_DATA - connect \EN $memwr$\mem_1$ls180.v:10391$13_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3093 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3093 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10393$14_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10393$14_DATA - connect \EN $memwr$\mem_1$ls180.v:10393$14_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3094 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3094 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10395$15_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10395$15_DATA - connect \EN $memwr$\mem_1$ls180.v:10395$15_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3095 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3095 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10397$16_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10397$16_DATA - connect \EN $memwr$\mem_1$ls180.v:10397$16_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3096 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3096 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10411$17_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10411$17_DATA - connect \EN $memwr$\mem_2$ls180.v:10411$17_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3097 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3097 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10413$18_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10413$18_DATA - connect \EN $memwr$\mem_2$ls180.v:10413$18_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3098 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3098 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10415$19_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10415$19_DATA - connect \EN $memwr$\mem_2$ls180.v:10415$19_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3099 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3099 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10417$20_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10417$20_DATA - connect \EN $memwr$\mem_2$ls180.v:10417$20_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3100 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3100 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10419$21_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10419$21_DATA - connect \EN $memwr$\mem_2$ls180.v:10419$21_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3101 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3101 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10421$22_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10421$22_DATA - connect \EN $memwr$\mem_2$ls180.v:10421$22_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3102 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3102 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10423$23_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10423$23_DATA - connect \EN $memwr$\mem_2$ls180.v:10423$23_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3103 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3103 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10425$24_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10425$24_DATA - connect \EN $memwr$\mem_2$ls180.v:10425$24_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3104 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3104 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10439$25_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10439$25_DATA - connect \EN $memwr$\mem_3$ls180.v:10439$25_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3105 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3105 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10441$26_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10441$26_DATA - connect \EN $memwr$\mem_3$ls180.v:10441$26_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3106 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3106 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10443$27_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10443$27_DATA - connect \EN $memwr$\mem_3$ls180.v:10443$27_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3107 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3107 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10445$28_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10445$28_DATA - connect \EN $memwr$\mem_3$ls180.v:10445$28_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3108 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3108 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10447$29_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10447$29_DATA - connect \EN $memwr$\mem_3$ls180.v:10447$29_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3109 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3109 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10449$30_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10449$30_DATA - connect \EN $memwr$\mem_3$ls180.v:10449$30_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3110 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3110 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10451$31_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10451$31_DATA - connect \EN $memwr$\mem_3$ls180.v:10451$31_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3111 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3111 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10453$32_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10453$32_DATA - connect \EN $memwr$\mem_3$ls180.v:10453$32_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3112 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3112 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10467$33_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10467$33_DATA - connect \EN $memwr$\mem_4$ls180.v:10467$33_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3113 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3113 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10469$34_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10469$34_DATA - connect \EN $memwr$\mem_4$ls180.v:10469$34_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3114 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3114 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10471$35_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10471$35_DATA - connect \EN $memwr$\mem_4$ls180.v:10471$35_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3115 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3115 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10473$36_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10473$36_DATA - connect \EN $memwr$\mem_4$ls180.v:10473$36_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3116 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3116 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10475$37_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10475$37_DATA - connect \EN $memwr$\mem_4$ls180.v:10475$37_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3117 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3117 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10477$38_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10477$38_DATA - connect \EN $memwr$\mem_4$ls180.v:10477$38_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3118 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3118 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10479$39_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10479$39_DATA - connect \EN $memwr$\mem_4$ls180.v:10479$39_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3119 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3119 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10481$40_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10481$40_DATA - connect \EN $memwr$\mem_4$ls180.v:10481$40_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage$ls180.v:0$3120 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \PRIORITY 3120 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage$ls180.v:10495$41_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage$ls180.v:10495$41_DATA - connect \EN $memwr$\storage$ls180.v:10495$41_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_1$ls180.v:0$3121 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \PRIORITY 3121 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_1$ls180.v:10509$42_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_1$ls180.v:10509$42_DATA - connect \EN $memwr$\storage_1$ls180.v:10509$42_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_2$ls180.v:0$3122 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \PRIORITY 3122 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_2$ls180.v:10523$43_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_2$ls180.v:10523$43_DATA - connect \EN $memwr$\storage_2$ls180.v:10523$43_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_3$ls180.v:0$3123 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \PRIORITY 3123 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_3$ls180.v:10537$44_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_3$ls180.v:10537$44_DATA - connect \EN $memwr$\storage_3$ls180.v:10537$44_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_4$ls180.v:0$3124 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \PRIORITY 3124 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_4$ls180.v:10552$45_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_4$ls180.v:10552$45_DATA - connect \EN $memwr$\storage_4$ls180.v:10552$45_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_5$ls180.v:0$3125 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \PRIORITY 3125 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_5$ls180.v:10569$46_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_5$ls180.v:10569$46_DATA - connect \EN $memwr$\storage_5$ls180.v:10569$46_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_6$ls180.v:0$3126 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \PRIORITY 3126 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_6$ls180.v:10585$47_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_6$ls180.v:10585$47_DATA - connect \EN $memwr$\storage_6$ls180.v:10585$47_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_7$ls180.v:0$3127 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \PRIORITY 3127 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_7$ls180.v:10599$48_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_7$ls180.v:10599$48_DATA - connect \EN $memwr$\storage_7$ls180.v:10599$48_EN - end - attribute \src "ls180.v:3089.41-3089.71" - cell $ne $ne$ls180.v:3089$108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_value - connect \B 1'0 - connect \Y $ne$ls180.v:3089$108_Y - end - attribute \src "ls180.v:3306.70-3306.104" - cell $ne $ne$ls180.v:3306$222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $ne$ls180.v:3306$222_Y - end - attribute \src "ls180.v:3367.8-3367.142" - cell $ne $ne$ls180.v:3367$241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3367$241_Y - end - attribute \src "ls180.v:3399.75-3399.133" - cell $ne $ne$ls180.v:3399$248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3399$248_Y - end - attribute \src "ls180.v:3400.75-3400.133" - cell $ne $ne$ls180.v:3400$249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3400$249_Y - end - attribute \src "ls180.v:3524.8-3524.142" - cell $ne $ne$ls180.v:3524$271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3524$271_Y - end - attribute \src "ls180.v:3556.75-3556.133" - cell $ne $ne$ls180.v:3556$278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3556$278_Y - end - attribute \src "ls180.v:3557.75-3557.133" - cell $ne $ne$ls180.v:3557$279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3557$279_Y - end - attribute \src "ls180.v:3681.8-3681.142" - cell $ne $ne$ls180.v:3681$301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3681$301_Y - end - attribute \src "ls180.v:3713.75-3713.133" - cell $ne $ne$ls180.v:3713$308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3713$308_Y - end - attribute \src "ls180.v:3714.75-3714.133" - cell $ne $ne$ls180.v:3714$309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3714$309_Y - end - attribute \src "ls180.v:3838.8-3838.142" - cell $ne $ne$ls180.v:3838$331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3838$331_Y - end - attribute \src "ls180.v:3870.75-3870.133" - cell $ne $ne$ls180.v:3870$338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3870$338_Y - end - attribute \src "ls180.v:3871.75-3871.133" - cell $ne $ne$ls180.v:3871$339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3871$339_Y - end - attribute \src "ls180.v:4363.47-4363.80" - cell $ne $ne$ls180.v:4363$737 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_level0 - connect \B 5'10000 - connect \Y $ne$ls180.v:4363$737_Y - end - attribute \src "ls180.v:4364.47-4364.79" - cell $ne $ne$ls180.v:4364$738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_level0 - connect \B 1'0 - connect \Y $ne$ls180.v:4364$738_Y - end - attribute \src "ls180.v:4393.47-4393.80" - cell $ne $ne$ls180.v:4393$748 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_level0 - connect \B 5'10000 - connect \Y $ne$ls180.v:4393$748_Y - end - attribute \src "ls180.v:4394.47-4394.79" - cell $ne $ne$ls180.v:4394$749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_level0 - connect \B 1'0 - connect \Y $ne$ls180.v:4394$749_Y - end - attribute \src "ls180.v:4874.32-4874.89" - cell $ne $ne$ls180.v:4874$831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 - connect \B 3'101 - connect \Y $ne$ls180.v:4874$831_Y - end - attribute \src "ls180.v:5521.10-5521.56" - cell $ne $ne$ls180.v:5521$1128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 2'10 - connect \Y $ne$ls180.v:5521$1128_Y - end - attribute \src "ls180.v:5626.51-5626.87" - cell $ne $ne$ls180.v:5626$1142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_level - connect \B 6'100000 - connect \Y $ne$ls180.v:5626$1142_Y - end - attribute \src "ls180.v:5627.51-5627.86" - cell $ne $ne$ls180.v:5627$1143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'0 - connect \Y $ne$ls180.v:5627$1143_Y - end - attribute \src "ls180.v:5846.51-5846.87" - cell $ne $ne$ls180.v:5846$1173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_level - connect \B 6'100000 - connect \Y $ne$ls180.v:5846$1173_Y - end - attribute \src "ls180.v:5847.51-5847.86" - cell $ne $ne$ls180.v:5847$1174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_level - connect \B 1'0 - connect \Y $ne$ls180.v:5847$1174_Y - end - attribute \src "ls180.v:5878.79-5878.119" - cell $ne $ne$ls180.v:5878$1177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_sel - connect \B 1'0 - connect \Y $ne$ls180.v:5878$1177_Y - end - attribute \src "ls180.v:7763.7-7763.52" - cell $ne $ne$ls180.v:7763$2603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_bus_errors - connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7763$2603_Y - end - attribute \src "ls180.v:7829.9-7829.43" - cell $ne $ne$ls180.v:7829$2629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $ne$ls180.v:7829$2629_Y - end - attribute \src "ls180.v:7865.8-7865.44" - cell $ne $ne$ls180.v:7865$2636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 1'0 - connect \Y $ne$ls180.v:7865$2636_Y - end - attribute \src "ls180.v:8803.9-8803.47" - cell $ne $ne$ls180.v:8803$2851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 4'1010 - connect \Y $ne$ls180.v:8803$2851_Y - end - attribute \src "ls180.v:2893.33-2893.73" - cell $not $not$ls180.v:2893$50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_converted_interface_cyc - connect \Y $not$ls180.v:2893$50_Y - end - attribute \src "ls180.v:2932.48-2932.69" - cell $not $not$ls180.v:2932$55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter0_skip - connect \Y $not$ls180.v:2932$55_Y - end - attribute \src "ls180.v:2933.48-2933.69" - cell $not $not$ls180.v:2933$56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter0_skip - connect \Y $not$ls180.v:2933$56_Y - end - attribute \src "ls180.v:2953.33-2953.73" - cell $not $not$ls180.v:2953$61 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_converted_interface_cyc - connect \Y $not$ls180.v:2953$61_Y - end - attribute \src "ls180.v:2992.48-2992.69" - cell $not $not$ls180.v:2992$66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter1_skip - connect \Y $not$ls180.v:2992$66_Y - end - attribute \src "ls180.v:2993.48-2993.69" - cell $not $not$ls180.v:2993$67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter1_skip - connect \Y $not$ls180.v:2993$67_Y - end - attribute \src "ls180.v:3013.36-3013.79" - cell $not $not$ls180.v:3013$72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_socbushandler_converted_interface_cyc - connect \Y $not$ls180.v:3013$72_Y - end - attribute \src "ls180.v:3052.27-3052.51" - cell $not $not$ls180.v:3052$77 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_socbushandler_skip - connect \Y $not$ls180.v:3052$77_Y - end - attribute \src "ls180.v:3053.27-3053.51" - cell $not $not$ls180.v:3053$78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_socbushandler_skip - connect \Y $not$ls180.v:3053$78_Y - end - attribute \src "ls180.v:3255.34-3255.64" - cell $not $not$ls180.v:3255$214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [0] - connect \Y $not$ls180.v:3255$214_Y - end - attribute \src "ls180.v:3256.31-3256.61" - cell $not $not$ls180.v:3256$215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [1] - connect \Y $not$ls180.v:3256$215_Y - end - attribute \src "ls180.v:3257.32-3257.62" - cell $not $not$ls180.v:3257$216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [2] - connect \Y $not$ls180.v:3257$216_Y - end - attribute \src "ls180.v:3258.32-3258.62" - cell $not $not$ls180.v:3258$217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [3] - connect \Y $not$ls180.v:3258$217_Y - end - attribute \src "ls180.v:3300.33-3300.56" - cell $not $not$ls180.v:3300$220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:3300$220_Y - end - attribute \src "ls180.v:3401.58-3401.106" - cell $not $not$ls180.v:3401$250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:3401$250_Y - end - attribute \src "ls180.v:3455.9-3455.45" - cell $not $not$ls180.v:3455$255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_refresh_req - connect \Y $not$ls180.v:3455$255_Y - end - attribute \src "ls180.v:3558.58-3558.106" - cell $not $not$ls180.v:3558$280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:3558$280_Y - end - attribute \src "ls180.v:3612.9-3612.45" - cell $not $not$ls180.v:3612$285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_refresh_req - connect \Y $not$ls180.v:3612$285_Y - end - attribute \src "ls180.v:3715.58-3715.106" - cell $not $not$ls180.v:3715$310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:3715$310_Y - end - attribute \src "ls180.v:3769.9-3769.45" - cell $not $not$ls180.v:3769$315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_refresh_req - connect \Y $not$ls180.v:3769$315_Y - end - attribute \src "ls180.v:3872.58-3872.106" - cell $not $not$ls180.v:3872$340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:3872$340_Y - end - attribute \src "ls180.v:3926.9-3926.45" - cell $not $not$ls180.v:3926$345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_refresh_req - connect \Y $not$ls180.v:3926$345_Y - end - attribute \src "ls180.v:3968.149-3968.187" - cell $not $not$ls180.v:3968$348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3968$348_Y - end - attribute \src "ls180.v:3968.193-3968.230" - cell $not $not$ls180.v:3968$350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3968$350_Y - end - attribute \src "ls180.v:3969.149-3969.187" - cell $not $not$ls180.v:3969$354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3969$354_Y - end - attribute \src "ls180.v:3969.193-3969.230" - cell $not $not$ls180.v:3969$356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3969$356_Y - end - attribute \src "ls180.v:3985.43-3985.73" - cell $not $not$ls180.v:3985$384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \main_sdram_interface_wdata_we - connect \Y $not$ls180.v:3985$384_Y - end - attribute \src "ls180.v:3988.205-3988.245" - cell $not $not$ls180.v:3988$387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3988$387_Y - end - attribute \src "ls180.v:3988.251-3988.290" - cell $not $not$ls180.v:3988$389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3988$389_Y - end - attribute \src "ls180.v:3988.159-3988.292" - cell $not $not$ls180.v:3988$391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$390_Y - connect \Y $not$ls180.v:3988$391_Y - end - attribute \src "ls180.v:3989.205-3989.245" - cell $not $not$ls180.v:3989$400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3989$400_Y - end - attribute \src "ls180.v:3989.251-3989.290" - cell $not $not$ls180.v:3989$402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3989$402_Y - end - attribute \src "ls180.v:3989.159-3989.292" - cell $not $not$ls180.v:3989$404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3989$403_Y - connect \Y $not$ls180.v:3989$404_Y - end - attribute \src "ls180.v:3990.205-3990.245" - cell $not $not$ls180.v:3990$413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3990$413_Y - end - attribute \src "ls180.v:3990.251-3990.290" - cell $not $not$ls180.v:3990$415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3990$415_Y - end - attribute \src "ls180.v:3990.159-3990.292" - cell $not $not$ls180.v:3990$417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3990$416_Y - connect \Y $not$ls180.v:3990$417_Y - end - attribute \src "ls180.v:3991.205-3991.245" - cell $not $not$ls180.v:3991$426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3991$426_Y - end - attribute \src "ls180.v:3991.251-3991.290" - cell $not $not$ls180.v:3991$428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3991$428_Y - end - attribute \src "ls180.v:3991.159-3991.292" - cell $not $not$ls180.v:3991$430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3991$429_Y - connect \Y $not$ls180.v:3991$430_Y - end - attribute \src "ls180.v:4018.71-4018.103" - cell $not $not$ls180.v:4018$441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \Y $not$ls180.v:4018$441_Y - end - attribute \src "ls180.v:4021.205-4021.245" - cell $not $not$ls180.v:4021$445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:4021$445_Y - end - attribute \src "ls180.v:4021.251-4021.290" - cell $not $not$ls180.v:4021$447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:4021$447_Y - end - attribute \src "ls180.v:4021.159-4021.292" - cell $not $not$ls180.v:4021$449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$448_Y - connect \Y $not$ls180.v:4021$449_Y - end - attribute \src "ls180.v:4022.205-4022.245" - cell $not $not$ls180.v:4022$458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:4022$458_Y - end - attribute \src "ls180.v:4022.251-4022.290" - cell $not $not$ls180.v:4022$460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:4022$460_Y - end - attribute \src "ls180.v:4022.159-4022.292" - cell $not $not$ls180.v:4022$462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4022$461_Y - connect \Y $not$ls180.v:4022$462_Y - end - attribute \src "ls180.v:4023.205-4023.245" - cell $not $not$ls180.v:4023$471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:4023$471_Y - end - attribute \src "ls180.v:4023.251-4023.290" - cell $not $not$ls180.v:4023$473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:4023$473_Y - end - attribute \src "ls180.v:4023.159-4023.292" - cell $not $not$ls180.v:4023$475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4023$474_Y - connect \Y $not$ls180.v:4023$475_Y - end - attribute \src "ls180.v:4024.205-4024.245" - cell $not $not$ls180.v:4024$484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:4024$484_Y - end - attribute \src "ls180.v:4024.251-4024.290" - cell $not $not$ls180.v:4024$486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:4024$486_Y - end - attribute \src "ls180.v:4024.159-4024.292" - cell $not $not$ls180.v:4024$488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4024$487_Y - connect \Y $not$ls180.v:4024$488_Y - end - attribute \src "ls180.v:4087.71-4087.103" - cell $not $not$ls180.v:4087$527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \Y $not$ls180.v:4087$527_Y - end - attribute \src "ls180.v:4108.112-4108.150" - cell $not $not$ls180.v:4108$530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:4108$530_Y - end - attribute \src "ls180.v:4108.156-4108.193" - cell $not $not$ls180.v:4108$532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:4108$532_Y - end - attribute \src "ls180.v:4108.68-4108.195" - cell $not $not$ls180.v:4108$534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4108$533_Y - connect \Y $not$ls180.v:4108$534_Y - end - attribute \src "ls180.v:4116.11-4116.38" - cell $not $not$ls180.v:4116$537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_write_available - connect \Y $not$ls180.v:4116$537_Y - end - attribute \src "ls180.v:4146.112-4146.150" - cell $not $not$ls180.v:4146$539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:4146$539_Y - end - attribute \src "ls180.v:4146.156-4146.193" - cell $not $not$ls180.v:4146$541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:4146$541_Y - end - attribute \src "ls180.v:4146.68-4146.195" - cell $not $not$ls180.v:4146$543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4146$542_Y - connect \Y $not$ls180.v:4146$543_Y - end - attribute \src "ls180.v:4154.11-4154.37" - cell $not $not$ls180.v:4154$546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_read_available - connect \Y $not$ls180.v:4154$546_Y - end - attribute \src "ls180.v:4164.87-4164.331" - cell $not $not$ls180.v:4164$558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4164$557_Y - connect \Y $not$ls180.v:4164$558_Y - end - attribute \src "ls180.v:4165.35-4165.68" - cell $not $not$ls180.v:4165$561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_valid - connect \Y $not$ls180.v:4165$561_Y - end - attribute \src "ls180.v:4165.73-4165.105" - cell $not $not$ls180.v:4165$562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \Y $not$ls180.v:4165$562_Y - end - attribute \src "ls180.v:4169.87-4169.331" - cell $not $not$ls180.v:4169$574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4169$573_Y - connect \Y $not$ls180.v:4169$574_Y - end - attribute \src "ls180.v:4170.35-4170.68" - cell $not $not$ls180.v:4170$577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_valid - connect \Y $not$ls180.v:4170$577_Y - end - attribute \src "ls180.v:4170.73-4170.105" - cell $not $not$ls180.v:4170$578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \Y $not$ls180.v:4170$578_Y - end - attribute \src "ls180.v:4174.87-4174.331" - cell $not $not$ls180.v:4174$590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4174$589_Y - connect \Y $not$ls180.v:4174$590_Y - end - attribute \src "ls180.v:4175.35-4175.68" - cell $not $not$ls180.v:4175$593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_valid - connect \Y $not$ls180.v:4175$593_Y - end - attribute \src "ls180.v:4175.73-4175.105" - cell $not $not$ls180.v:4175$594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \Y $not$ls180.v:4175$594_Y - end - attribute \src "ls180.v:4179.87-4179.331" - cell $not $not$ls180.v:4179$606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4179$605_Y - connect \Y $not$ls180.v:4179$606_Y - end - attribute \src "ls180.v:4180.35-4180.68" - cell $not $not$ls180.v:4180$609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_valid - connect \Y $not$ls180.v:4180$609_Y - end - attribute \src "ls180.v:4180.73-4180.105" - cell $not $not$ls180.v:4180$610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \Y $not$ls180.v:4180$610_Y - end - attribute \src "ls180.v:4184.128-4184.372" - cell $not $not$ls180.v:4184$623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$622_Y - connect \Y $not$ls180.v:4184$623_Y - end - attribute \src "ls180.v:4184.502-4184.746" - cell $not $not$ls180.v:4184$639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$638_Y - connect \Y $not$ls180.v:4184$639_Y - end - attribute \src "ls180.v:4184.876-4184.1120" - cell $not $not$ls180.v:4184$655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$654_Y - connect \Y $not$ls180.v:4184$655_Y - end - attribute \src "ls180.v:4184.1250-4184.1494" - cell $not $not$ls180.v:4184$671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$670_Y - connect \Y $not$ls180.v:4184$671_Y - end - attribute \src "ls180.v:4206.32-4206.50" - cell $not $not$ls180.v:4206$677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_cyc - connect \Y $not$ls180.v:4206$677_Y - end - attribute \src "ls180.v:4245.30-4245.50" - cell $not $not$ls180.v:4245$682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_skip - connect \Y $not$ls180.v:4245$682_Y - end - attribute \src "ls180.v:4246.30-4246.50" - cell $not $not$ls180.v:4246$683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_skip - connect \Y $not$ls180.v:4246$683_Y - end - attribute \src "ls180.v:4271.27-4271.48" - cell $not $not$ls180.v:4271$689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_cyc - connect \Y $not$ls180.v:4271$689_Y - end - attribute \src "ls180.v:4272.30-4272.50" - cell $not $not$ls180.v:4272$690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4272$690_Y - end - attribute \src "ls180.v:4273.80-4273.98" - cell $not $not$ls180.v:4273$692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_cmd_consumed - connect \Y $not$ls180.v:4273$692_Y - end - attribute \src "ls180.v:4274.107-4274.127" - cell $not $not$ls180.v:4274$696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wdata_consumed - connect \Y $not$ls180.v:4274$696_Y - end - attribute \src "ls180.v:4275.78-4275.103" - cell $not $not$ls180.v:4275$699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_we - connect \Y $not$ls180.v:4275$699_Y - end - attribute \src "ls180.v:4276.91-4276.111" - cell $not $not$ls180.v:4276$702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4276$702_Y - end - attribute \src "ls180.v:4292.35-4292.64" - cell $not $not$ls180.v:4292$711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4292$711_Y - end - attribute \src "ls180.v:4293.36-4293.67" - cell $not $not$ls180.v:4293$712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_source_valid - connect \Y $not$ls180.v:4293$712_Y - end - attribute \src "ls180.v:4299.32-4299.61" - cell $not $not$ls180.v:4299$713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4299$713_Y - end - attribute \src "ls180.v:4305.36-4305.67" - cell $not $not$ls180.v:4305$714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4305$714_Y - end - attribute \src "ls180.v:4306.35-4306.64" - cell $not $not$ls180.v:4306$715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_sink_ready - connect \Y $not$ls180.v:4306$715_Y - end - attribute \src "ls180.v:4309.32-4309.63" - cell $not $not$ls180.v:4309$718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4309$718_Y - end - attribute \src "ls180.v:4347.81-4347.108" - cell $not $not$ls180.v:4347$728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_readable - connect \Y $not$ls180.v:4347$728_Y - end - attribute \src "ls180.v:4377.81-4377.108" - cell $not $not$ls180.v:4377$739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_readable - connect \Y $not$ls180.v:4377$739_Y - end - attribute \src "ls180.v:4588.60-4588.85" - cell $not $not$ls180.v:4588$790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk_d - connect \Y $not$ls180.v:4588$790_Y - end - attribute \src "ls180.v:4729.54-4729.96" - cell $not $not$ls180.v:4729$804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \Y $not$ls180.v:4729$804_Y - end - attribute \src "ls180.v:4732.48-4732.86" - cell $not $not$ls180.v:4732$807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:4732$807_Y - end - attribute \src "ls180.v:4856.55-4856.98" - cell $not $not$ls180.v:4856$825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_strobe_all - connect \Y $not$ls180.v:4856$825_Y - end - attribute \src "ls180.v:4859.49-4859.88" - cell $not $not$ls180.v:4859$828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:4859$828_Y - end - attribute \src "ls180.v:4909.30-4909.58" - cell $not $not$ls180.v:4909$834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \Y $not$ls180.v:4909$834_Y - end - attribute \src "ls180.v:4990.56-4990.100" - cell $not $not$ls180.v:4990$840 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_strobe_all - connect \Y $not$ls180.v:4990$840_Y - end - attribute \src "ls180.v:4993.50-4993.90" - cell $not $not$ls180.v:4993$843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:4993$843_Y - end - attribute \src "ls180.v:5109.42-5109.74" - cell $not $not$ls180.v:5109$859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_valid - connect \Y $not$ls180.v:5109$859_Y - end - attribute \src "ls180.v:5633.50-5633.88" - cell $not $not$ls180.v:5633$1144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_strobe_all - connect \Y $not$ls180.v:5633$1144_Y - end - attribute \src "ls180.v:5645.52-5645.102" - cell $not $not$ls180.v:5645$1147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \Y $not$ls180.v:5645$1147_Y - end - attribute \src "ls180.v:5704.38-5704.74" - cell $not $not$ls180.v:5704$1154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_dma_enable_storage - connect \Y $not$ls180.v:5704$1154_Y - end - attribute \src "ls180.v:6030.69-6030.88" - cell $not $not$ls180.v:6030$1239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \Y $not$ls180.v:6030$1239_Y - end - attribute \src "ls180.v:6047.63-6047.94" - cell $not $not$ls180.v:6047$1284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6047$1284_Y - end - attribute \src "ls180.v:6050.65-6050.96" - cell $not $not$ls180.v:6050$1291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6050$1291_Y - end - attribute \src "ls180.v:6053.65-6053.96" - cell $not $not$ls180.v:6053$1298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6053$1298_Y - end - attribute \src "ls180.v:6056.65-6056.96" - cell $not $not$ls180.v:6056$1305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6056$1305_Y - end - attribute \src "ls180.v:6059.65-6059.96" - cell $not $not$ls180.v:6059$1312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6059$1312_Y - end - attribute \src "ls180.v:6062.68-6062.99" - cell $not $not$ls180.v:6062$1319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6062$1319_Y - end - attribute \src "ls180.v:6065.68-6065.99" - cell $not $not$ls180.v:6065$1326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6065$1326_Y - end - attribute \src "ls180.v:6068.68-6068.99" - cell $not $not$ls180.v:6068$1333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6068$1333_Y - end - attribute \src "ls180.v:6071.68-6071.99" - cell $not $not$ls180.v:6071$1340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6071$1340_Y - end - attribute \src "ls180.v:6085.60-6085.91" - cell $not $not$ls180.v:6085$1348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6085$1348_Y - end - attribute \src "ls180.v:6088.60-6088.91" - cell $not $not$ls180.v:6088$1355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6088$1355_Y - end - attribute \src "ls180.v:6091.60-6091.91" - cell $not $not$ls180.v:6091$1362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6091$1362_Y - end - attribute \src "ls180.v:6094.60-6094.91" - cell $not $not$ls180.v:6094$1369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6094$1369_Y - end - attribute \src "ls180.v:6097.61-6097.92" - cell $not $not$ls180.v:6097$1376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6097$1376_Y - end - attribute \src "ls180.v:6100.61-6100.92" - cell $not $not$ls180.v:6100$1383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6100$1383_Y - end - attribute \src "ls180.v:6111.59-6111.90" - cell $not $not$ls180.v:6111$1391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:6111$1391_Y - end - attribute \src "ls180.v:6114.58-6114.89" - cell $not $not$ls180.v:6114$1398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:6114$1398_Y - end - attribute \src "ls180.v:6125.64-6125.95" - cell $not $not$ls180.v:6125$1406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6125$1406_Y - end - attribute \src "ls180.v:6128.63-6128.94" - cell $not $not$ls180.v:6128$1413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6128$1413_Y - end - attribute \src "ls180.v:6131.63-6131.94" - cell $not $not$ls180.v:6131$1420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6131$1420_Y - end - attribute \src "ls180.v:6134.63-6134.94" - cell $not $not$ls180.v:6134$1427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6134$1427_Y - end - attribute \src "ls180.v:6137.63-6137.94" - cell $not $not$ls180.v:6137$1434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6137$1434_Y - end - attribute \src "ls180.v:6140.64-6140.95" - cell $not $not$ls180.v:6140$1441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6140$1441_Y - end - attribute \src "ls180.v:6143.64-6143.95" - cell $not $not$ls180.v:6143$1448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6143$1448_Y - end - attribute \src "ls180.v:6146.64-6146.95" - cell $not $not$ls180.v:6146$1455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6146$1455_Y - end - attribute \src "ls180.v:6149.64-6149.95" - cell $not $not$ls180.v:6149$1462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6149$1462_Y - end - attribute \src "ls180.v:6162.64-6162.95" - cell $not $not$ls180.v:6162$1470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6162$1470_Y - end - attribute \src "ls180.v:6165.63-6165.94" - cell $not $not$ls180.v:6165$1477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6165$1477_Y - end - attribute \src "ls180.v:6168.63-6168.94" - cell $not $not$ls180.v:6168$1484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6168$1484_Y - end - attribute \src "ls180.v:6171.63-6171.94" - cell $not $not$ls180.v:6171$1491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6171$1491_Y - end - attribute \src "ls180.v:6174.63-6174.94" - cell $not $not$ls180.v:6174$1498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6174$1498_Y - end - attribute \src "ls180.v:6177.64-6177.95" - cell $not $not$ls180.v:6177$1505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6177$1505_Y - end - attribute \src "ls180.v:6180.64-6180.95" - cell $not $not$ls180.v:6180$1512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6180$1512_Y - end - attribute \src "ls180.v:6183.64-6183.95" - cell $not $not$ls180.v:6183$1519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6183$1519_Y - end - attribute \src "ls180.v:6186.64-6186.95" - cell $not $not$ls180.v:6186$1526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6186$1526_Y - end - attribute \src "ls180.v:6199.66-6199.97" - cell $not $not$ls180.v:6199$1534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6199$1534_Y - end - attribute \src "ls180.v:6202.66-6202.97" - cell $not $not$ls180.v:6202$1541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6202$1541_Y - end - attribute \src "ls180.v:6205.66-6205.97" - cell $not $not$ls180.v:6205$1548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6205$1548_Y - end - attribute \src "ls180.v:6208.66-6208.97" - cell $not $not$ls180.v:6208$1555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6208$1555_Y - end - attribute \src "ls180.v:6211.66-6211.97" - cell $not $not$ls180.v:6211$1562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6211$1562_Y - end - attribute \src "ls180.v:6214.66-6214.97" - cell $not $not$ls180.v:6214$1569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6214$1569_Y - end - attribute \src "ls180.v:6217.66-6217.97" - cell $not $not$ls180.v:6217$1576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6217$1576_Y - end - attribute \src "ls180.v:6220.66-6220.97" - cell $not $not$ls180.v:6220$1583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6220$1583_Y - end - attribute \src "ls180.v:6223.68-6223.99" - cell $not $not$ls180.v:6223$1590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6223$1590_Y - end - attribute \src "ls180.v:6226.68-6226.99" - cell $not $not$ls180.v:6226$1597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6226$1597_Y - end - attribute \src "ls180.v:6229.68-6229.99" - cell $not $not$ls180.v:6229$1604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6229$1604_Y - end - attribute \src "ls180.v:6232.68-6232.99" - cell $not $not$ls180.v:6232$1611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6232$1611_Y - end - attribute \src "ls180.v:6235.68-6235.99" - cell $not $not$ls180.v:6235$1618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6235$1618_Y - end - attribute \src "ls180.v:6238.65-6238.96" - cell $not $not$ls180.v:6238$1625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6238$1625_Y - end - attribute \src "ls180.v:6241.66-6241.97" - cell $not $not$ls180.v:6241$1632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6241$1632_Y - end - attribute \src "ls180.v:6261.70-6261.101" - cell $not $not$ls180.v:6261$1640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6261$1640_Y - end - attribute \src "ls180.v:6264.70-6264.101" - cell $not $not$ls180.v:6264$1647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6264$1647_Y - end - attribute \src "ls180.v:6267.70-6267.101" - cell $not $not$ls180.v:6267$1654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6267$1654_Y - end - attribute \src "ls180.v:6270.70-6270.101" - cell $not $not$ls180.v:6270$1661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6270$1661_Y - end - attribute \src "ls180.v:6273.69-6273.100" - cell $not $not$ls180.v:6273$1668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6273$1668_Y - end - attribute \src "ls180.v:6276.69-6276.100" - cell $not $not$ls180.v:6276$1675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6276$1675_Y - end - attribute \src "ls180.v:6279.69-6279.100" - cell $not $not$ls180.v:6279$1682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6279$1682_Y - end - attribute \src "ls180.v:6282.69-6282.100" - cell $not $not$ls180.v:6282$1689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6282$1689_Y - end - attribute \src "ls180.v:6285.60-6285.91" - cell $not $not$ls180.v:6285$1696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6285$1696_Y - end - attribute \src "ls180.v:6288.71-6288.102" - cell $not $not$ls180.v:6288$1703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6288$1703_Y - end - attribute \src "ls180.v:6291.71-6291.102" - cell $not $not$ls180.v:6291$1710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6291$1710_Y - end - attribute \src "ls180.v:6294.71-6294.102" - cell $not $not$ls180.v:6294$1717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6294$1717_Y - end - attribute \src "ls180.v:6297.71-6297.102" - cell $not $not$ls180.v:6297$1724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6297$1724_Y - end - attribute \src "ls180.v:6300.71-6300.102" - cell $not $not$ls180.v:6300$1731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6300$1731_Y - end - attribute \src "ls180.v:6303.71-6303.102" - cell $not $not$ls180.v:6303$1738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6303$1738_Y - end - attribute \src "ls180.v:6306.70-6306.101" - cell $not $not$ls180.v:6306$1745 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6306$1745_Y - end - attribute \src "ls180.v:6309.70-6309.101" - cell $not $not$ls180.v:6309$1752 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6309$1752_Y - end - attribute \src "ls180.v:6312.70-6312.101" - cell $not $not$ls180.v:6312$1759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6312$1759_Y - end - attribute \src "ls180.v:6315.70-6315.101" - cell $not $not$ls180.v:6315$1766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6315$1766_Y - end - attribute \src "ls180.v:6318.70-6318.101" - cell $not $not$ls180.v:6318$1773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6318$1773_Y - end - attribute \src "ls180.v:6321.70-6321.101" - cell $not $not$ls180.v:6321$1780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6321$1780_Y - end - attribute \src "ls180.v:6324.70-6324.101" - cell $not $not$ls180.v:6324$1787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6324$1787_Y - end - attribute \src "ls180.v:6327.70-6327.101" - cell $not $not$ls180.v:6327$1794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6327$1794_Y - end - attribute \src "ls180.v:6330.70-6330.101" - cell $not $not$ls180.v:6330$1801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6330$1801_Y - end - attribute \src "ls180.v:6333.70-6333.101" - cell $not $not$ls180.v:6333$1808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6333$1808_Y - end - attribute \src "ls180.v:6336.66-6336.97" - cell $not $not$ls180.v:6336$1815 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6336$1815_Y - end - attribute \src "ls180.v:6339.67-6339.98" - cell $not $not$ls180.v:6339$1822 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6339$1822_Y - end - attribute \src "ls180.v:6342.70-6342.101" - cell $not $not$ls180.v:6342$1829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6342$1829_Y - end - attribute \src "ls180.v:6345.70-6345.101" - cell $not $not$ls180.v:6345$1836 - parameter \A_SIGNED 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attribute \src "ls180.v:6420.68-6420.99" - cell $not $not$ls180.v:6420$1928 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6420$1928_Y - end - attribute \src "ls180.v:6423.68-6423.99" - cell $not $not$ls180.v:6423$1935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6423$1935_Y - end - attribute \src "ls180.v:6426.68-6426.99" - cell $not $not$ls180.v:6426$1942 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6426$1942_Y - end - attribute \src "ls180.v:6429.68-6429.99" - cell $not $not$ls180.v:6429$1949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6429$1949_Y - end - attribute \src "ls180.v:6432.68-6432.99" - cell $not $not$ls180.v:6432$1956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6432$1956_Y - end - attribute \src "ls180.v:6435.65-6435.96" - cell $not $not$ls180.v:6435$1963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6435$1963_Y - end - attribute \src "ls180.v:6438.66-6438.97" - cell $not $not$ls180.v:6438$1970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6438$1970_Y - end - attribute \src "ls180.v:6441.68-6441.99" - cell $not $not$ls180.v:6441$1977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6441$1977_Y - end - attribute \src "ls180.v:6444.68-6444.99" - cell $not $not$ls180.v:6444$1984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6444$1984_Y - end - attribute \src "ls180.v:6447.68-6447.99" - cell $not $not$ls180.v:6447$1991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6447$1991_Y - end - attribute \src "ls180.v:6450.68-6450.99" - cell $not $not$ls180.v:6450$1998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6450$1998_Y - end - attribute \src "ls180.v:6475.68-6475.99" - cell $not $not$ls180.v:6475$2006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6475$2006_Y - end - attribute \src "ls180.v:6478.73-6478.104" - cell $not $not$ls180.v:6478$2013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - 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attribute \src "ls180.v:6510.73-6510.104" - cell $not $not$ls180.v:6510$2077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6510$2077_Y - end - attribute \src "ls180.v:6513.73-6513.104" - cell $not $not$ls180.v:6513$2084 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6513$2084_Y - end - attribute \src "ls180.v:6516.73-6516.104" - cell $not $not$ls180.v:6516$2091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6516$2091_Y - end - attribute \src "ls180.v:6519.73-6519.104" - cell $not $not$ls180.v:6519$2098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6519$2098_Y - end - attribute \src "ls180.v:6537.67-6537.99" - cell $not $not$ls180.v:6537$2106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6537$2106_Y - end - attribute \src "ls180.v:6540.67-6540.99" - cell $not $not$ls180.v:6540$2113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6540$2113_Y - end - attribute \src "ls180.v:6543.65-6543.97" - cell $not $not$ls180.v:6543$2120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6543$2120_Y - end - attribute \src "ls180.v:6546.64-6546.96" - cell $not $not$ls180.v:6546$2127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6546$2127_Y - end - attribute \src "ls180.v:6549.63-6549.95" - cell $not $not$ls180.v:6549$2134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6549$2134_Y - end - attribute \src "ls180.v:6552.62-6552.94" - cell $not $not$ls180.v:6552$2141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6552$2141_Y - end - attribute \src "ls180.v:6555.68-6555.100" - cell $not $not$ls180.v:6555$2148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6555$2148_Y - end - attribute \src "ls180.v:6577.67-6577.99" - cell $not $not$ls180.v:6577$2157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6577$2157_Y - end - attribute \src "ls180.v:6580.67-6580.99" - cell $not $not$ls180.v:6580$2164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter 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"ls180.v:6640.66-6640.98" - cell $not $not$ls180.v:6640$2257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6640$2257_Y - end - attribute \src "ls180.v:6643.66-6643.98" - cell $not $not$ls180.v:6643$2264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6643$2264_Y - end - attribute \src "ls180.v:6646.66-6646.98" - cell $not $not$ls180.v:6646$2271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6646$2271_Y - end - attribute \src "ls180.v:6649.62-6649.94" - cell $not $not$ls180.v:6649$2278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6649$2278_Y - end - attribute \src "ls180.v:6652.72-6652.104" - cell $not $not$ls180.v:6652$2285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6652$2285_Y - end - attribute \src "ls180.v:6655.65-6655.97" - cell $not $not$ls180.v:6655$2292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6655$2292_Y - end - attribute \src "ls180.v:6658.65-6658.97" - cell $not $not$ls180.v:6658$2299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6658$2299_Y - end - attribute \src "ls180.v:6661.65-6661.97" - cell $not $not$ls180.v:6661$2306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6661$2306_Y - end - attribute \src "ls180.v:6664.65-6664.97" - cell $not $not$ls180.v:6664$2313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6664$2313_Y - end - attribute \src "ls180.v:6667.77-6667.109" - cell $not $not$ls180.v:6667$2320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6667$2320_Y - end - attribute \src "ls180.v:6670.78-6670.110" - cell $not $not$ls180.v:6670$2327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6670$2327_Y - end - attribute \src "ls180.v:6673.69-6673.101" - cell $not $not$ls180.v:6673$2334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6673$2334_Y - end - attribute \src "ls180.v:6693.55-6693.87" - cell $not $not$ls180.v:6693$2342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6693$2342_Y - end - attribute \src "ls180.v:6696.65-6696.97" - cell $not $not$ls180.v:6696$2349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6696$2349_Y - end - attribute \src "ls180.v:6699.66-6699.98" - cell $not $not$ls180.v:6699$2356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6699$2356_Y - end - attribute \src "ls180.v:6702.70-6702.102" - cell $not $not$ls180.v:6702$2363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6702$2363_Y - end - attribute \src "ls180.v:6705.71-6705.103" - cell $not $not$ls180.v:6705$2370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6705$2370_Y - end - attribute \src "ls180.v:6708.69-6708.101" - cell $not $not$ls180.v:6708$2377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6708$2377_Y - end - attribute \src "ls180.v:6711.66-6711.98" - cell $not $not$ls180.v:6711$2384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6711$2384_Y - end - attribute \src "ls180.v:6714.65-6714.97" - cell $not $not$ls180.v:6714$2391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6714$2391_Y - end - attribute \src "ls180.v:6727.71-6727.103" - cell $not $not$ls180.v:6727$2399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6727$2399_Y - end - attribute \src "ls180.v:6730.71-6730.103" - cell $not $not$ls180.v:6730$2406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6730$2406_Y - end - attribute \src "ls180.v:6733.71-6733.103" - cell $not $not$ls180.v:6733$2413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6733$2413_Y - end - attribute \src "ls180.v:6736.71-6736.103" - cell $not $not$ls180.v:6736$2420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6736$2420_Y - end - attribute \src "ls180.v:7117.86-7117.330" - cell $not $not$ls180.v:7117$2469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7117$2468_Y - connect \Y $not$ls180.v:7117$2469_Y - end - attribute \src "ls180.v:7141.86-7141.330" - cell $not $not$ls180.v:7141$2485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7141$2484_Y - connect \Y $not$ls180.v:7141$2485_Y - end - attribute \src "ls180.v:7165.86-7165.330" - cell $not $not$ls180.v:7165$2501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7165$2500_Y - connect \Y $not$ls180.v:7165$2501_Y - end - attribute \src "ls180.v:7189.86-7189.330" - cell $not $not$ls180.v:7189$2517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7189$2516_Y - connect \Y $not$ls180.v:7189$2517_Y - end - attribute \src "ls180.v:7690.18-7690.42" - cell $not $not$ls180.v:7690$2573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk0 - connect \Y $not$ls180.v:7690$2573_Y - end - attribute \src "ls180.v:7769.72-7769.101" - cell $not $not$ls180.v:7769$2606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7769$2606_Y - end - attribute \src "ls180.v:7788.8-7788.38" - cell $not $not$ls180.v:7788$2610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_zero_trigger - connect \Y $not$ls180.v:7788$2610_Y - end - attribute \src "ls180.v:7792.70-7792.98" - cell $not $not$ls180.v:7792$2613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_ack - connect \Y $not$ls180.v:7792$2613_Y - end - attribute \src "ls180.v:7796.70-7796.98" - cell $not $not$ls180.v:7796$2616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_ack - connect \Y $not$ls180.v:7796$2616_Y - end - attribute \src "ls180.v:7800.70-7800.98" - cell $not $not$ls180.v:7800$2619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_ack - connect \Y $not$ls180.v:7800$2619_Y - end - attribute \src "ls180.v:7804.70-7804.98" - cell $not $not$ls180.v:7804$2622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_ack - connect \Y $not$ls180.v:7804$2622_Y - end - attribute \src "ls180.v:7812.32-7812.55" - cell $not $not$ls180.v:7812$2624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7812$2624_Y - end - attribute \src "ls180.v:7882.136-7882.189" - cell $not $not$ls180.v:7882$2639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7882$2639_Y - end - attribute \src "ls180.v:7888.136-7888.189" - cell $not $not$ls180.v:7888$2644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7888$2644_Y - end - attribute \src "ls180.v:7889.8-7889.61" - cell $not $not$ls180.v:7889$2646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7889$2646_Y - end - attribute \src "ls180.v:7897.8-7897.56" - cell $not $not$ls180.v:7897$2649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7897$2649_Y - end - attribute \src "ls180.v:7912.8-7912.46" - cell $not $not$ls180.v:7912$2651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7912$2651_Y - end - attribute \src "ls180.v:7928.136-7928.189" - cell $not $not$ls180.v:7928$2655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7928$2655_Y - end - attribute \src "ls180.v:7934.136-7934.189" - cell $not $not$ls180.v:7934$2660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7934$2660_Y - end - attribute \src "ls180.v:7935.8-7935.61" - cell $not $not$ls180.v:7935$2662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7935$2662_Y - end - attribute \src "ls180.v:7943.8-7943.56" - cell $not $not$ls180.v:7943$2665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7943$2665_Y - end - attribute \src "ls180.v:7958.8-7958.46" - cell $not $not$ls180.v:7958$2667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7958$2667_Y - end - attribute \src "ls180.v:7974.136-7974.189" - cell $not $not$ls180.v:7974$2671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7974$2671_Y - end - attribute \src "ls180.v:7980.136-7980.189" - cell $not $not$ls180.v:7980$2676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7980$2676_Y - end - attribute \src "ls180.v:7981.8-7981.61" - cell $not $not$ls180.v:7981$2678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7981$2678_Y - end - attribute \src "ls180.v:7989.8-7989.56" - cell $not $not$ls180.v:7989$2681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7989$2681_Y - end - attribute \src "ls180.v:8004.8-8004.46" - cell $not $not$ls180.v:8004$2683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:8004$2683_Y - end - attribute \src "ls180.v:8020.136-8020.189" - cell $not $not$ls180.v:8020$2687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:8020$2687_Y - end - attribute \src "ls180.v:8026.136-8026.189" - cell $not $not$ls180.v:8026$2692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:8026$2692_Y - end - attribute \src "ls180.v:8027.8-8027.61" - cell $not $not$ls180.v:8027$2694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:8027$2694_Y - end - attribute \src "ls180.v:8035.8-8035.56" - cell $not $not$ls180.v:8035$2697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:8035$2697_Y - end - attribute \src "ls180.v:8050.8-8050.46" - cell $not $not$ls180.v:8050$2699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:8050$2699_Y - end - attribute \src "ls180.v:8058.7-8058.22" - cell $not $not$ls180.v:8058$2702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_en0 - connect \Y $not$ls180.v:8058$2702_Y - end - attribute \src "ls180.v:8061.8-8061.29" - cell $not $not$ls180.v:8061$2703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:8061$2703_Y - end - attribute \src "ls180.v:8065.7-8065.22" - cell $not $not$ls180.v:8065$2705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_en1 - connect \Y $not$ls180.v:8065$2705_Y - end - attribute \src "ls180.v:8068.8-8068.29" - cell $not $not$ls180.v:8068$2706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:8068$2706_Y - end - attribute \src "ls180.v:8187.30-8187.60" - cell $not $not$ls180.v:8187$2708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:8187$2708_Y - end - attribute \src "ls180.v:8188.30-8188.60" - cell $not $not$ls180.v:8188$2709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:8188$2709_Y - end - attribute \src "ls180.v:8189.29-8189.59" - cell $not $not$ls180.v:8189$2710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:8189$2710_Y - end - attribute \src "ls180.v:8200.8-8200.33" - cell $not $not$ls180.v:8200$2711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:8200$2711_Y - end - attribute \src "ls180.v:8215.8-8215.33" - cell $not $not$ls180.v:8215$2714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:8215$2714_Y - end - attribute \src "ls180.v:8251.36-8251.58" - cell $not $not$ls180.v:8251$2744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_busy - connect \Y $not$ls180.v:8251$2744_Y - end - attribute \src "ls180.v:8251.64-8251.89" - cell $not $not$ls180.v:8251$2746 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_sink_ready - connect \Y $not$ls180.v:8251$2746_Y - end - attribute \src "ls180.v:8280.7-8280.29" - cell $not $not$ls180.v:8280$2753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_busy - connect \Y $not$ls180.v:8280$2753_Y - end - attribute \src "ls180.v:8281.9-8281.26" - cell $not $not$ls180.v:8281$2754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx - connect \Y $not$ls180.v:8281$2754_Y - end - attribute \src "ls180.v:8314.8-8314.29" - cell $not $not$ls180.v:8314$2760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_trigger - connect \Y $not$ls180.v:8314$2760_Y - end - attribute \src "ls180.v:8321.8-8321.29" - cell $not $not$ls180.v:8321$2762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_trigger - connect \Y $not$ls180.v:8321$2762_Y - end - attribute \src "ls180.v:8331.80-8331.106" - cell $not $not$ls180.v:8331$2765 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8331$2765_Y - end - attribute \src "ls180.v:8337.80-8337.106" - cell $not $not$ls180.v:8337$2770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8337$2770_Y - end - attribute \src "ls180.v:8338.8-8338.34" - cell $not $not$ls180.v:8338$2772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_do_read - connect \Y $not$ls180.v:8338$2772_Y - end - attribute \src "ls180.v:8353.80-8353.106" - cell $not $not$ls180.v:8353$2776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8353$2776_Y - end - attribute \src "ls180.v:8359.80-8359.106" - cell $not $not$ls180.v:8359$2781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8359$2781_Y - end - attribute \src "ls180.v:8360.8-8360.34" - cell $not $not$ls180.v:8360$2783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_do_read - connect \Y $not$ls180.v:8360$2783_Y - end - attribute \src "ls180.v:8391.22-8391.41" - cell $not $not$ls180.v:8391$2787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spimaster6_cs - connect \Y $not$ls180.v:8391$2787_Y - end - attribute \src "ls180.v:8391.46-8391.73" - cell $not $not$ls180.v:8391$2788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spimaster26_cs_enable - connect \Y $not$ls180.v:8391$2788_Y - end - attribute \src "ls180.v:8426.22-8426.40" - cell $not $not$ls180.v:8426$2792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_cs - connect \Y $not$ls180.v:8426$2792_Y - end - attribute \src "ls180.v:8426.45-8426.70" - cell $not $not$ls180.v:8426$2793 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_cs_enable - connect \Y $not$ls180.v:8426$2793_Y - end - attribute \src "ls180.v:8480.7-8480.31" - cell $not $not$ls180.v:8480$2804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_stop - connect \Y $not$ls180.v:8480$2804_Y - end - attribute \src "ls180.v:8552.8-8552.46" - cell $not $not$ls180.v:8552$2816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:8552$2816_Y - end - attribute \src "ls180.v:8633.8-8633.47" - cell $not $not$ls180.v:8633$2828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:8633$2828_Y - end - attribute \src "ls180.v:8694.8-8694.48" - cell $not $not$ls180.v:8694$2840 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:8694$2840_Y - end - attribute \src "ls180.v:8864.88-8864.118" - cell $not $not$ls180.v:8864$2854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8864$2854_Y - end - attribute \src "ls180.v:8870.88-8870.118" - cell $not $not$ls180.v:8870$2859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8870$2859_Y - end - attribute \src "ls180.v:8871.8-8871.38" - cell $not $not$ls180.v:8871$2861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8871$2861_Y - end - attribute \src "ls180.v:8962.88-8962.118" - cell $not $not$ls180.v:8962$2876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8962$2876_Y - end - attribute \src "ls180.v:8968.88-8968.118" - cell $not $not$ls180.v:8968$2881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8968$2881_Y - end - attribute \src "ls180.v:8969.8-8969.38" - cell $not $not$ls180.v:8969$2883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8969$2883_Y - end - attribute \src "ls180.v:8989.9-8989.28" - cell $not $not$ls180.v:8989$2886 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [0] - connect \Y $not$ls180.v:8989$2886_Y - end - attribute \src "ls180.v:9008.9-9008.28" - cell $not $not$ls180.v:9008$2887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [1] - connect \Y $not$ls180.v:9008$2887_Y - end - attribute \src "ls180.v:9027.9-9027.28" - cell $not $not$ls180.v:9027$2888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [2] - connect \Y $not$ls180.v:9027$2888_Y - end - attribute \src "ls180.v:9046.9-9046.28" - cell $not $not$ls180.v:9046$2889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [3] - connect \Y $not$ls180.v:9046$2889_Y - end - attribute \src "ls180.v:9065.9-9065.28" - cell $not $not$ls180.v:9065$2890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [4] - connect \Y $not$ls180.v:9065$2890_Y - end - attribute \src "ls180.v:9086.8-9086.21" - cell $not $not$ls180.v:9086$2891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_done - connect \Y $not$ls180.v:9086$2891_Y - end - attribute \src "ls180.v:10709.8-10709.51" - cell $or $or$ls180.v:10709$3079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sys_rst_1 - connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:10709$3079_Y - end - attribute \src "ls180.v:2934.10-2934.71" - cell $or $or$ls180.v:2934$57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_icp_ack - connect \B \main_converter0_skip - connect \Y $or$ls180.v:2934$57_Y - end - attribute \src "ls180.v:2994.10-2994.71" - cell $or $or$ls180.v:2994$68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_ics_ack - connect \B \main_converter1_skip - connect \Y $or$ls180.v:2994$68_Y - end - attribute \src "ls180.v:3054.10-3054.53" - cell $or $or$ls180.v:3054$79 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_ack - connect \B \main_socbushandler_skip - connect \Y $or$ls180.v:3054$79_Y - end - attribute \src "ls180.v:3306.39-3306.105" - cell $or $or$ls180.v:3306$223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_start0 - connect \B $ne$ls180.v:3306$222_Y - connect \Y $or$ls180.v:3306$223_Y - end - attribute \src "ls180.v:3349.59-3349.140" - cell $or $or$ls180.v:3349$227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_req_wdata_ready - connect \B \main_sdram_bankmachine0_req_rdata_valid - connect \Y $or$ls180.v:3349$227_Y - end - attribute \src "ls180.v:3350.44-3350.151" - cell $or $or$ls180.v:3350$228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $or$ls180.v:3350$228_Y - end - attribute \src "ls180.v:3358.45-3358.170" - cell $or $or$ls180.v:3358$232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3358$231_Y - connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3358$232_Y - end - attribute \src "ls180.v:3395.127-3395.245" - cell $or $or$ls180.v:3395$245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3395$245_Y - end - attribute \src "ls180.v:3401.57-3401.157" - cell $or $or$ls180.v:3401$251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3401$250_Y - connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:3401$251_Y - end - attribute \src "ls180.v:3506.59-3506.140" - cell $or $or$ls180.v:3506$257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_req_wdata_ready - connect \B \main_sdram_bankmachine1_req_rdata_valid - connect \Y $or$ls180.v:3506$257_Y - end - attribute \src "ls180.v:3507.44-3507.151" - cell $or $or$ls180.v:3507$258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $or$ls180.v:3507$258_Y - end - attribute \src "ls180.v:3515.45-3515.170" - cell $or $or$ls180.v:3515$262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3515$261_Y - connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3515$262_Y - end - attribute \src "ls180.v:3552.127-3552.245" - cell $or $or$ls180.v:3552$275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3552$275_Y - end - attribute \src "ls180.v:3558.57-3558.157" - cell $or $or$ls180.v:3558$281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3558$280_Y - connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:3558$281_Y - end - attribute \src "ls180.v:3663.59-3663.140" - cell $or $or$ls180.v:3663$287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_req_wdata_ready - connect \B \main_sdram_bankmachine2_req_rdata_valid - connect \Y $or$ls180.v:3663$287_Y - end - attribute \src "ls180.v:3664.44-3664.151" - cell $or $or$ls180.v:3664$288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $or$ls180.v:3664$288_Y - end - attribute \src "ls180.v:3672.45-3672.170" - cell $or $or$ls180.v:3672$292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3672$291_Y - connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3672$292_Y - end - attribute \src "ls180.v:3709.127-3709.245" - cell $or $or$ls180.v:3709$305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3709$305_Y - end - attribute \src "ls180.v:3715.57-3715.157" - cell $or $or$ls180.v:3715$311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3715$310_Y - connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:3715$311_Y - end - attribute \src "ls180.v:3820.59-3820.140" - cell $or $or$ls180.v:3820$317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_req_wdata_ready - connect \B \main_sdram_bankmachine3_req_rdata_valid - connect \Y $or$ls180.v:3820$317_Y - end - attribute \src "ls180.v:3821.44-3821.151" - cell $or $or$ls180.v:3821$318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $or$ls180.v:3821$318_Y - end - attribute \src "ls180.v:3829.45-3829.170" - cell $or $or$ls180.v:3829$322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3829$321_Y - connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3829$322_Y - end - attribute \src "ls180.v:3866.127-3866.245" - cell $or $or$ls180.v:3866$335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3866$335_Y - end - attribute \src "ls180.v:3872.57-3872.157" - cell $or $or$ls180.v:3872$341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3872$340_Y - connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:3872$341_Y - end - attribute \src "ls180.v:3971.107-3971.193" - cell $or $or$ls180.v:3971$361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_is_write - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $or$ls180.v:3971$361_Y - end - attribute \src "ls180.v:3974.39-3974.204" - cell $or $or$ls180.v:3974$367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3974$365_Y - connect \B $and$ls180.v:3974$366_Y - connect \Y $or$ls180.v:3974$367_Y - end - attribute \src "ls180.v:3974.38-3974.289" - cell $or $or$ls180.v:3974$369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3974$367_Y - connect \B $and$ls180.v:3974$368_Y - connect \Y $or$ls180.v:3974$369_Y - end - attribute \src "ls180.v:3974.37-3974.374" - cell $or $or$ls180.v:3974$371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3974$369_Y - connect \B $and$ls180.v:3974$370_Y - connect \Y $or$ls180.v:3974$371_Y - end - attribute \src "ls180.v:3975.40-3975.207" - cell $or $or$ls180.v:3975$374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3975$372_Y - connect \B $and$ls180.v:3975$373_Y - connect \Y $or$ls180.v:3975$374_Y - end - attribute \src "ls180.v:3975.39-3975.293" - cell $or $or$ls180.v:3975$376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3975$374_Y - connect \B $and$ls180.v:3975$375_Y - connect \Y $or$ls180.v:3975$376_Y - end - attribute \src "ls180.v:3975.38-3975.379" - cell $or $or$ls180.v:3975$378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3975$376_Y - connect \B $and$ls180.v:3975$377_Y - connect \Y $or$ls180.v:3975$378_Y - end - attribute \src "ls180.v:3988.158-3988.332" - cell $or $or$ls180.v:3988$392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3988$391_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3988$392_Y - end - attribute \src "ls180.v:3988.75-3988.506" - cell $or $or$ls180.v:3988$397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$393_Y - connect \B $and$ls180.v:3988$396_Y - connect \Y $or$ls180.v:3988$397_Y - end - attribute \src "ls180.v:3989.158-3989.332" - cell $or $or$ls180.v:3989$405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3989$404_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3989$405_Y - end - attribute \src "ls180.v:3989.75-3989.506" - cell $or $or$ls180.v:3989$410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3989$406_Y - connect \B $and$ls180.v:3989$409_Y - connect \Y $or$ls180.v:3989$410_Y - end - attribute \src "ls180.v:3990.158-3990.332" - cell $or $or$ls180.v:3990$418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3990$417_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3990$418_Y - end - attribute \src "ls180.v:3990.75-3990.506" - cell $or $or$ls180.v:3990$423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3990$419_Y - connect \B $and$ls180.v:3990$422_Y - connect \Y $or$ls180.v:3990$423_Y - end - attribute \src "ls180.v:3991.158-3991.332" - cell $or $or$ls180.v:3991$431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3991$430_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3991$431_Y - end - attribute \src "ls180.v:3991.75-3991.506" - cell $or $or$ls180.v:3991$436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3991$432_Y - connect \B $and$ls180.v:3991$435_Y - connect \Y $or$ls180.v:3991$436_Y - end - attribute \src "ls180.v:4018.36-4018.104" - cell $or $or$ls180.v:4018$442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_ready - connect \B $not$ls180.v:4018$441_Y - connect \Y $or$ls180.v:4018$442_Y - end - attribute \src "ls180.v:4021.158-4021.332" - cell $or $or$ls180.v:4021$450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4021$449_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4021$450_Y - end - attribute \src "ls180.v:4021.75-4021.506" - cell $or $or$ls180.v:4021$455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$451_Y - connect \B $and$ls180.v:4021$454_Y - connect \Y $or$ls180.v:4021$455_Y - end - attribute \src "ls180.v:4022.158-4022.332" - cell $or $or$ls180.v:4022$463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4022$462_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4022$463_Y - end - attribute \src "ls180.v:4022.75-4022.506" - cell $or $or$ls180.v:4022$468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4022$464_Y - connect \B $and$ls180.v:4022$467_Y - connect \Y $or$ls180.v:4022$468_Y - end - attribute \src "ls180.v:4023.158-4023.332" - cell $or $or$ls180.v:4023$476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4023$475_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4023$476_Y - end - attribute \src "ls180.v:4023.75-4023.506" - cell $or $or$ls180.v:4023$481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4023$477_Y - connect \B $and$ls180.v:4023$480_Y - connect \Y $or$ls180.v:4023$481_Y - end - attribute \src "ls180.v:4024.158-4024.332" - cell $or $or$ls180.v:4024$489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4024$488_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4024$489_Y - end - attribute \src "ls180.v:4024.75-4024.506" - cell $or $or$ls180.v:4024$494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4024$490_Y - connect \B $and$ls180.v:4024$493_Y - connect \Y $or$ls180.v:4024$494_Y - end - attribute \src "ls180.v:4087.36-4087.104" - cell $or $or$ls180.v:4087$528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_ready - connect \B $not$ls180.v:4087$527_Y - connect \Y $or$ls180.v:4087$528_Y - end - attribute \src "ls180.v:4108.67-4108.221" - cell $or $or$ls180.v:4108$535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4108$534_Y - connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:4108$535_Y - end - attribute \src "ls180.v:4116.10-4116.62" - cell $or $or$ls180.v:4116$538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4116$537_Y - connect \B \main_sdram_max_time1 - connect \Y $or$ls180.v:4116$538_Y - end - attribute \src "ls180.v:4146.67-4146.221" - cell $or $or$ls180.v:4146$544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4146$543_Y - connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:4146$544_Y - end - attribute \src "ls180.v:4154.10-4154.61" - cell $or $or$ls180.v:4154$547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4154$546_Y - connect \B \main_sdram_max_time0 - connect \Y $or$ls180.v:4154$547_Y - end - attribute \src "ls180.v:4164.91-4164.180" - cell $or $or$ls180.v:4164$551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:4164$550_Y - connect \Y $or$ls180.v:4164$551_Y - end - attribute \src "ls180.v:4164.90-4164.255" - cell $or $or$ls180.v:4164$554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4164$551_Y - connect \B $and$ls180.v:4164$553_Y - connect \Y $or$ls180.v:4164$554_Y - end - attribute \src "ls180.v:4164.89-4164.330" - cell $or $or$ls180.v:4164$557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4164$554_Y - connect \B $and$ls180.v:4164$556_Y - connect \Y $or$ls180.v:4164$557_Y - end - attribute \src "ls180.v:4169.91-4169.180" - cell $or $or$ls180.v:4169$567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:4169$566_Y - connect \Y $or$ls180.v:4169$567_Y - end - attribute \src "ls180.v:4169.90-4169.255" - cell $or $or$ls180.v:4169$570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4169$567_Y - connect \B $and$ls180.v:4169$569_Y - connect \Y $or$ls180.v:4169$570_Y - end - attribute \src "ls180.v:4169.89-4169.330" - cell $or $or$ls180.v:4169$573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4169$570_Y - connect \B $and$ls180.v:4169$572_Y - connect \Y $or$ls180.v:4169$573_Y - end - attribute \src "ls180.v:4174.91-4174.180" - cell $or $or$ls180.v:4174$583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:4174$582_Y - connect \Y $or$ls180.v:4174$583_Y - end - attribute \src "ls180.v:4174.90-4174.255" - cell $or $or$ls180.v:4174$586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4174$583_Y - connect \B $and$ls180.v:4174$585_Y - connect \Y $or$ls180.v:4174$586_Y - end - attribute \src "ls180.v:4174.89-4174.330" - cell $or $or$ls180.v:4174$589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4174$586_Y - connect \B $and$ls180.v:4174$588_Y - connect \Y $or$ls180.v:4174$589_Y - end - attribute \src "ls180.v:4179.91-4179.180" - cell $or $or$ls180.v:4179$599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:4179$598_Y - connect \Y $or$ls180.v:4179$599_Y - end - attribute \src "ls180.v:4179.90-4179.255" - cell $or $or$ls180.v:4179$602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4179$599_Y - connect \B $and$ls180.v:4179$601_Y - connect \Y $or$ls180.v:4179$602_Y - end - attribute \src "ls180.v:4179.89-4179.330" - cell $or $or$ls180.v:4179$605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4179$602_Y - connect \B $and$ls180.v:4179$604_Y - connect \Y $or$ls180.v:4179$605_Y - end - attribute \src "ls180.v:4184.132-4184.221" - cell $or $or$ls180.v:4184$616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:4184$615_Y - connect \Y $or$ls180.v:4184$616_Y - end - attribute \src "ls180.v:4184.131-4184.296" - cell $or $or$ls180.v:4184$619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$616_Y - connect \B $and$ls180.v:4184$618_Y - connect \Y $or$ls180.v:4184$619_Y - end - attribute \src "ls180.v:4184.130-4184.371" - cell $or $or$ls180.v:4184$622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$619_Y - connect \B $and$ls180.v:4184$621_Y - connect \Y $or$ls180.v:4184$622_Y - end - attribute \src "ls180.v:4184.34-4184.411" - cell $or $or$ls180.v:4184$627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:4184$626_Y - connect \Y $or$ls180.v:4184$627_Y - end - attribute \src "ls180.v:4184.506-4184.595" - cell $or $or$ls180.v:4184$632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:4184$631_Y - connect \Y $or$ls180.v:4184$632_Y - end - attribute \src "ls180.v:4184.505-4184.670" - cell $or $or$ls180.v:4184$635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$632_Y - connect \B $and$ls180.v:4184$634_Y - connect \Y $or$ls180.v:4184$635_Y - end - attribute \src "ls180.v:4184.504-4184.745" - cell $or $or$ls180.v:4184$638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$635_Y - connect \B $and$ls180.v:4184$637_Y - connect \Y $or$ls180.v:4184$638_Y - end - attribute \src "ls180.v:4184.33-4184.785" - cell $or $or$ls180.v:4184$643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$627_Y - connect \B $and$ls180.v:4184$642_Y - connect \Y $or$ls180.v:4184$643_Y - end - attribute \src "ls180.v:4184.880-4184.969" - cell $or $or$ls180.v:4184$648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:4184$647_Y - connect \Y $or$ls180.v:4184$648_Y - end - attribute \src "ls180.v:4184.879-4184.1044" - cell $or $or$ls180.v:4184$651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$648_Y - connect \B $and$ls180.v:4184$650_Y - connect \Y $or$ls180.v:4184$651_Y - end - attribute \src "ls180.v:4184.878-4184.1119" - cell $or $or$ls180.v:4184$654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$651_Y - connect \B $and$ls180.v:4184$653_Y - connect \Y $or$ls180.v:4184$654_Y - end - attribute \src "ls180.v:4184.32-4184.1159" - cell $or $or$ls180.v:4184$659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$643_Y - connect \B $and$ls180.v:4184$658_Y - connect \Y $or$ls180.v:4184$659_Y - end - attribute \src "ls180.v:4184.1254-4184.1343" - cell $or $or$ls180.v:4184$664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:4184$663_Y - connect \Y $or$ls180.v:4184$664_Y - end - attribute \src "ls180.v:4184.1253-4184.1418" - cell $or $or$ls180.v:4184$667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$664_Y - connect \B $and$ls180.v:4184$666_Y - connect \Y $or$ls180.v:4184$667_Y - end - attribute \src "ls180.v:4184.1252-4184.1493" - cell $or $or$ls180.v:4184$670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$667_Y - connect \B $and$ls180.v:4184$669_Y - connect \Y $or$ls180.v:4184$670_Y - end - attribute \src "ls180.v:4184.31-4184.1533" - cell $or $or$ls180.v:4184$675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$659_Y - connect \B $and$ls180.v:4184$674_Y - connect \Y $or$ls180.v:4184$675_Y - end - attribute \src "ls180.v:4247.10-4247.52" - cell $or $or$ls180.v:4247$684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_ack - connect \B \main_converter_skip - connect \Y $or$ls180.v:4247$684_Y - end - attribute \src "ls180.v:4274.35-4274.74" - cell $or $or$ls180.v:4274$694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4274$694_Y - end - attribute \src "ls180.v:4275.34-4275.73" - cell $or $or$ls180.v:4275$698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4275$698_Y - end - attribute \src "ls180.v:4276.48-4276.130" - cell $or $or$ls180.v:4276$704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4276$701_Y - connect \B $and$ls180.v:4276$703_Y - connect \Y $or$ls180.v:4276$704_Y - end - attribute \src "ls180.v:4277.24-4277.87" - cell $or $or$ls180.v:4277$707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4277$706_Y - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4277$707_Y - end - attribute \src "ls180.v:4278.26-4278.95" - cell $or $or$ls180.v:4278$709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4278$708_Y - connect \B \main_wdata_consumed - connect \Y $or$ls180.v:4278$709_Y - end - attribute \src "ls180.v:4308.42-4308.89" - cell $or $or$ls180.v:4308$717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_clear - connect \B $and$ls180.v:4308$716_Y - connect \Y $or$ls180.v:4308$717_Y - end - attribute \src "ls180.v:4332.25-4332.174" - cell $or $or$ls180.v:4332$727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4332$725_Y - connect \B $and$ls180.v:4332$726_Y - connect \Y $or$ls180.v:4332$727_Y - end - attribute \src "ls180.v:4347.80-4347.132" - cell $or $or$ls180.v:4347$729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4347$728_Y - connect \B \main_uart_tx_fifo_re - connect \Y $or$ls180.v:4347$729_Y - end - attribute \src "ls180.v:4358.72-4358.135" - cell $or $or$ls180.v:4358$734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_writable - connect \B \main_uart_tx_fifo_replace - connect \Y $or$ls180.v:4358$734_Y - end - attribute \src "ls180.v:4377.80-4377.132" - cell $or $or$ls180.v:4377$740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4377$739_Y - connect \B \main_uart_rx_fifo_re - connect \Y $or$ls180.v:4377$740_Y - end - attribute \src "ls180.v:4388.72-4388.135" - cell $or $or$ls180.v:4388$745 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_writable - connect \B \main_uart_rx_fifo_replace - connect \Y $or$ls180.v:4388$745_Y - end - attribute \src "ls180.v:4533.36-4533.111" - cell $or $or$ls180.v:4533$768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_clk - connect \B \main_sdphy_cmdw_pads_out_payload_clk - connect \Y $or$ls180.v:4533$768_Y - end - attribute \src "ls180.v:4533.35-4533.151" - cell $or $or$ls180.v:4533$769 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4533$768_Y - connect \B \main_sdphy_cmdr_pads_out_payload_clk - connect \Y $or$ls180.v:4533$769_Y - end - attribute \src "ls180.v:4533.34-4533.192" - cell $or $or$ls180.v:4533$770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4533$769_Y - connect \B \main_sdphy_dataw_pads_out_payload_clk - connect \Y $or$ls180.v:4533$770_Y - end - attribute \src "ls180.v:4533.33-4533.233" - cell $or $or$ls180.v:4533$771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4533$770_Y - connect \B \main_sdphy_datar_pads_out_payload_clk - connect \Y $or$ls180.v:4533$771_Y - end - attribute \src "ls180.v:4534.39-4534.120" - cell $or $or$ls180.v:4534$772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_cmd_oe - connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4534$772_Y - end - attribute \src "ls180.v:4534.38-4534.163" - cell $or $or$ls180.v:4534$773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4534$772_Y - connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4534$773_Y - end - attribute \src "ls180.v:4534.37-4534.207" - cell $or $or$ls180.v:4534$774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4534$773_Y - connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4534$774_Y - end - attribute \src "ls180.v:4534.36-4534.251" - cell $or $or$ls180.v:4534$775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4534$774_Y - connect \B \main_sdphy_datar_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4534$775_Y - end - attribute \src "ls180.v:4535.38-4535.117" - cell $or $or$ls180.v:4535$776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_cmd_o - connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4535$776_Y - end - attribute \src "ls180.v:4535.37-4535.159" - cell $or $or$ls180.v:4535$777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4535$776_Y - connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4535$777_Y - end - attribute \src "ls180.v:4535.36-4535.202" - cell $or $or$ls180.v:4535$778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4535$777_Y - connect \B \main_sdphy_dataw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4535$778_Y - end - attribute \src "ls180.v:4535.35-4535.245" - cell $or $or$ls180.v:4535$779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4535$778_Y - connect \B \main_sdphy_datar_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4535$779_Y - end - attribute \src "ls180.v:4536.40-4536.123" - cell $or $or$ls180.v:4536$780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_data_oe - connect \B \main_sdphy_cmdw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4536$780_Y - end - attribute \src "ls180.v:4536.39-4536.167" - cell $or $or$ls180.v:4536$781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4536$780_Y - connect \B \main_sdphy_cmdr_pads_out_payload_data_oe - connect \Y $or$ls180.v:4536$781_Y - end - attribute \src "ls180.v:4536.38-4536.212" - cell $or $or$ls180.v:4536$782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4536$781_Y - connect \B \main_sdphy_dataw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4536$782_Y - end - attribute \src "ls180.v:4536.37-4536.257" - cell $or $or$ls180.v:4536$783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4536$782_Y - connect \B \main_sdphy_datar_pads_out_payload_data_oe - connect \Y $or$ls180.v:4536$783_Y - end - attribute \src "ls180.v:4537.39-4537.120" - cell $or $or$ls180.v:4537$784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_init_pads_out_payload_data_o - connect \B \main_sdphy_cmdw_pads_out_payload_data_o - connect \Y $or$ls180.v:4537$784_Y - end - attribute \src "ls180.v:4537.38-4537.163" - cell $or $or$ls180.v:4537$785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4537$784_Y - connect \B \main_sdphy_cmdr_pads_out_payload_data_o - connect \Y $or$ls180.v:4537$785_Y - end - attribute \src "ls180.v:4537.37-4537.207" - cell $or $or$ls180.v:4537$786 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4537$785_Y - connect \B \main_sdphy_dataw_pads_out_payload_data_o - connect \Y $or$ls180.v:4537$786_Y - end - attribute \src "ls180.v:4537.36-4537.251" - cell $or $or$ls180.v:4537$787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4537$786_Y - connect \B \main_sdphy_datar_pads_out_payload_data_o - connect \Y $or$ls180.v:4537$787_Y - end - attribute \src "ls180.v:4558.35-4558.80" - cell $or $or$ls180.v:4558$788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_stop - connect \B \main_sdphy_datar_stop - connect \Y $or$ls180.v:4558$788_Y - end - attribute \src "ls180.v:4712.91-4712.144" - cell $or $or$ls180.v:4712$802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_start - connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:4712$802_Y - end - attribute \src "ls180.v:4729.53-4729.143" - cell $or $or$ls180.v:4729$805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4729$804_Y - connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $or$ls180.v:4729$805_Y - end - attribute \src "ls180.v:4732.47-4732.127" - cell $or $or$ls180.v:4732$808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4732$807_Y - connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:4732$808_Y - end - attribute \src "ls180.v:4856.54-4856.146" - cell $or $or$ls180.v:4856$826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4856$825_Y - connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $or$ls180.v:4856$826_Y - end - attribute \src "ls180.v:4859.48-4859.130" - cell $or $or$ls180.v:4859$829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4859$828_Y - connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:4859$829_Y - end - attribute \src "ls180.v:4990.55-4990.149" - cell $or $or$ls180.v:4990$841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4990$840_Y - connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $or$ls180.v:4990$841_Y - end - attribute \src "ls180.v:4993.49-4993.133" - cell $or $or$ls180.v:4993$844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4993$843_Y - connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:4993$844_Y - end - attribute \src "ls180.v:5622.80-5622.151" - cell $or $or$ls180.v:5622$1139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_writable - connect \B \main_sdblock2mem_fifo_replace - connect \Y $or$ls180.v:5622$1139_Y - end - attribute \src "ls180.v:5633.49-5633.131" - cell $or $or$ls180.v:5633$1145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:5633$1144_Y - connect \B \main_sdblock2mem_converter_source_ready - connect \Y $or$ls180.v:5633$1145_Y - end - attribute \src "ls180.v:5842.80-5842.151" - cell $or $or$ls180.v:5842$1170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_writable - connect \B \main_sdmem2block_fifo_replace - connect \Y $or$ls180.v:5842$1170_Y - end - attribute \src "ls180.v:6029.41-6029.99" - cell $or $or$ls180.v:6029$1226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_err - connect \B \main_interface0_ram_bus_err - connect \Y $or$ls180.v:6029$1226_Y - end - attribute \src "ls180.v:6029.40-6029.130" - cell $or $or$ls180.v:6029$1227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1226_Y - connect \B \main_interface1_ram_bus_err - connect \Y $or$ls180.v:6029$1227_Y - end - attribute \src "ls180.v:6029.39-6029.161" - cell $or $or$ls180.v:6029$1228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1227_Y - connect \B \main_interface2_ram_bus_err - connect \Y $or$ls180.v:6029$1228_Y - end - attribute \src "ls180.v:6029.38-6029.192" - cell $or $or$ls180.v:6029$1229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1228_Y - connect \B \main_interface3_ram_bus_err - connect \Y $or$ls180.v:6029$1229_Y - end - attribute \src "ls180.v:6029.37-6029.235" - cell $or $or$ls180.v:6029$1230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1229_Y - connect \B \main_interface0_converted_interface_err - connect \Y $or$ls180.v:6029$1230_Y - end - attribute \src "ls180.v:6029.36-6029.278" - cell $or $or$ls180.v:6029$1231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1230_Y - connect \B \main_interface1_converted_interface_err - connect \Y $or$ls180.v:6029$1231_Y - end - attribute \src "ls180.v:6029.35-6029.322" - cell $or $or$ls180.v:6029$1232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1231_Y - connect \B \main_libresocsim_libresoc_interface0_err - connect \Y $or$ls180.v:6029$1232_Y - end - attribute \src "ls180.v:6029.34-6029.366" - cell $or $or$ls180.v:6029$1233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1232_Y - connect \B \main_libresocsim_libresoc_interface1_err - connect \Y $or$ls180.v:6029$1233_Y - end - attribute \src "ls180.v:6029.33-6029.410" - cell $or $or$ls180.v:6029$1234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1233_Y - connect \B \main_libresocsim_libresoc_interface2_err - connect \Y $or$ls180.v:6029$1234_Y - end - attribute \src "ls180.v:6029.32-6029.454" - cell $or $or$ls180.v:6029$1235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1234_Y - connect \B \main_libresocsim_libresoc_interface3_err - connect \Y $or$ls180.v:6029$1235_Y - end - attribute \src "ls180.v:6029.31-6029.500" - cell $or $or$ls180.v:6029$1236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1235_Y - connect \B \main_socbushandler_converted_interface_err - connect \Y $or$ls180.v:6029$1236_Y - end - attribute \src "ls180.v:6029.30-6029.547" - cell $or $or$ls180.v:6029$1237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1236_Y - connect \B \builder_libresocsim_converted_interface_err - connect \Y $or$ls180.v:6029$1237_Y - end - attribute \src "ls180.v:6035.36-6035.94" - cell $or $or$ls180.v:6035$1242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_ack - connect \B \main_interface0_ram_bus_ack - connect \Y $or$ls180.v:6035$1242_Y - end - attribute \src "ls180.v:6035.35-6035.125" - cell $or $or$ls180.v:6035$1243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1242_Y - connect \B \main_interface1_ram_bus_ack - connect \Y $or$ls180.v:6035$1243_Y - end - attribute \src "ls180.v:6035.34-6035.156" - cell $or $or$ls180.v:6035$1244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1243_Y - connect \B \main_interface2_ram_bus_ack - connect \Y $or$ls180.v:6035$1244_Y - end - attribute \src "ls180.v:6035.33-6035.187" - cell $or $or$ls180.v:6035$1245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1244_Y - connect \B \main_interface3_ram_bus_ack - connect \Y $or$ls180.v:6035$1245_Y - end - attribute \src "ls180.v:6035.32-6035.230" - cell $or $or$ls180.v:6035$1246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1245_Y - connect \B \main_interface0_converted_interface_ack - connect \Y $or$ls180.v:6035$1246_Y - end - attribute \src "ls180.v:6035.31-6035.273" - cell $or $or$ls180.v:6035$1247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1246_Y - connect \B \main_interface1_converted_interface_ack - connect \Y $or$ls180.v:6035$1247_Y - end - attribute \src "ls180.v:6035.30-6035.317" - cell $or $or$ls180.v:6035$1248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1247_Y - connect \B \main_libresocsim_libresoc_interface0_ack - connect \Y $or$ls180.v:6035$1248_Y - end - attribute \src "ls180.v:6035.29-6035.361" - cell $or $or$ls180.v:6035$1249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1248_Y - connect \B \main_libresocsim_libresoc_interface1_ack - connect \Y $or$ls180.v:6035$1249_Y - end - attribute \src "ls180.v:6035.28-6035.405" - cell $or $or$ls180.v:6035$1250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1249_Y - connect \B \main_libresocsim_libresoc_interface2_ack - connect \Y $or$ls180.v:6035$1250_Y - end - attribute \src "ls180.v:6035.27-6035.449" - cell $or $or$ls180.v:6035$1251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1250_Y - connect \B \main_libresocsim_libresoc_interface3_ack - connect \Y $or$ls180.v:6035$1251_Y - end - attribute \src "ls180.v:6035.26-6035.495" - cell $or $or$ls180.v:6035$1252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1251_Y - connect \B \main_socbushandler_converted_interface_ack - connect \Y $or$ls180.v:6035$1252_Y - end - attribute \src "ls180.v:6035.25-6035.542" - cell $or $or$ls180.v:6035$1253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1252_Y - connect \B \builder_libresocsim_converted_interface_ack - connect \Y $or$ls180.v:6035$1253_Y - end - attribute \src "ls180.v:6036.38-6036.166" - cell $or $or$ls180.v:6036$1256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $and$ls180.v:6036$1254_Y - connect \B $and$ls180.v:6036$1255_Y - connect \Y $or$ls180.v:6036$1256_Y - end - attribute \src "ls180.v:6036.37-6036.232" - cell $or $or$ls180.v:6036$1258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1256_Y - connect \B $and$ls180.v:6036$1257_Y - connect \Y $or$ls180.v:6036$1258_Y - end - attribute \src "ls180.v:6036.36-6036.298" - cell $or $or$ls180.v:6036$1260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1258_Y - connect \B $and$ls180.v:6036$1259_Y - connect \Y $or$ls180.v:6036$1260_Y - end - attribute \src "ls180.v:6036.35-6036.364" - cell $or $or$ls180.v:6036$1262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1260_Y - connect \B $and$ls180.v:6036$1261_Y - connect \Y $or$ls180.v:6036$1262_Y - end - attribute \src "ls180.v:6036.34-6036.442" - cell $or $or$ls180.v:6036$1264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1262_Y - connect \B $and$ls180.v:6036$1263_Y - connect \Y $or$ls180.v:6036$1264_Y - end - attribute \src "ls180.v:6036.33-6036.520" - cell $or $or$ls180.v:6036$1266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1264_Y - connect \B $and$ls180.v:6036$1265_Y - connect \Y $or$ls180.v:6036$1266_Y - end - attribute \src "ls180.v:6036.32-6036.599" - cell $or $or$ls180.v:6036$1268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1266_Y - connect \B $and$ls180.v:6036$1267_Y - connect \Y $or$ls180.v:6036$1268_Y - end - attribute \src "ls180.v:6036.31-6036.678" - cell $or $or$ls180.v:6036$1270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1268_Y - connect \B $and$ls180.v:6036$1269_Y - connect \Y $or$ls180.v:6036$1270_Y - end - attribute \src "ls180.v:6036.30-6036.757" - cell $or $or$ls180.v:6036$1272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1270_Y - connect \B $and$ls180.v:6036$1271_Y - connect \Y $or$ls180.v:6036$1272_Y - end - attribute \src "ls180.v:6036.29-6036.837" - cell $or $or$ls180.v:6036$1274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1272_Y - connect \B $and$ls180.v:6036$1273_Y - connect \Y $or$ls180.v:6036$1274_Y - end - attribute \src "ls180.v:6036.28-6036.919" - cell $or $or$ls180.v:6036$1276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1274_Y - connect \B $and$ls180.v:6036$1275_Y - connect \Y $or$ls180.v:6036$1276_Y - end - attribute \src "ls180.v:6036.27-6036.1002" - cell $or $or$ls180.v:6036$1278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1276_Y - connect \B $and$ls180.v:6036$1277_Y - connect \Y $or$ls180.v:6036$1278_Y - end - attribute \src "ls180.v:6790.55-6790.124" - cell $or $or$ls180.v:6790$2424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \builder_interface0_bank_bus_dat_r - connect \B \builder_interface1_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2424_Y - end - attribute \src "ls180.v:6790.54-6790.161" - cell $or $or$ls180.v:6790$2425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2424_Y - connect \B \builder_interface2_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2425_Y - end - attribute \src "ls180.v:6790.53-6790.198" - cell $or $or$ls180.v:6790$2426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2425_Y - connect \B \builder_interface3_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2426_Y - end - attribute \src "ls180.v:6790.52-6790.235" - cell $or $or$ls180.v:6790$2427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2426_Y - connect \B \builder_interface4_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2427_Y - end - attribute \src "ls180.v:6790.51-6790.272" - cell $or $or$ls180.v:6790$2428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2427_Y - connect \B \builder_interface5_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2428_Y - end - attribute \src "ls180.v:6790.50-6790.309" - cell $or $or$ls180.v:6790$2429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2428_Y - connect \B \builder_interface6_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2429_Y - end - attribute \src "ls180.v:6790.49-6790.346" - cell $or $or$ls180.v:6790$2430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2429_Y - connect \B \builder_interface7_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2430_Y - end - attribute \src "ls180.v:6790.48-6790.383" - cell $or $or$ls180.v:6790$2431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2430_Y - connect \B \builder_interface8_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2431_Y - end - attribute \src "ls180.v:6790.47-6790.420" - cell $or $or$ls180.v:6790$2432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2431_Y - connect \B \builder_interface9_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2432_Y - end - attribute \src "ls180.v:6790.46-6790.458" - cell $or $or$ls180.v:6790$2433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2432_Y - connect \B \builder_interface10_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2433_Y - end - attribute \src "ls180.v:6790.45-6790.496" - cell $or $or$ls180.v:6790$2434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2433_Y - connect \B \builder_interface11_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2434_Y - end - attribute \src "ls180.v:6790.44-6790.534" - cell $or $or$ls180.v:6790$2435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2434_Y - connect \B \builder_interface12_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2435_Y - end - attribute \src "ls180.v:6790.43-6790.572" - cell $or $or$ls180.v:6790$2436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2435_Y - connect \B \builder_interface13_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2436_Y - end - attribute \src "ls180.v:6790.42-6790.610" - cell $or $or$ls180.v:6790$2437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2436_Y - connect \B \builder_interface14_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2437_Y - end - attribute \src "ls180.v:7117.90-7117.179" - cell $or $or$ls180.v:7117$2462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:7117$2461_Y - connect \Y $or$ls180.v:7117$2462_Y - end - attribute \src "ls180.v:7117.89-7117.254" - cell $or $or$ls180.v:7117$2465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7117$2462_Y - connect \B $and$ls180.v:7117$2464_Y - connect \Y $or$ls180.v:7117$2465_Y - end - attribute \src "ls180.v:7117.88-7117.329" - cell $or $or$ls180.v:7117$2468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7117$2465_Y - connect \B $and$ls180.v:7117$2467_Y - connect \Y $or$ls180.v:7117$2468_Y - end - attribute \src "ls180.v:7141.90-7141.179" - cell $or $or$ls180.v:7141$2478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:7141$2477_Y - connect \Y $or$ls180.v:7141$2478_Y - end - attribute \src "ls180.v:7141.89-7141.254" - cell $or $or$ls180.v:7141$2481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7141$2478_Y - connect \B $and$ls180.v:7141$2480_Y - connect \Y $or$ls180.v:7141$2481_Y - end - attribute \src "ls180.v:7141.88-7141.329" - cell $or $or$ls180.v:7141$2484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7141$2481_Y - connect \B $and$ls180.v:7141$2483_Y - connect \Y $or$ls180.v:7141$2484_Y - end - attribute \src "ls180.v:7165.90-7165.179" - cell $or $or$ls180.v:7165$2494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:7165$2493_Y - connect \Y $or$ls180.v:7165$2494_Y - end - attribute \src "ls180.v:7165.89-7165.254" - cell $or $or$ls180.v:7165$2497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7165$2494_Y - connect \B $and$ls180.v:7165$2496_Y - connect \Y $or$ls180.v:7165$2497_Y - end - attribute \src "ls180.v:7165.88-7165.329" - cell $or $or$ls180.v:7165$2500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7165$2497_Y - connect \B $and$ls180.v:7165$2499_Y - connect \Y $or$ls180.v:7165$2500_Y - end - attribute \src "ls180.v:7189.90-7189.179" - cell $or $or$ls180.v:7189$2510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:7189$2509_Y - connect \Y $or$ls180.v:7189$2510_Y - end - attribute \src "ls180.v:7189.89-7189.254" - cell $or $or$ls180.v:7189$2513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7189$2510_Y - connect \B $and$ls180.v:7189$2512_Y - connect \Y $or$ls180.v:7189$2513_Y - end - attribute \src "ls180.v:7189.88-7189.329" - cell $or $or$ls180.v:7189$2516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7189$2513_Y - connect \B $and$ls180.v:7189$2515_Y - connect \Y $or$ls180.v:7189$2516_Y - end - attribute \src "ls180.v:7706.20-7706.71" - cell $or $or$ls180.v:7706$2576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [0] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7706$2576_Y - end - attribute \src "ls180.v:7707.20-7707.71" - cell $or $or$ls180.v:7707$2577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [1] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7707$2577_Y - end - attribute \src "ls180.v:7708.20-7708.71" - cell $or $or$ls180.v:7708$2578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [2] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7708$2578_Y - end - attribute \src "ls180.v:7709.20-7709.71" - cell $or $or$ls180.v:7709$2579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [3] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7709$2579_Y - end - attribute \src "ls180.v:7710.20-7710.71" - cell $or $or$ls180.v:7710$2580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [4] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7710$2580_Y - end - attribute \src "ls180.v:7711.20-7711.71" - cell $or $or$ls180.v:7711$2581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [5] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7711$2581_Y - end - attribute \src "ls180.v:7712.20-7712.71" - cell $or $or$ls180.v:7712$2582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [6] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7712$2582_Y - end - attribute \src "ls180.v:7713.20-7713.71" - cell $or $or$ls180.v:7713$2583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [7] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7713$2583_Y - end - attribute \src "ls180.v:7714.20-7714.71" - cell $or $or$ls180.v:7714$2584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [8] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7714$2584_Y - end - attribute \src "ls180.v:7715.20-7715.71" - cell $or $or$ls180.v:7715$2585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [9] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7715$2585_Y - end - attribute \src "ls180.v:7716.21-7716.73" - cell $or $or$ls180.v:7716$2586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [10] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7716$2586_Y - end - attribute \src "ls180.v:7717.21-7717.73" - cell $or $or$ls180.v:7717$2587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [11] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7717$2587_Y - end - attribute \src "ls180.v:7718.21-7718.73" - cell $or $or$ls180.v:7718$2588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [12] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7718$2588_Y - end - attribute \src "ls180.v:7719.21-7719.73" - cell $or $or$ls180.v:7719$2589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [13] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7719$2589_Y - end - attribute \src "ls180.v:7720.21-7720.73" - cell $or $or$ls180.v:7720$2590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [14] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7720$2590_Y - end - attribute \src "ls180.v:7721.21-7721.73" - cell $or $or$ls180.v:7721$2591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [15] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7721$2591_Y - end - attribute \src "ls180.v:7722.21-7722.73" - cell $or $or$ls180.v:7722$2592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [16] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7722$2592_Y - end - attribute \src "ls180.v:7723.21-7723.73" - cell $or $or$ls180.v:7723$2593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [17] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7723$2593_Y - end - attribute \src "ls180.v:7724.21-7724.73" - cell $or $or$ls180.v:7724$2594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [18] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7724$2594_Y - end - attribute \src "ls180.v:7725.21-7725.73" - cell $or $or$ls180.v:7725$2595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [19] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7725$2595_Y - end - attribute \src "ls180.v:7726.21-7726.73" - cell $or $or$ls180.v:7726$2596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [20] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7726$2596_Y - end - attribute \src "ls180.v:7727.21-7727.73" - cell $or $or$ls180.v:7727$2597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [21] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7727$2597_Y - end - attribute \src "ls180.v:7728.21-7728.73" - cell $or $or$ls180.v:7728$2598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [22] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7728$2598_Y - end - attribute \src "ls180.v:7729.21-7729.73" - cell $or $or$ls180.v:7729$2599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [23] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7729$2599_Y - end - attribute \src "ls180.v:7730.7-7730.68" - cell $or $or$ls180.v:7730$2600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_icp_ack - connect \B \main_converter0_skip - connect \Y $or$ls180.v:7730$2600_Y - end - attribute \src "ls180.v:7741.7-7741.68" - cell $or $or$ls180.v:7741$2601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_ics_ack - connect \B \main_converter1_skip - connect \Y $or$ls180.v:7741$2601_Y - end - attribute \src "ls180.v:7752.7-7752.50" - cell $or $or$ls180.v:7752$2602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_ack - connect \B \main_socbushandler_skip - connect \Y $or$ls180.v:7752$2602_Y - end - attribute \src "ls180.v:7897.7-7897.107" - cell $or $or$ls180.v:7897$2650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7897$2649_Y - connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7897$2650_Y - end - attribute \src "ls180.v:7943.7-7943.107" - cell $or $or$ls180.v:7943$2666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7943$2665_Y - connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7943$2666_Y - end - attribute \src "ls180.v:7989.7-7989.107" - cell $or $or$ls180.v:7989$2682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7989$2681_Y - connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7989$2682_Y - end - attribute \src "ls180.v:8035.7-8035.107" - cell $or $or$ls180.v:8035$2698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8035$2697_Y - connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:8035$2698_Y - end - attribute \src "ls180.v:8223.40-8223.125" - cell $or $or$ls180.v:8223$2719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:8223$2718_Y - connect \Y $or$ls180.v:8223$2719_Y - end - attribute \src "ls180.v:8223.39-8223.207" - cell $or $or$ls180.v:8223$2722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8223$2719_Y - connect \B $and$ls180.v:8223$2721_Y - connect \Y $or$ls180.v:8223$2722_Y - end - attribute \src "ls180.v:8223.38-8223.289" - cell $or $or$ls180.v:8223$2725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8223$2722_Y - connect \B $and$ls180.v:8223$2724_Y - connect \Y $or$ls180.v:8223$2725_Y - end - attribute \src "ls180.v:8223.37-8223.371" - cell $or $or$ls180.v:8223$2728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8223$2725_Y - connect \B $and$ls180.v:8223$2727_Y - connect \Y $or$ls180.v:8223$2728_Y - end - attribute \src "ls180.v:8224.41-8224.126" - cell $or $or$ls180.v:8224$2731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:8224$2730_Y - connect \Y $or$ls180.v:8224$2731_Y - end - attribute \src "ls180.v:8224.40-8224.208" - cell $or $or$ls180.v:8224$2734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8224$2731_Y - connect \B $and$ls180.v:8224$2733_Y - connect \Y $or$ls180.v:8224$2734_Y - end - attribute \src "ls180.v:8224.39-8224.290" - cell $or $or$ls180.v:8224$2737 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8224$2734_Y - connect \B $and$ls180.v:8224$2736_Y - connect \Y $or$ls180.v:8224$2737_Y - end - attribute \src "ls180.v:8224.38-8224.372" - cell $or $or$ls180.v:8224$2740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8224$2737_Y - connect \B $and$ls180.v:8224$2739_Y - connect \Y $or$ls180.v:8224$2740_Y - end - attribute \src "ls180.v:8228.7-8228.49" - cell $or $or$ls180.v:8228$2741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_ack - connect \B \main_converter_skip - connect \Y $or$ls180.v:8228$2741_Y - end - attribute \src "ls180.v:8391.21-8391.74" - cell $or $or$ls180.v:8391$2789 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8391$2787_Y - connect \B $not$ls180.v:8391$2788_Y - connect \Y $or$ls180.v:8391$2789_Y - end - attribute \src "ls180.v:8426.21-8426.71" - cell $or $or$ls180.v:8426$2794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8426$2792_Y - connect \B $not$ls180.v:8426$2793_Y - connect \Y $or$ls180.v:8426$2794_Y - end - attribute \src "ls180.v:8494.32-8494.85" - cell $or $or$ls180.v:8494$2806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_start - connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:8494$2806_Y - end - attribute \src "ls180.v:8500.8-8500.97" - cell $or $or$ls180.v:8500$2808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8500$2807_Y - connect \B \main_sdphy_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:8500$2808_Y - end - attribute \src "ls180.v:8517.52-8517.139" - cell $or $or$ls180.v:8517$2813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_first - connect \B \main_sdphy_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:8517$2813_Y - end - attribute \src "ls180.v:8518.51-8518.136" - cell $or $or$ls180.v:8518$2814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_last - connect \B \main_sdphy_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:8518$2814_Y - end - attribute \src "ls180.v:8552.7-8552.87" - cell $or $or$ls180.v:8552$2817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8552$2816_Y - connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:8552$2817_Y - end - attribute \src "ls180.v:8575.33-8575.88" - cell $or $or$ls180.v:8575$2818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_start - connect \B \main_sdphy_dataw_crcr_run - connect \Y $or$ls180.v:8575$2818_Y - end - attribute \src "ls180.v:8581.8-8581.99" - cell $or $or$ls180.v:8581$2820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8581$2819_Y - connect \B \main_sdphy_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:8581$2820_Y - end - attribute \src "ls180.v:8598.53-8598.142" - cell $or $or$ls180.v:8598$2825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_first - connect \B \main_sdphy_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:8598$2825_Y - end - attribute \src "ls180.v:8599.52-8599.139" - cell $or $or$ls180.v:8599$2826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_last - connect \B \main_sdphy_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:8599$2826_Y - end - attribute \src "ls180.v:8633.7-8633.89" - cell $or $or$ls180.v:8633$2829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8633$2828_Y - connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:8633$2829_Y - end - attribute \src "ls180.v:8654.34-8654.91" - cell $or $or$ls180.v:8654$2830 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_start - connect \B \main_sdphy_datar_datar_run - connect \Y $or$ls180.v:8654$2830_Y - end - attribute \src "ls180.v:8660.8-8660.101" - cell $or $or$ls180.v:8660$2832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8660$2831_Y - connect \B \main_sdphy_datar_datar_converter_sink_last - connect \Y $or$ls180.v:8660$2832_Y - end - attribute \src "ls180.v:8677.54-8677.145" - cell $or $or$ls180.v:8677$2837 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_first - connect \B \main_sdphy_datar_datar_converter_source_first - connect \Y $or$ls180.v:8677$2837_Y - end - attribute \src "ls180.v:8678.53-8678.142" - cell $or $or$ls180.v:8678$2838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_last - connect \B \main_sdphy_datar_datar_converter_source_last - connect \Y $or$ls180.v:8678$2838_Y - end - attribute \src "ls180.v:8694.7-8694.91" - cell $or $or$ls180.v:8694$2841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8694$2840_Y - connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:8694$2841_Y - end - attribute \src "ls180.v:8883.8-8883.89" - cell $or $or$ls180.v:8883$2865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8883$2864_Y - connect \B \main_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8883$2865_Y - end - attribute \src "ls180.v:8900.48-8900.127" - cell $or $or$ls180.v:8900$2870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_first - connect \B \main_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8900$2870_Y - end - attribute \src "ls180.v:8901.47-8901.124" - cell $or $or$ls180.v:8901$2871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_last - connect \B \main_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8901$2871_Y - end - attribute \src "ls180.v:3358.46-3358.94" - cell $sshl $sshl$ls180.v:3358$231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine0_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3358$231_Y - end - attribute \src "ls180.v:3515.46-3515.94" - cell $sshl $sshl$ls180.v:3515$261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine1_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3515$261_Y - end - attribute \src "ls180.v:3672.46-3672.94" - cell $sshl $sshl$ls180.v:3672$291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine2_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3672$291_Y - end - attribute \src "ls180.v:3829.46-3829.94" - cell $sshl $sshl$ls180.v:3829$321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine3_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3829$321_Y - end - attribute \src "ls180.v:3389.63-3389.122" - cell $sub $sub$ls180.v:3389$244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3389$244_Y - end - attribute \src "ls180.v:3546.63-3546.122" - cell $sub $sub$ls180.v:3546$274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3546$274_Y - end - attribute \src "ls180.v:3703.63-3703.122" - cell $sub $sub$ls180.v:3703$304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3703$304_Y - end - attribute \src "ls180.v:3860.63-3860.122" - cell $sub $sub$ls180.v:3860$334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3860$334_Y - end - attribute \src "ls180.v:4266.38-4266.75" - cell $sub $sub$ls180.v:4266$688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 30 - parameter \B_SIGNED 0 - parameter \B_WIDTH 31 - parameter \Y_WIDTH 31 - connect \A \main_litedram_wb_adr - connect \B 31'1001000000000000000000000000000 - connect \Y $sub$ls180.v:4266$688_Y - end - attribute \src "ls180.v:4352.36-4352.68" - cell $sub $sub$ls180.v:4352$733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:4352$733_Y - end - attribute \src "ls180.v:4382.36-4382.68" - cell $sub $sub$ls180.v:4382$744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:4382$744_Y - end - attribute \src "ls180.v:4418.70-4418.110" - cell $sub $sub$ls180.v:4418$752 - parameter \A_SIGNED 0 - parameter \A_WIDTH 15 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spimaster8_clk_divider [15:1] - connect \B 1'1 - connect \Y $sub$ls180.v:4418$752_Y - end - attribute \src "ls180.v:4419.70-4419.104" - cell $sub $sub$ls180.v:4419$754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spimaster8_clk_divider - connect \B 1'1 - connect \Y $sub$ls180.v:4419$754_Y - end - attribute \src "ls180.v:4446.37-4446.66" - cell $sub $sub$ls180.v:4446$758 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_spimaster1_length - connect \B 1'1 - connect \Y $sub$ls180.v:4446$758_Y - end - attribute \src "ls180.v:4476.67-4476.107" - cell $sub $sub$ls180.v:4476$760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 15 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spisdcard_clk_divider0 [15:1] - connect \B 1'1 - connect \Y $sub$ls180.v:4476$760_Y - end - attribute \src "ls180.v:4477.67-4477.101" - cell $sub $sub$ls180.v:4477$762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spisdcard_clk_divider0 - connect \B 1'1 - connect \Y $sub$ls180.v:4477$762_Y - end - attribute \src "ls180.v:4505.35-4505.64" - cell $sub $sub$ls180.v:4505$766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_spisdcard_length0 - connect \B 1'1 - connect \Y $sub$ls180.v:4505$766_Y - end - attribute \src "ls180.v:4759.60-4759.90" - cell $sub $sub$ls180.v:4759$810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4759$810_Y - end - attribute \src "ls180.v:4770.62-4770.104" - cell $sub $sub$ls180.v:4770$812 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_sink_payload_length - connect \B 1'1 - connect \Y $sub$ls180.v:4770$812_Y - end - attribute \src "ls180.v:4787.60-4787.90" - cell $sub $sub$ls180.v:4787$816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4787$816_Y - end - attribute \src "ls180.v:5016.62-5016.93" - cell $sub $sub$ls180.v:5016$846 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:5016$846_Y - end - attribute \src "ls180.v:5021.62-5021.93" - cell $sub $sub$ls180.v:5021$847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:5021$847_Y - end - attribute \src "ls180.v:5032.64-5032.122" - cell $sub $sub$ls180.v:5032$850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A $add$ls180.v:5032$849_Y - connect \B 1'1 - connect \Y $sub$ls180.v:5032$850_Y - end - attribute \src "ls180.v:5053.62-5053.93" - cell $sub $sub$ls180.v:5053$853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:5053$853_Y - end - attribute \src "ls180.v:5515.37-5515.75" - cell $sub $sub$ls180.v:5515$1126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5515$1126_Y - end - attribute \src "ls180.v:5530.62-5530.100" - cell $sub $sub$ls180.v:5530$1129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5530$1129_Y - end - attribute \src "ls180.v:5541.39-5541.77" - cell $sub $sub$ls180.v:5541$1134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5541$1134_Y - end - attribute \src "ls180.v:5616.40-5616.76" - cell $sub $sub$ls180.v:5616$1138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:5616$1138_Y - end - attribute \src "ls180.v:5665.56-5665.104" - cell $sub $sub$ls180.v:5665$1152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_length - connect \B 1'1 - connect \Y $sub$ls180.v:5665$1152_Y - end - attribute \src "ls180.v:5755.71-5755.105" - cell $sub $sub$ls180.v:5755$1158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_length - connect \B 1'1 - connect \Y $sub$ls180.v:5755$1158_Y - end - attribute \src "ls180.v:5836.40-5836.76" - cell $sub $sub$ls180.v:5836$1169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:5836$1169_Y - end - attribute \src "ls180.v:7776.31-7776.60" - cell $sub $sub$ls180.v:7776$2609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_libresocsim_value - connect \B 1'1 - connect \Y $sub$ls180.v:7776$2609_Y - end - attribute \src "ls180.v:7813.31-7813.61" - cell $sub $sub$ls180.v:7813$2626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdram_timer_count1 - connect \B 1'1 - connect \Y $sub$ls180.v:7813$2626_Y - end - attribute \src "ls180.v:7819.34-7819.67" - cell $sub $sub$ls180.v:7819$2627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_postponer_count - connect \B 1'1 - connect \Y $sub$ls180.v:7819$2627_Y - end - attribute \src "ls180.v:7830.36-7830.69" - cell $sub $sub$ls180.v:7830$2630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'1 - connect \Y $sub$ls180.v:7830$2630_Y - end - attribute \src "ls180.v:7894.59-7894.116" - cell $sub $sub$ls180.v:7894$2648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7894$2648_Y - end - attribute \src "ls180.v:7913.46-7913.90" - cell $sub $sub$ls180.v:7913$2652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7913$2652_Y - end - attribute \src "ls180.v:7940.59-7940.116" - cell $sub $sub$ls180.v:7940$2664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7940$2664_Y - end - attribute \src "ls180.v:7959.46-7959.90" - cell $sub $sub$ls180.v:7959$2668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7959$2668_Y - end - attribute \src "ls180.v:7986.59-7986.116" - cell $sub $sub$ls180.v:7986$2680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7986$2680_Y - end - attribute \src "ls180.v:8005.46-8005.90" - cell $sub $sub$ls180.v:8005$2684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:8005$2684_Y - end - attribute \src "ls180.v:8032.59-8032.116" - cell $sub $sub$ls180.v:8032$2696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:8032$2696_Y - end - attribute \src "ls180.v:8051.46-8051.90" - cell $sub $sub$ls180.v:8051$2700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:8051$2700_Y - end - attribute \src "ls180.v:8062.25-8062.48" - cell $sub $sub$ls180.v:8062$2704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdram_time0 - connect \B 1'1 - connect \Y $sub$ls180.v:8062$2704_Y - end - attribute \src "ls180.v:8069.25-8069.48" - cell $sub $sub$ls180.v:8069$2707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_time1 - connect \B 1'1 - connect \Y $sub$ls180.v:8069$2707_Y - end - attribute \src "ls180.v:8201.33-8201.64" - cell $sub $sub$ls180.v:8201$2712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:8201$2712_Y - end - attribute \src "ls180.v:8216.33-8216.64" - cell $sub $sub$ls180.v:8216$2715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_twtrcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:8216$2715_Y - end - attribute \src "ls180.v:8343.33-8343.64" - cell $sub $sub$ls180.v:8343$2774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 - connect \B 1'1 - connect \Y $sub$ls180.v:8343$2774_Y - end - attribute \src "ls180.v:8365.33-8365.64" - cell $sub $sub$ls180.v:8365$2785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 - connect \B 1'1 - connect \Y $sub$ls180.v:8365$2785_Y - end - attribute \src "ls180.v:8400.34-8400.66" - cell $sub $sub$ls180.v:8400$2790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spimaster34_mosi_sel - connect \B 1'1 - connect \Y $sub$ls180.v:8400$2790_Y - end - attribute \src "ls180.v:8435.32-8435.62" - cell $sub $sub$ls180.v:8435$2795 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spisdcard_mosi_sel - connect \B 1'1 - connect \Y $sub$ls180.v:8435$2795_Y - end - attribute \src "ls180.v:8459.30-8459.53" - cell $sub $sub$ls180.v:8459$2798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm0_period - connect \B 1'1 - connect \Y $sub$ls180.v:8459$2798_Y - end - attribute \src "ls180.v:8473.30-8473.53" - cell $sub $sub$ls180.v:8473$2802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm1_period - connect \B 1'1 - connect \Y $sub$ls180.v:8473$2802_Y - end - attribute \src "ls180.v:8876.36-8876.70" - cell $sub $sub$ls180.v:8876$2863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'1 - connect \Y $sub$ls180.v:8876$2863_Y - end - attribute \src "ls180.v:8974.36-8974.70" - cell $sub $sub$ls180.v:8974$2885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdmem2block_fifo_level - connect \B 1'1 - connect \Y $sub$ls180.v:8974$2885_Y - end - attribute \src "ls180.v:9087.22-9087.42" - cell $sub $sub$ls180.v:9087$2892 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 20 - connect \A \builder_count - connect \B 1'1 - connect \Y $sub$ls180.v:9087$2892_Y - end - attribute \src "ls180.v:5113.353-5113.425" - cell $xor $xor$ls180.v:5113$860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [39] - connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:5113$860_Y - end - attribute \src "ls180.v:5113.200-5113.272" - cell $xor $xor$ls180.v:5113$861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [39] - connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:5113$861_Y - end - attribute \src "ls180.v:5113.160-5113.273" - cell $xor $xor$ls180.v:5113$862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg0 [2] - connect \B $xor$ls180.v:5113$861_Y - connect \Y $xor$ls180.v:5113$862_Y - end - attribute \src "ls180.v:5114.353-5114.425" - cell $xor $xor$ls180.v:5114$863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [38] - connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:5114$863_Y - end - attribute \src "ls180.v:5114.200-5114.272" - cell $xor $xor$ls180.v:5114$864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [38] - connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:5114$864_Y - end - attribute \src "ls180.v:5114.160-5114.273" - cell $xor $xor$ls180.v:5114$865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg1 [2] - connect \B $xor$ls180.v:5114$864_Y - connect \Y $xor$ls180.v:5114$865_Y - end - attribute \src "ls180.v:5115.353-5115.425" - cell $xor $xor$ls180.v:5115$866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [37] - connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:5115$866_Y - end - attribute \src "ls180.v:5115.200-5115.272" - cell $xor $xor$ls180.v:5115$867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [37] - connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:5115$867_Y - end - attribute \src "ls180.v:5115.160-5115.273" - cell $xor $xor$ls180.v:5115$868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg2 [2] - connect \B $xor$ls180.v:5115$867_Y - connect \Y $xor$ls180.v:5115$868_Y - end - attribute \src "ls180.v:5116.353-5116.425" - cell $xor $xor$ls180.v:5116$869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [36] - connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:5116$869_Y - end - attribute \src "ls180.v:5116.200-5116.272" - cell $xor $xor$ls180.v:5116$870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [36] - connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:5116$870_Y - end - attribute \src "ls180.v:5116.160-5116.273" - cell $xor $xor$ls180.v:5116$871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg3 [2] - connect \B $xor$ls180.v:5116$870_Y - connect \Y $xor$ls180.v:5116$871_Y - end - attribute \src "ls180.v:5117.353-5117.425" - cell $xor $xor$ls180.v:5117$872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [35] - connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:5117$872_Y - end - attribute \src "ls180.v:5117.200-5117.272" - cell $xor $xor$ls180.v:5117$873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [35] - connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:5117$873_Y - end - attribute \src "ls180.v:5117.160-5117.273" - cell $xor $xor$ls180.v:5117$874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg4 [2] - connect \B $xor$ls180.v:5117$873_Y - connect \Y $xor$ls180.v:5117$874_Y - end - attribute \src "ls180.v:5118.353-5118.425" - cell $xor $xor$ls180.v:5118$875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [34] - connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:5118$875_Y - end - attribute \src "ls180.v:5118.200-5118.272" - cell $xor $xor$ls180.v:5118$876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [34] - connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:5118$876_Y - end - attribute \src "ls180.v:5118.160-5118.273" - cell $xor $xor$ls180.v:5118$877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg5 [2] - connect \B $xor$ls180.v:5118$876_Y - connect \Y $xor$ls180.v:5118$877_Y - end - attribute \src "ls180.v:5119.353-5119.425" - cell $xor $xor$ls180.v:5119$878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [33] - connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:5119$878_Y - end - attribute \src "ls180.v:5119.200-5119.272" - cell $xor $xor$ls180.v:5119$879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [33] - connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:5119$879_Y - end - attribute \src "ls180.v:5119.160-5119.273" - cell $xor $xor$ls180.v:5119$880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg6 [2] - connect \B $xor$ls180.v:5119$879_Y - connect \Y $xor$ls180.v:5119$880_Y - end - attribute \src "ls180.v:5120.353-5120.425" - cell $xor $xor$ls180.v:5120$881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [32] - connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:5120$881_Y - end - attribute \src "ls180.v:5120.200-5120.272" - cell $xor $xor$ls180.v:5120$882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [32] - connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:5120$882_Y - end - attribute \src "ls180.v:5120.160-5120.273" - cell $xor $xor$ls180.v:5120$883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg7 [2] - connect \B $xor$ls180.v:5120$882_Y - connect \Y $xor$ls180.v:5120$883_Y - end - attribute \src "ls180.v:5121.353-5121.425" - cell $xor $xor$ls180.v:5121$884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [31] - connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:5121$884_Y - end - attribute \src "ls180.v:5121.200-5121.272" - cell $xor $xor$ls180.v:5121$885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [31] - connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:5121$885_Y - end - attribute \src "ls180.v:5121.160-5121.273" - cell $xor $xor$ls180.v:5121$886 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg8 [2] - connect \B $xor$ls180.v:5121$885_Y - connect \Y $xor$ls180.v:5121$886_Y - end - attribute \src "ls180.v:5122.354-5122.426" - cell $xor $xor$ls180.v:5122$887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [30] - connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:5122$887_Y - end - attribute \src "ls180.v:5122.201-5122.273" - cell $xor $xor$ls180.v:5122$888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [30] - connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:5122$888_Y - end - attribute \src "ls180.v:5122.161-5122.274" - cell $xor $xor$ls180.v:5122$889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg9 [2] - connect \B $xor$ls180.v:5122$888_Y - connect \Y $xor$ls180.v:5122$889_Y - end - attribute \src "ls180.v:5123.361-5123.434" - cell $xor $xor$ls180.v:5123$890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [29] - connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:5123$890_Y - end - attribute \src "ls180.v:5123.205-5123.278" - cell $xor $xor$ls180.v:5123$891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [29] - connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:5123$891_Y - end - attribute \src "ls180.v:5123.164-5123.279" - cell $xor $xor$ls180.v:5123$892 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg10 [2] - connect \B $xor$ls180.v:5123$891_Y - connect \Y $xor$ls180.v:5123$892_Y - end - attribute \src "ls180.v:5124.361-5124.434" - cell $xor $xor$ls180.v:5124$893 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [28] - connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:5124$893_Y - end - attribute \src "ls180.v:5124.205-5124.278" - cell $xor $xor$ls180.v:5124$894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [28] - connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:5124$894_Y - end - attribute \src "ls180.v:5124.164-5124.279" - cell $xor $xor$ls180.v:5124$895 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg11 [2] - connect \B $xor$ls180.v:5124$894_Y - connect \Y $xor$ls180.v:5124$895_Y - end - attribute \src "ls180.v:5125.361-5125.434" - cell $xor $xor$ls180.v:5125$896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [27] - connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:5125$896_Y - end - attribute \src "ls180.v:5125.205-5125.278" - cell $xor $xor$ls180.v:5125$897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [27] - connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:5125$897_Y - end - attribute \src "ls180.v:5125.164-5125.279" - cell $xor $xor$ls180.v:5125$898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg12 [2] - connect \B $xor$ls180.v:5125$897_Y - connect \Y $xor$ls180.v:5125$898_Y - end - attribute \src "ls180.v:5126.361-5126.434" - cell $xor $xor$ls180.v:5126$899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [26] - connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:5126$899_Y - end - attribute \src "ls180.v:5126.205-5126.278" - cell $xor $xor$ls180.v:5126$900 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [26] - connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:5126$900_Y - end - attribute \src "ls180.v:5126.164-5126.279" - cell $xor $xor$ls180.v:5126$901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg13 [2] - connect \B $xor$ls180.v:5126$900_Y - connect \Y $xor$ls180.v:5126$901_Y - end - attribute \src "ls180.v:5127.361-5127.434" - cell $xor $xor$ls180.v:5127$902 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [25] - connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:5127$902_Y - end - attribute \src "ls180.v:5127.205-5127.278" - cell $xor $xor$ls180.v:5127$903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [25] - connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:5127$903_Y - end - attribute \src "ls180.v:5127.164-5127.279" - cell $xor $xor$ls180.v:5127$904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg14 [2] - connect \B $xor$ls180.v:5127$903_Y - connect \Y $xor$ls180.v:5127$904_Y - end - attribute \src "ls180.v:5128.361-5128.434" - cell $xor $xor$ls180.v:5128$905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [24] - connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:5128$905_Y - end - attribute \src "ls180.v:5128.205-5128.278" - cell $xor $xor$ls180.v:5128$906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [24] - connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:5128$906_Y - end - attribute \src "ls180.v:5128.164-5128.279" - cell $xor $xor$ls180.v:5128$907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg15 [2] - connect \B $xor$ls180.v:5128$906_Y - connect \Y $xor$ls180.v:5128$907_Y - end - attribute \src "ls180.v:5129.361-5129.434" - cell $xor $xor$ls180.v:5129$908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [23] - connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:5129$908_Y - end - attribute \src "ls180.v:5129.205-5129.278" - cell $xor $xor$ls180.v:5129$909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [23] - connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:5129$909_Y - end - attribute \src "ls180.v:5129.164-5129.279" - cell $xor $xor$ls180.v:5129$910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg16 [2] - connect \B $xor$ls180.v:5129$909_Y - connect \Y $xor$ls180.v:5129$910_Y - end - attribute \src "ls180.v:5130.361-5130.434" - cell $xor $xor$ls180.v:5130$911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [22] - connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:5130$911_Y - end - attribute \src "ls180.v:5130.205-5130.278" - cell $xor $xor$ls180.v:5130$912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [22] - connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:5130$912_Y - end - attribute \src "ls180.v:5130.164-5130.279" - cell $xor $xor$ls180.v:5130$913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg17 [2] - connect \B $xor$ls180.v:5130$912_Y - connect \Y $xor$ls180.v:5130$913_Y - end - attribute \src "ls180.v:5131.361-5131.434" - cell $xor $xor$ls180.v:5131$914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [21] - connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:5131$914_Y - end - attribute \src "ls180.v:5131.205-5131.278" - cell $xor $xor$ls180.v:5131$915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [21] - connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:5131$915_Y - end - attribute \src "ls180.v:5131.164-5131.279" - cell $xor $xor$ls180.v:5131$916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg18 [2] - connect \B $xor$ls180.v:5131$915_Y - connect \Y $xor$ls180.v:5131$916_Y - end - attribute \src "ls180.v:5132.361-5132.434" - cell $xor $xor$ls180.v:5132$917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [20] - connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:5132$917_Y - end - attribute \src "ls180.v:5132.205-5132.278" - cell $xor $xor$ls180.v:5132$918 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [20] - connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:5132$918_Y - end - attribute \src "ls180.v:5132.164-5132.279" - cell $xor $xor$ls180.v:5132$919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg19 [2] - connect \B $xor$ls180.v:5132$918_Y - connect \Y $xor$ls180.v:5132$919_Y - end - attribute \src "ls180.v:5133.361-5133.434" - cell $xor $xor$ls180.v:5133$920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [19] - connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:5133$920_Y - end - attribute \src "ls180.v:5133.205-5133.278" - cell $xor $xor$ls180.v:5133$921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [19] - connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:5133$921_Y - end - attribute \src "ls180.v:5133.164-5133.279" - cell $xor $xor$ls180.v:5133$922 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg20 [2] - connect \B $xor$ls180.v:5133$921_Y - connect \Y $xor$ls180.v:5133$922_Y - end - attribute \src "ls180.v:5134.361-5134.434" - cell $xor $xor$ls180.v:5134$923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [18] - connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:5134$923_Y - end - attribute \src "ls180.v:5134.205-5134.278" - cell $xor $xor$ls180.v:5134$924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [18] - connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:5134$924_Y - end - attribute \src "ls180.v:5134.164-5134.279" - cell $xor $xor$ls180.v:5134$925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg21 [2] - connect \B $xor$ls180.v:5134$924_Y - connect \Y $xor$ls180.v:5134$925_Y - end - attribute \src "ls180.v:5135.361-5135.434" - cell $xor $xor$ls180.v:5135$926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [17] - connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:5135$926_Y - end - attribute \src "ls180.v:5135.205-5135.278" - cell $xor $xor$ls180.v:5135$927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [17] - connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:5135$927_Y - end - attribute \src "ls180.v:5135.164-5135.279" - cell $xor $xor$ls180.v:5135$928 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg22 [2] - connect \B $xor$ls180.v:5135$927_Y - connect \Y $xor$ls180.v:5135$928_Y - end - attribute \src "ls180.v:5136.361-5136.434" - cell $xor $xor$ls180.v:5136$929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [16] - connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:5136$929_Y - end - attribute \src "ls180.v:5136.205-5136.278" - cell $xor $xor$ls180.v:5136$930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [16] - connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:5136$930_Y - end - attribute \src "ls180.v:5136.164-5136.279" - cell $xor $xor$ls180.v:5136$931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg23 [2] - connect \B $xor$ls180.v:5136$930_Y - connect \Y $xor$ls180.v:5136$931_Y - end - attribute \src "ls180.v:5137.361-5137.434" - cell $xor $xor$ls180.v:5137$932 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [15] - connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:5137$932_Y - end - attribute \src "ls180.v:5137.205-5137.278" - cell $xor $xor$ls180.v:5137$933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [15] - connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:5137$933_Y - end - attribute \src "ls180.v:5137.164-5137.279" - cell $xor $xor$ls180.v:5137$934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg24 [2] - connect \B $xor$ls180.v:5137$933_Y - connect \Y $xor$ls180.v:5137$934_Y - end - attribute \src "ls180.v:5138.361-5138.434" - cell $xor $xor$ls180.v:5138$935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [14] - connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:5138$935_Y - end - attribute \src "ls180.v:5138.205-5138.278" - cell $xor $xor$ls180.v:5138$936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [14] - connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:5138$936_Y - end - attribute \src "ls180.v:5138.164-5138.279" - cell $xor $xor$ls180.v:5138$937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg25 [2] - connect \B $xor$ls180.v:5138$936_Y - connect \Y $xor$ls180.v:5138$937_Y - end - attribute \src "ls180.v:5139.361-5139.434" - cell $xor $xor$ls180.v:5139$938 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [13] - connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:5139$938_Y - end - attribute \src "ls180.v:5139.205-5139.278" - cell $xor $xor$ls180.v:5139$939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [13] - connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:5139$939_Y - end - attribute \src "ls180.v:5139.164-5139.279" - cell $xor $xor$ls180.v:5139$940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg26 [2] - connect \B $xor$ls180.v:5139$939_Y - connect \Y $xor$ls180.v:5139$940_Y - end - attribute \src "ls180.v:5140.361-5140.434" - cell $xor $xor$ls180.v:5140$941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [12] - connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:5140$941_Y - end - attribute \src "ls180.v:5140.205-5140.278" - cell $xor $xor$ls180.v:5140$942 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [12] - connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:5140$942_Y - end - attribute \src "ls180.v:5140.164-5140.279" - cell $xor $xor$ls180.v:5140$943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg27 [2] - connect \B $xor$ls180.v:5140$942_Y - connect \Y $xor$ls180.v:5140$943_Y - end - attribute \src "ls180.v:5141.361-5141.434" - cell $xor $xor$ls180.v:5141$944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [11] - connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:5141$944_Y - end - attribute \src "ls180.v:5141.205-5141.278" - cell $xor $xor$ls180.v:5141$945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [11] - connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:5141$945_Y - end - attribute \src "ls180.v:5141.164-5141.279" - cell $xor $xor$ls180.v:5141$946 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg28 [2] - connect \B $xor$ls180.v:5141$945_Y - connect \Y $xor$ls180.v:5141$946_Y - end - attribute \src "ls180.v:5142.361-5142.434" - cell $xor $xor$ls180.v:5142$947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [10] - connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:5142$947_Y - end - attribute \src "ls180.v:5142.205-5142.278" - cell $xor $xor$ls180.v:5142$948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [10] - connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:5142$948_Y - end - attribute \src "ls180.v:5142.164-5142.279" - cell $xor $xor$ls180.v:5142$949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg29 [2] - connect \B $xor$ls180.v:5142$948_Y - connect \Y $xor$ls180.v:5142$949_Y - end - attribute \src "ls180.v:5143.360-5143.432" - cell $xor $xor$ls180.v:5143$950 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [9] - connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:5143$950_Y - end - attribute \src "ls180.v:5143.205-5143.277" - cell $xor $xor$ls180.v:5143$951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [9] - connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:5143$951_Y - end - attribute \src "ls180.v:5143.164-5143.278" - cell $xor $xor$ls180.v:5143$952 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg30 [2] - connect \B $xor$ls180.v:5143$951_Y - connect \Y $xor$ls180.v:5143$952_Y - end - attribute \src "ls180.v:5144.360-5144.432" - cell $xor $xor$ls180.v:5144$953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [8] - connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:5144$953_Y - end - attribute \src "ls180.v:5144.205-5144.277" - cell $xor $xor$ls180.v:5144$954 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [8] - connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:5144$954_Y - end - attribute \src "ls180.v:5144.164-5144.278" - cell $xor $xor$ls180.v:5144$955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg31 [2] - connect \B $xor$ls180.v:5144$954_Y - connect \Y $xor$ls180.v:5144$955_Y - end - attribute \src "ls180.v:5145.360-5145.432" - cell $xor $xor$ls180.v:5145$956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [7] - connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:5145$956_Y - end - attribute \src "ls180.v:5145.205-5145.277" - cell $xor $xor$ls180.v:5145$957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [7] - connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:5145$957_Y - end - attribute \src "ls180.v:5145.164-5145.278" - cell $xor $xor$ls180.v:5145$958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg32 [2] - connect \B $xor$ls180.v:5145$957_Y - connect \Y $xor$ls180.v:5145$958_Y - end - attribute \src "ls180.v:5146.360-5146.432" - cell $xor $xor$ls180.v:5146$959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [6] - connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:5146$959_Y - end - attribute \src "ls180.v:5146.205-5146.277" - cell $xor $xor$ls180.v:5146$960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [6] - connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:5146$960_Y - end - attribute \src "ls180.v:5146.164-5146.278" - cell $xor $xor$ls180.v:5146$961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg33 [2] - connect \B $xor$ls180.v:5146$960_Y - connect \Y $xor$ls180.v:5146$961_Y - end - attribute \src "ls180.v:5147.360-5147.432" - cell $xor $xor$ls180.v:5147$962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [5] - connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:5147$962_Y - end - attribute \src "ls180.v:5147.205-5147.277" - cell $xor $xor$ls180.v:5147$963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [5] - connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:5147$963_Y - end - attribute \src "ls180.v:5147.164-5147.278" - cell $xor $xor$ls180.v:5147$964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg34 [2] - connect \B $xor$ls180.v:5147$963_Y - connect \Y $xor$ls180.v:5147$964_Y - end - attribute \src "ls180.v:5148.360-5148.432" - cell $xor $xor$ls180.v:5148$965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [4] - connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:5148$965_Y - end - attribute \src "ls180.v:5148.205-5148.277" - cell $xor $xor$ls180.v:5148$966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [4] - connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:5148$966_Y - end - attribute \src "ls180.v:5148.164-5148.278" - cell $xor $xor$ls180.v:5148$967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg35 [2] - connect \B $xor$ls180.v:5148$966_Y - connect \Y $xor$ls180.v:5148$967_Y - end - attribute \src "ls180.v:5149.360-5149.432" - cell $xor $xor$ls180.v:5149$968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [3] - connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:5149$968_Y - end - attribute \src "ls180.v:5149.205-5149.277" - cell $xor $xor$ls180.v:5149$969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [3] - connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:5149$969_Y - end - attribute \src "ls180.v:5149.164-5149.278" - cell $xor $xor$ls180.v:5149$970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg36 [2] - connect \B $xor$ls180.v:5149$969_Y - connect \Y $xor$ls180.v:5149$970_Y - end - attribute \src "ls180.v:5150.360-5150.432" - cell $xor $xor$ls180.v:5150$971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [2] - connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:5150$971_Y - end - attribute \src "ls180.v:5150.205-5150.277" - cell $xor $xor$ls180.v:5150$972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [2] - connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:5150$972_Y - end - attribute \src "ls180.v:5150.164-5150.278" - cell $xor $xor$ls180.v:5150$973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg37 [2] - connect \B $xor$ls180.v:5150$972_Y - connect \Y $xor$ls180.v:5150$973_Y - end - attribute \src "ls180.v:5151.360-5151.432" - cell $xor $xor$ls180.v:5151$974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [1] - connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:5151$974_Y - end - attribute \src "ls180.v:5151.205-5151.277" - cell $xor $xor$ls180.v:5151$975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [1] - connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:5151$975_Y - end - attribute \src "ls180.v:5151.164-5151.278" - cell $xor $xor$ls180.v:5151$976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg38 [2] - connect \B $xor$ls180.v:5151$975_Y - connect \Y $xor$ls180.v:5151$976_Y - end - attribute \src "ls180.v:5152.360-5152.432" - cell $xor $xor$ls180.v:5152$977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [0] - connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:5152$977_Y - end - attribute \src "ls180.v:5152.205-5152.277" - cell $xor $xor$ls180.v:5152$978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [0] - connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:5152$978_Y - end - attribute \src "ls180.v:5152.164-5152.278" - cell $xor $xor$ls180.v:5152$979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg39 [2] - connect \B $xor$ls180.v:5152$978_Y - connect \Y $xor$ls180.v:5152$979_Y - end - attribute \src "ls180.v:5173.899-5173.983" - cell $xor $xor$ls180.v:5173$993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5173$993_Y - end - attribute \src "ls180.v:5173.634-5173.718" - cell $xor $xor$ls180.v:5173$994 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5173$994_Y - end - attribute \src "ls180.v:5173.588-5173.719" - cell $xor $xor$ls180.v:5173$995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5173$994_Y - connect \Y $xor$ls180.v:5173$995_Y - end - attribute \src "ls180.v:5173.234-5173.318" - cell $xor $xor$ls180.v:5173$996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5173$996_Y - end - attribute \src "ls180.v:5173.187-5173.319" - cell $xor $xor$ls180.v:5173$997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5173$996_Y - connect \Y $xor$ls180.v:5173$997_Y - end - attribute \src "ls180.v:5174.588-5174.719" - cell $xor $xor$ls180.v:5174$1000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5174$999_Y - connect \Y $xor$ls180.v:5174$1000_Y - end - attribute \src "ls180.v:5174.234-5174.318" - cell $xor $xor$ls180.v:5174$1001 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5174$1001_Y - end - attribute \src "ls180.v:5174.187-5174.319" - cell $xor $xor$ls180.v:5174$1002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5174$1001_Y - connect \Y $xor$ls180.v:5174$1002_Y - end - attribute \src "ls180.v:5174.899-5174.983" - cell $xor $xor$ls180.v:5174$998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5174$998_Y - end - attribute \src "ls180.v:5174.634-5174.718" - cell $xor $xor$ls180.v:5174$999 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5174$999_Y - end - attribute \src "ls180.v:5183.899-5183.983" - cell $xor $xor$ls180.v:5183$1004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5183$1004_Y - end - attribute \src "ls180.v:5183.634-5183.718" - cell $xor $xor$ls180.v:5183$1005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5183$1005_Y - end - attribute \src "ls180.v:5183.588-5183.719" - cell $xor $xor$ls180.v:5183$1006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5183$1005_Y - connect \Y $xor$ls180.v:5183$1006_Y - end - attribute \src "ls180.v:5183.234-5183.318" - cell $xor $xor$ls180.v:5183$1007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5183$1007_Y - end - attribute \src "ls180.v:5183.187-5183.319" - cell $xor $xor$ls180.v:5183$1008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5183$1007_Y - connect \Y $xor$ls180.v:5183$1008_Y - end - attribute \src "ls180.v:5184.899-5184.983" - cell $xor $xor$ls180.v:5184$1009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5184$1009_Y - end - attribute \src "ls180.v:5184.634-5184.718" - cell $xor $xor$ls180.v:5184$1010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5184$1010_Y - end - attribute \src "ls180.v:5184.588-5184.719" - cell $xor $xor$ls180.v:5184$1011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5184$1010_Y - connect \Y $xor$ls180.v:5184$1011_Y - end - attribute \src "ls180.v:5184.234-5184.318" - cell $xor $xor$ls180.v:5184$1012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5184$1012_Y - end - attribute \src "ls180.v:5184.187-5184.319" - cell $xor $xor$ls180.v:5184$1013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5184$1012_Y - connect \Y $xor$ls180.v:5184$1013_Y - end - attribute \src "ls180.v:5193.899-5193.983" - cell $xor $xor$ls180.v:5193$1015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5193$1015_Y - end - attribute \src "ls180.v:5193.634-5193.718" - cell $xor $xor$ls180.v:5193$1016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5193$1016_Y - end - attribute \src "ls180.v:5193.588-5193.719" - cell $xor $xor$ls180.v:5193$1017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5193$1016_Y - connect \Y $xor$ls180.v:5193$1017_Y - end - attribute \src "ls180.v:5193.234-5193.318" - cell $xor $xor$ls180.v:5193$1018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5193$1018_Y - end - attribute \src "ls180.v:5193.187-5193.319" - cell $xor $xor$ls180.v:5193$1019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5193$1018_Y - connect \Y $xor$ls180.v:5193$1019_Y - end - attribute \src "ls180.v:5194.899-5194.983" - cell $xor $xor$ls180.v:5194$1020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5194$1020_Y - end - attribute \src "ls180.v:5194.634-5194.718" - cell $xor $xor$ls180.v:5194$1021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5194$1021_Y - end - attribute \src "ls180.v:5194.588-5194.719" - cell $xor $xor$ls180.v:5194$1022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5194$1021_Y - connect \Y $xor$ls180.v:5194$1022_Y - end - attribute \src "ls180.v:5194.234-5194.318" - cell $xor $xor$ls180.v:5194$1023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5194$1023_Y - end - attribute \src "ls180.v:5194.187-5194.319" - cell $xor $xor$ls180.v:5194$1024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5194$1023_Y - connect \Y $xor$ls180.v:5194$1024_Y - end - attribute \src "ls180.v:5203.899-5203.983" - cell $xor $xor$ls180.v:5203$1026 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5203$1026_Y - end - attribute \src "ls180.v:5203.634-5203.718" - cell $xor $xor$ls180.v:5203$1027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5203$1027_Y - end - attribute \src "ls180.v:5203.588-5203.719" - cell $xor $xor$ls180.v:5203$1028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5203$1027_Y - connect \Y $xor$ls180.v:5203$1028_Y - end - attribute \src "ls180.v:5203.234-5203.318" - cell $xor $xor$ls180.v:5203$1029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5203$1029_Y - end - attribute \src "ls180.v:5203.187-5203.319" - cell $xor $xor$ls180.v:5203$1030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5203$1029_Y - connect \Y $xor$ls180.v:5203$1030_Y - end - attribute \src "ls180.v:5204.899-5204.983" - cell $xor $xor$ls180.v:5204$1031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5204$1031_Y - end - attribute \src "ls180.v:5204.634-5204.718" - cell $xor $xor$ls180.v:5204$1032 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5204$1032_Y - end - attribute \src "ls180.v:5204.588-5204.719" - cell $xor $xor$ls180.v:5204$1033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5204$1032_Y - connect \Y $xor$ls180.v:5204$1033_Y - end - attribute \src "ls180.v:5204.234-5204.318" - cell $xor $xor$ls180.v:5204$1034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5204$1034_Y - end - attribute \src "ls180.v:5204.187-5204.319" - cell $xor $xor$ls180.v:5204$1035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5204$1034_Y - connect \Y $xor$ls180.v:5204$1035_Y - end - attribute \src "ls180.v:5355.879-5355.961" - cell $xor $xor$ls180.v:5355$1068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5355$1068_Y - end - attribute \src "ls180.v:5355.620-5355.702" - cell $xor $xor$ls180.v:5355$1069 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5355$1069_Y - end - attribute \src "ls180.v:5355.575-5355.703" - cell $xor $xor$ls180.v:5355$1070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5355$1069_Y - connect \Y $xor$ls180.v:5355$1070_Y - end - attribute \src "ls180.v:5355.229-5355.311" - cell $xor $xor$ls180.v:5355$1071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5355$1071_Y - end - attribute \src "ls180.v:5355.183-5355.312" - cell $xor $xor$ls180.v:5355$1072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5355$1071_Y - connect \Y $xor$ls180.v:5355$1072_Y - end - attribute \src "ls180.v:5356.879-5356.961" - cell $xor $xor$ls180.v:5356$1073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5356$1073_Y - end - attribute \src "ls180.v:5356.620-5356.702" - cell $xor $xor$ls180.v:5356$1074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5356$1074_Y - end - attribute \src "ls180.v:5356.575-5356.703" - cell $xor $xor$ls180.v:5356$1075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5356$1074_Y - connect \Y $xor$ls180.v:5356$1075_Y - end - attribute \src "ls180.v:5356.229-5356.311" - cell $xor $xor$ls180.v:5356$1076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5356$1076_Y - end - attribute \src "ls180.v:5356.183-5356.312" - cell $xor $xor$ls180.v:5356$1077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5356$1076_Y - connect \Y $xor$ls180.v:5356$1077_Y - end - attribute \src "ls180.v:5365.879-5365.961" - cell $xor $xor$ls180.v:5365$1079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5365$1079_Y - end - attribute \src "ls180.v:5365.620-5365.702" - cell $xor $xor$ls180.v:5365$1080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5365$1080_Y - end - attribute \src "ls180.v:5365.575-5365.703" - cell $xor $xor$ls180.v:5365$1081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5365$1080_Y - connect \Y $xor$ls180.v:5365$1081_Y - end - attribute \src "ls180.v:5365.229-5365.311" - cell $xor $xor$ls180.v:5365$1082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5365$1082_Y - end - attribute \src "ls180.v:5365.183-5365.312" - cell $xor $xor$ls180.v:5365$1083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5365$1082_Y - connect \Y $xor$ls180.v:5365$1083_Y - end - attribute \src "ls180.v:5366.879-5366.961" - cell $xor $xor$ls180.v:5366$1084 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5366$1084_Y - end - attribute \src "ls180.v:5366.620-5366.702" - cell $xor $xor$ls180.v:5366$1085 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5366$1085_Y - end - attribute \src "ls180.v:5366.575-5366.703" - cell $xor $xor$ls180.v:5366$1086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5366$1085_Y - connect \Y $xor$ls180.v:5366$1086_Y - end - attribute \src "ls180.v:5366.229-5366.311" - cell $xor $xor$ls180.v:5366$1087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5366$1087_Y - end - attribute \src "ls180.v:5366.183-5366.312" - cell $xor $xor$ls180.v:5366$1088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5366$1087_Y - connect \Y $xor$ls180.v:5366$1088_Y - end - attribute \src "ls180.v:5375.879-5375.961" - cell $xor $xor$ls180.v:5375$1090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5375$1090_Y - end - attribute \src "ls180.v:5375.620-5375.702" - cell $xor $xor$ls180.v:5375$1091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5375$1091_Y - end - attribute \src "ls180.v:5375.575-5375.703" - cell $xor $xor$ls180.v:5375$1092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5375$1091_Y - connect \Y $xor$ls180.v:5375$1092_Y - end - attribute \src "ls180.v:5375.229-5375.311" - cell $xor $xor$ls180.v:5375$1093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5375$1093_Y - end - attribute \src "ls180.v:5375.183-5375.312" - cell $xor $xor$ls180.v:5375$1094 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5375$1093_Y - connect \Y $xor$ls180.v:5375$1094_Y - end - attribute \src "ls180.v:5376.879-5376.961" - cell $xor $xor$ls180.v:5376$1095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5376$1095_Y - end - attribute \src "ls180.v:5376.620-5376.702" - cell $xor $xor$ls180.v:5376$1096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5376$1096_Y - end - attribute \src "ls180.v:5376.575-5376.703" - cell $xor $xor$ls180.v:5376$1097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5376$1096_Y - connect \Y $xor$ls180.v:5376$1097_Y - end - attribute \src "ls180.v:5376.229-5376.311" - cell $xor $xor$ls180.v:5376$1098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5376$1098_Y - end - attribute \src "ls180.v:5376.183-5376.312" - cell $xor $xor$ls180.v:5376$1099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5376$1098_Y - connect \Y $xor$ls180.v:5376$1099_Y - end - attribute \src "ls180.v:5385.879-5385.961" - cell $xor $xor$ls180.v:5385$1101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5385$1101_Y - end - attribute \src "ls180.v:5385.620-5385.702" - cell $xor $xor$ls180.v:5385$1102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5385$1102_Y - end - attribute \src "ls180.v:5385.575-5385.703" - cell $xor $xor$ls180.v:5385$1103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5385$1102_Y - connect \Y $xor$ls180.v:5385$1103_Y - end - attribute \src "ls180.v:5385.229-5385.311" - cell $xor $xor$ls180.v:5385$1104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5385$1104_Y - end - attribute \src "ls180.v:5385.183-5385.312" - cell $xor $xor$ls180.v:5385$1105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5385$1104_Y - connect \Y $xor$ls180.v:5385$1105_Y - end - attribute \src "ls180.v:5386.879-5386.961" - cell $xor $xor$ls180.v:5386$1106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5386$1106_Y - end - attribute \src "ls180.v:5386.620-5386.702" - cell $xor $xor$ls180.v:5386$1107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5386$1107_Y - end - attribute \src "ls180.v:5386.575-5386.703" - cell $xor $xor$ls180.v:5386$1108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5386$1107_Y - connect \Y $xor$ls180.v:5386$1108_Y - end - attribute \src "ls180.v:5386.229-5386.311" - cell $xor $xor$ls180.v:5386$1109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5386$1109_Y - end - attribute \src "ls180.v:5386.183-5386.312" - cell $xor $xor$ls180.v:5386$1110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5386$1109_Y - connect \Y $xor$ls180.v:5386$1110_Y - end - attribute \module_not_derived 1 - attribute \src "ls180.v:10609.13-11015.2" - cell \test_issuer \test_issuer - connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck - connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi - connect \TAP_bus__tdo \main_libresocsim_libresoc_jtag_tdo - connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms - connect \busy_o \main_libresocsim_libresoc0 - connect \clk \sys_clk_1 - connect \clk_sel_i \main_libresocsim_libresoc_clk_sel - connect \core_bigendian_i 1'0 - connect \dbus__ack \main_libresocsim_libresoc_dbus_ack - connect \dbus__adr \main_libresocsim_libresoc_dbus_adr - connect \dbus__bte 1'0 - connect \dbus__cti 1'0 - connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc - connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r - connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w - connect \dbus__err \main_libresocsim_libresoc_dbus_err - connect \dbus__sel \main_libresocsim_libresoc_dbus_sel - connect \dbus__stb \main_libresocsim_libresoc_dbus_stb - connect \dbus__we \main_libresocsim_libresoc_dbus_we - connect \eint_0__core__i \eint [0] - connect \eint_0__pad__i \eint_1 [0] - connect \eint_1__core__i \eint [1] - connect \eint_1__pad__i \eint_1 [1] - connect \eint_2__core__i \eint [2] - connect \eint_2__pad__i \eint_1 [2] - connect \gpio_e10__core__i \gpio_i [10] - connect \gpio_e10__core__o \gpio_o [10] - connect \gpio_e10__core__oe \gpio_oe [10] - connect \gpio_e10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [10] - connect \gpio_e10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [10] - connect \gpio_e10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [10] - connect \gpio_e11__core__i \gpio_i [11] - connect \gpio_e11__core__o \gpio_o [11] - connect \gpio_e11__core__oe \gpio_oe [11] - connect \gpio_e11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [11] - connect \gpio_e11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [11] - connect \gpio_e11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [11] - connect \gpio_e12__core__i \gpio_i [12] - connect \gpio_e12__core__o \gpio_o [12] - connect \gpio_e12__core__oe \gpio_oe [12] - connect \gpio_e12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [12] - connect \gpio_e12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [12] - connect \gpio_e12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [12] - connect \gpio_e13__core__i \gpio_i [13] - connect \gpio_e13__core__o \gpio_o [13] - connect \gpio_e13__core__oe \gpio_oe [13] - connect \gpio_e13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [13] - connect \gpio_e13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [13] - connect \gpio_e13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [13] - connect \gpio_e14__core__i \gpio_i [14] - connect \gpio_e14__core__o \gpio_o [14] - connect \gpio_e14__core__oe \gpio_oe [14] - connect \gpio_e14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [14] - connect \gpio_e14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [14] - connect \gpio_e14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [14] - connect \gpio_e15__core__i \gpio_i [15] - connect \gpio_e15__core__o \gpio_o [15] - connect \gpio_e15__core__oe \gpio_oe [15] - connect \gpio_e15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [15] - connect \gpio_e15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [15] - connect \gpio_e15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [15] - connect \gpio_e8__core__i \gpio_i [8] - connect \gpio_e8__core__o \gpio_o [8] - connect \gpio_e8__core__oe \gpio_oe [8] - connect \gpio_e8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [8] - connect \gpio_e8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [8] - connect \gpio_e8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [8] - connect \gpio_e9__core__i \gpio_i [9] - connect \gpio_e9__core__o \gpio_o [9] - connect \gpio_e9__core__oe \gpio_oe [9] - connect \gpio_e9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [9] - connect \gpio_e9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [9] - connect \gpio_e9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [9] - connect \gpio_s0__core__i \gpio_i [0] - connect \gpio_s0__core__o \gpio_o [0] - connect \gpio_s0__core__oe \gpio_oe [0] - connect \gpio_s0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [0] - connect \gpio_s0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [0] - connect \gpio_s0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [0] - connect \gpio_s1__core__i \gpio_i [1] - connect \gpio_s1__core__o \gpio_o [1] - connect \gpio_s1__core__oe \gpio_oe [1] - connect \gpio_s1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [1] - connect \gpio_s1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [1] - connect \gpio_s1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [1] - connect \gpio_s2__core__i \gpio_i [2] - connect \gpio_s2__core__o \gpio_o [2] - connect \gpio_s2__core__oe \gpio_oe [2] - connect \gpio_s2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [2] - connect \gpio_s2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [2] - connect \gpio_s2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [2] - connect \gpio_s3__core__i \gpio_i [3] - connect \gpio_s3__core__o \gpio_o [3] - connect \gpio_s3__core__oe \gpio_oe [3] - connect \gpio_s3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [3] - connect \gpio_s3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [3] - connect \gpio_s3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [3] - connect \gpio_s4__core__i \gpio_i [4] - connect \gpio_s4__core__o \gpio_o [4] - connect \gpio_s4__core__oe \gpio_oe [4] - connect \gpio_s4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [4] - connect \gpio_s4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [4] - connect \gpio_s4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [4] - connect \gpio_s5__core__i \gpio_i [5] - connect \gpio_s5__core__o \gpio_o [5] - connect \gpio_s5__core__oe \gpio_oe [5] - connect \gpio_s5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [5] - connect \gpio_s5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [5] - connect \gpio_s5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [5] - connect \gpio_s6__core__i \gpio_i [6] - connect \gpio_s6__core__o \gpio_o [6] - connect \gpio_s6__core__oe \gpio_oe [6] - connect \gpio_s6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [6] - connect \gpio_s6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [6] - connect \gpio_s6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [6] - connect \gpio_s7__core__i \gpio_i [7] - connect \gpio_s7__core__o \gpio_o [7] - connect \gpio_s7__core__oe \gpio_oe [7] - connect \gpio_s7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [7] - connect \gpio_s7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [7] - connect \gpio_s7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [7] - connect \ibus__ack \main_libresocsim_libresoc_ibus_ack - connect \ibus__adr \main_libresocsim_libresoc_ibus_adr - connect \ibus__bte 1'0 - connect \ibus__cti 1'0 - connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc - connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r - connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w - connect \ibus__err \main_libresocsim_libresoc_ibus_err - connect \ibus__sel \main_libresocsim_libresoc_ibus_sel - connect \ibus__stb \main_libresocsim_libresoc_ibus_stb - connect \ibus__we \main_libresocsim_libresoc_ibus_we - connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack - connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr - connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc - connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r - connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w - connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err - connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel - connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb - connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we - connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack - connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr - connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc - connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r - connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w - connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err - connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel - connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb - connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we - connect \int_level_i \main_libresocsim_libresoc_interrupt - connect \jtag_wb__ack \main_libresocsim_libresoc_jtag_wb_ack - connect \jtag_wb__adr \main_libresocsim_libresoc_jtag_wb_adr - connect \jtag_wb__cyc \main_libresocsim_libresoc_jtag_wb_cyc - connect \jtag_wb__dat_r \main_libresocsim_libresoc_jtag_wb_dat_r - connect \jtag_wb__dat_w \main_libresocsim_libresoc_jtag_wb_dat_w - connect \jtag_wb__err \main_libresocsim_libresoc_jtag_wb_err - connect \jtag_wb__sel \main_libresocsim_libresoc_jtag_wb_sel - connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb - connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we - connect \memerr_o \main_libresocsim_libresoc1 - connect \mspi0_clk__core__o \spimaster_clk - connect \mspi0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - connect \mspi0_cs_n__core__o \spimaster_cs_n - connect \mspi0_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - connect \mspi0_miso__core__i \spimaster_miso - connect \mspi0_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - connect \mspi0_mosi__core__o \spimaster_mosi - connect \mspi0_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - connect \mspi1_clk__core__o \spisdcard_clk - connect \mspi1_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - connect \mspi1_cs_n__core__o \spisdcard_cs_n - connect \mspi1_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - connect \mspi1_miso__core__i \spisdcard_miso - connect \mspi1_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - connect \mspi1_mosi__core__o \spisdcard_mosi - connect \mspi1_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi - connect \mtwi_scl__core__o \i2c_scl - connect \mtwi_scl__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - connect \mtwi_sda__core__i \i2c_sda_i - connect \mtwi_sda__core__o \i2c_sda_o - connect \mtwi_sda__core__oe \i2c_sda_oe - connect \mtwi_sda__pad__i \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - connect \mtwi_sda__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - connect \mtwi_sda__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - connect \pc_i 1'0 - connect \pc_i_ok 1'0 - connect \pc_o \main_libresocsim_libresoc2 - connect \pll_18_o \main_libresocsim_libresoc_pll_18_o - connect \pll_lck_o \main_libresocsim_libresoc_pll_lck_o - connect \pwm_0__core__o \pwm [0] - connect \pwm_0__pad__o \pwm_1 [0] - connect \pwm_1__core__o \pwm [1] - connect \pwm_1__pad__o \pwm_1 [1] - connect \rst $or$ls180.v:10709$3079_Y - connect \sd0_clk__core__o \sdcard_clk - connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - connect \sd0_cmd__core__i \sdcard_cmd_i - connect \sd0_cmd__core__o \sdcard_cmd_o - connect \sd0_cmd__core__oe \sdcard_cmd_oe - connect \sd0_cmd__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_cmd__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_cmd__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data0__core__i \sdcard_data_i [0] - connect \sd0_data0__core__o \sdcard_data_o [0] - connect \sd0_data0__core__oe \sdcard_data_oe - connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [0] - connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [0] - connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - connect \sd0_data1__core__i \sdcard_data_i [1] - connect \sd0_data1__core__o \sdcard_data_o [1] - connect \sd0_data1__core__oe \sdcard_data_oe - connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [1] - connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [1] - connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - connect \sd0_data2__core__i \sdcard_data_i [2] - connect \sd0_data2__core__o \sdcard_data_o [2] - connect \sd0_data2__core__oe \sdcard_data_oe - connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [2] - connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [2] - connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - connect \sd0_data3__core__i \sdcard_data_i [3] - connect \sd0_data3__core__o \sdcard_data_o [3] - connect \sd0_data3__core__oe \sdcard_data_oe - connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [3] - connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [3] - connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - connect \sdr_a_0__core__o \sdram_a [0] - connect \sdr_a_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [0] - connect \sdr_a_10__core__o \sdram_a [10] - connect \sdr_a_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [10] - connect \sdr_a_11__core__o \sdram_a [11] - connect \sdr_a_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [11] - connect \sdr_a_12__core__o \sdram_a [12] - connect \sdr_a_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [12] - connect \sdr_a_1__core__o \sdram_a [1] - connect \sdr_a_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [1] - connect \sdr_a_2__core__o \sdram_a [2] - connect \sdr_a_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [2] - connect \sdr_a_3__core__o \sdram_a [3] - connect \sdr_a_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [3] - connect \sdr_a_4__core__o \sdram_a [4] - connect \sdr_a_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [4] - connect \sdr_a_5__core__o \sdram_a [5] - connect \sdr_a_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [5] - connect \sdr_a_6__core__o \sdram_a [6] - connect \sdr_a_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [6] - connect \sdr_a_7__core__o \sdram_a [7] - connect \sdr_a_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [7] - connect \sdr_a_8__core__o \sdram_a [8] - connect \sdr_a_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [8] - connect \sdr_a_9__core__o \sdram_a [9] - connect \sdr_a_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [9] - connect \sdr_ba_0__core__o \sdram_ba [0] - connect \sdr_ba_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [0] - connect \sdr_ba_1__core__o \sdram_ba [1] - connect \sdr_ba_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [1] - connect \sdr_cas_n__core__o \sdram_cas_n - connect \sdr_cas_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - connect \sdr_cke__core__o \sdram_cke - connect \sdr_cke__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - connect \sdr_clock__core__o \sdram_clock - connect \sdr_clock__pad__o \sdram_clock_1 - connect \sdr_cs_n__core__o \sdram_cs_n - connect \sdr_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - connect \sdr_dm_0__core__o \sdram_dm [0] - connect \sdr_dm_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [0] - connect \sdr_dm_1__core__o \sdram_dm [1] - connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [1] - connect \sdr_dq_0__core__i \sdram_dq_i [0] - connect \sdr_dq_0__core__o \sdram_dq_o [0] - connect \sdr_dq_0__core__oe \sdram_dq_oe - connect \sdr_dq_0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0] - connect \sdr_dq_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [0] - connect \sdr_dq_0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_10__core__i \sdram_dq_i [10] - connect \sdr_dq_10__core__o \sdram_dq_o [10] - connect \sdr_dq_10__core__oe \sdram_dq_oe - connect \sdr_dq_10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10] - connect \sdr_dq_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [10] - connect \sdr_dq_10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_11__core__i \sdram_dq_i [11] - connect \sdr_dq_11__core__o \sdram_dq_o [11] - connect \sdr_dq_11__core__oe \sdram_dq_oe - connect \sdr_dq_11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11] - connect \sdr_dq_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [11] - connect \sdr_dq_11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_12__core__i \sdram_dq_i [12] - connect \sdr_dq_12__core__o \sdram_dq_o [12] - connect \sdr_dq_12__core__oe \sdram_dq_oe - connect \sdr_dq_12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12] - connect \sdr_dq_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [12] - connect \sdr_dq_12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_13__core__i \sdram_dq_i [13] - connect \sdr_dq_13__core__o \sdram_dq_o [13] - connect \sdr_dq_13__core__oe \sdram_dq_oe - connect \sdr_dq_13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13] - connect \sdr_dq_13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [13] - connect \sdr_dq_13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_14__core__i \sdram_dq_i [14] - connect \sdr_dq_14__core__o \sdram_dq_o [14] - connect \sdr_dq_14__core__oe \sdram_dq_oe - connect \sdr_dq_14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14] - connect \sdr_dq_14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [14] - connect \sdr_dq_14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_15__core__i \sdram_dq_i [15] - connect \sdr_dq_15__core__o \sdram_dq_o [15] - connect \sdr_dq_15__core__oe \sdram_dq_oe - connect \sdr_dq_15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15] - connect \sdr_dq_15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [15] - connect \sdr_dq_15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_1__core__i \sdram_dq_i [1] - connect \sdr_dq_1__core__o \sdram_dq_o [1] - connect \sdr_dq_1__core__oe \sdram_dq_oe - connect \sdr_dq_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] - connect \sdr_dq_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] - connect \sdr_dq_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_2__core__i \sdram_dq_i [2] - connect \sdr_dq_2__core__o \sdram_dq_o [2] - connect \sdr_dq_2__core__oe \sdram_dq_oe - connect \sdr_dq_2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2] - connect \sdr_dq_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [2] - connect \sdr_dq_2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_3__core__i \sdram_dq_i [3] - connect \sdr_dq_3__core__o \sdram_dq_o [3] - connect \sdr_dq_3__core__oe \sdram_dq_oe - connect \sdr_dq_3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3] - connect \sdr_dq_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [3] - connect \sdr_dq_3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_4__core__i \sdram_dq_i [4] - connect \sdr_dq_4__core__o \sdram_dq_o [4] - connect \sdr_dq_4__core__oe \sdram_dq_oe - connect \sdr_dq_4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4] - connect \sdr_dq_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [4] - connect \sdr_dq_4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_5__core__i \sdram_dq_i [5] - connect \sdr_dq_5__core__o \sdram_dq_o [5] - connect \sdr_dq_5__core__oe \sdram_dq_oe - connect \sdr_dq_5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5] - connect \sdr_dq_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [5] - connect \sdr_dq_5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_6__core__i \sdram_dq_i [6] - connect \sdr_dq_6__core__o \sdram_dq_o [6] - connect \sdr_dq_6__core__oe \sdram_dq_oe - connect \sdr_dq_6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6] - connect \sdr_dq_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [6] - connect \sdr_dq_6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_7__core__i \sdram_dq_i [7] - connect \sdr_dq_7__core__o \sdram_dq_o [7] - connect \sdr_dq_7__core__oe \sdram_dq_oe - connect \sdr_dq_7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7] - connect \sdr_dq_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [7] - connect \sdr_dq_7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_8__core__i \sdram_dq_i [8] - connect \sdr_dq_8__core__o \sdram_dq_o [8] - connect \sdr_dq_8__core__oe \sdram_dq_oe - connect \sdr_dq_8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8] - connect \sdr_dq_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [8] - connect \sdr_dq_8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_9__core__i \sdram_dq_i [9] - connect \sdr_dq_9__core__o \sdram_dq_o [9] - connect \sdr_dq_9__core__oe \sdram_dq_oe - connect \sdr_dq_9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9] - connect \sdr_dq_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [9] - connect \sdr_dq_9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_ras_n__core__o \sdram_ras_n - connect \sdr_ras_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - connect \sdr_we_n__core__o \sdram_we_n - connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - connect \sram4k_0_wb__ack \main_libresocsim_libresoc_interface0_ack - connect \sram4k_0_wb__adr \main_libresocsim_libresoc_interface0_adr - connect \sram4k_0_wb__cyc \main_libresocsim_libresoc_interface0_cyc - connect \sram4k_0_wb__dat_r \main_libresocsim_libresoc_interface0_dat_r - connect \sram4k_0_wb__dat_w \main_libresocsim_libresoc_interface0_dat_w - connect \sram4k_0_wb__err \main_libresocsim_libresoc_interface0_err - connect \sram4k_0_wb__sel \main_libresocsim_libresoc_interface0_sel - connect \sram4k_0_wb__stb \main_libresocsim_libresoc_interface0_stb - connect \sram4k_0_wb__we \main_libresocsim_libresoc_interface0_we - connect \sram4k_1_wb__ack \main_libresocsim_libresoc_interface1_ack - connect \sram4k_1_wb__adr \main_libresocsim_libresoc_interface1_adr - connect \sram4k_1_wb__cyc \main_libresocsim_libresoc_interface1_cyc - connect \sram4k_1_wb__dat_r \main_libresocsim_libresoc_interface1_dat_r - connect \sram4k_1_wb__dat_w \main_libresocsim_libresoc_interface1_dat_w - connect \sram4k_1_wb__err \main_libresocsim_libresoc_interface1_err - connect \sram4k_1_wb__sel \main_libresocsim_libresoc_interface1_sel - connect \sram4k_1_wb__stb \main_libresocsim_libresoc_interface1_stb - connect \sram4k_1_wb__we \main_libresocsim_libresoc_interface1_we - connect \sram4k_2_wb__ack \main_libresocsim_libresoc_interface2_ack - connect \sram4k_2_wb__adr \main_libresocsim_libresoc_interface2_adr - connect \sram4k_2_wb__cyc \main_libresocsim_libresoc_interface2_cyc - connect \sram4k_2_wb__dat_r \main_libresocsim_libresoc_interface2_dat_r - connect \sram4k_2_wb__dat_w \main_libresocsim_libresoc_interface2_dat_w - connect \sram4k_2_wb__err \main_libresocsim_libresoc_interface2_err - connect \sram4k_2_wb__sel \main_libresocsim_libresoc_interface2_sel - connect \sram4k_2_wb__stb \main_libresocsim_libresoc_interface2_stb - connect \sram4k_2_wb__we \main_libresocsim_libresoc_interface2_we - connect \sram4k_3_wb__ack \main_libresocsim_libresoc_interface3_ack - connect \sram4k_3_wb__adr \main_libresocsim_libresoc_interface3_adr - connect \sram4k_3_wb__cyc \main_libresocsim_libresoc_interface3_cyc - connect \sram4k_3_wb__dat_r \main_libresocsim_libresoc_interface3_dat_r - connect \sram4k_3_wb__dat_w \main_libresocsim_libresoc_interface3_dat_w - connect \sram4k_3_wb__err \main_libresocsim_libresoc_interface3_err - connect \sram4k_3_wb__sel \main_libresocsim_libresoc_interface3_sel - connect \sram4k_3_wb__stb \main_libresocsim_libresoc_interface3_stb - connect \sram4k_3_wb__we \main_libresocsim_libresoc_interface3_we - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4093 - sync always - sync init - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4094 - sync always - sync init - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4095 - sync always - sync init - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4096 - sync always - sync init - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4097 - sync always - sync init - end - attribute \src "ls180.v:100.11-100.56" - process $proc$ls180.v:100$3146 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_libresoc_xics_ics_sel $1\main_libresocsim_libresoc_xics_ics_sel[3:0] - end - attribute \src "ls180.v:101.5-101.50" - process $proc$ls180.v:101$3147 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] - end - attribute \src "ls180.v:1012.5-1012.40" - process $proc$ls180.v:1012$3485 - assign { } { } - assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 - sync always - update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1013.5-1013.39" - process $proc$ls180.v:1013$3486 - assign { } { } - assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 - sync always - update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] - sync init - end - attribute \src "ls180.v:102.5-102.50" - process $proc$ls180.v:102$3148 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0] - end - attribute \src "ls180.v:1021.5-1021.38" - process $proc$ls180.v:1021$3487 - assign { } { } - assign $1\main_uart_tx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] - end - attribute \src "ls180.v:1028.11-1028.42" - process $proc$ls180.v:1028$3488 - assign { } { } - assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 - sync always - sync init - update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] - end - attribute \src "ls180.v:1029.5-1029.37" - process $proc$ls180.v:1029$3489 - assign { } { } - assign $0\main_uart_tx_fifo_replace[0:0] 1'0 - sync always - update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1030.11-1030.43" - process $proc$ls180.v:1030$3490 - assign { } { } - assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] - end - attribute \src "ls180.v:1031.11-1031.43" - process $proc$ls180.v:1031$3491 - assign { } { } - assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] - end - attribute \src "ls180.v:1032.11-1032.46" - process $proc$ls180.v:1032$3492 - assign { } { } - assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:10353.1-10371.4" - process $proc$ls180.v:10353$2893 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr[5:0] \main_libresocsim_adr - attribute \src "ls180.v:10354.2-10355.65" - switch \main_libresocsim_we [0] - attribute \src "ls180.v:10354.6-10354.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10356.2-10357.67" - switch \main_libresocsim_we [1] - attribute \src "ls180.v:10356.6-10356.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10358.2-10359.69" - switch \main_libresocsim_we [2] - attribute \src "ls180.v:10358.6-10358.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10360.2-10361.69" - switch \main_libresocsim_we [3] - attribute \src "ls180.v:10360.6-10360.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10362.2-10363.69" - switch \main_libresocsim_we [4] - attribute \src "ls180.v:10362.6-10362.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10364.2-10365.69" - switch \main_libresocsim_we [5] - attribute \src "ls180.v:10364.6-10364.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10366.2-10367.69" - switch \main_libresocsim_we [6] - attribute \src "ls180.v:10366.6-10366.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10368.2-10369.69" - switch \main_libresocsim_we [7] - attribute \src "ls180.v:10368.6-10368.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr $0\memadr[5:0] - update $memwr$\mem$ls180.v:10355$1_ADDR $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 - update $memwr$\mem$ls180.v:10355$1_DATA $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 - update $memwr$\mem$ls180.v:10355$1_EN $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 - update $memwr$\mem$ls180.v:10357$2_ADDR $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 - update $memwr$\mem$ls180.v:10357$2_DATA $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 - update $memwr$\mem$ls180.v:10357$2_EN $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 - update $memwr$\mem$ls180.v:10359$3_ADDR $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 - update $memwr$\mem$ls180.v:10359$3_DATA $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 - update $memwr$\mem$ls180.v:10359$3_EN $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 - update $memwr$\mem$ls180.v:10361$4_ADDR $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 - update $memwr$\mem$ls180.v:10361$4_DATA $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 - update $memwr$\mem$ls180.v:10361$4_EN $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 - update $memwr$\mem$ls180.v:10363$5_ADDR $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 - update $memwr$\mem$ls180.v:10363$5_DATA $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 - update $memwr$\mem$ls180.v:10363$5_EN $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 - update $memwr$\mem$ls180.v:10365$6_ADDR $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 - update $memwr$\mem$ls180.v:10365$6_DATA $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 - update $memwr$\mem$ls180.v:10365$6_EN $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 - update $memwr$\mem$ls180.v:10367$7_ADDR $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 - update $memwr$\mem$ls180.v:10367$7_DATA $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 - update $memwr$\mem$ls180.v:10367$7_EN $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 - update $memwr$\mem$ls180.v:10369$8_ADDR $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 - update $memwr$\mem$ls180.v:10369$8_DATA $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 - update $memwr$\mem$ls180.v:10369$8_EN $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 - end - attribute \src "ls180.v:10381.1-10399.4" - process $proc$ls180.v:10381$2919 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr_1[5:0] \main_sram0_adr - attribute \src "ls180.v:10382.2-10383.55" - switch \main_sram0_we [0] - attribute \src "ls180.v:10382.6-10382.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] } - assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10384.2-10385.57" - switch \main_sram0_we [1] - attribute \src "ls180.v:10384.6-10384.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10386.2-10387.59" - switch \main_sram0_we [2] - attribute \src "ls180.v:10386.6-10386.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10388.2-10389.59" - switch \main_sram0_we [3] - attribute \src "ls180.v:10388.6-10388.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10390.2-10391.59" - switch \main_sram0_we [4] - attribute \src "ls180.v:10390.6-10390.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10392.2-10393.59" - switch \main_sram0_we [5] - attribute \src "ls180.v:10392.6-10392.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10394.2-10395.59" - switch \main_sram0_we [6] - attribute \src "ls180.v:10394.6-10394.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10396.2-10397.59" - switch \main_sram0_we [7] - attribute \src "ls180.v:10396.6-10396.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr_1 $0\memadr_1[5:0] - update $memwr$\mem_1$ls180.v:10383$9_ADDR $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 - update $memwr$\mem_1$ls180.v:10383$9_DATA $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 - update $memwr$\mem_1$ls180.v:10383$9_EN $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 - update $memwr$\mem_1$ls180.v:10385$10_ADDR $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 - update $memwr$\mem_1$ls180.v:10385$10_DATA $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 - update $memwr$\mem_1$ls180.v:10385$10_EN $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 - update $memwr$\mem_1$ls180.v:10387$11_ADDR $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 - update $memwr$\mem_1$ls180.v:10387$11_DATA $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 - update $memwr$\mem_1$ls180.v:10387$11_EN $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 - update $memwr$\mem_1$ls180.v:10389$12_ADDR $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 - update $memwr$\mem_1$ls180.v:10389$12_DATA $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 - update $memwr$\mem_1$ls180.v:10389$12_EN $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 - update $memwr$\mem_1$ls180.v:10391$13_ADDR $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 - update $memwr$\mem_1$ls180.v:10391$13_DATA $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 - update $memwr$\mem_1$ls180.v:10391$13_EN $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 - update $memwr$\mem_1$ls180.v:10393$14_ADDR $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 - update $memwr$\mem_1$ls180.v:10393$14_DATA $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 - update $memwr$\mem_1$ls180.v:10393$14_EN $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 - update $memwr$\mem_1$ls180.v:10395$15_ADDR $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 - update $memwr$\mem_1$ls180.v:10395$15_DATA $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 - update $memwr$\mem_1$ls180.v:10395$15_EN $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 - update $memwr$\mem_1$ls180.v:10397$16_ADDR $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 - update $memwr$\mem_1$ls180.v:10397$16_DATA $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 - update $memwr$\mem_1$ls180.v:10397$16_EN $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 - end - attribute \src "ls180.v:104.5-104.49" - process $proc$ls180.v:104$3149 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_ics_we $1\main_libresocsim_libresoc_xics_ics_we[0:0] - end - attribute \src "ls180.v:10409.1-10427.4" - process $proc$ls180.v:10409$2945 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr_2[5:0] \main_sram1_adr - attribute \src "ls180.v:10410.2-10411.55" - switch \main_sram1_we [0] - attribute \src "ls180.v:10410.6-10410.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] } - assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10412.2-10413.57" - switch \main_sram1_we [1] - attribute \src "ls180.v:10412.6-10412.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10414.2-10415.59" - switch \main_sram1_we [2] - attribute \src "ls180.v:10414.6-10414.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10416.2-10417.59" - switch \main_sram1_we [3] - attribute \src "ls180.v:10416.6-10416.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10418.2-10419.59" - switch \main_sram1_we [4] - attribute \src "ls180.v:10418.6-10418.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10420.2-10421.59" - switch \main_sram1_we [5] - attribute \src "ls180.v:10420.6-10420.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10422.2-10423.59" - switch \main_sram1_we [6] - attribute \src "ls180.v:10422.6-10422.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10424.2-10425.59" - switch \main_sram1_we [7] - attribute \src "ls180.v:10424.6-10424.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr_2 $0\memadr_2[5:0] - update $memwr$\mem_2$ls180.v:10411$17_ADDR $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 - update $memwr$\mem_2$ls180.v:10411$17_DATA $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 - update $memwr$\mem_2$ls180.v:10411$17_EN $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 - update $memwr$\mem_2$ls180.v:10413$18_ADDR $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 - update $memwr$\mem_2$ls180.v:10413$18_DATA $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 - update $memwr$\mem_2$ls180.v:10413$18_EN $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 - update $memwr$\mem_2$ls180.v:10415$19_ADDR $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 - update $memwr$\mem_2$ls180.v:10415$19_DATA $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 - update $memwr$\mem_2$ls180.v:10415$19_EN $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 - update $memwr$\mem_2$ls180.v:10417$20_ADDR $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 - update $memwr$\mem_2$ls180.v:10417$20_DATA $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 - update $memwr$\mem_2$ls180.v:10417$20_EN $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 - update $memwr$\mem_2$ls180.v:10419$21_ADDR $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 - update $memwr$\mem_2$ls180.v:10419$21_DATA $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 - update $memwr$\mem_2$ls180.v:10419$21_EN $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 - update $memwr$\mem_2$ls180.v:10421$22_ADDR $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 - update $memwr$\mem_2$ls180.v:10421$22_DATA $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 - update $memwr$\mem_2$ls180.v:10421$22_EN $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 - update $memwr$\mem_2$ls180.v:10423$23_ADDR $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 - update $memwr$\mem_2$ls180.v:10423$23_DATA $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 - update $memwr$\mem_2$ls180.v:10423$23_EN $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 - update $memwr$\mem_2$ls180.v:10425$24_ADDR $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 - update $memwr$\mem_2$ls180.v:10425$24_DATA $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 - update $memwr$\mem_2$ls180.v:10425$24_EN $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 - end - attribute \src "ls180.v:10437.1-10455.4" - process $proc$ls180.v:10437$2971 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr_3[5:0] \main_sram2_adr - attribute \src "ls180.v:10438.2-10439.55" - switch \main_sram2_we [0] - attribute \src "ls180.v:10438.6-10438.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] } - assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10440.2-10441.57" - switch \main_sram2_we [1] - attribute \src "ls180.v:10440.6-10440.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10442.2-10443.59" - switch \main_sram2_we [2] - attribute \src "ls180.v:10442.6-10442.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10444.2-10445.59" - switch \main_sram2_we [3] - attribute \src "ls180.v:10444.6-10444.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10446.2-10447.59" - switch \main_sram2_we [4] - attribute \src "ls180.v:10446.6-10446.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10448.2-10449.59" - switch \main_sram2_we [5] - attribute \src "ls180.v:10448.6-10448.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10450.2-10451.59" - switch \main_sram2_we [6] - attribute \src "ls180.v:10450.6-10450.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10452.2-10453.59" - switch \main_sram2_we [7] - attribute \src "ls180.v:10452.6-10452.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr_3 $0\memadr_3[5:0] - update $memwr$\mem_3$ls180.v:10439$25_ADDR $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 - update $memwr$\mem_3$ls180.v:10439$25_DATA $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 - update $memwr$\mem_3$ls180.v:10439$25_EN $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 - update $memwr$\mem_3$ls180.v:10441$26_ADDR $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 - update $memwr$\mem_3$ls180.v:10441$26_DATA $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 - update $memwr$\mem_3$ls180.v:10441$26_EN $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 - update $memwr$\mem_3$ls180.v:10443$27_ADDR $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 - update $memwr$\mem_3$ls180.v:10443$27_DATA $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 - update $memwr$\mem_3$ls180.v:10443$27_EN $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 - update $memwr$\mem_3$ls180.v:10445$28_ADDR $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 - update $memwr$\mem_3$ls180.v:10445$28_DATA $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 - update $memwr$\mem_3$ls180.v:10445$28_EN $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 - update $memwr$\mem_3$ls180.v:10447$29_ADDR $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 - update $memwr$\mem_3$ls180.v:10447$29_DATA $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 - update $memwr$\mem_3$ls180.v:10447$29_EN $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 - update $memwr$\mem_3$ls180.v:10449$30_ADDR $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 - update $memwr$\mem_3$ls180.v:10449$30_DATA $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 - update $memwr$\mem_3$ls180.v:10449$30_EN $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 - update $memwr$\mem_3$ls180.v:10451$31_ADDR $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 - update $memwr$\mem_3$ls180.v:10451$31_DATA $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 - update $memwr$\mem_3$ls180.v:10451$31_EN $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 - update $memwr$\mem_3$ls180.v:10453$32_ADDR $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 - update $memwr$\mem_3$ls180.v:10453$32_DATA $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 - update $memwr$\mem_3$ls180.v:10453$32_EN $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 - end - attribute \src "ls180.v:10465.1-10483.4" - process $proc$ls180.v:10465$2997 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr_4[5:0] \main_sram3_adr - attribute \src "ls180.v:10466.2-10467.55" - switch \main_sram3_we [0] - attribute \src "ls180.v:10466.6-10466.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram3_dat_w [7:0] } - assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10468.2-10469.57" - switch \main_sram3_we [1] - attribute \src "ls180.v:10468.6-10468.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 { 48'000000000000000000000000000000000000000000000000 \main_sram3_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10470.2-10471.59" - switch \main_sram3_we [2] - attribute \src "ls180.v:10470.6-10470.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 { 40'0000000000000000000000000000000000000000 \main_sram3_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10472.2-10473.59" - switch \main_sram3_we [3] - attribute \src "ls180.v:10472.6-10472.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 { 32'00000000000000000000000000000000 \main_sram3_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10474.2-10475.59" - switch \main_sram3_we [4] - attribute \src "ls180.v:10474.6-10474.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 { 24'000000000000000000000000 \main_sram3_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10476.2-10477.59" - switch \main_sram3_we [5] - attribute \src "ls180.v:10476.6-10476.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 { 16'0000000000000000 \main_sram3_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10478.2-10479.59" - switch \main_sram3_we [6] - attribute \src "ls180.v:10478.6-10478.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 { 8'00000000 \main_sram3_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10480.2-10481.59" - switch \main_sram3_we [7] - attribute \src "ls180.v:10480.6-10480.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 { \main_sram3_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr_4 $0\memadr_4[5:0] - update $memwr$\mem_4$ls180.v:10467$33_ADDR $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 - update $memwr$\mem_4$ls180.v:10467$33_DATA $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 - update $memwr$\mem_4$ls180.v:10467$33_EN $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 - update $memwr$\mem_4$ls180.v:10469$34_ADDR $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 - update $memwr$\mem_4$ls180.v:10469$34_DATA $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 - update $memwr$\mem_4$ls180.v:10469$34_EN $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 - update $memwr$\mem_4$ls180.v:10471$35_ADDR $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 - update $memwr$\mem_4$ls180.v:10471$35_DATA $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 - update $memwr$\mem_4$ls180.v:10471$35_EN $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 - update $memwr$\mem_4$ls180.v:10473$36_ADDR $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 - update $memwr$\mem_4$ls180.v:10473$36_DATA $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 - update $memwr$\mem_4$ls180.v:10473$36_EN $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 - update $memwr$\mem_4$ls180.v:10475$37_ADDR $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 - update $memwr$\mem_4$ls180.v:10475$37_DATA $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 - update $memwr$\mem_4$ls180.v:10475$37_EN $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 - update $memwr$\mem_4$ls180.v:10477$38_ADDR $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 - update $memwr$\mem_4$ls180.v:10477$38_DATA $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 - update $memwr$\mem_4$ls180.v:10477$38_EN $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 - update $memwr$\mem_4$ls180.v:10479$39_ADDR $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 - update $memwr$\mem_4$ls180.v:10479$39_DATA $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 - update $memwr$\mem_4$ls180.v:10479$39_EN $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 - update $memwr$\mem_4$ls180.v:10481$40_ADDR $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 - update $memwr$\mem_4$ls180.v:10481$40_DATA $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 - update $memwr$\mem_4$ls180.v:10481$40_EN $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 - end - attribute \src "ls180.v:10493.1-10497.4" - process $proc$ls180.v:10493$3023 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 3'xxx - assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 25'0000000000000000000000000 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:10496$3027_DATA - attribute \src "ls180.v:10494.2-10495.129" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10494.6-10494.60" - case 1'1 - assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:10495$41_ADDR $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 - update $memwr$\storage$ls180.v:10495$41_DATA $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 - update $memwr$\storage$ls180.v:10495$41_EN $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 - end - attribute \src "ls180.v:10499.1-10500.4" - process $proc$ls180.v:10499$3028 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10507.1-10511.4" - process $proc$ls180.v:10507$3030 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 3'xxx - assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 25'0000000000000000000000000 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10510$3034_DATA - attribute \src "ls180.v:10508.2-10509.131" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10508.6-10508.60" - case 1'1 - assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:10509$42_ADDR $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 - update $memwr$\storage_1$ls180.v:10509$42_DATA $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 - update $memwr$\storage_1$ls180.v:10509$42_EN $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 - end - attribute \src "ls180.v:10513.1-10514.4" - process $proc$ls180.v:10513$3035 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10521.1-10525.4" - process $proc$ls180.v:10521$3037 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 3'xxx - assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 25'0000000000000000000000000 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10524$3041_DATA - attribute \src "ls180.v:10522.2-10523.131" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10522.6-10522.60" - case 1'1 - assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:10523$43_ADDR $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 - update $memwr$\storage_2$ls180.v:10523$43_DATA $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 - update $memwr$\storage_2$ls180.v:10523$43_EN $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 - end - attribute \src "ls180.v:10527.1-10528.4" - process $proc$ls180.v:10527$3042 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10535.1-10539.4" - process $proc$ls180.v:10535$3044 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 3'xxx - assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 25'0000000000000000000000000 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10538$3048_DATA - attribute \src "ls180.v:10536.2-10537.131" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10536.6-10536.60" - case 1'1 - assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:10537$44_ADDR $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 - update $memwr$\storage_3$ls180.v:10537$44_DATA $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 - update $memwr$\storage_3$ls180.v:10537$44_EN $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 - end - attribute \src "ls180.v:10541.1-10542.4" - process $proc$ls180.v:10541$3049 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10550.1-10554.4" - process $proc$ls180.v:10550$3051 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 4'xxxx - assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 10'xxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 10'0000000000 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10553$3055_DATA - attribute \src "ls180.v:10551.2-10552.77" - switch \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:10551.6-10551.33" - case 1'1 - assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 \main_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 \main_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:10552$45_ADDR $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 - update $memwr$\storage_4$ls180.v:10552$45_DATA $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 - update $memwr$\storage_4$ls180.v:10552$45_EN $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 - end - attribute \src "ls180.v:10556.1-10559.4" - process $proc$ls180.v:10556$3056 - assign $0\memdat_5[9:0] \memdat_5 - attribute \src "ls180.v:10557.2-10558.55" - switch \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:10557.6-10557.33" - case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10558$3057_DATA - case - end - sync posedge \sys_clk_1 - update \memdat_5 $0\memdat_5[9:0] - end - attribute \src "ls180.v:10567.1-10571.4" - process $proc$ls180.v:10567$3058 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 4'xxxx - assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 10'xxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 10'0000000000 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10570$3062_DATA - attribute \src "ls180.v:10568.2-10569.77" - switch \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:10568.6-10568.33" - case 1'1 - assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 \main_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 \main_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:10569$46_ADDR $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 - update $memwr$\storage_5$ls180.v:10569$46_DATA $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 - update $memwr$\storage_5$ls180.v:10569$46_EN $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 - end - attribute \src "ls180.v:10573.1-10576.4" - process $proc$ls180.v:10573$3063 - assign $0\memdat_7[9:0] \memdat_7 - attribute \src "ls180.v:10574.2-10575.55" - switch \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:10574.6-10574.33" - case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10575$3064_DATA - case - end - sync posedge \sys_clk_1 - update \memdat_7 $0\memdat_7[9:0] - end - attribute \src "ls180.v:1058.5-1058.38" - process $proc$ls180.v:1058$3493 - assign { } { } - assign $1\main_uart_rx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] - end - attribute \src "ls180.v:10583.1-10587.4" - process $proc$ls180.v:10583$3065 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10586$3069_DATA - attribute \src "ls180.v:10584.2-10585.85" - switch \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:10584.6-10584.37" - case 1'1 - assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 \main_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 \main_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:10585$47_ADDR $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 - update $memwr$\storage_6$ls180.v:10585$47_DATA $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 - update $memwr$\storage_6$ls180.v:10585$47_EN $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 - end - attribute \src "ls180.v:10589.1-10590.4" - process $proc$ls180.v:10589$3070 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10597.1-10601.4" - process $proc$ls180.v:10597$3072 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10600$3076_DATA - attribute \src "ls180.v:10598.2-10599.85" - switch \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:10598.6-10598.37" - case 1'1 - assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 \main_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 \main_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:10599$48_ADDR $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 - update $memwr$\storage_7$ls180.v:10599$48_DATA $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 - update $memwr$\storage_7$ls180.v:10599$48_EN $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 - end - attribute \src "ls180.v:10603.1-10604.4" - process $proc$ls180.v:10603$3077 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:1065.11-1065.42" - process $proc$ls180.v:1065$3494 - assign { } { } - assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 - sync always - sync init - update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] - end - attribute \src "ls180.v:1066.5-1066.37" - process $proc$ls180.v:1066$3495 - assign { } { } - assign $0\main_uart_rx_fifo_replace[0:0] 1'0 - sync always - update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1067.11-1067.43" - process $proc$ls180.v:1067$3496 - assign { } { } - assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] - end - attribute \src "ls180.v:1068.11-1068.43" - process $proc$ls180.v:1068$3497 - assign { } { } - assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] - end - attribute \src "ls180.v:1069.11-1069.46" - process $proc$ls180.v:1069$3498 - assign { } { } - assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:1084.5-1084.27" - process $proc$ls180.v:1084$3499 - assign { } { } - assign $0\main_uart_reset[0:0] 1'0 - sync always - update \main_uart_reset $0\main_uart_reset[0:0] - sync init - end - attribute \src "ls180.v:1085.12-1085.53" - process $proc$ls180.v:1085$3500 - assign { } { } - assign $0\main_gpiotristateasic0_oe_storage[15:0] 16'0000000000000000 - sync always - update \main_gpiotristateasic0_oe_storage $0\main_gpiotristateasic0_oe_storage[15:0] - sync init - end - attribute \src "ls180.v:1086.12-1086.49" - process $proc$ls180.v:1086$3501 - assign { } { } - assign $1\main_gpiotristateasic0_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic0_status $1\main_gpiotristateasic0_status[15:0] - end - attribute \src "ls180.v:1087.12-1087.54" - process $proc$ls180.v:1087$3502 - assign { } { } - assign $0\main_gpiotristateasic0_out_storage[15:0] 16'0000000000000000 - sync always - update \main_gpiotristateasic0_out_storage $0\main_gpiotristateasic0_out_storage[15:0] - sync init - end - attribute \src "ls180.v:1091.12-1091.53" - process $proc$ls180.v:1091$3503 - assign { } { } - assign $1\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic1_oe_storage $1\main_gpiotristateasic1_oe_storage[15:0] - end - attribute \src "ls180.v:1092.5-1092.40" - process $proc$ls180.v:1092$3504 - assign { } { } - assign $1\main_gpiotristateasic1_oe_re[0:0] 1'0 - sync always - sync init - update \main_gpiotristateasic1_oe_re $1\main_gpiotristateasic1_oe_re[0:0] - end - attribute \src "ls180.v:1093.12-1093.49" - process $proc$ls180.v:1093$3505 - assign { } { } - assign $1\main_gpiotristateasic1_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic1_status $1\main_gpiotristateasic1_status[15:0] - end - attribute \src "ls180.v:1095.12-1095.54" - process $proc$ls180.v:1095$3506 - assign { } { } - assign $1\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic1_out_storage $1\main_gpiotristateasic1_out_storage[15:0] - end - attribute \src "ls180.v:1096.5-1096.41" - process $proc$ls180.v:1096$3507 - assign { } { } - assign $1\main_gpiotristateasic1_out_re[0:0] 1'0 - sync always - sync init - update \main_gpiotristateasic1_out_re $1\main_gpiotristateasic1_out_re[0:0] - end - attribute \src "ls180.v:1102.5-1102.32" - process $proc$ls180.v:1102$3508 - assign { } { } - assign $1\main_spimaster2_done[0:0] 1'0 - sync always - sync init - update \main_spimaster2_done $1\main_spimaster2_done[0:0] - end - attribute \src "ls180.v:1103.5-1103.31" - process $proc$ls180.v:1103$3509 - assign { } { } - assign $1\main_spimaster3_irq[0:0] 1'0 - sync always - sync init - update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] - end - attribute \src "ls180.v:1105.11-1105.38" - process $proc$ls180.v:1105$3510 - assign { } { } - assign $1\main_spimaster5_miso[7:0] 8'00000000 - sync always - sync init - update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] - end - attribute \src "ls180.v:1108.12-1108.47" - process $proc$ls180.v:1108$3511 - assign { } { } - assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 - sync always - update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] - sync init - end - attribute \src "ls180.v:1109.5-1109.33" - process $proc$ls180.v:1109$3512 - assign { } { } - assign $1\main_spimaster9_start[0:0] 1'0 - sync always - sync init - update \main_spimaster9_start $1\main_spimaster9_start[0:0] - end - attribute \src "ls180.v:1111.12-1111.44" - process $proc$ls180.v:1111$3513 - assign { } { } - assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] - end - attribute \src "ls180.v:1112.5-1112.31" - process $proc$ls180.v:1112$3514 - assign { } { } - assign $1\main_spimaster12_re[0:0] 1'0 - sync always - sync init - update \main_spimaster12_re $1\main_spimaster12_re[0:0] - end - attribute \src "ls180.v:1116.11-1116.42" - process $proc$ls180.v:1116$3515 - assign { } { } - assign $1\main_spimaster16_storage[7:0] 8'00000000 - sync always - sync init - update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] - end - attribute \src "ls180.v:1117.5-1117.31" - process $proc$ls180.v:1117$3516 - assign { } { } - assign $1\main_spimaster17_re[0:0] 1'0 - sync always - sync init - update \main_spimaster17_re $1\main_spimaster17_re[0:0] - end - attribute \src "ls180.v:1121.5-1121.36" - process $proc$ls180.v:1121$3517 - assign { } { } - assign $1\main_spimaster21_storage[0:0] 1'1 - sync always - sync init - update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] - end - attribute \src "ls180.v:1122.5-1122.31" - process $proc$ls180.v:1122$3518 - assign { } { } - assign $1\main_spimaster22_re[0:0] 1'0 - sync always - sync init - update \main_spimaster22_re $1\main_spimaster22_re[0:0] - end - attribute \src "ls180.v:1123.5-1123.36" - process $proc$ls180.v:1123$3519 - assign { } { } - assign $1\main_spimaster23_storage[0:0] 1'0 - sync always - sync init - update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] - end - attribute \src "ls180.v:1124.5-1124.31" - process $proc$ls180.v:1124$3520 - assign { } { } - assign $1\main_spimaster24_re[0:0] 1'0 - sync always - sync init - update \main_spimaster24_re $1\main_spimaster24_re[0:0] - end - attribute \src "ls180.v:1125.5-1125.39" - process $proc$ls180.v:1125$3521 - assign { } { } - assign $1\main_spimaster25_clk_enable[0:0] 1'0 - sync always - sync init - update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] - end - attribute \src "ls180.v:1126.5-1126.38" - process $proc$ls180.v:1126$3522 - assign { } { } - assign $1\main_spimaster26_cs_enable[0:0] 1'0 - sync always - sync init - update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] - end - attribute \src "ls180.v:1127.11-1127.40" - process $proc$ls180.v:1127$3523 - assign { } { } - assign $1\main_spimaster27_count[2:0] 3'000 - sync always - sync init - update \main_spimaster27_count $1\main_spimaster27_count[2:0] - end - attribute \src "ls180.v:1128.5-1128.39" - process $proc$ls180.v:1128$3524 - assign { } { } - assign $1\main_spimaster28_mosi_latch[0:0] 1'0 - sync always - sync init - update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] - end - attribute \src "ls180.v:1129.5-1129.39" - process $proc$ls180.v:1129$3525 - assign { } { } - assign $1\main_spimaster29_miso_latch[0:0] 1'0 - sync always - sync init - update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] - end - attribute \src "ls180.v:1130.12-1130.48" - process $proc$ls180.v:1130$3526 - assign { } { } - assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 - sync always - sync init - update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] - end - attribute \src "ls180.v:1133.11-1133.44" - process $proc$ls180.v:1133$3527 - assign { } { } - assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 - sync always - sync init - update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] - end - attribute \src "ls180.v:1134.11-1134.43" - process $proc$ls180.v:1134$3528 - assign { } { } - assign $1\main_spimaster34_mosi_sel[2:0] 3'000 - sync always - sync init - update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] - end - attribute \src "ls180.v:1135.11-1135.44" - process $proc$ls180.v:1135$3529 - assign { } { } - assign $1\main_spimaster35_miso_data[7:0] 8'00000000 - sync always - sync init - update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] - end - attribute \src "ls180.v:1138.5-1138.32" - process $proc$ls180.v:1138$3530 - assign { } { } - assign $1\main_spisdcard_done0[0:0] 1'0 - sync always - sync init - update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] - end - attribute \src "ls180.v:1139.5-1139.30" - process $proc$ls180.v:1139$3531 - assign { } { } - assign $1\main_spisdcard_irq[0:0] 1'0 - sync always - sync init - update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] - end - attribute \src "ls180.v:114.11-114.55" - process $proc$ls180.v:114$3150 - assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] 3'000 - sync always - update \main_libresocsim_libresoc_jtag_wb_cti $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] - sync init - end - attribute \src "ls180.v:1141.11-1141.37" - process $proc$ls180.v:1141$3532 - assign { } { } - assign $1\main_spisdcard_miso[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] - end - attribute \src "ls180.v:1145.5-1145.33" - process $proc$ls180.v:1145$3533 - assign { } { } - assign $1\main_spisdcard_start1[0:0] 1'0 - sync always - sync init - update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] - end - attribute \src "ls180.v:1147.12-1147.50" - process $proc$ls180.v:1147$3534 - assign { } { } - assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] - end - attribute \src "ls180.v:1148.5-1148.37" - process $proc$ls180.v:1148$3535 - assign { } { } - assign $1\main_spisdcard_control_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] - end - attribute \src "ls180.v:115.11-115.55" - process $proc$ls180.v:115$3151 - assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] 2'00 - sync always - update \main_libresocsim_libresoc_jtag_wb_bte $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] - sync init - end - attribute \src "ls180.v:1152.11-1152.45" - process $proc$ls180.v:1152$3536 - assign { } { } - assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] - end - attribute \src "ls180.v:1153.5-1153.34" - process $proc$ls180.v:1153$3537 - assign { } { } - assign $1\main_spisdcard_mosi_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] - end - attribute \src "ls180.v:1157.5-1157.37" - process $proc$ls180.v:1157$3538 - assign { } { } - assign $1\main_spisdcard_cs_storage[0:0] 1'1 - sync always - sync init - update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] - end - attribute \src "ls180.v:1158.5-1158.32" - process $proc$ls180.v:1158$3539 - assign { } { } - assign $1\main_spisdcard_cs_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] - end - attribute \src "ls180.v:1159.5-1159.43" - process $proc$ls180.v:1159$3540 - assign { } { } - assign $1\main_spisdcard_loopback_storage[0:0] 1'0 - sync always - sync init - update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] - end - attribute \src "ls180.v:1160.5-1160.38" - process $proc$ls180.v:1160$3541 - assign { } { } - assign $1\main_spisdcard_loopback_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] - end - attribute \src "ls180.v:1161.5-1161.37" - process $proc$ls180.v:1161$3542 - assign { } { } - assign $1\main_spisdcard_clk_enable[0:0] 1'0 - sync always - sync init - update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] - end - attribute \src "ls180.v:1162.5-1162.36" - process $proc$ls180.v:1162$3543 - assign { } { } - assign $1\main_spisdcard_cs_enable[0:0] 1'0 - sync always - sync init - update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] - end - attribute \src "ls180.v:1163.11-1163.38" - process $proc$ls180.v:1163$3544 - assign { } { } - assign $1\main_spisdcard_count[2:0] 3'000 - sync always - sync init - update \main_spisdcard_count $1\main_spisdcard_count[2:0] - end - attribute \src "ls180.v:1164.5-1164.37" - process $proc$ls180.v:1164$3545 - assign { } { } - assign $1\main_spisdcard_mosi_latch[0:0] 1'0 - sync always - sync init - update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] - end - attribute \src "ls180.v:1165.5-1165.37" - process $proc$ls180.v:1165$3546 - assign { } { } - assign $1\main_spisdcard_miso_latch[0:0] 1'0 - sync always - sync init - update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] - end - attribute \src "ls180.v:1166.12-1166.47" - process $proc$ls180.v:1166$3547 - assign { } { } - assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 - sync always - sync init - update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] - end - attribute \src "ls180.v:1169.11-1169.42" - process $proc$ls180.v:1169$3548 - assign { } { } - assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] - end - attribute \src "ls180.v:1170.11-1170.41" - process $proc$ls180.v:1170$3549 - assign { } { } - assign $1\main_spisdcard_mosi_sel[2:0] 3'000 - sync always - sync init - update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] - end - attribute \src "ls180.v:1171.11-1171.42" - process $proc$ls180.v:1171$3550 - assign { } { } - assign $1\main_spisdcard_miso_data[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] - end - attribute \src "ls180.v:1172.12-1172.45" - process $proc$ls180.v:1172$3551 - assign { } { } - assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 - sync always - sync init - update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] - end - attribute \src "ls180.v:1173.5-1173.30" - process $proc$ls180.v:1173$3552 - assign { } { } - assign $1\main_spimaster1_re[0:0] 1'0 - sync always - sync init - update \main_spimaster1_re $1\main_spimaster1_re[0:0] - end - attribute \src "ls180.v:1175.12-1175.30" - process $proc$ls180.v:1175$3553 - assign { } { } - assign $1\main_dummy[23:0] 24'000000000000000000000000 - sync always - sync init - update \main_dummy $1\main_dummy[23:0] - end - attribute \src "ls180.v:1179.12-1179.37" - process $proc$ls180.v:1179$3554 - assign { } { } - assign $1\main_pwm0_counter[31:0] 0 - sync always - sync init - update \main_pwm0_counter $1\main_pwm0_counter[31:0] - end - attribute \src "ls180.v:1180.5-1180.36" - process $proc$ls180.v:1180$3555 - assign { } { } - assign $1\main_pwm0_enable_storage[0:0] 1'0 - sync always - sync init - update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] - end - attribute \src "ls180.v:1181.5-1181.31" - process $proc$ls180.v:1181$3556 - assign { } { } - assign $1\main_pwm0_enable_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] - end - attribute \src "ls180.v:1182.12-1182.43" - process $proc$ls180.v:1182$3557 - assign { } { } - assign $1\main_pwm0_width_storage[31:0] 0 - sync always - sync init - update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] - end - attribute \src "ls180.v:1183.5-1183.30" - process $proc$ls180.v:1183$3558 - assign { } { } - assign $1\main_pwm0_width_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] - end - attribute \src "ls180.v:1184.12-1184.44" - process $proc$ls180.v:1184$3559 - assign { } { } - assign $1\main_pwm0_period_storage[31:0] 0 - sync always - sync init - update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] - end - attribute \src "ls180.v:1185.5-1185.31" - process $proc$ls180.v:1185$3560 - assign { } { } - assign $1\main_pwm0_period_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] - end - attribute \src "ls180.v:1189.12-1189.37" - process $proc$ls180.v:1189$3561 - assign { } { } - assign $1\main_pwm1_counter[31:0] 0 - sync always - sync init - update \main_pwm1_counter $1\main_pwm1_counter[31:0] - end - attribute \src "ls180.v:1190.5-1190.36" - process $proc$ls180.v:1190$3562 - assign { } { } - assign $1\main_pwm1_enable_storage[0:0] 1'0 - sync always - sync init - update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] - end - attribute \src "ls180.v:1191.5-1191.31" - process $proc$ls180.v:1191$3563 - assign { } { } - assign $1\main_pwm1_enable_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] - end - attribute \src "ls180.v:1192.12-1192.43" - process $proc$ls180.v:1192$3564 - assign { } { } - assign $1\main_pwm1_width_storage[31:0] 0 - sync always - sync init - update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] - end - attribute \src "ls180.v:1193.5-1193.30" - process $proc$ls180.v:1193$3565 - assign { } { } - assign $1\main_pwm1_width_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] - end - attribute \src "ls180.v:1194.12-1194.44" - process $proc$ls180.v:1194$3566 - assign { } { } - assign $1\main_pwm1_period_storage[31:0] 0 - sync always - sync init - update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] - end - attribute \src "ls180.v:1195.5-1195.31" - process $proc$ls180.v:1195$3567 - assign { } { } - assign $1\main_pwm1_period_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] - end - attribute \src "ls180.v:1199.11-1199.34" - process $proc$ls180.v:1199$3568 - assign { } { } - assign $1\main_i2c_storage[2:0] 3'000 - sync always - sync init - update \main_i2c_storage $1\main_i2c_storage[2:0] - end - attribute \src "ls180.v:1200.5-1200.23" - process $proc$ls180.v:1200$3569 - assign { } { } - assign $1\main_i2c_re[0:0] 1'0 - sync always - sync init - update \main_i2c_re $1\main_i2c_re[0:0] - end - attribute \src "ls180.v:1206.11-1206.46" - process $proc$ls180.v:1206$3570 - assign { } { } - assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 - sync always - sync init - update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] - end - attribute \src "ls180.v:1207.5-1207.33" - process $proc$ls180.v:1207$3571 - assign { } { } - assign $1\main_sdphy_clocker_re[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] - end - attribute \src "ls180.v:1209.5-1209.35" - process $proc$ls180.v:1209$3572 - assign { } { } - assign $1\main_sdphy_clocker_clk0[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] - end - attribute \src "ls180.v:1211.11-1211.41" - process $proc$ls180.v:1211$3573 - assign { } { } - assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 - sync always - sync init - update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] - end - attribute \src "ls180.v:1212.5-1212.35" - process $proc$ls180.v:1212$3574 - assign { } { } - assign $1\main_sdphy_clocker_clk1[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] - end - attribute \src "ls180.v:1213.5-1213.36" - process $proc$ls180.v:1213$3575 - assign { } { } - assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] - end - attribute \src "ls180.v:1217.5-1217.40" - process $proc$ls180.v:1217$3576 - assign { } { } - assign $0\main_sdphy_init_initialize_w[0:0] 1'0 - sync always - update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] - sync init - end - attribute \src "ls180.v:1222.5-1222.48" - process $proc$ls180.v:1222$3577 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1223.5-1223.50" - process $proc$ls180.v:1223$3578 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1224.5-1224.51" - process $proc$ls180.v:1224$3579 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1225.11-1225.57" - process $proc$ls180.v:1225$3580 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 - sync always - sync init - update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] - end - attribute \src "ls180.v:1226.5-1226.52" - process $proc$ls180.v:1226$3581 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - end - attribute \src "ls180.v:1227.11-1227.39" - process $proc$ls180.v:1227$3582 - assign { } { } - assign $1\main_sdphy_init_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] - end - attribute \src "ls180.v:1232.5-1232.48" - process $proc$ls180.v:1232$3583 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1233.5-1233.50" - process $proc$ls180.v:1233$3584 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1234.5-1234.51" - process $proc$ls180.v:1234$3585 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1235.11-1235.57" - process $proc$ls180.v:1235$3586 - assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1236.5-1236.52" - process $proc$ls180.v:1236$3587 - assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1237.5-1237.38" - process $proc$ls180.v:1237$3588 - assign { } { } - assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] - end - attribute \src "ls180.v:1238.5-1238.38" - process $proc$ls180.v:1238$3589 - assign { } { } - assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] - end - attribute \src "ls180.v:1239.5-1239.37" - process $proc$ls180.v:1239$3590 - assign { } { } - assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] - end - attribute \src "ls180.v:1240.11-1240.51" - process $proc$ls180.v:1240$3591 - assign { } { } - assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] - end - attribute \src "ls180.v:1241.5-1241.32" - process $proc$ls180.v:1241$3592 - assign { } { } - assign $1\main_sdphy_cmdw_done[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] - end - attribute \src "ls180.v:1242.11-1242.39" - process $proc$ls180.v:1242$3593 - assign { } { } - assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] - end - attribute \src "ls180.v:1245.5-1245.49" - process $proc$ls180.v:1245$3594 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1246.5-1246.48" - process $proc$ls180.v:1246$3595 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1247.5-1247.55" - process $proc$ls180.v:1247$3596 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1249.5-1249.57" - process $proc$ls180.v:1249$3597 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1250.5-1250.58" - process $proc$ls180.v:1250$3598 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1252.11-1252.64" - process $proc$ls180.v:1252$3599 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1253.5-1253.59" - process $proc$ls180.v:1253$3600 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1255.5-1255.48" - process $proc$ls180.v:1255$3601 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1256.5-1256.50" - process $proc$ls180.v:1256$3602 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1257.5-1257.51" - process $proc$ls180.v:1257$3603 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1258.11-1258.57" - process $proc$ls180.v:1258$3604 - assign { } { } - assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1259.5-1259.52" - process $proc$ls180.v:1259$3605 - assign { } { } - assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1260.5-1260.38" - process $proc$ls180.v:1260$3606 - assign { } { } - assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] - end - attribute \src "ls180.v:1261.5-1261.38" - process $proc$ls180.v:1261$3607 - assign { } { } - assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] - end - attribute \src "ls180.v:1262.5-1262.37" - process $proc$ls180.v:1262$3608 - assign { } { } - assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] - end - attribute \src "ls180.v:1263.11-1263.53" - process $proc$ls180.v:1263$3609 - assign { } { } - assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] - end - attribute \src "ls180.v:1264.5-1264.40" - process $proc$ls180.v:1264$3610 - assign { } { } - assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] - end - attribute \src "ls180.v:1265.5-1265.40" - process $proc$ls180.v:1265$3611 - assign { } { } - assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] - end - attribute \src "ls180.v:1266.5-1266.39" - process $proc$ls180.v:1266$3612 - assign { } { } - assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] - end - attribute \src "ls180.v:1267.11-1267.53" - process $proc$ls180.v:1267$3613 - assign { } { } - assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] - end - attribute \src "ls180.v:1268.11-1268.55" - process $proc$ls180.v:1268$3614 - assign { } { } - assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - sync always - sync init - update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] - end - attribute \src "ls180.v:1269.12-1269.48" - process $proc$ls180.v:1269$3615 - assign { } { } - assign $1\main_sdphy_cmdr_timeout[31:0] 500000 - sync always - sync init - update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] - end - attribute \src "ls180.v:1270.11-1270.39" - process $proc$ls180.v:1270$3616 - assign { } { } - assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] - end - attribute \src "ls180.v:1272.5-1272.46" - process $proc$ls180.v:1272$3617 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:1283.5-1283.53" - process $proc$ls180.v:1283$3618 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - end - attribute \src "ls180.v:1288.5-1288.36" - process $proc$ls180.v:1288$3619 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] - end - attribute \src "ls180.v:1291.5-1291.53" - process $proc$ls180.v:1291$3620 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1292.5-1292.52" - process $proc$ls180.v:1292$3621 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1296.5-1296.55" - process $proc$ls180.v:1296$3622 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - end - attribute \src "ls180.v:1297.5-1297.54" - process $proc$ls180.v:1297$3623 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - end - attribute \src "ls180.v:1298.11-1298.68" - process $proc$ls180.v:1298$3624 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1299.11-1299.81" - process $proc$ls180.v:1299$3625 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1300.11-1300.54" - process $proc$ls180.v:1300$3626 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - end - attribute \src "ls180.v:1302.5-1302.53" - process $proc$ls180.v:1302$3627 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1313.5-1313.49" - process $proc$ls180.v:1313$3628 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - end - attribute \src "ls180.v:1315.5-1315.49" - process $proc$ls180.v:1315$3629 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - end - attribute \src "ls180.v:1316.5-1316.48" - process $proc$ls180.v:1316$3630 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - end - attribute \src "ls180.v:1317.11-1317.62" - process $proc$ls180.v:1317$3631 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1318.5-1318.38" - process $proc$ls180.v:1318$3632 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] - end - attribute \src "ls180.v:1323.5-1323.49" - process $proc$ls180.v:1323$3633 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1324.5-1324.51" - process $proc$ls180.v:1324$3634 - assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1325.5-1325.52" - process $proc$ls180.v:1325$3635 - assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1326.11-1326.58" - process $proc$ls180.v:1326$3636 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - end - attribute \src "ls180.v:1327.5-1327.53" - process $proc$ls180.v:1327$3637 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - end - attribute \src "ls180.v:1328.5-1328.39" - process $proc$ls180.v:1328$3638 - assign { } { } - assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] - end - attribute \src "ls180.v:1329.5-1329.39" - process $proc$ls180.v:1329$3639 - assign { } { } - assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] - end - attribute \src "ls180.v:1330.5-1330.39" - process $proc$ls180.v:1330$3640 - assign { } { } - assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] - end - attribute \src "ls180.v:1331.5-1331.38" - process $proc$ls180.v:1331$3641 - assign { } { } - assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] - end - attribute \src "ls180.v:1332.11-1332.52" - process $proc$ls180.v:1332$3642 - assign { } { } - assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] - end - attribute \src "ls180.v:1333.5-1333.33" - process $proc$ls180.v:1333$3643 - assign { } { } - assign $1\main_sdphy_dataw_stop[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] - end - attribute \src "ls180.v:1334.11-1334.40" - process $proc$ls180.v:1334$3644 - assign { } { } - assign $1\main_sdphy_dataw_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] - end - attribute \src "ls180.v:1335.5-1335.50" - process $proc$ls180.v:1335$3645 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - sync init - end - attribute \src "ls180.v:1337.5-1337.50" - process $proc$ls180.v:1337$3646 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1338.5-1338.49" - process $proc$ls180.v:1338$3647 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1339.5-1339.56" - process $proc$ls180.v:1339$3648 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1340.5-1340.58" - process $proc$ls180.v:1340$3649 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - sync init - end - attribute \src "ls180.v:1341.5-1341.58" - process $proc$ls180.v:1341$3650 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1342.5-1342.59" - process $proc$ls180.v:1342$3651 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1343.11-1343.65" - process $proc$ls180.v:1343$3652 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - sync init - end - attribute \src "ls180.v:1344.11-1344.65" - process $proc$ls180.v:1344$3653 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1345.5-1345.60" - process $proc$ls180.v:1345$3654 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1346.5-1346.34" - process $proc$ls180.v:1346$3655 - assign { } { } - assign $1\main_sdphy_dataw_start[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] - end - attribute \src "ls180.v:1347.5-1347.34" - process $proc$ls180.v:1347$3656 - assign { } { } - assign $1\main_sdphy_dataw_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] - end - attribute \src "ls180.v:1348.5-1348.34" - process $proc$ls180.v:1348$3657 - assign { } { } - assign $1\main_sdphy_dataw_error[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] - end - attribute \src "ls180.v:1350.5-1350.47" - process $proc$ls180.v:1350$3658 - assign { } { } - assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:1361.5-1361.54" - process $proc$ls180.v:1361$3659 - assign { } { } - assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - end - attribute \src "ls180.v:1366.5-1366.37" - process $proc$ls180.v:1366$3660 - assign { } { } - assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] - end - attribute \src "ls180.v:1369.5-1369.54" - process $proc$ls180.v:1369$3661 - assign { } { } - assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1370.5-1370.53" - process $proc$ls180.v:1370$3662 - assign { } { } - assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1374.5-1374.56" - process $proc$ls180.v:1374$3663 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - end - attribute \src "ls180.v:1375.5-1375.55" - process $proc$ls180.v:1375$3664 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - end - attribute \src "ls180.v:1376.11-1376.69" - process $proc$ls180.v:1376$3665 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1377.11-1377.82" - process $proc$ls180.v:1377$3666 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1378.11-1378.55" - process $proc$ls180.v:1378$3667 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] - end - attribute \src "ls180.v:1380.5-1380.54" - process $proc$ls180.v:1380$3668 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1391.5-1391.50" - process $proc$ls180.v:1391$3669 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - end - attribute \src "ls180.v:1393.5-1393.50" - process $proc$ls180.v:1393$3670 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - end - attribute \src "ls180.v:1394.5-1394.49" - process $proc$ls180.v:1394$3671 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - end - attribute \src "ls180.v:1395.11-1395.63" - process $proc$ls180.v:1395$3672 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1396.5-1396.39" - process $proc$ls180.v:1396$3673 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] - end - attribute \src "ls180.v:1399.5-1399.50" - process $proc$ls180.v:1399$3674 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1400.5-1400.49" - process $proc$ls180.v:1400$3675 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1401.5-1401.56" - process $proc$ls180.v:1401$3676 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1403.5-1403.58" - process $proc$ls180.v:1403$3677 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1404.5-1404.59" - process $proc$ls180.v:1404$3678 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1406.11-1406.65" - process $proc$ls180.v:1406$3679 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1407.5-1407.60" - process $proc$ls180.v:1407$3680 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1409.5-1409.49" - process $proc$ls180.v:1409$3681 - assign { } { } - assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1410.5-1410.51" - process $proc$ls180.v:1410$3682 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1411.5-1411.52" - process $proc$ls180.v:1411$3683 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1412.11-1412.58" - process $proc$ls180.v:1412$3684 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1413.5-1413.53" - process $proc$ls180.v:1413$3685 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1414.5-1414.39" - process $proc$ls180.v:1414$3686 - assign { } { } - assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] - end - attribute \src "ls180.v:1415.5-1415.39" - process $proc$ls180.v:1415$3687 - assign { } { } - assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] - end - attribute \src "ls180.v:1416.5-1416.38" - process $proc$ls180.v:1416$3688 - assign { } { } - assign $1\main_sdphy_datar_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] - end - attribute \src "ls180.v:1417.11-1417.61" - process $proc$ls180.v:1417$3689 - assign { } { } - assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] - end - attribute \src "ls180.v:1418.5-1418.41" - process $proc$ls180.v:1418$3690 - assign { } { } - assign $1\main_sdphy_datar_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] - end - attribute \src "ls180.v:1419.5-1419.41" - process $proc$ls180.v:1419$3691 - assign { } { } - assign $1\main_sdphy_datar_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] - end - attribute \src "ls180.v:1420.5-1420.41" - process $proc$ls180.v:1420$3692 - assign { } { } - assign $0\main_sdphy_datar_source_first[0:0] 1'0 - sync always - update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] - sync init - end - attribute \src "ls180.v:1421.5-1421.40" - process $proc$ls180.v:1421$3693 - assign { } { } - assign $1\main_sdphy_datar_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] - end - attribute \src "ls180.v:1422.11-1422.54" - process $proc$ls180.v:1422$3694 - assign { } { } - assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] - end - attribute \src "ls180.v:1423.11-1423.56" - process $proc$ls180.v:1423$3695 - assign { } { } - assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 - sync always - sync init - update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] - end - attribute \src "ls180.v:1424.5-1424.33" - process $proc$ls180.v:1424$3696 - assign { } { } - assign $1\main_sdphy_datar_stop[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] - end - attribute \src "ls180.v:1425.12-1425.49" - process $proc$ls180.v:1425$3697 - assign { } { } - assign $1\main_sdphy_datar_timeout[31:0] 500000 - sync always - sync init - update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] - end - attribute \src "ls180.v:1426.11-1426.41" - process $proc$ls180.v:1426$3698 - assign { } { } - assign $1\main_sdphy_datar_count[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] - end - attribute \src "ls180.v:1428.5-1428.48" - process $proc$ls180.v:1428$3699 - assign { } { } - assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:1439.5-1439.55" - process $proc$ls180.v:1439$3700 - assign { } { } - assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] - end - attribute \src "ls180.v:1444.5-1444.38" - process $proc$ls180.v:1444$3701 - assign { } { } - assign $1\main_sdphy_datar_datar_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] - end - attribute \src "ls180.v:1447.5-1447.55" - process $proc$ls180.v:1447$3702 - assign { } { } - assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1448.5-1448.54" - process $proc$ls180.v:1448$3703 - assign { } { } - assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1452.5-1452.57" - process $proc$ls180.v:1452$3704 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] - end - attribute \src "ls180.v:1453.5-1453.56" - process $proc$ls180.v:1453$3705 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] - end - attribute \src "ls180.v:1454.11-1454.70" - process $proc$ls180.v:1454$3706 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1455.11-1455.83" - process $proc$ls180.v:1455$3707 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - end - attribute \src "ls180.v:1456.5-1456.50" - process $proc$ls180.v:1456$3708 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] - end - attribute \src "ls180.v:1458.5-1458.55" - process $proc$ls180.v:1458$3709 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1469.5-1469.51" - process $proc$ls180.v:1469$3710 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] - end - attribute \src "ls180.v:1471.5-1471.51" - process $proc$ls180.v:1471$3711 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] - end - attribute \src "ls180.v:1472.5-1472.50" - process $proc$ls180.v:1472$3712 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] - end - attribute \src "ls180.v:1473.11-1473.64" - process $proc$ls180.v:1473$3713 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1474.5-1474.40" - process $proc$ls180.v:1474$3714 - assign { } { } - assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] - end - attribute \src "ls180.v:1476.5-1476.35" - process $proc$ls180.v:1476$3715 - assign { } { } - assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 - sync always - sync init - update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] - end - attribute \src "ls180.v:1479.11-1479.42" - process $proc$ls180.v:1479$3716 - assign { } { } - assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 - sync always - sync init - update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] - end - attribute \src "ls180.v:1492.12-1492.52" - process $proc$ls180.v:1492$3717 - assign { } { } - assign $1\main_sdcore_cmd_argument_storage[31:0] 0 - sync always - sync init - update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] - end - attribute \src "ls180.v:1493.5-1493.39" - process $proc$ls180.v:1493$3718 - assign { } { } - assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] - end - attribute \src "ls180.v:1494.12-1494.51" - process $proc$ls180.v:1494$3719 - assign { } { } - assign $1\main_sdcore_cmd_command_storage[31:0] 0 - sync always - sync init - update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] - end - attribute \src "ls180.v:1495.5-1495.38" - process $proc$ls180.v:1495$3720 - assign { } { } - assign $1\main_sdcore_cmd_command_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] - end - attribute \src "ls180.v:1499.5-1499.34" - process $proc$ls180.v:1499$3721 - assign { } { } - assign $0\main_sdcore_cmd_send_w[0:0] 1'0 - sync always - update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] - sync init - end - attribute \src "ls180.v:1500.13-1500.53" - process $proc$ls180.v:1500$3722 - assign { } { } - assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] - end - attribute \src "ls180.v:1506.11-1506.51" - process $proc$ls180.v:1506$3723 - assign { } { } - assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 - sync always - sync init - update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] - end - attribute \src "ls180.v:1507.5-1507.39" - process $proc$ls180.v:1507$3724 - assign { } { } - assign $1\main_sdcore_block_length_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] - end - attribute \src "ls180.v:1508.12-1508.51" - process $proc$ls180.v:1508$3725 - assign { } { } - assign $1\main_sdcore_block_count_storage[31:0] 0 - sync always - sync init - update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] - end - attribute \src "ls180.v:1509.5-1509.38" - process $proc$ls180.v:1509$3726 - assign { } { } - assign $1\main_sdcore_block_count_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] - end - attribute \src "ls180.v:1510.11-1510.51" - process $proc$ls180.v:1510$3727 - assign { } { } - assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - sync always - sync init - update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - end - attribute \src "ls180.v:1552.11-1552.47" - process $proc$ls180.v:1552$3728 - assign { } { } - assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - sync always - sync init - update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] - end - attribute \src "ls180.v:1556.5-1556.49" - process $proc$ls180.v:1556$3729 - assign { } { } - assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] - end - attribute \src "ls180.v:1560.5-1560.51" - process $proc$ls180.v:1560$3730 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] - end - attribute \src "ls180.v:1561.5-1561.51" - process $proc$ls180.v:1561$3731 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] - end - attribute \src "ls180.v:1562.5-1562.51" - process $proc$ls180.v:1562$3732 - assign { } { } - assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 - sync always - update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] - sync init - end - attribute \src "ls180.v:1563.5-1563.50" - process $proc$ls180.v:1563$3733 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] - end - attribute \src "ls180.v:1564.11-1564.64" - process $proc$ls180.v:1564$3734 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - end - attribute \src "ls180.v:1565.11-1565.48" - process $proc$ls180.v:1565$3735 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] - end - attribute \src "ls180.v:1566.12-1566.59" - process $proc$ls180.v:1566$3736 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - end - attribute \src "ls180.v:1570.12-1570.55" - process $proc$ls180.v:1570$3737 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - end - attribute \src "ls180.v:1573.12-1573.59" - process $proc$ls180.v:1573$3738 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - end - attribute \src "ls180.v:1577.12-1577.55" - process $proc$ls180.v:1577$3739 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - end - attribute \src "ls180.v:1580.12-1580.59" - process $proc$ls180.v:1580$3740 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - end - attribute \src "ls180.v:1584.12-1584.55" - process $proc$ls180.v:1584$3741 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - end - attribute \src "ls180.v:1587.12-1587.59" - process $proc$ls180.v:1587$3742 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - end - attribute \src "ls180.v:1591.12-1591.55" - process $proc$ls180.v:1591$3743 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - end - attribute \src "ls180.v:1594.12-1594.54" - process $proc$ls180.v:1594$3744 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - end - attribute \src "ls180.v:1595.12-1595.54" - process $proc$ls180.v:1595$3745 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - end - attribute \src "ls180.v:1596.12-1596.54" - process $proc$ls180.v:1596$3746 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - end - attribute \src "ls180.v:1597.12-1597.54" - process $proc$ls180.v:1597$3747 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - end - attribute \src "ls180.v:1598.5-1598.48" - process $proc$ls180.v:1598$3748 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] - end - attribute \src "ls180.v:1599.5-1599.48" - process $proc$ls180.v:1599$3749 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] - end - attribute \src "ls180.v:1600.5-1600.48" - process $proc$ls180.v:1600$3750 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] - end - attribute \src "ls180.v:1601.5-1601.47" - process $proc$ls180.v:1601$3751 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] - end - attribute \src "ls180.v:1602.11-1602.61" - process $proc$ls180.v:1602$3752 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - end - attribute \src "ls180.v:1603.5-1603.50" - process $proc$ls180.v:1603$3753 - assign { } { } - assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] - end - attribute \src "ls180.v:1605.5-1605.50" - process $proc$ls180.v:1605$3754 - assign { } { } - assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 - sync always - update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] - sync init - end - attribute \src "ls180.v:1608.11-1608.47" - process $proc$ls180.v:1608$3755 - assign { } { } - assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] - end - attribute \src "ls180.v:1609.11-1609.47" - process $proc$ls180.v:1609$3756 - assign { } { } - assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - sync always - sync init - update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] - end - attribute \src "ls180.v:1610.12-1610.58" - process $proc$ls180.v:1610$3757 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - end - attribute \src "ls180.v:1614.12-1614.54" - process $proc$ls180.v:1614$3758 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] - end - attribute \src "ls180.v:1615.5-1615.46" - process $proc$ls180.v:1615$3759 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] - end - attribute \src "ls180.v:1617.12-1617.58" - process $proc$ls180.v:1617$3760 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - end - attribute \src "ls180.v:1621.12-1621.54" - process $proc$ls180.v:1621$3761 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] - end - attribute \src "ls180.v:1622.5-1622.46" - process $proc$ls180.v:1622$3762 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] - end - attribute \src "ls180.v:1624.12-1624.58" - process $proc$ls180.v:1624$3763 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - end - attribute \src "ls180.v:1628.12-1628.54" - process $proc$ls180.v:1628$3764 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] - end - attribute \src "ls180.v:1629.5-1629.46" - process $proc$ls180.v:1629$3765 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] - end - attribute \src "ls180.v:1631.12-1631.58" - process $proc$ls180.v:1631$3766 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - end - attribute \src "ls180.v:1635.12-1635.54" - process $proc$ls180.v:1635$3767 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] - end - attribute \src "ls180.v:1636.5-1636.46" - process $proc$ls180.v:1636$3768 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] - end - attribute \src "ls180.v:1638.12-1638.53" - process $proc$ls180.v:1638$3769 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] - end - attribute \src "ls180.v:1639.12-1639.53" - process $proc$ls180.v:1639$3770 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] - end - attribute \src "ls180.v:1640.12-1640.53" - process $proc$ls180.v:1640$3771 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] - end - attribute \src "ls180.v:1641.12-1641.53" - process $proc$ls180.v:1641$3772 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] - end - attribute \src "ls180.v:1642.5-1642.43" - process $proc$ls180.v:1642$3773 - assign { } { } - assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] - end - attribute \src "ls180.v:1643.12-1643.51" - process $proc$ls180.v:1643$3774 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] - end - attribute \src "ls180.v:1644.12-1644.51" - process $proc$ls180.v:1644$3775 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] - end - attribute \src "ls180.v:1645.12-1645.51" - process $proc$ls180.v:1645$3776 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] - end - attribute \src "ls180.v:1646.12-1646.51" - process $proc$ls180.v:1646$3777 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] - end - attribute \src "ls180.v:1648.11-1648.39" - process $proc$ls180.v:1648$3778 - assign { } { } - assign $1\main_sdcore_cmd_count[2:0] 3'000 - sync always - sync init - update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] - end - attribute \src "ls180.v:1649.5-1649.32" - process $proc$ls180.v:1649$3779 - assign { } { } - assign $1\main_sdcore_cmd_done[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] - end - attribute \src "ls180.v:1650.5-1650.33" - process $proc$ls180.v:1650$3780 - assign { } { } - assign $1\main_sdcore_cmd_error[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] - end - attribute \src "ls180.v:1651.5-1651.35" - process $proc$ls180.v:1651$3781 - assign { } { } - assign $1\main_sdcore_cmd_timeout[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] - end - attribute \src "ls180.v:1653.12-1653.42" - process $proc$ls180.v:1653$3782 - assign { } { } - assign $1\main_sdcore_data_count[31:0] 0 - sync always - sync init - update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] - end - attribute \src "ls180.v:1654.5-1654.33" - process $proc$ls180.v:1654$3783 - assign { } { } - assign $1\main_sdcore_data_done[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] - end - attribute \src "ls180.v:1655.5-1655.34" - process $proc$ls180.v:1655$3784 - assign { } { } - assign $1\main_sdcore_data_error[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] - end - attribute \src "ls180.v:1656.5-1656.36" - process $proc$ls180.v:1656$3785 - assign { } { } - assign $1\main_sdcore_data_timeout[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] - end - attribute \src "ls180.v:1665.11-1665.41" - process $proc$ls180.v:1665$3786 - assign { } { } - assign $0\main_interface0_bus_cti[2:0] 3'000 - sync always - update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] - sync init - end - attribute \src "ls180.v:1666.11-1666.41" - process $proc$ls180.v:1666$3787 - assign { } { } - assign $0\main_interface0_bus_bte[1:0] 2'00 - sync always - update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] - sync init - end - attribute \src "ls180.v:1689.11-1689.45" - process $proc$ls180.v:1689$3788 - assign { } { } - assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 - sync always - sync init - update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] - end - attribute \src "ls180.v:1690.5-1690.41" - process $proc$ls180.v:1690$3789 - assign { } { } - assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 - sync always - update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1691.11-1691.47" - process $proc$ls180.v:1691$3790 - assign { } { } - assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] - end - attribute \src "ls180.v:1692.11-1692.47" - process $proc$ls180.v:1692$3791 - assign { } { } - assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] - end - attribute \src "ls180.v:1693.11-1693.50" - process $proc$ls180.v:1693$3792 - assign { } { } - assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:171.12-171.74" - process $proc$ls180.v:171$3152 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - sync init - end - attribute \src "ls180.v:1713.5-1713.51" - process $proc$ls180.v:1713$3793 - assign { } { } - assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] - end - attribute \src "ls180.v:1714.5-1714.50" - process $proc$ls180.v:1714$3794 - assign { } { } - assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] - end - attribute \src "ls180.v:1715.12-1715.66" - process $proc$ls180.v:1715$3795 - assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[63:0] - end - attribute \src "ls180.v:1716.11-1716.77" - process $proc$ls180.v:1716$3796 - assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1717.11-1717.50" - process $proc$ls180.v:1717$3797 - assign { } { } - assign $1\main_sdblock2mem_converter_demux[2:0] 3'000 - sync always - sync init - update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[2:0] - end - attribute \src "ls180.v:1719.5-1719.49" - process $proc$ls180.v:1719$3798 - assign { } { } - assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1725.5-1725.45" - process $proc$ls180.v:1725$3799 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] - end - attribute \src "ls180.v:1727.12-1727.62" - process $proc$ls180.v:1727$3800 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 - sync always - sync init - update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] - end - attribute \src "ls180.v:1728.12-1728.60" - process $proc$ls180.v:1728$3801 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] - end - attribute \src "ls180.v:1730.5-1730.57" - process $proc$ls180.v:1730$3802 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - end - attribute \src "ls180.v:1734.12-1734.67" - process $proc$ls180.v:1734$3803 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - end - attribute \src "ls180.v:1735.5-1735.54" - process $proc$ls180.v:1735$3804 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - end - attribute \src "ls180.v:1736.12-1736.69" - process $proc$ls180.v:1736$3805 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - end - attribute \src "ls180.v:1737.5-1737.56" - process $proc$ls180.v:1737$3806 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - end - attribute \src "ls180.v:1738.5-1738.61" - process $proc$ls180.v:1738$3807 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - end - attribute \src "ls180.v:1739.5-1739.56" - process $proc$ls180.v:1739$3808 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - end - attribute \src "ls180.v:1740.5-1740.53" - process $proc$ls180.v:1740$3809 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - end - attribute \src "ls180.v:1742.5-1742.59" - process $proc$ls180.v:1742$3810 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - end - attribute \src "ls180.v:1743.5-1743.54" - process $proc$ls180.v:1743$3811 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - end - attribute \src "ls180.v:1745.12-1745.61" - process $proc$ls180.v:1745$3812 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - end - attribute \src "ls180.v:1748.12-1748.43" - process $proc$ls180.v:1748$3813 - assign { } { } - assign $1\main_interface1_bus_adr[31:0] 0 - sync always - sync init - update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] - end - attribute \src "ls180.v:1749.12-1749.45" - process $proc$ls180.v:1749$3814 - assign { } { } - assign $0\main_interface1_bus_dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] - sync init - end - attribute \src "ls180.v:175.5-175.69" - process $proc$ls180.v:175$3153 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - sync init - end - attribute \src "ls180.v:1751.11-1751.41" - process $proc$ls180.v:1751$3815 - assign { } { } - assign $1\main_interface1_bus_sel[7:0] 8'00000000 - sync always - sync init - update \main_interface1_bus_sel $1\main_interface1_bus_sel[7:0] - end - attribute \src "ls180.v:1752.5-1752.35" - process $proc$ls180.v:1752$3816 - assign { } { } - assign $1\main_interface1_bus_cyc[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] - end - attribute \src "ls180.v:1753.5-1753.35" - process $proc$ls180.v:1753$3817 - assign { } { } - assign $1\main_interface1_bus_stb[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] - end - attribute \src "ls180.v:1755.5-1755.34" - process $proc$ls180.v:1755$3818 - assign { } { } - assign $1\main_interface1_bus_we[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] - end - attribute \src "ls180.v:1756.11-1756.41" - process $proc$ls180.v:1756$3819 - assign { } { } - assign $0\main_interface1_bus_cti[2:0] 3'000 - sync always - update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] - sync init - end - attribute \src "ls180.v:1757.11-1757.41" - process $proc$ls180.v:1757$3820 - assign { } { } - assign $0\main_interface1_bus_bte[1:0] 2'00 - sync always - update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] - sync init - end - attribute \src "ls180.v:1764.5-1764.43" - process $proc$ls180.v:1764$3821 - assign { } { } - assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] - end - attribute \src "ls180.v:1765.5-1765.43" - process $proc$ls180.v:1765$3822 - assign { } { } - assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] - end - attribute \src "ls180.v:1766.5-1766.42" - process $proc$ls180.v:1766$3823 - assign { } { } - assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] - end - attribute \src "ls180.v:1767.12-1767.61" - process $proc$ls180.v:1767$3824 - assign { } { } - assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] - end - attribute \src "ls180.v:1768.5-1768.45" - process $proc$ls180.v:1768$3825 - assign { } { } - assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] - end - attribute \src "ls180.v:1770.5-1770.45" - process $proc$ls180.v:1770$3826 - assign { } { } - assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 - sync always - update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] - sync init - end - attribute \src "ls180.v:1771.5-1771.44" - process $proc$ls180.v:1771$3827 - assign { } { } - assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] - end - attribute \src "ls180.v:1772.12-1772.60" - process $proc$ls180.v:1772$3828 - assign { } { } - assign $1\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[63:0] - end - attribute \src "ls180.v:1773.12-1773.45" - process $proc$ls180.v:1773$3829 - assign { } { } - assign $1\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[63:0] - end - attribute \src "ls180.v:1774.12-1774.53" - process $proc$ls180.v:1774$3830 - assign { } { } - assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] - end - attribute \src "ls180.v:1775.5-1775.40" - process $proc$ls180.v:1775$3831 - assign { } { } - assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] - end - attribute \src "ls180.v:1776.12-1776.55" - process $proc$ls180.v:1776$3832 - assign { } { } - assign $1\main_sdmem2block_dma_length_storage[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] - end - attribute \src "ls180.v:1777.5-1777.42" - process $proc$ls180.v:1777$3833 - assign { } { } - assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] - end - attribute \src "ls180.v:1778.5-1778.47" - process $proc$ls180.v:1778$3834 - assign { } { } - assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] - end - attribute \src "ls180.v:1779.5-1779.42" - process $proc$ls180.v:1779$3835 - assign { } { } - assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] - end - attribute \src "ls180.v:1780.5-1780.44" - process $proc$ls180.v:1780$3836 - assign { } { } - assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] - end - attribute \src "ls180.v:1782.5-1782.45" - process $proc$ls180.v:1782$3837 - assign { } { } - assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] - end - attribute \src "ls180.v:1783.5-1783.40" - process $proc$ls180.v:1783$3838 - assign { } { } - assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] - end - attribute \src "ls180.v:1787.12-1787.47" - process $proc$ls180.v:1787$3839 - assign { } { } - assign $1\main_sdmem2block_dma_offset[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] - end - attribute \src "ls180.v:1799.11-1799.64" - process $proc$ls180.v:1799$3840 - assign { } { } - assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1801.11-1801.48" - process $proc$ls180.v:1801$3841 - assign { } { } - assign $1\main_sdmem2block_converter_mux[2:0] 3'000 - sync always - sync init - update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] - end - attribute \src "ls180.v:1825.11-1825.45" - process $proc$ls180.v:1825$3842 - assign { } { } - assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 - sync always - sync init - update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] - end - attribute \src "ls180.v:1826.5-1826.41" - process $proc$ls180.v:1826$3843 - assign { } { } - assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 - sync always - update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1827.11-1827.47" - process $proc$ls180.v:1827$3844 - assign { } { } - assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] - end - attribute \src "ls180.v:1828.11-1828.47" - process $proc$ls180.v:1828$3845 - assign { } { } - assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] - end - attribute \src "ls180.v:1829.11-1829.50" - process $proc$ls180.v:1829$3846 - assign { } { } - assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:1842.5-1842.36" - process $proc$ls180.v:1842$3847 - assign { } { } - assign $1\builder_converter0_state[0:0] 1'0 - sync always - sync init - update \builder_converter0_state $1\builder_converter0_state[0:0] - end - attribute \src "ls180.v:1843.5-1843.41" - process $proc$ls180.v:1843$3848 - assign { } { } - assign $1\builder_converter0_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] - end - attribute \src "ls180.v:1844.5-1844.57" - process $proc$ls180.v:1844$3849 - assign { } { } - assign $1\main_converter0_counter_converter0_next_value[0:0] 1'0 - sync always - sync init - update \main_converter0_counter_converter0_next_value $1\main_converter0_counter_converter0_next_value[0:0] - end - attribute \src "ls180.v:1845.5-1845.60" - process $proc$ls180.v:1845$3850 - assign { } { } - assign $1\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_converter0_counter_converter0_next_value_ce $1\main_converter0_counter_converter0_next_value_ce[0:0] - end - attribute \src "ls180.v:1846.5-1846.36" - process $proc$ls180.v:1846$3851 - assign { } { } - assign $1\builder_converter1_state[0:0] 1'0 - sync always - sync init - update \builder_converter1_state $1\builder_converter1_state[0:0] - end - attribute \src "ls180.v:1847.5-1847.41" - process $proc$ls180.v:1847$3852 - assign { } { } - assign $1\builder_converter1_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] - end - attribute \src "ls180.v:1848.5-1848.57" - process $proc$ls180.v:1848$3853 - assign { } { } - assign $1\main_converter1_counter_converter1_next_value[0:0] 1'0 - sync always - sync init - update \main_converter1_counter_converter1_next_value $1\main_converter1_counter_converter1_next_value[0:0] - end - attribute \src "ls180.v:1849.5-1849.60" - process $proc$ls180.v:1849$3854 - assign { } { } - assign $1\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_converter1_counter_converter1_next_value_ce $1\main_converter1_counter_converter1_next_value_ce[0:0] - end - attribute \src "ls180.v:1850.5-1850.36" - process $proc$ls180.v:1850$3855 - assign { } { } - assign $1\builder_converter2_state[0:0] 1'0 - sync always - sync init - update \builder_converter2_state $1\builder_converter2_state[0:0] - end - attribute \src "ls180.v:1851.5-1851.41" - process $proc$ls180.v:1851$3856 - assign { } { } - assign $1\builder_converter2_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] - end - attribute \src "ls180.v:1852.5-1852.60" - process $proc$ls180.v:1852$3857 - assign { } { } - assign $1\main_socbushandler_counter_converter2_next_value[0:0] 1'0 - sync always - sync init - update \main_socbushandler_counter_converter2_next_value $1\main_socbushandler_counter_converter2_next_value[0:0] - end - attribute \src "ls180.v:1853.5-1853.63" - process $proc$ls180.v:1853$3858 - assign { } { } - assign $1\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_socbushandler_counter_converter2_next_value_ce $1\main_socbushandler_counter_converter2_next_value_ce[0:0] - end - attribute \src "ls180.v:1854.11-1854.41" - process $proc$ls180.v:1854$3859 - assign { } { } - assign $1\builder_refresher_state[1:0] 2'00 - sync always - sync init - update \builder_refresher_state $1\builder_refresher_state[1:0] - end - attribute \src "ls180.v:1855.11-1855.46" - process $proc$ls180.v:1855$3860 - assign { } { } - assign $1\builder_refresher_next_state[1:0] 2'00 - sync always - sync init - update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] - end - attribute \src "ls180.v:1856.11-1856.44" - process $proc$ls180.v:1856$3861 - assign { } { } - assign $1\builder_bankmachine0_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] - end - attribute \src "ls180.v:1857.11-1857.49" - process $proc$ls180.v:1857$3862 - assign { } { } - assign $1\builder_bankmachine0_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] - end - attribute \src "ls180.v:1858.11-1858.44" - process $proc$ls180.v:1858$3863 - assign { } { } - assign $1\builder_bankmachine1_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] - end - attribute \src "ls180.v:1859.11-1859.49" - process $proc$ls180.v:1859$3864 - assign { } { } - assign $1\builder_bankmachine1_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] - end - attribute \src "ls180.v:1860.11-1860.44" - process $proc$ls180.v:1860$3865 - assign { } { } - assign $1\builder_bankmachine2_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] - end - attribute \src "ls180.v:1861.11-1861.49" - process $proc$ls180.v:1861$3866 - assign { } { } - assign $1\builder_bankmachine2_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] - end - attribute \src "ls180.v:1862.11-1862.44" - process $proc$ls180.v:1862$3867 - assign { } { } - assign $1\builder_bankmachine3_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] - end - attribute \src "ls180.v:1863.11-1863.49" - process $proc$ls180.v:1863$3868 - assign { } { } - assign $1\builder_bankmachine3_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] - end - attribute \src "ls180.v:1864.11-1864.43" - process $proc$ls180.v:1864$3869 - assign { } { } - assign $1\builder_multiplexer_state[2:0] 3'000 - sync always - sync init - update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] - end - attribute \src "ls180.v:1865.11-1865.48" - process $proc$ls180.v:1865$3870 - assign { } { } - assign $1\builder_multiplexer_next_state[2:0] 3'000 - sync always - sync init - update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] - end - attribute \src "ls180.v:1878.5-1878.27" - process $proc$ls180.v:1878$3871 - assign { } { } - assign $0\builder_locked0[0:0] 1'0 - sync always - update \builder_locked0 $0\builder_locked0[0:0] - sync init - end - attribute \src "ls180.v:1879.5-1879.27" - process $proc$ls180.v:1879$3872 - assign { } { } - assign $0\builder_locked1[0:0] 1'0 - sync always - update \builder_locked1 $0\builder_locked1[0:0] - sync init - end - attribute \src "ls180.v:1880.5-1880.27" - process $proc$ls180.v:1880$3873 - assign { } { } - assign $0\builder_locked2[0:0] 1'0 - sync always - update \builder_locked2 $0\builder_locked2[0:0] - sync init - end - attribute \src "ls180.v:1881.5-1881.27" - process $proc$ls180.v:1881$3874 - assign { } { } - assign $0\builder_locked3[0:0] 1'0 - sync always - update \builder_locked3 $0\builder_locked3[0:0] - sync init - end - attribute \src "ls180.v:1882.5-1882.42" - process $proc$ls180.v:1882$3875 - assign { } { } - assign $1\builder_new_master_wdata_ready[0:0] 1'0 - sync always - sync init - update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] - end - attribute \src "ls180.v:1883.5-1883.43" - process $proc$ls180.v:1883$3876 - assign { } { } - assign $1\builder_new_master_rdata_valid0[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] - end - attribute \src "ls180.v:1884.5-1884.43" - process $proc$ls180.v:1884$3877 - assign { } { } - assign $1\builder_new_master_rdata_valid1[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] - end - attribute \src "ls180.v:1885.5-1885.43" - process $proc$ls180.v:1885$3878 - assign { } { } - assign $1\builder_new_master_rdata_valid2[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] - end - attribute \src "ls180.v:1886.5-1886.43" - process $proc$ls180.v:1886$3879 - assign { } { } - assign $1\builder_new_master_rdata_valid3[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] - end - attribute \src "ls180.v:1887.5-1887.35" - process $proc$ls180.v:1887$3880 - assign { } { } - assign $1\builder_converter_state[0:0] 1'0 - sync always - sync init - update \builder_converter_state $1\builder_converter_state[0:0] - end - attribute \src "ls180.v:1888.5-1888.40" - process $proc$ls180.v:1888$3881 - assign { } { } - assign $1\builder_converter_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter_next_state $1\builder_converter_next_state[0:0] - end - attribute \src "ls180.v:1889.5-1889.55" - process $proc$ls180.v:1889$3882 - assign { } { } - assign $1\main_converter_counter_converter_next_value[0:0] 1'0 - sync always - sync init - update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] - end - attribute \src "ls180.v:189.12-189.78" - process $proc$ls180.v:189$3154 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] - sync init - end - attribute \src "ls180.v:1890.5-1890.58" - process $proc$ls180.v:1890$3883 - assign { } { } - assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] - end - attribute \src "ls180.v:1891.11-1891.42" - process $proc$ls180.v:1891$3884 - assign { } { } - assign $1\builder_spimaster0_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] - end - attribute \src "ls180.v:1892.11-1892.47" - process $proc$ls180.v:1892$3885 - assign { } { } - assign $1\builder_spimaster0_next_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] - end - attribute \src "ls180.v:1893.11-1893.62" - process $proc$ls180.v:1893$3886 - assign { } { } - assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 - sync always - sync init - update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] - end - attribute \src "ls180.v:1894.5-1894.59" - process $proc$ls180.v:1894$3887 - assign { } { } - assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] - end - attribute \src "ls180.v:1895.11-1895.42" - process $proc$ls180.v:1895$3888 - assign { } { } - assign $1\builder_spimaster1_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] - end - attribute \src "ls180.v:1896.11-1896.47" - process $proc$ls180.v:1896$3889 - assign { } { } - assign $1\builder_spimaster1_next_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] - end - attribute \src "ls180.v:1897.11-1897.60" - process $proc$ls180.v:1897$3890 - assign { } { } - assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 - sync always - sync init - update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] - end - attribute \src "ls180.v:1898.5-1898.57" - process $proc$ls180.v:1898$3891 - assign { } { } - assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] - end - attribute \src "ls180.v:1899.5-1899.41" - process $proc$ls180.v:1899$3892 - assign { } { } - assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] - end - attribute \src "ls180.v:1900.5-1900.46" - process $proc$ls180.v:1900$3893 - assign { } { } - assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] - end - attribute \src "ls180.v:1901.11-1901.66" - process $proc$ls180.v:1901$3894 - assign { } { } - assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - end - attribute \src "ls180.v:1902.5-1902.63" - process $proc$ls180.v:1902$3895 - assign { } { } - assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - end - attribute \src "ls180.v:1903.11-1903.47" - process $proc$ls180.v:1903$3896 - assign { } { } - assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 - sync always - sync init - update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] - end - attribute \src "ls180.v:1904.11-1904.52" - process $proc$ls180.v:1904$3897 - assign { } { } - assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] - end - attribute \src "ls180.v:1905.11-1905.66" - process $proc$ls180.v:1905$3898 - assign { } { } - assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - end - attribute \src "ls180.v:1906.5-1906.63" - process $proc$ls180.v:1906$3899 - assign { } { } - assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - end - attribute \src "ls180.v:1907.11-1907.47" - process $proc$ls180.v:1907$3900 - assign { } { } - assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] - end - attribute \src "ls180.v:1908.11-1908.52" - process $proc$ls180.v:1908$3901 - assign { } { } - assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] - end - attribute \src "ls180.v:1909.11-1909.67" - process $proc$ls180.v:1909$3902 - assign { } { } - assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - end - attribute \src "ls180.v:1910.5-1910.64" - process $proc$ls180.v:1910$3903 - assign { } { } - assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - end - attribute \src "ls180.v:1911.12-1911.71" - process $proc$ls180.v:1911$3904 - assign { } { } - assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 - sync always - sync init - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - end - attribute \src "ls180.v:1912.5-1912.66" - process $proc$ls180.v:1912$3905 - assign { } { } - assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - end - attribute \src "ls180.v:1913.5-1913.66" - process $proc$ls180.v:1913$3906 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - end - attribute \src "ls180.v:1914.5-1914.69" - process $proc$ls180.v:1914$3907 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - end - attribute \src "ls180.v:1915.5-1915.41" - process $proc$ls180.v:1915$3908 - assign { } { } - assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] - end - attribute \src "ls180.v:1916.5-1916.46" - process $proc$ls180.v:1916$3909 - assign { } { } - assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] - end - attribute \src "ls180.v:1917.5-1917.66" - process $proc$ls180.v:1917$3910 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - end - attribute \src "ls180.v:1918.5-1918.69" - process $proc$ls180.v:1918$3911 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - end - attribute \src "ls180.v:1919.11-1919.41" - process $proc$ls180.v:1919$3912 - assign { } { } - assign $1\builder_sdphy_fsm_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] - end - attribute \src "ls180.v:1920.11-1920.46" - process $proc$ls180.v:1920$3913 - assign { } { } - assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] - end - attribute \src "ls180.v:1921.11-1921.61" - process $proc$ls180.v:1921$3914 - assign { } { } - assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - end - attribute \src "ls180.v:1922.5-1922.58" - process $proc$ls180.v:1922$3915 - assign { } { } - assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:1923.11-1923.48" - process $proc$ls180.v:1923$3916 - assign { } { } - assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] - end - attribute \src "ls180.v:1924.11-1924.53" - process $proc$ls180.v:1924$3917 - assign { } { } - assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] - end - attribute \src "ls180.v:1925.11-1925.70" - process $proc$ls180.v:1925$3918 - assign { } { } - assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - end - attribute \src "ls180.v:1926.5-1926.66" - process $proc$ls180.v:1926$3919 - assign { } { } - assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - end - attribute \src "ls180.v:1927.12-1927.73" - process $proc$ls180.v:1927$3920 - assign { } { } - assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - sync always - sync init - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - end - attribute \src "ls180.v:1928.5-1928.68" - process $proc$ls180.v:1928$3921 - assign { } { } - assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - end - attribute \src "ls180.v:1929.5-1929.69" - process $proc$ls180.v:1929$3922 - assign { } { } - assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - end - attribute \src "ls180.v:1930.5-1930.72" - process $proc$ls180.v:1930$3923 - assign { } { } - assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - end - attribute \src "ls180.v:1931.5-1931.52" - process $proc$ls180.v:1931$3924 - assign { } { } - assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 - sync always - sync init - update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] - end - attribute \src "ls180.v:1932.5-1932.57" - process $proc$ls180.v:1932$3925 - assign { } { } - assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - end - attribute \src "ls180.v:1933.12-1933.93" - process $proc$ls180.v:1933$3926 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - end - attribute \src "ls180.v:1934.5-1934.88" - process $proc$ls180.v:1934$3927 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - end - attribute \src "ls180.v:1935.12-1935.93" - process $proc$ls180.v:1935$3928 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - end - attribute \src "ls180.v:1936.5-1936.88" - process $proc$ls180.v:1936$3929 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - end - attribute \src "ls180.v:1937.12-1937.93" - process $proc$ls180.v:1937$3930 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - end - attribute \src "ls180.v:1938.5-1938.88" - process $proc$ls180.v:1938$3931 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - end - attribute \src "ls180.v:1939.12-1939.93" - process $proc$ls180.v:1939$3932 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - end - attribute \src "ls180.v:1940.5-1940.88" - process $proc$ls180.v:1940$3933 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - end - attribute \src "ls180.v:1941.11-1941.87" - process $proc$ls180.v:1941$3934 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - end - attribute \src "ls180.v:1942.5-1942.84" - process $proc$ls180.v:1942$3935 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - end - attribute \src "ls180.v:1943.11-1943.42" - process $proc$ls180.v:1943$3936 - assign { } { } - assign $1\builder_sdcore_fsm_state[2:0] 3'000 - sync always - sync init - update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] - end - attribute \src "ls180.v:1944.11-1944.47" - process $proc$ls180.v:1944$3937 - assign { } { } - assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] - end - attribute \src "ls180.v:1945.5-1945.55" - process $proc$ls180.v:1945$3938 - assign { } { } - assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - end - attribute \src "ls180.v:1946.5-1946.58" - process $proc$ls180.v:1946$3939 - assign { } { } - assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - end - attribute \src "ls180.v:1947.5-1947.56" - process $proc$ls180.v:1947$3940 - assign { } { } - assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - end - attribute \src "ls180.v:1948.5-1948.59" - process $proc$ls180.v:1948$3941 - assign { } { } - assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - end - attribute \src "ls180.v:1949.11-1949.62" - process $proc$ls180.v:1949$3942 - assign { } { } - assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - sync always - sync init - update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - end - attribute \src "ls180.v:1950.5-1950.59" - process $proc$ls180.v:1950$3943 - assign { } { } - assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - end - attribute \src "ls180.v:1951.12-1951.65" - process $proc$ls180.v:1951$3944 - assign { } { } - assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - sync always - sync init - update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - end - attribute \src "ls180.v:1952.5-1952.60" - process $proc$ls180.v:1952$3945 - assign { } { } - assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - end - attribute \src "ls180.v:1953.5-1953.56" - process $proc$ls180.v:1953$3946 - assign { } { } - assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - end - attribute \src "ls180.v:1954.5-1954.59" - process $proc$ls180.v:1954$3947 - assign { } { } - assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - end - attribute \src "ls180.v:1955.5-1955.58" - process $proc$ls180.v:1955$3948 - assign { } { } - assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - end - attribute \src "ls180.v:1956.5-1956.61" - process $proc$ls180.v:1956$3949 - assign { } { } - assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - end - attribute \src "ls180.v:1957.5-1957.57" - process $proc$ls180.v:1957$3950 - assign { } { } - assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - end - attribute \src "ls180.v:1958.5-1958.60" - process $proc$ls180.v:1958$3951 - assign { } { } - assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - end - attribute \src "ls180.v:1959.5-1959.59" - process $proc$ls180.v:1959$3952 - assign { } { } - assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - end - attribute \src "ls180.v:1960.5-1960.62" - process $proc$ls180.v:1960$3953 - assign { } { } - assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - end - attribute \src "ls180.v:1961.13-1961.76" - process $proc$ls180.v:1961$3954 - assign { } { } - assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - end - attribute \src "ls180.v:1962.5-1962.69" - process $proc$ls180.v:1962$3955 - assign { } { } - assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - end - attribute \src "ls180.v:1963.11-1963.46" - process $proc$ls180.v:1963$3956 - assign { } { } - assign $1\builder_sdblock2memdma_state[1:0] 2'00 - sync always - sync init - update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] - end - attribute \src "ls180.v:1964.11-1964.51" - process $proc$ls180.v:1964$3957 - assign { } { } - assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] - end - attribute \src "ls180.v:1965.12-1965.87" - process $proc$ls180.v:1965$3958 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - end - attribute \src "ls180.v:1966.5-1966.82" - process $proc$ls180.v:1966$3959 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - end - attribute \src "ls180.v:1967.5-1967.44" - process $proc$ls180.v:1967$3960 - assign { } { } - assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 - sync always - sync init - update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] - end - attribute \src "ls180.v:1968.5-1968.49" - process $proc$ls180.v:1968$3961 - assign { } { } - assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] - end - attribute \src "ls180.v:1969.12-1969.75" - process $proc$ls180.v:1969$3962 - assign { } { } - assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - end - attribute \src "ls180.v:1970.5-1970.70" - process $proc$ls180.v:1970$3963 - assign { } { } - assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:1971.11-1971.60" - process $proc$ls180.v:1971$3964 - assign { } { } - assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - sync always - sync init - update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] - end - attribute \src "ls180.v:1972.11-1972.65" - process $proc$ls180.v:1972$3965 - assign { } { } - assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - end - attribute \src "ls180.v:1973.12-1973.87" - process $proc$ls180.v:1973$3966 - assign { } { } - assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - end - attribute \src "ls180.v:1974.5-1974.82" - process $proc$ls180.v:1974$3967 - assign { } { } - assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - end - attribute \src "ls180.v:1975.12-1975.43" - process $proc$ls180.v:1975$3968 - assign { } { } - assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 - sync always - sync init - update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] - end - attribute \src "ls180.v:1976.5-1976.34" - process $proc$ls180.v:1976$3969 - assign { } { } - assign $1\builder_libresocsim_we[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] - end - attribute \src "ls180.v:1977.11-1977.43" - process $proc$ls180.v:1977$3970 - assign { } { } - assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 - sync always - sync init - update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] - end - attribute \src "ls180.v:1979.12-1979.52" - process $proc$ls180.v:1979$3971 - assign { } { } - assign $0\builder_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000 - sync always - update \builder_libresocsim_wishbone_adr $0\builder_libresocsim_wishbone_adr[29:0] - sync init - end - attribute \src "ls180.v:1980.12-1980.54" - process $proc$ls180.v:1980$3972 - assign { } { } - assign $0\builder_libresocsim_wishbone_dat_w[31:0] 0 - sync always - update \builder_libresocsim_wishbone_dat_w $0\builder_libresocsim_wishbone_dat_w[31:0] - sync init - end - attribute \src "ls180.v:1981.12-1981.54" - process $proc$ls180.v:1981$3973 - assign { } { } - assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 - sync always - sync init - update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] - end - attribute \src "ls180.v:1982.11-1982.50" - process $proc$ls180.v:1982$3974 - assign { } { } - assign $0\builder_libresocsim_wishbone_sel[3:0] 4'0000 - sync always - update \builder_libresocsim_wishbone_sel $0\builder_libresocsim_wishbone_sel[3:0] - sync init - end - attribute \src "ls180.v:1983.5-1983.44" - process $proc$ls180.v:1983$3975 - assign { } { } - assign $0\builder_libresocsim_wishbone_cyc[0:0] 1'0 - sync always - update \builder_libresocsim_wishbone_cyc $0\builder_libresocsim_wishbone_cyc[0:0] - sync init - end - attribute \src "ls180.v:1984.5-1984.44" - process $proc$ls180.v:1984$3976 - assign { } { } - assign $0\builder_libresocsim_wishbone_stb[0:0] 1'0 - sync always - update \builder_libresocsim_wishbone_stb $0\builder_libresocsim_wishbone_stb[0:0] - sync init - end - attribute \src "ls180.v:1985.5-1985.44" - process $proc$ls180.v:1985$3977 - assign { } { } - assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] - end - attribute \src "ls180.v:1986.5-1986.43" - process $proc$ls180.v:1986$3978 - assign { } { } - assign $0\builder_libresocsim_wishbone_we[0:0] 1'0 - sync always - update \builder_libresocsim_wishbone_we $0\builder_libresocsim_wishbone_we[0:0] - sync init - end - attribute \src "ls180.v:1989.12-1989.65" - process $proc$ls180.v:1989$3979 - assign { } { } - assign $0\builder_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - update \builder_libresocsim_converted_interface_dat_r $0\builder_libresocsim_converted_interface_dat_r[63:0] - sync init - end - attribute \src "ls180.v:1993.5-1993.55" - process $proc$ls180.v:1993$3980 - assign { } { } - assign $0\builder_libresocsim_converted_interface_ack[0:0] 1'0 - sync always - update \builder_libresocsim_converted_interface_ack $0\builder_libresocsim_converted_interface_ack[0:0] - sync init - end - attribute \src "ls180.v:1997.5-1997.55" - process $proc$ls180.v:1997$3981 - assign { } { } - assign $0\builder_libresocsim_converted_interface_err[0:0] 1'0 - sync always - update \builder_libresocsim_converted_interface_err $0\builder_libresocsim_converted_interface_err[0:0] - sync init - end - attribute \src "ls180.v:2000.12-2000.40" - process $proc$ls180.v:2000$3982 - assign { } { } - assign $1\builder_shared_dat_r[31:0] 0 - sync always - sync init - update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] - end - attribute \src "ls180.v:2004.5-2004.30" - process $proc$ls180.v:2004$3983 - assign { } { } - assign $1\builder_shared_ack[0:0] 1'0 - sync always - sync init - update \builder_shared_ack $1\builder_shared_ack[0:0] - end - attribute \src "ls180.v:201.5-201.72" - process $proc$ls180.v:201$3155 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - sync init - end - attribute \src "ls180.v:2010.11-2010.31" - process $proc$ls180.v:2010$3984 - assign { } { } - assign $1\builder_grant[2:0] 3'000 - sync always - sync init - update \builder_grant $1\builder_grant[2:0] - end - attribute \src "ls180.v:2011.12-2011.37" - process $proc$ls180.v:2011$3985 - assign { } { } - assign $1\builder_slave_sel[12:0] 13'0000000000000 - sync always - sync init - update \builder_slave_sel $1\builder_slave_sel[12:0] - end - attribute \src "ls180.v:2012.12-2012.39" - process $proc$ls180.v:2012$3986 - assign { } { } - assign $1\builder_slave_sel_r[12:0] 13'0000000000000 - sync always - sync init - update \builder_slave_sel_r $1\builder_slave_sel_r[12:0] - end - attribute \src "ls180.v:2013.5-2013.25" - process $proc$ls180.v:2013$3987 - assign { } { } - assign $1\builder_error[0:0] 1'0 - sync always - sync init - update \builder_error $1\builder_error[0:0] - end - attribute \src "ls180.v:2016.12-2016.39" - process $proc$ls180.v:2016$3988 - assign { } { } - assign $1\builder_count[19:0] 20'11110100001001000000 - sync always - sync init - update \builder_count $1\builder_count[19:0] - end - attribute \src "ls180.v:2020.11-2020.51" - process $proc$ls180.v:2020$3989 - assign { } { } - assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:204.11-204.79" - process $proc$ls180.v:204$3156 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - sync init - end - attribute \src "ls180.v:2061.11-2061.51" - process $proc$ls180.v:2061$3990 - assign { } { } - assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2090.11-2090.51" - process $proc$ls180.v:2090$3991 - assign { } { } - assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2103.11-2103.51" - process $proc$ls180.v:2103$3992 - assign { } { } - assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:213.5-213.40" - process $proc$ls180.v:213$3157 - assign { } { } - assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2144.11-2144.51" - process $proc$ls180.v:2144$3993 - assign { } { } - assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:217.5-217.40" - process $proc$ls180.v:217$3158 - assign { } { } - assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 - sync always - update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:2185.11-2185.51" - process $proc$ls180.v:2185$3994 - assign { } { } - assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:220.11-220.37" - process $proc$ls180.v:220$3159 - assign { } { } - assign $1\main_libresocsim_we[7:0] 8'00000000 - sync always - sync init - update \main_libresocsim_we $1\main_libresocsim_we[7:0] - end - attribute \src "ls180.v:222.12-222.49" - process $proc$ls180.v:222$3160 - assign { } { } - assign $1\main_libresocsim_load_storage[31:0] 0 - sync always - sync init - update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] - end - attribute \src "ls180.v:223.5-223.36" - process $proc$ls180.v:223$3161 - assign { } { } - assign $1\main_libresocsim_load_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] - end - attribute \src "ls180.v:224.12-224.51" - process $proc$ls180.v:224$3162 - assign { } { } - assign $1\main_libresocsim_reload_storage[31:0] 0 - sync always - sync init - update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] - end - attribute \src "ls180.v:225.5-225.38" - process $proc$ls180.v:225$3163 - assign { } { } - assign $1\main_libresocsim_reload_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] - end - attribute \src "ls180.v:2250.11-2250.51" - process $proc$ls180.v:2250$3995 - assign { } { } - assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:226.5-226.39" - process $proc$ls180.v:226$3164 - assign { } { } - assign $1\main_libresocsim_en_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] - end - attribute \src "ls180.v:227.5-227.34" - process $proc$ls180.v:227$3165 - assign { } { } - assign $1\main_libresocsim_en_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] - end - attribute \src "ls180.v:228.5-228.49" - process $proc$ls180.v:228$3166 - assign { } { } - assign $1\main_libresocsim_update_value_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] - end - attribute \src "ls180.v:229.5-229.44" - process $proc$ls180.v:229$3167 - assign { } { } - assign $1\main_libresocsim_update_value_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] - end - attribute \src "ls180.v:230.12-230.49" - process $proc$ls180.v:230$3168 - assign { } { } - assign $1\main_libresocsim_value_status[31:0] 0 - sync always - sync init - update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] - end - attribute \src "ls180.v:234.5-234.41" - process $proc$ls180.v:234$3169 - assign { } { } - assign $1\main_libresocsim_zero_pending[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] - end - attribute \src "ls180.v:236.5-236.39" - process $proc$ls180.v:236$3170 - assign { } { } - assign $1\main_libresocsim_zero_clear[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] - end - attribute \src "ls180.v:237.5-237.45" - process $proc$ls180.v:237$3171 - assign { } { } - assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] - end - attribute \src "ls180.v:2383.11-2383.51" - process $proc$ls180.v:2383$3996 - assign { } { } - assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:246.5-246.49" - process $proc$ls180.v:246$3172 - assign { } { } - assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] - end - attribute \src "ls180.v:2464.11-2464.51" - process $proc$ls180.v:2464$3997 - assign { } { } - assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:247.5-247.44" - process $proc$ls180.v:247$3173 - assign { } { } - assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] - end - attribute \src "ls180.v:248.12-248.42" - process $proc$ls180.v:248$3174 - assign { } { } - assign $1\main_libresocsim_value[31:0] 0 - sync always - sync init - update \main_libresocsim_value $1\main_libresocsim_value[31:0] - end - attribute \src "ls180.v:2481.11-2481.51" - process $proc$ls180.v:2481$3998 - assign { } { } - assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2522.11-2522.52" - process $proc$ls180.v:2522$3999 - assign { } { } - assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:255.5-255.39" - process $proc$ls180.v:255$3175 - assign { } { } - assign $1\main_interface0_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_interface0_ram_bus_ack $1\main_interface0_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2555.11-2555.52" - process $proc$ls180.v:2555$4000 - assign { } { } - assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:259.5-259.39" - process $proc$ls180.v:259$3176 - assign { } { } - assign $0\main_interface0_ram_bus_err[0:0] 1'0 - sync always - update \main_interface0_ram_bus_err $0\main_interface0_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:2596.11-2596.52" - process $proc$ls180.v:2596$4001 - assign { } { } - assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:262.11-262.31" - process $proc$ls180.v:262$3177 - assign { } { } - assign $1\main_sram0_we[7:0] 8'00000000 - sync always - sync init - update \main_sram0_we $1\main_sram0_we[7:0] - end - attribute \src "ls180.v:2661.11-2661.52" - process $proc$ls180.v:2661$4002 - assign { } { } - assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2686.11-2686.52" - process $proc$ls180.v:2686$4003 - assign { } { } - assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:270.5-270.39" - process $proc$ls180.v:270$3178 - assign { } { } - assign $1\main_interface1_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2708.11-2708.31" - process $proc$ls180.v:2708$4004 - assign { } { } - assign $1\builder_state[1:0] 2'00 - sync always - sync init - update \builder_state $1\builder_state[1:0] - end - attribute \src "ls180.v:2709.11-2709.36" - process $proc$ls180.v:2709$4005 - assign { } { } - assign $1\builder_next_state[1:0] 2'00 - sync always - sync init - update \builder_next_state $1\builder_next_state[1:0] - end - attribute \src "ls180.v:2710.11-2710.55" - process $proc$ls180.v:2710$4006 - assign { } { } - assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 - sync always - sync init - update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] - end - attribute \src "ls180.v:2711.5-2711.52" - process $proc$ls180.v:2711$4007 - assign { } { } - assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - end - attribute \src "ls180.v:2712.12-2712.55" - process $proc$ls180.v:2712$4008 - assign { } { } - assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - sync always - sync init - update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] - end - attribute \src "ls180.v:2713.5-2713.50" - process $proc$ls180.v:2713$4009 - assign { } { } - assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] - end - attribute \src "ls180.v:2714.5-2714.46" - process $proc$ls180.v:2714$4010 - assign { } { } - assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] - end - attribute \src "ls180.v:2715.5-2715.49" - process $proc$ls180.v:2715$4011 - assign { } { } - assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] - end - attribute \src "ls180.v:2716.5-2716.41" - process $proc$ls180.v:2716$4012 - assign { } { } - assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] - end - attribute \src "ls180.v:2717.12-2717.49" - process $proc$ls180.v:2717$4013 - assign { } { } - assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:2718.11-2718.47" - process $proc$ls180.v:2718$4014 - assign { } { } - assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 - sync always - sync init - update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] - end - attribute \src "ls180.v:2719.5-2719.41" - process $proc$ls180.v:2719$4015 - assign { } { } - assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:2720.5-2720.41" - process $proc$ls180.v:2720$4016 - assign { } { } - assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:2721.5-2721.41" - process $proc$ls180.v:2721$4017 - assign { } { } - assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:2722.5-2722.39" - process $proc$ls180.v:2722$4018 - assign { } { } - assign $1\builder_comb_t_array_muxed0[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] - end - attribute \src "ls180.v:2723.5-2723.39" - process $proc$ls180.v:2723$4019 - assign { } { } - assign $1\builder_comb_t_array_muxed1[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] - end - attribute \src "ls180.v:2724.5-2724.39" - process $proc$ls180.v:2724$4020 - assign { } { } - assign $1\builder_comb_t_array_muxed2[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] - end - attribute \src "ls180.v:2725.5-2725.41" - process $proc$ls180.v:2725$4021 - assign { } { } - assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:2726.12-2726.49" - process $proc$ls180.v:2726$4022 - assign { } { } - assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] - end - attribute \src "ls180.v:2727.11-2727.47" - process $proc$ls180.v:2727$4023 - assign { } { } - assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 - sync always - sync init - update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] - end - attribute \src "ls180.v:2728.5-2728.41" - process $proc$ls180.v:2728$4024 - assign { } { } - assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] - end - attribute \src "ls180.v:2729.5-2729.42" - process $proc$ls180.v:2729$4025 - assign { } { } - assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] - end - attribute \src "ls180.v:2730.5-2730.42" - process $proc$ls180.v:2730$4026 - assign { } { } - assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] - end - attribute \src "ls180.v:2731.5-2731.39" - process $proc$ls180.v:2731$4027 + attribute \src "ls180.v:132.5-132.61" + process $proc$ls180.v:132$1569 assign { } { } - assign $1\builder_comb_t_array_muxed3[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] 1'0 sync always sync init - update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] + update \libresocsim_libresoc_constraintmanager_sdram_we_n $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] end - attribute \src "ls180.v:2732.5-2732.39" - process $proc$ls180.v:2732$4028 + attribute \src "ls180.v:133.5-133.62" + process $proc$ls180.v:133$1570 assign { } { } - assign $1\builder_comb_t_array_muxed4[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] 1'0 sync always sync init - update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] + update \libresocsim_libresoc_constraintmanager_sdram_ras_n $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] end - attribute \src "ls180.v:2733.5-2733.39" - process $proc$ls180.v:2733$4029 + attribute \src "ls180.v:1335.11-1335.35" + process $proc$ls180.v:1335$2002 assign { } { } - assign $1\builder_comb_t_array_muxed5[0:0] 1'0 + assign $1\libresocsim_state[1:0] 2'00 sync always sync init - update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] + update \libresocsim_state $1\libresocsim_state[1:0] end - attribute \src "ls180.v:2734.12-2734.50" - process $proc$ls180.v:2734$4030 + attribute \src "ls180.v:1336.11-1336.40" + process $proc$ls180.v:1336$2003 assign { } { } - assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + assign $1\libresocsim_next_state[1:0] 2'00 sync always sync init - update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] + update \libresocsim_next_state $1\libresocsim_next_state[1:0] end - attribute \src "ls180.v:2735.5-2735.42" - process $proc$ls180.v:2735$4031 + attribute \src "ls180.v:1337.11-1337.71" + process $proc$ls180.v:1337$2004 assign { } { } - assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 + assign $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] 8'00000000 sync always sync init - update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] + update \libresocsim_libresocsim_dat_w_libresocsim_next_value0 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] end - attribute \src "ls180.v:2736.5-2736.42" - process $proc$ls180.v:2736$4032 + attribute \src "ls180.v:1338.5-1338.68" + process $proc$ls180.v:1338$2005 assign { } { } - assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 + assign $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] + update \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] end - attribute \src "ls180.v:2737.12-2737.50" - process $proc$ls180.v:2737$4033 + attribute \src "ls180.v:1339.12-1339.71" + process $proc$ls180.v:1339$2006 assign { } { } - assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + assign $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000 sync always sync init - update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] + update \libresocsim_libresocsim_adr_libresocsim_next_value1 $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] end - attribute \src "ls180.v:2738.5-2738.42" - process $proc$ls180.v:2738$4034 + attribute \src "ls180.v:134.5-134.62" + process $proc$ls180.v:134$1571 assign { } { } - assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] + update \libresocsim_libresoc_constraintmanager_sdram_cas_n $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] end - attribute \src "ls180.v:2739.5-2739.42" - process $proc$ls180.v:2739$4035 + attribute \src "ls180.v:1340.5-1340.66" + process $proc$ls180.v:1340$2007 assign { } { } - assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 + assign $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] + update \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] end - attribute \src "ls180.v:274.5-274.39" - process $proc$ls180.v:274$3179 + attribute \src "ls180.v:1341.5-1341.62" + process $proc$ls180.v:1341$2008 assign { } { } - assign $0\main_interface1_ram_bus_err[0:0] 1'0 + assign $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0 sync always - update \main_interface1_ram_bus_err $0\main_interface1_ram_bus_err[0:0] sync init + update \libresocsim_libresocsim_we_libresocsim_next_value2 $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] end - attribute \src "ls180.v:2740.12-2740.50" - process $proc$ls180.v:2740$4036 + attribute \src "ls180.v:1342.5-1342.65" + process $proc$ls180.v:1342$2009 assign { } { } - assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + assign $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] + update \libresocsim_libresocsim_we_libresocsim_next_value_ce2 $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] end - attribute \src "ls180.v:2741.5-2741.42" - process $proc$ls180.v:2741$4037 + attribute \src "ls180.v:1343.5-1343.28" + process $proc$ls180.v:1343$2010 assign { } { } - assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 + assign $1\rhs_array_muxed0[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] + update \rhs_array_muxed0 $1\rhs_array_muxed0[0:0] end - attribute \src "ls180.v:2742.5-2742.42" - process $proc$ls180.v:2742$4038 + attribute \src "ls180.v:1344.12-1344.36" + process $proc$ls180.v:1344$2011 assign { } { } - assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 + assign $1\rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init - update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] + update \rhs_array_muxed1 $1\rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2743.12-2743.50" - process $proc$ls180.v:2743$4039 + attribute \src "ls180.v:1345.11-1345.34" + process $proc$ls180.v:1345$2012 assign { } { } - assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + assign $1\rhs_array_muxed2[1:0] 2'00 sync always sync init - update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] + update \rhs_array_muxed2 $1\rhs_array_muxed2[1:0] end - attribute \src "ls180.v:2744.5-2744.42" - process $proc$ls180.v:2744$4040 + attribute \src "ls180.v:1346.5-1346.28" + process $proc$ls180.v:1346$2013 assign { } { } - assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 + assign $1\rhs_array_muxed3[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] + update \rhs_array_muxed3 $1\rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2745.5-2745.42" - process $proc$ls180.v:2745$4041 + attribute \src "ls180.v:1347.5-1347.28" + process $proc$ls180.v:1347$2014 assign { } { } - assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 + assign $1\rhs_array_muxed4[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] + update \rhs_array_muxed4 $1\rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2746.12-2746.50" - process $proc$ls180.v:2746$4042 + attribute \src "ls180.v:1348.5-1348.28" + process $proc$ls180.v:1348$2015 assign { } { } - assign $1\builder_comb_rhs_array_muxed24[31:0] 0 + assign $1\rhs_array_muxed5[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] + update \rhs_array_muxed5 $1\rhs_array_muxed5[0:0] end - attribute \src "ls180.v:2747.12-2747.50" - process $proc$ls180.v:2747$4043 + attribute \src "ls180.v:1349.5-1349.26" + process $proc$ls180.v:1349$2016 assign { } { } - assign $1\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\t_array_muxed0[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[63:0] + update \t_array_muxed0 $1\t_array_muxed0[0:0] end - attribute \src "ls180.v:2748.11-2748.48" - process $proc$ls180.v:2748$4044 + attribute \src "ls180.v:135.5-135.61" + process $proc$ls180.v:135$1572 assign { } { } - assign $1\builder_comb_rhs_array_muxed26[7:0] 8'00000000 + assign $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[7:0] + update \libresocsim_libresoc_constraintmanager_sdram_cs_n $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] end - attribute \src "ls180.v:2749.5-2749.42" - process $proc$ls180.v:2749$4045 + attribute \src "ls180.v:1350.5-1350.26" + process $proc$ls180.v:1350$2017 assign { } { } - assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 + assign $1\t_array_muxed1[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] + update \t_array_muxed1 $1\t_array_muxed1[0:0] end - attribute \src "ls180.v:2750.5-2750.42" - process $proc$ls180.v:2750$4046 + attribute \src "ls180.v:1351.5-1351.26" + process $proc$ls180.v:1351$2018 assign { } { } - assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 + assign $1\t_array_muxed2[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] + update \t_array_muxed2 $1\t_array_muxed2[0:0] end - attribute \src "ls180.v:2751.5-2751.42" - process $proc$ls180.v:2751$4047 + attribute \src "ls180.v:1352.5-1352.28" + process $proc$ls180.v:1352$2019 assign { } { } - assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 + assign $1\rhs_array_muxed6[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] + update \rhs_array_muxed6 $1\rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2752.11-2752.48" - process $proc$ls180.v:2752$4048 + attribute \src "ls180.v:1353.12-1353.36" + process $proc$ls180.v:1353$2020 assign { } { } - assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 + assign $1\rhs_array_muxed7[12:0] 13'0000000000000 sync always sync init - update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] + update \rhs_array_muxed7 $1\rhs_array_muxed7[12:0] end - attribute \src "ls180.v:2753.11-2753.48" - process $proc$ls180.v:2753$4049 + attribute \src "ls180.v:1354.11-1354.34" + process $proc$ls180.v:1354$2021 assign { } { } - assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 + assign $1\rhs_array_muxed8[1:0] 2'00 sync always sync init - update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] + update \rhs_array_muxed8 $1\rhs_array_muxed8[1:0] end - attribute \src "ls180.v:2754.11-2754.47" - process $proc$ls180.v:2754$4050 + attribute \src "ls180.v:1355.5-1355.28" + process $proc$ls180.v:1355$2022 assign { } { } - assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 + assign $1\rhs_array_muxed9[0:0] 1'0 sync always sync init - update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] + update \rhs_array_muxed9 $1\rhs_array_muxed9[0:0] end - attribute \src "ls180.v:2755.12-2755.49" - process $proc$ls180.v:2755$4051 + attribute \src "ls180.v:1356.5-1356.29" + process $proc$ls180.v:1356$2023 assign { } { } - assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + assign $1\rhs_array_muxed10[0:0] 1'0 sync always sync init - update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] + update \rhs_array_muxed10 $1\rhs_array_muxed10[0:0] end - attribute \src "ls180.v:2756.5-2756.41" - process $proc$ls180.v:2756$4052 + attribute \src "ls180.v:1357.5-1357.29" + process $proc$ls180.v:1357$2024 assign { } { } - assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 + assign $1\rhs_array_muxed11[0:0] 1'0 sync always sync init - update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] + update \rhs_array_muxed11 $1\rhs_array_muxed11[0:0] end - attribute \src "ls180.v:2757.5-2757.41" - process $proc$ls180.v:2757$4053 + attribute \src "ls180.v:1358.5-1358.26" + process $proc$ls180.v:1358$2025 assign { } { } - assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 + assign $1\t_array_muxed3[0:0] 1'0 sync always sync init - update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] + update \t_array_muxed3 $1\t_array_muxed3[0:0] end - attribute \src "ls180.v:2758.5-2758.41" - process $proc$ls180.v:2758$4054 + attribute \src "ls180.v:1359.5-1359.26" + process $proc$ls180.v:1359$2026 assign { } { } - assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 + assign $1\t_array_muxed4[0:0] 1'0 sync always sync init - update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] + update \t_array_muxed4 $1\t_array_muxed4[0:0] end - attribute \src "ls180.v:2759.5-2759.41" - process $proc$ls180.v:2759$4055 + attribute \src "ls180.v:136.5-136.60" + process $proc$ls180.v:136$1573 assign { } { } - assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] 1'0 sync always sync init - update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] + update \libresocsim_libresoc_constraintmanager_sdram_cke $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] end - attribute \src "ls180.v:2760.5-2760.41" - process $proc$ls180.v:2760$4056 + attribute \src "ls180.v:1360.5-1360.26" + process $proc$ls180.v:1360$2027 assign { } { } - assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 + assign $1\t_array_muxed5[0:0] 1'0 sync always sync init - update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] + update \t_array_muxed5 $1\t_array_muxed5[0:0] end - attribute \src "ls180.v:2761.5-2761.39" - process $proc$ls180.v:2761$4057 + attribute \src "ls180.v:1361.12-1361.37" + process $proc$ls180.v:1361$2028 assign { } { } - assign $1\builder_sync_f_array_muxed0[0:0] 1'0 + assign $1\rhs_array_muxed12[21:0] 22'0000000000000000000000 sync always sync init - update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] + update \rhs_array_muxed12 $1\rhs_array_muxed12[21:0] end - attribute \src "ls180.v:2762.5-2762.39" - process $proc$ls180.v:2762$4058 + attribute \src "ls180.v:1362.5-1362.29" + process $proc$ls180.v:1362$2029 assign { } { } - assign $1\builder_sync_f_array_muxed1[0:0] 1'0 + assign $1\rhs_array_muxed13[0:0] 1'0 sync always sync init - update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] + update \rhs_array_muxed13 $1\rhs_array_muxed13[0:0] end - attribute \src "ls180.v:277.11-277.31" - process $proc$ls180.v:277$3180 + attribute \src "ls180.v:1363.5-1363.29" + process $proc$ls180.v:1363$2030 assign { } { } - assign $1\main_sram1_we[7:0] 8'00000000 + assign $1\rhs_array_muxed14[0:0] 1'0 sync always sync init - update \main_sram1_we $1\main_sram1_we[7:0] + update \rhs_array_muxed14 $1\rhs_array_muxed14[0:0] end - attribute \src "ls180.v:2819.32-2819.66" - process $proc$ls180.v:2819$4059 + attribute \src "ls180.v:1364.12-1364.37" + process $proc$ls180.v:1364$2031 assign { } { } - assign $1\builder_multiregimpl0_regs0[0:0] 1'0 + assign $1\rhs_array_muxed15[21:0] 22'0000000000000000000000 sync always sync init - update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] + update \rhs_array_muxed15 $1\rhs_array_muxed15[21:0] end - attribute \src "ls180.v:2820.32-2820.66" - process $proc$ls180.v:2820$4060 + attribute \src "ls180.v:1365.5-1365.29" + process $proc$ls180.v:1365$2032 assign { } { } - assign $1\builder_multiregimpl0_regs1[0:0] 1'0 + assign $1\rhs_array_muxed16[0:0] 1'0 sync always sync init - update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] + update \rhs_array_muxed16 $1\rhs_array_muxed16[0:0] end - attribute \src "ls180.v:2821.32-2821.66" - process $proc$ls180.v:2821$4061 + attribute \src "ls180.v:1366.5-1366.29" + process $proc$ls180.v:1366$2033 assign { } { } - assign $1\builder_multiregimpl1_regs0[0:0] 1'0 + assign $1\rhs_array_muxed17[0:0] 1'0 sync always sync init - update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] + update \rhs_array_muxed17 $1\rhs_array_muxed17[0:0] end - attribute \src "ls180.v:2822.32-2822.66" - process $proc$ls180.v:2822$4062 + attribute \src "ls180.v:1367.12-1367.37" + process $proc$ls180.v:1367$2034 assign { } { } - assign $1\builder_multiregimpl1_regs1[0:0] 1'0 + assign $1\rhs_array_muxed18[21:0] 22'0000000000000000000000 sync always sync init - update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] + update \rhs_array_muxed18 $1\rhs_array_muxed18[21:0] end - attribute \src "ls180.v:2823.32-2823.66" - process $proc$ls180.v:2823$4063 + attribute \src "ls180.v:1368.5-1368.29" + process $proc$ls180.v:1368$2035 assign { } { } - assign $1\builder_multiregimpl2_regs0[0:0] 1'0 + assign $1\rhs_array_muxed19[0:0] 1'0 sync always sync init - update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] + update \rhs_array_muxed19 $1\rhs_array_muxed19[0:0] end - attribute \src "ls180.v:2824.32-2824.66" - process $proc$ls180.v:2824$4064 + attribute \src "ls180.v:1369.5-1369.29" + process $proc$ls180.v:1369$2036 assign { } { } - assign $1\builder_multiregimpl2_regs1[0:0] 1'0 + assign $1\rhs_array_muxed20[0:0] 1'0 sync always sync init - update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] + update \rhs_array_muxed20 $1\rhs_array_muxed20[0:0] end - attribute \src "ls180.v:2825.32-2825.66" - process $proc$ls180.v:2825$4065 + attribute \src "ls180.v:137.11-137.65" + process $proc$ls180.v:137$1574 assign { } { } - assign $1\builder_multiregimpl3_regs0[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] 2'00 sync always sync init - update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] + update \libresocsim_libresoc_constraintmanager_sdram_ba $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] end - attribute \src "ls180.v:2826.32-2826.66" - process $proc$ls180.v:2826$4066 + attribute \src "ls180.v:1370.12-1370.37" + process $proc$ls180.v:1370$2037 assign { } { } - assign $1\builder_multiregimpl3_regs1[0:0] 1'0 + assign $1\rhs_array_muxed21[21:0] 22'0000000000000000000000 sync always sync init - update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] + update \rhs_array_muxed21 $1\rhs_array_muxed21[21:0] end - attribute \src "ls180.v:2827.32-2827.66" - process $proc$ls180.v:2827$4067 + attribute \src "ls180.v:1371.5-1371.29" + process $proc$ls180.v:1371$2038 assign { } { } - assign $1\builder_multiregimpl4_regs0[0:0] 1'0 + assign $1\rhs_array_muxed22[0:0] 1'0 sync always sync init - update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] + update \rhs_array_muxed22 $1\rhs_array_muxed22[0:0] end - attribute \src "ls180.v:2828.32-2828.66" - process $proc$ls180.v:2828$4068 + attribute \src "ls180.v:1372.5-1372.29" + process $proc$ls180.v:1372$2039 assign { } { } - assign $1\builder_multiregimpl4_regs1[0:0] 1'0 + assign $1\rhs_array_muxed23[0:0] 1'0 sync always sync init - update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] + update \rhs_array_muxed23 $1\rhs_array_muxed23[0:0] end - attribute \src "ls180.v:2829.32-2829.66" - process $proc$ls180.v:2829$4069 + attribute \src "ls180.v:1373.12-1373.37" + process $proc$ls180.v:1373$2040 assign { } { } - assign $1\builder_multiregimpl5_regs0[0:0] 1'0 + assign $1\rhs_array_muxed24[29:0] 30'000000000000000000000000000000 sync always sync init - update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] + update \rhs_array_muxed24 $1\rhs_array_muxed24[29:0] end - attribute \src "ls180.v:2830.32-2830.66" - process $proc$ls180.v:2830$4070 + attribute \src "ls180.v:1374.12-1374.37" + process $proc$ls180.v:1374$2041 assign { } { } - assign $1\builder_multiregimpl5_regs1[0:0] 1'0 + assign $1\rhs_array_muxed25[31:0] 0 sync always sync init - update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] + update \rhs_array_muxed25 $1\rhs_array_muxed25[31:0] end - attribute \src "ls180.v:2831.32-2831.66" - process $proc$ls180.v:2831$4071 + attribute \src "ls180.v:1375.11-1375.35" + process $proc$ls180.v:1375$2042 assign { } { } - assign $1\builder_multiregimpl6_regs0[0:0] 1'0 + assign $1\rhs_array_muxed26[3:0] 4'0000 sync always sync init - update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] + update \rhs_array_muxed26 $1\rhs_array_muxed26[3:0] end - attribute \src "ls180.v:2832.32-2832.66" - process $proc$ls180.v:2832$4072 + attribute \src "ls180.v:1376.5-1376.29" + process $proc$ls180.v:1376$2043 assign { } { } - assign $1\builder_multiregimpl6_regs1[0:0] 1'0 + assign $1\rhs_array_muxed27[0:0] 1'0 sync always sync init - update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] + update \rhs_array_muxed27 $1\rhs_array_muxed27[0:0] end - attribute \src "ls180.v:2833.32-2833.66" - process $proc$ls180.v:2833$4073 + attribute \src "ls180.v:1377.5-1377.29" + process $proc$ls180.v:1377$2044 assign { } { } - assign $1\builder_multiregimpl7_regs0[0:0] 1'0 + assign $1\rhs_array_muxed28[0:0] 1'0 sync always sync init - update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] + update \rhs_array_muxed28 $1\rhs_array_muxed28[0:0] end - attribute \src "ls180.v:2834.32-2834.66" - process $proc$ls180.v:2834$4074 + attribute \src "ls180.v:1378.5-1378.29" + process $proc$ls180.v:1378$2045 assign { } { } - assign $1\builder_multiregimpl7_regs1[0:0] 1'0 + assign $1\rhs_array_muxed29[0:0] 1'0 sync always sync init - update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] + update \rhs_array_muxed29 $1\rhs_array_muxed29[0:0] end - attribute \src "ls180.v:2835.32-2835.66" - process $proc$ls180.v:2835$4075 + attribute \src "ls180.v:1379.11-1379.35" + process $proc$ls180.v:1379$2046 assign { } { } - assign $1\builder_multiregimpl8_regs0[0:0] 1'0 + assign $1\rhs_array_muxed30[2:0] 3'000 sync always sync init - update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] + update \rhs_array_muxed30 $1\rhs_array_muxed30[2:0] end - attribute \src "ls180.v:2836.32-2836.66" - process $proc$ls180.v:2836$4076 + attribute \src "ls180.v:138.11-138.65" + process $proc$ls180.v:138$1575 assign { } { } - assign $1\builder_multiregimpl8_regs1[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] 2'00 sync always sync init - update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] + update \libresocsim_libresoc_constraintmanager_sdram_dm $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] end - attribute \src "ls180.v:2837.32-2837.66" - process $proc$ls180.v:2837$4077 + attribute \src "ls180.v:1380.11-1380.35" + process $proc$ls180.v:1380$2047 assign { } { } - assign $1\builder_multiregimpl9_regs0[0:0] 1'0 + assign $1\rhs_array_muxed31[1:0] 2'00 sync always sync init - update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] + update \rhs_array_muxed31 $1\rhs_array_muxed31[1:0] end - attribute \src "ls180.v:2838.32-2838.66" - process $proc$ls180.v:2838$4078 + attribute \src "ls180.v:1381.11-1381.30" + process $proc$ls180.v:1381$2048 assign { } { } - assign $1\builder_multiregimpl9_regs1[0:0] 1'0 + assign $1\array_muxed0[1:0] 2'00 sync always sync init - update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] + update \array_muxed0 $1\array_muxed0[1:0] end - attribute \src "ls180.v:2839.32-2839.67" - process $proc$ls180.v:2839$4079 + attribute \src "ls180.v:1382.12-1382.32" + process $proc$ls180.v:1382$2049 assign { } { } - assign $1\builder_multiregimpl10_regs0[0:0] 1'0 + assign $1\array_muxed1[12:0] 13'0000000000000 sync always sync init - update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] + update \array_muxed1 $1\array_muxed1[12:0] end - attribute \src "ls180.v:2840.32-2840.67" - process $proc$ls180.v:2840$4080 + attribute \src "ls180.v:1383.5-1383.24" + process $proc$ls180.v:1383$2050 assign { } { } - assign $1\builder_multiregimpl10_regs1[0:0] 1'0 + assign $1\array_muxed2[0:0] 1'0 sync always sync init - update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] + update \array_muxed2 $1\array_muxed2[0:0] end - attribute \src "ls180.v:2841.32-2841.67" - process $proc$ls180.v:2841$4081 + attribute \src "ls180.v:1384.5-1384.24" + process $proc$ls180.v:1384$2051 assign { } { } - assign $1\builder_multiregimpl11_regs0[0:0] 1'0 + assign $1\array_muxed3[0:0] 1'0 sync always sync init - update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] + update \array_muxed3 $1\array_muxed3[0:0] end - attribute \src "ls180.v:2842.32-2842.67" - process $proc$ls180.v:2842$4082 + attribute \src "ls180.v:1385.5-1385.24" + process $proc$ls180.v:1385$2052 assign { } { } - assign $1\builder_multiregimpl11_regs1[0:0] 1'0 + assign $1\array_muxed4[0:0] 1'0 sync always sync init - update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] + update \array_muxed4 $1\array_muxed4[0:0] end - attribute \src "ls180.v:2843.32-2843.67" - process $proc$ls180.v:2843$4083 + attribute \src "ls180.v:1386.5-1386.24" + process $proc$ls180.v:1386$2053 assign { } { } - assign $1\builder_multiregimpl12_regs0[0:0] 1'0 + assign $1\array_muxed5[0:0] 1'0 sync always sync init - update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] + update \array_muxed5 $1\array_muxed5[0:0] end - attribute \src "ls180.v:2844.32-2844.67" - process $proc$ls180.v:2844$4084 + attribute \src "ls180.v:1387.5-1387.24" + process $proc$ls180.v:1387$2054 assign { } { } - assign $1\builder_multiregimpl12_regs1[0:0] 1'0 + assign $1\array_muxed6[0:0] 1'0 sync always sync init - update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] + update \array_muxed6 $1\array_muxed6[0:0] end - attribute \src "ls180.v:2845.32-2845.67" - process $proc$ls180.v:2845$4085 + attribute \src "ls180.v:139.5-139.62" + process $proc$ls180.v:139$1576 assign { } { } - assign $1\builder_multiregimpl13_regs0[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] 1'0 sync always sync init - update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] + update \libresocsim_libresoc_constraintmanager_sdram_clock $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] end - attribute \src "ls180.v:2846.32-2846.67" - process $proc$ls180.v:2846$4086 + attribute \src "ls180.v:143.12-143.66" + process $proc$ls180.v:143$1577 assign { } { } - assign $1\builder_multiregimpl13_regs1[0:0] 1'0 + assign $1\libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 sync always sync init - update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] + update \libresocsim_interface0_converted_interface_adr $1\libresocsim_interface0_converted_interface_adr[29:0] end - attribute \src "ls180.v:2847.32-2847.67" - process $proc$ls180.v:2847$4087 + attribute \src "ls180.v:144.12-144.68" + process $proc$ls180.v:144$1578 assign { } { } - assign $1\builder_multiregimpl14_regs0[0:0] 1'0 + assign $1\libresocsim_interface0_converted_interface_dat_w[31:0] 0 sync always sync init - update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] + update \libresocsim_interface0_converted_interface_dat_w $1\libresocsim_interface0_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:2848.32-2848.67" - process $proc$ls180.v:2848$4088 + attribute \src "ls180.v:1444.32-1444.44" + process $proc$ls180.v:1444$2055 assign { } { } - assign $1\builder_multiregimpl14_regs1[0:0] 1'0 + assign $1\regs0[0:0] 1'0 sync always sync init - update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] + update \regs0 $1\regs0[0:0] end - attribute \src "ls180.v:2849.32-2849.67" - process $proc$ls180.v:2849$4089 + attribute \src "ls180.v:1445.32-1445.44" + process $proc$ls180.v:1445$2056 assign { } { } - assign $1\builder_multiregimpl15_regs0[0:0] 1'0 + assign $1\regs1[0:0] 1'0 sync always sync init - update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] + update \regs1 $1\regs1[0:0] end - attribute \src "ls180.v:285.5-285.39" - process $proc$ls180.v:285$3181 + attribute \src "ls180.v:146.11-146.64" + process $proc$ls180.v:146$1579 assign { } { } - assign $1\main_interface2_ram_bus_ack[0:0] 1'0 + assign $1\libresocsim_interface0_converted_interface_sel[3:0] 4'0000 sync always sync init - update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0] + update \libresocsim_interface0_converted_interface_sel $1\libresocsim_interface0_converted_interface_sel[3:0] end - attribute \src "ls180.v:2850.32-2850.67" - process $proc$ls180.v:2850$4090 + attribute \src "ls180.v:147.5-147.58" + process $proc$ls180.v:147$1580 assign { } { } - assign $1\builder_multiregimpl15_regs1[0:0] 1'0 + assign $1\libresocsim_interface0_converted_interface_cyc[0:0] 1'0 sync always sync init - update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] + update \libresocsim_interface0_converted_interface_cyc $1\libresocsim_interface0_converted_interface_cyc[0:0] end - attribute \src "ls180.v:2851.32-2851.67" - process $proc$ls180.v:2851$4091 + attribute \src "ls180.v:148.5-148.58" + process $proc$ls180.v:148$1581 assign { } { } - assign $1\builder_multiregimpl16_regs0[0:0] 1'0 + assign $1\libresocsim_interface0_converted_interface_stb[0:0] 1'0 sync always sync init - update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] + update \libresocsim_interface0_converted_interface_stb $1\libresocsim_interface0_converted_interface_stb[0:0] end - attribute \src "ls180.v:2852.32-2852.67" - process $proc$ls180.v:2852$4092 + attribute \src "ls180.v:1499.1-1504.4" + process $proc$ls180.v:1499$15 assign { } { } - assign $1\builder_multiregimpl16_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] - end - attribute \src "ls180.v:2887.1-2892.4" - process $proc$ls180.v:2887$49 assign { } { } - assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 - assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } - assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_irq - assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_uart_irq + assign $0\eint_tmp[2:0] [0] \libresocsim_libresoc_constraintmanager_eint_0 + assign $0\eint_tmp[2:0] [1] \libresocsim_libresoc_constraintmanager_eint_1 + assign $0\eint_tmp[2:0] [2] \libresocsim_libresoc_constraintmanager_eint_2 sync always - update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] + update \eint_tmp $0\eint_tmp[2:0] end - attribute \src "ls180.v:289.5-289.39" - process $proc$ls180.v:289$3182 + attribute \src "ls180.v:150.5-150.57" + process $proc$ls180.v:150$1582 assign { } { } - assign $0\main_interface2_ram_bus_err[0:0] 1'0 + assign $1\libresocsim_interface0_converted_interface_we[0:0] 1'0 sync always - update \main_interface2_ram_bus_err $0\main_interface2_ram_bus_err[0:0] sync init + update \libresocsim_interface0_converted_interface_we $1\libresocsim_interface0_converted_interface_we[0:0] end - attribute \src "ls180.v:2894.1-2904.4" - process $proc$ls180.v:2894$51 - assign { } { } - assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 - attribute \src "ls180.v:2896.2-2903.9" - switch \main_converter0_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [63:32] - case - end - sync always - update \main_libresocsim_libresoc_xics_icp_dat_w $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] - end - attribute \src "ls180.v:2906.1-2952.4" - process $proc$ls180.v:2906$52 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_interface0_converted_interface_ack[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 - assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 - assign $0\main_converter0_skip[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 - assign $0\builder_converter0_next_state[0:0] \builder_converter0_state - attribute \src "ls180.v:2918.2-2951.9" - switch \builder_converter0_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] { \main_interface0_converted_interface_adr [28:0] \main_converter0_counter } - attribute \src "ls180.v:2921.4-2928.11" - switch \main_converter0_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [7:4] - case - end - attribute \src "ls180.v:2929.4-2942.7" - switch $and$ls180.v:2929$53_Y - attribute \src "ls180.v:2929.8-2929.91" - case 1'1 - assign $0\main_converter0_skip[0:0] $eq$ls180.v:2930$54_Y - assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] \main_interface0_converted_interface_we - assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:2932$55_Y - assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:2933$56_Y - attribute \src "ls180.v:2934.5-2941.8" - switch $or$ls180.v:2934$57_Y - attribute \src "ls180.v:2934.9-2934.72" - case 1'1 - assign $0\main_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2935$58_Y - assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2937.6-2940.9" - switch $eq$ls180.v:2937$59_Y - attribute \src "ls180.v:2937.10-2937.43" - case 1'1 - assign $0\main_interface0_converted_interface_ack[0:0] 1'1 - assign $0\builder_converter0_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2947.4-2949.7" - switch $and$ls180.v:2947$60_Y - attribute \src "ls180.v:2947.8-2947.91" - case 1'1 - assign $0\builder_converter0_next_state[0:0] 1'1 - case - end - end - sync always - update \main_libresocsim_libresoc_xics_icp_adr $0\main_libresocsim_libresoc_xics_icp_adr[29:0] - update \main_libresocsim_libresoc_xics_icp_sel $0\main_libresocsim_libresoc_xics_icp_sel[3:0] - update \main_libresocsim_libresoc_xics_icp_cyc $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] - update \main_libresocsim_libresoc_xics_icp_stb $0\main_libresocsim_libresoc_xics_icp_stb[0:0] - update \main_libresocsim_libresoc_xics_icp_we $0\main_libresocsim_libresoc_xics_icp_we[0:0] - update \main_interface0_converted_interface_ack $0\main_interface0_converted_interface_ack[0:0] - update \main_converter0_skip $0\main_converter0_skip[0:0] - update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] - update \main_converter0_counter_converter0_next_value $0\main_converter0_counter_converter0_next_value[0:0] - update \main_converter0_counter_converter0_next_value_ce $0\main_converter0_counter_converter0_next_value_ce[0:0] - end - attribute \src "ls180.v:292.11-292.31" - process $proc$ls180.v:292$3183 + attribute \src "ls180.v:151.11-151.64" + process $proc$ls180.v:151$1583 assign { } { } - assign $1\main_sram2_we[7:0] 8'00000000 + assign $0\libresocsim_interface0_converted_interface_cti[2:0] 3'000 sync always + update \libresocsim_interface0_converted_interface_cti $0\libresocsim_interface0_converted_interface_cti[2:0] sync init - update \main_sram2_we $1\main_sram2_we[7:0] - end - attribute \src "ls180.v:2954.1-2964.4" - process $proc$ls180.v:2954$62 - assign { } { } - assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 - attribute \src "ls180.v:2956.2-2963.9" - switch \main_converter1_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [63:32] - case - end - sync always - update \main_libresocsim_libresoc_xics_ics_dat_w $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] end - attribute \src "ls180.v:2966.1-3012.4" - process $proc$ls180.v:2966$63 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:1511.1-1518.4" + process $proc$ls180.v:1511$16 assign { } { } - assign { } { } - assign { } { } - assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_interface1_converted_interface_ack[0:0] 1'0 - assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 - assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 - assign $0\main_converter1_skip[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 - assign $0\builder_converter1_next_state[0:0] \builder_converter1_state - attribute \src "ls180.v:2978.2-3011.9" - switch \builder_converter1_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] { \main_interface1_converted_interface_adr [28:0] \main_converter1_counter } - attribute \src "ls180.v:2981.4-2988.11" - switch \main_converter1_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [7:4] - case - end - attribute \src "ls180.v:2989.4-3002.7" - switch $and$ls180.v:2989$64_Y - attribute \src "ls180.v:2989.8-2989.91" - case 1'1 - assign $0\main_converter1_skip[0:0] $eq$ls180.v:2990$65_Y - assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] \main_interface1_converted_interface_we - assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:2992$66_Y - assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:2993$67_Y - attribute \src "ls180.v:2994.5-3001.8" - switch $or$ls180.v:2994$68_Y - attribute \src "ls180.v:2994.9-2994.72" - case 1'1 - assign $0\main_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2995$69_Y - assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2997.6-3000.9" - switch $eq$ls180.v:2997$70_Y - attribute \src "ls180.v:2997.10-2997.43" - case 1'1 - assign $0\main_interface1_converted_interface_ack[0:0] 1'1 - assign $0\builder_converter1_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:3007.4-3009.7" - switch $and$ls180.v:3007$71_Y - attribute \src "ls180.v:3007.8-3007.91" - case 1'1 - assign $0\builder_converter1_next_state[0:0] 1'1 - case - end - end + assign $0\libresocsim_libresoc_interrupt[15:0] [12:2] 11'00000000000 + assign $0\libresocsim_libresoc_interrupt[15:0] [13] \eint_tmp [0] + assign $0\libresocsim_libresoc_interrupt[15:0] [14] \eint_tmp [1] + assign $0\libresocsim_libresoc_interrupt[15:0] [15] \eint_tmp [2] + assign $0\libresocsim_libresoc_interrupt[15:0] [0] \libresocsim_irq + assign $0\libresocsim_libresoc_interrupt[15:0] [1] \irq sync always - update \main_libresocsim_libresoc_xics_ics_adr $0\main_libresocsim_libresoc_xics_ics_adr[29:0] - update \main_libresocsim_libresoc_xics_ics_sel $0\main_libresocsim_libresoc_xics_ics_sel[3:0] - update \main_libresocsim_libresoc_xics_ics_cyc $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] - update \main_libresocsim_libresoc_xics_ics_stb $0\main_libresocsim_libresoc_xics_ics_stb[0:0] - update \main_libresocsim_libresoc_xics_ics_we $0\main_libresocsim_libresoc_xics_ics_we[0:0] - update \main_interface1_converted_interface_ack $0\main_interface1_converted_interface_ack[0:0] - update \main_converter1_skip $0\main_converter1_skip[0:0] - update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] - update \main_converter1_counter_converter1_next_value $0\main_converter1_counter_converter1_next_value[0:0] - update \main_converter1_counter_converter1_next_value_ce $0\main_converter1_counter_converter1_next_value_ce[0:0] + update \libresocsim_libresoc_interrupt $0\libresocsim_libresoc_interrupt[15:0] end - attribute \src "ls180.v:300.5-300.39" - process $proc$ls180.v:300$3184 + attribute \src "ls180.v:152.11-152.64" + process $proc$ls180.v:152$1584 assign { } { } - assign $1\main_interface3_ram_bus_ack[0:0] 1'0 + assign $0\libresocsim_interface0_converted_interface_bte[1:0] 2'00 sync always + update \libresocsim_interface0_converted_interface_bte $0\libresocsim_interface0_converted_interface_bte[1:0] sync init - update \main_interface3_ram_bus_ack $1\main_interface3_ram_bus_ack[0:0] end - attribute \src "ls180.v:3014.1-3024.4" - process $proc$ls180.v:3014$73 + attribute \src "ls180.v:1520.1-1530.4" + process $proc$ls180.v:1520$18 assign { } { } - assign $0\main_wb_sdram_dat_w[31:0] 0 - attribute \src "ls180.v:3016.2-3023.9" - switch \main_socbushandler_counter + assign $0\libresocsim_interface0_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:1522.2-1529.9" + switch \libresocsim_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [31:0] + assign $0\libresocsim_interface0_converted_interface_dat_w[31:0] \libresocsim_libresoc_ibus_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [63:32] + assign $0\libresocsim_interface0_converted_interface_dat_w[31:0] \libresocsim_libresoc_ibus_dat_w [63:32] case end sync always - update \main_wb_sdram_dat_w $0\main_wb_sdram_dat_w[31:0] + update \libresocsim_interface0_converted_interface_dat_w $0\libresocsim_interface0_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:3026.1-3072.4" - process $proc$ls180.v:3026$74 + attribute \src "ls180.v:1532.1-1578.4" + process $proc$ls180.v:1532$19 assign { } { } assign { } { } assign { } { } @@ -291006,52 +261923,52 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 - assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 - assign $0\main_wb_sdram_we[0:0] 1'0 - assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 - assign $0\main_wb_sdram_sel[3:0] 4'0000 - assign $0\main_wb_sdram_cyc[0:0] 1'0 - assign $0\main_wb_sdram_stb[0:0] 1'0 - assign $0\main_socbushandler_skip[0:0] 1'0 + assign $0\libresocsim_libresoc_ibus_ack[0:0] 1'0 + assign $0\libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + assign $0\libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + assign $0\libresocsim_interface0_converted_interface_stb[0:0] 1'0 + assign $0\libresocsim_interface0_converted_interface_we[0:0] 1'0 + assign $0\libresocsim_converter0_skip[0:0] 1'0 assign { } { } - assign $0\builder_converter2_next_state[0:0] \builder_converter2_state - attribute \src "ls180.v:3038.2-3071.9" - switch \builder_converter2_state + assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] 1'0 + assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0 + assign $0\libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\subfragments_converter0_next_state[0:0] \subfragments_converter0_state + attribute \src "ls180.v:1544.2-1577.9" + switch \subfragments_converter0_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_wb_sdram_adr[29:0] { \main_socbushandler_converted_interface_adr [28:0] \main_socbushandler_counter } - attribute \src "ls180.v:3041.4-3048.11" - switch \main_socbushandler_counter + assign $0\libresocsim_interface0_converted_interface_adr[29:0] { \libresocsim_libresoc_ibus_adr \libresocsim_converter0_counter } + attribute \src "ls180.v:1547.4-1554.11" + switch \libresocsim_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [3:0] + assign $0\libresocsim_interface0_converted_interface_sel[3:0] \libresocsim_libresoc_ibus_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [7:4] + assign $0\libresocsim_interface0_converted_interface_sel[3:0] \libresocsim_libresoc_ibus_sel [7:4] case end - attribute \src "ls180.v:3049.4-3062.7" - switch $and$ls180.v:3049$75_Y - attribute \src "ls180.v:3049.8-3049.97" + attribute \src "ls180.v:1555.4-1568.7" + switch $and$ls180.v:1555$20_Y + attribute \src "ls180.v:1555.8-1555.71" case 1'1 - assign $0\main_socbushandler_skip[0:0] $eq$ls180.v:3050$76_Y - assign $0\main_wb_sdram_we[0:0] \main_socbushandler_converted_interface_we - assign $0\main_wb_sdram_cyc[0:0] $not$ls180.v:3052$77_Y - assign $0\main_wb_sdram_stb[0:0] $not$ls180.v:3053$78_Y - attribute \src "ls180.v:3054.5-3061.8" - switch $or$ls180.v:3054$79_Y - attribute \src "ls180.v:3054.9-3054.54" + assign $0\libresocsim_converter0_skip[0:0] $eq$ls180.v:1556$21_Y + assign $0\libresocsim_interface0_converted_interface_we[0:0] \libresocsim_libresoc_ibus_we + assign $0\libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:1558$22_Y + assign $0\libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:1559$23_Y + attribute \src "ls180.v:1560.5-1567.8" + switch $or$ls180.v:1560$24_Y + attribute \src "ls180.v:1560.9-1560.87" case 1'1 - assign $0\main_socbushandler_counter_converter2_next_value[0:0] $add$ls180.v:3055$80_Y - assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:3057.6-3060.9" - switch $eq$ls180.v:3057$81_Y - attribute \src "ls180.v:3057.10-3057.46" + assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] $add$ls180.v:1561$25_Y + assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:1563.6-1566.9" + switch $eq$ls180.v:1563$26_Y + attribute \src "ls180.v:1563.10-1563.50" case 1'1 - assign $0\main_socbushandler_converted_interface_ack[0:0] 1'1 - assign $0\builder_converter2_next_state[0:0] 1'0 + assign $0\libresocsim_libresoc_ibus_ack[0:0] 1'1 + assign $0\subfragments_converter0_next_state[0:0] 1'0 case end case @@ -291060,986 +261977,87 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 - assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:3067.4-3069.7" - switch $and$ls180.v:3067$82_Y - attribute \src "ls180.v:3067.8-3067.97" - case 1'1 - assign $0\builder_converter2_next_state[0:0] 1'1 - case - end - end - sync always - update \main_wb_sdram_adr $0\main_wb_sdram_adr[29:0] - update \main_wb_sdram_sel $0\main_wb_sdram_sel[3:0] - update \main_wb_sdram_cyc $0\main_wb_sdram_cyc[0:0] - update \main_wb_sdram_stb $0\main_wb_sdram_stb[0:0] - update \main_wb_sdram_we $0\main_wb_sdram_we[0:0] - update \main_socbushandler_converted_interface_ack $0\main_socbushandler_converted_interface_ack[0:0] - update \main_socbushandler_skip $0\main_socbushandler_skip[0:0] - update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] - update \main_socbushandler_counter_converter2_next_value $0\main_socbushandler_counter_converter2_next_value[0:0] - update \main_socbushandler_counter_converter2_next_value_ce $0\main_socbushandler_counter_converter2_next_value_ce[0:0] - end - attribute \src "ls180.v:304.5-304.39" - process $proc$ls180.v:304$3185 - assign { } { } - assign $0\main_interface3_ram_bus_err[0:0] 1'0 - sync always - update \main_interface3_ram_bus_err $0\main_interface3_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:307.11-307.31" - process $proc$ls180.v:307$3186 - assign { } { } - assign $1\main_sram3_we[7:0] 8'00000000 - sync always - sync init - update \main_sram3_we $1\main_sram3_we[7:0] - end - attribute \src "ls180.v:3075.1-3085.4" - process $proc$ls180.v:3075$83 - assign { } { } - assign { } { } - assign $0\main_libresocsim_we[7:0] [0] $and$ls180.v:3077$86_Y - assign $0\main_libresocsim_we[7:0] [1] $and$ls180.v:3078$89_Y - assign $0\main_libresocsim_we[7:0] [2] $and$ls180.v:3079$92_Y - assign $0\main_libresocsim_we[7:0] [3] $and$ls180.v:3080$95_Y - assign $0\main_libresocsim_we[7:0] [4] $and$ls180.v:3081$98_Y - assign $0\main_libresocsim_we[7:0] [5] $and$ls180.v:3082$101_Y - assign $0\main_libresocsim_we[7:0] [6] $and$ls180.v:3083$104_Y - assign $0\main_libresocsim_we[7:0] [7] $and$ls180.v:3084$107_Y - sync always - update \main_libresocsim_we $0\main_libresocsim_we[7:0] - end - attribute \src "ls180.v:3091.1-3096.4" - process $proc$ls180.v:3091$109 - assign { } { } - assign $0\main_libresocsim_zero_clear[0:0] 1'0 - attribute \src "ls180.v:3093.2-3095.5" - switch $and$ls180.v:3093$110_Y - attribute \src "ls180.v:3093.6-3093.90" - case 1'1 - assign $0\main_libresocsim_zero_clear[0:0] 1'1 - case - end - sync always - update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] - end - attribute \src "ls180.v:3100.1-3110.4" - process $proc$ls180.v:3100$112 - assign { } { } - assign { } { } - assign $0\main_sram0_we[7:0] [0] $and$ls180.v:3102$115_Y - assign $0\main_sram0_we[7:0] [1] $and$ls180.v:3103$118_Y - assign $0\main_sram0_we[7:0] [2] $and$ls180.v:3104$121_Y - assign $0\main_sram0_we[7:0] [3] $and$ls180.v:3105$124_Y - assign $0\main_sram0_we[7:0] [4] $and$ls180.v:3106$127_Y - assign $0\main_sram0_we[7:0] [5] $and$ls180.v:3107$130_Y - assign $0\main_sram0_we[7:0] [6] $and$ls180.v:3108$133_Y - assign $0\main_sram0_we[7:0] [7] $and$ls180.v:3109$136_Y - sync always - update \main_sram0_we $0\main_sram0_we[7:0] - end - attribute \src "ls180.v:3114.1-3124.4" - process $proc$ls180.v:3114$137 - assign { } { } - assign { } { } - assign $0\main_sram1_we[7:0] [0] $and$ls180.v:3116$140_Y - assign $0\main_sram1_we[7:0] [1] $and$ls180.v:3117$143_Y - assign $0\main_sram1_we[7:0] [2] $and$ls180.v:3118$146_Y - assign $0\main_sram1_we[7:0] [3] $and$ls180.v:3119$149_Y - assign $0\main_sram1_we[7:0] [4] $and$ls180.v:3120$152_Y - assign $0\main_sram1_we[7:0] [5] $and$ls180.v:3121$155_Y - assign $0\main_sram1_we[7:0] [6] $and$ls180.v:3122$158_Y - assign $0\main_sram1_we[7:0] [7] $and$ls180.v:3123$161_Y - sync always - update \main_sram1_we $0\main_sram1_we[7:0] - end - attribute \src "ls180.v:3128.1-3138.4" - process $proc$ls180.v:3128$162 - assign { } { } - assign { } { } - assign $0\main_sram2_we[7:0] [0] $and$ls180.v:3130$165_Y - assign $0\main_sram2_we[7:0] [1] $and$ls180.v:3131$168_Y - assign $0\main_sram2_we[7:0] [2] $and$ls180.v:3132$171_Y - assign $0\main_sram2_we[7:0] [3] $and$ls180.v:3133$174_Y - assign $0\main_sram2_we[7:0] [4] $and$ls180.v:3134$177_Y - assign $0\main_sram2_we[7:0] [5] $and$ls180.v:3135$180_Y - assign $0\main_sram2_we[7:0] [6] $and$ls180.v:3136$183_Y - assign $0\main_sram2_we[7:0] [7] $and$ls180.v:3137$186_Y - sync always - update \main_sram2_we $0\main_sram2_we[7:0] - end - attribute \src "ls180.v:3142.1-3152.4" - process $proc$ls180.v:3142$187 - assign { } { } - assign { } { } - assign $0\main_sram3_we[7:0] [0] $and$ls180.v:3144$190_Y - assign $0\main_sram3_we[7:0] [1] $and$ls180.v:3145$193_Y - assign $0\main_sram3_we[7:0] [2] $and$ls180.v:3146$196_Y - assign $0\main_sram3_we[7:0] [3] $and$ls180.v:3147$199_Y - assign $0\main_sram3_we[7:0] [4] $and$ls180.v:3148$202_Y - assign $0\main_sram3_we[7:0] [5] $and$ls180.v:3149$205_Y - assign $0\main_sram3_we[7:0] [6] $and$ls180.v:3150$208_Y - assign $0\main_sram3_we[7:0] [7] $and$ls180.v:3151$211_Y - sync always - update \main_sram3_we $0\main_sram3_we[7:0] - end - attribute \src "ls180.v:315.5-315.51" - process $proc$ls180.v:315$3187 - assign { } { } - assign $1\main_interface0_converted_interface_ack[0:0] 1'0 - sync always - sync init - update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] - end - attribute \src "ls180.v:319.5-319.51" - process $proc$ls180.v:319$3188 - assign { } { } - assign $0\main_interface0_converted_interface_err[0:0] 1'0 - sync always - update \main_interface0_converted_interface_err $0\main_interface0_converted_interface_err[0:0] - sync init - end - attribute \src "ls180.v:3191.1-3245.4" - process $proc$ls180.v:3191$212 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 - assign $0\main_sdram_master_p0_bank[1:0] 2'00 - assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_master_p0_we_n[0:0] 1'1 - assign $0\main_sdram_master_p0_cke[0:0] 1'0 - assign $0\main_sdram_master_p0_odt[0:0] 1'0 - assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 - assign $0\main_sdram_master_p0_act_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 - assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 - assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 - assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 - assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 - attribute \src "ls180.v:3210.2-3244.5" - switch \main_sdram_sel - attribute \src "ls180.v:3210.6-3210.20" - case 1'1 - assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address - assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank - assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n - assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n - assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n - assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n - assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke - assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt - assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n - assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n - assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata - assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en - assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask - assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en - assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata - assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:3227.6-3227.10" - case - assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address - assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank - assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n - assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n - assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n - assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n - assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke - assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt - assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n - assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n - assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata - assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en - assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask - assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en - assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata - assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - end - sync always - update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] - update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] - update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] - update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] - update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] - update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] - update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] - update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] - update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] - update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] - update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] - update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] - update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] - update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] - update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] - update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] - update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] - update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] - end - attribute \src "ls180.v:320.5-320.32" - process $proc$ls180.v:320$3189 - assign { } { } - assign $1\main_converter0_skip[0:0] 1'0 - sync always - sync init - update \main_converter0_skip $1\main_converter0_skip[0:0] - end - attribute \src "ls180.v:321.5-321.35" - process $proc$ls180.v:321$3190 - assign { } { } - assign $1\main_converter0_counter[0:0] 1'0 - sync always - sync init - update \main_converter0_counter $1\main_converter0_counter[0:0] - end - attribute \src "ls180.v:323.12-323.41" - process $proc$ls180.v:323$3191 - assign { } { } - assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_converter0_dat_r $1\main_converter0_dat_r[63:0] - end - attribute \src "ls180.v:3249.1-3265.4" - process $proc$ls180.v:3249$213 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - attribute \src "ls180.v:3254.2-3264.5" - switch \main_sdram_command_issue_re - attribute \src "ls180.v:3254.6-3254.33" - case 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3255$214_Y - assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3256$215_Y - assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3257$216_Y - assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3258$217_Y - attribute \src "ls180.v:3259.6-3259.10" - case - assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - end - sync always - update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] - update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] - update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] - update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] - end - attribute \src "ls180.v:330.5-330.51" - process $proc$ls180.v:330$3192 - assign { } { } - assign $1\main_interface1_converted_interface_ack[0:0] 1'0 - sync always - sync init - update \main_interface1_converted_interface_ack $1\main_interface1_converted_interface_ack[0:0] - end - attribute \src "ls180.v:3308.1-3338.4" - process $proc$ls180.v:3308$226 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_cmd_valid[0:0] 1'0 - assign { } { } - assign $0\main_sdram_cmd_last[0:0] 1'0 - assign $0\main_sdram_sequencer_start0[0:0] 1'0 - assign $0\builder_refresher_next_state[1:0] \builder_refresher_state - attribute \src "ls180.v:3314.2-3337.9" - switch \builder_refresher_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3317.4-3320.7" - switch \main_sdram_cmd_ready - attribute \src "ls180.v:3317.8-3317.28" - case 1'1 - assign $0\main_sdram_sequencer_start0[0:0] 1'1 - assign $0\builder_refresher_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3324.4-3328.7" - switch \main_sdram_sequencer_done0 - attribute \src "ls180.v:3324.8-3324.34" - case 1'1 - assign $0\main_sdram_cmd_valid[0:0] 1'0 - assign $0\main_sdram_cmd_last[0:0] 1'1 - assign $0\builder_refresher_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3331.4-3335.7" - switch 1'1 - attribute \src "ls180.v:3331.8-3331.12" + assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] 1'0 + assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:1573.4-1575.7" + switch $and$ls180.v:1573$27_Y + attribute \src "ls180.v:1573.8-1573.71" case 1'1 - attribute \src "ls180.v:3332.5-3334.8" - switch \main_sdram_wants_refresh - attribute \src "ls180.v:3332.9-3332.33" - case 1'1 - assign $0\builder_refresher_next_state[1:0] 2'01 - case - end + assign $0\subfragments_converter0_next_state[0:0] 1'1 case end end sync always - update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] - update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] - update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] - update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] - end - attribute \src "ls180.v:334.5-334.51" - process $proc$ls180.v:334$3193 - assign { } { } - assign $0\main_interface1_converted_interface_err[0:0] 1'0 - sync always - update \main_interface1_converted_interface_err $0\main_interface1_converted_interface_err[0:0] - sync init + update \libresocsim_libresoc_ibus_ack $0\libresocsim_libresoc_ibus_ack[0:0] + update \libresocsim_interface0_converted_interface_adr $0\libresocsim_interface0_converted_interface_adr[29:0] + update \libresocsim_interface0_converted_interface_sel $0\libresocsim_interface0_converted_interface_sel[3:0] + update \libresocsim_interface0_converted_interface_cyc $0\libresocsim_interface0_converted_interface_cyc[0:0] + update \libresocsim_interface0_converted_interface_stb $0\libresocsim_interface0_converted_interface_stb[0:0] + update \libresocsim_interface0_converted_interface_we $0\libresocsim_interface0_converted_interface_we[0:0] + update \libresocsim_converter0_skip $0\libresocsim_converter0_skip[0:0] + update \subfragments_converter0_next_state $0\subfragments_converter0_next_state[0:0] + update \libresocsim_converter0_counter_subfragments_converter0_next_value $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] + update \libresocsim_converter0_counter_subfragments_converter0_next_value_ce $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:335.5-335.32" - process $proc$ls180.v:335$3194 + attribute \src "ls180.v:154.5-154.39" + process $proc$ls180.v:154$1585 assign { } { } - assign $1\main_converter1_skip[0:0] 1'0 + assign $1\libresocsim_converter0_skip[0:0] 1'0 sync always sync init - update \main_converter1_skip $1\main_converter1_skip[0:0] - end - attribute \src "ls180.v:3353.1-3360.4" - process $proc$ls180.v:3353$230 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3355.2-3359.5" - switch \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:3355.6-3355.48" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3357.6-3357.10" - case - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3358$232_Y - end - sync always - update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + update \libresocsim_converter0_skip $1\libresocsim_converter0_skip[0:0] end - attribute \src "ls180.v:336.5-336.35" - process $proc$ls180.v:336$3195 + attribute \src "ls180.v:155.5-155.42" + process $proc$ls180.v:155$1586 assign { } { } - assign $1\main_converter1_counter[0:0] 1'0 + assign $1\libresocsim_converter0_counter[0:0] 1'0 sync always sync init - update \main_converter1_counter $1\main_converter1_counter[0:0] - end - attribute \src "ls180.v:3364.1-3371.4" - process $proc$ls180.v:3364$239 - assign { } { } - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3366.2-3370.5" - switch $and$ls180.v:3366$240_Y - attribute \src "ls180.v:3366.6-3366.115" - case 1'1 - attribute \src "ls180.v:3367.3-3369.6" - switch $ne$ls180.v:3367$241_Y - attribute \src "ls180.v:3367.7-3367.143" - case 1'1 - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3368$242_Y - case - end - case - end - sync always - update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] + update \libresocsim_converter0_counter $1\libresocsim_converter0_counter[0:0] end - attribute \src "ls180.v:338.12-338.41" - process $proc$ls180.v:338$3196 + attribute \src "ls180.v:157.12-157.48" + process $proc$ls180.v:157$1587 assign { } { } - assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_converter1_dat_r $1\main_converter1_dat_r[63:0] - end - attribute \src "ls180.v:3386.1-3393.4" - process $proc$ls180.v:3386$243 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3388.2-3392.5" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3388.6-3388.58" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3389$244_Y - attribute \src "ls180.v:3390.6-3390.10" - case - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:3402.1-3495.4" - process $proc$ls180.v:3402$252 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state - attribute \src "ls180.v:3418.2-3494.9" - switch \builder_bankmachine0_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3420.4-3428.7" - switch $and$ls180.v:3420$253_Y - attribute \src "ls180.v:3420.8-3420.87" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3422.5-3424.8" - switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3422.9-3422.42" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3432.4-3434.7" - switch $and$ls180.v:3432$254_Y - attribute \src "ls180.v:3432.8-3432.87" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3438.4-3447.7" - switch \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:3438.8-3438.44" - case 1'1 - assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3443.5-3445.8" - switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3443.9-3443.42" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3450.4-3452.7" - switch \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:3450.8-3450.45" - case 1'1 - assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3455.4-3457.7" - switch $not$ls180.v:3455$255_Y - attribute \src "ls180.v:3455.8-3455.46" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine0_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine0_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3466.4-3492.7" - switch \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:3466.8-3466.43" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'100 - attribute \src "ls180.v:3468.8-3468.12" - case - attribute \src "ls180.v:3469.5-3491.8" - switch \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:3469.9-3469.56" - case 1'1 - attribute \src "ls180.v:3470.6-3490.9" - switch \main_sdram_bankmachine0_row_opened - attribute \src "ls180.v:3470.10-3470.44" - case 1'1 - attribute \src "ls180.v:3471.7-3487.10" - switch \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:3471.11-3471.42" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3473.8-3480.11" - switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:3473.12-3473.64" - case 1'1 - assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready - assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3477.12-3477.16" - case - assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready - assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3482.8-3484.11" - switch $and$ls180.v:3482$256_Y - attribute \src "ls180.v:3482.12-3482.88" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3485.11-3485.15" - case - assign $0\builder_bankmachine0_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3488.10-3488.14" - case - assign $0\builder_bankmachine0_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] - update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] - update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] - update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] - update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] + update \libresocsim_converter0_dat_r $1\libresocsim_converter0_dat_r[63:0] end - attribute \src "ls180.v:342.5-342.24" - process $proc$ls180.v:342$3197 + attribute \src "ls180.v:158.12-158.66" + process $proc$ls180.v:158$1588 assign { } { } - assign $1\main_int_rst[0:0] 1'1 + assign $1\libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 sync always sync init - update \main_int_rst $1\main_int_rst[0:0] - end - attribute \src "ls180.v:3510.1-3517.4" - process $proc$ls180.v:3510$260 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3512.2-3516.5" - switch \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:3512.6-3512.48" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3514.6-3514.10" - case - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3515$262_Y - end - sync always - update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3521.1-3528.4" - process $proc$ls180.v:3521$269 - assign { } { } - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3523.2-3527.5" - switch $and$ls180.v:3523$270_Y - attribute \src "ls180.v:3523.6-3523.115" - case 1'1 - attribute \src "ls180.v:3524.3-3526.6" - switch $ne$ls180.v:3524$271_Y - attribute \src "ls180.v:3524.7-3524.143" - case 1'1 - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3525$272_Y - case - end - case - end - sync always - update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] - end - attribute \src "ls180.v:3543.1-3550.4" - process $proc$ls180.v:3543$273 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3545.2-3549.5" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3545.6-3545.58" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3546$274_Y - attribute \src "ls180.v:3547.6-3547.10" - case - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + update \libresocsim_interface1_converted_interface_adr $1\libresocsim_interface1_converted_interface_adr[29:0] end - attribute \src "ls180.v:3559.1-3652.4" - process $proc$ls180.v:3559$282 - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:1580.1-1590.4" + process $proc$ls180.v:1580$29 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state - attribute \src "ls180.v:3575.2-3651.9" - switch \builder_bankmachine1_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3577.4-3585.7" - switch $and$ls180.v:3577$283_Y - attribute \src "ls180.v:3577.8-3577.87" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3579.5-3581.8" - switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3579.9-3579.42" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3589.4-3591.7" - switch $and$ls180.v:3589$284_Y - attribute \src "ls180.v:3589.8-3589.87" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3595.4-3604.7" - switch \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:3595.8-3595.44" - case 1'1 - assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3600.5-3602.8" - switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3600.9-3600.42" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3607.4-3609.7" - switch \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:3607.8-3607.45" - case 1'1 - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3612.4-3614.7" - switch $not$ls180.v:3612$285_Y - attribute \src "ls180.v:3612.8-3612.46" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine1_next_state[2:0] 3'011 + assign $0\libresocsim_interface1_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:1582.2-1589.9" + switch \libresocsim_converter1_counter attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine1_next_state[2:0] 3'000 + case 1'0 + assign $0\libresocsim_interface1_converted_interface_dat_w[31:0] \libresocsim_libresoc_dbus_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3623.4-3649.7" - switch \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:3623.8-3623.43" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'100 - attribute \src "ls180.v:3625.8-3625.12" - case - attribute \src "ls180.v:3626.5-3648.8" - switch \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:3626.9-3626.56" - case 1'1 - attribute \src "ls180.v:3627.6-3647.9" - switch \main_sdram_bankmachine1_row_opened - attribute \src "ls180.v:3627.10-3627.44" - case 1'1 - attribute \src "ls180.v:3628.7-3644.10" - switch \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:3628.11-3628.42" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3630.8-3637.11" - switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:3630.12-3630.64" - case 1'1 - assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready - assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3634.12-3634.16" - case - assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready - assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3639.8-3641.11" - switch $and$ls180.v:3639$286_Y - attribute \src "ls180.v:3639.12-3639.88" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3642.11-3642.15" - case - assign $0\builder_bankmachine1_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3645.10-3645.14" - case - assign $0\builder_bankmachine1_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] - update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] - update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] - update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] - update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] - end - attribute \src "ls180.v:357.12-357.38" - process $proc$ls180.v:357$3198 - assign { } { } - assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] - end - attribute \src "ls180.v:358.5-358.36" - process $proc$ls180.v:358$3199 - assign { } { } - assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:359.11-359.32" - process $proc$ls180.v:359$3200 - assign { } { } - assign $1\main_rddata_en[2:0] 3'000 - sync always - sync init - update \main_rddata_en $1\main_rddata_en[2:0] - end - attribute \src "ls180.v:362.5-362.36" - process $proc$ls180.v:362$3201 - assign { } { } - assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] - end - attribute \src "ls180.v:363.5-363.35" - process $proc$ls180.v:363$3202 - assign { } { } - assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] - end - attribute \src "ls180.v:364.5-364.36" - process $proc$ls180.v:364$3203 - assign { } { } - assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] - end - attribute \src "ls180.v:365.5-365.35" - process $proc$ls180.v:365$3204 - assign { } { } - assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] - end - attribute \src "ls180.v:3667.1-3674.4" - process $proc$ls180.v:3667$290 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3669.2-3673.5" - switch \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:3669.6-3669.48" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3671.6-3671.10" - case - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3672$292_Y - end - sync always - update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3678.1-3685.4" - process $proc$ls180.v:3678$299 - assign { } { } - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3680.2-3684.5" - switch $and$ls180.v:3680$300_Y - attribute \src "ls180.v:3680.6-3680.115" case 1'1 - attribute \src "ls180.v:3681.3-3683.6" - switch $ne$ls180.v:3681$301_Y - attribute \src "ls180.v:3681.7-3681.143" - case 1'1 - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3682$302_Y - case - end + assign $0\libresocsim_interface1_converted_interface_dat_w[31:0] \libresocsim_libresoc_dbus_dat_w [63:32] case end sync always - update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] + update \libresocsim_interface1_converted_interface_dat_w $0\libresocsim_interface1_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:369.5-369.36" - process $proc$ls180.v:369$3205 + attribute \src "ls180.v:159.12-159.68" + process $proc$ls180.v:159$1589 assign { } { } - assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + assign $1\libresocsim_interface1_converted_interface_dat_w[31:0] 0 sync always - update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] sync init + update \libresocsim_interface1_converted_interface_dat_w $1\libresocsim_interface1_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:3700.1-3707.4" - process $proc$ls180.v:3700$303 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3702.2-3706.5" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3702.6-3702.58" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3703$304_Y - attribute \src "ls180.v:3704.6-3704.10" - case - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:3716.1-3809.4" - process $proc$ls180.v:3716$312 - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:1592.1-1638.4" + process $proc$ls180.v:1592$30 assign { } { } assign { } { } assign { } { } @@ -292050,953 +262068,133 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\libresocsim_interface1_converted_interface_stb[0:0] 1'0 + assign $0\libresocsim_interface1_converted_interface_we[0:0] 1'0 + assign $0\libresocsim_converter1_skip[0:0] 1'0 + assign $0\libresocsim_libresoc_dbus_ack[0:0] 1'0 assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state - attribute \src "ls180.v:3732.2-3808.9" - switch \builder_bankmachine2_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3734.4-3742.7" - switch $and$ls180.v:3734$313_Y - attribute \src "ls180.v:3734.8-3734.87" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3736.5-3738.8" - switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3736.9-3736.42" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3746.4-3748.7" - switch $and$ls180.v:3746$314_Y - attribute \src "ls180.v:3746.8-3746.87" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3752.4-3761.7" - switch \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:3752.8-3752.44" - case 1'1 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3757.5-3759.8" - switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3757.9-3757.42" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3764.4-3766.7" - switch \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:3764.8-3764.45" - case 1'1 - assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3769.4-3771.7" - switch $not$ls180.v:3769$315_Y - attribute \src "ls180.v:3769.8-3769.46" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine2_next_state[2:0] 3'011 + assign $0\libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] 1'0 + assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0 + assign $0\libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + assign $0\libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + assign $0\subfragments_converter1_next_state[0:0] \subfragments_converter1_state + attribute \src "ls180.v:1604.2-1637.9" + switch \subfragments_converter1_state attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine2_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3780.4-3806.7" - switch \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:3780.8-3780.43" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'100 - attribute \src "ls180.v:3782.8-3782.12" - case - attribute \src "ls180.v:3783.5-3805.8" - switch \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:3783.9-3783.56" - case 1'1 - attribute \src "ls180.v:3784.6-3804.9" - switch \main_sdram_bankmachine2_row_opened - attribute \src "ls180.v:3784.10-3784.44" - case 1'1 - attribute \src "ls180.v:3785.7-3801.10" - switch \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:3785.11-3785.42" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3787.8-3794.11" - switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:3787.12-3787.64" - case 1'1 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3791.12-3791.16" - case - assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3796.8-3798.11" - switch $and$ls180.v:3796$316_Y - attribute \src "ls180.v:3796.12-3796.88" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3799.11-3799.15" - case - assign $0\builder_bankmachine2_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3802.10-3802.14" - case - assign $0\builder_bankmachine2_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] - update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] - update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] - update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] - update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] - end - attribute \src "ls180.v:374.12-374.45" - process $proc$ls180.v:374$3206 - assign { } { } - assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] - end - attribute \src "ls180.v:375.5-375.43" - process $proc$ls180.v:375$3207 - assign { } { } - assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:3824.1-3831.4" - process $proc$ls180.v:3824$320 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3826.2-3830.5" - switch \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:3826.6-3826.48" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3828.6-3828.10" - case - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3829$322_Y - end - sync always - update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3835.1-3842.4" - process $proc$ls180.v:3835$329 - assign { } { } - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3837.2-3841.5" - switch $and$ls180.v:3837$330_Y - attribute \src "ls180.v:3837.6-3837.115" - case 1'1 - attribute \src "ls180.v:3838.3-3840.6" - switch $ne$ls180.v:3838$331_Y - attribute \src "ls180.v:3838.7-3838.143" - case 1'1 - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3839$332_Y - case - end - case - end - sync always - update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] - end - attribute \src "ls180.v:3857.1-3864.4" - process $proc$ls180.v:3857$333 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3859.2-3863.5" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3859.6-3859.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3860$334_Y - attribute \src "ls180.v:3861.6-3861.10" - case - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:3873.1-3966.4" - process $proc$ls180.v:3873$342 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 - assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state - attribute \src "ls180.v:3889.2-3965.9" - switch \builder_bankmachine3_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3891.4-3899.7" - switch $and$ls180.v:3891$343_Y - attribute \src "ls180.v:3891.8-3891.87" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3893.5-3895.8" - switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3893.9-3893.42" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3903.4-3905.7" - switch $and$ls180.v:3903$344_Y - attribute \src "ls180.v:3903.8-3903.87" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3909.4-3918.7" - switch \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:3909.8-3909.44" - case 1'1 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3914.5-3916.8" - switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3914.9-3914.42" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3921.4-3923.7" - switch \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:3921.8-3921.45" - case 1'1 - assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3926.4-3928.7" - switch $not$ls180.v:3926$345_Y - attribute \src "ls180.v:3926.8-3926.46" + assign $0\libresocsim_interface1_converted_interface_adr[29:0] { \libresocsim_libresoc_dbus_adr \libresocsim_converter1_counter } + attribute \src "ls180.v:1607.4-1614.11" + switch \libresocsim_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\libresocsim_interface1_converted_interface_sel[3:0] \libresocsim_libresoc_dbus_sel [3:0] + attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'000 + assign $0\libresocsim_interface1_converted_interface_sel[3:0] \libresocsim_libresoc_dbus_sel [7:4] case end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine3_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine3_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3937.4-3963.7" - switch \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:3937.8-3937.43" + attribute \src "ls180.v:1615.4-1628.7" + switch $and$ls180.v:1615$31_Y + attribute \src "ls180.v:1615.8-1615.71" case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'100 - attribute \src "ls180.v:3939.8-3939.12" - case - attribute \src "ls180.v:3940.5-3962.8" - switch \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:3940.9-3940.56" + assign $0\libresocsim_converter1_skip[0:0] $eq$ls180.v:1616$32_Y + assign $0\libresocsim_interface1_converted_interface_we[0:0] \libresocsim_libresoc_dbus_we + assign $0\libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:1618$33_Y + assign $0\libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:1619$34_Y + attribute \src "ls180.v:1620.5-1627.8" + switch $or$ls180.v:1620$35_Y + attribute \src "ls180.v:1620.9-1620.87" case 1'1 - attribute \src "ls180.v:3941.6-3961.9" - switch \main_sdram_bankmachine3_row_opened - attribute \src "ls180.v:3941.10-3941.44" + assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] $add$ls180.v:1621$36_Y + assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:1623.6-1626.9" + switch $eq$ls180.v:1623$37_Y + attribute \src "ls180.v:1623.10-1623.50" case 1'1 - attribute \src "ls180.v:3942.7-3958.10" - switch \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:3942.11-3942.42" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3944.8-3951.11" - switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:3944.12-3944.64" - case 1'1 - assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready - assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3948.12-3948.16" - case - assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready - assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3953.8-3955.11" - switch $and$ls180.v:3953$346_Y - attribute \src "ls180.v:3953.12-3953.88" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3956.11-3956.15" - case - assign $0\builder_bankmachine3_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3959.10-3959.14" + assign $0\libresocsim_libresoc_dbus_ack[0:0] 1'1 + assign $0\subfragments_converter1_next_state[0:0] 1'0 case - assign $0\builder_bankmachine3_next_state[2:0] 3'011 end case end - end - end - sync always - update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] - update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] - update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] - update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] - update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] - end - attribute \src "ls180.v:390.12-390.46" - process $proc$ls180.v:390$3208 - assign { } { } - assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] - end - attribute \src "ls180.v:391.5-391.44" - process $proc$ls180.v:391$3209 - assign { } { } - assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:392.12-392.48" - process $proc$ls180.v:392$3210 - assign { } { } - assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] - end - attribute \src "ls180.v:393.11-393.43" - process $proc$ls180.v:393$3211 - assign { } { } - assign $1\main_sdram_master_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] - end - attribute \src "ls180.v:394.5-394.38" - process $proc$ls180.v:394$3212 - assign { } { } - assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] - end - attribute \src "ls180.v:395.5-395.37" - process $proc$ls180.v:395$3213 - assign { } { } - assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] - end - attribute \src "ls180.v:396.5-396.38" - process $proc$ls180.v:396$3214 - assign { } { } - assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] - end - attribute \src "ls180.v:397.5-397.37" - process $proc$ls180.v:397$3215 - assign { } { } - assign $1\main_sdram_master_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] - end - attribute \src "ls180.v:398.5-398.36" - process $proc$ls180.v:398$3216 - assign { } { } - assign $1\main_sdram_master_p0_cke[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] - end - attribute \src "ls180.v:3986.1-3992.4" - process $proc$ls180.v:3986$385 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3988$398_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3989$411_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3990$424_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3991$437_Y - sync always - update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] - end - attribute \src "ls180.v:399.5-399.36" - process $proc$ls180.v:399$3217 - assign { } { } - assign $1\main_sdram_master_p0_odt[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] - end - attribute \src "ls180.v:400.5-400.40" - process $proc$ls180.v:400$3218 - assign { } { } - assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] - end - attribute \src "ls180.v:4000.1-4005.4" - process $proc$ls180.v:4000$438 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:4002.2-4004.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:4002.6-4002.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:4006.1-4011.4" - process $proc$ls180.v:4006$439 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:4008.2-4010.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:4008.6-4008.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:401.5-401.38" - process $proc$ls180.v:401$3219 - assign { } { } - assign $1\main_sdram_master_p0_act_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] - end - attribute \src "ls180.v:4012.1-4017.4" - process $proc$ls180.v:4012$440 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:4014.2-4016.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:4014.6-4014.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - end - attribute \src "ls180.v:4019.1-4025.4" - process $proc$ls180.v:4019$443 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:4021$456_Y - assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:4022$469_Y - assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:4023$482_Y - assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:4024$495_Y - sync always - update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] - end - attribute \src "ls180.v:402.12-402.47" - process $proc$ls180.v:402$3220 - assign { } { } - assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] - end - attribute \src "ls180.v:403.5-403.42" - process $proc$ls180.v:403$3221 - assign { } { } - assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:4033.1-4038.4" - process $proc$ls180.v:4033$496 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:4035.2-4037.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:4035.6-4035.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:4039.1-4044.4" - process $proc$ls180.v:4039$497 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:4041.2-4043.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:4041.6-4041.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:404.11-404.50" - process $proc$ls180.v:404$3222 - assign { } { } - assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] - end - attribute \src "ls180.v:4045.1-4050.4" - process $proc$ls180.v:4045$498 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:4047.2-4049.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:4047.6-4047.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] - end - attribute \src "ls180.v:405.5-405.42" - process $proc$ls180.v:405$3223 - assign { } { } - assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] - end - attribute \src "ls180.v:4051.1-4059.4" - process $proc$ls180.v:4051$499 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4053.2-4055.5" - switch $and$ls180.v:4053$502_Y - attribute \src "ls180.v:4053.6-4053.115" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:4056.2-4058.5" - switch $and$ls180.v:4056$505_Y - attribute \src "ls180.v:4056.6-4056.115" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] - end - attribute \src "ls180.v:4060.1-4068.4" - process $proc$ls180.v:4060$506 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4062.2-4064.5" - switch $and$ls180.v:4062$509_Y - attribute \src "ls180.v:4062.6-4062.115" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:4065.2-4067.5" - switch $and$ls180.v:4065$512_Y - attribute \src "ls180.v:4065.6-4065.115" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] - end - attribute \src "ls180.v:4069.1-4077.4" - process $proc$ls180.v:4069$513 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4071.2-4073.5" - switch $and$ls180.v:4071$516_Y - attribute \src "ls180.v:4071.6-4071.115" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:4074.2-4076.5" - switch $and$ls180.v:4074$519_Y - attribute \src "ls180.v:4074.6-4074.115" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] - end - attribute \src "ls180.v:4078.1-4086.4" - process $proc$ls180.v:4078$520 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4080.2-4082.5" - switch $and$ls180.v:4080$523_Y - attribute \src "ls180.v:4080.6-4080.115" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:4083.2-4085.5" - switch $and$ls180.v:4083$526_Y - attribute \src "ls180.v:4083.6-4083.115" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] - end - attribute \src "ls180.v:4091.1-4163.4" - process $proc$ls180.v:4091$529 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_en1[0:0] 1'0 - assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 - assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 - assign $0\main_sdram_cmd_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 - assign $0\main_sdram_steerer_sel[1:0] 2'00 - assign $0\main_sdram_en0[0:0] 1'0 - assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed - assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state - attribute \src "ls180.v:4103.2-4162.9" - switch \builder_multiplexer_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_en1[0:0] 1'1 - assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 - assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:4107.4-4113.7" - switch 1'1 - attribute \src "ls180.v:4107.8-4107.12" - case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4108$536_Y - case - end - attribute \src "ls180.v:4115.4-4119.7" - switch \main_sdram_read_available - attribute \src "ls180.v:4115.8-4115.33" - case 1'1 - attribute \src "ls180.v:4116.5-4118.8" - switch $or$ls180.v:4116$538_Y - attribute \src "ls180.v:4116.9-4116.63" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'011 - case - end - case - end - attribute \src "ls180.v:4120.4-4122.7" - switch \main_sdram_go_to_refresh - attribute \src "ls180.v:4120.8-4120.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_steerer_sel[1:0] 2'11 - assign $0\main_sdram_cmd_ready[0:0] 1'1 - attribute \src "ls180.v:4127.4-4129.7" - switch \main_sdram_cmd_last - attribute \src "ls180.v:4127.8-4127.27" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:4132.4-4134.7" - switch \main_sdram_twtrcon_ready - attribute \src "ls180.v:4132.8-4132.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_multiplexer_next_state[2:0] 3'101 - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_multiplexer_next_state[2:0] 3'001 - attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdram_en0[0:0] 1'1 - assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 - assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:4145.4-4151.7" - switch 1'1 - attribute \src "ls180.v:4145.8-4145.12" - case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4146$545_Y - case - end - attribute \src "ls180.v:4153.4-4157.7" - switch \main_sdram_write_available - attribute \src "ls180.v:4153.8-4153.34" - case 1'1 - attribute \src "ls180.v:4154.5-4156.8" - switch $or$ls180.v:4154$547_Y - attribute \src "ls180.v:4154.9-4154.62" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'100 - case - end - case - end - attribute \src "ls180.v:4158.4-4160.7" - switch \main_sdram_go_to_refresh - attribute \src "ls180.v:4158.8-4158.32" + assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] 1'0 + assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:1633.4-1635.7" + switch $and$ls180.v:1633$38_Y + attribute \src "ls180.v:1633.8-1633.71" case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'010 + assign $0\subfragments_converter1_next_state[0:0] 1'1 case end end sync always - update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] - update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] - update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] - update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] - update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] - update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] - update \main_sdram_en0 $0\main_sdram_en0[0:0] - update \main_sdram_en1 $0\main_sdram_en1[0:0] - update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] - end - attribute \src "ls180.v:412.11-412.36" - process $proc$ls180.v:412$3224 - assign { } { } - assign $1\main_sdram_storage[3:0] 4'0001 - sync always - sync init - update \main_sdram_storage $1\main_sdram_storage[3:0] - end - attribute \src "ls180.v:413.5-413.25" - process $proc$ls180.v:413$3225 - assign { } { } - assign $1\main_sdram_re[0:0] 1'0 - sync always - sync init - update \main_sdram_re $1\main_sdram_re[0:0] - end - attribute \src "ls180.v:414.11-414.44" - process $proc$ls180.v:414$3226 - assign { } { } - assign $1\main_sdram_command_storage[5:0] 6'000000 - sync always - sync init - update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + update \libresocsim_libresoc_dbus_ack $0\libresocsim_libresoc_dbus_ack[0:0] + update \libresocsim_interface1_converted_interface_adr $0\libresocsim_interface1_converted_interface_adr[29:0] + update \libresocsim_interface1_converted_interface_sel $0\libresocsim_interface1_converted_interface_sel[3:0] + update \libresocsim_interface1_converted_interface_cyc $0\libresocsim_interface1_converted_interface_cyc[0:0] + update \libresocsim_interface1_converted_interface_stb $0\libresocsim_interface1_converted_interface_stb[0:0] + update \libresocsim_interface1_converted_interface_we $0\libresocsim_interface1_converted_interface_we[0:0] + update \libresocsim_converter1_skip $0\libresocsim_converter1_skip[0:0] + update \subfragments_converter1_next_state $0\subfragments_converter1_next_state[0:0] + update \libresocsim_converter1_counter_subfragments_converter1_next_value $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] + update \libresocsim_converter1_counter_subfragments_converter1_next_value_ce $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:415.5-415.33" - process $proc$ls180.v:415$3227 + attribute \src "ls180.v:161.11-161.64" + process $proc$ls180.v:161$1590 assign { } { } - assign $1\main_sdram_command_re[0:0] 1'0 + assign $1\libresocsim_interface1_converted_interface_sel[3:0] 4'0000 sync always sync init - update \main_sdram_command_re $1\main_sdram_command_re[0:0] - end - attribute \src "ls180.v:4187.1-4200.4" - process $proc$ls180.v:4187$676 - assign { } { } - assign { } { } - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 - assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - attribute \src "ls180.v:4190.2-4199.9" - switch \builder_new_master_wdata_ready - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data - assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 - assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - end - sync always - update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] - update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] + update \libresocsim_interface1_converted_interface_sel $1\libresocsim_interface1_converted_interface_sel[3:0] end - attribute \src "ls180.v:419.5-419.38" - process $proc$ls180.v:419$3228 + attribute \src "ls180.v:162.5-162.58" + process $proc$ls180.v:162$1591 assign { } { } - assign $0\main_sdram_command_issue_w[0:0] 1'0 + assign $1\libresocsim_interface1_converted_interface_cyc[0:0] 1'0 sync always - update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] sync init + update \libresocsim_interface1_converted_interface_cyc $1\libresocsim_interface1_converted_interface_cyc[0:0] end - attribute \src "ls180.v:420.12-420.46" - process $proc$ls180.v:420$3229 + attribute \src "ls180.v:163.5-163.58" + process $proc$ls180.v:163$1592 assign { } { } - assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + assign $1\libresocsim_interface1_converted_interface_stb[0:0] 1'0 sync always sync init - update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + update \libresocsim_interface1_converted_interface_stb $1\libresocsim_interface1_converted_interface_stb[0:0] end - attribute \src "ls180.v:4207.1-4217.4" - process $proc$ls180.v:4207$678 + attribute \src "ls180.v:1640.1-1650.4" + process $proc$ls180.v:1640$40 assign { } { } - assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - attribute \src "ls180.v:4209.2-4216.9" - switch \main_converter_counter + assign $0\libresocsim_interface2_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:1642.2-1649.9" + switch \libresocsim_converter2_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] + assign $0\libresocsim_interface2_converted_interface_dat_w[31:0] \libresocsim_libresoc_jtag_wb_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] + assign $0\libresocsim_interface2_converted_interface_dat_w[31:0] \libresocsim_libresoc_jtag_wb_dat_w [63:32] case end sync always - update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] + update \libresocsim_interface2_converted_interface_dat_w $0\libresocsim_interface2_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:421.5-421.33" - process $proc$ls180.v:421$3230 + attribute \src "ls180.v:165.5-165.57" + process $proc$ls180.v:165$1593 assign { } { } - assign $1\main_sdram_address_re[0:0] 1'0 + assign $1\libresocsim_interface1_converted_interface_we[0:0] 1'0 sync always sync init - update \main_sdram_address_re $1\main_sdram_address_re[0:0] + update \libresocsim_interface1_converted_interface_we $1\libresocsim_interface1_converted_interface_we[0:0] end - attribute \src "ls180.v:4219.1-4265.4" - process $proc$ls180.v:4219$679 + attribute \src "ls180.v:1652.1-1698.4" + process $proc$ls180.v:1652$41 assign { } { } assign { } { } assign { } { } @@ -293007,52 +262205,52 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_litedram_wb_sel[1:0] 2'00 - assign $0\main_litedram_wb_cyc[0:0] 1'0 + assign $0\libresocsim_converter2_skip[0:0] 1'0 + assign $0\libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + assign $0\libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 assign { } { } - assign $0\main_litedram_wb_stb[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 - assign $0\main_litedram_wb_we[0:0] 1'0 - assign $0\main_converter_skip[0:0] 1'0 - assign $0\main_wb_sdram_ack[0:0] 1'0 - assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 - assign $0\builder_converter_next_state[0:0] \builder_converter_state - attribute \src "ls180.v:4231.2-4264.9" - switch \builder_converter_state + assign $0\libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] 1'0 + assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'0 + assign $0\libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + assign $0\libresocsim_interface2_converted_interface_stb[0:0] 1'0 + assign $0\libresocsim_interface2_converted_interface_we[0:0] 1'0 + assign $0\subfragments_converter2_next_state[0:0] \subfragments_converter2_state + attribute \src "ls180.v:1664.2-1697.9" + switch \subfragments_converter2_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } - attribute \src "ls180.v:4234.4-4241.11" - switch \main_converter_counter + assign $0\libresocsim_interface2_converted_interface_adr[29:0] { \libresocsim_libresoc_jtag_wb_adr \libresocsim_converter2_counter } + attribute \src "ls180.v:1667.4-1674.11" + switch \libresocsim_converter2_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] + assign $0\libresocsim_interface2_converted_interface_sel[3:0] \libresocsim_libresoc_jtag_wb_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] + assign $0\libresocsim_interface2_converted_interface_sel[3:0] \libresocsim_libresoc_jtag_wb_sel [7:4] case end - attribute \src "ls180.v:4242.4-4255.7" - switch $and$ls180.v:4242$680_Y - attribute \src "ls180.v:4242.8-4242.47" + attribute \src "ls180.v:1675.4-1688.7" + switch $and$ls180.v:1675$42_Y + attribute \src "ls180.v:1675.8-1675.77" case 1'1 - assign $0\main_converter_skip[0:0] $eq$ls180.v:4243$681_Y - assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we - assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4245$682_Y - assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4246$683_Y - attribute \src "ls180.v:4247.5-4254.8" - switch $or$ls180.v:4247$684_Y - attribute \src "ls180.v:4247.9-4247.53" + assign $0\libresocsim_converter2_skip[0:0] $eq$ls180.v:1676$43_Y + assign $0\libresocsim_interface2_converted_interface_we[0:0] \libresocsim_libresoc_jtag_wb_we + assign $0\libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:1678$44_Y + assign $0\libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:1679$45_Y + attribute \src "ls180.v:1680.5-1687.8" + switch $or$ls180.v:1680$46_Y + attribute \src "ls180.v:1680.9-1680.87" case 1'1 - assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4248$685_Y - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4250.6-4253.9" - switch $eq$ls180.v:4250$686_Y - attribute \src "ls180.v:4250.10-4250.42" + assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] $add$ls180.v:1681$47_Y + assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:1683.6-1686.9" + switch $eq$ls180.v:1683$48_Y + attribute \src "ls180.v:1683.10-1683.50" case 1'1 - assign $0\main_wb_sdram_ack[0:0] 1'1 - assign $0\builder_converter_next_state[0:0] 1'0 + assign $0\libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 + assign $0\subfragments_converter2_next_state[0:0] 1'0 case end case @@ -293061,258 +262259,130 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4260.4-4262.7" - switch $and$ls180.v:4260$687_Y - attribute \src "ls180.v:4260.8-4260.47" + assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] 1'0 + assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:1693.4-1695.7" + switch $and$ls180.v:1693$49_Y + attribute \src "ls180.v:1693.8-1693.77" case 1'1 - assign $0\builder_converter_next_state[0:0] 1'1 + assign $0\subfragments_converter2_next_state[0:0] 1'1 case end end sync always - update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] - update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] - update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] - update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] - update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] - update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] - update \main_converter_skip $0\main_converter_skip[0:0] - update \builder_converter_next_state $0\builder_converter_next_state[0:0] - update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] - update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] - end - attribute \src "ls180.v:422.11-422.45" - process $proc$ls180.v:422$3231 - assign { } { } - assign $1\main_sdram_baddress_storage[1:0] 2'00 - sync always - sync init - update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + update \libresocsim_libresoc_jtag_wb_ack $0\libresocsim_libresoc_jtag_wb_ack[0:0] + update \libresocsim_interface2_converted_interface_adr $0\libresocsim_interface2_converted_interface_adr[29:0] + update \libresocsim_interface2_converted_interface_sel $0\libresocsim_interface2_converted_interface_sel[3:0] + update \libresocsim_interface2_converted_interface_cyc $0\libresocsim_interface2_converted_interface_cyc[0:0] + update \libresocsim_interface2_converted_interface_stb $0\libresocsim_interface2_converted_interface_stb[0:0] + update \libresocsim_interface2_converted_interface_we $0\libresocsim_interface2_converted_interface_we[0:0] + update \libresocsim_converter2_skip $0\libresocsim_converter2_skip[0:0] + update \subfragments_converter2_next_state $0\subfragments_converter2_next_state[0:0] + update \libresocsim_converter2_counter_subfragments_converter2_next_value $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] + update \libresocsim_converter2_counter_subfragments_converter2_next_value_ce $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:423.5-423.34" - process $proc$ls180.v:423$3232 + attribute \src "ls180.v:166.11-166.64" + process $proc$ls180.v:166$1594 assign { } { } - assign $1\main_sdram_baddress_re[0:0] 1'0 + assign $0\libresocsim_interface1_converted_interface_cti[2:0] 3'000 sync always + update \libresocsim_interface1_converted_interface_cti $0\libresocsim_interface1_converted_interface_cti[2:0] sync init - update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] end - attribute \src "ls180.v:424.12-424.45" - process $proc$ls180.v:424$3233 + attribute \src "ls180.v:167.11-167.64" + process $proc$ls180.v:167$1595 assign { } { } - assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + assign $0\libresocsim_interface1_converted_interface_bte[1:0] 2'00 sync always + update \libresocsim_interface1_converted_interface_bte $0\libresocsim_interface1_converted_interface_bte[1:0] sync init - update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] end - attribute \src "ls180.v:425.5-425.32" - process $proc$ls180.v:425$3234 + attribute \src "ls180.v:169.5-169.39" + process $proc$ls180.v:169$1596 assign { } { } - assign $1\main_sdram_wrdata_re[0:0] 1'0 + assign $1\libresocsim_converter1_skip[0:0] 1'0 sync always sync init - update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + update \libresocsim_converter1_skip $1\libresocsim_converter1_skip[0:0] end - attribute \src "ls180.v:426.12-426.37" - process $proc$ls180.v:426$3235 + attribute \src "ls180.v:170.5-170.42" + process $proc$ls180.v:170$1597 assign { } { } - assign $1\main_sdram_status[15:0] 16'0000000000000000 + assign $1\libresocsim_converter1_counter[0:0] 1'0 sync always sync init - update \main_sdram_status $1\main_sdram_status[15:0] - end - attribute \src "ls180.v:4310.1-4315.4" - process $proc$ls180.v:4310$719 - assign { } { } - assign $0\main_uart_tx_clear[0:0] 1'0 - attribute \src "ls180.v:4312.2-4314.5" - switch $and$ls180.v:4312$720_Y - attribute \src "ls180.v:4312.6-4312.79" - case 1'1 - assign $0\main_uart_tx_clear[0:0] 1'1 - case - end - sync always - update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] + update \libresocsim_converter1_counter $1\libresocsim_converter1_counter[0:0] end - attribute \src "ls180.v:4316.1-4320.4" - process $proc$ls180.v:4316$721 + attribute \src "ls180.v:1701.1-1707.4" + process $proc$ls180.v:1701$50 assign { } { } assign { } { } - assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status - assign $0\main_uart_eventmanager_status_w[1:0] [1] \main_uart_rx_status + assign $0\libresocsim_we[3:0] [0] $and$ls180.v:1703$53_Y + assign $0\libresocsim_we[3:0] [1] $and$ls180.v:1704$56_Y + assign $0\libresocsim_we[3:0] [2] $and$ls180.v:1705$59_Y + assign $0\libresocsim_we[3:0] [3] $and$ls180.v:1706$62_Y sync always - update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] + update \libresocsim_we $0\libresocsim_we[3:0] end - attribute \src "ls180.v:4321.1-4326.4" - process $proc$ls180.v:4321$722 + attribute \src "ls180.v:1713.1-1718.4" + process $proc$ls180.v:1713$64 assign { } { } - assign $0\main_uart_rx_clear[0:0] 1'0 - attribute \src "ls180.v:4323.2-4325.5" - switch $and$ls180.v:4323$723_Y - attribute \src "ls180.v:4323.6-4323.79" + assign $0\libresocsim_zero_clear[0:0] 1'0 + attribute \src "ls180.v:1715.2-1717.5" + switch $and$ls180.v:1715$65_Y + attribute \src "ls180.v:1715.6-1715.80" case 1'1 - assign $0\main_uart_rx_clear[0:0] 1'1 + assign $0\libresocsim_zero_clear[0:0] 1'1 case end sync always - update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] + update \libresocsim_zero_clear $0\libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:4327.1-4331.4" - process $proc$ls180.v:4327$724 + attribute \src "ls180.v:172.12-172.48" + process $proc$ls180.v:172$1598 assign { } { } - assign { } { } - assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending - assign $0\main_uart_eventmanager_pending_w[1:0] [1] \main_uart_rx_pending + assign $1\libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] + sync init + update \libresocsim_converter1_dat_r $1\libresocsim_converter1_dat_r[63:0] end - attribute \src "ls180.v:4349.1-4356.4" - process $proc$ls180.v:4349$732 + attribute \src "ls180.v:1722.1-1728.4" + process $proc$ls180.v:1722$67 assign { } { } - assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4351.2-4355.5" - switch \main_uart_tx_fifo_replace - attribute \src "ls180.v:4351.6-4351.31" - case 1'1 - assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4352$733_Y - attribute \src "ls180.v:4353.6-4353.10" - case - assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce - end - sync always - update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:4379.1-4386.4" - process $proc$ls180.v:4379$743 assign { } { } - assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4381.2-4385.5" - switch \main_uart_rx_fifo_replace - attribute \src "ls180.v:4381.6-4381.31" - case 1'1 - assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4382$744_Y - attribute \src "ls180.v:4383.6-4383.10" - case - assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce - end + assign $0\ram_we[3:0] [0] $and$ls180.v:1724$70_Y + assign $0\ram_we[3:0] [1] $and$ls180.v:1725$73_Y + assign $0\ram_we[3:0] [2] $and$ls180.v:1726$76_Y + assign $0\ram_we[3:0] [3] $and$ls180.v:1727$79_Y sync always - update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] + update \ram_we $0\ram_we[3:0] end - attribute \src "ls180.v:4399.1-4403.4" - process $proc$ls180.v:4399$750 - assign { } { } - assign { } { } + attribute \src "ls180.v:173.12-173.66" + process $proc$ls180.v:173$1599 assign { } { } - assign $0\gpio_o[15:0] \main_gpiotristateasic1_pads_o + assign $1\libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 sync always - update \gpio_o $0\gpio_o[15:0] + sync init + update \libresocsim_interface2_converted_interface_adr $1\libresocsim_interface2_converted_interface_adr[29:0] end - attribute \src "ls180.v:4404.1-4408.4" - process $proc$ls180.v:4404$751 - assign { } { } + attribute \src "ls180.v:174.12-174.68" + process $proc$ls180.v:174$1600 assign { } { } - assign { } { } - assign $0\gpio_oe[15:0] \main_gpiotristateasic1_pads_oe + assign $1\libresocsim_interface2_converted_interface_dat_w[31:0] 0 sync always - update \gpio_oe $0\gpio_oe[15:0] + sync init + update \libresocsim_interface2_converted_interface_dat_w $1\libresocsim_interface2_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:4420.1-4468.4" - process $proc$ls180.v:4420$756 - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:176.11-176.64" + process $proc$ls180.v:176$1601 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 - assign $0\main_spimaster25_clk_enable[0:0] 1'0 - assign $0\main_spimaster26_cs_enable[0:0] 1'0 - assign $0\main_spimaster28_mosi_latch[0:0] 1'0 - assign $0\main_spimaster2_done[0:0] 1'0 - assign $0\main_spimaster29_miso_latch[0:0] 1'0 - assign $0\main_spimaster3_irq[0:0] 1'0 - assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state - attribute \src "ls180.v:4431.2-4467.9" - switch \builder_spimaster0_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4435.4-4438.7" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4435.8-4435.33" - case 1'1 - assign $0\main_spimaster26_cs_enable[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_spimaster25_clk_enable[0:0] 1'1 - assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4443.4-4449.7" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4443.8-4443.33" - case 1'1 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4444$757_Y - assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4446.5-4448.8" - switch $eq$ls180.v:4446$759_Y - attribute \src "ls180.v:4446.9-4446.68" - case 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'11 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4453.4-4457.7" - switch \main_spimaster31_clk_rise - attribute \src "ls180.v:4453.8-4453.33" - case 1'1 - assign $0\main_spimaster29_miso_latch[0:0] 1'1 - assign $0\main_spimaster3_irq[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_spimaster2_done[0:0] 1'1 - attribute \src "ls180.v:4461.4-4465.7" - switch \main_spimaster0_start - attribute \src "ls180.v:4461.8-4461.29" - case 1'1 - assign $0\main_spimaster2_done[0:0] 1'0 - assign $0\main_spimaster28_mosi_latch[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'01 - case - end - end + assign $1\libresocsim_interface2_converted_interface_sel[3:0] 4'0000 sync always - update \main_spimaster2_done $0\main_spimaster2_done[0:0] - update \main_spimaster3_irq $0\main_spimaster3_irq[0:0] - update \main_spimaster25_clk_enable $0\main_spimaster25_clk_enable[0:0] - update \main_spimaster26_cs_enable $0\main_spimaster26_cs_enable[0:0] - update \main_spimaster28_mosi_latch $0\main_spimaster28_mosi_latch[0:0] - update \main_spimaster29_miso_latch $0\main_spimaster29_miso_latch[0:0] - update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] - update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] - update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] + sync init + update \libresocsim_interface2_converted_interface_sel $1\libresocsim_interface2_converted_interface_sel[3:0] end - attribute \src "ls180.v:4479.1-4527.4" - process $proc$ls180.v:4479$764 - assign { } { } - assign { } { } + attribute \src "ls180.v:1767.1-1821.4" + process $proc$ls180.v:1767$80 assign { } { } assign { } { } assign { } { } @@ -293320,137 +262390,8 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 - assign $0\main_spisdcard_clk_enable[0:0] 1'0 - assign $0\main_spisdcard_cs_enable[0:0] 1'0 - assign $0\main_spisdcard_mosi_latch[0:0] 1'0 - assign $0\main_spisdcard_done0[0:0] 1'0 - assign $0\main_spisdcard_miso_latch[0:0] 1'0 - assign $0\main_spisdcard_irq[0:0] 1'0 - assign { } { } - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 - assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state - attribute \src "ls180.v:4490.2-4526.9" - switch \builder_spimaster1_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4494.4-4497.7" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4494.8-4494.31" - case 1'1 - assign $0\main_spisdcard_cs_enable[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_spisdcard_clk_enable[0:0] 1'1 - assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4502.4-4508.7" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4502.8-4502.31" - case 1'1 - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4503$765_Y - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4505.5-4507.8" - switch $eq$ls180.v:4505$767_Y - attribute \src "ls180.v:4505.9-4505.66" - case 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'11 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4512.4-4516.7" - switch \main_spisdcard_clk_rise - attribute \src "ls180.v:4512.8-4512.31" - case 1'1 - assign $0\main_spisdcard_miso_latch[0:0] 1'1 - assign $0\main_spisdcard_irq[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_spisdcard_done0[0:0] 1'1 - attribute \src "ls180.v:4520.4-4524.7" - switch \main_spisdcard_start0 - attribute \src "ls180.v:4520.8-4520.29" - case 1'1 - assign $0\main_spisdcard_done0[0:0] 1'0 - assign $0\main_spisdcard_mosi_latch[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'01 - case - end - end - sync always - update \main_spisdcard_done0 $0\main_spisdcard_done0[0:0] - update \main_spisdcard_irq $0\main_spisdcard_irq[0:0] - update \main_spisdcard_clk_enable $0\main_spisdcard_clk_enable[0:0] - update \main_spisdcard_cs_enable $0\main_spisdcard_cs_enable[0:0] - update \main_spisdcard_mosi_latch $0\main_spisdcard_mosi_latch[0:0] - update \main_spisdcard_miso_latch $0\main_spisdcard_miso_latch[0:0] - update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] - update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] - update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] - end - attribute \src "ls180.v:4559.1-4587.4" - process $proc$ls180.v:4559$789 - assign { } { } - assign $0\main_sdphy_clocker_clk1[0:0] 1'0 - attribute \src "ls180.v:4561.2-4586.9" - switch \main_sdphy_clocker_storage - attribute \src "ls180.v:0.0-0.0" - case 9'000000100 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [1] - attribute \src "ls180.v:0.0-0.0" - case 9'000001000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [2] - attribute \src "ls180.v:0.0-0.0" - case 9'000010000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [3] - attribute \src "ls180.v:0.0-0.0" - case 9'000100000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [4] - attribute \src "ls180.v:0.0-0.0" - case 9'001000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [5] - attribute \src "ls180.v:0.0-0.0" - case 9'010000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [6] - attribute \src "ls180.v:0.0-0.0" - case 9'100000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [7] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [0] - end - sync always - update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] - end - attribute \src "ls180.v:456.12-456.46" - process $proc$ls180.v:456$3236 assign { } { } - assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] - end - attribute \src "ls180.v:457.11-457.47" - process $proc$ls180.v:457$3237 assign { } { } - assign $1\main_sdram_interface_wdata_we[1:0] 2'00 - sync always - sync init - update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] - end - attribute \src "ls180.v:4589.1-4622.4" - process $proc$ls180.v:4589$792 assign { } { } assign { } { } assign { } { } @@ -293459,257 +262400,299 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 - assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 assign { } { } - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:4599.2-4621.9" - switch \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:0.0-0.0" + assign $0\sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $0\sdram_slave_p0_rddata_valid[0:0] 1'0 + assign $0\sdram_master_p0_address[12:0] 13'0000000000000 + assign $0\sdram_master_p0_bank[1:0] 2'00 + assign $0\sdram_master_p0_cas_n[0:0] 1'1 + assign $0\sdram_master_p0_cs_n[0:0] 1'1 + assign $0\sdram_master_p0_ras_n[0:0] 1'1 + assign $0\sdram_master_p0_we_n[0:0] 1'1 + assign $0\sdram_master_p0_cke[0:0] 1'0 + assign $0\sdram_master_p0_odt[0:0] 1'0 + assign $0\sdram_master_p0_reset_n[0:0] 1'0 + assign $0\sdram_master_p0_act_n[0:0] 1'1 + assign $0\sdram_inti_p0_rddata[15:0] 16'0000000000000000 + assign $0\sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $0\sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $0\sdram_master_p0_wrdata_en[0:0] 1'0 + assign $0\sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $0\sdram_master_p0_rddata_en[0:0] 1'0 + attribute \src "ls180.v:1786.2-1820.5" + switch \sdram_sel + attribute \src "ls180.v:1786.6-1786.15" case 1'1 - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4606.4-4612.7" - switch \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:4606.8-4606.38" - case 1'1 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4607$793_Y - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4609.5-4611.8" - switch $eq$ls180.v:4609$794_Y - attribute \src "ls180.v:4609.9-4609.41" - case 1'1 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" + assign $0\sdram_master_p0_address[12:0] \sdram_slave_p0_address + assign $0\sdram_master_p0_bank[1:0] \sdram_slave_p0_bank + assign $0\sdram_master_p0_cas_n[0:0] \sdram_slave_p0_cas_n + assign $0\sdram_master_p0_cs_n[0:0] \sdram_slave_p0_cs_n + assign $0\sdram_master_p0_ras_n[0:0] \sdram_slave_p0_ras_n + assign $0\sdram_master_p0_we_n[0:0] \sdram_slave_p0_we_n + assign $0\sdram_master_p0_cke[0:0] \sdram_slave_p0_cke + assign $0\sdram_master_p0_odt[0:0] \sdram_slave_p0_odt + assign $0\sdram_master_p0_reset_n[0:0] \sdram_slave_p0_reset_n + assign $0\sdram_master_p0_act_n[0:0] \sdram_slave_p0_act_n + assign $0\sdram_master_p0_wrdata[15:0] \sdram_slave_p0_wrdata + assign $0\sdram_master_p0_wrdata_en[0:0] \sdram_slave_p0_wrdata_en + assign $0\sdram_master_p0_wrdata_mask[1:0] \sdram_slave_p0_wrdata_mask + assign $0\sdram_master_p0_rddata_en[0:0] \sdram_slave_p0_rddata_en + assign $0\sdram_slave_p0_rddata[15:0] \sdram_master_p0_rddata + assign $0\sdram_slave_p0_rddata_valid[0:0] \sdram_master_p0_rddata_valid + attribute \src "ls180.v:1803.6-1803.10" case - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4617.4-4619.7" - switch \main_sdphy_init_initialize_re - attribute \src "ls180.v:4617.8-4617.37" - case 1'1 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 - case - end + assign $0\sdram_master_p0_address[12:0] \sdram_inti_p0_address + assign $0\sdram_master_p0_bank[1:0] \sdram_inti_p0_bank + assign $0\sdram_master_p0_cas_n[0:0] \sdram_inti_p0_cas_n + assign $0\sdram_master_p0_cs_n[0:0] \sdram_inti_p0_cs_n + assign $0\sdram_master_p0_ras_n[0:0] \sdram_inti_p0_ras_n + assign $0\sdram_master_p0_we_n[0:0] \sdram_inti_p0_we_n + assign $0\sdram_master_p0_cke[0:0] \sdram_inti_p0_cke + assign $0\sdram_master_p0_odt[0:0] \sdram_inti_p0_odt + assign $0\sdram_master_p0_reset_n[0:0] \sdram_inti_p0_reset_n + assign $0\sdram_master_p0_act_n[0:0] \sdram_inti_p0_act_n + assign $0\sdram_master_p0_wrdata[15:0] \sdram_inti_p0_wrdata + assign $0\sdram_master_p0_wrdata_en[0:0] \sdram_inti_p0_wrdata_en + assign $0\sdram_master_p0_wrdata_mask[1:0] \sdram_inti_p0_wrdata_mask + assign $0\sdram_master_p0_rddata_en[0:0] \sdram_inti_p0_rddata_en + assign $0\sdram_inti_p0_rddata[15:0] \sdram_master_p0_rddata + assign $0\sdram_inti_p0_rddata_valid[0:0] \sdram_master_p0_rddata_valid end sync always - update \main_sdphy_init_pads_out_payload_clk $0\main_sdphy_init_pads_out_payload_clk[0:0] - update \main_sdphy_init_pads_out_payload_cmd_o $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - update \main_sdphy_init_pads_out_payload_cmd_oe $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_init_pads_out_payload_data_o $0\main_sdphy_init_pads_out_payload_data_o[3:0] - update \main_sdphy_init_pads_out_payload_data_oe $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] - update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + update \sdram_inti_p0_rddata $0\sdram_inti_p0_rddata[15:0] + update \sdram_inti_p0_rddata_valid $0\sdram_inti_p0_rddata_valid[0:0] + update \sdram_slave_p0_rddata $0\sdram_slave_p0_rddata[15:0] + update \sdram_slave_p0_rddata_valid $0\sdram_slave_p0_rddata_valid[0:0] + update \sdram_master_p0_address $0\sdram_master_p0_address[12:0] + update \sdram_master_p0_bank $0\sdram_master_p0_bank[1:0] + update \sdram_master_p0_cas_n $0\sdram_master_p0_cas_n[0:0] + update \sdram_master_p0_cs_n $0\sdram_master_p0_cs_n[0:0] + update \sdram_master_p0_ras_n $0\sdram_master_p0_ras_n[0:0] + update \sdram_master_p0_we_n $0\sdram_master_p0_we_n[0:0] + update \sdram_master_p0_cke $0\sdram_master_p0_cke[0:0] + update \sdram_master_p0_odt $0\sdram_master_p0_odt[0:0] + update \sdram_master_p0_reset_n $0\sdram_master_p0_reset_n[0:0] + update \sdram_master_p0_act_n $0\sdram_master_p0_act_n[0:0] + update \sdram_master_p0_wrdata $0\sdram_master_p0_wrdata[15:0] + update \sdram_master_p0_wrdata_en $0\sdram_master_p0_wrdata_en[0:0] + update \sdram_master_p0_wrdata_mask $0\sdram_master_p0_wrdata_mask[1:0] + update \sdram_master_p0_rddata_en $0\sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:177.5-177.58" + process $proc$ls180.v:177$1602 + assign { } { } + assign $1\libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \libresocsim_interface2_converted_interface_cyc $1\libresocsim_interface2_converted_interface_cyc[0:0] end - attribute \src "ls180.v:459.12-459.45" - process $proc$ls180.v:459$3238 + attribute \src "ls180.v:178.5-178.58" + process $proc$ls180.v:178$1603 assign { } { } - assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $1\libresocsim_interface2_converted_interface_stb[0:0] 1'0 sync always sync init - update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] + update \libresocsim_interface2_converted_interface_stb $1\libresocsim_interface2_converted_interface_stb[0:0] end - attribute \src "ls180.v:460.11-460.40" - process $proc$ls180.v:460$3239 + attribute \src "ls180.v:180.5-180.57" + process $proc$ls180.v:180$1604 assign { } { } - assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + assign $1\libresocsim_interface2_converted_interface_we[0:0] 1'0 sync always sync init - update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + update \libresocsim_interface2_converted_interface_we $1\libresocsim_interface2_converted_interface_we[0:0] end - attribute \src "ls180.v:461.5-461.35" - process $proc$ls180.v:461$3240 + attribute \src "ls180.v:181.11-181.64" + process $proc$ls180.v:181$1605 assign { } { } - assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + assign $0\libresocsim_interface2_converted_interface_cti[2:0] 3'000 sync always + update \libresocsim_interface2_converted_interface_cti $0\libresocsim_interface2_converted_interface_cti[2:0] sync init - update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] end - attribute \src "ls180.v:462.5-462.34" - process $proc$ls180.v:462$3241 + attribute \src "ls180.v:182.11-182.64" + process $proc$ls180.v:182$1606 assign { } { } - assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + assign $0\libresocsim_interface2_converted_interface_bte[1:0] 2'00 sync always + update \libresocsim_interface2_converted_interface_bte $0\libresocsim_interface2_converted_interface_bte[1:0] sync init - update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] end - attribute \src "ls180.v:4623.1-4699.4" - process $proc$ls180.v:4623$795 + attribute \src "ls180.v:1825.1-1841.4" + process $proc$ls180.v:1825$81 + assign { } { } + assign { } { } + assign { } { } assign { } { } + assign $0\sdram_inti_p0_ras_n[0:0] 1'1 + assign $0\sdram_inti_p0_we_n[0:0] 1'1 + assign $0\sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\sdram_inti_p0_cs_n[0:0] 1'1 + attribute \src "ls180.v:1830.2-1840.5" + switch \sdram_command_issue_re + attribute \src "ls180.v:1830.6-1830.28" + case 1'1 + assign $0\sdram_inti_p0_cs_n[0:0] $not$ls180.v:1831$82_Y + assign $0\sdram_inti_p0_we_n[0:0] $not$ls180.v:1832$83_Y + assign $0\sdram_inti_p0_cas_n[0:0] $not$ls180.v:1833$84_Y + assign $0\sdram_inti_p0_ras_n[0:0] $not$ls180.v:1834$85_Y + attribute \src "ls180.v:1835.6-1835.10" + case + assign $0\sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\sdram_inti_p0_we_n[0:0] 1'1 + assign $0\sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\sdram_inti_p0_ras_n[0:0] 1'1 + end + sync always + update \sdram_inti_p0_cas_n $0\sdram_inti_p0_cas_n[0:0] + update \sdram_inti_p0_cs_n $0\sdram_inti_p0_cs_n[0:0] + update \sdram_inti_p0_ras_n $0\sdram_inti_p0_ras_n[0:0] + update \sdram_inti_p0_we_n $0\sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:184.5-184.39" + process $proc$ls180.v:184$1607 assign { } { } + assign $1\libresocsim_converter2_skip[0:0] 1'0 + sync always + sync init + update \libresocsim_converter2_skip $1\libresocsim_converter2_skip[0:0] + end + attribute \src "ls180.v:185.5-185.42" + process $proc$ls180.v:185$1608 assign { } { } + assign $1\libresocsim_converter2_counter[0:0] 1'0 + sync always + sync init + update \libresocsim_converter2_counter $1\libresocsim_converter2_counter[0:0] + end + attribute \src "ls180.v:187.12-187.48" + process $proc$ls180.v:187$1609 assign { } { } + assign $1\libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \libresocsim_converter2_dat_r $1\libresocsim_converter2_dat_r[63:0] + end + attribute \src "ls180.v:1884.1-1914.4" + process $proc$ls180.v:1884$94 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 + assign $0\sdram_cmd_last[0:0] 1'0 + assign $0\sdram_sequencer_start0[0:0] 1'0 assign { } { } - assign $0\main_sdphy_cmdw_done[0:0] 1'0 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:4633.2-4698.9" - switch \builder_sdphy_sdphycmdw_state + assign $0\sdram_cmd_valid[0:0] 1'0 + assign $0\subfragments_refresher_next_state[1:0] \subfragments_refresher_state + attribute \src "ls180.v:1890.2-1913.9" + switch \subfragments_refresher_state attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - attribute \src "ls180.v:4637.4-4662.11" - switch \main_sdphy_cmdw_count - attribute \src "ls180.v:0.0-0.0" - case 8'00000000 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [7] - attribute \src "ls180.v:0.0-0.0" - case 8'00000001 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [6] - attribute \src "ls180.v:0.0-0.0" - case 8'00000010 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [5] - attribute \src "ls180.v:0.0-0.0" - case 8'00000011 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [4] - attribute \src "ls180.v:0.0-0.0" - case 8'00000100 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [3] - attribute \src "ls180.v:0.0-0.0" - case 8'00000101 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [2] - attribute \src "ls180.v:0.0-0.0" - case 8'00000110 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [1] - attribute \src "ls180.v:0.0-0.0" - case 8'00000111 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] - case - end - attribute \src "ls180.v:4663.4-4674.7" - switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4663.8-4663.38" + assign $0\sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:1893.4-1896.7" + switch \sdram_cmd_ready + attribute \src "ls180.v:1893.8-1893.23" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4664$796_Y - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4666.5-4673.8" - switch $eq$ls180.v:4666$797_Y - attribute \src "ls180.v:4666.9-4666.40" - case 1'1 - attribute \src "ls180.v:4667.6-4672.9" - switch \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:4667.10-4667.35" - case 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 - attribute \src "ls180.v:4669.10-4669.14" - case - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - end - case - end + assign $0\sdram_sequencer_start0[0:0] 1'1 + assign $0\subfragments_refresher_next_state[1:0] 2'10 case end attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4680.4-4687.7" - switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4680.8-4680.38" + assign $0\sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:1900.4-1904.7" + switch \sdram_sequencer_done0 + attribute \src "ls180.v:1900.8-1900.29" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4681$798_Y - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4683.5-4686.8" - switch $eq$ls180.v:4683$799_Y - attribute \src "ls180.v:4683.9-4683.40" - case 1'1 - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - case - end + assign $0\sdram_cmd_valid[0:0] 1'0 + assign $0\sdram_cmd_last[0:0] 1'1 + assign $0\subfragments_refresher_next_state[1:0] 2'00 case end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4692.4-4696.7" - switch $and$ls180.v:4692$800_Y - attribute \src "ls180.v:4692.8-4692.69" + attribute \src "ls180.v:1907.4-1911.7" + switch 1'1 + attribute \src "ls180.v:1907.8-1907.12" case 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 - attribute \src "ls180.v:4694.8-4694.12" + attribute \src "ls180.v:1908.5-1910.8" + switch \sdram_wants_refresh + attribute \src "ls180.v:1908.9-1908.28" + case 1'1 + assign $0\subfragments_refresher_next_state[1:0] 2'01 + case + end case - assign $0\main_sdphy_cmdw_done[0:0] 1'1 end end sync always - update \main_sdphy_cmdw_pads_out_payload_clk $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - update \main_sdphy_cmdw_pads_out_payload_cmd_o $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - update \main_sdphy_cmdw_pads_out_payload_cmd_oe $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_cmdw_sink_ready $0\main_sdphy_cmdw_sink_ready[0:0] - update \main_sdphy_cmdw_done $0\main_sdphy_cmdw_done[0:0] - update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - end - attribute \src "ls180.v:463.5-463.35" - process $proc$ls180.v:463$3242 - assign { } { } - assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] + update \sdram_cmd_valid $0\sdram_cmd_valid[0:0] + update \sdram_cmd_last $0\sdram_cmd_last[0:0] + update \sdram_sequencer_start0 $0\sdram_sequencer_start0[0:0] + update \subfragments_refresher_next_state $0\subfragments_refresher_next_state[1:0] end - attribute \src "ls180.v:464.5-464.34" - process $proc$ls180.v:464$3243 + attribute \src "ls180.v:1929.1-1936.4" + process $proc$ls180.v:1929$98 assign { } { } - assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:1931.2-1935.5" + switch \sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:1931.6-1931.43" + case 1'1 + assign $0\sdram_bankmachine0_cmd_payload_a[12:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:1933.6-1933.10" + case + assign $0\sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:1934$100_Y + end sync always - sync init - update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] + update \sdram_bankmachine0_cmd_payload_a $0\sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "ls180.v:468.5-468.35" - process $proc$ls180.v:468$3244 + attribute \src "ls180.v:194.5-194.35" + process $proc$ls180.v:194$1610 assign { } { } - assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 + assign $1\libresocsim_ram_bus_ack[0:0] 1'0 sync always - update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] sync init + update \libresocsim_ram_bus_ack $1\libresocsim_ram_bus_ack[0:0] end - attribute \src "ls180.v:470.5-470.39" - process $proc$ls180.v:470$3245 + attribute \src "ls180.v:1940.1-1947.4" + process $proc$ls180.v:1940$107 assign { } { } - assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $0\sdram_bankmachine0_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:1942.2-1946.5" + switch $and$ls180.v:1942$108_Y + attribute \src "ls180.v:1942.6-1942.105" + case 1'1 + attribute \src "ls180.v:1943.3-1945.6" + switch $ne$ls180.v:1943$109_Y + attribute \src "ls180.v:1943.7-1943.133" + case 1'1 + assign $0\sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:1944$110_Y + case + end + case + end sync always - sync init - update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] + update \sdram_bankmachine0_auto_precharge $0\sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:472.5-472.39" - process $proc$ls180.v:472$3246 + attribute \src "ls180.v:1962.1-1969.4" + process $proc$ls180.v:1962$111 assign { } { } - assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:1964.2-1968.5" + switch \sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:1964.6-1964.53" + case 1'1 + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:1965$112_Y + attribute \src "ls180.v:1966.6-1966.10" + case + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine0_cmd_buffer_lookahead_produce + end sync always - sync init - update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] + update \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:4733.1-4826.4" - process $proc$ls180.v:4733$809 + attribute \src "ls180.v:1978.1-2071.4" + process $proc$ls180.v:1978$120 assign { } { } assign { } { } assign { } { } @@ -293725,291 +262708,310 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 - assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 - assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign { } { } - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:4751.2-4825.9" - switch \builder_sdphy_sdphycmdr_state + assign $0\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $0\sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $0\sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign $0\sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\sdram_bankmachine0_row_close[0:0] 1'0 + assign $0\subfragments_bankmachine0_next_state[2:0] \subfragments_bankmachine0_state + attribute \src "ls180.v:1994.2-2070.9" + switch \subfragments_bankmachine0_state attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4759$810_Y - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4756.4-4758.7" - switch \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:4756.8-4756.49" - case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:4761.4-4764.7" - switch $eq$ls180.v:4761$811_Y - attribute \src "ls180.v:4761.8-4761.41" - case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4770$813_Y - assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4787$816_Y - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4772.4-4786.7" - switch $and$ls180.v:4772$814_Y - attribute \src "ls180.v:4772.8-4772.69" + assign $0\sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:1996.4-2004.7" + switch $and$ls180.v:1996$121_Y + attribute \src "ls180.v:1996.8-1996.77" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4774$815_Y - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4776.5-4785.8" - switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:4776.9-4776.36" + assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:1998.5-2000.8" + switch \sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:1998.9-1998.37" case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4778.6-4784.9" - switch \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:4778.10-4778.35" - case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 - attribute \src "ls180.v:4782.10-4782.14" - case - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - end + assign $0\subfragments_bankmachine0_next_state[2:0] 3'101 case end case end - attribute \src "ls180.v:4789.4-4792.7" - switch $eq$ls180.v:4789$817_Y - attribute \src "ls180.v:4789.8-4789.41" + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:2008.4-2010.7" + switch $and$ls180.v:2008$122_Y + attribute \src "ls180.v:2008.8-2008.77" case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + assign $0\subfragments_bankmachine0_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4798.4-4804.7" - switch \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:4798.8-4798.38" + attribute \src "ls180.v:2014.4-2023.7" + switch \sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:2014.8-2014.39" case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4799$818_Y - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4801.5-4803.8" - switch $eq$ls180.v:4801$819_Y - attribute \src "ls180.v:4801.9-4801.40" + assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 + assign $0\sdram_bankmachine0_row_open[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:2019.5-2021.8" + switch \sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:2019.9-2019.37" case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + assign $0\subfragments_bankmachine0_next_state[2:0] 3'110 case end case end attribute \src "ls180.v:0.0-0.0" case 3'100 - assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 - assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 - attribute \src "ls180.v:4810.4-4812.7" - switch $and$ls180.v:4810$820_Y - attribute \src "ls180.v:4810.8-4810.69" + assign $0\sdram_bankmachine0_row_close[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2026.4-2028.7" + switch \sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:2026.8-2026.40" + case 1'1 + assign $0\sdram_bankmachine0_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:2031.4-2033.7" + switch $not$ls180.v:2031$123_Y + attribute \src "ls180.v:2031.8-2031.41" case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + assign $0\subfragments_bankmachine0_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\subfragments_bankmachine0_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\subfragments_bankmachine0_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4819.4-4823.7" - switch $and$ls180.v:4819$822_Y - attribute \src "ls180.v:4819.8-4819.94" + attribute \src "ls180.v:2042.4-2068.7" + switch \sdram_bankmachine0_refresh_req + attribute \src "ls180.v:2042.8-2042.38" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 + assign $0\subfragments_bankmachine0_next_state[2:0] 3'100 + attribute \src "ls180.v:2044.8-2044.12" case + attribute \src "ls180.v:2045.5-2067.8" + switch \sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:2045.9-2045.51" + case 1'1 + attribute \src "ls180.v:2046.6-2066.9" + switch \sdram_bankmachine0_row_opened + attribute \src "ls180.v:2046.10-2046.39" + case 1'1 + attribute \src "ls180.v:2047.7-2063.10" + switch \sdram_bankmachine0_row_hit + attribute \src "ls180.v:2047.11-2047.37" + case 1'1 + assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:2049.8-2056.11" + switch \sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:2049.12-2049.59" + case 1'1 + assign $0\sdram_bankmachine0_req_wdata_ready[0:0] \sdram_bankmachine0_cmd_ready + assign $0\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:2053.12-2053.16" + case + assign $0\sdram_bankmachine0_req_rdata_valid[0:0] \sdram_bankmachine0_cmd_ready + assign $0\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:2058.8-2060.11" + switch $and$ls180.v:2058$124_Y + attribute \src "ls180.v:2058.12-2058.78" + case 1'1 + assign $0\subfragments_bankmachine0_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:2061.11-2061.15" + case + assign $0\subfragments_bankmachine0_next_state[2:0] 3'001 + end + attribute \src "ls180.v:2064.10-2064.14" + case + assign $0\subfragments_bankmachine0_next_state[2:0] 3'011 + end + case + end end end sync always - update \main_sdphy_cmdr_pads_out_payload_clk $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - update \main_sdphy_cmdr_pads_out_payload_cmd_o $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - update \main_sdphy_cmdr_pads_out_payload_cmd_oe $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_cmdr_sink_ready $0\main_sdphy_cmdr_sink_ready[0:0] - update \main_sdphy_cmdr_source_valid $0\main_sdphy_cmdr_source_valid[0:0] - update \main_sdphy_cmdr_source_last $0\main_sdphy_cmdr_source_last[0:0] - update \main_sdphy_cmdr_source_payload_data $0\main_sdphy_cmdr_source_payload_data[7:0] - update \main_sdphy_cmdr_source_payload_status $0\main_sdphy_cmdr_source_payload_status[2:0] - update \main_sdphy_cmdr_cmdr_source_source_ready0 $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + update \sdram_bankmachine0_req_wdata_ready $0\sdram_bankmachine0_req_wdata_ready[0:0] + update \sdram_bankmachine0_req_rdata_valid $0\sdram_bankmachine0_req_rdata_valid[0:0] + update \sdram_bankmachine0_refresh_gnt $0\sdram_bankmachine0_refresh_gnt[0:0] + update \sdram_bankmachine0_cmd_valid $0\sdram_bankmachine0_cmd_valid[0:0] + update \sdram_bankmachine0_cmd_payload_cas $0\sdram_bankmachine0_cmd_payload_cas[0:0] + update \sdram_bankmachine0_cmd_payload_ras $0\sdram_bankmachine0_cmd_payload_ras[0:0] + update \sdram_bankmachine0_cmd_payload_we $0\sdram_bankmachine0_cmd_payload_we[0:0] + update \sdram_bankmachine0_cmd_payload_is_cmd $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \sdram_bankmachine0_cmd_payload_is_read $0\sdram_bankmachine0_cmd_payload_is_read[0:0] + update \sdram_bankmachine0_cmd_payload_is_write $0\sdram_bankmachine0_cmd_payload_is_write[0:0] + update \sdram_bankmachine0_row_open $0\sdram_bankmachine0_row_open[0:0] + update \sdram_bankmachine0_row_close $0\sdram_bankmachine0_row_close[0:0] + update \sdram_bankmachine0_row_col_n_addr_sel $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \subfragments_bankmachine0_next_state $0\subfragments_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:475.5-475.32" - process $proc$ls180.v:475$3247 + attribute \src "ls180.v:198.5-198.35" + process $proc$ls180.v:198$1611 assign { } { } - assign $1\main_sdram_cmd_valid[0:0] 1'0 + assign $0\libresocsim_ram_bus_err[0:0] 1'0 sync always + update \libresocsim_ram_bus_err $0\libresocsim_ram_bus_err[0:0] sync init - update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] end - attribute \src "ls180.v:476.5-476.32" - process $proc$ls180.v:476$3248 + attribute \src "ls180.v:201.11-201.32" + process $proc$ls180.v:201$1612 assign { } { } - assign $1\main_sdram_cmd_ready[0:0] 1'0 + assign $1\libresocsim_we[3:0] 4'0000 sync always sync init - update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] + update \libresocsim_we $1\libresocsim_we[3:0] end - attribute \src "ls180.v:477.5-477.31" - process $proc$ls180.v:477$3249 + attribute \src "ls180.v:203.12-203.44" + process $proc$ls180.v:203$1613 assign { } { } - assign $1\main_sdram_cmd_last[0:0] 1'0 + assign $1\libresocsim_load_storage[31:0] 0 sync always sync init - update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] + update \libresocsim_load_storage $1\libresocsim_load_storage[31:0] end - attribute \src "ls180.v:478.12-478.44" - process $proc$ls180.v:478$3250 + attribute \src "ls180.v:204.5-204.31" + process $proc$ls180.v:204$1614 assign { } { } - assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $1\libresocsim_load_re[0:0] 1'0 sync always sync init - update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] + update \libresocsim_load_re $1\libresocsim_load_re[0:0] end - attribute \src "ls180.v:479.11-479.43" - process $proc$ls180.v:479$3251 + attribute \src "ls180.v:205.12-205.46" + process $proc$ls180.v:205$1615 assign { } { } - assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $1\libresocsim_reload_storage[31:0] 0 sync always sync init - update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] + update \libresocsim_reload_storage $1\libresocsim_reload_storage[31:0] end - attribute \src "ls180.v:480.5-480.38" - process $proc$ls180.v:480$3252 + attribute \src "ls180.v:206.5-206.33" + process $proc$ls180.v:206$1616 assign { } { } - assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $1\libresocsim_reload_re[0:0] 1'0 sync always sync init - update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] + update \libresocsim_reload_re $1\libresocsim_reload_re[0:0] end - attribute \src "ls180.v:481.5-481.38" - process $proc$ls180.v:481$3253 + attribute \src "ls180.v:207.5-207.34" + process $proc$ls180.v:207$1617 assign { } { } - assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $1\libresocsim_en_storage[0:0] 1'0 sync always sync init - update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] + update \libresocsim_en_storage $1\libresocsim_en_storage[0:0] end - attribute \src "ls180.v:482.5-482.37" - process $proc$ls180.v:482$3254 + attribute \src "ls180.v:208.5-208.29" + process $proc$ls180.v:208$1618 assign { } { } - assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + assign $1\libresocsim_en_re[0:0] 1'0 sync always sync init - update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + update \libresocsim_en_re $1\libresocsim_en_re[0:0] end - attribute \src "ls180.v:483.5-483.42" - process $proc$ls180.v:483$3255 + attribute \src "ls180.v:2086.1-2093.4" + process $proc$ls180.v:2086$128 assign { } { } - assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + assign $0\sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:2088.2-2092.5" + switch \sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:2088.6-2088.43" + case 1'1 + assign $0\sdram_bankmachine1_cmd_payload_a[12:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:2090.6-2090.10" + case + assign $0\sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:2091$130_Y + end sync always - update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] - sync init + update \sdram_bankmachine1_cmd_payload_a $0\sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:484.5-484.43" - process $proc$ls180.v:484$3256 + attribute \src "ls180.v:209.5-209.44" + process $proc$ls180.v:209$1619 assign { } { } - assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + assign $1\libresocsim_update_value_storage[0:0] 1'0 sync always - update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] sync init + update \libresocsim_update_value_storage $1\libresocsim_update_value_storage[0:0] end - attribute \src "ls180.v:4860.1-4887.4" - process $proc$ls180.v:4860$830 - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:2097.1-2104.4" + process $proc$ls180.v:2097$137 assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_dataw_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_error[0:0] 1'0 - assign { } { } - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:4868.2-4886.9" - switch \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:0.0-0.0" + assign $0\sdram_bankmachine1_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:2099.2-2103.5" + switch $and$ls180.v:2099$138_Y + attribute \src "ls180.v:2099.6-2099.105" case 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 - attribute \src "ls180.v:4873.4-4877.7" - switch \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:4873.8-4873.50" + attribute \src "ls180.v:2100.3-2102.6" + switch $ne$ls180.v:2100$139_Y + attribute \src "ls180.v:2100.7-2100.133" case 1'1 - assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4874$831_Y - assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4875$832_Y - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + assign $0\sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:2101$140_Y case end - attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:4880.4-4884.7" - switch \main_sdphy_dataw_start - attribute \src "ls180.v:4880.8-4880.30" - case 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 - case - end end sync always - update \main_sdphy_dataw_valid $0\main_sdphy_dataw_valid[0:0] - update \main_sdphy_dataw_error $0\main_sdphy_dataw_error[0:0] - update \main_sdphy_dataw_crcr_source_source_ready0 $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + update \sdram_bankmachine1_auto_precharge $0\sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:210.5-210.39" + process $proc$ls180.v:210$1620 + assign { } { } + assign $1\libresocsim_update_value_re[0:0] 1'0 + sync always + sync init + update \libresocsim_update_value_re $1\libresocsim_update_value_re[0:0] + end + attribute \src "ls180.v:211.12-211.44" + process $proc$ls180.v:211$1621 + assign { } { } + assign $1\libresocsim_value_status[31:0] 0 + sync always + sync init + update \libresocsim_value_status $1\libresocsim_value_status[31:0] + end + attribute \src "ls180.v:2119.1-2126.4" + process $proc$ls180.v:2119$141 + assign { } { } + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:2121.2-2125.5" + switch \sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:2121.6-2121.53" + case 1'1 + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2122$142_Y + attribute \src "ls180.v:2123.6-2123.10" + case + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine1_cmd_buffer_lookahead_produce + end + sync always + update \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:4888.1-4960.4" - process $proc$ls180.v:4888$833 + attribute \src "ls180.v:2135.1-2228.4" + process $proc$ls180.v:2135$150 + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -294019,182 +263021,272 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 assign { } { } - assign $0\main_sdphy_dataw_start[0:0] 1'0 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_dataw_stop[0:0] 1'0 - assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state - attribute \src "ls180.v:4899.2-4959.9" - switch \builder_sdphy_fsm_state + assign { } { } + assign { } { } + assign $0\sdram_bankmachine1_row_open[0:0] 1'0 + assign $0\sdram_bankmachine1_row_close[0:0] 1'0 + assign $0\sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $0\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $0\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $0\sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign $0\sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign { } { } + assign $0\sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $0\subfragments_bankmachine1_next_state[2:0] \subfragments_bankmachine1_state + attribute \src "ls180.v:2151.2-2227.9" + switch \subfragments_bankmachine1_state attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - attribute \src "ls180.v:4904.4-4906.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4904.8-4904.39" + assign $0\sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:2153.4-2161.7" + switch $and$ls180.v:2153$151_Y + attribute \src "ls180.v:2153.8-2153.77" case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 + assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2155.5-2157.8" + switch \sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:2155.9-2155.37" + case 1'1 + assign $0\subfragments_bankmachine1_next_state[2:0] 3'101 + case + end case end attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4909$834_Y - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - attribute \src "ls180.v:4912.4-4919.11" - switch \main_sdphy_dataw_count - attribute \src "ls180.v:0.0-0.0" - case 8'00000000 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [7:4] - attribute \src "ls180.v:0.0-0.0" - case 8'00000001 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] + assign $0\sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:2165.4-2167.7" + switch $and$ls180.v:2165$152_Y + attribute \src "ls180.v:2165.8-2165.77" + case 1'1 + assign $0\subfragments_bankmachine1_next_state[2:0] 3'101 case end - attribute \src "ls180.v:4920.4-4932.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4920.8-4920.39" + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:2171.4-2180.7" + switch \sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:2171.8-2171.39" case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4921$835_Y - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4923.5-4931.8" - switch $eq$ls180.v:4923$836_Y - attribute \src "ls180.v:4923.9-4923.41" + assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 + assign $0\sdram_bankmachine1_row_open[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:2176.5-2178.8" + switch \sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:2176.9-2176.37" case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4926.6-4930.9" - switch \main_sdphy_dataw_sink_last - attribute \src "ls180.v:4926.10-4926.36" - case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:4928.10-4928.14" - case - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 - end + assign $0\subfragments_bankmachine1_next_state[2:0] 3'110 case end case end attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4938.4-4941.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4938.8-4938.39" + case 3'100 + assign $0\sdram_bankmachine1_row_close[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2183.4-2185.7" + switch \sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:2183.8-2183.40" case 1'1 - assign $0\main_sdphy_dataw_start[0:0] 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 + assign $0\sdram_bankmachine1_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4945.4-4950.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4945.8-4945.39" + attribute \src "ls180.v:2188.4-2190.7" + switch $not$ls180.v:2188$153_Y + attribute \src "ls180.v:2188.8-2188.41" case 1'1 - attribute \src "ls180.v:4946.5-4949.8" - switch \main_sdphy_dataw_pads_in_payload_data_i [0] - attribute \src "ls180.v:4946.9-4946.51" - case 1'1 - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 - case - end + assign $0\subfragments_bankmachine1_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\subfragments_bankmachine1_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\subfragments_bankmachine1_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4955.4-4957.7" - switch $and$ls180.v:4955$837_Y - attribute \src "ls180.v:4955.8-4955.71" + attribute \src "ls180.v:2199.4-2225.7" + switch \sdram_bankmachine1_refresh_req + attribute \src "ls180.v:2199.8-2199.38" case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 + assign $0\subfragments_bankmachine1_next_state[2:0] 3'100 + attribute \src "ls180.v:2201.8-2201.12" case + attribute \src "ls180.v:2202.5-2224.8" + switch \sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:2202.9-2202.51" + case 1'1 + attribute \src "ls180.v:2203.6-2223.9" + switch \sdram_bankmachine1_row_opened + attribute \src "ls180.v:2203.10-2203.39" + case 1'1 + attribute \src "ls180.v:2204.7-2220.10" + switch \sdram_bankmachine1_row_hit + attribute \src "ls180.v:2204.11-2204.37" + case 1'1 + assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:2206.8-2213.11" + switch \sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:2206.12-2206.59" + case 1'1 + assign $0\sdram_bankmachine1_req_wdata_ready[0:0] \sdram_bankmachine1_cmd_ready + assign $0\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:2210.12-2210.16" + case + assign $0\sdram_bankmachine1_req_rdata_valid[0:0] \sdram_bankmachine1_cmd_ready + assign $0\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:2215.8-2217.11" + switch $and$ls180.v:2215$154_Y + attribute \src "ls180.v:2215.12-2215.78" + case 1'1 + assign $0\subfragments_bankmachine1_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:2218.11-2218.15" + case + assign $0\subfragments_bankmachine1_next_state[2:0] 3'001 + end + attribute \src "ls180.v:2221.10-2221.14" + case + assign $0\subfragments_bankmachine1_next_state[2:0] 3'011 + end + case + end end end sync always - update \main_sdphy_dataw_pads_out_payload_clk $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - update \main_sdphy_dataw_pads_out_payload_data_o $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - update \main_sdphy_dataw_pads_out_payload_data_oe $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - update \main_sdphy_dataw_sink_ready $0\main_sdphy_dataw_sink_ready[0:0] - update \main_sdphy_dataw_stop $0\main_sdphy_dataw_stop[0:0] - update \main_sdphy_dataw_start $0\main_sdphy_dataw_start[0:0] - update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] - update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + update \sdram_bankmachine1_req_wdata_ready $0\sdram_bankmachine1_req_wdata_ready[0:0] + update \sdram_bankmachine1_req_rdata_valid $0\sdram_bankmachine1_req_rdata_valid[0:0] + update \sdram_bankmachine1_refresh_gnt $0\sdram_bankmachine1_refresh_gnt[0:0] + update \sdram_bankmachine1_cmd_valid $0\sdram_bankmachine1_cmd_valid[0:0] + update \sdram_bankmachine1_cmd_payload_cas $0\sdram_bankmachine1_cmd_payload_cas[0:0] + update \sdram_bankmachine1_cmd_payload_ras $0\sdram_bankmachine1_cmd_payload_ras[0:0] + update \sdram_bankmachine1_cmd_payload_we $0\sdram_bankmachine1_cmd_payload_we[0:0] + update \sdram_bankmachine1_cmd_payload_is_cmd $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \sdram_bankmachine1_cmd_payload_is_read $0\sdram_bankmachine1_cmd_payload_is_read[0:0] + update \sdram_bankmachine1_cmd_payload_is_write $0\sdram_bankmachine1_cmd_payload_is_write[0:0] + update \sdram_bankmachine1_row_open $0\sdram_bankmachine1_row_open[0:0] + update \sdram_bankmachine1_row_close $0\sdram_bankmachine1_row_close[0:0] + update \sdram_bankmachine1_row_col_n_addr_sel $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] + update \subfragments_bankmachine1_next_state $0\subfragments_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:490.11-490.44" - process $proc$ls180.v:490$3257 + attribute \src "ls180.v:215.5-215.36" + process $proc$ls180.v:215$1622 assign { } { } - assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + assign $1\libresocsim_zero_pending[0:0] 1'0 sync always sync init - update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + update \libresocsim_zero_pending $1\libresocsim_zero_pending[0:0] end - attribute \src "ls180.v:492.5-492.38" - process $proc$ls180.v:492$3258 + attribute \src "ls180.v:217.5-217.34" + process $proc$ls180.v:217$1623 assign { } { } - assign $1\main_sdram_postponer_req_o[0:0] 1'0 + assign $1\libresocsim_zero_clear[0:0] 1'0 sync always sync init - update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + update \libresocsim_zero_clear $1\libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:493.5-493.38" - process $proc$ls180.v:493$3259 + attribute \src "ls180.v:218.5-218.40" + process $proc$ls180.v:218$1624 assign { } { } - assign $1\main_sdram_postponer_count[0:0] 1'0 + assign $1\libresocsim_zero_old_trigger[0:0] 1'0 sync always sync init - update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + update \libresocsim_zero_old_trigger $1\libresocsim_zero_old_trigger[0:0] end - attribute \src "ls180.v:494.5-494.39" - process $proc$ls180.v:494$3260 + attribute \src "ls180.v:2243.1-2250.4" + process $proc$ls180.v:2243$158 assign { } { } - assign $1\main_sdram_sequencer_start0[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:2245.2-2249.5" + switch \sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:2245.6-2245.43" + case 1'1 + assign $0\sdram_bankmachine2_cmd_payload_a[12:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:2247.6-2247.10" + case + assign $0\sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:2248$160_Y + end sync always - sync init - update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] + update \sdram_bankmachine2_cmd_payload_a $0\sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:2254.1-2261.4" + process $proc$ls180.v:2254$167 + assign { } { } + assign $0\sdram_bankmachine2_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:2256.2-2260.5" + switch $and$ls180.v:2256$168_Y + attribute \src "ls180.v:2256.6-2256.105" + case 1'1 + attribute \src "ls180.v:2257.3-2259.6" + switch $ne$ls180.v:2257$169_Y + attribute \src "ls180.v:2257.7-2257.133" + case 1'1 + assign $0\sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:2258$170_Y + case + end + case + end + sync always + update \sdram_bankmachine2_auto_precharge $0\sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:497.5-497.38" - process $proc$ls180.v:497$3261 + attribute \src "ls180.v:227.5-227.44" + process $proc$ls180.v:227$1625 assign { } { } - assign $1\main_sdram_sequencer_done1[0:0] 1'0 + assign $1\libresocsim_eventmanager_storage[0:0] 1'0 sync always sync init - update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + update \libresocsim_eventmanager_storage $1\libresocsim_eventmanager_storage[0:0] end - attribute \src "ls180.v:498.11-498.46" - process $proc$ls180.v:498$3262 + attribute \src "ls180.v:2276.1-2283.4" + process $proc$ls180.v:2276$171 assign { } { } - assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:2278.2-2282.5" + switch \sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:2278.6-2278.53" + case 1'1 + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2279$172_Y + attribute \src "ls180.v:2280.6-2280.10" + case + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine2_cmd_buffer_lookahead_produce + end sync always - sync init - update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + update \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:499.5-499.38" - process $proc$ls180.v:499$3263 + attribute \src "ls180.v:228.5-228.39" + process $proc$ls180.v:228$1626 assign { } { } - assign $1\main_sdram_sequencer_count[0:0] 1'0 + assign $1\libresocsim_eventmanager_re[0:0] 1'0 sync always sync init - update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + update \libresocsim_eventmanager_re $1\libresocsim_eventmanager_re[0:0] end - attribute \src "ls180.v:4994.1-5095.4" - process $proc$ls180.v:4994$845 + attribute \src "ls180.v:229.12-229.37" + process $proc$ls180.v:229$1627 assign { } { } + assign $1\libresocsim_value[31:0] 0 + sync always + sync init + update \libresocsim_value $1\libresocsim_value[31:0] + end + attribute \src "ls180.v:2292.1-2385.4" + process $proc$ls180.v:2292$180 assign { } { } assign { } { } assign { } { } @@ -294209,358 +263301,245 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_datar_stop[0:0] 1'0 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 + assign $0\sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign $0\sdram_bankmachine2_row_open[0:0] 1'0 + assign $0\sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 assign { } { } - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - assign $0\main_sdphy_datar_source_valid[0:0] 1'0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_datar_source_last[0:0] 1'0 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:5011.2-5094.9" - switch \builder_sdphy_sdphydatar_state + assign $0\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $0\subfragments_bankmachine2_next_state[2:0] \subfragments_bankmachine2_state + attribute \src "ls180.v:2308.2-2384.9" + switch \subfragments_bankmachine2_state attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 - assign { } { } - assign { } { } - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5021$847_Y - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:5018.4-5020.7" - switch \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:5018.8-5018.51" - case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:5023.4-5026.7" - switch $eq$ls180.v:5023$848_Y - attribute \src "ls180.v:5023.8-5023.42" + assign $0\sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:2310.4-2318.7" + switch $and$ls180.v:2310$181_Y + attribute \src "ls180.v:2310.8-2310.77" case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:5032$851_Y - assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5053$853_Y - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:5034.4-5052.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5034.8-5034.37" - case 1'1 - attribute \src "ls180.v:5035.5-5051.8" - switch \main_sdphy_datar_source_ready - attribute \src "ls180.v:5035.9-5035.38" + assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2312.5-2314.8" + switch \sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:2312.9-2312.37" case 1'1 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5037$852_Y - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5039.6-5048.9" - switch \main_sdphy_datar_source_last - attribute \src "ls180.v:5039.10-5039.38" - case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5041.7-5047.10" - switch \main_sdphy_datar_sink_last - attribute \src "ls180.v:5041.11-5041.37" - case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 - attribute \src "ls180.v:5045.11-5045.15" - case - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - end - case - end - attribute \src "ls180.v:5049.9-5049.13" + assign $0\subfragments_bankmachine2_next_state[2:0] 3'101 case - assign $0\main_sdphy_datar_stop[0:0] 1'1 end case end - attribute \src "ls180.v:5055.4-5058.7" - switch $eq$ls180.v:5055$854_Y - attribute \src "ls180.v:5055.8-5055.42" + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:2322.4-2324.7" + switch $and$ls180.v:2322$182_Y + attribute \src "ls180.v:2322.8-2322.77" case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + assign $0\subfragments_bankmachine2_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:5062.4-5068.7" - switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:5062.8-5062.39" + attribute \src "ls180.v:2328.4-2337.7" + switch \sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:2328.8-2328.39" case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5063$855_Y - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5065.5-5067.8" - switch $eq$ls180.v:5065$856_Y - attribute \src "ls180.v:5065.9-5065.42" + assign $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 + assign $0\sdram_bankmachine2_row_open[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:2333.5-2335.8" + switch \sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:2333.9-2333.37" case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + assign $0\subfragments_bankmachine2_next_state[2:0] 3'110 case end case end attribute \src "ls180.v:0.0-0.0" case 3'100 - assign $0\main_sdphy_datar_source_valid[0:0] 1'1 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 - assign $0\main_sdphy_datar_source_last[0:0] 1'1 - attribute \src "ls180.v:5074.4-5076.7" - switch $and$ls180.v:5074$857_Y - attribute \src "ls180.v:5074.8-5074.71" + assign $0\sdram_bankmachine2_row_close[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2340.4-2342.7" + switch \sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:2340.8-2340.40" + case 1'1 + assign $0\sdram_bankmachine2_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:2345.4-2347.7" + switch $not$ls180.v:2345$183_Y + attribute \src "ls180.v:2345.8-2345.41" case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + assign $0\subfragments_bankmachine2_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\subfragments_bankmachine2_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\subfragments_bankmachine2_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5081.4-5092.7" - switch $and$ls180.v:5081$858_Y - attribute \src "ls180.v:5081.8-5081.71" + attribute \src "ls180.v:2356.4-2382.7" + switch \sdram_bankmachine2_refresh_req + attribute \src "ls180.v:2356.8-2356.38" case 1'1 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:5083.5-5091.8" - switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:5083.9-5083.40" + assign $0\subfragments_bankmachine2_next_state[2:0] 3'100 + attribute \src "ls180.v:2358.8-2358.12" + case + attribute \src "ls180.v:2359.5-2381.8" + switch \sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:2359.9-2359.51" case 1'1 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 + attribute \src "ls180.v:2360.6-2380.9" + switch \sdram_bankmachine2_row_opened + attribute \src "ls180.v:2360.10-2360.39" + case 1'1 + attribute \src "ls180.v:2361.7-2377.10" + switch \sdram_bankmachine2_row_hit + attribute \src "ls180.v:2361.11-2361.37" + case 1'1 + assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:2363.8-2370.11" + switch \sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:2363.12-2363.59" + case 1'1 + assign $0\sdram_bankmachine2_req_wdata_ready[0:0] \sdram_bankmachine2_cmd_ready + assign $0\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:2367.12-2367.16" + case + assign $0\sdram_bankmachine2_req_rdata_valid[0:0] \sdram_bankmachine2_cmd_ready + assign $0\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:2372.8-2374.11" + switch $and$ls180.v:2372$184_Y + attribute \src "ls180.v:2372.12-2372.78" + case 1'1 + assign $0\subfragments_bankmachine2_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:2375.11-2375.15" + case + assign $0\subfragments_bankmachine2_next_state[2:0] 3'001 + end + attribute \src "ls180.v:2378.10-2378.14" + case + assign $0\subfragments_bankmachine2_next_state[2:0] 3'011 + end case end - case end end sync always - update \main_sdphy_datar_pads_out_payload_clk $0\main_sdphy_datar_pads_out_payload_clk[0:0] - update \main_sdphy_datar_sink_ready $0\main_sdphy_datar_sink_ready[0:0] - update \main_sdphy_datar_source_valid $0\main_sdphy_datar_source_valid[0:0] - update \main_sdphy_datar_source_last $0\main_sdphy_datar_source_last[0:0] - update \main_sdphy_datar_source_payload_data $0\main_sdphy_datar_source_payload_data[7:0] - update \main_sdphy_datar_source_payload_status $0\main_sdphy_datar_source_payload_status[2:0] - update \main_sdphy_datar_stop $0\main_sdphy_datar_stop[0:0] - update \main_sdphy_datar_datar_source_source_ready0 $0\main_sdphy_datar_datar_source_source_ready0[0:0] - update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - end - attribute \src "ls180.v:505.5-505.51" - process $proc$ls180.v:505$3264 - assign { } { } - assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - end - attribute \src "ls180.v:506.5-506.51" - process $proc$ls180.v:506$3265 - assign { } { } - assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - end - attribute \src "ls180.v:508.5-508.47" - process $proc$ls180.v:508$3266 - assign { } { } - assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] - end - attribute \src "ls180.v:509.5-509.45" - process $proc$ls180.v:509$3267 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] - end - attribute \src "ls180.v:510.5-510.45" - process $proc$ls180.v:510$3268 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] - end - attribute \src "ls180.v:511.12-511.57" - process $proc$ls180.v:511$3269 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - end - attribute \src "ls180.v:513.5-513.51" - process $proc$ls180.v:513$3270 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:514.5-514.51" - process $proc$ls180.v:514$3271 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:515.5-515.50" - process $proc$ls180.v:515$3272 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - end - attribute \src "ls180.v:5153.1-5160.4" - process $proc$ls180.v:5153$980 - assign { } { } - assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - attribute \src "ls180.v:5155.2-5159.5" - switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:5155.6-5155.38" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:5157.6-5157.10" - case - assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 - end - sync always - update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] + update \sdram_bankmachine2_req_wdata_ready $0\sdram_bankmachine2_req_wdata_ready[0:0] + update \sdram_bankmachine2_req_rdata_valid $0\sdram_bankmachine2_req_rdata_valid[0:0] + update \sdram_bankmachine2_refresh_gnt $0\sdram_bankmachine2_refresh_gnt[0:0] + update \sdram_bankmachine2_cmd_valid $0\sdram_bankmachine2_cmd_valid[0:0] + update \sdram_bankmachine2_cmd_payload_cas $0\sdram_bankmachine2_cmd_payload_cas[0:0] + update \sdram_bankmachine2_cmd_payload_ras $0\sdram_bankmachine2_cmd_payload_ras[0:0] + update \sdram_bankmachine2_cmd_payload_we $0\sdram_bankmachine2_cmd_payload_we[0:0] + update \sdram_bankmachine2_cmd_payload_is_cmd $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] + update \sdram_bankmachine2_cmd_payload_is_read $0\sdram_bankmachine2_cmd_payload_is_read[0:0] + update \sdram_bankmachine2_cmd_payload_is_write $0\sdram_bankmachine2_cmd_payload_is_write[0:0] + update \sdram_bankmachine2_row_open $0\sdram_bankmachine2_row_open[0:0] + update \sdram_bankmachine2_row_close $0\sdram_bankmachine2_row_close[0:0] + update \sdram_bankmachine2_row_col_n_addr_sel $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \subfragments_bankmachine2_next_state $0\subfragments_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:516.5-516.54" - process $proc$ls180.v:516$3273 + attribute \src "ls180.v:236.5-236.31" + process $proc$ls180.v:236$1628 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $1\ram_bus_ram_bus_ack[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \ram_bus_ram_bus_ack $1\ram_bus_ram_bus_ack[0:0] end - attribute \src "ls180.v:517.5-517.55" - process $proc$ls180.v:517$3274 + attribute \src "ls180.v:240.5-240.31" + process $proc$ls180.v:240$1629 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $0\ram_bus_ram_bus_err[0:0] 1'0 sync always + update \ram_bus_ram_bus_err $0\ram_bus_ram_bus_err[0:0] sync init - update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:5175.1-5182.4" - process $proc$ls180.v:5175$1003 + attribute \src "ls180.v:2400.1-2407.4" + process $proc$ls180.v:2400$188 assign { } { } - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5177.2-5181.5" - switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:5177.6-5177.44" + assign $0\sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:2402.2-2406.5" + switch \sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:2402.6-2402.43" case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:5179.6-5179.10" + assign $0\sdram_bankmachine3_cmd_payload_a[12:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:2404.6-2404.10" case - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + assign $0\sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:2405$190_Y end sync always - update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - end - attribute \src "ls180.v:518.5-518.56" - process $proc$ls180.v:518$3275 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + update \sdram_bankmachine3_cmd_payload_a $0\sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:5185.1-5192.4" - process $proc$ls180.v:5185$1014 + attribute \src "ls180.v:2411.1-2418.4" + process $proc$ls180.v:2411$197 assign { } { } - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5187.2-5191.5" - switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:5187.6-5187.44" + assign $0\sdram_bankmachine3_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:2413.2-2417.5" + switch $and$ls180.v:2413$198_Y + attribute \src "ls180.v:2413.6-2413.105" case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:5189.6-5189.10" + attribute \src "ls180.v:2414.3-2416.6" + switch $ne$ls180.v:2414$199_Y + attribute \src "ls180.v:2414.7-2414.133" + case 1'1 + assign $0\sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:2415$200_Y + case + end case - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 end sync always - update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + update \sdram_bankmachine3_auto_precharge $0\sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "ls180.v:519.5-519.50" - process $proc$ls180.v:519$3276 + attribute \src "ls180.v:243.11-243.24" + process $proc$ls180.v:243$1630 assign { } { } - assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + assign $1\ram_we[3:0] 4'0000 sync always sync init - update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] - end - attribute \src "ls180.v:5195.1-5202.4" - process $proc$ls180.v:5195$1025 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5197.2-5201.5" - switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:5197.6-5197.44" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:5199.6-5199.10" - case - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 - end - sync always - update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + update \ram_we $1\ram_we[3:0] end - attribute \src "ls180.v:5205.1-5212.4" - process $proc$ls180.v:5205$1036 + attribute \src "ls180.v:2433.1-2440.4" + process $proc$ls180.v:2433$201 assign { } { } - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5207.2-5211.5" - switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:5207.6-5207.44" + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:2435.2-2439.5" + switch \sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:2435.6-2435.53" case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:5209.6-5209.10" + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2436$202_Y + attribute \src "ls180.v:2437.6-2437.10" case - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine3_cmd_buffer_lookahead_produce end sync always - update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + update \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:5213.1-5292.4" - process $proc$ls180.v:5213$1037 + attribute \src "ls180.v:2449.1-2542.4" + process $proc$ls180.v:2449$210 assign { } { } assign { } { } assign { } { } @@ -294575,356 +263554,391 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + assign $0\sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $0\sdram_bankmachine3_refresh_gnt[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign $0\sdram_bankmachine3_row_open[0:0] 1'0 assign { } { } - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:5230.2-5291.9" - switch \builder_sdcore_crcupstreaminserter_state + assign $0\sdram_bankmachine3_row_close[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $0\subfragments_bankmachine3_next_state[2:0] \subfragments_bankmachine3_state + attribute \src "ls180.v:2465.2-2541.9" + switch \subfragments_bankmachine3_state attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 - attribute \src "ls180.v:5234.4-5236.7" - switch $eq$ls180.v:5234$1038_Y - attribute \src "ls180.v:5234.8-5234.48" + case 3'001 + assign $0\sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:2467.4-2475.7" + switch $and$ls180.v:2467$211_Y + attribute \src "ls180.v:2467.8-2467.77" case 1'1 - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2469.5-2471.8" + switch \sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:2469.9-2469.37" + case 1'1 + assign $0\subfragments_bankmachine3_next_state[2:0] 3'101 + case + end case end - attribute \src "ls180.v:5237.4-5262.11" - switch \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [15] \main_sdcore_crc16_inserter_crctmp2 [15] \main_sdcore_crc16_inserter_crctmp1 [15] \main_sdcore_crc16_inserter_crctmp0 [15] \main_sdcore_crc16_inserter_crctmp3 [14] \main_sdcore_crc16_inserter_crctmp2 [14] \main_sdcore_crc16_inserter_crctmp1 [14] \main_sdcore_crc16_inserter_crctmp0 [14] } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [13] \main_sdcore_crc16_inserter_crctmp2 [13] \main_sdcore_crc16_inserter_crctmp1 [13] \main_sdcore_crc16_inserter_crctmp0 [13] \main_sdcore_crc16_inserter_crctmp3 [12] \main_sdcore_crc16_inserter_crctmp2 [12] \main_sdcore_crc16_inserter_crctmp1 [12] \main_sdcore_crc16_inserter_crctmp0 [12] } - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [11] \main_sdcore_crc16_inserter_crctmp2 [11] \main_sdcore_crc16_inserter_crctmp1 [11] \main_sdcore_crc16_inserter_crctmp0 [11] \main_sdcore_crc16_inserter_crctmp3 [10] \main_sdcore_crc16_inserter_crctmp2 [10] \main_sdcore_crc16_inserter_crctmp1 [10] \main_sdcore_crc16_inserter_crctmp0 [10] } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [9] \main_sdcore_crc16_inserter_crctmp2 [9] \main_sdcore_crc16_inserter_crctmp1 [9] \main_sdcore_crc16_inserter_crctmp0 [9] \main_sdcore_crc16_inserter_crctmp3 [8] \main_sdcore_crc16_inserter_crctmp2 [8] \main_sdcore_crc16_inserter_crctmp1 [8] \main_sdcore_crc16_inserter_crctmp0 [8] } - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [7] \main_sdcore_crc16_inserter_crctmp2 [7] \main_sdcore_crc16_inserter_crctmp1 [7] \main_sdcore_crc16_inserter_crctmp0 [7] \main_sdcore_crc16_inserter_crctmp3 [6] \main_sdcore_crc16_inserter_crctmp2 [6] \main_sdcore_crc16_inserter_crctmp1 [6] \main_sdcore_crc16_inserter_crctmp0 [6] } - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [5] \main_sdcore_crc16_inserter_crctmp2 [5] \main_sdcore_crc16_inserter_crctmp1 [5] \main_sdcore_crc16_inserter_crctmp0 [5] \main_sdcore_crc16_inserter_crctmp3 [4] \main_sdcore_crc16_inserter_crctmp2 [4] \main_sdcore_crc16_inserter_crctmp1 [4] \main_sdcore_crc16_inserter_crctmp0 [4] } - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [3] \main_sdcore_crc16_inserter_crctmp2 [3] \main_sdcore_crc16_inserter_crctmp1 [3] \main_sdcore_crc16_inserter_crctmp0 [3] \main_sdcore_crc16_inserter_crctmp3 [2] \main_sdcore_crc16_inserter_crctmp2 [2] \main_sdcore_crc16_inserter_crctmp1 [2] \main_sdcore_crc16_inserter_crctmp0 [2] } - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:2479.4-2481.7" + switch $and$ls180.v:2479$212_Y + attribute \src "ls180.v:2479.8-2479.77" + case 1'1 + assign $0\subfragments_bankmachine3_next_state[2:0] 3'101 case end - attribute \src "ls180.v:5263.4-5270.7" - switch \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:5263.8-5263.47" + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:2485.4-2494.7" + switch \sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:2485.8-2485.39" case 1'1 - attribute \src "ls180.v:5264.5-5269.8" - switch $eq$ls180.v:5264$1039_Y - attribute \src "ls180.v:5264.9-5264.49" + assign $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 + assign $0\sdram_bankmachine3_row_open[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:2490.5-2492.8" + switch \sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:2490.9-2490.37" case 1'1 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - attribute \src "ls180.v:5266.9-5266.13" + assign $0\subfragments_bankmachine3_next_state[2:0] 3'110 case - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5267$1040_Y - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 end case end attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\sdram_bankmachine3_row_close[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2497.4-2499.7" + switch \sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:2497.8-2497.40" + case 1'1 + assign $0\sdram_bankmachine3_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:2502.4-2504.7" + switch $not$ls180.v:2502$213_Y + attribute \src "ls180.v:2502.8-2502.41" + case 1'1 + assign $0\subfragments_bankmachine3_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\subfragments_bankmachine3_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\subfragments_bankmachine3_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] \main_sdcore_crc16_inserter_sink_payload_data - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] \main_sdcore_crc16_inserter_sink_valid - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] \main_sdcore_crc16_inserter_source_ready - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \main_sdcore_crc16_inserter_crc0_crc - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \main_sdcore_crc16_inserter_crc1_crc - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \main_sdcore_crc16_inserter_crc2_crc - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5285.4-5289.7" - switch $and$ls180.v:5285$1042_Y - attribute \src "ls180.v:5285.8-5285.128" + attribute \src "ls180.v:2513.4-2539.7" + switch \sdram_bankmachine3_refresh_req + attribute \src "ls180.v:2513.8-2513.38" case 1'1 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + assign $0\subfragments_bankmachine3_next_state[2:0] 3'100 + attribute \src "ls180.v:2515.8-2515.12" case + attribute \src "ls180.v:2516.5-2538.8" + switch \sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:2516.9-2516.51" + case 1'1 + attribute \src "ls180.v:2517.6-2537.9" + switch \sdram_bankmachine3_row_opened + attribute \src "ls180.v:2517.10-2517.39" + case 1'1 + attribute \src "ls180.v:2518.7-2534.10" + switch \sdram_bankmachine3_row_hit + attribute \src "ls180.v:2518.11-2518.37" + case 1'1 + assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:2520.8-2527.11" + switch \sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:2520.12-2520.59" + case 1'1 + assign $0\sdram_bankmachine3_req_wdata_ready[0:0] \sdram_bankmachine3_cmd_ready + assign $0\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:2524.12-2524.16" + case + assign $0\sdram_bankmachine3_req_rdata_valid[0:0] \sdram_bankmachine3_cmd_ready + assign $0\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:2529.8-2531.11" + switch $and$ls180.v:2529$214_Y + attribute \src "ls180.v:2529.12-2529.78" + case 1'1 + assign $0\subfragments_bankmachine3_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:2532.11-2532.15" + case + assign $0\subfragments_bankmachine3_next_state[2:0] 3'001 + end + attribute \src "ls180.v:2535.10-2535.14" + case + assign $0\subfragments_bankmachine3_next_state[2:0] 3'011 + end + case + end end end sync always - update \main_sdcore_crc16_inserter_sink_ready $0\main_sdcore_crc16_inserter_sink_ready[0:0] - update \main_sdcore_crc16_inserter_source_valid $0\main_sdcore_crc16_inserter_source_valid[0:0] - update \main_sdcore_crc16_inserter_source_last $0\main_sdcore_crc16_inserter_source_last[0:0] - update \main_sdcore_crc16_inserter_source_payload_data $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + update \sdram_bankmachine3_req_wdata_ready $0\sdram_bankmachine3_req_wdata_ready[0:0] + update \sdram_bankmachine3_req_rdata_valid $0\sdram_bankmachine3_req_rdata_valid[0:0] + update \sdram_bankmachine3_refresh_gnt $0\sdram_bankmachine3_refresh_gnt[0:0] + update \sdram_bankmachine3_cmd_valid $0\sdram_bankmachine3_cmd_valid[0:0] + update \sdram_bankmachine3_cmd_payload_cas $0\sdram_bankmachine3_cmd_payload_cas[0:0] + update \sdram_bankmachine3_cmd_payload_ras $0\sdram_bankmachine3_cmd_payload_ras[0:0] + update \sdram_bankmachine3_cmd_payload_we $0\sdram_bankmachine3_cmd_payload_we[0:0] + update \sdram_bankmachine3_cmd_payload_is_cmd $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] + update \sdram_bankmachine3_cmd_payload_is_read $0\sdram_bankmachine3_cmd_payload_is_read[0:0] + update \sdram_bankmachine3_cmd_payload_is_write $0\sdram_bankmachine3_cmd_payload_is_write[0:0] + update \sdram_bankmachine3_row_open $0\sdram_bankmachine3_row_open[0:0] + update \sdram_bankmachine3_row_close $0\sdram_bankmachine3_row_close[0:0] + update \sdram_bankmachine3_row_col_n_addr_sel $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] + update \subfragments_bankmachine3_next_state $0\subfragments_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:522.5-522.67" - process $proc$ls180.v:522$3277 + attribute \src "ls180.v:248.5-248.19" + process $proc$ls180.v:248$1631 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\int_rst[0:0] 1'1 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] sync init + update \int_rst $1\int_rst[0:0] end - attribute \src "ls180.v:523.5-523.66" - process $proc$ls180.v:523$3278 + attribute \src "ls180.v:2562.1-2568.4" + process $proc$ls180.v:2562$253 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign { } { } + assign $0\sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:2564$266_Y + assign $0\sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:2565$279_Y + assign $0\sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:2566$292_Y + assign $0\sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:2567$305_Y sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - sync init + update \sdram_choose_cmd_valids $0\sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:5293.1-5298.4" - process $proc$ls180.v:5293$1043 + attribute \src "ls180.v:2576.1-2581.4" + process $proc$ls180.v:2576$306 assign { } { } - assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 - attribute \src "ls180.v:5295.2-5297.5" - switch $and$ls180.v:5295$1050_Y - attribute \src "ls180.v:5295.6-5295.301" + assign $0\sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:2578.2-2580.5" + switch \sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:2578.6-2578.32" case 1'1 - assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 + assign $0\sdram_choose_cmd_cmd_payload_cas[0:0] \t_array_muxed0 case end sync always - update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] + update \sdram_choose_cmd_cmd_payload_cas $0\sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:5301.1-5308.4" - process $proc$ls180.v:5301$1052 + attribute \src "ls180.v:2582.1-2587.4" + process $proc$ls180.v:2582$307 assign { } { } - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - attribute \src "ls180.v:5303.2-5307.5" - switch $eq$ls180.v:5303$1053_Y - attribute \src "ls180.v:5303.6-5303.45" + assign $0\sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:2584.2-2586.5" + switch \sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:2584.6-2584.32" case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 - attribute \src "ls180.v:5305.6-5305.10" + assign $0\sdram_choose_cmd_cmd_payload_ras[0:0] \t_array_muxed1 case - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 end sync always - update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] + update \sdram_choose_cmd_cmd_payload_ras $0\sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:5311.1-5318.4" - process $proc$ls180.v:5311$1055 + attribute \src "ls180.v:2588.1-2593.4" + process $proc$ls180.v:2588$308 assign { } { } - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - attribute \src "ls180.v:5313.2-5317.5" - switch $eq$ls180.v:5313$1056_Y - attribute \src "ls180.v:5313.6-5313.45" + assign $0\sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:2590.2-2592.5" + switch \sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:2590.6-2590.32" case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 - attribute \src "ls180.v:5315.6-5315.10" + assign $0\sdram_choose_cmd_cmd_payload_we[0:0] \t_array_muxed2 case - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 end sync always - update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] + update \sdram_choose_cmd_cmd_payload_we $0\sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:5321.1-5328.4" - process $proc$ls180.v:5321$1058 + attribute \src "ls180.v:2595.1-2601.4" + process $proc$ls180.v:2595$311 assign { } { } - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - attribute \src "ls180.v:5323.2-5327.5" - switch $eq$ls180.v:5323$1059_Y - attribute \src "ls180.v:5323.6-5323.45" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 - attribute \src "ls180.v:5325.6-5325.10" - case - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - end + assign { } { } + assign $0\sdram_choose_req_valids[3:0] [0] $and$ls180.v:2597$324_Y + assign $0\sdram_choose_req_valids[3:0] [1] $and$ls180.v:2598$337_Y + assign $0\sdram_choose_req_valids[3:0] [2] $and$ls180.v:2599$350_Y + assign $0\sdram_choose_req_valids[3:0] [3] $and$ls180.v:2600$363_Y sync always - update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] + update \sdram_choose_req_valids $0\sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:5331.1-5338.4" - process $proc$ls180.v:5331$1061 + attribute \src "ls180.v:2609.1-2614.4" + process $proc$ls180.v:2609$364 assign { } { } - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - attribute \src "ls180.v:5333.2-5337.5" - switch $eq$ls180.v:5333$1062_Y - attribute \src "ls180.v:5333.6-5333.45" + assign $0\sdram_choose_req_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:2611.2-2613.5" + switch \sdram_choose_req_cmd_valid + attribute \src "ls180.v:2611.6-2611.32" case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 - attribute \src "ls180.v:5335.6-5335.10" + assign $0\sdram_choose_req_cmd_payload_cas[0:0] \t_array_muxed3 case - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 end sync always - update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] + update \sdram_choose_req_cmd_payload_cas $0\sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:5340.1-5345.4" - process $proc$ls180.v:5340$1063 + attribute \src "ls180.v:2615.1-2620.4" + process $proc$ls180.v:2615$365 assign { } { } - assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - attribute \src "ls180.v:5342.2-5344.5" - switch $and$ls180.v:5342$1065_Y - attribute \src "ls180.v:5342.6-5342.85" + assign $0\sdram_choose_req_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:2617.2-2619.5" + switch \sdram_choose_req_cmd_valid + attribute \src "ls180.v:2617.6-2617.32" case 1'1 - assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 + assign $0\sdram_choose_req_cmd_payload_ras[0:0] \t_array_muxed4 case end sync always - update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] + update \sdram_choose_req_cmd_payload_ras $0\sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:5346.1-5353.4" - process $proc$ls180.v:5346$1066 + attribute \src "ls180.v:2621.1-2626.4" + process $proc$ls180.v:2621$366 assign { } { } - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - attribute \src "ls180.v:5348.2-5352.5" - switch $lt$ls180.v:5348$1067_Y - attribute \src "ls180.v:5348.6-5348.44" + assign $0\sdram_choose_req_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:2623.2-2625.5" + switch \sdram_choose_req_cmd_valid + attribute \src "ls180.v:2623.6-2623.32" case 1'1 - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5350.6-5350.10" + assign $0\sdram_choose_req_cmd_payload_we[0:0] \t_array_muxed5 case - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready end sync always - update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] + update \sdram_choose_req_cmd_payload_we $0\sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:5357.1-5364.4" - process $proc$ls180.v:5357$1078 + attribute \src "ls180.v:2627.1-2635.4" + process $proc$ls180.v:2627$367 assign { } { } - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5359.2-5363.5" - switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:5359.6-5359.43" + assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:2629.2-2631.5" + switch $and$ls180.v:2629$370_Y + attribute \src "ls180.v:2629.6-2629.100" case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:5361.6-5361.10" + assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'1 case - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 end - sync always - update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] - end - attribute \src "ls180.v:5367.1-5374.4" - process $proc$ls180.v:5367$1089 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5369.2-5373.5" - switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:5369.6-5369.43" + attribute \src "ls180.v:2632.2-2634.5" + switch $and$ls180.v:2632$373_Y + attribute \src "ls180.v:2632.6-2632.100" case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:5371.6-5371.10" + assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'1 case - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 end sync always - update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] + update \sdram_bankmachine0_cmd_ready $0\sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:263.12-263.33" + process $proc$ls180.v:263$1632 + assign { } { } + assign $1\dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \dfi_p0_rddata $1\dfi_p0_rddata[15:0] end - attribute \src "ls180.v:5377.1-5384.4" - process $proc$ls180.v:5377$1100 + attribute \src "ls180.v:2636.1-2644.4" + process $proc$ls180.v:2636$374 assign { } { } - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5379.2-5383.5" - switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:5379.6-5379.43" + assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:2638.2-2640.5" + switch $and$ls180.v:2638$377_Y + attribute \src "ls180.v:2638.6-2638.100" + case 1'1 + assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:2641.2-2643.5" + switch $and$ls180.v:2641$380_Y + attribute \src "ls180.v:2641.6-2641.100" case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:5381.6-5381.10" + assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'1 case - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 end sync always - update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] + update \sdram_bankmachine1_cmd_ready $0\sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "ls180.v:538.11-538.68" - process $proc$ls180.v:538$3279 + attribute \src "ls180.v:264.5-264.31" + process $proc$ls180.v:264$1633 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\dfi_p0_rddata_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \dfi_p0_rddata_valid $1\dfi_p0_rddata_valid[0:0] end - attribute \src "ls180.v:5387.1-5394.4" - process $proc$ls180.v:5387$1111 + attribute \src "ls180.v:2645.1-2653.4" + process $proc$ls180.v:2645$381 assign { } { } - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5389.2-5393.5" - switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:5389.6-5389.43" + assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:2647.2-2649.5" + switch $and$ls180.v:2647$384_Y + attribute \src "ls180.v:2647.6-2647.100" case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:5391.6-5391.10" + assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:2650.2-2652.5" + switch $and$ls180.v:2650$387_Y + attribute \src "ls180.v:2650.6-2650.100" + case 1'1 + assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'1 case - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 end sync always - update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] + update \sdram_bankmachine2_cmd_ready $0\sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:539.5-539.64" - process $proc$ls180.v:539$3280 + attribute \src "ls180.v:265.11-265.27" + process $proc$ls180.v:265$1634 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\rddata_en[2:0] 3'000 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] sync init + update \rddata_en $1\rddata_en[2:0] end - attribute \src "ls180.v:5395.1-5585.4" - process $proc$ls180.v:5395$1112 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:2654.1-2662.4" + process $proc$ls180.v:2654$388 assign { } { } + assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:2656.2-2658.5" + switch $and$ls180.v:2656$391_Y + attribute \src "ls180.v:2656.6-2656.100" + case 1'1 + assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:2659.2-2661.5" + switch $and$ls180.v:2659$394_Y + attribute \src "ls180.v:2659.6-2659.100" + case 1'1 + assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + sync always + update \sdram_bankmachine3_cmd_ready $0\sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:2667.1-2739.4" + process $proc$ls180.v:2667$397 assign { } { } assign { } { } assign { } { } @@ -294934,510 +263948,201 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\sdram_en1[0:0] 1'0 + assign $0\sdram_choose_req_want_reads[0:0] 1'0 + assign $0\sdram_choose_req_want_writes[0:0] 1'0 + assign $0\sdram_cmd_ready[0:0] 1'0 assign { } { } - assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + assign $0\sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\sdram_steerer_sel[1:0] 2'00 assign { } { } - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 - assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 - assign $0\main_sdphy_datar_sink_last[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 - assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 - assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 - assign $0\main_sdphy_datar_source_ready[0:0] 1'0 - assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state - attribute \src "ls180.v:5436.2-5584.9" - switch \builder_sdcore_fsm_state + assign $0\sdram_en0[0:0] 1'0 + assign $0\sdram_choose_req_want_activates[0:0] \sdram_ras_allowed + assign $0\subfragments_multiplexer_next_state[2:0] \subfragments_multiplexer_state + attribute \src "ls180.v:2679.2-2738.9" + switch \subfragments_multiplexer_state attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 - attribute \src "ls180.v:5439.4-5459.11" - switch \main_sdcore_cmd_count - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { 2'01 \main_sdcore_cmd_command_storage [13:8] } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [31:24] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [23:16] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [15:8] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [7:0] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } - assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5457$1113_Y + assign $0\sdram_en1[0:0] 1'1 + assign $0\sdram_choose_req_want_writes[0:0] 1'1 + assign $0\sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:2683.4-2689.7" + switch 1'1 + attribute \src "ls180.v:2683.8-2683.12" + case 1'1 + assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2684$404_Y case end - attribute \src "ls180.v:5460.4-5472.7" - switch $and$ls180.v:5460$1114_Y - attribute \src "ls180.v:5460.8-5460.65" + attribute \src "ls180.v:2691.4-2695.7" + switch \sdram_read_available + attribute \src "ls180.v:2691.8-2691.28" case 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5461$1115_Y - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - attribute \src "ls180.v:5463.5-5471.8" - switch $eq$ls180.v:5463$1116_Y - attribute \src "ls180.v:5463.9-5463.40" + attribute \src "ls180.v:2692.5-2694.8" + switch $or$ls180.v:2692$406_Y + attribute \src "ls180.v:2692.9-2692.53" case 1'1 - attribute \src "ls180.v:5464.6-5470.9" - switch $eq$ls180.v:5464$1117_Y - attribute \src "ls180.v:5464.10-5464.40" - case 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5468.10-5468.14" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 - end + assign $0\subfragments_multiplexer_next_state[2:0] 3'011 case end case end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5476$1118_Y - assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 - attribute \src "ls180.v:5477.4-5481.7" - switch $eq$ls180.v:5477$1119_Y - attribute \src "ls180.v:5477.8-5477.38" + attribute \src "ls180.v:2696.4-2698.7" + switch \sdram_go_to_refresh + attribute \src "ls180.v:2696.8-2696.27" case 1'1 - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 - attribute \src "ls180.v:5479.8-5479.12" + assign $0\subfragments_multiplexer_next_state[2:0] 3'010 case - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 end - attribute \src "ls180.v:5483.4-5504.7" - switch \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:5483.8-5483.36" + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\sdram_steerer_sel[1:0] 2'11 + assign $0\sdram_cmd_ready[0:0] 1'1 + attribute \src "ls180.v:2703.4-2705.7" + switch \sdram_cmd_last + attribute \src "ls180.v:2703.8-2703.22" case 1'1 - attribute \src "ls180.v:5484.5-5503.8" - switch $eq$ls180.v:5484$1120_Y - attribute \src "ls180.v:5484.9-5484.56" - case 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5488.9-5488.13" - case - attribute \src "ls180.v:5489.6-5502.9" - switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:5489.10-5489.37" - case 1'1 - attribute \src "ls180.v:5490.7-5498.10" - switch $eq$ls180.v:5490$1121_Y - attribute \src "ls180.v:5490.11-5490.42" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:5492.11-5492.15" - case - attribute \src "ls180.v:5493.8-5497.11" - switch $eq$ls180.v:5493$1122_Y - attribute \src "ls180.v:5493.12-5493.43" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - attribute \src "ls180.v:5495.12-5495.16" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - end - end - attribute \src "ls180.v:5499.10-5499.14" - case - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 - end - end + assign $0\subfragments_multiplexer_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\main_sdphy_dataw_sink_valid[0:0] \main_sdcore_crc16_inserter_source_valid - assign $0\main_sdcore_crc16_inserter_source_ready[0:0] \main_sdphy_dataw_sink_ready - assign $0\main_sdphy_dataw_sink_first[0:0] \main_sdcore_crc16_inserter_source_first - assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last - assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data - assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - attribute \src "ls180.v:5512.4-5518.7" - switch $and$ls180.v:5512$1124_Y - attribute \src "ls180.v:5512.8-5512.98" + attribute \src "ls180.v:2708.4-2710.7" + switch \sdram_twtrcon_ready + attribute \src "ls180.v:2708.8-2708.27" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5513$1125_Y - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5515.5-5517.8" - switch $eq$ls180.v:5515$1127_Y - attribute \src "ls180.v:5515.9-5515.77" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - case - end + assign $0\subfragments_multiplexer_next_state[2:0] 3'000 case end - attribute \src "ls180.v:5520.4-5525.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5520.8-5520.37" + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\subfragments_multiplexer_next_state[2:0] 3'101 + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\subfragments_multiplexer_next_state[2:0] 3'001 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\sdram_en0[0:0] 1'1 + assign $0\sdram_choose_req_want_reads[0:0] 1'1 + assign $0\sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:2721.4-2727.7" + switch 1'1 + attribute \src "ls180.v:2721.8-2721.12" case 1'1 - attribute \src "ls180.v:5521.5-5524.8" - switch $ne$ls180.v:5521$1128_Y - attribute \src "ls180.v:5521.9-5521.57" - case 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 - case - end + assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2722$413_Y case end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 - assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage - assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5530$1130_Y - attribute \src "ls180.v:5531.4-5557.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5531.8-5531.37" + attribute \src "ls180.v:2729.4-2733.7" + switch \sdram_write_available + attribute \src "ls180.v:2729.8-2729.29" case 1'1 - attribute \src "ls180.v:5532.5-5556.8" - switch $eq$ls180.v:5532$1131_Y - attribute \src "ls180.v:5532.9-5532.57" + attribute \src "ls180.v:2730.5-2732.8" + switch $or$ls180.v:2730$415_Y + attribute \src "ls180.v:2730.9-2730.52" case 1'1 - assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid - assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready - assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first - assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last - assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:5538.6-5546.9" - switch $and$ls180.v:5538$1132_Y - attribute \src "ls180.v:5538.10-5538.72" - case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5539$1133_Y - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5541.7-5545.10" - switch $eq$ls180.v:5541$1135_Y - attribute \src "ls180.v:5541.11-5541.79" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5543.11-5543.15" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - end - case - end - attribute \src "ls180.v:5547.9-5547.13" + assign $0\subfragments_multiplexer_next_state[2:0] 3'100 case - attribute \src "ls180.v:5548.6-5555.9" - switch $eq$ls180.v:5548$1136_Y - attribute \src "ls180.v:5548.10-5548.58" - case 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - case - end end case end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5568.4-5582.7" - switch \main_sdcore_cmd_send_re - attribute \src "ls180.v:5568.8-5568.31" + attribute \src "ls180.v:2734.4-2736.7" + switch \sdram_go_to_refresh + attribute \src "ls180.v:2734.8-2734.27" case 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 + assign $0\subfragments_multiplexer_next_state[2:0] 3'010 case end end sync always - update \main_sdphy_cmdw_sink_valid $0\main_sdphy_cmdw_sink_valid[0:0] - update \main_sdphy_cmdw_sink_last $0\main_sdphy_cmdw_sink_last[0:0] - update \main_sdphy_cmdw_sink_payload_data $0\main_sdphy_cmdw_sink_payload_data[7:0] - update \main_sdphy_cmdr_sink_valid $0\main_sdphy_cmdr_sink_valid[0:0] - update \main_sdphy_cmdr_sink_last $0\main_sdphy_cmdr_sink_last[0:0] - update \main_sdphy_cmdr_sink_payload_length $0\main_sdphy_cmdr_sink_payload_length[7:0] - update \main_sdphy_cmdr_source_ready $0\main_sdphy_cmdr_source_ready[0:0] - update \main_sdphy_dataw_sink_valid $0\main_sdphy_dataw_sink_valid[0:0] - update \main_sdphy_dataw_sink_first $0\main_sdphy_dataw_sink_first[0:0] - update \main_sdphy_dataw_sink_last $0\main_sdphy_dataw_sink_last[0:0] - update \main_sdphy_dataw_sink_payload_data $0\main_sdphy_dataw_sink_payload_data[7:0] - update \main_sdphy_datar_sink_valid $0\main_sdphy_datar_sink_valid[0:0] - update \main_sdphy_datar_sink_last $0\main_sdphy_datar_sink_last[0:0] - update \main_sdphy_datar_sink_payload_block_length $0\main_sdphy_datar_sink_payload_block_length[9:0] - update \main_sdphy_datar_source_ready $0\main_sdphy_datar_source_ready[0:0] - update \main_sdcore_crc16_inserter_source_ready $0\main_sdcore_crc16_inserter_source_ready[0:0] - update \main_sdcore_crc16_checker_sink_valid $0\main_sdcore_crc16_checker_sink_valid[0:0] - update \main_sdcore_crc16_checker_sink_first $0\main_sdcore_crc16_checker_sink_first[0:0] - update \main_sdcore_crc16_checker_sink_last $0\main_sdcore_crc16_checker_sink_last[0:0] - update \main_sdcore_crc16_checker_sink_payload_data $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] - update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - update \main_sdcore_data_done_sdcore_fsm_next_value1 $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - update \main_sdcore_data_count_sdcore_fsm_next_value3 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - update \main_sdcore_data_error_sdcore_fsm_next_value6 $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + update \sdram_cmd_ready $0\sdram_cmd_ready[0:0] + update \sdram_choose_req_want_reads $0\sdram_choose_req_want_reads[0:0] + update \sdram_choose_req_want_writes $0\sdram_choose_req_want_writes[0:0] + update \sdram_choose_req_want_activates $0\sdram_choose_req_want_activates[0:0] + update \sdram_choose_req_cmd_ready $0\sdram_choose_req_cmd_ready[0:0] + update \sdram_steerer_sel $0\sdram_steerer_sel[1:0] + update \sdram_en0 $0\sdram_en0[0:0] + update \sdram_en1 $0\sdram_en1[0:0] + update \subfragments_multiplexer_next_state $0\subfragments_multiplexer_next_state[2:0] end - attribute \src "ls180.v:540.11-540.70" - process $proc$ls180.v:540$3281 + attribute \src "ls180.v:268.5-268.31" + process $proc$ls180.v:268$1635 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\sdram_inti_p0_cas_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \sdram_inti_p0_cas_n $1\sdram_inti_p0_cas_n[0:0] end - attribute \src "ls180.v:541.11-541.70" - process $proc$ls180.v:541$3282 + attribute \src "ls180.v:269.5-269.30" + process $proc$ls180.v:269$1636 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\sdram_inti_p0_cs_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \sdram_inti_p0_cs_n $1\sdram_inti_p0_cs_n[0:0] end - attribute \src "ls180.v:542.11-542.73" - process $proc$ls180.v:542$3283 + attribute \src "ls180.v:270.5-270.31" + process $proc$ls180.v:270$1637 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\sdram_inti_p0_ras_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + update \sdram_inti_p0_ras_n $1\sdram_inti_p0_ras_n[0:0] end - attribute \src "ls180.v:55.5-55.42" - process $proc$ls180.v:55$3128 + attribute \src "ls180.v:271.5-271.30" + process $proc$ls180.v:271$1638 assign { } { } - assign $1\main_libresocsim_reset_storage[0:0] 1'0 + assign $1\sdram_inti_p0_we_n[0:0] 1'1 sync always sync init - update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] + update \sdram_inti_p0_we_n $1\sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:56.5-56.37" - process $proc$ls180.v:56$3129 + attribute \src "ls180.v:275.5-275.31" + process $proc$ls180.v:275$1639 assign { } { } - assign $1\main_libresocsim_reset_re[0:0] 1'0 + assign $0\sdram_inti_p0_act_n[0:0] 1'1 sync always + update \sdram_inti_p0_act_n $0\sdram_inti_p0_act_n[0:0] sync init - update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] end - attribute \src "ls180.v:5613.1-5620.4" - process $proc$ls180.v:5613$1137 + attribute \src "ls180.v:2763.1-2776.4" + process $proc$ls180.v:2763$544 assign { } { } - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5615.2-5619.5" - switch \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:5615.6-5615.35" + assign { } { } + assign $0\sdram_interface_wdata_we[1:0] 2'00 + assign $0\sdram_interface_wdata[15:0] 16'0000000000000000 + attribute \src "ls180.v:2766.2-2775.9" + switch \subfragments_new_master_wdata_ready + attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5616$1138_Y - attribute \src "ls180.v:5617.6-5617.10" + assign $0\sdram_interface_wdata[15:0] \port_wdata_payload_data + assign $0\sdram_interface_wdata_we[1:0] \port_wdata_payload_we + attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce + assign $0\sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\sdram_interface_wdata_we[1:0] 2'00 end sync always - update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:563.5-563.59" - process $proc$ls180.v:563$3284 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \sdram_interface_wdata $0\sdram_interface_wdata[15:0] + update \sdram_interface_wdata_we $0\sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:5646.1-5685.4" - process $proc$ls180.v:5646$1148 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:2783.1-2793.4" + process $proc$ls180.v:2783$546 assign { } { } - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 - assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 - assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state - attribute \src "ls180.v:5656.2-5684.9" - switch \builder_sdblock2memdma_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid - assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5660$1149_Y - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:5662.4-5673.7" - switch $and$ls180.v:5662$1150_Y - attribute \src "ls180.v:5662.8-5662.103" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5663$1151_Y - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5665.5-5672.8" - switch $eq$ls180.v:5665$1153_Y - attribute \src "ls180.v:5665.9-5665.106" - case 1'1 - attribute \src "ls180.v:5666.6-5671.9" - switch \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:5666.10-5666.57" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5669.10-5669.14" - case - assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 - end - case - end - case - end + assign $0\litedram_wb_dat_w[15:0] 16'0000000000000000 + attribute \src "ls180.v:2785.2-2792.9" + switch \converter_counter attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 + case 1'0 + assign $0\litedram_wb_dat_w[15:0] \wb_sdram_dat_w [15:0] attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\litedram_wb_dat_w[15:0] \wb_sdram_dat_w [31:16] case - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 end sync always - update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] - update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] - update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] - update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - end - attribute \src "ls180.v:565.5-565.59" - process $proc$ls180.v:565$3285 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:566.5-566.58" - process $proc$ls180.v:566$3286 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:567.5-567.64" - process $proc$ls180.v:567$3287 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:568.12-568.74" - process $proc$ls180.v:568$3288 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:569.12-569.47" - process $proc$ls180.v:569$3289 - assign { } { } - assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] - end - attribute \src "ls180.v:57.12-57.60" - process $proc$ls180.v:57$3130 - assign { } { } - assign $1\main_libresocsim_scratch_storage[31:0] 305419896 - sync always - sync init - update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] - end - attribute \src "ls180.v:570.5-570.46" - process $proc$ls180.v:570$3290 - assign { } { } - assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + update \litedram_wb_dat_w $0\litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:5705.1-5742.4" - process $proc$ls180.v:5705$1155 - assign { } { } + attribute \src "ls180.v:2795.1-2841.4" + process $proc$ls180.v:2795$547 assign { } { } assign { } { } assign { } { } @@ -295448,2594 +264153,1963 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\litedram_wb_sel[1:0] 2'00 + assign $0\litedram_wb_cyc[0:0] 1'0 + assign $0\litedram_wb_stb[0:0] 1'0 + assign $0\litedram_wb_we[0:0] 1'0 + assign $0\wb_sdram_ack[0:0] 1'0 + assign $0\converter_skip[0:0] 1'0 assign { } { } - assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 - assign $0\main_interface1_bus_adr[31:0] 0 - assign { } { } - assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_interface1_bus_sel[7:0] 8'00000000 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 - assign $0\main_interface1_bus_cyc[0:0] 1'0 - assign $0\main_interface1_bus_stb[0:0] 1'0 - assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:5719.2-5741.9" - switch \builder_sdmem2blockdma_fsm_state + assign $0\converter_counter_subfragments_next_value[0:0] 1'0 + assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'0 + assign $0\subfragments_next_state[0:0] \subfragments_state + attribute \src "ls180.v:2807.2-2840.9" + switch \subfragments_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last - assign $0\main_sdmem2block_dma_source_payload_data[63:0] \main_sdmem2block_dma_data - attribute \src "ls180.v:5724.4-5727.7" - switch \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:5724.8-5724.41" - case 1'1 - assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid - assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid - assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_interface1_bus_sel[7:0] 8'11111111 - assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:5735.4-5739.7" - switch $and$ls180.v:5735$1156_Y - attribute \src "ls180.v:5735.8-5735.59" + assign $0\litedram_wb_adr[29:0] { \wb_sdram_adr [28:0] \converter_counter } + attribute \src "ls180.v:2810.4-2817.11" + switch \converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\litedram_wb_sel[1:0] \wb_sdram_sel [1:0] + attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] \main_interface1_bus_dat_r [39:32] \main_interface1_bus_dat_r [47:40] \main_interface1_bus_dat_r [55:48] \main_interface1_bus_dat_r [63:56] } - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 + assign $0\litedram_wb_sel[1:0] \wb_sdram_sel [3:2] case end - end - sync always - update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] - update \main_interface1_bus_sel $0\main_interface1_bus_sel[7:0] - update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] - update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] - update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] - update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] - update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] - update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] - update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[63:0] - update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:572.5-572.44" - process $proc$ls180.v:572$3291 - assign { } { } - assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] - end - attribute \src "ls180.v:573.5-573.45" - process $proc$ls180.v:573$3292 - assign { } { } - assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] - end - attribute \src "ls180.v:574.5-574.54" - process $proc$ls180.v:574$3293 - assign { } { } - assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:5743.1-5779.4" - process $proc$ls180.v:5743$1157 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 - assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:5752.2-5778.9" - switch \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5755$1159_Y - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5756$1160_Y - attribute \src "ls180.v:5757.4-5768.7" - switch \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:5757.8-5757.39" + attribute \src "ls180.v:2818.4-2831.7" + switch $and$ls180.v:2818$548_Y + attribute \src "ls180.v:2818.8-2818.37" case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5758$1161_Y - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5760.5-5767.8" - switch \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:5760.9-5760.39" + assign $0\converter_skip[0:0] $eq$ls180.v:2819$549_Y + assign $0\litedram_wb_we[0:0] \wb_sdram_we + assign $0\litedram_wb_cyc[0:0] $not$ls180.v:2821$550_Y + assign $0\litedram_wb_stb[0:0] $not$ls180.v:2822$551_Y + attribute \src "ls180.v:2823.5-2830.8" + switch $or$ls180.v:2823$552_Y + attribute \src "ls180.v:2823.9-2823.43" case 1'1 - attribute \src "ls180.v:5761.6-5766.9" - switch \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:5761.10-5761.43" + assign $0\converter_counter_subfragments_next_value[0:0] $add$ls180.v:2824$553_Y + assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2826.6-2829.9" + switch $eq$ls180.v:2826$554_Y + attribute \src "ls180.v:2826.10-2826.37" case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5764.10-5764.14" + assign $0\wb_sdram_ack[0:0] 1'1 + assign $0\subfragments_next_state[0:0] 1'0 case - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 end case end case end attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdmem2block_dma_done_status[0:0] 1'1 - attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 + assign $0\converter_counter_subfragments_next_value[0:0] 1'0 + assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2836.4-2838.7" + switch $and$ls180.v:2836$555_Y + attribute \src "ls180.v:2836.8-2836.37" + case 1'1 + assign $0\subfragments_next_state[0:0] 1'1 + case + end end sync always - update \main_sdmem2block_dma_sink_valid $0\main_sdmem2block_dma_sink_valid[0:0] - update \main_sdmem2block_dma_sink_last $0\main_sdmem2block_dma_sink_last[0:0] - update \main_sdmem2block_dma_sink_payload_address $0\main_sdmem2block_dma_sink_payload_address[31:0] - update \main_sdmem2block_dma_done_status $0\main_sdmem2block_dma_done_status[0:0] - update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - end - attribute \src "ls180.v:576.32-576.76" - process $proc$ls180.v:576$3294 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + update \wb_sdram_ack $0\wb_sdram_ack[0:0] + update \litedram_wb_adr $0\litedram_wb_adr[29:0] + update \litedram_wb_sel $0\litedram_wb_sel[1:0] + update \litedram_wb_cyc $0\litedram_wb_cyc[0:0] + update \litedram_wb_stb $0\litedram_wb_stb[0:0] + update \litedram_wb_we $0\litedram_wb_we[0:0] + update \converter_skip $0\converter_skip[0:0] + update \subfragments_next_state $0\subfragments_next_state[0:0] + update \converter_counter_subfragments_next_value $0\converter_counter_subfragments_next_value[0:0] + update \converter_counter_subfragments_next_value_ce $0\converter_counter_subfragments_next_value_ce[0:0] end - attribute \src "ls180.v:577.11-577.55" - process $proc$ls180.v:577$3295 + attribute \src "ls180.v:280.12-280.40" + process $proc$ls180.v:280$1640 assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + assign $1\sdram_inti_p0_rddata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] + update \sdram_inti_p0_rddata $1\sdram_inti_p0_rddata[15:0] end - attribute \src "ls180.v:579.32-579.75" - process $proc$ls180.v:579$3296 + attribute \src "ls180.v:281.5-281.38" + process $proc$ls180.v:281$1641 assign { } { } - assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + assign $1\sdram_inti_p0_rddata_valid[0:0] 1'0 sync always - update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] sync init + update \sdram_inti_p0_rddata_valid $1\sdram_inti_p0_rddata_valid[0:0] end - attribute \src "ls180.v:5791.1-5819.4" - process $proc$ls180.v:5791$1167 + attribute \src "ls180.v:2886.1-2891.4" + process $proc$ls180.v:2886$587 assign { } { } - assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - attribute \src "ls180.v:5793.2-5818.9" - switch \main_sdmem2block_converter_mux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [63:56] - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [55:48] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [47:40] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [39:32] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] - attribute \src "ls180.v:0.0-0.0" + assign $0\tx_clear[0:0] 1'0 + attribute \src "ls180.v:2888.2-2890.5" + switch $and$ls180.v:2888$588_Y + attribute \src "ls180.v:2888.6-2888.59" + case 1'1 + assign $0\tx_clear[0:0] 1'1 case - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] end sync always - update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] + update \tx_clear $0\tx_clear[0:0] end - attribute \src "ls180.v:58.5-58.39" - process $proc$ls180.v:58$3131 + attribute \src "ls180.v:2892.1-2896.4" + process $proc$ls180.v:2892$589 assign { } { } - assign $1\main_libresocsim_scratch_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] - end - attribute \src "ls180.v:581.32-581.76" - process $proc$ls180.v:581$3297 assign { } { } - assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + assign $0\eventmanager_status_w[1:0] [0] \tx_status + assign $0\eventmanager_status_w[1:0] [1] \rx_status sync always - update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] - sync init + update \eventmanager_status_w $0\eventmanager_status_w[1:0] end - attribute \src "ls180.v:5833.1-5840.4" - process $proc$ls180.v:5833$1168 + attribute \src "ls180.v:2897.1-2902.4" + process $proc$ls180.v:2897$590 assign { } { } - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5835.2-5839.5" - switch \main_sdmem2block_fifo_replace - attribute \src "ls180.v:5835.6-5835.35" + assign $0\rx_clear[0:0] 1'0 + attribute \src "ls180.v:2899.2-2901.5" + switch $and$ls180.v:2899$591_Y + attribute \src "ls180.v:2899.6-2899.59" case 1'1 - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5836$1169_Y - attribute \src "ls180.v:5837.6-5837.10" + assign $0\rx_clear[0:0] 1'1 case - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce end sync always - update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] + update \rx_clear $0\rx_clear[0:0] end - attribute \src "ls180.v:5848.1-5884.4" - process $proc$ls180.v:5848$1175 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:2903.1-2907.4" + process $proc$ls180.v:2903$592 assign { } { } assign { } { } + assign $0\eventmanager_pending_w[1:0] [0] \tx_pending + assign $0\eventmanager_pending_w[1:0] [1] \rx_pending + sync always + update \eventmanager_pending_w $0\eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:2925.1-2932.4" + process $proc$ls180.v:2925$600 assign { } { } - assign { } { } - assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 - assign { } { } - assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 - assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 - assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 - assign $0\builder_next_state[1:0] \builder_state - attribute \src "ls180.v:5859.2-5883.9" - switch \builder_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 - assign $0\builder_next_state[1:0] 2'10 - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 - assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } - assign $0\builder_next_state[1:0] 2'00 - attribute \src "ls180.v:0.0-0.0" + assign $0\tx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:2927.2-2931.5" + switch \tx_fifo_replace + attribute \src "ls180.v:2927.6-2927.21" + case 1'1 + assign $0\tx_fifo_wrport_adr[3:0] $sub$ls180.v:2928$601_Y + attribute \src "ls180.v:2929.6-2929.10" case - assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] - assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5875.4-5881.7" - switch $and$ls180.v:5875$1176_Y - attribute \src "ls180.v:5875.8-5875.77" - case 1'1 - assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5878$1178_Y - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 - assign $0\builder_next_state[1:0] 2'01 - case - end + assign $0\tx_fifo_wrport_adr[3:0] \tx_fifo_produce end sync always - update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] - update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] - update \builder_next_state $0\builder_next_state[1:0] - update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] - update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] - update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] - update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] - update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] + update \tx_fifo_wrport_adr $0\tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:587.5-587.51" - process $proc$ls180.v:587$3298 + attribute \src "ls180.v:2955.1-2962.4" + process $proc$ls180.v:2955$611 assign { } { } - assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign $0\rx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:2957.2-2961.5" + switch \rx_fifo_replace + attribute \src "ls180.v:2957.6-2957.21" + case 1'1 + assign $0\rx_fifo_wrport_adr[3:0] $sub$ls180.v:2958$612_Y + attribute \src "ls180.v:2959.6-2959.10" + case + assign $0\rx_fifo_wrport_adr[3:0] \rx_fifo_produce + end sync always - sync init - update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + update \rx_fifo_wrport_adr $0\rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:588.5-588.51" - process $proc$ls180.v:588$3299 + attribute \src "ls180.v:296.12-296.41" + process $proc$ls180.v:296$1642 assign { } { } - assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $1\sdram_slave_p0_rddata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + update \sdram_slave_p0_rddata $1\sdram_slave_p0_rddata[15:0] end - attribute \src "ls180.v:590.5-590.47" - process $proc$ls180.v:590$3300 + attribute \src "ls180.v:297.5-297.39" + process $proc$ls180.v:297$1643 assign { } { } - assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $1\sdram_slave_p0_rddata_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] + update \sdram_slave_p0_rddata_valid $1\sdram_slave_p0_rddata_valid[0:0] end - attribute \src "ls180.v:5909.1-5924.4" - process $proc$ls180.v:5909$1199 + attribute \src "ls180.v:2971.1-2981.4" + process $proc$ls180.v:2971$618 assign { } { } assign { } { } - assign $0\builder_slave_sel[12:0] [0] $eq$ls180.v:5911$1200_Y - assign $0\builder_slave_sel[12:0] [1] $eq$ls180.v:5912$1201_Y - assign $0\builder_slave_sel[12:0] [2] $eq$ls180.v:5913$1202_Y - assign $0\builder_slave_sel[12:0] [3] $eq$ls180.v:5914$1203_Y - assign $0\builder_slave_sel[12:0] [4] $eq$ls180.v:5915$1204_Y - assign $0\builder_slave_sel[12:0] [5] $eq$ls180.v:5916$1205_Y - assign $0\builder_slave_sel[12:0] [6] $eq$ls180.v:5917$1206_Y - assign $0\builder_slave_sel[12:0] [7] $eq$ls180.v:5918$1207_Y - assign $0\builder_slave_sel[12:0] [8] $eq$ls180.v:5919$1208_Y - assign $0\builder_slave_sel[12:0] [9] $eq$ls180.v:5920$1209_Y - assign $0\builder_slave_sel[12:0] [10] $eq$ls180.v:5921$1210_Y - assign $0\builder_slave_sel[12:0] [11] $eq$ls180.v:5922$1211_Y - assign $0\builder_slave_sel[12:0] [12] $eq$ls180.v:5923$1212_Y + assign $0\gpio0_pads_gpio0i[7:0] [0] \libresocsim_libresoc_constraintmanager_gpio_i [0] + assign $0\gpio0_pads_gpio0i[7:0] [1] \libresocsim_libresoc_constraintmanager_gpio_i [1] + assign $0\gpio0_pads_gpio0i[7:0] [2] \libresocsim_libresoc_constraintmanager_gpio_i [2] + assign $0\gpio0_pads_gpio0i[7:0] [3] \libresocsim_libresoc_constraintmanager_gpio_i [3] + assign $0\gpio0_pads_gpio0i[7:0] [4] \libresocsim_libresoc_constraintmanager_gpio_i [4] + assign $0\gpio0_pads_gpio0i[7:0] [5] \libresocsim_libresoc_constraintmanager_gpio_i [5] + assign $0\gpio0_pads_gpio0i[7:0] [6] \libresocsim_libresoc_constraintmanager_gpio_i [6] + assign $0\gpio0_pads_gpio0i[7:0] [7] \libresocsim_libresoc_constraintmanager_gpio_i [7] sync always - update \builder_slave_sel $0\builder_slave_sel[12:0] + update \gpio0_pads_gpio0i $0\gpio0_pads_gpio0i[7:0] end - attribute \src "ls180.v:591.5-591.45" - process $proc$ls180.v:591$3301 + attribute \src "ls180.v:298.12-298.43" + process $proc$ls180.v:298$1644 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $1\sdram_master_p0_address[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + update \sdram_master_p0_address $1\sdram_master_p0_address[12:0] end - attribute \src "ls180.v:592.5-592.45" - process $proc$ls180.v:592$3302 + attribute \src "ls180.v:2982.1-2992.4" + process $proc$ls180.v:2982$619 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] - end - attribute \src "ls180.v:593.12-593.57" - process $proc$ls180.v:593$3303 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + assign $0\gpio1_pads_gpio1i[7:0] [0] \libresocsim_libresoc_constraintmanager_gpio_i [8] + assign $0\gpio1_pads_gpio1i[7:0] [1] \libresocsim_libresoc_constraintmanager_gpio_i [9] + assign $0\gpio1_pads_gpio1i[7:0] [2] \libresocsim_libresoc_constraintmanager_gpio_i [10] + assign $0\gpio1_pads_gpio1i[7:0] [3] \libresocsim_libresoc_constraintmanager_gpio_i [11] + assign $0\gpio1_pads_gpio1i[7:0] [4] \libresocsim_libresoc_constraintmanager_gpio_i [12] + assign $0\gpio1_pads_gpio1i[7:0] [5] \libresocsim_libresoc_constraintmanager_gpio_i [13] + assign $0\gpio1_pads_gpio1i[7:0] [6] \libresocsim_libresoc_constraintmanager_gpio_i [14] + assign $0\gpio1_pads_gpio1i[7:0] [7] \libresocsim_libresoc_constraintmanager_gpio_i [15] sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + update \gpio1_pads_gpio1i $0\gpio1_pads_gpio1i[7:0] end - attribute \src "ls180.v:595.5-595.51" - process $proc$ls180.v:595$3304 + attribute \src "ls180.v:299.11-299.38" + process $proc$ls180.v:299$1645 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $1\sdram_master_p0_bank[1:0] 2'00 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + update \sdram_master_p0_bank $1\sdram_master_p0_bank[1:0] end - attribute \src "ls180.v:596.5-596.51" - process $proc$ls180.v:596$3305 + attribute \src "ls180.v:2993.1-3011.4" + process $proc$ls180.v:2993$620 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign { } { } + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [0] \gpio0_pads_gpio0o [0] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [1] \gpio0_pads_gpio0o [1] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [2] \gpio0_pads_gpio0o [2] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [3] \gpio0_pads_gpio0o [3] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [4] \gpio0_pads_gpio0o [4] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [5] \gpio0_pads_gpio0o [5] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [6] \gpio0_pads_gpio0o [6] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [7] \gpio0_pads_gpio0o [7] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [8] \gpio1_pads_gpio1o [0] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [9] \gpio1_pads_gpio1o [1] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [10] \gpio1_pads_gpio1o [2] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [11] \gpio1_pads_gpio1o [3] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [12] \gpio1_pads_gpio1o [4] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [13] \gpio1_pads_gpio1o [5] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [14] \gpio1_pads_gpio1o [6] + assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [15] \gpio1_pads_gpio1o [7] sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + update \libresocsim_libresoc_constraintmanager_gpio_o $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] end - attribute \src "ls180.v:597.5-597.50" - process $proc$ls180.v:597$3306 + attribute \src "ls180.v:300.5-300.33" + process $proc$ls180.v:300$1646 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $1\sdram_master_p0_cas_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + update \sdram_master_p0_cas_n $1\sdram_master_p0_cas_n[0:0] end - attribute \src "ls180.v:598.5-598.54" - process $proc$ls180.v:598$3307 + attribute \src "ls180.v:301.5-301.32" + process $proc$ls180.v:301$1647 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $1\sdram_master_p0_cs_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \sdram_master_p0_cs_n $1\sdram_master_p0_cs_n[0:0] end - attribute \src "ls180.v:599.5-599.55" - process $proc$ls180.v:599$3308 + attribute \src "ls180.v:3012.1-3030.4" + process $proc$ls180.v:3012$621 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign { } { } + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [0] \gpio0_pads_gpio0oe [0] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [1] \gpio0_pads_gpio0oe [1] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [2] \gpio0_pads_gpio0oe [2] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [3] \gpio0_pads_gpio0oe [3] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [4] \gpio0_pads_gpio0oe [4] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [5] \gpio0_pads_gpio0oe [5] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [6] \gpio0_pads_gpio0oe [6] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [7] \gpio0_pads_gpio0oe [7] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [8] \gpio1_pads_gpio1oe [0] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [9] \gpio1_pads_gpio1oe [1] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [10] \gpio1_pads_gpio1oe [2] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [11] \gpio1_pads_gpio1oe [3] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [12] \gpio1_pads_gpio1oe [4] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [13] \gpio1_pads_gpio1oe [5] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [14] \gpio1_pads_gpio1oe [6] + assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [15] \gpio1_pads_gpio1oe [7] sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + update \libresocsim_libresoc_constraintmanager_gpio_oe $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] end - attribute \src "ls180.v:600.5-600.56" - process $proc$ls180.v:600$3309 + attribute \src "ls180.v:302.5-302.33" + process $proc$ls180.v:302$1648 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $1\sdram_master_p0_ras_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + update \sdram_master_p0_ras_n $1\sdram_master_p0_ras_n[0:0] end - attribute \src "ls180.v:601.5-601.50" - process $proc$ls180.v:601$3310 + attribute \src "ls180.v:303.5-303.32" + process $proc$ls180.v:303$1649 assign { } { } - assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + assign $1\sdram_master_p0_we_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + update \sdram_master_p0_we_n $1\sdram_master_p0_we_n[0:0] end - attribute \src "ls180.v:6031.1-6042.4" - process $proc$ls180.v:6031$1241 + attribute \src "ls180.v:3035.1-3071.4" + process $proc$ls180.v:3035$622 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\builder_error[0:0] 1'0 - assign $0\builder_shared_ack[0:0] $or$ls180.v:6035$1253_Y - assign $0\builder_shared_dat_r[31:0] $or$ls180.v:6036$1278_Y [31:0] - attribute \src "ls180.v:6037.2-6041.5" - switch \builder_done - attribute \src "ls180.v:6037.6-6037.18" - case 1'1 - assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 - assign $0\builder_shared_ack[0:0] 1'1 - assign $0\builder_error[0:0] 1'1 - case - end - sync always - update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] - update \builder_shared_ack $0\builder_shared_ack[0:0] - update \builder_error $0\builder_error[0:0] - end - attribute \src "ls180.v:604.5-604.67" - process $proc$ls180.v:604$3311 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:605.5-605.66" - process $proc$ls180.v:605$3312 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:620.11-620.68" - process $proc$ls180.v:620$3313 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:621.5-621.64" - process $proc$ls180.v:621$3314 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:622.11-622.70" - process $proc$ls180.v:622$3315 + assign $0\libresocsim_libresocsim_wishbone_dat_r[31:0] 0 + assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0 + assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'0 + assign $0\libresocsim_libresocsim_wishbone_ack[0:0] 1'0 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] 8'00000000 + assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'0 + assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000 + assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'0 + assign $0\libresocsim_next_state[1:0] \libresocsim_state + attribute \src "ls180.v:3046.2-3070.9" + switch \libresocsim_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000 + assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'1 + assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0 + assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'1 + assign $0\libresocsim_next_state[1:0] 2'10 + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\libresocsim_libresocsim_wishbone_ack[0:0] 1'1 + assign $0\libresocsim_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \libresocsim_libresocsim_dat_r } + assign $0\libresocsim_next_state[1:0] 2'00 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] \libresocsim_libresocsim_wishbone_dat_w [7:0] + assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:3062.4-3068.7" + switch $and$ls180.v:3062$623_Y + attribute \src "ls180.v:3062.8-3062.85" + case 1'1 + assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] \libresocsim_libresocsim_wishbone_adr [13:0] + assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'1 + assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] $and$ls180.v:3065$625_Y + assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'1 + assign $0\libresocsim_next_state[1:0] 2'01 + case + end + end sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \libresocsim_libresocsim_wishbone_dat_r $0\libresocsim_libresocsim_wishbone_dat_r[31:0] + update \libresocsim_libresocsim_wishbone_ack $0\libresocsim_libresocsim_wishbone_ack[0:0] + update \libresocsim_next_state $0\libresocsim_next_state[1:0] + update \libresocsim_libresocsim_dat_w_libresocsim_next_value0 $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] + update \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] + update \libresocsim_libresocsim_adr_libresocsim_next_value1 $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] + update \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] + update \libresocsim_libresocsim_we_libresocsim_next_value2 $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] + update \libresocsim_libresocsim_we_libresocsim_next_value_ce2 $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] end - attribute \src "ls180.v:623.11-623.70" - process $proc$ls180.v:623$3316 + attribute \src "ls180.v:304.5-304.31" + process $proc$ls180.v:304$1650 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\sdram_master_p0_cke[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \sdram_master_p0_cke $1\sdram_master_p0_cke[0:0] end - attribute \src "ls180.v:624.11-624.73" - process $proc$ls180.v:624$3317 + attribute \src "ls180.v:305.5-305.31" + process $proc$ls180.v:305$1651 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\sdram_master_p0_odt[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + update \sdram_master_p0_odt $1\sdram_master_p0_odt[0:0] end - attribute \src "ls180.v:63.12-63.47" - process $proc$ls180.v:63$3132 + attribute \src "ls180.v:306.5-306.35" + process $proc$ls180.v:306$1652 assign { } { } - assign $1\main_libresocsim_bus_errors[31:0] 0 + assign $1\sdram_master_p0_reset_n[0:0] 1'0 sync always sync init - update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] + update \sdram_master_p0_reset_n $1\sdram_master_p0_reset_n[0:0] end - attribute \src "ls180.v:645.5-645.59" - process $proc$ls180.v:645$3318 + attribute \src "ls180.v:307.5-307.33" + process $proc$ls180.v:307$1653 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $1\sdram_master_p0_act_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \sdram_master_p0_act_n $1\sdram_master_p0_act_n[0:0] end - attribute \src "ls180.v:647.5-647.59" - process $proc$ls180.v:647$3319 + attribute \src "ls180.v:308.12-308.42" + process $proc$ls180.v:308$1654 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + assign $1\sdram_master_p0_wrdata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \sdram_master_p0_wrdata $1\sdram_master_p0_wrdata[15:0] end - attribute \src "ls180.v:648.5-648.58" - process $proc$ls180.v:648$3320 + attribute \src "ls180.v:309.5-309.37" + process $proc$ls180.v:309$1655 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + assign $1\sdram_master_p0_wrdata_en[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + update \sdram_master_p0_wrdata_en $1\sdram_master_p0_wrdata_en[0:0] end - attribute \src "ls180.v:649.5-649.64" - process $proc$ls180.v:649$3321 + attribute \src "ls180.v:3090.1-3098.4" + process $proc$ls180.v:3090$638 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:65.12-65.55" - process $proc$ls180.v:65$3133 assign { } { } - assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + assign $0\libresocsim_slave_sel[5:0] [0] $eq$ls180.v:3092$639_Y + assign $0\libresocsim_slave_sel[5:0] [1] $eq$ls180.v:3093$640_Y + assign $0\libresocsim_slave_sel[5:0] [2] $eq$ls180.v:3094$641_Y + assign $0\libresocsim_slave_sel[5:0] [3] $eq$ls180.v:3095$642_Y + assign $0\libresocsim_slave_sel[5:0] [4] $eq$ls180.v:3096$643_Y + assign $0\libresocsim_slave_sel[5:0] [5] $eq$ls180.v:3097$644_Y sync always - sync init - update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + update \libresocsim_slave_sel $0\libresocsim_slave_sel[5:0] end - attribute \src "ls180.v:650.12-650.74" - process $proc$ls180.v:650$3322 + attribute \src "ls180.v:310.11-310.45" + process $proc$ls180.v:310$1656 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + assign $1\sdram_master_p0_wrdata_mask[1:0] 2'00 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + update \sdram_master_p0_wrdata_mask $1\sdram_master_p0_wrdata_mask[1:0] end - attribute \src "ls180.v:651.12-651.47" - process $proc$ls180.v:651$3323 + attribute \src "ls180.v:311.5-311.37" + process $proc$ls180.v:311$1657 assign { } { } - assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $1\sdram_master_p0_rddata_en[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] + update \sdram_master_p0_rddata_en $1\sdram_master_p0_rddata_en[0:0] end - attribute \src "ls180.v:652.5-652.46" - process $proc$ls180.v:652$3324 + attribute \src "ls180.v:3149.1-3160.4" + process $proc$ls180.v:3149$659 assign { } { } - assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] - end - attribute \src "ls180.v:654.5-654.44" - process $proc$ls180.v:654$3325 assign { } { } - assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] - end - attribute \src "ls180.v:655.5-655.45" - process $proc$ls180.v:655$3326 assign { } { } - assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] - end - attribute \src "ls180.v:6556.1-6561.4" - process $proc$ls180.v:6556$2152 + assign $0\libresocsim_error[0:0] 1'0 + assign { } { } assign { } { } - assign $0\main_spimaster9_start[0:0] 1'0 - attribute \src "ls180.v:6558.2-6560.5" - switch \main_spimaster12_re - attribute \src "ls180.v:6558.6-6558.25" + assign $0\libresocsim_shared_ack[0:0] $or$ls180.v:3153$664_Y + assign $0\libresocsim_shared_dat_r[31:0] $or$ls180.v:3154$675_Y + attribute \src "ls180.v:3155.2-3159.5" + switch \libresocsim_done + attribute \src "ls180.v:3155.6-3155.22" case 1'1 - assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] + assign $0\libresocsim_shared_dat_r[31:0] 32'11111111111111111111111111111111 + assign $0\libresocsim_shared_ack[0:0] 1'1 + assign $0\libresocsim_error[0:0] 1'1 case end sync always - update \main_spimaster9_start $0\main_spimaster9_start[0:0] - end - attribute \src "ls180.v:656.5-656.54" - process $proc$ls180.v:656$3327 - assign { } { } - assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:658.32-658.76" - process $proc$ls180.v:658$3328 - assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + update \libresocsim_shared_dat_r $0\libresocsim_shared_dat_r[31:0] + update \libresocsim_shared_ack $0\libresocsim_shared_ack[0:0] + update \libresocsim_error $0\libresocsim_error[0:0] end - attribute \src "ls180.v:659.11-659.55" - process $proc$ls180.v:659$3329 + attribute \src "ls180.v:318.11-318.31" + process $proc$ls180.v:318$1658 assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $1\sdram_storage[3:0] 4'0001 sync always sync init - update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] - end - attribute \src "ls180.v:6602.1-6607.4" - process $proc$ls180.v:6602$2217 - assign { } { } - assign $0\main_spisdcard_start1[0:0] 1'0 - attribute \src "ls180.v:6604.2-6606.5" - switch \main_spisdcard_control_re - attribute \src "ls180.v:6604.6-6604.31" - case 1'1 - assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] - case - end - sync always - update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] + update \sdram_storage $1\sdram_storage[3:0] end - attribute \src "ls180.v:661.32-661.75" - process $proc$ls180.v:661$3330 + attribute \src "ls180.v:319.5-319.20" + process $proc$ls180.v:319$1659 assign { } { } - assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + assign $1\sdram_re[0:0] 1'0 sync always - update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] sync init + update \sdram_re $1\sdram_re[0:0] end - attribute \src "ls180.v:663.32-663.76" - process $proc$ls180.v:663$3331 + attribute \src "ls180.v:320.11-320.39" + process $proc$ls180.v:320$1660 assign { } { } - assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + assign $1\sdram_command_storage[5:0] 6'000000 sync always - update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] sync init + update \sdram_command_storage $1\sdram_command_storage[5:0] end - attribute \src "ls180.v:669.5-669.51" - process $proc$ls180.v:669$3332 + attribute \src "ls180.v:321.5-321.28" + process $proc$ls180.v:321$1661 assign { } { } - assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $1\sdram_command_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + update \sdram_command_re $1\sdram_command_re[0:0] end - attribute \src "ls180.v:670.5-670.51" - process $proc$ls180.v:670$3333 + attribute \src "ls180.v:325.5-325.33" + process $proc$ls180.v:325$1662 assign { } { } - assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign $0\sdram_command_issue_w[0:0] 1'0 sync always + update \sdram_command_issue_w $0\sdram_command_issue_w[0:0] sync init - update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] end - attribute \src "ls180.v:672.5-672.47" - process $proc$ls180.v:672$3334 + attribute \src "ls180.v:326.12-326.41" + process $proc$ls180.v:326$1663 assign { } { } - assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $1\sdram_address_storage[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] + update \sdram_address_storage $1\sdram_address_storage[12:0] end - attribute \src "ls180.v:673.5-673.45" - process $proc$ls180.v:673$3335 + attribute \src "ls180.v:327.5-327.28" + process $proc$ls180.v:327$1664 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign $1\sdram_address_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] + update \sdram_address_re $1\sdram_address_re[0:0] end - attribute \src "ls180.v:674.5-674.45" - process $proc$ls180.v:674$3336 + attribute \src "ls180.v:328.11-328.40" + process $proc$ls180.v:328$1665 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + assign $1\sdram_baddress_storage[1:0] 2'00 sync always sync init - update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] + update \sdram_baddress_storage $1\sdram_baddress_storage[1:0] end - attribute \src "ls180.v:675.12-675.57" - process $proc$ls180.v:675$3337 + attribute \src "ls180.v:329.5-329.29" + process $proc$ls180.v:329$1666 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + assign $1\sdram_baddress_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + update \sdram_baddress_re $1\sdram_baddress_re[0:0] end - attribute \src "ls180.v:677.5-677.51" - process $proc$ls180.v:677$3338 + attribute \src "ls180.v:330.12-330.40" + process $proc$ls180.v:330$1667 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $1\sdram_wrdata_storage[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + update \sdram_wrdata_storage $1\sdram_wrdata_storage[15:0] end - attribute \src "ls180.v:678.5-678.51" - process $proc$ls180.v:678$3339 + attribute \src "ls180.v:331.5-331.27" + process $proc$ls180.v:331$1668 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $1\sdram_wrdata_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + update \sdram_wrdata_re $1\sdram_wrdata_re[0:0] end - attribute \src "ls180.v:679.5-679.50" - process $proc$ls180.v:679$3340 + attribute \src "ls180.v:332.12-332.32" + process $proc$ls180.v:332$1669 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $1\sdram_status[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + update \sdram_status $1\sdram_status[15:0] end - attribute \src "ls180.v:6791.1-6807.4" - process $proc$ls180.v:6791$2438 + attribute \src "ls180.v:3435.1-3451.4" + process $proc$ls180.v:3435$1084 assign { } { } - assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6793.2-6806.9" - switch \main_sdram_choose_cmd_grant + assign $0\rhs_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:3437.2-3450.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] + assign $0\rhs_array_muxed0[0:0] \sdram_choose_cmd_valids [0] attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] + assign $0\rhs_array_muxed0[0:0] \sdram_choose_cmd_valids [1] attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] + assign $0\rhs_array_muxed0[0:0] \sdram_choose_cmd_valids [2] attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] + assign $0\rhs_array_muxed0[0:0] \sdram_choose_cmd_valids [3] end sync always - update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] - end - attribute \src "ls180.v:680.5-680.54" - process $proc$ls180.v:680$3341 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + update \rhs_array_muxed0 $0\rhs_array_muxed0[0:0] end - attribute \src "ls180.v:6808.1-6824.4" - process $proc$ls180.v:6808$2439 + attribute \src "ls180.v:3452.1-3468.4" + process $proc$ls180.v:3452$1085 assign { } { } - assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:6810.2-6823.9" - switch \main_sdram_choose_cmd_grant + assign $0\rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:3454.2-3467.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a + assign $0\rhs_array_muxed1[12:0] \sdram_bankmachine0_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a + assign $0\rhs_array_muxed1[12:0] \sdram_bankmachine1_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a + assign $0\rhs_array_muxed1[12:0] \sdram_bankmachine2_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a + assign $0\rhs_array_muxed1[12:0] \sdram_bankmachine3_cmd_payload_a end sync always - update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:681.5-681.55" - process $proc$ls180.v:681$3342 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:682.5-682.56" - process $proc$ls180.v:682$3343 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + update \rhs_array_muxed1 $0\rhs_array_muxed1[12:0] end - attribute \src "ls180.v:6825.1-6841.4" - process $proc$ls180.v:6825$2440 + attribute \src "ls180.v:3469.1-3485.4" + process $proc$ls180.v:3469$1086 assign { } { } - assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 - attribute \src "ls180.v:6827.2-6840.9" - switch \main_sdram_choose_cmd_grant + assign $0\rhs_array_muxed2[1:0] 2'00 + attribute \src "ls180.v:3471.2-3484.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba + assign $0\rhs_array_muxed2[1:0] \sdram_bankmachine0_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba + assign $0\rhs_array_muxed2[1:0] \sdram_bankmachine1_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba + assign $0\rhs_array_muxed2[1:0] \sdram_bankmachine2_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba + assign $0\rhs_array_muxed2[1:0] \sdram_bankmachine3_cmd_payload_ba end sync always - update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] + update \rhs_array_muxed2 $0\rhs_array_muxed2[1:0] end - attribute \src "ls180.v:683.5-683.50" - process $proc$ls180.v:683$3344 + attribute \src "ls180.v:3486.1-3502.4" + process $proc$ls180.v:3486$1087 assign { } { } - assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] - end - attribute \src "ls180.v:6842.1-6858.4" - process $proc$ls180.v:6842$2441 - assign { } { } - assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6844.2-6857.9" - switch \main_sdram_choose_cmd_grant + assign $0\rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:3488.2-3501.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + assign $0\rhs_array_muxed3[0:0] \sdram_bankmachine0_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + assign $0\rhs_array_muxed3[0:0] \sdram_bankmachine1_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + assign $0\rhs_array_muxed3[0:0] \sdram_bankmachine2_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + assign $0\rhs_array_muxed3[0:0] \sdram_bankmachine3_cmd_payload_is_read end sync always - update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] + update \rhs_array_muxed3 $0\rhs_array_muxed3[0:0] end - attribute \src "ls180.v:6859.1-6875.4" - process $proc$ls180.v:6859$2442 + attribute \src "ls180.v:3503.1-3519.4" + process $proc$ls180.v:3503$1088 assign { } { } - assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6861.2-6874.9" - switch \main_sdram_choose_cmd_grant + assign $0\rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:3505.2-3518.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + assign $0\rhs_array_muxed4[0:0] \sdram_bankmachine0_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + assign $0\rhs_array_muxed4[0:0] \sdram_bankmachine1_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + assign $0\rhs_array_muxed4[0:0] \sdram_bankmachine2_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + assign $0\rhs_array_muxed4[0:0] \sdram_bankmachine3_cmd_payload_is_write end sync always - update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:686.5-686.67" - process $proc$ls180.v:686$3345 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:687.5-687.66" - process $proc$ls180.v:687$3346 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - sync init + update \rhs_array_muxed4 $0\rhs_array_muxed4[0:0] end - attribute \src "ls180.v:6876.1-6892.4" - process $proc$ls180.v:6876$2443 + attribute \src "ls180.v:3520.1-3536.4" + process $proc$ls180.v:3520$1089 assign { } { } - assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6878.2-6891.9" - switch \main_sdram_choose_cmd_grant + assign $0\rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:3522.2-3535.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + assign $0\rhs_array_muxed5[0:0] \sdram_bankmachine0_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + assign $0\rhs_array_muxed5[0:0] \sdram_bankmachine1_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + assign $0\rhs_array_muxed5[0:0] \sdram_bankmachine2_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + assign $0\rhs_array_muxed5[0:0] \sdram_bankmachine3_cmd_payload_is_cmd end sync always - update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] + update \rhs_array_muxed5 $0\rhs_array_muxed5[0:0] end - attribute \src "ls180.v:6893.1-6909.4" - process $proc$ls180.v:6893$2444 + attribute \src "ls180.v:3537.1-3553.4" + process $proc$ls180.v:3537$1090 assign { } { } - assign $0\builder_comb_t_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6895.2-6908.9" - switch \main_sdram_choose_cmd_grant + assign $0\t_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:3539.2-3552.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas + assign $0\t_array_muxed0[0:0] \sdram_bankmachine0_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas + assign $0\t_array_muxed0[0:0] \sdram_bankmachine1_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas + assign $0\t_array_muxed0[0:0] \sdram_bankmachine2_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas + assign $0\t_array_muxed0[0:0] \sdram_bankmachine3_cmd_payload_cas end sync always - update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] + update \t_array_muxed0 $0\t_array_muxed0[0:0] end - attribute \src "ls180.v:6910.1-6926.4" - process $proc$ls180.v:6910$2445 + attribute \src "ls180.v:3554.1-3570.4" + process $proc$ls180.v:3554$1091 assign { } { } - assign $0\builder_comb_t_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:6912.2-6925.9" - switch \main_sdram_choose_cmd_grant + assign $0\t_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:3556.2-3569.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras + assign $0\t_array_muxed1[0:0] \sdram_bankmachine0_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras + assign $0\t_array_muxed1[0:0] \sdram_bankmachine1_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras + assign $0\t_array_muxed1[0:0] \sdram_bankmachine2_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras + assign $0\t_array_muxed1[0:0] \sdram_bankmachine3_cmd_payload_ras end sync always - update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] + update \t_array_muxed1 $0\t_array_muxed1[0:0] end - attribute \src "ls180.v:6927.1-6943.4" - process $proc$ls180.v:6927$2446 + attribute \src "ls180.v:3571.1-3587.4" + process $proc$ls180.v:3571$1092 assign { } { } - assign $0\builder_comb_t_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:6929.2-6942.9" - switch \main_sdram_choose_cmd_grant + assign $0\t_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:3573.2-3586.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we + assign $0\t_array_muxed2[0:0] \sdram_bankmachine0_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we + assign $0\t_array_muxed2[0:0] \sdram_bankmachine1_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we + assign $0\t_array_muxed2[0:0] \sdram_bankmachine2_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we + assign $0\t_array_muxed2[0:0] \sdram_bankmachine3_cmd_payload_we end sync always - update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] + update \t_array_muxed2 $0\t_array_muxed2[0:0] end - attribute \src "ls180.v:6944.1-6960.4" - process $proc$ls180.v:6944$2447 + attribute \src "ls180.v:3588.1-3604.4" + process $proc$ls180.v:3588$1093 assign { } { } - assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:6946.2-6959.9" - switch \main_sdram_choose_req_grant + assign $0\rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:3590.2-3603.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] + assign $0\rhs_array_muxed6[0:0] \sdram_choose_req_valids [0] attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] + assign $0\rhs_array_muxed6[0:0] \sdram_choose_req_valids [1] attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] + assign $0\rhs_array_muxed6[0:0] \sdram_choose_req_valids [2] attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] + assign $0\rhs_array_muxed6[0:0] \sdram_choose_req_valids [3] end sync always - update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] + update \rhs_array_muxed6 $0\rhs_array_muxed6[0:0] end - attribute \src "ls180.v:6961.1-6977.4" - process $proc$ls180.v:6961$2448 + attribute \src "ls180.v:3605.1-3621.4" + process $proc$ls180.v:3605$1094 assign { } { } - assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - attribute \src "ls180.v:6963.2-6976.9" - switch \main_sdram_choose_req_grant + assign $0\rhs_array_muxed7[12:0] 13'0000000000000 + attribute \src "ls180.v:3607.2-3620.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a + assign $0\rhs_array_muxed7[12:0] \sdram_bankmachine0_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a + assign $0\rhs_array_muxed7[12:0] \sdram_bankmachine1_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a + assign $0\rhs_array_muxed7[12:0] \sdram_bankmachine2_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a + assign $0\rhs_array_muxed7[12:0] \sdram_bankmachine3_cmd_payload_a end sync always - update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] + update \rhs_array_muxed7 $0\rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:362.12-362.41" + process $proc$ls180.v:362$1670 + assign { } { } + assign $1\sdram_interface_wdata[15:0] 16'0000000000000000 + sync always + sync init + update \sdram_interface_wdata $1\sdram_interface_wdata[15:0] end - attribute \src "ls180.v:6978.1-6994.4" - process $proc$ls180.v:6978$2449 + attribute \src "ls180.v:3622.1-3638.4" + process $proc$ls180.v:3622$1095 assign { } { } - assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 - attribute \src "ls180.v:6980.2-6993.9" - switch \main_sdram_choose_req_grant + assign $0\rhs_array_muxed8[1:0] 2'00 + attribute \src "ls180.v:3624.2-3637.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba + assign $0\rhs_array_muxed8[1:0] \sdram_bankmachine0_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba + assign $0\rhs_array_muxed8[1:0] \sdram_bankmachine1_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba + assign $0\rhs_array_muxed8[1:0] \sdram_bankmachine2_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba + assign $0\rhs_array_muxed8[1:0] \sdram_bankmachine3_cmd_payload_ba end sync always - update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] + update \rhs_array_muxed8 $0\rhs_array_muxed8[1:0] end - attribute \src "ls180.v:6995.1-7011.4" - process $proc$ls180.v:6995$2450 + attribute \src "ls180.v:363.11-363.42" + process $proc$ls180.v:363$1671 assign { } { } - assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 - attribute \src "ls180.v:6997.2-7010.9" - switch \main_sdram_choose_req_grant + assign $1\sdram_interface_wdata_we[1:0] 2'00 + sync always + sync init + update \sdram_interface_wdata_we $1\sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:3639.1-3655.4" + process $proc$ls180.v:3639$1096 + assign { } { } + assign $0\rhs_array_muxed9[0:0] 1'0 + attribute \src "ls180.v:3641.2-3654.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + assign $0\rhs_array_muxed9[0:0] \sdram_bankmachine0_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + assign $0\rhs_array_muxed9[0:0] \sdram_bankmachine1_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + assign $0\rhs_array_muxed9[0:0] \sdram_bankmachine2_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + assign $0\rhs_array_muxed9[0:0] \sdram_bankmachine3_cmd_payload_is_read end sync always - update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] + update \rhs_array_muxed9 $0\rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:365.12-365.40" + process $proc$ls180.v:365$1672 + assign { } { } + assign $1\sdram_dfi_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \sdram_dfi_p0_address $1\sdram_dfi_p0_address[12:0] end - attribute \src "ls180.v:7012.1-7028.4" - process $proc$ls180.v:7012$2451 + attribute \src "ls180.v:3656.1-3672.4" + process $proc$ls180.v:3656$1097 assign { } { } - assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 - attribute \src "ls180.v:7014.2-7027.9" - switch \main_sdram_choose_req_grant + assign $0\rhs_array_muxed10[0:0] 1'0 + attribute \src "ls180.v:3658.2-3671.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + assign $0\rhs_array_muxed10[0:0] \sdram_bankmachine0_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + assign $0\rhs_array_muxed10[0:0] \sdram_bankmachine1_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + assign $0\rhs_array_muxed10[0:0] \sdram_bankmachine2_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + assign $0\rhs_array_muxed10[0:0] \sdram_bankmachine3_cmd_payload_is_write end sync always - update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] + update \rhs_array_muxed10 $0\rhs_array_muxed10[0:0] end - attribute \src "ls180.v:702.11-702.68" - process $proc$ls180.v:702$3347 + attribute \src "ls180.v:366.11-366.35" + process $proc$ls180.v:366$1673 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\sdram_dfi_p0_bank[1:0] 2'00 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + update \sdram_dfi_p0_bank $1\sdram_dfi_p0_bank[1:0] end - attribute \src "ls180.v:7029.1-7045.4" - process $proc$ls180.v:7029$2452 + attribute \src "ls180.v:367.5-367.30" + process $proc$ls180.v:367$1674 assign { } { } - assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 - attribute \src "ls180.v:7031.2-7044.9" - switch \main_sdram_choose_req_grant + assign $1\sdram_dfi_p0_cas_n[0:0] 1'1 + sync always + sync init + update \sdram_dfi_p0_cas_n $1\sdram_dfi_p0_cas_n[0:0] + end + attribute \src "ls180.v:3673.1-3689.4" + process $proc$ls180.v:3673$1098 + assign { } { } + assign $0\rhs_array_muxed11[0:0] 1'0 + attribute \src "ls180.v:3675.2-3688.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + assign $0\rhs_array_muxed11[0:0] \sdram_bankmachine0_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + assign $0\rhs_array_muxed11[0:0] \sdram_bankmachine1_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + assign $0\rhs_array_muxed11[0:0] \sdram_bankmachine2_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + assign $0\rhs_array_muxed11[0:0] \sdram_bankmachine3_cmd_payload_is_cmd end sync always - update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] + update \rhs_array_muxed11 $0\rhs_array_muxed11[0:0] end - attribute \src "ls180.v:703.5-703.64" - process $proc$ls180.v:703$3348 + attribute \src "ls180.v:368.5-368.29" + process $proc$ls180.v:368$1675 assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\sdram_dfi_p0_cs_n[0:0] 1'1 sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] sync init + update \sdram_dfi_p0_cs_n $1\sdram_dfi_p0_cs_n[0:0] end - attribute \src "ls180.v:704.11-704.70" - process $proc$ls180.v:704$3349 + attribute \src "ls180.v:369.5-369.30" + process $proc$ls180.v:369$1676 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\sdram_dfi_p0_ras_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + update \sdram_dfi_p0_ras_n $1\sdram_dfi_p0_ras_n[0:0] end - attribute \src "ls180.v:7046.1-7062.4" - process $proc$ls180.v:7046$2453 + attribute \src "ls180.v:3690.1-3706.4" + process $proc$ls180.v:3690$1099 assign { } { } - assign $0\builder_comb_t_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7048.2-7061.9" - switch \main_sdram_choose_req_grant + assign $0\t_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:3692.2-3705.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas + assign $0\t_array_muxed3[0:0] \sdram_bankmachine0_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas + assign $0\t_array_muxed3[0:0] \sdram_bankmachine1_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas + assign $0\t_array_muxed3[0:0] \sdram_bankmachine2_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas + assign $0\t_array_muxed3[0:0] \sdram_bankmachine3_cmd_payload_cas end sync always - update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] - end - attribute \src "ls180.v:705.11-705.70" - process $proc$ls180.v:705$3350 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + update \t_array_muxed3 $0\t_array_muxed3[0:0] end - attribute \src "ls180.v:706.11-706.73" - process $proc$ls180.v:706$3351 + attribute \src "ls180.v:370.5-370.29" + process $proc$ls180.v:370$1677 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\sdram_dfi_p0_we_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + update \sdram_dfi_p0_we_n $1\sdram_dfi_p0_we_n[0:0] end - attribute \src "ls180.v:7063.1-7079.4" - process $proc$ls180.v:7063$2454 + attribute \src "ls180.v:3707.1-3723.4" + process $proc$ls180.v:3707$1100 assign { } { } - assign $0\builder_comb_t_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7065.2-7078.9" - switch \main_sdram_choose_req_grant + assign $0\t_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:3709.2-3722.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras + assign $0\t_array_muxed4[0:0] \sdram_bankmachine0_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras + assign $0\t_array_muxed4[0:0] \sdram_bankmachine1_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras + assign $0\t_array_muxed4[0:0] \sdram_bankmachine2_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras + assign $0\t_array_muxed4[0:0] \sdram_bankmachine3_cmd_payload_ras end sync always - update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] + update \t_array_muxed4 $0\t_array_muxed4[0:0] end - attribute \src "ls180.v:7080.1-7096.4" - process $proc$ls180.v:7080$2455 + attribute \src "ls180.v:3724.1-3740.4" + process $proc$ls180.v:3724$1101 assign { } { } - assign $0\builder_comb_t_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7082.2-7095.9" - switch \main_sdram_choose_req_grant + assign $0\t_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:3726.2-3739.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we + assign $0\t_array_muxed5[0:0] \sdram_bankmachine0_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we + assign $0\t_array_muxed5[0:0] \sdram_bankmachine1_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we + assign $0\t_array_muxed5[0:0] \sdram_bankmachine2_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we + assign $0\t_array_muxed5[0:0] \sdram_bankmachine3_cmd_payload_we end sync always - update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] + update \t_array_muxed5 $0\t_array_muxed5[0:0] end - attribute \src "ls180.v:7097.1-7104.4" - process $proc$ls180.v:7097$2456 + attribute \src "ls180.v:374.5-374.30" + process $proc$ls180.v:374$1678 assign { } { } - assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7099.2-7103.9" - switch \builder_roundrobin0_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end + assign $0\sdram_dfi_p0_act_n[0:0] 1'1 sync always - update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] + update \sdram_dfi_p0_act_n $0\sdram_dfi_p0_act_n[0:0] + sync init end - attribute \src "ls180.v:7105.1-7112.4" - process $proc$ls180.v:7105$2457 + attribute \src "ls180.v:3741.1-3748.4" + process $proc$ls180.v:3741$1102 assign { } { } - assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 - attribute \src "ls180.v:7107.2-7111.9" - switch \builder_roundrobin0_grant + assign $0\rhs_array_muxed12[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:3743.2-3747.9" + switch \subfragments_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we + assign $0\rhs_array_muxed12[21:0] { \port_cmd_payload_addr [23:11] \port_cmd_payload_addr [8:0] } end sync always - update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] + update \rhs_array_muxed12 $0\rhs_array_muxed12[21:0] end - attribute \src "ls180.v:7113.1-7120.4" - process $proc$ls180.v:7113$2458 + attribute \src "ls180.v:3749.1-3756.4" + process $proc$ls180.v:3749$1103 assign { } { } - assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 - attribute \src "ls180.v:7115.2-7119.9" - switch \builder_roundrobin0_grant + assign $0\rhs_array_muxed13[0:0] 1'0 + attribute \src "ls180.v:3751.2-3755.9" + switch \subfragments_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:7117$2471_Y + assign $0\rhs_array_muxed13[0:0] \port_cmd_payload_we end sync always - update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] + update \rhs_array_muxed13 $0\rhs_array_muxed13[0:0] end - attribute \src "ls180.v:7121.1-7128.4" - process $proc$ls180.v:7121$2472 + attribute \src "ls180.v:3757.1-3764.4" + process $proc$ls180.v:3757$1104 assign { } { } - assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7123.2-7127.9" - switch \builder_roundrobin1_grant + assign $0\rhs_array_muxed14[0:0] 1'0 + attribute \src "ls180.v:3759.2-3763.9" + switch \subfragments_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + assign $0\rhs_array_muxed14[0:0] $and$ls180.v:3761$1117_Y end sync always - update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] + update \rhs_array_muxed14 $0\rhs_array_muxed14[0:0] end - attribute \src "ls180.v:7129.1-7136.4" - process $proc$ls180.v:7129$2473 + attribute \src "ls180.v:376.5-376.34" + process $proc$ls180.v:376$1679 assign { } { } - assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 - attribute \src "ls180.v:7131.2-7135.9" - switch \builder_roundrobin1_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we - end + assign $1\sdram_dfi_p0_wrdata_en[0:0] 1'0 sync always - update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] + sync init + update \sdram_dfi_p0_wrdata_en $1\sdram_dfi_p0_wrdata_en[0:0] end - attribute \src "ls180.v:7137.1-7144.4" - process $proc$ls180.v:7137$2474 + attribute \src "ls180.v:3765.1-3772.4" + process $proc$ls180.v:3765$1118 assign { } { } - assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 - attribute \src "ls180.v:7139.2-7143.9" - switch \builder_roundrobin1_grant + assign $0\rhs_array_muxed15[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:3767.2-3771.9" + switch \subfragments_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:7141$2487_Y + assign $0\rhs_array_muxed15[21:0] { \port_cmd_payload_addr [23:11] \port_cmd_payload_addr [8:0] } end sync always - update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] + update \rhs_array_muxed15 $0\rhs_array_muxed15[21:0] end - attribute \src "ls180.v:7145.1-7152.4" - process $proc$ls180.v:7145$2488 + attribute \src "ls180.v:3773.1-3780.4" + process $proc$ls180.v:3773$1119 assign { } { } - assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7147.2-7151.9" - switch \builder_roundrobin2_grant + assign $0\rhs_array_muxed16[0:0] 1'0 + attribute \src "ls180.v:3775.2-3779.9" + switch \subfragments_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + assign $0\rhs_array_muxed16[0:0] \port_cmd_payload_we end sync always - update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] + update \rhs_array_muxed16 $0\rhs_array_muxed16[0:0] end - attribute \src "ls180.v:7153.1-7160.4" - process $proc$ls180.v:7153$2489 + attribute \src "ls180.v:378.5-378.34" + process $proc$ls180.v:378$1680 assign { } { } - assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 - attribute \src "ls180.v:7155.2-7159.9" - switch \builder_roundrobin2_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we - end + assign $1\sdram_dfi_p0_rddata_en[0:0] 1'0 sync always - update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] + sync init + update \sdram_dfi_p0_rddata_en $1\sdram_dfi_p0_rddata_en[0:0] end - attribute \src "ls180.v:7161.1-7168.4" - process $proc$ls180.v:7161$2490 + attribute \src "ls180.v:3781.1-3788.4" + process $proc$ls180.v:3781$1120 assign { } { } - assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 - attribute \src "ls180.v:7163.2-7167.9" - switch \builder_roundrobin2_grant + assign $0\rhs_array_muxed17[0:0] 1'0 + attribute \src "ls180.v:3783.2-3787.9" + switch \subfragments_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:7165$2503_Y + assign $0\rhs_array_muxed17[0:0] $and$ls180.v:3785$1133_Y end sync always - update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] + update \rhs_array_muxed17 $0\rhs_array_muxed17[0:0] end - attribute \src "ls180.v:7169.1-7176.4" - process $proc$ls180.v:7169$2504 + attribute \src "ls180.v:3789.1-3796.4" + process $proc$ls180.v:3789$1134 assign { } { } - assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7171.2-7175.9" - switch \builder_roundrobin3_grant + assign $0\rhs_array_muxed18[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:3791.2-3795.9" + switch \subfragments_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + assign $0\rhs_array_muxed18[21:0] { \port_cmd_payload_addr [23:11] \port_cmd_payload_addr [8:0] } end sync always - update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] + update \rhs_array_muxed18 $0\rhs_array_muxed18[21:0] end - attribute \src "ls180.v:7177.1-7184.4" - process $proc$ls180.v:7177$2505 + attribute \src "ls180.v:3797.1-3804.4" + process $proc$ls180.v:3797$1135 assign { } { } - assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 - attribute \src "ls180.v:7179.2-7183.9" - switch \builder_roundrobin3_grant + assign $0\rhs_array_muxed19[0:0] 1'0 + attribute \src "ls180.v:3799.2-3803.9" + switch \subfragments_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we + assign $0\rhs_array_muxed19[0:0] \port_cmd_payload_we end sync always - update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] + update \rhs_array_muxed19 $0\rhs_array_muxed19[0:0] end - attribute \src "ls180.v:7185.1-7192.4" - process $proc$ls180.v:7185$2506 + attribute \src "ls180.v:3805.1-3812.4" + process $proc$ls180.v:3805$1136 assign { } { } - assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 - attribute \src "ls180.v:7187.2-7191.9" - switch \builder_roundrobin3_grant + assign $0\rhs_array_muxed20[0:0] 1'0 + attribute \src "ls180.v:3807.2-3811.9" + switch \subfragments_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:7189$2519_Y + assign $0\rhs_array_muxed20[0:0] $and$ls180.v:3809$1149_Y end sync always - update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] + update \rhs_array_muxed20 $0\rhs_array_muxed20[0:0] end - attribute \src "ls180.v:7193.1-7212.4" - process $proc$ls180.v:7193$2520 + attribute \src "ls180.v:381.5-381.27" + process $proc$ls180.v:381$1681 assign { } { } - assign $0\builder_comb_rhs_array_muxed24[31:0] 0 - attribute \src "ls180.v:7195.2-7211.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_ibus_adr } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_dbus_adr } - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_jtag_wb_adr } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface1_bus_adr - end + assign $1\sdram_cmd_valid[0:0] 1'0 sync always - update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] + sync init + update \sdram_cmd_valid $1\sdram_cmd_valid[0:0] end - attribute \src "ls180.v:7213.1-7232.4" - process $proc$ls180.v:7213$2521 + attribute \src "ls180.v:3813.1-3820.4" + process $proc$ls180.v:3813$1150 assign { } { } - assign $0\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "ls180.v:7215.2-7231.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_ibus_dat_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_dbus_dat_w - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_jtag_wb_dat_w - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface0_bus_dat_w + assign $0\rhs_array_muxed21[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:3815.2-3819.9" + switch \subfragments_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface1_bus_dat_w + assign $0\rhs_array_muxed21[21:0] { \port_cmd_payload_addr [23:11] \port_cmd_payload_addr [8:0] } end sync always - update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[63:0] + update \rhs_array_muxed21 $0\rhs_array_muxed21[21:0] end - attribute \src "ls180.v:7233.1-7252.4" - process $proc$ls180.v:7233$2522 + attribute \src "ls180.v:382.5-382.27" + process $proc$ls180.v:382$1682 assign { } { } - assign $0\builder_comb_rhs_array_muxed26[7:0] 8'00000000 - attribute \src "ls180.v:7235.2-7251.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_ibus_sel - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_dbus_sel - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_jtag_wb_sel - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface0_bus_sel - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface1_bus_sel - end + assign $1\sdram_cmd_ready[0:0] 1'0 sync always - update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[7:0] + sync init + update \sdram_cmd_ready $1\sdram_cmd_ready[0:0] end - attribute \src "ls180.v:7253.1-7272.4" - process $proc$ls180.v:7253$2523 + attribute \src "ls180.v:3821.1-3828.4" + process $proc$ls180.v:3821$1151 assign { } { } - assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 - attribute \src "ls180.v:7255.2-7271.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_ibus_cyc - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_dbus_cyc - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_jtag_wb_cyc - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc + assign $0\rhs_array_muxed22[0:0] 1'0 + attribute \src "ls180.v:3823.2-3827.9" + switch \subfragments_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface1_bus_cyc + assign $0\rhs_array_muxed22[0:0] \port_cmd_payload_we end sync always - update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] - end - attribute \src "ls180.v:727.5-727.59" - process $proc$ls180.v:727$3352 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + update \rhs_array_muxed22 $0\rhs_array_muxed22[0:0] end - attribute \src "ls180.v:7273.1-7292.4" - process $proc$ls180.v:7273$2524 + attribute \src "ls180.v:3829.1-3836.4" + process $proc$ls180.v:3829$1152 assign { } { } - assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 - attribute \src "ls180.v:7275.2-7291.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_ibus_stb - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_dbus_stb - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_jtag_wb_stb - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb + assign $0\rhs_array_muxed23[0:0] 1'0 + attribute \src "ls180.v:3831.2-3835.9" + switch \subfragments_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface1_bus_stb + assign $0\rhs_array_muxed23[0:0] $and$ls180.v:3833$1165_Y end sync always - update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] + update \rhs_array_muxed23 $0\rhs_array_muxed23[0:0] end - attribute \src "ls180.v:729.5-729.59" - process $proc$ls180.v:729$3353 + attribute \src "ls180.v:383.5-383.26" + process $proc$ls180.v:383$1683 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + assign $1\sdram_cmd_last[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + update \sdram_cmd_last $1\sdram_cmd_last[0:0] end - attribute \src "ls180.v:7293.1-7312.4" - process $proc$ls180.v:7293$2525 + attribute \src "ls180.v:3837.1-3850.4" + process $proc$ls180.v:3837$1166 assign { } { } - assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 - attribute \src "ls180.v:7295.2-7311.9" - switch \builder_grant + assign $0\rhs_array_muxed24[29:0] 30'000000000000000000000000000000 + attribute \src "ls180.v:3839.2-3849.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_ibus_we - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_dbus_we - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_jtag_wb_we + case 2'00 + assign $0\rhs_array_muxed24[29:0] \libresocsim_interface0_converted_interface_adr attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we + case 2'01 + assign $0\rhs_array_muxed24[29:0] \libresocsim_interface1_converted_interface_adr attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface1_bus_we + assign $0\rhs_array_muxed24[29:0] \libresocsim_interface2_converted_interface_adr end sync always - update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] + update \rhs_array_muxed24 $0\rhs_array_muxed24[29:0] end - attribute \src "ls180.v:730.5-730.58" - process $proc$ls180.v:730$3354 + attribute \src "ls180.v:384.12-384.39" + process $proc$ls180.v:384$1684 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + assign $1\sdram_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \sdram_cmd_payload_a $1\sdram_cmd_payload_a[12:0] end - attribute \src "ls180.v:731.5-731.64" - process $proc$ls180.v:731$3355 + attribute \src "ls180.v:385.11-385.38" + process $proc$ls180.v:385$1685 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + assign $1\sdram_cmd_payload_ba[1:0] 2'00 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + update \sdram_cmd_payload_ba $1\sdram_cmd_payload_ba[1:0] end - attribute \src "ls180.v:7313.1-7332.4" - process $proc$ls180.v:7313$2526 + attribute \src "ls180.v:3851.1-3864.4" + process $proc$ls180.v:3851$1167 assign { } { } - assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 - attribute \src "ls180.v:7315.2-7331.9" - switch \builder_grant + assign $0\rhs_array_muxed25[31:0] 0 + attribute \src "ls180.v:3853.2-3863.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_ibus_cti - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_dbus_cti - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_jtag_wb_cti + case 2'00 + assign $0\rhs_array_muxed25[31:0] \libresocsim_interface0_converted_interface_dat_w attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti + case 2'01 + assign $0\rhs_array_muxed25[31:0] \libresocsim_interface1_converted_interface_dat_w attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface1_bus_cti + assign $0\rhs_array_muxed25[31:0] \libresocsim_interface2_converted_interface_dat_w end sync always - update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] + update \rhs_array_muxed25 $0\rhs_array_muxed25[31:0] end - attribute \src "ls180.v:732.12-732.74" - process $proc$ls180.v:732$3356 + attribute \src "ls180.v:386.5-386.33" + process $proc$ls180.v:386$1686 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + assign $1\sdram_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \sdram_cmd_payload_cas $1\sdram_cmd_payload_cas[0:0] end - attribute \src "ls180.v:733.12-733.47" - process $proc$ls180.v:733$3357 + attribute \src "ls180.v:3865.1-3878.4" + process $proc$ls180.v:3865$1168 assign { } { } - assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] - end - attribute \src "ls180.v:7333.1-7352.4" - process $proc$ls180.v:7333$2527 - assign { } { } - assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 - attribute \src "ls180.v:7335.2-7351.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_ibus_bte - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_dbus_bte + assign $0\rhs_array_muxed26[3:0] 4'0000 + attribute \src "ls180.v:3867.2-3877.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_jtag_wb_bte + case 2'00 + assign $0\rhs_array_muxed26[3:0] \libresocsim_interface0_converted_interface_sel attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte + case 2'01 + assign $0\rhs_array_muxed26[3:0] \libresocsim_interface1_converted_interface_sel attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface1_bus_bte + assign $0\rhs_array_muxed26[3:0] \libresocsim_interface2_converted_interface_sel end sync always - update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] + update \rhs_array_muxed26 $0\rhs_array_muxed26[3:0] end - attribute \src "ls180.v:734.5-734.46" - process $proc$ls180.v:734$3358 + attribute \src "ls180.v:387.5-387.33" + process $proc$ls180.v:387$1687 assign { } { } - assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $1\sdram_cmd_payload_ras[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + update \sdram_cmd_payload_ras $1\sdram_cmd_payload_ras[0:0] end - attribute \src "ls180.v:7353.1-7369.4" - process $proc$ls180.v:7353$2528 + attribute \src "ls180.v:3879.1-3892.4" + process $proc$ls180.v:3879$1169 assign { } { } - assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 - attribute \src "ls180.v:7355.2-7368.9" - switch \main_sdram_steerer_sel + assign $0\rhs_array_muxed27[0:0] 1'0 + attribute \src "ls180.v:3881.2-3891.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba + assign $0\rhs_array_muxed27[0:0] \libresocsim_interface0_converted_interface_cyc attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + assign $0\rhs_array_muxed27[0:0] \libresocsim_interface1_converted_interface_cyc attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba + assign $0\rhs_array_muxed27[0:0] \libresocsim_interface2_converted_interface_cyc end sync always - update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] + update \rhs_array_muxed27 $0\rhs_array_muxed27[0:0] end - attribute \src "ls180.v:736.5-736.44" - process $proc$ls180.v:736$3359 + attribute \src "ls180.v:388.5-388.32" + process $proc$ls180.v:388$1688 assign { } { } - assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $1\sdram_cmd_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + update \sdram_cmd_payload_we $1\sdram_cmd_payload_we[0:0] end - attribute \src "ls180.v:737.5-737.45" - process $proc$ls180.v:737$3360 + attribute \src "ls180.v:389.5-389.37" + process $proc$ls180.v:389$1689 assign { } { } - assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\sdram_cmd_payload_is_read[0:0] 1'0 sync always + update \sdram_cmd_payload_is_read $0\sdram_cmd_payload_is_read[0:0] sync init - update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] end - attribute \src "ls180.v:7370.1-7386.4" - process $proc$ls180.v:7370$2529 + attribute \src "ls180.v:3893.1-3906.4" + process $proc$ls180.v:3893$1170 assign { } { } - assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:7372.2-7385.9" - switch \main_sdram_steerer_sel + assign $0\rhs_array_muxed28[0:0] 1'0 + attribute \src "ls180.v:3895.2-3905.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a + assign $0\rhs_array_muxed28[0:0] \libresocsim_interface0_converted_interface_stb attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + assign $0\rhs_array_muxed28[0:0] \libresocsim_interface1_converted_interface_stb attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a + assign $0\rhs_array_muxed28[0:0] \libresocsim_interface2_converted_interface_stb end sync always - update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] + update \rhs_array_muxed28 $0\rhs_array_muxed28[0:0] end - attribute \src "ls180.v:738.5-738.54" - process $proc$ls180.v:738$3361 + attribute \src "ls180.v:390.5-390.38" + process $proc$ls180.v:390$1690 assign { } { } - assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $0\sdram_cmd_payload_is_write[0:0] 1'0 sync always + update \sdram_cmd_payload_is_write $0\sdram_cmd_payload_is_write[0:0] sync init - update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:7387.1-7403.4" - process $proc$ls180.v:7387$2530 + attribute \src "ls180.v:3907.1-3920.4" + process $proc$ls180.v:3907$1171 assign { } { } - assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:7389.2-7402.9" - switch \main_sdram_steerer_sel + assign $0\rhs_array_muxed29[0:0] 1'0 + attribute \src "ls180.v:3909.2-3919.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + assign $0\rhs_array_muxed29[0:0] \libresocsim_interface0_converted_interface_we attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7394$2532_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7397$2534_Y + assign $0\rhs_array_muxed29[0:0] \libresocsim_interface1_converted_interface_we attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7400$2536_Y + assign $0\rhs_array_muxed29[0:0] \libresocsim_interface2_converted_interface_we end sync always - update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] + update \rhs_array_muxed29 $0\rhs_array_muxed29[0:0] end - attribute \src "ls180.v:74.11-74.52" - process $proc$ls180.v:74$3134 + attribute \src "ls180.v:3921.1-3934.4" + process $proc$ls180.v:3921$1172 assign { } { } - assign $0\main_libresocsim_libresoc_dbus_cti[2:0] 3'000 + assign $0\rhs_array_muxed30[2:0] 3'000 + attribute \src "ls180.v:3923.2-3933.9" + switch \libresocsim_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\rhs_array_muxed30[2:0] \libresocsim_interface0_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\rhs_array_muxed30[2:0] \libresocsim_interface1_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case + assign $0\rhs_array_muxed30[2:0] \libresocsim_interface2_converted_interface_cti + end sync always - update \main_libresocsim_libresoc_dbus_cti $0\main_libresocsim_libresoc_dbus_cti[2:0] - sync init + update \rhs_array_muxed30 $0\rhs_array_muxed30[2:0] end - attribute \src "ls180.v:740.32-740.76" - process $proc$ls180.v:740$3362 + attribute \src "ls180.v:3935.1-3948.4" + process $proc$ls180.v:3935$1173 assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\rhs_array_muxed31[1:0] 2'00 + attribute \src "ls180.v:3937.2-3947.9" + switch \libresocsim_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\rhs_array_muxed31[1:0] \libresocsim_interface0_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\rhs_array_muxed31[1:0] \libresocsim_interface1_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case + assign $0\rhs_array_muxed31[1:0] \libresocsim_interface2_converted_interface_bte + end sync always - sync init - update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + update \rhs_array_muxed31 $0\rhs_array_muxed31[1:0] end - attribute \src "ls180.v:7404.1-7420.4" - process $proc$ls180.v:7404$2537 + attribute \src "ls180.v:3949.1-3965.4" + process $proc$ls180.v:3949$1174 assign { } { } - assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7406.2-7419.9" - switch \main_sdram_steerer_sel + assign $0\array_muxed0[1:0] 2'00 + attribute \src "ls180.v:3951.2-3964.9" + switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + assign $0\array_muxed0[1:0] \sdram_nop_ba attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7411$2539_Y + assign $0\array_muxed0[1:0] \sdram_choose_req_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7414$2541_Y + assign $0\array_muxed0[1:0] \sdram_choose_req_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7417$2543_Y + assign $0\array_muxed0[1:0] \sdram_cmd_payload_ba end sync always - update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] + update \array_muxed0 $0\array_muxed0[1:0] end - attribute \src "ls180.v:741.11-741.55" - process $proc$ls180.v:741$3363 + attribute \src "ls180.v:396.11-396.39" + process $proc$ls180.v:396$1691 assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $1\sdram_timer_count1[9:0] 10'1100001101 sync always sync init - update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + update \sdram_timer_count1 $1\sdram_timer_count1[9:0] end - attribute \src "ls180.v:7421.1-7437.4" - process $proc$ls180.v:7421$2544 + attribute \src "ls180.v:3966.1-3982.4" + process $proc$ls180.v:3966$1175 assign { } { } - assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7423.2-7436.9" - switch \main_sdram_steerer_sel + assign $0\array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:3968.2-3981.9" + switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + assign $0\array_muxed1[12:0] \sdram_nop_a attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7428$2546_Y + assign $0\array_muxed1[12:0] \sdram_choose_req_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7431$2548_Y + assign $0\array_muxed1[12:0] \sdram_choose_req_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7434$2550_Y + assign $0\array_muxed1[12:0] \sdram_cmd_payload_a end sync always - update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] + update \array_muxed1 $0\array_muxed1[12:0] end - attribute \src "ls180.v:743.32-743.75" - process $proc$ls180.v:743$3364 + attribute \src "ls180.v:398.5-398.33" + process $proc$ls180.v:398$1692 assign { } { } - assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + assign $1\sdram_postponer_req_o[0:0] 1'0 sync always - update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] sync init + update \sdram_postponer_req_o $1\sdram_postponer_req_o[0:0] end - attribute \src "ls180.v:7438.1-7454.4" - process $proc$ls180.v:7438$2551 + attribute \src "ls180.v:3983.1-3999.4" + process $proc$ls180.v:3983$1176 assign { } { } - assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7440.2-7453.9" - switch \main_sdram_steerer_sel + assign $0\array_muxed2[0:0] 1'0 + attribute \src "ls180.v:3985.2-3998.9" + switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + assign $0\array_muxed2[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7445$2553_Y + assign $0\array_muxed2[0:0] $and$ls180.v:3990$1178_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7448$2555_Y + assign $0\array_muxed2[0:0] $and$ls180.v:3993$1180_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7451$2557_Y + assign $0\array_muxed2[0:0] $and$ls180.v:3996$1182_Y end sync always - update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] + update \array_muxed2 $0\array_muxed2[0:0] + end + attribute \src "ls180.v:399.5-399.33" + process $proc$ls180.v:399$1693 + assign { } { } + assign $1\sdram_postponer_count[0:0] 1'0 + sync always + sync init + update \sdram_postponer_count $1\sdram_postponer_count[0:0] end - attribute \src "ls180.v:745.32-745.76" - process $proc$ls180.v:745$3365 + attribute \src "ls180.v:400.5-400.34" + process $proc$ls180.v:400$1694 assign { } { } - assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + assign $1\sdram_sequencer_start0[0:0] 1'0 sync always - update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] sync init + update \sdram_sequencer_start0 $1\sdram_sequencer_start0[0:0] end - attribute \src "ls180.v:7455.1-7471.4" - process $proc$ls180.v:7455$2558 + attribute \src "ls180.v:4000.1-4016.4" + process $proc$ls180.v:4000$1183 assign { } { } - assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:7457.2-7470.9" - switch \main_sdram_steerer_sel + assign $0\array_muxed3[0:0] 1'0 + attribute \src "ls180.v:4002.2-4015.9" + switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + assign $0\array_muxed3[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7462$2560_Y + assign $0\array_muxed3[0:0] $and$ls180.v:4007$1185_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7465$2562_Y + assign $0\array_muxed3[0:0] $and$ls180.v:4010$1187_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7468$2564_Y + assign $0\array_muxed3[0:0] $and$ls180.v:4013$1189_Y end sync always - update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] + update \array_muxed3 $0\array_muxed3[0:0] end - attribute \src "ls180.v:7472.1-7500.4" - process $proc$ls180.v:7472$2565 + attribute \src "ls180.v:4017.1-4033.4" + process $proc$ls180.v:4017$1190 assign { } { } - assign $0\builder_sync_f_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:7474.2-7499.9" - switch \main_spimaster34_mosi_sel - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [0] + assign $0\array_muxed4[0:0] 1'0 + attribute \src "ls180.v:4019.2-4032.9" + switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [1] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [2] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [3] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [4] + case 2'00 + assign $0\array_muxed4[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [5] + case 2'01 + assign $0\array_muxed4[0:0] $and$ls180.v:4024$1192_Y attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [6] + case 2'10 + assign $0\array_muxed4[0:0] $and$ls180.v:4027$1194_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [7] + assign $0\array_muxed4[0:0] $and$ls180.v:4030$1196_Y end sync always - update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] + update \array_muxed4 $0\array_muxed4[0:0] end - attribute \src "ls180.v:75.11-75.52" - process $proc$ls180.v:75$3135 + attribute \src "ls180.v:403.5-403.33" + process $proc$ls180.v:403$1695 assign { } { } - assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 + assign $1\sdram_sequencer_done1[0:0] 1'0 sync always - update \main_libresocsim_libresoc_dbus_bte $0\main_libresocsim_libresoc_dbus_bte[1:0] sync init + update \sdram_sequencer_done1 $1\sdram_sequencer_done1[0:0] end - attribute \src "ls180.v:7501.1-7529.4" - process $proc$ls180.v:7501$2566 + attribute \src "ls180.v:4034.1-4050.4" + process $proc$ls180.v:4034$1197 assign { } { } - assign $0\builder_sync_f_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:7503.2-7528.9" - switch \main_spisdcard_mosi_sel - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [0] - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [1] + assign $0\array_muxed5[0:0] 1'0 + attribute \src "ls180.v:4036.2-4049.9" + switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [2] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [3] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [4] + case 2'00 + assign $0\array_muxed5[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [5] + case 2'01 + assign $0\array_muxed5[0:0] $and$ls180.v:4041$1199_Y attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [6] + case 2'10 + assign $0\array_muxed5[0:0] $and$ls180.v:4044$1201_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [7] + assign $0\array_muxed5[0:0] $and$ls180.v:4047$1203_Y end sync always - update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] - end - attribute \src "ls180.v:751.5-751.51" - process $proc$ls180.v:751$3366 - assign { } { } - assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - end - attribute \src "ls180.v:752.5-752.51" - process $proc$ls180.v:752$3367 - assign { } { } - assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - end - attribute \src "ls180.v:754.5-754.47" - process $proc$ls180.v:754$3368 - assign { } { } - assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] - end - attribute \src "ls180.v:755.5-755.45" - process $proc$ls180.v:755$3369 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] - end - attribute \src "ls180.v:756.5-756.45" - process $proc$ls180.v:756$3370 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] - end - attribute \src "ls180.v:757.12-757.57" - process $proc$ls180.v:757$3371 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - end - attribute \src "ls180.v:7587.1-7597.4" - process $proc$ls180.v:7587$2567 - assign { } { } - assign $0\main_gpiotristateasic0_status[15:0] [15:8] 8'00000000 - assign $0\main_gpiotristateasic0_status[15:0] [0] \builder_multiregimpl1_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [1] \builder_multiregimpl2_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [2] \builder_multiregimpl3_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [3] \builder_multiregimpl4_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [4] \builder_multiregimpl5_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [5] \builder_multiregimpl6_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [6] \builder_multiregimpl7_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [7] \builder_multiregimpl8_regs1 - sync always - update \main_gpiotristateasic0_status $0\main_gpiotristateasic0_status[15:0] - end - attribute \src "ls180.v:759.5-759.51" - process $proc$ls180.v:759$3372 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:7598.1-7608.4" - process $proc$ls180.v:7598$2568 - assign { } { } - assign $0\main_gpiotristateasic1_status[15:0] [7:0] 8'00000000 - assign $0\main_gpiotristateasic1_status[15:0] [8] \builder_multiregimpl9_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [9] \builder_multiregimpl10_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [10] \builder_multiregimpl11_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [11] \builder_multiregimpl12_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [12] \builder_multiregimpl13_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [13] \builder_multiregimpl14_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [14] \builder_multiregimpl15_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [15] \builder_multiregimpl16_regs1 - sync always - update \main_gpiotristateasic1_status $0\main_gpiotristateasic1_status[15:0] - end - attribute \src "ls180.v:760.5-760.51" - process $proc$ls180.v:760$3373 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:761.5-761.50" - process $proc$ls180.v:761$3374 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - end - attribute \src "ls180.v:762.5-762.54" - process $proc$ls180.v:762$3375 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:7629.1-7631.4" - process $proc$ls180.v:7629$2569 - assign { } { } - assign $0\main_int_rst[0:0] \sys_rst - sync posedge \por_clk - update \main_int_rst $0\main_int_rst[0:0] - end - attribute \src "ls180.v:763.5-763.55" - process $proc$ls180.v:763$3376 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:7633.1-7703.4" - process $proc$ls180.v:7633$2570 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] - assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] - assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] - assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] - assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] - assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] - assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] - assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] - assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] - assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] - assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] - assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] - assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] - assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] - assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] - assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n - assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n - assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n - assign $0\sdram_cke[0:0] \main_dfi_p0_cke - assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n - assign $0\sdram_dq_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\sdram_dq_o[15:0] [0] \main_dfi_p0_wrdata [0] - assign $0\main_dfi_p0_rddata[15:0] [0] \sdram_dq_i [0] - assign $0\sdram_dq_o[15:0] [1] \main_dfi_p0_wrdata [1] - assign $0\main_dfi_p0_rddata[15:0] [1] \sdram_dq_i [1] - assign $0\sdram_dq_o[15:0] [2] \main_dfi_p0_wrdata [2] - assign $0\main_dfi_p0_rddata[15:0] [2] \sdram_dq_i [2] - assign $0\sdram_dq_o[15:0] [3] \main_dfi_p0_wrdata [3] - assign $0\main_dfi_p0_rddata[15:0] [3] \sdram_dq_i [3] - assign $0\sdram_dq_o[15:0] [4] \main_dfi_p0_wrdata [4] - assign $0\main_dfi_p0_rddata[15:0] [4] \sdram_dq_i [4] - assign $0\sdram_dq_o[15:0] [5] \main_dfi_p0_wrdata [5] - assign $0\main_dfi_p0_rddata[15:0] [5] \sdram_dq_i [5] - assign $0\sdram_dq_o[15:0] [6] \main_dfi_p0_wrdata [6] - assign $0\main_dfi_p0_rddata[15:0] [6] \sdram_dq_i [6] - assign $0\sdram_dq_o[15:0] [7] \main_dfi_p0_wrdata [7] - assign $0\main_dfi_p0_rddata[15:0] [7] \sdram_dq_i [7] - assign $0\sdram_dq_o[15:0] [8] \main_dfi_p0_wrdata [8] - assign $0\main_dfi_p0_rddata[15:0] [8] \sdram_dq_i [8] - assign $0\sdram_dq_o[15:0] [9] \main_dfi_p0_wrdata [9] - assign $0\main_dfi_p0_rddata[15:0] [9] \sdram_dq_i [9] - assign $0\sdram_dq_o[15:0] [10] \main_dfi_p0_wrdata [10] - assign $0\main_dfi_p0_rddata[15:0] [10] \sdram_dq_i [10] - assign $0\sdram_dq_o[15:0] [11] \main_dfi_p0_wrdata [11] - assign $0\main_dfi_p0_rddata[15:0] [11] \sdram_dq_i [11] - assign $0\sdram_dq_o[15:0] [12] \main_dfi_p0_wrdata [12] - assign $0\main_dfi_p0_rddata[15:0] [12] \sdram_dq_i [12] - assign $0\sdram_dq_o[15:0] [13] \main_dfi_p0_wrdata [13] - assign $0\main_dfi_p0_rddata[15:0] [13] \sdram_dq_i [13] - assign $0\sdram_dq_o[15:0] [14] \main_dfi_p0_wrdata [14] - assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] - assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] - assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] - assign $0\sdram_dm[1:0] [0] $and$ls180.v:7687$2571_Y - assign $0\sdram_dm[1:0] [1] $and$ls180.v:7688$2572_Y - assign $0\sdram_clock[0:0] \sys_clk_1 - assign $0\sdcard_clk[0:0] $and$ls180.v:7690$2574_Y - assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe - assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o - assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i - assign $0\sdcard_data_oe[0:0] \main_sdphy_sdpads_data_oe - assign $0\sdcard_data_o[3:0] [0] \main_sdphy_sdpads_data_o [0] - assign $0\main_sdphy_sdpads_data_i[3:0] [0] \sdcard_data_i [0] - assign $0\sdcard_data_o[3:0] [1] \main_sdphy_sdpads_data_o [1] - assign $0\main_sdphy_sdpads_data_i[3:0] [1] \sdcard_data_i [1] - assign $0\sdcard_data_o[3:0] [2] \main_sdphy_sdpads_data_o [2] - assign $0\main_sdphy_sdpads_data_i[3:0] [2] \sdcard_data_i [2] - assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] - assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] - sync posedge \sdrio_clk - update \sdram_a $0\sdram_a[12:0] - update \sdram_dq_o $0\sdram_dq_o[15:0] - update \sdram_dq_oe $0\sdram_dq_oe[0:0] - update \sdram_we_n $0\sdram_we_n[0:0] - update \sdram_ras_n $0\sdram_ras_n[0:0] - update \sdram_cas_n $0\sdram_cas_n[0:0] - update \sdram_cs_n $0\sdram_cs_n[0:0] - update \sdram_cke $0\sdram_cke[0:0] - update \sdram_ba $0\sdram_ba[1:0] - update \sdram_dm $0\sdram_dm[1:0] - update \sdram_clock $0\sdram_clock[0:0] - update \sdcard_clk $0\sdcard_clk[0:0] - update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] - update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] - update \sdcard_data_o $0\sdcard_data_o[3:0] - update \sdcard_data_oe $0\sdcard_data_oe[0:0] - update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] - update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] - update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] - end - attribute \src "ls180.v:764.5-764.56" - process $proc$ls180.v:764$3377 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:765.5-765.50" - process $proc$ls180.v:765$3378 - assign { } { } - assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + update \array_muxed5 $0\array_muxed5[0:0] end - attribute \src "ls180.v:768.5-768.67" - process $proc$ls180.v:768$3379 + attribute \src "ls180.v:404.11-404.41" + process $proc$ls180.v:404$1696 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\sdram_sequencer_counter[3:0] 4'0000 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] sync init + update \sdram_sequencer_counter $1\sdram_sequencer_counter[3:0] end - attribute \src "ls180.v:769.5-769.66" - process $proc$ls180.v:769$3380 + attribute \src "ls180.v:405.5-405.33" + process $proc$ls180.v:405$1697 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\sdram_sequencer_count[0:0] 1'0 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] sync init + update \sdram_sequencer_count $1\sdram_sequencer_count[0:0] end - attribute \src "ls180.v:7705.1-10349.4" - process $proc$ls180.v:7705$2575 - assign $0\spisdcard_clk[0:0] \spisdcard_clk - assign $0\spisdcard_mosi[0:0] \spisdcard_mosi - assign { } { } - assign $0\pwm[1:0] \pwm - assign $0\spimaster_clk[0:0] \spimaster_clk - assign $0\spimaster_mosi[0:0] \spimaster_mosi - assign { } { } - assign $0\uart_tx[0:0] \uart_tx - assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage - assign { } { } - assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage - assign { } { } - assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors - assign { } { } - assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage - assign { } { } - assign $0\main_libresocsim_reload_storage[31:0] \main_libresocsim_reload_storage - assign { } { } - assign $0\main_libresocsim_en_storage[0:0] \main_libresocsim_en_storage - assign { } { } - assign $0\main_libresocsim_update_value_storage[0:0] \main_libresocsim_update_value_storage - assign { } { } - assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value_status - assign $0\main_libresocsim_zero_pending[0:0] \main_libresocsim_zero_pending - assign { } { } - assign $0\main_libresocsim_eventmanager_storage[0:0] \main_libresocsim_eventmanager_storage - assign { } { } - assign $0\main_libresocsim_value[31:0] \main_libresocsim_value - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_converter0_counter[0:0] \main_converter0_counter - assign $0\main_converter0_dat_r[63:0] \main_converter0_dat_r - assign $0\main_converter1_counter[0:0] \main_converter1_counter - assign $0\main_converter1_dat_r[63:0] \main_converter1_dat_r - assign { } { } - assign { } { } - assign $0\main_sdram_storage[3:0] \main_sdram_storage - assign { } { } - assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage - assign { } { } - assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage - assign { } { } - assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage - assign { } { } - assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage - assign { } { } - assign $0\main_sdram_status[15:0] \main_sdram_status - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 - assign { } { } - assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count - assign { } { } - assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter - assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first - assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row - assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first - assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row - assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first - assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row - assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first - assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row - assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count - assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant - assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant - assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready - assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count - assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready - assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count - assign $0\main_sdram_time0[4:0] \main_sdram_time0 - assign $0\main_sdram_time1[3:0] \main_sdram_time1 - assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter - assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_dat_r - assign $0\main_converter_counter[0:0] \main_converter_counter - assign $0\main_converter_dat_r[31:0] \main_converter_dat_r - assign $0\main_cmd_consumed[0:0] \main_cmd_consumed - assign $0\main_wdata_consumed[0:0] \main_wdata_consumed - assign $0\main_uart_phy_storage[31:0] \main_uart_phy_storage - assign { } { } - assign { } { } - assign $0\main_uart_phy_uart_clk_txen[0:0] \main_uart_phy_uart_clk_txen - assign $0\main_uart_phy_phase_accumulator_tx[31:0] \main_uart_phy_phase_accumulator_tx - assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_tx_reg - assign $0\main_uart_phy_tx_bitcount[3:0] \main_uart_phy_tx_bitcount - assign $0\main_uart_phy_tx_busy[0:0] \main_uart_phy_tx_busy - assign { } { } - assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_source_payload_data - assign $0\main_uart_phy_uart_clk_rxen[0:0] \main_uart_phy_uart_clk_rxen - assign $0\main_uart_phy_phase_accumulator_rx[31:0] \main_uart_phy_phase_accumulator_rx - assign { } { } - assign $0\main_uart_phy_rx_reg[7:0] \main_uart_phy_rx_reg - assign $0\main_uart_phy_rx_bitcount[3:0] \main_uart_phy_rx_bitcount - assign $0\main_uart_phy_rx_busy[0:0] \main_uart_phy_rx_busy - assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending - assign { } { } - assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending - assign { } { } - assign $0\main_uart_eventmanager_storage[1:0] \main_uart_eventmanager_storage - assign { } { } - assign $0\main_uart_tx_fifo_readable[0:0] \main_uart_tx_fifo_readable - assign $0\main_uart_tx_fifo_level0[4:0] \main_uart_tx_fifo_level0 - assign $0\main_uart_tx_fifo_produce[3:0] \main_uart_tx_fifo_produce - assign $0\main_uart_tx_fifo_consume[3:0] \main_uart_tx_fifo_consume - assign $0\main_uart_rx_fifo_readable[0:0] \main_uart_rx_fifo_readable - assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 - assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce - assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume - assign $0\main_gpiotristateasic1_oe_storage[15:0] \main_gpiotristateasic1_oe_storage - assign { } { } - assign $0\main_gpiotristateasic1_out_storage[15:0] \main_gpiotristateasic1_out_storage - assign { } { } - assign $0\main_spimaster5_miso[7:0] \main_spimaster5_miso - assign $0\main_spimaster11_storage[15:0] \main_spimaster11_storage - assign { } { } - assign $0\main_spimaster16_storage[7:0] \main_spimaster16_storage - assign { } { } - assign $0\main_spimaster21_storage[0:0] \main_spimaster21_storage - assign { } { } - assign $0\main_spimaster23_storage[0:0] \main_spimaster23_storage - assign { } { } - assign $0\main_spimaster27_count[2:0] \main_spimaster27_count - assign { } { } - assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster33_mosi_data - assign $0\main_spimaster34_mosi_sel[2:0] \main_spimaster34_mosi_sel - assign $0\main_spimaster35_miso_data[7:0] \main_spimaster35_miso_data - assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso - assign $0\main_spisdcard_control_storage[15:0] \main_spisdcard_control_storage - assign { } { } - assign $0\main_spisdcard_mosi_storage[7:0] \main_spisdcard_mosi_storage - assign { } { } - assign $0\main_spisdcard_cs_storage[0:0] \main_spisdcard_cs_storage - assign { } { } - assign $0\main_spisdcard_loopback_storage[0:0] \main_spisdcard_loopback_storage - assign { } { } - assign $0\main_spisdcard_count[2:0] \main_spisdcard_count - assign { } { } - assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi_data - assign $0\main_spisdcard_mosi_sel[2:0] \main_spisdcard_mosi_sel - assign $0\main_spisdcard_miso_data[7:0] \main_spisdcard_miso_data - assign $0\main_spimaster1_storage[15:0] \main_spimaster1_storage - assign { } { } - assign { } { } - assign $0\main_pwm0_counter[31:0] \main_pwm0_counter - assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage - assign { } { } - assign $0\main_pwm0_width_storage[31:0] \main_pwm0_width_storage - assign { } { } - assign $0\main_pwm0_period_storage[31:0] \main_pwm0_period_storage - assign { } { } - assign $0\main_pwm1_counter[31:0] \main_pwm1_counter - assign $0\main_pwm1_enable_storage[0:0] \main_pwm1_enable_storage - assign { } { } - assign $0\main_pwm1_width_storage[31:0] \main_pwm1_width_storage - assign { } { } - assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage - assign { } { } - assign $0\main_i2c_storage[2:0] \main_i2c_storage - assign { } { } - assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage - assign { } { } - assign { } { } - assign $0\main_sdphy_clocker_clks[8:0] \main_sdphy_clocker_clks - assign { } { } - assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count - assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count - assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout - assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count - assign $0\main_sdphy_cmdr_cmdr_run[0:0] \main_sdphy_cmdr_cmdr_run - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_source_first - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_source_last - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_converter_source_payload_data - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] \main_sdphy_cmdr_cmdr_converter_demux - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] \main_sdphy_cmdr_cmdr_converter_strobe_all - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_source_valid - assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_source_first - assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_source_last - assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_source_payload_data - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset - assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count - assign $0\main_sdphy_dataw_crcr_run[0:0] \main_sdphy_dataw_crcr_run - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_source_first - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_source_last - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] \main_sdphy_dataw_crcr_converter_source_payload_data - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] \main_sdphy_dataw_crcr_converter_demux - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] \main_sdphy_dataw_crcr_converter_strobe_all - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_source_valid - assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_source_first - assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_source_last - assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_source_payload_data - assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset - assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout - assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count - assign $0\main_sdphy_datar_datar_run[0:0] \main_sdphy_datar_datar_run - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_source_first - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_source_last - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] \main_sdphy_datar_datar_converter_source_payload_data - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] \main_sdphy_datar_datar_converter_source_payload_valid_token_count - assign $0\main_sdphy_datar_datar_converter_demux[0:0] \main_sdphy_datar_datar_converter_demux - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] \main_sdphy_datar_datar_converter_strobe_all - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_source_valid - assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_source_first - assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_source_last - assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_source_payload_data - assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset - assign $0\main_sdcore_cmd_argument_storage[31:0] \main_sdcore_cmd_argument_storage - assign { } { } - assign $0\main_sdcore_cmd_command_storage[31:0] \main_sdcore_cmd_command_storage - assign { } { } - assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status - assign $0\main_sdcore_block_length_storage[9:0] \main_sdcore_block_length_storage - assign { } { } - assign $0\main_sdcore_block_count_storage[31:0] \main_sdcore_block_count_storage - assign { } { } - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg0 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3 - assign $0\main_sdcore_crc16_checker_val[7:0] \main_sdcore_crc16_checker_val - assign $0\main_sdcore_crc16_checker_cnt[3:0] \main_sdcore_crc16_checker_cnt - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crctmp0 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crctmp1 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crctmp2 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crctmp3 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] \main_sdcore_crc16_checker_fifo0 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] \main_sdcore_crc16_checker_fifo1 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] \main_sdcore_crc16_checker_fifo2 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] \main_sdcore_crc16_checker_fifo3 - assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count - assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done - assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error - assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout - assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count - assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done - assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error - assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout - assign $0\main_sdblock2mem_fifo_level[5:0] \main_sdblock2mem_fifo_level - assign $0\main_sdblock2mem_fifo_produce[4:0] \main_sdblock2mem_fifo_produce - assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume - assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first - assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] \main_sdblock2mem_converter_source_payload_data - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] \main_sdblock2mem_converter_source_payload_valid_token_count - assign $0\main_sdblock2mem_converter_demux[2:0] \main_sdblock2mem_converter_demux - assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] \main_sdblock2mem_wishbonedmawriter_length_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \main_sdblock2mem_wishbonedmawriter_enable_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset - assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data - assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage - assign { } { } - assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage - assign { } { } - assign $0\main_sdmem2block_dma_enable_storage[0:0] \main_sdmem2block_dma_enable_storage - assign { } { } - assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage - assign { } { } - assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset - assign $0\main_sdmem2block_converter_mux[2:0] \main_sdmem2block_converter_mux - assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level - assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce - assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:4051.1-4067.4" + process $proc$ls180.v:4051$1204 assign { } { } + assign $0\array_muxed6[0:0] 1'0 + attribute \src "ls180.v:4053.2-4066.9" + switch \sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\array_muxed6[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\array_muxed6[0:0] $and$ls180.v:4058$1206_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\array_muxed6[0:0] $and$ls180.v:4061$1208_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\array_muxed6[0:0] $and$ls180.v:4064$1210_Y + end + sync always + update \array_muxed6 $0\array_muxed6[0:0] + end + attribute \src "ls180.v:411.5-411.46" + process $proc$ls180.v:411$1698 assign { } { } + assign $1\sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_req_wdata_ready $1\sdram_bankmachine0_req_wdata_ready[0:0] + end + attribute \src "ls180.v:412.5-412.46" + process $proc$ls180.v:412$1699 assign { } { } + assign $1\sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_req_rdata_valid $1\sdram_bankmachine0_req_rdata_valid[0:0] + end + attribute \src "ls180.v:414.5-414.42" + process $proc$ls180.v:414$1700 assign { } { } - assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr - assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we - assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w - assign $0\builder_grant[2:0] \builder_grant + assign $1\sdram_bankmachine0_refresh_gnt[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_refresh_gnt $1\sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "ls180.v:415.5-415.40" + process $proc$ls180.v:415$1701 assign { } { } - assign $0\builder_count[19:0] \builder_count + assign $1\sdram_bankmachine0_cmd_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_valid $1\sdram_bankmachine0_cmd_valid[0:0] + end + attribute \src "ls180.v:416.5-416.40" + process $proc$ls180.v:416$1702 assign { } { } + assign $1\sdram_bankmachine0_cmd_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_ready $1\sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:417.12-417.52" + process $proc$ls180.v:417$1703 assign { } { } + assign $1\sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \sdram_bankmachine0_cmd_payload_a $1\sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:4174.1-4176.4" + process $proc$ls180.v:4174$1211 assign { } { } + assign $0\int_rst[0:0] \sys_rst + sync posedge \por_clk + update \int_rst $0\int_rst[0:0] + end + attribute \src "ls180.v:4178.1-4283.4" + process $proc$ls180.v:4178$1212 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [0] \dfi_p0_address [0] + assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [1] \dfi_p0_address [1] + assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [2] \dfi_p0_address [2] + assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [3] \dfi_p0_address [3] + assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [4] \dfi_p0_address [4] + assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [5] \dfi_p0_address [5] + assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [6] \dfi_p0_address [6] + assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [7] \dfi_p0_address [7] + assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [8] \dfi_p0_address [8] + assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [9] \dfi_p0_address [9] + assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [10] \dfi_p0_address [10] + assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [11] \dfi_p0_address [11] + assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [12] \dfi_p0_address [12] + assign $0\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] [0] \dfi_p0_bank [0] + assign $0\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] [1] \dfi_p0_bank [1] + assign $0\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] \dfi_p0_cas_n + assign $0\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] \dfi_p0_ras_n + assign $0\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] \dfi_p0_we_n + assign $0\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] \dfi_p0_cke + assign $0\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] \dfi_p0_cs_n + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] \dfi_p0_wrdata_en + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [0] \dfi_p0_wrdata [0] + assign $0\dfi_p0_rddata[15:0] [0] \libresocsim_libresoc_constraintmanager_sdram_dq_i [0] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [1] \dfi_p0_wrdata [1] + assign $0\dfi_p0_rddata[15:0] [1] \libresocsim_libresoc_constraintmanager_sdram_dq_i [1] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [2] \dfi_p0_wrdata [2] + assign $0\dfi_p0_rddata[15:0] [2] \libresocsim_libresoc_constraintmanager_sdram_dq_i [2] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [3] \dfi_p0_wrdata [3] + assign $0\dfi_p0_rddata[15:0] [3] \libresocsim_libresoc_constraintmanager_sdram_dq_i [3] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [4] \dfi_p0_wrdata [4] + assign $0\dfi_p0_rddata[15:0] [4] \libresocsim_libresoc_constraintmanager_sdram_dq_i [4] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [5] \dfi_p0_wrdata [5] + assign $0\dfi_p0_rddata[15:0] [5] \libresocsim_libresoc_constraintmanager_sdram_dq_i [5] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [6] \dfi_p0_wrdata [6] + assign $0\dfi_p0_rddata[15:0] [6] \libresocsim_libresoc_constraintmanager_sdram_dq_i [6] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [7] \dfi_p0_wrdata [7] + assign $0\dfi_p0_rddata[15:0] [7] \libresocsim_libresoc_constraintmanager_sdram_dq_i [7] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [8] \dfi_p0_wrdata [8] + assign $0\dfi_p0_rddata[15:0] [8] \libresocsim_libresoc_constraintmanager_sdram_dq_i [8] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [9] \dfi_p0_wrdata [9] + assign $0\dfi_p0_rddata[15:0] [9] \libresocsim_libresoc_constraintmanager_sdram_dq_i [9] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [10] \dfi_p0_wrdata [10] + assign $0\dfi_p0_rddata[15:0] [10] \libresocsim_libresoc_constraintmanager_sdram_dq_i [10] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [11] \dfi_p0_wrdata [11] + assign $0\dfi_p0_rddata[15:0] [11] \libresocsim_libresoc_constraintmanager_sdram_dq_i [11] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [12] \dfi_p0_wrdata [12] + assign $0\dfi_p0_rddata[15:0] [12] \libresocsim_libresoc_constraintmanager_sdram_dq_i [12] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [13] \dfi_p0_wrdata [13] + assign $0\dfi_p0_rddata[15:0] [13] \libresocsim_libresoc_constraintmanager_sdram_dq_i [13] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [14] \dfi_p0_wrdata [14] + assign $0\dfi_p0_rddata[15:0] [14] \libresocsim_libresoc_constraintmanager_sdram_dq_i [14] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [15] \dfi_p0_wrdata [15] + assign $0\dfi_p0_rddata[15:0] [15] \libresocsim_libresoc_constraintmanager_sdram_dq_i [15] + assign $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] [0] $and$ls180.v:4232$1213_Y + assign $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] [1] $and$ls180.v:4233$1214_Y + assign $0\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] \sys_clk_1 + assign $0\gpio0_pads_gpio0oe[7:0] [0] \gpio0_oe_storage [0] + assign $0\gpio0_pads_gpio0o[7:0] [0] \gpio0_out_storage [0] + assign $0\gpio0_status[7:0] [0] \gpio0_pads_gpio0i [0] + assign $0\gpio0_pads_gpio0oe[7:0] [1] \gpio0_oe_storage [1] + assign $0\gpio0_pads_gpio0o[7:0] [1] \gpio0_out_storage [1] + assign $0\gpio0_status[7:0] [1] \gpio0_pads_gpio0i [1] + assign $0\gpio0_pads_gpio0oe[7:0] [2] \gpio0_oe_storage [2] + assign $0\gpio0_pads_gpio0o[7:0] [2] \gpio0_out_storage [2] + assign $0\gpio0_status[7:0] [2] \gpio0_pads_gpio0i [2] + assign $0\gpio0_pads_gpio0oe[7:0] [3] \gpio0_oe_storage [3] + assign $0\gpio0_pads_gpio0o[7:0] [3] \gpio0_out_storage [3] + assign $0\gpio0_status[7:0] [3] \gpio0_pads_gpio0i [3] + assign $0\gpio0_pads_gpio0oe[7:0] [4] \gpio0_oe_storage [4] + assign $0\gpio0_pads_gpio0o[7:0] [4] \gpio0_out_storage [4] + assign $0\gpio0_status[7:0] [4] \gpio0_pads_gpio0i [4] + assign $0\gpio0_pads_gpio0oe[7:0] [5] \gpio0_oe_storage [5] + assign $0\gpio0_pads_gpio0o[7:0] [5] \gpio0_out_storage [5] + assign $0\gpio0_status[7:0] [5] \gpio0_pads_gpio0i [5] + assign $0\gpio0_pads_gpio0oe[7:0] [6] \gpio0_oe_storage [6] + assign $0\gpio0_pads_gpio0o[7:0] [6] \gpio0_out_storage [6] + assign $0\gpio0_status[7:0] [6] \gpio0_pads_gpio0i [6] + assign $0\gpio0_pads_gpio0oe[7:0] [7] \gpio0_oe_storage [7] + assign $0\gpio0_pads_gpio0o[7:0] [7] \gpio0_out_storage [7] + assign $0\gpio0_status[7:0] [7] \gpio0_pads_gpio0i [7] + assign $0\gpio1_pads_gpio1oe[7:0] [0] \gpio1_oe_storage [0] + assign $0\gpio1_pads_gpio1o[7:0] [0] \gpio1_out_storage [0] + assign $0\gpio1_status[7:0] [0] \gpio1_pads_gpio1i [0] + assign $0\gpio1_pads_gpio1oe[7:0] [1] \gpio1_oe_storage [1] + assign $0\gpio1_pads_gpio1o[7:0] [1] \gpio1_out_storage [1] + assign $0\gpio1_status[7:0] [1] \gpio1_pads_gpio1i [1] + assign $0\gpio1_pads_gpio1oe[7:0] [2] \gpio1_oe_storage [2] + assign $0\gpio1_pads_gpio1o[7:0] [2] \gpio1_out_storage [2] + assign $0\gpio1_status[7:0] [2] \gpio1_pads_gpio1i [2] + assign $0\gpio1_pads_gpio1oe[7:0] [3] \gpio1_oe_storage [3] + assign $0\gpio1_pads_gpio1o[7:0] [3] \gpio1_out_storage [3] + assign $0\gpio1_status[7:0] [3] \gpio1_pads_gpio1i [3] + assign $0\gpio1_pads_gpio1oe[7:0] [4] \gpio1_oe_storage [4] + assign $0\gpio1_pads_gpio1o[7:0] [4] \gpio1_out_storage [4] + assign $0\gpio1_status[7:0] [4] \gpio1_pads_gpio1i [4] + assign $0\gpio1_pads_gpio1oe[7:0] [5] \gpio1_oe_storage [5] + assign $0\gpio1_pads_gpio1o[7:0] [5] \gpio1_out_storage [5] + assign $0\gpio1_status[7:0] [5] \gpio1_pads_gpio1i [5] + assign $0\gpio1_pads_gpio1oe[7:0] [6] \gpio1_oe_storage [6] + assign $0\gpio1_pads_gpio1o[7:0] [6] \gpio1_out_storage [6] + assign $0\gpio1_status[7:0] [6] \gpio1_pads_gpio1i [6] + assign $0\gpio1_pads_gpio1oe[7:0] [7] \gpio1_oe_storage [7] + assign $0\gpio1_pads_gpio1o[7:0] [7] \gpio1_out_storage [7] + assign $0\gpio1_status[7:0] [7] \gpio1_pads_gpio1i [7] + sync posedge \sdrio_clk + update \libresocsim_libresoc_constraintmanager_sdram_a $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] + update \libresocsim_libresoc_constraintmanager_sdram_dq_o $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] + update \libresocsim_libresoc_constraintmanager_sdram_dq_oe $0\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] + update \libresocsim_libresoc_constraintmanager_sdram_we_n $0\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] + update \libresocsim_libresoc_constraintmanager_sdram_ras_n $0\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] + update \libresocsim_libresoc_constraintmanager_sdram_cas_n $0\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] + update \libresocsim_libresoc_constraintmanager_sdram_cs_n $0\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] + update \libresocsim_libresoc_constraintmanager_sdram_cke $0\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] + update \libresocsim_libresoc_constraintmanager_sdram_ba $0\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] + update \libresocsim_libresoc_constraintmanager_sdram_dm $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] + update \libresocsim_libresoc_constraintmanager_sdram_clock $0\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] + update \dfi_p0_rddata $0\dfi_p0_rddata[15:0] + update \gpio0_status $0\gpio0_status[7:0] + update \gpio0_pads_gpio0o $0\gpio0_pads_gpio0o[7:0] + update \gpio0_pads_gpio0oe $0\gpio0_pads_gpio0oe[7:0] + update \gpio1_status $0\gpio1_status[7:0] + update \gpio1_pads_gpio1o $0\gpio1_pads_gpio1o[7:0] + update \gpio1_pads_gpio1oe $0\gpio1_pads_gpio1oe[7:0] + end + attribute \src "ls180.v:419.5-419.46" + process $proc$ls180.v:419$1704 assign { } { } + assign $1\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_payload_cas $1\sdram_bankmachine0_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:420.5-420.46" + process $proc$ls180.v:420$1705 assign { } { } + assign $1\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_payload_ras $1\sdram_bankmachine0_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:421.5-421.45" + process $proc$ls180.v:421$1706 assign { } { } + assign $1\sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_payload_we $1\sdram_bankmachine0_cmd_payload_we[0:0] + end + attribute \src "ls180.v:422.5-422.49" + process $proc$ls180.v:422$1707 assign { } { } + assign $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_payload_is_cmd $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:423.5-423.50" + process $proc$ls180.v:423$1708 assign { } { } + assign $1\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_payload_is_read $1\sdram_bankmachine0_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:424.5-424.51" + process $proc$ls180.v:424$1709 assign { } { } + assign $1\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_payload_is_write $1\sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:425.5-425.45" + process $proc$ls180.v:425$1710 assign { } { } + assign $1\sdram_bankmachine0_auto_precharge[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_auto_precharge $1\sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:428.5-428.62" + process $proc$ls180.v:428$1711 assign { } { } + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:4285.1-5491.4" + process $proc$ls180.v:4285$1215 + assign $0\libresocsim_reset_storage[0:0] \libresocsim_reset_storage assign { } { } + assign $0\libresocsim_scratch_storage[31:0] \libresocsim_scratch_storage assign { } { } + assign $0\libresocsim_bus_errors[31:0] \libresocsim_bus_errors + assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] \libresocsim_libresoc_constraintmanager_uart_tx + assign $0\libresocsim_converter0_counter[0:0] \libresocsim_converter0_counter + assign $0\libresocsim_converter0_dat_r[63:0] \libresocsim_converter0_dat_r + assign $0\libresocsim_converter1_counter[0:0] \libresocsim_converter1_counter + assign $0\libresocsim_converter1_dat_r[63:0] \libresocsim_converter1_dat_r + assign $0\libresocsim_converter2_counter[0:0] \libresocsim_converter2_counter + assign $0\libresocsim_converter2_dat_r[63:0] \libresocsim_converter2_dat_r assign { } { } + assign $0\libresocsim_load_storage[31:0] \libresocsim_load_storage assign { } { } + assign $0\libresocsim_reload_storage[31:0] \libresocsim_reload_storage assign { } { } + assign $0\libresocsim_en_storage[0:0] \libresocsim_en_storage assign { } { } + assign $0\libresocsim_update_value_storage[0:0] \libresocsim_update_value_storage assign { } { } + assign $0\libresocsim_value_status[31:0] \libresocsim_value_status + assign $0\libresocsim_zero_pending[0:0] \libresocsim_zero_pending assign { } { } + assign $0\libresocsim_eventmanager_storage[0:0] \libresocsim_eventmanager_storage assign { } { } + assign $0\libresocsim_value[31:0] \libresocsim_value assign { } { } assign { } { } assign { } { } + assign $0\sdram_storage[3:0] \sdram_storage assign { } { } + assign $0\sdram_command_storage[5:0] \sdram_command_storage assign { } { } + assign $0\sdram_address_storage[12:0] \sdram_address_storage assign { } { } + assign $0\sdram_baddress_storage[1:0] \sdram_baddress_storage assign { } { } + assign $0\sdram_wrdata_storage[15:0] \sdram_wrdata_storage assign { } { } + assign $0\sdram_status[15:0] \sdram_status assign { } { } assign { } { } assign { } { } @@ -298049,950 +266123,984 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\sdram_timer_count1[9:0] \sdram_timer_count1 assign { } { } + assign $0\sdram_postponer_count[0:0] \sdram_postponer_count assign { } { } + assign $0\sdram_sequencer_counter[3:0] \sdram_sequencer_counter + assign $0\sdram_sequencer_count[0:0] \sdram_sequencer_count + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \sdram_bankmachine0_cmd_buffer_lookahead_level + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \sdram_bankmachine0_cmd_buffer_lookahead_produce + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \sdram_bankmachine0_cmd_buffer_lookahead_consume + assign $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] \sdram_bankmachine0_cmd_buffer_source_valid + assign $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] \sdram_bankmachine0_cmd_buffer_source_first + assign $0\sdram_bankmachine0_cmd_buffer_source_last[0:0] \sdram_bankmachine0_cmd_buffer_source_last + assign $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine0_cmd_buffer_source_payload_we + assign $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr + assign $0\sdram_bankmachine0_row[12:0] \sdram_bankmachine0_row + assign $0\sdram_bankmachine0_row_opened[0:0] \sdram_bankmachine0_row_opened + assign $0\sdram_bankmachine0_twtpcon_ready[0:0] \sdram_bankmachine0_twtpcon_ready + assign $0\sdram_bankmachine0_twtpcon_count[2:0] \sdram_bankmachine0_twtpcon_count + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \sdram_bankmachine1_cmd_buffer_lookahead_level + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \sdram_bankmachine1_cmd_buffer_lookahead_produce + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \sdram_bankmachine1_cmd_buffer_lookahead_consume + assign $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] \sdram_bankmachine1_cmd_buffer_source_valid + assign $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] \sdram_bankmachine1_cmd_buffer_source_first + assign $0\sdram_bankmachine1_cmd_buffer_source_last[0:0] \sdram_bankmachine1_cmd_buffer_source_last + assign $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine1_cmd_buffer_source_payload_we + assign $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr + assign $0\sdram_bankmachine1_row[12:0] \sdram_bankmachine1_row + assign $0\sdram_bankmachine1_row_opened[0:0] \sdram_bankmachine1_row_opened + assign $0\sdram_bankmachine1_twtpcon_ready[0:0] \sdram_bankmachine1_twtpcon_ready + assign $0\sdram_bankmachine1_twtpcon_count[2:0] \sdram_bankmachine1_twtpcon_count + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \sdram_bankmachine2_cmd_buffer_lookahead_level + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \sdram_bankmachine2_cmd_buffer_lookahead_produce + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \sdram_bankmachine2_cmd_buffer_lookahead_consume + assign $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] \sdram_bankmachine2_cmd_buffer_source_valid + assign $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] \sdram_bankmachine2_cmd_buffer_source_first + assign $0\sdram_bankmachine2_cmd_buffer_source_last[0:0] \sdram_bankmachine2_cmd_buffer_source_last + assign $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine2_cmd_buffer_source_payload_we + assign $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr + assign $0\sdram_bankmachine2_row[12:0] \sdram_bankmachine2_row + assign $0\sdram_bankmachine2_row_opened[0:0] \sdram_bankmachine2_row_opened + assign $0\sdram_bankmachine2_twtpcon_ready[0:0] \sdram_bankmachine2_twtpcon_ready + assign $0\sdram_bankmachine2_twtpcon_count[2:0] \sdram_bankmachine2_twtpcon_count + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \sdram_bankmachine3_cmd_buffer_lookahead_level + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \sdram_bankmachine3_cmd_buffer_lookahead_produce + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \sdram_bankmachine3_cmd_buffer_lookahead_consume + assign $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] \sdram_bankmachine3_cmd_buffer_source_valid + assign $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] \sdram_bankmachine3_cmd_buffer_source_first + assign $0\sdram_bankmachine3_cmd_buffer_source_last[0:0] \sdram_bankmachine3_cmd_buffer_source_last + assign $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine3_cmd_buffer_source_payload_we + assign $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr + assign $0\sdram_bankmachine3_row[12:0] \sdram_bankmachine3_row + assign $0\sdram_bankmachine3_row_opened[0:0] \sdram_bankmachine3_row_opened + assign $0\sdram_bankmachine3_twtpcon_ready[0:0] \sdram_bankmachine3_twtpcon_ready + assign $0\sdram_bankmachine3_twtpcon_count[2:0] \sdram_bankmachine3_twtpcon_count + assign $0\sdram_choose_cmd_grant[1:0] \sdram_choose_cmd_grant + assign $0\sdram_choose_req_grant[1:0] \sdram_choose_req_grant + assign $0\sdram_tccdcon_ready[0:0] \sdram_tccdcon_ready + assign $0\sdram_tccdcon_count[0:0] \sdram_tccdcon_count + assign $0\sdram_twtrcon_ready[0:0] \sdram_twtrcon_ready + assign $0\sdram_twtrcon_count[2:0] \sdram_twtrcon_count + assign $0\sdram_time0[4:0] \sdram_time0 + assign $0\sdram_time1[3:0] \sdram_time1 + assign $0\converter_counter[0:0] \converter_counter + assign $0\converter_dat_r[31:0] \converter_dat_r + assign $0\cmd_consumed[0:0] \cmd_consumed + assign $0\wdata_consumed[0:0] \wdata_consumed + assign $0\uart_phy_storage[31:0] \uart_phy_storage assign { } { } assign { } { } + assign $0\uart_phy_uart_clk_txen[0:0] \uart_phy_uart_clk_txen + assign $0\uart_phy_phase_accumulator_tx[31:0] \uart_phy_phase_accumulator_tx + assign $0\uart_phy_tx_reg[7:0] \uart_phy_tx_reg + assign $0\uart_phy_tx_bitcount[3:0] \uart_phy_tx_bitcount + assign $0\uart_phy_tx_busy[0:0] \uart_phy_tx_busy assign { } { } + assign $0\uart_phy_source_payload_data[7:0] \uart_phy_source_payload_data + assign $0\uart_phy_uart_clk_rxen[0:0] \uart_phy_uart_clk_rxen + assign $0\uart_phy_phase_accumulator_rx[31:0] \uart_phy_phase_accumulator_rx assign { } { } + assign $0\uart_phy_rx_reg[7:0] \uart_phy_rx_reg + assign $0\uart_phy_rx_bitcount[3:0] \uart_phy_rx_bitcount + assign $0\uart_phy_rx_busy[0:0] \uart_phy_rx_busy + assign $0\tx_pending[0:0] \tx_pending assign { } { } + assign $0\rx_pending[0:0] \rx_pending assign { } { } + assign $0\eventmanager_storage[1:0] \eventmanager_storage assign { } { } - assign $0\main_dummy[23:0] [0] $or$ls180.v:7706$2576_Y - assign $0\main_dummy[23:0] [1] $or$ls180.v:7707$2577_Y - assign $0\main_dummy[23:0] [2] $or$ls180.v:7708$2578_Y - assign $0\main_dummy[23:0] [3] $or$ls180.v:7709$2579_Y - assign $0\main_dummy[23:0] [4] $or$ls180.v:7710$2580_Y - assign $0\main_dummy[23:0] [5] $or$ls180.v:7711$2581_Y - assign $0\main_dummy[23:0] [6] $or$ls180.v:7712$2582_Y - assign $0\main_dummy[23:0] [7] $or$ls180.v:7713$2583_Y - assign $0\main_dummy[23:0] [8] $or$ls180.v:7714$2584_Y - assign $0\main_dummy[23:0] [9] $or$ls180.v:7715$2585_Y - assign $0\main_dummy[23:0] [10] $or$ls180.v:7716$2586_Y - assign $0\main_dummy[23:0] [11] $or$ls180.v:7717$2587_Y - assign $0\main_dummy[23:0] [12] $or$ls180.v:7718$2588_Y - assign $0\main_dummy[23:0] [13] $or$ls180.v:7719$2589_Y - assign $0\main_dummy[23:0] [14] $or$ls180.v:7720$2590_Y - assign $0\main_dummy[23:0] [15] $or$ls180.v:7721$2591_Y - assign $0\main_dummy[23:0] [16] $or$ls180.v:7722$2592_Y - assign $0\main_dummy[23:0] [17] $or$ls180.v:7723$2593_Y - assign $0\main_dummy[23:0] [18] $or$ls180.v:7724$2594_Y - assign $0\main_dummy[23:0] [19] $or$ls180.v:7725$2595_Y - assign $0\main_dummy[23:0] [20] $or$ls180.v:7726$2596_Y - assign $0\main_dummy[23:0] [21] $or$ls180.v:7727$2597_Y - assign $0\main_dummy[23:0] [22] $or$ls180.v:7728$2598_Y - assign $0\main_dummy[23:0] [23] $or$ls180.v:7729$2599_Y - assign $0\builder_converter0_state[0:0] \builder_converter0_next_state - assign $0\builder_converter1_state[0:0] \builder_converter1_next_state - assign $0\builder_converter2_state[0:0] \builder_converter2_next_state - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 - assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger - assign $0\main_interface0_ram_bus_ack[0:0] 1'0 - assign $0\main_interface1_ram_bus_ack[0:0] 1'0 - assign $0\main_interface2_ram_bus_ack[0:0] 1'0 - assign $0\main_interface3_ram_bus_ack[0:0] 1'0 - assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } - assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] - assign $0\main_sdram_postponer_req_o[0:0] 1'0 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'0 - assign $0\builder_refresher_state[1:0] \builder_refresher_next_state - assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state - assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state - assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state - assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state - assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 - assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 - assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8187$2708_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8188$2709_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8189$2710_Y - assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 - assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 - assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8223$2728_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8224$2740_Y - assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 - assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 - assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 - assign $0\builder_converter_state[0:0] \builder_converter_next_state - assign $0\main_uart_phy_sink_ready[0:0] 1'0 - assign $0\main_uart_phy_source_valid[0:0] 1'0 - assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx - assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger - assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger - assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8382$2786_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8391$2789_Y - assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state - assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8417$2791_Y - assign $0\spimaster_cs_n[0:0] $or$ls180.v:8426$2794_Y - assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state - assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 - assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 - assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state - assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state - assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state - assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state - assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state - assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state - assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state - assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state - assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state - assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state - assign $0\builder_state[1:0] \builder_next_state - assign $0\builder_slave_sel_r[12:0] \builder_slave_sel - assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re - assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re - assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_gpiotristateasic1_oe_re[0:0] \builder_csrbank1_oe0_re - assign $0\main_gpiotristateasic1_out_re[0:0] \builder_csrbank1_out0_re - assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re - assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_pwm0_enable_re[0:0] \builder_csrbank3_enable0_re - assign $0\main_pwm0_width_re[0:0] \builder_csrbank3_width0_re - assign $0\main_pwm0_period_re[0:0] \builder_csrbank3_period0_re - assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_pwm1_enable_re[0:0] \builder_csrbank4_enable0_re - assign $0\main_pwm1_width_re[0:0] \builder_csrbank4_width0_re - assign $0\main_pwm1_period_re[0:0] \builder_csrbank4_period0_re - assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank5_dma_base0_re - assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank5_dma_length0_re - assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank5_dma_enable0_re - assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank5_dma_loop0_re - assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank6_cmd_argument0_re - assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank6_cmd_command0_re - assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank6_block_length0_re - assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank6_block_count0_re - assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank7_dma_base0_re - assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank7_dma_length0_re - assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank7_dma_enable0_re - assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank7_dma_loop0_re - assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank8_clocker_divider0_re - assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdram_re[0:0] \builder_csrbank9_dfii_control0_re - assign $0\main_sdram_command_re[0:0] \builder_csrbank9_dfii_pi0_command0_re - assign $0\main_sdram_address_re[0:0] \builder_csrbank9_dfii_pi0_address0_re - assign $0\main_sdram_baddress_re[0:0] \builder_csrbank9_dfii_pi0_baddress0_re - assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank9_dfii_pi0_wrdata0_re - assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_spimaster12_re[0:0] \builder_csrbank10_control0_re - assign $0\main_spimaster17_re[0:0] \builder_csrbank10_mosi0_re - assign $0\main_spimaster22_re[0:0] \builder_csrbank10_cs0_re - assign $0\main_spimaster24_re[0:0] \builder_csrbank10_loopback0_re - assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_spisdcard_control_re[0:0] \builder_csrbank11_control0_re - assign $0\main_spisdcard_mosi_re[0:0] \builder_csrbank11_mosi0_re - assign $0\main_spisdcard_cs_re[0:0] \builder_csrbank11_cs0_re - assign $0\main_spisdcard_loopback_re[0:0] \builder_csrbank11_loopback0_re - assign $0\main_spimaster1_re[0:0] \builder_csrbank11_clk_divider0_re - assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_load_re[0:0] \builder_csrbank12_load0_re - assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank12_reload0_re - assign $0\main_libresocsim_en_re[0:0] \builder_csrbank12_en0_re - assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank12_update_value0_re - assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re - assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank13_ev_enable0_re - assign $0\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re - assign $0\builder_multiregimpl0_regs0[0:0] \uart_rx - assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 - assign $0\builder_multiregimpl1_regs0[0:0] \main_gpiotristateasic0_pads_i [0] - assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 - assign $0\builder_multiregimpl2_regs0[0:0] \main_gpiotristateasic0_pads_i [1] - assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 - assign $0\builder_multiregimpl3_regs0[0:0] \main_gpiotristateasic0_pads_i [2] - assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 - assign $0\builder_multiregimpl4_regs0[0:0] \main_gpiotristateasic0_pads_i [3] - assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 - assign $0\builder_multiregimpl5_regs0[0:0] \main_gpiotristateasic0_pads_i [4] - assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 - assign $0\builder_multiregimpl6_regs0[0:0] \main_gpiotristateasic0_pads_i [5] - assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 - assign $0\builder_multiregimpl7_regs0[0:0] \main_gpiotristateasic0_pads_i [6] - assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 - assign $0\builder_multiregimpl8_regs0[0:0] \main_gpiotristateasic0_pads_i [7] - assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 - assign $0\builder_multiregimpl9_regs0[0:0] \main_gpiotristateasic1_pads_i [8] - assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 - assign $0\builder_multiregimpl10_regs0[0:0] \main_gpiotristateasic1_pads_i [9] - assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 - assign $0\builder_multiregimpl11_regs0[0:0] \main_gpiotristateasic1_pads_i [10] - assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 - assign $0\builder_multiregimpl12_regs0[0:0] \main_gpiotristateasic1_pads_i [11] - assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 - assign $0\builder_multiregimpl13_regs0[0:0] \main_gpiotristateasic1_pads_i [12] - assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 - assign $0\builder_multiregimpl14_regs0[0:0] \main_gpiotristateasic1_pads_i [13] - assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 - assign $0\builder_multiregimpl15_regs0[0:0] \main_gpiotristateasic1_pads_i [14] - assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 - assign $0\builder_multiregimpl16_regs0[0:0] \main_gpiotristateasic1_pads_i [15] - assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 - attribute \src "ls180.v:7730.2-7732.5" - switch $or$ls180.v:7730$2600_Y - attribute \src "ls180.v:7730.6-7730.69" - case 1'1 - assign $0\main_converter0_dat_r[63:0] \main_interface0_converted_interface_dat_r - case - end - attribute \src "ls180.v:7734.2-7736.5" - switch \main_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:7734.6-7734.54" - case 1'1 - assign $0\main_converter0_counter[0:0] \main_converter0_counter_converter0_next_value - case - end - attribute \src "ls180.v:7737.2-7740.5" - switch \main_converter0_reset - attribute \src "ls180.v:7737.6-7737.27" - case 1'1 - assign $0\main_converter0_counter[0:0] 1'0 - assign $0\builder_converter0_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7741.2-7743.5" - switch $or$ls180.v:7741$2601_Y - attribute \src "ls180.v:7741.6-7741.69" - case 1'1 - assign $0\main_converter1_dat_r[63:0] \main_interface1_converted_interface_dat_r - case - end - attribute \src "ls180.v:7745.2-7747.5" - switch \main_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:7745.6-7745.54" - case 1'1 - assign $0\main_converter1_counter[0:0] \main_converter1_counter_converter1_next_value - case - end - attribute \src "ls180.v:7748.2-7751.5" - switch \main_converter1_reset - attribute \src "ls180.v:7748.6-7748.27" - case 1'1 - assign $0\main_converter1_counter[0:0] 1'0 - assign $0\builder_converter1_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7752.2-7754.5" - switch $or$ls180.v:7752$2602_Y - attribute \src "ls180.v:7752.6-7752.51" - case 1'1 - assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_converted_interface_dat_r - case - end - attribute \src "ls180.v:7756.2-7758.5" - switch \main_socbushandler_counter_converter2_next_value_ce - attribute \src "ls180.v:7756.6-7756.57" - case 1'1 - assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter_converter2_next_value - case - end - attribute \src "ls180.v:7759.2-7762.5" - switch \main_socbushandler_reset - attribute \src "ls180.v:7759.6-7759.30" + assign $0\tx_fifo_readable[0:0] \tx_fifo_readable + assign $0\tx_fifo_level0[4:0] \tx_fifo_level0 + assign $0\tx_fifo_produce[3:0] \tx_fifo_produce + assign $0\tx_fifo_consume[3:0] \tx_fifo_consume + assign $0\rx_fifo_readable[0:0] \rx_fifo_readable + assign $0\rx_fifo_level0[4:0] \rx_fifo_level0 + assign $0\rx_fifo_produce[3:0] \rx_fifo_produce + assign $0\rx_fifo_consume[3:0] \rx_fifo_consume + assign $0\gpio0_oe_storage[7:0] \gpio0_oe_storage + assign { } { } + assign $0\gpio0_out_storage[7:0] \gpio0_out_storage + assign { } { } + assign $0\gpio1_oe_storage[7:0] \gpio1_oe_storage + assign { } { } + assign $0\gpio1_out_storage[7:0] \gpio1_out_storage + assign { } { } + assign { } { } + assign $0\i2c_storage[2:0] \i2c_storage + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_libresocsim_adr[13:0] \libresocsim_libresocsim_adr + assign $0\libresocsim_libresocsim_we[0:0] \libresocsim_libresocsim_we + assign $0\libresocsim_libresocsim_dat_w[7:0] \libresocsim_libresocsim_dat_w + assign $0\libresocsim_grant[1:0] \libresocsim_grant + assign { } { } + assign $0\libresocsim_count[19:0] \libresocsim_count + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dummy[35:0] [0] $or$ls180.v:4286$1216_Y + assign $0\dummy[35:0] [1] $or$ls180.v:4287$1217_Y + assign $0\dummy[35:0] [2] $or$ls180.v:4288$1218_Y + assign $0\dummy[35:0] [3] $or$ls180.v:4289$1219_Y + assign $0\dummy[35:0] [4] $or$ls180.v:4290$1220_Y + assign $0\dummy[35:0] [5] $or$ls180.v:4291$1221_Y + assign $0\dummy[35:0] [6] $or$ls180.v:4292$1222_Y + assign $0\dummy[35:0] [7] $or$ls180.v:4293$1223_Y + assign $0\dummy[35:0] [8] $or$ls180.v:4294$1224_Y + assign $0\dummy[35:0] [9] $or$ls180.v:4295$1225_Y + assign $0\dummy[35:0] [10] $or$ls180.v:4296$1226_Y + assign $0\dummy[35:0] [11] $or$ls180.v:4297$1227_Y + assign $0\dummy[35:0] [12] $or$ls180.v:4298$1228_Y + assign $0\dummy[35:0] [13] $or$ls180.v:4299$1229_Y + assign $0\dummy[35:0] [14] $or$ls180.v:4300$1230_Y + assign $0\dummy[35:0] [15] $or$ls180.v:4301$1231_Y + assign $0\dummy[35:0] [16] $or$ls180.v:4302$1232_Y + assign $0\dummy[35:0] [17] $or$ls180.v:4303$1233_Y + assign $0\dummy[35:0] [18] $or$ls180.v:4304$1234_Y + assign $0\dummy[35:0] [19] $or$ls180.v:4305$1235_Y + assign $0\dummy[35:0] [20] $or$ls180.v:4306$1236_Y + assign $0\dummy[35:0] [21] $or$ls180.v:4307$1237_Y + assign $0\dummy[35:0] [22] $or$ls180.v:4308$1238_Y + assign $0\dummy[35:0] [23] $or$ls180.v:4309$1239_Y + assign $0\dummy[35:0] [24] $or$ls180.v:4310$1240_Y + assign $0\dummy[35:0] [25] $or$ls180.v:4311$1241_Y + assign $0\dummy[35:0] [26] $or$ls180.v:4312$1242_Y + assign $0\dummy[35:0] [27] $or$ls180.v:4313$1243_Y + assign $0\dummy[35:0] [28] $or$ls180.v:4314$1244_Y + assign $0\dummy[35:0] [29] $or$ls180.v:4315$1245_Y + assign $0\dummy[35:0] [30] $or$ls180.v:4316$1246_Y + assign $0\dummy[35:0] [31] $or$ls180.v:4317$1247_Y + assign $0\dummy[35:0] [32] $or$ls180.v:4318$1248_Y + assign $0\dummy[35:0] [33] $or$ls180.v:4319$1249_Y + assign $0\dummy[35:0] [34] $or$ls180.v:4320$1250_Y + assign $0\dummy[35:0] [35] $or$ls180.v:4321$1251_Y + assign $0\subfragments_converter0_state[0:0] \subfragments_converter0_next_state + assign $0\subfragments_converter1_state[0:0] \subfragments_converter1_next_state + assign $0\subfragments_converter2_state[0:0] \subfragments_converter2_next_state + assign $0\libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\libresocsim_zero_old_trigger[0:0] \libresocsim_zero_trigger + assign $0\ram_bus_ram_bus_ack[0:0] 1'0 + assign $0\rddata_en[2:0] { \rddata_en [1:0] \dfi_p0_rddata_en } + assign $0\dfi_p0_rddata_valid[0:0] \rddata_en [2] + assign $0\sdram_postponer_req_o[0:0] 1'0 + assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\sdram_cmd_payload_ba[1:0] 2'00 + assign $0\sdram_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_cmd_payload_ras[0:0] 1'0 + assign $0\sdram_cmd_payload_we[0:0] 1'0 + assign $0\sdram_sequencer_done1[0:0] 1'0 + assign $0\subfragments_refresher_state[1:0] \subfragments_refresher_next_state + assign $0\subfragments_bankmachine0_state[2:0] \subfragments_bankmachine0_next_state + assign $0\subfragments_bankmachine1_state[2:0] \subfragments_bankmachine1_next_state + assign $0\subfragments_bankmachine2_state[2:0] \subfragments_bankmachine2_next_state + assign $0\subfragments_bankmachine3_state[2:0] \subfragments_bankmachine3_next_state + assign $0\sdram_dfi_p0_cs_n[0:0] 1'0 + assign $0\sdram_dfi_p0_bank[1:0] \array_muxed0 + assign $0\sdram_dfi_p0_address[12:0] \array_muxed1 + assign $0\sdram_dfi_p0_cas_n[0:0] $not$ls180.v:4767$1351_Y + assign $0\sdram_dfi_p0_ras_n[0:0] $not$ls180.v:4768$1352_Y + assign $0\sdram_dfi_p0_we_n[0:0] $not$ls180.v:4769$1353_Y + assign $0\sdram_dfi_p0_rddata_en[0:0] \array_muxed5 + assign $0\sdram_dfi_p0_wrdata_en[0:0] \array_muxed6 + assign $0\subfragments_multiplexer_state[2:0] \subfragments_multiplexer_next_state + assign $0\subfragments_new_master_wdata_ready[0:0] $or$ls180.v:4803$1371_Y + assign $0\subfragments_new_master_rdata_valid0[0:0] $or$ls180.v:4804$1383_Y + assign $0\subfragments_new_master_rdata_valid1[0:0] \subfragments_new_master_rdata_valid0 + assign $0\subfragments_new_master_rdata_valid2[0:0] \subfragments_new_master_rdata_valid1 + assign $0\subfragments_new_master_rdata_valid3[0:0] \subfragments_new_master_rdata_valid2 + assign $0\subfragments_state[0:0] \subfragments_next_state + assign $0\uart_phy_sink_ready[0:0] 1'0 + assign $0\uart_phy_source_valid[0:0] 1'0 + assign $0\uart_phy_rx_r[0:0] \uart_phy_rx + assign $0\tx_old_trigger[0:0] \tx_trigger + assign $0\rx_old_trigger[0:0] \rx_trigger + assign $0\libresocsim_state[1:0] \libresocsim_next_state + assign $0\libresocsim_slave_sel_r[5:0] \libresocsim_slave_sel + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] 8'00000000 + assign $0\libresocsim_reset_re[0:0] \libresocsim_csrbank0_reset0_re + assign $0\libresocsim_scratch_re[0:0] \libresocsim_csrbank0_scratch0_re + assign $0\libresocsim_interface1_bank_bus_dat_r[7:0] 8'00000000 + assign $0\gpio0_oe_re[0:0] \libresocsim_csrbank1_oe0_re + assign $0\gpio0_out_re[0:0] \libresocsim_csrbank1_out0_re + assign $0\libresocsim_interface2_bank_bus_dat_r[7:0] 8'00000000 + assign $0\gpio1_oe_re[0:0] \libresocsim_csrbank2_oe0_re + assign $0\gpio1_out_re[0:0] \libresocsim_csrbank2_out0_re + assign $0\libresocsim_interface3_bank_bus_dat_r[7:0] 8'00000000 + assign $0\i2c_re[0:0] \libresocsim_csrbank3_w0_re + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] 8'00000000 + assign $0\sdram_re[0:0] \libresocsim_csrbank4_dfii_control0_re + assign $0\sdram_command_re[0:0] \libresocsim_csrbank4_dfii_pi0_command0_re + assign $0\sdram_address_re[0:0] \libresocsim_csrbank4_dfii_pi0_address0_re + assign $0\sdram_baddress_re[0:0] \libresocsim_csrbank4_dfii_pi0_baddress0_re + assign $0\sdram_wrdata_re[0:0] \libresocsim_csrbank4_dfii_pi0_wrdata0_re + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $0\libresocsim_load_re[0:0] \libresocsim_csrbank5_load0_re + assign $0\libresocsim_reload_re[0:0] \libresocsim_csrbank5_reload0_re + assign $0\libresocsim_en_re[0:0] \libresocsim_csrbank5_en0_re + assign $0\libresocsim_update_value_re[0:0] \libresocsim_csrbank5_update_value0_re + assign $0\libresocsim_eventmanager_re[0:0] \libresocsim_csrbank5_ev_enable0_re + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $0\eventmanager_re[0:0] \libresocsim_csrbank6_ev_enable0_re + assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] 8'00000000 + assign $0\uart_phy_re[0:0] \libresocsim_csrbank7_tuning_word0_re + assign $0\regs0[0:0] \libresocsim_libresoc_constraintmanager_uart_rx + assign $0\regs1[0:0] \regs0 + attribute \src "ls180.v:4322.2-4324.5" + switch $or$ls180.v:4322$1252_Y + attribute \src "ls180.v:4322.6-4322.84" + case 1'1 + assign $0\libresocsim_converter0_dat_r[63:0] \libresocsim_libresoc_ibus_dat_r + case + end + attribute \src "ls180.v:4326.2-4328.5" + switch \libresocsim_converter0_counter_subfragments_converter0_next_value_ce + attribute \src "ls180.v:4326.6-4326.74" + case 1'1 + assign $0\libresocsim_converter0_counter[0:0] \libresocsim_converter0_counter_subfragments_converter0_next_value + case + end + attribute \src "ls180.v:4329.2-4332.5" + switch \libresocsim_converter0_reset + attribute \src "ls180.v:4329.6-4329.34" + case 1'1 + assign $0\libresocsim_converter0_counter[0:0] 1'0 + assign $0\subfragments_converter0_state[0:0] 1'0 + case + end + attribute \src "ls180.v:4333.2-4335.5" + switch $or$ls180.v:4333$1253_Y + attribute \src "ls180.v:4333.6-4333.84" + case 1'1 + assign $0\libresocsim_converter1_dat_r[63:0] \libresocsim_libresoc_dbus_dat_r + case + end + attribute \src "ls180.v:4337.2-4339.5" + switch \libresocsim_converter1_counter_subfragments_converter1_next_value_ce + attribute \src "ls180.v:4337.6-4337.74" + case 1'1 + assign $0\libresocsim_converter1_counter[0:0] \libresocsim_converter1_counter_subfragments_converter1_next_value + case + end + attribute \src "ls180.v:4340.2-4343.5" + switch \libresocsim_converter1_reset + attribute \src "ls180.v:4340.6-4340.34" + case 1'1 + assign $0\libresocsim_converter1_counter[0:0] 1'0 + assign $0\subfragments_converter1_state[0:0] 1'0 + case + end + attribute \src "ls180.v:4344.2-4346.5" + switch $or$ls180.v:4344$1254_Y + attribute \src "ls180.v:4344.6-4344.84" + case 1'1 + assign $0\libresocsim_converter2_dat_r[63:0] \libresocsim_libresoc_jtag_wb_dat_r + case + end + attribute \src "ls180.v:4348.2-4350.5" + switch \libresocsim_converter2_counter_subfragments_converter2_next_value_ce + attribute \src "ls180.v:4348.6-4348.74" + case 1'1 + assign $0\libresocsim_converter2_counter[0:0] \libresocsim_converter2_counter_subfragments_converter2_next_value + case + end + attribute \src "ls180.v:4351.2-4354.5" + switch \libresocsim_converter2_reset + attribute \src "ls180.v:4351.6-4351.34" case 1'1 - assign $0\main_socbushandler_counter[0:0] 1'0 - assign $0\builder_converter2_state[0:0] 1'0 + assign $0\libresocsim_converter2_counter[0:0] 1'0 + assign $0\subfragments_converter2_state[0:0] 1'0 case end - attribute \src "ls180.v:7763.2-7767.5" - switch $ne$ls180.v:7763$2603_Y - attribute \src "ls180.v:7763.6-7763.53" + attribute \src "ls180.v:4355.2-4359.5" + switch $ne$ls180.v:4355$1255_Y + attribute \src "ls180.v:4355.6-4355.48" case 1'1 - attribute \src "ls180.v:7764.3-7766.6" - switch \main_libresocsim_bus_error - attribute \src "ls180.v:7764.7-7764.33" + attribute \src "ls180.v:4356.3-4358.6" + switch \libresocsim_bus_error + attribute \src "ls180.v:4356.7-4356.28" case 1'1 - assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7765$2604_Y + assign $0\libresocsim_bus_errors[31:0] $add$ls180.v:4357$1256_Y case end case end - attribute \src "ls180.v:7769.2-7771.5" - switch $and$ls180.v:7769$2607_Y - attribute \src "ls180.v:7769.6-7769.103" + attribute \src "ls180.v:4361.2-4363.5" + switch $and$ls180.v:4361$1259_Y + attribute \src "ls180.v:4361.6-4361.88" case 1'1 - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 + assign $0\libresocsim_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7772.2-7780.5" - switch \main_libresocsim_en_storage - attribute \src "ls180.v:7772.6-7772.33" + attribute \src "ls180.v:4364.2-4372.5" + switch \libresocsim_en_storage + attribute \src "ls180.v:4364.6-4364.28" case 1'1 - attribute \src "ls180.v:7773.3-7777.6" - switch $eq$ls180.v:7773$2608_Y - attribute \src "ls180.v:7773.7-7773.39" + attribute \src "ls180.v:4365.3-4369.6" + switch $eq$ls180.v:4365$1260_Y + attribute \src "ls180.v:4365.7-4365.34" case 1'1 - assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage - attribute \src "ls180.v:7775.7-7775.11" + assign $0\libresocsim_value[31:0] \libresocsim_reload_storage + attribute \src "ls180.v:4367.7-4367.11" case - assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7776$2609_Y + assign $0\libresocsim_value[31:0] $sub$ls180.v:4368$1261_Y end - attribute \src "ls180.v:7778.6-7778.10" + attribute \src "ls180.v:4370.6-4370.10" case - assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage + assign $0\libresocsim_value[31:0] \libresocsim_load_storage end - attribute \src "ls180.v:7781.2-7783.5" - switch \main_libresocsim_update_value_re - attribute \src "ls180.v:7781.6-7781.38" + attribute \src "ls180.v:4373.2-4375.5" + switch \libresocsim_update_value_re + attribute \src "ls180.v:4373.6-4373.33" case 1'1 - assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value + assign $0\libresocsim_value_status[31:0] \libresocsim_value case end - attribute \src "ls180.v:7784.2-7786.5" - switch \main_libresocsim_zero_clear - attribute \src "ls180.v:7784.6-7784.33" + attribute \src "ls180.v:4376.2-4378.5" + switch \libresocsim_zero_clear + attribute \src "ls180.v:4376.6-4376.28" case 1'1 - assign $0\main_libresocsim_zero_pending[0:0] 1'0 + assign $0\libresocsim_zero_pending[0:0] 1'0 case end - attribute \src "ls180.v:7788.2-7790.5" - switch $and$ls180.v:7788$2611_Y - attribute \src "ls180.v:7788.6-7788.76" + attribute \src "ls180.v:4380.2-4382.5" + switch $and$ls180.v:4380$1263_Y + attribute \src "ls180.v:4380.6-4380.66" case 1'1 - assign $0\main_libresocsim_zero_pending[0:0] 1'1 + assign $0\libresocsim_zero_pending[0:0] 1'1 case end - attribute \src "ls180.v:7792.2-7794.5" - switch $and$ls180.v:7792$2614_Y - attribute \src "ls180.v:7792.6-7792.100" + attribute \src "ls180.v:4384.2-4386.5" + switch $and$ls180.v:4384$1266_Y + attribute \src "ls180.v:4384.6-4384.76" case 1'1 - assign $0\main_interface0_ram_bus_ack[0:0] 1'1 + assign $0\ram_bus_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7796.2-7798.5" - switch $and$ls180.v:7796$2617_Y - attribute \src "ls180.v:7796.6-7796.100" + attribute \src "ls180.v:4389.2-4391.5" + switch \sdram_inti_p0_rddata_valid + attribute \src "ls180.v:4389.6-4389.32" case 1'1 - assign $0\main_interface1_ram_bus_ack[0:0] 1'1 + assign $0\sdram_status[15:0] \sdram_inti_p0_rddata case end - attribute \src "ls180.v:7800.2-7802.5" - switch $and$ls180.v:7800$2620_Y - attribute \src "ls180.v:7800.6-7800.100" + attribute \src "ls180.v:4392.2-4396.5" + switch $and$ls180.v:4392$1268_Y + attribute \src "ls180.v:4392.6-4392.47" case 1'1 - assign $0\main_interface2_ram_bus_ack[0:0] 1'1 + assign $0\sdram_timer_count1[9:0] $sub$ls180.v:4393$1269_Y + attribute \src "ls180.v:4394.6-4394.10" case + assign $0\sdram_timer_count1[9:0] 10'1100001101 end - attribute \src "ls180.v:7804.2-7806.5" - switch $and$ls180.v:7804$2623_Y - attribute \src "ls180.v:7804.6-7804.100" + attribute \src "ls180.v:4398.2-4404.5" + switch \sdram_postponer_req_i + attribute \src "ls180.v:4398.6-4398.27" case 1'1 - assign $0\main_interface3_ram_bus_ack[0:0] 1'1 - case - end - attribute \src "ls180.v:7809.2-7811.5" - switch \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:7809.6-7809.37" - case 1'1 - assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata - case - end - attribute \src "ls180.v:7812.2-7816.5" - switch $and$ls180.v:7812$2625_Y - attribute \src "ls180.v:7812.6-7812.57" - case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7813$2626_Y - attribute \src "ls180.v:7814.6-7814.10" - case - assign $0\main_sdram_timer_count1[9:0] 10'1100001101 - end - attribute \src "ls180.v:7818.2-7824.5" - switch \main_sdram_postponer_req_i - attribute \src "ls180.v:7818.6-7818.32" - case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7819$2627_Y - attribute \src "ls180.v:7820.3-7823.6" - switch $eq$ls180.v:7820$2628_Y - attribute \src "ls180.v:7820.7-7820.43" + assign $0\sdram_postponer_count[0:0] $sub$ls180.v:4399$1270_Y + attribute \src "ls180.v:4400.3-4403.6" + switch $eq$ls180.v:4400$1271_Y + attribute \src "ls180.v:4400.7-4400.38" case 1'1 - assign $0\main_sdram_postponer_count[0:0] 1'0 - assign $0\main_sdram_postponer_req_o[0:0] 1'1 + assign $0\sdram_postponer_count[0:0] 1'0 + assign $0\sdram_postponer_req_o[0:0] 1'1 case end case end - attribute \src "ls180.v:7825.2-7833.5" - switch \main_sdram_sequencer_start0 - attribute \src "ls180.v:7825.6-7825.33" + attribute \src "ls180.v:4405.2-4413.5" + switch \sdram_sequencer_start0 + attribute \src "ls180.v:4405.6-4405.28" case 1'1 - assign $0\main_sdram_sequencer_count[0:0] 1'0 - attribute \src "ls180.v:7827.6-7827.10" + assign $0\sdram_sequencer_count[0:0] 1'0 + attribute \src "ls180.v:4407.6-4407.10" case - attribute \src "ls180.v:7828.3-7832.6" - switch \main_sdram_sequencer_done1 - attribute \src "ls180.v:7828.7-7828.33" + attribute \src "ls180.v:4408.3-4412.6" + switch \sdram_sequencer_done1 + attribute \src "ls180.v:4408.7-4408.28" case 1'1 - attribute \src "ls180.v:7829.4-7831.7" - switch $ne$ls180.v:7829$2629_Y - attribute \src "ls180.v:7829.8-7829.44" + attribute \src "ls180.v:4409.4-4411.7" + switch $ne$ls180.v:4409$1272_Y + attribute \src "ls180.v:4409.8-4409.39" case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7830$2630_Y + assign $0\sdram_sequencer_count[0:0] $sub$ls180.v:4410$1273_Y case end case end end - attribute \src "ls180.v:7840.2-7846.5" - switch $and$ls180.v:7840$2632_Y - attribute \src "ls180.v:7840.6-7840.76" + attribute \src "ls180.v:4420.2-4426.5" + switch $and$ls180.v:4420$1275_Y + attribute \src "ls180.v:4420.6-4420.66" case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_cmd_payload_we[0:0] 1'1 + assign $0\sdram_cmd_payload_a[12:0] 13'0010000000000 + assign $0\sdram_cmd_payload_ba[1:0] 2'00 + assign $0\sdram_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_cmd_payload_ras[0:0] 1'1 + assign $0\sdram_cmd_payload_we[0:0] 1'1 case end - attribute \src "ls180.v:7847.2-7853.5" - switch $eq$ls180.v:7847$2633_Y - attribute \src "ls180.v:7847.6-7847.44" + attribute \src "ls180.v:4427.2-4433.5" + switch $eq$ls180.v:4427$1276_Y + attribute \src "ls180.v:4427.6-4427.39" case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\sdram_cmd_payload_ba[1:0] 2'00 + assign $0\sdram_cmd_payload_cas[0:0] 1'1 + assign $0\sdram_cmd_payload_ras[0:0] 1'1 + assign $0\sdram_cmd_payload_we[0:0] 1'0 case end - attribute \src "ls180.v:7854.2-7861.5" - switch $eq$ls180.v:7854$2634_Y - attribute \src "ls180.v:7854.6-7854.44" + attribute \src "ls180.v:4434.2-4441.5" + switch $eq$ls180.v:4434$1277_Y + attribute \src "ls180.v:4434.6-4434.39" case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'1 + assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\sdram_cmd_payload_ba[1:0] 2'00 + assign $0\sdram_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_cmd_payload_ras[0:0] 1'0 + assign $0\sdram_cmd_payload_we[0:0] 1'0 + assign $0\sdram_sequencer_done1[0:0] 1'1 case end - attribute \src "ls180.v:7862.2-7872.5" - switch $eq$ls180.v:7862$2635_Y - attribute \src "ls180.v:7862.6-7862.44" + attribute \src "ls180.v:4442.2-4452.5" + switch $eq$ls180.v:4442$1278_Y + attribute \src "ls180.v:4442.6-4442.39" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - attribute \src "ls180.v:7864.6-7864.10" + assign $0\sdram_sequencer_counter[3:0] 4'0000 + attribute \src "ls180.v:4444.6-4444.10" case - attribute \src "ls180.v:7865.3-7871.6" - switch $ne$ls180.v:7865$2636_Y - attribute \src "ls180.v:7865.7-7865.45" + attribute \src "ls180.v:4445.3-4451.6" + switch $ne$ls180.v:4445$1279_Y + attribute \src "ls180.v:4445.7-4445.40" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7866$2637_Y - attribute \src "ls180.v:7867.7-7867.11" + assign $0\sdram_sequencer_counter[3:0] $add$ls180.v:4446$1280_Y + attribute \src "ls180.v:4447.7-4447.11" case - attribute \src "ls180.v:7868.4-7870.7" - switch \main_sdram_sequencer_start1 - attribute \src "ls180.v:7868.8-7868.35" + attribute \src "ls180.v:4448.4-4450.7" + switch \sdram_sequencer_start1 + attribute \src "ls180.v:4448.8-4448.30" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] 4'0001 + assign $0\sdram_sequencer_counter[3:0] 4'0001 case end end end - attribute \src "ls180.v:7874.2-7881.5" - switch \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:7874.6-7874.39" + attribute \src "ls180.v:4454.2-4461.5" + switch \sdram_bankmachine0_row_close + attribute \src "ls180.v:4454.6-4454.34" case 1'1 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - attribute \src "ls180.v:7876.6-7876.10" + assign $0\sdram_bankmachine0_row_opened[0:0] 1'0 + attribute \src "ls180.v:4456.6-4456.10" case - attribute \src "ls180.v:7877.3-7880.6" - switch \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:7877.7-7877.39" + attribute \src "ls180.v:4457.3-4460.6" + switch \sdram_bankmachine0_row_open + attribute \src "ls180.v:4457.7-4457.34" case 1'1 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + assign $0\sdram_bankmachine0_row_opened[0:0] 1'1 + assign $0\sdram_bankmachine0_row[12:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7882.2-7884.5" - switch $and$ls180.v:7882$2640_Y - attribute \src "ls180.v:7882.6-7882.191" + attribute \src "ls180.v:4462.2-4464.5" + switch $and$ls180.v:4462$1283_Y + attribute \src "ls180.v:4462.6-4462.176" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7883$2641_Y + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4463$1284_Y case end - attribute \src "ls180.v:7885.2-7887.5" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7885.6-7885.58" + attribute \src "ls180.v:4465.2-4467.5" + switch \sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4465.6-4465.53" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7886$2642_Y + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4466$1285_Y case end - attribute \src "ls180.v:7888.2-7896.5" - switch $and$ls180.v:7888$2645_Y - attribute \src "ls180.v:7888.6-7888.191" + attribute \src "ls180.v:4468.2-4476.5" + switch $and$ls180.v:4468$1288_Y + attribute \src "ls180.v:4468.6-4468.176" case 1'1 - attribute \src "ls180.v:7889.3-7891.6" - switch $not$ls180.v:7889$2646_Y - attribute \src "ls180.v:7889.7-7889.62" + attribute \src "ls180.v:4469.3-4471.6" + switch $not$ls180.v:4469$1289_Y + attribute \src "ls180.v:4469.7-4469.57" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7890$2647_Y + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4470$1290_Y case end - attribute \src "ls180.v:7892.6-7892.10" + attribute \src "ls180.v:4472.6-4472.10" case - attribute \src "ls180.v:7893.3-7895.6" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7893.7-7893.59" + attribute \src "ls180.v:4473.3-4475.6" + switch \sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4473.7-4473.54" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7894$2648_Y + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4474$1291_Y case end end - attribute \src "ls180.v:7897.2-7903.5" - switch $or$ls180.v:7897$2650_Y - attribute \src "ls180.v:7897.6-7897.108" + attribute \src "ls180.v:4477.2-4483.5" + switch $or$ls180.v:4477$1293_Y + attribute \src "ls180.v:4477.6-4477.98" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + assign $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] \sdram_bankmachine0_cmd_buffer_sink_valid + assign $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] \sdram_bankmachine0_cmd_buffer_sink_first + assign $0\sdram_bankmachine0_cmd_buffer_source_last[0:0] \sdram_bankmachine0_cmd_buffer_sink_last + assign $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine0_cmd_buffer_sink_payload_we + assign $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine0_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7904.2-7918.5" - switch \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:7904.6-7904.43" + attribute \src "ls180.v:4484.2-4498.5" + switch \sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:4484.6-4484.38" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7906.3-7910.6" + assign $0\sdram_bankmachine0_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:4486.3-4490.6" switch 1'0 - attribute \src "ls180.v:7908.7-7908.11" + attribute \src "ls180.v:4488.7-4488.11" case - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7911.6-7911.10" + attribute \src "ls180.v:4491.6-4491.10" case - attribute \src "ls180.v:7912.3-7917.6" - switch $not$ls180.v:7912$2651_Y - attribute \src "ls180.v:7912.7-7912.47" + attribute \src "ls180.v:4492.3-4497.6" + switch $not$ls180.v:4492$1294_Y + attribute \src "ls180.v:4492.7-4492.42" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7913$2652_Y - attribute \src "ls180.v:7914.4-7916.7" - switch $eq$ls180.v:7914$2653_Y - attribute \src "ls180.v:7914.8-7914.55" + assign $0\sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:4493$1295_Y + attribute \src "ls180.v:4494.4-4496.7" + switch $eq$ls180.v:4494$1296_Y + attribute \src "ls180.v:4494.8-4494.50" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 + assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'1 case end case end end - attribute \src "ls180.v:7920.2-7927.5" - switch \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:7920.6-7920.39" + attribute \src "ls180.v:4500.2-4507.5" + switch \sdram_bankmachine1_row_close + attribute \src "ls180.v:4500.6-4500.34" case 1'1 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - attribute \src "ls180.v:7922.6-7922.10" + assign $0\sdram_bankmachine1_row_opened[0:0] 1'0 + attribute \src "ls180.v:4502.6-4502.10" case - attribute \src "ls180.v:7923.3-7926.6" - switch \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:7923.7-7923.39" + attribute \src "ls180.v:4503.3-4506.6" + switch \sdram_bankmachine1_row_open + attribute \src "ls180.v:4503.7-4503.34" case 1'1 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + assign $0\sdram_bankmachine1_row_opened[0:0] 1'1 + assign $0\sdram_bankmachine1_row[12:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7928.2-7930.5" - switch $and$ls180.v:7928$2656_Y - attribute \src "ls180.v:7928.6-7928.191" + attribute \src "ls180.v:4508.2-4510.5" + switch $and$ls180.v:4508$1299_Y + attribute \src "ls180.v:4508.6-4508.176" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7929$2657_Y + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4509$1300_Y case end - attribute \src "ls180.v:7931.2-7933.5" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7931.6-7931.58" + attribute \src "ls180.v:4511.2-4513.5" + switch \sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4511.6-4511.53" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7932$2658_Y + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4512$1301_Y case end - attribute \src "ls180.v:7934.2-7942.5" - switch $and$ls180.v:7934$2661_Y - attribute \src "ls180.v:7934.6-7934.191" + attribute \src "ls180.v:4514.2-4522.5" + switch $and$ls180.v:4514$1304_Y + attribute \src "ls180.v:4514.6-4514.176" case 1'1 - attribute \src "ls180.v:7935.3-7937.6" - switch $not$ls180.v:7935$2662_Y - attribute \src "ls180.v:7935.7-7935.62" + attribute \src "ls180.v:4515.3-4517.6" + switch $not$ls180.v:4515$1305_Y + attribute \src "ls180.v:4515.7-4515.57" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7936$2663_Y + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4516$1306_Y case end - attribute \src "ls180.v:7938.6-7938.10" + attribute \src "ls180.v:4518.6-4518.10" case - attribute \src "ls180.v:7939.3-7941.6" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7939.7-7939.59" + attribute \src "ls180.v:4519.3-4521.6" + switch \sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4519.7-4519.54" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7940$2664_Y + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4520$1307_Y case end end - attribute \src "ls180.v:7943.2-7949.5" - switch $or$ls180.v:7943$2666_Y - attribute \src "ls180.v:7943.6-7943.108" + attribute \src "ls180.v:4523.2-4529.5" + switch $or$ls180.v:4523$1309_Y + attribute \src "ls180.v:4523.6-4523.98" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + assign $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] \sdram_bankmachine1_cmd_buffer_sink_valid + assign $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] \sdram_bankmachine1_cmd_buffer_sink_first + assign $0\sdram_bankmachine1_cmd_buffer_source_last[0:0] \sdram_bankmachine1_cmd_buffer_sink_last + assign $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine1_cmd_buffer_sink_payload_we + assign $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine1_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7950.2-7964.5" - switch \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:7950.6-7950.43" + attribute \src "ls180.v:4530.2-4544.5" + switch \sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:4530.6-4530.38" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7952.3-7956.6" + assign $0\sdram_bankmachine1_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:4532.3-4536.6" switch 1'0 - attribute \src "ls180.v:7954.7-7954.11" + attribute \src "ls180.v:4534.7-4534.11" case - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7957.6-7957.10" + attribute \src "ls180.v:4537.6-4537.10" case - attribute \src "ls180.v:7958.3-7963.6" - switch $not$ls180.v:7958$2667_Y - attribute \src "ls180.v:7958.7-7958.47" + attribute \src "ls180.v:4538.3-4543.6" + switch $not$ls180.v:4538$1310_Y + attribute \src "ls180.v:4538.7-4538.42" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7959$2668_Y - attribute \src "ls180.v:7960.4-7962.7" - switch $eq$ls180.v:7960$2669_Y - attribute \src "ls180.v:7960.8-7960.55" + assign $0\sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:4539$1311_Y + attribute \src "ls180.v:4540.4-4542.7" + switch $eq$ls180.v:4540$1312_Y + attribute \src "ls180.v:4540.8-4540.50" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 + assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'1 case end case end end - attribute \src "ls180.v:7966.2-7973.5" - switch \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:7966.6-7966.39" + attribute \src "ls180.v:4546.2-4553.5" + switch \sdram_bankmachine2_row_close + attribute \src "ls180.v:4546.6-4546.34" case 1'1 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - attribute \src "ls180.v:7968.6-7968.10" + assign $0\sdram_bankmachine2_row_opened[0:0] 1'0 + attribute \src "ls180.v:4548.6-4548.10" case - attribute \src "ls180.v:7969.3-7972.6" - switch \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:7969.7-7969.39" + attribute \src "ls180.v:4549.3-4552.6" + switch \sdram_bankmachine2_row_open + attribute \src "ls180.v:4549.7-4549.34" case 1'1 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + assign $0\sdram_bankmachine2_row_opened[0:0] 1'1 + assign $0\sdram_bankmachine2_row[12:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7974.2-7976.5" - switch $and$ls180.v:7974$2672_Y - attribute \src "ls180.v:7974.6-7974.191" + attribute \src "ls180.v:4554.2-4556.5" + switch $and$ls180.v:4554$1315_Y + attribute \src "ls180.v:4554.6-4554.176" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7975$2673_Y + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4555$1316_Y case end - attribute \src "ls180.v:7977.2-7979.5" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7977.6-7977.58" + attribute \src "ls180.v:4557.2-4559.5" + switch \sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4557.6-4557.53" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7978$2674_Y + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4558$1317_Y case end - attribute \src "ls180.v:7980.2-7988.5" - switch $and$ls180.v:7980$2677_Y - attribute \src "ls180.v:7980.6-7980.191" + attribute \src "ls180.v:4560.2-4568.5" + switch $and$ls180.v:4560$1320_Y + attribute \src "ls180.v:4560.6-4560.176" case 1'1 - attribute \src "ls180.v:7981.3-7983.6" - switch $not$ls180.v:7981$2678_Y - attribute \src "ls180.v:7981.7-7981.62" + attribute \src "ls180.v:4561.3-4563.6" + switch $not$ls180.v:4561$1321_Y + attribute \src "ls180.v:4561.7-4561.57" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7982$2679_Y + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4562$1322_Y case end - attribute \src "ls180.v:7984.6-7984.10" + attribute \src "ls180.v:4564.6-4564.10" case - attribute \src "ls180.v:7985.3-7987.6" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7985.7-7985.59" + attribute \src "ls180.v:4565.3-4567.6" + switch \sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4565.7-4565.54" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7986$2680_Y + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4566$1323_Y case end end - attribute \src "ls180.v:7989.2-7995.5" - switch $or$ls180.v:7989$2682_Y - attribute \src "ls180.v:7989.6-7989.108" + attribute \src "ls180.v:4569.2-4575.5" + switch $or$ls180.v:4569$1325_Y + attribute \src "ls180.v:4569.6-4569.98" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + assign $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] \sdram_bankmachine2_cmd_buffer_sink_valid + assign $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] \sdram_bankmachine2_cmd_buffer_sink_first + assign $0\sdram_bankmachine2_cmd_buffer_source_last[0:0] \sdram_bankmachine2_cmd_buffer_sink_last + assign $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine2_cmd_buffer_sink_payload_we + assign $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine2_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7996.2-8010.5" - switch \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:7996.6-7996.43" + attribute \src "ls180.v:4576.2-4590.5" + switch \sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:4576.6-4576.38" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7998.3-8002.6" + assign $0\sdram_bankmachine2_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:4578.3-4582.6" switch 1'0 - attribute \src "ls180.v:8000.7-8000.11" + attribute \src "ls180.v:4580.7-4580.11" case - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:8003.6-8003.10" + attribute \src "ls180.v:4583.6-4583.10" case - attribute \src "ls180.v:8004.3-8009.6" - switch $not$ls180.v:8004$2683_Y - attribute \src "ls180.v:8004.7-8004.47" + attribute \src "ls180.v:4584.3-4589.6" + switch $not$ls180.v:4584$1326_Y + attribute \src "ls180.v:4584.7-4584.42" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:8005$2684_Y - attribute \src "ls180.v:8006.4-8008.7" - switch $eq$ls180.v:8006$2685_Y - attribute \src "ls180.v:8006.8-8006.55" + assign $0\sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:4585$1327_Y + attribute \src "ls180.v:4586.4-4588.7" + switch $eq$ls180.v:4586$1328_Y + attribute \src "ls180.v:4586.8-4586.50" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 + assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'1 case end case end end - attribute \src "ls180.v:8012.2-8019.5" - switch \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:8012.6-8012.39" + attribute \src "ls180.v:4592.2-4599.5" + switch \sdram_bankmachine3_row_close + attribute \src "ls180.v:4592.6-4592.34" case 1'1 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - attribute \src "ls180.v:8014.6-8014.10" + assign $0\sdram_bankmachine3_row_opened[0:0] 1'0 + attribute \src "ls180.v:4594.6-4594.10" case - attribute \src "ls180.v:8015.3-8018.6" - switch \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:8015.7-8015.39" + attribute \src "ls180.v:4595.3-4598.6" + switch \sdram_bankmachine3_row_open + attribute \src "ls180.v:4595.7-4595.34" case 1'1 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + assign $0\sdram_bankmachine3_row_opened[0:0] 1'1 + assign $0\sdram_bankmachine3_row[12:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:8020.2-8022.5" - switch $and$ls180.v:8020$2688_Y - attribute \src "ls180.v:8020.6-8020.191" + attribute \src "ls180.v:4600.2-4602.5" + switch $and$ls180.v:4600$1331_Y + attribute \src "ls180.v:4600.6-4600.176" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:8021$2689_Y + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4601$1332_Y case end - attribute \src "ls180.v:8023.2-8025.5" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:8023.6-8023.58" + attribute \src "ls180.v:4603.2-4605.5" + switch \sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4603.6-4603.53" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:8024$2690_Y + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4604$1333_Y case end - attribute \src "ls180.v:8026.2-8034.5" - switch $and$ls180.v:8026$2693_Y - attribute \src "ls180.v:8026.6-8026.191" + attribute \src "ls180.v:4606.2-4614.5" + switch $and$ls180.v:4606$1336_Y + attribute \src "ls180.v:4606.6-4606.176" case 1'1 - attribute \src "ls180.v:8027.3-8029.6" - switch $not$ls180.v:8027$2694_Y - attribute \src "ls180.v:8027.7-8027.62" + attribute \src "ls180.v:4607.3-4609.6" + switch $not$ls180.v:4607$1337_Y + attribute \src "ls180.v:4607.7-4607.57" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:8028$2695_Y + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4608$1338_Y case end - attribute \src "ls180.v:8030.6-8030.10" + attribute \src "ls180.v:4610.6-4610.10" case - attribute \src "ls180.v:8031.3-8033.6" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:8031.7-8031.59" + attribute \src "ls180.v:4611.3-4613.6" + switch \sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4611.7-4611.54" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:8032$2696_Y + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4612$1339_Y case end end - attribute \src "ls180.v:8035.2-8041.5" - switch $or$ls180.v:8035$2698_Y - attribute \src "ls180.v:8035.6-8035.108" + attribute \src "ls180.v:4615.2-4621.5" + switch $or$ls180.v:4615$1341_Y + attribute \src "ls180.v:4615.6-4615.98" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + assign $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] \sdram_bankmachine3_cmd_buffer_sink_valid + assign $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] \sdram_bankmachine3_cmd_buffer_sink_first + assign $0\sdram_bankmachine3_cmd_buffer_source_last[0:0] \sdram_bankmachine3_cmd_buffer_sink_last + assign $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine3_cmd_buffer_sink_payload_we + assign $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine3_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:8042.2-8056.5" - switch \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:8042.6-8042.43" + attribute \src "ls180.v:4622.2-4636.5" + switch \sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:4622.6-4622.38" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:8044.3-8048.6" + assign $0\sdram_bankmachine3_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:4624.3-4628.6" switch 1'0 - attribute \src "ls180.v:8046.7-8046.11" + attribute \src "ls180.v:4626.7-4626.11" case - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:8049.6-8049.10" + attribute \src "ls180.v:4629.6-4629.10" case - attribute \src "ls180.v:8050.3-8055.6" - switch $not$ls180.v:8050$2699_Y - attribute \src "ls180.v:8050.7-8050.47" + attribute \src "ls180.v:4630.3-4635.6" + switch $not$ls180.v:4630$1342_Y + attribute \src "ls180.v:4630.7-4630.42" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:8051$2700_Y - attribute \src "ls180.v:8052.4-8054.7" - switch $eq$ls180.v:8052$2701_Y - attribute \src "ls180.v:8052.8-8052.55" + assign $0\sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:4631$1343_Y + attribute \src "ls180.v:4632.4-4634.7" + switch $eq$ls180.v:4632$1344_Y + attribute \src "ls180.v:4632.8-4632.50" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 + assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'1 case end case end end - attribute \src "ls180.v:8058.2-8064.5" - switch $not$ls180.v:8058$2702_Y - attribute \src "ls180.v:8058.6-8058.23" + attribute \src "ls180.v:4638.2-4644.5" + switch $not$ls180.v:4638$1345_Y + attribute \src "ls180.v:4638.6-4638.18" case 1'1 - assign $0\main_sdram_time0[4:0] 5'11111 - attribute \src "ls180.v:8060.6-8060.10" + assign $0\sdram_time0[4:0] 5'11111 + attribute \src "ls180.v:4640.6-4640.10" case - attribute \src "ls180.v:8061.3-8063.6" - switch $not$ls180.v:8061$2703_Y - attribute \src "ls180.v:8061.7-8061.30" + attribute \src "ls180.v:4641.3-4643.6" + switch $not$ls180.v:4641$1346_Y + attribute \src "ls180.v:4641.7-4641.25" case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:8062$2704_Y + assign $0\sdram_time0[4:0] $sub$ls180.v:4642$1347_Y case end end - attribute \src "ls180.v:8065.2-8071.5" - switch $not$ls180.v:8065$2705_Y - attribute \src "ls180.v:8065.6-8065.23" + attribute \src "ls180.v:4645.2-4651.5" + switch $not$ls180.v:4645$1348_Y + attribute \src "ls180.v:4645.6-4645.18" case 1'1 - assign $0\main_sdram_time1[3:0] 4'1111 - attribute \src "ls180.v:8067.6-8067.10" + assign $0\sdram_time1[3:0] 4'1111 + attribute \src "ls180.v:4647.6-4647.10" case - attribute \src "ls180.v:8068.3-8070.6" - switch $not$ls180.v:8068$2706_Y - attribute \src "ls180.v:8068.7-8068.30" + attribute \src "ls180.v:4648.3-4650.6" + switch $not$ls180.v:4648$1349_Y + attribute \src "ls180.v:4648.7-4648.25" case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:8069$2707_Y + assign $0\sdram_time1[3:0] $sub$ls180.v:4649$1350_Y case end end - attribute \src "ls180.v:8072.2-8127.5" - switch \main_sdram_choose_cmd_ce - attribute \src "ls180.v:8072.6-8072.30" + attribute \src "ls180.v:4652.2-4707.5" + switch \sdram_choose_cmd_ce + attribute \src "ls180.v:4652.6-4652.25" case 1'1 - attribute \src "ls180.v:8073.3-8126.10" - switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:4653.3-4706.10" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:8075.5-8085.8" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:8075.9-8075.41" + attribute \src "ls180.v:4655.5-4665.8" + switch \sdram_choose_cmd_request [1] + attribute \src "ls180.v:4655.9-4655.36" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:8077.9-8077.13" + assign $0\sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:4657.9-4657.13" case - attribute \src "ls180.v:8078.6-8084.9" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:8078.10-8078.42" + attribute \src "ls180.v:4658.6-4664.9" + switch \sdram_choose_cmd_request [2] + attribute \src "ls180.v:4658.10-4658.37" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:8080.10-8080.14" + assign $0\sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:4660.10-4660.14" case - attribute \src "ls180.v:8081.7-8083.10" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:8081.11-8081.43" + attribute \src "ls180.v:4661.7-4663.10" + switch \sdram_choose_cmd_request [3] + attribute \src "ls180.v:4661.11-4661.38" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + assign $0\sdram_choose_cmd_grant[1:0] 2'11 case end end end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:8088.5-8098.8" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:8088.9-8088.41" + attribute \src "ls180.v:4668.5-4678.8" + switch \sdram_choose_cmd_request [2] + attribute \src "ls180.v:4668.9-4668.36" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:8090.9-8090.13" + assign $0\sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:4670.9-4670.13" case - attribute \src "ls180.v:8091.6-8097.9" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:8091.10-8091.42" + attribute \src "ls180.v:4671.6-4677.9" + switch \sdram_choose_cmd_request [3] + attribute \src "ls180.v:4671.10-4671.37" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:8093.10-8093.14" + assign $0\sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:4673.10-4673.14" case - attribute \src "ls180.v:8094.7-8096.10" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:8094.11-8094.43" + attribute \src "ls180.v:4674.7-4676.10" + switch \sdram_choose_cmd_request [0] + attribute \src "ls180.v:4674.11-4674.38" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + assign $0\sdram_choose_cmd_grant[1:0] 2'00 case end end end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:8101.5-8111.8" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:8101.9-8101.41" + attribute \src "ls180.v:4681.5-4691.8" + switch \sdram_choose_cmd_request [3] + attribute \src "ls180.v:4681.9-4681.36" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:8103.9-8103.13" + assign $0\sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:4683.9-4683.13" case - attribute \src "ls180.v:8104.6-8110.9" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:8104.10-8104.42" + attribute \src "ls180.v:4684.6-4690.9" + switch \sdram_choose_cmd_request [0] + attribute \src "ls180.v:4684.10-4684.37" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:8106.10-8106.14" + assign $0\sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:4686.10-4686.14" case - attribute \src "ls180.v:8107.7-8109.10" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:8107.11-8107.43" + attribute \src "ls180.v:4687.7-4689.10" + switch \sdram_choose_cmd_request [1] + attribute \src "ls180.v:4687.11-4687.38" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + assign $0\sdram_choose_cmd_grant[1:0] 2'01 case end end end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:8114.5-8124.8" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:8114.9-8114.41" + attribute \src "ls180.v:4694.5-4704.8" + switch \sdram_choose_cmd_request [0] + attribute \src "ls180.v:4694.9-4694.36" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:8116.9-8116.13" + assign $0\sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:4696.9-4696.13" case - attribute \src "ls180.v:8117.6-8123.9" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:8117.10-8117.42" + attribute \src "ls180.v:4697.6-4703.9" + switch \sdram_choose_cmd_request [1] + attribute \src "ls180.v:4697.10-4697.37" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:8119.10-8119.14" + assign $0\sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:4699.10-4699.14" case - attribute \src "ls180.v:8120.7-8122.10" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:8120.11-8120.43" + attribute \src "ls180.v:4700.7-4702.10" + switch \sdram_choose_cmd_request [2] + attribute \src "ls180.v:4700.11-4700.38" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + assign $0\sdram_choose_cmd_grant[1:0] 2'10 case end end @@ -299001,108 +267109,108 @@ module \ls180 end case end - attribute \src "ls180.v:8128.2-8183.5" - switch \main_sdram_choose_req_ce - attribute \src "ls180.v:8128.6-8128.30" + attribute \src "ls180.v:4708.2-4763.5" + switch \sdram_choose_req_ce + attribute \src "ls180.v:4708.6-4708.25" case 1'1 - attribute \src "ls180.v:8129.3-8182.10" - switch \main_sdram_choose_req_grant + attribute \src "ls180.v:4709.3-4762.10" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:8131.5-8141.8" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:8131.9-8131.41" + attribute \src "ls180.v:4711.5-4721.8" + switch \sdram_choose_req_request [1] + attribute \src "ls180.v:4711.9-4711.36" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:8133.9-8133.13" + assign $0\sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:4713.9-4713.13" case - attribute \src "ls180.v:8134.6-8140.9" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:8134.10-8134.42" + attribute \src "ls180.v:4714.6-4720.9" + switch \sdram_choose_req_request [2] + attribute \src "ls180.v:4714.10-4714.37" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:8136.10-8136.14" + assign $0\sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:4716.10-4716.14" case - attribute \src "ls180.v:8137.7-8139.10" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:8137.11-8137.43" + attribute \src "ls180.v:4717.7-4719.10" + switch \sdram_choose_req_request [3] + attribute \src "ls180.v:4717.11-4717.38" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 + assign $0\sdram_choose_req_grant[1:0] 2'11 case end end end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:8144.5-8154.8" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:8144.9-8144.41" + attribute \src "ls180.v:4724.5-4734.8" + switch \sdram_choose_req_request [2] + attribute \src "ls180.v:4724.9-4724.36" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:8146.9-8146.13" + assign $0\sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:4726.9-4726.13" case - attribute \src "ls180.v:8147.6-8153.9" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:8147.10-8147.42" + attribute \src "ls180.v:4727.6-4733.9" + switch \sdram_choose_req_request [3] + attribute \src "ls180.v:4727.10-4727.37" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:8149.10-8149.14" + assign $0\sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:4729.10-4729.14" case - attribute \src "ls180.v:8150.7-8152.10" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:8150.11-8150.43" + attribute \src "ls180.v:4730.7-4732.10" + switch \sdram_choose_req_request [0] + attribute \src "ls180.v:4730.11-4730.38" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 + assign $0\sdram_choose_req_grant[1:0] 2'00 case end end end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:8157.5-8167.8" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:8157.9-8157.41" + attribute \src "ls180.v:4737.5-4747.8" + switch \sdram_choose_req_request [3] + attribute \src "ls180.v:4737.9-4737.36" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:8159.9-8159.13" + assign $0\sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:4739.9-4739.13" case - attribute \src "ls180.v:8160.6-8166.9" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:8160.10-8160.42" + attribute \src "ls180.v:4740.6-4746.9" + switch \sdram_choose_req_request [0] + attribute \src "ls180.v:4740.10-4740.37" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:8162.10-8162.14" + assign $0\sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:4742.10-4742.14" case - attribute \src "ls180.v:8163.7-8165.10" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:8163.11-8163.43" + attribute \src "ls180.v:4743.7-4745.10" + switch \sdram_choose_req_request [1] + attribute \src "ls180.v:4743.11-4743.38" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 + assign $0\sdram_choose_req_grant[1:0] 2'01 case end end end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:8170.5-8180.8" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:8170.9-8170.41" + attribute \src "ls180.v:4750.5-4760.8" + switch \sdram_choose_req_request [0] + attribute \src "ls180.v:4750.9-4750.36" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:8172.9-8172.13" + assign $0\sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:4752.9-4752.13" case - attribute \src "ls180.v:8173.6-8179.9" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:8173.10-8173.42" + attribute \src "ls180.v:4753.6-4759.9" + switch \sdram_choose_req_request [1] + attribute \src "ls180.v:4753.10-4753.37" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:8175.10-8175.14" + assign $0\sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:4755.10-4755.14" case - attribute \src "ls180.v:8176.7-8178.10" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:8176.11-8176.43" + attribute \src "ls180.v:4756.7-4758.10" + switch \sdram_choose_req_request [2] + attribute \src "ls180.v:4756.11-4756.38" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 + assign $0\sdram_choose_req_grant[1:0] 2'10 case end end @@ -299111,6403 +267219,4492 @@ module \ls180 end case end - attribute \src "ls180.v:8192.2-8206.5" - switch \main_sdram_tccdcon_valid - attribute \src "ls180.v:8192.6-8192.30" + attribute \src "ls180.v:4772.2-4786.5" + switch \sdram_tccdcon_valid + attribute \src "ls180.v:4772.6-4772.25" case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] 1'0 - attribute \src "ls180.v:8194.3-8198.6" + assign $0\sdram_tccdcon_count[0:0] 1'0 + attribute \src "ls180.v:4774.3-4778.6" switch 1'1 - attribute \src "ls180.v:8194.7-8194.11" + attribute \src "ls180.v:4774.7-4774.11" case 1'1 - assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + assign $0\sdram_tccdcon_ready[0:0] 1'1 case end - attribute \src "ls180.v:8199.6-8199.10" + attribute \src "ls180.v:4779.6-4779.10" case - attribute \src "ls180.v:8200.3-8205.6" - switch $not$ls180.v:8200$2711_Y - attribute \src "ls180.v:8200.7-8200.34" + attribute \src "ls180.v:4780.3-4785.6" + switch $not$ls180.v:4780$1354_Y + attribute \src "ls180.v:4780.7-4780.29" case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8201$2712_Y - attribute \src "ls180.v:8202.4-8204.7" - switch $eq$ls180.v:8202$2713_Y - attribute \src "ls180.v:8202.8-8202.42" + assign $0\sdram_tccdcon_count[0:0] $sub$ls180.v:4781$1355_Y + attribute \src "ls180.v:4782.4-4784.7" + switch $eq$ls180.v:4782$1356_Y + attribute \src "ls180.v:4782.8-4782.37" case 1'1 - assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + assign $0\sdram_tccdcon_ready[0:0] 1'1 case end case end end - attribute \src "ls180.v:8207.2-8221.5" - switch \main_sdram_twtrcon_valid - attribute \src "ls180.v:8207.6-8207.30" + attribute \src "ls180.v:4787.2-4801.5" + switch \sdram_twtrcon_valid + attribute \src "ls180.v:4787.6-4787.25" case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] 3'100 - attribute \src "ls180.v:8209.3-8213.6" + assign $0\sdram_twtrcon_count[2:0] 3'100 + attribute \src "ls180.v:4789.3-4793.6" switch 1'0 - attribute \src "ls180.v:8211.7-8211.11" + attribute \src "ls180.v:4791.7-4791.11" case - assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + assign $0\sdram_twtrcon_ready[0:0] 1'0 end - attribute \src "ls180.v:8214.6-8214.10" + attribute \src "ls180.v:4794.6-4794.10" case - attribute \src "ls180.v:8215.3-8220.6" - switch $not$ls180.v:8215$2714_Y - attribute \src "ls180.v:8215.7-8215.34" + attribute \src "ls180.v:4795.3-4800.6" + switch $not$ls180.v:4795$1357_Y + attribute \src "ls180.v:4795.7-4795.29" case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8216$2715_Y - attribute \src "ls180.v:8217.4-8219.7" - switch $eq$ls180.v:8217$2716_Y - attribute \src "ls180.v:8217.8-8217.42" + assign $0\sdram_twtrcon_count[2:0] $sub$ls180.v:4796$1358_Y + attribute \src "ls180.v:4797.4-4799.7" + switch $eq$ls180.v:4797$1359_Y + attribute \src "ls180.v:4797.8-4797.37" case 1'1 - assign $0\main_sdram_twtrcon_ready[0:0] 1'1 + assign $0\sdram_twtrcon_ready[0:0] 1'1 case end case end end - attribute \src "ls180.v:8228.2-8230.5" - switch $or$ls180.v:8228$2741_Y - attribute \src "ls180.v:8228.6-8228.50" + attribute \src "ls180.v:4808.2-4810.5" + switch $or$ls180.v:4808$1384_Y + attribute \src "ls180.v:4808.6-4808.40" case 1'1 - assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r + assign $0\converter_dat_r[31:0] \wb_sdram_dat_r case end - attribute \src "ls180.v:8232.2-8234.5" - switch \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:8232.6-8232.52" + attribute \src "ls180.v:4812.2-4814.5" + switch \converter_counter_subfragments_next_value_ce + attribute \src "ls180.v:4812.6-4812.50" case 1'1 - assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value + assign $0\converter_counter[0:0] \converter_counter_subfragments_next_value case end - attribute \src "ls180.v:8235.2-8238.5" - switch \main_converter_reset - attribute \src "ls180.v:8235.6-8235.26" + attribute \src "ls180.v:4815.2-4818.5" + switch \converter_reset + attribute \src "ls180.v:4815.6-4815.21" case 1'1 - assign $0\main_converter_counter[0:0] 1'0 - assign $0\builder_converter_state[0:0] 1'0 + assign $0\converter_counter[0:0] 1'0 + assign $0\subfragments_state[0:0] 1'0 case end - attribute \src "ls180.v:8239.2-8249.5" - switch \main_litedram_wb_ack - attribute \src "ls180.v:8239.6-8239.26" + attribute \src "ls180.v:4819.2-4829.5" + switch \litedram_wb_ack + attribute \src "ls180.v:4819.6-4819.21" case 1'1 - assign $0\main_cmd_consumed[0:0] 1'0 - assign $0\main_wdata_consumed[0:0] 1'0 - attribute \src "ls180.v:8242.6-8242.10" + assign $0\cmd_consumed[0:0] 1'0 + assign $0\wdata_consumed[0:0] 1'0 + attribute \src "ls180.v:4822.6-4822.10" case - attribute \src "ls180.v:8243.3-8245.6" - switch $and$ls180.v:8243$2742_Y - attribute \src "ls180.v:8243.7-8243.50" + attribute \src "ls180.v:4823.3-4825.6" + switch $and$ls180.v:4823$1385_Y + attribute \src "ls180.v:4823.7-4823.40" case 1'1 - assign $0\main_cmd_consumed[0:0] 1'1 + assign $0\cmd_consumed[0:0] 1'1 case end - attribute \src "ls180.v:8246.3-8248.6" - switch $and$ls180.v:8246$2743_Y - attribute \src "ls180.v:8246.7-8246.54" + attribute \src "ls180.v:4826.3-4828.6" + switch $and$ls180.v:4826$1386_Y + attribute \src "ls180.v:4826.7-4826.44" case 1'1 - assign $0\main_wdata_consumed[0:0] 1'1 + assign $0\wdata_consumed[0:0] 1'1 case end end - attribute \src "ls180.v:8251.2-8272.5" - switch $and$ls180.v:8251$2747_Y - attribute \src "ls180.v:8251.6-8251.91" + attribute \src "ls180.v:4831.2-4852.5" + switch $and$ls180.v:4831$1390_Y + attribute \src "ls180.v:4831.6-4831.76" case 1'1 - assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data - assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 - assign $0\main_uart_phy_tx_busy[0:0] 1'1 - assign $0\uart_tx[0:0] 1'0 - attribute \src "ls180.v:8256.6-8256.10" + assign $0\uart_phy_tx_reg[7:0] \uart_phy_sink_payload_data + assign $0\uart_phy_tx_bitcount[3:0] 4'0000 + assign $0\uart_phy_tx_busy[0:0] 1'1 + assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'0 + attribute \src "ls180.v:4836.6-4836.10" case - attribute \src "ls180.v:8257.3-8271.6" - switch $and$ls180.v:8257$2748_Y - attribute \src "ls180.v:8257.7-8257.60" + attribute \src "ls180.v:4837.3-4851.6" + switch $and$ls180.v:4837$1391_Y + attribute \src "ls180.v:4837.7-4837.50" case 1'1 - assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8258$2749_Y - attribute \src "ls180.v:8259.4-8270.7" - switch $eq$ls180.v:8259$2750_Y - attribute \src "ls180.v:8259.8-8259.43" + assign $0\uart_phy_tx_bitcount[3:0] $add$ls180.v:4838$1392_Y + attribute \src "ls180.v:4839.4-4850.7" + switch $eq$ls180.v:4839$1393_Y + attribute \src "ls180.v:4839.8-4839.38" case 1'1 - assign $0\uart_tx[0:0] 1'1 - attribute \src "ls180.v:8261.8-8261.12" + assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1 + attribute \src "ls180.v:4841.8-4841.12" case - attribute \src "ls180.v:8262.5-8269.8" - switch $eq$ls180.v:8262$2751_Y - attribute \src "ls180.v:8262.9-8262.44" + attribute \src "ls180.v:4842.5-4849.8" + switch $eq$ls180.v:4842$1394_Y + attribute \src "ls180.v:4842.9-4842.39" case 1'1 - assign $0\uart_tx[0:0] 1'1 - assign $0\main_uart_phy_tx_busy[0:0] 1'0 - assign $0\main_uart_phy_sink_ready[0:0] 1'1 - attribute \src "ls180.v:8266.9-8266.13" + assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1 + assign $0\uart_phy_tx_busy[0:0] 1'0 + assign $0\uart_phy_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4846.9-4846.13" case - assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] - assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } + assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] \uart_phy_tx_reg [0] + assign $0\uart_phy_tx_reg[7:0] { 1'0 \uart_phy_tx_reg [7:1] } end end case end end - attribute \src "ls180.v:8273.2-8277.5" - switch \main_uart_phy_tx_busy - attribute \src "ls180.v:8273.6-8273.27" + attribute \src "ls180.v:4853.2-4857.5" + switch \uart_phy_tx_busy + attribute \src "ls180.v:4853.6-4853.22" case 1'1 - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8274$2752_Y - attribute \src "ls180.v:8275.6-8275.10" + assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:4854$1395_Y + attribute \src "ls180.v:4855.6-4855.10" case - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } + assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } { 1'0 \uart_phy_storage } end - attribute \src "ls180.v:8280.2-8304.5" - switch $not$ls180.v:8280$2753_Y - attribute \src "ls180.v:8280.6-8280.30" + attribute \src "ls180.v:4860.2-4884.5" + switch $not$ls180.v:4860$1396_Y + attribute \src "ls180.v:4860.6-4860.25" case 1'1 - attribute \src "ls180.v:8281.3-8284.6" - switch $and$ls180.v:8281$2755_Y - attribute \src "ls180.v:8281.7-8281.49" + attribute \src "ls180.v:4861.3-4864.6" + switch $and$ls180.v:4861$1398_Y + attribute \src "ls180.v:4861.7-4861.39" case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 + assign $0\uart_phy_rx_busy[0:0] 1'1 + assign $0\uart_phy_rx_bitcount[3:0] 4'0000 case end - attribute \src "ls180.v:8285.6-8285.10" + attribute \src "ls180.v:4865.6-4865.10" case - attribute \src "ls180.v:8286.3-8303.6" - switch \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:8286.7-8286.34" + attribute \src "ls180.v:4866.3-4883.6" + switch \uart_phy_uart_clk_rxen + attribute \src "ls180.v:4866.7-4866.29" case 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8287$2756_Y - attribute \src "ls180.v:8288.4-8302.7" - switch $eq$ls180.v:8288$2757_Y - attribute \src "ls180.v:8288.8-8288.43" + assign $0\uart_phy_rx_bitcount[3:0] $add$ls180.v:4867$1399_Y + attribute \src "ls180.v:4868.4-4882.7" + switch $eq$ls180.v:4868$1400_Y + attribute \src "ls180.v:4868.8-4868.38" case 1'1 - attribute \src "ls180.v:8289.5-8291.8" - switch \main_uart_phy_rx - attribute \src "ls180.v:8289.9-8289.25" + attribute \src "ls180.v:4869.5-4871.8" + switch \uart_phy_rx + attribute \src "ls180.v:4869.9-4869.20" case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 + assign $0\uart_phy_rx_busy[0:0] 1'0 case end - attribute \src "ls180.v:8292.8-8292.12" + attribute \src "ls180.v:4872.8-4872.12" case - attribute \src "ls180.v:8293.5-8301.8" - switch $eq$ls180.v:8293$2758_Y - attribute \src "ls180.v:8293.9-8293.44" + attribute \src "ls180.v:4873.5-4881.8" + switch $eq$ls180.v:4873$1401_Y + attribute \src "ls180.v:4873.9-4873.39" case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 - attribute \src "ls180.v:8295.6-8298.9" - switch \main_uart_phy_rx - attribute \src "ls180.v:8295.10-8295.26" + assign $0\uart_phy_rx_busy[0:0] 1'0 + attribute \src "ls180.v:4875.6-4878.9" + switch \uart_phy_rx + attribute \src "ls180.v:4875.10-4875.21" case 1'1 - assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg - assign $0\main_uart_phy_source_valid[0:0] 1'1 + assign $0\uart_phy_source_payload_data[7:0] \uart_phy_rx_reg + assign $0\uart_phy_source_valid[0:0] 1'1 case end - attribute \src "ls180.v:8299.9-8299.13" + attribute \src "ls180.v:4879.9-4879.13" case - assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } + assign $0\uart_phy_rx_reg[7:0] { \uart_phy_rx \uart_phy_rx_reg [7:1] } end end case end end - attribute \src "ls180.v:8305.2-8309.5" - switch \main_uart_phy_rx_busy - attribute \src "ls180.v:8305.6-8305.27" - case 1'1 - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8306$2759_Y - attribute \src "ls180.v:8307.6-8307.10" - case - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 - end - attribute \src "ls180.v:8310.2-8312.5" - switch \main_uart_tx_clear - attribute \src "ls180.v:8310.6-8310.24" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:8314.2-8316.5" - switch $and$ls180.v:8314$2761_Y - attribute \src "ls180.v:8314.6-8314.58" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:8317.2-8319.5" - switch \main_uart_rx_clear - attribute \src "ls180.v:8317.6-8317.24" - case 1'1 - assign $0\main_uart_rx_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:8321.2-8323.5" - switch $and$ls180.v:8321$2763_Y - attribute \src "ls180.v:8321.6-8321.58" - case 1'1 - assign $0\main_uart_rx_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:8324.2-8330.5" - switch \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:8324.6-8324.35" - case 1'1 - assign $0\main_uart_tx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8326.6-8326.10" - case - attribute \src "ls180.v:8327.3-8329.6" - switch \main_uart_tx_fifo_re - attribute \src "ls180.v:8327.7-8327.27" - case 1'1 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8331.2-8333.5" - switch $and$ls180.v:8331$2766_Y - attribute \src "ls180.v:8331.6-8331.108" - case 1'1 - assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8332$2767_Y - case - end - attribute \src "ls180.v:8334.2-8336.5" - switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8334.6-8334.31" - case 1'1 - assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8335$2768_Y - case - end - attribute \src "ls180.v:8337.2-8345.5" - switch $and$ls180.v:8337$2771_Y - attribute \src "ls180.v:8337.6-8337.108" - case 1'1 - attribute \src "ls180.v:8338.3-8340.6" - switch $not$ls180.v:8338$2772_Y - attribute \src "ls180.v:8338.7-8338.35" - case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8339$2773_Y - case - end - attribute \src "ls180.v:8341.6-8341.10" - case - attribute \src "ls180.v:8342.3-8344.6" - switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8342.7-8342.32" - case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8343$2774_Y - case - end - end - attribute \src "ls180.v:8346.2-8352.5" - switch \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:8346.6-8346.35" - case 1'1 - assign $0\main_uart_rx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8348.6-8348.10" - case - attribute \src "ls180.v:8349.3-8351.6" - switch \main_uart_rx_fifo_re - attribute \src "ls180.v:8349.7-8349.27" - case 1'1 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8353.2-8355.5" - switch $and$ls180.v:8353$2777_Y - attribute \src "ls180.v:8353.6-8353.108" - case 1'1 - assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8354$2778_Y - case - end - attribute \src "ls180.v:8356.2-8358.5" - switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8356.6-8356.31" - case 1'1 - assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8357$2779_Y - case - end - attribute \src "ls180.v:8359.2-8367.5" - switch $and$ls180.v:8359$2782_Y - attribute \src "ls180.v:8359.6-8359.108" - case 1'1 - attribute \src "ls180.v:8360.3-8362.6" - switch $not$ls180.v:8360$2783_Y - attribute \src "ls180.v:8360.7-8360.35" - case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8361$2784_Y - case - end - attribute \src "ls180.v:8363.6-8363.10" - case - attribute \src "ls180.v:8364.3-8366.6" - switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8364.7-8364.32" - case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8365$2785_Y - case - end - end - attribute \src "ls180.v:8368.2-8381.5" - switch \main_uart_reset - attribute \src "ls180.v:8368.6-8368.21" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'0 - assign $0\main_uart_tx_old_trigger[0:0] 1'0 - assign $0\main_uart_rx_pending[0:0] 1'0 - assign $0\main_uart_rx_old_trigger[0:0] 1'0 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 - case - end - attribute \src "ls180.v:8383.2-8390.5" - switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8383.6-8383.31" - case 1'1 - assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable - attribute \src "ls180.v:8385.6-8385.10" - case - attribute \src "ls180.v:8386.3-8389.6" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8386.7-8386.32" - case 1'1 - assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 - assign $0\spisdcard_clk[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8392.2-8402.5" - switch \main_spimaster28_mosi_latch - attribute \src "ls180.v:8392.6-8392.33" - case 1'1 - assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi - assign $0\main_spimaster34_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8395.6-8395.10" - case - attribute \src "ls180.v:8396.3-8401.6" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8396.7-8396.32" - case 1'1 - assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8400$2790_Y - attribute \src "ls180.v:8397.4-8399.7" - switch \main_spimaster26_cs_enable - attribute \src "ls180.v:8397.8-8397.34" - case 1'1 - assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 - case - end - case - end - end - attribute \src "ls180.v:8403.2-8409.5" - switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8403.6-8403.31" - case 1'1 - attribute \src "ls180.v:8404.3-8408.6" - switch \main_spimaster7_loopback - attribute \src "ls180.v:8404.7-8404.31" - case 1'1 - assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } - attribute \src "ls180.v:8406.7-8406.11" - case - assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } - end - case - end - attribute \src "ls180.v:8410.2-8412.5" - switch \main_spimaster29_miso_latch - attribute \src "ls180.v:8410.6-8410.33" - case 1'1 - assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data - case - end - attribute \src "ls180.v:8414.2-8416.5" - switch \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:8414.6-8414.53" - case 1'1 - assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value - case - end - attribute \src "ls180.v:8418.2-8425.5" - switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8418.6-8418.29" - case 1'1 - assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable - attribute \src "ls180.v:8420.6-8420.10" - case - attribute \src "ls180.v:8421.3-8424.6" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8421.7-8421.30" - case 1'1 - assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 - assign $0\spimaster_clk[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8427.2-8437.5" - switch \main_spisdcard_mosi_latch - attribute \src "ls180.v:8427.6-8427.31" - case 1'1 - assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi - assign $0\main_spisdcard_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8430.6-8430.10" - case - attribute \src "ls180.v:8431.3-8436.6" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8431.7-8431.30" - case 1'1 - assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8435$2795_Y - attribute \src "ls180.v:8432.4-8434.7" - switch \main_spisdcard_cs_enable - attribute \src "ls180.v:8432.8-8432.32" - case 1'1 - assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 - case - end - case - end - end - attribute \src "ls180.v:8438.2-8444.5" - switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8438.6-8438.29" - case 1'1 - attribute \src "ls180.v:8439.3-8443.6" - switch \main_spisdcard_loopback - attribute \src "ls180.v:8439.7-8439.30" - case 1'1 - assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } - attribute \src "ls180.v:8441.7-8441.11" - case - assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } - end - case - end - attribute \src "ls180.v:8445.2-8447.5" - switch \main_spisdcard_miso_latch - attribute \src "ls180.v:8445.6-8445.31" - case 1'1 - assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data - case - end - attribute \src "ls180.v:8449.2-8451.5" - switch \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:8449.6-8449.51" - case 1'1 - assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value - case - end - attribute \src "ls180.v:8452.2-8465.5" - switch \main_pwm0_enable - attribute \src "ls180.v:8452.6-8452.22" - case 1'1 - assign $0\main_pwm0_counter[31:0] $add$ls180.v:8453$2796_Y - attribute \src "ls180.v:8454.3-8458.6" - switch $lt$ls180.v:8454$2797_Y - attribute \src "ls180.v:8454.7-8454.44" - case 1'1 - assign $0\pwm[1:0] [0] 1'1 - attribute \src "ls180.v:8456.7-8456.11" - case - assign $0\pwm[1:0] [0] 1'0 - end - attribute \src "ls180.v:8459.3-8461.6" - switch $ge$ls180.v:8459$2799_Y - attribute \src "ls180.v:8459.7-8459.55" - case 1'1 - assign $0\main_pwm0_counter[31:0] 0 - case - end - attribute \src "ls180.v:8462.6-8462.10" - case - assign $0\main_pwm0_counter[31:0] 0 - assign $0\pwm[1:0] [0] 1'0 - end - attribute \src "ls180.v:8466.2-8479.5" - switch \main_pwm1_enable - attribute \src "ls180.v:8466.6-8466.22" - case 1'1 - assign $0\main_pwm1_counter[31:0] $add$ls180.v:8467$2800_Y - attribute \src "ls180.v:8468.3-8472.6" - switch $lt$ls180.v:8468$2801_Y - attribute \src "ls180.v:8468.7-8468.44" - case 1'1 - assign $0\pwm[1:0] [1] 1'1 - attribute \src "ls180.v:8470.7-8470.11" - case - assign $0\pwm[1:0] [1] 1'0 - end - attribute \src "ls180.v:8473.3-8475.6" - switch $ge$ls180.v:8473$2803_Y - attribute \src "ls180.v:8473.7-8473.55" - case 1'1 - assign $0\main_pwm1_counter[31:0] 0 - case - end - attribute \src "ls180.v:8476.6-8476.10" - case - assign $0\main_pwm1_counter[31:0] 0 - assign $0\pwm[1:0] [1] 1'0 - end - attribute \src "ls180.v:8480.2-8482.5" - switch $not$ls180.v:8480$2804_Y - attribute \src "ls180.v:8480.6-8480.32" - case 1'1 - assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8481$2805_Y - case - end - attribute \src "ls180.v:8486.2-8488.5" - switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:8486.6-8486.57" - case 1'1 - assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value - case - end - attribute \src "ls180.v:8490.2-8492.5" - switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:8490.6-8490.57" - case 1'1 - assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - case - end - attribute \src "ls180.v:8493.2-8495.5" - switch \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:8493.6-8493.40" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8494$2806_Y - case - end - attribute \src "ls180.v:8496.2-8498.5" - switch \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:8496.6-8496.49" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8499.2-8506.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8499.6-8499.46" - case 1'1 - attribute \src "ls180.v:8500.3-8505.6" - switch $or$ls180.v:8500$2808_Y - attribute \src "ls180.v:8500.7-8500.98" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8503.7-8503.11" - case - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8504$2809_Y - end - case - end - attribute \src "ls180.v:8507.2-8520.5" - switch $and$ls180.v:8507$2810_Y - attribute \src "ls180.v:8507.6-8507.97" - case 1'1 - attribute \src "ls180.v:8508.3-8514.6" - switch $and$ls180.v:8508$2811_Y - attribute \src "ls180.v:8508.7-8508.94" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:8511.7-8511.11" - case - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8515.6-8515.10" - case - attribute \src "ls180.v:8516.3-8519.6" - switch $and$ls180.v:8516$2812_Y - attribute \src "ls180.v:8516.7-8516.94" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8517$2813_Y - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8518$2814_Y - case - end - end - attribute \src "ls180.v:8521.2-8548.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8521.6-8521.46" - case 1'1 - attribute \src "ls180.v:8522.3-8547.10" - switch \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [7] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [6] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [5] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [4] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [3] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [2] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [1] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [0] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8549.2-8551.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8549.6-8549.46" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8550$2815_Y - case - end - attribute \src "ls180.v:8552.2-8557.5" - switch $or$ls180.v:8552$2817_Y - attribute \src "ls180.v:8552.6-8552.88" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid - assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first - assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_sink_last - assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data - case - end - attribute \src "ls180.v:8558.2-8563.5" - switch \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:8558.6-8558.32" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8565.2-8567.5" - switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:8565.6-8565.58" - case 1'1 - assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - case - end - attribute \src "ls180.v:8568.2-8570.5" - switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:8568.6-8568.60" - case 1'1 - assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - case - end - attribute \src "ls180.v:8571.2-8573.5" - switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:8571.6-8571.63" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - case - end - attribute \src "ls180.v:8574.2-8576.5" - switch \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:8574.6-8574.41" - case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8575$2818_Y - case - end - attribute \src "ls180.v:8577.2-8579.5" - switch \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:8577.6-8577.50" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8580.2-8587.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8580.6-8580.47" - case 1'1 - attribute \src "ls180.v:8581.3-8586.6" - switch $or$ls180.v:8581$2820_Y - attribute \src "ls180.v:8581.7-8581.100" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8584.7-8584.11" - case - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8585$2821_Y - end - case - end - attribute \src "ls180.v:8588.2-8601.5" - switch $and$ls180.v:8588$2822_Y - attribute \src "ls180.v:8588.6-8588.99" - case 1'1 - attribute \src "ls180.v:8589.3-8595.6" - switch $and$ls180.v:8589$2823_Y - attribute \src "ls180.v:8589.7-8589.96" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:8592.7-8592.11" - case - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8596.6-8596.10" - case - attribute \src "ls180.v:8597.3-8600.6" - switch $and$ls180.v:8597$2824_Y - attribute \src "ls180.v:8597.7-8597.96" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8598$2825_Y - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8599$2826_Y - case - end - end - attribute \src "ls180.v:8602.2-8629.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8602.6-8602.47" - case 1'1 - attribute \src "ls180.v:8603.3-8628.10" - switch \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [7] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [6] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [5] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [4] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [3] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [2] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [1] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [0] \main_sdphy_dataw_crcr_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8630.2-8632.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8630.6-8630.47" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8631$2827_Y - case - end - attribute \src "ls180.v:8633.2-8638.5" - switch $or$ls180.v:8633$2829_Y - attribute \src "ls180.v:8633.6-8633.90" - case 1'1 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid - assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first - assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_sink_last - assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data - case - end - attribute \src "ls180.v:8639.2-8644.5" - switch \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:8639.6-8639.33" - case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8646.2-8648.5" - switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:8646.6-8646.63" - case 1'1 - assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - case - end - attribute \src "ls180.v:8650.2-8652.5" - switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:8650.6-8650.52" - case 1'1 - assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value - case - end - attribute \src "ls180.v:8653.2-8655.5" - switch \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:8653.6-8653.42" - case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8654$2830_Y - case - end - attribute \src "ls180.v:8656.2-8658.5" - switch \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:8656.6-8656.51" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8659.2-8666.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8659.6-8659.48" - case 1'1 - attribute \src "ls180.v:8660.3-8665.6" - switch $or$ls180.v:8660$2832_Y - attribute \src "ls180.v:8660.7-8660.102" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8663.7-8663.11" - case - assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8664$2833_Y - end - case - end - attribute \src "ls180.v:8667.2-8680.5" - switch $and$ls180.v:8667$2834_Y - attribute \src "ls180.v:8667.6-8667.101" - case 1'1 - attribute \src "ls180.v:8668.3-8674.6" - switch $and$ls180.v:8668$2835_Y - attribute \src "ls180.v:8668.7-8668.98" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:8671.7-8671.11" - case - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8675.6-8675.10" - case - attribute \src "ls180.v:8676.3-8679.6" - switch $and$ls180.v:8676$2836_Y - attribute \src "ls180.v:8676.7-8676.98" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8677$2837_Y - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8678$2838_Y - case - end - end - attribute \src "ls180.v:8681.2-8690.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8681.6-8681.48" - case 1'1 - attribute \src "ls180.v:8682.3-8689.10" - switch \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [7:4] \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [3:0] \main_sdphy_datar_datar_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8691.2-8693.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8691.6-8691.48" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8692$2839_Y - case - end - attribute \src "ls180.v:8694.2-8699.5" - switch $or$ls180.v:8694$2841_Y - attribute \src "ls180.v:8694.6-8694.92" - case 1'1 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid - assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first - assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_sink_last - assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data - case - end - attribute \src "ls180.v:8700.2-8705.5" - switch \main_sdphy_datar_datar_reset - attribute \src "ls180.v:8700.6-8700.34" - case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8707.2-8709.5" - switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:8707.6-8707.60" - case 1'1 - assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - case - end - attribute \src "ls180.v:8710.2-8712.5" - switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:8710.6-8710.62" - case 1'1 - assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - case - end - attribute \src "ls180.v:8713.2-8715.5" - switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:8713.6-8713.66" - case 1'1 - assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - case - end - attribute \src "ls180.v:8716.2-8722.5" - switch \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:8716.6-8716.35" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - attribute \src "ls180.v:8718.6-8718.10" - case - attribute \src "ls180.v:8719.3-8721.6" - switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:8719.7-8719.39" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 - case - end - end - attribute \src "ls180.v:8723.2-8729.5" - switch \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:8723.6-8723.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8725.6-8725.10" - case - attribute \src "ls180.v:8726.3-8728.6" - switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:8726.7-8726.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - case - end - end - attribute \src "ls180.v:8730.2-8736.5" - switch \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:8730.6-8730.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8732.6-8732.10" - case - attribute \src "ls180.v:8733.3-8735.6" - switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:8733.7-8733.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - case - end - end - attribute \src "ls180.v:8737.2-8743.5" - switch \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:8737.6-8737.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8739.6-8739.10" - case - attribute \src "ls180.v:8740.3-8742.6" - switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:8740.7-8740.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - case - end - end - attribute \src "ls180.v:8744.2-8750.5" - switch \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:8744.6-8744.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8746.6-8746.10" - case - attribute \src "ls180.v:8747.3-8749.6" - switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:8747.7-8747.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - case - end - end - attribute \src "ls180.v:8752.2-8754.5" - switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:8752.6-8752.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - case - end - attribute \src "ls180.v:8755.2-8757.5" - switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:8755.6-8755.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - case - end - attribute \src "ls180.v:8758.2-8760.5" - switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:8758.6-8758.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - case - end - attribute \src "ls180.v:8761.2-8763.5" - switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:8761.6-8761.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - case - end - attribute \src "ls180.v:8764.2-8766.5" - switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:8764.6-8764.78" + attribute \src "ls180.v:4885.2-4889.5" + switch \uart_phy_rx_busy + attribute \src "ls180.v:4885.6-4885.22" case 1'1 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:4886$1402_Y + attribute \src "ls180.v:4887.6-4887.10" case + assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 end - attribute \src "ls180.v:8767.2-8769.5" - switch $and$ls180.v:8767$2842_Y - attribute \src "ls180.v:8767.6-8767.83" + attribute \src "ls180.v:4890.2-4892.5" + switch \tx_clear + attribute \src "ls180.v:4890.6-4890.14" case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc + assign $0\tx_pending[0:0] 1'0 case end - attribute \src "ls180.v:8770.2-8772.5" - switch $and$ls180.v:8770$2843_Y - attribute \src "ls180.v:8770.6-8770.83" + attribute \src "ls180.v:4894.2-4896.5" + switch $and$ls180.v:4894$1404_Y + attribute \src "ls180.v:4894.6-4894.38" case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc + assign $0\tx_pending[0:0] 1'1 case end - attribute \src "ls180.v:8773.2-8775.5" - switch $and$ls180.v:8773$2844_Y - attribute \src "ls180.v:8773.6-8773.83" + attribute \src "ls180.v:4897.2-4899.5" + switch \rx_clear + attribute \src "ls180.v:4897.6-4897.14" case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc + assign $0\rx_pending[0:0] 1'0 case end - attribute \src "ls180.v:8776.2-8778.5" - switch $and$ls180.v:8776$2845_Y - attribute \src "ls180.v:8776.6-8776.83" + attribute \src "ls180.v:4901.2-4903.5" + switch $and$ls180.v:4901$1406_Y + attribute \src "ls180.v:4901.6-4901.38" case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc + assign $0\rx_pending[0:0] 1'1 case end - attribute \src "ls180.v:8779.2-8783.5" - switch $and$ls180.v:8779$2846_Y - attribute \src "ls180.v:8779.6-8779.83" + attribute \src "ls180.v:4904.2-4910.5" + switch \tx_fifo_syncfifo_re + attribute \src "ls180.v:4904.6-4904.25" case 1'1 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } - assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] + assign $0\tx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:4906.6-4906.10" case - end - attribute \src "ls180.v:8784.2-8788.5" - switch $and$ls180.v:8784$2847_Y - attribute \src "ls180.v:8784.6-8784.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } - assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] - case - end - attribute \src "ls180.v:8789.2-8793.5" - switch $and$ls180.v:8789$2848_Y - attribute \src "ls180.v:8789.6-8789.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } - assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] - case - end - attribute \src "ls180.v:8794.2-8798.5" - switch $and$ls180.v:8794$2849_Y - attribute \src "ls180.v:8794.6-8794.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } - assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] - case - end - attribute \src "ls180.v:8799.2-8807.5" - switch $and$ls180.v:8799$2850_Y - attribute \src "ls180.v:8799.6-8799.83" - case 1'1 - attribute \src "ls180.v:8800.3-8806.6" - switch \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:8800.7-8800.42" + attribute \src "ls180.v:4907.3-4909.6" + switch \tx_fifo_re + attribute \src "ls180.v:4907.7-4907.17" case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - attribute \src "ls180.v:8802.7-8802.11" + assign $0\tx_fifo_readable[0:0] 1'0 case - attribute \src "ls180.v:8803.4-8805.7" - switch $ne$ls180.v:8803$2851_Y - attribute \src "ls180.v:8803.8-8803.48" - case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8804$2852_Y - case - end end - case end - attribute \src "ls180.v:8808.2-8814.5" - switch \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:8808.6-8808.40" + attribute \src "ls180.v:4911.2-4913.5" + switch $and$ls180.v:4911$1409_Y + attribute \src "ls180.v:4911.6-4911.78" case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8810.6-8810.10" + assign $0\tx_fifo_produce[3:0] $add$ls180.v:4912$1410_Y case - attribute \src "ls180.v:8811.3-8813.6" - switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:8811.7-8811.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - case - end end - attribute \src "ls180.v:8815.2-8821.5" - switch \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:8815.6-8815.40" + attribute \src "ls180.v:4914.2-4916.5" + switch \tx_fifo_do_read + attribute \src "ls180.v:4914.6-4914.21" case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8817.6-8817.10" + assign $0\tx_fifo_consume[3:0] $add$ls180.v:4915$1411_Y case - attribute \src "ls180.v:8818.3-8820.6" - switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:8818.7-8818.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - case - end end - attribute \src "ls180.v:8822.2-8828.5" - switch \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:8822.6-8822.40" + attribute \src "ls180.v:4917.2-4925.5" + switch $and$ls180.v:4917$1414_Y + attribute \src "ls180.v:4917.6-4917.78" case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8824.6-8824.10" - case - attribute \src "ls180.v:8825.3-8827.6" - switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:8825.7-8825.44" + attribute \src "ls180.v:4918.3-4920.6" + switch $not$ls180.v:4918$1415_Y + attribute \src "ls180.v:4918.7-4918.25" case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + assign $0\tx_fifo_level0[4:0] $add$ls180.v:4919$1416_Y case end - end - attribute \src "ls180.v:8829.2-8835.5" - switch \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:8829.6-8829.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8831.6-8831.10" + attribute \src "ls180.v:4921.6-4921.10" case - attribute \src "ls180.v:8832.3-8834.6" - switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:8832.7-8832.44" + attribute \src "ls180.v:4922.3-4924.6" + switch \tx_fifo_do_read + attribute \src "ls180.v:4922.7-4922.22" case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + assign $0\tx_fifo_level0[4:0] $sub$ls180.v:4923$1417_Y case end end - attribute \src "ls180.v:8837.2-8839.5" - switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:8837.6-8837.52" - case 1'1 - assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 - case - end - attribute \src "ls180.v:8840.2-8842.5" - switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:8840.6-8840.53" - case 1'1 - assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 - case - end - attribute \src "ls180.v:8843.2-8845.5" - switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:8843.6-8843.53" - case 1'1 - assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 - case - end - attribute \src "ls180.v:8846.2-8848.5" - switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:8846.6-8846.54" - case 1'1 - assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 - case - end - attribute \src "ls180.v:8849.2-8851.5" - switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:8849.6-8849.53" - case 1'1 - assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 - case - end - attribute \src "ls180.v:8852.2-8854.5" - switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:8852.6-8852.55" - case 1'1 - assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - case - end - attribute \src "ls180.v:8855.2-8857.5" - switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:8855.6-8855.54" - case 1'1 - assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 - case - end - attribute \src "ls180.v:8858.2-8860.5" - switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:8858.6-8858.56" - case 1'1 - assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 - case - end - attribute \src "ls180.v:8861.2-8863.5" - switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:8861.6-8861.63" + attribute \src "ls180.v:4926.2-4932.5" + switch \rx_fifo_syncfifo_re + attribute \src "ls180.v:4926.6-4926.25" case 1'1 - assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + assign $0\rx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:4928.6-4928.10" case - end - attribute \src "ls180.v:8864.2-8866.5" - switch $and$ls180.v:8864$2855_Y - attribute \src "ls180.v:8864.6-8864.120" - case 1'1 - assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8865$2856_Y - case - end - attribute \src "ls180.v:8867.2-8869.5" - switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8867.6-8867.35" - case 1'1 - assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8868$2857_Y - case - end - attribute \src "ls180.v:8870.2-8878.5" - switch $and$ls180.v:8870$2860_Y - attribute \src "ls180.v:8870.6-8870.120" - case 1'1 - attribute \src "ls180.v:8871.3-8873.6" - switch $not$ls180.v:8871$2861_Y - attribute \src "ls180.v:8871.7-8871.39" + attribute \src "ls180.v:4929.3-4931.6" + switch \rx_fifo_re + attribute \src "ls180.v:4929.7-4929.17" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8872$2862_Y - case - end - attribute \src "ls180.v:8874.6-8874.10" - case - attribute \src "ls180.v:8875.3-8877.6" - switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8875.7-8875.36" - case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8876$2863_Y + assign $0\rx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:8879.2-8881.5" - switch \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:8879.6-8879.45" + attribute \src "ls180.v:4933.2-4935.5" + switch $and$ls180.v:4933$1420_Y + attribute \src "ls180.v:4933.6-4933.78" case 1'1 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + assign $0\rx_fifo_produce[3:0] $add$ls180.v:4934$1421_Y case end - attribute \src "ls180.v:8882.2-8889.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8882.6-8882.42" + attribute \src "ls180.v:4936.2-4938.5" + switch \rx_fifo_do_read + attribute \src "ls180.v:4936.6-4936.21" case 1'1 - attribute \src "ls180.v:8883.3-8888.6" - switch $or$ls180.v:8883$2865_Y - attribute \src "ls180.v:8883.7-8883.90" - case 1'1 - assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8886.7-8886.11" - case - assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8887$2866_Y - end + assign $0\rx_fifo_consume[3:0] $add$ls180.v:4937$1422_Y case end - attribute \src "ls180.v:8890.2-8903.5" - switch $and$ls180.v:8890$2867_Y - attribute \src "ls180.v:8890.6-8890.89" + attribute \src "ls180.v:4939.2-4947.5" + switch $and$ls180.v:4939$1425_Y + attribute \src "ls180.v:4939.6-4939.78" case 1'1 - attribute \src "ls180.v:8891.3-8897.6" - switch $and$ls180.v:8891$2868_Y - attribute \src "ls180.v:8891.7-8891.86" - case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first - assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:8894.7-8894.11" - case - assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 - assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8898.6-8898.10" - case - attribute \src "ls180.v:8899.3-8902.6" - switch $and$ls180.v:8899$2869_Y - attribute \src "ls180.v:8899.7-8899.86" + attribute \src "ls180.v:4940.3-4942.6" + switch $not$ls180.v:4940$1426_Y + attribute \src "ls180.v:4940.7-4940.25" case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8900$2870_Y - assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8901$2871_Y - case - end - end - attribute \src "ls180.v:8904.2-8931.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8904.6-8904.42" - case 1'1 - attribute \src "ls180.v:8905.3-8930.10" - switch \main_sdblock2mem_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [63:56] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [55:48] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [47:40] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [39:32] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [31:24] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [23:16] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [15:8] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [7:0] \main_sdblock2mem_converter_sink_payload_data + assign $0\rx_fifo_level0[4:0] $add$ls180.v:4941$1427_Y case end + attribute \src "ls180.v:4943.6-4943.10" case - end - attribute \src "ls180.v:8932.2-8934.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8932.6-8932.42" - case 1'1 - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8933$2872_Y - case - end - attribute \src "ls180.v:8936.2-8938.5" - switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:8936.6-8936.76" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - case - end - attribute \src "ls180.v:8939.2-8942.5" - switch \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:8939.6-8939.46" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\builder_sdblock2memdma_state[1:0] 2'00 - case - end - attribute \src "ls180.v:8944.2-8946.5" - switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:8944.6-8944.64" - case 1'1 - assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - case - end - attribute \src "ls180.v:8948.2-8950.5" - switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:8948.6-8948.76" - case 1'1 - assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - case - end - attribute \src "ls180.v:8951.2-8954.5" - switch \main_sdmem2block_dma_reset - attribute \src "ls180.v:8951.6-8951.32" - case 1'1 - assign $0\main_sdmem2block_dma_offset[31:0] 0 - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - case - end - attribute \src "ls180.v:8955.2-8961.5" - switch $and$ls180.v:8955$2873_Y - attribute \src "ls180.v:8955.6-8955.89" - case 1'1 - attribute \src "ls180.v:8956.3-8960.6" - switch \main_sdmem2block_converter_last - attribute \src "ls180.v:8956.7-8956.38" + attribute \src "ls180.v:4944.3-4946.6" + switch \rx_fifo_do_read + attribute \src "ls180.v:4944.7-4944.22" case 1'1 - assign $0\main_sdmem2block_converter_mux[2:0] 3'000 - attribute \src "ls180.v:8958.7-8958.11" + assign $0\rx_fifo_level0[4:0] $sub$ls180.v:4945$1428_Y case - assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8959$2874_Y end - case - end - attribute \src "ls180.v:8962.2-8964.5" - switch $and$ls180.v:8962$2877_Y - attribute \src "ls180.v:8962.6-8962.120" - case 1'1 - assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8963$2878_Y - case - end - attribute \src "ls180.v:8965.2-8967.5" - switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8965.6-8965.35" - case 1'1 - assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8966$2879_Y - case end - attribute \src "ls180.v:8968.2-8976.5" - switch $and$ls180.v:8968$2882_Y - attribute \src "ls180.v:8968.6-8968.120" + attribute \src "ls180.v:4948.2-4961.5" + switch \reset + attribute \src "ls180.v:4948.6-4948.11" case 1'1 - attribute \src "ls180.v:8969.3-8971.6" - switch $not$ls180.v:8969$2883_Y - attribute \src "ls180.v:8969.7-8969.39" - case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8970$2884_Y - case - end - attribute \src "ls180.v:8972.6-8972.10" + assign $0\tx_pending[0:0] 1'0 + assign $0\tx_old_trigger[0:0] 1'0 + assign $0\rx_pending[0:0] 1'0 + assign $0\rx_old_trigger[0:0] 1'0 + assign $0\tx_fifo_readable[0:0] 1'0 + assign $0\tx_fifo_level0[4:0] 5'00000 + assign $0\tx_fifo_produce[3:0] 4'0000 + assign $0\tx_fifo_consume[3:0] 4'0000 + assign $0\rx_fifo_readable[0:0] 1'0 + assign $0\rx_fifo_level0[4:0] 5'00000 + assign $0\rx_fifo_produce[3:0] 4'0000 + assign $0\rx_fifo_consume[3:0] 4'0000 case - attribute \src "ls180.v:8973.3-8975.6" - switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8973.7-8973.36" - case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8974$2885_Y - case - end end - attribute \src "ls180.v:8978.2-8980.5" - switch \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:8978.6-8978.46" + attribute \src "ls180.v:4963.2-4965.5" + switch \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 + attribute \src "ls180.v:4963.6-4963.62" case 1'1 - assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 + assign $0\libresocsim_libresocsim_dat_w[7:0] \libresocsim_libresocsim_dat_w_libresocsim_next_value0 case end - attribute \src "ls180.v:8981.2-8983.5" - switch \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:8981.6-8981.44" + attribute \src "ls180.v:4966.2-4968.5" + switch \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 + attribute \src "ls180.v:4966.6-4966.60" case 1'1 - assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 + assign $0\libresocsim_libresocsim_adr[13:0] \libresocsim_libresocsim_adr_libresocsim_next_value1 case end - attribute \src "ls180.v:8984.2-8986.5" - switch \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:8984.6-8984.43" + attribute \src "ls180.v:4969.2-4971.5" + switch \libresocsim_libresocsim_we_libresocsim_next_value_ce2 + attribute \src "ls180.v:4969.6-4969.59" case 1'1 - assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 + assign $0\libresocsim_libresocsim_we[0:0] \libresocsim_libresocsim_we_libresocsim_next_value2 case end - attribute \src "ls180.v:8987.2-9083.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - attribute \src "ls180.v:8989.4-9005.7" - switch $not$ls180.v:8989$2886_Y - attribute \src "ls180.v:8989.8-8989.29" - case 1'1 - attribute \src "ls180.v:8990.5-9004.8" - switch \builder_request [1] - attribute \src "ls180.v:8990.9-8990.27" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8992.9-8992.13" - case - attribute \src "ls180.v:8993.6-9003.9" - switch \builder_request [2] - attribute \src "ls180.v:8993.10-8993.28" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8995.10-8995.14" - case - attribute \src "ls180.v:8996.7-9002.10" - switch \builder_request [3] - attribute \src "ls180.v:8996.11-8996.29" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8998.11-8998.15" - case - attribute \src "ls180.v:8999.8-9001.11" - switch \builder_request [4] - attribute \src "ls180.v:8999.12-8999.30" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'001 - attribute \src "ls180.v:9008.4-9024.7" - switch $not$ls180.v:9008$2887_Y - attribute \src "ls180.v:9008.8-9008.29" - case 1'1 - attribute \src "ls180.v:9009.5-9023.8" - switch \builder_request [2] - attribute \src "ls180.v:9009.9-9009.27" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:9011.9-9011.13" - case - attribute \src "ls180.v:9012.6-9022.9" - switch \builder_request [3] - attribute \src "ls180.v:9012.10-9012.28" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:9014.10-9014.14" - case - attribute \src "ls180.v:9015.7-9021.10" - switch \builder_request [4] - attribute \src "ls180.v:9015.11-9015.29" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:9017.11-9017.15" - case - attribute \src "ls180.v:9018.8-9020.11" - switch \builder_request [0] - attribute \src "ls180.v:9018.12-9018.30" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - case - end - end - end - end - case - end + attribute \src "ls180.v:4972.2-5006.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" - case 3'010 - attribute \src "ls180.v:9027.4-9043.7" - switch $not$ls180.v:9027$2888_Y - attribute \src "ls180.v:9027.8-9027.29" + case 2'00 + attribute \src "ls180.v:4974.4-4982.7" + switch $not$ls180.v:4974$1429_Y + attribute \src "ls180.v:4974.8-4974.33" case 1'1 - attribute \src "ls180.v:9028.5-9042.8" - switch \builder_request [3] - attribute \src "ls180.v:9028.9-9028.27" + attribute \src "ls180.v:4975.5-4981.8" + switch \libresocsim_request [1] + attribute \src "ls180.v:4975.9-4975.31" case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:9030.9-9030.13" + assign $0\libresocsim_grant[1:0] 2'01 + attribute \src "ls180.v:4977.9-4977.13" case - attribute \src "ls180.v:9031.6-9041.9" - switch \builder_request [4] - attribute \src "ls180.v:9031.10-9031.28" + attribute \src "ls180.v:4978.6-4980.9" + switch \libresocsim_request [2] + attribute \src "ls180.v:4978.10-4978.32" case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:9033.10-9033.14" + assign $0\libresocsim_grant[1:0] 2'10 case - attribute \src "ls180.v:9034.7-9040.10" - switch \builder_request [0] - attribute \src "ls180.v:9034.11-9034.29" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:9036.11-9036.15" - case - attribute \src "ls180.v:9037.8-9039.11" - switch \builder_request [1] - attribute \src "ls180.v:9037.12-9037.30" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - case - end - end end end case end attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:9046.4-9062.7" - switch $not$ls180.v:9046$2889_Y - attribute \src "ls180.v:9046.8-9046.29" + case 2'01 + attribute \src "ls180.v:4985.4-4993.7" + switch $not$ls180.v:4985$1430_Y + attribute \src "ls180.v:4985.8-4985.33" case 1'1 - attribute \src "ls180.v:9047.5-9061.8" - switch \builder_request [4] - attribute \src "ls180.v:9047.9-9047.27" + attribute \src "ls180.v:4986.5-4992.8" + switch \libresocsim_request [2] + attribute \src "ls180.v:4986.9-4986.31" case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:9049.9-9049.13" + assign $0\libresocsim_grant[1:0] 2'10 + attribute \src "ls180.v:4988.9-4988.13" case - attribute \src "ls180.v:9050.6-9060.9" - switch \builder_request [0] - attribute \src "ls180.v:9050.10-9050.28" + attribute \src "ls180.v:4989.6-4991.9" + switch \libresocsim_request [0] + attribute \src "ls180.v:4989.10-4989.32" case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:9052.10-9052.14" + assign $0\libresocsim_grant[1:0] 2'00 case - attribute \src "ls180.v:9053.7-9059.10" - switch \builder_request [1] - attribute \src "ls180.v:9053.11-9053.29" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:9055.11-9055.15" - case - attribute \src "ls180.v:9056.8-9058.11" - switch \builder_request [2] - attribute \src "ls180.v:9056.12-9056.30" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - case - end - end end end case end attribute \src "ls180.v:0.0-0.0" - case 3'100 - attribute \src "ls180.v:9065.4-9081.7" - switch $not$ls180.v:9065$2890_Y - attribute \src "ls180.v:9065.8-9065.29" + case 2'10 + attribute \src "ls180.v:4996.4-5004.7" + switch $not$ls180.v:4996$1431_Y + attribute \src "ls180.v:4996.8-4996.33" case 1'1 - attribute \src "ls180.v:9066.5-9080.8" - switch \builder_request [0] - attribute \src "ls180.v:9066.9-9066.27" + attribute \src "ls180.v:4997.5-5003.8" + switch \libresocsim_request [0] + attribute \src "ls180.v:4997.9-4997.31" case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:9068.9-9068.13" + assign $0\libresocsim_grant[1:0] 2'00 + attribute \src "ls180.v:4999.9-4999.13" case - attribute \src "ls180.v:9069.6-9079.9" - switch \builder_request [1] - attribute \src "ls180.v:9069.10-9069.28" + attribute \src "ls180.v:5000.6-5002.9" + switch \libresocsim_request [1] + attribute \src "ls180.v:5000.10-5000.32" case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:9071.10-9071.14" + assign $0\libresocsim_grant[1:0] 2'01 case - attribute \src "ls180.v:9072.7-9078.10" - switch \builder_request [2] - attribute \src "ls180.v:9072.11-9072.29" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:9074.11-9074.15" - case - attribute \src "ls180.v:9075.8-9077.11" - switch \builder_request [3] - attribute \src "ls180.v:9075.12-9075.30" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - case - end - end end end case end case end - attribute \src "ls180.v:9085.2-9091.5" - switch \builder_wait - attribute \src "ls180.v:9085.6-9085.18" - case 1'1 - attribute \src "ls180.v:9086.3-9088.6" - switch $not$ls180.v:9086$2891_Y - attribute \src "ls180.v:9086.7-9086.22" - case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:9087$2892_Y - case - end - attribute \src "ls180.v:9089.6-9089.10" - case - assign $0\builder_count[19:0] 20'11110100001001000000 - end - attribute \src "ls180.v:9093.2-9123.5" - switch \builder_csrbank0_sel - attribute \src "ls180.v:9093.6-9093.26" - case 1'1 - attribute \src "ls180.v:9094.3-9122.10" - switch \builder_interface0_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w - case - end - case - end - attribute \src "ls180.v:9124.2-9126.5" - switch \builder_csrbank0_reset0_re - attribute \src "ls180.v:9124.6-9124.32" - case 1'1 - assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r - case - end - attribute \src "ls180.v:9128.2-9130.5" - switch \builder_csrbank0_scratch3_re - attribute \src "ls180.v:9128.6-9128.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r - case - end - attribute \src "ls180.v:9131.2-9133.5" - switch \builder_csrbank0_scratch2_re - attribute \src "ls180.v:9131.6-9131.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r - case - end - attribute \src "ls180.v:9134.2-9136.5" - switch \builder_csrbank0_scratch1_re - attribute \src "ls180.v:9134.6-9134.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r - case - end - attribute \src "ls180.v:9137.2-9139.5" - switch \builder_csrbank0_scratch0_re - attribute \src "ls180.v:9137.6-9137.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r - case - end - attribute \src "ls180.v:9142.2-9163.5" - switch \builder_csrbank1_sel - attribute \src "ls180.v:9142.6-9142.26" - case 1'1 - attribute \src "ls180.v:9143.3-9162.10" - switch \builder_interface1_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe1_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe0_w - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in1_w - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in0_w - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out1_w - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out0_w - case - end - case - end - attribute \src "ls180.v:9164.2-9166.5" - switch \builder_csrbank1_oe1_re - attribute \src "ls180.v:9164.6-9164.29" - case 1'1 - assign $0\main_gpiotristateasic1_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r - case - end - attribute \src "ls180.v:9167.2-9169.5" - switch \builder_csrbank1_oe0_re - attribute \src "ls180.v:9167.6-9167.29" - case 1'1 - assign $0\main_gpiotristateasic1_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r - case - end - attribute \src "ls180.v:9171.2-9173.5" - switch \builder_csrbank1_out1_re - attribute \src "ls180.v:9171.6-9171.30" - case 1'1 - assign $0\main_gpiotristateasic1_out_storage[15:0] [15:8] \builder_csrbank1_out1_r - case - end - attribute \src "ls180.v:9174.2-9176.5" - switch \builder_csrbank1_out0_re - attribute \src "ls180.v:9174.6-9174.30" + attribute \src "ls180.v:5008.2-5014.5" + switch \libresocsim_wait + attribute \src "ls180.v:5008.6-5008.22" case 1'1 - assign $0\main_gpiotristateasic1_out_storage[15:0] [7:0] \builder_csrbank1_out0_r - case - end - attribute \src "ls180.v:9179.2-9188.5" - switch \builder_csrbank2_sel - attribute \src "ls180.v:9179.6-9179.26" - case 1'1 - attribute \src "ls180.v:9180.3-9187.10" - switch \builder_interface2_bank_bus_adr [0] - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\builder_interface2_bank_bus_dat_r[7:0] { 5'00000 \builder_csrbank2_w0_w } - attribute \src "ls180.v:0.0-0.0" + attribute \src "ls180.v:5009.3-5011.6" + switch $not$ls180.v:5009$1432_Y + attribute \src "ls180.v:5009.7-5009.26" case 1'1 - assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_r_w } - case - end - case - end - attribute \src "ls180.v:9189.2-9191.5" - switch \builder_csrbank2_w0_re - attribute \src "ls180.v:9189.6-9189.28" - case 1'1 - assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r - case - end - attribute \src "ls180.v:9194.2-9224.5" - switch \builder_csrbank3_sel - attribute \src "ls180.v:9194.6-9194.26" - case 1'1 - attribute \src "ls180.v:9195.3-9223.10" - switch \builder_interface3_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w - case - end - case - end - attribute \src "ls180.v:9225.2-9227.5" - switch \builder_csrbank3_enable0_re - attribute \src "ls180.v:9225.6-9225.33" - case 1'1 - assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r - case - end - attribute \src "ls180.v:9229.2-9231.5" - switch \builder_csrbank3_width3_re - attribute \src "ls180.v:9229.6-9229.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r - case - end - attribute \src "ls180.v:9232.2-9234.5" - switch \builder_csrbank3_width2_re - attribute \src "ls180.v:9232.6-9232.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r - case - end - attribute \src "ls180.v:9235.2-9237.5" - switch \builder_csrbank3_width1_re - attribute \src "ls180.v:9235.6-9235.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r - case - end - attribute \src "ls180.v:9238.2-9240.5" - switch \builder_csrbank3_width0_re - attribute \src "ls180.v:9238.6-9238.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r - case - end - attribute \src "ls180.v:9242.2-9244.5" - switch \builder_csrbank3_period3_re - attribute \src "ls180.v:9242.6-9242.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r - case - end - attribute \src "ls180.v:9245.2-9247.5" - switch \builder_csrbank3_period2_re - attribute \src "ls180.v:9245.6-9245.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r - case - end - attribute \src "ls180.v:9248.2-9250.5" - switch \builder_csrbank3_period1_re - attribute \src "ls180.v:9248.6-9248.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r - case - end - attribute \src "ls180.v:9251.2-9253.5" - switch \builder_csrbank3_period0_re - attribute \src "ls180.v:9251.6-9251.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r - case - end - attribute \src "ls180.v:9256.2-9286.5" - switch \builder_csrbank4_sel - attribute \src "ls180.v:9256.6-9256.26" - case 1'1 - attribute \src "ls180.v:9257.3-9285.10" - switch \builder_interface4_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period0_w + assign $0\libresocsim_count[19:0] $sub$ls180.v:5010$1433_Y case end + attribute \src "ls180.v:5012.6-5012.10" case + assign $0\libresocsim_count[19:0] 20'11110100001001000000 end - attribute \src "ls180.v:9287.2-9289.5" - switch \builder_csrbank4_enable0_re - attribute \src "ls180.v:9287.6-9287.33" - case 1'1 - assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r - case - end - attribute \src "ls180.v:9291.2-9293.5" - switch \builder_csrbank4_width3_re - attribute \src "ls180.v:9291.6-9291.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r - case - end - attribute \src "ls180.v:9294.2-9296.5" - switch \builder_csrbank4_width2_re - attribute \src "ls180.v:9294.6-9294.32" + attribute \src "ls180.v:5016.2-5046.5" + switch \libresocsim_csrbank0_sel + attribute \src "ls180.v:5016.6-5016.30" case 1'1 - assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r - case - end - attribute \src "ls180.v:9297.2-9299.5" - switch \builder_csrbank4_width1_re - attribute \src "ls180.v:9297.6-9297.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r - case - end - attribute \src "ls180.v:9300.2-9302.5" - switch \builder_csrbank4_width0_re - attribute \src "ls180.v:9300.6-9300.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r - case - end - attribute \src "ls180.v:9304.2-9306.5" - switch \builder_csrbank4_period3_re - attribute \src "ls180.v:9304.6-9304.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r - case - end - attribute \src "ls180.v:9307.2-9309.5" - switch \builder_csrbank4_period2_re - attribute \src "ls180.v:9307.6-9307.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r - case - end - attribute \src "ls180.v:9310.2-9312.5" - switch \builder_csrbank4_period1_re - attribute \src "ls180.v:9310.6-9310.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r - case - end - attribute \src "ls180.v:9313.2-9315.5" - switch \builder_csrbank4_period0_re - attribute \src "ls180.v:9313.6-9313.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r - case - end - attribute \src "ls180.v:9318.2-9366.5" - switch \builder_csrbank5_sel - attribute \src "ls180.v:9318.6-9318.26" - case 1'1 - attribute \src "ls180.v:9319.3-9365.10" - switch \builder_interface5_bank_bus_adr [3:0] + attribute \src "ls180.v:5017.3-5045.10" + switch \libresocsim_interface0_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank0_reset0_w } attribute \src "ls180.v:0.0-0.0" case 4'0001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_scratch3_w attribute \src "ls180.v:0.0-0.0" case 4'0010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_scratch2_w attribute \src "ls180.v:0.0-0.0" case 4'0011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_scratch1_w attribute \src "ls180.v:0.0-0.0" case 4'0100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_scratch0_w attribute \src "ls180.v:0.0-0.0" case 4'0101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_bus_errors3_w attribute \src "ls180.v:0.0-0.0" case 4'0110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_bus_errors2_w attribute \src "ls180.v:0.0-0.0" case 4'0111 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_bus_errors1_w attribute \src "ls180.v:0.0-0.0" case 4'1000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:0.0-0.0" - case 4'1001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:0.0-0.0" - case 4'1010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'1101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w } - attribute \src "ls180.v:0.0-0.0" - case 4'1110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w } - case - end - case - end - attribute \src "ls180.v:9367.2-9369.5" - switch \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:9367.6-9367.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r - case - end - attribute \src "ls180.v:9370.2-9372.5" - switch \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:9370.6-9370.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r - case - end - attribute \src "ls180.v:9373.2-9375.5" - switch \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:9373.6-9373.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r - case - end - attribute \src "ls180.v:9376.2-9378.5" - switch \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:9376.6-9376.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r - case - end - attribute \src "ls180.v:9379.2-9381.5" - switch \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:9379.6-9379.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r - case - end - attribute \src "ls180.v:9382.2-9384.5" - switch \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:9382.6-9382.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r - case - end - attribute \src "ls180.v:9385.2-9387.5" - switch \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:9385.6-9385.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r - case - end - attribute \src "ls180.v:9388.2-9390.5" - switch \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:9388.6-9388.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r - case - end - attribute \src "ls180.v:9392.2-9394.5" - switch \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:9392.6-9392.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r - case - end - attribute \src "ls180.v:9395.2-9397.5" - switch \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:9395.6-9395.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r - case - end - attribute \src "ls180.v:9398.2-9400.5" - switch \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:9398.6-9398.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r - case - end - attribute \src "ls180.v:9401.2-9403.5" - switch \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:9401.6-9401.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r - case - end - attribute \src "ls180.v:9405.2-9407.5" - switch \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:9405.6-9405.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r - case - end - attribute \src "ls180.v:9409.2-9411.5" - switch \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:9409.6-9409.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r - case - end - attribute \src "ls180.v:9414.2-9516.5" - switch \builder_csrbank6_sel - attribute \src "ls180.v:9414.6-9414.26" - case 1'1 - attribute \src "ls180.v:9415.3-9515.10" - switch \builder_interface6_bank_bus_adr [5:0] - attribute \src "ls180.v:0.0-0.0" - case 6'000000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:0.0-0.0" - case 6'000001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:0.0-0.0" - case 6'000010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:0.0-0.0" - case 6'000011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:0.0-0.0" - case 6'000100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:0.0-0.0" - case 6'000101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:0.0-0.0" - case 6'000110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:0.0-0.0" - case 6'000111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:0.0-0.0" - case 6'001000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } - attribute \src "ls180.v:0.0-0.0" - case 6'001001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:0.0-0.0" - case 6'001010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:0.0-0.0" - case 6'001011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:0.0-0.0" - case 6'001100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:0.0-0.0" - case 6'001101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:0.0-0.0" - case 6'001110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:0.0-0.0" - case 6'001111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:0.0-0.0" - case 6'010000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:0.0-0.0" - case 6'010001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:0.0-0.0" - case 6'010010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:0.0-0.0" - case 6'010011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:0.0-0.0" - case 6'010100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:0.0-0.0" - case 6'010101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:0.0-0.0" - case 6'010110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:0.0-0.0" - case 6'010111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:0.0-0.0" - case 6'011000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:0.0-0.0" - case 6'011001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_cmd_event_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_data_event_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank6_block_length1_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_length0_w - attribute \src "ls180.v:0.0-0.0" - case 6'011101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count3_w - attribute \src "ls180.v:0.0-0.0" - case 6'011110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count2_w - attribute \src "ls180.v:0.0-0.0" - case 6'011111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count1_w - attribute \src "ls180.v:0.0-0.0" - case 6'100000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count0_w - case - end - case - end - attribute \src "ls180.v:9517.2-9519.5" - switch \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:9517.6-9517.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r - case - end - attribute \src "ls180.v:9520.2-9522.5" - switch \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:9520.6-9520.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r - case - end - attribute \src "ls180.v:9523.2-9525.5" - switch \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:9523.6-9523.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r - case - end - attribute \src "ls180.v:9526.2-9528.5" - switch \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:9526.6-9526.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r - case - end - attribute \src "ls180.v:9530.2-9532.5" - switch \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:9530.6-9530.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r - case - end - attribute \src "ls180.v:9533.2-9535.5" - switch \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:9533.6-9533.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r - case - end - attribute \src "ls180.v:9536.2-9538.5" - switch \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:9536.6-9536.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r - case - end - attribute \src "ls180.v:9539.2-9541.5" - switch \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:9539.6-9539.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r - case - end - attribute \src "ls180.v:9543.2-9545.5" - switch \builder_csrbank6_block_length1_re - attribute \src "ls180.v:9543.6-9543.39" - case 1'1 - assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r - case - end - attribute \src "ls180.v:9546.2-9548.5" - switch \builder_csrbank6_block_length0_re - attribute \src "ls180.v:9546.6-9546.39" - case 1'1 - assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r - case - end - attribute \src "ls180.v:9550.2-9552.5" - switch \builder_csrbank6_block_count3_re - attribute \src "ls180.v:9550.6-9550.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r - case - end - attribute \src "ls180.v:9553.2-9555.5" - switch \builder_csrbank6_block_count2_re - attribute \src "ls180.v:9553.6-9553.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r - case - end - attribute \src "ls180.v:9556.2-9558.5" - switch \builder_csrbank6_block_count1_re - attribute \src "ls180.v:9556.6-9556.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r - case - end - attribute \src "ls180.v:9559.2-9561.5" - switch \builder_csrbank6_block_count0_re - attribute \src "ls180.v:9559.6-9559.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r - case - end - attribute \src "ls180.v:9564.2-9624.5" - switch \builder_csrbank7_sel - attribute \src "ls180.v:9564.6-9564.26" - case 1'1 - attribute \src "ls180.v:9565.3-9623.10" - switch \builder_interface7_bank_bus_adr [4:0] - attribute \src "ls180.v:0.0-0.0" - case 5'00000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:0.0-0.0" - case 5'00001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:0.0-0.0" - case 5'00010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:0.0-0.0" - case 5'00011 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:0.0-0.0" - case 5'00100 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:0.0-0.0" - case 5'00101 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:0.0-0.0" - case 5'00110 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:0.0-0.0" - case 5'00111 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:0.0-0.0" - case 5'01001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:0.0-0.0" - case 5'01010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:0.0-0.0" - case 5'01011 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01100 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01101 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_done_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01110 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_loop0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01111 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:0.0-0.0" - case 5'10000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:0.0-0.0" - case 5'10001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:0.0-0.0" - case 5'10010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset0_w + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_bus_errors0_w case end case end - attribute \src "ls180.v:9625.2-9627.5" - switch \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:9625.6-9625.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r - case - end - attribute \src "ls180.v:9628.2-9630.5" - switch \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:9628.6-9628.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r - case - end - attribute \src "ls180.v:9631.2-9633.5" - switch \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:9631.6-9631.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r - case - end - attribute \src "ls180.v:9634.2-9636.5" - switch \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:9634.6-9634.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r - case - end - attribute \src "ls180.v:9637.2-9639.5" - switch \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:9637.6-9637.35" + attribute \src "ls180.v:5047.2-5049.5" + switch \libresocsim_csrbank0_reset0_re + attribute \src "ls180.v:5047.6-5047.36" case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r + assign $0\libresocsim_reset_storage[0:0] \libresocsim_csrbank0_reset0_r case end - attribute \src "ls180.v:9640.2-9642.5" - switch \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:9640.6-9640.35" + attribute \src "ls180.v:5051.2-5053.5" + switch \libresocsim_csrbank0_scratch3_re + attribute \src "ls180.v:5051.6-5051.38" case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r + assign $0\libresocsim_scratch_storage[31:0] [31:24] \libresocsim_csrbank0_scratch3_r case end - attribute \src "ls180.v:9643.2-9645.5" - switch \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:9643.6-9643.35" + attribute \src "ls180.v:5054.2-5056.5" + switch \libresocsim_csrbank0_scratch2_re + attribute \src "ls180.v:5054.6-5054.38" case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r + assign $0\libresocsim_scratch_storage[31:0] [23:16] \libresocsim_csrbank0_scratch2_r case end - attribute \src "ls180.v:9646.2-9648.5" - switch \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:9646.6-9646.35" + attribute \src "ls180.v:5057.2-5059.5" + switch \libresocsim_csrbank0_scratch1_re + attribute \src "ls180.v:5057.6-5057.38" case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r + assign $0\libresocsim_scratch_storage[31:0] [15:8] \libresocsim_csrbank0_scratch1_r case end - attribute \src "ls180.v:9650.2-9652.5" - switch \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:9650.6-9650.37" + attribute \src "ls180.v:5060.2-5062.5" + switch \libresocsim_csrbank0_scratch0_re + attribute \src "ls180.v:5060.6-5060.38" case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r + assign $0\libresocsim_scratch_storage[31:0] [7:0] \libresocsim_csrbank0_scratch0_r case end - attribute \src "ls180.v:9653.2-9655.5" - switch \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:9653.6-9653.37" + attribute \src "ls180.v:5065.2-5077.5" + switch \libresocsim_csrbank1_sel + attribute \src "ls180.v:5065.6-5065.30" case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r - case - end - attribute \src "ls180.v:9656.2-9658.5" - switch \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:9656.6-9656.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r - case - end - attribute \src "ls180.v:9659.2-9661.5" - switch \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:9659.6-9659.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r - case - end - attribute \src "ls180.v:9663.2-9665.5" - switch \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:9663.6-9663.37" - case 1'1 - assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r - case - end - attribute \src "ls180.v:9667.2-9669.5" - switch \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:9667.6-9667.35" - case 1'1 - assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r - case - end - attribute \src "ls180.v:9672.2-9687.5" - switch \builder_csrbank8_sel - attribute \src "ls180.v:9672.6-9672.26" - case 1'1 - attribute \src "ls180.v:9673.3-9686.10" - switch \builder_interface8_bank_bus_adr [1:0] + attribute \src "ls180.v:5066.3-5076.10" + switch \libresocsim_interface1_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_card_detect_w } + assign $0\libresocsim_interface1_bank_bus_dat_r[7:0] \libresocsim_csrbank1_oe0_w attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_clocker_divider1_w } + assign $0\libresocsim_interface1_bank_bus_dat_r[7:0] \libresocsim_csrbank1_in_w attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } + assign $0\libresocsim_interface1_bank_bus_dat_r[7:0] \libresocsim_csrbank1_out0_w case end case end - attribute \src "ls180.v:9688.2-9690.5" - switch \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:9688.6-9688.42" + attribute \src "ls180.v:5078.2-5080.5" + switch \libresocsim_csrbank1_oe0_re + attribute \src "ls180.v:5078.6-5078.33" case 1'1 - assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r + assign $0\gpio0_oe_storage[7:0] \libresocsim_csrbank1_oe0_r case end - attribute \src "ls180.v:9691.2-9693.5" - switch \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:9691.6-9691.42" + attribute \src "ls180.v:5082.2-5084.5" + switch \libresocsim_csrbank1_out0_re + attribute \src "ls180.v:5082.6-5082.34" case 1'1 - assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r + assign $0\gpio0_out_storage[7:0] \libresocsim_csrbank1_out0_r case end - attribute \src "ls180.v:9696.2-9729.5" - switch \builder_csrbank9_sel - attribute \src "ls180.v:9696.6-9696.26" + attribute \src "ls180.v:5087.2-5099.5" + switch \libresocsim_csrbank2_sel + attribute \src "ls180.v:5087.6-5087.30" case 1'1 - attribute \src "ls180.v:9697.3-9728.10" - switch \builder_interface9_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank9_dfii_control0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank9_dfii_pi0_command0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank9_dfii_pi0_address1_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_address0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank9_dfii_pi0_baddress0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata1_w + attribute \src "ls180.v:5088.3-5098.10" + switch \libresocsim_interface2_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata0_w + case 2'00 + assign $0\libresocsim_interface2_bank_bus_dat_r[7:0] \libresocsim_csrbank2_oe0_w attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata1_w + case 2'01 + assign $0\libresocsim_interface2_bank_bus_dat_r[7:0] \libresocsim_csrbank2_in_w attribute \src "ls180.v:0.0-0.0" - case 4'1001 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata0_w + case 2'10 + assign $0\libresocsim_interface2_bank_bus_dat_r[7:0] \libresocsim_csrbank2_out0_w case end case end - attribute \src "ls180.v:9730.2-9732.5" - switch \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:9730.6-9730.39" - case 1'1 - assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r - case - end - attribute \src "ls180.v:9734.2-9736.5" - switch \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:9734.6-9734.43" - case 1'1 - assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r - case - end - attribute \src "ls180.v:9738.2-9740.5" - switch \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:9738.6-9738.43" - case 1'1 - assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r - case - end - attribute \src "ls180.v:9741.2-9743.5" - switch \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:9741.6-9741.43" - case 1'1 - assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r - case - end - attribute \src "ls180.v:9745.2-9747.5" - switch \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:9745.6-9745.44" - case 1'1 - assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r - case - end - attribute \src "ls180.v:9749.2-9751.5" - switch \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:9749.6-9749.42" + attribute \src "ls180.v:5100.2-5102.5" + switch \libresocsim_csrbank2_oe0_re + attribute \src "ls180.v:5100.6-5100.33" case 1'1 - assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r + assign $0\gpio1_oe_storage[7:0] \libresocsim_csrbank2_oe0_r case end - attribute \src "ls180.v:9752.2-9754.5" - switch \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:9752.6-9752.42" + attribute \src "ls180.v:5104.2-5106.5" + switch \libresocsim_csrbank2_out0_re + attribute \src "ls180.v:5104.6-5104.34" case 1'1 - assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r + assign $0\gpio1_out_storage[7:0] \libresocsim_csrbank2_out0_r case end - attribute \src "ls180.v:9757.2-9781.5" - switch \builder_csrbank10_sel - attribute \src "ls180.v:9757.6-9757.27" + attribute \src "ls180.v:5109.2-5118.5" + switch \libresocsim_csrbank3_sel + attribute \src "ls180.v:5109.6-5109.30" case 1'1 - attribute \src "ls180.v:9758.3-9780.10" - switch \builder_interface10_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w + attribute \src "ls180.v:5110.3-5117.10" + switch \libresocsim_interface3_bank_bus_adr [0] attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } + case 1'0 + assign $0\libresocsim_interface3_bank_bus_dat_r[7:0] { 5'00000 \libresocsim_csrbank3_w0_w } attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } + case 1'1 + assign $0\libresocsim_interface3_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank3_r_w } case end case end - attribute \src "ls180.v:9782.2-9784.5" - switch \builder_csrbank10_control1_re - attribute \src "ls180.v:9782.6-9782.35" - case 1'1 - assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r - case - end - attribute \src "ls180.v:9785.2-9787.5" - switch \builder_csrbank10_control0_re - attribute \src "ls180.v:9785.6-9785.35" - case 1'1 - assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r - case - end - attribute \src "ls180.v:9789.2-9791.5" - switch \builder_csrbank10_mosi0_re - attribute \src "ls180.v:9789.6-9789.32" + attribute \src "ls180.v:5119.2-5121.5" + switch \libresocsim_csrbank3_w0_re + attribute \src "ls180.v:5119.6-5119.32" case 1'1 - assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r + assign $0\i2c_storage[2:0] \libresocsim_csrbank3_w0_r case end - attribute \src "ls180.v:9793.2-9795.5" - switch \builder_csrbank10_cs0_re - attribute \src "ls180.v:9793.6-9793.30" + attribute \src "ls180.v:5124.2-5157.5" + switch \libresocsim_csrbank4_sel + attribute \src "ls180.v:5124.6-5124.30" case 1'1 - assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r - case - end - attribute \src "ls180.v:9797.2-9799.5" - switch \builder_csrbank10_loopback0_re - attribute \src "ls180.v:9797.6-9797.36" - case 1'1 - assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r - case - end - attribute \src "ls180.v:9802.2-9832.5" - switch \builder_csrbank11_sel - attribute \src "ls180.v:9802.6-9802.27" - case 1'1 - attribute \src "ls180.v:9803.3-9831.10" - switch \builder_interface11_bank_bus_adr [3:0] + attribute \src "ls180.v:5125.3-5156.10" + switch \libresocsim_interface4_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control1_w + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 4'0000 \libresocsim_csrbank4_dfii_control0_w } attribute \src "ls180.v:0.0-0.0" case 4'0001 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control0_w + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 2'00 \libresocsim_csrbank4_dfii_pi0_command0_w } attribute \src "ls180.v:0.0-0.0" case 4'0010 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_status_w } + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 7'0000000 \sdram_command_issue_w } attribute \src "ls180.v:0.0-0.0" case 4'0011 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_mosi0_w + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 3'000 \libresocsim_csrbank4_dfii_pi0_address1_w } attribute \src "ls180.v:0.0-0.0" case 4'0100 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_miso_w + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_address0_w attribute \src "ls180.v:0.0-0.0" case 4'0101 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_cs0_w } + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 6'000000 \libresocsim_csrbank4_dfii_pi0_baddress0_w } attribute \src "ls180.v:0.0-0.0" case 4'0110 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_loopback0_w } + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_wrdata1_w attribute \src "ls180.v:0.0-0.0" case 4'0111 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider1_w + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_wrdata0_w attribute \src "ls180.v:0.0-0.0" case 4'1000 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider0_w + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_rddata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_rddata0_w case end case end - attribute \src "ls180.v:9833.2-9835.5" - switch \builder_csrbank11_control1_re - attribute \src "ls180.v:9833.6-9833.35" + attribute \src "ls180.v:5158.2-5160.5" + switch \libresocsim_csrbank4_dfii_control0_re + attribute \src "ls180.v:5158.6-5158.43" case 1'1 - assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r + assign $0\sdram_storage[3:0] \libresocsim_csrbank4_dfii_control0_r case end - attribute \src "ls180.v:9836.2-9838.5" - switch \builder_csrbank11_control0_re - attribute \src "ls180.v:9836.6-9836.35" + attribute \src "ls180.v:5162.2-5164.5" + switch \libresocsim_csrbank4_dfii_pi0_command0_re + attribute \src "ls180.v:5162.6-5162.47" case 1'1 - assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r + assign $0\sdram_command_storage[5:0] \libresocsim_csrbank4_dfii_pi0_command0_r case end - attribute \src "ls180.v:9840.2-9842.5" - switch \builder_csrbank11_mosi0_re - attribute \src "ls180.v:9840.6-9840.32" + attribute \src "ls180.v:5166.2-5168.5" + switch \libresocsim_csrbank4_dfii_pi0_address1_re + attribute \src "ls180.v:5166.6-5166.47" case 1'1 - assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r + assign $0\sdram_address_storage[12:0] [12:8] \libresocsim_csrbank4_dfii_pi0_address1_r case end - attribute \src "ls180.v:9844.2-9846.5" - switch \builder_csrbank11_cs0_re - attribute \src "ls180.v:9844.6-9844.30" + attribute \src "ls180.v:5169.2-5171.5" + switch \libresocsim_csrbank4_dfii_pi0_address0_re + attribute \src "ls180.v:5169.6-5169.47" case 1'1 - assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r + assign $0\sdram_address_storage[12:0] [7:0] \libresocsim_csrbank4_dfii_pi0_address0_r case end - attribute \src "ls180.v:9848.2-9850.5" - switch \builder_csrbank11_loopback0_re - attribute \src "ls180.v:9848.6-9848.36" + attribute \src "ls180.v:5173.2-5175.5" + switch \libresocsim_csrbank4_dfii_pi0_baddress0_re + attribute \src "ls180.v:5173.6-5173.48" case 1'1 - assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r + assign $0\sdram_baddress_storage[1:0] \libresocsim_csrbank4_dfii_pi0_baddress0_r case end - attribute \src "ls180.v:9852.2-9854.5" - switch \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:9852.6-9852.39" + attribute \src "ls180.v:5177.2-5179.5" + switch \libresocsim_csrbank4_dfii_pi0_wrdata1_re + attribute \src "ls180.v:5177.6-5177.46" case 1'1 - assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r + assign $0\sdram_wrdata_storage[15:0] [15:8] \libresocsim_csrbank4_dfii_pi0_wrdata1_r case end - attribute \src "ls180.v:9855.2-9857.5" - switch \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:9855.6-9855.39" + attribute \src "ls180.v:5180.2-5182.5" + switch \libresocsim_csrbank4_dfii_pi0_wrdata0_re + attribute \src "ls180.v:5180.6-5180.46" case 1'1 - assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r + assign $0\sdram_wrdata_storage[15:0] [7:0] \libresocsim_csrbank4_dfii_pi0_wrdata0_r case end - attribute \src "ls180.v:9860.2-9914.5" - switch \builder_csrbank12_sel - attribute \src "ls180.v:9860.6-9860.27" + attribute \src "ls180.v:5185.2-5239.5" + switch \libresocsim_csrbank5_sel + attribute \src "ls180.v:5185.6-5185.30" case 1'1 - attribute \src "ls180.v:9861.3-9913.10" - switch \builder_interface12_bank_bus_adr [4:0] + attribute \src "ls180.v:5186.3-5238.10" + switch \libresocsim_interface5_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load3_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_load3_w attribute \src "ls180.v:0.0-0.0" case 5'00001 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load2_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_load2_w attribute \src "ls180.v:0.0-0.0" case 5'00010 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load1_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_load1_w attribute \src "ls180.v:0.0-0.0" case 5'00011 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load0_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_load0_w attribute \src "ls180.v:0.0-0.0" case 5'00100 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload3_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_reload3_w attribute \src "ls180.v:0.0-0.0" case 5'00101 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload2_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_reload2_w attribute \src "ls180.v:0.0-0.0" case 5'00110 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload1_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_reload1_w attribute \src "ls180.v:0.0-0.0" case 5'00111 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload0_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_reload0_w attribute \src "ls180.v:0.0-0.0" case 5'01000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_en0_w } + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank5_en0_w } attribute \src "ls180.v:0.0-0.0" case 5'01001 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_update_value0_w } + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank5_update_value0_w } attribute \src "ls180.v:0.0-0.0" case 5'01010 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value3_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_value3_w attribute \src "ls180.v:0.0-0.0" case 5'01011 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value2_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_value2_w attribute \src "ls180.v:0.0-0.0" case 5'01100 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value1_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_value1_w attribute \src "ls180.v:0.0-0.0" case 5'01101 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value0_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_value0_w attribute \src "ls180.v:0.0-0.0" case 5'01110 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_eventmanager_status_w } attribute \src "ls180.v:0.0-0.0" case 5'01111 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_eventmanager_pending_w } attribute \src "ls180.v:0.0-0.0" case 5'10000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_ev_enable0_w } + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank5_ev_enable0_w } case end case end - attribute \src "ls180.v:9915.2-9917.5" - switch \builder_csrbank12_load3_re - attribute \src "ls180.v:9915.6-9915.32" + attribute \src "ls180.v:5240.2-5242.5" + switch \libresocsim_csrbank5_load3_re + attribute \src "ls180.v:5240.6-5240.35" case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r + assign $0\libresocsim_load_storage[31:0] [31:24] \libresocsim_csrbank5_load3_r case end - attribute \src "ls180.v:9918.2-9920.5" - switch \builder_csrbank12_load2_re - attribute \src "ls180.v:9918.6-9918.32" + attribute \src "ls180.v:5243.2-5245.5" + switch \libresocsim_csrbank5_load2_re + attribute \src "ls180.v:5243.6-5243.35" case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r + assign $0\libresocsim_load_storage[31:0] [23:16] \libresocsim_csrbank5_load2_r case end - attribute \src "ls180.v:9921.2-9923.5" - switch \builder_csrbank12_load1_re - attribute \src "ls180.v:9921.6-9921.32" + attribute \src "ls180.v:5246.2-5248.5" + switch \libresocsim_csrbank5_load1_re + attribute \src "ls180.v:5246.6-5246.35" case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r + assign $0\libresocsim_load_storage[31:0] [15:8] \libresocsim_csrbank5_load1_r case end - attribute \src "ls180.v:9924.2-9926.5" - switch \builder_csrbank12_load0_re - attribute \src "ls180.v:9924.6-9924.32" + attribute \src "ls180.v:5249.2-5251.5" + switch \libresocsim_csrbank5_load0_re + attribute \src "ls180.v:5249.6-5249.35" case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r + assign $0\libresocsim_load_storage[31:0] [7:0] \libresocsim_csrbank5_load0_r case end - attribute \src "ls180.v:9928.2-9930.5" - switch \builder_csrbank12_reload3_re - attribute \src "ls180.v:9928.6-9928.34" + attribute \src "ls180.v:5253.2-5255.5" + switch \libresocsim_csrbank5_reload3_re + attribute \src "ls180.v:5253.6-5253.37" case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r + assign $0\libresocsim_reload_storage[31:0] [31:24] \libresocsim_csrbank5_reload3_r case end - attribute \src "ls180.v:9931.2-9933.5" - switch \builder_csrbank12_reload2_re - attribute \src "ls180.v:9931.6-9931.34" + attribute \src "ls180.v:5256.2-5258.5" + switch \libresocsim_csrbank5_reload2_re + attribute \src "ls180.v:5256.6-5256.37" case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r + assign $0\libresocsim_reload_storage[31:0] [23:16] \libresocsim_csrbank5_reload2_r case end - attribute \src "ls180.v:9934.2-9936.5" - switch \builder_csrbank12_reload1_re - attribute \src "ls180.v:9934.6-9934.34" + attribute \src "ls180.v:5259.2-5261.5" + switch \libresocsim_csrbank5_reload1_re + attribute \src "ls180.v:5259.6-5259.37" case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r + assign $0\libresocsim_reload_storage[31:0] [15:8] \libresocsim_csrbank5_reload1_r case end - attribute \src "ls180.v:9937.2-9939.5" - switch \builder_csrbank12_reload0_re - attribute \src "ls180.v:9937.6-9937.34" + attribute \src "ls180.v:5262.2-5264.5" + switch \libresocsim_csrbank5_reload0_re + attribute \src "ls180.v:5262.6-5262.37" case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r + assign $0\libresocsim_reload_storage[31:0] [7:0] \libresocsim_csrbank5_reload0_r case end - attribute \src "ls180.v:9941.2-9943.5" - switch \builder_csrbank12_en0_re - attribute \src "ls180.v:9941.6-9941.30" + attribute \src "ls180.v:5266.2-5268.5" + switch \libresocsim_csrbank5_en0_re + attribute \src "ls180.v:5266.6-5266.33" case 1'1 - assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r + assign $0\libresocsim_en_storage[0:0] \libresocsim_csrbank5_en0_r case end - attribute \src "ls180.v:9945.2-9947.5" - switch \builder_csrbank12_update_value0_re - attribute \src "ls180.v:9945.6-9945.40" + attribute \src "ls180.v:5270.2-5272.5" + switch \libresocsim_csrbank5_update_value0_re + attribute \src "ls180.v:5270.6-5270.43" case 1'1 - assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r + assign $0\libresocsim_update_value_storage[0:0] \libresocsim_csrbank5_update_value0_r case end - attribute \src "ls180.v:9949.2-9951.5" - switch \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:9949.6-9949.37" + attribute \src "ls180.v:5274.2-5276.5" + switch \libresocsim_csrbank5_ev_enable0_re + attribute \src "ls180.v:5274.6-5274.40" case 1'1 - assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r + assign $0\libresocsim_eventmanager_storage[0:0] \libresocsim_csrbank5_ev_enable0_r case end - attribute \src "ls180.v:9954.2-9981.5" - switch \builder_csrbank13_sel - attribute \src "ls180.v:9954.6-9954.27" + attribute \src "ls180.v:5279.2-5306.5" + switch \libresocsim_csrbank6_sel + attribute \src "ls180.v:5279.6-5279.30" case 1'1 - attribute \src "ls180.v:9955.3-9980.10" - switch \builder_interface13_bank_bus_adr [2:0] + attribute \src "ls180.v:5280.3-5305.10" + switch \libresocsim_interface6_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_interface13_bank_bus_dat_r[7:0] \main_uart_rxtx_w + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] \rxtx_w attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txfull_w } + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank6_txfull_w } attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxempty_w } + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank6_rxempty_w } attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 6'000000 \eventmanager_status_w } attribute \src "ls180.v:0.0-0.0" case 3'100 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 6'000000 \eventmanager_pending_w } attribute \src "ls180.v:0.0-0.0" case 3'101 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank13_ev_enable0_w } + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 6'000000 \libresocsim_csrbank6_ev_enable0_w } attribute \src "ls180.v:0.0-0.0" case 3'110 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txempty_w } + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank6_txempty_w } attribute \src "ls180.v:0.0-0.0" case 3'111 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxfull_w } + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank6_rxfull_w } case end case end - attribute \src "ls180.v:9982.2-9984.5" - switch \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:9982.6-9982.37" + attribute \src "ls180.v:5307.2-5309.5" + switch \libresocsim_csrbank6_ev_enable0_re + attribute \src "ls180.v:5307.6-5307.40" case 1'1 - assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r + assign $0\eventmanager_storage[1:0] \libresocsim_csrbank6_ev_enable0_r case end - attribute \src "ls180.v:9987.2-10002.5" - switch \builder_csrbank14_sel - attribute \src "ls180.v:9987.6-9987.27" + attribute \src "ls180.v:5312.2-5327.5" + switch \libresocsim_csrbank7_sel + attribute \src "ls180.v:5312.6-5312.30" case 1'1 - attribute \src "ls180.v:9988.3-10001.10" - switch \builder_interface14_bank_bus_adr [1:0] + attribute \src "ls180.v:5313.3-5326.10" + switch \libresocsim_interface7_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word3_w + assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] \libresocsim_csrbank7_tuning_word3_w attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word2_w + assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] \libresocsim_csrbank7_tuning_word2_w attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word1_w + assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] \libresocsim_csrbank7_tuning_word1_w attribute \src "ls180.v:0.0-0.0" case 2'11 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word0_w + assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] \libresocsim_csrbank7_tuning_word0_w case end case end - attribute \src "ls180.v:10003.2-10005.5" - switch \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:10003.6-10003.39" + attribute \src "ls180.v:5328.2-5330.5" + switch \libresocsim_csrbank7_tuning_word3_re + attribute \src "ls180.v:5328.6-5328.42" case 1'1 - assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r + assign $0\uart_phy_storage[31:0] [31:24] \libresocsim_csrbank7_tuning_word3_r case end - attribute \src "ls180.v:10006.2-10008.5" - switch \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:10006.6-10006.39" + attribute \src "ls180.v:5331.2-5333.5" + switch \libresocsim_csrbank7_tuning_word2_re + attribute \src "ls180.v:5331.6-5331.42" case 1'1 - assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r + assign $0\uart_phy_storage[31:0] [23:16] \libresocsim_csrbank7_tuning_word2_r case end - attribute \src "ls180.v:10009.2-10011.5" - switch \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:10009.6-10009.39" + attribute \src "ls180.v:5334.2-5336.5" + switch \libresocsim_csrbank7_tuning_word1_re + attribute \src "ls180.v:5334.6-5334.42" case 1'1 - assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r + assign $0\uart_phy_storage[31:0] [15:8] \libresocsim_csrbank7_tuning_word1_r case end - attribute \src "ls180.v:10012.2-10014.5" - switch \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:10012.6-10012.39" + attribute \src "ls180.v:5337.2-5339.5" + switch \libresocsim_csrbank7_tuning_word0_re + attribute \src "ls180.v:5337.6-5337.42" case 1'1 - assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r + assign $0\uart_phy_storage[31:0] [7:0] \libresocsim_csrbank7_tuning_word0_r case end - attribute \src "ls180.v:10016.2-10314.5" + attribute \src "ls180.v:5341.2-5488.5" switch \sys_rst_1 - attribute \src "ls180.v:10016.6-10016.15" - case 1'1 - assign $0\main_libresocsim_reset_storage[0:0] 1'0 - assign $0\main_libresocsim_reset_re[0:0] 1'0 - assign $0\main_libresocsim_scratch_storage[31:0] 305419896 - assign $0\main_libresocsim_scratch_re[0:0] 1'0 - assign $0\main_libresocsim_bus_errors[31:0] 0 - assign $0\spisdcard_clk[0:0] 1'0 - assign $0\spisdcard_mosi[0:0] 1'0 - assign $0\spisdcard_cs_n[0:0] 1'0 - assign $0\pwm[1:0] 2'00 - assign $0\spimaster_clk[0:0] 1'0 - assign $0\spimaster_mosi[0:0] 1'0 - assign $0\spimaster_cs_n[0:0] 1'0 - assign $0\uart_tx[0:0] 1'1 - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 - assign $0\main_libresocsim_load_storage[31:0] 0 - assign $0\main_libresocsim_load_re[0:0] 1'0 - assign $0\main_libresocsim_reload_storage[31:0] 0 - assign $0\main_libresocsim_reload_re[0:0] 1'0 - assign $0\main_libresocsim_en_storage[0:0] 1'0 - assign $0\main_libresocsim_en_re[0:0] 1'0 - assign $0\main_libresocsim_update_value_storage[0:0] 1'0 - assign $0\main_libresocsim_update_value_re[0:0] 1'0 - assign $0\main_libresocsim_value_status[31:0] 0 - assign $0\main_libresocsim_zero_pending[0:0] 1'0 - assign $0\main_libresocsim_zero_old_trigger[0:0] 1'0 - assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 - assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 - assign $0\main_libresocsim_value[31:0] 0 - assign $0\main_interface0_ram_bus_ack[0:0] 1'0 - assign $0\main_interface1_ram_bus_ack[0:0] 1'0 - assign $0\main_interface2_ram_bus_ack[0:0] 1'0 - assign $0\main_interface3_ram_bus_ack[0:0] 1'0 - assign $0\main_converter0_counter[0:0] 1'0 - assign $0\main_converter1_counter[0:0] 1'0 - assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 - assign $0\main_rddata_en[2:0] 3'000 - assign $0\main_sdram_storage[3:0] 4'0001 - assign $0\main_sdram_re[0:0] 1'0 - assign $0\main_sdram_command_storage[5:0] 6'000000 - assign $0\main_sdram_command_re[0:0] 1'0 - assign $0\main_sdram_address_re[0:0] 1'0 - assign $0\main_sdram_baddress_re[0:0] 1'0 - assign $0\main_sdram_wrdata_re[0:0] 1'0 - assign $0\main_sdram_status[15:0] 16'0000000000000000 - assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 - assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - assign $0\main_sdram_timer_count1[9:0] 10'1100001101 - assign $0\main_sdram_postponer_req_o[0:0] 1'0 - assign $0\main_sdram_postponer_count[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'0 - assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - assign $0\main_sdram_sequencer_count[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - assign $0\main_sdram_tccdcon_ready[0:0] 1'0 - assign $0\main_sdram_tccdcon_count[0:0] 1'0 - assign $0\main_sdram_twtrcon_ready[0:0] 1'0 - assign $0\main_sdram_twtrcon_count[2:0] 3'000 - assign $0\main_sdram_time0[4:0] 5'00000 - assign $0\main_sdram_time1[3:0] 4'0000 - assign $0\main_socbushandler_counter[0:0] 1'0 - assign $0\main_converter_counter[0:0] 1'0 - assign $0\main_cmd_consumed[0:0] 1'0 - assign $0\main_wdata_consumed[0:0] 1'0 - assign $0\main_uart_phy_storage[31:0] 9895604 - assign $0\main_uart_phy_re[0:0] 1'0 - assign $0\main_uart_phy_sink_ready[0:0] 1'0 - assign $0\main_uart_phy_uart_clk_txen[0:0] 1'0 - assign $0\main_uart_phy_tx_busy[0:0] 1'0 - assign $0\main_uart_phy_source_valid[0:0] 1'0 - assign $0\main_uart_phy_uart_clk_rxen[0:0] 1'0 - assign $0\main_uart_phy_rx_r[0:0] 1'0 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 - assign $0\main_uart_tx_pending[0:0] 1'0 - assign $0\main_uart_tx_old_trigger[0:0] 1'0 - assign $0\main_uart_rx_pending[0:0] 1'0 - assign $0\main_uart_rx_old_trigger[0:0] 1'0 - assign $0\main_uart_eventmanager_storage[1:0] 2'00 - assign $0\main_uart_eventmanager_re[0:0] 1'0 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 - assign $0\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 - assign $0\main_gpiotristateasic1_oe_re[0:0] 1'0 - assign $0\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 - assign $0\main_gpiotristateasic1_out_re[0:0] 1'0 - assign $0\main_spimaster5_miso[7:0] 8'00000000 - assign $0\main_spimaster11_storage[15:0] 16'0000000000000000 - assign $0\main_spimaster12_re[0:0] 1'0 - assign $0\main_spimaster17_re[0:0] 1'0 - assign $0\main_spimaster21_storage[0:0] 1'1 - assign $0\main_spimaster22_re[0:0] 1'0 - assign $0\main_spimaster23_storage[0:0] 1'0 - assign $0\main_spimaster24_re[0:0] 1'0 - assign $0\main_spimaster27_count[2:0] 3'000 - assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 - assign $0\main_spimaster33_mosi_data[7:0] 8'00000000 - assign $0\main_spimaster34_mosi_sel[2:0] 3'000 - assign $0\main_spimaster35_miso_data[7:0] 8'00000000 - assign $0\main_spisdcard_miso[7:0] 8'00000000 - assign $0\main_spisdcard_control_storage[15:0] 16'0000000000000000 - assign $0\main_spisdcard_control_re[0:0] 1'0 - assign $0\main_spisdcard_mosi_re[0:0] 1'0 - assign $0\main_spisdcard_cs_storage[0:0] 1'1 - assign $0\main_spisdcard_cs_re[0:0] 1'0 - assign $0\main_spisdcard_loopback_storage[0:0] 1'0 - assign $0\main_spisdcard_loopback_re[0:0] 1'0 - assign $0\main_spisdcard_count[2:0] 3'000 - assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 - assign $0\main_spisdcard_mosi_data[7:0] 8'00000000 - assign $0\main_spisdcard_mosi_sel[2:0] 3'000 - assign $0\main_spisdcard_miso_data[7:0] 8'00000000 - assign $0\main_spimaster1_storage[15:0] 16'0000000001111101 - assign $0\main_spimaster1_re[0:0] 1'0 - assign $0\main_dummy[23:0] 24'000000000000000000000000 - assign $0\main_pwm0_enable_storage[0:0] 1'0 - assign $0\main_pwm0_enable_re[0:0] 1'0 - assign $0\main_pwm0_width_re[0:0] 1'0 - assign $0\main_pwm0_period_re[0:0] 1'0 - assign $0\main_pwm1_enable_storage[0:0] 1'0 - assign $0\main_pwm1_enable_re[0:0] 1'0 - assign $0\main_pwm1_width_re[0:0] 1'0 - assign $0\main_pwm1_period_re[0:0] 1'0 - assign $0\main_i2c_storage[2:0] 3'000 - assign $0\main_i2c_re[0:0] 1'0 - assign $0\main_sdphy_clocker_storage[8:0] 9'100000000 - assign $0\main_sdphy_clocker_re[0:0] 1'0 - assign $0\main_sdphy_clocker_clk0[0:0] 1'0 - assign $0\main_sdphy_clocker_clks[8:0] 9'000000000 - assign $0\main_sdphy_clocker_clk_d[0:0] 1'0 - assign $0\main_sdphy_init_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_timeout[31:0] 500000 - assign $0\main_sdphy_cmdr_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 - assign $0\main_sdphy_dataw_count[7:0] 8'00000000 - assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset[0:0] 1'0 - assign $0\main_sdphy_datar_timeout[31:0] 500000 - assign $0\main_sdphy_datar_count[9:0] 10'0000000000 - assign $0\main_sdphy_datar_datar_run[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset[0:0] 1'0 - assign $0\main_sdcore_cmd_argument_storage[31:0] 0 - assign $0\main_sdcore_cmd_argument_re[0:0] 1'0 - assign $0\main_sdcore_cmd_command_storage[31:0] 0 - assign $0\main_sdcore_cmd_command_re[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdcore_block_length_storage[9:0] 10'0000000000 - assign $0\main_sdcore_block_length_re[0:0] 1'0 - assign $0\main_sdcore_block_count_storage[31:0] 0 - assign $0\main_sdcore_block_count_re[0:0] 1'0 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_val[7:0] 8'00000000 - assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 - assign $0\main_sdcore_cmd_count[2:0] 3'000 - assign $0\main_sdcore_cmd_done[0:0] 1'0 - assign $0\main_sdcore_cmd_error[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout[0:0] 1'0 - assign $0\main_sdcore_data_count[31:0] 0 - assign $0\main_sdcore_data_done[0:0] 1'0 - assign $0\main_sdcore_data_error[0:0] 1'0 - assign $0\main_sdcore_data_timeout[0:0] 1'0 - assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 - assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 - assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 - assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_length_storage[31:0] 0 - assign $0\main_sdmem2block_dma_length_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_enable_storage[0:0] 1'0 - assign $0\main_sdmem2block_dma_enable_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 - assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset[31:0] 0 - assign $0\main_sdmem2block_converter_mux[2:0] 3'000 - assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 - assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 - assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 - assign $0\builder_converter0_state[0:0] 1'0 - assign $0\builder_converter1_state[0:0] 1'0 - assign $0\builder_converter2_state[0:0] 1'0 - assign $0\builder_refresher_state[1:0] 2'00 - assign $0\builder_bankmachine0_state[2:0] 3'000 - assign $0\builder_bankmachine1_state[2:0] 3'000 - assign $0\builder_bankmachine2_state[2:0] 3'000 - assign $0\builder_bankmachine3_state[2:0] 3'000 - assign $0\builder_multiplexer_state[2:0] 3'000 - assign $0\builder_new_master_wdata_ready[0:0] 1'0 - assign $0\builder_new_master_rdata_valid0[0:0] 1'0 - assign $0\builder_new_master_rdata_valid1[0:0] 1'0 - assign $0\builder_new_master_rdata_valid2[0:0] 1'0 - assign $0\builder_new_master_rdata_valid3[0:0] 1'0 - assign $0\builder_converter_state[0:0] 1'0 - assign $0\builder_spimaster0_state[1:0] 2'00 - assign $0\builder_spimaster1_state[1:0] 2'00 - assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 - assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 - assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 - assign $0\builder_sdphy_fsm_state[2:0] 3'000 - assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 - assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 - assign $0\builder_sdcore_fsm_state[2:0] 3'000 - assign $0\builder_sdblock2memdma_state[1:0] 2'00 - assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - assign $0\builder_libresocsim_we[0:0] 1'0 - assign $0\builder_grant[2:0] 3'000 - assign $0\builder_slave_sel_r[12:0] 13'0000000000000 - assign $0\builder_count[19:0] 20'11110100001001000000 - assign $0\builder_state[1:0] 2'00 + attribute \src "ls180.v:5341.6-5341.15" + case 1'1 + assign $0\libresocsim_reset_storage[0:0] 1'0 + assign $0\libresocsim_reset_re[0:0] 1'0 + assign $0\libresocsim_scratch_storage[31:0] 305419896 + assign $0\libresocsim_scratch_re[0:0] 1'0 + assign $0\libresocsim_bus_errors[31:0] 0 + assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1 + assign $0\libresocsim_converter0_counter[0:0] 1'0 + assign $0\libresocsim_converter1_counter[0:0] 1'0 + assign $0\libresocsim_converter2_counter[0:0] 1'0 + assign $0\libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\libresocsim_load_storage[31:0] 0 + assign $0\libresocsim_load_re[0:0] 1'0 + assign $0\libresocsim_reload_storage[31:0] 0 + assign $0\libresocsim_reload_re[0:0] 1'0 + assign $0\libresocsim_en_storage[0:0] 1'0 + assign $0\libresocsim_en_re[0:0] 1'0 + assign $0\libresocsim_update_value_storage[0:0] 1'0 + assign $0\libresocsim_update_value_re[0:0] 1'0 + assign $0\libresocsim_value_status[31:0] 0 + assign $0\libresocsim_zero_pending[0:0] 1'0 + assign $0\libresocsim_zero_old_trigger[0:0] 1'0 + assign $0\libresocsim_eventmanager_storage[0:0] 1'0 + assign $0\libresocsim_eventmanager_re[0:0] 1'0 + assign $0\libresocsim_value[31:0] 0 + assign $0\ram_bus_ram_bus_ack[0:0] 1'0 + assign $0\dfi_p0_rddata_valid[0:0] 1'0 + assign $0\rddata_en[2:0] 3'000 + assign $0\sdram_storage[3:0] 4'0001 + assign $0\sdram_re[0:0] 1'0 + assign $0\sdram_command_storage[5:0] 6'000000 + assign $0\sdram_command_re[0:0] 1'0 + assign $0\sdram_address_re[0:0] 1'0 + assign $0\sdram_baddress_re[0:0] 1'0 + assign $0\sdram_wrdata_re[0:0] 1'0 + assign $0\sdram_status[15:0] 16'0000000000000000 + assign $0\sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $0\sdram_dfi_p0_bank[1:0] 2'00 + assign $0\sdram_dfi_p0_cas_n[0:0] 1'1 + assign $0\sdram_dfi_p0_cs_n[0:0] 1'1 + assign $0\sdram_dfi_p0_ras_n[0:0] 1'1 + assign $0\sdram_dfi_p0_we_n[0:0] 1'1 + assign $0\sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $0\sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $0\sdram_timer_count1[9:0] 10'1100001101 + assign $0\sdram_postponer_req_o[0:0] 1'0 + assign $0\sdram_postponer_count[0:0] 1'0 + assign $0\sdram_sequencer_done1[0:0] 1'0 + assign $0\sdram_sequencer_counter[3:0] 4'0000 + assign $0\sdram_sequencer_count[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $0\sdram_bankmachine0_row[12:0] 13'0000000000000 + assign $0\sdram_bankmachine0_row_opened[0:0] 1'0 + assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine0_twtpcon_count[2:0] 3'000 + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $0\sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $0\sdram_bankmachine1_row_opened[0:0] 1'0 + assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + assign $0\sdram_bankmachine2_row[12:0] 13'0000000000000 + assign $0\sdram_bankmachine2_row_opened[0:0] 1'0 + assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $0\sdram_bankmachine3_row[12:0] 13'0000000000000 + assign $0\sdram_bankmachine3_row_opened[0:0] 1'0 + assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine3_twtpcon_count[2:0] 3'000 + assign $0\sdram_choose_cmd_grant[1:0] 2'00 + assign $0\sdram_choose_req_grant[1:0] 2'00 + assign $0\sdram_tccdcon_ready[0:0] 1'0 + assign $0\sdram_tccdcon_count[0:0] 1'0 + assign $0\sdram_twtrcon_ready[0:0] 1'0 + assign $0\sdram_twtrcon_count[2:0] 3'000 + assign $0\sdram_time0[4:0] 5'00000 + assign $0\sdram_time1[3:0] 4'0000 + assign $0\converter_counter[0:0] 1'0 + assign $0\cmd_consumed[0:0] 1'0 + assign $0\wdata_consumed[0:0] 1'0 + assign $0\uart_phy_storage[31:0] 9895604 + assign $0\uart_phy_re[0:0] 1'0 + assign $0\uart_phy_sink_ready[0:0] 1'0 + assign $0\uart_phy_uart_clk_txen[0:0] 1'0 + assign $0\uart_phy_tx_busy[0:0] 1'0 + assign $0\uart_phy_source_valid[0:0] 1'0 + assign $0\uart_phy_uart_clk_rxen[0:0] 1'0 + assign $0\uart_phy_rx_r[0:0] 1'0 + assign $0\uart_phy_rx_busy[0:0] 1'0 + assign $0\tx_pending[0:0] 1'0 + assign $0\tx_old_trigger[0:0] 1'0 + assign $0\rx_pending[0:0] 1'0 + assign $0\rx_old_trigger[0:0] 1'0 + assign $0\eventmanager_storage[1:0] 2'00 + assign $0\eventmanager_re[0:0] 1'0 + assign $0\tx_fifo_readable[0:0] 1'0 + assign $0\tx_fifo_level0[4:0] 5'00000 + assign $0\tx_fifo_produce[3:0] 4'0000 + assign $0\tx_fifo_consume[3:0] 4'0000 + assign $0\rx_fifo_readable[0:0] 1'0 + assign $0\rx_fifo_level0[4:0] 5'00000 + assign $0\rx_fifo_produce[3:0] 4'0000 + assign $0\rx_fifo_consume[3:0] 4'0000 + assign $0\gpio0_oe_storage[7:0] 8'00000000 + assign $0\gpio0_oe_re[0:0] 1'0 + assign $0\gpio0_out_storage[7:0] 8'00000000 + assign $0\gpio0_out_re[0:0] 1'0 + assign $0\gpio1_oe_storage[7:0] 8'00000000 + assign $0\gpio1_oe_re[0:0] 1'0 + assign $0\gpio1_out_storage[7:0] 8'00000000 + assign $0\gpio1_out_re[0:0] 1'0 + assign $0\dummy[35:0] 36'000000000000000000000000000000000000 + assign $0\i2c_storage[2:0] 3'000 + assign $0\i2c_re[0:0] 1'0 + assign $0\subfragments_converter0_state[0:0] 1'0 + assign $0\subfragments_converter1_state[0:0] 1'0 + assign $0\subfragments_converter2_state[0:0] 1'0 + assign $0\subfragments_refresher_state[1:0] 2'00 + assign $0\subfragments_bankmachine0_state[2:0] 3'000 + assign $0\subfragments_bankmachine1_state[2:0] 3'000 + assign $0\subfragments_bankmachine2_state[2:0] 3'000 + assign $0\subfragments_bankmachine3_state[2:0] 3'000 + assign $0\subfragments_multiplexer_state[2:0] 3'000 + assign $0\subfragments_new_master_wdata_ready[0:0] 1'0 + assign $0\subfragments_new_master_rdata_valid0[0:0] 1'0 + assign $0\subfragments_new_master_rdata_valid1[0:0] 1'0 + assign $0\subfragments_new_master_rdata_valid2[0:0] 1'0 + assign $0\subfragments_new_master_rdata_valid3[0:0] 1'0 + assign $0\subfragments_state[0:0] 1'0 + assign $0\libresocsim_libresocsim_we[0:0] 1'0 + assign $0\libresocsim_grant[1:0] 2'00 + assign $0\libresocsim_slave_sel_r[5:0] 6'000000 + assign $0\libresocsim_count[19:0] 20'11110100001001000000 + assign $0\libresocsim_state[1:0] 2'00 case end sync posedge \sys_clk_1 - update \spisdcard_clk $0\spisdcard_clk[0:0] - update \spisdcard_mosi $0\spisdcard_mosi[0:0] - update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] - update \pwm $0\pwm[1:0] - update \spimaster_clk $0\spimaster_clk[0:0] - update \spimaster_mosi $0\spimaster_mosi[0:0] - update \spimaster_cs_n $0\spimaster_cs_n[0:0] - update \uart_tx $0\uart_tx[0:0] - update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] - update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] - update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] - update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] - update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] - update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] - update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] - update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] - update \main_libresocsim_reload_storage $0\main_libresocsim_reload_storage[31:0] - update \main_libresocsim_reload_re $0\main_libresocsim_reload_re[0:0] - update \main_libresocsim_en_storage $0\main_libresocsim_en_storage[0:0] - update \main_libresocsim_en_re $0\main_libresocsim_en_re[0:0] - update \main_libresocsim_update_value_storage $0\main_libresocsim_update_value_storage[0:0] - update \main_libresocsim_update_value_re $0\main_libresocsim_update_value_re[0:0] - update \main_libresocsim_value_status $0\main_libresocsim_value_status[31:0] - update \main_libresocsim_zero_pending $0\main_libresocsim_zero_pending[0:0] - update \main_libresocsim_zero_old_trigger $0\main_libresocsim_zero_old_trigger[0:0] - update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] - update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] - update \main_libresocsim_value $0\main_libresocsim_value[31:0] - update \main_interface0_ram_bus_ack $0\main_interface0_ram_bus_ack[0:0] - update \main_interface1_ram_bus_ack $0\main_interface1_ram_bus_ack[0:0] - update \main_interface2_ram_bus_ack $0\main_interface2_ram_bus_ack[0:0] - update \main_interface3_ram_bus_ack $0\main_interface3_ram_bus_ack[0:0] - update \main_converter0_counter $0\main_converter0_counter[0:0] - update \main_converter0_dat_r $0\main_converter0_dat_r[63:0] - update \main_converter1_counter $0\main_converter1_counter[0:0] - update \main_converter1_dat_r $0\main_converter1_dat_r[63:0] - update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] - update \main_rddata_en $0\main_rddata_en[2:0] - update \main_sdram_storage $0\main_sdram_storage[3:0] - update \main_sdram_re $0\main_sdram_re[0:0] - update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] - update \main_sdram_command_re $0\main_sdram_command_re[0:0] - update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] - update \main_sdram_address_re $0\main_sdram_address_re[0:0] - update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] - update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] - update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] - update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] - update \main_sdram_status $0\main_sdram_status[15:0] - update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] - update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] - update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] - update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] - update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] - update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] - update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] - update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] - update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] - update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] - update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] - update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] - update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] - update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] - update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] - update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] - update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] - update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] - update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] - update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] - update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] - update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] - update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] - update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] - update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] - update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] - update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] - update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] - update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] - update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] - update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] - update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] - update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] - update \main_sdram_time0 $0\main_sdram_time0[4:0] - update \main_sdram_time1 $0\main_sdram_time1[3:0] - update \main_socbushandler_counter $0\main_socbushandler_counter[0:0] - update \main_socbushandler_dat_r $0\main_socbushandler_dat_r[63:0] - update \main_converter_counter $0\main_converter_counter[0:0] - update \main_converter_dat_r $0\main_converter_dat_r[31:0] - update \main_cmd_consumed $0\main_cmd_consumed[0:0] - update \main_wdata_consumed $0\main_wdata_consumed[0:0] - update \main_uart_phy_storage $0\main_uart_phy_storage[31:0] - update \main_uart_phy_re $0\main_uart_phy_re[0:0] - update \main_uart_phy_sink_ready $0\main_uart_phy_sink_ready[0:0] - update \main_uart_phy_uart_clk_txen $0\main_uart_phy_uart_clk_txen[0:0] - update \main_uart_phy_phase_accumulator_tx $0\main_uart_phy_phase_accumulator_tx[31:0] - update \main_uart_phy_tx_reg $0\main_uart_phy_tx_reg[7:0] - update \main_uart_phy_tx_bitcount $0\main_uart_phy_tx_bitcount[3:0] - update \main_uart_phy_tx_busy $0\main_uart_phy_tx_busy[0:0] - update \main_uart_phy_source_valid $0\main_uart_phy_source_valid[0:0] - update \main_uart_phy_source_payload_data $0\main_uart_phy_source_payload_data[7:0] - update \main_uart_phy_uart_clk_rxen $0\main_uart_phy_uart_clk_rxen[0:0] - update \main_uart_phy_phase_accumulator_rx $0\main_uart_phy_phase_accumulator_rx[31:0] - update \main_uart_phy_rx_r $0\main_uart_phy_rx_r[0:0] - update \main_uart_phy_rx_reg $0\main_uart_phy_rx_reg[7:0] - update \main_uart_phy_rx_bitcount $0\main_uart_phy_rx_bitcount[3:0] - update \main_uart_phy_rx_busy $0\main_uart_phy_rx_busy[0:0] - update \main_uart_tx_pending $0\main_uart_tx_pending[0:0] - update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0] - update \main_uart_rx_pending $0\main_uart_rx_pending[0:0] - update \main_uart_rx_old_trigger $0\main_uart_rx_old_trigger[0:0] - update \main_uart_eventmanager_storage $0\main_uart_eventmanager_storage[1:0] - update \main_uart_eventmanager_re $0\main_uart_eventmanager_re[0:0] - update \main_uart_tx_fifo_readable $0\main_uart_tx_fifo_readable[0:0] - update \main_uart_tx_fifo_level0 $0\main_uart_tx_fifo_level0[4:0] - update \main_uart_tx_fifo_produce $0\main_uart_tx_fifo_produce[3:0] - update \main_uart_tx_fifo_consume $0\main_uart_tx_fifo_consume[3:0] - update \main_uart_rx_fifo_readable $0\main_uart_rx_fifo_readable[0:0] - update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] - update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] - update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] - update \main_gpiotristateasic1_oe_storage $0\main_gpiotristateasic1_oe_storage[15:0] - update \main_gpiotristateasic1_oe_re $0\main_gpiotristateasic1_oe_re[0:0] - update \main_gpiotristateasic1_out_storage $0\main_gpiotristateasic1_out_storage[15:0] - update \main_gpiotristateasic1_out_re $0\main_gpiotristateasic1_out_re[0:0] - update \main_spimaster5_miso $0\main_spimaster5_miso[7:0] - update \main_spimaster11_storage $0\main_spimaster11_storage[15:0] - update \main_spimaster12_re $0\main_spimaster12_re[0:0] - update \main_spimaster16_storage $0\main_spimaster16_storage[7:0] - update \main_spimaster17_re $0\main_spimaster17_re[0:0] - update \main_spimaster21_storage $0\main_spimaster21_storage[0:0] - update \main_spimaster22_re $0\main_spimaster22_re[0:0] - update \main_spimaster23_storage $0\main_spimaster23_storage[0:0] - update \main_spimaster24_re $0\main_spimaster24_re[0:0] - update \main_spimaster27_count $0\main_spimaster27_count[2:0] - update \main_spimaster30_clk_divider $0\main_spimaster30_clk_divider[15:0] - update \main_spimaster33_mosi_data $0\main_spimaster33_mosi_data[7:0] - update \main_spimaster34_mosi_sel $0\main_spimaster34_mosi_sel[2:0] - update \main_spimaster35_miso_data $0\main_spimaster35_miso_data[7:0] - update \main_spisdcard_miso $0\main_spisdcard_miso[7:0] - update \main_spisdcard_control_storage $0\main_spisdcard_control_storage[15:0] - update \main_spisdcard_control_re $0\main_spisdcard_control_re[0:0] - update \main_spisdcard_mosi_storage $0\main_spisdcard_mosi_storage[7:0] - update \main_spisdcard_mosi_re $0\main_spisdcard_mosi_re[0:0] - update \main_spisdcard_cs_storage $0\main_spisdcard_cs_storage[0:0] - update \main_spisdcard_cs_re $0\main_spisdcard_cs_re[0:0] - update \main_spisdcard_loopback_storage $0\main_spisdcard_loopback_storage[0:0] - update \main_spisdcard_loopback_re $0\main_spisdcard_loopback_re[0:0] - update \main_spisdcard_count $0\main_spisdcard_count[2:0] - update \main_spisdcard_clk_divider1 $0\main_spisdcard_clk_divider1[15:0] - update \main_spisdcard_mosi_data $0\main_spisdcard_mosi_data[7:0] - update \main_spisdcard_mosi_sel $0\main_spisdcard_mosi_sel[2:0] - update \main_spisdcard_miso_data $0\main_spisdcard_miso_data[7:0] - update \main_spimaster1_storage $0\main_spimaster1_storage[15:0] - update \main_spimaster1_re $0\main_spimaster1_re[0:0] - update \main_dummy $0\main_dummy[23:0] - update \main_pwm0_counter $0\main_pwm0_counter[31:0] - update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] - update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] - update \main_pwm0_width_storage $0\main_pwm0_width_storage[31:0] - update \main_pwm0_width_re $0\main_pwm0_width_re[0:0] - update \main_pwm0_period_storage $0\main_pwm0_period_storage[31:0] - update \main_pwm0_period_re $0\main_pwm0_period_re[0:0] - update \main_pwm1_counter $0\main_pwm1_counter[31:0] - update \main_pwm1_enable_storage $0\main_pwm1_enable_storage[0:0] - update \main_pwm1_enable_re $0\main_pwm1_enable_re[0:0] - update \main_pwm1_width_storage $0\main_pwm1_width_storage[31:0] - update \main_pwm1_width_re $0\main_pwm1_width_re[0:0] - update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0] - update \main_pwm1_period_re $0\main_pwm1_period_re[0:0] - update \main_i2c_storage $0\main_i2c_storage[2:0] - update \main_i2c_re $0\main_i2c_re[0:0] - update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0] - update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0] - update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0] - update \main_sdphy_clocker_clks $0\main_sdphy_clocker_clks[8:0] - update \main_sdphy_clocker_clk_d $0\main_sdphy_clocker_clk_d[0:0] - update \main_sdphy_init_count $0\main_sdphy_init_count[7:0] - update \main_sdphy_cmdw_count $0\main_sdphy_cmdw_count[7:0] - update \main_sdphy_cmdr_timeout $0\main_sdphy_cmdr_timeout[31:0] - update \main_sdphy_cmdr_count $0\main_sdphy_cmdr_count[7:0] - update \main_sdphy_cmdr_cmdr_run $0\main_sdphy_cmdr_cmdr_run[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_first $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_last $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_payload_data $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - update \main_sdphy_cmdr_cmdr_converter_demux $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - update \main_sdphy_cmdr_cmdr_converter_strobe_all $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_valid $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_first $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_last $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_payload_data $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - update \main_sdphy_cmdr_cmdr_reset $0\main_sdphy_cmdr_cmdr_reset[0:0] - update \main_sdphy_dataw_count $0\main_sdphy_dataw_count[7:0] - update \main_sdphy_dataw_crcr_run $0\main_sdphy_dataw_crcr_run[0:0] - update \main_sdphy_dataw_crcr_converter_source_first $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - update \main_sdphy_dataw_crcr_converter_source_last $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - update \main_sdphy_dataw_crcr_converter_source_payload_data $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - update \main_sdphy_dataw_crcr_converter_demux $0\main_sdphy_dataw_crcr_converter_demux[2:0] - update \main_sdphy_dataw_crcr_converter_strobe_all $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - update \main_sdphy_dataw_crcr_buf_source_valid $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - update \main_sdphy_dataw_crcr_buf_source_first $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - update \main_sdphy_dataw_crcr_buf_source_last $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - update \main_sdphy_dataw_crcr_buf_source_payload_data $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - update \main_sdphy_dataw_crcr_reset $0\main_sdphy_dataw_crcr_reset[0:0] - update \main_sdphy_datar_timeout $0\main_sdphy_datar_timeout[31:0] - update \main_sdphy_datar_count $0\main_sdphy_datar_count[9:0] - update \main_sdphy_datar_datar_run $0\main_sdphy_datar_datar_run[0:0] - update \main_sdphy_datar_datar_converter_source_first $0\main_sdphy_datar_datar_converter_source_first[0:0] - update \main_sdphy_datar_datar_converter_source_last $0\main_sdphy_datar_datar_converter_source_last[0:0] - update \main_sdphy_datar_datar_converter_source_payload_data $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - update \main_sdphy_datar_datar_converter_demux $0\main_sdphy_datar_datar_converter_demux[0:0] - update \main_sdphy_datar_datar_converter_strobe_all $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - update \main_sdphy_datar_datar_buf_source_valid $0\main_sdphy_datar_datar_buf_source_valid[0:0] - update \main_sdphy_datar_datar_buf_source_first $0\main_sdphy_datar_datar_buf_source_first[0:0] - update \main_sdphy_datar_datar_buf_source_last $0\main_sdphy_datar_datar_buf_source_last[0:0] - update \main_sdphy_datar_datar_buf_source_payload_data $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - update \main_sdphy_datar_datar_reset $0\main_sdphy_datar_datar_reset[0:0] - update \main_sdcore_cmd_argument_storage $0\main_sdcore_cmd_argument_storage[31:0] - update \main_sdcore_cmd_argument_re $0\main_sdcore_cmd_argument_re[0:0] - update \main_sdcore_cmd_command_storage $0\main_sdcore_cmd_command_storage[31:0] - update \main_sdcore_cmd_command_re $0\main_sdcore_cmd_command_re[0:0] - update \main_sdcore_cmd_response_status $0\main_sdcore_cmd_response_status[127:0] - update \main_sdcore_block_length_storage $0\main_sdcore_block_length_storage[9:0] - update \main_sdcore_block_length_re $0\main_sdcore_block_length_re[0:0] - update \main_sdcore_block_count_storage $0\main_sdcore_block_count_storage[31:0] - update \main_sdcore_block_count_re $0\main_sdcore_block_count_re[0:0] - update \main_sdcore_crc7_inserter_crcreg0 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - update \main_sdcore_crc16_inserter_cnt $0\main_sdcore_crc16_inserter_cnt[2:0] - update \main_sdcore_crc16_inserter_crc0_crcreg0 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc1_crcreg0 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc2_crcreg0 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc3_crcreg0 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crctmp0 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - update \main_sdcore_crc16_inserter_crctmp1 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - update \main_sdcore_crc16_inserter_crctmp2 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - update \main_sdcore_crc16_inserter_crctmp3 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - update \main_sdcore_crc16_checker_val $0\main_sdcore_crc16_checker_val[7:0] - update \main_sdcore_crc16_checker_cnt $0\main_sdcore_crc16_checker_cnt[3:0] - update \main_sdcore_crc16_checker_crc0_crcreg0 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc1_crcreg0 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc2_crcreg0 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc3_crcreg0 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - update \main_sdcore_crc16_checker_crctmp0 $0\main_sdcore_crc16_checker_crctmp0[15:0] - update \main_sdcore_crc16_checker_crctmp1 $0\main_sdcore_crc16_checker_crctmp1[15:0] - update \main_sdcore_crc16_checker_crctmp2 $0\main_sdcore_crc16_checker_crctmp2[15:0] - update \main_sdcore_crc16_checker_crctmp3 $0\main_sdcore_crc16_checker_crctmp3[15:0] - update \main_sdcore_crc16_checker_fifo0 $0\main_sdcore_crc16_checker_fifo0[15:0] - update \main_sdcore_crc16_checker_fifo1 $0\main_sdcore_crc16_checker_fifo1[15:0] - update \main_sdcore_crc16_checker_fifo2 $0\main_sdcore_crc16_checker_fifo2[15:0] - update \main_sdcore_crc16_checker_fifo3 $0\main_sdcore_crc16_checker_fifo3[15:0] - update \main_sdcore_cmd_count $0\main_sdcore_cmd_count[2:0] - update \main_sdcore_cmd_done $0\main_sdcore_cmd_done[0:0] - update \main_sdcore_cmd_error $0\main_sdcore_cmd_error[0:0] - update \main_sdcore_cmd_timeout $0\main_sdcore_cmd_timeout[0:0] - update \main_sdcore_data_count $0\main_sdcore_data_count[31:0] - update \main_sdcore_data_done $0\main_sdcore_data_done[0:0] - update \main_sdcore_data_error $0\main_sdcore_data_error[0:0] - update \main_sdcore_data_timeout $0\main_sdcore_data_timeout[0:0] - update \main_sdblock2mem_fifo_level $0\main_sdblock2mem_fifo_level[5:0] - update \main_sdblock2mem_fifo_produce $0\main_sdblock2mem_fifo_produce[4:0] - update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] - update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] - update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] - update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[63:0] - update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[2:0] - update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] - update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_length_storage $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - update \main_sdblock2mem_wishbonedmawriter_length_re $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_enable_storage $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - update \main_sdblock2mem_wishbonedmawriter_enable_re $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[63:0] - update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] - update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] - update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] - update \main_sdmem2block_dma_length_re $0\main_sdmem2block_dma_length_re[0:0] - update \main_sdmem2block_dma_enable_storage $0\main_sdmem2block_dma_enable_storage[0:0] - update \main_sdmem2block_dma_enable_re $0\main_sdmem2block_dma_enable_re[0:0] - update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] - update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] - update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] - update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[2:0] - update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] - update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] - update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] - update \builder_converter0_state $0\builder_converter0_state[0:0] - update \builder_converter1_state $0\builder_converter1_state[0:0] - update \builder_converter2_state $0\builder_converter2_state[0:0] - update \builder_refresher_state $0\builder_refresher_state[1:0] - update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] - update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] - update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] - update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] - update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] - update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] - update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] - update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] - update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] - update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] - update \builder_converter_state $0\builder_converter_state[0:0] - update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] - update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] - update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] - update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] - update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] - update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] - update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] - update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] - update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] - update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] - update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] - update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] - update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] - update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] - update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] - update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] - update \builder_grant $0\builder_grant[2:0] - update \builder_slave_sel_r $0\builder_slave_sel_r[12:0] - update \builder_count $0\builder_count[19:0] - update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] - update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] - update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] - update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] - update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] - update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] - update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] - update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] - update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] - update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] - update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] - update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] - update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] - update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0] - update \builder_interface14_bank_bus_dat_r $0\builder_interface14_bank_bus_dat_r[7:0] - update \builder_state $0\builder_state[1:0] - update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] - update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] - update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[0:0] - update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[0:0] - update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[0:0] - update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[0:0] - update \builder_multiregimpl3_regs0 $0\builder_multiregimpl3_regs0[0:0] - update \builder_multiregimpl3_regs1 $0\builder_multiregimpl3_regs1[0:0] - update \builder_multiregimpl4_regs0 $0\builder_multiregimpl4_regs0[0:0] - update \builder_multiregimpl4_regs1 $0\builder_multiregimpl4_regs1[0:0] - update \builder_multiregimpl5_regs0 $0\builder_multiregimpl5_regs0[0:0] - update \builder_multiregimpl5_regs1 $0\builder_multiregimpl5_regs1[0:0] - update \builder_multiregimpl6_regs0 $0\builder_multiregimpl6_regs0[0:0] - update \builder_multiregimpl6_regs1 $0\builder_multiregimpl6_regs1[0:0] - update \builder_multiregimpl7_regs0 $0\builder_multiregimpl7_regs0[0:0] - update \builder_multiregimpl7_regs1 $0\builder_multiregimpl7_regs1[0:0] - update \builder_multiregimpl8_regs0 $0\builder_multiregimpl8_regs0[0:0] - update \builder_multiregimpl8_regs1 $0\builder_multiregimpl8_regs1[0:0] - update \builder_multiregimpl9_regs0 $0\builder_multiregimpl9_regs0[0:0] - update \builder_multiregimpl9_regs1 $0\builder_multiregimpl9_regs1[0:0] - update \builder_multiregimpl10_regs0 $0\builder_multiregimpl10_regs0[0:0] - update \builder_multiregimpl10_regs1 $0\builder_multiregimpl10_regs1[0:0] - update \builder_multiregimpl11_regs0 $0\builder_multiregimpl11_regs0[0:0] - update \builder_multiregimpl11_regs1 $0\builder_multiregimpl11_regs1[0:0] - update \builder_multiregimpl12_regs0 $0\builder_multiregimpl12_regs0[0:0] - update \builder_multiregimpl12_regs1 $0\builder_multiregimpl12_regs1[0:0] - update \builder_multiregimpl13_regs0 $0\builder_multiregimpl13_regs0[0:0] - update \builder_multiregimpl13_regs1 $0\builder_multiregimpl13_regs1[0:0] - update \builder_multiregimpl14_regs0 $0\builder_multiregimpl14_regs0[0:0] - update \builder_multiregimpl14_regs1 $0\builder_multiregimpl14_regs1[0:0] - update \builder_multiregimpl15_regs0 $0\builder_multiregimpl15_regs0[0:0] - update \builder_multiregimpl15_regs1 $0\builder_multiregimpl15_regs1[0:0] - update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] - update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] + update \libresocsim_reset_storage $0\libresocsim_reset_storage[0:0] + update \libresocsim_reset_re $0\libresocsim_reset_re[0:0] + update \libresocsim_scratch_storage $0\libresocsim_scratch_storage[31:0] + update \libresocsim_scratch_re $0\libresocsim_scratch_re[0:0] + update \libresocsim_bus_errors $0\libresocsim_bus_errors[31:0] + update \libresocsim_libresoc_constraintmanager_uart_tx $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] + update \libresocsim_converter0_counter $0\libresocsim_converter0_counter[0:0] + update \libresocsim_converter0_dat_r $0\libresocsim_converter0_dat_r[63:0] + update \libresocsim_converter1_counter $0\libresocsim_converter1_counter[0:0] + update \libresocsim_converter1_dat_r $0\libresocsim_converter1_dat_r[63:0] + update \libresocsim_converter2_counter $0\libresocsim_converter2_counter[0:0] + update \libresocsim_converter2_dat_r $0\libresocsim_converter2_dat_r[63:0] + update \libresocsim_ram_bus_ack $0\libresocsim_ram_bus_ack[0:0] + update \libresocsim_load_storage $0\libresocsim_load_storage[31:0] + update \libresocsim_load_re $0\libresocsim_load_re[0:0] + update \libresocsim_reload_storage $0\libresocsim_reload_storage[31:0] + update \libresocsim_reload_re $0\libresocsim_reload_re[0:0] + update \libresocsim_en_storage $0\libresocsim_en_storage[0:0] + update \libresocsim_en_re $0\libresocsim_en_re[0:0] + update \libresocsim_update_value_storage $0\libresocsim_update_value_storage[0:0] + update \libresocsim_update_value_re $0\libresocsim_update_value_re[0:0] + update \libresocsim_value_status $0\libresocsim_value_status[31:0] + update \libresocsim_zero_pending $0\libresocsim_zero_pending[0:0] + update \libresocsim_zero_old_trigger $0\libresocsim_zero_old_trigger[0:0] + update \libresocsim_eventmanager_storage $0\libresocsim_eventmanager_storage[0:0] + update \libresocsim_eventmanager_re $0\libresocsim_eventmanager_re[0:0] + update \libresocsim_value $0\libresocsim_value[31:0] + update \ram_bus_ram_bus_ack $0\ram_bus_ram_bus_ack[0:0] + update \dfi_p0_rddata_valid $0\dfi_p0_rddata_valid[0:0] + update \rddata_en $0\rddata_en[2:0] + update \sdram_storage $0\sdram_storage[3:0] + update \sdram_re $0\sdram_re[0:0] + update \sdram_command_storage $0\sdram_command_storage[5:0] + update \sdram_command_re $0\sdram_command_re[0:0] + update \sdram_address_storage $0\sdram_address_storage[12:0] + update \sdram_address_re $0\sdram_address_re[0:0] + update \sdram_baddress_storage $0\sdram_baddress_storage[1:0] + update \sdram_baddress_re $0\sdram_baddress_re[0:0] + update \sdram_wrdata_storage $0\sdram_wrdata_storage[15:0] + update \sdram_wrdata_re $0\sdram_wrdata_re[0:0] + update \sdram_status $0\sdram_status[15:0] + update \sdram_dfi_p0_address $0\sdram_dfi_p0_address[12:0] + update \sdram_dfi_p0_bank $0\sdram_dfi_p0_bank[1:0] + update \sdram_dfi_p0_cas_n $0\sdram_dfi_p0_cas_n[0:0] + update \sdram_dfi_p0_cs_n $0\sdram_dfi_p0_cs_n[0:0] + update \sdram_dfi_p0_ras_n $0\sdram_dfi_p0_ras_n[0:0] + update \sdram_dfi_p0_we_n $0\sdram_dfi_p0_we_n[0:0] + update \sdram_dfi_p0_wrdata_en $0\sdram_dfi_p0_wrdata_en[0:0] + update \sdram_dfi_p0_rddata_en $0\sdram_dfi_p0_rddata_en[0:0] + update \sdram_cmd_payload_a $0\sdram_cmd_payload_a[12:0] + update \sdram_cmd_payload_ba $0\sdram_cmd_payload_ba[1:0] + update \sdram_cmd_payload_cas $0\sdram_cmd_payload_cas[0:0] + update \sdram_cmd_payload_ras $0\sdram_cmd_payload_ras[0:0] + update \sdram_cmd_payload_we $0\sdram_cmd_payload_we[0:0] + update \sdram_timer_count1 $0\sdram_timer_count1[9:0] + update \sdram_postponer_req_o $0\sdram_postponer_req_o[0:0] + update \sdram_postponer_count $0\sdram_postponer_count[0:0] + update \sdram_sequencer_done1 $0\sdram_sequencer_done1[0:0] + update \sdram_sequencer_counter $0\sdram_sequencer_counter[3:0] + update \sdram_sequencer_count $0\sdram_sequencer_count[0:0] + update \sdram_bankmachine0_cmd_buffer_lookahead_level $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \sdram_bankmachine0_cmd_buffer_lookahead_produce $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \sdram_bankmachine0_cmd_buffer_lookahead_consume $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \sdram_bankmachine0_cmd_buffer_source_valid $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \sdram_bankmachine0_cmd_buffer_source_first $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] + update \sdram_bankmachine0_cmd_buffer_source_last $0\sdram_bankmachine0_cmd_buffer_source_last[0:0] + update \sdram_bankmachine0_cmd_buffer_source_payload_we $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + update \sdram_bankmachine0_cmd_buffer_source_payload_addr $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + update \sdram_bankmachine0_row $0\sdram_bankmachine0_row[12:0] + update \sdram_bankmachine0_row_opened $0\sdram_bankmachine0_row_opened[0:0] + update \sdram_bankmachine0_twtpcon_ready $0\sdram_bankmachine0_twtpcon_ready[0:0] + update \sdram_bankmachine0_twtpcon_count $0\sdram_bankmachine0_twtpcon_count[2:0] + update \sdram_bankmachine1_cmd_buffer_lookahead_level $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + update \sdram_bankmachine1_cmd_buffer_lookahead_produce $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \sdram_bankmachine1_cmd_buffer_lookahead_consume $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \sdram_bankmachine1_cmd_buffer_source_valid $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \sdram_bankmachine1_cmd_buffer_source_first $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \sdram_bankmachine1_cmd_buffer_source_last $0\sdram_bankmachine1_cmd_buffer_source_last[0:0] + update \sdram_bankmachine1_cmd_buffer_source_payload_we $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + update \sdram_bankmachine1_cmd_buffer_source_payload_addr $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + update \sdram_bankmachine1_row $0\sdram_bankmachine1_row[12:0] + update \sdram_bankmachine1_row_opened $0\sdram_bankmachine1_row_opened[0:0] + update \sdram_bankmachine1_twtpcon_ready $0\sdram_bankmachine1_twtpcon_ready[0:0] + update \sdram_bankmachine1_twtpcon_count $0\sdram_bankmachine1_twtpcon_count[2:0] + update \sdram_bankmachine2_cmd_buffer_lookahead_level $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + update \sdram_bankmachine2_cmd_buffer_lookahead_produce $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + update \sdram_bankmachine2_cmd_buffer_lookahead_consume $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + update \sdram_bankmachine2_cmd_buffer_source_valid $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] + update \sdram_bankmachine2_cmd_buffer_source_first $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] + update \sdram_bankmachine2_cmd_buffer_source_last $0\sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \sdram_bankmachine2_cmd_buffer_source_payload_we $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + update \sdram_bankmachine2_cmd_buffer_source_payload_addr $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \sdram_bankmachine2_row $0\sdram_bankmachine2_row[12:0] + update \sdram_bankmachine2_row_opened $0\sdram_bankmachine2_row_opened[0:0] + update \sdram_bankmachine2_twtpcon_ready $0\sdram_bankmachine2_twtpcon_ready[0:0] + update \sdram_bankmachine2_twtpcon_count $0\sdram_bankmachine2_twtpcon_count[2:0] + update \sdram_bankmachine3_cmd_buffer_lookahead_level $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + update \sdram_bankmachine3_cmd_buffer_lookahead_produce $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \sdram_bankmachine3_cmd_buffer_lookahead_consume $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \sdram_bankmachine3_cmd_buffer_source_valid $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \sdram_bankmachine3_cmd_buffer_source_first $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \sdram_bankmachine3_cmd_buffer_source_last $0\sdram_bankmachine3_cmd_buffer_source_last[0:0] + update \sdram_bankmachine3_cmd_buffer_source_payload_we $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \sdram_bankmachine3_cmd_buffer_source_payload_addr $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + update \sdram_bankmachine3_row $0\sdram_bankmachine3_row[12:0] + update \sdram_bankmachine3_row_opened $0\sdram_bankmachine3_row_opened[0:0] + update \sdram_bankmachine3_twtpcon_ready $0\sdram_bankmachine3_twtpcon_ready[0:0] + update \sdram_bankmachine3_twtpcon_count $0\sdram_bankmachine3_twtpcon_count[2:0] + update \sdram_choose_cmd_grant $0\sdram_choose_cmd_grant[1:0] + update \sdram_choose_req_grant $0\sdram_choose_req_grant[1:0] + update \sdram_tccdcon_ready $0\sdram_tccdcon_ready[0:0] + update \sdram_tccdcon_count $0\sdram_tccdcon_count[0:0] + update \sdram_twtrcon_ready $0\sdram_twtrcon_ready[0:0] + update \sdram_twtrcon_count $0\sdram_twtrcon_count[2:0] + update \sdram_time0 $0\sdram_time0[4:0] + update \sdram_time1 $0\sdram_time1[3:0] + update \converter_counter $0\converter_counter[0:0] + update \converter_dat_r $0\converter_dat_r[31:0] + update \cmd_consumed $0\cmd_consumed[0:0] + update \wdata_consumed $0\wdata_consumed[0:0] + update \uart_phy_storage $0\uart_phy_storage[31:0] + update \uart_phy_re $0\uart_phy_re[0:0] + update \uart_phy_sink_ready $0\uart_phy_sink_ready[0:0] + update \uart_phy_uart_clk_txen $0\uart_phy_uart_clk_txen[0:0] + update \uart_phy_phase_accumulator_tx $0\uart_phy_phase_accumulator_tx[31:0] + update \uart_phy_tx_reg $0\uart_phy_tx_reg[7:0] + update \uart_phy_tx_bitcount $0\uart_phy_tx_bitcount[3:0] + update \uart_phy_tx_busy $0\uart_phy_tx_busy[0:0] + update \uart_phy_source_valid $0\uart_phy_source_valid[0:0] + update \uart_phy_source_payload_data $0\uart_phy_source_payload_data[7:0] + update \uart_phy_uart_clk_rxen $0\uart_phy_uart_clk_rxen[0:0] + update \uart_phy_phase_accumulator_rx $0\uart_phy_phase_accumulator_rx[31:0] + update \uart_phy_rx_r $0\uart_phy_rx_r[0:0] + update \uart_phy_rx_reg $0\uart_phy_rx_reg[7:0] + update \uart_phy_rx_bitcount $0\uart_phy_rx_bitcount[3:0] + update \uart_phy_rx_busy $0\uart_phy_rx_busy[0:0] + update \tx_pending $0\tx_pending[0:0] + update \tx_old_trigger $0\tx_old_trigger[0:0] + update \rx_pending $0\rx_pending[0:0] + update \rx_old_trigger $0\rx_old_trigger[0:0] + update \eventmanager_storage $0\eventmanager_storage[1:0] + update \eventmanager_re $0\eventmanager_re[0:0] + update \tx_fifo_readable $0\tx_fifo_readable[0:0] + update \tx_fifo_level0 $0\tx_fifo_level0[4:0] + update \tx_fifo_produce $0\tx_fifo_produce[3:0] + update \tx_fifo_consume $0\tx_fifo_consume[3:0] + update \rx_fifo_readable $0\rx_fifo_readable[0:0] + update \rx_fifo_level0 $0\rx_fifo_level0[4:0] + update \rx_fifo_produce $0\rx_fifo_produce[3:0] + update \rx_fifo_consume $0\rx_fifo_consume[3:0] + update \gpio0_oe_storage $0\gpio0_oe_storage[7:0] + update \gpio0_oe_re $0\gpio0_oe_re[0:0] + update \gpio0_out_storage $0\gpio0_out_storage[7:0] + update \gpio0_out_re $0\gpio0_out_re[0:0] + update \gpio1_oe_storage $0\gpio1_oe_storage[7:0] + update \gpio1_oe_re $0\gpio1_oe_re[0:0] + update \gpio1_out_storage $0\gpio1_out_storage[7:0] + update \gpio1_out_re $0\gpio1_out_re[0:0] + update \dummy $0\dummy[35:0] + update \i2c_storage $0\i2c_storage[2:0] + update \i2c_re $0\i2c_re[0:0] + update \subfragments_converter0_state $0\subfragments_converter0_state[0:0] + update \subfragments_converter1_state $0\subfragments_converter1_state[0:0] + update \subfragments_converter2_state $0\subfragments_converter2_state[0:0] + update \subfragments_refresher_state $0\subfragments_refresher_state[1:0] + update \subfragments_bankmachine0_state $0\subfragments_bankmachine0_state[2:0] + update \subfragments_bankmachine1_state $0\subfragments_bankmachine1_state[2:0] + update \subfragments_bankmachine2_state $0\subfragments_bankmachine2_state[2:0] + update \subfragments_bankmachine3_state $0\subfragments_bankmachine3_state[2:0] + update \subfragments_multiplexer_state $0\subfragments_multiplexer_state[2:0] + update \subfragments_new_master_wdata_ready $0\subfragments_new_master_wdata_ready[0:0] + update \subfragments_new_master_rdata_valid0 $0\subfragments_new_master_rdata_valid0[0:0] + update \subfragments_new_master_rdata_valid1 $0\subfragments_new_master_rdata_valid1[0:0] + update \subfragments_new_master_rdata_valid2 $0\subfragments_new_master_rdata_valid2[0:0] + update \subfragments_new_master_rdata_valid3 $0\subfragments_new_master_rdata_valid3[0:0] + update \subfragments_state $0\subfragments_state[0:0] + update \libresocsim_libresocsim_adr $0\libresocsim_libresocsim_adr[13:0] + update \libresocsim_libresocsim_we $0\libresocsim_libresocsim_we[0:0] + update \libresocsim_libresocsim_dat_w $0\libresocsim_libresocsim_dat_w[7:0] + update \libresocsim_grant $0\libresocsim_grant[1:0] + update \libresocsim_slave_sel_r $0\libresocsim_slave_sel_r[5:0] + update \libresocsim_count $0\libresocsim_count[19:0] + update \libresocsim_interface0_bank_bus_dat_r $0\libresocsim_interface0_bank_bus_dat_r[7:0] + update \libresocsim_interface1_bank_bus_dat_r $0\libresocsim_interface1_bank_bus_dat_r[7:0] + update \libresocsim_interface2_bank_bus_dat_r $0\libresocsim_interface2_bank_bus_dat_r[7:0] + update \libresocsim_interface3_bank_bus_dat_r $0\libresocsim_interface3_bank_bus_dat_r[7:0] + update \libresocsim_interface4_bank_bus_dat_r $0\libresocsim_interface4_bank_bus_dat_r[7:0] + update \libresocsim_interface5_bank_bus_dat_r $0\libresocsim_interface5_bank_bus_dat_r[7:0] + update \libresocsim_interface6_bank_bus_dat_r $0\libresocsim_interface6_bank_bus_dat_r[7:0] + update \libresocsim_interface7_bank_bus_dat_r $0\libresocsim_interface7_bank_bus_dat_r[7:0] + update \libresocsim_state $0\libresocsim_state[1:0] + update \regs0 $0\regs0[0:0] + update \regs1 $0\regs1[0:0] end - attribute \src "ls180.v:784.11-784.68" - process $proc$ls180.v:784$3381 + attribute \src "ls180.v:429.5-429.61" + process $proc$ls180.v:429$1712 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always + update \sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:785.5-785.64" - process $proc$ls180.v:785$3382 + attribute \src "ls180.v:444.11-444.63" + process $proc$ls180.v:444$1713 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] sync init + update \sdram_bankmachine0_cmd_buffer_lookahead_level $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:786.11-786.70" - process $proc$ls180.v:786$3383 + attribute \src "ls180.v:445.5-445.59" + process $proc$ls180.v:445$1714 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 sync always + update \sdram_bankmachine0_cmd_buffer_lookahead_replace $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:787.11-787.70" - process $proc$ls180.v:787$3384 + attribute \src "ls180.v:446.11-446.65" + process $proc$ls180.v:446$1715 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \sdram_bankmachine0_cmd_buffer_lookahead_produce $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:788.11-788.73" - process $proc$ls180.v:788$3385 + attribute \src "ls180.v:447.11-447.65" + process $proc$ls180.v:447$1716 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + update \sdram_bankmachine0_cmd_buffer_lookahead_consume $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:809.5-809.59" - process $proc$ls180.v:809$3386 + attribute \src "ls180.v:448.11-448.68" + process $proc$ls180.v:448$1717 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:811.5-811.59" - process $proc$ls180.v:811$3387 + attribute \src "ls180.v:45.5-45.37" + process $proc$ls180.v:45$1547 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + assign $1\libresocsim_reset_storage[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \libresocsim_reset_storage $1\libresocsim_reset_storage[0:0] end - attribute \src "ls180.v:812.5-812.58" - process $proc$ls180.v:812$3388 + attribute \src "ls180.v:46.5-46.32" + process $proc$ls180.v:46$1548 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + assign $1\libresocsim_reset_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + update \libresocsim_reset_re $1\libresocsim_reset_re[0:0] end - attribute \src "ls180.v:813.5-813.64" - process $proc$ls180.v:813$3389 + attribute \src "ls180.v:469.5-469.54" + process $proc$ls180.v:469$1718 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + assign $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \sdram_bankmachine0_cmd_buffer_source_valid $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:814.12-814.74" - process $proc$ls180.v:814$3390 + attribute \src "ls180.v:47.12-47.55" + process $proc$ls180.v:47$1549 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + assign $1\libresocsim_scratch_storage[31:0] 305419896 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + update \libresocsim_scratch_storage $1\libresocsim_scratch_storage[31:0] end - attribute \src "ls180.v:815.12-815.47" - process $proc$ls180.v:815$3391 + attribute \src "ls180.v:471.5-471.54" + process $proc$ls180.v:471$1719 assign { } { } - assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + assign $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] + update \sdram_bankmachine0_cmd_buffer_source_first $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:816.5-816.46" - process $proc$ls180.v:816$3392 + attribute \src "ls180.v:472.5-472.53" + process $proc$ls180.v:472$1720 assign { } { } - assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 + assign $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] + update \sdram_bankmachine0_cmd_buffer_source_last $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:818.5-818.44" - process $proc$ls180.v:818$3393 + attribute \src "ls180.v:473.5-473.59" + process $proc$ls180.v:473$1721 assign { } { } - assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 + assign $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] + update \sdram_bankmachine0_cmd_buffer_source_payload_we $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:819.5-819.45" - process $proc$ls180.v:819$3394 + attribute \src "ls180.v:474.12-474.69" + process $proc$ls180.v:474$1722 assign { } { } - assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init - update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] + update \sdram_bankmachine0_cmd_buffer_source_payload_addr $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:820.5-820.54" - process $proc$ls180.v:820$3395 + attribute \src "ls180.v:475.12-475.42" + process $proc$ls180.v:475$1723 assign { } { } - assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + assign $1\sdram_bankmachine0_row[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + update \sdram_bankmachine0_row $1\sdram_bankmachine0_row[12:0] end - attribute \src "ls180.v:822.32-822.76" - process $proc$ls180.v:822$3396 + attribute \src "ls180.v:476.5-476.41" + process $proc$ls180.v:476$1724 assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + assign $1\sdram_bankmachine0_row_opened[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + update \sdram_bankmachine0_row_opened $1\sdram_bankmachine0_row_opened[0:0] end - attribute \src "ls180.v:823.11-823.55" - process $proc$ls180.v:823$3397 + attribute \src "ls180.v:478.5-478.39" + process $proc$ls180.v:478$1725 assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + assign $1\sdram_bankmachine0_row_open[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] + update \sdram_bankmachine0_row_open $1\sdram_bankmachine0_row_open[0:0] end - attribute \src "ls180.v:825.32-825.75" - process $proc$ls180.v:825$3398 + attribute \src "ls180.v:479.5-479.40" + process $proc$ls180.v:479$1726 assign { } { } - assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 + assign $1\sdram_bankmachine0_row_close[0:0] 1'0 sync always - update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] sync init + update \sdram_bankmachine0_row_close $1\sdram_bankmachine0_row_close[0:0] end - attribute \src "ls180.v:827.32-827.76" - process $proc$ls180.v:827$3399 + attribute \src "ls180.v:48.5-48.34" + process $proc$ls180.v:48$1550 assign { } { } - assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 + assign $1\libresocsim_scratch_re[0:0] 1'0 sync always - update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] sync init + update \libresocsim_scratch_re $1\libresocsim_scratch_re[0:0] end - attribute \src "ls180.v:830.5-830.44" - process $proc$ls180.v:830$3400 + attribute \src "ls180.v:480.5-480.49" + process $proc$ls180.v:480$1727 assign { } { } - assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 + assign $1\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 sync always - update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] sync init + update \sdram_bankmachine0_row_col_n_addr_sel $1\sdram_bankmachine0_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:831.5-831.45" - process $proc$ls180.v:831$3401 + attribute \src "ls180.v:482.32-482.71" + process $proc$ls180.v:482$1728 assign { } { } - assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 + assign $1\sdram_bankmachine0_twtpcon_ready[0:0] 1'0 sync always - update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] sync init + update \sdram_bankmachine0_twtpcon_ready $1\sdram_bankmachine0_twtpcon_ready[0:0] end - attribute \src "ls180.v:832.5-832.43" - process $proc$ls180.v:832$3402 + attribute \src "ls180.v:483.11-483.50" + process $proc$ls180.v:483$1729 assign { } { } - assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 + assign $1\sdram_bankmachine0_twtpcon_count[2:0] 3'000 sync always - update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] sync init + update \sdram_bankmachine0_twtpcon_count $1\sdram_bankmachine0_twtpcon_count[2:0] end - attribute \src "ls180.v:833.5-833.48" - process $proc$ls180.v:833$3403 + attribute \src "ls180.v:485.32-485.70" + process $proc$ls180.v:485$1730 assign { } { } - assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 + assign $0\sdram_bankmachine0_trccon_ready[0:0] 1'1 sync always - update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] + update \sdram_bankmachine0_trccon_ready $0\sdram_bankmachine0_trccon_ready[0:0] sync init end - attribute \src "ls180.v:835.5-835.43" - process $proc$ls180.v:835$3404 + attribute \src "ls180.v:487.32-487.71" + process $proc$ls180.v:487$1731 assign { } { } - assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 + assign $0\sdram_bankmachine0_trascon_ready[0:0] 1'1 sync always - update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] + update \sdram_bankmachine0_trascon_ready $0\sdram_bankmachine0_trascon_ready[0:0] sync init end - attribute \src "ls180.v:838.5-838.49" - process $proc$ls180.v:838$3405 + attribute \src "ls180.v:493.5-493.46" + process $proc$ls180.v:493$1732 assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + assign $1\sdram_bankmachine1_req_wdata_ready[0:0] 1'0 sync always sync init - update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + update \sdram_bankmachine1_req_wdata_ready $1\sdram_bankmachine1_req_wdata_ready[0:0] end - attribute \src "ls180.v:839.5-839.49" - process $proc$ls180.v:839$3406 + attribute \src "ls180.v:494.5-494.46" + process $proc$ls180.v:494$1733 assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + assign $1\sdram_bankmachine1_req_rdata_valid[0:0] 1'0 sync always sync init - update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + update \sdram_bankmachine1_req_rdata_valid $1\sdram_bankmachine1_req_rdata_valid[0:0] end - attribute \src "ls180.v:840.5-840.48" - process $proc$ls180.v:840$3407 + attribute \src "ls180.v:496.5-496.42" + process $proc$ls180.v:496$1734 assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + assign $1\sdram_bankmachine1_refresh_gnt[0:0] 1'0 sync always sync init - update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + update \sdram_bankmachine1_refresh_gnt $1\sdram_bankmachine1_refresh_gnt[0:0] end - attribute \src "ls180.v:844.11-844.46" - process $proc$ls180.v:844$3408 + attribute \src "ls180.v:497.5-497.40" + process $proc$ls180.v:497$1735 assign { } { } - assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 + assign $1\sdram_bankmachine1_cmd_valid[0:0] 1'0 sync always sync init - update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] + update \sdram_bankmachine1_cmd_valid $1\sdram_bankmachine1_cmd_valid[0:0] end - attribute \src "ls180.v:846.11-846.45" - process $proc$ls180.v:846$3409 + attribute \src "ls180.v:498.5-498.40" + process $proc$ls180.v:498$1736 assign { } { } - assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 + assign $1\sdram_bankmachine1_cmd_ready[0:0] 1'0 sync always sync init - update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] + update \sdram_bankmachine1_cmd_ready $1\sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "ls180.v:848.5-848.44" - process $proc$ls180.v:848$3410 + attribute \src "ls180.v:499.12-499.52" + process $proc$ls180.v:499$1737 assign { } { } - assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 + assign $1\sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] + update \sdram_bankmachine1_cmd_payload_a $1\sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:849.5-849.45" - process $proc$ls180.v:849$3411 + attribute \src "ls180.v:501.5-501.46" + process $proc$ls180.v:501$1738 assign { } { } - assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 + assign $1\sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] + update \sdram_bankmachine1_cmd_payload_cas $1\sdram_bankmachine1_cmd_payload_cas[0:0] end - attribute \src "ls180.v:85.11-85.52" - process $proc$ls180.v:85$3136 + attribute \src "ls180.v:502.5-502.46" + process $proc$ls180.v:502$1739 assign { } { } - assign $0\main_libresocsim_libresoc_ibus_cti[2:0] 3'000 + assign $1\sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 sync always - update \main_libresocsim_libresoc_ibus_cti $0\main_libresocsim_libresoc_ibus_cti[2:0] sync init + update \sdram_bankmachine1_cmd_payload_ras $1\sdram_bankmachine1_cmd_payload_ras[0:0] end - attribute \src "ls180.v:851.5-851.48" - process $proc$ls180.v:851$3412 + attribute \src "ls180.v:503.5-503.45" + process $proc$ls180.v:503$1740 assign { } { } - assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 + assign $1\sdram_bankmachine1_cmd_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] + update \sdram_bankmachine1_cmd_payload_we $1\sdram_bankmachine1_cmd_payload_we[0:0] end - attribute \src "ls180.v:853.5-853.43" - process $proc$ls180.v:853$3413 + attribute \src "ls180.v:504.5-504.49" + process $proc$ls180.v:504$1741 assign { } { } - assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 sync always sync init - update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] + update \sdram_bankmachine1_cmd_payload_is_cmd $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:856.5-856.49" - process $proc$ls180.v:856$3414 + attribute \src "ls180.v:505.5-505.50" + process $proc$ls180.v:505$1742 assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + assign $1\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 sync always sync init - update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] + update \sdram_bankmachine1_cmd_payload_is_read $1\sdram_bankmachine1_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:857.5-857.49" - process $proc$ls180.v:857$3415 + attribute \src "ls180.v:506.5-506.51" + process $proc$ls180.v:506$1743 + assign { } { } + assign $1\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_payload_is_write $1\sdram_bankmachine1_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:507.5-507.45" + process $proc$ls180.v:507$1744 + assign { } { } + assign $1\sdram_bankmachine1_auto_precharge[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_auto_precharge $1\sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:510.5-510.62" + process $proc$ls180.v:510$1745 + assign { } { } + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:511.5-511.61" + process $proc$ls180.v:511$1746 + assign { } { } + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:526.11-526.63" + process $proc$ls180.v:526$1747 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_lookahead_level $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:527.5-527.59" + process $proc$ls180.v:527$1748 + assign { } { } + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \sdram_bankmachine1_cmd_buffer_lookahead_replace $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:528.11-528.65" + process $proc$ls180.v:528$1749 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_lookahead_produce $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:529.11-529.65" + process $proc$ls180.v:529$1750 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_lookahead_consume $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:53.12-53.42" + process $proc$ls180.v:53$1551 + assign { } { } + assign $1\libresocsim_bus_errors[31:0] 0 + sync always + sync init + update \libresocsim_bus_errors $1\libresocsim_bus_errors[31:0] + end + attribute \src "ls180.v:530.11-530.68" + process $proc$ls180.v:530$1751 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:5495.1-5505.4" + process $proc$ls180.v:5495$1434 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1435 $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447 + assign $0$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1436 $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448 + assign $0$memwr$\mem$ls180.v:5497$1_EN[31:0]$1437 $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449 + assign $0$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1438 $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450 + assign $0$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1439 $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451 + assign $0$memwr$\mem$ls180.v:5499$2_EN[31:0]$1440 $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452 + assign $0$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1441 $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453 + assign $0$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1442 $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454 + assign $0$memwr$\mem$ls180.v:5501$3_EN[31:0]$1443 $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455 + assign $0$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1444 $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456 + assign $0$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1445 $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457 + assign $0$memwr$\mem$ls180.v:5503$4_EN[31:0]$1446 $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458 + assign $0\memadr[6:0] \libresocsim_adr + attribute \src "ls180.v:5496.2-5497.55" + switch \libresocsim_we [0] + attribute \src "ls180.v:5496.6-5496.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448 { 24'000000000000000000000000 \libresocsim_dat_w [7:0] } + assign $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449 255 + case + assign $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447 7'xxxxxxx + assign $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449 0 + end + attribute \src "ls180.v:5498.2-5499.57" + switch \libresocsim_we [1] + attribute \src "ls180.v:5498.6-5498.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451 { 16'0000000000000000 \libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452 65280 + case + assign $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450 7'xxxxxxx + assign $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452 0 + end + attribute \src "ls180.v:5500.2-5501.59" + switch \libresocsim_we [2] + attribute \src "ls180.v:5500.6-5500.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454 { 8'00000000 \libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455 16711680 + case + assign $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453 7'xxxxxxx + assign $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455 0 + end + attribute \src "ls180.v:5502.2-5503.59" + switch \libresocsim_we [3] + attribute \src "ls180.v:5502.6-5502.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457 { \libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458 32'11111111000000000000000000000000 + case + assign $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456 7'xxxxxxx + assign $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458 0 + end + sync posedge \sys_clk_1 + update \memadr $0\memadr[6:0] + update $memwr$\mem$ls180.v:5497$1_ADDR $0$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1435 + update $memwr$\mem$ls180.v:5497$1_DATA $0$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1436 + update $memwr$\mem$ls180.v:5497$1_EN $0$memwr$\mem$ls180.v:5497$1_EN[31:0]$1437 + update $memwr$\mem$ls180.v:5499$2_ADDR $0$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1438 + update $memwr$\mem$ls180.v:5499$2_DATA $0$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1439 + update $memwr$\mem$ls180.v:5499$2_EN $0$memwr$\mem$ls180.v:5499$2_EN[31:0]$1440 + update $memwr$\mem$ls180.v:5501$3_ADDR $0$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1441 + update $memwr$\mem$ls180.v:5501$3_DATA $0$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1442 + update $memwr$\mem$ls180.v:5501$3_EN $0$memwr$\mem$ls180.v:5501$3_EN[31:0]$1443 + update $memwr$\mem$ls180.v:5503$4_ADDR $0$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1444 + update $memwr$\mem$ls180.v:5503$4_DATA $0$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1445 + update $memwr$\mem$ls180.v:5503$4_EN $0$memwr$\mem$ls180.v:5503$4_EN[31:0]$1446 + attribute \src "ls180.v:5497.3-5497.54" + memwr \mem $1$memwr$\mem$ls180.v:5497$1_ADDR[6:0]$1447 $1$memwr$\mem$ls180.v:5497$1_DATA[31:0]$1448 $1$memwr$\mem$ls180.v:5497$1_EN[31:0]$1449 0' + attribute \src "ls180.v:5499.3-5499.56" + memwr \mem $1$memwr$\mem$ls180.v:5499$2_ADDR[6:0]$1450 $1$memwr$\mem$ls180.v:5499$2_DATA[31:0]$1451 $1$memwr$\mem$ls180.v:5499$2_EN[31:0]$1452 1'1 + attribute \src "ls180.v:5501.3-5501.58" + memwr \mem $1$memwr$\mem$ls180.v:5501$3_ADDR[6:0]$1453 $1$memwr$\mem$ls180.v:5501$3_DATA[31:0]$1454 $1$memwr$\mem$ls180.v:5501$3_EN[31:0]$1455 2'11 + attribute \src "ls180.v:5503.3-5503.58" + memwr \mem $1$memwr$\mem$ls180.v:5503$4_ADDR[6:0]$1456 $1$memwr$\mem$ls180.v:5503$4_DATA[31:0]$1457 $1$memwr$\mem$ls180.v:5503$4_EN[31:0]$1458 3'111 + end + attribute \src "ls180.v:55.12-55.50" + process $proc$ls180.v:55$1552 + assign { } { } + assign $1\libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_libresoc_interrupt $1\libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:551.5-551.54" + process $proc$ls180.v:551$1752 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_source_valid $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:5515.1-5525.4" + process $proc$ls180.v:5515$1460 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1461 $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473 + assign $0$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1462 $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474 + assign $0$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1463 $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475 + assign $0$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1464 $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476 + assign $0$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1465 $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477 + assign $0$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1466 $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478 + assign $0$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1467 $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479 + assign $0$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1468 $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480 + assign $0$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1469 $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481 + assign $0$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1470 $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482 + assign $0$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1471 $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483 + assign $0$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1472 $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484 + assign $0\memadr_1[4:0] \ram_adr + attribute \src "ls180.v:5516.2-5517.41" + switch \ram_we [0] + attribute \src "ls180.v:5516.6-5516.15" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474 { 24'000000000000000000000000 \ram_dat_w [7:0] } + assign $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475 255 + case + assign $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473 5'xxxxx + assign $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475 0 + end + attribute \src "ls180.v:5518.2-5519.43" + switch \ram_we [1] + attribute \src "ls180.v:5518.6-5518.15" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477 { 16'0000000000000000 \ram_dat_w [15:8] 8'xxxxxxxx } + assign $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478 65280 + case + assign $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476 5'xxxxx + assign $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478 0 + end + attribute \src "ls180.v:5520.2-5521.45" + switch \ram_we [2] + attribute \src "ls180.v:5520.6-5520.15" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480 { 8'00000000 \ram_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481 16711680 + case + assign $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479 5'xxxxx + assign $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481 0 + end + attribute \src "ls180.v:5522.2-5523.45" + switch \ram_we [3] + attribute \src "ls180.v:5522.6-5522.15" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483 { \ram_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484 32'11111111000000000000000000000000 + case + assign $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482 5'xxxxx + assign $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484 0 + end + sync posedge \sys_clk_1 + update \memadr_1 $0\memadr_1[4:0] + update $memwr$\mem_1$ls180.v:5517$5_ADDR $0$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1461 + update $memwr$\mem_1$ls180.v:5517$5_DATA $0$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1462 + update $memwr$\mem_1$ls180.v:5517$5_EN $0$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1463 + update $memwr$\mem_1$ls180.v:5519$6_ADDR $0$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1464 + update $memwr$\mem_1$ls180.v:5519$6_DATA $0$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1465 + update $memwr$\mem_1$ls180.v:5519$6_EN $0$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1466 + update $memwr$\mem_1$ls180.v:5521$7_ADDR $0$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1467 + update $memwr$\mem_1$ls180.v:5521$7_DATA $0$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1468 + update $memwr$\mem_1$ls180.v:5521$7_EN $0$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1469 + update $memwr$\mem_1$ls180.v:5523$8_ADDR $0$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1470 + update $memwr$\mem_1$ls180.v:5523$8_DATA $0$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1471 + update $memwr$\mem_1$ls180.v:5523$8_EN $0$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1472 + attribute \src "ls180.v:5517.3-5517.40" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5517$5_ADDR[4:0]$1473 $1$memwr$\mem_1$ls180.v:5517$5_DATA[31:0]$1474 $1$memwr$\mem_1$ls180.v:5517$5_EN[31:0]$1475 0' + attribute \src "ls180.v:5519.3-5519.42" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5519$6_ADDR[4:0]$1476 $1$memwr$\mem_1$ls180.v:5519$6_DATA[31:0]$1477 $1$memwr$\mem_1$ls180.v:5519$6_EN[31:0]$1478 1'1 + attribute \src "ls180.v:5521.3-5521.44" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5521$7_ADDR[4:0]$1479 $1$memwr$\mem_1$ls180.v:5521$7_DATA[31:0]$1480 $1$memwr$\mem_1$ls180.v:5521$7_EN[31:0]$1481 2'11 + attribute \src "ls180.v:5523.3-5523.44" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5523$8_ADDR[4:0]$1482 $1$memwr$\mem_1$ls180.v:5523$8_DATA[31:0]$1483 $1$memwr$\mem_1$ls180.v:5523$8_EN[31:0]$1484 3'111 + end + attribute \src "ls180.v:553.5-553.54" + process $proc$ls180.v:553$1753 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_source_first $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:5535.1-5539.4" + process $proc$ls180.v:5535$1486 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1487 $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490 + assign $0$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1488 $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491 + assign $0$memwr$\storage$ls180.v:5537$9_EN[24:0]$1489 $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:5538$1493_DATA + attribute \src "ls180.v:5536.2-5537.119" + switch \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:5536.6-5536.55" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492 25'1111111111111111111111111 + case + assign $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490 3'xxx + assign $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492 25'0000000000000000000000000 + end + sync posedge \sys_clk_1 + update \memdat $0\memdat[24:0] + update $memwr$\storage$ls180.v:5537$9_ADDR $0$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1487 + update $memwr$\storage$ls180.v:5537$9_DATA $0$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1488 + update $memwr$\storage$ls180.v:5537$9_EN $0$memwr$\storage$ls180.v:5537$9_EN[24:0]$1489 + attribute \src "ls180.v:5537.3-5537.118" + memwr \storage $1$memwr$\storage$ls180.v:5537$9_ADDR[2:0]$1490 $1$memwr$\storage$ls180.v:5537$9_DATA[24:0]$1491 $1$memwr$\storage$ls180.v:5537$9_EN[24:0]$1492 0' + end + attribute \src "ls180.v:554.5-554.53" + process $proc$ls180.v:554$1754 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_source_last $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:5541.1-5542.4" + process $proc$ls180.v:5541$1494 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:5549.1-5553.4" + process $proc$ls180.v:5549$1496 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1497 $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500 + assign $0$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1498 $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501 + assign $0$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1499 $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:5552$1503_DATA + attribute \src "ls180.v:5550.2-5551.121" + switch \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:5550.6-5550.55" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502 25'1111111111111111111111111 + case + assign $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500 3'xxx + assign $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502 25'0000000000000000000000000 + end + sync posedge \sys_clk_1 + update \memdat_1 $0\memdat_1[24:0] + update $memwr$\storage_1$ls180.v:5551$10_ADDR $0$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1497 + update $memwr$\storage_1$ls180.v:5551$10_DATA $0$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1498 + update $memwr$\storage_1$ls180.v:5551$10_EN $0$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1499 + attribute \src "ls180.v:5551.3-5551.120" + memwr \storage_1 $1$memwr$\storage_1$ls180.v:5551$10_ADDR[2:0]$1500 $1$memwr$\storage_1$ls180.v:5551$10_DATA[24:0]$1501 $1$memwr$\storage_1$ls180.v:5551$10_EN[24:0]$1502 0' + end + attribute \src "ls180.v:555.5-555.59" + process $proc$ls180.v:555$1755 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_source_payload_we $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:5555.1-5556.4" + process $proc$ls180.v:5555$1504 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:556.12-556.69" + process $proc$ls180.v:556$1756 assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + assign $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init - update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] + update \sdram_bankmachine1_cmd_buffer_source_payload_addr $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:858.5-858.48" - process $proc$ls180.v:858$3416 + attribute \src "ls180.v:5563.1-5567.4" + process $proc$ls180.v:5563$1506 assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1507 $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510 + assign $0$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1508 $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511 + assign $0$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1509 $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:5566$1513_DATA + attribute \src "ls180.v:5564.2-5565.121" + switch \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:5564.6-5564.55" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512 25'1111111111111111111111111 + case + assign $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510 3'xxx + assign $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512 25'0000000000000000000000000 + end + sync posedge \sys_clk_1 + update \memdat_2 $0\memdat_2[24:0] + update $memwr$\storage_2$ls180.v:5565$11_ADDR $0$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1507 + update $memwr$\storage_2$ls180.v:5565$11_DATA $0$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1508 + update $memwr$\storage_2$ls180.v:5565$11_EN $0$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1509 + attribute \src "ls180.v:5565.3-5565.120" + memwr \storage_2 $1$memwr$\storage_2$ls180.v:5565$11_ADDR[2:0]$1510 $1$memwr$\storage_2$ls180.v:5565$11_DATA[24:0]$1511 $1$memwr$\storage_2$ls180.v:5565$11_EN[24:0]$1512 0' + end + attribute \src "ls180.v:5569.1-5570.4" + process $proc$ls180.v:5569$1514 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:557.12-557.42" + process $proc$ls180.v:557$1757 + assign { } { } + assign $1\sdram_bankmachine1_row[12:0] 13'0000000000000 + sync always + sync init + update \sdram_bankmachine1_row $1\sdram_bankmachine1_row[12:0] + end + attribute \src "ls180.v:5577.1-5581.4" + process $proc$ls180.v:5577$1516 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1517 $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520 + assign $0$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1518 $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521 + assign $0$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1519 $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:5580$1523_DATA + attribute \src "ls180.v:5578.2-5579.121" + switch \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:5578.6-5578.55" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522 25'1111111111111111111111111 + case + assign $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520 3'xxx + assign $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522 25'0000000000000000000000000 + end + sync posedge \sys_clk_1 + update \memdat_3 $0\memdat_3[24:0] + update $memwr$\storage_3$ls180.v:5579$12_ADDR $0$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1517 + update $memwr$\storage_3$ls180.v:5579$12_DATA $0$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1518 + update $memwr$\storage_3$ls180.v:5579$12_EN $0$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1519 + attribute \src "ls180.v:5579.3-5579.120" + memwr \storage_3 $1$memwr$\storage_3$ls180.v:5579$12_ADDR[2:0]$1520 $1$memwr$\storage_3$ls180.v:5579$12_DATA[24:0]$1521 $1$memwr$\storage_3$ls180.v:5579$12_EN[24:0]$1522 0' + end + attribute \src "ls180.v:558.5-558.41" + process $proc$ls180.v:558$1758 + assign { } { } + assign $1\sdram_bankmachine1_row_opened[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_row_opened $1\sdram_bankmachine1_row_opened[0:0] + end + attribute \src "ls180.v:5583.1-5584.4" + process $proc$ls180.v:5583$1524 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:5592.1-5596.4" + process $proc$ls180.v:5592$1526 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1527 $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530 + assign $0$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1528 $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531 + assign $0$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1529 $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:5595$1533_DATA + attribute \src "ls180.v:5593.2-5594.57" + switch \tx_fifo_wrport_we + attribute \src "ls180.v:5593.6-5593.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530 \tx_fifo_wrport_adr + assign $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531 \tx_fifo_wrport_dat_w + assign $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532 10'1111111111 + case + assign $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530 4'xxxx + assign $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531 10'xxxxxxxxxx + assign $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532 10'0000000000 + end + sync posedge \sys_clk_1 + update \memdat_4 $0\memdat_4[9:0] + update $memwr$\storage_4$ls180.v:5594$13_ADDR $0$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1527 + update $memwr$\storage_4$ls180.v:5594$13_DATA $0$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1528 + update $memwr$\storage_4$ls180.v:5594$13_EN $0$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1529 + attribute \src "ls180.v:5594.3-5594.56" + memwr \storage_4 $1$memwr$\storage_4$ls180.v:5594$13_ADDR[3:0]$1530 $1$memwr$\storage_4$ls180.v:5594$13_DATA[9:0]$1531 $1$memwr$\storage_4$ls180.v:5594$13_EN[9:0]$1532 0' + end + attribute \src "ls180.v:5598.1-5601.4" + process $proc$ls180.v:5598$1534 + assign $0\memdat_5[9:0] \memdat_5 + attribute \src "ls180.v:5599.2-5600.45" + switch \tx_fifo_rdport_re + attribute \src "ls180.v:5599.6-5599.23" + case 1'1 + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:5600$1535_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_5 $0\memdat_5[9:0] + end + attribute \src "ls180.v:560.5-560.39" + process $proc$ls180.v:560$1759 + assign { } { } + assign $1\sdram_bankmachine1_row_open[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_row_open $1\sdram_bankmachine1_row_open[0:0] + end + attribute \src "ls180.v:5609.1-5613.4" + process $proc$ls180.v:5609$1536 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1537 $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540 + assign $0$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1538 $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541 + assign $0$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1539 $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:5612$1543_DATA + attribute \src "ls180.v:5610.2-5611.57" + switch \rx_fifo_wrport_we + attribute \src "ls180.v:5610.6-5610.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540 \rx_fifo_wrport_adr + assign $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541 \rx_fifo_wrport_dat_w + assign $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542 10'1111111111 + case + assign $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540 4'xxxx + assign $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541 10'xxxxxxxxxx + assign $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542 10'0000000000 + end + sync posedge \sys_clk_1 + update \memdat_6 $0\memdat_6[9:0] + update $memwr$\storage_5$ls180.v:5611$14_ADDR $0$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1537 + update $memwr$\storage_5$ls180.v:5611$14_DATA $0$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1538 + update $memwr$\storage_5$ls180.v:5611$14_EN $0$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1539 + attribute \src "ls180.v:5611.3-5611.56" + memwr \storage_5 $1$memwr$\storage_5$ls180.v:5611$14_ADDR[3:0]$1540 $1$memwr$\storage_5$ls180.v:5611$14_DATA[9:0]$1541 $1$memwr$\storage_5$ls180.v:5611$14_EN[9:0]$1542 0' + end + attribute \src "ls180.v:561.5-561.40" + process $proc$ls180.v:561$1760 + assign { } { } + assign $1\sdram_bankmachine1_row_close[0:0] 1'0 sync always sync init - update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] + update \sdram_bankmachine1_row_close $1\sdram_bankmachine1_row_close[0:0] end - attribute \src "ls180.v:86.11-86.52" - process $proc$ls180.v:86$3137 + attribute \src "ls180.v:5615.1-5618.4" + process $proc$ls180.v:5615$1544 + assign $0\memdat_7[9:0] \memdat_7 + attribute \src "ls180.v:5616.2-5617.45" + switch \rx_fifo_rdport_re + attribute \src "ls180.v:5616.6-5616.23" + case 1'1 + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:5617$1545_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_7 $0\memdat_7[9:0] + end + attribute \src "ls180.v:562.5-562.49" + process $proc$ls180.v:562$1761 assign { } { } - assign $0\main_libresocsim_libresoc_ibus_bte[1:0] 2'00 + assign $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 sync always - update \main_libresocsim_libresoc_ibus_bte $0\main_libresocsim_libresoc_ibus_bte[1:0] sync init + update \sdram_bankmachine1_row_col_n_addr_sel $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:862.11-862.46" - process $proc$ls180.v:862$3417 + attribute \src "ls180.v:564.32-564.71" + process $proc$ls180.v:564$1762 assign { } { } - assign $1\main_sdram_choose_req_valids[3:0] 4'0000 + assign $1\sdram_bankmachine1_twtpcon_ready[0:0] 1'0 sync always sync init - update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] + update \sdram_bankmachine1_twtpcon_ready $1\sdram_bankmachine1_twtpcon_ready[0:0] end - attribute \src "ls180.v:864.11-864.45" - process $proc$ls180.v:864$3418 + attribute \src "ls180.v:565.11-565.50" + process $proc$ls180.v:565$1763 assign { } { } - assign $1\main_sdram_choose_req_grant[1:0] 2'00 + assign $1\sdram_bankmachine1_twtpcon_count[2:0] 3'000 sync always sync init - update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] + update \sdram_bankmachine1_twtpcon_count $1\sdram_bankmachine1_twtpcon_count[2:0] end - attribute \src "ls180.v:866.12-866.36" - process $proc$ls180.v:866$3419 + attribute \src "ls180.v:567.32-567.70" + process $proc$ls180.v:567$1764 assign { } { } - assign $0\main_sdram_nop_a[12:0] 13'0000000000000 + assign $0\sdram_bankmachine1_trccon_ready[0:0] 1'1 sync always - update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] + update \sdram_bankmachine1_trccon_ready $0\sdram_bankmachine1_trccon_ready[0:0] sync init end - attribute \src "ls180.v:867.11-867.35" - process $proc$ls180.v:867$3420 + attribute \src "ls180.v:569.32-569.71" + process $proc$ls180.v:569$1765 assign { } { } - assign $0\main_sdram_nop_ba[1:0] 2'00 + assign $0\sdram_bankmachine1_trascon_ready[0:0] 1'1 sync always - update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] + update \sdram_bankmachine1_trascon_ready $0\sdram_bankmachine1_trascon_ready[0:0] sync init end - attribute \src "ls180.v:868.11-868.40" - process $proc$ls180.v:868$3421 + attribute \src "ls180.v:575.5-575.46" + process $proc$ls180.v:575$1766 assign { } { } - assign $1\main_sdram_steerer_sel[1:0] 2'00 + assign $1\sdram_bankmachine2_req_wdata_ready[0:0] 1'0 sync always sync init - update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] + update \sdram_bankmachine2_req_wdata_ready $1\sdram_bankmachine2_req_wdata_ready[0:0] end - attribute \src "ls180.v:869.5-869.31" - process $proc$ls180.v:869$3422 + attribute \src "ls180.v:576.5-576.46" + process $proc$ls180.v:576$1767 assign { } { } - assign $0\main_sdram_steerer0[0:0] 1'1 + assign $1\sdram_bankmachine2_req_rdata_valid[0:0] 1'0 sync always - update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] sync init + update \sdram_bankmachine2_req_rdata_valid $1\sdram_bankmachine2_req_rdata_valid[0:0] end - attribute \src "ls180.v:870.5-870.31" - process $proc$ls180.v:870$3423 + attribute \src "ls180.v:578.5-578.42" + process $proc$ls180.v:578$1768 assign { } { } - assign $0\main_sdram_steerer1[0:0] 1'1 + assign $1\sdram_bankmachine2_refresh_gnt[0:0] 1'0 sync always - update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] sync init + update \sdram_bankmachine2_refresh_gnt $1\sdram_bankmachine2_refresh_gnt[0:0] end - attribute \src "ls180.v:872.32-872.63" - process $proc$ls180.v:872$3424 + attribute \src "ls180.v:579.5-579.40" + process $proc$ls180.v:579$1769 assign { } { } - assign $0\main_sdram_trrdcon_ready[0:0] 1'1 + assign $1\sdram_bankmachine2_cmd_valid[0:0] 1'0 sync always - update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] sync init + update \sdram_bankmachine2_cmd_valid $1\sdram_bankmachine2_cmd_valid[0:0] end - attribute \src "ls180.v:874.32-874.63" - process $proc$ls180.v:874$3425 + attribute \src "ls180.v:580.5-580.40" + process $proc$ls180.v:580$1770 assign { } { } - assign $0\main_sdram_tfawcon_ready[0:0] 1'1 + assign $1\sdram_bankmachine2_cmd_ready[0:0] 1'0 sync always - update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] sync init + update \sdram_bankmachine2_cmd_ready $1\sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:876.32-876.63" - process $proc$ls180.v:876$3426 + attribute \src "ls180.v:581.12-581.52" + process $proc$ls180.v:581$1771 assign { } { } - assign $1\main_sdram_tccdcon_ready[0:0] 1'0 + assign $1\sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] + update \sdram_bankmachine2_cmd_payload_a $1\sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:877.5-877.36" - process $proc$ls180.v:877$3427 + attribute \src "ls180.v:583.5-583.46" + process $proc$ls180.v:583$1772 assign { } { } - assign $1\main_sdram_tccdcon_count[0:0] 1'0 + assign $1\sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] + update \sdram_bankmachine2_cmd_payload_cas $1\sdram_bankmachine2_cmd_payload_cas[0:0] end - attribute \src "ls180.v:879.32-879.63" - process $proc$ls180.v:879$3428 + attribute \src "ls180.v:584.5-584.46" + process $proc$ls180.v:584$1773 assign { } { } - assign $1\main_sdram_twtrcon_ready[0:0] 1'0 + assign $1\sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 sync always sync init - update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] + update \sdram_bankmachine2_cmd_payload_ras $1\sdram_bankmachine2_cmd_payload_ras[0:0] end - attribute \src "ls180.v:88.12-88.58" - process $proc$ls180.v:88$3138 + attribute \src "ls180.v:585.5-585.45" + process $proc$ls180.v:585$1774 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + assign $1\sdram_bankmachine2_cmd_payload_we[0:0] 1'0 sync always sync init - update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0] + update \sdram_bankmachine2_cmd_payload_we $1\sdram_bankmachine2_cmd_payload_we[0:0] end - attribute \src "ls180.v:880.11-880.42" - process $proc$ls180.v:880$3429 + attribute \src "ls180.v:586.5-586.49" + process $proc$ls180.v:586$1775 assign { } { } - assign $1\main_sdram_twtrcon_count[2:0] 3'000 + assign $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 sync always sync init - update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] + update \sdram_bankmachine2_cmd_payload_is_cmd $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:883.5-883.26" - process $proc$ls180.v:883$3430 + attribute \src "ls180.v:587.5-587.50" + process $proc$ls180.v:587$1776 assign { } { } - assign $1\main_sdram_en0[0:0] 1'0 + assign $1\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 sync always sync init - update \main_sdram_en0 $1\main_sdram_en0[0:0] + update \sdram_bankmachine2_cmd_payload_is_read $1\sdram_bankmachine2_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:885.11-885.34" - process $proc$ls180.v:885$3431 + attribute \src "ls180.v:588.5-588.51" + process $proc$ls180.v:588$1777 assign { } { } - assign $1\main_sdram_time0[4:0] 5'00000 + assign $1\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 sync always sync init - update \main_sdram_time0 $1\main_sdram_time0[4:0] + update \sdram_bankmachine2_cmd_payload_is_write $1\sdram_bankmachine2_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:886.5-886.26" - process $proc$ls180.v:886$3432 + attribute \src "ls180.v:589.5-589.45" + process $proc$ls180.v:589$1778 assign { } { } - assign $1\main_sdram_en1[0:0] 1'0 + assign $1\sdram_bankmachine2_auto_precharge[0:0] 1'0 sync always sync init - update \main_sdram_en1 $1\main_sdram_en1[0:0] + update \sdram_bankmachine2_auto_precharge $1\sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:888.11-888.34" - process $proc$ls180.v:888$3433 + attribute \src "ls180.v:592.5-592.62" + process $proc$ls180.v:592$1779 assign { } { } - assign $1\main_sdram_time1[3:0] 4'0000 + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always + update \sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] sync init - update \main_sdram_time1 $1\main_sdram_time1[3:0] end - attribute \src "ls180.v:89.12-89.60" - process $proc$ls180.v:89$3139 + attribute \src "ls180.v:593.5-593.61" + process $proc$ls180.v:593$1780 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always + update \sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] sync init - update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] end - attribute \src "ls180.v:903.12-903.37" - process $proc$ls180.v:903$3434 + attribute \src "ls180.v:608.11-608.63" + process $proc$ls180.v:608$1781 assign { } { } - assign $1\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 + assign $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init - update \main_wb_sdram_adr $1\main_wb_sdram_adr[29:0] + update \sdram_bankmachine2_cmd_buffer_lookahead_level $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:904.12-904.39" - process $proc$ls180.v:904$3435 + attribute \src "ls180.v:609.5-609.59" + process $proc$ls180.v:609$1782 assign { } { } - assign $1\main_wb_sdram_dat_w[31:0] 0 + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 sync always + update \sdram_bankmachine2_cmd_buffer_lookahead_replace $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] sync init - update \main_wb_sdram_dat_w $1\main_wb_sdram_dat_w[31:0] end - attribute \src "ls180.v:906.11-906.35" - process $proc$ls180.v:906$3436 + attribute \src "ls180.v:610.11-610.65" + process $proc$ls180.v:610$1783 assign { } { } - assign $1\main_wb_sdram_sel[3:0] 4'0000 + assign $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init - update \main_wb_sdram_sel $1\main_wb_sdram_sel[3:0] + update \sdram_bankmachine2_cmd_buffer_lookahead_produce $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:907.5-907.29" - process $proc$ls180.v:907$3437 + attribute \src "ls180.v:611.11-611.65" + process $proc$ls180.v:611$1784 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_lookahead_consume $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:612.11-612.68" + process $proc$ls180.v:612$1785 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:62.5-62.41" + process $proc$ls180.v:62$1553 + assign { } { } + assign $1\libresocsim_libresoc_dbus_ack[0:0] 1'0 + sync always + sync init + update \libresocsim_libresoc_dbus_ack $1\libresocsim_libresoc_dbus_ack[0:0] + end + attribute \src "ls180.v:633.5-633.54" + process $proc$ls180.v:633$1786 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_source_valid $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:635.5-635.54" + process $proc$ls180.v:635$1787 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_source_first $1\sdram_bankmachine2_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:636.5-636.53" + process $proc$ls180.v:636$1788 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_source_last $1\sdram_bankmachine2_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:637.5-637.59" + process $proc$ls180.v:637$1789 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_source_payload_we $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:638.12-638.69" + process $proc$ls180.v:638$1790 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_source_payload_addr $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:639.12-639.42" + process $proc$ls180.v:639$1791 + assign { } { } + assign $1\sdram_bankmachine2_row[12:0] 13'0000000000000 + sync always + sync init + update \sdram_bankmachine2_row $1\sdram_bankmachine2_row[12:0] + end + attribute \src "ls180.v:64.5-64.41" + process $proc$ls180.v:64$1554 + assign { } { } + assign $0\libresocsim_libresoc_dbus_err[0:0] 1'0 + sync always + update \libresocsim_libresoc_dbus_err $0\libresocsim_libresoc_dbus_err[0:0] + sync init + end + attribute \src "ls180.v:640.5-640.41" + process $proc$ls180.v:640$1792 + assign { } { } + assign $1\sdram_bankmachine2_row_opened[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_row_opened $1\sdram_bankmachine2_row_opened[0:0] + end + attribute \src "ls180.v:642.5-642.39" + process $proc$ls180.v:642$1793 + assign { } { } + assign $1\sdram_bankmachine2_row_open[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_row_open $1\sdram_bankmachine2_row_open[0:0] + end + attribute \src "ls180.v:643.5-643.40" + process $proc$ls180.v:643$1794 + assign { } { } + assign $1\sdram_bankmachine2_row_close[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_row_close $1\sdram_bankmachine2_row_close[0:0] + end + attribute \src "ls180.v:644.5-644.49" + process $proc$ls180.v:644$1795 + assign { } { } + assign $1\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_row_col_n_addr_sel $1\sdram_bankmachine2_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:646.32-646.71" + process $proc$ls180.v:646$1796 + assign { } { } + assign $1\sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_twtpcon_ready $1\sdram_bankmachine2_twtpcon_ready[0:0] + end + attribute \src "ls180.v:647.11-647.50" + process $proc$ls180.v:647$1797 + assign { } { } + assign $1\sdram_bankmachine2_twtpcon_count[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine2_twtpcon_count $1\sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "ls180.v:649.32-649.70" + process $proc$ls180.v:649$1798 + assign { } { } + assign $0\sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \sdram_bankmachine2_trccon_ready $0\sdram_bankmachine2_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:651.32-651.71" + process $proc$ls180.v:651$1799 + assign { } { } + assign $0\sdram_bankmachine2_trascon_ready[0:0] 1'1 + sync always + update \sdram_bankmachine2_trascon_ready $0\sdram_bankmachine2_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:657.5-657.46" + process $proc$ls180.v:657$1800 + assign { } { } + assign $1\sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_req_wdata_ready $1\sdram_bankmachine3_req_wdata_ready[0:0] + end + attribute \src "ls180.v:658.5-658.46" + process $proc$ls180.v:658$1801 + assign { } { } + assign $1\sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_req_rdata_valid $1\sdram_bankmachine3_req_rdata_valid[0:0] + end + attribute \src "ls180.v:660.5-660.42" + process $proc$ls180.v:660$1802 + assign { } { } + assign $1\sdram_bankmachine3_refresh_gnt[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_refresh_gnt $1\sdram_bankmachine3_refresh_gnt[0:0] + end + attribute \src "ls180.v:661.5-661.40" + process $proc$ls180.v:661$1803 + assign { } { } + assign $1\sdram_bankmachine3_cmd_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_valid $1\sdram_bankmachine3_cmd_valid[0:0] + end + attribute \src "ls180.v:662.5-662.40" + process $proc$ls180.v:662$1804 + assign { } { } + assign $1\sdram_bankmachine3_cmd_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_ready $1\sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:663.12-663.52" + process $proc$ls180.v:663$1805 + assign { } { } + assign $1\sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \sdram_bankmachine3_cmd_payload_a $1\sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:665.5-665.46" + process $proc$ls180.v:665$1806 + assign { } { } + assign $1\sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_payload_cas $1\sdram_bankmachine3_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:666.5-666.46" + process $proc$ls180.v:666$1807 + assign { } { } + assign $1\sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_payload_ras $1\sdram_bankmachine3_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:667.5-667.45" + process $proc$ls180.v:667$1808 + assign { } { } + assign $1\sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_payload_we $1\sdram_bankmachine3_cmd_payload_we[0:0] + end + attribute \src "ls180.v:668.5-668.49" + process $proc$ls180.v:668$1809 + assign { } { } + assign $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_payload_is_cmd $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:669.5-669.50" + process $proc$ls180.v:669$1810 + assign { } { } + assign $1\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_payload_is_read $1\sdram_bankmachine3_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:670.5-670.51" + process $proc$ls180.v:670$1811 + assign { } { } + assign $1\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_payload_is_write $1\sdram_bankmachine3_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:671.5-671.45" + process $proc$ls180.v:671$1812 + assign { } { } + assign $1\sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_auto_precharge $1\sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:674.5-674.62" + process $proc$ls180.v:674$1813 + assign { } { } + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:675.5-675.61" + process $proc$ls180.v:675$1814 + assign { } { } + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:690.11-690.63" + process $proc$ls180.v:690$1815 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_lookahead_level $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:691.5-691.59" + process $proc$ls180.v:691$1816 + assign { } { } + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \sdram_bankmachine3_cmd_buffer_lookahead_replace $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:692.11-692.65" + process $proc$ls180.v:692$1817 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_lookahead_produce $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:693.11-693.65" + process $proc$ls180.v:693$1818 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_lookahead_consume $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:694.11-694.68" + process $proc$ls180.v:694$1819 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:71.5-71.41" + process $proc$ls180.v:71$1555 + assign { } { } + assign $1\libresocsim_libresoc_ibus_ack[0:0] 1'0 + sync always + sync init + update \libresocsim_libresoc_ibus_ack $1\libresocsim_libresoc_ibus_ack[0:0] + end + attribute \src "ls180.v:715.5-715.54" + process $proc$ls180.v:715$1820 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_source_valid $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:717.5-717.54" + process $proc$ls180.v:717$1821 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_source_first $1\sdram_bankmachine3_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:718.5-718.53" + process $proc$ls180.v:718$1822 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_source_last $1\sdram_bankmachine3_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:719.5-719.59" + process $proc$ls180.v:719$1823 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_source_payload_we $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:720.12-720.69" + process $proc$ls180.v:720$1824 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_source_payload_addr $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:721.12-721.42" + process $proc$ls180.v:721$1825 + assign { } { } + assign $1\sdram_bankmachine3_row[12:0] 13'0000000000000 + sync always + sync init + update \sdram_bankmachine3_row $1\sdram_bankmachine3_row[12:0] + end + attribute \src "ls180.v:722.5-722.41" + process $proc$ls180.v:722$1826 + assign { } { } + assign $1\sdram_bankmachine3_row_opened[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_row_opened $1\sdram_bankmachine3_row_opened[0:0] + end + attribute \src "ls180.v:724.5-724.39" + process $proc$ls180.v:724$1827 + assign { } { } + assign $1\sdram_bankmachine3_row_open[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_row_open $1\sdram_bankmachine3_row_open[0:0] + end + attribute \src "ls180.v:725.5-725.40" + process $proc$ls180.v:725$1828 + assign { } { } + assign $1\sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_row_close $1\sdram_bankmachine3_row_close[0:0] + end + attribute \src "ls180.v:726.5-726.49" + process $proc$ls180.v:726$1829 + assign { } { } + assign $1\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_row_col_n_addr_sel $1\sdram_bankmachine3_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:728.32-728.71" + process $proc$ls180.v:728$1830 + assign { } { } + assign $1\sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_twtpcon_ready $1\sdram_bankmachine3_twtpcon_ready[0:0] + end + attribute \src "ls180.v:729.11-729.50" + process $proc$ls180.v:729$1831 + assign { } { } + assign $1\sdram_bankmachine3_twtpcon_count[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine3_twtpcon_count $1\sdram_bankmachine3_twtpcon_count[2:0] + end + attribute \src "ls180.v:73.5-73.41" + process $proc$ls180.v:73$1556 + assign { } { } + assign $0\libresocsim_libresoc_ibus_err[0:0] 1'0 + sync always + update \libresocsim_libresoc_ibus_err $0\libresocsim_libresoc_ibus_err[0:0] + sync init + end + attribute \src "ls180.v:731.32-731.70" + process $proc$ls180.v:731$1832 + assign { } { } + assign $0\sdram_bankmachine3_trccon_ready[0:0] 1'1 + sync always + update \sdram_bankmachine3_trccon_ready $0\sdram_bankmachine3_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:733.32-733.71" + process $proc$ls180.v:733$1833 + assign { } { } + assign $0\sdram_bankmachine3_trascon_ready[0:0] 1'1 + sync always + update \sdram_bankmachine3_trascon_ready $0\sdram_bankmachine3_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:736.5-736.39" + process $proc$ls180.v:736$1834 + assign { } { } + assign $0\sdram_choose_cmd_want_reads[0:0] 1'0 + sync always + update \sdram_choose_cmd_want_reads $0\sdram_choose_cmd_want_reads[0:0] + sync init + end + attribute \src "ls180.v:737.5-737.40" + process $proc$ls180.v:737$1835 + assign { } { } + assign $0\sdram_choose_cmd_want_writes[0:0] 1'0 + sync always + update \sdram_choose_cmd_want_writes $0\sdram_choose_cmd_want_writes[0:0] + sync init + end + attribute \src "ls180.v:738.5-738.38" + process $proc$ls180.v:738$1836 + assign { } { } + assign $0\sdram_choose_cmd_want_cmds[0:0] 1'0 + sync always + update \sdram_choose_cmd_want_cmds $0\sdram_choose_cmd_want_cmds[0:0] + sync init + end + attribute \src "ls180.v:739.5-739.43" + process $proc$ls180.v:739$1837 + assign { } { } + assign $0\sdram_choose_cmd_want_activates[0:0] 1'0 + sync always + update \sdram_choose_cmd_want_activates $0\sdram_choose_cmd_want_activates[0:0] + sync init + end + attribute \src "ls180.v:741.5-741.38" + process $proc$ls180.v:741$1838 + assign { } { } + assign $0\sdram_choose_cmd_cmd_ready[0:0] 1'0 + sync always + update \sdram_choose_cmd_cmd_ready $0\sdram_choose_cmd_cmd_ready[0:0] + sync init + end + attribute \src "ls180.v:744.5-744.44" + process $proc$ls180.v:744$1839 + assign { } { } + assign $1\sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \sdram_choose_cmd_cmd_payload_cas $1\sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:745.5-745.44" + process $proc$ls180.v:745$1840 + assign { } { } + assign $1\sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \sdram_choose_cmd_cmd_payload_ras $1\sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:746.5-746.43" + process $proc$ls180.v:746$1841 + assign { } { } + assign $1\sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_choose_cmd_cmd_payload_we $1\sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:750.11-750.41" + process $proc$ls180.v:750$1842 + assign { } { } + assign $1\sdram_choose_cmd_valids[3:0] 4'0000 + sync always + sync init + update \sdram_choose_cmd_valids $1\sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:752.11-752.40" + process $proc$ls180.v:752$1843 + assign { } { } + assign $1\sdram_choose_cmd_grant[1:0] 2'00 + sync always + sync init + update \sdram_choose_cmd_grant $1\sdram_choose_cmd_grant[1:0] + end + attribute \src "ls180.v:754.5-754.39" + process $proc$ls180.v:754$1844 + assign { } { } + assign $1\sdram_choose_req_want_reads[0:0] 1'0 + sync always + sync init + update \sdram_choose_req_want_reads $1\sdram_choose_req_want_reads[0:0] + end + attribute \src "ls180.v:755.5-755.40" + process $proc$ls180.v:755$1845 + assign { } { } + assign $1\sdram_choose_req_want_writes[0:0] 1'0 + sync always + sync init + update \sdram_choose_req_want_writes $1\sdram_choose_req_want_writes[0:0] + end + attribute \src "ls180.v:757.5-757.43" + process $proc$ls180.v:757$1846 + assign { } { } + assign $1\sdram_choose_req_want_activates[0:0] 1'0 + sync always + sync init + update \sdram_choose_req_want_activates $1\sdram_choose_req_want_activates[0:0] + end + attribute \src "ls180.v:759.5-759.38" + process $proc$ls180.v:759$1847 + assign { } { } + assign $1\sdram_choose_req_cmd_ready[0:0] 1'0 + sync always + sync init + update \sdram_choose_req_cmd_ready $1\sdram_choose_req_cmd_ready[0:0] + end + attribute \src "ls180.v:762.5-762.44" + process $proc$ls180.v:762$1848 + assign { } { } + assign $1\sdram_choose_req_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \sdram_choose_req_cmd_payload_cas $1\sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:763.5-763.44" + process $proc$ls180.v:763$1849 + assign { } { } + assign $1\sdram_choose_req_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \sdram_choose_req_cmd_payload_ras $1\sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:764.5-764.43" + process $proc$ls180.v:764$1850 + assign { } { } + assign $1\sdram_choose_req_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_choose_req_cmd_payload_we $1\sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:768.11-768.41" + process $proc$ls180.v:768$1851 + assign { } { } + assign $1\sdram_choose_req_valids[3:0] 4'0000 + sync always + sync init + update \sdram_choose_req_valids $1\sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:770.11-770.40" + process $proc$ls180.v:770$1852 + assign { } { } + assign $1\sdram_choose_req_grant[1:0] 2'00 + sync always + sync init + update \sdram_choose_req_grant $1\sdram_choose_req_grant[1:0] + end + attribute \src "ls180.v:772.12-772.31" + process $proc$ls180.v:772$1853 + assign { } { } + assign $0\sdram_nop_a[12:0] 13'0000000000000 + sync always + update \sdram_nop_a $0\sdram_nop_a[12:0] + sync init + end + attribute \src "ls180.v:773.11-773.30" + process $proc$ls180.v:773$1854 + assign { } { } + assign $0\sdram_nop_ba[1:0] 2'00 + sync always + update \sdram_nop_ba $0\sdram_nop_ba[1:0] + sync init + end + attribute \src "ls180.v:774.11-774.35" + process $proc$ls180.v:774$1855 + assign { } { } + assign $1\sdram_steerer_sel[1:0] 2'00 + sync always + sync init + update \sdram_steerer_sel $1\sdram_steerer_sel[1:0] + end + attribute \src "ls180.v:775.5-775.26" + process $proc$ls180.v:775$1856 + assign { } { } + assign $0\sdram_steerer0[0:0] 1'1 + sync always + update \sdram_steerer0 $0\sdram_steerer0[0:0] + sync init + end + attribute \src "ls180.v:776.5-776.26" + process $proc$ls180.v:776$1857 + assign { } { } + assign $0\sdram_steerer1[0:0] 1'1 + sync always + update \sdram_steerer1 $0\sdram_steerer1[0:0] + sync init + end + attribute \src "ls180.v:778.32-778.58" + process $proc$ls180.v:778$1858 + assign { } { } + assign $0\sdram_trrdcon_ready[0:0] 1'1 + sync always + update \sdram_trrdcon_ready $0\sdram_trrdcon_ready[0:0] + sync init + end + attribute \src "ls180.v:780.32-780.58" + process $proc$ls180.v:780$1859 + assign { } { } + assign $0\sdram_tfawcon_ready[0:0] 1'1 + sync always + update \sdram_tfawcon_ready $0\sdram_tfawcon_ready[0:0] + sync init + end + attribute \src "ls180.v:782.32-782.58" + process $proc$ls180.v:782$1860 + assign { } { } + assign $1\sdram_tccdcon_ready[0:0] 1'0 + sync always + sync init + update \sdram_tccdcon_ready $1\sdram_tccdcon_ready[0:0] + end + attribute \src "ls180.v:783.5-783.31" + process $proc$ls180.v:783$1861 + assign { } { } + assign $1\sdram_tccdcon_count[0:0] 1'0 + sync always + sync init + update \sdram_tccdcon_count $1\sdram_tccdcon_count[0:0] + end + attribute \src "ls180.v:785.32-785.58" + process $proc$ls180.v:785$1862 + assign { } { } + assign $1\sdram_twtrcon_ready[0:0] 1'0 + sync always + sync init + update \sdram_twtrcon_ready $1\sdram_twtrcon_ready[0:0] + end + attribute \src "ls180.v:786.11-786.37" + process $proc$ls180.v:786$1863 + assign { } { } + assign $1\sdram_twtrcon_count[2:0] 3'000 + sync always + sync init + update \sdram_twtrcon_count $1\sdram_twtrcon_count[2:0] + end + attribute \src "ls180.v:789.5-789.21" + process $proc$ls180.v:789$1864 + assign { } { } + assign $1\sdram_en0[0:0] 1'0 + sync always + sync init + update \sdram_en0 $1\sdram_en0[0:0] + end + attribute \src "ls180.v:791.11-791.29" + process $proc$ls180.v:791$1865 + assign { } { } + assign $1\sdram_time0[4:0] 5'00000 + sync always + sync init + update \sdram_time0 $1\sdram_time0[4:0] + end + attribute \src "ls180.v:792.5-792.21" + process $proc$ls180.v:792$1866 + assign { } { } + assign $1\sdram_en1[0:0] 1'0 + sync always + sync init + update \sdram_en1 $1\sdram_en1[0:0] + end + attribute \src "ls180.v:794.11-794.29" + process $proc$ls180.v:794$1867 + assign { } { } + assign $1\sdram_time1[3:0] 4'0000 + sync always + sync init + update \sdram_time1 $1\sdram_time1[3:0] + end + attribute \src "ls180.v:815.5-815.24" + process $proc$ls180.v:815$1868 + assign { } { } + assign $1\wb_sdram_ack[0:0] 1'0 + sync always + sync init + update \wb_sdram_ack $1\wb_sdram_ack[0:0] + end + attribute \src "ls180.v:819.5-819.24" + process $proc$ls180.v:819$1869 + assign { } { } + assign $0\wb_sdram_err[0:0] 1'0 + sync always + update \wb_sdram_err $0\wb_sdram_err[0:0] + sync init + end + attribute \src "ls180.v:820.12-820.35" + process $proc$ls180.v:820$1870 + assign { } { } + assign $1\litedram_wb_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \litedram_wb_adr $1\litedram_wb_adr[29:0] + end + attribute \src "ls180.v:821.12-821.37" + process $proc$ls180.v:821$1871 + assign { } { } + assign $1\litedram_wb_dat_w[15:0] 16'0000000000000000 + sync always + sync init + update \litedram_wb_dat_w $1\litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:823.11-823.33" + process $proc$ls180.v:823$1872 + assign { } { } + assign $1\litedram_wb_sel[1:0] 2'00 + sync always + sync init + update \litedram_wb_sel $1\litedram_wb_sel[1:0] + end + attribute \src "ls180.v:824.5-824.27" + process $proc$ls180.v:824$1873 + assign { } { } + assign $1\litedram_wb_cyc[0:0] 1'0 + sync always + sync init + update \litedram_wb_cyc $1\litedram_wb_cyc[0:0] + end + attribute \src "ls180.v:825.5-825.27" + process $proc$ls180.v:825$1874 + assign { } { } + assign $1\litedram_wb_stb[0:0] 1'0 + sync always + sync init + update \litedram_wb_stb $1\litedram_wb_stb[0:0] + end + attribute \src "ls180.v:827.5-827.26" + process $proc$ls180.v:827$1875 assign { } { } - assign $1\main_wb_sdram_cyc[0:0] 1'0 + assign $1\litedram_wb_we[0:0] 1'0 sync always sync init - update \main_wb_sdram_cyc $1\main_wb_sdram_cyc[0:0] + update \litedram_wb_we $1\litedram_wb_we[0:0] end - attribute \src "ls180.v:908.5-908.29" - process $proc$ls180.v:908$3438 + attribute \src "ls180.v:828.5-828.26" + process $proc$ls180.v:828$1876 assign { } { } - assign $1\main_wb_sdram_stb[0:0] 1'0 + assign $1\converter_skip[0:0] 1'0 sync always sync init - update \main_wb_sdram_stb $1\main_wb_sdram_stb[0:0] + update \converter_skip $1\converter_skip[0:0] end - attribute \src "ls180.v:909.5-909.29" - process $proc$ls180.v:909$3439 + attribute \src "ls180.v:829.5-829.29" + process $proc$ls180.v:829$1877 assign { } { } - assign $1\main_wb_sdram_ack[0:0] 1'0 + assign $1\converter_counter[0:0] 1'0 sync always sync init - update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] + update \converter_counter $1\converter_counter[0:0] end - attribute \src "ls180.v:91.11-91.56" - process $proc$ls180.v:91$3140 + attribute \src "ls180.v:831.12-831.35" + process $proc$ls180.v:831$1878 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + assign $1\converter_dat_r[31:0] 0 sync always sync init - update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0] + update \converter_dat_r $1\converter_dat_r[31:0] end - attribute \src "ls180.v:910.5-910.28" - process $proc$ls180.v:910$3440 + attribute \src "ls180.v:832.5-832.24" + process $proc$ls180.v:832$1879 assign { } { } - assign $1\main_wb_sdram_we[0:0] 1'0 + assign $1\cmd_consumed[0:0] 1'0 sync always sync init - update \main_wb_sdram_we $1\main_wb_sdram_we[0:0] + update \cmd_consumed $1\cmd_consumed[0:0] end - attribute \src "ls180.v:917.5-917.54" - process $proc$ls180.v:917$3441 + attribute \src "ls180.v:833.5-833.26" + process $proc$ls180.v:833$1880 assign { } { } - assign $1\main_socbushandler_converted_interface_ack[0:0] 1'0 + assign $1\wdata_consumed[0:0] 1'0 sync always sync init - update \main_socbushandler_converted_interface_ack $1\main_socbushandler_converted_interface_ack[0:0] + update \wdata_consumed $1\wdata_consumed[0:0] end - attribute \src "ls180.v:92.5-92.50" - process $proc$ls180.v:92$3141 + attribute \src "ls180.v:837.12-837.42" + process $proc$ls180.v:837$1881 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + assign $1\uart_phy_storage[31:0] 9895604 sync always sync init - update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + update \uart_phy_storage $1\uart_phy_storage[31:0] end - attribute \src "ls180.v:921.5-921.54" - process $proc$ls180.v:921$3442 + attribute \src "ls180.v:838.5-838.23" + process $proc$ls180.v:838$1882 assign { } { } - assign $0\main_socbushandler_converted_interface_err[0:0] 1'0 + assign $1\uart_phy_re[0:0] 1'0 sync always - update \main_socbushandler_converted_interface_err $0\main_socbushandler_converted_interface_err[0:0] sync init + update \uart_phy_re $1\uart_phy_re[0:0] end - attribute \src "ls180.v:922.5-922.35" - process $proc$ls180.v:922$3443 + attribute \src "ls180.v:840.5-840.31" + process $proc$ls180.v:840$1883 assign { } { } - assign $1\main_socbushandler_skip[0:0] 1'0 + assign $1\uart_phy_sink_ready[0:0] 1'0 sync always sync init - update \main_socbushandler_skip $1\main_socbushandler_skip[0:0] + update \uart_phy_sink_ready $1\uart_phy_sink_ready[0:0] end - attribute \src "ls180.v:923.5-923.38" - process $proc$ls180.v:923$3444 + attribute \src "ls180.v:844.5-844.34" + process $proc$ls180.v:844$1884 assign { } { } - assign $1\main_socbushandler_counter[0:0] 1'0 + assign $1\uart_phy_uart_clk_txen[0:0] 1'0 sync always sync init - update \main_socbushandler_counter $1\main_socbushandler_counter[0:0] + update \uart_phy_uart_clk_txen $1\uart_phy_uart_clk_txen[0:0] end - attribute \src "ls180.v:925.12-925.44" - process $proc$ls180.v:925$3445 + attribute \src "ls180.v:845.12-845.49" + process $proc$ls180.v:845$1885 assign { } { } - assign $1\main_socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\uart_phy_phase_accumulator_tx[31:0] 0 sync always sync init - update \main_socbushandler_dat_r $1\main_socbushandler_dat_r[63:0] + update \uart_phy_phase_accumulator_tx $1\uart_phy_phase_accumulator_tx[31:0] end - attribute \src "ls180.v:926.12-926.40" - process $proc$ls180.v:926$3446 + attribute \src "ls180.v:846.11-846.33" + process $proc$ls180.v:846$1886 assign { } { } - assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $1\uart_phy_tx_reg[7:0] 8'00000000 sync always sync init - update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] + update \uart_phy_tx_reg $1\uart_phy_tx_reg[7:0] end - attribute \src "ls180.v:927.12-927.42" - process $proc$ls180.v:927$3447 + attribute \src "ls180.v:847.11-847.38" + process $proc$ls180.v:847$1887 assign { } { } - assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + assign $1\uart_phy_tx_bitcount[3:0] 4'0000 sync always sync init - update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] + update \uart_phy_tx_bitcount $1\uart_phy_tx_bitcount[3:0] end - attribute \src "ls180.v:929.11-929.38" - process $proc$ls180.v:929$3448 + attribute \src "ls180.v:848.5-848.28" + process $proc$ls180.v:848$1888 assign { } { } - assign $1\main_litedram_wb_sel[1:0] 2'00 + assign $1\uart_phy_tx_busy[0:0] 1'0 sync always sync init - update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] + update \uart_phy_tx_busy $1\uart_phy_tx_busy[0:0] end - attribute \src "ls180.v:93.5-93.50" - process $proc$ls180.v:93$3142 + attribute \src "ls180.v:849.5-849.33" + process $proc$ls180.v:849$1889 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + assign $1\uart_phy_source_valid[0:0] 1'0 sync always sync init - update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + update \uart_phy_source_valid $1\uart_phy_source_valid[0:0] end - attribute \src "ls180.v:930.5-930.32" - process $proc$ls180.v:930$3449 + attribute \src "ls180.v:851.5-851.33" + process $proc$ls180.v:851$1890 assign { } { } - assign $1\main_litedram_wb_cyc[0:0] 1'0 + assign $0\uart_phy_source_first[0:0] 1'0 sync always + update \uart_phy_source_first $0\uart_phy_source_first[0:0] sync init - update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] end - attribute \src "ls180.v:931.5-931.32" - process $proc$ls180.v:931$3450 + attribute \src "ls180.v:852.5-852.32" + process $proc$ls180.v:852$1891 assign { } { } - assign $1\main_litedram_wb_stb[0:0] 1'0 + assign $0\uart_phy_source_last[0:0] 1'0 sync always + update \uart_phy_source_last $0\uart_phy_source_last[0:0] sync init - update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] end - attribute \src "ls180.v:933.5-933.31" - process $proc$ls180.v:933$3451 + attribute \src "ls180.v:853.11-853.46" + process $proc$ls180.v:853$1892 assign { } { } - assign $1\main_litedram_wb_we[0:0] 1'0 + assign $1\uart_phy_source_payload_data[7:0] 8'00000000 sync always sync init - update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] + update \uart_phy_source_payload_data $1\uart_phy_source_payload_data[7:0] end - attribute \src "ls180.v:934.5-934.31" - process $proc$ls180.v:934$3452 + attribute \src "ls180.v:854.5-854.34" + process $proc$ls180.v:854$1893 assign { } { } - assign $1\main_converter_skip[0:0] 1'0 + assign $1\uart_phy_uart_clk_rxen[0:0] 1'0 sync always sync init - update \main_converter_skip $1\main_converter_skip[0:0] + update \uart_phy_uart_clk_rxen $1\uart_phy_uart_clk_rxen[0:0] end - attribute \src "ls180.v:935.5-935.34" - process $proc$ls180.v:935$3453 + attribute \src "ls180.v:855.12-855.49" + process $proc$ls180.v:855$1894 assign { } { } - assign $1\main_converter_counter[0:0] 1'0 + assign $1\uart_phy_phase_accumulator_rx[31:0] 0 sync always sync init - update \main_converter_counter $1\main_converter_counter[0:0] + update \uart_phy_phase_accumulator_rx $1\uart_phy_phase_accumulator_rx[31:0] end - attribute \src "ls180.v:937.12-937.40" - process $proc$ls180.v:937$3454 + attribute \src "ls180.v:857.5-857.25" + process $proc$ls180.v:857$1895 assign { } { } - assign $1\main_converter_dat_r[31:0] 0 + assign $1\uart_phy_rx_r[0:0] 1'0 sync always sync init - update \main_converter_dat_r $1\main_converter_dat_r[31:0] + update \uart_phy_rx_r $1\uart_phy_rx_r[0:0] end - attribute \src "ls180.v:938.5-938.29" - process $proc$ls180.v:938$3455 + attribute \src "ls180.v:858.11-858.33" + process $proc$ls180.v:858$1896 assign { } { } - assign $1\main_cmd_consumed[0:0] 1'0 + assign $1\uart_phy_rx_reg[7:0] 8'00000000 sync always sync init - update \main_cmd_consumed $1\main_cmd_consumed[0:0] + update \uart_phy_rx_reg $1\uart_phy_rx_reg[7:0] end - attribute \src "ls180.v:939.5-939.31" - process $proc$ls180.v:939$3456 + attribute \src "ls180.v:859.11-859.38" + process $proc$ls180.v:859$1897 assign { } { } - assign $1\main_wdata_consumed[0:0] 1'0 + assign $1\uart_phy_rx_bitcount[3:0] 4'0000 sync always sync init - update \main_wdata_consumed $1\main_wdata_consumed[0:0] + update \uart_phy_rx_bitcount $1\uart_phy_rx_bitcount[3:0] end - attribute \src "ls180.v:943.12-943.47" - process $proc$ls180.v:943$3457 + attribute \src "ls180.v:860.5-860.28" + process $proc$ls180.v:860$1898 assign { } { } - assign $1\main_uart_phy_storage[31:0] 9895604 + assign $1\uart_phy_rx_busy[0:0] 1'0 sync always sync init - update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] + update \uart_phy_rx_busy $1\uart_phy_rx_busy[0:0] end - attribute \src "ls180.v:944.5-944.28" - process $proc$ls180.v:944$3458 + attribute \src "ls180.v:871.5-871.22" + process $proc$ls180.v:871$1899 assign { } { } - assign $1\main_uart_phy_re[0:0] 1'0 + assign $1\tx_pending[0:0] 1'0 sync always sync init - update \main_uart_phy_re $1\main_uart_phy_re[0:0] + update \tx_pending $1\tx_pending[0:0] end - attribute \src "ls180.v:946.5-946.36" - process $proc$ls180.v:946$3459 + attribute \src "ls180.v:873.5-873.20" + process $proc$ls180.v:873$1900 assign { } { } - assign $1\main_uart_phy_sink_ready[0:0] 1'0 + assign $1\tx_clear[0:0] 1'0 sync always sync init - update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] + update \tx_clear $1\tx_clear[0:0] end - attribute \src "ls180.v:95.5-95.49" - process $proc$ls180.v:95$3143 + attribute \src "ls180.v:874.5-874.26" + process $proc$ls180.v:874$1901 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 + assign $1\tx_old_trigger[0:0] 1'0 sync always sync init - update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] + update \tx_old_trigger $1\tx_old_trigger[0:0] end - attribute \src "ls180.v:950.5-950.39" - process $proc$ls180.v:950$3460 + attribute \src "ls180.v:876.5-876.22" + process $proc$ls180.v:876$1902 assign { } { } - assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 + assign $1\rx_pending[0:0] 1'0 sync always sync init - update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] + update \rx_pending $1\rx_pending[0:0] end - attribute \src "ls180.v:951.12-951.54" - process $proc$ls180.v:951$3461 + attribute \src "ls180.v:878.5-878.20" + process $proc$ls180.v:878$1903 assign { } { } - assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 + assign $1\rx_clear[0:0] 1'0 sync always sync init - update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] + update \rx_clear $1\rx_clear[0:0] end - attribute \src "ls180.v:952.11-952.38" - process $proc$ls180.v:952$3462 + attribute \src "ls180.v:879.5-879.26" + process $proc$ls180.v:879$1904 assign { } { } - assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 + assign $1\rx_old_trigger[0:0] 1'0 sync always sync init - update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] + update \rx_old_trigger $1\rx_old_trigger[0:0] end - attribute \src "ls180.v:953.11-953.43" - process $proc$ls180.v:953$3463 + attribute \src "ls180.v:883.11-883.39" + process $proc$ls180.v:883$1905 assign { } { } - assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 + assign $1\eventmanager_status_w[1:0] 2'00 sync always sync init - update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] + update \eventmanager_status_w $1\eventmanager_status_w[1:0] end - attribute \src "ls180.v:954.5-954.33" - process $proc$ls180.v:954$3464 + attribute \src "ls180.v:887.11-887.40" + process $proc$ls180.v:887$1906 assign { } { } - assign $1\main_uart_phy_tx_busy[0:0] 1'0 + assign $1\eventmanager_pending_w[1:0] 2'00 sync always sync init - update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] + update \eventmanager_pending_w $1\eventmanager_pending_w[1:0] end - attribute \src "ls180.v:955.5-955.38" - process $proc$ls180.v:955$3465 + attribute \src "ls180.v:888.11-888.38" + process $proc$ls180.v:888$1907 assign { } { } - assign $1\main_uart_phy_source_valid[0:0] 1'0 + assign $1\eventmanager_storage[1:0] 2'00 sync always sync init - update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] + update \eventmanager_storage $1\eventmanager_storage[1:0] end - attribute \src "ls180.v:957.5-957.38" - process $proc$ls180.v:957$3466 + attribute \src "ls180.v:889.5-889.27" + process $proc$ls180.v:889$1908 assign { } { } - assign $0\main_uart_phy_source_first[0:0] 1'0 + assign $1\eventmanager_re[0:0] 1'0 sync always - update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] sync init + update \eventmanager_re $1\eventmanager_re[0:0] end - attribute \src "ls180.v:958.5-958.37" - process $proc$ls180.v:958$3467 + attribute \src "ls180.v:906.5-906.30" + process $proc$ls180.v:906$1909 + assign { } { } + assign $0\tx_fifo_sink_first[0:0] 1'0 + sync always + update \tx_fifo_sink_first $0\tx_fifo_sink_first[0:0] + sync init + end + attribute \src "ls180.v:907.5-907.29" + process $proc$ls180.v:907$1910 assign { } { } - assign $0\main_uart_phy_source_last[0:0] 1'0 + assign $0\tx_fifo_sink_last[0:0] 1'0 sync always - update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] + update \tx_fifo_sink_last $0\tx_fifo_sink_last[0:0] sync init end - attribute \src "ls180.v:959.11-959.51" - process $proc$ls180.v:959$3468 + attribute \src "ls180.v:915.5-915.28" + process $proc$ls180.v:915$1911 assign { } { } - assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 + assign $1\tx_fifo_readable[0:0] 1'0 sync always sync init - update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] + update \tx_fifo_readable $1\tx_fifo_readable[0:0] end - attribute \src "ls180.v:960.5-960.39" - process $proc$ls180.v:960$3469 + attribute \src "ls180.v:922.11-922.32" + process $proc$ls180.v:922$1912 assign { } { } - assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 + assign $1\tx_fifo_level0[4:0] 5'00000 sync always sync init - update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] + update \tx_fifo_level0 $1\tx_fifo_level0[4:0] end - attribute \src "ls180.v:961.12-961.54" - process $proc$ls180.v:961$3470 + attribute \src "ls180.v:923.5-923.27" + process $proc$ls180.v:923$1913 assign { } { } - assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 + assign $0\tx_fifo_replace[0:0] 1'0 sync always + update \tx_fifo_replace $0\tx_fifo_replace[0:0] sync init - update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] end - attribute \src "ls180.v:963.5-963.30" - process $proc$ls180.v:963$3471 + attribute \src "ls180.v:924.11-924.33" + process $proc$ls180.v:924$1914 assign { } { } - assign $1\main_uart_phy_rx_r[0:0] 1'0 + assign $1\tx_fifo_produce[3:0] 4'0000 sync always sync init - update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] + update \tx_fifo_produce $1\tx_fifo_produce[3:0] end - attribute \src "ls180.v:964.11-964.38" - process $proc$ls180.v:964$3472 + attribute \src "ls180.v:925.11-925.33" + process $proc$ls180.v:925$1915 assign { } { } - assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 + assign $1\tx_fifo_consume[3:0] 4'0000 sync always sync init - update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] + update \tx_fifo_consume $1\tx_fifo_consume[3:0] end - attribute \src "ls180.v:965.11-965.43" - process $proc$ls180.v:965$3473 + attribute \src "ls180.v:926.11-926.36" + process $proc$ls180.v:926$1916 assign { } { } - assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 + assign $1\tx_fifo_wrport_adr[3:0] 4'0000 sync always sync init - update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] + update \tx_fifo_wrport_adr $1\tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:966.5-966.33" - process $proc$ls180.v:966$3474 + attribute \src "ls180.v:952.5-952.28" + process $proc$ls180.v:952$1917 assign { } { } - assign $1\main_uart_phy_rx_busy[0:0] 1'0 + assign $1\rx_fifo_readable[0:0] 1'0 sync always sync init - update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] + update \rx_fifo_readable $1\rx_fifo_readable[0:0] end - attribute \src "ls180.v:97.12-97.58" - process $proc$ls180.v:97$3144 + attribute \src "ls180.v:959.11-959.32" + process $proc$ls180.v:959$1918 assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + assign $1\rx_fifo_level0[4:0] 5'00000 sync always sync init - update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + update \rx_fifo_level0 $1\rx_fifo_level0[4:0] end - attribute \src "ls180.v:977.5-977.32" - process $proc$ls180.v:977$3475 + attribute \src "ls180.v:960.5-960.27" + process $proc$ls180.v:960$1919 assign { } { } - assign $1\main_uart_tx_pending[0:0] 1'0 + assign $0\rx_fifo_replace[0:0] 1'0 sync always + update \rx_fifo_replace $0\rx_fifo_replace[0:0] sync init - update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] end - attribute \src "ls180.v:979.5-979.30" - process $proc$ls180.v:979$3476 + attribute \src "ls180.v:961.11-961.33" + process $proc$ls180.v:961$1920 assign { } { } - assign $1\main_uart_tx_clear[0:0] 1'0 + assign $1\rx_fifo_produce[3:0] 4'0000 sync always sync init - update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] + update \rx_fifo_produce $1\rx_fifo_produce[3:0] end - attribute \src "ls180.v:98.12-98.60" - process $proc$ls180.v:98$3145 + attribute \src "ls180.v:962.11-962.33" + process $proc$ls180.v:962$1921 assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + assign $1\rx_fifo_consume[3:0] 4'0000 sync always sync init - update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + update \rx_fifo_consume $1\rx_fifo_consume[3:0] end - attribute \src "ls180.v:980.5-980.36" - process $proc$ls180.v:980$3477 + attribute \src "ls180.v:963.11-963.36" + process $proc$ls180.v:963$1922 assign { } { } - assign $1\main_uart_tx_old_trigger[0:0] 1'0 + assign $1\rx_fifo_wrport_adr[3:0] 4'0000 sync always sync init - update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] + update \rx_fifo_wrport_adr $1\rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:982.5-982.32" - process $proc$ls180.v:982$3478 + attribute \src "ls180.v:978.5-978.17" + process $proc$ls180.v:978$1923 assign { } { } - assign $1\main_uart_rx_pending[0:0] 1'0 + assign $0\reset[0:0] 1'0 sync always + update \reset $0\reset[0:0] sync init - update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] end - attribute \src "ls180.v:984.5-984.30" - process $proc$ls180.v:984$3479 + attribute \src "ls180.v:979.11-979.34" + process $proc$ls180.v:979$1924 assign { } { } - assign $1\main_uart_rx_clear[0:0] 1'0 + assign $1\gpio0_oe_storage[7:0] 8'00000000 sync always sync init - update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] + update \gpio0_oe_storage $1\gpio0_oe_storage[7:0] end - attribute \src "ls180.v:985.5-985.36" - process $proc$ls180.v:985$3480 + attribute \src "ls180.v:980.5-980.23" + process $proc$ls180.v:980$1925 assign { } { } - assign $1\main_uart_rx_old_trigger[0:0] 1'0 + assign $1\gpio0_oe_re[0:0] 1'0 sync always sync init - update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] + update \gpio0_oe_re $1\gpio0_oe_re[0:0] end - attribute \src "ls180.v:989.11-989.49" - process $proc$ls180.v:989$3481 + attribute \src "ls180.v:981.11-981.30" + process $proc$ls180.v:981$1926 assign { } { } - assign $1\main_uart_eventmanager_status_w[1:0] 2'00 + assign $1\gpio0_status[7:0] 8'00000000 sync always sync init - update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] + update \gpio0_status $1\gpio0_status[7:0] end - attribute \src "ls180.v:993.11-993.50" - process $proc$ls180.v:993$3482 + attribute \src "ls180.v:983.11-983.35" + process $proc$ls180.v:983$1927 assign { } { } - assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 + assign $1\gpio0_out_storage[7:0] 8'00000000 sync always sync init - update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] + update \gpio0_out_storage $1\gpio0_out_storage[7:0] end - attribute \src "ls180.v:994.11-994.48" - process $proc$ls180.v:994$3483 + attribute \src "ls180.v:984.5-984.24" + process $proc$ls180.v:984$1928 assign { } { } - assign $1\main_uart_eventmanager_storage[1:0] 2'00 + assign $1\gpio0_out_re[0:0] 1'0 sync always sync init - update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] + update \gpio0_out_re $1\gpio0_out_re[0:0] end - attribute \src "ls180.v:995.5-995.37" - process $proc$ls180.v:995$3484 + attribute \src "ls180.v:985.11-985.35" + process $proc$ls180.v:985$1929 assign { } { } - assign $1\main_uart_eventmanager_re[0:0] 1'0 + assign $1\gpio0_pads_gpio0i[7:0] 8'00000000 sync always sync init - update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] + update \gpio0_pads_gpio0i $1\gpio0_pads_gpio0i[7:0] end - connect \main_libresocsim_libresoc_reset \main_libresocsim_reset - connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i - connect \sys_pll_18_o \main_libresocsim_libresoc_pll_18_o - connect \sys_pll_lck_o \main_libresocsim_libresoc_pll_lck_o - connect \main_libresocsim_libresoc_jtag_tck \jtag_tck - connect \main_libresocsim_libresoc_jtag_tms \jtag_tms - connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi - connect \jtag_tdo \main_libresocsim_libresoc_jtag_tdo - connect \main_nc \nc - connect \main_sdblock2mem_sink_sink_valid0 \main_sdcore_source_source_valid - connect \main_sdcore_source_source_ready \main_sdblock2mem_sink_sink_ready0 - connect \main_sdblock2mem_sink_sink_first \main_sdcore_source_source_first - connect \main_sdblock2mem_sink_sink_last \main_sdcore_source_source_last - connect \main_sdblock2mem_sink_sink_payload_data0 \main_sdcore_source_source_payload_data - connect \main_sdcore_sink_sink_valid \main_sdmem2block_source_source_valid0 - connect \main_sdmem2block_source_source_ready0 \main_sdcore_sink_sink_ready - connect \main_sdcore_sink_sink_first \main_sdmem2block_source_source_first0 - connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 - connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 - connect \main_libresocsim_bus_error \builder_error - connect \main_converter0_reset $not$ls180.v:2893$50_Y - connect \main_interface0_converted_interface_dat_r { \main_libresocsim_libresoc_xics_icp_dat_r \main_converter0_dat_r [63:32] } - connect \main_converter1_reset $not$ls180.v:2953$61_Y - connect \main_interface1_converted_interface_dat_r { \main_libresocsim_libresoc_xics_ics_dat_r \main_converter1_dat_r [63:32] } - connect \main_socbushandler_reset $not$ls180.v:3013$72_Y - connect \main_socbushandler_converted_interface_dat_r { \main_wb_sdram_dat_r \main_socbushandler_dat_r [63:32] } - connect \main_libresocsim_reset \main_libresocsim_reset_re - connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors - connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [5:0] - connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r - connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w - connect \main_libresocsim_zero_trigger $ne$ls180.v:3089$108_Y - connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status - connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending - connect \main_libresocsim_irq $and$ls180.v:3098$111_Y - connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger - connect \main_sram0_adr \main_interface0_ram_bus_adr [5:0] - connect \main_interface0_ram_bus_dat_r \main_sram0_dat_r - connect \main_sram0_dat_w \main_interface0_ram_bus_dat_w - connect \main_sram1_adr \main_interface1_ram_bus_adr [5:0] - connect \main_interface1_ram_bus_dat_r \main_sram1_dat_r - connect \main_sram1_dat_w \main_interface1_ram_bus_dat_w - connect \main_sram2_adr \main_interface2_ram_bus_adr [5:0] - connect \main_interface2_ram_bus_dat_r \main_sram2_dat_r - connect \main_sram2_dat_w \main_interface2_ram_bus_dat_w - connect \main_sram3_adr \main_interface3_ram_bus_adr [5:0] - connect \main_interface3_ram_bus_dat_r \main_sram3_dat_r - connect \main_sram3_dat_w \main_interface3_ram_bus_dat_w + attribute \src "ls180.v:986.11-986.35" + process $proc$ls180.v:986$1930 + assign { } { } + assign $1\gpio0_pads_gpio0o[7:0] 8'00000000 + sync always + sync init + update \gpio0_pads_gpio0o $1\gpio0_pads_gpio0o[7:0] + end + attribute \src "ls180.v:987.11-987.36" + process $proc$ls180.v:987$1931 + assign { } { } + assign $1\gpio0_pads_gpio0oe[7:0] 8'00000000 + sync always + sync init + update \gpio0_pads_gpio0oe $1\gpio0_pads_gpio0oe[7:0] + end + attribute \src "ls180.v:988.11-988.34" + process $proc$ls180.v:988$1932 + assign { } { } + assign $1\gpio1_oe_storage[7:0] 8'00000000 + sync always + sync init + update \gpio1_oe_storage $1\gpio1_oe_storage[7:0] + end + attribute \src "ls180.v:989.5-989.23" + process $proc$ls180.v:989$1933 + assign { } { } + assign $1\gpio1_oe_re[0:0] 1'0 + sync always + sync init + update \gpio1_oe_re $1\gpio1_oe_re[0:0] + end + attribute \src "ls180.v:990.11-990.30" + process $proc$ls180.v:990$1934 + assign { } { } + assign $1\gpio1_status[7:0] 8'00000000 + sync always + sync init + update \gpio1_status $1\gpio1_status[7:0] + end + attribute \src "ls180.v:992.11-992.35" + process $proc$ls180.v:992$1935 + assign { } { } + assign $1\gpio1_out_storage[7:0] 8'00000000 + sync always + sync init + update \gpio1_out_storage $1\gpio1_out_storage[7:0] + end + attribute \src "ls180.v:993.5-993.24" + process $proc$ls180.v:993$1936 + assign { } { } + assign $1\gpio1_out_re[0:0] 1'0 + sync always + sync init + update \gpio1_out_re $1\gpio1_out_re[0:0] + end + attribute \src "ls180.v:994.11-994.35" + process $proc$ls180.v:994$1937 + assign { } { } + assign $1\gpio1_pads_gpio1i[7:0] 8'00000000 + sync always + sync init + update \gpio1_pads_gpio1i $1\gpio1_pads_gpio1i[7:0] + end + attribute \src "ls180.v:995.11-995.35" + process $proc$ls180.v:995$1938 + assign { } { } + assign $1\gpio1_pads_gpio1o[7:0] 8'00000000 + sync always + sync init + update \gpio1_pads_gpio1o $1\gpio1_pads_gpio1o[7:0] + end + attribute \src "ls180.v:996.11-996.36" + process $proc$ls180.v:996$1939 + assign { } { } + assign $1\gpio1_pads_gpio1oe[7:0] 8'00000000 + sync always + sync init + update \gpio1_pads_gpio1oe $1\gpio1_pads_gpio1oe[7:0] + end + attribute \src "ls180.v:997.11-997.26" + process $proc$ls180.v:997$1940 + assign { } { } + assign $1\eint_tmp[2:0] 3'000 + sync always + sync init + update \eint_tmp $1\eint_tmp[2:0] + end + attribute \src "ls180.v:999.12-999.25" + process $proc$ls180.v:999$1941 + assign { } { } + assign $1\dummy[35:0] 36'000000000000000000000000000000000000 + sync always + sync init + update \dummy $1\dummy[35:0] + end + connect \libresocsim_libresoc_reset \libresocsim_reset + connect \libresocsim_libresoc_clk_sel \sys_clksel_i + connect \sys_pll_18_o \libresocsim_libresoc_pll_18_o + connect \sys_pll_lck_o \libresocsim_libresoc_pll_lck_o + connect \libresocsim_libresoc_jtag_tck \jtag_tck + connect \libresocsim_libresoc_jtag_tms \jtag_tms + connect \libresocsim_libresoc_jtag_tdi \jtag_tdi + connect \jtag_tdo \libresocsim_libresoc_jtag_tdo + connect \nc_1 \nc + connect \libresocsim_bus_error \libresocsim_error + connect \libresocsim_converter0_reset $not$ls180.v:1519$17_Y + connect \libresocsim_libresoc_ibus_dat_r { \libresocsim_interface0_converted_interface_dat_r \libresocsim_converter0_dat_r [63:32] } + connect \libresocsim_converter1_reset $not$ls180.v:1579$28_Y + connect \libresocsim_libresoc_dbus_dat_r { \libresocsim_interface1_converted_interface_dat_r \libresocsim_converter1_dat_r [63:32] } + connect \libresocsim_converter2_reset $not$ls180.v:1639$39_Y + connect \libresocsim_libresoc_jtag_wb_dat_r { \libresocsim_interface2_converted_interface_dat_r \libresocsim_converter2_dat_r [63:32] } + connect \libresocsim_reset \libresocsim_reset_re + connect \libresocsim_bus_errors_status \libresocsim_bus_errors + connect \libresocsim_adr \libresocsim_ram_bus_adr [6:0] + connect \libresocsim_ram_bus_dat_r \libresocsim_dat_r + connect \libresocsim_dat_w \libresocsim_ram_bus_dat_w + connect \libresocsim_zero_trigger $ne$ls180.v:1711$63_Y + connect \libresocsim_eventmanager_status_w \libresocsim_zero_status + connect \libresocsim_eventmanager_pending_w \libresocsim_zero_pending + connect \libresocsim_irq $and$ls180.v:1720$66_Y + connect \libresocsim_zero_status \libresocsim_zero_trigger + connect \ram_adr \ram_bus_ram_bus_adr [4:0] + connect \ram_bus_ram_bus_dat_r \ram_dat_r + connect \ram_dat_w \ram_bus_ram_bus_dat_w connect \sys_clk_1 \sys_clk connect \por_clk \sys_clk - connect \sys_rst_1 \main_int_rst - connect \main_dfi_p0_address \main_sdram_master_p0_address - connect \main_dfi_p0_bank \main_sdram_master_p0_bank - connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n - connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n - connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n - connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n - connect \main_dfi_p0_cke \main_sdram_master_p0_cke - connect \main_dfi_p0_odt \main_sdram_master_p0_odt - connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n - connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n - connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata - connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en - connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask - connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en - connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata - connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid - connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address - connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank - connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n - connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n - connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n - connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n - connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke - connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt - connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n - connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n - connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata - connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en - connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask - connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en - connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata - connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid - connect \main_sdram_inti_p0_cke \main_sdram_cke - connect \main_sdram_inti_p0_odt \main_sdram_odt - connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n - connect \main_sdram_inti_p0_address \main_sdram_address_storage - connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage - connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3268$218_Y - connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3269$219_Y - connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage - connect \main_sdram_inti_p0_wrdata_mask 2'00 - connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid - connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready - connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we - connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr - connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock - connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready - connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid - connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid - connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready - connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we - connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr - connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock - connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready - connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid - connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid - connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready - connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we - connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr - connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock - connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready - connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid - connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid - connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready - connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we - connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr - connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock - connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready - connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid - connect \main_sdram_timer_wait $not$ls180.v:3300$220_Y - connect \main_sdram_postponer_req_i \main_sdram_timer_done0 - connect \main_sdram_wants_refresh \main_sdram_postponer_req_o - connect \main_sdram_timer_done1 $eq$ls180.v:3303$221_Y - connect \main_sdram_timer_done0 \main_sdram_timer_done1 - connect \main_sdram_timer_count0 \main_sdram_timer_count1 - connect \main_sdram_sequencer_start1 $or$ls180.v:3306$223_Y - connect \main_sdram_sequencer_done0 $and$ls180.v:3307$225_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid - connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr - connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready - connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3349$227_Y - connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3350$228_Y - connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3351$229_Y - connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 - connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3361$234_Y - connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3362$236_Y - connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3363$238_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3395$246_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3396$247_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3399$248_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3400$249_Y - connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3401$251_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid - connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr - connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready - connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3506$257_Y - connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3507$258_Y - connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3508$259_Y - connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 - connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3518$264_Y - connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3519$266_Y - connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3520$268_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3552$276_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3553$277_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3556$278_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3557$279_Y - connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3558$281_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid - connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr - connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready - connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3663$287_Y - connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3664$288_Y - connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3665$289_Y - connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 - connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3675$294_Y - connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3676$296_Y - connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3677$298_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3709$306_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3710$307_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3713$308_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3714$309_Y - connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3715$311_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid - connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr - connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready - connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3820$317_Y - connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3821$318_Y - connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3822$319_Y - connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 - connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3832$324_Y - connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3833$326_Y - connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3834$328_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3866$336_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3867$337_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3870$338_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3871$339_Y - connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3872$341_Y - connect \main_sdram_choose_req_want_cmds 1'1 - connect \main_sdram_trrdcon_valid $and$ls180.v:3968$352_Y - connect \main_sdram_tfawcon_valid $and$ls180.v:3969$358_Y - connect \main_sdram_ras_allowed $and$ls180.v:3970$359_Y - connect \main_sdram_tccdcon_valid $and$ls180.v:3971$362_Y - connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready - connect \main_sdram_twtrcon_valid $and$ls180.v:3973$364_Y - connect \main_sdram_read_available $or$ls180.v:3974$371_Y - connect \main_sdram_write_available $or$ls180.v:3975$378_Y - connect \main_sdram_max_time0 $eq$ls180.v:3976$379_Y - connect \main_sdram_max_time1 $eq$ls180.v:3977$380_Y - connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid - connect \main_sdram_go_to_refresh $and$ls180.v:3982$383_Y - connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata - connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata - connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3985$384_Y - connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids - connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 - connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 - connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 - connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 - connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 - connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 - connect \main_sdram_choose_cmd_ce $or$ls180.v:4018$442_Y - connect \main_sdram_choose_req_request \main_sdram_choose_req_valids - connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 - connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 - connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 - connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 - connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 - connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 - connect \main_sdram_choose_req_ce $or$ls180.v:4087$528_Y - connect \main_sdram_dfi_p0_reset_n 1'1 - connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 - connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 - connect \builder_roundrobin0_request $and$ls180.v:4164$560_Y - connect \builder_roundrobin0_ce $and$ls180.v:4165$563_Y - connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 - connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 - connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 - connect \builder_roundrobin1_request $and$ls180.v:4169$576_Y - connect \builder_roundrobin1_ce $and$ls180.v:4170$579_Y - connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 - connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 - connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 - connect \builder_roundrobin2_request $and$ls180.v:4174$592_Y - connect \builder_roundrobin2_ce $and$ls180.v:4175$595_Y - connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 - connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 - connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 - connect \builder_roundrobin3_request $and$ls180.v:4179$608_Y - connect \builder_roundrobin3_ce $and$ls180.v:4180$611_Y - connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 - connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 - connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 - connect \main_port_cmd_ready $or$ls180.v:4184$675_Y - connect \main_port_wdata_ready \builder_new_master_wdata_ready - connect \main_port_rdata_valid \builder_new_master_rdata_valid3 - connect \main_port_rdata_payload_data \main_sdram_interface_rdata - connect \builder_roundrobin0_grant 1'0 - connect \builder_roundrobin1_grant 1'0 - connect \builder_roundrobin2_grant 1'0 - connect \builder_roundrobin3_grant 1'0 - connect \main_converter_reset $not$ls180.v:4206$677_Y - connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } - connect \main_port_cmd_payload_addr $sub$ls180.v:4266$688_Y [23:0] - connect \main_port_cmd_payload_we \main_litedram_wb_we - connect \main_port_wdata_payload_data \main_litedram_wb_dat_w - connect \main_port_wdata_payload_we \main_litedram_wb_sel - connect \main_litedram_wb_dat_r \main_port_rdata_payload_data - connect \main_port_flush $not$ls180.v:4271$689_Y - connect \main_port_cmd_last $not$ls180.v:4272$690_Y - connect \main_port_cmd_valid $and$ls180.v:4273$693_Y - connect \main_port_wdata_valid $and$ls180.v:4274$697_Y - connect \main_port_rdata_ready $and$ls180.v:4275$700_Y - connect \main_litedram_wb_ack $and$ls180.v:4276$705_Y - connect \main_ack_cmd $or$ls180.v:4277$707_Y - connect \main_ack_wdata $or$ls180.v:4278$709_Y - connect \main_ack_rdata $and$ls180.v:4279$710_Y - connect \main_uart_uart_sink_valid \main_uart_phy_source_valid - connect \main_uart_phy_source_ready \main_uart_uart_sink_ready - connect \main_uart_uart_sink_first \main_uart_phy_source_first - connect \main_uart_uart_sink_last \main_uart_phy_source_last - connect \main_uart_uart_sink_payload_data \main_uart_phy_source_payload_data - connect \main_uart_phy_sink_valid \main_uart_uart_source_valid - connect \main_uart_uart_source_ready \main_uart_phy_sink_ready - connect \main_uart_phy_sink_first \main_uart_uart_source_first - connect \main_uart_phy_sink_last \main_uart_uart_source_last - connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data - connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re - connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r - connect \main_uart_txfull_status $not$ls180.v:4292$711_Y - connect \main_uart_txempty_status $not$ls180.v:4293$712_Y - connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid - connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready - connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first - connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last - connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data - connect \main_uart_tx_trigger $not$ls180.v:4299$713_Y - connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid - connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready - connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first - connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last - connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data - connect \main_uart_rxempty_status $not$ls180.v:4305$714_Y - connect \main_uart_rxfull_status $not$ls180.v:4306$715_Y - connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data - connect \main_uart_rx_fifo_source_ready $or$ls180.v:4308$717_Y - connect \main_uart_rx_trigger $not$ls180.v:4309$718_Y - connect \main_uart_irq $or$ls180.v:4332$727_Y - connect \main_uart_tx_status \main_uart_tx_trigger - connect \main_uart_rx_status \main_uart_rx_trigger - connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } - connect { \main_uart_tx_fifo_fifo_out_last \main_uart_tx_fifo_fifo_out_first \main_uart_tx_fifo_fifo_out_payload_data } \main_uart_tx_fifo_syncfifo_dout - connect \main_uart_tx_fifo_sink_ready \main_uart_tx_fifo_syncfifo_writable - connect \main_uart_tx_fifo_syncfifo_we \main_uart_tx_fifo_sink_valid - connect \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_sink_first - connect \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_sink_last - connect \main_uart_tx_fifo_fifo_in_payload_data \main_uart_tx_fifo_sink_payload_data - connect \main_uart_tx_fifo_source_valid \main_uart_tx_fifo_readable - connect \main_uart_tx_fifo_source_first \main_uart_tx_fifo_fifo_out_first - connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last - connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data - connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready - connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4347$730_Y - connect \main_uart_tx_fifo_level1 $add$ls180.v:4348$731_Y - connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din - connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4358$735_Y - connect \main_uart_tx_fifo_do_read $and$ls180.v:4359$736_Y - connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume - connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r - connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read - connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4363$737_Y - connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4364$738_Y - connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } - connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout - connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable - connect \main_uart_rx_fifo_syncfifo_we \main_uart_rx_fifo_sink_valid - connect \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_sink_first - connect \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_sink_last - connect \main_uart_rx_fifo_fifo_in_payload_data \main_uart_rx_fifo_sink_payload_data - connect \main_uart_rx_fifo_source_valid \main_uart_rx_fifo_readable - connect \main_uart_rx_fifo_source_first \main_uart_rx_fifo_fifo_out_first - connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last - connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data - connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready - connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4377$741_Y - connect \main_uart_rx_fifo_level1 $add$ls180.v:4378$742_Y - connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din - connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4388$746_Y - connect \main_uart_rx_fifo_do_read $and$ls180.v:4389$747_Y - connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume - connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r - connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read - connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4393$748_Y - connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4394$749_Y - connect \main_gpiotristateasic0_pads_i \gpio_i - connect \main_gpiotristateasic0_pads_oe \main_gpiotristateasic0_oe_storage - connect \main_gpiotristateasic0_pads_o \main_gpiotristateasic0_out_storage - connect \main_gpiotristateasic1_pads_i \gpio_i - connect \main_gpiotristateasic1_pads_oe \main_gpiotristateasic1_oe_storage - connect \main_gpiotristateasic1_pads_o \main_gpiotristateasic1_out_storage - connect \main_spimaster0_start \main_spimaster9_start - connect \main_spimaster1_length \main_spimaster10_length - connect \main_spimaster4_mosi \main_spimaster16_storage - connect \main_spimaster13_done \main_spimaster2_done - connect \main_spimaster18_status \main_spimaster5_miso - connect \main_spimaster6_cs \main_spimaster21_storage - connect \main_spimaster7_loopback \main_spimaster23_storage - connect \main_spimaster31_clk_rise $eq$ls180.v:4418$753_Y - connect \main_spimaster32_clk_fall $eq$ls180.v:4419$755_Y - connect \main_spisdcard_start0 \main_spisdcard_start1 - connect \main_spisdcard_length0 \main_spisdcard_length1 - connect \main_spisdcard_mosi \main_spisdcard_mosi_storage - connect \main_spisdcard_done1 \main_spisdcard_done0 - connect \main_spisdcard_miso_status \main_spisdcard_miso - connect \main_spisdcard_cs \main_spisdcard_cs_storage - connect \main_spisdcard_loopback \main_spisdcard_loopback_storage - connect \main_spisdcard_clk_rise $eq$ls180.v:4476$761_Y - connect \main_spisdcard_clk_fall $eq$ls180.v:4477$763_Y - connect \main_spisdcard_clk_divider0 \main_spimaster1_storage - connect \i2c_scl \main_i2c_scl - connect \i2c_sda_oe \main_i2c_oe - connect \i2c_sda_o \main_i2c_sda0 - connect \main_i2c_sda1 \i2c_sda_i - connect \main_sdphy_status 1'0 - connect \main_sdphy_sdpads_clk $or$ls180.v:4533$771_Y - connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4534$775_Y - connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4535$779_Y - connect \main_sdphy_sdpads_data_oe $or$ls180.v:4536$783_Y - connect \main_sdphy_sdpads_data_o $or$ls180.v:4537$787_Y - connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_dataw_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_datar_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_init_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_init_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_init_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_cmdw_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_cmdw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_cmdw_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_cmdr_pads_in_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_cmdr_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_dataw_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_dataw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_dataw_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_clocker_stop $or$ls180.v:4558$788_Y - connect \main_sdphy_clocker_ce $and$ls180.v:4588$791_Y - connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid - connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready - connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first - connect \main_sdphy_cmdr_cmdr_pads_in_last \main_sdphy_cmdr_pads_in_pads_in_last - connect \main_sdphy_cmdr_cmdr_pads_in_payload_clk \main_sdphy_cmdr_pads_in_pads_in_payload_clk - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4711$801_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4712$803_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 - connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready - connect \main_sdphy_cmdr_cmdr_buf_sink_first \main_sdphy_cmdr_cmdr_source_source_first1 - connect \main_sdphy_cmdr_cmdr_buf_sink_last \main_sdphy_cmdr_cmdr_source_source_last1 - connect \main_sdphy_cmdr_cmdr_buf_sink_payload_data \main_sdphy_cmdr_cmdr_source_source_payload_data1 - connect \main_sdphy_cmdr_cmdr_source_source_valid0 \main_sdphy_cmdr_cmdr_buf_source_valid - connect \main_sdphy_cmdr_cmdr_buf_source_ready \main_sdphy_cmdr_cmdr_source_source_ready0 - connect \main_sdphy_cmdr_cmdr_source_source_first0 \main_sdphy_cmdr_cmdr_buf_source_first - connect \main_sdphy_cmdr_cmdr_source_source_last0 \main_sdphy_cmdr_cmdr_buf_source_last - connect \main_sdphy_cmdr_cmdr_source_source_payload_data0 \main_sdphy_cmdr_cmdr_buf_source_payload_data - connect \main_sdphy_cmdr_cmdr_source_source_valid1 \main_sdphy_cmdr_cmdr_converter_source_valid - connect \main_sdphy_cmdr_cmdr_converter_source_ready \main_sdphy_cmdr_cmdr_source_source_ready1 - connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first - connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last - connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data - connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4729$805_Y - connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4731$806_Y - connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4732$808_Y - connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid - connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready - connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first - connect \main_sdphy_dataw_crcr_pads_in_last \main_sdphy_dataw_pads_in_pads_in_last - connect \main_sdphy_dataw_crcr_pads_in_payload_clk \main_sdphy_dataw_pads_in_pads_in_payload_clk - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_i \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_o \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i - connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o - connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4838$823_Y - connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4839$824_Y - connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] - connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 - connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready - connect \main_sdphy_dataw_crcr_buf_sink_first \main_sdphy_dataw_crcr_source_source_first1 - connect \main_sdphy_dataw_crcr_buf_sink_last \main_sdphy_dataw_crcr_source_source_last1 - connect \main_sdphy_dataw_crcr_buf_sink_payload_data \main_sdphy_dataw_crcr_source_source_payload_data1 - connect \main_sdphy_dataw_crcr_source_source_valid0 \main_sdphy_dataw_crcr_buf_source_valid - connect \main_sdphy_dataw_crcr_buf_source_ready \main_sdphy_dataw_crcr_source_source_ready0 - connect \main_sdphy_dataw_crcr_source_source_first0 \main_sdphy_dataw_crcr_buf_source_first - connect \main_sdphy_dataw_crcr_source_source_last0 \main_sdphy_dataw_crcr_buf_source_last - connect \main_sdphy_dataw_crcr_source_source_payload_data0 \main_sdphy_dataw_crcr_buf_source_payload_data - connect \main_sdphy_dataw_crcr_source_source_valid1 \main_sdphy_dataw_crcr_converter_source_valid - connect \main_sdphy_dataw_crcr_converter_source_ready \main_sdphy_dataw_crcr_source_source_ready1 - connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first - connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last - connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data - connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4856$826_Y - connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all - connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4858$827_Y - connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4859$829_Y - connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid - connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready - connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first - connect \main_sdphy_datar_datar_pads_in_last \main_sdphy_datar_pads_in_pads_in_last - connect \main_sdphy_datar_datar_pads_in_payload_clk \main_sdphy_datar_pads_in_pads_in_payload_clk - connect \main_sdphy_datar_datar_pads_in_payload_cmd_i \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_datar_datar_pads_in_payload_cmd_o \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_datar_datar_pads_in_payload_cmd_oe \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i - connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o - connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe - connect \main_sdphy_datar_datar_start $eq$ls180.v:4972$838_Y - connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4973$839_Y - connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i - connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 - connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready - connect \main_sdphy_datar_datar_buf_sink_first \main_sdphy_datar_datar_source_source_first1 - connect \main_sdphy_datar_datar_buf_sink_last \main_sdphy_datar_datar_source_source_last1 - connect \main_sdphy_datar_datar_buf_sink_payload_data \main_sdphy_datar_datar_source_source_payload_data1 - connect \main_sdphy_datar_datar_source_source_valid0 \main_sdphy_datar_datar_buf_source_valid - connect \main_sdphy_datar_datar_buf_source_ready \main_sdphy_datar_datar_source_source_ready0 - connect \main_sdphy_datar_datar_source_source_first0 \main_sdphy_datar_datar_buf_source_first - connect \main_sdphy_datar_datar_source_source_last0 \main_sdphy_datar_datar_buf_source_last - connect \main_sdphy_datar_datar_source_source_payload_data0 \main_sdphy_datar_datar_buf_source_payload_data - connect \main_sdphy_datar_datar_source_source_valid1 \main_sdphy_datar_datar_converter_source_valid - connect \main_sdphy_datar_datar_converter_source_ready \main_sdphy_datar_datar_source_source_ready1 - connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first - connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last - connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data - connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4990$841_Y - connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all - connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4992$842_Y - connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4993$844_Y - connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid - connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready - connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first - connect \main_sdcore_crc16_inserter_sink_last \main_sdcore_sink_sink_last - connect \main_sdcore_crc16_inserter_sink_payload_data \main_sdcore_sink_sink_payload_data - connect \main_sdcore_source_source_valid \main_sdcore_crc16_checker_source_valid - connect \main_sdcore_crc16_checker_source_ready \main_sdcore_source_source_ready - connect \main_sdcore_source_source_first \main_sdcore_crc16_checker_source_first - connect \main_sdcore_source_source_last \main_sdcore_crc16_checker_source_last - connect \main_sdcore_source_source_payload_data \main_sdcore_crc16_checker_source_payload_data - connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] - connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] - connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } - connect \main_sdcore_data_event_status { $not$ls180.v:5109$859_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } - connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } - connect \main_sdcore_crc7_inserter_clr 1'1 - connect \main_sdcore_crc7_inserter_enable 1'1 - connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:5113$862_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:5113$860_Y } - connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:5114$865_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:5114$863_Y } - connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:5115$868_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:5115$866_Y } - connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:5116$871_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:5116$869_Y } - connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:5117$874_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:5117$872_Y } - connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:5118$877_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:5118$875_Y } - connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:5119$880_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:5119$878_Y } - connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:5120$883_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:5120$881_Y } - connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:5121$886_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:5121$884_Y } - connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:5122$889_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:5122$887_Y } - connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:5123$892_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:5123$890_Y } - connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:5124$895_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:5124$893_Y } - connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:5125$898_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:5125$896_Y } - connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:5126$901_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:5126$899_Y } - connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:5127$904_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:5127$902_Y } - connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:5128$907_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:5128$905_Y } - connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:5129$910_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:5129$908_Y } - connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:5130$913_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:5130$911_Y } - connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5131$916_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5131$914_Y } - connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5132$919_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5132$917_Y } - connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5133$922_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5133$920_Y } - connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5134$925_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5134$923_Y } - connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5135$928_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5135$926_Y } - connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5136$931_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5136$929_Y } - connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5137$934_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5137$932_Y } - connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5138$937_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5138$935_Y } - connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5139$940_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5139$938_Y } - connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5140$943_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5140$941_Y } - connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5141$946_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5141$944_Y } - connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5142$949_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5142$947_Y } - connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5143$952_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5143$950_Y } - connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5144$955_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5144$953_Y } - connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5145$958_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5145$956_Y } - connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5146$961_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5146$959_Y } - connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5147$964_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5147$962_Y } - connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5148$967_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5148$965_Y } - connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5149$970_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5149$968_Y } - connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5150$973_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5150$971_Y } - connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5151$976_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5151$974_Y } - connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5152$979_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5152$977_Y } - connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } - connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5162$982_Y - connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5163$983_Y - connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } - connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5165$985_Y - connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5166$986_Y - connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } - connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5168$988_Y - connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5169$989_Y - connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } - connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5171$991_Y - connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5172$992_Y - connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5173$997_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5173$995_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5173$993_Y } - connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5174$1002_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5174$1000_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5174$998_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5183$1008_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5183$1006_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5183$1004_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5184$1013_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5184$1011_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5184$1009_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5193$1019_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5193$1017_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5193$1015_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5194$1024_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5194$1022_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5194$1020_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5203$1030_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5203$1028_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5203$1026_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5204$1035_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5204$1033_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5204$1031_Y } - connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } - connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5300$1051_Y - connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } - connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5310$1054_Y - connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } - connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5320$1057_Y - connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } - connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5330$1060_Y - connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val - connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last - connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5355$1072_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5355$1070_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5355$1068_Y } - connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5356$1077_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5356$1075_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5356$1073_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5365$1083_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5365$1081_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5365$1079_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5366$1088_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5366$1086_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5366$1084_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5375$1094_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5375$1092_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5375$1090_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5376$1099_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5376$1097_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5376$1095_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5385$1105_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5385$1103_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5385$1101_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5386$1110_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5386$1108_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5386$1106_Y } - connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 - connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready - connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first - connect \main_sdblock2mem_fifo_sink_last \main_sdblock2mem_sink_sink_last - connect \main_sdblock2mem_fifo_sink_payload_data \main_sdblock2mem_sink_sink_payload_data0 - connect \main_sdblock2mem_converter_sink_valid \main_sdblock2mem_fifo_source_valid - connect \main_sdblock2mem_fifo_source_ready \main_sdblock2mem_converter_sink_ready - connect \main_sdblock2mem_converter_sink_first \main_sdblock2mem_fifo_source_first - connect \main_sdblock2mem_converter_sink_last \main_sdblock2mem_fifo_source_last - connect \main_sdblock2mem_converter_sink_payload_data \main_sdblock2mem_fifo_source_payload_data - connect \main_sdblock2mem_wishbonedmawriter_sink_valid \main_sdblock2mem_source_source_valid - connect \main_sdblock2mem_source_source_ready \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \main_sdblock2mem_wishbonedmawriter_sink_first \main_sdblock2mem_source_source_first - connect \main_sdblock2mem_wishbonedmawriter_sink_last \main_sdblock2mem_source_source_last - connect \main_sdblock2mem_wishbonedmawriter_sink_payload_data \main_sdblock2mem_source_source_payload_data - connect \main_sdblock2mem_fifo_syncfifo_din { \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_fifo_in_payload_data } - connect { \main_sdblock2mem_fifo_fifo_out_last \main_sdblock2mem_fifo_fifo_out_first \main_sdblock2mem_fifo_fifo_out_payload_data } \main_sdblock2mem_fifo_syncfifo_dout - connect \main_sdblock2mem_fifo_sink_ready \main_sdblock2mem_fifo_syncfifo_writable - connect \main_sdblock2mem_fifo_syncfifo_we \main_sdblock2mem_fifo_sink_valid - connect \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_sink_first - connect \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_sink_last - connect \main_sdblock2mem_fifo_fifo_in_payload_data \main_sdblock2mem_fifo_sink_payload_data - connect \main_sdblock2mem_fifo_source_valid \main_sdblock2mem_fifo_syncfifo_readable - connect \main_sdblock2mem_fifo_source_first \main_sdblock2mem_fifo_fifo_out_first - connect \main_sdblock2mem_fifo_source_last \main_sdblock2mem_fifo_fifo_out_last - connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data - connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready - connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din - connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5622$1140_Y - connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5623$1141_Y - connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume - connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r - connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5626$1142_Y - connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5627$1143_Y - connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid - connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready - connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first - connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last - connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data - connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5633$1145_Y - connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all - connect \main_sdblock2mem_converter_load_part $and$ls180.v:5635$1146_Y - connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 - connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 - connect \main_interface0_bus_we 1'1 - connect \main_interface0_bus_sel 8'11111111 - connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address - connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] \main_sdblock2mem_sink_sink_payload_data1 [39:32] \main_sdblock2mem_sink_sink_payload_data1 [47:40] \main_sdblock2mem_sink_sink_payload_data1 [55:48] \main_sdblock2mem_sink_sink_payload_data1 [63:56] } - connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack - connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [34:3] - connect \main_sdblock2mem_wishbonedmawriter_length { 3'000 \main_sdblock2mem_wishbonedmawriter_length_storage [31:3] } - connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5645$1147_Y - connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid - connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready - connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first - connect \main_sdmem2block_converter_sink_last \main_sdmem2block_dma_source_last - connect \main_sdmem2block_converter_sink_payload_data \main_sdmem2block_dma_source_payload_data - connect \main_sdmem2block_fifo_sink_valid \main_sdmem2block_source_source_valid1 - connect \main_sdmem2block_source_source_ready1 \main_sdmem2block_fifo_sink_ready - connect \main_sdmem2block_fifo_sink_first \main_sdmem2block_source_source_first1 - connect \main_sdmem2block_fifo_sink_last \main_sdmem2block_source_source_last1 - connect \main_sdmem2block_fifo_sink_payload_data \main_sdmem2block_source_source_payload_data1 - connect \main_sdmem2block_source_source_valid0 \main_sdmem2block_fifo_source_valid - connect \main_sdmem2block_fifo_source_ready \main_sdmem2block_source_source_ready0 - connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first - connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last - connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data - connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [34:3] - connect \main_sdmem2block_dma_length { 3'000 \main_sdmem2block_dma_length_storage [31:3] } - connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset - connect \main_sdmem2block_dma_reset $not$ls180.v:5704$1154_Y - connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid - connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 - connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first - connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last - connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data - connect \main_sdmem2block_converter_first $eq$ls180.v:5785$1162_Y - connect \main_sdmem2block_converter_last $eq$ls180.v:5786$1163_Y - connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid - connect \main_sdmem2block_converter_source_first $and$ls180.v:5788$1164_Y - connect \main_sdmem2block_converter_source_last $and$ls180.v:5789$1165_Y - connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5790$1166_Y - connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last - connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } - connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout - connect \main_sdmem2block_fifo_sink_ready \main_sdmem2block_fifo_syncfifo_writable - connect \main_sdmem2block_fifo_syncfifo_we \main_sdmem2block_fifo_sink_valid - connect \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_sink_first - connect \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_sink_last - connect \main_sdmem2block_fifo_fifo_in_payload_data \main_sdmem2block_fifo_sink_payload_data - connect \main_sdmem2block_fifo_source_valid \main_sdmem2block_fifo_syncfifo_readable - connect \main_sdmem2block_fifo_source_first \main_sdmem2block_fifo_fifo_out_first - connect \main_sdmem2block_fifo_source_last \main_sdmem2block_fifo_fifo_out_last - connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data - connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready - connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din - connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5842$1171_Y - connect \main_sdmem2block_fifo_do_read $and$ls180.v:5843$1172_Y - connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume - connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r - connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5846$1173_Y - connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5847$1174_Y - connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] - connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 [31:0] - connect \builder_shared_sel \builder_comb_rhs_array_muxed26 [3:0] - connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 - connect \builder_shared_stb \builder_comb_rhs_array_muxed28 - connect \builder_shared_we \builder_comb_rhs_array_muxed29 - connect \builder_shared_cti \builder_comb_rhs_array_muxed30 - connect \builder_shared_bte \builder_comb_rhs_array_muxed31 - connect \main_libresocsim_libresoc_ibus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_libresocsim_libresoc_dbus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_libresocsim_libresoc_jtag_wb_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_interface0_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_interface1_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_libresocsim_libresoc_ibus_ack $and$ls180.v:5898$1180_Y - connect \main_libresocsim_libresoc_dbus_ack $and$ls180.v:5899$1182_Y - connect \main_libresocsim_libresoc_jtag_wb_ack $and$ls180.v:5900$1184_Y - connect \main_interface0_bus_ack $and$ls180.v:5901$1186_Y - connect \main_interface1_bus_ack $and$ls180.v:5902$1188_Y - connect \main_libresocsim_libresoc_ibus_err $and$ls180.v:5903$1190_Y - connect \main_libresocsim_libresoc_dbus_err $and$ls180.v:5904$1192_Y - connect \main_libresocsim_libresoc_jtag_wb_err $and$ls180.v:5905$1194_Y - connect \main_interface0_bus_err $and$ls180.v:5906$1196_Y - connect \main_interface1_bus_err $and$ls180.v:5907$1198_Y - connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_libresoc_jtag_wb_cyc \main_libresocsim_libresoc_dbus_cyc \main_libresocsim_libresoc_ibus_cyc } - connect \main_libresocsim_ram_bus_adr \builder_shared_adr - connect \main_libresocsim_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_ram_bus_stb \builder_shared_stb - connect \main_libresocsim_ram_bus_we \builder_shared_we - connect \main_libresocsim_ram_bus_cti \builder_shared_cti - connect \main_libresocsim_ram_bus_bte \builder_shared_bte - connect \main_interface0_ram_bus_adr \builder_shared_adr - connect \main_interface0_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface0_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_interface0_ram_bus_stb \builder_shared_stb - connect \main_interface0_ram_bus_we \builder_shared_we - connect \main_interface0_ram_bus_cti \builder_shared_cti - connect \main_interface0_ram_bus_bte \builder_shared_bte - connect \main_interface1_ram_bus_adr \builder_shared_adr - connect \main_interface1_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface1_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_interface1_ram_bus_stb \builder_shared_stb - connect \main_interface1_ram_bus_we \builder_shared_we - connect \main_interface1_ram_bus_cti \builder_shared_cti - connect \main_interface1_ram_bus_bte \builder_shared_bte - connect \main_interface2_ram_bus_adr \builder_shared_adr - connect \main_interface2_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface2_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_interface2_ram_bus_stb \builder_shared_stb - connect \main_interface2_ram_bus_we \builder_shared_we - connect \main_interface2_ram_bus_cti \builder_shared_cti - connect \main_interface2_ram_bus_bte \builder_shared_bte - connect \main_interface3_ram_bus_adr \builder_shared_adr - connect \main_interface3_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface3_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_interface3_ram_bus_stb \builder_shared_stb - connect \main_interface3_ram_bus_we \builder_shared_we - connect \main_interface3_ram_bus_cti \builder_shared_cti - connect \main_interface3_ram_bus_bte \builder_shared_bte - connect \main_interface0_converted_interface_adr \builder_shared_adr - connect \main_interface0_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface0_converted_interface_sel { 4'0000 \builder_shared_sel } - connect \main_interface0_converted_interface_stb \builder_shared_stb - connect \main_interface0_converted_interface_we \builder_shared_we - connect \main_interface0_converted_interface_cti \builder_shared_cti - connect \main_interface0_converted_interface_bte \builder_shared_bte - connect \main_interface1_converted_interface_adr \builder_shared_adr - connect \main_interface1_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface1_converted_interface_sel { 4'0000 \builder_shared_sel } - connect \main_interface1_converted_interface_stb \builder_shared_stb - connect \main_interface1_converted_interface_we \builder_shared_we - connect \main_interface1_converted_interface_cti \builder_shared_cti - connect \main_interface1_converted_interface_bte \builder_shared_bte - connect \main_libresocsim_libresoc_interface0_adr \builder_shared_adr [28:0] - connect \main_libresocsim_libresoc_interface0_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_libresoc_interface0_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_libresoc_interface0_stb \builder_shared_stb - connect \main_libresocsim_libresoc_interface0_we \builder_shared_we - connect \main_libresocsim_libresoc_interface0_cti \builder_shared_cti - connect \main_libresocsim_libresoc_interface0_bte \builder_shared_bte - connect \main_libresocsim_libresoc_interface1_adr \builder_shared_adr [28:0] - connect \main_libresocsim_libresoc_interface1_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_libresoc_interface1_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_libresoc_interface1_stb \builder_shared_stb - connect \main_libresocsim_libresoc_interface1_we \builder_shared_we - connect \main_libresocsim_libresoc_interface1_cti \builder_shared_cti - connect \main_libresocsim_libresoc_interface1_bte \builder_shared_bte - connect \main_libresocsim_libresoc_interface2_adr \builder_shared_adr [28:0] - connect \main_libresocsim_libresoc_interface2_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_libresoc_interface2_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_libresoc_interface2_stb \builder_shared_stb - connect \main_libresocsim_libresoc_interface2_we \builder_shared_we - connect \main_libresocsim_libresoc_interface2_cti \builder_shared_cti - connect \main_libresocsim_libresoc_interface2_bte \builder_shared_bte - connect \main_libresocsim_libresoc_interface3_adr \builder_shared_adr [28:0] - connect \main_libresocsim_libresoc_interface3_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_libresoc_interface3_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_libresoc_interface3_stb \builder_shared_stb - connect \main_libresocsim_libresoc_interface3_we \builder_shared_we - connect \main_libresocsim_libresoc_interface3_cti \builder_shared_cti - connect \main_libresocsim_libresoc_interface3_bte \builder_shared_bte - connect \main_socbushandler_converted_interface_adr \builder_shared_adr - connect \main_socbushandler_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_socbushandler_converted_interface_sel { 4'0000 \builder_shared_sel } - connect \main_socbushandler_converted_interface_stb \builder_shared_stb - connect \main_socbushandler_converted_interface_we \builder_shared_we - connect \main_socbushandler_converted_interface_cti \builder_shared_cti - connect \main_socbushandler_converted_interface_bte \builder_shared_bte - connect \builder_libresocsim_converted_interface_adr \builder_shared_adr - connect \builder_libresocsim_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \builder_libresocsim_converted_interface_sel { 4'0000 \builder_shared_sel } - connect \builder_libresocsim_converted_interface_stb \builder_shared_stb - connect \builder_libresocsim_converted_interface_we \builder_shared_we - connect \builder_libresocsim_converted_interface_cti \builder_shared_cti - connect \builder_libresocsim_converted_interface_bte \builder_shared_bte - connect \main_libresocsim_ram_bus_cyc $and$ls180.v:6016$1213_Y - connect \main_interface0_ram_bus_cyc $and$ls180.v:6017$1214_Y - connect \main_interface1_ram_bus_cyc $and$ls180.v:6018$1215_Y - connect \main_interface2_ram_bus_cyc $and$ls180.v:6019$1216_Y - connect \main_interface3_ram_bus_cyc $and$ls180.v:6020$1217_Y - connect \main_interface0_converted_interface_cyc $and$ls180.v:6021$1218_Y - connect \main_interface1_converted_interface_cyc $and$ls180.v:6022$1219_Y - connect \main_libresocsim_libresoc_interface0_cyc $and$ls180.v:6023$1220_Y - connect \main_libresocsim_libresoc_interface1_cyc $and$ls180.v:6024$1221_Y - connect \main_libresocsim_libresoc_interface2_cyc $and$ls180.v:6025$1222_Y - connect \main_libresocsim_libresoc_interface3_cyc $and$ls180.v:6026$1223_Y - connect \main_socbushandler_converted_interface_cyc $and$ls180.v:6027$1224_Y - connect \builder_libresocsim_converted_interface_cyc $and$ls180.v:6028$1225_Y - connect \builder_shared_err $or$ls180.v:6029$1237_Y - connect \builder_wait $and$ls180.v:6030$1240_Y - connect \builder_done $eq$ls180.v:6043$1279_Y - connect \builder_csrbank0_sel $eq$ls180.v:6044$1280_Y - connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] - connect \builder_csrbank0_reset0_re $and$ls180.v:6046$1283_Y - connect \builder_csrbank0_reset0_we $and$ls180.v:6047$1287_Y - connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch3_re $and$ls180.v:6049$1290_Y - connect \builder_csrbank0_scratch3_we $and$ls180.v:6050$1294_Y - connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch2_re $and$ls180.v:6052$1297_Y - connect \builder_csrbank0_scratch2_we $and$ls180.v:6053$1301_Y - connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch1_re $and$ls180.v:6055$1304_Y - connect \builder_csrbank0_scratch1_we $and$ls180.v:6056$1308_Y - connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch0_re $and$ls180.v:6058$1311_Y - connect \builder_csrbank0_scratch0_we $and$ls180.v:6059$1315_Y - connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors3_re $and$ls180.v:6061$1318_Y - connect \builder_csrbank0_bus_errors3_we $and$ls180.v:6062$1322_Y - connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors2_re $and$ls180.v:6064$1325_Y - connect \builder_csrbank0_bus_errors2_we $and$ls180.v:6065$1329_Y - connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors1_re $and$ls180.v:6067$1332_Y - connect \builder_csrbank0_bus_errors1_we $and$ls180.v:6068$1336_Y - connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors0_re $and$ls180.v:6070$1339_Y - connect \builder_csrbank0_bus_errors0_we $and$ls180.v:6071$1343_Y - connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage - connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] - connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] - connect \builder_csrbank0_scratch1_w \main_libresocsim_scratch_storage [15:8] - connect \builder_csrbank0_scratch0_w \main_libresocsim_scratch_storage [7:0] - connect \builder_csrbank0_bus_errors3_w \main_libresocsim_bus_errors_status [31:24] - connect \builder_csrbank0_bus_errors2_w \main_libresocsim_bus_errors_status [23:16] - connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] - connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] - connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we - connect \builder_csrbank1_sel $eq$ls180.v:6082$1344_Y - connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe1_re $and$ls180.v:6084$1347_Y - connect \builder_csrbank1_oe1_we $and$ls180.v:6085$1351_Y - connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe0_re $and$ls180.v:6087$1354_Y - connect \builder_csrbank1_oe0_we $and$ls180.v:6088$1358_Y - connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in1_re $and$ls180.v:6090$1361_Y - connect \builder_csrbank1_in1_we $and$ls180.v:6091$1365_Y - connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in0_re $and$ls180.v:6093$1368_Y - connect \builder_csrbank1_in0_we $and$ls180.v:6094$1372_Y - connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out1_re $and$ls180.v:6096$1375_Y - connect \builder_csrbank1_out1_we $and$ls180.v:6097$1379_Y - connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out0_re $and$ls180.v:6099$1382_Y - connect \builder_csrbank1_out0_we $and$ls180.v:6100$1386_Y - connect \builder_csrbank1_oe1_w \main_gpiotristateasic1_oe_storage [15:8] - connect \builder_csrbank1_oe0_w \main_gpiotristateasic1_oe_storage [7:0] - connect \builder_csrbank1_in1_w \main_gpiotristateasic1_status [15:8] - connect \builder_csrbank1_in0_w \main_gpiotristateasic1_status [7:0] - connect \main_gpiotristateasic1_we \builder_csrbank1_in0_we - connect \builder_csrbank1_out1_w \main_gpiotristateasic1_out_storage [15:8] - connect \builder_csrbank1_out0_w \main_gpiotristateasic1_out_storage [7:0] - connect \builder_csrbank2_sel $eq$ls180.v:6108$1387_Y - connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] - connect \builder_csrbank2_w0_re $and$ls180.v:6110$1390_Y - connect \builder_csrbank2_w0_we $and$ls180.v:6111$1394_Y - connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] - connect \builder_csrbank2_r_re $and$ls180.v:6113$1397_Y - connect \builder_csrbank2_r_we $and$ls180.v:6114$1401_Y - connect \main_i2c_scl \main_i2c_storage [0] - connect \main_i2c_oe \main_i2c_storage [1] - connect \main_i2c_sda0 \main_i2c_storage [2] - connect \builder_csrbank2_w0_w \main_i2c_storage - connect \main_i2c_status \main_i2c_sda1 - connect \builder_csrbank2_r_w \main_i2c_status - connect \main_i2c_we \builder_csrbank2_r_we - connect \builder_csrbank3_sel $eq$ls180.v:6122$1402_Y - connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_enable0_re $and$ls180.v:6124$1405_Y - connect \builder_csrbank3_enable0_we $and$ls180.v:6125$1409_Y - connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width3_re $and$ls180.v:6127$1412_Y - connect \builder_csrbank3_width3_we $and$ls180.v:6128$1416_Y - connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width2_re $and$ls180.v:6130$1419_Y - connect \builder_csrbank3_width2_we $and$ls180.v:6131$1423_Y - connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width1_re $and$ls180.v:6133$1426_Y - connect \builder_csrbank3_width1_we $and$ls180.v:6134$1430_Y - connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width0_re $and$ls180.v:6136$1433_Y - connect \builder_csrbank3_width0_we $and$ls180.v:6137$1437_Y - connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period3_re $and$ls180.v:6139$1440_Y - connect \builder_csrbank3_period3_we $and$ls180.v:6140$1444_Y - connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period2_re $and$ls180.v:6142$1447_Y - connect \builder_csrbank3_period2_we $and$ls180.v:6143$1451_Y - connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period1_re $and$ls180.v:6145$1454_Y - connect \builder_csrbank3_period1_we $and$ls180.v:6146$1458_Y - connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period0_re $and$ls180.v:6148$1461_Y - connect \builder_csrbank3_period0_we $and$ls180.v:6149$1465_Y - connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage - connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] - connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] - connect \builder_csrbank3_width1_w \main_pwm0_width_storage [15:8] - connect \builder_csrbank3_width0_w \main_pwm0_width_storage [7:0] - connect \builder_csrbank3_period3_w \main_pwm0_period_storage [31:24] - connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] - connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] - connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] - connect \builder_csrbank4_sel $eq$ls180.v:6159$1466_Y - connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_enable0_re $and$ls180.v:6161$1469_Y - connect \builder_csrbank4_enable0_we $and$ls180.v:6162$1473_Y - connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width3_re $and$ls180.v:6164$1476_Y - connect \builder_csrbank4_width3_we $and$ls180.v:6165$1480_Y - connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width2_re $and$ls180.v:6167$1483_Y - connect \builder_csrbank4_width2_we $and$ls180.v:6168$1487_Y - connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width1_re $and$ls180.v:6170$1490_Y - connect \builder_csrbank4_width1_we $and$ls180.v:6171$1494_Y - connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width0_re $and$ls180.v:6173$1497_Y - connect \builder_csrbank4_width0_we $and$ls180.v:6174$1501_Y - connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period3_re $and$ls180.v:6176$1504_Y - connect \builder_csrbank4_period3_we $and$ls180.v:6177$1508_Y - connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period2_re $and$ls180.v:6179$1511_Y - connect \builder_csrbank4_period2_we $and$ls180.v:6180$1515_Y - connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period1_re $and$ls180.v:6182$1518_Y - connect \builder_csrbank4_period1_we $and$ls180.v:6183$1522_Y - connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period0_re $and$ls180.v:6185$1525_Y - connect \builder_csrbank4_period0_we $and$ls180.v:6186$1529_Y - connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage - connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] - connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] - connect \builder_csrbank4_width1_w \main_pwm1_width_storage [15:8] - connect \builder_csrbank4_width0_w \main_pwm1_width_storage [7:0] - connect \builder_csrbank4_period3_w \main_pwm1_period_storage [31:24] - connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] - connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] - connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] - connect \builder_csrbank5_sel $eq$ls180.v:6196$1530_Y - connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base7_re $and$ls180.v:6198$1533_Y - connect \builder_csrbank5_dma_base7_we $and$ls180.v:6199$1537_Y - connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base6_re $and$ls180.v:6201$1540_Y - connect \builder_csrbank5_dma_base6_we $and$ls180.v:6202$1544_Y - connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base5_re $and$ls180.v:6204$1547_Y - connect \builder_csrbank5_dma_base5_we $and$ls180.v:6205$1551_Y - connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base4_re $and$ls180.v:6207$1554_Y - connect \builder_csrbank5_dma_base4_we $and$ls180.v:6208$1558_Y - connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base3_re $and$ls180.v:6210$1561_Y - connect \builder_csrbank5_dma_base3_we $and$ls180.v:6211$1565_Y - connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base2_re $and$ls180.v:6213$1568_Y - connect \builder_csrbank5_dma_base2_we $and$ls180.v:6214$1572_Y - connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base1_re $and$ls180.v:6216$1575_Y - connect \builder_csrbank5_dma_base1_we $and$ls180.v:6217$1579_Y - connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base0_re $and$ls180.v:6219$1582_Y - connect \builder_csrbank5_dma_base0_we $and$ls180.v:6220$1586_Y - connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length3_re $and$ls180.v:6222$1589_Y - connect \builder_csrbank5_dma_length3_we $and$ls180.v:6223$1593_Y - connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length2_re $and$ls180.v:6225$1596_Y - connect \builder_csrbank5_dma_length2_we $and$ls180.v:6226$1600_Y - connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length1_re $and$ls180.v:6228$1603_Y - connect \builder_csrbank5_dma_length1_we $and$ls180.v:6229$1607_Y - connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length0_re $and$ls180.v:6231$1610_Y - connect \builder_csrbank5_dma_length0_we $and$ls180.v:6232$1614_Y - connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6234$1617_Y - connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6235$1621_Y - connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_done_re $and$ls180.v:6237$1624_Y - connect \builder_csrbank5_dma_done_we $and$ls180.v:6238$1628_Y - connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6240$1631_Y - connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6241$1635_Y - connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] - connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] - connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] - connect \builder_csrbank5_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] - connect \builder_csrbank5_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] - connect \builder_csrbank5_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] - connect \builder_csrbank5_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] - connect \builder_csrbank5_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] - connect \builder_csrbank5_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] - connect \builder_csrbank5_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] - connect \builder_csrbank5_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] - connect \builder_csrbank5_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] - connect \builder_csrbank5_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status - connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we - connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage - connect \builder_csrbank6_sel $eq$ls180.v:6258$1636_Y - connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6260$1639_Y - connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6261$1643_Y - connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6263$1646_Y - connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6264$1650_Y - connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6266$1653_Y - connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6267$1657_Y - connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6269$1660_Y - connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6270$1664_Y - connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6272$1667_Y - connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6273$1671_Y - connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6275$1674_Y - connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6276$1678_Y - connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6278$1681_Y - connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6279$1685_Y - connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6281$1688_Y - connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6282$1692_Y - connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] - connect \main_sdcore_cmd_send_re $and$ls180.v:6284$1695_Y - connect \main_sdcore_cmd_send_we $and$ls180.v:6285$1699_Y - connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6287$1702_Y - connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6288$1706_Y - connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6290$1709_Y - connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6291$1713_Y - connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6293$1716_Y - connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6294$1720_Y - connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6296$1723_Y - connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6297$1727_Y - connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6299$1730_Y - connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6300$1734_Y - connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6302$1737_Y - connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6303$1741_Y - connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6305$1744_Y - connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6306$1748_Y - connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6308$1751_Y - connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6309$1755_Y - connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6311$1758_Y - connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6312$1762_Y - connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6314$1765_Y - connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6315$1769_Y - connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6317$1772_Y - connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6318$1776_Y - connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6320$1779_Y - connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6321$1783_Y - connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6323$1786_Y - connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6324$1790_Y - connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6326$1793_Y - connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6327$1797_Y - connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6329$1800_Y - connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6330$1804_Y - connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6332$1807_Y - connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6333$1811_Y - connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_cmd_event_re $and$ls180.v:6335$1814_Y - connect \builder_csrbank6_cmd_event_we $and$ls180.v:6336$1818_Y - connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_data_event_re $and$ls180.v:6338$1821_Y - connect \builder_csrbank6_data_event_we $and$ls180.v:6339$1825_Y - connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] - connect \builder_csrbank6_block_length1_re $and$ls180.v:6341$1828_Y - connect \builder_csrbank6_block_length1_we $and$ls180.v:6342$1832_Y - connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_length0_re $and$ls180.v:6344$1835_Y - connect \builder_csrbank6_block_length0_we $and$ls180.v:6345$1839_Y - connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count3_re $and$ls180.v:6347$1842_Y - connect \builder_csrbank6_block_count3_we $and$ls180.v:6348$1846_Y - connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count2_re $and$ls180.v:6350$1849_Y - connect \builder_csrbank6_block_count2_we $and$ls180.v:6351$1853_Y - connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count1_re $and$ls180.v:6353$1856_Y - connect \builder_csrbank6_block_count1_we $and$ls180.v:6354$1860_Y - connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count0_re $and$ls180.v:6356$1863_Y - connect \builder_csrbank6_block_count0_we $and$ls180.v:6357$1867_Y - connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] - connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] - connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] - connect \builder_csrbank6_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] - connect \builder_csrbank6_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] - connect \builder_csrbank6_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] - connect \builder_csrbank6_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] - connect \builder_csrbank6_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] - connect \builder_csrbank6_cmd_response15_w \main_sdcore_cmd_response_status [127:120] - connect \builder_csrbank6_cmd_response14_w \main_sdcore_cmd_response_status [119:112] - connect \builder_csrbank6_cmd_response13_w \main_sdcore_cmd_response_status [111:104] - connect \builder_csrbank6_cmd_response12_w \main_sdcore_cmd_response_status [103:96] - connect \builder_csrbank6_cmd_response11_w \main_sdcore_cmd_response_status [95:88] - connect \builder_csrbank6_cmd_response10_w \main_sdcore_cmd_response_status [87:80] - connect \builder_csrbank6_cmd_response9_w \main_sdcore_cmd_response_status [79:72] - connect \builder_csrbank6_cmd_response8_w \main_sdcore_cmd_response_status [71:64] - connect \builder_csrbank6_cmd_response7_w \main_sdcore_cmd_response_status [63:56] - connect \builder_csrbank6_cmd_response6_w \main_sdcore_cmd_response_status [55:48] - connect \builder_csrbank6_cmd_response5_w \main_sdcore_cmd_response_status [47:40] - connect \builder_csrbank6_cmd_response4_w \main_sdcore_cmd_response_status [39:32] - connect \builder_csrbank6_cmd_response3_w \main_sdcore_cmd_response_status [31:24] - connect \builder_csrbank6_cmd_response2_w \main_sdcore_cmd_response_status [23:16] - connect \builder_csrbank6_cmd_response1_w \main_sdcore_cmd_response_status [15:8] - connect \builder_csrbank6_cmd_response0_w \main_sdcore_cmd_response_status [7:0] - connect \main_sdcore_cmd_response_we \builder_csrbank6_cmd_response0_we - connect \builder_csrbank6_cmd_event_w \main_sdcore_cmd_event_status - connect \main_sdcore_cmd_event_we \builder_csrbank6_cmd_event_we - connect \builder_csrbank6_data_event_w \main_sdcore_data_event_status - connect \main_sdcore_data_event_we \builder_csrbank6_data_event_we - connect \builder_csrbank6_block_length1_w \main_sdcore_block_length_storage [9:8] - connect \builder_csrbank6_block_length0_w \main_sdcore_block_length_storage [7:0] - connect \builder_csrbank6_block_count3_w \main_sdcore_block_count_storage [31:24] - connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] - connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] - connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] - connect \builder_csrbank7_sel $eq$ls180.v:6393$1868_Y - connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base7_re $and$ls180.v:6395$1871_Y - connect \builder_csrbank7_dma_base7_we $and$ls180.v:6396$1875_Y - connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base6_re $and$ls180.v:6398$1878_Y - connect \builder_csrbank7_dma_base6_we $and$ls180.v:6399$1882_Y - connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base5_re $and$ls180.v:6401$1885_Y - connect \builder_csrbank7_dma_base5_we $and$ls180.v:6402$1889_Y - connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base4_re $and$ls180.v:6404$1892_Y - connect \builder_csrbank7_dma_base4_we $and$ls180.v:6405$1896_Y - connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base3_re $and$ls180.v:6407$1899_Y - connect \builder_csrbank7_dma_base3_we $and$ls180.v:6408$1903_Y - connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base2_re $and$ls180.v:6410$1906_Y - connect \builder_csrbank7_dma_base2_we $and$ls180.v:6411$1910_Y - connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base1_re $and$ls180.v:6413$1913_Y - connect \builder_csrbank7_dma_base1_we $and$ls180.v:6414$1917_Y - connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base0_re $and$ls180.v:6416$1920_Y - connect \builder_csrbank7_dma_base0_we $and$ls180.v:6417$1924_Y - connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length3_re $and$ls180.v:6419$1927_Y - connect \builder_csrbank7_dma_length3_we $and$ls180.v:6420$1931_Y - connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length2_re $and$ls180.v:6422$1934_Y - connect \builder_csrbank7_dma_length2_we $and$ls180.v:6423$1938_Y - connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length1_re $and$ls180.v:6425$1941_Y - connect \builder_csrbank7_dma_length1_we $and$ls180.v:6426$1945_Y - connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length0_re $and$ls180.v:6428$1948_Y - connect \builder_csrbank7_dma_length0_we $and$ls180.v:6429$1952_Y - connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6431$1955_Y - connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6432$1959_Y - connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_done_re $and$ls180.v:6434$1962_Y - connect \builder_csrbank7_dma_done_we $and$ls180.v:6435$1966_Y - connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6437$1969_Y - connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6438$1973_Y - connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6440$1976_Y - connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6441$1980_Y - connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6443$1983_Y - connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6444$1987_Y - connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6446$1990_Y - connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6447$1994_Y - connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6449$1997_Y - connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6450$2001_Y - connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] - connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] - connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] - connect \builder_csrbank7_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] - connect \builder_csrbank7_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] - connect \builder_csrbank7_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] - connect \builder_csrbank7_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] - connect \builder_csrbank7_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] - connect \builder_csrbank7_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] - connect \builder_csrbank7_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] - connect \builder_csrbank7_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] - connect \builder_csrbank7_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] - connect \builder_csrbank7_dma_enable0_w \main_sdmem2block_dma_enable_storage - connect \builder_csrbank7_dma_done_w \main_sdmem2block_dma_done_status - connect \main_sdmem2block_dma_done_we \builder_csrbank7_dma_done_we - connect \builder_csrbank7_dma_loop0_w \main_sdmem2block_dma_loop_storage - connect \builder_csrbank7_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] - connect \builder_csrbank7_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] - connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] - connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] - connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we - connect \builder_csrbank8_sel $eq$ls180.v:6472$2002_Y - connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_card_detect_re $and$ls180.v:6474$2005_Y - connect \builder_csrbank8_card_detect_we $and$ls180.v:6475$2009_Y - connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6477$2012_Y - connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6478$2016_Y - connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6480$2019_Y - connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6481$2023_Y - connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] - connect \main_sdphy_init_initialize_re $and$ls180.v:6483$2026_Y - connect \main_sdphy_init_initialize_we $and$ls180.v:6484$2030_Y - connect \builder_csrbank8_card_detect_w \main_sdphy_status - connect \main_sdphy_we \builder_csrbank8_card_detect_we - connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] - connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] - connect \builder_csrbank9_sel $eq$ls180.v:6489$2031_Y - connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] - connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6491$2034_Y - connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6492$2038_Y - connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] - connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6494$2041_Y - connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6495$2045_Y - connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] - connect \main_sdram_command_issue_re $and$ls180.v:6497$2048_Y - connect \main_sdram_command_issue_we $and$ls180.v:6498$2052_Y - connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] - connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6500$2055_Y - connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6501$2059_Y - connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6503$2062_Y - connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6504$2066_Y - connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] - connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6506$2069_Y - connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6507$2073_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6509$2076_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6510$2080_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6512$2083_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6513$2087_Y - connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6515$2090_Y - connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6516$2094_Y - connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6518$2097_Y - connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6519$2101_Y - connect \main_sdram_sel \main_sdram_storage [0] - connect \main_sdram_cke \main_sdram_storage [1] - connect \main_sdram_odt \main_sdram_storage [2] - connect \main_sdram_reset_n \main_sdram_storage [3] - connect \builder_csrbank9_dfii_control0_w \main_sdram_storage - connect \builder_csrbank9_dfii_pi0_command0_w \main_sdram_command_storage - connect \builder_csrbank9_dfii_pi0_address1_w \main_sdram_address_storage [12:8] - connect \builder_csrbank9_dfii_pi0_address0_w \main_sdram_address_storage [7:0] - connect \builder_csrbank9_dfii_pi0_baddress0_w \main_sdram_baddress_storage - connect \builder_csrbank9_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] - connect \builder_csrbank9_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] - connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] - connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] - connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we - connect \builder_csrbank10_sel $eq$ls180.v:6534$2102_Y - connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control1_re $and$ls180.v:6536$2105_Y - connect \builder_csrbank10_control1_we $and$ls180.v:6537$2109_Y - connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control0_re $and$ls180.v:6539$2112_Y - connect \builder_csrbank10_control0_we $and$ls180.v:6540$2116_Y - connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_status_re $and$ls180.v:6542$2119_Y - connect \builder_csrbank10_status_we $and$ls180.v:6543$2123_Y - connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_mosi0_re $and$ls180.v:6545$2126_Y - connect \builder_csrbank10_mosi0_we $and$ls180.v:6546$2130_Y - connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_miso_re $and$ls180.v:6548$2133_Y - connect \builder_csrbank10_miso_we $and$ls180.v:6549$2137_Y - connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_cs0_re $and$ls180.v:6551$2140_Y - connect \builder_csrbank10_cs0_we $and$ls180.v:6552$2144_Y - connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_loopback0_re $and$ls180.v:6554$2147_Y - connect \builder_csrbank10_loopback0_we $and$ls180.v:6555$2151_Y - connect \main_spimaster10_length \main_spimaster11_storage [15:8] - connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] - connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] - connect \main_spimaster14_status \main_spimaster13_done - connect \builder_csrbank10_status_w \main_spimaster14_status - connect \main_spimaster15_we \builder_csrbank10_status_we - connect \builder_csrbank10_mosi0_w \main_spimaster16_storage - connect \builder_csrbank10_miso_w \main_spimaster18_status - connect \main_spimaster19_we \builder_csrbank10_miso_we - connect \main_spimaster20_sel \main_spimaster21_storage - connect \builder_csrbank10_cs0_w \main_spimaster21_storage - connect \builder_csrbank10_loopback0_w \main_spimaster23_storage - connect \builder_csrbank11_sel $eq$ls180.v:6574$2153_Y - connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control1_re $and$ls180.v:6576$2156_Y - connect \builder_csrbank11_control1_we $and$ls180.v:6577$2160_Y - connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control0_re $and$ls180.v:6579$2163_Y - connect \builder_csrbank11_control0_we $and$ls180.v:6580$2167_Y - connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_status_re $and$ls180.v:6582$2170_Y - connect \builder_csrbank11_status_we $and$ls180.v:6583$2174_Y - connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_mosi0_re $and$ls180.v:6585$2177_Y - connect \builder_csrbank11_mosi0_we $and$ls180.v:6586$2181_Y - connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_miso_re $and$ls180.v:6588$2184_Y - connect \builder_csrbank11_miso_we $and$ls180.v:6589$2188_Y - connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_cs0_re $and$ls180.v:6591$2191_Y - connect \builder_csrbank11_cs0_we $and$ls180.v:6592$2195_Y - connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_loopback0_re $and$ls180.v:6594$2198_Y - connect \builder_csrbank11_loopback0_we $and$ls180.v:6595$2202_Y - connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6597$2205_Y - connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6598$2209_Y - connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6600$2212_Y - connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6601$2216_Y - connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] - connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] - connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] - connect \main_spisdcard_status_status \main_spisdcard_done1 - connect \builder_csrbank11_status_w \main_spisdcard_status_status - connect \main_spisdcard_status_we \builder_csrbank11_status_we - connect \builder_csrbank11_mosi0_w \main_spisdcard_mosi_storage - connect \builder_csrbank11_miso_w \main_spisdcard_miso_status - connect \main_spisdcard_miso_we \builder_csrbank11_miso_we - connect \main_spisdcard_sel \main_spisdcard_cs_storage - connect \builder_csrbank11_cs0_w \main_spisdcard_cs_storage - connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage - connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] - connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] - connect \builder_csrbank12_sel $eq$ls180.v:6622$2218_Y - connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load3_re $and$ls180.v:6624$2221_Y - connect \builder_csrbank12_load3_we $and$ls180.v:6625$2225_Y - connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load2_re $and$ls180.v:6627$2228_Y - connect \builder_csrbank12_load2_we $and$ls180.v:6628$2232_Y - connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load1_re $and$ls180.v:6630$2235_Y - connect \builder_csrbank12_load1_we $and$ls180.v:6631$2239_Y - connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load0_re $and$ls180.v:6633$2242_Y - connect \builder_csrbank12_load0_we $and$ls180.v:6634$2246_Y - connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload3_re $and$ls180.v:6636$2249_Y - connect \builder_csrbank12_reload3_we $and$ls180.v:6637$2253_Y - connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload2_re $and$ls180.v:6639$2256_Y - connect \builder_csrbank12_reload2_we $and$ls180.v:6640$2260_Y - connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload1_re $and$ls180.v:6642$2263_Y - connect \builder_csrbank12_reload1_we $and$ls180.v:6643$2267_Y - connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload0_re $and$ls180.v:6645$2270_Y - connect \builder_csrbank12_reload0_we $and$ls180.v:6646$2274_Y - connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_en0_re $and$ls180.v:6648$2277_Y - connect \builder_csrbank12_en0_we $and$ls180.v:6649$2281_Y - connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_update_value0_re $and$ls180.v:6651$2284_Y - connect \builder_csrbank12_update_value0_we $and$ls180.v:6652$2288_Y - connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value3_re $and$ls180.v:6654$2291_Y - connect \builder_csrbank12_value3_we $and$ls180.v:6655$2295_Y - connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value2_re $and$ls180.v:6657$2298_Y - connect \builder_csrbank12_value2_we $and$ls180.v:6658$2302_Y - connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value1_re $and$ls180.v:6660$2305_Y - connect \builder_csrbank12_value1_we $and$ls180.v:6661$2309_Y - connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value0_re $and$ls180.v:6663$2312_Y - connect \builder_csrbank12_value0_we $and$ls180.v:6664$2316_Y - connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6666$2319_Y - connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6667$2323_Y - connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6669$2326_Y - connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6670$2330_Y - connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6672$2333_Y - connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6673$2337_Y - connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] - connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] - connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] - connect \builder_csrbank12_load0_w \main_libresocsim_load_storage [7:0] - connect \builder_csrbank12_reload3_w \main_libresocsim_reload_storage [31:24] - connect \builder_csrbank12_reload2_w \main_libresocsim_reload_storage [23:16] - connect \builder_csrbank12_reload1_w \main_libresocsim_reload_storage [15:8] - connect \builder_csrbank12_reload0_w \main_libresocsim_reload_storage [7:0] - connect \builder_csrbank12_en0_w \main_libresocsim_en_storage - connect \builder_csrbank12_update_value0_w \main_libresocsim_update_value_storage - connect \builder_csrbank12_value3_w \main_libresocsim_value_status [31:24] - connect \builder_csrbank12_value2_w \main_libresocsim_value_status [23:16] - connect \builder_csrbank12_value1_w \main_libresocsim_value_status [15:8] - connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] - connect \main_libresocsim_value_we \builder_csrbank12_value0_we - connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage - connect \builder_csrbank13_sel $eq$ls180.v:6690$2338_Y - connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w - connect \main_uart_rxtx_re $and$ls180.v:6692$2341_Y - connect \main_uart_rxtx_we $and$ls180.v:6693$2345_Y - connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txfull_re $and$ls180.v:6695$2348_Y - connect \builder_csrbank13_txfull_we $and$ls180.v:6696$2352_Y - connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxempty_re $and$ls180.v:6698$2355_Y - connect \builder_csrbank13_rxempty_we $and$ls180.v:6699$2359_Y - connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_status_re $and$ls180.v:6701$2362_Y - connect \main_uart_eventmanager_status_we $and$ls180.v:6702$2366_Y - connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_pending_re $and$ls180.v:6704$2369_Y - connect \main_uart_eventmanager_pending_we $and$ls180.v:6705$2373_Y - connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] - connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6707$2376_Y - connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6708$2380_Y - connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txempty_re $and$ls180.v:6710$2383_Y - connect \builder_csrbank13_txempty_we $and$ls180.v:6711$2387_Y - connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxfull_re $and$ls180.v:6713$2390_Y - connect \builder_csrbank13_rxfull_we $and$ls180.v:6714$2394_Y - connect \builder_csrbank13_txfull_w \main_uart_txfull_status - connect \main_uart_txfull_we \builder_csrbank13_txfull_we - connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status - connect \main_uart_rxempty_we \builder_csrbank13_rxempty_we - connect \builder_csrbank13_ev_enable0_w \main_uart_eventmanager_storage - connect \builder_csrbank13_txempty_w \main_uart_txempty_status - connect \main_uart_txempty_we \builder_csrbank13_txempty_we - connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status - connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we - connect \builder_csrbank14_sel $eq$ls180.v:6724$2395_Y - connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6726$2398_Y - connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6727$2402_Y - connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6729$2405_Y - connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6730$2409_Y - connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6732$2412_Y - connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6733$2416_Y - connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6735$2419_Y - connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6736$2423_Y - connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] - connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] - connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] - connect \builder_csrbank14_tuning_word0_w \main_uart_phy_storage [7:0] - connect \builder_csr_interconnect_adr \builder_libresocsim_adr - connect \builder_csr_interconnect_we \builder_libresocsim_we - connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w - connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r - connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface14_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface14_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_csr_interconnect_dat_r $or$ls180.v:6790$2437_Y + connect \sys_rst_1 \int_rst + connect \dfi_p0_address \sdram_master_p0_address + connect \dfi_p0_bank \sdram_master_p0_bank + connect \dfi_p0_cas_n \sdram_master_p0_cas_n + connect \dfi_p0_cs_n \sdram_master_p0_cs_n + connect \dfi_p0_ras_n \sdram_master_p0_ras_n + connect \dfi_p0_we_n \sdram_master_p0_we_n + connect \dfi_p0_cke \sdram_master_p0_cke + connect \dfi_p0_odt \sdram_master_p0_odt + connect \dfi_p0_reset_n \sdram_master_p0_reset_n + connect \dfi_p0_act_n \sdram_master_p0_act_n + connect \dfi_p0_wrdata \sdram_master_p0_wrdata + connect \dfi_p0_wrdata_en \sdram_master_p0_wrdata_en + connect \dfi_p0_wrdata_mask \sdram_master_p0_wrdata_mask + connect \dfi_p0_rddata_en \sdram_master_p0_rddata_en + connect \sdram_master_p0_rddata \dfi_p0_rddata + connect \sdram_master_p0_rddata_valid \dfi_p0_rddata_valid + connect \sdram_slave_p0_address \sdram_dfi_p0_address + connect \sdram_slave_p0_bank \sdram_dfi_p0_bank + connect \sdram_slave_p0_cas_n \sdram_dfi_p0_cas_n + connect \sdram_slave_p0_cs_n \sdram_dfi_p0_cs_n + connect \sdram_slave_p0_ras_n \sdram_dfi_p0_ras_n + connect \sdram_slave_p0_we_n \sdram_dfi_p0_we_n + connect \sdram_slave_p0_cke \sdram_dfi_p0_cke + connect \sdram_slave_p0_odt \sdram_dfi_p0_odt + connect \sdram_slave_p0_reset_n \sdram_dfi_p0_reset_n + connect \sdram_slave_p0_act_n \sdram_dfi_p0_act_n + connect \sdram_slave_p0_wrdata \sdram_dfi_p0_wrdata + connect \sdram_slave_p0_wrdata_en \sdram_dfi_p0_wrdata_en + connect \sdram_slave_p0_wrdata_mask \sdram_dfi_p0_wrdata_mask + connect \sdram_slave_p0_rddata_en \sdram_dfi_p0_rddata_en + connect \sdram_dfi_p0_rddata \sdram_slave_p0_rddata + connect \sdram_dfi_p0_rddata_valid \sdram_slave_p0_rddata_valid + connect \sdram_inti_p0_cke \sdram_cke_1 + connect \sdram_inti_p0_odt \sdram_odt + connect \sdram_inti_p0_reset_n \sdram_reset_n + connect \sdram_inti_p0_address \sdram_address_storage + connect \sdram_inti_p0_bank \sdram_baddress_storage + connect \sdram_inti_p0_wrdata_en $and$ls180.v:1844$86_Y + connect \sdram_inti_p0_rddata_en $and$ls180.v:1845$87_Y + connect \sdram_inti_p0_wrdata \sdram_wrdata_storage + connect \sdram_inti_p0_wrdata_mask 2'00 + connect \sdram_bankmachine0_req_valid \sdram_interface_bank0_valid + connect \sdram_interface_bank0_ready \sdram_bankmachine0_req_ready + connect \sdram_bankmachine0_req_we \sdram_interface_bank0_we + connect \sdram_bankmachine0_req_addr \sdram_interface_bank0_addr + connect \sdram_interface_bank0_lock \sdram_bankmachine0_req_lock + connect \sdram_interface_bank0_wdata_ready \sdram_bankmachine0_req_wdata_ready + connect \sdram_interface_bank0_rdata_valid \sdram_bankmachine0_req_rdata_valid + connect \sdram_bankmachine1_req_valid \sdram_interface_bank1_valid + connect \sdram_interface_bank1_ready \sdram_bankmachine1_req_ready + connect \sdram_bankmachine1_req_we \sdram_interface_bank1_we + connect \sdram_bankmachine1_req_addr \sdram_interface_bank1_addr + connect \sdram_interface_bank1_lock \sdram_bankmachine1_req_lock + connect \sdram_interface_bank1_wdata_ready \sdram_bankmachine1_req_wdata_ready + connect \sdram_interface_bank1_rdata_valid \sdram_bankmachine1_req_rdata_valid + connect \sdram_bankmachine2_req_valid \sdram_interface_bank2_valid + connect \sdram_interface_bank2_ready \sdram_bankmachine2_req_ready + connect \sdram_bankmachine2_req_we \sdram_interface_bank2_we + connect \sdram_bankmachine2_req_addr \sdram_interface_bank2_addr + connect \sdram_interface_bank2_lock \sdram_bankmachine2_req_lock + connect \sdram_interface_bank2_wdata_ready \sdram_bankmachine2_req_wdata_ready + connect \sdram_interface_bank2_rdata_valid \sdram_bankmachine2_req_rdata_valid + connect \sdram_bankmachine3_req_valid \sdram_interface_bank3_valid + connect \sdram_interface_bank3_ready \sdram_bankmachine3_req_ready + connect \sdram_bankmachine3_req_we \sdram_interface_bank3_we + connect \sdram_bankmachine3_req_addr \sdram_interface_bank3_addr + connect \sdram_interface_bank3_lock \sdram_bankmachine3_req_lock + connect \sdram_interface_bank3_wdata_ready \sdram_bankmachine3_req_wdata_ready + connect \sdram_interface_bank3_rdata_valid \sdram_bankmachine3_req_rdata_valid + connect \sdram_timer_wait $not$ls180.v:1876$88_Y + connect \sdram_postponer_req_i \sdram_timer_done0 + connect \sdram_wants_refresh \sdram_postponer_req_o + connect \sdram_timer_done1 $eq$ls180.v:1879$89_Y + connect \sdram_timer_done0 \sdram_timer_done1 + connect \sdram_timer_count0 \sdram_timer_count1 + connect \sdram_sequencer_start1 $or$ls180.v:1882$91_Y + connect \sdram_sequencer_done0 $and$ls180.v:1883$93_Y + connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \sdram_bankmachine0_req_valid + connect \sdram_bankmachine0_req_ready \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine0_req_we + connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \sdram_bankmachine0_req_addr + connect \sdram_bankmachine0_cmd_buffer_sink_valid \sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \sdram_bankmachine0_cmd_buffer_lookahead_source_ready \sdram_bankmachine0_cmd_buffer_sink_ready + connect \sdram_bankmachine0_cmd_buffer_sink_first \sdram_bankmachine0_cmd_buffer_lookahead_source_first + connect \sdram_bankmachine0_cmd_buffer_sink_last \sdram_bankmachine0_cmd_buffer_lookahead_source_last + connect \sdram_bankmachine0_cmd_buffer_sink_payload_we \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + connect \sdram_bankmachine0_cmd_buffer_sink_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + connect \sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:1925$95_Y + connect \sdram_bankmachine0_req_lock $or$ls180.v:1926$96_Y + connect \sdram_bankmachine0_row_hit $eq$ls180.v:1927$97_Y + connect \sdram_bankmachine0_cmd_payload_ba 2'00 + connect \sdram_bankmachine0_twtpcon_valid $and$ls180.v:1937$102_Y + connect \sdram_bankmachine0_trccon_valid $and$ls180.v:1938$104_Y + connect \sdram_bankmachine0_trascon_valid $and$ls180.v:1939$106_Y + connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + connect \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine0_cmd_buffer_lookahead_sink_first + connect \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine0_cmd_buffer_lookahead_sink_last + connect \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + connect \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + connect \sdram_bankmachine0_cmd_buffer_lookahead_source_valid \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \sdram_bankmachine0_cmd_buffer_lookahead_source_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + connect \sdram_bankmachine0_cmd_buffer_lookahead_source_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + connect \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + connect \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \sdram_bankmachine0_cmd_buffer_lookahead_source_ready + connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:1971$114_Y + connect \sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:1972$115_Y + connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:1975$116_Y + connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:1976$117_Y + connect \sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:1977$119_Y + connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \sdram_bankmachine1_req_valid + connect \sdram_bankmachine1_req_ready \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine1_req_we + connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \sdram_bankmachine1_req_addr + connect \sdram_bankmachine1_cmd_buffer_sink_valid \sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \sdram_bankmachine1_cmd_buffer_lookahead_source_ready \sdram_bankmachine1_cmd_buffer_sink_ready + connect \sdram_bankmachine1_cmd_buffer_sink_first \sdram_bankmachine1_cmd_buffer_lookahead_source_first + connect \sdram_bankmachine1_cmd_buffer_sink_last \sdram_bankmachine1_cmd_buffer_lookahead_source_last + connect \sdram_bankmachine1_cmd_buffer_sink_payload_we \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + connect \sdram_bankmachine1_cmd_buffer_sink_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + connect \sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:2082$125_Y + connect \sdram_bankmachine1_req_lock $or$ls180.v:2083$126_Y + connect \sdram_bankmachine1_row_hit $eq$ls180.v:2084$127_Y + connect \sdram_bankmachine1_cmd_payload_ba 2'01 + connect \sdram_bankmachine1_twtpcon_valid $and$ls180.v:2094$132_Y + connect \sdram_bankmachine1_trccon_valid $and$ls180.v:2095$134_Y + connect \sdram_bankmachine1_trascon_valid $and$ls180.v:2096$136_Y + connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + connect \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine1_cmd_buffer_lookahead_sink_first + connect \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine1_cmd_buffer_lookahead_sink_last + connect \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + connect \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + connect \sdram_bankmachine1_cmd_buffer_lookahead_source_valid \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \sdram_bankmachine1_cmd_buffer_lookahead_source_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + connect \sdram_bankmachine1_cmd_buffer_lookahead_source_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + connect \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + connect \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \sdram_bankmachine1_cmd_buffer_lookahead_source_ready + connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:2128$144_Y + connect \sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:2129$145_Y + connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:2132$146_Y + connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:2133$147_Y + connect \sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:2134$149_Y + connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \sdram_bankmachine2_req_valid + connect \sdram_bankmachine2_req_ready \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine2_req_we + connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \sdram_bankmachine2_req_addr + connect \sdram_bankmachine2_cmd_buffer_sink_valid \sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \sdram_bankmachine2_cmd_buffer_lookahead_source_ready \sdram_bankmachine2_cmd_buffer_sink_ready + connect \sdram_bankmachine2_cmd_buffer_sink_first \sdram_bankmachine2_cmd_buffer_lookahead_source_first + connect \sdram_bankmachine2_cmd_buffer_sink_last \sdram_bankmachine2_cmd_buffer_lookahead_source_last + connect \sdram_bankmachine2_cmd_buffer_sink_payload_we \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + connect \sdram_bankmachine2_cmd_buffer_sink_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + connect \sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:2239$155_Y + connect \sdram_bankmachine2_req_lock $or$ls180.v:2240$156_Y + connect \sdram_bankmachine2_row_hit $eq$ls180.v:2241$157_Y + connect \sdram_bankmachine2_cmd_payload_ba 2'10 + connect \sdram_bankmachine2_twtpcon_valid $and$ls180.v:2251$162_Y + connect \sdram_bankmachine2_trccon_valid $and$ls180.v:2252$164_Y + connect \sdram_bankmachine2_trascon_valid $and$ls180.v:2253$166_Y + connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + connect \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine2_cmd_buffer_lookahead_sink_first + connect \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine2_cmd_buffer_lookahead_sink_last + connect \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + connect \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + connect \sdram_bankmachine2_cmd_buffer_lookahead_source_valid \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \sdram_bankmachine2_cmd_buffer_lookahead_source_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + connect \sdram_bankmachine2_cmd_buffer_lookahead_source_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + connect \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + connect \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \sdram_bankmachine2_cmd_buffer_lookahead_source_ready + connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:2285$174_Y + connect \sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:2286$175_Y + connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:2289$176_Y + connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:2290$177_Y + connect \sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:2291$179_Y + connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \sdram_bankmachine3_req_valid + connect \sdram_bankmachine3_req_ready \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine3_req_we + connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \sdram_bankmachine3_req_addr + connect \sdram_bankmachine3_cmd_buffer_sink_valid \sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \sdram_bankmachine3_cmd_buffer_lookahead_source_ready \sdram_bankmachine3_cmd_buffer_sink_ready + connect \sdram_bankmachine3_cmd_buffer_sink_first \sdram_bankmachine3_cmd_buffer_lookahead_source_first + connect \sdram_bankmachine3_cmd_buffer_sink_last \sdram_bankmachine3_cmd_buffer_lookahead_source_last + connect \sdram_bankmachine3_cmd_buffer_sink_payload_we \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + connect \sdram_bankmachine3_cmd_buffer_sink_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + connect \sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:2396$185_Y + connect \sdram_bankmachine3_req_lock $or$ls180.v:2397$186_Y + connect \sdram_bankmachine3_row_hit $eq$ls180.v:2398$187_Y + connect \sdram_bankmachine3_cmd_payload_ba 2'11 + connect \sdram_bankmachine3_twtpcon_valid $and$ls180.v:2408$192_Y + connect \sdram_bankmachine3_trccon_valid $and$ls180.v:2409$194_Y + connect \sdram_bankmachine3_trascon_valid $and$ls180.v:2410$196_Y + connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + connect \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine3_cmd_buffer_lookahead_sink_first + connect \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine3_cmd_buffer_lookahead_sink_last + connect \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + connect \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + connect \sdram_bankmachine3_cmd_buffer_lookahead_source_valid \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \sdram_bankmachine3_cmd_buffer_lookahead_source_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + connect \sdram_bankmachine3_cmd_buffer_lookahead_source_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + connect \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + connect \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \sdram_bankmachine3_cmd_buffer_lookahead_source_ready + connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:2442$204_Y + connect \sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:2443$205_Y + connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:2446$206_Y + connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:2447$207_Y + connect \sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:2448$209_Y + connect \sdram_choose_req_want_cmds 1'1 + connect \sdram_trrdcon_valid $and$ls180.v:2544$220_Y + connect \sdram_tfawcon_valid $and$ls180.v:2545$226_Y + connect \sdram_ras_allowed $and$ls180.v:2546$227_Y + connect \sdram_tccdcon_valid $and$ls180.v:2547$230_Y + connect \sdram_cas_allowed \sdram_tccdcon_ready + connect \sdram_twtrcon_valid $and$ls180.v:2549$232_Y + connect \sdram_read_available $or$ls180.v:2550$239_Y + connect \sdram_write_available $or$ls180.v:2551$246_Y + connect \sdram_max_time0 $eq$ls180.v:2552$247_Y + connect \sdram_max_time1 $eq$ls180.v:2553$248_Y + connect \sdram_bankmachine0_refresh_req \sdram_cmd_valid + connect \sdram_bankmachine1_refresh_req \sdram_cmd_valid + connect \sdram_bankmachine2_refresh_req \sdram_cmd_valid + connect \sdram_bankmachine3_refresh_req \sdram_cmd_valid + connect \sdram_go_to_refresh $and$ls180.v:2558$251_Y + connect \sdram_interface_rdata \sdram_dfi_p0_rddata + connect \sdram_dfi_p0_wrdata \sdram_interface_wdata + connect \sdram_dfi_p0_wrdata_mask $not$ls180.v:2561$252_Y + connect \sdram_choose_cmd_request \sdram_choose_cmd_valids + connect \sdram_choose_cmd_cmd_valid \rhs_array_muxed0 + connect \sdram_choose_cmd_cmd_payload_a \rhs_array_muxed1 + connect \sdram_choose_cmd_cmd_payload_ba \rhs_array_muxed2 + connect \sdram_choose_cmd_cmd_payload_is_read \rhs_array_muxed3 + connect \sdram_choose_cmd_cmd_payload_is_write \rhs_array_muxed4 + connect \sdram_choose_cmd_cmd_payload_is_cmd \rhs_array_muxed5 + connect \sdram_choose_cmd_ce $or$ls180.v:2594$310_Y + connect \sdram_choose_req_request \sdram_choose_req_valids + connect \sdram_choose_req_cmd_valid \rhs_array_muxed6 + connect \sdram_choose_req_cmd_payload_a \rhs_array_muxed7 + connect \sdram_choose_req_cmd_payload_ba \rhs_array_muxed8 + connect \sdram_choose_req_cmd_payload_is_read \rhs_array_muxed9 + connect \sdram_choose_req_cmd_payload_is_write \rhs_array_muxed10 + connect \sdram_choose_req_cmd_payload_is_cmd \rhs_array_muxed11 + connect \sdram_choose_req_ce $or$ls180.v:2663$396_Y + connect \sdram_dfi_p0_reset_n 1'1 + connect \sdram_dfi_p0_cke \sdram_steerer0 + connect \sdram_dfi_p0_odt \sdram_steerer1 + connect \subfragments_roundrobin0_request $and$ls180.v:2740$428_Y + connect \subfragments_roundrobin0_ce $and$ls180.v:2741$431_Y + connect \sdram_interface_bank0_addr \rhs_array_muxed12 + connect \sdram_interface_bank0_we \rhs_array_muxed13 + connect \sdram_interface_bank0_valid \rhs_array_muxed14 + connect \subfragments_roundrobin1_request $and$ls180.v:2745$444_Y + connect \subfragments_roundrobin1_ce $and$ls180.v:2746$447_Y + connect \sdram_interface_bank1_addr \rhs_array_muxed15 + connect \sdram_interface_bank1_we \rhs_array_muxed16 + connect \sdram_interface_bank1_valid \rhs_array_muxed17 + connect \subfragments_roundrobin2_request $and$ls180.v:2750$460_Y + connect \subfragments_roundrobin2_ce $and$ls180.v:2751$463_Y + connect \sdram_interface_bank2_addr \rhs_array_muxed18 + connect \sdram_interface_bank2_we \rhs_array_muxed19 + connect \sdram_interface_bank2_valid \rhs_array_muxed20 + connect \subfragments_roundrobin3_request $and$ls180.v:2755$476_Y + connect \subfragments_roundrobin3_ce $and$ls180.v:2756$479_Y + connect \sdram_interface_bank3_addr \rhs_array_muxed21 + connect \sdram_interface_bank3_we \rhs_array_muxed22 + connect \sdram_interface_bank3_valid \rhs_array_muxed23 + connect \port_cmd_ready $or$ls180.v:2760$543_Y + connect \port_wdata_ready \subfragments_new_master_wdata_ready + connect \port_rdata_valid \subfragments_new_master_rdata_valid3 + connect \port_rdata_payload_data \sdram_interface_rdata + connect \subfragments_roundrobin0_grant 1'0 + connect \subfragments_roundrobin1_grant 1'0 + connect \subfragments_roundrobin2_grant 1'0 + connect \subfragments_roundrobin3_grant 1'0 + connect \converter_reset $not$ls180.v:2782$545_Y + connect \wb_sdram_dat_r { \litedram_wb_dat_r \converter_dat_r [31:16] } + connect \port_cmd_payload_addr $sub$ls180.v:2842$556_Y [23:0] + connect \port_cmd_payload_we \litedram_wb_we + connect \port_wdata_payload_data \litedram_wb_dat_w + connect \port_wdata_payload_we \litedram_wb_sel + connect \litedram_wb_dat_r \port_rdata_payload_data + connect \port_flush $not$ls180.v:2847$557_Y + connect \port_cmd_last $not$ls180.v:2848$558_Y + connect \port_cmd_valid $and$ls180.v:2849$561_Y + connect \port_wdata_valid $and$ls180.v:2850$565_Y + connect \port_rdata_ready $and$ls180.v:2851$568_Y + connect \litedram_wb_ack $and$ls180.v:2852$573_Y + connect \ack_cmd $or$ls180.v:2853$575_Y + connect \ack_wdata $or$ls180.v:2854$577_Y + connect \ack_rdata $and$ls180.v:2855$578_Y + connect \uart_sink_valid \uart_phy_source_valid + connect \uart_phy_source_ready \uart_sink_ready + connect \uart_sink_first \uart_phy_source_first + connect \uart_sink_last \uart_phy_source_last + connect \uart_sink_payload_data \uart_phy_source_payload_data + connect \uart_phy_sink_valid \uart_source_valid + connect \uart_source_ready \uart_phy_sink_ready + connect \uart_phy_sink_first \uart_source_first + connect \uart_phy_sink_last \uart_source_last + connect \uart_phy_sink_payload_data \uart_source_payload_data + connect \tx_fifo_sink_valid \rxtx_re + connect \tx_fifo_sink_payload_data \rxtx_r + connect \txfull_status $not$ls180.v:2868$579_Y + connect \txempty_status $not$ls180.v:2869$580_Y + connect \uart_source_valid \tx_fifo_source_valid + connect \tx_fifo_source_ready \uart_source_ready + connect \uart_source_first \tx_fifo_source_first + connect \uart_source_last \tx_fifo_source_last + connect \uart_source_payload_data \tx_fifo_source_payload_data + connect \tx_trigger $not$ls180.v:2875$581_Y + connect \rx_fifo_sink_valid \uart_sink_valid + connect \uart_sink_ready \rx_fifo_sink_ready + connect \rx_fifo_sink_first \uart_sink_first + connect \rx_fifo_sink_last \uart_sink_last + connect \rx_fifo_sink_payload_data \uart_sink_payload_data + connect \rxempty_status $not$ls180.v:2881$582_Y + connect \rxfull_status $not$ls180.v:2882$583_Y + connect \rxtx_w \rx_fifo_source_payload_data + connect \rx_fifo_source_ready $or$ls180.v:2884$585_Y + connect \rx_trigger $not$ls180.v:2885$586_Y + connect \irq $or$ls180.v:2908$595_Y + connect \tx_status \tx_trigger + connect \rx_status \rx_trigger + connect \tx_fifo_syncfifo_din { \tx_fifo_fifo_in_last \tx_fifo_fifo_in_first \tx_fifo_fifo_in_payload_data } + connect { \tx_fifo_fifo_out_last \tx_fifo_fifo_out_first \tx_fifo_fifo_out_payload_data } \tx_fifo_syncfifo_dout + connect \tx_fifo_sink_ready \tx_fifo_syncfifo_writable + connect \tx_fifo_syncfifo_we \tx_fifo_sink_valid + connect \tx_fifo_fifo_in_first \tx_fifo_sink_first + connect \tx_fifo_fifo_in_last \tx_fifo_sink_last + connect \tx_fifo_fifo_in_payload_data \tx_fifo_sink_payload_data + connect \tx_fifo_source_valid \tx_fifo_readable + connect \tx_fifo_source_first \tx_fifo_fifo_out_first + connect \tx_fifo_source_last \tx_fifo_fifo_out_last + connect \tx_fifo_source_payload_data \tx_fifo_fifo_out_payload_data + connect \tx_fifo_re \tx_fifo_source_ready + connect \tx_fifo_syncfifo_re $and$ls180.v:2923$598_Y + connect \tx_fifo_level1 $add$ls180.v:2924$599_Y + connect \tx_fifo_wrport_dat_w \tx_fifo_syncfifo_din + connect \tx_fifo_wrport_we $and$ls180.v:2934$603_Y + connect \tx_fifo_do_read $and$ls180.v:2935$604_Y + connect \tx_fifo_rdport_adr \tx_fifo_consume + connect \tx_fifo_syncfifo_dout \tx_fifo_rdport_dat_r + connect \tx_fifo_rdport_re \tx_fifo_do_read + connect \tx_fifo_syncfifo_writable $ne$ls180.v:2939$605_Y + connect \tx_fifo_syncfifo_readable $ne$ls180.v:2940$606_Y + connect \rx_fifo_syncfifo_din { \rx_fifo_fifo_in_last \rx_fifo_fifo_in_first \rx_fifo_fifo_in_payload_data } + connect { \rx_fifo_fifo_out_last \rx_fifo_fifo_out_first \rx_fifo_fifo_out_payload_data } \rx_fifo_syncfifo_dout + connect \rx_fifo_sink_ready \rx_fifo_syncfifo_writable + connect \rx_fifo_syncfifo_we \rx_fifo_sink_valid + connect \rx_fifo_fifo_in_first \rx_fifo_sink_first + connect \rx_fifo_fifo_in_last \rx_fifo_sink_last + connect \rx_fifo_fifo_in_payload_data \rx_fifo_sink_payload_data + connect \rx_fifo_source_valid \rx_fifo_readable + connect \rx_fifo_source_first \rx_fifo_fifo_out_first + connect \rx_fifo_source_last \rx_fifo_fifo_out_last + connect \rx_fifo_source_payload_data \rx_fifo_fifo_out_payload_data + connect \rx_fifo_re \rx_fifo_source_ready + connect \rx_fifo_syncfifo_re $and$ls180.v:2953$609_Y + connect \rx_fifo_level1 $add$ls180.v:2954$610_Y + connect \rx_fifo_wrport_dat_w \rx_fifo_syncfifo_din + connect \rx_fifo_wrport_we $and$ls180.v:2964$614_Y + connect \rx_fifo_do_read $and$ls180.v:2965$615_Y + connect \rx_fifo_rdport_adr \rx_fifo_consume + connect \rx_fifo_syncfifo_dout \rx_fifo_rdport_dat_r + connect \rx_fifo_rdport_re \rx_fifo_do_read + connect \rx_fifo_syncfifo_writable $ne$ls180.v:2969$616_Y + connect \rx_fifo_syncfifo_readable $ne$ls180.v:2970$617_Y + connect \libresocsim_libresoc_constraintmanager_i2c_scl \i2c_scl_1 + connect \libresocsim_libresoc_constraintmanager_i2c_sda_oe \i2c_oe + connect \libresocsim_libresoc_constraintmanager_i2c_sda_o \i2c_sda0 + connect \i2c_sda1 \libresocsim_libresoc_constraintmanager_i2c_sda_i + connect \libresocsim_shared_adr \rhs_array_muxed24 + connect \libresocsim_shared_dat_w \rhs_array_muxed25 + connect \libresocsim_shared_sel \rhs_array_muxed26 + connect \libresocsim_shared_cyc \rhs_array_muxed27 + connect \libresocsim_shared_stb \rhs_array_muxed28 + connect \libresocsim_shared_we \rhs_array_muxed29 + connect \libresocsim_shared_cti \rhs_array_muxed30 + connect \libresocsim_shared_bte \rhs_array_muxed31 + connect \libresocsim_interface0_converted_interface_dat_r \libresocsim_shared_dat_r + connect \libresocsim_interface1_converted_interface_dat_r \libresocsim_shared_dat_r + connect \libresocsim_interface2_converted_interface_dat_r \libresocsim_shared_dat_r + connect \libresocsim_interface0_converted_interface_ack $and$ls180.v:3083$627_Y + connect \libresocsim_interface1_converted_interface_ack $and$ls180.v:3084$629_Y + connect \libresocsim_interface2_converted_interface_ack $and$ls180.v:3085$631_Y + connect \libresocsim_interface0_converted_interface_err $and$ls180.v:3086$633_Y + connect \libresocsim_interface1_converted_interface_err $and$ls180.v:3087$635_Y + connect \libresocsim_interface2_converted_interface_err $and$ls180.v:3088$637_Y + connect \libresocsim_request { \libresocsim_interface2_converted_interface_cyc \libresocsim_interface1_converted_interface_cyc \libresocsim_interface0_converted_interface_cyc } + connect \libresocsim_ram_bus_adr \libresocsim_shared_adr + connect \libresocsim_ram_bus_dat_w \libresocsim_shared_dat_w + connect \libresocsim_ram_bus_sel \libresocsim_shared_sel + connect \libresocsim_ram_bus_stb \libresocsim_shared_stb + connect \libresocsim_ram_bus_we \libresocsim_shared_we + connect \libresocsim_ram_bus_cti \libresocsim_shared_cti + connect \libresocsim_ram_bus_bte \libresocsim_shared_bte + connect \ram_bus_ram_bus_adr \libresocsim_shared_adr + connect \ram_bus_ram_bus_dat_w \libresocsim_shared_dat_w + connect \ram_bus_ram_bus_sel \libresocsim_shared_sel + connect \ram_bus_ram_bus_stb \libresocsim_shared_stb + connect \ram_bus_ram_bus_we \libresocsim_shared_we + connect \ram_bus_ram_bus_cti \libresocsim_shared_cti + connect \ram_bus_ram_bus_bte \libresocsim_shared_bte + connect \libresocsim_libresoc_xics_icp_adr \libresocsim_shared_adr + connect \libresocsim_libresoc_xics_icp_dat_w \libresocsim_shared_dat_w + connect \libresocsim_libresoc_xics_icp_sel \libresocsim_shared_sel + connect \libresocsim_libresoc_xics_icp_stb \libresocsim_shared_stb + connect \libresocsim_libresoc_xics_icp_we \libresocsim_shared_we + connect \libresocsim_libresoc_xics_icp_cti \libresocsim_shared_cti + connect \libresocsim_libresoc_xics_icp_bte \libresocsim_shared_bte + connect \libresocsim_libresoc_xics_ics_adr \libresocsim_shared_adr + connect \libresocsim_libresoc_xics_ics_dat_w \libresocsim_shared_dat_w + connect \libresocsim_libresoc_xics_ics_sel \libresocsim_shared_sel + connect \libresocsim_libresoc_xics_ics_stb \libresocsim_shared_stb + connect \libresocsim_libresoc_xics_ics_we \libresocsim_shared_we + connect \libresocsim_libresoc_xics_ics_cti \libresocsim_shared_cti + connect \libresocsim_libresoc_xics_ics_bte \libresocsim_shared_bte + connect \wb_sdram_adr \libresocsim_shared_adr + connect \wb_sdram_dat_w \libresocsim_shared_dat_w + connect \wb_sdram_sel \libresocsim_shared_sel + connect \wb_sdram_stb \libresocsim_shared_stb + connect \wb_sdram_we \libresocsim_shared_we + connect \wb_sdram_cti \libresocsim_shared_cti + connect \wb_sdram_bte \libresocsim_shared_bte + connect \libresocsim_libresocsim_wishbone_adr \libresocsim_shared_adr + connect \libresocsim_libresocsim_wishbone_dat_w \libresocsim_shared_dat_w + connect \libresocsim_libresocsim_wishbone_sel \libresocsim_shared_sel + connect \libresocsim_libresocsim_wishbone_stb \libresocsim_shared_stb + connect \libresocsim_libresocsim_wishbone_we \libresocsim_shared_we + connect \libresocsim_libresocsim_wishbone_cti \libresocsim_shared_cti + connect \libresocsim_libresocsim_wishbone_bte \libresocsim_shared_bte + connect \libresocsim_ram_bus_cyc $and$ls180.v:3141$645_Y + connect \ram_bus_ram_bus_cyc $and$ls180.v:3142$646_Y + connect \libresocsim_libresoc_xics_icp_cyc $and$ls180.v:3143$647_Y + connect \libresocsim_libresoc_xics_ics_cyc $and$ls180.v:3144$648_Y + connect \wb_sdram_cyc $and$ls180.v:3145$649_Y + connect \libresocsim_libresocsim_wishbone_cyc $and$ls180.v:3146$650_Y + connect \libresocsim_shared_err $or$ls180.v:3147$655_Y + connect \libresocsim_wait $and$ls180.v:3148$658_Y + connect \libresocsim_done $eq$ls180.v:3161$676_Y + connect \libresocsim_csrbank0_sel $eq$ls180.v:3162$677_Y + connect \libresocsim_csrbank0_reset0_r \libresocsim_interface0_bank_bus_dat_w [0] + connect \libresocsim_csrbank0_reset0_re $and$ls180.v:3164$680_Y + connect \libresocsim_csrbank0_reset0_we $and$ls180.v:3165$684_Y + connect \libresocsim_csrbank0_scratch3_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_scratch3_re $and$ls180.v:3167$687_Y + connect \libresocsim_csrbank0_scratch3_we $and$ls180.v:3168$691_Y + connect \libresocsim_csrbank0_scratch2_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_scratch2_re $and$ls180.v:3170$694_Y + connect \libresocsim_csrbank0_scratch2_we $and$ls180.v:3171$698_Y + connect \libresocsim_csrbank0_scratch1_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_scratch1_re $and$ls180.v:3173$701_Y + connect \libresocsim_csrbank0_scratch1_we $and$ls180.v:3174$705_Y + connect \libresocsim_csrbank0_scratch0_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_scratch0_re $and$ls180.v:3176$708_Y + connect \libresocsim_csrbank0_scratch0_we $and$ls180.v:3177$712_Y + connect \libresocsim_csrbank0_bus_errors3_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_bus_errors3_re $and$ls180.v:3179$715_Y + connect \libresocsim_csrbank0_bus_errors3_we $and$ls180.v:3180$719_Y + connect \libresocsim_csrbank0_bus_errors2_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_bus_errors2_re $and$ls180.v:3182$722_Y + connect \libresocsim_csrbank0_bus_errors2_we $and$ls180.v:3183$726_Y + connect \libresocsim_csrbank0_bus_errors1_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_bus_errors1_re $and$ls180.v:3185$729_Y + connect \libresocsim_csrbank0_bus_errors1_we $and$ls180.v:3186$733_Y + connect \libresocsim_csrbank0_bus_errors0_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_bus_errors0_re $and$ls180.v:3188$736_Y + connect \libresocsim_csrbank0_bus_errors0_we $and$ls180.v:3189$740_Y + connect \libresocsim_csrbank0_reset0_w \libresocsim_reset_storage + connect \libresocsim_csrbank0_scratch3_w \libresocsim_scratch_storage [31:24] + connect \libresocsim_csrbank0_scratch2_w \libresocsim_scratch_storage [23:16] + connect \libresocsim_csrbank0_scratch1_w \libresocsim_scratch_storage [15:8] + connect \libresocsim_csrbank0_scratch0_w \libresocsim_scratch_storage [7:0] + connect \libresocsim_csrbank0_bus_errors3_w \libresocsim_bus_errors_status [31:24] + connect \libresocsim_csrbank0_bus_errors2_w \libresocsim_bus_errors_status [23:16] + connect \libresocsim_csrbank0_bus_errors1_w \libresocsim_bus_errors_status [15:8] + connect \libresocsim_csrbank0_bus_errors0_w \libresocsim_bus_errors_status [7:0] + connect \libresocsim_bus_errors_we \libresocsim_csrbank0_bus_errors0_we + connect \libresocsim_csrbank1_sel $eq$ls180.v:3200$741_Y + connect \libresocsim_csrbank1_oe0_r \libresocsim_interface1_bank_bus_dat_w + connect \libresocsim_csrbank1_oe0_re $and$ls180.v:3202$744_Y + connect \libresocsim_csrbank1_oe0_we $and$ls180.v:3203$748_Y + connect \libresocsim_csrbank1_in_r \libresocsim_interface1_bank_bus_dat_w + connect \libresocsim_csrbank1_in_re $and$ls180.v:3205$751_Y + connect \libresocsim_csrbank1_in_we $and$ls180.v:3206$755_Y + connect \libresocsim_csrbank1_out0_r \libresocsim_interface1_bank_bus_dat_w + connect \libresocsim_csrbank1_out0_re $and$ls180.v:3208$758_Y + connect \libresocsim_csrbank1_out0_we $and$ls180.v:3209$762_Y + connect \libresocsim_csrbank1_oe0_w \gpio0_oe_storage + connect \libresocsim_csrbank1_in_w \gpio0_status + connect \gpio0_we \libresocsim_csrbank1_in_we + connect \libresocsim_csrbank1_out0_w \gpio0_out_storage + connect \libresocsim_csrbank2_sel $eq$ls180.v:3214$763_Y + connect \libresocsim_csrbank2_oe0_r \libresocsim_interface2_bank_bus_dat_w + connect \libresocsim_csrbank2_oe0_re $and$ls180.v:3216$766_Y + connect \libresocsim_csrbank2_oe0_we $and$ls180.v:3217$770_Y + connect \libresocsim_csrbank2_in_r \libresocsim_interface2_bank_bus_dat_w + connect \libresocsim_csrbank2_in_re $and$ls180.v:3219$773_Y + connect \libresocsim_csrbank2_in_we $and$ls180.v:3220$777_Y + connect \libresocsim_csrbank2_out0_r \libresocsim_interface2_bank_bus_dat_w + connect \libresocsim_csrbank2_out0_re $and$ls180.v:3222$780_Y + connect \libresocsim_csrbank2_out0_we $and$ls180.v:3223$784_Y + connect \libresocsim_csrbank2_oe0_w \gpio1_oe_storage + connect \libresocsim_csrbank2_in_w \gpio1_status + connect \gpio1_we \libresocsim_csrbank2_in_we + connect \libresocsim_csrbank2_out0_w \gpio1_out_storage + connect \libresocsim_csrbank3_sel $eq$ls180.v:3228$785_Y + connect \libresocsim_csrbank3_w0_r \libresocsim_interface3_bank_bus_dat_w [2:0] + connect \libresocsim_csrbank3_w0_re $and$ls180.v:3230$788_Y + connect \libresocsim_csrbank3_w0_we $and$ls180.v:3231$792_Y + connect \libresocsim_csrbank3_r_r \libresocsim_interface3_bank_bus_dat_w [0] + connect \libresocsim_csrbank3_r_re $and$ls180.v:3233$795_Y + connect \libresocsim_csrbank3_r_we $and$ls180.v:3234$799_Y + connect \i2c_scl_1 \i2c_storage [0] + connect \i2c_oe \i2c_storage [1] + connect \i2c_sda0 \i2c_storage [2] + connect \libresocsim_csrbank3_w0_w \i2c_storage + connect \i2c_status \i2c_sda1 + connect \libresocsim_csrbank3_r_w \i2c_status + connect \i2c_we \libresocsim_csrbank3_r_we + connect \libresocsim_csrbank4_sel $eq$ls180.v:3242$800_Y + connect \libresocsim_csrbank4_dfii_control0_r \libresocsim_interface4_bank_bus_dat_w [3:0] + connect \libresocsim_csrbank4_dfii_control0_re $and$ls180.v:3244$803_Y + connect \libresocsim_csrbank4_dfii_control0_we $and$ls180.v:3245$807_Y + connect \libresocsim_csrbank4_dfii_pi0_command0_r \libresocsim_interface4_bank_bus_dat_w [5:0] + connect \libresocsim_csrbank4_dfii_pi0_command0_re $and$ls180.v:3247$810_Y + connect \libresocsim_csrbank4_dfii_pi0_command0_we $and$ls180.v:3248$814_Y + connect \sdram_command_issue_r \libresocsim_interface4_bank_bus_dat_w [0] + connect \sdram_command_issue_re $and$ls180.v:3250$817_Y + connect \sdram_command_issue_we $and$ls180.v:3251$821_Y + connect \libresocsim_csrbank4_dfii_pi0_address1_r \libresocsim_interface4_bank_bus_dat_w [4:0] + connect \libresocsim_csrbank4_dfii_pi0_address1_re $and$ls180.v:3253$824_Y + connect \libresocsim_csrbank4_dfii_pi0_address1_we $and$ls180.v:3254$828_Y + connect \libresocsim_csrbank4_dfii_pi0_address0_r \libresocsim_interface4_bank_bus_dat_w + connect \libresocsim_csrbank4_dfii_pi0_address0_re $and$ls180.v:3256$831_Y + connect \libresocsim_csrbank4_dfii_pi0_address0_we $and$ls180.v:3257$835_Y + connect \libresocsim_csrbank4_dfii_pi0_baddress0_r \libresocsim_interface4_bank_bus_dat_w [1:0] + connect \libresocsim_csrbank4_dfii_pi0_baddress0_re $and$ls180.v:3259$838_Y + connect \libresocsim_csrbank4_dfii_pi0_baddress0_we $and$ls180.v:3260$842_Y + connect \libresocsim_csrbank4_dfii_pi0_wrdata1_r \libresocsim_interface4_bank_bus_dat_w + connect \libresocsim_csrbank4_dfii_pi0_wrdata1_re $and$ls180.v:3262$845_Y + connect \libresocsim_csrbank4_dfii_pi0_wrdata1_we $and$ls180.v:3263$849_Y + connect \libresocsim_csrbank4_dfii_pi0_wrdata0_r \libresocsim_interface4_bank_bus_dat_w + connect \libresocsim_csrbank4_dfii_pi0_wrdata0_re $and$ls180.v:3265$852_Y + connect \libresocsim_csrbank4_dfii_pi0_wrdata0_we $and$ls180.v:3266$856_Y + connect \libresocsim_csrbank4_dfii_pi0_rddata1_r \libresocsim_interface4_bank_bus_dat_w + connect \libresocsim_csrbank4_dfii_pi0_rddata1_re $and$ls180.v:3268$859_Y + connect \libresocsim_csrbank4_dfii_pi0_rddata1_we $and$ls180.v:3269$863_Y + connect \libresocsim_csrbank4_dfii_pi0_rddata0_r \libresocsim_interface4_bank_bus_dat_w + connect \libresocsim_csrbank4_dfii_pi0_rddata0_re $and$ls180.v:3271$866_Y + connect \libresocsim_csrbank4_dfii_pi0_rddata0_we $and$ls180.v:3272$870_Y + connect \sdram_sel \sdram_storage [0] + connect \sdram_cke_1 \sdram_storage [1] + connect \sdram_odt \sdram_storage [2] + connect \sdram_reset_n \sdram_storage [3] + connect \libresocsim_csrbank4_dfii_control0_w \sdram_storage + connect \libresocsim_csrbank4_dfii_pi0_command0_w \sdram_command_storage + connect \libresocsim_csrbank4_dfii_pi0_address1_w \sdram_address_storage [12:8] + connect \libresocsim_csrbank4_dfii_pi0_address0_w \sdram_address_storage [7:0] + connect \libresocsim_csrbank4_dfii_pi0_baddress0_w \sdram_baddress_storage + connect \libresocsim_csrbank4_dfii_pi0_wrdata1_w \sdram_wrdata_storage [15:8] + connect \libresocsim_csrbank4_dfii_pi0_wrdata0_w \sdram_wrdata_storage [7:0] + connect \libresocsim_csrbank4_dfii_pi0_rddata1_w \sdram_status [15:8] + connect \libresocsim_csrbank4_dfii_pi0_rddata0_w \sdram_status [7:0] + connect \sdram_we \libresocsim_csrbank4_dfii_pi0_rddata0_we + connect \libresocsim_csrbank5_sel $eq$ls180.v:3287$871_Y + connect \libresocsim_csrbank5_load3_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_load3_re $and$ls180.v:3289$874_Y + connect \libresocsim_csrbank5_load3_we $and$ls180.v:3290$878_Y + connect \libresocsim_csrbank5_load2_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_load2_re $and$ls180.v:3292$881_Y + connect \libresocsim_csrbank5_load2_we $and$ls180.v:3293$885_Y + connect \libresocsim_csrbank5_load1_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_load1_re $and$ls180.v:3295$888_Y + connect \libresocsim_csrbank5_load1_we $and$ls180.v:3296$892_Y + connect \libresocsim_csrbank5_load0_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_load0_re $and$ls180.v:3298$895_Y + connect \libresocsim_csrbank5_load0_we $and$ls180.v:3299$899_Y + connect \libresocsim_csrbank5_reload3_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_reload3_re $and$ls180.v:3301$902_Y + connect \libresocsim_csrbank5_reload3_we $and$ls180.v:3302$906_Y + connect \libresocsim_csrbank5_reload2_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_reload2_re $and$ls180.v:3304$909_Y + connect \libresocsim_csrbank5_reload2_we $and$ls180.v:3305$913_Y + connect \libresocsim_csrbank5_reload1_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_reload1_re $and$ls180.v:3307$916_Y + connect \libresocsim_csrbank5_reload1_we $and$ls180.v:3308$920_Y + connect \libresocsim_csrbank5_reload0_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_reload0_re $and$ls180.v:3310$923_Y + connect \libresocsim_csrbank5_reload0_we $and$ls180.v:3311$927_Y + connect \libresocsim_csrbank5_en0_r \libresocsim_interface5_bank_bus_dat_w [0] + connect \libresocsim_csrbank5_en0_re $and$ls180.v:3313$930_Y + connect \libresocsim_csrbank5_en0_we $and$ls180.v:3314$934_Y + connect \libresocsim_csrbank5_update_value0_r \libresocsim_interface5_bank_bus_dat_w [0] + connect \libresocsim_csrbank5_update_value0_re $and$ls180.v:3316$937_Y + connect \libresocsim_csrbank5_update_value0_we $and$ls180.v:3317$941_Y + connect \libresocsim_csrbank5_value3_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_value3_re $and$ls180.v:3319$944_Y + connect \libresocsim_csrbank5_value3_we $and$ls180.v:3320$948_Y + connect \libresocsim_csrbank5_value2_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_value2_re $and$ls180.v:3322$951_Y + connect \libresocsim_csrbank5_value2_we $and$ls180.v:3323$955_Y + connect \libresocsim_csrbank5_value1_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_value1_re $and$ls180.v:3325$958_Y + connect \libresocsim_csrbank5_value1_we $and$ls180.v:3326$962_Y + connect \libresocsim_csrbank5_value0_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_value0_re $and$ls180.v:3328$965_Y + connect \libresocsim_csrbank5_value0_we $and$ls180.v:3329$969_Y + connect \libresocsim_eventmanager_status_r \libresocsim_interface5_bank_bus_dat_w [0] + connect \libresocsim_eventmanager_status_re $and$ls180.v:3331$972_Y + connect \libresocsim_eventmanager_status_we $and$ls180.v:3332$976_Y + connect \libresocsim_eventmanager_pending_r \libresocsim_interface5_bank_bus_dat_w [0] + connect \libresocsim_eventmanager_pending_re $and$ls180.v:3334$979_Y + connect \libresocsim_eventmanager_pending_we $and$ls180.v:3335$983_Y + connect \libresocsim_csrbank5_ev_enable0_r \libresocsim_interface5_bank_bus_dat_w [0] + connect \libresocsim_csrbank5_ev_enable0_re $and$ls180.v:3337$986_Y + connect \libresocsim_csrbank5_ev_enable0_we $and$ls180.v:3338$990_Y + connect \libresocsim_csrbank5_load3_w \libresocsim_load_storage [31:24] + connect \libresocsim_csrbank5_load2_w \libresocsim_load_storage [23:16] + connect \libresocsim_csrbank5_load1_w \libresocsim_load_storage [15:8] + connect \libresocsim_csrbank5_load0_w \libresocsim_load_storage [7:0] + connect \libresocsim_csrbank5_reload3_w \libresocsim_reload_storage [31:24] + connect \libresocsim_csrbank5_reload2_w \libresocsim_reload_storage [23:16] + connect \libresocsim_csrbank5_reload1_w \libresocsim_reload_storage [15:8] + connect \libresocsim_csrbank5_reload0_w \libresocsim_reload_storage [7:0] + connect \libresocsim_csrbank5_en0_w \libresocsim_en_storage + connect \libresocsim_csrbank5_update_value0_w \libresocsim_update_value_storage + connect \libresocsim_csrbank5_value3_w \libresocsim_value_status [31:24] + connect \libresocsim_csrbank5_value2_w \libresocsim_value_status [23:16] + connect \libresocsim_csrbank5_value1_w \libresocsim_value_status [15:8] + connect \libresocsim_csrbank5_value0_w \libresocsim_value_status [7:0] + connect \libresocsim_value_we \libresocsim_csrbank5_value0_we + connect \libresocsim_csrbank5_ev_enable0_w \libresocsim_eventmanager_storage + connect \libresocsim_csrbank6_sel $eq$ls180.v:3355$991_Y + connect \rxtx_r \libresocsim_interface6_bank_bus_dat_w + connect \rxtx_re $and$ls180.v:3357$994_Y + connect \rxtx_we $and$ls180.v:3358$998_Y + connect \libresocsim_csrbank6_txfull_r \libresocsim_interface6_bank_bus_dat_w [0] + connect \libresocsim_csrbank6_txfull_re $and$ls180.v:3360$1001_Y + connect \libresocsim_csrbank6_txfull_we $and$ls180.v:3361$1005_Y + connect \libresocsim_csrbank6_rxempty_r \libresocsim_interface6_bank_bus_dat_w [0] + connect \libresocsim_csrbank6_rxempty_re $and$ls180.v:3363$1008_Y + connect \libresocsim_csrbank6_rxempty_we $and$ls180.v:3364$1012_Y + connect \eventmanager_status_r \libresocsim_interface6_bank_bus_dat_w [1:0] + connect \eventmanager_status_re $and$ls180.v:3366$1015_Y + connect \eventmanager_status_we $and$ls180.v:3367$1019_Y + connect \eventmanager_pending_r \libresocsim_interface6_bank_bus_dat_w [1:0] + connect \eventmanager_pending_re $and$ls180.v:3369$1022_Y + connect \eventmanager_pending_we $and$ls180.v:3370$1026_Y + connect \libresocsim_csrbank6_ev_enable0_r \libresocsim_interface6_bank_bus_dat_w [1:0] + connect \libresocsim_csrbank6_ev_enable0_re $and$ls180.v:3372$1029_Y + connect \libresocsim_csrbank6_ev_enable0_we $and$ls180.v:3373$1033_Y + connect \libresocsim_csrbank6_txempty_r \libresocsim_interface6_bank_bus_dat_w [0] + connect \libresocsim_csrbank6_txempty_re $and$ls180.v:3375$1036_Y + connect \libresocsim_csrbank6_txempty_we $and$ls180.v:3376$1040_Y + connect \libresocsim_csrbank6_rxfull_r \libresocsim_interface6_bank_bus_dat_w [0] + connect \libresocsim_csrbank6_rxfull_re $and$ls180.v:3378$1043_Y + connect \libresocsim_csrbank6_rxfull_we $and$ls180.v:3379$1047_Y + connect \libresocsim_csrbank6_txfull_w \txfull_status + connect \txfull_we \libresocsim_csrbank6_txfull_we + connect \libresocsim_csrbank6_rxempty_w \rxempty_status + connect \rxempty_we \libresocsim_csrbank6_rxempty_we + connect \libresocsim_csrbank6_ev_enable0_w \eventmanager_storage + connect \libresocsim_csrbank6_txempty_w \txempty_status + connect \txempty_we \libresocsim_csrbank6_txempty_we + connect \libresocsim_csrbank6_rxfull_w \rxfull_status + connect \rxfull_we \libresocsim_csrbank6_rxfull_we + connect \libresocsim_csrbank7_sel $eq$ls180.v:3389$1048_Y + connect \libresocsim_csrbank7_tuning_word3_r \libresocsim_interface7_bank_bus_dat_w + connect \libresocsim_csrbank7_tuning_word3_re $and$ls180.v:3391$1051_Y + connect \libresocsim_csrbank7_tuning_word3_we $and$ls180.v:3392$1055_Y + connect \libresocsim_csrbank7_tuning_word2_r \libresocsim_interface7_bank_bus_dat_w + connect \libresocsim_csrbank7_tuning_word2_re $and$ls180.v:3394$1058_Y + connect \libresocsim_csrbank7_tuning_word2_we $and$ls180.v:3395$1062_Y + connect \libresocsim_csrbank7_tuning_word1_r \libresocsim_interface7_bank_bus_dat_w + connect \libresocsim_csrbank7_tuning_word1_re $and$ls180.v:3397$1065_Y + connect \libresocsim_csrbank7_tuning_word1_we $and$ls180.v:3398$1069_Y + connect \libresocsim_csrbank7_tuning_word0_r \libresocsim_interface7_bank_bus_dat_w + connect \libresocsim_csrbank7_tuning_word0_re $and$ls180.v:3400$1072_Y + connect \libresocsim_csrbank7_tuning_word0_we $and$ls180.v:3401$1076_Y + connect \libresocsim_csrbank7_tuning_word3_w \uart_phy_storage [31:24] + connect \libresocsim_csrbank7_tuning_word2_w \uart_phy_storage [23:16] + connect \libresocsim_csrbank7_tuning_word1_w \uart_phy_storage [15:8] + connect \libresocsim_csrbank7_tuning_word0_w \uart_phy_storage [7:0] + connect \libresocsim_csr_interconnect_adr \libresocsim_libresocsim_adr + connect \libresocsim_csr_interconnect_we \libresocsim_libresocsim_we + connect \libresocsim_csr_interconnect_dat_w \libresocsim_libresocsim_dat_w + connect \libresocsim_libresocsim_dat_r \libresocsim_csr_interconnect_dat_r + connect \libresocsim_interface0_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface1_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface2_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface3_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface4_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface5_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface6_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface7_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface0_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface1_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface2_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface3_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface4_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface5_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface6_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface7_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface0_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_interface1_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_interface2_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_interface3_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_interface4_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_interface5_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_interface6_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_interface7_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_csr_interconnect_dat_r $or$ls180.v:3434$1083_Y connect \sdrio_clk \sys_clk_1 connect \sdrio_clk_1 \sys_clk_1 connect \sdrio_clk_2 \sys_clk_1 @@ -305564,13 +271761,7 @@ module \ls180 connect \sdrio_clk_53 \sys_clk_1 connect \sdrio_clk_54 \sys_clk_1 connect \sdrio_clk_55 \sys_clk_1 - connect \main_uart_phy_rx \builder_multiregimpl0_regs1 - connect \main_pwm0_enable \main_pwm0_enable_storage - connect \main_pwm0_width \main_pwm0_width_storage - connect \main_pwm0_period \main_pwm0_period_storage - connect \main_pwm1_enable \main_pwm1_enable_storage - connect \main_pwm1_width \main_pwm1_width_storage - connect \main_pwm1_period \main_pwm1_period_storage + connect \uart_phy_rx \regs1 connect \sdrio_clk_56 \sys_clk_1 connect \sdrio_clk_57 \sys_clk_1 connect \sdrio_clk_58 \sys_clk_1 @@ -305584,59 +271775,87 @@ module \ls180 connect \sdrio_clk_66 \sys_clk_1 connect \sdrio_clk_67 \sys_clk_1 connect \sdrio_clk_68 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10373$2918_DATA - connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10401$2944_DATA - connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10429$2970_DATA - connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10457$2996_DATA - connect \main_sram3_dat_r $memrd$\mem_4$ls180.v:10485$3022_DATA - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10503$3029_DATA - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10517$3036_DATA - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10531$3043_DATA - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10545$3050_DATA - connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 - connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 - connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 - connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 - connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10593$3071_DATA - connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10607$3078_DATA + connect \sdrio_clk_69 \sys_clk_1 + connect \sdrio_clk_70 \sys_clk_1 + connect \sdrio_clk_71 \sys_clk_1 + connect \sdrio_clk_72 \sys_clk_1 + connect \sdrio_clk_73 \sys_clk_1 + connect \sdrio_clk_74 \sys_clk_1 + connect \sdrio_clk_75 \sys_clk_1 + connect \sdrio_clk_76 \sys_clk_1 + connect \sdrio_clk_77 \sys_clk_1 + connect \sdrio_clk_78 \sys_clk_1 + connect \sdrio_clk_79 \sys_clk_1 + connect \sdrio_clk_80 \sys_clk_1 + connect \sdrio_clk_81 \sys_clk_1 + connect \sdrio_clk_82 \sys_clk_1 + connect \sdrio_clk_83 \sys_clk_1 + connect \sdrio_clk_84 \sys_clk_1 + connect \sdrio_clk_85 \sys_clk_1 + connect \sdrio_clk_86 \sys_clk_1 + connect \sdrio_clk_87 \sys_clk_1 + connect \sdrio_clk_88 \sys_clk_1 + connect \sdrio_clk_89 \sys_clk_1 + connect \sdrio_clk_90 \sys_clk_1 + connect \sdrio_clk_91 \sys_clk_1 + connect \sdrio_clk_92 \sys_clk_1 + connect \sdrio_clk_93 \sys_clk_1 + connect \sdrio_clk_94 \sys_clk_1 + connect \sdrio_clk_95 \sys_clk_1 + connect \sdrio_clk_96 \sys_clk_1 + connect \sdrio_clk_97 \sys_clk_1 + connect \sdrio_clk_98 \sys_clk_1 + connect \sdrio_clk_99 \sys_clk_1 + connect \sdrio_clk_100 \sys_clk_1 + connect \sdrio_clk_101 \sys_clk_1 + connect \sdrio_clk_102 \sys_clk_1 + connect \sdrio_clk_103 \sys_clk_1 + connect \libresocsim_dat_r $memrd$\mem$ls180.v:5507$1459_DATA + connect \ram_dat_r $memrd$\mem_1$ls180.v:5527$1485_DATA + connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat + connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:5545$1495_DATA + connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 + connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:5559$1505_DATA + connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 + connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:5573$1515_DATA + connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 + connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:5587$1525_DATA + connect \tx_fifo_wrport_dat_r \memdat_4 + connect \tx_fifo_rdport_dat_r \memdat_5 + connect \rx_fifo_wrport_dat_r \memdat_6 + connect \rx_fifo_rdport_dat_r \memdat_7 end -attribute \src "libresoc.v:146562.1-146620.10" +attribute \src "libresoc.v:146902.1-146960.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" attribute \generator "nMigen" module \lsd_l - attribute \src "libresoc.v:146563.7-146563.20" + attribute \src "libresoc.v:146903.7-146903.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146608.3-146616.6" - wire $0\q_int$next[0:0]$7149 - attribute \src "libresoc.v:146606.3-146607.27" + attribute \src "libresoc.v:146948.3-146956.6" + wire $0\q_int$next[0:0]$7081 + attribute \src "libresoc.v:146946.3-146947.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:146608.3-146616.6" - wire $1\q_int$next[0:0]$7150 - attribute \src "libresoc.v:146585.7-146585.19" + attribute \src "libresoc.v:146948.3-146956.6" + wire $1\q_int$next[0:0]$7082 + attribute \src "libresoc.v:146925.7-146925.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:146598.17-146598.96" - wire $and$libresoc.v:146598$7139_Y - attribute \src "libresoc.v:146603.17-146603.96" - wire $and$libresoc.v:146603$7144_Y - attribute \src "libresoc.v:146600.18-146600.93" - wire $not$libresoc.v:146600$7141_Y - attribute \src "libresoc.v:146602.17-146602.92" - wire $not$libresoc.v:146602$7143_Y - attribute \src "libresoc.v:146605.17-146605.92" - wire $not$libresoc.v:146605$7146_Y - attribute \src "libresoc.v:146599.18-146599.98" - wire $or$libresoc.v:146599$7140_Y - attribute \src "libresoc.v:146601.18-146601.99" - wire $or$libresoc.v:146601$7142_Y - attribute \src "libresoc.v:146604.17-146604.97" - wire $or$libresoc.v:146604$7145_Y + attribute \src "libresoc.v:146938.17-146938.96" + wire $and$libresoc.v:146938$7071_Y + attribute \src "libresoc.v:146943.17-146943.96" + wire $and$libresoc.v:146943$7076_Y + attribute \src "libresoc.v:146940.18-146940.93" + wire $not$libresoc.v:146940$7073_Y + attribute \src "libresoc.v:146942.17-146942.92" + wire $not$libresoc.v:146942$7075_Y + attribute \src "libresoc.v:146945.17-146945.92" + wire $not$libresoc.v:146945$7078_Y + attribute \src "libresoc.v:146939.18-146939.98" + wire $or$libresoc.v:146939$7072_Y + attribute \src "libresoc.v:146941.18-146941.99" + wire $or$libresoc.v:146941$7074_Y + attribute \src "libresoc.v:146944.17-146944.97" + wire $or$libresoc.v:146944$7077_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -305653,11 +271872,11 @@ module \lsd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:146563.7-146563.15" + attribute \src "libresoc.v:146903.7-146903.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -305674,7 +271893,7 @@ module \lsd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:146598$7139 + cell $and $and$libresoc.v:146938$7071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305682,10 +271901,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:146598$7139_Y + connect \Y $and$libresoc.v:146938$7071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:146603$7144 + cell $and $and$libresoc.v:146943$7076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305693,34 +271912,34 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:146603$7144_Y + connect \Y $and$libresoc.v:146943$7076_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:146600$7141 + cell $not $not$libresoc.v:146940$7073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lsd - connect \Y $not$libresoc.v:146600$7141_Y + connect \Y $not$libresoc.v:146940$7073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:146602$7143 + cell $not $not$libresoc.v:146942$7075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:146602$7143_Y + connect \Y $not$libresoc.v:146942$7075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:146605$7146 + cell $not $not$libresoc.v:146945$7078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:146605$7146_Y + connect \Y $not$libresoc.v:146945$7078_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:146599$7140 + cell $or $or$libresoc.v:146939$7072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305728,10 +271947,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lsd - connect \Y $or$libresoc.v:146599$7140_Y + connect \Y $or$libresoc.v:146939$7072_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:146601$7142 + cell $or $or$libresoc.v:146941$7074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305739,10 +271958,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_lsd connect \B \q_int - connect \Y $or$libresoc.v:146601$7142_Y + connect \Y $or$libresoc.v:146941$7074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:146604$7145 + cell $or $or$libresoc.v:146944$7077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305750,39 +271969,39 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lsd - connect \Y $or$libresoc.v:146604$7145_Y + connect \Y $or$libresoc.v:146944$7077_Y end - attribute \src "libresoc.v:146563.7-146563.20" - process $proc$libresoc.v:146563$7151 + attribute \src "libresoc.v:146903.7-146903.20" + process $proc$libresoc.v:146903$7083 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146585.7-146585.19" - process $proc$libresoc.v:146585$7152 + attribute \src "libresoc.v:146925.7-146925.19" + process $proc$libresoc.v:146925$7084 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:146606.3-146607.27" - process $proc$libresoc.v:146606$7147 + attribute \src "libresoc.v:146946.3-146947.27" + process $proc$libresoc.v:146946$7079 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:146608.3-146616.6" - process $proc$libresoc.v:146608$7148 + attribute \src "libresoc.v:146948.3-146956.6" + process $proc$libresoc.v:146948$7080 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7149 $1\q_int$next[0:0]$7150 - attribute \src "libresoc.v:146609.5-146609.29" + assign $0\q_int$next[0:0]$7081 $1\q_int$next[0:0]$7082 + attribute \src "libresoc.v:146949.5-146949.29" switch \initial - attribute \src "libresoc.v:146609.9-146609.17" + attribute \src "libresoc.v:146949.9-146949.17" case 1'1 case end @@ -305791,266 +272010,266 @@ module \lsd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7150 1'0 + assign $1\q_int$next[0:0]$7082 1'0 case - assign $1\q_int$next[0:0]$7150 \$5 + assign $1\q_int$next[0:0]$7082 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7149 + update \q_int$next $0\q_int$next[0:0]$7081 end - connect \$9 $and$libresoc.v:146598$7139_Y - connect \$11 $or$libresoc.v:146599$7140_Y - connect \$13 $not$libresoc.v:146600$7141_Y - connect \$15 $or$libresoc.v:146601$7142_Y - connect \$1 $not$libresoc.v:146602$7143_Y - connect \$3 $and$libresoc.v:146603$7144_Y - connect \$5 $or$libresoc.v:146604$7145_Y - connect \$7 $not$libresoc.v:146605$7146_Y + connect \$9 $and$libresoc.v:146938$7071_Y + connect \$11 $or$libresoc.v:146939$7072_Y + connect \$13 $not$libresoc.v:146940$7073_Y + connect \$15 $or$libresoc.v:146941$7074_Y + connect \$1 $not$libresoc.v:146942$7075_Y + connect \$3 $and$libresoc.v:146943$7076_Y + connect \$5 $or$libresoc.v:146944$7077_Y + connect \$7 $not$libresoc.v:146945$7078_Y connect \qlq_lsd \$15 connect \qn_lsd \$13 connect \q_lsd \$11 end -attribute \src "libresoc.v:146624.1-147158.10" +attribute \src "libresoc.v:146964.1-147498.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem" attribute \generator "nMigen" module \lsmem - attribute \src "libresoc.v:147012.3-147037.6" - wire width 45 $0\dbus__adr$next[44:0]$7238 - attribute \src "libresoc.v:146862.3-146863.35" + attribute \src "libresoc.v:147352.3-147377.6" + wire width 45 $0\dbus__adr$next[44:0]$7170 + attribute \src "libresoc.v:147202.3-147203.35" wire width 45 $0\dbus__adr[44:0] - attribute \src "libresoc.v:146872.3-146899.6" - wire $0\dbus__cyc$next[0:0]$7212 - attribute \src "libresoc.v:146870.3-146871.35" + attribute \src "libresoc.v:147212.3-147239.6" + wire $0\dbus__cyc$next[0:0]$7144 + attribute \src "libresoc.v:147210.3-147211.35" wire $0\dbus__cyc[0:0] - attribute \src "libresoc.v:147064.3-147089.6" - wire width 64 $0\dbus__dat_w$next[63:0]$7248 - attribute \src "libresoc.v:146858.3-146859.39" + attribute \src "libresoc.v:147404.3-147429.6" + wire width 64 $0\dbus__dat_w$next[63:0]$7180 + attribute \src "libresoc.v:147198.3-147199.39" wire width 64 $0\dbus__dat_w[63:0] - attribute \src "libresoc.v:146956.3-146986.6" - wire width 8 $0\dbus__sel$next[7:0]$7226 - attribute \src "libresoc.v:146866.3-146867.35" + attribute \src "libresoc.v:147296.3-147326.6" + wire width 8 $0\dbus__sel$next[7:0]$7158 + attribute \src "libresoc.v:147206.3-147207.35" wire width 8 $0\dbus__sel[7:0] - attribute \src "libresoc.v:146900.3-146927.6" - wire $0\dbus__stb$next[0:0]$7218 - attribute \src "libresoc.v:146868.3-146869.35" + attribute \src "libresoc.v:147240.3-147267.6" + wire $0\dbus__stb$next[0:0]$7150 + attribute \src "libresoc.v:147208.3-147209.35" wire $0\dbus__stb[0:0] - attribute \src "libresoc.v:147038.3-147063.6" - wire $0\dbus__we$next[0:0]$7243 - attribute \src "libresoc.v:146860.3-146861.33" + attribute \src "libresoc.v:147378.3-147403.6" + wire $0\dbus__we$next[0:0]$7175 + attribute \src "libresoc.v:147200.3-147201.33" wire $0\dbus__we[0:0] - attribute \src "libresoc.v:146625.7-146625.20" + attribute \src "libresoc.v:146965.7-146965.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147136.3-147155.6" - wire width 45 $0\m_badaddr_o$next[44:0]$7263 - attribute \src "libresoc.v:146852.3-146853.39" + attribute \src "libresoc.v:147476.3-147495.6" + wire width 45 $0\m_badaddr_o$next[44:0]$7195 + attribute \src "libresoc.v:147192.3-147193.39" wire width 45 $0\m_badaddr_o[44:0] - attribute \src "libresoc.v:146938.3-146955.6" + attribute \src "libresoc.v:147278.3-147295.6" wire $0\m_busy_o[0:0] - attribute \src "libresoc.v:146987.3-147011.6" - wire width 64 $0\m_ld_data_o$next[63:0]$7232 - attribute \src "libresoc.v:146864.3-146865.39" + attribute \src "libresoc.v:147327.3-147351.6" + wire width 64 $0\m_ld_data_o$next[63:0]$7164 + attribute \src "libresoc.v:147204.3-147205.39" wire width 64 $0\m_ld_data_o[63:0] - attribute \src "libresoc.v:147090.3-147112.6" - wire $0\m_load_err_o$next[0:0]$7253 - attribute \src "libresoc.v:146856.3-146857.41" + attribute \src "libresoc.v:147430.3-147452.6" + wire $0\m_load_err_o$next[0:0]$7185 + attribute \src "libresoc.v:147196.3-147197.41" wire $0\m_load_err_o[0:0] - attribute \src "libresoc.v:147113.3-147135.6" - wire $0\m_store_err_o$next[0:0]$7258 - attribute \src "libresoc.v:146854.3-146855.43" + attribute \src "libresoc.v:147453.3-147475.6" + wire $0\m_store_err_o$next[0:0]$7190 + attribute \src "libresoc.v:147194.3-147195.43" wire $0\m_store_err_o[0:0] - attribute \src "libresoc.v:146928.3-146937.6" + attribute \src "libresoc.v:147268.3-147277.6" wire $0\x_busy_o[0:0] - attribute \src "libresoc.v:147012.3-147037.6" - wire width 45 $1\dbus__adr$next[44:0]$7239 - attribute \src "libresoc.v:146730.14-146730.42" + attribute \src "libresoc.v:147352.3-147377.6" + wire width 45 $1\dbus__adr$next[44:0]$7171 + attribute \src "libresoc.v:147070.14-147070.42" wire width 45 $1\dbus__adr[44:0] - attribute \src "libresoc.v:146872.3-146899.6" - wire $1\dbus__cyc$next[0:0]$7213 - attribute \src "libresoc.v:146735.7-146735.23" + attribute \src "libresoc.v:147212.3-147239.6" + wire $1\dbus__cyc$next[0:0]$7145 + attribute \src "libresoc.v:147075.7-147075.23" wire $1\dbus__cyc[0:0] - attribute \src "libresoc.v:147064.3-147089.6" - wire width 64 $1\dbus__dat_w$next[63:0]$7249 - attribute \src "libresoc.v:146742.14-146742.48" + attribute \src "libresoc.v:147404.3-147429.6" + wire width 64 $1\dbus__dat_w$next[63:0]$7181 + attribute \src "libresoc.v:147082.14-147082.48" wire width 64 $1\dbus__dat_w[63:0] - attribute \src "libresoc.v:146956.3-146986.6" - wire width 8 $1\dbus__sel$next[7:0]$7227 - attribute \src "libresoc.v:146749.13-146749.30" + attribute \src "libresoc.v:147296.3-147326.6" + wire width 8 $1\dbus__sel$next[7:0]$7159 + attribute \src "libresoc.v:147089.13-147089.30" wire width 8 $1\dbus__sel[7:0] - attribute \src "libresoc.v:146900.3-146927.6" - wire $1\dbus__stb$next[0:0]$7219 - attribute \src "libresoc.v:146754.7-146754.23" + attribute \src "libresoc.v:147240.3-147267.6" + wire $1\dbus__stb$next[0:0]$7151 + attribute \src "libresoc.v:147094.7-147094.23" wire $1\dbus__stb[0:0] - attribute \src "libresoc.v:147038.3-147063.6" - wire $1\dbus__we$next[0:0]$7244 - attribute \src "libresoc.v:146759.7-146759.22" + attribute \src "libresoc.v:147378.3-147403.6" + wire $1\dbus__we$next[0:0]$7176 + attribute \src "libresoc.v:147099.7-147099.22" wire $1\dbus__we[0:0] - attribute \src "libresoc.v:147136.3-147155.6" - wire width 45 $1\m_badaddr_o$next[44:0]$7264 - attribute \src "libresoc.v:146763.14-146763.44" + attribute \src "libresoc.v:147476.3-147495.6" + wire width 45 $1\m_badaddr_o$next[44:0]$7196 + attribute \src "libresoc.v:147103.14-147103.44" wire width 45 $1\m_badaddr_o[44:0] - attribute \src "libresoc.v:146938.3-146955.6" + attribute \src "libresoc.v:147278.3-147295.6" wire $1\m_busy_o[0:0] - attribute \src "libresoc.v:146987.3-147011.6" - wire width 64 $1\m_ld_data_o$next[63:0]$7233 - attribute \src "libresoc.v:146770.14-146770.48" + attribute \src "libresoc.v:147327.3-147351.6" + wire width 64 $1\m_ld_data_o$next[63:0]$7165 + attribute \src "libresoc.v:147110.14-147110.48" wire width 64 $1\m_ld_data_o[63:0] - attribute \src "libresoc.v:147090.3-147112.6" - wire $1\m_load_err_o$next[0:0]$7254 - attribute \src "libresoc.v:146774.7-146774.26" + attribute \src "libresoc.v:147430.3-147452.6" + wire $1\m_load_err_o$next[0:0]$7186 + attribute \src "libresoc.v:147114.7-147114.26" wire $1\m_load_err_o[0:0] - attribute \src "libresoc.v:147113.3-147135.6" - wire $1\m_store_err_o$next[0:0]$7259 - attribute \src "libresoc.v:146780.7-146780.27" + attribute \src "libresoc.v:147453.3-147475.6" + wire $1\m_store_err_o$next[0:0]$7191 + attribute \src "libresoc.v:147120.7-147120.27" wire $1\m_store_err_o[0:0] - attribute \src "libresoc.v:146928.3-146937.6" + attribute \src "libresoc.v:147268.3-147277.6" wire $1\x_busy_o[0:0] - attribute \src "libresoc.v:147012.3-147037.6" - wire width 45 $2\dbus__adr$next[44:0]$7240 - attribute \src "libresoc.v:146872.3-146899.6" - wire $2\dbus__cyc$next[0:0]$7214 - attribute \src "libresoc.v:147064.3-147089.6" - wire width 64 $2\dbus__dat_w$next[63:0]$7250 - attribute \src "libresoc.v:146956.3-146986.6" - wire width 8 $2\dbus__sel$next[7:0]$7228 - attribute \src "libresoc.v:146900.3-146927.6" - wire $2\dbus__stb$next[0:0]$7220 - attribute \src "libresoc.v:147038.3-147063.6" - wire $2\dbus__we$next[0:0]$7245 - attribute \src "libresoc.v:147136.3-147155.6" - wire width 45 $2\m_badaddr_o$next[44:0]$7265 - attribute \src "libresoc.v:146938.3-146955.6" + attribute \src "libresoc.v:147352.3-147377.6" + wire width 45 $2\dbus__adr$next[44:0]$7172 + attribute \src "libresoc.v:147212.3-147239.6" + wire $2\dbus__cyc$next[0:0]$7146 + attribute \src "libresoc.v:147404.3-147429.6" + wire width 64 $2\dbus__dat_w$next[63:0]$7182 + attribute \src "libresoc.v:147296.3-147326.6" + wire width 8 $2\dbus__sel$next[7:0]$7160 + attribute \src "libresoc.v:147240.3-147267.6" + wire $2\dbus__stb$next[0:0]$7152 + attribute \src "libresoc.v:147378.3-147403.6" + wire $2\dbus__we$next[0:0]$7177 + attribute \src "libresoc.v:147476.3-147495.6" + wire width 45 $2\m_badaddr_o$next[44:0]$7197 + attribute \src "libresoc.v:147278.3-147295.6" wire $2\m_busy_o[0:0] - attribute \src "libresoc.v:146987.3-147011.6" - wire width 64 $2\m_ld_data_o$next[63:0]$7234 - attribute \src "libresoc.v:147090.3-147112.6" - wire $2\m_load_err_o$next[0:0]$7255 - attribute \src "libresoc.v:147113.3-147135.6" - wire $2\m_store_err_o$next[0:0]$7260 - attribute \src "libresoc.v:147012.3-147037.6" - wire width 45 $3\dbus__adr$next[44:0]$7241 - attribute \src "libresoc.v:146872.3-146899.6" - wire $3\dbus__cyc$next[0:0]$7215 - attribute \src "libresoc.v:147064.3-147089.6" - wire width 64 $3\dbus__dat_w$next[63:0]$7251 - attribute \src "libresoc.v:146956.3-146986.6" - wire width 8 $3\dbus__sel$next[7:0]$7229 - attribute \src "libresoc.v:146900.3-146927.6" - wire $3\dbus__stb$next[0:0]$7221 - attribute \src "libresoc.v:147038.3-147063.6" - wire $3\dbus__we$next[0:0]$7246 - attribute \src "libresoc.v:147136.3-147155.6" - wire width 45 $3\m_badaddr_o$next[44:0]$7266 - attribute \src "libresoc.v:146987.3-147011.6" - wire width 64 $3\m_ld_data_o$next[63:0]$7235 - attribute \src "libresoc.v:147090.3-147112.6" - wire $3\m_load_err_o$next[0:0]$7256 - attribute \src "libresoc.v:147113.3-147135.6" - wire $3\m_store_err_o$next[0:0]$7261 - attribute \src "libresoc.v:146872.3-146899.6" - wire $4\dbus__cyc$next[0:0]$7216 - attribute \src "libresoc.v:146956.3-146986.6" - wire width 8 $4\dbus__sel$next[7:0]$7230 - attribute \src "libresoc.v:146900.3-146927.6" - wire $4\dbus__stb$next[0:0]$7222 - attribute \src "libresoc.v:146987.3-147011.6" - wire width 64 $4\m_ld_data_o$next[63:0]$7236 - attribute \src "libresoc.v:146808.18-146808.116" - wire $and$libresoc.v:146808$7157_Y - attribute \src "libresoc.v:146811.18-146811.111" - wire $and$libresoc.v:146811$7160_Y - attribute \src "libresoc.v:146816.18-146816.116" - wire $and$libresoc.v:146816$7165_Y - attribute \src "libresoc.v:146818.18-146818.111" - wire $and$libresoc.v:146818$7167_Y - attribute \src "libresoc.v:146820.17-146820.114" - wire $and$libresoc.v:146820$7169_Y - attribute \src "libresoc.v:146824.18-146824.116" - wire $and$libresoc.v:146824$7173_Y - attribute \src "libresoc.v:146826.18-146826.111" - wire $and$libresoc.v:146826$7175_Y - attribute \src "libresoc.v:146832.18-146832.116" - wire $and$libresoc.v:146832$7181_Y - attribute \src "libresoc.v:146834.18-146834.111" - wire $and$libresoc.v:146834$7183_Y - attribute \src "libresoc.v:146836.18-146836.116" - wire $and$libresoc.v:146836$7185_Y - attribute \src "libresoc.v:146838.18-146838.111" - wire $and$libresoc.v:146838$7187_Y - attribute \src "libresoc.v:146840.18-146840.116" - wire $and$libresoc.v:146840$7189_Y - attribute \src "libresoc.v:146842.17-146842.108" - wire $and$libresoc.v:146842$7191_Y - attribute \src "libresoc.v:146843.18-146843.111" - wire $and$libresoc.v:146843$7192_Y - attribute \src "libresoc.v:146844.18-146844.120" - wire $and$libresoc.v:146844$7193_Y - attribute \src "libresoc.v:146847.18-146847.120" - wire $and$libresoc.v:146847$7196_Y - attribute \src "libresoc.v:146849.18-146849.120" - wire $and$libresoc.v:146849$7198_Y - attribute \src "libresoc.v:146805.18-146805.110" - wire $not$libresoc.v:146805$7154_Y - attribute \src "libresoc.v:146810.18-146810.110" - wire $not$libresoc.v:146810$7159_Y - attribute \src "libresoc.v:146813.18-146813.110" - wire $not$libresoc.v:146813$7162_Y - attribute \src "libresoc.v:146817.18-146817.110" - wire $not$libresoc.v:146817$7166_Y - attribute \src "libresoc.v:146821.18-146821.110" - wire $not$libresoc.v:146821$7170_Y - attribute \src "libresoc.v:146825.18-146825.110" - wire $not$libresoc.v:146825$7174_Y - attribute \src "libresoc.v:146828.18-146828.110" - wire $not$libresoc.v:146828$7177_Y - attribute \src "libresoc.v:146831.17-146831.109" - wire $not$libresoc.v:146831$7180_Y - attribute \src "libresoc.v:146833.18-146833.110" - wire $not$libresoc.v:146833$7182_Y - attribute \src "libresoc.v:146837.18-146837.110" - wire $not$libresoc.v:146837$7186_Y - attribute \src "libresoc.v:146841.18-146841.110" - wire $not$libresoc.v:146841$7190_Y - attribute \src "libresoc.v:146845.18-146845.110" - wire $not$libresoc.v:146845$7194_Y - attribute \src "libresoc.v:146846.18-146846.109" - wire $not$libresoc.v:146846$7195_Y - attribute \src "libresoc.v:146848.18-146848.110" - wire $not$libresoc.v:146848$7197_Y - attribute \src "libresoc.v:146850.18-146850.110" - wire $not$libresoc.v:146850$7199_Y - attribute \src "libresoc.v:146804.17-146804.119" - wire $or$libresoc.v:146804$7153_Y - attribute \src "libresoc.v:146806.18-146806.110" - wire $or$libresoc.v:146806$7155_Y - attribute \src "libresoc.v:146807.18-146807.114" - wire $or$libresoc.v:146807$7156_Y - attribute \src "libresoc.v:146809.17-146809.113" - wire $or$libresoc.v:146809$7158_Y - attribute \src "libresoc.v:146812.18-146812.120" - wire $or$libresoc.v:146812$7161_Y - attribute \src "libresoc.v:146814.18-146814.111" - wire $or$libresoc.v:146814$7163_Y - attribute \src "libresoc.v:146815.18-146815.114" - wire $or$libresoc.v:146815$7164_Y - attribute \src "libresoc.v:146819.18-146819.120" - wire $or$libresoc.v:146819$7168_Y - attribute \src "libresoc.v:146822.18-146822.111" - wire $or$libresoc.v:146822$7171_Y - attribute \src "libresoc.v:146823.18-146823.114" - wire $or$libresoc.v:146823$7172_Y - attribute \src "libresoc.v:146827.18-146827.120" - wire $or$libresoc.v:146827$7176_Y - attribute \src "libresoc.v:146829.18-146829.111" - wire $or$libresoc.v:146829$7178_Y - attribute \src "libresoc.v:146830.18-146830.114" - wire $or$libresoc.v:146830$7179_Y - attribute \src "libresoc.v:146835.18-146835.114" - wire $or$libresoc.v:146835$7184_Y - attribute \src "libresoc.v:146839.18-146839.114" - wire $or$libresoc.v:146839$7188_Y - attribute \src "libresoc.v:146851.18-146851.127" - wire $or$libresoc.v:146851$7200_Y + attribute \src "libresoc.v:147327.3-147351.6" + wire width 64 $2\m_ld_data_o$next[63:0]$7166 + attribute \src "libresoc.v:147430.3-147452.6" + wire $2\m_load_err_o$next[0:0]$7187 + attribute \src "libresoc.v:147453.3-147475.6" + wire $2\m_store_err_o$next[0:0]$7192 + attribute \src "libresoc.v:147352.3-147377.6" + wire width 45 $3\dbus__adr$next[44:0]$7173 + attribute \src "libresoc.v:147212.3-147239.6" + wire $3\dbus__cyc$next[0:0]$7147 + attribute \src "libresoc.v:147404.3-147429.6" + wire width 64 $3\dbus__dat_w$next[63:0]$7183 + attribute \src "libresoc.v:147296.3-147326.6" + wire width 8 $3\dbus__sel$next[7:0]$7161 + attribute \src "libresoc.v:147240.3-147267.6" + wire $3\dbus__stb$next[0:0]$7153 + attribute \src "libresoc.v:147378.3-147403.6" + wire $3\dbus__we$next[0:0]$7178 + attribute \src "libresoc.v:147476.3-147495.6" + wire width 45 $3\m_badaddr_o$next[44:0]$7198 + attribute \src "libresoc.v:147327.3-147351.6" + wire width 64 $3\m_ld_data_o$next[63:0]$7167 + attribute \src "libresoc.v:147430.3-147452.6" + wire $3\m_load_err_o$next[0:0]$7188 + attribute \src "libresoc.v:147453.3-147475.6" + wire $3\m_store_err_o$next[0:0]$7193 + attribute \src "libresoc.v:147212.3-147239.6" + wire $4\dbus__cyc$next[0:0]$7148 + attribute \src "libresoc.v:147296.3-147326.6" + wire width 8 $4\dbus__sel$next[7:0]$7162 + attribute \src "libresoc.v:147240.3-147267.6" + wire $4\dbus__stb$next[0:0]$7154 + attribute \src "libresoc.v:147327.3-147351.6" + wire width 64 $4\m_ld_data_o$next[63:0]$7168 + attribute \src "libresoc.v:147148.18-147148.116" + wire $and$libresoc.v:147148$7089_Y + attribute \src "libresoc.v:147151.18-147151.111" + wire $and$libresoc.v:147151$7092_Y + attribute \src "libresoc.v:147156.18-147156.116" + wire $and$libresoc.v:147156$7097_Y + attribute \src "libresoc.v:147158.18-147158.111" + wire $and$libresoc.v:147158$7099_Y + attribute \src "libresoc.v:147160.17-147160.114" + wire $and$libresoc.v:147160$7101_Y + attribute \src "libresoc.v:147164.18-147164.116" + wire $and$libresoc.v:147164$7105_Y + attribute \src "libresoc.v:147166.18-147166.111" + wire $and$libresoc.v:147166$7107_Y + attribute \src "libresoc.v:147172.18-147172.116" + wire $and$libresoc.v:147172$7113_Y + attribute \src "libresoc.v:147174.18-147174.111" + wire $and$libresoc.v:147174$7115_Y + attribute \src "libresoc.v:147176.18-147176.116" + wire $and$libresoc.v:147176$7117_Y + attribute \src "libresoc.v:147178.18-147178.111" + wire $and$libresoc.v:147178$7119_Y + attribute \src "libresoc.v:147180.18-147180.116" + wire $and$libresoc.v:147180$7121_Y + attribute \src "libresoc.v:147182.17-147182.108" + wire $and$libresoc.v:147182$7123_Y + attribute \src "libresoc.v:147183.18-147183.111" + wire $and$libresoc.v:147183$7124_Y + attribute \src "libresoc.v:147184.18-147184.120" + wire $and$libresoc.v:147184$7125_Y + attribute \src "libresoc.v:147187.18-147187.120" + wire $and$libresoc.v:147187$7128_Y + attribute \src "libresoc.v:147189.18-147189.120" + wire $and$libresoc.v:147189$7130_Y + attribute \src "libresoc.v:147145.18-147145.110" + wire $not$libresoc.v:147145$7086_Y + attribute \src "libresoc.v:147150.18-147150.110" + wire $not$libresoc.v:147150$7091_Y + attribute \src "libresoc.v:147153.18-147153.110" + wire $not$libresoc.v:147153$7094_Y + attribute \src "libresoc.v:147157.18-147157.110" + wire $not$libresoc.v:147157$7098_Y + attribute \src "libresoc.v:147161.18-147161.110" + wire $not$libresoc.v:147161$7102_Y + attribute \src "libresoc.v:147165.18-147165.110" + wire $not$libresoc.v:147165$7106_Y + attribute \src "libresoc.v:147168.18-147168.110" + wire $not$libresoc.v:147168$7109_Y + attribute \src "libresoc.v:147171.17-147171.109" + wire $not$libresoc.v:147171$7112_Y + attribute \src "libresoc.v:147173.18-147173.110" + wire $not$libresoc.v:147173$7114_Y + attribute \src "libresoc.v:147177.18-147177.110" + wire $not$libresoc.v:147177$7118_Y + attribute \src "libresoc.v:147181.18-147181.110" + wire $not$libresoc.v:147181$7122_Y + attribute \src "libresoc.v:147185.18-147185.110" + wire $not$libresoc.v:147185$7126_Y + attribute \src "libresoc.v:147186.18-147186.109" + wire $not$libresoc.v:147186$7127_Y + attribute \src "libresoc.v:147188.18-147188.110" + wire $not$libresoc.v:147188$7129_Y + attribute \src "libresoc.v:147190.18-147190.110" + wire $not$libresoc.v:147190$7131_Y + attribute \src "libresoc.v:147144.17-147144.119" + wire $or$libresoc.v:147144$7085_Y + attribute \src "libresoc.v:147146.18-147146.110" + wire $or$libresoc.v:147146$7087_Y + attribute \src "libresoc.v:147147.18-147147.114" + wire $or$libresoc.v:147147$7088_Y + attribute \src "libresoc.v:147149.17-147149.113" + wire $or$libresoc.v:147149$7090_Y + attribute \src "libresoc.v:147152.18-147152.120" + wire $or$libresoc.v:147152$7093_Y + attribute \src "libresoc.v:147154.18-147154.111" + wire $or$libresoc.v:147154$7095_Y + attribute \src "libresoc.v:147155.18-147155.114" + wire $or$libresoc.v:147155$7096_Y + attribute \src "libresoc.v:147159.18-147159.120" + wire $or$libresoc.v:147159$7100_Y + attribute \src "libresoc.v:147162.18-147162.111" + wire $or$libresoc.v:147162$7103_Y + attribute \src "libresoc.v:147163.18-147163.114" + wire $or$libresoc.v:147163$7104_Y + attribute \src "libresoc.v:147167.18-147167.120" + wire $or$libresoc.v:147167$7108_Y + attribute \src "libresoc.v:147169.18-147169.111" + wire $or$libresoc.v:147169$7110_Y + attribute \src "libresoc.v:147170.18-147170.114" + wire $or$libresoc.v:147170$7111_Y + attribute \src "libresoc.v:147175.18-147175.114" + wire $or$libresoc.v:147175$7116_Y + attribute \src "libresoc.v:147179.18-147179.114" + wire $or$libresoc.v:147179$7120_Y + attribute \src "libresoc.v:147191.18-147191.127" + wire $or$libresoc.v:147191$7132_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" @@ -306147,9 +272366,9 @@ module \lsmem wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 13 \dbus__ack @@ -306181,7 +272400,7 @@ module \lsmem wire output 19 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire \dbus__we$next - attribute \src "libresoc.v:146625.7-146625.15" + attribute \src "libresoc.v:146965.7-146965.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" wire width 45 \m_badaddr_o @@ -306224,7 +272443,7 @@ module \lsmem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire input 10 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146808$7157 + cell $and $and$libresoc.v:147148$7089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306232,10 +272451,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$15 connect \B \x_valid_i - connect \Y $and$libresoc.v:146808$7157_Y + connect \Y $and$libresoc.v:147148$7089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146811$7160 + cell $and $and$libresoc.v:147151$7092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306243,10 +272462,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$17 connect \B \$19 - connect \Y $and$libresoc.v:146811$7160_Y + connect \Y $and$libresoc.v:147151$7092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146816$7165 + cell $and $and$libresoc.v:147156$7097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306254,10 +272473,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$29 connect \B \x_valid_i - connect \Y $and$libresoc.v:146816$7165_Y + connect \Y $and$libresoc.v:147156$7097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146818$7167 + cell $and $and$libresoc.v:147158$7099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306265,10 +272484,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:146818$7167_Y + connect \Y $and$libresoc.v:147158$7099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146820$7169 + cell $and $and$libresoc.v:147160$7101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306276,10 +272495,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$1 connect \B \x_valid_i - connect \Y $and$libresoc.v:146820$7169_Y + connect \Y $and$libresoc.v:147160$7101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146824$7173 + cell $and $and$libresoc.v:147164$7105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306287,10 +272506,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$43 connect \B \x_valid_i - connect \Y $and$libresoc.v:146824$7173_Y + connect \Y $and$libresoc.v:147164$7105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146826$7175 + cell $and $and$libresoc.v:147166$7107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306298,10 +272517,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:146826$7175_Y + connect \Y $and$libresoc.v:147166$7107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146832$7181 + cell $and $and$libresoc.v:147172$7113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306309,10 +272528,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$57 connect \B \x_valid_i - connect \Y $and$libresoc.v:146832$7181_Y + connect \Y $and$libresoc.v:147172$7113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146834$7183 + cell $and $and$libresoc.v:147174$7115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306320,10 +272539,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:146834$7183_Y + connect \Y $and$libresoc.v:147174$7115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146836$7185 + cell $and $and$libresoc.v:147176$7117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306331,10 +272550,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$65 connect \B \x_valid_i - connect \Y $and$libresoc.v:146836$7185_Y + connect \Y $and$libresoc.v:147176$7117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146838$7187 + cell $and $and$libresoc.v:147178$7119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306342,10 +272561,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$67 connect \B \$69 - connect \Y $and$libresoc.v:146838$7187_Y + connect \Y $and$libresoc.v:147178$7119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146840$7189 + cell $and $and$libresoc.v:147180$7121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306353,10 +272572,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$73 connect \B \x_valid_i - connect \Y $and$libresoc.v:146840$7189_Y + connect \Y $and$libresoc.v:147180$7121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146842$7191 + cell $and $and$libresoc.v:147182$7123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306364,10 +272583,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:146842$7191_Y + connect \Y $and$libresoc.v:147182$7123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146843$7192 + cell $and $and$libresoc.v:147183$7124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306375,10 +272594,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$75 connect \B \$77 - connect \Y $and$libresoc.v:146843$7192_Y + connect \Y $and$libresoc.v:147183$7124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:146844$7193 + cell $and $and$libresoc.v:147184$7125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306386,10 +272605,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:146844$7193_Y + connect \Y $and$libresoc.v:147184$7125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:146847$7196 + cell $and $and$libresoc.v:147187$7128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306397,10 +272616,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:146847$7196_Y + connect \Y $and$libresoc.v:147187$7128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:146849$7198 + cell $and $and$libresoc.v:147189$7130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306408,130 +272627,130 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:146849$7198_Y + connect \Y $and$libresoc.v:147189$7130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:146805$7154 + cell $not $not$libresoc.v:147145$7086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:146805$7154_Y + connect \Y $not$libresoc.v:147145$7086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146810$7159 + cell $not $not$libresoc.v:147150$7091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146810$7159_Y + connect \Y $not$libresoc.v:147150$7091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:146813$7162 + cell $not $not$libresoc.v:147153$7094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:146813$7162_Y + connect \Y $not$libresoc.v:147153$7094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146817$7166 + cell $not $not$libresoc.v:147157$7098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146817$7166_Y + connect \Y $not$libresoc.v:147157$7098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:146821$7170 + cell $not $not$libresoc.v:147161$7102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:146821$7170_Y + connect \Y $not$libresoc.v:147161$7102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146825$7174 + cell $not $not$libresoc.v:147165$7106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146825$7174_Y + connect \Y $not$libresoc.v:147165$7106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:146828$7177 + cell $not $not$libresoc.v:147168$7109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:146828$7177_Y + connect \Y $not$libresoc.v:147168$7109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146831$7180 + cell $not $not$libresoc.v:147171$7112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146831$7180_Y + connect \Y $not$libresoc.v:147171$7112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146833$7182 + cell $not $not$libresoc.v:147173$7114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146833$7182_Y + connect \Y $not$libresoc.v:147173$7114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146837$7186 + cell $not $not$libresoc.v:147177$7118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146837$7186_Y + connect \Y $not$libresoc.v:147177$7118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146841$7190 + cell $not $not$libresoc.v:147181$7122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146841$7190_Y + connect \Y $not$libresoc.v:147181$7122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:146845$7194 + cell $not $not$libresoc.v:147185$7126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:146845$7194_Y + connect \Y $not$libresoc.v:147185$7126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" - cell $not $not$libresoc.v:146846$7195 + cell $not $not$libresoc.v:147186$7127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__we - connect \Y $not$libresoc.v:146846$7195_Y + connect \Y $not$libresoc.v:147186$7127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:146848$7197 + cell $not $not$libresoc.v:147188$7129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:146848$7197_Y + connect \Y $not$libresoc.v:147188$7129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:146850$7199 + cell $not $not$libresoc.v:147190$7131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:146850$7199_Y + connect \Y $not$libresoc.v:147190$7131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146804$7153 + cell $or $or$libresoc.v:147144$7085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306539,10 +272758,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:146804$7153_Y + connect \Y $or$libresoc.v:147144$7085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146806$7155 + cell $or $or$libresoc.v:147146$7087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306550,10 +272769,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:146806$7155_Y + connect \Y $or$libresoc.v:147146$7087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146807$7156 + cell $or $or$libresoc.v:147147$7088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306561,10 +272780,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146807$7156_Y + connect \Y $or$libresoc.v:147147$7088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146809$7158 + cell $or $or$libresoc.v:147149$7090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306572,10 +272791,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146809$7158_Y + connect \Y $or$libresoc.v:147149$7090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146812$7161 + cell $or $or$libresoc.v:147152$7093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306583,10 +272802,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:146812$7161_Y + connect \Y $or$libresoc.v:147152$7093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146814$7163 + cell $or $or$libresoc.v:147154$7095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306594,10 +272813,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:146814$7163_Y + connect \Y $or$libresoc.v:147154$7095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146815$7164 + cell $or $or$libresoc.v:147155$7096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306605,10 +272824,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146815$7164_Y + connect \Y $or$libresoc.v:147155$7096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146819$7168 + cell $or $or$libresoc.v:147159$7100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306616,10 +272835,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:146819$7168_Y + connect \Y $or$libresoc.v:147159$7100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146822$7171 + cell $or $or$libresoc.v:147162$7103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306627,10 +272846,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:146822$7171_Y + connect \Y $or$libresoc.v:147162$7103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146823$7172 + cell $or $or$libresoc.v:147163$7104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306638,10 +272857,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146823$7172_Y + connect \Y $or$libresoc.v:147163$7104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146827$7176 + cell $or $or$libresoc.v:147167$7108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306649,10 +272868,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:146827$7176_Y + connect \Y $or$libresoc.v:147167$7108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146829$7178 + cell $or $or$libresoc.v:147169$7110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306660,10 +272879,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:146829$7178_Y + connect \Y $or$libresoc.v:147169$7110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146830$7179 + cell $or $or$libresoc.v:147170$7111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306671,10 +272890,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146830$7179_Y + connect \Y $or$libresoc.v:147170$7111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146835$7184 + cell $or $or$libresoc.v:147175$7116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306682,10 +272901,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146835$7184_Y + connect \Y $or$libresoc.v:147175$7116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146839$7188 + cell $or $or$libresoc.v:147179$7120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306693,10 +272912,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146839$7188_Y + connect \Y $or$libresoc.v:147179$7120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" - cell $or $or$libresoc.v:146851$7200 + cell $or $or$libresoc.v:147191$7132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306704,175 +272923,175 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \m_load_err_o connect \B \m_store_err_o - connect \Y $or$libresoc.v:146851$7200_Y + connect \Y $or$libresoc.v:147191$7132_Y end - attribute \src "libresoc.v:146625.7-146625.20" - process $proc$libresoc.v:146625$7267 + attribute \src "libresoc.v:146965.7-146965.20" + process $proc$libresoc.v:146965$7199 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146730.14-146730.42" - process $proc$libresoc.v:146730$7268 + attribute \src "libresoc.v:147070.14-147070.42" + process $proc$libresoc.v:147070$7200 assign { } { } assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \dbus__adr $1\dbus__adr[44:0] end - attribute \src "libresoc.v:146735.7-146735.23" - process $proc$libresoc.v:146735$7269 + attribute \src "libresoc.v:147075.7-147075.23" + process $proc$libresoc.v:147075$7201 assign { } { } assign $1\dbus__cyc[0:0] 1'0 sync always sync init update \dbus__cyc $1\dbus__cyc[0:0] end - attribute \src "libresoc.v:146742.14-146742.48" - process $proc$libresoc.v:146742$7270 + attribute \src "libresoc.v:147082.14-147082.48" + process $proc$libresoc.v:147082$7202 assign { } { } assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbus__dat_w $1\dbus__dat_w[63:0] end - attribute \src "libresoc.v:146749.13-146749.30" - process $proc$libresoc.v:146749$7271 + attribute \src "libresoc.v:147089.13-147089.30" + process $proc$libresoc.v:147089$7203 assign { } { } assign $1\dbus__sel[7:0] 8'00000000 sync always sync init update \dbus__sel $1\dbus__sel[7:0] end - attribute \src "libresoc.v:146754.7-146754.23" - process $proc$libresoc.v:146754$7272 + attribute \src "libresoc.v:147094.7-147094.23" + process $proc$libresoc.v:147094$7204 assign { } { } assign $1\dbus__stb[0:0] 1'0 sync always sync init update \dbus__stb $1\dbus__stb[0:0] end - attribute \src "libresoc.v:146759.7-146759.22" - process $proc$libresoc.v:146759$7273 + attribute \src "libresoc.v:147099.7-147099.22" + process $proc$libresoc.v:147099$7205 assign { } { } assign $1\dbus__we[0:0] 1'0 sync always sync init update \dbus__we $1\dbus__we[0:0] end - attribute \src "libresoc.v:146763.14-146763.44" - process $proc$libresoc.v:146763$7274 + attribute \src "libresoc.v:147103.14-147103.44" + process $proc$libresoc.v:147103$7206 assign { } { } assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \m_badaddr_o $1\m_badaddr_o[44:0] end - attribute \src "libresoc.v:146770.14-146770.48" - process $proc$libresoc.v:146770$7275 + attribute \src "libresoc.v:147110.14-147110.48" + process $proc$libresoc.v:147110$7207 assign { } { } assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \m_ld_data_o $1\m_ld_data_o[63:0] end - attribute \src "libresoc.v:146774.7-146774.26" - process $proc$libresoc.v:146774$7276 + attribute \src "libresoc.v:147114.7-147114.26" + process $proc$libresoc.v:147114$7208 assign { } { } assign $1\m_load_err_o[0:0] 1'0 sync always sync init update \m_load_err_o $1\m_load_err_o[0:0] end - attribute \src "libresoc.v:146780.7-146780.27" - process $proc$libresoc.v:146780$7277 + attribute \src "libresoc.v:147120.7-147120.27" + process $proc$libresoc.v:147120$7209 assign { } { } assign $1\m_store_err_o[0:0] 1'0 sync always sync init update \m_store_err_o $1\m_store_err_o[0:0] end - attribute \src "libresoc.v:146852.3-146853.39" - process $proc$libresoc.v:146852$7201 + attribute \src "libresoc.v:147192.3-147193.39" + process $proc$libresoc.v:147192$7133 assign { } { } assign $0\m_badaddr_o[44:0] \m_badaddr_o$next sync posedge \coresync_clk update \m_badaddr_o $0\m_badaddr_o[44:0] end - attribute \src "libresoc.v:146854.3-146855.43" - process $proc$libresoc.v:146854$7202 + attribute \src "libresoc.v:147194.3-147195.43" + process $proc$libresoc.v:147194$7134 assign { } { } assign $0\m_store_err_o[0:0] \m_store_err_o$next sync posedge \coresync_clk update \m_store_err_o $0\m_store_err_o[0:0] end - attribute \src "libresoc.v:146856.3-146857.41" - process $proc$libresoc.v:146856$7203 + attribute \src "libresoc.v:147196.3-147197.41" + process $proc$libresoc.v:147196$7135 assign { } { } assign $0\m_load_err_o[0:0] \m_load_err_o$next sync posedge \coresync_clk update \m_load_err_o $0\m_load_err_o[0:0] end - attribute \src "libresoc.v:146858.3-146859.39" - process $proc$libresoc.v:146858$7204 + attribute \src "libresoc.v:147198.3-147199.39" + process $proc$libresoc.v:147198$7136 assign { } { } assign $0\dbus__dat_w[63:0] \dbus__dat_w$next sync posedge \coresync_clk update \dbus__dat_w $0\dbus__dat_w[63:0] end - attribute \src "libresoc.v:146860.3-146861.33" - process $proc$libresoc.v:146860$7205 + attribute \src "libresoc.v:147200.3-147201.33" + process $proc$libresoc.v:147200$7137 assign { } { } assign $0\dbus__we[0:0] \dbus__we$next sync posedge \coresync_clk update \dbus__we $0\dbus__we[0:0] end - attribute \src "libresoc.v:146862.3-146863.35" - process $proc$libresoc.v:146862$7206 + attribute \src "libresoc.v:147202.3-147203.35" + process $proc$libresoc.v:147202$7138 assign { } { } assign $0\dbus__adr[44:0] \dbus__adr$next sync posedge \coresync_clk update \dbus__adr $0\dbus__adr[44:0] end - attribute \src "libresoc.v:146864.3-146865.39" - process $proc$libresoc.v:146864$7207 + attribute \src "libresoc.v:147204.3-147205.39" + process $proc$libresoc.v:147204$7139 assign { } { } assign $0\m_ld_data_o[63:0] \m_ld_data_o$next sync posedge \coresync_clk update \m_ld_data_o $0\m_ld_data_o[63:0] end - attribute \src "libresoc.v:146866.3-146867.35" - process $proc$libresoc.v:146866$7208 + attribute \src "libresoc.v:147206.3-147207.35" + process $proc$libresoc.v:147206$7140 assign { } { } assign $0\dbus__sel[7:0] \dbus__sel$next sync posedge \coresync_clk update \dbus__sel $0\dbus__sel[7:0] end - attribute \src "libresoc.v:146868.3-146869.35" - process $proc$libresoc.v:146868$7209 + attribute \src "libresoc.v:147208.3-147209.35" + process $proc$libresoc.v:147208$7141 assign { } { } assign $0\dbus__stb[0:0] \dbus__stb$next sync posedge \coresync_clk update \dbus__stb $0\dbus__stb[0:0] end - attribute \src "libresoc.v:146870.3-146871.35" - process $proc$libresoc.v:146870$7210 + attribute \src "libresoc.v:147210.3-147211.35" + process $proc$libresoc.v:147210$7142 assign { } { } assign $0\dbus__cyc[0:0] \dbus__cyc$next sync posedge \coresync_clk update \dbus__cyc $0\dbus__cyc[0:0] end - attribute \src "libresoc.v:146872.3-146899.6" - process $proc$libresoc.v:146872$7211 + attribute \src "libresoc.v:147212.3-147239.6" + process $proc$libresoc.v:147212$7143 assign { } { } assign { } { } assign { } { } - assign $0\dbus__cyc$next[0:0]$7212 $4\dbus__cyc$next[0:0]$7216 - attribute \src "libresoc.v:146873.5-146873.29" + assign $0\dbus__cyc$next[0:0]$7144 $4\dbus__cyc$next[0:0]$7148 + attribute \src "libresoc.v:147213.5-147213.29" switch \initial - attribute \src "libresoc.v:146873.9-146873.17" + attribute \src "libresoc.v:147213.9-147213.17" case 1'1 case end @@ -306881,53 +273100,53 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__cyc$next[0:0]$7213 $2\dbus__cyc$next[0:0]$7214 + assign $1\dbus__cyc$next[0:0]$7145 $2\dbus__cyc$next[0:0]$7146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$7 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__cyc$next[0:0]$7214 $3\dbus__cyc$next[0:0]$7215 + assign $2\dbus__cyc$next[0:0]$7146 $3\dbus__cyc$next[0:0]$7147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__cyc$next[0:0]$7215 1'0 + assign $3\dbus__cyc$next[0:0]$7147 1'0 case - assign $3\dbus__cyc$next[0:0]$7215 \dbus__cyc + assign $3\dbus__cyc$next[0:0]$7147 \dbus__cyc end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__cyc$next[0:0]$7214 1'1 + assign $2\dbus__cyc$next[0:0]$7146 1'1 case - assign $2\dbus__cyc$next[0:0]$7214 \dbus__cyc + assign $2\dbus__cyc$next[0:0]$7146 \dbus__cyc end case - assign $1\dbus__cyc$next[0:0]$7213 \dbus__cyc + assign $1\dbus__cyc$next[0:0]$7145 \dbus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__cyc$next[0:0]$7216 1'0 + assign $4\dbus__cyc$next[0:0]$7148 1'0 case - assign $4\dbus__cyc$next[0:0]$7216 $1\dbus__cyc$next[0:0]$7213 + assign $4\dbus__cyc$next[0:0]$7148 $1\dbus__cyc$next[0:0]$7145 end sync always - update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7212 + update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7144 end - attribute \src "libresoc.v:146900.3-146927.6" - process $proc$libresoc.v:146900$7217 + attribute \src "libresoc.v:147240.3-147267.6" + process $proc$libresoc.v:147240$7149 assign { } { } assign { } { } assign { } { } - assign $0\dbus__stb$next[0:0]$7218 $4\dbus__stb$next[0:0]$7222 - attribute \src "libresoc.v:146901.5-146901.29" + assign $0\dbus__stb$next[0:0]$7150 $4\dbus__stb$next[0:0]$7154 + attribute \src "libresoc.v:147241.5-147241.29" switch \initial - attribute \src "libresoc.v:146901.9-146901.17" + attribute \src "libresoc.v:147241.9-147241.17" case 1'1 case end @@ -306936,52 +273155,52 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__stb$next[0:0]$7219 $2\dbus__stb$next[0:0]$7220 + assign $1\dbus__stb$next[0:0]$7151 $2\dbus__stb$next[0:0]$7152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$21 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__stb$next[0:0]$7220 $3\dbus__stb$next[0:0]$7221 + assign $2\dbus__stb$next[0:0]$7152 $3\dbus__stb$next[0:0]$7153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__stb$next[0:0]$7221 1'0 + assign $3\dbus__stb$next[0:0]$7153 1'0 case - assign $3\dbus__stb$next[0:0]$7221 \dbus__stb + assign $3\dbus__stb$next[0:0]$7153 \dbus__stb end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__stb$next[0:0]$7220 1'1 + assign $2\dbus__stb$next[0:0]$7152 1'1 case - assign $2\dbus__stb$next[0:0]$7220 \dbus__stb + assign $2\dbus__stb$next[0:0]$7152 \dbus__stb end case - assign $1\dbus__stb$next[0:0]$7219 \dbus__stb + assign $1\dbus__stb$next[0:0]$7151 \dbus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__stb$next[0:0]$7222 1'0 + assign $4\dbus__stb$next[0:0]$7154 1'0 case - assign $4\dbus__stb$next[0:0]$7222 $1\dbus__stb$next[0:0]$7219 + assign $4\dbus__stb$next[0:0]$7154 $1\dbus__stb$next[0:0]$7151 end sync always - update \dbus__stb$next $0\dbus__stb$next[0:0]$7218 + update \dbus__stb$next $0\dbus__stb$next[0:0]$7150 end - attribute \src "libresoc.v:146928.3-146937.6" - process $proc$libresoc.v:146928$7223 + attribute \src "libresoc.v:147268.3-147277.6" + process $proc$libresoc.v:147268$7155 assign { } { } assign { } { } assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] - attribute \src "libresoc.v:146929.5-146929.29" + attribute \src "libresoc.v:147269.5-147269.29" switch \initial - attribute \src "libresoc.v:146929.9-146929.17" + attribute \src "libresoc.v:147269.9-147269.17" case 1'1 case end @@ -306997,14 +273216,14 @@ module \lsmem sync always update \x_busy_o $0\x_busy_o[0:0] end - attribute \src "libresoc.v:146938.3-146955.6" - process $proc$libresoc.v:146938$7224 + attribute \src "libresoc.v:147278.3-147295.6" + process $proc$libresoc.v:147278$7156 assign { } { } assign { } { } assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] - attribute \src "libresoc.v:146939.5-146939.29" + attribute \src "libresoc.v:147279.5-147279.29" switch \initial - attribute \src "libresoc.v:146939.9-146939.17" + attribute \src "libresoc.v:147279.9-147279.17" case 1'1 case end @@ -307031,15 +273250,15 @@ module \lsmem sync always update \m_busy_o $0\m_busy_o[0:0] end - attribute \src "libresoc.v:146956.3-146986.6" - process $proc$libresoc.v:146956$7225 + attribute \src "libresoc.v:147296.3-147326.6" + process $proc$libresoc.v:147296$7157 assign { } { } assign { } { } assign { } { } - assign $0\dbus__sel$next[7:0]$7226 $4\dbus__sel$next[7:0]$7230 - attribute \src "libresoc.v:146957.5-146957.29" + assign $0\dbus__sel$next[7:0]$7158 $4\dbus__sel$next[7:0]$7162 + attribute \src "libresoc.v:147297.5-147297.29" switch \initial - attribute \src "libresoc.v:146957.9-146957.17" + attribute \src "libresoc.v:147297.9-147297.17" case 1'1 case end @@ -307048,55 +273267,55 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__sel$next[7:0]$7227 $2\dbus__sel$next[7:0]$7228 + assign $1\dbus__sel$next[7:0]$7159 $2\dbus__sel$next[7:0]$7160 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$35 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__sel$next[7:0]$7228 $3\dbus__sel$next[7:0]$7229 + assign $2\dbus__sel$next[7:0]$7160 $3\dbus__sel$next[7:0]$7161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__sel$next[7:0]$7229 8'00000000 + assign $3\dbus__sel$next[7:0]$7161 8'00000000 case - assign $3\dbus__sel$next[7:0]$7229 \dbus__sel + assign $3\dbus__sel$next[7:0]$7161 \dbus__sel end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__sel$next[7:0]$7228 \x_mask_i + assign $2\dbus__sel$next[7:0]$7160 \x_mask_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__sel$next[7:0]$7228 8'00000000 + assign $2\dbus__sel$next[7:0]$7160 8'00000000 end case - assign $1\dbus__sel$next[7:0]$7227 \dbus__sel + assign $1\dbus__sel$next[7:0]$7159 \dbus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__sel$next[7:0]$7230 8'00000000 + assign $4\dbus__sel$next[7:0]$7162 8'00000000 case - assign $4\dbus__sel$next[7:0]$7230 $1\dbus__sel$next[7:0]$7227 + assign $4\dbus__sel$next[7:0]$7162 $1\dbus__sel$next[7:0]$7159 end sync always - update \dbus__sel$next $0\dbus__sel$next[7:0]$7226 + update \dbus__sel$next $0\dbus__sel$next[7:0]$7158 end - attribute \src "libresoc.v:146987.3-147011.6" - process $proc$libresoc.v:146987$7231 + attribute \src "libresoc.v:147327.3-147351.6" + process $proc$libresoc.v:147327$7163 assign { } { } assign { } { } assign { } { } - assign $0\m_ld_data_o$next[63:0]$7232 $4\m_ld_data_o$next[63:0]$7236 - attribute \src "libresoc.v:146988.5-146988.29" + assign $0\m_ld_data_o$next[63:0]$7164 $4\m_ld_data_o$next[63:0]$7168 + attribute \src "libresoc.v:147328.5-147328.29" switch \initial - attribute \src "libresoc.v:146988.9-146988.17" + attribute \src "libresoc.v:147328.9-147328.17" case 1'1 case end @@ -307105,49 +273324,49 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_ld_data_o$next[63:0]$7233 $2\m_ld_data_o$next[63:0]$7234 + assign $1\m_ld_data_o$next[63:0]$7165 $2\m_ld_data_o$next[63:0]$7166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$49 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_ld_data_o$next[63:0]$7234 $3\m_ld_data_o$next[63:0]$7235 + assign $2\m_ld_data_o$next[63:0]$7166 $3\m_ld_data_o$next[63:0]$7167 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_ld_data_o$next[63:0]$7235 \dbus__dat_r + assign $3\m_ld_data_o$next[63:0]$7167 \dbus__dat_r case - assign $3\m_ld_data_o$next[63:0]$7235 \m_ld_data_o + assign $3\m_ld_data_o$next[63:0]$7167 \m_ld_data_o end case - assign $2\m_ld_data_o$next[63:0]$7234 \m_ld_data_o + assign $2\m_ld_data_o$next[63:0]$7166 \m_ld_data_o end case - assign $1\m_ld_data_o$next[63:0]$7233 \m_ld_data_o + assign $1\m_ld_data_o$next[63:0]$7165 \m_ld_data_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\m_ld_data_o$next[63:0]$7236 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\m_ld_data_o$next[63:0]$7168 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\m_ld_data_o$next[63:0]$7236 $1\m_ld_data_o$next[63:0]$7233 + assign $4\m_ld_data_o$next[63:0]$7168 $1\m_ld_data_o$next[63:0]$7165 end sync always - update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7232 + update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7164 end - attribute \src "libresoc.v:147012.3-147037.6" - process $proc$libresoc.v:147012$7237 + attribute \src "libresoc.v:147352.3-147377.6" + process $proc$libresoc.v:147352$7169 assign { } { } assign { } { } assign { } { } - assign $0\dbus__adr$next[44:0]$7238 $3\dbus__adr$next[44:0]$7241 - attribute \src "libresoc.v:147013.5-147013.29" + assign $0\dbus__adr$next[44:0]$7170 $3\dbus__adr$next[44:0]$7173 + attribute \src "libresoc.v:147353.5-147353.29" switch \initial - attribute \src "libresoc.v:147013.9-147013.17" + attribute \src "libresoc.v:147353.9-147353.17" case 1'1 case end @@ -307156,45 +273375,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__adr$next[44:0]$7239 $2\dbus__adr$next[44:0]$7240 + assign $1\dbus__adr$next[44:0]$7171 $2\dbus__adr$next[44:0]$7172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$63 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__adr$next[44:0]$7240 \dbus__adr + assign $2\dbus__adr$next[44:0]$7172 \dbus__adr attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__adr$next[44:0]$7240 \x_addr_i [47:3] + assign $2\dbus__adr$next[44:0]$7172 \x_addr_i [47:3] attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__adr$next[44:0]$7240 45'000000000000000000000000000000000000000000000 + assign $2\dbus__adr$next[44:0]$7172 45'000000000000000000000000000000000000000000000 end case - assign $1\dbus__adr$next[44:0]$7239 \dbus__adr + assign $1\dbus__adr$next[44:0]$7171 \dbus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__adr$next[44:0]$7241 45'000000000000000000000000000000000000000000000 + assign $3\dbus__adr$next[44:0]$7173 45'000000000000000000000000000000000000000000000 case - assign $3\dbus__adr$next[44:0]$7241 $1\dbus__adr$next[44:0]$7239 + assign $3\dbus__adr$next[44:0]$7173 $1\dbus__adr$next[44:0]$7171 end sync always - update \dbus__adr$next $0\dbus__adr$next[44:0]$7238 + update \dbus__adr$next $0\dbus__adr$next[44:0]$7170 end - attribute \src "libresoc.v:147038.3-147063.6" - process $proc$libresoc.v:147038$7242 + attribute \src "libresoc.v:147378.3-147403.6" + process $proc$libresoc.v:147378$7174 assign { } { } assign { } { } assign { } { } - assign $0\dbus__we$next[0:0]$7243 $3\dbus__we$next[0:0]$7246 - attribute \src "libresoc.v:147039.5-147039.29" + assign $0\dbus__we$next[0:0]$7175 $3\dbus__we$next[0:0]$7178 + attribute \src "libresoc.v:147379.5-147379.29" switch \initial - attribute \src "libresoc.v:147039.9-147039.17" + attribute \src "libresoc.v:147379.9-147379.17" case 1'1 case end @@ -307203,45 +273422,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__we$next[0:0]$7244 $2\dbus__we$next[0:0]$7245 + assign $1\dbus__we$next[0:0]$7176 $2\dbus__we$next[0:0]$7177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$71 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__we$next[0:0]$7245 \dbus__we + assign $2\dbus__we$next[0:0]$7177 \dbus__we attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__we$next[0:0]$7245 \x_st_i + assign $2\dbus__we$next[0:0]$7177 \x_st_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__we$next[0:0]$7245 1'0 + assign $2\dbus__we$next[0:0]$7177 1'0 end case - assign $1\dbus__we$next[0:0]$7244 \dbus__we + assign $1\dbus__we$next[0:0]$7176 \dbus__we end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__we$next[0:0]$7246 1'0 + assign $3\dbus__we$next[0:0]$7178 1'0 case - assign $3\dbus__we$next[0:0]$7246 $1\dbus__we$next[0:0]$7244 + assign $3\dbus__we$next[0:0]$7178 $1\dbus__we$next[0:0]$7176 end sync always - update \dbus__we$next $0\dbus__we$next[0:0]$7243 + update \dbus__we$next $0\dbus__we$next[0:0]$7175 end - attribute \src "libresoc.v:147064.3-147089.6" - process $proc$libresoc.v:147064$7247 + attribute \src "libresoc.v:147404.3-147429.6" + process $proc$libresoc.v:147404$7179 assign { } { } assign { } { } assign { } { } - assign $0\dbus__dat_w$next[63:0]$7248 $3\dbus__dat_w$next[63:0]$7251 - attribute \src "libresoc.v:147065.5-147065.29" + assign $0\dbus__dat_w$next[63:0]$7180 $3\dbus__dat_w$next[63:0]$7183 + attribute \src "libresoc.v:147405.5-147405.29" switch \initial - attribute \src "libresoc.v:147065.9-147065.17" + attribute \src "libresoc.v:147405.9-147405.17" case 1'1 case end @@ -307250,45 +273469,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__dat_w$next[63:0]$7249 $2\dbus__dat_w$next[63:0]$7250 + assign $1\dbus__dat_w$next[63:0]$7181 $2\dbus__dat_w$next[63:0]$7182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$79 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__dat_w$next[63:0]$7250 \dbus__dat_w + assign $2\dbus__dat_w$next[63:0]$7182 \dbus__dat_w attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__dat_w$next[63:0]$7250 \x_st_data_i + assign $2\dbus__dat_w$next[63:0]$7182 \x_st_data_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__dat_w$next[63:0]$7250 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dbus__dat_w$next[63:0]$7182 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\dbus__dat_w$next[63:0]$7249 \dbus__dat_w + assign $1\dbus__dat_w$next[63:0]$7181 \dbus__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__dat_w$next[63:0]$7251 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dbus__dat_w$next[63:0]$7183 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dbus__dat_w$next[63:0]$7251 $1\dbus__dat_w$next[63:0]$7249 + assign $3\dbus__dat_w$next[63:0]$7183 $1\dbus__dat_w$next[63:0]$7181 end sync always - update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7248 + update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7180 end - attribute \src "libresoc.v:147090.3-147112.6" - process $proc$libresoc.v:147090$7252 + attribute \src "libresoc.v:147430.3-147452.6" + process $proc$libresoc.v:147430$7184 assign { } { } assign { } { } assign { } { } - assign $0\m_load_err_o$next[0:0]$7253 $3\m_load_err_o$next[0:0]$7256 - attribute \src "libresoc.v:147091.5-147091.29" + assign $0\m_load_err_o$next[0:0]$7185 $3\m_load_err_o$next[0:0]$7188 + attribute \src "libresoc.v:147431.5-147431.29" switch \initial - attribute \src "libresoc.v:147091.9-147091.17" + attribute \src "libresoc.v:147431.9-147431.17" case 1'1 case end @@ -307297,44 +273516,44 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_load_err_o$next[0:0]$7254 $2\m_load_err_o$next[0:0]$7255 + assign $1\m_load_err_o$next[0:0]$7186 $2\m_load_err_o$next[0:0]$7187 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$83 \$81 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_load_err_o$next[0:0]$7255 \$85 + assign $2\m_load_err_o$next[0:0]$7187 \$85 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\m_load_err_o$next[0:0]$7255 1'0 + assign $2\m_load_err_o$next[0:0]$7187 1'0 case - assign $2\m_load_err_o$next[0:0]$7255 \m_load_err_o + assign $2\m_load_err_o$next[0:0]$7187 \m_load_err_o end case - assign $1\m_load_err_o$next[0:0]$7254 \m_load_err_o + assign $1\m_load_err_o$next[0:0]$7186 \m_load_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_load_err_o$next[0:0]$7256 1'0 + assign $3\m_load_err_o$next[0:0]$7188 1'0 case - assign $3\m_load_err_o$next[0:0]$7256 $1\m_load_err_o$next[0:0]$7254 + assign $3\m_load_err_o$next[0:0]$7188 $1\m_load_err_o$next[0:0]$7186 end sync always - update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7253 + update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7185 end - attribute \src "libresoc.v:147113.3-147135.6" - process $proc$libresoc.v:147113$7257 + attribute \src "libresoc.v:147453.3-147475.6" + process $proc$libresoc.v:147453$7189 assign { } { } assign { } { } assign { } { } - assign $0\m_store_err_o$next[0:0]$7258 $3\m_store_err_o$next[0:0]$7261 - attribute \src "libresoc.v:147114.5-147114.29" + assign $0\m_store_err_o$next[0:0]$7190 $3\m_store_err_o$next[0:0]$7193 + attribute \src "libresoc.v:147454.5-147454.29" switch \initial - attribute \src "libresoc.v:147114.9-147114.17" + attribute \src "libresoc.v:147454.9-147454.17" case 1'1 case end @@ -307343,44 +273562,44 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_store_err_o$next[0:0]$7259 $2\m_store_err_o$next[0:0]$7260 + assign $1\m_store_err_o$next[0:0]$7191 $2\m_store_err_o$next[0:0]$7192 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$89 \$87 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_store_err_o$next[0:0]$7260 \dbus__we + assign $2\m_store_err_o$next[0:0]$7192 \dbus__we attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\m_store_err_o$next[0:0]$7260 1'0 + assign $2\m_store_err_o$next[0:0]$7192 1'0 case - assign $2\m_store_err_o$next[0:0]$7260 \m_store_err_o + assign $2\m_store_err_o$next[0:0]$7192 \m_store_err_o end case - assign $1\m_store_err_o$next[0:0]$7259 \m_store_err_o + assign $1\m_store_err_o$next[0:0]$7191 \m_store_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_store_err_o$next[0:0]$7261 1'0 + assign $3\m_store_err_o$next[0:0]$7193 1'0 case - assign $3\m_store_err_o$next[0:0]$7261 $1\m_store_err_o$next[0:0]$7259 + assign $3\m_store_err_o$next[0:0]$7193 $1\m_store_err_o$next[0:0]$7191 end sync always - update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7258 + update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7190 end - attribute \src "libresoc.v:147136.3-147155.6" - process $proc$libresoc.v:147136$7262 + attribute \src "libresoc.v:147476.3-147495.6" + process $proc$libresoc.v:147476$7194 assign { } { } assign { } { } assign { } { } - assign $0\m_badaddr_o$next[44:0]$7263 $3\m_badaddr_o$next[44:0]$7266 - attribute \src "libresoc.v:147137.5-147137.29" + assign $0\m_badaddr_o$next[44:0]$7195 $3\m_badaddr_o$next[44:0]$7198 + attribute \src "libresoc.v:147477.5-147477.29" switch \initial - attribute \src "libresoc.v:147137.9-147137.17" + attribute \src "libresoc.v:147477.9-147477.17" case 1'1 case end @@ -307389,343 +273608,343 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_badaddr_o$next[44:0]$7264 $2\m_badaddr_o$next[44:0]$7265 + assign $1\m_badaddr_o$next[44:0]$7196 $2\m_badaddr_o$next[44:0]$7197 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$93 \$91 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_badaddr_o$next[44:0]$7265 \dbus__adr + assign $2\m_badaddr_o$next[44:0]$7197 \dbus__adr case - assign $2\m_badaddr_o$next[44:0]$7265 \m_badaddr_o + assign $2\m_badaddr_o$next[44:0]$7197 \m_badaddr_o end case - assign $1\m_badaddr_o$next[44:0]$7264 \m_badaddr_o + assign $1\m_badaddr_o$next[44:0]$7196 \m_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_badaddr_o$next[44:0]$7266 45'000000000000000000000000000000000000000000000 - case - assign $3\m_badaddr_o$next[44:0]$7266 $1\m_badaddr_o$next[44:0]$7264 - end - sync always - update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7263 - end - connect \$9 $or$libresoc.v:146804$7153_Y - connect \$11 $not$libresoc.v:146805$7154_Y - connect \$13 $or$libresoc.v:146806$7155_Y - connect \$15 $or$libresoc.v:146807$7156_Y - connect \$17 $and$libresoc.v:146808$7157_Y - connect \$1 $or$libresoc.v:146809$7158_Y - connect \$19 $not$libresoc.v:146810$7159_Y - connect \$21 $and$libresoc.v:146811$7160_Y - connect \$23 $or$libresoc.v:146812$7161_Y - connect \$25 $not$libresoc.v:146813$7162_Y - connect \$27 $or$libresoc.v:146814$7163_Y - connect \$29 $or$libresoc.v:146815$7164_Y - connect \$31 $and$libresoc.v:146816$7165_Y - connect \$33 $not$libresoc.v:146817$7166_Y - connect \$35 $and$libresoc.v:146818$7167_Y - connect \$37 $or$libresoc.v:146819$7168_Y - connect \$3 $and$libresoc.v:146820$7169_Y - connect \$39 $not$libresoc.v:146821$7170_Y - connect \$41 $or$libresoc.v:146822$7171_Y - connect \$43 $or$libresoc.v:146823$7172_Y - connect \$45 $and$libresoc.v:146824$7173_Y - connect \$47 $not$libresoc.v:146825$7174_Y - connect \$49 $and$libresoc.v:146826$7175_Y - connect \$51 $or$libresoc.v:146827$7176_Y - connect \$53 $not$libresoc.v:146828$7177_Y - connect \$55 $or$libresoc.v:146829$7178_Y - connect \$57 $or$libresoc.v:146830$7179_Y - connect \$5 $not$libresoc.v:146831$7180_Y - connect \$59 $and$libresoc.v:146832$7181_Y - connect \$61 $not$libresoc.v:146833$7182_Y - connect \$63 $and$libresoc.v:146834$7183_Y - connect \$65 $or$libresoc.v:146835$7184_Y - connect \$67 $and$libresoc.v:146836$7185_Y - connect \$69 $not$libresoc.v:146837$7186_Y - connect \$71 $and$libresoc.v:146838$7187_Y - connect \$73 $or$libresoc.v:146839$7188_Y - connect \$75 $and$libresoc.v:146840$7189_Y - connect \$77 $not$libresoc.v:146841$7190_Y - connect \$7 $and$libresoc.v:146842$7191_Y - connect \$79 $and$libresoc.v:146843$7192_Y - connect \$81 $and$libresoc.v:146844$7193_Y - connect \$83 $not$libresoc.v:146845$7194_Y - connect \$85 $not$libresoc.v:146846$7195_Y - connect \$87 $and$libresoc.v:146847$7196_Y - connect \$89 $not$libresoc.v:146848$7197_Y - connect \$91 $and$libresoc.v:146849$7198_Y - connect \$93 $not$libresoc.v:146850$7199_Y - connect \$95 $or$libresoc.v:146851$7200_Y + assign $3\m_badaddr_o$next[44:0]$7198 45'000000000000000000000000000000000000000000000 + case + assign $3\m_badaddr_o$next[44:0]$7198 $1\m_badaddr_o$next[44:0]$7196 + end + sync always + update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7195 + end + connect \$9 $or$libresoc.v:147144$7085_Y + connect \$11 $not$libresoc.v:147145$7086_Y + connect \$13 $or$libresoc.v:147146$7087_Y + connect \$15 $or$libresoc.v:147147$7088_Y + connect \$17 $and$libresoc.v:147148$7089_Y + connect \$1 $or$libresoc.v:147149$7090_Y + connect \$19 $not$libresoc.v:147150$7091_Y + connect \$21 $and$libresoc.v:147151$7092_Y + connect \$23 $or$libresoc.v:147152$7093_Y + connect \$25 $not$libresoc.v:147153$7094_Y + connect \$27 $or$libresoc.v:147154$7095_Y + connect \$29 $or$libresoc.v:147155$7096_Y + connect \$31 $and$libresoc.v:147156$7097_Y + connect \$33 $not$libresoc.v:147157$7098_Y + connect \$35 $and$libresoc.v:147158$7099_Y + connect \$37 $or$libresoc.v:147159$7100_Y + connect \$3 $and$libresoc.v:147160$7101_Y + connect \$39 $not$libresoc.v:147161$7102_Y + connect \$41 $or$libresoc.v:147162$7103_Y + connect \$43 $or$libresoc.v:147163$7104_Y + connect \$45 $and$libresoc.v:147164$7105_Y + connect \$47 $not$libresoc.v:147165$7106_Y + connect \$49 $and$libresoc.v:147166$7107_Y + connect \$51 $or$libresoc.v:147167$7108_Y + connect \$53 $not$libresoc.v:147168$7109_Y + connect \$55 $or$libresoc.v:147169$7110_Y + connect \$57 $or$libresoc.v:147170$7111_Y + connect \$5 $not$libresoc.v:147171$7112_Y + connect \$59 $and$libresoc.v:147172$7113_Y + connect \$61 $not$libresoc.v:147173$7114_Y + connect \$63 $and$libresoc.v:147174$7115_Y + connect \$65 $or$libresoc.v:147175$7116_Y + connect \$67 $and$libresoc.v:147176$7117_Y + connect \$69 $not$libresoc.v:147177$7118_Y + connect \$71 $and$libresoc.v:147178$7119_Y + connect \$73 $or$libresoc.v:147179$7120_Y + connect \$75 $and$libresoc.v:147180$7121_Y + connect \$77 $not$libresoc.v:147181$7122_Y + connect \$7 $and$libresoc.v:147182$7123_Y + connect \$79 $and$libresoc.v:147183$7124_Y + connect \$81 $and$libresoc.v:147184$7125_Y + connect \$83 $not$libresoc.v:147185$7126_Y + connect \$85 $not$libresoc.v:147186$7127_Y + connect \$87 $and$libresoc.v:147187$7128_Y + connect \$89 $not$libresoc.v:147188$7129_Y + connect \$91 $and$libresoc.v:147189$7130_Y + connect \$93 $not$libresoc.v:147190$7131_Y + connect \$95 $or$libresoc.v:147191$7132_Y connect \x_stall_i 1'0 connect \m_stall_i 1'0 end -attribute \src "libresoc.v:147162.1-148123.10" +attribute \src "libresoc.v:147502.1-148535.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" attribute \generator "nMigen" module \main - attribute \src "libresoc.v:147695.3-147717.6" + attribute \src "libresoc.v:148035.3-148057.6" wire width 64 $0\a_i[63:0] - attribute \src "libresoc.v:147794.3-147820.6" + attribute \src "libresoc.v:148134.3-148160.6" wire $0\a_lt[0:0] - attribute \src "libresoc.v:148075.3-148085.6" + attribute \src "libresoc.v:148487.3-148497.6" wire width 64 $0\a_n[63:0] - attribute \src "libresoc.v:148045.3-148054.6" + attribute \src "libresoc.v:148457.3-148466.6" wire width 66 $0\add_a[65:0] - attribute \src "libresoc.v:148055.3-148064.6" + attribute \src "libresoc.v:148467.3-148476.6" wire width 66 $0\add_b[65:0] - attribute \src "libresoc.v:148065.3-148074.6" + attribute \src "libresoc.v:148477.3-148486.6" wire width 66 $0\add_o[65:0] - attribute \src "libresoc.v:147933.3-147955.6" + attribute \src "libresoc.v:148301.3-148323.6" wire width 64 $0\b_i[63:0] - attribute \src "libresoc.v:147919.3-147932.6" + attribute \src "libresoc.v:148283.3-148300.6" wire width 2 $0\ca[1:0] - attribute \src "libresoc.v:148086.3-148096.6" + attribute \src "libresoc.v:148498.3-148508.6" wire $0\carry_32[0:0] - attribute \src "libresoc.v:148097.3-148107.6" + attribute \src "libresoc.v:148509.3-148519.6" wire $0\carry_64[0:0] - attribute \src "libresoc.v:147821.3-147846.6" + attribute \src "libresoc.v:148161.3-148194.6" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:147847.3-147861.6" + attribute \src "libresoc.v:148195.3-148217.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:148025.3-148044.6" + attribute \src "libresoc.v:148425.3-148456.6" wire width 8 $0\eqs[7:0] - attribute \src "libresoc.v:147163.7-147163.20" + attribute \src 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- attribute \src "libresoc.v:147956.3-147966.6" - wire width 2 $0\xer_ca$20[1:0]$7353 - attribute \src "libresoc.v:147967.3-147977.6" + attribute \src "libresoc.v:148324.3-148338.6" + wire width 2 $0\xer_ca$20[1:0]$7285 + attribute \src "libresoc.v:148339.3-148353.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:147992.3-148002.6" + attribute \src "libresoc.v:148372.3-148386.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:148003.3-148013.6" + attribute \src "libresoc.v:148387.3-148401.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:147718.3-147728.6" + attribute \src "libresoc.v:148058.3-148068.6" wire $0\zerohi[0:0] - attribute \src "libresoc.v:148108.3-148118.6" + attribute \src "libresoc.v:148520.3-148530.6" wire $0\zerolo[0:0] - attribute \src "libresoc.v:147695.3-147717.6" + attribute \src "libresoc.v:148035.3-148057.6" wire width 64 $1\a_i[63:0] - attribute \src "libresoc.v:147794.3-147820.6" + attribute \src "libresoc.v:148134.3-148160.6" wire $1\a_lt[0:0] - attribute \src "libresoc.v:148075.3-148085.6" + attribute \src "libresoc.v:148487.3-148497.6" wire width 64 $1\a_n[63:0] - attribute \src "libresoc.v:148045.3-148054.6" + attribute \src "libresoc.v:148457.3-148466.6" wire width 66 $1\add_a[65:0] - attribute \src "libresoc.v:148055.3-148064.6" + attribute \src "libresoc.v:148467.3-148476.6" wire width 66 $1\add_b[65:0] - attribute \src "libresoc.v:148065.3-148074.6" + attribute \src "libresoc.v:148477.3-148486.6" wire width 66 $1\add_o[65:0] - attribute \src "libresoc.v:147933.3-147955.6" + attribute \src "libresoc.v:148301.3-148323.6" wire width 64 $1\b_i[63:0] - attribute \src "libresoc.v:147919.3-147932.6" + attribute \src "libresoc.v:148283.3-148300.6" wire width 2 $1\ca[1:0] - attribute \src "libresoc.v:148086.3-148096.6" + attribute \src "libresoc.v:148498.3-148508.6" wire $1\carry_32[0:0] - attribute \src "libresoc.v:148097.3-148107.6" + attribute \src "libresoc.v:148509.3-148519.6" wire $1\carry_64[0:0] - attribute \src "libresoc.v:147821.3-147846.6" + attribute \src "libresoc.v:148161.3-148194.6" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:147847.3-147861.6" + attribute \src "libresoc.v:148195.3-148217.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:148025.3-148044.6" + attribute \src "libresoc.v:148425.3-148456.6" wire width 8 $1\eqs[7:0] - attribute \src "libresoc.v:147685.3-147694.6" + attribute \src "libresoc.v:148025.3-148034.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:147756.3-147774.6" + attribute \src "libresoc.v:148096.3-148114.6" wire $1\msb_a[0:0] - attribute \src "libresoc.v:147775.3-147793.6" + attribute \src "libresoc.v:148115.3-148133.6" wire $1\msb_b[0:0] - attribute \src "libresoc.v:147862.3-147899.6" + attribute \src "libresoc.v:148218.3-148259.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:147900.3-147918.6" + attribute \src "libresoc.v:148260.3-148282.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:147978.3-147991.6" + attribute \src "libresoc.v:148354.3-148371.6" wire width 2 $1\ov[1:0] - attribute \src "libresoc.v:148014.3-148024.6" + attribute \src "libresoc.v:148402.3-148424.6" wire width 8 $1\src1[7:0] - attribute \src "libresoc.v:147729.3-147755.6" + attribute \src "libresoc.v:148069.3-148095.6" wire width 5 $1\tval[4:0] - attribute \src "libresoc.v:147956.3-147966.6" - wire width 2 $1\xer_ca$20[1:0]$7354 - attribute \src "libresoc.v:147967.3-147977.6" + attribute \src "libresoc.v:148324.3-148338.6" + wire width 2 $1\xer_ca$20[1:0]$7286 + attribute \src "libresoc.v:148339.3-148353.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:147992.3-148002.6" + attribute \src "libresoc.v:148372.3-148386.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:148003.3-148013.6" + attribute \src "libresoc.v:148387.3-148401.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:147718.3-147728.6" + attribute \src "libresoc.v:148058.3-148068.6" wire $1\zerohi[0:0] - attribute \src "libresoc.v:148108.3-148118.6" + attribute \src "libresoc.v:148520.3-148530.6" wire $1\zerolo[0:0] - attribute \src "libresoc.v:147695.3-147717.6" + attribute \src "libresoc.v:148035.3-148057.6" wire width 64 $2\a_i[63:0] - attribute \src "libresoc.v:147794.3-147820.6" + attribute \src "libresoc.v:148134.3-148160.6" wire $2\a_lt[0:0] - attribute \src "libresoc.v:147933.3-147955.6" + attribute \src "libresoc.v:148301.3-148323.6" wire width 64 $2\b_i[63:0] - attribute \src "libresoc.v:147821.3-147846.6" + attribute \src "libresoc.v:148161.3-148194.6" wire width 2 $2\cr_a[3:2] - attribute \src "libresoc.v:147756.3-147774.6" + attribute \src "libresoc.v:148096.3-148114.6" wire $2\msb_a[0:0] - attribute \src "libresoc.v:147775.3-147793.6" + attribute \src "libresoc.v:148115.3-148133.6" wire $2\msb_b[0:0] - attribute \src "libresoc.v:147862.3-147899.6" + attribute \src "libresoc.v:148218.3-148259.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:147729.3-147755.6" + attribute \src "libresoc.v:148069.3-148095.6" wire width 5 $2\tval[4:0] - attribute \src "libresoc.v:147794.3-147820.6" + attribute \src "libresoc.v:148134.3-148160.6" wire $3\a_lt[0:0] - attribute \src "libresoc.v:147862.3-147899.6" + attribute \src "libresoc.v:148218.3-148259.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:147729.3-147755.6" + attribute \src "libresoc.v:148069.3-148095.6" wire width 5 $3\tval[4:0] - attribute \src "libresoc.v:147862.3-147899.6" + attribute \src "libresoc.v:148218.3-148259.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:147660.18-147660.105" - wire width 67 $add$libresoc.v:147660$7314_Y - attribute \src "libresoc.v:147634.19-147634.107" - wire $and$libresoc.v:147634$7288_Y - attribute \src "libresoc.v:147638.19-147638.107" - wire $and$libresoc.v:147638$7292_Y - attribute \src "libresoc.v:147671.18-147671.106" - wire $and$libresoc.v:147671$7325_Y - attribute \src "libresoc.v:147676.18-147676.106" - wire $and$libresoc.v:147676$7330_Y - attribute \src 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$eq$libresoc.v:147645$7299_Y - attribute \src "libresoc.v:147646.19-147646.111" - wire $eq$libresoc.v:147646$7300_Y - attribute \src "libresoc.v:147647.18-147647.118" - wire $eq$libresoc.v:147647$7301_Y - attribute \src "libresoc.v:147649.18-147649.118" - wire $eq$libresoc.v:147649$7303_Y - attribute \src "libresoc.v:147650.18-147650.118" - wire $eq$libresoc.v:147650$7304_Y - attribute \src "libresoc.v:147651.18-147651.118" - wire $eq$libresoc.v:147651$7305_Y - attribute \src "libresoc.v:147652.18-147652.118" - wire $eq$libresoc.v:147652$7306_Y - attribute \src "libresoc.v:147654.18-147654.118" - wire $eq$libresoc.v:147654$7308_Y - attribute \src "libresoc.v:147655.18-147655.118" - wire $eq$libresoc.v:147655$7309_Y - attribute \src "libresoc.v:147657.18-147657.118" - wire $eq$libresoc.v:147657$7311_Y - attribute \src "libresoc.v:147658.18-147658.118" - wire $eq$libresoc.v:147658$7312_Y - attribute \src "libresoc.v:147672.18-147672.107" - wire $ne$libresoc.v:147672$7326_Y - attribute \src "libresoc.v:147683.18-147683.107" - wire $ne$libresoc.v:147683$7337_Y - attribute \src "libresoc.v:147633.19-147633.100" - wire $not$libresoc.v:147633$7287_Y - attribute \src "libresoc.v:147637.19-147637.100" - wire $not$libresoc.v:147637$7291_Y - attribute \src "libresoc.v:147648.18-147648.110" - wire $not$libresoc.v:147648$7302_Y - attribute \src "libresoc.v:147661.18-147661.97" - wire width 64 $not$libresoc.v:147661$7315_Y - attribute \src "libresoc.v:147666.18-147666.99" - wire $not$libresoc.v:147666$7320_Y - attribute \src "libresoc.v:147669.18-147669.99" - wire $not$libresoc.v:147669$7323_Y - attribute \src "libresoc.v:147673.18-147673.99" - wire $not$libresoc.v:147673$7327_Y - attribute \src "libresoc.v:147674.18-147674.99" - wire $not$libresoc.v:147674$7328_Y - attribute \src "libresoc.v:147653.18-147653.104" - wire $or$libresoc.v:147653$7307_Y - attribute \src "libresoc.v:147656.18-147656.104" - wire $or$libresoc.v:147656$7310_Y - attribute \src "libresoc.v:147659.18-147659.104" - wire $or$libresoc.v:147659$7313_Y - attribute \src "libresoc.v:147670.18-147670.110" - wire $or$libresoc.v:147670$7324_Y - attribute \src "libresoc.v:147675.18-147675.110" - wire $or$libresoc.v:147675$7329_Y - attribute \src "libresoc.v:147678.18-147678.110" - wire $or$libresoc.v:147678$7332_Y - attribute \src "libresoc.v:147681.18-147681.110" - wire $or$libresoc.v:147681$7335_Y - attribute \src "libresoc.v:147624.18-147624.98" - wire $reduce_or$libresoc.v:147624$7278_Y - attribute \src "libresoc.v:147628.19-147628.99" - wire $reduce_or$libresoc.v:147628$7282_Y - attribute \src "libresoc.v:147665.18-147665.99" - wire $reduce_or$libresoc.v:147665$7319_Y - attribute \src "libresoc.v:147668.18-147668.99" - wire $reduce_or$libresoc.v:147668$7322_Y - attribute \src "libresoc.v:147677.18-147677.121" - wire $ternary$libresoc.v:147677$7331_Y - attribute \src "libresoc.v:147680.18-147680.119" - wire $ternary$libresoc.v:147680$7334_Y - attribute \src "libresoc.v:147684.18-147684.123" - wire $ternary$libresoc.v:147684$7338_Y - attribute \src "libresoc.v:147629.19-147629.111" - wire $xor$libresoc.v:147629$7283_Y - attribute \src "libresoc.v:147630.19-147630.111" - wire $xor$libresoc.v:147630$7284_Y - attribute \src "libresoc.v:147631.19-147631.110" - wire $xor$libresoc.v:147631$7285_Y - attribute \src "libresoc.v:147632.19-147632.110" - wire $xor$libresoc.v:147632$7286_Y - attribute \src "libresoc.v:147635.19-147635.110" - wire $xor$libresoc.v:147635$7289_Y - attribute \src "libresoc.v:147636.19-147636.110" - wire $xor$libresoc.v:147636$7290_Y - attribute \src "libresoc.v:147662.18-147662.111" - wire $xor$libresoc.v:147662$7316_Y - attribute \src "libresoc.v:147663.18-147663.107" - wire $xor$libresoc.v:147663$7317_Y - attribute \src "libresoc.v:147664.18-147664.113" - wire width 32 $xor$libresoc.v:147664$7318_Y - attribute \src "libresoc.v:147667.18-147667.115" - wire width 32 $xor$libresoc.v:147667$7321_Y + attribute \src "libresoc.v:148000.18-148000.105" + wire width 67 $add$libresoc.v:148000$7246_Y + attribute \src "libresoc.v:147974.19-147974.107" + wire $and$libresoc.v:147974$7220_Y + attribute \src "libresoc.v:147978.19-147978.107" + wire $and$libresoc.v:147978$7224_Y + attribute \src "libresoc.v:148011.18-148011.106" + wire $and$libresoc.v:148011$7257_Y + attribute \src "libresoc.v:148016.18-148016.106" + wire $and$libresoc.v:148016$7262_Y + attribute \src "libresoc.v:148019.18-148019.106" + wire $and$libresoc.v:148019$7265_Y + attribute \src "libresoc.v:148022.18-148022.106" + wire $and$libresoc.v:148022$7268_Y + attribute \src "libresoc.v:147965.19-147965.118" + wire $eq$libresoc.v:147965$7211_Y + attribute \src "libresoc.v:147966.19-147966.118" + wire $eq$libresoc.v:147966$7212_Y + attribute \src "libresoc.v:147967.19-147967.118" + wire $eq$libresoc.v:147967$7213_Y + attribute \src "libresoc.v:147979.19-147979.109" + wire $eq$libresoc.v:147979$7225_Y + attribute \src "libresoc.v:147980.19-147980.110" + wire $eq$libresoc.v:147980$7226_Y + attribute \src "libresoc.v:147981.19-147981.111" + wire $eq$libresoc.v:147981$7227_Y + attribute \src "libresoc.v:147982.19-147982.111" + wire $eq$libresoc.v:147982$7228_Y + attribute \src "libresoc.v:147983.19-147983.111" + wire $eq$libresoc.v:147983$7229_Y + attribute \src "libresoc.v:147984.19-147984.111" + wire $eq$libresoc.v:147984$7230_Y + attribute \src "libresoc.v:147985.19-147985.111" + wire $eq$libresoc.v:147985$7231_Y + attribute \src "libresoc.v:147986.19-147986.111" + wire $eq$libresoc.v:147986$7232_Y + attribute \src "libresoc.v:147987.18-147987.118" + wire $eq$libresoc.v:147987$7233_Y + attribute \src "libresoc.v:147989.18-147989.118" + wire $eq$libresoc.v:147989$7235_Y + attribute \src "libresoc.v:147990.18-147990.118" + wire $eq$libresoc.v:147990$7236_Y + attribute \src "libresoc.v:147991.18-147991.118" + wire $eq$libresoc.v:147991$7237_Y + attribute \src "libresoc.v:147992.18-147992.118" + wire $eq$libresoc.v:147992$7238_Y + attribute \src "libresoc.v:147994.18-147994.118" + wire $eq$libresoc.v:147994$7240_Y + attribute \src "libresoc.v:147995.18-147995.118" + wire $eq$libresoc.v:147995$7241_Y + attribute \src "libresoc.v:147997.18-147997.118" + wire $eq$libresoc.v:147997$7243_Y + attribute \src "libresoc.v:147998.18-147998.118" + wire $eq$libresoc.v:147998$7244_Y + attribute \src "libresoc.v:148012.18-148012.107" + wire $ne$libresoc.v:148012$7258_Y + attribute \src "libresoc.v:148023.18-148023.107" + wire $ne$libresoc.v:148023$7269_Y + attribute \src "libresoc.v:147973.19-147973.100" + wire $not$libresoc.v:147973$7219_Y + attribute \src "libresoc.v:147977.19-147977.100" + wire $not$libresoc.v:147977$7223_Y + attribute \src "libresoc.v:147988.18-147988.110" + wire $not$libresoc.v:147988$7234_Y + attribute \src "libresoc.v:148001.18-148001.97" + wire width 64 $not$libresoc.v:148001$7247_Y + attribute \src "libresoc.v:148006.18-148006.99" + wire $not$libresoc.v:148006$7252_Y + attribute \src "libresoc.v:148009.18-148009.99" + wire $not$libresoc.v:148009$7255_Y + attribute \src "libresoc.v:148013.18-148013.99" + wire $not$libresoc.v:148013$7259_Y + attribute \src "libresoc.v:148014.18-148014.99" + wire $not$libresoc.v:148014$7260_Y + attribute \src "libresoc.v:147993.18-147993.104" + wire $or$libresoc.v:147993$7239_Y + attribute \src "libresoc.v:147996.18-147996.104" + wire $or$libresoc.v:147996$7242_Y + attribute \src "libresoc.v:147999.18-147999.104" + wire $or$libresoc.v:147999$7245_Y + attribute \src "libresoc.v:148010.18-148010.110" + wire $or$libresoc.v:148010$7256_Y + attribute \src "libresoc.v:148015.18-148015.110" + wire $or$libresoc.v:148015$7261_Y + attribute \src "libresoc.v:148018.18-148018.110" + wire $or$libresoc.v:148018$7264_Y + attribute \src "libresoc.v:148021.18-148021.110" + wire $or$libresoc.v:148021$7267_Y + attribute \src "libresoc.v:147964.18-147964.98" + wire $reduce_or$libresoc.v:147964$7210_Y + attribute \src "libresoc.v:147968.19-147968.99" + wire $reduce_or$libresoc.v:147968$7214_Y + attribute \src "libresoc.v:148005.18-148005.99" + wire $reduce_or$libresoc.v:148005$7251_Y + attribute \src "libresoc.v:148008.18-148008.99" + wire $reduce_or$libresoc.v:148008$7254_Y + attribute \src "libresoc.v:148017.18-148017.121" + wire $ternary$libresoc.v:148017$7263_Y + attribute \src "libresoc.v:148020.18-148020.119" + wire $ternary$libresoc.v:148020$7266_Y + attribute \src "libresoc.v:148024.18-148024.123" + wire $ternary$libresoc.v:148024$7270_Y + attribute \src "libresoc.v:147969.19-147969.111" + wire $xor$libresoc.v:147969$7215_Y + attribute \src "libresoc.v:147970.19-147970.111" + wire $xor$libresoc.v:147970$7216_Y + attribute \src "libresoc.v:147971.19-147971.110" + wire $xor$libresoc.v:147971$7217_Y + attribute \src "libresoc.v:147972.19-147972.110" + wire $xor$libresoc.v:147972$7218_Y + attribute \src "libresoc.v:147975.19-147975.110" + wire $xor$libresoc.v:147975$7221_Y + attribute \src "libresoc.v:147976.19-147976.110" + wire $xor$libresoc.v:147976$7222_Y + attribute \src "libresoc.v:148002.18-148002.111" + wire $xor$libresoc.v:148002$7248_Y + attribute \src "libresoc.v:148003.18-148003.107" + wire $xor$libresoc.v:148003$7249_Y + attribute \src "libresoc.v:148004.18-148004.113" + wire width 32 $xor$libresoc.v:148004$7250_Y + attribute \src "libresoc.v:148007.18-148007.115" + wire width 32 $xor$libresoc.v:148007$7253_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" @@ -308130,13 +274349,13 @@ module \main wire \carry_32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" wire \carry_64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 44 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 45 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" wire width 8 \eqs - attribute \src "libresoc.v:147163.7-147163.15" + attribute \src "libresoc.v:147503.7-147503.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" wire \is_32bit @@ -308148,9 +274367,9 @@ module \main wire width 2 input 51 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 42 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 43 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:156" wire width 2 \ov @@ -308164,24 +274383,24 @@ module \main wire width 5 \tval attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 46 \xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 47 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 48 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 49 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 50 \xer_so$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" wire \zerohi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" wire \zerolo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" - cell $add $add$libresoc.v:147660$7314 + cell $add $add$libresoc.v:148000$7246 parameter \A_SIGNED 0 parameter \A_WIDTH 66 parameter \B_SIGNED 0 @@ -308189,10 +274408,10 @@ module \main parameter \Y_WIDTH 67 connect \A \add_a connect \B \add_b - connect \Y $add$libresoc.v:147660$7314_Y + connect \Y $add$libresoc.v:148000$7246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:147634$7288 + cell $and $and$libresoc.v:147974$7220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308200,10 +274419,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$113 connect \B \$115 - connect \Y $and$libresoc.v:147634$7288_Y + connect \Y $and$libresoc.v:147974$7220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:147638$7292 + cell $and $and$libresoc.v:147978$7224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308211,10 +274430,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$121 connect \B \$123 - connect \Y $and$libresoc.v:147638$7292_Y + connect \Y $and$libresoc.v:147978$7224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:147671$7325 + cell $and $and$libresoc.v:148011$7257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308222,10 +274441,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$69 - connect \Y $and$libresoc.v:147671$7325_Y + connect \Y $and$libresoc.v:148011$7257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:147676$7330 + cell $and $and$libresoc.v:148016$7262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308233,10 +274452,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$79 - connect \Y $and$libresoc.v:147676$7330_Y + connect \Y $and$libresoc.v:148016$7262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:147679$7333 + cell $and $and$libresoc.v:148019$7265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308244,10 +274463,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$85 - connect \Y $and$libresoc.v:147679$7333_Y + connect \Y $and$libresoc.v:148019$7265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:147682$7336 + cell $and $and$libresoc.v:148022$7268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308255,10 +274474,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$91 - connect \Y $and$libresoc.v:147682$7336_Y + connect \Y $and$libresoc.v:148022$7268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - cell $eq $eq$libresoc.v:147625$7279 + cell $eq $eq$libresoc.v:147965$7211 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -308266,10 +274485,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 1'1 - connect \Y $eq$libresoc.v:147625$7279_Y + connect \Y $eq$libresoc.v:147965$7211_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" - cell $eq $eq$libresoc.v:147626$7280 + cell $eq $eq$libresoc.v:147966$7212 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -308277,10 +274496,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:147626$7280_Y + connect \Y $eq$libresoc.v:147966$7212_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" - cell $eq $eq$libresoc.v:147627$7281 + cell $eq $eq$libresoc.v:147967$7213 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -308288,10 +274507,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 3'100 - connect \Y $eq$libresoc.v:147627$7281_Y + connect \Y $eq$libresoc.v:147967$7213_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147639$7293 + cell $eq $eq$libresoc.v:147979$7225 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308299,10 +274518,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [7:0] - connect \Y $eq$libresoc.v:147639$7293_Y + connect \Y $eq$libresoc.v:147979$7225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147640$7294 + cell $eq $eq$libresoc.v:147980$7226 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308310,10 +274529,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [15:8] - connect \Y $eq$libresoc.v:147640$7294_Y + connect \Y $eq$libresoc.v:147980$7226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147641$7295 + cell $eq $eq$libresoc.v:147981$7227 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308321,10 +274540,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [23:16] - connect \Y $eq$libresoc.v:147641$7295_Y + connect \Y $eq$libresoc.v:147981$7227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147642$7296 + cell $eq $eq$libresoc.v:147982$7228 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308332,10 +274551,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [31:24] - connect \Y $eq$libresoc.v:147642$7296_Y + connect \Y $eq$libresoc.v:147982$7228_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147643$7297 + cell $eq $eq$libresoc.v:147983$7229 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308343,10 +274562,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [39:32] - connect \Y $eq$libresoc.v:147643$7297_Y + connect \Y $eq$libresoc.v:147983$7229_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147644$7298 + cell $eq $eq$libresoc.v:147984$7230 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308354,10 +274573,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [47:40] - connect \Y $eq$libresoc.v:147644$7298_Y + connect \Y $eq$libresoc.v:147984$7230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147645$7299 + cell $eq $eq$libresoc.v:147985$7231 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308365,10 +274584,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [55:48] - connect \Y $eq$libresoc.v:147645$7299_Y + connect \Y $eq$libresoc.v:147985$7231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147646$7300 + cell $eq $eq$libresoc.v:147986$7232 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308376,10 +274595,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [63:56] - connect \Y $eq$libresoc.v:147646$7300_Y + connect \Y $eq$libresoc.v:147986$7232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" - cell $eq $eq$libresoc.v:147647$7301 + cell $eq $eq$libresoc.v:147987$7233 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308387,10 +274606,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147647$7301_Y + connect \Y $eq$libresoc.v:147987$7233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:147649$7303 + cell $eq $eq$libresoc.v:147989$7235 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308398,10 +274617,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147649$7303_Y + connect \Y $eq$libresoc.v:147989$7235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:147650$7304 + cell $eq $eq$libresoc.v:147990$7236 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308409,10 +274628,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147650$7304_Y + connect \Y $eq$libresoc.v:147990$7236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:147651$7305 + cell $eq $eq$libresoc.v:147991$7237 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308420,10 +274639,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:147651$7305_Y + connect \Y $eq$libresoc.v:147991$7237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:147652$7306 + cell $eq $eq$libresoc.v:147992$7238 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308431,10 +274650,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147652$7306_Y + connect \Y $eq$libresoc.v:147992$7238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:147654$7308 + cell $eq $eq$libresoc.v:147994$7240 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308442,10 +274661,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:147654$7308_Y + connect \Y $eq$libresoc.v:147994$7240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:147655$7309 + cell $eq $eq$libresoc.v:147995$7241 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308453,10 +274672,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147655$7309_Y + connect \Y $eq$libresoc.v:147995$7241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:147657$7311 + cell $eq $eq$libresoc.v:147997$7243 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308464,10 +274683,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:147657$7311_Y + connect \Y $eq$libresoc.v:147997$7243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:147658$7312 + cell $eq $eq$libresoc.v:147998$7244 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308475,10 +274694,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147658$7312_Y + connect \Y $eq$libresoc.v:147998$7244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:147672$7326 + cell $ne $ne$libresoc.v:148012$7258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308486,10 +274705,10 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:147672$7326_Y + connect \Y $ne$libresoc.v:148012$7258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:147683$7337 + cell $ne $ne$libresoc.v:148023$7269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308497,74 +274716,74 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:147683$7337_Y + connect \Y $ne$libresoc.v:148023$7269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:147633$7287 + cell $not $not$libresoc.v:147973$7219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$116 - connect \Y $not$libresoc.v:147633$7287_Y + connect \Y $not$libresoc.v:147973$7219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:147637$7291 + cell $not $not$libresoc.v:147977$7223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$124 - connect \Y $not$libresoc.v:147637$7291_Y + connect \Y $not$libresoc.v:147977$7223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" - cell $not $not$libresoc.v:147648$7302 + cell $not $not$libresoc.v:147988$7234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_op__insn [21] - connect \Y $not$libresoc.v:147648$7302_Y + connect \Y $not$libresoc.v:147988$7234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $not $not$libresoc.v:147661$7315 + cell $not $not$libresoc.v:148001$7247 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:147661$7315_Y + connect \Y $not$libresoc.v:148001$7247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $not $not$libresoc.v:147666$7320 + cell $not $not$libresoc.v:148006$7252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$58 - connect \Y $not$libresoc.v:147666$7320_Y + connect \Y $not$libresoc.v:148006$7252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $not $not$libresoc.v:147669$7323 + cell $not $not$libresoc.v:148009$7255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $not$libresoc.v:147669$7323_Y + connect \Y $not$libresoc.v:148009$7255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:147673$7327 + cell $not $not$libresoc.v:148013$7259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:147673$7327_Y + connect \Y $not$libresoc.v:148013$7259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:147674$7328 + cell $not $not$libresoc.v:148014$7260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:147674$7328_Y + connect \Y $not$libresoc.v:148014$7260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:147653$7307 + cell $or $or$libresoc.v:147993$7239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308572,10 +274791,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:147653$7307_Y + connect \Y $or$libresoc.v:147993$7239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:147656$7310 + cell $or $or$libresoc.v:147996$7242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308583,10 +274802,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:147656$7310_Y + connect \Y $or$libresoc.v:147996$7242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:147659$7313 + cell $or $or$libresoc.v:147999$7245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308594,10 +274813,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$42 connect \B \$44 - connect \Y $or$libresoc.v:147659$7313_Y + connect \Y $or$libresoc.v:147999$7245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:147670$7324 + cell $or $or$libresoc.v:148010$7256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308605,10 +274824,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:147670$7324_Y + connect \Y $or$libresoc.v:148010$7256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:147675$7329 + cell $or $or$libresoc.v:148015$7261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308616,10 +274835,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:147675$7329_Y + connect \Y $or$libresoc.v:148015$7261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:147678$7332 + cell $or $or$libresoc.v:148018$7264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308627,10 +274846,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:147678$7332_Y + connect \Y $or$libresoc.v:148018$7264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:147681$7335 + cell $or $or$libresoc.v:148021$7267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308638,66 +274857,66 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:147681$7335_Y + connect \Y $or$libresoc.v:148021$7267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" - cell $reduce_or $reduce_or$libresoc.v:147624$7278 + cell $reduce_or $reduce_or$libresoc.v:147964$7210 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:147624$7278_Y + connect \Y $reduce_or$libresoc.v:147964$7210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" - cell $reduce_or $reduce_or$libresoc.v:147628$7282 + cell $reduce_or $reduce_or$libresoc.v:147968$7214 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:147628$7282_Y + connect \Y $reduce_or$libresoc.v:147968$7214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $reduce_or $reduce_or$libresoc.v:147665$7319 + cell $reduce_or $reduce_or$libresoc.v:148005$7251 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$59 - connect \Y $reduce_or$libresoc.v:147665$7319_Y + connect \Y $reduce_or$libresoc.v:148005$7251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $reduce_or $reduce_or$libresoc.v:147668$7322 + cell $reduce_or $reduce_or$libresoc.v:148008$7254 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$65 - connect \Y $reduce_or$libresoc.v:147668$7322_Y + connect \Y $reduce_or$libresoc.v:148008$7254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" - cell $mux $ternary$libresoc.v:147677$7331 + cell $mux $ternary$libresoc.v:148017$7263 parameter \WIDTH 1 connect \A \a_n [63] connect \B \a_n [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:147677$7331_Y + connect \Y $ternary$libresoc.v:148017$7263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" - cell $mux $ternary$libresoc.v:147680$7334 + cell $mux $ternary$libresoc.v:148020$7266 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:147680$7334_Y + connect \Y $ternary$libresoc.v:148020$7266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" - cell $mux $ternary$libresoc.v:147684$7338 + cell $mux $ternary$libresoc.v:148024$7270 parameter \WIDTH 1 connect \A \carry_64 connect \B \carry_32 connect \S \is_32bit - connect \Y $ternary$libresoc.v:147684$7338_Y + connect \Y $ternary$libresoc.v:148024$7270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:147629$7283 + cell $xor $xor$libresoc.v:147969$7215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308705,10 +274924,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [32] connect \B \b_i [32] - connect \Y $xor$libresoc.v:147629$7283_Y + connect \Y $xor$libresoc.v:147969$7215_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:147630$7284 + cell $xor $xor$libresoc.v:147970$7216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308716,10 +274935,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \$109 - connect \Y $xor$libresoc.v:147630$7284_Y + connect \Y $xor$libresoc.v:147970$7216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:147631$7285 + cell $xor $xor$libresoc.v:147971$7217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308727,10 +274946,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [0] connect \B \add_o [64] - connect \Y $xor$libresoc.v:147631$7285_Y + connect \Y $xor$libresoc.v:147971$7217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:147632$7286 + cell $xor $xor$libresoc.v:147972$7218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308738,10 +274957,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [63] connect \B \b_i [63] - connect \Y $xor$libresoc.v:147632$7286_Y + connect \Y $xor$libresoc.v:147972$7218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:147635$7289 + cell $xor $xor$libresoc.v:147975$7221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308749,10 +274968,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [1] connect \B \add_o [32] - connect \Y $xor$libresoc.v:147635$7289_Y + connect \Y $xor$libresoc.v:147975$7221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:147636$7290 + cell $xor $xor$libresoc.v:147976$7222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308760,10 +274979,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [31] connect \B \b_i [31] - connect \Y $xor$libresoc.v:147636$7290_Y + connect \Y $xor$libresoc.v:147976$7222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:147662$7316 + cell $xor $xor$libresoc.v:148002$7248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308771,10 +274990,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \ra [32] - connect \Y $xor$libresoc.v:147662$7316_Y + connect \Y $xor$libresoc.v:148002$7248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:147663$7317 + cell $xor $xor$libresoc.v:148003$7249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308782,10 +275001,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$53 connect \B \rb [32] - connect \Y $xor$libresoc.v:147663$7317_Y + connect \Y $xor$libresoc.v:148003$7249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $xor $xor$libresoc.v:147664$7318 + cell $xor $xor$libresoc.v:148004$7250 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -308793,10 +275012,10 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [31:0] connect \B \rb [31:0] - connect \Y $xor$libresoc.v:147664$7318_Y + connect \Y $xor$libresoc.v:148004$7250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $xor $xor$libresoc.v:147667$7321 + cell $xor $xor$libresoc.v:148007$7253 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -308804,24 +275023,24 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [63:32] connect \B \rb [63:32] - connect \Y $xor$libresoc.v:147667$7321_Y + connect \Y $xor$libresoc.v:148007$7253_Y end - attribute \src "libresoc.v:147163.7-147163.20" - process $proc$libresoc.v:147163$7368 + attribute \src "libresoc.v:147503.7-147503.20" + process $proc$libresoc.v:147503$7300 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147685.3-147694.6" - process $proc$libresoc.v:147685$7339 + attribute \src "libresoc.v:148025.3-148034.6" + process $proc$libresoc.v:148025$7271 assign { } { } assign { } { } assign $0\is_32bit[0:0] $1\is_32bit[0:0] - attribute \src "libresoc.v:147686.5-147686.29" + attribute \src "libresoc.v:148026.5-148026.29" switch \initial - attribute \src "libresoc.v:147686.9-147686.17" + attribute \src "libresoc.v:148026.9-148026.17" case 1'1 case end @@ -308837,13 +275056,13 @@ module \main sync always update \is_32bit $0\is_32bit[0:0] end - attribute \src "libresoc.v:147695.3-147717.6" - process $proc$libresoc.v:147695$7340 + attribute \src "libresoc.v:148035.3-148057.6" + process $proc$libresoc.v:148035$7272 assign { } { } assign $0\a_i[63:0] $1\a_i[63:0] - attribute \src "libresoc.v:147696.5-147696.29" + attribute \src "libresoc.v:148036.5-148036.29" switch \initial - attribute \src "libresoc.v:147696.9-147696.17" + attribute \src "libresoc.v:148036.9-148036.17" case 1'1 case end @@ -308876,14 +275095,14 @@ module \main sync always update \a_i $0\a_i[63:0] end - attribute \src "libresoc.v:147718.3-147728.6" - process $proc$libresoc.v:147718$7341 + attribute \src "libresoc.v:148058.3-148068.6" + process $proc$libresoc.v:148058$7273 assign { } { } assign { } { } assign $0\zerohi[0:0] $1\zerohi[0:0] - attribute \src "libresoc.v:147719.5-147719.29" + attribute \src "libresoc.v:148059.5-148059.29" switch \initial - attribute \src "libresoc.v:147719.9-147719.17" + attribute \src "libresoc.v:148059.9-148059.17" case 1'1 case end @@ -308899,14 +275118,14 @@ module \main sync always update \zerohi $0\zerohi[0:0] end - attribute \src "libresoc.v:147729.3-147755.6" - process $proc$libresoc.v:147729$7342 + attribute \src "libresoc.v:148069.3-148095.6" + process $proc$libresoc.v:148069$7274 assign { } { } assign { } { } assign $0\tval[4:0] $1\tval[4:0] - attribute \src "libresoc.v:147730.5-147730.29" + attribute \src "libresoc.v:148070.5-148070.29" switch \initial - attribute \src "libresoc.v:147730.9-147730.17" + attribute \src "libresoc.v:148070.9-148070.17" case 1'1 case end @@ -308944,14 +275163,14 @@ module \main sync always update \tval $0\tval[4:0] end - attribute \src "libresoc.v:147756.3-147774.6" - process $proc$libresoc.v:147756$7343 + attribute \src "libresoc.v:148096.3-148114.6" + process $proc$libresoc.v:148096$7275 assign { } { } assign { } { } assign $0\msb_a[0:0] $1\msb_a[0:0] - attribute \src "libresoc.v:147757.5-147757.29" + attribute \src "libresoc.v:148097.5-148097.29" switch \initial - attribute \src "libresoc.v:147757.9-147757.17" + attribute \src "libresoc.v:148097.9-148097.17" case 1'1 case end @@ -308977,14 +275196,14 @@ module \main sync always update \msb_a $0\msb_a[0:0] end - attribute \src "libresoc.v:147775.3-147793.6" - process $proc$libresoc.v:147775$7344 + attribute \src "libresoc.v:148115.3-148133.6" + process $proc$libresoc.v:148115$7276 assign { } { } assign { } { } assign $0\msb_b[0:0] $1\msb_b[0:0] - attribute \src "libresoc.v:147776.5-147776.29" + attribute \src "libresoc.v:148116.5-148116.29" switch \initial - attribute \src "libresoc.v:147776.9-147776.17" + attribute \src "libresoc.v:148116.9-148116.17" case 1'1 case end @@ -309010,14 +275229,14 @@ module \main sync always update \msb_b $0\msb_b[0:0] end - attribute \src "libresoc.v:147794.3-147820.6" - process $proc$libresoc.v:147794$7345 + attribute \src "libresoc.v:148134.3-148160.6" + process $proc$libresoc.v:148134$7277 assign { } { } assign { } { } assign $0\a_lt[0:0] $1\a_lt[0:0] - attribute \src "libresoc.v:147795.5-147795.29" + attribute \src "libresoc.v:148135.5-148135.29" switch \initial - attribute \src "libresoc.v:147795.9-147795.17" + attribute \src "libresoc.v:148135.9-148135.17" case 1'1 case end @@ -309053,14 +275272,14 @@ module \main sync always update \a_lt $0\a_lt[0:0] end - attribute \src "libresoc.v:147821.3-147846.6" - process $proc$libresoc.v:147821$7346 + attribute \src "libresoc.v:148161.3-148194.6" + process $proc$libresoc.v:148161$7278 assign { } { } assign { } { } assign $0\cr_a[3:0] $1\cr_a[3:0] - attribute \src "libresoc.v:147822.5-147822.29" + attribute \src "libresoc.v:148162.5-148162.29" switch \initial - attribute \src "libresoc.v:147822.9-147822.17" + attribute \src "libresoc.v:148162.9-148162.17" case 1'1 case end @@ -309083,6 +275302,12 @@ module \main assign $2\cr_a[3:2] \tval [1:0] end attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign $1\cr_a[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign $1\cr_a[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" case 7'0001100 assign { } { } assign $1\cr_a[3:0] { 1'0 \$99 2'00 } @@ -309092,14 +275317,14 @@ module \main sync always update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:147847.3-147861.6" - process $proc$libresoc.v:147847$7347 + attribute \src "libresoc.v:148195.3-148217.6" + process $proc$libresoc.v:148195$7279 assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - attribute \src "libresoc.v:147848.5-147848.29" + attribute \src "libresoc.v:148196.5-148196.29" switch \initial - attribute \src "libresoc.v:147848.9-147848.17" + attribute \src "libresoc.v:148196.9-148196.17" case 1'1 case end @@ -309110,6 +275335,12 @@ module \main assign { } { } assign $1\cr_a_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign $1\cr_a_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign $1\cr_a_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0001100 assign { } { } assign $1\cr_a_ok[0:0] 1'1 @@ -309119,20 +275350,23 @@ module \main sync always update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:147862.3-147899.6" - process $proc$libresoc.v:147862$7348 + attribute \src "libresoc.v:148218.3-148259.6" + process $proc$libresoc.v:148218$7280 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:147863.5-147863.29" + attribute \src "libresoc.v:148219.5-148219.29" switch \initial - attribute \src "libresoc.v:147863.9-147863.17" + attribute \src "libresoc.v:148219.9-148219.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\o[63:0] \add_o [64:1] @@ -309179,20 +275413,23 @@ module \main sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:147900.3-147918.6" - process $proc$libresoc.v:147900$7349 + attribute \src "libresoc.v:148260.3-148282.6" + process $proc$libresoc.v:148260$7281 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:147901.5-147901.29" + attribute \src "libresoc.v:148261.5-148261.29" switch \initial - attribute \src "libresoc.v:147901.9-147901.17" + attribute \src "libresoc.v:148261.9-148261.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\o_ok[0:0] 1'1 @@ -309210,20 +275447,23 @@ module \main sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:147919.3-147932.6" - process $proc$libresoc.v:147919$7350 + attribute \src "libresoc.v:148283.3-148300.6" + process $proc$libresoc.v:148283$7282 assign { } { } assign { } { } assign $0\ca[1:0] $1\ca[1:0] - attribute \src "libresoc.v:147920.5-147920.29" + attribute \src "libresoc.v:148284.5-148284.29" switch \initial - attribute \src "libresoc.v:147920.9-147920.17" + attribute \src "libresoc.v:148284.9-148284.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\ca[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\ca[1:0] [0] \add_o [65] @@ -309234,13 +275474,13 @@ module \main sync always update \ca $0\ca[1:0] end - attribute \src "libresoc.v:147933.3-147955.6" - process $proc$libresoc.v:147933$7351 + attribute \src "libresoc.v:148301.3-148323.6" + process $proc$libresoc.v:148301$7283 assign { } { } assign $0\b_i[63:0] $1\b_i[63:0] - attribute \src "libresoc.v:147934.5-147934.29" + attribute \src "libresoc.v:148302.5-148302.29" switch \initial - attribute \src "libresoc.v:147934.9-147934.17" + attribute \src "libresoc.v:148302.9-148302.17" case 1'1 case end @@ -309273,43 +275513,49 @@ module \main sync always update \b_i $0\b_i[63:0] end - attribute \src "libresoc.v:147956.3-147966.6" - process $proc$libresoc.v:147956$7352 + attribute \src "libresoc.v:148324.3-148338.6" + process $proc$libresoc.v:148324$7284 assign { } { } assign { } { } - assign $0\xer_ca$20[1:0]$7353 $1\xer_ca$20[1:0]$7354 - attribute \src "libresoc.v:147957.5-147957.29" + assign $0\xer_ca$20[1:0]$7285 $1\xer_ca$20[1:0]$7286 + attribute \src "libresoc.v:148325.5-148325.29" switch \initial - attribute \src "libresoc.v:147957.9-147957.17" + attribute \src "libresoc.v:148325.9-148325.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\xer_ca$20[1:0]$7286 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } - assign $1\xer_ca$20[1:0]$7354 \ca + assign $1\xer_ca$20[1:0]$7286 \ca case - assign $1\xer_ca$20[1:0]$7354 2'00 + assign $1\xer_ca$20[1:0]$7286 2'00 end sync always - update \xer_ca$20 $0\xer_ca$20[1:0]$7353 + update \xer_ca$20 $0\xer_ca$20[1:0]$7285 end - attribute \src "libresoc.v:147967.3-147977.6" - process $proc$libresoc.v:147967$7355 + attribute \src "libresoc.v:148339.3-148353.6" + process $proc$libresoc.v:148339$7287 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:147968.5-147968.29" + attribute \src "libresoc.v:148340.5-148340.29" switch \initial - attribute \src "libresoc.v:147968.9-147968.17" + attribute \src "libresoc.v:148340.9-148340.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\xer_ca_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\xer_ca_ok[0:0] 1'1 @@ -309319,20 +275565,23 @@ module \main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:147978.3-147991.6" - process $proc$libresoc.v:147978$7356 + attribute \src "libresoc.v:148354.3-148371.6" + process $proc$libresoc.v:148354$7288 assign { } { } assign { } { } assign $0\ov[1:0] $1\ov[1:0] - attribute \src "libresoc.v:147979.5-147979.29" + attribute \src "libresoc.v:148355.5-148355.29" switch \initial - attribute \src "libresoc.v:147979.9-147979.17" + attribute \src "libresoc.v:148355.9-148355.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\ov[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\ov[1:0] [0] \$119 @@ -309343,20 +275592,23 @@ module \main sync always update \ov $0\ov[1:0] end - attribute \src "libresoc.v:147992.3-148002.6" - process $proc$libresoc.v:147992$7357 + attribute \src "libresoc.v:148372.3-148386.6" + process $proc$libresoc.v:148372$7289 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:147993.5-147993.29" + attribute \src "libresoc.v:148373.5-148373.29" switch \initial - attribute \src "libresoc.v:147993.9-147993.17" + attribute \src "libresoc.v:148373.9-148373.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\xer_ov[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\xer_ov[1:0] \ov @@ -309366,20 +275618,23 @@ module \main sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:148003.3-148013.6" - process $proc$libresoc.v:148003$7358 + attribute \src "libresoc.v:148387.3-148401.6" + process $proc$libresoc.v:148387$7290 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:148004.5-148004.29" + attribute \src "libresoc.v:148388.5-148388.29" switch \initial - attribute \src "libresoc.v:148004.9-148004.17" + attribute \src "libresoc.v:148388.9-148388.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\xer_ov_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\xer_ov_ok[0:0] 1'1 @@ -309389,20 +275644,29 @@ module \main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:148014.3-148024.6" - process $proc$libresoc.v:148014$7359 + attribute \src "libresoc.v:148402.3-148424.6" + process $proc$libresoc.v:148402$7291 assign { } { } assign { } { } assign $0\src1[7:0] $1\src1[7:0] - attribute \src "libresoc.v:148015.5-148015.29" + attribute \src "libresoc.v:148403.5-148403.29" switch \initial - attribute \src "libresoc.v:148015.9-148015.17" + attribute \src "libresoc.v:148403.9-148403.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\src1[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign $1\src1[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign $1\src1[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0001100 assign { } { } assign $1\src1[7:0] \ra [7:0] @@ -309412,20 +275676,29 @@ module \main sync always update \src1 $0\src1[7:0] end - attribute \src "libresoc.v:148025.3-148044.6" - process $proc$libresoc.v:148025$7360 + attribute \src "libresoc.v:148425.3-148456.6" + process $proc$libresoc.v:148425$7292 assign { } { } assign { } { } assign $0\eqs[7:0] $1\eqs[7:0] - attribute \src "libresoc.v:148026.5-148026.29" + attribute \src "libresoc.v:148426.5-148426.29" switch \initial - attribute \src "libresoc.v:148026.9-148026.17" + attribute \src "libresoc.v:148426.9-148426.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\eqs[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign $1\eqs[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign $1\eqs[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0001100 assign { } { } assign $1\eqs[7:0] [0] \$129 @@ -309442,14 +275715,14 @@ module \main sync always update \eqs $0\eqs[7:0] end - attribute \src "libresoc.v:148045.3-148054.6" - process $proc$libresoc.v:148045$7361 + attribute \src "libresoc.v:148457.3-148466.6" + process $proc$libresoc.v:148457$7293 assign { } { } assign { } { } assign $0\add_a[65:0] $1\add_a[65:0] - attribute \src "libresoc.v:148046.5-148046.29" + attribute \src "libresoc.v:148458.5-148458.29" switch \initial - attribute \src "libresoc.v:148046.9-148046.17" + attribute \src "libresoc.v:148458.9-148458.17" case 1'1 case end @@ -309465,14 +275738,14 @@ module \main sync always update \add_a $0\add_a[65:0] end - attribute \src "libresoc.v:148055.3-148064.6" - process $proc$libresoc.v:148055$7362 + attribute \src "libresoc.v:148467.3-148476.6" + process $proc$libresoc.v:148467$7294 assign { } { } assign { } { } assign $0\add_b[65:0] $1\add_b[65:0] - attribute \src "libresoc.v:148056.5-148056.29" + attribute \src "libresoc.v:148468.5-148468.29" switch \initial - attribute \src "libresoc.v:148056.9-148056.17" + attribute \src "libresoc.v:148468.9-148468.17" case 1'1 case end @@ -309488,14 +275761,14 @@ module \main sync always update \add_b $0\add_b[65:0] end - attribute \src "libresoc.v:148065.3-148074.6" - process $proc$libresoc.v:148065$7363 + attribute \src "libresoc.v:148477.3-148486.6" + process $proc$libresoc.v:148477$7295 assign { } { } assign { } { } assign $0\add_o[65:0] $1\add_o[65:0] - attribute \src "libresoc.v:148066.5-148066.29" + attribute \src "libresoc.v:148478.5-148478.29" switch \initial - attribute \src "libresoc.v:148066.9-148066.17" + attribute \src "libresoc.v:148478.9-148478.17" case 1'1 case end @@ -309511,14 +275784,14 @@ module \main sync always update \add_o $0\add_o[65:0] end - attribute \src "libresoc.v:148075.3-148085.6" - process $proc$libresoc.v:148075$7364 + attribute \src "libresoc.v:148487.3-148497.6" + process $proc$libresoc.v:148487$7296 assign { } { } assign { } { } assign $0\a_n[63:0] $1\a_n[63:0] - attribute \src "libresoc.v:148076.5-148076.29" + attribute \src "libresoc.v:148488.5-148488.29" switch \initial - attribute \src "libresoc.v:148076.9-148076.17" + attribute \src "libresoc.v:148488.9-148488.17" case 1'1 case end @@ -309534,14 +275807,14 @@ module \main sync always update \a_n $0\a_n[63:0] end - attribute \src "libresoc.v:148086.3-148096.6" - process $proc$libresoc.v:148086$7365 + attribute \src "libresoc.v:148498.3-148508.6" + process $proc$libresoc.v:148498$7297 assign { } { } assign { } { } assign $0\carry_32[0:0] $1\carry_32[0:0] - attribute \src "libresoc.v:148087.5-148087.29" + attribute \src "libresoc.v:148499.5-148499.29" switch \initial - attribute \src "libresoc.v:148087.9-148087.17" + attribute \src "libresoc.v:148499.9-148499.17" case 1'1 case end @@ -309557,14 +275830,14 @@ module \main sync always update \carry_32 $0\carry_32[0:0] end - attribute \src "libresoc.v:148097.3-148107.6" - process $proc$libresoc.v:148097$7366 + attribute \src "libresoc.v:148509.3-148519.6" + process $proc$libresoc.v:148509$7298 assign { } { } assign { } { } assign $0\carry_64[0:0] $1\carry_64[0:0] - attribute \src "libresoc.v:148098.5-148098.29" + attribute \src "libresoc.v:148510.5-148510.29" switch \initial - attribute \src "libresoc.v:148098.9-148098.17" + attribute \src "libresoc.v:148510.9-148510.17" case 1'1 case end @@ -309580,14 +275853,14 @@ module \main sync always update \carry_64 $0\carry_64[0:0] end - attribute \src "libresoc.v:148108.3-148118.6" - process $proc$libresoc.v:148108$7367 + attribute \src "libresoc.v:148520.3-148530.6" + process $proc$libresoc.v:148520$7299 assign { } { } assign { } { } assign $0\zerolo[0:0] $1\zerolo[0:0] - attribute \src "libresoc.v:148109.5-148109.29" + attribute \src "libresoc.v:148521.5-148521.29" switch \initial - attribute \src "libresoc.v:148109.9-148109.17" + attribute \src "libresoc.v:148521.9-148521.17" case 1'1 case end @@ -309603,88 +275876,88 @@ module \main sync always update \zerolo $0\zerolo[0:0] end - connect \$99 $reduce_or$libresoc.v:147624$7278_Y - connect \$101 $eq$libresoc.v:147625$7279_Y - connect \$103 $eq$libresoc.v:147626$7280_Y - connect \$105 $eq$libresoc.v:147627$7281_Y - connect \$107 $reduce_or$libresoc.v:147628$7282_Y - connect \$109 $xor$libresoc.v:147629$7283_Y - connect \$111 $xor$libresoc.v:147630$7284_Y - connect \$113 $xor$libresoc.v:147631$7285_Y - connect \$116 $xor$libresoc.v:147632$7286_Y - connect \$115 $not$libresoc.v:147633$7287_Y - connect \$119 $and$libresoc.v:147634$7288_Y - connect \$121 $xor$libresoc.v:147635$7289_Y - connect \$124 $xor$libresoc.v:147636$7290_Y - connect \$123 $not$libresoc.v:147637$7291_Y - connect \$127 $and$libresoc.v:147638$7292_Y - connect \$129 $eq$libresoc.v:147639$7293_Y - connect \$131 $eq$libresoc.v:147640$7294_Y - connect \$133 $eq$libresoc.v:147641$7295_Y - connect \$135 $eq$libresoc.v:147642$7296_Y - connect \$137 $eq$libresoc.v:147643$7297_Y - connect \$139 $eq$libresoc.v:147644$7298_Y - connect \$141 $eq$libresoc.v:147645$7299_Y - connect \$143 $eq$libresoc.v:147646$7300_Y - connect \$22 $eq$libresoc.v:147647$7301_Y - connect \$24 $not$libresoc.v:147648$7302_Y - connect \$26 $eq$libresoc.v:147649$7303_Y - connect \$28 $eq$libresoc.v:147650$7304_Y - connect \$30 $eq$libresoc.v:147651$7305_Y - connect \$32 $eq$libresoc.v:147652$7306_Y - connect \$34 $or$libresoc.v:147653$7307_Y - connect \$36 $eq$libresoc.v:147654$7308_Y - connect \$38 $eq$libresoc.v:147655$7309_Y - connect \$40 $or$libresoc.v:147656$7310_Y - connect \$42 $eq$libresoc.v:147657$7311_Y - connect \$44 $eq$libresoc.v:147658$7312_Y - connect \$46 $or$libresoc.v:147659$7313_Y - connect \$49 $add$libresoc.v:147660$7314_Y - connect \$51 $not$libresoc.v:147661$7315_Y - connect \$53 $xor$libresoc.v:147662$7316_Y - connect \$55 $xor$libresoc.v:147663$7317_Y - connect \$59 $xor$libresoc.v:147664$7318_Y - connect \$58 $reduce_or$libresoc.v:147665$7319_Y - connect \$57 $not$libresoc.v:147666$7320_Y - connect \$65 $xor$libresoc.v:147667$7321_Y - connect \$64 $reduce_or$libresoc.v:147668$7322_Y - connect \$63 $not$libresoc.v:147669$7323_Y - connect \$69 $or$libresoc.v:147670$7324_Y - connect \$71 $and$libresoc.v:147671$7325_Y - connect \$73 $ne$libresoc.v:147672$7326_Y - connect \$75 $not$libresoc.v:147673$7327_Y - connect \$77 $not$libresoc.v:147674$7328_Y - connect \$79 $or$libresoc.v:147675$7329_Y - connect \$81 $and$libresoc.v:147676$7330_Y - connect \$83 $ternary$libresoc.v:147677$7331_Y - connect \$85 $or$libresoc.v:147678$7332_Y - connect \$87 $and$libresoc.v:147679$7333_Y - connect \$89 $ternary$libresoc.v:147680$7334_Y - connect \$91 $or$libresoc.v:147681$7335_Y - connect \$93 $and$libresoc.v:147682$7336_Y - connect \$95 $ne$libresoc.v:147683$7337_Y - connect \$97 $ternary$libresoc.v:147684$7338_Y + connect \$99 $reduce_or$libresoc.v:147964$7210_Y + connect \$101 $eq$libresoc.v:147965$7211_Y + connect \$103 $eq$libresoc.v:147966$7212_Y + connect \$105 $eq$libresoc.v:147967$7213_Y + connect \$107 $reduce_or$libresoc.v:147968$7214_Y + connect \$109 $xor$libresoc.v:147969$7215_Y + connect \$111 $xor$libresoc.v:147970$7216_Y + connect \$113 $xor$libresoc.v:147971$7217_Y + connect \$116 $xor$libresoc.v:147972$7218_Y + connect \$115 $not$libresoc.v:147973$7219_Y + connect \$119 $and$libresoc.v:147974$7220_Y + connect \$121 $xor$libresoc.v:147975$7221_Y + connect \$124 $xor$libresoc.v:147976$7222_Y + connect \$123 $not$libresoc.v:147977$7223_Y + connect \$127 $and$libresoc.v:147978$7224_Y + connect \$129 $eq$libresoc.v:147979$7225_Y + connect \$131 $eq$libresoc.v:147980$7226_Y + connect \$133 $eq$libresoc.v:147981$7227_Y + connect \$135 $eq$libresoc.v:147982$7228_Y + connect \$137 $eq$libresoc.v:147983$7229_Y + connect \$139 $eq$libresoc.v:147984$7230_Y + connect \$141 $eq$libresoc.v:147985$7231_Y + connect \$143 $eq$libresoc.v:147986$7232_Y + connect \$22 $eq$libresoc.v:147987$7233_Y + connect \$24 $not$libresoc.v:147988$7234_Y + connect \$26 $eq$libresoc.v:147989$7235_Y + connect \$28 $eq$libresoc.v:147990$7236_Y + connect \$30 $eq$libresoc.v:147991$7237_Y + connect \$32 $eq$libresoc.v:147992$7238_Y + connect \$34 $or$libresoc.v:147993$7239_Y + connect \$36 $eq$libresoc.v:147994$7240_Y + connect \$38 $eq$libresoc.v:147995$7241_Y + connect \$40 $or$libresoc.v:147996$7242_Y + connect \$42 $eq$libresoc.v:147997$7243_Y + connect \$44 $eq$libresoc.v:147998$7244_Y + connect \$46 $or$libresoc.v:147999$7245_Y + connect \$49 $add$libresoc.v:148000$7246_Y + connect \$51 $not$libresoc.v:148001$7247_Y + connect \$53 $xor$libresoc.v:148002$7248_Y + connect \$55 $xor$libresoc.v:148003$7249_Y + connect \$59 $xor$libresoc.v:148004$7250_Y + connect \$58 $reduce_or$libresoc.v:148005$7251_Y + connect \$57 $not$libresoc.v:148006$7252_Y + connect \$65 $xor$libresoc.v:148007$7253_Y + connect \$64 $reduce_or$libresoc.v:148008$7254_Y + connect \$63 $not$libresoc.v:148009$7255_Y + connect \$69 $or$libresoc.v:148010$7256_Y + connect \$71 $and$libresoc.v:148011$7257_Y + connect \$73 $ne$libresoc.v:148012$7258_Y + connect \$75 $not$libresoc.v:148013$7259_Y + connect \$77 $not$libresoc.v:148014$7260_Y + connect \$79 $or$libresoc.v:148015$7261_Y + connect \$81 $and$libresoc.v:148016$7262_Y + connect \$83 $ternary$libresoc.v:148017$7263_Y + connect \$85 $or$libresoc.v:148018$7264_Y + connect \$87 $and$libresoc.v:148019$7265_Y + connect \$89 $ternary$libresoc.v:148020$7266_Y + connect \$91 $or$libresoc.v:148021$7267_Y + connect \$93 $and$libresoc.v:148022$7268_Y + connect \$95 $ne$libresoc.v:148023$7269_Y + connect \$97 $ternary$libresoc.v:148024$7270_Y connect \$48 \$49 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$21 \xer_so end -attribute \src "libresoc.v:148127.1-148541.10" +attribute \src "libresoc.v:148539.1-148953.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" attribute \generator "nMigen" module \main$114 - attribute \src "libresoc.v:148128.7-148128.20" + attribute \src "libresoc.v:148540.7-148540.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148493.3-148523.6" + attribute \src "libresoc.v:148905.3-148935.6" wire width 4 $0\mode[3:0] - attribute \src "libresoc.v:148458.3-148492.6" + attribute \src "libresoc.v:148870.3-148904.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:148493.3-148523.6" + attribute \src "libresoc.v:148905.3-148935.6" wire width 4 $1\mode[3:0] - attribute \src "libresoc.v:148458.3-148492.6" + attribute \src "libresoc.v:148870.3-148904.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:148128.7-148128.15" + attribute \src "libresoc.v:148540.7-148540.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" wire width 5 \mb @@ -309698,9 +275971,9 @@ module \main$114 wire width 2 input 44 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 40 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 41 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 18 \ra @@ -309992,14 +276265,14 @@ module \main$114 wire input 9 \sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \sr_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 43 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 42 \xer_so$19 attribute \module_not_derived 1 - attribute \src "libresoc.v:148442.11-148457.4" + attribute \src "libresoc.v:148854.11-148869.4" cell \rotator \rotator connect \arith \rotator_arith connect \carry_out_o \rotator_carry_out_o @@ -310016,22 +276289,22 @@ module \main$114 connect \shift \rotator_shift connect \sign_ext_rs \rotator_sign_ext_rs end - attribute \src "libresoc.v:148128.7-148128.20" - process $proc$libresoc.v:148128$7371 + attribute \src "libresoc.v:148540.7-148540.20" + process $proc$libresoc.v:148540$7303 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:148458.3-148492.6" - process $proc$libresoc.v:148458$7369 + attribute \src "libresoc.v:148870.3-148904.6" + process $proc$libresoc.v:148870$7301 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:148459.5-148459.29" + attribute \src "libresoc.v:148871.5-148871.29" switch \initial - attribute \src "libresoc.v:148459.9-148459.17" + attribute \src "libresoc.v:148871.9-148871.17" case 1'1 case end @@ -310063,14 +276336,14 @@ module \main$114 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:148493.3-148523.6" - process $proc$libresoc.v:148493$7370 + attribute \src "libresoc.v:148905.3-148935.6" + process $proc$libresoc.v:148905$7302 assign { } { } assign { } { } assign $0\mode[3:0] $1\mode[3:0] - attribute \src "libresoc.v:148494.5-148494.29" + attribute \src "libresoc.v:148906.5-148906.29" switch \initial - attribute \src "libresoc.v:148494.9-148494.17" + attribute \src "libresoc.v:148906.9-148906.17" case 1'1 case end @@ -310124,109 +276397,109 @@ module \main$114 connect \me \sr_op__insn [5:1] connect \mb \sr_op__insn [10:6] end -attribute \src "libresoc.v:148545.1-149081.10" +attribute \src "libresoc.v:148957.1-149497.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" attribute \generator "nMigen" module \main$22 - attribute \src "libresoc.v:148988.3-149011.6" + attribute \src "libresoc.v:149404.3-149427.6" wire $0\bc_taken[0:0] - attribute \src "libresoc.v:148867.3-148878.6" + attribute \src "libresoc.v:149279.3-149290.6" wire width 64 $0\br_addr[63:0] - attribute \src "libresoc.v:148879.3-148905.6" + attribute \src "libresoc.v:149291.3-149317.6" wire width 64 $0\br_imm_addr[63:0] - attribute \src "libresoc.v:148906.3-148924.6" + attribute \src "libresoc.v:149318.3-149336.6" wire $0\br_taken[0:0] - attribute \src "libresoc.v:148960.3-148974.6" + attribute \src "libresoc.v:149376.3-149390.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:149038.3-149058.6" + attribute \src "libresoc.v:149454.3-149474.6" wire width 64 $0\ctr_m[63:0] - attribute \src "libresoc.v:149012.3-149024.6" + attribute \src "libresoc.v:149428.3-149440.6" wire width 64 $0\ctr_n[63:0] - attribute \src "libresoc.v:148975.3-148987.6" + attribute \src "libresoc.v:149391.3-149403.6" wire $0\ctr_write[0:0] - attribute \src "libresoc.v:149059.3-149071.6" + attribute \src "libresoc.v:149475.3-149487.6" wire $0\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:149025.3-149037.6" - wire width 64 $0\fast1$10[63:0]$7404 - attribute \src "libresoc.v:148925.3-148939.6" + attribute \src "libresoc.v:149441.3-149453.6" + wire width 64 $0\fast1$10[63:0]$7336 + attribute \src "libresoc.v:149337.3-149355.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:148940.3-148949.6" - wire width 64 $0\fast2$11[63:0]$7396 - attribute \src "libresoc.v:148950.3-148959.6" + attribute \src "libresoc.v:149356.3-149365.6" + wire width 64 $0\fast2$11[63:0]$7328 + attribute \src "libresoc.v:149366.3-149375.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:148546.7-148546.20" + attribute \src "libresoc.v:148958.7-148958.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148988.3-149011.6" + attribute \src "libresoc.v:149404.3-149427.6" wire $1\bc_taken[0:0] - attribute \src "libresoc.v:148867.3-148878.6" + attribute \src "libresoc.v:149279.3-149290.6" wire width 64 $1\br_addr[63:0] - attribute \src "libresoc.v:148879.3-148905.6" + attribute \src "libresoc.v:149291.3-149317.6" wire width 64 $1\br_imm_addr[63:0] - attribute \src "libresoc.v:148906.3-148924.6" + attribute \src "libresoc.v:149318.3-149336.6" wire $1\br_taken[0:0] - attribute \src "libresoc.v:148960.3-148974.6" + attribute \src "libresoc.v:149376.3-149390.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:149038.3-149058.6" + attribute \src "libresoc.v:149454.3-149474.6" wire width 64 $1\ctr_m[63:0] - attribute \src "libresoc.v:149012.3-149024.6" + attribute \src "libresoc.v:149428.3-149440.6" wire width 64 $1\ctr_n[63:0] - attribute \src "libresoc.v:148975.3-148987.6" + attribute \src "libresoc.v:149391.3-149403.6" wire $1\ctr_write[0:0] - attribute \src "libresoc.v:149059.3-149071.6" + attribute \src "libresoc.v:149475.3-149487.6" wire $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:149025.3-149037.6" - wire width 64 $1\fast1$10[63:0]$7405 - attribute \src "libresoc.v:148925.3-148939.6" + attribute \src "libresoc.v:149441.3-149453.6" + wire width 64 $1\fast1$10[63:0]$7337 + attribute \src "libresoc.v:149337.3-149355.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:148940.3-148949.6" - wire width 64 $1\fast2$11[63:0]$7397 - attribute \src "libresoc.v:148950.3-148959.6" + attribute \src "libresoc.v:149356.3-149365.6" + wire width 64 $1\fast2$11[63:0]$7329 + attribute \src "libresoc.v:149366.3-149375.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:148988.3-149011.6" + attribute \src "libresoc.v:149404.3-149427.6" wire $2\bc_taken[0:0] - attribute \src "libresoc.v:148879.3-148905.6" + attribute \src "libresoc.v:149291.3-149317.6" wire width 64 $2\br_imm_addr[63:0] - attribute \src "libresoc.v:149038.3-149058.6" + attribute \src "libresoc.v:149454.3-149474.6" wire width 64 $2\ctr_m[63:0] - attribute \src "libresoc.v:148851.18-148851.119" - wire width 65 $add$libresoc.v:148851$7374_Y - attribute \src "libresoc.v:148866.18-148866.113" - wire width 65 $add$libresoc.v:148866$7390_Y - attribute \src "libresoc.v:148858.18-148858.115" - wire $and$libresoc.v:148858$7381_Y - attribute \src "libresoc.v:148859.18-148859.117" - wire $and$libresoc.v:148859$7382_Y - attribute \src "libresoc.v:148865.18-148865.118" - wire $and$libresoc.v:148865$7389_Y - attribute \src "libresoc.v:148849.18-148849.120" - wire $eq$libresoc.v:148849$7372_Y - attribute \src "libresoc.v:148852.18-148852.111" - wire $eq$libresoc.v:148852$7375_Y - attribute \src "libresoc.v:148854.18-148854.111" - wire $eq$libresoc.v:148854$7377_Y - attribute \src "libresoc.v:148855.18-148855.111" - wire $eq$libresoc.v:148855$7378_Y - attribute \src "libresoc.v:148856.18-148856.109" - wire $eq$libresoc.v:148856$7379_Y - attribute \src "libresoc.v:148861.18-148861.98" - wire width 64 $extend$libresoc.v:148861$7384_Y - attribute \src "libresoc.v:148857.18-148857.104" - wire $not$libresoc.v:148857$7380_Y - attribute \src "libresoc.v:148864.18-148864.112" - wire $not$libresoc.v:148864$7388_Y - attribute \src "libresoc.v:148850.18-148850.116" - wire $or$libresoc.v:148850$7373_Y - attribute \src "libresoc.v:148853.18-148853.109" - wire $or$libresoc.v:148853$7376_Y - attribute \src "libresoc.v:148861.18-148861.98" - wire width 64 $pos$libresoc.v:148861$7385_Y - attribute \src "libresoc.v:148862.18-148862.103" - wire $reduce_or$libresoc.v:148862$7386_Y - attribute \src "libresoc.v:148860.18-148860.108" - wire width 65 $sub$libresoc.v:148860$7383_Y - attribute \src "libresoc.v:148863.18-148863.108" - wire $xor$libresoc.v:148863$7387_Y + attribute \src "libresoc.v:149263.18-149263.119" + wire width 65 $add$libresoc.v:149263$7306_Y + attribute \src "libresoc.v:149278.18-149278.113" + wire width 65 $add$libresoc.v:149278$7322_Y + attribute \src "libresoc.v:149270.18-149270.115" + wire $and$libresoc.v:149270$7313_Y + attribute \src "libresoc.v:149271.18-149271.117" + wire $and$libresoc.v:149271$7314_Y + attribute \src "libresoc.v:149277.18-149277.118" + wire $and$libresoc.v:149277$7321_Y + attribute \src "libresoc.v:149261.18-149261.120" + wire $eq$libresoc.v:149261$7304_Y + attribute \src "libresoc.v:149264.18-149264.111" + wire $eq$libresoc.v:149264$7307_Y + attribute \src "libresoc.v:149266.18-149266.111" + wire $eq$libresoc.v:149266$7309_Y + attribute \src "libresoc.v:149267.18-149267.111" + wire $eq$libresoc.v:149267$7310_Y + attribute \src "libresoc.v:149268.18-149268.109" + wire $eq$libresoc.v:149268$7311_Y + attribute \src "libresoc.v:149273.18-149273.98" + wire width 64 $extend$libresoc.v:149273$7316_Y + attribute \src "libresoc.v:149269.18-149269.104" + wire $not$libresoc.v:149269$7312_Y + attribute \src "libresoc.v:149276.18-149276.112" + wire $not$libresoc.v:149276$7320_Y + attribute \src "libresoc.v:149262.18-149262.116" + wire $or$libresoc.v:149262$7305_Y + attribute \src "libresoc.v:149265.18-149265.109" + wire $or$libresoc.v:149265$7308_Y + attribute \src "libresoc.v:149273.18-149273.98" + wire width 64 $pos$libresoc.v:149273$7317_Y + attribute \src "libresoc.v:149274.18-149274.103" + wire $reduce_or$libresoc.v:149274$7318_Y + attribute \src "libresoc.v:149272.18-149272.108" + wire width 65 $sub$libresoc.v:149272$7315_Y + attribute \src "libresoc.v:149275.18-149275.108" + wire $xor$libresoc.v:149275$7319_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" @@ -310507,28 +276780,28 @@ module \main$22 wire \ctr_zero_bo1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 9 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 21 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 22 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 10 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 23 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 24 \fast2_ok - attribute \src "libresoc.v:148546.7-148546.15" + attribute \src "libresoc.v:148958.7-148958.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 27 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 12 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 25 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 26 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - cell $add $add$libresoc.v:148851$7374 + cell $add $add$libresoc.v:149263$7306 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -310536,10 +276809,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_imm_addr connect \B \br_op__cia - connect \Y $add$libresoc.v:148851$7374_Y + connect \Y $add$libresoc.v:149263$7306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - cell $add $add$libresoc.v:148866$7390 + cell $add $add$libresoc.v:149278$7322 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -310547,10 +276820,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:148866$7390_Y + connect \Y $add$libresoc.v:149278$7322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $and $and$libresoc.v:148858$7381 + cell $and $and$libresoc.v:149270$7313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310558,10 +276831,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \$29 - connect \Y $and$libresoc.v:148858$7381_Y + connect \Y $and$libresoc.v:149270$7313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" - cell $and $and$libresoc.v:148859$7382 + cell $and $and$libresoc.v:149271$7314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310569,10 +276842,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \cr_bit - connect \Y $and$libresoc.v:148859$7382_Y + connect \Y $and$libresoc.v:149271$7314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $and $and$libresoc.v:148865$7389 + cell $and $and$libresoc.v:149277$7321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310580,10 +276853,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [10] connect \B \$44 - connect \Y $and$libresoc.v:148865$7389_Y + connect \Y $and$libresoc.v:149277$7321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $eq $eq$libresoc.v:148849$7372 + cell $eq $eq$libresoc.v:149261$7304 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -310591,10 +276864,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn_type connect \B 7'0001000 - connect \Y $eq$libresoc.v:148849$7372_Y + connect \Y $eq$libresoc.v:149261$7304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $eq $eq$libresoc.v:148852$7375 + cell $eq $eq$libresoc.v:149264$7307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310602,10 +276875,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \cr_bit connect \B \bo [3] - connect \Y $eq$libresoc.v:148852$7375_Y + connect \Y $eq$libresoc.v:149264$7307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - cell $eq $eq$libresoc.v:148854$7377 + cell $eq $eq$libresoc.v:149266$7309 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -310613,10 +276886,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'0 - connect \Y $eq$libresoc.v:148854$7377_Y + connect \Y $eq$libresoc.v:149266$7309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - cell $eq $eq$libresoc.v:148855$7378 + cell $eq $eq$libresoc.v:149267$7310 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -310624,10 +276897,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'1 - connect \Y $eq$libresoc.v:148855$7378_Y + connect \Y $eq$libresoc.v:149267$7310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - cell $eq $eq$libresoc.v:148856$7379 + cell $eq $eq$libresoc.v:149268$7311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310635,34 +276908,34 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4] connect \B 1'1 - connect \Y $eq$libresoc.v:148856$7379_Y + connect \Y $eq$libresoc.v:149268$7311_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:148861$7384 + cell $pos $extend$libresoc.v:149273$7316 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \fast1 [31:0] - connect \Y $extend$libresoc.v:148861$7384_Y + connect \Y $extend$libresoc.v:149273$7316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $not $not$libresoc.v:148857$7380 + cell $not $not$libresoc.v:149269$7312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_bit - connect \Y $not$libresoc.v:148857$7380_Y + connect \Y $not$libresoc.v:149269$7312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $not $not$libresoc.v:148864$7388 + cell $not $not$libresoc.v:149276$7320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \br_op__insn [6] - connect \Y $not$libresoc.v:148864$7388_Y + connect \Y $not$libresoc.v:149276$7320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $or $or$libresoc.v:148850$7373 + cell $or $or$libresoc.v:149262$7305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310670,10 +276943,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [1] connect \B \$12 - connect \Y $or$libresoc.v:148850$7373_Y + connect \Y $or$libresoc.v:149262$7305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $or $or$libresoc.v:148853$7376 + cell $or $or$libresoc.v:149265$7308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310681,26 +276954,26 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \$19 connect \B \bo [4] - connect \Y $or$libresoc.v:148853$7376_Y + connect \Y $or$libresoc.v:149265$7308_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:148861$7385 + cell $pos $pos$libresoc.v:149273$7317 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148861$7384_Y - connect \Y $pos$libresoc.v:148861$7385_Y + connect \A $extend$libresoc.v:149273$7316_Y + connect \Y $pos$libresoc.v:149273$7317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $reduce_or $reduce_or$libresoc.v:148862$7386 + cell $reduce_or $reduce_or$libresoc.v:149274$7318 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \ctr_n - connect \Y $reduce_or$libresoc.v:148862$7386_Y + connect \Y $reduce_or$libresoc.v:149274$7318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - cell $sub $sub$libresoc.v:148860$7383 + cell $sub $sub$libresoc.v:149272$7315 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -310708,10 +276981,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \fast1 connect \B 1'1 - connect \Y $sub$libresoc.v:148860$7383_Y + connect \Y $sub$libresoc.v:149272$7315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $xor $xor$libresoc.v:148863$7387 + cell $xor $xor$libresoc.v:149275$7319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310719,23 +276992,23 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [1] connect \B \$40 - connect \Y $xor$libresoc.v:148863$7387_Y + connect \Y $xor$libresoc.v:149275$7319_Y end - attribute \src "libresoc.v:148546.7-148546.20" - process $proc$libresoc.v:148546$7408 + attribute \src "libresoc.v:148958.7-148958.20" + process $proc$libresoc.v:148958$7340 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:148867.3-148878.6" - process $proc$libresoc.v:148867$7391 + attribute \src "libresoc.v:149279.3-149290.6" + process $proc$libresoc.v:149279$7323 assign { } { } assign $0\br_addr[63:0] $1\br_addr[63:0] - attribute \src "libresoc.v:148868.5-148868.29" + attribute \src "libresoc.v:149280.5-149280.29" switch \initial - attribute \src "libresoc.v:148868.9-148868.17" + attribute \src "libresoc.v:149280.9-149280.17" case 1'1 case end @@ -310753,14 +277026,14 @@ module \main$22 sync always update \br_addr $0\br_addr[63:0] end - attribute \src "libresoc.v:148879.3-148905.6" - process $proc$libresoc.v:148879$7392 + attribute \src "libresoc.v:149291.3-149317.6" + process $proc$libresoc.v:149291$7324 assign { } { } assign { } { } assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] - attribute \src "libresoc.v:148880.5-148880.29" + attribute \src "libresoc.v:149292.5-149292.29" switch \initial - attribute \src "libresoc.v:148880.9-148880.17" + attribute \src "libresoc.v:149292.9-149292.17" case 1'1 case end @@ -310795,14 +277068,14 @@ module \main$22 sync always update \br_imm_addr $0\br_imm_addr[63:0] end - attribute \src "libresoc.v:148906.3-148924.6" - process $proc$libresoc.v:148906$7393 + attribute \src "libresoc.v:149318.3-149336.6" + process $proc$libresoc.v:149318$7325 assign { } { } assign { } { } assign $0\br_taken[0:0] $1\br_taken[0:0] - attribute \src "libresoc.v:148907.5-148907.29" + attribute \src "libresoc.v:149319.5-149319.29" switch \initial - attribute \src "libresoc.v:148907.9-148907.17" + attribute \src "libresoc.v:149319.9-149319.17" case 1'1 case end @@ -310826,20 +277099,23 @@ module \main$22 sync always update \br_taken $0\br_taken[0:0] end - attribute \src "libresoc.v:148925.3-148939.6" - process $proc$libresoc.v:148925$7394 + attribute \src "libresoc.v:149337.3-149355.6" + process $proc$libresoc.v:149337$7326 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:148926.5-148926.29" + attribute \src "libresoc.v:149338.5-149338.29" switch \initial - attribute \src "libresoc.v:148926.9-148926.17" + attribute \src "libresoc.v:149338.9-149338.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" switch \br_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000110 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0000111 assign { } { } assign $1\fast1_ok[0:0] \ctr_write @@ -310853,14 +277129,14 @@ module \main$22 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:148940.3-148949.6" - process $proc$libresoc.v:148940$7395 + attribute \src "libresoc.v:149356.3-149365.6" + process $proc$libresoc.v:149356$7327 assign { } { } assign { } { } - assign $0\fast2$11[63:0]$7396 $1\fast2$11[63:0]$7397 - attribute \src "libresoc.v:148941.5-148941.29" + assign $0\fast2$11[63:0]$7328 $1\fast2$11[63:0]$7329 + attribute \src "libresoc.v:149357.5-149357.29" switch \initial - attribute \src "libresoc.v:148941.9-148941.17" + attribute \src "libresoc.v:149357.9-149357.17" case 1'1 case end @@ -310869,21 +277145,21 @@ module \main$22 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fast2$11[63:0]$7397 \$48 [63:0] + assign $1\fast2$11[63:0]$7329 \$48 [63:0] case - assign $1\fast2$11[63:0]$7397 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$11[63:0]$7329 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast2$11 $0\fast2$11[63:0]$7396 + update \fast2$11 $0\fast2$11[63:0]$7328 end - attribute \src "libresoc.v:148950.3-148959.6" - process $proc$libresoc.v:148950$7398 + attribute \src "libresoc.v:149366.3-149375.6" + process $proc$libresoc.v:149366$7330 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:148951.5-148951.29" + attribute \src "libresoc.v:149367.5-149367.29" switch \initial - attribute \src "libresoc.v:148951.9-148951.17" + attribute \src "libresoc.v:149367.9-149367.17" case 1'1 case end @@ -310899,14 +277175,14 @@ module \main$22 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:148960.3-148974.6" - process $proc$libresoc.v:148960$7399 + attribute \src "libresoc.v:149376.3-149390.6" + process $proc$libresoc.v:149376$7331 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:148961.5-148961.29" + attribute \src "libresoc.v:149377.5-149377.29" switch \initial - attribute \src "libresoc.v:148961.9-148961.17" + attribute \src "libresoc.v:149377.9-149377.17" case 1'1 case end @@ -310934,14 +277210,14 @@ module \main$22 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:148975.3-148987.6" - process $proc$libresoc.v:148975$7400 + attribute \src "libresoc.v:149391.3-149403.6" + process $proc$libresoc.v:149391$7332 assign { } { } assign { } { } assign $0\ctr_write[0:0] $1\ctr_write[0:0] - attribute \src "libresoc.v:148976.5-148976.29" + attribute \src "libresoc.v:149392.5-149392.29" switch \initial - attribute \src "libresoc.v:148976.9-148976.17" + attribute \src "libresoc.v:149392.9-149392.17" case 1'1 case end @@ -310958,14 +277234,14 @@ module \main$22 sync always update \ctr_write $0\ctr_write[0:0] end - attribute \src "libresoc.v:148988.3-149011.6" - process $proc$libresoc.v:148988$7401 + attribute \src "libresoc.v:149404.3-149427.6" + process $proc$libresoc.v:149404$7333 assign { } { } assign { } { } assign $0\bc_taken[0:0] $1\bc_taken[0:0] - attribute \src "libresoc.v:148989.5-148989.29" + attribute \src "libresoc.v:149405.5-149405.29" switch \initial - attribute \src "libresoc.v:148989.9-148989.17" + attribute \src "libresoc.v:149405.9-149405.17" case 1'1 case end @@ -311000,14 +277276,14 @@ module \main$22 sync always update \bc_taken $0\bc_taken[0:0] end - attribute \src "libresoc.v:149012.3-149024.6" - process $proc$libresoc.v:149012$7402 + attribute \src "libresoc.v:149428.3-149440.6" + process $proc$libresoc.v:149428$7334 assign { } { } assign { } { } assign $0\ctr_n[63:0] $1\ctr_n[63:0] - attribute \src "libresoc.v:149013.5-149013.29" + attribute \src "libresoc.v:149429.5-149429.29" switch \initial - attribute \src "libresoc.v:149013.9-149013.17" + attribute \src "libresoc.v:149429.9-149429.17" case 1'1 case end @@ -311024,14 +277300,14 @@ module \main$22 sync always update \ctr_n $0\ctr_n[63:0] end - attribute \src "libresoc.v:149025.3-149037.6" - process $proc$libresoc.v:149025$7403 + attribute \src "libresoc.v:149441.3-149453.6" + process $proc$libresoc.v:149441$7335 assign { } { } assign { } { } - assign $0\fast1$10[63:0]$7404 $1\fast1$10[63:0]$7405 - attribute \src "libresoc.v:149026.5-149026.29" + assign $0\fast1$10[63:0]$7336 $1\fast1$10[63:0]$7337 + attribute \src "libresoc.v:149442.5-149442.29" switch \initial - attribute \src "libresoc.v:149026.9-149026.17" + attribute \src "libresoc.v:149442.9-149442.17" case 1'1 case end @@ -311039,23 +277315,23 @@ module \main$22 switch \bo [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $1\fast1$10[63:0]$7405 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$10[63:0]$7337 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\fast1$10[63:0]$7405 \ctr_n + assign $1\fast1$10[63:0]$7337 \ctr_n end sync always - update \fast1$10 $0\fast1$10[63:0]$7404 + update \fast1$10 $0\fast1$10[63:0]$7336 end - attribute \src "libresoc.v:149038.3-149058.6" - process $proc$libresoc.v:149038$7406 + attribute \src "libresoc.v:149454.3-149474.6" + process $proc$libresoc.v:149454$7338 assign { } { } assign { } { } assign $0\ctr_m[63:0] $1\ctr_m[63:0] - attribute \src "libresoc.v:149039.5-149039.29" + attribute \src "libresoc.v:149455.5-149455.29" switch \initial - attribute \src "libresoc.v:149039.9-149039.17" + attribute \src "libresoc.v:149455.9-149455.17" case 1'1 case end @@ -311083,14 +277359,14 @@ module \main$22 sync always update \ctr_m $0\ctr_m[63:0] end - attribute \src "libresoc.v:149059.3-149071.6" - process $proc$libresoc.v:149059$7407 + attribute \src "libresoc.v:149475.3-149487.6" + process $proc$libresoc.v:149475$7339 assign { } { } assign { } { } assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:149060.5-149060.29" + attribute \src "libresoc.v:149476.5-149476.29" switch \initial - attribute \src "libresoc.v:149060.9-149060.17" + attribute \src "libresoc.v:149476.9-149476.17" case 1'1 case end @@ -311107,24 +277383,24 @@ module \main$22 sync always update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] end - connect \$12 $eq$libresoc.v:148849$7372_Y - connect \$14 $or$libresoc.v:148850$7373_Y - connect \$17 $add$libresoc.v:148851$7374_Y - connect \$19 $eq$libresoc.v:148852$7375_Y - connect \$21 $or$libresoc.v:148853$7376_Y - connect \$23 $eq$libresoc.v:148854$7377_Y - connect \$25 $eq$libresoc.v:148855$7378_Y - connect \$27 $eq$libresoc.v:148856$7379_Y - connect \$29 $not$libresoc.v:148857$7380_Y - connect \$31 $and$libresoc.v:148858$7381_Y - connect \$33 $and$libresoc.v:148859$7382_Y - connect \$36 $sub$libresoc.v:148860$7383_Y - connect \$38 $pos$libresoc.v:148861$7385_Y - connect \$40 $reduce_or$libresoc.v:148862$7386_Y - connect \$42 $xor$libresoc.v:148863$7387_Y - connect \$44 $not$libresoc.v:148864$7388_Y - connect \$46 $and$libresoc.v:148865$7389_Y - connect \$49 $add$libresoc.v:148866$7390_Y + connect \$12 $eq$libresoc.v:149261$7304_Y + connect \$14 $or$libresoc.v:149262$7305_Y + connect \$17 $add$libresoc.v:149263$7306_Y + connect \$19 $eq$libresoc.v:149264$7307_Y + connect \$21 $or$libresoc.v:149265$7308_Y + connect \$23 $eq$libresoc.v:149266$7309_Y + connect \$25 $eq$libresoc.v:149267$7310_Y + connect \$27 $eq$libresoc.v:149268$7311_Y + connect \$29 $not$libresoc.v:149269$7312_Y + connect \$31 $and$libresoc.v:149270$7313_Y + connect \$33 $and$libresoc.v:149271$7314_Y + connect \$36 $sub$libresoc.v:149272$7315_Y + connect \$38 $pos$libresoc.v:149273$7317_Y + connect \$40 $reduce_or$libresoc.v:149274$7318_Y + connect \$42 $xor$libresoc.v:149275$7319_Y + connect \$44 $not$libresoc.v:149276$7320_Y + connect \$46 $and$libresoc.v:149277$7321_Y + connect \$49 $add$libresoc.v:149278$7322_Y connect \$16 \$17 connect \$35 \$36 connect \$48 \$49 @@ -311135,279 +277411,279 @@ module \main$22 connect \bi \br_op__insn [17:16] connect \bo \br_op__insn [25:21] end -attribute \src "libresoc.v:149085.1-150035.10" +attribute \src "libresoc.v:149501.1-150451.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" attribute \generator "nMigen" module \main$38 - attribute \src "libresoc.v:150000.3-150011.6" + attribute \src "libresoc.v:150416.3-150427.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:149498.3-149509.6" + attribute \src "libresoc.v:149914.3-149925.6" wire width 64 $0\a_s[63:0] - attribute \src "libresoc.v:150012.3-150023.6" + attribute \src "libresoc.v:150428.3-150439.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:149781.3-149792.6" + attribute \src "libresoc.v:150197.3-150208.6" wire width 64 $0\b_s[63:0] - attribute \src "libresoc.v:149574.3-149605.6" - wire width 64 $0\fast1$11[63:0]$7454 - attribute \src "libresoc.v:149606.3-149637.6" + attribute \src "libresoc.v:149990.3-150021.6" + wire width 64 $0\fast1$11[63:0]$7386 + attribute \src "libresoc.v:150022.3-150053.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:149638.3-149720.6" - wire width 64 $0\fast2$12[63:0]$7459 - attribute \src "libresoc.v:149721.3-149752.6" + attribute \src "libresoc.v:150054.3-150136.6" + wire width 64 $0\fast2$12[63:0]$7391 + attribute \src "libresoc.v:150137.3-150168.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:149086.7-149086.20" + attribute \src "libresoc.v:149502.7-149502.20" wire $0\initial[0:0] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150209.3-150377.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150209.3-150377.6" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:149510.3-149541.6" + attribute \src "libresoc.v:149926.3-149957.6" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:149542.3-149573.6" + attribute \src "libresoc.v:149958.3-149989.6" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:149962.3-149980.6" + attribute \src "libresoc.v:150378.3-150396.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:149981.3-149999.6" + attribute \src "libresoc.v:150397.3-150415.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:149753.3-149780.6" - wire $0\trapexc_$signal$60[0:0]$7473 - attribute \src "libresoc.v:149753.3-149780.6" - wire $0\trapexc_$signal$61[0:0]$7474 - attribute \src "libresoc.v:149753.3-149780.6" - wire $0\trapexc_$signal$62[0:0]$7475 - attribute \src "libresoc.v:149753.3-149780.6" - wire $0\trapexc_$signal$67[0:0]$7476 - attribute \src "libresoc.v:149753.3-149780.6" - wire $0\trapexc_$signal$68[0:0]$7477 - attribute \src "libresoc.v:149753.3-149780.6" - wire $0\trapexc_$signal$69[0:0]$7478 - attribute \src "libresoc.v:149753.3-149780.6" - wire $0\trapexc_$signal$70[0:0]$7479 - attribute \src "libresoc.v:149753.3-149780.6" - wire $0\trapexc_$signal[0:0]$7472 - attribute \src "libresoc.v:149638.3-149720.6" - wire $10\fast2$12[19:19]$7469 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150169.3-150196.6" + wire $0\trapexc_$signal$60[0:0]$7405 + attribute \src "libresoc.v:150169.3-150196.6" + wire $0\trapexc_$signal$61[0:0]$7406 + attribute \src "libresoc.v:150169.3-150196.6" + wire $0\trapexc_$signal$62[0:0]$7407 + attribute \src "libresoc.v:150169.3-150196.6" + wire $0\trapexc_$signal$67[0:0]$7408 + attribute \src "libresoc.v:150169.3-150196.6" + wire $0\trapexc_$signal$68[0:0]$7409 + attribute \src "libresoc.v:150169.3-150196.6" + wire $0\trapexc_$signal$69[0:0]$7410 + attribute \src "libresoc.v:150169.3-150196.6" + wire $0\trapexc_$signal$70[0:0]$7411 + attribute \src "libresoc.v:150169.3-150196.6" + wire $0\trapexc_$signal[0:0]$7404 + attribute \src "libresoc.v:150054.3-150136.6" + wire $10\fast2$12[19:19]$7401 + attribute \src "libresoc.v:150209.3-150377.6" wire width 2 $10\msr[5:4] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150209.3-150377.6" wire $11\msr[15:15] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150209.3-150377.6" wire $12\msr[12:12] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150209.3-150377.6" wire $13\msr[60:60] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150209.3-150377.6" wire $14\msr[12:12] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150209.3-150377.6" wire $15\msr[12:12] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150209.3-150377.6" wire width 2 $16\msr[5:4] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150209.3-150377.6" wire $17\msr[15:15] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150209.3-150377.6" wire width 3 $18\msr[34:32] - attribute \src "libresoc.v:150000.3-150011.6" + attribute \src "libresoc.v:150416.3-150427.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:149498.3-149509.6" + attribute \src "libresoc.v:149914.3-149925.6" wire width 64 $1\a_s[63:0] - attribute \src "libresoc.v:150012.3-150023.6" + attribute \src "libresoc.v:150428.3-150439.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:149781.3-149792.6" + attribute \src "libresoc.v:150197.3-150208.6" wire width 64 $1\b_s[63:0] - attribute \src "libresoc.v:149574.3-149605.6" - wire width 64 $1\fast1$11[63:0]$7455 - attribute \src "libresoc.v:149606.3-149637.6" + attribute \src "libresoc.v:149990.3-150021.6" + wire width 64 $1\fast1$11[63:0]$7387 + attribute \src "libresoc.v:150022.3-150053.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:149638.3-149720.6" - wire width 64 $1\fast2$12[63:0]$7460 - attribute \src "libresoc.v:149721.3-149752.6" + attribute \src "libresoc.v:150054.3-150136.6" + wire width 64 $1\fast2$12[63:0]$7392 + attribute \src "libresoc.v:150137.3-150168.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150209.3-150377.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150209.3-150377.6" wire $1\msr_ok[0:0] - attribute \src "libresoc.v:149510.3-149541.6" + attribute \src "libresoc.v:149926.3-149957.6" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:149542.3-149573.6" + attribute \src "libresoc.v:149958.3-149989.6" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:149962.3-149980.6" + attribute \src "libresoc.v:150378.3-150396.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:149981.3-149999.6" + attribute \src "libresoc.v:150397.3-150415.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:149753.3-149780.6" - wire $1\trapexc_$signal$60[0:0]$7481 - attribute \src "libresoc.v:149753.3-149780.6" - wire $1\trapexc_$signal$61[0:0]$7482 - attribute \src "libresoc.v:149753.3-149780.6" - wire $1\trapexc_$signal$62[0:0]$7483 - attribute \src "libresoc.v:149753.3-149780.6" - wire $1\trapexc_$signal$67[0:0]$7484 - attribute \src "libresoc.v:149753.3-149780.6" - wire $1\trapexc_$signal$68[0:0]$7485 - attribute \src "libresoc.v:149753.3-149780.6" - wire $1\trapexc_$signal$69[0:0]$7486 - attribute \src "libresoc.v:149753.3-149780.6" - wire $1\trapexc_$signal$70[0:0]$7487 - attribute \src "libresoc.v:149753.3-149780.6" - wire $1\trapexc_$signal[0:0]$7480 - attribute \src "libresoc.v:149574.3-149605.6" - wire width 64 $2\fast1$11[63:0]$7456 - attribute \src "libresoc.v:149606.3-149637.6" + attribute \src "libresoc.v:150169.3-150196.6" + wire $1\trapexc_$signal$60[0:0]$7413 + attribute \src "libresoc.v:150169.3-150196.6" + wire $1\trapexc_$signal$61[0:0]$7414 + attribute \src "libresoc.v:150169.3-150196.6" + wire $1\trapexc_$signal$62[0:0]$7415 + attribute \src "libresoc.v:150169.3-150196.6" + wire $1\trapexc_$signal$67[0:0]$7416 + attribute \src "libresoc.v:150169.3-150196.6" + wire $1\trapexc_$signal$68[0:0]$7417 + attribute \src "libresoc.v:150169.3-150196.6" + wire $1\trapexc_$signal$69[0:0]$7418 + attribute \src "libresoc.v:150169.3-150196.6" + wire $1\trapexc_$signal$70[0:0]$7419 + attribute \src "libresoc.v:150169.3-150196.6" + wire $1\trapexc_$signal[0:0]$7412 + attribute \src "libresoc.v:149990.3-150021.6" + wire width 64 $2\fast1$11[63:0]$7388 + attribute \src "libresoc.v:150022.3-150053.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:149638.3-149720.6" - wire width 64 $2\fast2$12[63:0]$7461 - attribute \src "libresoc.v:149721.3-149752.6" + attribute \src "libresoc.v:150054.3-150136.6" + wire width 64 $2\fast2$12[63:0]$7393 + attribute \src "libresoc.v:150137.3-150168.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150209.3-150377.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150209.3-150377.6" wire $2\msr_ok[0:0] - attribute \src "libresoc.v:149510.3-149541.6" + attribute \src "libresoc.v:149926.3-149957.6" wire width 64 $2\nia[63:0] - attribute \src "libresoc.v:149542.3-149573.6" + attribute \src "libresoc.v:149958.3-149989.6" wire $2\nia_ok[0:0] - attribute \src "libresoc.v:149753.3-149780.6" - wire $2\trapexc_$signal$60[0:0]$7489 - attribute \src "libresoc.v:149753.3-149780.6" - wire $2\trapexc_$signal$61[0:0]$7490 - attribute \src "libresoc.v:149753.3-149780.6" - wire $2\trapexc_$signal$62[0:0]$7491 - attribute \src "libresoc.v:149753.3-149780.6" - wire $2\trapexc_$signal$67[0:0]$7492 - attribute \src "libresoc.v:149753.3-149780.6" - wire $2\trapexc_$signal$68[0:0]$7493 - attribute \src "libresoc.v:149753.3-149780.6" - wire $2\trapexc_$signal$69[0:0]$7494 - attribute \src "libresoc.v:149753.3-149780.6" - wire $2\trapexc_$signal$70[0:0]$7495 - attribute \src "libresoc.v:149753.3-149780.6" - wire $2\trapexc_$signal[0:0]$7488 - attribute \src "libresoc.v:149638.3-149720.6" - wire $3\fast2$12[17:17]$7462 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150169.3-150196.6" + wire $2\trapexc_$signal$60[0:0]$7421 + attribute \src "libresoc.v:150169.3-150196.6" + wire $2\trapexc_$signal$61[0:0]$7422 + attribute \src "libresoc.v:150169.3-150196.6" + wire $2\trapexc_$signal$62[0:0]$7423 + attribute \src "libresoc.v:150169.3-150196.6" + wire $2\trapexc_$signal$67[0:0]$7424 + attribute \src "libresoc.v:150169.3-150196.6" + wire $2\trapexc_$signal$68[0:0]$7425 + attribute \src "libresoc.v:150169.3-150196.6" + wire $2\trapexc_$signal$69[0:0]$7426 + attribute \src "libresoc.v:150169.3-150196.6" + wire $2\trapexc_$signal$70[0:0]$7427 + attribute \src "libresoc.v:150169.3-150196.6" + wire $2\trapexc_$signal[0:0]$7420 + attribute \src "libresoc.v:150054.3-150136.6" + wire $3\fast2$12[17:17]$7394 + attribute \src "libresoc.v:150209.3-150377.6" wire width 11 $3\msr[11:1] - attribute \src "libresoc.v:149753.3-149780.6" - wire $3\trapexc_$signal$60[0:0]$7497 - attribute \src "libresoc.v:149753.3-149780.6" - wire $3\trapexc_$signal$61[0:0]$7498 - attribute \src "libresoc.v:149753.3-149780.6" - wire $3\trapexc_$signal$62[0:0]$7499 - attribute \src "libresoc.v:149753.3-149780.6" - wire $3\trapexc_$signal$67[0:0]$7500 - attribute \src "libresoc.v:149753.3-149780.6" - wire $3\trapexc_$signal$68[0:0]$7501 - attribute \src "libresoc.v:149753.3-149780.6" - wire $3\trapexc_$signal$69[0:0]$7502 - attribute \src "libresoc.v:149753.3-149780.6" - wire $3\trapexc_$signal$70[0:0]$7503 - attribute \src "libresoc.v:149753.3-149780.6" - wire $3\trapexc_$signal[0:0]$7496 - attribute \src "libresoc.v:149638.3-149720.6" - wire $4\fast2$12[18:18]$7463 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150169.3-150196.6" + wire $3\trapexc_$signal$60[0:0]$7429 + attribute \src "libresoc.v:150169.3-150196.6" + wire $3\trapexc_$signal$61[0:0]$7430 + attribute \src "libresoc.v:150169.3-150196.6" + wire $3\trapexc_$signal$62[0:0]$7431 + attribute \src "libresoc.v:150169.3-150196.6" + wire $3\trapexc_$signal$67[0:0]$7432 + attribute \src "libresoc.v:150169.3-150196.6" + wire $3\trapexc_$signal$68[0:0]$7433 + attribute \src "libresoc.v:150169.3-150196.6" + wire $3\trapexc_$signal$69[0:0]$7434 + attribute \src "libresoc.v:150169.3-150196.6" + wire $3\trapexc_$signal$70[0:0]$7435 + attribute \src "libresoc.v:150169.3-150196.6" + wire $3\trapexc_$signal[0:0]$7428 + attribute \src "libresoc.v:150054.3-150136.6" + wire $4\fast2$12[18:18]$7395 + attribute \src "libresoc.v:150209.3-150377.6" wire width 47 $4\msr[59:13] - attribute \src "libresoc.v:149638.3-149720.6" - wire $5\fast2$12[20:20]$7464 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150054.3-150136.6" + wire $5\fast2$12[20:20]$7396 + attribute \src "libresoc.v:150209.3-150377.6" wire width 3 $5\msr[63:61] - attribute \src "libresoc.v:149638.3-149720.6" - wire $6\fast2$12[16:16]$7465 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150054.3-150136.6" + wire $6\fast2$12[16:16]$7397 + attribute \src "libresoc.v:150209.3-150377.6" wire width 11 $6\msr[11:1] - attribute \src "libresoc.v:149638.3-149720.6" - wire width 2 $7\fast2$12[19:18]$7466 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150054.3-150136.6" + wire width 2 $7\fast2$12[19:18]$7398 + attribute \src "libresoc.v:150209.3-150377.6" wire width 47 $7\msr[59:13] - attribute \src "libresoc.v:149638.3-149720.6" - wire $8\fast2$12[28:28]$7467 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150054.3-150136.6" + wire $8\fast2$12[28:28]$7399 + attribute \src "libresoc.v:150209.3-150377.6" wire width 3 $8\msr[63:61] - attribute \src "libresoc.v:149638.3-149720.6" - wire $9\fast2$12[30:30]$7468 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:150054.3-150136.6" + wire $9\fast2$12[30:30]$7400 + attribute \src "libresoc.v:150209.3-150377.6" wire width 3 $9\msr[34:32] - attribute \src "libresoc.v:149474.18-149474.113" - wire width 65 $add$libresoc.v:149474$7425_Y - attribute \src "libresoc.v:149468.18-149468.108" - wire width 5 $and$libresoc.v:149468$7418_Y - attribute \src "libresoc.v:149476.18-149476.118" - wire width 8 $and$libresoc.v:149476$7427_Y - attribute \src "libresoc.v:149478.18-149478.118" - wire width 8 $and$libresoc.v:149478$7429_Y - attribute \src "libresoc.v:149480.18-149480.118" - wire width 8 $and$libresoc.v:149480$7431_Y - attribute \src "libresoc.v:149482.18-149482.119" - wire width 8 $and$libresoc.v:149482$7433_Y - attribute \src "libresoc.v:149484.18-149484.119" - wire width 8 $and$libresoc.v:149484$7435_Y - attribute \src "libresoc.v:149486.18-149486.119" - wire width 8 $and$libresoc.v:149486$7437_Y - attribute \src "libresoc.v:149492.18-149492.106" - wire $and$libresoc.v:149492$7444_Y - attribute \src "libresoc.v:149497.18-149497.106" - wire $and$libresoc.v:149497$7449_Y - attribute \src "libresoc.v:149467.18-149467.100" - wire $eq$libresoc.v:149467$7417_Y - attribute \src "libresoc.v:149475.18-149475.119" - wire $eq$libresoc.v:149475$7426_Y - attribute \src "libresoc.v:149489.18-149489.121" - wire $eq$libresoc.v:149489$7441_Y - attribute \src "libresoc.v:149490.18-149490.121" - wire $eq$libresoc.v:149490$7442_Y - attribute \src "libresoc.v:149491.18-149491.111" - wire $eq$libresoc.v:149491$7443_Y - attribute \src "libresoc.v:149495.18-149495.121" - wire $eq$libresoc.v:149495$7447_Y - attribute \src "libresoc.v:149496.18-149496.114" - wire $eq$libresoc.v:149496$7448_Y - attribute \src "libresoc.v:149461.18-149461.95" - wire width 64 $extend$libresoc.v:149461$7409_Y - attribute \src "libresoc.v:149462.18-149462.95" - wire width 64 $extend$libresoc.v:149462$7411_Y - attribute \src "libresoc.v:149473.18-149473.100" - wire width 64 $extend$libresoc.v:149473$7423_Y - attribute \src "libresoc.v:149488.18-149488.109" - wire width 65 $extend$libresoc.v:149488$7439_Y - attribute \src "libresoc.v:149464.18-149464.121" - wire $gt$libresoc.v:149464$7414_Y - attribute \src "libresoc.v:149466.18-149466.99" - wire $gt$libresoc.v:149466$7416_Y - attribute \src "libresoc.v:149463.18-149463.121" - wire $lt$libresoc.v:149463$7413_Y - attribute \src "libresoc.v:149465.18-149465.99" - wire $lt$libresoc.v:149465$7415_Y - attribute \src "libresoc.v:149493.18-149493.112" - wire $not$libresoc.v:149493$7445_Y - attribute \src "libresoc.v:149494.18-149494.112" - wire $not$libresoc.v:149494$7446_Y - attribute \src "libresoc.v:149471.18-149471.106" - wire $or$libresoc.v:149471$7421_Y - attribute \src "libresoc.v:149461.18-149461.95" - wire width 64 $pos$libresoc.v:149461$7410_Y - attribute \src "libresoc.v:149462.18-149462.95" - wire width 64 $pos$libresoc.v:149462$7412_Y - attribute \src "libresoc.v:149473.18-149473.100" - wire width 64 $pos$libresoc.v:149473$7424_Y - attribute \src "libresoc.v:149488.18-149488.109" - wire width 65 $pos$libresoc.v:149488$7440_Y - attribute \src "libresoc.v:149469.18-149469.100" - wire $reduce_or$libresoc.v:149469$7419_Y - attribute \src "libresoc.v:149470.18-149470.113" - wire $reduce_or$libresoc.v:149470$7420_Y - attribute \src "libresoc.v:149477.18-149477.91" - wire $reduce_or$libresoc.v:149477$7428_Y - attribute \src "libresoc.v:149479.18-149479.91" - wire $reduce_or$libresoc.v:149479$7430_Y - attribute \src "libresoc.v:149481.18-149481.91" - wire $reduce_or$libresoc.v:149481$7432_Y - attribute \src "libresoc.v:149483.18-149483.91" - wire $reduce_or$libresoc.v:149483$7434_Y - attribute \src "libresoc.v:149485.18-149485.91" - wire $reduce_or$libresoc.v:149485$7436_Y - attribute \src "libresoc.v:149487.18-149487.91" - wire $reduce_or$libresoc.v:149487$7438_Y - attribute \src "libresoc.v:149472.18-149472.120" - wire width 20 $sshl$libresoc.v:149472$7422_Y + attribute \src "libresoc.v:149890.18-149890.113" + wire width 65 $add$libresoc.v:149890$7357_Y + attribute \src "libresoc.v:149884.18-149884.108" + wire width 5 $and$libresoc.v:149884$7350_Y + attribute \src "libresoc.v:149892.18-149892.118" + wire width 8 $and$libresoc.v:149892$7359_Y + attribute \src "libresoc.v:149894.18-149894.118" + wire width 8 $and$libresoc.v:149894$7361_Y + attribute \src "libresoc.v:149896.18-149896.118" + wire width 8 $and$libresoc.v:149896$7363_Y + attribute \src "libresoc.v:149898.18-149898.119" + wire width 8 $and$libresoc.v:149898$7365_Y + attribute \src "libresoc.v:149900.18-149900.119" + wire width 8 $and$libresoc.v:149900$7367_Y + attribute \src "libresoc.v:149902.18-149902.119" + wire width 8 $and$libresoc.v:149902$7369_Y + attribute \src "libresoc.v:149908.18-149908.106" + wire $and$libresoc.v:149908$7376_Y + attribute \src "libresoc.v:149913.18-149913.106" + wire $and$libresoc.v:149913$7381_Y + attribute \src "libresoc.v:149883.18-149883.100" + wire $eq$libresoc.v:149883$7349_Y + attribute \src "libresoc.v:149891.18-149891.119" + wire $eq$libresoc.v:149891$7358_Y + attribute \src "libresoc.v:149905.18-149905.121" + wire $eq$libresoc.v:149905$7373_Y + attribute \src "libresoc.v:149906.18-149906.121" + wire $eq$libresoc.v:149906$7374_Y + attribute \src "libresoc.v:149907.18-149907.111" + wire $eq$libresoc.v:149907$7375_Y + attribute \src "libresoc.v:149911.18-149911.121" + wire $eq$libresoc.v:149911$7379_Y + attribute \src "libresoc.v:149912.18-149912.114" + wire $eq$libresoc.v:149912$7380_Y + attribute \src "libresoc.v:149877.18-149877.95" + wire width 64 $extend$libresoc.v:149877$7341_Y + attribute \src "libresoc.v:149878.18-149878.95" + wire width 64 $extend$libresoc.v:149878$7343_Y + attribute \src "libresoc.v:149889.18-149889.100" + wire width 64 $extend$libresoc.v:149889$7355_Y + attribute \src "libresoc.v:149904.18-149904.109" + wire width 65 $extend$libresoc.v:149904$7371_Y + attribute \src "libresoc.v:149880.18-149880.121" + wire $gt$libresoc.v:149880$7346_Y + attribute \src "libresoc.v:149882.18-149882.99" + wire $gt$libresoc.v:149882$7348_Y + attribute \src "libresoc.v:149879.18-149879.121" + wire $lt$libresoc.v:149879$7345_Y + attribute \src "libresoc.v:149881.18-149881.99" + wire $lt$libresoc.v:149881$7347_Y + attribute \src "libresoc.v:149909.18-149909.112" + wire $not$libresoc.v:149909$7377_Y + attribute \src "libresoc.v:149910.18-149910.112" + wire $not$libresoc.v:149910$7378_Y + attribute \src "libresoc.v:149887.18-149887.106" + wire $or$libresoc.v:149887$7353_Y + attribute \src "libresoc.v:149877.18-149877.95" + wire width 64 $pos$libresoc.v:149877$7342_Y + attribute \src "libresoc.v:149878.18-149878.95" + wire width 64 $pos$libresoc.v:149878$7344_Y + attribute \src "libresoc.v:149889.18-149889.100" + wire width 64 $pos$libresoc.v:149889$7356_Y + attribute \src "libresoc.v:149904.18-149904.109" + wire width 65 $pos$libresoc.v:149904$7372_Y + attribute \src "libresoc.v:149885.18-149885.100" + wire $reduce_or$libresoc.v:149885$7351_Y + attribute \src "libresoc.v:149886.18-149886.113" + wire $reduce_or$libresoc.v:149886$7352_Y + attribute \src "libresoc.v:149893.18-149893.91" + wire $reduce_or$libresoc.v:149893$7360_Y + attribute \src "libresoc.v:149895.18-149895.91" + wire $reduce_or$libresoc.v:149895$7362_Y + attribute \src "libresoc.v:149897.18-149897.91" + wire $reduce_or$libresoc.v:149897$7364_Y + attribute \src "libresoc.v:149899.18-149899.91" + wire $reduce_or$libresoc.v:149899$7366_Y + attribute \src "libresoc.v:149901.18-149901.91" + wire $reduce_or$libresoc.v:149901$7368_Y + attribute \src "libresoc.v:149903.18-149903.91" + wire $reduce_or$libresoc.v:149903$7370_Y + attribute \src "libresoc.v:149888.18-149888.120" + wire width 20 $sshl$libresoc.v:149888$7354_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 64 \$13 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" @@ -311496,41 +277772,41 @@ module \main$38 wire \equal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 12 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 26 \fast1$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 13 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 28 \fast2$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" wire \gt_s attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" wire \gt_u - attribute \src "libresoc.v:149086.7-149086.15" + attribute \src "libresoc.v:149502.7-149502.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" wire \lt_s attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" wire \lt_u - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 32 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \msr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 34 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 14 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 30 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 31 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 24 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 10 \ra @@ -311775,7 +278051,7 @@ module \main$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" - cell $add $add$libresoc.v:149474$7425 + cell $add $add$libresoc.v:149890$7357 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -311783,10 +278059,10 @@ module \main$38 parameter \Y_WIDTH 65 connect \A \trap_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:149474$7425_Y + connect \Y $add$libresoc.v:149890$7357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $and $and$libresoc.v:149468$7418 + cell $and $and$libresoc.v:149884$7350 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -311794,10 +278070,10 @@ module \main$38 parameter \Y_WIDTH 5 connect \A \trap_bits connect \B \to - connect \Y $and$libresoc.v:149468$7418_Y + connect \Y $and$libresoc.v:149884$7350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" - cell $and $and$libresoc.v:149476$7427 + cell $and $and$libresoc.v:149892$7359 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311805,10 +278081,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 2'10 - connect \Y $and$libresoc.v:149476$7427_Y + connect \Y $and$libresoc.v:149892$7359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" - cell $and $and$libresoc.v:149478$7429 + cell $and $and$libresoc.v:149894$7361 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311816,10 +278092,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 1'1 - connect \Y $and$libresoc.v:149478$7429_Y + connect \Y $and$libresoc.v:149894$7361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" - cell $and $and$libresoc.v:149480$7431 + cell $and $and$libresoc.v:149896$7363 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311827,10 +278103,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 4'1000 - connect \Y $and$libresoc.v:149480$7431_Y + connect \Y $and$libresoc.v:149896$7363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:149482$7433 + cell $and $and$libresoc.v:149898$7365 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311838,10 +278114,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:149482$7433_Y + connect \Y $and$libresoc.v:149898$7365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" - cell $and $and$libresoc.v:149484$7435 + cell $and $and$libresoc.v:149900$7367 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311849,10 +278125,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 8'10000000 - connect \Y $and$libresoc.v:149484$7435_Y + connect \Y $and$libresoc.v:149900$7367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:149486$7437 + cell $and $and$libresoc.v:149902$7369 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311860,10 +278136,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:149486$7437_Y + connect \Y $and$libresoc.v:149902$7369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $and $and$libresoc.v:149492$7444 + cell $and $and$libresoc.v:149908$7376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311871,10 +278147,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 - connect \Y $and$libresoc.v:149492$7444_Y + connect \Y $and$libresoc.v:149908$7376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $and $and$libresoc.v:149497$7449 + cell $and $and$libresoc.v:149913$7381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311882,10 +278158,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$89 connect \B \$91 - connect \Y $and$libresoc.v:149497$7449_Y + connect \Y $and$libresoc.v:149913$7381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" - cell $eq $eq$libresoc.v:149467$7417 + cell $eq $eq$libresoc.v:149883$7349 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -311893,10 +278169,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $eq$libresoc.v:149467$7417_Y + connect \Y $eq$libresoc.v:149883$7349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" - cell $eq $eq$libresoc.v:149475$7426 + cell $eq $eq$libresoc.v:149891$7358 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311904,10 +278180,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__traptype connect \B 1'0 - connect \Y $eq$libresoc.v:149475$7426_Y + connect \Y $eq$libresoc.v:149891$7358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" - cell $eq $eq$libresoc.v:149489$7441 + cell $eq $eq$libresoc.v:149905$7373 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -311915,10 +278191,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__insn_type connect \B 7'1001000 - connect \Y $eq$libresoc.v:149489$7441_Y + connect \Y $eq$libresoc.v:149905$7373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" - cell $eq $eq$libresoc.v:149490$7442 + cell $eq $eq$libresoc.v:149906$7374 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -311926,10 +278202,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:149490$7442_Y + connect \Y $eq$libresoc.v:149906$7374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $eq $eq$libresoc.v:149491$7443 + cell $eq $eq$libresoc.v:149907$7375 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -311937,10 +278213,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \ra [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:149491$7443_Y + connect \Y $eq$libresoc.v:149907$7375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - cell $eq $eq$libresoc.v:149495$7447 + cell $eq $eq$libresoc.v:149911$7379 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -311948,10 +278224,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:149495$7447_Y + connect \Y $eq$libresoc.v:149911$7379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $eq $eq$libresoc.v:149496$7448 + cell $eq $eq$libresoc.v:149912$7380 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -311959,42 +278235,42 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \fast2 [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:149496$7448_Y + connect \Y $eq$libresoc.v:149912$7380_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:149461$7409 + cell $pos $extend$libresoc.v:149877$7341 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \ra [31:0] - connect \Y $extend$libresoc.v:149461$7409_Y + connect \Y $extend$libresoc.v:149877$7341_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:149462$7411 + cell $pos $extend$libresoc.v:149878$7343 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \rb [31:0] - connect \Y $extend$libresoc.v:149462$7411_Y + connect \Y $extend$libresoc.v:149878$7343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $extend$libresoc.v:149473$7423 + cell $pos $extend$libresoc.v:149889$7355 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \Y_WIDTH 64 connect \A \$36 - connect \Y $extend$libresoc.v:149473$7423_Y + connect \Y $extend$libresoc.v:149889$7355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:149488$7439 + cell $pos $extend$libresoc.v:149904$7371 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \trap_op__msr - connect \Y $extend$libresoc.v:149488$7439_Y + connect \Y $extend$libresoc.v:149904$7371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - cell $gt $gt$libresoc.v:149464$7414 + cell $gt $gt$libresoc.v:149880$7346 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -312002,10 +278278,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $gt$libresoc.v:149464$7414_Y + connect \Y $gt$libresoc.v:149880$7346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - cell $gt $gt$libresoc.v:149466$7416 + cell $gt $gt$libresoc.v:149882$7348 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -312013,10 +278289,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $gt$libresoc.v:149466$7416_Y + connect \Y $gt$libresoc.v:149882$7348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - cell $lt $lt$libresoc.v:149463$7413 + cell $lt $lt$libresoc.v:149879$7345 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -312024,10 +278300,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $lt$libresoc.v:149463$7413_Y + connect \Y $lt$libresoc.v:149879$7345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - cell $lt $lt$libresoc.v:149465$7415 + cell $lt $lt$libresoc.v:149881$7347 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -312035,26 +278311,26 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $lt$libresoc.v:149465$7415_Y + connect \Y $lt$libresoc.v:149881$7347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - cell $not $not$libresoc.v:149493$7445 + cell $not $not$libresoc.v:149909$7377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__msr [60] - connect \Y $not$libresoc.v:149493$7445_Y + connect \Y $not$libresoc.v:149909$7377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - cell $not $not$libresoc.v:149494$7446 + cell $not $not$libresoc.v:149910$7378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__insn [9] - connect \Y $not$libresoc.v:149494$7446_Y + connect \Y $not$libresoc.v:149910$7378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $or $or$libresoc.v:149471$7421 + cell $or $or$libresoc.v:149887$7353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312062,106 +278338,106 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$27 connect \B \$31 - connect \Y $or$libresoc.v:149471$7421_Y + connect \Y $or$libresoc.v:149887$7353_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:149461$7410 + cell $pos $pos$libresoc.v:149877$7342 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:149461$7409_Y - connect \Y $pos$libresoc.v:149461$7410_Y + connect \A $extend$libresoc.v:149877$7341_Y + connect \Y $pos$libresoc.v:149877$7342_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:149462$7412 + cell $pos $pos$libresoc.v:149878$7344 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:149462$7411_Y - connect \Y $pos$libresoc.v:149462$7412_Y + connect \A $extend$libresoc.v:149878$7343_Y + connect \Y $pos$libresoc.v:149878$7344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $pos$libresoc.v:149473$7424 + cell $pos $pos$libresoc.v:149889$7356 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:149473$7423_Y - connect \Y $pos$libresoc.v:149473$7424_Y + connect \A $extend$libresoc.v:149889$7355_Y + connect \Y $pos$libresoc.v:149889$7356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:149488$7440 + cell $pos $pos$libresoc.v:149904$7372 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:149488$7439_Y - connect \Y $pos$libresoc.v:149488$7440_Y + connect \A $extend$libresoc.v:149904$7371_Y + connect \Y $pos$libresoc.v:149904$7372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:149469$7419 + cell $reduce_or $reduce_or$libresoc.v:149885$7351 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $reduce_or$libresoc.v:149469$7419_Y + connect \Y $reduce_or$libresoc.v:149885$7351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:149470$7420 + cell $reduce_or $reduce_or$libresoc.v:149886$7352 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \trap_op__traptype - connect \Y $reduce_or$libresoc.v:149470$7420_Y + connect \Y $reduce_or$libresoc.v:149886$7352_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149477$7428 + cell $reduce_or $reduce_or$libresoc.v:149893$7360 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$45 - connect \Y $reduce_or$libresoc.v:149477$7428_Y + connect \Y $reduce_or$libresoc.v:149893$7360_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149479$7430 + cell $reduce_or $reduce_or$libresoc.v:149895$7362 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$49 - connect \Y $reduce_or$libresoc.v:149479$7430_Y + connect \Y $reduce_or$libresoc.v:149895$7362_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149481$7432 + cell $reduce_or $reduce_or$libresoc.v:149897$7364 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$53 - connect \Y $reduce_or$libresoc.v:149481$7432_Y + connect \Y $reduce_or$libresoc.v:149897$7364_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149483$7434 + cell $reduce_or $reduce_or$libresoc.v:149899$7366 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$57 - connect \Y $reduce_or$libresoc.v:149483$7434_Y + connect \Y $reduce_or$libresoc.v:149899$7366_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149485$7436 + cell $reduce_or $reduce_or$libresoc.v:149901$7368 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $reduce_or$libresoc.v:149485$7436_Y + connect \Y $reduce_or$libresoc.v:149901$7368_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149487$7438 + cell $reduce_or $reduce_or$libresoc.v:149903$7370 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$72 - connect \Y $reduce_or$libresoc.v:149487$7438_Y + connect \Y $reduce_or$libresoc.v:149903$7370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $sshl $sshl$libresoc.v:149472$7422 + cell $sshl $sshl$libresoc.v:149888$7354 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -312169,23 +278445,23 @@ module \main$38 parameter \Y_WIDTH 20 connect \A \trap_op__trapaddr connect \B 3'100 - connect \Y $sshl$libresoc.v:149472$7422_Y + connect \Y $sshl$libresoc.v:149888$7354_Y end - attribute \src "libresoc.v:149086.7-149086.20" - process $proc$libresoc.v:149086$7510 + attribute \src "libresoc.v:149502.7-149502.20" + process $proc$libresoc.v:149502$7442 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:149498.3-149509.6" - process $proc$libresoc.v:149498$7450 + attribute \src "libresoc.v:149914.3-149925.6" + process $proc$libresoc.v:149914$7382 assign { } { } assign $0\a_s[63:0] $1\a_s[63:0] - attribute \src "libresoc.v:149499.5-149499.29" + attribute \src "libresoc.v:149915.5-149915.29" switch \initial - attribute \src "libresoc.v:149499.9-149499.17" + attribute \src "libresoc.v:149915.9-149915.17" case 1'1 case end @@ -312203,14 +278479,14 @@ module \main$38 sync always update \a_s $0\a_s[63:0] end - attribute \src "libresoc.v:149510.3-149541.6" - process $proc$libresoc.v:149510$7451 + attribute \src "libresoc.v:149926.3-149957.6" + process $proc$libresoc.v:149926$7383 assign { } { } assign { } { } assign $0\nia[63:0] $1\nia[63:0] - attribute \src "libresoc.v:149511.5-149511.29" + attribute \src "libresoc.v:149927.5-149927.29" switch \initial - attribute \src "libresoc.v:149511.9-149511.17" + attribute \src "libresoc.v:149927.9-149927.17" case 1'1 case end @@ -312249,14 +278525,14 @@ module \main$38 sync always update \nia $0\nia[63:0] end - attribute \src "libresoc.v:149542.3-149573.6" - process $proc$libresoc.v:149542$7452 + attribute \src "libresoc.v:149958.3-149989.6" + process $proc$libresoc.v:149958$7384 assign { } { } assign { } { } assign $0\nia_ok[0:0] $1\nia_ok[0:0] - attribute \src "libresoc.v:149543.5-149543.29" + attribute \src "libresoc.v:149959.5-149959.29" switch \initial - attribute \src "libresoc.v:149543.9-149543.17" + attribute \src "libresoc.v:149959.9-149959.17" case 1'1 case end @@ -312295,14 +278571,14 @@ module \main$38 sync always update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:149574.3-149605.6" - process $proc$libresoc.v:149574$7453 + attribute \src "libresoc.v:149990.3-150021.6" + process $proc$libresoc.v:149990$7385 assign { } { } assign { } { } - assign $0\fast1$11[63:0]$7454 $1\fast1$11[63:0]$7455 - attribute \src "libresoc.v:149575.5-149575.29" + assign $0\fast1$11[63:0]$7386 $1\fast1$11[63:0]$7387 + attribute \src "libresoc.v:149991.5-149991.29" switch \initial - attribute \src "libresoc.v:149575.9-149575.17" + attribute \src "libresoc.v:149991.9-149991.17" case 1'1 case end @@ -312311,43 +278587,43 @@ module \main$38 attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } - assign $1\fast1$11[63:0]$7455 $2\fast1$11[63:0]$7456 + assign $1\fast1$11[63:0]$7387 $2\fast1$11[63:0]$7388 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1$11[63:0]$7456 \trap_op__cia + assign $2\fast1$11[63:0]$7388 \trap_op__cia case - assign $2\fast1$11[63:0]$7456 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$11[63:0]$7388 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 - assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7387 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 - assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7387 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 - assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7387 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } - assign $1\fast1$11[63:0]$7455 \$39 [63:0] + assign $1\fast1$11[63:0]$7387 \$39 [63:0] case - assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7387 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$11 $0\fast1$11[63:0]$7454 + update \fast1$11 $0\fast1$11[63:0]$7386 end - attribute \src "libresoc.v:149606.3-149637.6" - process $proc$libresoc.v:149606$7457 + attribute \src "libresoc.v:150022.3-150053.6" + process $proc$libresoc.v:150022$7389 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:149607.5-149607.29" + attribute \src "libresoc.v:150023.5-150023.29" switch \initial - attribute \src "libresoc.v:149607.9-149607.17" + attribute \src "libresoc.v:150023.9-150023.17" case 1'1 case end @@ -312385,14 +278661,14 @@ module \main$38 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:149638.3-149720.6" - process $proc$libresoc.v:149638$7458 + attribute \src "libresoc.v:150054.3-150136.6" + process $proc$libresoc.v:150054$7390 assign { } { } assign { } { } - assign $0\fast2$12[63:0]$7459 $1\fast2$12[63:0]$7460 - attribute \src "libresoc.v:149639.5-149639.29" + assign $0\fast2$12[63:0]$7391 $1\fast2$12[63:0]$7392 + attribute \src "libresoc.v:150055.5-150055.29" switch \initial - attribute \src "libresoc.v:149639.9-149639.17" + attribute \src "libresoc.v:150055.9-150055.17" case 1'1 case end @@ -312401,59 +278677,59 @@ module \main$38 attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } - assign $1\fast2$12[63:0]$7460 $2\fast2$12[63:0]$7461 + assign $1\fast2$12[63:0]$7392 $2\fast2$12[63:0]$7393 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { $2\fast2$12[63:0]$7461 [29] $2\fast2$12[63:0]$7461 [27] $2\fast2$12[63:0]$7461 [21] } 3'000 - assign $2\fast2$12[63:0]$7461 [15:0] \trap_op__msr [15:0] - assign $2\fast2$12[63:0]$7461 [26:22] \trap_op__msr [26:22] - assign $2\fast2$12[63:0]$7461 [63:31] \trap_op__msr [63:31] - assign $2\fast2$12[63:0]$7461 [17] $3\fast2$12[17:17]$7462 - assign { } { } - assign $2\fast2$12[63:0]$7461 [20] $5\fast2$12[20:20]$7464 - assign $2\fast2$12[63:0]$7461 [16] $6\fast2$12[16:16]$7465 - assign $2\fast2$12[63:0]$7461 [18] $7\fast2$12[19:18]$7466 [0] - assign $2\fast2$12[63:0]$7461 [28] $8\fast2$12[28:28]$7467 - assign $2\fast2$12[63:0]$7461 [30] $9\fast2$12[30:30]$7468 - assign $2\fast2$12[63:0]$7461 [19] $10\fast2$12[19:19]$7469 + assign { $2\fast2$12[63:0]$7393 [29] $2\fast2$12[63:0]$7393 [27] $2\fast2$12[63:0]$7393 [21] } 3'000 + assign $2\fast2$12[63:0]$7393 [15:0] \trap_op__msr [15:0] + assign $2\fast2$12[63:0]$7393 [26:22] \trap_op__msr [26:22] + assign $2\fast2$12[63:0]$7393 [63:31] \trap_op__msr [63:31] + assign $2\fast2$12[63:0]$7393 [17] $3\fast2$12[17:17]$7394 + assign { } { } + assign $2\fast2$12[63:0]$7393 [20] $5\fast2$12[20:20]$7396 + assign $2\fast2$12[63:0]$7393 [16] $6\fast2$12[16:16]$7397 + assign $2\fast2$12[63:0]$7393 [18] $7\fast2$12[19:18]$7398 [0] + assign $2\fast2$12[63:0]$7393 [28] $8\fast2$12[28:28]$7399 + assign $2\fast2$12[63:0]$7393 [30] $9\fast2$12[30:30]$7400 + assign $2\fast2$12[63:0]$7393 [19] $10\fast2$12[19:19]$7401 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" switch \$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fast2$12[17:17]$7462 1'1 + assign $3\fast2$12[17:17]$7394 1'1 case - assign $3\fast2$12[17:17]$7462 1'0 + assign $3\fast2$12[17:17]$7394 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" switch \$44 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fast2$12[18:18]$7463 1'1 + assign $4\fast2$12[18:18]$7395 1'1 case - assign $4\fast2$12[18:18]$7463 1'0 + assign $4\fast2$12[18:18]$7395 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fast2$12[20:20]$7464 1'1 + assign $5\fast2$12[20:20]$7396 1'1 case - assign $5\fast2$12[20:20]$7464 1'0 + assign $5\fast2$12[20:20]$7396 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fast2$12[16:16]$7465 1'1 + assign $6\fast2$12[16:16]$7397 1'1 case - assign $6\fast2$12[16:16]$7465 1'0 + assign $6\fast2$12[16:16]$7397 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" switch \$56 @@ -312462,57 +278738,57 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $9\fast2$12[30:30]$7468 \trapexc_$signal - assign $8\fast2$12[28:28]$7467 \trapexc_$signal$60 - assign $7\fast2$12[19:18]$7466 [1] \trapexc_$signal$61 - assign $7\fast2$12[19:18]$7466 [0] \trapexc_$signal$62 + assign $9\fast2$12[30:30]$7400 \trapexc_$signal + assign $8\fast2$12[28:28]$7399 \trapexc_$signal$60 + assign $7\fast2$12[19:18]$7398 [1] \trapexc_$signal$61 + assign $7\fast2$12[19:18]$7398 [0] \trapexc_$signal$62 case - assign $7\fast2$12[19:18]$7466 { 1'0 $4\fast2$12[18:18]$7463 } - assign $8\fast2$12[28:28]$7467 1'0 - assign $9\fast2$12[30:30]$7468 1'0 + assign $7\fast2$12[19:18]$7398 { 1'0 $4\fast2$12[18:18]$7395 } + assign $8\fast2$12[28:28]$7399 1'0 + assign $9\fast2$12[30:30]$7400 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\fast2$12[19:19]$7469 1'1 + assign $10\fast2$12[19:19]$7401 1'1 case - assign $10\fast2$12[19:19]$7469 $7\fast2$12[19:18]$7466 [1] + assign $10\fast2$12[19:19]$7401 $7\fast2$12[19:18]$7398 [1] end case - assign $2\fast2$12[63:0]$7461 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast2$12[63:0]$7393 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 - assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7392 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 - assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7392 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 - assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7392 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } - assign { $1\fast2$12[63:0]$7460 [30:27] $1\fast2$12[63:0]$7460 [21:16] } 10'0000000000 - assign $1\fast2$12[63:0]$7460 [15:0] \trap_op__msr [15:0] - assign $1\fast2$12[63:0]$7460 [26:22] \trap_op__msr [26:22] - assign $1\fast2$12[63:0]$7460 [63:31] \trap_op__msr [63:31] + assign { $1\fast2$12[63:0]$7392 [30:27] $1\fast2$12[63:0]$7392 [21:16] } 10'0000000000 + assign $1\fast2$12[63:0]$7392 [15:0] \trap_op__msr [15:0] + assign $1\fast2$12[63:0]$7392 [26:22] \trap_op__msr [26:22] + assign $1\fast2$12[63:0]$7392 [63:31] \trap_op__msr [63:31] case - assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7392 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast2$12 $0\fast2$12[63:0]$7459 + update \fast2$12 $0\fast2$12[63:0]$7391 end - attribute \src "libresoc.v:149721.3-149752.6" - process $proc$libresoc.v:149721$7470 + attribute \src "libresoc.v:150137.3-150168.6" + process $proc$libresoc.v:150137$7402 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:149722.5-149722.29" + attribute \src "libresoc.v:150138.5-150138.29" switch \initial - attribute \src "libresoc.v:149722.9-149722.17" + attribute \src "libresoc.v:150138.9-150138.17" case 1'1 case end @@ -312550,8 +278826,8 @@ module \main$38 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:149753.3-149780.6" - process $proc$libresoc.v:149753$7471 + attribute \src "libresoc.v:150169.3-150196.6" + process $proc$libresoc.v:150169$7403 assign { } { } assign { } { } assign { } { } @@ -312568,17 +278844,17 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $0\trapexc_$signal[0:0]$7472 $1\trapexc_$signal[0:0]$7480 - assign $0\trapexc_$signal$60[0:0]$7473 $1\trapexc_$signal$60[0:0]$7481 - assign $0\trapexc_$signal$61[0:0]$7474 $1\trapexc_$signal$61[0:0]$7482 - assign $0\trapexc_$signal$62[0:0]$7475 $1\trapexc_$signal$62[0:0]$7483 - assign $0\trapexc_$signal$67[0:0]$7476 $1\trapexc_$signal$67[0:0]$7484 - assign $0\trapexc_$signal$68[0:0]$7477 $1\trapexc_$signal$68[0:0]$7485 - assign $0\trapexc_$signal$69[0:0]$7478 $1\trapexc_$signal$69[0:0]$7486 - assign $0\trapexc_$signal$70[0:0]$7479 $1\trapexc_$signal$70[0:0]$7487 - attribute \src "libresoc.v:149754.5-149754.29" + assign $0\trapexc_$signal[0:0]$7404 $1\trapexc_$signal[0:0]$7412 + assign $0\trapexc_$signal$60[0:0]$7405 $1\trapexc_$signal$60[0:0]$7413 + assign $0\trapexc_$signal$61[0:0]$7406 $1\trapexc_$signal$61[0:0]$7414 + assign $0\trapexc_$signal$62[0:0]$7407 $1\trapexc_$signal$62[0:0]$7415 + assign $0\trapexc_$signal$67[0:0]$7408 $1\trapexc_$signal$67[0:0]$7416 + assign $0\trapexc_$signal$68[0:0]$7409 $1\trapexc_$signal$68[0:0]$7417 + assign $0\trapexc_$signal$69[0:0]$7410 $1\trapexc_$signal$69[0:0]$7418 + assign $0\trapexc_$signal$70[0:0]$7411 $1\trapexc_$signal$70[0:0]$7419 + attribute \src "libresoc.v:150170.5-150170.29" switch \initial - attribute \src "libresoc.v:149754.9-149754.17" + attribute \src "libresoc.v:150170.9-150170.17" case 1'1 case end @@ -312594,14 +278870,14 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $1\trapexc_$signal[0:0]$7480 $2\trapexc_$signal[0:0]$7488 - assign $1\trapexc_$signal$60[0:0]$7481 $2\trapexc_$signal$60[0:0]$7489 - assign $1\trapexc_$signal$61[0:0]$7482 $2\trapexc_$signal$61[0:0]$7490 - assign $1\trapexc_$signal$62[0:0]$7483 $2\trapexc_$signal$62[0:0]$7491 - assign $1\trapexc_$signal$67[0:0]$7484 $2\trapexc_$signal$67[0:0]$7492 - assign $1\trapexc_$signal$68[0:0]$7485 $2\trapexc_$signal$68[0:0]$7493 - assign $1\trapexc_$signal$69[0:0]$7486 $2\trapexc_$signal$69[0:0]$7494 - assign $1\trapexc_$signal$70[0:0]$7487 $2\trapexc_$signal$70[0:0]$7495 + assign $1\trapexc_$signal[0:0]$7412 $2\trapexc_$signal[0:0]$7420 + assign $1\trapexc_$signal$60[0:0]$7413 $2\trapexc_$signal$60[0:0]$7421 + assign $1\trapexc_$signal$61[0:0]$7414 $2\trapexc_$signal$61[0:0]$7422 + assign $1\trapexc_$signal$62[0:0]$7415 $2\trapexc_$signal$62[0:0]$7423 + assign $1\trapexc_$signal$67[0:0]$7416 $2\trapexc_$signal$67[0:0]$7424 + assign $1\trapexc_$signal$68[0:0]$7417 $2\trapexc_$signal$68[0:0]$7425 + assign $1\trapexc_$signal$69[0:0]$7418 $2\trapexc_$signal$69[0:0]$7426 + assign $1\trapexc_$signal$70[0:0]$7419 $2\trapexc_$signal$70[0:0]$7427 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" @@ -312614,14 +278890,14 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $2\trapexc_$signal[0:0]$7488 $3\trapexc_$signal[0:0]$7496 - assign $2\trapexc_$signal$60[0:0]$7489 $3\trapexc_$signal$60[0:0]$7497 - assign $2\trapexc_$signal$61[0:0]$7490 $3\trapexc_$signal$61[0:0]$7498 - assign $2\trapexc_$signal$62[0:0]$7491 $3\trapexc_$signal$62[0:0]$7499 - assign $2\trapexc_$signal$67[0:0]$7492 $3\trapexc_$signal$67[0:0]$7500 - assign $2\trapexc_$signal$68[0:0]$7493 $3\trapexc_$signal$68[0:0]$7501 - assign $2\trapexc_$signal$69[0:0]$7494 $3\trapexc_$signal$69[0:0]$7502 - assign $2\trapexc_$signal$70[0:0]$7495 $3\trapexc_$signal$70[0:0]$7503 + assign $2\trapexc_$signal[0:0]$7420 $3\trapexc_$signal[0:0]$7428 + assign $2\trapexc_$signal$60[0:0]$7421 $3\trapexc_$signal$60[0:0]$7429 + assign $2\trapexc_$signal$61[0:0]$7422 $3\trapexc_$signal$61[0:0]$7430 + assign $2\trapexc_$signal$62[0:0]$7423 $3\trapexc_$signal$62[0:0]$7431 + assign $2\trapexc_$signal$67[0:0]$7424 $3\trapexc_$signal$67[0:0]$7432 + assign $2\trapexc_$signal$68[0:0]$7425 $3\trapexc_$signal$68[0:0]$7433 + assign $2\trapexc_$signal$69[0:0]$7426 $3\trapexc_$signal$69[0:0]$7434 + assign $2\trapexc_$signal$70[0:0]$7427 $3\trapexc_$signal$70[0:0]$7435 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" switch \$71 attribute \src "libresoc.v:0.0-0.0" @@ -312634,54 +278910,54 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign { $3\trapexc_$signal$70[0:0]$7503 $3\trapexc_$signal$62[0:0]$7499 $3\trapexc_$signal$60[0:0]$7497 $3\trapexc_$signal$61[0:0]$7498 $3\trapexc_$signal[0:0]$7496 $3\trapexc_$signal$69[0:0]$7502 $3\trapexc_$signal$68[0:0]$7501 $3\trapexc_$signal$67[0:0]$7500 } \trap_op__ldst_exc + assign { $3\trapexc_$signal$70[0:0]$7435 $3\trapexc_$signal$62[0:0]$7431 $3\trapexc_$signal$60[0:0]$7429 $3\trapexc_$signal$61[0:0]$7430 $3\trapexc_$signal[0:0]$7428 $3\trapexc_$signal$69[0:0]$7434 $3\trapexc_$signal$68[0:0]$7433 $3\trapexc_$signal$67[0:0]$7432 } \trap_op__ldst_exc case - assign $3\trapexc_$signal[0:0]$7496 1'0 - assign $3\trapexc_$signal$60[0:0]$7497 1'0 - assign $3\trapexc_$signal$61[0:0]$7498 1'0 - assign $3\trapexc_$signal$62[0:0]$7499 1'0 - assign $3\trapexc_$signal$67[0:0]$7500 1'0 - assign $3\trapexc_$signal$68[0:0]$7501 1'0 - assign $3\trapexc_$signal$69[0:0]$7502 1'0 - assign $3\trapexc_$signal$70[0:0]$7503 1'0 + assign $3\trapexc_$signal[0:0]$7428 1'0 + assign $3\trapexc_$signal$60[0:0]$7429 1'0 + assign $3\trapexc_$signal$61[0:0]$7430 1'0 + assign $3\trapexc_$signal$62[0:0]$7431 1'0 + assign $3\trapexc_$signal$67[0:0]$7432 1'0 + assign $3\trapexc_$signal$68[0:0]$7433 1'0 + assign $3\trapexc_$signal$69[0:0]$7434 1'0 + assign $3\trapexc_$signal$70[0:0]$7435 1'0 end case - assign $2\trapexc_$signal[0:0]$7488 1'0 - assign $2\trapexc_$signal$60[0:0]$7489 1'0 - assign $2\trapexc_$signal$61[0:0]$7490 1'0 - assign $2\trapexc_$signal$62[0:0]$7491 1'0 - assign $2\trapexc_$signal$67[0:0]$7492 1'0 - assign $2\trapexc_$signal$68[0:0]$7493 1'0 - assign $2\trapexc_$signal$69[0:0]$7494 1'0 - assign $2\trapexc_$signal$70[0:0]$7495 1'0 - end - case - assign $1\trapexc_$signal[0:0]$7480 1'0 - assign $1\trapexc_$signal$60[0:0]$7481 1'0 - assign $1\trapexc_$signal$61[0:0]$7482 1'0 - assign $1\trapexc_$signal$62[0:0]$7483 1'0 - assign $1\trapexc_$signal$67[0:0]$7484 1'0 - assign $1\trapexc_$signal$68[0:0]$7485 1'0 - assign $1\trapexc_$signal$69[0:0]$7486 1'0 - assign $1\trapexc_$signal$70[0:0]$7487 1'0 - end - sync always - update \trapexc_$signal $0\trapexc_$signal[0:0]$7472 - update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7473 - update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7474 - update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7475 - update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7476 - update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7477 - update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7478 - update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7479 - end - attribute \src "libresoc.v:149781.3-149792.6" - process $proc$libresoc.v:149781$7504 + assign $2\trapexc_$signal[0:0]$7420 1'0 + assign $2\trapexc_$signal$60[0:0]$7421 1'0 + assign $2\trapexc_$signal$61[0:0]$7422 1'0 + assign $2\trapexc_$signal$62[0:0]$7423 1'0 + assign $2\trapexc_$signal$67[0:0]$7424 1'0 + assign $2\trapexc_$signal$68[0:0]$7425 1'0 + assign $2\trapexc_$signal$69[0:0]$7426 1'0 + assign $2\trapexc_$signal$70[0:0]$7427 1'0 + end + case + assign $1\trapexc_$signal[0:0]$7412 1'0 + assign $1\trapexc_$signal$60[0:0]$7413 1'0 + assign $1\trapexc_$signal$61[0:0]$7414 1'0 + assign $1\trapexc_$signal$62[0:0]$7415 1'0 + assign $1\trapexc_$signal$67[0:0]$7416 1'0 + assign $1\trapexc_$signal$68[0:0]$7417 1'0 + assign $1\trapexc_$signal$69[0:0]$7418 1'0 + assign $1\trapexc_$signal$70[0:0]$7419 1'0 + end + sync always + update \trapexc_$signal $0\trapexc_$signal[0:0]$7404 + update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7405 + update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7406 + update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7407 + update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7408 + update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7409 + update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7410 + update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7411 + end + attribute \src "libresoc.v:150197.3-150208.6" + process $proc$libresoc.v:150197$7436 assign { } { } assign $0\b_s[63:0] $1\b_s[63:0] - attribute \src "libresoc.v:149782.5-149782.29" + attribute \src "libresoc.v:150198.5-150198.29" switch \initial - attribute \src "libresoc.v:149782.9-149782.17" + attribute \src "libresoc.v:150198.9-150198.17" case 1'1 case end @@ -312699,17 +278975,17 @@ module \main$38 sync always update \b_s $0\b_s[63:0] end - attribute \src "libresoc.v:149793.3-149961.6" - process $proc$libresoc.v:149793$7505 + attribute \src "libresoc.v:150209.3-150377.6" + process $proc$libresoc.v:150209$7437 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\msr[63:0] $1\msr[63:0] assign $0\msr_ok[0:0] $1\msr_ok[0:0] - attribute \src "libresoc.v:149794.5-149794.29" + attribute \src "libresoc.v:150210.5-150210.29" switch \initial - attribute \src "libresoc.v:149794.9-149794.17" + attribute \src "libresoc.v:150210.9-150210.17" case 1'1 case end @@ -312923,14 +279199,14 @@ module \main$38 update \msr $0\msr[63:0] update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:149962.3-149980.6" - process $proc$libresoc.v:149962$7506 + attribute \src "libresoc.v:150378.3-150396.6" + process $proc$libresoc.v:150378$7438 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:149963.5-149963.29" + attribute \src "libresoc.v:150379.5-150379.29" switch \initial - attribute \src "libresoc.v:149963.9-149963.17" + attribute \src "libresoc.v:150379.9-150379.17" case 1'1 case end @@ -312952,14 +279228,14 @@ module \main$38 sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:149981.3-149999.6" - process $proc$libresoc.v:149981$7507 + attribute \src "libresoc.v:150397.3-150415.6" + process $proc$libresoc.v:150397$7439 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:149982.5-149982.29" + attribute \src "libresoc.v:150398.5-150398.29" switch \initial - attribute \src "libresoc.v:149982.9-149982.17" + attribute \src "libresoc.v:150398.9-150398.17" case 1'1 case end @@ -312981,13 +279257,13 @@ module \main$38 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:150000.3-150011.6" - process $proc$libresoc.v:150000$7508 + attribute \src "libresoc.v:150416.3-150427.6" + process $proc$libresoc.v:150416$7440 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:150001.5-150001.29" + attribute \src "libresoc.v:150417.5-150417.29" switch \initial - attribute \src "libresoc.v:150001.9-150001.17" + attribute \src "libresoc.v:150417.9-150417.17" case 1'1 case end @@ -313005,13 +279281,13 @@ module \main$38 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:150012.3-150023.6" - process $proc$libresoc.v:150012$7509 + attribute \src "libresoc.v:150428.3-150439.6" + process $proc$libresoc.v:150428$7441 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:150013.5-150013.29" + attribute \src "libresoc.v:150429.5-150429.29" switch \initial - attribute \src "libresoc.v:150013.9-150013.17" + attribute \src "libresoc.v:150429.9-150429.17" case 1'1 case end @@ -313029,43 +279305,43 @@ module \main$38 sync always update \b $0\b[63:0] end - connect \$13 $pos$libresoc.v:149461$7410_Y - connect \$15 $pos$libresoc.v:149462$7412_Y - connect \$17 $lt$libresoc.v:149463$7413_Y - connect \$19 $gt$libresoc.v:149464$7414_Y - connect \$21 $lt$libresoc.v:149465$7415_Y - connect \$23 $gt$libresoc.v:149466$7416_Y - connect \$25 $eq$libresoc.v:149467$7417_Y - connect \$28 $and$libresoc.v:149468$7418_Y - connect \$27 $reduce_or$libresoc.v:149469$7419_Y - connect \$31 $reduce_or$libresoc.v:149470$7420_Y - connect \$33 $or$libresoc.v:149471$7421_Y - connect \$36 $sshl$libresoc.v:149472$7422_Y - connect \$35 $pos$libresoc.v:149473$7424_Y - connect \$40 $add$libresoc.v:149474$7425_Y - connect \$42 $eq$libresoc.v:149475$7426_Y - connect \$45 $and$libresoc.v:149476$7427_Y - connect \$44 $reduce_or$libresoc.v:149477$7428_Y - connect \$49 $and$libresoc.v:149478$7429_Y - connect \$48 $reduce_or$libresoc.v:149479$7430_Y - connect \$53 $and$libresoc.v:149480$7431_Y - connect \$52 $reduce_or$libresoc.v:149481$7432_Y - connect \$57 $and$libresoc.v:149482$7433_Y - connect \$56 $reduce_or$libresoc.v:149483$7434_Y - connect \$64 $and$libresoc.v:149484$7435_Y - connect \$63 $reduce_or$libresoc.v:149485$7436_Y - connect \$72 $and$libresoc.v:149486$7437_Y - connect \$71 $reduce_or$libresoc.v:149487$7438_Y - connect \$75 $pos$libresoc.v:149488$7440_Y - connect \$77 $eq$libresoc.v:149489$7441_Y - connect \$79 $eq$libresoc.v:149490$7442_Y - connect \$81 $eq$libresoc.v:149491$7443_Y - connect \$83 $and$libresoc.v:149492$7444_Y - connect \$85 $not$libresoc.v:149493$7445_Y - connect \$87 $not$libresoc.v:149494$7446_Y - connect \$89 $eq$libresoc.v:149495$7447_Y - connect \$91 $eq$libresoc.v:149496$7448_Y - connect \$93 $and$libresoc.v:149497$7449_Y + connect \$13 $pos$libresoc.v:149877$7342_Y + connect \$15 $pos$libresoc.v:149878$7344_Y + connect \$17 $lt$libresoc.v:149879$7345_Y + connect \$19 $gt$libresoc.v:149880$7346_Y + connect \$21 $lt$libresoc.v:149881$7347_Y + connect \$23 $gt$libresoc.v:149882$7348_Y + connect \$25 $eq$libresoc.v:149883$7349_Y + connect \$28 $and$libresoc.v:149884$7350_Y + connect \$27 $reduce_or$libresoc.v:149885$7351_Y + connect \$31 $reduce_or$libresoc.v:149886$7352_Y + connect \$33 $or$libresoc.v:149887$7353_Y + connect \$36 $sshl$libresoc.v:149888$7354_Y + connect \$35 $pos$libresoc.v:149889$7356_Y + connect \$40 $add$libresoc.v:149890$7357_Y + connect \$42 $eq$libresoc.v:149891$7358_Y + connect \$45 $and$libresoc.v:149892$7359_Y + connect \$44 $reduce_or$libresoc.v:149893$7360_Y + connect \$49 $and$libresoc.v:149894$7361_Y + connect \$48 $reduce_or$libresoc.v:149895$7362_Y + connect \$53 $and$libresoc.v:149896$7363_Y + connect \$52 $reduce_or$libresoc.v:149897$7364_Y + connect \$57 $and$libresoc.v:149898$7365_Y + connect \$56 $reduce_or$libresoc.v:149899$7366_Y + connect \$64 $and$libresoc.v:149900$7367_Y + connect \$63 $reduce_or$libresoc.v:149901$7368_Y + connect \$72 $and$libresoc.v:149902$7369_Y + connect \$71 $reduce_or$libresoc.v:149903$7370_Y + connect \$75 $pos$libresoc.v:149904$7372_Y + connect \$77 $eq$libresoc.v:149905$7373_Y + connect \$79 $eq$libresoc.v:149906$7374_Y + connect \$81 $eq$libresoc.v:149907$7375_Y + connect \$83 $and$libresoc.v:149908$7376_Y + connect \$85 $not$libresoc.v:149909$7377_Y + connect \$87 $not$libresoc.v:149910$7378_Y + connect \$89 $eq$libresoc.v:149911$7379_Y + connect \$91 $eq$libresoc.v:149912$7380_Y + connect \$93 $and$libresoc.v:149913$7381_Y connect \$39 \$40 connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid @@ -313078,239 +279354,239 @@ module \main$38 connect \lt_s \$17 connect \to \trap_op__insn [25:21] end -attribute \src "libresoc.v:150039.1-150788.10" +attribute \src "libresoc.v:150455.1-151444.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" attribute \generator "nMigen" module \main$51 - attribute \src "libresoc.v:150755.3-150765.6" + attribute \src "libresoc.v:151363.3-151397.6" wire width 32 $0\a32[31:0] - attribute \src "libresoc.v:150700.3-150710.6" + attribute \src "libresoc.v:151212.3-151238.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:150678.3-150688.6" + attribute \src "libresoc.v:151146.3-151184.6" wire width 64 $0\bpermd_rb[63:0] - attribute \src "libresoc.v:150667.3-150677.6" + attribute \src "libresoc.v:151107.3-151145.6" wire width 64 $0\bpermd_rs[63:0] - attribute \src "libresoc.v:150656.3-150666.6" + attribute \src "libresoc.v:151072.3-151106.6" wire width 64 $0\clz_sig_in[63:0] - attribute \src "libresoc.v:150766.3-150784.6" + attribute \src "libresoc.v:151398.3-151440.6" wire width 64 $0\cntz_i[63:0] - attribute \src "libresoc.v:150744.3-150754.6" + attribute \src "libresoc.v:151328.3-151362.6" wire $0\count_right[0:0] - attribute \src "libresoc.v:150040.7-150040.20" + attribute \src "libresoc.v:150456.7-150456.20" wire $0\initial[0:0] - attribute \src "libresoc.v:150601.3-150655.6" + attribute \src "libresoc.v:151017.3-151071.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:150601.3-150655.6" + attribute \src "libresoc.v:151017.3-151071.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:150722.3-150732.6" + attribute \src "libresoc.v:151266.3-151296.6" wire $0\par0[0:0] - attribute \src "libresoc.v:150733.3-150743.6" + attribute \src "libresoc.v:151297.3-151327.6" wire $0\par1[0:0] - attribute \src "libresoc.v:150689.3-150699.6" + attribute \src "libresoc.v:151185.3-151211.6" wire width 64 $0\popcount_a[63:0] - attribute \src "libresoc.v:150711.3-150721.6" + attribute \src "libresoc.v:151239.3-151265.6" wire width 64 $0\popcount_data_len[63:0] - attribute \src "libresoc.v:150755.3-150765.6" + attribute \src "libresoc.v:151363.3-151397.6" wire width 32 $1\a32[31:0] - attribute \src "libresoc.v:150700.3-150710.6" + attribute \src "libresoc.v:151212.3-151238.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:150678.3-150688.6" + attribute \src "libresoc.v:151146.3-151184.6" wire width 64 $1\bpermd_rb[63:0] - attribute \src "libresoc.v:150667.3-150677.6" + attribute \src "libresoc.v:151107.3-151145.6" wire width 64 $1\bpermd_rs[63:0] - attribute \src "libresoc.v:150656.3-150666.6" + attribute \src "libresoc.v:151072.3-151106.6" wire width 64 $1\clz_sig_in[63:0] - attribute \src "libresoc.v:150766.3-150784.6" + attribute \src "libresoc.v:151398.3-151440.6" wire width 64 $1\cntz_i[63:0] - attribute \src "libresoc.v:150744.3-150754.6" + attribute \src "libresoc.v:151328.3-151362.6" wire $1\count_right[0:0] - attribute \src "libresoc.v:150601.3-150655.6" + attribute \src "libresoc.v:151017.3-151071.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:150601.3-150655.6" + attribute \src "libresoc.v:151017.3-151071.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:150722.3-150732.6" + attribute \src "libresoc.v:151266.3-151296.6" wire $1\par0[0:0] - attribute \src "libresoc.v:150733.3-150743.6" + attribute \src "libresoc.v:151297.3-151327.6" wire $1\par1[0:0] - attribute \src "libresoc.v:150689.3-150699.6" + attribute \src "libresoc.v:151185.3-151211.6" wire width 64 $1\popcount_a[63:0] - attribute \src "libresoc.v:150711.3-150721.6" + attribute \src "libresoc.v:151239.3-151265.6" wire width 64 $1\popcount_data_len[63:0] - attribute \src "libresoc.v:150766.3-150784.6" + attribute \src "libresoc.v:151398.3-151440.6" wire width 64 $2\cntz_i[63:0] - attribute \src "libresoc.v:150601.3-150655.6" + attribute \src "libresoc.v:151017.3-151071.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:150548.18-150548.103" - wire width 64 $and$libresoc.v:150548$7557_Y - attribute \src "libresoc.v:150507.18-150507.118" - wire $eq$libresoc.v:150507$7511_Y - attribute \src "libresoc.v:150508.19-150508.119" - wire $eq$libresoc.v:150508$7512_Y - attribute \src "libresoc.v:150509.19-150509.119" - wire $eq$libresoc.v:150509$7513_Y - attribute \src "libresoc.v:150510.19-150510.119" - wire $eq$libresoc.v:150510$7514_Y - attribute \src "libresoc.v:150511.19-150511.119" - wire $eq$libresoc.v:150511$7515_Y - attribute \src "libresoc.v:150512.19-150512.119" - wire $eq$libresoc.v:150512$7516_Y - attribute \src "libresoc.v:150513.19-150513.119" - wire $eq$libresoc.v:150513$7517_Y - attribute \src "libresoc.v:150514.19-150514.119" - wire $eq$libresoc.v:150514$7518_Y - attribute \src "libresoc.v:150515.19-150515.119" - wire $eq$libresoc.v:150515$7519_Y - attribute \src "libresoc.v:150516.19-150516.119" - wire $eq$libresoc.v:150516$7520_Y - attribute \src "libresoc.v:150517.19-150517.119" - wire $eq$libresoc.v:150517$7521_Y - attribute \src "libresoc.v:150518.19-150518.119" - wire $eq$libresoc.v:150518$7522_Y - attribute \src "libresoc.v:150519.19-150519.119" - wire $eq$libresoc.v:150519$7523_Y - attribute \src "libresoc.v:150520.19-150520.119" - wire $eq$libresoc.v:150520$7524_Y - attribute \src "libresoc.v:150521.19-150521.119" - wire $eq$libresoc.v:150521$7525_Y - attribute \src "libresoc.v:150522.19-150522.119" - wire $eq$libresoc.v:150522$7526_Y - attribute \src "libresoc.v:150523.19-150523.119" - wire $eq$libresoc.v:150523$7527_Y - attribute \src "libresoc.v:150524.19-150524.119" - wire $eq$libresoc.v:150524$7528_Y - attribute \src "libresoc.v:150525.19-150525.119" - wire $eq$libresoc.v:150525$7529_Y - attribute \src "libresoc.v:150526.19-150526.119" - wire $eq$libresoc.v:150526$7530_Y - attribute \src "libresoc.v:150527.19-150527.119" - wire $eq$libresoc.v:150527$7531_Y - attribute \src "libresoc.v:150528.19-150528.119" - wire $eq$libresoc.v:150528$7532_Y - attribute \src "libresoc.v:150529.19-150529.119" - wire $eq$libresoc.v:150529$7533_Y - attribute \src "libresoc.v:150530.19-150530.119" - wire $eq$libresoc.v:150530$7534_Y - attribute \src "libresoc.v:150531.19-150531.119" - wire $eq$libresoc.v:150531$7535_Y - attribute \src "libresoc.v:150532.19-150532.119" - wire $eq$libresoc.v:150532$7536_Y - attribute \src "libresoc.v:150533.19-150533.119" - wire $eq$libresoc.v:150533$7537_Y - attribute \src "libresoc.v:150534.19-150534.119" - wire $eq$libresoc.v:150534$7538_Y - attribute \src "libresoc.v:150535.19-150535.128" - wire $eq$libresoc.v:150535$7539_Y - attribute \src "libresoc.v:150551.18-150551.114" - wire $eq$libresoc.v:150551$7560_Y - attribute \src "libresoc.v:150552.18-150552.114" - wire $eq$libresoc.v:150552$7561_Y - attribute \src "libresoc.v:150553.18-150553.114" - wire $eq$libresoc.v:150553$7562_Y - attribute \src "libresoc.v:150554.18-150554.114" - wire $eq$libresoc.v:150554$7563_Y - attribute \src "libresoc.v:150555.18-150555.114" - wire $eq$libresoc.v:150555$7564_Y - attribute \src "libresoc.v:150556.18-150556.114" - wire $eq$libresoc.v:150556$7565_Y - attribute \src "libresoc.v:150557.18-150557.114" - wire $eq$libresoc.v:150557$7566_Y - attribute \src "libresoc.v:150558.18-150558.114" - wire $eq$libresoc.v:150558$7567_Y - attribute \src "libresoc.v:150559.18-150559.116" - wire $eq$libresoc.v:150559$7568_Y - attribute \src "libresoc.v:150560.18-150560.116" - wire $eq$libresoc.v:150560$7569_Y - attribute \src "libresoc.v:150561.18-150561.116" - wire $eq$libresoc.v:150561$7570_Y - attribute \src "libresoc.v:150562.18-150562.116" - wire $eq$libresoc.v:150562$7571_Y - attribute \src "libresoc.v:150563.18-150563.116" - wire $eq$libresoc.v:150563$7572_Y - attribute \src "libresoc.v:150564.18-150564.116" - wire $eq$libresoc.v:150564$7573_Y - attribute \src "libresoc.v:150565.18-150565.116" - wire $eq$libresoc.v:150565$7574_Y - attribute \src "libresoc.v:150566.18-150566.116" - wire $eq$libresoc.v:150566$7575_Y - attribute \src "libresoc.v:150567.18-150567.118" - wire $eq$libresoc.v:150567$7576_Y - attribute \src "libresoc.v:150568.18-150568.118" - wire $eq$libresoc.v:150568$7577_Y - attribute \src "libresoc.v:150569.18-150569.118" - wire $eq$libresoc.v:150569$7578_Y - attribute \src "libresoc.v:150570.18-150570.118" - wire $eq$libresoc.v:150570$7579_Y - attribute \src "libresoc.v:150571.18-150571.118" - wire $eq$libresoc.v:150571$7580_Y - attribute \src "libresoc.v:150572.18-150572.118" - wire $eq$libresoc.v:150572$7581_Y - attribute \src "libresoc.v:150573.18-150573.118" - wire $eq$libresoc.v:150573$7582_Y - attribute \src "libresoc.v:150574.18-150574.118" - wire $eq$libresoc.v:150574$7583_Y - attribute \src "libresoc.v:150575.18-150575.118" - wire $eq$libresoc.v:150575$7584_Y - attribute \src "libresoc.v:150576.18-150576.118" - wire $eq$libresoc.v:150576$7585_Y - attribute \src "libresoc.v:150577.18-150577.118" - wire $eq$libresoc.v:150577$7586_Y - attribute \src "libresoc.v:150578.18-150578.118" - wire $eq$libresoc.v:150578$7587_Y - attribute \src "libresoc.v:150579.18-150579.118" - wire $eq$libresoc.v:150579$7588_Y - attribute \src "libresoc.v:150580.18-150580.118" - wire $eq$libresoc.v:150580$7589_Y - attribute \src "libresoc.v:150581.18-150581.118" - wire $eq$libresoc.v:150581$7590_Y - attribute \src "libresoc.v:150582.18-150582.118" - wire $eq$libresoc.v:150582$7591_Y - attribute \src "libresoc.v:150583.18-150583.118" - wire $eq$libresoc.v:150583$7592_Y - attribute \src "libresoc.v:150584.18-150584.118" - wire $eq$libresoc.v:150584$7593_Y - attribute \src "libresoc.v:150585.18-150585.118" - wire $eq$libresoc.v:150585$7594_Y - attribute \src "libresoc.v:150586.18-150586.118" - wire $eq$libresoc.v:150586$7595_Y - attribute \src "libresoc.v:150537.19-150537.104" - wire width 64 $extend$libresoc.v:150537$7541_Y - attribute \src "libresoc.v:150539.19-150539.93" - wire width 8 $extend$libresoc.v:150539$7544_Y - attribute \src "libresoc.v:150541.19-150541.105" - wire width 64 $extend$libresoc.v:150541$7547_Y - attribute \src "libresoc.v:150542.19-150542.118" - wire width 64 $extend$libresoc.v:150542$7549_Y - attribute \src "libresoc.v:150546.19-150546.105" - wire width 64 $extend$libresoc.v:150546$7554_Y - attribute \src "libresoc.v:150549.18-150549.103" - wire width 64 $or$libresoc.v:150549$7558_Y - attribute \src "libresoc.v:150537.19-150537.104" - wire width 64 $pos$libresoc.v:150537$7542_Y - attribute \src "libresoc.v:150539.19-150539.93" - wire width 8 $pos$libresoc.v:150539$7545_Y - attribute \src "libresoc.v:150541.19-150541.105" - wire width 64 $pos$libresoc.v:150541$7548_Y - attribute \src "libresoc.v:150542.19-150542.118" - wire width 64 $pos$libresoc.v:150542$7550_Y - attribute \src "libresoc.v:150546.19-150546.105" - wire width 64 $pos$libresoc.v:150546$7555_Y - attribute \src "libresoc.v:150543.19-150543.131" - wire $reduce_xor$libresoc.v:150543$7551_Y - attribute \src "libresoc.v:150544.19-150544.133" - wire $reduce_xor$libresoc.v:150544$7552_Y - attribute \src "libresoc.v:150538.19-150538.112" - wire width 8 $sub$libresoc.v:150538$7543_Y - attribute \src "libresoc.v:150540.19-150540.135" - wire width 8 $ternary$libresoc.v:150540$7546_Y - attribute \src "libresoc.v:150545.19-150545.398" - wire width 32 $ternary$libresoc.v:150545$7553_Y - attribute \src "libresoc.v:150547.19-150547.621" - wire width 64 $ternary$libresoc.v:150547$7556_Y - attribute \src "libresoc.v:150536.19-150536.108" - wire $xor$libresoc.v:150536$7540_Y - attribute \src "libresoc.v:150550.18-150550.103" - wire width 64 $xor$libresoc.v:150550$7559_Y + attribute \src "libresoc.v:150964.18-150964.103" + wire width 64 $and$libresoc.v:150964$7489_Y + attribute \src "libresoc.v:150923.18-150923.118" + wire $eq$libresoc.v:150923$7443_Y + attribute \src "libresoc.v:150924.19-150924.119" + wire $eq$libresoc.v:150924$7444_Y + attribute \src "libresoc.v:150925.19-150925.119" + wire $eq$libresoc.v:150925$7445_Y + attribute \src "libresoc.v:150926.19-150926.119" + wire $eq$libresoc.v:150926$7446_Y + attribute \src "libresoc.v:150927.19-150927.119" + wire $eq$libresoc.v:150927$7447_Y + attribute \src "libresoc.v:150928.19-150928.119" + wire $eq$libresoc.v:150928$7448_Y + attribute \src "libresoc.v:150929.19-150929.119" + wire $eq$libresoc.v:150929$7449_Y + attribute \src "libresoc.v:150930.19-150930.119" + wire $eq$libresoc.v:150930$7450_Y + attribute \src "libresoc.v:150931.19-150931.119" + wire $eq$libresoc.v:150931$7451_Y + attribute \src "libresoc.v:150932.19-150932.119" + wire $eq$libresoc.v:150932$7452_Y + attribute \src "libresoc.v:150933.19-150933.119" + wire $eq$libresoc.v:150933$7453_Y + attribute \src "libresoc.v:150934.19-150934.119" + wire $eq$libresoc.v:150934$7454_Y + attribute \src "libresoc.v:150935.19-150935.119" + wire $eq$libresoc.v:150935$7455_Y + attribute \src "libresoc.v:150936.19-150936.119" + wire $eq$libresoc.v:150936$7456_Y + attribute \src "libresoc.v:150937.19-150937.119" + wire $eq$libresoc.v:150937$7457_Y + attribute \src "libresoc.v:150938.19-150938.119" + wire $eq$libresoc.v:150938$7458_Y + attribute \src "libresoc.v:150939.19-150939.119" + wire $eq$libresoc.v:150939$7459_Y + attribute \src "libresoc.v:150940.19-150940.119" + wire $eq$libresoc.v:150940$7460_Y + attribute \src "libresoc.v:150941.19-150941.119" + wire $eq$libresoc.v:150941$7461_Y + attribute \src "libresoc.v:150942.19-150942.119" + wire $eq$libresoc.v:150942$7462_Y + attribute \src "libresoc.v:150943.19-150943.119" + wire $eq$libresoc.v:150943$7463_Y + attribute \src "libresoc.v:150944.19-150944.119" + wire $eq$libresoc.v:150944$7464_Y + attribute \src "libresoc.v:150945.19-150945.119" + wire $eq$libresoc.v:150945$7465_Y + attribute \src "libresoc.v:150946.19-150946.119" + wire $eq$libresoc.v:150946$7466_Y + attribute \src "libresoc.v:150947.19-150947.119" + wire $eq$libresoc.v:150947$7467_Y + attribute \src "libresoc.v:150948.19-150948.119" + wire $eq$libresoc.v:150948$7468_Y + attribute \src "libresoc.v:150949.19-150949.119" + wire $eq$libresoc.v:150949$7469_Y + attribute \src "libresoc.v:150950.19-150950.119" + wire $eq$libresoc.v:150950$7470_Y + attribute \src "libresoc.v:150951.19-150951.128" + wire $eq$libresoc.v:150951$7471_Y + attribute \src "libresoc.v:150967.18-150967.114" + wire $eq$libresoc.v:150967$7492_Y + attribute \src "libresoc.v:150968.18-150968.114" + wire $eq$libresoc.v:150968$7493_Y + attribute \src "libresoc.v:150969.18-150969.114" + wire $eq$libresoc.v:150969$7494_Y + attribute \src "libresoc.v:150970.18-150970.114" + wire $eq$libresoc.v:150970$7495_Y + attribute \src "libresoc.v:150971.18-150971.114" + wire $eq$libresoc.v:150971$7496_Y + attribute \src "libresoc.v:150972.18-150972.114" + wire $eq$libresoc.v:150972$7497_Y + attribute \src "libresoc.v:150973.18-150973.114" + wire $eq$libresoc.v:150973$7498_Y + attribute \src "libresoc.v:150974.18-150974.114" + wire $eq$libresoc.v:150974$7499_Y + attribute \src "libresoc.v:150975.18-150975.116" + wire $eq$libresoc.v:150975$7500_Y + attribute \src "libresoc.v:150976.18-150976.116" + wire $eq$libresoc.v:150976$7501_Y + attribute \src "libresoc.v:150977.18-150977.116" + wire $eq$libresoc.v:150977$7502_Y + attribute \src "libresoc.v:150978.18-150978.116" + wire $eq$libresoc.v:150978$7503_Y + attribute \src "libresoc.v:150979.18-150979.116" + wire $eq$libresoc.v:150979$7504_Y + attribute \src "libresoc.v:150980.18-150980.116" + wire $eq$libresoc.v:150980$7505_Y + attribute \src "libresoc.v:150981.18-150981.116" + wire $eq$libresoc.v:150981$7506_Y + attribute \src "libresoc.v:150982.18-150982.116" + wire $eq$libresoc.v:150982$7507_Y + attribute \src "libresoc.v:150983.18-150983.118" + wire $eq$libresoc.v:150983$7508_Y + attribute \src "libresoc.v:150984.18-150984.118" + wire $eq$libresoc.v:150984$7509_Y + attribute \src "libresoc.v:150985.18-150985.118" + wire $eq$libresoc.v:150985$7510_Y + attribute \src "libresoc.v:150986.18-150986.118" + wire $eq$libresoc.v:150986$7511_Y + attribute \src "libresoc.v:150987.18-150987.118" + wire $eq$libresoc.v:150987$7512_Y + attribute \src "libresoc.v:150988.18-150988.118" + wire $eq$libresoc.v:150988$7513_Y + attribute \src "libresoc.v:150989.18-150989.118" + wire $eq$libresoc.v:150989$7514_Y + attribute \src "libresoc.v:150990.18-150990.118" + wire $eq$libresoc.v:150990$7515_Y + attribute \src "libresoc.v:150991.18-150991.118" + wire $eq$libresoc.v:150991$7516_Y + attribute \src "libresoc.v:150992.18-150992.118" + wire $eq$libresoc.v:150992$7517_Y + attribute \src "libresoc.v:150993.18-150993.118" + wire $eq$libresoc.v:150993$7518_Y + attribute \src "libresoc.v:150994.18-150994.118" + wire $eq$libresoc.v:150994$7519_Y + attribute \src "libresoc.v:150995.18-150995.118" + wire $eq$libresoc.v:150995$7520_Y + attribute \src "libresoc.v:150996.18-150996.118" + wire $eq$libresoc.v:150996$7521_Y + attribute \src "libresoc.v:150997.18-150997.118" + wire $eq$libresoc.v:150997$7522_Y + attribute \src "libresoc.v:150998.18-150998.118" + wire $eq$libresoc.v:150998$7523_Y + attribute \src "libresoc.v:150999.18-150999.118" + wire $eq$libresoc.v:150999$7524_Y + attribute \src "libresoc.v:151000.18-151000.118" + wire $eq$libresoc.v:151000$7525_Y + attribute \src "libresoc.v:151001.18-151001.118" + wire $eq$libresoc.v:151001$7526_Y + attribute \src "libresoc.v:151002.18-151002.118" + wire $eq$libresoc.v:151002$7527_Y + attribute \src "libresoc.v:150953.19-150953.104" + wire width 64 $extend$libresoc.v:150953$7473_Y + attribute \src "libresoc.v:150955.19-150955.93" + wire width 8 $extend$libresoc.v:150955$7476_Y + attribute \src "libresoc.v:150957.19-150957.105" + wire width 64 $extend$libresoc.v:150957$7479_Y + attribute \src "libresoc.v:150958.19-150958.118" + wire width 64 $extend$libresoc.v:150958$7481_Y + attribute \src "libresoc.v:150962.19-150962.105" + wire width 64 $extend$libresoc.v:150962$7486_Y + attribute \src "libresoc.v:150965.18-150965.103" + wire width 64 $or$libresoc.v:150965$7490_Y + attribute \src "libresoc.v:150953.19-150953.104" + wire width 64 $pos$libresoc.v:150953$7474_Y + attribute \src "libresoc.v:150955.19-150955.93" + wire width 8 $pos$libresoc.v:150955$7477_Y + attribute \src "libresoc.v:150957.19-150957.105" + wire width 64 $pos$libresoc.v:150957$7480_Y + attribute \src "libresoc.v:150958.19-150958.118" + wire width 64 $pos$libresoc.v:150958$7482_Y + attribute \src "libresoc.v:150962.19-150962.105" + wire width 64 $pos$libresoc.v:150962$7487_Y + attribute \src "libresoc.v:150959.19-150959.131" + wire $reduce_xor$libresoc.v:150959$7483_Y + attribute \src "libresoc.v:150960.19-150960.133" + wire $reduce_xor$libresoc.v:150960$7484_Y + attribute \src "libresoc.v:150954.19-150954.112" + wire width 8 $sub$libresoc.v:150954$7475_Y + attribute \src "libresoc.v:150956.19-150956.135" + wire width 8 $ternary$libresoc.v:150956$7478_Y + attribute \src "libresoc.v:150961.19-150961.398" + wire width 32 $ternary$libresoc.v:150961$7485_Y + attribute \src "libresoc.v:150963.19-150963.621" + wire width 64 $ternary$libresoc.v:150963$7488_Y + attribute \src "libresoc.v:150952.19-150952.108" + wire $xor$libresoc.v:150952$7472_Y + attribute \src "libresoc.v:150966.18-150966.103" + wire width 64 $xor$libresoc.v:150966$7491_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" @@ -313489,7 +279765,7 @@ module \main$51 wire width 64 \cntz_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" wire \count_right - attribute \src "libresoc.v:150040.7-150040.15" + attribute \src "libresoc.v:150456.7-150456.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -313755,9 +280031,9 @@ module \main$51 wire width 2 input 44 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 41 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 42 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" wire \par0 @@ -313775,10 +280051,10 @@ module \main$51 wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 43 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - cell $and $and$libresoc.v:150548$7557 + cell $and $and$libresoc.v:150964$7489 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -313786,10 +280062,10 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $and$libresoc.v:150548$7557_Y + connect \Y $and$libresoc.v:150964$7489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150507$7511 + cell $eq $eq$libresoc.v:150923$7443 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313797,10 +280073,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150507$7511_Y + connect \Y $eq$libresoc.v:150923$7443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150508$7512 + cell $eq $eq$libresoc.v:150924$7444 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313808,10 +280084,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150508$7512_Y + connect \Y $eq$libresoc.v:150924$7444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150509$7513 + cell $eq $eq$libresoc.v:150925$7445 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313819,10 +280095,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150509$7513_Y + connect \Y $eq$libresoc.v:150925$7445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150510$7514 + cell $eq $eq$libresoc.v:150926$7446 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313830,10 +280106,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150510$7514_Y + connect \Y $eq$libresoc.v:150926$7446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150511$7515 + cell $eq $eq$libresoc.v:150927$7447 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313841,10 +280117,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150511$7515_Y + connect \Y $eq$libresoc.v:150927$7447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150512$7516 + cell $eq $eq$libresoc.v:150928$7448 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313852,10 +280128,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150512$7516_Y + connect \Y $eq$libresoc.v:150928$7448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150513$7517 + cell $eq $eq$libresoc.v:150929$7449 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313863,10 +280139,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150513$7517_Y + connect \Y $eq$libresoc.v:150929$7449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150514$7518 + cell $eq $eq$libresoc.v:150930$7450 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313874,10 +280150,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150514$7518_Y + connect \Y $eq$libresoc.v:150930$7450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150515$7519 + cell $eq $eq$libresoc.v:150931$7451 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313885,10 +280161,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150515$7519_Y + connect \Y $eq$libresoc.v:150931$7451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150516$7520 + cell $eq $eq$libresoc.v:150932$7452 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313896,10 +280172,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150516$7520_Y + connect \Y $eq$libresoc.v:150932$7452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150517$7521 + cell $eq $eq$libresoc.v:150933$7453 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313907,10 +280183,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150517$7521_Y + connect \Y $eq$libresoc.v:150933$7453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150518$7522 + cell $eq $eq$libresoc.v:150934$7454 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313918,10 +280194,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150518$7522_Y + connect \Y $eq$libresoc.v:150934$7454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150519$7523 + cell $eq $eq$libresoc.v:150935$7455 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313929,10 +280205,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150519$7523_Y + connect \Y $eq$libresoc.v:150935$7455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150520$7524 + cell $eq $eq$libresoc.v:150936$7456 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313940,10 +280216,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150520$7524_Y + connect \Y $eq$libresoc.v:150936$7456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150521$7525 + cell $eq $eq$libresoc.v:150937$7457 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313951,10 +280227,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150521$7525_Y + connect \Y $eq$libresoc.v:150937$7457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150522$7526 + cell $eq $eq$libresoc.v:150938$7458 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313962,10 +280238,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150522$7526_Y + connect \Y $eq$libresoc.v:150938$7458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150523$7527 + cell $eq $eq$libresoc.v:150939$7459 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313973,10 +280249,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150523$7527_Y + connect \Y $eq$libresoc.v:150939$7459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150524$7528 + cell $eq $eq$libresoc.v:150940$7460 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313984,10 +280260,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150524$7528_Y + connect \Y $eq$libresoc.v:150940$7460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150525$7529 + cell $eq $eq$libresoc.v:150941$7461 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313995,10 +280271,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150525$7529_Y + connect \Y $eq$libresoc.v:150941$7461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150526$7530 + cell $eq $eq$libresoc.v:150942$7462 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314006,10 +280282,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150526$7530_Y + connect \Y $eq$libresoc.v:150942$7462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150527$7531 + cell $eq $eq$libresoc.v:150943$7463 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314017,10 +280293,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150527$7531_Y + connect \Y $eq$libresoc.v:150943$7463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150528$7532 + cell $eq $eq$libresoc.v:150944$7464 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314028,10 +280304,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150528$7532_Y + connect \Y $eq$libresoc.v:150944$7464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150529$7533 + cell $eq $eq$libresoc.v:150945$7465 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314039,10 +280315,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150529$7533_Y + connect \Y $eq$libresoc.v:150945$7465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150530$7534 + cell $eq $eq$libresoc.v:150946$7466 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314050,10 +280326,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150530$7534_Y + connect \Y $eq$libresoc.v:150946$7466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150531$7535 + cell $eq $eq$libresoc.v:150947$7467 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314061,10 +280337,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150531$7535_Y + connect \Y $eq$libresoc.v:150947$7467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150532$7536 + cell $eq $eq$libresoc.v:150948$7468 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314072,10 +280348,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150532$7536_Y + connect \Y $eq$libresoc.v:150948$7468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150533$7537 + cell $eq $eq$libresoc.v:150949$7469 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314083,10 +280359,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150533$7537_Y + connect \Y $eq$libresoc.v:150949$7469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150534$7538 + cell $eq $eq$libresoc.v:150950$7470 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314094,10 +280370,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150534$7538_Y + connect \Y $eq$libresoc.v:150950$7470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $eq $eq$libresoc.v:150535$7539 + cell $eq $eq$libresoc.v:150951$7471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314105,10 +280381,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \logical_op__data_len [3] connect \B 1'1 - connect \Y $eq$libresoc.v:150535$7539_Y + connect \Y $eq$libresoc.v:150951$7471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150551$7560 + cell $eq $eq$libresoc.v:150967$7492 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314116,10 +280392,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150551$7560_Y + connect \Y $eq$libresoc.v:150967$7492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150552$7561 + cell $eq $eq$libresoc.v:150968$7493 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314127,10 +280403,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150552$7561_Y + connect \Y $eq$libresoc.v:150968$7493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150553$7562 + cell $eq $eq$libresoc.v:150969$7494 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314138,10 +280414,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150553$7562_Y + connect \Y $eq$libresoc.v:150969$7494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150554$7563 + cell $eq $eq$libresoc.v:150970$7495 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314149,10 +280425,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150554$7563_Y + connect \Y $eq$libresoc.v:150970$7495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150555$7564 + cell $eq $eq$libresoc.v:150971$7496 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314160,10 +280436,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150555$7564_Y + connect \Y $eq$libresoc.v:150971$7496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150556$7565 + cell $eq $eq$libresoc.v:150972$7497 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314171,10 +280447,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150556$7565_Y + connect \Y $eq$libresoc.v:150972$7497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150557$7566 + cell $eq $eq$libresoc.v:150973$7498 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314182,10 +280458,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150557$7566_Y + connect \Y $eq$libresoc.v:150973$7498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150558$7567 + cell $eq $eq$libresoc.v:150974$7499 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314193,10 +280469,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150558$7567_Y + connect \Y $eq$libresoc.v:150974$7499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150559$7568 + cell $eq $eq$libresoc.v:150975$7500 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314204,10 +280480,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150559$7568_Y + connect \Y $eq$libresoc.v:150975$7500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150560$7569 + cell $eq $eq$libresoc.v:150976$7501 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314215,10 +280491,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150560$7569_Y + connect \Y $eq$libresoc.v:150976$7501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150561$7570 + cell $eq $eq$libresoc.v:150977$7502 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314226,10 +280502,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150561$7570_Y + connect \Y $eq$libresoc.v:150977$7502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150562$7571 + cell $eq $eq$libresoc.v:150978$7503 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314237,10 +280513,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150562$7571_Y + connect \Y $eq$libresoc.v:150978$7503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150563$7572 + cell $eq $eq$libresoc.v:150979$7504 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314248,10 +280524,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150563$7572_Y + connect \Y $eq$libresoc.v:150979$7504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150564$7573 + cell $eq $eq$libresoc.v:150980$7505 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314259,10 +280535,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150564$7573_Y + connect \Y $eq$libresoc.v:150980$7505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150565$7574 + cell $eq $eq$libresoc.v:150981$7506 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314270,10 +280546,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150565$7574_Y + connect \Y $eq$libresoc.v:150981$7506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150566$7575 + cell $eq $eq$libresoc.v:150982$7507 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314281,10 +280557,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150566$7575_Y + connect \Y $eq$libresoc.v:150982$7507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150567$7576 + cell $eq $eq$libresoc.v:150983$7508 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314292,10 +280568,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150567$7576_Y + connect \Y $eq$libresoc.v:150983$7508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150568$7577 + cell $eq $eq$libresoc.v:150984$7509 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314303,10 +280579,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150568$7577_Y + connect \Y $eq$libresoc.v:150984$7509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150569$7578 + cell $eq $eq$libresoc.v:150985$7510 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314314,10 +280590,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150569$7578_Y + connect \Y $eq$libresoc.v:150985$7510_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150570$7579 + cell $eq $eq$libresoc.v:150986$7511 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314325,10 +280601,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150570$7579_Y + connect \Y $eq$libresoc.v:150986$7511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150571$7580 + cell $eq $eq$libresoc.v:150987$7512 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314336,10 +280612,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150571$7580_Y + connect \Y $eq$libresoc.v:150987$7512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150572$7581 + cell $eq $eq$libresoc.v:150988$7513 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314347,10 +280623,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150572$7581_Y + connect \Y $eq$libresoc.v:150988$7513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150573$7582 + cell $eq $eq$libresoc.v:150989$7514 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314358,10 +280634,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150573$7582_Y + connect \Y $eq$libresoc.v:150989$7514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150574$7583 + cell $eq $eq$libresoc.v:150990$7515 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314369,10 +280645,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150574$7583_Y + connect \Y $eq$libresoc.v:150990$7515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150575$7584 + cell $eq $eq$libresoc.v:150991$7516 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314380,10 +280656,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150575$7584_Y + connect \Y $eq$libresoc.v:150991$7516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150576$7585 + cell $eq $eq$libresoc.v:150992$7517 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314391,10 +280667,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150576$7585_Y + connect \Y $eq$libresoc.v:150992$7517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150577$7586 + cell $eq $eq$libresoc.v:150993$7518 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314402,10 +280678,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150577$7586_Y + connect \Y $eq$libresoc.v:150993$7518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150578$7587 + cell $eq $eq$libresoc.v:150994$7519 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314413,10 +280689,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150578$7587_Y + connect \Y $eq$libresoc.v:150994$7519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150579$7588 + cell $eq $eq$libresoc.v:150995$7520 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314424,10 +280700,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150579$7588_Y + connect \Y $eq$libresoc.v:150995$7520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150580$7589 + cell $eq $eq$libresoc.v:150996$7521 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314435,10 +280711,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150580$7589_Y + connect \Y $eq$libresoc.v:150996$7521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150581$7590 + cell $eq $eq$libresoc.v:150997$7522 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314446,10 +280722,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150581$7590_Y + connect \Y $eq$libresoc.v:150997$7522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150582$7591 + cell $eq $eq$libresoc.v:150998$7523 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314457,10 +280733,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150582$7591_Y + connect \Y $eq$libresoc.v:150998$7523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150583$7592 + cell $eq $eq$libresoc.v:150999$7524 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314468,10 +280744,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150583$7592_Y + connect \Y $eq$libresoc.v:150999$7524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150584$7593 + cell $eq $eq$libresoc.v:151000$7525 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314479,10 +280755,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150584$7593_Y + connect \Y $eq$libresoc.v:151000$7525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150585$7594 + cell $eq $eq$libresoc.v:151001$7526 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314490,10 +280766,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150585$7594_Y + connect \Y $eq$libresoc.v:151001$7526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150586$7595 + cell $eq $eq$libresoc.v:151002$7527 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314501,50 +280777,50 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150586$7595_Y + connect \Y $eq$libresoc.v:151002$7527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $extend$libresoc.v:150537$7541 + cell $pos $extend$libresoc.v:150953$7473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 64 connect \A \$158 - connect \Y $extend$libresoc.v:150537$7541_Y + connect \Y $extend$libresoc.v:150953$7473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $extend$libresoc.v:150539$7544 + cell $pos $extend$libresoc.v:150955$7476 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 8 connect \A \clz_lz - connect \Y $extend$libresoc.v:150539$7544_Y + connect \Y $extend$libresoc.v:150955$7476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $extend$libresoc.v:150541$7547 + cell $pos $extend$libresoc.v:150957$7479 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \$166 - connect \Y $extend$libresoc.v:150541$7547_Y + connect \Y $extend$libresoc.v:150957$7479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:150542$7549 + cell $pos $extend$libresoc.v:150958$7481 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 64 connect \A \logical_op__data_len - connect \Y $extend$libresoc.v:150542$7549_Y + connect \Y $extend$libresoc.v:150958$7481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $extend$libresoc.v:150546$7554 + cell $pos $extend$libresoc.v:150962$7486 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$176 - connect \Y $extend$libresoc.v:150546$7554_Y + connect \Y $extend$libresoc.v:150962$7486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - cell $or $or$libresoc.v:150549$7558 + cell $or $or$libresoc.v:150965$7490 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -314552,66 +280828,66 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $or$libresoc.v:150549$7558_Y + connect \Y $or$libresoc.v:150965$7490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $pos$libresoc.v:150537$7542 + cell $pos $pos$libresoc.v:150953$7474 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150537$7541_Y - connect \Y $pos$libresoc.v:150537$7542_Y + connect \A $extend$libresoc.v:150953$7473_Y + connect \Y $pos$libresoc.v:150953$7474_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $pos$libresoc.v:150539$7545 + cell $pos $pos$libresoc.v:150955$7477 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:150539$7544_Y - connect \Y $pos$libresoc.v:150539$7545_Y + connect \A $extend$libresoc.v:150955$7476_Y + connect \Y $pos$libresoc.v:150955$7477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $pos$libresoc.v:150541$7548 + cell $pos $pos$libresoc.v:150957$7480 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150541$7547_Y - connect \Y $pos$libresoc.v:150541$7548_Y + connect \A $extend$libresoc.v:150957$7479_Y + connect \Y $pos$libresoc.v:150957$7480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:150542$7550 + cell $pos $pos$libresoc.v:150958$7482 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150542$7549_Y - connect \Y $pos$libresoc.v:150542$7550_Y + connect \A $extend$libresoc.v:150958$7481_Y + connect \Y $pos$libresoc.v:150958$7482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $pos$libresoc.v:150546$7555 + cell $pos $pos$libresoc.v:150962$7487 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150546$7554_Y - connect \Y $pos$libresoc.v:150546$7555_Y + connect \A $extend$libresoc.v:150962$7486_Y + connect \Y $pos$libresoc.v:150962$7487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $reduce_xor$libresoc.v:150543$7551 + cell $reduce_xor $reduce_xor$libresoc.v:150959$7483 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $reduce_xor$libresoc.v:150543$7551_Y + connect \Y $reduce_xor$libresoc.v:150959$7483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $reduce_xor $reduce_xor$libresoc.v:150544$7552 + cell $reduce_xor $reduce_xor$libresoc.v:150960$7484 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $reduce_xor$libresoc.v:150544$7552_Y + connect \Y $reduce_xor$libresoc.v:150960$7484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $sub $sub$libresoc.v:150538$7543 + cell $sub $sub$libresoc.v:150954$7475 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -314619,34 +280895,34 @@ module \main$51 parameter \Y_WIDTH 8 connect \A \clz_lz connect \B 6'100000 - connect \Y $sub$libresoc.v:150538$7543_Y + connect \Y $sub$libresoc.v:150954$7475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $mux $ternary$libresoc.v:150540$7546 + cell $mux $ternary$libresoc.v:150956$7478 parameter \WIDTH 8 connect \A \$164 connect \B \$162 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:150540$7546_Y + connect \Y $ternary$libresoc.v:150956$7478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $mux $ternary$libresoc.v:150545$7553 + cell $mux $ternary$libresoc.v:150961$7485 parameter \WIDTH 32 connect \A \a32 connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } connect \S \count_right - connect \Y $ternary$libresoc.v:150545$7553_Y + connect \Y $ternary$libresoc.v:150961$7485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - cell $mux $ternary$libresoc.v:150547$7556 + cell $mux $ternary$libresoc.v:150963$7488 parameter \WIDTH 64 connect \A \ra connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } connect \S \count_right - connect \Y $ternary$libresoc.v:150547$7556_Y + connect \Y $ternary$libresoc.v:150963$7488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $xor $xor$libresoc.v:150536$7540 + cell $xor $xor$libresoc.v:150952$7472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314654,10 +280930,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \par0 connect \B \par1 - connect \Y $xor$libresoc.v:150536$7540_Y + connect \Y $xor$libresoc.v:150952$7472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - cell $xor $xor$libresoc.v:150550$7559 + cell $xor $xor$libresoc.v:150966$7491 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -314665,47 +280941,47 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $xor$libresoc.v:150550$7559_Y + connect \Y $xor$libresoc.v:150966$7491_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:150587.10-150591.4" + attribute \src "libresoc.v:151003.10-151007.4" cell \bpermd \bpermd connect \ra \bpermd_ra connect \rb \bpermd_rb connect \rs \bpermd_rs end attribute \module_not_derived 1 - attribute \src "libresoc.v:150592.7-150595.4" + attribute \src "libresoc.v:151008.7-151011.4" cell \clz \clz connect \lz \clz_lz connect \sig_in \clz_sig_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:150596.12-150600.4" + attribute \src "libresoc.v:151012.12-151016.4" cell \popcount \popcount connect \a \popcount_a connect \data_len \popcount_data_len connect \o \popcount_o end - attribute \src "libresoc.v:150040.7-150040.20" - process $proc$libresoc.v:150040$7608 + attribute \src "libresoc.v:150456.7-150456.20" + process $proc$libresoc.v:150456$7540 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:150601.3-150655.6" - process $proc$libresoc.v:150601$7596 + attribute \src "libresoc.v:151017.3-151071.6" + process $proc$libresoc.v:151017$7528 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:150602.5-150602.29" + attribute \src "libresoc.v:151018.5-151018.29" switch \initial - attribute \src "libresoc.v:150602.9-150602.17" + attribute \src "libresoc.v:151018.9-151018.17" case 1'1 case end @@ -314773,20 +281049,38 @@ module \main$51 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:150656.3-150666.6" - process $proc$libresoc.v:150656$7597 + attribute \src "libresoc.v:151072.3-151106.6" + process $proc$libresoc.v:151072$7529 assign { } { } assign { } { } assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] - attribute \src "libresoc.v:150657.5-150657.29" + attribute \src "libresoc.v:151073.5-151073.29" switch \initial - attribute \src "libresoc.v:150657.9-150657.17" + attribute \src "libresoc.v:151073.9-151073.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign { } { } assign $1\clz_sig_in[63:0] \cntz_i @@ -314796,20 +281090,41 @@ module \main$51 sync always update \clz_sig_in $0\clz_sig_in[63:0] end - attribute \src "libresoc.v:150667.3-150677.6" - process $proc$libresoc.v:150667$7598 + attribute \src "libresoc.v:151107.3-151145.6" + process $proc$libresoc.v:151107$7530 assign { } { } assign { } { } assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] - attribute \src "libresoc.v:150668.5-150668.29" + attribute \src "libresoc.v:151108.5-151108.29" switch \initial - attribute \src "libresoc.v:150668.9-150668.17" + attribute \src "libresoc.v:151108.9-151108.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0001001 assign { } { } assign $1\bpermd_rs[63:0] \ra @@ -314819,20 +281134,41 @@ module \main$51 sync always update \bpermd_rs $0\bpermd_rs[63:0] end - attribute \src "libresoc.v:150678.3-150688.6" - process $proc$libresoc.v:150678$7599 + attribute \src "libresoc.v:151146.3-151184.6" + process $proc$libresoc.v:151146$7531 assign { } { } assign { } { } assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] - attribute \src "libresoc.v:150679.5-150679.29" + attribute \src "libresoc.v:151147.5-151147.29" switch \initial - attribute \src "libresoc.v:150679.9-150679.17" + attribute \src "libresoc.v:151147.9-151147.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0001001 assign { } { } assign $1\bpermd_rb[63:0] \rb @@ -314842,20 +281178,32 @@ module \main$51 sync always update \bpermd_rb $0\bpermd_rb[63:0] end - attribute \src "libresoc.v:150689.3-150699.6" - process $proc$libresoc.v:150689$7600 + attribute \src "libresoc.v:151185.3-151211.6" + process $proc$libresoc.v:151185$7532 assign { } { } assign { } { } assign $0\popcount_a[63:0] $1\popcount_a[63:0] - attribute \src "libresoc.v:150690.5-150690.29" + attribute \src "libresoc.v:151186.5-151186.29" switch \initial - attribute \src "libresoc.v:150690.9-150690.17" + attribute \src "libresoc.v:151186.9-151186.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign { } { } assign $1\popcount_a[63:0] \ra @@ -314865,20 +281213,32 @@ module \main$51 sync always update \popcount_a $0\popcount_a[63:0] end - attribute \src "libresoc.v:150700.3-150710.6" - process $proc$libresoc.v:150700$7601 + attribute \src "libresoc.v:151212.3-151238.6" + process $proc$libresoc.v:151212$7533 assign { } { } assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:150701.5-150701.29" + attribute \src "libresoc.v:151213.5-151213.29" switch \initial - attribute \src "libresoc.v:150701.9-150701.17" + attribute \src "libresoc.v:151213.9-151213.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign { } { } assign $1\b[63:0] \rb @@ -314888,20 +281248,32 @@ module \main$51 sync always update \b $0\b[63:0] end - attribute \src "libresoc.v:150711.3-150721.6" - process $proc$libresoc.v:150711$7602 + attribute \src "libresoc.v:151239.3-151265.6" + process $proc$libresoc.v:151239$7534 assign { } { } assign { } { } assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] - attribute \src "libresoc.v:150712.5-150712.29" + attribute \src "libresoc.v:151240.5-151240.29" switch \initial - attribute \src "libresoc.v:150712.9-150712.17" + attribute \src "libresoc.v:151240.9-151240.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign { } { } assign $1\popcount_data_len[63:0] \$169 @@ -314911,20 +281283,35 @@ module \main$51 sync always update \popcount_data_len $0\popcount_data_len[63:0] end - attribute \src "libresoc.v:150722.3-150732.6" - process $proc$libresoc.v:150722$7603 + attribute \src "libresoc.v:151266.3-151296.6" + process $proc$libresoc.v:151266$7535 assign { } { } assign { } { } assign $0\par0[0:0] $1\par0[0:0] - attribute \src "libresoc.v:150723.5-150723.29" + attribute \src "libresoc.v:151267.5-151267.29" switch \initial - attribute \src "libresoc.v:150723.9-150723.17" + attribute \src "libresoc.v:151267.9-151267.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\par0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\par0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\par0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\par0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\par0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0110111 assign { } { } assign $1\par0[0:0] \$171 @@ -314934,20 +281321,35 @@ module \main$51 sync always update \par0 $0\par0[0:0] end - attribute \src "libresoc.v:150733.3-150743.6" - process $proc$libresoc.v:150733$7604 + attribute \src "libresoc.v:151297.3-151327.6" + process $proc$libresoc.v:151297$7536 assign { } { } assign { } { } assign $0\par1[0:0] $1\par1[0:0] - attribute \src "libresoc.v:150734.5-150734.29" + attribute \src "libresoc.v:151298.5-151298.29" switch \initial - attribute \src "libresoc.v:150734.9-150734.17" + attribute \src "libresoc.v:151298.9-151298.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\par1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\par1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\par1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\par1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\par1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0110111 assign { } { } assign $1\par1[0:0] \$173 @@ -314957,20 +281359,38 @@ module \main$51 sync always update \par1 $0\par1[0:0] end - attribute \src "libresoc.v:150744.3-150754.6" - process $proc$libresoc.v:150744$7605 + attribute \src "libresoc.v:151328.3-151362.6" + process $proc$libresoc.v:151328$7537 assign { } { } assign { } { } assign $0\count_right[0:0] $1\count_right[0:0] - attribute \src "libresoc.v:150745.5-150745.29" + attribute \src "libresoc.v:151329.5-151329.29" switch \initial - attribute \src "libresoc.v:150745.9-150745.17" + attribute \src "libresoc.v:151329.9-151329.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\count_right[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\count_right[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\count_right[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\count_right[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\count_right[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\count_right[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign { } { } assign $1\count_right[0:0] \logical_op__insn [10] @@ -314980,20 +281400,38 @@ module \main$51 sync always update \count_right $0\count_right[0:0] end - attribute \src "libresoc.v:150755.3-150765.6" - process $proc$libresoc.v:150755$7606 + attribute \src "libresoc.v:151363.3-151397.6" + process $proc$libresoc.v:151363$7538 assign { } { } assign { } { } assign $0\a32[31:0] $1\a32[31:0] - attribute \src "libresoc.v:150756.5-150756.29" + attribute \src "libresoc.v:151364.5-151364.29" switch \initial - attribute \src "libresoc.v:150756.9-150756.17" + attribute \src "libresoc.v:151364.9-151364.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\a32[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\a32[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\a32[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\a32[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\a32[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\a32[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign { } { } assign $1\a32[31:0] \ra [31:0] @@ -315003,20 +281441,38 @@ module \main$51 sync always update \a32 $0\a32[31:0] end - attribute \src "libresoc.v:150766.3-150784.6" - process $proc$libresoc.v:150766$7607 + attribute \src "libresoc.v:151398.3-151440.6" + process $proc$libresoc.v:151398$7539 assign { } { } assign { } { } assign $0\cntz_i[63:0] $1\cntz_i[63:0] - attribute \src "libresoc.v:150767.5-150767.29" + attribute \src "libresoc.v:151399.5-151399.29" switch \initial - attribute \src "libresoc.v:150767.9-150767.17" + attribute \src "libresoc.v:151399.9-151399.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign { } { } assign $1\cntz_i[63:0] $2\cntz_i[63:0] @@ -315037,193 +281493,193 @@ module \main$51 sync always update \cntz_i $0\cntz_i[63:0] end - connect \$99 $eq$libresoc.v:150507$7511_Y - connect \$101 $eq$libresoc.v:150508$7512_Y - connect \$103 $eq$libresoc.v:150509$7513_Y - connect \$105 $eq$libresoc.v:150510$7514_Y - connect \$107 $eq$libresoc.v:150511$7515_Y - connect \$109 $eq$libresoc.v:150512$7516_Y - connect \$111 $eq$libresoc.v:150513$7517_Y - connect \$113 $eq$libresoc.v:150514$7518_Y - connect \$115 $eq$libresoc.v:150515$7519_Y - connect \$117 $eq$libresoc.v:150516$7520_Y - connect \$119 $eq$libresoc.v:150517$7521_Y - connect \$121 $eq$libresoc.v:150518$7522_Y - connect \$123 $eq$libresoc.v:150519$7523_Y - connect \$125 $eq$libresoc.v:150520$7524_Y - connect \$127 $eq$libresoc.v:150521$7525_Y - connect \$129 $eq$libresoc.v:150522$7526_Y - connect \$131 $eq$libresoc.v:150523$7527_Y - connect \$133 $eq$libresoc.v:150524$7528_Y - connect \$135 $eq$libresoc.v:150525$7529_Y - connect \$137 $eq$libresoc.v:150526$7530_Y - connect \$139 $eq$libresoc.v:150527$7531_Y - connect \$141 $eq$libresoc.v:150528$7532_Y - connect \$143 $eq$libresoc.v:150529$7533_Y - connect \$145 $eq$libresoc.v:150530$7534_Y - connect \$147 $eq$libresoc.v:150531$7535_Y - connect \$149 $eq$libresoc.v:150532$7536_Y - connect \$151 $eq$libresoc.v:150533$7537_Y - connect \$153 $eq$libresoc.v:150534$7538_Y - connect \$155 $eq$libresoc.v:150535$7539_Y - connect \$158 $xor$libresoc.v:150536$7540_Y - connect \$157 $pos$libresoc.v:150537$7542_Y - connect \$162 $sub$libresoc.v:150538$7543_Y - connect \$164 $pos$libresoc.v:150539$7545_Y - connect \$166 $ternary$libresoc.v:150540$7546_Y - connect \$161 $pos$libresoc.v:150541$7548_Y - connect \$169 $pos$libresoc.v:150542$7550_Y - connect \$171 $reduce_xor$libresoc.v:150543$7551_Y - connect \$173 $reduce_xor$libresoc.v:150544$7552_Y - connect \$176 $ternary$libresoc.v:150545$7553_Y - connect \$175 $pos$libresoc.v:150546$7555_Y - connect \$179 $ternary$libresoc.v:150547$7556_Y - connect \$21 $and$libresoc.v:150548$7557_Y - connect \$23 $or$libresoc.v:150549$7558_Y - connect \$25 $xor$libresoc.v:150550$7559_Y - connect \$27 $eq$libresoc.v:150551$7560_Y - connect \$29 $eq$libresoc.v:150552$7561_Y - connect \$31 $eq$libresoc.v:150553$7562_Y - connect \$33 $eq$libresoc.v:150554$7563_Y - connect \$35 $eq$libresoc.v:150555$7564_Y - connect \$37 $eq$libresoc.v:150556$7565_Y - connect \$39 $eq$libresoc.v:150557$7566_Y - connect \$41 $eq$libresoc.v:150558$7567_Y - connect \$43 $eq$libresoc.v:150559$7568_Y - connect \$45 $eq$libresoc.v:150560$7569_Y - connect \$47 $eq$libresoc.v:150561$7570_Y - connect \$49 $eq$libresoc.v:150562$7571_Y - connect \$51 $eq$libresoc.v:150563$7572_Y - connect \$53 $eq$libresoc.v:150564$7573_Y - connect \$55 $eq$libresoc.v:150565$7574_Y - connect \$57 $eq$libresoc.v:150566$7575_Y - connect \$59 $eq$libresoc.v:150567$7576_Y - connect \$61 $eq$libresoc.v:150568$7577_Y - connect \$63 $eq$libresoc.v:150569$7578_Y - connect \$65 $eq$libresoc.v:150570$7579_Y - connect \$67 $eq$libresoc.v:150571$7580_Y - connect \$69 $eq$libresoc.v:150572$7581_Y - connect \$71 $eq$libresoc.v:150573$7582_Y - connect \$73 $eq$libresoc.v:150574$7583_Y - connect \$75 $eq$libresoc.v:150575$7584_Y - connect \$77 $eq$libresoc.v:150576$7585_Y - connect \$79 $eq$libresoc.v:150577$7586_Y - connect \$81 $eq$libresoc.v:150578$7587_Y - connect \$83 $eq$libresoc.v:150579$7588_Y - connect \$85 $eq$libresoc.v:150580$7589_Y - connect \$87 $eq$libresoc.v:150581$7590_Y - connect \$89 $eq$libresoc.v:150582$7591_Y - connect \$91 $eq$libresoc.v:150583$7592_Y - connect \$93 $eq$libresoc.v:150584$7593_Y - connect \$95 $eq$libresoc.v:150585$7594_Y - connect \$97 $eq$libresoc.v:150586$7595_Y + connect \$99 $eq$libresoc.v:150923$7443_Y + connect \$101 $eq$libresoc.v:150924$7444_Y + connect \$103 $eq$libresoc.v:150925$7445_Y + connect \$105 $eq$libresoc.v:150926$7446_Y + connect \$107 $eq$libresoc.v:150927$7447_Y + connect \$109 $eq$libresoc.v:150928$7448_Y + connect \$111 $eq$libresoc.v:150929$7449_Y + connect \$113 $eq$libresoc.v:150930$7450_Y + connect \$115 $eq$libresoc.v:150931$7451_Y + connect \$117 $eq$libresoc.v:150932$7452_Y + connect \$119 $eq$libresoc.v:150933$7453_Y + connect \$121 $eq$libresoc.v:150934$7454_Y + connect \$123 $eq$libresoc.v:150935$7455_Y + connect \$125 $eq$libresoc.v:150936$7456_Y + connect \$127 $eq$libresoc.v:150937$7457_Y + connect \$129 $eq$libresoc.v:150938$7458_Y + connect \$131 $eq$libresoc.v:150939$7459_Y + connect \$133 $eq$libresoc.v:150940$7460_Y + connect \$135 $eq$libresoc.v:150941$7461_Y + connect \$137 $eq$libresoc.v:150942$7462_Y + connect \$139 $eq$libresoc.v:150943$7463_Y + connect \$141 $eq$libresoc.v:150944$7464_Y + connect \$143 $eq$libresoc.v:150945$7465_Y + connect \$145 $eq$libresoc.v:150946$7466_Y + connect \$147 $eq$libresoc.v:150947$7467_Y + connect \$149 $eq$libresoc.v:150948$7468_Y + connect \$151 $eq$libresoc.v:150949$7469_Y + connect \$153 $eq$libresoc.v:150950$7470_Y + connect \$155 $eq$libresoc.v:150951$7471_Y + connect \$158 $xor$libresoc.v:150952$7472_Y + connect \$157 $pos$libresoc.v:150953$7474_Y + connect \$162 $sub$libresoc.v:150954$7475_Y + connect \$164 $pos$libresoc.v:150955$7477_Y + connect \$166 $ternary$libresoc.v:150956$7478_Y + connect \$161 $pos$libresoc.v:150957$7480_Y + connect \$169 $pos$libresoc.v:150958$7482_Y + connect \$171 $reduce_xor$libresoc.v:150959$7483_Y + connect \$173 $reduce_xor$libresoc.v:150960$7484_Y + connect \$176 $ternary$libresoc.v:150961$7485_Y + connect \$175 $pos$libresoc.v:150962$7487_Y + connect \$179 $ternary$libresoc.v:150963$7488_Y + connect \$21 $and$libresoc.v:150964$7489_Y + connect \$23 $or$libresoc.v:150965$7490_Y + connect \$25 $xor$libresoc.v:150966$7491_Y + connect \$27 $eq$libresoc.v:150967$7492_Y + connect \$29 $eq$libresoc.v:150968$7493_Y + connect \$31 $eq$libresoc.v:150969$7494_Y + connect \$33 $eq$libresoc.v:150970$7495_Y + connect \$35 $eq$libresoc.v:150971$7496_Y + connect \$37 $eq$libresoc.v:150972$7497_Y + connect \$39 $eq$libresoc.v:150973$7498_Y + connect \$41 $eq$libresoc.v:150974$7499_Y + connect \$43 $eq$libresoc.v:150975$7500_Y + connect \$45 $eq$libresoc.v:150976$7501_Y + connect \$47 $eq$libresoc.v:150977$7502_Y + connect \$49 $eq$libresoc.v:150978$7503_Y + connect \$51 $eq$libresoc.v:150979$7504_Y + connect \$53 $eq$libresoc.v:150980$7505_Y + connect \$55 $eq$libresoc.v:150981$7506_Y + connect \$57 $eq$libresoc.v:150982$7507_Y + connect \$59 $eq$libresoc.v:150983$7508_Y + connect \$61 $eq$libresoc.v:150984$7509_Y + connect \$63 $eq$libresoc.v:150985$7510_Y + connect \$65 $eq$libresoc.v:150986$7511_Y + connect \$67 $eq$libresoc.v:150987$7512_Y + connect \$69 $eq$libresoc.v:150988$7513_Y + connect \$71 $eq$libresoc.v:150989$7514_Y + connect \$73 $eq$libresoc.v:150990$7515_Y + connect \$75 $eq$libresoc.v:150991$7516_Y + connect \$77 $eq$libresoc.v:150992$7517_Y + connect \$79 $eq$libresoc.v:150993$7518_Y + connect \$81 $eq$libresoc.v:150994$7519_Y + connect \$83 $eq$libresoc.v:150995$7520_Y + connect \$85 $eq$libresoc.v:150996$7521_Y + connect \$87 $eq$libresoc.v:150997$7522_Y + connect \$89 $eq$libresoc.v:150998$7523_Y + connect \$91 $eq$libresoc.v:150999$7524_Y + connect \$93 $eq$libresoc.v:151000$7525_Y + connect \$95 $eq$libresoc.v:151001$7526_Y + connect \$97 $eq$libresoc.v:151002$7527_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$20 \xer_so end -attribute \src "libresoc.v:150792.1-151307.10" +attribute \src "libresoc.v:151448.1-152051.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" attribute \generator "nMigen" module \main$9 - attribute \src "libresoc.v:151162.3-151172.6" + attribute \src "libresoc.v:151838.3-151864.6" wire width 2 $0\BC[1:0] - attribute \src "libresoc.v:151216.3-151226.6" + attribute \src "libresoc.v:151932.3-151946.6" wire width 2 $0\ba[1:0] - attribute \src "libresoc.v:151227.3-151237.6" + attribute \src "libresoc.v:151947.3-151961.6" wire width 2 $0\bb[1:0] - attribute \src "libresoc.v:151238.3-151258.6" + attribute \src "libresoc.v:151962.3-151986.6" wire $0\bit_a[0:0] - attribute \src "libresoc.v:151259.3-151279.6" + attribute \src "libresoc.v:151987.3-152011.6" wire $0\bit_b[0:0] - attribute \src "libresoc.v:151280.3-151290.6" + attribute \src "libresoc.v:152012.3-152026.6" wire $0\bit_o[0:0] - attribute \src "libresoc.v:151205.3-151215.6" + attribute \src "libresoc.v:151917.3-151931.6" wire width 2 $0\bt[1:0] - attribute \src "libresoc.v:151074.3-151108.6" - wire width 4 $0\cr_a$6[3:0]$7623 - attribute \src "libresoc.v:151074.3-151108.6" + attribute \src "libresoc.v:151730.3-151764.6" + wire width 4 $0\cr_a$6[3:0]$7555 + attribute \src "libresoc.v:151730.3-151764.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:151173.3-151193.6" + attribute \src "libresoc.v:151865.3-151901.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:151291.3-151301.6" - wire width 32 $0\full_cr$5[31:0]$7638 - attribute \src "libresoc.v:151109.3-151119.6" + attribute \src "libresoc.v:152027.3-152045.6" + wire width 32 $0\full_cr$5[31:0]$7570 + attribute \src "libresoc.v:151765.3-151783.6" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:150793.7-150793.20" + attribute \src "libresoc.v:151449.7-151449.20" wire $0\initial[0:0] - attribute \src "libresoc.v:151194.3-151204.6" + attribute \src "libresoc.v:151902.3-151916.6" wire width 4 $0\lut[3:0] - attribute \src "libresoc.v:151120.3-151161.6" + attribute \src "libresoc.v:151784.3-151837.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:151120.3-151161.6" + attribute \src "libresoc.v:151784.3-151837.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:151162.3-151172.6" + attribute \src "libresoc.v:151838.3-151864.6" wire width 2 $1\BC[1:0] - attribute \src "libresoc.v:151216.3-151226.6" + attribute \src "libresoc.v:151932.3-151946.6" wire width 2 $1\ba[1:0] - attribute \src "libresoc.v:151227.3-151237.6" + attribute \src "libresoc.v:151947.3-151961.6" wire width 2 $1\bb[1:0] - attribute \src "libresoc.v:151238.3-151258.6" + attribute \src "libresoc.v:151962.3-151986.6" wire $1\bit_a[0:0] - attribute \src "libresoc.v:151259.3-151279.6" + attribute \src "libresoc.v:151987.3-152011.6" wire $1\bit_b[0:0] - attribute \src "libresoc.v:151280.3-151290.6" + attribute \src "libresoc.v:152012.3-152026.6" wire $1\bit_o[0:0] - attribute \src "libresoc.v:151205.3-151215.6" + attribute \src "libresoc.v:151917.3-151931.6" wire width 2 $1\bt[1:0] - attribute \src "libresoc.v:151074.3-151108.6" - wire width 4 $1\cr_a$6[3:0]$7624 - attribute \src "libresoc.v:151074.3-151108.6" + attribute \src "libresoc.v:151730.3-151764.6" + wire width 4 $1\cr_a$6[3:0]$7556 + attribute \src "libresoc.v:151730.3-151764.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:151173.3-151193.6" + attribute \src "libresoc.v:151865.3-151901.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:151291.3-151301.6" - wire width 32 $1\full_cr$5[31:0]$7639 - attribute \src "libresoc.v:151109.3-151119.6" + attribute \src "libresoc.v:152027.3-152045.6" + wire width 32 $1\full_cr$5[31:0]$7571 + attribute \src "libresoc.v:151765.3-151783.6" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:151194.3-151204.6" + attribute \src "libresoc.v:151902.3-151916.6" wire width 4 $1\lut[3:0] - attribute \src "libresoc.v:151120.3-151161.6" + attribute \src "libresoc.v:151784.3-151837.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:151120.3-151161.6" + attribute \src "libresoc.v:151784.3-151837.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:151238.3-151258.6" + attribute \src "libresoc.v:151962.3-151986.6" wire $2\bit_a[0:0] - attribute \src "libresoc.v:151259.3-151279.6" + attribute \src "libresoc.v:151987.3-152011.6" wire $2\bit_b[0:0] - attribute \src "libresoc.v:151074.3-151108.6" - wire width 4 $2\cr_a$6[3:0]$7625 - attribute \src "libresoc.v:151173.3-151193.6" + attribute \src "libresoc.v:151730.3-151764.6" + wire width 4 $2\cr_a$6[3:0]$7557 + attribute \src "libresoc.v:151865.3-151901.6" wire $2\cr_bit[0:0] - attribute \src "libresoc.v:151120.3-151161.6" + attribute \src "libresoc.v:151784.3-151837.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:151070.18-151070.96" - wire width 64 $extend$libresoc.v:151070$7615_Y - attribute \src "libresoc.v:151072.18-151072.98" - wire width 65 $extend$libresoc.v:151072$7618_Y - attribute \src "libresoc.v:151073.17-151073.92" - wire width 5 $extend$libresoc.v:151073$7620_Y - attribute \src "libresoc.v:151070.18-151070.96" - wire width 64 $pos$libresoc.v:151070$7616_Y - attribute \src "libresoc.v:151072.18-151072.98" - wire width 65 $pos$libresoc.v:151072$7619_Y - attribute \src "libresoc.v:151073.17-151073.92" - wire width 5 $pos$libresoc.v:151073$7621_Y - attribute \src "libresoc.v:151064.18-151064.116" - wire width 3 $sub$libresoc.v:151064$7609_Y - attribute \src "libresoc.v:151065.18-151065.116" - wire width 3 $sub$libresoc.v:151065$7610_Y - attribute \src "libresoc.v:151066.18-151066.116" - wire width 3 $sub$libresoc.v:151066$7611_Y - attribute \src "libresoc.v:151067.18-151067.114" - wire $ternary$libresoc.v:151067$7612_Y - attribute \src "libresoc.v:151068.18-151068.115" - wire $ternary$libresoc.v:151068$7613_Y - attribute \src "libresoc.v:151069.18-151069.112" - wire $ternary$libresoc.v:151069$7614_Y - attribute \src "libresoc.v:151071.18-151071.108" - wire width 64 $ternary$libresoc.v:151071$7617_Y + attribute \src "libresoc.v:151726.18-151726.96" + wire width 64 $extend$libresoc.v:151726$7547_Y + attribute \src "libresoc.v:151728.18-151728.98" + wire width 65 $extend$libresoc.v:151728$7550_Y + attribute \src "libresoc.v:151729.17-151729.92" + wire width 5 $extend$libresoc.v:151729$7552_Y + attribute \src "libresoc.v:151726.18-151726.96" + wire width 64 $pos$libresoc.v:151726$7548_Y + attribute \src "libresoc.v:151728.18-151728.98" + wire width 65 $pos$libresoc.v:151728$7551_Y + attribute \src "libresoc.v:151729.17-151729.92" + wire width 5 $pos$libresoc.v:151729$7553_Y + attribute \src "libresoc.v:151720.18-151720.116" + wire width 3 $sub$libresoc.v:151720$7541_Y + attribute \src "libresoc.v:151721.18-151721.116" + wire width 3 $sub$libresoc.v:151721$7542_Y + attribute \src "libresoc.v:151722.18-151722.116" + wire width 3 $sub$libresoc.v:151722$7543_Y + attribute \src "libresoc.v:151723.18-151723.114" + wire $ternary$libresoc.v:151723$7544_Y + attribute \src "libresoc.v:151724.18-151724.115" + wire $ternary$libresoc.v:151724$7545_Y + attribute \src "libresoc.v:151725.18-151725.112" + wire $ternary$libresoc.v:151725$7546_Y + attribute \src "libresoc.v:151727.18-151727.108" + wire width 64 $ternary$libresoc.v:151727$7549_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" wire width 3 \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" @@ -315266,9 +281722,9 @@ module \main$9 wire width 2 \bt attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 7 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 18 \cr_a$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 19 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 8 \cr_b @@ -315470,11 +281926,11 @@ module \main$9 wire width 7 output 11 \cr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 input 6 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 output 16 \full_cr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 17 \full_cr_ok - attribute \src "libresoc.v:150793.7-150793.15" + attribute \src "libresoc.v:151449.7-151449.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" wire width 4 \lut @@ -315482,64 +281938,64 @@ module \main$9 wire width 2 input 20 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 10 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 14 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 15 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 4 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 5 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151070$7615 + cell $pos $extend$libresoc.v:151726$7547 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \full_cr - connect \Y $extend$libresoc.v:151070$7615_Y + connect \Y $extend$libresoc.v:151726$7547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $extend$libresoc.v:151072$7618 + cell $pos $extend$libresoc.v:151728$7550 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$27 - connect \Y $extend$libresoc.v:151072$7618_Y + connect \Y $extend$libresoc.v:151728$7550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151073$7620 + cell $pos $extend$libresoc.v:151729$7552 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 5 connect \A \cr_a - connect \Y $extend$libresoc.v:151073$7620_Y + connect \Y $extend$libresoc.v:151729$7552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151070$7616 + cell $pos $pos$libresoc.v:151726$7548 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:151070$7615_Y - connect \Y $pos$libresoc.v:151070$7616_Y + connect \A $extend$libresoc.v:151726$7547_Y + connect \Y $pos$libresoc.v:151726$7548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $pos$libresoc.v:151072$7619 + cell $pos $pos$libresoc.v:151728$7551 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:151072$7618_Y - connect \Y $pos$libresoc.v:151072$7619_Y + connect \A $extend$libresoc.v:151728$7550_Y + connect \Y $pos$libresoc.v:151728$7551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151073$7621 + cell $pos $pos$libresoc.v:151729$7553 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $extend$libresoc.v:151073$7620_Y - connect \Y $pos$libresoc.v:151073$7621_Y + connect \A $extend$libresoc.v:151729$7552_Y + connect \Y $pos$libresoc.v:151729$7553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - cell $sub $sub$libresoc.v:151064$7609 + cell $sub $sub$libresoc.v:151720$7541 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -315547,10 +282003,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [22:21] - connect \Y $sub$libresoc.v:151064$7609_Y + connect \Y $sub$libresoc.v:151720$7541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - cell $sub $sub$libresoc.v:151065$7610 + cell $sub $sub$libresoc.v:151721$7542 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -315558,10 +282014,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [17:16] - connect \Y $sub$libresoc.v:151065$7610_Y + connect \Y $sub$libresoc.v:151721$7542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - cell $sub $sub$libresoc.v:151066$7611 + cell $sub $sub$libresoc.v:151722$7543 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -315569,59 +282025,59 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [12:11] - connect \Y $sub$libresoc.v:151066$7611_Y + connect \Y $sub$libresoc.v:151722$7543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" - cell $mux $ternary$libresoc.v:151067$7612 + cell $mux $ternary$libresoc.v:151723$7544 parameter \WIDTH 1 connect \A \lut [1] connect \B \lut [3] connect \S \bit_a - connect \Y $ternary$libresoc.v:151067$7612_Y + connect \Y $ternary$libresoc.v:151723$7544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:151068$7613 + cell $mux $ternary$libresoc.v:151724$7545 parameter \WIDTH 1 connect \A \lut [0] connect \B \lut [2] connect \S \bit_a - connect \Y $ternary$libresoc.v:151068$7613_Y + connect \Y $ternary$libresoc.v:151724$7545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:151069$7614 + cell $mux $ternary$libresoc.v:151725$7546 parameter \WIDTH 1 connect \A \$20 connect \B \$18 connect \S \bit_b - connect \Y $ternary$libresoc.v:151069$7614_Y + connect \Y $ternary$libresoc.v:151725$7546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $mux $ternary$libresoc.v:151071$7617 + cell $mux $ternary$libresoc.v:151727$7549 parameter \WIDTH 64 connect \A \rb connect \B \ra connect \S \cr_bit - connect \Y $ternary$libresoc.v:151071$7617_Y + connect \Y $ternary$libresoc.v:151727$7549_Y end - attribute \src "libresoc.v:150793.7-150793.20" - process $proc$libresoc.v:150793$7640 + attribute \src "libresoc.v:151449.7-151449.20" + process $proc$libresoc.v:151449$7572 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:151074.3-151108.6" - process $proc$libresoc.v:151074$7622 + attribute \src "libresoc.v:151730.3-151764.6" + process $proc$libresoc.v:151730$7554 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - assign $0\cr_a$6[3:0]$7623 $1\cr_a$6[3:0]$7624 - attribute \src "libresoc.v:151075.5-151075.29" + assign $0\cr_a$6[3:0]$7555 $1\cr_a$6[3:0]$7556 + attribute \src "libresoc.v:151731.5-151731.29" switch \initial - attribute \src "libresoc.v:151075.9-151075.17" + attribute \src "libresoc.v:151731.9-151731.17" case 1'1 case end @@ -315631,58 +282087,64 @@ module \main$9 case 7'0101010 assign { } { } assign { } { } - assign $1\cr_a$6[3:0]$7624 \$7 [3:0] + assign $1\cr_a$6[3:0]$7556 \$7 [3:0] assign $1\cr_a_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign { } { } assign { } { } - assign $1\cr_a$6[3:0]$7624 $2\cr_a$6[3:0]$7625 + assign $1\cr_a$6[3:0]$7556 $2\cr_a$6[3:0]$7557 assign $1\cr_a_ok[0:0] 1'1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" switch \bt attribute \src "libresoc.v:0.0-0.0" case 2'00 - assign $2\cr_a$6[3:0]$7625 [3:1] \cr_c [3:1] - assign $2\cr_a$6[3:0]$7625 [0] \bit_o + assign $2\cr_a$6[3:0]$7557 [3:1] \cr_c [3:1] + assign $2\cr_a$6[3:0]$7557 [0] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'01 - assign { $2\cr_a$6[3:0]$7625 [3:2] $2\cr_a$6[3:0]$7625 [0] } { \cr_c [3:2] \cr_c [0] } - assign $2\cr_a$6[3:0]$7625 [1] \bit_o + assign { $2\cr_a$6[3:0]$7557 [3:2] $2\cr_a$6[3:0]$7557 [0] } { \cr_c [3:2] \cr_c [0] } + assign $2\cr_a$6[3:0]$7557 [1] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'10 - assign { $2\cr_a$6[3:0]$7625 [3] $2\cr_a$6[3:0]$7625 [1:0] } { \cr_c [3] \cr_c [1:0] } - assign $2\cr_a$6[3:0]$7625 [2] \bit_o + assign { $2\cr_a$6[3:0]$7557 [3] $2\cr_a$6[3:0]$7557 [1:0] } { \cr_c [3] \cr_c [1:0] } + assign $2\cr_a$6[3:0]$7557 [2] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'-- - assign $2\cr_a$6[3:0]$7625 [2:0] \cr_c [2:0] - assign $2\cr_a$6[3:0]$7625 [3] \bit_o + assign $2\cr_a$6[3:0]$7557 [2:0] \cr_c [2:0] + assign $2\cr_a$6[3:0]$7557 [3] \bit_o case - assign $2\cr_a$6[3:0]$7625 \cr_c + assign $2\cr_a$6[3:0]$7557 \cr_c end case assign $1\cr_a_ok[0:0] 1'0 - assign $1\cr_a$6[3:0]$7624 4'0000 + assign $1\cr_a$6[3:0]$7556 4'0000 end sync always update \cr_a_ok $0\cr_a_ok[0:0] - update \cr_a$6 $0\cr_a$6[3:0]$7623 + update \cr_a$6 $0\cr_a$6[3:0]$7555 end - attribute \src "libresoc.v:151109.3-151119.6" - process $proc$libresoc.v:151109$7626 + attribute \src "libresoc.v:151765.3-151783.6" + process $proc$libresoc.v:151765$7558 assign { } { } assign { } { } assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] - attribute \src "libresoc.v:151110.5-151110.29" + attribute \src "libresoc.v:151766.5-151766.29" switch \initial - attribute \src "libresoc.v:151110.9-151110.17" + attribute \src "libresoc.v:151766.9-151766.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\full_cr_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign $1\full_cr_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0110000 assign { } { } assign $1\full_cr_ok[0:0] 1'1 @@ -315692,23 +282154,35 @@ module \main$9 sync always update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:151120.3-151161.6" - process $proc$libresoc.v:151120$7627 + attribute \src "libresoc.v:151784.3-151837.6" + process $proc$libresoc.v:151784$7559 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:151121.5-151121.29" + attribute \src "libresoc.v:151785.5-151785.29" switch \initial - attribute \src "libresoc.v:151121.9-151121.17" + attribute \src "libresoc.v:151785.9-151785.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0101101 assign { } { } assign { } { } @@ -315749,20 +282223,32 @@ module \main$9 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:151162.3-151172.6" - process $proc$libresoc.v:151162$7628 + attribute \src "libresoc.v:151838.3-151864.6" + process $proc$libresoc.v:151838$7560 assign { } { } assign { } { } assign $0\BC[1:0] $1\BC[1:0] - attribute \src "libresoc.v:151163.5-151163.29" + attribute \src "libresoc.v:151839.5-151839.29" switch \initial - attribute \src "libresoc.v:151163.9-151163.17" + attribute \src "libresoc.v:151839.9-151839.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\BC[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign $1\BC[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign $1\BC[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0101101 + assign $1\BC[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'0100011 assign { } { } assign $1\BC[1:0] \cr_op__insn [7:6] @@ -315772,20 +282258,32 @@ module \main$9 sync always update \BC $0\BC[1:0] end - attribute \src "libresoc.v:151173.3-151193.6" - process $proc$libresoc.v:151173$7629 + attribute \src "libresoc.v:151865.3-151901.6" + process $proc$libresoc.v:151865$7561 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:151174.5-151174.29" + attribute \src "libresoc.v:151866.5-151866.29" switch \initial - attribute \src "libresoc.v:151174.9-151174.17" + attribute \src "libresoc.v:151866.9-151866.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\cr_bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign $1\cr_bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign $1\cr_bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0101101 + assign $1\cr_bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0100011 assign { } { } assign $1\cr_bit[0:0] $2\cr_bit[0:0] @@ -315816,20 +282314,23 @@ module \main$9 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:151194.3-151204.6" - process $proc$libresoc.v:151194$7630 + attribute \src "libresoc.v:151902.3-151916.6" + process $proc$libresoc.v:151902$7562 assign { } { } assign { } { } assign $0\lut[3:0] $1\lut[3:0] - attribute \src "libresoc.v:151195.5-151195.29" + attribute \src "libresoc.v:151903.5-151903.29" switch \initial - attribute \src "libresoc.v:151195.9-151195.17" + attribute \src "libresoc.v:151903.9-151903.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\lut[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\lut[3:0] \cr_op__insn [9:6] @@ -315839,20 +282340,23 @@ module \main$9 sync always update \lut $0\lut[3:0] end - attribute \src "libresoc.v:151205.3-151215.6" - process $proc$libresoc.v:151205$7631 + attribute \src "libresoc.v:151917.3-151931.6" + process $proc$libresoc.v:151917$7563 assign { } { } assign { } { } assign $0\bt[1:0] $1\bt[1:0] - attribute \src "libresoc.v:151206.5-151206.29" + attribute \src "libresoc.v:151918.5-151918.29" switch \initial - attribute \src "libresoc.v:151206.9-151206.17" + attribute \src "libresoc.v:151918.9-151918.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\bt[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bt[1:0] \$9 [1:0] @@ -315862,20 +282366,23 @@ module \main$9 sync always update \bt $0\bt[1:0] end - attribute \src "libresoc.v:151216.3-151226.6" - process $proc$libresoc.v:151216$7632 + attribute \src "libresoc.v:151932.3-151946.6" + process $proc$libresoc.v:151932$7564 assign { } { } assign { } { } assign $0\ba[1:0] $1\ba[1:0] - attribute \src "libresoc.v:151217.5-151217.29" + attribute \src "libresoc.v:151933.5-151933.29" switch \initial - attribute \src "libresoc.v:151217.9-151217.17" + attribute \src "libresoc.v:151933.9-151933.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\ba[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\ba[1:0] \$12 [1:0] @@ -315885,20 +282392,23 @@ module \main$9 sync always update \ba $0\ba[1:0] end - attribute \src "libresoc.v:151227.3-151237.6" - process $proc$libresoc.v:151227$7633 + attribute \src "libresoc.v:151947.3-151961.6" + process $proc$libresoc.v:151947$7565 assign { } { } assign { } { } assign $0\bb[1:0] $1\bb[1:0] - attribute \src "libresoc.v:151228.5-151228.29" + attribute \src "libresoc.v:151948.5-151948.29" switch \initial - attribute \src "libresoc.v:151228.9-151228.17" + attribute \src "libresoc.v:151948.9-151948.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\bb[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bb[1:0] \$15 [1:0] @@ -315908,20 +282418,23 @@ module \main$9 sync always update \bb $0\bb[1:0] end - attribute \src "libresoc.v:151238.3-151258.6" - process $proc$libresoc.v:151238$7634 + attribute \src "libresoc.v:151962.3-151986.6" + process $proc$libresoc.v:151962$7566 assign { } { } assign { } { } assign $0\bit_a[0:0] $1\bit_a[0:0] - attribute \src "libresoc.v:151239.5-151239.29" + attribute \src "libresoc.v:151963.5-151963.29" switch \initial - attribute \src "libresoc.v:151239.9-151239.17" + attribute \src "libresoc.v:151963.9-151963.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\bit_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bit_a[0:0] $2\bit_a[0:0] @@ -315952,20 +282465,23 @@ module \main$9 sync always update \bit_a $0\bit_a[0:0] end - attribute \src "libresoc.v:151259.3-151279.6" - process $proc$libresoc.v:151259$7635 + attribute \src "libresoc.v:151987.3-152011.6" + process $proc$libresoc.v:151987$7567 assign { } { } assign { } { } assign $0\bit_b[0:0] $1\bit_b[0:0] - attribute \src "libresoc.v:151260.5-151260.29" + attribute \src "libresoc.v:151988.5-151988.29" switch \initial - attribute \src "libresoc.v:151260.9-151260.17" + attribute \src "libresoc.v:151988.9-151988.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\bit_b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bit_b[0:0] $2\bit_b[0:0] @@ -315996,20 +282512,23 @@ module \main$9 sync always update \bit_b $0\bit_b[0:0] end - attribute \src "libresoc.v:151280.3-151290.6" - process $proc$libresoc.v:151280$7636 + attribute \src "libresoc.v:152012.3-152026.6" + process $proc$libresoc.v:152012$7568 assign { } { } assign { } { } assign $0\bit_o[0:0] $1\bit_o[0:0] - attribute \src "libresoc.v:151281.5-151281.29" + attribute \src "libresoc.v:152013.5-152013.29" switch \initial - attribute \src "libresoc.v:151281.9-151281.17" + attribute \src "libresoc.v:152013.9-152013.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\bit_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bit_o[0:0] \$22 @@ -316019,524 +282538,530 @@ module \main$9 sync always update \bit_o $0\bit_o[0:0] end - attribute \src "libresoc.v:151291.3-151301.6" - process $proc$libresoc.v:151291$7637 + attribute \src "libresoc.v:152027.3-152045.6" + process $proc$libresoc.v:152027$7569 assign { } { } assign { } { } - assign $0\full_cr$5[31:0]$7638 $1\full_cr$5[31:0]$7639 - attribute \src "libresoc.v:151292.5-151292.29" + assign $0\full_cr$5[31:0]$7570 $1\full_cr$5[31:0]$7571 + attribute \src "libresoc.v:152028.5-152028.29" switch \initial - attribute \src "libresoc.v:151292.9-151292.17" + attribute \src "libresoc.v:152028.9-152028.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\full_cr$5[31:0]$7571 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign $1\full_cr$5[31:0]$7571 0 + attribute \src "libresoc.v:0.0-0.0" case 7'0110000 assign { } { } - assign $1\full_cr$5[31:0]$7639 \ra [31:0] + assign $1\full_cr$5[31:0]$7571 \ra [31:0] case - assign $1\full_cr$5[31:0]$7639 0 + assign $1\full_cr$5[31:0]$7571 0 end sync always - update \full_cr$5 $0\full_cr$5[31:0]$7638 + update \full_cr$5 $0\full_cr$5[31:0]$7570 end - connect \$10 $sub$libresoc.v:151064$7609_Y - connect \$13 $sub$libresoc.v:151065$7610_Y - connect \$16 $sub$libresoc.v:151066$7611_Y - connect \$18 $ternary$libresoc.v:151067$7612_Y - connect \$20 $ternary$libresoc.v:151068$7613_Y - connect \$22 $ternary$libresoc.v:151069$7614_Y - connect \$24 $pos$libresoc.v:151070$7616_Y - connect \$27 $ternary$libresoc.v:151071$7617_Y - connect \$26 $pos$libresoc.v:151072$7619_Y - connect \$7 $pos$libresoc.v:151073$7621_Y + connect \$10 $sub$libresoc.v:151720$7541_Y + connect \$13 $sub$libresoc.v:151721$7542_Y + connect \$16 $sub$libresoc.v:151722$7543_Y + connect \$18 $ternary$libresoc.v:151723$7544_Y + connect \$20 $ternary$libresoc.v:151724$7545_Y + connect \$22 $ternary$libresoc.v:151725$7546_Y + connect \$24 $pos$libresoc.v:151726$7548_Y + connect \$27 $ternary$libresoc.v:151727$7549_Y + connect \$26 $pos$libresoc.v:151728$7551_Y + connect \$7 $pos$libresoc.v:151729$7553_Y connect \$9 \$10 connect \$12 \$13 connect \$15 \$16 connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:151311.1-152472.10" +attribute \src "libresoc.v:152055.1-153216.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" attribute \generator "nMigen" module \mul0 - attribute \src "libresoc.v:152043.3-152044.25" + attribute \src "libresoc.v:152787.3-152788.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:152041.3-152042.40" + attribute \src "libresoc.v:152785.3-152786.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:152384.3-152392.6" - wire $0\alu_l_r_alu$next[0:0]$7846 - attribute \src "libresoc.v:151969.3-151970.39" + attribute \src "libresoc.v:153128.3-153136.6" + wire $0\alu_l_r_alu$next[0:0]$7778 + attribute \src "libresoc.v:152713.3-152714.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 - attribute \src "libresoc.v:151997.3-151998.65" + attribute \src "libresoc.v:152968.3-153000.6" + wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7703 + attribute \src "libresoc.v:152741.3-152742.65" wire width 14 $0\alu_mul0_mul_op__fn_unit[13:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 - attribute \src "libresoc.v:151999.3-152000.79" + attribute \src "libresoc.v:152968.3-153000.6" + wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7704 + attribute \src "libresoc.v:152743.3-152744.79" wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 - attribute \src "libresoc.v:152001.3-152002.75" + attribute \src "libresoc.v:152968.3-153000.6" + wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7705 + attribute \src "libresoc.v:152745.3-152746.75" wire $0\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7774 - attribute \src "libresoc.v:152017.3-152018.59" + attribute \src "libresoc.v:152968.3-153000.6" + wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7706 + attribute \src "libresoc.v:152761.3-152762.59" wire width 32 $0\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 - attribute \src "libresoc.v:151995.3-151996.69" + attribute \src "libresoc.v:152968.3-153000.6" + wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7707 + attribute \src "libresoc.v:152739.3-152740.69" wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 - attribute \src "libresoc.v:152013.3-152014.67" + attribute \src "libresoc.v:152968.3-153000.6" + wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7708 + attribute \src "libresoc.v:152757.3-152758.67" wire $0\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 - attribute \src "libresoc.v:152015.3-152016.69" + attribute \src "libresoc.v:152968.3-153000.6" + wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7709 + attribute \src "libresoc.v:152759.3-152760.69" wire $0\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 - attribute \src "libresoc.v:152007.3-152008.63" + attribute \src "libresoc.v:152968.3-153000.6" + wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7710 + attribute \src "libresoc.v:152751.3-152752.63" wire $0\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 - attribute \src "libresoc.v:152009.3-152010.63" + attribute \src "libresoc.v:152968.3-153000.6" + wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7711 + attribute \src "libresoc.v:152753.3-152754.63" wire $0\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 - attribute \src "libresoc.v:152005.3-152006.63" + attribute \src "libresoc.v:152968.3-153000.6" + wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7712 + attribute \src "libresoc.v:152749.3-152750.63" wire $0\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 - attribute \src "libresoc.v:152003.3-152004.63" + attribute \src "libresoc.v:152968.3-153000.6" + wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7713 + attribute \src "libresoc.v:152747.3-152748.63" wire $0\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 - attribute \src "libresoc.v:152011.3-152012.69" + attribute \src "libresoc.v:152968.3-153000.6" + wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7714 + attribute \src "libresoc.v:152755.3-152756.69" wire $0\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:152375.3-152383.6" - wire $0\alui_l_r_alui$next[0:0]$7843 - attribute \src "libresoc.v:151971.3-151972.43" + attribute \src "libresoc.v:153119.3-153127.6" + wire $0\alui_l_r_alui$next[0:0]$7775 + attribute \src "libresoc.v:152715.3-152716.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:152257.3-152278.6" - wire width 64 $0\data_r0__o$next[63:0]$7802 - attribute \src "libresoc.v:151991.3-151992.37" + attribute \src "libresoc.v:153001.3-153022.6" + wire width 64 $0\data_r0__o$next[63:0]$7734 + attribute \src "libresoc.v:152735.3-152736.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:152257.3-152278.6" - wire $0\data_r0__o_ok$next[0:0]$7803 - attribute \src "libresoc.v:151993.3-151994.43" + attribute \src "libresoc.v:153001.3-153022.6" + wire $0\data_r0__o_ok$next[0:0]$7735 + attribute \src "libresoc.v:152737.3-152738.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:152279.3-152300.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$7810 - attribute \src "libresoc.v:151987.3-151988.43" + attribute \src "libresoc.v:153023.3-153044.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$7742 + attribute \src "libresoc.v:152731.3-152732.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:152279.3-152300.6" - wire $0\data_r1__cr_a_ok$next[0:0]$7811 - attribute \src "libresoc.v:151989.3-151990.49" + attribute \src "libresoc.v:153023.3-153044.6" + wire $0\data_r1__cr_a_ok$next[0:0]$7743 + attribute \src "libresoc.v:152733.3-152734.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:152301.3-152322.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$7818 - attribute \src "libresoc.v:151983.3-151984.47" + attribute \src "libresoc.v:153045.3-153066.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$7750 + attribute \src "libresoc.v:152727.3-152728.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:152301.3-152322.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$7819 - attribute \src "libresoc.v:151985.3-151986.53" + attribute \src "libresoc.v:153045.3-153066.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$7751 + attribute \src "libresoc.v:152729.3-152730.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:152323.3-152344.6" - wire $0\data_r3__xer_so$next[0:0]$7826 - attribute \src "libresoc.v:151979.3-151980.47" + attribute \src "libresoc.v:153067.3-153088.6" + wire $0\data_r3__xer_so$next[0:0]$7758 + attribute \src "libresoc.v:152723.3-152724.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:152323.3-152344.6" - wire $0\data_r3__xer_so_ok$next[0:0]$7827 - attribute \src "libresoc.v:151981.3-151982.53" + attribute \src "libresoc.v:153067.3-153088.6" + wire $0\data_r3__xer_so_ok$next[0:0]$7759 + attribute \src "libresoc.v:152725.3-152726.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:152393.3-152402.6" + attribute \src "libresoc.v:153137.3-153146.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:152403.3-152412.6" + attribute \src "libresoc.v:153147.3-153156.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:152413.3-152422.6" + attribute \src "libresoc.v:153157.3-153166.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:152423.3-152432.6" + attribute \src "libresoc.v:153167.3-153176.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:151312.7-151312.20" + attribute \src "libresoc.v:152056.7-152056.20" wire $0\initial[0:0] - attribute \src "libresoc.v:152179.3-152187.6" - wire $0\opc_l_r_opc$next[0:0]$7756 - attribute \src "libresoc.v:152027.3-152028.39" + attribute \src "libresoc.v:152923.3-152931.6" + wire $0\opc_l_r_opc$next[0:0]$7688 + attribute \src "libresoc.v:152771.3-152772.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:152170.3-152178.6" - wire $0\opc_l_s_opc$next[0:0]$7753 - attribute \src "libresoc.v:152029.3-152030.39" + attribute \src "libresoc.v:152914.3-152922.6" + wire $0\opc_l_s_opc$next[0:0]$7685 + attribute \src "libresoc.v:152773.3-152774.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:152433.3-152441.6" - wire width 4 $0\prev_wr_go$next[3:0]$7853 - attribute \src "libresoc.v:152039.3-152040.37" + attribute \src "libresoc.v:153177.3-153185.6" + wire width 4 $0\prev_wr_go$next[3:0]$7785 + attribute \src "libresoc.v:152783.3-152784.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:152124.3-152133.6" + attribute \src "libresoc.v:152868.3-152877.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:152215.3-152223.6" - wire width 4 $0\req_l_r_req$next[3:0]$7768 - attribute \src "libresoc.v:152019.3-152020.39" + attribute \src "libresoc.v:152959.3-152967.6" + wire width 4 $0\req_l_r_req$next[3:0]$7700 + attribute \src "libresoc.v:152763.3-152764.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:152206.3-152214.6" - wire width 4 $0\req_l_s_req$next[3:0]$7765 - attribute \src "libresoc.v:152021.3-152022.39" + attribute \src "libresoc.v:152950.3-152958.6" + wire width 4 $0\req_l_s_req$next[3:0]$7697 + attribute \src "libresoc.v:152765.3-152766.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:152143.3-152151.6" - wire $0\rok_l_r_rdok$next[0:0]$7744 - attribute \src "libresoc.v:152035.3-152036.41" + attribute \src "libresoc.v:152887.3-152895.6" + wire $0\rok_l_r_rdok$next[0:0]$7676 + attribute \src "libresoc.v:152779.3-152780.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:152134.3-152142.6" - wire $0\rok_l_s_rdok$next[0:0]$7741 - attribute \src "libresoc.v:152037.3-152038.41" + attribute \src "libresoc.v:152878.3-152886.6" + wire $0\rok_l_s_rdok$next[0:0]$7673 + attribute \src "libresoc.v:152781.3-152782.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:152161.3-152169.6" - wire $0\rst_l_r_rst$next[0:0]$7750 - attribute \src "libresoc.v:152031.3-152032.39" + attribute \src "libresoc.v:152905.3-152913.6" + wire $0\rst_l_r_rst$next[0:0]$7682 + attribute \src "libresoc.v:152775.3-152776.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:152152.3-152160.6" - wire $0\rst_l_s_rst$next[0:0]$7747 - attribute \src "libresoc.v:152033.3-152034.39" + attribute \src "libresoc.v:152896.3-152904.6" + wire $0\rst_l_s_rst$next[0:0]$7679 + attribute \src "libresoc.v:152777.3-152778.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:152197.3-152205.6" - wire width 3 $0\src_l_r_src$next[2:0]$7762 - attribute \src "libresoc.v:152023.3-152024.39" + attribute \src "libresoc.v:152941.3-152949.6" + wire width 3 $0\src_l_r_src$next[2:0]$7694 + attribute \src "libresoc.v:152767.3-152768.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:152188.3-152196.6" - wire width 3 $0\src_l_s_src$next[2:0]$7759 - attribute \src "libresoc.v:152025.3-152026.39" + attribute \src "libresoc.v:152932.3-152940.6" + wire width 3 $0\src_l_s_src$next[2:0]$7691 + attribute \src "libresoc.v:152769.3-152770.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:152345.3-152354.6" - wire width 64 $0\src_r0$next[63:0]$7834 - attribute \src "libresoc.v:151977.3-151978.29" + attribute \src "libresoc.v:153089.3-153098.6" + wire width 64 $0\src_r0$next[63:0]$7766 + attribute \src "libresoc.v:152721.3-152722.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:152355.3-152364.6" - wire width 64 $0\src_r1$next[63:0]$7837 - attribute \src "libresoc.v:151975.3-151976.29" + attribute \src "libresoc.v:153099.3-153108.6" + wire width 64 $0\src_r1$next[63:0]$7769 + attribute \src "libresoc.v:152719.3-152720.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:152365.3-152374.6" - wire $0\src_r2$next[0:0]$7840 - attribute \src "libresoc.v:151973.3-151974.29" + attribute \src "libresoc.v:153109.3-153118.6" + wire $0\src_r2$next[0:0]$7772 + attribute \src "libresoc.v:152717.3-152718.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:151436.7-151436.24" + attribute \src "libresoc.v:152180.7-152180.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:151446.7-151446.26" + attribute \src "libresoc.v:152190.7-152190.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:152384.3-152392.6" - wire $1\alu_l_r_alu$next[0:0]$7847 - attribute \src "libresoc.v:151454.7-151454.25" + attribute \src "libresoc.v:153128.3-153136.6" + wire $1\alu_l_r_alu$next[0:0]$7779 + attribute \src "libresoc.v:152198.7-152198.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 - attribute \src "libresoc.v:151477.14-151477.49" + attribute \src "libresoc.v:152968.3-153000.6" + wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7715 + attribute \src "libresoc.v:152221.14-152221.49" wire width 14 $1\alu_mul0_mul_op__fn_unit[13:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 - attribute \src "libresoc.v:151481.14-151481.68" + attribute \src "libresoc.v:152968.3-153000.6" + wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7716 + attribute \src "libresoc.v:152225.14-152225.68" wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 - attribute \src "libresoc.v:151485.7-151485.43" + attribute \src "libresoc.v:152968.3-153000.6" + wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7717 + attribute \src "libresoc.v:152229.7-152229.43" wire $1\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7786 - attribute \src "libresoc.v:151489.14-151489.43" + attribute \src "libresoc.v:152968.3-153000.6" + wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7718 + attribute \src "libresoc.v:152233.14-152233.43" wire width 32 $1\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 - attribute \src "libresoc.v:151568.13-151568.47" + attribute \src "libresoc.v:152968.3-153000.6" + wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7719 + attribute \src "libresoc.v:152312.13-152312.47" wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 - attribute \src "libresoc.v:151572.7-151572.39" + attribute \src "libresoc.v:152968.3-153000.6" + wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7720 + attribute \src "libresoc.v:152316.7-152316.39" wire $1\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 - attribute \src "libresoc.v:151576.7-151576.40" + attribute \src "libresoc.v:152968.3-153000.6" + wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7721 + attribute \src "libresoc.v:152320.7-152320.40" wire $1\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 - attribute \src "libresoc.v:151580.7-151580.37" + attribute \src "libresoc.v:152968.3-153000.6" + wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7722 + attribute \src "libresoc.v:152324.7-152324.37" wire $1\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 - attribute \src "libresoc.v:151584.7-151584.37" + attribute \src "libresoc.v:152968.3-153000.6" + wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7723 + attribute \src "libresoc.v:152328.7-152328.37" wire $1\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 - attribute \src "libresoc.v:151588.7-151588.37" + attribute \src "libresoc.v:152968.3-153000.6" + wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7724 + attribute \src "libresoc.v:152332.7-152332.37" wire $1\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 - attribute \src "libresoc.v:151592.7-151592.37" + attribute \src "libresoc.v:152968.3-153000.6" + wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7725 + attribute \src "libresoc.v:152336.7-152336.37" wire $1\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 - attribute \src "libresoc.v:151596.7-151596.40" + attribute \src "libresoc.v:152968.3-153000.6" + wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7726 + attribute \src "libresoc.v:152340.7-152340.40" wire $1\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:152375.3-152383.6" - wire $1\alui_l_r_alui$next[0:0]$7844 - attribute \src "libresoc.v:151626.7-151626.27" + attribute \src "libresoc.v:153119.3-153127.6" + wire $1\alui_l_r_alui$next[0:0]$7776 + attribute \src "libresoc.v:152370.7-152370.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:152257.3-152278.6" - wire width 64 $1\data_r0__o$next[63:0]$7804 - attribute \src "libresoc.v:151660.14-151660.47" + attribute \src "libresoc.v:153001.3-153022.6" + wire width 64 $1\data_r0__o$next[63:0]$7736 + attribute \src "libresoc.v:152404.14-152404.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:152257.3-152278.6" - wire $1\data_r0__o_ok$next[0:0]$7805 - attribute \src "libresoc.v:151664.7-151664.27" + attribute \src "libresoc.v:153001.3-153022.6" + wire $1\data_r0__o_ok$next[0:0]$7737 + attribute \src "libresoc.v:152408.7-152408.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:152279.3-152300.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$7812 - attribute \src "libresoc.v:151668.13-151668.33" + attribute \src "libresoc.v:153023.3-153044.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$7744 + attribute \src "libresoc.v:152412.13-152412.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:152279.3-152300.6" - wire $1\data_r1__cr_a_ok$next[0:0]$7813 - attribute \src "libresoc.v:151672.7-151672.30" + attribute \src "libresoc.v:153023.3-153044.6" + wire $1\data_r1__cr_a_ok$next[0:0]$7745 + attribute \src "libresoc.v:152416.7-152416.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:152301.3-152322.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$7820 - attribute \src "libresoc.v:151676.13-151676.35" + attribute \src "libresoc.v:153045.3-153066.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$7752 + attribute \src "libresoc.v:152420.13-152420.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:152301.3-152322.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$7821 - attribute \src "libresoc.v:151680.7-151680.32" + attribute \src "libresoc.v:153045.3-153066.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$7753 + attribute \src "libresoc.v:152424.7-152424.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:152323.3-152344.6" - wire $1\data_r3__xer_so$next[0:0]$7828 - attribute \src "libresoc.v:151684.7-151684.29" + attribute \src "libresoc.v:153067.3-153088.6" + wire $1\data_r3__xer_so$next[0:0]$7760 + attribute \src "libresoc.v:152428.7-152428.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:152323.3-152344.6" - wire $1\data_r3__xer_so_ok$next[0:0]$7829 - attribute \src "libresoc.v:151688.7-151688.32" + attribute \src "libresoc.v:153067.3-153088.6" + wire $1\data_r3__xer_so_ok$next[0:0]$7761 + attribute \src "libresoc.v:152432.7-152432.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:152393.3-152402.6" + attribute \src "libresoc.v:153137.3-153146.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:152403.3-152412.6" + attribute \src "libresoc.v:153147.3-153156.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:152413.3-152422.6" + attribute \src "libresoc.v:153157.3-153166.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:152423.3-152432.6" + attribute \src "libresoc.v:153167.3-153176.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:152179.3-152187.6" - wire $1\opc_l_r_opc$next[0:0]$7757 - attribute \src "libresoc.v:151708.7-151708.25" + attribute \src "libresoc.v:152923.3-152931.6" + wire $1\opc_l_r_opc$next[0:0]$7689 + attribute \src "libresoc.v:152452.7-152452.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:152170.3-152178.6" - wire $1\opc_l_s_opc$next[0:0]$7754 - attribute \src "libresoc.v:151712.7-151712.25" + attribute \src "libresoc.v:152914.3-152922.6" + wire $1\opc_l_s_opc$next[0:0]$7686 + attribute \src "libresoc.v:152456.7-152456.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:152433.3-152441.6" - wire width 4 $1\prev_wr_go$next[3:0]$7854 - attribute \src "libresoc.v:151830.13-151830.30" + attribute \src "libresoc.v:153177.3-153185.6" + wire width 4 $1\prev_wr_go$next[3:0]$7786 + attribute \src "libresoc.v:152574.13-152574.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:152124.3-152133.6" + attribute \src "libresoc.v:152868.3-152877.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:152215.3-152223.6" - wire width 4 $1\req_l_r_req$next[3:0]$7769 - attribute \src "libresoc.v:151838.13-151838.31" + attribute \src "libresoc.v:152959.3-152967.6" + wire width 4 $1\req_l_r_req$next[3:0]$7701 + attribute \src "libresoc.v:152582.13-152582.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:152206.3-152214.6" - wire width 4 $1\req_l_s_req$next[3:0]$7766 - attribute \src "libresoc.v:151842.13-151842.31" + attribute \src "libresoc.v:152950.3-152958.6" + wire width 4 $1\req_l_s_req$next[3:0]$7698 + attribute \src "libresoc.v:152586.13-152586.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:152143.3-152151.6" - wire $1\rok_l_r_rdok$next[0:0]$7745 - attribute \src "libresoc.v:151854.7-151854.26" + attribute \src "libresoc.v:152887.3-152895.6" + wire $1\rok_l_r_rdok$next[0:0]$7677 + attribute \src "libresoc.v:152598.7-152598.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:152134.3-152142.6" - wire $1\rok_l_s_rdok$next[0:0]$7742 - attribute \src "libresoc.v:151858.7-151858.26" + attribute \src "libresoc.v:152878.3-152886.6" + wire $1\rok_l_s_rdok$next[0:0]$7674 + attribute \src "libresoc.v:152602.7-152602.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:152161.3-152169.6" - wire $1\rst_l_r_rst$next[0:0]$7751 - attribute \src "libresoc.v:151862.7-151862.25" + attribute \src "libresoc.v:152905.3-152913.6" + wire $1\rst_l_r_rst$next[0:0]$7683 + attribute \src "libresoc.v:152606.7-152606.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:152152.3-152160.6" - wire $1\rst_l_s_rst$next[0:0]$7748 - attribute \src "libresoc.v:151866.7-151866.25" + attribute \src "libresoc.v:152896.3-152904.6" + wire $1\rst_l_s_rst$next[0:0]$7680 + attribute \src "libresoc.v:152610.7-152610.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:152197.3-152205.6" - wire width 3 $1\src_l_r_src$next[2:0]$7763 - attribute \src "libresoc.v:151880.13-151880.31" + attribute \src "libresoc.v:152941.3-152949.6" + wire width 3 $1\src_l_r_src$next[2:0]$7695 + attribute \src "libresoc.v:152624.13-152624.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:152188.3-152196.6" - wire width 3 $1\src_l_s_src$next[2:0]$7760 - attribute \src "libresoc.v:151884.13-151884.31" + attribute \src "libresoc.v:152932.3-152940.6" + wire width 3 $1\src_l_s_src$next[2:0]$7692 + attribute \src "libresoc.v:152628.13-152628.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:152345.3-152354.6" - wire width 64 $1\src_r0$next[63:0]$7835 - attribute \src "libresoc.v:151890.14-151890.43" + attribute \src "libresoc.v:153089.3-153098.6" + wire width 64 $1\src_r0$next[63:0]$7767 + attribute \src "libresoc.v:152634.14-152634.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:152355.3-152364.6" - wire width 64 $1\src_r1$next[63:0]$7838 - attribute \src "libresoc.v:151894.14-151894.43" + attribute \src "libresoc.v:153099.3-153108.6" + wire width 64 $1\src_r1$next[63:0]$7770 + attribute \src "libresoc.v:152638.14-152638.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:152365.3-152374.6" - wire $1\src_r2$next[0:0]$7841 - attribute \src "libresoc.v:151898.7-151898.20" + attribute \src "libresoc.v:153109.3-153118.6" + wire $1\src_r2$next[0:0]$7773 + attribute \src "libresoc.v:152642.7-152642.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:152224.3-152256.6" - wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 - attribute \src "libresoc.v:152224.3-152256.6" - wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 - attribute \src "libresoc.v:152224.3-152256.6" - wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 - attribute \src "libresoc.v:152224.3-152256.6" - wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 - attribute \src "libresoc.v:152224.3-152256.6" - wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 - attribute \src "libresoc.v:152224.3-152256.6" - wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 - attribute \src "libresoc.v:152257.3-152278.6" - wire width 64 $2\data_r0__o$next[63:0]$7806 - attribute \src "libresoc.v:152257.3-152278.6" - wire $2\data_r0__o_ok$next[0:0]$7807 - attribute \src "libresoc.v:152279.3-152300.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$7814 - attribute \src "libresoc.v:152279.3-152300.6" - wire $2\data_r1__cr_a_ok$next[0:0]$7815 - attribute \src "libresoc.v:152301.3-152322.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$7822 - attribute \src "libresoc.v:152301.3-152322.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$7823 - attribute \src "libresoc.v:152323.3-152344.6" - wire $2\data_r3__xer_so$next[0:0]$7830 - attribute \src "libresoc.v:152323.3-152344.6" - wire $2\data_r3__xer_so_ok$next[0:0]$7831 - attribute \src "libresoc.v:152257.3-152278.6" - wire $3\data_r0__o_ok$next[0:0]$7808 - attribute \src "libresoc.v:152279.3-152300.6" - wire $3\data_r1__cr_a_ok$next[0:0]$7816 - attribute \src "libresoc.v:152301.3-152322.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$7824 - attribute \src "libresoc.v:152323.3-152344.6" - wire $3\data_r3__xer_so_ok$next[0:0]$7832 - attribute \src "libresoc.v:151909.19-151909.113" - wire width 3 $and$libresoc.v:151909$7641_Y - attribute \src "libresoc.v:151910.19-151910.125" - wire $and$libresoc.v:151910$7642_Y - attribute \src "libresoc.v:151911.19-151911.125" - wire $and$libresoc.v:151911$7643_Y - attribute \src "libresoc.v:151912.19-151912.125" - wire $and$libresoc.v:151912$7644_Y - attribute \src "libresoc.v:151913.19-151913.125" - wire $and$libresoc.v:151913$7645_Y - attribute \src "libresoc.v:151914.18-151914.110" - wire $and$libresoc.v:151914$7646_Y - attribute \src "libresoc.v:151915.19-151915.149" - wire width 4 $and$libresoc.v:151915$7647_Y - attribute \src "libresoc.v:151916.19-151916.121" - wire width 4 $and$libresoc.v:151916$7648_Y - attribute \src "libresoc.v:151917.19-151917.127" - wire $and$libresoc.v:151917$7649_Y - attribute \src "libresoc.v:151918.19-151918.127" - wire $and$libresoc.v:151918$7650_Y - attribute \src "libresoc.v:151919.19-151919.127" - wire $and$libresoc.v:151919$7651_Y - attribute \src "libresoc.v:151920.19-151920.127" - wire $and$libresoc.v:151920$7652_Y - attribute \src "libresoc.v:151922.18-151922.98" - wire $and$libresoc.v:151922$7654_Y - attribute \src "libresoc.v:151924.18-151924.100" - wire $and$libresoc.v:151924$7656_Y - attribute \src "libresoc.v:151925.18-151925.160" - wire width 4 $and$libresoc.v:151925$7657_Y - attribute \src "libresoc.v:151927.18-151927.119" - wire width 4 $and$libresoc.v:151927$7659_Y - attribute \src "libresoc.v:151930.17-151930.123" - wire $and$libresoc.v:151930$7662_Y - attribute \src "libresoc.v:151931.18-151931.116" - wire $and$libresoc.v:151931$7663_Y - attribute \src "libresoc.v:151936.18-151936.113" - wire $and$libresoc.v:151936$7668_Y - attribute \src "libresoc.v:151937.18-151937.125" - wire width 4 $and$libresoc.v:151937$7669_Y - attribute \src "libresoc.v:151939.18-151939.112" - wire $and$libresoc.v:151939$7671_Y - attribute \src "libresoc.v:151941.18-151941.126" - wire $and$libresoc.v:151941$7673_Y - attribute \src "libresoc.v:151942.18-151942.126" - wire $and$libresoc.v:151942$7674_Y - attribute \src "libresoc.v:151943.18-151943.117" - wire $and$libresoc.v:151943$7675_Y - attribute \src "libresoc.v:151949.18-151949.130" - wire $and$libresoc.v:151949$7681_Y - attribute \src "libresoc.v:151950.18-151950.124" - wire width 4 $and$libresoc.v:151950$7682_Y - attribute \src "libresoc.v:151952.18-151952.116" - wire $and$libresoc.v:151952$7684_Y - attribute \src "libresoc.v:151953.18-151953.119" - wire $and$libresoc.v:151953$7685_Y - attribute \src "libresoc.v:151954.18-151954.121" - wire $and$libresoc.v:151954$7686_Y - attribute \src "libresoc.v:151955.18-151955.121" - wire $and$libresoc.v:151955$7687_Y - attribute \src "libresoc.v:151962.18-151962.134" - wire $and$libresoc.v:151962$7694_Y - attribute \src "libresoc.v:151964.18-151964.132" - wire $and$libresoc.v:151964$7696_Y - attribute \src "libresoc.v:151965.18-151965.149" - wire width 3 $and$libresoc.v:151965$7697_Y - attribute \src "libresoc.v:151967.18-151967.129" - wire width 3 $and$libresoc.v:151967$7699_Y - attribute \src "libresoc.v:151938.18-151938.113" - wire $eq$libresoc.v:151938$7670_Y - attribute \src "libresoc.v:151940.18-151940.119" - wire $eq$libresoc.v:151940$7672_Y - attribute \src "libresoc.v:151921.18-151921.97" - wire $not$libresoc.v:151921$7653_Y - attribute \src "libresoc.v:151923.18-151923.99" - wire $not$libresoc.v:151923$7655_Y - attribute \src "libresoc.v:151926.18-151926.113" - wire width 4 $not$libresoc.v:151926$7658_Y - attribute \src "libresoc.v:151929.18-151929.106" - wire $not$libresoc.v:151929$7661_Y - attribute \src "libresoc.v:151935.18-151935.120" - wire $not$libresoc.v:151935$7667_Y - attribute \src "libresoc.v:151946.17-151946.113" - wire width 3 $not$libresoc.v:151946$7678_Y - attribute \src "libresoc.v:151966.18-151966.131" - wire $not$libresoc.v:151966$7698_Y - attribute \src "libresoc.v:151968.18-151968.114" - wire width 3 $not$libresoc.v:151968$7700_Y - attribute \src "libresoc.v:151934.18-151934.112" - wire $or$libresoc.v:151934$7666_Y - attribute \src "libresoc.v:151944.18-151944.122" - wire $or$libresoc.v:151944$7676_Y - attribute \src "libresoc.v:151945.18-151945.124" - wire $or$libresoc.v:151945$7677_Y - attribute \src "libresoc.v:151947.18-151947.168" - wire width 4 $or$libresoc.v:151947$7679_Y - attribute \src "libresoc.v:151948.18-151948.155" - wire width 3 $or$libresoc.v:151948$7680_Y - attribute \src "libresoc.v:151951.18-151951.120" - wire width 4 $or$libresoc.v:151951$7683_Y - attribute \src "libresoc.v:151957.17-151957.117" - wire width 3 $or$libresoc.v:151957$7689_Y - attribute \src "libresoc.v:151963.17-151963.104" - wire $reduce_and$libresoc.v:151963$7695_Y - attribute \src "libresoc.v:151928.18-151928.106" - wire $reduce_or$libresoc.v:151928$7660_Y - attribute \src "libresoc.v:151932.18-151932.113" - wire $reduce_or$libresoc.v:151932$7664_Y - attribute \src "libresoc.v:151933.18-151933.112" - wire $reduce_or$libresoc.v:151933$7665_Y - attribute \src "libresoc.v:151956.18-151956.160" - wire $ternary$libresoc.v:151956$7688_Y - attribute \src "libresoc.v:151958.18-151958.172" - wire width 64 $ternary$libresoc.v:151958$7690_Y - attribute \src "libresoc.v:151959.18-151959.118" - wire width 64 $ternary$libresoc.v:151959$7691_Y - attribute \src "libresoc.v:151960.18-151960.115" - wire width 64 $ternary$libresoc.v:151960$7692_Y - attribute \src "libresoc.v:151961.18-151961.118" - wire $ternary$libresoc.v:151961$7693_Y + attribute \src "libresoc.v:152968.3-153000.6" + wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7727 + attribute \src "libresoc.v:152968.3-153000.6" + wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7728 + attribute \src "libresoc.v:152968.3-153000.6" + wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7729 + attribute \src "libresoc.v:152968.3-153000.6" + wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7730 + attribute \src "libresoc.v:152968.3-153000.6" + wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7731 + attribute \src "libresoc.v:152968.3-153000.6" + wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7732 + attribute \src "libresoc.v:153001.3-153022.6" + wire width 64 $2\data_r0__o$next[63:0]$7738 + attribute \src "libresoc.v:153001.3-153022.6" + wire $2\data_r0__o_ok$next[0:0]$7739 + attribute \src "libresoc.v:153023.3-153044.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$7746 + attribute \src "libresoc.v:153023.3-153044.6" + wire $2\data_r1__cr_a_ok$next[0:0]$7747 + attribute \src "libresoc.v:153045.3-153066.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$7754 + attribute \src "libresoc.v:153045.3-153066.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$7755 + attribute \src "libresoc.v:153067.3-153088.6" + wire $2\data_r3__xer_so$next[0:0]$7762 + attribute \src "libresoc.v:153067.3-153088.6" + wire $2\data_r3__xer_so_ok$next[0:0]$7763 + attribute \src "libresoc.v:153001.3-153022.6" + wire $3\data_r0__o_ok$next[0:0]$7740 + attribute \src "libresoc.v:153023.3-153044.6" + wire $3\data_r1__cr_a_ok$next[0:0]$7748 + attribute \src "libresoc.v:153045.3-153066.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$7756 + attribute \src "libresoc.v:153067.3-153088.6" + wire $3\data_r3__xer_so_ok$next[0:0]$7764 + attribute \src "libresoc.v:152653.19-152653.113" + wire width 3 $and$libresoc.v:152653$7573_Y + attribute \src "libresoc.v:152654.19-152654.125" + wire $and$libresoc.v:152654$7574_Y + attribute \src "libresoc.v:152655.19-152655.125" + wire $and$libresoc.v:152655$7575_Y + attribute \src "libresoc.v:152656.19-152656.125" + wire $and$libresoc.v:152656$7576_Y + attribute \src "libresoc.v:152657.19-152657.125" + wire $and$libresoc.v:152657$7577_Y + attribute \src "libresoc.v:152658.18-152658.110" + wire $and$libresoc.v:152658$7578_Y + attribute \src "libresoc.v:152659.19-152659.149" + wire width 4 $and$libresoc.v:152659$7579_Y + attribute \src "libresoc.v:152660.19-152660.121" + wire width 4 $and$libresoc.v:152660$7580_Y + attribute \src "libresoc.v:152661.19-152661.127" + wire $and$libresoc.v:152661$7581_Y + attribute \src "libresoc.v:152662.19-152662.127" + wire $and$libresoc.v:152662$7582_Y + attribute \src "libresoc.v:152663.19-152663.127" + wire $and$libresoc.v:152663$7583_Y + attribute \src "libresoc.v:152664.19-152664.127" + wire $and$libresoc.v:152664$7584_Y + attribute \src "libresoc.v:152666.18-152666.98" + wire $and$libresoc.v:152666$7586_Y + attribute \src "libresoc.v:152668.18-152668.100" + wire $and$libresoc.v:152668$7588_Y + attribute \src "libresoc.v:152669.18-152669.160" + wire width 4 $and$libresoc.v:152669$7589_Y + attribute \src "libresoc.v:152671.18-152671.119" + wire width 4 $and$libresoc.v:152671$7591_Y + attribute \src "libresoc.v:152674.17-152674.123" + wire $and$libresoc.v:152674$7594_Y + attribute \src "libresoc.v:152675.18-152675.116" + wire $and$libresoc.v:152675$7595_Y + attribute \src "libresoc.v:152680.18-152680.113" + wire $and$libresoc.v:152680$7600_Y + attribute \src "libresoc.v:152681.18-152681.125" + wire width 4 $and$libresoc.v:152681$7601_Y + attribute \src "libresoc.v:152683.18-152683.112" + wire $and$libresoc.v:152683$7603_Y + attribute \src "libresoc.v:152685.18-152685.126" + wire $and$libresoc.v:152685$7605_Y + attribute \src "libresoc.v:152686.18-152686.126" + wire $and$libresoc.v:152686$7606_Y + attribute \src "libresoc.v:152687.18-152687.117" + wire $and$libresoc.v:152687$7607_Y + attribute \src "libresoc.v:152693.18-152693.130" + wire $and$libresoc.v:152693$7613_Y + attribute \src "libresoc.v:152694.18-152694.124" + wire width 4 $and$libresoc.v:152694$7614_Y + attribute \src "libresoc.v:152696.18-152696.116" + wire $and$libresoc.v:152696$7616_Y + attribute \src "libresoc.v:152697.18-152697.119" + wire $and$libresoc.v:152697$7617_Y + attribute \src "libresoc.v:152698.18-152698.121" + wire $and$libresoc.v:152698$7618_Y + attribute \src "libresoc.v:152699.18-152699.121" + wire $and$libresoc.v:152699$7619_Y + attribute \src "libresoc.v:152706.18-152706.134" + wire $and$libresoc.v:152706$7626_Y + attribute \src "libresoc.v:152708.18-152708.132" + wire $and$libresoc.v:152708$7628_Y + attribute \src "libresoc.v:152709.18-152709.149" + wire width 3 $and$libresoc.v:152709$7629_Y + attribute \src "libresoc.v:152711.18-152711.129" + wire width 3 $and$libresoc.v:152711$7631_Y + attribute \src "libresoc.v:152682.18-152682.113" + wire $eq$libresoc.v:152682$7602_Y + attribute \src "libresoc.v:152684.18-152684.119" + wire $eq$libresoc.v:152684$7604_Y + attribute \src "libresoc.v:152665.18-152665.97" + wire $not$libresoc.v:152665$7585_Y + attribute \src "libresoc.v:152667.18-152667.99" + wire $not$libresoc.v:152667$7587_Y + attribute \src "libresoc.v:152670.18-152670.113" + wire width 4 $not$libresoc.v:152670$7590_Y + attribute \src "libresoc.v:152673.18-152673.106" + wire $not$libresoc.v:152673$7593_Y + attribute \src "libresoc.v:152679.18-152679.120" + wire $not$libresoc.v:152679$7599_Y + attribute \src "libresoc.v:152690.17-152690.113" + wire width 3 $not$libresoc.v:152690$7610_Y + attribute \src "libresoc.v:152710.18-152710.131" + wire $not$libresoc.v:152710$7630_Y + attribute \src "libresoc.v:152712.18-152712.114" + wire width 3 $not$libresoc.v:152712$7632_Y + attribute \src "libresoc.v:152678.18-152678.112" + wire $or$libresoc.v:152678$7598_Y + attribute \src "libresoc.v:152688.18-152688.122" + wire $or$libresoc.v:152688$7608_Y + attribute \src "libresoc.v:152689.18-152689.124" + wire $or$libresoc.v:152689$7609_Y + attribute \src "libresoc.v:152691.18-152691.168" + wire width 4 $or$libresoc.v:152691$7611_Y + attribute \src "libresoc.v:152692.18-152692.155" + wire width 3 $or$libresoc.v:152692$7612_Y + attribute \src "libresoc.v:152695.18-152695.120" + wire width 4 $or$libresoc.v:152695$7615_Y + attribute \src "libresoc.v:152701.17-152701.117" + wire width 3 $or$libresoc.v:152701$7621_Y + attribute \src "libresoc.v:152707.17-152707.104" + wire $reduce_and$libresoc.v:152707$7627_Y + attribute \src "libresoc.v:152672.18-152672.106" + wire $reduce_or$libresoc.v:152672$7592_Y + attribute \src "libresoc.v:152676.18-152676.113" + wire $reduce_or$libresoc.v:152676$7596_Y + attribute \src "libresoc.v:152677.18-152677.112" + wire $reduce_or$libresoc.v:152677$7597_Y + attribute \src "libresoc.v:152700.18-152700.160" + wire $ternary$libresoc.v:152700$7620_Y + attribute \src "libresoc.v:152702.18-152702.172" + wire width 64 $ternary$libresoc.v:152702$7622_Y + attribute \src "libresoc.v:152703.18-152703.118" + wire width 64 $ternary$libresoc.v:152703$7623_Y + attribute \src "libresoc.v:152704.18-152704.115" + wire width 64 $ternary$libresoc.v:152704$7624_Y + attribute \src "libresoc.v:152705.18-152705.118" + wire $ternary$libresoc.v:152705$7625_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -316683,7 +283208,7 @@ module \mul0 wire \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \alu_mul0_cr_a attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -316827,7 +283352,7 @@ module \mul0 wire \alu_mul0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_mul0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_mul0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_mul0_p_ready_o @@ -316837,9 +283362,9 @@ module \mul0 wire width 64 \alu_mul0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_mul0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \alu_mul0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \alu_mul0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_mul0_xer_so$1 @@ -316855,11 +283380,11 @@ module \mul0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 26 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 15 \cu_busy_o @@ -316923,9 +283448,9 @@ module \mul0 wire width 2 output 29 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 31 \dest4_o - attribute \src "libresoc.v:151312.7-151312.15" + attribute \src "libresoc.v:152056.7-152056.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 22 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc @@ -317094,9 +283619,9 @@ module \mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 19 \src1_i + wire width 64 input 20 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 20 \src2_i + wire width 64 input 19 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 21 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" @@ -317127,12 +283652,12 @@ module \mul0 wire \src_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 30 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:151909$7641 + cell $and $and$libresoc.v:152653$7573 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -317140,10 +283665,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$96 connect \B \$98 - connect \Y $and$libresoc.v:151909$7641_Y + connect \Y $and$libresoc.v:152653$7573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:151910$7642 + cell $and $and$libresoc.v:152654$7574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317151,10 +283676,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:151910$7642_Y + connect \Y $and$libresoc.v:152654$7574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:151911$7643 + cell $and $and$libresoc.v:152655$7575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317162,10 +283687,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:151911$7643_Y + connect \Y $and$libresoc.v:152655$7575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:151912$7644 + cell $and $and$libresoc.v:152656$7576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317173,10 +283698,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:151912$7644_Y + connect \Y $and$libresoc.v:152656$7576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:151913$7645 + cell $and $and$libresoc.v:152657$7577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317184,10 +283709,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:151913$7645_Y + connect \Y $and$libresoc.v:152657$7577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:151914$7646 + cell $and $and$libresoc.v:152658$7578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317195,10 +283720,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:151914$7646_Y + connect \Y $and$libresoc.v:152658$7578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:151915$7647 + cell $and $and$libresoc.v:152659$7579 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317206,10 +283731,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$102 \$104 \$106 \$108 } - connect \Y $and$libresoc.v:151915$7647_Y + connect \Y $and$libresoc.v:152659$7579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:151916$7648 + cell $and $and$libresoc.v:152660$7580 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317217,10 +283742,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:151916$7648_Y + connect \Y $and$libresoc.v:152660$7580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:151917$7649 + cell $and $and$libresoc.v:152661$7581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317228,10 +283753,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:151917$7649_Y + connect \Y $and$libresoc.v:152661$7581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:151918$7650 + cell $and $and$libresoc.v:152662$7582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317239,10 +283764,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:151918$7650_Y + connect \Y $and$libresoc.v:152662$7582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:151919$7651 + cell $and $and$libresoc.v:152663$7583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317250,10 +283775,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:151919$7651_Y + connect \Y $and$libresoc.v:152663$7583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:151920$7652 + cell $and $and$libresoc.v:152664$7584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317261,10 +283786,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:151920$7652_Y + connect \Y $and$libresoc.v:152664$7584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:151922$7654 + cell $and $and$libresoc.v:152666$7586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317272,10 +283797,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:151922$7654_Y + connect \Y $and$libresoc.v:152666$7586_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:151924$7656 + cell $and $and$libresoc.v:152668$7588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317283,10 +283808,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:151924$7656_Y + connect \Y $and$libresoc.v:152668$7588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:151925$7657 + cell $and $and$libresoc.v:152669$7589 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317294,10 +283819,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:151925$7657_Y + connect \Y $and$libresoc.v:152669$7589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:151927$7659 + cell $and $and$libresoc.v:152671$7591 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317305,10 +283830,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:151927$7659_Y + connect \Y $and$libresoc.v:152671$7591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:151930$7662 + cell $and $and$libresoc.v:152674$7594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317316,10 +283841,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:151930$7662_Y + connect \Y $and$libresoc.v:152674$7594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:151931$7663 + cell $and $and$libresoc.v:152675$7595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317327,10 +283852,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:151931$7663_Y + connect \Y $and$libresoc.v:152675$7595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:151936$7668 + cell $and $and$libresoc.v:152680$7600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317338,10 +283863,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:151936$7668_Y + connect \Y $and$libresoc.v:152680$7600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:151937$7669 + cell $and $and$libresoc.v:152681$7601 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317349,10 +283874,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:151937$7669_Y + connect \Y $and$libresoc.v:152681$7601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:151939$7671 + cell $and $and$libresoc.v:152683$7603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317360,10 +283885,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:151939$7671_Y + connect \Y $and$libresoc.v:152683$7603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:151941$7673 + cell $and $and$libresoc.v:152685$7605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317371,10 +283896,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_mul0_n_ready_i - connect \Y $and$libresoc.v:151941$7673_Y + connect \Y $and$libresoc.v:152685$7605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:151942$7674 + cell $and $and$libresoc.v:152686$7606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317382,10 +283907,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_mul0_n_valid_o - connect \Y $and$libresoc.v:151942$7674_Y + connect \Y $and$libresoc.v:152686$7606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:151943$7675 + cell $and $and$libresoc.v:152687$7607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317393,10 +283918,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:151943$7675_Y + connect \Y $and$libresoc.v:152687$7607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:151949$7681 + cell $and $and$libresoc.v:152693$7613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317404,10 +283929,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:151949$7681_Y + connect \Y $and$libresoc.v:152693$7613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:151950$7682 + cell $and $and$libresoc.v:152694$7614 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317415,10 +283940,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:151950$7682_Y + connect \Y $and$libresoc.v:152694$7614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:151952$7684 + cell $and $and$libresoc.v:152696$7616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317426,10 +283951,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:151952$7684_Y + connect \Y $and$libresoc.v:152696$7616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:151953$7685 + cell $and $and$libresoc.v:152697$7617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317437,10 +283962,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:151953$7685_Y + connect \Y $and$libresoc.v:152697$7617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:151954$7686 + cell $and $and$libresoc.v:152698$7618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317448,10 +283973,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:151954$7686_Y + connect \Y $and$libresoc.v:152698$7618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:151955$7687 + cell $and $and$libresoc.v:152699$7619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317459,10 +283984,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:151955$7687_Y + connect \Y $and$libresoc.v:152699$7619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:151962$7694 + cell $and $and$libresoc.v:152706$7626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317470,10 +283995,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:151962$7694_Y + connect \Y $and$libresoc.v:152706$7626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:151964$7696 + cell $and $and$libresoc.v:152708$7628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317481,10 +284006,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:151964$7696_Y + connect \Y $and$libresoc.v:152708$7628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:151965$7697 + cell $and $and$libresoc.v:152709$7629 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -317492,10 +284017,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:151965$7697_Y + connect \Y $and$libresoc.v:152709$7629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:151967$7699 + cell $and $and$libresoc.v:152711$7631 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -317503,10 +284028,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$92 connect \B { 1'1 \$94 1'1 } - connect \Y $and$libresoc.v:151967$7699_Y + connect \Y $and$libresoc.v:152711$7631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:151938$7670 + cell $eq $eq$libresoc.v:152682$7602 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317514,10 +284039,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:151938$7670_Y + connect \Y $eq$libresoc.v:152682$7602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:151940$7672 + cell $eq $eq$libresoc.v:152684$7604 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317525,74 +284050,74 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:151940$7672_Y + connect \Y $eq$libresoc.v:152684$7604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:151921$7653 + cell $not $not$libresoc.v:152665$7585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:151921$7653_Y + connect \Y $not$libresoc.v:152665$7585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:151923$7655 + cell $not $not$libresoc.v:152667$7587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:151923$7655_Y + connect \Y $not$libresoc.v:152667$7587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:151926$7658 + cell $not $not$libresoc.v:152670$7590 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:151926$7658_Y + connect \Y $not$libresoc.v:152670$7590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:151929$7661 + cell $not $not$libresoc.v:152673$7593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:151929$7661_Y + connect \Y $not$libresoc.v:152673$7593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:151935$7667 + cell $not $not$libresoc.v:152679$7599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_ready_i - connect \Y $not$libresoc.v:151935$7667_Y + connect \Y $not$libresoc.v:152679$7599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:151946$7678 + cell $not $not$libresoc.v:152690$7610 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:151946$7678_Y + connect \Y $not$libresoc.v:152690$7610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:151966$7698 + cell $not $not$libresoc.v:152710$7630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_mul_op__imm_data__ok - connect \Y $not$libresoc.v:151966$7698_Y + connect \Y $not$libresoc.v:152710$7630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:151968$7700 + cell $not $not$libresoc.v:152712$7632 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:151968$7700_Y + connect \Y $not$libresoc.v:152712$7632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:151934$7666 + cell $or $or$libresoc.v:152678$7598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317600,10 +284125,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:151934$7666_Y + connect \Y $or$libresoc.v:152678$7598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:151944$7676 + cell $or $or$libresoc.v:152688$7608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317611,10 +284136,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:151944$7676_Y + connect \Y $or$libresoc.v:152688$7608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:151945$7677 + cell $or $or$libresoc.v:152689$7609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317622,10 +284147,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:151945$7677_Y + connect \Y $or$libresoc.v:152689$7609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:151947$7679 + cell $or $or$libresoc.v:152691$7611 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317633,10 +284158,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:151947$7679_Y + connect \Y $or$libresoc.v:152691$7611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:151948$7680 + cell $or $or$libresoc.v:152692$7612 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -317644,10 +284169,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:151948$7680_Y + connect \Y $or$libresoc.v:152692$7612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:151951$7683 + cell $or $or$libresoc.v:152695$7615 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317655,10 +284180,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:151951$7683_Y + connect \Y $or$libresoc.v:152695$7615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:151957$7689 + cell $or $or$libresoc.v:152701$7621 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -317666,82 +284191,82 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:151957$7689_Y + connect \Y $or$libresoc.v:152701$7621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:151963$7695 + cell $reduce_and $reduce_and$libresoc.v:152707$7627 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:151963$7695_Y + connect \Y $reduce_and$libresoc.v:152707$7627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:151928$7660 + cell $reduce_or $reduce_or$libresoc.v:152672$7592 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:151928$7660_Y + connect \Y $reduce_or$libresoc.v:152672$7592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:151932$7664 + cell $reduce_or $reduce_or$libresoc.v:152676$7596 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:151932$7664_Y + connect \Y $reduce_or$libresoc.v:152676$7596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:151933$7665 + cell $reduce_or $reduce_or$libresoc.v:152677$7597 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:151933$7665_Y + connect \Y $reduce_or$libresoc.v:152677$7597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:151956$7688 + cell $mux $ternary$libresoc.v:152700$7620 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:151956$7688_Y + connect \Y $ternary$libresoc.v:152700$7620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:151958$7690 + cell $mux $ternary$libresoc.v:152702$7622 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_mul0_mul_op__imm_data__data connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:151958$7690_Y + connect \Y $ternary$libresoc.v:152702$7622_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:151959$7691 + cell $mux $ternary$libresoc.v:152703$7623 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:151959$7691_Y + connect \Y $ternary$libresoc.v:152703$7623_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:151960$7692 + cell $mux $ternary$libresoc.v:152704$7624 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:151960$7692_Y + connect \Y $ternary$libresoc.v:152704$7624_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:151961$7693 + cell $mux $ternary$libresoc.v:152705$7625 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:151961$7693_Y + connect \Y $ternary$libresoc.v:152705$7625_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:152045.15-152051.4" + attribute \src "libresoc.v:152789.15-152795.4" cell \alu_l$107 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317750,7 +284275,7 @@ module \mul0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:152052.12-152082.4" + attribute \src "libresoc.v:152796.12-152826.4" cell \alu_mul0 \alu_mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317783,7 +284308,7 @@ module \mul0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:152083.16-152089.4" + attribute \src "libresoc.v:152827.16-152833.4" cell \alui_l$106 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317792,7 +284317,7 @@ module \mul0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:152090.15-152096.4" + attribute \src "libresoc.v:152834.15-152840.4" cell \opc_l$102 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317801,7 +284326,7 @@ module \mul0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:152097.15-152103.4" + attribute \src "libresoc.v:152841.15-152847.4" cell \req_l$103 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317810,7 +284335,7 @@ module \mul0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:152104.15-152110.4" + attribute \src "libresoc.v:152848.15-152854.4" cell \rok_l$105 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317819,7 +284344,7 @@ module \mul0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:152111.15-152116.4" + attribute \src "libresoc.v:152855.15-152860.4" cell \rst_l$104 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317827,7 +284352,7 @@ module \mul0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:152117.15-152123.4" + attribute \src "libresoc.v:152861.15-152867.4" cell \src_l$101 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317835,592 +284360,592 @@ module \mul0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:151312.7-151312.20" - process $proc$libresoc.v:151312$7855 + attribute \src "libresoc.v:152056.7-152056.20" + process $proc$libresoc.v:152056$7787 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:151436.7-151436.24" - process $proc$libresoc.v:151436$7856 + attribute \src "libresoc.v:152180.7-152180.24" + process $proc$libresoc.v:152180$7788 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:151446.7-151446.26" - process $proc$libresoc.v:151446$7857 + attribute \src "libresoc.v:152190.7-152190.26" + process $proc$libresoc.v:152190$7789 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:151454.7-151454.25" - process $proc$libresoc.v:151454$7858 + attribute \src "libresoc.v:152198.7-152198.25" + process $proc$libresoc.v:152198$7790 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:151477.14-151477.49" - process $proc$libresoc.v:151477$7859 + attribute \src "libresoc.v:152221.14-152221.49" + process $proc$libresoc.v:152221$7791 assign { } { } assign $1\alu_mul0_mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:151481.14-151481.68" - process $proc$libresoc.v:151481$7860 + attribute \src "libresoc.v:152225.14-152225.68" + process $proc$libresoc.v:152225$7792 assign { } { } assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:151485.7-151485.43" - process $proc$libresoc.v:151485$7861 + attribute \src "libresoc.v:152229.7-152229.43" + process $proc$libresoc.v:152229$7793 assign { } { } assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:151489.14-151489.43" - process $proc$libresoc.v:151489$7862 + attribute \src "libresoc.v:152233.14-152233.43" + process $proc$libresoc.v:152233$7794 assign { } { } assign $1\alu_mul0_mul_op__insn[31:0] 0 sync always sync init update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:151568.13-151568.47" - process $proc$libresoc.v:151568$7863 + attribute \src "libresoc.v:152312.13-152312.47" + process $proc$libresoc.v:152312$7795 assign { } { } assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:151572.7-151572.39" - process $proc$libresoc.v:151572$7864 + attribute \src "libresoc.v:152316.7-152316.39" + process $proc$libresoc.v:152316$7796 assign { } { } assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:151576.7-151576.40" - process $proc$libresoc.v:151576$7865 + attribute \src "libresoc.v:152320.7-152320.40" + process $proc$libresoc.v:152320$7797 assign { } { } assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:151580.7-151580.37" - process $proc$libresoc.v:151580$7866 + attribute \src "libresoc.v:152324.7-152324.37" + process $proc$libresoc.v:152324$7798 assign { } { } assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:151584.7-151584.37" - process $proc$libresoc.v:151584$7867 + attribute \src "libresoc.v:152328.7-152328.37" + process $proc$libresoc.v:152328$7799 assign { } { } assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:151588.7-151588.37" - process $proc$libresoc.v:151588$7868 + attribute \src "libresoc.v:152332.7-152332.37" + process $proc$libresoc.v:152332$7800 assign { } { } assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:151592.7-151592.37" - process $proc$libresoc.v:151592$7869 + attribute \src "libresoc.v:152336.7-152336.37" + process $proc$libresoc.v:152336$7801 assign { } { } assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:151596.7-151596.40" - process $proc$libresoc.v:151596$7870 + attribute \src "libresoc.v:152340.7-152340.40" + process $proc$libresoc.v:152340$7802 assign { } { } assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:151626.7-151626.27" - process $proc$libresoc.v:151626$7871 + attribute \src "libresoc.v:152370.7-152370.27" + process $proc$libresoc.v:152370$7803 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:151660.14-151660.47" - process $proc$libresoc.v:151660$7872 + attribute \src "libresoc.v:152404.14-152404.47" + process $proc$libresoc.v:152404$7804 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:151664.7-151664.27" - process $proc$libresoc.v:151664$7873 + attribute \src "libresoc.v:152408.7-152408.27" + process $proc$libresoc.v:152408$7805 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:151668.13-151668.33" - process $proc$libresoc.v:151668$7874 + attribute \src "libresoc.v:152412.13-152412.33" + process $proc$libresoc.v:152412$7806 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:151672.7-151672.30" - process $proc$libresoc.v:151672$7875 + attribute \src "libresoc.v:152416.7-152416.30" + process $proc$libresoc.v:152416$7807 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:151676.13-151676.35" - process $proc$libresoc.v:151676$7876 + attribute \src "libresoc.v:152420.13-152420.35" + process $proc$libresoc.v:152420$7808 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:151680.7-151680.32" - process $proc$libresoc.v:151680$7877 + attribute \src "libresoc.v:152424.7-152424.32" + process $proc$libresoc.v:152424$7809 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:151684.7-151684.29" - process $proc$libresoc.v:151684$7878 + attribute \src "libresoc.v:152428.7-152428.29" + process $proc$libresoc.v:152428$7810 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:151688.7-151688.32" - process $proc$libresoc.v:151688$7879 + attribute \src "libresoc.v:152432.7-152432.32" + process $proc$libresoc.v:152432$7811 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:151708.7-151708.25" - process $proc$libresoc.v:151708$7880 + attribute \src "libresoc.v:152452.7-152452.25" + process $proc$libresoc.v:152452$7812 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:151712.7-151712.25" - process $proc$libresoc.v:151712$7881 + attribute \src "libresoc.v:152456.7-152456.25" + process $proc$libresoc.v:152456$7813 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:151830.13-151830.30" - process $proc$libresoc.v:151830$7882 + attribute \src "libresoc.v:152574.13-152574.30" + process $proc$libresoc.v:152574$7814 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:151838.13-151838.31" - process $proc$libresoc.v:151838$7883 + attribute \src "libresoc.v:152582.13-152582.31" + process $proc$libresoc.v:152582$7815 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:151842.13-151842.31" - process $proc$libresoc.v:151842$7884 + attribute \src "libresoc.v:152586.13-152586.31" + process $proc$libresoc.v:152586$7816 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:151854.7-151854.26" - process $proc$libresoc.v:151854$7885 + attribute \src "libresoc.v:152598.7-152598.26" + process $proc$libresoc.v:152598$7817 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:151858.7-151858.26" - process $proc$libresoc.v:151858$7886 + attribute \src "libresoc.v:152602.7-152602.26" + process $proc$libresoc.v:152602$7818 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:151862.7-151862.25" - process $proc$libresoc.v:151862$7887 + attribute \src "libresoc.v:152606.7-152606.25" + process $proc$libresoc.v:152606$7819 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:151866.7-151866.25" - process $proc$libresoc.v:151866$7888 + attribute \src "libresoc.v:152610.7-152610.25" + process $proc$libresoc.v:152610$7820 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:151880.13-151880.31" - process $proc$libresoc.v:151880$7889 + attribute \src "libresoc.v:152624.13-152624.31" + process $proc$libresoc.v:152624$7821 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:151884.13-151884.31" - process $proc$libresoc.v:151884$7890 + attribute \src "libresoc.v:152628.13-152628.31" + process $proc$libresoc.v:152628$7822 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:151890.14-151890.43" - process $proc$libresoc.v:151890$7891 + attribute \src "libresoc.v:152634.14-152634.43" + process $proc$libresoc.v:152634$7823 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:151894.14-151894.43" - process $proc$libresoc.v:151894$7892 + attribute \src "libresoc.v:152638.14-152638.43" + process $proc$libresoc.v:152638$7824 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:151898.7-151898.20" - process $proc$libresoc.v:151898$7893 + attribute \src "libresoc.v:152642.7-152642.20" + process $proc$libresoc.v:152642$7825 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:151969.3-151970.39" - process $proc$libresoc.v:151969$7701 + attribute \src "libresoc.v:152713.3-152714.39" + process $proc$libresoc.v:152713$7633 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:151971.3-151972.43" - process $proc$libresoc.v:151971$7702 + attribute \src "libresoc.v:152715.3-152716.43" + process $proc$libresoc.v:152715$7634 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:151973.3-151974.29" - process $proc$libresoc.v:151973$7703 + attribute \src "libresoc.v:152717.3-152718.29" + process $proc$libresoc.v:152717$7635 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:151975.3-151976.29" - process $proc$libresoc.v:151975$7704 + attribute \src "libresoc.v:152719.3-152720.29" + process $proc$libresoc.v:152719$7636 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:151977.3-151978.29" - process $proc$libresoc.v:151977$7705 + attribute \src "libresoc.v:152721.3-152722.29" + process $proc$libresoc.v:152721$7637 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:151979.3-151980.47" - process $proc$libresoc.v:151979$7706 + attribute \src "libresoc.v:152723.3-152724.47" + process $proc$libresoc.v:152723$7638 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:151981.3-151982.53" - process $proc$libresoc.v:151981$7707 + attribute \src "libresoc.v:152725.3-152726.53" + process $proc$libresoc.v:152725$7639 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:151983.3-151984.47" - process $proc$libresoc.v:151983$7708 + attribute \src "libresoc.v:152727.3-152728.47" + process $proc$libresoc.v:152727$7640 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:151985.3-151986.53" - process $proc$libresoc.v:151985$7709 + attribute \src "libresoc.v:152729.3-152730.53" + process $proc$libresoc.v:152729$7641 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:151987.3-151988.43" - process $proc$libresoc.v:151987$7710 + attribute \src "libresoc.v:152731.3-152732.43" + process $proc$libresoc.v:152731$7642 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:151989.3-151990.49" - process $proc$libresoc.v:151989$7711 + attribute \src "libresoc.v:152733.3-152734.49" + process $proc$libresoc.v:152733$7643 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:151991.3-151992.37" - process $proc$libresoc.v:151991$7712 + attribute \src "libresoc.v:152735.3-152736.37" + process $proc$libresoc.v:152735$7644 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:151993.3-151994.43" - process $proc$libresoc.v:151993$7713 + attribute \src "libresoc.v:152737.3-152738.43" + process $proc$libresoc.v:152737$7645 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:151995.3-151996.69" - process $proc$libresoc.v:151995$7714 + attribute \src "libresoc.v:152739.3-152740.69" + process $proc$libresoc.v:152739$7646 assign { } { } assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:151997.3-151998.65" - process $proc$libresoc.v:151997$7715 + attribute \src "libresoc.v:152741.3-152742.65" + process $proc$libresoc.v:152741$7647 assign { } { } assign $0\alu_mul0_mul_op__fn_unit[13:0] \alu_mul0_mul_op__fn_unit$next sync posedge \coresync_clk update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:151999.3-152000.79" - process $proc$libresoc.v:151999$7716 + attribute \src "libresoc.v:152743.3-152744.79" + process $proc$libresoc.v:152743$7648 assign { } { } assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:152001.3-152002.75" - process $proc$libresoc.v:152001$7717 + attribute \src "libresoc.v:152745.3-152746.75" + process $proc$libresoc.v:152745$7649 assign { } { } assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:152003.3-152004.63" - process $proc$libresoc.v:152003$7718 + attribute \src "libresoc.v:152747.3-152748.63" + process $proc$libresoc.v:152747$7650 assign { } { } assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:152005.3-152006.63" - process $proc$libresoc.v:152005$7719 + attribute \src "libresoc.v:152749.3-152750.63" + process $proc$libresoc.v:152749$7651 assign { } { } assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:152007.3-152008.63" - process $proc$libresoc.v:152007$7720 + attribute \src "libresoc.v:152751.3-152752.63" + process $proc$libresoc.v:152751$7652 assign { } { } assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:152009.3-152010.63" - process $proc$libresoc.v:152009$7721 + attribute \src "libresoc.v:152753.3-152754.63" + process $proc$libresoc.v:152753$7653 assign { } { } assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:152011.3-152012.69" - process $proc$libresoc.v:152011$7722 + attribute \src "libresoc.v:152755.3-152756.69" + process $proc$libresoc.v:152755$7654 assign { } { } assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next sync posedge \coresync_clk update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:152013.3-152014.67" - process $proc$libresoc.v:152013$7723 + attribute \src "libresoc.v:152757.3-152758.67" + process $proc$libresoc.v:152757$7655 assign { } { } assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:152015.3-152016.69" - process $proc$libresoc.v:152015$7724 + attribute \src "libresoc.v:152759.3-152760.69" + process $proc$libresoc.v:152759$7656 assign { } { } assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:152017.3-152018.59" - process $proc$libresoc.v:152017$7725 + attribute \src "libresoc.v:152761.3-152762.59" + process $proc$libresoc.v:152761$7657 assign { } { } assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:152019.3-152020.39" - process $proc$libresoc.v:152019$7726 + attribute \src "libresoc.v:152763.3-152764.39" + process $proc$libresoc.v:152763$7658 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:152021.3-152022.39" - process $proc$libresoc.v:152021$7727 + attribute \src "libresoc.v:152765.3-152766.39" + process $proc$libresoc.v:152765$7659 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:152023.3-152024.39" - process $proc$libresoc.v:152023$7728 + attribute \src "libresoc.v:152767.3-152768.39" + process $proc$libresoc.v:152767$7660 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:152025.3-152026.39" - process $proc$libresoc.v:152025$7729 + attribute \src "libresoc.v:152769.3-152770.39" + process $proc$libresoc.v:152769$7661 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:152027.3-152028.39" - process $proc$libresoc.v:152027$7730 + attribute \src "libresoc.v:152771.3-152772.39" + process $proc$libresoc.v:152771$7662 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:152029.3-152030.39" - process $proc$libresoc.v:152029$7731 + attribute \src "libresoc.v:152773.3-152774.39" + process $proc$libresoc.v:152773$7663 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:152031.3-152032.39" - process $proc$libresoc.v:152031$7732 + attribute \src "libresoc.v:152775.3-152776.39" + process $proc$libresoc.v:152775$7664 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:152033.3-152034.39" - process $proc$libresoc.v:152033$7733 + attribute \src "libresoc.v:152777.3-152778.39" + process $proc$libresoc.v:152777$7665 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:152035.3-152036.41" - process $proc$libresoc.v:152035$7734 + attribute \src "libresoc.v:152779.3-152780.41" + process $proc$libresoc.v:152779$7666 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:152037.3-152038.41" - process $proc$libresoc.v:152037$7735 + attribute \src "libresoc.v:152781.3-152782.41" + process $proc$libresoc.v:152781$7667 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:152039.3-152040.37" - process $proc$libresoc.v:152039$7736 + attribute \src "libresoc.v:152783.3-152784.37" + process $proc$libresoc.v:152783$7668 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:152041.3-152042.40" - process $proc$libresoc.v:152041$7737 + attribute \src "libresoc.v:152785.3-152786.40" + process $proc$libresoc.v:152785$7669 assign { } { } assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:152043.3-152044.25" - process $proc$libresoc.v:152043$7738 + attribute \src "libresoc.v:152787.3-152788.25" + process $proc$libresoc.v:152787$7670 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:152124.3-152133.6" - process $proc$libresoc.v:152124$7739 + attribute \src "libresoc.v:152868.3-152877.6" + process $proc$libresoc.v:152868$7671 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:152125.5-152125.29" + attribute \src "libresoc.v:152869.5-152869.29" switch \initial - attribute \src "libresoc.v:152125.9-152125.17" + attribute \src "libresoc.v:152869.9-152869.17" case 1'1 case end @@ -318436,14 +284961,14 @@ module \mul0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:152134.3-152142.6" - process $proc$libresoc.v:152134$7740 + attribute \src "libresoc.v:152878.3-152886.6" + process $proc$libresoc.v:152878$7672 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$7741 $1\rok_l_s_rdok$next[0:0]$7742 - attribute \src "libresoc.v:152135.5-152135.29" + assign $0\rok_l_s_rdok$next[0:0]$7673 $1\rok_l_s_rdok$next[0:0]$7674 + attribute \src "libresoc.v:152879.5-152879.29" switch \initial - attribute \src "libresoc.v:152135.9-152135.17" + attribute \src "libresoc.v:152879.9-152879.17" case 1'1 case end @@ -318452,21 +284977,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$7742 1'0 + assign $1\rok_l_s_rdok$next[0:0]$7674 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$7742 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$7674 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7741 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7673 end - attribute \src "libresoc.v:152143.3-152151.6" - process $proc$libresoc.v:152143$7743 + attribute \src "libresoc.v:152887.3-152895.6" + process $proc$libresoc.v:152887$7675 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$7744 $1\rok_l_r_rdok$next[0:0]$7745 - attribute \src "libresoc.v:152144.5-152144.29" + assign $0\rok_l_r_rdok$next[0:0]$7676 $1\rok_l_r_rdok$next[0:0]$7677 + attribute \src "libresoc.v:152888.5-152888.29" switch \initial - attribute \src "libresoc.v:152144.9-152144.17" + attribute \src "libresoc.v:152888.9-152888.17" case 1'1 case end @@ -318475,21 +285000,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$7745 1'1 + assign $1\rok_l_r_rdok$next[0:0]$7677 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$7745 \$64 + assign $1\rok_l_r_rdok$next[0:0]$7677 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7744 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7676 end - attribute \src "libresoc.v:152152.3-152160.6" - process $proc$libresoc.v:152152$7746 + attribute \src "libresoc.v:152896.3-152904.6" + process $proc$libresoc.v:152896$7678 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$7747 $1\rst_l_s_rst$next[0:0]$7748 - attribute \src "libresoc.v:152153.5-152153.29" + assign $0\rst_l_s_rst$next[0:0]$7679 $1\rst_l_s_rst$next[0:0]$7680 + attribute \src "libresoc.v:152897.5-152897.29" switch \initial - attribute \src "libresoc.v:152153.9-152153.17" + attribute \src "libresoc.v:152897.9-152897.17" case 1'1 case end @@ -318498,21 +285023,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$7748 1'0 + assign $1\rst_l_s_rst$next[0:0]$7680 1'0 case - assign $1\rst_l_s_rst$next[0:0]$7748 \all_rd + assign $1\rst_l_s_rst$next[0:0]$7680 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7747 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7679 end - attribute \src "libresoc.v:152161.3-152169.6" - process $proc$libresoc.v:152161$7749 + attribute \src "libresoc.v:152905.3-152913.6" + process $proc$libresoc.v:152905$7681 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$7750 $1\rst_l_r_rst$next[0:0]$7751 - attribute \src "libresoc.v:152162.5-152162.29" + assign $0\rst_l_r_rst$next[0:0]$7682 $1\rst_l_r_rst$next[0:0]$7683 + attribute \src "libresoc.v:152906.5-152906.29" switch \initial - attribute \src "libresoc.v:152162.9-152162.17" + attribute \src "libresoc.v:152906.9-152906.17" case 1'1 case end @@ -318521,21 +285046,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$7751 1'1 + assign $1\rst_l_r_rst$next[0:0]$7683 1'1 case - assign $1\rst_l_r_rst$next[0:0]$7751 \rst_r + assign $1\rst_l_r_rst$next[0:0]$7683 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7750 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7682 end - attribute \src "libresoc.v:152170.3-152178.6" - process $proc$libresoc.v:152170$7752 + attribute \src "libresoc.v:152914.3-152922.6" + process $proc$libresoc.v:152914$7684 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$7753 $1\opc_l_s_opc$next[0:0]$7754 - attribute \src "libresoc.v:152171.5-152171.29" + assign $0\opc_l_s_opc$next[0:0]$7685 $1\opc_l_s_opc$next[0:0]$7686 + attribute \src "libresoc.v:152915.5-152915.29" switch \initial - attribute \src "libresoc.v:152171.9-152171.17" + attribute \src "libresoc.v:152915.9-152915.17" case 1'1 case end @@ -318544,21 +285069,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$7754 1'0 + assign $1\opc_l_s_opc$next[0:0]$7686 1'0 case - assign $1\opc_l_s_opc$next[0:0]$7754 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$7686 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7753 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7685 end - attribute \src "libresoc.v:152179.3-152187.6" - process $proc$libresoc.v:152179$7755 + attribute \src "libresoc.v:152923.3-152931.6" + process $proc$libresoc.v:152923$7687 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$7756 $1\opc_l_r_opc$next[0:0]$7757 - attribute \src "libresoc.v:152180.5-152180.29" + assign $0\opc_l_r_opc$next[0:0]$7688 $1\opc_l_r_opc$next[0:0]$7689 + attribute \src "libresoc.v:152924.5-152924.29" switch \initial - attribute \src "libresoc.v:152180.9-152180.17" + attribute \src "libresoc.v:152924.9-152924.17" case 1'1 case end @@ -318567,21 +285092,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$7757 1'1 + assign $1\opc_l_r_opc$next[0:0]$7689 1'1 case - assign $1\opc_l_r_opc$next[0:0]$7757 \req_done + assign $1\opc_l_r_opc$next[0:0]$7689 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7756 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7688 end - attribute \src "libresoc.v:152188.3-152196.6" - process $proc$libresoc.v:152188$7758 + attribute \src "libresoc.v:152932.3-152940.6" + process $proc$libresoc.v:152932$7690 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$7759 $1\src_l_s_src$next[2:0]$7760 - attribute \src "libresoc.v:152189.5-152189.29" + assign $0\src_l_s_src$next[2:0]$7691 $1\src_l_s_src$next[2:0]$7692 + attribute \src "libresoc.v:152933.5-152933.29" switch \initial - attribute \src "libresoc.v:152189.9-152189.17" + attribute \src "libresoc.v:152933.9-152933.17" case 1'1 case end @@ -318590,21 +285115,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$7760 3'000 + assign $1\src_l_s_src$next[2:0]$7692 3'000 case - assign $1\src_l_s_src$next[2:0]$7760 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$7692 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7759 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7691 end - attribute \src "libresoc.v:152197.3-152205.6" - process $proc$libresoc.v:152197$7761 + attribute \src "libresoc.v:152941.3-152949.6" + process $proc$libresoc.v:152941$7693 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$7762 $1\src_l_r_src$next[2:0]$7763 - attribute \src "libresoc.v:152198.5-152198.29" + assign $0\src_l_r_src$next[2:0]$7694 $1\src_l_r_src$next[2:0]$7695 + attribute \src "libresoc.v:152942.5-152942.29" switch \initial - attribute \src "libresoc.v:152198.9-152198.17" + attribute \src "libresoc.v:152942.9-152942.17" case 1'1 case end @@ -318613,21 +285138,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$7763 3'111 + assign $1\src_l_r_src$next[2:0]$7695 3'111 case - assign $1\src_l_r_src$next[2:0]$7763 \reset_r + assign $1\src_l_r_src$next[2:0]$7695 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7762 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7694 end - attribute \src "libresoc.v:152206.3-152214.6" - process $proc$libresoc.v:152206$7764 + attribute \src "libresoc.v:152950.3-152958.6" + process $proc$libresoc.v:152950$7696 assign { } { } assign { } { } - assign $0\req_l_s_req$next[3:0]$7765 $1\req_l_s_req$next[3:0]$7766 - attribute \src "libresoc.v:152207.5-152207.29" + assign $0\req_l_s_req$next[3:0]$7697 $1\req_l_s_req$next[3:0]$7698 + attribute \src "libresoc.v:152951.5-152951.29" switch \initial - attribute \src "libresoc.v:152207.9-152207.17" + attribute \src "libresoc.v:152951.9-152951.17" case 1'1 case end @@ -318636,21 +285161,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[3:0]$7766 4'0000 + assign $1\req_l_s_req$next[3:0]$7698 4'0000 case - assign $1\req_l_s_req$next[3:0]$7766 \$66 + assign $1\req_l_s_req$next[3:0]$7698 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7765 + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7697 end - attribute \src "libresoc.v:152215.3-152223.6" - process $proc$libresoc.v:152215$7767 + attribute \src "libresoc.v:152959.3-152967.6" + process $proc$libresoc.v:152959$7699 assign { } { } assign { } { } - assign $0\req_l_r_req$next[3:0]$7768 $1\req_l_r_req$next[3:0]$7769 - attribute \src "libresoc.v:152216.5-152216.29" + assign $0\req_l_r_req$next[3:0]$7700 $1\req_l_r_req$next[3:0]$7701 + attribute \src "libresoc.v:152960.5-152960.29" switch \initial - attribute \src "libresoc.v:152216.9-152216.17" + attribute \src "libresoc.v:152960.9-152960.17" case 1'1 case end @@ -318659,15 +285184,15 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[3:0]$7769 4'1111 + assign $1\req_l_r_req$next[3:0]$7701 4'1111 case - assign $1\req_l_r_req$next[3:0]$7769 \$68 + assign $1\req_l_r_req$next[3:0]$7701 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7768 + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7700 end - attribute \src "libresoc.v:152224.3-152256.6" - process $proc$libresoc.v:152224$7770 + attribute \src "libresoc.v:152968.3-153000.6" + process $proc$libresoc.v:152968$7702 assign { } { } assign { } { } assign { } { } @@ -318692,27 +285217,27 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 + assign $0\alu_mul0_mul_op__fn_unit$next[13:0]$7703 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7715 assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__insn$next[31:0]$7774 $1\alu_mul0_mul_op__insn$next[31:0]$7786 - assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 - assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 - assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 + assign $0\alu_mul0_mul_op__insn$next[31:0]$7706 $1\alu_mul0_mul_op__insn$next[31:0]$7718 + assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7707 $1\alu_mul0_mul_op__insn_type$next[6:0]$7719 + assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7708 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7720 + assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7709 $1\alu_mul0_mul_op__is_signed$next[0:0]$7721 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 - assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 - assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 - assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 - assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 - assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 - assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 - attribute \src "libresoc.v:152225.5-152225.29" + assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7714 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7726 + assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7704 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7727 + assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7705 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7728 + assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7710 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7729 + assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7711 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7730 + assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7712 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7731 + assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7713 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7732 + attribute \src "libresoc.v:152969.5-152969.29" switch \initial - attribute \src "libresoc.v:152225.9-152225.17" + attribute \src "libresoc.v:152969.9-152969.17" case 1'1 case end @@ -318732,20 +285257,20 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_mul0_mul_op__insn$next[31:0]$7786 $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + assign { $1\alu_mul0_mul_op__insn$next[31:0]$7718 $1\alu_mul0_mul_op__is_signed$next[0:0]$7721 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7720 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7726 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7723 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7722 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7724 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7725 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7717 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7716 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7715 $1\alu_mul0_mul_op__insn_type$next[6:0]$7719 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } case - assign $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 \alu_mul0_mul_op__fn_unit - assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 \alu_mul0_mul_op__imm_data__data - assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 \alu_mul0_mul_op__imm_data__ok - assign $1\alu_mul0_mul_op__insn$next[31:0]$7786 \alu_mul0_mul_op__insn - assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 \alu_mul0_mul_op__insn_type - assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 \alu_mul0_mul_op__is_32bit - assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 \alu_mul0_mul_op__is_signed - assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 \alu_mul0_mul_op__oe__oe - assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 \alu_mul0_mul_op__oe__ok - assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 \alu_mul0_mul_op__rc__ok - assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 \alu_mul0_mul_op__rc__rc - assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 \alu_mul0_mul_op__write_cr0 + assign $1\alu_mul0_mul_op__fn_unit$next[13:0]$7715 \alu_mul0_mul_op__fn_unit + assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7716 \alu_mul0_mul_op__imm_data__data + assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7717 \alu_mul0_mul_op__imm_data__ok + assign $1\alu_mul0_mul_op__insn$next[31:0]$7718 \alu_mul0_mul_op__insn + assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7719 \alu_mul0_mul_op__insn_type + assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7720 \alu_mul0_mul_op__is_32bit + assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7721 \alu_mul0_mul_op__is_signed + assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7722 \alu_mul0_mul_op__oe__oe + assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7723 \alu_mul0_mul_op__oe__ok + assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7724 \alu_mul0_mul_op__rc__ok + assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7725 \alu_mul0_mul_op__rc__rc + assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7726 \alu_mul0_mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -318757,48 +285282,48 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 1'0 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 1'0 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 1'0 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 1'0 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 1'0 + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7727 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7728 1'0 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7732 1'0 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7731 1'0 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7729 1'0 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7730 1'0 case - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7727 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7716 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7728 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7717 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7729 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7722 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7730 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7723 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7731 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7724 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7732 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7725 end sync always - update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 - update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 - update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 - update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7774 - update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 - update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 - update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 - update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 - update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 - update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 - update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 - update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 + update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[13:0]$7703 + update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7704 + update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7705 + update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7706 + update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7707 + update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7708 + update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7709 + update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7710 + update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7711 + update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7712 + update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7713 + update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7714 end - attribute \src "libresoc.v:152257.3-152278.6" - process $proc$libresoc.v:152257$7801 + attribute \src "libresoc.v:153001.3-153022.6" + process $proc$libresoc.v:153001$7733 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$7802 $2\data_r0__o$next[63:0]$7806 + assign $0\data_r0__o$next[63:0]$7734 $2\data_r0__o$next[63:0]$7738 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$7803 $3\data_r0__o_ok$next[0:0]$7808 - attribute \src "libresoc.v:152258.5-152258.29" + assign $0\data_r0__o_ok$next[0:0]$7735 $3\data_r0__o_ok$next[0:0]$7740 + attribute \src "libresoc.v:153002.5-153002.29" switch \initial - attribute \src "libresoc.v:152258.9-152258.17" + attribute \src "libresoc.v:153002.9-153002.17" case 1'1 case end @@ -318808,10 +285333,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$7805 $1\data_r0__o$next[63:0]$7804 } { \o_ok \alu_mul0_o } + assign { $1\data_r0__o_ok$next[0:0]$7737 $1\data_r0__o$next[63:0]$7736 } { \o_ok \alu_mul0_o } case - assign $1\data_r0__o$next[63:0]$7804 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$7805 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$7736 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$7737 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -318819,38 +285344,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$7807 $2\data_r0__o$next[63:0]$7806 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$7739 $2\data_r0__o$next[63:0]$7738 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$7806 $1\data_r0__o$next[63:0]$7804 - assign $2\data_r0__o_ok$next[0:0]$7807 $1\data_r0__o_ok$next[0:0]$7805 + assign $2\data_r0__o$next[63:0]$7738 $1\data_r0__o$next[63:0]$7736 + assign $2\data_r0__o_ok$next[0:0]$7739 $1\data_r0__o_ok$next[0:0]$7737 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$7808 1'0 + assign $3\data_r0__o_ok$next[0:0]$7740 1'0 case - assign $3\data_r0__o_ok$next[0:0]$7808 $2\data_r0__o_ok$next[0:0]$7807 + assign $3\data_r0__o_ok$next[0:0]$7740 $2\data_r0__o_ok$next[0:0]$7739 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$7802 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7803 + update \data_r0__o$next $0\data_r0__o$next[63:0]$7734 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7735 end - attribute \src "libresoc.v:152279.3-152300.6" - process $proc$libresoc.v:152279$7809 + attribute \src "libresoc.v:153023.3-153044.6" + process $proc$libresoc.v:153023$7741 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$7810 $2\data_r1__cr_a$next[3:0]$7814 + assign $0\data_r1__cr_a$next[3:0]$7742 $2\data_r1__cr_a$next[3:0]$7746 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$7811 $3\data_r1__cr_a_ok$next[0:0]$7816 - attribute \src "libresoc.v:152280.5-152280.29" + assign $0\data_r1__cr_a_ok$next[0:0]$7743 $3\data_r1__cr_a_ok$next[0:0]$7748 + attribute \src "libresoc.v:153024.5-153024.29" switch \initial - attribute \src "libresoc.v:152280.9-152280.17" + attribute \src "libresoc.v:153024.9-153024.17" case 1'1 case end @@ -318860,10 +285385,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$7813 $1\data_r1__cr_a$next[3:0]$7812 } { \cr_a_ok \alu_mul0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$7745 $1\data_r1__cr_a$next[3:0]$7744 } { \cr_a_ok \alu_mul0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$7812 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$7813 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$7744 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$7745 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -318871,38 +285396,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$7815 $2\data_r1__cr_a$next[3:0]$7814 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$7747 $2\data_r1__cr_a$next[3:0]$7746 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$7814 $1\data_r1__cr_a$next[3:0]$7812 - assign $2\data_r1__cr_a_ok$next[0:0]$7815 $1\data_r1__cr_a_ok$next[0:0]$7813 + assign $2\data_r1__cr_a$next[3:0]$7746 $1\data_r1__cr_a$next[3:0]$7744 + assign $2\data_r1__cr_a_ok$next[0:0]$7747 $1\data_r1__cr_a_ok$next[0:0]$7745 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$7816 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$7748 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$7816 $2\data_r1__cr_a_ok$next[0:0]$7815 + assign $3\data_r1__cr_a_ok$next[0:0]$7748 $2\data_r1__cr_a_ok$next[0:0]$7747 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7810 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7811 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7742 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7743 end - attribute \src "libresoc.v:152301.3-152322.6" - process $proc$libresoc.v:152301$7817 + attribute \src "libresoc.v:153045.3-153066.6" + process $proc$libresoc.v:153045$7749 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$7818 $2\data_r2__xer_ov$next[1:0]$7822 + assign $0\data_r2__xer_ov$next[1:0]$7750 $2\data_r2__xer_ov$next[1:0]$7754 assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$7819 $3\data_r2__xer_ov_ok$next[0:0]$7824 - attribute \src "libresoc.v:152302.5-152302.29" + assign $0\data_r2__xer_ov_ok$next[0:0]$7751 $3\data_r2__xer_ov_ok$next[0:0]$7756 + attribute \src "libresoc.v:153046.5-153046.29" switch \initial - attribute \src "libresoc.v:152302.9-152302.17" + attribute \src "libresoc.v:153046.9-153046.17" case 1'1 case end @@ -318912,10 +285437,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$7821 $1\data_r2__xer_ov$next[1:0]$7820 } { \xer_ov_ok \alu_mul0_xer_ov } + assign { $1\data_r2__xer_ov_ok$next[0:0]$7753 $1\data_r2__xer_ov$next[1:0]$7752 } { \xer_ov_ok \alu_mul0_xer_ov } case - assign $1\data_r2__xer_ov$next[1:0]$7820 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$7821 \data_r2__xer_ov_ok + assign $1\data_r2__xer_ov$next[1:0]$7752 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$7753 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -318923,38 +285448,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$7823 $2\data_r2__xer_ov$next[1:0]$7822 } 3'000 + assign { $2\data_r2__xer_ov_ok$next[0:0]$7755 $2\data_r2__xer_ov$next[1:0]$7754 } 3'000 case - assign $2\data_r2__xer_ov$next[1:0]$7822 $1\data_r2__xer_ov$next[1:0]$7820 - assign $2\data_r2__xer_ov_ok$next[0:0]$7823 $1\data_r2__xer_ov_ok$next[0:0]$7821 + assign $2\data_r2__xer_ov$next[1:0]$7754 $1\data_r2__xer_ov$next[1:0]$7752 + assign $2\data_r2__xer_ov_ok$next[0:0]$7755 $1\data_r2__xer_ov_ok$next[0:0]$7753 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$7824 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$7756 1'0 case - assign $3\data_r2__xer_ov_ok$next[0:0]$7824 $2\data_r2__xer_ov_ok$next[0:0]$7823 + assign $3\data_r2__xer_ov_ok$next[0:0]$7756 $2\data_r2__xer_ov_ok$next[0:0]$7755 end sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7818 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7819 + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7750 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7751 end - attribute \src "libresoc.v:152323.3-152344.6" - process $proc$libresoc.v:152323$7825 + attribute \src "libresoc.v:153067.3-153088.6" + process $proc$libresoc.v:153067$7757 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$7826 $2\data_r3__xer_so$next[0:0]$7830 + assign $0\data_r3__xer_so$next[0:0]$7758 $2\data_r3__xer_so$next[0:0]$7762 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$7827 $3\data_r3__xer_so_ok$next[0:0]$7832 - attribute \src "libresoc.v:152324.5-152324.29" + assign $0\data_r3__xer_so_ok$next[0:0]$7759 $3\data_r3__xer_so_ok$next[0:0]$7764 + attribute \src "libresoc.v:153068.5-153068.29" switch \initial - attribute \src "libresoc.v:152324.9-152324.17" + attribute \src "libresoc.v:153068.9-153068.17" case 1'1 case end @@ -318964,10 +285489,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$7829 $1\data_r3__xer_so$next[0:0]$7828 } { \xer_so_ok \alu_mul0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$7761 $1\data_r3__xer_so$next[0:0]$7760 } { \xer_so_ok \alu_mul0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$7828 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$7829 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$7760 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$7761 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -318975,32 +285500,32 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$7831 $2\data_r3__xer_so$next[0:0]$7830 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$7763 $2\data_r3__xer_so$next[0:0]$7762 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$7830 $1\data_r3__xer_so$next[0:0]$7828 - assign $2\data_r3__xer_so_ok$next[0:0]$7831 $1\data_r3__xer_so_ok$next[0:0]$7829 + assign $2\data_r3__xer_so$next[0:0]$7762 $1\data_r3__xer_so$next[0:0]$7760 + assign $2\data_r3__xer_so_ok$next[0:0]$7763 $1\data_r3__xer_so_ok$next[0:0]$7761 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$7832 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$7764 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$7832 $2\data_r3__xer_so_ok$next[0:0]$7831 + assign $3\data_r3__xer_so_ok$next[0:0]$7764 $2\data_r3__xer_so_ok$next[0:0]$7763 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7826 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7827 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7758 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7759 end - attribute \src "libresoc.v:152345.3-152354.6" - process $proc$libresoc.v:152345$7833 + attribute \src "libresoc.v:153089.3-153098.6" + process $proc$libresoc.v:153089$7765 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$7834 $1\src_r0$next[63:0]$7835 - attribute \src "libresoc.v:152346.5-152346.29" + assign $0\src_r0$next[63:0]$7766 $1\src_r0$next[63:0]$7767 + attribute \src "libresoc.v:153090.5-153090.29" switch \initial - attribute \src "libresoc.v:152346.9-152346.17" + attribute \src "libresoc.v:153090.9-153090.17" case 1'1 case end @@ -319009,21 +285534,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$7835 \src1_i + assign $1\src_r0$next[63:0]$7767 \src1_i case - assign $1\src_r0$next[63:0]$7835 \src_r0 + assign $1\src_r0$next[63:0]$7767 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$7834 + update \src_r0$next $0\src_r0$next[63:0]$7766 end - attribute \src "libresoc.v:152355.3-152364.6" - process $proc$libresoc.v:152355$7836 + attribute \src "libresoc.v:153099.3-153108.6" + process $proc$libresoc.v:153099$7768 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$7837 $1\src_r1$next[63:0]$7838 - attribute \src "libresoc.v:152356.5-152356.29" + assign $0\src_r1$next[63:0]$7769 $1\src_r1$next[63:0]$7770 + attribute \src "libresoc.v:153100.5-153100.29" switch \initial - attribute \src "libresoc.v:152356.9-152356.17" + attribute \src "libresoc.v:153100.9-153100.17" case 1'1 case end @@ -319032,21 +285557,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$7838 \src_or_imm + assign $1\src_r1$next[63:0]$7770 \src_or_imm case - assign $1\src_r1$next[63:0]$7838 \src_r1 + assign $1\src_r1$next[63:0]$7770 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$7837 + update \src_r1$next $0\src_r1$next[63:0]$7769 end - attribute \src "libresoc.v:152365.3-152374.6" - process $proc$libresoc.v:152365$7839 + attribute \src "libresoc.v:153109.3-153118.6" + process $proc$libresoc.v:153109$7771 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$7840 $1\src_r2$next[0:0]$7841 - attribute \src "libresoc.v:152366.5-152366.29" + assign $0\src_r2$next[0:0]$7772 $1\src_r2$next[0:0]$7773 + attribute \src "libresoc.v:153110.5-153110.29" switch \initial - attribute \src "libresoc.v:152366.9-152366.17" + attribute \src "libresoc.v:153110.9-153110.17" case 1'1 case end @@ -319055,21 +285580,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$7841 \src3_i + assign $1\src_r2$next[0:0]$7773 \src3_i case - assign $1\src_r2$next[0:0]$7841 \src_r2 + assign $1\src_r2$next[0:0]$7773 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$7840 + update \src_r2$next $0\src_r2$next[0:0]$7772 end - attribute \src "libresoc.v:152375.3-152383.6" - process $proc$libresoc.v:152375$7842 + attribute \src "libresoc.v:153119.3-153127.6" + process $proc$libresoc.v:153119$7774 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$7843 $1\alui_l_r_alui$next[0:0]$7844 - attribute \src "libresoc.v:152376.5-152376.29" + assign $0\alui_l_r_alui$next[0:0]$7775 $1\alui_l_r_alui$next[0:0]$7776 + attribute \src "libresoc.v:153120.5-153120.29" switch \initial - attribute \src "libresoc.v:152376.9-152376.17" + attribute \src "libresoc.v:153120.9-153120.17" case 1'1 case end @@ -319078,21 +285603,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$7844 1'1 + assign $1\alui_l_r_alui$next[0:0]$7776 1'1 case - assign $1\alui_l_r_alui$next[0:0]$7844 \$88 + assign $1\alui_l_r_alui$next[0:0]$7776 \$88 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7843 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7775 end - attribute \src "libresoc.v:152384.3-152392.6" - process $proc$libresoc.v:152384$7845 + attribute \src "libresoc.v:153128.3-153136.6" + process $proc$libresoc.v:153128$7777 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$7846 $1\alu_l_r_alu$next[0:0]$7847 - attribute \src "libresoc.v:152385.5-152385.29" + assign $0\alu_l_r_alu$next[0:0]$7778 $1\alu_l_r_alu$next[0:0]$7779 + attribute \src "libresoc.v:153129.5-153129.29" switch \initial - attribute \src "libresoc.v:152385.9-152385.17" + attribute \src "libresoc.v:153129.9-153129.17" case 1'1 case end @@ -319101,21 +285626,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$7847 1'1 + assign $1\alu_l_r_alu$next[0:0]$7779 1'1 case - assign $1\alu_l_r_alu$next[0:0]$7847 \$90 + assign $1\alu_l_r_alu$next[0:0]$7779 \$90 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7846 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7778 end - attribute \src "libresoc.v:152393.3-152402.6" - process $proc$libresoc.v:152393$7848 + attribute \src "libresoc.v:153137.3-153146.6" + process $proc$libresoc.v:153137$7780 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:152394.5-152394.29" + attribute \src "libresoc.v:153138.5-153138.29" switch \initial - attribute \src "libresoc.v:152394.9-152394.17" + attribute \src "libresoc.v:153138.9-153138.17" case 1'1 case end @@ -319131,14 +285656,14 @@ module \mul0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:152403.3-152412.6" - process $proc$libresoc.v:152403$7849 + attribute \src "libresoc.v:153147.3-153156.6" + process $proc$libresoc.v:153147$7781 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:152404.5-152404.29" + attribute \src "libresoc.v:153148.5-153148.29" switch \initial - attribute \src "libresoc.v:152404.9-152404.17" + attribute \src "libresoc.v:153148.9-153148.17" case 1'1 case end @@ -319154,14 +285679,14 @@ module \mul0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:152413.3-152422.6" - process $proc$libresoc.v:152413$7850 + attribute \src "libresoc.v:153157.3-153166.6" + process $proc$libresoc.v:153157$7782 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:152414.5-152414.29" + attribute \src "libresoc.v:153158.5-153158.29" switch \initial - attribute \src "libresoc.v:152414.9-152414.17" + attribute \src "libresoc.v:153158.9-153158.17" case 1'1 case end @@ -319177,14 +285702,14 @@ module \mul0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:152423.3-152432.6" - process $proc$libresoc.v:152423$7851 + attribute \src "libresoc.v:153167.3-153176.6" + process $proc$libresoc.v:153167$7783 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:152424.5-152424.29" + attribute \src "libresoc.v:153168.5-153168.29" switch \initial - attribute \src "libresoc.v:152424.9-152424.17" + attribute \src "libresoc.v:153168.9-153168.17" case 1'1 case end @@ -319200,14 +285725,14 @@ module \mul0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:152433.3-152441.6" - process $proc$libresoc.v:152433$7852 + attribute \src "libresoc.v:153177.3-153185.6" + process $proc$libresoc.v:153177$7784 assign { } { } assign { } { } - assign $0\prev_wr_go$next[3:0]$7853 $1\prev_wr_go$next[3:0]$7854 - attribute \src "libresoc.v:152434.5-152434.29" + assign $0\prev_wr_go$next[3:0]$7785 $1\prev_wr_go$next[3:0]$7786 + attribute \src "libresoc.v:153178.5-153178.29" switch \initial - attribute \src "libresoc.v:152434.9-152434.17" + attribute \src "libresoc.v:153178.9-153178.17" case 1'1 case end @@ -319216,73 +285741,73 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[3:0]$7854 4'0000 - case - assign $1\prev_wr_go$next[3:0]$7854 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7853 - end - connect \$100 $and$libresoc.v:151909$7641_Y - connect \$102 $and$libresoc.v:151910$7642_Y - connect \$104 $and$libresoc.v:151911$7643_Y - connect \$106 $and$libresoc.v:151912$7644_Y - connect \$108 $and$libresoc.v:151913$7645_Y - connect \$10 $and$libresoc.v:151914$7646_Y - connect \$110 $and$libresoc.v:151915$7647_Y - connect \$112 $and$libresoc.v:151916$7648_Y - connect \$114 $and$libresoc.v:151917$7649_Y - connect \$116 $and$libresoc.v:151918$7650_Y - connect \$118 $and$libresoc.v:151919$7651_Y - connect \$120 $and$libresoc.v:151920$7652_Y - connect \$12 $not$libresoc.v:151921$7653_Y - connect \$14 $and$libresoc.v:151922$7654_Y - connect \$16 $not$libresoc.v:151923$7655_Y - connect \$18 $and$libresoc.v:151924$7656_Y - connect \$20 $and$libresoc.v:151925$7657_Y - connect \$24 $not$libresoc.v:151926$7658_Y - connect \$26 $and$libresoc.v:151927$7659_Y - connect \$23 $reduce_or$libresoc.v:151928$7660_Y - connect \$22 $not$libresoc.v:151929$7661_Y - connect \$2 $and$libresoc.v:151930$7662_Y - connect \$30 $and$libresoc.v:151931$7663_Y - connect \$32 $reduce_or$libresoc.v:151932$7664_Y - connect \$34 $reduce_or$libresoc.v:151933$7665_Y - connect \$36 $or$libresoc.v:151934$7666_Y - connect \$38 $not$libresoc.v:151935$7667_Y - connect \$40 $and$libresoc.v:151936$7668_Y - connect \$42 $and$libresoc.v:151937$7669_Y - connect \$44 $eq$libresoc.v:151938$7670_Y - connect \$46 $and$libresoc.v:151939$7671_Y - connect \$48 $eq$libresoc.v:151940$7672_Y - connect \$50 $and$libresoc.v:151941$7673_Y - connect \$52 $and$libresoc.v:151942$7674_Y - connect \$54 $and$libresoc.v:151943$7675_Y - connect \$56 $or$libresoc.v:151944$7676_Y - connect \$58 $or$libresoc.v:151945$7677_Y - connect \$5 $not$libresoc.v:151946$7678_Y - connect \$60 $or$libresoc.v:151947$7679_Y - connect \$62 $or$libresoc.v:151948$7680_Y - connect \$64 $and$libresoc.v:151949$7681_Y - connect \$66 $and$libresoc.v:151950$7682_Y - connect \$68 $or$libresoc.v:151951$7683_Y - connect \$70 $and$libresoc.v:151952$7684_Y - connect \$72 $and$libresoc.v:151953$7685_Y - connect \$74 $and$libresoc.v:151954$7686_Y - connect \$76 $and$libresoc.v:151955$7687_Y - connect \$78 $ternary$libresoc.v:151956$7688_Y - connect \$7 $or$libresoc.v:151957$7689_Y - connect \$80 $ternary$libresoc.v:151958$7690_Y - connect \$82 $ternary$libresoc.v:151959$7691_Y - connect \$84 $ternary$libresoc.v:151960$7692_Y - connect \$86 $ternary$libresoc.v:151961$7693_Y - connect \$88 $and$libresoc.v:151962$7694_Y - connect \$4 $reduce_and$libresoc.v:151963$7695_Y - connect \$90 $and$libresoc.v:151964$7696_Y - connect \$92 $and$libresoc.v:151965$7697_Y - connect \$94 $not$libresoc.v:151966$7698_Y - connect \$96 $and$libresoc.v:151967$7699_Y - connect \$98 $not$libresoc.v:151968$7700_Y + assign $1\prev_wr_go$next[3:0]$7786 4'0000 + case + assign $1\prev_wr_go$next[3:0]$7786 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7785 + end + connect \$100 $and$libresoc.v:152653$7573_Y + connect \$102 $and$libresoc.v:152654$7574_Y + connect \$104 $and$libresoc.v:152655$7575_Y + connect \$106 $and$libresoc.v:152656$7576_Y + connect \$108 $and$libresoc.v:152657$7577_Y + connect \$10 $and$libresoc.v:152658$7578_Y + connect \$110 $and$libresoc.v:152659$7579_Y + connect \$112 $and$libresoc.v:152660$7580_Y + connect \$114 $and$libresoc.v:152661$7581_Y + connect \$116 $and$libresoc.v:152662$7582_Y + connect \$118 $and$libresoc.v:152663$7583_Y + connect \$120 $and$libresoc.v:152664$7584_Y + connect \$12 $not$libresoc.v:152665$7585_Y + connect \$14 $and$libresoc.v:152666$7586_Y + connect \$16 $not$libresoc.v:152667$7587_Y + connect \$18 $and$libresoc.v:152668$7588_Y + connect \$20 $and$libresoc.v:152669$7589_Y + connect \$24 $not$libresoc.v:152670$7590_Y + connect \$26 $and$libresoc.v:152671$7591_Y + connect \$23 $reduce_or$libresoc.v:152672$7592_Y + connect \$22 $not$libresoc.v:152673$7593_Y + connect \$2 $and$libresoc.v:152674$7594_Y + connect \$30 $and$libresoc.v:152675$7595_Y + connect \$32 $reduce_or$libresoc.v:152676$7596_Y + connect \$34 $reduce_or$libresoc.v:152677$7597_Y + connect \$36 $or$libresoc.v:152678$7598_Y + connect \$38 $not$libresoc.v:152679$7599_Y + connect \$40 $and$libresoc.v:152680$7600_Y + connect \$42 $and$libresoc.v:152681$7601_Y + connect \$44 $eq$libresoc.v:152682$7602_Y + connect \$46 $and$libresoc.v:152683$7603_Y + connect \$48 $eq$libresoc.v:152684$7604_Y + connect \$50 $and$libresoc.v:152685$7605_Y + connect \$52 $and$libresoc.v:152686$7606_Y + connect \$54 $and$libresoc.v:152687$7607_Y + connect \$56 $or$libresoc.v:152688$7608_Y + connect \$58 $or$libresoc.v:152689$7609_Y + connect \$5 $not$libresoc.v:152690$7610_Y + connect \$60 $or$libresoc.v:152691$7611_Y + connect \$62 $or$libresoc.v:152692$7612_Y + connect \$64 $and$libresoc.v:152693$7613_Y + connect \$66 $and$libresoc.v:152694$7614_Y + connect \$68 $or$libresoc.v:152695$7615_Y + connect \$70 $and$libresoc.v:152696$7616_Y + connect \$72 $and$libresoc.v:152697$7617_Y + connect \$74 $and$libresoc.v:152698$7618_Y + connect \$76 $and$libresoc.v:152699$7619_Y + connect \$78 $ternary$libresoc.v:152700$7620_Y + connect \$7 $or$libresoc.v:152701$7621_Y + connect \$80 $ternary$libresoc.v:152702$7622_Y + connect \$82 $ternary$libresoc.v:152703$7623_Y + connect \$84 $ternary$libresoc.v:152704$7624_Y + connect \$86 $ternary$libresoc.v:152705$7625_Y + connect \$88 $and$libresoc.v:152706$7626_Y + connect \$4 $reduce_and$libresoc.v:152707$7627_Y + connect \$90 $and$libresoc.v:152708$7628_Y + connect \$92 $and$libresoc.v:152709$7629_Y + connect \$94 $not$libresoc.v:152710$7630_Y + connect \$96 $and$libresoc.v:152711$7631_Y + connect \$98 $not$libresoc.v:152712$7632_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -319314,51 +285839,51 @@ module \mul0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:152476.1-152809.10" +attribute \src "libresoc.v:153220.1-153553.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" attribute \generator "nMigen" module \mul1 - attribute \src "libresoc.v:152776.18-152776.116" - wire $and$libresoc.v:152776$7895_Y - attribute \src "libresoc.v:152778.18-152778.116" - wire $and$libresoc.v:152778$7897_Y - attribute \src "libresoc.v:152779.18-152779.117" - wire $and$libresoc.v:152779$7898_Y - attribute \src "libresoc.v:152780.18-152780.117" - wire $and$libresoc.v:152780$7899_Y - attribute \src "libresoc.v:152783.18-152783.95" - wire width 65 $extend$libresoc.v:152783$7902_Y - attribute \src "libresoc.v:152784.18-152784.91" - wire width 65 $extend$libresoc.v:152784$7904_Y - attribute \src "libresoc.v:152786.18-152786.95" - wire width 65 $extend$libresoc.v:152786$7907_Y - attribute \src "libresoc.v:152787.18-152787.91" - wire width 65 $extend$libresoc.v:152787$7909_Y - attribute \src "libresoc.v:152783.18-152783.95" - wire width 65 $neg$libresoc.v:152783$7903_Y - attribute \src "libresoc.v:152786.18-152786.95" - wire width 65 $neg$libresoc.v:152786$7908_Y - attribute \src "libresoc.v:152784.18-152784.91" - wire width 65 $pos$libresoc.v:152784$7905_Y - attribute \src "libresoc.v:152787.18-152787.91" - wire width 65 $pos$libresoc.v:152787$7910_Y - attribute \src "libresoc.v:152775.18-152775.125" - wire $ternary$libresoc.v:152775$7894_Y - attribute \src "libresoc.v:152777.18-152777.125" - wire $ternary$libresoc.v:152777$7896_Y - attribute \src "libresoc.v:152785.18-152785.112" - wire width 65 $ternary$libresoc.v:152785$7906_Y - attribute \src "libresoc.v:152788.18-152788.112" - wire width 65 $ternary$libresoc.v:152788$7911_Y - attribute \src "libresoc.v:152789.18-152789.116" - wire width 32 $ternary$libresoc.v:152789$7912_Y - attribute \src "libresoc.v:152790.18-152790.116" - wire width 32 $ternary$libresoc.v:152790$7913_Y - attribute \src "libresoc.v:152781.18-152781.106" - wire $xor$libresoc.v:152781$7900_Y - attribute \src "libresoc.v:152782.18-152782.110" - wire $xor$libresoc.v:152782$7901_Y + attribute \src "libresoc.v:153520.18-153520.116" + wire $and$libresoc.v:153520$7827_Y + attribute \src "libresoc.v:153522.18-153522.116" + wire $and$libresoc.v:153522$7829_Y + attribute \src "libresoc.v:153523.18-153523.117" + wire $and$libresoc.v:153523$7830_Y + attribute \src "libresoc.v:153524.18-153524.117" + wire $and$libresoc.v:153524$7831_Y + attribute \src "libresoc.v:153527.18-153527.95" + wire width 65 $extend$libresoc.v:153527$7834_Y + attribute \src "libresoc.v:153528.18-153528.91" + wire width 65 $extend$libresoc.v:153528$7836_Y + attribute \src "libresoc.v:153530.18-153530.95" + wire width 65 $extend$libresoc.v:153530$7839_Y + attribute \src "libresoc.v:153531.18-153531.91" + wire width 65 $extend$libresoc.v:153531$7841_Y + attribute \src "libresoc.v:153527.18-153527.95" + wire width 65 $neg$libresoc.v:153527$7835_Y + attribute \src "libresoc.v:153530.18-153530.95" + wire width 65 $neg$libresoc.v:153530$7840_Y + attribute \src "libresoc.v:153528.18-153528.91" + wire width 65 $pos$libresoc.v:153528$7837_Y + attribute \src "libresoc.v:153531.18-153531.91" + wire width 65 $pos$libresoc.v:153531$7842_Y + attribute \src "libresoc.v:153519.18-153519.125" + wire $ternary$libresoc.v:153519$7826_Y + attribute \src "libresoc.v:153521.18-153521.125" + wire $ternary$libresoc.v:153521$7828_Y + attribute \src "libresoc.v:153529.18-153529.112" + wire width 65 $ternary$libresoc.v:153529$7838_Y + attribute \src "libresoc.v:153532.18-153532.112" + wire width 65 $ternary$libresoc.v:153532$7843_Y + attribute \src "libresoc.v:153533.18-153533.116" + wire width 32 $ternary$libresoc.v:153533$7844_Y + attribute \src "libresoc.v:153534.18-153534.116" + wire width 32 $ternary$libresoc.v:153534$7845_Y + attribute \src "libresoc.v:153525.18-153525.106" + wire $xor$libresoc.v:153525$7832_Y + attribute \src "libresoc.v:153526.18-153526.110" + wire $xor$libresoc.v:153526$7833_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" @@ -319658,7 +286183,7 @@ module \mul1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 31 \xer_so$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $and $and$libresoc.v:152776$7895 + cell $and $and$libresoc.v:153520$7827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319666,10 +286191,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$17 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:152776$7895_Y + connect \Y $and$libresoc.v:153520$7827_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $and $and$libresoc.v:152778$7897 + cell $and $and$libresoc.v:153522$7829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319677,10 +286202,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$21 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:152778$7897_Y + connect \Y $and$libresoc.v:153522$7829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" - cell $and $and$libresoc.v:152779$7898 + cell $and $and$libresoc.v:153523$7830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319688,10 +286213,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \ra [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:152779$7898_Y + connect \Y $and$libresoc.v:153523$7830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" - cell $and $and$libresoc.v:152780$7899 + cell $and $and$libresoc.v:153524$7831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319699,122 +286224,122 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \rb [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:152780$7899_Y + connect \Y $and$libresoc.v:153524$7831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $pos $extend$libresoc.v:152783$7902 + cell $pos $extend$libresoc.v:153527$7834 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:152783$7902_Y + connect \Y $extend$libresoc.v:153527$7834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:152784$7904 + cell $pos $extend$libresoc.v:153528$7836 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:152784$7904_Y + connect \Y $extend$libresoc.v:153528$7836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $pos $extend$libresoc.v:152786$7907 + cell $pos $extend$libresoc.v:153530$7839 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:152786$7907_Y + connect \Y $extend$libresoc.v:153530$7839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:152787$7909 + cell $pos $extend$libresoc.v:153531$7841 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:152787$7909_Y + connect \Y $extend$libresoc.v:153531$7841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $neg $neg$libresoc.v:152783$7903 + cell $neg $neg$libresoc.v:153527$7835 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:152783$7902_Y - connect \Y $neg$libresoc.v:152783$7903_Y + connect \A $extend$libresoc.v:153527$7834_Y + connect \Y $neg$libresoc.v:153527$7835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $neg $neg$libresoc.v:152786$7908 + cell $neg $neg$libresoc.v:153530$7840 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:152786$7907_Y - connect \Y $neg$libresoc.v:152786$7908_Y + connect \A $extend$libresoc.v:153530$7839_Y + connect \Y $neg$libresoc.v:153530$7840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:152784$7905 + cell $pos $pos$libresoc.v:153528$7837 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:152784$7904_Y - connect \Y $pos$libresoc.v:152784$7905_Y + connect \A $extend$libresoc.v:153528$7836_Y + connect \Y $pos$libresoc.v:153528$7837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:152787$7910 + cell $pos $pos$libresoc.v:153531$7842 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:152787$7909_Y - connect \Y $pos$libresoc.v:152787$7910_Y + connect \A $extend$libresoc.v:153531$7841_Y + connect \Y $pos$libresoc.v:153531$7842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $mux $ternary$libresoc.v:152775$7894 + cell $mux $ternary$libresoc.v:153519$7826 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:152775$7894_Y + connect \Y $ternary$libresoc.v:153519$7826_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $mux $ternary$libresoc.v:152777$7896 + cell $mux $ternary$libresoc.v:153521$7828 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:152777$7896_Y + connect \Y $ternary$libresoc.v:153521$7828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $mux $ternary$libresoc.v:152785$7906 + cell $mux $ternary$libresoc.v:153529$7838 parameter \WIDTH 65 connect \A \$36 connect \B \$34 connect \S \sign_a - connect \Y $ternary$libresoc.v:152785$7906_Y + connect \Y $ternary$libresoc.v:153529$7838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $mux $ternary$libresoc.v:152788$7911 + cell $mux $ternary$libresoc.v:153532$7843 parameter \WIDTH 65 connect \A \$43 connect \B \$41 connect \S \sign_b - connect \Y $ternary$libresoc.v:152788$7911_Y + connect \Y $ternary$libresoc.v:153532$7843_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:152789$7912 + cell $mux $ternary$libresoc.v:153533$7844 parameter \WIDTH 32 connect \A \abs_a [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:152789$7912_Y + connect \Y $ternary$libresoc.v:153533$7844_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:152790$7913 + cell $mux $ternary$libresoc.v:153534$7845 parameter \WIDTH 32 connect \A \abs_b [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:152790$7913_Y + connect \Y $ternary$libresoc.v:153534$7845_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" - cell $xor $xor$libresoc.v:152781$7900 + cell $xor $xor$libresoc.v:153525$7832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319822,10 +286347,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign_a connect \B \sign_b - connect \Y $xor$libresoc.v:152781$7900_Y + connect \Y $xor$libresoc.v:153525$7832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" - cell $xor $xor$libresoc.v:152782$7901 + cell $xor $xor$libresoc.v:153526$7833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319833,24 +286358,24 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign32_a connect \B \sign32_b - connect \Y $xor$libresoc.v:152782$7901_Y - end - connect \$17 $ternary$libresoc.v:152775$7894_Y - connect \$19 $and$libresoc.v:152776$7895_Y - connect \$21 $ternary$libresoc.v:152777$7896_Y - connect \$23 $and$libresoc.v:152778$7897_Y - connect \$25 $and$libresoc.v:152779$7898_Y - connect \$27 $and$libresoc.v:152780$7899_Y - connect \$29 $xor$libresoc.v:152781$7900_Y - connect \$31 $xor$libresoc.v:152782$7901_Y - connect \$34 $neg$libresoc.v:152783$7903_Y - connect \$36 $pos$libresoc.v:152784$7905_Y - connect \$38 $ternary$libresoc.v:152785$7906_Y - connect \$41 $neg$libresoc.v:152786$7908_Y - connect \$43 $pos$libresoc.v:152787$7910_Y - connect \$45 $ternary$libresoc.v:152788$7911_Y - connect \$47 $ternary$libresoc.v:152789$7912_Y - connect \$49 $ternary$libresoc.v:152790$7913_Y + connect \Y $xor$libresoc.v:153526$7833_Y + end + connect \$17 $ternary$libresoc.v:153519$7826_Y + connect \$19 $and$libresoc.v:153520$7827_Y + connect \$21 $ternary$libresoc.v:153521$7828_Y + connect \$23 $and$libresoc.v:153522$7829_Y + connect \$25 $and$libresoc.v:153523$7830_Y + connect \$27 $and$libresoc.v:153524$7831_Y + connect \$29 $xor$libresoc.v:153525$7832_Y + connect \$31 $xor$libresoc.v:153526$7833_Y + connect \$34 $neg$libresoc.v:153527$7835_Y + connect \$36 $pos$libresoc.v:153528$7837_Y + connect \$38 $ternary$libresoc.v:153529$7838_Y + connect \$41 $neg$libresoc.v:153530$7840_Y + connect \$43 $pos$libresoc.v:153531$7842_Y + connect \$45 $ternary$libresoc.v:153532$7843_Y + connect \$47 $ternary$libresoc.v:153533$7844_Y + connect \$49 $ternary$libresoc.v:153534$7845_Y connect \$33 \$38 connect \$40 \$45 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } @@ -319870,17 +286395,17 @@ module \mul1 connect \sign_a \$19 connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:152813.1-153076.10" +attribute \src "libresoc.v:153557.1-153820.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" attribute \generator "nMigen" module \mul2 - attribute \src "libresoc.v:153069.18-153069.98" - wire width 129 $extend$libresoc.v:153069$7915_Y - attribute \src "libresoc.v:153068.18-153068.99" - wire width 128 $mul$libresoc.v:153068$7914_Y - attribute \src "libresoc.v:153069.18-153069.98" - wire width 129 $pos$libresoc.v:153069$7916_Y + attribute \src "libresoc.v:153813.18-153813.98" + wire width 129 $extend$libresoc.v:153813$7847_Y + attribute \src "libresoc.v:153812.18-153812.99" + wire width 128 $mul$libresoc.v:153812$7846_Y + attribute \src "libresoc.v:153813.18-153813.98" + wire width 129 $pos$libresoc.v:153813$7848_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" wire width 129 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" @@ -320136,15 +286661,15 @@ module \mul2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 32 \xer_so$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $extend$libresoc.v:153069$7915 + cell $pos $extend$libresoc.v:153813$7847 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 129 connect \A \$18 - connect \Y $extend$libresoc.v:153069$7915_Y + connect \Y $extend$libresoc.v:153813$7847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $mul $mul$libresoc.v:153068$7914 + cell $mul $mul$libresoc.v:153812$7846 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -320152,18 +286677,18 @@ module \mul2 parameter \Y_WIDTH 128 connect \A \ra connect \B \rb - connect \Y $mul$libresoc.v:153068$7914_Y + connect \Y $mul$libresoc.v:153812$7846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $pos$libresoc.v:153069$7916 + cell $pos $pos$libresoc.v:153813$7848 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 129 - connect \A $extend$libresoc.v:153069$7915_Y - connect \Y $pos$libresoc.v:153069$7916_Y + connect \A $extend$libresoc.v:153813$7847_Y + connect \Y $pos$libresoc.v:153813$7848_Y end - connect \$18 $mul$libresoc.v:153068$7914_Y - connect \$17 $pos$libresoc.v:153069$7916_Y + connect \$18 $mul$libresoc.v:153812$7846_Y + connect \$17 $pos$libresoc.v:153813$7848_Y connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid connect \xer_so$14 \xer_so @@ -320171,65 +286696,65 @@ module \mul2 connect \neg_res$15 \neg_res connect \o \$17 end -attribute \src "libresoc.v:153080.1-153465.10" +attribute \src "libresoc.v:153824.1-154233.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" attribute \generator "nMigen" module \mul3 - attribute \src "libresoc.v:153081.7-153081.20" + attribute \src "libresoc.v:153825.7-153825.20" wire $0\initial[0:0] - attribute \src "libresoc.v:153418.3-153436.6" + attribute \src "libresoc.v:154162.3-154188.6" wire $0\mul_ov[0:0] - attribute \src "libresoc.v:153380.3-153398.6" - wire width 64 $0\o$14[63:0]$7933 - attribute \src "libresoc.v:153399.3-153417.6" + attribute \src "libresoc.v:154124.3-154142.6" + wire width 64 $0\o$14[63:0]$7865 + attribute \src "libresoc.v:154143.3-154161.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:153437.3-153447.6" + attribute \src "libresoc.v:154189.3-154207.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:153448.3-153458.6" + attribute \src "libresoc.v:154208.3-154226.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:153418.3-153436.6" + attribute \src "libresoc.v:154162.3-154188.6" wire $1\mul_ov[0:0] - attribute \src "libresoc.v:153380.3-153398.6" - wire width 64 $1\o$14[63:0]$7934 - attribute \src "libresoc.v:153399.3-153417.6" + attribute \src "libresoc.v:154124.3-154142.6" + wire width 64 $1\o$14[63:0]$7866 + attribute \src "libresoc.v:154143.3-154161.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:153437.3-153447.6" + attribute \src "libresoc.v:154189.3-154207.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:153448.3-153458.6" + attribute \src "libresoc.v:154208.3-154226.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:153418.3-153436.6" + attribute \src "libresoc.v:154162.3-154188.6" wire $2\mul_ov[0:0] - attribute \src "libresoc.v:153374.18-153374.104" - wire $and$libresoc.v:153374$7925_Y - attribute \src "libresoc.v:153378.18-153378.104" - wire $and$libresoc.v:153378$7929_Y - attribute \src "libresoc.v:153368.18-153368.95" - wire width 130 $extend$libresoc.v:153368$7917_Y - attribute \src "libresoc.v:153369.18-153369.90" - wire width 130 $extend$libresoc.v:153369$7919_Y - attribute \src "libresoc.v:153379.18-153379.95" - wire width 2 $extend$libresoc.v:153379$7930_Y - attribute \src "libresoc.v:153368.18-153368.95" - wire width 130 $neg$libresoc.v:153368$7918_Y - attribute \src "libresoc.v:153373.18-153373.98" - wire $not$libresoc.v:153373$7924_Y - attribute \src "libresoc.v:153377.18-153377.98" - wire $not$libresoc.v:153377$7928_Y - attribute \src "libresoc.v:153369.18-153369.90" - wire width 130 $pos$libresoc.v:153369$7920_Y - attribute \src "libresoc.v:153379.18-153379.95" - wire width 2 $pos$libresoc.v:153379$7931_Y - attribute \src "libresoc.v:153372.18-153372.106" - wire $reduce_and$libresoc.v:153372$7923_Y - attribute \src "libresoc.v:153376.18-153376.107" - wire $reduce_and$libresoc.v:153376$7927_Y - attribute \src "libresoc.v:153371.18-153371.106" - wire $reduce_or$libresoc.v:153371$7922_Y - attribute \src "libresoc.v:153375.18-153375.107" - wire $reduce_or$libresoc.v:153375$7926_Y - attribute \src "libresoc.v:153370.18-153370.114" - wire width 130 $ternary$libresoc.v:153370$7921_Y + attribute \src "libresoc.v:154118.18-154118.104" + wire $and$libresoc.v:154118$7857_Y + attribute \src "libresoc.v:154122.18-154122.104" + wire $and$libresoc.v:154122$7861_Y + attribute \src "libresoc.v:154112.18-154112.95" + wire width 130 $extend$libresoc.v:154112$7849_Y + attribute \src "libresoc.v:154113.18-154113.90" + wire width 130 $extend$libresoc.v:154113$7851_Y + attribute \src "libresoc.v:154123.18-154123.95" + wire width 2 $extend$libresoc.v:154123$7862_Y + attribute \src "libresoc.v:154112.18-154112.95" + wire width 130 $neg$libresoc.v:154112$7850_Y + attribute \src "libresoc.v:154117.18-154117.98" + wire $not$libresoc.v:154117$7856_Y + attribute \src "libresoc.v:154121.18-154121.98" + wire $not$libresoc.v:154121$7860_Y + attribute \src "libresoc.v:154113.18-154113.90" + wire width 130 $pos$libresoc.v:154113$7852_Y + attribute \src "libresoc.v:154123.18-154123.95" + wire width 2 $pos$libresoc.v:154123$7863_Y + attribute \src "libresoc.v:154116.18-154116.106" + wire $reduce_and$libresoc.v:154116$7855_Y + attribute \src "libresoc.v:154120.18-154120.107" + wire $reduce_and$libresoc.v:154120$7859_Y + attribute \src "libresoc.v:154115.18-154115.106" + wire $reduce_or$libresoc.v:154115$7854_Y + attribute \src "libresoc.v:154119.18-154119.107" + wire $reduce_or$libresoc.v:154119$7858_Y + attribute \src "libresoc.v:154114.18-154114.114" + wire width 130 $ternary$libresoc.v:154114$7853_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" wire width 130 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" @@ -320256,7 +286781,7 @@ module \mul3 wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \$39 - attribute \src "libresoc.v:153081.7-153081.15" + attribute \src "libresoc.v:153825.7-153825.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" wire \is_32bit @@ -320500,22 +287025,22 @@ module \mul3 wire input 15 \neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 input 13 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 29 \o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 30 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 31 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 32 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 14 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \xer_so$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 34 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $and $and$libresoc.v:153374$7925 + cell $and $and$libresoc.v:154118$7857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -320523,10 +287048,10 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $and$libresoc.v:153374$7925_Y + connect \Y $and$libresoc.v:154118$7857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $and $and$libresoc.v:153378$7929 + cell $and $and$libresoc.v:154122$7861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -320534,128 +287059,128 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:153378$7929_Y + connect \Y $and$libresoc.v:154122$7861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $pos $extend$libresoc.v:153368$7917 + cell $pos $extend$libresoc.v:154112$7849 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:153368$7917_Y + connect \Y $extend$libresoc.v:154112$7849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:153369$7919 + cell $pos $extend$libresoc.v:154113$7851 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:153369$7919_Y + connect \Y $extend$libresoc.v:154113$7851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:153379$7930 + cell $pos $extend$libresoc.v:154123$7862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 connect \A \xer_so - connect \Y $extend$libresoc.v:153379$7930_Y + connect \Y $extend$libresoc.v:154123$7862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $neg $neg$libresoc.v:153368$7918 + cell $neg $neg$libresoc.v:154112$7850 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:153368$7917_Y - connect \Y $neg$libresoc.v:153368$7918_Y + connect \A $extend$libresoc.v:154112$7849_Y + connect \Y $neg$libresoc.v:154112$7850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $not $not$libresoc.v:153373$7924 + cell $not $not$libresoc.v:154117$7856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $not$libresoc.v:153373$7924_Y + connect \Y $not$libresoc.v:154117$7856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $not $not$libresoc.v:153377$7928 + cell $not $not$libresoc.v:154121$7860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$34 - connect \Y $not$libresoc.v:153377$7928_Y + connect \Y $not$libresoc.v:154121$7860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:153369$7920 + cell $pos $pos$libresoc.v:154113$7852 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:153369$7919_Y - connect \Y $pos$libresoc.v:153369$7920_Y + connect \A $extend$libresoc.v:154113$7851_Y + connect \Y $pos$libresoc.v:154113$7852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:153379$7931 + cell $pos $pos$libresoc.v:154123$7863 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:153379$7930_Y - connect \Y $pos$libresoc.v:153379$7931_Y + connect \A $extend$libresoc.v:154123$7862_Y + connect \Y $pos$libresoc.v:154123$7863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_and $reduce_and$libresoc.v:153372$7923 + cell $reduce_and $reduce_and$libresoc.v:154116$7855 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_and$libresoc.v:153372$7923_Y + connect \Y $reduce_and$libresoc.v:154116$7855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_and $reduce_and$libresoc.v:153376$7927 + cell $reduce_and $reduce_and$libresoc.v:154120$7859 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_and$libresoc.v:153376$7927_Y + connect \Y $reduce_and$libresoc.v:154120$7859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_or $reduce_or$libresoc.v:153371$7922 + cell $reduce_or $reduce_or$libresoc.v:154115$7854 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_or$libresoc.v:153371$7922_Y + connect \Y $reduce_or$libresoc.v:154115$7854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_or $reduce_or$libresoc.v:153375$7926 + cell $reduce_or $reduce_or$libresoc.v:154119$7858 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_or$libresoc.v:153375$7926_Y + connect \Y $reduce_or$libresoc.v:154119$7858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $mux $ternary$libresoc.v:153370$7921 + cell $mux $ternary$libresoc.v:154114$7853 parameter \WIDTH 130 connect \A \$19 connect \B \$17 connect \S \neg_res - connect \Y $ternary$libresoc.v:153370$7921_Y + connect \Y $ternary$libresoc.v:154114$7853_Y end - attribute \src "libresoc.v:153081.7-153081.20" - process $proc$libresoc.v:153081$7939 + attribute \src "libresoc.v:153825.7-153825.20" + process $proc$libresoc.v:153825$7871 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:153380.3-153398.6" - process $proc$libresoc.v:153380$7932 + attribute \src "libresoc.v:154124.3-154142.6" + process $proc$libresoc.v:154124$7864 assign { } { } assign { } { } - assign $0\o$14[63:0]$7933 $1\o$14[63:0]$7934 - attribute \src "libresoc.v:153381.5-153381.29" + assign $0\o$14[63:0]$7865 $1\o$14[63:0]$7866 + attribute \src "libresoc.v:154125.5-154125.29" switch \initial - attribute \src "libresoc.v:153381.9-153381.17" + attribute \src "libresoc.v:154125.9-154125.17" case 1'1 case end @@ -320664,29 +287189,29 @@ module \mul3 attribute \src "libresoc.v:0.0-0.0" case 7'0110100 assign { } { } - assign $1\o$14[63:0]$7934 { \mul_o [63:32] \mul_o [63:32] } + assign $1\o$14[63:0]$7866 { \mul_o [63:32] \mul_o [63:32] } attribute \src "libresoc.v:0.0-0.0" case 7'0110011 assign { } { } - assign $1\o$14[63:0]$7934 \mul_o [127:64] + assign $1\o$14[63:0]$7866 \mul_o [127:64] attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } - assign $1\o$14[63:0]$7934 \mul_o [63:0] + assign $1\o$14[63:0]$7866 \mul_o [63:0] case - assign $1\o$14[63:0]$7934 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\o$14[63:0]$7866 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \o$14 $0\o$14[63:0]$7933 + update \o$14 $0\o$14[63:0]$7865 end - attribute \src "libresoc.v:153399.3-153417.6" - process $proc$libresoc.v:153399$7935 + attribute \src "libresoc.v:154143.3-154161.6" + process $proc$libresoc.v:154143$7867 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:153400.5-153400.29" + attribute \src "libresoc.v:154144.5-154144.29" switch \initial - attribute \src "libresoc.v:153400.9-153400.17" + attribute \src "libresoc.v:154144.9-154144.17" case 1'1 case end @@ -320710,20 +287235,26 @@ module \mul3 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:153418.3-153436.6" - process $proc$libresoc.v:153418$7936 + attribute \src "libresoc.v:154162.3-154188.6" + process $proc$libresoc.v:154162$7868 assign { } { } assign { } { } assign $0\mul_ov[0:0] $1\mul_ov[0:0] - attribute \src "libresoc.v:153419.5-153419.29" + attribute \src "libresoc.v:154163.5-154163.29" switch \initial - attribute \src "libresoc.v:153419.9-153419.17" + attribute \src "libresoc.v:154163.9-154163.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0110100 + assign $1\mul_ov[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 + assign $1\mul_ov[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } assign $1\mul_ov[0:0] $2\mul_ov[0:0] @@ -320744,20 +287275,26 @@ module \mul3 sync always update \mul_ov $0\mul_ov[0:0] end - attribute \src "libresoc.v:153437.3-153447.6" - process $proc$libresoc.v:153437$7937 + attribute \src "libresoc.v:154189.3-154207.6" + process $proc$libresoc.v:154189$7869 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:153438.5-153438.29" + attribute \src "libresoc.v:154190.5-154190.29" switch \initial - attribute \src "libresoc.v:153438.9-153438.17" + attribute \src "libresoc.v:154190.9-154190.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0110100 + assign $1\xer_ov[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 + assign $1\xer_ov[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } assign $1\xer_ov[1:0] { \mul_ov \mul_ov } @@ -320767,20 +287304,26 @@ module \mul3 sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:153448.3-153458.6" - process $proc$libresoc.v:153448$7938 + attribute \src "libresoc.v:154208.3-154226.6" + process $proc$libresoc.v:154208$7870 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:153449.5-153449.29" + attribute \src "libresoc.v:154209.5-154209.29" switch \initial - attribute \src "libresoc.v:153449.9-153449.17" + attribute \src "libresoc.v:154209.9-154209.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0110100 + assign $1\xer_ov_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 + assign $1\xer_ov_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } assign $1\xer_ov_ok[0:0] 1'1 @@ -320790,18 +287333,18 @@ module \mul3 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$17 $neg$libresoc.v:153368$7918_Y - connect \$19 $pos$libresoc.v:153369$7920_Y - connect \$21 $ternary$libresoc.v:153370$7921_Y - connect \$23 $reduce_or$libresoc.v:153371$7922_Y - connect \$26 $reduce_and$libresoc.v:153372$7923_Y - connect \$25 $not$libresoc.v:153373$7924_Y - connect \$29 $and$libresoc.v:153374$7925_Y - connect \$31 $reduce_or$libresoc.v:153375$7926_Y - connect \$34 $reduce_and$libresoc.v:153376$7927_Y - connect \$33 $not$libresoc.v:153377$7928_Y - connect \$37 $and$libresoc.v:153378$7929_Y - connect \$39 $pos$libresoc.v:153379$7931_Y + connect \$17 $neg$libresoc.v:154112$7850_Y + connect \$19 $pos$libresoc.v:154113$7852_Y + connect \$21 $ternary$libresoc.v:154114$7853_Y + connect \$23 $reduce_or$libresoc.v:154115$7854_Y + connect \$26 $reduce_and$libresoc.v:154116$7855_Y + connect \$25 $not$libresoc.v:154117$7856_Y + connect \$29 $and$libresoc.v:154118$7857_Y + connect \$31 $reduce_or$libresoc.v:154119$7858_Y + connect \$34 $reduce_and$libresoc.v:154120$7859_Y + connect \$33 $not$libresoc.v:154121$7860_Y + connect \$37 $and$libresoc.v:154122$7861_Y + connect \$39 $pos$libresoc.v:154123$7863_Y connect \$16 \$21 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -320809,188 +287352,188 @@ module \mul3 connect \mul_o \$21 [128:0] connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:153469.1-154686.10" +attribute \src "libresoc.v:154237.1-155454.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" attribute \generator "nMigen" module \mul_pipe1 - attribute \src "libresoc.v:153470.7-153470.20" + attribute \src "libresoc.v:154238.7-154238.20" wire $0\initial[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire width 14 $0\mul_op__fn_unit$next[13:0]$7968 - attribute \src "libresoc.v:154428.3-154429.47" + attribute \src "libresoc.v:155331.3-155366.6" + wire width 14 $0\mul_op__fn_unit$next[13:0]$7900 + attribute \src "libresoc.v:155196.3-155197.47" wire width 14 $0\mul_op__fn_unit[13:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire width 64 $0\mul_op__imm_data__data$next[63:0]$7969 - attribute \src "libresoc.v:154430.3-154431.61" + attribute \src "libresoc.v:155331.3-155366.6" + wire width 64 $0\mul_op__imm_data__data$next[63:0]$7901 + attribute \src "libresoc.v:155198.3-155199.61" wire width 64 $0\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $0\mul_op__imm_data__ok$next[0:0]$7970 - attribute \src "libresoc.v:154432.3-154433.57" + attribute \src "libresoc.v:155331.3-155366.6" + wire $0\mul_op__imm_data__ok$next[0:0]$7902 + attribute \src "libresoc.v:155200.3-155201.57" wire $0\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire width 32 $0\mul_op__insn$next[31:0]$7971 - attribute \src "libresoc.v:154448.3-154449.41" + attribute \src "libresoc.v:155331.3-155366.6" + wire width 32 $0\mul_op__insn$next[31:0]$7903 + attribute \src "libresoc.v:155216.3-155217.41" wire width 32 $0\mul_op__insn[31:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire width 7 $0\mul_op__insn_type$next[6:0]$7972 - attribute \src "libresoc.v:154426.3-154427.51" + attribute \src "libresoc.v:155331.3-155366.6" + wire width 7 $0\mul_op__insn_type$next[6:0]$7904 + attribute \src "libresoc.v:155194.3-155195.51" wire width 7 $0\mul_op__insn_type[6:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $0\mul_op__is_32bit$next[0:0]$7973 - attribute \src "libresoc.v:154444.3-154445.49" + attribute \src "libresoc.v:155331.3-155366.6" + wire $0\mul_op__is_32bit$next[0:0]$7905 + attribute \src "libresoc.v:155212.3-155213.49" wire $0\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $0\mul_op__is_signed$next[0:0]$7974 - attribute \src "libresoc.v:154446.3-154447.51" + attribute \src "libresoc.v:155331.3-155366.6" + wire $0\mul_op__is_signed$next[0:0]$7906 + attribute \src "libresoc.v:155214.3-155215.51" wire $0\mul_op__is_signed[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $0\mul_op__oe__oe$next[0:0]$7975 - attribute \src "libresoc.v:154438.3-154439.45" + attribute \src "libresoc.v:155331.3-155366.6" + wire $0\mul_op__oe__oe$next[0:0]$7907 + attribute \src "libresoc.v:155206.3-155207.45" wire $0\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $0\mul_op__oe__ok$next[0:0]$7976 - attribute \src "libresoc.v:154440.3-154441.45" + attribute \src "libresoc.v:155331.3-155366.6" + wire $0\mul_op__oe__ok$next[0:0]$7908 + attribute \src "libresoc.v:155208.3-155209.45" wire $0\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $0\mul_op__rc__ok$next[0:0]$7977 - attribute \src "libresoc.v:154436.3-154437.45" + attribute \src "libresoc.v:155331.3-155366.6" + wire $0\mul_op__rc__ok$next[0:0]$7909 + attribute \src "libresoc.v:155204.3-155205.45" wire $0\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $0\mul_op__rc__rc$next[0:0]$7978 - attribute \src "libresoc.v:154434.3-154435.45" + attribute \src "libresoc.v:155331.3-155366.6" + wire $0\mul_op__rc__rc$next[0:0]$7910 + attribute \src "libresoc.v:155202.3-155203.45" wire $0\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $0\mul_op__write_cr0$next[0:0]$7979 - attribute \src "libresoc.v:154442.3-154443.51" + attribute \src "libresoc.v:155331.3-155366.6" + wire $0\mul_op__write_cr0$next[0:0]$7911 + attribute \src "libresoc.v:155210.3-155211.51" wire $0\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:154550.3-154562.6" - wire width 2 $0\muxid$next[1:0]$7965 - attribute \src "libresoc.v:154450.3-154451.27" + attribute \src "libresoc.v:155318.3-155330.6" + wire width 2 $0\muxid$next[1:0]$7897 + attribute \src "libresoc.v:155218.3-155219.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:154638.3-154650.6" - wire $0\neg_res$next[0:0]$8008 - attribute \src "libresoc.v:154651.3-154663.6" - wire $0\neg_res32$next[0:0]$8011 - attribute \src "libresoc.v:154416.3-154417.35" + attribute \src "libresoc.v:155406.3-155418.6" + wire $0\neg_res$next[0:0]$7940 + attribute \src "libresoc.v:155419.3-155431.6" + wire $0\neg_res32$next[0:0]$7943 + attribute \src "libresoc.v:155184.3-155185.35" wire $0\neg_res32[0:0] - attribute \src "libresoc.v:154418.3-154419.31" + attribute \src "libresoc.v:155186.3-155187.31" wire $0\neg_res[0:0] - attribute \src "libresoc.v:154532.3-154549.6" - wire $0\r_busy$next[0:0]$7961 - attribute \src "libresoc.v:154452.3-154453.29" + attribute \src "libresoc.v:155300.3-155317.6" + wire $0\r_busy$next[0:0]$7893 + attribute \src "libresoc.v:155220.3-155221.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:154599.3-154611.6" - wire width 64 $0\ra$next[63:0]$7999 - attribute \src "libresoc.v:154424.3-154425.21" + attribute \src "libresoc.v:155367.3-155379.6" + wire width 64 $0\ra$next[63:0]$7931 + attribute \src "libresoc.v:155192.3-155193.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:154612.3-154624.6" - wire width 64 $0\rb$next[63:0]$8002 - attribute \src "libresoc.v:154422.3-154423.21" + attribute \src "libresoc.v:155380.3-155392.6" + wire width 64 $0\rb$next[63:0]$7934 + attribute \src "libresoc.v:155190.3-155191.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:154625.3-154637.6" - wire $0\xer_so$next[0:0]$8005 - attribute \src "libresoc.v:154420.3-154421.29" + attribute \src "libresoc.v:155393.3-155405.6" + wire $0\xer_so$next[0:0]$7937 + attribute \src "libresoc.v:155188.3-155189.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire width 14 $1\mul_op__fn_unit$next[13:0]$7980 - attribute \src "libresoc.v:153986.14-153986.40" + attribute \src "libresoc.v:155331.3-155366.6" + wire width 14 $1\mul_op__fn_unit$next[13:0]$7912 + attribute \src "libresoc.v:154754.14-154754.40" wire width 14 $1\mul_op__fn_unit[13:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire width 64 $1\mul_op__imm_data__data$next[63:0]$7981 - attribute \src "libresoc.v:154025.14-154025.59" + attribute \src "libresoc.v:155331.3-155366.6" + wire width 64 $1\mul_op__imm_data__data$next[63:0]$7913 + attribute \src "libresoc.v:154793.14-154793.59" wire width 64 $1\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $1\mul_op__imm_data__ok$next[0:0]$7982 - attribute \src "libresoc.v:154034.7-154034.34" + attribute \src "libresoc.v:155331.3-155366.6" + wire $1\mul_op__imm_data__ok$next[0:0]$7914 + attribute \src "libresoc.v:154802.7-154802.34" wire $1\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire width 32 $1\mul_op__insn$next[31:0]$7983 - attribute \src "libresoc.v:154043.14-154043.34" + attribute \src "libresoc.v:155331.3-155366.6" + wire width 32 $1\mul_op__insn$next[31:0]$7915 + attribute \src "libresoc.v:154811.14-154811.34" wire width 32 $1\mul_op__insn[31:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire width 7 $1\mul_op__insn_type$next[6:0]$7984 - attribute \src "libresoc.v:154127.13-154127.38" + attribute \src "libresoc.v:155331.3-155366.6" + wire width 7 $1\mul_op__insn_type$next[6:0]$7916 + attribute \src "libresoc.v:154895.13-154895.38" wire width 7 $1\mul_op__insn_type[6:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $1\mul_op__is_32bit$next[0:0]$7985 - attribute \src "libresoc.v:154286.7-154286.30" + attribute \src "libresoc.v:155331.3-155366.6" + wire $1\mul_op__is_32bit$next[0:0]$7917 + attribute \src "libresoc.v:155054.7-155054.30" wire $1\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $1\mul_op__is_signed$next[0:0]$7986 - attribute \src "libresoc.v:154295.7-154295.31" + attribute \src "libresoc.v:155331.3-155366.6" + wire $1\mul_op__is_signed$next[0:0]$7918 + attribute \src "libresoc.v:155063.7-155063.31" wire $1\mul_op__is_signed[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $1\mul_op__oe__oe$next[0:0]$7987 - attribute \src "libresoc.v:154304.7-154304.28" + attribute \src "libresoc.v:155331.3-155366.6" + wire $1\mul_op__oe__oe$next[0:0]$7919 + attribute \src "libresoc.v:155072.7-155072.28" wire $1\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $1\mul_op__oe__ok$next[0:0]$7988 - attribute \src "libresoc.v:154313.7-154313.28" + attribute \src "libresoc.v:155331.3-155366.6" + wire $1\mul_op__oe__ok$next[0:0]$7920 + attribute \src "libresoc.v:155081.7-155081.28" wire $1\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $1\mul_op__rc__ok$next[0:0]$7989 - attribute \src "libresoc.v:154322.7-154322.28" + attribute \src "libresoc.v:155331.3-155366.6" + wire $1\mul_op__rc__ok$next[0:0]$7921 + attribute \src "libresoc.v:155090.7-155090.28" wire $1\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $1\mul_op__rc__rc$next[0:0]$7990 - attribute \src "libresoc.v:154331.7-154331.28" + attribute \src "libresoc.v:155331.3-155366.6" + wire $1\mul_op__rc__rc$next[0:0]$7922 + attribute \src "libresoc.v:155099.7-155099.28" wire $1\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire $1\mul_op__write_cr0$next[0:0]$7991 - attribute \src "libresoc.v:154340.7-154340.31" + attribute \src "libresoc.v:155331.3-155366.6" + wire $1\mul_op__write_cr0$next[0:0]$7923 + attribute \src "libresoc.v:155108.7-155108.31" wire $1\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:154550.3-154562.6" - wire width 2 $1\muxid$next[1:0]$7966 - attribute \src "libresoc.v:154349.13-154349.25" + attribute \src "libresoc.v:155318.3-155330.6" + wire width 2 $1\muxid$next[1:0]$7898 + attribute \src "libresoc.v:155117.13-155117.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:154638.3-154650.6" - wire $1\neg_res$next[0:0]$8009 - attribute \src "libresoc.v:154651.3-154663.6" - wire $1\neg_res32$next[0:0]$8012 - attribute \src "libresoc.v:154371.7-154371.23" + attribute \src "libresoc.v:155406.3-155418.6" + wire $1\neg_res$next[0:0]$7941 + attribute \src "libresoc.v:155419.3-155431.6" + wire $1\neg_res32$next[0:0]$7944 + attribute \src "libresoc.v:155139.7-155139.23" wire $1\neg_res32[0:0] - attribute \src "libresoc.v:154364.7-154364.21" + attribute \src "libresoc.v:155132.7-155132.21" wire $1\neg_res[0:0] - attribute \src "libresoc.v:154532.3-154549.6" - wire $1\r_busy$next[0:0]$7962 - attribute \src "libresoc.v:154385.7-154385.20" + attribute \src "libresoc.v:155300.3-155317.6" + wire $1\r_busy$next[0:0]$7894 + attribute \src "libresoc.v:155153.7-155153.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:154599.3-154611.6" - wire width 64 $1\ra$next[63:0]$8000 - attribute \src "libresoc.v:154390.14-154390.39" + attribute \src "libresoc.v:155367.3-155379.6" + wire width 64 $1\ra$next[63:0]$7932 + attribute \src "libresoc.v:155158.14-155158.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:154612.3-154624.6" - wire width 64 $1\rb$next[63:0]$8003 - attribute \src "libresoc.v:154399.14-154399.39" + attribute \src "libresoc.v:155380.3-155392.6" + wire width 64 $1\rb$next[63:0]$7935 + attribute \src "libresoc.v:155167.14-155167.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:154625.3-154637.6" - wire $1\xer_so$next[0:0]$8006 - attribute \src "libresoc.v:154408.7-154408.20" + attribute \src "libresoc.v:155393.3-155405.6" + wire $1\xer_so$next[0:0]$7938 + attribute \src "libresoc.v:155176.7-155176.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:154563.3-154598.6" - wire width 64 $2\mul_op__imm_data__data$next[63:0]$7992 - attribute \src "libresoc.v:154563.3-154598.6" - wire $2\mul_op__imm_data__ok$next[0:0]$7993 - attribute \src "libresoc.v:154563.3-154598.6" - wire $2\mul_op__oe__oe$next[0:0]$7994 - attribute \src "libresoc.v:154563.3-154598.6" - wire $2\mul_op__oe__ok$next[0:0]$7995 - attribute \src "libresoc.v:154563.3-154598.6" - wire $2\mul_op__rc__ok$next[0:0]$7996 - attribute \src "libresoc.v:154563.3-154598.6" - wire $2\mul_op__rc__rc$next[0:0]$7997 - attribute \src "libresoc.v:154532.3-154549.6" - wire $2\r_busy$next[0:0]$7963 - attribute \src "libresoc.v:154415.18-154415.118" - wire $and$libresoc.v:154415$7940_Y + attribute \src "libresoc.v:155331.3-155366.6" + wire width 64 $2\mul_op__imm_data__data$next[63:0]$7924 + attribute \src "libresoc.v:155331.3-155366.6" + wire $2\mul_op__imm_data__ok$next[0:0]$7925 + attribute \src "libresoc.v:155331.3-155366.6" + wire $2\mul_op__oe__oe$next[0:0]$7926 + attribute \src "libresoc.v:155331.3-155366.6" + wire $2\mul_op__oe__ok$next[0:0]$7927 + attribute \src "libresoc.v:155331.3-155366.6" + wire $2\mul_op__rc__ok$next[0:0]$7928 + attribute \src "libresoc.v:155331.3-155366.6" + wire $2\mul_op__rc__rc$next[0:0]$7929 + attribute \src "libresoc.v:155300.3-155317.6" + wire $2\r_busy$next[0:0]$7895 + attribute \src "libresoc.v:155183.18-155183.118" + wire $and$libresoc.v:155183$7872_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:153470.7-153470.15" + attribute \src "libresoc.v:154238.7-154238.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -321913,7 +288456,7 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:154415$7940 + cell $and $and$libresoc.v:155183$7872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321921,10 +288464,10 @@ module \mul_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$49 connect \B \p_ready_o - connect \Y $and$libresoc.v:154415$7940_Y + connect \Y $and$libresoc.v:155183$7872_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:154454.14-154487.4" + attribute \src "libresoc.v:155222.14-155255.4" cell \input$95 \input connect \mul_op__fn_unit \input_mul_op__fn_unit connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 @@ -321960,7 +288503,7 @@ module \mul_pipe1 connect \xer_so$16 \input_xer_so$32 end attribute \module_not_derived 1 - attribute \src "libresoc.v:154488.8-154523.4" + attribute \src "libresoc.v:155256.8-155291.4" cell \mul1 \mul1 connect \mul_op__fn_unit \mul1_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 @@ -321998,319 +288541,319 @@ module \mul_pipe1 connect \xer_so$16 \mul1_xer_so$48 end attribute \module_not_derived 1 - attribute \src "libresoc.v:154524.10-154527.4" + attribute \src "libresoc.v:155292.10-155295.4" cell \n$94 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:154528.10-154531.4" + attribute \src "libresoc.v:155296.10-155299.4" cell \p$93 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:153470.7-153470.20" - process $proc$libresoc.v:153470$8013 + attribute \src "libresoc.v:154238.7-154238.20" + process $proc$libresoc.v:154238$7945 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:153986.14-153986.40" - process $proc$libresoc.v:153986$8014 + attribute \src "libresoc.v:154754.14-154754.40" + process $proc$libresoc.v:154754$7946 assign { } { } assign $1\mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \mul_op__fn_unit $1\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:154025.14-154025.59" - process $proc$libresoc.v:154025$8015 + attribute \src "libresoc.v:154793.14-154793.59" + process $proc$libresoc.v:154793$7947 assign { } { } assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:154034.7-154034.34" - process $proc$libresoc.v:154034$8016 + attribute \src "libresoc.v:154802.7-154802.34" + process $proc$libresoc.v:154802$7948 assign { } { } assign $1\mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:154043.14-154043.34" - process $proc$libresoc.v:154043$8017 + attribute \src "libresoc.v:154811.14-154811.34" + process $proc$libresoc.v:154811$7949 assign { } { } assign $1\mul_op__insn[31:0] 0 sync always sync init update \mul_op__insn $1\mul_op__insn[31:0] end - attribute \src "libresoc.v:154127.13-154127.38" - process $proc$libresoc.v:154127$8018 + attribute \src "libresoc.v:154895.13-154895.38" + process $proc$libresoc.v:154895$7950 assign { } { } assign $1\mul_op__insn_type[6:0] 7'0000000 sync always sync init update \mul_op__insn_type $1\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:154286.7-154286.30" - process $proc$libresoc.v:154286$8019 + attribute \src "libresoc.v:155054.7-155054.30" + process $proc$libresoc.v:155054$7951 assign { } { } assign $1\mul_op__is_32bit[0:0] 1'0 sync always sync init update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:154295.7-154295.31" - process $proc$libresoc.v:154295$8020 + attribute \src "libresoc.v:155063.7-155063.31" + process $proc$libresoc.v:155063$7952 assign { } { } assign $1\mul_op__is_signed[0:0] 1'0 sync always sync init update \mul_op__is_signed $1\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:154304.7-154304.28" - process $proc$libresoc.v:154304$8021 + attribute \src "libresoc.v:155072.7-155072.28" + process $proc$libresoc.v:155072$7953 assign { } { } assign $1\mul_op__oe__oe[0:0] 1'0 sync always sync init update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:154313.7-154313.28" - process $proc$libresoc.v:154313$8022 + attribute \src "libresoc.v:155081.7-155081.28" + process $proc$libresoc.v:155081$7954 assign { } { } assign $1\mul_op__oe__ok[0:0] 1'0 sync always sync init update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:154322.7-154322.28" - process $proc$libresoc.v:154322$8023 + attribute \src "libresoc.v:155090.7-155090.28" + process $proc$libresoc.v:155090$7955 assign { } { } assign $1\mul_op__rc__ok[0:0] 1'0 sync always sync init update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:154331.7-154331.28" - process $proc$libresoc.v:154331$8024 + attribute \src "libresoc.v:155099.7-155099.28" + process $proc$libresoc.v:155099$7956 assign { } { } assign $1\mul_op__rc__rc[0:0] 1'0 sync always sync init update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:154340.7-154340.31" - process $proc$libresoc.v:154340$8025 + attribute \src "libresoc.v:155108.7-155108.31" + process $proc$libresoc.v:155108$7957 assign { } { } assign $1\mul_op__write_cr0[0:0] 1'0 sync always sync init update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:154349.13-154349.25" - process $proc$libresoc.v:154349$8026 + attribute \src "libresoc.v:155117.13-155117.25" + process $proc$libresoc.v:155117$7958 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:154364.7-154364.21" - process $proc$libresoc.v:154364$8027 + attribute \src "libresoc.v:155132.7-155132.21" + process $proc$libresoc.v:155132$7959 assign { } { } assign $1\neg_res[0:0] 1'0 sync always sync init update \neg_res $1\neg_res[0:0] end - attribute \src "libresoc.v:154371.7-154371.23" - process $proc$libresoc.v:154371$8028 + attribute \src "libresoc.v:155139.7-155139.23" + process $proc$libresoc.v:155139$7960 assign { } { } assign $1\neg_res32[0:0] 1'0 sync always sync init update \neg_res32 $1\neg_res32[0:0] end - attribute \src "libresoc.v:154385.7-154385.20" - process $proc$libresoc.v:154385$8029 + attribute \src "libresoc.v:155153.7-155153.20" + process $proc$libresoc.v:155153$7961 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:154390.14-154390.39" - process $proc$libresoc.v:154390$8030 + attribute \src "libresoc.v:155158.14-155158.39" + process $proc$libresoc.v:155158$7962 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:154399.14-154399.39" - process $proc$libresoc.v:154399$8031 + attribute \src "libresoc.v:155167.14-155167.39" + process $proc$libresoc.v:155167$7963 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:154408.7-154408.20" - process $proc$libresoc.v:154408$8032 + attribute \src "libresoc.v:155176.7-155176.20" + process $proc$libresoc.v:155176$7964 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:154416.3-154417.35" - process $proc$libresoc.v:154416$7941 + attribute \src "libresoc.v:155184.3-155185.35" + process $proc$libresoc.v:155184$7873 assign { } { } assign $0\neg_res32[0:0] \neg_res32$next sync posedge \coresync_clk update \neg_res32 $0\neg_res32[0:0] end - attribute \src "libresoc.v:154418.3-154419.31" - process $proc$libresoc.v:154418$7942 + attribute \src "libresoc.v:155186.3-155187.31" + process $proc$libresoc.v:155186$7874 assign { } { } assign $0\neg_res[0:0] \neg_res$next sync posedge \coresync_clk update \neg_res $0\neg_res[0:0] end - attribute \src "libresoc.v:154420.3-154421.29" - process $proc$libresoc.v:154420$7943 + attribute \src "libresoc.v:155188.3-155189.29" + process $proc$libresoc.v:155188$7875 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:154422.3-154423.21" - process $proc$libresoc.v:154422$7944 + attribute \src "libresoc.v:155190.3-155191.21" + process $proc$libresoc.v:155190$7876 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:154424.3-154425.21" - process $proc$libresoc.v:154424$7945 + attribute \src "libresoc.v:155192.3-155193.21" + process $proc$libresoc.v:155192$7877 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:154426.3-154427.51" - process $proc$libresoc.v:154426$7946 + attribute \src "libresoc.v:155194.3-155195.51" + process $proc$libresoc.v:155194$7878 assign { } { } assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next sync posedge \coresync_clk update \mul_op__insn_type $0\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:154428.3-154429.47" - process $proc$libresoc.v:154428$7947 + attribute \src "libresoc.v:155196.3-155197.47" + process $proc$libresoc.v:155196$7879 assign { } { } assign $0\mul_op__fn_unit[13:0] \mul_op__fn_unit$next sync posedge \coresync_clk update \mul_op__fn_unit $0\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:154430.3-154431.61" - process $proc$libresoc.v:154430$7948 + attribute \src "libresoc.v:155198.3-155199.61" + process $proc$libresoc.v:155198$7880 assign { } { } assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next sync posedge \coresync_clk update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:154432.3-154433.57" - process $proc$libresoc.v:154432$7949 + attribute \src "libresoc.v:155200.3-155201.57" + process $proc$libresoc.v:155200$7881 assign { } { } assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next sync posedge \coresync_clk update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:154434.3-154435.45" - process $proc$libresoc.v:154434$7950 + attribute \src "libresoc.v:155202.3-155203.45" + process $proc$libresoc.v:155202$7882 assign { } { } assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next sync posedge \coresync_clk update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:154436.3-154437.45" - process $proc$libresoc.v:154436$7951 + attribute \src "libresoc.v:155204.3-155205.45" + process $proc$libresoc.v:155204$7883 assign { } { } assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next sync posedge \coresync_clk update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:154438.3-154439.45" - process $proc$libresoc.v:154438$7952 + attribute \src "libresoc.v:155206.3-155207.45" + process $proc$libresoc.v:155206$7884 assign { } { } assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next sync posedge \coresync_clk update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:154440.3-154441.45" - process $proc$libresoc.v:154440$7953 + attribute \src "libresoc.v:155208.3-155209.45" + process $proc$libresoc.v:155208$7885 assign { } { } assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next sync posedge \coresync_clk update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:154442.3-154443.51" - process $proc$libresoc.v:154442$7954 + attribute \src "libresoc.v:155210.3-155211.51" + process $proc$libresoc.v:155210$7886 assign { } { } assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next sync posedge \coresync_clk update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:154444.3-154445.49" - process $proc$libresoc.v:154444$7955 + attribute \src "libresoc.v:155212.3-155213.49" + process $proc$libresoc.v:155212$7887 assign { } { } assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next sync posedge \coresync_clk update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:154446.3-154447.51" - process $proc$libresoc.v:154446$7956 + attribute \src "libresoc.v:155214.3-155215.51" + process $proc$libresoc.v:155214$7888 assign { } { } assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next sync posedge \coresync_clk update \mul_op__is_signed $0\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:154448.3-154449.41" - process $proc$libresoc.v:154448$7957 + attribute \src "libresoc.v:155216.3-155217.41" + process $proc$libresoc.v:155216$7889 assign { } { } assign $0\mul_op__insn[31:0] \mul_op__insn$next sync posedge \coresync_clk update \mul_op__insn $0\mul_op__insn[31:0] end - attribute \src "libresoc.v:154450.3-154451.27" - process $proc$libresoc.v:154450$7958 + attribute \src "libresoc.v:155218.3-155219.27" + process $proc$libresoc.v:155218$7890 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:154452.3-154453.29" - process $proc$libresoc.v:154452$7959 + attribute \src "libresoc.v:155220.3-155221.29" + process $proc$libresoc.v:155220$7891 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:154532.3-154549.6" - process $proc$libresoc.v:154532$7960 + attribute \src "libresoc.v:155300.3-155317.6" + process $proc$libresoc.v:155300$7892 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7961 $2\r_busy$next[0:0]$7963 - attribute \src "libresoc.v:154533.5-154533.29" + assign $0\r_busy$next[0:0]$7893 $2\r_busy$next[0:0]$7895 + attribute \src "libresoc.v:155301.5-155301.29" switch \initial - attribute \src "libresoc.v:154533.9-154533.17" + attribute \src "libresoc.v:155301.9-155301.17" case 1'1 case end @@ -322319,34 +288862,34 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$7962 1'1 + assign $1\r_busy$next[0:0]$7894 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$7962 1'0 + assign $1\r_busy$next[0:0]$7894 1'0 case - assign $1\r_busy$next[0:0]$7962 \r_busy + assign $1\r_busy$next[0:0]$7894 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$7963 1'0 + assign $2\r_busy$next[0:0]$7895 1'0 case - assign $2\r_busy$next[0:0]$7963 $1\r_busy$next[0:0]$7962 + assign $2\r_busy$next[0:0]$7895 $1\r_busy$next[0:0]$7894 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7961 + update \r_busy$next $0\r_busy$next[0:0]$7893 end - attribute \src "libresoc.v:154550.3-154562.6" - process $proc$libresoc.v:154550$7964 + attribute \src "libresoc.v:155318.3-155330.6" + process $proc$libresoc.v:155318$7896 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$7965 $1\muxid$next[1:0]$7966 - attribute \src "libresoc.v:154551.5-154551.29" + assign $0\muxid$next[1:0]$7897 $1\muxid$next[1:0]$7898 + attribute \src "libresoc.v:155319.5-155319.29" switch \initial - attribute \src "libresoc.v:154551.9-154551.17" + attribute \src "libresoc.v:155319.9-155319.17" case 1'1 case end @@ -322355,19 +288898,19 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$7966 \muxid$52 + assign $1\muxid$next[1:0]$7898 \muxid$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$7966 \muxid$52 + assign $1\muxid$next[1:0]$7898 \muxid$52 case - assign $1\muxid$next[1:0]$7966 \muxid + assign $1\muxid$next[1:0]$7898 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$7965 + update \muxid$next $0\muxid$next[1:0]$7897 end - attribute \src "libresoc.v:154563.3-154598.6" - process $proc$libresoc.v:154563$7967 + attribute \src "libresoc.v:155331.3-155366.6" + process $proc$libresoc.v:155331$7899 assign { } { } assign { } { } assign { } { } @@ -322392,27 +288935,27 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$next[13:0]$7968 $1\mul_op__fn_unit$next[13:0]$7980 + assign $0\mul_op__fn_unit$next[13:0]$7900 $1\mul_op__fn_unit$next[13:0]$7912 assign { } { } assign { } { } - assign $0\mul_op__insn$next[31:0]$7971 $1\mul_op__insn$next[31:0]$7983 - assign $0\mul_op__insn_type$next[6:0]$7972 $1\mul_op__insn_type$next[6:0]$7984 - assign $0\mul_op__is_32bit$next[0:0]$7973 $1\mul_op__is_32bit$next[0:0]$7985 - assign $0\mul_op__is_signed$next[0:0]$7974 $1\mul_op__is_signed$next[0:0]$7986 + assign $0\mul_op__insn$next[31:0]$7903 $1\mul_op__insn$next[31:0]$7915 + assign $0\mul_op__insn_type$next[6:0]$7904 $1\mul_op__insn_type$next[6:0]$7916 + assign $0\mul_op__is_32bit$next[0:0]$7905 $1\mul_op__is_32bit$next[0:0]$7917 + assign $0\mul_op__is_signed$next[0:0]$7906 $1\mul_op__is_signed$next[0:0]$7918 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$next[0:0]$7979 $1\mul_op__write_cr0$next[0:0]$7991 - assign $0\mul_op__imm_data__data$next[63:0]$7969 $2\mul_op__imm_data__data$next[63:0]$7992 - assign $0\mul_op__imm_data__ok$next[0:0]$7970 $2\mul_op__imm_data__ok$next[0:0]$7993 - assign $0\mul_op__oe__oe$next[0:0]$7975 $2\mul_op__oe__oe$next[0:0]$7994 - assign $0\mul_op__oe__ok$next[0:0]$7976 $2\mul_op__oe__ok$next[0:0]$7995 - assign $0\mul_op__rc__ok$next[0:0]$7977 $2\mul_op__rc__ok$next[0:0]$7996 - assign $0\mul_op__rc__rc$next[0:0]$7978 $2\mul_op__rc__rc$next[0:0]$7997 - attribute \src "libresoc.v:154564.5-154564.29" + assign $0\mul_op__write_cr0$next[0:0]$7911 $1\mul_op__write_cr0$next[0:0]$7923 + assign $0\mul_op__imm_data__data$next[63:0]$7901 $2\mul_op__imm_data__data$next[63:0]$7924 + assign $0\mul_op__imm_data__ok$next[0:0]$7902 $2\mul_op__imm_data__ok$next[0:0]$7925 + assign $0\mul_op__oe__oe$next[0:0]$7907 $2\mul_op__oe__oe$next[0:0]$7926 + assign $0\mul_op__oe__ok$next[0:0]$7908 $2\mul_op__oe__ok$next[0:0]$7927 + assign $0\mul_op__rc__ok$next[0:0]$7909 $2\mul_op__rc__ok$next[0:0]$7928 + assign $0\mul_op__rc__rc$next[0:0]$7910 $2\mul_op__rc__rc$next[0:0]$7929 + attribute \src "libresoc.v:155332.5-155332.29" switch \initial - attribute \src "libresoc.v:154564.9-154564.17" + attribute \src "libresoc.v:155332.9-155332.17" case 1'1 case end @@ -322432,7 +288975,7 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7983 $1\mul_op__is_signed$next[0:0]$7986 $1\mul_op__is_32bit$next[0:0]$7985 $1\mul_op__write_cr0$next[0:0]$7991 $1\mul_op__oe__ok$next[0:0]$7988 $1\mul_op__oe__oe$next[0:0]$7987 $1\mul_op__rc__ok$next[0:0]$7989 $1\mul_op__rc__rc$next[0:0]$7990 $1\mul_op__imm_data__ok$next[0:0]$7982 $1\mul_op__imm_data__data$next[63:0]$7981 $1\mul_op__fn_unit$next[13:0]$7980 $1\mul_op__insn_type$next[6:0]$7984 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { $1\mul_op__insn$next[31:0]$7915 $1\mul_op__is_signed$next[0:0]$7918 $1\mul_op__is_32bit$next[0:0]$7917 $1\mul_op__write_cr0$next[0:0]$7923 $1\mul_op__oe__ok$next[0:0]$7920 $1\mul_op__oe__oe$next[0:0]$7919 $1\mul_op__rc__ok$next[0:0]$7921 $1\mul_op__rc__rc$next[0:0]$7922 $1\mul_op__imm_data__ok$next[0:0]$7914 $1\mul_op__imm_data__data$next[63:0]$7913 $1\mul_op__fn_unit$next[13:0]$7912 $1\mul_op__insn_type$next[6:0]$7916 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -322447,20 +288990,20 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7983 $1\mul_op__is_signed$next[0:0]$7986 $1\mul_op__is_32bit$next[0:0]$7985 $1\mul_op__write_cr0$next[0:0]$7991 $1\mul_op__oe__ok$next[0:0]$7988 $1\mul_op__oe__oe$next[0:0]$7987 $1\mul_op__rc__ok$next[0:0]$7989 $1\mul_op__rc__rc$next[0:0]$7990 $1\mul_op__imm_data__ok$next[0:0]$7982 $1\mul_op__imm_data__data$next[63:0]$7981 $1\mul_op__fn_unit$next[13:0]$7980 $1\mul_op__insn_type$next[6:0]$7984 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { $1\mul_op__insn$next[31:0]$7915 $1\mul_op__is_signed$next[0:0]$7918 $1\mul_op__is_32bit$next[0:0]$7917 $1\mul_op__write_cr0$next[0:0]$7923 $1\mul_op__oe__ok$next[0:0]$7920 $1\mul_op__oe__oe$next[0:0]$7919 $1\mul_op__rc__ok$next[0:0]$7921 $1\mul_op__rc__rc$next[0:0]$7922 $1\mul_op__imm_data__ok$next[0:0]$7914 $1\mul_op__imm_data__data$next[63:0]$7913 $1\mul_op__fn_unit$next[13:0]$7912 $1\mul_op__insn_type$next[6:0]$7916 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } case - assign $1\mul_op__fn_unit$next[13:0]$7980 \mul_op__fn_unit - assign $1\mul_op__imm_data__data$next[63:0]$7981 \mul_op__imm_data__data - assign $1\mul_op__imm_data__ok$next[0:0]$7982 \mul_op__imm_data__ok - assign $1\mul_op__insn$next[31:0]$7983 \mul_op__insn - assign $1\mul_op__insn_type$next[6:0]$7984 \mul_op__insn_type - assign $1\mul_op__is_32bit$next[0:0]$7985 \mul_op__is_32bit - assign $1\mul_op__is_signed$next[0:0]$7986 \mul_op__is_signed - assign $1\mul_op__oe__oe$next[0:0]$7987 \mul_op__oe__oe - assign $1\mul_op__oe__ok$next[0:0]$7988 \mul_op__oe__ok - assign $1\mul_op__rc__ok$next[0:0]$7989 \mul_op__rc__ok - assign $1\mul_op__rc__rc$next[0:0]$7990 \mul_op__rc__rc - assign $1\mul_op__write_cr0$next[0:0]$7991 \mul_op__write_cr0 + assign $1\mul_op__fn_unit$next[13:0]$7912 \mul_op__fn_unit + assign $1\mul_op__imm_data__data$next[63:0]$7913 \mul_op__imm_data__data + assign $1\mul_op__imm_data__ok$next[0:0]$7914 \mul_op__imm_data__ok + assign $1\mul_op__insn$next[31:0]$7915 \mul_op__insn + assign $1\mul_op__insn_type$next[6:0]$7916 \mul_op__insn_type + assign $1\mul_op__is_32bit$next[0:0]$7917 \mul_op__is_32bit + assign $1\mul_op__is_signed$next[0:0]$7918 \mul_op__is_signed + assign $1\mul_op__oe__oe$next[0:0]$7919 \mul_op__oe__oe + assign $1\mul_op__oe__ok$next[0:0]$7920 \mul_op__oe__ok + assign $1\mul_op__rc__ok$next[0:0]$7921 \mul_op__rc__ok + assign $1\mul_op__rc__rc$next[0:0]$7922 \mul_op__rc__rc + assign $1\mul_op__write_cr0$next[0:0]$7923 \mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -322472,42 +289015,42 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$next[63:0]$7992 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$next[0:0]$7993 1'0 - assign $2\mul_op__rc__rc$next[0:0]$7997 1'0 - assign $2\mul_op__rc__ok$next[0:0]$7996 1'0 - assign $2\mul_op__oe__oe$next[0:0]$7994 1'0 - assign $2\mul_op__oe__ok$next[0:0]$7995 1'0 + assign $2\mul_op__imm_data__data$next[63:0]$7924 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$next[0:0]$7925 1'0 + assign $2\mul_op__rc__rc$next[0:0]$7929 1'0 + assign $2\mul_op__rc__ok$next[0:0]$7928 1'0 + assign $2\mul_op__oe__oe$next[0:0]$7926 1'0 + assign $2\mul_op__oe__ok$next[0:0]$7927 1'0 case - assign $2\mul_op__imm_data__data$next[63:0]$7992 $1\mul_op__imm_data__data$next[63:0]$7981 - assign $2\mul_op__imm_data__ok$next[0:0]$7993 $1\mul_op__imm_data__ok$next[0:0]$7982 - assign $2\mul_op__oe__oe$next[0:0]$7994 $1\mul_op__oe__oe$next[0:0]$7987 - assign $2\mul_op__oe__ok$next[0:0]$7995 $1\mul_op__oe__ok$next[0:0]$7988 - assign $2\mul_op__rc__ok$next[0:0]$7996 $1\mul_op__rc__ok$next[0:0]$7989 - assign $2\mul_op__rc__rc$next[0:0]$7997 $1\mul_op__rc__rc$next[0:0]$7990 + assign $2\mul_op__imm_data__data$next[63:0]$7924 $1\mul_op__imm_data__data$next[63:0]$7913 + assign $2\mul_op__imm_data__ok$next[0:0]$7925 $1\mul_op__imm_data__ok$next[0:0]$7914 + assign $2\mul_op__oe__oe$next[0:0]$7926 $1\mul_op__oe__oe$next[0:0]$7919 + assign $2\mul_op__oe__ok$next[0:0]$7927 $1\mul_op__oe__ok$next[0:0]$7920 + assign $2\mul_op__rc__ok$next[0:0]$7928 $1\mul_op__rc__ok$next[0:0]$7921 + assign $2\mul_op__rc__rc$next[0:0]$7929 $1\mul_op__rc__rc$next[0:0]$7922 end sync always - update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[13:0]$7968 - update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7969 - update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7970 - update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7971 - update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7972 - update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7973 - update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7974 - update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7975 - update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7976 - update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7977 - update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7978 - update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7979 + update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[13:0]$7900 + update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7901 + update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7902 + update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7903 + update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7904 + update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7905 + update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7906 + update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7907 + update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7908 + update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7909 + update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7910 + update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7911 end - attribute \src "libresoc.v:154599.3-154611.6" - process $proc$libresoc.v:154599$7998 + attribute \src "libresoc.v:155367.3-155379.6" + process $proc$libresoc.v:155367$7930 assign { } { } assign { } { } - assign $0\ra$next[63:0]$7999 $1\ra$next[63:0]$8000 - attribute \src "libresoc.v:154600.5-154600.29" + assign $0\ra$next[63:0]$7931 $1\ra$next[63:0]$7932 + attribute \src "libresoc.v:155368.5-155368.29" switch \initial - attribute \src "libresoc.v:154600.9-154600.17" + attribute \src "libresoc.v:155368.9-155368.17" case 1'1 case end @@ -322516,25 +289059,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$8000 \ra$65 + assign $1\ra$next[63:0]$7932 \ra$65 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$8000 \ra$65 + assign $1\ra$next[63:0]$7932 \ra$65 case - assign $1\ra$next[63:0]$8000 \ra + assign $1\ra$next[63:0]$7932 \ra end sync always - update \ra$next $0\ra$next[63:0]$7999 + update \ra$next $0\ra$next[63:0]$7931 end - attribute \src "libresoc.v:154612.3-154624.6" - process $proc$libresoc.v:154612$8001 + attribute \src "libresoc.v:155380.3-155392.6" + process $proc$libresoc.v:155380$7933 assign { } { } assign { } { } - assign $0\rb$next[63:0]$8002 $1\rb$next[63:0]$8003 - attribute \src "libresoc.v:154613.5-154613.29" + assign $0\rb$next[63:0]$7934 $1\rb$next[63:0]$7935 + attribute \src "libresoc.v:155381.5-155381.29" switch \initial - attribute \src "libresoc.v:154613.9-154613.17" + attribute \src "libresoc.v:155381.9-155381.17" case 1'1 case end @@ -322543,25 +289086,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$8003 \rb$66 + assign $1\rb$next[63:0]$7935 \rb$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$8003 \rb$66 + assign $1\rb$next[63:0]$7935 \rb$66 case - assign $1\rb$next[63:0]$8003 \rb + assign $1\rb$next[63:0]$7935 \rb end sync always - update \rb$next $0\rb$next[63:0]$8002 + update \rb$next $0\rb$next[63:0]$7934 end - attribute \src "libresoc.v:154625.3-154637.6" - process $proc$libresoc.v:154625$8004 + attribute \src "libresoc.v:155393.3-155405.6" + process $proc$libresoc.v:155393$7936 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$8005 $1\xer_so$next[0:0]$8006 - attribute \src "libresoc.v:154626.5-154626.29" + assign $0\xer_so$next[0:0]$7937 $1\xer_so$next[0:0]$7938 + attribute \src "libresoc.v:155394.5-155394.29" switch \initial - attribute \src "libresoc.v:154626.9-154626.17" + attribute \src "libresoc.v:155394.9-155394.17" case 1'1 case end @@ -322570,25 +289113,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$next[0:0]$8006 \xer_so$67 + assign $1\xer_so$next[0:0]$7938 \xer_so$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$next[0:0]$8006 \xer_so$67 + assign $1\xer_so$next[0:0]$7938 \xer_so$67 case - assign $1\xer_so$next[0:0]$8006 \xer_so + assign $1\xer_so$next[0:0]$7938 \xer_so end sync always - update \xer_so$next $0\xer_so$next[0:0]$8005 + update \xer_so$next $0\xer_so$next[0:0]$7937 end - attribute \src "libresoc.v:154638.3-154650.6" - process $proc$libresoc.v:154638$8007 + attribute \src "libresoc.v:155406.3-155418.6" + process $proc$libresoc.v:155406$7939 assign { } { } assign { } { } - assign $0\neg_res$next[0:0]$8008 $1\neg_res$next[0:0]$8009 - attribute \src "libresoc.v:154639.5-154639.29" + assign $0\neg_res$next[0:0]$7940 $1\neg_res$next[0:0]$7941 + attribute \src "libresoc.v:155407.5-155407.29" switch \initial - attribute \src "libresoc.v:154639.9-154639.17" + attribute \src "libresoc.v:155407.9-155407.17" case 1'1 case end @@ -322597,25 +289140,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res$next[0:0]$8009 \neg_res$68 + assign $1\neg_res$next[0:0]$7941 \neg_res$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res$next[0:0]$8009 \neg_res$68 + assign $1\neg_res$next[0:0]$7941 \neg_res$68 case - assign $1\neg_res$next[0:0]$8009 \neg_res + assign $1\neg_res$next[0:0]$7941 \neg_res end sync always - update \neg_res$next $0\neg_res$next[0:0]$8008 + update \neg_res$next $0\neg_res$next[0:0]$7940 end - attribute \src "libresoc.v:154651.3-154663.6" - process $proc$libresoc.v:154651$8010 + attribute \src "libresoc.v:155419.3-155431.6" + process $proc$libresoc.v:155419$7942 assign { } { } assign { } { } - assign $0\neg_res32$next[0:0]$8011 $1\neg_res32$next[0:0]$8012 - attribute \src "libresoc.v:154652.5-154652.29" + assign $0\neg_res32$next[0:0]$7943 $1\neg_res32$next[0:0]$7944 + attribute \src "libresoc.v:155420.5-155420.29" switch \initial - attribute \src "libresoc.v:154652.9-154652.17" + attribute \src "libresoc.v:155420.9-155420.17" case 1'1 case end @@ -322624,18 +289167,18 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res32$next[0:0]$8012 \neg_res32$69 + assign $1\neg_res32$next[0:0]$7944 \neg_res32$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res32$next[0:0]$8012 \neg_res32$69 + assign $1\neg_res32$next[0:0]$7944 \neg_res32$69 case - assign $1\neg_res32$next[0:0]$8012 \neg_res32 + assign $1\neg_res32$next[0:0]$7944 \neg_res32 end sync always - update \neg_res32$next $0\neg_res32$next[0:0]$8011 + update \neg_res32$next $0\neg_res32$next[0:0]$7943 end - connect \$50 $and$libresoc.v:154415$7940_Y + connect \$50 $and$libresoc.v:155183$7872_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$69 \mul1_neg_res32 @@ -322659,180 +289202,180 @@ module \mul_pipe1 connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:154690.1-155610.10" +attribute \src "libresoc.v:155458.1-156378.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" attribute \generator "nMigen" module \mul_pipe2 - attribute \src "libresoc.v:154691.7-154691.20" + attribute \src "libresoc.v:155459.7-155459.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155504.3-155539.6" - wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8076 - attribute \src "libresoc.v:155402.3-155403.53" - wire width 14 $0\mul_op__fn_unit$3[13:0]$8044 - attribute \src "libresoc.v:154982.14-154982.44" - wire width 14 $0\mul_op__fn_unit$3[13:0]$8120 - attribute \src "libresoc.v:155504.3-155539.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8077 - attribute \src "libresoc.v:155404.3-155405.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8046 - attribute \src "libresoc.v:155008.14-155008.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8122 - attribute \src "libresoc.v:155504.3-155539.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$8078 - attribute \src "libresoc.v:155406.3-155407.63" - wire $0\mul_op__imm_data__ok$5[0:0]$8048 - attribute \src "libresoc.v:155017.7-155017.38" - wire $0\mul_op__imm_data__ok$5[0:0]$8124 - attribute \src "libresoc.v:155504.3-155539.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$8079 - attribute \src "libresoc.v:155422.3-155423.49" - wire width 32 $0\mul_op__insn$13[31:0]$8064 - attribute \src "libresoc.v:155024.14-155024.39" - wire width 32 $0\mul_op__insn$13[31:0]$8126 - attribute \src "libresoc.v:155504.3-155539.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$8080 - attribute \src "libresoc.v:155400.3-155401.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$8042 - attribute \src "libresoc.v:155183.13-155183.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$8128 - attribute \src "libresoc.v:155504.3-155539.6" - wire $0\mul_op__is_32bit$11$next[0:0]$8081 - attribute \src "libresoc.v:155418.3-155419.57" - wire $0\mul_op__is_32bit$11[0:0]$8060 - attribute \src "libresoc.v:155267.7-155267.35" - wire $0\mul_op__is_32bit$11[0:0]$8130 - attribute \src "libresoc.v:155504.3-155539.6" - wire $0\mul_op__is_signed$12$next[0:0]$8082 - attribute \src "libresoc.v:155420.3-155421.59" - wire $0\mul_op__is_signed$12[0:0]$8062 - attribute \src "libresoc.v:155276.7-155276.36" - wire $0\mul_op__is_signed$12[0:0]$8132 - attribute \src "libresoc.v:155504.3-155539.6" - wire $0\mul_op__oe__oe$8$next[0:0]$8083 - attribute \src "libresoc.v:155412.3-155413.51" - wire $0\mul_op__oe__oe$8[0:0]$8054 - attribute \src "libresoc.v:155287.7-155287.32" - wire $0\mul_op__oe__oe$8[0:0]$8134 - attribute \src "libresoc.v:155504.3-155539.6" - wire $0\mul_op__oe__ok$9$next[0:0]$8084 - attribute \src "libresoc.v:155414.3-155415.51" - wire $0\mul_op__oe__ok$9[0:0]$8056 - attribute \src "libresoc.v:155296.7-155296.32" - wire $0\mul_op__oe__ok$9[0:0]$8136 - attribute \src "libresoc.v:155504.3-155539.6" - wire $0\mul_op__rc__ok$7$next[0:0]$8085 - attribute \src "libresoc.v:155410.3-155411.51" - wire $0\mul_op__rc__ok$7[0:0]$8052 - attribute \src "libresoc.v:155305.7-155305.32" - wire $0\mul_op__rc__ok$7[0:0]$8138 - attribute \src "libresoc.v:155504.3-155539.6" - wire $0\mul_op__rc__rc$6$next[0:0]$8086 - attribute \src "libresoc.v:155408.3-155409.51" - wire $0\mul_op__rc__rc$6[0:0]$8050 - attribute \src "libresoc.v:155314.7-155314.32" - wire $0\mul_op__rc__rc$6[0:0]$8140 - attribute \src "libresoc.v:155504.3-155539.6" - wire $0\mul_op__write_cr0$10$next[0:0]$8087 - attribute \src "libresoc.v:155416.3-155417.59" - wire $0\mul_op__write_cr0$10[0:0]$8058 - attribute \src "libresoc.v:155321.7-155321.36" - wire $0\mul_op__write_cr0$10[0:0]$8142 - attribute \src "libresoc.v:155491.3-155503.6" - wire width 2 $0\muxid$1$next[1:0]$8073 - attribute \src "libresoc.v:155424.3-155425.33" - wire width 2 $0\muxid$1[1:0]$8066 - attribute \src "libresoc.v:155330.13-155330.29" - wire width 2 $0\muxid$1[1:0]$8144 - attribute \src "libresoc.v:155566.3-155578.6" - wire $0\neg_res$15$next[0:0]$8113 - attribute \src "libresoc.v:155394.3-155395.39" - wire $0\neg_res$15[0:0]$8037 - attribute \src "libresoc.v:155345.7-155345.26" - wire $0\neg_res$15[0:0]$8146 - attribute \src "libresoc.v:155579.3-155591.6" - wire $0\neg_res32$16$next[0:0]$8116 - attribute \src "libresoc.v:155392.3-155393.43" - wire $0\neg_res32$16[0:0]$8035 - attribute \src "libresoc.v:155354.7-155354.28" - wire $0\neg_res32$16[0:0]$8148 - attribute \src "libresoc.v:155540.3-155552.6" - wire width 129 $0\o$next[128:0]$8107 - attribute \src "libresoc.v:155398.3-155399.19" + attribute \src "libresoc.v:156272.3-156307.6" + wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8008 + attribute \src "libresoc.v:156170.3-156171.53" + wire width 14 $0\mul_op__fn_unit$3[13:0]$7976 + attribute \src "libresoc.v:155750.14-155750.44" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8052 + attribute \src "libresoc.v:156272.3-156307.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8009 + attribute \src "libresoc.v:156172.3-156173.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7978 + attribute \src "libresoc.v:155776.14-155776.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8054 + attribute \src "libresoc.v:156272.3-156307.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8010 + attribute \src "libresoc.v:156174.3-156175.63" + wire $0\mul_op__imm_data__ok$5[0:0]$7980 + attribute \src "libresoc.v:155785.7-155785.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8056 + attribute \src "libresoc.v:156272.3-156307.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8011 + attribute \src "libresoc.v:156190.3-156191.49" + wire width 32 $0\mul_op__insn$13[31:0]$7996 + attribute \src "libresoc.v:155792.14-155792.39" + wire width 32 $0\mul_op__insn$13[31:0]$8058 + attribute \src "libresoc.v:156272.3-156307.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8012 + attribute \src "libresoc.v:156168.3-156169.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$7974 + attribute \src "libresoc.v:155951.13-155951.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8060 + attribute \src "libresoc.v:156272.3-156307.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8013 + attribute \src "libresoc.v:156186.3-156187.57" + wire $0\mul_op__is_32bit$11[0:0]$7992 + attribute \src "libresoc.v:156035.7-156035.35" + wire $0\mul_op__is_32bit$11[0:0]$8062 + attribute \src "libresoc.v:156272.3-156307.6" + wire $0\mul_op__is_signed$12$next[0:0]$8014 + attribute \src "libresoc.v:156188.3-156189.59" + wire $0\mul_op__is_signed$12[0:0]$7994 + attribute \src "libresoc.v:156044.7-156044.36" + wire $0\mul_op__is_signed$12[0:0]$8064 + attribute \src "libresoc.v:156272.3-156307.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8015 + attribute \src "libresoc.v:156180.3-156181.51" + wire $0\mul_op__oe__oe$8[0:0]$7986 + attribute \src "libresoc.v:156055.7-156055.32" + wire $0\mul_op__oe__oe$8[0:0]$8066 + attribute \src "libresoc.v:156272.3-156307.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8016 + attribute \src "libresoc.v:156182.3-156183.51" + wire $0\mul_op__oe__ok$9[0:0]$7988 + attribute \src "libresoc.v:156064.7-156064.32" + wire $0\mul_op__oe__ok$9[0:0]$8068 + attribute \src "libresoc.v:156272.3-156307.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8017 + attribute \src "libresoc.v:156178.3-156179.51" + wire $0\mul_op__rc__ok$7[0:0]$7984 + attribute \src "libresoc.v:156073.7-156073.32" + wire $0\mul_op__rc__ok$7[0:0]$8070 + attribute \src "libresoc.v:156272.3-156307.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8018 + attribute \src "libresoc.v:156176.3-156177.51" + wire $0\mul_op__rc__rc$6[0:0]$7982 + attribute \src "libresoc.v:156082.7-156082.32" + wire $0\mul_op__rc__rc$6[0:0]$8072 + attribute \src "libresoc.v:156272.3-156307.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8019 + attribute \src "libresoc.v:156184.3-156185.59" + wire $0\mul_op__write_cr0$10[0:0]$7990 + attribute \src "libresoc.v:156089.7-156089.36" + wire $0\mul_op__write_cr0$10[0:0]$8074 + attribute \src "libresoc.v:156259.3-156271.6" + wire width 2 $0\muxid$1$next[1:0]$8005 + attribute \src "libresoc.v:156192.3-156193.33" + wire width 2 $0\muxid$1[1:0]$7998 + attribute \src "libresoc.v:156098.13-156098.29" + wire width 2 $0\muxid$1[1:0]$8076 + attribute \src "libresoc.v:156334.3-156346.6" + wire $0\neg_res$15$next[0:0]$8045 + attribute \src "libresoc.v:156162.3-156163.39" + wire $0\neg_res$15[0:0]$7969 + attribute \src "libresoc.v:156113.7-156113.26" + wire $0\neg_res$15[0:0]$8078 + attribute \src "libresoc.v:156347.3-156359.6" + wire $0\neg_res32$16$next[0:0]$8048 + attribute \src "libresoc.v:156160.3-156161.43" + wire $0\neg_res32$16[0:0]$7967 + attribute \src "libresoc.v:156122.7-156122.28" + wire $0\neg_res32$16[0:0]$8080 + attribute \src "libresoc.v:156308.3-156320.6" + wire width 129 $0\o$next[128:0]$8039 + attribute \src "libresoc.v:156166.3-156167.19" wire width 129 $0\o[128:0] - attribute \src "libresoc.v:155473.3-155490.6" - wire $0\r_busy$next[0:0]$8069 - attribute \src "libresoc.v:155426.3-155427.29" + attribute \src "libresoc.v:156241.3-156258.6" + wire $0\r_busy$next[0:0]$8001 + attribute \src "libresoc.v:156194.3-156195.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:155553.3-155565.6" - wire $0\xer_so$14$next[0:0]$8110 - attribute \src "libresoc.v:155396.3-155397.37" - wire $0\xer_so$14[0:0]$8039 - attribute \src "libresoc.v:155386.7-155386.25" - wire $0\xer_so$14[0:0]$8152 - attribute \src "libresoc.v:155504.3-155539.6" - wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8088 - attribute \src "libresoc.v:155504.3-155539.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8089 - attribute \src "libresoc.v:155504.3-155539.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$8090 - attribute \src "libresoc.v:155504.3-155539.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$8091 - attribute \src "libresoc.v:155504.3-155539.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$8092 - attribute \src "libresoc.v:155504.3-155539.6" - wire $1\mul_op__is_32bit$11$next[0:0]$8093 - attribute \src "libresoc.v:155504.3-155539.6" - wire $1\mul_op__is_signed$12$next[0:0]$8094 - attribute \src "libresoc.v:155504.3-155539.6" - wire $1\mul_op__oe__oe$8$next[0:0]$8095 - attribute \src "libresoc.v:155504.3-155539.6" - wire $1\mul_op__oe__ok$9$next[0:0]$8096 - attribute \src "libresoc.v:155504.3-155539.6" - wire $1\mul_op__rc__ok$7$next[0:0]$8097 - attribute \src "libresoc.v:155504.3-155539.6" - wire $1\mul_op__rc__rc$6$next[0:0]$8098 - attribute \src "libresoc.v:155504.3-155539.6" - wire $1\mul_op__write_cr0$10$next[0:0]$8099 - attribute \src "libresoc.v:155491.3-155503.6" - wire width 2 $1\muxid$1$next[1:0]$8074 - attribute \src "libresoc.v:155566.3-155578.6" - wire $1\neg_res$15$next[0:0]$8114 - attribute \src "libresoc.v:155579.3-155591.6" - wire $1\neg_res32$16$next[0:0]$8117 - attribute \src "libresoc.v:155540.3-155552.6" - wire width 129 $1\o$next[128:0]$8108 - attribute \src "libresoc.v:155361.15-155361.57" + attribute \src "libresoc.v:156321.3-156333.6" + wire $0\xer_so$14$next[0:0]$8042 + attribute \src "libresoc.v:156164.3-156165.37" + wire $0\xer_so$14[0:0]$7971 + attribute \src "libresoc.v:156154.7-156154.25" + wire $0\xer_so$14[0:0]$8084 + attribute \src "libresoc.v:156272.3-156307.6" + wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8020 + attribute \src "libresoc.v:156272.3-156307.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8021 + attribute \src "libresoc.v:156272.3-156307.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8022 + attribute \src "libresoc.v:156272.3-156307.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8023 + attribute \src "libresoc.v:156272.3-156307.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8024 + attribute \src "libresoc.v:156272.3-156307.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8025 + attribute \src "libresoc.v:156272.3-156307.6" + wire $1\mul_op__is_signed$12$next[0:0]$8026 + attribute \src "libresoc.v:156272.3-156307.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8027 + attribute \src "libresoc.v:156272.3-156307.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8028 + attribute \src "libresoc.v:156272.3-156307.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8029 + attribute \src "libresoc.v:156272.3-156307.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8030 + attribute \src "libresoc.v:156272.3-156307.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8031 + attribute \src "libresoc.v:156259.3-156271.6" + wire width 2 $1\muxid$1$next[1:0]$8006 + attribute \src "libresoc.v:156334.3-156346.6" + wire $1\neg_res$15$next[0:0]$8046 + attribute \src "libresoc.v:156347.3-156359.6" + wire $1\neg_res32$16$next[0:0]$8049 + attribute \src "libresoc.v:156308.3-156320.6" + wire width 129 $1\o$next[128:0]$8040 + attribute \src "libresoc.v:156129.15-156129.57" wire width 129 $1\o[128:0] - attribute \src "libresoc.v:155473.3-155490.6" - wire $1\r_busy$next[0:0]$8070 - attribute \src "libresoc.v:155375.7-155375.20" + attribute \src "libresoc.v:156241.3-156258.6" + wire $1\r_busy$next[0:0]$8002 + attribute \src "libresoc.v:156143.7-156143.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:155553.3-155565.6" - wire $1\xer_so$14$next[0:0]$8111 - attribute \src "libresoc.v:155504.3-155539.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8100 - attribute \src "libresoc.v:155504.3-155539.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$8101 - attribute \src "libresoc.v:155504.3-155539.6" - wire $2\mul_op__oe__oe$8$next[0:0]$8102 - attribute \src "libresoc.v:155504.3-155539.6" - wire $2\mul_op__oe__ok$9$next[0:0]$8103 - attribute \src "libresoc.v:155504.3-155539.6" - wire $2\mul_op__rc__ok$7$next[0:0]$8104 - attribute \src "libresoc.v:155504.3-155539.6" - wire $2\mul_op__rc__rc$6$next[0:0]$8105 - attribute \src "libresoc.v:155473.3-155490.6" - wire $2\r_busy$next[0:0]$8071 - attribute \src "libresoc.v:155391.18-155391.118" - wire $and$libresoc.v:155391$8033_Y + attribute \src "libresoc.v:156321.3-156333.6" + wire $1\xer_so$14$next[0:0]$8043 + attribute \src "libresoc.v:156272.3-156307.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8032 + attribute \src "libresoc.v:156272.3-156307.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8033 + attribute \src "libresoc.v:156272.3-156307.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8034 + attribute \src "libresoc.v:156272.3-156307.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8035 + attribute \src "libresoc.v:156272.3-156307.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8036 + attribute \src "libresoc.v:156272.3-156307.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8037 + attribute \src "libresoc.v:156241.3-156258.6" + wire $2\r_busy$next[0:0]$8003 + attribute \src "libresoc.v:156159.18-156159.118" + wire $and$libresoc.v:156159$7965_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:154691.7-154691.15" + attribute \src "libresoc.v:155459.7-155459.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -323511,7 +290054,7 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$50 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:155391$8033 + cell $and $and$libresoc.v:156159$7965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323519,10 +290062,10 @@ module \mul_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$33 connect \B \p_ready_o - connect \Y $and$libresoc.v:155391$8033_Y + connect \Y $and$libresoc.v:156159$7965_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:155428.8-155464.4" + attribute \src "libresoc.v:156196.8-156232.4" cell \mul2 \mul2 connect \mul_op__fn_unit \mul2_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 @@ -323561,304 +290104,304 @@ module \mul_pipe2 connect \xer_so$14 \mul2_xer_so$30 end attribute \module_not_derived 1 - attribute \src "libresoc.v:155465.10-155468.4" + attribute \src "libresoc.v:156233.10-156236.4" cell \n$97 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:155469.10-155472.4" + attribute \src "libresoc.v:156237.10-156240.4" cell \p$96 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:154691.7-154691.20" - process $proc$libresoc.v:154691$8118 + attribute \src "libresoc.v:155459.7-155459.20" + process $proc$libresoc.v:155459$8050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:154982.14-154982.44" - process $proc$libresoc.v:154982$8119 + attribute \src "libresoc.v:155750.14-155750.44" + process $proc$libresoc.v:155750$8051 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$8120 14'00000000000000 + assign $0\mul_op__fn_unit$3[13:0]$8052 14'00000000000000 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8120 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8052 end - attribute \src "libresoc.v:155008.14-155008.63" - process $proc$libresoc.v:155008$8121 + attribute \src "libresoc.v:155776.14-155776.63" + process $proc$libresoc.v:155776$8053 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8122 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\mul_op__imm_data__data$4[63:0]$8054 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8122 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8054 end - attribute \src "libresoc.v:155017.7-155017.38" - process $proc$libresoc.v:155017$8123 + attribute \src "libresoc.v:155785.7-155785.38" + process $proc$libresoc.v:155785$8055 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8124 1'0 + assign $0\mul_op__imm_data__ok$5[0:0]$8056 1'0 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8124 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8056 end - attribute \src "libresoc.v:155024.14-155024.39" - process $proc$libresoc.v:155024$8125 + attribute \src "libresoc.v:155792.14-155792.39" + process $proc$libresoc.v:155792$8057 assign { } { } - assign $0\mul_op__insn$13[31:0]$8126 0 + assign $0\mul_op__insn$13[31:0]$8058 0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8126 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8058 end - attribute \src "libresoc.v:155183.13-155183.42" - process $proc$libresoc.v:155183$8127 + attribute \src "libresoc.v:155951.13-155951.42" + process $proc$libresoc.v:155951$8059 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8128 7'0000000 + assign $0\mul_op__insn_type$2[6:0]$8060 7'0000000 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8128 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8060 end - attribute \src "libresoc.v:155267.7-155267.35" - process $proc$libresoc.v:155267$8129 + attribute \src "libresoc.v:156035.7-156035.35" + process $proc$libresoc.v:156035$8061 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8130 1'0 + assign $0\mul_op__is_32bit$11[0:0]$8062 1'0 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8130 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8062 end - attribute \src "libresoc.v:155276.7-155276.36" - process $proc$libresoc.v:155276$8131 + attribute \src "libresoc.v:156044.7-156044.36" + process $proc$libresoc.v:156044$8063 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8132 1'0 + assign $0\mul_op__is_signed$12[0:0]$8064 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8132 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8064 end - attribute \src "libresoc.v:155287.7-155287.32" - process $proc$libresoc.v:155287$8133 + attribute \src "libresoc.v:156055.7-156055.32" + process $proc$libresoc.v:156055$8065 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8134 1'0 + assign $0\mul_op__oe__oe$8[0:0]$8066 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8134 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8066 end - attribute \src "libresoc.v:155296.7-155296.32" - process $proc$libresoc.v:155296$8135 + attribute \src "libresoc.v:156064.7-156064.32" + process $proc$libresoc.v:156064$8067 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8136 1'0 + assign $0\mul_op__oe__ok$9[0:0]$8068 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8136 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8068 end - attribute \src "libresoc.v:155305.7-155305.32" - process $proc$libresoc.v:155305$8137 + attribute \src "libresoc.v:156073.7-156073.32" + process $proc$libresoc.v:156073$8069 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8138 1'0 + assign $0\mul_op__rc__ok$7[0:0]$8070 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8138 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8070 end - attribute \src "libresoc.v:155314.7-155314.32" - process $proc$libresoc.v:155314$8139 + attribute \src "libresoc.v:156082.7-156082.32" + process $proc$libresoc.v:156082$8071 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8140 1'0 + assign $0\mul_op__rc__rc$6[0:0]$8072 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8140 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8072 end - attribute \src "libresoc.v:155321.7-155321.36" - process $proc$libresoc.v:155321$8141 + attribute \src "libresoc.v:156089.7-156089.36" + process $proc$libresoc.v:156089$8073 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8142 1'0 + assign $0\mul_op__write_cr0$10[0:0]$8074 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8142 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8074 end - attribute \src "libresoc.v:155330.13-155330.29" - process $proc$libresoc.v:155330$8143 + attribute \src "libresoc.v:156098.13-156098.29" + process $proc$libresoc.v:156098$8075 assign { } { } - assign $0\muxid$1[1:0]$8144 2'00 + assign $0\muxid$1[1:0]$8076 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8144 + update \muxid$1 $0\muxid$1[1:0]$8076 end - attribute \src "libresoc.v:155345.7-155345.26" - process $proc$libresoc.v:155345$8145 + attribute \src "libresoc.v:156113.7-156113.26" + process $proc$libresoc.v:156113$8077 assign { } { } - assign $0\neg_res$15[0:0]$8146 1'0 + assign $0\neg_res$15[0:0]$8078 1'0 sync always sync init - update \neg_res$15 $0\neg_res$15[0:0]$8146 + update \neg_res$15 $0\neg_res$15[0:0]$8078 end - attribute \src "libresoc.v:155354.7-155354.28" - process $proc$libresoc.v:155354$8147 + attribute \src "libresoc.v:156122.7-156122.28" + process $proc$libresoc.v:156122$8079 assign { } { } - assign $0\neg_res32$16[0:0]$8148 1'0 + assign $0\neg_res32$16[0:0]$8080 1'0 sync always sync init - update \neg_res32$16 $0\neg_res32$16[0:0]$8148 + update \neg_res32$16 $0\neg_res32$16[0:0]$8080 end - attribute \src "libresoc.v:155361.15-155361.57" - process $proc$libresoc.v:155361$8149 + attribute \src "libresoc.v:156129.15-156129.57" + process $proc$libresoc.v:156129$8081 assign { } { } assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[128:0] end - attribute \src "libresoc.v:155375.7-155375.20" - process $proc$libresoc.v:155375$8150 + attribute \src "libresoc.v:156143.7-156143.20" + process $proc$libresoc.v:156143$8082 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:155386.7-155386.25" - process $proc$libresoc.v:155386$8151 + attribute \src "libresoc.v:156154.7-156154.25" + process $proc$libresoc.v:156154$8083 assign { } { } - assign $0\xer_so$14[0:0]$8152 1'0 + assign $0\xer_so$14[0:0]$8084 1'0 sync always sync init - update \xer_so$14 $0\xer_so$14[0:0]$8152 + update \xer_so$14 $0\xer_so$14[0:0]$8084 end - attribute \src "libresoc.v:155392.3-155393.43" - process $proc$libresoc.v:155392$8034 + attribute \src "libresoc.v:156160.3-156161.43" + process $proc$libresoc.v:156160$7966 assign { } { } - assign $0\neg_res32$16[0:0]$8035 \neg_res32$16$next + assign $0\neg_res32$16[0:0]$7967 \neg_res32$16$next sync posedge \coresync_clk - update \neg_res32$16 $0\neg_res32$16[0:0]$8035 + update \neg_res32$16 $0\neg_res32$16[0:0]$7967 end - attribute \src "libresoc.v:155394.3-155395.39" - process $proc$libresoc.v:155394$8036 + attribute \src "libresoc.v:156162.3-156163.39" + process $proc$libresoc.v:156162$7968 assign { } { } - assign $0\neg_res$15[0:0]$8037 \neg_res$15$next + assign $0\neg_res$15[0:0]$7969 \neg_res$15$next sync posedge \coresync_clk - update \neg_res$15 $0\neg_res$15[0:0]$8037 + update \neg_res$15 $0\neg_res$15[0:0]$7969 end - attribute \src "libresoc.v:155396.3-155397.37" - process $proc$libresoc.v:155396$8038 + attribute \src "libresoc.v:156164.3-156165.37" + process $proc$libresoc.v:156164$7970 assign { } { } - assign $0\xer_so$14[0:0]$8039 \xer_so$14$next + assign $0\xer_so$14[0:0]$7971 \xer_so$14$next sync posedge \coresync_clk - update \xer_so$14 $0\xer_so$14[0:0]$8039 + update \xer_so$14 $0\xer_so$14[0:0]$7971 end - attribute \src "libresoc.v:155398.3-155399.19" - process $proc$libresoc.v:155398$8040 + attribute \src "libresoc.v:156166.3-156167.19" + process $proc$libresoc.v:156166$7972 assign { } { } assign $0\o[128:0] \o$next sync posedge \coresync_clk update \o $0\o[128:0] end - attribute \src "libresoc.v:155400.3-155401.57" - process $proc$libresoc.v:155400$8041 + attribute \src "libresoc.v:156168.3-156169.57" + process $proc$libresoc.v:156168$7973 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8042 \mul_op__insn_type$2$next + assign $0\mul_op__insn_type$2[6:0]$7974 \mul_op__insn_type$2$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8042 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7974 end - attribute \src "libresoc.v:155402.3-155403.53" - process $proc$libresoc.v:155402$8043 + attribute \src "libresoc.v:156170.3-156171.53" + process $proc$libresoc.v:156170$7975 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$8044 \mul_op__fn_unit$3$next + assign $0\mul_op__fn_unit$3[13:0]$7976 \mul_op__fn_unit$3$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8044 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$7976 end - attribute \src "libresoc.v:155404.3-155405.67" - process $proc$libresoc.v:155404$8045 + attribute \src "libresoc.v:156172.3-156173.67" + process $proc$libresoc.v:156172$7977 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8046 \mul_op__imm_data__data$4$next + assign $0\mul_op__imm_data__data$4[63:0]$7978 \mul_op__imm_data__data$4$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8046 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7978 end - attribute \src "libresoc.v:155406.3-155407.63" - process $proc$libresoc.v:155406$8047 + attribute \src "libresoc.v:156174.3-156175.63" + process $proc$libresoc.v:156174$7979 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8048 \mul_op__imm_data__ok$5$next + assign $0\mul_op__imm_data__ok$5[0:0]$7980 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8048 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7980 end - attribute \src "libresoc.v:155408.3-155409.51" - process $proc$libresoc.v:155408$8049 + attribute \src "libresoc.v:156176.3-156177.51" + process $proc$libresoc.v:156176$7981 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8050 \mul_op__rc__rc$6$next + assign $0\mul_op__rc__rc$6[0:0]$7982 \mul_op__rc__rc$6$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8050 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7982 end - attribute \src "libresoc.v:155410.3-155411.51" - process $proc$libresoc.v:155410$8051 + attribute \src "libresoc.v:156178.3-156179.51" + process $proc$libresoc.v:156178$7983 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8052 \mul_op__rc__ok$7$next + assign $0\mul_op__rc__ok$7[0:0]$7984 \mul_op__rc__ok$7$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8052 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7984 end - attribute \src "libresoc.v:155412.3-155413.51" - process $proc$libresoc.v:155412$8053 + attribute \src "libresoc.v:156180.3-156181.51" + process $proc$libresoc.v:156180$7985 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8054 \mul_op__oe__oe$8$next + assign $0\mul_op__oe__oe$8[0:0]$7986 \mul_op__oe__oe$8$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8054 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7986 end - attribute \src "libresoc.v:155414.3-155415.51" - process $proc$libresoc.v:155414$8055 + attribute \src "libresoc.v:156182.3-156183.51" + process $proc$libresoc.v:156182$7987 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8056 \mul_op__oe__ok$9$next + assign $0\mul_op__oe__ok$9[0:0]$7988 \mul_op__oe__ok$9$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8056 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7988 end - attribute \src "libresoc.v:155416.3-155417.59" - process $proc$libresoc.v:155416$8057 + attribute \src "libresoc.v:156184.3-156185.59" + process $proc$libresoc.v:156184$7989 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8058 \mul_op__write_cr0$10$next + assign $0\mul_op__write_cr0$10[0:0]$7990 \mul_op__write_cr0$10$next sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8058 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7990 end - attribute \src "libresoc.v:155418.3-155419.57" - process $proc$libresoc.v:155418$8059 + attribute \src "libresoc.v:156186.3-156187.57" + process $proc$libresoc.v:156186$7991 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8060 \mul_op__is_32bit$11$next + assign $0\mul_op__is_32bit$11[0:0]$7992 \mul_op__is_32bit$11$next sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8060 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7992 end - attribute \src "libresoc.v:155420.3-155421.59" - process $proc$libresoc.v:155420$8061 + attribute \src "libresoc.v:156188.3-156189.59" + process $proc$libresoc.v:156188$7993 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8062 \mul_op__is_signed$12$next + assign $0\mul_op__is_signed$12[0:0]$7994 \mul_op__is_signed$12$next sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8062 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7994 end - attribute \src "libresoc.v:155422.3-155423.49" - process $proc$libresoc.v:155422$8063 + attribute \src "libresoc.v:156190.3-156191.49" + process $proc$libresoc.v:156190$7995 assign { } { } - assign $0\mul_op__insn$13[31:0]$8064 \mul_op__insn$13$next + assign $0\mul_op__insn$13[31:0]$7996 \mul_op__insn$13$next sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8064 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7996 end - attribute \src "libresoc.v:155424.3-155425.33" - process $proc$libresoc.v:155424$8065 + attribute \src "libresoc.v:156192.3-156193.33" + process $proc$libresoc.v:156192$7997 assign { } { } - assign $0\muxid$1[1:0]$8066 \muxid$1$next + assign $0\muxid$1[1:0]$7998 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8066 + update \muxid$1 $0\muxid$1[1:0]$7998 end - attribute \src "libresoc.v:155426.3-155427.29" - process $proc$libresoc.v:155426$8067 + attribute \src "libresoc.v:156194.3-156195.29" + process $proc$libresoc.v:156194$7999 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:155473.3-155490.6" - process $proc$libresoc.v:155473$8068 + attribute \src "libresoc.v:156241.3-156258.6" + process $proc$libresoc.v:156241$8000 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8069 $2\r_busy$next[0:0]$8071 - attribute \src "libresoc.v:155474.5-155474.29" + assign $0\r_busy$next[0:0]$8001 $2\r_busy$next[0:0]$8003 + attribute \src "libresoc.v:156242.5-156242.29" switch \initial - attribute \src "libresoc.v:155474.9-155474.17" + attribute \src "libresoc.v:156242.9-156242.17" case 1'1 case end @@ -323867,34 +290410,34 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8070 1'1 + assign $1\r_busy$next[0:0]$8002 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8070 1'0 + assign $1\r_busy$next[0:0]$8002 1'0 case - assign $1\r_busy$next[0:0]$8070 \r_busy + assign $1\r_busy$next[0:0]$8002 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8071 1'0 + assign $2\r_busy$next[0:0]$8003 1'0 case - assign $2\r_busy$next[0:0]$8071 $1\r_busy$next[0:0]$8070 + assign $2\r_busy$next[0:0]$8003 $1\r_busy$next[0:0]$8002 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8069 + update \r_busy$next $0\r_busy$next[0:0]$8001 end - attribute \src "libresoc.v:155491.3-155503.6" - process $proc$libresoc.v:155491$8072 + attribute \src "libresoc.v:156259.3-156271.6" + process $proc$libresoc.v:156259$8004 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8073 $1\muxid$1$next[1:0]$8074 - attribute \src "libresoc.v:155492.5-155492.29" + assign $0\muxid$1$next[1:0]$8005 $1\muxid$1$next[1:0]$8006 + attribute \src "libresoc.v:156260.5-156260.29" switch \initial - attribute \src "libresoc.v:155492.9-155492.17" + attribute \src "libresoc.v:156260.9-156260.17" case 1'1 case end @@ -323903,19 +290446,19 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8074 \muxid$36 + assign $1\muxid$1$next[1:0]$8006 \muxid$36 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8074 \muxid$36 + assign $1\muxid$1$next[1:0]$8006 \muxid$36 case - assign $1\muxid$1$next[1:0]$8074 \muxid$1 + assign $1\muxid$1$next[1:0]$8006 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8073 + update \muxid$1$next $0\muxid$1$next[1:0]$8005 end - attribute \src "libresoc.v:155504.3-155539.6" - process $proc$libresoc.v:155504$8075 + attribute \src "libresoc.v:156272.3-156307.6" + process $proc$libresoc.v:156272$8007 assign { } { } assign { } { } assign { } { } @@ -323940,27 +290483,27 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[13:0]$8076 $1\mul_op__fn_unit$3$next[13:0]$8088 + assign $0\mul_op__fn_unit$3$next[13:0]$8008 $1\mul_op__fn_unit$3$next[13:0]$8020 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$8079 $1\mul_op__insn$13$next[31:0]$8091 - assign $0\mul_op__insn_type$2$next[6:0]$8080 $1\mul_op__insn_type$2$next[6:0]$8092 - assign $0\mul_op__is_32bit$11$next[0:0]$8081 $1\mul_op__is_32bit$11$next[0:0]$8093 - assign $0\mul_op__is_signed$12$next[0:0]$8082 $1\mul_op__is_signed$12$next[0:0]$8094 + assign $0\mul_op__insn$13$next[31:0]$8011 $1\mul_op__insn$13$next[31:0]$8023 + assign $0\mul_op__insn_type$2$next[6:0]$8012 $1\mul_op__insn_type$2$next[6:0]$8024 + assign $0\mul_op__is_32bit$11$next[0:0]$8013 $1\mul_op__is_32bit$11$next[0:0]$8025 + assign $0\mul_op__is_signed$12$next[0:0]$8014 $1\mul_op__is_signed$12$next[0:0]$8026 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$8087 $1\mul_op__write_cr0$10$next[0:0]$8099 - assign $0\mul_op__imm_data__data$4$next[63:0]$8077 $2\mul_op__imm_data__data$4$next[63:0]$8100 - assign $0\mul_op__imm_data__ok$5$next[0:0]$8078 $2\mul_op__imm_data__ok$5$next[0:0]$8101 - assign $0\mul_op__oe__oe$8$next[0:0]$8083 $2\mul_op__oe__oe$8$next[0:0]$8102 - assign $0\mul_op__oe__ok$9$next[0:0]$8084 $2\mul_op__oe__ok$9$next[0:0]$8103 - assign $0\mul_op__rc__ok$7$next[0:0]$8085 $2\mul_op__rc__ok$7$next[0:0]$8104 - assign $0\mul_op__rc__rc$6$next[0:0]$8086 $2\mul_op__rc__rc$6$next[0:0]$8105 - attribute \src "libresoc.v:155505.5-155505.29" + assign $0\mul_op__write_cr0$10$next[0:0]$8019 $1\mul_op__write_cr0$10$next[0:0]$8031 + assign $0\mul_op__imm_data__data$4$next[63:0]$8009 $2\mul_op__imm_data__data$4$next[63:0]$8032 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8010 $2\mul_op__imm_data__ok$5$next[0:0]$8033 + assign $0\mul_op__oe__oe$8$next[0:0]$8015 $2\mul_op__oe__oe$8$next[0:0]$8034 + assign $0\mul_op__oe__ok$9$next[0:0]$8016 $2\mul_op__oe__ok$9$next[0:0]$8035 + assign $0\mul_op__rc__ok$7$next[0:0]$8017 $2\mul_op__rc__ok$7$next[0:0]$8036 + assign $0\mul_op__rc__rc$6$next[0:0]$8018 $2\mul_op__rc__rc$6$next[0:0]$8037 + attribute \src "libresoc.v:156273.5-156273.29" switch \initial - attribute \src "libresoc.v:155505.9-155505.17" + attribute \src "libresoc.v:156273.9-156273.17" case 1'1 case end @@ -323980,7 +290523,7 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8091 $1\mul_op__is_signed$12$next[0:0]$8094 $1\mul_op__is_32bit$11$next[0:0]$8093 $1\mul_op__write_cr0$10$next[0:0]$8099 $1\mul_op__oe__ok$9$next[0:0]$8096 $1\mul_op__oe__oe$8$next[0:0]$8095 $1\mul_op__rc__ok$7$next[0:0]$8097 $1\mul_op__rc__rc$6$next[0:0]$8098 $1\mul_op__imm_data__ok$5$next[0:0]$8090 $1\mul_op__imm_data__data$4$next[63:0]$8089 $1\mul_op__fn_unit$3$next[13:0]$8088 $1\mul_op__insn_type$2$next[6:0]$8092 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { $1\mul_op__insn$13$next[31:0]$8023 $1\mul_op__is_signed$12$next[0:0]$8026 $1\mul_op__is_32bit$11$next[0:0]$8025 $1\mul_op__write_cr0$10$next[0:0]$8031 $1\mul_op__oe__ok$9$next[0:0]$8028 $1\mul_op__oe__oe$8$next[0:0]$8027 $1\mul_op__rc__ok$7$next[0:0]$8029 $1\mul_op__rc__rc$6$next[0:0]$8030 $1\mul_op__imm_data__ok$5$next[0:0]$8022 $1\mul_op__imm_data__data$4$next[63:0]$8021 $1\mul_op__fn_unit$3$next[13:0]$8020 $1\mul_op__insn_type$2$next[6:0]$8024 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -323995,20 +290538,20 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8091 $1\mul_op__is_signed$12$next[0:0]$8094 $1\mul_op__is_32bit$11$next[0:0]$8093 $1\mul_op__write_cr0$10$next[0:0]$8099 $1\mul_op__oe__ok$9$next[0:0]$8096 $1\mul_op__oe__oe$8$next[0:0]$8095 $1\mul_op__rc__ok$7$next[0:0]$8097 $1\mul_op__rc__rc$6$next[0:0]$8098 $1\mul_op__imm_data__ok$5$next[0:0]$8090 $1\mul_op__imm_data__data$4$next[63:0]$8089 $1\mul_op__fn_unit$3$next[13:0]$8088 $1\mul_op__insn_type$2$next[6:0]$8092 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { $1\mul_op__insn$13$next[31:0]$8023 $1\mul_op__is_signed$12$next[0:0]$8026 $1\mul_op__is_32bit$11$next[0:0]$8025 $1\mul_op__write_cr0$10$next[0:0]$8031 $1\mul_op__oe__ok$9$next[0:0]$8028 $1\mul_op__oe__oe$8$next[0:0]$8027 $1\mul_op__rc__ok$7$next[0:0]$8029 $1\mul_op__rc__rc$6$next[0:0]$8030 $1\mul_op__imm_data__ok$5$next[0:0]$8022 $1\mul_op__imm_data__data$4$next[63:0]$8021 $1\mul_op__fn_unit$3$next[13:0]$8020 $1\mul_op__insn_type$2$next[6:0]$8024 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } case - assign $1\mul_op__fn_unit$3$next[13:0]$8088 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$8089 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$8090 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$8091 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$8092 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$8093 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$8094 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$8095 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$8096 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$8097 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$8098 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$8099 \mul_op__write_cr0$10 + assign $1\mul_op__fn_unit$3$next[13:0]$8020 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8021 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8022 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8023 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8024 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8025 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8026 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8027 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8028 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8029 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8030 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8031 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -324020,42 +290563,42 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$8100 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8101 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$8105 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$8104 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$8102 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$8103 1'0 + assign $2\mul_op__imm_data__data$4$next[63:0]$8032 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8033 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8037 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8036 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8034 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8035 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$8100 $1\mul_op__imm_data__data$4$next[63:0]$8089 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8101 $1\mul_op__imm_data__ok$5$next[0:0]$8090 - assign $2\mul_op__oe__oe$8$next[0:0]$8102 $1\mul_op__oe__oe$8$next[0:0]$8095 - assign $2\mul_op__oe__ok$9$next[0:0]$8103 $1\mul_op__oe__ok$9$next[0:0]$8096 - assign $2\mul_op__rc__ok$7$next[0:0]$8104 $1\mul_op__rc__ok$7$next[0:0]$8097 - assign $2\mul_op__rc__rc$6$next[0:0]$8105 $1\mul_op__rc__rc$6$next[0:0]$8098 + assign $2\mul_op__imm_data__data$4$next[63:0]$8032 $1\mul_op__imm_data__data$4$next[63:0]$8021 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8033 $1\mul_op__imm_data__ok$5$next[0:0]$8022 + assign $2\mul_op__oe__oe$8$next[0:0]$8034 $1\mul_op__oe__oe$8$next[0:0]$8027 + assign $2\mul_op__oe__ok$9$next[0:0]$8035 $1\mul_op__oe__ok$9$next[0:0]$8028 + assign $2\mul_op__rc__ok$7$next[0:0]$8036 $1\mul_op__rc__ok$7$next[0:0]$8029 + assign $2\mul_op__rc__rc$6$next[0:0]$8037 $1\mul_op__rc__rc$6$next[0:0]$8030 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8076 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8077 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8078 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8079 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8080 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8081 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8082 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8083 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8084 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8085 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8086 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8087 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8008 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8009 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8010 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8011 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8012 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8013 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8014 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8015 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8016 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8017 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8018 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8019 end - attribute \src "libresoc.v:155540.3-155552.6" - process $proc$libresoc.v:155540$8106 + attribute \src "libresoc.v:156308.3-156320.6" + process $proc$libresoc.v:156308$8038 assign { } { } assign { } { } - assign $0\o$next[128:0]$8107 $1\o$next[128:0]$8108 - attribute \src "libresoc.v:155541.5-155541.29" + assign $0\o$next[128:0]$8039 $1\o$next[128:0]$8040 + attribute \src "libresoc.v:156309.5-156309.29" switch \initial - attribute \src "libresoc.v:155541.9-155541.17" + attribute \src "libresoc.v:156309.9-156309.17" case 1'1 case end @@ -324064,25 +290607,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\o$next[128:0]$8108 \o$49 + assign $1\o$next[128:0]$8040 \o$49 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\o$next[128:0]$8108 \o$49 + assign $1\o$next[128:0]$8040 \o$49 case - assign $1\o$next[128:0]$8108 \o + assign $1\o$next[128:0]$8040 \o end sync always - update \o$next $0\o$next[128:0]$8107 + update \o$next $0\o$next[128:0]$8039 end - attribute \src "libresoc.v:155553.3-155565.6" - process $proc$libresoc.v:155553$8109 + attribute \src "libresoc.v:156321.3-156333.6" + process $proc$libresoc.v:156321$8041 assign { } { } assign { } { } - assign $0\xer_so$14$next[0:0]$8110 $1\xer_so$14$next[0:0]$8111 - attribute \src "libresoc.v:155554.5-155554.29" + assign $0\xer_so$14$next[0:0]$8042 $1\xer_so$14$next[0:0]$8043 + attribute \src "libresoc.v:156322.5-156322.29" switch \initial - attribute \src "libresoc.v:155554.9-155554.17" + attribute \src "libresoc.v:156322.9-156322.17" case 1'1 case end @@ -324091,25 +290634,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$14$next[0:0]$8111 \xer_so$50 + assign $1\xer_so$14$next[0:0]$8043 \xer_so$50 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$14$next[0:0]$8111 \xer_so$50 + assign $1\xer_so$14$next[0:0]$8043 \xer_so$50 case - assign $1\xer_so$14$next[0:0]$8111 \xer_so$14 + assign $1\xer_so$14$next[0:0]$8043 \xer_so$14 end sync always - update \xer_so$14$next $0\xer_so$14$next[0:0]$8110 + update \xer_so$14$next $0\xer_so$14$next[0:0]$8042 end - attribute \src "libresoc.v:155566.3-155578.6" - process $proc$libresoc.v:155566$8112 + attribute \src "libresoc.v:156334.3-156346.6" + process $proc$libresoc.v:156334$8044 assign { } { } assign { } { } - assign $0\neg_res$15$next[0:0]$8113 $1\neg_res$15$next[0:0]$8114 - attribute \src "libresoc.v:155567.5-155567.29" + assign $0\neg_res$15$next[0:0]$8045 $1\neg_res$15$next[0:0]$8046 + attribute \src "libresoc.v:156335.5-156335.29" switch \initial - attribute \src "libresoc.v:155567.9-155567.17" + attribute \src "libresoc.v:156335.9-156335.17" case 1'1 case end @@ -324118,25 +290661,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res$15$next[0:0]$8114 \neg_res$51 + assign $1\neg_res$15$next[0:0]$8046 \neg_res$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res$15$next[0:0]$8114 \neg_res$51 + assign $1\neg_res$15$next[0:0]$8046 \neg_res$51 case - assign $1\neg_res$15$next[0:0]$8114 \neg_res$15 + assign $1\neg_res$15$next[0:0]$8046 \neg_res$15 end sync always - update \neg_res$15$next $0\neg_res$15$next[0:0]$8113 + update \neg_res$15$next $0\neg_res$15$next[0:0]$8045 end - attribute \src "libresoc.v:155579.3-155591.6" - process $proc$libresoc.v:155579$8115 + attribute \src "libresoc.v:156347.3-156359.6" + process $proc$libresoc.v:156347$8047 assign { } { } assign { } { } - assign $0\neg_res32$16$next[0:0]$8116 $1\neg_res32$16$next[0:0]$8117 - attribute \src "libresoc.v:155580.5-155580.29" + assign $0\neg_res32$16$next[0:0]$8048 $1\neg_res32$16$next[0:0]$8049 + attribute \src "libresoc.v:156348.5-156348.29" switch \initial - attribute \src "libresoc.v:155580.9-155580.17" + attribute \src "libresoc.v:156348.9-156348.17" case 1'1 case end @@ -324145,18 +290688,18 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$52 + assign $1\neg_res32$16$next[0:0]$8049 \neg_res32$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$52 + assign $1\neg_res32$16$next[0:0]$8049 \neg_res32$52 case - assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$16 + assign $1\neg_res32$16$next[0:0]$8049 \neg_res32$16 end sync always - update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8116 + update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8048 end - connect \$34 $and$libresoc.v:155391$8033_Y + connect \$34 $and$libresoc.v:156159$7965_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$52 \mul2_neg_res32$32 @@ -324176,238 +290719,238 @@ module \mul_pipe2 connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul2_muxid \muxid end -attribute \src "libresoc.v:155614.1-156910.10" +attribute \src "libresoc.v:156382.1-157678.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" attribute \generator "nMigen" module \mul_pipe3 - attribute \src "libresoc.v:156828.3-156846.6" - wire width 4 $0\cr_a$next[3:0]$8236 - attribute \src "libresoc.v:156620.3-156621.25" + attribute \src "libresoc.v:157596.3-157614.6" + wire width 4 $0\cr_a$next[3:0]$8168 + attribute \src "libresoc.v:157388.3-157389.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:156828.3-156846.6" - wire $0\cr_a_ok$next[0:0]$8237 - attribute \src "libresoc.v:156622.3-156623.31" + attribute \src "libresoc.v:157596.3-157614.6" + wire $0\cr_a_ok$next[0:0]$8169 + attribute \src "libresoc.v:157390.3-157391.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:155615.7-155615.20" + attribute \src "libresoc.v:156383.7-156383.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156773.3-156808.6" - wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8199 - attribute \src "libresoc.v:156630.3-156631.53" - wire width 14 $0\mul_op__fn_unit$3[13:0]$8167 - attribute \src "libresoc.v:155926.14-155926.44" - wire width 14 $0\mul_op__fn_unit$3[13:0]$8257 - attribute \src "libresoc.v:156773.3-156808.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8200 - attribute \src "libresoc.v:156632.3-156633.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8169 - attribute \src "libresoc.v:155950.14-155950.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8259 - attribute \src "libresoc.v:156773.3-156808.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$8201 - attribute \src "libresoc.v:156634.3-156635.63" - wire $0\mul_op__imm_data__ok$5[0:0]$8171 - attribute \src "libresoc.v:155959.7-155959.38" - wire $0\mul_op__imm_data__ok$5[0:0]$8261 - attribute \src "libresoc.v:156773.3-156808.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$8202 - attribute \src "libresoc.v:156650.3-156651.49" - wire width 32 $0\mul_op__insn$13[31:0]$8187 - attribute \src "libresoc.v:155968.14-155968.39" - wire width 32 $0\mul_op__insn$13[31:0]$8263 - attribute \src "libresoc.v:156773.3-156808.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$8203 - attribute \src "libresoc.v:156628.3-156629.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$8165 - attribute \src "libresoc.v:156127.13-156127.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$8265 - attribute \src "libresoc.v:156773.3-156808.6" - wire $0\mul_op__is_32bit$11$next[0:0]$8204 - attribute \src "libresoc.v:156646.3-156647.57" - wire $0\mul_op__is_32bit$11[0:0]$8183 - attribute \src "libresoc.v:156211.7-156211.35" - wire $0\mul_op__is_32bit$11[0:0]$8267 - attribute \src "libresoc.v:156773.3-156808.6" - wire $0\mul_op__is_signed$12$next[0:0]$8205 - attribute \src "libresoc.v:156648.3-156649.59" - wire $0\mul_op__is_signed$12[0:0]$8185 - attribute \src "libresoc.v:156220.7-156220.36" - wire $0\mul_op__is_signed$12[0:0]$8269 - attribute \src "libresoc.v:156773.3-156808.6" - wire $0\mul_op__oe__oe$8$next[0:0]$8206 - attribute \src "libresoc.v:156640.3-156641.51" - wire $0\mul_op__oe__oe$8[0:0]$8177 - attribute \src "libresoc.v:156231.7-156231.32" - wire $0\mul_op__oe__oe$8[0:0]$8271 - attribute \src "libresoc.v:156773.3-156808.6" - wire $0\mul_op__oe__ok$9$next[0:0]$8207 - attribute \src "libresoc.v:156642.3-156643.51" - wire $0\mul_op__oe__ok$9[0:0]$8179 - attribute \src "libresoc.v:156240.7-156240.32" - wire $0\mul_op__oe__ok$9[0:0]$8273 - attribute \src "libresoc.v:156773.3-156808.6" - wire $0\mul_op__rc__ok$7$next[0:0]$8208 - attribute \src "libresoc.v:156638.3-156639.51" - wire $0\mul_op__rc__ok$7[0:0]$8175 - attribute \src "libresoc.v:156249.7-156249.32" - wire $0\mul_op__rc__ok$7[0:0]$8275 - attribute \src "libresoc.v:156773.3-156808.6" - wire $0\mul_op__rc__rc$6$next[0:0]$8209 - attribute \src "libresoc.v:156636.3-156637.51" - wire $0\mul_op__rc__rc$6[0:0]$8173 - attribute \src "libresoc.v:156256.7-156256.32" - wire $0\mul_op__rc__rc$6[0:0]$8277 - attribute \src "libresoc.v:156773.3-156808.6" - wire $0\mul_op__write_cr0$10$next[0:0]$8210 - attribute \src "libresoc.v:156644.3-156645.59" - wire $0\mul_op__write_cr0$10[0:0]$8181 - attribute \src "libresoc.v:156265.7-156265.36" - wire $0\mul_op__write_cr0$10[0:0]$8279 - attribute \src "libresoc.v:156760.3-156772.6" - wire width 2 $0\muxid$1$next[1:0]$8196 - attribute \src "libresoc.v:156652.3-156653.33" - wire width 2 $0\muxid$1[1:0]$8189 - attribute \src "libresoc.v:156274.13-156274.29" - wire width 2 $0\muxid$1[1:0]$8281 - attribute \src "libresoc.v:156809.3-156827.6" - wire width 64 $0\o$14$next[63:0]$8231 - attribute \src "libresoc.v:156624.3-156625.27" - wire width 64 $0\o$14[63:0]$8162 - attribute \src "libresoc.v:156295.14-156295.43" - wire width 64 $0\o$14[63:0]$8283 - attribute \src "libresoc.v:156809.3-156827.6" - wire $0\o_ok$next[0:0]$8230 - attribute \src "libresoc.v:156626.3-156627.25" + attribute \src "libresoc.v:157541.3-157576.6" + wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8131 + attribute \src "libresoc.v:157398.3-157399.53" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8099 + attribute \src "libresoc.v:156694.14-156694.44" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8189 + attribute \src "libresoc.v:157541.3-157576.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8132 + attribute \src "libresoc.v:157400.3-157401.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8101 + attribute \src "libresoc.v:156718.14-156718.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8191 + attribute \src "libresoc.v:157541.3-157576.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8133 + attribute \src "libresoc.v:157402.3-157403.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8103 + attribute \src "libresoc.v:156727.7-156727.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8193 + attribute \src "libresoc.v:157541.3-157576.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8134 + attribute \src "libresoc.v:157418.3-157419.49" + wire width 32 $0\mul_op__insn$13[31:0]$8119 + attribute \src "libresoc.v:156736.14-156736.39" + wire width 32 $0\mul_op__insn$13[31:0]$8195 + attribute \src "libresoc.v:157541.3-157576.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8135 + attribute \src "libresoc.v:157396.3-157397.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8097 + attribute \src "libresoc.v:156895.13-156895.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8197 + attribute \src "libresoc.v:157541.3-157576.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8136 + attribute \src "libresoc.v:157414.3-157415.57" + wire $0\mul_op__is_32bit$11[0:0]$8115 + attribute \src "libresoc.v:156979.7-156979.35" + wire $0\mul_op__is_32bit$11[0:0]$8199 + attribute \src "libresoc.v:157541.3-157576.6" + wire $0\mul_op__is_signed$12$next[0:0]$8137 + attribute \src "libresoc.v:157416.3-157417.59" + wire $0\mul_op__is_signed$12[0:0]$8117 + attribute \src "libresoc.v:156988.7-156988.36" + wire $0\mul_op__is_signed$12[0:0]$8201 + attribute \src "libresoc.v:157541.3-157576.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8138 + attribute \src "libresoc.v:157408.3-157409.51" + wire $0\mul_op__oe__oe$8[0:0]$8109 + attribute \src "libresoc.v:156999.7-156999.32" + wire $0\mul_op__oe__oe$8[0:0]$8203 + attribute \src "libresoc.v:157541.3-157576.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8139 + attribute \src "libresoc.v:157410.3-157411.51" + wire $0\mul_op__oe__ok$9[0:0]$8111 + attribute \src "libresoc.v:157008.7-157008.32" + wire $0\mul_op__oe__ok$9[0:0]$8205 + attribute \src "libresoc.v:157541.3-157576.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8140 + attribute \src "libresoc.v:157406.3-157407.51" + wire $0\mul_op__rc__ok$7[0:0]$8107 + attribute \src "libresoc.v:157017.7-157017.32" + wire $0\mul_op__rc__ok$7[0:0]$8207 + attribute \src "libresoc.v:157541.3-157576.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8141 + attribute \src "libresoc.v:157404.3-157405.51" + wire $0\mul_op__rc__rc$6[0:0]$8105 + attribute \src "libresoc.v:157024.7-157024.32" + wire $0\mul_op__rc__rc$6[0:0]$8209 + attribute \src "libresoc.v:157541.3-157576.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8142 + attribute \src "libresoc.v:157412.3-157413.59" + wire $0\mul_op__write_cr0$10[0:0]$8113 + attribute \src "libresoc.v:157033.7-157033.36" + wire $0\mul_op__write_cr0$10[0:0]$8211 + attribute \src "libresoc.v:157528.3-157540.6" + wire width 2 $0\muxid$1$next[1:0]$8128 + attribute \src "libresoc.v:157420.3-157421.33" + wire width 2 $0\muxid$1[1:0]$8121 + attribute \src "libresoc.v:157042.13-157042.29" + wire width 2 $0\muxid$1[1:0]$8213 + attribute \src "libresoc.v:157577.3-157595.6" + wire width 64 $0\o$14$next[63:0]$8163 + attribute \src "libresoc.v:157392.3-157393.27" + wire width 64 $0\o$14[63:0]$8094 + attribute \src "libresoc.v:157063.14-157063.43" + wire width 64 $0\o$14[63:0]$8215 + attribute \src "libresoc.v:157577.3-157595.6" + wire $0\o_ok$next[0:0]$8162 + attribute \src "libresoc.v:157394.3-157395.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:156742.3-156759.6" - wire $0\r_busy$next[0:0]$8192 - attribute \src "libresoc.v:156654.3-156655.29" + attribute \src "libresoc.v:157510.3-157527.6" + wire $0\r_busy$next[0:0]$8124 + attribute \src "libresoc.v:157422.3-157423.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:156847.3-156865.6" - wire width 2 $0\xer_ov$next[1:0]$8242 - attribute \src "libresoc.v:156616.3-156617.29" + attribute \src "libresoc.v:157615.3-157633.6" + wire width 2 $0\xer_ov$next[1:0]$8174 + attribute \src "libresoc.v:157384.3-157385.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:156847.3-156865.6" - wire $0\xer_ov_ok$next[0:0]$8243 - attribute \src "libresoc.v:156618.3-156619.35" + attribute \src "libresoc.v:157615.3-157633.6" + wire $0\xer_ov_ok$next[0:0]$8175 + attribute \src "libresoc.v:157386.3-157387.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:156866.3-156884.6" - wire $0\xer_so$15$next[0:0]$8249 - attribute \src "libresoc.v:156612.3-156613.37" - wire $0\xer_so$15[0:0]$8155 - attribute \src "libresoc.v:156597.7-156597.25" - wire $0\xer_so$15[0:0]$8289 - attribute \src "libresoc.v:156866.3-156884.6" - wire $0\xer_so_ok$next[0:0]$8248 - attribute \src "libresoc.v:156614.3-156615.35" + attribute \src "libresoc.v:157634.3-157652.6" + wire $0\xer_so$15$next[0:0]$8181 + attribute \src "libresoc.v:157380.3-157381.37" + wire $0\xer_so$15[0:0]$8087 + attribute \src "libresoc.v:157365.7-157365.25" + wire $0\xer_so$15[0:0]$8221 + attribute \src "libresoc.v:157634.3-157652.6" + wire $0\xer_so_ok$next[0:0]$8180 + attribute \src "libresoc.v:157382.3-157383.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:156828.3-156846.6" - wire width 4 $1\cr_a$next[3:0]$8238 - attribute \src "libresoc.v:155624.13-155624.24" + attribute \src "libresoc.v:157596.3-157614.6" + wire width 4 $1\cr_a$next[3:0]$8170 + attribute \src "libresoc.v:156392.13-156392.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:156828.3-156846.6" - wire $1\cr_a_ok$next[0:0]$8239 - attribute \src "libresoc.v:155633.7-155633.21" + attribute \src "libresoc.v:157596.3-157614.6" + wire $1\cr_a_ok$next[0:0]$8171 + attribute \src "libresoc.v:156401.7-156401.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:156773.3-156808.6" - wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8211 - attribute \src "libresoc.v:156773.3-156808.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8212 - attribute \src "libresoc.v:156773.3-156808.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$8213 - attribute \src "libresoc.v:156773.3-156808.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$8214 - attribute \src "libresoc.v:156773.3-156808.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$8215 - attribute \src "libresoc.v:156773.3-156808.6" - wire $1\mul_op__is_32bit$11$next[0:0]$8216 - attribute \src "libresoc.v:156773.3-156808.6" - wire $1\mul_op__is_signed$12$next[0:0]$8217 - attribute \src "libresoc.v:156773.3-156808.6" - wire $1\mul_op__oe__oe$8$next[0:0]$8218 - attribute \src "libresoc.v:156773.3-156808.6" - wire $1\mul_op__oe__ok$9$next[0:0]$8219 - attribute \src "libresoc.v:156773.3-156808.6" - wire $1\mul_op__rc__ok$7$next[0:0]$8220 - attribute \src "libresoc.v:156773.3-156808.6" - wire $1\mul_op__rc__rc$6$next[0:0]$8221 - attribute \src "libresoc.v:156773.3-156808.6" - wire $1\mul_op__write_cr0$10$next[0:0]$8222 - attribute \src "libresoc.v:156760.3-156772.6" - wire width 2 $1\muxid$1$next[1:0]$8197 - attribute \src "libresoc.v:156809.3-156827.6" - wire width 64 $1\o$14$next[63:0]$8233 - attribute \src "libresoc.v:156809.3-156827.6" - wire $1\o_ok$next[0:0]$8232 - attribute \src "libresoc.v:156302.7-156302.18" + attribute \src "libresoc.v:157541.3-157576.6" + wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8143 + attribute \src "libresoc.v:157541.3-157576.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8144 + attribute \src "libresoc.v:157541.3-157576.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8145 + attribute \src "libresoc.v:157541.3-157576.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8146 + attribute \src "libresoc.v:157541.3-157576.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8147 + attribute \src "libresoc.v:157541.3-157576.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8148 + attribute \src "libresoc.v:157541.3-157576.6" + wire $1\mul_op__is_signed$12$next[0:0]$8149 + attribute \src "libresoc.v:157541.3-157576.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8150 + attribute \src "libresoc.v:157541.3-157576.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8151 + attribute \src "libresoc.v:157541.3-157576.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8152 + attribute \src "libresoc.v:157541.3-157576.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8153 + attribute \src "libresoc.v:157541.3-157576.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8154 + attribute \src "libresoc.v:157528.3-157540.6" + wire width 2 $1\muxid$1$next[1:0]$8129 + attribute \src "libresoc.v:157577.3-157595.6" + wire width 64 $1\o$14$next[63:0]$8165 + attribute \src "libresoc.v:157577.3-157595.6" + wire $1\o_ok$next[0:0]$8164 + attribute \src "libresoc.v:157070.7-157070.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:156742.3-156759.6" - wire $1\r_busy$next[0:0]$8193 - attribute \src "libresoc.v:156574.7-156574.20" + attribute \src "libresoc.v:157510.3-157527.6" + wire $1\r_busy$next[0:0]$8125 + attribute \src "libresoc.v:157342.7-157342.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:156847.3-156865.6" - wire width 2 $1\xer_ov$next[1:0]$8244 - attribute \src "libresoc.v:156579.13-156579.26" + attribute \src "libresoc.v:157615.3-157633.6" + wire width 2 $1\xer_ov$next[1:0]$8176 + attribute \src "libresoc.v:157347.13-157347.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:156847.3-156865.6" - wire $1\xer_ov_ok$next[0:0]$8245 - attribute \src "libresoc.v:156586.7-156586.23" + attribute \src "libresoc.v:157615.3-157633.6" + wire $1\xer_ov_ok$next[0:0]$8177 + attribute \src "libresoc.v:157354.7-157354.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:156866.3-156884.6" - wire $1\xer_so$15$next[0:0]$8251 - attribute \src "libresoc.v:156866.3-156884.6" - wire $1\xer_so_ok$next[0:0]$8250 - attribute \src "libresoc.v:156604.7-156604.23" + attribute \src "libresoc.v:157634.3-157652.6" + wire $1\xer_so$15$next[0:0]$8183 + attribute \src "libresoc.v:157634.3-157652.6" + wire $1\xer_so_ok$next[0:0]$8182 + attribute \src "libresoc.v:157372.7-157372.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:156828.3-156846.6" - wire $2\cr_a_ok$next[0:0]$8240 - attribute \src "libresoc.v:156773.3-156808.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8223 - attribute \src "libresoc.v:156773.3-156808.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$8224 - attribute \src "libresoc.v:156773.3-156808.6" - wire $2\mul_op__oe__oe$8$next[0:0]$8225 - attribute \src "libresoc.v:156773.3-156808.6" - wire $2\mul_op__oe__ok$9$next[0:0]$8226 - attribute \src "libresoc.v:156773.3-156808.6" - wire $2\mul_op__rc__ok$7$next[0:0]$8227 - attribute \src "libresoc.v:156773.3-156808.6" - wire $2\mul_op__rc__rc$6$next[0:0]$8228 - attribute \src "libresoc.v:156809.3-156827.6" - wire $2\o_ok$next[0:0]$8234 - attribute \src "libresoc.v:156742.3-156759.6" - wire $2\r_busy$next[0:0]$8194 - attribute \src "libresoc.v:156847.3-156865.6" - wire $2\xer_ov_ok$next[0:0]$8246 - attribute \src "libresoc.v:156866.3-156884.6" - wire $2\xer_so_ok$next[0:0]$8252 - attribute \src "libresoc.v:156611.18-156611.118" - wire $and$libresoc.v:156611$8153_Y + attribute \src "libresoc.v:157596.3-157614.6" + wire $2\cr_a_ok$next[0:0]$8172 + attribute \src "libresoc.v:157541.3-157576.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8155 + attribute \src "libresoc.v:157541.3-157576.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8156 + attribute \src "libresoc.v:157541.3-157576.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8157 + attribute \src "libresoc.v:157541.3-157576.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8158 + attribute \src "libresoc.v:157541.3-157576.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8159 + attribute \src "libresoc.v:157541.3-157576.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8160 + attribute \src "libresoc.v:157577.3-157595.6" + wire $2\o_ok$next[0:0]$8166 + attribute \src "libresoc.v:157510.3-157527.6" + wire $2\r_busy$next[0:0]$8126 + attribute \src "libresoc.v:157615.3-157633.6" + wire $2\xer_ov_ok$next[0:0]$8178 + attribute \src "libresoc.v:157634.3-157652.6" + wire $2\xer_so_ok$next[0:0]$8184 + attribute \src "libresoc.v:157379.18-157379.118" + wire $and$libresoc.v:157379$8085_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 44 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 38 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 39 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next - attribute \src "libresoc.v:155615.7-155615.15" + attribute \src "libresoc.v:156383.7-156383.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -324645,19 +291188,19 @@ module \mul_pipe3 wire \mul3_neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 \mul3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \mul3_o$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul3_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \mul3_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul3_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul3_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul3_xer_so$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul3_xer_so_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -325047,23 +291590,23 @@ module \mul_pipe3 wire \neg_res32$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 input 17 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 36 \o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 37 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_cr_a_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -325297,25 +291840,25 @@ module \mul_pipe3 wire width 2 \output_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ov$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o @@ -325329,38 +291872,38 @@ module \mul_pipe3 wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 40 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 41 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 18 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 42 \xer_so$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 43 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:156611$8153 + cell $and $and$libresoc.v:157379$8085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325368,10 +291911,10 @@ module \mul_pipe3 parameter \Y_WIDTH 1 connect \A \p_valid_i$55 connect \B \p_ready_o - connect \Y $and$libresoc.v:156611$8153_Y + connect \Y $and$libresoc.v:157379$8085_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:156656.8-156692.4" + attribute \src "libresoc.v:157424.8-157460.4" cell \mul3 \mul3 connect \mul_op__fn_unit \mul3_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 @@ -325410,13 +291953,13 @@ module \mul_pipe3 connect \xer_so_ok \mul3_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:156693.10-156696.4" + attribute \src "libresoc.v:157461.10-157464.4" cell \n$99 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:156697.16-156737.4" + attribute \src "libresoc.v:157465.16-157505.4" cell \output$100 \output connect \cr_a \output_cr_a connect \cr_a$16 \output_cr_a$46 @@ -325459,358 +292002,358 @@ module \mul_pipe3 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:156738.10-156741.4" + attribute \src "libresoc.v:157506.10-157509.4" cell \p$98 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:155615.7-155615.20" - process $proc$libresoc.v:155615$8253 + attribute \src "libresoc.v:156383.7-156383.20" + process $proc$libresoc.v:156383$8185 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155624.13-155624.24" - process $proc$libresoc.v:155624$8254 + attribute \src "libresoc.v:156392.13-156392.24" + process $proc$libresoc.v:156392$8186 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:155633.7-155633.21" - process $proc$libresoc.v:155633$8255 + attribute \src "libresoc.v:156401.7-156401.21" + process $proc$libresoc.v:156401$8187 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:155926.14-155926.44" - process $proc$libresoc.v:155926$8256 + attribute \src "libresoc.v:156694.14-156694.44" + process $proc$libresoc.v:156694$8188 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$8257 14'00000000000000 + assign $0\mul_op__fn_unit$3[13:0]$8189 14'00000000000000 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8257 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8189 end - attribute \src "libresoc.v:155950.14-155950.63" - process $proc$libresoc.v:155950$8258 + attribute \src "libresoc.v:156718.14-156718.63" + process $proc$libresoc.v:156718$8190 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8259 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\mul_op__imm_data__data$4[63:0]$8191 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8259 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8191 end - attribute \src "libresoc.v:155959.7-155959.38" - process $proc$libresoc.v:155959$8260 + attribute \src "libresoc.v:156727.7-156727.38" + process $proc$libresoc.v:156727$8192 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8261 1'0 + assign $0\mul_op__imm_data__ok$5[0:0]$8193 1'0 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8261 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8193 end - attribute \src "libresoc.v:155968.14-155968.39" - process $proc$libresoc.v:155968$8262 + attribute \src "libresoc.v:156736.14-156736.39" + process $proc$libresoc.v:156736$8194 assign { } { } - assign $0\mul_op__insn$13[31:0]$8263 0 + assign $0\mul_op__insn$13[31:0]$8195 0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8263 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8195 end - attribute \src "libresoc.v:156127.13-156127.42" - process $proc$libresoc.v:156127$8264 + attribute \src "libresoc.v:156895.13-156895.42" + process $proc$libresoc.v:156895$8196 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8265 7'0000000 + assign $0\mul_op__insn_type$2[6:0]$8197 7'0000000 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8265 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8197 end - attribute \src "libresoc.v:156211.7-156211.35" - process $proc$libresoc.v:156211$8266 + attribute \src "libresoc.v:156979.7-156979.35" + process $proc$libresoc.v:156979$8198 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8267 1'0 + assign $0\mul_op__is_32bit$11[0:0]$8199 1'0 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8267 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8199 end - attribute \src "libresoc.v:156220.7-156220.36" - process $proc$libresoc.v:156220$8268 + attribute \src "libresoc.v:156988.7-156988.36" + process $proc$libresoc.v:156988$8200 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8269 1'0 + assign $0\mul_op__is_signed$12[0:0]$8201 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8269 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8201 end - attribute \src "libresoc.v:156231.7-156231.32" - process $proc$libresoc.v:156231$8270 + attribute \src "libresoc.v:156999.7-156999.32" + process $proc$libresoc.v:156999$8202 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8271 1'0 + assign $0\mul_op__oe__oe$8[0:0]$8203 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8271 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8203 end - attribute \src "libresoc.v:156240.7-156240.32" - process $proc$libresoc.v:156240$8272 + attribute \src "libresoc.v:157008.7-157008.32" + process $proc$libresoc.v:157008$8204 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8273 1'0 + assign $0\mul_op__oe__ok$9[0:0]$8205 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8273 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8205 end - attribute \src "libresoc.v:156249.7-156249.32" - process $proc$libresoc.v:156249$8274 + attribute \src "libresoc.v:157017.7-157017.32" + process $proc$libresoc.v:157017$8206 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8275 1'0 + assign $0\mul_op__rc__ok$7[0:0]$8207 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8275 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8207 end - attribute \src "libresoc.v:156256.7-156256.32" - process $proc$libresoc.v:156256$8276 + attribute \src "libresoc.v:157024.7-157024.32" + process $proc$libresoc.v:157024$8208 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8277 1'0 + assign $0\mul_op__rc__rc$6[0:0]$8209 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8277 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8209 end - attribute \src "libresoc.v:156265.7-156265.36" - process $proc$libresoc.v:156265$8278 + attribute \src "libresoc.v:157033.7-157033.36" + process $proc$libresoc.v:157033$8210 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8279 1'0 + assign $0\mul_op__write_cr0$10[0:0]$8211 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8279 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8211 end - attribute \src "libresoc.v:156274.13-156274.29" - process $proc$libresoc.v:156274$8280 + attribute \src "libresoc.v:157042.13-157042.29" + process $proc$libresoc.v:157042$8212 assign { } { } - assign $0\muxid$1[1:0]$8281 2'00 + assign $0\muxid$1[1:0]$8213 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8281 + update \muxid$1 $0\muxid$1[1:0]$8213 end - attribute \src "libresoc.v:156295.14-156295.43" - process $proc$libresoc.v:156295$8282 + attribute \src "libresoc.v:157063.14-157063.43" + process $proc$libresoc.v:157063$8214 assign { } { } - assign $0\o$14[63:0]$8283 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$14[63:0]$8215 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$14 $0\o$14[63:0]$8283 + update \o$14 $0\o$14[63:0]$8215 end - attribute \src "libresoc.v:156302.7-156302.18" - process $proc$libresoc.v:156302$8284 + attribute \src "libresoc.v:157070.7-157070.18" + process $proc$libresoc.v:157070$8216 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:156574.7-156574.20" - process $proc$libresoc.v:156574$8285 + attribute \src "libresoc.v:157342.7-157342.20" + process $proc$libresoc.v:157342$8217 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:156579.13-156579.26" - process $proc$libresoc.v:156579$8286 + attribute \src "libresoc.v:157347.13-157347.26" + process $proc$libresoc.v:157347$8218 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:156586.7-156586.23" - process $proc$libresoc.v:156586$8287 + attribute \src "libresoc.v:157354.7-157354.23" + process $proc$libresoc.v:157354$8219 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:156597.7-156597.25" - process $proc$libresoc.v:156597$8288 + attribute \src "libresoc.v:157365.7-157365.25" + process $proc$libresoc.v:157365$8220 assign { } { } - assign $0\xer_so$15[0:0]$8289 1'0 + assign $0\xer_so$15[0:0]$8221 1'0 sync always sync init - update \xer_so$15 $0\xer_so$15[0:0]$8289 + update \xer_so$15 $0\xer_so$15[0:0]$8221 end - attribute \src "libresoc.v:156604.7-156604.23" - process $proc$libresoc.v:156604$8290 + attribute \src "libresoc.v:157372.7-157372.23" + process $proc$libresoc.v:157372$8222 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:156612.3-156613.37" - process $proc$libresoc.v:156612$8154 + attribute \src "libresoc.v:157380.3-157381.37" + process $proc$libresoc.v:157380$8086 assign { } { } - assign $0\xer_so$15[0:0]$8155 \xer_so$15$next + assign $0\xer_so$15[0:0]$8087 \xer_so$15$next sync posedge \coresync_clk - update \xer_so$15 $0\xer_so$15[0:0]$8155 + update \xer_so$15 $0\xer_so$15[0:0]$8087 end - attribute \src "libresoc.v:156614.3-156615.35" - process $proc$libresoc.v:156614$8156 + attribute \src "libresoc.v:157382.3-157383.35" + process $proc$libresoc.v:157382$8088 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:156616.3-156617.29" - process $proc$libresoc.v:156616$8157 + attribute \src "libresoc.v:157384.3-157385.29" + process $proc$libresoc.v:157384$8089 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:156618.3-156619.35" - process $proc$libresoc.v:156618$8158 + attribute \src "libresoc.v:157386.3-157387.35" + process $proc$libresoc.v:157386$8090 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:156620.3-156621.25" - process $proc$libresoc.v:156620$8159 + attribute \src "libresoc.v:157388.3-157389.25" + process $proc$libresoc.v:157388$8091 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:156622.3-156623.31" - process $proc$libresoc.v:156622$8160 + attribute \src "libresoc.v:157390.3-157391.31" + process $proc$libresoc.v:157390$8092 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:156624.3-156625.27" - process $proc$libresoc.v:156624$8161 + attribute \src "libresoc.v:157392.3-157393.27" + process $proc$libresoc.v:157392$8093 assign { } { } - assign $0\o$14[63:0]$8162 \o$14$next + assign $0\o$14[63:0]$8094 \o$14$next sync posedge \coresync_clk - update \o$14 $0\o$14[63:0]$8162 + update \o$14 $0\o$14[63:0]$8094 end - attribute \src "libresoc.v:156626.3-156627.25" - process $proc$libresoc.v:156626$8163 + attribute \src "libresoc.v:157394.3-157395.25" + process $proc$libresoc.v:157394$8095 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:156628.3-156629.57" - process $proc$libresoc.v:156628$8164 + attribute \src "libresoc.v:157396.3-157397.57" + process $proc$libresoc.v:157396$8096 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8165 \mul_op__insn_type$2$next + assign $0\mul_op__insn_type$2[6:0]$8097 \mul_op__insn_type$2$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8165 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8097 end - attribute \src "libresoc.v:156630.3-156631.53" - process $proc$libresoc.v:156630$8166 + attribute \src "libresoc.v:157398.3-157399.53" + process $proc$libresoc.v:157398$8098 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$8167 \mul_op__fn_unit$3$next + assign $0\mul_op__fn_unit$3[13:0]$8099 \mul_op__fn_unit$3$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8167 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8099 end - attribute \src "libresoc.v:156632.3-156633.67" - process $proc$libresoc.v:156632$8168 + attribute \src "libresoc.v:157400.3-157401.67" + process $proc$libresoc.v:157400$8100 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8169 \mul_op__imm_data__data$4$next + assign $0\mul_op__imm_data__data$4[63:0]$8101 \mul_op__imm_data__data$4$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8169 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8101 end - attribute \src "libresoc.v:156634.3-156635.63" - process $proc$libresoc.v:156634$8170 + attribute \src "libresoc.v:157402.3-157403.63" + process $proc$libresoc.v:157402$8102 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8171 \mul_op__imm_data__ok$5$next + assign $0\mul_op__imm_data__ok$5[0:0]$8103 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8171 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8103 end - attribute \src "libresoc.v:156636.3-156637.51" - process $proc$libresoc.v:156636$8172 + attribute \src "libresoc.v:157404.3-157405.51" + process $proc$libresoc.v:157404$8104 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8173 \mul_op__rc__rc$6$next + assign $0\mul_op__rc__rc$6[0:0]$8105 \mul_op__rc__rc$6$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8173 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8105 end - attribute \src "libresoc.v:156638.3-156639.51" - process $proc$libresoc.v:156638$8174 + attribute \src "libresoc.v:157406.3-157407.51" + process $proc$libresoc.v:157406$8106 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8175 \mul_op__rc__ok$7$next + assign $0\mul_op__rc__ok$7[0:0]$8107 \mul_op__rc__ok$7$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8175 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8107 end - attribute \src "libresoc.v:156640.3-156641.51" - process $proc$libresoc.v:156640$8176 + attribute \src "libresoc.v:157408.3-157409.51" + process $proc$libresoc.v:157408$8108 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8177 \mul_op__oe__oe$8$next + assign $0\mul_op__oe__oe$8[0:0]$8109 \mul_op__oe__oe$8$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8177 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8109 end - attribute \src "libresoc.v:156642.3-156643.51" - process $proc$libresoc.v:156642$8178 + attribute \src "libresoc.v:157410.3-157411.51" + process $proc$libresoc.v:157410$8110 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8179 \mul_op__oe__ok$9$next + assign $0\mul_op__oe__ok$9[0:0]$8111 \mul_op__oe__ok$9$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8179 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8111 end - attribute \src "libresoc.v:156644.3-156645.59" - process $proc$libresoc.v:156644$8180 + attribute \src "libresoc.v:157412.3-157413.59" + process $proc$libresoc.v:157412$8112 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8181 \mul_op__write_cr0$10$next + assign $0\mul_op__write_cr0$10[0:0]$8113 \mul_op__write_cr0$10$next sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8181 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8113 end - attribute \src "libresoc.v:156646.3-156647.57" - process $proc$libresoc.v:156646$8182 + attribute \src "libresoc.v:157414.3-157415.57" + process $proc$libresoc.v:157414$8114 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8183 \mul_op__is_32bit$11$next + assign $0\mul_op__is_32bit$11[0:0]$8115 \mul_op__is_32bit$11$next sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8183 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8115 end - attribute \src "libresoc.v:156648.3-156649.59" - process $proc$libresoc.v:156648$8184 + attribute \src "libresoc.v:157416.3-157417.59" + process $proc$libresoc.v:157416$8116 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8185 \mul_op__is_signed$12$next + assign $0\mul_op__is_signed$12[0:0]$8117 \mul_op__is_signed$12$next sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8185 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8117 end - attribute \src "libresoc.v:156650.3-156651.49" - process $proc$libresoc.v:156650$8186 + attribute \src "libresoc.v:157418.3-157419.49" + process $proc$libresoc.v:157418$8118 assign { } { } - assign $0\mul_op__insn$13[31:0]$8187 \mul_op__insn$13$next + assign $0\mul_op__insn$13[31:0]$8119 \mul_op__insn$13$next sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8187 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8119 end - attribute \src "libresoc.v:156652.3-156653.33" - process $proc$libresoc.v:156652$8188 + attribute \src "libresoc.v:157420.3-157421.33" + process $proc$libresoc.v:157420$8120 assign { } { } - assign $0\muxid$1[1:0]$8189 \muxid$1$next + assign $0\muxid$1[1:0]$8121 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8189 + update \muxid$1 $0\muxid$1[1:0]$8121 end - attribute \src "libresoc.v:156654.3-156655.29" - process $proc$libresoc.v:156654$8190 + attribute \src "libresoc.v:157422.3-157423.29" + process $proc$libresoc.v:157422$8122 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:156742.3-156759.6" - process $proc$libresoc.v:156742$8191 + attribute \src "libresoc.v:157510.3-157527.6" + process $proc$libresoc.v:157510$8123 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8192 $2\r_busy$next[0:0]$8194 - attribute \src "libresoc.v:156743.5-156743.29" + assign $0\r_busy$next[0:0]$8124 $2\r_busy$next[0:0]$8126 + attribute \src "libresoc.v:157511.5-157511.29" switch \initial - attribute \src "libresoc.v:156743.9-156743.17" + attribute \src "libresoc.v:157511.9-157511.17" case 1'1 case end @@ -325819,34 +292362,34 @@ module \mul_pipe3 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8193 1'1 + assign $1\r_busy$next[0:0]$8125 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8193 1'0 + assign $1\r_busy$next[0:0]$8125 1'0 case - assign $1\r_busy$next[0:0]$8193 \r_busy + assign $1\r_busy$next[0:0]$8125 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8194 1'0 + assign $2\r_busy$next[0:0]$8126 1'0 case - assign $2\r_busy$next[0:0]$8194 $1\r_busy$next[0:0]$8193 + assign $2\r_busy$next[0:0]$8126 $1\r_busy$next[0:0]$8125 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8192 + update \r_busy$next $0\r_busy$next[0:0]$8124 end - attribute \src "libresoc.v:156760.3-156772.6" - process $proc$libresoc.v:156760$8195 + attribute \src "libresoc.v:157528.3-157540.6" + process $proc$libresoc.v:157528$8127 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8196 $1\muxid$1$next[1:0]$8197 - attribute \src "libresoc.v:156761.5-156761.29" + assign $0\muxid$1$next[1:0]$8128 $1\muxid$1$next[1:0]$8129 + attribute \src "libresoc.v:157529.5-157529.29" switch \initial - attribute \src "libresoc.v:156761.9-156761.17" + attribute \src "libresoc.v:157529.9-157529.17" case 1'1 case end @@ -325855,19 +292398,19 @@ module \mul_pipe3 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8197 \muxid$58 + assign $1\muxid$1$next[1:0]$8129 \muxid$58 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8197 \muxid$58 + assign $1\muxid$1$next[1:0]$8129 \muxid$58 case - assign $1\muxid$1$next[1:0]$8197 \muxid$1 + assign $1\muxid$1$next[1:0]$8129 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8196 + update \muxid$1$next $0\muxid$1$next[1:0]$8128 end - attribute \src "libresoc.v:156773.3-156808.6" - process $proc$libresoc.v:156773$8198 + attribute \src "libresoc.v:157541.3-157576.6" + process $proc$libresoc.v:157541$8130 assign { } { } assign { } { } assign { } { } @@ -325892,27 +292435,27 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[13:0]$8199 $1\mul_op__fn_unit$3$next[13:0]$8211 + assign $0\mul_op__fn_unit$3$next[13:0]$8131 $1\mul_op__fn_unit$3$next[13:0]$8143 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$8202 $1\mul_op__insn$13$next[31:0]$8214 - assign $0\mul_op__insn_type$2$next[6:0]$8203 $1\mul_op__insn_type$2$next[6:0]$8215 - assign $0\mul_op__is_32bit$11$next[0:0]$8204 $1\mul_op__is_32bit$11$next[0:0]$8216 - assign $0\mul_op__is_signed$12$next[0:0]$8205 $1\mul_op__is_signed$12$next[0:0]$8217 + assign $0\mul_op__insn$13$next[31:0]$8134 $1\mul_op__insn$13$next[31:0]$8146 + assign $0\mul_op__insn_type$2$next[6:0]$8135 $1\mul_op__insn_type$2$next[6:0]$8147 + assign $0\mul_op__is_32bit$11$next[0:0]$8136 $1\mul_op__is_32bit$11$next[0:0]$8148 + assign $0\mul_op__is_signed$12$next[0:0]$8137 $1\mul_op__is_signed$12$next[0:0]$8149 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$8210 $1\mul_op__write_cr0$10$next[0:0]$8222 - assign $0\mul_op__imm_data__data$4$next[63:0]$8200 $2\mul_op__imm_data__data$4$next[63:0]$8223 - assign $0\mul_op__imm_data__ok$5$next[0:0]$8201 $2\mul_op__imm_data__ok$5$next[0:0]$8224 - assign $0\mul_op__oe__oe$8$next[0:0]$8206 $2\mul_op__oe__oe$8$next[0:0]$8225 - assign $0\mul_op__oe__ok$9$next[0:0]$8207 $2\mul_op__oe__ok$9$next[0:0]$8226 - assign $0\mul_op__rc__ok$7$next[0:0]$8208 $2\mul_op__rc__ok$7$next[0:0]$8227 - assign $0\mul_op__rc__rc$6$next[0:0]$8209 $2\mul_op__rc__rc$6$next[0:0]$8228 - attribute \src "libresoc.v:156774.5-156774.29" + assign $0\mul_op__write_cr0$10$next[0:0]$8142 $1\mul_op__write_cr0$10$next[0:0]$8154 + assign $0\mul_op__imm_data__data$4$next[63:0]$8132 $2\mul_op__imm_data__data$4$next[63:0]$8155 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8133 $2\mul_op__imm_data__ok$5$next[0:0]$8156 + assign $0\mul_op__oe__oe$8$next[0:0]$8138 $2\mul_op__oe__oe$8$next[0:0]$8157 + assign $0\mul_op__oe__ok$9$next[0:0]$8139 $2\mul_op__oe__ok$9$next[0:0]$8158 + assign $0\mul_op__rc__ok$7$next[0:0]$8140 $2\mul_op__rc__ok$7$next[0:0]$8159 + assign $0\mul_op__rc__rc$6$next[0:0]$8141 $2\mul_op__rc__rc$6$next[0:0]$8160 + attribute \src "libresoc.v:157542.5-157542.29" switch \initial - attribute \src "libresoc.v:156774.9-156774.17" + attribute \src "libresoc.v:157542.9-157542.17" case 1'1 case end @@ -325932,7 +292475,7 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8214 $1\mul_op__is_signed$12$next[0:0]$8217 $1\mul_op__is_32bit$11$next[0:0]$8216 $1\mul_op__write_cr0$10$next[0:0]$8222 $1\mul_op__oe__ok$9$next[0:0]$8219 $1\mul_op__oe__oe$8$next[0:0]$8218 $1\mul_op__rc__ok$7$next[0:0]$8220 $1\mul_op__rc__rc$6$next[0:0]$8221 $1\mul_op__imm_data__ok$5$next[0:0]$8213 $1\mul_op__imm_data__data$4$next[63:0]$8212 $1\mul_op__fn_unit$3$next[13:0]$8211 $1\mul_op__insn_type$2$next[6:0]$8215 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\mul_op__insn$13$next[31:0]$8146 $1\mul_op__is_signed$12$next[0:0]$8149 $1\mul_op__is_32bit$11$next[0:0]$8148 $1\mul_op__write_cr0$10$next[0:0]$8154 $1\mul_op__oe__ok$9$next[0:0]$8151 $1\mul_op__oe__oe$8$next[0:0]$8150 $1\mul_op__rc__ok$7$next[0:0]$8152 $1\mul_op__rc__rc$6$next[0:0]$8153 $1\mul_op__imm_data__ok$5$next[0:0]$8145 $1\mul_op__imm_data__data$4$next[63:0]$8144 $1\mul_op__fn_unit$3$next[13:0]$8143 $1\mul_op__insn_type$2$next[6:0]$8147 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -325947,20 +292490,20 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8214 $1\mul_op__is_signed$12$next[0:0]$8217 $1\mul_op__is_32bit$11$next[0:0]$8216 $1\mul_op__write_cr0$10$next[0:0]$8222 $1\mul_op__oe__ok$9$next[0:0]$8219 $1\mul_op__oe__oe$8$next[0:0]$8218 $1\mul_op__rc__ok$7$next[0:0]$8220 $1\mul_op__rc__rc$6$next[0:0]$8221 $1\mul_op__imm_data__ok$5$next[0:0]$8213 $1\mul_op__imm_data__data$4$next[63:0]$8212 $1\mul_op__fn_unit$3$next[13:0]$8211 $1\mul_op__insn_type$2$next[6:0]$8215 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\mul_op__insn$13$next[31:0]$8146 $1\mul_op__is_signed$12$next[0:0]$8149 $1\mul_op__is_32bit$11$next[0:0]$8148 $1\mul_op__write_cr0$10$next[0:0]$8154 $1\mul_op__oe__ok$9$next[0:0]$8151 $1\mul_op__oe__oe$8$next[0:0]$8150 $1\mul_op__rc__ok$7$next[0:0]$8152 $1\mul_op__rc__rc$6$next[0:0]$8153 $1\mul_op__imm_data__ok$5$next[0:0]$8145 $1\mul_op__imm_data__data$4$next[63:0]$8144 $1\mul_op__fn_unit$3$next[13:0]$8143 $1\mul_op__insn_type$2$next[6:0]$8147 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } case - assign $1\mul_op__fn_unit$3$next[13:0]$8211 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$8212 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$8213 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$8214 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$8215 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$8216 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$8217 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$8218 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$8219 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$8220 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$8221 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$8222 \mul_op__write_cr0$10 + assign $1\mul_op__fn_unit$3$next[13:0]$8143 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8144 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8145 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8146 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8147 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8148 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8149 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8150 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8151 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8152 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8153 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8154 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -325972,46 +292515,46 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$8223 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8224 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$8228 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$8227 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$8225 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$8226 1'0 + assign $2\mul_op__imm_data__data$4$next[63:0]$8155 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8156 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8160 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8159 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8157 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8158 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$8223 $1\mul_op__imm_data__data$4$next[63:0]$8212 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8224 $1\mul_op__imm_data__ok$5$next[0:0]$8213 - assign $2\mul_op__oe__oe$8$next[0:0]$8225 $1\mul_op__oe__oe$8$next[0:0]$8218 - assign $2\mul_op__oe__ok$9$next[0:0]$8226 $1\mul_op__oe__ok$9$next[0:0]$8219 - assign $2\mul_op__rc__ok$7$next[0:0]$8227 $1\mul_op__rc__ok$7$next[0:0]$8220 - assign $2\mul_op__rc__rc$6$next[0:0]$8228 $1\mul_op__rc__rc$6$next[0:0]$8221 + assign $2\mul_op__imm_data__data$4$next[63:0]$8155 $1\mul_op__imm_data__data$4$next[63:0]$8144 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8156 $1\mul_op__imm_data__ok$5$next[0:0]$8145 + assign $2\mul_op__oe__oe$8$next[0:0]$8157 $1\mul_op__oe__oe$8$next[0:0]$8150 + assign $2\mul_op__oe__ok$9$next[0:0]$8158 $1\mul_op__oe__ok$9$next[0:0]$8151 + assign $2\mul_op__rc__ok$7$next[0:0]$8159 $1\mul_op__rc__ok$7$next[0:0]$8152 + assign $2\mul_op__rc__rc$6$next[0:0]$8160 $1\mul_op__rc__rc$6$next[0:0]$8153 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8199 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8200 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8201 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8202 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8203 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8204 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8205 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8206 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8207 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8208 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8209 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8210 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8131 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8132 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8133 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8134 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8135 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8136 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8137 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8138 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8139 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8140 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8141 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8142 end - attribute \src "libresoc.v:156809.3-156827.6" - process $proc$libresoc.v:156809$8229 + attribute \src "libresoc.v:157577.3-157595.6" + process $proc$libresoc.v:157577$8161 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$14$next[63:0]$8231 $1\o$14$next[63:0]$8233 - assign $0\o_ok$next[0:0]$8230 $2\o_ok$next[0:0]$8234 - attribute \src "libresoc.v:156810.5-156810.29" + assign $0\o$14$next[63:0]$8163 $1\o$14$next[63:0]$8165 + assign $0\o_ok$next[0:0]$8162 $2\o_ok$next[0:0]$8166 + attribute \src "libresoc.v:157578.5-157578.29" switch \initial - attribute \src "libresoc.v:156810.9-156810.17" + attribute \src "libresoc.v:157578.9-157578.17" case 1'1 case end @@ -326021,41 +292564,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8232 $1\o$14$next[63:0]$8233 } { \o_ok$72 \o$71 } + assign { $1\o_ok$next[0:0]$8164 $1\o$14$next[63:0]$8165 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8232 $1\o$14$next[63:0]$8233 } { \o_ok$72 \o$71 } + assign { $1\o_ok$next[0:0]$8164 $1\o$14$next[63:0]$8165 } { \o_ok$72 \o$71 } case - assign $1\o_ok$next[0:0]$8232 \o_ok - assign $1\o$14$next[63:0]$8233 \o$14 + assign $1\o_ok$next[0:0]$8164 \o_ok + assign $1\o$14$next[63:0]$8165 \o$14 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8234 1'0 + assign $2\o_ok$next[0:0]$8166 1'0 case - assign $2\o_ok$next[0:0]$8234 $1\o_ok$next[0:0]$8232 + assign $2\o_ok$next[0:0]$8166 $1\o_ok$next[0:0]$8164 end sync always - update \o_ok$next $0\o_ok$next[0:0]$8230 - update \o$14$next $0\o$14$next[63:0]$8231 + update \o_ok$next $0\o_ok$next[0:0]$8162 + update \o$14$next $0\o$14$next[63:0]$8163 end - attribute \src "libresoc.v:156828.3-156846.6" - process $proc$libresoc.v:156828$8235 + attribute \src "libresoc.v:157596.3-157614.6" + process $proc$libresoc.v:157596$8167 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$8236 $1\cr_a$next[3:0]$8238 + assign $0\cr_a$next[3:0]$8168 $1\cr_a$next[3:0]$8170 assign { } { } - assign $0\cr_a_ok$next[0:0]$8237 $2\cr_a_ok$next[0:0]$8240 - attribute \src "libresoc.v:156829.5-156829.29" + assign $0\cr_a_ok$next[0:0]$8169 $2\cr_a_ok$next[0:0]$8172 + attribute \src "libresoc.v:157597.5-157597.29" switch \initial - attribute \src "libresoc.v:156829.9-156829.17" + attribute \src "libresoc.v:157597.9-157597.17" case 1'1 case end @@ -326065,41 +292608,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8239 $1\cr_a$next[3:0]$8238 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$next[0:0]$8171 $1\cr_a$next[3:0]$8170 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8239 $1\cr_a$next[3:0]$8238 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$next[0:0]$8171 $1\cr_a$next[3:0]$8170 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\cr_a$next[3:0]$8238 \cr_a - assign $1\cr_a_ok$next[0:0]$8239 \cr_a_ok + assign $1\cr_a$next[3:0]$8170 \cr_a + assign $1\cr_a_ok$next[0:0]$8171 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8240 1'0 + assign $2\cr_a_ok$next[0:0]$8172 1'0 case - assign $2\cr_a_ok$next[0:0]$8240 $1\cr_a_ok$next[0:0]$8239 + assign $2\cr_a_ok$next[0:0]$8172 $1\cr_a_ok$next[0:0]$8171 end sync always - update \cr_a$next $0\cr_a$next[3:0]$8236 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8237 + update \cr_a$next $0\cr_a$next[3:0]$8168 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8169 end - attribute \src "libresoc.v:156847.3-156865.6" - process $proc$libresoc.v:156847$8241 + attribute \src "libresoc.v:157615.3-157633.6" + process $proc$libresoc.v:157615$8173 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$8242 $1\xer_ov$next[1:0]$8244 + assign $0\xer_ov$next[1:0]$8174 $1\xer_ov$next[1:0]$8176 assign { } { } - assign $0\xer_ov_ok$next[0:0]$8243 $2\xer_ov_ok$next[0:0]$8246 - attribute \src "libresoc.v:156848.5-156848.29" + assign $0\xer_ov_ok$next[0:0]$8175 $2\xer_ov_ok$next[0:0]$8178 + attribute \src "libresoc.v:157616.5-157616.29" switch \initial - attribute \src "libresoc.v:156848.9-156848.17" + attribute \src "libresoc.v:157616.9-157616.17" case 1'1 case end @@ -326109,41 +292652,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8245 $1\xer_ov$next[1:0]$8244 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\xer_ov_ok$next[0:0]$8177 $1\xer_ov$next[1:0]$8176 } { \xer_ov_ok$76 \xer_ov$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8245 $1\xer_ov$next[1:0]$8244 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\xer_ov_ok$next[0:0]$8177 $1\xer_ov$next[1:0]$8176 } { \xer_ov_ok$76 \xer_ov$75 } case - assign $1\xer_ov$next[1:0]$8244 \xer_ov - assign $1\xer_ov_ok$next[0:0]$8245 \xer_ov_ok + assign $1\xer_ov$next[1:0]$8176 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8177 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8246 1'0 + assign $2\xer_ov_ok$next[0:0]$8178 1'0 case - assign $2\xer_ov_ok$next[0:0]$8246 $1\xer_ov_ok$next[0:0]$8245 + assign $2\xer_ov_ok$next[0:0]$8178 $1\xer_ov_ok$next[0:0]$8177 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$8242 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8243 + update \xer_ov$next $0\xer_ov$next[1:0]$8174 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8175 end - attribute \src "libresoc.v:156866.3-156884.6" - process $proc$libresoc.v:156866$8247 + attribute \src "libresoc.v:157634.3-157652.6" + process $proc$libresoc.v:157634$8179 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$15$next[0:0]$8249 $1\xer_so$15$next[0:0]$8251 - assign $0\xer_so_ok$next[0:0]$8248 $2\xer_so_ok$next[0:0]$8252 - attribute \src "libresoc.v:156867.5-156867.29" + assign $0\xer_so$15$next[0:0]$8181 $1\xer_so$15$next[0:0]$8183 + assign $0\xer_so_ok$next[0:0]$8180 $2\xer_so_ok$next[0:0]$8184 + attribute \src "libresoc.v:157635.5-157635.29" switch \initial - attribute \src "libresoc.v:156867.9-156867.17" + attribute \src "libresoc.v:157635.9-157635.17" case 1'1 case end @@ -326153,30 +292696,30 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8250 $1\xer_so$15$next[0:0]$8251 } { \xer_so_ok$78 \xer_so$77 } + assign { $1\xer_so_ok$next[0:0]$8182 $1\xer_so$15$next[0:0]$8183 } { \xer_so_ok$78 \xer_so$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8250 $1\xer_so$15$next[0:0]$8251 } { \xer_so_ok$78 \xer_so$77 } + assign { $1\xer_so_ok$next[0:0]$8182 $1\xer_so$15$next[0:0]$8183 } { \xer_so_ok$78 \xer_so$77 } case - assign $1\xer_so_ok$next[0:0]$8250 \xer_so_ok - assign $1\xer_so$15$next[0:0]$8251 \xer_so$15 + assign $1\xer_so_ok$next[0:0]$8182 \xer_so_ok + assign $1\xer_so$15$next[0:0]$8183 \xer_so$15 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8252 1'0 + assign $2\xer_so_ok$next[0:0]$8184 1'0 case - assign $2\xer_so_ok$next[0:0]$8252 $1\xer_so_ok$next[0:0]$8250 + assign $2\xer_so_ok$next[0:0]$8184 $1\xer_so_ok$next[0:0]$8182 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8248 - update \xer_so$15$next $0\xer_so$15$next[0:0]$8249 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8180 + update \xer_so$15$next $0\xer_so$15$next[0:0]$8181 end - connect \$56 $and$libresoc.v:156611$8153_Y + connect \$56 $and$libresoc.v:157379$8085_Y connect \cr_a$51 4'0000 connect \cr_a_ok$52 1'0 connect \p_ready_o \n_i_rdy_data @@ -326203,13 +292746,13 @@ module \mul_pipe3 connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul3_muxid \muxid end -attribute \src "libresoc.v:156914.1-156925.10" +attribute \src "libresoc.v:157682.1-157693.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" attribute \generator "nMigen" module \n - attribute \src "libresoc.v:156923.17-156923.111" - wire $and$libresoc.v:156923$8291_Y + attribute \src "libresoc.v:157691.17-157691.111" + wire $and$libresoc.v:157691$8223_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326219,7 +292762,7 @@ module \n attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156923$8291 + cell $and $and$libresoc.v:157691$8223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326227,18 +292770,18 @@ module \n parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156923$8291_Y + connect \Y $and$libresoc.v:157691$8223_Y end - connect \$1 $and$libresoc.v:156923$8291_Y + connect \$1 $and$libresoc.v:157691$8223_Y connect \trigger \$1 end -attribute \src "libresoc.v:156929.1-156940.10" +attribute \src "libresoc.v:157697.1-157708.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" attribute \generator "nMigen" module \n$109 - attribute \src "libresoc.v:156938.17-156938.111" - wire $and$libresoc.v:156938$8292_Y + attribute \src "libresoc.v:157706.17-157706.111" + wire $and$libresoc.v:157706$8224_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326248,7 +292791,7 @@ module \n$109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156938$8292 + cell $and $and$libresoc.v:157706$8224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326256,18 +292799,18 @@ module \n$109 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156938$8292_Y + connect \Y $and$libresoc.v:157706$8224_Y end - connect \$1 $and$libresoc.v:156938$8292_Y + connect \$1 $and$libresoc.v:157706$8224_Y connect \trigger \$1 end -attribute \src "libresoc.v:156944.1-156955.10" +attribute \src "libresoc.v:157712.1-157723.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" attribute \generator "nMigen" module \n$112 - attribute \src "libresoc.v:156953.17-156953.111" - wire $and$libresoc.v:156953$8293_Y + attribute \src "libresoc.v:157721.17-157721.111" + wire $and$libresoc.v:157721$8225_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326277,7 +292820,7 @@ module \n$112 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156953$8293 + cell $and $and$libresoc.v:157721$8225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326285,18 +292828,18 @@ module \n$112 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156953$8293_Y + connect \Y $and$libresoc.v:157721$8225_Y end - connect \$1 $and$libresoc.v:156953$8293_Y + connect \$1 $and$libresoc.v:157721$8225_Y connect \trigger \$1 end -attribute \src "libresoc.v:156959.1-156970.10" +attribute \src "libresoc.v:157727.1-157738.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" attribute \generator "nMigen" module \n$117 - attribute \src "libresoc.v:156968.17-156968.111" - wire $and$libresoc.v:156968$8294_Y + attribute \src "libresoc.v:157736.17-157736.111" + wire $and$libresoc.v:157736$8226_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326306,7 +292849,7 @@ module \n$117 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156968$8294 + cell $and $and$libresoc.v:157736$8226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326314,18 +292857,18 @@ module \n$117 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156968$8294_Y + connect \Y $and$libresoc.v:157736$8226_Y end - connect \$1 $and$libresoc.v:156968$8294_Y + connect \$1 $and$libresoc.v:157736$8226_Y connect \trigger \$1 end -attribute \src "libresoc.v:156974.1-156985.10" +attribute \src "libresoc.v:157742.1-157753.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" attribute \generator "nMigen" module \n$18 - attribute \src "libresoc.v:156983.17-156983.111" - wire $and$libresoc.v:156983$8295_Y + attribute \src "libresoc.v:157751.17-157751.111" + wire $and$libresoc.v:157751$8227_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326335,7 +292878,7 @@ module \n$18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156983$8295 + cell $and $and$libresoc.v:157751$8227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326343,18 +292886,18 @@ module \n$18 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156983$8295_Y + connect \Y $and$libresoc.v:157751$8227_Y end - connect \$1 $and$libresoc.v:156983$8295_Y + connect \$1 $and$libresoc.v:157751$8227_Y connect \trigger \$1 end -attribute \src "libresoc.v:156989.1-157000.10" +attribute \src "libresoc.v:157757.1-157768.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" attribute \generator "nMigen" module \n$2 - attribute \src "libresoc.v:156998.17-156998.111" - wire $and$libresoc.v:156998$8296_Y + attribute \src "libresoc.v:157766.17-157766.111" + wire $and$libresoc.v:157766$8228_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326364,7 +292907,7 @@ module \n$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156998$8296 + cell $and $and$libresoc.v:157766$8228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326372,18 +292915,18 @@ module \n$2 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156998$8296_Y + connect \Y $and$libresoc.v:157766$8228_Y end - connect \$1 $and$libresoc.v:156998$8296_Y + connect \$1 $and$libresoc.v:157766$8228_Y connect \trigger \$1 end -attribute \src "libresoc.v:157004.1-157015.10" +attribute \src "libresoc.v:157772.1-157783.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" attribute \generator "nMigen" module \n$21 - attribute \src "libresoc.v:157013.17-157013.111" - wire $and$libresoc.v:157013$8297_Y + attribute \src "libresoc.v:157781.17-157781.111" + wire $and$libresoc.v:157781$8229_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326393,7 +292936,7 @@ module \n$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157013$8297 + cell $and $and$libresoc.v:157781$8229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326401,18 +292944,18 @@ module \n$21 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157013$8297_Y + connect \Y $and$libresoc.v:157781$8229_Y end - connect \$1 $and$libresoc.v:157013$8297_Y + connect \$1 $and$libresoc.v:157781$8229_Y connect \trigger \$1 end -attribute \src "libresoc.v:157019.1-157030.10" +attribute \src "libresoc.v:157787.1-157798.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n" attribute \generator "nMigen" module \n$31 - attribute \src "libresoc.v:157028.17-157028.111" - wire $and$libresoc.v:157028$8298_Y + attribute \src "libresoc.v:157796.17-157796.111" + wire $and$libresoc.v:157796$8230_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326422,7 +292965,7 @@ module \n$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157028$8298 + cell $and $and$libresoc.v:157796$8230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326430,18 +292973,18 @@ module \n$31 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157028$8298_Y + connect \Y $and$libresoc.v:157796$8230_Y end - connect \$1 $and$libresoc.v:157028$8298_Y + connect \$1 $and$libresoc.v:157796$8230_Y connect \trigger \$1 end -attribute \src "libresoc.v:157034.1-157045.10" +attribute \src "libresoc.v:157802.1-157813.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" attribute \generator "nMigen" module \n$34 - attribute \src "libresoc.v:157043.17-157043.111" - wire $and$libresoc.v:157043$8299_Y + attribute \src "libresoc.v:157811.17-157811.111" + wire $and$libresoc.v:157811$8231_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326451,7 +292994,7 @@ module \n$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157043$8299 + cell $and $and$libresoc.v:157811$8231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326459,18 +293002,18 @@ module \n$34 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157043$8299_Y + connect \Y $and$libresoc.v:157811$8231_Y end - connect \$1 $and$libresoc.v:157043$8299_Y + connect \$1 $and$libresoc.v:157811$8231_Y connect \trigger \$1 end -attribute \src "libresoc.v:157049.1-157060.10" +attribute \src "libresoc.v:157817.1-157828.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" attribute \generator "nMigen" module \n$37 - attribute \src "libresoc.v:157058.17-157058.111" - wire $and$libresoc.v:157058$8300_Y + attribute \src "libresoc.v:157826.17-157826.111" + wire $and$libresoc.v:157826$8232_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326480,7 +293023,7 @@ module \n$37 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157058$8300 + cell $and $and$libresoc.v:157826$8232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326488,18 +293031,18 @@ module \n$37 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157058$8300_Y + connect \Y $and$libresoc.v:157826$8232_Y end - connect \$1 $and$libresoc.v:157058$8300_Y + connect \$1 $and$libresoc.v:157826$8232_Y connect \trigger \$1 end -attribute \src "libresoc.v:157064.1-157075.10" +attribute \src "libresoc.v:157832.1-157843.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" attribute \generator "nMigen" module \n$4 - attribute \src "libresoc.v:157073.17-157073.111" - wire $and$libresoc.v:157073$8301_Y + attribute \src "libresoc.v:157841.17-157841.111" + wire $and$libresoc.v:157841$8233_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326509,7 +293052,7 @@ module \n$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157073$8301 + cell $and $and$libresoc.v:157841$8233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326517,18 +293060,18 @@ module \n$4 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157073$8301_Y + connect \Y $and$libresoc.v:157841$8233_Y end - connect \$1 $and$libresoc.v:157073$8301_Y + connect \$1 $and$libresoc.v:157841$8233_Y connect \trigger \$1 end -attribute \src "libresoc.v:157079.1-157090.10" +attribute \src "libresoc.v:157847.1-157858.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n" attribute \generator "nMigen" module \n$47 - attribute \src "libresoc.v:157088.17-157088.111" - wire $and$libresoc.v:157088$8302_Y + attribute \src "libresoc.v:157856.17-157856.111" + wire $and$libresoc.v:157856$8234_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326538,7 +293081,7 @@ module \n$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157088$8302 + cell $and $and$libresoc.v:157856$8234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326546,18 +293089,18 @@ module \n$47 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157088$8302_Y + connect \Y $and$libresoc.v:157856$8234_Y end - connect \$1 $and$libresoc.v:157088$8302_Y + connect \$1 $and$libresoc.v:157856$8234_Y connect \trigger \$1 end -attribute \src "libresoc.v:157094.1-157105.10" +attribute \src "libresoc.v:157862.1-157873.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" attribute \generator "nMigen" module \n$49 - attribute \src "libresoc.v:157103.17-157103.111" - wire $and$libresoc.v:157103$8303_Y + attribute \src "libresoc.v:157871.17-157871.111" + wire $and$libresoc.v:157871$8235_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326567,7 +293110,7 @@ module \n$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157103$8303 + cell $and $and$libresoc.v:157871$8235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326575,18 +293118,18 @@ module \n$49 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157103$8303_Y + connect \Y $and$libresoc.v:157871$8235_Y end - connect \$1 $and$libresoc.v:157103$8303_Y + connect \$1 $and$libresoc.v:157871$8235_Y connect \trigger \$1 end -attribute \src "libresoc.v:157109.1-157120.10" +attribute \src "libresoc.v:157877.1-157888.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" attribute \generator "nMigen" module \n$53 - attribute \src "libresoc.v:157118.17-157118.111" - wire $and$libresoc.v:157118$8304_Y + attribute \src "libresoc.v:157886.17-157886.111" + wire $and$libresoc.v:157886$8236_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326596,7 +293139,7 @@ module \n$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157118$8304 + cell $and $and$libresoc.v:157886$8236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326604,18 +293147,18 @@ module \n$53 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157118$8304_Y + connect \Y $and$libresoc.v:157886$8236_Y end - connect \$1 $and$libresoc.v:157118$8304_Y + connect \$1 $and$libresoc.v:157886$8236_Y connect \trigger \$1 end -attribute \src "libresoc.v:157124.1-157135.10" +attribute \src "libresoc.v:157892.1-157903.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.n" attribute \generator "nMigen" module \n$6 - attribute \src "libresoc.v:157133.17-157133.111" - wire $and$libresoc.v:157133$8305_Y + attribute \src "libresoc.v:157901.17-157901.111" + wire $and$libresoc.v:157901$8237_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326625,7 +293168,7 @@ module \n$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157133$8305 + cell $and $and$libresoc.v:157901$8237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326633,18 +293176,18 @@ module \n$6 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157133$8305_Y + connect \Y $and$libresoc.v:157901$8237_Y end - connect \$1 $and$libresoc.v:157133$8305_Y + connect \$1 $and$libresoc.v:157901$8237_Y connect \trigger \$1 end -attribute \src "libresoc.v:157139.1-157150.10" +attribute \src "libresoc.v:157907.1-157918.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.n" attribute \generator "nMigen" module \n$63 - attribute \src "libresoc.v:157148.17-157148.111" - wire $and$libresoc.v:157148$8306_Y + attribute \src "libresoc.v:157916.17-157916.111" + wire $and$libresoc.v:157916$8238_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326654,7 +293197,7 @@ module \n$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157148$8306 + cell $and $and$libresoc.v:157916$8238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326662,18 +293205,18 @@ module \n$63 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157148$8306_Y + connect \Y $and$libresoc.v:157916$8238_Y end - connect \$1 $and$libresoc.v:157148$8306_Y + connect \$1 $and$libresoc.v:157916$8238_Y connect \trigger \$1 end -attribute \src "libresoc.v:157154.1-157165.10" +attribute \src "libresoc.v:157922.1-157933.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n" attribute \generator "nMigen" module \n$66 - attribute \src "libresoc.v:157163.17-157163.111" - wire $and$libresoc.v:157163$8307_Y + attribute \src "libresoc.v:157931.17-157931.111" + wire $and$libresoc.v:157931$8239_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326683,7 +293226,7 @@ module \n$66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157163$8307 + cell $and $and$libresoc.v:157931$8239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326691,18 +293234,18 @@ module \n$66 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157163$8307_Y + connect \Y $and$libresoc.v:157931$8239_Y end - connect \$1 $and$libresoc.v:157163$8307_Y + connect \$1 $and$libresoc.v:157931$8239_Y connect \trigger \$1 end -attribute \src "libresoc.v:157169.1-157180.10" +attribute \src "libresoc.v:157937.1-157948.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.n" attribute \generator "nMigen" module \n$75 - attribute \src "libresoc.v:157178.17-157178.111" - wire $and$libresoc.v:157178$8308_Y + attribute \src "libresoc.v:157946.17-157946.111" + wire $and$libresoc.v:157946$8240_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326712,7 +293255,7 @@ module \n$75 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157178$8308 + cell $and $and$libresoc.v:157946$8240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326720,18 +293263,18 @@ module \n$75 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157178$8308_Y + connect \Y $and$libresoc.v:157946$8240_Y end - connect \$1 $and$libresoc.v:157178$8308_Y + connect \$1 $and$libresoc.v:157946$8240_Y connect \trigger \$1 end -attribute \src "libresoc.v:157184.1-157195.10" +attribute \src "libresoc.v:157952.1-157963.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n" attribute \generator "nMigen" module \n$77 - attribute \src "libresoc.v:157193.17-157193.111" - wire $and$libresoc.v:157193$8309_Y + attribute \src "libresoc.v:157961.17-157961.111" + wire $and$libresoc.v:157961$8241_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326741,7 +293284,7 @@ module \n$77 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157193$8309 + cell $and $and$libresoc.v:157961$8241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326749,18 +293292,18 @@ module \n$77 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157193$8309_Y + connect \Y $and$libresoc.v:157961$8241_Y end - connect \$1 $and$libresoc.v:157193$8309_Y + connect \$1 $and$libresoc.v:157961$8241_Y connect \trigger \$1 end -attribute \src "libresoc.v:157199.1-157210.10" +attribute \src "libresoc.v:157967.1-157978.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n" attribute \generator "nMigen" module \n$8 - attribute \src "libresoc.v:157208.17-157208.111" - wire $and$libresoc.v:157208$8310_Y + attribute \src "libresoc.v:157976.17-157976.111" + wire $and$libresoc.v:157976$8242_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326770,7 +293313,7 @@ module \n$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157208$8310 + cell $and $and$libresoc.v:157976$8242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326778,18 +293321,18 @@ module \n$8 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157208$8310_Y + connect \Y $and$libresoc.v:157976$8242_Y end - connect \$1 $and$libresoc.v:157208$8310_Y + connect \$1 $and$libresoc.v:157976$8242_Y connect \trigger \$1 end -attribute \src "libresoc.v:157214.1-157225.10" +attribute \src "libresoc.v:157982.1-157993.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n" attribute \generator "nMigen" module \n$80 - attribute \src "libresoc.v:157223.17-157223.111" - wire $and$libresoc.v:157223$8311_Y + attribute \src "libresoc.v:157991.17-157991.111" + wire $and$libresoc.v:157991$8243_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326799,7 +293342,7 @@ module \n$80 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157223$8311 + cell $and $and$libresoc.v:157991$8243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326807,18 +293350,18 @@ module \n$80 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157223$8311_Y + connect \Y $and$libresoc.v:157991$8243_Y end - connect \$1 $and$libresoc.v:157223$8311_Y + connect \$1 $and$libresoc.v:157991$8243_Y connect \trigger \$1 end -attribute \src "libresoc.v:157229.1-157240.10" +attribute \src "libresoc.v:157997.1-158008.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n" attribute \generator "nMigen" module \n$82 - attribute \src "libresoc.v:157238.17-157238.111" - wire $and$libresoc.v:157238$8312_Y + attribute \src "libresoc.v:158006.17-158006.111" + wire $and$libresoc.v:158006$8244_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326828,7 +293371,7 @@ module \n$82 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157238$8312 + cell $and $and$libresoc.v:158006$8244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326836,18 +293379,18 @@ module \n$82 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157238$8312_Y + connect \Y $and$libresoc.v:158006$8244_Y end - connect \$1 $and$libresoc.v:157238$8312_Y + connect \$1 $and$libresoc.v:158006$8244_Y connect \trigger \$1 end -attribute \src "libresoc.v:157244.1-157255.10" +attribute \src "libresoc.v:158012.1-158023.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.n" attribute \generator "nMigen" module \n$92 - attribute \src "libresoc.v:157253.17-157253.111" - wire $and$libresoc.v:157253$8313_Y + attribute \src "libresoc.v:158021.17-158021.111" + wire $and$libresoc.v:158021$8245_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326857,7 +293400,7 @@ module \n$92 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157253$8313 + cell $and $and$libresoc.v:158021$8245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326865,18 +293408,18 @@ module \n$92 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157253$8313_Y + connect \Y $and$libresoc.v:158021$8245_Y end - connect \$1 $and$libresoc.v:157253$8313_Y + connect \$1 $and$libresoc.v:158021$8245_Y connect \trigger \$1 end -attribute \src "libresoc.v:157259.1-157270.10" +attribute \src "libresoc.v:158027.1-158038.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n" attribute \generator "nMigen" module \n$94 - attribute \src "libresoc.v:157268.17-157268.111" - wire $and$libresoc.v:157268$8314_Y + attribute \src "libresoc.v:158036.17-158036.111" + wire $and$libresoc.v:158036$8246_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326886,7 +293429,7 @@ module \n$94 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157268$8314 + cell $and $and$libresoc.v:158036$8246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326894,18 +293437,18 @@ module \n$94 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157268$8314_Y + connect \Y $and$libresoc.v:158036$8246_Y end - connect \$1 $and$libresoc.v:157268$8314_Y + connect \$1 $and$libresoc.v:158036$8246_Y connect \trigger \$1 end -attribute \src "libresoc.v:157274.1-157285.10" +attribute \src "libresoc.v:158042.1-158053.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n" attribute \generator "nMigen" module \n$97 - attribute \src "libresoc.v:157283.17-157283.111" - wire $and$libresoc.v:157283$8315_Y + attribute \src "libresoc.v:158051.17-158051.111" + wire $and$libresoc.v:158051$8247_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326915,7 +293458,7 @@ module \n$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157283$8315 + cell $and $and$libresoc.v:158051$8247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326923,18 +293466,18 @@ module \n$97 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157283$8315_Y + connect \Y $and$libresoc.v:158051$8247_Y end - connect \$1 $and$libresoc.v:157283$8315_Y + connect \$1 $and$libresoc.v:158051$8247_Y connect \trigger \$1 end -attribute \src "libresoc.v:157289.1-157300.10" +attribute \src "libresoc.v:158057.1-158068.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n" attribute \generator "nMigen" module \n$99 - attribute \src "libresoc.v:157298.17-157298.111" - wire $and$libresoc.v:157298$8316_Y + attribute \src "libresoc.v:158066.17-158066.111" + wire $and$libresoc.v:158066$8248_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326944,7 +293487,7 @@ module \n$99 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157298$8316 + cell $and $and$libresoc.v:158066$8248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326952,42 +293495,42 @@ module \n$99 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157298$8316_Y + connect \Y $and$libresoc.v:158066$8248_Y end - connect \$1 $and$libresoc.v:157298$8316_Y + connect \$1 $and$libresoc.v:158066$8248_Y connect \trigger \$1 end -attribute \src "libresoc.v:157304.1-157362.10" +attribute \src "libresoc.v:158072.1-158130.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.opc_l" attribute \generator "nMigen" module \opc_l - attribute \src "libresoc.v:157305.7-157305.20" + attribute \src "libresoc.v:158073.7-158073.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157350.3-157358.6" - wire $0\q_int$next[0:0]$8327 - attribute \src "libresoc.v:157348.3-157349.27" + attribute \src "libresoc.v:158118.3-158126.6" + wire $0\q_int$next[0:0]$8259 + attribute \src "libresoc.v:158116.3-158117.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157350.3-157358.6" - wire $1\q_int$next[0:0]$8328 - attribute \src "libresoc.v:157327.7-157327.19" + attribute \src "libresoc.v:158118.3-158126.6" + wire $1\q_int$next[0:0]$8260 + attribute \src "libresoc.v:158095.7-158095.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157340.17-157340.96" - wire $and$libresoc.v:157340$8317_Y - attribute \src "libresoc.v:157345.17-157345.96" - wire $and$libresoc.v:157345$8322_Y - attribute \src "libresoc.v:157342.18-157342.93" - wire $not$libresoc.v:157342$8319_Y - attribute \src "libresoc.v:157344.17-157344.92" - wire $not$libresoc.v:157344$8321_Y - attribute \src "libresoc.v:157347.17-157347.92" - wire $not$libresoc.v:157347$8324_Y - attribute \src "libresoc.v:157341.18-157341.98" - wire $or$libresoc.v:157341$8318_Y - attribute \src "libresoc.v:157343.18-157343.99" - wire $or$libresoc.v:157343$8320_Y - attribute \src "libresoc.v:157346.17-157346.97" - wire $or$libresoc.v:157346$8323_Y + attribute \src "libresoc.v:158108.17-158108.96" + wire $and$libresoc.v:158108$8249_Y + attribute \src "libresoc.v:158113.17-158113.96" + wire $and$libresoc.v:158113$8254_Y + attribute \src "libresoc.v:158110.18-158110.93" + wire $not$libresoc.v:158110$8251_Y + attribute \src "libresoc.v:158112.17-158112.92" + wire $not$libresoc.v:158112$8253_Y + attribute \src "libresoc.v:158115.17-158115.92" + wire $not$libresoc.v:158115$8256_Y + attribute \src "libresoc.v:158109.18-158109.98" + wire $or$libresoc.v:158109$8250_Y + attribute \src "libresoc.v:158111.18-158111.99" + wire $or$libresoc.v:158111$8252_Y + attribute \src "libresoc.v:158114.17-158114.97" + wire $or$libresoc.v:158114$8255_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -327004,11 +293547,11 @@ module \opc_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:157305.7-157305.15" + attribute \src "libresoc.v:158073.7-158073.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -327025,7 +293568,7 @@ module \opc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157340$8317 + cell $and $and$libresoc.v:158108$8249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327033,10 +293576,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157340$8317_Y + connect \Y $and$libresoc.v:158108$8249_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157345$8322 + cell $and $and$libresoc.v:158113$8254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327044,34 +293587,34 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157345$8322_Y + connect \Y $and$libresoc.v:158113$8254_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157342$8319 + cell $not $not$libresoc.v:158110$8251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157342$8319_Y + connect \Y $not$libresoc.v:158110$8251_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157344$8321 + cell $not $not$libresoc.v:158112$8253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157344$8321_Y + connect \Y $not$libresoc.v:158112$8253_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157347$8324 + cell $not $not$libresoc.v:158115$8256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157347$8324_Y + connect \Y $not$libresoc.v:158115$8256_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157341$8318 + cell $or $or$libresoc.v:158109$8250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327079,10 +293622,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157341$8318_Y + connect \Y $or$libresoc.v:158109$8250_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157343$8320 + cell $or $or$libresoc.v:158111$8252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327090,10 +293633,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157343$8320_Y + connect \Y $or$libresoc.v:158111$8252_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157346$8323 + cell $or $or$libresoc.v:158114$8255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327101,39 +293644,39 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157346$8323_Y + connect \Y $or$libresoc.v:158114$8255_Y end - attribute \src "libresoc.v:157305.7-157305.20" - process $proc$libresoc.v:157305$8329 + attribute \src "libresoc.v:158073.7-158073.20" + process $proc$libresoc.v:158073$8261 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157327.7-157327.19" - process $proc$libresoc.v:157327$8330 + attribute \src "libresoc.v:158095.7-158095.19" + process $proc$libresoc.v:158095$8262 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157348.3-157349.27" - process $proc$libresoc.v:157348$8325 + attribute \src "libresoc.v:158116.3-158117.27" + process $proc$libresoc.v:158116$8257 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157350.3-157358.6" - process $proc$libresoc.v:157350$8326 + attribute \src "libresoc.v:158118.3-158126.6" + process $proc$libresoc.v:158118$8258 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8327 $1\q_int$next[0:0]$8328 - attribute \src "libresoc.v:157351.5-157351.29" + assign $0\q_int$next[0:0]$8259 $1\q_int$next[0:0]$8260 + attribute \src "libresoc.v:158119.5-158119.29" switch \initial - attribute \src "libresoc.v:157351.9-157351.17" + attribute \src "libresoc.v:158119.9-158119.17" case 1'1 case end @@ -327142,56 +293685,56 @@ module \opc_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8328 1'0 + assign $1\q_int$next[0:0]$8260 1'0 case - assign $1\q_int$next[0:0]$8328 \$5 + assign $1\q_int$next[0:0]$8260 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8327 + update \q_int$next $0\q_int$next[0:0]$8259 end - connect \$9 $and$libresoc.v:157340$8317_Y - connect \$11 $or$libresoc.v:157341$8318_Y - connect \$13 $not$libresoc.v:157342$8319_Y - connect \$15 $or$libresoc.v:157343$8320_Y - connect \$1 $not$libresoc.v:157344$8321_Y - connect \$3 $and$libresoc.v:157345$8322_Y - connect \$5 $or$libresoc.v:157346$8323_Y - connect \$7 $not$libresoc.v:157347$8324_Y + connect \$9 $and$libresoc.v:158108$8249_Y + connect \$11 $or$libresoc.v:158109$8250_Y + connect \$13 $not$libresoc.v:158110$8251_Y + connect \$15 $or$libresoc.v:158111$8252_Y + connect \$1 $not$libresoc.v:158112$8253_Y + connect \$3 $and$libresoc.v:158113$8254_Y + connect \$5 $or$libresoc.v:158114$8255_Y + connect \$7 $not$libresoc.v:158115$8256_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157366.1-157424.10" +attribute \src "libresoc.v:158134.1-158192.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.opc_l" attribute \generator "nMigen" module \opc_l$102 - attribute \src "libresoc.v:157367.7-157367.20" + attribute \src "libresoc.v:158135.7-158135.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157412.3-157420.6" - wire $0\q_int$next[0:0]$8341 - attribute \src "libresoc.v:157410.3-157411.27" + attribute \src "libresoc.v:158180.3-158188.6" + wire $0\q_int$next[0:0]$8273 + attribute \src "libresoc.v:158178.3-158179.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157412.3-157420.6" - wire $1\q_int$next[0:0]$8342 - attribute \src "libresoc.v:157389.7-157389.19" + attribute \src "libresoc.v:158180.3-158188.6" + wire $1\q_int$next[0:0]$8274 + attribute \src "libresoc.v:158157.7-158157.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157402.17-157402.96" - wire $and$libresoc.v:157402$8331_Y - attribute \src "libresoc.v:157407.17-157407.96" - wire $and$libresoc.v:157407$8336_Y - attribute \src "libresoc.v:157404.18-157404.93" - wire $not$libresoc.v:157404$8333_Y - attribute \src "libresoc.v:157406.17-157406.92" - wire $not$libresoc.v:157406$8335_Y - attribute \src "libresoc.v:157409.17-157409.92" - wire $not$libresoc.v:157409$8338_Y - attribute \src "libresoc.v:157403.18-157403.98" - wire $or$libresoc.v:157403$8332_Y - attribute \src "libresoc.v:157405.18-157405.99" - wire $or$libresoc.v:157405$8334_Y - attribute \src "libresoc.v:157408.17-157408.97" - wire $or$libresoc.v:157408$8337_Y + attribute \src "libresoc.v:158170.17-158170.96" + wire $and$libresoc.v:158170$8263_Y + attribute \src "libresoc.v:158175.17-158175.96" + wire $and$libresoc.v:158175$8268_Y + attribute \src "libresoc.v:158172.18-158172.93" + wire $not$libresoc.v:158172$8265_Y + attribute \src "libresoc.v:158174.17-158174.92" + wire $not$libresoc.v:158174$8267_Y + attribute \src "libresoc.v:158177.17-158177.92" + wire $not$libresoc.v:158177$8270_Y + attribute \src "libresoc.v:158171.18-158171.98" + wire $or$libresoc.v:158171$8264_Y + attribute \src "libresoc.v:158173.18-158173.99" + wire $or$libresoc.v:158173$8266_Y + attribute \src "libresoc.v:158176.17-158176.97" + wire $or$libresoc.v:158176$8269_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -327208,11 +293751,11 @@ module \opc_l$102 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:157367.7-157367.15" + attribute \src "libresoc.v:158135.7-158135.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -327229,7 +293772,7 @@ module \opc_l$102 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157402$8331 + cell $and $and$libresoc.v:158170$8263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327237,10 +293780,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157402$8331_Y + connect \Y $and$libresoc.v:158170$8263_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157407$8336 + cell $and $and$libresoc.v:158175$8268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327248,34 +293791,34 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157407$8336_Y + connect \Y $and$libresoc.v:158175$8268_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157404$8333 + cell $not $not$libresoc.v:158172$8265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157404$8333_Y + connect \Y $not$libresoc.v:158172$8265_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157406$8335 + cell $not $not$libresoc.v:158174$8267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157406$8335_Y + connect \Y $not$libresoc.v:158174$8267_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157409$8338 + cell $not $not$libresoc.v:158177$8270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157409$8338_Y + connect \Y $not$libresoc.v:158177$8270_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157403$8332 + cell $or $or$libresoc.v:158171$8264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327283,10 +293826,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157403$8332_Y + connect \Y $or$libresoc.v:158171$8264_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157405$8334 + cell $or $or$libresoc.v:158173$8266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327294,10 +293837,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157405$8334_Y + connect \Y $or$libresoc.v:158173$8266_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157408$8337 + cell $or $or$libresoc.v:158176$8269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327305,39 +293848,39 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157408$8337_Y + connect \Y $or$libresoc.v:158176$8269_Y end - attribute \src "libresoc.v:157367.7-157367.20" - process $proc$libresoc.v:157367$8343 + attribute \src "libresoc.v:158135.7-158135.20" + process $proc$libresoc.v:158135$8275 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157389.7-157389.19" - process $proc$libresoc.v:157389$8344 + attribute \src "libresoc.v:158157.7-158157.19" + process $proc$libresoc.v:158157$8276 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157410.3-157411.27" - process $proc$libresoc.v:157410$8339 + attribute \src "libresoc.v:158178.3-158179.27" + process $proc$libresoc.v:158178$8271 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157412.3-157420.6" - process $proc$libresoc.v:157412$8340 + attribute \src "libresoc.v:158180.3-158188.6" + process $proc$libresoc.v:158180$8272 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8341 $1\q_int$next[0:0]$8342 - attribute \src "libresoc.v:157413.5-157413.29" + assign $0\q_int$next[0:0]$8273 $1\q_int$next[0:0]$8274 + attribute \src "libresoc.v:158181.5-158181.29" switch \initial - attribute \src "libresoc.v:157413.9-157413.17" + attribute \src "libresoc.v:158181.9-158181.17" case 1'1 case end @@ -327346,56 +293889,56 @@ module \opc_l$102 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8342 1'0 + assign $1\q_int$next[0:0]$8274 1'0 case - assign $1\q_int$next[0:0]$8342 \$5 + assign $1\q_int$next[0:0]$8274 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8341 + update \q_int$next $0\q_int$next[0:0]$8273 end - connect \$9 $and$libresoc.v:157402$8331_Y - connect \$11 $or$libresoc.v:157403$8332_Y - connect \$13 $not$libresoc.v:157404$8333_Y - connect \$15 $or$libresoc.v:157405$8334_Y - connect \$1 $not$libresoc.v:157406$8335_Y - connect \$3 $and$libresoc.v:157407$8336_Y - connect \$5 $or$libresoc.v:157408$8337_Y - connect \$7 $not$libresoc.v:157409$8338_Y + connect \$9 $and$libresoc.v:158170$8263_Y + connect \$11 $or$libresoc.v:158171$8264_Y + connect \$13 $not$libresoc.v:158172$8265_Y + connect \$15 $or$libresoc.v:158173$8266_Y + connect \$1 $not$libresoc.v:158174$8267_Y + connect \$3 $and$libresoc.v:158175$8268_Y + connect \$5 $or$libresoc.v:158176$8269_Y + connect \$7 $not$libresoc.v:158177$8270_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157428.1-157486.10" +attribute \src "libresoc.v:158196.1-158254.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l" attribute \generator "nMigen" module \opc_l$11 - attribute \src "libresoc.v:157429.7-157429.20" + attribute \src "libresoc.v:158197.7-158197.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157474.3-157482.6" - wire $0\q_int$next[0:0]$8355 - attribute \src "libresoc.v:157472.3-157473.27" + attribute \src "libresoc.v:158242.3-158250.6" + wire $0\q_int$next[0:0]$8287 + attribute \src "libresoc.v:158240.3-158241.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157474.3-157482.6" - wire $1\q_int$next[0:0]$8356 - attribute \src "libresoc.v:157451.7-157451.19" + attribute \src "libresoc.v:158242.3-158250.6" + wire $1\q_int$next[0:0]$8288 + attribute \src "libresoc.v:158219.7-158219.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157464.17-157464.96" - wire $and$libresoc.v:157464$8345_Y - attribute \src "libresoc.v:157469.17-157469.96" - wire $and$libresoc.v:157469$8350_Y - attribute \src "libresoc.v:157466.18-157466.93" - wire $not$libresoc.v:157466$8347_Y - attribute \src "libresoc.v:157468.17-157468.92" - wire $not$libresoc.v:157468$8349_Y - attribute \src "libresoc.v:157471.17-157471.92" - wire $not$libresoc.v:157471$8352_Y - attribute \src "libresoc.v:157465.18-157465.98" - wire $or$libresoc.v:157465$8346_Y - attribute \src "libresoc.v:157467.18-157467.99" - wire $or$libresoc.v:157467$8348_Y - attribute \src "libresoc.v:157470.17-157470.97" - wire $or$libresoc.v:157470$8351_Y + attribute \src "libresoc.v:158232.17-158232.96" + wire $and$libresoc.v:158232$8277_Y + attribute \src "libresoc.v:158237.17-158237.96" + wire $and$libresoc.v:158237$8282_Y + attribute \src "libresoc.v:158234.18-158234.93" + wire $not$libresoc.v:158234$8279_Y + attribute \src "libresoc.v:158236.17-158236.92" + wire $not$libresoc.v:158236$8281_Y + attribute \src "libresoc.v:158239.17-158239.92" + wire $not$libresoc.v:158239$8284_Y + attribute \src "libresoc.v:158233.18-158233.98" + wire $or$libresoc.v:158233$8278_Y + attribute \src "libresoc.v:158235.18-158235.99" + wire $or$libresoc.v:158235$8280_Y + attribute \src "libresoc.v:158238.17-158238.97" + wire $or$libresoc.v:158238$8283_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -327412,11 +293955,11 @@ module \opc_l$11 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:157429.7-157429.15" + attribute \src "libresoc.v:158197.7-158197.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -327433,7 +293976,7 @@ module \opc_l$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157464$8345 + cell $and $and$libresoc.v:158232$8277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327441,10 +293984,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157464$8345_Y + connect \Y $and$libresoc.v:158232$8277_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157469$8350 + cell $and $and$libresoc.v:158237$8282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327452,34 +293995,34 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157469$8350_Y + connect \Y $and$libresoc.v:158237$8282_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157466$8347 + cell $not $not$libresoc.v:158234$8279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157466$8347_Y + connect \Y $not$libresoc.v:158234$8279_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157468$8349 + cell $not $not$libresoc.v:158236$8281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157468$8349_Y + connect \Y $not$libresoc.v:158236$8281_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157471$8352 + cell $not $not$libresoc.v:158239$8284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157471$8352_Y + connect \Y $not$libresoc.v:158239$8284_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157465$8346 + cell $or $or$libresoc.v:158233$8278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327487,10 +294030,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157465$8346_Y + connect \Y $or$libresoc.v:158233$8278_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157467$8348 + cell $or $or$libresoc.v:158235$8280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327498,10 +294041,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157467$8348_Y + connect \Y $or$libresoc.v:158235$8280_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157470$8351 + cell $or $or$libresoc.v:158238$8283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327509,39 +294052,39 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157470$8351_Y + connect \Y $or$libresoc.v:158238$8283_Y end - attribute \src "libresoc.v:157429.7-157429.20" - process $proc$libresoc.v:157429$8357 + attribute \src "libresoc.v:158197.7-158197.20" + process $proc$libresoc.v:158197$8289 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157451.7-157451.19" - process $proc$libresoc.v:157451$8358 + attribute \src "libresoc.v:158219.7-158219.19" + process $proc$libresoc.v:158219$8290 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157472.3-157473.27" - process $proc$libresoc.v:157472$8353 + attribute \src "libresoc.v:158240.3-158241.27" + process $proc$libresoc.v:158240$8285 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157474.3-157482.6" - process $proc$libresoc.v:157474$8354 + attribute \src "libresoc.v:158242.3-158250.6" + process $proc$libresoc.v:158242$8286 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8355 $1\q_int$next[0:0]$8356 - attribute \src "libresoc.v:157475.5-157475.29" + assign $0\q_int$next[0:0]$8287 $1\q_int$next[0:0]$8288 + attribute \src "libresoc.v:158243.5-158243.29" switch \initial - attribute \src "libresoc.v:157475.9-157475.17" + attribute \src "libresoc.v:158243.9-158243.17" case 1'1 case end @@ -327550,56 +294093,56 @@ module \opc_l$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8356 1'0 + assign $1\q_int$next[0:0]$8288 1'0 case - assign $1\q_int$next[0:0]$8356 \$5 + assign $1\q_int$next[0:0]$8288 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8355 + update \q_int$next $0\q_int$next[0:0]$8287 end - connect \$9 $and$libresoc.v:157464$8345_Y - connect \$11 $or$libresoc.v:157465$8346_Y - connect \$13 $not$libresoc.v:157466$8347_Y - connect \$15 $or$libresoc.v:157467$8348_Y - connect \$1 $not$libresoc.v:157468$8349_Y - connect \$3 $and$libresoc.v:157469$8350_Y - connect \$5 $or$libresoc.v:157470$8351_Y - connect \$7 $not$libresoc.v:157471$8352_Y + connect \$9 $and$libresoc.v:158232$8277_Y + connect \$11 $or$libresoc.v:158233$8278_Y + connect \$13 $not$libresoc.v:158234$8279_Y + connect \$15 $or$libresoc.v:158235$8280_Y + connect \$1 $not$libresoc.v:158236$8281_Y + connect \$3 $and$libresoc.v:158237$8282_Y + connect \$5 $or$libresoc.v:158238$8283_Y + connect \$7 $not$libresoc.v:158239$8284_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157490.1-157548.10" +attribute \src "libresoc.v:158258.1-158316.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" attribute \generator "nMigen" module \opc_l$120 - attribute \src "libresoc.v:157491.7-157491.20" + attribute \src "libresoc.v:158259.7-158259.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157536.3-157544.6" - wire $0\q_int$next[0:0]$8369 - attribute \src "libresoc.v:157534.3-157535.27" + attribute \src "libresoc.v:158304.3-158312.6" + wire $0\q_int$next[0:0]$8301 + attribute \src "libresoc.v:158302.3-158303.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157536.3-157544.6" - wire $1\q_int$next[0:0]$8370 - attribute \src "libresoc.v:157513.7-157513.19" + attribute \src "libresoc.v:158304.3-158312.6" + wire $1\q_int$next[0:0]$8302 + attribute \src "libresoc.v:158281.7-158281.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157526.17-157526.96" - wire $and$libresoc.v:157526$8359_Y - attribute \src "libresoc.v:157531.17-157531.96" - wire $and$libresoc.v:157531$8364_Y - attribute \src "libresoc.v:157528.18-157528.93" - wire $not$libresoc.v:157528$8361_Y - attribute \src "libresoc.v:157530.17-157530.92" - wire $not$libresoc.v:157530$8363_Y - attribute \src "libresoc.v:157533.17-157533.92" - wire $not$libresoc.v:157533$8366_Y - attribute \src "libresoc.v:157527.18-157527.98" - wire $or$libresoc.v:157527$8360_Y - attribute \src "libresoc.v:157529.18-157529.99" - wire $or$libresoc.v:157529$8362_Y - attribute \src "libresoc.v:157532.17-157532.97" - wire $or$libresoc.v:157532$8365_Y + attribute \src "libresoc.v:158294.17-158294.96" + wire $and$libresoc.v:158294$8291_Y + attribute \src "libresoc.v:158299.17-158299.96" + wire $and$libresoc.v:158299$8296_Y + attribute \src "libresoc.v:158296.18-158296.93" + wire $not$libresoc.v:158296$8293_Y + attribute \src "libresoc.v:158298.17-158298.92" + wire $not$libresoc.v:158298$8295_Y + attribute \src "libresoc.v:158301.17-158301.92" + wire $not$libresoc.v:158301$8298_Y + attribute \src "libresoc.v:158295.18-158295.98" + wire $or$libresoc.v:158295$8292_Y + attribute \src "libresoc.v:158297.18-158297.99" + wire $or$libresoc.v:158297$8294_Y + attribute \src "libresoc.v:158300.17-158300.97" + wire $or$libresoc.v:158300$8297_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -327616,11 +294159,11 @@ module \opc_l$120 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:157491.7-157491.15" + attribute \src "libresoc.v:158259.7-158259.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -327637,7 +294180,7 @@ module \opc_l$120 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157526$8359 + cell $and $and$libresoc.v:158294$8291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327645,10 +294188,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157526$8359_Y + connect \Y $and$libresoc.v:158294$8291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157531$8364 + cell $and $and$libresoc.v:158299$8296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327656,34 +294199,34 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157531$8364_Y + connect \Y $and$libresoc.v:158299$8296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157528$8361 + cell $not $not$libresoc.v:158296$8293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157528$8361_Y + connect \Y $not$libresoc.v:158296$8293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157530$8363 + cell $not $not$libresoc.v:158298$8295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157530$8363_Y + connect \Y $not$libresoc.v:158298$8295_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157533$8366 + cell $not $not$libresoc.v:158301$8298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157533$8366_Y + connect \Y $not$libresoc.v:158301$8298_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157527$8360 + cell $or $or$libresoc.v:158295$8292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327691,10 +294234,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157527$8360_Y + connect \Y $or$libresoc.v:158295$8292_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157529$8362 + cell $or $or$libresoc.v:158297$8294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327702,10 +294245,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157529$8362_Y + connect \Y $or$libresoc.v:158297$8294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157532$8365 + cell $or $or$libresoc.v:158300$8297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327713,39 +294256,39 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157532$8365_Y + connect \Y $or$libresoc.v:158300$8297_Y end - attribute \src "libresoc.v:157491.7-157491.20" - process $proc$libresoc.v:157491$8371 + attribute \src "libresoc.v:158259.7-158259.20" + process $proc$libresoc.v:158259$8303 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157513.7-157513.19" - process $proc$libresoc.v:157513$8372 + attribute \src "libresoc.v:158281.7-158281.19" + process $proc$libresoc.v:158281$8304 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157534.3-157535.27" - process $proc$libresoc.v:157534$8367 + attribute \src "libresoc.v:158302.3-158303.27" + process $proc$libresoc.v:158302$8299 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157536.3-157544.6" - process $proc$libresoc.v:157536$8368 + attribute \src "libresoc.v:158304.3-158312.6" + process $proc$libresoc.v:158304$8300 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8369 $1\q_int$next[0:0]$8370 - attribute \src "libresoc.v:157537.5-157537.29" + assign $0\q_int$next[0:0]$8301 $1\q_int$next[0:0]$8302 + attribute \src "libresoc.v:158305.5-158305.29" switch \initial - attribute \src "libresoc.v:157537.9-157537.17" + attribute \src "libresoc.v:158305.9-158305.17" case 1'1 case end @@ -327754,56 +294297,56 @@ module \opc_l$120 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8370 1'0 + assign $1\q_int$next[0:0]$8302 1'0 case - assign $1\q_int$next[0:0]$8370 \$5 + assign $1\q_int$next[0:0]$8302 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8369 + update \q_int$next $0\q_int$next[0:0]$8301 end - connect \$9 $and$libresoc.v:157526$8359_Y - connect \$11 $or$libresoc.v:157527$8360_Y - connect \$13 $not$libresoc.v:157528$8361_Y - connect \$15 $or$libresoc.v:157529$8362_Y - connect \$1 $not$libresoc.v:157530$8363_Y - connect \$3 $and$libresoc.v:157531$8364_Y - connect \$5 $or$libresoc.v:157532$8365_Y - connect \$7 $not$libresoc.v:157533$8366_Y + connect \$9 $and$libresoc.v:158294$8291_Y + connect \$11 $or$libresoc.v:158295$8292_Y + connect \$13 $not$libresoc.v:158296$8293_Y + connect \$15 $or$libresoc.v:158297$8294_Y + connect \$1 $not$libresoc.v:158298$8295_Y + connect \$3 $and$libresoc.v:158299$8296_Y + connect \$5 $or$libresoc.v:158300$8297_Y + connect \$7 $not$libresoc.v:158301$8298_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157552.1-157610.10" +attribute \src "libresoc.v:158320.1-158378.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" attribute \generator "nMigen" module \opc_l$126 - attribute \src "libresoc.v:157553.7-157553.20" + attribute \src "libresoc.v:158321.7-158321.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157598.3-157606.6" - wire $0\q_int$next[0:0]$8383 - attribute \src "libresoc.v:157596.3-157597.27" + attribute \src "libresoc.v:158366.3-158374.6" + wire $0\q_int$next[0:0]$8315 + attribute \src "libresoc.v:158364.3-158365.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157598.3-157606.6" - wire $1\q_int$next[0:0]$8384 - attribute \src "libresoc.v:157575.7-157575.19" + attribute \src "libresoc.v:158366.3-158374.6" + wire $1\q_int$next[0:0]$8316 + attribute \src "libresoc.v:158343.7-158343.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157588.17-157588.96" - wire $and$libresoc.v:157588$8373_Y - attribute \src "libresoc.v:157593.17-157593.96" - wire $and$libresoc.v:157593$8378_Y - attribute \src "libresoc.v:157590.18-157590.93" - wire $not$libresoc.v:157590$8375_Y - attribute \src "libresoc.v:157592.17-157592.92" - wire $not$libresoc.v:157592$8377_Y - attribute \src "libresoc.v:157595.17-157595.92" - wire $not$libresoc.v:157595$8380_Y - attribute \src "libresoc.v:157589.18-157589.98" - wire $or$libresoc.v:157589$8374_Y - attribute \src "libresoc.v:157591.18-157591.99" - wire $or$libresoc.v:157591$8376_Y - attribute \src "libresoc.v:157594.17-157594.97" - wire $or$libresoc.v:157594$8379_Y + attribute \src "libresoc.v:158356.17-158356.96" + wire $and$libresoc.v:158356$8305_Y + attribute \src "libresoc.v:158361.17-158361.96" + wire $and$libresoc.v:158361$8310_Y + attribute \src "libresoc.v:158358.18-158358.93" + wire $not$libresoc.v:158358$8307_Y + attribute \src "libresoc.v:158360.17-158360.92" + wire $not$libresoc.v:158360$8309_Y + attribute \src "libresoc.v:158363.17-158363.92" + wire $not$libresoc.v:158363$8312_Y + attribute \src "libresoc.v:158357.18-158357.98" + wire $or$libresoc.v:158357$8306_Y + attribute \src "libresoc.v:158359.18-158359.99" + wire $or$libresoc.v:158359$8308_Y + attribute \src "libresoc.v:158362.17-158362.97" + wire $or$libresoc.v:158362$8311_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -327820,11 +294363,11 @@ module \opc_l$126 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:157553.7-157553.15" + attribute \src "libresoc.v:158321.7-158321.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -327841,7 +294384,7 @@ module \opc_l$126 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157588$8373 + cell $and $and$libresoc.v:158356$8305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327849,10 +294392,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157588$8373_Y + connect \Y $and$libresoc.v:158356$8305_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157593$8378 + cell $and $and$libresoc.v:158361$8310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327860,34 +294403,34 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157593$8378_Y + connect \Y $and$libresoc.v:158361$8310_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157590$8375 + cell $not $not$libresoc.v:158358$8307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157590$8375_Y + connect \Y $not$libresoc.v:158358$8307_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157592$8377 + cell $not $not$libresoc.v:158360$8309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157592$8377_Y + connect \Y $not$libresoc.v:158360$8309_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157595$8380 + cell $not $not$libresoc.v:158363$8312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157595$8380_Y + connect \Y $not$libresoc.v:158363$8312_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157589$8374 + cell $or $or$libresoc.v:158357$8306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327895,10 +294438,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157589$8374_Y + connect \Y $or$libresoc.v:158357$8306_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157591$8376 + cell $or $or$libresoc.v:158359$8308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327906,10 +294449,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157591$8376_Y + connect \Y $or$libresoc.v:158359$8308_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157594$8379 + cell $or $or$libresoc.v:158362$8311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327917,39 +294460,39 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157594$8379_Y + connect \Y $or$libresoc.v:158362$8311_Y end - attribute \src "libresoc.v:157553.7-157553.20" - process $proc$libresoc.v:157553$8385 + attribute \src "libresoc.v:158321.7-158321.20" + process $proc$libresoc.v:158321$8317 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157575.7-157575.19" - process $proc$libresoc.v:157575$8386 + attribute \src "libresoc.v:158343.7-158343.19" + process $proc$libresoc.v:158343$8318 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157596.3-157597.27" - process $proc$libresoc.v:157596$8381 + attribute \src "libresoc.v:158364.3-158365.27" + process $proc$libresoc.v:158364$8313 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157598.3-157606.6" - process $proc$libresoc.v:157598$8382 + attribute \src "libresoc.v:158366.3-158374.6" + process $proc$libresoc.v:158366$8314 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8383 $1\q_int$next[0:0]$8384 - attribute \src "libresoc.v:157599.5-157599.29" + assign $0\q_int$next[0:0]$8315 $1\q_int$next[0:0]$8316 + attribute \src "libresoc.v:158367.5-158367.29" switch \initial - attribute \src "libresoc.v:157599.9-157599.17" + attribute \src "libresoc.v:158367.9-158367.17" case 1'1 case end @@ -327958,56 +294501,56 @@ module \opc_l$126 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8384 1'0 + assign $1\q_int$next[0:0]$8316 1'0 case - assign $1\q_int$next[0:0]$8384 \$5 + assign $1\q_int$next[0:0]$8316 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8383 + update \q_int$next $0\q_int$next[0:0]$8315 end - connect \$9 $and$libresoc.v:157588$8373_Y - connect \$11 $or$libresoc.v:157589$8374_Y - connect \$13 $not$libresoc.v:157590$8375_Y - connect \$15 $or$libresoc.v:157591$8376_Y - connect \$1 $not$libresoc.v:157592$8377_Y - connect \$3 $and$libresoc.v:157593$8378_Y - connect \$5 $or$libresoc.v:157594$8379_Y - connect \$7 $not$libresoc.v:157595$8380_Y + connect \$9 $and$libresoc.v:158356$8305_Y + connect \$11 $or$libresoc.v:158357$8306_Y + connect \$13 $not$libresoc.v:158358$8307_Y + connect \$15 $or$libresoc.v:158359$8308_Y + connect \$1 $not$libresoc.v:158360$8309_Y + connect \$3 $and$libresoc.v:158361$8310_Y + connect \$5 $or$libresoc.v:158362$8311_Y + connect \$7 $not$libresoc.v:158363$8312_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157614.1-157672.10" +attribute \src "libresoc.v:158382.1-158440.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" attribute \generator "nMigen" module \opc_l$24 - attribute \src "libresoc.v:157615.7-157615.20" + attribute \src "libresoc.v:158383.7-158383.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157660.3-157668.6" - wire $0\q_int$next[0:0]$8397 - attribute \src "libresoc.v:157658.3-157659.27" + attribute \src "libresoc.v:158428.3-158436.6" + wire $0\q_int$next[0:0]$8329 + attribute \src "libresoc.v:158426.3-158427.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157660.3-157668.6" - wire $1\q_int$next[0:0]$8398 - attribute \src "libresoc.v:157637.7-157637.19" + attribute \src "libresoc.v:158428.3-158436.6" + wire $1\q_int$next[0:0]$8330 + attribute \src "libresoc.v:158405.7-158405.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157650.17-157650.96" - wire $and$libresoc.v:157650$8387_Y - attribute \src "libresoc.v:157655.17-157655.96" - wire $and$libresoc.v:157655$8392_Y - attribute \src "libresoc.v:157652.18-157652.93" - wire $not$libresoc.v:157652$8389_Y - attribute \src "libresoc.v:157654.17-157654.92" - wire $not$libresoc.v:157654$8391_Y - attribute \src "libresoc.v:157657.17-157657.92" - wire $not$libresoc.v:157657$8394_Y - attribute \src "libresoc.v:157651.18-157651.98" - wire $or$libresoc.v:157651$8388_Y - attribute \src "libresoc.v:157653.18-157653.99" - wire $or$libresoc.v:157653$8390_Y - attribute \src "libresoc.v:157656.17-157656.97" - wire $or$libresoc.v:157656$8393_Y + attribute \src "libresoc.v:158418.17-158418.96" + wire $and$libresoc.v:158418$8319_Y + attribute \src "libresoc.v:158423.17-158423.96" + wire $and$libresoc.v:158423$8324_Y + attribute \src "libresoc.v:158420.18-158420.93" + wire $not$libresoc.v:158420$8321_Y + attribute \src "libresoc.v:158422.17-158422.92" + wire $not$libresoc.v:158422$8323_Y + attribute \src "libresoc.v:158425.17-158425.92" + wire $not$libresoc.v:158425$8326_Y + attribute \src "libresoc.v:158419.18-158419.98" + wire $or$libresoc.v:158419$8320_Y + attribute \src "libresoc.v:158421.18-158421.99" + wire $or$libresoc.v:158421$8322_Y + attribute \src "libresoc.v:158424.17-158424.97" + wire $or$libresoc.v:158424$8325_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -328024,11 +294567,11 @@ module \opc_l$24 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:157615.7-157615.15" + attribute \src "libresoc.v:158383.7-158383.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -328045,7 +294588,7 @@ module \opc_l$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157650$8387 + cell $and $and$libresoc.v:158418$8319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328053,10 +294596,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157650$8387_Y + connect \Y $and$libresoc.v:158418$8319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157655$8392 + cell $and $and$libresoc.v:158423$8324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328064,34 +294607,34 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157655$8392_Y + connect \Y $and$libresoc.v:158423$8324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157652$8389 + cell $not $not$libresoc.v:158420$8321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157652$8389_Y + connect \Y $not$libresoc.v:158420$8321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157654$8391 + cell $not $not$libresoc.v:158422$8323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157654$8391_Y + connect \Y $not$libresoc.v:158422$8323_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157657$8394 + cell $not $not$libresoc.v:158425$8326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157657$8394_Y + connect \Y $not$libresoc.v:158425$8326_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157651$8388 + cell $or $or$libresoc.v:158419$8320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328099,10 +294642,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157651$8388_Y + connect \Y $or$libresoc.v:158419$8320_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157653$8390 + cell $or $or$libresoc.v:158421$8322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328110,10 +294653,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157653$8390_Y + connect \Y $or$libresoc.v:158421$8322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157656$8393 + cell $or $or$libresoc.v:158424$8325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328121,39 +294664,39 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157656$8393_Y + connect \Y $or$libresoc.v:158424$8325_Y end - attribute \src "libresoc.v:157615.7-157615.20" - process $proc$libresoc.v:157615$8399 + attribute \src "libresoc.v:158383.7-158383.20" + process $proc$libresoc.v:158383$8331 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157637.7-157637.19" - process $proc$libresoc.v:157637$8400 + attribute \src "libresoc.v:158405.7-158405.19" + process $proc$libresoc.v:158405$8332 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157658.3-157659.27" - process $proc$libresoc.v:157658$8395 + attribute \src "libresoc.v:158426.3-158427.27" + process $proc$libresoc.v:158426$8327 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157660.3-157668.6" - process $proc$libresoc.v:157660$8396 + attribute \src "libresoc.v:158428.3-158436.6" + process $proc$libresoc.v:158428$8328 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8397 $1\q_int$next[0:0]$8398 - attribute \src "libresoc.v:157661.5-157661.29" + assign $0\q_int$next[0:0]$8329 $1\q_int$next[0:0]$8330 + attribute \src "libresoc.v:158429.5-158429.29" switch \initial - attribute \src "libresoc.v:157661.9-157661.17" + attribute \src "libresoc.v:158429.9-158429.17" case 1'1 case end @@ -328162,56 +294705,56 @@ module \opc_l$24 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8398 1'0 + assign $1\q_int$next[0:0]$8330 1'0 case - assign $1\q_int$next[0:0]$8398 \$5 + assign $1\q_int$next[0:0]$8330 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8397 + update \q_int$next $0\q_int$next[0:0]$8329 end - connect \$9 $and$libresoc.v:157650$8387_Y - connect \$11 $or$libresoc.v:157651$8388_Y - connect \$13 $not$libresoc.v:157652$8389_Y - connect \$15 $or$libresoc.v:157653$8390_Y - connect \$1 $not$libresoc.v:157654$8391_Y - connect \$3 $and$libresoc.v:157655$8392_Y - connect \$5 $or$libresoc.v:157656$8393_Y - connect \$7 $not$libresoc.v:157657$8394_Y + connect \$9 $and$libresoc.v:158418$8319_Y + connect \$11 $or$libresoc.v:158419$8320_Y + connect \$13 $not$libresoc.v:158420$8321_Y + connect \$15 $or$libresoc.v:158421$8322_Y + connect \$1 $not$libresoc.v:158422$8323_Y + connect \$3 $and$libresoc.v:158423$8324_Y + connect \$5 $or$libresoc.v:158424$8325_Y + connect \$7 $not$libresoc.v:158425$8326_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157676.1-157734.10" +attribute \src "libresoc.v:158444.1-158502.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l" attribute \generator "nMigen" module \opc_l$40 - attribute \src "libresoc.v:157677.7-157677.20" + attribute \src "libresoc.v:158445.7-158445.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157722.3-157730.6" - wire $0\q_int$next[0:0]$8411 - attribute \src "libresoc.v:157720.3-157721.27" + attribute \src "libresoc.v:158490.3-158498.6" + wire $0\q_int$next[0:0]$8343 + attribute \src "libresoc.v:158488.3-158489.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157722.3-157730.6" - wire $1\q_int$next[0:0]$8412 - attribute \src "libresoc.v:157699.7-157699.19" + attribute \src "libresoc.v:158490.3-158498.6" + wire $1\q_int$next[0:0]$8344 + attribute \src "libresoc.v:158467.7-158467.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157712.17-157712.96" - wire $and$libresoc.v:157712$8401_Y - attribute \src "libresoc.v:157717.17-157717.96" - wire $and$libresoc.v:157717$8406_Y - attribute \src "libresoc.v:157714.18-157714.93" - wire $not$libresoc.v:157714$8403_Y - attribute \src "libresoc.v:157716.17-157716.92" - wire $not$libresoc.v:157716$8405_Y - attribute \src "libresoc.v:157719.17-157719.92" - wire $not$libresoc.v:157719$8408_Y - attribute \src "libresoc.v:157713.18-157713.98" - wire $or$libresoc.v:157713$8402_Y - attribute \src "libresoc.v:157715.18-157715.99" - wire $or$libresoc.v:157715$8404_Y - attribute \src "libresoc.v:157718.17-157718.97" - wire $or$libresoc.v:157718$8407_Y + attribute \src "libresoc.v:158480.17-158480.96" + wire $and$libresoc.v:158480$8333_Y + attribute \src "libresoc.v:158485.17-158485.96" + wire $and$libresoc.v:158485$8338_Y + attribute \src "libresoc.v:158482.18-158482.93" + wire $not$libresoc.v:158482$8335_Y + attribute \src "libresoc.v:158484.17-158484.92" + wire $not$libresoc.v:158484$8337_Y + attribute \src "libresoc.v:158487.17-158487.92" + wire $not$libresoc.v:158487$8340_Y + attribute \src "libresoc.v:158481.18-158481.98" + wire $or$libresoc.v:158481$8334_Y + attribute \src "libresoc.v:158483.18-158483.99" + wire $or$libresoc.v:158483$8336_Y + attribute \src "libresoc.v:158486.17-158486.97" + wire $or$libresoc.v:158486$8339_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -328228,11 +294771,11 @@ module \opc_l$40 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:157677.7-157677.15" + attribute \src "libresoc.v:158445.7-158445.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -328249,7 +294792,7 @@ module \opc_l$40 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157712$8401 + cell $and $and$libresoc.v:158480$8333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328257,10 +294800,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157712$8401_Y + connect \Y $and$libresoc.v:158480$8333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157717$8406 + cell $and $and$libresoc.v:158485$8338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328268,34 +294811,34 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157717$8406_Y + connect \Y $and$libresoc.v:158485$8338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157714$8403 + cell $not $not$libresoc.v:158482$8335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157714$8403_Y + connect \Y $not$libresoc.v:158482$8335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157716$8405 + cell $not $not$libresoc.v:158484$8337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157716$8405_Y + connect \Y $not$libresoc.v:158484$8337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157719$8408 + cell $not $not$libresoc.v:158487$8340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157719$8408_Y + connect \Y $not$libresoc.v:158487$8340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157713$8402 + cell $or $or$libresoc.v:158481$8334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328303,10 +294846,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157713$8402_Y + connect \Y $or$libresoc.v:158481$8334_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157715$8404 + cell $or $or$libresoc.v:158483$8336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328314,10 +294857,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157715$8404_Y + connect \Y $or$libresoc.v:158483$8336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157718$8407 + cell $or $or$libresoc.v:158486$8339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328325,39 +294868,39 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157718$8407_Y + connect \Y $or$libresoc.v:158486$8339_Y end - attribute \src "libresoc.v:157677.7-157677.20" - process $proc$libresoc.v:157677$8413 + attribute \src "libresoc.v:158445.7-158445.20" + process $proc$libresoc.v:158445$8345 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157699.7-157699.19" - process $proc$libresoc.v:157699$8414 + attribute \src "libresoc.v:158467.7-158467.19" + process $proc$libresoc.v:158467$8346 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157720.3-157721.27" - process $proc$libresoc.v:157720$8409 + attribute \src "libresoc.v:158488.3-158489.27" + process $proc$libresoc.v:158488$8341 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157722.3-157730.6" - process $proc$libresoc.v:157722$8410 + attribute \src "libresoc.v:158490.3-158498.6" + process $proc$libresoc.v:158490$8342 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8411 $1\q_int$next[0:0]$8412 - attribute \src "libresoc.v:157723.5-157723.29" + assign $0\q_int$next[0:0]$8343 $1\q_int$next[0:0]$8344 + attribute \src "libresoc.v:158491.5-158491.29" switch \initial - attribute \src "libresoc.v:157723.9-157723.17" + attribute \src "libresoc.v:158491.9-158491.17" case 1'1 case end @@ -328366,56 +294909,56 @@ module \opc_l$40 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8412 1'0 + assign $1\q_int$next[0:0]$8344 1'0 case - assign $1\q_int$next[0:0]$8412 \$5 + assign $1\q_int$next[0:0]$8344 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8411 + update \q_int$next $0\q_int$next[0:0]$8343 end - connect \$9 $and$libresoc.v:157712$8401_Y - connect \$11 $or$libresoc.v:157713$8402_Y - connect \$13 $not$libresoc.v:157714$8403_Y - connect \$15 $or$libresoc.v:157715$8404_Y - connect \$1 $not$libresoc.v:157716$8405_Y - connect \$3 $and$libresoc.v:157717$8406_Y - connect \$5 $or$libresoc.v:157718$8407_Y - connect \$7 $not$libresoc.v:157719$8408_Y + connect \$9 $and$libresoc.v:158480$8333_Y + connect \$11 $or$libresoc.v:158481$8334_Y + connect \$13 $not$libresoc.v:158482$8335_Y + connect \$15 $or$libresoc.v:158483$8336_Y + connect \$1 $not$libresoc.v:158484$8337_Y + connect \$3 $and$libresoc.v:158485$8338_Y + connect \$5 $or$libresoc.v:158486$8339_Y + connect \$7 $not$libresoc.v:158487$8340_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157738.1-157796.10" +attribute \src "libresoc.v:158506.1-158564.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" attribute \generator "nMigen" module \opc_l$56 - attribute \src "libresoc.v:157739.7-157739.20" + attribute \src "libresoc.v:158507.7-158507.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157784.3-157792.6" - wire $0\q_int$next[0:0]$8425 - attribute \src "libresoc.v:157782.3-157783.27" + attribute \src "libresoc.v:158552.3-158560.6" + wire $0\q_int$next[0:0]$8357 + attribute \src "libresoc.v:158550.3-158551.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157784.3-157792.6" - wire $1\q_int$next[0:0]$8426 - attribute \src "libresoc.v:157761.7-157761.19" + attribute \src "libresoc.v:158552.3-158560.6" + wire $1\q_int$next[0:0]$8358 + attribute \src "libresoc.v:158529.7-158529.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157774.17-157774.96" - wire $and$libresoc.v:157774$8415_Y - attribute \src "libresoc.v:157779.17-157779.96" - wire $and$libresoc.v:157779$8420_Y - attribute \src "libresoc.v:157776.18-157776.93" - wire $not$libresoc.v:157776$8417_Y - attribute \src "libresoc.v:157778.17-157778.92" - wire $not$libresoc.v:157778$8419_Y - attribute \src "libresoc.v:157781.17-157781.92" - wire $not$libresoc.v:157781$8422_Y - attribute \src "libresoc.v:157775.18-157775.98" - wire $or$libresoc.v:157775$8416_Y - attribute \src "libresoc.v:157777.18-157777.99" - wire $or$libresoc.v:157777$8418_Y - attribute \src "libresoc.v:157780.17-157780.97" - wire $or$libresoc.v:157780$8421_Y + attribute \src "libresoc.v:158542.17-158542.96" + wire $and$libresoc.v:158542$8347_Y + attribute \src "libresoc.v:158547.17-158547.96" + wire $and$libresoc.v:158547$8352_Y + attribute \src "libresoc.v:158544.18-158544.93" + wire $not$libresoc.v:158544$8349_Y + attribute \src "libresoc.v:158546.17-158546.92" + wire $not$libresoc.v:158546$8351_Y + attribute \src "libresoc.v:158549.17-158549.92" + wire $not$libresoc.v:158549$8354_Y + attribute \src "libresoc.v:158543.18-158543.98" + wire $or$libresoc.v:158543$8348_Y + attribute \src "libresoc.v:158545.18-158545.99" + wire $or$libresoc.v:158545$8350_Y + attribute \src "libresoc.v:158548.17-158548.97" + wire $or$libresoc.v:158548$8353_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -328432,11 +294975,11 @@ module \opc_l$56 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:157739.7-157739.15" + attribute \src "libresoc.v:158507.7-158507.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -328453,7 +294996,7 @@ module \opc_l$56 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157774$8415 + cell $and $and$libresoc.v:158542$8347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328461,10 +295004,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157774$8415_Y + connect \Y $and$libresoc.v:158542$8347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157779$8420 + cell $and $and$libresoc.v:158547$8352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328472,34 +295015,34 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157779$8420_Y + connect \Y $and$libresoc.v:158547$8352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157776$8417 + cell $not $not$libresoc.v:158544$8349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157776$8417_Y + connect \Y $not$libresoc.v:158544$8349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157778$8419 + cell $not $not$libresoc.v:158546$8351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157778$8419_Y + connect \Y $not$libresoc.v:158546$8351_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157781$8422 + cell $not $not$libresoc.v:158549$8354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157781$8422_Y + connect \Y $not$libresoc.v:158549$8354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157775$8416 + cell $or $or$libresoc.v:158543$8348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328507,10 +295050,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157775$8416_Y + connect \Y $or$libresoc.v:158543$8348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157777$8418 + cell $or $or$libresoc.v:158545$8350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328518,10 +295061,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157777$8418_Y + connect \Y $or$libresoc.v:158545$8350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157780$8421 + cell $or $or$libresoc.v:158548$8353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328529,39 +295072,39 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157780$8421_Y + connect \Y $or$libresoc.v:158548$8353_Y end - attribute \src "libresoc.v:157739.7-157739.20" - process $proc$libresoc.v:157739$8427 + attribute \src "libresoc.v:158507.7-158507.20" + process $proc$libresoc.v:158507$8359 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157761.7-157761.19" - process $proc$libresoc.v:157761$8428 + attribute \src "libresoc.v:158529.7-158529.19" + process $proc$libresoc.v:158529$8360 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157782.3-157783.27" - process $proc$libresoc.v:157782$8423 + attribute \src "libresoc.v:158550.3-158551.27" + process $proc$libresoc.v:158550$8355 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157784.3-157792.6" - process $proc$libresoc.v:157784$8424 + attribute \src "libresoc.v:158552.3-158560.6" + process $proc$libresoc.v:158552$8356 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8425 $1\q_int$next[0:0]$8426 - attribute \src "libresoc.v:157785.5-157785.29" + assign $0\q_int$next[0:0]$8357 $1\q_int$next[0:0]$8358 + attribute \src "libresoc.v:158553.5-158553.29" switch \initial - attribute \src "libresoc.v:157785.9-157785.17" + attribute \src "libresoc.v:158553.9-158553.17" case 1'1 case end @@ -328570,56 +295113,56 @@ module \opc_l$56 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8426 1'0 + assign $1\q_int$next[0:0]$8358 1'0 case - assign $1\q_int$next[0:0]$8426 \$5 + assign $1\q_int$next[0:0]$8358 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8425 + update \q_int$next $0\q_int$next[0:0]$8357 end - connect \$9 $and$libresoc.v:157774$8415_Y - connect \$11 $or$libresoc.v:157775$8416_Y - connect \$13 $not$libresoc.v:157776$8417_Y - connect \$15 $or$libresoc.v:157777$8418_Y - connect \$1 $not$libresoc.v:157778$8419_Y - connect \$3 $and$libresoc.v:157779$8420_Y - connect \$5 $or$libresoc.v:157780$8421_Y - connect \$7 $not$libresoc.v:157781$8422_Y + connect \$9 $and$libresoc.v:158542$8347_Y + connect \$11 $or$libresoc.v:158543$8348_Y + connect \$13 $not$libresoc.v:158544$8349_Y + connect \$15 $or$libresoc.v:158545$8350_Y + connect \$1 $not$libresoc.v:158546$8351_Y + connect \$3 $and$libresoc.v:158547$8352_Y + connect \$5 $or$libresoc.v:158548$8353_Y + connect \$7 $not$libresoc.v:158549$8354_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157800.1-157858.10" +attribute \src "libresoc.v:158568.1-158626.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" attribute \generator "nMigen" module \opc_l$68 - attribute \src "libresoc.v:157801.7-157801.20" + attribute \src "libresoc.v:158569.7-158569.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157846.3-157854.6" - wire $0\q_int$next[0:0]$8439 - attribute \src "libresoc.v:157844.3-157845.27" + attribute \src "libresoc.v:158614.3-158622.6" + wire $0\q_int$next[0:0]$8371 + attribute \src "libresoc.v:158612.3-158613.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157846.3-157854.6" - wire $1\q_int$next[0:0]$8440 - attribute \src "libresoc.v:157823.7-157823.19" + attribute \src "libresoc.v:158614.3-158622.6" + wire $1\q_int$next[0:0]$8372 + attribute \src "libresoc.v:158591.7-158591.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157836.17-157836.96" - wire $and$libresoc.v:157836$8429_Y - attribute \src "libresoc.v:157841.17-157841.96" - wire $and$libresoc.v:157841$8434_Y - attribute \src "libresoc.v:157838.18-157838.93" - wire $not$libresoc.v:157838$8431_Y - attribute \src "libresoc.v:157840.17-157840.92" - wire $not$libresoc.v:157840$8433_Y - attribute \src "libresoc.v:157843.17-157843.92" - wire $not$libresoc.v:157843$8436_Y - attribute \src "libresoc.v:157837.18-157837.98" - wire $or$libresoc.v:157837$8430_Y - attribute \src "libresoc.v:157839.18-157839.99" - wire $or$libresoc.v:157839$8432_Y - attribute \src "libresoc.v:157842.17-157842.97" - wire $or$libresoc.v:157842$8435_Y + attribute \src "libresoc.v:158604.17-158604.96" + wire $and$libresoc.v:158604$8361_Y + attribute \src "libresoc.v:158609.17-158609.96" + wire $and$libresoc.v:158609$8366_Y + attribute \src "libresoc.v:158606.18-158606.93" + wire $not$libresoc.v:158606$8363_Y + attribute \src "libresoc.v:158608.17-158608.92" + wire $not$libresoc.v:158608$8365_Y + attribute \src "libresoc.v:158611.17-158611.92" + wire $not$libresoc.v:158611$8368_Y + attribute \src "libresoc.v:158605.18-158605.98" + wire $or$libresoc.v:158605$8362_Y + attribute \src "libresoc.v:158607.18-158607.99" + wire $or$libresoc.v:158607$8364_Y + attribute \src "libresoc.v:158610.17-158610.97" + wire $or$libresoc.v:158610$8367_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -328636,11 +295179,11 @@ module \opc_l$68 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:157801.7-157801.15" + attribute \src "libresoc.v:158569.7-158569.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -328657,7 +295200,7 @@ module \opc_l$68 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157836$8429 + cell $and $and$libresoc.v:158604$8361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328665,10 +295208,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157836$8429_Y + connect \Y $and$libresoc.v:158604$8361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157841$8434 + cell $and $and$libresoc.v:158609$8366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328676,34 +295219,34 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157841$8434_Y + connect \Y $and$libresoc.v:158609$8366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157838$8431 + cell $not $not$libresoc.v:158606$8363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157838$8431_Y + connect \Y $not$libresoc.v:158606$8363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157840$8433 + cell $not $not$libresoc.v:158608$8365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157840$8433_Y + connect \Y $not$libresoc.v:158608$8365_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157843$8436 + cell $not $not$libresoc.v:158611$8368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157843$8436_Y + connect \Y $not$libresoc.v:158611$8368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157837$8430 + cell $or $or$libresoc.v:158605$8362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328711,10 +295254,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157837$8430_Y + connect \Y $or$libresoc.v:158605$8362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157839$8432 + cell $or $or$libresoc.v:158607$8364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328722,10 +295265,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157839$8432_Y + connect \Y $or$libresoc.v:158607$8364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157842$8435 + cell $or $or$libresoc.v:158610$8367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328733,39 +295276,39 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157842$8435_Y + connect \Y $or$libresoc.v:158610$8367_Y end - attribute \src "libresoc.v:157801.7-157801.20" - process $proc$libresoc.v:157801$8441 + attribute \src "libresoc.v:158569.7-158569.20" + process $proc$libresoc.v:158569$8373 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157823.7-157823.19" - process $proc$libresoc.v:157823$8442 + attribute \src "libresoc.v:158591.7-158591.19" + process $proc$libresoc.v:158591$8374 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157844.3-157845.27" - process $proc$libresoc.v:157844$8437 + attribute \src "libresoc.v:158612.3-158613.27" + process $proc$libresoc.v:158612$8369 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157846.3-157854.6" - process $proc$libresoc.v:157846$8438 + attribute \src "libresoc.v:158614.3-158622.6" + process $proc$libresoc.v:158614$8370 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8439 $1\q_int$next[0:0]$8440 - attribute \src "libresoc.v:157847.5-157847.29" + assign $0\q_int$next[0:0]$8371 $1\q_int$next[0:0]$8372 + attribute \src "libresoc.v:158615.5-158615.29" switch \initial - attribute \src "libresoc.v:157847.9-157847.17" + attribute \src "libresoc.v:158615.9-158615.17" case 1'1 case end @@ -328774,56 +295317,56 @@ module \opc_l$68 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8440 1'0 + assign $1\q_int$next[0:0]$8372 1'0 case - assign $1\q_int$next[0:0]$8440 \$5 + assign $1\q_int$next[0:0]$8372 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8439 + update \q_int$next $0\q_int$next[0:0]$8371 end - connect \$9 $and$libresoc.v:157836$8429_Y - connect \$11 $or$libresoc.v:157837$8430_Y - connect \$13 $not$libresoc.v:157838$8431_Y - connect \$15 $or$libresoc.v:157839$8432_Y - connect \$1 $not$libresoc.v:157840$8433_Y - connect \$3 $and$libresoc.v:157841$8434_Y - connect \$5 $or$libresoc.v:157842$8435_Y - connect \$7 $not$libresoc.v:157843$8436_Y + connect \$9 $and$libresoc.v:158604$8361_Y + connect \$11 $or$libresoc.v:158605$8362_Y + connect \$13 $not$libresoc.v:158606$8363_Y + connect \$15 $or$libresoc.v:158607$8364_Y + connect \$1 $not$libresoc.v:158608$8365_Y + connect \$3 $and$libresoc.v:158609$8366_Y + connect \$5 $or$libresoc.v:158610$8367_Y + connect \$7 $not$libresoc.v:158611$8368_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157862.1-157920.10" +attribute \src "libresoc.v:158630.1-158688.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l" attribute \generator "nMigen" module \opc_l$85 - attribute \src "libresoc.v:157863.7-157863.20" + attribute \src "libresoc.v:158631.7-158631.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157908.3-157916.6" - wire $0\q_int$next[0:0]$8453 - attribute \src "libresoc.v:157906.3-157907.27" + attribute \src "libresoc.v:158676.3-158684.6" + wire $0\q_int$next[0:0]$8385 + attribute \src "libresoc.v:158674.3-158675.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157908.3-157916.6" - wire $1\q_int$next[0:0]$8454 - attribute \src "libresoc.v:157885.7-157885.19" + attribute \src "libresoc.v:158676.3-158684.6" + wire $1\q_int$next[0:0]$8386 + attribute \src "libresoc.v:158653.7-158653.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157898.17-157898.96" - wire $and$libresoc.v:157898$8443_Y - attribute \src "libresoc.v:157903.17-157903.96" - wire $and$libresoc.v:157903$8448_Y - attribute \src "libresoc.v:157900.18-157900.93" - wire $not$libresoc.v:157900$8445_Y - attribute \src "libresoc.v:157902.17-157902.92" - wire $not$libresoc.v:157902$8447_Y - attribute \src "libresoc.v:157905.17-157905.92" - wire $not$libresoc.v:157905$8450_Y - attribute \src "libresoc.v:157899.18-157899.98" - wire $or$libresoc.v:157899$8444_Y - attribute \src "libresoc.v:157901.18-157901.99" - wire $or$libresoc.v:157901$8446_Y - attribute \src "libresoc.v:157904.17-157904.97" - wire $or$libresoc.v:157904$8449_Y + attribute \src "libresoc.v:158666.17-158666.96" + wire $and$libresoc.v:158666$8375_Y + attribute \src "libresoc.v:158671.17-158671.96" + wire $and$libresoc.v:158671$8380_Y + attribute \src "libresoc.v:158668.18-158668.93" + wire $not$libresoc.v:158668$8377_Y + attribute \src "libresoc.v:158670.17-158670.92" + wire $not$libresoc.v:158670$8379_Y + attribute \src "libresoc.v:158673.17-158673.92" + wire $not$libresoc.v:158673$8382_Y + attribute \src "libresoc.v:158667.18-158667.98" + wire $or$libresoc.v:158667$8376_Y + attribute \src "libresoc.v:158669.18-158669.99" + wire $or$libresoc.v:158669$8378_Y + attribute \src "libresoc.v:158672.17-158672.97" + wire $or$libresoc.v:158672$8381_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -328840,11 +295383,11 @@ module \opc_l$85 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:157863.7-157863.15" + attribute \src "libresoc.v:158631.7-158631.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -328861,7 +295404,7 @@ module \opc_l$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157898$8443 + cell $and $and$libresoc.v:158666$8375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328869,10 +295412,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157898$8443_Y + connect \Y $and$libresoc.v:158666$8375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157903$8448 + cell $and $and$libresoc.v:158671$8380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328880,34 +295423,34 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157903$8448_Y + connect \Y $and$libresoc.v:158671$8380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157900$8445 + cell $not $not$libresoc.v:158668$8377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157900$8445_Y + connect \Y $not$libresoc.v:158668$8377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157902$8447 + cell $not $not$libresoc.v:158670$8379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157902$8447_Y + connect \Y $not$libresoc.v:158670$8379_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157905$8450 + cell $not $not$libresoc.v:158673$8382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157905$8450_Y + connect \Y $not$libresoc.v:158673$8382_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157899$8444 + cell $or $or$libresoc.v:158667$8376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328915,10 +295458,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157899$8444_Y + connect \Y $or$libresoc.v:158667$8376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157901$8446 + cell $or $or$libresoc.v:158669$8378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328926,10 +295469,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157901$8446_Y + connect \Y $or$libresoc.v:158669$8378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157904$8449 + cell $or $or$libresoc.v:158672$8381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328937,39 +295480,39 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157904$8449_Y + connect \Y $or$libresoc.v:158672$8381_Y end - attribute \src "libresoc.v:157863.7-157863.20" - process $proc$libresoc.v:157863$8455 + attribute \src "libresoc.v:158631.7-158631.20" + process $proc$libresoc.v:158631$8387 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157885.7-157885.19" - process $proc$libresoc.v:157885$8456 + attribute \src "libresoc.v:158653.7-158653.19" + process $proc$libresoc.v:158653$8388 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157906.3-157907.27" - process $proc$libresoc.v:157906$8451 + attribute \src "libresoc.v:158674.3-158675.27" + process $proc$libresoc.v:158674$8383 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157908.3-157916.6" - process $proc$libresoc.v:157908$8452 + attribute \src "libresoc.v:158676.3-158684.6" + process $proc$libresoc.v:158676$8384 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8453 $1\q_int$next[0:0]$8454 - attribute \src "libresoc.v:157909.5-157909.29" + assign $0\q_int$next[0:0]$8385 $1\q_int$next[0:0]$8386 + attribute \src "libresoc.v:158677.5-158677.29" switch \initial - attribute \src "libresoc.v:157909.9-157909.17" + attribute \src "libresoc.v:158677.9-158677.17" case 1'1 case end @@ -328978,97 +295521,97 @@ module \opc_l$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8454 1'0 + assign $1\q_int$next[0:0]$8386 1'0 case - assign $1\q_int$next[0:0]$8454 \$5 + assign $1\q_int$next[0:0]$8386 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8453 + update \q_int$next $0\q_int$next[0:0]$8385 end - connect \$9 $and$libresoc.v:157898$8443_Y - connect \$11 $or$libresoc.v:157899$8444_Y - connect \$13 $not$libresoc.v:157900$8445_Y - connect \$15 $or$libresoc.v:157901$8446_Y - connect \$1 $not$libresoc.v:157902$8447_Y - connect \$3 $and$libresoc.v:157903$8448_Y - connect \$5 $or$libresoc.v:157904$8449_Y - connect \$7 $not$libresoc.v:157905$8450_Y + connect \$9 $and$libresoc.v:158666$8375_Y + connect \$11 $or$libresoc.v:158667$8376_Y + connect \$13 $not$libresoc.v:158668$8377_Y + connect \$15 $or$libresoc.v:158669$8378_Y + connect \$1 $not$libresoc.v:158670$8379_Y + connect \$3 $and$libresoc.v:158671$8380_Y + connect \$5 $or$libresoc.v:158672$8381_Y + connect \$7 $not$libresoc.v:158673$8382_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157924.1-158382.10" +attribute \src "libresoc.v:158692.1-159150.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" attribute \generator "nMigen" module \output - attribute \src "libresoc.v:158301.3-158312.6" + attribute \src "libresoc.v:159069.3-159080.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:157925.7-157925.20" + attribute \src "libresoc.v:158693.7-158693.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158313.3-158324.6" - wire width 65 $0\o$28[64:0]$8475 - attribute \src "libresoc.v:158289.3-158300.6" + attribute \src "libresoc.v:159081.3-159092.6" + wire width 65 $0\o$28[64:0]$8407 + attribute \src "libresoc.v:159057.3-159068.6" wire $0\so[0:0] - attribute \src "libresoc.v:158345.3-158354.6" - wire width 2 $0\xer_ov$24[1:0]$8482 - attribute \src "libresoc.v:158355.3-158364.6" + attribute \src "libresoc.v:159113.3-159122.6" + wire width 2 $0\xer_ov$24[1:0]$8414 + attribute \src "libresoc.v:159123.3-159132.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:158325.3-158334.6" - wire $0\xer_so$25[0:0]$8478 - attribute \src "libresoc.v:158335.3-158344.6" + attribute \src "libresoc.v:159093.3-159102.6" + wire $0\xer_so$25[0:0]$8410 + attribute \src "libresoc.v:159103.3-159112.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:158301.3-158312.6" + attribute \src "libresoc.v:159069.3-159080.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:158313.3-158324.6" - wire width 65 $1\o$28[64:0]$8476 - attribute \src "libresoc.v:158289.3-158300.6" + attribute \src "libresoc.v:159081.3-159092.6" + wire width 65 $1\o$28[64:0]$8408 + attribute \src "libresoc.v:159057.3-159068.6" wire $1\so[0:0] - attribute \src "libresoc.v:158345.3-158354.6" - wire width 2 $1\xer_ov$24[1:0]$8483 - attribute \src "libresoc.v:158355.3-158364.6" + attribute \src "libresoc.v:159113.3-159122.6" + wire width 2 $1\xer_ov$24[1:0]$8415 + attribute \src "libresoc.v:159123.3-159132.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158325.3-158334.6" - wire $1\xer_so$25[0:0]$8479 - attribute \src "libresoc.v:158335.3-158344.6" + attribute \src "libresoc.v:159093.3-159102.6" + wire $1\xer_so$25[0:0]$8411 + attribute \src "libresoc.v:159103.3-159112.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158276.18-158276.128" - wire $and$libresoc.v:158276$8457_Y - attribute \src "libresoc.v:158284.18-158284.112" - wire $and$libresoc.v:158284$8467_Y - attribute \src "libresoc.v:158287.18-158287.125" - wire $and$libresoc.v:158287$8470_Y - attribute \src "libresoc.v:158280.18-158280.123" - wire $eq$libresoc.v:158280$8463_Y - attribute \src "libresoc.v:158281.18-158281.123" - wire $eq$libresoc.v:158281$8464_Y - attribute \src "libresoc.v:158278.18-158278.103" - wire width 65 $extend$libresoc.v:158278$8459_Y - attribute \src "libresoc.v:158279.18-158279.101" - wire width 65 $extend$libresoc.v:158279$8461_Y - attribute \src "libresoc.v:158277.18-158277.100" - wire width 64 $not$libresoc.v:158277$8458_Y - attribute \src "libresoc.v:158283.18-158283.107" - wire $not$libresoc.v:158283$8466_Y - attribute \src "libresoc.v:158286.18-158286.107" - wire $not$libresoc.v:158286$8469_Y - attribute \src "libresoc.v:158285.18-158285.115" - wire $or$libresoc.v:158285$8468_Y - attribute \src "libresoc.v:158288.18-158288.112" - wire $or$libresoc.v:158288$8471_Y - attribute \src "libresoc.v:158278.18-158278.103" - wire width 65 $pos$libresoc.v:158278$8460_Y - attribute \src "libresoc.v:158279.18-158279.101" - wire width 65 $pos$libresoc.v:158279$8462_Y - attribute \src "libresoc.v:158282.18-158282.105" - wire $reduce_or$libresoc.v:158282$8465_Y + attribute \src "libresoc.v:159044.18-159044.128" + wire $and$libresoc.v:159044$8389_Y + attribute \src "libresoc.v:159052.18-159052.112" + wire $and$libresoc.v:159052$8399_Y + attribute \src "libresoc.v:159055.18-159055.125" + wire $and$libresoc.v:159055$8402_Y + attribute \src "libresoc.v:159048.18-159048.123" + wire $eq$libresoc.v:159048$8395_Y + attribute \src "libresoc.v:159049.18-159049.123" + wire $eq$libresoc.v:159049$8396_Y + attribute \src "libresoc.v:159046.18-159046.103" + wire width 65 $extend$libresoc.v:159046$8391_Y + attribute \src "libresoc.v:159047.18-159047.101" + wire width 65 $extend$libresoc.v:159047$8393_Y + attribute \src "libresoc.v:159045.18-159045.100" + wire width 64 $not$libresoc.v:159045$8390_Y + attribute \src "libresoc.v:159051.18-159051.107" + wire $not$libresoc.v:159051$8398_Y + attribute \src "libresoc.v:159054.18-159054.107" + wire $not$libresoc.v:159054$8401_Y + attribute \src "libresoc.v:159053.18-159053.115" + wire $or$libresoc.v:159053$8400_Y + attribute \src "libresoc.v:159056.18-159056.112" + wire $or$libresoc.v:159056$8403_Y + attribute \src "libresoc.v:159046.18-159046.103" + wire width 65 $pos$libresoc.v:159046$8392_Y + attribute \src "libresoc.v:159047.18-159047.101" + wire width 65 $pos$libresoc.v:159047$8394_Y + attribute \src "libresoc.v:159050.18-159050.105" + wire $reduce_or$libresoc.v:159050$8397_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 64 \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 65 \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire \$35 @@ -329350,13 +295893,13 @@ module \output wire output 35 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 46 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 47 \cr_a_ok - attribute \src "libresoc.v:157925.7-157925.15" + attribute \src "libresoc.v:158693.7-158693.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -329374,15 +295917,15 @@ module \output wire width 2 input 54 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 25 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 44 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" wire width 65 \o$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 45 \o_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" wire \oe @@ -329392,26 +295935,26 @@ module \output wire \so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 48 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 49 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 23 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 50 \xer_ov$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 51 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 24 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 52 \xer_so$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 53 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:158276$8457 + cell $and $and$libresoc.v:159044$8389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329419,10 +295962,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:158276$8457_Y + connect \Y $and$libresoc.v:159044$8389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:158284$8467 + cell $and $and$libresoc.v:159052$8399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329430,10 +295973,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$41 - connect \Y $and$libresoc.v:158284$8467_Y + connect \Y $and$libresoc.v:159052$8399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:158287$8470 + cell $and $and$libresoc.v:159055$8402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329441,10 +295984,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:158287$8470_Y + connect \Y $and$libresoc.v:159055$8402_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:158280$8463 + cell $eq $eq$libresoc.v:159048$8395 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -329452,10 +295995,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:158280$8463_Y + connect \Y $eq$libresoc.v:159048$8395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:158281$8464 + cell $eq $eq$libresoc.v:159049$8396 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -329463,50 +296006,50 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:158281$8464_Y + connect \Y $eq$libresoc.v:159049$8396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:158278$8459 + cell $pos $extend$libresoc.v:159046$8391 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$30 - connect \Y $extend$libresoc.v:158278$8459_Y + connect \Y $extend$libresoc.v:159046$8391_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:158279$8461 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $extend$libresoc.v:159047$8393 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:158279$8461_Y + connect \Y $extend$libresoc.v:159047$8393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:158277$8458 + cell $not $not$libresoc.v:159045$8390 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:158277$8458_Y + connect \Y $not$libresoc.v:159045$8390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:158283$8466 + cell $not $not$libresoc.v:159051$8398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:158283$8466_Y + connect \Y $not$libresoc.v:159051$8398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:158286$8469 + cell $not $not$libresoc.v:159054$8401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:158286$8469_Y + connect \Y $not$libresoc.v:159054$8401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:158285$8468 + cell $or $or$libresoc.v:159053$8400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329514,10 +296057,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:158285$8468_Y + connect \Y $or$libresoc.v:159053$8400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:158288$8471 + cell $or $or$libresoc.v:159056$8403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329525,47 +296068,47 @@ module \output parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:158288$8471_Y + connect \Y $or$libresoc.v:159056$8403_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:158278$8460 + cell $pos $pos$libresoc.v:159046$8392 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158278$8459_Y - connect \Y $pos$libresoc.v:158278$8460_Y + connect \A $extend$libresoc.v:159046$8391_Y + connect \Y $pos$libresoc.v:159046$8392_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:158279$8462 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $pos$libresoc.v:159047$8394 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158279$8461_Y - connect \Y $pos$libresoc.v:158279$8462_Y + connect \A $extend$libresoc.v:159047$8393_Y + connect \Y $pos$libresoc.v:159047$8394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:158282$8465 + cell $reduce_or $reduce_or$libresoc.v:159050$8397 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:158282$8465_Y + connect \Y $reduce_or$libresoc.v:159050$8397_Y end - attribute \src "libresoc.v:157925.7-157925.20" - process $proc$libresoc.v:157925$8485 + attribute \src "libresoc.v:158693.7-158693.20" + process $proc$libresoc.v:158693$8417 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158289.3-158300.6" - process $proc$libresoc.v:158289$8472 + attribute \src "libresoc.v:159057.3-159068.6" + process $proc$libresoc.v:159057$8404 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:158290.5-158290.29" + attribute \src "libresoc.v:159058.5-159058.29" switch \initial - attribute \src "libresoc.v:158290.9-158290.17" + attribute \src "libresoc.v:159058.9-159058.17" case 1'1 case end @@ -329583,13 +296126,13 @@ module \output sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:158301.3-158312.6" - process $proc$libresoc.v:158301$8473 + attribute \src "libresoc.v:159069.3-159080.6" + process $proc$libresoc.v:159069$8405 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:158302.5-158302.29" + attribute \src "libresoc.v:159070.5-159070.29" switch \initial - attribute \src "libresoc.v:158302.9-158302.17" + attribute \src "libresoc.v:159070.9-159070.17" case 1'1 case end @@ -329607,13 +296150,13 @@ module \output sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:158313.3-158324.6" - process $proc$libresoc.v:158313$8474 + attribute \src "libresoc.v:159081.3-159092.6" + process $proc$libresoc.v:159081$8406 assign { } { } - assign $0\o$28[64:0]$8475 $1\o$28[64:0]$8476 - attribute \src "libresoc.v:158314.5-158314.29" + assign $0\o$28[64:0]$8407 $1\o$28[64:0]$8408 + attribute \src "libresoc.v:159082.5-159082.29" switch \initial - attribute \src "libresoc.v:158314.9-158314.17" + attribute \src "libresoc.v:159082.9-159082.17" case 1'1 case end @@ -329622,23 +296165,23 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$28[64:0]$8476 \$29 + assign $1\o$28[64:0]$8408 \$29 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$28[64:0]$8476 \$33 + assign $1\o$28[64:0]$8408 \$33 end sync always - update \o$28 $0\o$28[64:0]$8475 + update \o$28 $0\o$28[64:0]$8407 end - attribute \src "libresoc.v:158325.3-158334.6" - process $proc$libresoc.v:158325$8477 + attribute \src "libresoc.v:159093.3-159102.6" + process $proc$libresoc.v:159093$8409 assign { } { } assign { } { } - assign $0\xer_so$25[0:0]$8478 $1\xer_so$25[0:0]$8479 - attribute \src "libresoc.v:158326.5-158326.29" + assign $0\xer_so$25[0:0]$8410 $1\xer_so$25[0:0]$8411 + attribute \src "libresoc.v:159094.5-159094.29" switch \initial - attribute \src "libresoc.v:158326.9-158326.17" + attribute \src "libresoc.v:159094.9-159094.17" case 1'1 case end @@ -329647,21 +296190,21 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$25[0:0]$8479 \$52 + assign $1\xer_so$25[0:0]$8411 \$52 case - assign $1\xer_so$25[0:0]$8479 1'0 + assign $1\xer_so$25[0:0]$8411 1'0 end sync always - update \xer_so$25 $0\xer_so$25[0:0]$8478 + update \xer_so$25 $0\xer_so$25[0:0]$8410 end - attribute \src "libresoc.v:158335.3-158344.6" - process $proc$libresoc.v:158335$8480 + attribute \src "libresoc.v:159103.3-159112.6" + process $proc$libresoc.v:159103$8412 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158336.5-158336.29" + attribute \src "libresoc.v:159104.5-159104.29" switch \initial - attribute \src "libresoc.v:158336.9-158336.17" + attribute \src "libresoc.v:159104.9-159104.17" case 1'1 case end @@ -329677,14 +296220,14 @@ module \output sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:158345.3-158354.6" - process $proc$libresoc.v:158345$8481 + attribute \src "libresoc.v:159113.3-159122.6" + process $proc$libresoc.v:159113$8413 assign { } { } assign { } { } - assign $0\xer_ov$24[1:0]$8482 $1\xer_ov$24[1:0]$8483 - attribute \src "libresoc.v:158346.5-158346.29" + assign $0\xer_ov$24[1:0]$8414 $1\xer_ov$24[1:0]$8415 + attribute \src "libresoc.v:159114.5-159114.29" switch \initial - attribute \src "libresoc.v:158346.9-158346.17" + attribute \src "libresoc.v:159114.9-159114.17" case 1'1 case end @@ -329693,21 +296236,21 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$24[1:0]$8483 \xer_ov + assign $1\xer_ov$24[1:0]$8415 \xer_ov case - assign $1\xer_ov$24[1:0]$8483 2'00 + assign $1\xer_ov$24[1:0]$8415 2'00 end sync always - update \xer_ov$24 $0\xer_ov$24[1:0]$8482 + update \xer_ov$24 $0\xer_ov$24[1:0]$8414 end - attribute \src "libresoc.v:158355.3-158364.6" - process $proc$libresoc.v:158355$8484 + attribute \src "libresoc.v:159123.3-159132.6" + process $proc$libresoc.v:159123$8416 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158356.5-158356.29" + attribute \src "libresoc.v:159124.5-159124.29" switch \initial - attribute \src "libresoc.v:158356.9-158356.17" + attribute \src "libresoc.v:159124.9-159124.17" case 1'1 case end @@ -329723,19 +296266,19 @@ module \output sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$26 $and$libresoc.v:158276$8457_Y - connect \$30 $not$libresoc.v:158277$8458_Y - connect \$29 $pos$libresoc.v:158278$8460_Y - connect \$33 $pos$libresoc.v:158279$8462_Y - connect \$35 $eq$libresoc.v:158280$8463_Y - connect \$37 $eq$libresoc.v:158281$8464_Y - connect \$39 $reduce_or$libresoc.v:158282$8465_Y - connect \$41 $not$libresoc.v:158283$8466_Y - connect \$43 $and$libresoc.v:158284$8467_Y - connect \$45 $or$libresoc.v:158285$8468_Y - connect \$47 $not$libresoc.v:158286$8469_Y - connect \$50 $and$libresoc.v:158287$8470_Y - connect \$52 $or$libresoc.v:158288$8471_Y + connect \$26 $and$libresoc.v:159044$8389_Y + connect \$30 $not$libresoc.v:159045$8390_Y + connect \$29 $pos$libresoc.v:159046$8392_Y + connect \$33 $pos$libresoc.v:159047$8394_Y + connect \$35 $eq$libresoc.v:159048$8395_Y + connect \$37 $eq$libresoc.v:159049$8396_Y + connect \$39 $reduce_or$libresoc.v:159050$8397_Y + connect \$41 $not$libresoc.v:159051$8398_Y + connect \$43 $and$libresoc.v:159052$8399_Y + connect \$45 $or$libresoc.v:159053$8400_Y + connect \$47 $not$libresoc.v:159054$8401_Y + connect \$50 $and$libresoc.v:159055$8402_Y + connect \$52 $or$libresoc.v:159056$8403_Y connect \oe$49 \$50 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid @@ -329754,64 +296297,64 @@ module \output connect \target \o$28 [63:0] connect \oe \$26 end -attribute \src "libresoc.v:158386.1-158787.10" +attribute \src "libresoc.v:159154.1-159555.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" attribute \generator "nMigen" module \output$100 - attribute \src "libresoc.v:158719.3-158730.6" + attribute \src "libresoc.v:159487.3-159498.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:158387.7-158387.20" + attribute \src "libresoc.v:159155.7-159155.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158707.3-158718.6" + attribute \src "libresoc.v:159475.3-159486.6" wire $0\so[0:0] - attribute \src "libresoc.v:158751.3-158760.6" - wire width 2 $0\xer_ov$17[1:0]$8505 - attribute \src "libresoc.v:158761.3-158770.6" + attribute \src "libresoc.v:159519.3-159528.6" + wire width 2 $0\xer_ov$17[1:0]$8437 + attribute \src "libresoc.v:159529.3-159538.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:158731.3-158740.6" - wire $0\xer_so$18[0:0]$8501 - attribute \src "libresoc.v:158741.3-158750.6" + attribute \src "libresoc.v:159499.3-159508.6" + wire $0\xer_so$18[0:0]$8433 + attribute \src "libresoc.v:159509.3-159518.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:158719.3-158730.6" + attribute \src "libresoc.v:159487.3-159498.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:158707.3-158718.6" + attribute \src "libresoc.v:159475.3-159486.6" wire $1\so[0:0] - attribute \src "libresoc.v:158751.3-158760.6" - wire width 2 $1\xer_ov$17[1:0]$8506 - attribute \src "libresoc.v:158761.3-158770.6" + attribute \src "libresoc.v:159519.3-159528.6" + wire width 2 $1\xer_ov$17[1:0]$8438 + attribute \src "libresoc.v:159529.3-159538.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158731.3-158740.6" - wire $1\xer_so$18[0:0]$8502 - attribute \src "libresoc.v:158741.3-158750.6" + attribute \src "libresoc.v:159499.3-159508.6" + wire $1\xer_so$18[0:0]$8434 + attribute \src "libresoc.v:159509.3-159518.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158696.18-158696.128" - wire $and$libresoc.v:158696$8486_Y - attribute \src "libresoc.v:158702.18-158702.112" - wire $and$libresoc.v:158702$8493_Y - attribute \src "libresoc.v:158705.18-158705.125" - wire $and$libresoc.v:158705$8496_Y - attribute \src "libresoc.v:158698.18-158698.123" - wire $eq$libresoc.v:158698$8489_Y - attribute \src "libresoc.v:158699.18-158699.123" - wire $eq$libresoc.v:158699$8490_Y - attribute \src "libresoc.v:158697.18-158697.101" - wire width 65 $extend$libresoc.v:158697$8487_Y - attribute \src "libresoc.v:158701.18-158701.107" - wire $not$libresoc.v:158701$8492_Y - attribute \src "libresoc.v:158704.18-158704.107" - wire $not$libresoc.v:158704$8495_Y - attribute \src "libresoc.v:158703.18-158703.115" - wire $or$libresoc.v:158703$8494_Y - attribute \src "libresoc.v:158706.18-158706.112" - wire $or$libresoc.v:158706$8497_Y - attribute \src "libresoc.v:158697.18-158697.101" - wire width 65 $pos$libresoc.v:158697$8488_Y - attribute \src "libresoc.v:158700.18-158700.105" - wire $reduce_or$libresoc.v:158700$8491_Y + attribute \src "libresoc.v:159464.18-159464.128" + wire $and$libresoc.v:159464$8418_Y + attribute \src "libresoc.v:159470.18-159470.112" + wire $and$libresoc.v:159470$8425_Y + attribute \src "libresoc.v:159473.18-159473.125" + wire $and$libresoc.v:159473$8428_Y + attribute \src "libresoc.v:159466.18-159466.123" + wire $eq$libresoc.v:159466$8421_Y + attribute \src "libresoc.v:159467.18-159467.123" + wire $eq$libresoc.v:159467$8422_Y + attribute \src "libresoc.v:159465.18-159465.101" + wire width 65 $extend$libresoc.v:159465$8419_Y + attribute \src "libresoc.v:159469.18-159469.107" + wire $not$libresoc.v:159469$8424_Y + attribute \src "libresoc.v:159472.18-159472.107" + wire $not$libresoc.v:159472$8427_Y + attribute \src "libresoc.v:159471.18-159471.115" + wire $or$libresoc.v:159471$8426_Y + attribute \src "libresoc.v:159474.18-159474.112" + wire $or$libresoc.v:159474$8429_Y + attribute \src "libresoc.v:159465.18-159465.101" + wire width 65 $pos$libresoc.v:159465$8420_Y + attribute \src "libresoc.v:159468.18-159468.105" + wire $reduce_or$libresoc.v:159468$8423_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 65 \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire \$24 @@ -329833,13 +296376,13 @@ module \output$100 wire \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 15 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 33 \cr_a$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 34 \cr_a_ok - attribute \src "libresoc.v:158387.7-158387.15" + attribute \src "libresoc.v:159155.7-159155.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -330085,15 +296628,15 @@ module \output$100 wire width 2 input 39 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 18 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 13 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 31 \o$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" wire width 65 \o$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 14 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 32 \o_ok$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" wire \oe @@ -330103,20 +296646,20 @@ module \output$100 wire \so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 16 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 35 \xer_ov$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 36 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 17 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 37 \xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 38 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:158696$8486 + cell $and $and$libresoc.v:159464$8418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330124,10 +296667,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:158696$8486_Y + connect \Y $and$libresoc.v:159464$8418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:158702$8493 + cell $and $and$libresoc.v:159470$8425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330135,10 +296678,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$30 - connect \Y $and$libresoc.v:158702$8493_Y + connect \Y $and$libresoc.v:159470$8425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:158705$8496 + cell $and $and$libresoc.v:159473$8428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330146,10 +296689,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:158705$8496_Y + connect \Y $and$libresoc.v:159473$8428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:158698$8489 + cell $eq $eq$libresoc.v:159466$8421 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -330157,10 +296700,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:158698$8489_Y + connect \Y $eq$libresoc.v:159466$8421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:158699$8490 + cell $eq $eq$libresoc.v:159467$8422 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -330168,34 +296711,34 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:158699$8490_Y + connect \Y $eq$libresoc.v:159467$8422_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:158697$8487 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $extend$libresoc.v:159465$8419 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:158697$8487_Y + connect \Y $extend$libresoc.v:159465$8419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:158701$8492 + cell $not $not$libresoc.v:159469$8424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:158701$8492_Y + connect \Y $not$libresoc.v:159469$8424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:158704$8495 + cell $not $not$libresoc.v:159472$8427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:158704$8495_Y + connect \Y $not$libresoc.v:159472$8427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:158703$8494 + cell $or $or$libresoc.v:159471$8426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330203,10 +296746,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:158703$8494_Y + connect \Y $or$libresoc.v:159471$8426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:158706$8497 + cell $or $or$libresoc.v:159474$8429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330214,39 +296757,39 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:158706$8497_Y + connect \Y $or$libresoc.v:159474$8429_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:158697$8488 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $pos$libresoc.v:159465$8420 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158697$8487_Y - connect \Y $pos$libresoc.v:158697$8488_Y + connect \A $extend$libresoc.v:159465$8419_Y + connect \Y $pos$libresoc.v:159465$8420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:158700$8491 + cell $reduce_or $reduce_or$libresoc.v:159468$8423 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:158700$8491_Y + connect \Y $reduce_or$libresoc.v:159468$8423_Y end - attribute \src "libresoc.v:158387.7-158387.20" - process $proc$libresoc.v:158387$8508 + attribute \src "libresoc.v:159155.7-159155.20" + process $proc$libresoc.v:159155$8440 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158707.3-158718.6" - process $proc$libresoc.v:158707$8498 + attribute \src "libresoc.v:159475.3-159486.6" + process $proc$libresoc.v:159475$8430 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:158708.5-158708.29" + attribute \src "libresoc.v:159476.5-159476.29" switch \initial - attribute \src "libresoc.v:158708.9-158708.17" + attribute \src "libresoc.v:159476.9-159476.17" case 1'1 case end @@ -330264,13 +296807,13 @@ module \output$100 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:158719.3-158730.6" - process $proc$libresoc.v:158719$8499 + attribute \src "libresoc.v:159487.3-159498.6" + process $proc$libresoc.v:159487$8431 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:158720.5-158720.29" + attribute \src "libresoc.v:159488.5-159488.29" switch \initial - attribute \src "libresoc.v:158720.9-158720.17" + attribute \src "libresoc.v:159488.9-159488.17" case 1'1 case end @@ -330288,14 +296831,14 @@ module \output$100 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:158731.3-158740.6" - process $proc$libresoc.v:158731$8500 + attribute \src "libresoc.v:159499.3-159508.6" + process $proc$libresoc.v:159499$8432 assign { } { } assign { } { } - assign $0\xer_so$18[0:0]$8501 $1\xer_so$18[0:0]$8502 - attribute \src "libresoc.v:158732.5-158732.29" + assign $0\xer_so$18[0:0]$8433 $1\xer_so$18[0:0]$8434 + attribute \src "libresoc.v:159500.5-159500.29" switch \initial - attribute \src "libresoc.v:158732.9-158732.17" + attribute \src "libresoc.v:159500.9-159500.17" case 1'1 case end @@ -330304,21 +296847,21 @@ module \output$100 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$18[0:0]$8502 \$41 + assign $1\xer_so$18[0:0]$8434 \$41 case - assign $1\xer_so$18[0:0]$8502 1'0 + assign $1\xer_so$18[0:0]$8434 1'0 end sync always - update \xer_so$18 $0\xer_so$18[0:0]$8501 + update \xer_so$18 $0\xer_so$18[0:0]$8433 end - attribute \src "libresoc.v:158741.3-158750.6" - process $proc$libresoc.v:158741$8503 + attribute \src "libresoc.v:159509.3-159518.6" + process $proc$libresoc.v:159509$8435 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158742.5-158742.29" + attribute \src "libresoc.v:159510.5-159510.29" switch \initial - attribute \src "libresoc.v:158742.9-158742.17" + attribute \src "libresoc.v:159510.9-159510.17" case 1'1 case end @@ -330334,14 +296877,14 @@ module \output$100 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:158751.3-158760.6" - process $proc$libresoc.v:158751$8504 + attribute \src "libresoc.v:159519.3-159528.6" + process $proc$libresoc.v:159519$8436 assign { } { } assign { } { } - assign $0\xer_ov$17[1:0]$8505 $1\xer_ov$17[1:0]$8506 - attribute \src "libresoc.v:158752.5-158752.29" + assign $0\xer_ov$17[1:0]$8437 $1\xer_ov$17[1:0]$8438 + attribute \src "libresoc.v:159520.5-159520.29" switch \initial - attribute \src "libresoc.v:158752.9-158752.17" + attribute \src "libresoc.v:159520.9-159520.17" case 1'1 case end @@ -330350,21 +296893,21 @@ module \output$100 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$17[1:0]$8506 \xer_ov + assign $1\xer_ov$17[1:0]$8438 \xer_ov case - assign $1\xer_ov$17[1:0]$8506 2'00 + assign $1\xer_ov$17[1:0]$8438 2'00 end sync always - update \xer_ov$17 $0\xer_ov$17[1:0]$8505 + update \xer_ov$17 $0\xer_ov$17[1:0]$8437 end - attribute \src "libresoc.v:158761.3-158770.6" - process $proc$libresoc.v:158761$8507 + attribute \src "libresoc.v:159529.3-159538.6" + process $proc$libresoc.v:159529$8439 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158762.5-158762.29" + attribute \src "libresoc.v:159530.5-159530.29" switch \initial - attribute \src "libresoc.v:158762.9-158762.17" + attribute \src "libresoc.v:159530.9-159530.17" case 1'1 case end @@ -330380,17 +296923,17 @@ module \output$100 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$19 $and$libresoc.v:158696$8486_Y - connect \$22 $pos$libresoc.v:158697$8488_Y - connect \$24 $eq$libresoc.v:158698$8489_Y - connect \$26 $eq$libresoc.v:158699$8490_Y - connect \$28 $reduce_or$libresoc.v:158700$8491_Y - connect \$30 $not$libresoc.v:158701$8492_Y - connect \$32 $and$libresoc.v:158702$8493_Y - connect \$34 $or$libresoc.v:158703$8494_Y - connect \$36 $not$libresoc.v:158704$8495_Y - connect \$39 $and$libresoc.v:158705$8496_Y - connect \$41 $or$libresoc.v:158706$8497_Y + connect \$19 $and$libresoc.v:159464$8418_Y + connect \$22 $pos$libresoc.v:159465$8420_Y + connect \$24 $eq$libresoc.v:159466$8421_Y + connect \$26 $eq$libresoc.v:159467$8422_Y + connect \$28 $reduce_or$libresoc.v:159468$8423_Y + connect \$30 $not$libresoc.v:159469$8424_Y + connect \$32 $and$libresoc.v:159470$8425_Y + connect \$34 $or$libresoc.v:159471$8426_Y + connect \$36 $not$libresoc.v:159472$8427_Y + connect \$39 $and$libresoc.v:159473$8428_Y + connect \$41 $or$libresoc.v:159474$8429_Y connect \oe$38 \$39 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -330408,36 +296951,36 @@ module \output$100 connect \o$21 \$22 connect \oe \$19 end -attribute \src "libresoc.v:158791.1-159145.10" +attribute \src "libresoc.v:159559.1-159913.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" attribute \generator "nMigen" module \output$118 - attribute \src "libresoc.v:159117.3-159128.6" + attribute \src "libresoc.v:159885.3-159896.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:158792.7-158792.20" + attribute \src "libresoc.v:159560.7-159560.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159117.3-159128.6" + attribute \src "libresoc.v:159885.3-159896.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:159114.18-159114.112" - wire $and$libresoc.v:159114$8515_Y - attribute \src "libresoc.v:159110.18-159110.122" - wire $eq$libresoc.v:159110$8511_Y - attribute \src "libresoc.v:159111.18-159111.122" - wire $eq$libresoc.v:159111$8512_Y - attribute \src "libresoc.v:159109.18-159109.101" - wire width 65 $extend$libresoc.v:159109$8509_Y - attribute \src "libresoc.v:159113.18-159113.107" - wire $not$libresoc.v:159113$8514_Y - attribute \src "libresoc.v:159116.18-159116.107" - wire $not$libresoc.v:159116$8517_Y - attribute \src "libresoc.v:159115.18-159115.115" - wire $or$libresoc.v:159115$8516_Y - attribute \src "libresoc.v:159109.18-159109.101" - wire width 65 $pos$libresoc.v:159109$8510_Y - attribute \src "libresoc.v:159112.18-159112.105" - wire $reduce_or$libresoc.v:159112$8513_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "libresoc.v:159882.18-159882.112" + wire $and$libresoc.v:159882$8447_Y + attribute \src "libresoc.v:159878.18-159878.122" + wire $eq$libresoc.v:159878$8443_Y + attribute \src "libresoc.v:159879.18-159879.122" + wire $eq$libresoc.v:159879$8444_Y + attribute \src "libresoc.v:159877.18-159877.101" + wire width 65 $extend$libresoc.v:159877$8441_Y + attribute \src "libresoc.v:159881.18-159881.107" + wire $not$libresoc.v:159881$8446_Y + attribute \src "libresoc.v:159884.18-159884.107" + wire $not$libresoc.v:159884$8449_Y + attribute \src "libresoc.v:159883.18-159883.115" + wire $or$libresoc.v:159883$8448_Y + attribute \src "libresoc.v:159877.18-159877.101" + wire width 65 $pos$libresoc.v:159877$8442_Y + attribute \src "libresoc.v:159880.18-159880.105" + wire $reduce_or$libresoc.v:159880$8445_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire \$26 @@ -330455,13 +296998,13 @@ module \output$118 wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 20 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 43 \cr_a$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 44 \cr_a_ok - attribute \src "libresoc.v:158792.7-158792.15" + attribute \src "libresoc.v:159560.7-159560.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -330479,15 +297022,15 @@ module \output$118 wire width 2 input 47 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 18 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 41 \o$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" wire width 65 \o$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 19 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 42 \o_ok$20 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -330747,16 +297290,16 @@ module \output$118 wire output 32 \sr_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 45 \xer_ca$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 46 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:159114$8515 + cell $and $and$libresoc.v:159882$8447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330764,10 +297307,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$32 - connect \Y $and$libresoc.v:159114$8515_Y + connect \Y $and$libresoc.v:159882$8447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:159110$8511 + cell $eq $eq$libresoc.v:159878$8443 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -330775,10 +297318,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:159110$8511_Y + connect \Y $eq$libresoc.v:159878$8443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:159111$8512 + cell $eq $eq$libresoc.v:159879$8444 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -330786,34 +297329,34 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:159111$8512_Y + connect \Y $eq$libresoc.v:159879$8444_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:159109$8509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $extend$libresoc.v:159877$8441 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:159109$8509_Y + connect \Y $extend$libresoc.v:159877$8441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:159113$8514 + cell $not $not$libresoc.v:159881$8446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:159113$8514_Y + connect \Y $not$libresoc.v:159881$8446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:159116$8517 + cell $not $not$libresoc.v:159884$8449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:159116$8517_Y + connect \Y $not$libresoc.v:159884$8449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:159115$8516 + cell $or $or$libresoc.v:159883$8448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330821,39 +297364,39 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:159115$8516_Y + connect \Y $or$libresoc.v:159883$8448_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:159109$8510 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $pos$libresoc.v:159877$8442 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159109$8509_Y - connect \Y $pos$libresoc.v:159109$8510_Y + connect \A $extend$libresoc.v:159877$8441_Y + connect \Y $pos$libresoc.v:159877$8442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:159112$8513 + cell $reduce_or $reduce_or$libresoc.v:159880$8445 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:159112$8513_Y + connect \Y $reduce_or$libresoc.v:159880$8445_Y end - attribute \src "libresoc.v:158792.7-158792.20" - process $proc$libresoc.v:158792$8519 + attribute \src "libresoc.v:159560.7-159560.20" + process $proc$libresoc.v:159560$8451 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159117.3-159128.6" - process $proc$libresoc.v:159117$8518 + attribute \src "libresoc.v:159885.3-159896.6" + process $proc$libresoc.v:159885$8450 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:159118.5-159118.29" + attribute \src "libresoc.v:159886.5-159886.29" switch \initial - attribute \src "libresoc.v:159118.9-159118.17" + attribute \src "libresoc.v:159886.9-159886.17" case 1'1 case end @@ -330871,14 +297414,14 @@ module \output$118 sync always update \cr0 $0\cr0[3:0] end - connect \$24 $pos$libresoc.v:159109$8510_Y - connect \$26 $eq$libresoc.v:159110$8511_Y - connect \$28 $eq$libresoc.v:159111$8512_Y - connect \$30 $reduce_or$libresoc.v:159112$8513_Y - connect \$32 $not$libresoc.v:159113$8514_Y - connect \$34 $and$libresoc.v:159114$8515_Y - connect \$36 $or$libresoc.v:159115$8516_Y - connect \$38 $not$libresoc.v:159116$8517_Y + connect \$24 $pos$libresoc.v:159877$8442_Y + connect \$26 $eq$libresoc.v:159878$8443_Y + connect \$28 $eq$libresoc.v:159879$8444_Y + connect \$30 $reduce_or$libresoc.v:159880$8445_Y + connect \$32 $not$libresoc.v:159881$8446_Y + connect \$34 $and$libresoc.v:159882$8447_Y + connect \$36 $or$libresoc.v:159883$8448_Y + connect \$38 $not$libresoc.v:159884$8449_Y connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \sr_op__write_cr0 @@ -330896,50 +297439,50 @@ module \output$118 connect \target \o$23 [63:0] connect \o$23 \$24 end -attribute \src "libresoc.v:159149.1-159516.10" +attribute \src "libresoc.v:159917.1-160284.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" attribute \generator "nMigen" module \output$54 - attribute \src "libresoc.v:159491.3-159502.6" + attribute \src "libresoc.v:160259.3-160270.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:159150.7-159150.20" + attribute \src "libresoc.v:159918.7-159918.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159479.3-159490.6" - wire width 65 $0\o$23[64:0]$8533 - attribute \src "libresoc.v:159491.3-159502.6" + attribute \src "libresoc.v:160247.3-160258.6" + wire width 65 $0\o$23[64:0]$8465 + attribute \src "libresoc.v:160259.3-160270.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:159479.3-159490.6" - wire width 65 $1\o$23[64:0]$8534 - attribute \src "libresoc.v:159476.18-159476.112" - wire $and$libresoc.v:159476$8529_Y - attribute \src "libresoc.v:159472.18-159472.127" - wire $eq$libresoc.v:159472$8525_Y - attribute \src "libresoc.v:159473.18-159473.127" - wire $eq$libresoc.v:159473$8526_Y - attribute \src "libresoc.v:159470.18-159470.103" - wire width 65 $extend$libresoc.v:159470$8521_Y - attribute \src "libresoc.v:159471.18-159471.101" - wire width 65 $extend$libresoc.v:159471$8523_Y - attribute \src "libresoc.v:159469.18-159469.100" - wire width 64 $not$libresoc.v:159469$8520_Y - attribute \src "libresoc.v:159475.18-159475.107" - wire $not$libresoc.v:159475$8528_Y - attribute \src "libresoc.v:159478.18-159478.107" - wire $not$libresoc.v:159478$8531_Y - attribute \src "libresoc.v:159477.18-159477.115" - wire $or$libresoc.v:159477$8530_Y - attribute \src "libresoc.v:159470.18-159470.103" - wire width 65 $pos$libresoc.v:159470$8522_Y - attribute \src "libresoc.v:159471.18-159471.101" - wire width 65 $pos$libresoc.v:159471$8524_Y - attribute \src "libresoc.v:159474.18-159474.105" - wire $reduce_or$libresoc.v:159474$8527_Y + attribute \src "libresoc.v:160247.3-160258.6" + wire width 65 $1\o$23[64:0]$8466 + attribute \src "libresoc.v:160244.18-160244.112" + wire $and$libresoc.v:160244$8461_Y + attribute \src "libresoc.v:160240.18-160240.127" + wire $eq$libresoc.v:160240$8457_Y + attribute \src "libresoc.v:160241.18-160241.127" + wire $eq$libresoc.v:160241$8458_Y + attribute \src "libresoc.v:160238.18-160238.103" + wire width 65 $extend$libresoc.v:160238$8453_Y + attribute \src "libresoc.v:160239.18-160239.101" + wire width 65 $extend$libresoc.v:160239$8455_Y + attribute \src "libresoc.v:160237.18-160237.100" + wire width 64 $not$libresoc.v:160237$8452_Y + attribute \src "libresoc.v:160243.18-160243.107" + wire $not$libresoc.v:160243$8460_Y + attribute \src "libresoc.v:160246.18-160246.107" + wire $not$libresoc.v:160246$8463_Y + attribute \src "libresoc.v:160245.18-160245.115" + wire $or$libresoc.v:160245$8462_Y + attribute \src "libresoc.v:160238.18-160238.103" + wire width 65 $pos$libresoc.v:160238$8454_Y + attribute \src "libresoc.v:160239.18-160239.101" + wire width 65 $pos$libresoc.v:160239$8456_Y + attribute \src "libresoc.v:160242.18-160242.105" + wire $reduce_or$libresoc.v:160242$8459_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 64 \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 65 \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire \$30 @@ -330957,13 +297500,13 @@ module \output$54 wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 44 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 45 \cr_a_ok - attribute \src "libresoc.v:159150.7-159150.15" + attribute \src "libresoc.v:159918.7-159918.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -331241,22 +297784,22 @@ module \output$54 wire width 2 input 46 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 42 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" wire width 65 \o$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 43 \o_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 22 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:159476$8529 + cell $and $and$libresoc.v:160244$8461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331264,10 +297807,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$36 - connect \Y $and$libresoc.v:159476$8529_Y + connect \Y $and$libresoc.v:160244$8461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:159472$8525 + cell $eq $eq$libresoc.v:160240$8457 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -331275,10 +297818,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:159472$8525_Y + connect \Y $eq$libresoc.v:160240$8457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:159473$8526 + cell $eq $eq$libresoc.v:160241$8458 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -331286,50 +297829,50 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:159473$8526_Y + connect \Y $eq$libresoc.v:160241$8458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:159470$8521 + cell $pos $extend$libresoc.v:160238$8453 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$25 - connect \Y $extend$libresoc.v:159470$8521_Y + connect \Y $extend$libresoc.v:160238$8453_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:159471$8523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $extend$libresoc.v:160239$8455 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:159471$8523_Y + connect \Y $extend$libresoc.v:160239$8455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:159469$8520 + cell $not $not$libresoc.v:160237$8452 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:159469$8520_Y + connect \Y $not$libresoc.v:160237$8452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:159475$8528 + cell $not $not$libresoc.v:160243$8460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:159475$8528_Y + connect \Y $not$libresoc.v:160243$8460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:159478$8531 + cell $not $not$libresoc.v:160246$8463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:159478$8531_Y + connect \Y $not$libresoc.v:160246$8463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:159477$8530 + cell $or $or$libresoc.v:160245$8462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331337,47 +297880,47 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:159477$8530_Y + connect \Y $or$libresoc.v:160245$8462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:159470$8522 + cell $pos $pos$libresoc.v:160238$8454 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159470$8521_Y - connect \Y $pos$libresoc.v:159470$8522_Y + connect \A $extend$libresoc.v:160238$8453_Y + connect \Y $pos$libresoc.v:160238$8454_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:159471$8524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $pos$libresoc.v:160239$8456 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159471$8523_Y - connect \Y $pos$libresoc.v:159471$8524_Y + connect \A $extend$libresoc.v:160239$8455_Y + connect \Y $pos$libresoc.v:160239$8456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:159474$8527 + cell $reduce_or $reduce_or$libresoc.v:160242$8459 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:159474$8527_Y + connect \Y $reduce_or$libresoc.v:160242$8459_Y end - attribute \src "libresoc.v:159150.7-159150.20" - process $proc$libresoc.v:159150$8536 + attribute \src "libresoc.v:159918.7-159918.20" + process $proc$libresoc.v:159918$8468 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159479.3-159490.6" - process $proc$libresoc.v:159479$8532 + attribute \src "libresoc.v:160247.3-160258.6" + process $proc$libresoc.v:160247$8464 assign { } { } - assign $0\o$23[64:0]$8533 $1\o$23[64:0]$8534 - attribute \src "libresoc.v:159480.5-159480.29" + assign $0\o$23[64:0]$8465 $1\o$23[64:0]$8466 + attribute \src "libresoc.v:160248.5-160248.29" switch \initial - attribute \src "libresoc.v:159480.9-159480.17" + attribute \src "libresoc.v:160248.9-160248.17" case 1'1 case end @@ -331386,22 +297929,22 @@ module \output$54 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$23[64:0]$8534 \$24 + assign $1\o$23[64:0]$8466 \$24 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$23[64:0]$8534 \$28 + assign $1\o$23[64:0]$8466 \$28 end sync always - update \o$23 $0\o$23[64:0]$8533 + update \o$23 $0\o$23[64:0]$8465 end - attribute \src "libresoc.v:159491.3-159502.6" - process $proc$libresoc.v:159491$8535 + attribute \src "libresoc.v:160259.3-160270.6" + process $proc$libresoc.v:160259$8467 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:159492.5-159492.29" + attribute \src "libresoc.v:160260.5-160260.29" switch \initial - attribute \src "libresoc.v:159492.9-159492.17" + attribute \src "libresoc.v:160260.9-160260.17" case 1'1 case end @@ -331419,16 +297962,16 @@ module \output$54 sync always update \cr0 $0\cr0[3:0] end - connect \$25 $not$libresoc.v:159469$8520_Y - connect \$24 $pos$libresoc.v:159470$8522_Y - connect \$28 $pos$libresoc.v:159471$8524_Y - connect \$30 $eq$libresoc.v:159472$8525_Y - connect \$32 $eq$libresoc.v:159473$8526_Y - connect \$34 $reduce_or$libresoc.v:159474$8527_Y - connect \$36 $not$libresoc.v:159475$8528_Y - connect \$38 $and$libresoc.v:159476$8529_Y - connect \$40 $or$libresoc.v:159477$8530_Y - connect \$42 $not$libresoc.v:159478$8531_Y + connect \$25 $not$libresoc.v:160237$8452_Y + connect \$24 $pos$libresoc.v:160238$8454_Y + connect \$28 $pos$libresoc.v:160239$8456_Y + connect \$30 $eq$libresoc.v:160240$8457_Y + connect \$32 $eq$libresoc.v:160241$8458_Y + connect \$34 $reduce_or$libresoc.v:160242$8459_Y + connect \$36 $not$libresoc.v:160243$8460_Y + connect \$38 $and$libresoc.v:160244$8461_Y + connect \$40 $or$libresoc.v:160245$8462_Y + connect \$42 $not$libresoc.v:160246$8463_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \logical_op__write_cr0 @@ -331443,78 +297986,78 @@ module \output$54 connect \is_cmp \$30 connect \target \o$23 [63:0] end -attribute \src "libresoc.v:159520.1-159970.10" +attribute \src "libresoc.v:160288.1-160738.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output" attribute \generator "nMigen" module \output$83 - attribute \src "libresoc.v:159891.3-159902.6" + attribute \src "libresoc.v:160659.3-160670.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:159521.7-159521.20" + attribute \src "libresoc.v:160289.7-160289.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159903.3-159914.6" - wire width 65 $0\o$27[64:0]$8555 - attribute \src "libresoc.v:159879.3-159890.6" + attribute \src "libresoc.v:160671.3-160682.6" + wire width 65 $0\o$27[64:0]$8487 + attribute \src "libresoc.v:160647.3-160658.6" wire $0\so[0:0] - attribute \src "libresoc.v:159935.3-159944.6" - wire width 2 $0\xer_ov$23[1:0]$8562 - attribute \src "libresoc.v:159945.3-159954.6" + attribute \src "libresoc.v:160703.3-160712.6" + wire width 2 $0\xer_ov$23[1:0]$8494 + attribute \src "libresoc.v:160713.3-160722.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:159915.3-159924.6" - wire $0\xer_so$24[0:0]$8558 - attribute \src "libresoc.v:159925.3-159934.6" + attribute \src "libresoc.v:160683.3-160692.6" + wire $0\xer_so$24[0:0]$8490 + attribute \src "libresoc.v:160693.3-160702.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:159891.3-159902.6" + attribute \src "libresoc.v:160659.3-160670.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:159903.3-159914.6" - wire width 65 $1\o$27[64:0]$8556 - attribute \src "libresoc.v:159879.3-159890.6" + attribute \src "libresoc.v:160671.3-160682.6" + wire width 65 $1\o$27[64:0]$8488 + attribute \src "libresoc.v:160647.3-160658.6" wire $1\so[0:0] - attribute \src "libresoc.v:159935.3-159944.6" - wire width 2 $1\xer_ov$23[1:0]$8563 - attribute \src "libresoc.v:159945.3-159954.6" + attribute \src "libresoc.v:160703.3-160712.6" + wire width 2 $1\xer_ov$23[1:0]$8495 + attribute \src "libresoc.v:160713.3-160722.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:159915.3-159924.6" - wire $1\xer_so$24[0:0]$8559 - attribute \src "libresoc.v:159925.3-159934.6" + attribute \src "libresoc.v:160683.3-160692.6" + wire $1\xer_so$24[0:0]$8491 + attribute \src "libresoc.v:160693.3-160702.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:159866.18-159866.136" - wire $and$libresoc.v:159866$8537_Y - attribute \src "libresoc.v:159874.18-159874.112" - wire $and$libresoc.v:159874$8547_Y - attribute \src "libresoc.v:159877.18-159877.133" - wire $and$libresoc.v:159877$8550_Y - attribute \src "libresoc.v:159870.18-159870.127" - wire $eq$libresoc.v:159870$8543_Y - attribute \src "libresoc.v:159871.18-159871.127" - wire $eq$libresoc.v:159871$8544_Y - attribute \src "libresoc.v:159868.18-159868.103" - wire width 65 $extend$libresoc.v:159868$8539_Y - attribute \src "libresoc.v:159869.18-159869.101" - wire width 65 $extend$libresoc.v:159869$8541_Y - attribute \src "libresoc.v:159867.18-159867.100" - wire width 64 $not$libresoc.v:159867$8538_Y - attribute \src "libresoc.v:159873.18-159873.107" - wire $not$libresoc.v:159873$8546_Y - attribute \src "libresoc.v:159876.18-159876.107" - wire $not$libresoc.v:159876$8549_Y - attribute \src "libresoc.v:159875.18-159875.115" - wire $or$libresoc.v:159875$8548_Y - attribute \src "libresoc.v:159878.18-159878.112" - wire $or$libresoc.v:159878$8551_Y - attribute \src "libresoc.v:159868.18-159868.103" - wire width 65 $pos$libresoc.v:159868$8540_Y - attribute \src "libresoc.v:159869.18-159869.101" - wire width 65 $pos$libresoc.v:159869$8542_Y - attribute \src "libresoc.v:159872.18-159872.105" - wire $reduce_or$libresoc.v:159872$8545_Y + attribute \src "libresoc.v:160634.18-160634.136" + wire $and$libresoc.v:160634$8469_Y + attribute \src "libresoc.v:160642.18-160642.112" + wire $and$libresoc.v:160642$8479_Y + attribute \src "libresoc.v:160645.18-160645.133" + wire $and$libresoc.v:160645$8482_Y + attribute \src "libresoc.v:160638.18-160638.127" + wire $eq$libresoc.v:160638$8475_Y + attribute \src "libresoc.v:160639.18-160639.127" + wire $eq$libresoc.v:160639$8476_Y + attribute \src "libresoc.v:160636.18-160636.103" + wire width 65 $extend$libresoc.v:160636$8471_Y + attribute \src "libresoc.v:160637.18-160637.101" + wire width 65 $extend$libresoc.v:160637$8473_Y + attribute \src "libresoc.v:160635.18-160635.100" + wire width 64 $not$libresoc.v:160635$8470_Y + attribute \src "libresoc.v:160641.18-160641.107" + wire $not$libresoc.v:160641$8478_Y + attribute \src "libresoc.v:160644.18-160644.107" + wire $not$libresoc.v:160644$8481_Y + attribute \src "libresoc.v:160643.18-160643.115" + wire $or$libresoc.v:160643$8480_Y + attribute \src "libresoc.v:160646.18-160646.112" + wire $or$libresoc.v:160646$8483_Y + attribute \src "libresoc.v:160636.18-160636.103" + wire width 65 $pos$libresoc.v:160636$8472_Y + attribute \src "libresoc.v:160637.18-160637.101" + wire width 65 $pos$libresoc.v:160637$8474_Y + attribute \src "libresoc.v:160640.18-160640.105" + wire $reduce_or$libresoc.v:160640$8477_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 64 \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 65 \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire \$34 @@ -331536,13 +298079,13 @@ module \output$83 wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 45 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 46 \cr_a_ok - attribute \src "libresoc.v:159521.7-159521.15" + attribute \src "libresoc.v:160289.7-160289.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -331820,15 +298363,15 @@ module \output$83 wire width 2 input 51 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 24 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 43 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" wire width 65 \o$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 44 \o_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" wire \oe @@ -331838,20 +298381,20 @@ module \output$83 wire \so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 22 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 47 \xer_ov$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 48 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 23 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 49 \xer_so$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 50 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:159866$8537 + cell $and $and$libresoc.v:160634$8469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331859,10 +298402,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:159866$8537_Y + connect \Y $and$libresoc.v:160634$8469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:159874$8547 + cell $and $and$libresoc.v:160642$8479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331870,10 +298413,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$40 - connect \Y $and$libresoc.v:159874$8547_Y + connect \Y $and$libresoc.v:160642$8479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:159877$8550 + cell $and $and$libresoc.v:160645$8482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331881,10 +298424,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:159877$8550_Y + connect \Y $and$libresoc.v:160645$8482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:159870$8543 + cell $eq $eq$libresoc.v:160638$8475 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -331892,10 +298435,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:159870$8543_Y + connect \Y $eq$libresoc.v:160638$8475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:159871$8544 + cell $eq $eq$libresoc.v:160639$8476 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -331903,50 +298446,50 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:159871$8544_Y + connect \Y $eq$libresoc.v:160639$8476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:159868$8539 + cell $pos $extend$libresoc.v:160636$8471 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$29 - connect \Y $extend$libresoc.v:159868$8539_Y + connect \Y $extend$libresoc.v:160636$8471_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:159869$8541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $extend$libresoc.v:160637$8473 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:159869$8541_Y + connect \Y $extend$libresoc.v:160637$8473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:159867$8538 + cell $not $not$libresoc.v:160635$8470 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:159867$8538_Y + connect \Y $not$libresoc.v:160635$8470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:159873$8546 + cell $not $not$libresoc.v:160641$8478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:159873$8546_Y + connect \Y $not$libresoc.v:160641$8478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:159876$8549 + cell $not $not$libresoc.v:160644$8481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:159876$8549_Y + connect \Y $not$libresoc.v:160644$8481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:159875$8548 + cell $or $or$libresoc.v:160643$8480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331954,10 +298497,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:159875$8548_Y + connect \Y $or$libresoc.v:160643$8480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:159878$8551 + cell $or $or$libresoc.v:160646$8483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331965,47 +298508,47 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:159878$8551_Y + connect \Y $or$libresoc.v:160646$8483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:159868$8540 + cell $pos $pos$libresoc.v:160636$8472 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159868$8539_Y - connect \Y $pos$libresoc.v:159868$8540_Y + connect \A $extend$libresoc.v:160636$8471_Y + connect \Y $pos$libresoc.v:160636$8472_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:159869$8542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $pos$libresoc.v:160637$8474 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159869$8541_Y - connect \Y $pos$libresoc.v:159869$8542_Y + connect \A $extend$libresoc.v:160637$8473_Y + connect \Y $pos$libresoc.v:160637$8474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:159872$8545 + cell $reduce_or $reduce_or$libresoc.v:160640$8477 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:159872$8545_Y + connect \Y $reduce_or$libresoc.v:160640$8477_Y end - attribute \src "libresoc.v:159521.7-159521.20" - process $proc$libresoc.v:159521$8565 + attribute \src "libresoc.v:160289.7-160289.20" + process $proc$libresoc.v:160289$8497 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159879.3-159890.6" - process $proc$libresoc.v:159879$8552 + attribute \src "libresoc.v:160647.3-160658.6" + process $proc$libresoc.v:160647$8484 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:159880.5-159880.29" + attribute \src "libresoc.v:160648.5-160648.29" switch \initial - attribute \src "libresoc.v:159880.9-159880.17" + attribute \src "libresoc.v:160648.9-160648.17" case 1'1 case end @@ -332023,13 +298566,13 @@ module \output$83 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:159891.3-159902.6" - process $proc$libresoc.v:159891$8553 + attribute \src "libresoc.v:160659.3-160670.6" + process $proc$libresoc.v:160659$8485 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:159892.5-159892.29" + attribute \src "libresoc.v:160660.5-160660.29" switch \initial - attribute \src "libresoc.v:159892.9-159892.17" + attribute \src "libresoc.v:160660.9-160660.17" case 1'1 case end @@ -332047,13 +298590,13 @@ module \output$83 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:159903.3-159914.6" - process $proc$libresoc.v:159903$8554 + attribute \src "libresoc.v:160671.3-160682.6" + process $proc$libresoc.v:160671$8486 assign { } { } - assign $0\o$27[64:0]$8555 $1\o$27[64:0]$8556 - attribute \src "libresoc.v:159904.5-159904.29" + assign $0\o$27[64:0]$8487 $1\o$27[64:0]$8488 + attribute \src "libresoc.v:160672.5-160672.29" switch \initial - attribute \src "libresoc.v:159904.9-159904.17" + attribute \src "libresoc.v:160672.9-160672.17" case 1'1 case end @@ -332062,23 +298605,23 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$27[64:0]$8556 \$28 + assign $1\o$27[64:0]$8488 \$28 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$27[64:0]$8556 \$32 + assign $1\o$27[64:0]$8488 \$32 end sync always - update \o$27 $0\o$27[64:0]$8555 + update \o$27 $0\o$27[64:0]$8487 end - attribute \src "libresoc.v:159915.3-159924.6" - process $proc$libresoc.v:159915$8557 + attribute \src "libresoc.v:160683.3-160692.6" + process $proc$libresoc.v:160683$8489 assign { } { } assign { } { } - assign $0\xer_so$24[0:0]$8558 $1\xer_so$24[0:0]$8559 - attribute \src "libresoc.v:159916.5-159916.29" + assign $0\xer_so$24[0:0]$8490 $1\xer_so$24[0:0]$8491 + attribute \src "libresoc.v:160684.5-160684.29" switch \initial - attribute \src "libresoc.v:159916.9-159916.17" + attribute \src "libresoc.v:160684.9-160684.17" case 1'1 case end @@ -332087,21 +298630,21 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$24[0:0]$8559 \$51 + assign $1\xer_so$24[0:0]$8491 \$51 case - assign $1\xer_so$24[0:0]$8559 1'0 + assign $1\xer_so$24[0:0]$8491 1'0 end sync always - update \xer_so$24 $0\xer_so$24[0:0]$8558 + update \xer_so$24 $0\xer_so$24[0:0]$8490 end - attribute \src "libresoc.v:159925.3-159934.6" - process $proc$libresoc.v:159925$8560 + attribute \src "libresoc.v:160693.3-160702.6" + process $proc$libresoc.v:160693$8492 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:159926.5-159926.29" + attribute \src "libresoc.v:160694.5-160694.29" switch \initial - attribute \src "libresoc.v:159926.9-159926.17" + attribute \src "libresoc.v:160694.9-160694.17" case 1'1 case end @@ -332117,14 +298660,14 @@ module \output$83 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:159935.3-159944.6" - process $proc$libresoc.v:159935$8561 + attribute \src "libresoc.v:160703.3-160712.6" + process $proc$libresoc.v:160703$8493 assign { } { } assign { } { } - assign $0\xer_ov$23[1:0]$8562 $1\xer_ov$23[1:0]$8563 - attribute \src "libresoc.v:159936.5-159936.29" + assign $0\xer_ov$23[1:0]$8494 $1\xer_ov$23[1:0]$8495 + attribute \src "libresoc.v:160704.5-160704.29" switch \initial - attribute \src "libresoc.v:159936.9-159936.17" + attribute \src "libresoc.v:160704.9-160704.17" case 1'1 case end @@ -332133,21 +298676,21 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$23[1:0]$8563 \xer_ov + assign $1\xer_ov$23[1:0]$8495 \xer_ov case - assign $1\xer_ov$23[1:0]$8563 2'00 + assign $1\xer_ov$23[1:0]$8495 2'00 end sync always - update \xer_ov$23 $0\xer_ov$23[1:0]$8562 + update \xer_ov$23 $0\xer_ov$23[1:0]$8494 end - attribute \src "libresoc.v:159945.3-159954.6" - process $proc$libresoc.v:159945$8564 + attribute \src "libresoc.v:160713.3-160722.6" + process $proc$libresoc.v:160713$8496 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:159946.5-159946.29" + attribute \src "libresoc.v:160714.5-160714.29" switch \initial - attribute \src "libresoc.v:159946.9-159946.17" + attribute \src "libresoc.v:160714.9-160714.17" case 1'1 case end @@ -332163,19 +298706,19 @@ module \output$83 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$25 $and$libresoc.v:159866$8537_Y - connect \$29 $not$libresoc.v:159867$8538_Y - connect \$28 $pos$libresoc.v:159868$8540_Y - connect \$32 $pos$libresoc.v:159869$8542_Y - connect \$34 $eq$libresoc.v:159870$8543_Y - connect \$36 $eq$libresoc.v:159871$8544_Y - connect \$38 $reduce_or$libresoc.v:159872$8545_Y - connect \$40 $not$libresoc.v:159873$8546_Y - connect \$42 $and$libresoc.v:159874$8547_Y - connect \$44 $or$libresoc.v:159875$8548_Y - connect \$46 $not$libresoc.v:159876$8549_Y - connect \$49 $and$libresoc.v:159877$8550_Y - connect \$51 $or$libresoc.v:159878$8551_Y + connect \$25 $and$libresoc.v:160634$8469_Y + connect \$29 $not$libresoc.v:160635$8470_Y + connect \$28 $pos$libresoc.v:160636$8472_Y + connect \$32 $pos$libresoc.v:160637$8474_Y + connect \$34 $eq$libresoc.v:160638$8475_Y + connect \$36 $eq$libresoc.v:160639$8476_Y + connect \$38 $reduce_or$libresoc.v:160640$8477_Y + connect \$40 $not$libresoc.v:160641$8478_Y + connect \$42 $and$libresoc.v:160642$8479_Y + connect \$44 $or$libresoc.v:160643$8480_Y + connect \$46 $not$libresoc.v:160644$8481_Y + connect \$49 $and$libresoc.v:160645$8482_Y + connect \$51 $or$libresoc.v:160646$8483_Y connect \oe$48 \$49 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -332192,93 +298735,93 @@ module \output$83 connect \target \o$27 [63:0] connect \oe \$25 end -attribute \src "libresoc.v:159974.1-160456.10" +attribute \src "libresoc.v:160742.1-161224.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage" attribute \generator "nMigen" module \output_stage - attribute \src "libresoc.v:159975.7-159975.20" + attribute \src "libresoc.v:160743.7-160743.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:161105.3-161176.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:160409.3-160442.6" + attribute \src "libresoc.v:161177.3-161210.6" wire $0\ov[0:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:161105.3-161176.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:160409.3-160442.6" + attribute \src "libresoc.v:161177.3-161210.6" wire $1\ov[0:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:161105.3-161176.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:160409.3-160442.6" + attribute \src "libresoc.v:161177.3-161210.6" wire $2\ov[0:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:161105.3-161176.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:160409.3-160442.6" + attribute \src "libresoc.v:161177.3-161210.6" wire $3\ov[0:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:161105.3-161176.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:161105.3-161176.6" wire width 64 $5\o[63:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:161105.3-161176.6" wire width 64 $6\o[63:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:161105.3-161176.6" wire width 64 $7\o[63:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:161105.3-161176.6" wire width 64 $8\o[63:0] - attribute \src "libresoc.v:160328.18-160328.122" - wire $and$libresoc.v:160328$8579_Y - attribute \src "libresoc.v:160320.18-160320.109" - wire width 65 $extend$libresoc.v:160320$8567_Y - attribute \src "libresoc.v:160321.18-160321.100" - wire width 65 $extend$libresoc.v:160321$8569_Y - attribute \src "libresoc.v:160323.18-160323.113" - wire width 65 $extend$libresoc.v:160323$8572_Y - attribute \src "libresoc.v:160324.18-160324.104" - wire width 65 $extend$libresoc.v:160324$8574_Y - attribute \src "libresoc.v:160332.18-160332.114" - wire width 64 $extend$libresoc.v:160332$8583_Y - attribute \src "libresoc.v:160333.18-160333.114" - wire width 64 $extend$libresoc.v:160333$8585_Y - attribute \src "libresoc.v:160334.18-160334.114" - wire width 64 $extend$libresoc.v:160334$8587_Y - attribute \src "libresoc.v:160335.18-160335.114" - wire width 64 $extend$libresoc.v:160335$8589_Y - attribute \src "libresoc.v:160336.18-160336.115" - wire width 64 $extend$libresoc.v:160336$8591_Y - attribute \src "libresoc.v:160329.18-160329.128" - wire $ne$libresoc.v:160329$8580_Y - attribute \src "libresoc.v:160320.18-160320.109" - wire width 65 $neg$libresoc.v:160320$8568_Y - attribute \src "libresoc.v:160323.18-160323.113" - wire width 65 $neg$libresoc.v:160323$8573_Y - attribute \src "libresoc.v:160326.18-160326.116" - wire $not$libresoc.v:160326$8577_Y - attribute \src "libresoc.v:160331.18-160331.99" - wire $not$libresoc.v:160331$8582_Y - attribute \src "libresoc.v:160321.18-160321.100" - wire width 65 $pos$libresoc.v:160321$8570_Y - attribute \src "libresoc.v:160324.18-160324.104" - wire width 65 $pos$libresoc.v:160324$8575_Y - attribute \src "libresoc.v:160330.18-160330.118" - wire width 64 $pos$libresoc.v:160330$8581_Y - attribute \src "libresoc.v:160332.18-160332.114" - wire width 64 $pos$libresoc.v:160332$8584_Y - attribute \src "libresoc.v:160333.18-160333.114" - wire width 64 $pos$libresoc.v:160333$8586_Y - attribute \src "libresoc.v:160334.18-160334.114" - wire width 64 $pos$libresoc.v:160334$8588_Y - attribute \src "libresoc.v:160335.18-160335.114" - wire width 64 $pos$libresoc.v:160335$8590_Y - attribute \src "libresoc.v:160336.18-160336.115" - wire width 64 $pos$libresoc.v:160336$8592_Y - attribute \src "libresoc.v:160322.18-160322.121" - wire width 65 $ternary$libresoc.v:160322$8571_Y - attribute \src "libresoc.v:160325.18-160325.122" - wire width 65 $ternary$libresoc.v:160325$8576_Y - attribute \src "libresoc.v:160319.18-160319.120" - wire $xor$libresoc.v:160319$8566_Y - attribute \src "libresoc.v:160327.18-160327.127" - wire $xor$libresoc.v:160327$8578_Y + attribute \src "libresoc.v:161096.18-161096.122" + wire $and$libresoc.v:161096$8511_Y + attribute \src "libresoc.v:161088.18-161088.109" + wire width 65 $extend$libresoc.v:161088$8499_Y + attribute \src "libresoc.v:161089.18-161089.100" + wire width 65 $extend$libresoc.v:161089$8501_Y + attribute \src "libresoc.v:161091.18-161091.113" + wire width 65 $extend$libresoc.v:161091$8504_Y + attribute \src "libresoc.v:161092.18-161092.104" + wire width 65 $extend$libresoc.v:161092$8506_Y + attribute \src "libresoc.v:161100.18-161100.114" + wire width 64 $extend$libresoc.v:161100$8515_Y + attribute \src "libresoc.v:161101.18-161101.114" + wire width 64 $extend$libresoc.v:161101$8517_Y + attribute \src "libresoc.v:161102.18-161102.114" + wire width 64 $extend$libresoc.v:161102$8519_Y + attribute \src "libresoc.v:161103.18-161103.114" + wire width 64 $extend$libresoc.v:161103$8521_Y + attribute \src "libresoc.v:161104.18-161104.115" + wire width 64 $extend$libresoc.v:161104$8523_Y + attribute \src "libresoc.v:161097.18-161097.128" + wire $ne$libresoc.v:161097$8512_Y + attribute \src "libresoc.v:161088.18-161088.109" + wire width 65 $neg$libresoc.v:161088$8500_Y + attribute \src "libresoc.v:161091.18-161091.113" + wire width 65 $neg$libresoc.v:161091$8505_Y + attribute \src "libresoc.v:161094.18-161094.116" + wire $not$libresoc.v:161094$8509_Y + attribute \src "libresoc.v:161099.18-161099.99" + wire $not$libresoc.v:161099$8514_Y + attribute \src "libresoc.v:161089.18-161089.100" + wire width 65 $pos$libresoc.v:161089$8502_Y + attribute \src "libresoc.v:161092.18-161092.104" + wire width 65 $pos$libresoc.v:161092$8507_Y + attribute \src "libresoc.v:161098.18-161098.118" + wire width 64 signed $pos$libresoc.v:161098$8513_Y + attribute \src "libresoc.v:161100.18-161100.114" + wire width 64 $pos$libresoc.v:161100$8516_Y + attribute \src "libresoc.v:161101.18-161101.114" + wire width 64 $pos$libresoc.v:161101$8518_Y + attribute \src "libresoc.v:161102.18-161102.114" + wire width 64 $pos$libresoc.v:161102$8520_Y + attribute \src "libresoc.v:161103.18-161103.114" + wire width 64 $pos$libresoc.v:161103$8522_Y + attribute \src "libresoc.v:161104.18-161104.115" + wire width 64 $pos$libresoc.v:161104$8524_Y + attribute \src "libresoc.v:161090.18-161090.121" + wire width 65 $ternary$libresoc.v:161090$8503_Y + attribute \src "libresoc.v:161093.18-161093.122" + wire width 65 $ternary$libresoc.v:161093$8508_Y + attribute \src "libresoc.v:161087.18-161087.120" + wire $xor$libresoc.v:161087$8498_Y + attribute \src "libresoc.v:161095.18-161095.127" + wire $xor$libresoc.v:161095$8510_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" @@ -332327,7 +298870,7 @@ module \output_stage wire input 21 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 20 \divisor_neg - attribute \src "libresoc.v:159975.7-159975.15" + attribute \src "libresoc.v:160743.7-160743.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -332593,9 +299136,9 @@ module \output_stage wire width 2 input 51 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 27 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 46 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 47 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" wire \ov @@ -332615,16 +299158,16 @@ module \output_stage wire width 32 \remainder_s32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" wire width 64 \remainder_s32_as_s64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 48 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 49 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 19 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 50 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $and $and$libresoc.v:160328$8579 + cell $and $and$libresoc.v:161096$8511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332632,82 +299175,82 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \logical_op__is_signed connect \B \$38 - connect \Y $and$libresoc.v:160328$8579_Y + connect \Y $and$libresoc.v:161096$8511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $pos $extend$libresoc.v:160320$8567 + cell $pos $extend$libresoc.v:161088$8499 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:160320$8567_Y + connect \Y $extend$libresoc.v:161088$8499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $extend$libresoc.v:160321$8569 + cell $pos $extend$libresoc.v:161089$8501 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:160321$8569_Y + connect \Y $extend$libresoc.v:161089$8501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $pos $extend$libresoc.v:160323$8572 + cell $pos $extend$libresoc.v:161091$8504 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:160323$8572_Y + connect \Y $extend$libresoc.v:161091$8504_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:160324$8574 + cell $pos $extend$libresoc.v:161092$8506 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:160324$8574_Y + connect \Y $extend$libresoc.v:161092$8506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $extend$libresoc.v:160332$8583 + cell $pos $extend$libresoc.v:161100$8515 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:160332$8583_Y + connect \Y $extend$libresoc.v:161100$8515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $extend$libresoc.v:160333$8585 + cell $pos $extend$libresoc.v:161101$8517 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:160333$8585_Y + connect \Y $extend$libresoc.v:161101$8517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $extend$libresoc.v:160334$8587 + cell $pos $extend$libresoc.v:161102$8519 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:160334$8587_Y + connect \Y $extend$libresoc.v:161102$8519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $extend$libresoc.v:160335$8589 + cell $pos $extend$libresoc.v:161103$8521 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:160335$8589_Y + connect \Y $extend$libresoc.v:161103$8521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $extend$libresoc.v:160336$8591 + cell $pos $extend$libresoc.v:161104$8523 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \remainder_64 [31:0] - connect \Y $extend$libresoc.v:160336$8591_Y + connect \Y $extend$libresoc.v:161104$8523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - cell $ne $ne$libresoc.v:160329$8580 + cell $ne $ne$libresoc.v:161097$8512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332715,122 +299258,122 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [32] connect \B \quotient_65 [31] - connect \Y $ne$libresoc.v:160329$8580_Y + connect \Y $ne$libresoc.v:161097$8512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $neg $neg$libresoc.v:160320$8568 + cell $neg $neg$libresoc.v:161088$8500 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160320$8567_Y - connect \Y $neg$libresoc.v:160320$8568_Y + connect \A $extend$libresoc.v:161088$8499_Y + connect \Y $neg$libresoc.v:161088$8500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $neg $neg$libresoc.v:160323$8573 + cell $neg $neg$libresoc.v:161091$8505 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160323$8572_Y - connect \Y $neg$libresoc.v:160323$8573_Y + connect \A $extend$libresoc.v:161091$8504_Y + connect \Y $neg$libresoc.v:161091$8505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - cell $not $not$libresoc.v:160326$8577 + cell $not $not$libresoc.v:161094$8509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__is_32bit - connect \Y $not$libresoc.v:160326$8577_Y + connect \Y $not$libresoc.v:161094$8509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $not $not$libresoc.v:160331$8582 + cell $not $not$libresoc.v:161099$8514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ov - connect \Y $not$libresoc.v:160331$8582_Y + connect \Y $not$libresoc.v:161099$8514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $pos$libresoc.v:160321$8570 + cell $pos $pos$libresoc.v:161089$8502 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160321$8569_Y - connect \Y $pos$libresoc.v:160321$8570_Y + connect \A $extend$libresoc.v:161089$8501_Y + connect \Y $pos$libresoc.v:161089$8502_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:160324$8575 + cell $pos $pos$libresoc.v:161092$8507 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160324$8574_Y - connect \Y $pos$libresoc.v:160324$8575_Y + connect \A $extend$libresoc.v:161092$8506_Y + connect \Y $pos$libresoc.v:161092$8507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" - cell $pos $pos$libresoc.v:160330$8581 + cell $pos $pos$libresoc.v:161098$8513 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } - connect \Y $pos$libresoc.v:160330$8581_Y + connect \Y $pos$libresoc.v:161098$8513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $pos$libresoc.v:160332$8584 + cell $pos $pos$libresoc.v:161100$8516 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160332$8583_Y - connect \Y $pos$libresoc.v:160332$8584_Y + connect \A $extend$libresoc.v:161100$8515_Y + connect \Y $pos$libresoc.v:161100$8516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $pos$libresoc.v:160333$8586 + cell $pos $pos$libresoc.v:161101$8518 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160333$8585_Y - connect \Y $pos$libresoc.v:160333$8586_Y + connect \A $extend$libresoc.v:161101$8517_Y + connect \Y $pos$libresoc.v:161101$8518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $pos$libresoc.v:160334$8588 + cell $pos $pos$libresoc.v:161102$8520 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160334$8587_Y - connect \Y $pos$libresoc.v:160334$8588_Y + connect \A $extend$libresoc.v:161102$8519_Y + connect \Y $pos$libresoc.v:161102$8520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $pos$libresoc.v:160335$8590 + cell $pos $pos$libresoc.v:161103$8522 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160335$8589_Y - connect \Y $pos$libresoc.v:160335$8590_Y + connect \A $extend$libresoc.v:161103$8521_Y + connect \Y $pos$libresoc.v:161103$8522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $pos$libresoc.v:160336$8592 + cell $pos $pos$libresoc.v:161104$8524 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160336$8591_Y - connect \Y $pos$libresoc.v:160336$8592_Y + connect \A $extend$libresoc.v:161104$8523_Y + connect \Y $pos$libresoc.v:161104$8524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $mux $ternary$libresoc.v:160322$8571 + cell $mux $ternary$libresoc.v:161090$8503 parameter \WIDTH 65 connect \A \$25 connect \B \$23 connect \S \quotient_neg - connect \Y $ternary$libresoc.v:160322$8571_Y + connect \Y $ternary$libresoc.v:161090$8503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $mux $ternary$libresoc.v:160325$8576 + cell $mux $ternary$libresoc.v:161093$8508 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \remainder_neg - connect \Y $ternary$libresoc.v:160325$8576_Y + connect \Y $ternary$libresoc.v:161093$8508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - cell $xor $xor$libresoc.v:160319$8566 + cell $xor $xor$libresoc.v:161087$8498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332838,10 +299381,10 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \dividend_neg connect \B \divisor_neg - connect \Y $xor$libresoc.v:160319$8566_Y + connect \Y $xor$libresoc.v:161087$8498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $xor $xor$libresoc.v:160327$8578 + cell $xor $xor$libresoc.v:161095$8510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332849,24 +299392,24 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [64] connect \B \quotient_65 [63] - connect \Y $xor$libresoc.v:160327$8578_Y + connect \Y $xor$libresoc.v:161095$8510_Y end - attribute \src "libresoc.v:159975.7-159975.20" - process $proc$libresoc.v:159975$8595 + attribute \src "libresoc.v:160743.7-160743.20" + process $proc$libresoc.v:160743$8527 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160337.3-160408.6" - process $proc$libresoc.v:160337$8593 + attribute \src "libresoc.v:161105.3-161176.6" + process $proc$libresoc.v:161105$8525 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:160338.5-160338.29" + attribute \src "libresoc.v:161106.5-161106.29" switch \initial - attribute \src "libresoc.v:160338.9-160338.17" + attribute \src "libresoc.v:161106.9-161106.17" case 1'1 case end @@ -332965,13 +299508,13 @@ module \output_stage sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:160409.3-160442.6" - process $proc$libresoc.v:160409$8594 + attribute \src "libresoc.v:161177.3-161210.6" + process $proc$libresoc.v:161177$8526 assign { } { } assign $0\ov[0:0] $1\ov[0:0] - attribute \src "libresoc.v:160410.5-160410.29" + attribute \src "libresoc.v:161178.5-161178.29" switch \initial - attribute \src "libresoc.v:160410.9-160410.17" + attribute \src "libresoc.v:161178.9-161178.17" case 1'1 case end @@ -333017,24 +299560,24 @@ module \output_stage sync always update \ov $0\ov[0:0] end - connect \$21 $xor$libresoc.v:160319$8566_Y - connect \$23 $neg$libresoc.v:160320$8568_Y - connect \$25 $pos$libresoc.v:160321$8570_Y - connect \$27 $ternary$libresoc.v:160322$8571_Y - connect \$30 $neg$libresoc.v:160323$8573_Y - connect \$32 $pos$libresoc.v:160324$8575_Y - connect \$34 $ternary$libresoc.v:160325$8576_Y - connect \$36 $not$libresoc.v:160326$8577_Y - connect \$38 $xor$libresoc.v:160327$8578_Y - connect \$40 $and$libresoc.v:160328$8579_Y - connect \$42 $ne$libresoc.v:160329$8580_Y - connect \$44 $pos$libresoc.v:160330$8581_Y - connect \$46 $not$libresoc.v:160331$8582_Y - connect \$48 $pos$libresoc.v:160332$8584_Y - connect \$50 $pos$libresoc.v:160333$8586_Y - connect \$52 $pos$libresoc.v:160334$8588_Y - connect \$54 $pos$libresoc.v:160335$8590_Y - connect \$56 $pos$libresoc.v:160336$8592_Y + connect \$21 $xor$libresoc.v:161087$8498_Y + connect \$23 $neg$libresoc.v:161088$8500_Y + connect \$25 $pos$libresoc.v:161089$8502_Y + connect \$27 $ternary$libresoc.v:161090$8503_Y + connect \$30 $neg$libresoc.v:161091$8505_Y + connect \$32 $pos$libresoc.v:161092$8507_Y + connect \$34 $ternary$libresoc.v:161093$8508_Y + connect \$36 $not$libresoc.v:161094$8509_Y + connect \$38 $xor$libresoc.v:161095$8510_Y + connect \$40 $and$libresoc.v:161096$8511_Y + connect \$42 $ne$libresoc.v:161097$8512_Y + connect \$44 $pos$libresoc.v:161098$8513_Y + connect \$46 $not$libresoc.v:161099$8514_Y + connect \$48 $pos$libresoc.v:161100$8516_Y + connect \$50 $pos$libresoc.v:161101$8518_Y + connect \$52 $pos$libresoc.v:161102$8520_Y + connect \$54 $pos$libresoc.v:161103$8522_Y + connect \$56 $pos$libresoc.v:161104$8524_Y connect \$29 \$34 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -333049,13 +299592,13 @@ module \output_stage connect \remainder_neg \dividend_neg connect \quotient_neg \$21 end -attribute \src "libresoc.v:160460.1-160471.10" +attribute \src "libresoc.v:161228.1-161239.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" attribute \generator "nMigen" module \p - attribute \src "libresoc.v:160469.17-160469.111" - wire $and$libresoc.v:160469$8596_Y + attribute \src "libresoc.v:161237.17-161237.111" + wire $and$libresoc.v:161237$8528_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333065,7 +299608,7 @@ module \p attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160469$8596 + cell $and $and$libresoc.v:161237$8528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333073,18 +299616,18 @@ module \p parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160469$8596_Y + connect \Y $and$libresoc.v:161237$8528_Y end - connect \$1 $and$libresoc.v:160469$8596_Y + connect \$1 $and$libresoc.v:161237$8528_Y connect \trigger \$1 end -attribute \src "libresoc.v:160475.1-160486.10" +attribute \src "libresoc.v:161243.1-161254.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" attribute \generator "nMigen" module \p$1 - attribute \src "libresoc.v:160484.17-160484.111" - wire $and$libresoc.v:160484$8597_Y + attribute \src "libresoc.v:161252.17-161252.111" + wire $and$libresoc.v:161252$8529_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333094,7 +299637,7 @@ module \p$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160484$8597 + cell $and $and$libresoc.v:161252$8529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333102,18 +299645,18 @@ module \p$1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160484$8597_Y + connect \Y $and$libresoc.v:161252$8529_Y end - connect \$1 $and$libresoc.v:160484$8597_Y + connect \$1 $and$libresoc.v:161252$8529_Y connect \trigger \$1 end -attribute \src "libresoc.v:160490.1-160501.10" +attribute \src "libresoc.v:161258.1-161269.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" attribute \generator "nMigen" module \p$108 - attribute \src "libresoc.v:160499.17-160499.111" - wire $and$libresoc.v:160499$8598_Y + attribute \src "libresoc.v:161267.17-161267.111" + wire $and$libresoc.v:161267$8530_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333123,7 +299666,7 @@ module \p$108 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160499$8598 + cell $and $and$libresoc.v:161267$8530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333131,18 +299674,18 @@ module \p$108 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160499$8598_Y + connect \Y $and$libresoc.v:161267$8530_Y end - connect \$1 $and$libresoc.v:160499$8598_Y + connect \$1 $and$libresoc.v:161267$8530_Y connect \trigger \$1 end -attribute \src "libresoc.v:160505.1-160516.10" +attribute \src "libresoc.v:161273.1-161284.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" attribute \generator "nMigen" module \p$111 - attribute \src "libresoc.v:160514.17-160514.111" - wire $and$libresoc.v:160514$8599_Y + attribute \src "libresoc.v:161282.17-161282.111" + wire $and$libresoc.v:161282$8531_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333152,7 +299695,7 @@ module \p$111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160514$8599 + cell $and $and$libresoc.v:161282$8531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333160,18 +299703,18 @@ module \p$111 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160514$8599_Y + connect \Y $and$libresoc.v:161282$8531_Y end - connect \$1 $and$libresoc.v:160514$8599_Y + connect \$1 $and$libresoc.v:161282$8531_Y connect \trigger \$1 end -attribute \src "libresoc.v:160520.1-160531.10" +attribute \src "libresoc.v:161288.1-161299.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" attribute \generator "nMigen" module \p$116 - attribute \src "libresoc.v:160529.17-160529.111" - wire $and$libresoc.v:160529$8600_Y + attribute \src "libresoc.v:161297.17-161297.111" + wire $and$libresoc.v:161297$8532_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333181,7 +299724,7 @@ module \p$116 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160529$8600 + cell $and $and$libresoc.v:161297$8532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333189,18 +299732,18 @@ module \p$116 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160529$8600_Y + connect \Y $and$libresoc.v:161297$8532_Y end - connect \$1 $and$libresoc.v:160529$8600_Y + connect \$1 $and$libresoc.v:161297$8532_Y connect \trigger \$1 end -attribute \src "libresoc.v:160535.1-160546.10" +attribute \src "libresoc.v:161303.1-161314.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p" attribute \generator "nMigen" module \p$17 - attribute \src "libresoc.v:160544.17-160544.111" - wire $and$libresoc.v:160544$8601_Y + attribute \src "libresoc.v:161312.17-161312.111" + wire $and$libresoc.v:161312$8533_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333210,7 +299753,7 @@ module \p$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160544$8601 + cell $and $and$libresoc.v:161312$8533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333218,18 +299761,18 @@ module \p$17 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160544$8601_Y + connect \Y $and$libresoc.v:161312$8533_Y end - connect \$1 $and$libresoc.v:160544$8601_Y + connect \$1 $and$libresoc.v:161312$8533_Y connect \trigger \$1 end -attribute \src "libresoc.v:160550.1-160561.10" +attribute \src "libresoc.v:161318.1-161329.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" attribute \generator "nMigen" module \p$20 - attribute \src "libresoc.v:160559.17-160559.111" - wire $and$libresoc.v:160559$8602_Y + attribute \src "libresoc.v:161327.17-161327.111" + wire $and$libresoc.v:161327$8534_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333239,7 +299782,7 @@ module \p$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160559$8602 + cell $and $and$libresoc.v:161327$8534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333247,18 +299790,18 @@ module \p$20 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160559$8602_Y + connect \Y $and$libresoc.v:161327$8534_Y end - connect \$1 $and$libresoc.v:160559$8602_Y + connect \$1 $and$libresoc.v:161327$8534_Y connect \trigger \$1 end -attribute \src "libresoc.v:160565.1-160576.10" +attribute \src "libresoc.v:161333.1-161344.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" attribute \generator "nMigen" module \p$3 - attribute \src "libresoc.v:160574.17-160574.111" - wire $and$libresoc.v:160574$8603_Y + attribute \src "libresoc.v:161342.17-161342.111" + wire $and$libresoc.v:161342$8535_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333268,7 +299811,7 @@ module \p$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160574$8603 + cell $and $and$libresoc.v:161342$8535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333276,18 +299819,18 @@ module \p$3 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160574$8603_Y + connect \Y $and$libresoc.v:161342$8535_Y end - connect \$1 $and$libresoc.v:160574$8603_Y + connect \$1 $and$libresoc.v:161342$8535_Y connect \trigger \$1 end -attribute \src "libresoc.v:160580.1-160591.10" +attribute \src "libresoc.v:161348.1-161359.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p" attribute \generator "nMigen" module \p$30 - attribute \src "libresoc.v:160589.17-160589.111" - wire $and$libresoc.v:160589$8604_Y + attribute \src "libresoc.v:161357.17-161357.111" + wire $and$libresoc.v:161357$8536_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333297,7 +299840,7 @@ module \p$30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160589$8604 + cell $and $and$libresoc.v:161357$8536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333305,18 +299848,18 @@ module \p$30 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160589$8604_Y + connect \Y $and$libresoc.v:161357$8536_Y end - connect \$1 $and$libresoc.v:160589$8604_Y + connect \$1 $and$libresoc.v:161357$8536_Y connect \trigger \$1 end -attribute \src "libresoc.v:160595.1-160606.10" +attribute \src "libresoc.v:161363.1-161374.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" attribute \generator "nMigen" module \p$33 - attribute \src "libresoc.v:160604.17-160604.111" - wire $and$libresoc.v:160604$8605_Y + attribute \src "libresoc.v:161372.17-161372.111" + wire $and$libresoc.v:161372$8537_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333326,7 +299869,7 @@ module \p$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160604$8605 + cell $and $and$libresoc.v:161372$8537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333334,18 +299877,18 @@ module \p$33 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160604$8605_Y + connect \Y $and$libresoc.v:161372$8537_Y end - connect \$1 $and$libresoc.v:160604$8605_Y + connect \$1 $and$libresoc.v:161372$8537_Y connect \trigger \$1 end -attribute \src "libresoc.v:160610.1-160621.10" +attribute \src "libresoc.v:161378.1-161389.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p" attribute \generator "nMigen" module \p$36 - attribute \src "libresoc.v:160619.17-160619.111" - wire $and$libresoc.v:160619$8606_Y + attribute \src "libresoc.v:161387.17-161387.111" + wire $and$libresoc.v:161387$8538_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333355,7 +299898,7 @@ module \p$36 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160619$8606 + cell $and $and$libresoc.v:161387$8538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333363,18 +299906,18 @@ module \p$36 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160619$8606_Y + connect \Y $and$libresoc.v:161387$8538_Y end - connect \$1 $and$libresoc.v:160619$8606_Y + connect \$1 $and$libresoc.v:161387$8538_Y connect \trigger \$1 end -attribute \src "libresoc.v:160625.1-160636.10" +attribute \src "libresoc.v:161393.1-161404.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.p" attribute \generator "nMigen" module \p$46 - attribute \src "libresoc.v:160634.17-160634.111" - wire $and$libresoc.v:160634$8607_Y + attribute \src "libresoc.v:161402.17-161402.111" + wire $and$libresoc.v:161402$8539_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333384,7 +299927,7 @@ module \p$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160634$8607 + cell $and $and$libresoc.v:161402$8539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333392,18 +299935,18 @@ module \p$46 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160634$8607_Y + connect \Y $and$libresoc.v:161402$8539_Y end - connect \$1 $and$libresoc.v:160634$8607_Y + connect \$1 $and$libresoc.v:161402$8539_Y connect \trigger \$1 end -attribute \src "libresoc.v:160640.1-160651.10" +attribute \src "libresoc.v:161408.1-161419.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p" attribute \generator "nMigen" module \p$48 - attribute \src "libresoc.v:160649.17-160649.111" - wire $and$libresoc.v:160649$8608_Y + attribute \src "libresoc.v:161417.17-161417.111" + wire $and$libresoc.v:161417$8540_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333413,7 +299956,7 @@ module \p$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160649$8608 + cell $and $and$libresoc.v:161417$8540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333421,18 +299964,18 @@ module \p$48 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160649$8608_Y + connect \Y $and$libresoc.v:161417$8540_Y end - connect \$1 $and$libresoc.v:160649$8608_Y + connect \$1 $and$libresoc.v:161417$8540_Y connect \trigger \$1 end -attribute \src "libresoc.v:160655.1-160666.10" +attribute \src "libresoc.v:161423.1-161434.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.p" attribute \generator "nMigen" module \p$5 - attribute \src "libresoc.v:160664.17-160664.111" - wire $and$libresoc.v:160664$8609_Y + attribute \src "libresoc.v:161432.17-161432.111" + wire $and$libresoc.v:161432$8541_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333442,7 +299985,7 @@ module \p$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160664$8609 + cell $and $and$libresoc.v:161432$8541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333450,18 +299993,18 @@ module \p$5 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160664$8609_Y + connect \Y $and$libresoc.v:161432$8541_Y end - connect \$1 $and$libresoc.v:160664$8609_Y + connect \$1 $and$libresoc.v:161432$8541_Y connect \trigger \$1 end -attribute \src "libresoc.v:160670.1-160681.10" +attribute \src "libresoc.v:161438.1-161449.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p" attribute \generator "nMigen" module \p$52 - attribute \src "libresoc.v:160679.17-160679.111" - wire $and$libresoc.v:160679$8610_Y + attribute \src "libresoc.v:161447.17-161447.111" + wire $and$libresoc.v:161447$8542_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333471,7 +300014,7 @@ module \p$52 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160679$8610 + cell $and $and$libresoc.v:161447$8542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333479,18 +300022,18 @@ module \p$52 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160679$8610_Y + connect \Y $and$libresoc.v:161447$8542_Y end - connect \$1 $and$libresoc.v:160679$8610_Y + connect \$1 $and$libresoc.v:161447$8542_Y connect \trigger \$1 end -attribute \src "libresoc.v:160685.1-160696.10" +attribute \src "libresoc.v:161453.1-161464.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.p" attribute \generator "nMigen" module \p$62 - attribute \src "libresoc.v:160694.17-160694.111" - wire $and$libresoc.v:160694$8611_Y + attribute \src "libresoc.v:161462.17-161462.111" + wire $and$libresoc.v:161462$8543_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333500,7 +300043,7 @@ module \p$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160694$8611 + cell $and $and$libresoc.v:161462$8543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333508,18 +300051,18 @@ module \p$62 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160694$8611_Y + connect \Y $and$libresoc.v:161462$8543_Y end - connect \$1 $and$libresoc.v:160694$8611_Y + connect \$1 $and$libresoc.v:161462$8543_Y connect \trigger \$1 end -attribute \src "libresoc.v:160700.1-160711.10" +attribute \src "libresoc.v:161468.1-161479.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p" attribute \generator "nMigen" module \p$65 - attribute \src "libresoc.v:160709.17-160709.111" - wire $and$libresoc.v:160709$8612_Y + attribute \src "libresoc.v:161477.17-161477.111" + wire $and$libresoc.v:161477$8544_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333529,7 +300072,7 @@ module \p$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160709$8612 + cell $and $and$libresoc.v:161477$8544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333537,18 +300080,18 @@ module \p$65 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160709$8612_Y + connect \Y $and$libresoc.v:161477$8544_Y end - connect \$1 $and$libresoc.v:160709$8612_Y + connect \$1 $and$libresoc.v:161477$8544_Y connect \trigger \$1 end -attribute \src "libresoc.v:160715.1-160726.10" +attribute \src "libresoc.v:161483.1-161494.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p" attribute \generator "nMigen" module \p$7 - attribute \src "libresoc.v:160724.17-160724.111" - wire $and$libresoc.v:160724$8613_Y + attribute \src "libresoc.v:161492.17-161492.111" + wire $and$libresoc.v:161492$8545_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333558,7 +300101,7 @@ module \p$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160724$8613 + cell $and $and$libresoc.v:161492$8545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333566,18 +300109,18 @@ module \p$7 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160724$8613_Y + connect \Y $and$libresoc.v:161492$8545_Y end - connect \$1 $and$libresoc.v:160724$8613_Y + connect \$1 $and$libresoc.v:161492$8545_Y connect \trigger \$1 end -attribute \src "libresoc.v:160730.1-160741.10" +attribute \src "libresoc.v:161498.1-161509.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.p" attribute \generator "nMigen" module \p$74 - attribute \src "libresoc.v:160739.17-160739.111" - wire $and$libresoc.v:160739$8614_Y + attribute \src "libresoc.v:161507.17-161507.111" + wire $and$libresoc.v:161507$8546_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333587,7 +300130,7 @@ module \p$74 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160739$8614 + cell $and $and$libresoc.v:161507$8546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333595,18 +300138,18 @@ module \p$74 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160739$8614_Y + connect \Y $and$libresoc.v:161507$8546_Y end - connect \$1 $and$libresoc.v:160739$8614_Y + connect \$1 $and$libresoc.v:161507$8546_Y connect \trigger \$1 end -attribute \src "libresoc.v:160745.1-160756.10" +attribute \src "libresoc.v:161513.1-161524.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" attribute \generator "nMigen" module \p$76 - attribute \src "libresoc.v:160754.17-160754.111" - wire $and$libresoc.v:160754$8615_Y + attribute \src "libresoc.v:161522.17-161522.111" + wire $and$libresoc.v:161522$8547_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333616,7 +300159,7 @@ module \p$76 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160754$8615 + cell $and $and$libresoc.v:161522$8547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333624,18 +300167,18 @@ module \p$76 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160754$8615_Y + connect \Y $and$libresoc.v:161522$8547_Y end - connect \$1 $and$libresoc.v:160754$8615_Y + connect \$1 $and$libresoc.v:161522$8547_Y connect \trigger \$1 end -attribute \src "libresoc.v:160760.1-160771.10" +attribute \src "libresoc.v:161528.1-161539.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" attribute \generator "nMigen" module \p$79 - attribute \src "libresoc.v:160769.17-160769.111" - wire $and$libresoc.v:160769$8616_Y + attribute \src "libresoc.v:161537.17-161537.111" + wire $and$libresoc.v:161537$8548_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333645,7 +300188,7 @@ module \p$79 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160769$8616 + cell $and $and$libresoc.v:161537$8548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333653,18 +300196,18 @@ module \p$79 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160769$8616_Y + connect \Y $and$libresoc.v:161537$8548_Y end - connect \$1 $and$libresoc.v:160769$8616_Y + connect \$1 $and$libresoc.v:161537$8548_Y connect \trigger \$1 end -attribute \src "libresoc.v:160775.1-160786.10" +attribute \src "libresoc.v:161543.1-161554.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" attribute \generator "nMigen" module \p$81 - attribute \src "libresoc.v:160784.17-160784.111" - wire $and$libresoc.v:160784$8617_Y + attribute \src "libresoc.v:161552.17-161552.111" + wire $and$libresoc.v:161552$8549_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333674,7 +300217,7 @@ module \p$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160784$8617 + cell $and $and$libresoc.v:161552$8549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333682,18 +300225,18 @@ module \p$81 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160784$8617_Y + connect \Y $and$libresoc.v:161552$8549_Y end - connect \$1 $and$libresoc.v:160784$8617_Y + connect \$1 $and$libresoc.v:161552$8549_Y connect \trigger \$1 end -attribute \src "libresoc.v:160790.1-160801.10" +attribute \src "libresoc.v:161558.1-161569.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p" attribute \generator "nMigen" module \p$91 - attribute \src "libresoc.v:160799.17-160799.111" - wire $and$libresoc.v:160799$8618_Y + attribute \src "libresoc.v:161567.17-161567.111" + wire $and$libresoc.v:161567$8550_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333703,7 +300246,7 @@ module \p$91 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160799$8618 + cell $and $and$libresoc.v:161567$8550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333711,18 +300254,18 @@ module \p$91 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160799$8618_Y + connect \Y $and$libresoc.v:161567$8550_Y end - connect \$1 $and$libresoc.v:160799$8618_Y + connect \$1 $and$libresoc.v:161567$8550_Y connect \trigger \$1 end -attribute \src "libresoc.v:160805.1-160816.10" +attribute \src "libresoc.v:161573.1-161584.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" attribute \generator "nMigen" module \p$93 - attribute \src "libresoc.v:160814.17-160814.111" - wire $and$libresoc.v:160814$8619_Y + attribute \src "libresoc.v:161582.17-161582.111" + wire $and$libresoc.v:161582$8551_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333732,7 +300275,7 @@ module \p$93 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160814$8619 + cell $and $and$libresoc.v:161582$8551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333740,18 +300283,18 @@ module \p$93 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160814$8619_Y + connect \Y $and$libresoc.v:161582$8551_Y end - connect \$1 $and$libresoc.v:160814$8619_Y + connect \$1 $and$libresoc.v:161582$8551_Y connect \trigger \$1 end -attribute \src "libresoc.v:160820.1-160831.10" +attribute \src "libresoc.v:161588.1-161599.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" attribute \generator "nMigen" module \p$96 - attribute \src "libresoc.v:160829.17-160829.111" - wire $and$libresoc.v:160829$8620_Y + attribute \src "libresoc.v:161597.17-161597.111" + wire $and$libresoc.v:161597$8552_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333761,7 +300304,7 @@ module \p$96 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160829$8620 + cell $and $and$libresoc.v:161597$8552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333769,18 +300312,18 @@ module \p$96 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160829$8620_Y + connect \Y $and$libresoc.v:161597$8552_Y end - connect \$1 $and$libresoc.v:160829$8620_Y + connect \$1 $and$libresoc.v:161597$8552_Y connect \trigger \$1 end -attribute \src "libresoc.v:160835.1-160846.10" +attribute \src "libresoc.v:161603.1-161614.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" attribute \generator "nMigen" module \p$98 - attribute \src "libresoc.v:160844.17-160844.111" - wire $and$libresoc.v:160844$8621_Y + attribute \src "libresoc.v:161612.17-161612.111" + wire $and$libresoc.v:161612$8553_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333790,7 +300333,7 @@ module \p$98 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160844$8621 + cell $and $and$libresoc.v:161612$8553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333798,36 +300341,36 @@ module \p$98 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160844$8621_Y + connect \Y $and$libresoc.v:161612$8553_Y end - connect \$1 $and$libresoc.v:160844$8621_Y + connect \$1 $and$libresoc.v:161612$8553_Y connect \trigger \$1 end -attribute \src "libresoc.v:160850.1-160873.10" +attribute \src "libresoc.v:161618.1-161641.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick" attribute \generator "nMigen" module \pick - attribute \src "libresoc.v:160851.7-160851.20" + attribute \src "libresoc.v:161619.7-161619.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160862.3-160871.6" + attribute \src "libresoc.v:161630.3-161639.6" wire $0\o[0:0] - attribute \src "libresoc.v:160862.3-160871.6" + attribute \src "libresoc.v:161630.3-161639.6" wire $1\o[0:0] - attribute \src "libresoc.v:160861.17-160861.95" - wire $eq$libresoc.v:160861$8622_Y + attribute \src "libresoc.v:161629.17-161629.95" + wire $eq$libresoc.v:161629$8554_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" wire input 3 \i - attribute \src "libresoc.v:160851.7-160851.15" + attribute \src "libresoc.v:161619.7-161619.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" wire output 2 \n attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $eq$libresoc.v:160861$8622 + cell $eq $eq$libresoc.v:161629$8554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333835,24 +300378,24 @@ module \pick parameter \Y_WIDTH 1 connect \A \i connect \B 1'0 - connect \Y $eq$libresoc.v:160861$8622_Y + connect \Y $eq$libresoc.v:161629$8554_Y end - attribute \src "libresoc.v:160851.7-160851.20" - process $proc$libresoc.v:160851$8624 + attribute \src "libresoc.v:161619.7-161619.20" + process $proc$libresoc.v:161619$8556 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160862.3-160871.6" - process $proc$libresoc.v:160862$8623 + attribute \src "libresoc.v:161630.3-161639.6" + process $proc$libresoc.v:161630$8555 assign { } { } assign { } { } assign $0\o[0:0] $1\o[0:0] - attribute \src "libresoc.v:160863.5-160863.29" + attribute \src "libresoc.v:161631.5-161631.29" switch \initial - attribute \src "libresoc.v:160863.9-160863.17" + attribute \src "libresoc.v:161631.9-161631.17" case 1'1 case end @@ -333868,296 +300411,296 @@ module \pick sync always update \o $0\o[0:0] end - connect \$1 $eq$libresoc.v:160861$8622_Y + connect \$1 $eq$libresoc.v:161629$8554_Y connect \n \$1 end -attribute \src "libresoc.v:160877.1-161691.10" +attribute \src "libresoc.v:161645.1-162459.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem" attribute \generator "nMigen" module \pimem - attribute \src "libresoc.v:161654.3-161669.6" + attribute \src "libresoc.v:162422.3-162437.6" wire $0\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:161618.3-161653.6" - wire $0\adrok_l_s_addr_acked$next[0:0]$8714 - attribute \src "libresoc.v:161176.3-161177.57" + attribute \src "libresoc.v:162386.3-162421.6" + wire $0\adrok_l_s_addr_acked$next[0:0]$8646 + attribute \src "libresoc.v:161944.3-161945.57" wire $0\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:161268.3-161276.6" - wire $0\busy_delay$next[0:0]$8682 - attribute \src "libresoc.v:161174.3-161175.37" + attribute \src "libresoc.v:162036.3-162044.6" + wire $0\busy_delay$next[0:0]$8614 + attribute \src "libresoc.v:161942.3-161943.37" wire $0\busy_delay[0:0] - attribute \src "libresoc.v:161602.3-161617.6" + attribute \src "libresoc.v:162370.3-162385.6" wire $0\busy_l_r_busy[0:0] - attribute \src "libresoc.v:161592.3-161601.6" + attribute \src "libresoc.v:162360.3-162369.6" wire $0\busy_l_s_busy[0:0] - attribute \src "libresoc.v:161582.3-161591.6" + attribute \src "libresoc.v:162350.3-162359.6" wire $0\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:161563.3-161572.6" + attribute \src "libresoc.v:162331.3-162340.6" wire $0\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:161524.3-161562.6" - wire width 2 $0\fsm_state$next[1:0]$8700 - attribute \src "libresoc.v:161166.3-161167.35" + attribute \src "libresoc.v:162292.3-162330.6" + wire width 2 $0\fsm_state$next[1:0]$8632 + attribute \src "libresoc.v:161934.3-161935.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:160878.7-160878.20" + attribute \src "libresoc.v:161646.7-161646.20" wire $0\initial[0:0] - attribute \src "libresoc.v:161464.3-161473.6" + attribute \src "libresoc.v:162232.3-162241.6" wire $0\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:161172.3-161173.35" + attribute \src "libresoc.v:161940.3-161941.35" wire $0\lds_dly[0:0] - attribute \src "libresoc.v:161397.3-161427.6" + attribute \src "libresoc.v:162165.3-162195.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161454.3-161463.6" + attribute \src "libresoc.v:162222.3-162231.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:161474.3-161483.6" + attribute \src "libresoc.v:162242.3-162251.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:161303.3-161318.6" + attribute \src "libresoc.v:162071.3-162086.6" wire width 4 $0\lenexp_addr_i[3:0] - attribute \src "libresoc.v:161287.3-161302.6" + attribute \src "libresoc.v:162055.3-162070.6" wire width 4 $0\lenexp_len_i[3:0] - attribute \src "libresoc.v:161573.3-161581.6" - wire $0\lsui_active_dly$next[0:0]$8708 - attribute \src "libresoc.v:161164.3-161165.47" + attribute \src "libresoc.v:162341.3-162349.6" + wire $0\lsui_active_dly$next[0:0]$8640 + attribute \src "libresoc.v:161932.3-161933.47" wire $0\lsui_active_dly[0:0] - attribute \src "libresoc.v:161504.3-161523.6" + attribute \src "libresoc.v:162272.3-162291.6" wire $0\lsui_busy[0:0] - attribute \src "libresoc.v:161168.3-161169.36" + attribute \src "libresoc.v:161936.3-161937.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:161444.3-161453.6" + attribute \src "libresoc.v:162212.3-162221.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:161428.3-161443.6" + attribute \src "libresoc.v:162196.3-162211.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:161277.3-161286.6" + attribute \src "libresoc.v:162045.3-162054.6" wire $0\st_active_r_st_active[0:0] - attribute \src "libresoc.v:161258.3-161267.6" + attribute \src "libresoc.v:162026.3-162035.6" wire $0\st_done_r_st_done[0:0] - attribute \src "libresoc.v:161243.3-161257.6" - wire $0\st_done_s_st_done$next[0:0]$8677 - attribute \src "libresoc.v:161178.3-161179.51" + attribute \src "libresoc.v:162011.3-162025.6" + wire $0\st_done_s_st_done$next[0:0]$8609 + attribute \src "libresoc.v:161946.3-161947.51" wire $0\st_done_s_st_done[0:0] - attribute \src "libresoc.v:161484.3-161493.6" + attribute \src "libresoc.v:162252.3-162261.6" wire width 64 $0\stdata[63:0] - attribute \src "libresoc.v:161170.3-161171.35" + attribute \src "libresoc.v:161938.3-161939.35" wire $0\sts_dly[0:0] - attribute \src "libresoc.v:161319.3-161344.6" + attribute \src "libresoc.v:162087.3-162112.6" wire $0\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161371.3-161396.6" + attribute \src "libresoc.v:162139.3-162164.6" wire width 48 $0\x_addr_i[47:0] - attribute \src "libresoc.v:161345.3-161370.6" + attribute \src "libresoc.v:162113.3-162138.6" wire width 8 $0\x_mask_i[7:0] - attribute \src "libresoc.v:161494.3-161503.6" + attribute \src "libresoc.v:162262.3-162271.6" wire width 64 $0\x_st_data_i[63:0] - attribute \src "libresoc.v:161654.3-161669.6" + attribute \src "libresoc.v:162422.3-162437.6" wire $1\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:161618.3-161653.6" - wire $1\adrok_l_s_addr_acked$next[0:0]$8715 - attribute \src "libresoc.v:160972.7-160972.34" + attribute \src "libresoc.v:162386.3-162421.6" + wire $1\adrok_l_s_addr_acked$next[0:0]$8647 + attribute \src "libresoc.v:161740.7-161740.34" wire $1\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:161268.3-161276.6" - wire $1\busy_delay$next[0:0]$8683 - attribute \src "libresoc.v:160976.7-160976.24" + attribute \src "libresoc.v:162036.3-162044.6" + wire $1\busy_delay$next[0:0]$8615 + attribute \src "libresoc.v:161744.7-161744.24" wire $1\busy_delay[0:0] - attribute \src "libresoc.v:161602.3-161617.6" + attribute \src "libresoc.v:162370.3-162385.6" wire $1\busy_l_r_busy[0:0] - attribute \src "libresoc.v:161592.3-161601.6" + attribute \src "libresoc.v:162360.3-162369.6" wire $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:161582.3-161591.6" + attribute \src "libresoc.v:162350.3-162359.6" wire $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:161563.3-161572.6" + attribute \src "libresoc.v:162331.3-162340.6" wire $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:161524.3-161562.6" - wire width 2 $1\fsm_state$next[1:0]$8701 - attribute \src "libresoc.v:160998.13-160998.29" + attribute \src "libresoc.v:162292.3-162330.6" + wire width 2 $1\fsm_state$next[1:0]$8633 + attribute \src "libresoc.v:161766.13-161766.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:161464.3-161473.6" + attribute \src "libresoc.v:162232.3-162241.6" wire $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:161012.7-161012.21" + attribute \src "libresoc.v:161780.7-161780.21" wire $1\lds_dly[0:0] - attribute \src "libresoc.v:161397.3-161427.6" + attribute \src "libresoc.v:162165.3-162195.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161454.3-161463.6" + attribute \src "libresoc.v:162222.3-162231.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:161474.3-161483.6" + attribute \src "libresoc.v:162242.3-162251.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:161303.3-161318.6" + attribute \src "libresoc.v:162071.3-162086.6" wire width 4 $1\lenexp_addr_i[3:0] - attribute \src "libresoc.v:161287.3-161302.6" + attribute \src "libresoc.v:162055.3-162070.6" wire width 4 $1\lenexp_len_i[3:0] - attribute \src "libresoc.v:161573.3-161581.6" - wire $1\lsui_active_dly$next[0:0]$8709 - attribute \src "libresoc.v:161055.7-161055.29" + attribute \src "libresoc.v:162341.3-162349.6" + wire $1\lsui_active_dly$next[0:0]$8641 + attribute \src "libresoc.v:161823.7-161823.29" wire $1\lsui_active_dly[0:0] - attribute \src "libresoc.v:161504.3-161523.6" + attribute \src "libresoc.v:162272.3-162291.6" wire $1\lsui_busy[0:0] - attribute \src "libresoc.v:161067.7-161067.25" + attribute \src "libresoc.v:161835.7-161835.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:161444.3-161453.6" + attribute \src "libresoc.v:162212.3-162221.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:161428.3-161443.6" + attribute \src "libresoc.v:162196.3-162211.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:161277.3-161286.6" + attribute \src "libresoc.v:162045.3-162054.6" wire $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:161258.3-161267.6" + attribute \src "libresoc.v:162026.3-162035.6" wire $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:161243.3-161257.6" - wire $1\st_done_s_st_done$next[0:0]$8678 - attribute \src "libresoc.v:161087.7-161087.31" + attribute \src "libresoc.v:162011.3-162025.6" + wire $1\st_done_s_st_done$next[0:0]$8610 + attribute \src "libresoc.v:161855.7-161855.31" wire $1\st_done_s_st_done[0:0] - attribute \src "libresoc.v:161484.3-161493.6" + attribute \src "libresoc.v:162252.3-162261.6" wire width 64 $1\stdata[63:0] - attribute \src "libresoc.v:161095.7-161095.21" + attribute \src "libresoc.v:161863.7-161863.21" wire $1\sts_dly[0:0] - attribute \src "libresoc.v:161319.3-161344.6" + attribute \src "libresoc.v:162087.3-162112.6" wire $1\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161371.3-161396.6" + attribute \src "libresoc.v:162139.3-162164.6" wire width 48 $1\x_addr_i[47:0] - attribute \src "libresoc.v:161345.3-161370.6" + attribute \src "libresoc.v:162113.3-162138.6" wire width 8 $1\x_mask_i[7:0] - attribute \src "libresoc.v:161494.3-161503.6" + attribute \src "libresoc.v:162262.3-162271.6" wire width 64 $1\x_st_data_i[63:0] - attribute \src "libresoc.v:161654.3-161669.6" + attribute \src "libresoc.v:162422.3-162437.6" wire $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:161618.3-161653.6" - wire $2\adrok_l_s_addr_acked$next[0:0]$8716 - attribute \src "libresoc.v:161602.3-161617.6" + attribute \src "libresoc.v:162386.3-162421.6" + wire $2\adrok_l_s_addr_acked$next[0:0]$8648 + attribute \src "libresoc.v:162370.3-162385.6" wire $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:161524.3-161562.6" - wire width 2 $2\fsm_state$next[1:0]$8702 - attribute \src "libresoc.v:161397.3-161427.6" + attribute \src "libresoc.v:162292.3-162330.6" + wire width 2 $2\fsm_state$next[1:0]$8634 + attribute \src "libresoc.v:162165.3-162195.6" wire $2\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161303.3-161318.6" + attribute \src "libresoc.v:162071.3-162086.6" wire width 4 $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:161287.3-161302.6" + attribute \src "libresoc.v:162055.3-162070.6" wire width 4 $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:161504.3-161523.6" + attribute \src "libresoc.v:162272.3-162291.6" wire $2\lsui_busy[0:0] - attribute \src "libresoc.v:161428.3-161443.6" + attribute \src "libresoc.v:162196.3-162211.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:161243.3-161257.6" - wire $2\st_done_s_st_done$next[0:0]$8679 - attribute \src "libresoc.v:161319.3-161344.6" + attribute \src "libresoc.v:162011.3-162025.6" + wire $2\st_done_s_st_done$next[0:0]$8611 + attribute \src "libresoc.v:162087.3-162112.6" wire $2\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161371.3-161396.6" + attribute \src "libresoc.v:162139.3-162164.6" wire width 48 $2\x_addr_i[47:0] - attribute \src "libresoc.v:161345.3-161370.6" + attribute \src "libresoc.v:162113.3-162138.6" wire width 8 $2\x_mask_i[7:0] - attribute \src "libresoc.v:161618.3-161653.6" - wire $3\adrok_l_s_addr_acked$next[0:0]$8717 - attribute \src "libresoc.v:161524.3-161562.6" - wire width 2 $3\fsm_state$next[1:0]$8703 - attribute \src "libresoc.v:161397.3-161427.6" + attribute \src "libresoc.v:162386.3-162421.6" + wire $3\adrok_l_s_addr_acked$next[0:0]$8649 + attribute \src "libresoc.v:162292.3-162330.6" + wire width 2 $3\fsm_state$next[1:0]$8635 + attribute \src "libresoc.v:162165.3-162195.6" wire $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161319.3-161344.6" + attribute \src "libresoc.v:162087.3-162112.6" wire $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161371.3-161396.6" + attribute \src "libresoc.v:162139.3-162164.6" wire width 48 $3\x_addr_i[47:0] - attribute \src "libresoc.v:161345.3-161370.6" + attribute \src "libresoc.v:162113.3-162138.6" wire width 8 $3\x_mask_i[7:0] - attribute \src "libresoc.v:161618.3-161653.6" - wire $4\adrok_l_s_addr_acked$next[0:0]$8718 - attribute \src "libresoc.v:161524.3-161562.6" - wire width 2 $4\fsm_state$next[1:0]$8704 - attribute \src "libresoc.v:161397.3-161427.6" + attribute \src "libresoc.v:162386.3-162421.6" + wire $4\adrok_l_s_addr_acked$next[0:0]$8650 + attribute \src "libresoc.v:162292.3-162330.6" + wire width 2 $4\fsm_state$next[1:0]$8636 + attribute \src "libresoc.v:162165.3-162195.6" wire $4\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161319.3-161344.6" + attribute \src "libresoc.v:162087.3-162112.6" wire $4\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161371.3-161396.6" + attribute \src "libresoc.v:162139.3-162164.6" wire width 48 $4\x_addr_i[47:0] - attribute \src "libresoc.v:161345.3-161370.6" + attribute \src "libresoc.v:162113.3-162138.6" wire width 8 $4\x_mask_i[7:0] - attribute \src "libresoc.v:161618.3-161653.6" - wire $5\adrok_l_s_addr_acked$next[0:0]$8719 - attribute \src "libresoc.v:161524.3-161562.6" - wire width 2 $5\fsm_state$next[1:0]$8705 - attribute \src "libresoc.v:161397.3-161427.6" + attribute \src "libresoc.v:162386.3-162421.6" + wire $5\adrok_l_s_addr_acked$next[0:0]$8651 + attribute \src "libresoc.v:162292.3-162330.6" + wire width 2 $5\fsm_state$next[1:0]$8637 + attribute \src "libresoc.v:162165.3-162195.6" wire $5\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161618.3-161653.6" - wire $6\adrok_l_s_addr_acked$next[0:0]$8720 - attribute \src "libresoc.v:161124.18-161124.115" - wire $and$libresoc.v:161124$8626_Y - attribute \src "libresoc.v:161126.18-161126.95" - wire $and$libresoc.v:161126$8628_Y - attribute \src "libresoc.v:161128.17-161128.138" - wire $and$libresoc.v:161128$8630_Y - attribute \src "libresoc.v:161129.18-161129.95" - wire $and$libresoc.v:161129$8631_Y - attribute \src "libresoc.v:161132.18-161132.136" - wire $and$libresoc.v:161132$8636_Y - attribute \src "libresoc.v:161133.18-161133.136" - wire $and$libresoc.v:161133$8637_Y - attribute \src "libresoc.v:161134.18-161134.136" - wire $and$libresoc.v:161134$8638_Y - attribute \src "libresoc.v:161135.18-161135.136" - wire $and$libresoc.v:161135$8639_Y - attribute \src "libresoc.v:161136.18-161136.136" - wire $and$libresoc.v:161136$8640_Y - attribute \src "libresoc.v:161141.18-161141.119" - wire width 176 $and$libresoc.v:161141$8645_Y - attribute \src "libresoc.v:161144.18-161144.136" - wire $and$libresoc.v:161144$8648_Y - attribute \src "libresoc.v:161145.18-161145.136" - wire $and$libresoc.v:161145$8649_Y - attribute \src "libresoc.v:161147.18-161147.139" - wire $and$libresoc.v:161147$8651_Y - attribute \src "libresoc.v:161151.18-161151.139" - wire $and$libresoc.v:161151$8655_Y - attribute \src "libresoc.v:161153.18-161153.114" - wire $and$libresoc.v:161153$8657_Y - attribute \src "libresoc.v:161155.18-161155.114" - wire $and$libresoc.v:161155$8659_Y - attribute \src "libresoc.v:161159.18-161159.103" - wire $and$libresoc.v:161159$8663_Y - attribute \src "libresoc.v:161160.17-161160.135" - wire $and$libresoc.v:161160$8664_Y - attribute \src "libresoc.v:161163.18-161163.103" - wire $and$libresoc.v:161163$8667_Y - attribute \src "libresoc.v:161130.18-161130.109" - wire width 4 $extend$libresoc.v:161130$8632_Y - attribute \src "libresoc.v:161131.18-161131.109" - wire width 4 $extend$libresoc.v:161131$8634_Y - attribute \src "libresoc.v:161142.18-161142.112" - wire width 8 $mul$libresoc.v:161142$8646_Y - attribute \src "libresoc.v:161148.18-161148.112" - wire width 8 $mul$libresoc.v:161148$8652_Y - attribute \src "libresoc.v:161123.17-161123.103" - wire $not$libresoc.v:161123$8625_Y - attribute \src "libresoc.v:161125.18-161125.94" - wire $not$libresoc.v:161125$8627_Y - attribute \src "libresoc.v:161127.18-161127.94" - wire $not$libresoc.v:161127$8629_Y - attribute \src "libresoc.v:161137.18-161137.102" - wire $not$libresoc.v:161137$8641_Y - attribute \src "libresoc.v:161140.18-161140.97" - wire $not$libresoc.v:161140$8644_Y - attribute \src "libresoc.v:161146.18-161146.102" - wire $not$libresoc.v:161146$8650_Y - attribute \src "libresoc.v:161149.17-161149.103" - wire $not$libresoc.v:161149$8653_Y - attribute \src "libresoc.v:161156.18-161156.101" - wire $not$libresoc.v:161156$8660_Y - attribute \src "libresoc.v:161157.18-161157.111" - wire $not$libresoc.v:161157$8661_Y - attribute \src "libresoc.v:161158.18-161158.110" - wire $not$libresoc.v:161158$8662_Y - attribute \src "libresoc.v:161161.18-161161.102" - wire $not$libresoc.v:161161$8665_Y - attribute \src "libresoc.v:161162.18-161162.102" - wire $not$libresoc.v:161162$8666_Y - attribute \src "libresoc.v:161138.18-161138.111" - wire $or$libresoc.v:161138$8642_Y - attribute \src "libresoc.v:161139.17-161139.130" - wire $or$libresoc.v:161139$8643_Y - attribute \src "libresoc.v:161152.18-161152.130" - wire $or$libresoc.v:161152$8656_Y - attribute \src "libresoc.v:161154.18-161154.130" - wire $or$libresoc.v:161154$8658_Y - attribute \src "libresoc.v:161130.18-161130.109" - wire width 4 $pos$libresoc.v:161130$8633_Y - attribute \src "libresoc.v:161131.18-161131.109" - wire width 4 $pos$libresoc.v:161131$8635_Y - attribute \src "libresoc.v:161150.18-161150.121" - wire width 319 $sshl$libresoc.v:161150$8654_Y - attribute \src "libresoc.v:161143.18-161143.106" - wire width 176 $sshr$libresoc.v:161143$8647_Y + attribute \src "libresoc.v:162386.3-162421.6" + wire $6\adrok_l_s_addr_acked$next[0:0]$8652 + attribute \src "libresoc.v:161892.18-161892.115" + wire $and$libresoc.v:161892$8558_Y + attribute \src "libresoc.v:161894.18-161894.95" + wire $and$libresoc.v:161894$8560_Y + attribute \src "libresoc.v:161896.17-161896.138" + wire $and$libresoc.v:161896$8562_Y + attribute \src "libresoc.v:161897.18-161897.95" + wire $and$libresoc.v:161897$8563_Y + attribute \src "libresoc.v:161900.18-161900.136" + wire $and$libresoc.v:161900$8568_Y + attribute \src "libresoc.v:161901.18-161901.136" + wire $and$libresoc.v:161901$8569_Y + attribute \src "libresoc.v:161902.18-161902.136" + wire $and$libresoc.v:161902$8570_Y + attribute \src "libresoc.v:161903.18-161903.136" + wire $and$libresoc.v:161903$8571_Y + attribute \src "libresoc.v:161904.18-161904.136" + wire $and$libresoc.v:161904$8572_Y + attribute \src "libresoc.v:161909.18-161909.119" + wire width 176 $and$libresoc.v:161909$8577_Y + attribute \src "libresoc.v:161912.18-161912.136" + wire $and$libresoc.v:161912$8580_Y + attribute \src "libresoc.v:161913.18-161913.136" + wire $and$libresoc.v:161913$8581_Y + attribute \src "libresoc.v:161915.18-161915.139" + wire $and$libresoc.v:161915$8583_Y + attribute \src "libresoc.v:161919.18-161919.139" + wire $and$libresoc.v:161919$8587_Y + attribute \src "libresoc.v:161921.18-161921.114" + wire $and$libresoc.v:161921$8589_Y + attribute \src "libresoc.v:161923.18-161923.114" + wire $and$libresoc.v:161923$8591_Y + attribute \src "libresoc.v:161927.18-161927.103" + wire $and$libresoc.v:161927$8595_Y + attribute \src "libresoc.v:161928.17-161928.135" + wire $and$libresoc.v:161928$8596_Y + attribute \src "libresoc.v:161931.18-161931.103" + wire $and$libresoc.v:161931$8599_Y + attribute \src "libresoc.v:161898.18-161898.109" + wire width 4 $extend$libresoc.v:161898$8564_Y + attribute \src "libresoc.v:161899.18-161899.109" + wire width 4 $extend$libresoc.v:161899$8566_Y + attribute \src "libresoc.v:161910.18-161910.112" + wire width 8 $mul$libresoc.v:161910$8578_Y + attribute \src "libresoc.v:161916.18-161916.112" + wire width 8 $mul$libresoc.v:161916$8584_Y + attribute \src "libresoc.v:161891.17-161891.103" + wire $not$libresoc.v:161891$8557_Y + attribute \src "libresoc.v:161893.18-161893.94" + wire $not$libresoc.v:161893$8559_Y + attribute \src "libresoc.v:161895.18-161895.94" + wire $not$libresoc.v:161895$8561_Y + attribute \src "libresoc.v:161905.18-161905.102" + wire $not$libresoc.v:161905$8573_Y + attribute \src "libresoc.v:161908.18-161908.97" + wire $not$libresoc.v:161908$8576_Y + attribute \src "libresoc.v:161914.18-161914.102" + wire $not$libresoc.v:161914$8582_Y + attribute \src "libresoc.v:161917.17-161917.103" + wire $not$libresoc.v:161917$8585_Y + attribute \src "libresoc.v:161924.18-161924.101" + wire $not$libresoc.v:161924$8592_Y + attribute \src "libresoc.v:161925.18-161925.111" + wire $not$libresoc.v:161925$8593_Y + attribute \src "libresoc.v:161926.18-161926.110" + wire $not$libresoc.v:161926$8594_Y + attribute \src "libresoc.v:161929.18-161929.102" + wire $not$libresoc.v:161929$8597_Y + attribute \src "libresoc.v:161930.18-161930.102" + wire $not$libresoc.v:161930$8598_Y + attribute \src "libresoc.v:161906.18-161906.111" + wire $or$libresoc.v:161906$8574_Y + attribute \src "libresoc.v:161907.17-161907.130" + wire $or$libresoc.v:161907$8575_Y + attribute \src "libresoc.v:161920.18-161920.130" + wire $or$libresoc.v:161920$8588_Y + attribute \src "libresoc.v:161922.18-161922.130" + wire $or$libresoc.v:161922$8590_Y + attribute \src "libresoc.v:161898.18-161898.109" + wire width 4 $pos$libresoc.v:161898$8565_Y + attribute \src "libresoc.v:161899.18-161899.109" + wire width 4 $pos$libresoc.v:161899$8567_Y + attribute \src "libresoc.v:161918.18-161918.121" + wire width 319 $sshl$libresoc.v:161918$8586_Y + attribute \src "libresoc.v:161911.18-161911.106" + wire width 176 $sshr$libresoc.v:161911$8579_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" @@ -334266,9 +300809,9 @@ module \pimem wire \busy_l_r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \busy_l_s_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \cyc_l_q_cyc @@ -334280,7 +300823,7 @@ module \pimem wire width 2 \fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" wire width 2 \fsm_state$next - attribute \src "libresoc.v:160878.7-160878.15" + attribute \src "libresoc.v:161646.7-161646.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \ld_active_q_ld_active @@ -334298,9 +300841,9 @@ module \pimem wire \lds_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \lds_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 48 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 7 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire output 10 \ldst_port0_addr_ok_o @@ -334314,13 +300857,13 @@ module \pimem wire input 2 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire input 3 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 12 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 13 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 15 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 14 \ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" wire width 4 \lenexp_addr_i @@ -334399,7 +300942,7 @@ module \pimem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire output 22 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $and $and$libresoc.v:161124$8626 + cell $and $and$libresoc.v:161892$8558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334407,10 +300950,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o connect \B \$9 - connect \Y $and$libresoc.v:161124$8626_Y + connect \Y $and$libresoc.v:161892$8558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:161126$8628 + cell $and $and$libresoc.v:161894$8560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334418,10 +300961,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lds connect \B \$13 - connect \Y $and$libresoc.v:161126$8628_Y + connect \Y $and$libresoc.v:161894$8560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:161128$8630 + cell $and $and$libresoc.v:161896$8562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334429,10 +300972,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:161128$8630_Y + connect \Y $and$libresoc.v:161896$8562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:161129$8631 + cell $and $and$libresoc.v:161897$8563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334440,10 +300983,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \sts connect \B \$17 - connect \Y $and$libresoc.v:161129$8631_Y + connect \Y $and$libresoc.v:161897$8563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161132$8636 + cell $and $and$libresoc.v:161900$8568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334451,10 +300994,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161132$8636_Y + connect \Y $and$libresoc.v:161900$8568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161133$8637 + cell $and $and$libresoc.v:161901$8569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334462,10 +301005,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161133$8637_Y + connect \Y $and$libresoc.v:161901$8569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161134$8638 + cell $and $and$libresoc.v:161902$8570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334473,10 +301016,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161134$8638_Y + connect \Y $and$libresoc.v:161902$8570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161135$8639 + cell $and $and$libresoc.v:161903$8571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334484,10 +301027,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161135$8639_Y + connect \Y $and$libresoc.v:161903$8571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:161136$8640 + cell $and $and$libresoc.v:161904$8572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334495,10 +301038,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:161136$8640_Y + connect \Y $and$libresoc.v:161904$8572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" - cell $and $and$libresoc.v:161141$8645 + cell $and $and$libresoc.v:161909$8577 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -334506,10 +301049,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \m_ld_data_o connect \B \lenexp_rexp_o - connect \Y $and$libresoc.v:161141$8645_Y + connect \Y $and$libresoc.v:161909$8577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:161144$8648 + cell $and $and$libresoc.v:161912$8580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334517,10 +301060,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:161144$8648_Y + connect \Y $and$libresoc.v:161912$8580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:161145$8649 + cell $and $and$libresoc.v:161913$8581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334528,10 +301071,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:161145$8649_Y + connect \Y $and$libresoc.v:161913$8581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:161147$8651 + cell $and $and$libresoc.v:161915$8583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334539,10 +301082,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:161147$8651_Y + connect \Y $and$libresoc.v:161915$8583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:161151$8655 + cell $and $and$libresoc.v:161919$8587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334550,10 +301093,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:161151$8655_Y + connect \Y $and$libresoc.v:161919$8587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:161153$8657 + cell $and $and$libresoc.v:161921$8589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334561,10 +301104,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$63 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:161153$8657_Y + connect \Y $and$libresoc.v:161921$8589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:161155$8659 + cell $and $and$libresoc.v:161923$8591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334572,10 +301115,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$67 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:161155$8659_Y + connect \Y $and$libresoc.v:161923$8591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $and $and$libresoc.v:161159$8663 + cell $and $and$libresoc.v:161927$8595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334583,10 +301126,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$73 connect \B \$75 - connect \Y $and$libresoc.v:161159$8663_Y + connect \Y $and$libresoc.v:161927$8595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161160$8664 + cell $and $and$libresoc.v:161928$8596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334594,10 +301137,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161160$8664_Y + connect \Y $and$libresoc.v:161928$8596_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:161163$8667 + cell $and $and$libresoc.v:161931$8599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334605,26 +301148,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lsui_active connect \B \$81 - connect \Y $and$libresoc.v:161163$8667_Y + connect \Y $and$libresoc.v:161931$8599_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:161130$8632 + cell $pos $extend$libresoc.v:161898$8564 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:161130$8632_Y + connect \Y $extend$libresoc.v:161898$8564_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:161131$8634 + cell $pos $extend$libresoc.v:161899$8566 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:161131$8634_Y + connect \Y $extend$libresoc.v:161899$8566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $mul $mul$libresoc.v:161142$8646 + cell $mul $mul$libresoc.v:161910$8578 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -334632,10 +301175,10 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:161142$8646_Y + connect \Y $mul$libresoc.v:161910$8578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $mul $mul$libresoc.v:161148$8652 + cell $mul $mul$libresoc.v:161916$8584 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -334643,106 +301186,106 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:161148$8652_Y + connect \Y $mul$libresoc.v:161916$8584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $not $not$libresoc.v:161123$8625 + cell $not $not$libresoc.v:161891$8557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:161123$8625_Y + connect \Y $not$libresoc.v:161891$8557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:161125$8627 + cell $not $not$libresoc.v:161893$8559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lds_dly - connect \Y $not$libresoc.v:161125$8627_Y + connect \Y $not$libresoc.v:161893$8559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:161127$8629 + cell $not $not$libresoc.v:161895$8561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sts_dly - connect \Y $not$libresoc.v:161127$8629_Y + connect \Y $not$libresoc.v:161895$8561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:161137$8641 + cell $not $not$libresoc.v:161905$8573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:161137$8641_Y + connect \Y $not$libresoc.v:161905$8573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $not $not$libresoc.v:161140$8644 + cell $not $not$libresoc.v:161908$8576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 - connect \Y $not$libresoc.v:161140$8644_Y + connect \Y $not$libresoc.v:161908$8576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:161146$8650 + cell $not $not$libresoc.v:161914$8582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:161146$8650_Y + connect \Y $not$libresoc.v:161914$8582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" - cell $not $not$libresoc.v:161149$8653 + cell $not $not$libresoc.v:161917$8585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:161149$8653_Y + connect \Y $not$libresoc.v:161917$8585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - cell $not $not$libresoc.v:161156$8660 + cell $not $not$libresoc.v:161924$8592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:161156$8660_Y + connect \Y $not$libresoc.v:161924$8592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:161157$8661 + cell $not $not$libresoc.v:161925$8593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_st_i - connect \Y $not$libresoc.v:161157$8661_Y + connect \Y $not$libresoc.v:161925$8593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:161158$8662 + cell $not $not$libresoc.v:161926$8594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:161158$8662_Y + connect \Y $not$libresoc.v:161926$8594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" - cell $not $not$libresoc.v:161161$8665 + cell $not $not$libresoc.v:161929$8597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:161161$8665_Y + connect \Y $not$libresoc.v:161929$8597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:161162$8666 + cell $not $not$libresoc.v:161930$8598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_active_dly - connect \Y $not$libresoc.v:161162$8666_Y + connect \Y $not$libresoc.v:161930$8598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $or $or$libresoc.v:161138$8642 + cell $or $or$libresoc.v:161906$8574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334750,10 +301293,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \x_busy_o connect \B \lsui_busy - connect \Y $or$libresoc.v:161138$8642_Y + connect \Y $or$libresoc.v:161906$8574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - cell $or $or$libresoc.v:161139$8643 + cell $or $or$libresoc.v:161907$8575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334761,10 +301304,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:161139$8643_Y + connect \Y $or$libresoc.v:161907$8575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:161152$8656 + cell $or $or$libresoc.v:161920$8588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334772,10 +301315,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:161152$8656_Y + connect \Y $or$libresoc.v:161920$8588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:161154$8658 + cell $or $or$libresoc.v:161922$8590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334783,26 +301326,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:161154$8658_Y + connect \Y $or$libresoc.v:161922$8590_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:161130$8633 + cell $pos $pos$libresoc.v:161898$8565 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:161130$8632_Y - connect \Y $pos$libresoc.v:161130$8633_Y + connect \A $extend$libresoc.v:161898$8564_Y + connect \Y $pos$libresoc.v:161898$8565_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:161131$8635 + cell $pos $pos$libresoc.v:161899$8567 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:161131$8634_Y - connect \Y $pos$libresoc.v:161131$8635_Y + connect \A $extend$libresoc.v:161899$8566_Y + connect \Y $pos$libresoc.v:161899$8567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $sshl $sshl$libresoc.v:161150$8654 + cell $sshl $sshl$libresoc.v:161918$8586 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -334810,10 +301353,10 @@ module \pimem parameter \Y_WIDTH 319 connect \A \ldst_port0_st_data_i connect \B \$57 - connect \Y $sshl$libresoc.v:161150$8654_Y + connect \Y $sshl$libresoc.v:161918$8586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $sshr $sshr$libresoc.v:161143$8647 + cell $sshr $sshr$libresoc.v:161911$8579 parameter \A_SIGNED 0 parameter \A_WIDTH 176 parameter \B_SIGNED 0 @@ -334821,10 +301364,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \$42 connect \B \$44 - connect \Y $sshr$libresoc.v:161143$8647_Y + connect \Y $sshr$libresoc.v:161911$8579_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:161180.11-161187.4" + attribute \src "libresoc.v:161948.11-161955.4" cell \adrok_l \adrok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334834,7 +301377,7 @@ module \pimem connect \s_addr_acked \adrok_l_s_addr_acked end attribute \module_not_derived 1 - attribute \src "libresoc.v:161188.10-161194.4" + attribute \src "libresoc.v:161956.10-161962.4" cell \busy_l \busy_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334843,7 +301386,7 @@ module \pimem connect \s_busy \busy_l_s_busy end attribute \module_not_derived 1 - attribute \src "libresoc.v:161195.9-161201.4" + attribute \src "libresoc.v:161963.9-161969.4" cell \cyc_l \cyc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334852,7 +301395,7 @@ module \pimem connect \s_cyc \cyc_l_s_cyc end attribute \module_not_derived 1 - attribute \src "libresoc.v:161202.13-161208.4" + attribute \src "libresoc.v:161970.13-161976.4" cell \ld_active \ld_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334861,7 +301404,7 @@ module \pimem connect \s_ld_active \ld_active_s_ld_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:161209.10-161214.4" + attribute \src "libresoc.v:161977.10-161982.4" cell \lenexp \lenexp connect \addr_i \lenexp_addr_i connect \len_i \lenexp_len_i @@ -334869,7 +301412,7 @@ module \pimem connect \rexp_o \lenexp_rexp_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:161215.11-161221.4" + attribute \src "libresoc.v:161983.11-161989.4" cell \reset_l \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334878,7 +301421,7 @@ module \pimem connect \s_reset \reset_l_s_reset end attribute \module_not_derived 1 - attribute \src "libresoc.v:161222.13-161228.4" + attribute \src "libresoc.v:161990.13-161996.4" cell \st_active \st_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334887,7 +301430,7 @@ module \pimem connect \s_st_active \st_active_s_st_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:161229.11-161235.4" + attribute \src "libresoc.v:161997.11-162003.4" cell \st_done \st_done connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334896,7 +301439,7 @@ module \pimem connect \s_st_done \st_done_s_st_done end attribute \module_not_derived 1 - attribute \src "libresoc.v:161236.11-161242.4" + attribute \src "libresoc.v:162004.11-162010.4" cell \valid_l \valid_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334904,143 +301447,143 @@ module \pimem connect \r_valid \valid_l_r_valid connect \s_valid \valid_l_s_valid end - attribute \src "libresoc.v:160878.7-160878.20" - process $proc$libresoc.v:160878$8722 + attribute \src "libresoc.v:161646.7-161646.20" + process $proc$libresoc.v:161646$8654 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160972.7-160972.34" - process $proc$libresoc.v:160972$8723 + attribute \src "libresoc.v:161740.7-161740.34" + process $proc$libresoc.v:161740$8655 assign { } { } assign $1\adrok_l_s_addr_acked[0:0] 1'0 sync always sync init update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:160976.7-160976.24" - process $proc$libresoc.v:160976$8724 + attribute \src "libresoc.v:161744.7-161744.24" + process $proc$libresoc.v:161744$8656 assign { } { } assign $1\busy_delay[0:0] 1'0 sync always sync init update \busy_delay $1\busy_delay[0:0] end - attribute \src "libresoc.v:160998.13-160998.29" - process $proc$libresoc.v:160998$8725 + attribute \src "libresoc.v:161766.13-161766.29" + process $proc$libresoc.v:161766$8657 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:161012.7-161012.21" - process $proc$libresoc.v:161012$8726 + attribute \src "libresoc.v:161780.7-161780.21" + process $proc$libresoc.v:161780$8658 assign { } { } assign $1\lds_dly[0:0] 1'0 sync always sync init update \lds_dly $1\lds_dly[0:0] end - attribute \src "libresoc.v:161055.7-161055.29" - process $proc$libresoc.v:161055$8727 + attribute \src "libresoc.v:161823.7-161823.29" + process $proc$libresoc.v:161823$8659 assign { } { } assign $1\lsui_active_dly[0:0] 1'0 sync always sync init update \lsui_active_dly $1\lsui_active_dly[0:0] end - attribute \src "libresoc.v:161067.7-161067.25" - process $proc$libresoc.v:161067$8728 + attribute \src "libresoc.v:161835.7-161835.25" + process $proc$libresoc.v:161835$8660 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:161087.7-161087.31" - process $proc$libresoc.v:161087$8729 + attribute \src "libresoc.v:161855.7-161855.31" + process $proc$libresoc.v:161855$8661 assign { } { } assign $1\st_done_s_st_done[0:0] 1'0 sync always sync init update \st_done_s_st_done $1\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:161095.7-161095.21" - process $proc$libresoc.v:161095$8730 + attribute \src "libresoc.v:161863.7-161863.21" + process $proc$libresoc.v:161863$8662 assign { } { } assign $1\sts_dly[0:0] 1'0 sync always sync init update \sts_dly $1\sts_dly[0:0] end - attribute \src "libresoc.v:161164.3-161165.47" - process $proc$libresoc.v:161164$8668 + attribute \src "libresoc.v:161932.3-161933.47" + process $proc$libresoc.v:161932$8600 assign { } { } assign $0\lsui_active_dly[0:0] \lsui_active_dly$next sync posedge \coresync_clk update \lsui_active_dly $0\lsui_active_dly[0:0] end - attribute \src "libresoc.v:161166.3-161167.35" - process $proc$libresoc.v:161166$8669 + attribute \src "libresoc.v:161934.3-161935.35" + process $proc$libresoc.v:161934$8601 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \coresync_clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:161168.3-161169.36" - process $proc$libresoc.v:161168$8670 + attribute \src "libresoc.v:161936.3-161937.36" + process $proc$libresoc.v:161936$8602 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:161170.3-161171.35" - process $proc$libresoc.v:161170$8671 + attribute \src "libresoc.v:161938.3-161939.35" + process $proc$libresoc.v:161938$8603 assign { } { } assign $0\sts_dly[0:0] \ldst_port0_is_st_i sync posedge \coresync_clk update \sts_dly $0\sts_dly[0:0] end - attribute \src "libresoc.v:161172.3-161173.35" - process $proc$libresoc.v:161172$8672 + attribute \src "libresoc.v:161940.3-161941.35" + process $proc$libresoc.v:161940$8604 assign { } { } assign $0\lds_dly[0:0] \ldst_port0_is_ld_i sync posedge \coresync_clk update \lds_dly $0\lds_dly[0:0] end - attribute \src "libresoc.v:161174.3-161175.37" - process $proc$libresoc.v:161174$8673 + attribute \src "libresoc.v:161942.3-161943.37" + process $proc$libresoc.v:161942$8605 assign { } { } assign $0\busy_delay[0:0] \busy_delay$next sync posedge \coresync_clk update \busy_delay $0\busy_delay[0:0] end - attribute \src "libresoc.v:161176.3-161177.57" - process $proc$libresoc.v:161176$8674 + attribute \src "libresoc.v:161944.3-161945.57" + process $proc$libresoc.v:161944$8606 assign { } { } assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next sync posedge \coresync_clk update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:161178.3-161179.51" - process $proc$libresoc.v:161178$8675 + attribute \src "libresoc.v:161946.3-161947.51" + process $proc$libresoc.v:161946$8607 assign { } { } assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next sync posedge \coresync_clk update \st_done_s_st_done $0\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:161243.3-161257.6" - process $proc$libresoc.v:161243$8676 + attribute \src "libresoc.v:162011.3-162025.6" + process $proc$libresoc.v:162011$8608 assign { } { } assign { } { } assign { } { } - assign $0\st_done_s_st_done$next[0:0]$8677 $2\st_done_s_st_done$next[0:0]$8679 - attribute \src "libresoc.v:161244.5-161244.29" + assign $0\st_done_s_st_done$next[0:0]$8609 $2\st_done_s_st_done$next[0:0]$8611 + attribute \src "libresoc.v:162012.5-162012.29" switch \initial - attribute \src "libresoc.v:161244.9-161244.17" + attribute \src "libresoc.v:162012.9-162012.17" case 1'1 case end @@ -335049,30 +301592,30 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\st_done_s_st_done$next[0:0]$8678 1'1 + assign $1\st_done_s_st_done$next[0:0]$8610 1'1 case - assign $1\st_done_s_st_done$next[0:0]$8678 1'0 + assign $1\st_done_s_st_done$next[0:0]$8610 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\st_done_s_st_done$next[0:0]$8679 1'0 + assign $2\st_done_s_st_done$next[0:0]$8611 1'0 case - assign $2\st_done_s_st_done$next[0:0]$8679 $1\st_done_s_st_done$next[0:0]$8678 + assign $2\st_done_s_st_done$next[0:0]$8611 $1\st_done_s_st_done$next[0:0]$8610 end sync always - update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8677 + update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8609 end - attribute \src "libresoc.v:161258.3-161267.6" - process $proc$libresoc.v:161258$8680 + attribute \src "libresoc.v:162026.3-162035.6" + process $proc$libresoc.v:162026$8612 assign { } { } assign { } { } assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:161259.5-161259.29" + attribute \src "libresoc.v:162027.5-162027.29" switch \initial - attribute \src "libresoc.v:161259.9-161259.17" + attribute \src "libresoc.v:162027.9-162027.17" case 1'1 case end @@ -335088,14 +301631,14 @@ module \pimem sync always update \st_done_r_st_done $0\st_done_r_st_done[0:0] end - attribute \src "libresoc.v:161268.3-161276.6" - process $proc$libresoc.v:161268$8681 + attribute \src "libresoc.v:162036.3-162044.6" + process $proc$libresoc.v:162036$8613 assign { } { } assign { } { } - assign $0\busy_delay$next[0:0]$8682 $1\busy_delay$next[0:0]$8683 - attribute \src "libresoc.v:161269.5-161269.29" + assign $0\busy_delay$next[0:0]$8614 $1\busy_delay$next[0:0]$8615 + attribute \src "libresoc.v:162037.5-162037.29" switch \initial - attribute \src "libresoc.v:161269.9-161269.17" + attribute \src "libresoc.v:162037.9-162037.17" case 1'1 case end @@ -335104,21 +301647,21 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\busy_delay$next[0:0]$8683 1'0 + assign $1\busy_delay$next[0:0]$8615 1'0 case - assign $1\busy_delay$next[0:0]$8683 \ldst_port0_busy_o + assign $1\busy_delay$next[0:0]$8615 \ldst_port0_busy_o end sync always - update \busy_delay$next $0\busy_delay$next[0:0]$8682 + update \busy_delay$next $0\busy_delay$next[0:0]$8614 end - attribute \src "libresoc.v:161277.3-161286.6" - process $proc$libresoc.v:161277$8684 + attribute \src "libresoc.v:162045.3-162054.6" + process $proc$libresoc.v:162045$8616 assign { } { } assign { } { } assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:161278.5-161278.29" + attribute \src "libresoc.v:162046.5-162046.29" switch \initial - attribute \src "libresoc.v:161278.9-161278.17" + attribute \src "libresoc.v:162046.9-162046.17" case 1'1 case end @@ -335134,15 +301677,15 @@ module \pimem sync always update \st_active_r_st_active $0\st_active_r_st_active[0:0] end - attribute \src "libresoc.v:161287.3-161302.6" - process $proc$libresoc.v:161287$8685 + attribute \src "libresoc.v:162055.3-162070.6" + process $proc$libresoc.v:162055$8617 assign { } { } assign { } { } assign { } { } assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:161288.5-161288.29" + attribute \src "libresoc.v:162056.5-162056.29" switch \initial - attribute \src "libresoc.v:161288.9-161288.17" + attribute \src "libresoc.v:162056.9-162056.17" case 1'1 case end @@ -335167,15 +301710,15 @@ module \pimem sync always update \lenexp_len_i $0\lenexp_len_i[3:0] end - attribute \src "libresoc.v:161303.3-161318.6" - process $proc$libresoc.v:161303$8686 + attribute \src "libresoc.v:162071.3-162086.6" + process $proc$libresoc.v:162071$8618 assign { } { } assign { } { } assign { } { } assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:161304.5-161304.29" + attribute \src "libresoc.v:162072.5-162072.29" switch \initial - attribute \src "libresoc.v:161304.9-161304.17" + attribute \src "libresoc.v:162072.9-162072.17" case 1'1 case end @@ -335200,15 +301743,15 @@ module \pimem sync always update \lenexp_addr_i $0\lenexp_addr_i[3:0] end - attribute \src "libresoc.v:161319.3-161344.6" - process $proc$libresoc.v:161319$8687 + attribute \src "libresoc.v:162087.3-162112.6" + process $proc$libresoc.v:162087$8619 assign { } { } assign { } { } assign { } { } assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161320.5-161320.29" + attribute \src "libresoc.v:162088.5-162088.29" switch \initial - attribute \src "libresoc.v:161320.9-161320.17" + attribute \src "libresoc.v:162088.9-162088.17" case 1'1 case end @@ -335251,15 +301794,15 @@ module \pimem sync always update \valid_l_s_valid $0\valid_l_s_valid[0:0] end - attribute \src "libresoc.v:161345.3-161370.6" - process $proc$libresoc.v:161345$8688 + attribute \src "libresoc.v:162113.3-162138.6" + process $proc$libresoc.v:162113$8620 assign { } { } assign { } { } assign { } { } assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] - attribute \src "libresoc.v:161346.5-161346.29" + attribute \src "libresoc.v:162114.5-162114.29" switch \initial - attribute \src "libresoc.v:161346.9-161346.17" + attribute \src "libresoc.v:162114.9-162114.17" case 1'1 case end @@ -335302,15 +301845,15 @@ module \pimem sync always update \x_mask_i $0\x_mask_i[7:0] end - attribute \src "libresoc.v:161371.3-161396.6" - process $proc$libresoc.v:161371$8689 + attribute \src "libresoc.v:162139.3-162164.6" + process $proc$libresoc.v:162139$8621 assign { } { } assign { } { } assign { } { } assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] - attribute \src "libresoc.v:161372.5-161372.29" + attribute \src "libresoc.v:162140.5-162140.29" switch \initial - attribute \src "libresoc.v:161372.9-161372.17" + attribute \src "libresoc.v:162140.9-162140.17" case 1'1 case end @@ -335353,15 +301896,15 @@ module \pimem sync always update \x_addr_i $0\x_addr_i[47:0] end - attribute \src "libresoc.v:161397.3-161427.6" - process $proc$libresoc.v:161397$8690 + attribute \src "libresoc.v:162165.3-162195.6" + process $proc$libresoc.v:162165$8622 assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161398.5-161398.29" + attribute \src "libresoc.v:162166.5-162166.29" switch \initial - attribute \src "libresoc.v:161398.9-161398.17" + attribute \src "libresoc.v:162166.9-162166.17" case 1'1 case end @@ -335413,15 +301956,15 @@ module \pimem sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:161428.3-161443.6" - process $proc$libresoc.v:161428$8691 + attribute \src "libresoc.v:162196.3-162211.6" + process $proc$libresoc.v:162196$8623 assign { } { } assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:161429.5-161429.29" + attribute \src "libresoc.v:162197.5-162197.29" switch \initial - attribute \src "libresoc.v:161429.9-161429.17" + attribute \src "libresoc.v:162197.9-162197.17" case 1'1 case end @@ -335446,14 +301989,14 @@ module \pimem sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:161444.3-161453.6" - process $proc$libresoc.v:161444$8692 + attribute \src "libresoc.v:162212.3-162221.6" + process $proc$libresoc.v:162212$8624 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:161445.5-161445.29" + attribute \src "libresoc.v:162213.5-162213.29" switch \initial - attribute \src "libresoc.v:161445.9-161445.17" + attribute \src "libresoc.v:162213.9-162213.17" case 1'1 case end @@ -335469,14 +302012,14 @@ module \pimem sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:161454.3-161463.6" - process $proc$libresoc.v:161454$8693 + attribute \src "libresoc.v:162222.3-162231.6" + process $proc$libresoc.v:162222$8625 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:161455.5-161455.29" + attribute \src "libresoc.v:162223.5-162223.29" switch \initial - attribute \src "libresoc.v:161455.9-161455.17" + attribute \src "libresoc.v:162223.9-162223.17" case 1'1 case end @@ -335492,14 +302035,14 @@ module \pimem sync always update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] end - attribute \src "libresoc.v:161464.3-161473.6" - process $proc$libresoc.v:161464$8694 + attribute \src "libresoc.v:162232.3-162241.6" + process $proc$libresoc.v:162232$8626 assign { } { } assign { } { } assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:161465.5-161465.29" + attribute \src "libresoc.v:162233.5-162233.29" switch \initial - attribute \src "libresoc.v:161465.9-161465.17" + attribute \src "libresoc.v:162233.9-162233.17" case 1'1 case end @@ -335515,14 +302058,14 @@ module \pimem sync always update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] end - attribute \src "libresoc.v:161474.3-161483.6" - process $proc$libresoc.v:161474$8695 + attribute \src "libresoc.v:162242.3-162251.6" + process $proc$libresoc.v:162242$8627 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:161475.5-161475.29" + attribute \src "libresoc.v:162243.5-162243.29" switch \initial - attribute \src "libresoc.v:161475.9-161475.17" + attribute \src "libresoc.v:162243.9-162243.17" case 1'1 case end @@ -335538,14 +302081,14 @@ module \pimem sync always update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:161484.3-161493.6" - process $proc$libresoc.v:161484$8696 + attribute \src "libresoc.v:162252.3-162261.6" + process $proc$libresoc.v:162252$8628 assign { } { } assign { } { } assign $0\stdata[63:0] $1\stdata[63:0] - attribute \src "libresoc.v:161485.5-161485.29" + attribute \src "libresoc.v:162253.5-162253.29" switch \initial - attribute \src "libresoc.v:161485.9-161485.17" + attribute \src "libresoc.v:162253.9-162253.17" case 1'1 case end @@ -335561,14 +302104,14 @@ module \pimem sync always update \stdata $0\stdata[63:0] end - attribute \src "libresoc.v:161494.3-161503.6" - process $proc$libresoc.v:161494$8697 + attribute \src "libresoc.v:162262.3-162271.6" + process $proc$libresoc.v:162262$8629 assign { } { } assign { } { } assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] - attribute \src "libresoc.v:161495.5-161495.29" + attribute \src "libresoc.v:162263.5-162263.29" switch \initial - attribute \src "libresoc.v:161495.9-161495.17" + attribute \src "libresoc.v:162263.9-162263.17" case 1'1 case end @@ -335584,14 +302127,14 @@ module \pimem sync always update \x_st_data_i $0\x_st_data_i[63:0] end - attribute \src "libresoc.v:161504.3-161523.6" - process $proc$libresoc.v:161504$8698 + attribute \src "libresoc.v:162272.3-162291.6" + process $proc$libresoc.v:162272$8630 assign { } { } assign { } { } assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] - attribute \src "libresoc.v:161505.5-161505.29" + attribute \src "libresoc.v:162273.5-162273.29" switch \initial - attribute \src "libresoc.v:161505.9-161505.17" + attribute \src "libresoc.v:162273.9-162273.17" case 1'1 case end @@ -335620,15 +302163,15 @@ module \pimem sync always update \lsui_busy $0\lsui_busy[0:0] end - attribute \src "libresoc.v:161524.3-161562.6" - process $proc$libresoc.v:161524$8699 + attribute \src "libresoc.v:162292.3-162330.6" + process $proc$libresoc.v:162292$8631 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$8700 $5\fsm_state$next[1:0]$8705 - attribute \src "libresoc.v:161525.5-161525.29" + assign $0\fsm_state$next[1:0]$8632 $5\fsm_state$next[1:0]$8637 + attribute \src "libresoc.v:162293.5-162293.29" switch \initial - attribute \src "libresoc.v:161525.9-161525.17" + attribute \src "libresoc.v:162293.9-162293.17" case 1'1 case end @@ -335637,65 +302180,65 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$8701 $2\fsm_state$next[1:0]$8702 + assign $1\fsm_state$next[1:0]$8633 $2\fsm_state$next[1:0]$8634 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$8702 2'01 + assign $2\fsm_state$next[1:0]$8634 2'01 case - assign $2\fsm_state$next[1:0]$8702 \fsm_state + assign $2\fsm_state$next[1:0]$8634 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$8701 $3\fsm_state$next[1:0]$8703 + assign $1\fsm_state$next[1:0]$8633 $3\fsm_state$next[1:0]$8635 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" switch \$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[1:0]$8703 2'10 + assign $3\fsm_state$next[1:0]$8635 2'10 case - assign $3\fsm_state$next[1:0]$8703 \fsm_state + assign $3\fsm_state$next[1:0]$8635 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$8701 $4\fsm_state$next[1:0]$8704 + assign $1\fsm_state$next[1:0]$8633 $4\fsm_state$next[1:0]$8636 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" switch \$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[1:0]$8704 2'00 + assign $4\fsm_state$next[1:0]$8636 2'00 case - assign $4\fsm_state$next[1:0]$8704 \fsm_state + assign $4\fsm_state$next[1:0]$8636 \fsm_state end case - assign $1\fsm_state$next[1:0]$8701 \fsm_state + assign $1\fsm_state$next[1:0]$8633 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[1:0]$8705 2'00 + assign $5\fsm_state$next[1:0]$8637 2'00 case - assign $5\fsm_state$next[1:0]$8705 $1\fsm_state$next[1:0]$8701 + assign $5\fsm_state$next[1:0]$8637 $1\fsm_state$next[1:0]$8633 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$8700 + update \fsm_state$next $0\fsm_state$next[1:0]$8632 end - attribute \src "libresoc.v:161563.3-161572.6" - process $proc$libresoc.v:161563$8706 + attribute \src "libresoc.v:162331.3-162340.6" + process $proc$libresoc.v:162331$8638 assign { } { } assign { } { } assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:161564.5-161564.29" + attribute \src "libresoc.v:162332.5-162332.29" switch \initial - attribute \src "libresoc.v:161564.9-161564.17" + attribute \src "libresoc.v:162332.9-162332.17" case 1'1 case end @@ -335711,14 +302254,14 @@ module \pimem sync always update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] end - attribute \src "libresoc.v:161573.3-161581.6" - process $proc$libresoc.v:161573$8707 + attribute \src "libresoc.v:162341.3-162349.6" + process $proc$libresoc.v:162341$8639 assign { } { } assign { } { } - assign $0\lsui_active_dly$next[0:0]$8708 $1\lsui_active_dly$next[0:0]$8709 - attribute \src "libresoc.v:161574.5-161574.29" + assign $0\lsui_active_dly$next[0:0]$8640 $1\lsui_active_dly$next[0:0]$8641 + attribute \src "libresoc.v:162342.5-162342.29" switch \initial - attribute \src "libresoc.v:161574.9-161574.17" + attribute \src "libresoc.v:162342.9-162342.17" case 1'1 case end @@ -335727,21 +302270,21 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsui_active_dly$next[0:0]$8709 1'0 + assign $1\lsui_active_dly$next[0:0]$8641 1'0 case - assign $1\lsui_active_dly$next[0:0]$8709 \lsui_active + assign $1\lsui_active_dly$next[0:0]$8641 \lsui_active end sync always - update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8708 + update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8640 end - attribute \src "libresoc.v:161582.3-161591.6" - process $proc$libresoc.v:161582$8710 + attribute \src "libresoc.v:162350.3-162359.6" + process $proc$libresoc.v:162350$8642 assign { } { } assign { } { } assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:161583.5-161583.29" + attribute \src "libresoc.v:162351.5-162351.29" switch \initial - attribute \src "libresoc.v:161583.9-161583.17" + attribute \src "libresoc.v:162351.9-162351.17" case 1'1 case end @@ -335757,14 +302300,14 @@ module \pimem sync always update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] end - attribute \src "libresoc.v:161592.3-161601.6" - process $proc$libresoc.v:161592$8711 + attribute \src "libresoc.v:162360.3-162369.6" + process $proc$libresoc.v:162360$8643 assign { } { } assign { } { } assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:161593.5-161593.29" + attribute \src "libresoc.v:162361.5-162361.29" switch \initial - attribute \src "libresoc.v:161593.9-161593.17" + attribute \src "libresoc.v:162361.9-162361.17" case 1'1 case end @@ -335780,15 +302323,15 @@ module \pimem sync always update \busy_l_s_busy $0\busy_l_s_busy[0:0] end - attribute \src "libresoc.v:161602.3-161617.6" - process $proc$libresoc.v:161602$8712 + attribute \src "libresoc.v:162370.3-162385.6" + process $proc$libresoc.v:162370$8644 assign { } { } assign { } { } assign { } { } assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:161603.5-161603.29" + attribute \src "libresoc.v:162371.5-162371.29" switch \initial - attribute \src "libresoc.v:161603.9-161603.17" + attribute \src "libresoc.v:162371.9-162371.17" case 1'1 case end @@ -335813,16 +302356,16 @@ module \pimem sync always update \busy_l_r_busy $0\busy_l_r_busy[0:0] end - attribute \src "libresoc.v:161618.3-161653.6" - process $proc$libresoc.v:161618$8713 + attribute \src "libresoc.v:162386.3-162421.6" + process $proc$libresoc.v:162386$8645 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\adrok_l_s_addr_acked$next[0:0]$8714 $6\adrok_l_s_addr_acked$next[0:0]$8720 - attribute \src "libresoc.v:161619.5-161619.29" + assign $0\adrok_l_s_addr_acked$next[0:0]$8646 $6\adrok_l_s_addr_acked$next[0:0]$8652 + attribute \src "libresoc.v:162387.5-162387.29" switch \initial - attribute \src "libresoc.v:161619.9-161619.17" + attribute \src "libresoc.v:162387.9-162387.17" case 1'1 case end @@ -335831,67 +302374,67 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adrok_l_s_addr_acked$next[0:0]$8715 $2\adrok_l_s_addr_acked$next[0:0]$8716 + assign $1\adrok_l_s_addr_acked$next[0:0]$8647 $2\adrok_l_s_addr_acked$next[0:0]$8648 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\adrok_l_s_addr_acked$next[0:0]$8716 1'1 + assign $2\adrok_l_s_addr_acked$next[0:0]$8648 1'1 case - assign $2\adrok_l_s_addr_acked$next[0:0]$8716 1'0 + assign $2\adrok_l_s_addr_acked$next[0:0]$8648 1'0 end case - assign $1\adrok_l_s_addr_acked$next[0:0]$8715 1'0 + assign $1\adrok_l_s_addr_acked$next[0:0]$8647 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\adrok_l_s_addr_acked$next[0:0]$8717 $4\adrok_l_s_addr_acked$next[0:0]$8718 + assign $3\adrok_l_s_addr_acked$next[0:0]$8649 $4\adrok_l_s_addr_acked$next[0:0]$8650 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\adrok_l_s_addr_acked$next[0:0]$8718 $5\adrok_l_s_addr_acked$next[0:0]$8719 + assign $4\adrok_l_s_addr_acked$next[0:0]$8650 $5\adrok_l_s_addr_acked$next[0:0]$8651 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" switch \adrok_l_qn_addr_acked attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\adrok_l_s_addr_acked$next[0:0]$8719 1'1 + assign $5\adrok_l_s_addr_acked$next[0:0]$8651 1'1 case - assign $5\adrok_l_s_addr_acked$next[0:0]$8719 $1\adrok_l_s_addr_acked$next[0:0]$8715 + assign $5\adrok_l_s_addr_acked$next[0:0]$8651 $1\adrok_l_s_addr_acked$next[0:0]$8647 end case - assign $4\adrok_l_s_addr_acked$next[0:0]$8718 $1\adrok_l_s_addr_acked$next[0:0]$8715 + assign $4\adrok_l_s_addr_acked$next[0:0]$8650 $1\adrok_l_s_addr_acked$next[0:0]$8647 end case - assign $3\adrok_l_s_addr_acked$next[0:0]$8717 $1\adrok_l_s_addr_acked$next[0:0]$8715 + assign $3\adrok_l_s_addr_acked$next[0:0]$8649 $1\adrok_l_s_addr_acked$next[0:0]$8647 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\adrok_l_s_addr_acked$next[0:0]$8720 1'0 + assign $6\adrok_l_s_addr_acked$next[0:0]$8652 1'0 case - assign $6\adrok_l_s_addr_acked$next[0:0]$8720 $3\adrok_l_s_addr_acked$next[0:0]$8717 + assign $6\adrok_l_s_addr_acked$next[0:0]$8652 $3\adrok_l_s_addr_acked$next[0:0]$8649 end sync always - update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8714 + update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8646 end - attribute \src "libresoc.v:161654.3-161669.6" - process $proc$libresoc.v:161654$8721 + attribute \src "libresoc.v:162422.3-162437.6" + process $proc$libresoc.v:162422$8653 assign { } { } assign { } { } assign { } { } assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:161655.5-161655.29" + attribute \src "libresoc.v:162423.5-162423.29" switch \initial - attribute \src "libresoc.v:161655.9-161655.17" + attribute \src "libresoc.v:162423.9-162423.17" case 1'1 case end @@ -335916,47 +302459,47 @@ module \pimem sync always update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] end - connect \$9 $not$libresoc.v:161123$8625_Y - connect \$11 $and$libresoc.v:161124$8626_Y - connect \$13 $not$libresoc.v:161125$8627_Y - connect \$15 $and$libresoc.v:161126$8628_Y - connect \$17 $not$libresoc.v:161127$8629_Y - connect \$1 $and$libresoc.v:161128$8630_Y - connect \$19 $and$libresoc.v:161129$8631_Y - connect \$21 $pos$libresoc.v:161130$8633_Y - connect \$23 $pos$libresoc.v:161131$8635_Y - connect \$25 $and$libresoc.v:161132$8636_Y - connect \$27 $and$libresoc.v:161133$8637_Y - connect \$29 $and$libresoc.v:161134$8638_Y - connect \$31 $and$libresoc.v:161135$8639_Y - connect \$33 $and$libresoc.v:161136$8640_Y - connect \$35 $not$libresoc.v:161137$8641_Y - connect \$38 $or$libresoc.v:161138$8642_Y - connect \$3 $or$libresoc.v:161139$8643_Y - connect \$37 $not$libresoc.v:161140$8644_Y - connect \$42 $and$libresoc.v:161141$8645_Y - connect \$44 $mul$libresoc.v:161142$8646_Y - connect \$46 $sshr$libresoc.v:161143$8647_Y - connect \$48 $and$libresoc.v:161144$8648_Y - connect \$50 $and$libresoc.v:161145$8649_Y - connect \$52 $not$libresoc.v:161146$8650_Y - connect \$54 $and$libresoc.v:161147$8651_Y - connect \$57 $mul$libresoc.v:161148$8652_Y - connect \$5 $not$libresoc.v:161149$8653_Y - connect \$59 $sshl$libresoc.v:161150$8654_Y - connect \$61 $and$libresoc.v:161151$8655_Y - connect \$63 $or$libresoc.v:161152$8656_Y - connect \$65 $and$libresoc.v:161153$8657_Y - connect \$67 $or$libresoc.v:161154$8658_Y - connect \$69 $and$libresoc.v:161155$8659_Y - connect \$71 $not$libresoc.v:161156$8660_Y - connect \$73 $not$libresoc.v:161157$8661_Y - connect \$75 $not$libresoc.v:161158$8662_Y - connect \$77 $and$libresoc.v:161159$8663_Y - connect \$7 $and$libresoc.v:161160$8664_Y - connect \$79 $not$libresoc.v:161161$8665_Y - connect \$81 $not$libresoc.v:161162$8666_Y - connect \$83 $and$libresoc.v:161163$8667_Y + connect \$9 $not$libresoc.v:161891$8557_Y + connect \$11 $and$libresoc.v:161892$8558_Y + connect \$13 $not$libresoc.v:161893$8559_Y + connect \$15 $and$libresoc.v:161894$8560_Y + connect \$17 $not$libresoc.v:161895$8561_Y + connect \$1 $and$libresoc.v:161896$8562_Y + connect \$19 $and$libresoc.v:161897$8563_Y + connect \$21 $pos$libresoc.v:161898$8565_Y + connect \$23 $pos$libresoc.v:161899$8567_Y + connect \$25 $and$libresoc.v:161900$8568_Y + connect \$27 $and$libresoc.v:161901$8569_Y + connect \$29 $and$libresoc.v:161902$8570_Y + connect \$31 $and$libresoc.v:161903$8571_Y + connect \$33 $and$libresoc.v:161904$8572_Y + connect \$35 $not$libresoc.v:161905$8573_Y + connect \$38 $or$libresoc.v:161906$8574_Y + connect \$3 $or$libresoc.v:161907$8575_Y + connect \$37 $not$libresoc.v:161908$8576_Y + connect \$42 $and$libresoc.v:161909$8577_Y + connect \$44 $mul$libresoc.v:161910$8578_Y + connect \$46 $sshr$libresoc.v:161911$8579_Y + connect \$48 $and$libresoc.v:161912$8580_Y + connect \$50 $and$libresoc.v:161913$8581_Y + connect \$52 $not$libresoc.v:161914$8582_Y + connect \$54 $and$libresoc.v:161915$8583_Y + connect \$57 $mul$libresoc.v:161916$8584_Y + connect \$5 $not$libresoc.v:161917$8585_Y + connect \$59 $sshl$libresoc.v:161918$8586_Y + connect \$61 $and$libresoc.v:161919$8587_Y + connect \$63 $or$libresoc.v:161920$8588_Y + connect \$65 $and$libresoc.v:161921$8589_Y + connect \$67 $or$libresoc.v:161922$8590_Y + connect \$69 $and$libresoc.v:161923$8591_Y + connect \$71 $not$libresoc.v:161924$8592_Y + connect \$73 $not$libresoc.v:161925$8593_Y + connect \$75 $not$libresoc.v:161926$8594_Y + connect \$77 $and$libresoc.v:161927$8595_Y + connect \$7 $and$libresoc.v:161928$8596_Y + connect \$79 $not$libresoc.v:161929$8597_Y + connect \$81 $not$libresoc.v:161930$8598_Y + connect \$83 $and$libresoc.v:161931$8599_Y connect \$41 \$46 connect \$56 \$59 connect \valid_l_r_valid \lsui_active_rise @@ -335979,130 +302522,130 @@ module \pimem connect \sts \ldst_port0_is_st_i connect \lds \ldst_port0_is_ld_i end -attribute \src "libresoc.v:161695.1-162475.10" +attribute \src "libresoc.v:162463.1-163243.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" attribute \generator "nMigen" module \pipe - attribute \src "libresoc.v:162438.3-162456.6" - wire width 4 $0\cr_a$6$next[3:0]$8777 - attribute \src "libresoc.v:162302.3-162303.31" - wire width 4 $0\cr_a$6[3:0]$8733 - attribute \src "libresoc.v:161709.13-161709.28" - wire width 4 $0\cr_a$6[3:0]$8783 - attribute \src "libresoc.v:162438.3-162456.6" - wire $0\cr_a_ok$next[0:0]$8776 - attribute \src "libresoc.v:162304.3-162305.31" + attribute \src "libresoc.v:163206.3-163224.6" + wire width 4 $0\cr_a$6$next[3:0]$8709 + attribute \src "libresoc.v:163070.3-163071.31" + wire width 4 $0\cr_a$6[3:0]$8665 + attribute \src "libresoc.v:162477.13-162477.28" + wire width 4 $0\cr_a$6[3:0]$8715 + attribute \src "libresoc.v:163206.3-163224.6" + wire $0\cr_a_ok$next[0:0]$8708 + attribute \src "libresoc.v:163072.3-163073.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:162385.3-162399.6" - wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8757 - attribute \src "libresoc.v:162316.3-162317.51" - wire width 14 $0\cr_op__fn_unit$3[13:0]$8743 - attribute \src "libresoc.v:161774.14-161774.43" - wire width 14 $0\cr_op__fn_unit$3[13:0]$8786 - attribute \src "libresoc.v:162385.3-162399.6" - wire width 32 $0\cr_op__insn$4$next[31:0]$8758 - attribute \src "libresoc.v:162318.3-162319.45" - wire width 32 $0\cr_op__insn$4[31:0]$8745 - attribute \src "libresoc.v:161783.14-161783.37" - wire width 32 $0\cr_op__insn$4[31:0]$8788 - attribute \src "libresoc.v:162385.3-162399.6" - wire width 7 $0\cr_op__insn_type$2$next[6:0]$8759 - attribute \src "libresoc.v:162314.3-162315.55" - wire width 7 $0\cr_op__insn_type$2[6:0]$8741 - attribute \src "libresoc.v:162017.13-162017.41" - wire width 7 $0\cr_op__insn_type$2[6:0]$8790 - attribute \src "libresoc.v:162419.3-162437.6" - wire width 32 $0\full_cr$5$next[31:0]$8770 - attribute \src "libresoc.v:162306.3-162307.37" - wire width 32 $0\full_cr$5[31:0]$8736 - attribute \src "libresoc.v:162026.14-162026.33" - wire width 32 $0\full_cr$5[31:0]$8792 - attribute \src "libresoc.v:162419.3-162437.6" - wire $0\full_cr_ok$next[0:0]$8771 - attribute \src "libresoc.v:162308.3-162309.37" + attribute \src "libresoc.v:163153.3-163167.6" + wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8689 + attribute \src "libresoc.v:163084.3-163085.51" + wire width 14 $0\cr_op__fn_unit$3[13:0]$8675 + attribute \src "libresoc.v:162542.14-162542.43" + wire width 14 $0\cr_op__fn_unit$3[13:0]$8718 + attribute \src "libresoc.v:163153.3-163167.6" + wire width 32 $0\cr_op__insn$4$next[31:0]$8690 + attribute \src "libresoc.v:163086.3-163087.45" + wire width 32 $0\cr_op__insn$4[31:0]$8677 + attribute \src "libresoc.v:162551.14-162551.37" + wire width 32 $0\cr_op__insn$4[31:0]$8720 + attribute \src "libresoc.v:163153.3-163167.6" + wire width 7 $0\cr_op__insn_type$2$next[6:0]$8691 + attribute \src "libresoc.v:163082.3-163083.55" + wire width 7 $0\cr_op__insn_type$2[6:0]$8673 + attribute \src "libresoc.v:162785.13-162785.41" + wire width 7 $0\cr_op__insn_type$2[6:0]$8722 + attribute \src "libresoc.v:163187.3-163205.6" + wire width 32 $0\full_cr$5$next[31:0]$8702 + attribute \src "libresoc.v:163074.3-163075.37" + wire width 32 $0\full_cr$5[31:0]$8668 + attribute \src "libresoc.v:162794.14-162794.33" + wire width 32 $0\full_cr$5[31:0]$8724 + attribute \src "libresoc.v:163187.3-163205.6" + wire $0\full_cr_ok$next[0:0]$8703 + attribute \src "libresoc.v:163076.3-163077.37" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:161696.7-161696.20" + attribute \src "libresoc.v:162464.7-162464.20" wire $0\initial[0:0] - attribute \src "libresoc.v:162372.3-162384.6" - wire width 2 $0\muxid$1$next[1:0]$8754 - attribute \src "libresoc.v:162320.3-162321.33" - wire width 2 $0\muxid$1[1:0]$8747 - attribute \src "libresoc.v:162260.13-162260.29" - wire width 2 $0\muxid$1[1:0]$8795 - attribute \src "libresoc.v:162400.3-162418.6" - wire width 64 $0\o$next[63:0]$8764 - attribute \src "libresoc.v:162310.3-162311.19" + attribute \src "libresoc.v:163140.3-163152.6" + wire width 2 $0\muxid$1$next[1:0]$8686 + attribute \src "libresoc.v:163088.3-163089.33" + wire width 2 $0\muxid$1[1:0]$8679 + attribute \src "libresoc.v:163028.13-163028.29" + wire width 2 $0\muxid$1[1:0]$8727 + attribute \src "libresoc.v:163168.3-163186.6" + wire width 64 $0\o$next[63:0]$8696 + attribute \src "libresoc.v:163078.3-163079.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:162400.3-162418.6" - wire $0\o_ok$next[0:0]$8765 - attribute \src "libresoc.v:162312.3-162313.25" + attribute \src "libresoc.v:163168.3-163186.6" + wire $0\o_ok$next[0:0]$8697 + attribute \src "libresoc.v:163080.3-163081.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:162354.3-162371.6" - wire $0\r_busy$next[0:0]$8750 - attribute \src "libresoc.v:162322.3-162323.29" + attribute \src "libresoc.v:163122.3-163139.6" + wire $0\r_busy$next[0:0]$8682 + attribute \src "libresoc.v:163090.3-163091.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:162438.3-162456.6" - wire width 4 $1\cr_a$6$next[3:0]$8779 - attribute \src "libresoc.v:162438.3-162456.6" - wire $1\cr_a_ok$next[0:0]$8778 - attribute \src "libresoc.v:161714.7-161714.21" + attribute \src "libresoc.v:163206.3-163224.6" + wire width 4 $1\cr_a$6$next[3:0]$8711 + attribute \src "libresoc.v:163206.3-163224.6" + wire $1\cr_a_ok$next[0:0]$8710 + attribute \src "libresoc.v:162482.7-162482.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:162385.3-162399.6" - wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8760 - attribute \src "libresoc.v:162385.3-162399.6" - wire width 32 $1\cr_op__insn$4$next[31:0]$8761 - attribute \src "libresoc.v:162385.3-162399.6" - wire width 7 $1\cr_op__insn_type$2$next[6:0]$8762 - attribute \src "libresoc.v:162419.3-162437.6" - wire width 32 $1\full_cr$5$next[31:0]$8772 - attribute \src "libresoc.v:162419.3-162437.6" - wire $1\full_cr_ok$next[0:0]$8773 - attribute \src "libresoc.v:162031.7-162031.24" + attribute \src "libresoc.v:163153.3-163167.6" + wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8692 + attribute \src "libresoc.v:163153.3-163167.6" + wire width 32 $1\cr_op__insn$4$next[31:0]$8693 + attribute \src "libresoc.v:163153.3-163167.6" + wire width 7 $1\cr_op__insn_type$2$next[6:0]$8694 + attribute \src "libresoc.v:163187.3-163205.6" + wire width 32 $1\full_cr$5$next[31:0]$8704 + attribute \src "libresoc.v:163187.3-163205.6" + wire $1\full_cr_ok$next[0:0]$8705 + attribute \src "libresoc.v:162799.7-162799.24" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:162372.3-162384.6" - wire width 2 $1\muxid$1$next[1:0]$8755 - attribute \src "libresoc.v:162400.3-162418.6" - wire width 64 $1\o$next[63:0]$8766 - attribute \src "libresoc.v:162273.14-162273.38" + attribute \src "libresoc.v:163140.3-163152.6" + wire width 2 $1\muxid$1$next[1:0]$8687 + attribute \src "libresoc.v:163168.3-163186.6" + wire width 64 $1\o$next[63:0]$8698 + attribute \src "libresoc.v:163041.14-163041.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:162400.3-162418.6" - wire $1\o_ok$next[0:0]$8767 - attribute \src "libresoc.v:162280.7-162280.18" + attribute \src "libresoc.v:163168.3-163186.6" + wire $1\o_ok$next[0:0]$8699 + attribute \src "libresoc.v:163048.7-163048.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:162354.3-162371.6" - wire $1\r_busy$next[0:0]$8751 - attribute \src "libresoc.v:162294.7-162294.20" + attribute \src "libresoc.v:163122.3-163139.6" + wire $1\r_busy$next[0:0]$8683 + attribute \src "libresoc.v:163062.7-163062.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:162438.3-162456.6" - wire $2\cr_a_ok$next[0:0]$8780 - attribute \src "libresoc.v:162419.3-162437.6" - wire $2\full_cr_ok$next[0:0]$8774 - attribute \src "libresoc.v:162400.3-162418.6" - wire $2\o_ok$next[0:0]$8768 - attribute \src "libresoc.v:162354.3-162371.6" - wire $2\r_busy$next[0:0]$8752 - attribute \src "libresoc.v:162301.18-162301.118" - wire $and$libresoc.v:162301$8731_Y + attribute \src "libresoc.v:163206.3-163224.6" + wire $2\cr_a_ok$next[0:0]$8712 + attribute \src "libresoc.v:163187.3-163205.6" + wire $2\full_cr_ok$next[0:0]$8706 + attribute \src "libresoc.v:163168.3-163186.6" + wire $2\o_ok$next[0:0]$8700 + attribute \src "libresoc.v:163122.3-163139.6" + wire $2\r_busy$next[0:0]$8684 + attribute \src "libresoc.v:163069.18-163069.118" + wire $and$libresoc.v:163069$8663_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 11 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 24 \cr_a$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 12 \cr_b @@ -336404,25 +302947,25 @@ module \pipe wire width 7 \cr_op__insn_type$2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 input 10 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 \full_cr$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 output 22 \full_cr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 \full_cr$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \full_cr_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \full_cr_ok$next - attribute \src "libresoc.v:161696.7-161696.15" + attribute \src "libresoc.v:162464.7-162464.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \main_cr_a$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_b @@ -336622,17 +303165,17 @@ module \pipe wire width 7 \main_cr_op__insn_type$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 \main_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 \main_full_cr$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_full_cr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_ra @@ -336652,17 +303195,17 @@ module \pipe wire input 15 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 14 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 20 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 21 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o @@ -336681,7 +303224,7 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 9 \rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:162301$8731 + cell $and $and$libresoc.v:163069$8663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -336689,10 +303232,10 @@ module \pipe parameter \Y_WIDTH 1 connect \A \p_valid_i$13 connect \B \p_ready_o - connect \Y $and$libresoc.v:162301$8731_Y + connect \Y $and$libresoc.v:163069$8663_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:162324.12-162345.4" + attribute \src "libresoc.v:163092.12-163113.4" cell \main$9 \main connect \cr_a \main_cr_a connect \cr_a$6 \main_cr_a$12 @@ -336716,199 +303259,199 @@ module \pipe connect \rb \main_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:162346.9-162349.4" + attribute \src "libresoc.v:163114.9-163117.4" cell \n$8 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:162350.9-162353.4" + attribute \src "libresoc.v:163118.9-163121.4" cell \p$7 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:161696.7-161696.20" - process $proc$libresoc.v:161696$8781 + attribute \src "libresoc.v:162464.7-162464.20" + process $proc$libresoc.v:162464$8713 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:161709.13-161709.28" - process $proc$libresoc.v:161709$8782 + attribute \src "libresoc.v:162477.13-162477.28" + process $proc$libresoc.v:162477$8714 assign { } { } - assign $0\cr_a$6[3:0]$8783 4'0000 + assign $0\cr_a$6[3:0]$8715 4'0000 sync always sync init - update \cr_a$6 $0\cr_a$6[3:0]$8783 + update \cr_a$6 $0\cr_a$6[3:0]$8715 end - attribute \src "libresoc.v:161714.7-161714.21" - process $proc$libresoc.v:161714$8784 + attribute \src "libresoc.v:162482.7-162482.21" + process $proc$libresoc.v:162482$8716 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:161774.14-161774.43" - process $proc$libresoc.v:161774$8785 + attribute \src "libresoc.v:162542.14-162542.43" + process $proc$libresoc.v:162542$8717 assign { } { } - assign $0\cr_op__fn_unit$3[13:0]$8786 14'00000000000000 + assign $0\cr_op__fn_unit$3[13:0]$8718 14'00000000000000 sync always sync init - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8786 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8718 end - attribute \src "libresoc.v:161783.14-161783.37" - process $proc$libresoc.v:161783$8787 + attribute \src "libresoc.v:162551.14-162551.37" + process $proc$libresoc.v:162551$8719 assign { } { } - assign $0\cr_op__insn$4[31:0]$8788 0 + assign $0\cr_op__insn$4[31:0]$8720 0 sync always sync init - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8788 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8720 end - attribute \src "libresoc.v:162017.13-162017.41" - process $proc$libresoc.v:162017$8789 + attribute \src "libresoc.v:162785.13-162785.41" + process $proc$libresoc.v:162785$8721 assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8790 7'0000000 + assign $0\cr_op__insn_type$2[6:0]$8722 7'0000000 sync always sync init - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8790 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8722 end - attribute \src "libresoc.v:162026.14-162026.33" - process $proc$libresoc.v:162026$8791 + attribute \src "libresoc.v:162794.14-162794.33" + process $proc$libresoc.v:162794$8723 assign { } { } - assign $0\full_cr$5[31:0]$8792 0 + assign $0\full_cr$5[31:0]$8724 0 sync always sync init - update \full_cr$5 $0\full_cr$5[31:0]$8792 + update \full_cr$5 $0\full_cr$5[31:0]$8724 end - attribute \src "libresoc.v:162031.7-162031.24" - process $proc$libresoc.v:162031$8793 + attribute \src "libresoc.v:162799.7-162799.24" + process $proc$libresoc.v:162799$8725 assign { } { } assign $1\full_cr_ok[0:0] 1'0 sync always sync init update \full_cr_ok $1\full_cr_ok[0:0] end - attribute \src "libresoc.v:162260.13-162260.29" - process $proc$libresoc.v:162260$8794 + attribute \src "libresoc.v:163028.13-163028.29" + process $proc$libresoc.v:163028$8726 assign { } { } - assign $0\muxid$1[1:0]$8795 2'00 + assign $0\muxid$1[1:0]$8727 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8795 + update \muxid$1 $0\muxid$1[1:0]$8727 end - attribute \src "libresoc.v:162273.14-162273.38" - process $proc$libresoc.v:162273$8796 + attribute \src "libresoc.v:163041.14-163041.38" + process $proc$libresoc.v:163041$8728 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:162280.7-162280.18" - process $proc$libresoc.v:162280$8797 + attribute \src "libresoc.v:163048.7-163048.18" + process $proc$libresoc.v:163048$8729 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:162294.7-162294.20" - process $proc$libresoc.v:162294$8798 + attribute \src "libresoc.v:163062.7-163062.20" + process $proc$libresoc.v:163062$8730 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:162302.3-162303.31" - process $proc$libresoc.v:162302$8732 + attribute \src "libresoc.v:163070.3-163071.31" + process $proc$libresoc.v:163070$8664 assign { } { } - assign $0\cr_a$6[3:0]$8733 \cr_a$6$next + assign $0\cr_a$6[3:0]$8665 \cr_a$6$next sync posedge \coresync_clk - update \cr_a$6 $0\cr_a$6[3:0]$8733 + update \cr_a$6 $0\cr_a$6[3:0]$8665 end - attribute \src "libresoc.v:162304.3-162305.31" - process $proc$libresoc.v:162304$8734 + attribute \src "libresoc.v:163072.3-163073.31" + process $proc$libresoc.v:163072$8666 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:162306.3-162307.37" - process $proc$libresoc.v:162306$8735 + attribute \src "libresoc.v:163074.3-163075.37" + process $proc$libresoc.v:163074$8667 assign { } { } - assign $0\full_cr$5[31:0]$8736 \full_cr$5$next + assign $0\full_cr$5[31:0]$8668 \full_cr$5$next sync posedge \coresync_clk - update \full_cr$5 $0\full_cr$5[31:0]$8736 + update \full_cr$5 $0\full_cr$5[31:0]$8668 end - attribute \src "libresoc.v:162308.3-162309.37" - process $proc$libresoc.v:162308$8737 + attribute \src "libresoc.v:163076.3-163077.37" + process $proc$libresoc.v:163076$8669 assign { } { } assign $0\full_cr_ok[0:0] \full_cr_ok$next sync posedge \coresync_clk update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:162310.3-162311.19" - process $proc$libresoc.v:162310$8738 + attribute \src "libresoc.v:163078.3-163079.19" + process $proc$libresoc.v:163078$8670 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:162312.3-162313.25" - process $proc$libresoc.v:162312$8739 + attribute \src "libresoc.v:163080.3-163081.25" + process $proc$libresoc.v:163080$8671 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:162314.3-162315.55" - process $proc$libresoc.v:162314$8740 + attribute \src "libresoc.v:163082.3-163083.55" + process $proc$libresoc.v:163082$8672 assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8741 \cr_op__insn_type$2$next + assign $0\cr_op__insn_type$2[6:0]$8673 \cr_op__insn_type$2$next sync posedge \coresync_clk - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8741 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8673 end - attribute \src "libresoc.v:162316.3-162317.51" - process $proc$libresoc.v:162316$8742 + attribute \src "libresoc.v:163084.3-163085.51" + process $proc$libresoc.v:163084$8674 assign { } { } - assign $0\cr_op__fn_unit$3[13:0]$8743 \cr_op__fn_unit$3$next + assign $0\cr_op__fn_unit$3[13:0]$8675 \cr_op__fn_unit$3$next sync posedge \coresync_clk - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8743 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8675 end - attribute \src "libresoc.v:162318.3-162319.45" - process $proc$libresoc.v:162318$8744 + attribute \src "libresoc.v:163086.3-163087.45" + process $proc$libresoc.v:163086$8676 assign { } { } - assign $0\cr_op__insn$4[31:0]$8745 \cr_op__insn$4$next + assign $0\cr_op__insn$4[31:0]$8677 \cr_op__insn$4$next sync posedge \coresync_clk - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8745 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8677 end - attribute \src "libresoc.v:162320.3-162321.33" - process $proc$libresoc.v:162320$8746 + attribute \src "libresoc.v:163088.3-163089.33" + process $proc$libresoc.v:163088$8678 assign { } { } - assign $0\muxid$1[1:0]$8747 \muxid$1$next + assign $0\muxid$1[1:0]$8679 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8747 + update \muxid$1 $0\muxid$1[1:0]$8679 end - attribute \src "libresoc.v:162322.3-162323.29" - process $proc$libresoc.v:162322$8748 + attribute \src "libresoc.v:163090.3-163091.29" + process $proc$libresoc.v:163090$8680 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:162354.3-162371.6" - process $proc$libresoc.v:162354$8749 + attribute \src "libresoc.v:163122.3-163139.6" + process $proc$libresoc.v:163122$8681 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8750 $2\r_busy$next[0:0]$8752 - attribute \src "libresoc.v:162355.5-162355.29" + assign $0\r_busy$next[0:0]$8682 $2\r_busy$next[0:0]$8684 + attribute \src "libresoc.v:163123.5-163123.29" switch \initial - attribute \src "libresoc.v:162355.9-162355.17" + attribute \src "libresoc.v:163123.9-163123.17" case 1'1 case end @@ -336917,34 +303460,34 @@ module \pipe attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8751 1'1 + assign $1\r_busy$next[0:0]$8683 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8751 1'0 + assign $1\r_busy$next[0:0]$8683 1'0 case - assign $1\r_busy$next[0:0]$8751 \r_busy + assign $1\r_busy$next[0:0]$8683 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8752 1'0 + assign $2\r_busy$next[0:0]$8684 1'0 case - assign $2\r_busy$next[0:0]$8752 $1\r_busy$next[0:0]$8751 + assign $2\r_busy$next[0:0]$8684 $1\r_busy$next[0:0]$8683 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8750 + update \r_busy$next $0\r_busy$next[0:0]$8682 end - attribute \src "libresoc.v:162372.3-162384.6" - process $proc$libresoc.v:162372$8753 + attribute \src "libresoc.v:163140.3-163152.6" + process $proc$libresoc.v:163140$8685 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8754 $1\muxid$1$next[1:0]$8755 - attribute \src "libresoc.v:162373.5-162373.29" + assign $0\muxid$1$next[1:0]$8686 $1\muxid$1$next[1:0]$8687 + attribute \src "libresoc.v:163141.5-163141.29" switch \initial - attribute \src "libresoc.v:162373.9-162373.17" + attribute \src "libresoc.v:163141.9-163141.17" case 1'1 case end @@ -336953,31 +303496,31 @@ module \pipe attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8755 \muxid$16 + assign $1\muxid$1$next[1:0]$8687 \muxid$16 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8755 \muxid$16 + assign $1\muxid$1$next[1:0]$8687 \muxid$16 case - assign $1\muxid$1$next[1:0]$8755 \muxid$1 + assign $1\muxid$1$next[1:0]$8687 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8754 + update \muxid$1$next $0\muxid$1$next[1:0]$8686 end - attribute \src "libresoc.v:162385.3-162399.6" - process $proc$libresoc.v:162385$8756 + attribute \src "libresoc.v:163153.3-163167.6" + process $proc$libresoc.v:163153$8688 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_op__fn_unit$3$next[13:0]$8757 $1\cr_op__fn_unit$3$next[13:0]$8760 - assign $0\cr_op__insn$4$next[31:0]$8758 $1\cr_op__insn$4$next[31:0]$8761 - assign $0\cr_op__insn_type$2$next[6:0]$8759 $1\cr_op__insn_type$2$next[6:0]$8762 - attribute \src "libresoc.v:162386.5-162386.29" + assign $0\cr_op__fn_unit$3$next[13:0]$8689 $1\cr_op__fn_unit$3$next[13:0]$8692 + assign $0\cr_op__insn$4$next[31:0]$8690 $1\cr_op__insn$4$next[31:0]$8693 + assign $0\cr_op__insn_type$2$next[6:0]$8691 $1\cr_op__insn_type$2$next[6:0]$8694 + attribute \src "libresoc.v:163154.5-163154.29" switch \initial - attribute \src "libresoc.v:162386.9-162386.17" + attribute \src "libresoc.v:163154.9-163154.17" case 1'1 case end @@ -336988,35 +303531,35 @@ module \pipe assign { } { } assign { } { } assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8761 $1\cr_op__fn_unit$3$next[13:0]$8760 $1\cr_op__insn_type$2$next[6:0]$8762 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign { $1\cr_op__insn$4$next[31:0]$8693 $1\cr_op__fn_unit$3$next[13:0]$8692 $1\cr_op__insn_type$2$next[6:0]$8694 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8761 $1\cr_op__fn_unit$3$next[13:0]$8760 $1\cr_op__insn_type$2$next[6:0]$8762 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign { $1\cr_op__insn$4$next[31:0]$8693 $1\cr_op__fn_unit$3$next[13:0]$8692 $1\cr_op__insn_type$2$next[6:0]$8694 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } case - assign $1\cr_op__fn_unit$3$next[13:0]$8760 \cr_op__fn_unit$3 - assign $1\cr_op__insn$4$next[31:0]$8761 \cr_op__insn$4 - assign $1\cr_op__insn_type$2$next[6:0]$8762 \cr_op__insn_type$2 + assign $1\cr_op__fn_unit$3$next[13:0]$8692 \cr_op__fn_unit$3 + assign $1\cr_op__insn$4$next[31:0]$8693 \cr_op__insn$4 + assign $1\cr_op__insn_type$2$next[6:0]$8694 \cr_op__insn_type$2 end sync always - update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[13:0]$8757 - update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8758 - update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8759 + update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[13:0]$8689 + update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8690 + update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8691 end - attribute \src "libresoc.v:162400.3-162418.6" - process $proc$libresoc.v:162400$8763 + attribute \src "libresoc.v:163168.3-163186.6" + process $proc$libresoc.v:163168$8695 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8764 $1\o$next[63:0]$8766 + assign $0\o$next[63:0]$8696 $1\o$next[63:0]$8698 assign { } { } - assign $0\o_ok$next[0:0]$8765 $2\o_ok$next[0:0]$8768 - attribute \src "libresoc.v:162401.5-162401.29" + assign $0\o_ok$next[0:0]$8697 $2\o_ok$next[0:0]$8700 + attribute \src "libresoc.v:163169.5-163169.29" switch \initial - attribute \src "libresoc.v:162401.9-162401.17" + attribute \src "libresoc.v:163169.9-163169.17" case 1'1 case end @@ -337026,41 +303569,41 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8767 $1\o$next[63:0]$8766 } { \o_ok$21 \o$20 } + assign { $1\o_ok$next[0:0]$8699 $1\o$next[63:0]$8698 } { \o_ok$21 \o$20 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8767 $1\o$next[63:0]$8766 } { \o_ok$21 \o$20 } + assign { $1\o_ok$next[0:0]$8699 $1\o$next[63:0]$8698 } { \o_ok$21 \o$20 } case - assign $1\o$next[63:0]$8766 \o - assign $1\o_ok$next[0:0]$8767 \o_ok + assign $1\o$next[63:0]$8698 \o + assign $1\o_ok$next[0:0]$8699 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8768 1'0 + assign $2\o_ok$next[0:0]$8700 1'0 case - assign $2\o_ok$next[0:0]$8768 $1\o_ok$next[0:0]$8767 + assign $2\o_ok$next[0:0]$8700 $1\o_ok$next[0:0]$8699 end sync always - update \o$next $0\o$next[63:0]$8764 - update \o_ok$next $0\o_ok$next[0:0]$8765 + update \o$next $0\o$next[63:0]$8696 + update \o_ok$next $0\o_ok$next[0:0]$8697 end - attribute \src "libresoc.v:162419.3-162437.6" - process $proc$libresoc.v:162419$8769 + attribute \src "libresoc.v:163187.3-163205.6" + process $proc$libresoc.v:163187$8701 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\full_cr$5$next[31:0]$8770 $1\full_cr$5$next[31:0]$8772 + assign $0\full_cr$5$next[31:0]$8702 $1\full_cr$5$next[31:0]$8704 assign { } { } - assign $0\full_cr_ok$next[0:0]$8771 $2\full_cr_ok$next[0:0]$8774 - attribute \src "libresoc.v:162420.5-162420.29" + assign $0\full_cr_ok$next[0:0]$8703 $2\full_cr_ok$next[0:0]$8706 + attribute \src "libresoc.v:163188.5-163188.29" switch \initial - attribute \src "libresoc.v:162420.9-162420.17" + attribute \src "libresoc.v:163188.9-163188.17" case 1'1 case end @@ -337070,41 +303613,41 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\full_cr_ok$next[0:0]$8773 $1\full_cr$5$next[31:0]$8772 } { \full_cr_ok$23 \full_cr$22 } + assign { $1\full_cr_ok$next[0:0]$8705 $1\full_cr$5$next[31:0]$8704 } { \full_cr_ok$23 \full_cr$22 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\full_cr_ok$next[0:0]$8773 $1\full_cr$5$next[31:0]$8772 } { \full_cr_ok$23 \full_cr$22 } + assign { $1\full_cr_ok$next[0:0]$8705 $1\full_cr$5$next[31:0]$8704 } { \full_cr_ok$23 \full_cr$22 } case - assign $1\full_cr$5$next[31:0]$8772 \full_cr$5 - assign $1\full_cr_ok$next[0:0]$8773 \full_cr_ok + assign $1\full_cr$5$next[31:0]$8704 \full_cr$5 + assign $1\full_cr_ok$next[0:0]$8705 \full_cr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\full_cr_ok$next[0:0]$8774 1'0 + assign $2\full_cr_ok$next[0:0]$8706 1'0 case - assign $2\full_cr_ok$next[0:0]$8774 $1\full_cr_ok$next[0:0]$8773 + assign $2\full_cr_ok$next[0:0]$8706 $1\full_cr_ok$next[0:0]$8705 end sync always - update \full_cr$5$next $0\full_cr$5$next[31:0]$8770 - update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8771 + update \full_cr$5$next $0\full_cr$5$next[31:0]$8702 + update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8703 end - attribute \src "libresoc.v:162438.3-162456.6" - process $proc$libresoc.v:162438$8775 + attribute \src "libresoc.v:163206.3-163224.6" + process $proc$libresoc.v:163206$8707 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$6$next[3:0]$8777 $1\cr_a$6$next[3:0]$8779 - assign $0\cr_a_ok$next[0:0]$8776 $2\cr_a_ok$next[0:0]$8780 - attribute \src "libresoc.v:162439.5-162439.29" + assign $0\cr_a$6$next[3:0]$8709 $1\cr_a$6$next[3:0]$8711 + assign $0\cr_a_ok$next[0:0]$8708 $2\cr_a_ok$next[0:0]$8712 + attribute \src "libresoc.v:163207.5-163207.29" switch \initial - attribute \src "libresoc.v:162439.9-162439.17" + attribute \src "libresoc.v:163207.9-163207.17" case 1'1 case end @@ -337114,30 +303657,30 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8778 $1\cr_a$6$next[3:0]$8779 } { \cr_a_ok$25 \cr_a$24 } + assign { $1\cr_a_ok$next[0:0]$8710 $1\cr_a$6$next[3:0]$8711 } { \cr_a_ok$25 \cr_a$24 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8778 $1\cr_a$6$next[3:0]$8779 } { \cr_a_ok$25 \cr_a$24 } + assign { $1\cr_a_ok$next[0:0]$8710 $1\cr_a$6$next[3:0]$8711 } { \cr_a_ok$25 \cr_a$24 } case - assign $1\cr_a_ok$next[0:0]$8778 \cr_a_ok - assign $1\cr_a$6$next[3:0]$8779 \cr_a$6 + assign $1\cr_a_ok$next[0:0]$8710 \cr_a_ok + assign $1\cr_a$6$next[3:0]$8711 \cr_a$6 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8780 1'0 + assign $2\cr_a_ok$next[0:0]$8712 1'0 case - assign $2\cr_a_ok$next[0:0]$8780 $1\cr_a_ok$next[0:0]$8778 + assign $2\cr_a_ok$next[0:0]$8712 $1\cr_a_ok$next[0:0]$8710 end sync always - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8776 - update \cr_a$6$next $0\cr_a$6$next[3:0]$8777 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8708 + update \cr_a$6$next $0\cr_a$6$next[3:0]$8709 end - connect \$14 $and$libresoc.v:162301$8731_Y + connect \$14 $and$libresoc.v:163069$8663_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } @@ -337157,155 +303700,155 @@ module \pipe connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:162479.1-163339.10" +attribute \src "libresoc.v:163247.1-164107.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" attribute \generator "nMigen" module \pipe$19 - attribute \src "libresoc.v:163239.3-163266.6" - wire width 64 $0\br_op__cia$2$next[63:0]$8835 - attribute \src "libresoc.v:163151.3-163152.43" - wire width 64 $0\br_op__cia$2[63:0]$8809 - attribute \src "libresoc.v:162487.14-162487.51" - wire width 64 $0\br_op__cia$2[63:0]$8873 - attribute \src "libresoc.v:163239.3-163266.6" - wire width 14 $0\br_op__fn_unit$4$next[13:0]$8836 - attribute \src "libresoc.v:163155.3-163156.51" - wire width 14 $0\br_op__fn_unit$4[13:0]$8813 - attribute \src "libresoc.v:162543.14-162543.43" - wire width 14 $0\br_op__fn_unit$4[13:0]$8875 - attribute \src "libresoc.v:163239.3-163266.6" - wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8837 - attribute \src "libresoc.v:163159.3-163160.65" - wire width 64 $0\br_op__imm_data__data$6[63:0]$8817 - attribute \src "libresoc.v:162552.14-162552.62" - wire width 64 $0\br_op__imm_data__data$6[63:0]$8877 - attribute \src "libresoc.v:163239.3-163266.6" - wire $0\br_op__imm_data__ok$7$next[0:0]$8838 - attribute \src "libresoc.v:163161.3-163162.61" - wire $0\br_op__imm_data__ok$7[0:0]$8819 - attribute \src "libresoc.v:162561.7-162561.37" - wire $0\br_op__imm_data__ok$7[0:0]$8879 - attribute \src "libresoc.v:163239.3-163266.6" - wire width 32 $0\br_op__insn$5$next[31:0]$8839 - attribute \src "libresoc.v:163157.3-163158.45" - wire width 32 $0\br_op__insn$5[31:0]$8815 - attribute \src "libresoc.v:162570.14-162570.37" - wire width 32 $0\br_op__insn$5[31:0]$8881 - attribute \src "libresoc.v:163239.3-163266.6" - wire width 7 $0\br_op__insn_type$3$next[6:0]$8840 - attribute \src "libresoc.v:163153.3-163154.55" - wire width 7 $0\br_op__insn_type$3[6:0]$8811 - attribute \src "libresoc.v:162804.13-162804.41" - wire width 7 $0\br_op__insn_type$3[6:0]$8883 - attribute \src "libresoc.v:163239.3-163266.6" - wire $0\br_op__is_32bit$9$next[0:0]$8841 - attribute \src "libresoc.v:163165.3-163166.53" - wire $0\br_op__is_32bit$9[0:0]$8823 - attribute \src "libresoc.v:162813.7-162813.33" - wire $0\br_op__is_32bit$9[0:0]$8885 - attribute \src "libresoc.v:163239.3-163266.6" - wire $0\br_op__lk$8$next[0:0]$8842 - attribute \src "libresoc.v:163163.3-163164.41" - wire $0\br_op__lk$8[0:0]$8821 - attribute \src "libresoc.v:162822.7-162822.27" - wire $0\br_op__lk$8[0:0]$8887 - attribute \src "libresoc.v:163267.3-163285.6" - wire width 64 $0\fast1$10$next[63:0]$8854 - attribute \src "libresoc.v:163147.3-163148.35" - wire width 64 $0\fast1$10[63:0]$8806 - attribute \src "libresoc.v:162835.14-162835.47" - wire width 64 $0\fast1$10[63:0]$8889 - attribute \src "libresoc.v:163267.3-163285.6" - wire $0\fast1_ok$next[0:0]$8855 - attribute \src "libresoc.v:163149.3-163150.33" + attribute \src "libresoc.v:164007.3-164034.6" + wire width 64 $0\br_op__cia$2$next[63:0]$8767 + attribute \src "libresoc.v:163919.3-163920.43" + wire width 64 $0\br_op__cia$2[63:0]$8741 + attribute \src "libresoc.v:163255.14-163255.51" + wire width 64 $0\br_op__cia$2[63:0]$8805 + attribute \src "libresoc.v:164007.3-164034.6" + wire width 14 $0\br_op__fn_unit$4$next[13:0]$8768 + attribute \src "libresoc.v:163923.3-163924.51" + wire width 14 $0\br_op__fn_unit$4[13:0]$8745 + attribute \src "libresoc.v:163311.14-163311.43" + wire width 14 $0\br_op__fn_unit$4[13:0]$8807 + attribute \src "libresoc.v:164007.3-164034.6" + wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8769 + attribute \src "libresoc.v:163927.3-163928.65" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8749 + attribute \src "libresoc.v:163320.14-163320.62" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8809 + attribute \src "libresoc.v:164007.3-164034.6" + wire $0\br_op__imm_data__ok$7$next[0:0]$8770 + attribute \src "libresoc.v:163929.3-163930.61" + wire $0\br_op__imm_data__ok$7[0:0]$8751 + attribute \src "libresoc.v:163329.7-163329.37" + wire $0\br_op__imm_data__ok$7[0:0]$8811 + attribute \src "libresoc.v:164007.3-164034.6" + wire width 32 $0\br_op__insn$5$next[31:0]$8771 + attribute \src "libresoc.v:163925.3-163926.45" + wire width 32 $0\br_op__insn$5[31:0]$8747 + attribute \src "libresoc.v:163338.14-163338.37" + wire width 32 $0\br_op__insn$5[31:0]$8813 + attribute \src "libresoc.v:164007.3-164034.6" + wire width 7 $0\br_op__insn_type$3$next[6:0]$8772 + attribute \src "libresoc.v:163921.3-163922.55" + wire width 7 $0\br_op__insn_type$3[6:0]$8743 + attribute \src "libresoc.v:163572.13-163572.41" + wire width 7 $0\br_op__insn_type$3[6:0]$8815 + attribute \src "libresoc.v:164007.3-164034.6" + wire $0\br_op__is_32bit$9$next[0:0]$8773 + attribute \src "libresoc.v:163933.3-163934.53" + wire $0\br_op__is_32bit$9[0:0]$8755 + attribute \src "libresoc.v:163581.7-163581.33" + wire $0\br_op__is_32bit$9[0:0]$8817 + attribute \src "libresoc.v:164007.3-164034.6" + wire $0\br_op__lk$8$next[0:0]$8774 + attribute \src "libresoc.v:163931.3-163932.41" + wire $0\br_op__lk$8[0:0]$8753 + attribute \src "libresoc.v:163590.7-163590.27" + wire $0\br_op__lk$8[0:0]$8819 + attribute \src "libresoc.v:164035.3-164053.6" + wire width 64 $0\fast1$10$next[63:0]$8786 + attribute \src "libresoc.v:163915.3-163916.35" + wire width 64 $0\fast1$10[63:0]$8738 + attribute \src "libresoc.v:163603.14-163603.47" + wire width 64 $0\fast1$10[63:0]$8821 + attribute \src "libresoc.v:164035.3-164053.6" + wire $0\fast1_ok$next[0:0]$8787 + attribute \src "libresoc.v:163917.3-163918.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:163286.3-163304.6" - wire width 64 $0\fast2$11$next[63:0]$8860 - attribute \src "libresoc.v:163143.3-163144.35" - wire width 64 $0\fast2$11[63:0]$8803 - attribute \src "libresoc.v:162851.14-162851.47" - wire width 64 $0\fast2$11[63:0]$8892 - attribute \src "libresoc.v:163286.3-163304.6" - wire $0\fast2_ok$next[0:0]$8861 - attribute \src "libresoc.v:163145.3-163146.33" + attribute \src "libresoc.v:164054.3-164072.6" + wire width 64 $0\fast2$11$next[63:0]$8792 + attribute \src "libresoc.v:163911.3-163912.35" + wire width 64 $0\fast2$11[63:0]$8735 + attribute \src "libresoc.v:163619.14-163619.47" + wire width 64 $0\fast2$11[63:0]$8824 + attribute \src "libresoc.v:164054.3-164072.6" + wire $0\fast2_ok$next[0:0]$8793 + attribute \src "libresoc.v:163913.3-163914.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:162480.7-162480.20" + attribute \src "libresoc.v:163248.7-163248.20" wire $0\initial[0:0] - attribute \src "libresoc.v:163226.3-163238.6" - wire width 2 $0\muxid$1$next[1:0]$8832 - attribute \src "libresoc.v:163167.3-163168.33" - wire width 2 $0\muxid$1[1:0]$8825 - attribute \src "libresoc.v:163101.13-163101.29" - wire width 2 $0\muxid$1[1:0]$8895 - attribute \src "libresoc.v:163305.3-163323.6" - wire width 64 $0\nia$next[63:0]$8866 - attribute \src "libresoc.v:163139.3-163140.23" + attribute \src "libresoc.v:163994.3-164006.6" + wire width 2 $0\muxid$1$next[1:0]$8764 + attribute \src "libresoc.v:163935.3-163936.33" + wire width 2 $0\muxid$1[1:0]$8757 + attribute \src "libresoc.v:163869.13-163869.29" + wire width 2 $0\muxid$1[1:0]$8827 + attribute \src "libresoc.v:164073.3-164091.6" + wire width 64 $0\nia$next[63:0]$8798 + attribute \src "libresoc.v:163907.3-163908.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:163305.3-163323.6" - wire $0\nia_ok$next[0:0]$8867 - attribute \src "libresoc.v:163141.3-163142.29" + attribute \src "libresoc.v:164073.3-164091.6" + wire $0\nia_ok$next[0:0]$8799 + attribute \src "libresoc.v:163909.3-163910.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:163208.3-163225.6" - wire $0\r_busy$next[0:0]$8828 - attribute \src "libresoc.v:163169.3-163170.29" + attribute \src "libresoc.v:163976.3-163993.6" + wire $0\r_busy$next[0:0]$8760 + attribute \src "libresoc.v:163937.3-163938.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:163239.3-163266.6" - wire width 64 $1\br_op__cia$2$next[63:0]$8843 - attribute \src "libresoc.v:163239.3-163266.6" - wire width 14 $1\br_op__fn_unit$4$next[13:0]$8844 - attribute \src "libresoc.v:163239.3-163266.6" - wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8845 - attribute \src "libresoc.v:163239.3-163266.6" - wire $1\br_op__imm_data__ok$7$next[0:0]$8846 - attribute \src "libresoc.v:163239.3-163266.6" - wire width 32 $1\br_op__insn$5$next[31:0]$8847 - attribute \src "libresoc.v:163239.3-163266.6" - wire width 7 $1\br_op__insn_type$3$next[6:0]$8848 - attribute \src "libresoc.v:163239.3-163266.6" - wire $1\br_op__is_32bit$9$next[0:0]$8849 - attribute \src "libresoc.v:163239.3-163266.6" - wire $1\br_op__lk$8$next[0:0]$8850 - attribute \src "libresoc.v:163267.3-163285.6" - wire width 64 $1\fast1$10$next[63:0]$8856 - attribute \src "libresoc.v:163267.3-163285.6" - wire $1\fast1_ok$next[0:0]$8857 - attribute \src "libresoc.v:162842.7-162842.22" + attribute \src "libresoc.v:164007.3-164034.6" + wire width 64 $1\br_op__cia$2$next[63:0]$8775 + attribute \src "libresoc.v:164007.3-164034.6" + wire width 14 $1\br_op__fn_unit$4$next[13:0]$8776 + attribute \src "libresoc.v:164007.3-164034.6" + wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8777 + attribute \src "libresoc.v:164007.3-164034.6" + wire $1\br_op__imm_data__ok$7$next[0:0]$8778 + attribute \src "libresoc.v:164007.3-164034.6" + wire width 32 $1\br_op__insn$5$next[31:0]$8779 + attribute \src "libresoc.v:164007.3-164034.6" + wire width 7 $1\br_op__insn_type$3$next[6:0]$8780 + attribute \src "libresoc.v:164007.3-164034.6" + wire $1\br_op__is_32bit$9$next[0:0]$8781 + attribute \src "libresoc.v:164007.3-164034.6" + wire $1\br_op__lk$8$next[0:0]$8782 + attribute \src "libresoc.v:164035.3-164053.6" + wire width 64 $1\fast1$10$next[63:0]$8788 + attribute \src "libresoc.v:164035.3-164053.6" + wire $1\fast1_ok$next[0:0]$8789 + attribute \src "libresoc.v:163610.7-163610.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:163286.3-163304.6" - wire width 64 $1\fast2$11$next[63:0]$8862 - attribute \src "libresoc.v:163286.3-163304.6" - wire $1\fast2_ok$next[0:0]$8863 - attribute \src "libresoc.v:162858.7-162858.22" + attribute \src "libresoc.v:164054.3-164072.6" + wire width 64 $1\fast2$11$next[63:0]$8794 + attribute \src "libresoc.v:164054.3-164072.6" + wire $1\fast2_ok$next[0:0]$8795 + attribute \src "libresoc.v:163626.7-163626.22" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:163226.3-163238.6" - wire width 2 $1\muxid$1$next[1:0]$8833 - attribute \src "libresoc.v:163305.3-163323.6" - wire width 64 $1\nia$next[63:0]$8868 - attribute \src "libresoc.v:163114.14-163114.40" + attribute \src "libresoc.v:163994.3-164006.6" + wire width 2 $1\muxid$1$next[1:0]$8765 + attribute \src "libresoc.v:164073.3-164091.6" + wire width 64 $1\nia$next[63:0]$8800 + attribute \src "libresoc.v:163882.14-163882.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:163305.3-163323.6" - wire $1\nia_ok$next[0:0]$8869 - attribute \src "libresoc.v:163121.7-163121.20" + attribute \src "libresoc.v:164073.3-164091.6" + wire $1\nia_ok$next[0:0]$8801 + attribute \src "libresoc.v:163889.7-163889.20" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:163208.3-163225.6" - wire $1\r_busy$next[0:0]$8829 - attribute \src "libresoc.v:163135.7-163135.20" + attribute \src "libresoc.v:163976.3-163993.6" + wire $1\r_busy$next[0:0]$8761 + attribute \src "libresoc.v:163903.7-163903.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:163239.3-163266.6" - wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8851 - attribute \src "libresoc.v:163239.3-163266.6" - wire $2\br_op__imm_data__ok$7$next[0:0]$8852 - attribute \src "libresoc.v:163267.3-163285.6" - wire $2\fast1_ok$next[0:0]$8858 - attribute \src "libresoc.v:163286.3-163304.6" - wire $2\fast2_ok$next[0:0]$8864 - attribute \src "libresoc.v:163305.3-163323.6" - wire $2\nia_ok$next[0:0]$8870 - attribute \src "libresoc.v:163208.3-163225.6" - wire $2\r_busy$next[0:0]$8830 - attribute \src "libresoc.v:163138.18-163138.118" - wire $and$libresoc.v:163138$8799_Y + attribute \src "libresoc.v:164007.3-164034.6" + wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8783 + attribute \src "libresoc.v:164007.3-164034.6" + wire $2\br_op__imm_data__ok$7$next[0:0]$8784 + attribute \src "libresoc.v:164035.3-164053.6" + wire $2\fast1_ok$next[0:0]$8790 + attribute \src "libresoc.v:164054.3-164072.6" + wire $2\fast2_ok$next[0:0]$8796 + attribute \src "libresoc.v:164073.3-164091.6" + wire $2\nia_ok$next[0:0]$8802 + attribute \src "libresoc.v:163976.3-163993.6" + wire $2\r_busy$next[0:0]$8762 + attribute \src "libresoc.v:163906.18-163906.118" + wire $and$libresoc.v:163906$8731_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -337642,41 +304185,41 @@ module \pipe$19 wire output 25 \br_op__lk$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 15 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 13 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 27 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast1$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast1$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast1_ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 14 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 29 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast2$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast2$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 30 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast2_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast2_ok$next - attribute \src "libresoc.v:162480.7-162480.15" + attribute \src "libresoc.v:163248.7-163248.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_br_op__cia @@ -337894,23 +304437,23 @@ module \pipe$19 wire width 4 \main_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_fast1$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_fast2$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_nia_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -337926,17 +304469,17 @@ module \pipe$19 wire input 17 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 16 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 31 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \nia$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 32 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \nia_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \nia_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o @@ -337951,7 +304494,7 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:163138$8799 + cell $and $and$libresoc.v:163906$8731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -337959,10 +304502,10 @@ module \pipe$19 parameter \Y_WIDTH 1 connect \A \p_valid_i$23 connect \B \p_ready_o - connect \Y $and$libresoc.v:163138$8799_Y + connect \Y $and$libresoc.v:163906$8731_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:163171.13-163199.4" + attribute \src "libresoc.v:163939.13-163967.4" cell \main$22 \main connect \br_op__cia \main_br_op__cia connect \br_op__cia$2 \main_br_op__cia$13 @@ -337993,274 +304536,274 @@ module \pipe$19 connect \nia_ok \main_nia_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:163200.10-163203.4" + attribute \src "libresoc.v:163968.10-163971.4" cell \n$21 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:163204.10-163207.4" + attribute \src "libresoc.v:163972.10-163975.4" cell \p$20 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:162480.7-162480.20" - process $proc$libresoc.v:162480$8871 + attribute \src "libresoc.v:163248.7-163248.20" + process $proc$libresoc.v:163248$8803 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:162487.14-162487.51" - process $proc$libresoc.v:162487$8872 + attribute \src "libresoc.v:163255.14-163255.51" + process $proc$libresoc.v:163255$8804 assign { } { } - assign $0\br_op__cia$2[63:0]$8873 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\br_op__cia$2[63:0]$8805 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8873 + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8805 end - attribute \src "libresoc.v:162543.14-162543.43" - process $proc$libresoc.v:162543$8874 + attribute \src "libresoc.v:163311.14-163311.43" + process $proc$libresoc.v:163311$8806 assign { } { } - assign $0\br_op__fn_unit$4[13:0]$8875 14'00000000000000 + assign $0\br_op__fn_unit$4[13:0]$8807 14'00000000000000 sync always sync init - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8875 + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8807 end - attribute \src "libresoc.v:162552.14-162552.62" - process $proc$libresoc.v:162552$8876 + attribute \src "libresoc.v:163320.14-163320.62" + process $proc$libresoc.v:163320$8808 assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8877 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\br_op__imm_data__data$6[63:0]$8809 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8877 + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8809 end - attribute \src "libresoc.v:162561.7-162561.37" - process $proc$libresoc.v:162561$8878 + attribute \src "libresoc.v:163329.7-163329.37" + process $proc$libresoc.v:163329$8810 assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8879 1'0 + assign $0\br_op__imm_data__ok$7[0:0]$8811 1'0 sync always sync init - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8879 + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8811 end - attribute \src "libresoc.v:162570.14-162570.37" - process $proc$libresoc.v:162570$8880 + attribute \src "libresoc.v:163338.14-163338.37" + process $proc$libresoc.v:163338$8812 assign { } { } - assign $0\br_op__insn$5[31:0]$8881 0 + assign $0\br_op__insn$5[31:0]$8813 0 sync always sync init - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8881 + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8813 end - attribute \src "libresoc.v:162804.13-162804.41" - process $proc$libresoc.v:162804$8882 + attribute \src "libresoc.v:163572.13-163572.41" + process $proc$libresoc.v:163572$8814 assign { } { } - assign $0\br_op__insn_type$3[6:0]$8883 7'0000000 + assign $0\br_op__insn_type$3[6:0]$8815 7'0000000 sync always sync init - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8883 + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8815 end - attribute \src "libresoc.v:162813.7-162813.33" - process $proc$libresoc.v:162813$8884 + attribute \src "libresoc.v:163581.7-163581.33" + process $proc$libresoc.v:163581$8816 assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8885 1'0 + assign $0\br_op__is_32bit$9[0:0]$8817 1'0 sync always sync init - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8885 + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8817 end - attribute \src "libresoc.v:162822.7-162822.27" - process $proc$libresoc.v:162822$8886 + attribute \src "libresoc.v:163590.7-163590.27" + process $proc$libresoc.v:163590$8818 assign { } { } - assign $0\br_op__lk$8[0:0]$8887 1'0 + assign $0\br_op__lk$8[0:0]$8819 1'0 sync always sync init - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8887 + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8819 end - attribute \src "libresoc.v:162835.14-162835.47" - process $proc$libresoc.v:162835$8888 + attribute \src "libresoc.v:163603.14-163603.47" + process $proc$libresoc.v:163603$8820 assign { } { } - assign $0\fast1$10[63:0]$8889 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$10[63:0]$8821 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$10 $0\fast1$10[63:0]$8889 + update \fast1$10 $0\fast1$10[63:0]$8821 end - attribute \src "libresoc.v:162842.7-162842.22" - process $proc$libresoc.v:162842$8890 + attribute \src "libresoc.v:163610.7-163610.22" + process $proc$libresoc.v:163610$8822 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:162851.14-162851.47" - process $proc$libresoc.v:162851$8891 + attribute \src "libresoc.v:163619.14-163619.47" + process $proc$libresoc.v:163619$8823 assign { } { } - assign $0\fast2$11[63:0]$8892 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast2$11[63:0]$8824 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast2$11 $0\fast2$11[63:0]$8892 + update \fast2$11 $0\fast2$11[63:0]$8824 end - attribute \src "libresoc.v:162858.7-162858.22" - process $proc$libresoc.v:162858$8893 + attribute \src "libresoc.v:163626.7-163626.22" + process $proc$libresoc.v:163626$8825 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:163101.13-163101.29" - process $proc$libresoc.v:163101$8894 + attribute \src "libresoc.v:163869.13-163869.29" + process $proc$libresoc.v:163869$8826 assign { } { } - assign $0\muxid$1[1:0]$8895 2'00 + assign $0\muxid$1[1:0]$8827 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8895 + update \muxid$1 $0\muxid$1[1:0]$8827 end - attribute \src "libresoc.v:163114.14-163114.40" - process $proc$libresoc.v:163114$8896 + attribute \src "libresoc.v:163882.14-163882.40" + process $proc$libresoc.v:163882$8828 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:163121.7-163121.20" - process $proc$libresoc.v:163121$8897 + attribute \src "libresoc.v:163889.7-163889.20" + process $proc$libresoc.v:163889$8829 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:163135.7-163135.20" - process $proc$libresoc.v:163135$8898 + attribute \src "libresoc.v:163903.7-163903.20" + process $proc$libresoc.v:163903$8830 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:163139.3-163140.23" - process $proc$libresoc.v:163139$8800 + attribute \src "libresoc.v:163907.3-163908.23" + process $proc$libresoc.v:163907$8732 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \coresync_clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:163141.3-163142.29" - process $proc$libresoc.v:163141$8801 + attribute \src "libresoc.v:163909.3-163910.29" + process $proc$libresoc.v:163909$8733 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:163143.3-163144.35" - process $proc$libresoc.v:163143$8802 + attribute \src "libresoc.v:163911.3-163912.35" + process $proc$libresoc.v:163911$8734 assign { } { } - assign $0\fast2$11[63:0]$8803 \fast2$11$next + assign $0\fast2$11[63:0]$8735 \fast2$11$next sync posedge \coresync_clk - update \fast2$11 $0\fast2$11[63:0]$8803 + update \fast2$11 $0\fast2$11[63:0]$8735 end - attribute \src "libresoc.v:163145.3-163146.33" - process $proc$libresoc.v:163145$8804 + attribute \src "libresoc.v:163913.3-163914.33" + process $proc$libresoc.v:163913$8736 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:163147.3-163148.35" - process $proc$libresoc.v:163147$8805 + attribute \src "libresoc.v:163915.3-163916.35" + process $proc$libresoc.v:163915$8737 assign { } { } - assign $0\fast1$10[63:0]$8806 \fast1$10$next + assign $0\fast1$10[63:0]$8738 \fast1$10$next sync posedge \coresync_clk - update \fast1$10 $0\fast1$10[63:0]$8806 + update \fast1$10 $0\fast1$10[63:0]$8738 end - attribute \src "libresoc.v:163149.3-163150.33" - process $proc$libresoc.v:163149$8807 + attribute \src "libresoc.v:163917.3-163918.33" + process $proc$libresoc.v:163917$8739 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:163151.3-163152.43" - process $proc$libresoc.v:163151$8808 + attribute \src "libresoc.v:163919.3-163920.43" + process $proc$libresoc.v:163919$8740 assign { } { } - assign $0\br_op__cia$2[63:0]$8809 \br_op__cia$2$next + assign $0\br_op__cia$2[63:0]$8741 \br_op__cia$2$next sync posedge \coresync_clk - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8809 + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8741 end - attribute \src "libresoc.v:163153.3-163154.55" - process $proc$libresoc.v:163153$8810 + attribute \src "libresoc.v:163921.3-163922.55" + process $proc$libresoc.v:163921$8742 assign { } { } - assign $0\br_op__insn_type$3[6:0]$8811 \br_op__insn_type$3$next + assign $0\br_op__insn_type$3[6:0]$8743 \br_op__insn_type$3$next sync posedge \coresync_clk - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8811 + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8743 end - attribute \src "libresoc.v:163155.3-163156.51" - process $proc$libresoc.v:163155$8812 + attribute \src "libresoc.v:163923.3-163924.51" + process $proc$libresoc.v:163923$8744 assign { } { } - assign $0\br_op__fn_unit$4[13:0]$8813 \br_op__fn_unit$4$next + assign $0\br_op__fn_unit$4[13:0]$8745 \br_op__fn_unit$4$next sync posedge \coresync_clk - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8813 + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8745 end - attribute \src "libresoc.v:163157.3-163158.45" - process $proc$libresoc.v:163157$8814 + attribute \src "libresoc.v:163925.3-163926.45" + process $proc$libresoc.v:163925$8746 assign { } { } - assign $0\br_op__insn$5[31:0]$8815 \br_op__insn$5$next + assign $0\br_op__insn$5[31:0]$8747 \br_op__insn$5$next sync posedge \coresync_clk - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8815 + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8747 end - attribute \src "libresoc.v:163159.3-163160.65" - process $proc$libresoc.v:163159$8816 + attribute \src "libresoc.v:163927.3-163928.65" + process $proc$libresoc.v:163927$8748 assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8817 \br_op__imm_data__data$6$next + assign $0\br_op__imm_data__data$6[63:0]$8749 \br_op__imm_data__data$6$next sync posedge \coresync_clk - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8817 + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8749 end - attribute \src "libresoc.v:163161.3-163162.61" - process $proc$libresoc.v:163161$8818 + attribute \src "libresoc.v:163929.3-163930.61" + process $proc$libresoc.v:163929$8750 assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8819 \br_op__imm_data__ok$7$next + assign $0\br_op__imm_data__ok$7[0:0]$8751 \br_op__imm_data__ok$7$next sync posedge \coresync_clk - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8819 + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8751 end - attribute \src "libresoc.v:163163.3-163164.41" - process $proc$libresoc.v:163163$8820 + attribute \src "libresoc.v:163931.3-163932.41" + process $proc$libresoc.v:163931$8752 assign { } { } - assign $0\br_op__lk$8[0:0]$8821 \br_op__lk$8$next + assign $0\br_op__lk$8[0:0]$8753 \br_op__lk$8$next sync posedge \coresync_clk - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8821 + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8753 end - attribute \src "libresoc.v:163165.3-163166.53" - process $proc$libresoc.v:163165$8822 + attribute \src "libresoc.v:163933.3-163934.53" + process $proc$libresoc.v:163933$8754 assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8823 \br_op__is_32bit$9$next + assign $0\br_op__is_32bit$9[0:0]$8755 \br_op__is_32bit$9$next sync posedge \coresync_clk - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8823 + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8755 end - attribute \src "libresoc.v:163167.3-163168.33" - process $proc$libresoc.v:163167$8824 + attribute \src "libresoc.v:163935.3-163936.33" + process $proc$libresoc.v:163935$8756 assign { } { } - assign $0\muxid$1[1:0]$8825 \muxid$1$next + assign $0\muxid$1[1:0]$8757 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8825 + update \muxid$1 $0\muxid$1[1:0]$8757 end - attribute \src "libresoc.v:163169.3-163170.29" - process $proc$libresoc.v:163169$8826 + attribute \src "libresoc.v:163937.3-163938.29" + process $proc$libresoc.v:163937$8758 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:163208.3-163225.6" - process $proc$libresoc.v:163208$8827 + attribute \src "libresoc.v:163976.3-163993.6" + process $proc$libresoc.v:163976$8759 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8828 $2\r_busy$next[0:0]$8830 - attribute \src "libresoc.v:163209.5-163209.29" + assign $0\r_busy$next[0:0]$8760 $2\r_busy$next[0:0]$8762 + attribute \src "libresoc.v:163977.5-163977.29" switch \initial - attribute \src "libresoc.v:163209.9-163209.17" + attribute \src "libresoc.v:163977.9-163977.17" case 1'1 case end @@ -338269,34 +304812,34 @@ module \pipe$19 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8829 1'1 + assign $1\r_busy$next[0:0]$8761 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8829 1'0 + assign $1\r_busy$next[0:0]$8761 1'0 case - assign $1\r_busy$next[0:0]$8829 \r_busy + assign $1\r_busy$next[0:0]$8761 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8830 1'0 + assign $2\r_busy$next[0:0]$8762 1'0 case - assign $2\r_busy$next[0:0]$8830 $1\r_busy$next[0:0]$8829 + assign $2\r_busy$next[0:0]$8762 $1\r_busy$next[0:0]$8761 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8828 + update \r_busy$next $0\r_busy$next[0:0]$8760 end - attribute \src "libresoc.v:163226.3-163238.6" - process $proc$libresoc.v:163226$8831 + attribute \src "libresoc.v:163994.3-164006.6" + process $proc$libresoc.v:163994$8763 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8832 $1\muxid$1$next[1:0]$8833 - attribute \src "libresoc.v:163227.5-163227.29" + assign $0\muxid$1$next[1:0]$8764 $1\muxid$1$next[1:0]$8765 + attribute \src "libresoc.v:163995.5-163995.29" switch \initial - attribute \src "libresoc.v:163227.9-163227.17" + attribute \src "libresoc.v:163995.9-163995.17" case 1'1 case end @@ -338305,19 +304848,19 @@ module \pipe$19 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8833 \muxid$26 + assign $1\muxid$1$next[1:0]$8765 \muxid$26 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8833 \muxid$26 + assign $1\muxid$1$next[1:0]$8765 \muxid$26 case - assign $1\muxid$1$next[1:0]$8833 \muxid$1 + assign $1\muxid$1$next[1:0]$8765 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8832 + update \muxid$1$next $0\muxid$1$next[1:0]$8764 end - attribute \src "libresoc.v:163239.3-163266.6" - process $proc$libresoc.v:163239$8834 + attribute \src "libresoc.v:164007.3-164034.6" + process $proc$libresoc.v:164007$8766 assign { } { } assign { } { } assign { } { } @@ -338334,19 +304877,19 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign $0\br_op__cia$2$next[63:0]$8835 $1\br_op__cia$2$next[63:0]$8843 - assign $0\br_op__fn_unit$4$next[13:0]$8836 $1\br_op__fn_unit$4$next[13:0]$8844 + assign $0\br_op__cia$2$next[63:0]$8767 $1\br_op__cia$2$next[63:0]$8775 + assign $0\br_op__fn_unit$4$next[13:0]$8768 $1\br_op__fn_unit$4$next[13:0]$8776 assign { } { } assign { } { } - assign $0\br_op__insn$5$next[31:0]$8839 $1\br_op__insn$5$next[31:0]$8847 - assign $0\br_op__insn_type$3$next[6:0]$8840 $1\br_op__insn_type$3$next[6:0]$8848 - assign $0\br_op__is_32bit$9$next[0:0]$8841 $1\br_op__is_32bit$9$next[0:0]$8849 - assign $0\br_op__lk$8$next[0:0]$8842 $1\br_op__lk$8$next[0:0]$8850 - assign $0\br_op__imm_data__data$6$next[63:0]$8837 $2\br_op__imm_data__data$6$next[63:0]$8851 - assign $0\br_op__imm_data__ok$7$next[0:0]$8838 $2\br_op__imm_data__ok$7$next[0:0]$8852 - attribute \src "libresoc.v:163240.5-163240.29" + assign $0\br_op__insn$5$next[31:0]$8771 $1\br_op__insn$5$next[31:0]$8779 + assign $0\br_op__insn_type$3$next[6:0]$8772 $1\br_op__insn_type$3$next[6:0]$8780 + assign $0\br_op__is_32bit$9$next[0:0]$8773 $1\br_op__is_32bit$9$next[0:0]$8781 + assign $0\br_op__lk$8$next[0:0]$8774 $1\br_op__lk$8$next[0:0]$8782 + assign $0\br_op__imm_data__data$6$next[63:0]$8769 $2\br_op__imm_data__data$6$next[63:0]$8783 + assign $0\br_op__imm_data__ok$7$next[0:0]$8770 $2\br_op__imm_data__ok$7$next[0:0]$8784 + attribute \src "libresoc.v:164008.5-164008.29" switch \initial - attribute \src "libresoc.v:163240.9-163240.17" + attribute \src "libresoc.v:164008.9-164008.17" case 1'1 case end @@ -338362,7 +304905,7 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8849 $1\br_op__lk$8$next[0:0]$8850 $1\br_op__imm_data__ok$7$next[0:0]$8846 $1\br_op__imm_data__data$6$next[63:0]$8845 $1\br_op__insn$5$next[31:0]$8847 $1\br_op__fn_unit$4$next[13:0]$8844 $1\br_op__insn_type$3$next[6:0]$8848 $1\br_op__cia$2$next[63:0]$8843 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { $1\br_op__is_32bit$9$next[0:0]$8781 $1\br_op__lk$8$next[0:0]$8782 $1\br_op__imm_data__ok$7$next[0:0]$8778 $1\br_op__imm_data__data$6$next[63:0]$8777 $1\br_op__insn$5$next[31:0]$8779 $1\br_op__fn_unit$4$next[13:0]$8776 $1\br_op__insn_type$3$next[6:0]$8780 $1\br_op__cia$2$next[63:0]$8775 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -338373,16 +304916,16 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8849 $1\br_op__lk$8$next[0:0]$8850 $1\br_op__imm_data__ok$7$next[0:0]$8846 $1\br_op__imm_data__data$6$next[63:0]$8845 $1\br_op__insn$5$next[31:0]$8847 $1\br_op__fn_unit$4$next[13:0]$8844 $1\br_op__insn_type$3$next[6:0]$8848 $1\br_op__cia$2$next[63:0]$8843 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { $1\br_op__is_32bit$9$next[0:0]$8781 $1\br_op__lk$8$next[0:0]$8782 $1\br_op__imm_data__ok$7$next[0:0]$8778 $1\br_op__imm_data__data$6$next[63:0]$8777 $1\br_op__insn$5$next[31:0]$8779 $1\br_op__fn_unit$4$next[13:0]$8776 $1\br_op__insn_type$3$next[6:0]$8780 $1\br_op__cia$2$next[63:0]$8775 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } case - assign $1\br_op__cia$2$next[63:0]$8843 \br_op__cia$2 - assign $1\br_op__fn_unit$4$next[13:0]$8844 \br_op__fn_unit$4 - assign $1\br_op__imm_data__data$6$next[63:0]$8845 \br_op__imm_data__data$6 - assign $1\br_op__imm_data__ok$7$next[0:0]$8846 \br_op__imm_data__ok$7 - assign $1\br_op__insn$5$next[31:0]$8847 \br_op__insn$5 - assign $1\br_op__insn_type$3$next[6:0]$8848 \br_op__insn_type$3 - assign $1\br_op__is_32bit$9$next[0:0]$8849 \br_op__is_32bit$9 - assign $1\br_op__lk$8$next[0:0]$8850 \br_op__lk$8 + assign $1\br_op__cia$2$next[63:0]$8775 \br_op__cia$2 + assign $1\br_op__fn_unit$4$next[13:0]$8776 \br_op__fn_unit$4 + assign $1\br_op__imm_data__data$6$next[63:0]$8777 \br_op__imm_data__data$6 + assign $1\br_op__imm_data__ok$7$next[0:0]$8778 \br_op__imm_data__ok$7 + assign $1\br_op__insn$5$next[31:0]$8779 \br_op__insn$5 + assign $1\br_op__insn_type$3$next[6:0]$8780 \br_op__insn_type$3 + assign $1\br_op__is_32bit$9$next[0:0]$8781 \br_op__is_32bit$9 + assign $1\br_op__lk$8$next[0:0]$8782 \br_op__lk$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -338390,34 +304933,34 @@ module \pipe$19 case 1'1 assign { } { } assign { } { } - assign $2\br_op__imm_data__data$6$next[63:0]$8851 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\br_op__imm_data__ok$7$next[0:0]$8852 1'0 + assign $2\br_op__imm_data__data$6$next[63:0]$8783 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\br_op__imm_data__ok$7$next[0:0]$8784 1'0 case - assign $2\br_op__imm_data__data$6$next[63:0]$8851 $1\br_op__imm_data__data$6$next[63:0]$8845 - assign $2\br_op__imm_data__ok$7$next[0:0]$8852 $1\br_op__imm_data__ok$7$next[0:0]$8846 + assign $2\br_op__imm_data__data$6$next[63:0]$8783 $1\br_op__imm_data__data$6$next[63:0]$8777 + assign $2\br_op__imm_data__ok$7$next[0:0]$8784 $1\br_op__imm_data__ok$7$next[0:0]$8778 end sync always - update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8835 - update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[13:0]$8836 - update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8837 - update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8838 - update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8839 - update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8840 - update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8841 - update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8842 + update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8767 + update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[13:0]$8768 + update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8769 + update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8770 + update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8771 + update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8772 + update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8773 + update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8774 end - attribute \src "libresoc.v:163267.3-163285.6" - process $proc$libresoc.v:163267$8853 + attribute \src "libresoc.v:164035.3-164053.6" + process $proc$libresoc.v:164035$8785 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$10$next[63:0]$8854 $1\fast1$10$next[63:0]$8856 + assign $0\fast1$10$next[63:0]$8786 $1\fast1$10$next[63:0]$8788 assign { } { } - assign $0\fast1_ok$next[0:0]$8855 $2\fast1_ok$next[0:0]$8858 - attribute \src "libresoc.v:163268.5-163268.29" + assign $0\fast1_ok$next[0:0]$8787 $2\fast1_ok$next[0:0]$8790 + attribute \src "libresoc.v:164036.5-164036.29" switch \initial - attribute \src "libresoc.v:163268.9-163268.17" + attribute \src "libresoc.v:164036.9-164036.17" case 1'1 case end @@ -338427,41 +304970,41 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8857 $1\fast1$10$next[63:0]$8856 } { \fast1_ok$36 \fast1$35 } + assign { $1\fast1_ok$next[0:0]$8789 $1\fast1$10$next[63:0]$8788 } { \fast1_ok$36 \fast1$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8857 $1\fast1$10$next[63:0]$8856 } { \fast1_ok$36 \fast1$35 } + assign { $1\fast1_ok$next[0:0]$8789 $1\fast1$10$next[63:0]$8788 } { \fast1_ok$36 \fast1$35 } case - assign $1\fast1$10$next[63:0]$8856 \fast1$10 - assign $1\fast1_ok$next[0:0]$8857 \fast1_ok + assign $1\fast1$10$next[63:0]$8788 \fast1$10 + assign $1\fast1_ok$next[0:0]$8789 \fast1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8858 1'0 + assign $2\fast1_ok$next[0:0]$8790 1'0 case - assign $2\fast1_ok$next[0:0]$8858 $1\fast1_ok$next[0:0]$8857 + assign $2\fast1_ok$next[0:0]$8790 $1\fast1_ok$next[0:0]$8789 end sync always - update \fast1$10$next $0\fast1$10$next[63:0]$8854 - update \fast1_ok$next $0\fast1_ok$next[0:0]$8855 + update \fast1$10$next $0\fast1$10$next[63:0]$8786 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8787 end - attribute \src "libresoc.v:163286.3-163304.6" - process $proc$libresoc.v:163286$8859 + attribute \src "libresoc.v:164054.3-164072.6" + process $proc$libresoc.v:164054$8791 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast2$11$next[63:0]$8860 $1\fast2$11$next[63:0]$8862 + assign $0\fast2$11$next[63:0]$8792 $1\fast2$11$next[63:0]$8794 assign { } { } - assign $0\fast2_ok$next[0:0]$8861 $2\fast2_ok$next[0:0]$8864 - attribute \src "libresoc.v:163287.5-163287.29" + assign $0\fast2_ok$next[0:0]$8793 $2\fast2_ok$next[0:0]$8796 + attribute \src "libresoc.v:164055.5-164055.29" switch \initial - attribute \src "libresoc.v:163287.9-163287.17" + attribute \src "libresoc.v:164055.9-164055.17" case 1'1 case end @@ -338471,41 +305014,41 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$8863 $1\fast2$11$next[63:0]$8862 } { \fast2_ok$38 \fast2$37 } + assign { $1\fast2_ok$next[0:0]$8795 $1\fast2$11$next[63:0]$8794 } { \fast2_ok$38 \fast2$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$8863 $1\fast2$11$next[63:0]$8862 } { \fast2_ok$38 \fast2$37 } + assign { $1\fast2_ok$next[0:0]$8795 $1\fast2$11$next[63:0]$8794 } { \fast2_ok$38 \fast2$37 } case - assign $1\fast2$11$next[63:0]$8862 \fast2$11 - assign $1\fast2_ok$next[0:0]$8863 \fast2_ok + assign $1\fast2$11$next[63:0]$8794 \fast2$11 + assign $1\fast2_ok$next[0:0]$8795 \fast2_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$8864 1'0 + assign $2\fast2_ok$next[0:0]$8796 1'0 case - assign $2\fast2_ok$next[0:0]$8864 $1\fast2_ok$next[0:0]$8863 + assign $2\fast2_ok$next[0:0]$8796 $1\fast2_ok$next[0:0]$8795 end sync always - update \fast2$11$next $0\fast2$11$next[63:0]$8860 - update \fast2_ok$next $0\fast2_ok$next[0:0]$8861 + update \fast2$11$next $0\fast2$11$next[63:0]$8792 + update \fast2_ok$next $0\fast2_ok$next[0:0]$8793 end - attribute \src "libresoc.v:163305.3-163323.6" - process $proc$libresoc.v:163305$8865 + attribute \src "libresoc.v:164073.3-164091.6" + process $proc$libresoc.v:164073$8797 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$8866 $1\nia$next[63:0]$8868 + assign $0\nia$next[63:0]$8798 $1\nia$next[63:0]$8800 assign { } { } - assign $0\nia_ok$next[0:0]$8867 $2\nia_ok$next[0:0]$8870 - attribute \src "libresoc.v:163306.5-163306.29" + assign $0\nia_ok$next[0:0]$8799 $2\nia_ok$next[0:0]$8802 + attribute \src "libresoc.v:164074.5-164074.29" switch \initial - attribute \src "libresoc.v:163306.9-163306.17" + attribute \src "libresoc.v:164074.9-164074.17" case 1'1 case end @@ -338515,30 +305058,30 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$8869 $1\nia$next[63:0]$8868 } { \nia_ok$40 \nia$39 } + assign { $1\nia_ok$next[0:0]$8801 $1\nia$next[63:0]$8800 } { \nia_ok$40 \nia$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$8869 $1\nia$next[63:0]$8868 } { \nia_ok$40 \nia$39 } + assign { $1\nia_ok$next[0:0]$8801 $1\nia$next[63:0]$8800 } { \nia_ok$40 \nia$39 } case - assign $1\nia$next[63:0]$8868 \nia - assign $1\nia_ok$next[0:0]$8869 \nia_ok + assign $1\nia$next[63:0]$8800 \nia + assign $1\nia_ok$next[0:0]$8801 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$8870 1'0 + assign $2\nia_ok$next[0:0]$8802 1'0 case - assign $2\nia_ok$next[0:0]$8870 $1\nia_ok$next[0:0]$8869 + assign $2\nia_ok$next[0:0]$8802 $1\nia_ok$next[0:0]$8801 end sync always - update \nia$next $0\nia$next[63:0]$8866 - update \nia_ok$next $0\nia_ok$next[0:0]$8867 + update \nia$next $0\nia$next[63:0]$8798 + update \nia_ok$next $0\nia_ok$next[0:0]$8799 end - connect \$24 $and$libresoc.v:163138$8799_Y + connect \$24 $and$libresoc.v:163906$8731_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } @@ -338555,194 +305098,194 @@ module \pipe$19 connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } connect \main_muxid \muxid end -attribute \src "libresoc.v:163343.1-164273.10" +attribute \src "libresoc.v:164111.1-165041.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" attribute \generator "nMigen" module \pipe$64 - attribute \src "libresoc.v:164176.3-164194.6" - wire width 64 $0\fast1$7$next[63:0]$8958 - attribute \src "libresoc.v:164029.3-164030.33" - wire width 64 $0\fast1$7[63:0]$8910 - attribute \src "libresoc.v:163357.14-163357.46" - wire width 64 $0\fast1$7[63:0]$8982 - attribute \src "libresoc.v:164176.3-164194.6" - wire $0\fast1_ok$next[0:0]$8957 - attribute \src "libresoc.v:164031.3-164032.33" + attribute \src "libresoc.v:164944.3-164962.6" + wire width 64 $0\fast1$7$next[63:0]$8890 + attribute \src "libresoc.v:164797.3-164798.33" + wire width 64 $0\fast1$7[63:0]$8842 + attribute \src "libresoc.v:164125.14-164125.46" + wire width 64 $0\fast1$7[63:0]$8914 + attribute \src "libresoc.v:164944.3-164962.6" + wire $0\fast1_ok$next[0:0]$8889 + attribute \src "libresoc.v:164799.3-164800.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:163344.7-163344.20" + attribute \src "libresoc.v:164112.7-164112.20" wire $0\initial[0:0] - attribute \src "libresoc.v:164109.3-164121.6" - wire width 2 $0\muxid$1$next[1:0]$8933 - attribute \src "libresoc.v:164049.3-164050.33" - wire width 2 $0\muxid$1[1:0]$8926 - attribute \src "libresoc.v:163371.13-163371.29" - wire width 2 $0\muxid$1[1:0]$8985 - attribute \src "libresoc.v:164138.3-164156.6" - wire width 64 $0\o$next[63:0]$8945 - attribute \src "libresoc.v:164037.3-164038.19" + attribute \src "libresoc.v:164877.3-164889.6" + wire width 2 $0\muxid$1$next[1:0]$8865 + attribute \src "libresoc.v:164817.3-164818.33" + wire width 2 $0\muxid$1[1:0]$8858 + attribute \src "libresoc.v:164139.13-164139.29" + wire width 2 $0\muxid$1[1:0]$8917 + attribute \src "libresoc.v:164906.3-164924.6" + wire width 64 $0\o$next[63:0]$8877 + attribute \src "libresoc.v:164805.3-164806.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:164138.3-164156.6" - wire $0\o_ok$next[0:0]$8946 - attribute \src "libresoc.v:164039.3-164040.25" + attribute \src "libresoc.v:164906.3-164924.6" + wire $0\o_ok$next[0:0]$8878 + attribute \src "libresoc.v:164807.3-164808.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:164091.3-164108.6" - wire $0\r_busy$next[0:0]$8929 - attribute \src "libresoc.v:164051.3-164052.29" + attribute \src "libresoc.v:164859.3-164876.6" + wire $0\r_busy$next[0:0]$8861 + attribute \src "libresoc.v:164819.3-164820.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:164157.3-164175.6" - wire width 64 $0\spr1$6$next[63:0]$8951 - attribute \src "libresoc.v:164033.3-164034.31" - wire width 64 $0\spr1$6[63:0]$8913 - attribute \src "libresoc.v:163416.14-163416.45" - wire width 64 $0\spr1$6[63:0]$8990 - attribute \src "libresoc.v:164157.3-164175.6" - wire $0\spr1_ok$next[0:0]$8952 - attribute \src "libresoc.v:164035.3-164036.31" + attribute \src "libresoc.v:164925.3-164943.6" + wire width 64 $0\spr1$6$next[63:0]$8883 + attribute \src "libresoc.v:164801.3-164802.31" + wire width 64 $0\spr1$6[63:0]$8845 + attribute \src "libresoc.v:164184.14-164184.45" + wire width 64 $0\spr1$6[63:0]$8922 + attribute \src "libresoc.v:164925.3-164943.6" + wire $0\spr1_ok$next[0:0]$8884 + attribute \src "libresoc.v:164803.3-164804.31" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:164122.3-164137.6" - wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8936 - attribute \src "libresoc.v:164043.3-164044.53" - wire width 14 $0\spr_op__fn_unit$3[13:0]$8920 - attribute \src "libresoc.v:163713.14-163713.44" - wire width 14 $0\spr_op__fn_unit$3[13:0]$8993 - attribute \src "libresoc.v:164122.3-164137.6" - wire width 32 $0\spr_op__insn$4$next[31:0]$8937 - attribute \src "libresoc.v:164045.3-164046.47" - wire width 32 $0\spr_op__insn$4[31:0]$8922 - attribute \src "libresoc.v:163722.14-163722.38" - wire width 32 $0\spr_op__insn$4[31:0]$8995 - attribute \src "libresoc.v:164122.3-164137.6" - wire width 7 $0\spr_op__insn_type$2$next[6:0]$8938 - attribute \src "libresoc.v:164041.3-164042.57" - wire width 7 $0\spr_op__insn_type$2[6:0]$8918 - attribute \src "libresoc.v:163879.13-163879.42" - wire width 7 $0\spr_op__insn_type$2[6:0]$8997 - attribute \src "libresoc.v:164122.3-164137.6" - wire $0\spr_op__is_32bit$5$next[0:0]$8939 - attribute \src "libresoc.v:164047.3-164048.55" - wire $0\spr_op__is_32bit$5[0:0]$8924 - attribute \src "libresoc.v:163965.7-163965.34" - wire $0\spr_op__is_32bit$5[0:0]$8999 - attribute \src "libresoc.v:164233.3-164251.6" - wire width 2 $0\xer_ca$10$next[1:0]$8975 - attribute \src "libresoc.v:164017.3-164018.37" - wire width 2 $0\xer_ca$10[1:0]$8901 - attribute \src "libresoc.v:163972.13-163972.31" - wire width 2 $0\xer_ca$10[1:0]$9001 - attribute \src "libresoc.v:164233.3-164251.6" - wire $0\xer_ca_ok$next[0:0]$8976 - attribute \src "libresoc.v:164019.3-164020.35" + attribute \src "libresoc.v:164890.3-164905.6" + wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8868 + attribute \src "libresoc.v:164811.3-164812.53" + wire width 14 $0\spr_op__fn_unit$3[13:0]$8852 + attribute \src "libresoc.v:164481.14-164481.44" + wire width 14 $0\spr_op__fn_unit$3[13:0]$8925 + attribute \src "libresoc.v:164890.3-164905.6" + wire width 32 $0\spr_op__insn$4$next[31:0]$8869 + attribute \src "libresoc.v:164813.3-164814.47" + wire width 32 $0\spr_op__insn$4[31:0]$8854 + attribute \src "libresoc.v:164490.14-164490.38" + wire width 32 $0\spr_op__insn$4[31:0]$8927 + attribute \src "libresoc.v:164890.3-164905.6" + wire width 7 $0\spr_op__insn_type$2$next[6:0]$8870 + attribute \src "libresoc.v:164809.3-164810.57" + wire width 7 $0\spr_op__insn_type$2[6:0]$8850 + attribute \src "libresoc.v:164647.13-164647.42" + wire width 7 $0\spr_op__insn_type$2[6:0]$8929 + attribute \src "libresoc.v:164890.3-164905.6" + wire $0\spr_op__is_32bit$5$next[0:0]$8871 + attribute \src "libresoc.v:164815.3-164816.55" + wire $0\spr_op__is_32bit$5[0:0]$8856 + attribute \src "libresoc.v:164733.7-164733.34" + wire $0\spr_op__is_32bit$5[0:0]$8931 + attribute \src "libresoc.v:165001.3-165019.6" + wire width 2 $0\xer_ca$10$next[1:0]$8907 + attribute \src "libresoc.v:164785.3-164786.37" + wire width 2 $0\xer_ca$10[1:0]$8833 + attribute \src "libresoc.v:164740.13-164740.31" + wire width 2 $0\xer_ca$10[1:0]$8933 + attribute \src "libresoc.v:165001.3-165019.6" + wire $0\xer_ca_ok$next[0:0]$8908 + attribute \src "libresoc.v:164787.3-164788.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:164214.3-164232.6" - wire width 2 $0\xer_ov$9$next[1:0]$8970 - attribute \src "libresoc.v:164021.3-164022.35" - wire width 2 $0\xer_ov$9[1:0]$8904 - attribute \src "libresoc.v:163990.13-163990.30" - wire width 2 $0\xer_ov$9[1:0]$9004 - attribute \src "libresoc.v:164214.3-164232.6" - wire $0\xer_ov_ok$next[0:0]$8969 - attribute \src "libresoc.v:164023.3-164024.35" + attribute \src "libresoc.v:164982.3-165000.6" + wire width 2 $0\xer_ov$9$next[1:0]$8902 + attribute \src "libresoc.v:164789.3-164790.35" + wire width 2 $0\xer_ov$9[1:0]$8836 + attribute \src "libresoc.v:164758.13-164758.30" + wire width 2 $0\xer_ov$9[1:0]$8936 + attribute \src "libresoc.v:164982.3-165000.6" + wire $0\xer_ov_ok$next[0:0]$8901 + attribute \src "libresoc.v:164791.3-164792.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:164195.3-164213.6" - wire $0\xer_so$8$next[0:0]$8964 - attribute \src "libresoc.v:164025.3-164026.35" - wire $0\xer_so$8[0:0]$8907 - attribute \src "libresoc.v:164006.7-164006.24" - wire $0\xer_so$8[0:0]$9007 - attribute \src "libresoc.v:164195.3-164213.6" - wire $0\xer_so_ok$next[0:0]$8963 - attribute \src "libresoc.v:164027.3-164028.35" + attribute \src "libresoc.v:164963.3-164981.6" + wire $0\xer_so$8$next[0:0]$8896 + attribute \src "libresoc.v:164793.3-164794.35" + wire $0\xer_so$8[0:0]$8839 + attribute \src "libresoc.v:164774.7-164774.24" + wire $0\xer_so$8[0:0]$8939 + attribute \src "libresoc.v:164963.3-164981.6" + wire $0\xer_so_ok$next[0:0]$8895 + attribute \src "libresoc.v:164795.3-164796.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:164176.3-164194.6" - wire width 64 $1\fast1$7$next[63:0]$8960 - attribute \src "libresoc.v:164176.3-164194.6" - wire $1\fast1_ok$next[0:0]$8959 - attribute \src "libresoc.v:163362.7-163362.22" + attribute \src "libresoc.v:164944.3-164962.6" + wire width 64 $1\fast1$7$next[63:0]$8892 + attribute \src "libresoc.v:164944.3-164962.6" + wire $1\fast1_ok$next[0:0]$8891 + attribute \src "libresoc.v:164130.7-164130.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:164109.3-164121.6" - wire width 2 $1\muxid$1$next[1:0]$8934 - attribute \src "libresoc.v:164138.3-164156.6" - wire width 64 $1\o$next[63:0]$8947 - attribute \src "libresoc.v:163384.14-163384.38" + attribute \src "libresoc.v:164877.3-164889.6" + wire width 2 $1\muxid$1$next[1:0]$8866 + attribute \src "libresoc.v:164906.3-164924.6" + wire width 64 $1\o$next[63:0]$8879 + attribute \src "libresoc.v:164152.14-164152.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:164138.3-164156.6" - wire $1\o_ok$next[0:0]$8948 - attribute \src "libresoc.v:163391.7-163391.18" + attribute \src "libresoc.v:164906.3-164924.6" + wire $1\o_ok$next[0:0]$8880 + attribute \src "libresoc.v:164159.7-164159.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:164091.3-164108.6" - wire $1\r_busy$next[0:0]$8930 - attribute \src "libresoc.v:163405.7-163405.20" + attribute \src "libresoc.v:164859.3-164876.6" + wire $1\r_busy$next[0:0]$8862 + attribute \src "libresoc.v:164173.7-164173.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:164157.3-164175.6" - wire width 64 $1\spr1$6$next[63:0]$8953 - attribute \src "libresoc.v:164157.3-164175.6" - wire $1\spr1_ok$next[0:0]$8954 - attribute \src "libresoc.v:163421.7-163421.21" + attribute \src "libresoc.v:164925.3-164943.6" + wire width 64 $1\spr1$6$next[63:0]$8885 + attribute \src "libresoc.v:164925.3-164943.6" + wire $1\spr1_ok$next[0:0]$8886 + attribute \src "libresoc.v:164189.7-164189.21" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:164122.3-164137.6" - wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8940 - attribute \src "libresoc.v:164122.3-164137.6" - wire width 32 $1\spr_op__insn$4$next[31:0]$8941 - attribute \src "libresoc.v:164122.3-164137.6" - wire width 7 $1\spr_op__insn_type$2$next[6:0]$8942 - attribute \src "libresoc.v:164122.3-164137.6" - wire $1\spr_op__is_32bit$5$next[0:0]$8943 - attribute \src "libresoc.v:164233.3-164251.6" - wire width 2 $1\xer_ca$10$next[1:0]$8977 - attribute \src "libresoc.v:164233.3-164251.6" - wire $1\xer_ca_ok$next[0:0]$8978 - attribute \src "libresoc.v:163979.7-163979.23" + attribute \src "libresoc.v:164890.3-164905.6" + wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8872 + attribute \src "libresoc.v:164890.3-164905.6" + wire width 32 $1\spr_op__insn$4$next[31:0]$8873 + attribute \src "libresoc.v:164890.3-164905.6" + wire width 7 $1\spr_op__insn_type$2$next[6:0]$8874 + attribute \src "libresoc.v:164890.3-164905.6" + wire $1\spr_op__is_32bit$5$next[0:0]$8875 + attribute \src "libresoc.v:165001.3-165019.6" + wire width 2 $1\xer_ca$10$next[1:0]$8909 + attribute \src "libresoc.v:165001.3-165019.6" + wire $1\xer_ca_ok$next[0:0]$8910 + attribute \src "libresoc.v:164747.7-164747.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:164214.3-164232.6" - wire width 2 $1\xer_ov$9$next[1:0]$8972 - attribute \src "libresoc.v:164214.3-164232.6" - wire $1\xer_ov_ok$next[0:0]$8971 - attribute \src "libresoc.v:163995.7-163995.23" + attribute \src "libresoc.v:164982.3-165000.6" + wire width 2 $1\xer_ov$9$next[1:0]$8904 + attribute \src "libresoc.v:164982.3-165000.6" + wire $1\xer_ov_ok$next[0:0]$8903 + attribute \src "libresoc.v:164763.7-164763.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:164195.3-164213.6" - wire $1\xer_so$8$next[0:0]$8966 - attribute \src "libresoc.v:164195.3-164213.6" - wire $1\xer_so_ok$next[0:0]$8965 - attribute \src "libresoc.v:164011.7-164011.23" + attribute \src "libresoc.v:164963.3-164981.6" + wire $1\xer_so$8$next[0:0]$8898 + attribute \src "libresoc.v:164963.3-164981.6" + wire $1\xer_so_ok$next[0:0]$8897 + attribute \src "libresoc.v:164779.7-164779.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:164176.3-164194.6" - wire $2\fast1_ok$next[0:0]$8961 - attribute \src "libresoc.v:164138.3-164156.6" - wire $2\o_ok$next[0:0]$8949 - attribute \src "libresoc.v:164091.3-164108.6" - wire $2\r_busy$next[0:0]$8931 - attribute \src "libresoc.v:164157.3-164175.6" - wire $2\spr1_ok$next[0:0]$8955 - attribute \src "libresoc.v:164233.3-164251.6" - wire $2\xer_ca_ok$next[0:0]$8979 - attribute \src "libresoc.v:164214.3-164232.6" - wire $2\xer_ov_ok$next[0:0]$8973 - attribute \src "libresoc.v:164195.3-164213.6" - wire $2\xer_so_ok$next[0:0]$8967 - attribute \src "libresoc.v:164016.18-164016.118" - wire $and$libresoc.v:164016$8899_Y + attribute \src "libresoc.v:164944.3-164962.6" + wire $2\fast1_ok$next[0:0]$8893 + attribute \src "libresoc.v:164906.3-164924.6" + wire $2\o_ok$next[0:0]$8881 + attribute \src "libresoc.v:164859.3-164876.6" + wire $2\r_busy$next[0:0]$8863 + attribute \src "libresoc.v:164925.3-164943.6" + wire $2\spr1_ok$next[0:0]$8887 + attribute \src "libresoc.v:165001.3-165019.6" + wire $2\xer_ca_ok$next[0:0]$8911 + attribute \src "libresoc.v:164982.3-165000.6" + wire $2\xer_ov_ok$next[0:0]$8905 + attribute \src "libresoc.v:164963.3-164981.6" + wire $2\xer_so_ok$next[0:0]$8899 + attribute \src "libresoc.v:164784.18-164784.118" + wire $and$libresoc.v:164784$8831_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 11 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast1$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 26 \fast1$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast1$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast1_ok$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast1_ok$next - attribute \src "libresoc.v:163344.7-163344.15" + attribute \src "libresoc.v:164112.7-164112.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -338758,17 +305301,17 @@ module \pipe$64 wire input 16 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 15 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 22 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o @@ -338786,39 +305329,39 @@ module \pipe$64 wire width 64 input 9 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 10 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \spr1$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 24 \spr1$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \spr1$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr1_ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \spr_main_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \spr_main_fast1$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr_main_fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \spr_main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \spr_main_muxid$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \spr_main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr_main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \spr_main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \spr_main_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \spr_main_spr1$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr_main_spr1_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -339018,21 +305561,21 @@ module \pipe$64 wire \spr_main_spr_op__is_32bit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \spr_main_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \spr_main_xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr_main_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \spr_main_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \spr_main_xer_ov$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr_main_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \spr_main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr_main_xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr_main_xer_so_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -339338,48 +305881,48 @@ module \pipe$64 wire \spr_op__is_32bit$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 14 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 32 \xer_ca$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 13 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 30 \xer_ov$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 31 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 12 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \xer_so$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:164016$8899 + cell $and $and$libresoc.v:164784$8831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -339387,22 +305930,22 @@ module \pipe$64 parameter \Y_WIDTH 1 connect \A \p_valid_i$21 connect \B \p_ready_o - connect \Y $and$libresoc.v:164016$8899_Y + connect \Y $and$libresoc.v:164784$8831_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:164053.10-164056.4" + attribute \src "libresoc.v:164821.10-164824.4" cell \n$66 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:164057.10-164060.4" + attribute \src "libresoc.v:164825.10-164828.4" cell \p$65 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:164061.12-164090.4" + attribute \src "libresoc.v:164829.12-164858.4" cell \spr_main \spr_main connect \fast1 \spr_main_fast1 connect \fast1$7 \spr_main_fast1$17 @@ -339433,293 +305976,293 @@ module \pipe$64 connect \xer_so$8 \spr_main_xer_so$18 connect \xer_so_ok \spr_main_xer_so_ok end - attribute \src "libresoc.v:163344.7-163344.20" - process $proc$libresoc.v:163344$8980 + attribute \src "libresoc.v:164112.7-164112.20" + process $proc$libresoc.v:164112$8912 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:163357.14-163357.46" - process $proc$libresoc.v:163357$8981 + attribute \src "libresoc.v:164125.14-164125.46" + process $proc$libresoc.v:164125$8913 assign { } { } - assign $0\fast1$7[63:0]$8982 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$7[63:0]$8914 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$7 $0\fast1$7[63:0]$8982 + update \fast1$7 $0\fast1$7[63:0]$8914 end - attribute \src "libresoc.v:163362.7-163362.22" - process $proc$libresoc.v:163362$8983 + attribute \src "libresoc.v:164130.7-164130.22" + process $proc$libresoc.v:164130$8915 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:163371.13-163371.29" - process $proc$libresoc.v:163371$8984 + attribute \src "libresoc.v:164139.13-164139.29" + process $proc$libresoc.v:164139$8916 assign { } { } - assign $0\muxid$1[1:0]$8985 2'00 + assign $0\muxid$1[1:0]$8917 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8985 + update \muxid$1 $0\muxid$1[1:0]$8917 end - attribute \src "libresoc.v:163384.14-163384.38" - process $proc$libresoc.v:163384$8986 + attribute \src "libresoc.v:164152.14-164152.38" + process $proc$libresoc.v:164152$8918 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:163391.7-163391.18" - process $proc$libresoc.v:163391$8987 + attribute \src "libresoc.v:164159.7-164159.18" + process $proc$libresoc.v:164159$8919 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:163405.7-163405.20" - process $proc$libresoc.v:163405$8988 + attribute \src "libresoc.v:164173.7-164173.20" + process $proc$libresoc.v:164173$8920 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:163416.14-163416.45" - process $proc$libresoc.v:163416$8989 + attribute \src "libresoc.v:164184.14-164184.45" + process $proc$libresoc.v:164184$8921 assign { } { } - assign $0\spr1$6[63:0]$8990 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\spr1$6[63:0]$8922 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \spr1$6 $0\spr1$6[63:0]$8990 + update \spr1$6 $0\spr1$6[63:0]$8922 end - attribute \src "libresoc.v:163421.7-163421.21" - process $proc$libresoc.v:163421$8991 + attribute \src "libresoc.v:164189.7-164189.21" + process $proc$libresoc.v:164189$8923 assign { } { } assign $1\spr1_ok[0:0] 1'0 sync always sync init update \spr1_ok $1\spr1_ok[0:0] end - attribute \src "libresoc.v:163713.14-163713.44" - process $proc$libresoc.v:163713$8992 + attribute \src "libresoc.v:164481.14-164481.44" + process $proc$libresoc.v:164481$8924 assign { } { } - assign $0\spr_op__fn_unit$3[13:0]$8993 14'00000000000000 + assign $0\spr_op__fn_unit$3[13:0]$8925 14'00000000000000 sync always sync init - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8993 + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8925 end - attribute \src "libresoc.v:163722.14-163722.38" - process $proc$libresoc.v:163722$8994 + attribute \src "libresoc.v:164490.14-164490.38" + process $proc$libresoc.v:164490$8926 assign { } { } - assign $0\spr_op__insn$4[31:0]$8995 0 + assign $0\spr_op__insn$4[31:0]$8927 0 sync always sync init - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8995 + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8927 end - attribute \src "libresoc.v:163879.13-163879.42" - process $proc$libresoc.v:163879$8996 + attribute \src "libresoc.v:164647.13-164647.42" + process $proc$libresoc.v:164647$8928 assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8997 7'0000000 + assign $0\spr_op__insn_type$2[6:0]$8929 7'0000000 sync always sync init - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8997 + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8929 end - attribute \src "libresoc.v:163965.7-163965.34" - process $proc$libresoc.v:163965$8998 + attribute \src "libresoc.v:164733.7-164733.34" + process $proc$libresoc.v:164733$8930 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8999 1'0 + assign $0\spr_op__is_32bit$5[0:0]$8931 1'0 sync always sync init - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8999 + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8931 end - attribute \src "libresoc.v:163972.13-163972.31" - process $proc$libresoc.v:163972$9000 + attribute \src "libresoc.v:164740.13-164740.31" + process $proc$libresoc.v:164740$8932 assign { } { } - assign $0\xer_ca$10[1:0]$9001 2'00 + assign $0\xer_ca$10[1:0]$8933 2'00 sync always sync init - update \xer_ca$10 $0\xer_ca$10[1:0]$9001 + update \xer_ca$10 $0\xer_ca$10[1:0]$8933 end - attribute \src "libresoc.v:163979.7-163979.23" - process $proc$libresoc.v:163979$9002 + attribute \src "libresoc.v:164747.7-164747.23" + process $proc$libresoc.v:164747$8934 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:163990.13-163990.30" - process $proc$libresoc.v:163990$9003 + attribute \src "libresoc.v:164758.13-164758.30" + process $proc$libresoc.v:164758$8935 assign { } { } - assign $0\xer_ov$9[1:0]$9004 2'00 + assign $0\xer_ov$9[1:0]$8936 2'00 sync always sync init - update \xer_ov$9 $0\xer_ov$9[1:0]$9004 + update \xer_ov$9 $0\xer_ov$9[1:0]$8936 end - attribute \src "libresoc.v:163995.7-163995.23" - process $proc$libresoc.v:163995$9005 + attribute \src "libresoc.v:164763.7-164763.23" + process $proc$libresoc.v:164763$8937 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:164006.7-164006.24" - process $proc$libresoc.v:164006$9006 + attribute \src "libresoc.v:164774.7-164774.24" + process $proc$libresoc.v:164774$8938 assign { } { } - assign $0\xer_so$8[0:0]$9007 1'0 + assign $0\xer_so$8[0:0]$8939 1'0 sync always sync init - update \xer_so$8 $0\xer_so$8[0:0]$9007 + update \xer_so$8 $0\xer_so$8[0:0]$8939 end - attribute \src "libresoc.v:164011.7-164011.23" - process $proc$libresoc.v:164011$9008 + attribute \src "libresoc.v:164779.7-164779.23" + process $proc$libresoc.v:164779$8940 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:164017.3-164018.37" - process $proc$libresoc.v:164017$8900 + attribute \src "libresoc.v:164785.3-164786.37" + process $proc$libresoc.v:164785$8832 assign { } { } - assign $0\xer_ca$10[1:0]$8901 \xer_ca$10$next + assign $0\xer_ca$10[1:0]$8833 \xer_ca$10$next sync posedge \coresync_clk - update \xer_ca$10 $0\xer_ca$10[1:0]$8901 + update \xer_ca$10 $0\xer_ca$10[1:0]$8833 end - attribute \src "libresoc.v:164019.3-164020.35" - process $proc$libresoc.v:164019$8902 + attribute \src "libresoc.v:164787.3-164788.35" + process $proc$libresoc.v:164787$8834 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:164021.3-164022.35" - process $proc$libresoc.v:164021$8903 + attribute \src "libresoc.v:164789.3-164790.35" + process $proc$libresoc.v:164789$8835 assign { } { } - assign $0\xer_ov$9[1:0]$8904 \xer_ov$9$next + assign $0\xer_ov$9[1:0]$8836 \xer_ov$9$next sync posedge \coresync_clk - update \xer_ov$9 $0\xer_ov$9[1:0]$8904 + update \xer_ov$9 $0\xer_ov$9[1:0]$8836 end - attribute \src "libresoc.v:164023.3-164024.35" - process $proc$libresoc.v:164023$8905 + attribute \src "libresoc.v:164791.3-164792.35" + process $proc$libresoc.v:164791$8837 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:164025.3-164026.35" - process $proc$libresoc.v:164025$8906 + attribute \src "libresoc.v:164793.3-164794.35" + process $proc$libresoc.v:164793$8838 assign { } { } - assign $0\xer_so$8[0:0]$8907 \xer_so$8$next + assign $0\xer_so$8[0:0]$8839 \xer_so$8$next sync posedge \coresync_clk - update \xer_so$8 $0\xer_so$8[0:0]$8907 + update \xer_so$8 $0\xer_so$8[0:0]$8839 end - attribute \src "libresoc.v:164027.3-164028.35" - process $proc$libresoc.v:164027$8908 + attribute \src "libresoc.v:164795.3-164796.35" + process $proc$libresoc.v:164795$8840 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:164029.3-164030.33" - process $proc$libresoc.v:164029$8909 + attribute \src "libresoc.v:164797.3-164798.33" + process $proc$libresoc.v:164797$8841 assign { } { } - assign $0\fast1$7[63:0]$8910 \fast1$7$next + assign $0\fast1$7[63:0]$8842 \fast1$7$next sync posedge \coresync_clk - update \fast1$7 $0\fast1$7[63:0]$8910 + update \fast1$7 $0\fast1$7[63:0]$8842 end - attribute \src "libresoc.v:164031.3-164032.33" - process $proc$libresoc.v:164031$8911 + attribute \src "libresoc.v:164799.3-164800.33" + process $proc$libresoc.v:164799$8843 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:164033.3-164034.31" - process $proc$libresoc.v:164033$8912 + attribute \src "libresoc.v:164801.3-164802.31" + process $proc$libresoc.v:164801$8844 assign { } { } - assign $0\spr1$6[63:0]$8913 \spr1$6$next + assign $0\spr1$6[63:0]$8845 \spr1$6$next sync posedge \coresync_clk - update \spr1$6 $0\spr1$6[63:0]$8913 + update \spr1$6 $0\spr1$6[63:0]$8845 end - attribute \src "libresoc.v:164035.3-164036.31" - process $proc$libresoc.v:164035$8914 + attribute \src "libresoc.v:164803.3-164804.31" + process $proc$libresoc.v:164803$8846 assign { } { } assign $0\spr1_ok[0:0] \spr1_ok$next sync posedge \coresync_clk update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:164037.3-164038.19" - process $proc$libresoc.v:164037$8915 + attribute \src "libresoc.v:164805.3-164806.19" + process $proc$libresoc.v:164805$8847 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:164039.3-164040.25" - process $proc$libresoc.v:164039$8916 + attribute \src "libresoc.v:164807.3-164808.25" + process $proc$libresoc.v:164807$8848 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:164041.3-164042.57" - process $proc$libresoc.v:164041$8917 + attribute \src "libresoc.v:164809.3-164810.57" + process $proc$libresoc.v:164809$8849 assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8918 \spr_op__insn_type$2$next + assign $0\spr_op__insn_type$2[6:0]$8850 \spr_op__insn_type$2$next sync posedge \coresync_clk - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8918 + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8850 end - attribute \src "libresoc.v:164043.3-164044.53" - process $proc$libresoc.v:164043$8919 + attribute \src "libresoc.v:164811.3-164812.53" + process $proc$libresoc.v:164811$8851 assign { } { } - assign $0\spr_op__fn_unit$3[13:0]$8920 \spr_op__fn_unit$3$next + assign $0\spr_op__fn_unit$3[13:0]$8852 \spr_op__fn_unit$3$next sync posedge \coresync_clk - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8920 + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8852 end - attribute \src "libresoc.v:164045.3-164046.47" - process $proc$libresoc.v:164045$8921 + attribute \src "libresoc.v:164813.3-164814.47" + process $proc$libresoc.v:164813$8853 assign { } { } - assign $0\spr_op__insn$4[31:0]$8922 \spr_op__insn$4$next + assign $0\spr_op__insn$4[31:0]$8854 \spr_op__insn$4$next sync posedge \coresync_clk - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8922 + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8854 end - attribute \src "libresoc.v:164047.3-164048.55" - process $proc$libresoc.v:164047$8923 + attribute \src "libresoc.v:164815.3-164816.55" + process $proc$libresoc.v:164815$8855 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8924 \spr_op__is_32bit$5$next + assign $0\spr_op__is_32bit$5[0:0]$8856 \spr_op__is_32bit$5$next sync posedge \coresync_clk - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8924 + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8856 end - attribute \src "libresoc.v:164049.3-164050.33" - process $proc$libresoc.v:164049$8925 + attribute \src "libresoc.v:164817.3-164818.33" + process $proc$libresoc.v:164817$8857 assign { } { } - assign $0\muxid$1[1:0]$8926 \muxid$1$next + assign $0\muxid$1[1:0]$8858 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8926 + update \muxid$1 $0\muxid$1[1:0]$8858 end - attribute \src "libresoc.v:164051.3-164052.29" - process $proc$libresoc.v:164051$8927 + attribute \src "libresoc.v:164819.3-164820.29" + process $proc$libresoc.v:164819$8859 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:164091.3-164108.6" - process $proc$libresoc.v:164091$8928 + attribute \src "libresoc.v:164859.3-164876.6" + process $proc$libresoc.v:164859$8860 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8929 $2\r_busy$next[0:0]$8931 - attribute \src "libresoc.v:164092.5-164092.29" + assign $0\r_busy$next[0:0]$8861 $2\r_busy$next[0:0]$8863 + attribute \src "libresoc.v:164860.5-164860.29" switch \initial - attribute \src "libresoc.v:164092.9-164092.17" + attribute \src "libresoc.v:164860.9-164860.17" case 1'1 case end @@ -339728,34 +306271,34 @@ module \pipe$64 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8930 1'1 + assign $1\r_busy$next[0:0]$8862 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8930 1'0 + assign $1\r_busy$next[0:0]$8862 1'0 case - assign $1\r_busy$next[0:0]$8930 \r_busy + assign $1\r_busy$next[0:0]$8862 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8931 1'0 + assign $2\r_busy$next[0:0]$8863 1'0 case - assign $2\r_busy$next[0:0]$8931 $1\r_busy$next[0:0]$8930 + assign $2\r_busy$next[0:0]$8863 $1\r_busy$next[0:0]$8862 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8929 + update \r_busy$next $0\r_busy$next[0:0]$8861 end - attribute \src "libresoc.v:164109.3-164121.6" - process $proc$libresoc.v:164109$8932 + attribute \src "libresoc.v:164877.3-164889.6" + process $proc$libresoc.v:164877$8864 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8933 $1\muxid$1$next[1:0]$8934 - attribute \src "libresoc.v:164110.5-164110.29" + assign $0\muxid$1$next[1:0]$8865 $1\muxid$1$next[1:0]$8866 + attribute \src "libresoc.v:164878.5-164878.29" switch \initial - attribute \src "libresoc.v:164110.9-164110.17" + attribute \src "libresoc.v:164878.9-164878.17" case 1'1 case end @@ -339764,19 +306307,19 @@ module \pipe$64 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8934 \muxid$24 + assign $1\muxid$1$next[1:0]$8866 \muxid$24 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8934 \muxid$24 + assign $1\muxid$1$next[1:0]$8866 \muxid$24 case - assign $1\muxid$1$next[1:0]$8934 \muxid$1 + assign $1\muxid$1$next[1:0]$8866 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8933 + update \muxid$1$next $0\muxid$1$next[1:0]$8865 end - attribute \src "libresoc.v:164122.3-164137.6" - process $proc$libresoc.v:164122$8935 + attribute \src "libresoc.v:164890.3-164905.6" + process $proc$libresoc.v:164890$8867 assign { } { } assign { } { } assign { } { } @@ -339785,13 +306328,13 @@ module \pipe$64 assign { } { } assign { } { } assign { } { } - assign $0\spr_op__fn_unit$3$next[13:0]$8936 $1\spr_op__fn_unit$3$next[13:0]$8940 - assign $0\spr_op__insn$4$next[31:0]$8937 $1\spr_op__insn$4$next[31:0]$8941 - assign $0\spr_op__insn_type$2$next[6:0]$8938 $1\spr_op__insn_type$2$next[6:0]$8942 - assign $0\spr_op__is_32bit$5$next[0:0]$8939 $1\spr_op__is_32bit$5$next[0:0]$8943 - attribute \src "libresoc.v:164123.5-164123.29" + assign $0\spr_op__fn_unit$3$next[13:0]$8868 $1\spr_op__fn_unit$3$next[13:0]$8872 + assign $0\spr_op__insn$4$next[31:0]$8869 $1\spr_op__insn$4$next[31:0]$8873 + assign $0\spr_op__insn_type$2$next[6:0]$8870 $1\spr_op__insn_type$2$next[6:0]$8874 + assign $0\spr_op__is_32bit$5$next[0:0]$8871 $1\spr_op__is_32bit$5$next[0:0]$8875 + attribute \src "libresoc.v:164891.5-164891.29" switch \initial - attribute \src "libresoc.v:164123.9-164123.17" + attribute \src "libresoc.v:164891.9-164891.17" case 1'1 case end @@ -339803,38 +306346,38 @@ module \pipe$64 assign { } { } assign { } { } assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8943 $1\spr_op__insn$4$next[31:0]$8941 $1\spr_op__fn_unit$3$next[13:0]$8940 $1\spr_op__insn_type$2$next[6:0]$8942 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign { $1\spr_op__is_32bit$5$next[0:0]$8875 $1\spr_op__insn$4$next[31:0]$8873 $1\spr_op__fn_unit$3$next[13:0]$8872 $1\spr_op__insn_type$2$next[6:0]$8874 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8943 $1\spr_op__insn$4$next[31:0]$8941 $1\spr_op__fn_unit$3$next[13:0]$8940 $1\spr_op__insn_type$2$next[6:0]$8942 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign { $1\spr_op__is_32bit$5$next[0:0]$8875 $1\spr_op__insn$4$next[31:0]$8873 $1\spr_op__fn_unit$3$next[13:0]$8872 $1\spr_op__insn_type$2$next[6:0]$8874 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } case - assign $1\spr_op__fn_unit$3$next[13:0]$8940 \spr_op__fn_unit$3 - assign $1\spr_op__insn$4$next[31:0]$8941 \spr_op__insn$4 - assign $1\spr_op__insn_type$2$next[6:0]$8942 \spr_op__insn_type$2 - assign $1\spr_op__is_32bit$5$next[0:0]$8943 \spr_op__is_32bit$5 + assign $1\spr_op__fn_unit$3$next[13:0]$8872 \spr_op__fn_unit$3 + assign $1\spr_op__insn$4$next[31:0]$8873 \spr_op__insn$4 + assign $1\spr_op__insn_type$2$next[6:0]$8874 \spr_op__insn_type$2 + assign $1\spr_op__is_32bit$5$next[0:0]$8875 \spr_op__is_32bit$5 end sync always - update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[13:0]$8936 - update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8937 - update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8938 - update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8939 + update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[13:0]$8868 + update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8869 + update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8870 + update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8871 end - attribute \src "libresoc.v:164138.3-164156.6" - process $proc$libresoc.v:164138$8944 + attribute \src "libresoc.v:164906.3-164924.6" + process $proc$libresoc.v:164906$8876 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8945 $1\o$next[63:0]$8947 + assign $0\o$next[63:0]$8877 $1\o$next[63:0]$8879 assign { } { } - assign $0\o_ok$next[0:0]$8946 $2\o_ok$next[0:0]$8949 - attribute \src "libresoc.v:164139.5-164139.29" + assign $0\o_ok$next[0:0]$8878 $2\o_ok$next[0:0]$8881 + attribute \src "libresoc.v:164907.5-164907.29" switch \initial - attribute \src "libresoc.v:164139.9-164139.17" + attribute \src "libresoc.v:164907.9-164907.17" case 1'1 case end @@ -339844,41 +306387,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8948 $1\o$next[63:0]$8947 } { \o_ok$30 \o$29 } + assign { $1\o_ok$next[0:0]$8880 $1\o$next[63:0]$8879 } { \o_ok$30 \o$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8948 $1\o$next[63:0]$8947 } { \o_ok$30 \o$29 } + assign { $1\o_ok$next[0:0]$8880 $1\o$next[63:0]$8879 } { \o_ok$30 \o$29 } case - assign $1\o$next[63:0]$8947 \o - assign $1\o_ok$next[0:0]$8948 \o_ok + assign $1\o$next[63:0]$8879 \o + assign $1\o_ok$next[0:0]$8880 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8949 1'0 + assign $2\o_ok$next[0:0]$8881 1'0 case - assign $2\o_ok$next[0:0]$8949 $1\o_ok$next[0:0]$8948 + assign $2\o_ok$next[0:0]$8881 $1\o_ok$next[0:0]$8880 end sync always - update \o$next $0\o$next[63:0]$8945 - update \o_ok$next $0\o_ok$next[0:0]$8946 + update \o$next $0\o$next[63:0]$8877 + update \o_ok$next $0\o_ok$next[0:0]$8878 end - attribute \src "libresoc.v:164157.3-164175.6" - process $proc$libresoc.v:164157$8950 + attribute \src "libresoc.v:164925.3-164943.6" + process $proc$libresoc.v:164925$8882 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\spr1$6$next[63:0]$8951 $1\spr1$6$next[63:0]$8953 + assign $0\spr1$6$next[63:0]$8883 $1\spr1$6$next[63:0]$8885 assign { } { } - assign $0\spr1_ok$next[0:0]$8952 $2\spr1_ok$next[0:0]$8955 - attribute \src "libresoc.v:164158.5-164158.29" + assign $0\spr1_ok$next[0:0]$8884 $2\spr1_ok$next[0:0]$8887 + attribute \src "libresoc.v:164926.5-164926.29" switch \initial - attribute \src "libresoc.v:164158.9-164158.17" + attribute \src "libresoc.v:164926.9-164926.17" case 1'1 case end @@ -339888,41 +306431,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\spr1_ok$next[0:0]$8954 $1\spr1$6$next[63:0]$8953 } { \spr1_ok$32 \spr1$31 } + assign { $1\spr1_ok$next[0:0]$8886 $1\spr1$6$next[63:0]$8885 } { \spr1_ok$32 \spr1$31 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\spr1_ok$next[0:0]$8954 $1\spr1$6$next[63:0]$8953 } { \spr1_ok$32 \spr1$31 } + assign { $1\spr1_ok$next[0:0]$8886 $1\spr1$6$next[63:0]$8885 } { \spr1_ok$32 \spr1$31 } case - assign $1\spr1$6$next[63:0]$8953 \spr1$6 - assign $1\spr1_ok$next[0:0]$8954 \spr1_ok + assign $1\spr1$6$next[63:0]$8885 \spr1$6 + assign $1\spr1_ok$next[0:0]$8886 \spr1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\spr1_ok$next[0:0]$8955 1'0 + assign $2\spr1_ok$next[0:0]$8887 1'0 case - assign $2\spr1_ok$next[0:0]$8955 $1\spr1_ok$next[0:0]$8954 + assign $2\spr1_ok$next[0:0]$8887 $1\spr1_ok$next[0:0]$8886 end sync always - update \spr1$6$next $0\spr1$6$next[63:0]$8951 - update \spr1_ok$next $0\spr1_ok$next[0:0]$8952 + update \spr1$6$next $0\spr1$6$next[63:0]$8883 + update \spr1_ok$next $0\spr1_ok$next[0:0]$8884 end - attribute \src "libresoc.v:164176.3-164194.6" - process $proc$libresoc.v:164176$8956 + attribute \src "libresoc.v:164944.3-164962.6" + process $proc$libresoc.v:164944$8888 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$7$next[63:0]$8958 $1\fast1$7$next[63:0]$8960 - assign $0\fast1_ok$next[0:0]$8957 $2\fast1_ok$next[0:0]$8961 - attribute \src "libresoc.v:164177.5-164177.29" + assign $0\fast1$7$next[63:0]$8890 $1\fast1$7$next[63:0]$8892 + assign $0\fast1_ok$next[0:0]$8889 $2\fast1_ok$next[0:0]$8893 + attribute \src "libresoc.v:164945.5-164945.29" switch \initial - attribute \src "libresoc.v:164177.9-164177.17" + attribute \src "libresoc.v:164945.9-164945.17" case 1'1 case end @@ -339932,41 +306475,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8959 $1\fast1$7$next[63:0]$8960 } { \fast1_ok$34 \fast1$33 } + assign { $1\fast1_ok$next[0:0]$8891 $1\fast1$7$next[63:0]$8892 } { \fast1_ok$34 \fast1$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8959 $1\fast1$7$next[63:0]$8960 } { \fast1_ok$34 \fast1$33 } + assign { $1\fast1_ok$next[0:0]$8891 $1\fast1$7$next[63:0]$8892 } { \fast1_ok$34 \fast1$33 } case - assign $1\fast1_ok$next[0:0]$8959 \fast1_ok - assign $1\fast1$7$next[63:0]$8960 \fast1$7 + assign $1\fast1_ok$next[0:0]$8891 \fast1_ok + assign $1\fast1$7$next[63:0]$8892 \fast1$7 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8961 1'0 + assign $2\fast1_ok$next[0:0]$8893 1'0 case - assign $2\fast1_ok$next[0:0]$8961 $1\fast1_ok$next[0:0]$8959 + assign $2\fast1_ok$next[0:0]$8893 $1\fast1_ok$next[0:0]$8891 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$8957 - update \fast1$7$next $0\fast1$7$next[63:0]$8958 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8889 + update \fast1$7$next $0\fast1$7$next[63:0]$8890 end - attribute \src "libresoc.v:164195.3-164213.6" - process $proc$libresoc.v:164195$8962 + attribute \src "libresoc.v:164963.3-164981.6" + process $proc$libresoc.v:164963$8894 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$8$next[0:0]$8964 $1\xer_so$8$next[0:0]$8966 - assign $0\xer_so_ok$next[0:0]$8963 $2\xer_so_ok$next[0:0]$8967 - attribute \src "libresoc.v:164196.5-164196.29" + assign $0\xer_so$8$next[0:0]$8896 $1\xer_so$8$next[0:0]$8898 + assign $0\xer_so_ok$next[0:0]$8895 $2\xer_so_ok$next[0:0]$8899 + attribute \src "libresoc.v:164964.5-164964.29" switch \initial - attribute \src "libresoc.v:164196.9-164196.17" + attribute \src "libresoc.v:164964.9-164964.17" case 1'1 case end @@ -339976,41 +306519,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8965 $1\xer_so$8$next[0:0]$8966 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\xer_so_ok$next[0:0]$8897 $1\xer_so$8$next[0:0]$8898 } { \xer_so_ok$36 \xer_so$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8965 $1\xer_so$8$next[0:0]$8966 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\xer_so_ok$next[0:0]$8897 $1\xer_so$8$next[0:0]$8898 } { \xer_so_ok$36 \xer_so$35 } case - assign $1\xer_so_ok$next[0:0]$8965 \xer_so_ok - assign $1\xer_so$8$next[0:0]$8966 \xer_so$8 + assign $1\xer_so_ok$next[0:0]$8897 \xer_so_ok + assign $1\xer_so$8$next[0:0]$8898 \xer_so$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8967 1'0 + assign $2\xer_so_ok$next[0:0]$8899 1'0 case - assign $2\xer_so_ok$next[0:0]$8967 $1\xer_so_ok$next[0:0]$8965 + assign $2\xer_so_ok$next[0:0]$8899 $1\xer_so_ok$next[0:0]$8897 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8963 - update \xer_so$8$next $0\xer_so$8$next[0:0]$8964 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8895 + update \xer_so$8$next $0\xer_so$8$next[0:0]$8896 end - attribute \src "libresoc.v:164214.3-164232.6" - process $proc$libresoc.v:164214$8968 + attribute \src "libresoc.v:164982.3-165000.6" + process $proc$libresoc.v:164982$8900 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$9$next[1:0]$8970 $1\xer_ov$9$next[1:0]$8972 - assign $0\xer_ov_ok$next[0:0]$8969 $2\xer_ov_ok$next[0:0]$8973 - attribute \src "libresoc.v:164215.5-164215.29" + assign $0\xer_ov$9$next[1:0]$8902 $1\xer_ov$9$next[1:0]$8904 + assign $0\xer_ov_ok$next[0:0]$8901 $2\xer_ov_ok$next[0:0]$8905 + attribute \src "libresoc.v:164983.5-164983.29" switch \initial - attribute \src "libresoc.v:164215.9-164215.17" + attribute \src "libresoc.v:164983.9-164983.17" case 1'1 case end @@ -340020,41 +306563,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8971 $1\xer_ov$9$next[1:0]$8972 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\xer_ov_ok$next[0:0]$8903 $1\xer_ov$9$next[1:0]$8904 } { \xer_ov_ok$38 \xer_ov$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8971 $1\xer_ov$9$next[1:0]$8972 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\xer_ov_ok$next[0:0]$8903 $1\xer_ov$9$next[1:0]$8904 } { \xer_ov_ok$38 \xer_ov$37 } case - assign $1\xer_ov_ok$next[0:0]$8971 \xer_ov_ok - assign $1\xer_ov$9$next[1:0]$8972 \xer_ov$9 + assign $1\xer_ov_ok$next[0:0]$8903 \xer_ov_ok + assign $1\xer_ov$9$next[1:0]$8904 \xer_ov$9 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8973 1'0 + assign $2\xer_ov_ok$next[0:0]$8905 1'0 case - assign $2\xer_ov_ok$next[0:0]$8973 $1\xer_ov_ok$next[0:0]$8971 + assign $2\xer_ov_ok$next[0:0]$8905 $1\xer_ov_ok$next[0:0]$8903 end sync always - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8969 - update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8970 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8901 + update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8902 end - attribute \src "libresoc.v:164233.3-164251.6" - process $proc$libresoc.v:164233$8974 + attribute \src "libresoc.v:165001.3-165019.6" + process $proc$libresoc.v:165001$8906 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$10$next[1:0]$8975 $1\xer_ca$10$next[1:0]$8977 + assign $0\xer_ca$10$next[1:0]$8907 $1\xer_ca$10$next[1:0]$8909 assign { } { } - assign $0\xer_ca_ok$next[0:0]$8976 $2\xer_ca_ok$next[0:0]$8979 - attribute \src "libresoc.v:164234.5-164234.29" + assign $0\xer_ca_ok$next[0:0]$8908 $2\xer_ca_ok$next[0:0]$8911 + attribute \src "libresoc.v:165002.5-165002.29" switch \initial - attribute \src "libresoc.v:164234.9-164234.17" + attribute \src "libresoc.v:165002.9-165002.17" case 1'1 case end @@ -340064,30 +306607,30 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8978 $1\xer_ca$10$next[1:0]$8977 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\xer_ca_ok$next[0:0]$8910 $1\xer_ca$10$next[1:0]$8909 } { \xer_ca_ok$40 \xer_ca$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8978 $1\xer_ca$10$next[1:0]$8977 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\xer_ca_ok$next[0:0]$8910 $1\xer_ca$10$next[1:0]$8909 } { \xer_ca_ok$40 \xer_ca$39 } case - assign $1\xer_ca$10$next[1:0]$8977 \xer_ca$10 - assign $1\xer_ca_ok$next[0:0]$8978 \xer_ca_ok + assign $1\xer_ca$10$next[1:0]$8909 \xer_ca$10 + assign $1\xer_ca_ok$next[0:0]$8910 \xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$8979 1'0 + assign $2\xer_ca_ok$next[0:0]$8911 1'0 case - assign $2\xer_ca_ok$next[0:0]$8979 $1\xer_ca_ok$next[0:0]$8978 + assign $2\xer_ca_ok$next[0:0]$8911 $1\xer_ca_ok$next[0:0]$8910 end sync always - update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8975 - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8976 + update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8907 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8908 end - connect \$22 $and$libresoc.v:164016$8899_Y + connect \$22 $and$libresoc.v:164784$8831_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } @@ -340110,279 +306653,279 @@ module \pipe$64 connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \spr_main_muxid \muxid end -attribute \src "libresoc.v:164277.1-165769.10" +attribute \src "libresoc.v:165045.1-166537.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" attribute \generator "nMigen" module \pipe1 - attribute \src "libresoc.v:165683.3-165724.6" - wire width 4 $0\alu_op__data_len$next[3:0]$9072 - attribute \src "libresoc.v:165459.3-165460.49" + attribute \src "libresoc.v:166451.3-166492.6" + wire width 4 $0\alu_op__data_len$next[3:0]$9004 + attribute \src "libresoc.v:166227.3-166228.49" wire width 4 $0\alu_op__data_len[3:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire width 14 $0\alu_op__fn_unit$next[13:0]$9073 - attribute \src "libresoc.v:165429.3-165430.47" + attribute \src "libresoc.v:166451.3-166492.6" + wire width 14 $0\alu_op__fn_unit$next[13:0]$9005 + attribute \src "libresoc.v:166197.3-166198.47" wire width 14 $0\alu_op__fn_unit[13:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire width 64 $0\alu_op__imm_data__data$next[63:0]$9074 - attribute \src "libresoc.v:165431.3-165432.61" + attribute \src "libresoc.v:166451.3-166492.6" + wire width 64 $0\alu_op__imm_data__data$next[63:0]$9006 + attribute \src "libresoc.v:166199.3-166200.61" wire width 64 $0\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $0\alu_op__imm_data__ok$next[0:0]$9075 - attribute \src "libresoc.v:165433.3-165434.57" + attribute \src "libresoc.v:166451.3-166492.6" + wire $0\alu_op__imm_data__ok$next[0:0]$9007 + attribute \src "libresoc.v:166201.3-166202.57" wire $0\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire width 2 $0\alu_op__input_carry$next[1:0]$9076 - attribute \src "libresoc.v:165451.3-165452.55" + attribute \src "libresoc.v:166451.3-166492.6" + wire width 2 $0\alu_op__input_carry$next[1:0]$9008 + attribute \src "libresoc.v:166219.3-166220.55" wire width 2 $0\alu_op__input_carry[1:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire width 32 $0\alu_op__insn$next[31:0]$9077 - attribute \src "libresoc.v:165461.3-165462.41" + attribute \src "libresoc.v:166451.3-166492.6" + wire width 32 $0\alu_op__insn$next[31:0]$9009 + attribute \src "libresoc.v:166229.3-166230.41" wire width 32 $0\alu_op__insn[31:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire width 7 $0\alu_op__insn_type$next[6:0]$9078 - attribute \src "libresoc.v:165427.3-165428.51" + attribute \src "libresoc.v:166451.3-166492.6" + wire width 7 $0\alu_op__insn_type$next[6:0]$9010 + attribute \src "libresoc.v:166195.3-166196.51" wire width 7 $0\alu_op__insn_type[6:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $0\alu_op__invert_in$next[0:0]$9079 - attribute \src "libresoc.v:165443.3-165444.51" + attribute \src "libresoc.v:166451.3-166492.6" + wire $0\alu_op__invert_in$next[0:0]$9011 + attribute \src "libresoc.v:166211.3-166212.51" wire $0\alu_op__invert_in[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $0\alu_op__invert_out$next[0:0]$9080 - attribute \src "libresoc.v:165447.3-165448.53" + attribute \src "libresoc.v:166451.3-166492.6" + wire $0\alu_op__invert_out$next[0:0]$9012 + attribute \src "libresoc.v:166215.3-166216.53" wire $0\alu_op__invert_out[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $0\alu_op__is_32bit$next[0:0]$9081 - attribute \src "libresoc.v:165455.3-165456.49" + attribute \src "libresoc.v:166451.3-166492.6" + wire $0\alu_op__is_32bit$next[0:0]$9013 + attribute \src "libresoc.v:166223.3-166224.49" wire $0\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $0\alu_op__is_signed$next[0:0]$9082 - attribute \src "libresoc.v:165457.3-165458.51" + attribute \src "libresoc.v:166451.3-166492.6" + wire $0\alu_op__is_signed$next[0:0]$9014 + attribute \src "libresoc.v:166225.3-166226.51" wire $0\alu_op__is_signed[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $0\alu_op__oe__oe$next[0:0]$9083 - attribute \src "libresoc.v:165439.3-165440.45" + attribute \src "libresoc.v:166451.3-166492.6" + wire $0\alu_op__oe__oe$next[0:0]$9015 + attribute \src "libresoc.v:166207.3-166208.45" wire $0\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $0\alu_op__oe__ok$next[0:0]$9084 - attribute \src "libresoc.v:165441.3-165442.45" + attribute \src "libresoc.v:166451.3-166492.6" + wire $0\alu_op__oe__ok$next[0:0]$9016 + attribute \src "libresoc.v:166209.3-166210.45" wire $0\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $0\alu_op__output_carry$next[0:0]$9085 - attribute \src "libresoc.v:165453.3-165454.57" + attribute \src "libresoc.v:166451.3-166492.6" + wire $0\alu_op__output_carry$next[0:0]$9017 + attribute \src "libresoc.v:166221.3-166222.57" wire $0\alu_op__output_carry[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $0\alu_op__rc__ok$next[0:0]$9086 - attribute \src "libresoc.v:165437.3-165438.45" + attribute \src "libresoc.v:166451.3-166492.6" + wire $0\alu_op__rc__ok$next[0:0]$9018 + attribute \src "libresoc.v:166205.3-166206.45" wire $0\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $0\alu_op__rc__rc$next[0:0]$9087 - attribute \src "libresoc.v:165435.3-165436.45" + attribute \src "libresoc.v:166451.3-166492.6" + wire $0\alu_op__rc__rc$next[0:0]$9019 + attribute \src "libresoc.v:166203.3-166204.45" wire $0\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $0\alu_op__write_cr0$next[0:0]$9088 - attribute \src "libresoc.v:165449.3-165450.51" + attribute \src "libresoc.v:166451.3-166492.6" + wire $0\alu_op__write_cr0$next[0:0]$9020 + attribute \src "libresoc.v:166217.3-166218.51" wire $0\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $0\alu_op__zero_a$next[0:0]$9089 - attribute \src "libresoc.v:165445.3-165446.45" + attribute \src "libresoc.v:166451.3-166492.6" + wire $0\alu_op__zero_a$next[0:0]$9021 + attribute \src "libresoc.v:166213.3-166214.45" wire $0\alu_op__zero_a[0:0] - attribute \src "libresoc.v:165576.3-165594.6" - wire width 4 $0\cr_a$next[3:0]$9041 - attribute \src "libresoc.v:165419.3-165420.25" + attribute \src "libresoc.v:166344.3-166362.6" + wire width 4 $0\cr_a$next[3:0]$8973 + attribute \src "libresoc.v:166187.3-166188.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:165576.3-165594.6" - wire $0\cr_a_ok$next[0:0]$9042 - attribute \src "libresoc.v:165421.3-165422.31" + attribute \src "libresoc.v:166344.3-166362.6" + wire $0\cr_a_ok$next[0:0]$8974 + attribute \src "libresoc.v:166189.3-166190.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:164278.7-164278.20" + attribute \src "libresoc.v:165046.7-165046.20" wire $0\initial[0:0] - attribute \src "libresoc.v:165670.3-165682.6" - wire width 2 $0\muxid$next[1:0]$9069 - attribute \src "libresoc.v:165463.3-165464.27" + attribute \src "libresoc.v:166438.3-166450.6" + wire width 2 $0\muxid$next[1:0]$9001 + attribute \src "libresoc.v:166231.3-166232.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:165725.3-165743.6" - wire width 64 $0\o$next[63:0]$9115 - attribute \src "libresoc.v:165423.3-165424.19" + attribute \src "libresoc.v:166493.3-166511.6" + wire width 64 $0\o$next[63:0]$9047 + attribute \src "libresoc.v:166191.3-166192.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:165725.3-165743.6" - wire $0\o_ok$next[0:0]$9116 - attribute \src "libresoc.v:165425.3-165426.25" + attribute \src "libresoc.v:166493.3-166511.6" + wire $0\o_ok$next[0:0]$9048 + attribute \src "libresoc.v:166193.3-166194.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:165652.3-165669.6" - wire $0\r_busy$next[0:0]$9065 - attribute \src "libresoc.v:165465.3-165466.29" + attribute \src "libresoc.v:166420.3-166437.6" + wire $0\r_busy$next[0:0]$8997 + attribute \src "libresoc.v:166233.3-166234.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:165595.3-165613.6" - wire width 2 $0\xer_ca$next[1:0]$9048 - attribute \src "libresoc.v:165415.3-165416.29" + attribute \src "libresoc.v:166363.3-166381.6" + wire width 2 $0\xer_ca$next[1:0]$8980 + attribute \src "libresoc.v:166183.3-166184.29" wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:165595.3-165613.6" - wire $0\xer_ca_ok$next[0:0]$9047 - attribute \src "libresoc.v:165417.3-165418.35" + attribute \src "libresoc.v:166363.3-166381.6" + wire $0\xer_ca_ok$next[0:0]$8979 + attribute \src "libresoc.v:166185.3-166186.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:165614.3-165632.6" - wire width 2 $0\xer_ov$next[1:0]$9053 - attribute \src "libresoc.v:165411.3-165412.29" + attribute \src "libresoc.v:166382.3-166400.6" + wire width 2 $0\xer_ov$next[1:0]$8985 + attribute \src "libresoc.v:166179.3-166180.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:165614.3-165632.6" - wire $0\xer_ov_ok$next[0:0]$9054 - attribute \src "libresoc.v:165413.3-165414.35" + attribute \src "libresoc.v:166382.3-166400.6" + wire $0\xer_ov_ok$next[0:0]$8986 + attribute \src "libresoc.v:166181.3-166182.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:165633.3-165651.6" - wire $0\xer_so$next[0:0]$9059 - attribute \src "libresoc.v:165407.3-165408.29" + attribute \src "libresoc.v:166401.3-166419.6" + wire $0\xer_so$next[0:0]$8991 + attribute \src "libresoc.v:166175.3-166176.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:165633.3-165651.6" - wire $0\xer_so_ok$next[0:0]$9060 - attribute \src "libresoc.v:165409.3-165410.35" + attribute \src "libresoc.v:166401.3-166419.6" + wire $0\xer_so_ok$next[0:0]$8992 + attribute \src "libresoc.v:166177.3-166178.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire width 4 $1\alu_op__data_len$next[3:0]$9090 - attribute \src "libresoc.v:164283.13-164283.36" + attribute \src "libresoc.v:166451.3-166492.6" + wire width 4 $1\alu_op__data_len$next[3:0]$9022 + attribute \src "libresoc.v:165051.13-165051.36" wire width 4 $1\alu_op__data_len[3:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire width 14 $1\alu_op__fn_unit$next[13:0]$9091 - attribute \src "libresoc.v:164307.14-164307.40" + attribute \src "libresoc.v:166451.3-166492.6" + wire width 14 $1\alu_op__fn_unit$next[13:0]$9023 + attribute \src "libresoc.v:165075.14-165075.40" wire width 14 $1\alu_op__fn_unit[13:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire width 64 $1\alu_op__imm_data__data$next[63:0]$9092 - attribute \src "libresoc.v:164346.14-164346.59" + attribute \src "libresoc.v:166451.3-166492.6" + wire width 64 $1\alu_op__imm_data__data$next[63:0]$9024 + attribute \src "libresoc.v:165114.14-165114.59" wire width 64 $1\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $1\alu_op__imm_data__ok$next[0:0]$9093 - attribute \src "libresoc.v:164355.7-164355.34" + attribute \src "libresoc.v:166451.3-166492.6" + wire $1\alu_op__imm_data__ok$next[0:0]$9025 + attribute \src "libresoc.v:165123.7-165123.34" wire $1\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire width 2 $1\alu_op__input_carry$next[1:0]$9094 - attribute \src "libresoc.v:164368.13-164368.39" + attribute \src "libresoc.v:166451.3-166492.6" + wire width 2 $1\alu_op__input_carry$next[1:0]$9026 + attribute \src "libresoc.v:165136.13-165136.39" wire width 2 $1\alu_op__input_carry[1:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire width 32 $1\alu_op__insn$next[31:0]$9095 - attribute \src "libresoc.v:164385.14-164385.34" + attribute \src "libresoc.v:166451.3-166492.6" + wire width 32 $1\alu_op__insn$next[31:0]$9027 + attribute \src "libresoc.v:165153.14-165153.34" wire width 32 $1\alu_op__insn[31:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire width 7 $1\alu_op__insn_type$next[6:0]$9096 - attribute \src "libresoc.v:164469.13-164469.38" + attribute \src "libresoc.v:166451.3-166492.6" + wire width 7 $1\alu_op__insn_type$next[6:0]$9028 + attribute \src "libresoc.v:165237.13-165237.38" wire width 7 $1\alu_op__insn_type[6:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $1\alu_op__invert_in$next[0:0]$9097 - attribute \src "libresoc.v:164628.7-164628.31" + attribute \src "libresoc.v:166451.3-166492.6" + wire $1\alu_op__invert_in$next[0:0]$9029 + attribute \src "libresoc.v:165396.7-165396.31" wire $1\alu_op__invert_in[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $1\alu_op__invert_out$next[0:0]$9098 - attribute \src "libresoc.v:164637.7-164637.32" + attribute \src "libresoc.v:166451.3-166492.6" + wire $1\alu_op__invert_out$next[0:0]$9030 + attribute \src "libresoc.v:165405.7-165405.32" wire $1\alu_op__invert_out[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $1\alu_op__is_32bit$next[0:0]$9099 - attribute \src "libresoc.v:164646.7-164646.30" + attribute \src "libresoc.v:166451.3-166492.6" + wire $1\alu_op__is_32bit$next[0:0]$9031 + attribute \src "libresoc.v:165414.7-165414.30" wire $1\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $1\alu_op__is_signed$next[0:0]$9100 - attribute \src "libresoc.v:164655.7-164655.31" + attribute \src "libresoc.v:166451.3-166492.6" + wire $1\alu_op__is_signed$next[0:0]$9032 + attribute \src "libresoc.v:165423.7-165423.31" wire $1\alu_op__is_signed[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $1\alu_op__oe__oe$next[0:0]$9101 - attribute \src "libresoc.v:164664.7-164664.28" + attribute \src "libresoc.v:166451.3-166492.6" + wire $1\alu_op__oe__oe$next[0:0]$9033 + attribute \src "libresoc.v:165432.7-165432.28" wire $1\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $1\alu_op__oe__ok$next[0:0]$9102 - attribute \src "libresoc.v:164673.7-164673.28" + attribute \src "libresoc.v:166451.3-166492.6" + wire $1\alu_op__oe__ok$next[0:0]$9034 + attribute \src "libresoc.v:165441.7-165441.28" wire $1\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $1\alu_op__output_carry$next[0:0]$9103 - attribute \src "libresoc.v:164682.7-164682.34" + attribute \src "libresoc.v:166451.3-166492.6" + wire $1\alu_op__output_carry$next[0:0]$9035 + attribute \src "libresoc.v:165450.7-165450.34" wire $1\alu_op__output_carry[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $1\alu_op__rc__ok$next[0:0]$9104 - attribute \src "libresoc.v:164691.7-164691.28" + attribute \src "libresoc.v:166451.3-166492.6" + wire $1\alu_op__rc__ok$next[0:0]$9036 + attribute \src "libresoc.v:165459.7-165459.28" wire $1\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $1\alu_op__rc__rc$next[0:0]$9105 - attribute \src "libresoc.v:164700.7-164700.28" + attribute \src "libresoc.v:166451.3-166492.6" + wire $1\alu_op__rc__rc$next[0:0]$9037 + attribute \src "libresoc.v:165468.7-165468.28" wire $1\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $1\alu_op__write_cr0$next[0:0]$9106 - attribute \src "libresoc.v:164709.7-164709.31" + attribute \src "libresoc.v:166451.3-166492.6" + wire $1\alu_op__write_cr0$next[0:0]$9038 + attribute \src "libresoc.v:165477.7-165477.31" wire $1\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire $1\alu_op__zero_a$next[0:0]$9107 - attribute \src "libresoc.v:164718.7-164718.28" + attribute \src "libresoc.v:166451.3-166492.6" + wire $1\alu_op__zero_a$next[0:0]$9039 + attribute \src "libresoc.v:165486.7-165486.28" wire $1\alu_op__zero_a[0:0] - attribute \src "libresoc.v:165576.3-165594.6" - wire width 4 $1\cr_a$next[3:0]$9043 - attribute \src "libresoc.v:164731.13-164731.24" + attribute \src "libresoc.v:166344.3-166362.6" + wire width 4 $1\cr_a$next[3:0]$8975 + attribute \src "libresoc.v:165499.13-165499.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:165576.3-165594.6" - wire $1\cr_a_ok$next[0:0]$9044 - attribute \src "libresoc.v:164738.7-164738.21" + attribute \src "libresoc.v:166344.3-166362.6" + wire $1\cr_a_ok$next[0:0]$8976 + attribute \src "libresoc.v:165506.7-165506.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:165670.3-165682.6" - wire width 2 $1\muxid$next[1:0]$9070 - attribute \src "libresoc.v:165315.13-165315.25" + attribute \src "libresoc.v:166438.3-166450.6" + wire width 2 $1\muxid$next[1:0]$9002 + attribute \src "libresoc.v:166083.13-166083.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:165725.3-165743.6" - wire width 64 $1\o$next[63:0]$9117 - attribute \src "libresoc.v:165330.14-165330.38" + attribute \src "libresoc.v:166493.3-166511.6" + wire width 64 $1\o$next[63:0]$9049 + attribute \src "libresoc.v:166098.14-166098.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:165725.3-165743.6" - wire $1\o_ok$next[0:0]$9118 - attribute \src "libresoc.v:165337.7-165337.18" + attribute \src "libresoc.v:166493.3-166511.6" + wire $1\o_ok$next[0:0]$9050 + attribute \src "libresoc.v:166105.7-166105.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:165652.3-165669.6" - wire $1\r_busy$next[0:0]$9066 - attribute \src "libresoc.v:165351.7-165351.20" + attribute \src "libresoc.v:166420.3-166437.6" + wire $1\r_busy$next[0:0]$8998 + attribute \src "libresoc.v:166119.7-166119.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:165595.3-165613.6" - wire width 2 $1\xer_ca$next[1:0]$9050 - attribute \src "libresoc.v:165360.13-165360.26" + attribute \src "libresoc.v:166363.3-166381.6" + wire width 2 $1\xer_ca$next[1:0]$8982 + attribute \src "libresoc.v:166128.13-166128.26" wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:165595.3-165613.6" - wire $1\xer_ca_ok$next[0:0]$9049 - attribute \src "libresoc.v:165369.7-165369.23" + attribute \src "libresoc.v:166363.3-166381.6" + wire $1\xer_ca_ok$next[0:0]$8981 + attribute \src "libresoc.v:166137.7-166137.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:165614.3-165632.6" - wire width 2 $1\xer_ov$next[1:0]$9055 - attribute \src "libresoc.v:165376.13-165376.26" + attribute \src "libresoc.v:166382.3-166400.6" + wire width 2 $1\xer_ov$next[1:0]$8987 + attribute \src "libresoc.v:166144.13-166144.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:165614.3-165632.6" - wire $1\xer_ov_ok$next[0:0]$9056 - attribute \src "libresoc.v:165383.7-165383.23" + attribute \src "libresoc.v:166382.3-166400.6" + wire $1\xer_ov_ok$next[0:0]$8988 + attribute \src "libresoc.v:166151.7-166151.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:165633.3-165651.6" - wire $1\xer_so$next[0:0]$9061 - attribute \src "libresoc.v:165390.7-165390.20" + attribute \src "libresoc.v:166401.3-166419.6" + wire $1\xer_so$next[0:0]$8993 + attribute \src "libresoc.v:166158.7-166158.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:165633.3-165651.6" - wire $1\xer_so_ok$next[0:0]$9062 - attribute \src "libresoc.v:165399.7-165399.23" + attribute \src "libresoc.v:166401.3-166419.6" + wire $1\xer_so_ok$next[0:0]$8994 + attribute \src "libresoc.v:166167.7-166167.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" - wire width 64 $2\alu_op__imm_data__data$next[63:0]$9108 - attribute \src "libresoc.v:165683.3-165724.6" - wire $2\alu_op__imm_data__ok$next[0:0]$9109 - attribute \src "libresoc.v:165683.3-165724.6" - wire $2\alu_op__oe__oe$next[0:0]$9110 - attribute \src "libresoc.v:165683.3-165724.6" - wire $2\alu_op__oe__ok$next[0:0]$9111 - attribute \src "libresoc.v:165683.3-165724.6" - wire $2\alu_op__rc__ok$next[0:0]$9112 - attribute \src "libresoc.v:165683.3-165724.6" - wire $2\alu_op__rc__rc$next[0:0]$9113 - attribute \src "libresoc.v:165576.3-165594.6" - wire $2\cr_a_ok$next[0:0]$9045 - attribute \src "libresoc.v:165725.3-165743.6" - wire $2\o_ok$next[0:0]$9119 - attribute \src "libresoc.v:165652.3-165669.6" - wire $2\r_busy$next[0:0]$9067 - attribute \src "libresoc.v:165595.3-165613.6" - wire $2\xer_ca_ok$next[0:0]$9051 - attribute \src "libresoc.v:165614.3-165632.6" - wire $2\xer_ov_ok$next[0:0]$9057 - attribute \src "libresoc.v:165633.3-165651.6" - wire $2\xer_so_ok$next[0:0]$9063 - attribute \src "libresoc.v:165406.18-165406.118" - wire $and$libresoc.v:165406$9009_Y + attribute \src "libresoc.v:166451.3-166492.6" + wire width 64 $2\alu_op__imm_data__data$next[63:0]$9040 + attribute \src "libresoc.v:166451.3-166492.6" + wire $2\alu_op__imm_data__ok$next[0:0]$9041 + attribute \src "libresoc.v:166451.3-166492.6" + wire $2\alu_op__oe__oe$next[0:0]$9042 + attribute \src "libresoc.v:166451.3-166492.6" + wire $2\alu_op__oe__ok$next[0:0]$9043 + attribute \src "libresoc.v:166451.3-166492.6" + wire $2\alu_op__rc__ok$next[0:0]$9044 + attribute \src "libresoc.v:166451.3-166492.6" + wire $2\alu_op__rc__rc$next[0:0]$9045 + attribute \src "libresoc.v:166344.3-166362.6" + wire $2\cr_a_ok$next[0:0]$8977 + attribute \src "libresoc.v:166493.3-166511.6" + wire $2\o_ok$next[0:0]$9051 + attribute \src "libresoc.v:166420.3-166437.6" + wire $2\r_busy$next[0:0]$8999 + attribute \src "libresoc.v:166363.3-166381.6" + wire $2\xer_ca_ok$next[0:0]$8983 + attribute \src "libresoc.v:166382.3-166400.6" + wire $2\xer_ov_ok$next[0:0]$8989 + attribute \src "libresoc.v:166401.3-166419.6" + wire $2\xer_so_ok$next[0:0]$8995 + attribute \src "libresoc.v:166174.18-166174.118" + wire $and$libresoc.v:166174$8941_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -340811,23 +307354,23 @@ module \pipe1 wire \alu_op__zero_a$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next - attribute \src "libresoc.v:164278.7-164278.15" + attribute \src "libresoc.v:165046.7-165046.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_alu_op__data_len @@ -341369,17 +307912,17 @@ module \pipe1 wire \main_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__zero_a$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \main_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_ra @@ -341387,17 +307930,17 @@ module \pipe1 wire width 64 \main_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \main_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \main_xer_ca$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \main_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_xer_so$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid @@ -341413,17 +307956,17 @@ module \pipe1 wire input 3 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 34 \p_ready_o @@ -341441,50 +307984,50 @@ module \pipe1 wire width 64 input 54 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 55 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 27 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 57 \xer_ca$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 29 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 30 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 31 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 56 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 32 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:165406$9009 + cell $and $and$libresoc.v:166174$8941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -341492,10 +308035,10 @@ module \pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$66 connect \B \p_ready_o - connect \Y $and$libresoc.v:165406$9009_Y + connect \Y $and$libresoc.v:166174$8941_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:165467.11-165514.4" + attribute \src "libresoc.v:166235.11-166282.4" cell \input \input connect \alu_op__data_len \input_alu_op__data_len connect \alu_op__data_len$18 \input_alu_op__data_len$39 @@ -341545,7 +308088,7 @@ module \pipe1 connect \xer_so$22 \input_xer_so$43 end attribute \module_not_derived 1 - attribute \src "libresoc.v:165515.8-165567.4" + attribute \src "libresoc.v:166283.8-166335.4" cell \main \main connect \alu_op__data_len \main_alu_op__data_len connect \alu_op__data_len$18 \main_alu_op__data_len$62 @@ -341600,487 +308143,487 @@ module \pipe1 connect \xer_so$21 \main_xer_so$65 end attribute \module_not_derived 1 - attribute \src "libresoc.v:165568.9-165571.4" + attribute \src "libresoc.v:166336.9-166339.4" cell \n$2 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:165572.9-165575.4" + attribute \src "libresoc.v:166340.9-166343.4" cell \p$1 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:164278.7-164278.20" - process $proc$libresoc.v:164278$9120 + attribute \src "libresoc.v:165046.7-165046.20" + process $proc$libresoc.v:165046$9052 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:164283.13-164283.36" - process $proc$libresoc.v:164283$9121 + attribute \src "libresoc.v:165051.13-165051.36" + process $proc$libresoc.v:165051$9053 assign { } { } assign $1\alu_op__data_len[3:0] 4'0000 sync always sync init update \alu_op__data_len $1\alu_op__data_len[3:0] end - attribute \src "libresoc.v:164307.14-164307.40" - process $proc$libresoc.v:164307$9122 + attribute \src "libresoc.v:165075.14-165075.40" + process $proc$libresoc.v:165075$9054 assign { } { } assign $1\alu_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_op__fn_unit $1\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:164346.14-164346.59" - process $proc$libresoc.v:164346$9123 + attribute \src "libresoc.v:165114.14-165114.59" + process $proc$libresoc.v:165114$9055 assign { } { } assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:164355.7-164355.34" - process $proc$libresoc.v:164355$9124 + attribute \src "libresoc.v:165123.7-165123.34" + process $proc$libresoc.v:165123$9056 assign { } { } assign $1\alu_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:164368.13-164368.39" - process $proc$libresoc.v:164368$9125 + attribute \src "libresoc.v:165136.13-165136.39" + process $proc$libresoc.v:165136$9057 assign { } { } assign $1\alu_op__input_carry[1:0] 2'00 sync always sync init update \alu_op__input_carry $1\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:164385.14-164385.34" - process $proc$libresoc.v:164385$9126 + attribute \src "libresoc.v:165153.14-165153.34" + process $proc$libresoc.v:165153$9058 assign { } { } assign $1\alu_op__insn[31:0] 0 sync always sync init update \alu_op__insn $1\alu_op__insn[31:0] end - attribute \src "libresoc.v:164469.13-164469.38" - process $proc$libresoc.v:164469$9127 + attribute \src "libresoc.v:165237.13-165237.38" + process $proc$libresoc.v:165237$9059 assign { } { } assign $1\alu_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_op__insn_type $1\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:164628.7-164628.31" - process $proc$libresoc.v:164628$9128 + attribute \src "libresoc.v:165396.7-165396.31" + process $proc$libresoc.v:165396$9060 assign { } { } assign $1\alu_op__invert_in[0:0] 1'0 sync always sync init update \alu_op__invert_in $1\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:164637.7-164637.32" - process $proc$libresoc.v:164637$9129 + attribute \src "libresoc.v:165405.7-165405.32" + process $proc$libresoc.v:165405$9061 assign { } { } assign $1\alu_op__invert_out[0:0] 1'0 sync always sync init update \alu_op__invert_out $1\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:164646.7-164646.30" - process $proc$libresoc.v:164646$9130 + attribute \src "libresoc.v:165414.7-165414.30" + process $proc$libresoc.v:165414$9062 assign { } { } assign $1\alu_op__is_32bit[0:0] 1'0 sync always sync init update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:164655.7-164655.31" - process $proc$libresoc.v:164655$9131 + attribute \src "libresoc.v:165423.7-165423.31" + process $proc$libresoc.v:165423$9063 assign { } { } assign $1\alu_op__is_signed[0:0] 1'0 sync always sync init update \alu_op__is_signed $1\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:164664.7-164664.28" - process $proc$libresoc.v:164664$9132 + attribute \src "libresoc.v:165432.7-165432.28" + process $proc$libresoc.v:165432$9064 assign { } { } assign $1\alu_op__oe__oe[0:0] 1'0 sync always sync init update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:164673.7-164673.28" - process $proc$libresoc.v:164673$9133 + attribute \src "libresoc.v:165441.7-165441.28" + process $proc$libresoc.v:165441$9065 assign { } { } assign $1\alu_op__oe__ok[0:0] 1'0 sync always sync init update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:164682.7-164682.34" - process $proc$libresoc.v:164682$9134 + attribute \src "libresoc.v:165450.7-165450.34" + process $proc$libresoc.v:165450$9066 assign { } { } assign $1\alu_op__output_carry[0:0] 1'0 sync always sync init update \alu_op__output_carry $1\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:164691.7-164691.28" - process $proc$libresoc.v:164691$9135 + attribute \src "libresoc.v:165459.7-165459.28" + process $proc$libresoc.v:165459$9067 assign { } { } assign $1\alu_op__rc__ok[0:0] 1'0 sync always sync init update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:164700.7-164700.28" - process $proc$libresoc.v:164700$9136 + attribute \src "libresoc.v:165468.7-165468.28" + process $proc$libresoc.v:165468$9068 assign { } { } assign $1\alu_op__rc__rc[0:0] 1'0 sync always sync init update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:164709.7-164709.31" - process $proc$libresoc.v:164709$9137 + attribute \src "libresoc.v:165477.7-165477.31" + process $proc$libresoc.v:165477$9069 assign { } { } assign $1\alu_op__write_cr0[0:0] 1'0 sync always sync init update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:164718.7-164718.28" - process $proc$libresoc.v:164718$9138 + attribute \src "libresoc.v:165486.7-165486.28" + process $proc$libresoc.v:165486$9070 assign { } { } assign $1\alu_op__zero_a[0:0] 1'0 sync always sync init update \alu_op__zero_a $1\alu_op__zero_a[0:0] end - attribute \src "libresoc.v:164731.13-164731.24" - process $proc$libresoc.v:164731$9139 + attribute \src "libresoc.v:165499.13-165499.24" + process $proc$libresoc.v:165499$9071 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:164738.7-164738.21" - process $proc$libresoc.v:164738$9140 + attribute \src "libresoc.v:165506.7-165506.21" + process $proc$libresoc.v:165506$9072 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:165315.13-165315.25" - process $proc$libresoc.v:165315$9141 + attribute \src "libresoc.v:166083.13-166083.25" + process $proc$libresoc.v:166083$9073 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:165330.14-165330.38" - process $proc$libresoc.v:165330$9142 + attribute \src "libresoc.v:166098.14-166098.38" + process $proc$libresoc.v:166098$9074 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:165337.7-165337.18" - process $proc$libresoc.v:165337$9143 + attribute \src "libresoc.v:166105.7-166105.18" + process $proc$libresoc.v:166105$9075 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:165351.7-165351.20" - process $proc$libresoc.v:165351$9144 + attribute \src "libresoc.v:166119.7-166119.20" + process $proc$libresoc.v:166119$9076 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:165360.13-165360.26" - process $proc$libresoc.v:165360$9145 + attribute \src "libresoc.v:166128.13-166128.26" + process $proc$libresoc.v:166128$9077 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:165369.7-165369.23" - process $proc$libresoc.v:165369$9146 + attribute \src "libresoc.v:166137.7-166137.23" + process $proc$libresoc.v:166137$9078 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:165376.13-165376.26" - process $proc$libresoc.v:165376$9147 + attribute \src "libresoc.v:166144.13-166144.26" + process $proc$libresoc.v:166144$9079 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:165383.7-165383.23" - process $proc$libresoc.v:165383$9148 + attribute \src "libresoc.v:166151.7-166151.23" + process $proc$libresoc.v:166151$9080 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:165390.7-165390.20" - process $proc$libresoc.v:165390$9149 + attribute \src "libresoc.v:166158.7-166158.20" + process $proc$libresoc.v:166158$9081 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:165399.7-165399.23" - process $proc$libresoc.v:165399$9150 + attribute \src "libresoc.v:166167.7-166167.23" + process $proc$libresoc.v:166167$9082 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:165407.3-165408.29" - process $proc$libresoc.v:165407$9010 + attribute \src "libresoc.v:166175.3-166176.29" + process $proc$libresoc.v:166175$8942 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:165409.3-165410.35" - process $proc$libresoc.v:165409$9011 + attribute \src "libresoc.v:166177.3-166178.35" + process $proc$libresoc.v:166177$8943 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:165411.3-165412.29" - process $proc$libresoc.v:165411$9012 + attribute \src "libresoc.v:166179.3-166180.29" + process $proc$libresoc.v:166179$8944 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:165413.3-165414.35" - process $proc$libresoc.v:165413$9013 + attribute \src "libresoc.v:166181.3-166182.35" + process $proc$libresoc.v:166181$8945 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:165415.3-165416.29" - process $proc$libresoc.v:165415$9014 + attribute \src "libresoc.v:166183.3-166184.29" + process $proc$libresoc.v:166183$8946 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:165417.3-165418.35" - process $proc$libresoc.v:165417$9015 + attribute \src "libresoc.v:166185.3-166186.35" + process $proc$libresoc.v:166185$8947 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:165419.3-165420.25" - process $proc$libresoc.v:165419$9016 + attribute \src "libresoc.v:166187.3-166188.25" + process $proc$libresoc.v:166187$8948 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:165421.3-165422.31" - process $proc$libresoc.v:165421$9017 + attribute \src "libresoc.v:166189.3-166190.31" + process $proc$libresoc.v:166189$8949 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:165423.3-165424.19" - process $proc$libresoc.v:165423$9018 + attribute \src "libresoc.v:166191.3-166192.19" + process $proc$libresoc.v:166191$8950 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:165425.3-165426.25" - process $proc$libresoc.v:165425$9019 + attribute \src "libresoc.v:166193.3-166194.25" + process $proc$libresoc.v:166193$8951 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:165427.3-165428.51" - process $proc$libresoc.v:165427$9020 + attribute \src "libresoc.v:166195.3-166196.51" + process $proc$libresoc.v:166195$8952 assign { } { } assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next sync posedge \coresync_clk update \alu_op__insn_type $0\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:165429.3-165430.47" - process $proc$libresoc.v:165429$9021 + attribute \src "libresoc.v:166197.3-166198.47" + process $proc$libresoc.v:166197$8953 assign { } { } assign $0\alu_op__fn_unit[13:0] \alu_op__fn_unit$next sync posedge \coresync_clk update \alu_op__fn_unit $0\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:165431.3-165432.61" - process $proc$libresoc.v:165431$9022 + attribute \src "libresoc.v:166199.3-166200.61" + process $proc$libresoc.v:166199$8954 assign { } { } assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next sync posedge \coresync_clk update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:165433.3-165434.57" - process $proc$libresoc.v:165433$9023 + attribute \src "libresoc.v:166201.3-166202.57" + process $proc$libresoc.v:166201$8955 assign { } { } assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next sync posedge \coresync_clk update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:165435.3-165436.45" - process $proc$libresoc.v:165435$9024 + attribute \src "libresoc.v:166203.3-166204.45" + process $proc$libresoc.v:166203$8956 assign { } { } assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next sync posedge \coresync_clk update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:165437.3-165438.45" - process $proc$libresoc.v:165437$9025 + attribute \src "libresoc.v:166205.3-166206.45" + process $proc$libresoc.v:166205$8957 assign { } { } assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next sync posedge \coresync_clk update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:165439.3-165440.45" - process $proc$libresoc.v:165439$9026 + attribute \src "libresoc.v:166207.3-166208.45" + process $proc$libresoc.v:166207$8958 assign { } { } assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next sync posedge \coresync_clk update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:165441.3-165442.45" - process $proc$libresoc.v:165441$9027 + attribute \src "libresoc.v:166209.3-166210.45" + process $proc$libresoc.v:166209$8959 assign { } { } assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next sync posedge \coresync_clk update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:165443.3-165444.51" - process $proc$libresoc.v:165443$9028 + attribute \src "libresoc.v:166211.3-166212.51" + process $proc$libresoc.v:166211$8960 assign { } { } assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next sync posedge \coresync_clk update \alu_op__invert_in $0\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:165445.3-165446.45" - process $proc$libresoc.v:165445$9029 + attribute \src "libresoc.v:166213.3-166214.45" + process $proc$libresoc.v:166213$8961 assign { } { } assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next sync posedge \coresync_clk update \alu_op__zero_a $0\alu_op__zero_a[0:0] end - attribute \src "libresoc.v:165447.3-165448.53" - process $proc$libresoc.v:165447$9030 + attribute \src "libresoc.v:166215.3-166216.53" + process $proc$libresoc.v:166215$8962 assign { } { } assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next sync posedge \coresync_clk update \alu_op__invert_out $0\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:165449.3-165450.51" - process $proc$libresoc.v:165449$9031 + attribute \src "libresoc.v:166217.3-166218.51" + process $proc$libresoc.v:166217$8963 assign { } { } assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next sync posedge \coresync_clk update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:165451.3-165452.55" - process $proc$libresoc.v:165451$9032 + attribute \src "libresoc.v:166219.3-166220.55" + process $proc$libresoc.v:166219$8964 assign { } { } assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next sync posedge \coresync_clk update \alu_op__input_carry $0\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:165453.3-165454.57" - process $proc$libresoc.v:165453$9033 + attribute \src "libresoc.v:166221.3-166222.57" + process $proc$libresoc.v:166221$8965 assign { } { } assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next sync posedge \coresync_clk update \alu_op__output_carry $0\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:165455.3-165456.49" - process $proc$libresoc.v:165455$9034 + attribute \src "libresoc.v:166223.3-166224.49" + process $proc$libresoc.v:166223$8966 assign { } { } assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next sync posedge \coresync_clk update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:165457.3-165458.51" - process $proc$libresoc.v:165457$9035 + attribute \src "libresoc.v:166225.3-166226.51" + process $proc$libresoc.v:166225$8967 assign { } { } assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next sync posedge \coresync_clk update \alu_op__is_signed $0\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:165459.3-165460.49" - process $proc$libresoc.v:165459$9036 + attribute \src "libresoc.v:166227.3-166228.49" + process $proc$libresoc.v:166227$8968 assign { } { } assign $0\alu_op__data_len[3:0] \alu_op__data_len$next sync posedge \coresync_clk update \alu_op__data_len $0\alu_op__data_len[3:0] end - attribute \src "libresoc.v:165461.3-165462.41" - process $proc$libresoc.v:165461$9037 + attribute \src "libresoc.v:166229.3-166230.41" + process $proc$libresoc.v:166229$8969 assign { } { } assign $0\alu_op__insn[31:0] \alu_op__insn$next sync posedge \coresync_clk update \alu_op__insn $0\alu_op__insn[31:0] end - attribute \src "libresoc.v:165463.3-165464.27" - process $proc$libresoc.v:165463$9038 + attribute \src "libresoc.v:166231.3-166232.27" + process $proc$libresoc.v:166231$8970 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:165465.3-165466.29" - process $proc$libresoc.v:165465$9039 + attribute \src "libresoc.v:166233.3-166234.29" + process $proc$libresoc.v:166233$8971 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:165576.3-165594.6" - process $proc$libresoc.v:165576$9040 + attribute \src "libresoc.v:166344.3-166362.6" + process $proc$libresoc.v:166344$8972 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9041 $1\cr_a$next[3:0]$9043 + assign $0\cr_a$next[3:0]$8973 $1\cr_a$next[3:0]$8975 assign { } { } - assign $0\cr_a_ok$next[0:0]$9042 $2\cr_a_ok$next[0:0]$9045 - attribute \src "libresoc.v:165577.5-165577.29" + assign $0\cr_a_ok$next[0:0]$8974 $2\cr_a_ok$next[0:0]$8977 + attribute \src "libresoc.v:166345.5-166345.29" switch \initial - attribute \src "libresoc.v:165577.9-165577.17" + attribute \src "libresoc.v:166345.9-166345.17" case 1'1 case end @@ -342090,41 +308633,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9044 $1\cr_a$next[3:0]$9043 } { \cr_a_ok$91 \cr_a$90 } + assign { $1\cr_a_ok$next[0:0]$8976 $1\cr_a$next[3:0]$8975 } { \cr_a_ok$91 \cr_a$90 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9044 $1\cr_a$next[3:0]$9043 } { \cr_a_ok$91 \cr_a$90 } + assign { $1\cr_a_ok$next[0:0]$8976 $1\cr_a$next[3:0]$8975 } { \cr_a_ok$91 \cr_a$90 } case - assign $1\cr_a$next[3:0]$9043 \cr_a - assign $1\cr_a_ok$next[0:0]$9044 \cr_a_ok + assign $1\cr_a$next[3:0]$8975 \cr_a + assign $1\cr_a_ok$next[0:0]$8976 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9045 1'0 + assign $2\cr_a_ok$next[0:0]$8977 1'0 case - assign $2\cr_a_ok$next[0:0]$9045 $1\cr_a_ok$next[0:0]$9044 + assign $2\cr_a_ok$next[0:0]$8977 $1\cr_a_ok$next[0:0]$8976 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9041 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9042 + update \cr_a$next $0\cr_a$next[3:0]$8973 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8974 end - attribute \src "libresoc.v:165595.3-165613.6" - process $proc$libresoc.v:165595$9046 + attribute \src "libresoc.v:166363.3-166381.6" + process $proc$libresoc.v:166363$8978 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$next[1:0]$9048 $1\xer_ca$next[1:0]$9050 - assign $0\xer_ca_ok$next[0:0]$9047 $2\xer_ca_ok$next[0:0]$9051 - attribute \src "libresoc.v:165596.5-165596.29" + assign $0\xer_ca$next[1:0]$8980 $1\xer_ca$next[1:0]$8982 + assign $0\xer_ca_ok$next[0:0]$8979 $2\xer_ca_ok$next[0:0]$8983 + attribute \src "libresoc.v:166364.5-166364.29" switch \initial - attribute \src "libresoc.v:165596.9-165596.17" + attribute \src "libresoc.v:166364.9-166364.17" case 1'1 case end @@ -342134,41 +308677,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9049 $1\xer_ca$next[1:0]$9050 } { \xer_ca_ok$93 \xer_ca$92 } + assign { $1\xer_ca_ok$next[0:0]$8981 $1\xer_ca$next[1:0]$8982 } { \xer_ca_ok$93 \xer_ca$92 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9049 $1\xer_ca$next[1:0]$9050 } { \xer_ca_ok$93 \xer_ca$92 } + assign { $1\xer_ca_ok$next[0:0]$8981 $1\xer_ca$next[1:0]$8982 } { \xer_ca_ok$93 \xer_ca$92 } case - assign $1\xer_ca_ok$next[0:0]$9049 \xer_ca_ok - assign $1\xer_ca$next[1:0]$9050 \xer_ca + assign $1\xer_ca_ok$next[0:0]$8981 \xer_ca_ok + assign $1\xer_ca$next[1:0]$8982 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$9051 1'0 + assign $2\xer_ca_ok$next[0:0]$8983 1'0 case - assign $2\xer_ca_ok$next[0:0]$9051 $1\xer_ca_ok$next[0:0]$9049 + assign $2\xer_ca_ok$next[0:0]$8983 $1\xer_ca_ok$next[0:0]$8981 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9047 - update \xer_ca$next $0\xer_ca$next[1:0]$9048 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8979 + update \xer_ca$next $0\xer_ca$next[1:0]$8980 end - attribute \src "libresoc.v:165614.3-165632.6" - process $proc$libresoc.v:165614$9052 + attribute \src "libresoc.v:166382.3-166400.6" + process $proc$libresoc.v:166382$8984 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$9053 $1\xer_ov$next[1:0]$9055 + assign $0\xer_ov$next[1:0]$8985 $1\xer_ov$next[1:0]$8987 assign { } { } - assign $0\xer_ov_ok$next[0:0]$9054 $2\xer_ov_ok$next[0:0]$9057 - attribute \src "libresoc.v:165615.5-165615.29" + assign $0\xer_ov_ok$next[0:0]$8986 $2\xer_ov_ok$next[0:0]$8989 + attribute \src "libresoc.v:166383.5-166383.29" switch \initial - attribute \src "libresoc.v:165615.9-165615.17" + attribute \src "libresoc.v:166383.9-166383.17" case 1'1 case end @@ -342178,41 +308721,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9056 $1\xer_ov$next[1:0]$9055 } { \xer_ov_ok$95 \xer_ov$94 } + assign { $1\xer_ov_ok$next[0:0]$8988 $1\xer_ov$next[1:0]$8987 } { \xer_ov_ok$95 \xer_ov$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9056 $1\xer_ov$next[1:0]$9055 } { \xer_ov_ok$95 \xer_ov$94 } + assign { $1\xer_ov_ok$next[0:0]$8988 $1\xer_ov$next[1:0]$8987 } { \xer_ov_ok$95 \xer_ov$94 } case - assign $1\xer_ov$next[1:0]$9055 \xer_ov - assign $1\xer_ov_ok$next[0:0]$9056 \xer_ov_ok + assign $1\xer_ov$next[1:0]$8987 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8988 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$9057 1'0 + assign $2\xer_ov_ok$next[0:0]$8989 1'0 case - assign $2\xer_ov_ok$next[0:0]$9057 $1\xer_ov_ok$next[0:0]$9056 + assign $2\xer_ov_ok$next[0:0]$8989 $1\xer_ov_ok$next[0:0]$8988 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$9053 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9054 + update \xer_ov$next $0\xer_ov$next[1:0]$8985 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8986 end - attribute \src "libresoc.v:165633.3-165651.6" - process $proc$libresoc.v:165633$9058 + attribute \src "libresoc.v:166401.3-166419.6" + process $proc$libresoc.v:166401$8990 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$9059 $1\xer_so$next[0:0]$9061 + assign $0\xer_so$next[0:0]$8991 $1\xer_so$next[0:0]$8993 assign { } { } - assign $0\xer_so_ok$next[0:0]$9060 $2\xer_so_ok$next[0:0]$9063 - attribute \src "libresoc.v:165634.5-165634.29" + assign $0\xer_so_ok$next[0:0]$8992 $2\xer_so_ok$next[0:0]$8995 + attribute \src "libresoc.v:166402.5-166402.29" switch \initial - attribute \src "libresoc.v:165634.9-165634.17" + attribute \src "libresoc.v:166402.9-166402.17" case 1'1 case end @@ -342222,38 +308765,38 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9062 $1\xer_so$next[0:0]$9061 } { \xer_so_ok$97 \xer_so$96 } + assign { $1\xer_so_ok$next[0:0]$8994 $1\xer_so$next[0:0]$8993 } { \xer_so_ok$97 \xer_so$96 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9062 $1\xer_so$next[0:0]$9061 } { \xer_so_ok$97 \xer_so$96 } + assign { $1\xer_so_ok$next[0:0]$8994 $1\xer_so$next[0:0]$8993 } { \xer_so_ok$97 \xer_so$96 } case - assign $1\xer_so$next[0:0]$9061 \xer_so - assign $1\xer_so_ok$next[0:0]$9062 \xer_so_ok + assign $1\xer_so$next[0:0]$8993 \xer_so + assign $1\xer_so_ok$next[0:0]$8994 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9063 1'0 + assign $2\xer_so_ok$next[0:0]$8995 1'0 case - assign $2\xer_so_ok$next[0:0]$9063 $1\xer_so_ok$next[0:0]$9062 + assign $2\xer_so_ok$next[0:0]$8995 $1\xer_so_ok$next[0:0]$8994 end sync always - update \xer_so$next $0\xer_so$next[0:0]$9059 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9060 + update \xer_so$next $0\xer_so$next[0:0]$8991 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8992 end - attribute \src "libresoc.v:165652.3-165669.6" - process $proc$libresoc.v:165652$9064 + attribute \src "libresoc.v:166420.3-166437.6" + process $proc$libresoc.v:166420$8996 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9065 $2\r_busy$next[0:0]$9067 - attribute \src "libresoc.v:165653.5-165653.29" + assign $0\r_busy$next[0:0]$8997 $2\r_busy$next[0:0]$8999 + attribute \src "libresoc.v:166421.5-166421.29" switch \initial - attribute \src "libresoc.v:165653.9-165653.17" + attribute \src "libresoc.v:166421.9-166421.17" case 1'1 case end @@ -342262,34 +308805,34 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9066 1'1 + assign $1\r_busy$next[0:0]$8998 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9066 1'0 + assign $1\r_busy$next[0:0]$8998 1'0 case - assign $1\r_busy$next[0:0]$9066 \r_busy + assign $1\r_busy$next[0:0]$8998 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9067 1'0 + assign $2\r_busy$next[0:0]$8999 1'0 case - assign $2\r_busy$next[0:0]$9067 $1\r_busy$next[0:0]$9066 + assign $2\r_busy$next[0:0]$8999 $1\r_busy$next[0:0]$8998 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9065 + update \r_busy$next $0\r_busy$next[0:0]$8997 end - attribute \src "libresoc.v:165670.3-165682.6" - process $proc$libresoc.v:165670$9068 + attribute \src "libresoc.v:166438.3-166450.6" + process $proc$libresoc.v:166438$9000 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9069 $1\muxid$next[1:0]$9070 - attribute \src "libresoc.v:165671.5-165671.29" + assign $0\muxid$next[1:0]$9001 $1\muxid$next[1:0]$9002 + attribute \src "libresoc.v:166439.5-166439.29" switch \initial - attribute \src "libresoc.v:165671.9-165671.17" + attribute \src "libresoc.v:166439.9-166439.17" case 1'1 case end @@ -342298,19 +308841,19 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9070 \muxid$69 + assign $1\muxid$next[1:0]$9002 \muxid$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9070 \muxid$69 + assign $1\muxid$next[1:0]$9002 \muxid$69 case - assign $1\muxid$next[1:0]$9070 \muxid + assign $1\muxid$next[1:0]$9002 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9069 + update \muxid$next $0\muxid$next[1:0]$9001 end - attribute \src "libresoc.v:165683.3-165724.6" - process $proc$libresoc.v:165683$9071 + attribute \src "libresoc.v:166451.3-166492.6" + process $proc$libresoc.v:166451$9003 assign { } { } assign { } { } assign { } { } @@ -342347,33 +308890,33 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign $0\alu_op__data_len$next[3:0]$9072 $1\alu_op__data_len$next[3:0]$9090 - assign $0\alu_op__fn_unit$next[13:0]$9073 $1\alu_op__fn_unit$next[13:0]$9091 + assign $0\alu_op__data_len$next[3:0]$9004 $1\alu_op__data_len$next[3:0]$9022 + assign $0\alu_op__fn_unit$next[13:0]$9005 $1\alu_op__fn_unit$next[13:0]$9023 assign { } { } assign { } { } - assign $0\alu_op__input_carry$next[1:0]$9076 $1\alu_op__input_carry$next[1:0]$9094 - assign $0\alu_op__insn$next[31:0]$9077 $1\alu_op__insn$next[31:0]$9095 - assign $0\alu_op__insn_type$next[6:0]$9078 $1\alu_op__insn_type$next[6:0]$9096 - assign $0\alu_op__invert_in$next[0:0]$9079 $1\alu_op__invert_in$next[0:0]$9097 - assign $0\alu_op__invert_out$next[0:0]$9080 $1\alu_op__invert_out$next[0:0]$9098 - assign $0\alu_op__is_32bit$next[0:0]$9081 $1\alu_op__is_32bit$next[0:0]$9099 - assign $0\alu_op__is_signed$next[0:0]$9082 $1\alu_op__is_signed$next[0:0]$9100 + assign $0\alu_op__input_carry$next[1:0]$9008 $1\alu_op__input_carry$next[1:0]$9026 + assign $0\alu_op__insn$next[31:0]$9009 $1\alu_op__insn$next[31:0]$9027 + assign $0\alu_op__insn_type$next[6:0]$9010 $1\alu_op__insn_type$next[6:0]$9028 + assign $0\alu_op__invert_in$next[0:0]$9011 $1\alu_op__invert_in$next[0:0]$9029 + assign $0\alu_op__invert_out$next[0:0]$9012 $1\alu_op__invert_out$next[0:0]$9030 + assign $0\alu_op__is_32bit$next[0:0]$9013 $1\alu_op__is_32bit$next[0:0]$9031 + assign $0\alu_op__is_signed$next[0:0]$9014 $1\alu_op__is_signed$next[0:0]$9032 assign { } { } assign { } { } - assign $0\alu_op__output_carry$next[0:0]$9085 $1\alu_op__output_carry$next[0:0]$9103 + assign $0\alu_op__output_carry$next[0:0]$9017 $1\alu_op__output_carry$next[0:0]$9035 assign { } { } assign { } { } - assign $0\alu_op__write_cr0$next[0:0]$9088 $1\alu_op__write_cr0$next[0:0]$9106 - assign $0\alu_op__zero_a$next[0:0]$9089 $1\alu_op__zero_a$next[0:0]$9107 - assign $0\alu_op__imm_data__data$next[63:0]$9074 $2\alu_op__imm_data__data$next[63:0]$9108 - assign $0\alu_op__imm_data__ok$next[0:0]$9075 $2\alu_op__imm_data__ok$next[0:0]$9109 - assign $0\alu_op__oe__oe$next[0:0]$9083 $2\alu_op__oe__oe$next[0:0]$9110 - assign $0\alu_op__oe__ok$next[0:0]$9084 $2\alu_op__oe__ok$next[0:0]$9111 - assign $0\alu_op__rc__ok$next[0:0]$9086 $2\alu_op__rc__ok$next[0:0]$9112 - assign $0\alu_op__rc__rc$next[0:0]$9087 $2\alu_op__rc__rc$next[0:0]$9113 - attribute \src "libresoc.v:165684.5-165684.29" + assign $0\alu_op__write_cr0$next[0:0]$9020 $1\alu_op__write_cr0$next[0:0]$9038 + assign $0\alu_op__zero_a$next[0:0]$9021 $1\alu_op__zero_a$next[0:0]$9039 + assign $0\alu_op__imm_data__data$next[63:0]$9006 $2\alu_op__imm_data__data$next[63:0]$9040 + assign $0\alu_op__imm_data__ok$next[0:0]$9007 $2\alu_op__imm_data__ok$next[0:0]$9041 + assign $0\alu_op__oe__oe$next[0:0]$9015 $2\alu_op__oe__oe$next[0:0]$9042 + assign $0\alu_op__oe__ok$next[0:0]$9016 $2\alu_op__oe__ok$next[0:0]$9043 + assign $0\alu_op__rc__ok$next[0:0]$9018 $2\alu_op__rc__ok$next[0:0]$9044 + assign $0\alu_op__rc__rc$next[0:0]$9019 $2\alu_op__rc__rc$next[0:0]$9045 + attribute \src "libresoc.v:166452.5-166452.29" switch \initial - attribute \src "libresoc.v:165684.9-165684.17" + attribute \src "libresoc.v:166452.9-166452.17" case 1'1 case end @@ -342399,7 +308942,7 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$next[31:0]$9095 $1\alu_op__data_len$next[3:0]$9090 $1\alu_op__is_signed$next[0:0]$9100 $1\alu_op__is_32bit$next[0:0]$9099 $1\alu_op__output_carry$next[0:0]$9103 $1\alu_op__input_carry$next[1:0]$9094 $1\alu_op__write_cr0$next[0:0]$9106 $1\alu_op__invert_out$next[0:0]$9098 $1\alu_op__zero_a$next[0:0]$9107 $1\alu_op__invert_in$next[0:0]$9097 $1\alu_op__oe__ok$next[0:0]$9102 $1\alu_op__oe__oe$next[0:0]$9101 $1\alu_op__rc__ok$next[0:0]$9104 $1\alu_op__rc__rc$next[0:0]$9105 $1\alu_op__imm_data__ok$next[0:0]$9093 $1\alu_op__imm_data__data$next[63:0]$9092 $1\alu_op__fn_unit$next[13:0]$9091 $1\alu_op__insn_type$next[6:0]$9096 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { $1\alu_op__insn$next[31:0]$9027 $1\alu_op__data_len$next[3:0]$9022 $1\alu_op__is_signed$next[0:0]$9032 $1\alu_op__is_32bit$next[0:0]$9031 $1\alu_op__output_carry$next[0:0]$9035 $1\alu_op__input_carry$next[1:0]$9026 $1\alu_op__write_cr0$next[0:0]$9038 $1\alu_op__invert_out$next[0:0]$9030 $1\alu_op__zero_a$next[0:0]$9039 $1\alu_op__invert_in$next[0:0]$9029 $1\alu_op__oe__ok$next[0:0]$9034 $1\alu_op__oe__oe$next[0:0]$9033 $1\alu_op__rc__ok$next[0:0]$9036 $1\alu_op__rc__rc$next[0:0]$9037 $1\alu_op__imm_data__ok$next[0:0]$9025 $1\alu_op__imm_data__data$next[63:0]$9024 $1\alu_op__fn_unit$next[13:0]$9023 $1\alu_op__insn_type$next[6:0]$9028 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -342420,26 +308963,26 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$next[31:0]$9095 $1\alu_op__data_len$next[3:0]$9090 $1\alu_op__is_signed$next[0:0]$9100 $1\alu_op__is_32bit$next[0:0]$9099 $1\alu_op__output_carry$next[0:0]$9103 $1\alu_op__input_carry$next[1:0]$9094 $1\alu_op__write_cr0$next[0:0]$9106 $1\alu_op__invert_out$next[0:0]$9098 $1\alu_op__zero_a$next[0:0]$9107 $1\alu_op__invert_in$next[0:0]$9097 $1\alu_op__oe__ok$next[0:0]$9102 $1\alu_op__oe__oe$next[0:0]$9101 $1\alu_op__rc__ok$next[0:0]$9104 $1\alu_op__rc__rc$next[0:0]$9105 $1\alu_op__imm_data__ok$next[0:0]$9093 $1\alu_op__imm_data__data$next[63:0]$9092 $1\alu_op__fn_unit$next[13:0]$9091 $1\alu_op__insn_type$next[6:0]$9096 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { $1\alu_op__insn$next[31:0]$9027 $1\alu_op__data_len$next[3:0]$9022 $1\alu_op__is_signed$next[0:0]$9032 $1\alu_op__is_32bit$next[0:0]$9031 $1\alu_op__output_carry$next[0:0]$9035 $1\alu_op__input_carry$next[1:0]$9026 $1\alu_op__write_cr0$next[0:0]$9038 $1\alu_op__invert_out$next[0:0]$9030 $1\alu_op__zero_a$next[0:0]$9039 $1\alu_op__invert_in$next[0:0]$9029 $1\alu_op__oe__ok$next[0:0]$9034 $1\alu_op__oe__oe$next[0:0]$9033 $1\alu_op__rc__ok$next[0:0]$9036 $1\alu_op__rc__rc$next[0:0]$9037 $1\alu_op__imm_data__ok$next[0:0]$9025 $1\alu_op__imm_data__data$next[63:0]$9024 $1\alu_op__fn_unit$next[13:0]$9023 $1\alu_op__insn_type$next[6:0]$9028 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } case - assign $1\alu_op__data_len$next[3:0]$9090 \alu_op__data_len - assign $1\alu_op__fn_unit$next[13:0]$9091 \alu_op__fn_unit - assign $1\alu_op__imm_data__data$next[63:0]$9092 \alu_op__imm_data__data - assign $1\alu_op__imm_data__ok$next[0:0]$9093 \alu_op__imm_data__ok - assign $1\alu_op__input_carry$next[1:0]$9094 \alu_op__input_carry - assign $1\alu_op__insn$next[31:0]$9095 \alu_op__insn - assign $1\alu_op__insn_type$next[6:0]$9096 \alu_op__insn_type - assign $1\alu_op__invert_in$next[0:0]$9097 \alu_op__invert_in - assign $1\alu_op__invert_out$next[0:0]$9098 \alu_op__invert_out - assign $1\alu_op__is_32bit$next[0:0]$9099 \alu_op__is_32bit - assign $1\alu_op__is_signed$next[0:0]$9100 \alu_op__is_signed - assign $1\alu_op__oe__oe$next[0:0]$9101 \alu_op__oe__oe - assign $1\alu_op__oe__ok$next[0:0]$9102 \alu_op__oe__ok - assign $1\alu_op__output_carry$next[0:0]$9103 \alu_op__output_carry - assign $1\alu_op__rc__ok$next[0:0]$9104 \alu_op__rc__ok - assign $1\alu_op__rc__rc$next[0:0]$9105 \alu_op__rc__rc - assign $1\alu_op__write_cr0$next[0:0]$9106 \alu_op__write_cr0 - assign $1\alu_op__zero_a$next[0:0]$9107 \alu_op__zero_a + assign $1\alu_op__data_len$next[3:0]$9022 \alu_op__data_len + assign $1\alu_op__fn_unit$next[13:0]$9023 \alu_op__fn_unit + assign $1\alu_op__imm_data__data$next[63:0]$9024 \alu_op__imm_data__data + assign $1\alu_op__imm_data__ok$next[0:0]$9025 \alu_op__imm_data__ok + assign $1\alu_op__input_carry$next[1:0]$9026 \alu_op__input_carry + assign $1\alu_op__insn$next[31:0]$9027 \alu_op__insn + assign $1\alu_op__insn_type$next[6:0]$9028 \alu_op__insn_type + assign $1\alu_op__invert_in$next[0:0]$9029 \alu_op__invert_in + assign $1\alu_op__invert_out$next[0:0]$9030 \alu_op__invert_out + assign $1\alu_op__is_32bit$next[0:0]$9031 \alu_op__is_32bit + assign $1\alu_op__is_signed$next[0:0]$9032 \alu_op__is_signed + assign $1\alu_op__oe__oe$next[0:0]$9033 \alu_op__oe__oe + assign $1\alu_op__oe__ok$next[0:0]$9034 \alu_op__oe__ok + assign $1\alu_op__output_carry$next[0:0]$9035 \alu_op__output_carry + assign $1\alu_op__rc__ok$next[0:0]$9036 \alu_op__rc__ok + assign $1\alu_op__rc__rc$next[0:0]$9037 \alu_op__rc__rc + assign $1\alu_op__write_cr0$next[0:0]$9038 \alu_op__write_cr0 + assign $1\alu_op__zero_a$next[0:0]$9039 \alu_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -342451,52 +308994,52 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign $2\alu_op__imm_data__data$next[63:0]$9108 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$next[0:0]$9109 1'0 - assign $2\alu_op__rc__rc$next[0:0]$9113 1'0 - assign $2\alu_op__rc__ok$next[0:0]$9112 1'0 - assign $2\alu_op__oe__oe$next[0:0]$9110 1'0 - assign $2\alu_op__oe__ok$next[0:0]$9111 1'0 + assign $2\alu_op__imm_data__data$next[63:0]$9040 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$next[0:0]$9041 1'0 + assign $2\alu_op__rc__rc$next[0:0]$9045 1'0 + assign $2\alu_op__rc__ok$next[0:0]$9044 1'0 + assign $2\alu_op__oe__oe$next[0:0]$9042 1'0 + assign $2\alu_op__oe__ok$next[0:0]$9043 1'0 case - assign $2\alu_op__imm_data__data$next[63:0]$9108 $1\alu_op__imm_data__data$next[63:0]$9092 - assign $2\alu_op__imm_data__ok$next[0:0]$9109 $1\alu_op__imm_data__ok$next[0:0]$9093 - assign $2\alu_op__oe__oe$next[0:0]$9110 $1\alu_op__oe__oe$next[0:0]$9101 - assign $2\alu_op__oe__ok$next[0:0]$9111 $1\alu_op__oe__ok$next[0:0]$9102 - assign $2\alu_op__rc__ok$next[0:0]$9112 $1\alu_op__rc__ok$next[0:0]$9104 - assign $2\alu_op__rc__rc$next[0:0]$9113 $1\alu_op__rc__rc$next[0:0]$9105 + assign $2\alu_op__imm_data__data$next[63:0]$9040 $1\alu_op__imm_data__data$next[63:0]$9024 + assign $2\alu_op__imm_data__ok$next[0:0]$9041 $1\alu_op__imm_data__ok$next[0:0]$9025 + assign $2\alu_op__oe__oe$next[0:0]$9042 $1\alu_op__oe__oe$next[0:0]$9033 + assign $2\alu_op__oe__ok$next[0:0]$9043 $1\alu_op__oe__ok$next[0:0]$9034 + assign $2\alu_op__rc__ok$next[0:0]$9044 $1\alu_op__rc__ok$next[0:0]$9036 + assign $2\alu_op__rc__rc$next[0:0]$9045 $1\alu_op__rc__rc$next[0:0]$9037 end sync always - update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9072 - update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[13:0]$9073 - update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9074 - update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9075 - update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9076 - update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9077 - update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9078 - update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9079 - update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9080 - update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9081 - update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9082 - update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9083 - update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9084 - update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9085 - update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9086 - update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9087 - update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9088 - update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9089 + update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9004 + update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[13:0]$9005 + update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9006 + update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9007 + update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9008 + update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9009 + update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9010 + update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9011 + update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9012 + update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9013 + update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9014 + update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9015 + update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9016 + update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9017 + update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9018 + update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9019 + update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9020 + update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9021 end - attribute \src "libresoc.v:165725.3-165743.6" - process $proc$libresoc.v:165725$9114 + attribute \src "libresoc.v:166493.3-166511.6" + process $proc$libresoc.v:166493$9046 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9115 $1\o$next[63:0]$9117 + assign $0\o$next[63:0]$9047 $1\o$next[63:0]$9049 assign { } { } - assign $0\o_ok$next[0:0]$9116 $2\o_ok$next[0:0]$9119 - attribute \src "libresoc.v:165726.5-165726.29" + assign $0\o_ok$next[0:0]$9048 $2\o_ok$next[0:0]$9051 + attribute \src "libresoc.v:166494.5-166494.29" switch \initial - attribute \src "libresoc.v:165726.9-165726.17" + attribute \src "libresoc.v:166494.9-166494.17" case 1'1 case end @@ -342506,30 +309049,30 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9118 $1\o$next[63:0]$9117 } { \o_ok$89 \o$88 } + assign { $1\o_ok$next[0:0]$9050 $1\o$next[63:0]$9049 } { \o_ok$89 \o$88 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9118 $1\o$next[63:0]$9117 } { \o_ok$89 \o$88 } + assign { $1\o_ok$next[0:0]$9050 $1\o$next[63:0]$9049 } { \o_ok$89 \o$88 } case - assign $1\o$next[63:0]$9117 \o - assign $1\o_ok$next[0:0]$9118 \o_ok + assign $1\o$next[63:0]$9049 \o + assign $1\o_ok$next[0:0]$9050 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9119 1'0 + assign $2\o_ok$next[0:0]$9051 1'0 case - assign $2\o_ok$next[0:0]$9119 $1\o_ok$next[0:0]$9118 + assign $2\o_ok$next[0:0]$9051 $1\o_ok$next[0:0]$9050 end sync always - update \o$next $0\o$next[63:0]$9115 - update \o_ok$next $0\o_ok$next[0:0]$9116 + update \o$next $0\o$next[63:0]$9047 + update \o_ok$next $0\o_ok$next[0:0]$9048 end - connect \$67 $and$libresoc.v:165406$9009_Y + connect \$67 $and$libresoc.v:166174$8941_Y connect \xer_so_ok$98 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy @@ -342556,276 +309099,276 @@ module \pipe1 connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:165773.1-167209.10" +attribute \src "libresoc.v:166541.1-167977.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" attribute \generator "nMigen" module \pipe1$110 - attribute \src "libresoc.v:167142.3-167160.6" - wire width 4 $0\cr_a$next[3:0]$9240 - attribute \src "libresoc.v:166884.3-166885.25" + attribute \src "libresoc.v:167910.3-167928.6" + wire width 4 $0\cr_a$next[3:0]$9172 + attribute \src "libresoc.v:167652.3-167653.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:167142.3-167160.6" - wire $0\cr_a_ok$next[0:0]$9241 - attribute \src "libresoc.v:166886.3-166887.31" + attribute \src "libresoc.v:167910.3-167928.6" + wire $0\cr_a_ok$next[0:0]$9173 + attribute \src "libresoc.v:167654.3-167655.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:165774.7-165774.20" + attribute \src "libresoc.v:166542.7-166542.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167069.3-167081.6" - wire width 2 $0\muxid$next[1:0]$9190 - attribute \src "libresoc.v:166926.3-166927.27" + attribute \src "libresoc.v:167837.3-167849.6" + wire width 2 $0\muxid$next[1:0]$9122 + attribute \src "libresoc.v:167694.3-167695.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:167123.3-167141.6" - wire width 64 $0\o$next[63:0]$9234 - attribute \src "libresoc.v:166888.3-166889.19" + attribute \src "libresoc.v:167891.3-167909.6" + wire width 64 $0\o$next[63:0]$9166 + attribute \src "libresoc.v:167656.3-167657.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:167123.3-167141.6" - wire $0\o_ok$next[0:0]$9235 - attribute \src "libresoc.v:166890.3-166891.25" + attribute \src "libresoc.v:167891.3-167909.6" + wire $0\o_ok$next[0:0]$9167 + attribute \src "libresoc.v:167658.3-167659.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:167051.3-167068.6" - wire $0\r_busy$next[0:0]$9186 - attribute \src "libresoc.v:166928.3-166929.29" + attribute \src "libresoc.v:167819.3-167836.6" + wire $0\r_busy$next[0:0]$9118 + attribute \src "libresoc.v:167696.3-167697.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire width 14 $0\sr_op__fn_unit$next[13:0]$9193 - attribute \src "libresoc.v:166894.3-166895.45" + attribute \src "libresoc.v:167850.3-167890.6" + wire width 14 $0\sr_op__fn_unit$next[13:0]$9125 + attribute \src "libresoc.v:167662.3-167663.45" wire width 14 $0\sr_op__fn_unit[13:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire width 64 $0\sr_op__imm_data__data$next[63:0]$9194 - attribute \src "libresoc.v:166896.3-166897.59" + attribute \src "libresoc.v:167850.3-167890.6" + wire width 64 $0\sr_op__imm_data__data$next[63:0]$9126 + attribute \src "libresoc.v:167664.3-167665.59" wire width 64 $0\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $0\sr_op__imm_data__ok$next[0:0]$9195 - attribute \src "libresoc.v:166898.3-166899.55" + attribute \src "libresoc.v:167850.3-167890.6" + wire $0\sr_op__imm_data__ok$next[0:0]$9127 + attribute \src "libresoc.v:167666.3-167667.55" wire $0\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire width 2 $0\sr_op__input_carry$next[1:0]$9196 - attribute \src "libresoc.v:166912.3-166913.53" + attribute \src "libresoc.v:167850.3-167890.6" + wire width 2 $0\sr_op__input_carry$next[1:0]$9128 + attribute \src "libresoc.v:167680.3-167681.53" wire width 2 $0\sr_op__input_carry[1:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $0\sr_op__input_cr$next[0:0]$9197 - attribute \src "libresoc.v:166916.3-166917.47" + attribute \src "libresoc.v:167850.3-167890.6" + wire $0\sr_op__input_cr$next[0:0]$9129 + attribute \src "libresoc.v:167684.3-167685.47" wire $0\sr_op__input_cr[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire width 32 $0\sr_op__insn$next[31:0]$9198 - attribute \src "libresoc.v:166924.3-166925.39" + attribute \src "libresoc.v:167850.3-167890.6" + wire width 32 $0\sr_op__insn$next[31:0]$9130 + attribute \src "libresoc.v:167692.3-167693.39" wire width 32 $0\sr_op__insn[31:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire width 7 $0\sr_op__insn_type$next[6:0]$9199 - attribute \src "libresoc.v:166892.3-166893.49" + attribute \src "libresoc.v:167850.3-167890.6" + wire width 7 $0\sr_op__insn_type$next[6:0]$9131 + attribute \src "libresoc.v:167660.3-167661.49" wire width 7 $0\sr_op__insn_type[6:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $0\sr_op__invert_in$next[0:0]$9200 - attribute \src "libresoc.v:166910.3-166911.49" + attribute \src "libresoc.v:167850.3-167890.6" + wire $0\sr_op__invert_in$next[0:0]$9132 + attribute \src "libresoc.v:167678.3-167679.49" wire $0\sr_op__invert_in[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $0\sr_op__is_32bit$next[0:0]$9201 - attribute \src "libresoc.v:166920.3-166921.47" + attribute \src "libresoc.v:167850.3-167890.6" + wire $0\sr_op__is_32bit$next[0:0]$9133 + attribute \src "libresoc.v:167688.3-167689.47" wire $0\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $0\sr_op__is_signed$next[0:0]$9202 - attribute \src "libresoc.v:166922.3-166923.49" + attribute \src "libresoc.v:167850.3-167890.6" + wire $0\sr_op__is_signed$next[0:0]$9134 + attribute \src "libresoc.v:167690.3-167691.49" wire $0\sr_op__is_signed[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $0\sr_op__oe__oe$next[0:0]$9203 - attribute \src "libresoc.v:166904.3-166905.43" + attribute \src "libresoc.v:167850.3-167890.6" + wire $0\sr_op__oe__oe$next[0:0]$9135 + attribute \src "libresoc.v:167672.3-167673.43" wire $0\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $0\sr_op__oe__ok$next[0:0]$9204 - attribute \src "libresoc.v:166906.3-166907.43" + attribute \src "libresoc.v:167850.3-167890.6" + wire $0\sr_op__oe__ok$next[0:0]$9136 + attribute \src "libresoc.v:167674.3-167675.43" wire $0\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $0\sr_op__output_carry$next[0:0]$9205 - attribute \src "libresoc.v:166914.3-166915.55" + attribute \src "libresoc.v:167850.3-167890.6" + wire $0\sr_op__output_carry$next[0:0]$9137 + attribute \src "libresoc.v:167682.3-167683.55" wire $0\sr_op__output_carry[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $0\sr_op__output_cr$next[0:0]$9206 - attribute \src "libresoc.v:166918.3-166919.49" + attribute \src "libresoc.v:167850.3-167890.6" + wire $0\sr_op__output_cr$next[0:0]$9138 + attribute \src "libresoc.v:167686.3-167687.49" wire $0\sr_op__output_cr[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $0\sr_op__rc__ok$next[0:0]$9207 - attribute \src "libresoc.v:166902.3-166903.43" + attribute \src "libresoc.v:167850.3-167890.6" + wire $0\sr_op__rc__ok$next[0:0]$9139 + attribute \src "libresoc.v:167670.3-167671.43" wire $0\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $0\sr_op__rc__rc$next[0:0]$9208 - attribute \src "libresoc.v:166900.3-166901.43" + attribute \src "libresoc.v:167850.3-167890.6" + wire $0\sr_op__rc__rc$next[0:0]$9140 + attribute \src "libresoc.v:167668.3-167669.43" wire $0\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $0\sr_op__write_cr0$next[0:0]$9209 - attribute \src "libresoc.v:166908.3-166909.49" + attribute \src "libresoc.v:167850.3-167890.6" + wire $0\sr_op__write_cr0$next[0:0]$9141 + attribute \src "libresoc.v:167676.3-167677.49" wire $0\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:167032.3-167050.6" - wire width 2 $0\xer_ca$next[1:0]$9181 - attribute \src "libresoc.v:166876.3-166877.29" + attribute \src "libresoc.v:167800.3-167818.6" + wire width 2 $0\xer_ca$next[1:0]$9113 + attribute \src "libresoc.v:167644.3-167645.29" wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:167032.3-167050.6" - wire $0\xer_ca_ok$next[0:0]$9180 - attribute \src "libresoc.v:166878.3-166879.35" + attribute \src "libresoc.v:167800.3-167818.6" + wire $0\xer_ca_ok$next[0:0]$9112 + attribute \src "libresoc.v:167646.3-167647.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:167161.3-167179.6" - wire $0\xer_so$next[0:0]$9246 - attribute \src "libresoc.v:166880.3-166881.29" + attribute \src "libresoc.v:167929.3-167947.6" + wire $0\xer_so$next[0:0]$9178 + attribute \src "libresoc.v:167648.3-167649.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:167161.3-167179.6" - wire $0\xer_so_ok$next[0:0]$9247 - attribute \src "libresoc.v:166882.3-166883.35" + attribute \src "libresoc.v:167929.3-167947.6" + wire $0\xer_so_ok$next[0:0]$9179 + attribute \src "libresoc.v:167650.3-167651.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:167142.3-167160.6" - wire width 4 $1\cr_a$next[3:0]$9242 - attribute \src "libresoc.v:165783.13-165783.24" + attribute \src "libresoc.v:167910.3-167928.6" + wire width 4 $1\cr_a$next[3:0]$9174 + attribute \src "libresoc.v:166551.13-166551.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:167142.3-167160.6" - wire $1\cr_a_ok$next[0:0]$9243 - attribute \src "libresoc.v:165792.7-165792.21" + attribute \src "libresoc.v:167910.3-167928.6" + wire $1\cr_a_ok$next[0:0]$9175 + attribute \src "libresoc.v:166560.7-166560.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:167069.3-167081.6" - wire width 2 $1\muxid$next[1:0]$9191 - attribute \src "libresoc.v:166357.13-166357.25" + attribute \src "libresoc.v:167837.3-167849.6" + wire width 2 $1\muxid$next[1:0]$9123 + attribute \src "libresoc.v:167125.13-167125.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:167123.3-167141.6" - wire width 64 $1\o$next[63:0]$9236 - attribute \src "libresoc.v:166372.14-166372.38" + attribute \src "libresoc.v:167891.3-167909.6" + wire width 64 $1\o$next[63:0]$9168 + attribute \src "libresoc.v:167140.14-167140.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:167123.3-167141.6" - wire $1\o_ok$next[0:0]$9237 - attribute \src "libresoc.v:166379.7-166379.18" + attribute \src "libresoc.v:167891.3-167909.6" + wire $1\o_ok$next[0:0]$9169 + attribute \src "libresoc.v:167147.7-167147.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:167051.3-167068.6" - wire $1\r_busy$next[0:0]$9187 - attribute \src "libresoc.v:166393.7-166393.20" + attribute \src "libresoc.v:167819.3-167836.6" + wire $1\r_busy$next[0:0]$9119 + attribute \src "libresoc.v:167161.7-167161.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire width 14 $1\sr_op__fn_unit$next[13:0]$9210 - attribute \src "libresoc.v:166419.14-166419.39" + attribute \src "libresoc.v:167850.3-167890.6" + wire width 14 $1\sr_op__fn_unit$next[13:0]$9142 + attribute \src "libresoc.v:167187.14-167187.39" wire width 14 $1\sr_op__fn_unit[13:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire width 64 $1\sr_op__imm_data__data$next[63:0]$9211 - attribute \src "libresoc.v:166458.14-166458.58" + attribute \src "libresoc.v:167850.3-167890.6" + wire width 64 $1\sr_op__imm_data__data$next[63:0]$9143 + attribute \src "libresoc.v:167226.14-167226.58" wire width 64 $1\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $1\sr_op__imm_data__ok$next[0:0]$9212 - attribute \src "libresoc.v:166467.7-166467.33" + attribute \src "libresoc.v:167850.3-167890.6" + wire $1\sr_op__imm_data__ok$next[0:0]$9144 + attribute \src "libresoc.v:167235.7-167235.33" wire $1\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire width 2 $1\sr_op__input_carry$next[1:0]$9213 - attribute \src "libresoc.v:166480.13-166480.38" + attribute \src "libresoc.v:167850.3-167890.6" + wire width 2 $1\sr_op__input_carry$next[1:0]$9145 + attribute \src "libresoc.v:167248.13-167248.38" wire width 2 $1\sr_op__input_carry[1:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $1\sr_op__input_cr$next[0:0]$9214 - attribute \src "libresoc.v:166497.7-166497.29" + attribute \src "libresoc.v:167850.3-167890.6" + wire $1\sr_op__input_cr$next[0:0]$9146 + attribute \src "libresoc.v:167265.7-167265.29" wire $1\sr_op__input_cr[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire width 32 $1\sr_op__insn$next[31:0]$9215 - attribute \src "libresoc.v:166506.14-166506.33" + attribute \src "libresoc.v:167850.3-167890.6" + wire width 32 $1\sr_op__insn$next[31:0]$9147 + attribute \src "libresoc.v:167274.14-167274.33" wire width 32 $1\sr_op__insn[31:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire width 7 $1\sr_op__insn_type$next[6:0]$9216 - attribute \src "libresoc.v:166590.13-166590.37" + attribute \src "libresoc.v:167850.3-167890.6" + wire width 7 $1\sr_op__insn_type$next[6:0]$9148 + attribute \src "libresoc.v:167358.13-167358.37" wire width 7 $1\sr_op__insn_type[6:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $1\sr_op__invert_in$next[0:0]$9217 - attribute \src "libresoc.v:166749.7-166749.30" + attribute \src "libresoc.v:167850.3-167890.6" + wire $1\sr_op__invert_in$next[0:0]$9149 + attribute \src "libresoc.v:167517.7-167517.30" wire $1\sr_op__invert_in[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $1\sr_op__is_32bit$next[0:0]$9218 - attribute \src "libresoc.v:166758.7-166758.29" + attribute \src "libresoc.v:167850.3-167890.6" + wire $1\sr_op__is_32bit$next[0:0]$9150 + attribute \src "libresoc.v:167526.7-167526.29" wire $1\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $1\sr_op__is_signed$next[0:0]$9219 - attribute \src "libresoc.v:166767.7-166767.30" + attribute \src "libresoc.v:167850.3-167890.6" + wire $1\sr_op__is_signed$next[0:0]$9151 + attribute \src "libresoc.v:167535.7-167535.30" wire $1\sr_op__is_signed[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $1\sr_op__oe__oe$next[0:0]$9220 - attribute \src "libresoc.v:166776.7-166776.27" + attribute \src "libresoc.v:167850.3-167890.6" + wire $1\sr_op__oe__oe$next[0:0]$9152 + attribute \src "libresoc.v:167544.7-167544.27" wire $1\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $1\sr_op__oe__ok$next[0:0]$9221 - attribute \src "libresoc.v:166785.7-166785.27" + attribute \src "libresoc.v:167850.3-167890.6" + wire $1\sr_op__oe__ok$next[0:0]$9153 + attribute \src "libresoc.v:167553.7-167553.27" wire $1\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $1\sr_op__output_carry$next[0:0]$9222 - attribute \src "libresoc.v:166794.7-166794.33" + attribute \src "libresoc.v:167850.3-167890.6" + wire $1\sr_op__output_carry$next[0:0]$9154 + attribute \src "libresoc.v:167562.7-167562.33" wire $1\sr_op__output_carry[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $1\sr_op__output_cr$next[0:0]$9223 - attribute \src "libresoc.v:166803.7-166803.30" + attribute \src "libresoc.v:167850.3-167890.6" + wire $1\sr_op__output_cr$next[0:0]$9155 + attribute \src "libresoc.v:167571.7-167571.30" wire $1\sr_op__output_cr[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $1\sr_op__rc__ok$next[0:0]$9224 - attribute \src "libresoc.v:166812.7-166812.27" + attribute \src "libresoc.v:167850.3-167890.6" + wire $1\sr_op__rc__ok$next[0:0]$9156 + attribute \src "libresoc.v:167580.7-167580.27" wire $1\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $1\sr_op__rc__rc$next[0:0]$9225 - attribute \src "libresoc.v:166821.7-166821.27" + attribute \src "libresoc.v:167850.3-167890.6" + wire $1\sr_op__rc__rc$next[0:0]$9157 + attribute \src "libresoc.v:167589.7-167589.27" wire $1\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:167082.3-167122.6" - wire $1\sr_op__write_cr0$next[0:0]$9226 - attribute \src "libresoc.v:166830.7-166830.30" + attribute \src "libresoc.v:167850.3-167890.6" + wire $1\sr_op__write_cr0$next[0:0]$9158 + attribute \src "libresoc.v:167598.7-167598.30" wire $1\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:167032.3-167050.6" - wire width 2 $1\xer_ca$next[1:0]$9183 - attribute \src "libresoc.v:166839.13-166839.26" + attribute \src "libresoc.v:167800.3-167818.6" + wire width 2 $1\xer_ca$next[1:0]$9115 + attribute \src "libresoc.v:167607.13-167607.26" wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:167032.3-167050.6" - wire $1\xer_ca_ok$next[0:0]$9182 - attribute \src "libresoc.v:166850.7-166850.23" + attribute \src "libresoc.v:167800.3-167818.6" + wire $1\xer_ca_ok$next[0:0]$9114 + attribute \src "libresoc.v:167618.7-167618.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:167161.3-167179.6" - wire $1\xer_so$next[0:0]$9248 - attribute \src "libresoc.v:166859.7-166859.20" + attribute \src "libresoc.v:167929.3-167947.6" + wire $1\xer_so$next[0:0]$9180 + attribute \src "libresoc.v:167627.7-167627.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:167161.3-167179.6" - wire $1\xer_so_ok$next[0:0]$9249 - attribute \src "libresoc.v:166868.7-166868.23" + attribute \src "libresoc.v:167929.3-167947.6" + wire $1\xer_so_ok$next[0:0]$9181 + attribute \src "libresoc.v:167636.7-167636.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:167142.3-167160.6" - wire $2\cr_a_ok$next[0:0]$9244 - attribute \src "libresoc.v:167123.3-167141.6" - wire $2\o_ok$next[0:0]$9238 - attribute \src "libresoc.v:167051.3-167068.6" - wire $2\r_busy$next[0:0]$9188 - attribute \src "libresoc.v:167082.3-167122.6" - wire width 64 $2\sr_op__imm_data__data$next[63:0]$9227 - attribute \src "libresoc.v:167082.3-167122.6" - wire $2\sr_op__imm_data__ok$next[0:0]$9228 - attribute \src "libresoc.v:167082.3-167122.6" - wire $2\sr_op__oe__oe$next[0:0]$9229 - attribute \src "libresoc.v:167082.3-167122.6" - wire $2\sr_op__oe__ok$next[0:0]$9230 - attribute \src "libresoc.v:167082.3-167122.6" - wire $2\sr_op__rc__ok$next[0:0]$9231 - attribute \src "libresoc.v:167082.3-167122.6" - wire $2\sr_op__rc__rc$next[0:0]$9232 - attribute \src "libresoc.v:167032.3-167050.6" - wire $2\xer_ca_ok$next[0:0]$9184 - attribute \src "libresoc.v:167161.3-167179.6" - wire $2\xer_so_ok$next[0:0]$9250 - attribute \src "libresoc.v:166875.18-166875.118" - wire $and$libresoc.v:166875$9151_Y + attribute \src "libresoc.v:167910.3-167928.6" + wire $2\cr_a_ok$next[0:0]$9176 + attribute \src "libresoc.v:167891.3-167909.6" + wire $2\o_ok$next[0:0]$9170 + attribute \src "libresoc.v:167819.3-167836.6" + wire $2\r_busy$next[0:0]$9120 + attribute \src "libresoc.v:167850.3-167890.6" + wire width 64 $2\sr_op__imm_data__data$next[63:0]$9159 + attribute \src "libresoc.v:167850.3-167890.6" + wire $2\sr_op__imm_data__ok$next[0:0]$9160 + attribute \src "libresoc.v:167850.3-167890.6" + wire $2\sr_op__oe__oe$next[0:0]$9161 + attribute \src "libresoc.v:167850.3-167890.6" + wire $2\sr_op__oe__ok$next[0:0]$9162 + attribute \src "libresoc.v:167850.3-167890.6" + wire $2\sr_op__rc__ok$next[0:0]$9163 + attribute \src "libresoc.v:167850.3-167890.6" + wire $2\sr_op__rc__rc$next[0:0]$9164 + attribute \src "libresoc.v:167800.3-167818.6" + wire $2\xer_ca_ok$next[0:0]$9116 + attribute \src "libresoc.v:167929.3-167947.6" + wire $2\xer_so_ok$next[0:0]$9182 + attribute \src "libresoc.v:167643.18-167643.118" + wire $and$libresoc.v:167643$9083_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 55 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 24 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next - attribute \src "libresoc.v:165774.7-165774.15" + attribute \src "libresoc.v:166542.7-166542.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid @@ -343111,9 +309654,9 @@ module \pipe1$110 wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_ra @@ -343377,11 +309920,11 @@ module \pipe1$110 wire \main_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__write_cr0$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \main_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_xer_so$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid @@ -343397,17 +309940,17 @@ module \pipe1$110 wire input 3 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 22 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 31 \p_ready_o @@ -343845,42 +310388,42 @@ module \pipe1$110 wire \sr_op__write_cr0$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 28 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 54 \xer_ca$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \xer_ca$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 26 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 53 \xer_so$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:166875$9151 + cell $and $and$libresoc.v:167643$9083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -343888,10 +310431,10 @@ module \pipe1$110 parameter \Y_WIDTH 1 connect \A \p_valid_i$64 connect \B \p_ready_o - connect \Y $and$libresoc.v:166875$9151_Y + connect \Y $and$libresoc.v:167643$9083_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:166930.15-166977.4" + attribute \src "libresoc.v:167698.15-167745.4" cell \input$113 \input connect \muxid \input_muxid connect \muxid$1 \input_muxid$21 @@ -343941,7 +310484,7 @@ module \pipe1$110 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:166978.14-167023.4" + attribute \src "libresoc.v:167746.14-167791.4" cell \main$114 \main connect \muxid \main_muxid connect \muxid$1 \main_muxid$44 @@ -343989,442 +310532,442 @@ module \pipe1$110 connect \xer_so$19 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:167024.11-167027.4" + attribute \src "libresoc.v:167792.11-167795.4" cell \n$112 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:167028.11-167031.4" + attribute \src "libresoc.v:167796.11-167799.4" cell \p$111 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:165774.7-165774.20" - process $proc$libresoc.v:165774$9251 + attribute \src "libresoc.v:166542.7-166542.20" + process $proc$libresoc.v:166542$9183 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:165783.13-165783.24" - process $proc$libresoc.v:165783$9252 + attribute \src "libresoc.v:166551.13-166551.24" + process $proc$libresoc.v:166551$9184 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:165792.7-165792.21" - process $proc$libresoc.v:165792$9253 + attribute \src "libresoc.v:166560.7-166560.21" + process $proc$libresoc.v:166560$9185 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:166357.13-166357.25" - process $proc$libresoc.v:166357$9254 + attribute \src "libresoc.v:167125.13-167125.25" + process $proc$libresoc.v:167125$9186 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:166372.14-166372.38" - process $proc$libresoc.v:166372$9255 + attribute \src "libresoc.v:167140.14-167140.38" + process $proc$libresoc.v:167140$9187 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:166379.7-166379.18" - process $proc$libresoc.v:166379$9256 + attribute \src "libresoc.v:167147.7-167147.18" + process $proc$libresoc.v:167147$9188 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:166393.7-166393.20" - process $proc$libresoc.v:166393$9257 + attribute \src "libresoc.v:167161.7-167161.20" + process $proc$libresoc.v:167161$9189 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:166419.14-166419.39" - process $proc$libresoc.v:166419$9258 + attribute \src "libresoc.v:167187.14-167187.39" + process $proc$libresoc.v:167187$9190 assign { } { } assign $1\sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \sr_op__fn_unit $1\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:166458.14-166458.58" - process $proc$libresoc.v:166458$9259 + attribute \src "libresoc.v:167226.14-167226.58" + process $proc$libresoc.v:167226$9191 assign { } { } assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:166467.7-166467.33" - process $proc$libresoc.v:166467$9260 + attribute \src "libresoc.v:167235.7-167235.33" + process $proc$libresoc.v:167235$9192 assign { } { } assign $1\sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:166480.13-166480.38" - process $proc$libresoc.v:166480$9261 + attribute \src "libresoc.v:167248.13-167248.38" + process $proc$libresoc.v:167248$9193 assign { } { } assign $1\sr_op__input_carry[1:0] 2'00 sync always sync init update \sr_op__input_carry $1\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:166497.7-166497.29" - process $proc$libresoc.v:166497$9262 + attribute \src "libresoc.v:167265.7-167265.29" + process $proc$libresoc.v:167265$9194 assign { } { } assign $1\sr_op__input_cr[0:0] 1'0 sync always sync init update \sr_op__input_cr $1\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:166506.14-166506.33" - process $proc$libresoc.v:166506$9263 + attribute \src "libresoc.v:167274.14-167274.33" + process $proc$libresoc.v:167274$9195 assign { } { } assign $1\sr_op__insn[31:0] 0 sync always sync init update \sr_op__insn $1\sr_op__insn[31:0] end - attribute \src "libresoc.v:166590.13-166590.37" - process $proc$libresoc.v:166590$9264 + attribute \src "libresoc.v:167358.13-167358.37" + process $proc$libresoc.v:167358$9196 assign { } { } assign $1\sr_op__insn_type[6:0] 7'0000000 sync always sync init update \sr_op__insn_type $1\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:166749.7-166749.30" - process $proc$libresoc.v:166749$9265 + attribute \src "libresoc.v:167517.7-167517.30" + process $proc$libresoc.v:167517$9197 assign { } { } assign $1\sr_op__invert_in[0:0] 1'0 sync always sync init update \sr_op__invert_in $1\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:166758.7-166758.29" - process $proc$libresoc.v:166758$9266 + attribute \src "libresoc.v:167526.7-167526.29" + process $proc$libresoc.v:167526$9198 assign { } { } assign $1\sr_op__is_32bit[0:0] 1'0 sync always sync init update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:166767.7-166767.30" - process $proc$libresoc.v:166767$9267 + attribute \src "libresoc.v:167535.7-167535.30" + process $proc$libresoc.v:167535$9199 assign { } { } assign $1\sr_op__is_signed[0:0] 1'0 sync always sync init update \sr_op__is_signed $1\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:166776.7-166776.27" - process $proc$libresoc.v:166776$9268 + attribute \src "libresoc.v:167544.7-167544.27" + process $proc$libresoc.v:167544$9200 assign { } { } assign $1\sr_op__oe__oe[0:0] 1'0 sync always sync init update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:166785.7-166785.27" - process $proc$libresoc.v:166785$9269 + attribute \src "libresoc.v:167553.7-167553.27" + process $proc$libresoc.v:167553$9201 assign { } { } assign $1\sr_op__oe__ok[0:0] 1'0 sync always sync init update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:166794.7-166794.33" - process $proc$libresoc.v:166794$9270 + attribute \src "libresoc.v:167562.7-167562.33" + process $proc$libresoc.v:167562$9202 assign { } { } assign $1\sr_op__output_carry[0:0] 1'0 sync always sync init update \sr_op__output_carry $1\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:166803.7-166803.30" - process $proc$libresoc.v:166803$9271 + attribute \src "libresoc.v:167571.7-167571.30" + process $proc$libresoc.v:167571$9203 assign { } { } assign $1\sr_op__output_cr[0:0] 1'0 sync always sync init update \sr_op__output_cr $1\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:166812.7-166812.27" - process $proc$libresoc.v:166812$9272 + attribute \src "libresoc.v:167580.7-167580.27" + process $proc$libresoc.v:167580$9204 assign { } { } assign $1\sr_op__rc__ok[0:0] 1'0 sync always sync init update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:166821.7-166821.27" - process $proc$libresoc.v:166821$9273 + attribute \src "libresoc.v:167589.7-167589.27" + process $proc$libresoc.v:167589$9205 assign { } { } assign $1\sr_op__rc__rc[0:0] 1'0 sync always sync init update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:166830.7-166830.30" - process $proc$libresoc.v:166830$9274 + attribute \src "libresoc.v:167598.7-167598.30" + process $proc$libresoc.v:167598$9206 assign { } { } assign $1\sr_op__write_cr0[0:0] 1'0 sync always sync init update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:166839.13-166839.26" - process $proc$libresoc.v:166839$9275 + attribute \src "libresoc.v:167607.13-167607.26" + process $proc$libresoc.v:167607$9207 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:166850.7-166850.23" - process $proc$libresoc.v:166850$9276 + attribute \src "libresoc.v:167618.7-167618.23" + process $proc$libresoc.v:167618$9208 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:166859.7-166859.20" - process $proc$libresoc.v:166859$9277 + attribute \src "libresoc.v:167627.7-167627.20" + process $proc$libresoc.v:167627$9209 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:166868.7-166868.23" - process $proc$libresoc.v:166868$9278 + attribute \src "libresoc.v:167636.7-167636.23" + process $proc$libresoc.v:167636$9210 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:166876.3-166877.29" - process $proc$libresoc.v:166876$9152 + attribute \src "libresoc.v:167644.3-167645.29" + process $proc$libresoc.v:167644$9084 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:166878.3-166879.35" - process $proc$libresoc.v:166878$9153 + attribute \src "libresoc.v:167646.3-167647.35" + process $proc$libresoc.v:167646$9085 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:166880.3-166881.29" - process $proc$libresoc.v:166880$9154 + attribute \src "libresoc.v:167648.3-167649.29" + process $proc$libresoc.v:167648$9086 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:166882.3-166883.35" - process $proc$libresoc.v:166882$9155 + attribute \src "libresoc.v:167650.3-167651.35" + process $proc$libresoc.v:167650$9087 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:166884.3-166885.25" - process $proc$libresoc.v:166884$9156 + attribute \src "libresoc.v:167652.3-167653.25" + process $proc$libresoc.v:167652$9088 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:166886.3-166887.31" - process $proc$libresoc.v:166886$9157 + attribute \src "libresoc.v:167654.3-167655.31" + process $proc$libresoc.v:167654$9089 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:166888.3-166889.19" - process $proc$libresoc.v:166888$9158 + attribute \src "libresoc.v:167656.3-167657.19" + process $proc$libresoc.v:167656$9090 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:166890.3-166891.25" - process $proc$libresoc.v:166890$9159 + attribute \src "libresoc.v:167658.3-167659.25" + process $proc$libresoc.v:167658$9091 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:166892.3-166893.49" - process $proc$libresoc.v:166892$9160 + attribute \src "libresoc.v:167660.3-167661.49" + process $proc$libresoc.v:167660$9092 assign { } { } assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next sync posedge \coresync_clk update \sr_op__insn_type $0\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:166894.3-166895.45" - process $proc$libresoc.v:166894$9161 + attribute \src "libresoc.v:167662.3-167663.45" + process $proc$libresoc.v:167662$9093 assign { } { } assign $0\sr_op__fn_unit[13:0] \sr_op__fn_unit$next sync posedge \coresync_clk update \sr_op__fn_unit $0\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:166896.3-166897.59" - process $proc$libresoc.v:166896$9162 + attribute \src "libresoc.v:167664.3-167665.59" + process $proc$libresoc.v:167664$9094 assign { } { } assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next sync posedge \coresync_clk update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:166898.3-166899.55" - process $proc$libresoc.v:166898$9163 + attribute \src "libresoc.v:167666.3-167667.55" + process $proc$libresoc.v:167666$9095 assign { } { } assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next sync posedge \coresync_clk update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:166900.3-166901.43" - process $proc$libresoc.v:166900$9164 + attribute \src "libresoc.v:167668.3-167669.43" + process $proc$libresoc.v:167668$9096 assign { } { } assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next sync posedge \coresync_clk update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:166902.3-166903.43" - process $proc$libresoc.v:166902$9165 + attribute \src "libresoc.v:167670.3-167671.43" + process $proc$libresoc.v:167670$9097 assign { } { } assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next sync posedge \coresync_clk update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:166904.3-166905.43" - process $proc$libresoc.v:166904$9166 + attribute \src "libresoc.v:167672.3-167673.43" + process $proc$libresoc.v:167672$9098 assign { } { } assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next sync posedge \coresync_clk update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:166906.3-166907.43" - process $proc$libresoc.v:166906$9167 + attribute \src "libresoc.v:167674.3-167675.43" + process $proc$libresoc.v:167674$9099 assign { } { } assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next sync posedge \coresync_clk update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:166908.3-166909.49" - process $proc$libresoc.v:166908$9168 + attribute \src "libresoc.v:167676.3-167677.49" + process $proc$libresoc.v:167676$9100 assign { } { } assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next sync posedge \coresync_clk update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:166910.3-166911.49" - process $proc$libresoc.v:166910$9169 + attribute \src "libresoc.v:167678.3-167679.49" + process $proc$libresoc.v:167678$9101 assign { } { } assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next sync posedge \coresync_clk update \sr_op__invert_in $0\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:166912.3-166913.53" - process $proc$libresoc.v:166912$9170 + attribute \src "libresoc.v:167680.3-167681.53" + process $proc$libresoc.v:167680$9102 assign { } { } assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next sync posedge \coresync_clk update \sr_op__input_carry $0\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:166914.3-166915.55" - process $proc$libresoc.v:166914$9171 + attribute \src "libresoc.v:167682.3-167683.55" + process $proc$libresoc.v:167682$9103 assign { } { } assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next sync posedge \coresync_clk update \sr_op__output_carry $0\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:166916.3-166917.47" - process $proc$libresoc.v:166916$9172 + attribute \src "libresoc.v:167684.3-167685.47" + process $proc$libresoc.v:167684$9104 assign { } { } assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next sync posedge \coresync_clk update \sr_op__input_cr $0\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:166918.3-166919.49" - process $proc$libresoc.v:166918$9173 + attribute \src "libresoc.v:167686.3-167687.49" + process $proc$libresoc.v:167686$9105 assign { } { } assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next sync posedge \coresync_clk update \sr_op__output_cr $0\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:166920.3-166921.47" - process $proc$libresoc.v:166920$9174 + attribute \src "libresoc.v:167688.3-167689.47" + process $proc$libresoc.v:167688$9106 assign { } { } assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next sync posedge \coresync_clk update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:166922.3-166923.49" - process $proc$libresoc.v:166922$9175 + attribute \src "libresoc.v:167690.3-167691.49" + process $proc$libresoc.v:167690$9107 assign { } { } assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next sync posedge \coresync_clk update \sr_op__is_signed $0\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:166924.3-166925.39" - process $proc$libresoc.v:166924$9176 + attribute \src "libresoc.v:167692.3-167693.39" + process $proc$libresoc.v:167692$9108 assign { } { } assign $0\sr_op__insn[31:0] \sr_op__insn$next sync posedge \coresync_clk update \sr_op__insn $0\sr_op__insn[31:0] end - attribute \src "libresoc.v:166926.3-166927.27" - process $proc$libresoc.v:166926$9177 + attribute \src "libresoc.v:167694.3-167695.27" + process $proc$libresoc.v:167694$9109 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:166928.3-166929.29" - process $proc$libresoc.v:166928$9178 + attribute \src "libresoc.v:167696.3-167697.29" + process $proc$libresoc.v:167696$9110 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:167032.3-167050.6" - process $proc$libresoc.v:167032$9179 + attribute \src "libresoc.v:167800.3-167818.6" + process $proc$libresoc.v:167800$9111 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$next[1:0]$9181 $1\xer_ca$next[1:0]$9183 - assign $0\xer_ca_ok$next[0:0]$9180 $2\xer_ca_ok$next[0:0]$9184 - attribute \src "libresoc.v:167033.5-167033.29" + assign $0\xer_ca$next[1:0]$9113 $1\xer_ca$next[1:0]$9115 + assign $0\xer_ca_ok$next[0:0]$9112 $2\xer_ca_ok$next[0:0]$9116 + attribute \src "libresoc.v:167801.5-167801.29" switch \initial - attribute \src "libresoc.v:167033.9-167033.17" + attribute \src "libresoc.v:167801.9-167801.17" case 1'1 case end @@ -344434,38 +310977,38 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9182 $1\xer_ca$next[1:0]$9183 } { \xer_ca_ok$95 \xer_ca$94 } + assign { $1\xer_ca_ok$next[0:0]$9114 $1\xer_ca$next[1:0]$9115 } { \xer_ca_ok$95 \xer_ca$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9182 $1\xer_ca$next[1:0]$9183 } { \xer_ca_ok$95 \xer_ca$94 } + assign { $1\xer_ca_ok$next[0:0]$9114 $1\xer_ca$next[1:0]$9115 } { \xer_ca_ok$95 \xer_ca$94 } case - assign $1\xer_ca_ok$next[0:0]$9182 \xer_ca_ok - assign $1\xer_ca$next[1:0]$9183 \xer_ca + assign $1\xer_ca_ok$next[0:0]$9114 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9115 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$9184 1'0 + assign $2\xer_ca_ok$next[0:0]$9116 1'0 case - assign $2\xer_ca_ok$next[0:0]$9184 $1\xer_ca_ok$next[0:0]$9182 + assign $2\xer_ca_ok$next[0:0]$9116 $1\xer_ca_ok$next[0:0]$9114 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9180 - update \xer_ca$next $0\xer_ca$next[1:0]$9181 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9112 + update \xer_ca$next $0\xer_ca$next[1:0]$9113 end - attribute \src "libresoc.v:167051.3-167068.6" - process $proc$libresoc.v:167051$9185 + attribute \src "libresoc.v:167819.3-167836.6" + process $proc$libresoc.v:167819$9117 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9186 $2\r_busy$next[0:0]$9188 - attribute \src "libresoc.v:167052.5-167052.29" + assign $0\r_busy$next[0:0]$9118 $2\r_busy$next[0:0]$9120 + attribute \src "libresoc.v:167820.5-167820.29" switch \initial - attribute \src "libresoc.v:167052.9-167052.17" + attribute \src "libresoc.v:167820.9-167820.17" case 1'1 case end @@ -344474,34 +311017,34 @@ module \pipe1$110 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9187 1'1 + assign $1\r_busy$next[0:0]$9119 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9187 1'0 + assign $1\r_busy$next[0:0]$9119 1'0 case - assign $1\r_busy$next[0:0]$9187 \r_busy + assign $1\r_busy$next[0:0]$9119 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9188 1'0 + assign $2\r_busy$next[0:0]$9120 1'0 case - assign $2\r_busy$next[0:0]$9188 $1\r_busy$next[0:0]$9187 + assign $2\r_busy$next[0:0]$9120 $1\r_busy$next[0:0]$9119 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9186 + update \r_busy$next $0\r_busy$next[0:0]$9118 end - attribute \src "libresoc.v:167069.3-167081.6" - process $proc$libresoc.v:167069$9189 + attribute \src "libresoc.v:167837.3-167849.6" + process $proc$libresoc.v:167837$9121 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9190 $1\muxid$next[1:0]$9191 - attribute \src "libresoc.v:167070.5-167070.29" + assign $0\muxid$next[1:0]$9122 $1\muxid$next[1:0]$9123 + attribute \src "libresoc.v:167838.5-167838.29" switch \initial - attribute \src "libresoc.v:167070.9-167070.17" + attribute \src "libresoc.v:167838.9-167838.17" case 1'1 case end @@ -344510,19 +311053,19 @@ module \pipe1$110 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9191 \muxid$67 + assign $1\muxid$next[1:0]$9123 \muxid$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9191 \muxid$67 + assign $1\muxid$next[1:0]$9123 \muxid$67 case - assign $1\muxid$next[1:0]$9191 \muxid + assign $1\muxid$next[1:0]$9123 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9190 + update \muxid$next $0\muxid$next[1:0]$9122 end - attribute \src "libresoc.v:167082.3-167122.6" - process $proc$libresoc.v:167082$9192 + attribute \src "libresoc.v:167850.3-167890.6" + process $proc$libresoc.v:167850$9124 assign { } { } assign { } { } assign { } { } @@ -344557,32 +311100,32 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign $0\sr_op__fn_unit$next[13:0]$9193 $1\sr_op__fn_unit$next[13:0]$9210 + assign $0\sr_op__fn_unit$next[13:0]$9125 $1\sr_op__fn_unit$next[13:0]$9142 assign { } { } assign { } { } - assign $0\sr_op__input_carry$next[1:0]$9196 $1\sr_op__input_carry$next[1:0]$9213 - assign $0\sr_op__input_cr$next[0:0]$9197 $1\sr_op__input_cr$next[0:0]$9214 - assign $0\sr_op__insn$next[31:0]$9198 $1\sr_op__insn$next[31:0]$9215 - assign $0\sr_op__insn_type$next[6:0]$9199 $1\sr_op__insn_type$next[6:0]$9216 - assign $0\sr_op__invert_in$next[0:0]$9200 $1\sr_op__invert_in$next[0:0]$9217 - assign $0\sr_op__is_32bit$next[0:0]$9201 $1\sr_op__is_32bit$next[0:0]$9218 - assign $0\sr_op__is_signed$next[0:0]$9202 $1\sr_op__is_signed$next[0:0]$9219 + assign $0\sr_op__input_carry$next[1:0]$9128 $1\sr_op__input_carry$next[1:0]$9145 + assign $0\sr_op__input_cr$next[0:0]$9129 $1\sr_op__input_cr$next[0:0]$9146 + assign $0\sr_op__insn$next[31:0]$9130 $1\sr_op__insn$next[31:0]$9147 + assign $0\sr_op__insn_type$next[6:0]$9131 $1\sr_op__insn_type$next[6:0]$9148 + assign $0\sr_op__invert_in$next[0:0]$9132 $1\sr_op__invert_in$next[0:0]$9149 + assign $0\sr_op__is_32bit$next[0:0]$9133 $1\sr_op__is_32bit$next[0:0]$9150 + assign $0\sr_op__is_signed$next[0:0]$9134 $1\sr_op__is_signed$next[0:0]$9151 assign { } { } assign { } { } - assign $0\sr_op__output_carry$next[0:0]$9205 $1\sr_op__output_carry$next[0:0]$9222 - assign $0\sr_op__output_cr$next[0:0]$9206 $1\sr_op__output_cr$next[0:0]$9223 + assign $0\sr_op__output_carry$next[0:0]$9137 $1\sr_op__output_carry$next[0:0]$9154 + assign $0\sr_op__output_cr$next[0:0]$9138 $1\sr_op__output_cr$next[0:0]$9155 assign { } { } assign { } { } - assign $0\sr_op__write_cr0$next[0:0]$9209 $1\sr_op__write_cr0$next[0:0]$9226 - assign $0\sr_op__imm_data__data$next[63:0]$9194 $2\sr_op__imm_data__data$next[63:0]$9227 - assign $0\sr_op__imm_data__ok$next[0:0]$9195 $2\sr_op__imm_data__ok$next[0:0]$9228 - assign $0\sr_op__oe__oe$next[0:0]$9203 $2\sr_op__oe__oe$next[0:0]$9229 - assign $0\sr_op__oe__ok$next[0:0]$9204 $2\sr_op__oe__ok$next[0:0]$9230 - assign $0\sr_op__rc__ok$next[0:0]$9207 $2\sr_op__rc__ok$next[0:0]$9231 - assign $0\sr_op__rc__rc$next[0:0]$9208 $2\sr_op__rc__rc$next[0:0]$9232 - attribute \src "libresoc.v:167083.5-167083.29" + assign $0\sr_op__write_cr0$next[0:0]$9141 $1\sr_op__write_cr0$next[0:0]$9158 + assign $0\sr_op__imm_data__data$next[63:0]$9126 $2\sr_op__imm_data__data$next[63:0]$9159 + assign $0\sr_op__imm_data__ok$next[0:0]$9127 $2\sr_op__imm_data__ok$next[0:0]$9160 + assign $0\sr_op__oe__oe$next[0:0]$9135 $2\sr_op__oe__oe$next[0:0]$9161 + assign $0\sr_op__oe__ok$next[0:0]$9136 $2\sr_op__oe__ok$next[0:0]$9162 + assign $0\sr_op__rc__ok$next[0:0]$9139 $2\sr_op__rc__ok$next[0:0]$9163 + assign $0\sr_op__rc__rc$next[0:0]$9140 $2\sr_op__rc__rc$next[0:0]$9164 + attribute \src "libresoc.v:167851.5-167851.29" switch \initial - attribute \src "libresoc.v:167083.9-167083.17" + attribute \src "libresoc.v:167851.9-167851.17" case 1'1 case end @@ -344607,7 +311150,7 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$next[31:0]$9215 $1\sr_op__is_signed$next[0:0]$9219 $1\sr_op__is_32bit$next[0:0]$9218 $1\sr_op__output_cr$next[0:0]$9223 $1\sr_op__input_cr$next[0:0]$9214 $1\sr_op__output_carry$next[0:0]$9222 $1\sr_op__input_carry$next[1:0]$9213 $1\sr_op__invert_in$next[0:0]$9217 $1\sr_op__write_cr0$next[0:0]$9226 $1\sr_op__oe__ok$next[0:0]$9221 $1\sr_op__oe__oe$next[0:0]$9220 $1\sr_op__rc__ok$next[0:0]$9224 $1\sr_op__rc__rc$next[0:0]$9225 $1\sr_op__imm_data__ok$next[0:0]$9212 $1\sr_op__imm_data__data$next[63:0]$9211 $1\sr_op__fn_unit$next[13:0]$9210 $1\sr_op__insn_type$next[6:0]$9216 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign { $1\sr_op__insn$next[31:0]$9147 $1\sr_op__is_signed$next[0:0]$9151 $1\sr_op__is_32bit$next[0:0]$9150 $1\sr_op__output_cr$next[0:0]$9155 $1\sr_op__input_cr$next[0:0]$9146 $1\sr_op__output_carry$next[0:0]$9154 $1\sr_op__input_carry$next[1:0]$9145 $1\sr_op__invert_in$next[0:0]$9149 $1\sr_op__write_cr0$next[0:0]$9158 $1\sr_op__oe__ok$next[0:0]$9153 $1\sr_op__oe__oe$next[0:0]$9152 $1\sr_op__rc__ok$next[0:0]$9156 $1\sr_op__rc__rc$next[0:0]$9157 $1\sr_op__imm_data__ok$next[0:0]$9144 $1\sr_op__imm_data__data$next[63:0]$9143 $1\sr_op__fn_unit$next[13:0]$9142 $1\sr_op__insn_type$next[6:0]$9148 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -344627,25 +311170,25 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$next[31:0]$9215 $1\sr_op__is_signed$next[0:0]$9219 $1\sr_op__is_32bit$next[0:0]$9218 $1\sr_op__output_cr$next[0:0]$9223 $1\sr_op__input_cr$next[0:0]$9214 $1\sr_op__output_carry$next[0:0]$9222 $1\sr_op__input_carry$next[1:0]$9213 $1\sr_op__invert_in$next[0:0]$9217 $1\sr_op__write_cr0$next[0:0]$9226 $1\sr_op__oe__ok$next[0:0]$9221 $1\sr_op__oe__oe$next[0:0]$9220 $1\sr_op__rc__ok$next[0:0]$9224 $1\sr_op__rc__rc$next[0:0]$9225 $1\sr_op__imm_data__ok$next[0:0]$9212 $1\sr_op__imm_data__data$next[63:0]$9211 $1\sr_op__fn_unit$next[13:0]$9210 $1\sr_op__insn_type$next[6:0]$9216 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign { $1\sr_op__insn$next[31:0]$9147 $1\sr_op__is_signed$next[0:0]$9151 $1\sr_op__is_32bit$next[0:0]$9150 $1\sr_op__output_cr$next[0:0]$9155 $1\sr_op__input_cr$next[0:0]$9146 $1\sr_op__output_carry$next[0:0]$9154 $1\sr_op__input_carry$next[1:0]$9145 $1\sr_op__invert_in$next[0:0]$9149 $1\sr_op__write_cr0$next[0:0]$9158 $1\sr_op__oe__ok$next[0:0]$9153 $1\sr_op__oe__oe$next[0:0]$9152 $1\sr_op__rc__ok$next[0:0]$9156 $1\sr_op__rc__rc$next[0:0]$9157 $1\sr_op__imm_data__ok$next[0:0]$9144 $1\sr_op__imm_data__data$next[63:0]$9143 $1\sr_op__fn_unit$next[13:0]$9142 $1\sr_op__insn_type$next[6:0]$9148 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } case - assign $1\sr_op__fn_unit$next[13:0]$9210 \sr_op__fn_unit - assign $1\sr_op__imm_data__data$next[63:0]$9211 \sr_op__imm_data__data - assign $1\sr_op__imm_data__ok$next[0:0]$9212 \sr_op__imm_data__ok - assign $1\sr_op__input_carry$next[1:0]$9213 \sr_op__input_carry - assign $1\sr_op__input_cr$next[0:0]$9214 \sr_op__input_cr - assign $1\sr_op__insn$next[31:0]$9215 \sr_op__insn - assign $1\sr_op__insn_type$next[6:0]$9216 \sr_op__insn_type - assign $1\sr_op__invert_in$next[0:0]$9217 \sr_op__invert_in - assign $1\sr_op__is_32bit$next[0:0]$9218 \sr_op__is_32bit - assign $1\sr_op__is_signed$next[0:0]$9219 \sr_op__is_signed - assign $1\sr_op__oe__oe$next[0:0]$9220 \sr_op__oe__oe - assign $1\sr_op__oe__ok$next[0:0]$9221 \sr_op__oe__ok - assign $1\sr_op__output_carry$next[0:0]$9222 \sr_op__output_carry - assign $1\sr_op__output_cr$next[0:0]$9223 \sr_op__output_cr - assign $1\sr_op__rc__ok$next[0:0]$9224 \sr_op__rc__ok - assign $1\sr_op__rc__rc$next[0:0]$9225 \sr_op__rc__rc - assign $1\sr_op__write_cr0$next[0:0]$9226 \sr_op__write_cr0 + assign $1\sr_op__fn_unit$next[13:0]$9142 \sr_op__fn_unit + assign $1\sr_op__imm_data__data$next[63:0]$9143 \sr_op__imm_data__data + assign $1\sr_op__imm_data__ok$next[0:0]$9144 \sr_op__imm_data__ok + assign $1\sr_op__input_carry$next[1:0]$9145 \sr_op__input_carry + assign $1\sr_op__input_cr$next[0:0]$9146 \sr_op__input_cr + assign $1\sr_op__insn$next[31:0]$9147 \sr_op__insn + assign $1\sr_op__insn_type$next[6:0]$9148 \sr_op__insn_type + assign $1\sr_op__invert_in$next[0:0]$9149 \sr_op__invert_in + assign $1\sr_op__is_32bit$next[0:0]$9150 \sr_op__is_32bit + assign $1\sr_op__is_signed$next[0:0]$9151 \sr_op__is_signed + assign $1\sr_op__oe__oe$next[0:0]$9152 \sr_op__oe__oe + assign $1\sr_op__oe__ok$next[0:0]$9153 \sr_op__oe__ok + assign $1\sr_op__output_carry$next[0:0]$9154 \sr_op__output_carry + assign $1\sr_op__output_cr$next[0:0]$9155 \sr_op__output_cr + assign $1\sr_op__rc__ok$next[0:0]$9156 \sr_op__rc__ok + assign $1\sr_op__rc__rc$next[0:0]$9157 \sr_op__rc__rc + assign $1\sr_op__write_cr0$next[0:0]$9158 \sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -344657,51 +311200,51 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign $2\sr_op__imm_data__data$next[63:0]$9227 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$next[0:0]$9228 1'0 - assign $2\sr_op__rc__rc$next[0:0]$9232 1'0 - assign $2\sr_op__rc__ok$next[0:0]$9231 1'0 - assign $2\sr_op__oe__oe$next[0:0]$9229 1'0 - assign $2\sr_op__oe__ok$next[0:0]$9230 1'0 + assign $2\sr_op__imm_data__data$next[63:0]$9159 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$next[0:0]$9160 1'0 + assign $2\sr_op__rc__rc$next[0:0]$9164 1'0 + assign $2\sr_op__rc__ok$next[0:0]$9163 1'0 + assign $2\sr_op__oe__oe$next[0:0]$9161 1'0 + assign $2\sr_op__oe__ok$next[0:0]$9162 1'0 case - assign $2\sr_op__imm_data__data$next[63:0]$9227 $1\sr_op__imm_data__data$next[63:0]$9211 - assign $2\sr_op__imm_data__ok$next[0:0]$9228 $1\sr_op__imm_data__ok$next[0:0]$9212 - assign $2\sr_op__oe__oe$next[0:0]$9229 $1\sr_op__oe__oe$next[0:0]$9220 - assign $2\sr_op__oe__ok$next[0:0]$9230 $1\sr_op__oe__ok$next[0:0]$9221 - assign $2\sr_op__rc__ok$next[0:0]$9231 $1\sr_op__rc__ok$next[0:0]$9224 - assign $2\sr_op__rc__rc$next[0:0]$9232 $1\sr_op__rc__rc$next[0:0]$9225 + assign $2\sr_op__imm_data__data$next[63:0]$9159 $1\sr_op__imm_data__data$next[63:0]$9143 + assign $2\sr_op__imm_data__ok$next[0:0]$9160 $1\sr_op__imm_data__ok$next[0:0]$9144 + assign $2\sr_op__oe__oe$next[0:0]$9161 $1\sr_op__oe__oe$next[0:0]$9152 + assign $2\sr_op__oe__ok$next[0:0]$9162 $1\sr_op__oe__ok$next[0:0]$9153 + assign $2\sr_op__rc__ok$next[0:0]$9163 $1\sr_op__rc__ok$next[0:0]$9156 + assign $2\sr_op__rc__rc$next[0:0]$9164 $1\sr_op__rc__rc$next[0:0]$9157 end sync always - update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[13:0]$9193 - update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9194 - update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9195 - update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9196 - update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9197 - update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9198 - update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9199 - update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9200 - update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9201 - update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9202 - update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9203 - update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9204 - update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9205 - update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9206 - update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9207 - update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9208 - update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9209 + update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[13:0]$9125 + update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9126 + update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9127 + update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9128 + update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9129 + update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9130 + update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9131 + update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9132 + update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9133 + update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9134 + update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9135 + update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9136 + update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9137 + update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9138 + update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9139 + update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9140 + update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9141 end - attribute \src "libresoc.v:167123.3-167141.6" - process $proc$libresoc.v:167123$9233 + attribute \src "libresoc.v:167891.3-167909.6" + process $proc$libresoc.v:167891$9165 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9234 $1\o$next[63:0]$9236 + assign $0\o$next[63:0]$9166 $1\o$next[63:0]$9168 assign { } { } - assign $0\o_ok$next[0:0]$9235 $2\o_ok$next[0:0]$9238 - attribute \src "libresoc.v:167124.5-167124.29" + assign $0\o_ok$next[0:0]$9167 $2\o_ok$next[0:0]$9170 + attribute \src "libresoc.v:167892.5-167892.29" switch \initial - attribute \src "libresoc.v:167124.9-167124.17" + attribute \src "libresoc.v:167892.9-167892.17" case 1'1 case end @@ -344711,41 +311254,41 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9237 $1\o$next[63:0]$9236 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$9169 $1\o$next[63:0]$9168 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9237 $1\o$next[63:0]$9236 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$9169 $1\o$next[63:0]$9168 } { \o_ok$86 \o$85 } case - assign $1\o$next[63:0]$9236 \o - assign $1\o_ok$next[0:0]$9237 \o_ok + assign $1\o$next[63:0]$9168 \o + assign $1\o_ok$next[0:0]$9169 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9238 1'0 + assign $2\o_ok$next[0:0]$9170 1'0 case - assign $2\o_ok$next[0:0]$9238 $1\o_ok$next[0:0]$9237 + assign $2\o_ok$next[0:0]$9170 $1\o_ok$next[0:0]$9169 end sync always - update \o$next $0\o$next[63:0]$9234 - update \o_ok$next $0\o_ok$next[0:0]$9235 + update \o$next $0\o$next[63:0]$9166 + update \o_ok$next $0\o_ok$next[0:0]$9167 end - attribute \src "libresoc.v:167142.3-167160.6" - process $proc$libresoc.v:167142$9239 + attribute \src "libresoc.v:167910.3-167928.6" + process $proc$libresoc.v:167910$9171 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9240 $1\cr_a$next[3:0]$9242 + assign $0\cr_a$next[3:0]$9172 $1\cr_a$next[3:0]$9174 assign { } { } - assign $0\cr_a_ok$next[0:0]$9241 $2\cr_a_ok$next[0:0]$9244 - attribute \src "libresoc.v:167143.5-167143.29" + assign $0\cr_a_ok$next[0:0]$9173 $2\cr_a_ok$next[0:0]$9176 + attribute \src "libresoc.v:167911.5-167911.29" switch \initial - attribute \src "libresoc.v:167143.9-167143.17" + attribute \src "libresoc.v:167911.9-167911.17" case 1'1 case end @@ -344755,41 +311298,41 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9243 $1\cr_a$next[3:0]$9242 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$9175 $1\cr_a$next[3:0]$9174 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9243 $1\cr_a$next[3:0]$9242 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$9175 $1\cr_a$next[3:0]$9174 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\cr_a$next[3:0]$9242 \cr_a - assign $1\cr_a_ok$next[0:0]$9243 \cr_a_ok + assign $1\cr_a$next[3:0]$9174 \cr_a + assign $1\cr_a_ok$next[0:0]$9175 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9244 1'0 + assign $2\cr_a_ok$next[0:0]$9176 1'0 case - assign $2\cr_a_ok$next[0:0]$9244 $1\cr_a_ok$next[0:0]$9243 + assign $2\cr_a_ok$next[0:0]$9176 $1\cr_a_ok$next[0:0]$9175 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9240 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9241 + update \cr_a$next $0\cr_a$next[3:0]$9172 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9173 end - attribute \src "libresoc.v:167161.3-167179.6" - process $proc$libresoc.v:167161$9245 + attribute \src "libresoc.v:167929.3-167947.6" + process $proc$libresoc.v:167929$9177 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$9246 $1\xer_so$next[0:0]$9248 + assign $0\xer_so$next[0:0]$9178 $1\xer_so$next[0:0]$9180 assign { } { } - assign $0\xer_so_ok$next[0:0]$9247 $2\xer_so_ok$next[0:0]$9250 - attribute \src "libresoc.v:167162.5-167162.29" + assign $0\xer_so_ok$next[0:0]$9179 $2\xer_so_ok$next[0:0]$9182 + attribute \src "libresoc.v:167930.5-167930.29" switch \initial - attribute \src "libresoc.v:167162.9-167162.17" + attribute \src "libresoc.v:167930.9-167930.17" case 1'1 case end @@ -344799,30 +311342,30 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9249 $1\xer_so$next[0:0]$9248 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$9181 $1\xer_so$next[0:0]$9180 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9249 $1\xer_so$next[0:0]$9248 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$9181 $1\xer_so$next[0:0]$9180 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_so$next[0:0]$9248 \xer_so - assign $1\xer_so_ok$next[0:0]$9249 \xer_so_ok + assign $1\xer_so$next[0:0]$9180 \xer_so + assign $1\xer_so_ok$next[0:0]$9181 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9250 1'0 + assign $2\xer_so_ok$next[0:0]$9182 1'0 case - assign $2\xer_so_ok$next[0:0]$9250 $1\xer_so_ok$next[0:0]$9249 + assign $2\xer_so_ok$next[0:0]$9182 $1\xer_so_ok$next[0:0]$9181 end sync always - update \xer_so$next $0\xer_so$next[0:0]$9246 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9247 + update \xer_so$next $0\xer_so$next[0:0]$9178 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9179 end - connect \$65 $and$libresoc.v:166875$9151_Y + connect \$65 $and$libresoc.v:167643$9083_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -344853,142 +311396,142 @@ module \pipe1$110 connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:167213.1-168061.10" +attribute \src "libresoc.v:167981.1-168829.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" attribute \generator "nMigen" module \pipe1$32 - attribute \src "libresoc.v:168018.3-168030.6" - wire width 64 $0\fast1$next[63:0]$9328 - attribute \src "libresoc.v:167874.3-167875.27" + attribute \src "libresoc.v:168786.3-168798.6" + wire width 64 $0\fast1$next[63:0]$9260 + attribute \src "libresoc.v:168642.3-168643.27" wire width 64 $0\fast1[63:0] - attribute \src "libresoc.v:168031.3-168043.6" - wire width 64 $0\fast2$next[63:0]$9331 - attribute \src "libresoc.v:167872.3-167873.27" + attribute \src "libresoc.v:168799.3-168811.6" + wire width 64 $0\fast2$next[63:0]$9263 + attribute \src "libresoc.v:168640.3-168641.27" wire width 64 $0\fast2[63:0] - attribute \src "libresoc.v:167214.7-167214.20" + attribute \src "libresoc.v:167982.7-167982.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167958.3-167970.6" - wire width 2 $0\muxid$next[1:0]$9300 - attribute \src "libresoc.v:167898.3-167899.27" + attribute \src "libresoc.v:168726.3-168738.6" + wire width 2 $0\muxid$next[1:0]$9232 + attribute \src "libresoc.v:168666.3-168667.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:167940.3-167957.6" - wire $0\r_busy$next[0:0]$9296 - attribute \src "libresoc.v:167900.3-167901.29" + attribute \src "libresoc.v:168708.3-168725.6" + wire $0\r_busy$next[0:0]$9228 + attribute \src "libresoc.v:168668.3-168669.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:167992.3-168004.6" - wire width 64 $0\ra$next[63:0]$9322 - attribute \src "libresoc.v:167878.3-167879.21" + attribute \src "libresoc.v:168760.3-168772.6" + wire width 64 $0\ra$next[63:0]$9254 + attribute \src "libresoc.v:168646.3-168647.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:168005.3-168017.6" - wire width 64 $0\rb$next[63:0]$9325 - attribute \src "libresoc.v:167876.3-167877.21" + attribute \src "libresoc.v:168773.3-168785.6" + wire width 64 $0\rb$next[63:0]$9257 + attribute \src "libresoc.v:168644.3-168645.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 64 $0\trap_op__cia$next[63:0]$9303 - attribute \src "libresoc.v:167888.3-167889.41" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 64 $0\trap_op__cia$next[63:0]$9235 + attribute \src "libresoc.v:168656.3-168657.41" wire width 64 $0\trap_op__cia[63:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 14 $0\trap_op__fn_unit$next[13:0]$9304 - attribute \src "libresoc.v:167882.3-167883.49" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 14 $0\trap_op__fn_unit$next[13:0]$9236 + attribute \src "libresoc.v:168650.3-168651.49" wire width 14 $0\trap_op__fn_unit[13:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 32 $0\trap_op__insn$next[31:0]$9305 - attribute \src "libresoc.v:167884.3-167885.43" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 32 $0\trap_op__insn$next[31:0]$9237 + attribute \src "libresoc.v:168652.3-168653.43" wire width 32 $0\trap_op__insn[31:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 7 $0\trap_op__insn_type$next[6:0]$9306 - attribute \src "libresoc.v:167880.3-167881.53" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 7 $0\trap_op__insn_type$next[6:0]$9238 + attribute \src "libresoc.v:168648.3-168649.53" wire width 7 $0\trap_op__insn_type[6:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire $0\trap_op__is_32bit$next[0:0]$9307 - attribute \src "libresoc.v:167890.3-167891.51" + attribute \src "libresoc.v:168739.3-168759.6" + wire $0\trap_op__is_32bit$next[0:0]$9239 + attribute \src "libresoc.v:168658.3-168659.51" wire $0\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 8 $0\trap_op__ldst_exc$next[7:0]$9308 - attribute \src "libresoc.v:167896.3-167897.51" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 8 $0\trap_op__ldst_exc$next[7:0]$9240 + attribute \src "libresoc.v:168664.3-168665.51" wire width 8 $0\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 64 $0\trap_op__msr$next[63:0]$9309 - attribute \src "libresoc.v:167886.3-167887.41" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 64 $0\trap_op__msr$next[63:0]$9241 + attribute \src "libresoc.v:168654.3-168655.41" wire width 64 $0\trap_op__msr[63:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 13 $0\trap_op__trapaddr$next[12:0]$9310 - attribute \src "libresoc.v:167894.3-167895.51" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 13 $0\trap_op__trapaddr$next[12:0]$9242 + attribute \src "libresoc.v:168662.3-168663.51" wire width 13 $0\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 8 $0\trap_op__traptype$next[7:0]$9311 - attribute \src "libresoc.v:167892.3-167893.51" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 8 $0\trap_op__traptype$next[7:0]$9243 + attribute \src "libresoc.v:168660.3-168661.51" wire width 8 $0\trap_op__traptype[7:0] - attribute \src "libresoc.v:168018.3-168030.6" - wire width 64 $1\fast1$next[63:0]$9329 - attribute \src "libresoc.v:167459.14-167459.42" + attribute \src "libresoc.v:168786.3-168798.6" + wire width 64 $1\fast1$next[63:0]$9261 + attribute \src "libresoc.v:168227.14-168227.42" wire width 64 $1\fast1[63:0] - attribute \src "libresoc.v:168031.3-168043.6" - wire width 64 $1\fast2$next[63:0]$9332 - attribute \src "libresoc.v:167468.14-167468.42" + attribute \src "libresoc.v:168799.3-168811.6" + wire width 64 $1\fast2$next[63:0]$9264 + attribute \src "libresoc.v:168236.14-168236.42" wire width 64 $1\fast2[63:0] - attribute \src "libresoc.v:167958.3-167970.6" - wire width 2 $1\muxid$next[1:0]$9301 - attribute \src "libresoc.v:167477.13-167477.25" + attribute \src "libresoc.v:168726.3-168738.6" + wire width 2 $1\muxid$next[1:0]$9233 + attribute \src "libresoc.v:168245.13-168245.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:167940.3-167957.6" - wire $1\r_busy$next[0:0]$9297 - attribute \src "libresoc.v:167499.7-167499.20" + attribute \src "libresoc.v:168708.3-168725.6" + wire $1\r_busy$next[0:0]$9229 + attribute \src "libresoc.v:168267.7-168267.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:167992.3-168004.6" - wire width 64 $1\ra$next[63:0]$9323 - attribute \src "libresoc.v:167504.14-167504.39" + attribute \src "libresoc.v:168760.3-168772.6" + wire width 64 $1\ra$next[63:0]$9255 + attribute \src "libresoc.v:168272.14-168272.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:168005.3-168017.6" - wire width 64 $1\rb$next[63:0]$9326 - attribute \src "libresoc.v:167513.14-167513.39" + attribute \src "libresoc.v:168773.3-168785.6" + wire width 64 $1\rb$next[63:0]$9258 + attribute \src "libresoc.v:168281.14-168281.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 64 $1\trap_op__cia$next[63:0]$9312 - attribute \src "libresoc.v:167522.14-167522.49" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 64 $1\trap_op__cia$next[63:0]$9244 + attribute \src "libresoc.v:168290.14-168290.49" wire width 64 $1\trap_op__cia[63:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 14 $1\trap_op__fn_unit$next[13:0]$9313 - attribute \src "libresoc.v:167546.14-167546.41" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 14 $1\trap_op__fn_unit$next[13:0]$9245 + attribute \src "libresoc.v:168314.14-168314.41" wire width 14 $1\trap_op__fn_unit[13:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 32 $1\trap_op__insn$next[31:0]$9314 - attribute \src "libresoc.v:167585.14-167585.35" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 32 $1\trap_op__insn$next[31:0]$9246 + attribute \src "libresoc.v:168353.14-168353.35" wire width 32 $1\trap_op__insn[31:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 7 $1\trap_op__insn_type$next[6:0]$9315 - attribute \src "libresoc.v:167669.13-167669.39" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 7 $1\trap_op__insn_type$next[6:0]$9247 + attribute \src "libresoc.v:168437.13-168437.39" wire width 7 $1\trap_op__insn_type[6:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire $1\trap_op__is_32bit$next[0:0]$9316 - attribute \src "libresoc.v:167828.7-167828.31" + attribute \src "libresoc.v:168739.3-168759.6" + wire $1\trap_op__is_32bit$next[0:0]$9248 + attribute \src "libresoc.v:168596.7-168596.31" wire $1\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 8 $1\trap_op__ldst_exc$next[7:0]$9317 - attribute \src "libresoc.v:167837.13-167837.38" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 8 $1\trap_op__ldst_exc$next[7:0]$9249 + attribute \src "libresoc.v:168605.13-168605.38" wire width 8 $1\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 64 $1\trap_op__msr$next[63:0]$9318 - attribute \src "libresoc.v:167846.14-167846.49" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 64 $1\trap_op__msr$next[63:0]$9250 + attribute \src "libresoc.v:168614.14-168614.49" wire width 64 $1\trap_op__msr[63:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 13 $1\trap_op__trapaddr$next[12:0]$9319 - attribute \src "libresoc.v:167855.14-167855.42" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 13 $1\trap_op__trapaddr$next[12:0]$9251 + attribute \src "libresoc.v:168623.14-168623.42" wire width 13 $1\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:167971.3-167991.6" - wire width 8 $1\trap_op__traptype$next[7:0]$9320 - attribute \src "libresoc.v:167864.13-167864.38" + attribute \src "libresoc.v:168739.3-168759.6" + wire width 8 $1\trap_op__traptype$next[7:0]$9252 + attribute \src "libresoc.v:168632.13-168632.38" wire width 8 $1\trap_op__traptype[7:0] - attribute \src "libresoc.v:167940.3-167957.6" - wire $2\r_busy$next[0:0]$9298 - attribute \src "libresoc.v:167871.18-167871.118" - wire $and$libresoc.v:167871$9279_Y + attribute \src "libresoc.v:168708.3-168725.6" + wire $2\r_busy$next[0:0]$9230 + attribute \src "libresoc.v:168639.18-168639.118" + wire $and$libresoc.v:168639$9211_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \dummy_fast1 @@ -345242,7 +311785,7 @@ module \pipe1$32 wire width 64 \fast2$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \fast2$next - attribute \src "libresoc.v:167214.7-167214.15" + attribute \src "libresoc.v:167982.7-167982.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid @@ -345629,7 +312172,7 @@ module \pipe1$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:167871$9279 + cell $and $and$libresoc.v:168639$9211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -345637,10 +312180,10 @@ module \pipe1$32 parameter \Y_WIDTH 1 connect \A \p_valid_i$29 connect \B \p_ready_o - connect \Y $and$libresoc.v:167871$9279_Y + connect \Y $and$libresoc.v:168639$9211_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:167902.9-167931.4" + attribute \src "libresoc.v:168670.9-168699.4" cell \dummy \dummy connect \fast1 \dummy_fast1 connect \fast1$13 \dummy_fast1$27 @@ -345672,259 +312215,259 @@ module \pipe1$32 connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 end attribute \module_not_derived 1 - attribute \src "libresoc.v:167932.10-167935.4" + attribute \src "libresoc.v:168700.10-168703.4" cell \n$34 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:167936.10-167939.4" + attribute \src "libresoc.v:168704.10-168707.4" cell \p$33 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:167214.7-167214.20" - process $proc$libresoc.v:167214$9333 + attribute \src "libresoc.v:167982.7-167982.20" + process $proc$libresoc.v:167982$9265 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:167459.14-167459.42" - process $proc$libresoc.v:167459$9334 + attribute \src "libresoc.v:168227.14-168227.42" + process $proc$libresoc.v:168227$9266 assign { } { } assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1 $1\fast1[63:0] end - attribute \src "libresoc.v:167468.14-167468.42" - process $proc$libresoc.v:167468$9335 + attribute \src "libresoc.v:168236.14-168236.42" + process $proc$libresoc.v:168236$9267 assign { } { } assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast2 $1\fast2[63:0] end - attribute \src "libresoc.v:167477.13-167477.25" - process $proc$libresoc.v:167477$9336 + attribute \src "libresoc.v:168245.13-168245.25" + process $proc$libresoc.v:168245$9268 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:167499.7-167499.20" - process $proc$libresoc.v:167499$9337 + attribute \src "libresoc.v:168267.7-168267.20" + process $proc$libresoc.v:168267$9269 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:167504.14-167504.39" - process $proc$libresoc.v:167504$9338 + attribute \src "libresoc.v:168272.14-168272.39" + process $proc$libresoc.v:168272$9270 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:167513.14-167513.39" - process $proc$libresoc.v:167513$9339 + attribute \src "libresoc.v:168281.14-168281.39" + process $proc$libresoc.v:168281$9271 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:167522.14-167522.49" - process $proc$libresoc.v:167522$9340 + attribute \src "libresoc.v:168290.14-168290.49" + process $proc$libresoc.v:168290$9272 assign { } { } assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__cia $1\trap_op__cia[63:0] end - attribute \src "libresoc.v:167546.14-167546.41" - process $proc$libresoc.v:167546$9341 + attribute \src "libresoc.v:168314.14-168314.41" + process $proc$libresoc.v:168314$9273 assign { } { } assign $1\trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \trap_op__fn_unit $1\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:167585.14-167585.35" - process $proc$libresoc.v:167585$9342 + attribute \src "libresoc.v:168353.14-168353.35" + process $proc$libresoc.v:168353$9274 assign { } { } assign $1\trap_op__insn[31:0] 0 sync always sync init update \trap_op__insn $1\trap_op__insn[31:0] end - attribute \src "libresoc.v:167669.13-167669.39" - process $proc$libresoc.v:167669$9343 + attribute \src "libresoc.v:168437.13-168437.39" + process $proc$libresoc.v:168437$9275 assign { } { } assign $1\trap_op__insn_type[6:0] 7'0000000 sync always sync init update \trap_op__insn_type $1\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:167828.7-167828.31" - process $proc$libresoc.v:167828$9344 + attribute \src "libresoc.v:168596.7-168596.31" + process $proc$libresoc.v:168596$9276 assign { } { } assign $1\trap_op__is_32bit[0:0] 1'0 sync always sync init update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:167837.13-167837.38" - process $proc$libresoc.v:167837$9345 + attribute \src "libresoc.v:168605.13-168605.38" + process $proc$libresoc.v:168605$9277 assign { } { } assign $1\trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:167846.14-167846.49" - process $proc$libresoc.v:167846$9346 + attribute \src "libresoc.v:168614.14-168614.49" + process $proc$libresoc.v:168614$9278 assign { } { } assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__msr $1\trap_op__msr[63:0] end - attribute \src "libresoc.v:167855.14-167855.42" - process $proc$libresoc.v:167855$9347 + attribute \src "libresoc.v:168623.14-168623.42" + process $proc$libresoc.v:168623$9279 assign { } { } assign $1\trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:167864.13-167864.38" - process $proc$libresoc.v:167864$9348 + attribute \src "libresoc.v:168632.13-168632.38" + process $proc$libresoc.v:168632$9280 assign { } { } assign $1\trap_op__traptype[7:0] 8'00000000 sync always sync init update \trap_op__traptype $1\trap_op__traptype[7:0] end - attribute \src "libresoc.v:167872.3-167873.27" - process $proc$libresoc.v:167872$9280 + attribute \src "libresoc.v:168640.3-168641.27" + process $proc$libresoc.v:168640$9212 assign { } { } assign $0\fast2[63:0] \fast2$next sync posedge \coresync_clk update \fast2 $0\fast2[63:0] end - attribute \src "libresoc.v:167874.3-167875.27" - process $proc$libresoc.v:167874$9281 + attribute \src "libresoc.v:168642.3-168643.27" + process $proc$libresoc.v:168642$9213 assign { } { } assign $0\fast1[63:0] \fast1$next sync posedge \coresync_clk update \fast1 $0\fast1[63:0] end - attribute \src "libresoc.v:167876.3-167877.21" - process $proc$libresoc.v:167876$9282 + attribute \src "libresoc.v:168644.3-168645.21" + process $proc$libresoc.v:168644$9214 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:167878.3-167879.21" - process $proc$libresoc.v:167878$9283 + attribute \src "libresoc.v:168646.3-168647.21" + process $proc$libresoc.v:168646$9215 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:167880.3-167881.53" - process $proc$libresoc.v:167880$9284 + attribute \src "libresoc.v:168648.3-168649.53" + process $proc$libresoc.v:168648$9216 assign { } { } assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next sync posedge \coresync_clk update \trap_op__insn_type $0\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:167882.3-167883.49" - process $proc$libresoc.v:167882$9285 + attribute \src "libresoc.v:168650.3-168651.49" + process $proc$libresoc.v:168650$9217 assign { } { } assign $0\trap_op__fn_unit[13:0] \trap_op__fn_unit$next sync posedge \coresync_clk update \trap_op__fn_unit $0\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:167884.3-167885.43" - process $proc$libresoc.v:167884$9286 + attribute \src "libresoc.v:168652.3-168653.43" + process $proc$libresoc.v:168652$9218 assign { } { } assign $0\trap_op__insn[31:0] \trap_op__insn$next sync posedge \coresync_clk update \trap_op__insn $0\trap_op__insn[31:0] end - attribute \src "libresoc.v:167886.3-167887.41" - process $proc$libresoc.v:167886$9287 + attribute \src "libresoc.v:168654.3-168655.41" + process $proc$libresoc.v:168654$9219 assign { } { } assign $0\trap_op__msr[63:0] \trap_op__msr$next sync posedge \coresync_clk update \trap_op__msr $0\trap_op__msr[63:0] end - attribute \src "libresoc.v:167888.3-167889.41" - process $proc$libresoc.v:167888$9288 + attribute \src "libresoc.v:168656.3-168657.41" + process $proc$libresoc.v:168656$9220 assign { } { } assign $0\trap_op__cia[63:0] \trap_op__cia$next sync posedge \coresync_clk update \trap_op__cia $0\trap_op__cia[63:0] end - attribute \src "libresoc.v:167890.3-167891.51" - process $proc$libresoc.v:167890$9289 + attribute \src "libresoc.v:168658.3-168659.51" + process $proc$libresoc.v:168658$9221 assign { } { } assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next sync posedge \coresync_clk update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:167892.3-167893.51" - process $proc$libresoc.v:167892$9290 + attribute \src "libresoc.v:168660.3-168661.51" + process $proc$libresoc.v:168660$9222 assign { } { } assign $0\trap_op__traptype[7:0] \trap_op__traptype$next sync posedge \coresync_clk update \trap_op__traptype $0\trap_op__traptype[7:0] end - attribute \src "libresoc.v:167894.3-167895.51" - process $proc$libresoc.v:167894$9291 + attribute \src "libresoc.v:168662.3-168663.51" + process $proc$libresoc.v:168662$9223 assign { } { } assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next sync posedge \coresync_clk update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:167896.3-167897.51" - process $proc$libresoc.v:167896$9292 + attribute \src "libresoc.v:168664.3-168665.51" + process $proc$libresoc.v:168664$9224 assign { } { } assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next sync posedge \coresync_clk update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:167898.3-167899.27" - process $proc$libresoc.v:167898$9293 + attribute \src "libresoc.v:168666.3-168667.27" + process $proc$libresoc.v:168666$9225 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:167900.3-167901.29" - process $proc$libresoc.v:167900$9294 + attribute \src "libresoc.v:168668.3-168669.29" + process $proc$libresoc.v:168668$9226 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:167940.3-167957.6" - process $proc$libresoc.v:167940$9295 + attribute \src "libresoc.v:168708.3-168725.6" + process $proc$libresoc.v:168708$9227 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9296 $2\r_busy$next[0:0]$9298 - attribute \src "libresoc.v:167941.5-167941.29" + assign $0\r_busy$next[0:0]$9228 $2\r_busy$next[0:0]$9230 + attribute \src "libresoc.v:168709.5-168709.29" switch \initial - attribute \src "libresoc.v:167941.9-167941.17" + attribute \src "libresoc.v:168709.9-168709.17" case 1'1 case end @@ -345933,34 +312476,34 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9297 1'1 + assign $1\r_busy$next[0:0]$9229 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9297 1'0 + assign $1\r_busy$next[0:0]$9229 1'0 case - assign $1\r_busy$next[0:0]$9297 \r_busy + assign $1\r_busy$next[0:0]$9229 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9298 1'0 + assign $2\r_busy$next[0:0]$9230 1'0 case - assign $2\r_busy$next[0:0]$9298 $1\r_busy$next[0:0]$9297 + assign $2\r_busy$next[0:0]$9230 $1\r_busy$next[0:0]$9229 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9296 + update \r_busy$next $0\r_busy$next[0:0]$9228 end - attribute \src "libresoc.v:167958.3-167970.6" - process $proc$libresoc.v:167958$9299 + attribute \src "libresoc.v:168726.3-168738.6" + process $proc$libresoc.v:168726$9231 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9300 $1\muxid$next[1:0]$9301 - attribute \src "libresoc.v:167959.5-167959.29" + assign $0\muxid$next[1:0]$9232 $1\muxid$next[1:0]$9233 + attribute \src "libresoc.v:168727.5-168727.29" switch \initial - attribute \src "libresoc.v:167959.9-167959.17" + attribute \src "libresoc.v:168727.9-168727.17" case 1'1 case end @@ -345969,19 +312512,19 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9301 \muxid$32 + assign $1\muxid$next[1:0]$9233 \muxid$32 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9301 \muxid$32 + assign $1\muxid$next[1:0]$9233 \muxid$32 case - assign $1\muxid$next[1:0]$9301 \muxid + assign $1\muxid$next[1:0]$9233 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9300 + update \muxid$next $0\muxid$next[1:0]$9232 end - attribute \src "libresoc.v:167971.3-167991.6" - process $proc$libresoc.v:167971$9302 + attribute \src "libresoc.v:168739.3-168759.6" + process $proc$libresoc.v:168739$9234 assign { } { } assign { } { } assign { } { } @@ -346000,18 +312543,18 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign $0\trap_op__cia$next[63:0]$9303 $1\trap_op__cia$next[63:0]$9312 - assign $0\trap_op__fn_unit$next[13:0]$9304 $1\trap_op__fn_unit$next[13:0]$9313 - assign $0\trap_op__insn$next[31:0]$9305 $1\trap_op__insn$next[31:0]$9314 - assign $0\trap_op__insn_type$next[6:0]$9306 $1\trap_op__insn_type$next[6:0]$9315 - assign $0\trap_op__is_32bit$next[0:0]$9307 $1\trap_op__is_32bit$next[0:0]$9316 - assign $0\trap_op__ldst_exc$next[7:0]$9308 $1\trap_op__ldst_exc$next[7:0]$9317 - assign $0\trap_op__msr$next[63:0]$9309 $1\trap_op__msr$next[63:0]$9318 - assign $0\trap_op__trapaddr$next[12:0]$9310 $1\trap_op__trapaddr$next[12:0]$9319 - assign $0\trap_op__traptype$next[7:0]$9311 $1\trap_op__traptype$next[7:0]$9320 - attribute \src "libresoc.v:167972.5-167972.29" + assign $0\trap_op__cia$next[63:0]$9235 $1\trap_op__cia$next[63:0]$9244 + assign $0\trap_op__fn_unit$next[13:0]$9236 $1\trap_op__fn_unit$next[13:0]$9245 + assign $0\trap_op__insn$next[31:0]$9237 $1\trap_op__insn$next[31:0]$9246 + assign $0\trap_op__insn_type$next[6:0]$9238 $1\trap_op__insn_type$next[6:0]$9247 + assign $0\trap_op__is_32bit$next[0:0]$9239 $1\trap_op__is_32bit$next[0:0]$9248 + assign $0\trap_op__ldst_exc$next[7:0]$9240 $1\trap_op__ldst_exc$next[7:0]$9249 + assign $0\trap_op__msr$next[63:0]$9241 $1\trap_op__msr$next[63:0]$9250 + assign $0\trap_op__trapaddr$next[12:0]$9242 $1\trap_op__trapaddr$next[12:0]$9251 + assign $0\trap_op__traptype$next[7:0]$9243 $1\trap_op__traptype$next[7:0]$9252 + attribute \src "libresoc.v:168740.5-168740.29" switch \initial - attribute \src "libresoc.v:167972.9-167972.17" + attribute \src "libresoc.v:168740.9-168740.17" case 1'1 case end @@ -346028,7 +312571,7 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$9317 $1\trap_op__trapaddr$next[12:0]$9319 $1\trap_op__traptype$next[7:0]$9320 $1\trap_op__is_32bit$next[0:0]$9316 $1\trap_op__cia$next[63:0]$9312 $1\trap_op__msr$next[63:0]$9318 $1\trap_op__insn$next[31:0]$9314 $1\trap_op__fn_unit$next[13:0]$9313 $1\trap_op__insn_type$next[6:0]$9315 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + assign { $1\trap_op__ldst_exc$next[7:0]$9249 $1\trap_op__trapaddr$next[12:0]$9251 $1\trap_op__traptype$next[7:0]$9252 $1\trap_op__is_32bit$next[0:0]$9248 $1\trap_op__cia$next[63:0]$9244 $1\trap_op__msr$next[63:0]$9250 $1\trap_op__insn$next[31:0]$9246 $1\trap_op__fn_unit$next[13:0]$9245 $1\trap_op__insn_type$next[6:0]$9247 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -346040,37 +312583,37 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$9317 $1\trap_op__trapaddr$next[12:0]$9319 $1\trap_op__traptype$next[7:0]$9320 $1\trap_op__is_32bit$next[0:0]$9316 $1\trap_op__cia$next[63:0]$9312 $1\trap_op__msr$next[63:0]$9318 $1\trap_op__insn$next[31:0]$9314 $1\trap_op__fn_unit$next[13:0]$9313 $1\trap_op__insn_type$next[6:0]$9315 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + assign { $1\trap_op__ldst_exc$next[7:0]$9249 $1\trap_op__trapaddr$next[12:0]$9251 $1\trap_op__traptype$next[7:0]$9252 $1\trap_op__is_32bit$next[0:0]$9248 $1\trap_op__cia$next[63:0]$9244 $1\trap_op__msr$next[63:0]$9250 $1\trap_op__insn$next[31:0]$9246 $1\trap_op__fn_unit$next[13:0]$9245 $1\trap_op__insn_type$next[6:0]$9247 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } case - assign $1\trap_op__cia$next[63:0]$9312 \trap_op__cia - assign $1\trap_op__fn_unit$next[13:0]$9313 \trap_op__fn_unit - assign $1\trap_op__insn$next[31:0]$9314 \trap_op__insn - assign $1\trap_op__insn_type$next[6:0]$9315 \trap_op__insn_type - assign $1\trap_op__is_32bit$next[0:0]$9316 \trap_op__is_32bit - assign $1\trap_op__ldst_exc$next[7:0]$9317 \trap_op__ldst_exc - assign $1\trap_op__msr$next[63:0]$9318 \trap_op__msr - assign $1\trap_op__trapaddr$next[12:0]$9319 \trap_op__trapaddr - assign $1\trap_op__traptype$next[7:0]$9320 \trap_op__traptype + assign $1\trap_op__cia$next[63:0]$9244 \trap_op__cia + assign $1\trap_op__fn_unit$next[13:0]$9245 \trap_op__fn_unit + assign $1\trap_op__insn$next[31:0]$9246 \trap_op__insn + assign $1\trap_op__insn_type$next[6:0]$9247 \trap_op__insn_type + assign $1\trap_op__is_32bit$next[0:0]$9248 \trap_op__is_32bit + assign $1\trap_op__ldst_exc$next[7:0]$9249 \trap_op__ldst_exc + assign $1\trap_op__msr$next[63:0]$9250 \trap_op__msr + assign $1\trap_op__trapaddr$next[12:0]$9251 \trap_op__trapaddr + assign $1\trap_op__traptype$next[7:0]$9252 \trap_op__traptype end sync always - update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9303 - update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[13:0]$9304 - update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9305 - update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9306 - update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9307 - update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9308 - update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9309 - update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9310 - update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9311 + update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9235 + update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[13:0]$9236 + update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9237 + update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9238 + update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9239 + update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9240 + update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9241 + update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9242 + update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9243 end - attribute \src "libresoc.v:167992.3-168004.6" - process $proc$libresoc.v:167992$9321 + attribute \src "libresoc.v:168760.3-168772.6" + process $proc$libresoc.v:168760$9253 assign { } { } assign { } { } - assign $0\ra$next[63:0]$9322 $1\ra$next[63:0]$9323 - attribute \src "libresoc.v:167993.5-167993.29" + assign $0\ra$next[63:0]$9254 $1\ra$next[63:0]$9255 + attribute \src "libresoc.v:168761.5-168761.29" switch \initial - attribute \src "libresoc.v:167993.9-167993.17" + attribute \src "libresoc.v:168761.9-168761.17" case 1'1 case end @@ -346079,25 +312622,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$9323 \ra$42 + assign $1\ra$next[63:0]$9255 \ra$42 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$9323 \ra$42 + assign $1\ra$next[63:0]$9255 \ra$42 case - assign $1\ra$next[63:0]$9323 \ra + assign $1\ra$next[63:0]$9255 \ra end sync always - update \ra$next $0\ra$next[63:0]$9322 + update \ra$next $0\ra$next[63:0]$9254 end - attribute \src "libresoc.v:168005.3-168017.6" - process $proc$libresoc.v:168005$9324 + attribute \src "libresoc.v:168773.3-168785.6" + process $proc$libresoc.v:168773$9256 assign { } { } assign { } { } - assign $0\rb$next[63:0]$9325 $1\rb$next[63:0]$9326 - attribute \src "libresoc.v:168006.5-168006.29" + assign $0\rb$next[63:0]$9257 $1\rb$next[63:0]$9258 + attribute \src "libresoc.v:168774.5-168774.29" switch \initial - attribute \src "libresoc.v:168006.9-168006.17" + attribute \src "libresoc.v:168774.9-168774.17" case 1'1 case end @@ -346106,25 +312649,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$9326 \rb$43 + assign $1\rb$next[63:0]$9258 \rb$43 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$9326 \rb$43 + assign $1\rb$next[63:0]$9258 \rb$43 case - assign $1\rb$next[63:0]$9326 \rb + assign $1\rb$next[63:0]$9258 \rb end sync always - update \rb$next $0\rb$next[63:0]$9325 + update \rb$next $0\rb$next[63:0]$9257 end - attribute \src "libresoc.v:168018.3-168030.6" - process $proc$libresoc.v:168018$9327 + attribute \src "libresoc.v:168786.3-168798.6" + process $proc$libresoc.v:168786$9259 assign { } { } assign { } { } - assign $0\fast1$next[63:0]$9328 $1\fast1$next[63:0]$9329 - attribute \src "libresoc.v:168019.5-168019.29" + assign $0\fast1$next[63:0]$9260 $1\fast1$next[63:0]$9261 + attribute \src "libresoc.v:168787.5-168787.29" switch \initial - attribute \src "libresoc.v:168019.9-168019.17" + attribute \src "libresoc.v:168787.9-168787.17" case 1'1 case end @@ -346133,25 +312676,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\fast1$next[63:0]$9329 \fast1$44 + assign $1\fast1$next[63:0]$9261 \fast1$44 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\fast1$next[63:0]$9329 \fast1$44 + assign $1\fast1$next[63:0]$9261 \fast1$44 case - assign $1\fast1$next[63:0]$9329 \fast1 + assign $1\fast1$next[63:0]$9261 \fast1 end sync always - update \fast1$next $0\fast1$next[63:0]$9328 + update \fast1$next $0\fast1$next[63:0]$9260 end - attribute \src "libresoc.v:168031.3-168043.6" - process $proc$libresoc.v:168031$9330 + attribute \src "libresoc.v:168799.3-168811.6" + process $proc$libresoc.v:168799$9262 assign { } { } assign { } { } - assign $0\fast2$next[63:0]$9331 $1\fast2$next[63:0]$9332 - attribute \src "libresoc.v:168032.5-168032.29" + assign $0\fast2$next[63:0]$9263 $1\fast2$next[63:0]$9264 + attribute \src "libresoc.v:168800.5-168800.29" switch \initial - attribute \src "libresoc.v:168032.9-168032.17" + attribute \src "libresoc.v:168800.9-168800.17" case 1'1 case end @@ -346160,18 +312703,18 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\fast2$next[63:0]$9332 \fast2$45 + assign $1\fast2$next[63:0]$9264 \fast2$45 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\fast2$next[63:0]$9332 \fast2$45 + assign $1\fast2$next[63:0]$9264 \fast2$45 case - assign $1\fast2$next[63:0]$9332 \fast2 + assign $1\fast2$next[63:0]$9264 \fast2 end sync always - update \fast2$next $0\fast2$next[63:0]$9331 + update \fast2$next $0\fast2$next[63:0]$9263 end - connect \$30 $and$libresoc.v:167871$9279_Y + connect \$30 $and$libresoc.v:168639$9211_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \fast2$45 \dummy_fast2$28 @@ -346190,279 +312733,279 @@ module \pipe1$32 connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } connect \dummy_muxid \muxid$1 end -attribute \src "libresoc.v:168065.1-169250.10" +attribute \src "libresoc.v:168833.1-170018.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" attribute \generator "nMigen" module \pipe2 - attribute \src "libresoc.v:169094.3-169135.6" - wire width 4 $0\alu_op__data_len$18$next[3:0]$9417 - attribute \src "libresoc.v:168991.3-168992.57" - wire width 4 $0\alu_op__data_len$18[3:0]$9403 - attribute \src "libresoc.v:168073.13-168073.41" - wire width 4 $0\alu_op__data_len$18[3:0]$9491 - attribute \src "libresoc.v:169094.3-169135.6" - wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9418 - attribute \src "libresoc.v:168961.3-168962.53" - wire width 14 $0\alu_op__fn_unit$3[13:0]$9373 - attribute \src "libresoc.v:168112.14-168112.44" - wire width 14 $0\alu_op__fn_unit$3[13:0]$9493 - attribute \src "libresoc.v:169094.3-169135.6" - wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9419 - attribute \src "libresoc.v:168963.3-168964.67" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9375 - attribute \src "libresoc.v:168136.14-168136.63" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9495 - attribute \src "libresoc.v:169094.3-169135.6" - wire $0\alu_op__imm_data__ok$5$next[0:0]$9420 - attribute \src "libresoc.v:168965.3-168966.63" - wire $0\alu_op__imm_data__ok$5[0:0]$9377 - attribute \src "libresoc.v:168145.7-168145.38" - wire $0\alu_op__imm_data__ok$5[0:0]$9497 - attribute \src "libresoc.v:169094.3-169135.6" - wire width 2 $0\alu_op__input_carry$14$next[1:0]$9421 - attribute \src "libresoc.v:168983.3-168984.63" - wire width 2 $0\alu_op__input_carry$14[1:0]$9395 - attribute \src "libresoc.v:168162.13-168162.44" - wire width 2 $0\alu_op__input_carry$14[1:0]$9499 - attribute \src "libresoc.v:169094.3-169135.6" - wire width 32 $0\alu_op__insn$19$next[31:0]$9422 - attribute \src "libresoc.v:168993.3-168994.49" - wire width 32 $0\alu_op__insn$19[31:0]$9405 - attribute \src "libresoc.v:168175.14-168175.39" - wire width 32 $0\alu_op__insn$19[31:0]$9501 - attribute \src "libresoc.v:169094.3-169135.6" - wire width 7 $0\alu_op__insn_type$2$next[6:0]$9423 - attribute \src "libresoc.v:168959.3-168960.57" - wire width 7 $0\alu_op__insn_type$2[6:0]$9371 - attribute \src "libresoc.v:168334.13-168334.42" - wire width 7 $0\alu_op__insn_type$2[6:0]$9503 - attribute \src "libresoc.v:169094.3-169135.6" - wire $0\alu_op__invert_in$10$next[0:0]$9424 - attribute \src "libresoc.v:168975.3-168976.59" - wire $0\alu_op__invert_in$10[0:0]$9387 - attribute \src "libresoc.v:168418.7-168418.36" - wire $0\alu_op__invert_in$10[0:0]$9505 - attribute \src "libresoc.v:169094.3-169135.6" - wire $0\alu_op__invert_out$12$next[0:0]$9425 - attribute \src "libresoc.v:168979.3-168980.61" - wire $0\alu_op__invert_out$12[0:0]$9391 - attribute \src "libresoc.v:168427.7-168427.37" - wire $0\alu_op__invert_out$12[0:0]$9507 - attribute \src "libresoc.v:169094.3-169135.6" - wire $0\alu_op__is_32bit$16$next[0:0]$9426 - attribute \src "libresoc.v:168987.3-168988.57" - wire $0\alu_op__is_32bit$16[0:0]$9399 - attribute \src "libresoc.v:168436.7-168436.35" - wire $0\alu_op__is_32bit$16[0:0]$9509 - attribute \src "libresoc.v:169094.3-169135.6" - wire $0\alu_op__is_signed$17$next[0:0]$9427 - attribute \src "libresoc.v:168989.3-168990.59" - wire $0\alu_op__is_signed$17[0:0]$9401 - attribute \src "libresoc.v:168445.7-168445.36" - wire $0\alu_op__is_signed$17[0:0]$9511 - attribute \src "libresoc.v:169094.3-169135.6" - wire $0\alu_op__oe__oe$8$next[0:0]$9428 - attribute \src "libresoc.v:168971.3-168972.51" - wire $0\alu_op__oe__oe$8[0:0]$9383 - attribute \src "libresoc.v:168456.7-168456.32" - wire $0\alu_op__oe__oe$8[0:0]$9513 - attribute \src "libresoc.v:169094.3-169135.6" - wire $0\alu_op__oe__ok$9$next[0:0]$9429 - attribute \src "libresoc.v:168973.3-168974.51" - wire $0\alu_op__oe__ok$9[0:0]$9385 - attribute \src "libresoc.v:168465.7-168465.32" - wire $0\alu_op__oe__ok$9[0:0]$9515 - attribute \src "libresoc.v:169094.3-169135.6" - wire $0\alu_op__output_carry$15$next[0:0]$9430 - attribute \src "libresoc.v:168985.3-168986.65" - wire $0\alu_op__output_carry$15[0:0]$9397 - attribute \src "libresoc.v:168472.7-168472.39" - wire $0\alu_op__output_carry$15[0:0]$9517 - attribute \src "libresoc.v:169094.3-169135.6" - wire $0\alu_op__rc__ok$7$next[0:0]$9431 - attribute \src "libresoc.v:168969.3-168970.51" - wire $0\alu_op__rc__ok$7[0:0]$9381 - attribute \src "libresoc.v:168483.7-168483.32" - wire $0\alu_op__rc__ok$7[0:0]$9519 - attribute \src "libresoc.v:169094.3-169135.6" - wire $0\alu_op__rc__rc$6$next[0:0]$9432 - attribute \src "libresoc.v:168967.3-168968.51" - wire $0\alu_op__rc__rc$6[0:0]$9379 - attribute \src "libresoc.v:168490.7-168490.32" - wire $0\alu_op__rc__rc$6[0:0]$9521 - attribute \src "libresoc.v:169094.3-169135.6" - wire $0\alu_op__write_cr0$13$next[0:0]$9433 - attribute \src "libresoc.v:168981.3-168982.59" - wire $0\alu_op__write_cr0$13[0:0]$9393 - attribute \src "libresoc.v:168499.7-168499.36" - wire $0\alu_op__write_cr0$13[0:0]$9523 - attribute \src "libresoc.v:169094.3-169135.6" - wire $0\alu_op__zero_a$11$next[0:0]$9434 - attribute \src "libresoc.v:168977.3-168978.53" - wire $0\alu_op__zero_a$11[0:0]$9389 - attribute \src "libresoc.v:168508.7-168508.33" - wire $0\alu_op__zero_a$11[0:0]$9525 - attribute \src "libresoc.v:169155.3-169173.6" - wire width 4 $0\cr_a$22$next[3:0]$9466 - attribute \src "libresoc.v:168951.3-168952.33" - wire width 4 $0\cr_a$22[3:0]$9363 - attribute \src "libresoc.v:168521.13-168521.29" - wire width 4 $0\cr_a$22[3:0]$9527 - attribute \src "libresoc.v:169155.3-169173.6" - wire $0\cr_a_ok$23$next[0:0]$9467 - attribute \src "libresoc.v:168953.3-168954.39" - wire $0\cr_a_ok$23[0:0]$9365 - attribute \src "libresoc.v:168530.7-168530.26" - wire $0\cr_a_ok$23[0:0]$9529 - attribute \src "libresoc.v:168066.7-168066.20" + attribute \src "libresoc.v:169862.3-169903.6" + wire width 4 $0\alu_op__data_len$18$next[3:0]$9349 + attribute \src "libresoc.v:169759.3-169760.57" + wire width 4 $0\alu_op__data_len$18[3:0]$9335 + attribute \src "libresoc.v:168841.13-168841.41" + wire width 4 $0\alu_op__data_len$18[3:0]$9423 + attribute \src "libresoc.v:169862.3-169903.6" + wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9350 + attribute \src "libresoc.v:169729.3-169730.53" + wire width 14 $0\alu_op__fn_unit$3[13:0]$9305 + attribute \src "libresoc.v:168880.14-168880.44" + wire width 14 $0\alu_op__fn_unit$3[13:0]$9425 + attribute \src "libresoc.v:169862.3-169903.6" + wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9351 + attribute \src "libresoc.v:169731.3-169732.67" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9307 + attribute \src "libresoc.v:168904.14-168904.63" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9427 + attribute \src "libresoc.v:169862.3-169903.6" + wire $0\alu_op__imm_data__ok$5$next[0:0]$9352 + attribute \src "libresoc.v:169733.3-169734.63" + wire $0\alu_op__imm_data__ok$5[0:0]$9309 + attribute \src "libresoc.v:168913.7-168913.38" + wire $0\alu_op__imm_data__ok$5[0:0]$9429 + attribute \src "libresoc.v:169862.3-169903.6" + wire width 2 $0\alu_op__input_carry$14$next[1:0]$9353 + attribute \src "libresoc.v:169751.3-169752.63" + wire width 2 $0\alu_op__input_carry$14[1:0]$9327 + attribute \src "libresoc.v:168930.13-168930.44" + wire width 2 $0\alu_op__input_carry$14[1:0]$9431 + attribute \src "libresoc.v:169862.3-169903.6" + wire width 32 $0\alu_op__insn$19$next[31:0]$9354 + attribute \src "libresoc.v:169761.3-169762.49" + wire width 32 $0\alu_op__insn$19[31:0]$9337 + attribute \src "libresoc.v:168943.14-168943.39" + wire width 32 $0\alu_op__insn$19[31:0]$9433 + attribute \src "libresoc.v:169862.3-169903.6" + wire width 7 $0\alu_op__insn_type$2$next[6:0]$9355 + attribute \src "libresoc.v:169727.3-169728.57" + wire width 7 $0\alu_op__insn_type$2[6:0]$9303 + attribute \src "libresoc.v:169102.13-169102.42" + wire width 7 $0\alu_op__insn_type$2[6:0]$9435 + attribute \src "libresoc.v:169862.3-169903.6" + wire $0\alu_op__invert_in$10$next[0:0]$9356 + attribute \src "libresoc.v:169743.3-169744.59" + wire $0\alu_op__invert_in$10[0:0]$9319 + attribute \src "libresoc.v:169186.7-169186.36" + wire $0\alu_op__invert_in$10[0:0]$9437 + attribute \src "libresoc.v:169862.3-169903.6" + wire $0\alu_op__invert_out$12$next[0:0]$9357 + attribute \src "libresoc.v:169747.3-169748.61" + wire $0\alu_op__invert_out$12[0:0]$9323 + attribute \src "libresoc.v:169195.7-169195.37" + wire $0\alu_op__invert_out$12[0:0]$9439 + attribute \src "libresoc.v:169862.3-169903.6" + wire $0\alu_op__is_32bit$16$next[0:0]$9358 + attribute \src "libresoc.v:169755.3-169756.57" + wire $0\alu_op__is_32bit$16[0:0]$9331 + attribute \src "libresoc.v:169204.7-169204.35" + wire $0\alu_op__is_32bit$16[0:0]$9441 + attribute \src "libresoc.v:169862.3-169903.6" + wire $0\alu_op__is_signed$17$next[0:0]$9359 + attribute \src "libresoc.v:169757.3-169758.59" + wire $0\alu_op__is_signed$17[0:0]$9333 + attribute \src "libresoc.v:169213.7-169213.36" + wire $0\alu_op__is_signed$17[0:0]$9443 + attribute \src "libresoc.v:169862.3-169903.6" + wire $0\alu_op__oe__oe$8$next[0:0]$9360 + attribute \src "libresoc.v:169739.3-169740.51" + wire $0\alu_op__oe__oe$8[0:0]$9315 + attribute \src "libresoc.v:169224.7-169224.32" + wire $0\alu_op__oe__oe$8[0:0]$9445 + attribute \src "libresoc.v:169862.3-169903.6" + wire $0\alu_op__oe__ok$9$next[0:0]$9361 + attribute \src "libresoc.v:169741.3-169742.51" + wire $0\alu_op__oe__ok$9[0:0]$9317 + attribute \src "libresoc.v:169233.7-169233.32" + wire $0\alu_op__oe__ok$9[0:0]$9447 + attribute \src "libresoc.v:169862.3-169903.6" + wire $0\alu_op__output_carry$15$next[0:0]$9362 + attribute \src "libresoc.v:169753.3-169754.65" + wire $0\alu_op__output_carry$15[0:0]$9329 + attribute \src "libresoc.v:169240.7-169240.39" + wire $0\alu_op__output_carry$15[0:0]$9449 + attribute \src "libresoc.v:169862.3-169903.6" + wire $0\alu_op__rc__ok$7$next[0:0]$9363 + attribute \src "libresoc.v:169737.3-169738.51" + wire $0\alu_op__rc__ok$7[0:0]$9313 + attribute \src "libresoc.v:169251.7-169251.32" + wire $0\alu_op__rc__ok$7[0:0]$9451 + attribute \src "libresoc.v:169862.3-169903.6" + wire $0\alu_op__rc__rc$6$next[0:0]$9364 + attribute \src "libresoc.v:169735.3-169736.51" + wire $0\alu_op__rc__rc$6[0:0]$9311 + attribute \src "libresoc.v:169258.7-169258.32" + wire $0\alu_op__rc__rc$6[0:0]$9453 + attribute \src "libresoc.v:169862.3-169903.6" + wire $0\alu_op__write_cr0$13$next[0:0]$9365 + attribute \src "libresoc.v:169749.3-169750.59" + wire $0\alu_op__write_cr0$13[0:0]$9325 + attribute \src "libresoc.v:169267.7-169267.36" + wire $0\alu_op__write_cr0$13[0:0]$9455 + attribute \src "libresoc.v:169862.3-169903.6" + wire $0\alu_op__zero_a$11$next[0:0]$9366 + attribute \src "libresoc.v:169745.3-169746.53" + wire $0\alu_op__zero_a$11[0:0]$9321 + attribute \src "libresoc.v:169276.7-169276.33" + wire $0\alu_op__zero_a$11[0:0]$9457 + attribute \src "libresoc.v:169923.3-169941.6" + wire width 4 $0\cr_a$22$next[3:0]$9398 + attribute \src "libresoc.v:169719.3-169720.33" + wire width 4 $0\cr_a$22[3:0]$9295 + attribute \src "libresoc.v:169289.13-169289.29" + wire width 4 $0\cr_a$22[3:0]$9459 + attribute \src "libresoc.v:169923.3-169941.6" + wire $0\cr_a_ok$23$next[0:0]$9399 + attribute \src "libresoc.v:169721.3-169722.39" + wire $0\cr_a_ok$23[0:0]$9297 + attribute \src "libresoc.v:169298.7-169298.26" + wire $0\cr_a_ok$23[0:0]$9461 + attribute \src "libresoc.v:168834.7-168834.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169081.3-169093.6" - wire width 2 $0\muxid$1$next[1:0]$9414 - attribute \src "libresoc.v:168995.3-168996.33" - wire width 2 $0\muxid$1[1:0]$9407 - attribute \src "libresoc.v:168541.13-168541.29" - wire width 2 $0\muxid$1[1:0]$9531 - attribute \src "libresoc.v:169136.3-169154.6" - wire width 64 $0\o$20$next[63:0]$9460 - attribute \src "libresoc.v:168955.3-168956.27" - wire width 64 $0\o$20[63:0]$9367 - attribute \src "libresoc.v:168556.14-168556.43" - wire width 64 $0\o$20[63:0]$9533 - attribute \src "libresoc.v:169136.3-169154.6" - wire $0\o_ok$21$next[0:0]$9461 - attribute \src "libresoc.v:168957.3-168958.33" - wire $0\o_ok$21[0:0]$9369 - attribute \src "libresoc.v:168565.7-168565.23" - wire $0\o_ok$21[0:0]$9535 - attribute \src "libresoc.v:169063.3-169080.6" - wire $0\r_busy$next[0:0]$9410 - attribute \src "libresoc.v:168997.3-168998.29" + attribute \src "libresoc.v:169849.3-169861.6" + wire width 2 $0\muxid$1$next[1:0]$9346 + attribute \src "libresoc.v:169763.3-169764.33" + wire width 2 $0\muxid$1[1:0]$9339 + attribute \src "libresoc.v:169309.13-169309.29" + wire width 2 $0\muxid$1[1:0]$9463 + attribute \src "libresoc.v:169904.3-169922.6" + wire width 64 $0\o$20$next[63:0]$9392 + attribute \src "libresoc.v:169723.3-169724.27" + wire width 64 $0\o$20[63:0]$9299 + attribute \src "libresoc.v:169324.14-169324.43" + wire width 64 $0\o$20[63:0]$9465 + attribute \src "libresoc.v:169904.3-169922.6" + wire $0\o_ok$21$next[0:0]$9393 + attribute \src "libresoc.v:169725.3-169726.33" + wire $0\o_ok$21[0:0]$9301 + attribute \src "libresoc.v:169333.7-169333.23" + wire $0\o_ok$21[0:0]$9467 + attribute \src "libresoc.v:169831.3-169848.6" + wire $0\r_busy$next[0:0]$9342 + attribute \src "libresoc.v:169765.3-169766.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:169174.3-169192.6" - wire width 2 $0\xer_ca$24$next[1:0]$9472 - attribute \src "libresoc.v:168947.3-168948.37" - wire width 2 $0\xer_ca$24[1:0]$9359 - attribute \src "libresoc.v:168882.13-168882.31" - wire width 2 $0\xer_ca$24[1:0]$9538 - attribute \src "libresoc.v:169174.3-169192.6" - wire $0\xer_ca_ok$25$next[0:0]$9473 - attribute \src "libresoc.v:168949.3-168950.43" - wire $0\xer_ca_ok$25[0:0]$9361 - attribute \src "libresoc.v:168891.7-168891.28" - wire $0\xer_ca_ok$25[0:0]$9540 - attribute \src "libresoc.v:169193.3-169211.6" - wire width 2 $0\xer_ov$26$next[1:0]$9478 - attribute \src "libresoc.v:168943.3-168944.37" - wire width 2 $0\xer_ov$26[1:0]$9355 - attribute \src "libresoc.v:168902.13-168902.31" - wire width 2 $0\xer_ov$26[1:0]$9542 - attribute \src "libresoc.v:169193.3-169211.6" - wire $0\xer_ov_ok$27$next[0:0]$9479 - attribute \src "libresoc.v:168945.3-168946.43" - wire $0\xer_ov_ok$27[0:0]$9357 - attribute \src "libresoc.v:168911.7-168911.28" - wire $0\xer_ov_ok$27[0:0]$9544 - attribute \src "libresoc.v:169212.3-169230.6" - wire $0\xer_so$28$next[0:0]$9484 - attribute \src "libresoc.v:168939.3-168940.37" - wire $0\xer_so$28[0:0]$9351 - attribute \src "libresoc.v:168922.7-168922.25" - wire $0\xer_so$28[0:0]$9546 - attribute \src "libresoc.v:169212.3-169230.6" - wire $0\xer_so_ok$29$next[0:0]$9485 - attribute \src "libresoc.v:168941.3-168942.43" - wire $0\xer_so_ok$29[0:0]$9353 - attribute \src "libresoc.v:168931.7-168931.28" - wire $0\xer_so_ok$29[0:0]$9548 - attribute \src "libresoc.v:169094.3-169135.6" - wire width 4 $1\alu_op__data_len$18$next[3:0]$9435 - attribute \src "libresoc.v:169094.3-169135.6" - wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9436 - attribute \src "libresoc.v:169094.3-169135.6" - wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9437 - attribute \src "libresoc.v:169094.3-169135.6" - wire $1\alu_op__imm_data__ok$5$next[0:0]$9438 - attribute \src "libresoc.v:169094.3-169135.6" - wire width 2 $1\alu_op__input_carry$14$next[1:0]$9439 - attribute \src "libresoc.v:169094.3-169135.6" - wire width 32 $1\alu_op__insn$19$next[31:0]$9440 - attribute \src "libresoc.v:169094.3-169135.6" - wire width 7 $1\alu_op__insn_type$2$next[6:0]$9441 - attribute \src "libresoc.v:169094.3-169135.6" - wire $1\alu_op__invert_in$10$next[0:0]$9442 - attribute \src "libresoc.v:169094.3-169135.6" - wire $1\alu_op__invert_out$12$next[0:0]$9443 - attribute \src "libresoc.v:169094.3-169135.6" - wire $1\alu_op__is_32bit$16$next[0:0]$9444 - attribute \src "libresoc.v:169094.3-169135.6" - wire $1\alu_op__is_signed$17$next[0:0]$9445 - attribute \src "libresoc.v:169094.3-169135.6" - wire $1\alu_op__oe__oe$8$next[0:0]$9446 - attribute \src "libresoc.v:169094.3-169135.6" - wire $1\alu_op__oe__ok$9$next[0:0]$9447 - attribute \src "libresoc.v:169094.3-169135.6" - wire $1\alu_op__output_carry$15$next[0:0]$9448 - attribute \src "libresoc.v:169094.3-169135.6" - wire $1\alu_op__rc__ok$7$next[0:0]$9449 - attribute \src "libresoc.v:169094.3-169135.6" - wire $1\alu_op__rc__rc$6$next[0:0]$9450 - attribute \src "libresoc.v:169094.3-169135.6" - wire $1\alu_op__write_cr0$13$next[0:0]$9451 - attribute \src "libresoc.v:169094.3-169135.6" - wire $1\alu_op__zero_a$11$next[0:0]$9452 - attribute \src "libresoc.v:169155.3-169173.6" - wire width 4 $1\cr_a$22$next[3:0]$9468 - attribute \src "libresoc.v:169155.3-169173.6" - wire $1\cr_a_ok$23$next[0:0]$9469 - attribute \src "libresoc.v:169081.3-169093.6" - wire width 2 $1\muxid$1$next[1:0]$9415 - attribute \src "libresoc.v:169136.3-169154.6" - wire width 64 $1\o$20$next[63:0]$9462 - attribute \src "libresoc.v:169136.3-169154.6" - wire $1\o_ok$21$next[0:0]$9463 - attribute \src "libresoc.v:169063.3-169080.6" - wire $1\r_busy$next[0:0]$9411 - attribute \src "libresoc.v:168875.7-168875.20" + attribute \src "libresoc.v:169942.3-169960.6" + wire width 2 $0\xer_ca$24$next[1:0]$9404 + attribute \src "libresoc.v:169715.3-169716.37" + wire width 2 $0\xer_ca$24[1:0]$9291 + attribute \src "libresoc.v:169650.13-169650.31" + wire width 2 $0\xer_ca$24[1:0]$9470 + attribute \src "libresoc.v:169942.3-169960.6" + wire $0\xer_ca_ok$25$next[0:0]$9405 + attribute \src "libresoc.v:169717.3-169718.43" + wire $0\xer_ca_ok$25[0:0]$9293 + attribute \src "libresoc.v:169659.7-169659.28" + wire $0\xer_ca_ok$25[0:0]$9472 + attribute \src "libresoc.v:169961.3-169979.6" + wire width 2 $0\xer_ov$26$next[1:0]$9410 + attribute \src "libresoc.v:169711.3-169712.37" + wire width 2 $0\xer_ov$26[1:0]$9287 + attribute \src "libresoc.v:169670.13-169670.31" + wire width 2 $0\xer_ov$26[1:0]$9474 + attribute \src "libresoc.v:169961.3-169979.6" + wire $0\xer_ov_ok$27$next[0:0]$9411 + attribute \src "libresoc.v:169713.3-169714.43" + wire $0\xer_ov_ok$27[0:0]$9289 + attribute \src "libresoc.v:169679.7-169679.28" + wire $0\xer_ov_ok$27[0:0]$9476 + attribute \src "libresoc.v:169980.3-169998.6" + wire $0\xer_so$28$next[0:0]$9416 + attribute \src "libresoc.v:169707.3-169708.37" + wire $0\xer_so$28[0:0]$9283 + attribute \src "libresoc.v:169690.7-169690.25" + wire $0\xer_so$28[0:0]$9478 + attribute \src "libresoc.v:169980.3-169998.6" + wire $0\xer_so_ok$29$next[0:0]$9417 + attribute \src "libresoc.v:169709.3-169710.43" + wire $0\xer_so_ok$29[0:0]$9285 + attribute \src "libresoc.v:169699.7-169699.28" + wire $0\xer_so_ok$29[0:0]$9480 + attribute \src "libresoc.v:169862.3-169903.6" + wire width 4 $1\alu_op__data_len$18$next[3:0]$9367 + attribute \src "libresoc.v:169862.3-169903.6" + wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9368 + attribute \src "libresoc.v:169862.3-169903.6" + wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9369 + attribute \src "libresoc.v:169862.3-169903.6" + wire $1\alu_op__imm_data__ok$5$next[0:0]$9370 + attribute \src "libresoc.v:169862.3-169903.6" + wire width 2 $1\alu_op__input_carry$14$next[1:0]$9371 + attribute \src "libresoc.v:169862.3-169903.6" + wire width 32 $1\alu_op__insn$19$next[31:0]$9372 + attribute \src "libresoc.v:169862.3-169903.6" + wire width 7 $1\alu_op__insn_type$2$next[6:0]$9373 + attribute \src "libresoc.v:169862.3-169903.6" + wire $1\alu_op__invert_in$10$next[0:0]$9374 + attribute \src "libresoc.v:169862.3-169903.6" + wire $1\alu_op__invert_out$12$next[0:0]$9375 + attribute \src "libresoc.v:169862.3-169903.6" + wire $1\alu_op__is_32bit$16$next[0:0]$9376 + attribute \src "libresoc.v:169862.3-169903.6" + wire $1\alu_op__is_signed$17$next[0:0]$9377 + attribute \src "libresoc.v:169862.3-169903.6" + wire $1\alu_op__oe__oe$8$next[0:0]$9378 + attribute \src "libresoc.v:169862.3-169903.6" + wire $1\alu_op__oe__ok$9$next[0:0]$9379 + attribute \src "libresoc.v:169862.3-169903.6" + wire $1\alu_op__output_carry$15$next[0:0]$9380 + attribute \src "libresoc.v:169862.3-169903.6" + wire $1\alu_op__rc__ok$7$next[0:0]$9381 + attribute \src "libresoc.v:169862.3-169903.6" + wire $1\alu_op__rc__rc$6$next[0:0]$9382 + attribute \src "libresoc.v:169862.3-169903.6" + wire $1\alu_op__write_cr0$13$next[0:0]$9383 + attribute \src "libresoc.v:169862.3-169903.6" + wire $1\alu_op__zero_a$11$next[0:0]$9384 + attribute \src "libresoc.v:169923.3-169941.6" + wire width 4 $1\cr_a$22$next[3:0]$9400 + attribute \src "libresoc.v:169923.3-169941.6" + wire $1\cr_a_ok$23$next[0:0]$9401 + attribute \src "libresoc.v:169849.3-169861.6" + wire width 2 $1\muxid$1$next[1:0]$9347 + attribute \src "libresoc.v:169904.3-169922.6" + wire width 64 $1\o$20$next[63:0]$9394 + attribute \src "libresoc.v:169904.3-169922.6" + wire $1\o_ok$21$next[0:0]$9395 + attribute \src "libresoc.v:169831.3-169848.6" + wire $1\r_busy$next[0:0]$9343 + attribute \src "libresoc.v:169643.7-169643.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:169174.3-169192.6" - wire width 2 $1\xer_ca$24$next[1:0]$9474 - attribute \src "libresoc.v:169174.3-169192.6" - wire $1\xer_ca_ok$25$next[0:0]$9475 - attribute \src "libresoc.v:169193.3-169211.6" - wire width 2 $1\xer_ov$26$next[1:0]$9480 - attribute \src "libresoc.v:169193.3-169211.6" - wire $1\xer_ov_ok$27$next[0:0]$9481 - attribute \src "libresoc.v:169212.3-169230.6" - wire $1\xer_so$28$next[0:0]$9486 - attribute \src "libresoc.v:169212.3-169230.6" - wire $1\xer_so_ok$29$next[0:0]$9487 - attribute \src "libresoc.v:169094.3-169135.6" - wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9453 - attribute \src "libresoc.v:169094.3-169135.6" - wire $2\alu_op__imm_data__ok$5$next[0:0]$9454 - attribute \src "libresoc.v:169094.3-169135.6" - wire $2\alu_op__oe__oe$8$next[0:0]$9455 - attribute \src "libresoc.v:169094.3-169135.6" - wire $2\alu_op__oe__ok$9$next[0:0]$9456 - attribute \src "libresoc.v:169094.3-169135.6" - wire $2\alu_op__rc__ok$7$next[0:0]$9457 - attribute \src "libresoc.v:169094.3-169135.6" - wire $2\alu_op__rc__rc$6$next[0:0]$9458 - attribute \src "libresoc.v:169155.3-169173.6" - wire $2\cr_a_ok$23$next[0:0]$9470 - attribute \src "libresoc.v:169136.3-169154.6" - wire $2\o_ok$21$next[0:0]$9464 - attribute \src "libresoc.v:169063.3-169080.6" - wire $2\r_busy$next[0:0]$9412 - attribute \src "libresoc.v:169174.3-169192.6" - wire $2\xer_ca_ok$25$next[0:0]$9476 - attribute \src "libresoc.v:169193.3-169211.6" - wire $2\xer_ov_ok$27$next[0:0]$9482 - attribute \src "libresoc.v:169212.3-169230.6" - wire $2\xer_so_ok$29$next[0:0]$9488 - attribute \src "libresoc.v:168938.18-168938.118" - wire $and$libresoc.v:168938$9349_Y + attribute \src "libresoc.v:169942.3-169960.6" + wire width 2 $1\xer_ca$24$next[1:0]$9406 + attribute \src "libresoc.v:169942.3-169960.6" + wire $1\xer_ca_ok$25$next[0:0]$9407 + attribute \src "libresoc.v:169961.3-169979.6" + wire width 2 $1\xer_ov$26$next[1:0]$9412 + attribute \src "libresoc.v:169961.3-169979.6" + wire $1\xer_ov_ok$27$next[0:0]$9413 + attribute \src "libresoc.v:169980.3-169998.6" + wire $1\xer_so$28$next[0:0]$9418 + attribute \src "libresoc.v:169980.3-169998.6" + wire $1\xer_so_ok$29$next[0:0]$9419 + attribute \src "libresoc.v:169862.3-169903.6" + wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9385 + attribute \src "libresoc.v:169862.3-169903.6" + wire $2\alu_op__imm_data__ok$5$next[0:0]$9386 + attribute \src "libresoc.v:169862.3-169903.6" + wire $2\alu_op__oe__oe$8$next[0:0]$9387 + attribute \src "libresoc.v:169862.3-169903.6" + wire $2\alu_op__oe__ok$9$next[0:0]$9388 + attribute \src "libresoc.v:169862.3-169903.6" + wire $2\alu_op__rc__ok$7$next[0:0]$9389 + attribute \src "libresoc.v:169862.3-169903.6" + wire $2\alu_op__rc__rc$6$next[0:0]$9390 + attribute \src "libresoc.v:169923.3-169941.6" + wire $2\cr_a_ok$23$next[0:0]$9402 + attribute \src "libresoc.v:169904.3-169922.6" + wire $2\o_ok$21$next[0:0]$9396 + attribute \src "libresoc.v:169831.3-169848.6" + wire $2\r_busy$next[0:0]$9344 + attribute \src "libresoc.v:169942.3-169960.6" + wire $2\xer_ca_ok$25$next[0:0]$9408 + attribute \src "libresoc.v:169961.3-169979.6" + wire $2\xer_ov_ok$27$next[0:0]$9414 + attribute \src "libresoc.v:169980.3-169998.6" + wire $2\xer_so_ok$29$next[0:0]$9420 + attribute \src "libresoc.v:169706.18-169706.118" + wire $and$libresoc.v:169706$9281_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -346891,29 +313434,29 @@ module \pipe2 wire \alu_op__zero_a$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 64 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 56 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 57 \cr_a_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$84 - attribute \src "libresoc.v:168066.7-168066.15" + attribute \src "libresoc.v:168834.7-168834.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -346929,21 +313472,21 @@ module \pipe2 wire input 34 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 33 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 54 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 55 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_alu_op__data_len @@ -347205,41 +313748,41 @@ module \pipe2 wire \output_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__zero_a$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ca$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ov$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o @@ -347253,62 +313796,62 @@ module \pipe2 wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 27 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 58 \xer_ca$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 59 \xer_ca_ok$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 29 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 60 \xer_ov$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 30 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 61 \xer_ov_ok$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$27$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 31 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 62 \xer_so$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$28$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 32 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 63 \xer_so_ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$29$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:168938$9349 + cell $and $and$libresoc.v:169706$9281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347316,16 +313859,16 @@ module \pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$59 connect \B \p_ready_o - connect \Y $and$libresoc.v:168938$9349_Y + connect \Y $and$libresoc.v:169706$9281_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:168999.9-169002.4" + attribute \src "libresoc.v:169767.9-169770.4" cell \n$4 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:169003.12-169058.4" + attribute \src "libresoc.v:169771.12-169826.4" cell \output \output connect \alu_op__data_len \output_alu_op__data_len connect \alu_op__data_len$18 \output_alu_op__data_len$47 @@ -347383,478 +313926,478 @@ module \pipe2 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:169059.9-169062.4" + attribute \src "libresoc.v:169827.9-169830.4" cell \p$3 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:168066.7-168066.20" - process $proc$libresoc.v:168066$9489 + attribute \src "libresoc.v:168834.7-168834.20" + process $proc$libresoc.v:168834$9421 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:168073.13-168073.41" - process $proc$libresoc.v:168073$9490 + attribute \src "libresoc.v:168841.13-168841.41" + process $proc$libresoc.v:168841$9422 assign { } { } - assign $0\alu_op__data_len$18[3:0]$9491 4'0000 + assign $0\alu_op__data_len$18[3:0]$9423 4'0000 sync always sync init - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9491 + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9423 end - attribute \src "libresoc.v:168112.14-168112.44" - process $proc$libresoc.v:168112$9492 + attribute \src "libresoc.v:168880.14-168880.44" + process $proc$libresoc.v:168880$9424 assign { } { } - assign $0\alu_op__fn_unit$3[13:0]$9493 14'00000000000000 + assign $0\alu_op__fn_unit$3[13:0]$9425 14'00000000000000 sync always sync init - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9493 + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9425 end - attribute \src "libresoc.v:168136.14-168136.63" - process $proc$libresoc.v:168136$9494 + attribute \src "libresoc.v:168904.14-168904.63" + process $proc$libresoc.v:168904$9426 assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9495 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__imm_data__data$4[63:0]$9427 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9495 + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9427 end - attribute \src "libresoc.v:168145.7-168145.38" - process $proc$libresoc.v:168145$9496 + attribute \src "libresoc.v:168913.7-168913.38" + process $proc$libresoc.v:168913$9428 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9497 1'0 + assign $0\alu_op__imm_data__ok$5[0:0]$9429 1'0 sync always sync init - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9497 + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9429 end - attribute \src "libresoc.v:168162.13-168162.44" - process $proc$libresoc.v:168162$9498 + attribute \src "libresoc.v:168930.13-168930.44" + process $proc$libresoc.v:168930$9430 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9499 2'00 + assign $0\alu_op__input_carry$14[1:0]$9431 2'00 sync always sync init - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9499 + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9431 end - attribute \src "libresoc.v:168175.14-168175.39" - process $proc$libresoc.v:168175$9500 + attribute \src "libresoc.v:168943.14-168943.39" + process $proc$libresoc.v:168943$9432 assign { } { } - assign $0\alu_op__insn$19[31:0]$9501 0 + assign $0\alu_op__insn$19[31:0]$9433 0 sync always sync init - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9501 + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9433 end - attribute \src "libresoc.v:168334.13-168334.42" - process $proc$libresoc.v:168334$9502 + attribute \src "libresoc.v:169102.13-169102.42" + process $proc$libresoc.v:169102$9434 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9503 7'0000000 + assign $0\alu_op__insn_type$2[6:0]$9435 7'0000000 sync always sync init - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9503 + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9435 end - attribute \src "libresoc.v:168418.7-168418.36" - process $proc$libresoc.v:168418$9504 + attribute \src "libresoc.v:169186.7-169186.36" + process $proc$libresoc.v:169186$9436 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9505 1'0 + assign $0\alu_op__invert_in$10[0:0]$9437 1'0 sync always sync init - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9505 + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9437 end - attribute \src "libresoc.v:168427.7-168427.37" - process $proc$libresoc.v:168427$9506 + attribute \src "libresoc.v:169195.7-169195.37" + process $proc$libresoc.v:169195$9438 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9507 1'0 + assign $0\alu_op__invert_out$12[0:0]$9439 1'0 sync always sync init - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9507 + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9439 end - attribute \src "libresoc.v:168436.7-168436.35" - process $proc$libresoc.v:168436$9508 + attribute \src "libresoc.v:169204.7-169204.35" + process $proc$libresoc.v:169204$9440 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9509 1'0 + assign $0\alu_op__is_32bit$16[0:0]$9441 1'0 sync always sync init - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9509 + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9441 end - attribute \src "libresoc.v:168445.7-168445.36" - process $proc$libresoc.v:168445$9510 + attribute \src "libresoc.v:169213.7-169213.36" + process $proc$libresoc.v:169213$9442 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9511 1'0 + assign $0\alu_op__is_signed$17[0:0]$9443 1'0 sync always sync init - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9511 + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9443 end - attribute \src "libresoc.v:168456.7-168456.32" - process $proc$libresoc.v:168456$9512 + attribute \src "libresoc.v:169224.7-169224.32" + process $proc$libresoc.v:169224$9444 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9513 1'0 + assign $0\alu_op__oe__oe$8[0:0]$9445 1'0 sync always sync init - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9513 + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9445 end - attribute \src "libresoc.v:168465.7-168465.32" - process $proc$libresoc.v:168465$9514 + attribute \src "libresoc.v:169233.7-169233.32" + process $proc$libresoc.v:169233$9446 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9515 1'0 + assign $0\alu_op__oe__ok$9[0:0]$9447 1'0 sync always sync init - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9515 + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9447 end - attribute \src "libresoc.v:168472.7-168472.39" - process $proc$libresoc.v:168472$9516 + attribute \src "libresoc.v:169240.7-169240.39" + process $proc$libresoc.v:169240$9448 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9517 1'0 + assign $0\alu_op__output_carry$15[0:0]$9449 1'0 sync always sync init - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9517 + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9449 end - attribute \src "libresoc.v:168483.7-168483.32" - process $proc$libresoc.v:168483$9518 + attribute \src "libresoc.v:169251.7-169251.32" + process $proc$libresoc.v:169251$9450 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9519 1'0 + assign $0\alu_op__rc__ok$7[0:0]$9451 1'0 sync always sync init - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9519 + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9451 end - attribute \src "libresoc.v:168490.7-168490.32" - process $proc$libresoc.v:168490$9520 + attribute \src "libresoc.v:169258.7-169258.32" + process $proc$libresoc.v:169258$9452 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9521 1'0 + assign $0\alu_op__rc__rc$6[0:0]$9453 1'0 sync always sync init - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9521 + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9453 end - attribute \src "libresoc.v:168499.7-168499.36" - process $proc$libresoc.v:168499$9522 + attribute \src "libresoc.v:169267.7-169267.36" + process $proc$libresoc.v:169267$9454 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9523 1'0 + assign $0\alu_op__write_cr0$13[0:0]$9455 1'0 sync always sync init - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9523 + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9455 end - attribute \src "libresoc.v:168508.7-168508.33" - process $proc$libresoc.v:168508$9524 + attribute \src "libresoc.v:169276.7-169276.33" + process $proc$libresoc.v:169276$9456 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9525 1'0 + assign $0\alu_op__zero_a$11[0:0]$9457 1'0 sync always sync init - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9525 + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9457 end - attribute \src "libresoc.v:168521.13-168521.29" - process $proc$libresoc.v:168521$9526 + attribute \src "libresoc.v:169289.13-169289.29" + process $proc$libresoc.v:169289$9458 assign { } { } - assign $0\cr_a$22[3:0]$9527 4'0000 + assign $0\cr_a$22[3:0]$9459 4'0000 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$9527 + update \cr_a$22 $0\cr_a$22[3:0]$9459 end - attribute \src "libresoc.v:168530.7-168530.26" - process $proc$libresoc.v:168530$9528 + attribute \src "libresoc.v:169298.7-169298.26" + process $proc$libresoc.v:169298$9460 assign { } { } - assign $0\cr_a_ok$23[0:0]$9529 1'0 + assign $0\cr_a_ok$23[0:0]$9461 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9529 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9461 end - attribute \src "libresoc.v:168541.13-168541.29" - process $proc$libresoc.v:168541$9530 + attribute \src "libresoc.v:169309.13-169309.29" + process $proc$libresoc.v:169309$9462 assign { } { } - assign $0\muxid$1[1:0]$9531 2'00 + assign $0\muxid$1[1:0]$9463 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9531 + update \muxid$1 $0\muxid$1[1:0]$9463 end - attribute \src "libresoc.v:168556.14-168556.43" - process $proc$libresoc.v:168556$9532 + attribute \src "libresoc.v:169324.14-169324.43" + process $proc$libresoc.v:169324$9464 assign { } { } - assign $0\o$20[63:0]$9533 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$20[63:0]$9465 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$20 $0\o$20[63:0]$9533 + update \o$20 $0\o$20[63:0]$9465 end - attribute \src "libresoc.v:168565.7-168565.23" - process $proc$libresoc.v:168565$9534 + attribute \src "libresoc.v:169333.7-169333.23" + process $proc$libresoc.v:169333$9466 assign { } { } - assign $0\o_ok$21[0:0]$9535 1'0 + assign $0\o_ok$21[0:0]$9467 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$9535 + update \o_ok$21 $0\o_ok$21[0:0]$9467 end - attribute \src "libresoc.v:168875.7-168875.20" - process $proc$libresoc.v:168875$9536 + attribute \src "libresoc.v:169643.7-169643.20" + process $proc$libresoc.v:169643$9468 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:168882.13-168882.31" - process $proc$libresoc.v:168882$9537 + attribute \src "libresoc.v:169650.13-169650.31" + process $proc$libresoc.v:169650$9469 assign { } { } - assign $0\xer_ca$24[1:0]$9538 2'00 + assign $0\xer_ca$24[1:0]$9470 2'00 sync always sync init - update \xer_ca$24 $0\xer_ca$24[1:0]$9538 + update \xer_ca$24 $0\xer_ca$24[1:0]$9470 end - attribute \src "libresoc.v:168891.7-168891.28" - process $proc$libresoc.v:168891$9539 + attribute \src "libresoc.v:169659.7-169659.28" + process $proc$libresoc.v:169659$9471 assign { } { } - assign $0\xer_ca_ok$25[0:0]$9540 1'0 + assign $0\xer_ca_ok$25[0:0]$9472 1'0 sync always sync init - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9540 + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9472 end - attribute \src "libresoc.v:168902.13-168902.31" - process $proc$libresoc.v:168902$9541 + attribute \src "libresoc.v:169670.13-169670.31" + process $proc$libresoc.v:169670$9473 assign { } { } - assign $0\xer_ov$26[1:0]$9542 2'00 + assign $0\xer_ov$26[1:0]$9474 2'00 sync always sync init - update \xer_ov$26 $0\xer_ov$26[1:0]$9542 + update \xer_ov$26 $0\xer_ov$26[1:0]$9474 end - attribute \src "libresoc.v:168911.7-168911.28" - process $proc$libresoc.v:168911$9543 + attribute \src "libresoc.v:169679.7-169679.28" + process $proc$libresoc.v:169679$9475 assign { } { } - assign $0\xer_ov_ok$27[0:0]$9544 1'0 + assign $0\xer_ov_ok$27[0:0]$9476 1'0 sync always sync init - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9544 + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9476 end - attribute \src "libresoc.v:168922.7-168922.25" - process $proc$libresoc.v:168922$9545 + attribute \src "libresoc.v:169690.7-169690.25" + process $proc$libresoc.v:169690$9477 assign { } { } - assign $0\xer_so$28[0:0]$9546 1'0 + assign $0\xer_so$28[0:0]$9478 1'0 sync always sync init - update \xer_so$28 $0\xer_so$28[0:0]$9546 + update \xer_so$28 $0\xer_so$28[0:0]$9478 end - attribute \src "libresoc.v:168931.7-168931.28" - process $proc$libresoc.v:168931$9547 + attribute \src "libresoc.v:169699.7-169699.28" + process $proc$libresoc.v:169699$9479 assign { } { } - assign $0\xer_so_ok$29[0:0]$9548 1'0 + assign $0\xer_so_ok$29[0:0]$9480 1'0 sync always sync init - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9548 + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9480 end - attribute \src "libresoc.v:168939.3-168940.37" - process $proc$libresoc.v:168939$9350 + attribute \src "libresoc.v:169707.3-169708.37" + process $proc$libresoc.v:169707$9282 assign { } { } - assign $0\xer_so$28[0:0]$9351 \xer_so$28$next + assign $0\xer_so$28[0:0]$9283 \xer_so$28$next sync posedge \coresync_clk - update \xer_so$28 $0\xer_so$28[0:0]$9351 + update \xer_so$28 $0\xer_so$28[0:0]$9283 end - attribute \src "libresoc.v:168941.3-168942.43" - process $proc$libresoc.v:168941$9352 + attribute \src "libresoc.v:169709.3-169710.43" + process $proc$libresoc.v:169709$9284 assign { } { } - assign $0\xer_so_ok$29[0:0]$9353 \xer_so_ok$29$next + assign $0\xer_so_ok$29[0:0]$9285 \xer_so_ok$29$next sync posedge \coresync_clk - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9353 + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9285 end - attribute \src "libresoc.v:168943.3-168944.37" - process $proc$libresoc.v:168943$9354 + attribute \src "libresoc.v:169711.3-169712.37" + process $proc$libresoc.v:169711$9286 assign { } { } - assign $0\xer_ov$26[1:0]$9355 \xer_ov$26$next + assign $0\xer_ov$26[1:0]$9287 \xer_ov$26$next sync posedge \coresync_clk - update \xer_ov$26 $0\xer_ov$26[1:0]$9355 + update \xer_ov$26 $0\xer_ov$26[1:0]$9287 end - attribute \src "libresoc.v:168945.3-168946.43" - process $proc$libresoc.v:168945$9356 + attribute \src "libresoc.v:169713.3-169714.43" + process $proc$libresoc.v:169713$9288 assign { } { } - assign $0\xer_ov_ok$27[0:0]$9357 \xer_ov_ok$27$next + assign $0\xer_ov_ok$27[0:0]$9289 \xer_ov_ok$27$next sync posedge \coresync_clk - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9357 + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9289 end - attribute \src "libresoc.v:168947.3-168948.37" - process $proc$libresoc.v:168947$9358 + attribute \src "libresoc.v:169715.3-169716.37" + process $proc$libresoc.v:169715$9290 assign { } { } - assign $0\xer_ca$24[1:0]$9359 \xer_ca$24$next + assign $0\xer_ca$24[1:0]$9291 \xer_ca$24$next sync posedge \coresync_clk - update \xer_ca$24 $0\xer_ca$24[1:0]$9359 + update \xer_ca$24 $0\xer_ca$24[1:0]$9291 end - attribute \src "libresoc.v:168949.3-168950.43" - process $proc$libresoc.v:168949$9360 + attribute \src "libresoc.v:169717.3-169718.43" + process $proc$libresoc.v:169717$9292 assign { } { } - assign $0\xer_ca_ok$25[0:0]$9361 \xer_ca_ok$25$next + assign $0\xer_ca_ok$25[0:0]$9293 \xer_ca_ok$25$next sync posedge \coresync_clk - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9361 + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9293 end - attribute \src "libresoc.v:168951.3-168952.33" - process $proc$libresoc.v:168951$9362 + attribute \src "libresoc.v:169719.3-169720.33" + process $proc$libresoc.v:169719$9294 assign { } { } - assign $0\cr_a$22[3:0]$9363 \cr_a$22$next + assign $0\cr_a$22[3:0]$9295 \cr_a$22$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$9363 + update \cr_a$22 $0\cr_a$22[3:0]$9295 end - attribute \src "libresoc.v:168953.3-168954.39" - process $proc$libresoc.v:168953$9364 + attribute \src "libresoc.v:169721.3-169722.39" + process $proc$libresoc.v:169721$9296 assign { } { } - assign $0\cr_a_ok$23[0:0]$9365 \cr_a_ok$23$next + assign $0\cr_a_ok$23[0:0]$9297 \cr_a_ok$23$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9365 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9297 end - attribute \src "libresoc.v:168955.3-168956.27" - process $proc$libresoc.v:168955$9366 + attribute \src "libresoc.v:169723.3-169724.27" + process $proc$libresoc.v:169723$9298 assign { } { } - assign $0\o$20[63:0]$9367 \o$20$next + assign $0\o$20[63:0]$9299 \o$20$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$9367 + update \o$20 $0\o$20[63:0]$9299 end - attribute \src "libresoc.v:168957.3-168958.33" - process $proc$libresoc.v:168957$9368 + attribute \src "libresoc.v:169725.3-169726.33" + process $proc$libresoc.v:169725$9300 assign { } { } - assign $0\o_ok$21[0:0]$9369 \o_ok$21$next + assign $0\o_ok$21[0:0]$9301 \o_ok$21$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$9369 + update \o_ok$21 $0\o_ok$21[0:0]$9301 end - attribute \src "libresoc.v:168959.3-168960.57" - process $proc$libresoc.v:168959$9370 + attribute \src "libresoc.v:169727.3-169728.57" + process $proc$libresoc.v:169727$9302 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9371 \alu_op__insn_type$2$next + assign $0\alu_op__insn_type$2[6:0]$9303 \alu_op__insn_type$2$next sync posedge \coresync_clk - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9371 + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9303 end - attribute \src "libresoc.v:168961.3-168962.53" - process $proc$libresoc.v:168961$9372 + attribute \src "libresoc.v:169729.3-169730.53" + process $proc$libresoc.v:169729$9304 assign { } { } - assign $0\alu_op__fn_unit$3[13:0]$9373 \alu_op__fn_unit$3$next + assign $0\alu_op__fn_unit$3[13:0]$9305 \alu_op__fn_unit$3$next sync posedge \coresync_clk - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9373 + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9305 end - attribute \src "libresoc.v:168963.3-168964.67" - process $proc$libresoc.v:168963$9374 + attribute \src "libresoc.v:169731.3-169732.67" + process $proc$libresoc.v:169731$9306 assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9375 \alu_op__imm_data__data$4$next + assign $0\alu_op__imm_data__data$4[63:0]$9307 \alu_op__imm_data__data$4$next sync posedge \coresync_clk - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9375 + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9307 end - attribute \src "libresoc.v:168965.3-168966.63" - process $proc$libresoc.v:168965$9376 + attribute \src "libresoc.v:169733.3-169734.63" + process $proc$libresoc.v:169733$9308 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9377 \alu_op__imm_data__ok$5$next + assign $0\alu_op__imm_data__ok$5[0:0]$9309 \alu_op__imm_data__ok$5$next sync posedge \coresync_clk - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9377 + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9309 end - attribute \src "libresoc.v:168967.3-168968.51" - process $proc$libresoc.v:168967$9378 + attribute \src "libresoc.v:169735.3-169736.51" + process $proc$libresoc.v:169735$9310 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9379 \alu_op__rc__rc$6$next + assign $0\alu_op__rc__rc$6[0:0]$9311 \alu_op__rc__rc$6$next sync posedge \coresync_clk - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9379 + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9311 end - attribute \src "libresoc.v:168969.3-168970.51" - process $proc$libresoc.v:168969$9380 + attribute \src "libresoc.v:169737.3-169738.51" + process $proc$libresoc.v:169737$9312 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9381 \alu_op__rc__ok$7$next + assign $0\alu_op__rc__ok$7[0:0]$9313 \alu_op__rc__ok$7$next sync posedge \coresync_clk - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9381 + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9313 end - attribute \src "libresoc.v:168971.3-168972.51" - process $proc$libresoc.v:168971$9382 + attribute \src "libresoc.v:169739.3-169740.51" + process $proc$libresoc.v:169739$9314 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9383 \alu_op__oe__oe$8$next + assign $0\alu_op__oe__oe$8[0:0]$9315 \alu_op__oe__oe$8$next sync posedge \coresync_clk - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9383 + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9315 end - attribute \src "libresoc.v:168973.3-168974.51" - process $proc$libresoc.v:168973$9384 + attribute \src "libresoc.v:169741.3-169742.51" + process $proc$libresoc.v:169741$9316 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9385 \alu_op__oe__ok$9$next + assign $0\alu_op__oe__ok$9[0:0]$9317 \alu_op__oe__ok$9$next sync posedge \coresync_clk - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9385 + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9317 end - attribute \src "libresoc.v:168975.3-168976.59" - process $proc$libresoc.v:168975$9386 + attribute \src "libresoc.v:169743.3-169744.59" + process $proc$libresoc.v:169743$9318 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9387 \alu_op__invert_in$10$next + assign $0\alu_op__invert_in$10[0:0]$9319 \alu_op__invert_in$10$next sync posedge \coresync_clk - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9387 + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9319 end - attribute \src "libresoc.v:168977.3-168978.53" - process $proc$libresoc.v:168977$9388 + attribute \src "libresoc.v:169745.3-169746.53" + process $proc$libresoc.v:169745$9320 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9389 \alu_op__zero_a$11$next + assign $0\alu_op__zero_a$11[0:0]$9321 \alu_op__zero_a$11$next sync posedge \coresync_clk - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9389 + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9321 end - attribute \src "libresoc.v:168979.3-168980.61" - process $proc$libresoc.v:168979$9390 + attribute \src "libresoc.v:169747.3-169748.61" + process $proc$libresoc.v:169747$9322 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9391 \alu_op__invert_out$12$next + assign $0\alu_op__invert_out$12[0:0]$9323 \alu_op__invert_out$12$next sync posedge \coresync_clk - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9391 + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9323 end - attribute \src "libresoc.v:168981.3-168982.59" - process $proc$libresoc.v:168981$9392 + attribute \src "libresoc.v:169749.3-169750.59" + process $proc$libresoc.v:169749$9324 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9393 \alu_op__write_cr0$13$next + assign $0\alu_op__write_cr0$13[0:0]$9325 \alu_op__write_cr0$13$next sync posedge \coresync_clk - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9393 + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9325 end - attribute \src "libresoc.v:168983.3-168984.63" - process $proc$libresoc.v:168983$9394 + attribute \src "libresoc.v:169751.3-169752.63" + process $proc$libresoc.v:169751$9326 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9395 \alu_op__input_carry$14$next + assign $0\alu_op__input_carry$14[1:0]$9327 \alu_op__input_carry$14$next sync posedge \coresync_clk - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9395 + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9327 end - attribute \src "libresoc.v:168985.3-168986.65" - process $proc$libresoc.v:168985$9396 + attribute \src "libresoc.v:169753.3-169754.65" + process $proc$libresoc.v:169753$9328 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9397 \alu_op__output_carry$15$next + assign $0\alu_op__output_carry$15[0:0]$9329 \alu_op__output_carry$15$next sync posedge \coresync_clk - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9397 + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9329 end - attribute \src "libresoc.v:168987.3-168988.57" - process $proc$libresoc.v:168987$9398 + attribute \src "libresoc.v:169755.3-169756.57" + process $proc$libresoc.v:169755$9330 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9399 \alu_op__is_32bit$16$next + assign $0\alu_op__is_32bit$16[0:0]$9331 \alu_op__is_32bit$16$next sync posedge \coresync_clk - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9399 + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9331 end - attribute \src "libresoc.v:168989.3-168990.59" - process $proc$libresoc.v:168989$9400 + attribute \src "libresoc.v:169757.3-169758.59" + process $proc$libresoc.v:169757$9332 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9401 \alu_op__is_signed$17$next + assign $0\alu_op__is_signed$17[0:0]$9333 \alu_op__is_signed$17$next sync posedge \coresync_clk - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9401 + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9333 end - attribute \src "libresoc.v:168991.3-168992.57" - process $proc$libresoc.v:168991$9402 + attribute \src "libresoc.v:169759.3-169760.57" + process $proc$libresoc.v:169759$9334 assign { } { } - assign $0\alu_op__data_len$18[3:0]$9403 \alu_op__data_len$18$next + assign $0\alu_op__data_len$18[3:0]$9335 \alu_op__data_len$18$next sync posedge \coresync_clk - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9403 + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9335 end - attribute \src "libresoc.v:168993.3-168994.49" - process $proc$libresoc.v:168993$9404 + attribute \src "libresoc.v:169761.3-169762.49" + process $proc$libresoc.v:169761$9336 assign { } { } - assign $0\alu_op__insn$19[31:0]$9405 \alu_op__insn$19$next + assign $0\alu_op__insn$19[31:0]$9337 \alu_op__insn$19$next sync posedge \coresync_clk - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9405 + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9337 end - attribute \src "libresoc.v:168995.3-168996.33" - process $proc$libresoc.v:168995$9406 + attribute \src "libresoc.v:169763.3-169764.33" + process $proc$libresoc.v:169763$9338 assign { } { } - assign $0\muxid$1[1:0]$9407 \muxid$1$next + assign $0\muxid$1[1:0]$9339 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9407 + update \muxid$1 $0\muxid$1[1:0]$9339 end - attribute \src "libresoc.v:168997.3-168998.29" - process $proc$libresoc.v:168997$9408 + attribute \src "libresoc.v:169765.3-169766.29" + process $proc$libresoc.v:169765$9340 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:169063.3-169080.6" - process $proc$libresoc.v:169063$9409 + attribute \src "libresoc.v:169831.3-169848.6" + process $proc$libresoc.v:169831$9341 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9410 $2\r_busy$next[0:0]$9412 - attribute \src "libresoc.v:169064.5-169064.29" + assign $0\r_busy$next[0:0]$9342 $2\r_busy$next[0:0]$9344 + attribute \src "libresoc.v:169832.5-169832.29" switch \initial - attribute \src "libresoc.v:169064.9-169064.17" + attribute \src "libresoc.v:169832.9-169832.17" case 1'1 case end @@ -347863,34 +314406,34 @@ module \pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9411 1'1 + assign $1\r_busy$next[0:0]$9343 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9411 1'0 + assign $1\r_busy$next[0:0]$9343 1'0 case - assign $1\r_busy$next[0:0]$9411 \r_busy + assign $1\r_busy$next[0:0]$9343 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9412 1'0 + assign $2\r_busy$next[0:0]$9344 1'0 case - assign $2\r_busy$next[0:0]$9412 $1\r_busy$next[0:0]$9411 + assign $2\r_busy$next[0:0]$9344 $1\r_busy$next[0:0]$9343 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9410 + update \r_busy$next $0\r_busy$next[0:0]$9342 end - attribute \src "libresoc.v:169081.3-169093.6" - process $proc$libresoc.v:169081$9413 + attribute \src "libresoc.v:169849.3-169861.6" + process $proc$libresoc.v:169849$9345 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9414 $1\muxid$1$next[1:0]$9415 - attribute \src "libresoc.v:169082.5-169082.29" + assign $0\muxid$1$next[1:0]$9346 $1\muxid$1$next[1:0]$9347 + attribute \src "libresoc.v:169850.5-169850.29" switch \initial - attribute \src "libresoc.v:169082.9-169082.17" + attribute \src "libresoc.v:169850.9-169850.17" case 1'1 case end @@ -347899,19 +314442,19 @@ module \pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9415 \muxid$62 + assign $1\muxid$1$next[1:0]$9347 \muxid$62 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9415 \muxid$62 + assign $1\muxid$1$next[1:0]$9347 \muxid$62 case - assign $1\muxid$1$next[1:0]$9415 \muxid$1 + assign $1\muxid$1$next[1:0]$9347 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9414 + update \muxid$1$next $0\muxid$1$next[1:0]$9346 end - attribute \src "libresoc.v:169094.3-169135.6" - process $proc$libresoc.v:169094$9416 + attribute \src "libresoc.v:169862.3-169903.6" + process $proc$libresoc.v:169862$9348 assign { } { } assign { } { } assign { } { } @@ -347948,33 +314491,33 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign $0\alu_op__data_len$18$next[3:0]$9417 $1\alu_op__data_len$18$next[3:0]$9435 - assign $0\alu_op__fn_unit$3$next[13:0]$9418 $1\alu_op__fn_unit$3$next[13:0]$9436 + assign $0\alu_op__data_len$18$next[3:0]$9349 $1\alu_op__data_len$18$next[3:0]$9367 + assign $0\alu_op__fn_unit$3$next[13:0]$9350 $1\alu_op__fn_unit$3$next[13:0]$9368 assign { } { } assign { } { } - assign $0\alu_op__input_carry$14$next[1:0]$9421 $1\alu_op__input_carry$14$next[1:0]$9439 - assign $0\alu_op__insn$19$next[31:0]$9422 $1\alu_op__insn$19$next[31:0]$9440 - assign $0\alu_op__insn_type$2$next[6:0]$9423 $1\alu_op__insn_type$2$next[6:0]$9441 - assign $0\alu_op__invert_in$10$next[0:0]$9424 $1\alu_op__invert_in$10$next[0:0]$9442 - assign $0\alu_op__invert_out$12$next[0:0]$9425 $1\alu_op__invert_out$12$next[0:0]$9443 - assign $0\alu_op__is_32bit$16$next[0:0]$9426 $1\alu_op__is_32bit$16$next[0:0]$9444 - assign $0\alu_op__is_signed$17$next[0:0]$9427 $1\alu_op__is_signed$17$next[0:0]$9445 + assign $0\alu_op__input_carry$14$next[1:0]$9353 $1\alu_op__input_carry$14$next[1:0]$9371 + assign $0\alu_op__insn$19$next[31:0]$9354 $1\alu_op__insn$19$next[31:0]$9372 + assign $0\alu_op__insn_type$2$next[6:0]$9355 $1\alu_op__insn_type$2$next[6:0]$9373 + assign $0\alu_op__invert_in$10$next[0:0]$9356 $1\alu_op__invert_in$10$next[0:0]$9374 + assign $0\alu_op__invert_out$12$next[0:0]$9357 $1\alu_op__invert_out$12$next[0:0]$9375 + assign $0\alu_op__is_32bit$16$next[0:0]$9358 $1\alu_op__is_32bit$16$next[0:0]$9376 + assign $0\alu_op__is_signed$17$next[0:0]$9359 $1\alu_op__is_signed$17$next[0:0]$9377 assign { } { } assign { } { } - assign $0\alu_op__output_carry$15$next[0:0]$9430 $1\alu_op__output_carry$15$next[0:0]$9448 + assign $0\alu_op__output_carry$15$next[0:0]$9362 $1\alu_op__output_carry$15$next[0:0]$9380 assign { } { } assign { } { } - assign $0\alu_op__write_cr0$13$next[0:0]$9433 $1\alu_op__write_cr0$13$next[0:0]$9451 - assign $0\alu_op__zero_a$11$next[0:0]$9434 $1\alu_op__zero_a$11$next[0:0]$9452 - assign $0\alu_op__imm_data__data$4$next[63:0]$9419 $2\alu_op__imm_data__data$4$next[63:0]$9453 - assign $0\alu_op__imm_data__ok$5$next[0:0]$9420 $2\alu_op__imm_data__ok$5$next[0:0]$9454 - assign $0\alu_op__oe__oe$8$next[0:0]$9428 $2\alu_op__oe__oe$8$next[0:0]$9455 - assign $0\alu_op__oe__ok$9$next[0:0]$9429 $2\alu_op__oe__ok$9$next[0:0]$9456 - assign $0\alu_op__rc__ok$7$next[0:0]$9431 $2\alu_op__rc__ok$7$next[0:0]$9457 - assign $0\alu_op__rc__rc$6$next[0:0]$9432 $2\alu_op__rc__rc$6$next[0:0]$9458 - attribute \src "libresoc.v:169095.5-169095.29" + assign $0\alu_op__write_cr0$13$next[0:0]$9365 $1\alu_op__write_cr0$13$next[0:0]$9383 + assign $0\alu_op__zero_a$11$next[0:0]$9366 $1\alu_op__zero_a$11$next[0:0]$9384 + assign $0\alu_op__imm_data__data$4$next[63:0]$9351 $2\alu_op__imm_data__data$4$next[63:0]$9385 + assign $0\alu_op__imm_data__ok$5$next[0:0]$9352 $2\alu_op__imm_data__ok$5$next[0:0]$9386 + assign $0\alu_op__oe__oe$8$next[0:0]$9360 $2\alu_op__oe__oe$8$next[0:0]$9387 + assign $0\alu_op__oe__ok$9$next[0:0]$9361 $2\alu_op__oe__ok$9$next[0:0]$9388 + assign $0\alu_op__rc__ok$7$next[0:0]$9363 $2\alu_op__rc__ok$7$next[0:0]$9389 + assign $0\alu_op__rc__rc$6$next[0:0]$9364 $2\alu_op__rc__rc$6$next[0:0]$9390 + attribute \src "libresoc.v:169863.5-169863.29" switch \initial - attribute \src "libresoc.v:169095.9-169095.17" + attribute \src "libresoc.v:169863.9-169863.17" case 1'1 case end @@ -348000,7 +314543,7 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9440 $1\alu_op__data_len$18$next[3:0]$9435 $1\alu_op__is_signed$17$next[0:0]$9445 $1\alu_op__is_32bit$16$next[0:0]$9444 $1\alu_op__output_carry$15$next[0:0]$9448 $1\alu_op__input_carry$14$next[1:0]$9439 $1\alu_op__write_cr0$13$next[0:0]$9451 $1\alu_op__invert_out$12$next[0:0]$9443 $1\alu_op__zero_a$11$next[0:0]$9452 $1\alu_op__invert_in$10$next[0:0]$9442 $1\alu_op__oe__ok$9$next[0:0]$9447 $1\alu_op__oe__oe$8$next[0:0]$9446 $1\alu_op__rc__ok$7$next[0:0]$9449 $1\alu_op__rc__rc$6$next[0:0]$9450 $1\alu_op__imm_data__ok$5$next[0:0]$9438 $1\alu_op__imm_data__data$4$next[63:0]$9437 $1\alu_op__fn_unit$3$next[13:0]$9436 $1\alu_op__insn_type$2$next[6:0]$9441 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { $1\alu_op__insn$19$next[31:0]$9372 $1\alu_op__data_len$18$next[3:0]$9367 $1\alu_op__is_signed$17$next[0:0]$9377 $1\alu_op__is_32bit$16$next[0:0]$9376 $1\alu_op__output_carry$15$next[0:0]$9380 $1\alu_op__input_carry$14$next[1:0]$9371 $1\alu_op__write_cr0$13$next[0:0]$9383 $1\alu_op__invert_out$12$next[0:0]$9375 $1\alu_op__zero_a$11$next[0:0]$9384 $1\alu_op__invert_in$10$next[0:0]$9374 $1\alu_op__oe__ok$9$next[0:0]$9379 $1\alu_op__oe__oe$8$next[0:0]$9378 $1\alu_op__rc__ok$7$next[0:0]$9381 $1\alu_op__rc__rc$6$next[0:0]$9382 $1\alu_op__imm_data__ok$5$next[0:0]$9370 $1\alu_op__imm_data__data$4$next[63:0]$9369 $1\alu_op__fn_unit$3$next[13:0]$9368 $1\alu_op__insn_type$2$next[6:0]$9373 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -348021,26 +314564,26 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9440 $1\alu_op__data_len$18$next[3:0]$9435 $1\alu_op__is_signed$17$next[0:0]$9445 $1\alu_op__is_32bit$16$next[0:0]$9444 $1\alu_op__output_carry$15$next[0:0]$9448 $1\alu_op__input_carry$14$next[1:0]$9439 $1\alu_op__write_cr0$13$next[0:0]$9451 $1\alu_op__invert_out$12$next[0:0]$9443 $1\alu_op__zero_a$11$next[0:0]$9452 $1\alu_op__invert_in$10$next[0:0]$9442 $1\alu_op__oe__ok$9$next[0:0]$9447 $1\alu_op__oe__oe$8$next[0:0]$9446 $1\alu_op__rc__ok$7$next[0:0]$9449 $1\alu_op__rc__rc$6$next[0:0]$9450 $1\alu_op__imm_data__ok$5$next[0:0]$9438 $1\alu_op__imm_data__data$4$next[63:0]$9437 $1\alu_op__fn_unit$3$next[13:0]$9436 $1\alu_op__insn_type$2$next[6:0]$9441 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { $1\alu_op__insn$19$next[31:0]$9372 $1\alu_op__data_len$18$next[3:0]$9367 $1\alu_op__is_signed$17$next[0:0]$9377 $1\alu_op__is_32bit$16$next[0:0]$9376 $1\alu_op__output_carry$15$next[0:0]$9380 $1\alu_op__input_carry$14$next[1:0]$9371 $1\alu_op__write_cr0$13$next[0:0]$9383 $1\alu_op__invert_out$12$next[0:0]$9375 $1\alu_op__zero_a$11$next[0:0]$9384 $1\alu_op__invert_in$10$next[0:0]$9374 $1\alu_op__oe__ok$9$next[0:0]$9379 $1\alu_op__oe__oe$8$next[0:0]$9378 $1\alu_op__rc__ok$7$next[0:0]$9381 $1\alu_op__rc__rc$6$next[0:0]$9382 $1\alu_op__imm_data__ok$5$next[0:0]$9370 $1\alu_op__imm_data__data$4$next[63:0]$9369 $1\alu_op__fn_unit$3$next[13:0]$9368 $1\alu_op__insn_type$2$next[6:0]$9373 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } case - assign $1\alu_op__data_len$18$next[3:0]$9435 \alu_op__data_len$18 - assign $1\alu_op__fn_unit$3$next[13:0]$9436 \alu_op__fn_unit$3 - assign $1\alu_op__imm_data__data$4$next[63:0]$9437 \alu_op__imm_data__data$4 - assign $1\alu_op__imm_data__ok$5$next[0:0]$9438 \alu_op__imm_data__ok$5 - assign $1\alu_op__input_carry$14$next[1:0]$9439 \alu_op__input_carry$14 - assign $1\alu_op__insn$19$next[31:0]$9440 \alu_op__insn$19 - assign $1\alu_op__insn_type$2$next[6:0]$9441 \alu_op__insn_type$2 - assign $1\alu_op__invert_in$10$next[0:0]$9442 \alu_op__invert_in$10 - assign $1\alu_op__invert_out$12$next[0:0]$9443 \alu_op__invert_out$12 - assign $1\alu_op__is_32bit$16$next[0:0]$9444 \alu_op__is_32bit$16 - assign $1\alu_op__is_signed$17$next[0:0]$9445 \alu_op__is_signed$17 - assign $1\alu_op__oe__oe$8$next[0:0]$9446 \alu_op__oe__oe$8 - assign $1\alu_op__oe__ok$9$next[0:0]$9447 \alu_op__oe__ok$9 - assign $1\alu_op__output_carry$15$next[0:0]$9448 \alu_op__output_carry$15 - assign $1\alu_op__rc__ok$7$next[0:0]$9449 \alu_op__rc__ok$7 - assign $1\alu_op__rc__rc$6$next[0:0]$9450 \alu_op__rc__rc$6 - assign $1\alu_op__write_cr0$13$next[0:0]$9451 \alu_op__write_cr0$13 - assign $1\alu_op__zero_a$11$next[0:0]$9452 \alu_op__zero_a$11 + assign $1\alu_op__data_len$18$next[3:0]$9367 \alu_op__data_len$18 + assign $1\alu_op__fn_unit$3$next[13:0]$9368 \alu_op__fn_unit$3 + assign $1\alu_op__imm_data__data$4$next[63:0]$9369 \alu_op__imm_data__data$4 + assign $1\alu_op__imm_data__ok$5$next[0:0]$9370 \alu_op__imm_data__ok$5 + assign $1\alu_op__input_carry$14$next[1:0]$9371 \alu_op__input_carry$14 + assign $1\alu_op__insn$19$next[31:0]$9372 \alu_op__insn$19 + assign $1\alu_op__insn_type$2$next[6:0]$9373 \alu_op__insn_type$2 + assign $1\alu_op__invert_in$10$next[0:0]$9374 \alu_op__invert_in$10 + assign $1\alu_op__invert_out$12$next[0:0]$9375 \alu_op__invert_out$12 + assign $1\alu_op__is_32bit$16$next[0:0]$9376 \alu_op__is_32bit$16 + assign $1\alu_op__is_signed$17$next[0:0]$9377 \alu_op__is_signed$17 + assign $1\alu_op__oe__oe$8$next[0:0]$9378 \alu_op__oe__oe$8 + assign $1\alu_op__oe__ok$9$next[0:0]$9379 \alu_op__oe__ok$9 + assign $1\alu_op__output_carry$15$next[0:0]$9380 \alu_op__output_carry$15 + assign $1\alu_op__rc__ok$7$next[0:0]$9381 \alu_op__rc__ok$7 + assign $1\alu_op__rc__rc$6$next[0:0]$9382 \alu_op__rc__rc$6 + assign $1\alu_op__write_cr0$13$next[0:0]$9383 \alu_op__write_cr0$13 + assign $1\alu_op__zero_a$11$next[0:0]$9384 \alu_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -348052,52 +314595,52 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign $2\alu_op__imm_data__data$4$next[63:0]$9453 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9454 1'0 - assign $2\alu_op__rc__rc$6$next[0:0]$9458 1'0 - assign $2\alu_op__rc__ok$7$next[0:0]$9457 1'0 - assign $2\alu_op__oe__oe$8$next[0:0]$9455 1'0 - assign $2\alu_op__oe__ok$9$next[0:0]$9456 1'0 + assign $2\alu_op__imm_data__data$4$next[63:0]$9385 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9386 1'0 + assign $2\alu_op__rc__rc$6$next[0:0]$9390 1'0 + assign $2\alu_op__rc__ok$7$next[0:0]$9389 1'0 + assign $2\alu_op__oe__oe$8$next[0:0]$9387 1'0 + assign $2\alu_op__oe__ok$9$next[0:0]$9388 1'0 case - assign $2\alu_op__imm_data__data$4$next[63:0]$9453 $1\alu_op__imm_data__data$4$next[63:0]$9437 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9454 $1\alu_op__imm_data__ok$5$next[0:0]$9438 - assign $2\alu_op__oe__oe$8$next[0:0]$9455 $1\alu_op__oe__oe$8$next[0:0]$9446 - assign $2\alu_op__oe__ok$9$next[0:0]$9456 $1\alu_op__oe__ok$9$next[0:0]$9447 - assign $2\alu_op__rc__ok$7$next[0:0]$9457 $1\alu_op__rc__ok$7$next[0:0]$9449 - assign $2\alu_op__rc__rc$6$next[0:0]$9458 $1\alu_op__rc__rc$6$next[0:0]$9450 + assign $2\alu_op__imm_data__data$4$next[63:0]$9385 $1\alu_op__imm_data__data$4$next[63:0]$9369 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9386 $1\alu_op__imm_data__ok$5$next[0:0]$9370 + assign $2\alu_op__oe__oe$8$next[0:0]$9387 $1\alu_op__oe__oe$8$next[0:0]$9378 + assign $2\alu_op__oe__ok$9$next[0:0]$9388 $1\alu_op__oe__ok$9$next[0:0]$9379 + assign $2\alu_op__rc__ok$7$next[0:0]$9389 $1\alu_op__rc__ok$7$next[0:0]$9381 + assign $2\alu_op__rc__rc$6$next[0:0]$9390 $1\alu_op__rc__rc$6$next[0:0]$9382 end sync always - update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9417 - update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[13:0]$9418 - update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9419 - update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9420 - update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9421 - update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9422 - update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9423 - update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9424 - update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9425 - update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9426 - update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9427 - update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9428 - update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9429 - update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9430 - update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9431 - update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9432 - update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9433 - update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9434 + update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9349 + update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[13:0]$9350 + update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9351 + update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9352 + update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9353 + update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9354 + update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9355 + update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9356 + update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9357 + update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9358 + update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9359 + update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9360 + update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9361 + update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9362 + update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9363 + update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9364 + update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9365 + update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9366 end - attribute \src "libresoc.v:169136.3-169154.6" - process $proc$libresoc.v:169136$9459 + attribute \src "libresoc.v:169904.3-169922.6" + process $proc$libresoc.v:169904$9391 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$20$next[63:0]$9460 $1\o$20$next[63:0]$9462 + assign $0\o$20$next[63:0]$9392 $1\o$20$next[63:0]$9394 assign { } { } - assign $0\o_ok$21$next[0:0]$9461 $2\o_ok$21$next[0:0]$9464 - attribute \src "libresoc.v:169137.5-169137.29" + assign $0\o_ok$21$next[0:0]$9393 $2\o_ok$21$next[0:0]$9396 + attribute \src "libresoc.v:169905.5-169905.29" switch \initial - attribute \src "libresoc.v:169137.9-169137.17" + attribute \src "libresoc.v:169905.9-169905.17" case 1'1 case end @@ -348107,41 +314650,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$9463 $1\o$20$next[63:0]$9462 } { \o_ok$82 \o$81 } + assign { $1\o_ok$21$next[0:0]$9395 $1\o$20$next[63:0]$9394 } { \o_ok$82 \o$81 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$9463 $1\o$20$next[63:0]$9462 } { \o_ok$82 \o$81 } + assign { $1\o_ok$21$next[0:0]$9395 $1\o$20$next[63:0]$9394 } { \o_ok$82 \o$81 } case - assign $1\o$20$next[63:0]$9462 \o$20 - assign $1\o_ok$21$next[0:0]$9463 \o_ok$21 + assign $1\o$20$next[63:0]$9394 \o$20 + assign $1\o_ok$21$next[0:0]$9395 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$9464 1'0 + assign $2\o_ok$21$next[0:0]$9396 1'0 case - assign $2\o_ok$21$next[0:0]$9464 $1\o_ok$21$next[0:0]$9463 + assign $2\o_ok$21$next[0:0]$9396 $1\o_ok$21$next[0:0]$9395 end sync always - update \o$20$next $0\o$20$next[63:0]$9460 - update \o_ok$21$next $0\o_ok$21$next[0:0]$9461 + update \o$20$next $0\o$20$next[63:0]$9392 + update \o_ok$21$next $0\o_ok$21$next[0:0]$9393 end - attribute \src "libresoc.v:169155.3-169173.6" - process $proc$libresoc.v:169155$9465 + attribute \src "libresoc.v:169923.3-169941.6" + process $proc$libresoc.v:169923$9397 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$22$next[3:0]$9466 $1\cr_a$22$next[3:0]$9468 + assign $0\cr_a$22$next[3:0]$9398 $1\cr_a$22$next[3:0]$9400 assign { } { } - assign $0\cr_a_ok$23$next[0:0]$9467 $2\cr_a_ok$23$next[0:0]$9470 - attribute \src "libresoc.v:169156.5-169156.29" + assign $0\cr_a_ok$23$next[0:0]$9399 $2\cr_a_ok$23$next[0:0]$9402 + attribute \src "libresoc.v:169924.5-169924.29" switch \initial - attribute \src "libresoc.v:169156.9-169156.17" + attribute \src "libresoc.v:169924.9-169924.17" case 1'1 case end @@ -348151,41 +314694,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9469 $1\cr_a$22$next[3:0]$9468 } { \cr_a_ok$84 \cr_a$83 } + assign { $1\cr_a_ok$23$next[0:0]$9401 $1\cr_a$22$next[3:0]$9400 } { \cr_a_ok$84 \cr_a$83 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9469 $1\cr_a$22$next[3:0]$9468 } { \cr_a_ok$84 \cr_a$83 } + assign { $1\cr_a_ok$23$next[0:0]$9401 $1\cr_a$22$next[3:0]$9400 } { \cr_a_ok$84 \cr_a$83 } case - assign $1\cr_a$22$next[3:0]$9468 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$9469 \cr_a_ok$23 + assign $1\cr_a$22$next[3:0]$9400 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$9401 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$9470 1'0 + assign $2\cr_a_ok$23$next[0:0]$9402 1'0 case - assign $2\cr_a_ok$23$next[0:0]$9470 $1\cr_a_ok$23$next[0:0]$9469 + assign $2\cr_a_ok$23$next[0:0]$9402 $1\cr_a_ok$23$next[0:0]$9401 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$9466 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9467 + update \cr_a$22$next $0\cr_a$22$next[3:0]$9398 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9399 end - attribute \src "libresoc.v:169174.3-169192.6" - process $proc$libresoc.v:169174$9471 + attribute \src "libresoc.v:169942.3-169960.6" + process $proc$libresoc.v:169942$9403 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$24$next[1:0]$9472 $1\xer_ca$24$next[1:0]$9474 + assign $0\xer_ca$24$next[1:0]$9404 $1\xer_ca$24$next[1:0]$9406 assign { } { } - assign $0\xer_ca_ok$25$next[0:0]$9473 $2\xer_ca_ok$25$next[0:0]$9476 - attribute \src "libresoc.v:169175.5-169175.29" + assign $0\xer_ca_ok$25$next[0:0]$9405 $2\xer_ca_ok$25$next[0:0]$9408 + attribute \src "libresoc.v:169943.5-169943.29" switch \initial - attribute \src "libresoc.v:169175.9-169175.17" + attribute \src "libresoc.v:169943.9-169943.17" case 1'1 case end @@ -348195,41 +314738,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9475 $1\xer_ca$24$next[1:0]$9474 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\xer_ca_ok$25$next[0:0]$9407 $1\xer_ca$24$next[1:0]$9406 } { \xer_ca_ok$86 \xer_ca$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9475 $1\xer_ca$24$next[1:0]$9474 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\xer_ca_ok$25$next[0:0]$9407 $1\xer_ca$24$next[1:0]$9406 } { \xer_ca_ok$86 \xer_ca$85 } case - assign $1\xer_ca$24$next[1:0]$9474 \xer_ca$24 - assign $1\xer_ca_ok$25$next[0:0]$9475 \xer_ca_ok$25 + assign $1\xer_ca$24$next[1:0]$9406 \xer_ca$24 + assign $1\xer_ca_ok$25$next[0:0]$9407 \xer_ca_ok$25 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$25$next[0:0]$9476 1'0 + assign $2\xer_ca_ok$25$next[0:0]$9408 1'0 case - assign $2\xer_ca_ok$25$next[0:0]$9476 $1\xer_ca_ok$25$next[0:0]$9475 + assign $2\xer_ca_ok$25$next[0:0]$9408 $1\xer_ca_ok$25$next[0:0]$9407 end sync always - update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9472 - update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9473 + update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9404 + update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9405 end - attribute \src "libresoc.v:169193.3-169211.6" - process $proc$libresoc.v:169193$9477 + attribute \src "libresoc.v:169961.3-169979.6" + process $proc$libresoc.v:169961$9409 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$26$next[1:0]$9478 $1\xer_ov$26$next[1:0]$9480 + assign $0\xer_ov$26$next[1:0]$9410 $1\xer_ov$26$next[1:0]$9412 assign { } { } - assign $0\xer_ov_ok$27$next[0:0]$9479 $2\xer_ov_ok$27$next[0:0]$9482 - attribute \src "libresoc.v:169194.5-169194.29" + assign $0\xer_ov_ok$27$next[0:0]$9411 $2\xer_ov_ok$27$next[0:0]$9414 + attribute \src "libresoc.v:169962.5-169962.29" switch \initial - attribute \src "libresoc.v:169194.9-169194.17" + attribute \src "libresoc.v:169962.9-169962.17" case 1'1 case end @@ -348239,41 +314782,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9481 $1\xer_ov$26$next[1:0]$9480 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\xer_ov_ok$27$next[0:0]$9413 $1\xer_ov$26$next[1:0]$9412 } { \xer_ov_ok$88 \xer_ov$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9481 $1\xer_ov$26$next[1:0]$9480 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\xer_ov_ok$27$next[0:0]$9413 $1\xer_ov$26$next[1:0]$9412 } { \xer_ov_ok$88 \xer_ov$87 } case - assign $1\xer_ov$26$next[1:0]$9480 \xer_ov$26 - assign $1\xer_ov_ok$27$next[0:0]$9481 \xer_ov_ok$27 + assign $1\xer_ov$26$next[1:0]$9412 \xer_ov$26 + assign $1\xer_ov_ok$27$next[0:0]$9413 \xer_ov_ok$27 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$27$next[0:0]$9482 1'0 + assign $2\xer_ov_ok$27$next[0:0]$9414 1'0 case - assign $2\xer_ov_ok$27$next[0:0]$9482 $1\xer_ov_ok$27$next[0:0]$9481 + assign $2\xer_ov_ok$27$next[0:0]$9414 $1\xer_ov_ok$27$next[0:0]$9413 end sync always - update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9478 - update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9479 + update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9410 + update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9411 end - attribute \src "libresoc.v:169212.3-169230.6" - process $proc$libresoc.v:169212$9483 + attribute \src "libresoc.v:169980.3-169998.6" + process $proc$libresoc.v:169980$9415 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$28$next[0:0]$9484 $1\xer_so$28$next[0:0]$9486 + assign $0\xer_so$28$next[0:0]$9416 $1\xer_so$28$next[0:0]$9418 assign { } { } - assign $0\xer_so_ok$29$next[0:0]$9485 $2\xer_so_ok$29$next[0:0]$9488 - attribute \src "libresoc.v:169213.5-169213.29" + assign $0\xer_so_ok$29$next[0:0]$9417 $2\xer_so_ok$29$next[0:0]$9420 + attribute \src "libresoc.v:169981.5-169981.29" switch \initial - attribute \src "libresoc.v:169213.9-169213.17" + attribute \src "libresoc.v:169981.9-169981.17" case 1'1 case end @@ -348283,30 +314826,30 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9487 $1\xer_so$28$next[0:0]$9486 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_so_ok$29$next[0:0]$9419 $1\xer_so$28$next[0:0]$9418 } { \xer_so_ok$90 \xer_so$89 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9487 $1\xer_so$28$next[0:0]$9486 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_so_ok$29$next[0:0]$9419 $1\xer_so$28$next[0:0]$9418 } { \xer_so_ok$90 \xer_so$89 } case - assign $1\xer_so$28$next[0:0]$9486 \xer_so$28 - assign $1\xer_so_ok$29$next[0:0]$9487 \xer_so_ok$29 + assign $1\xer_so$28$next[0:0]$9418 \xer_so$28 + assign $1\xer_so_ok$29$next[0:0]$9419 \xer_so_ok$29 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$29$next[0:0]$9488 1'0 + assign $2\xer_so_ok$29$next[0:0]$9420 1'0 case - assign $2\xer_so_ok$29$next[0:0]$9488 $1\xer_so_ok$29$next[0:0]$9487 + assign $2\xer_so_ok$29$next[0:0]$9420 $1\xer_so_ok$29$next[0:0]$9419 end sync always - update \xer_so$28$next $0\xer_so$28$next[0:0]$9484 - update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9485 + update \xer_so$28$next $0\xer_so$28$next[0:0]$9416 + update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9417 end - connect \$60 $and$libresoc.v:168938$9349_Y + connect \$60 $and$libresoc.v:169706$9281_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } @@ -348327,260 +314870,260 @@ module \pipe2 connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:169254.1-170323.10" +attribute \src "libresoc.v:170022.1-171091.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" attribute \generator "nMigen" module \pipe2$115 - attribute \src "libresoc.v:170269.3-170287.6" - wire width 4 $0\cr_a$21$next[3:0]$9654 - attribute \src "libresoc.v:170075.3-170076.33" - wire width 4 $0\cr_a$21[3:0]$9555 - attribute \src "libresoc.v:169266.13-169266.29" - wire width 4 $0\cr_a$21[3:0]$9667 - attribute \src "libresoc.v:170269.3-170287.6" - wire $0\cr_a_ok$22$next[0:0]$9655 - attribute \src "libresoc.v:170077.3-170078.39" - wire $0\cr_a_ok$22[0:0]$9557 - attribute \src "libresoc.v:169275.7-169275.26" - wire $0\cr_a_ok$22[0:0]$9669 - attribute \src "libresoc.v:169255.7-169255.20" + attribute \src "libresoc.v:171037.3-171055.6" + wire width 4 $0\cr_a$21$next[3:0]$9586 + attribute \src "libresoc.v:170843.3-170844.33" + wire width 4 $0\cr_a$21[3:0]$9487 + attribute \src "libresoc.v:170034.13-170034.29" + wire width 4 $0\cr_a$21[3:0]$9599 + attribute \src "libresoc.v:171037.3-171055.6" + wire $0\cr_a_ok$22$next[0:0]$9587 + attribute \src "libresoc.v:170845.3-170846.39" + wire $0\cr_a_ok$22[0:0]$9489 + attribute \src "libresoc.v:170043.7-170043.26" + wire $0\cr_a_ok$22[0:0]$9601 + attribute \src "libresoc.v:170023.7-170023.20" wire $0\initial[0:0] - attribute \src "libresoc.v:170196.3-170208.6" - wire width 2 $0\muxid$1$next[1:0]$9604 - attribute \src "libresoc.v:170117.3-170118.33" - wire width 2 $0\muxid$1[1:0]$9597 - attribute \src "libresoc.v:169286.13-169286.29" - wire width 2 $0\muxid$1[1:0]$9671 - attribute \src "libresoc.v:170250.3-170268.6" - wire width 64 $0\o$19$next[63:0]$9648 - attribute \src "libresoc.v:170079.3-170080.27" - wire width 64 $0\o$19[63:0]$9559 - attribute \src "libresoc.v:169301.14-169301.43" - wire width 64 $0\o$19[63:0]$9673 - attribute \src "libresoc.v:170250.3-170268.6" - wire $0\o_ok$20$next[0:0]$9649 - attribute \src "libresoc.v:170081.3-170082.33" - wire $0\o_ok$20[0:0]$9561 - attribute \src "libresoc.v:169310.7-169310.23" - wire $0\o_ok$20[0:0]$9675 - attribute \src "libresoc.v:170178.3-170195.6" - wire $0\r_busy$next[0:0]$9600 - attribute \src "libresoc.v:170119.3-170120.29" + attribute \src "libresoc.v:170964.3-170976.6" + wire width 2 $0\muxid$1$next[1:0]$9536 + attribute \src "libresoc.v:170885.3-170886.33" + wire width 2 $0\muxid$1[1:0]$9529 + attribute \src "libresoc.v:170054.13-170054.29" + wire width 2 $0\muxid$1[1:0]$9603 + attribute \src "libresoc.v:171018.3-171036.6" + wire width 64 $0\o$19$next[63:0]$9580 + attribute \src "libresoc.v:170847.3-170848.27" + wire width 64 $0\o$19[63:0]$9491 + attribute \src "libresoc.v:170069.14-170069.43" + wire width 64 $0\o$19[63:0]$9605 + attribute \src "libresoc.v:171018.3-171036.6" + wire $0\o_ok$20$next[0:0]$9581 + attribute \src "libresoc.v:170849.3-170850.33" + wire $0\o_ok$20[0:0]$9493 + attribute \src "libresoc.v:170078.7-170078.23" + wire $0\o_ok$20[0:0]$9607 + attribute \src "libresoc.v:170946.3-170963.6" + wire $0\r_busy$next[0:0]$9532 + attribute \src "libresoc.v:170887.3-170888.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:170209.3-170249.6" - wire width 14 $0\sr_op__fn_unit$3$next[13:0]$9607 - attribute \src "libresoc.v:170085.3-170086.51" - wire width 14 $0\sr_op__fn_unit$3[13:0]$9565 - attribute \src "libresoc.v:169643.14-169643.43" - wire width 14 $0\sr_op__fn_unit$3[13:0]$9678 - attribute \src "libresoc.v:170209.3-170249.6" - wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9608 - attribute \src "libresoc.v:170087.3-170088.65" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9567 - attribute \src "libresoc.v:169667.14-169667.62" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9680 - attribute \src "libresoc.v:170209.3-170249.6" - wire $0\sr_op__imm_data__ok$5$next[0:0]$9609 - attribute \src "libresoc.v:170089.3-170090.61" - wire $0\sr_op__imm_data__ok$5[0:0]$9569 - attribute \src "libresoc.v:169676.7-169676.37" - wire $0\sr_op__imm_data__ok$5[0:0]$9682 - attribute \src "libresoc.v:170209.3-170249.6" - wire width 2 $0\sr_op__input_carry$12$next[1:0]$9610 - attribute \src "libresoc.v:170103.3-170104.61" - wire width 2 $0\sr_op__input_carry$12[1:0]$9583 - attribute \src "libresoc.v:169693.13-169693.43" - wire width 2 $0\sr_op__input_carry$12[1:0]$9684 - attribute \src "libresoc.v:170209.3-170249.6" - wire $0\sr_op__input_cr$14$next[0:0]$9611 - attribute \src "libresoc.v:170107.3-170108.55" - wire $0\sr_op__input_cr$14[0:0]$9587 - attribute \src "libresoc.v:169706.7-169706.34" - wire $0\sr_op__input_cr$14[0:0]$9686 - attribute \src "libresoc.v:170209.3-170249.6" - wire width 32 $0\sr_op__insn$18$next[31:0]$9612 - attribute \src "libresoc.v:170115.3-170116.47" - wire width 32 $0\sr_op__insn$18[31:0]$9595 - attribute \src "libresoc.v:169715.14-169715.38" - wire width 32 $0\sr_op__insn$18[31:0]$9688 - attribute \src "libresoc.v:170209.3-170249.6" - wire width 7 $0\sr_op__insn_type$2$next[6:0]$9613 - attribute \src "libresoc.v:170083.3-170084.55" - wire width 7 $0\sr_op__insn_type$2[6:0]$9563 - attribute \src "libresoc.v:169874.13-169874.41" - wire width 7 $0\sr_op__insn_type$2[6:0]$9690 - attribute \src "libresoc.v:170209.3-170249.6" - wire $0\sr_op__invert_in$11$next[0:0]$9614 - attribute \src "libresoc.v:170101.3-170102.57" - wire $0\sr_op__invert_in$11[0:0]$9581 - attribute \src "libresoc.v:169958.7-169958.35" - wire $0\sr_op__invert_in$11[0:0]$9692 - attribute \src "libresoc.v:170209.3-170249.6" - wire $0\sr_op__is_32bit$16$next[0:0]$9615 - attribute \src "libresoc.v:170111.3-170112.55" - wire $0\sr_op__is_32bit$16[0:0]$9591 - attribute \src "libresoc.v:169967.7-169967.34" - wire $0\sr_op__is_32bit$16[0:0]$9694 - attribute \src "libresoc.v:170209.3-170249.6" - wire $0\sr_op__is_signed$17$next[0:0]$9616 - attribute \src "libresoc.v:170113.3-170114.57" - wire $0\sr_op__is_signed$17[0:0]$9593 - attribute \src "libresoc.v:169976.7-169976.35" - wire $0\sr_op__is_signed$17[0:0]$9696 - attribute \src "libresoc.v:170209.3-170249.6" - wire $0\sr_op__oe__oe$8$next[0:0]$9617 - attribute \src "libresoc.v:170095.3-170096.49" - wire $0\sr_op__oe__oe$8[0:0]$9575 - attribute \src "libresoc.v:169987.7-169987.31" - wire $0\sr_op__oe__oe$8[0:0]$9698 - attribute \src "libresoc.v:170209.3-170249.6" - wire $0\sr_op__oe__ok$9$next[0:0]$9618 - attribute \src "libresoc.v:170097.3-170098.49" - wire $0\sr_op__oe__ok$9[0:0]$9577 - attribute \src "libresoc.v:169996.7-169996.31" - wire $0\sr_op__oe__ok$9[0:0]$9700 - attribute \src "libresoc.v:170209.3-170249.6" - wire $0\sr_op__output_carry$13$next[0:0]$9619 - attribute \src "libresoc.v:170105.3-170106.63" - wire $0\sr_op__output_carry$13[0:0]$9585 - attribute \src "libresoc.v:170003.7-170003.38" - wire $0\sr_op__output_carry$13[0:0]$9702 - attribute \src "libresoc.v:170209.3-170249.6" - wire $0\sr_op__output_cr$15$next[0:0]$9620 - attribute \src "libresoc.v:170109.3-170110.57" - wire $0\sr_op__output_cr$15[0:0]$9589 - attribute \src "libresoc.v:170012.7-170012.35" - wire $0\sr_op__output_cr$15[0:0]$9704 - attribute \src "libresoc.v:170209.3-170249.6" - wire $0\sr_op__rc__ok$7$next[0:0]$9621 - attribute \src "libresoc.v:170093.3-170094.49" - wire $0\sr_op__rc__ok$7[0:0]$9573 - attribute \src "libresoc.v:170023.7-170023.31" - wire $0\sr_op__rc__ok$7[0:0]$9706 - attribute \src "libresoc.v:170209.3-170249.6" - wire $0\sr_op__rc__rc$6$next[0:0]$9622 - attribute \src "libresoc.v:170091.3-170092.49" - wire $0\sr_op__rc__rc$6[0:0]$9571 - attribute \src "libresoc.v:170032.7-170032.31" - wire $0\sr_op__rc__rc$6[0:0]$9708 - attribute \src "libresoc.v:170209.3-170249.6" - wire $0\sr_op__write_cr0$10$next[0:0]$9623 - attribute \src "libresoc.v:170099.3-170100.57" - wire $0\sr_op__write_cr0$10[0:0]$9579 - attribute \src "libresoc.v:170039.7-170039.35" - wire $0\sr_op__write_cr0$10[0:0]$9710 - attribute \src "libresoc.v:170288.3-170306.6" - wire width 2 $0\xer_ca$23$next[1:0]$9660 - attribute \src "libresoc.v:170071.3-170072.37" - wire width 2 $0\xer_ca$23[1:0]$9551 - attribute \src "libresoc.v:170048.13-170048.31" - wire width 2 $0\xer_ca$23[1:0]$9712 - attribute \src "libresoc.v:170288.3-170306.6" - wire $0\xer_ca_ok$24$next[0:0]$9661 - attribute \src "libresoc.v:170073.3-170074.43" - wire $0\xer_ca_ok$24[0:0]$9553 - attribute \src "libresoc.v:170057.7-170057.28" - wire $0\xer_ca_ok$24[0:0]$9714 - attribute \src "libresoc.v:170269.3-170287.6" - wire width 4 $1\cr_a$21$next[3:0]$9656 - attribute \src "libresoc.v:170269.3-170287.6" - wire $1\cr_a_ok$22$next[0:0]$9657 - attribute \src "libresoc.v:170196.3-170208.6" - wire width 2 $1\muxid$1$next[1:0]$9605 - attribute \src "libresoc.v:170250.3-170268.6" - wire width 64 $1\o$19$next[63:0]$9650 - attribute \src "libresoc.v:170250.3-170268.6" - wire $1\o_ok$20$next[0:0]$9651 - attribute \src "libresoc.v:170178.3-170195.6" - wire $1\r_busy$next[0:0]$9601 - attribute \src "libresoc.v:169606.7-169606.20" + attribute \src "libresoc.v:170977.3-171017.6" + wire width 14 $0\sr_op__fn_unit$3$next[13:0]$9539 + attribute \src "libresoc.v:170853.3-170854.51" + wire width 14 $0\sr_op__fn_unit$3[13:0]$9497 + attribute \src "libresoc.v:170411.14-170411.43" + wire width 14 $0\sr_op__fn_unit$3[13:0]$9610 + attribute \src "libresoc.v:170977.3-171017.6" + wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9540 + attribute \src "libresoc.v:170855.3-170856.65" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9499 + attribute \src "libresoc.v:170435.14-170435.62" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9612 + attribute \src "libresoc.v:170977.3-171017.6" + wire $0\sr_op__imm_data__ok$5$next[0:0]$9541 + attribute \src "libresoc.v:170857.3-170858.61" + wire $0\sr_op__imm_data__ok$5[0:0]$9501 + attribute \src "libresoc.v:170444.7-170444.37" + wire $0\sr_op__imm_data__ok$5[0:0]$9614 + attribute \src "libresoc.v:170977.3-171017.6" + wire width 2 $0\sr_op__input_carry$12$next[1:0]$9542 + attribute \src "libresoc.v:170871.3-170872.61" + wire width 2 $0\sr_op__input_carry$12[1:0]$9515 + attribute \src "libresoc.v:170461.13-170461.43" + wire width 2 $0\sr_op__input_carry$12[1:0]$9616 + attribute \src "libresoc.v:170977.3-171017.6" + wire $0\sr_op__input_cr$14$next[0:0]$9543 + attribute \src "libresoc.v:170875.3-170876.55" + wire $0\sr_op__input_cr$14[0:0]$9519 + attribute \src "libresoc.v:170474.7-170474.34" + wire $0\sr_op__input_cr$14[0:0]$9618 + attribute \src "libresoc.v:170977.3-171017.6" + wire width 32 $0\sr_op__insn$18$next[31:0]$9544 + attribute \src "libresoc.v:170883.3-170884.47" + wire width 32 $0\sr_op__insn$18[31:0]$9527 + attribute \src "libresoc.v:170483.14-170483.38" + wire width 32 $0\sr_op__insn$18[31:0]$9620 + attribute \src "libresoc.v:170977.3-171017.6" + wire width 7 $0\sr_op__insn_type$2$next[6:0]$9545 + attribute \src "libresoc.v:170851.3-170852.55" + wire width 7 $0\sr_op__insn_type$2[6:0]$9495 + attribute \src "libresoc.v:170642.13-170642.41" + wire width 7 $0\sr_op__insn_type$2[6:0]$9622 + attribute \src "libresoc.v:170977.3-171017.6" + wire $0\sr_op__invert_in$11$next[0:0]$9546 + attribute \src "libresoc.v:170869.3-170870.57" + wire $0\sr_op__invert_in$11[0:0]$9513 + attribute \src "libresoc.v:170726.7-170726.35" + wire $0\sr_op__invert_in$11[0:0]$9624 + attribute \src "libresoc.v:170977.3-171017.6" + wire $0\sr_op__is_32bit$16$next[0:0]$9547 + attribute \src "libresoc.v:170879.3-170880.55" + wire $0\sr_op__is_32bit$16[0:0]$9523 + attribute \src "libresoc.v:170735.7-170735.34" + wire $0\sr_op__is_32bit$16[0:0]$9626 + attribute \src "libresoc.v:170977.3-171017.6" + wire $0\sr_op__is_signed$17$next[0:0]$9548 + attribute \src "libresoc.v:170881.3-170882.57" + wire $0\sr_op__is_signed$17[0:0]$9525 + attribute \src "libresoc.v:170744.7-170744.35" + wire $0\sr_op__is_signed$17[0:0]$9628 + attribute \src "libresoc.v:170977.3-171017.6" + wire $0\sr_op__oe__oe$8$next[0:0]$9549 + attribute \src "libresoc.v:170863.3-170864.49" + wire $0\sr_op__oe__oe$8[0:0]$9507 + attribute \src "libresoc.v:170755.7-170755.31" + wire $0\sr_op__oe__oe$8[0:0]$9630 + attribute \src "libresoc.v:170977.3-171017.6" + wire $0\sr_op__oe__ok$9$next[0:0]$9550 + attribute \src "libresoc.v:170865.3-170866.49" + wire $0\sr_op__oe__ok$9[0:0]$9509 + attribute \src "libresoc.v:170764.7-170764.31" + wire $0\sr_op__oe__ok$9[0:0]$9632 + attribute \src "libresoc.v:170977.3-171017.6" + wire $0\sr_op__output_carry$13$next[0:0]$9551 + attribute \src "libresoc.v:170873.3-170874.63" + wire $0\sr_op__output_carry$13[0:0]$9517 + attribute \src "libresoc.v:170771.7-170771.38" + wire $0\sr_op__output_carry$13[0:0]$9634 + attribute \src "libresoc.v:170977.3-171017.6" + wire $0\sr_op__output_cr$15$next[0:0]$9552 + attribute \src "libresoc.v:170877.3-170878.57" + wire $0\sr_op__output_cr$15[0:0]$9521 + attribute \src "libresoc.v:170780.7-170780.35" + wire $0\sr_op__output_cr$15[0:0]$9636 + attribute \src "libresoc.v:170977.3-171017.6" + wire $0\sr_op__rc__ok$7$next[0:0]$9553 + attribute \src "libresoc.v:170861.3-170862.49" + wire $0\sr_op__rc__ok$7[0:0]$9505 + attribute \src "libresoc.v:170791.7-170791.31" + wire $0\sr_op__rc__ok$7[0:0]$9638 + attribute \src "libresoc.v:170977.3-171017.6" + wire $0\sr_op__rc__rc$6$next[0:0]$9554 + attribute \src "libresoc.v:170859.3-170860.49" + wire $0\sr_op__rc__rc$6[0:0]$9503 + attribute \src "libresoc.v:170800.7-170800.31" + wire $0\sr_op__rc__rc$6[0:0]$9640 + attribute \src "libresoc.v:170977.3-171017.6" + wire $0\sr_op__write_cr0$10$next[0:0]$9555 + attribute \src "libresoc.v:170867.3-170868.57" + wire $0\sr_op__write_cr0$10[0:0]$9511 + attribute \src "libresoc.v:170807.7-170807.35" + wire $0\sr_op__write_cr0$10[0:0]$9642 + attribute \src "libresoc.v:171056.3-171074.6" + wire width 2 $0\xer_ca$23$next[1:0]$9592 + attribute \src "libresoc.v:170839.3-170840.37" + wire width 2 $0\xer_ca$23[1:0]$9483 + attribute \src "libresoc.v:170816.13-170816.31" + wire width 2 $0\xer_ca$23[1:0]$9644 + attribute \src "libresoc.v:171056.3-171074.6" + wire $0\xer_ca_ok$24$next[0:0]$9593 + attribute \src "libresoc.v:170841.3-170842.43" + wire $0\xer_ca_ok$24[0:0]$9485 + attribute \src "libresoc.v:170825.7-170825.28" + wire $0\xer_ca_ok$24[0:0]$9646 + attribute \src "libresoc.v:171037.3-171055.6" + wire width 4 $1\cr_a$21$next[3:0]$9588 + attribute \src "libresoc.v:171037.3-171055.6" + wire $1\cr_a_ok$22$next[0:0]$9589 + attribute \src "libresoc.v:170964.3-170976.6" + wire width 2 $1\muxid$1$next[1:0]$9537 + attribute \src "libresoc.v:171018.3-171036.6" + wire width 64 $1\o$19$next[63:0]$9582 + attribute \src "libresoc.v:171018.3-171036.6" + wire $1\o_ok$20$next[0:0]$9583 + attribute \src "libresoc.v:170946.3-170963.6" + wire $1\r_busy$next[0:0]$9533 + attribute \src "libresoc.v:170374.7-170374.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:170209.3-170249.6" - wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9624 - attribute \src "libresoc.v:170209.3-170249.6" - wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9625 - attribute \src "libresoc.v:170209.3-170249.6" - wire $1\sr_op__imm_data__ok$5$next[0:0]$9626 - attribute \src "libresoc.v:170209.3-170249.6" - wire width 2 $1\sr_op__input_carry$12$next[1:0]$9627 - attribute \src "libresoc.v:170209.3-170249.6" - wire $1\sr_op__input_cr$14$next[0:0]$9628 - attribute \src "libresoc.v:170209.3-170249.6" - wire width 32 $1\sr_op__insn$18$next[31:0]$9629 - attribute \src "libresoc.v:170209.3-170249.6" - wire width 7 $1\sr_op__insn_type$2$next[6:0]$9630 - attribute \src "libresoc.v:170209.3-170249.6" - wire $1\sr_op__invert_in$11$next[0:0]$9631 - attribute \src "libresoc.v:170209.3-170249.6" - wire $1\sr_op__is_32bit$16$next[0:0]$9632 - attribute \src "libresoc.v:170209.3-170249.6" - wire $1\sr_op__is_signed$17$next[0:0]$9633 - attribute \src "libresoc.v:170209.3-170249.6" - wire $1\sr_op__oe__oe$8$next[0:0]$9634 - attribute \src "libresoc.v:170209.3-170249.6" - wire $1\sr_op__oe__ok$9$next[0:0]$9635 - attribute \src "libresoc.v:170209.3-170249.6" - wire $1\sr_op__output_carry$13$next[0:0]$9636 - attribute \src "libresoc.v:170209.3-170249.6" - wire $1\sr_op__output_cr$15$next[0:0]$9637 - attribute \src "libresoc.v:170209.3-170249.6" - wire $1\sr_op__rc__ok$7$next[0:0]$9638 - attribute \src "libresoc.v:170209.3-170249.6" - wire $1\sr_op__rc__rc$6$next[0:0]$9639 - attribute \src "libresoc.v:170209.3-170249.6" - wire $1\sr_op__write_cr0$10$next[0:0]$9640 - attribute \src "libresoc.v:170288.3-170306.6" - wire width 2 $1\xer_ca$23$next[1:0]$9662 - attribute \src "libresoc.v:170288.3-170306.6" - wire $1\xer_ca_ok$24$next[0:0]$9663 - attribute \src "libresoc.v:170269.3-170287.6" - wire $2\cr_a_ok$22$next[0:0]$9658 - attribute \src "libresoc.v:170250.3-170268.6" - wire $2\o_ok$20$next[0:0]$9652 - attribute \src "libresoc.v:170178.3-170195.6" - wire $2\r_busy$next[0:0]$9602 - attribute \src "libresoc.v:170209.3-170249.6" - wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9641 - attribute \src "libresoc.v:170209.3-170249.6" - wire $2\sr_op__imm_data__ok$5$next[0:0]$9642 - attribute \src "libresoc.v:170209.3-170249.6" - wire $2\sr_op__oe__oe$8$next[0:0]$9643 - attribute \src "libresoc.v:170209.3-170249.6" - wire $2\sr_op__oe__ok$9$next[0:0]$9644 - attribute \src "libresoc.v:170209.3-170249.6" - wire $2\sr_op__rc__ok$7$next[0:0]$9645 - attribute \src "libresoc.v:170209.3-170249.6" - wire $2\sr_op__rc__rc$6$next[0:0]$9646 - attribute \src "libresoc.v:170288.3-170306.6" - wire $2\xer_ca_ok$24$next[0:0]$9664 - attribute \src "libresoc.v:170070.18-170070.118" - wire $and$libresoc.v:170070$9549_Y + attribute \src "libresoc.v:170977.3-171017.6" + wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9556 + attribute \src "libresoc.v:170977.3-171017.6" + wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9557 + attribute \src "libresoc.v:170977.3-171017.6" + wire $1\sr_op__imm_data__ok$5$next[0:0]$9558 + attribute \src "libresoc.v:170977.3-171017.6" + wire width 2 $1\sr_op__input_carry$12$next[1:0]$9559 + attribute \src "libresoc.v:170977.3-171017.6" + wire $1\sr_op__input_cr$14$next[0:0]$9560 + attribute \src "libresoc.v:170977.3-171017.6" + wire width 32 $1\sr_op__insn$18$next[31:0]$9561 + attribute \src "libresoc.v:170977.3-171017.6" + wire width 7 $1\sr_op__insn_type$2$next[6:0]$9562 + attribute \src "libresoc.v:170977.3-171017.6" + wire $1\sr_op__invert_in$11$next[0:0]$9563 + attribute \src "libresoc.v:170977.3-171017.6" + wire $1\sr_op__is_32bit$16$next[0:0]$9564 + attribute \src "libresoc.v:170977.3-171017.6" + wire $1\sr_op__is_signed$17$next[0:0]$9565 + attribute \src "libresoc.v:170977.3-171017.6" + wire $1\sr_op__oe__oe$8$next[0:0]$9566 + attribute \src "libresoc.v:170977.3-171017.6" + wire $1\sr_op__oe__ok$9$next[0:0]$9567 + attribute \src "libresoc.v:170977.3-171017.6" + wire $1\sr_op__output_carry$13$next[0:0]$9568 + attribute \src "libresoc.v:170977.3-171017.6" + wire $1\sr_op__output_cr$15$next[0:0]$9569 + attribute \src "libresoc.v:170977.3-171017.6" + wire $1\sr_op__rc__ok$7$next[0:0]$9570 + attribute \src "libresoc.v:170977.3-171017.6" + wire $1\sr_op__rc__rc$6$next[0:0]$9571 + attribute \src "libresoc.v:170977.3-171017.6" + wire $1\sr_op__write_cr0$10$next[0:0]$9572 + attribute \src "libresoc.v:171056.3-171074.6" + wire width 2 $1\xer_ca$23$next[1:0]$9594 + attribute \src "libresoc.v:171056.3-171074.6" + wire $1\xer_ca_ok$24$next[0:0]$9595 + attribute \src "libresoc.v:171037.3-171055.6" + wire $2\cr_a_ok$22$next[0:0]$9590 + attribute \src "libresoc.v:171018.3-171036.6" + wire $2\o_ok$20$next[0:0]$9584 + attribute \src "libresoc.v:170946.3-170963.6" + wire $2\r_busy$next[0:0]$9534 + attribute \src "libresoc.v:170977.3-171017.6" + wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9573 + attribute \src "libresoc.v:170977.3-171017.6" + wire $2\sr_op__imm_data__ok$5$next[0:0]$9574 + attribute \src "libresoc.v:170977.3-171017.6" + wire $2\sr_op__oe__oe$8$next[0:0]$9575 + attribute \src "libresoc.v:170977.3-171017.6" + wire $2\sr_op__oe__ok$9$next[0:0]$9576 + attribute \src "libresoc.v:170977.3-171017.6" + wire $2\sr_op__rc__ok$7$next[0:0]$9577 + attribute \src "libresoc.v:170977.3-171017.6" + wire $2\sr_op__rc__rc$6$next[0:0]$9578 + attribute \src "libresoc.v:171056.3-171074.6" + wire $2\xer_ca_ok$24$next[0:0]$9596 + attribute \src "libresoc.v:170838.18-170838.118" + wire $and$libresoc.v:170838$9481_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 56 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 24 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 52 \cr_a$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 25 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 53 \cr_a_ok$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$74 - attribute \src "libresoc.v:169255.7-169255.15" + attribute \src "libresoc.v:170023.7-170023.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -348596,39 +315139,39 @@ module \pipe2$115 wire input 31 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 30 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 22 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 50 \o$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 23 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 51 \o_ok$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok$44 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -348886,13 +315429,13 @@ module \pipe2$115 wire \output_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__write_cr0$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ca$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o @@ -349324,32 +315867,32 @@ module \pipe2$115 wire \sr_op__write_cr0$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__write_cr0$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 28 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 54 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 29 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 55 \xer_ca_ok$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 26 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 27 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:170070$9549 + cell $and $and$libresoc.v:170838$9481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349357,16 +315900,16 @@ module \pipe2$115 parameter \Y_WIDTH 1 connect \A \p_valid_i$50 connect \B \p_ready_o - connect \Y $and$libresoc.v:170070$9549_Y + connect \Y $and$libresoc.v:170838$9481_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:170121.11-170124.4" + attribute \src "libresoc.v:170889.11-170892.4" cell \n$117 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:170125.16-170173.4" + attribute \src "libresoc.v:170893.16-170941.4" cell \output$118 \output connect \cr_a \output_cr_a connect \cr_a$21 \output_cr_a$45 @@ -349417,403 +315960,403 @@ module \pipe2$115 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:170174.11-170177.4" + attribute \src "libresoc.v:170942.11-170945.4" cell \p$116 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:169255.7-169255.20" - process $proc$libresoc.v:169255$9665 + attribute \src "libresoc.v:170023.7-170023.20" + process $proc$libresoc.v:170023$9597 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169266.13-169266.29" - process $proc$libresoc.v:169266$9666 + attribute \src "libresoc.v:170034.13-170034.29" + process $proc$libresoc.v:170034$9598 assign { } { } - assign $0\cr_a$21[3:0]$9667 4'0000 + assign $0\cr_a$21[3:0]$9599 4'0000 sync always sync init - update \cr_a$21 $0\cr_a$21[3:0]$9667 + update \cr_a$21 $0\cr_a$21[3:0]$9599 end - attribute \src "libresoc.v:169275.7-169275.26" - process $proc$libresoc.v:169275$9668 + attribute \src "libresoc.v:170043.7-170043.26" + process $proc$libresoc.v:170043$9600 assign { } { } - assign $0\cr_a_ok$22[0:0]$9669 1'0 + assign $0\cr_a_ok$22[0:0]$9601 1'0 sync always sync init - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9669 + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9601 end - attribute \src "libresoc.v:169286.13-169286.29" - process $proc$libresoc.v:169286$9670 + attribute \src "libresoc.v:170054.13-170054.29" + process $proc$libresoc.v:170054$9602 assign { } { } - assign $0\muxid$1[1:0]$9671 2'00 + assign $0\muxid$1[1:0]$9603 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9671 + update \muxid$1 $0\muxid$1[1:0]$9603 end - attribute \src "libresoc.v:169301.14-169301.43" - process $proc$libresoc.v:169301$9672 + attribute \src "libresoc.v:170069.14-170069.43" + process $proc$libresoc.v:170069$9604 assign { } { } - assign $0\o$19[63:0]$9673 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$19[63:0]$9605 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$19 $0\o$19[63:0]$9673 + update \o$19 $0\o$19[63:0]$9605 end - attribute \src "libresoc.v:169310.7-169310.23" - process $proc$libresoc.v:169310$9674 + attribute \src "libresoc.v:170078.7-170078.23" + process $proc$libresoc.v:170078$9606 assign { } { } - assign $0\o_ok$20[0:0]$9675 1'0 + assign $0\o_ok$20[0:0]$9607 1'0 sync always sync init - update \o_ok$20 $0\o_ok$20[0:0]$9675 + update \o_ok$20 $0\o_ok$20[0:0]$9607 end - attribute \src "libresoc.v:169606.7-169606.20" - process $proc$libresoc.v:169606$9676 + attribute \src "libresoc.v:170374.7-170374.20" + process $proc$libresoc.v:170374$9608 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:169643.14-169643.43" - process $proc$libresoc.v:169643$9677 + attribute \src "libresoc.v:170411.14-170411.43" + process $proc$libresoc.v:170411$9609 assign { } { } - assign $0\sr_op__fn_unit$3[13:0]$9678 14'00000000000000 + assign $0\sr_op__fn_unit$3[13:0]$9610 14'00000000000000 sync always sync init - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9678 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9610 end - attribute \src "libresoc.v:169667.14-169667.62" - process $proc$libresoc.v:169667$9679 + attribute \src "libresoc.v:170435.14-170435.62" + process $proc$libresoc.v:170435$9611 assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9680 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\sr_op__imm_data__data$4[63:0]$9612 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9680 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9612 end - attribute \src "libresoc.v:169676.7-169676.37" - process $proc$libresoc.v:169676$9681 + attribute \src "libresoc.v:170444.7-170444.37" + process $proc$libresoc.v:170444$9613 assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9682 1'0 + assign $0\sr_op__imm_data__ok$5[0:0]$9614 1'0 sync always sync init - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9682 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9614 end - attribute \src "libresoc.v:169693.13-169693.43" - process $proc$libresoc.v:169693$9683 + attribute \src "libresoc.v:170461.13-170461.43" + process $proc$libresoc.v:170461$9615 assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9684 2'00 + assign $0\sr_op__input_carry$12[1:0]$9616 2'00 sync always sync init - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9684 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9616 end - attribute \src "libresoc.v:169706.7-169706.34" - process $proc$libresoc.v:169706$9685 + attribute \src "libresoc.v:170474.7-170474.34" + process $proc$libresoc.v:170474$9617 assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9686 1'0 + assign $0\sr_op__input_cr$14[0:0]$9618 1'0 sync always sync init - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9686 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9618 end - attribute \src "libresoc.v:169715.14-169715.38" - process $proc$libresoc.v:169715$9687 + attribute \src "libresoc.v:170483.14-170483.38" + process $proc$libresoc.v:170483$9619 assign { } { } - assign $0\sr_op__insn$18[31:0]$9688 0 + assign $0\sr_op__insn$18[31:0]$9620 0 sync always sync init - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9688 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9620 end - attribute \src "libresoc.v:169874.13-169874.41" - process $proc$libresoc.v:169874$9689 + attribute \src "libresoc.v:170642.13-170642.41" + process $proc$libresoc.v:170642$9621 assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9690 7'0000000 + assign $0\sr_op__insn_type$2[6:0]$9622 7'0000000 sync always sync init - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9690 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9622 end - attribute \src "libresoc.v:169958.7-169958.35" - process $proc$libresoc.v:169958$9691 + attribute \src "libresoc.v:170726.7-170726.35" + process $proc$libresoc.v:170726$9623 assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9692 1'0 + assign $0\sr_op__invert_in$11[0:0]$9624 1'0 sync always sync init - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9692 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9624 end - attribute \src "libresoc.v:169967.7-169967.34" - process $proc$libresoc.v:169967$9693 + attribute \src "libresoc.v:170735.7-170735.34" + process $proc$libresoc.v:170735$9625 assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9694 1'0 + assign $0\sr_op__is_32bit$16[0:0]$9626 1'0 sync always sync init - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9694 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9626 end - attribute \src "libresoc.v:169976.7-169976.35" - process $proc$libresoc.v:169976$9695 + attribute \src "libresoc.v:170744.7-170744.35" + process $proc$libresoc.v:170744$9627 assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9696 1'0 + assign $0\sr_op__is_signed$17[0:0]$9628 1'0 sync always sync init - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9696 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9628 end - attribute \src "libresoc.v:169987.7-169987.31" - process $proc$libresoc.v:169987$9697 + attribute \src "libresoc.v:170755.7-170755.31" + process $proc$libresoc.v:170755$9629 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9698 1'0 + assign $0\sr_op__oe__oe$8[0:0]$9630 1'0 sync always sync init - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9698 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9630 end - attribute \src "libresoc.v:169996.7-169996.31" - process $proc$libresoc.v:169996$9699 + attribute \src "libresoc.v:170764.7-170764.31" + process $proc$libresoc.v:170764$9631 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9700 1'0 + assign $0\sr_op__oe__ok$9[0:0]$9632 1'0 sync always sync init - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9700 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9632 end - attribute \src "libresoc.v:170003.7-170003.38" - process $proc$libresoc.v:170003$9701 + attribute \src "libresoc.v:170771.7-170771.38" + process $proc$libresoc.v:170771$9633 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9702 1'0 + assign $0\sr_op__output_carry$13[0:0]$9634 1'0 sync always sync init - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9702 + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9634 end - attribute \src "libresoc.v:170012.7-170012.35" - process $proc$libresoc.v:170012$9703 + attribute \src "libresoc.v:170780.7-170780.35" + process $proc$libresoc.v:170780$9635 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9704 1'0 + assign $0\sr_op__output_cr$15[0:0]$9636 1'0 sync always sync init - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9704 + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9636 end - attribute \src "libresoc.v:170023.7-170023.31" - process $proc$libresoc.v:170023$9705 + attribute \src "libresoc.v:170791.7-170791.31" + process $proc$libresoc.v:170791$9637 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9706 1'0 + assign $0\sr_op__rc__ok$7[0:0]$9638 1'0 sync always sync init - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9706 + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9638 end - attribute \src "libresoc.v:170032.7-170032.31" - process $proc$libresoc.v:170032$9707 + attribute \src "libresoc.v:170800.7-170800.31" + process $proc$libresoc.v:170800$9639 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9708 1'0 + assign $0\sr_op__rc__rc$6[0:0]$9640 1'0 sync always sync init - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9708 + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9640 end - attribute \src "libresoc.v:170039.7-170039.35" - process $proc$libresoc.v:170039$9709 + attribute \src "libresoc.v:170807.7-170807.35" + process $proc$libresoc.v:170807$9641 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9710 1'0 + assign $0\sr_op__write_cr0$10[0:0]$9642 1'0 sync always sync init - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9710 + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9642 end - attribute \src "libresoc.v:170048.13-170048.31" - process $proc$libresoc.v:170048$9711 + attribute \src "libresoc.v:170816.13-170816.31" + process $proc$libresoc.v:170816$9643 assign { } { } - assign $0\xer_ca$23[1:0]$9712 2'00 + assign $0\xer_ca$23[1:0]$9644 2'00 sync always sync init - update \xer_ca$23 $0\xer_ca$23[1:0]$9712 + update \xer_ca$23 $0\xer_ca$23[1:0]$9644 end - attribute \src "libresoc.v:170057.7-170057.28" - process $proc$libresoc.v:170057$9713 + attribute \src "libresoc.v:170825.7-170825.28" + process $proc$libresoc.v:170825$9645 assign { } { } - assign $0\xer_ca_ok$24[0:0]$9714 1'0 + assign $0\xer_ca_ok$24[0:0]$9646 1'0 sync always sync init - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9714 + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9646 end - attribute \src "libresoc.v:170071.3-170072.37" - process $proc$libresoc.v:170071$9550 + attribute \src "libresoc.v:170839.3-170840.37" + process $proc$libresoc.v:170839$9482 assign { } { } - assign $0\xer_ca$23[1:0]$9551 \xer_ca$23$next + assign $0\xer_ca$23[1:0]$9483 \xer_ca$23$next sync posedge \coresync_clk - update \xer_ca$23 $0\xer_ca$23[1:0]$9551 + update \xer_ca$23 $0\xer_ca$23[1:0]$9483 end - attribute \src "libresoc.v:170073.3-170074.43" - process $proc$libresoc.v:170073$9552 + attribute \src "libresoc.v:170841.3-170842.43" + process $proc$libresoc.v:170841$9484 assign { } { } - assign $0\xer_ca_ok$24[0:0]$9553 \xer_ca_ok$24$next + assign $0\xer_ca_ok$24[0:0]$9485 \xer_ca_ok$24$next sync posedge \coresync_clk - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9553 + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9485 end - attribute \src "libresoc.v:170075.3-170076.33" - process $proc$libresoc.v:170075$9554 + attribute \src "libresoc.v:170843.3-170844.33" + process $proc$libresoc.v:170843$9486 assign { } { } - assign $0\cr_a$21[3:0]$9555 \cr_a$21$next + assign $0\cr_a$21[3:0]$9487 \cr_a$21$next sync posedge \coresync_clk - update \cr_a$21 $0\cr_a$21[3:0]$9555 + update \cr_a$21 $0\cr_a$21[3:0]$9487 end - attribute \src "libresoc.v:170077.3-170078.39" - process $proc$libresoc.v:170077$9556 + attribute \src "libresoc.v:170845.3-170846.39" + process $proc$libresoc.v:170845$9488 assign { } { } - assign $0\cr_a_ok$22[0:0]$9557 \cr_a_ok$22$next + assign $0\cr_a_ok$22[0:0]$9489 \cr_a_ok$22$next sync posedge \coresync_clk - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9557 + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9489 end - attribute \src "libresoc.v:170079.3-170080.27" - process $proc$libresoc.v:170079$9558 + attribute \src "libresoc.v:170847.3-170848.27" + process $proc$libresoc.v:170847$9490 assign { } { } - assign $0\o$19[63:0]$9559 \o$19$next + assign $0\o$19[63:0]$9491 \o$19$next sync posedge \coresync_clk - update \o$19 $0\o$19[63:0]$9559 + update \o$19 $0\o$19[63:0]$9491 end - attribute \src "libresoc.v:170081.3-170082.33" - process $proc$libresoc.v:170081$9560 + attribute \src "libresoc.v:170849.3-170850.33" + process $proc$libresoc.v:170849$9492 assign { } { } - assign $0\o_ok$20[0:0]$9561 \o_ok$20$next + assign $0\o_ok$20[0:0]$9493 \o_ok$20$next sync posedge \coresync_clk - update \o_ok$20 $0\o_ok$20[0:0]$9561 + update \o_ok$20 $0\o_ok$20[0:0]$9493 end - attribute \src "libresoc.v:170083.3-170084.55" - process $proc$libresoc.v:170083$9562 + attribute \src "libresoc.v:170851.3-170852.55" + process $proc$libresoc.v:170851$9494 assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9563 \sr_op__insn_type$2$next + assign $0\sr_op__insn_type$2[6:0]$9495 \sr_op__insn_type$2$next sync posedge \coresync_clk - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9563 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9495 end - attribute \src "libresoc.v:170085.3-170086.51" - process $proc$libresoc.v:170085$9564 + attribute \src "libresoc.v:170853.3-170854.51" + process $proc$libresoc.v:170853$9496 assign { } { } - assign $0\sr_op__fn_unit$3[13:0]$9565 \sr_op__fn_unit$3$next + assign $0\sr_op__fn_unit$3[13:0]$9497 \sr_op__fn_unit$3$next sync posedge \coresync_clk - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9565 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9497 end - attribute \src "libresoc.v:170087.3-170088.65" - process $proc$libresoc.v:170087$9566 + attribute \src "libresoc.v:170855.3-170856.65" + process $proc$libresoc.v:170855$9498 assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9567 \sr_op__imm_data__data$4$next + assign $0\sr_op__imm_data__data$4[63:0]$9499 \sr_op__imm_data__data$4$next sync posedge \coresync_clk - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9567 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9499 end - attribute \src "libresoc.v:170089.3-170090.61" - process $proc$libresoc.v:170089$9568 + attribute \src "libresoc.v:170857.3-170858.61" + process $proc$libresoc.v:170857$9500 assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9569 \sr_op__imm_data__ok$5$next + assign $0\sr_op__imm_data__ok$5[0:0]$9501 \sr_op__imm_data__ok$5$next sync posedge \coresync_clk - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9569 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9501 end - attribute \src "libresoc.v:170091.3-170092.49" - process $proc$libresoc.v:170091$9570 + attribute \src "libresoc.v:170859.3-170860.49" + process $proc$libresoc.v:170859$9502 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9571 \sr_op__rc__rc$6$next + assign $0\sr_op__rc__rc$6[0:0]$9503 \sr_op__rc__rc$6$next sync posedge \coresync_clk - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9571 + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9503 end - attribute \src "libresoc.v:170093.3-170094.49" - process $proc$libresoc.v:170093$9572 + attribute \src "libresoc.v:170861.3-170862.49" + process $proc$libresoc.v:170861$9504 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9573 \sr_op__rc__ok$7$next + assign $0\sr_op__rc__ok$7[0:0]$9505 \sr_op__rc__ok$7$next sync posedge \coresync_clk - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9573 + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9505 end - attribute \src "libresoc.v:170095.3-170096.49" - process $proc$libresoc.v:170095$9574 + attribute \src "libresoc.v:170863.3-170864.49" + process $proc$libresoc.v:170863$9506 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9575 \sr_op__oe__oe$8$next + assign $0\sr_op__oe__oe$8[0:0]$9507 \sr_op__oe__oe$8$next sync posedge \coresync_clk - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9575 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9507 end - attribute \src "libresoc.v:170097.3-170098.49" - process $proc$libresoc.v:170097$9576 + attribute \src "libresoc.v:170865.3-170866.49" + process $proc$libresoc.v:170865$9508 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9577 \sr_op__oe__ok$9$next + assign $0\sr_op__oe__ok$9[0:0]$9509 \sr_op__oe__ok$9$next sync posedge \coresync_clk - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9577 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9509 end - attribute \src "libresoc.v:170099.3-170100.57" - process $proc$libresoc.v:170099$9578 + attribute \src "libresoc.v:170867.3-170868.57" + process $proc$libresoc.v:170867$9510 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9579 \sr_op__write_cr0$10$next + assign $0\sr_op__write_cr0$10[0:0]$9511 \sr_op__write_cr0$10$next sync posedge \coresync_clk - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9579 + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9511 end - attribute \src "libresoc.v:170101.3-170102.57" - process $proc$libresoc.v:170101$9580 + attribute \src "libresoc.v:170869.3-170870.57" + process $proc$libresoc.v:170869$9512 assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9581 \sr_op__invert_in$11$next + assign $0\sr_op__invert_in$11[0:0]$9513 \sr_op__invert_in$11$next sync posedge \coresync_clk - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9581 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9513 end - attribute \src "libresoc.v:170103.3-170104.61" - process $proc$libresoc.v:170103$9582 + attribute \src "libresoc.v:170871.3-170872.61" + process $proc$libresoc.v:170871$9514 assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9583 \sr_op__input_carry$12$next + assign $0\sr_op__input_carry$12[1:0]$9515 \sr_op__input_carry$12$next sync posedge \coresync_clk - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9583 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9515 end - attribute \src "libresoc.v:170105.3-170106.63" - process $proc$libresoc.v:170105$9584 + attribute \src "libresoc.v:170873.3-170874.63" + process $proc$libresoc.v:170873$9516 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9585 \sr_op__output_carry$13$next + assign $0\sr_op__output_carry$13[0:0]$9517 \sr_op__output_carry$13$next sync posedge \coresync_clk - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9585 + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9517 end - attribute \src "libresoc.v:170107.3-170108.55" - process $proc$libresoc.v:170107$9586 + attribute \src "libresoc.v:170875.3-170876.55" + process $proc$libresoc.v:170875$9518 assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9587 \sr_op__input_cr$14$next + assign $0\sr_op__input_cr$14[0:0]$9519 \sr_op__input_cr$14$next sync posedge \coresync_clk - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9587 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9519 end - attribute \src "libresoc.v:170109.3-170110.57" - process $proc$libresoc.v:170109$9588 + attribute \src "libresoc.v:170877.3-170878.57" + process $proc$libresoc.v:170877$9520 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9589 \sr_op__output_cr$15$next + assign $0\sr_op__output_cr$15[0:0]$9521 \sr_op__output_cr$15$next sync posedge \coresync_clk - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9589 + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9521 end - attribute \src "libresoc.v:170111.3-170112.55" - process $proc$libresoc.v:170111$9590 + attribute \src "libresoc.v:170879.3-170880.55" + process $proc$libresoc.v:170879$9522 assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9591 \sr_op__is_32bit$16$next + assign $0\sr_op__is_32bit$16[0:0]$9523 \sr_op__is_32bit$16$next sync posedge \coresync_clk - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9591 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9523 end - attribute \src "libresoc.v:170113.3-170114.57" - process $proc$libresoc.v:170113$9592 + attribute \src "libresoc.v:170881.3-170882.57" + process $proc$libresoc.v:170881$9524 assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9593 \sr_op__is_signed$17$next + assign $0\sr_op__is_signed$17[0:0]$9525 \sr_op__is_signed$17$next sync posedge \coresync_clk - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9593 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9525 end - attribute \src "libresoc.v:170115.3-170116.47" - process $proc$libresoc.v:170115$9594 + attribute \src "libresoc.v:170883.3-170884.47" + process $proc$libresoc.v:170883$9526 assign { } { } - assign $0\sr_op__insn$18[31:0]$9595 \sr_op__insn$18$next + assign $0\sr_op__insn$18[31:0]$9527 \sr_op__insn$18$next sync posedge \coresync_clk - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9595 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9527 end - attribute \src "libresoc.v:170117.3-170118.33" - process $proc$libresoc.v:170117$9596 + attribute \src "libresoc.v:170885.3-170886.33" + process $proc$libresoc.v:170885$9528 assign { } { } - assign $0\muxid$1[1:0]$9597 \muxid$1$next + assign $0\muxid$1[1:0]$9529 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9597 + update \muxid$1 $0\muxid$1[1:0]$9529 end - attribute \src "libresoc.v:170119.3-170120.29" - process $proc$libresoc.v:170119$9598 + attribute \src "libresoc.v:170887.3-170888.29" + process $proc$libresoc.v:170887$9530 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:170178.3-170195.6" - process $proc$libresoc.v:170178$9599 + attribute \src "libresoc.v:170946.3-170963.6" + process $proc$libresoc.v:170946$9531 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9600 $2\r_busy$next[0:0]$9602 - attribute \src "libresoc.v:170179.5-170179.29" + assign $0\r_busy$next[0:0]$9532 $2\r_busy$next[0:0]$9534 + attribute \src "libresoc.v:170947.5-170947.29" switch \initial - attribute \src "libresoc.v:170179.9-170179.17" + attribute \src "libresoc.v:170947.9-170947.17" case 1'1 case end @@ -349822,34 +316365,34 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9601 1'1 + assign $1\r_busy$next[0:0]$9533 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9601 1'0 + assign $1\r_busy$next[0:0]$9533 1'0 case - assign $1\r_busy$next[0:0]$9601 \r_busy + assign $1\r_busy$next[0:0]$9533 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9602 1'0 + assign $2\r_busy$next[0:0]$9534 1'0 case - assign $2\r_busy$next[0:0]$9602 $1\r_busy$next[0:0]$9601 + assign $2\r_busy$next[0:0]$9534 $1\r_busy$next[0:0]$9533 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9600 + update \r_busy$next $0\r_busy$next[0:0]$9532 end - attribute \src "libresoc.v:170196.3-170208.6" - process $proc$libresoc.v:170196$9603 + attribute \src "libresoc.v:170964.3-170976.6" + process $proc$libresoc.v:170964$9535 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9604 $1\muxid$1$next[1:0]$9605 - attribute \src "libresoc.v:170197.5-170197.29" + assign $0\muxid$1$next[1:0]$9536 $1\muxid$1$next[1:0]$9537 + attribute \src "libresoc.v:170965.5-170965.29" switch \initial - attribute \src "libresoc.v:170197.9-170197.17" + attribute \src "libresoc.v:170965.9-170965.17" case 1'1 case end @@ -349858,19 +316401,19 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9605 \muxid$53 + assign $1\muxid$1$next[1:0]$9537 \muxid$53 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9605 \muxid$53 + assign $1\muxid$1$next[1:0]$9537 \muxid$53 case - assign $1\muxid$1$next[1:0]$9605 \muxid$1 + assign $1\muxid$1$next[1:0]$9537 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9604 + update \muxid$1$next $0\muxid$1$next[1:0]$9536 end - attribute \src "libresoc.v:170209.3-170249.6" - process $proc$libresoc.v:170209$9606 + attribute \src "libresoc.v:170977.3-171017.6" + process $proc$libresoc.v:170977$9538 assign { } { } assign { } { } assign { } { } @@ -349905,32 +316448,32 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign $0\sr_op__fn_unit$3$next[13:0]$9607 $1\sr_op__fn_unit$3$next[13:0]$9624 + assign $0\sr_op__fn_unit$3$next[13:0]$9539 $1\sr_op__fn_unit$3$next[13:0]$9556 assign { } { } assign { } { } - assign $0\sr_op__input_carry$12$next[1:0]$9610 $1\sr_op__input_carry$12$next[1:0]$9627 - assign $0\sr_op__input_cr$14$next[0:0]$9611 $1\sr_op__input_cr$14$next[0:0]$9628 - assign $0\sr_op__insn$18$next[31:0]$9612 $1\sr_op__insn$18$next[31:0]$9629 - assign $0\sr_op__insn_type$2$next[6:0]$9613 $1\sr_op__insn_type$2$next[6:0]$9630 - assign $0\sr_op__invert_in$11$next[0:0]$9614 $1\sr_op__invert_in$11$next[0:0]$9631 - assign $0\sr_op__is_32bit$16$next[0:0]$9615 $1\sr_op__is_32bit$16$next[0:0]$9632 - assign $0\sr_op__is_signed$17$next[0:0]$9616 $1\sr_op__is_signed$17$next[0:0]$9633 + assign $0\sr_op__input_carry$12$next[1:0]$9542 $1\sr_op__input_carry$12$next[1:0]$9559 + assign $0\sr_op__input_cr$14$next[0:0]$9543 $1\sr_op__input_cr$14$next[0:0]$9560 + assign $0\sr_op__insn$18$next[31:0]$9544 $1\sr_op__insn$18$next[31:0]$9561 + assign $0\sr_op__insn_type$2$next[6:0]$9545 $1\sr_op__insn_type$2$next[6:0]$9562 + assign $0\sr_op__invert_in$11$next[0:0]$9546 $1\sr_op__invert_in$11$next[0:0]$9563 + assign $0\sr_op__is_32bit$16$next[0:0]$9547 $1\sr_op__is_32bit$16$next[0:0]$9564 + assign $0\sr_op__is_signed$17$next[0:0]$9548 $1\sr_op__is_signed$17$next[0:0]$9565 assign { } { } assign { } { } - assign $0\sr_op__output_carry$13$next[0:0]$9619 $1\sr_op__output_carry$13$next[0:0]$9636 - assign $0\sr_op__output_cr$15$next[0:0]$9620 $1\sr_op__output_cr$15$next[0:0]$9637 + assign $0\sr_op__output_carry$13$next[0:0]$9551 $1\sr_op__output_carry$13$next[0:0]$9568 + assign $0\sr_op__output_cr$15$next[0:0]$9552 $1\sr_op__output_cr$15$next[0:0]$9569 assign { } { } assign { } { } - assign $0\sr_op__write_cr0$10$next[0:0]$9623 $1\sr_op__write_cr0$10$next[0:0]$9640 - assign $0\sr_op__imm_data__data$4$next[63:0]$9608 $2\sr_op__imm_data__data$4$next[63:0]$9641 - assign $0\sr_op__imm_data__ok$5$next[0:0]$9609 $2\sr_op__imm_data__ok$5$next[0:0]$9642 - assign $0\sr_op__oe__oe$8$next[0:0]$9617 $2\sr_op__oe__oe$8$next[0:0]$9643 - assign $0\sr_op__oe__ok$9$next[0:0]$9618 $2\sr_op__oe__ok$9$next[0:0]$9644 - assign $0\sr_op__rc__ok$7$next[0:0]$9621 $2\sr_op__rc__ok$7$next[0:0]$9645 - assign $0\sr_op__rc__rc$6$next[0:0]$9622 $2\sr_op__rc__rc$6$next[0:0]$9646 - attribute \src "libresoc.v:170210.5-170210.29" + assign $0\sr_op__write_cr0$10$next[0:0]$9555 $1\sr_op__write_cr0$10$next[0:0]$9572 + assign $0\sr_op__imm_data__data$4$next[63:0]$9540 $2\sr_op__imm_data__data$4$next[63:0]$9573 + assign $0\sr_op__imm_data__ok$5$next[0:0]$9541 $2\sr_op__imm_data__ok$5$next[0:0]$9574 + assign $0\sr_op__oe__oe$8$next[0:0]$9549 $2\sr_op__oe__oe$8$next[0:0]$9575 + assign $0\sr_op__oe__ok$9$next[0:0]$9550 $2\sr_op__oe__ok$9$next[0:0]$9576 + assign $0\sr_op__rc__ok$7$next[0:0]$9553 $2\sr_op__rc__ok$7$next[0:0]$9577 + assign $0\sr_op__rc__rc$6$next[0:0]$9554 $2\sr_op__rc__rc$6$next[0:0]$9578 + attribute \src "libresoc.v:170978.5-170978.29" switch \initial - attribute \src "libresoc.v:170210.9-170210.17" + attribute \src "libresoc.v:170978.9-170978.17" case 1'1 case end @@ -349955,7 +316498,7 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9629 $1\sr_op__is_signed$17$next[0:0]$9633 $1\sr_op__is_32bit$16$next[0:0]$9632 $1\sr_op__output_cr$15$next[0:0]$9637 $1\sr_op__input_cr$14$next[0:0]$9628 $1\sr_op__output_carry$13$next[0:0]$9636 $1\sr_op__input_carry$12$next[1:0]$9627 $1\sr_op__invert_in$11$next[0:0]$9631 $1\sr_op__write_cr0$10$next[0:0]$9640 $1\sr_op__oe__ok$9$next[0:0]$9635 $1\sr_op__oe__oe$8$next[0:0]$9634 $1\sr_op__rc__ok$7$next[0:0]$9638 $1\sr_op__rc__rc$6$next[0:0]$9639 $1\sr_op__imm_data__ok$5$next[0:0]$9626 $1\sr_op__imm_data__data$4$next[63:0]$9625 $1\sr_op__fn_unit$3$next[13:0]$9624 $1\sr_op__insn_type$2$next[6:0]$9630 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign { $1\sr_op__insn$18$next[31:0]$9561 $1\sr_op__is_signed$17$next[0:0]$9565 $1\sr_op__is_32bit$16$next[0:0]$9564 $1\sr_op__output_cr$15$next[0:0]$9569 $1\sr_op__input_cr$14$next[0:0]$9560 $1\sr_op__output_carry$13$next[0:0]$9568 $1\sr_op__input_carry$12$next[1:0]$9559 $1\sr_op__invert_in$11$next[0:0]$9563 $1\sr_op__write_cr0$10$next[0:0]$9572 $1\sr_op__oe__ok$9$next[0:0]$9567 $1\sr_op__oe__oe$8$next[0:0]$9566 $1\sr_op__rc__ok$7$next[0:0]$9570 $1\sr_op__rc__rc$6$next[0:0]$9571 $1\sr_op__imm_data__ok$5$next[0:0]$9558 $1\sr_op__imm_data__data$4$next[63:0]$9557 $1\sr_op__fn_unit$3$next[13:0]$9556 $1\sr_op__insn_type$2$next[6:0]$9562 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -349975,25 +316518,25 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9629 $1\sr_op__is_signed$17$next[0:0]$9633 $1\sr_op__is_32bit$16$next[0:0]$9632 $1\sr_op__output_cr$15$next[0:0]$9637 $1\sr_op__input_cr$14$next[0:0]$9628 $1\sr_op__output_carry$13$next[0:0]$9636 $1\sr_op__input_carry$12$next[1:0]$9627 $1\sr_op__invert_in$11$next[0:0]$9631 $1\sr_op__write_cr0$10$next[0:0]$9640 $1\sr_op__oe__ok$9$next[0:0]$9635 $1\sr_op__oe__oe$8$next[0:0]$9634 $1\sr_op__rc__ok$7$next[0:0]$9638 $1\sr_op__rc__rc$6$next[0:0]$9639 $1\sr_op__imm_data__ok$5$next[0:0]$9626 $1\sr_op__imm_data__data$4$next[63:0]$9625 $1\sr_op__fn_unit$3$next[13:0]$9624 $1\sr_op__insn_type$2$next[6:0]$9630 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign { $1\sr_op__insn$18$next[31:0]$9561 $1\sr_op__is_signed$17$next[0:0]$9565 $1\sr_op__is_32bit$16$next[0:0]$9564 $1\sr_op__output_cr$15$next[0:0]$9569 $1\sr_op__input_cr$14$next[0:0]$9560 $1\sr_op__output_carry$13$next[0:0]$9568 $1\sr_op__input_carry$12$next[1:0]$9559 $1\sr_op__invert_in$11$next[0:0]$9563 $1\sr_op__write_cr0$10$next[0:0]$9572 $1\sr_op__oe__ok$9$next[0:0]$9567 $1\sr_op__oe__oe$8$next[0:0]$9566 $1\sr_op__rc__ok$7$next[0:0]$9570 $1\sr_op__rc__rc$6$next[0:0]$9571 $1\sr_op__imm_data__ok$5$next[0:0]$9558 $1\sr_op__imm_data__data$4$next[63:0]$9557 $1\sr_op__fn_unit$3$next[13:0]$9556 $1\sr_op__insn_type$2$next[6:0]$9562 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } case - assign $1\sr_op__fn_unit$3$next[13:0]$9624 \sr_op__fn_unit$3 - assign $1\sr_op__imm_data__data$4$next[63:0]$9625 \sr_op__imm_data__data$4 - assign $1\sr_op__imm_data__ok$5$next[0:0]$9626 \sr_op__imm_data__ok$5 - assign $1\sr_op__input_carry$12$next[1:0]$9627 \sr_op__input_carry$12 - assign $1\sr_op__input_cr$14$next[0:0]$9628 \sr_op__input_cr$14 - assign $1\sr_op__insn$18$next[31:0]$9629 \sr_op__insn$18 - assign $1\sr_op__insn_type$2$next[6:0]$9630 \sr_op__insn_type$2 - assign $1\sr_op__invert_in$11$next[0:0]$9631 \sr_op__invert_in$11 - assign $1\sr_op__is_32bit$16$next[0:0]$9632 \sr_op__is_32bit$16 - assign $1\sr_op__is_signed$17$next[0:0]$9633 \sr_op__is_signed$17 - assign $1\sr_op__oe__oe$8$next[0:0]$9634 \sr_op__oe__oe$8 - assign $1\sr_op__oe__ok$9$next[0:0]$9635 \sr_op__oe__ok$9 - assign $1\sr_op__output_carry$13$next[0:0]$9636 \sr_op__output_carry$13 - assign $1\sr_op__output_cr$15$next[0:0]$9637 \sr_op__output_cr$15 - assign $1\sr_op__rc__ok$7$next[0:0]$9638 \sr_op__rc__ok$7 - assign $1\sr_op__rc__rc$6$next[0:0]$9639 \sr_op__rc__rc$6 - assign $1\sr_op__write_cr0$10$next[0:0]$9640 \sr_op__write_cr0$10 + assign $1\sr_op__fn_unit$3$next[13:0]$9556 \sr_op__fn_unit$3 + assign $1\sr_op__imm_data__data$4$next[63:0]$9557 \sr_op__imm_data__data$4 + assign $1\sr_op__imm_data__ok$5$next[0:0]$9558 \sr_op__imm_data__ok$5 + assign $1\sr_op__input_carry$12$next[1:0]$9559 \sr_op__input_carry$12 + assign $1\sr_op__input_cr$14$next[0:0]$9560 \sr_op__input_cr$14 + assign $1\sr_op__insn$18$next[31:0]$9561 \sr_op__insn$18 + assign $1\sr_op__insn_type$2$next[6:0]$9562 \sr_op__insn_type$2 + assign $1\sr_op__invert_in$11$next[0:0]$9563 \sr_op__invert_in$11 + assign $1\sr_op__is_32bit$16$next[0:0]$9564 \sr_op__is_32bit$16 + assign $1\sr_op__is_signed$17$next[0:0]$9565 \sr_op__is_signed$17 + assign $1\sr_op__oe__oe$8$next[0:0]$9566 \sr_op__oe__oe$8 + assign $1\sr_op__oe__ok$9$next[0:0]$9567 \sr_op__oe__ok$9 + assign $1\sr_op__output_carry$13$next[0:0]$9568 \sr_op__output_carry$13 + assign $1\sr_op__output_cr$15$next[0:0]$9569 \sr_op__output_cr$15 + assign $1\sr_op__rc__ok$7$next[0:0]$9570 \sr_op__rc__ok$7 + assign $1\sr_op__rc__rc$6$next[0:0]$9571 \sr_op__rc__rc$6 + assign $1\sr_op__write_cr0$10$next[0:0]$9572 \sr_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -350005,51 +316548,51 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign $2\sr_op__imm_data__data$4$next[63:0]$9641 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9642 1'0 - assign $2\sr_op__rc__rc$6$next[0:0]$9646 1'0 - assign $2\sr_op__rc__ok$7$next[0:0]$9645 1'0 - assign $2\sr_op__oe__oe$8$next[0:0]$9643 1'0 - assign $2\sr_op__oe__ok$9$next[0:0]$9644 1'0 + assign $2\sr_op__imm_data__data$4$next[63:0]$9573 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9574 1'0 + assign $2\sr_op__rc__rc$6$next[0:0]$9578 1'0 + assign $2\sr_op__rc__ok$7$next[0:0]$9577 1'0 + assign $2\sr_op__oe__oe$8$next[0:0]$9575 1'0 + assign $2\sr_op__oe__ok$9$next[0:0]$9576 1'0 case - assign $2\sr_op__imm_data__data$4$next[63:0]$9641 $1\sr_op__imm_data__data$4$next[63:0]$9625 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9642 $1\sr_op__imm_data__ok$5$next[0:0]$9626 - assign $2\sr_op__oe__oe$8$next[0:0]$9643 $1\sr_op__oe__oe$8$next[0:0]$9634 - assign $2\sr_op__oe__ok$9$next[0:0]$9644 $1\sr_op__oe__ok$9$next[0:0]$9635 - assign $2\sr_op__rc__ok$7$next[0:0]$9645 $1\sr_op__rc__ok$7$next[0:0]$9638 - assign $2\sr_op__rc__rc$6$next[0:0]$9646 $1\sr_op__rc__rc$6$next[0:0]$9639 + assign $2\sr_op__imm_data__data$4$next[63:0]$9573 $1\sr_op__imm_data__data$4$next[63:0]$9557 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9574 $1\sr_op__imm_data__ok$5$next[0:0]$9558 + assign $2\sr_op__oe__oe$8$next[0:0]$9575 $1\sr_op__oe__oe$8$next[0:0]$9566 + assign $2\sr_op__oe__ok$9$next[0:0]$9576 $1\sr_op__oe__ok$9$next[0:0]$9567 + assign $2\sr_op__rc__ok$7$next[0:0]$9577 $1\sr_op__rc__ok$7$next[0:0]$9570 + assign $2\sr_op__rc__rc$6$next[0:0]$9578 $1\sr_op__rc__rc$6$next[0:0]$9571 end sync always - update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[13:0]$9607 - update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9608 - update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9609 - update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9610 - update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9611 - update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9612 - update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9613 - update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9614 - update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9615 - update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9616 - update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9617 - update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9618 - update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9619 - update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9620 - update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9621 - update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9622 - update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9623 + update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[13:0]$9539 + update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9540 + update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9541 + update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9542 + update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9543 + update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9544 + update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9545 + update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9546 + update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9547 + update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9548 + update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9549 + update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9550 + update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9551 + update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9552 + update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9553 + update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9554 + update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9555 end - attribute \src "libresoc.v:170250.3-170268.6" - process $proc$libresoc.v:170250$9647 + attribute \src "libresoc.v:171018.3-171036.6" + process $proc$libresoc.v:171018$9579 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$19$next[63:0]$9648 $1\o$19$next[63:0]$9650 + assign $0\o$19$next[63:0]$9580 $1\o$19$next[63:0]$9582 assign { } { } - assign $0\o_ok$20$next[0:0]$9649 $2\o_ok$20$next[0:0]$9652 - attribute \src "libresoc.v:170251.5-170251.29" + assign $0\o_ok$20$next[0:0]$9581 $2\o_ok$20$next[0:0]$9584 + attribute \src "libresoc.v:171019.5-171019.29" switch \initial - attribute \src "libresoc.v:170251.9-170251.17" + attribute \src "libresoc.v:171019.9-171019.17" case 1'1 case end @@ -350059,41 +316602,41 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$20$next[0:0]$9651 $1\o$19$next[63:0]$9650 } { \o_ok$72 \o$71 } + assign { $1\o_ok$20$next[0:0]$9583 $1\o$19$next[63:0]$9582 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$20$next[0:0]$9651 $1\o$19$next[63:0]$9650 } { \o_ok$72 \o$71 } + assign { $1\o_ok$20$next[0:0]$9583 $1\o$19$next[63:0]$9582 } { \o_ok$72 \o$71 } case - assign $1\o$19$next[63:0]$9650 \o$19 - assign $1\o_ok$20$next[0:0]$9651 \o_ok$20 + assign $1\o$19$next[63:0]$9582 \o$19 + assign $1\o_ok$20$next[0:0]$9583 \o_ok$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$20$next[0:0]$9652 1'0 + assign $2\o_ok$20$next[0:0]$9584 1'0 case - assign $2\o_ok$20$next[0:0]$9652 $1\o_ok$20$next[0:0]$9651 + assign $2\o_ok$20$next[0:0]$9584 $1\o_ok$20$next[0:0]$9583 end sync always - update \o$19$next $0\o$19$next[63:0]$9648 - update \o_ok$20$next $0\o_ok$20$next[0:0]$9649 + update \o$19$next $0\o$19$next[63:0]$9580 + update \o_ok$20$next $0\o_ok$20$next[0:0]$9581 end - attribute \src "libresoc.v:170269.3-170287.6" - process $proc$libresoc.v:170269$9653 + attribute \src "libresoc.v:171037.3-171055.6" + process $proc$libresoc.v:171037$9585 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$21$next[3:0]$9654 $1\cr_a$21$next[3:0]$9656 + assign $0\cr_a$21$next[3:0]$9586 $1\cr_a$21$next[3:0]$9588 assign { } { } - assign $0\cr_a_ok$22$next[0:0]$9655 $2\cr_a_ok$22$next[0:0]$9658 - attribute \src "libresoc.v:170270.5-170270.29" + assign $0\cr_a_ok$22$next[0:0]$9587 $2\cr_a_ok$22$next[0:0]$9590 + attribute \src "libresoc.v:171038.5-171038.29" switch \initial - attribute \src "libresoc.v:170270.9-170270.17" + attribute \src "libresoc.v:171038.9-171038.17" case 1'1 case end @@ -350103,41 +316646,41 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9657 $1\cr_a$21$next[3:0]$9656 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$22$next[0:0]$9589 $1\cr_a$21$next[3:0]$9588 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9657 $1\cr_a$21$next[3:0]$9656 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$22$next[0:0]$9589 $1\cr_a$21$next[3:0]$9588 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\cr_a$21$next[3:0]$9656 \cr_a$21 - assign $1\cr_a_ok$22$next[0:0]$9657 \cr_a_ok$22 + assign $1\cr_a$21$next[3:0]$9588 \cr_a$21 + assign $1\cr_a_ok$22$next[0:0]$9589 \cr_a_ok$22 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$22$next[0:0]$9658 1'0 + assign $2\cr_a_ok$22$next[0:0]$9590 1'0 case - assign $2\cr_a_ok$22$next[0:0]$9658 $1\cr_a_ok$22$next[0:0]$9657 + assign $2\cr_a_ok$22$next[0:0]$9590 $1\cr_a_ok$22$next[0:0]$9589 end sync always - update \cr_a$21$next $0\cr_a$21$next[3:0]$9654 - update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9655 + update \cr_a$21$next $0\cr_a$21$next[3:0]$9586 + update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9587 end - attribute \src "libresoc.v:170288.3-170306.6" - process $proc$libresoc.v:170288$9659 + attribute \src "libresoc.v:171056.3-171074.6" + process $proc$libresoc.v:171056$9591 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$23$next[1:0]$9660 $1\xer_ca$23$next[1:0]$9662 + assign $0\xer_ca$23$next[1:0]$9592 $1\xer_ca$23$next[1:0]$9594 assign { } { } - assign $0\xer_ca_ok$24$next[0:0]$9661 $2\xer_ca_ok$24$next[0:0]$9664 - attribute \src "libresoc.v:170289.5-170289.29" + assign $0\xer_ca_ok$24$next[0:0]$9593 $2\xer_ca_ok$24$next[0:0]$9596 + attribute \src "libresoc.v:171057.5-171057.29" switch \initial - attribute \src "libresoc.v:170289.9-170289.17" + attribute \src "libresoc.v:171057.9-171057.17" case 1'1 case end @@ -350147,30 +316690,30 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9663 $1\xer_ca$23$next[1:0]$9662 } { \xer_ca_ok$76 \xer_ca$75 } + assign { $1\xer_ca_ok$24$next[0:0]$9595 $1\xer_ca$23$next[1:0]$9594 } { \xer_ca_ok$76 \xer_ca$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9663 $1\xer_ca$23$next[1:0]$9662 } { \xer_ca_ok$76 \xer_ca$75 } + assign { $1\xer_ca_ok$24$next[0:0]$9595 $1\xer_ca$23$next[1:0]$9594 } { \xer_ca_ok$76 \xer_ca$75 } case - assign $1\xer_ca$23$next[1:0]$9662 \xer_ca$23 - assign $1\xer_ca_ok$24$next[0:0]$9663 \xer_ca_ok$24 + assign $1\xer_ca$23$next[1:0]$9594 \xer_ca$23 + assign $1\xer_ca_ok$24$next[0:0]$9595 \xer_ca_ok$24 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$24$next[0:0]$9664 1'0 + assign $2\xer_ca_ok$24$next[0:0]$9596 1'0 case - assign $2\xer_ca_ok$24$next[0:0]$9664 $1\xer_ca_ok$24$next[0:0]$9663 + assign $2\xer_ca_ok$24$next[0:0]$9596 $1\xer_ca_ok$24$next[0:0]$9595 end sync always - update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9660 - update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9661 + update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9592 + update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9593 end - connect \$51 $and$libresoc.v:170070$9549_Y + connect \$51 $and$libresoc.v:170838$9481_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } @@ -350188,258 +316731,258 @@ module \pipe2$115 connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:170327.1-171291.10" +attribute \src "libresoc.v:171095.1-172059.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" attribute \generator "nMigen" module \pipe2$35 - attribute \src "libresoc.v:171197.3-171215.6" - wire width 64 $0\fast1$11$next[63:0]$9783 - attribute \src "libresoc.v:171052.3-171053.35" - wire width 64 $0\fast1$11[63:0]$9724 - attribute \src "libresoc.v:170339.14-170339.47" - wire width 64 $0\fast1$11[63:0]$9807 - attribute \src "libresoc.v:171197.3-171215.6" - wire $0\fast1_ok$next[0:0]$9782 - attribute \src "libresoc.v:171054.3-171055.33" + attribute \src "libresoc.v:171965.3-171983.6" + wire width 64 $0\fast1$11$next[63:0]$9715 + attribute \src "libresoc.v:171808.3-171809.35" + wire width 64 $0\fast1$11[63:0]$9649 + attribute \src "libresoc.v:171107.14-171107.47" + wire width 64 $0\fast1$11[63:0]$9739 + attribute \src "libresoc.v:171965.3-171983.6" + wire $0\fast1_ok$next[0:0]$9714 + attribute \src "libresoc.v:171810.3-171811.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:171216.3-171234.6" - wire width 64 $0\fast2$12$next[63:0]$9789 - attribute \src "libresoc.v:171048.3-171049.35" - wire width 64 $0\fast2$12[63:0]$9721 - attribute \src "libresoc.v:170355.14-170355.47" - wire width 64 $0\fast2$12[63:0]$9810 - attribute \src "libresoc.v:171216.3-171234.6" - wire $0\fast2_ok$next[0:0]$9788 - attribute \src "libresoc.v:171050.3-171051.33" + attribute \src "libresoc.v:171984.3-172002.6" + wire width 64 $0\fast2$12$next[63:0]$9721 + attribute \src "libresoc.v:171846.3-171847.35" + wire width 64 $0\fast2$12[63:0]$9679 + attribute \src "libresoc.v:171123.14-171123.47" + wire width 64 $0\fast2$12[63:0]$9742 + attribute \src "libresoc.v:171984.3-172002.6" + wire $0\fast2_ok$next[0:0]$9720 + attribute \src "libresoc.v:171848.3-171849.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:170328.7-170328.20" + attribute \src "libresoc.v:171096.7-171096.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171254.3-171272.6" - wire width 64 $0\msr$next[63:0]$9800 - attribute \src "libresoc.v:171040.3-171041.23" + attribute \src "libresoc.v:172022.3-172040.6" + wire width 64 $0\msr$next[63:0]$9732 + attribute \src "libresoc.v:171838.3-171839.23" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:171254.3-171272.6" - wire $0\msr_ok$next[0:0]$9801 - attribute \src "libresoc.v:171042.3-171043.29" + attribute \src "libresoc.v:172022.3-172040.6" + wire $0\msr_ok$next[0:0]$9733 + attribute \src "libresoc.v:171840.3-171841.29" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:171144.3-171156.6" - wire width 2 $0\muxid$1$next[1:0]$9754 - attribute \src "libresoc.v:171078.3-171079.33" + attribute \src "libresoc.v:171912.3-171924.6" + wire width 2 $0\muxid$1$next[1:0]$9686 + attribute \src "libresoc.v:171834.3-171835.33" + wire width 2 $0\muxid$1[1:0]$9672 + attribute \src "libresoc.v:171401.13-171401.29" wire width 2 $0\muxid$1[1:0]$9747 - attribute \src "libresoc.v:170633.13-170633.29" - wire width 2 $0\muxid$1[1:0]$9815 - attribute \src "libresoc.v:171235.3-171253.6" - wire width 64 $0\nia$next[63:0]$9794 - attribute \src "libresoc.v:171044.3-171045.23" + attribute \src "libresoc.v:172003.3-172021.6" + wire width 64 $0\nia$next[63:0]$9726 + attribute \src "libresoc.v:171842.3-171843.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:171235.3-171253.6" - wire $0\nia_ok$next[0:0]$9795 - attribute \src "libresoc.v:171046.3-171047.29" + attribute \src "libresoc.v:172003.3-172021.6" + wire $0\nia_ok$next[0:0]$9727 + attribute \src "libresoc.v:171844.3-171845.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:171178.3-171196.6" - wire width 64 $0\o$next[63:0]$9776 - attribute \src "libresoc.v:171056.3-171057.19" + attribute \src "libresoc.v:171946.3-171964.6" + wire width 64 $0\o$next[63:0]$9708 + attribute \src "libresoc.v:171812.3-171813.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:171178.3-171196.6" - wire $0\o_ok$next[0:0]$9777 - attribute \src "libresoc.v:171058.3-171059.25" + attribute \src "libresoc.v:171946.3-171964.6" + wire $0\o_ok$next[0:0]$9709 + attribute \src "libresoc.v:171814.3-171815.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:171126.3-171143.6" - wire $0\r_busy$next[0:0]$9750 - attribute \src "libresoc.v:171080.3-171081.29" + attribute \src "libresoc.v:171894.3-171911.6" + wire $0\r_busy$next[0:0]$9682 + attribute \src "libresoc.v:171836.3-171837.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:171157.3-171177.6" - wire width 64 $0\trap_op__cia$6$next[63:0]$9757 - attribute \src "libresoc.v:171068.3-171069.47" - wire width 64 $0\trap_op__cia$6[63:0]$9737 - attribute \src "libresoc.v:170694.14-170694.53" - wire width 64 $0\trap_op__cia$6[63:0]$9822 - attribute \src "libresoc.v:171157.3-171177.6" - wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9758 - attribute \src "libresoc.v:171062.3-171063.55" - wire width 14 $0\trap_op__fn_unit$3[13:0]$9731 - attribute \src "libresoc.v:170731.14-170731.45" - wire width 14 $0\trap_op__fn_unit$3[13:0]$9824 - attribute \src "libresoc.v:171157.3-171177.6" - wire width 32 $0\trap_op__insn$4$next[31:0]$9759 - attribute \src "libresoc.v:171064.3-171065.49" - wire width 32 $0\trap_op__insn$4[31:0]$9733 - attribute \src "libresoc.v:170757.14-170757.39" - wire width 32 $0\trap_op__insn$4[31:0]$9826 - attribute \src "libresoc.v:171157.3-171177.6" - wire width 7 $0\trap_op__insn_type$2$next[6:0]$9760 - attribute \src "libresoc.v:171060.3-171061.59" - wire width 7 $0\trap_op__insn_type$2[6:0]$9729 - attribute \src "libresoc.v:170914.13-170914.43" - wire width 7 $0\trap_op__insn_type$2[6:0]$9828 - attribute \src "libresoc.v:171157.3-171177.6" - wire $0\trap_op__is_32bit$7$next[0:0]$9761 - attribute \src "libresoc.v:171070.3-171071.57" - wire $0\trap_op__is_32bit$7[0:0]$9739 - attribute \src "libresoc.v:171000.7-171000.35" - wire $0\trap_op__is_32bit$7[0:0]$9830 - attribute \src "libresoc.v:171157.3-171177.6" - wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9762 - attribute \src "libresoc.v:171076.3-171077.59" - wire width 8 $0\trap_op__ldst_exc$10[7:0]$9745 - attribute \src "libresoc.v:171007.13-171007.43" - wire width 8 $0\trap_op__ldst_exc$10[7:0]$9832 - attribute \src "libresoc.v:171157.3-171177.6" - wire width 64 $0\trap_op__msr$5$next[63:0]$9763 - attribute \src "libresoc.v:171066.3-171067.47" - wire width 64 $0\trap_op__msr$5[63:0]$9735 - attribute \src "libresoc.v:171018.14-171018.53" - wire width 64 $0\trap_op__msr$5[63:0]$9834 - attribute \src "libresoc.v:171157.3-171177.6" - wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9764 - attribute \src "libresoc.v:171074.3-171075.57" - wire width 13 $0\trap_op__trapaddr$9[12:0]$9743 - attribute \src "libresoc.v:171027.14-171027.46" - wire width 13 $0\trap_op__trapaddr$9[12:0]$9836 - attribute \src "libresoc.v:171157.3-171177.6" - wire width 8 $0\trap_op__traptype$8$next[7:0]$9765 - attribute \src "libresoc.v:171072.3-171073.57" - wire width 8 $0\trap_op__traptype$8[7:0]$9741 - attribute \src "libresoc.v:171036.13-171036.42" - wire width 8 $0\trap_op__traptype$8[7:0]$9838 - attribute \src "libresoc.v:171197.3-171215.6" - wire width 64 $1\fast1$11$next[63:0]$9785 - attribute \src "libresoc.v:171197.3-171215.6" - wire $1\fast1_ok$next[0:0]$9784 - attribute \src "libresoc.v:170346.7-170346.22" + attribute \src "libresoc.v:171925.3-171945.6" + wire width 64 $0\trap_op__cia$6$next[63:0]$9689 + attribute \src "libresoc.v:171824.3-171825.47" + wire width 64 $0\trap_op__cia$6[63:0]$9662 + attribute \src "libresoc.v:171462.14-171462.53" + wire width 64 $0\trap_op__cia$6[63:0]$9754 + attribute \src "libresoc.v:171925.3-171945.6" + wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9690 + attribute \src "libresoc.v:171818.3-171819.55" + wire width 14 $0\trap_op__fn_unit$3[13:0]$9656 + attribute \src "libresoc.v:171499.14-171499.45" + wire width 14 $0\trap_op__fn_unit$3[13:0]$9756 + attribute \src "libresoc.v:171925.3-171945.6" + wire width 32 $0\trap_op__insn$4$next[31:0]$9691 + attribute \src "libresoc.v:171820.3-171821.49" + wire width 32 $0\trap_op__insn$4[31:0]$9658 + attribute \src "libresoc.v:171525.14-171525.39" + wire width 32 $0\trap_op__insn$4[31:0]$9758 + attribute \src "libresoc.v:171925.3-171945.6" + wire width 7 $0\trap_op__insn_type$2$next[6:0]$9692 + attribute \src "libresoc.v:171816.3-171817.59" + wire width 7 $0\trap_op__insn_type$2[6:0]$9654 + attribute \src "libresoc.v:171682.13-171682.43" + wire width 7 $0\trap_op__insn_type$2[6:0]$9760 + attribute \src "libresoc.v:171925.3-171945.6" + wire $0\trap_op__is_32bit$7$next[0:0]$9693 + attribute \src "libresoc.v:171826.3-171827.57" + wire $0\trap_op__is_32bit$7[0:0]$9664 + attribute \src "libresoc.v:171768.7-171768.35" + wire $0\trap_op__is_32bit$7[0:0]$9762 + attribute \src "libresoc.v:171925.3-171945.6" + wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9694 + attribute \src "libresoc.v:171832.3-171833.59" + wire width 8 $0\trap_op__ldst_exc$10[7:0]$9670 + attribute \src "libresoc.v:171775.13-171775.43" + wire width 8 $0\trap_op__ldst_exc$10[7:0]$9764 + attribute \src "libresoc.v:171925.3-171945.6" + wire width 64 $0\trap_op__msr$5$next[63:0]$9695 + attribute \src "libresoc.v:171822.3-171823.47" + wire width 64 $0\trap_op__msr$5[63:0]$9660 + attribute \src "libresoc.v:171786.14-171786.53" + wire width 64 $0\trap_op__msr$5[63:0]$9766 + attribute \src "libresoc.v:171925.3-171945.6" + wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9696 + attribute \src "libresoc.v:171830.3-171831.57" + wire width 13 $0\trap_op__trapaddr$9[12:0]$9668 + attribute \src "libresoc.v:171795.14-171795.46" + wire width 13 $0\trap_op__trapaddr$9[12:0]$9768 + attribute \src "libresoc.v:171925.3-171945.6" + wire width 8 $0\trap_op__traptype$8$next[7:0]$9697 + attribute \src "libresoc.v:171828.3-171829.57" + wire width 8 $0\trap_op__traptype$8[7:0]$9666 + attribute \src "libresoc.v:171804.13-171804.42" + wire width 8 $0\trap_op__traptype$8[7:0]$9770 + attribute \src "libresoc.v:171965.3-171983.6" + wire width 64 $1\fast1$11$next[63:0]$9717 + attribute \src "libresoc.v:171965.3-171983.6" + wire $1\fast1_ok$next[0:0]$9716 + attribute \src "libresoc.v:171114.7-171114.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:171216.3-171234.6" - wire width 64 $1\fast2$12$next[63:0]$9791 - attribute \src "libresoc.v:171216.3-171234.6" - wire $1\fast2_ok$next[0:0]$9790 - attribute \src "libresoc.v:170362.7-170362.22" + attribute \src "libresoc.v:171984.3-172002.6" + wire width 64 $1\fast2$12$next[63:0]$9723 + attribute \src "libresoc.v:171984.3-172002.6" + wire $1\fast2_ok$next[0:0]$9722 + attribute \src "libresoc.v:171130.7-171130.22" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:171254.3-171272.6" - wire width 64 $1\msr$next[63:0]$9802 - attribute \src "libresoc.v:170617.14-170617.40" + attribute \src "libresoc.v:172022.3-172040.6" + wire width 64 $1\msr$next[63:0]$9734 + attribute \src "libresoc.v:171385.14-171385.40" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:171254.3-171272.6" - wire $1\msr_ok$next[0:0]$9803 - attribute \src "libresoc.v:170624.7-170624.20" + attribute \src "libresoc.v:172022.3-172040.6" + wire $1\msr_ok$next[0:0]$9735 + attribute \src "libresoc.v:171392.7-171392.20" wire $1\msr_ok[0:0] - attribute \src "libresoc.v:171144.3-171156.6" - wire width 2 $1\muxid$1$next[1:0]$9755 - attribute \src "libresoc.v:171235.3-171253.6" - wire width 64 $1\nia$next[63:0]$9796 - attribute \src "libresoc.v:170646.14-170646.40" + attribute \src "libresoc.v:171912.3-171924.6" + wire width 2 $1\muxid$1$next[1:0]$9687 + attribute \src "libresoc.v:172003.3-172021.6" + wire width 64 $1\nia$next[63:0]$9728 + attribute \src "libresoc.v:171414.14-171414.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:171235.3-171253.6" - wire $1\nia_ok$next[0:0]$9797 - attribute \src "libresoc.v:170653.7-170653.20" + attribute \src "libresoc.v:172003.3-172021.6" + wire $1\nia_ok$next[0:0]$9729 + attribute \src "libresoc.v:171421.7-171421.20" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:171178.3-171196.6" - wire width 64 $1\o$next[63:0]$9778 - attribute \src "libresoc.v:170660.14-170660.38" + attribute \src "libresoc.v:171946.3-171964.6" + wire width 64 $1\o$next[63:0]$9710 + attribute \src "libresoc.v:171428.14-171428.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:171178.3-171196.6" - wire $1\o_ok$next[0:0]$9779 - attribute \src "libresoc.v:170667.7-170667.18" + attribute \src "libresoc.v:171946.3-171964.6" + wire $1\o_ok$next[0:0]$9711 + attribute \src "libresoc.v:171435.7-171435.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:171126.3-171143.6" - wire $1\r_busy$next[0:0]$9751 - attribute \src "libresoc.v:170681.7-170681.20" + attribute \src "libresoc.v:171894.3-171911.6" + wire $1\r_busy$next[0:0]$9683 + attribute \src "libresoc.v:171449.7-171449.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:171157.3-171177.6" - wire width 64 $1\trap_op__cia$6$next[63:0]$9766 - attribute \src "libresoc.v:171157.3-171177.6" - wire width 14 $1\trap_op__fn_unit$3$next[13:0]$9767 - attribute \src "libresoc.v:171157.3-171177.6" - wire width 32 $1\trap_op__insn$4$next[31:0]$9768 - attribute \src "libresoc.v:171157.3-171177.6" - wire width 7 $1\trap_op__insn_type$2$next[6:0]$9769 - attribute \src "libresoc.v:171157.3-171177.6" - wire $1\trap_op__is_32bit$7$next[0:0]$9770 - attribute \src "libresoc.v:171157.3-171177.6" - wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9771 - attribute \src "libresoc.v:171157.3-171177.6" - wire width 64 $1\trap_op__msr$5$next[63:0]$9772 - attribute \src "libresoc.v:171157.3-171177.6" - wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9773 - attribute \src "libresoc.v:171157.3-171177.6" - wire width 8 $1\trap_op__traptype$8$next[7:0]$9774 - attribute \src "libresoc.v:171197.3-171215.6" - wire $2\fast1_ok$next[0:0]$9786 - attribute \src "libresoc.v:171216.3-171234.6" - wire $2\fast2_ok$next[0:0]$9792 - attribute \src "libresoc.v:171254.3-171272.6" - wire $2\msr_ok$next[0:0]$9804 - attribute \src "libresoc.v:171235.3-171253.6" - wire $2\nia_ok$next[0:0]$9798 - attribute \src "libresoc.v:171178.3-171196.6" - wire $2\o_ok$next[0:0]$9780 - attribute \src "libresoc.v:171126.3-171143.6" - wire $2\r_busy$next[0:0]$9752 - attribute \src "libresoc.v:171039.18-171039.118" - wire $and$libresoc.v:171039$9715_Y + attribute \src "libresoc.v:171925.3-171945.6" + wire width 64 $1\trap_op__cia$6$next[63:0]$9698 + attribute \src "libresoc.v:171925.3-171945.6" + wire width 14 $1\trap_op__fn_unit$3$next[13:0]$9699 + attribute \src "libresoc.v:171925.3-171945.6" + wire width 32 $1\trap_op__insn$4$next[31:0]$9700 + attribute \src "libresoc.v:171925.3-171945.6" + wire width 7 $1\trap_op__insn_type$2$next[6:0]$9701 + attribute \src "libresoc.v:171925.3-171945.6" + wire $1\trap_op__is_32bit$7$next[0:0]$9702 + attribute \src "libresoc.v:171925.3-171945.6" + wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9703 + attribute \src "libresoc.v:171925.3-171945.6" + wire width 64 $1\trap_op__msr$5$next[63:0]$9704 + attribute \src "libresoc.v:171925.3-171945.6" + wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9705 + attribute \src "libresoc.v:171925.3-171945.6" + wire width 8 $1\trap_op__traptype$8$next[7:0]$9706 + attribute \src "libresoc.v:171965.3-171983.6" + wire $2\fast1_ok$next[0:0]$9718 + attribute \src "libresoc.v:171984.3-172002.6" + wire $2\fast2_ok$next[0:0]$9724 + attribute \src "libresoc.v:172022.3-172040.6" + wire $2\msr_ok$next[0:0]$9736 + attribute \src "libresoc.v:172003.3-172021.6" + wire $2\nia_ok$next[0:0]$9730 + attribute \src "libresoc.v:171946.3-171964.6" + wire $2\o_ok$next[0:0]$9712 + attribute \src "libresoc.v:171894.3-171911.6" + wire $2\r_busy$next[0:0]$9684 + attribute \src "libresoc.v:171807.18-171807.118" + wire $and$libresoc.v:171807$9647_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 16 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 32 \fast1$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast1$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast1$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast1_ok$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 17 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 34 \fast2$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast2$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast2$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 35 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast2_ok$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast2_ok$next - attribute \src "libresoc.v:170328.7-170328.15" + attribute \src "libresoc.v:171096.7-171096.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_fast1$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_fast2$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_msr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_ra @@ -350661,17 +317204,17 @@ module \pipe2$35 wire width 8 \main_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \main_trap_op__traptype$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 38 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \msr$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 39 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \msr_ok$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \msr_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -350687,29 +317230,29 @@ module \pipe2$35 wire input 19 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 18 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 36 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \nia$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 37 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \nia_ok$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \nia_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 30 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 31 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o @@ -351070,7 +317613,7 @@ module \pipe2$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$8$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:171039$9715 + cell $and $and$libresoc.v:171807$9647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351078,10 +317621,10 @@ module \pipe2$35 parameter \Y_WIDTH 1 connect \A \p_valid_i$25 connect \B \p_ready_o - connect \Y $and$libresoc.v:171039$9715_Y + connect \Y $and$libresoc.v:171807$9647_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:171082.13-171117.4" + attribute \src "libresoc.v:171850.13-171885.4" cell \main$38 \main connect \fast1 \main_fast1 connect \fast1$11 \main_fast1$23 @@ -351119,349 +317662,349 @@ module \pipe2$35 connect \trap_op__traptype$8 \main_trap_op__traptype$20 end attribute \module_not_derived 1 - attribute \src "libresoc.v:171118.10-171121.4" + attribute \src "libresoc.v:171886.10-171889.4" cell \n$37 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:171122.10-171125.4" + attribute \src "libresoc.v:171890.10-171893.4" cell \p$36 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:170328.7-170328.20" - process $proc$libresoc.v:170328$9805 + attribute \src "libresoc.v:171096.7-171096.20" + process $proc$libresoc.v:171096$9737 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170339.14-170339.47" - process $proc$libresoc.v:170339$9806 + attribute \src "libresoc.v:171107.14-171107.47" + process $proc$libresoc.v:171107$9738 assign { } { } - assign $0\fast1$11[63:0]$9807 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$11[63:0]$9739 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$11 $0\fast1$11[63:0]$9807 + update \fast1$11 $0\fast1$11[63:0]$9739 end - attribute \src "libresoc.v:170346.7-170346.22" - process $proc$libresoc.v:170346$9808 + attribute \src "libresoc.v:171114.7-171114.22" + process $proc$libresoc.v:171114$9740 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:170355.14-170355.47" - process $proc$libresoc.v:170355$9809 + attribute \src "libresoc.v:171123.14-171123.47" + process $proc$libresoc.v:171123$9741 assign { } { } - assign $0\fast2$12[63:0]$9810 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast2$12[63:0]$9742 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast2$12 $0\fast2$12[63:0]$9810 + update \fast2$12 $0\fast2$12[63:0]$9742 end - attribute \src "libresoc.v:170362.7-170362.22" - process $proc$libresoc.v:170362$9811 + attribute \src "libresoc.v:171130.7-171130.22" + process $proc$libresoc.v:171130$9743 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:170617.14-170617.40" - process $proc$libresoc.v:170617$9812 + attribute \src "libresoc.v:171385.14-171385.40" + process $proc$libresoc.v:171385$9744 assign { } { } assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr $1\msr[63:0] end - attribute \src "libresoc.v:170624.7-170624.20" - process $proc$libresoc.v:170624$9813 + attribute \src "libresoc.v:171392.7-171392.20" + process $proc$libresoc.v:171392$9745 assign { } { } assign $1\msr_ok[0:0] 1'0 sync always sync init update \msr_ok $1\msr_ok[0:0] end - attribute \src "libresoc.v:170633.13-170633.29" - process $proc$libresoc.v:170633$9814 + attribute \src "libresoc.v:171401.13-171401.29" + process $proc$libresoc.v:171401$9746 assign { } { } - assign $0\muxid$1[1:0]$9815 2'00 + assign $0\muxid$1[1:0]$9747 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9815 + update \muxid$1 $0\muxid$1[1:0]$9747 end - attribute \src "libresoc.v:170646.14-170646.40" - process $proc$libresoc.v:170646$9816 + attribute \src "libresoc.v:171414.14-171414.40" + process $proc$libresoc.v:171414$9748 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:170653.7-170653.20" - process $proc$libresoc.v:170653$9817 + attribute \src "libresoc.v:171421.7-171421.20" + process $proc$libresoc.v:171421$9749 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:170660.14-170660.38" - process $proc$libresoc.v:170660$9818 + attribute \src "libresoc.v:171428.14-171428.38" + process $proc$libresoc.v:171428$9750 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:170667.7-170667.18" - process $proc$libresoc.v:170667$9819 + attribute \src "libresoc.v:171435.7-171435.18" + process $proc$libresoc.v:171435$9751 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:170681.7-170681.20" - process $proc$libresoc.v:170681$9820 + attribute \src "libresoc.v:171449.7-171449.20" + process $proc$libresoc.v:171449$9752 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:170694.14-170694.53" - process $proc$libresoc.v:170694$9821 + attribute \src "libresoc.v:171462.14-171462.53" + process $proc$libresoc.v:171462$9753 assign { } { } - assign $0\trap_op__cia$6[63:0]$9822 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__cia$6[63:0]$9754 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9822 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9754 end - attribute \src "libresoc.v:170731.14-170731.45" - process $proc$libresoc.v:170731$9823 + attribute \src "libresoc.v:171499.14-171499.45" + process $proc$libresoc.v:171499$9755 assign { } { } - assign $0\trap_op__fn_unit$3[13:0]$9824 14'00000000000000 + assign $0\trap_op__fn_unit$3[13:0]$9756 14'00000000000000 sync always sync init - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9824 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9756 end - attribute \src "libresoc.v:170757.14-170757.39" - process $proc$libresoc.v:170757$9825 + attribute \src "libresoc.v:171525.14-171525.39" + process $proc$libresoc.v:171525$9757 assign { } { } - assign $0\trap_op__insn$4[31:0]$9826 0 + assign $0\trap_op__insn$4[31:0]$9758 0 sync always sync init - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9826 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9758 end - attribute \src "libresoc.v:170914.13-170914.43" - process $proc$libresoc.v:170914$9827 + attribute \src "libresoc.v:171682.13-171682.43" + process $proc$libresoc.v:171682$9759 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9828 7'0000000 + assign $0\trap_op__insn_type$2[6:0]$9760 7'0000000 sync always sync init - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9828 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9760 end - attribute \src "libresoc.v:171000.7-171000.35" - process $proc$libresoc.v:171000$9829 + attribute \src "libresoc.v:171768.7-171768.35" + process $proc$libresoc.v:171768$9761 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9830 1'0 + assign $0\trap_op__is_32bit$7[0:0]$9762 1'0 sync always sync init - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9830 + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9762 end - attribute \src "libresoc.v:171007.13-171007.43" - process $proc$libresoc.v:171007$9831 + attribute \src "libresoc.v:171775.13-171775.43" + process $proc$libresoc.v:171775$9763 assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9832 8'00000000 + assign $0\trap_op__ldst_exc$10[7:0]$9764 8'00000000 sync always sync init - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9832 + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9764 end - attribute \src "libresoc.v:171018.14-171018.53" - process $proc$libresoc.v:171018$9833 + attribute \src "libresoc.v:171786.14-171786.53" + process $proc$libresoc.v:171786$9765 assign { } { } - assign $0\trap_op__msr$5[63:0]$9834 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__msr$5[63:0]$9766 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9834 + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9766 end - attribute \src "libresoc.v:171027.14-171027.46" - process $proc$libresoc.v:171027$9835 + attribute \src "libresoc.v:171795.14-171795.46" + process $proc$libresoc.v:171795$9767 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9836 13'0000000000000 + assign $0\trap_op__trapaddr$9[12:0]$9768 13'0000000000000 sync always sync init - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9836 + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9768 end - attribute \src "libresoc.v:171036.13-171036.42" - process $proc$libresoc.v:171036$9837 + attribute \src "libresoc.v:171804.13-171804.42" + process $proc$libresoc.v:171804$9769 assign { } { } - assign $0\trap_op__traptype$8[7:0]$9838 8'00000000 + assign $0\trap_op__traptype$8[7:0]$9770 8'00000000 sync always sync init - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9838 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9770 end - attribute \src "libresoc.v:171040.3-171041.23" - process $proc$libresoc.v:171040$9716 + attribute \src "libresoc.v:171808.3-171809.35" + process $proc$libresoc.v:171808$9648 assign { } { } - assign $0\msr[63:0] \msr$next + assign $0\fast1$11[63:0]$9649 \fast1$11$next sync posedge \coresync_clk - update \msr $0\msr[63:0] + update \fast1$11 $0\fast1$11[63:0]$9649 end - attribute \src "libresoc.v:171042.3-171043.29" - process $proc$libresoc.v:171042$9717 + attribute \src "libresoc.v:171810.3-171811.33" + process $proc$libresoc.v:171810$9650 assign { } { } - assign $0\msr_ok[0:0] \msr_ok$next + assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk - update \msr_ok $0\msr_ok[0:0] + update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:171044.3-171045.23" - process $proc$libresoc.v:171044$9718 + attribute \src "libresoc.v:171812.3-171813.19" + process $proc$libresoc.v:171812$9651 assign { } { } - assign $0\nia[63:0] \nia$next + assign $0\o[63:0] \o$next sync posedge \coresync_clk - update \nia $0\nia[63:0] + update \o $0\o[63:0] end - attribute \src "libresoc.v:171046.3-171047.29" - process $proc$libresoc.v:171046$9719 + attribute \src "libresoc.v:171814.3-171815.25" + process $proc$libresoc.v:171814$9652 assign { } { } - assign $0\nia_ok[0:0] \nia_ok$next + assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk - update \nia_ok $0\nia_ok[0:0] + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:171048.3-171049.35" - process $proc$libresoc.v:171048$9720 + attribute \src "libresoc.v:171816.3-171817.59" + process $proc$libresoc.v:171816$9653 assign { } { } - assign $0\fast2$12[63:0]$9721 \fast2$12$next + assign $0\trap_op__insn_type$2[6:0]$9654 \trap_op__insn_type$2$next sync posedge \coresync_clk - update \fast2$12 $0\fast2$12[63:0]$9721 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9654 end - attribute \src "libresoc.v:171050.3-171051.33" - process $proc$libresoc.v:171050$9722 + attribute \src "libresoc.v:171818.3-171819.55" + process $proc$libresoc.v:171818$9655 assign { } { } - assign $0\fast2_ok[0:0] \fast2_ok$next + assign $0\trap_op__fn_unit$3[13:0]$9656 \trap_op__fn_unit$3$next sync posedge \coresync_clk - update \fast2_ok $0\fast2_ok[0:0] + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9656 end - attribute \src "libresoc.v:171052.3-171053.35" - process $proc$libresoc.v:171052$9723 + attribute \src "libresoc.v:171820.3-171821.49" + process $proc$libresoc.v:171820$9657 assign { } { } - assign $0\fast1$11[63:0]$9724 \fast1$11$next + assign $0\trap_op__insn$4[31:0]$9658 \trap_op__insn$4$next sync posedge \coresync_clk - update \fast1$11 $0\fast1$11[63:0]$9724 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9658 end - attribute \src "libresoc.v:171054.3-171055.33" - process $proc$libresoc.v:171054$9725 + attribute \src "libresoc.v:171822.3-171823.47" + process $proc$libresoc.v:171822$9659 assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next + assign $0\trap_op__msr$5[63:0]$9660 \trap_op__msr$5$next sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9660 end - attribute \src "libresoc.v:171056.3-171057.19" - process $proc$libresoc.v:171056$9726 + attribute \src "libresoc.v:171824.3-171825.47" + process $proc$libresoc.v:171824$9661 assign { } { } - assign $0\o[63:0] \o$next + assign $0\trap_op__cia$6[63:0]$9662 \trap_op__cia$6$next sync posedge \coresync_clk - update \o $0\o[63:0] + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9662 end - attribute \src "libresoc.v:171058.3-171059.25" - process $proc$libresoc.v:171058$9727 + attribute \src "libresoc.v:171826.3-171827.57" + process $proc$libresoc.v:171826$9663 assign { } { } - assign $0\o_ok[0:0] \o_ok$next + assign $0\trap_op__is_32bit$7[0:0]$9664 \trap_op__is_32bit$7$next sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9664 end - attribute \src "libresoc.v:171060.3-171061.59" - process $proc$libresoc.v:171060$9728 + attribute \src "libresoc.v:171828.3-171829.57" + process $proc$libresoc.v:171828$9665 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9729 \trap_op__insn_type$2$next + assign $0\trap_op__traptype$8[7:0]$9666 \trap_op__traptype$8$next sync posedge \coresync_clk - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9729 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9666 end - attribute \src "libresoc.v:171062.3-171063.55" - process $proc$libresoc.v:171062$9730 + attribute \src "libresoc.v:171830.3-171831.57" + process $proc$libresoc.v:171830$9667 assign { } { } - assign $0\trap_op__fn_unit$3[13:0]$9731 \trap_op__fn_unit$3$next + assign $0\trap_op__trapaddr$9[12:0]$9668 \trap_op__trapaddr$9$next sync posedge \coresync_clk - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9731 + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9668 end - attribute \src "libresoc.v:171064.3-171065.49" - process $proc$libresoc.v:171064$9732 + attribute \src "libresoc.v:171832.3-171833.59" + process $proc$libresoc.v:171832$9669 assign { } { } - assign $0\trap_op__insn$4[31:0]$9733 \trap_op__insn$4$next + assign $0\trap_op__ldst_exc$10[7:0]$9670 \trap_op__ldst_exc$10$next sync posedge \coresync_clk - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9733 + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9670 end - attribute \src "libresoc.v:171066.3-171067.47" - process $proc$libresoc.v:171066$9734 + attribute \src "libresoc.v:171834.3-171835.33" + process $proc$libresoc.v:171834$9671 assign { } { } - assign $0\trap_op__msr$5[63:0]$9735 \trap_op__msr$5$next + assign $0\muxid$1[1:0]$9672 \muxid$1$next sync posedge \coresync_clk - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9735 + update \muxid$1 $0\muxid$1[1:0]$9672 end - attribute \src "libresoc.v:171068.3-171069.47" - process $proc$libresoc.v:171068$9736 + attribute \src "libresoc.v:171836.3-171837.29" + process $proc$libresoc.v:171836$9673 assign { } { } - assign $0\trap_op__cia$6[63:0]$9737 \trap_op__cia$6$next + assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9737 + update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:171070.3-171071.57" - process $proc$libresoc.v:171070$9738 + attribute \src "libresoc.v:171838.3-171839.23" + process $proc$libresoc.v:171838$9674 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9739 \trap_op__is_32bit$7$next + assign $0\msr[63:0] \msr$next sync posedge \coresync_clk - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9739 + update \msr $0\msr[63:0] end - attribute \src "libresoc.v:171072.3-171073.57" - process $proc$libresoc.v:171072$9740 + attribute \src "libresoc.v:171840.3-171841.29" + process $proc$libresoc.v:171840$9675 assign { } { } - assign $0\trap_op__traptype$8[7:0]$9741 \trap_op__traptype$8$next + assign $0\msr_ok[0:0] \msr_ok$next sync posedge \coresync_clk - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9741 + update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:171074.3-171075.57" - process $proc$libresoc.v:171074$9742 + attribute \src "libresoc.v:171842.3-171843.23" + process $proc$libresoc.v:171842$9676 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9743 \trap_op__trapaddr$9$next + assign $0\nia[63:0] \nia$next sync posedge \coresync_clk - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9743 + update \nia $0\nia[63:0] end - attribute \src "libresoc.v:171076.3-171077.59" - process $proc$libresoc.v:171076$9744 + attribute \src "libresoc.v:171844.3-171845.29" + process $proc$libresoc.v:171844$9677 assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9745 \trap_op__ldst_exc$10$next + assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9745 + update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:171078.3-171079.33" - process $proc$libresoc.v:171078$9746 + attribute \src "libresoc.v:171846.3-171847.35" + process $proc$libresoc.v:171846$9678 assign { } { } - assign $0\muxid$1[1:0]$9747 \muxid$1$next + assign $0\fast2$12[63:0]$9679 \fast2$12$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9747 + update \fast2$12 $0\fast2$12[63:0]$9679 end - attribute \src "libresoc.v:171080.3-171081.29" - process $proc$libresoc.v:171080$9748 + attribute \src "libresoc.v:171848.3-171849.33" + process $proc$libresoc.v:171848$9680 assign { } { } - assign $0\r_busy[0:0] \r_busy$next + assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:171126.3-171143.6" - process $proc$libresoc.v:171126$9749 + attribute \src "libresoc.v:171894.3-171911.6" + process $proc$libresoc.v:171894$9681 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9750 $2\r_busy$next[0:0]$9752 - attribute \src "libresoc.v:171127.5-171127.29" + assign $0\r_busy$next[0:0]$9682 $2\r_busy$next[0:0]$9684 + attribute \src "libresoc.v:171895.5-171895.29" switch \initial - attribute \src "libresoc.v:171127.9-171127.17" + attribute \src "libresoc.v:171895.9-171895.17" case 1'1 case end @@ -351470,34 +318013,34 @@ module \pipe2$35 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9751 1'1 + assign $1\r_busy$next[0:0]$9683 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9751 1'0 + assign $1\r_busy$next[0:0]$9683 1'0 case - assign $1\r_busy$next[0:0]$9751 \r_busy + assign $1\r_busy$next[0:0]$9683 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9752 1'0 + assign $2\r_busy$next[0:0]$9684 1'0 case - assign $2\r_busy$next[0:0]$9752 $1\r_busy$next[0:0]$9751 + assign $2\r_busy$next[0:0]$9684 $1\r_busy$next[0:0]$9683 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9750 + update \r_busy$next $0\r_busy$next[0:0]$9682 end - attribute \src "libresoc.v:171144.3-171156.6" - process $proc$libresoc.v:171144$9753 + attribute \src "libresoc.v:171912.3-171924.6" + process $proc$libresoc.v:171912$9685 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9754 $1\muxid$1$next[1:0]$9755 - attribute \src "libresoc.v:171145.5-171145.29" + assign $0\muxid$1$next[1:0]$9686 $1\muxid$1$next[1:0]$9687 + attribute \src "libresoc.v:171913.5-171913.29" switch \initial - attribute \src "libresoc.v:171145.9-171145.17" + attribute \src "libresoc.v:171913.9-171913.17" case 1'1 case end @@ -351506,19 +318049,19 @@ module \pipe2$35 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9755 \muxid$28 + assign $1\muxid$1$next[1:0]$9687 \muxid$28 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9755 \muxid$28 + assign $1\muxid$1$next[1:0]$9687 \muxid$28 case - assign $1\muxid$1$next[1:0]$9755 \muxid$1 + assign $1\muxid$1$next[1:0]$9687 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9754 + update \muxid$1$next $0\muxid$1$next[1:0]$9686 end - attribute \src "libresoc.v:171157.3-171177.6" - process $proc$libresoc.v:171157$9756 + attribute \src "libresoc.v:171925.3-171945.6" + process $proc$libresoc.v:171925$9688 assign { } { } assign { } { } assign { } { } @@ -351537,18 +318080,18 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign $0\trap_op__cia$6$next[63:0]$9757 $1\trap_op__cia$6$next[63:0]$9766 - assign $0\trap_op__fn_unit$3$next[13:0]$9758 $1\trap_op__fn_unit$3$next[13:0]$9767 - assign $0\trap_op__insn$4$next[31:0]$9759 $1\trap_op__insn$4$next[31:0]$9768 - assign $0\trap_op__insn_type$2$next[6:0]$9760 $1\trap_op__insn_type$2$next[6:0]$9769 - assign $0\trap_op__is_32bit$7$next[0:0]$9761 $1\trap_op__is_32bit$7$next[0:0]$9770 - assign $0\trap_op__ldst_exc$10$next[7:0]$9762 $1\trap_op__ldst_exc$10$next[7:0]$9771 - assign $0\trap_op__msr$5$next[63:0]$9763 $1\trap_op__msr$5$next[63:0]$9772 - assign $0\trap_op__trapaddr$9$next[12:0]$9764 $1\trap_op__trapaddr$9$next[12:0]$9773 - assign $0\trap_op__traptype$8$next[7:0]$9765 $1\trap_op__traptype$8$next[7:0]$9774 - attribute \src "libresoc.v:171158.5-171158.29" + assign $0\trap_op__cia$6$next[63:0]$9689 $1\trap_op__cia$6$next[63:0]$9698 + assign $0\trap_op__fn_unit$3$next[13:0]$9690 $1\trap_op__fn_unit$3$next[13:0]$9699 + assign $0\trap_op__insn$4$next[31:0]$9691 $1\trap_op__insn$4$next[31:0]$9700 + assign $0\trap_op__insn_type$2$next[6:0]$9692 $1\trap_op__insn_type$2$next[6:0]$9701 + assign $0\trap_op__is_32bit$7$next[0:0]$9693 $1\trap_op__is_32bit$7$next[0:0]$9702 + assign $0\trap_op__ldst_exc$10$next[7:0]$9694 $1\trap_op__ldst_exc$10$next[7:0]$9703 + assign $0\trap_op__msr$5$next[63:0]$9695 $1\trap_op__msr$5$next[63:0]$9704 + assign $0\trap_op__trapaddr$9$next[12:0]$9696 $1\trap_op__trapaddr$9$next[12:0]$9705 + assign $0\trap_op__traptype$8$next[7:0]$9697 $1\trap_op__traptype$8$next[7:0]$9706 + attribute \src "libresoc.v:171926.5-171926.29" switch \initial - attribute \src "libresoc.v:171158.9-171158.17" + attribute \src "libresoc.v:171926.9-171926.17" case 1'1 case end @@ -351565,7 +318108,7 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9771 $1\trap_op__trapaddr$9$next[12:0]$9773 $1\trap_op__traptype$8$next[7:0]$9774 $1\trap_op__is_32bit$7$next[0:0]$9770 $1\trap_op__cia$6$next[63:0]$9766 $1\trap_op__msr$5$next[63:0]$9772 $1\trap_op__insn$4$next[31:0]$9768 $1\trap_op__fn_unit$3$next[13:0]$9767 $1\trap_op__insn_type$2$next[6:0]$9769 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9703 $1\trap_op__trapaddr$9$next[12:0]$9705 $1\trap_op__traptype$8$next[7:0]$9706 $1\trap_op__is_32bit$7$next[0:0]$9702 $1\trap_op__cia$6$next[63:0]$9698 $1\trap_op__msr$5$next[63:0]$9704 $1\trap_op__insn$4$next[31:0]$9700 $1\trap_op__fn_unit$3$next[13:0]$9699 $1\trap_op__insn_type$2$next[6:0]$9701 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -351577,41 +318120,41 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9771 $1\trap_op__trapaddr$9$next[12:0]$9773 $1\trap_op__traptype$8$next[7:0]$9774 $1\trap_op__is_32bit$7$next[0:0]$9770 $1\trap_op__cia$6$next[63:0]$9766 $1\trap_op__msr$5$next[63:0]$9772 $1\trap_op__insn$4$next[31:0]$9768 $1\trap_op__fn_unit$3$next[13:0]$9767 $1\trap_op__insn_type$2$next[6:0]$9769 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9703 $1\trap_op__trapaddr$9$next[12:0]$9705 $1\trap_op__traptype$8$next[7:0]$9706 $1\trap_op__is_32bit$7$next[0:0]$9702 $1\trap_op__cia$6$next[63:0]$9698 $1\trap_op__msr$5$next[63:0]$9704 $1\trap_op__insn$4$next[31:0]$9700 $1\trap_op__fn_unit$3$next[13:0]$9699 $1\trap_op__insn_type$2$next[6:0]$9701 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } case - assign $1\trap_op__cia$6$next[63:0]$9766 \trap_op__cia$6 - assign $1\trap_op__fn_unit$3$next[13:0]$9767 \trap_op__fn_unit$3 - assign $1\trap_op__insn$4$next[31:0]$9768 \trap_op__insn$4 - assign $1\trap_op__insn_type$2$next[6:0]$9769 \trap_op__insn_type$2 - assign $1\trap_op__is_32bit$7$next[0:0]$9770 \trap_op__is_32bit$7 - assign $1\trap_op__ldst_exc$10$next[7:0]$9771 \trap_op__ldst_exc$10 - assign $1\trap_op__msr$5$next[63:0]$9772 \trap_op__msr$5 - assign $1\trap_op__trapaddr$9$next[12:0]$9773 \trap_op__trapaddr$9 - assign $1\trap_op__traptype$8$next[7:0]$9774 \trap_op__traptype$8 + assign $1\trap_op__cia$6$next[63:0]$9698 \trap_op__cia$6 + assign $1\trap_op__fn_unit$3$next[13:0]$9699 \trap_op__fn_unit$3 + assign $1\trap_op__insn$4$next[31:0]$9700 \trap_op__insn$4 + assign $1\trap_op__insn_type$2$next[6:0]$9701 \trap_op__insn_type$2 + assign $1\trap_op__is_32bit$7$next[0:0]$9702 \trap_op__is_32bit$7 + assign $1\trap_op__ldst_exc$10$next[7:0]$9703 \trap_op__ldst_exc$10 + assign $1\trap_op__msr$5$next[63:0]$9704 \trap_op__msr$5 + assign $1\trap_op__trapaddr$9$next[12:0]$9705 \trap_op__trapaddr$9 + assign $1\trap_op__traptype$8$next[7:0]$9706 \trap_op__traptype$8 end sync always - update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9757 - update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[13:0]$9758 - update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9759 - update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9760 - update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9761 - update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9762 - update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9763 - update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9764 - update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9765 + update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9689 + update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[13:0]$9690 + update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9691 + update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9692 + update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9693 + update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9694 + update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9695 + update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9696 + update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9697 end - attribute \src "libresoc.v:171178.3-171196.6" - process $proc$libresoc.v:171178$9775 + attribute \src "libresoc.v:171946.3-171964.6" + process $proc$libresoc.v:171946$9707 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9776 $1\o$next[63:0]$9778 + assign $0\o$next[63:0]$9708 $1\o$next[63:0]$9710 assign { } { } - assign $0\o_ok$next[0:0]$9777 $2\o_ok$next[0:0]$9780 - attribute \src "libresoc.v:171179.5-171179.29" + assign $0\o_ok$next[0:0]$9709 $2\o_ok$next[0:0]$9712 + attribute \src "libresoc.v:171947.5-171947.29" switch \initial - attribute \src "libresoc.v:171179.9-171179.17" + attribute \src "libresoc.v:171947.9-171947.17" case 1'1 case end @@ -351621,41 +318164,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9779 $1\o$next[63:0]$9778 } { \o_ok$39 \o$38 } + assign { $1\o_ok$next[0:0]$9711 $1\o$next[63:0]$9710 } { \o_ok$39 \o$38 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9779 $1\o$next[63:0]$9778 } { \o_ok$39 \o$38 } + assign { $1\o_ok$next[0:0]$9711 $1\o$next[63:0]$9710 } { \o_ok$39 \o$38 } case - assign $1\o$next[63:0]$9778 \o - assign $1\o_ok$next[0:0]$9779 \o_ok + assign $1\o$next[63:0]$9710 \o + assign $1\o_ok$next[0:0]$9711 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9780 1'0 + assign $2\o_ok$next[0:0]$9712 1'0 case - assign $2\o_ok$next[0:0]$9780 $1\o_ok$next[0:0]$9779 + assign $2\o_ok$next[0:0]$9712 $1\o_ok$next[0:0]$9711 end sync always - update \o$next $0\o$next[63:0]$9776 - update \o_ok$next $0\o_ok$next[0:0]$9777 + update \o$next $0\o$next[63:0]$9708 + update \o_ok$next $0\o_ok$next[0:0]$9709 end - attribute \src "libresoc.v:171197.3-171215.6" - process $proc$libresoc.v:171197$9781 + attribute \src "libresoc.v:171965.3-171983.6" + process $proc$libresoc.v:171965$9713 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$11$next[63:0]$9783 $1\fast1$11$next[63:0]$9785 - assign $0\fast1_ok$next[0:0]$9782 $2\fast1_ok$next[0:0]$9786 - attribute \src "libresoc.v:171198.5-171198.29" + assign $0\fast1$11$next[63:0]$9715 $1\fast1$11$next[63:0]$9717 + assign $0\fast1_ok$next[0:0]$9714 $2\fast1_ok$next[0:0]$9718 + attribute \src "libresoc.v:171966.5-171966.29" switch \initial - attribute \src "libresoc.v:171198.9-171198.17" + attribute \src "libresoc.v:171966.9-171966.17" case 1'1 case end @@ -351665,41 +318208,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$9784 $1\fast1$11$next[63:0]$9785 } { \fast1_ok$41 \fast1$40 } + assign { $1\fast1_ok$next[0:0]$9716 $1\fast1$11$next[63:0]$9717 } { \fast1_ok$41 \fast1$40 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$9784 $1\fast1$11$next[63:0]$9785 } { \fast1_ok$41 \fast1$40 } + assign { $1\fast1_ok$next[0:0]$9716 $1\fast1$11$next[63:0]$9717 } { \fast1_ok$41 \fast1$40 } case - assign $1\fast1_ok$next[0:0]$9784 \fast1_ok - assign $1\fast1$11$next[63:0]$9785 \fast1$11 + assign $1\fast1_ok$next[0:0]$9716 \fast1_ok + assign $1\fast1$11$next[63:0]$9717 \fast1$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$9786 1'0 + assign $2\fast1_ok$next[0:0]$9718 1'0 case - assign $2\fast1_ok$next[0:0]$9786 $1\fast1_ok$next[0:0]$9784 + assign $2\fast1_ok$next[0:0]$9718 $1\fast1_ok$next[0:0]$9716 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$9782 - update \fast1$11$next $0\fast1$11$next[63:0]$9783 + update \fast1_ok$next $0\fast1_ok$next[0:0]$9714 + update \fast1$11$next $0\fast1$11$next[63:0]$9715 end - attribute \src "libresoc.v:171216.3-171234.6" - process $proc$libresoc.v:171216$9787 + attribute \src "libresoc.v:171984.3-172002.6" + process $proc$libresoc.v:171984$9719 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast2$12$next[63:0]$9789 $1\fast2$12$next[63:0]$9791 - assign $0\fast2_ok$next[0:0]$9788 $2\fast2_ok$next[0:0]$9792 - attribute \src "libresoc.v:171217.5-171217.29" + assign $0\fast2$12$next[63:0]$9721 $1\fast2$12$next[63:0]$9723 + assign $0\fast2_ok$next[0:0]$9720 $2\fast2_ok$next[0:0]$9724 + attribute \src "libresoc.v:171985.5-171985.29" switch \initial - attribute \src "libresoc.v:171217.9-171217.17" + attribute \src "libresoc.v:171985.9-171985.17" case 1'1 case end @@ -351709,41 +318252,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$9790 $1\fast2$12$next[63:0]$9791 } { \fast2_ok$43 \fast2$42 } + assign { $1\fast2_ok$next[0:0]$9722 $1\fast2$12$next[63:0]$9723 } { \fast2_ok$43 \fast2$42 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$9790 $1\fast2$12$next[63:0]$9791 } { \fast2_ok$43 \fast2$42 } + assign { $1\fast2_ok$next[0:0]$9722 $1\fast2$12$next[63:0]$9723 } { \fast2_ok$43 \fast2$42 } case - assign $1\fast2_ok$next[0:0]$9790 \fast2_ok - assign $1\fast2$12$next[63:0]$9791 \fast2$12 + assign $1\fast2_ok$next[0:0]$9722 \fast2_ok + assign $1\fast2$12$next[63:0]$9723 \fast2$12 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$9792 1'0 + assign $2\fast2_ok$next[0:0]$9724 1'0 case - assign $2\fast2_ok$next[0:0]$9792 $1\fast2_ok$next[0:0]$9790 + assign $2\fast2_ok$next[0:0]$9724 $1\fast2_ok$next[0:0]$9722 end sync always - update \fast2_ok$next $0\fast2_ok$next[0:0]$9788 - update \fast2$12$next $0\fast2$12$next[63:0]$9789 + update \fast2_ok$next $0\fast2_ok$next[0:0]$9720 + update \fast2$12$next $0\fast2$12$next[63:0]$9721 end - attribute \src "libresoc.v:171235.3-171253.6" - process $proc$libresoc.v:171235$9793 + attribute \src "libresoc.v:172003.3-172021.6" + process $proc$libresoc.v:172003$9725 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$9794 $1\nia$next[63:0]$9796 + assign $0\nia$next[63:0]$9726 $1\nia$next[63:0]$9728 assign { } { } - assign $0\nia_ok$next[0:0]$9795 $2\nia_ok$next[0:0]$9798 - attribute \src "libresoc.v:171236.5-171236.29" + assign $0\nia_ok$next[0:0]$9727 $2\nia_ok$next[0:0]$9730 + attribute \src "libresoc.v:172004.5-172004.29" switch \initial - attribute \src "libresoc.v:171236.9-171236.17" + attribute \src "libresoc.v:172004.9-172004.17" case 1'1 case end @@ -351753,41 +318296,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$9797 $1\nia$next[63:0]$9796 } { \nia_ok$45 \nia$44 } + assign { $1\nia_ok$next[0:0]$9729 $1\nia$next[63:0]$9728 } { \nia_ok$45 \nia$44 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$9797 $1\nia$next[63:0]$9796 } { \nia_ok$45 \nia$44 } + assign { $1\nia_ok$next[0:0]$9729 $1\nia$next[63:0]$9728 } { \nia_ok$45 \nia$44 } case - assign $1\nia$next[63:0]$9796 \nia - assign $1\nia_ok$next[0:0]$9797 \nia_ok + assign $1\nia$next[63:0]$9728 \nia + assign $1\nia_ok$next[0:0]$9729 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$9798 1'0 + assign $2\nia_ok$next[0:0]$9730 1'0 case - assign $2\nia_ok$next[0:0]$9798 $1\nia_ok$next[0:0]$9797 + assign $2\nia_ok$next[0:0]$9730 $1\nia_ok$next[0:0]$9729 end sync always - update \nia$next $0\nia$next[63:0]$9794 - update \nia_ok$next $0\nia_ok$next[0:0]$9795 + update \nia$next $0\nia$next[63:0]$9726 + update \nia_ok$next $0\nia_ok$next[0:0]$9727 end - attribute \src "libresoc.v:171254.3-171272.6" - process $proc$libresoc.v:171254$9799 + attribute \src "libresoc.v:172022.3-172040.6" + process $proc$libresoc.v:172022$9731 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\msr$next[63:0]$9800 $1\msr$next[63:0]$9802 + assign $0\msr$next[63:0]$9732 $1\msr$next[63:0]$9734 assign { } { } - assign $0\msr_ok$next[0:0]$9801 $2\msr_ok$next[0:0]$9804 - attribute \src "libresoc.v:171255.5-171255.29" + assign $0\msr_ok$next[0:0]$9733 $2\msr_ok$next[0:0]$9736 + attribute \src "libresoc.v:172023.5-172023.29" switch \initial - attribute \src "libresoc.v:171255.9-171255.17" + attribute \src "libresoc.v:172023.9-172023.17" case 1'1 case end @@ -351797,30 +318340,30 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$9803 $1\msr$next[63:0]$9802 } { \msr_ok$47 \msr$46 } + assign { $1\msr_ok$next[0:0]$9735 $1\msr$next[63:0]$9734 } { \msr_ok$47 \msr$46 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$9803 $1\msr$next[63:0]$9802 } { \msr_ok$47 \msr$46 } + assign { $1\msr_ok$next[0:0]$9735 $1\msr$next[63:0]$9734 } { \msr_ok$47 \msr$46 } case - assign $1\msr$next[63:0]$9802 \msr - assign $1\msr_ok$next[0:0]$9803 \msr_ok + assign $1\msr$next[63:0]$9734 \msr + assign $1\msr_ok$next[0:0]$9735 \msr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_ok$next[0:0]$9804 1'0 + assign $2\msr_ok$next[0:0]$9736 1'0 case - assign $2\msr_ok$next[0:0]$9804 $1\msr_ok$next[0:0]$9803 + assign $2\msr_ok$next[0:0]$9736 $1\msr_ok$next[0:0]$9735 end sync always - update \msr$next $0\msr$next[63:0]$9800 - update \msr_ok$next $0\msr_ok$next[0:0]$9801 + update \msr$next $0\msr$next[63:0]$9732 + update \msr_ok$next $0\msr_ok$next[0:0]$9733 end - connect \$26 $and$libresoc.v:171039$9715_Y + connect \$26 $and$libresoc.v:171807$9647_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } @@ -351840,284 +318383,284 @@ module \pipe2$35 connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:171295.1-172798.10" +attribute \src "libresoc.v:172063.1-173566.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" attribute \generator "nMigen" module \pipe_end - attribute \src "libresoc.v:172636.3-172654.6" - wire width 4 $0\cr_a$next[3:0]$9895 - attribute \src "libresoc.v:172455.3-172456.25" + attribute \src "libresoc.v:173404.3-173422.6" + wire width 4 $0\cr_a$next[3:0]$9827 + attribute \src "libresoc.v:173223.3-173224.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:172636.3-172654.6" - wire $0\cr_a_ok$next[0:0]$9896 - attribute \src "libresoc.v:172457.3-172458.31" + attribute \src "libresoc.v:173404.3-173422.6" + wire $0\cr_a_ok$next[0:0]$9828 + attribute \src "libresoc.v:173225.3-173226.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:171296.7-171296.20" + attribute \src "libresoc.v:172064.7-172064.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172724.3-172765.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$9920 - attribute \src "libresoc.v:172495.3-172496.65" - wire width 4 $0\logical_op__data_len$18[3:0]$9882 - attribute \src "libresoc.v:171337.13-171337.45" - wire width 4 $0\logical_op__data_len$18[3:0]$9966 - attribute \src "libresoc.v:172724.3-172765.6" - wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9921 - attribute \src "libresoc.v:172465.3-172466.61" - wire width 14 $0\logical_op__fn_unit$3[13:0]$9852 - attribute \src "libresoc.v:171376.14-171376.48" - wire width 14 $0\logical_op__fn_unit$3[13:0]$9968 - attribute \src "libresoc.v:172724.3-172765.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9922 - attribute \src "libresoc.v:172467.3-172468.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9854 - attribute \src "libresoc.v:171400.14-171400.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9970 - attribute \src "libresoc.v:172724.3-172765.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$9923 - attribute \src "libresoc.v:172469.3-172470.71" - wire $0\logical_op__imm_data__ok$5[0:0]$9856 - attribute \src "libresoc.v:171409.7-171409.42" - wire $0\logical_op__imm_data__ok$5[0:0]$9972 - attribute \src "libresoc.v:172724.3-172765.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$9924 - attribute \src "libresoc.v:172483.3-172484.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$9870 - attribute \src "libresoc.v:171426.13-171426.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$9974 - attribute \src "libresoc.v:172724.3-172765.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$9925 - attribute \src "libresoc.v:172497.3-172498.57" - wire width 32 $0\logical_op__insn$19[31:0]$9884 - attribute \src "libresoc.v:171439.14-171439.43" - wire width 32 $0\logical_op__insn$19[31:0]$9976 - attribute \src "libresoc.v:172724.3-172765.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$9926 - attribute \src "libresoc.v:172463.3-172464.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$9850 - attribute \src "libresoc.v:171598.13-171598.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$9978 - attribute \src "libresoc.v:172724.3-172765.6" - wire $0\logical_op__invert_in$10$next[0:0]$9927 - attribute \src "libresoc.v:172479.3-172480.67" - wire $0\logical_op__invert_in$10[0:0]$9866 - attribute \src "libresoc.v:171682.7-171682.40" - wire $0\logical_op__invert_in$10[0:0]$9980 - attribute \src "libresoc.v:172724.3-172765.6" - wire $0\logical_op__invert_out$13$next[0:0]$9928 - attribute \src "libresoc.v:172485.3-172486.69" - wire $0\logical_op__invert_out$13[0:0]$9872 - attribute \src "libresoc.v:171691.7-171691.41" - wire $0\logical_op__invert_out$13[0:0]$9982 - attribute \src "libresoc.v:172724.3-172765.6" - wire $0\logical_op__is_32bit$16$next[0:0]$9929 - attribute \src "libresoc.v:172491.3-172492.65" - wire $0\logical_op__is_32bit$16[0:0]$9878 - attribute \src "libresoc.v:171700.7-171700.39" - wire $0\logical_op__is_32bit$16[0:0]$9984 - attribute \src "libresoc.v:172724.3-172765.6" - wire $0\logical_op__is_signed$17$next[0:0]$9930 - attribute \src "libresoc.v:172493.3-172494.67" - wire $0\logical_op__is_signed$17[0:0]$9880 - attribute \src "libresoc.v:171709.7-171709.40" - wire $0\logical_op__is_signed$17[0:0]$9986 - attribute \src "libresoc.v:172724.3-172765.6" - wire $0\logical_op__oe__oe$8$next[0:0]$9931 - attribute \src "libresoc.v:172475.3-172476.59" - wire $0\logical_op__oe__oe$8[0:0]$9862 - attribute \src "libresoc.v:171718.7-171718.36" - wire $0\logical_op__oe__oe$8[0:0]$9988 - attribute \src "libresoc.v:172724.3-172765.6" - wire $0\logical_op__oe__ok$9$next[0:0]$9932 - attribute \src "libresoc.v:172477.3-172478.59" - wire $0\logical_op__oe__ok$9[0:0]$9864 - attribute \src "libresoc.v:171729.7-171729.36" - wire $0\logical_op__oe__ok$9[0:0]$9990 - attribute \src "libresoc.v:172724.3-172765.6" - wire $0\logical_op__output_carry$15$next[0:0]$9933 - attribute \src "libresoc.v:172489.3-172490.73" - wire $0\logical_op__output_carry$15[0:0]$9876 - attribute \src "libresoc.v:171736.7-171736.43" - wire $0\logical_op__output_carry$15[0:0]$9992 - attribute \src "libresoc.v:172724.3-172765.6" - wire $0\logical_op__rc__ok$7$next[0:0]$9934 - attribute \src "libresoc.v:172473.3-172474.59" - wire $0\logical_op__rc__ok$7[0:0]$9860 - attribute \src "libresoc.v:171745.7-171745.36" - wire $0\logical_op__rc__ok$7[0:0]$9994 - attribute \src "libresoc.v:172724.3-172765.6" - wire $0\logical_op__rc__rc$6$next[0:0]$9935 - attribute \src "libresoc.v:172471.3-172472.59" - wire $0\logical_op__rc__rc$6[0:0]$9858 - attribute \src "libresoc.v:171754.7-171754.36" - wire $0\logical_op__rc__rc$6[0:0]$9996 - attribute \src "libresoc.v:172724.3-172765.6" - wire $0\logical_op__write_cr0$14$next[0:0]$9936 - attribute \src "libresoc.v:172487.3-172488.67" - wire $0\logical_op__write_cr0$14[0:0]$9874 - attribute \src "libresoc.v:171763.7-171763.40" - wire $0\logical_op__write_cr0$14[0:0]$9998 - attribute \src "libresoc.v:172724.3-172765.6" - wire $0\logical_op__zero_a$11$next[0:0]$9937 - attribute \src "libresoc.v:171772.7-171772.37" - wire $0\logical_op__zero_a$11[0:0]$10000 - attribute \src "libresoc.v:172481.3-172482.61" - wire $0\logical_op__zero_a$11[0:0]$9868 - attribute \src "libresoc.v:172711.3-172723.6" - wire width 2 $0\muxid$1$next[1:0]$9917 - attribute \src "libresoc.v:171781.13-171781.29" - wire width 2 $0\muxid$1[1:0]$10002 - attribute \src "libresoc.v:172499.3-172500.33" - wire width 2 $0\muxid$1[1:0]$9886 - attribute \src "libresoc.v:172617.3-172635.6" - wire width 64 $0\o$next[63:0]$9889 - attribute \src "libresoc.v:172459.3-172460.19" + attribute \src "libresoc.v:173492.3-173533.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$9852 + attribute \src "libresoc.v:173263.3-173264.65" + wire width 4 $0\logical_op__data_len$18[3:0]$9814 + attribute \src "libresoc.v:172105.13-172105.45" + wire width 4 $0\logical_op__data_len$18[3:0]$9898 + attribute \src "libresoc.v:173492.3-173533.6" + wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9853 + attribute \src "libresoc.v:173233.3-173234.61" + wire width 14 $0\logical_op__fn_unit$3[13:0]$9784 + attribute \src "libresoc.v:172144.14-172144.48" + wire width 14 $0\logical_op__fn_unit$3[13:0]$9900 + attribute \src "libresoc.v:173492.3-173533.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9854 + attribute \src "libresoc.v:173235.3-173236.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9786 + attribute \src "libresoc.v:172168.14-172168.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9902 + attribute \src "libresoc.v:173492.3-173533.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$9855 + attribute \src "libresoc.v:173237.3-173238.71" + wire $0\logical_op__imm_data__ok$5[0:0]$9788 + attribute \src "libresoc.v:172177.7-172177.42" + wire $0\logical_op__imm_data__ok$5[0:0]$9904 + attribute \src "libresoc.v:173492.3-173533.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$9856 + attribute \src "libresoc.v:173251.3-173252.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$9802 + attribute \src "libresoc.v:172194.13-172194.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$9906 + attribute \src "libresoc.v:173492.3-173533.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$9857 + attribute \src "libresoc.v:173265.3-173266.57" + wire width 32 $0\logical_op__insn$19[31:0]$9816 + attribute \src "libresoc.v:172207.14-172207.43" + wire width 32 $0\logical_op__insn$19[31:0]$9908 + attribute \src "libresoc.v:173492.3-173533.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$9858 + attribute \src "libresoc.v:173231.3-173232.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$9782 + attribute \src "libresoc.v:172366.13-172366.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$9910 + attribute \src "libresoc.v:173492.3-173533.6" + wire $0\logical_op__invert_in$10$next[0:0]$9859 + attribute \src "libresoc.v:173247.3-173248.67" + wire $0\logical_op__invert_in$10[0:0]$9798 + attribute \src "libresoc.v:172450.7-172450.40" + wire $0\logical_op__invert_in$10[0:0]$9912 + attribute \src "libresoc.v:173492.3-173533.6" + wire $0\logical_op__invert_out$13$next[0:0]$9860 + attribute \src "libresoc.v:173253.3-173254.69" + wire $0\logical_op__invert_out$13[0:0]$9804 + attribute \src "libresoc.v:172459.7-172459.41" + wire $0\logical_op__invert_out$13[0:0]$9914 + attribute \src "libresoc.v:173492.3-173533.6" + wire $0\logical_op__is_32bit$16$next[0:0]$9861 + attribute \src "libresoc.v:173259.3-173260.65" + wire $0\logical_op__is_32bit$16[0:0]$9810 + attribute \src "libresoc.v:172468.7-172468.39" + wire $0\logical_op__is_32bit$16[0:0]$9916 + attribute \src "libresoc.v:173492.3-173533.6" + wire $0\logical_op__is_signed$17$next[0:0]$9862 + attribute \src "libresoc.v:173261.3-173262.67" + wire $0\logical_op__is_signed$17[0:0]$9812 + attribute \src "libresoc.v:172477.7-172477.40" + wire $0\logical_op__is_signed$17[0:0]$9918 + attribute \src "libresoc.v:173492.3-173533.6" + wire $0\logical_op__oe__oe$8$next[0:0]$9863 + attribute \src "libresoc.v:173243.3-173244.59" + wire $0\logical_op__oe__oe$8[0:0]$9794 + attribute \src "libresoc.v:172486.7-172486.36" + wire $0\logical_op__oe__oe$8[0:0]$9920 + attribute \src "libresoc.v:173492.3-173533.6" + wire $0\logical_op__oe__ok$9$next[0:0]$9864 + attribute \src "libresoc.v:173245.3-173246.59" + wire $0\logical_op__oe__ok$9[0:0]$9796 + attribute \src "libresoc.v:172497.7-172497.36" + wire $0\logical_op__oe__ok$9[0:0]$9922 + attribute \src "libresoc.v:173492.3-173533.6" + wire $0\logical_op__output_carry$15$next[0:0]$9865 + attribute \src "libresoc.v:173257.3-173258.73" + wire $0\logical_op__output_carry$15[0:0]$9808 + attribute \src "libresoc.v:172504.7-172504.43" + wire $0\logical_op__output_carry$15[0:0]$9924 + attribute \src "libresoc.v:173492.3-173533.6" + wire $0\logical_op__rc__ok$7$next[0:0]$9866 + attribute \src "libresoc.v:173241.3-173242.59" + wire $0\logical_op__rc__ok$7[0:0]$9792 + attribute \src "libresoc.v:172513.7-172513.36" + wire $0\logical_op__rc__ok$7[0:0]$9926 + attribute \src "libresoc.v:173492.3-173533.6" + wire $0\logical_op__rc__rc$6$next[0:0]$9867 + attribute \src "libresoc.v:173239.3-173240.59" + wire $0\logical_op__rc__rc$6[0:0]$9790 + attribute \src "libresoc.v:172522.7-172522.36" + wire $0\logical_op__rc__rc$6[0:0]$9928 + attribute \src "libresoc.v:173492.3-173533.6" + wire $0\logical_op__write_cr0$14$next[0:0]$9868 + attribute \src "libresoc.v:173255.3-173256.67" + wire $0\logical_op__write_cr0$14[0:0]$9806 + attribute \src "libresoc.v:172531.7-172531.40" + wire $0\logical_op__write_cr0$14[0:0]$9930 + attribute \src "libresoc.v:173492.3-173533.6" + wire $0\logical_op__zero_a$11$next[0:0]$9869 + attribute \src "libresoc.v:173249.3-173250.61" + wire $0\logical_op__zero_a$11[0:0]$9800 + attribute \src "libresoc.v:172540.7-172540.37" + wire $0\logical_op__zero_a$11[0:0]$9932 + attribute \src "libresoc.v:173479.3-173491.6" + wire width 2 $0\muxid$1$next[1:0]$9849 + attribute \src "libresoc.v:173267.3-173268.33" + wire width 2 $0\muxid$1[1:0]$9818 + attribute \src "libresoc.v:172549.13-172549.29" + wire width 2 $0\muxid$1[1:0]$9934 + attribute \src "libresoc.v:173385.3-173403.6" + wire width 64 $0\o$next[63:0]$9821 + attribute \src "libresoc.v:173227.3-173228.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:172617.3-172635.6" - wire $0\o_ok$next[0:0]$9890 - attribute \src "libresoc.v:172461.3-172462.25" + attribute \src "libresoc.v:173385.3-173403.6" + wire $0\o_ok$next[0:0]$9822 + attribute \src "libresoc.v:173229.3-173230.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:172693.3-172710.6" - wire $0\r_busy$next[0:0]$9913 - attribute \src "libresoc.v:172501.3-172502.29" + attribute \src "libresoc.v:173461.3-173478.6" + wire $0\r_busy$next[0:0]$9845 + attribute \src "libresoc.v:173269.3-173270.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:172655.3-172673.6" - wire width 2 $0\xer_ov$next[1:0]$9901 - attribute \src "libresoc.v:172451.3-172452.29" + attribute \src "libresoc.v:173423.3-173441.6" + wire width 2 $0\xer_ov$next[1:0]$9833 + attribute \src "libresoc.v:173219.3-173220.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:172655.3-172673.6" - wire $0\xer_ov_ok$next[0:0]$9902 - attribute \src "libresoc.v:172453.3-172454.35" + attribute \src "libresoc.v:173423.3-173441.6" + wire $0\xer_ov_ok$next[0:0]$9834 + attribute \src "libresoc.v:173221.3-173222.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:172674.3-172692.6" - wire $0\xer_so$20$next[0:0]$9908 - attribute \src "libresoc.v:172432.7-172432.25" - wire $0\xer_so$20[0:0]$10009 - attribute \src "libresoc.v:172447.3-172448.37" - wire $0\xer_so$20[0:0]$9841 - attribute \src "libresoc.v:172674.3-172692.6" - wire $0\xer_so_ok$next[0:0]$9907 - attribute \src "libresoc.v:172449.3-172450.35" + attribute \src "libresoc.v:173442.3-173460.6" + wire $0\xer_so$20$next[0:0]$9840 + attribute \src "libresoc.v:173215.3-173216.37" + wire $0\xer_so$20[0:0]$9773 + attribute \src "libresoc.v:173200.7-173200.25" + wire $0\xer_so$20[0:0]$9941 + attribute \src "libresoc.v:173442.3-173460.6" + wire $0\xer_so_ok$next[0:0]$9839 + attribute \src "libresoc.v:173217.3-173218.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:172636.3-172654.6" - wire width 4 $1\cr_a$next[3:0]$9897 - attribute \src "libresoc.v:171305.13-171305.24" + attribute \src "libresoc.v:173404.3-173422.6" + wire width 4 $1\cr_a$next[3:0]$9829 + attribute \src "libresoc.v:172073.13-172073.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:172636.3-172654.6" - wire $1\cr_a_ok$next[0:0]$9898 - attribute \src "libresoc.v:171314.7-171314.21" + attribute \src "libresoc.v:173404.3-173422.6" + wire $1\cr_a_ok$next[0:0]$9830 + attribute \src "libresoc.v:172082.7-172082.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:172724.3-172765.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$9938 - attribute \src "libresoc.v:172724.3-172765.6" - wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9939 - attribute \src "libresoc.v:172724.3-172765.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9940 - attribute \src "libresoc.v:172724.3-172765.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$9941 - attribute \src "libresoc.v:172724.3-172765.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$9942 - attribute \src "libresoc.v:172724.3-172765.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$9943 - attribute \src "libresoc.v:172724.3-172765.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$9944 - attribute \src "libresoc.v:172724.3-172765.6" - wire $1\logical_op__invert_in$10$next[0:0]$9945 - attribute \src "libresoc.v:172724.3-172765.6" - wire $1\logical_op__invert_out$13$next[0:0]$9946 - attribute \src "libresoc.v:172724.3-172765.6" - wire $1\logical_op__is_32bit$16$next[0:0]$9947 - attribute \src "libresoc.v:172724.3-172765.6" - wire $1\logical_op__is_signed$17$next[0:0]$9948 - attribute \src "libresoc.v:172724.3-172765.6" - wire $1\logical_op__oe__oe$8$next[0:0]$9949 - attribute \src "libresoc.v:172724.3-172765.6" - wire $1\logical_op__oe__ok$9$next[0:0]$9950 - attribute \src "libresoc.v:172724.3-172765.6" - wire $1\logical_op__output_carry$15$next[0:0]$9951 - attribute \src "libresoc.v:172724.3-172765.6" - wire $1\logical_op__rc__ok$7$next[0:0]$9952 - attribute \src "libresoc.v:172724.3-172765.6" - wire $1\logical_op__rc__rc$6$next[0:0]$9953 - attribute \src "libresoc.v:172724.3-172765.6" - wire $1\logical_op__write_cr0$14$next[0:0]$9954 - attribute \src "libresoc.v:172724.3-172765.6" - wire $1\logical_op__zero_a$11$next[0:0]$9955 - attribute \src "libresoc.v:172711.3-172723.6" - wire width 2 $1\muxid$1$next[1:0]$9918 - attribute \src "libresoc.v:172617.3-172635.6" - wire width 64 $1\o$next[63:0]$9891 - attribute \src "libresoc.v:171794.14-171794.38" + attribute \src "libresoc.v:173492.3-173533.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$9870 + attribute \src "libresoc.v:173492.3-173533.6" + wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9871 + attribute \src "libresoc.v:173492.3-173533.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9872 + attribute \src "libresoc.v:173492.3-173533.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$9873 + attribute \src "libresoc.v:173492.3-173533.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$9874 + attribute \src "libresoc.v:173492.3-173533.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$9875 + attribute \src "libresoc.v:173492.3-173533.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$9876 + attribute \src "libresoc.v:173492.3-173533.6" + wire $1\logical_op__invert_in$10$next[0:0]$9877 + attribute \src "libresoc.v:173492.3-173533.6" + wire $1\logical_op__invert_out$13$next[0:0]$9878 + attribute \src "libresoc.v:173492.3-173533.6" + wire $1\logical_op__is_32bit$16$next[0:0]$9879 + attribute \src "libresoc.v:173492.3-173533.6" + wire $1\logical_op__is_signed$17$next[0:0]$9880 + attribute \src "libresoc.v:173492.3-173533.6" + wire $1\logical_op__oe__oe$8$next[0:0]$9881 + attribute \src "libresoc.v:173492.3-173533.6" + wire $1\logical_op__oe__ok$9$next[0:0]$9882 + attribute \src "libresoc.v:173492.3-173533.6" + wire $1\logical_op__output_carry$15$next[0:0]$9883 + attribute \src "libresoc.v:173492.3-173533.6" + wire $1\logical_op__rc__ok$7$next[0:0]$9884 + attribute \src "libresoc.v:173492.3-173533.6" + wire $1\logical_op__rc__rc$6$next[0:0]$9885 + attribute \src "libresoc.v:173492.3-173533.6" + wire $1\logical_op__write_cr0$14$next[0:0]$9886 + attribute \src "libresoc.v:173492.3-173533.6" + wire $1\logical_op__zero_a$11$next[0:0]$9887 + attribute \src "libresoc.v:173479.3-173491.6" + wire width 2 $1\muxid$1$next[1:0]$9850 + attribute \src "libresoc.v:173385.3-173403.6" + wire width 64 $1\o$next[63:0]$9823 + attribute \src "libresoc.v:172562.14-172562.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:172617.3-172635.6" - wire $1\o_ok$next[0:0]$9892 - attribute \src "libresoc.v:171801.7-171801.18" + attribute \src "libresoc.v:173385.3-173403.6" + wire $1\o_ok$next[0:0]$9824 + attribute \src "libresoc.v:172569.7-172569.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:172693.3-172710.6" - wire $1\r_busy$next[0:0]$9914 - attribute \src "libresoc.v:172397.7-172397.20" + attribute \src "libresoc.v:173461.3-173478.6" + wire $1\r_busy$next[0:0]$9846 + attribute \src "libresoc.v:173165.7-173165.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:172655.3-172673.6" - wire width 2 $1\xer_ov$next[1:0]$9903 - attribute \src "libresoc.v:172412.13-172412.26" + attribute \src "libresoc.v:173423.3-173441.6" + wire width 2 $1\xer_ov$next[1:0]$9835 + attribute \src "libresoc.v:173180.13-173180.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:172655.3-172673.6" - wire $1\xer_ov_ok$next[0:0]$9904 - attribute \src "libresoc.v:172419.7-172419.23" + attribute \src "libresoc.v:173423.3-173441.6" + wire $1\xer_ov_ok$next[0:0]$9836 + attribute \src "libresoc.v:173187.7-173187.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:172674.3-172692.6" - wire $1\xer_so$20$next[0:0]$9910 - attribute \src "libresoc.v:172674.3-172692.6" - wire $1\xer_so_ok$next[0:0]$9909 - attribute \src "libresoc.v:172437.7-172437.23" + attribute \src "libresoc.v:173442.3-173460.6" + wire $1\xer_so$20$next[0:0]$9842 + attribute \src "libresoc.v:173442.3-173460.6" + wire $1\xer_so_ok$next[0:0]$9841 + attribute \src "libresoc.v:173205.7-173205.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:172636.3-172654.6" - wire $2\cr_a_ok$next[0:0]$9899 - attribute \src "libresoc.v:172724.3-172765.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9956 - attribute \src "libresoc.v:172724.3-172765.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$9957 - attribute \src "libresoc.v:172724.3-172765.6" - wire $2\logical_op__oe__oe$8$next[0:0]$9958 - attribute \src "libresoc.v:172724.3-172765.6" - wire $2\logical_op__oe__ok$9$next[0:0]$9959 - attribute \src "libresoc.v:172724.3-172765.6" - wire $2\logical_op__rc__ok$7$next[0:0]$9960 - attribute \src "libresoc.v:172724.3-172765.6" - wire $2\logical_op__rc__rc$6$next[0:0]$9961 - attribute \src "libresoc.v:172617.3-172635.6" - wire $2\o_ok$next[0:0]$9893 - attribute \src "libresoc.v:172693.3-172710.6" - wire $2\r_busy$next[0:0]$9915 - attribute \src "libresoc.v:172655.3-172673.6" - wire $2\xer_ov_ok$next[0:0]$9905 - attribute \src "libresoc.v:172674.3-172692.6" - wire $2\xer_so_ok$next[0:0]$9911 - attribute \src "libresoc.v:172446.18-172446.118" - wire $and$libresoc.v:172446$9839_Y + attribute \src "libresoc.v:173404.3-173422.6" + wire $2\cr_a_ok$next[0:0]$9831 + attribute \src "libresoc.v:173492.3-173533.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9888 + attribute \src "libresoc.v:173492.3-173533.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$9889 + attribute \src "libresoc.v:173492.3-173533.6" + wire $2\logical_op__oe__oe$8$next[0:0]$9890 + attribute \src "libresoc.v:173492.3-173533.6" + wire $2\logical_op__oe__ok$9$next[0:0]$9891 + attribute \src "libresoc.v:173492.3-173533.6" + wire $2\logical_op__rc__ok$7$next[0:0]$9892 + attribute \src "libresoc.v:173492.3-173533.6" + wire $2\logical_op__rc__rc$6$next[0:0]$9893 + attribute \src "libresoc.v:173385.3-173403.6" + wire $2\o_ok$next[0:0]$9825 + attribute \src "libresoc.v:173461.3-173478.6" + wire $2\r_busy$next[0:0]$9847 + attribute \src "libresoc.v:173423.3-173441.6" + wire $2\xer_ov_ok$next[0:0]$9837 + attribute \src "libresoc.v:173442.3-173460.6" + wire $2\xer_so_ok$next[0:0]$9843 + attribute \src "libresoc.v:173214.18-173214.118" + wire $and$libresoc.v:173214$9771_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 62 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 56 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 57 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire input 30 \div_by_zero @@ -352129,7 +318672,7 @@ module \pipe_end wire input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 26 \divisor_neg - attribute \src "libresoc.v:171296.7-171296.15" + attribute \src "libresoc.v:172064.7-172064.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -352571,23 +319114,23 @@ module \pipe_end wire input 34 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 33 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 54 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 55 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_logical_op__data_len @@ -352853,13 +319396,13 @@ module \pipe_end wire width 2 \output_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \output_stage_div_by_zero @@ -353135,33 +319678,33 @@ module \pipe_end wire width 2 \output_stage_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_stage_muxid$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_stage_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_stage_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" wire width 64 \output_stage_quotient_root attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" wire width 192 \output_stage_remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_stage_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_stage_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \output_stage_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_stage_xer_so$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ov$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o @@ -353187,40 +319730,40 @@ module \pipe_end wire width 64 \rb$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" wire width 192 input 32 \remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 58 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 59 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 60 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 61 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:172446$9839 + cell $and $and$libresoc.v:173214$9771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -353228,16 +319771,16 @@ module \pipe_end parameter \Y_WIDTH 1 connect \A \p_valid_i$73 connect \B \p_ready_o - connect \Y $and$libresoc.v:172446$9839_Y + connect \Y $and$libresoc.v:173214$9771_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:172503.10-172506.4" + attribute \src "libresoc.v:173271.10-173274.4" cell \n$82 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:172507.15-172559.4" + attribute \src "libresoc.v:173275.15-173327.4" cell \output$83 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$62 @@ -353292,7 +319835,7 @@ module \pipe_end connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:172560.16-172612.4" + attribute \src "libresoc.v:173328.16-173380.4" cell \output_stage \output_stage connect \div_by_zero \output_stage_div_by_zero connect \dive_abs_ov32 \output_stage_dive_abs_ov32 @@ -353347,451 +319890,451 @@ module \pipe_end connect \xer_so$20 \output_stage_xer_so$40 end attribute \module_not_derived 1 - attribute \src "libresoc.v:172613.10-172616.4" + attribute \src "libresoc.v:173381.10-173384.4" cell \p$81 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:171296.7-171296.20" - process $proc$libresoc.v:171296$9962 + attribute \src "libresoc.v:172064.7-172064.20" + process $proc$libresoc.v:172064$9894 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171305.13-171305.24" - process $proc$libresoc.v:171305$9963 + attribute \src "libresoc.v:172073.13-172073.24" + process $proc$libresoc.v:172073$9895 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:171314.7-171314.21" - process $proc$libresoc.v:171314$9964 + attribute \src "libresoc.v:172082.7-172082.21" + process $proc$libresoc.v:172082$9896 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:171337.13-171337.45" - process $proc$libresoc.v:171337$9965 + attribute \src "libresoc.v:172105.13-172105.45" + process $proc$libresoc.v:172105$9897 assign { } { } - assign $0\logical_op__data_len$18[3:0]$9966 4'0000 + assign $0\logical_op__data_len$18[3:0]$9898 4'0000 sync always sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9966 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9898 end - attribute \src "libresoc.v:171376.14-171376.48" - process $proc$libresoc.v:171376$9967 + attribute \src "libresoc.v:172144.14-172144.48" + process $proc$libresoc.v:172144$9899 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$9968 14'00000000000000 + assign $0\logical_op__fn_unit$3[13:0]$9900 14'00000000000000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9968 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9900 end - attribute \src "libresoc.v:171400.14-171400.67" - process $proc$libresoc.v:171400$9969 + attribute \src "libresoc.v:172168.14-172168.67" + process $proc$libresoc.v:172168$9901 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9970 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$4[63:0]$9902 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9970 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9902 end - attribute \src "libresoc.v:171409.7-171409.42" - process $proc$libresoc.v:171409$9971 + attribute \src "libresoc.v:172177.7-172177.42" + process $proc$libresoc.v:172177$9903 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9972 1'0 + assign $0\logical_op__imm_data__ok$5[0:0]$9904 1'0 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9972 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9904 end - attribute \src "libresoc.v:171426.13-171426.48" - process $proc$libresoc.v:171426$9973 + attribute \src "libresoc.v:172194.13-172194.48" + process $proc$libresoc.v:172194$9905 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9974 2'00 + assign $0\logical_op__input_carry$12[1:0]$9906 2'00 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9974 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9906 end - attribute \src "libresoc.v:171439.14-171439.43" - process $proc$libresoc.v:171439$9975 + attribute \src "libresoc.v:172207.14-172207.43" + process $proc$libresoc.v:172207$9907 assign { } { } - assign $0\logical_op__insn$19[31:0]$9976 0 + assign $0\logical_op__insn$19[31:0]$9908 0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9976 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9908 end - attribute \src "libresoc.v:171598.13-171598.46" - process $proc$libresoc.v:171598$9977 + attribute \src "libresoc.v:172366.13-172366.46" + process $proc$libresoc.v:172366$9909 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9978 7'0000000 + assign $0\logical_op__insn_type$2[6:0]$9910 7'0000000 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9978 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9910 end - attribute \src "libresoc.v:171682.7-171682.40" - process $proc$libresoc.v:171682$9979 + attribute \src "libresoc.v:172450.7-172450.40" + process $proc$libresoc.v:172450$9911 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9980 1'0 + assign $0\logical_op__invert_in$10[0:0]$9912 1'0 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9980 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9912 end - attribute \src "libresoc.v:171691.7-171691.41" - process $proc$libresoc.v:171691$9981 + attribute \src "libresoc.v:172459.7-172459.41" + process $proc$libresoc.v:172459$9913 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9982 1'0 + assign $0\logical_op__invert_out$13[0:0]$9914 1'0 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9982 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9914 end - attribute \src "libresoc.v:171700.7-171700.39" - process $proc$libresoc.v:171700$9983 + attribute \src "libresoc.v:172468.7-172468.39" + process $proc$libresoc.v:172468$9915 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9984 1'0 + assign $0\logical_op__is_32bit$16[0:0]$9916 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9984 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9916 end - attribute \src "libresoc.v:171709.7-171709.40" - process $proc$libresoc.v:171709$9985 + attribute \src "libresoc.v:172477.7-172477.40" + process $proc$libresoc.v:172477$9917 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9986 1'0 + assign $0\logical_op__is_signed$17[0:0]$9918 1'0 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9986 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9918 end - attribute \src "libresoc.v:171718.7-171718.36" - process $proc$libresoc.v:171718$9987 + attribute \src "libresoc.v:172486.7-172486.36" + process $proc$libresoc.v:172486$9919 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9988 1'0 + assign $0\logical_op__oe__oe$8[0:0]$9920 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9988 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9920 end - attribute \src "libresoc.v:171729.7-171729.36" - process $proc$libresoc.v:171729$9989 + attribute \src "libresoc.v:172497.7-172497.36" + process $proc$libresoc.v:172497$9921 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9990 1'0 + assign $0\logical_op__oe__ok$9[0:0]$9922 1'0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9990 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9922 end - attribute \src "libresoc.v:171736.7-171736.43" - process $proc$libresoc.v:171736$9991 + attribute \src "libresoc.v:172504.7-172504.43" + process $proc$libresoc.v:172504$9923 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9992 1'0 + assign $0\logical_op__output_carry$15[0:0]$9924 1'0 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9992 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9924 end - attribute \src "libresoc.v:171745.7-171745.36" - process $proc$libresoc.v:171745$9993 + attribute \src "libresoc.v:172513.7-172513.36" + process $proc$libresoc.v:172513$9925 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9994 1'0 + assign $0\logical_op__rc__ok$7[0:0]$9926 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9994 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9926 end - attribute \src "libresoc.v:171754.7-171754.36" - process $proc$libresoc.v:171754$9995 + attribute \src "libresoc.v:172522.7-172522.36" + process $proc$libresoc.v:172522$9927 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9996 1'0 + assign $0\logical_op__rc__rc$6[0:0]$9928 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9996 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9928 end - attribute \src "libresoc.v:171763.7-171763.40" - process $proc$libresoc.v:171763$9997 + attribute \src "libresoc.v:172531.7-172531.40" + process $proc$libresoc.v:172531$9929 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9998 1'0 + assign $0\logical_op__write_cr0$14[0:0]$9930 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9998 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9930 end - attribute \src "libresoc.v:171772.7-171772.37" - process $proc$libresoc.v:171772$9999 + attribute \src "libresoc.v:172540.7-172540.37" + process $proc$libresoc.v:172540$9931 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$10000 1'0 + assign $0\logical_op__zero_a$11[0:0]$9932 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$10000 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9932 end - attribute \src "libresoc.v:171781.13-171781.29" - process $proc$libresoc.v:171781$10001 + attribute \src "libresoc.v:172549.13-172549.29" + process $proc$libresoc.v:172549$9933 assign { } { } - assign $0\muxid$1[1:0]$10002 2'00 + assign $0\muxid$1[1:0]$9934 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$10002 + update \muxid$1 $0\muxid$1[1:0]$9934 end - attribute \src "libresoc.v:171794.14-171794.38" - process $proc$libresoc.v:171794$10003 + attribute \src "libresoc.v:172562.14-172562.38" + process $proc$libresoc.v:172562$9935 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:171801.7-171801.18" - process $proc$libresoc.v:171801$10004 + attribute \src "libresoc.v:172569.7-172569.18" + process $proc$libresoc.v:172569$9936 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:172397.7-172397.20" - process $proc$libresoc.v:172397$10005 + attribute \src "libresoc.v:173165.7-173165.20" + process $proc$libresoc.v:173165$9937 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:172412.13-172412.26" - process $proc$libresoc.v:172412$10006 + attribute \src "libresoc.v:173180.13-173180.26" + process $proc$libresoc.v:173180$9938 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:172419.7-172419.23" - process $proc$libresoc.v:172419$10007 + attribute \src "libresoc.v:173187.7-173187.23" + process $proc$libresoc.v:173187$9939 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:172432.7-172432.25" - process $proc$libresoc.v:172432$10008 + attribute \src "libresoc.v:173200.7-173200.25" + process $proc$libresoc.v:173200$9940 assign { } { } - assign $0\xer_so$20[0:0]$10009 1'0 + assign $0\xer_so$20[0:0]$9941 1'0 sync always sync init - update \xer_so$20 $0\xer_so$20[0:0]$10009 + update \xer_so$20 $0\xer_so$20[0:0]$9941 end - attribute \src "libresoc.v:172437.7-172437.23" - process $proc$libresoc.v:172437$10010 + attribute \src "libresoc.v:173205.7-173205.23" + process $proc$libresoc.v:173205$9942 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:172447.3-172448.37" - process $proc$libresoc.v:172447$9840 + attribute \src "libresoc.v:173215.3-173216.37" + process $proc$libresoc.v:173215$9772 assign { } { } - assign $0\xer_so$20[0:0]$9841 \xer_so$20$next + assign $0\xer_so$20[0:0]$9773 \xer_so$20$next sync posedge \coresync_clk - update \xer_so$20 $0\xer_so$20[0:0]$9841 + update \xer_so$20 $0\xer_so$20[0:0]$9773 end - attribute \src "libresoc.v:172449.3-172450.35" - process $proc$libresoc.v:172449$9842 + attribute \src "libresoc.v:173217.3-173218.35" + process $proc$libresoc.v:173217$9774 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:172451.3-172452.29" - process $proc$libresoc.v:172451$9843 + attribute \src "libresoc.v:173219.3-173220.29" + process $proc$libresoc.v:173219$9775 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:172453.3-172454.35" - process $proc$libresoc.v:172453$9844 + attribute \src "libresoc.v:173221.3-173222.35" + process $proc$libresoc.v:173221$9776 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:172455.3-172456.25" - process $proc$libresoc.v:172455$9845 + attribute \src "libresoc.v:173223.3-173224.25" + process $proc$libresoc.v:173223$9777 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:172457.3-172458.31" - process $proc$libresoc.v:172457$9846 + attribute \src "libresoc.v:173225.3-173226.31" + process $proc$libresoc.v:173225$9778 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:172459.3-172460.19" - process $proc$libresoc.v:172459$9847 + attribute \src "libresoc.v:173227.3-173228.19" + process $proc$libresoc.v:173227$9779 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:172461.3-172462.25" - process $proc$libresoc.v:172461$9848 + attribute \src "libresoc.v:173229.3-173230.25" + process $proc$libresoc.v:173229$9780 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:172463.3-172464.65" - process $proc$libresoc.v:172463$9849 + attribute \src "libresoc.v:173231.3-173232.65" + process $proc$libresoc.v:173231$9781 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9850 \logical_op__insn_type$2$next + assign $0\logical_op__insn_type$2[6:0]$9782 \logical_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9850 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9782 end - attribute \src "libresoc.v:172465.3-172466.61" - process $proc$libresoc.v:172465$9851 + attribute \src "libresoc.v:173233.3-173234.61" + process $proc$libresoc.v:173233$9783 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$9852 \logical_op__fn_unit$3$next + assign $0\logical_op__fn_unit$3[13:0]$9784 \logical_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9852 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9784 end - attribute \src "libresoc.v:172467.3-172468.75" - process $proc$libresoc.v:172467$9853 + attribute \src "libresoc.v:173235.3-173236.75" + process $proc$libresoc.v:173235$9785 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9854 \logical_op__imm_data__data$4$next + assign $0\logical_op__imm_data__data$4[63:0]$9786 \logical_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9854 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9786 end - attribute \src "libresoc.v:172469.3-172470.71" - process $proc$libresoc.v:172469$9855 + attribute \src "libresoc.v:173237.3-173238.71" + process $proc$libresoc.v:173237$9787 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9856 \logical_op__imm_data__ok$5$next + assign $0\logical_op__imm_data__ok$5[0:0]$9788 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9856 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9788 end - attribute \src "libresoc.v:172471.3-172472.59" - process $proc$libresoc.v:172471$9857 + attribute \src "libresoc.v:173239.3-173240.59" + process $proc$libresoc.v:173239$9789 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9858 \logical_op__rc__rc$6$next + assign $0\logical_op__rc__rc$6[0:0]$9790 \logical_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9858 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9790 end - attribute \src "libresoc.v:172473.3-172474.59" - process $proc$libresoc.v:172473$9859 + attribute \src "libresoc.v:173241.3-173242.59" + process $proc$libresoc.v:173241$9791 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9860 \logical_op__rc__ok$7$next + assign $0\logical_op__rc__ok$7[0:0]$9792 \logical_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9860 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9792 end - attribute \src "libresoc.v:172475.3-172476.59" - process $proc$libresoc.v:172475$9861 + attribute \src "libresoc.v:173243.3-173244.59" + process $proc$libresoc.v:173243$9793 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9862 \logical_op__oe__oe$8$next + assign $0\logical_op__oe__oe$8[0:0]$9794 \logical_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9862 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9794 end - attribute \src "libresoc.v:172477.3-172478.59" - process $proc$libresoc.v:172477$9863 + attribute \src "libresoc.v:173245.3-173246.59" + process $proc$libresoc.v:173245$9795 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9864 \logical_op__oe__ok$9$next + assign $0\logical_op__oe__ok$9[0:0]$9796 \logical_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9864 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9796 end - attribute \src "libresoc.v:172479.3-172480.67" - process $proc$libresoc.v:172479$9865 + attribute \src "libresoc.v:173247.3-173248.67" + process $proc$libresoc.v:173247$9797 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9866 \logical_op__invert_in$10$next + assign $0\logical_op__invert_in$10[0:0]$9798 \logical_op__invert_in$10$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9866 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9798 end - attribute \src "libresoc.v:172481.3-172482.61" - process $proc$libresoc.v:172481$9867 + attribute \src "libresoc.v:173249.3-173250.61" + process $proc$libresoc.v:173249$9799 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9868 \logical_op__zero_a$11$next + assign $0\logical_op__zero_a$11[0:0]$9800 \logical_op__zero_a$11$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9868 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9800 end - attribute \src "libresoc.v:172483.3-172484.71" - process $proc$libresoc.v:172483$9869 + attribute \src "libresoc.v:173251.3-173252.71" + process $proc$libresoc.v:173251$9801 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9870 \logical_op__input_carry$12$next + assign $0\logical_op__input_carry$12[1:0]$9802 \logical_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9870 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9802 end - attribute \src "libresoc.v:172485.3-172486.69" - process $proc$libresoc.v:172485$9871 + attribute \src "libresoc.v:173253.3-173254.69" + process $proc$libresoc.v:173253$9803 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9872 \logical_op__invert_out$13$next + assign $0\logical_op__invert_out$13[0:0]$9804 \logical_op__invert_out$13$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9872 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9804 end - attribute \src "libresoc.v:172487.3-172488.67" - process $proc$libresoc.v:172487$9873 + attribute \src "libresoc.v:173255.3-173256.67" + process $proc$libresoc.v:173255$9805 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9874 \logical_op__write_cr0$14$next + assign $0\logical_op__write_cr0$14[0:0]$9806 \logical_op__write_cr0$14$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9874 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9806 end - attribute \src "libresoc.v:172489.3-172490.73" - process $proc$libresoc.v:172489$9875 + attribute \src "libresoc.v:173257.3-173258.73" + process $proc$libresoc.v:173257$9807 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9876 \logical_op__output_carry$15$next + assign $0\logical_op__output_carry$15[0:0]$9808 \logical_op__output_carry$15$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9876 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9808 end - attribute \src "libresoc.v:172491.3-172492.65" - process $proc$libresoc.v:172491$9877 + attribute \src "libresoc.v:173259.3-173260.65" + process $proc$libresoc.v:173259$9809 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9878 \logical_op__is_32bit$16$next + assign $0\logical_op__is_32bit$16[0:0]$9810 \logical_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9878 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9810 end - attribute \src "libresoc.v:172493.3-172494.67" - process $proc$libresoc.v:172493$9879 + attribute \src "libresoc.v:173261.3-173262.67" + process $proc$libresoc.v:173261$9811 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9880 \logical_op__is_signed$17$next + assign $0\logical_op__is_signed$17[0:0]$9812 \logical_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9880 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9812 end - attribute \src "libresoc.v:172495.3-172496.65" - process $proc$libresoc.v:172495$9881 + attribute \src "libresoc.v:173263.3-173264.65" + process $proc$libresoc.v:173263$9813 assign { } { } - assign $0\logical_op__data_len$18[3:0]$9882 \logical_op__data_len$18$next + assign $0\logical_op__data_len$18[3:0]$9814 \logical_op__data_len$18$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9882 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9814 end - attribute \src "libresoc.v:172497.3-172498.57" - process $proc$libresoc.v:172497$9883 + attribute \src "libresoc.v:173265.3-173266.57" + process $proc$libresoc.v:173265$9815 assign { } { } - assign $0\logical_op__insn$19[31:0]$9884 \logical_op__insn$19$next + assign $0\logical_op__insn$19[31:0]$9816 \logical_op__insn$19$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9884 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9816 end - attribute \src "libresoc.v:172499.3-172500.33" - process $proc$libresoc.v:172499$9885 + attribute \src "libresoc.v:173267.3-173268.33" + process $proc$libresoc.v:173267$9817 assign { } { } - assign $0\muxid$1[1:0]$9886 \muxid$1$next + assign $0\muxid$1[1:0]$9818 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9886 + update \muxid$1 $0\muxid$1[1:0]$9818 end - attribute \src "libresoc.v:172501.3-172502.29" - process $proc$libresoc.v:172501$9887 + attribute \src "libresoc.v:173269.3-173270.29" + process $proc$libresoc.v:173269$9819 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:172617.3-172635.6" - process $proc$libresoc.v:172617$9888 + attribute \src "libresoc.v:173385.3-173403.6" + process $proc$libresoc.v:173385$9820 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9889 $1\o$next[63:0]$9891 + assign $0\o$next[63:0]$9821 $1\o$next[63:0]$9823 assign { } { } - assign $0\o_ok$next[0:0]$9890 $2\o_ok$next[0:0]$9893 - attribute \src "libresoc.v:172618.5-172618.29" + assign $0\o_ok$next[0:0]$9822 $2\o_ok$next[0:0]$9825 + attribute \src "libresoc.v:173386.5-173386.29" switch \initial - attribute \src "libresoc.v:172618.9-172618.17" + attribute \src "libresoc.v:173386.9-173386.17" case 1'1 case end @@ -353801,41 +320344,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9892 $1\o$next[63:0]$9891 } { \o_ok$96 \o$95 } + assign { $1\o_ok$next[0:0]$9824 $1\o$next[63:0]$9823 } { \o_ok$96 \o$95 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9892 $1\o$next[63:0]$9891 } { \o_ok$96 \o$95 } + assign { $1\o_ok$next[0:0]$9824 $1\o$next[63:0]$9823 } { \o_ok$96 \o$95 } case - assign $1\o$next[63:0]$9891 \o - assign $1\o_ok$next[0:0]$9892 \o_ok + assign $1\o$next[63:0]$9823 \o + assign $1\o_ok$next[0:0]$9824 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9893 1'0 + assign $2\o_ok$next[0:0]$9825 1'0 case - assign $2\o_ok$next[0:0]$9893 $1\o_ok$next[0:0]$9892 + assign $2\o_ok$next[0:0]$9825 $1\o_ok$next[0:0]$9824 end sync always - update \o$next $0\o$next[63:0]$9889 - update \o_ok$next $0\o_ok$next[0:0]$9890 + update \o$next $0\o$next[63:0]$9821 + update \o_ok$next $0\o_ok$next[0:0]$9822 end - attribute \src "libresoc.v:172636.3-172654.6" - process $proc$libresoc.v:172636$9894 + attribute \src "libresoc.v:173404.3-173422.6" + process $proc$libresoc.v:173404$9826 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9895 $1\cr_a$next[3:0]$9897 + assign $0\cr_a$next[3:0]$9827 $1\cr_a$next[3:0]$9829 assign { } { } - assign $0\cr_a_ok$next[0:0]$9896 $2\cr_a_ok$next[0:0]$9899 - attribute \src "libresoc.v:172637.5-172637.29" + assign $0\cr_a_ok$next[0:0]$9828 $2\cr_a_ok$next[0:0]$9831 + attribute \src "libresoc.v:173405.5-173405.29" switch \initial - attribute \src "libresoc.v:172637.9-172637.17" + attribute \src "libresoc.v:173405.9-173405.17" case 1'1 case end @@ -353845,41 +320388,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9898 $1\cr_a$next[3:0]$9897 } { \cr_a_ok$98 \cr_a$97 } + assign { $1\cr_a_ok$next[0:0]$9830 $1\cr_a$next[3:0]$9829 } { \cr_a_ok$98 \cr_a$97 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9898 $1\cr_a$next[3:0]$9897 } { \cr_a_ok$98 \cr_a$97 } + assign { $1\cr_a_ok$next[0:0]$9830 $1\cr_a$next[3:0]$9829 } { \cr_a_ok$98 \cr_a$97 } case - assign $1\cr_a$next[3:0]$9897 \cr_a - assign $1\cr_a_ok$next[0:0]$9898 \cr_a_ok + assign $1\cr_a$next[3:0]$9829 \cr_a + assign $1\cr_a_ok$next[0:0]$9830 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9899 1'0 + assign $2\cr_a_ok$next[0:0]$9831 1'0 case - assign $2\cr_a_ok$next[0:0]$9899 $1\cr_a_ok$next[0:0]$9898 + assign $2\cr_a_ok$next[0:0]$9831 $1\cr_a_ok$next[0:0]$9830 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9895 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9896 + update \cr_a$next $0\cr_a$next[3:0]$9827 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9828 end - attribute \src "libresoc.v:172655.3-172673.6" - process $proc$libresoc.v:172655$9900 + attribute \src "libresoc.v:173423.3-173441.6" + process $proc$libresoc.v:173423$9832 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$9901 $1\xer_ov$next[1:0]$9903 + assign $0\xer_ov$next[1:0]$9833 $1\xer_ov$next[1:0]$9835 assign { } { } - assign $0\xer_ov_ok$next[0:0]$9902 $2\xer_ov_ok$next[0:0]$9905 - attribute \src "libresoc.v:172656.5-172656.29" + assign $0\xer_ov_ok$next[0:0]$9834 $2\xer_ov_ok$next[0:0]$9837 + attribute \src "libresoc.v:173424.5-173424.29" switch \initial - attribute \src "libresoc.v:172656.9-172656.17" + attribute \src "libresoc.v:173424.9-173424.17" case 1'1 case end @@ -353889,41 +320432,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9904 $1\xer_ov$next[1:0]$9903 } { \xer_ov_ok$100 \xer_ov$99 } + assign { $1\xer_ov_ok$next[0:0]$9836 $1\xer_ov$next[1:0]$9835 } { \xer_ov_ok$100 \xer_ov$99 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9904 $1\xer_ov$next[1:0]$9903 } { \xer_ov_ok$100 \xer_ov$99 } + assign { $1\xer_ov_ok$next[0:0]$9836 $1\xer_ov$next[1:0]$9835 } { \xer_ov_ok$100 \xer_ov$99 } case - assign $1\xer_ov$next[1:0]$9903 \xer_ov - assign $1\xer_ov_ok$next[0:0]$9904 \xer_ov_ok + assign $1\xer_ov$next[1:0]$9835 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9836 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$9905 1'0 + assign $2\xer_ov_ok$next[0:0]$9837 1'0 case - assign $2\xer_ov_ok$next[0:0]$9905 $1\xer_ov_ok$next[0:0]$9904 + assign $2\xer_ov_ok$next[0:0]$9837 $1\xer_ov_ok$next[0:0]$9836 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$9901 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9902 + update \xer_ov$next $0\xer_ov$next[1:0]$9833 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9834 end - attribute \src "libresoc.v:172674.3-172692.6" - process $proc$libresoc.v:172674$9906 + attribute \src "libresoc.v:173442.3-173460.6" + process $proc$libresoc.v:173442$9838 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$20$next[0:0]$9908 $1\xer_so$20$next[0:0]$9910 - assign $0\xer_so_ok$next[0:0]$9907 $2\xer_so_ok$next[0:0]$9911 - attribute \src "libresoc.v:172675.5-172675.29" + assign $0\xer_so$20$next[0:0]$9840 $1\xer_so$20$next[0:0]$9842 + assign $0\xer_so_ok$next[0:0]$9839 $2\xer_so_ok$next[0:0]$9843 + attribute \src "libresoc.v:173443.5-173443.29" switch \initial - attribute \src "libresoc.v:172675.9-172675.17" + attribute \src "libresoc.v:173443.9-173443.17" case 1'1 case end @@ -353933,38 +320476,38 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9909 $1\xer_so$20$next[0:0]$9910 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\xer_so_ok$next[0:0]$9841 $1\xer_so$20$next[0:0]$9842 } { \xer_so_ok$102 \xer_so$101 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9909 $1\xer_so$20$next[0:0]$9910 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\xer_so_ok$next[0:0]$9841 $1\xer_so$20$next[0:0]$9842 } { \xer_so_ok$102 \xer_so$101 } case - assign $1\xer_so_ok$next[0:0]$9909 \xer_so_ok - assign $1\xer_so$20$next[0:0]$9910 \xer_so$20 + assign $1\xer_so_ok$next[0:0]$9841 \xer_so_ok + assign $1\xer_so$20$next[0:0]$9842 \xer_so$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9911 1'0 + assign $2\xer_so_ok$next[0:0]$9843 1'0 case - assign $2\xer_so_ok$next[0:0]$9911 $1\xer_so_ok$next[0:0]$9909 + assign $2\xer_so_ok$next[0:0]$9843 $1\xer_so_ok$next[0:0]$9841 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9907 - update \xer_so$20$next $0\xer_so$20$next[0:0]$9908 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9839 + update \xer_so$20$next $0\xer_so$20$next[0:0]$9840 end - attribute \src "libresoc.v:172693.3-172710.6" - process $proc$libresoc.v:172693$9912 + attribute \src "libresoc.v:173461.3-173478.6" + process $proc$libresoc.v:173461$9844 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9913 $2\r_busy$next[0:0]$9915 - attribute \src "libresoc.v:172694.5-172694.29" + assign $0\r_busy$next[0:0]$9845 $2\r_busy$next[0:0]$9847 + attribute \src "libresoc.v:173462.5-173462.29" switch \initial - attribute \src "libresoc.v:172694.9-172694.17" + attribute \src "libresoc.v:173462.9-173462.17" case 1'1 case end @@ -353973,34 +320516,34 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9914 1'1 + assign $1\r_busy$next[0:0]$9846 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9914 1'0 + assign $1\r_busy$next[0:0]$9846 1'0 case - assign $1\r_busy$next[0:0]$9914 \r_busy + assign $1\r_busy$next[0:0]$9846 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9915 1'0 + assign $2\r_busy$next[0:0]$9847 1'0 case - assign $2\r_busy$next[0:0]$9915 $1\r_busy$next[0:0]$9914 + assign $2\r_busy$next[0:0]$9847 $1\r_busy$next[0:0]$9846 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9913 + update \r_busy$next $0\r_busy$next[0:0]$9845 end - attribute \src "libresoc.v:172711.3-172723.6" - process $proc$libresoc.v:172711$9916 + attribute \src "libresoc.v:173479.3-173491.6" + process $proc$libresoc.v:173479$9848 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9917 $1\muxid$1$next[1:0]$9918 - attribute \src "libresoc.v:172712.5-172712.29" + assign $0\muxid$1$next[1:0]$9849 $1\muxid$1$next[1:0]$9850 + attribute \src "libresoc.v:173480.5-173480.29" switch \initial - attribute \src "libresoc.v:172712.9-172712.17" + attribute \src "libresoc.v:173480.9-173480.17" case 1'1 case end @@ -354009,19 +320552,19 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9918 \muxid$76 + assign $1\muxid$1$next[1:0]$9850 \muxid$76 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9918 \muxid$76 + assign $1\muxid$1$next[1:0]$9850 \muxid$76 case - assign $1\muxid$1$next[1:0]$9918 \muxid$1 + assign $1\muxid$1$next[1:0]$9850 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9917 + update \muxid$1$next $0\muxid$1$next[1:0]$9849 end - attribute \src "libresoc.v:172724.3-172765.6" - process $proc$libresoc.v:172724$9919 + attribute \src "libresoc.v:173492.3-173533.6" + process $proc$libresoc.v:173492$9851 assign { } { } assign { } { } assign { } { } @@ -354058,33 +320601,33 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$9920 $1\logical_op__data_len$18$next[3:0]$9938 - assign $0\logical_op__fn_unit$3$next[13:0]$9921 $1\logical_op__fn_unit$3$next[13:0]$9939 + assign $0\logical_op__data_len$18$next[3:0]$9852 $1\logical_op__data_len$18$next[3:0]$9870 + assign $0\logical_op__fn_unit$3$next[13:0]$9853 $1\logical_op__fn_unit$3$next[13:0]$9871 assign { } { } assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$9924 $1\logical_op__input_carry$12$next[1:0]$9942 - assign $0\logical_op__insn$19$next[31:0]$9925 $1\logical_op__insn$19$next[31:0]$9943 - assign $0\logical_op__insn_type$2$next[6:0]$9926 $1\logical_op__insn_type$2$next[6:0]$9944 - assign $0\logical_op__invert_in$10$next[0:0]$9927 $1\logical_op__invert_in$10$next[0:0]$9945 - assign $0\logical_op__invert_out$13$next[0:0]$9928 $1\logical_op__invert_out$13$next[0:0]$9946 - assign $0\logical_op__is_32bit$16$next[0:0]$9929 $1\logical_op__is_32bit$16$next[0:0]$9947 - assign $0\logical_op__is_signed$17$next[0:0]$9930 $1\logical_op__is_signed$17$next[0:0]$9948 + assign $0\logical_op__input_carry$12$next[1:0]$9856 $1\logical_op__input_carry$12$next[1:0]$9874 + assign $0\logical_op__insn$19$next[31:0]$9857 $1\logical_op__insn$19$next[31:0]$9875 + assign $0\logical_op__insn_type$2$next[6:0]$9858 $1\logical_op__insn_type$2$next[6:0]$9876 + assign $0\logical_op__invert_in$10$next[0:0]$9859 $1\logical_op__invert_in$10$next[0:0]$9877 + assign $0\logical_op__invert_out$13$next[0:0]$9860 $1\logical_op__invert_out$13$next[0:0]$9878 + assign $0\logical_op__is_32bit$16$next[0:0]$9861 $1\logical_op__is_32bit$16$next[0:0]$9879 + assign $0\logical_op__is_signed$17$next[0:0]$9862 $1\logical_op__is_signed$17$next[0:0]$9880 assign { } { } assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$9933 $1\logical_op__output_carry$15$next[0:0]$9951 + assign $0\logical_op__output_carry$15$next[0:0]$9865 $1\logical_op__output_carry$15$next[0:0]$9883 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$9936 $1\logical_op__write_cr0$14$next[0:0]$9954 - assign $0\logical_op__zero_a$11$next[0:0]$9937 $1\logical_op__zero_a$11$next[0:0]$9955 - assign $0\logical_op__imm_data__data$4$next[63:0]$9922 $2\logical_op__imm_data__data$4$next[63:0]$9956 - assign $0\logical_op__imm_data__ok$5$next[0:0]$9923 $2\logical_op__imm_data__ok$5$next[0:0]$9957 - assign $0\logical_op__oe__oe$8$next[0:0]$9931 $2\logical_op__oe__oe$8$next[0:0]$9958 - assign $0\logical_op__oe__ok$9$next[0:0]$9932 $2\logical_op__oe__ok$9$next[0:0]$9959 - assign $0\logical_op__rc__ok$7$next[0:0]$9934 $2\logical_op__rc__ok$7$next[0:0]$9960 - assign $0\logical_op__rc__rc$6$next[0:0]$9935 $2\logical_op__rc__rc$6$next[0:0]$9961 - attribute \src "libresoc.v:172725.5-172725.29" + assign $0\logical_op__write_cr0$14$next[0:0]$9868 $1\logical_op__write_cr0$14$next[0:0]$9886 + assign $0\logical_op__zero_a$11$next[0:0]$9869 $1\logical_op__zero_a$11$next[0:0]$9887 + assign $0\logical_op__imm_data__data$4$next[63:0]$9854 $2\logical_op__imm_data__data$4$next[63:0]$9888 + assign $0\logical_op__imm_data__ok$5$next[0:0]$9855 $2\logical_op__imm_data__ok$5$next[0:0]$9889 + assign $0\logical_op__oe__oe$8$next[0:0]$9863 $2\logical_op__oe__oe$8$next[0:0]$9890 + assign $0\logical_op__oe__ok$9$next[0:0]$9864 $2\logical_op__oe__ok$9$next[0:0]$9891 + assign $0\logical_op__rc__ok$7$next[0:0]$9866 $2\logical_op__rc__ok$7$next[0:0]$9892 + assign $0\logical_op__rc__rc$6$next[0:0]$9867 $2\logical_op__rc__rc$6$next[0:0]$9893 + attribute \src "libresoc.v:173493.5-173493.29" switch \initial - attribute \src "libresoc.v:172725.9-172725.17" + attribute \src "libresoc.v:173493.9-173493.17" case 1'1 case end @@ -354110,7 +320653,7 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9943 $1\logical_op__data_len$18$next[3:0]$9938 $1\logical_op__is_signed$17$next[0:0]$9948 $1\logical_op__is_32bit$16$next[0:0]$9947 $1\logical_op__output_carry$15$next[0:0]$9951 $1\logical_op__write_cr0$14$next[0:0]$9954 $1\logical_op__invert_out$13$next[0:0]$9946 $1\logical_op__input_carry$12$next[1:0]$9942 $1\logical_op__zero_a$11$next[0:0]$9955 $1\logical_op__invert_in$10$next[0:0]$9945 $1\logical_op__oe__ok$9$next[0:0]$9950 $1\logical_op__oe__oe$8$next[0:0]$9949 $1\logical_op__rc__ok$7$next[0:0]$9952 $1\logical_op__rc__rc$6$next[0:0]$9953 $1\logical_op__imm_data__ok$5$next[0:0]$9941 $1\logical_op__imm_data__data$4$next[63:0]$9940 $1\logical_op__fn_unit$3$next[13:0]$9939 $1\logical_op__insn_type$2$next[6:0]$9944 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\logical_op__insn$19$next[31:0]$9875 $1\logical_op__data_len$18$next[3:0]$9870 $1\logical_op__is_signed$17$next[0:0]$9880 $1\logical_op__is_32bit$16$next[0:0]$9879 $1\logical_op__output_carry$15$next[0:0]$9883 $1\logical_op__write_cr0$14$next[0:0]$9886 $1\logical_op__invert_out$13$next[0:0]$9878 $1\logical_op__input_carry$12$next[1:0]$9874 $1\logical_op__zero_a$11$next[0:0]$9887 $1\logical_op__invert_in$10$next[0:0]$9877 $1\logical_op__oe__ok$9$next[0:0]$9882 $1\logical_op__oe__oe$8$next[0:0]$9881 $1\logical_op__rc__ok$7$next[0:0]$9884 $1\logical_op__rc__rc$6$next[0:0]$9885 $1\logical_op__imm_data__ok$5$next[0:0]$9873 $1\logical_op__imm_data__data$4$next[63:0]$9872 $1\logical_op__fn_unit$3$next[13:0]$9871 $1\logical_op__insn_type$2$next[6:0]$9876 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -354131,26 +320674,26 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9943 $1\logical_op__data_len$18$next[3:0]$9938 $1\logical_op__is_signed$17$next[0:0]$9948 $1\logical_op__is_32bit$16$next[0:0]$9947 $1\logical_op__output_carry$15$next[0:0]$9951 $1\logical_op__write_cr0$14$next[0:0]$9954 $1\logical_op__invert_out$13$next[0:0]$9946 $1\logical_op__input_carry$12$next[1:0]$9942 $1\logical_op__zero_a$11$next[0:0]$9955 $1\logical_op__invert_in$10$next[0:0]$9945 $1\logical_op__oe__ok$9$next[0:0]$9950 $1\logical_op__oe__oe$8$next[0:0]$9949 $1\logical_op__rc__ok$7$next[0:0]$9952 $1\logical_op__rc__rc$6$next[0:0]$9953 $1\logical_op__imm_data__ok$5$next[0:0]$9941 $1\logical_op__imm_data__data$4$next[63:0]$9940 $1\logical_op__fn_unit$3$next[13:0]$9939 $1\logical_op__insn_type$2$next[6:0]$9944 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\logical_op__insn$19$next[31:0]$9875 $1\logical_op__data_len$18$next[3:0]$9870 $1\logical_op__is_signed$17$next[0:0]$9880 $1\logical_op__is_32bit$16$next[0:0]$9879 $1\logical_op__output_carry$15$next[0:0]$9883 $1\logical_op__write_cr0$14$next[0:0]$9886 $1\logical_op__invert_out$13$next[0:0]$9878 $1\logical_op__input_carry$12$next[1:0]$9874 $1\logical_op__zero_a$11$next[0:0]$9887 $1\logical_op__invert_in$10$next[0:0]$9877 $1\logical_op__oe__ok$9$next[0:0]$9882 $1\logical_op__oe__oe$8$next[0:0]$9881 $1\logical_op__rc__ok$7$next[0:0]$9884 $1\logical_op__rc__rc$6$next[0:0]$9885 $1\logical_op__imm_data__ok$5$next[0:0]$9873 $1\logical_op__imm_data__data$4$next[63:0]$9872 $1\logical_op__fn_unit$3$next[13:0]$9871 $1\logical_op__insn_type$2$next[6:0]$9876 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } case - assign $1\logical_op__data_len$18$next[3:0]$9938 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[13:0]$9939 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$9940 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$9941 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$9942 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$9943 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$9944 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$9945 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$9946 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$9947 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$9948 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$9949 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$9950 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$9951 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$9952 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$9953 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$9954 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$9955 \logical_op__zero_a$11 + assign $1\logical_op__data_len$18$next[3:0]$9870 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[13:0]$9871 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$9872 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$9873 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$9874 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$9875 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$9876 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$9877 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$9878 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$9879 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$9880 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$9881 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$9882 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$9883 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$9884 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$9885 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$9886 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$9887 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -354162,41 +320705,41 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$9956 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9957 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$9961 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$9960 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$9958 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$9959 1'0 + assign $2\logical_op__imm_data__data$4$next[63:0]$9888 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9889 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$9893 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$9892 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$9890 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$9891 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$9956 $1\logical_op__imm_data__data$4$next[63:0]$9940 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9957 $1\logical_op__imm_data__ok$5$next[0:0]$9941 - assign $2\logical_op__oe__oe$8$next[0:0]$9958 $1\logical_op__oe__oe$8$next[0:0]$9949 - assign $2\logical_op__oe__ok$9$next[0:0]$9959 $1\logical_op__oe__ok$9$next[0:0]$9950 - assign $2\logical_op__rc__ok$7$next[0:0]$9960 $1\logical_op__rc__ok$7$next[0:0]$9952 - assign $2\logical_op__rc__rc$6$next[0:0]$9961 $1\logical_op__rc__rc$6$next[0:0]$9953 + assign $2\logical_op__imm_data__data$4$next[63:0]$9888 $1\logical_op__imm_data__data$4$next[63:0]$9872 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9889 $1\logical_op__imm_data__ok$5$next[0:0]$9873 + assign $2\logical_op__oe__oe$8$next[0:0]$9890 $1\logical_op__oe__oe$8$next[0:0]$9881 + assign $2\logical_op__oe__ok$9$next[0:0]$9891 $1\logical_op__oe__ok$9$next[0:0]$9882 + assign $2\logical_op__rc__ok$7$next[0:0]$9892 $1\logical_op__rc__ok$7$next[0:0]$9884 + assign $2\logical_op__rc__rc$6$next[0:0]$9893 $1\logical_op__rc__rc$6$next[0:0]$9885 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9920 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$9921 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9922 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9923 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9924 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9925 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9926 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9927 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9928 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9929 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9930 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9931 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9932 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9933 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9934 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9935 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9936 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9937 + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9852 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$9853 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9854 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9855 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9856 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9857 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9858 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9859 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9860 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9861 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9862 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9863 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9864 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9865 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9866 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9867 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9868 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9869 end - connect \$74 $and$libresoc.v:172446$9839_Y + connect \$74 $and$libresoc.v:173214$9771_Y connect \cr_a$68 4'0000 connect \cr_a_ok$69 1'0 connect \xer_so_ok$72 1'0 @@ -354230,381 +320773,381 @@ module \pipe_end connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_stage_muxid \muxid end -attribute \src "libresoc.v:172802.1-173789.10" +attribute \src "libresoc.v:173570.1-174557.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" attribute \generator "nMigen" module \pipe_middle_0 - attribute \src "libresoc.v:173714.3-173728.6" - wire $0\div_by_zero$54$next[0:0]$10190 - attribute \src "libresoc.v:173388.3-173389.47" - wire $0\div_by_zero$54[0:0]$10025 - attribute \src "libresoc.v:172825.7-172825.30" - wire $0\div_by_zero$54[0:0]$10207 - attribute \src "libresoc.v:173510.3-173521.6" + attribute \src "libresoc.v:174482.3-174496.6" + wire $0\div_by_zero$54$next[0:0]$10122 + attribute \src "libresoc.v:173593.7-173593.30" + wire $0\div_by_zero$54[0:0]$10139 + attribute \src "libresoc.v:174156.3-174157.47" + wire $0\div_by_zero$54[0:0]$9957 + attribute \src "libresoc.v:174278.3-174289.6" wire width 64 $0\div_state_next_divisor[63:0] - attribute \src "libresoc.v:173498.3-173509.6" + attribute \src "libresoc.v:174266.3-174277.6" wire width 128 $0\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:173486.3-173497.6" + attribute \src "libresoc.v:174254.3-174265.6" wire width 7 $0\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:173684.3-173698.6" - wire $0\dive_abs_ov32$52$next[0:0]$10182 - attribute \src "libresoc.v:173392.3-173393.51" - wire $0\dive_abs_ov32$52[0:0]$10029 - attribute \src "libresoc.v:172849.7-172849.32" - wire $0\dive_abs_ov32$52[0:0]$10209 - attribute \src "libresoc.v:173699.3-173713.6" - wire $0\dive_abs_ov64$53$next[0:0]$10186 - attribute \src "libresoc.v:173390.3-173391.51" - wire $0\dive_abs_ov64$53[0:0]$10027 - attribute \src "libresoc.v:172857.7-172857.32" - wire $0\dive_abs_ov64$53[0:0]$10211 - attribute \src "libresoc.v:173729.3-173743.6" - wire width 128 $0\dividend$68$next[127:0]$10194 - attribute \src "libresoc.v:173386.3-173387.41" - wire width 128 $0\dividend$68[127:0]$10023 - attribute \src "libresoc.v:172863.15-172863.68" - wire width 128 $0\dividend$68[127:0]$10213 - attribute \src "libresoc.v:173669.3-173683.6" - wire $0\dividend_neg$51$next[0:0]$10178 - attribute \src "libresoc.v:173394.3-173395.49" - wire $0\dividend_neg$51[0:0]$10031 - attribute \src "libresoc.v:172871.7-172871.31" - wire $0\dividend_neg$51[0:0]$10215 - attribute \src "libresoc.v:173654.3-173668.6" - wire $0\divisor_neg$50$next[0:0]$10174 - attribute \src "libresoc.v:173396.3-173397.47" - wire $0\divisor_neg$50[0:0]$10033 - attribute \src "libresoc.v:172879.7-172879.30" - wire $0\divisor_neg$50[0:0]$10217 - attribute \src "libresoc.v:173744.3-173758.6" - wire width 64 $0\divisor_radicand$65$next[63:0]$10198 - attribute \src "libresoc.v:173384.3-173385.57" - wire width 64 $0\divisor_radicand$65[63:0]$10021 - attribute \src "libresoc.v:172885.14-172885.58" - wire width 64 $0\divisor_radicand$65[63:0]$10219 - attribute \src "libresoc.v:173522.3-173549.6" - wire $0\empty$next[0:0]$10091 - attribute \src "libresoc.v:173442.3-173443.27" + attribute \src "libresoc.v:174452.3-174466.6" + wire $0\dive_abs_ov32$52$next[0:0]$10114 + attribute \src "libresoc.v:173617.7-173617.32" + wire $0\dive_abs_ov32$52[0:0]$10141 + attribute \src "libresoc.v:174160.3-174161.51" + wire $0\dive_abs_ov32$52[0:0]$9961 + attribute \src "libresoc.v:174467.3-174481.6" + wire $0\dive_abs_ov64$53$next[0:0]$10118 + attribute \src "libresoc.v:173625.7-173625.32" + wire $0\dive_abs_ov64$53[0:0]$10143 + attribute \src "libresoc.v:174158.3-174159.51" + wire $0\dive_abs_ov64$53[0:0]$9959 + attribute \src "libresoc.v:174497.3-174511.6" + wire width 128 $0\dividend$68$next[127:0]$10126 + attribute \src "libresoc.v:173631.15-173631.68" + wire width 128 $0\dividend$68[127:0]$10145 + attribute \src "libresoc.v:174154.3-174155.41" + wire width 128 $0\dividend$68[127:0]$9955 + attribute \src "libresoc.v:174437.3-174451.6" + wire $0\dividend_neg$51$next[0:0]$10110 + attribute \src "libresoc.v:173639.7-173639.31" + wire $0\dividend_neg$51[0:0]$10147 + attribute \src "libresoc.v:174162.3-174163.49" + wire $0\dividend_neg$51[0:0]$9963 + attribute \src "libresoc.v:174422.3-174436.6" + wire $0\divisor_neg$50$next[0:0]$10106 + attribute \src "libresoc.v:173647.7-173647.30" + wire $0\divisor_neg$50[0:0]$10149 + attribute \src "libresoc.v:174164.3-174165.47" + wire $0\divisor_neg$50[0:0]$9965 + attribute \src "libresoc.v:174512.3-174526.6" + wire width 64 $0\divisor_radicand$65$next[63:0]$10130 + attribute \src "libresoc.v:173653.14-173653.58" + wire width 64 $0\divisor_radicand$65[63:0]$10151 + attribute \src "libresoc.v:174152.3-174153.57" + wire width 64 $0\divisor_radicand$65[63:0]$9953 + attribute \src "libresoc.v:174290.3-174317.6" + wire $0\empty$next[0:0]$10023 + attribute \src "libresoc.v:174210.3-174211.27" wire $0\empty[0:0] - attribute \src "libresoc.v:172803.7-172803.20" + attribute \src "libresoc.v:173571.7-173571.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173565.3-173608.6" - wire width 4 $0\logical_op__data_len$45$next[3:0]$10101 - attribute \src "libresoc.v:173436.3-173437.65" - wire width 4 $0\logical_op__data_len$45[3:0]$10073 - attribute \src "libresoc.v:172897.13-172897.45" - wire width 4 $0\logical_op__data_len$45[3:0]$10222 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10102 - attribute \src "libresoc.v:173406.3-173407.63" - wire width 14 $0\logical_op__fn_unit$30[13:0]$10043 - attribute \src "libresoc.v:172950.14-172950.49" - wire width 14 $0\logical_op__fn_unit$30[13:0]$10224 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10103 - attribute \src "libresoc.v:173408.3-173409.77" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$10045 - attribute \src "libresoc.v:172956.14-172956.68" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$10226 - attribute \src "libresoc.v:173565.3-173608.6" - wire $0\logical_op__imm_data__ok$32$next[0:0]$10104 - attribute \src "libresoc.v:173410.3-173411.73" - wire $0\logical_op__imm_data__ok$32[0:0]$10047 - attribute \src "libresoc.v:172964.7-172964.43" - wire $0\logical_op__imm_data__ok$32[0:0]$10228 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 2 $0\logical_op__input_carry$39$next[1:0]$10105 - attribute \src "libresoc.v:173424.3-173425.71" - wire width 2 $0\logical_op__input_carry$39[1:0]$10061 - attribute \src "libresoc.v:172986.13-172986.48" - wire width 2 $0\logical_op__input_carry$39[1:0]$10230 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 32 $0\logical_op__insn$46$next[31:0]$10106 - attribute \src "libresoc.v:173438.3-173439.57" - wire width 32 $0\logical_op__insn$46[31:0]$10075 - attribute \src "libresoc.v:172994.14-172994.43" - wire width 32 $0\logical_op__insn$46[31:0]$10232 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 7 $0\logical_op__insn_type$29$next[6:0]$10107 - attribute \src "libresoc.v:173404.3-173405.67" - wire width 7 $0\logical_op__insn_type$29[6:0]$10041 - attribute \src "libresoc.v:173227.13-173227.47" - wire width 7 $0\logical_op__insn_type$29[6:0]$10234 - attribute \src "libresoc.v:173565.3-173608.6" - wire $0\logical_op__invert_in$37$next[0:0]$10108 - attribute \src "libresoc.v:173420.3-173421.67" - wire $0\logical_op__invert_in$37[0:0]$10057 - attribute \src "libresoc.v:173235.7-173235.40" - wire $0\logical_op__invert_in$37[0:0]$10236 - attribute \src "libresoc.v:173565.3-173608.6" - wire $0\logical_op__invert_out$40$next[0:0]$10109 - attribute \src "libresoc.v:173426.3-173427.69" - wire $0\logical_op__invert_out$40[0:0]$10063 - attribute \src "libresoc.v:173243.7-173243.41" - wire $0\logical_op__invert_out$40[0:0]$10238 - attribute \src "libresoc.v:173565.3-173608.6" - wire $0\logical_op__is_32bit$43$next[0:0]$10110 - attribute \src "libresoc.v:173432.3-173433.65" - wire $0\logical_op__is_32bit$43[0:0]$10069 - attribute \src "libresoc.v:173251.7-173251.39" - wire $0\logical_op__is_32bit$43[0:0]$10240 - attribute \src "libresoc.v:173565.3-173608.6" - wire $0\logical_op__is_signed$44$next[0:0]$10111 - attribute \src "libresoc.v:173434.3-173435.67" - wire $0\logical_op__is_signed$44[0:0]$10071 - attribute \src "libresoc.v:173259.7-173259.40" - wire $0\logical_op__is_signed$44[0:0]$10242 - attribute \src "libresoc.v:173565.3-173608.6" - wire $0\logical_op__oe__oe$35$next[0:0]$10112 - attribute \src "libresoc.v:173416.3-173417.61" - wire $0\logical_op__oe__oe$35[0:0]$10053 - attribute \src "libresoc.v:173265.7-173265.37" - wire $0\logical_op__oe__oe$35[0:0]$10244 - attribute \src "libresoc.v:173565.3-173608.6" - wire $0\logical_op__oe__ok$36$next[0:0]$10113 - attribute \src "libresoc.v:173418.3-173419.61" - wire $0\logical_op__oe__ok$36[0:0]$10055 - attribute \src "libresoc.v:173273.7-173273.37" - wire $0\logical_op__oe__ok$36[0:0]$10246 - attribute \src "libresoc.v:173565.3-173608.6" - wire $0\logical_op__output_carry$42$next[0:0]$10114 - attribute \src "libresoc.v:173430.3-173431.73" - wire $0\logical_op__output_carry$42[0:0]$10067 - attribute \src "libresoc.v:173283.7-173283.43" - wire $0\logical_op__output_carry$42[0:0]$10248 - attribute \src "libresoc.v:173565.3-173608.6" - wire $0\logical_op__rc__ok$34$next[0:0]$10115 - attribute \src "libresoc.v:173414.3-173415.61" - wire $0\logical_op__rc__ok$34[0:0]$10051 - attribute \src "libresoc.v:173289.7-173289.37" - wire $0\logical_op__rc__ok$34[0:0]$10250 - attribute \src "libresoc.v:173565.3-173608.6" - wire $0\logical_op__rc__rc$33$next[0:0]$10116 - attribute \src "libresoc.v:173412.3-173413.61" - wire $0\logical_op__rc__rc$33[0:0]$10049 - attribute \src "libresoc.v:173297.7-173297.37" - wire $0\logical_op__rc__rc$33[0:0]$10252 - attribute \src "libresoc.v:173565.3-173608.6" - wire $0\logical_op__write_cr0$41$next[0:0]$10117 - attribute \src "libresoc.v:173428.3-173429.67" - wire $0\logical_op__write_cr0$41[0:0]$10065 - attribute \src "libresoc.v:173307.7-173307.40" - wire $0\logical_op__write_cr0$41[0:0]$10254 - attribute \src "libresoc.v:173565.3-173608.6" - wire $0\logical_op__zero_a$38$next[0:0]$10118 - attribute \src "libresoc.v:173422.3-173423.61" - wire $0\logical_op__zero_a$38[0:0]$10059 - attribute \src "libresoc.v:173315.7-173315.37" - wire $0\logical_op__zero_a$38[0:0]$10256 - attribute \src "libresoc.v:173550.3-173564.6" - wire width 2 $0\muxid$28$next[1:0]$10097 - attribute \src "libresoc.v:173440.3-173441.35" - wire width 2 $0\muxid$28[1:0]$10077 - attribute \src "libresoc.v:173323.13-173323.30" - wire width 2 $0\muxid$28[1:0]$10258 - attribute \src "libresoc.v:173759.3-173773.6" - wire width 2 $0\operation$69$next[1:0]$10202 - attribute \src "libresoc.v:173382.3-173383.43" - wire width 2 $0\operation$69[1:0]$10019 - attribute \src "libresoc.v:173333.13-173333.34" - wire width 2 $0\operation$69[1:0]$10260 - attribute \src "libresoc.v:173609.3-173623.6" - wire width 64 $0\ra$47$next[63:0]$10162 - attribute \src "libresoc.v:173402.3-173403.29" - wire width 64 $0\ra$47[63:0]$10039 - attribute \src "libresoc.v:173347.14-173347.44" - wire width 64 $0\ra$47[63:0]$10262 - attribute \src "libresoc.v:173624.3-173638.6" - wire width 64 $0\rb$48$next[63:0]$10166 - attribute \src "libresoc.v:173400.3-173401.29" - wire width 64 $0\rb$48[63:0]$10037 - attribute \src "libresoc.v:173355.14-173355.44" - wire width 64 $0\rb$48[63:0]$10264 - attribute \src "libresoc.v:173477.3-173485.6" - wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10085 - attribute \src "libresoc.v:173444.3-173445.75" + attribute \src "libresoc.v:174333.3-174376.6" + wire width 4 $0\logical_op__data_len$45$next[3:0]$10033 + attribute \src "libresoc.v:174204.3-174205.65" + wire width 4 $0\logical_op__data_len$45[3:0]$10005 + attribute \src "libresoc.v:173665.13-173665.45" + wire width 4 $0\logical_op__data_len$45[3:0]$10154 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10034 + attribute \src "libresoc.v:173718.14-173718.49" + wire width 14 $0\logical_op__fn_unit$30[13:0]$10156 + attribute \src "libresoc.v:174174.3-174175.63" + wire width 14 $0\logical_op__fn_unit$30[13:0]$9975 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10035 + attribute \src "libresoc.v:173724.14-173724.68" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10158 + attribute \src "libresoc.v:174176.3-174177.77" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$9977 + attribute \src "libresoc.v:174333.3-174376.6" + wire $0\logical_op__imm_data__ok$32$next[0:0]$10036 + attribute \src "libresoc.v:173732.7-173732.43" + wire $0\logical_op__imm_data__ok$32[0:0]$10160 + attribute \src "libresoc.v:174178.3-174179.73" + wire $0\logical_op__imm_data__ok$32[0:0]$9979 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 2 $0\logical_op__input_carry$39$next[1:0]$10037 + attribute \src "libresoc.v:173754.13-173754.48" + wire width 2 $0\logical_op__input_carry$39[1:0]$10162 + attribute \src "libresoc.v:174192.3-174193.71" + wire width 2 $0\logical_op__input_carry$39[1:0]$9993 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 32 $0\logical_op__insn$46$next[31:0]$10038 + attribute \src "libresoc.v:174206.3-174207.57" + wire width 32 $0\logical_op__insn$46[31:0]$10007 + attribute \src "libresoc.v:173762.14-173762.43" + wire width 32 $0\logical_op__insn$46[31:0]$10164 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 7 $0\logical_op__insn_type$29$next[6:0]$10039 + attribute \src "libresoc.v:173995.13-173995.47" + wire width 7 $0\logical_op__insn_type$29[6:0]$10166 + attribute \src "libresoc.v:174172.3-174173.67" + wire width 7 $0\logical_op__insn_type$29[6:0]$9973 + attribute \src "libresoc.v:174333.3-174376.6" + wire $0\logical_op__invert_in$37$next[0:0]$10040 + attribute \src "libresoc.v:174003.7-174003.40" + wire $0\logical_op__invert_in$37[0:0]$10168 + attribute \src "libresoc.v:174188.3-174189.67" + wire $0\logical_op__invert_in$37[0:0]$9989 + attribute \src "libresoc.v:174333.3-174376.6" + wire $0\logical_op__invert_out$40$next[0:0]$10041 + attribute \src "libresoc.v:174011.7-174011.41" + wire $0\logical_op__invert_out$40[0:0]$10170 + attribute \src "libresoc.v:174194.3-174195.69" + wire $0\logical_op__invert_out$40[0:0]$9995 + attribute \src "libresoc.v:174333.3-174376.6" + wire $0\logical_op__is_32bit$43$next[0:0]$10042 + attribute \src "libresoc.v:174200.3-174201.65" + wire $0\logical_op__is_32bit$43[0:0]$10001 + attribute \src "libresoc.v:174019.7-174019.39" + wire $0\logical_op__is_32bit$43[0:0]$10172 + attribute \src "libresoc.v:174333.3-174376.6" + wire $0\logical_op__is_signed$44$next[0:0]$10043 + attribute \src "libresoc.v:174202.3-174203.67" + wire $0\logical_op__is_signed$44[0:0]$10003 + attribute \src "libresoc.v:174027.7-174027.40" + wire $0\logical_op__is_signed$44[0:0]$10174 + attribute \src "libresoc.v:174333.3-174376.6" + wire $0\logical_op__oe__oe$35$next[0:0]$10044 + attribute \src "libresoc.v:174033.7-174033.37" + wire $0\logical_op__oe__oe$35[0:0]$10176 + attribute \src "libresoc.v:174184.3-174185.61" + wire $0\logical_op__oe__oe$35[0:0]$9985 + attribute \src "libresoc.v:174333.3-174376.6" + wire $0\logical_op__oe__ok$36$next[0:0]$10045 + attribute \src "libresoc.v:174041.7-174041.37" + wire $0\logical_op__oe__ok$36[0:0]$10178 + attribute \src "libresoc.v:174186.3-174187.61" + wire $0\logical_op__oe__ok$36[0:0]$9987 + attribute \src "libresoc.v:174333.3-174376.6" + wire $0\logical_op__output_carry$42$next[0:0]$10046 + attribute \src "libresoc.v:174051.7-174051.43" + wire $0\logical_op__output_carry$42[0:0]$10180 + attribute \src "libresoc.v:174198.3-174199.73" + wire $0\logical_op__output_carry$42[0:0]$9999 + attribute \src "libresoc.v:174333.3-174376.6" + wire $0\logical_op__rc__ok$34$next[0:0]$10047 + attribute \src "libresoc.v:174057.7-174057.37" + wire $0\logical_op__rc__ok$34[0:0]$10182 + attribute \src "libresoc.v:174182.3-174183.61" + wire $0\logical_op__rc__ok$34[0:0]$9983 + attribute \src "libresoc.v:174333.3-174376.6" + wire $0\logical_op__rc__rc$33$next[0:0]$10048 + attribute \src "libresoc.v:174065.7-174065.37" + wire $0\logical_op__rc__rc$33[0:0]$10184 + attribute \src "libresoc.v:174180.3-174181.61" + wire $0\logical_op__rc__rc$33[0:0]$9981 + attribute \src "libresoc.v:174333.3-174376.6" + wire $0\logical_op__write_cr0$41$next[0:0]$10049 + attribute \src "libresoc.v:174075.7-174075.40" + wire $0\logical_op__write_cr0$41[0:0]$10186 + attribute \src "libresoc.v:174196.3-174197.67" + wire $0\logical_op__write_cr0$41[0:0]$9997 + attribute \src "libresoc.v:174333.3-174376.6" + wire $0\logical_op__zero_a$38$next[0:0]$10050 + attribute \src "libresoc.v:174083.7-174083.37" + wire $0\logical_op__zero_a$38[0:0]$10188 + attribute \src "libresoc.v:174190.3-174191.61" + wire $0\logical_op__zero_a$38[0:0]$9991 + attribute \src "libresoc.v:174318.3-174332.6" + wire width 2 $0\muxid$28$next[1:0]$10029 + attribute \src "libresoc.v:174208.3-174209.35" + wire width 2 $0\muxid$28[1:0]$10009 + attribute \src "libresoc.v:174091.13-174091.30" + wire width 2 $0\muxid$28[1:0]$10190 + attribute \src "libresoc.v:174527.3-174541.6" + wire width 2 $0\operation$69$next[1:0]$10134 + attribute \src "libresoc.v:174101.13-174101.34" + wire width 2 $0\operation$69[1:0]$10192 + attribute \src "libresoc.v:174150.3-174151.43" + wire width 2 $0\operation$69[1:0]$9951 + attribute \src "libresoc.v:174377.3-174391.6" + wire width 64 $0\ra$47$next[63:0]$10094 + attribute \src "libresoc.v:174115.14-174115.44" + wire width 64 $0\ra$47[63:0]$10194 + attribute \src "libresoc.v:174170.3-174171.29" + wire width 64 $0\ra$47[63:0]$9971 + attribute \src "libresoc.v:174392.3-174406.6" + wire width 64 $0\rb$48$next[63:0]$10098 + attribute \src "libresoc.v:174123.14-174123.44" + wire width 64 $0\rb$48[63:0]$10196 + attribute \src "libresoc.v:174168.3-174169.29" + wire width 64 $0\rb$48[63:0]$9969 + attribute \src "libresoc.v:174245.3-174253.6" + wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10017 + attribute \src "libresoc.v:174212.3-174213.75" wire width 128 $0\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:173468.3-173476.6" - wire width 7 $0\saved_state_q_bits_known$next[6:0]$10082 - attribute \src "libresoc.v:173446.3-173447.65" + attribute \src "libresoc.v:174236.3-174244.6" + wire width 7 $0\saved_state_q_bits_known$next[6:0]$10014 + attribute \src "libresoc.v:174214.3-174215.65" wire width 7 $0\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:173639.3-173653.6" - wire $0\xer_so$49$next[0:0]$10170 - attribute \src "libresoc.v:173398.3-173399.37" - wire $0\xer_so$49[0:0]$10035 - attribute \src "libresoc.v:173373.7-173373.25" - wire $0\xer_so$49[0:0]$10268 - attribute \src "libresoc.v:173714.3-173728.6" - wire $1\div_by_zero$54$next[0:0]$10191 - attribute \src "libresoc.v:173510.3-173521.6" + attribute \src "libresoc.v:174407.3-174421.6" + wire $0\xer_so$49$next[0:0]$10102 + attribute \src "libresoc.v:174141.7-174141.25" + wire $0\xer_so$49[0:0]$10200 + attribute \src "libresoc.v:174166.3-174167.37" + wire $0\xer_so$49[0:0]$9967 + attribute \src "libresoc.v:174482.3-174496.6" + wire $1\div_by_zero$54$next[0:0]$10123 + attribute \src "libresoc.v:174278.3-174289.6" wire width 64 $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:173498.3-173509.6" + attribute \src "libresoc.v:174266.3-174277.6" wire width 128 $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:173486.3-173497.6" + attribute \src "libresoc.v:174254.3-174265.6" wire width 7 $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:173684.3-173698.6" - wire $1\dive_abs_ov32$52$next[0:0]$10183 - attribute \src "libresoc.v:173699.3-173713.6" - wire $1\dive_abs_ov64$53$next[0:0]$10187 - attribute \src "libresoc.v:173729.3-173743.6" - wire width 128 $1\dividend$68$next[127:0]$10195 - attribute \src "libresoc.v:173669.3-173683.6" - wire $1\dividend_neg$51$next[0:0]$10179 - attribute \src "libresoc.v:173654.3-173668.6" - wire $1\divisor_neg$50$next[0:0]$10175 - attribute \src "libresoc.v:173744.3-173758.6" - wire width 64 $1\divisor_radicand$65$next[63:0]$10199 - attribute \src "libresoc.v:173522.3-173549.6" - wire $1\empty$next[0:0]$10092 - attribute \src "libresoc.v:172889.7-172889.19" + attribute \src "libresoc.v:174452.3-174466.6" + wire $1\dive_abs_ov32$52$next[0:0]$10115 + attribute \src "libresoc.v:174467.3-174481.6" + wire $1\dive_abs_ov64$53$next[0:0]$10119 + attribute \src "libresoc.v:174497.3-174511.6" + wire width 128 $1\dividend$68$next[127:0]$10127 + attribute \src "libresoc.v:174437.3-174451.6" + wire $1\dividend_neg$51$next[0:0]$10111 + attribute \src "libresoc.v:174422.3-174436.6" + wire $1\divisor_neg$50$next[0:0]$10107 + attribute \src "libresoc.v:174512.3-174526.6" + wire width 64 $1\divisor_radicand$65$next[63:0]$10131 + attribute \src "libresoc.v:174290.3-174317.6" + wire $1\empty$next[0:0]$10024 + attribute \src "libresoc.v:173657.7-173657.19" wire $1\empty[0:0] - attribute \src "libresoc.v:173565.3-173608.6" - wire width 4 $1\logical_op__data_len$45$next[3:0]$10119 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10120 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10121 - attribute \src "libresoc.v:173565.3-173608.6" - wire $1\logical_op__imm_data__ok$32$next[0:0]$10122 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 2 $1\logical_op__input_carry$39$next[1:0]$10123 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 32 $1\logical_op__insn$46$next[31:0]$10124 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 7 $1\logical_op__insn_type$29$next[6:0]$10125 - attribute \src "libresoc.v:173565.3-173608.6" - wire $1\logical_op__invert_in$37$next[0:0]$10126 - attribute \src "libresoc.v:173565.3-173608.6" - wire $1\logical_op__invert_out$40$next[0:0]$10127 - attribute \src "libresoc.v:173565.3-173608.6" - wire $1\logical_op__is_32bit$43$next[0:0]$10128 - attribute \src "libresoc.v:173565.3-173608.6" - wire $1\logical_op__is_signed$44$next[0:0]$10129 - attribute \src "libresoc.v:173565.3-173608.6" - wire $1\logical_op__oe__oe$35$next[0:0]$10130 - attribute \src "libresoc.v:173565.3-173608.6" - wire $1\logical_op__oe__ok$36$next[0:0]$10131 - attribute \src "libresoc.v:173565.3-173608.6" - wire $1\logical_op__output_carry$42$next[0:0]$10132 - attribute \src "libresoc.v:173565.3-173608.6" - wire $1\logical_op__rc__ok$34$next[0:0]$10133 - attribute \src "libresoc.v:173565.3-173608.6" - wire $1\logical_op__rc__rc$33$next[0:0]$10134 - attribute \src "libresoc.v:173565.3-173608.6" - wire $1\logical_op__write_cr0$41$next[0:0]$10135 - attribute \src "libresoc.v:173565.3-173608.6" - wire $1\logical_op__zero_a$38$next[0:0]$10136 - attribute \src "libresoc.v:173550.3-173564.6" - wire width 2 $1\muxid$28$next[1:0]$10098 - attribute \src "libresoc.v:173759.3-173773.6" - wire width 2 $1\operation$69$next[1:0]$10203 - attribute \src "libresoc.v:173609.3-173623.6" - wire width 64 $1\ra$47$next[63:0]$10163 - attribute \src "libresoc.v:173624.3-173638.6" - wire width 64 $1\rb$48$next[63:0]$10167 - attribute \src "libresoc.v:173477.3-173485.6" - wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10086 - attribute \src "libresoc.v:173361.15-173361.84" + attribute \src "libresoc.v:174333.3-174376.6" + wire width 4 $1\logical_op__data_len$45$next[3:0]$10051 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10052 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10053 + attribute \src "libresoc.v:174333.3-174376.6" + wire $1\logical_op__imm_data__ok$32$next[0:0]$10054 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 2 $1\logical_op__input_carry$39$next[1:0]$10055 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 32 $1\logical_op__insn$46$next[31:0]$10056 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 7 $1\logical_op__insn_type$29$next[6:0]$10057 + attribute \src "libresoc.v:174333.3-174376.6" + wire $1\logical_op__invert_in$37$next[0:0]$10058 + attribute \src "libresoc.v:174333.3-174376.6" + wire $1\logical_op__invert_out$40$next[0:0]$10059 + attribute \src "libresoc.v:174333.3-174376.6" + wire $1\logical_op__is_32bit$43$next[0:0]$10060 + attribute \src "libresoc.v:174333.3-174376.6" + wire $1\logical_op__is_signed$44$next[0:0]$10061 + attribute \src "libresoc.v:174333.3-174376.6" + wire $1\logical_op__oe__oe$35$next[0:0]$10062 + attribute \src "libresoc.v:174333.3-174376.6" + wire $1\logical_op__oe__ok$36$next[0:0]$10063 + attribute \src "libresoc.v:174333.3-174376.6" + wire $1\logical_op__output_carry$42$next[0:0]$10064 + attribute \src "libresoc.v:174333.3-174376.6" + wire $1\logical_op__rc__ok$34$next[0:0]$10065 + attribute \src "libresoc.v:174333.3-174376.6" + wire $1\logical_op__rc__rc$33$next[0:0]$10066 + attribute \src "libresoc.v:174333.3-174376.6" + wire $1\logical_op__write_cr0$41$next[0:0]$10067 + attribute \src "libresoc.v:174333.3-174376.6" + wire $1\logical_op__zero_a$38$next[0:0]$10068 + attribute \src "libresoc.v:174318.3-174332.6" + wire width 2 $1\muxid$28$next[1:0]$10030 + attribute \src "libresoc.v:174527.3-174541.6" + wire width 2 $1\operation$69$next[1:0]$10135 + attribute \src "libresoc.v:174377.3-174391.6" + wire width 64 $1\ra$47$next[63:0]$10095 + attribute \src "libresoc.v:174392.3-174406.6" + wire width 64 $1\rb$48$next[63:0]$10099 + attribute \src "libresoc.v:174245.3-174253.6" + wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10018 + attribute \src "libresoc.v:174129.15-174129.84" wire width 128 $1\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:173468.3-173476.6" - wire width 7 $1\saved_state_q_bits_known$next[6:0]$10083 - attribute \src "libresoc.v:173365.13-173365.45" + attribute \src "libresoc.v:174236.3-174244.6" + wire width 7 $1\saved_state_q_bits_known$next[6:0]$10015 + attribute \src "libresoc.v:174133.13-174133.45" wire width 7 $1\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:173639.3-173653.6" - wire $1\xer_so$49$next[0:0]$10171 - attribute \src "libresoc.v:173714.3-173728.6" - wire $2\div_by_zero$54$next[0:0]$10192 - attribute \src "libresoc.v:173684.3-173698.6" - wire $2\dive_abs_ov32$52$next[0:0]$10184 - attribute \src "libresoc.v:173699.3-173713.6" - wire $2\dive_abs_ov64$53$next[0:0]$10188 - attribute \src "libresoc.v:173729.3-173743.6" - wire width 128 $2\dividend$68$next[127:0]$10196 - attribute \src "libresoc.v:173669.3-173683.6" - wire $2\dividend_neg$51$next[0:0]$10180 - attribute \src "libresoc.v:173654.3-173668.6" - wire $2\divisor_neg$50$next[0:0]$10176 - attribute \src "libresoc.v:173744.3-173758.6" - wire width 64 $2\divisor_radicand$65$next[63:0]$10200 - attribute \src "libresoc.v:173522.3-173549.6" - wire $2\empty$next[0:0]$10093 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 4 $2\logical_op__data_len$45$next[3:0]$10137 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10138 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10139 - attribute \src "libresoc.v:173565.3-173608.6" - wire $2\logical_op__imm_data__ok$32$next[0:0]$10140 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 2 $2\logical_op__input_carry$39$next[1:0]$10141 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 32 $2\logical_op__insn$46$next[31:0]$10142 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 7 $2\logical_op__insn_type$29$next[6:0]$10143 - attribute \src "libresoc.v:173565.3-173608.6" - wire $2\logical_op__invert_in$37$next[0:0]$10144 - attribute \src "libresoc.v:173565.3-173608.6" - wire $2\logical_op__invert_out$40$next[0:0]$10145 - attribute \src "libresoc.v:173565.3-173608.6" - wire $2\logical_op__is_32bit$43$next[0:0]$10146 - attribute \src "libresoc.v:173565.3-173608.6" - wire $2\logical_op__is_signed$44$next[0:0]$10147 - attribute \src "libresoc.v:173565.3-173608.6" - wire $2\logical_op__oe__oe$35$next[0:0]$10148 - attribute \src "libresoc.v:173565.3-173608.6" - wire $2\logical_op__oe__ok$36$next[0:0]$10149 - attribute \src "libresoc.v:173565.3-173608.6" - wire $2\logical_op__output_carry$42$next[0:0]$10150 - attribute \src "libresoc.v:173565.3-173608.6" - wire $2\logical_op__rc__ok$34$next[0:0]$10151 - attribute \src "libresoc.v:173565.3-173608.6" - wire $2\logical_op__rc__rc$33$next[0:0]$10152 - attribute \src "libresoc.v:173565.3-173608.6" - wire $2\logical_op__write_cr0$41$next[0:0]$10153 - attribute \src "libresoc.v:173565.3-173608.6" - wire $2\logical_op__zero_a$38$next[0:0]$10154 - attribute \src "libresoc.v:173550.3-173564.6" - wire width 2 $2\muxid$28$next[1:0]$10099 - attribute \src "libresoc.v:173759.3-173773.6" - wire width 2 $2\operation$69$next[1:0]$10204 - attribute \src "libresoc.v:173609.3-173623.6" - wire width 64 $2\ra$47$next[63:0]$10164 - attribute \src "libresoc.v:173624.3-173638.6" - wire width 64 $2\rb$48$next[63:0]$10168 - attribute \src "libresoc.v:173639.3-173653.6" - wire $2\xer_so$49$next[0:0]$10172 - attribute \src "libresoc.v:173522.3-173549.6" - wire $3\empty$next[0:0]$10094 - attribute \src "libresoc.v:173565.3-173608.6" - wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10155 - attribute \src "libresoc.v:173565.3-173608.6" - wire $3\logical_op__imm_data__ok$32$next[0:0]$10156 - attribute \src "libresoc.v:173565.3-173608.6" - wire $3\logical_op__oe__oe$35$next[0:0]$10157 - attribute \src "libresoc.v:173565.3-173608.6" - wire $3\logical_op__oe__ok$36$next[0:0]$10158 - attribute \src "libresoc.v:173565.3-173608.6" - wire $3\logical_op__rc__ok$34$next[0:0]$10159 - attribute \src "libresoc.v:173565.3-173608.6" - wire $3\logical_op__rc__rc$33$next[0:0]$10160 - attribute \src "libresoc.v:173522.3-173549.6" - wire $4\empty$next[0:0]$10095 - attribute \src "libresoc.v:173380.18-173380.98" - wire $and$libresoc.v:173380$10016_Y - attribute \src "libresoc.v:173381.18-173381.107" - wire $and$libresoc.v:173381$10017_Y - attribute \src "libresoc.v:173377.18-173377.92" - wire width 192 $extend$libresoc.v:173377$10012_Y - attribute \src "libresoc.v:173379.18-173379.119" - wire $ge$libresoc.v:173379$10015_Y - attribute \src "libresoc.v:173378.18-173378.93" - wire $not$libresoc.v:173378$10014_Y - attribute \src "libresoc.v:173377.18-173377.92" - wire width 192 $pos$libresoc.v:173377$10013_Y - attribute \src "libresoc.v:173376.18-173376.138" - wire width 191 $sshl$libresoc.v:173376$10011_Y + attribute \src "libresoc.v:174407.3-174421.6" + wire $1\xer_so$49$next[0:0]$10103 + attribute \src "libresoc.v:174482.3-174496.6" + wire $2\div_by_zero$54$next[0:0]$10124 + attribute \src "libresoc.v:174452.3-174466.6" + wire $2\dive_abs_ov32$52$next[0:0]$10116 + attribute \src "libresoc.v:174467.3-174481.6" + wire $2\dive_abs_ov64$53$next[0:0]$10120 + attribute \src "libresoc.v:174497.3-174511.6" + wire width 128 $2\dividend$68$next[127:0]$10128 + attribute \src "libresoc.v:174437.3-174451.6" + wire $2\dividend_neg$51$next[0:0]$10112 + attribute \src "libresoc.v:174422.3-174436.6" + wire $2\divisor_neg$50$next[0:0]$10108 + attribute \src "libresoc.v:174512.3-174526.6" + wire width 64 $2\divisor_radicand$65$next[63:0]$10132 + attribute \src "libresoc.v:174290.3-174317.6" + wire $2\empty$next[0:0]$10025 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 4 $2\logical_op__data_len$45$next[3:0]$10069 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10070 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10071 + attribute \src "libresoc.v:174333.3-174376.6" + wire $2\logical_op__imm_data__ok$32$next[0:0]$10072 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 2 $2\logical_op__input_carry$39$next[1:0]$10073 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 32 $2\logical_op__insn$46$next[31:0]$10074 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 7 $2\logical_op__insn_type$29$next[6:0]$10075 + attribute \src "libresoc.v:174333.3-174376.6" + wire $2\logical_op__invert_in$37$next[0:0]$10076 + attribute \src "libresoc.v:174333.3-174376.6" + wire $2\logical_op__invert_out$40$next[0:0]$10077 + attribute \src "libresoc.v:174333.3-174376.6" + wire $2\logical_op__is_32bit$43$next[0:0]$10078 + attribute \src "libresoc.v:174333.3-174376.6" + wire $2\logical_op__is_signed$44$next[0:0]$10079 + attribute \src "libresoc.v:174333.3-174376.6" + wire $2\logical_op__oe__oe$35$next[0:0]$10080 + attribute \src "libresoc.v:174333.3-174376.6" + wire $2\logical_op__oe__ok$36$next[0:0]$10081 + attribute \src "libresoc.v:174333.3-174376.6" + wire $2\logical_op__output_carry$42$next[0:0]$10082 + attribute \src "libresoc.v:174333.3-174376.6" + wire $2\logical_op__rc__ok$34$next[0:0]$10083 + attribute \src "libresoc.v:174333.3-174376.6" + wire $2\logical_op__rc__rc$33$next[0:0]$10084 + attribute \src "libresoc.v:174333.3-174376.6" + wire $2\logical_op__write_cr0$41$next[0:0]$10085 + attribute \src "libresoc.v:174333.3-174376.6" + wire $2\logical_op__zero_a$38$next[0:0]$10086 + attribute \src "libresoc.v:174318.3-174332.6" + wire width 2 $2\muxid$28$next[1:0]$10031 + attribute \src "libresoc.v:174527.3-174541.6" + wire width 2 $2\operation$69$next[1:0]$10136 + attribute \src "libresoc.v:174377.3-174391.6" + wire width 64 $2\ra$47$next[63:0]$10096 + attribute \src "libresoc.v:174392.3-174406.6" + wire width 64 $2\rb$48$next[63:0]$10100 + attribute \src "libresoc.v:174407.3-174421.6" + wire $2\xer_so$49$next[0:0]$10104 + attribute \src "libresoc.v:174290.3-174317.6" + wire $3\empty$next[0:0]$10026 + attribute \src "libresoc.v:174333.3-174376.6" + wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10087 + attribute \src "libresoc.v:174333.3-174376.6" + wire $3\logical_op__imm_data__ok$32$next[0:0]$10088 + attribute \src "libresoc.v:174333.3-174376.6" + wire $3\logical_op__oe__oe$35$next[0:0]$10089 + attribute \src "libresoc.v:174333.3-174376.6" + wire $3\logical_op__oe__ok$36$next[0:0]$10090 + attribute \src "libresoc.v:174333.3-174376.6" + wire $3\logical_op__rc__ok$34$next[0:0]$10091 + attribute \src "libresoc.v:174333.3-174376.6" + wire $3\logical_op__rc__rc$33$next[0:0]$10092 + attribute \src "libresoc.v:174290.3-174317.6" + wire $4\empty$next[0:0]$10027 + attribute \src "libresoc.v:174148.18-174148.98" + wire $and$libresoc.v:174148$9948_Y + attribute \src "libresoc.v:174149.18-174149.107" + wire $and$libresoc.v:174149$9949_Y + attribute \src "libresoc.v:174145.18-174145.92" + wire width 192 $extend$libresoc.v:174145$9944_Y + attribute \src "libresoc.v:174147.18-174147.119" + wire $ge$libresoc.v:174147$9947_Y + attribute \src "libresoc.v:174146.18-174146.93" + wire $not$libresoc.v:174146$9946_Y + attribute \src "libresoc.v:174145.18-174145.92" + wire width 192 $pos$libresoc.v:174145$9945_Y + attribute \src "libresoc.v:174144.18-174144.138" + wire width 191 $sshl$libresoc.v:174144$9943_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" wire width 192 \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" @@ -354617,9 +321160,9 @@ module \pipe_middle_0 wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 65 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire input 30 \div_by_zero @@ -354693,7 +321236,7 @@ module \pipe_middle_0 wire \empty attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" wire \empty$next - attribute \src "libresoc.v:172803.7-172803.15" + attribute \src "libresoc.v:173571.7-173571.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -355180,7 +321723,7 @@ module \pipe_middle_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$49$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $and $and$libresoc.v:173380$10016 + cell $and $and$libresoc.v:174148$9948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355188,10 +321731,10 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:173380$10016_Y + connect \Y $and$libresoc.v:174148$9948_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - cell $and $and$libresoc.v:173381$10017 + cell $and $and$libresoc.v:174149$9949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355199,18 +321742,18 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:173381$10017_Y + connect \Y $and$libresoc.v:174149$9949_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $extend$libresoc.v:173377$10012 + cell $pos $extend$libresoc.v:174145$9944 parameter \A_SIGNED 0 parameter \A_WIDTH 191 parameter \Y_WIDTH 192 connect \A \$56 - connect \Y $extend$libresoc.v:173377$10012_Y + connect \Y $extend$libresoc.v:174145$9944_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:173379$10015 + cell $ge $ge$libresoc.v:174147$9947 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -355218,26 +321761,26 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \saved_state_q_bits_known connect \B 6'111111 - connect \Y $ge$libresoc.v:173379$10015_Y + connect \Y $ge$libresoc.v:174147$9947_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $not $not$libresoc.v:173378$10014 + cell $not $not$libresoc.v:174146$9946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \empty - connect \Y $not$libresoc.v:173378$10014_Y + connect \Y $not$libresoc.v:174146$9946_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $pos$libresoc.v:173377$10013 + cell $pos $pos$libresoc.v:174145$9945 parameter \A_SIGNED 0 parameter \A_WIDTH 192 parameter \Y_WIDTH 192 - connect \A $extend$libresoc.v:173377$10012_Y - connect \Y $pos$libresoc.v:173377$10013_Y + connect \A $extend$libresoc.v:174145$9944_Y + connect \Y $pos$libresoc.v:174145$9945_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $sshl $sshl$libresoc.v:173376$10011 + cell $sshl $sshl$libresoc.v:174144$9943 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -355245,17 +321788,17 @@ module \pipe_middle_0 parameter \Y_WIDTH 191 connect \A \div_state_next_o_dividend_quotient [127:64] connect \B 7'1000000 - connect \Y $sshl$libresoc.v:173376$10011_Y + connect \Y $sshl$libresoc.v:174144$9943_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:173448.18-173452.4" + attribute \src "libresoc.v:174216.18-174220.4" cell \div_state_init \div_state_init connect \dividend \div_state_init_dividend connect \o_dividend_quotient \div_state_init_o_dividend_quotient connect \o_q_bits_known \div_state_init_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:173453.18-173459.4" + attribute \src "libresoc.v:174221.18-174227.4" cell \div_state_next \div_state_next connect \divisor \div_state_next_divisor connect \i_dividend_quotient \div_state_next_i_dividend_quotient @@ -355264,528 +321807,528 @@ module \pipe_middle_0 connect \o_q_bits_known \div_state_next_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:173460.10-173463.4" + attribute \src "libresoc.v:174228.10-174231.4" cell \n$80 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:173464.10-173467.4" + attribute \src "libresoc.v:174232.10-174235.4" cell \p$79 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:172803.7-172803.20" - process $proc$libresoc.v:172803$10205 + attribute \src "libresoc.v:173571.7-173571.20" + process $proc$libresoc.v:173571$10137 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172825.7-172825.30" - process $proc$libresoc.v:172825$10206 + attribute \src "libresoc.v:173593.7-173593.30" + process $proc$libresoc.v:173593$10138 assign { } { } - assign $0\div_by_zero$54[0:0]$10207 1'0 + assign $0\div_by_zero$54[0:0]$10139 1'0 sync always sync init - update \div_by_zero$54 $0\div_by_zero$54[0:0]$10207 + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10139 end - attribute \src "libresoc.v:172849.7-172849.32" - process $proc$libresoc.v:172849$10208 + attribute \src "libresoc.v:173617.7-173617.32" + process $proc$libresoc.v:173617$10140 assign { } { } - assign $0\dive_abs_ov32$52[0:0]$10209 1'0 + assign $0\dive_abs_ov32$52[0:0]$10141 1'0 sync always sync init - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10209 + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10141 end - attribute \src "libresoc.v:172857.7-172857.32" - process $proc$libresoc.v:172857$10210 + attribute \src "libresoc.v:173625.7-173625.32" + process $proc$libresoc.v:173625$10142 assign { } { } - assign $0\dive_abs_ov64$53[0:0]$10211 1'0 + assign $0\dive_abs_ov64$53[0:0]$10143 1'0 sync always sync init - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10211 + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10143 end - attribute \src "libresoc.v:172863.15-172863.68" - process $proc$libresoc.v:172863$10212 + attribute \src "libresoc.v:173631.15-173631.68" + process $proc$libresoc.v:173631$10144 assign { } { } - assign $0\dividend$68[127:0]$10213 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\dividend$68[127:0]$10145 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \dividend$68 $0\dividend$68[127:0]$10213 + update \dividend$68 $0\dividend$68[127:0]$10145 end - attribute \src "libresoc.v:172871.7-172871.31" - process $proc$libresoc.v:172871$10214 + attribute \src "libresoc.v:173639.7-173639.31" + process $proc$libresoc.v:173639$10146 assign { } { } - assign $0\dividend_neg$51[0:0]$10215 1'0 + assign $0\dividend_neg$51[0:0]$10147 1'0 sync always sync init - update \dividend_neg$51 $0\dividend_neg$51[0:0]$10215 + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10147 end - attribute \src "libresoc.v:172879.7-172879.30" - process $proc$libresoc.v:172879$10216 + attribute \src "libresoc.v:173647.7-173647.30" + process $proc$libresoc.v:173647$10148 assign { } { } - assign $0\divisor_neg$50[0:0]$10217 1'0 + assign $0\divisor_neg$50[0:0]$10149 1'0 sync always sync init - update \divisor_neg$50 $0\divisor_neg$50[0:0]$10217 + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10149 end - attribute \src "libresoc.v:172885.14-172885.58" - process $proc$libresoc.v:172885$10218 + attribute \src "libresoc.v:173653.14-173653.58" + process $proc$libresoc.v:173653$10150 assign { } { } - assign $0\divisor_radicand$65[63:0]$10219 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\divisor_radicand$65[63:0]$10151 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10219 + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10151 end - attribute \src "libresoc.v:172889.7-172889.19" - process $proc$libresoc.v:172889$10220 + attribute \src "libresoc.v:173657.7-173657.19" + process $proc$libresoc.v:173657$10152 assign { } { } assign $1\empty[0:0] 1'1 sync always sync init update \empty $1\empty[0:0] end - attribute \src "libresoc.v:172897.13-172897.45" - process $proc$libresoc.v:172897$10221 + attribute \src "libresoc.v:173665.13-173665.45" + process $proc$libresoc.v:173665$10153 assign { } { } - assign $0\logical_op__data_len$45[3:0]$10222 4'0000 + assign $0\logical_op__data_len$45[3:0]$10154 4'0000 sync always sync init - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10222 + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10154 end - attribute \src "libresoc.v:172950.14-172950.49" - process $proc$libresoc.v:172950$10223 + attribute \src "libresoc.v:173718.14-173718.49" + process $proc$libresoc.v:173718$10155 assign { } { } - assign $0\logical_op__fn_unit$30[13:0]$10224 14'00000000000000 + assign $0\logical_op__fn_unit$30[13:0]$10156 14'00000000000000 sync always sync init - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10224 + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10156 end - attribute \src "libresoc.v:172956.14-172956.68" - process $proc$libresoc.v:172956$10225 + attribute \src "libresoc.v:173724.14-173724.68" + process $proc$libresoc.v:173724$10157 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$10226 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$31[63:0]$10158 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10226 + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10158 end - attribute \src "libresoc.v:172964.7-172964.43" - process $proc$libresoc.v:172964$10227 + attribute \src "libresoc.v:173732.7-173732.43" + process $proc$libresoc.v:173732$10159 assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$10228 1'0 + assign $0\logical_op__imm_data__ok$32[0:0]$10160 1'0 sync always sync init - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10228 + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10160 end - attribute \src "libresoc.v:172986.13-172986.48" - process $proc$libresoc.v:172986$10229 + attribute \src "libresoc.v:173754.13-173754.48" + process $proc$libresoc.v:173754$10161 assign { } { } - assign $0\logical_op__input_carry$39[1:0]$10230 2'00 + assign $0\logical_op__input_carry$39[1:0]$10162 2'00 sync always sync init - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10230 + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10162 end - attribute \src "libresoc.v:172994.14-172994.43" - process $proc$libresoc.v:172994$10231 + attribute \src "libresoc.v:173762.14-173762.43" + process $proc$libresoc.v:173762$10163 assign { } { } - assign $0\logical_op__insn$46[31:0]$10232 0 + assign $0\logical_op__insn$46[31:0]$10164 0 sync always sync init - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10232 + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10164 end - attribute \src "libresoc.v:173227.13-173227.47" - process $proc$libresoc.v:173227$10233 + attribute \src "libresoc.v:173995.13-173995.47" + process $proc$libresoc.v:173995$10165 assign { } { } - assign $0\logical_op__insn_type$29[6:0]$10234 7'0000000 + assign $0\logical_op__insn_type$29[6:0]$10166 7'0000000 sync always sync init - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10234 + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10166 end - attribute \src "libresoc.v:173235.7-173235.40" - process $proc$libresoc.v:173235$10235 + attribute \src "libresoc.v:174003.7-174003.40" + process $proc$libresoc.v:174003$10167 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$10236 1'0 + assign $0\logical_op__invert_in$37[0:0]$10168 1'0 sync always sync init - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10236 + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10168 end - attribute \src "libresoc.v:173243.7-173243.41" - process $proc$libresoc.v:173243$10237 + attribute \src "libresoc.v:174011.7-174011.41" + process $proc$libresoc.v:174011$10169 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$10238 1'0 + assign $0\logical_op__invert_out$40[0:0]$10170 1'0 sync always sync init - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10238 + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10170 end - attribute \src "libresoc.v:173251.7-173251.39" - process $proc$libresoc.v:173251$10239 + attribute \src "libresoc.v:174019.7-174019.39" + process $proc$libresoc.v:174019$10171 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$10240 1'0 + assign $0\logical_op__is_32bit$43[0:0]$10172 1'0 sync always sync init - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10240 + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10172 end - attribute \src "libresoc.v:173259.7-173259.40" - process $proc$libresoc.v:173259$10241 + attribute \src "libresoc.v:174027.7-174027.40" + process $proc$libresoc.v:174027$10173 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$10242 1'0 + assign $0\logical_op__is_signed$44[0:0]$10174 1'0 sync always sync init - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10242 + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10174 end - attribute \src "libresoc.v:173265.7-173265.37" - process $proc$libresoc.v:173265$10243 + attribute \src "libresoc.v:174033.7-174033.37" + process $proc$libresoc.v:174033$10175 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$10244 1'0 + assign $0\logical_op__oe__oe$35[0:0]$10176 1'0 sync always sync init - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10244 + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10176 end - attribute \src "libresoc.v:173273.7-173273.37" - process $proc$libresoc.v:173273$10245 + attribute \src "libresoc.v:174041.7-174041.37" + process $proc$libresoc.v:174041$10177 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$10246 1'0 + assign $0\logical_op__oe__ok$36[0:0]$10178 1'0 sync always sync init - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10246 + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10178 end - attribute \src "libresoc.v:173283.7-173283.43" - process $proc$libresoc.v:173283$10247 + attribute \src "libresoc.v:174051.7-174051.43" + process $proc$libresoc.v:174051$10179 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$10248 1'0 + assign $0\logical_op__output_carry$42[0:0]$10180 1'0 sync always sync init - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10248 + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10180 end - attribute \src "libresoc.v:173289.7-173289.37" - process $proc$libresoc.v:173289$10249 + attribute \src "libresoc.v:174057.7-174057.37" + process $proc$libresoc.v:174057$10181 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$10250 1'0 + assign $0\logical_op__rc__ok$34[0:0]$10182 1'0 sync always sync init - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10250 + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10182 end - attribute \src "libresoc.v:173297.7-173297.37" - process $proc$libresoc.v:173297$10251 + attribute \src "libresoc.v:174065.7-174065.37" + process $proc$libresoc.v:174065$10183 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$10252 1'0 + assign $0\logical_op__rc__rc$33[0:0]$10184 1'0 sync always sync init - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10252 + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10184 end - attribute \src "libresoc.v:173307.7-173307.40" - process $proc$libresoc.v:173307$10253 + attribute \src "libresoc.v:174075.7-174075.40" + process $proc$libresoc.v:174075$10185 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$10254 1'0 + assign $0\logical_op__write_cr0$41[0:0]$10186 1'0 sync always sync init - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10254 + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10186 end - attribute \src "libresoc.v:173315.7-173315.37" - process $proc$libresoc.v:173315$10255 + attribute \src "libresoc.v:174083.7-174083.37" + process $proc$libresoc.v:174083$10187 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$10256 1'0 + assign $0\logical_op__zero_a$38[0:0]$10188 1'0 sync always sync init - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10256 + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10188 end - attribute \src "libresoc.v:173323.13-173323.30" - process $proc$libresoc.v:173323$10257 + attribute \src "libresoc.v:174091.13-174091.30" + process $proc$libresoc.v:174091$10189 assign { } { } - assign $0\muxid$28[1:0]$10258 2'00 + assign $0\muxid$28[1:0]$10190 2'00 sync always sync init - update \muxid$28 $0\muxid$28[1:0]$10258 + update \muxid$28 $0\muxid$28[1:0]$10190 end - attribute \src "libresoc.v:173333.13-173333.34" - process $proc$libresoc.v:173333$10259 + attribute \src "libresoc.v:174101.13-174101.34" + process $proc$libresoc.v:174101$10191 assign { } { } - assign $0\operation$69[1:0]$10260 2'00 + assign $0\operation$69[1:0]$10192 2'00 sync always sync init - update \operation$69 $0\operation$69[1:0]$10260 + update \operation$69 $0\operation$69[1:0]$10192 end - attribute \src "libresoc.v:173347.14-173347.44" - process $proc$libresoc.v:173347$10261 + attribute \src "libresoc.v:174115.14-174115.44" + process $proc$libresoc.v:174115$10193 assign { } { } - assign $0\ra$47[63:0]$10262 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\ra$47[63:0]$10194 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \ra$47 $0\ra$47[63:0]$10262 + update \ra$47 $0\ra$47[63:0]$10194 end - attribute \src "libresoc.v:173355.14-173355.44" - process $proc$libresoc.v:173355$10263 + attribute \src "libresoc.v:174123.14-174123.44" + process $proc$libresoc.v:174123$10195 assign { } { } - assign $0\rb$48[63:0]$10264 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\rb$48[63:0]$10196 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \rb$48 $0\rb$48[63:0]$10264 + update \rb$48 $0\rb$48[63:0]$10196 end - attribute \src "libresoc.v:173361.15-173361.84" - process $proc$libresoc.v:173361$10265 + attribute \src "libresoc.v:174129.15-174129.84" + process $proc$libresoc.v:174129$10197 assign { } { } assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:173365.13-173365.45" - process $proc$libresoc.v:173365$10266 + attribute \src "libresoc.v:174133.13-174133.45" + process $proc$libresoc.v:174133$10198 assign { } { } assign $1\saved_state_q_bits_known[6:0] 7'0000000 sync always sync init update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:173373.7-173373.25" - process $proc$libresoc.v:173373$10267 + attribute \src "libresoc.v:174141.7-174141.25" + process $proc$libresoc.v:174141$10199 assign { } { } - assign $0\xer_so$49[0:0]$10268 1'0 + assign $0\xer_so$49[0:0]$10200 1'0 sync always sync init - update \xer_so$49 $0\xer_so$49[0:0]$10268 + update \xer_so$49 $0\xer_so$49[0:0]$10200 end - attribute \src "libresoc.v:173382.3-173383.43" - process $proc$libresoc.v:173382$10018 + attribute \src "libresoc.v:174150.3-174151.43" + process $proc$libresoc.v:174150$9950 assign { } { } - assign $0\operation$69[1:0]$10019 \operation$69$next + assign $0\operation$69[1:0]$9951 \operation$69$next sync posedge \coresync_clk - update \operation$69 $0\operation$69[1:0]$10019 + update \operation$69 $0\operation$69[1:0]$9951 end - attribute \src "libresoc.v:173384.3-173385.57" - process $proc$libresoc.v:173384$10020 + attribute \src "libresoc.v:174152.3-174153.57" + process $proc$libresoc.v:174152$9952 assign { } { } - assign $0\divisor_radicand$65[63:0]$10021 \divisor_radicand$65$next + assign $0\divisor_radicand$65[63:0]$9953 \divisor_radicand$65$next sync posedge \coresync_clk - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10021 + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9953 end - attribute \src "libresoc.v:173386.3-173387.41" - process $proc$libresoc.v:173386$10022 + attribute \src "libresoc.v:174154.3-174155.41" + process $proc$libresoc.v:174154$9954 assign { } { } - assign $0\dividend$68[127:0]$10023 \dividend$68$next + assign $0\dividend$68[127:0]$9955 \dividend$68$next sync posedge \coresync_clk - update \dividend$68 $0\dividend$68[127:0]$10023 + update \dividend$68 $0\dividend$68[127:0]$9955 end - attribute \src "libresoc.v:173388.3-173389.47" - process $proc$libresoc.v:173388$10024 + attribute \src "libresoc.v:174156.3-174157.47" + process $proc$libresoc.v:174156$9956 assign { } { } - assign $0\div_by_zero$54[0:0]$10025 \div_by_zero$54$next + assign $0\div_by_zero$54[0:0]$9957 \div_by_zero$54$next sync posedge \coresync_clk - update \div_by_zero$54 $0\div_by_zero$54[0:0]$10025 + update \div_by_zero$54 $0\div_by_zero$54[0:0]$9957 end - attribute \src "libresoc.v:173390.3-173391.51" - process $proc$libresoc.v:173390$10026 + attribute \src "libresoc.v:174158.3-174159.51" + process $proc$libresoc.v:174158$9958 assign { } { } - assign $0\dive_abs_ov64$53[0:0]$10027 \dive_abs_ov64$53$next + assign $0\dive_abs_ov64$53[0:0]$9959 \dive_abs_ov64$53$next sync posedge \coresync_clk - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10027 + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9959 end - attribute \src "libresoc.v:173392.3-173393.51" - process $proc$libresoc.v:173392$10028 + attribute \src "libresoc.v:174160.3-174161.51" + process $proc$libresoc.v:174160$9960 assign { } { } - assign $0\dive_abs_ov32$52[0:0]$10029 \dive_abs_ov32$52$next + assign $0\dive_abs_ov32$52[0:0]$9961 \dive_abs_ov32$52$next sync posedge \coresync_clk - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10029 + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9961 end - attribute \src "libresoc.v:173394.3-173395.49" - process $proc$libresoc.v:173394$10030 + attribute \src "libresoc.v:174162.3-174163.49" + process $proc$libresoc.v:174162$9962 assign { } { } - assign $0\dividend_neg$51[0:0]$10031 \dividend_neg$51$next + assign $0\dividend_neg$51[0:0]$9963 \dividend_neg$51$next sync posedge \coresync_clk - update \dividend_neg$51 $0\dividend_neg$51[0:0]$10031 + update \dividend_neg$51 $0\dividend_neg$51[0:0]$9963 end - attribute \src "libresoc.v:173396.3-173397.47" - process $proc$libresoc.v:173396$10032 + attribute \src "libresoc.v:174164.3-174165.47" + process $proc$libresoc.v:174164$9964 assign { } { } - assign $0\divisor_neg$50[0:0]$10033 \divisor_neg$50$next + assign $0\divisor_neg$50[0:0]$9965 \divisor_neg$50$next sync posedge \coresync_clk - update \divisor_neg$50 $0\divisor_neg$50[0:0]$10033 + update \divisor_neg$50 $0\divisor_neg$50[0:0]$9965 end - attribute \src "libresoc.v:173398.3-173399.37" - process $proc$libresoc.v:173398$10034 + attribute \src "libresoc.v:174166.3-174167.37" + process $proc$libresoc.v:174166$9966 assign { } { } - assign $0\xer_so$49[0:0]$10035 \xer_so$49$next + assign $0\xer_so$49[0:0]$9967 \xer_so$49$next sync posedge \coresync_clk - update \xer_so$49 $0\xer_so$49[0:0]$10035 + update \xer_so$49 $0\xer_so$49[0:0]$9967 end - attribute \src "libresoc.v:173400.3-173401.29" - process $proc$libresoc.v:173400$10036 + attribute \src "libresoc.v:174168.3-174169.29" + process $proc$libresoc.v:174168$9968 assign { } { } - assign $0\rb$48[63:0]$10037 \rb$48$next + assign $0\rb$48[63:0]$9969 \rb$48$next sync posedge \coresync_clk - update \rb$48 $0\rb$48[63:0]$10037 + update \rb$48 $0\rb$48[63:0]$9969 end - attribute \src "libresoc.v:173402.3-173403.29" - process $proc$libresoc.v:173402$10038 + attribute \src "libresoc.v:174170.3-174171.29" + process $proc$libresoc.v:174170$9970 assign { } { } - assign $0\ra$47[63:0]$10039 \ra$47$next + assign $0\ra$47[63:0]$9971 \ra$47$next sync posedge \coresync_clk - update \ra$47 $0\ra$47[63:0]$10039 + update \ra$47 $0\ra$47[63:0]$9971 end - attribute \src "libresoc.v:173404.3-173405.67" - process $proc$libresoc.v:173404$10040 + attribute \src "libresoc.v:174172.3-174173.67" + process $proc$libresoc.v:174172$9972 assign { } { } - assign $0\logical_op__insn_type$29[6:0]$10041 \logical_op__insn_type$29$next + assign $0\logical_op__insn_type$29[6:0]$9973 \logical_op__insn_type$29$next sync posedge \coresync_clk - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10041 + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9973 end - attribute \src "libresoc.v:173406.3-173407.63" - process $proc$libresoc.v:173406$10042 + attribute \src "libresoc.v:174174.3-174175.63" + process $proc$libresoc.v:174174$9974 assign { } { } - assign $0\logical_op__fn_unit$30[13:0]$10043 \logical_op__fn_unit$30$next + assign $0\logical_op__fn_unit$30[13:0]$9975 \logical_op__fn_unit$30$next sync posedge \coresync_clk - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10043 + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$9975 end - attribute \src "libresoc.v:173408.3-173409.77" - process $proc$libresoc.v:173408$10044 + attribute \src "libresoc.v:174176.3-174177.77" + process $proc$libresoc.v:174176$9976 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$10045 \logical_op__imm_data__data$31$next + assign $0\logical_op__imm_data__data$31[63:0]$9977 \logical_op__imm_data__data$31$next sync posedge \coresync_clk - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10045 + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9977 end - attribute \src "libresoc.v:173410.3-173411.73" - process $proc$libresoc.v:173410$10046 + attribute \src "libresoc.v:174178.3-174179.73" + process $proc$libresoc.v:174178$9978 assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$10047 \logical_op__imm_data__ok$32$next + assign $0\logical_op__imm_data__ok$32[0:0]$9979 \logical_op__imm_data__ok$32$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10047 + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9979 end - attribute \src "libresoc.v:173412.3-173413.61" - process $proc$libresoc.v:173412$10048 + attribute \src "libresoc.v:174180.3-174181.61" + process $proc$libresoc.v:174180$9980 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$10049 \logical_op__rc__rc$33$next + assign $0\logical_op__rc__rc$33[0:0]$9981 \logical_op__rc__rc$33$next sync posedge \coresync_clk - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10049 + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9981 end - attribute \src "libresoc.v:173414.3-173415.61" - process $proc$libresoc.v:173414$10050 + attribute \src "libresoc.v:174182.3-174183.61" + process $proc$libresoc.v:174182$9982 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$10051 \logical_op__rc__ok$34$next + assign $0\logical_op__rc__ok$34[0:0]$9983 \logical_op__rc__ok$34$next sync posedge \coresync_clk - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10051 + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9983 end - attribute \src "libresoc.v:173416.3-173417.61" - process $proc$libresoc.v:173416$10052 + attribute \src "libresoc.v:174184.3-174185.61" + process $proc$libresoc.v:174184$9984 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$10053 \logical_op__oe__oe$35$next + assign $0\logical_op__oe__oe$35[0:0]$9985 \logical_op__oe__oe$35$next sync posedge \coresync_clk - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10053 + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9985 end - attribute \src "libresoc.v:173418.3-173419.61" - process $proc$libresoc.v:173418$10054 + attribute \src "libresoc.v:174186.3-174187.61" + process $proc$libresoc.v:174186$9986 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$10055 \logical_op__oe__ok$36$next + assign $0\logical_op__oe__ok$36[0:0]$9987 \logical_op__oe__ok$36$next sync posedge \coresync_clk - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10055 + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9987 end - attribute \src "libresoc.v:173420.3-173421.67" - process $proc$libresoc.v:173420$10056 + attribute \src "libresoc.v:174188.3-174189.67" + process $proc$libresoc.v:174188$9988 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$10057 \logical_op__invert_in$37$next + assign $0\logical_op__invert_in$37[0:0]$9989 \logical_op__invert_in$37$next sync posedge \coresync_clk - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10057 + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9989 end - attribute \src "libresoc.v:173422.3-173423.61" - process $proc$libresoc.v:173422$10058 + attribute \src "libresoc.v:174190.3-174191.61" + process $proc$libresoc.v:174190$9990 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$10059 \logical_op__zero_a$38$next + assign $0\logical_op__zero_a$38[0:0]$9991 \logical_op__zero_a$38$next sync posedge \coresync_clk - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10059 + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9991 end - attribute \src "libresoc.v:173424.3-173425.71" - process $proc$libresoc.v:173424$10060 + attribute \src "libresoc.v:174192.3-174193.71" + process $proc$libresoc.v:174192$9992 assign { } { } - assign $0\logical_op__input_carry$39[1:0]$10061 \logical_op__input_carry$39$next + assign $0\logical_op__input_carry$39[1:0]$9993 \logical_op__input_carry$39$next sync posedge \coresync_clk - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10061 + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9993 end - attribute \src "libresoc.v:173426.3-173427.69" - process $proc$libresoc.v:173426$10062 + attribute \src "libresoc.v:174194.3-174195.69" + process $proc$libresoc.v:174194$9994 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$10063 \logical_op__invert_out$40$next + assign $0\logical_op__invert_out$40[0:0]$9995 \logical_op__invert_out$40$next sync posedge \coresync_clk - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10063 + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9995 end - attribute \src "libresoc.v:173428.3-173429.67" - process $proc$libresoc.v:173428$10064 + attribute \src "libresoc.v:174196.3-174197.67" + process $proc$libresoc.v:174196$9996 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$10065 \logical_op__write_cr0$41$next + assign $0\logical_op__write_cr0$41[0:0]$9997 \logical_op__write_cr0$41$next sync posedge \coresync_clk - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10065 + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9997 end - attribute \src "libresoc.v:173430.3-173431.73" - process $proc$libresoc.v:173430$10066 + attribute \src "libresoc.v:174198.3-174199.73" + process $proc$libresoc.v:174198$9998 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$10067 \logical_op__output_carry$42$next + assign $0\logical_op__output_carry$42[0:0]$9999 \logical_op__output_carry$42$next sync posedge \coresync_clk - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10067 + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9999 end - attribute \src "libresoc.v:173432.3-173433.65" - process $proc$libresoc.v:173432$10068 + attribute \src "libresoc.v:174200.3-174201.65" + process $proc$libresoc.v:174200$10000 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$10069 \logical_op__is_32bit$43$next + assign $0\logical_op__is_32bit$43[0:0]$10001 \logical_op__is_32bit$43$next sync posedge \coresync_clk - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10069 + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10001 end - attribute \src "libresoc.v:173434.3-173435.67" - process $proc$libresoc.v:173434$10070 + attribute \src "libresoc.v:174202.3-174203.67" + process $proc$libresoc.v:174202$10002 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$10071 \logical_op__is_signed$44$next + assign $0\logical_op__is_signed$44[0:0]$10003 \logical_op__is_signed$44$next sync posedge \coresync_clk - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10071 + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10003 end - attribute \src "libresoc.v:173436.3-173437.65" - process $proc$libresoc.v:173436$10072 + attribute \src "libresoc.v:174204.3-174205.65" + process $proc$libresoc.v:174204$10004 assign { } { } - assign $0\logical_op__data_len$45[3:0]$10073 \logical_op__data_len$45$next + assign $0\logical_op__data_len$45[3:0]$10005 \logical_op__data_len$45$next sync posedge \coresync_clk - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10073 + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10005 end - attribute \src "libresoc.v:173438.3-173439.57" - process $proc$libresoc.v:173438$10074 + attribute \src "libresoc.v:174206.3-174207.57" + process $proc$libresoc.v:174206$10006 assign { } { } - assign $0\logical_op__insn$46[31:0]$10075 \logical_op__insn$46$next + assign $0\logical_op__insn$46[31:0]$10007 \logical_op__insn$46$next sync posedge \coresync_clk - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10075 + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10007 end - attribute \src "libresoc.v:173440.3-173441.35" - process $proc$libresoc.v:173440$10076 + attribute \src "libresoc.v:174208.3-174209.35" + process $proc$libresoc.v:174208$10008 assign { } { } - assign $0\muxid$28[1:0]$10077 \muxid$28$next + assign $0\muxid$28[1:0]$10009 \muxid$28$next sync posedge \coresync_clk - update \muxid$28 $0\muxid$28[1:0]$10077 + update \muxid$28 $0\muxid$28[1:0]$10009 end - attribute \src "libresoc.v:173442.3-173443.27" - process $proc$libresoc.v:173442$10078 + attribute \src "libresoc.v:174210.3-174211.27" + process $proc$libresoc.v:174210$10010 assign { } { } assign $0\empty[0:0] \empty$next sync posedge \coresync_clk update \empty $0\empty[0:0] end - attribute \src "libresoc.v:173444.3-173445.75" - process $proc$libresoc.v:173444$10079 + attribute \src "libresoc.v:174212.3-174213.75" + process $proc$libresoc.v:174212$10011 assign { } { } assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next sync posedge \coresync_clk update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:173446.3-173447.65" - process $proc$libresoc.v:173446$10080 + attribute \src "libresoc.v:174214.3-174215.65" + process $proc$libresoc.v:174214$10012 assign { } { } assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next sync posedge \coresync_clk update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:173468.3-173476.6" - process $proc$libresoc.v:173468$10081 + attribute \src "libresoc.v:174236.3-174244.6" + process $proc$libresoc.v:174236$10013 assign { } { } assign { } { } - assign $0\saved_state_q_bits_known$next[6:0]$10082 $1\saved_state_q_bits_known$next[6:0]$10083 - attribute \src "libresoc.v:173469.5-173469.29" + assign $0\saved_state_q_bits_known$next[6:0]$10014 $1\saved_state_q_bits_known$next[6:0]$10015 + attribute \src "libresoc.v:174237.5-174237.29" switch \initial - attribute \src "libresoc.v:173469.9-173469.17" + attribute \src "libresoc.v:174237.9-174237.17" case 1'1 case end @@ -355794,21 +322337,21 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\saved_state_q_bits_known$next[6:0]$10083 7'0000000 + assign $1\saved_state_q_bits_known$next[6:0]$10015 7'0000000 case - assign $1\saved_state_q_bits_known$next[6:0]$10083 \div_state_next_o_q_bits_known + assign $1\saved_state_q_bits_known$next[6:0]$10015 \div_state_next_o_q_bits_known end sync always - update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10082 + update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10014 end - attribute \src "libresoc.v:173477.3-173485.6" - process $proc$libresoc.v:173477$10084 + attribute \src "libresoc.v:174245.3-174253.6" + process $proc$libresoc.v:174245$10016 assign { } { } assign { } { } - assign $0\saved_state_dividend_quotient$next[127:0]$10085 $1\saved_state_dividend_quotient$next[127:0]$10086 - attribute \src "libresoc.v:173478.5-173478.29" + assign $0\saved_state_dividend_quotient$next[127:0]$10017 $1\saved_state_dividend_quotient$next[127:0]$10018 + attribute \src "libresoc.v:174246.5-174246.29" switch \initial - attribute \src "libresoc.v:173478.9-173478.17" + attribute \src "libresoc.v:174246.9-174246.17" case 1'1 case end @@ -355817,20 +322360,20 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\saved_state_dividend_quotient$next[127:0]$10086 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\saved_state_dividend_quotient$next[127:0]$10018 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $1\saved_state_dividend_quotient$next[127:0]$10086 \div_state_next_o_dividend_quotient + assign $1\saved_state_dividend_quotient$next[127:0]$10018 \div_state_next_o_dividend_quotient end sync always - update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10085 + update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10017 end - attribute \src "libresoc.v:173486.3-173497.6" - process $proc$libresoc.v:173486$10087 + attribute \src "libresoc.v:174254.3-174265.6" + process $proc$libresoc.v:174254$10019 assign { } { } assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:173487.5-173487.29" + attribute \src "libresoc.v:174255.5-174255.29" switch \initial - attribute \src "libresoc.v:173487.9-173487.17" + attribute \src "libresoc.v:174255.9-174255.17" case 1'1 case end @@ -355848,13 +322391,13 @@ module \pipe_middle_0 sync always update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] end - attribute \src "libresoc.v:173498.3-173509.6" - process $proc$libresoc.v:173498$10088 + attribute \src "libresoc.v:174266.3-174277.6" + process $proc$libresoc.v:174266$10020 assign { } { } assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:173499.5-173499.29" + attribute \src "libresoc.v:174267.5-174267.29" switch \initial - attribute \src "libresoc.v:173499.9-173499.17" + attribute \src "libresoc.v:174267.9-174267.17" case 1'1 case end @@ -355872,13 +322415,13 @@ module \pipe_middle_0 sync always update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] end - attribute \src "libresoc.v:173510.3-173521.6" - process $proc$libresoc.v:173510$10089 + attribute \src "libresoc.v:174278.3-174289.6" + process $proc$libresoc.v:174278$10021 assign { } { } assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:173511.5-173511.29" + attribute \src "libresoc.v:174279.5-174279.29" switch \initial - attribute \src "libresoc.v:173511.9-173511.17" + attribute \src "libresoc.v:174279.9-174279.17" case 1'1 case end @@ -355896,15 +322439,15 @@ module \pipe_middle_0 sync always update \div_state_next_divisor $0\div_state_next_divisor[63:0] end - attribute \src "libresoc.v:173522.3-173549.6" - process $proc$libresoc.v:173522$10090 + attribute \src "libresoc.v:174290.3-174317.6" + process $proc$libresoc.v:174290$10022 assign { } { } assign { } { } assign { } { } - assign $0\empty$next[0:0]$10091 $4\empty$next[0:0]$10095 - attribute \src "libresoc.v:173523.5-173523.29" + assign $0\empty$next[0:0]$10023 $4\empty$next[0:0]$10027 + attribute \src "libresoc.v:174291.5-174291.29" switch \initial - attribute \src "libresoc.v:173523.9-173523.17" + attribute \src "libresoc.v:174291.9-174291.17" case 1'1 case end @@ -355913,28 +322456,28 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\empty$next[0:0]$10092 $2\empty$next[0:0]$10093 + assign $1\empty$next[0:0]$10024 $2\empty$next[0:0]$10025 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\empty$next[0:0]$10093 1'0 + assign $2\empty$next[0:0]$10025 1'0 case - assign $2\empty$next[0:0]$10093 \empty + assign $2\empty$next[0:0]$10025 \empty end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\empty$next[0:0]$10092 $3\empty$next[0:0]$10094 + assign $1\empty$next[0:0]$10024 $3\empty$next[0:0]$10026 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch \$66 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\empty$next[0:0]$10094 1'1 + assign $3\empty$next[0:0]$10026 1'1 case - assign $3\empty$next[0:0]$10094 \empty + assign $3\empty$next[0:0]$10026 \empty end end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" @@ -355942,21 +322485,21 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\empty$next[0:0]$10095 1'1 + assign $4\empty$next[0:0]$10027 1'1 case - assign $4\empty$next[0:0]$10095 $1\empty$next[0:0]$10092 + assign $4\empty$next[0:0]$10027 $1\empty$next[0:0]$10024 end sync always - update \empty$next $0\empty$next[0:0]$10091 + update \empty$next $0\empty$next[0:0]$10023 end - attribute \src "libresoc.v:173550.3-173564.6" - process $proc$libresoc.v:173550$10096 + attribute \src "libresoc.v:174318.3-174332.6" + process $proc$libresoc.v:174318$10028 assign { } { } assign { } { } - assign $0\muxid$28$next[1:0]$10097 $1\muxid$28$next[1:0]$10098 - attribute \src "libresoc.v:173551.5-173551.29" + assign $0\muxid$28$next[1:0]$10029 $1\muxid$28$next[1:0]$10030 + attribute \src "libresoc.v:174319.5-174319.29" switch \initial - attribute \src "libresoc.v:173551.9-173551.17" + attribute \src "libresoc.v:174319.9-174319.17" case 1'1 case end @@ -355965,24 +322508,24 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\muxid$28$next[1:0]$10098 $2\muxid$28$next[1:0]$10099 + assign $1\muxid$28$next[1:0]$10030 $2\muxid$28$next[1:0]$10031 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\muxid$28$next[1:0]$10099 \muxid + assign $2\muxid$28$next[1:0]$10031 \muxid case - assign $2\muxid$28$next[1:0]$10099 \muxid$28 + assign $2\muxid$28$next[1:0]$10031 \muxid$28 end case - assign $1\muxid$28$next[1:0]$10098 \muxid$28 + assign $1\muxid$28$next[1:0]$10030 \muxid$28 end sync always - update \muxid$28$next $0\muxid$28$next[1:0]$10097 + update \muxid$28$next $0\muxid$28$next[1:0]$10029 end - attribute \src "libresoc.v:173565.3-173608.6" - process $proc$libresoc.v:173565$10100 + attribute \src "libresoc.v:174333.3-174376.6" + process $proc$libresoc.v:174333$10032 assign { } { } assign { } { } assign { } { } @@ -356019,33 +322562,33 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$45$next[3:0]$10101 $1\logical_op__data_len$45$next[3:0]$10119 - assign $0\logical_op__fn_unit$30$next[13:0]$10102 $1\logical_op__fn_unit$30$next[13:0]$10120 + assign $0\logical_op__data_len$45$next[3:0]$10033 $1\logical_op__data_len$45$next[3:0]$10051 + assign $0\logical_op__fn_unit$30$next[13:0]$10034 $1\logical_op__fn_unit$30$next[13:0]$10052 assign { } { } assign { } { } - assign $0\logical_op__input_carry$39$next[1:0]$10105 $1\logical_op__input_carry$39$next[1:0]$10123 - assign $0\logical_op__insn$46$next[31:0]$10106 $1\logical_op__insn$46$next[31:0]$10124 - assign $0\logical_op__insn_type$29$next[6:0]$10107 $1\logical_op__insn_type$29$next[6:0]$10125 - assign $0\logical_op__invert_in$37$next[0:0]$10108 $1\logical_op__invert_in$37$next[0:0]$10126 - assign $0\logical_op__invert_out$40$next[0:0]$10109 $1\logical_op__invert_out$40$next[0:0]$10127 - assign $0\logical_op__is_32bit$43$next[0:0]$10110 $1\logical_op__is_32bit$43$next[0:0]$10128 - assign $0\logical_op__is_signed$44$next[0:0]$10111 $1\logical_op__is_signed$44$next[0:0]$10129 + assign $0\logical_op__input_carry$39$next[1:0]$10037 $1\logical_op__input_carry$39$next[1:0]$10055 + assign $0\logical_op__insn$46$next[31:0]$10038 $1\logical_op__insn$46$next[31:0]$10056 + assign $0\logical_op__insn_type$29$next[6:0]$10039 $1\logical_op__insn_type$29$next[6:0]$10057 + assign $0\logical_op__invert_in$37$next[0:0]$10040 $1\logical_op__invert_in$37$next[0:0]$10058 + assign $0\logical_op__invert_out$40$next[0:0]$10041 $1\logical_op__invert_out$40$next[0:0]$10059 + assign $0\logical_op__is_32bit$43$next[0:0]$10042 $1\logical_op__is_32bit$43$next[0:0]$10060 + assign $0\logical_op__is_signed$44$next[0:0]$10043 $1\logical_op__is_signed$44$next[0:0]$10061 assign { } { } assign { } { } - assign $0\logical_op__output_carry$42$next[0:0]$10114 $1\logical_op__output_carry$42$next[0:0]$10132 + assign $0\logical_op__output_carry$42$next[0:0]$10046 $1\logical_op__output_carry$42$next[0:0]$10064 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$41$next[0:0]$10117 $1\logical_op__write_cr0$41$next[0:0]$10135 - assign $0\logical_op__zero_a$38$next[0:0]$10118 $1\logical_op__zero_a$38$next[0:0]$10136 - assign $0\logical_op__imm_data__data$31$next[63:0]$10103 $3\logical_op__imm_data__data$31$next[63:0]$10155 - assign $0\logical_op__imm_data__ok$32$next[0:0]$10104 $3\logical_op__imm_data__ok$32$next[0:0]$10156 - assign $0\logical_op__oe__oe$35$next[0:0]$10112 $3\logical_op__oe__oe$35$next[0:0]$10157 - assign $0\logical_op__oe__ok$36$next[0:0]$10113 $3\logical_op__oe__ok$36$next[0:0]$10158 - assign $0\logical_op__rc__ok$34$next[0:0]$10115 $3\logical_op__rc__ok$34$next[0:0]$10159 - assign $0\logical_op__rc__rc$33$next[0:0]$10116 $3\logical_op__rc__rc$33$next[0:0]$10160 - attribute \src "libresoc.v:173566.5-173566.29" + assign $0\logical_op__write_cr0$41$next[0:0]$10049 $1\logical_op__write_cr0$41$next[0:0]$10067 + assign $0\logical_op__zero_a$38$next[0:0]$10050 $1\logical_op__zero_a$38$next[0:0]$10068 + assign $0\logical_op__imm_data__data$31$next[63:0]$10035 $3\logical_op__imm_data__data$31$next[63:0]$10087 + assign $0\logical_op__imm_data__ok$32$next[0:0]$10036 $3\logical_op__imm_data__ok$32$next[0:0]$10088 + assign $0\logical_op__oe__oe$35$next[0:0]$10044 $3\logical_op__oe__oe$35$next[0:0]$10089 + assign $0\logical_op__oe__ok$36$next[0:0]$10045 $3\logical_op__oe__ok$36$next[0:0]$10090 + assign $0\logical_op__rc__ok$34$next[0:0]$10047 $3\logical_op__rc__ok$34$next[0:0]$10091 + assign $0\logical_op__rc__rc$33$next[0:0]$10048 $3\logical_op__rc__rc$33$next[0:0]$10092 + attribute \src "libresoc.v:174334.5-174334.29" switch \initial - attribute \src "libresoc.v:173566.9-173566.17" + attribute \src "libresoc.v:174334.9-174334.17" case 1'1 case end @@ -356071,24 +322614,24 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $1\logical_op__data_len$45$next[3:0]$10119 $2\logical_op__data_len$45$next[3:0]$10137 - assign $1\logical_op__fn_unit$30$next[13:0]$10120 $2\logical_op__fn_unit$30$next[13:0]$10138 - assign $1\logical_op__imm_data__data$31$next[63:0]$10121 $2\logical_op__imm_data__data$31$next[63:0]$10139 - assign $1\logical_op__imm_data__ok$32$next[0:0]$10122 $2\logical_op__imm_data__ok$32$next[0:0]$10140 - assign $1\logical_op__input_carry$39$next[1:0]$10123 $2\logical_op__input_carry$39$next[1:0]$10141 - assign $1\logical_op__insn$46$next[31:0]$10124 $2\logical_op__insn$46$next[31:0]$10142 - assign $1\logical_op__insn_type$29$next[6:0]$10125 $2\logical_op__insn_type$29$next[6:0]$10143 - assign $1\logical_op__invert_in$37$next[0:0]$10126 $2\logical_op__invert_in$37$next[0:0]$10144 - assign $1\logical_op__invert_out$40$next[0:0]$10127 $2\logical_op__invert_out$40$next[0:0]$10145 - assign $1\logical_op__is_32bit$43$next[0:0]$10128 $2\logical_op__is_32bit$43$next[0:0]$10146 - assign $1\logical_op__is_signed$44$next[0:0]$10129 $2\logical_op__is_signed$44$next[0:0]$10147 - assign $1\logical_op__oe__oe$35$next[0:0]$10130 $2\logical_op__oe__oe$35$next[0:0]$10148 - assign $1\logical_op__oe__ok$36$next[0:0]$10131 $2\logical_op__oe__ok$36$next[0:0]$10149 - assign $1\logical_op__output_carry$42$next[0:0]$10132 $2\logical_op__output_carry$42$next[0:0]$10150 - assign $1\logical_op__rc__ok$34$next[0:0]$10133 $2\logical_op__rc__ok$34$next[0:0]$10151 - assign $1\logical_op__rc__rc$33$next[0:0]$10134 $2\logical_op__rc__rc$33$next[0:0]$10152 - assign $1\logical_op__write_cr0$41$next[0:0]$10135 $2\logical_op__write_cr0$41$next[0:0]$10153 - assign $1\logical_op__zero_a$38$next[0:0]$10136 $2\logical_op__zero_a$38$next[0:0]$10154 + assign $1\logical_op__data_len$45$next[3:0]$10051 $2\logical_op__data_len$45$next[3:0]$10069 + assign $1\logical_op__fn_unit$30$next[13:0]$10052 $2\logical_op__fn_unit$30$next[13:0]$10070 + assign $1\logical_op__imm_data__data$31$next[63:0]$10053 $2\logical_op__imm_data__data$31$next[63:0]$10071 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10054 $2\logical_op__imm_data__ok$32$next[0:0]$10072 + assign $1\logical_op__input_carry$39$next[1:0]$10055 $2\logical_op__input_carry$39$next[1:0]$10073 + assign $1\logical_op__insn$46$next[31:0]$10056 $2\logical_op__insn$46$next[31:0]$10074 + assign $1\logical_op__insn_type$29$next[6:0]$10057 $2\logical_op__insn_type$29$next[6:0]$10075 + assign $1\logical_op__invert_in$37$next[0:0]$10058 $2\logical_op__invert_in$37$next[0:0]$10076 + assign $1\logical_op__invert_out$40$next[0:0]$10059 $2\logical_op__invert_out$40$next[0:0]$10077 + assign $1\logical_op__is_32bit$43$next[0:0]$10060 $2\logical_op__is_32bit$43$next[0:0]$10078 + assign $1\logical_op__is_signed$44$next[0:0]$10061 $2\logical_op__is_signed$44$next[0:0]$10079 + assign $1\logical_op__oe__oe$35$next[0:0]$10062 $2\logical_op__oe__oe$35$next[0:0]$10080 + assign $1\logical_op__oe__ok$36$next[0:0]$10063 $2\logical_op__oe__ok$36$next[0:0]$10081 + assign $1\logical_op__output_carry$42$next[0:0]$10064 $2\logical_op__output_carry$42$next[0:0]$10082 + assign $1\logical_op__rc__ok$34$next[0:0]$10065 $2\logical_op__rc__ok$34$next[0:0]$10083 + assign $1\logical_op__rc__rc$33$next[0:0]$10066 $2\logical_op__rc__rc$33$next[0:0]$10084 + assign $1\logical_op__write_cr0$41$next[0:0]$10067 $2\logical_op__write_cr0$41$next[0:0]$10085 + assign $1\logical_op__zero_a$38$next[0:0]$10068 $2\logical_op__zero_a$38$next[0:0]$10086 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" @@ -356111,46 +322654,46 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign { $2\logical_op__insn$46$next[31:0]$10142 $2\logical_op__data_len$45$next[3:0]$10137 $2\logical_op__is_signed$44$next[0:0]$10147 $2\logical_op__is_32bit$43$next[0:0]$10146 $2\logical_op__output_carry$42$next[0:0]$10150 $2\logical_op__write_cr0$41$next[0:0]$10153 $2\logical_op__invert_out$40$next[0:0]$10145 $2\logical_op__input_carry$39$next[1:0]$10141 $2\logical_op__zero_a$38$next[0:0]$10154 $2\logical_op__invert_in$37$next[0:0]$10144 $2\logical_op__oe__ok$36$next[0:0]$10149 $2\logical_op__oe__oe$35$next[0:0]$10148 $2\logical_op__rc__ok$34$next[0:0]$10151 $2\logical_op__rc__rc$33$next[0:0]$10152 $2\logical_op__imm_data__ok$32$next[0:0]$10140 $2\logical_op__imm_data__data$31$next[63:0]$10139 $2\logical_op__fn_unit$30$next[13:0]$10138 $2\logical_op__insn_type$29$next[6:0]$10143 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + assign { $2\logical_op__insn$46$next[31:0]$10074 $2\logical_op__data_len$45$next[3:0]$10069 $2\logical_op__is_signed$44$next[0:0]$10079 $2\logical_op__is_32bit$43$next[0:0]$10078 $2\logical_op__output_carry$42$next[0:0]$10082 $2\logical_op__write_cr0$41$next[0:0]$10085 $2\logical_op__invert_out$40$next[0:0]$10077 $2\logical_op__input_carry$39$next[1:0]$10073 $2\logical_op__zero_a$38$next[0:0]$10086 $2\logical_op__invert_in$37$next[0:0]$10076 $2\logical_op__oe__ok$36$next[0:0]$10081 $2\logical_op__oe__oe$35$next[0:0]$10080 $2\logical_op__rc__ok$34$next[0:0]$10083 $2\logical_op__rc__rc$33$next[0:0]$10084 $2\logical_op__imm_data__ok$32$next[0:0]$10072 $2\logical_op__imm_data__data$31$next[63:0]$10071 $2\logical_op__fn_unit$30$next[13:0]$10070 $2\logical_op__insn_type$29$next[6:0]$10075 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } case - assign $2\logical_op__data_len$45$next[3:0]$10137 \logical_op__data_len$45 - assign $2\logical_op__fn_unit$30$next[13:0]$10138 \logical_op__fn_unit$30 - assign $2\logical_op__imm_data__data$31$next[63:0]$10139 \logical_op__imm_data__data$31 - assign $2\logical_op__imm_data__ok$32$next[0:0]$10140 \logical_op__imm_data__ok$32 - assign $2\logical_op__input_carry$39$next[1:0]$10141 \logical_op__input_carry$39 - assign $2\logical_op__insn$46$next[31:0]$10142 \logical_op__insn$46 - assign $2\logical_op__insn_type$29$next[6:0]$10143 \logical_op__insn_type$29 - assign $2\logical_op__invert_in$37$next[0:0]$10144 \logical_op__invert_in$37 - assign $2\logical_op__invert_out$40$next[0:0]$10145 \logical_op__invert_out$40 - assign $2\logical_op__is_32bit$43$next[0:0]$10146 \logical_op__is_32bit$43 - assign $2\logical_op__is_signed$44$next[0:0]$10147 \logical_op__is_signed$44 - assign $2\logical_op__oe__oe$35$next[0:0]$10148 \logical_op__oe__oe$35 - assign $2\logical_op__oe__ok$36$next[0:0]$10149 \logical_op__oe__ok$36 - assign $2\logical_op__output_carry$42$next[0:0]$10150 \logical_op__output_carry$42 - assign $2\logical_op__rc__ok$34$next[0:0]$10151 \logical_op__rc__ok$34 - assign $2\logical_op__rc__rc$33$next[0:0]$10152 \logical_op__rc__rc$33 - assign $2\logical_op__write_cr0$41$next[0:0]$10153 \logical_op__write_cr0$41 - assign $2\logical_op__zero_a$38$next[0:0]$10154 \logical_op__zero_a$38 + assign $2\logical_op__data_len$45$next[3:0]$10069 \logical_op__data_len$45 + assign $2\logical_op__fn_unit$30$next[13:0]$10070 \logical_op__fn_unit$30 + assign $2\logical_op__imm_data__data$31$next[63:0]$10071 \logical_op__imm_data__data$31 + assign $2\logical_op__imm_data__ok$32$next[0:0]$10072 \logical_op__imm_data__ok$32 + assign $2\logical_op__input_carry$39$next[1:0]$10073 \logical_op__input_carry$39 + assign $2\logical_op__insn$46$next[31:0]$10074 \logical_op__insn$46 + assign $2\logical_op__insn_type$29$next[6:0]$10075 \logical_op__insn_type$29 + assign $2\logical_op__invert_in$37$next[0:0]$10076 \logical_op__invert_in$37 + assign $2\logical_op__invert_out$40$next[0:0]$10077 \logical_op__invert_out$40 + assign $2\logical_op__is_32bit$43$next[0:0]$10078 \logical_op__is_32bit$43 + assign $2\logical_op__is_signed$44$next[0:0]$10079 \logical_op__is_signed$44 + assign $2\logical_op__oe__oe$35$next[0:0]$10080 \logical_op__oe__oe$35 + assign $2\logical_op__oe__ok$36$next[0:0]$10081 \logical_op__oe__ok$36 + assign $2\logical_op__output_carry$42$next[0:0]$10082 \logical_op__output_carry$42 + assign $2\logical_op__rc__ok$34$next[0:0]$10083 \logical_op__rc__ok$34 + assign $2\logical_op__rc__rc$33$next[0:0]$10084 \logical_op__rc__rc$33 + assign $2\logical_op__write_cr0$41$next[0:0]$10085 \logical_op__write_cr0$41 + assign $2\logical_op__zero_a$38$next[0:0]$10086 \logical_op__zero_a$38 end case - assign $1\logical_op__data_len$45$next[3:0]$10119 \logical_op__data_len$45 - assign $1\logical_op__fn_unit$30$next[13:0]$10120 \logical_op__fn_unit$30 - assign $1\logical_op__imm_data__data$31$next[63:0]$10121 \logical_op__imm_data__data$31 - assign $1\logical_op__imm_data__ok$32$next[0:0]$10122 \logical_op__imm_data__ok$32 - assign $1\logical_op__input_carry$39$next[1:0]$10123 \logical_op__input_carry$39 - assign $1\logical_op__insn$46$next[31:0]$10124 \logical_op__insn$46 - assign $1\logical_op__insn_type$29$next[6:0]$10125 \logical_op__insn_type$29 - assign $1\logical_op__invert_in$37$next[0:0]$10126 \logical_op__invert_in$37 - assign $1\logical_op__invert_out$40$next[0:0]$10127 \logical_op__invert_out$40 - assign $1\logical_op__is_32bit$43$next[0:0]$10128 \logical_op__is_32bit$43 - assign $1\logical_op__is_signed$44$next[0:0]$10129 \logical_op__is_signed$44 - assign $1\logical_op__oe__oe$35$next[0:0]$10130 \logical_op__oe__oe$35 - assign $1\logical_op__oe__ok$36$next[0:0]$10131 \logical_op__oe__ok$36 - assign $1\logical_op__output_carry$42$next[0:0]$10132 \logical_op__output_carry$42 - assign $1\logical_op__rc__ok$34$next[0:0]$10133 \logical_op__rc__ok$34 - assign $1\logical_op__rc__rc$33$next[0:0]$10134 \logical_op__rc__rc$33 - assign $1\logical_op__write_cr0$41$next[0:0]$10135 \logical_op__write_cr0$41 - assign $1\logical_op__zero_a$38$next[0:0]$10136 \logical_op__zero_a$38 + assign $1\logical_op__data_len$45$next[3:0]$10051 \logical_op__data_len$45 + assign $1\logical_op__fn_unit$30$next[13:0]$10052 \logical_op__fn_unit$30 + assign $1\logical_op__imm_data__data$31$next[63:0]$10053 \logical_op__imm_data__data$31 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10054 \logical_op__imm_data__ok$32 + assign $1\logical_op__input_carry$39$next[1:0]$10055 \logical_op__input_carry$39 + assign $1\logical_op__insn$46$next[31:0]$10056 \logical_op__insn$46 + assign $1\logical_op__insn_type$29$next[6:0]$10057 \logical_op__insn_type$29 + assign $1\logical_op__invert_in$37$next[0:0]$10058 \logical_op__invert_in$37 + assign $1\logical_op__invert_out$40$next[0:0]$10059 \logical_op__invert_out$40 + assign $1\logical_op__is_32bit$43$next[0:0]$10060 \logical_op__is_32bit$43 + assign $1\logical_op__is_signed$44$next[0:0]$10061 \logical_op__is_signed$44 + assign $1\logical_op__oe__oe$35$next[0:0]$10062 \logical_op__oe__oe$35 + assign $1\logical_op__oe__ok$36$next[0:0]$10063 \logical_op__oe__ok$36 + assign $1\logical_op__output_carry$42$next[0:0]$10064 \logical_op__output_carry$42 + assign $1\logical_op__rc__ok$34$next[0:0]$10065 \logical_op__rc__ok$34 + assign $1\logical_op__rc__rc$33$next[0:0]$10066 \logical_op__rc__rc$33 + assign $1\logical_op__write_cr0$41$next[0:0]$10067 \logical_op__write_cr0$41 + assign $1\logical_op__zero_a$38$next[0:0]$10068 \logical_op__zero_a$38 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -356162,48 +322705,48 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $3\logical_op__imm_data__data$31$next[63:0]$10155 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\logical_op__imm_data__ok$32$next[0:0]$10156 1'0 - assign $3\logical_op__rc__rc$33$next[0:0]$10160 1'0 - assign $3\logical_op__rc__ok$34$next[0:0]$10159 1'0 - assign $3\logical_op__oe__oe$35$next[0:0]$10157 1'0 - assign $3\logical_op__oe__ok$36$next[0:0]$10158 1'0 + assign $3\logical_op__imm_data__data$31$next[63:0]$10087 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10088 1'0 + assign $3\logical_op__rc__rc$33$next[0:0]$10092 1'0 + assign $3\logical_op__rc__ok$34$next[0:0]$10091 1'0 + assign $3\logical_op__oe__oe$35$next[0:0]$10089 1'0 + assign $3\logical_op__oe__ok$36$next[0:0]$10090 1'0 case - assign $3\logical_op__imm_data__data$31$next[63:0]$10155 $1\logical_op__imm_data__data$31$next[63:0]$10121 - assign $3\logical_op__imm_data__ok$32$next[0:0]$10156 $1\logical_op__imm_data__ok$32$next[0:0]$10122 - assign $3\logical_op__oe__oe$35$next[0:0]$10157 $1\logical_op__oe__oe$35$next[0:0]$10130 - assign $3\logical_op__oe__ok$36$next[0:0]$10158 $1\logical_op__oe__ok$36$next[0:0]$10131 - assign $3\logical_op__rc__ok$34$next[0:0]$10159 $1\logical_op__rc__ok$34$next[0:0]$10133 - assign $3\logical_op__rc__rc$33$next[0:0]$10160 $1\logical_op__rc__rc$33$next[0:0]$10134 + assign $3\logical_op__imm_data__data$31$next[63:0]$10087 $1\logical_op__imm_data__data$31$next[63:0]$10053 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10088 $1\logical_op__imm_data__ok$32$next[0:0]$10054 + assign $3\logical_op__oe__oe$35$next[0:0]$10089 $1\logical_op__oe__oe$35$next[0:0]$10062 + assign $3\logical_op__oe__ok$36$next[0:0]$10090 $1\logical_op__oe__ok$36$next[0:0]$10063 + assign $3\logical_op__rc__ok$34$next[0:0]$10091 $1\logical_op__rc__ok$34$next[0:0]$10065 + assign $3\logical_op__rc__rc$33$next[0:0]$10092 $1\logical_op__rc__rc$33$next[0:0]$10066 end sync always - update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10101 - update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[13:0]$10102 - update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10103 - update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10104 - update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10105 - update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10106 - update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10107 - update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10108 - update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10109 - update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10110 - update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10111 - update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10112 - update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10113 - update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10114 - update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10115 - update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10116 - update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10117 - update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10118 + update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10033 + update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[13:0]$10034 + update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10035 + update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10036 + update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10037 + update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10038 + update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10039 + update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10040 + update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10041 + update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10042 + update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10043 + update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10044 + update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10045 + update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10046 + update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10047 + update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10048 + update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10049 + update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10050 end - attribute \src "libresoc.v:173609.3-173623.6" - process $proc$libresoc.v:173609$10161 + attribute \src "libresoc.v:174377.3-174391.6" + process $proc$libresoc.v:174377$10093 assign { } { } assign { } { } - assign $0\ra$47$next[63:0]$10162 $1\ra$47$next[63:0]$10163 - attribute \src "libresoc.v:173610.5-173610.29" + assign $0\ra$47$next[63:0]$10094 $1\ra$47$next[63:0]$10095 + attribute \src "libresoc.v:174378.5-174378.29" switch \initial - attribute \src "libresoc.v:173610.9-173610.17" + attribute \src "libresoc.v:174378.9-174378.17" case 1'1 case end @@ -356212,30 +322755,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ra$47$next[63:0]$10163 $2\ra$47$next[63:0]$10164 + assign $1\ra$47$next[63:0]$10095 $2\ra$47$next[63:0]$10096 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\ra$47$next[63:0]$10164 \ra + assign $2\ra$47$next[63:0]$10096 \ra case - assign $2\ra$47$next[63:0]$10164 \ra$47 + assign $2\ra$47$next[63:0]$10096 \ra$47 end case - assign $1\ra$47$next[63:0]$10163 \ra$47 + assign $1\ra$47$next[63:0]$10095 \ra$47 end sync always - update \ra$47$next $0\ra$47$next[63:0]$10162 + update \ra$47$next $0\ra$47$next[63:0]$10094 end - attribute \src "libresoc.v:173624.3-173638.6" - process $proc$libresoc.v:173624$10165 + attribute \src "libresoc.v:174392.3-174406.6" + process $proc$libresoc.v:174392$10097 assign { } { } assign { } { } - assign $0\rb$48$next[63:0]$10166 $1\rb$48$next[63:0]$10167 - attribute \src "libresoc.v:173625.5-173625.29" + assign $0\rb$48$next[63:0]$10098 $1\rb$48$next[63:0]$10099 + attribute \src "libresoc.v:174393.5-174393.29" switch \initial - attribute \src "libresoc.v:173625.9-173625.17" + attribute \src "libresoc.v:174393.9-174393.17" case 1'1 case end @@ -356244,30 +322787,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rb$48$next[63:0]$10167 $2\rb$48$next[63:0]$10168 + assign $1\rb$48$next[63:0]$10099 $2\rb$48$next[63:0]$10100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\rb$48$next[63:0]$10168 \rb + assign $2\rb$48$next[63:0]$10100 \rb case - assign $2\rb$48$next[63:0]$10168 \rb$48 + assign $2\rb$48$next[63:0]$10100 \rb$48 end case - assign $1\rb$48$next[63:0]$10167 \rb$48 + assign $1\rb$48$next[63:0]$10099 \rb$48 end sync always - update \rb$48$next $0\rb$48$next[63:0]$10166 + update \rb$48$next $0\rb$48$next[63:0]$10098 end - attribute \src "libresoc.v:173639.3-173653.6" - process $proc$libresoc.v:173639$10169 + attribute \src "libresoc.v:174407.3-174421.6" + process $proc$libresoc.v:174407$10101 assign { } { } assign { } { } - assign $0\xer_so$49$next[0:0]$10170 $1\xer_so$49$next[0:0]$10171 - attribute \src "libresoc.v:173640.5-173640.29" + assign $0\xer_so$49$next[0:0]$10102 $1\xer_so$49$next[0:0]$10103 + attribute \src "libresoc.v:174408.5-174408.29" switch \initial - attribute \src "libresoc.v:173640.9-173640.17" + attribute \src "libresoc.v:174408.9-174408.17" case 1'1 case end @@ -356276,30 +322819,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$49$next[0:0]$10171 $2\xer_so$49$next[0:0]$10172 + assign $1\xer_so$49$next[0:0]$10103 $2\xer_so$49$next[0:0]$10104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so$49$next[0:0]$10172 \xer_so + assign $2\xer_so$49$next[0:0]$10104 \xer_so case - assign $2\xer_so$49$next[0:0]$10172 \xer_so$49 + assign $2\xer_so$49$next[0:0]$10104 \xer_so$49 end case - assign $1\xer_so$49$next[0:0]$10171 \xer_so$49 + assign $1\xer_so$49$next[0:0]$10103 \xer_so$49 end sync always - update \xer_so$49$next $0\xer_so$49$next[0:0]$10170 + update \xer_so$49$next $0\xer_so$49$next[0:0]$10102 end - attribute \src "libresoc.v:173654.3-173668.6" - process $proc$libresoc.v:173654$10173 + attribute \src "libresoc.v:174422.3-174436.6" + process $proc$libresoc.v:174422$10105 assign { } { } assign { } { } - assign $0\divisor_neg$50$next[0:0]$10174 $1\divisor_neg$50$next[0:0]$10175 - attribute \src "libresoc.v:173655.5-173655.29" + assign $0\divisor_neg$50$next[0:0]$10106 $1\divisor_neg$50$next[0:0]$10107 + attribute \src "libresoc.v:174423.5-174423.29" switch \initial - attribute \src "libresoc.v:173655.9-173655.17" + attribute \src "libresoc.v:174423.9-174423.17" case 1'1 case end @@ -356308,30 +322851,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\divisor_neg$50$next[0:0]$10175 $2\divisor_neg$50$next[0:0]$10176 + assign $1\divisor_neg$50$next[0:0]$10107 $2\divisor_neg$50$next[0:0]$10108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\divisor_neg$50$next[0:0]$10176 \divisor_neg + assign $2\divisor_neg$50$next[0:0]$10108 \divisor_neg case - assign $2\divisor_neg$50$next[0:0]$10176 \divisor_neg$50 + assign $2\divisor_neg$50$next[0:0]$10108 \divisor_neg$50 end case - assign $1\divisor_neg$50$next[0:0]$10175 \divisor_neg$50 + assign $1\divisor_neg$50$next[0:0]$10107 \divisor_neg$50 end sync always - update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10174 + update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10106 end - attribute \src "libresoc.v:173669.3-173683.6" - process $proc$libresoc.v:173669$10177 + attribute \src "libresoc.v:174437.3-174451.6" + process $proc$libresoc.v:174437$10109 assign { } { } assign { } { } - assign $0\dividend_neg$51$next[0:0]$10178 $1\dividend_neg$51$next[0:0]$10179 - attribute \src "libresoc.v:173670.5-173670.29" + assign $0\dividend_neg$51$next[0:0]$10110 $1\dividend_neg$51$next[0:0]$10111 + attribute \src "libresoc.v:174438.5-174438.29" switch \initial - attribute \src "libresoc.v:173670.9-173670.17" + attribute \src "libresoc.v:174438.9-174438.17" case 1'1 case end @@ -356340,30 +322883,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend_neg$51$next[0:0]$10179 $2\dividend_neg$51$next[0:0]$10180 + assign $1\dividend_neg$51$next[0:0]$10111 $2\dividend_neg$51$next[0:0]$10112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dividend_neg$51$next[0:0]$10180 \dividend_neg + assign $2\dividend_neg$51$next[0:0]$10112 \dividend_neg case - assign $2\dividend_neg$51$next[0:0]$10180 \dividend_neg$51 + assign $2\dividend_neg$51$next[0:0]$10112 \dividend_neg$51 end case - assign $1\dividend_neg$51$next[0:0]$10179 \dividend_neg$51 + assign $1\dividend_neg$51$next[0:0]$10111 \dividend_neg$51 end sync always - update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10178 + update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10110 end - attribute \src "libresoc.v:173684.3-173698.6" - process $proc$libresoc.v:173684$10181 + attribute \src "libresoc.v:174452.3-174466.6" + process $proc$libresoc.v:174452$10113 assign { } { } assign { } { } - assign $0\dive_abs_ov32$52$next[0:0]$10182 $1\dive_abs_ov32$52$next[0:0]$10183 - attribute \src "libresoc.v:173685.5-173685.29" + assign $0\dive_abs_ov32$52$next[0:0]$10114 $1\dive_abs_ov32$52$next[0:0]$10115 + attribute \src "libresoc.v:174453.5-174453.29" switch \initial - attribute \src "libresoc.v:173685.9-173685.17" + attribute \src "libresoc.v:174453.9-174453.17" case 1'1 case end @@ -356372,30 +322915,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dive_abs_ov32$52$next[0:0]$10183 $2\dive_abs_ov32$52$next[0:0]$10184 + assign $1\dive_abs_ov32$52$next[0:0]$10115 $2\dive_abs_ov32$52$next[0:0]$10116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dive_abs_ov32$52$next[0:0]$10184 \dive_abs_ov32 + assign $2\dive_abs_ov32$52$next[0:0]$10116 \dive_abs_ov32 case - assign $2\dive_abs_ov32$52$next[0:0]$10184 \dive_abs_ov32$52 + assign $2\dive_abs_ov32$52$next[0:0]$10116 \dive_abs_ov32$52 end case - assign $1\dive_abs_ov32$52$next[0:0]$10183 \dive_abs_ov32$52 + assign $1\dive_abs_ov32$52$next[0:0]$10115 \dive_abs_ov32$52 end sync always - update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10182 + update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10114 end - attribute \src "libresoc.v:173699.3-173713.6" - process $proc$libresoc.v:173699$10185 + attribute \src "libresoc.v:174467.3-174481.6" + process $proc$libresoc.v:174467$10117 assign { } { } assign { } { } - assign $0\dive_abs_ov64$53$next[0:0]$10186 $1\dive_abs_ov64$53$next[0:0]$10187 - attribute \src "libresoc.v:173700.5-173700.29" + assign $0\dive_abs_ov64$53$next[0:0]$10118 $1\dive_abs_ov64$53$next[0:0]$10119 + attribute \src "libresoc.v:174468.5-174468.29" switch \initial - attribute \src "libresoc.v:173700.9-173700.17" + attribute \src "libresoc.v:174468.9-174468.17" case 1'1 case end @@ -356404,30 +322947,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dive_abs_ov64$53$next[0:0]$10187 $2\dive_abs_ov64$53$next[0:0]$10188 + assign $1\dive_abs_ov64$53$next[0:0]$10119 $2\dive_abs_ov64$53$next[0:0]$10120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dive_abs_ov64$53$next[0:0]$10188 \dive_abs_ov64 + assign $2\dive_abs_ov64$53$next[0:0]$10120 \dive_abs_ov64 case - assign $2\dive_abs_ov64$53$next[0:0]$10188 \dive_abs_ov64$53 + assign $2\dive_abs_ov64$53$next[0:0]$10120 \dive_abs_ov64$53 end case - assign $1\dive_abs_ov64$53$next[0:0]$10187 \dive_abs_ov64$53 + assign $1\dive_abs_ov64$53$next[0:0]$10119 \dive_abs_ov64$53 end sync always - update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10186 + update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10118 end - attribute \src "libresoc.v:173714.3-173728.6" - process $proc$libresoc.v:173714$10189 + attribute \src "libresoc.v:174482.3-174496.6" + process $proc$libresoc.v:174482$10121 assign { } { } assign { } { } - assign $0\div_by_zero$54$next[0:0]$10190 $1\div_by_zero$54$next[0:0]$10191 - attribute \src "libresoc.v:173715.5-173715.29" + assign $0\div_by_zero$54$next[0:0]$10122 $1\div_by_zero$54$next[0:0]$10123 + attribute \src "libresoc.v:174483.5-174483.29" switch \initial - attribute \src "libresoc.v:173715.9-173715.17" + attribute \src "libresoc.v:174483.9-174483.17" case 1'1 case end @@ -356436,30 +322979,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\div_by_zero$54$next[0:0]$10191 $2\div_by_zero$54$next[0:0]$10192 + assign $1\div_by_zero$54$next[0:0]$10123 $2\div_by_zero$54$next[0:0]$10124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\div_by_zero$54$next[0:0]$10192 \div_by_zero + assign $2\div_by_zero$54$next[0:0]$10124 \div_by_zero case - assign $2\div_by_zero$54$next[0:0]$10192 \div_by_zero$54 + assign $2\div_by_zero$54$next[0:0]$10124 \div_by_zero$54 end case - assign $1\div_by_zero$54$next[0:0]$10191 \div_by_zero$54 + assign $1\div_by_zero$54$next[0:0]$10123 \div_by_zero$54 end sync always - update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10190 + update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10122 end - attribute \src "libresoc.v:173729.3-173743.6" - process $proc$libresoc.v:173729$10193 + attribute \src "libresoc.v:174497.3-174511.6" + process $proc$libresoc.v:174497$10125 assign { } { } assign { } { } - assign $0\dividend$68$next[127:0]$10194 $1\dividend$68$next[127:0]$10195 - attribute \src "libresoc.v:173730.5-173730.29" + assign $0\dividend$68$next[127:0]$10126 $1\dividend$68$next[127:0]$10127 + attribute \src "libresoc.v:174498.5-174498.29" switch \initial - attribute \src "libresoc.v:173730.9-173730.17" + attribute \src "libresoc.v:174498.9-174498.17" case 1'1 case end @@ -356468,30 +323011,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend$68$next[127:0]$10195 $2\dividend$68$next[127:0]$10196 + assign $1\dividend$68$next[127:0]$10127 $2\dividend$68$next[127:0]$10128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dividend$68$next[127:0]$10196 \dividend + assign $2\dividend$68$next[127:0]$10128 \dividend case - assign $2\dividend$68$next[127:0]$10196 \dividend$68 + assign $2\dividend$68$next[127:0]$10128 \dividend$68 end case - assign $1\dividend$68$next[127:0]$10195 \dividend$68 + assign $1\dividend$68$next[127:0]$10127 \dividend$68 end sync always - update \dividend$68$next $0\dividend$68$next[127:0]$10194 + update \dividend$68$next $0\dividend$68$next[127:0]$10126 end - attribute \src "libresoc.v:173744.3-173758.6" - process $proc$libresoc.v:173744$10197 + attribute \src "libresoc.v:174512.3-174526.6" + process $proc$libresoc.v:174512$10129 assign { } { } assign { } { } - assign $0\divisor_radicand$65$next[63:0]$10198 $1\divisor_radicand$65$next[63:0]$10199 - attribute \src "libresoc.v:173745.5-173745.29" + assign $0\divisor_radicand$65$next[63:0]$10130 $1\divisor_radicand$65$next[63:0]$10131 + attribute \src "libresoc.v:174513.5-174513.29" switch \initial - attribute \src "libresoc.v:173745.9-173745.17" + attribute \src "libresoc.v:174513.9-174513.17" case 1'1 case end @@ -356500,30 +323043,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\divisor_radicand$65$next[63:0]$10199 $2\divisor_radicand$65$next[63:0]$10200 + assign $1\divisor_radicand$65$next[63:0]$10131 $2\divisor_radicand$65$next[63:0]$10132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\divisor_radicand$65$next[63:0]$10200 \divisor_radicand + assign $2\divisor_radicand$65$next[63:0]$10132 \divisor_radicand case - assign $2\divisor_radicand$65$next[63:0]$10200 \divisor_radicand$65 + assign $2\divisor_radicand$65$next[63:0]$10132 \divisor_radicand$65 end case - assign $1\divisor_radicand$65$next[63:0]$10199 \divisor_radicand$65 + assign $1\divisor_radicand$65$next[63:0]$10131 \divisor_radicand$65 end sync always - update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10198 + update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10130 end - attribute \src "libresoc.v:173759.3-173773.6" - process $proc$libresoc.v:173759$10201 + attribute \src "libresoc.v:174527.3-174541.6" + process $proc$libresoc.v:174527$10133 assign { } { } assign { } { } - assign $0\operation$69$next[1:0]$10202 $1\operation$69$next[1:0]$10203 - attribute \src "libresoc.v:173760.5-173760.29" + assign $0\operation$69$next[1:0]$10134 $1\operation$69$next[1:0]$10135 + attribute \src "libresoc.v:174528.5-174528.29" switch \initial - attribute \src "libresoc.v:173760.9-173760.17" + attribute \src "libresoc.v:174528.9-174528.17" case 1'1 case end @@ -356532,28 +323075,28 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\operation$69$next[1:0]$10203 $2\operation$69$next[1:0]$10204 + assign $1\operation$69$next[1:0]$10135 $2\operation$69$next[1:0]$10136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\operation$69$next[1:0]$10204 \operation + assign $2\operation$69$next[1:0]$10136 \operation case - assign $2\operation$69$next[1:0]$10204 \operation$69 + assign $2\operation$69$next[1:0]$10136 \operation$69 end case - assign $1\operation$69$next[1:0]$10203 \operation$69 + assign $1\operation$69$next[1:0]$10135 \operation$69 end sync always - update \operation$69$next $0\operation$69$next[1:0]$10202 + update \operation$69$next $0\operation$69$next[1:0]$10134 end - connect \$56 $sshl$libresoc.v:173376$10011_Y - connect \$55 $pos$libresoc.v:173377$10013_Y - connect \$59 $not$libresoc.v:173378$10014_Y - connect \$61 $ge$libresoc.v:173379$10015_Y - connect \$63 $and$libresoc.v:173380$10016_Y - connect \$66 $and$libresoc.v:173381$10017_Y + connect \$56 $sshl$libresoc.v:174144$9943_Y + connect \$55 $pos$libresoc.v:174145$9945_Y + connect \$59 $not$libresoc.v:174146$9946_Y + connect \$61 $ge$libresoc.v:174147$9947_Y + connect \$63 $and$libresoc.v:174148$9948_Y + connect \$66 $and$libresoc.v:174149$9949_Y connect \p_ready_o \empty connect \n_valid_o \$63 connect \remainder \$55 @@ -356570,282 +323113,282 @@ module \pipe_middle_0 connect \muxid$1 \muxid$28 connect \div_state_init_dividend \dividend end -attribute \src "libresoc.v:173793.1-175338.10" +attribute \src "libresoc.v:174561.1-176106.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" attribute \generator "nMigen" module \pipe_start - attribute \src "libresoc.v:175144.3-175156.6" - wire $0\div_by_zero$next[0:0]$10314 - attribute \src "libresoc.v:174930.3-174931.39" + attribute \src "libresoc.v:175912.3-175924.6" + wire $0\div_by_zero$next[0:0]$10246 + attribute \src "libresoc.v:175698.3-175699.39" wire $0\div_by_zero[0:0] - attribute \src "libresoc.v:175118.3-175130.6" - wire $0\dive_abs_ov32$next[0:0]$10308 - attribute \src "libresoc.v:174934.3-174935.43" + attribute \src "libresoc.v:175886.3-175898.6" + wire $0\dive_abs_ov32$next[0:0]$10240 + attribute \src "libresoc.v:175702.3-175703.43" wire $0\dive_abs_ov32[0:0] - attribute \src "libresoc.v:175131.3-175143.6" - wire $0\dive_abs_ov64$next[0:0]$10311 - attribute \src "libresoc.v:174932.3-174933.43" + attribute \src "libresoc.v:175899.3-175911.6" + wire $0\dive_abs_ov64$next[0:0]$10243 + attribute \src "libresoc.v:175700.3-175701.43" wire $0\dive_abs_ov64[0:0] - attribute \src "libresoc.v:175157.3-175169.6" - wire width 128 $0\dividend$next[127:0]$10317 - attribute \src "libresoc.v:174928.3-174929.33" + attribute \src "libresoc.v:175925.3-175937.6" + wire width 128 $0\dividend$next[127:0]$10249 + attribute \src "libresoc.v:175696.3-175697.33" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:175105.3-175117.6" - wire $0\dividend_neg$next[0:0]$10305 - attribute \src "libresoc.v:174936.3-174937.41" + attribute \src "libresoc.v:175873.3-175885.6" + wire $0\dividend_neg$next[0:0]$10237 + attribute \src "libresoc.v:175704.3-175705.41" wire $0\dividend_neg[0:0] - attribute \src "libresoc.v:175092.3-175104.6" - wire $0\divisor_neg$next[0:0]$10302 - attribute \src "libresoc.v:174938.3-174939.39" + attribute \src "libresoc.v:175860.3-175872.6" + wire $0\divisor_neg$next[0:0]$10234 + attribute \src "libresoc.v:175706.3-175707.39" wire $0\divisor_neg[0:0] - attribute \src "libresoc.v:175170.3-175182.6" - wire width 64 $0\divisor_radicand$next[63:0]$10320 - attribute \src "libresoc.v:174926.3-174927.49" + attribute \src "libresoc.v:175938.3-175950.6" + wire width 64 $0\divisor_radicand$next[63:0]$10252 + attribute \src "libresoc.v:175694.3-175695.49" wire width 64 $0\divisor_radicand[63:0] - attribute \src "libresoc.v:173794.7-173794.20" + attribute \src "libresoc.v:174562.7-174562.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire width 4 $0\logical_op__data_len$next[3:0]$10333 - attribute \src "libresoc.v:174978.3-174979.57" + attribute \src "libresoc.v:175995.3-176036.6" + wire width 4 $0\logical_op__data_len$next[3:0]$10265 + attribute \src "libresoc.v:175746.3-175747.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire width 14 $0\logical_op__fn_unit$next[13:0]$10334 - attribute \src "libresoc.v:174948.3-174949.55" + attribute \src "libresoc.v:175995.3-176036.6" + wire width 14 $0\logical_op__fn_unit$next[13:0]$10266 + attribute \src "libresoc.v:175716.3-175717.55" wire width 14 $0\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$10335 - attribute \src "libresoc.v:174950.3-174951.69" + attribute \src "libresoc.v:175995.3-176036.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$10267 + attribute \src "libresoc.v:175718.3-175719.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $0\logical_op__imm_data__ok$next[0:0]$10336 - attribute \src "libresoc.v:174952.3-174953.65" + attribute \src "libresoc.v:175995.3-176036.6" + wire $0\logical_op__imm_data__ok$next[0:0]$10268 + attribute \src "libresoc.v:175720.3-175721.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$10337 - attribute \src "libresoc.v:174966.3-174967.63" + attribute \src "libresoc.v:175995.3-176036.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$10269 + attribute \src "libresoc.v:175734.3-175735.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire width 32 $0\logical_op__insn$next[31:0]$10338 - attribute \src "libresoc.v:174980.3-174981.49" + attribute \src "libresoc.v:175995.3-176036.6" + wire width 32 $0\logical_op__insn$next[31:0]$10270 + attribute \src "libresoc.v:175748.3-175749.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$10339 - attribute \src "libresoc.v:174946.3-174947.59" + attribute \src "libresoc.v:175995.3-176036.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$10271 + attribute \src "libresoc.v:175714.3-175715.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $0\logical_op__invert_in$next[0:0]$10340 - attribute \src "libresoc.v:174962.3-174963.59" + attribute \src "libresoc.v:175995.3-176036.6" + wire $0\logical_op__invert_in$next[0:0]$10272 + attribute \src "libresoc.v:175730.3-175731.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $0\logical_op__invert_out$next[0:0]$10341 - attribute \src "libresoc.v:174968.3-174969.61" + attribute \src "libresoc.v:175995.3-176036.6" + wire $0\logical_op__invert_out$next[0:0]$10273 + attribute \src "libresoc.v:175736.3-175737.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $0\logical_op__is_32bit$next[0:0]$10342 - attribute \src "libresoc.v:174974.3-174975.57" + attribute \src "libresoc.v:175995.3-176036.6" + wire $0\logical_op__is_32bit$next[0:0]$10274 + attribute \src "libresoc.v:175742.3-175743.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $0\logical_op__is_signed$next[0:0]$10343 - attribute \src "libresoc.v:174976.3-174977.59" + attribute \src "libresoc.v:175995.3-176036.6" + wire $0\logical_op__is_signed$next[0:0]$10275 + attribute \src "libresoc.v:175744.3-175745.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $0\logical_op__oe__oe$next[0:0]$10344 - attribute \src "libresoc.v:174958.3-174959.53" + attribute \src "libresoc.v:175995.3-176036.6" + wire $0\logical_op__oe__oe$next[0:0]$10276 + attribute \src "libresoc.v:175726.3-175727.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $0\logical_op__oe__ok$next[0:0]$10345 - attribute \src "libresoc.v:174960.3-174961.53" + attribute \src "libresoc.v:175995.3-176036.6" + wire $0\logical_op__oe__ok$next[0:0]$10277 + attribute \src "libresoc.v:175728.3-175729.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $0\logical_op__output_carry$next[0:0]$10346 - attribute \src "libresoc.v:174972.3-174973.65" + attribute \src "libresoc.v:175995.3-176036.6" + wire $0\logical_op__output_carry$next[0:0]$10278 + attribute \src "libresoc.v:175740.3-175741.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $0\logical_op__rc__ok$next[0:0]$10347 - attribute \src "libresoc.v:174956.3-174957.53" + attribute \src "libresoc.v:175995.3-176036.6" + wire $0\logical_op__rc__ok$next[0:0]$10279 + attribute \src "libresoc.v:175724.3-175725.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $0\logical_op__rc__rc$next[0:0]$10348 - attribute \src "libresoc.v:174954.3-174955.53" + attribute \src "libresoc.v:175995.3-176036.6" + wire $0\logical_op__rc__rc$next[0:0]$10280 + attribute \src "libresoc.v:175722.3-175723.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $0\logical_op__write_cr0$next[0:0]$10349 - attribute \src "libresoc.v:174970.3-174971.59" + attribute \src "libresoc.v:175995.3-176036.6" + wire $0\logical_op__write_cr0$next[0:0]$10281 + attribute \src "libresoc.v:175738.3-175739.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $0\logical_op__zero_a$next[0:0]$10350 - attribute \src "libresoc.v:174964.3-174965.53" + attribute \src "libresoc.v:175995.3-176036.6" + wire $0\logical_op__zero_a$next[0:0]$10282 + attribute \src "libresoc.v:175732.3-175733.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:175214.3-175226.6" - wire width 2 $0\muxid$next[1:0]$10330 - attribute \src "libresoc.v:174982.3-174983.27" + attribute \src "libresoc.v:175982.3-175994.6" + wire width 2 $0\muxid$next[1:0]$10262 + attribute \src "libresoc.v:175750.3-175751.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:175183.3-175195.6" - wire width 2 $0\operation$next[1:0]$10323 - attribute \src "libresoc.v:174924.3-174925.35" + attribute \src "libresoc.v:175951.3-175963.6" + wire width 2 $0\operation$next[1:0]$10255 + attribute \src "libresoc.v:175692.3-175693.35" wire width 2 $0\operation[1:0] - attribute \src "libresoc.v:175196.3-175213.6" - wire $0\r_busy$next[0:0]$10326 - attribute \src "libresoc.v:174984.3-174985.29" + attribute \src "libresoc.v:175964.3-175981.6" + wire $0\r_busy$next[0:0]$10258 + attribute \src "libresoc.v:175752.3-175753.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:175269.3-175281.6" - wire width 64 $0\ra$next[63:0]$10376 - attribute \src "libresoc.v:174944.3-174945.21" + attribute \src "libresoc.v:176037.3-176049.6" + wire width 64 $0\ra$next[63:0]$10308 + attribute \src "libresoc.v:175712.3-175713.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:175282.3-175294.6" - wire width 64 $0\rb$next[63:0]$10379 - attribute \src "libresoc.v:174942.3-174943.21" + attribute \src "libresoc.v:176050.3-176062.6" + wire width 64 $0\rb$next[63:0]$10311 + attribute \src "libresoc.v:175710.3-175711.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:175295.3-175307.6" - wire $0\xer_so$next[0:0]$10382 - attribute \src "libresoc.v:174940.3-174941.29" + attribute \src "libresoc.v:176063.3-176075.6" + wire $0\xer_so$next[0:0]$10314 + attribute \src "libresoc.v:175708.3-175709.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:175144.3-175156.6" - wire $1\div_by_zero$next[0:0]$10315 - attribute \src "libresoc.v:173803.7-173803.25" + attribute \src "libresoc.v:175912.3-175924.6" + wire $1\div_by_zero$next[0:0]$10247 + attribute \src "libresoc.v:174571.7-174571.25" wire $1\div_by_zero[0:0] - attribute \src "libresoc.v:175118.3-175130.6" - wire $1\dive_abs_ov32$next[0:0]$10309 - attribute \src "libresoc.v:173810.7-173810.27" + attribute \src "libresoc.v:175886.3-175898.6" + wire $1\dive_abs_ov32$next[0:0]$10241 + attribute \src "libresoc.v:174578.7-174578.27" wire $1\dive_abs_ov32[0:0] - attribute \src "libresoc.v:175131.3-175143.6" - wire $1\dive_abs_ov64$next[0:0]$10312 - attribute \src "libresoc.v:173817.7-173817.27" + attribute \src "libresoc.v:175899.3-175911.6" + wire $1\dive_abs_ov64$next[0:0]$10244 + attribute \src "libresoc.v:174585.7-174585.27" wire $1\dive_abs_ov64[0:0] - attribute \src "libresoc.v:175157.3-175169.6" - wire width 128 $1\dividend$next[127:0]$10318 - attribute \src "libresoc.v:173824.15-173824.63" + attribute \src "libresoc.v:175925.3-175937.6" + wire width 128 $1\dividend$next[127:0]$10250 + attribute \src "libresoc.v:174592.15-174592.63" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:175105.3-175117.6" - wire $1\dividend_neg$next[0:0]$10306 - attribute \src "libresoc.v:173831.7-173831.26" + attribute \src "libresoc.v:175873.3-175885.6" + wire $1\dividend_neg$next[0:0]$10238 + attribute \src "libresoc.v:174599.7-174599.26" wire $1\dividend_neg[0:0] - attribute \src "libresoc.v:175092.3-175104.6" - wire $1\divisor_neg$next[0:0]$10303 - attribute \src "libresoc.v:173838.7-173838.25" + attribute \src "libresoc.v:175860.3-175872.6" + wire $1\divisor_neg$next[0:0]$10235 + attribute \src "libresoc.v:174606.7-174606.25" wire $1\divisor_neg[0:0] - attribute \src "libresoc.v:175170.3-175182.6" - wire width 64 $1\divisor_radicand$next[63:0]$10321 - attribute \src "libresoc.v:173845.14-173845.53" + attribute \src "libresoc.v:175938.3-175950.6" + wire width 64 $1\divisor_radicand$next[63:0]$10253 + attribute \src "libresoc.v:174613.14-174613.53" wire width 64 $1\divisor_radicand[63:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire width 4 $1\logical_op__data_len$next[3:0]$10351 - attribute \src "libresoc.v:174128.13-174128.40" + attribute \src "libresoc.v:175995.3-176036.6" + wire width 4 $1\logical_op__data_len$next[3:0]$10283 + attribute \src "libresoc.v:174896.13-174896.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire width 14 $1\logical_op__fn_unit$next[13:0]$10352 - attribute \src "libresoc.v:174152.14-174152.44" + attribute \src "libresoc.v:175995.3-176036.6" + wire width 14 $1\logical_op__fn_unit$next[13:0]$10284 + attribute \src "libresoc.v:174920.14-174920.44" wire width 14 $1\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$10353 - attribute \src "libresoc.v:174191.14-174191.63" + attribute \src "libresoc.v:175995.3-176036.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$10285 + attribute \src "libresoc.v:174959.14-174959.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $1\logical_op__imm_data__ok$next[0:0]$10354 - attribute \src "libresoc.v:174200.7-174200.38" + attribute \src "libresoc.v:175995.3-176036.6" + wire $1\logical_op__imm_data__ok$next[0:0]$10286 + attribute \src "libresoc.v:174968.7-174968.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$10355 - attribute \src "libresoc.v:174213.13-174213.43" + attribute \src "libresoc.v:175995.3-176036.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$10287 + attribute \src "libresoc.v:174981.13-174981.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire width 32 $1\logical_op__insn$next[31:0]$10356 - attribute \src "libresoc.v:174230.14-174230.38" + attribute \src "libresoc.v:175995.3-176036.6" + wire width 32 $1\logical_op__insn$next[31:0]$10288 + attribute \src "libresoc.v:174998.14-174998.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$10357 - attribute \src "libresoc.v:174314.13-174314.42" + attribute \src "libresoc.v:175995.3-176036.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$10289 + attribute \src "libresoc.v:175082.13-175082.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $1\logical_op__invert_in$next[0:0]$10358 - attribute \src "libresoc.v:174473.7-174473.35" + attribute \src "libresoc.v:175995.3-176036.6" + wire $1\logical_op__invert_in$next[0:0]$10290 + attribute \src "libresoc.v:175241.7-175241.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $1\logical_op__invert_out$next[0:0]$10359 - attribute \src "libresoc.v:174482.7-174482.36" + attribute \src "libresoc.v:175995.3-176036.6" + wire $1\logical_op__invert_out$next[0:0]$10291 + attribute \src "libresoc.v:175250.7-175250.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $1\logical_op__is_32bit$next[0:0]$10360 - attribute \src "libresoc.v:174491.7-174491.34" + attribute \src "libresoc.v:175995.3-176036.6" + wire $1\logical_op__is_32bit$next[0:0]$10292 + attribute \src "libresoc.v:175259.7-175259.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $1\logical_op__is_signed$next[0:0]$10361 - attribute \src "libresoc.v:174500.7-174500.35" + attribute \src "libresoc.v:175995.3-176036.6" + wire $1\logical_op__is_signed$next[0:0]$10293 + attribute \src "libresoc.v:175268.7-175268.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $1\logical_op__oe__oe$next[0:0]$10362 - attribute \src "libresoc.v:174509.7-174509.32" + attribute \src "libresoc.v:175995.3-176036.6" + wire $1\logical_op__oe__oe$next[0:0]$10294 + attribute \src "libresoc.v:175277.7-175277.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $1\logical_op__oe__ok$next[0:0]$10363 - attribute \src "libresoc.v:174518.7-174518.32" + attribute \src "libresoc.v:175995.3-176036.6" + wire $1\logical_op__oe__ok$next[0:0]$10295 + attribute \src "libresoc.v:175286.7-175286.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $1\logical_op__output_carry$next[0:0]$10364 - attribute \src "libresoc.v:174527.7-174527.38" + attribute \src "libresoc.v:175995.3-176036.6" + wire $1\logical_op__output_carry$next[0:0]$10296 + attribute \src "libresoc.v:175295.7-175295.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $1\logical_op__rc__ok$next[0:0]$10365 - attribute \src "libresoc.v:174536.7-174536.32" + attribute \src "libresoc.v:175995.3-176036.6" + wire $1\logical_op__rc__ok$next[0:0]$10297 + attribute \src "libresoc.v:175304.7-175304.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $1\logical_op__rc__rc$next[0:0]$10366 - attribute \src "libresoc.v:174545.7-174545.32" + attribute \src "libresoc.v:175995.3-176036.6" + wire $1\logical_op__rc__rc$next[0:0]$10298 + attribute \src "libresoc.v:175313.7-175313.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $1\logical_op__write_cr0$next[0:0]$10367 - attribute \src "libresoc.v:174554.7-174554.35" + attribute \src "libresoc.v:175995.3-176036.6" + wire $1\logical_op__write_cr0$next[0:0]$10299 + attribute \src "libresoc.v:175322.7-175322.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire $1\logical_op__zero_a$next[0:0]$10368 - attribute \src "libresoc.v:174563.7-174563.32" + attribute \src "libresoc.v:175995.3-176036.6" + wire $1\logical_op__zero_a$next[0:0]$10300 + attribute \src "libresoc.v:175331.7-175331.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:175214.3-175226.6" - wire width 2 $1\muxid$next[1:0]$10331 - attribute \src "libresoc.v:174572.13-174572.25" + attribute \src "libresoc.v:175982.3-175994.6" + wire width 2 $1\muxid$next[1:0]$10263 + attribute \src "libresoc.v:175340.13-175340.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:175183.3-175195.6" - wire width 2 $1\operation$next[1:0]$10324 - attribute \src "libresoc.v:174587.13-174587.29" + attribute \src "libresoc.v:175951.3-175963.6" + wire width 2 $1\operation$next[1:0]$10256 + attribute \src "libresoc.v:175355.13-175355.29" wire width 2 $1\operation[1:0] - attribute \src "libresoc.v:175196.3-175213.6" - wire $1\r_busy$next[0:0]$10327 - attribute \src "libresoc.v:174601.7-174601.20" + attribute \src "libresoc.v:175964.3-175981.6" + wire $1\r_busy$next[0:0]$10259 + attribute \src "libresoc.v:175369.7-175369.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:175269.3-175281.6" - wire width 64 $1\ra$next[63:0]$10377 - attribute \src "libresoc.v:174606.14-174606.39" + attribute \src "libresoc.v:176037.3-176049.6" + wire width 64 $1\ra$next[63:0]$10309 + attribute \src "libresoc.v:175374.14-175374.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:175282.3-175294.6" - wire width 64 $1\rb$next[63:0]$10380 - attribute \src "libresoc.v:174617.14-174617.39" + attribute \src "libresoc.v:176050.3-176062.6" + wire width 64 $1\rb$next[63:0]$10312 + attribute \src "libresoc.v:175385.14-175385.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:175295.3-175307.6" - wire $1\xer_so$next[0:0]$10383 - attribute \src "libresoc.v:174916.7-174916.20" + attribute \src "libresoc.v:176063.3-176075.6" + wire $1\xer_so$next[0:0]$10315 + attribute \src "libresoc.v:175684.7-175684.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:175227.3-175268.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$10369 - attribute \src "libresoc.v:175227.3-175268.6" - wire $2\logical_op__imm_data__ok$next[0:0]$10370 - attribute \src "libresoc.v:175227.3-175268.6" - wire $2\logical_op__oe__oe$next[0:0]$10371 - attribute \src "libresoc.v:175227.3-175268.6" - wire $2\logical_op__oe__ok$next[0:0]$10372 - attribute \src "libresoc.v:175227.3-175268.6" - wire $2\logical_op__rc__ok$next[0:0]$10373 - attribute \src "libresoc.v:175227.3-175268.6" - wire $2\logical_op__rc__rc$next[0:0]$10374 - attribute \src "libresoc.v:175196.3-175213.6" - wire $2\r_busy$next[0:0]$10328 - attribute \src "libresoc.v:174923.18-174923.118" - wire $and$libresoc.v:174923$10269_Y + attribute \src "libresoc.v:175995.3-176036.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$10301 + attribute \src "libresoc.v:175995.3-176036.6" + wire $2\logical_op__imm_data__ok$next[0:0]$10302 + attribute \src "libresoc.v:175995.3-176036.6" + wire $2\logical_op__oe__oe$next[0:0]$10303 + attribute \src "libresoc.v:175995.3-176036.6" + wire $2\logical_op__oe__ok$next[0:0]$10304 + attribute \src "libresoc.v:175995.3-176036.6" + wire $2\logical_op__rc__ok$next[0:0]$10305 + attribute \src "libresoc.v:175995.3-176036.6" + wire $2\logical_op__rc__rc$next[0:0]$10306 + attribute \src "libresoc.v:175964.3-175981.6" + wire $2\r_busy$next[0:0]$10260 + attribute \src "libresoc.v:175691.18-175691.118" + wire $and$libresoc.v:175691$10201_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire output 30 \div_by_zero @@ -356889,7 +323432,7 @@ module \pipe_start wire width 64 \divisor_radicand$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \divisor_radicand$next - attribute \src "libresoc.v:173794.7-173794.15" + attribute \src "libresoc.v:174562.7-174562.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len @@ -357942,7 +324485,7 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:174923$10269 + cell $and $and$libresoc.v:175691$10201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357950,10 +324493,10 @@ module \pipe_start parameter \Y_WIDTH 1 connect \A \p_valid_i$65 connect \B \p_ready_o - connect \Y $and$libresoc.v:174923$10269_Y + connect \Y $and$libresoc.v:175691$10201_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:174986.14-175031.4" + attribute \src "libresoc.v:175754.14-175799.4" cell \input$78 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$40 @@ -358001,19 +324544,19 @@ module \pipe_start connect \xer_so$22 \input_xer_so$44 end attribute \module_not_derived 1 - attribute \src "libresoc.v:175032.10-175035.4" + attribute \src "libresoc.v:175800.10-175803.4" cell \n$77 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:175036.10-175039.4" + attribute \src "libresoc.v:175804.10-175807.4" cell \p$76 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:175040.15-175091.4" + attribute \src "libresoc.v:175808.15-175859.4" cell \setup_stage \setup_stage connect \div_by_zero \setup_stage_div_by_zero connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 @@ -358066,487 +324609,487 @@ module \pipe_start connect \xer_so \setup_stage_xer_so connect \xer_so$20 \setup_stage_xer_so$64 end - attribute \src "libresoc.v:173794.7-173794.20" - process $proc$libresoc.v:173794$10384 + attribute \src "libresoc.v:174562.7-174562.20" + process $proc$libresoc.v:174562$10316 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173803.7-173803.25" - process $proc$libresoc.v:173803$10385 + attribute \src "libresoc.v:174571.7-174571.25" + process $proc$libresoc.v:174571$10317 assign { } { } assign $1\div_by_zero[0:0] 1'0 sync always sync init update \div_by_zero $1\div_by_zero[0:0] end - attribute \src "libresoc.v:173810.7-173810.27" - process $proc$libresoc.v:173810$10386 + attribute \src "libresoc.v:174578.7-174578.27" + process $proc$libresoc.v:174578$10318 assign { } { } assign $1\dive_abs_ov32[0:0] 1'0 sync always sync init update \dive_abs_ov32 $1\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:173817.7-173817.27" - process $proc$libresoc.v:173817$10387 + attribute \src "libresoc.v:174585.7-174585.27" + process $proc$libresoc.v:174585$10319 assign { } { } assign $1\dive_abs_ov64[0:0] 1'0 sync always sync init update \dive_abs_ov64 $1\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:173824.15-173824.63" - process $proc$libresoc.v:173824$10388 + attribute \src "libresoc.v:174592.15-174592.63" + process $proc$libresoc.v:174592$10320 assign { } { } assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dividend $1\dividend[127:0] end - attribute \src "libresoc.v:173831.7-173831.26" - process $proc$libresoc.v:173831$10389 + attribute \src "libresoc.v:174599.7-174599.26" + process $proc$libresoc.v:174599$10321 assign { } { } assign $1\dividend_neg[0:0] 1'0 sync always sync init update \dividend_neg $1\dividend_neg[0:0] end - attribute \src "libresoc.v:173838.7-173838.25" - process $proc$libresoc.v:173838$10390 + attribute \src "libresoc.v:174606.7-174606.25" + process $proc$libresoc.v:174606$10322 assign { } { } assign $1\divisor_neg[0:0] 1'0 sync always sync init update \divisor_neg $1\divisor_neg[0:0] end - attribute \src "libresoc.v:173845.14-173845.53" - process $proc$libresoc.v:173845$10391 + attribute \src "libresoc.v:174613.14-174613.53" + process $proc$libresoc.v:174613$10323 assign { } { } assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \divisor_radicand $1\divisor_radicand[63:0] end - attribute \src "libresoc.v:174128.13-174128.40" - process $proc$libresoc.v:174128$10392 + attribute \src "libresoc.v:174896.13-174896.40" + process $proc$libresoc.v:174896$10324 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:174152.14-174152.44" - process $proc$libresoc.v:174152$10393 + attribute \src "libresoc.v:174920.14-174920.44" + process $proc$libresoc.v:174920$10325 assign { } { } assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:174191.14-174191.63" - process $proc$libresoc.v:174191$10394 + attribute \src "libresoc.v:174959.14-174959.63" + process $proc$libresoc.v:174959$10326 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:174200.7-174200.38" - process $proc$libresoc.v:174200$10395 + attribute \src "libresoc.v:174968.7-174968.38" + process $proc$libresoc.v:174968$10327 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:174213.13-174213.43" - process $proc$libresoc.v:174213$10396 + attribute \src "libresoc.v:174981.13-174981.43" + process $proc$libresoc.v:174981$10328 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:174230.14-174230.38" - process $proc$libresoc.v:174230$10397 + attribute \src "libresoc.v:174998.14-174998.38" + process $proc$libresoc.v:174998$10329 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:174314.13-174314.42" - process $proc$libresoc.v:174314$10398 + attribute \src "libresoc.v:175082.13-175082.42" + process $proc$libresoc.v:175082$10330 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:174473.7-174473.35" - process $proc$libresoc.v:174473$10399 + attribute \src "libresoc.v:175241.7-175241.35" + process $proc$libresoc.v:175241$10331 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:174482.7-174482.36" - process $proc$libresoc.v:174482$10400 + attribute \src "libresoc.v:175250.7-175250.36" + process $proc$libresoc.v:175250$10332 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:174491.7-174491.34" - process $proc$libresoc.v:174491$10401 + attribute \src "libresoc.v:175259.7-175259.34" + process $proc$libresoc.v:175259$10333 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:174500.7-174500.35" - process $proc$libresoc.v:174500$10402 + attribute \src "libresoc.v:175268.7-175268.35" + process $proc$libresoc.v:175268$10334 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:174509.7-174509.32" - process $proc$libresoc.v:174509$10403 + attribute \src "libresoc.v:175277.7-175277.32" + process $proc$libresoc.v:175277$10335 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:174518.7-174518.32" - process $proc$libresoc.v:174518$10404 + attribute \src "libresoc.v:175286.7-175286.32" + process $proc$libresoc.v:175286$10336 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:174527.7-174527.38" - process $proc$libresoc.v:174527$10405 + attribute \src "libresoc.v:175295.7-175295.38" + process $proc$libresoc.v:175295$10337 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:174536.7-174536.32" - process $proc$libresoc.v:174536$10406 + attribute \src "libresoc.v:175304.7-175304.32" + process $proc$libresoc.v:175304$10338 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:174545.7-174545.32" - process $proc$libresoc.v:174545$10407 + attribute \src "libresoc.v:175313.7-175313.32" + process $proc$libresoc.v:175313$10339 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:174554.7-174554.35" - process $proc$libresoc.v:174554$10408 + attribute \src "libresoc.v:175322.7-175322.35" + process $proc$libresoc.v:175322$10340 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:174563.7-174563.32" - process $proc$libresoc.v:174563$10409 + attribute \src "libresoc.v:175331.7-175331.32" + process $proc$libresoc.v:175331$10341 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:174572.13-174572.25" - process $proc$libresoc.v:174572$10410 + attribute \src "libresoc.v:175340.13-175340.25" + process $proc$libresoc.v:175340$10342 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:174587.13-174587.29" - process $proc$libresoc.v:174587$10411 + attribute \src "libresoc.v:175355.13-175355.29" + process $proc$libresoc.v:175355$10343 assign { } { } assign $1\operation[1:0] 2'00 sync always sync init update \operation $1\operation[1:0] end - attribute \src "libresoc.v:174601.7-174601.20" - process $proc$libresoc.v:174601$10412 + attribute \src "libresoc.v:175369.7-175369.20" + process $proc$libresoc.v:175369$10344 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:174606.14-174606.39" - process $proc$libresoc.v:174606$10413 + attribute \src "libresoc.v:175374.14-175374.39" + process $proc$libresoc.v:175374$10345 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:174617.14-174617.39" - process $proc$libresoc.v:174617$10414 + attribute \src "libresoc.v:175385.14-175385.39" + process $proc$libresoc.v:175385$10346 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:174916.7-174916.20" - process $proc$libresoc.v:174916$10415 + attribute \src "libresoc.v:175684.7-175684.20" + process $proc$libresoc.v:175684$10347 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:174924.3-174925.35" - process $proc$libresoc.v:174924$10270 + attribute \src "libresoc.v:175692.3-175693.35" + process $proc$libresoc.v:175692$10202 assign { } { } assign $0\operation[1:0] \operation$next sync posedge \coresync_clk update \operation $0\operation[1:0] end - attribute \src "libresoc.v:174926.3-174927.49" - process $proc$libresoc.v:174926$10271 + attribute \src "libresoc.v:175694.3-175695.49" + process $proc$libresoc.v:175694$10203 assign { } { } assign $0\divisor_radicand[63:0] \divisor_radicand$next sync posedge \coresync_clk update \divisor_radicand $0\divisor_radicand[63:0] end - attribute \src "libresoc.v:174928.3-174929.33" - process $proc$libresoc.v:174928$10272 + attribute \src "libresoc.v:175696.3-175697.33" + process $proc$libresoc.v:175696$10204 assign { } { } assign $0\dividend[127:0] \dividend$next sync posedge \coresync_clk update \dividend $0\dividend[127:0] end - attribute \src "libresoc.v:174930.3-174931.39" - process $proc$libresoc.v:174930$10273 + attribute \src "libresoc.v:175698.3-175699.39" + process $proc$libresoc.v:175698$10205 assign { } { } assign $0\div_by_zero[0:0] \div_by_zero$next sync posedge \coresync_clk update \div_by_zero $0\div_by_zero[0:0] end - attribute \src "libresoc.v:174932.3-174933.43" - process $proc$libresoc.v:174932$10274 + attribute \src "libresoc.v:175700.3-175701.43" + process $proc$libresoc.v:175700$10206 assign { } { } assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next sync posedge \coresync_clk update \dive_abs_ov64 $0\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:174934.3-174935.43" - process $proc$libresoc.v:174934$10275 + attribute \src "libresoc.v:175702.3-175703.43" + process $proc$libresoc.v:175702$10207 assign { } { } assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next sync posedge \coresync_clk update \dive_abs_ov32 $0\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:174936.3-174937.41" - process $proc$libresoc.v:174936$10276 + attribute \src "libresoc.v:175704.3-175705.41" + process $proc$libresoc.v:175704$10208 assign { } { } assign $0\dividend_neg[0:0] \dividend_neg$next sync posedge \coresync_clk update \dividend_neg $0\dividend_neg[0:0] end - attribute \src "libresoc.v:174938.3-174939.39" - process $proc$libresoc.v:174938$10277 + attribute \src "libresoc.v:175706.3-175707.39" + process $proc$libresoc.v:175706$10209 assign { } { } assign $0\divisor_neg[0:0] \divisor_neg$next sync posedge \coresync_clk update \divisor_neg $0\divisor_neg[0:0] end - attribute \src "libresoc.v:174940.3-174941.29" - process $proc$libresoc.v:174940$10278 + attribute \src "libresoc.v:175708.3-175709.29" + process $proc$libresoc.v:175708$10210 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:174942.3-174943.21" - process $proc$libresoc.v:174942$10279 + attribute \src "libresoc.v:175710.3-175711.21" + process $proc$libresoc.v:175710$10211 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:174944.3-174945.21" - process $proc$libresoc.v:174944$10280 + attribute \src "libresoc.v:175712.3-175713.21" + process $proc$libresoc.v:175712$10212 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:174946.3-174947.59" - process $proc$libresoc.v:174946$10281 + attribute \src "libresoc.v:175714.3-175715.59" + process $proc$libresoc.v:175714$10213 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:174948.3-174949.55" - process $proc$libresoc.v:174948$10282 + attribute \src "libresoc.v:175716.3-175717.55" + process $proc$libresoc.v:175716$10214 assign { } { } assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:174950.3-174951.69" - process $proc$libresoc.v:174950$10283 + attribute \src "libresoc.v:175718.3-175719.69" + process $proc$libresoc.v:175718$10215 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:174952.3-174953.65" - process $proc$libresoc.v:174952$10284 + attribute \src "libresoc.v:175720.3-175721.65" + process $proc$libresoc.v:175720$10216 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:174954.3-174955.53" - process $proc$libresoc.v:174954$10285 + attribute \src "libresoc.v:175722.3-175723.53" + process $proc$libresoc.v:175722$10217 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:174956.3-174957.53" - process $proc$libresoc.v:174956$10286 + attribute \src "libresoc.v:175724.3-175725.53" + process $proc$libresoc.v:175724$10218 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:174958.3-174959.53" - process $proc$libresoc.v:174958$10287 + attribute \src "libresoc.v:175726.3-175727.53" + process $proc$libresoc.v:175726$10219 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:174960.3-174961.53" - process $proc$libresoc.v:174960$10288 + attribute \src "libresoc.v:175728.3-175729.53" + process $proc$libresoc.v:175728$10220 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:174962.3-174963.59" - process $proc$libresoc.v:174962$10289 + attribute \src "libresoc.v:175730.3-175731.59" + process $proc$libresoc.v:175730$10221 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:174964.3-174965.53" - process $proc$libresoc.v:174964$10290 + attribute \src "libresoc.v:175732.3-175733.53" + process $proc$libresoc.v:175732$10222 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:174966.3-174967.63" - process $proc$libresoc.v:174966$10291 + attribute \src "libresoc.v:175734.3-175735.63" + process $proc$libresoc.v:175734$10223 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:174968.3-174969.61" - process $proc$libresoc.v:174968$10292 + attribute \src "libresoc.v:175736.3-175737.61" + process $proc$libresoc.v:175736$10224 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:174970.3-174971.59" - process $proc$libresoc.v:174970$10293 + attribute \src "libresoc.v:175738.3-175739.59" + process $proc$libresoc.v:175738$10225 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:174972.3-174973.65" - process $proc$libresoc.v:174972$10294 + attribute \src "libresoc.v:175740.3-175741.65" + process $proc$libresoc.v:175740$10226 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:174974.3-174975.57" - process $proc$libresoc.v:174974$10295 + attribute \src "libresoc.v:175742.3-175743.57" + process $proc$libresoc.v:175742$10227 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:174976.3-174977.59" - process $proc$libresoc.v:174976$10296 + attribute \src "libresoc.v:175744.3-175745.59" + process $proc$libresoc.v:175744$10228 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:174978.3-174979.57" - process $proc$libresoc.v:174978$10297 + attribute \src "libresoc.v:175746.3-175747.57" + process $proc$libresoc.v:175746$10229 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:174980.3-174981.49" - process $proc$libresoc.v:174980$10298 + attribute \src "libresoc.v:175748.3-175749.49" + process $proc$libresoc.v:175748$10230 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:174982.3-174983.27" - process $proc$libresoc.v:174982$10299 + attribute \src "libresoc.v:175750.3-175751.27" + process $proc$libresoc.v:175750$10231 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:174984.3-174985.29" - process $proc$libresoc.v:174984$10300 + attribute \src "libresoc.v:175752.3-175753.29" + process $proc$libresoc.v:175752$10232 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:175092.3-175104.6" - process $proc$libresoc.v:175092$10301 + attribute \src "libresoc.v:175860.3-175872.6" + process $proc$libresoc.v:175860$10233 assign { } { } assign { } { } - assign $0\divisor_neg$next[0:0]$10302 $1\divisor_neg$next[0:0]$10303 - attribute \src "libresoc.v:175093.5-175093.29" + assign $0\divisor_neg$next[0:0]$10234 $1\divisor_neg$next[0:0]$10235 + attribute \src "libresoc.v:175861.5-175861.29" switch \initial - attribute \src "libresoc.v:175093.9-175093.17" + attribute \src "libresoc.v:175861.9-175861.17" case 1'1 case end @@ -358555,25 +325098,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\divisor_neg$next[0:0]$10303 \divisor_neg$92 + assign $1\divisor_neg$next[0:0]$10235 \divisor_neg$92 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\divisor_neg$next[0:0]$10303 \divisor_neg$92 + assign $1\divisor_neg$next[0:0]$10235 \divisor_neg$92 case - assign $1\divisor_neg$next[0:0]$10303 \divisor_neg + assign $1\divisor_neg$next[0:0]$10235 \divisor_neg end sync always - update \divisor_neg$next $0\divisor_neg$next[0:0]$10302 + update \divisor_neg$next $0\divisor_neg$next[0:0]$10234 end - attribute \src "libresoc.v:175105.3-175117.6" - process $proc$libresoc.v:175105$10304 + attribute \src "libresoc.v:175873.3-175885.6" + process $proc$libresoc.v:175873$10236 assign { } { } assign { } { } - assign $0\dividend_neg$next[0:0]$10305 $1\dividend_neg$next[0:0]$10306 - attribute \src "libresoc.v:175106.5-175106.29" + assign $0\dividend_neg$next[0:0]$10237 $1\dividend_neg$next[0:0]$10238 + attribute \src "libresoc.v:175874.5-175874.29" switch \initial - attribute \src "libresoc.v:175106.9-175106.17" + attribute \src "libresoc.v:175874.9-175874.17" case 1'1 case end @@ -358582,25 +325125,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dividend_neg$next[0:0]$10306 \dividend_neg$93 + assign $1\dividend_neg$next[0:0]$10238 \dividend_neg$93 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dividend_neg$next[0:0]$10306 \dividend_neg$93 + assign $1\dividend_neg$next[0:0]$10238 \dividend_neg$93 case - assign $1\dividend_neg$next[0:0]$10306 \dividend_neg + assign $1\dividend_neg$next[0:0]$10238 \dividend_neg end sync always - update \dividend_neg$next $0\dividend_neg$next[0:0]$10305 + update \dividend_neg$next $0\dividend_neg$next[0:0]$10237 end - attribute \src "libresoc.v:175118.3-175130.6" - process $proc$libresoc.v:175118$10307 + attribute \src "libresoc.v:175886.3-175898.6" + process $proc$libresoc.v:175886$10239 assign { } { } assign { } { } - assign $0\dive_abs_ov32$next[0:0]$10308 $1\dive_abs_ov32$next[0:0]$10309 - attribute \src "libresoc.v:175119.5-175119.29" + assign $0\dive_abs_ov32$next[0:0]$10240 $1\dive_abs_ov32$next[0:0]$10241 + attribute \src "libresoc.v:175887.5-175887.29" switch \initial - attribute \src "libresoc.v:175119.9-175119.17" + attribute \src "libresoc.v:175887.9-175887.17" case 1'1 case end @@ -358609,25 +325152,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32$94 + assign $1\dive_abs_ov32$next[0:0]$10241 \dive_abs_ov32$94 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32$94 + assign $1\dive_abs_ov32$next[0:0]$10241 \dive_abs_ov32$94 case - assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32 + assign $1\dive_abs_ov32$next[0:0]$10241 \dive_abs_ov32 end sync always - update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10308 + update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10240 end - attribute \src "libresoc.v:175131.3-175143.6" - process $proc$libresoc.v:175131$10310 + attribute \src "libresoc.v:175899.3-175911.6" + process $proc$libresoc.v:175899$10242 assign { } { } assign { } { } - assign $0\dive_abs_ov64$next[0:0]$10311 $1\dive_abs_ov64$next[0:0]$10312 - attribute \src "libresoc.v:175132.5-175132.29" + assign $0\dive_abs_ov64$next[0:0]$10243 $1\dive_abs_ov64$next[0:0]$10244 + attribute \src "libresoc.v:175900.5-175900.29" switch \initial - attribute \src "libresoc.v:175132.9-175132.17" + attribute \src "libresoc.v:175900.9-175900.17" case 1'1 case end @@ -358636,25 +325179,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64$95 + assign $1\dive_abs_ov64$next[0:0]$10244 \dive_abs_ov64$95 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64$95 + assign $1\dive_abs_ov64$next[0:0]$10244 \dive_abs_ov64$95 case - assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64 + assign $1\dive_abs_ov64$next[0:0]$10244 \dive_abs_ov64 end sync always - update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10311 + update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10243 end - attribute \src "libresoc.v:175144.3-175156.6" - process $proc$libresoc.v:175144$10313 + attribute \src "libresoc.v:175912.3-175924.6" + process $proc$libresoc.v:175912$10245 assign { } { } assign { } { } - assign $0\div_by_zero$next[0:0]$10314 $1\div_by_zero$next[0:0]$10315 - attribute \src "libresoc.v:175145.5-175145.29" + assign $0\div_by_zero$next[0:0]$10246 $1\div_by_zero$next[0:0]$10247 + attribute \src "libresoc.v:175913.5-175913.29" switch \initial - attribute \src "libresoc.v:175145.9-175145.17" + attribute \src "libresoc.v:175913.9-175913.17" case 1'1 case end @@ -358663,25 +325206,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\div_by_zero$next[0:0]$10315 \div_by_zero$96 + assign $1\div_by_zero$next[0:0]$10247 \div_by_zero$96 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\div_by_zero$next[0:0]$10315 \div_by_zero$96 + assign $1\div_by_zero$next[0:0]$10247 \div_by_zero$96 case - assign $1\div_by_zero$next[0:0]$10315 \div_by_zero + assign $1\div_by_zero$next[0:0]$10247 \div_by_zero end sync always - update \div_by_zero$next $0\div_by_zero$next[0:0]$10314 + update \div_by_zero$next $0\div_by_zero$next[0:0]$10246 end - attribute \src "libresoc.v:175157.3-175169.6" - process $proc$libresoc.v:175157$10316 + attribute \src "libresoc.v:175925.3-175937.6" + process $proc$libresoc.v:175925$10248 assign { } { } assign { } { } - assign $0\dividend$next[127:0]$10317 $1\dividend$next[127:0]$10318 - attribute \src "libresoc.v:175158.5-175158.29" + assign $0\dividend$next[127:0]$10249 $1\dividend$next[127:0]$10250 + attribute \src "libresoc.v:175926.5-175926.29" switch \initial - attribute \src "libresoc.v:175158.9-175158.17" + attribute \src "libresoc.v:175926.9-175926.17" case 1'1 case end @@ -358690,25 +325233,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dividend$next[127:0]$10318 \dividend$97 + assign $1\dividend$next[127:0]$10250 \dividend$97 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dividend$next[127:0]$10318 \dividend$97 + assign $1\dividend$next[127:0]$10250 \dividend$97 case - assign $1\dividend$next[127:0]$10318 \dividend + assign $1\dividend$next[127:0]$10250 \dividend end sync always - update \dividend$next $0\dividend$next[127:0]$10317 + update \dividend$next $0\dividend$next[127:0]$10249 end - attribute \src "libresoc.v:175170.3-175182.6" - process $proc$libresoc.v:175170$10319 + attribute \src "libresoc.v:175938.3-175950.6" + process $proc$libresoc.v:175938$10251 assign { } { } assign { } { } - assign $0\divisor_radicand$next[63:0]$10320 $1\divisor_radicand$next[63:0]$10321 - attribute \src "libresoc.v:175171.5-175171.29" + assign $0\divisor_radicand$next[63:0]$10252 $1\divisor_radicand$next[63:0]$10253 + attribute \src "libresoc.v:175939.5-175939.29" switch \initial - attribute \src "libresoc.v:175171.9-175171.17" + attribute \src "libresoc.v:175939.9-175939.17" case 1'1 case end @@ -358717,25 +325260,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand$98 + assign $1\divisor_radicand$next[63:0]$10253 \divisor_radicand$98 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand$98 + assign $1\divisor_radicand$next[63:0]$10253 \divisor_radicand$98 case - assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand + assign $1\divisor_radicand$next[63:0]$10253 \divisor_radicand end sync always - update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10320 + update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10252 end - attribute \src "libresoc.v:175183.3-175195.6" - process $proc$libresoc.v:175183$10322 + attribute \src "libresoc.v:175951.3-175963.6" + process $proc$libresoc.v:175951$10254 assign { } { } assign { } { } - assign $0\operation$next[1:0]$10323 $1\operation$next[1:0]$10324 - attribute \src "libresoc.v:175184.5-175184.29" + assign $0\operation$next[1:0]$10255 $1\operation$next[1:0]$10256 + attribute \src "libresoc.v:175952.5-175952.29" switch \initial - attribute \src "libresoc.v:175184.9-175184.17" + attribute \src "libresoc.v:175952.9-175952.17" case 1'1 case end @@ -358744,26 +325287,26 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\operation$next[1:0]$10324 \operation$99 + assign $1\operation$next[1:0]$10256 \operation$99 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\operation$next[1:0]$10324 \operation$99 + assign $1\operation$next[1:0]$10256 \operation$99 case - assign $1\operation$next[1:0]$10324 \operation + assign $1\operation$next[1:0]$10256 \operation end sync always - update \operation$next $0\operation$next[1:0]$10323 + update \operation$next $0\operation$next[1:0]$10255 end - attribute \src "libresoc.v:175196.3-175213.6" - process $proc$libresoc.v:175196$10325 + attribute \src "libresoc.v:175964.3-175981.6" + process $proc$libresoc.v:175964$10257 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$10326 $2\r_busy$next[0:0]$10328 - attribute \src "libresoc.v:175197.5-175197.29" + assign $0\r_busy$next[0:0]$10258 $2\r_busy$next[0:0]$10260 + attribute \src "libresoc.v:175965.5-175965.29" switch \initial - attribute \src "libresoc.v:175197.9-175197.17" + attribute \src "libresoc.v:175965.9-175965.17" case 1'1 case end @@ -358772,34 +325315,34 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$10327 1'1 + assign $1\r_busy$next[0:0]$10259 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$10327 1'0 + assign $1\r_busy$next[0:0]$10259 1'0 case - assign $1\r_busy$next[0:0]$10327 \r_busy + assign $1\r_busy$next[0:0]$10259 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$10328 1'0 + assign $2\r_busy$next[0:0]$10260 1'0 case - assign $2\r_busy$next[0:0]$10328 $1\r_busy$next[0:0]$10327 + assign $2\r_busy$next[0:0]$10260 $1\r_busy$next[0:0]$10259 end sync always - update \r_busy$next $0\r_busy$next[0:0]$10326 + update \r_busy$next $0\r_busy$next[0:0]$10258 end - attribute \src "libresoc.v:175214.3-175226.6" - process $proc$libresoc.v:175214$10329 + attribute \src "libresoc.v:175982.3-175994.6" + process $proc$libresoc.v:175982$10261 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$10330 $1\muxid$next[1:0]$10331 - attribute \src "libresoc.v:175215.5-175215.29" + assign $0\muxid$next[1:0]$10262 $1\muxid$next[1:0]$10263 + attribute \src "libresoc.v:175983.5-175983.29" switch \initial - attribute \src "libresoc.v:175215.9-175215.17" + attribute \src "libresoc.v:175983.9-175983.17" case 1'1 case end @@ -358808,19 +325351,19 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$10331 \muxid$68 + assign $1\muxid$next[1:0]$10263 \muxid$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$10331 \muxid$68 + assign $1\muxid$next[1:0]$10263 \muxid$68 case - assign $1\muxid$next[1:0]$10331 \muxid + assign $1\muxid$next[1:0]$10263 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$10330 + update \muxid$next $0\muxid$next[1:0]$10262 end - attribute \src "libresoc.v:175227.3-175268.6" - process $proc$libresoc.v:175227$10332 + attribute \src "libresoc.v:175995.3-176036.6" + process $proc$libresoc.v:175995$10264 assign { } { } assign { } { } assign { } { } @@ -358857,33 +325400,33 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$next[3:0]$10333 $1\logical_op__data_len$next[3:0]$10351 - assign $0\logical_op__fn_unit$next[13:0]$10334 $1\logical_op__fn_unit$next[13:0]$10352 + assign $0\logical_op__data_len$next[3:0]$10265 $1\logical_op__data_len$next[3:0]$10283 + assign $0\logical_op__fn_unit$next[13:0]$10266 $1\logical_op__fn_unit$next[13:0]$10284 assign { } { } assign { } { } - assign $0\logical_op__input_carry$next[1:0]$10337 $1\logical_op__input_carry$next[1:0]$10355 - assign $0\logical_op__insn$next[31:0]$10338 $1\logical_op__insn$next[31:0]$10356 - assign $0\logical_op__insn_type$next[6:0]$10339 $1\logical_op__insn_type$next[6:0]$10357 - assign $0\logical_op__invert_in$next[0:0]$10340 $1\logical_op__invert_in$next[0:0]$10358 - assign $0\logical_op__invert_out$next[0:0]$10341 $1\logical_op__invert_out$next[0:0]$10359 - assign $0\logical_op__is_32bit$next[0:0]$10342 $1\logical_op__is_32bit$next[0:0]$10360 - assign $0\logical_op__is_signed$next[0:0]$10343 $1\logical_op__is_signed$next[0:0]$10361 + assign $0\logical_op__input_carry$next[1:0]$10269 $1\logical_op__input_carry$next[1:0]$10287 + assign $0\logical_op__insn$next[31:0]$10270 $1\logical_op__insn$next[31:0]$10288 + assign $0\logical_op__insn_type$next[6:0]$10271 $1\logical_op__insn_type$next[6:0]$10289 + assign $0\logical_op__invert_in$next[0:0]$10272 $1\logical_op__invert_in$next[0:0]$10290 + assign $0\logical_op__invert_out$next[0:0]$10273 $1\logical_op__invert_out$next[0:0]$10291 + assign $0\logical_op__is_32bit$next[0:0]$10274 $1\logical_op__is_32bit$next[0:0]$10292 + assign $0\logical_op__is_signed$next[0:0]$10275 $1\logical_op__is_signed$next[0:0]$10293 assign { } { } assign { } { } - assign $0\logical_op__output_carry$next[0:0]$10346 $1\logical_op__output_carry$next[0:0]$10364 + assign $0\logical_op__output_carry$next[0:0]$10278 $1\logical_op__output_carry$next[0:0]$10296 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$10349 $1\logical_op__write_cr0$next[0:0]$10367 - assign $0\logical_op__zero_a$next[0:0]$10350 $1\logical_op__zero_a$next[0:0]$10368 - assign $0\logical_op__imm_data__data$next[63:0]$10335 $2\logical_op__imm_data__data$next[63:0]$10369 - assign $0\logical_op__imm_data__ok$next[0:0]$10336 $2\logical_op__imm_data__ok$next[0:0]$10370 - assign $0\logical_op__oe__oe$next[0:0]$10344 $2\logical_op__oe__oe$next[0:0]$10371 - assign $0\logical_op__oe__ok$next[0:0]$10345 $2\logical_op__oe__ok$next[0:0]$10372 - assign $0\logical_op__rc__ok$next[0:0]$10347 $2\logical_op__rc__ok$next[0:0]$10373 - assign $0\logical_op__rc__rc$next[0:0]$10348 $2\logical_op__rc__rc$next[0:0]$10374 - attribute \src "libresoc.v:175228.5-175228.29" + assign $0\logical_op__write_cr0$next[0:0]$10281 $1\logical_op__write_cr0$next[0:0]$10299 + assign $0\logical_op__zero_a$next[0:0]$10282 $1\logical_op__zero_a$next[0:0]$10300 + assign $0\logical_op__imm_data__data$next[63:0]$10267 $2\logical_op__imm_data__data$next[63:0]$10301 + assign $0\logical_op__imm_data__ok$next[0:0]$10268 $2\logical_op__imm_data__ok$next[0:0]$10302 + assign $0\logical_op__oe__oe$next[0:0]$10276 $2\logical_op__oe__oe$next[0:0]$10303 + assign $0\logical_op__oe__ok$next[0:0]$10277 $2\logical_op__oe__ok$next[0:0]$10304 + assign $0\logical_op__rc__ok$next[0:0]$10279 $2\logical_op__rc__ok$next[0:0]$10305 + assign $0\logical_op__rc__rc$next[0:0]$10280 $2\logical_op__rc__rc$next[0:0]$10306 + attribute \src "libresoc.v:175996.5-175996.29" switch \initial - attribute \src "libresoc.v:175228.9-175228.17" + attribute \src "libresoc.v:175996.9-175996.17" case 1'1 case end @@ -358909,7 +325452,7 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$10356 $1\logical_op__data_len$next[3:0]$10351 $1\logical_op__is_signed$next[0:0]$10361 $1\logical_op__is_32bit$next[0:0]$10360 $1\logical_op__output_carry$next[0:0]$10364 $1\logical_op__write_cr0$next[0:0]$10367 $1\logical_op__invert_out$next[0:0]$10359 $1\logical_op__input_carry$next[1:0]$10355 $1\logical_op__zero_a$next[0:0]$10368 $1\logical_op__invert_in$next[0:0]$10358 $1\logical_op__oe__ok$next[0:0]$10363 $1\logical_op__oe__oe$next[0:0]$10362 $1\logical_op__rc__ok$next[0:0]$10365 $1\logical_op__rc__rc$next[0:0]$10366 $1\logical_op__imm_data__ok$next[0:0]$10354 $1\logical_op__imm_data__data$next[63:0]$10353 $1\logical_op__fn_unit$next[13:0]$10352 $1\logical_op__insn_type$next[6:0]$10357 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign { $1\logical_op__insn$next[31:0]$10288 $1\logical_op__data_len$next[3:0]$10283 $1\logical_op__is_signed$next[0:0]$10293 $1\logical_op__is_32bit$next[0:0]$10292 $1\logical_op__output_carry$next[0:0]$10296 $1\logical_op__write_cr0$next[0:0]$10299 $1\logical_op__invert_out$next[0:0]$10291 $1\logical_op__input_carry$next[1:0]$10287 $1\logical_op__zero_a$next[0:0]$10300 $1\logical_op__invert_in$next[0:0]$10290 $1\logical_op__oe__ok$next[0:0]$10295 $1\logical_op__oe__oe$next[0:0]$10294 $1\logical_op__rc__ok$next[0:0]$10297 $1\logical_op__rc__rc$next[0:0]$10298 $1\logical_op__imm_data__ok$next[0:0]$10286 $1\logical_op__imm_data__data$next[63:0]$10285 $1\logical_op__fn_unit$next[13:0]$10284 $1\logical_op__insn_type$next[6:0]$10289 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -358930,26 +325473,26 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$10356 $1\logical_op__data_len$next[3:0]$10351 $1\logical_op__is_signed$next[0:0]$10361 $1\logical_op__is_32bit$next[0:0]$10360 $1\logical_op__output_carry$next[0:0]$10364 $1\logical_op__write_cr0$next[0:0]$10367 $1\logical_op__invert_out$next[0:0]$10359 $1\logical_op__input_carry$next[1:0]$10355 $1\logical_op__zero_a$next[0:0]$10368 $1\logical_op__invert_in$next[0:0]$10358 $1\logical_op__oe__ok$next[0:0]$10363 $1\logical_op__oe__oe$next[0:0]$10362 $1\logical_op__rc__ok$next[0:0]$10365 $1\logical_op__rc__rc$next[0:0]$10366 $1\logical_op__imm_data__ok$next[0:0]$10354 $1\logical_op__imm_data__data$next[63:0]$10353 $1\logical_op__fn_unit$next[13:0]$10352 $1\logical_op__insn_type$next[6:0]$10357 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign { $1\logical_op__insn$next[31:0]$10288 $1\logical_op__data_len$next[3:0]$10283 $1\logical_op__is_signed$next[0:0]$10293 $1\logical_op__is_32bit$next[0:0]$10292 $1\logical_op__output_carry$next[0:0]$10296 $1\logical_op__write_cr0$next[0:0]$10299 $1\logical_op__invert_out$next[0:0]$10291 $1\logical_op__input_carry$next[1:0]$10287 $1\logical_op__zero_a$next[0:0]$10300 $1\logical_op__invert_in$next[0:0]$10290 $1\logical_op__oe__ok$next[0:0]$10295 $1\logical_op__oe__oe$next[0:0]$10294 $1\logical_op__rc__ok$next[0:0]$10297 $1\logical_op__rc__rc$next[0:0]$10298 $1\logical_op__imm_data__ok$next[0:0]$10286 $1\logical_op__imm_data__data$next[63:0]$10285 $1\logical_op__fn_unit$next[13:0]$10284 $1\logical_op__insn_type$next[6:0]$10289 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } case - assign $1\logical_op__data_len$next[3:0]$10351 \logical_op__data_len - assign $1\logical_op__fn_unit$next[13:0]$10352 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$10353 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$10354 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$10355 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$10356 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$10357 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$10358 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$10359 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$10360 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$10361 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$10362 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$10363 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$10364 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$10365 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$10366 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$10367 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$10368 \logical_op__zero_a + assign $1\logical_op__data_len$next[3:0]$10283 \logical_op__data_len + assign $1\logical_op__fn_unit$next[13:0]$10284 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$10285 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$10286 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$10287 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$10288 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$10289 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$10290 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$10291 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$10292 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$10293 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$10294 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$10295 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$10296 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$10297 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$10298 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$10299 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$10300 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -358961,48 +325504,48 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$10369 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$10370 1'0 - assign $2\logical_op__rc__rc$next[0:0]$10374 1'0 - assign $2\logical_op__rc__ok$next[0:0]$10373 1'0 - assign $2\logical_op__oe__oe$next[0:0]$10371 1'0 - assign $2\logical_op__oe__ok$next[0:0]$10372 1'0 + assign $2\logical_op__imm_data__data$next[63:0]$10301 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$10302 1'0 + assign $2\logical_op__rc__rc$next[0:0]$10306 1'0 + assign $2\logical_op__rc__ok$next[0:0]$10305 1'0 + assign $2\logical_op__oe__oe$next[0:0]$10303 1'0 + assign $2\logical_op__oe__ok$next[0:0]$10304 1'0 case - assign $2\logical_op__imm_data__data$next[63:0]$10369 $1\logical_op__imm_data__data$next[63:0]$10353 - assign $2\logical_op__imm_data__ok$next[0:0]$10370 $1\logical_op__imm_data__ok$next[0:0]$10354 - assign $2\logical_op__oe__oe$next[0:0]$10371 $1\logical_op__oe__oe$next[0:0]$10362 - assign $2\logical_op__oe__ok$next[0:0]$10372 $1\logical_op__oe__ok$next[0:0]$10363 - assign $2\logical_op__rc__ok$next[0:0]$10373 $1\logical_op__rc__ok$next[0:0]$10365 - assign $2\logical_op__rc__rc$next[0:0]$10374 $1\logical_op__rc__rc$next[0:0]$10366 + assign $2\logical_op__imm_data__data$next[63:0]$10301 $1\logical_op__imm_data__data$next[63:0]$10285 + assign $2\logical_op__imm_data__ok$next[0:0]$10302 $1\logical_op__imm_data__ok$next[0:0]$10286 + assign $2\logical_op__oe__oe$next[0:0]$10303 $1\logical_op__oe__oe$next[0:0]$10294 + assign $2\logical_op__oe__ok$next[0:0]$10304 $1\logical_op__oe__ok$next[0:0]$10295 + assign $2\logical_op__rc__ok$next[0:0]$10305 $1\logical_op__rc__ok$next[0:0]$10297 + assign $2\logical_op__rc__rc$next[0:0]$10306 $1\logical_op__rc__rc$next[0:0]$10298 end sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10333 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$10334 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10335 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10336 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10337 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10338 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10339 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10340 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10341 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10342 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10343 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10344 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10345 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10346 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10347 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10348 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10349 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10350 + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10265 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$10266 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10267 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10268 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10269 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10270 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10271 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10272 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10273 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10274 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10275 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10276 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10277 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10278 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10279 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10280 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10281 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10282 end - attribute \src "libresoc.v:175269.3-175281.6" - process $proc$libresoc.v:175269$10375 + attribute \src "libresoc.v:176037.3-176049.6" + process $proc$libresoc.v:176037$10307 assign { } { } assign { } { } - assign $0\ra$next[63:0]$10376 $1\ra$next[63:0]$10377 - attribute \src "libresoc.v:175270.5-175270.29" + assign $0\ra$next[63:0]$10308 $1\ra$next[63:0]$10309 + attribute \src "libresoc.v:176038.5-176038.29" switch \initial - attribute \src "libresoc.v:175270.9-175270.17" + attribute \src "libresoc.v:176038.9-176038.17" case 1'1 case end @@ -359011,25 +325554,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$10377 \ra$87 + assign $1\ra$next[63:0]$10309 \ra$87 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$10377 \ra$87 + assign $1\ra$next[63:0]$10309 \ra$87 case - assign $1\ra$next[63:0]$10377 \ra + assign $1\ra$next[63:0]$10309 \ra end sync always - update \ra$next $0\ra$next[63:0]$10376 + update \ra$next $0\ra$next[63:0]$10308 end - attribute \src "libresoc.v:175282.3-175294.6" - process $proc$libresoc.v:175282$10378 + attribute \src "libresoc.v:176050.3-176062.6" + process $proc$libresoc.v:176050$10310 assign { } { } assign { } { } - assign $0\rb$next[63:0]$10379 $1\rb$next[63:0]$10380 - attribute \src "libresoc.v:175283.5-175283.29" + assign $0\rb$next[63:0]$10311 $1\rb$next[63:0]$10312 + attribute \src "libresoc.v:176051.5-176051.29" switch \initial - attribute \src "libresoc.v:175283.9-175283.17" + attribute \src "libresoc.v:176051.9-176051.17" case 1'1 case end @@ -359038,25 +325581,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$10380 \rb$89 + assign $1\rb$next[63:0]$10312 \rb$89 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$10380 \rb$89 + assign $1\rb$next[63:0]$10312 \rb$89 case - assign $1\rb$next[63:0]$10380 \rb + assign $1\rb$next[63:0]$10312 \rb end sync always - update \rb$next $0\rb$next[63:0]$10379 + update \rb$next $0\rb$next[63:0]$10311 end - attribute \src "libresoc.v:175295.3-175307.6" - process $proc$libresoc.v:175295$10381 + attribute \src "libresoc.v:176063.3-176075.6" + process $proc$libresoc.v:176063$10313 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$10382 $1\xer_so$next[0:0]$10383 - attribute \src "libresoc.v:175296.5-175296.29" + assign $0\xer_so$next[0:0]$10314 $1\xer_so$next[0:0]$10315 + attribute \src "libresoc.v:176064.5-176064.29" switch \initial - attribute \src "libresoc.v:175296.9-175296.17" + attribute \src "libresoc.v:176064.9-176064.17" case 1'1 case end @@ -359065,18 +325608,18 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$next[0:0]$10383 \xer_so$91 + assign $1\xer_so$next[0:0]$10315 \xer_so$91 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$next[0:0]$10383 \xer_so$91 + assign $1\xer_so$next[0:0]$10315 \xer_so$91 case - assign $1\xer_so$next[0:0]$10383 \xer_so + assign $1\xer_so$next[0:0]$10315 \xer_so end sync always - update \xer_so$next $0\xer_so$next[0:0]$10382 + update \xer_so$next $0\xer_so$next[0:0]$10314 end - connect \$66 $and$libresoc.v:174923$10269_Y + connect \$66 $and$libresoc.v:175691$10201_Y connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 connect \p_ready_o \n_i_rdy_data @@ -359108,27 +325651,27 @@ module \pipe_start connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:175342.1-175386.10" +attribute \src "libresoc.v:176110.1-176154.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.pll" attribute \generator "nMigen" module \pll - attribute \src "libresoc.v:175343.7-175343.20" + attribute \src "libresoc.v:176111.7-176111.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175375.3-175384.6" + attribute \src "libresoc.v:176143.3-176152.6" wire $0\pll_18_o[0:0] - attribute \src "libresoc.v:175365.3-175374.6" + attribute \src "libresoc.v:176133.3-176142.6" wire $0\pll_lck_o[0:0] - attribute \src "libresoc.v:175375.3-175384.6" + attribute \src "libresoc.v:176143.3-176152.6" wire $1\pll_18_o[0:0] - attribute \src "libresoc.v:175365.3-175374.6" + attribute \src "libresoc.v:176133.3-176142.6" wire $1\pll_lck_o[0:0] - attribute \src "libresoc.v:175362.17-175362.105" - wire $eq$libresoc.v:175362$10416_Y - attribute \src "libresoc.v:175363.17-175363.105" - wire $eq$libresoc.v:175363$10417_Y - attribute \src "libresoc.v:175364.17-175364.98" - wire $not$libresoc.v:175364$10418_Y + attribute \src "libresoc.v:176130.17-176130.105" + wire $eq$libresoc.v:176130$10348_Y + attribute \src "libresoc.v:176131.17-176131.105" + wire $eq$libresoc.v:176131$10349_Y + attribute \src "libresoc.v:176132.17-176132.98" + wire $not$libresoc.v:176132$10350_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" @@ -359141,14 +325684,14 @@ module \pll wire output 5 \clk_pll_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" wire width 2 input 3 \clk_sel_i - attribute \src "libresoc.v:175343.7-175343.15" + attribute \src "libresoc.v:176111.7-176111.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" wire output 2 \pll_18_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" wire output 4 \pll_lck_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:175362$10416 + cell $eq $eq$libresoc.v:176130$10348 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -359156,10 +325699,10 @@ module \pll parameter \Y_WIDTH 1 connect \A \clk_sel_i connect \B 2'00 - connect \Y $eq$libresoc.v:175362$10416_Y + connect \Y $eq$libresoc.v:176130$10348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:175363$10417 + cell $eq $eq$libresoc.v:176131$10349 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -359167,32 +325710,32 @@ module \pll parameter \Y_WIDTH 1 connect \A \clk_sel_i connect \B 2'00 - connect \Y $eq$libresoc.v:175363$10417_Y + connect \Y $eq$libresoc.v:176131$10349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" - cell $not $not$libresoc.v:175364$10418 + cell $not $not$libresoc.v:176132$10350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clk_24_i - connect \Y $not$libresoc.v:175364$10418_Y + connect \Y $not$libresoc.v:176132$10350_Y end - attribute \src "libresoc.v:175343.7-175343.20" - process $proc$libresoc.v:175343$10421 + attribute \src "libresoc.v:176111.7-176111.20" + process $proc$libresoc.v:176111$10353 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175365.3-175374.6" - process $proc$libresoc.v:175365$10419 + attribute \src "libresoc.v:176133.3-176142.6" + process $proc$libresoc.v:176133$10351 assign { } { } assign { } { } assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] - attribute \src "libresoc.v:175366.5-175366.29" + attribute \src "libresoc.v:176134.5-176134.29" switch \initial - attribute \src "libresoc.v:175366.9-175366.17" + attribute \src "libresoc.v:176134.9-176134.17" case 1'1 case end @@ -359208,14 +325751,14 @@ module \pll sync always update \pll_lck_o $0\pll_lck_o[0:0] end - attribute \src "libresoc.v:175375.3-175384.6" - process $proc$libresoc.v:175375$10420 + attribute \src "libresoc.v:176143.3-176152.6" + process $proc$libresoc.v:176143$10352 assign { } { } assign { } { } assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] - attribute \src "libresoc.v:175376.5-175376.29" + attribute \src "libresoc.v:176144.5-176144.29" switch \initial - attribute \src "libresoc.v:175376.9-175376.17" + attribute \src "libresoc.v:176144.9-176144.17" case 1'1 case end @@ -359231,196 +325774,196 @@ module \pll sync always update \pll_18_o $0\pll_18_o[0:0] end - connect \$1 $eq$libresoc.v:175362$10416_Y - connect \$3 $eq$libresoc.v:175363$10417_Y - connect \$5 $not$libresoc.v:175364$10418_Y + connect \$1 $eq$libresoc.v:176130$10348_Y + connect \$3 $eq$libresoc.v:176131$10349_Y + connect \$5 $not$libresoc.v:176132$10350_Y connect \clk_pll_o \clk_24_i end -attribute \src "libresoc.v:175390.1-176032.10" +attribute \src "libresoc.v:176158.1-176800.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" attribute \generator "nMigen" module \popcount - attribute \src "libresoc.v:175391.7-175391.20" + attribute \src "libresoc.v:176159.7-176159.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175879.3-175905.6" + attribute \src "libresoc.v:176647.3-176673.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:175879.3-175905.6" + attribute \src "libresoc.v:176647.3-176673.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:175803.19-175803.132" - wire width 4 $add$libresoc.v:175803$10422_Y - attribute \src "libresoc.v:175804.19-175804.132" - wire width 4 $add$libresoc.v:175804$10423_Y - attribute \src "libresoc.v:175805.19-175805.132" - wire width 4 $add$libresoc.v:175805$10424_Y - attribute \src "libresoc.v:175806.19-175806.132" - wire width 4 $add$libresoc.v:175806$10425_Y - attribute \src "libresoc.v:175807.19-175807.134" - wire width 4 $add$libresoc.v:175807$10426_Y - attribute \src "libresoc.v:175808.19-175808.134" - wire width 4 $add$libresoc.v:175808$10427_Y - attribute \src "libresoc.v:175809.18-175809.125" - wire width 3 $add$libresoc.v:175809$10428_Y - attribute \src "libresoc.v:175810.19-175810.134" - wire width 4 $add$libresoc.v:175810$10429_Y - attribute \src "libresoc.v:175811.19-175811.134" - wire width 4 $add$libresoc.v:175811$10430_Y - attribute \src "libresoc.v:175812.19-175812.134" - wire width 4 $add$libresoc.v:175812$10431_Y - attribute \src "libresoc.v:175813.19-175813.134" - wire width 4 $add$libresoc.v:175813$10432_Y - attribute \src "libresoc.v:175814.19-175814.134" - wire width 4 $add$libresoc.v:175814$10433_Y - attribute \src "libresoc.v:175815.19-175815.134" - wire width 4 $add$libresoc.v:175815$10434_Y - attribute \src "libresoc.v:175816.19-175816.134" - wire width 4 $add$libresoc.v:175816$10435_Y - attribute \src "libresoc.v:175817.19-175817.134" - wire width 4 $add$libresoc.v:175817$10436_Y - attribute \src "libresoc.v:175818.19-175818.134" - wire width 4 $add$libresoc.v:175818$10437_Y - attribute \src "libresoc.v:175819.19-175819.132" - wire width 5 $add$libresoc.v:175819$10438_Y - attribute \src "libresoc.v:175820.18-175820.125" - wire width 3 $add$libresoc.v:175820$10439_Y - attribute \src "libresoc.v:175821.19-175821.132" - wire width 5 $add$libresoc.v:175821$10440_Y - attribute \src "libresoc.v:175822.19-175822.132" - wire width 5 $add$libresoc.v:175822$10441_Y - attribute \src "libresoc.v:175823.19-175823.132" - wire width 5 $add$libresoc.v:175823$10442_Y - attribute \src "libresoc.v:175824.19-175824.132" - wire width 5 $add$libresoc.v:175824$10443_Y - attribute \src "libresoc.v:175825.19-175825.134" - wire width 5 $add$libresoc.v:175825$10444_Y - attribute \src "libresoc.v:175826.19-175826.134" - wire width 5 $add$libresoc.v:175826$10445_Y - attribute \src "libresoc.v:175827.19-175827.134" - wire width 5 $add$libresoc.v:175827$10446_Y - attribute \src "libresoc.v:175828.19-175828.132" - wire width 6 $add$libresoc.v:175828$10447_Y - attribute \src "libresoc.v:175829.19-175829.132" - wire width 6 $add$libresoc.v:175829$10448_Y - attribute \src "libresoc.v:175830.19-175830.132" - wire width 6 $add$libresoc.v:175830$10449_Y - attribute \src "libresoc.v:175831.18-175831.127" - wire width 3 $add$libresoc.v:175831$10450_Y - attribute \src "libresoc.v:175832.19-175832.132" - wire width 6 $add$libresoc.v:175832$10451_Y - attribute \src "libresoc.v:175833.19-175833.132" - wire width 7 $add$libresoc.v:175833$10452_Y - attribute \src "libresoc.v:175834.19-175834.132" - wire width 7 $add$libresoc.v:175834$10453_Y - attribute \src "libresoc.v:175835.19-175835.132" - wire width 8 $add$libresoc.v:175835$10454_Y - attribute \src "libresoc.v:175846.18-175846.127" - wire width 3 $add$libresoc.v:175846$10473_Y - attribute \src "libresoc.v:175850.18-175850.127" - wire width 3 $add$libresoc.v:175850$10480_Y - attribute \src "libresoc.v:175851.18-175851.127" - wire width 3 $add$libresoc.v:175851$10481_Y - attribute \src "libresoc.v:175852.17-175852.124" - wire width 3 $add$libresoc.v:175852$10482_Y - attribute \src "libresoc.v:175853.18-175853.127" - wire width 3 $add$libresoc.v:175853$10483_Y - attribute \src "libresoc.v:175854.18-175854.127" - wire width 3 $add$libresoc.v:175854$10484_Y - attribute \src "libresoc.v:175855.18-175855.127" - wire width 3 $add$libresoc.v:175855$10485_Y - attribute \src "libresoc.v:175856.18-175856.127" - wire width 3 $add$libresoc.v:175856$10486_Y - attribute \src "libresoc.v:175857.18-175857.127" - wire width 3 $add$libresoc.v:175857$10487_Y - attribute \src "libresoc.v:175858.18-175858.127" - wire width 3 $add$libresoc.v:175858$10488_Y - attribute \src "libresoc.v:175859.18-175859.127" - wire width 3 $add$libresoc.v:175859$10489_Y - attribute \src "libresoc.v:175860.18-175860.127" - wire width 3 $add$libresoc.v:175860$10490_Y - attribute \src "libresoc.v:175861.18-175861.127" - wire width 3 $add$libresoc.v:175861$10491_Y - attribute \src "libresoc.v:175862.18-175862.127" - wire width 3 $add$libresoc.v:175862$10492_Y - attribute \src "libresoc.v:175863.17-175863.124" - wire width 3 $add$libresoc.v:175863$10493_Y - attribute \src "libresoc.v:175864.18-175864.127" - wire width 3 $add$libresoc.v:175864$10494_Y - attribute \src "libresoc.v:175865.18-175865.127" - wire width 3 $add$libresoc.v:175865$10495_Y - attribute \src "libresoc.v:175866.18-175866.127" - wire width 3 $add$libresoc.v:175866$10496_Y - attribute \src "libresoc.v:175867.18-175867.127" - wire width 3 $add$libresoc.v:175867$10497_Y - attribute \src "libresoc.v:175868.18-175868.127" - wire width 3 $add$libresoc.v:175868$10498_Y - attribute \src "libresoc.v:175869.18-175869.127" - wire width 3 $add$libresoc.v:175869$10499_Y - attribute \src "libresoc.v:175870.18-175870.127" - wire width 3 $add$libresoc.v:175870$10500_Y - attribute \src "libresoc.v:175871.18-175871.127" - wire width 3 $add$libresoc.v:175871$10501_Y - attribute \src "libresoc.v:175872.18-175872.127" - wire width 3 $add$libresoc.v:175872$10502_Y - attribute \src "libresoc.v:175873.18-175873.127" - wire width 3 $add$libresoc.v:175873$10503_Y - attribute \src "libresoc.v:175874.17-175874.124" - wire width 3 $add$libresoc.v:175874$10504_Y - attribute \src "libresoc.v:175875.18-175875.127" - wire width 3 $add$libresoc.v:175875$10505_Y - attribute \src "libresoc.v:175876.18-175876.127" - wire width 3 $add$libresoc.v:175876$10506_Y - attribute \src "libresoc.v:175877.18-175877.127" - wire width 3 $add$libresoc.v:175877$10507_Y - attribute \src "libresoc.v:175878.18-175878.131" - wire width 4 $add$libresoc.v:175878$10508_Y - attribute \src "libresoc.v:175836.19-175836.111" - wire $eq$libresoc.v:175836$10455_Y - attribute \src "libresoc.v:175837.19-175837.111" - wire $eq$libresoc.v:175837$10456_Y - attribute \src "libresoc.v:175838.19-175838.104" - wire width 8 $extend$libresoc.v:175838$10457_Y - attribute \src "libresoc.v:175839.19-175839.104" - wire width 8 $extend$libresoc.v:175839$10459_Y - attribute \src "libresoc.v:175840.19-175840.104" - wire width 8 $extend$libresoc.v:175840$10461_Y - attribute \src "libresoc.v:175841.19-175841.104" - wire width 8 $extend$libresoc.v:175841$10463_Y - attribute \src "libresoc.v:175842.19-175842.104" - wire width 8 $extend$libresoc.v:175842$10465_Y - attribute \src "libresoc.v:175843.19-175843.104" - wire width 8 $extend$libresoc.v:175843$10467_Y - attribute \src "libresoc.v:175844.19-175844.104" - wire width 8 $extend$libresoc.v:175844$10469_Y - attribute \src "libresoc.v:175845.19-175845.104" - wire width 8 $extend$libresoc.v:175845$10471_Y - attribute \src "libresoc.v:175847.19-175847.104" - wire width 32 $extend$libresoc.v:175847$10474_Y - attribute \src "libresoc.v:175848.19-175848.104" - wire width 32 $extend$libresoc.v:175848$10476_Y - attribute \src "libresoc.v:175849.19-175849.104" - wire width 64 $extend$libresoc.v:175849$10478_Y - attribute \src "libresoc.v:175838.19-175838.104" - wire width 8 $pos$libresoc.v:175838$10458_Y - attribute \src "libresoc.v:175839.19-175839.104" - wire width 8 $pos$libresoc.v:175839$10460_Y - attribute \src "libresoc.v:175840.19-175840.104" - wire width 8 $pos$libresoc.v:175840$10462_Y - attribute \src "libresoc.v:175841.19-175841.104" - wire width 8 $pos$libresoc.v:175841$10464_Y - attribute \src "libresoc.v:175842.19-175842.104" - wire width 8 $pos$libresoc.v:175842$10466_Y - attribute \src "libresoc.v:175843.19-175843.104" - wire width 8 $pos$libresoc.v:175843$10468_Y - attribute \src "libresoc.v:175844.19-175844.104" - wire width 8 $pos$libresoc.v:175844$10470_Y - attribute \src "libresoc.v:175845.19-175845.104" - wire width 8 $pos$libresoc.v:175845$10472_Y - attribute \src "libresoc.v:175847.19-175847.104" - wire width 32 $pos$libresoc.v:175847$10475_Y - attribute \src "libresoc.v:175848.19-175848.104" - wire width 32 $pos$libresoc.v:175848$10477_Y - attribute \src "libresoc.v:175849.19-175849.104" - wire width 64 $pos$libresoc.v:175849$10479_Y + attribute \src "libresoc.v:176571.19-176571.132" + wire width 4 $add$libresoc.v:176571$10354_Y + attribute \src "libresoc.v:176572.19-176572.132" + wire width 4 $add$libresoc.v:176572$10355_Y + attribute \src "libresoc.v:176573.19-176573.132" + wire width 4 $add$libresoc.v:176573$10356_Y + attribute \src "libresoc.v:176574.19-176574.132" + wire width 4 $add$libresoc.v:176574$10357_Y + attribute \src "libresoc.v:176575.19-176575.134" + wire width 4 $add$libresoc.v:176575$10358_Y + attribute \src "libresoc.v:176576.19-176576.134" + wire width 4 $add$libresoc.v:176576$10359_Y + attribute \src "libresoc.v:176577.18-176577.125" + wire width 3 $add$libresoc.v:176577$10360_Y + attribute \src "libresoc.v:176578.19-176578.134" + wire width 4 $add$libresoc.v:176578$10361_Y + attribute \src "libresoc.v:176579.19-176579.134" + wire width 4 $add$libresoc.v:176579$10362_Y + attribute \src "libresoc.v:176580.19-176580.134" + wire width 4 $add$libresoc.v:176580$10363_Y + attribute \src "libresoc.v:176581.19-176581.134" + wire width 4 $add$libresoc.v:176581$10364_Y + attribute \src "libresoc.v:176582.19-176582.134" + wire width 4 $add$libresoc.v:176582$10365_Y + attribute \src "libresoc.v:176583.19-176583.134" + wire width 4 $add$libresoc.v:176583$10366_Y + attribute \src "libresoc.v:176584.19-176584.134" + wire width 4 $add$libresoc.v:176584$10367_Y + attribute \src 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"libresoc.v:176628.18-176628.127" + wire width 3 $add$libresoc.v:176628$10422_Y + attribute \src "libresoc.v:176629.18-176629.127" + wire width 3 $add$libresoc.v:176629$10423_Y + attribute \src "libresoc.v:176630.18-176630.127" + wire width 3 $add$libresoc.v:176630$10424_Y + attribute \src "libresoc.v:176631.17-176631.124" + wire width 3 $add$libresoc.v:176631$10425_Y + attribute \src "libresoc.v:176632.18-176632.127" + wire width 3 $add$libresoc.v:176632$10426_Y + attribute \src "libresoc.v:176633.18-176633.127" + wire width 3 $add$libresoc.v:176633$10427_Y + attribute \src "libresoc.v:176634.18-176634.127" + wire width 3 $add$libresoc.v:176634$10428_Y + attribute \src "libresoc.v:176635.18-176635.127" + wire width 3 $add$libresoc.v:176635$10429_Y + attribute \src "libresoc.v:176636.18-176636.127" + wire width 3 $add$libresoc.v:176636$10430_Y + attribute \src "libresoc.v:176637.18-176637.127" + wire width 3 $add$libresoc.v:176637$10431_Y + attribute \src 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wire $eq$libresoc.v:176605$10388_Y + attribute \src "libresoc.v:176606.19-176606.104" + wire width 8 $extend$libresoc.v:176606$10389_Y + attribute \src "libresoc.v:176607.19-176607.104" + wire width 8 $extend$libresoc.v:176607$10391_Y + attribute \src "libresoc.v:176608.19-176608.104" + wire width 8 $extend$libresoc.v:176608$10393_Y + attribute \src "libresoc.v:176609.19-176609.104" + wire width 8 $extend$libresoc.v:176609$10395_Y + attribute \src "libresoc.v:176610.19-176610.104" + wire width 8 $extend$libresoc.v:176610$10397_Y + attribute \src "libresoc.v:176611.19-176611.104" + wire width 8 $extend$libresoc.v:176611$10399_Y + attribute \src "libresoc.v:176612.19-176612.104" + wire width 8 $extend$libresoc.v:176612$10401_Y + attribute \src "libresoc.v:176613.19-176613.104" + wire width 8 $extend$libresoc.v:176613$10403_Y + attribute \src "libresoc.v:176615.19-176615.104" + wire width 32 $extend$libresoc.v:176615$10406_Y + attribute \src "libresoc.v:176616.19-176616.104" + wire width 32 $extend$libresoc.v:176616$10408_Y + attribute \src "libresoc.v:176617.19-176617.104" + wire width 64 $extend$libresoc.v:176617$10410_Y + attribute \src "libresoc.v:176606.19-176606.104" + wire width 8 $pos$libresoc.v:176606$10390_Y + attribute \src "libresoc.v:176607.19-176607.104" + wire width 8 $pos$libresoc.v:176607$10392_Y + attribute \src "libresoc.v:176608.19-176608.104" + wire width 8 $pos$libresoc.v:176608$10394_Y + attribute \src "libresoc.v:176609.19-176609.104" + wire width 8 $pos$libresoc.v:176609$10396_Y + attribute \src "libresoc.v:176610.19-176610.104" + wire width 8 $pos$libresoc.v:176610$10398_Y + attribute \src "libresoc.v:176611.19-176611.104" + wire width 8 $pos$libresoc.v:176611$10400_Y + attribute \src "libresoc.v:176612.19-176612.104" + wire width 8 $pos$libresoc.v:176612$10402_Y + attribute \src "libresoc.v:176613.19-176613.104" + wire width 8 $pos$libresoc.v:176613$10404_Y + attribute \src "libresoc.v:176615.19-176615.104" + wire width 32 $pos$libresoc.v:176615$10407_Y + attribute \src "libresoc.v:176616.19-176616.104" + wire width 32 $pos$libresoc.v:176616$10409_Y + attribute \src "libresoc.v:176617.19-176617.104" + wire width 64 $pos$libresoc.v:176617$10411_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" @@ -359703,7 +326246,7 @@ module \popcount wire width 64 input 3 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" wire width 64 input 1 \data_len - attribute \src "libresoc.v:175391.7-175391.15" + attribute \src "libresoc.v:176159.7-176159.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" wire width 64 output 2 \o @@ -359834,7 +326377,7 @@ module \popcount attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 7 \pop_7_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175803$10422 + cell $add $add$libresoc.v:176571$10354 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359842,10 +326385,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_2 } connect \B { 2'00 \pop_2_3 } - connect \Y $add$libresoc.v:175803$10422_Y + connect \Y $add$libresoc.v:176571$10354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175804$10423 + cell $add $add$libresoc.v:176572$10355 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359853,10 +326396,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_4 } connect \B { 2'00 \pop_2_5 } - connect \Y $add$libresoc.v:175804$10423_Y + connect \Y $add$libresoc.v:176572$10355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175805$10424 + cell $add $add$libresoc.v:176573$10356 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359864,10 +326407,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_6 } connect \B { 2'00 \pop_2_7 } - connect \Y $add$libresoc.v:175805$10424_Y + connect \Y $add$libresoc.v:176573$10356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175806$10425 + cell $add $add$libresoc.v:176574$10357 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359875,10 +326418,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_8 } connect \B { 2'00 \pop_2_9 } - connect \Y $add$libresoc.v:175806$10425_Y + connect \Y $add$libresoc.v:176574$10357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175807$10426 + cell $add $add$libresoc.v:176575$10358 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359886,10 +326429,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_10 } connect \B { 2'00 \pop_2_11 } - connect \Y $add$libresoc.v:175807$10426_Y + connect \Y $add$libresoc.v:176575$10358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175808$10427 + cell $add $add$libresoc.v:176576$10359 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359897,10 +326440,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_12 } connect \B { 2'00 \pop_2_13 } - connect \Y $add$libresoc.v:175808$10427_Y + connect \Y $add$libresoc.v:176576$10359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175809$10428 + cell $add $add$libresoc.v:176577$10360 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -359908,10 +326451,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [6] } connect \B { 2'00 \a [7] } - connect \Y $add$libresoc.v:175809$10428_Y + connect \Y $add$libresoc.v:176577$10360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175810$10429 + cell $add $add$libresoc.v:176578$10361 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359919,10 +326462,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_14 } connect \B { 2'00 \pop_2_15 } - connect \Y $add$libresoc.v:175810$10429_Y + connect \Y $add$libresoc.v:176578$10361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175811$10430 + cell $add $add$libresoc.v:176579$10362 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359930,10 +326473,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_16 } connect \B { 2'00 \pop_2_17 } - connect \Y $add$libresoc.v:175811$10430_Y + connect \Y $add$libresoc.v:176579$10362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175812$10431 + cell $add $add$libresoc.v:176580$10363 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359941,10 +326484,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_18 } connect \B { 2'00 \pop_2_19 } - connect \Y $add$libresoc.v:175812$10431_Y + connect \Y $add$libresoc.v:176580$10363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175813$10432 + cell $add $add$libresoc.v:176581$10364 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359952,10 +326495,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_20 } connect \B { 2'00 \pop_2_21 } - connect \Y $add$libresoc.v:175813$10432_Y + connect \Y $add$libresoc.v:176581$10364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175814$10433 + cell $add $add$libresoc.v:176582$10365 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359963,10 +326506,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_22 } connect \B { 2'00 \pop_2_23 } - connect \Y $add$libresoc.v:175814$10433_Y + connect \Y $add$libresoc.v:176582$10365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175815$10434 + cell $add $add$libresoc.v:176583$10366 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359974,10 +326517,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_24 } connect \B { 2'00 \pop_2_25 } - connect \Y $add$libresoc.v:175815$10434_Y + connect \Y $add$libresoc.v:176583$10366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175816$10435 + cell $add $add$libresoc.v:176584$10367 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359985,10 +326528,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_26 } connect \B { 2'00 \pop_2_27 } - connect \Y $add$libresoc.v:175816$10435_Y + connect \Y $add$libresoc.v:176584$10367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175817$10436 + cell $add $add$libresoc.v:176585$10368 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359996,10 +326539,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_28 } connect \B { 2'00 \pop_2_29 } - connect \Y $add$libresoc.v:175817$10436_Y + connect \Y $add$libresoc.v:176585$10368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175818$10437 + cell $add $add$libresoc.v:176586$10369 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -360007,10 +326550,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_30 } connect \B { 2'00 \pop_2_31 } - connect \Y $add$libresoc.v:175818$10437_Y + connect \Y $add$libresoc.v:176586$10369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175819$10438 + cell $add $add$libresoc.v:176587$10370 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360018,10 +326561,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_0 } connect \B { 2'00 \pop_3_1 } - connect \Y $add$libresoc.v:175819$10438_Y + connect \Y $add$libresoc.v:176587$10370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175820$10439 + cell $add $add$libresoc.v:176588$10371 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360029,10 +326572,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [8] } connect \B { 2'00 \a [9] } - connect \Y $add$libresoc.v:175820$10439_Y + connect \Y $add$libresoc.v:176588$10371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175821$10440 + cell $add $add$libresoc.v:176589$10372 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360040,10 +326583,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_2 } connect \B { 2'00 \pop_3_3 } - connect \Y $add$libresoc.v:175821$10440_Y + connect \Y $add$libresoc.v:176589$10372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175822$10441 + cell $add $add$libresoc.v:176590$10373 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360051,10 +326594,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_4 } connect \B { 2'00 \pop_3_5 } - connect \Y $add$libresoc.v:175822$10441_Y + connect \Y $add$libresoc.v:176590$10373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175823$10442 + cell $add $add$libresoc.v:176591$10374 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360062,10 +326605,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_6 } connect \B { 2'00 \pop_3_7 } - connect \Y $add$libresoc.v:175823$10442_Y + connect \Y $add$libresoc.v:176591$10374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175824$10443 + cell $add $add$libresoc.v:176592$10375 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360073,10 +326616,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_8 } connect \B { 2'00 \pop_3_9 } - connect \Y $add$libresoc.v:175824$10443_Y + connect \Y $add$libresoc.v:176592$10375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175825$10444 + cell $add $add$libresoc.v:176593$10376 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360084,10 +326627,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_10 } connect \B { 2'00 \pop_3_11 } - connect \Y $add$libresoc.v:175825$10444_Y + connect \Y $add$libresoc.v:176593$10376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175826$10445 + cell $add $add$libresoc.v:176594$10377 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360095,10 +326638,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_12 } connect \B { 2'00 \pop_3_13 } - connect \Y $add$libresoc.v:175826$10445_Y + connect \Y $add$libresoc.v:176594$10377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175827$10446 + cell $add $add$libresoc.v:176595$10378 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360106,10 +326649,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_14 } connect \B { 2'00 \pop_3_15 } - connect \Y $add$libresoc.v:175827$10446_Y + connect \Y $add$libresoc.v:176595$10378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175828$10447 + cell $add $add$libresoc.v:176596$10379 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -360117,10 +326660,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_0 } connect \B { 2'00 \pop_4_1 } - connect \Y $add$libresoc.v:175828$10447_Y + connect \Y $add$libresoc.v:176596$10379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175829$10448 + cell $add $add$libresoc.v:176597$10380 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -360128,10 +326671,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_2 } connect \B { 2'00 \pop_4_3 } - connect \Y $add$libresoc.v:175829$10448_Y + connect \Y $add$libresoc.v:176597$10380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175830$10449 + cell $add $add$libresoc.v:176598$10381 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -360139,10 +326682,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_4 } connect \B { 2'00 \pop_4_5 } - connect \Y $add$libresoc.v:175830$10449_Y + connect \Y $add$libresoc.v:176598$10381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175831$10450 + cell $add $add$libresoc.v:176599$10382 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360150,10 +326693,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [10] } connect \B { 2'00 \a [11] } - connect \Y $add$libresoc.v:175831$10450_Y + connect \Y $add$libresoc.v:176599$10382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175832$10451 + cell $add $add$libresoc.v:176600$10383 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -360161,10 +326704,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_6 } connect \B { 2'00 \pop_4_7 } - connect \Y $add$libresoc.v:175832$10451_Y + connect \Y $add$libresoc.v:176600$10383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175833$10452 + cell $add $add$libresoc.v:176601$10384 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -360172,10 +326715,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_0 } connect \B { 2'00 \pop_5_1 } - connect \Y $add$libresoc.v:175833$10452_Y + connect \Y $add$libresoc.v:176601$10384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175834$10453 + cell $add $add$libresoc.v:176602$10385 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -360183,10 +326726,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_2 } connect \B { 2'00 \pop_5_3 } - connect \Y $add$libresoc.v:175834$10453_Y + connect \Y $add$libresoc.v:176602$10385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175835$10454 + cell $add $add$libresoc.v:176603$10386 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -360194,10 +326737,10 @@ module \popcount parameter \Y_WIDTH 8 connect \A { 2'00 \pop_6_0 } connect \B { 2'00 \pop_6_1 } - connect \Y $add$libresoc.v:175835$10454_Y + connect \Y $add$libresoc.v:176603$10386_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175846$10473 + cell $add $add$libresoc.v:176614$10405 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360205,10 +326748,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [12] } connect \B { 2'00 \a [13] } - connect \Y $add$libresoc.v:175846$10473_Y + connect \Y $add$libresoc.v:176614$10405_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175850$10480 + cell $add $add$libresoc.v:176618$10412 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360216,10 +326759,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [14] } connect \B { 2'00 \a [15] } - connect \Y $add$libresoc.v:175850$10480_Y + connect \Y $add$libresoc.v:176618$10412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175851$10481 + cell $add $add$libresoc.v:176619$10413 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360227,10 +326770,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [16] } connect \B { 2'00 \a [17] } - connect \Y $add$libresoc.v:175851$10481_Y + connect \Y $add$libresoc.v:176619$10413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175852$10482 + cell $add $add$libresoc.v:176620$10414 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360238,10 +326781,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [0] } connect \B { 2'00 \a [1] } - connect \Y $add$libresoc.v:175852$10482_Y + connect \Y $add$libresoc.v:176620$10414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175853$10483 + cell $add $add$libresoc.v:176621$10415 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360249,10 +326792,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [18] } connect \B { 2'00 \a [19] } - connect \Y $add$libresoc.v:175853$10483_Y + connect \Y $add$libresoc.v:176621$10415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175854$10484 + cell $add $add$libresoc.v:176622$10416 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360260,10 +326803,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [20] } connect \B { 2'00 \a [21] } - connect \Y $add$libresoc.v:175854$10484_Y + connect \Y $add$libresoc.v:176622$10416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175855$10485 + cell $add $add$libresoc.v:176623$10417 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360271,10 +326814,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [22] } connect \B { 2'00 \a [23] } - connect \Y $add$libresoc.v:175855$10485_Y + connect \Y $add$libresoc.v:176623$10417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175856$10486 + cell $add $add$libresoc.v:176624$10418 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360282,10 +326825,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [24] } connect \B { 2'00 \a [25] } - connect \Y $add$libresoc.v:175856$10486_Y + connect \Y $add$libresoc.v:176624$10418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175857$10487 + cell $add $add$libresoc.v:176625$10419 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360293,10 +326836,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [26] } connect \B { 2'00 \a [27] } - connect \Y $add$libresoc.v:175857$10487_Y + connect \Y $add$libresoc.v:176625$10419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175858$10488 + cell $add $add$libresoc.v:176626$10420 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360304,10 +326847,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [28] } connect \B { 2'00 \a [29] } - connect \Y $add$libresoc.v:175858$10488_Y + connect \Y $add$libresoc.v:176626$10420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175859$10489 + cell $add $add$libresoc.v:176627$10421 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360315,10 +326858,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [30] } connect \B { 2'00 \a [31] } - connect \Y $add$libresoc.v:175859$10489_Y + connect \Y $add$libresoc.v:176627$10421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175860$10490 + cell $add $add$libresoc.v:176628$10422 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360326,10 +326869,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [32] } connect \B { 2'00 \a [33] } - connect \Y $add$libresoc.v:175860$10490_Y + connect \Y $add$libresoc.v:176628$10422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175861$10491 + cell $add $add$libresoc.v:176629$10423 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360337,10 +326880,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [34] } connect \B { 2'00 \a [35] } - connect \Y $add$libresoc.v:175861$10491_Y + connect \Y $add$libresoc.v:176629$10423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175862$10492 + cell $add $add$libresoc.v:176630$10424 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360348,10 +326891,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [36] } connect \B { 2'00 \a [37] } - connect \Y $add$libresoc.v:175862$10492_Y + connect \Y $add$libresoc.v:176630$10424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175863$10493 + cell $add $add$libresoc.v:176631$10425 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360359,10 +326902,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [2] } connect \B { 2'00 \a [3] } - connect \Y $add$libresoc.v:175863$10493_Y + connect \Y $add$libresoc.v:176631$10425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175864$10494 + cell $add $add$libresoc.v:176632$10426 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360370,10 +326913,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [38] } connect \B { 2'00 \a [39] } - connect \Y $add$libresoc.v:175864$10494_Y + connect \Y $add$libresoc.v:176632$10426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175865$10495 + cell $add $add$libresoc.v:176633$10427 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360381,10 +326924,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [40] } connect \B { 2'00 \a [41] } - connect \Y $add$libresoc.v:175865$10495_Y + connect \Y $add$libresoc.v:176633$10427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175866$10496 + cell $add $add$libresoc.v:176634$10428 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360392,10 +326935,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [42] } connect \B { 2'00 \a [43] } - connect \Y $add$libresoc.v:175866$10496_Y + connect \Y $add$libresoc.v:176634$10428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175867$10497 + cell $add $add$libresoc.v:176635$10429 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360403,10 +326946,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [44] } connect \B { 2'00 \a [45] } - connect \Y $add$libresoc.v:175867$10497_Y + connect \Y $add$libresoc.v:176635$10429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175868$10498 + cell $add $add$libresoc.v:176636$10430 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360414,10 +326957,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [46] } connect \B { 2'00 \a [47] } - connect \Y $add$libresoc.v:175868$10498_Y + connect \Y $add$libresoc.v:176636$10430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175869$10499 + cell $add $add$libresoc.v:176637$10431 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360425,10 +326968,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [48] } connect \B { 2'00 \a [49] } - connect \Y $add$libresoc.v:175869$10499_Y + connect \Y $add$libresoc.v:176637$10431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175870$10500 + cell $add $add$libresoc.v:176638$10432 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360436,10 +326979,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [50] } connect \B { 2'00 \a [51] } - connect \Y $add$libresoc.v:175870$10500_Y + connect \Y $add$libresoc.v:176638$10432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175871$10501 + cell $add $add$libresoc.v:176639$10433 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360447,10 +326990,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [52] } connect \B { 2'00 \a [53] } - connect \Y $add$libresoc.v:175871$10501_Y + connect \Y $add$libresoc.v:176639$10433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175872$10502 + cell $add $add$libresoc.v:176640$10434 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360458,10 +327001,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [54] } connect \B { 2'00 \a [55] } - connect \Y $add$libresoc.v:175872$10502_Y + connect \Y $add$libresoc.v:176640$10434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175873$10503 + cell $add $add$libresoc.v:176641$10435 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360469,10 +327012,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [56] } connect \B { 2'00 \a [57] } - connect \Y $add$libresoc.v:175873$10503_Y + connect \Y $add$libresoc.v:176641$10435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175874$10504 + cell $add $add$libresoc.v:176642$10436 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360480,10 +327023,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [4] } connect \B { 2'00 \a [5] } - connect \Y $add$libresoc.v:175874$10504_Y + connect \Y $add$libresoc.v:176642$10436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175875$10505 + cell $add $add$libresoc.v:176643$10437 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360491,10 +327034,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [58] } connect \B { 2'00 \a [59] } - connect \Y $add$libresoc.v:175875$10505_Y + connect \Y $add$libresoc.v:176643$10437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175876$10506 + cell $add $add$libresoc.v:176644$10438 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360502,10 +327045,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [60] } connect \B { 2'00 \a [61] } - connect \Y $add$libresoc.v:175876$10506_Y + connect \Y $add$libresoc.v:176644$10438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175877$10507 + cell $add $add$libresoc.v:176645$10439 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360513,10 +327056,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [62] } connect \B { 2'00 \a [63] } - connect \Y $add$libresoc.v:175877$10507_Y + connect \Y $add$libresoc.v:176645$10439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175878$10508 + cell $add $add$libresoc.v:176646$10440 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -360524,10 +327067,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_0 } connect \B { 2'00 \pop_2_1 } - connect \Y $add$libresoc.v:175878$10508_Y + connect \Y $add$libresoc.v:176646$10440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - cell $eq $eq$libresoc.v:175836$10455 + cell $eq $eq$libresoc.v:176604$10387 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -360535,10 +327078,10 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 1'1 - connect \Y $eq$libresoc.v:175836$10455_Y + connect \Y $eq$libresoc.v:176604$10387_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - cell $eq $eq$libresoc.v:175837$10456 + cell $eq $eq$libresoc.v:176605$10388 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -360546,199 +327089,199 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 3'100 - connect \Y $eq$libresoc.v:175837$10456_Y + connect \Y $eq$libresoc.v:176605$10388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175838$10457 + cell $pos $extend$libresoc.v:176606$10389 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_0 - connect \Y $extend$libresoc.v:175838$10457_Y + connect \Y $extend$libresoc.v:176606$10389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175839$10459 + cell $pos $extend$libresoc.v:176607$10391 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_1 - connect \Y $extend$libresoc.v:175839$10459_Y + connect \Y $extend$libresoc.v:176607$10391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175840$10461 + cell $pos $extend$libresoc.v:176608$10393 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_2 - connect \Y $extend$libresoc.v:175840$10461_Y + connect \Y $extend$libresoc.v:176608$10393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175841$10463 + cell $pos $extend$libresoc.v:176609$10395 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_3 - connect \Y $extend$libresoc.v:175841$10463_Y + connect \Y $extend$libresoc.v:176609$10395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175842$10465 + cell $pos $extend$libresoc.v:176610$10397 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_4 - connect \Y $extend$libresoc.v:175842$10465_Y + connect \Y $extend$libresoc.v:176610$10397_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175843$10467 + cell $pos $extend$libresoc.v:176611$10399 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_5 - connect \Y $extend$libresoc.v:175843$10467_Y + connect \Y $extend$libresoc.v:176611$10399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175844$10469 + cell $pos $extend$libresoc.v:176612$10401 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_6 - connect \Y $extend$libresoc.v:175844$10469_Y + connect \Y $extend$libresoc.v:176612$10401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175845$10471 + cell $pos $extend$libresoc.v:176613$10403 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_7 - connect \Y $extend$libresoc.v:175845$10471_Y + connect \Y $extend$libresoc.v:176613$10403_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175847$10474 + cell $pos $extend$libresoc.v:176615$10406 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_0 - connect \Y $extend$libresoc.v:175847$10474_Y + connect \Y $extend$libresoc.v:176615$10406_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175848$10476 + cell $pos $extend$libresoc.v:176616$10408 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_1 - connect \Y $extend$libresoc.v:175848$10476_Y + connect \Y $extend$libresoc.v:176616$10408_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175849$10478 + cell $pos $extend$libresoc.v:176617$10410 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 64 connect \A \pop_7_0 - connect \Y $extend$libresoc.v:175849$10478_Y + connect \Y $extend$libresoc.v:176617$10410_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175838$10458 + cell $pos $pos$libresoc.v:176606$10390 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175838$10457_Y - connect \Y $pos$libresoc.v:175838$10458_Y + connect \A $extend$libresoc.v:176606$10389_Y + connect \Y $pos$libresoc.v:176606$10390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175839$10460 + cell $pos $pos$libresoc.v:176607$10392 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175839$10459_Y - connect \Y $pos$libresoc.v:175839$10460_Y + connect \A $extend$libresoc.v:176607$10391_Y + connect \Y $pos$libresoc.v:176607$10392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175840$10462 + cell $pos $pos$libresoc.v:176608$10394 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175840$10461_Y - connect \Y $pos$libresoc.v:175840$10462_Y + connect \A $extend$libresoc.v:176608$10393_Y + connect \Y $pos$libresoc.v:176608$10394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175841$10464 + cell $pos $pos$libresoc.v:176609$10396 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175841$10463_Y - connect \Y $pos$libresoc.v:175841$10464_Y + connect \A $extend$libresoc.v:176609$10395_Y + connect \Y $pos$libresoc.v:176609$10396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175842$10466 + cell $pos $pos$libresoc.v:176610$10398 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175842$10465_Y - connect \Y $pos$libresoc.v:175842$10466_Y + connect \A $extend$libresoc.v:176610$10397_Y + connect \Y $pos$libresoc.v:176610$10398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175843$10468 + cell $pos $pos$libresoc.v:176611$10400 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175843$10467_Y - connect \Y $pos$libresoc.v:175843$10468_Y + connect \A $extend$libresoc.v:176611$10399_Y + connect \Y $pos$libresoc.v:176611$10400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175844$10470 + cell $pos $pos$libresoc.v:176612$10402 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175844$10469_Y - connect \Y $pos$libresoc.v:175844$10470_Y + connect \A $extend$libresoc.v:176612$10401_Y + connect \Y $pos$libresoc.v:176612$10402_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175845$10472 + cell $pos $pos$libresoc.v:176613$10404 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175845$10471_Y - connect \Y $pos$libresoc.v:175845$10472_Y + connect \A $extend$libresoc.v:176613$10403_Y + connect \Y $pos$libresoc.v:176613$10404_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175847$10475 + cell $pos $pos$libresoc.v:176615$10407 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:175847$10474_Y - connect \Y $pos$libresoc.v:175847$10475_Y + connect \A $extend$libresoc.v:176615$10406_Y + connect \Y $pos$libresoc.v:176615$10407_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175848$10477 + cell $pos $pos$libresoc.v:176616$10409 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:175848$10476_Y - connect \Y $pos$libresoc.v:175848$10477_Y + connect \A $extend$libresoc.v:176616$10408_Y + connect \Y $pos$libresoc.v:176616$10409_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175849$10479 + cell $pos $pos$libresoc.v:176617$10411 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:175849$10478_Y - connect \Y $pos$libresoc.v:175849$10479_Y + connect \A $extend$libresoc.v:176617$10410_Y + connect \Y $pos$libresoc.v:176617$10411_Y end - attribute \src "libresoc.v:175391.7-175391.20" - process $proc$libresoc.v:175391$10510 + attribute \src "libresoc.v:176159.7-176159.20" + process $proc$libresoc.v:176159$10442 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175879.3-175905.6" - process $proc$libresoc.v:175879$10509 + attribute \src "libresoc.v:176647.3-176673.6" + process $proc$libresoc.v:176647$10441 assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:175880.5-175880.29" + attribute \src "libresoc.v:176648.5-176648.29" switch \initial - attribute \src "libresoc.v:175880.9-175880.17" + attribute \src "libresoc.v:176648.9-176648.17" case 1'1 case end @@ -360768,82 +327311,82 @@ module \popcount sync always update \o $0\o[63:0] end - connect \$101 $add$libresoc.v:175803$10422_Y - connect \$104 $add$libresoc.v:175804$10423_Y - connect \$107 $add$libresoc.v:175805$10424_Y - connect \$110 $add$libresoc.v:175806$10425_Y - connect \$113 $add$libresoc.v:175807$10426_Y - connect \$116 $add$libresoc.v:175808$10427_Y - connect \$11 $add$libresoc.v:175809$10428_Y - connect \$119 $add$libresoc.v:175810$10429_Y - connect \$122 $add$libresoc.v:175811$10430_Y - connect \$125 $add$libresoc.v:175812$10431_Y - connect \$128 $add$libresoc.v:175813$10432_Y - connect \$131 $add$libresoc.v:175814$10433_Y - connect \$134 $add$libresoc.v:175815$10434_Y - connect \$137 $add$libresoc.v:175816$10435_Y - connect \$140 $add$libresoc.v:175817$10436_Y - connect \$143 $add$libresoc.v:175818$10437_Y - connect \$146 $add$libresoc.v:175819$10438_Y - connect \$14 $add$libresoc.v:175820$10439_Y - connect \$149 $add$libresoc.v:175821$10440_Y - connect \$152 $add$libresoc.v:175822$10441_Y - connect \$155 $add$libresoc.v:175823$10442_Y - connect \$158 $add$libresoc.v:175824$10443_Y - connect \$161 $add$libresoc.v:175825$10444_Y - connect \$164 $add$libresoc.v:175826$10445_Y - connect \$167 $add$libresoc.v:175827$10446_Y - connect \$170 $add$libresoc.v:175828$10447_Y - connect \$173 $add$libresoc.v:175829$10448_Y - connect \$176 $add$libresoc.v:175830$10449_Y - connect \$17 $add$libresoc.v:175831$10450_Y - connect \$179 $add$libresoc.v:175832$10451_Y - connect \$182 $add$libresoc.v:175833$10452_Y - connect \$185 $add$libresoc.v:175834$10453_Y - connect \$188 $add$libresoc.v:175835$10454_Y - connect \$190 $eq$libresoc.v:175836$10455_Y - connect \$192 $eq$libresoc.v:175837$10456_Y - connect \$194 $pos$libresoc.v:175838$10458_Y - connect \$196 $pos$libresoc.v:175839$10460_Y - connect \$198 $pos$libresoc.v:175840$10462_Y - connect \$200 $pos$libresoc.v:175841$10464_Y - connect \$202 $pos$libresoc.v:175842$10466_Y - connect \$204 $pos$libresoc.v:175843$10468_Y - connect \$206 $pos$libresoc.v:175844$10470_Y - connect \$208 $pos$libresoc.v:175845$10472_Y - connect \$20 $add$libresoc.v:175846$10473_Y - connect \$210 $pos$libresoc.v:175847$10475_Y - connect \$212 $pos$libresoc.v:175848$10477_Y - connect \$214 $pos$libresoc.v:175849$10479_Y - connect \$23 $add$libresoc.v:175850$10480_Y - connect \$26 $add$libresoc.v:175851$10481_Y - connect \$2 $add$libresoc.v:175852$10482_Y - connect \$29 $add$libresoc.v:175853$10483_Y - connect \$32 $add$libresoc.v:175854$10484_Y - connect \$35 $add$libresoc.v:175855$10485_Y - connect \$38 $add$libresoc.v:175856$10486_Y - connect \$41 $add$libresoc.v:175857$10487_Y - connect \$44 $add$libresoc.v:175858$10488_Y - connect \$47 $add$libresoc.v:175859$10489_Y - connect \$50 $add$libresoc.v:175860$10490_Y - connect \$53 $add$libresoc.v:175861$10491_Y - connect \$56 $add$libresoc.v:175862$10492_Y - connect \$5 $add$libresoc.v:175863$10493_Y - connect \$59 $add$libresoc.v:175864$10494_Y - connect \$62 $add$libresoc.v:175865$10495_Y - connect \$65 $add$libresoc.v:175866$10496_Y - connect \$68 $add$libresoc.v:175867$10497_Y - connect \$71 $add$libresoc.v:175868$10498_Y - connect \$74 $add$libresoc.v:175869$10499_Y - connect \$77 $add$libresoc.v:175870$10500_Y - connect \$80 $add$libresoc.v:175871$10501_Y - connect \$83 $add$libresoc.v:175872$10502_Y - connect \$86 $add$libresoc.v:175873$10503_Y - connect \$8 $add$libresoc.v:175874$10504_Y - connect \$89 $add$libresoc.v:175875$10505_Y - connect \$92 $add$libresoc.v:175876$10506_Y - connect \$95 $add$libresoc.v:175877$10507_Y - connect \$98 $add$libresoc.v:175878$10508_Y + connect \$101 $add$libresoc.v:176571$10354_Y + connect \$104 $add$libresoc.v:176572$10355_Y + connect \$107 $add$libresoc.v:176573$10356_Y + connect \$110 $add$libresoc.v:176574$10357_Y + connect \$113 $add$libresoc.v:176575$10358_Y + connect \$116 $add$libresoc.v:176576$10359_Y + connect \$11 $add$libresoc.v:176577$10360_Y + connect \$119 $add$libresoc.v:176578$10361_Y + connect \$122 $add$libresoc.v:176579$10362_Y + connect \$125 $add$libresoc.v:176580$10363_Y + connect \$128 $add$libresoc.v:176581$10364_Y + connect \$131 $add$libresoc.v:176582$10365_Y + connect \$134 $add$libresoc.v:176583$10366_Y + connect \$137 $add$libresoc.v:176584$10367_Y + connect \$140 $add$libresoc.v:176585$10368_Y + connect \$143 $add$libresoc.v:176586$10369_Y + connect \$146 $add$libresoc.v:176587$10370_Y + connect \$14 $add$libresoc.v:176588$10371_Y + connect \$149 $add$libresoc.v:176589$10372_Y + connect \$152 $add$libresoc.v:176590$10373_Y + connect \$155 $add$libresoc.v:176591$10374_Y + connect \$158 $add$libresoc.v:176592$10375_Y + connect \$161 $add$libresoc.v:176593$10376_Y + connect \$164 $add$libresoc.v:176594$10377_Y + connect \$167 $add$libresoc.v:176595$10378_Y + connect \$170 $add$libresoc.v:176596$10379_Y + connect \$173 $add$libresoc.v:176597$10380_Y + connect \$176 $add$libresoc.v:176598$10381_Y + connect \$17 $add$libresoc.v:176599$10382_Y + connect \$179 $add$libresoc.v:176600$10383_Y + connect \$182 $add$libresoc.v:176601$10384_Y + connect \$185 $add$libresoc.v:176602$10385_Y + connect \$188 $add$libresoc.v:176603$10386_Y + connect \$190 $eq$libresoc.v:176604$10387_Y + connect \$192 $eq$libresoc.v:176605$10388_Y + connect \$194 $pos$libresoc.v:176606$10390_Y + connect \$196 $pos$libresoc.v:176607$10392_Y + connect \$198 $pos$libresoc.v:176608$10394_Y + connect \$200 $pos$libresoc.v:176609$10396_Y + connect \$202 $pos$libresoc.v:176610$10398_Y + connect \$204 $pos$libresoc.v:176611$10400_Y + connect \$206 $pos$libresoc.v:176612$10402_Y + connect \$208 $pos$libresoc.v:176613$10404_Y + connect \$20 $add$libresoc.v:176614$10405_Y + connect \$210 $pos$libresoc.v:176615$10407_Y + connect \$212 $pos$libresoc.v:176616$10409_Y + connect \$214 $pos$libresoc.v:176617$10411_Y + connect \$23 $add$libresoc.v:176618$10412_Y + connect \$26 $add$libresoc.v:176619$10413_Y + connect \$2 $add$libresoc.v:176620$10414_Y + connect \$29 $add$libresoc.v:176621$10415_Y + connect \$32 $add$libresoc.v:176622$10416_Y + connect \$35 $add$libresoc.v:176623$10417_Y + connect \$38 $add$libresoc.v:176624$10418_Y + connect \$41 $add$libresoc.v:176625$10419_Y + connect \$44 $add$libresoc.v:176626$10420_Y + connect \$47 $add$libresoc.v:176627$10421_Y + connect \$50 $add$libresoc.v:176628$10422_Y + connect \$53 $add$libresoc.v:176629$10423_Y + connect \$56 $add$libresoc.v:176630$10424_Y + connect \$5 $add$libresoc.v:176631$10425_Y + connect \$59 $add$libresoc.v:176632$10426_Y + connect \$62 $add$libresoc.v:176633$10427_Y + connect \$65 $add$libresoc.v:176634$10428_Y + connect \$68 $add$libresoc.v:176635$10429_Y + connect \$71 $add$libresoc.v:176636$10430_Y + connect \$74 $add$libresoc.v:176637$10431_Y + connect \$77 $add$libresoc.v:176638$10432_Y + connect \$80 $add$libresoc.v:176639$10433_Y + connect \$83 $add$libresoc.v:176640$10434_Y + connect \$86 $add$libresoc.v:176641$10435_Y + connect \$8 $add$libresoc.v:176642$10436_Y + connect \$89 $add$libresoc.v:176643$10437_Y + connect \$92 $add$libresoc.v:176644$10438_Y + connect \$95 $add$libresoc.v:176645$10439_Y + connect \$98 $add$libresoc.v:176646$10440_Y connect \$1 \$2 connect \$4 \$5 connect \$7 \$8 @@ -360971,43 +327514,43 @@ module \popcount connect \pop_2_1 \$5 [1:0] connect \pop_2_0 \$2 [1:0] end -attribute \src "libresoc.v:176036.1-176120.10" +attribute \src "libresoc.v:176804.1-176888.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" attribute \generator "nMigen" module \ppick - attribute \src "libresoc.v:176093.17-176093.91" - wire $not$libresoc.v:176093$10511_Y - attribute \src "libresoc.v:176095.18-176095.93" - wire $not$libresoc.v:176095$10513_Y - attribute \src "libresoc.v:176097.18-176097.93" - wire $not$libresoc.v:176097$10515_Y - attribute \src "libresoc.v:176098.17-176098.138" - wire width 8 $not$libresoc.v:176098$10516_Y - attribute \src "libresoc.v:176100.18-176100.93" - wire $not$libresoc.v:176100$10518_Y - attribute \src "libresoc.v:176102.18-176102.93" - wire $not$libresoc.v:176102$10520_Y - attribute \src "libresoc.v:176104.18-176104.93" - wire $not$libresoc.v:176104$10522_Y - attribute \src "libresoc.v:176107.17-176107.91" - wire $not$libresoc.v:176107$10525_Y - attribute \src "libresoc.v:176094.18-176094.116" - wire $reduce_or$libresoc.v:176094$10512_Y - attribute \src "libresoc.v:176096.18-176096.122" - wire $reduce_or$libresoc.v:176096$10514_Y - attribute \src "libresoc.v:176099.18-176099.128" - wire $reduce_or$libresoc.v:176099$10517_Y - attribute \src "libresoc.v:176101.18-176101.134" - wire $reduce_or$libresoc.v:176101$10519_Y - attribute \src "libresoc.v:176103.18-176103.140" - wire $reduce_or$libresoc.v:176103$10521_Y - attribute \src "libresoc.v:176105.18-176105.90" - wire $reduce_or$libresoc.v:176105$10523_Y - attribute \src "libresoc.v:176106.17-176106.103" - wire $reduce_or$libresoc.v:176106$10524_Y - attribute \src "libresoc.v:176108.17-176108.109" - wire $reduce_or$libresoc.v:176108$10526_Y + attribute \src "libresoc.v:176861.17-176861.91" + wire $not$libresoc.v:176861$10443_Y + attribute \src "libresoc.v:176863.18-176863.93" + wire $not$libresoc.v:176863$10445_Y + attribute \src "libresoc.v:176865.18-176865.93" + wire $not$libresoc.v:176865$10447_Y + attribute \src "libresoc.v:176866.17-176866.138" + wire width 8 $not$libresoc.v:176866$10448_Y + attribute \src "libresoc.v:176868.18-176868.93" + wire $not$libresoc.v:176868$10450_Y + attribute \src "libresoc.v:176870.18-176870.93" + wire $not$libresoc.v:176870$10452_Y + attribute \src "libresoc.v:176872.18-176872.93" + wire $not$libresoc.v:176872$10454_Y + attribute \src "libresoc.v:176875.17-176875.91" + wire $not$libresoc.v:176875$10457_Y + attribute \src "libresoc.v:176862.18-176862.116" + wire $reduce_or$libresoc.v:176862$10444_Y + attribute \src "libresoc.v:176864.18-176864.122" + wire $reduce_or$libresoc.v:176864$10446_Y + attribute \src "libresoc.v:176867.18-176867.128" + wire $reduce_or$libresoc.v:176867$10449_Y + attribute \src "libresoc.v:176869.18-176869.134" + wire $reduce_or$libresoc.v:176869$10451_Y + attribute \src "libresoc.v:176871.18-176871.140" + wire $reduce_or$libresoc.v:176871$10453_Y + attribute \src "libresoc.v:176873.18-176873.90" + wire $reduce_or$libresoc.v:176873$10455_Y + attribute \src "libresoc.v:176874.17-176874.103" + wire $reduce_or$libresoc.v:176874$10456_Y + attribute \src "libresoc.v:176876.17-176876.109" + wire $reduce_or$libresoc.v:176876$10458_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -361065,149 +327608,149 @@ module \ppick attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176093$10511 + cell $not $not$libresoc.v:176861$10443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176093$10511_Y + connect \Y $not$libresoc.v:176861$10443_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176095$10513 + cell $not $not$libresoc.v:176863$10445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:176095$10513_Y + connect \Y $not$libresoc.v:176863$10445_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176097$10515 + cell $not $not$libresoc.v:176865$10447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:176097$10515_Y + connect \Y $not$libresoc.v:176865$10447_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176098$10516 + cell $not $not$libresoc.v:176866$10448 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:176098$10516_Y + connect \Y $not$libresoc.v:176866$10448_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176100$10518 + cell $not $not$libresoc.v:176868$10450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:176100$10518_Y + connect \Y $not$libresoc.v:176868$10450_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176102$10520 + cell $not $not$libresoc.v:176870$10452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:176102$10520_Y + connect \Y $not$libresoc.v:176870$10452_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176104$10522 + cell $not $not$libresoc.v:176872$10454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:176104$10522_Y + connect \Y $not$libresoc.v:176872$10454_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176107$10525 + cell $not $not$libresoc.v:176875$10457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176107$10525_Y + connect \Y $not$libresoc.v:176875$10457_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176094$10512 + cell $reduce_or $reduce_or$libresoc.v:176862$10444 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:176094$10512_Y + connect \Y $reduce_or$libresoc.v:176862$10444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176096$10514 + cell $reduce_or $reduce_or$libresoc.v:176864$10446 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:176096$10514_Y + connect \Y $reduce_or$libresoc.v:176864$10446_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176099$10517 + cell $reduce_or $reduce_or$libresoc.v:176867$10449 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:176099$10517_Y + connect \Y $reduce_or$libresoc.v:176867$10449_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176101$10519 + cell $reduce_or $reduce_or$libresoc.v:176869$10451 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:176101$10519_Y + connect \Y $reduce_or$libresoc.v:176869$10451_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176103$10521 + cell $reduce_or $reduce_or$libresoc.v:176871$10453 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:176103$10521_Y + connect \Y $reduce_or$libresoc.v:176871$10453_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176105$10523 + cell $reduce_or $reduce_or$libresoc.v:176873$10455 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176105$10523_Y + connect \Y $reduce_or$libresoc.v:176873$10455_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176106$10524 + cell $reduce_or $reduce_or$libresoc.v:176874$10456 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:176106$10524_Y + connect \Y $reduce_or$libresoc.v:176874$10456_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176108$10526 + cell $reduce_or $reduce_or$libresoc.v:176876$10458 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:176108$10526_Y - end - connect \$7 $not$libresoc.v:176093$10511_Y - connect \$12 $reduce_or$libresoc.v:176094$10512_Y - connect \$11 $not$libresoc.v:176095$10513_Y - connect \$16 $reduce_or$libresoc.v:176096$10514_Y - connect \$15 $not$libresoc.v:176097$10515_Y - connect \$1 $not$libresoc.v:176098$10516_Y - connect \$20 $reduce_or$libresoc.v:176099$10517_Y - connect \$19 $not$libresoc.v:176100$10518_Y - connect \$24 $reduce_or$libresoc.v:176101$10519_Y - connect \$23 $not$libresoc.v:176102$10520_Y - connect \$28 $reduce_or$libresoc.v:176103$10521_Y - connect \$27 $not$libresoc.v:176104$10522_Y - connect \$31 $reduce_or$libresoc.v:176105$10523_Y - connect \$4 $reduce_or$libresoc.v:176106$10524_Y - connect \$3 $not$libresoc.v:176107$10525_Y - connect \$8 $reduce_or$libresoc.v:176108$10526_Y + connect \Y $reduce_or$libresoc.v:176876$10458_Y + end + connect \$7 $not$libresoc.v:176861$10443_Y + connect \$12 $reduce_or$libresoc.v:176862$10444_Y + connect \$11 $not$libresoc.v:176863$10445_Y + connect \$16 $reduce_or$libresoc.v:176864$10446_Y + connect \$15 $not$libresoc.v:176865$10447_Y + connect \$1 $not$libresoc.v:176866$10448_Y + connect \$20 $reduce_or$libresoc.v:176867$10449_Y + connect \$19 $not$libresoc.v:176868$10450_Y + connect \$24 $reduce_or$libresoc.v:176869$10451_Y + connect \$23 $not$libresoc.v:176870$10452_Y + connect \$28 $reduce_or$libresoc.v:176871$10453_Y + connect \$27 $not$libresoc.v:176872$10454_Y + connect \$31 $reduce_or$libresoc.v:176873$10455_Y + connect \$4 $reduce_or$libresoc.v:176874$10456_Y + connect \$3 $not$libresoc.v:176875$10457_Y + connect \$8 $reduce_or$libresoc.v:176876$10458_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -361220,43 +327763,43 @@ module \ppick connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:176124.1-176208.10" +attribute \src "libresoc.v:176892.1-176976.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" attribute \generator "nMigen" module \ppick$175 - attribute \src "libresoc.v:176181.17-176181.91" - wire $not$libresoc.v:176181$10527_Y - attribute \src "libresoc.v:176183.18-176183.93" - wire $not$libresoc.v:176183$10529_Y - attribute \src "libresoc.v:176185.18-176185.93" - wire $not$libresoc.v:176185$10531_Y - attribute \src "libresoc.v:176186.17-176186.138" - wire width 8 $not$libresoc.v:176186$10532_Y - attribute \src "libresoc.v:176188.18-176188.93" - wire $not$libresoc.v:176188$10534_Y - attribute \src "libresoc.v:176190.18-176190.93" - wire $not$libresoc.v:176190$10536_Y - attribute \src "libresoc.v:176192.18-176192.93" - wire $not$libresoc.v:176192$10538_Y - attribute \src "libresoc.v:176195.17-176195.91" - wire $not$libresoc.v:176195$10541_Y - attribute \src "libresoc.v:176182.18-176182.116" - wire $reduce_or$libresoc.v:176182$10528_Y - attribute \src "libresoc.v:176184.18-176184.122" - wire $reduce_or$libresoc.v:176184$10530_Y - attribute \src "libresoc.v:176187.18-176187.128" - wire $reduce_or$libresoc.v:176187$10533_Y - attribute \src "libresoc.v:176189.18-176189.134" - wire $reduce_or$libresoc.v:176189$10535_Y - attribute \src "libresoc.v:176191.18-176191.140" - wire $reduce_or$libresoc.v:176191$10537_Y - attribute \src "libresoc.v:176193.18-176193.90" - wire $reduce_or$libresoc.v:176193$10539_Y - attribute \src "libresoc.v:176194.17-176194.103" - wire $reduce_or$libresoc.v:176194$10540_Y - attribute \src "libresoc.v:176196.17-176196.109" - wire $reduce_or$libresoc.v:176196$10542_Y + attribute \src "libresoc.v:176949.17-176949.91" + wire $not$libresoc.v:176949$10459_Y + attribute \src "libresoc.v:176951.18-176951.93" + wire $not$libresoc.v:176951$10461_Y + attribute \src "libresoc.v:176953.18-176953.93" + wire $not$libresoc.v:176953$10463_Y + attribute \src "libresoc.v:176954.17-176954.138" + wire width 8 $not$libresoc.v:176954$10464_Y + attribute \src "libresoc.v:176956.18-176956.93" + wire $not$libresoc.v:176956$10466_Y + attribute \src "libresoc.v:176958.18-176958.93" + wire $not$libresoc.v:176958$10468_Y + attribute \src "libresoc.v:176960.18-176960.93" + wire $not$libresoc.v:176960$10470_Y + attribute \src "libresoc.v:176963.17-176963.91" + wire $not$libresoc.v:176963$10473_Y + attribute \src "libresoc.v:176950.18-176950.116" + wire $reduce_or$libresoc.v:176950$10460_Y + attribute \src "libresoc.v:176952.18-176952.122" + wire $reduce_or$libresoc.v:176952$10462_Y + attribute \src "libresoc.v:176955.18-176955.128" + wire $reduce_or$libresoc.v:176955$10465_Y + attribute \src "libresoc.v:176957.18-176957.134" + wire $reduce_or$libresoc.v:176957$10467_Y + attribute \src "libresoc.v:176959.18-176959.140" + wire $reduce_or$libresoc.v:176959$10469_Y + attribute \src "libresoc.v:176961.18-176961.90" + wire $reduce_or$libresoc.v:176961$10471_Y + attribute \src "libresoc.v:176962.17-176962.103" + wire $reduce_or$libresoc.v:176962$10472_Y + attribute \src "libresoc.v:176964.17-176964.109" + wire $reduce_or$libresoc.v:176964$10474_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -361314,149 +327857,149 @@ module \ppick$175 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176181$10527 + cell $not $not$libresoc.v:176949$10459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176181$10527_Y + connect \Y $not$libresoc.v:176949$10459_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176183$10529 + cell $not $not$libresoc.v:176951$10461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:176183$10529_Y + connect \Y $not$libresoc.v:176951$10461_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176185$10531 + cell $not $not$libresoc.v:176953$10463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:176185$10531_Y + connect \Y $not$libresoc.v:176953$10463_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176186$10532 + cell $not $not$libresoc.v:176954$10464 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:176186$10532_Y + connect \Y $not$libresoc.v:176954$10464_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176188$10534 + cell $not $not$libresoc.v:176956$10466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:176188$10534_Y + connect \Y $not$libresoc.v:176956$10466_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176190$10536 + cell $not $not$libresoc.v:176958$10468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:176190$10536_Y + connect \Y $not$libresoc.v:176958$10468_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176192$10538 + cell $not $not$libresoc.v:176960$10470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:176192$10538_Y + connect \Y $not$libresoc.v:176960$10470_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176195$10541 + cell $not $not$libresoc.v:176963$10473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176195$10541_Y + connect \Y $not$libresoc.v:176963$10473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176182$10528 + cell $reduce_or $reduce_or$libresoc.v:176950$10460 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:176182$10528_Y + connect \Y $reduce_or$libresoc.v:176950$10460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176184$10530 + cell $reduce_or $reduce_or$libresoc.v:176952$10462 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:176184$10530_Y + connect \Y $reduce_or$libresoc.v:176952$10462_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176187$10533 + cell $reduce_or $reduce_or$libresoc.v:176955$10465 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:176187$10533_Y + connect \Y $reduce_or$libresoc.v:176955$10465_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176189$10535 + cell $reduce_or $reduce_or$libresoc.v:176957$10467 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:176189$10535_Y + connect \Y $reduce_or$libresoc.v:176957$10467_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176191$10537 + cell $reduce_or $reduce_or$libresoc.v:176959$10469 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:176191$10537_Y + connect \Y $reduce_or$libresoc.v:176959$10469_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176193$10539 + cell $reduce_or $reduce_or$libresoc.v:176961$10471 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176193$10539_Y + connect \Y $reduce_or$libresoc.v:176961$10471_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176194$10540 + cell $reduce_or $reduce_or$libresoc.v:176962$10472 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:176194$10540_Y + connect \Y $reduce_or$libresoc.v:176962$10472_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176196$10542 + cell $reduce_or $reduce_or$libresoc.v:176964$10474 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:176196$10542_Y - end - connect \$7 $not$libresoc.v:176181$10527_Y - connect \$12 $reduce_or$libresoc.v:176182$10528_Y - connect \$11 $not$libresoc.v:176183$10529_Y - connect \$16 $reduce_or$libresoc.v:176184$10530_Y - connect \$15 $not$libresoc.v:176185$10531_Y - connect \$1 $not$libresoc.v:176186$10532_Y - connect \$20 $reduce_or$libresoc.v:176187$10533_Y - connect \$19 $not$libresoc.v:176188$10534_Y - connect \$24 $reduce_or$libresoc.v:176189$10535_Y - connect \$23 $not$libresoc.v:176190$10536_Y - connect \$28 $reduce_or$libresoc.v:176191$10537_Y - connect \$27 $not$libresoc.v:176192$10538_Y - connect \$31 $reduce_or$libresoc.v:176193$10539_Y - connect \$4 $reduce_or$libresoc.v:176194$10540_Y - connect \$3 $not$libresoc.v:176195$10541_Y - connect \$8 $reduce_or$libresoc.v:176196$10542_Y + connect \Y $reduce_or$libresoc.v:176964$10474_Y + end + connect \$7 $not$libresoc.v:176949$10459_Y + connect \$12 $reduce_or$libresoc.v:176950$10460_Y + connect \$11 $not$libresoc.v:176951$10461_Y + connect \$16 $reduce_or$libresoc.v:176952$10462_Y + connect \$15 $not$libresoc.v:176953$10463_Y + connect \$1 $not$libresoc.v:176954$10464_Y + connect \$20 $reduce_or$libresoc.v:176955$10465_Y + connect \$19 $not$libresoc.v:176956$10466_Y + connect \$24 $reduce_or$libresoc.v:176957$10467_Y + connect \$23 $not$libresoc.v:176958$10468_Y + connect \$28 $reduce_or$libresoc.v:176959$10469_Y + connect \$27 $not$libresoc.v:176960$10470_Y + connect \$31 $reduce_or$libresoc.v:176961$10471_Y + connect \$4 $reduce_or$libresoc.v:176962$10472_Y + connect \$3 $not$libresoc.v:176963$10473_Y + connect \$8 $reduce_or$libresoc.v:176964$10474_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -361469,19 +328012,19 @@ module \ppick$175 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:176212.1-176242.10" +attribute \src "libresoc.v:176980.1-177010.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" attribute \generator "nMigen" module \rdpick_CR_cr_a - attribute \src "libresoc.v:176233.17-176233.89" - wire width 2 $not$libresoc.v:176233$10543_Y - attribute \src "libresoc.v:176235.17-176235.91" - wire $not$libresoc.v:176235$10545_Y - attribute \src "libresoc.v:176234.17-176234.103" - wire $reduce_or$libresoc.v:176234$10544_Y - attribute \src "libresoc.v:176236.17-176236.89" - wire $reduce_or$libresoc.v:176236$10546_Y + attribute \src "libresoc.v:177001.17-177001.89" + wire width 2 $not$libresoc.v:177001$10475_Y + attribute \src "libresoc.v:177003.17-177003.91" + wire $not$libresoc.v:177003$10477_Y + attribute \src "libresoc.v:177002.17-177002.103" + wire $reduce_or$libresoc.v:177002$10476_Y + attribute \src "libresoc.v:177004.17-177004.89" + wire $reduce_or$libresoc.v:177004$10478_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -361503,56 +328046,56 @@ module \rdpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176233$10543 + cell $not $not$libresoc.v:177001$10475 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:176233$10543_Y + connect \Y $not$libresoc.v:177001$10475_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176235$10545 + cell $not $not$libresoc.v:177003$10477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176235$10545_Y + connect \Y $not$libresoc.v:177003$10477_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176234$10544 + cell $reduce_or $reduce_or$libresoc.v:177002$10476 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176234$10544_Y + connect \Y $reduce_or$libresoc.v:177002$10476_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176236$10546 + cell $reduce_or $reduce_or$libresoc.v:177004$10478 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176236$10546_Y + connect \Y $reduce_or$libresoc.v:177004$10478_Y end - connect \$1 $not$libresoc.v:176233$10543_Y - connect \$4 $reduce_or$libresoc.v:176234$10544_Y - connect \$3 $not$libresoc.v:176235$10545_Y - connect \$7 $reduce_or$libresoc.v:176236$10546_Y + connect \$1 $not$libresoc.v:177001$10475_Y + connect \$4 $reduce_or$libresoc.v:177002$10476_Y + connect \$3 $not$libresoc.v:177003$10477_Y + connect \$7 $reduce_or$libresoc.v:177004$10478_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176246.1-176267.10" +attribute \src "libresoc.v:177014.1-177035.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" attribute \generator "nMigen" module \rdpick_CR_cr_b - attribute \src "libresoc.v:176261.17-176261.89" - wire $not$libresoc.v:176261$10547_Y - attribute \src "libresoc.v:176262.17-176262.89" - wire $reduce_or$libresoc.v:176262$10548_Y + attribute \src "libresoc.v:177029.17-177029.89" + wire $not$libresoc.v:177029$10479_Y + attribute \src "libresoc.v:177030.17-177030.89" + wire $reduce_or$libresoc.v:177030$10480_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -361568,37 +328111,37 @@ module \rdpick_CR_cr_b attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176261$10547 + cell $not $not$libresoc.v:177029$10479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176261$10547_Y + connect \Y $not$libresoc.v:177029$10479_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176262$10548 + cell $reduce_or $reduce_or$libresoc.v:177030$10480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176262$10548_Y + connect \Y $reduce_or$libresoc.v:177030$10480_Y end - connect \$1 $not$libresoc.v:176261$10547_Y - connect \$3 $reduce_or$libresoc.v:176262$10548_Y + connect \$1 $not$libresoc.v:177029$10479_Y + connect \$3 $reduce_or$libresoc.v:177030$10480_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176271.1-176292.10" +attribute \src "libresoc.v:177039.1-177060.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" attribute \generator "nMigen" module \rdpick_CR_cr_c - attribute \src "libresoc.v:176286.17-176286.89" - wire $not$libresoc.v:176286$10549_Y - attribute \src "libresoc.v:176287.17-176287.89" - wire $reduce_or$libresoc.v:176287$10550_Y + attribute \src "libresoc.v:177054.17-177054.89" + wire $not$libresoc.v:177054$10481_Y + attribute \src "libresoc.v:177055.17-177055.89" + wire $reduce_or$libresoc.v:177055$10482_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -361614,37 +328157,37 @@ module \rdpick_CR_cr_c attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176286$10549 + cell $not $not$libresoc.v:177054$10481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176286$10549_Y + connect \Y $not$libresoc.v:177054$10481_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176287$10550 + cell $reduce_or $reduce_or$libresoc.v:177055$10482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176287$10550_Y + connect \Y $reduce_or$libresoc.v:177055$10482_Y end - connect \$1 $not$libresoc.v:176286$10549_Y - connect \$3 $reduce_or$libresoc.v:176287$10550_Y + connect \$1 $not$libresoc.v:177054$10481_Y + connect \$3 $reduce_or$libresoc.v:177055$10482_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176296.1-176317.10" +attribute \src "libresoc.v:177064.1-177085.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" attribute \generator "nMigen" module \rdpick_CR_full_cr - attribute \src "libresoc.v:176311.17-176311.89" - wire $not$libresoc.v:176311$10551_Y - attribute \src "libresoc.v:176312.17-176312.89" - wire $reduce_or$libresoc.v:176312$10552_Y + attribute \src "libresoc.v:177079.17-177079.89" + wire $not$libresoc.v:177079$10483_Y + attribute \src "libresoc.v:177080.17-177080.89" + wire $reduce_or$libresoc.v:177080$10484_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -361660,50 +328203,66 @@ module \rdpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176311$10551 + cell $not $not$libresoc.v:177079$10483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176311$10551_Y + connect \Y $not$libresoc.v:177079$10483_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176312$10552 + cell $reduce_or $reduce_or$libresoc.v:177080$10484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176312$10552_Y + connect \Y $reduce_or$libresoc.v:177080$10484_Y end - connect \$1 $not$libresoc.v:176311$10551_Y - connect \$3 $reduce_or$libresoc.v:176312$10552_Y + connect \$1 $not$libresoc.v:177079$10483_Y + connect \$3 $reduce_or$libresoc.v:177080$10484_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176321.1-176360.10" +attribute \src "libresoc.v:177089.1-177146.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" attribute \generator "nMigen" module \rdpick_FAST_fast1 - attribute \src "libresoc.v:176348.17-176348.91" - wire $not$libresoc.v:176348$10553_Y - attribute \src "libresoc.v:176350.17-176350.89" - wire width 3 $not$libresoc.v:176350$10555_Y - attribute \src "libresoc.v:176352.17-176352.91" - wire $not$libresoc.v:176352$10557_Y - attribute \src "libresoc.v:176349.18-176349.90" - wire $reduce_or$libresoc.v:176349$10554_Y - attribute \src "libresoc.v:176351.17-176351.103" - wire $reduce_or$libresoc.v:176351$10556_Y - attribute \src "libresoc.v:176353.17-176353.105" - wire $reduce_or$libresoc.v:176353$10558_Y + attribute \src "libresoc.v:177128.17-177128.91" + wire $not$libresoc.v:177128$10485_Y + attribute \src "libresoc.v:177130.18-177130.93" + wire $not$libresoc.v:177130$10487_Y + attribute \src "libresoc.v:177132.18-177132.93" + wire $not$libresoc.v:177132$10489_Y + attribute \src "libresoc.v:177133.17-177133.89" + wire width 5 $not$libresoc.v:177133$10490_Y + attribute \src "libresoc.v:177136.17-177136.91" + wire $not$libresoc.v:177136$10493_Y + attribute \src "libresoc.v:177129.18-177129.106" + wire $reduce_or$libresoc.v:177129$10486_Y + attribute \src "libresoc.v:177131.18-177131.106" + wire $reduce_or$libresoc.v:177131$10488_Y + attribute \src "libresoc.v:177134.18-177134.90" + wire $reduce_or$libresoc.v:177134$10491_Y + attribute \src "libresoc.v:177135.17-177135.103" + wire $reduce_or$libresoc.v:177135$10492_Y + attribute \src "libresoc.v:177137.17-177137.105" + wire $reduce_or$libresoc.v:177137$10494_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 @@ -361714,196 +328273,203 @@ module \rdpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 3 input 3 \i + wire width 5 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 3 \ni + wire width 5 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 3 output 1 \o + wire width 5 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176348$10553 + cell $not $not$libresoc.v:177128$10485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176348$10553_Y + connect \Y $not$libresoc.v:177128$10485_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176350$10555 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:177130$10487 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \i - connect \Y $not$libresoc.v:176350$10555_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:177130$10487_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176352$10557 + cell $not $not$libresoc.v:177132$10489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:176352$10557_Y + connect \A \$16 + connect \Y $not$libresoc.v:177132$10489_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176349$10554 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:177133$10490 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:176349$10554_Y + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \i + connect \Y $not$libresoc.v:177133$10490_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176351$10556 + cell $not $not$libresoc.v:177136$10493 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176351$10556_Y + connect \A \$4 + connect \Y $not$libresoc.v:177136$10493_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176353$10558 + cell $reduce_or $reduce_or$libresoc.v:177129$10486 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 4 parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176353$10558_Y - end - connect \$7 $not$libresoc.v:176348$10553_Y - connect \$11 $reduce_or$libresoc.v:176349$10554_Y - connect \$1 $not$libresoc.v:176350$10555_Y - connect \$4 $reduce_or$libresoc.v:176351$10556_Y - connect \$3 $not$libresoc.v:176352$10557_Y - connect \$8 $reduce_or$libresoc.v:176353$10558_Y - connect \en_o \$11 - connect \o { \t2 \t1 \t0 } - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "libresoc.v:176364.1-176394.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2" -attribute \generator "nMigen" -module \rdpick_FAST_fast2 - attribute \src "libresoc.v:176385.17-176385.89" - wire width 2 $not$libresoc.v:176385$10559_Y - attribute \src "libresoc.v:176387.17-176387.91" - wire $not$libresoc.v:176387$10561_Y - attribute \src "libresoc.v:176386.17-176386.103" - wire $reduce_or$libresoc.v:176386$10560_Y - attribute \src "libresoc.v:176388.17-176388.89" - wire $reduce_or$libresoc.v:176388$10562_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:177129$10486_Y + end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 2 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176385$10559 + cell $reduce_or $reduce_or$libresoc.v:177131$10488 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \i - connect \Y $not$libresoc.v:176385$10559_Y + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:177131$10488_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176387$10561 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:177134$10491 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:176387$10561_Y + connect \A \o + connect \Y $reduce_or$libresoc.v:177134$10491_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176386$10560 + cell $reduce_or $reduce_or$libresoc.v:177135$10492 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176386$10560_Y + connect \Y $reduce_or$libresoc.v:177135$10492_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176388$10562 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:177137$10494 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:176388$10562_Y - end - connect \$1 $not$libresoc.v:176385$10559_Y - connect \$4 $reduce_or$libresoc.v:176386$10560_Y - connect \$3 $not$libresoc.v:176387$10561_Y - connect \$7 $reduce_or$libresoc.v:176388$10562_Y - connect \en_o \$7 - connect \o { \t1 \t0 } + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:177137$10494_Y + end + connect \$7 $not$libresoc.v:177128$10485_Y + connect \$12 $reduce_or$libresoc.v:177129$10486_Y + connect \$11 $not$libresoc.v:177130$10487_Y + connect \$16 $reduce_or$libresoc.v:177131$10488_Y + connect \$15 $not$libresoc.v:177132$10489_Y + connect \$1 $not$libresoc.v:177133$10490_Y + connect \$19 $reduce_or$libresoc.v:177134$10491_Y + connect \$4 $reduce_or$libresoc.v:177135$10492_Y + connect \$3 $not$libresoc.v:177136$10493_Y + connect \$8 $reduce_or$libresoc.v:177137$10494_Y + connect \en_o \$19 + connect \o { \t4 \t3 \t2 \t1 \t0 } + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176398.1-176491.10" +attribute \src "libresoc.v:177150.1-177333.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra" +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rabc" attribute \generator "nMigen" -module \rdpick_INT_ra - attribute \src "libresoc.v:176461.17-176461.91" - wire $not$libresoc.v:176461$10563_Y - attribute \src "libresoc.v:176463.18-176463.93" - wire $not$libresoc.v:176463$10565_Y - attribute \src "libresoc.v:176465.18-176465.93" - wire $not$libresoc.v:176465$10567_Y - attribute \src "libresoc.v:176466.17-176466.89" - wire width 9 $not$libresoc.v:176466$10568_Y - attribute \src "libresoc.v:176468.18-176468.93" - wire $not$libresoc.v:176468$10570_Y - attribute \src "libresoc.v:176470.18-176470.93" - wire $not$libresoc.v:176470$10572_Y - attribute \src "libresoc.v:176472.18-176472.93" - wire $not$libresoc.v:176472$10574_Y - attribute \src "libresoc.v:176474.18-176474.93" - wire $not$libresoc.v:176474$10576_Y - attribute \src "libresoc.v:176477.17-176477.91" - wire $not$libresoc.v:176477$10579_Y - attribute \src "libresoc.v:176462.18-176462.106" - wire $reduce_or$libresoc.v:176462$10564_Y - attribute \src "libresoc.v:176464.18-176464.106" - wire $reduce_or$libresoc.v:176464$10566_Y - attribute \src "libresoc.v:176467.18-176467.106" - wire $reduce_or$libresoc.v:176467$10569_Y - attribute \src "libresoc.v:176469.18-176469.106" - wire $reduce_or$libresoc.v:176469$10571_Y - attribute \src "libresoc.v:176471.18-176471.106" - wire $reduce_or$libresoc.v:176471$10573_Y - attribute \src "libresoc.v:176473.18-176473.106" - wire $reduce_or$libresoc.v:176473$10575_Y - attribute \src "libresoc.v:176475.18-176475.90" - wire $reduce_or$libresoc.v:176475$10577_Y - attribute \src "libresoc.v:176476.17-176476.103" - wire $reduce_or$libresoc.v:176476$10578_Y - attribute \src "libresoc.v:176478.17-176478.105" - wire $reduce_or$libresoc.v:176478$10580_Y +module \rdpick_INT_rabc + attribute \src "libresoc.v:177273.17-177273.91" + wire $not$libresoc.v:177273$10495_Y + attribute \src "libresoc.v:177275.18-177275.93" + wire $not$libresoc.v:177275$10497_Y + attribute \src "libresoc.v:177277.18-177277.93" + wire $not$libresoc.v:177277$10499_Y + attribute \src "libresoc.v:177278.17-177278.89" + wire width 19 $not$libresoc.v:177278$10500_Y + attribute \src "libresoc.v:177280.18-177280.93" + wire $not$libresoc.v:177280$10502_Y + attribute \src "libresoc.v:177282.18-177282.93" + wire $not$libresoc.v:177282$10504_Y + attribute \src "libresoc.v:177284.18-177284.93" + wire $not$libresoc.v:177284$10506_Y + attribute \src "libresoc.v:177286.18-177286.93" + wire $not$libresoc.v:177286$10508_Y + attribute \src "libresoc.v:177288.18-177288.93" + wire $not$libresoc.v:177288$10510_Y + attribute \src "libresoc.v:177290.18-177290.93" + wire $not$libresoc.v:177290$10512_Y + attribute \src "libresoc.v:177292.18-177292.93" + wire $not$libresoc.v:177292$10514_Y + attribute \src "libresoc.v:177295.18-177295.93" + wire $not$libresoc.v:177295$10517_Y + attribute \src "libresoc.v:177297.18-177297.93" + wire $not$libresoc.v:177297$10519_Y + attribute \src "libresoc.v:177299.18-177299.93" + wire $not$libresoc.v:177299$10521_Y + attribute \src "libresoc.v:177300.17-177300.91" + wire $not$libresoc.v:177300$10522_Y + attribute \src "libresoc.v:177302.18-177302.93" + wire $not$libresoc.v:177302$10524_Y + attribute \src "libresoc.v:177304.18-177304.93" + wire $not$libresoc.v:177304$10526_Y + attribute \src "libresoc.v:177306.18-177306.93" + wire $not$libresoc.v:177306$10528_Y + attribute \src "libresoc.v:177308.18-177308.93" + wire $not$libresoc.v:177308$10530_Y + attribute \src "libresoc.v:177274.18-177274.106" + wire $reduce_or$libresoc.v:177274$10496_Y + attribute \src "libresoc.v:177276.18-177276.106" + wire $reduce_or$libresoc.v:177276$10498_Y + attribute \src "libresoc.v:177279.18-177279.106" + wire $reduce_or$libresoc.v:177279$10501_Y + attribute \src "libresoc.v:177281.18-177281.106" + wire $reduce_or$libresoc.v:177281$10503_Y + attribute \src "libresoc.v:177283.18-177283.106" + wire $reduce_or$libresoc.v:177283$10505_Y + attribute \src "libresoc.v:177285.18-177285.106" + wire $reduce_or$libresoc.v:177285$10507_Y + attribute \src "libresoc.v:177287.18-177287.106" + wire $reduce_or$libresoc.v:177287$10509_Y + attribute \src "libresoc.v:177289.18-177289.107" + wire $reduce_or$libresoc.v:177289$10511_Y + attribute \src "libresoc.v:177291.18-177291.108" + wire $reduce_or$libresoc.v:177291$10513_Y + attribute \src "libresoc.v:177293.18-177293.108" + wire $reduce_or$libresoc.v:177293$10515_Y + attribute \src "libresoc.v:177294.17-177294.103" + wire $reduce_or$libresoc.v:177294$10516_Y + attribute \src "libresoc.v:177296.18-177296.108" + wire $reduce_or$libresoc.v:177296$10518_Y + attribute \src "libresoc.v:177298.18-177298.108" + wire $reduce_or$libresoc.v:177298$10520_Y + attribute \src "libresoc.v:177301.18-177301.108" + wire $reduce_or$libresoc.v:177301$10523_Y + attribute \src "libresoc.v:177303.18-177303.108" + wire $reduce_or$libresoc.v:177303$10525_Y + attribute \src "libresoc.v:177305.18-177305.108" + wire $reduce_or$libresoc.v:177305$10527_Y + attribute \src "libresoc.v:177307.18-177307.108" + wire $reduce_or$libresoc.v:177307$10529_Y + attribute \src "libresoc.v:177309.18-177309.90" + wire $reduce_or$libresoc.v:177309$10531_Y + attribute \src "libresoc.v:177310.17-177310.105" + wire $reduce_or$libresoc.v:177310$10532_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 9 \$1 + wire width 19 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -361930,27 +328496,85 @@ module \rdpick_INT_ra wire \$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$35 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$60 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$64 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$68 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$72 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 9 input 3 \i + wire width 19 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 9 \ni + wire width 19 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 9 output 1 \o + wire width 19 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 @@ -361964,514 +328588,382 @@ module \rdpick_INT_ra wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176461$10563 + cell $not $not$libresoc.v:177273$10495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176461$10563_Y + connect \Y $not$libresoc.v:177273$10495_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176463$10565 + cell $not $not$libresoc.v:177275$10497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:176463$10565_Y + connect \Y $not$libresoc.v:177275$10497_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176465$10567 + cell $not $not$libresoc.v:177277$10499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:176465$10567_Y + connect \Y $not$libresoc.v:177277$10499_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176466$10568 + cell $not $not$libresoc.v:177278$10500 parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 9 + parameter \A_WIDTH 19 + parameter \Y_WIDTH 19 connect \A \i - connect \Y $not$libresoc.v:176466$10568_Y + connect \Y $not$libresoc.v:177278$10500_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176468$10570 + cell $not $not$libresoc.v:177280$10502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:176468$10570_Y + connect \Y $not$libresoc.v:177280$10502_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176470$10572 + cell $not $not$libresoc.v:177282$10504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:176470$10572_Y + connect \Y $not$libresoc.v:177282$10504_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176472$10574 + cell $not $not$libresoc.v:177284$10506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:176472$10574_Y + connect \Y $not$libresoc.v:177284$10506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176474$10576 + cell $not $not$libresoc.v:177286$10508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:176474$10576_Y + connect \Y $not$libresoc.v:177286$10508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176477$10579 + cell $not $not$libresoc.v:177288$10510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:176477$10579_Y + connect \A \$36 + connect \Y $not$libresoc.v:177288$10510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176462$10564 + cell $not $not$libresoc.v:177290$10512 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:176462$10564_Y + connect \A \$40 + connect \Y $not$libresoc.v:177290$10512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176464$10566 + cell $not $not$libresoc.v:177292$10514 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:176464$10566_Y + connect \A \$44 + connect \Y $not$libresoc.v:177292$10514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176467$10569 + cell $not $not$libresoc.v:177295$10517 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:176467$10569_Y + connect \A \$48 + connect \Y $not$libresoc.v:177295$10517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176469$10571 + cell $not $not$libresoc.v:177297$10519 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:176469$10571_Y + connect \A \$52 + connect \Y $not$libresoc.v:177297$10519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176471$10573 + cell $not $not$libresoc.v:177299$10521 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:176471$10573_Y + connect \A \$56 + connect \Y $not$libresoc.v:177299$10521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176473$10575 + cell $not $not$libresoc.v:177300$10522 parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 1 - connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:176473$10575_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176475$10577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:176475$10577_Y + connect \A \$4 + connect \Y $not$libresoc.v:177300$10522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176476$10578 + cell $not $not$libresoc.v:177302$10524 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176476$10578_Y + connect \A \$60 + connect \Y $not$libresoc.v:177302$10524_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176478$10580 + cell $not $not$libresoc.v:177304$10526 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176478$10580_Y - end - connect \$7 $not$libresoc.v:176461$10563_Y - connect \$12 $reduce_or$libresoc.v:176462$10564_Y - connect \$11 $not$libresoc.v:176463$10565_Y - connect \$16 $reduce_or$libresoc.v:176464$10566_Y - connect \$15 $not$libresoc.v:176465$10567_Y - connect \$1 $not$libresoc.v:176466$10568_Y - connect \$20 $reduce_or$libresoc.v:176467$10569_Y - connect \$19 $not$libresoc.v:176468$10570_Y - connect \$24 $reduce_or$libresoc.v:176469$10571_Y - connect \$23 $not$libresoc.v:176470$10572_Y - connect \$28 $reduce_or$libresoc.v:176471$10573_Y - connect \$27 $not$libresoc.v:176472$10574_Y - connect \$32 $reduce_or$libresoc.v:176473$10575_Y - connect \$31 $not$libresoc.v:176474$10576_Y - connect \$35 $reduce_or$libresoc.v:176475$10577_Y - connect \$4 $reduce_or$libresoc.v:176476$10578_Y - connect \$3 $not$libresoc.v:176477$10579_Y - connect \$8 $reduce_or$libresoc.v:176478$10580_Y - connect \en_o \$35 - connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } - connect \t8 \$31 - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "libresoc.v:176495.1-176579.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rb" -attribute \generator "nMigen" -module \rdpick_INT_rb - attribute \src "libresoc.v:176552.17-176552.91" - wire $not$libresoc.v:176552$10581_Y - attribute \src "libresoc.v:176554.18-176554.93" - wire $not$libresoc.v:176554$10583_Y - attribute \src "libresoc.v:176556.18-176556.93" - wire $not$libresoc.v:176556$10585_Y - attribute \src "libresoc.v:176557.17-176557.89" - wire width 8 $not$libresoc.v:176557$10586_Y - attribute \src "libresoc.v:176559.18-176559.93" - wire $not$libresoc.v:176559$10588_Y - attribute \src "libresoc.v:176561.18-176561.93" - wire $not$libresoc.v:176561$10590_Y - attribute \src "libresoc.v:176563.18-176563.93" - wire $not$libresoc.v:176563$10592_Y - attribute \src "libresoc.v:176566.17-176566.91" - wire $not$libresoc.v:176566$10595_Y - attribute \src "libresoc.v:176553.18-176553.106" - wire $reduce_or$libresoc.v:176553$10582_Y - attribute \src "libresoc.v:176555.18-176555.106" - wire $reduce_or$libresoc.v:176555$10584_Y - attribute \src "libresoc.v:176558.18-176558.106" - wire $reduce_or$libresoc.v:176558$10587_Y - attribute \src "libresoc.v:176560.18-176560.106" - wire $reduce_or$libresoc.v:176560$10589_Y - attribute \src "libresoc.v:176562.18-176562.106" - wire $reduce_or$libresoc.v:176562$10591_Y - attribute \src "libresoc.v:176564.18-176564.90" - wire $reduce_or$libresoc.v:176564$10593_Y - attribute \src "libresoc.v:176565.17-176565.103" - wire $reduce_or$libresoc.v:176565$10594_Y - attribute \src "libresoc.v:176567.17-176567.105" - wire $reduce_or$libresoc.v:176567$10596_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 + connect \A \$64 + connect \Y $not$libresoc.v:177304$10526_Y + end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176552$10581 + cell $not $not$libresoc.v:177306$10528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:176552$10581_Y + connect \A \$68 + connect \Y $not$libresoc.v:177306$10528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176554$10583 + cell $not $not$libresoc.v:177308$10530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:176554$10583_Y + connect \A \$72 + connect \Y $not$libresoc.v:177308$10530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176556$10585 + cell $reduce_or $reduce_or$libresoc.v:177274$10496 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:176556$10585_Y + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:177274$10496_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176557$10586 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:177276$10498 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \i - connect \Y $not$libresoc.v:176557$10586_Y + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:177276$10498_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176559$10588 + cell $reduce_or $reduce_or$libresoc.v:177279$10501 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:176559$10588_Y + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:177279$10501_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176561$10590 + cell $reduce_or $reduce_or$libresoc.v:177281$10503 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:176561$10590_Y + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$libresoc.v:177281$10503_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176563$10592 + cell $reduce_or $reduce_or$libresoc.v:177283$10505 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 8 parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:176563$10592_Y + connect \A { \i [6:0] \ni [7] } + connect \Y $reduce_or$libresoc.v:177283$10505_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176566$10595 + cell $reduce_or $reduce_or$libresoc.v:177285$10507 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 9 parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:176566$10595_Y + connect \A { \i [7:0] \ni [8] } + connect \Y $reduce_or$libresoc.v:177285$10507_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176553$10582 + cell $reduce_or $reduce_or$libresoc.v:177287$10509 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 10 parameter \Y_WIDTH 1 - connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:176553$10582_Y + connect \A { \i [8:0] \ni [9] } + connect \Y $reduce_or$libresoc.v:177287$10509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176555$10584 + cell $reduce_or $reduce_or$libresoc.v:177289$10511 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:176555$10584_Y + connect \A { \i [9:0] \ni [10] } + connect \Y $reduce_or$libresoc.v:177289$10511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176558$10587 + cell $reduce_or $reduce_or$libresoc.v:177291$10513 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 12 parameter \Y_WIDTH 1 - connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:176558$10587_Y + connect \A { \i [10:0] \ni [11] } + connect \Y $reduce_or$libresoc.v:177291$10513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176560$10589 + cell $reduce_or $reduce_or$libresoc.v:177293$10515 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 13 parameter \Y_WIDTH 1 - connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:176560$10589_Y + connect \A { \i [11:0] \ni [12] } + connect \Y $reduce_or$libresoc.v:177293$10515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176562$10591 + cell $reduce_or $reduce_or$libresoc.v:177294$10516 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 2 parameter \Y_WIDTH 1 - connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:176562$10591_Y + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:177294$10516_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176564$10593 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:177296$10518 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:176564$10593_Y + connect \A { \i [12:0] \ni [13] } + connect \Y $reduce_or$libresoc.v:177296$10518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176565$10594 + cell $reduce_or $reduce_or$libresoc.v:177298$10520 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 15 parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176565$10594_Y + connect \A { \i [13:0] \ni [14] } + connect \Y $reduce_or$libresoc.v:177298$10520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176567$10596 + cell $reduce_or $reduce_or$libresoc.v:177301$10523 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 16 parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176567$10596_Y - end - connect \$7 $not$libresoc.v:176552$10581_Y - connect \$12 $reduce_or$libresoc.v:176553$10582_Y - connect \$11 $not$libresoc.v:176554$10583_Y - connect \$16 $reduce_or$libresoc.v:176555$10584_Y - connect \$15 $not$libresoc.v:176556$10585_Y - connect \$1 $not$libresoc.v:176557$10586_Y - connect \$20 $reduce_or$libresoc.v:176558$10587_Y - connect \$19 $not$libresoc.v:176559$10588_Y - connect \$24 $reduce_or$libresoc.v:176560$10589_Y - connect \$23 $not$libresoc.v:176561$10590_Y - connect \$28 $reduce_or$libresoc.v:176562$10591_Y - connect \$27 $not$libresoc.v:176563$10592_Y - connect \$31 $reduce_or$libresoc.v:176564$10593_Y - connect \$4 $reduce_or$libresoc.v:176565$10594_Y - connect \$3 $not$libresoc.v:176566$10595_Y - connect \$8 $reduce_or$libresoc.v:176567$10596_Y - connect \en_o \$31 - connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "libresoc.v:176583.1-176613.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc" -attribute \generator "nMigen" -module \rdpick_INT_rc - attribute \src "libresoc.v:176604.17-176604.89" - wire width 2 $not$libresoc.v:176604$10597_Y - attribute \src "libresoc.v:176606.17-176606.91" - wire $not$libresoc.v:176606$10599_Y - attribute \src "libresoc.v:176605.17-176605.103" - wire $reduce_or$libresoc.v:176605$10598_Y - attribute \src "libresoc.v:176607.17-176607.89" - wire $reduce_or$libresoc.v:176607$10600_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 + connect \A { \i [14:0] \ni [15] } + connect \Y $reduce_or$libresoc.v:177301$10523_Y + end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 2 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176604$10597 + cell $reduce_or $reduce_or$libresoc.v:177303$10525 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \i - connect \Y $not$libresoc.v:176604$10597_Y + parameter \A_WIDTH 17 + parameter \Y_WIDTH 1 + connect \A { \i [15:0] \ni [16] } + connect \Y $reduce_or$libresoc.v:177303$10525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176606$10599 + cell $reduce_or $reduce_or$libresoc.v:177305$10527 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 18 parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:176606$10599_Y + connect \A { \i [16:0] \ni [17] } + connect \Y $reduce_or$libresoc.v:177305$10527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176605$10598 + cell $reduce_or $reduce_or$libresoc.v:177307$10529 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 19 parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176605$10598_Y + connect \A { \i [17:0] \ni [18] } + connect \Y $reduce_or$libresoc.v:177307$10529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176607$10600 + cell $reduce_or $reduce_or$libresoc.v:177309$10531 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 19 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176607$10600_Y + connect \Y $reduce_or$libresoc.v:177309$10531_Y end - connect \$1 $not$libresoc.v:176604$10597_Y - connect \$4 $reduce_or$libresoc.v:176605$10598_Y - connect \$3 $not$libresoc.v:176606$10599_Y - connect \$7 $reduce_or$libresoc.v:176607$10600_Y - connect \en_o \$7 - connect \o { \t1 \t0 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:177310$10532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:177310$10532_Y + end + connect \$7 $not$libresoc.v:177273$10495_Y + connect \$12 $reduce_or$libresoc.v:177274$10496_Y + connect \$11 $not$libresoc.v:177275$10497_Y + connect \$16 $reduce_or$libresoc.v:177276$10498_Y + connect \$15 $not$libresoc.v:177277$10499_Y + connect \$1 $not$libresoc.v:177278$10500_Y + connect \$20 $reduce_or$libresoc.v:177279$10501_Y + connect \$19 $not$libresoc.v:177280$10502_Y + connect \$24 $reduce_or$libresoc.v:177281$10503_Y + connect \$23 $not$libresoc.v:177282$10504_Y + connect \$28 $reduce_or$libresoc.v:177283$10505_Y + connect \$27 $not$libresoc.v:177284$10506_Y + connect \$32 $reduce_or$libresoc.v:177285$10507_Y + connect \$31 $not$libresoc.v:177286$10508_Y + connect \$36 $reduce_or$libresoc.v:177287$10509_Y + connect \$35 $not$libresoc.v:177288$10510_Y + connect \$40 $reduce_or$libresoc.v:177289$10511_Y + connect \$39 $not$libresoc.v:177290$10512_Y + connect \$44 $reduce_or$libresoc.v:177291$10513_Y + connect \$43 $not$libresoc.v:177292$10514_Y + connect \$48 $reduce_or$libresoc.v:177293$10515_Y + connect \$4 $reduce_or$libresoc.v:177294$10516_Y + connect \$47 $not$libresoc.v:177295$10517_Y + connect \$52 $reduce_or$libresoc.v:177296$10518_Y + connect \$51 $not$libresoc.v:177297$10519_Y + connect \$56 $reduce_or$libresoc.v:177298$10520_Y + connect \$55 $not$libresoc.v:177299$10521_Y + connect \$3 $not$libresoc.v:177300$10522_Y + connect \$60 $reduce_or$libresoc.v:177301$10523_Y + connect \$59 $not$libresoc.v:177302$10524_Y + connect \$64 $reduce_or$libresoc.v:177303$10525_Y + connect \$63 $not$libresoc.v:177304$10526_Y + connect \$68 $reduce_or$libresoc.v:177305$10527_Y + connect \$67 $not$libresoc.v:177306$10528_Y + connect \$72 $reduce_or$libresoc.v:177307$10529_Y + connect \$71 $not$libresoc.v:177308$10530_Y + connect \$75 $reduce_or$libresoc.v:177309$10531_Y + connect \$8 $reduce_or$libresoc.v:177310$10532_Y + connect \en_o \$75 + connect \o { \t18 \t17 \t16 \t15 \t14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t18 \$71 + connect \t17 \$67 + connect \t16 \$63 + connect \t15 \$59 + connect \t14 \$55 + connect \t13 \$51 + connect \t12 \$47 + connect \t11 \$43 + connect \t10 \$39 + connect \t9 \$35 + connect \t8 \$31 + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176617.1-176638.10" +attribute \src "libresoc.v:177337.1-177358.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1" attribute \generator "nMigen" module \rdpick_SPR_spr1 - attribute \src "libresoc.v:176632.17-176632.89" - wire $not$libresoc.v:176632$10601_Y - attribute \src "libresoc.v:176633.17-176633.89" - wire $reduce_or$libresoc.v:176633$10602_Y + attribute \src "libresoc.v:177352.17-177352.89" + wire $not$libresoc.v:177352$10533_Y + attribute \src "libresoc.v:177353.17-177353.89" + wire $reduce_or$libresoc.v:177353$10534_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -362487,45 +328979,45 @@ module \rdpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176632$10601 + cell $not $not$libresoc.v:177352$10533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176632$10601_Y + connect \Y $not$libresoc.v:177352$10533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176633$10602 + cell $reduce_or $reduce_or$libresoc.v:177353$10534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176633$10602_Y + connect \Y $reduce_or$libresoc.v:177353$10534_Y end - connect \$1 $not$libresoc.v:176632$10601_Y - connect \$3 $reduce_or$libresoc.v:176633$10602_Y + connect \$1 $not$libresoc.v:177352$10533_Y + connect \$3 $reduce_or$libresoc.v:177353$10534_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176642.1-176681.10" +attribute \src "libresoc.v:177362.1-177401.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca" attribute \generator "nMigen" module \rdpick_XER_xer_ca - attribute \src "libresoc.v:176669.17-176669.91" - wire $not$libresoc.v:176669$10603_Y - attribute \src "libresoc.v:176671.17-176671.89" - wire width 3 $not$libresoc.v:176671$10605_Y - attribute \src "libresoc.v:176673.17-176673.91" - wire $not$libresoc.v:176673$10607_Y - attribute \src "libresoc.v:176670.18-176670.90" - wire $reduce_or$libresoc.v:176670$10604_Y - attribute \src "libresoc.v:176672.17-176672.103" - wire $reduce_or$libresoc.v:176672$10606_Y - attribute \src "libresoc.v:176674.17-176674.105" - wire $reduce_or$libresoc.v:176674$10608_Y + attribute \src "libresoc.v:177389.17-177389.91" + wire $not$libresoc.v:177389$10535_Y + attribute \src "libresoc.v:177391.17-177391.89" + wire width 3 $not$libresoc.v:177391$10537_Y + attribute \src "libresoc.v:177393.17-177393.91" + wire $not$libresoc.v:177393$10539_Y + attribute \src "libresoc.v:177390.18-177390.90" + wire $reduce_or$libresoc.v:177390$10536_Y + attribute \src "libresoc.v:177392.17-177392.103" + wire $reduce_or$libresoc.v:177392$10538_Y + attribute \src "libresoc.v:177394.17-177394.105" + wire $reduce_or$libresoc.v:177394$10540_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -362553,59 +329045,59 @@ module \rdpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176669$10603 + cell $not $not$libresoc.v:177389$10535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176669$10603_Y + connect \Y $not$libresoc.v:177389$10535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176671$10605 + cell $not $not$libresoc.v:177391$10537 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:176671$10605_Y + connect \Y $not$libresoc.v:177391$10537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176673$10607 + cell $not $not$libresoc.v:177393$10539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176673$10607_Y + connect \Y $not$libresoc.v:177393$10539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176670$10604 + cell $reduce_or $reduce_or$libresoc.v:177390$10536 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176670$10604_Y + connect \Y $reduce_or$libresoc.v:177390$10536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176672$10606 + cell $reduce_or $reduce_or$libresoc.v:177392$10538 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176672$10606_Y + connect \Y $reduce_or$libresoc.v:177392$10538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176674$10608 + cell $reduce_or $reduce_or$libresoc.v:177394$10540 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176674$10608_Y - end - connect \$7 $not$libresoc.v:176669$10603_Y - connect \$11 $reduce_or$libresoc.v:176670$10604_Y - connect \$1 $not$libresoc.v:176671$10605_Y - connect \$4 $reduce_or$libresoc.v:176672$10606_Y - connect \$3 $not$libresoc.v:176673$10607_Y - connect \$8 $reduce_or$libresoc.v:176674$10608_Y + connect \Y $reduce_or$libresoc.v:177394$10540_Y + end + connect \$7 $not$libresoc.v:177389$10535_Y + connect \$11 $reduce_or$libresoc.v:177390$10536_Y + connect \$1 $not$libresoc.v:177391$10537_Y + connect \$4 $reduce_or$libresoc.v:177392$10538_Y + connect \$3 $not$libresoc.v:177393$10539_Y + connect \$8 $reduce_or$libresoc.v:177394$10540_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -362613,15 +329105,15 @@ module \rdpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176685.1-176706.10" +attribute \src "libresoc.v:177405.1-177426.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov" attribute \generator "nMigen" module \rdpick_XER_xer_ov - attribute \src "libresoc.v:176700.17-176700.89" - wire $not$libresoc.v:176700$10609_Y - attribute \src "libresoc.v:176701.17-176701.89" - wire $reduce_or$libresoc.v:176701$10610_Y + attribute \src "libresoc.v:177420.17-177420.89" + wire $not$libresoc.v:177420$10541_Y + attribute \src "libresoc.v:177421.17-177421.89" + wire $reduce_or$libresoc.v:177421$10542_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -362637,57 +329129,57 @@ module \rdpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176700$10609 + cell $not $not$libresoc.v:177420$10541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176700$10609_Y + connect \Y $not$libresoc.v:177420$10541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176701$10610 + cell $reduce_or $reduce_or$libresoc.v:177421$10542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176701$10610_Y + connect \Y $reduce_or$libresoc.v:177421$10542_Y end - connect \$1 $not$libresoc.v:176700$10609_Y - connect \$3 $reduce_or$libresoc.v:176701$10610_Y + connect \$1 $not$libresoc.v:177420$10541_Y + connect \$3 $reduce_or$libresoc.v:177421$10542_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176710.1-176776.10" +attribute \src "libresoc.v:177430.1-177496.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" attribute \generator "nMigen" module \rdpick_XER_xer_so - attribute \src "libresoc.v:176755.17-176755.91" - wire $not$libresoc.v:176755$10611_Y - attribute \src "libresoc.v:176757.18-176757.93" - wire $not$libresoc.v:176757$10613_Y - attribute \src "libresoc.v:176759.18-176759.93" - wire $not$libresoc.v:176759$10615_Y - attribute \src "libresoc.v:176760.17-176760.89" - wire width 6 $not$libresoc.v:176760$10616_Y - attribute \src "libresoc.v:176762.18-176762.93" - wire $not$libresoc.v:176762$10618_Y - attribute \src "libresoc.v:176765.17-176765.91" - wire $not$libresoc.v:176765$10621_Y - attribute \src "libresoc.v:176756.18-176756.106" - wire $reduce_or$libresoc.v:176756$10612_Y - attribute \src "libresoc.v:176758.18-176758.106" - wire $reduce_or$libresoc.v:176758$10614_Y - attribute \src "libresoc.v:176761.18-176761.106" - wire $reduce_or$libresoc.v:176761$10617_Y - attribute \src "libresoc.v:176763.18-176763.90" - wire $reduce_or$libresoc.v:176763$10619_Y - attribute \src "libresoc.v:176764.17-176764.103" - wire $reduce_or$libresoc.v:176764$10620_Y - attribute \src "libresoc.v:176766.17-176766.105" - wire $reduce_or$libresoc.v:176766$10622_Y + attribute \src "libresoc.v:177475.17-177475.91" + wire $not$libresoc.v:177475$10543_Y + attribute \src "libresoc.v:177477.18-177477.93" + wire $not$libresoc.v:177477$10545_Y + attribute \src "libresoc.v:177479.18-177479.93" + wire $not$libresoc.v:177479$10547_Y + attribute \src "libresoc.v:177480.17-177480.89" + wire width 6 $not$libresoc.v:177480$10548_Y + attribute \src "libresoc.v:177482.18-177482.93" + wire $not$libresoc.v:177482$10550_Y + attribute \src "libresoc.v:177485.17-177485.91" + wire $not$libresoc.v:177485$10553_Y + attribute \src "libresoc.v:177476.18-177476.106" + wire $reduce_or$libresoc.v:177476$10544_Y + attribute \src "libresoc.v:177478.18-177478.106" + wire $reduce_or$libresoc.v:177478$10546_Y + attribute \src "libresoc.v:177481.18-177481.106" + wire $reduce_or$libresoc.v:177481$10549_Y + attribute \src "libresoc.v:177483.18-177483.90" + wire $reduce_or$libresoc.v:177483$10551_Y + attribute \src "libresoc.v:177484.17-177484.103" + wire $reduce_or$libresoc.v:177484$10552_Y + attribute \src "libresoc.v:177486.17-177486.105" + wire $reduce_or$libresoc.v:177486$10554_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -362733,113 +329225,113 @@ module \rdpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176755$10611 + cell $not $not$libresoc.v:177475$10543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176755$10611_Y + connect \Y $not$libresoc.v:177475$10543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176757$10613 + cell $not $not$libresoc.v:177477$10545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:176757$10613_Y + connect \Y $not$libresoc.v:177477$10545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176759$10615 + cell $not $not$libresoc.v:177479$10547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:176759$10615_Y + connect \Y $not$libresoc.v:177479$10547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176760$10616 + cell $not $not$libresoc.v:177480$10548 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:176760$10616_Y + connect \Y $not$libresoc.v:177480$10548_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176762$10618 + cell $not $not$libresoc.v:177482$10550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:176762$10618_Y + connect \Y $not$libresoc.v:177482$10550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176765$10621 + cell $not $not$libresoc.v:177485$10553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176765$10621_Y + connect \Y $not$libresoc.v:177485$10553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176756$10612 + cell $reduce_or $reduce_or$libresoc.v:177476$10544 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:176756$10612_Y + connect \Y $reduce_or$libresoc.v:177476$10544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176758$10614 + cell $reduce_or $reduce_or$libresoc.v:177478$10546 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:176758$10614_Y + connect \Y $reduce_or$libresoc.v:177478$10546_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176761$10617 + cell $reduce_or $reduce_or$libresoc.v:177481$10549 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:176761$10617_Y + connect \Y $reduce_or$libresoc.v:177481$10549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176763$10619 + cell $reduce_or $reduce_or$libresoc.v:177483$10551 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176763$10619_Y + connect \Y $reduce_or$libresoc.v:177483$10551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176764$10620 + cell $reduce_or $reduce_or$libresoc.v:177484$10552 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176764$10620_Y + connect \Y $reduce_or$libresoc.v:177484$10552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176766$10622 + cell $reduce_or $reduce_or$libresoc.v:177486$10554 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176766$10622_Y - end - connect \$7 $not$libresoc.v:176755$10611_Y - connect \$12 $reduce_or$libresoc.v:176756$10612_Y - connect \$11 $not$libresoc.v:176757$10613_Y - connect \$16 $reduce_or$libresoc.v:176758$10614_Y - connect \$15 $not$libresoc.v:176759$10615_Y - connect \$1 $not$libresoc.v:176760$10616_Y - connect \$20 $reduce_or$libresoc.v:176761$10617_Y - connect \$19 $not$libresoc.v:176762$10618_Y - connect \$23 $reduce_or$libresoc.v:176763$10619_Y - connect \$4 $reduce_or$libresoc.v:176764$10620_Y - connect \$3 $not$libresoc.v:176765$10621_Y - connect \$8 $reduce_or$libresoc.v:176766$10622_Y + connect \Y $reduce_or$libresoc.v:177486$10554_Y + end + connect \$7 $not$libresoc.v:177475$10543_Y + connect \$12 $reduce_or$libresoc.v:177476$10544_Y + connect \$11 $not$libresoc.v:177477$10545_Y + connect \$16 $reduce_or$libresoc.v:177478$10546_Y + connect \$15 $not$libresoc.v:177479$10547_Y + connect \$1 $not$libresoc.v:177480$10548_Y + connect \$20 $reduce_or$libresoc.v:177481$10549_Y + connect \$19 $not$libresoc.v:177482$10550_Y + connect \$23 $reduce_or$libresoc.v:177483$10551_Y + connect \$4 $reduce_or$libresoc.v:177484$10552_Y + connect \$3 $not$libresoc.v:177485$10553_Y + connect \$8 $reduce_or$libresoc.v:177486$10554_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -362850,277 +329342,239 @@ module \rdpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176780.1-177335.10" +attribute \src "libresoc.v:177500.1-177971.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0" attribute \generator "nMigen" module \reg_0 - attribute \src "libresoc.v:176888.3-176927.6" - wire width 4 $0\cr_pred0__data_o$next[3:0]$10637 - attribute \src "libresoc.v:176886.3-176887.49" - wire width 4 $0\cr_pred0__data_o[3:0] - attribute \src "libresoc.v:176781.7-176781.20" + attribute \src "libresoc.v:177501.7-177501.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177265.3-177304.6" - wire width 4 $0\r0__data_o$next[3:0]$10708 - attribute \src "libresoc.v:176878.3-176879.37" + attribute \src "libresoc.v:177831.3-177870.6" + wire width 4 $0\r0__data_o$next[3:0]$10610 + attribute \src "libresoc.v:177586.3-177587.37" wire width 4 $0\r0__data_o[3:0] - attribute \src "libresoc.v:176958.3-176997.6" - wire width 4 $0\r20__data_o$next[3:0]$10646 - attribute \src "libresoc.v:176876.3-176877.39" + attribute \src "libresoc.v:177901.3-177940.6" + wire width 4 $0\r20__data_o$next[3:0]$10624 + attribute \src "libresoc.v:177584.3-177585.39" wire width 4 $0\r20__data_o[3:0] - attribute \src "libresoc.v:177028.3-177054.6" - wire width 4 $0\reg$next[3:0]$10660 - attribute \src "libresoc.v:176874.3-176875.25" + attribute \src "libresoc.v:177664.3-177690.6" + wire width 4 $0\reg$next[3:0]$10576 + attribute \src "libresoc.v:177582.3-177583.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:177055.3-177094.6" - wire width 4 $0\src10__data_o$next[3:0]$10666 - attribute \src "libresoc.v:176884.3-176885.43" + attribute \src "libresoc.v:177594.3-177633.6" + wire width 4 $0\src10__data_o$next[3:0]$10567 + attribute \src "libresoc.v:177592.3-177593.43" wire width 4 $0\src10__data_o[3:0] - attribute \src "libresoc.v:177125.3-177164.6" - wire width 4 $0\src20__data_o$next[3:0]$10680 - attribute \src "libresoc.v:176882.3-176883.43" + attribute \src "libresoc.v:177691.3-177730.6" + wire width 4 $0\src20__data_o$next[3:0]$10582 + attribute \src "libresoc.v:177590.3-177591.43" wire width 4 $0\src20__data_o[3:0] - attribute \src "libresoc.v:177195.3-177234.6" - wire width 4 $0\src30__data_o$next[3:0]$10694 - attribute \src "libresoc.v:176880.3-176881.43" + attribute \src "libresoc.v:177761.3-177800.6" + wire width 4 $0\src30__data_o$next[3:0]$10596 + attribute \src "libresoc.v:177588.3-177589.43" wire width 4 $0\src30__data_o[3:0] - attribute \src "libresoc.v:177235.3-177264.6" - wire $0\wr_detect$10[0:0]$10702 - attribute \src "libresoc.v:177305.3-177334.6" - wire $0\wr_detect$13[0:0]$10716 - attribute \src "libresoc.v:176998.3-177027.6" - wire $0\wr_detect$16[0:0]$10654 - attribute \src "libresoc.v:177095.3-177124.6" - wire $0\wr_detect$4[0:0]$10674 - attribute \src "libresoc.v:177165.3-177194.6" - wire $0\wr_detect$7[0:0]$10688 - attribute \src "libresoc.v:176928.3-176957.6" + attribute \src "libresoc.v:177871.3-177900.6" + wire $0\wr_detect$10[0:0]$10618 + attribute \src "libresoc.v:177941.3-177970.6" + wire $0\wr_detect$13[0:0]$10632 + attribute \src "libresoc.v:177731.3-177760.6" + wire $0\wr_detect$4[0:0]$10590 + attribute \src "libresoc.v:177801.3-177830.6" + wire $0\wr_detect$7[0:0]$10604 + attribute \src "libresoc.v:177634.3-177663.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:176888.3-176927.6" - wire width 4 $1\cr_pred0__data_o$next[3:0]$10638 - attribute \src "libresoc.v:176800.13-176800.36" - wire width 4 $1\cr_pred0__data_o[3:0] - attribute \src "libresoc.v:177265.3-177304.6" - wire width 4 $1\r0__data_o$next[3:0]$10709 - attribute \src "libresoc.v:176815.13-176815.30" + attribute \src "libresoc.v:177831.3-177870.6" + wire width 4 $1\r0__data_o$next[3:0]$10611 + attribute \src "libresoc.v:177526.13-177526.30" wire width 4 $1\r0__data_o[3:0] - attribute \src "libresoc.v:176958.3-176997.6" - wire width 4 $1\r20__data_o$next[3:0]$10647 - attribute \src "libresoc.v:176822.13-176822.31" + attribute \src "libresoc.v:177901.3-177940.6" + wire width 4 $1\r20__data_o$next[3:0]$10625 + attribute \src "libresoc.v:177533.13-177533.31" wire width 4 $1\r20__data_o[3:0] - attribute \src "libresoc.v:177028.3-177054.6" - wire width 4 $1\reg$next[3:0]$10661 - attribute \src "libresoc.v:176828.13-176828.25" + attribute \src "libresoc.v:177664.3-177690.6" + wire width 4 $1\reg$next[3:0]$10577 + attribute \src "libresoc.v:177539.13-177539.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:177055.3-177094.6" - wire width 4 $1\src10__data_o$next[3:0]$10667 - attribute \src "libresoc.v:176833.13-176833.33" + attribute \src "libresoc.v:177594.3-177633.6" + wire width 4 $1\src10__data_o$next[3:0]$10568 + attribute \src "libresoc.v:177544.13-177544.33" wire width 4 $1\src10__data_o[3:0] - attribute \src "libresoc.v:177125.3-177164.6" - wire width 4 $1\src20__data_o$next[3:0]$10681 - attribute \src "libresoc.v:176840.13-176840.33" + attribute \src "libresoc.v:177691.3-177730.6" + wire width 4 $1\src20__data_o$next[3:0]$10583 + attribute \src "libresoc.v:177551.13-177551.33" wire width 4 $1\src20__data_o[3:0] - attribute \src "libresoc.v:177195.3-177234.6" - wire width 4 $1\src30__data_o$next[3:0]$10695 - attribute \src "libresoc.v:176847.13-176847.33" + attribute \src "libresoc.v:177761.3-177800.6" + wire width 4 $1\src30__data_o$next[3:0]$10597 + attribute \src "libresoc.v:177558.13-177558.33" wire width 4 $1\src30__data_o[3:0] - attribute \src "libresoc.v:177235.3-177264.6" - wire $1\wr_detect$10[0:0]$10703 - attribute \src "libresoc.v:177305.3-177334.6" - wire $1\wr_detect$13[0:0]$10717 - attribute \src "libresoc.v:176998.3-177027.6" - wire $1\wr_detect$16[0:0]$10655 - attribute \src "libresoc.v:177095.3-177124.6" - wire $1\wr_detect$4[0:0]$10675 - attribute \src "libresoc.v:177165.3-177194.6" - wire $1\wr_detect$7[0:0]$10689 - attribute \src "libresoc.v:176928.3-176957.6" + attribute \src "libresoc.v:177871.3-177900.6" + wire $1\wr_detect$10[0:0]$10619 + attribute \src "libresoc.v:177941.3-177970.6" + wire $1\wr_detect$13[0:0]$10633 + attribute \src "libresoc.v:177731.3-177760.6" + wire $1\wr_detect$4[0:0]$10591 + attribute \src "libresoc.v:177801.3-177830.6" + wire $1\wr_detect$7[0:0]$10605 + attribute \src "libresoc.v:177634.3-177663.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:176888.3-176927.6" - wire width 4 $2\cr_pred0__data_o$next[3:0]$10639 - attribute \src "libresoc.v:177265.3-177304.6" - wire width 4 $2\r0__data_o$next[3:0]$10710 - attribute \src "libresoc.v:176958.3-176997.6" - wire width 4 $2\r20__data_o$next[3:0]$10648 - attribute \src "libresoc.v:177028.3-177054.6" - wire width 4 $2\reg$next[3:0]$10662 - attribute \src "libresoc.v:177055.3-177094.6" - wire width 4 $2\src10__data_o$next[3:0]$10668 - attribute \src "libresoc.v:177125.3-177164.6" - wire width 4 $2\src20__data_o$next[3:0]$10682 - attribute \src "libresoc.v:177195.3-177234.6" - wire width 4 $2\src30__data_o$next[3:0]$10696 - attribute \src "libresoc.v:177235.3-177264.6" - wire $2\wr_detect$10[0:0]$10704 - attribute \src "libresoc.v:177305.3-177334.6" - wire $2\wr_detect$13[0:0]$10718 - attribute \src "libresoc.v:176998.3-177027.6" - wire $2\wr_detect$16[0:0]$10656 - attribute \src "libresoc.v:177095.3-177124.6" - wire $2\wr_detect$4[0:0]$10676 - attribute \src "libresoc.v:177165.3-177194.6" - wire $2\wr_detect$7[0:0]$10690 - attribute \src "libresoc.v:176928.3-176957.6" + attribute \src "libresoc.v:177831.3-177870.6" + wire width 4 $2\r0__data_o$next[3:0]$10612 + attribute \src "libresoc.v:177901.3-177940.6" + wire width 4 $2\r20__data_o$next[3:0]$10626 + attribute \src "libresoc.v:177664.3-177690.6" + wire width 4 $2\reg$next[3:0]$10578 + attribute \src "libresoc.v:177594.3-177633.6" + wire width 4 $2\src10__data_o$next[3:0]$10569 + attribute \src "libresoc.v:177691.3-177730.6" + wire width 4 $2\src20__data_o$next[3:0]$10584 + attribute \src "libresoc.v:177761.3-177800.6" + wire width 4 $2\src30__data_o$next[3:0]$10598 + attribute \src "libresoc.v:177871.3-177900.6" + wire $2\wr_detect$10[0:0]$10620 + attribute \src "libresoc.v:177941.3-177970.6" + wire $2\wr_detect$13[0:0]$10634 + attribute \src "libresoc.v:177731.3-177760.6" + wire $2\wr_detect$4[0:0]$10592 + attribute \src "libresoc.v:177801.3-177830.6" + wire $2\wr_detect$7[0:0]$10606 + attribute \src "libresoc.v:177634.3-177663.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:176888.3-176927.6" - wire width 4 $3\cr_pred0__data_o$next[3:0]$10640 - attribute \src "libresoc.v:177265.3-177304.6" - wire width 4 $3\r0__data_o$next[3:0]$10711 - attribute \src "libresoc.v:176958.3-176997.6" - wire width 4 $3\r20__data_o$next[3:0]$10649 - attribute \src "libresoc.v:177028.3-177054.6" - wire width 4 $3\reg$next[3:0]$10663 - attribute \src "libresoc.v:177055.3-177094.6" - wire width 4 $3\src10__data_o$next[3:0]$10669 - attribute \src "libresoc.v:177125.3-177164.6" - wire width 4 $3\src20__data_o$next[3:0]$10683 - attribute \src "libresoc.v:177195.3-177234.6" - wire width 4 $3\src30__data_o$next[3:0]$10697 - attribute \src "libresoc.v:177235.3-177264.6" - wire $3\wr_detect$10[0:0]$10705 - attribute \src "libresoc.v:177305.3-177334.6" - wire $3\wr_detect$13[0:0]$10719 - attribute \src "libresoc.v:176998.3-177027.6" - wire $3\wr_detect$16[0:0]$10657 - attribute \src "libresoc.v:177095.3-177124.6" - wire $3\wr_detect$4[0:0]$10677 - attribute \src "libresoc.v:177165.3-177194.6" - wire $3\wr_detect$7[0:0]$10691 - attribute \src "libresoc.v:176928.3-176957.6" + attribute \src "libresoc.v:177831.3-177870.6" + wire width 4 $3\r0__data_o$next[3:0]$10613 + attribute \src "libresoc.v:177901.3-177940.6" + wire width 4 $3\r20__data_o$next[3:0]$10627 + attribute \src "libresoc.v:177664.3-177690.6" + wire width 4 $3\reg$next[3:0]$10579 + attribute \src "libresoc.v:177594.3-177633.6" + wire width 4 $3\src10__data_o$next[3:0]$10570 + attribute \src "libresoc.v:177691.3-177730.6" + wire width 4 $3\src20__data_o$next[3:0]$10585 + attribute \src "libresoc.v:177761.3-177800.6" + wire width 4 $3\src30__data_o$next[3:0]$10599 + attribute \src "libresoc.v:177871.3-177900.6" + wire $3\wr_detect$10[0:0]$10621 + attribute \src "libresoc.v:177941.3-177970.6" + wire $3\wr_detect$13[0:0]$10635 + attribute \src "libresoc.v:177731.3-177760.6" + wire $3\wr_detect$4[0:0]$10593 + attribute \src "libresoc.v:177801.3-177830.6" + wire $3\wr_detect$7[0:0]$10607 + attribute \src "libresoc.v:177634.3-177663.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:176888.3-176927.6" - wire width 4 $4\cr_pred0__data_o$next[3:0]$10641 - attribute \src "libresoc.v:177265.3-177304.6" - wire width 4 $4\r0__data_o$next[3:0]$10712 - attribute \src "libresoc.v:176958.3-176997.6" - wire width 4 $4\r20__data_o$next[3:0]$10650 - attribute \src "libresoc.v:177028.3-177054.6" - wire width 4 $4\reg$next[3:0]$10664 - attribute \src "libresoc.v:177055.3-177094.6" - wire width 4 $4\src10__data_o$next[3:0]$10670 - attribute \src "libresoc.v:177125.3-177164.6" - wire width 4 $4\src20__data_o$next[3:0]$10684 - attribute \src "libresoc.v:177195.3-177234.6" - wire width 4 $4\src30__data_o$next[3:0]$10698 - attribute \src "libresoc.v:177235.3-177264.6" - wire $4\wr_detect$10[0:0]$10706 - attribute \src "libresoc.v:177305.3-177334.6" - wire $4\wr_detect$13[0:0]$10720 - attribute \src "libresoc.v:176998.3-177027.6" - wire $4\wr_detect$16[0:0]$10658 - attribute \src "libresoc.v:177095.3-177124.6" - wire $4\wr_detect$4[0:0]$10678 - attribute \src "libresoc.v:177165.3-177194.6" - wire $4\wr_detect$7[0:0]$10692 - attribute \src "libresoc.v:176928.3-176957.6" + attribute \src "libresoc.v:177831.3-177870.6" + wire width 4 $4\r0__data_o$next[3:0]$10614 + attribute \src "libresoc.v:177901.3-177940.6" + wire width 4 $4\r20__data_o$next[3:0]$10628 + attribute \src "libresoc.v:177664.3-177690.6" + wire width 4 $4\reg$next[3:0]$10580 + attribute \src "libresoc.v:177594.3-177633.6" + wire width 4 $4\src10__data_o$next[3:0]$10571 + attribute \src "libresoc.v:177691.3-177730.6" + wire width 4 $4\src20__data_o$next[3:0]$10586 + attribute \src "libresoc.v:177761.3-177800.6" + wire width 4 $4\src30__data_o$next[3:0]$10600 + attribute \src "libresoc.v:177871.3-177900.6" + wire $4\wr_detect$10[0:0]$10622 + attribute \src "libresoc.v:177941.3-177970.6" + wire $4\wr_detect$13[0:0]$10636 + attribute \src "libresoc.v:177731.3-177760.6" + wire $4\wr_detect$4[0:0]$10594 + attribute \src "libresoc.v:177801.3-177830.6" + wire $4\wr_detect$7[0:0]$10608 + attribute \src "libresoc.v:177634.3-177663.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:176888.3-176927.6" - wire width 4 $5\cr_pred0__data_o$next[3:0]$10642 - attribute \src "libresoc.v:177265.3-177304.6" - wire width 4 $5\r0__data_o$next[3:0]$10713 - attribute \src "libresoc.v:176958.3-176997.6" - wire width 4 $5\r20__data_o$next[3:0]$10651 - attribute \src "libresoc.v:177055.3-177094.6" - wire width 4 $5\src10__data_o$next[3:0]$10671 - attribute \src "libresoc.v:177125.3-177164.6" - wire width 4 $5\src20__data_o$next[3:0]$10685 - attribute \src "libresoc.v:177195.3-177234.6" - wire width 4 $5\src30__data_o$next[3:0]$10699 - attribute \src "libresoc.v:176888.3-176927.6" - wire width 4 $6\cr_pred0__data_o$next[3:0]$10643 - attribute \src "libresoc.v:177265.3-177304.6" - wire width 4 $6\r0__data_o$next[3:0]$10714 - attribute \src "libresoc.v:176958.3-176997.6" - wire width 4 $6\r20__data_o$next[3:0]$10652 - attribute \src "libresoc.v:177055.3-177094.6" - wire width 4 $6\src10__data_o$next[3:0]$10672 - attribute \src "libresoc.v:177125.3-177164.6" - wire width 4 $6\src20__data_o$next[3:0]$10686 - attribute \src "libresoc.v:177195.3-177234.6" - wire width 4 $6\src30__data_o$next[3:0]$10700 - attribute \src "libresoc.v:176868.17-176868.104" - wire $not$libresoc.v:176868$10623_Y - attribute \src "libresoc.v:176869.18-176869.105" - wire $not$libresoc.v:176869$10624_Y - attribute \src "libresoc.v:176870.18-176870.105" - wire $not$libresoc.v:176870$10625_Y - attribute \src "libresoc.v:176871.17-176871.100" - wire $not$libresoc.v:176871$10626_Y - attribute \src "libresoc.v:176872.17-176872.103" - wire $not$libresoc.v:176872$10627_Y - attribute \src "libresoc.v:176873.17-176873.103" - wire $not$libresoc.v:176873$10628_Y + attribute \src "libresoc.v:177831.3-177870.6" + wire width 4 $5\r0__data_o$next[3:0]$10615 + attribute \src "libresoc.v:177901.3-177940.6" + wire width 4 $5\r20__data_o$next[3:0]$10629 + attribute \src "libresoc.v:177594.3-177633.6" + wire width 4 $5\src10__data_o$next[3:0]$10572 + attribute \src "libresoc.v:177691.3-177730.6" + wire width 4 $5\src20__data_o$next[3:0]$10587 + attribute \src "libresoc.v:177761.3-177800.6" + wire width 4 $5\src30__data_o$next[3:0]$10601 + attribute \src "libresoc.v:177831.3-177870.6" + wire width 4 $6\r0__data_o$next[3:0]$10616 + attribute \src "libresoc.v:177901.3-177940.6" + wire width 4 $6\r20__data_o$next[3:0]$10630 + attribute \src "libresoc.v:177594.3-177633.6" + wire width 4 $6\src10__data_o$next[3:0]$10573 + attribute \src "libresoc.v:177691.3-177730.6" + wire width 4 $6\src20__data_o$next[3:0]$10588 + attribute \src "libresoc.v:177761.3-177800.6" + wire width 4 $6\src30__data_o$next[3:0]$10602 + attribute \src "libresoc.v:177577.17-177577.104" + wire $not$libresoc.v:177577$10555_Y + attribute \src "libresoc.v:177578.18-177578.105" + wire $not$libresoc.v:177578$10556_Y + attribute \src "libresoc.v:177579.17-177579.100" + wire $not$libresoc.v:177579$10557_Y + attribute \src "libresoc.v:177580.17-177580.103" + wire $not$libresoc.v:177580$10558_Y + attribute \src "libresoc.v:177581.17-177581.103" + wire $not$libresoc.v:177581$10559_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" - wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \cr_pred0__data_o + wire width 4 input 9 \dest10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \cr_pred0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \cr_pred0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest10__wen + wire input 8 \dest10__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 13 \dest20__data_i + wire width 4 input 11 \dest20__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 12 \dest20__wen - attribute \src "libresoc.v:176781.7-176781.15" + wire input 10 \dest20__wen + attribute \src "libresoc.v:177501.7-177501.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r0__data_o + wire width 4 output 12 \r0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r0__ren + wire input 13 \r0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 16 \r20__data_o + wire width 4 output 14 \r20__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r20__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \r20__ren + wire input 15 \r20__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src10__data_o + wire width 4 output 3 \src10__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src10__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src10__ren + wire input 2 \src10__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src20__data_o + wire width 4 output 5 \src20__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src20__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src20__ren + wire input 4 \src20__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 9 \src30__data_o + wire width 4 output 7 \src30__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src30__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \src30__ren + wire input 6 \src30__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 18 \w0__data_i + wire width 4 input 16 \w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 19 \w0__wen + wire input 17 \w0__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -363128,257 +329582,232 @@ module \reg_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176868$10623 + cell $not $not$libresoc.v:177577$10555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:176868$10623_Y + connect \Y $not$libresoc.v:177577$10555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176869$10624 + cell $not $not$libresoc.v:177578$10556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:176869$10624_Y + connect \Y $not$libresoc.v:177578$10556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176870$10625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$16 - connect \Y $not$libresoc.v:176870$10625_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176871$10626 + cell $not $not$libresoc.v:177579$10557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:176871$10626_Y + connect \Y $not$libresoc.v:177579$10557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176872$10627 + cell $not $not$libresoc.v:177580$10558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:176872$10627_Y + connect \Y $not$libresoc.v:177580$10558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176873$10628 + cell $not $not$libresoc.v:177581$10559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:176873$10628_Y + connect \Y $not$libresoc.v:177581$10559_Y end - attribute \src "libresoc.v:176781.7-176781.20" - process $proc$libresoc.v:176781$10721 + attribute \src "libresoc.v:177501.7-177501.20" + process $proc$libresoc.v:177501$10637 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:176800.13-176800.36" - process $proc$libresoc.v:176800$10722 - assign { } { } - assign $1\cr_pred0__data_o[3:0] 4'0000 - sync always - sync init - update \cr_pred0__data_o $1\cr_pred0__data_o[3:0] - end - attribute \src "libresoc.v:176815.13-176815.30" - process $proc$libresoc.v:176815$10723 + attribute \src "libresoc.v:177526.13-177526.30" + process $proc$libresoc.v:177526$10638 assign { } { } assign $1\r0__data_o[3:0] 4'0000 sync always sync init update \r0__data_o $1\r0__data_o[3:0] end - attribute \src "libresoc.v:176822.13-176822.31" - process $proc$libresoc.v:176822$10724 + attribute \src "libresoc.v:177533.13-177533.31" + process $proc$libresoc.v:177533$10639 assign { } { } assign $1\r20__data_o[3:0] 4'0000 sync always sync init update \r20__data_o $1\r20__data_o[3:0] end - attribute \src "libresoc.v:176828.13-176828.25" - process $proc$libresoc.v:176828$10725 + attribute \src "libresoc.v:177539.13-177539.25" + process $proc$libresoc.v:177539$10640 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:176833.13-176833.33" - process $proc$libresoc.v:176833$10726 + attribute \src "libresoc.v:177544.13-177544.33" + process $proc$libresoc.v:177544$10641 assign { } { } assign $1\src10__data_o[3:0] 4'0000 sync always sync init update \src10__data_o $1\src10__data_o[3:0] end - attribute \src "libresoc.v:176840.13-176840.33" - process $proc$libresoc.v:176840$10727 + attribute \src "libresoc.v:177551.13-177551.33" + process $proc$libresoc.v:177551$10642 assign { } { } assign $1\src20__data_o[3:0] 4'0000 sync always sync init update \src20__data_o $1\src20__data_o[3:0] end - attribute \src "libresoc.v:176847.13-176847.33" - process $proc$libresoc.v:176847$10728 + attribute \src "libresoc.v:177558.13-177558.33" + process $proc$libresoc.v:177558$10643 assign { } { } assign $1\src30__data_o[3:0] 4'0000 sync always sync init update \src30__data_o $1\src30__data_o[3:0] end - attribute \src "libresoc.v:176874.3-176875.25" - process $proc$libresoc.v:176874$10629 + attribute \src "libresoc.v:177582.3-177583.25" + process $proc$libresoc.v:177582$10560 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:176876.3-176877.39" - process $proc$libresoc.v:176876$10630 + attribute \src "libresoc.v:177584.3-177585.39" + process $proc$libresoc.v:177584$10561 assign { } { } assign $0\r20__data_o[3:0] \r20__data_o$next sync posedge \coresync_clk update \r20__data_o $0\r20__data_o[3:0] end - attribute \src "libresoc.v:176878.3-176879.37" - process $proc$libresoc.v:176878$10631 + attribute \src "libresoc.v:177586.3-177587.37" + process $proc$libresoc.v:177586$10562 assign { } { } assign $0\r0__data_o[3:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[3:0] end - attribute \src "libresoc.v:176880.3-176881.43" - process $proc$libresoc.v:176880$10632 + attribute \src "libresoc.v:177588.3-177589.43" + process $proc$libresoc.v:177588$10563 assign { } { } assign $0\src30__data_o[3:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[3:0] end - attribute \src "libresoc.v:176882.3-176883.43" - process $proc$libresoc.v:176882$10633 + attribute \src "libresoc.v:177590.3-177591.43" + process $proc$libresoc.v:177590$10564 assign { } { } assign $0\src20__data_o[3:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[3:0] end - attribute \src "libresoc.v:176884.3-176885.43" - process $proc$libresoc.v:176884$10634 + attribute \src "libresoc.v:177592.3-177593.43" + process $proc$libresoc.v:177592$10565 assign { } { } assign $0\src10__data_o[3:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[3:0] end - attribute \src "libresoc.v:176886.3-176887.49" - process $proc$libresoc.v:176886$10635 + attribute \src "libresoc.v:177594.3-177633.6" + process $proc$libresoc.v:177594$10566 assign { } { } - assign $0\cr_pred0__data_o[3:0] \cr_pred0__data_o$next - sync posedge \coresync_clk - update \cr_pred0__data_o $0\cr_pred0__data_o[3:0] - end - attribute \src "libresoc.v:176888.3-176927.6" - process $proc$libresoc.v:176888$10636 assign { } { } assign { } { } - assign { } { } - assign $0\cr_pred0__data_o$next[3:0]$10637 $6\cr_pred0__data_o$next[3:0]$10643 - attribute \src "libresoc.v:176889.5-176889.29" + assign $0\src10__data_o$next[3:0]$10567 $6\src10__data_o$next[3:0]$10573 + attribute \src "libresoc.v:177595.5-177595.29" switch \initial - attribute \src "libresoc.v:176889.9-176889.17" + attribute \src "libresoc.v:177595.9-177595.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred0__ren + switch \src10__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\cr_pred0__data_o$next[3:0]$10638 $5\cr_pred0__data_o$next[3:0]$10642 + assign $1\src10__data_o$next[3:0]$10568 $5\src10__data_o$next[3:0]$10572 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred0__data_o$next[3:0]$10639 \dest10__data_i + assign $2\src10__data_o$next[3:0]$10569 \dest10__data_i case - assign $2\cr_pred0__data_o$next[3:0]$10639 4'0000 + assign $2\src10__data_o$next[3:0]$10569 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred0__data_o$next[3:0]$10640 \dest20__data_i + assign $3\src10__data_o$next[3:0]$10570 \dest20__data_i case - assign $3\cr_pred0__data_o$next[3:0]$10640 $2\cr_pred0__data_o$next[3:0]$10639 + assign $3\src10__data_o$next[3:0]$10570 $2\src10__data_o$next[3:0]$10569 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred0__data_o$next[3:0]$10641 \w0__data_i + assign $4\src10__data_o$next[3:0]$10571 \w0__data_i case - assign $4\cr_pred0__data_o$next[3:0]$10641 $3\cr_pred0__data_o$next[3:0]$10640 + assign $4\src10__data_o$next[3:0]$10571 $3\src10__data_o$next[3:0]$10570 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred0__data_o$next[3:0]$10642 \reg + assign $5\src10__data_o$next[3:0]$10572 \reg case - assign $5\cr_pred0__data_o$next[3:0]$10642 $4\cr_pred0__data_o$next[3:0]$10641 + assign $5\src10__data_o$next[3:0]$10572 $4\src10__data_o$next[3:0]$10571 end case - assign $1\cr_pred0__data_o$next[3:0]$10638 4'0000 + assign $1\src10__data_o$next[3:0]$10568 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred0__data_o$next[3:0]$10643 4'0000 + assign $6\src10__data_o$next[3:0]$10573 4'0000 case - assign $6\cr_pred0__data_o$next[3:0]$10643 $1\cr_pred0__data_o$next[3:0]$10638 + assign $6\src10__data_o$next[3:0]$10573 $1\src10__data_o$next[3:0]$10568 end sync always - update \cr_pred0__data_o$next $0\cr_pred0__data_o$next[3:0]$10637 + update \src10__data_o$next $0\src10__data_o$next[3:0]$10567 end - attribute \src "libresoc.v:176928.3-176957.6" - process $proc$libresoc.v:176928$10644 + attribute \src "libresoc.v:177634.3-177663.6" + process $proc$libresoc.v:177634$10574 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:176929.5-176929.29" + attribute \src "libresoc.v:177635.5-177635.29" switch \initial - attribute \src "libresoc.v:176929.9-176929.17" + attribute \src "libresoc.v:177635.9-177635.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred0__ren + switch \src10__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -363419,142 +329848,17 @@ module \reg_0 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:176958.3-176997.6" - process $proc$libresoc.v:176958$10645 + attribute \src "libresoc.v:177664.3-177690.6" + process $proc$libresoc.v:177664$10575 assign { } { } assign { } { } assign { } { } - assign $0\r20__data_o$next[3:0]$10646 $6\r20__data_o$next[3:0]$10652 - attribute \src "libresoc.v:176959.5-176959.29" - switch \initial - attribute \src "libresoc.v:176959.9-176959.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r20__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r20__data_o$next[3:0]$10647 $5\r20__data_o$next[3:0]$10651 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r20__data_o$next[3:0]$10648 \dest10__data_i - case - assign $2\r20__data_o$next[3:0]$10648 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r20__data_o$next[3:0]$10649 \dest20__data_i - case - assign $3\r20__data_o$next[3:0]$10649 $2\r20__data_o$next[3:0]$10648 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r20__data_o$next[3:0]$10650 \w0__data_i - case - assign $4\r20__data_o$next[3:0]$10650 $3\r20__data_o$next[3:0]$10649 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r20__data_o$next[3:0]$10651 \reg - case - assign $5\r20__data_o$next[3:0]$10651 $4\r20__data_o$next[3:0]$10650 - end - case - assign $1\r20__data_o$next[3:0]$10647 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r20__data_o$next[3:0]$10652 4'0000 - case - assign $6\r20__data_o$next[3:0]$10652 $1\r20__data_o$next[3:0]$10647 - end - sync always - update \r20__data_o$next $0\r20__data_o$next[3:0]$10646 - end - attribute \src "libresoc.v:176998.3-177027.6" - process $proc$libresoc.v:176998$10653 - assign { } { } - assign { } { } - assign $0\wr_detect$16[0:0]$10654 $1\wr_detect$16[0:0]$10655 - attribute \src "libresoc.v:176999.5-176999.29" - switch \initial - attribute \src "libresoc.v:176999.9-176999.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r20__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$16[0:0]$10655 $4\wr_detect$16[0:0]$10658 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$16[0:0]$10656 1'1 - case - assign $2\wr_detect$16[0:0]$10656 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$16[0:0]$10657 1'1 - case - assign $3\wr_detect$16[0:0]$10657 $2\wr_detect$16[0:0]$10656 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$16[0:0]$10658 1'1 - case - assign $4\wr_detect$16[0:0]$10658 $3\wr_detect$16[0:0]$10657 - end - case - assign $1\wr_detect$16[0:0]$10655 1'0 - end - sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$10654 - end - attribute \src "libresoc.v:177028.3-177054.6" - process $proc$libresoc.v:177028$10659 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$10660 $4\reg$next[3:0]$10664 - attribute \src "libresoc.v:177029.5-177029.29" + assign $0\reg$next[3:0]$10576 $4\reg$next[3:0]$10580 + attribute \src "libresoc.v:177665.5-177665.29" switch \initial - attribute \src "libresoc.v:177029.9-177029.17" + attribute \src "libresoc.v:177665.9-177665.17" case 1'1 case end @@ -363563,706 +329867,705 @@ module \reg_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10661 \dest10__data_i + assign $1\reg$next[3:0]$10577 \dest10__data_i case - assign $1\reg$next[3:0]$10661 \reg + assign $1\reg$next[3:0]$10577 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10662 \dest20__data_i + assign $2\reg$next[3:0]$10578 \dest20__data_i case - assign $2\reg$next[3:0]$10662 $1\reg$next[3:0]$10661 + assign $2\reg$next[3:0]$10578 $1\reg$next[3:0]$10577 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10663 \w0__data_i + assign $3\reg$next[3:0]$10579 \w0__data_i case - assign $3\reg$next[3:0]$10663 $2\reg$next[3:0]$10662 + assign $3\reg$next[3:0]$10579 $2\reg$next[3:0]$10578 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10664 4'0000 + assign $4\reg$next[3:0]$10580 4'0000 case - assign $4\reg$next[3:0]$10664 $3\reg$next[3:0]$10663 + assign $4\reg$next[3:0]$10580 $3\reg$next[3:0]$10579 end sync always - update \reg$next $0\reg$next[3:0]$10660 + update \reg$next $0\reg$next[3:0]$10576 end - attribute \src "libresoc.v:177055.3-177094.6" - process $proc$libresoc.v:177055$10665 + attribute \src "libresoc.v:177691.3-177730.6" + process $proc$libresoc.v:177691$10581 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[3:0]$10666 $6\src10__data_o$next[3:0]$10672 - attribute \src "libresoc.v:177056.5-177056.29" + assign $0\src20__data_o$next[3:0]$10582 $6\src20__data_o$next[3:0]$10588 + attribute \src "libresoc.v:177692.5-177692.29" switch \initial - attribute \src "libresoc.v:177056.9-177056.17" + attribute \src "libresoc.v:177692.9-177692.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src10__ren + switch \src20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[3:0]$10667 $5\src10__data_o$next[3:0]$10671 + assign $1\src20__data_o$next[3:0]$10583 $5\src20__data_o$next[3:0]$10587 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[3:0]$10668 \dest10__data_i + assign $2\src20__data_o$next[3:0]$10584 \dest10__data_i case - assign $2\src10__data_o$next[3:0]$10668 4'0000 + assign $2\src20__data_o$next[3:0]$10584 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[3:0]$10669 \dest20__data_i + assign $3\src20__data_o$next[3:0]$10585 \dest20__data_i case - assign $3\src10__data_o$next[3:0]$10669 $2\src10__data_o$next[3:0]$10668 + assign $3\src20__data_o$next[3:0]$10585 $2\src20__data_o$next[3:0]$10584 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[3:0]$10670 \w0__data_i + assign $4\src20__data_o$next[3:0]$10586 \w0__data_i case - assign $4\src10__data_o$next[3:0]$10670 $3\src10__data_o$next[3:0]$10669 + assign $4\src20__data_o$next[3:0]$10586 $3\src20__data_o$next[3:0]$10585 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[3:0]$10671 \reg + assign $5\src20__data_o$next[3:0]$10587 \reg case - assign $5\src10__data_o$next[3:0]$10671 $4\src10__data_o$next[3:0]$10670 + assign $5\src20__data_o$next[3:0]$10587 $4\src20__data_o$next[3:0]$10586 end case - assign $1\src10__data_o$next[3:0]$10667 4'0000 + assign $1\src20__data_o$next[3:0]$10583 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[3:0]$10672 4'0000 + assign $6\src20__data_o$next[3:0]$10588 4'0000 case - assign $6\src10__data_o$next[3:0]$10672 $1\src10__data_o$next[3:0]$10667 + assign $6\src20__data_o$next[3:0]$10588 $1\src20__data_o$next[3:0]$10583 end sync always - update \src10__data_o$next $0\src10__data_o$next[3:0]$10666 + update \src20__data_o$next $0\src20__data_o$next[3:0]$10582 end - attribute \src "libresoc.v:177095.3-177124.6" - process $proc$libresoc.v:177095$10673 + attribute \src "libresoc.v:177731.3-177760.6" + process $proc$libresoc.v:177731$10589 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10674 $1\wr_detect$4[0:0]$10675 - attribute \src "libresoc.v:177096.5-177096.29" + assign $0\wr_detect$4[0:0]$10590 $1\wr_detect$4[0:0]$10591 + attribute \src "libresoc.v:177732.5-177732.29" switch \initial - attribute \src "libresoc.v:177096.9-177096.17" + attribute \src "libresoc.v:177732.9-177732.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src10__ren + switch \src20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10675 $4\wr_detect$4[0:0]$10678 + assign $1\wr_detect$4[0:0]$10591 $4\wr_detect$4[0:0]$10594 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10676 1'1 + assign $2\wr_detect$4[0:0]$10592 1'1 case - assign $2\wr_detect$4[0:0]$10676 1'0 + assign $2\wr_detect$4[0:0]$10592 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10677 1'1 + assign $3\wr_detect$4[0:0]$10593 1'1 case - assign $3\wr_detect$4[0:0]$10677 $2\wr_detect$4[0:0]$10676 + assign $3\wr_detect$4[0:0]$10593 $2\wr_detect$4[0:0]$10592 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10678 1'1 + assign $4\wr_detect$4[0:0]$10594 1'1 case - assign $4\wr_detect$4[0:0]$10678 $3\wr_detect$4[0:0]$10677 + assign $4\wr_detect$4[0:0]$10594 $3\wr_detect$4[0:0]$10593 end case - assign $1\wr_detect$4[0:0]$10675 1'0 + assign $1\wr_detect$4[0:0]$10591 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10674 + update \wr_detect$4 $0\wr_detect$4[0:0]$10590 end - attribute \src "libresoc.v:177125.3-177164.6" - process $proc$libresoc.v:177125$10679 + attribute \src "libresoc.v:177761.3-177800.6" + process $proc$libresoc.v:177761$10595 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[3:0]$10680 $6\src20__data_o$next[3:0]$10686 - attribute \src "libresoc.v:177126.5-177126.29" + assign $0\src30__data_o$next[3:0]$10596 $6\src30__data_o$next[3:0]$10602 + attribute \src "libresoc.v:177762.5-177762.29" switch \initial - attribute \src "libresoc.v:177126.9-177126.17" + attribute \src "libresoc.v:177762.9-177762.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src20__ren + switch \src30__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[3:0]$10681 $5\src20__data_o$next[3:0]$10685 + assign $1\src30__data_o$next[3:0]$10597 $5\src30__data_o$next[3:0]$10601 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[3:0]$10682 \dest10__data_i + assign $2\src30__data_o$next[3:0]$10598 \dest10__data_i case - assign $2\src20__data_o$next[3:0]$10682 4'0000 + assign $2\src30__data_o$next[3:0]$10598 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[3:0]$10683 \dest20__data_i + assign $3\src30__data_o$next[3:0]$10599 \dest20__data_i case - assign $3\src20__data_o$next[3:0]$10683 $2\src20__data_o$next[3:0]$10682 + assign $3\src30__data_o$next[3:0]$10599 $2\src30__data_o$next[3:0]$10598 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[3:0]$10684 \w0__data_i + assign $4\src30__data_o$next[3:0]$10600 \w0__data_i case - assign $4\src20__data_o$next[3:0]$10684 $3\src20__data_o$next[3:0]$10683 + assign $4\src30__data_o$next[3:0]$10600 $3\src30__data_o$next[3:0]$10599 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[3:0]$10685 \reg + assign $5\src30__data_o$next[3:0]$10601 \reg case - assign $5\src20__data_o$next[3:0]$10685 $4\src20__data_o$next[3:0]$10684 + assign $5\src30__data_o$next[3:0]$10601 $4\src30__data_o$next[3:0]$10600 end case - assign $1\src20__data_o$next[3:0]$10681 4'0000 + assign $1\src30__data_o$next[3:0]$10597 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[3:0]$10686 4'0000 + assign $6\src30__data_o$next[3:0]$10602 4'0000 case - assign $6\src20__data_o$next[3:0]$10686 $1\src20__data_o$next[3:0]$10681 + assign $6\src30__data_o$next[3:0]$10602 $1\src30__data_o$next[3:0]$10597 end sync always - update \src20__data_o$next $0\src20__data_o$next[3:0]$10680 + update \src30__data_o$next $0\src30__data_o$next[3:0]$10596 end - attribute \src "libresoc.v:177165.3-177194.6" - process $proc$libresoc.v:177165$10687 + attribute \src "libresoc.v:177801.3-177830.6" + process $proc$libresoc.v:177801$10603 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10688 $1\wr_detect$7[0:0]$10689 - attribute \src "libresoc.v:177166.5-177166.29" + assign $0\wr_detect$7[0:0]$10604 $1\wr_detect$7[0:0]$10605 + attribute \src "libresoc.v:177802.5-177802.29" switch \initial - attribute \src "libresoc.v:177166.9-177166.17" + attribute \src "libresoc.v:177802.9-177802.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src20__ren + switch \src30__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10689 $4\wr_detect$7[0:0]$10692 + assign $1\wr_detect$7[0:0]$10605 $4\wr_detect$7[0:0]$10608 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10690 1'1 + assign $2\wr_detect$7[0:0]$10606 1'1 case - assign $2\wr_detect$7[0:0]$10690 1'0 + assign $2\wr_detect$7[0:0]$10606 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10691 1'1 + assign $3\wr_detect$7[0:0]$10607 1'1 case - assign $3\wr_detect$7[0:0]$10691 $2\wr_detect$7[0:0]$10690 + assign $3\wr_detect$7[0:0]$10607 $2\wr_detect$7[0:0]$10606 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10692 1'1 + assign $4\wr_detect$7[0:0]$10608 1'1 case - assign $4\wr_detect$7[0:0]$10692 $3\wr_detect$7[0:0]$10691 + assign $4\wr_detect$7[0:0]$10608 $3\wr_detect$7[0:0]$10607 end case - assign $1\wr_detect$7[0:0]$10689 1'0 + assign $1\wr_detect$7[0:0]$10605 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10688 + update \wr_detect$7 $0\wr_detect$7[0:0]$10604 end - attribute \src "libresoc.v:177195.3-177234.6" - process $proc$libresoc.v:177195$10693 + attribute \src "libresoc.v:177831.3-177870.6" + process $proc$libresoc.v:177831$10609 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[3:0]$10694 $6\src30__data_o$next[3:0]$10700 - attribute \src "libresoc.v:177196.5-177196.29" + assign $0\r0__data_o$next[3:0]$10610 $6\r0__data_o$next[3:0]$10616 + attribute \src "libresoc.v:177832.5-177832.29" switch \initial - attribute \src "libresoc.v:177196.9-177196.17" + attribute \src "libresoc.v:177832.9-177832.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src30__ren + switch \r0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[3:0]$10695 $5\src30__data_o$next[3:0]$10699 + assign $1\r0__data_o$next[3:0]$10611 $5\r0__data_o$next[3:0]$10615 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[3:0]$10696 \dest10__data_i + assign $2\r0__data_o$next[3:0]$10612 \dest10__data_i case - assign $2\src30__data_o$next[3:0]$10696 4'0000 + assign $2\r0__data_o$next[3:0]$10612 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[3:0]$10697 \dest20__data_i + assign $3\r0__data_o$next[3:0]$10613 \dest20__data_i case - assign $3\src30__data_o$next[3:0]$10697 $2\src30__data_o$next[3:0]$10696 + assign $3\r0__data_o$next[3:0]$10613 $2\r0__data_o$next[3:0]$10612 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[3:0]$10698 \w0__data_i + assign $4\r0__data_o$next[3:0]$10614 \w0__data_i case - assign $4\src30__data_o$next[3:0]$10698 $3\src30__data_o$next[3:0]$10697 + assign $4\r0__data_o$next[3:0]$10614 $3\r0__data_o$next[3:0]$10613 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[3:0]$10699 \reg + assign $5\r0__data_o$next[3:0]$10615 \reg case - assign $5\src30__data_o$next[3:0]$10699 $4\src30__data_o$next[3:0]$10698 + assign $5\r0__data_o$next[3:0]$10615 $4\r0__data_o$next[3:0]$10614 end case - assign $1\src30__data_o$next[3:0]$10695 4'0000 + assign $1\r0__data_o$next[3:0]$10611 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[3:0]$10700 4'0000 + assign $6\r0__data_o$next[3:0]$10616 4'0000 case - assign $6\src30__data_o$next[3:0]$10700 $1\src30__data_o$next[3:0]$10695 + assign $6\r0__data_o$next[3:0]$10616 $1\r0__data_o$next[3:0]$10611 end sync always - update \src30__data_o$next $0\src30__data_o$next[3:0]$10694 + update \r0__data_o$next $0\r0__data_o$next[3:0]$10610 end - attribute \src "libresoc.v:177235.3-177264.6" - process $proc$libresoc.v:177235$10701 + attribute \src "libresoc.v:177871.3-177900.6" + process $proc$libresoc.v:177871$10617 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10702 $1\wr_detect$10[0:0]$10703 - attribute \src "libresoc.v:177236.5-177236.29" + assign $0\wr_detect$10[0:0]$10618 $1\wr_detect$10[0:0]$10619 + attribute \src "libresoc.v:177872.5-177872.29" switch \initial - attribute \src "libresoc.v:177236.9-177236.17" + attribute \src "libresoc.v:177872.9-177872.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src30__ren + switch \r0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10703 $4\wr_detect$10[0:0]$10706 + assign $1\wr_detect$10[0:0]$10619 $4\wr_detect$10[0:0]$10622 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10704 1'1 + assign $2\wr_detect$10[0:0]$10620 1'1 case - assign $2\wr_detect$10[0:0]$10704 1'0 + assign $2\wr_detect$10[0:0]$10620 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10705 1'1 + assign $3\wr_detect$10[0:0]$10621 1'1 case - assign $3\wr_detect$10[0:0]$10705 $2\wr_detect$10[0:0]$10704 + assign $3\wr_detect$10[0:0]$10621 $2\wr_detect$10[0:0]$10620 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10706 1'1 + assign $4\wr_detect$10[0:0]$10622 1'1 case - assign $4\wr_detect$10[0:0]$10706 $3\wr_detect$10[0:0]$10705 + assign $4\wr_detect$10[0:0]$10622 $3\wr_detect$10[0:0]$10621 end case - assign $1\wr_detect$10[0:0]$10703 1'0 + assign $1\wr_detect$10[0:0]$10619 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10702 + update \wr_detect$10 $0\wr_detect$10[0:0]$10618 end - attribute \src "libresoc.v:177265.3-177304.6" - process $proc$libresoc.v:177265$10707 + attribute \src "libresoc.v:177901.3-177940.6" + process $proc$libresoc.v:177901$10623 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[3:0]$10708 $6\r0__data_o$next[3:0]$10714 - attribute \src "libresoc.v:177266.5-177266.29" + assign $0\r20__data_o$next[3:0]$10624 $6\r20__data_o$next[3:0]$10630 + attribute \src "libresoc.v:177902.5-177902.29" switch \initial - attribute \src "libresoc.v:177266.9-177266.17" + attribute \src "libresoc.v:177902.9-177902.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r0__ren + switch \r20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[3:0]$10709 $5\r0__data_o$next[3:0]$10713 + assign $1\r20__data_o$next[3:0]$10625 $5\r20__data_o$next[3:0]$10629 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[3:0]$10710 \dest10__data_i + assign $2\r20__data_o$next[3:0]$10626 \dest10__data_i case - assign $2\r0__data_o$next[3:0]$10710 4'0000 + assign $2\r20__data_o$next[3:0]$10626 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[3:0]$10711 \dest20__data_i + assign $3\r20__data_o$next[3:0]$10627 \dest20__data_i case - assign $3\r0__data_o$next[3:0]$10711 $2\r0__data_o$next[3:0]$10710 + assign $3\r20__data_o$next[3:0]$10627 $2\r20__data_o$next[3:0]$10626 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[3:0]$10712 \w0__data_i + assign $4\r20__data_o$next[3:0]$10628 \w0__data_i case - assign $4\r0__data_o$next[3:0]$10712 $3\r0__data_o$next[3:0]$10711 + assign $4\r20__data_o$next[3:0]$10628 $3\r20__data_o$next[3:0]$10627 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[3:0]$10713 \reg + assign $5\r20__data_o$next[3:0]$10629 \reg case - assign $5\r0__data_o$next[3:0]$10713 $4\r0__data_o$next[3:0]$10712 + assign $5\r20__data_o$next[3:0]$10629 $4\r20__data_o$next[3:0]$10628 end case - assign $1\r0__data_o$next[3:0]$10709 4'0000 + assign $1\r20__data_o$next[3:0]$10625 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[3:0]$10714 4'0000 + assign $6\r20__data_o$next[3:0]$10630 4'0000 case - assign $6\r0__data_o$next[3:0]$10714 $1\r0__data_o$next[3:0]$10709 + assign $6\r20__data_o$next[3:0]$10630 $1\r20__data_o$next[3:0]$10625 end sync always - update \r0__data_o$next $0\r0__data_o$next[3:0]$10708 + update \r20__data_o$next $0\r20__data_o$next[3:0]$10624 end - attribute \src "libresoc.v:177305.3-177334.6" - process $proc$libresoc.v:177305$10715 + attribute \src "libresoc.v:177941.3-177970.6" + process $proc$libresoc.v:177941$10631 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10716 $1\wr_detect$13[0:0]$10717 - attribute \src "libresoc.v:177306.5-177306.29" + assign $0\wr_detect$13[0:0]$10632 $1\wr_detect$13[0:0]$10633 + attribute \src "libresoc.v:177942.5-177942.29" switch \initial - attribute \src "libresoc.v:177306.9-177306.17" + attribute \src "libresoc.v:177942.9-177942.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r0__ren + switch \r20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10717 $4\wr_detect$13[0:0]$10720 + assign $1\wr_detect$13[0:0]$10633 $4\wr_detect$13[0:0]$10636 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10718 1'1 + assign $2\wr_detect$13[0:0]$10634 1'1 case - assign $2\wr_detect$13[0:0]$10718 1'0 + assign $2\wr_detect$13[0:0]$10634 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10719 1'1 + assign $3\wr_detect$13[0:0]$10635 1'1 case - assign $3\wr_detect$13[0:0]$10719 $2\wr_detect$13[0:0]$10718 + assign $3\wr_detect$13[0:0]$10635 $2\wr_detect$13[0:0]$10634 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10720 1'1 + assign $4\wr_detect$13[0:0]$10636 1'1 case - assign $4\wr_detect$13[0:0]$10720 $3\wr_detect$13[0:0]$10719 + assign $4\wr_detect$13[0:0]$10636 $3\wr_detect$13[0:0]$10635 end case - assign $1\wr_detect$13[0:0]$10717 1'0 + assign $1\wr_detect$13[0:0]$10633 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10716 + update \wr_detect$13 $0\wr_detect$13[0:0]$10632 end - connect \$9 $not$libresoc.v:176868$10623_Y - connect \$12 $not$libresoc.v:176869$10624_Y - connect \$15 $not$libresoc.v:176870$10625_Y - connect \$1 $not$libresoc.v:176871$10626_Y - connect \$3 $not$libresoc.v:176872$10627_Y - connect \$6 $not$libresoc.v:176873$10628_Y + connect \$9 $not$libresoc.v:177577$10555_Y + connect \$12 $not$libresoc.v:177578$10556_Y + connect \$1 $not$libresoc.v:177579$10557_Y + connect \$3 $not$libresoc.v:177580$10558_Y + connect \$6 $not$libresoc.v:177581$10559_Y end -attribute \src "libresoc.v:177339.1-177784.10" +attribute \src "libresoc.v:177975.1-178420.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" attribute \generator "nMigen" module \reg_0$132 - attribute \src "libresoc.v:177340.7-177340.20" + attribute \src "libresoc.v:177976.7-177976.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177669.3-177714.6" - wire width 2 $0\r0__data_o$next[1:0]$10781 - attribute \src "libresoc.v:177415.3-177416.37" + attribute \src "libresoc.v:178305.3-178350.6" + wire width 2 $0\r0__data_o$next[1:0]$10696 + attribute \src "libresoc.v:178051.3-178052.37" wire width 2 $0\r0__data_o[1:0] - attribute \src "libresoc.v:177751.3-177783.6" - wire width 2 $0\reg$next[1:0]$10797 - attribute \src "libresoc.v:177413.3-177414.25" + attribute \src "libresoc.v:178387.3-178419.6" + wire width 2 $0\reg$next[1:0]$10712 + attribute \src "libresoc.v:178049.3-178050.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:177423.3-177468.6" - wire width 2 $0\src10__data_o$next[1:0]$10739 - attribute \src "libresoc.v:177421.3-177422.43" + attribute \src "libresoc.v:178059.3-178104.6" + wire width 2 $0\src10__data_o$next[1:0]$10654 + attribute \src "libresoc.v:178057.3-178058.43" wire width 2 $0\src10__data_o[1:0] - attribute \src "libresoc.v:177505.3-177550.6" - wire width 2 $0\src20__data_o$next[1:0]$10749 - attribute \src "libresoc.v:177419.3-177420.43" + attribute \src "libresoc.v:178141.3-178186.6" + wire width 2 $0\src20__data_o$next[1:0]$10664 + attribute \src "libresoc.v:178055.3-178056.43" wire width 2 $0\src20__data_o[1:0] - attribute \src "libresoc.v:177587.3-177632.6" - wire width 2 $0\src30__data_o$next[1:0]$10765 - attribute \src "libresoc.v:177417.3-177418.43" + attribute \src "libresoc.v:178223.3-178268.6" + wire width 2 $0\src30__data_o$next[1:0]$10680 + attribute \src "libresoc.v:178053.3-178054.43" wire width 2 $0\src30__data_o[1:0] - attribute \src "libresoc.v:177715.3-177750.6" - wire $0\wr_detect$10[0:0]$10790 - attribute \src "libresoc.v:177551.3-177586.6" - wire $0\wr_detect$4[0:0]$10758 - attribute \src "libresoc.v:177633.3-177668.6" - wire $0\wr_detect$7[0:0]$10774 - attribute \src "libresoc.v:177469.3-177504.6" + attribute \src "libresoc.v:178351.3-178386.6" + wire $0\wr_detect$10[0:0]$10705 + attribute \src "libresoc.v:178187.3-178222.6" + wire $0\wr_detect$4[0:0]$10673 + attribute \src "libresoc.v:178269.3-178304.6" + wire $0\wr_detect$7[0:0]$10689 + attribute \src "libresoc.v:178105.3-178140.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:177669.3-177714.6" - wire width 2 $1\r0__data_o$next[1:0]$10782 - attribute \src "libresoc.v:177367.13-177367.30" + attribute \src "libresoc.v:178305.3-178350.6" + wire width 2 $1\r0__data_o$next[1:0]$10697 + attribute \src "libresoc.v:178003.13-178003.30" wire width 2 $1\r0__data_o[1:0] - attribute \src "libresoc.v:177751.3-177783.6" - wire width 2 $1\reg$next[1:0]$10798 - attribute \src "libresoc.v:177373.13-177373.25" + attribute \src "libresoc.v:178387.3-178419.6" + wire width 2 $1\reg$next[1:0]$10713 + attribute \src "libresoc.v:178009.13-178009.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:177423.3-177468.6" - wire width 2 $1\src10__data_o$next[1:0]$10740 - attribute \src "libresoc.v:177378.13-177378.33" + attribute \src "libresoc.v:178059.3-178104.6" + wire width 2 $1\src10__data_o$next[1:0]$10655 + attribute \src "libresoc.v:178014.13-178014.33" wire width 2 $1\src10__data_o[1:0] - attribute \src "libresoc.v:177505.3-177550.6" - wire width 2 $1\src20__data_o$next[1:0]$10750 - attribute \src "libresoc.v:177385.13-177385.33" + attribute \src "libresoc.v:178141.3-178186.6" + wire width 2 $1\src20__data_o$next[1:0]$10665 + attribute \src "libresoc.v:178021.13-178021.33" wire width 2 $1\src20__data_o[1:0] - attribute \src "libresoc.v:177587.3-177632.6" - wire width 2 $1\src30__data_o$next[1:0]$10766 - attribute \src "libresoc.v:177392.13-177392.33" + attribute \src "libresoc.v:178223.3-178268.6" + wire width 2 $1\src30__data_o$next[1:0]$10681 + attribute \src "libresoc.v:178028.13-178028.33" wire width 2 $1\src30__data_o[1:0] - attribute \src "libresoc.v:177715.3-177750.6" - wire $1\wr_detect$10[0:0]$10791 - attribute \src "libresoc.v:177551.3-177586.6" - wire $1\wr_detect$4[0:0]$10759 - attribute \src "libresoc.v:177633.3-177668.6" - wire $1\wr_detect$7[0:0]$10775 - attribute \src "libresoc.v:177469.3-177504.6" + attribute \src "libresoc.v:178351.3-178386.6" + wire $1\wr_detect$10[0:0]$10706 + attribute \src "libresoc.v:178187.3-178222.6" + wire $1\wr_detect$4[0:0]$10674 + attribute \src "libresoc.v:178269.3-178304.6" + wire $1\wr_detect$7[0:0]$10690 + attribute \src "libresoc.v:178105.3-178140.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:177669.3-177714.6" - wire width 2 $2\r0__data_o$next[1:0]$10783 - attribute \src "libresoc.v:177751.3-177783.6" - wire width 2 $2\reg$next[1:0]$10799 - attribute \src "libresoc.v:177423.3-177468.6" - wire width 2 $2\src10__data_o$next[1:0]$10741 - attribute \src "libresoc.v:177505.3-177550.6" - wire width 2 $2\src20__data_o$next[1:0]$10751 - attribute \src "libresoc.v:177587.3-177632.6" - wire width 2 $2\src30__data_o$next[1:0]$10767 - attribute \src "libresoc.v:177715.3-177750.6" - wire $2\wr_detect$10[0:0]$10792 - attribute \src "libresoc.v:177551.3-177586.6" - wire $2\wr_detect$4[0:0]$10760 - attribute \src "libresoc.v:177633.3-177668.6" - wire $2\wr_detect$7[0:0]$10776 - attribute \src "libresoc.v:177469.3-177504.6" + attribute \src "libresoc.v:178305.3-178350.6" + wire width 2 $2\r0__data_o$next[1:0]$10698 + attribute \src "libresoc.v:178387.3-178419.6" + wire width 2 $2\reg$next[1:0]$10714 + attribute \src "libresoc.v:178059.3-178104.6" + wire width 2 $2\src10__data_o$next[1:0]$10656 + attribute \src "libresoc.v:178141.3-178186.6" + wire width 2 $2\src20__data_o$next[1:0]$10666 + attribute \src "libresoc.v:178223.3-178268.6" + wire width 2 $2\src30__data_o$next[1:0]$10682 + attribute \src "libresoc.v:178351.3-178386.6" + wire $2\wr_detect$10[0:0]$10707 + attribute \src "libresoc.v:178187.3-178222.6" + wire $2\wr_detect$4[0:0]$10675 + attribute \src "libresoc.v:178269.3-178304.6" + wire $2\wr_detect$7[0:0]$10691 + attribute \src "libresoc.v:178105.3-178140.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:177669.3-177714.6" - wire width 2 $3\r0__data_o$next[1:0]$10784 - attribute \src "libresoc.v:177751.3-177783.6" - wire width 2 $3\reg$next[1:0]$10800 - attribute \src "libresoc.v:177423.3-177468.6" - wire width 2 $3\src10__data_o$next[1:0]$10742 - attribute \src "libresoc.v:177505.3-177550.6" - wire width 2 $3\src20__data_o$next[1:0]$10752 - attribute \src "libresoc.v:177587.3-177632.6" - wire width 2 $3\src30__data_o$next[1:0]$10768 - attribute \src "libresoc.v:177715.3-177750.6" - wire $3\wr_detect$10[0:0]$10793 - attribute \src "libresoc.v:177551.3-177586.6" - wire $3\wr_detect$4[0:0]$10761 - attribute \src "libresoc.v:177633.3-177668.6" - wire $3\wr_detect$7[0:0]$10777 - attribute \src "libresoc.v:177469.3-177504.6" + attribute \src "libresoc.v:178305.3-178350.6" + wire width 2 $3\r0__data_o$next[1:0]$10699 + attribute \src "libresoc.v:178387.3-178419.6" + wire width 2 $3\reg$next[1:0]$10715 + attribute \src "libresoc.v:178059.3-178104.6" + wire width 2 $3\src10__data_o$next[1:0]$10657 + attribute \src "libresoc.v:178141.3-178186.6" + wire width 2 $3\src20__data_o$next[1:0]$10667 + attribute \src "libresoc.v:178223.3-178268.6" + wire width 2 $3\src30__data_o$next[1:0]$10683 + attribute \src "libresoc.v:178351.3-178386.6" + wire $3\wr_detect$10[0:0]$10708 + attribute \src "libresoc.v:178187.3-178222.6" + wire $3\wr_detect$4[0:0]$10676 + attribute \src "libresoc.v:178269.3-178304.6" + wire $3\wr_detect$7[0:0]$10692 + attribute \src "libresoc.v:178105.3-178140.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:177669.3-177714.6" - wire width 2 $4\r0__data_o$next[1:0]$10785 - attribute \src "libresoc.v:177751.3-177783.6" - wire width 2 $4\reg$next[1:0]$10801 - attribute \src "libresoc.v:177423.3-177468.6" - wire width 2 $4\src10__data_o$next[1:0]$10743 - attribute \src "libresoc.v:177505.3-177550.6" - wire width 2 $4\src20__data_o$next[1:0]$10753 - attribute \src "libresoc.v:177587.3-177632.6" - wire width 2 $4\src30__data_o$next[1:0]$10769 - attribute \src "libresoc.v:177715.3-177750.6" - wire $4\wr_detect$10[0:0]$10794 - attribute \src "libresoc.v:177551.3-177586.6" - wire $4\wr_detect$4[0:0]$10762 - attribute \src "libresoc.v:177633.3-177668.6" - wire $4\wr_detect$7[0:0]$10778 - attribute \src "libresoc.v:177469.3-177504.6" + attribute \src "libresoc.v:178305.3-178350.6" + wire width 2 $4\r0__data_o$next[1:0]$10700 + attribute \src "libresoc.v:178387.3-178419.6" + wire width 2 $4\reg$next[1:0]$10716 + attribute \src "libresoc.v:178059.3-178104.6" + wire width 2 $4\src10__data_o$next[1:0]$10658 + attribute \src "libresoc.v:178141.3-178186.6" + wire width 2 $4\src20__data_o$next[1:0]$10668 + attribute \src "libresoc.v:178223.3-178268.6" + wire width 2 $4\src30__data_o$next[1:0]$10684 + attribute \src "libresoc.v:178351.3-178386.6" + wire $4\wr_detect$10[0:0]$10709 + attribute \src "libresoc.v:178187.3-178222.6" + wire $4\wr_detect$4[0:0]$10677 + attribute \src "libresoc.v:178269.3-178304.6" + wire $4\wr_detect$7[0:0]$10693 + attribute \src "libresoc.v:178105.3-178140.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:177669.3-177714.6" - wire width 2 $5\r0__data_o$next[1:0]$10786 - attribute \src "libresoc.v:177751.3-177783.6" - wire width 2 $5\reg$next[1:0]$10802 - attribute \src "libresoc.v:177423.3-177468.6" - wire width 2 $5\src10__data_o$next[1:0]$10744 - attribute \src "libresoc.v:177505.3-177550.6" - wire width 2 $5\src20__data_o$next[1:0]$10754 - attribute \src "libresoc.v:177587.3-177632.6" - wire width 2 $5\src30__data_o$next[1:0]$10770 - attribute \src "libresoc.v:177715.3-177750.6" - wire $5\wr_detect$10[0:0]$10795 - attribute \src "libresoc.v:177551.3-177586.6" - wire $5\wr_detect$4[0:0]$10763 - attribute \src "libresoc.v:177633.3-177668.6" - wire $5\wr_detect$7[0:0]$10779 - attribute \src "libresoc.v:177469.3-177504.6" + attribute \src "libresoc.v:178305.3-178350.6" + wire width 2 $5\r0__data_o$next[1:0]$10701 + attribute \src "libresoc.v:178387.3-178419.6" + wire width 2 $5\reg$next[1:0]$10717 + attribute \src "libresoc.v:178059.3-178104.6" + wire width 2 $5\src10__data_o$next[1:0]$10659 + attribute \src "libresoc.v:178141.3-178186.6" + wire width 2 $5\src20__data_o$next[1:0]$10669 + attribute \src "libresoc.v:178223.3-178268.6" + wire width 2 $5\src30__data_o$next[1:0]$10685 + attribute \src "libresoc.v:178351.3-178386.6" + wire $5\wr_detect$10[0:0]$10710 + attribute \src "libresoc.v:178187.3-178222.6" + wire $5\wr_detect$4[0:0]$10678 + attribute \src "libresoc.v:178269.3-178304.6" + wire $5\wr_detect$7[0:0]$10694 + attribute \src "libresoc.v:178105.3-178140.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:177669.3-177714.6" - wire width 2 $6\r0__data_o$next[1:0]$10787 - attribute \src "libresoc.v:177423.3-177468.6" - wire width 2 $6\src10__data_o$next[1:0]$10745 - attribute \src "libresoc.v:177505.3-177550.6" - wire width 2 $6\src20__data_o$next[1:0]$10755 - attribute \src "libresoc.v:177587.3-177632.6" - wire width 2 $6\src30__data_o$next[1:0]$10771 - attribute \src "libresoc.v:177669.3-177714.6" - wire width 2 $7\r0__data_o$next[1:0]$10788 - attribute \src "libresoc.v:177423.3-177468.6" - wire width 2 $7\src10__data_o$next[1:0]$10746 - attribute \src "libresoc.v:177505.3-177550.6" - wire width 2 $7\src20__data_o$next[1:0]$10756 - attribute \src "libresoc.v:177587.3-177632.6" - wire width 2 $7\src30__data_o$next[1:0]$10772 - attribute \src "libresoc.v:177409.17-177409.104" - wire $not$libresoc.v:177409$10729_Y - attribute \src "libresoc.v:177410.17-177410.100" - wire $not$libresoc.v:177410$10730_Y - attribute \src "libresoc.v:177411.17-177411.103" - wire $not$libresoc.v:177411$10731_Y - attribute \src "libresoc.v:177412.17-177412.103" - wire $not$libresoc.v:177412$10732_Y + attribute \src "libresoc.v:178305.3-178350.6" + wire width 2 $6\r0__data_o$next[1:0]$10702 + attribute \src "libresoc.v:178059.3-178104.6" + wire width 2 $6\src10__data_o$next[1:0]$10660 + attribute \src "libresoc.v:178141.3-178186.6" + wire width 2 $6\src20__data_o$next[1:0]$10670 + attribute \src "libresoc.v:178223.3-178268.6" + wire width 2 $6\src30__data_o$next[1:0]$10686 + attribute \src "libresoc.v:178305.3-178350.6" + wire width 2 $7\r0__data_o$next[1:0]$10703 + attribute \src "libresoc.v:178059.3-178104.6" + wire width 2 $7\src10__data_o$next[1:0]$10661 + attribute \src "libresoc.v:178141.3-178186.6" + wire width 2 $7\src20__data_o$next[1:0]$10671 + attribute \src "libresoc.v:178223.3-178268.6" + wire width 2 $7\src30__data_o$next[1:0]$10687 + attribute \src "libresoc.v:178045.17-178045.104" + wire $not$libresoc.v:178045$10644_Y + attribute \src "libresoc.v:178046.17-178046.100" + wire $not$libresoc.v:178046$10645_Y + attribute \src "libresoc.v:178047.17-178047.103" + wire $not$libresoc.v:178047$10646_Y + attribute \src "libresoc.v:178048.17-178048.103" + wire $not$libresoc.v:178048$10647_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -364271,9 +330574,9 @@ module \reg_0$132 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest10__data_i @@ -364287,7 +330590,7 @@ module \reg_0$132 wire width 2 input 13 \dest30__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest30__wen - attribute \src "libresoc.v:177340.7-177340.15" + attribute \src "libresoc.v:177976.7-177976.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r0__data_o @@ -364330,129 +330633,129 @@ module \reg_0$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177409$10729 + cell $not $not$libresoc.v:178045$10644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:177409$10729_Y + connect \Y $not$libresoc.v:178045$10644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177410$10730 + cell $not $not$libresoc.v:178046$10645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:177410$10730_Y + connect \Y $not$libresoc.v:178046$10645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177411$10731 + cell $not $not$libresoc.v:178047$10646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:177411$10731_Y + connect \Y $not$libresoc.v:178047$10646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177412$10732 + cell $not $not$libresoc.v:178048$10647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:177412$10732_Y + connect \Y $not$libresoc.v:178048$10647_Y end - attribute \src "libresoc.v:177340.7-177340.20" - process $proc$libresoc.v:177340$10803 + attribute \src "libresoc.v:177976.7-177976.20" + process $proc$libresoc.v:177976$10718 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177367.13-177367.30" - process $proc$libresoc.v:177367$10804 + attribute \src "libresoc.v:178003.13-178003.30" + process $proc$libresoc.v:178003$10719 assign { } { } assign $1\r0__data_o[1:0] 2'00 sync always sync init update \r0__data_o $1\r0__data_o[1:0] end - attribute \src "libresoc.v:177373.13-177373.25" - process $proc$libresoc.v:177373$10805 + attribute \src "libresoc.v:178009.13-178009.25" + process $proc$libresoc.v:178009$10720 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:177378.13-177378.33" - process $proc$libresoc.v:177378$10806 + attribute \src "libresoc.v:178014.13-178014.33" + process $proc$libresoc.v:178014$10721 assign { } { } assign $1\src10__data_o[1:0] 2'00 sync always sync init update \src10__data_o $1\src10__data_o[1:0] end - attribute \src "libresoc.v:177385.13-177385.33" - process $proc$libresoc.v:177385$10807 + attribute \src "libresoc.v:178021.13-178021.33" + process $proc$libresoc.v:178021$10722 assign { } { } assign $1\src20__data_o[1:0] 2'00 sync always sync init update \src20__data_o $1\src20__data_o[1:0] end - attribute \src "libresoc.v:177392.13-177392.33" - process $proc$libresoc.v:177392$10808 + attribute \src "libresoc.v:178028.13-178028.33" + process $proc$libresoc.v:178028$10723 assign { } { } assign $1\src30__data_o[1:0] 2'00 sync always sync init update \src30__data_o $1\src30__data_o[1:0] end - attribute \src "libresoc.v:177413.3-177414.25" - process $proc$libresoc.v:177413$10733 + attribute \src "libresoc.v:178049.3-178050.25" + process $proc$libresoc.v:178049$10648 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:177415.3-177416.37" - process $proc$libresoc.v:177415$10734 + attribute \src "libresoc.v:178051.3-178052.37" + process $proc$libresoc.v:178051$10649 assign { } { } assign $0\r0__data_o[1:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[1:0] end - attribute \src "libresoc.v:177417.3-177418.43" - process $proc$libresoc.v:177417$10735 + attribute \src "libresoc.v:178053.3-178054.43" + process $proc$libresoc.v:178053$10650 assign { } { } assign $0\src30__data_o[1:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[1:0] end - attribute \src "libresoc.v:177419.3-177420.43" - process $proc$libresoc.v:177419$10736 + attribute \src "libresoc.v:178055.3-178056.43" + process $proc$libresoc.v:178055$10651 assign { } { } assign $0\src20__data_o[1:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[1:0] end - attribute \src "libresoc.v:177421.3-177422.43" - process $proc$libresoc.v:177421$10737 + attribute \src "libresoc.v:178057.3-178058.43" + process $proc$libresoc.v:178057$10652 assign { } { } assign $0\src10__data_o[1:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[1:0] end - attribute \src "libresoc.v:177423.3-177468.6" - process $proc$libresoc.v:177423$10738 + attribute \src "libresoc.v:178059.3-178104.6" + process $proc$libresoc.v:178059$10653 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[1:0]$10739 $7\src10__data_o$next[1:0]$10746 - attribute \src "libresoc.v:177424.5-177424.29" + assign $0\src10__data_o$next[1:0]$10654 $7\src10__data_o$next[1:0]$10661 + attribute \src "libresoc.v:178060.5-178060.29" switch \initial - attribute \src "libresoc.v:177424.9-177424.17" + attribute \src "libresoc.v:178060.9-178060.17" case 1'1 case end @@ -364465,75 +330768,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[1:0]$10740 $6\src10__data_o$next[1:0]$10745 + assign $1\src10__data_o$next[1:0]$10655 $6\src10__data_o$next[1:0]$10660 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[1:0]$10741 \dest10__data_i + assign $2\src10__data_o$next[1:0]$10656 \dest10__data_i case - assign $2\src10__data_o$next[1:0]$10741 2'00 + assign $2\src10__data_o$next[1:0]$10656 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[1:0]$10742 \dest20__data_i + assign $3\src10__data_o$next[1:0]$10657 \dest20__data_i case - assign $3\src10__data_o$next[1:0]$10742 $2\src10__data_o$next[1:0]$10741 + assign $3\src10__data_o$next[1:0]$10657 $2\src10__data_o$next[1:0]$10656 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[1:0]$10743 \dest30__data_i + assign $4\src10__data_o$next[1:0]$10658 \dest30__data_i case - assign $4\src10__data_o$next[1:0]$10743 $3\src10__data_o$next[1:0]$10742 + assign $4\src10__data_o$next[1:0]$10658 $3\src10__data_o$next[1:0]$10657 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[1:0]$10744 \w0__data_i + assign $5\src10__data_o$next[1:0]$10659 \w0__data_i case - assign $5\src10__data_o$next[1:0]$10744 $4\src10__data_o$next[1:0]$10743 + assign $5\src10__data_o$next[1:0]$10659 $4\src10__data_o$next[1:0]$10658 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[1:0]$10745 \reg + assign $6\src10__data_o$next[1:0]$10660 \reg case - assign $6\src10__data_o$next[1:0]$10745 $5\src10__data_o$next[1:0]$10744 + assign $6\src10__data_o$next[1:0]$10660 $5\src10__data_o$next[1:0]$10659 end case - assign $1\src10__data_o$next[1:0]$10740 2'00 + assign $1\src10__data_o$next[1:0]$10655 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src10__data_o$next[1:0]$10746 2'00 + assign $7\src10__data_o$next[1:0]$10661 2'00 case - assign $7\src10__data_o$next[1:0]$10746 $1\src10__data_o$next[1:0]$10740 + assign $7\src10__data_o$next[1:0]$10661 $1\src10__data_o$next[1:0]$10655 end sync always - update \src10__data_o$next $0\src10__data_o$next[1:0]$10739 + update \src10__data_o$next $0\src10__data_o$next[1:0]$10654 end - attribute \src "libresoc.v:177469.3-177504.6" - process $proc$libresoc.v:177469$10747 + attribute \src "libresoc.v:178105.3-178140.6" + process $proc$libresoc.v:178105$10662 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177470.5-177470.29" + attribute \src "libresoc.v:178106.5-178106.29" switch \initial - attribute \src "libresoc.v:177470.9-177470.17" + attribute \src "libresoc.v:178106.9-178106.17" case 1'1 case end @@ -364589,15 +330892,15 @@ module \reg_0$132 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177505.3-177550.6" - process $proc$libresoc.v:177505$10748 + attribute \src "libresoc.v:178141.3-178186.6" + process $proc$libresoc.v:178141$10663 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[1:0]$10749 $7\src20__data_o$next[1:0]$10756 - attribute \src "libresoc.v:177506.5-177506.29" + assign $0\src20__data_o$next[1:0]$10664 $7\src20__data_o$next[1:0]$10671 + attribute \src "libresoc.v:178142.5-178142.29" switch \initial - attribute \src "libresoc.v:177506.9-177506.17" + attribute \src "libresoc.v:178142.9-178142.17" case 1'1 case end @@ -364610,75 +330913,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[1:0]$10750 $6\src20__data_o$next[1:0]$10755 + assign $1\src20__data_o$next[1:0]$10665 $6\src20__data_o$next[1:0]$10670 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[1:0]$10751 \dest10__data_i + assign $2\src20__data_o$next[1:0]$10666 \dest10__data_i case - assign $2\src20__data_o$next[1:0]$10751 2'00 + assign $2\src20__data_o$next[1:0]$10666 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[1:0]$10752 \dest20__data_i + assign $3\src20__data_o$next[1:0]$10667 \dest20__data_i case - assign $3\src20__data_o$next[1:0]$10752 $2\src20__data_o$next[1:0]$10751 + assign $3\src20__data_o$next[1:0]$10667 $2\src20__data_o$next[1:0]$10666 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[1:0]$10753 \dest30__data_i + assign $4\src20__data_o$next[1:0]$10668 \dest30__data_i case - assign $4\src20__data_o$next[1:0]$10753 $3\src20__data_o$next[1:0]$10752 + assign $4\src20__data_o$next[1:0]$10668 $3\src20__data_o$next[1:0]$10667 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[1:0]$10754 \w0__data_i + assign $5\src20__data_o$next[1:0]$10669 \w0__data_i case - assign $5\src20__data_o$next[1:0]$10754 $4\src20__data_o$next[1:0]$10753 + assign $5\src20__data_o$next[1:0]$10669 $4\src20__data_o$next[1:0]$10668 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[1:0]$10755 \reg + assign $6\src20__data_o$next[1:0]$10670 \reg case - assign $6\src20__data_o$next[1:0]$10755 $5\src20__data_o$next[1:0]$10754 + assign $6\src20__data_o$next[1:0]$10670 $5\src20__data_o$next[1:0]$10669 end case - assign $1\src20__data_o$next[1:0]$10750 2'00 + assign $1\src20__data_o$next[1:0]$10665 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src20__data_o$next[1:0]$10756 2'00 + assign $7\src20__data_o$next[1:0]$10671 2'00 case - assign $7\src20__data_o$next[1:0]$10756 $1\src20__data_o$next[1:0]$10750 + assign $7\src20__data_o$next[1:0]$10671 $1\src20__data_o$next[1:0]$10665 end sync always - update \src20__data_o$next $0\src20__data_o$next[1:0]$10749 + update \src20__data_o$next $0\src20__data_o$next[1:0]$10664 end - attribute \src "libresoc.v:177551.3-177586.6" - process $proc$libresoc.v:177551$10757 + attribute \src "libresoc.v:178187.3-178222.6" + process $proc$libresoc.v:178187$10672 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10758 $1\wr_detect$4[0:0]$10759 - attribute \src "libresoc.v:177552.5-177552.29" + assign $0\wr_detect$4[0:0]$10673 $1\wr_detect$4[0:0]$10674 + attribute \src "libresoc.v:178188.5-178188.29" switch \initial - attribute \src "libresoc.v:177552.9-177552.17" + attribute \src "libresoc.v:178188.9-178188.17" case 1'1 case end @@ -364691,58 +330994,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10759 $5\wr_detect$4[0:0]$10763 + assign $1\wr_detect$4[0:0]$10674 $5\wr_detect$4[0:0]$10678 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10760 1'1 + assign $2\wr_detect$4[0:0]$10675 1'1 case - assign $2\wr_detect$4[0:0]$10760 1'0 + assign $2\wr_detect$4[0:0]$10675 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10761 1'1 + assign $3\wr_detect$4[0:0]$10676 1'1 case - assign $3\wr_detect$4[0:0]$10761 $2\wr_detect$4[0:0]$10760 + assign $3\wr_detect$4[0:0]$10676 $2\wr_detect$4[0:0]$10675 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10762 1'1 + assign $4\wr_detect$4[0:0]$10677 1'1 case - assign $4\wr_detect$4[0:0]$10762 $3\wr_detect$4[0:0]$10761 + assign $4\wr_detect$4[0:0]$10677 $3\wr_detect$4[0:0]$10676 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10763 1'1 + assign $5\wr_detect$4[0:0]$10678 1'1 case - assign $5\wr_detect$4[0:0]$10763 $4\wr_detect$4[0:0]$10762 + assign $5\wr_detect$4[0:0]$10678 $4\wr_detect$4[0:0]$10677 end case - assign $1\wr_detect$4[0:0]$10759 1'0 + assign $1\wr_detect$4[0:0]$10674 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10758 + update \wr_detect$4 $0\wr_detect$4[0:0]$10673 end - attribute \src "libresoc.v:177587.3-177632.6" - process $proc$libresoc.v:177587$10764 + attribute \src "libresoc.v:178223.3-178268.6" + process $proc$libresoc.v:178223$10679 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[1:0]$10765 $7\src30__data_o$next[1:0]$10772 - attribute \src "libresoc.v:177588.5-177588.29" + assign $0\src30__data_o$next[1:0]$10680 $7\src30__data_o$next[1:0]$10687 + attribute \src "libresoc.v:178224.5-178224.29" switch \initial - attribute \src "libresoc.v:177588.9-177588.17" + attribute \src "libresoc.v:178224.9-178224.17" case 1'1 case end @@ -364755,75 +331058,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[1:0]$10766 $6\src30__data_o$next[1:0]$10771 + assign $1\src30__data_o$next[1:0]$10681 $6\src30__data_o$next[1:0]$10686 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[1:0]$10767 \dest10__data_i + assign $2\src30__data_o$next[1:0]$10682 \dest10__data_i case - assign $2\src30__data_o$next[1:0]$10767 2'00 + assign $2\src30__data_o$next[1:0]$10682 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[1:0]$10768 \dest20__data_i + assign $3\src30__data_o$next[1:0]$10683 \dest20__data_i case - assign $3\src30__data_o$next[1:0]$10768 $2\src30__data_o$next[1:0]$10767 + assign $3\src30__data_o$next[1:0]$10683 $2\src30__data_o$next[1:0]$10682 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[1:0]$10769 \dest30__data_i + assign $4\src30__data_o$next[1:0]$10684 \dest30__data_i case - assign $4\src30__data_o$next[1:0]$10769 $3\src30__data_o$next[1:0]$10768 + assign $4\src30__data_o$next[1:0]$10684 $3\src30__data_o$next[1:0]$10683 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[1:0]$10770 \w0__data_i + assign $5\src30__data_o$next[1:0]$10685 \w0__data_i case - assign $5\src30__data_o$next[1:0]$10770 $4\src30__data_o$next[1:0]$10769 + assign $5\src30__data_o$next[1:0]$10685 $4\src30__data_o$next[1:0]$10684 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[1:0]$10771 \reg + assign $6\src30__data_o$next[1:0]$10686 \reg case - assign $6\src30__data_o$next[1:0]$10771 $5\src30__data_o$next[1:0]$10770 + assign $6\src30__data_o$next[1:0]$10686 $5\src30__data_o$next[1:0]$10685 end case - assign $1\src30__data_o$next[1:0]$10766 2'00 + assign $1\src30__data_o$next[1:0]$10681 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src30__data_o$next[1:0]$10772 2'00 + assign $7\src30__data_o$next[1:0]$10687 2'00 case - assign $7\src30__data_o$next[1:0]$10772 $1\src30__data_o$next[1:0]$10766 + assign $7\src30__data_o$next[1:0]$10687 $1\src30__data_o$next[1:0]$10681 end sync always - update \src30__data_o$next $0\src30__data_o$next[1:0]$10765 + update \src30__data_o$next $0\src30__data_o$next[1:0]$10680 end - attribute \src "libresoc.v:177633.3-177668.6" - process $proc$libresoc.v:177633$10773 + attribute \src "libresoc.v:178269.3-178304.6" + process $proc$libresoc.v:178269$10688 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10774 $1\wr_detect$7[0:0]$10775 - attribute \src "libresoc.v:177634.5-177634.29" + assign $0\wr_detect$7[0:0]$10689 $1\wr_detect$7[0:0]$10690 + attribute \src "libresoc.v:178270.5-178270.29" switch \initial - attribute \src "libresoc.v:177634.9-177634.17" + attribute \src "libresoc.v:178270.9-178270.17" case 1'1 case end @@ -364836,58 +331139,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10775 $5\wr_detect$7[0:0]$10779 + assign $1\wr_detect$7[0:0]$10690 $5\wr_detect$7[0:0]$10694 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10776 1'1 + assign $2\wr_detect$7[0:0]$10691 1'1 case - assign $2\wr_detect$7[0:0]$10776 1'0 + assign $2\wr_detect$7[0:0]$10691 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10777 1'1 + assign $3\wr_detect$7[0:0]$10692 1'1 case - assign $3\wr_detect$7[0:0]$10777 $2\wr_detect$7[0:0]$10776 + assign $3\wr_detect$7[0:0]$10692 $2\wr_detect$7[0:0]$10691 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10778 1'1 + assign $4\wr_detect$7[0:0]$10693 1'1 case - assign $4\wr_detect$7[0:0]$10778 $3\wr_detect$7[0:0]$10777 + assign $4\wr_detect$7[0:0]$10693 $3\wr_detect$7[0:0]$10692 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10779 1'1 + assign $5\wr_detect$7[0:0]$10694 1'1 case - assign $5\wr_detect$7[0:0]$10779 $4\wr_detect$7[0:0]$10778 + assign $5\wr_detect$7[0:0]$10694 $4\wr_detect$7[0:0]$10693 end case - assign $1\wr_detect$7[0:0]$10775 1'0 + assign $1\wr_detect$7[0:0]$10690 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10774 + update \wr_detect$7 $0\wr_detect$7[0:0]$10689 end - attribute \src "libresoc.v:177669.3-177714.6" - process $proc$libresoc.v:177669$10780 + attribute \src "libresoc.v:178305.3-178350.6" + process $proc$libresoc.v:178305$10695 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[1:0]$10781 $7\r0__data_o$next[1:0]$10788 - attribute \src "libresoc.v:177670.5-177670.29" + assign $0\r0__data_o$next[1:0]$10696 $7\r0__data_o$next[1:0]$10703 + attribute \src "libresoc.v:178306.5-178306.29" switch \initial - attribute \src "libresoc.v:177670.9-177670.17" + attribute \src "libresoc.v:178306.9-178306.17" case 1'1 case end @@ -364900,75 +331203,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[1:0]$10782 $6\r0__data_o$next[1:0]$10787 + assign $1\r0__data_o$next[1:0]$10697 $6\r0__data_o$next[1:0]$10702 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[1:0]$10783 \dest10__data_i + assign $2\r0__data_o$next[1:0]$10698 \dest10__data_i case - assign $2\r0__data_o$next[1:0]$10783 2'00 + assign $2\r0__data_o$next[1:0]$10698 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[1:0]$10784 \dest20__data_i + assign $3\r0__data_o$next[1:0]$10699 \dest20__data_i case - assign $3\r0__data_o$next[1:0]$10784 $2\r0__data_o$next[1:0]$10783 + assign $3\r0__data_o$next[1:0]$10699 $2\r0__data_o$next[1:0]$10698 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[1:0]$10785 \dest30__data_i + assign $4\r0__data_o$next[1:0]$10700 \dest30__data_i case - assign $4\r0__data_o$next[1:0]$10785 $3\r0__data_o$next[1:0]$10784 + assign $4\r0__data_o$next[1:0]$10700 $3\r0__data_o$next[1:0]$10699 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[1:0]$10786 \w0__data_i + assign $5\r0__data_o$next[1:0]$10701 \w0__data_i case - assign $5\r0__data_o$next[1:0]$10786 $4\r0__data_o$next[1:0]$10785 + assign $5\r0__data_o$next[1:0]$10701 $4\r0__data_o$next[1:0]$10700 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[1:0]$10787 \reg + assign $6\r0__data_o$next[1:0]$10702 \reg case - assign $6\r0__data_o$next[1:0]$10787 $5\r0__data_o$next[1:0]$10786 + assign $6\r0__data_o$next[1:0]$10702 $5\r0__data_o$next[1:0]$10701 end case - assign $1\r0__data_o$next[1:0]$10782 2'00 + assign $1\r0__data_o$next[1:0]$10697 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r0__data_o$next[1:0]$10788 2'00 + assign $7\r0__data_o$next[1:0]$10703 2'00 case - assign $7\r0__data_o$next[1:0]$10788 $1\r0__data_o$next[1:0]$10782 + assign $7\r0__data_o$next[1:0]$10703 $1\r0__data_o$next[1:0]$10697 end sync always - update \r0__data_o$next $0\r0__data_o$next[1:0]$10781 + update \r0__data_o$next $0\r0__data_o$next[1:0]$10696 end - attribute \src "libresoc.v:177715.3-177750.6" - process $proc$libresoc.v:177715$10789 + attribute \src "libresoc.v:178351.3-178386.6" + process $proc$libresoc.v:178351$10704 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10790 $1\wr_detect$10[0:0]$10791 - attribute \src "libresoc.v:177716.5-177716.29" + assign $0\wr_detect$10[0:0]$10705 $1\wr_detect$10[0:0]$10706 + attribute \src "libresoc.v:178352.5-178352.29" switch \initial - attribute \src "libresoc.v:177716.9-177716.17" + attribute \src "libresoc.v:178352.9-178352.17" case 1'1 case end @@ -364981,61 +331284,61 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10791 $5\wr_detect$10[0:0]$10795 + assign $1\wr_detect$10[0:0]$10706 $5\wr_detect$10[0:0]$10710 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10792 1'1 + assign $2\wr_detect$10[0:0]$10707 1'1 case - assign $2\wr_detect$10[0:0]$10792 1'0 + assign $2\wr_detect$10[0:0]$10707 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10793 1'1 + assign $3\wr_detect$10[0:0]$10708 1'1 case - assign $3\wr_detect$10[0:0]$10793 $2\wr_detect$10[0:0]$10792 + assign $3\wr_detect$10[0:0]$10708 $2\wr_detect$10[0:0]$10707 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10794 1'1 + assign $4\wr_detect$10[0:0]$10709 1'1 case - assign $4\wr_detect$10[0:0]$10794 $3\wr_detect$10[0:0]$10793 + assign $4\wr_detect$10[0:0]$10709 $3\wr_detect$10[0:0]$10708 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10795 1'1 + assign $5\wr_detect$10[0:0]$10710 1'1 case - assign $5\wr_detect$10[0:0]$10795 $4\wr_detect$10[0:0]$10794 + assign $5\wr_detect$10[0:0]$10710 $4\wr_detect$10[0:0]$10709 end case - assign $1\wr_detect$10[0:0]$10791 1'0 + assign $1\wr_detect$10[0:0]$10706 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10790 + update \wr_detect$10 $0\wr_detect$10[0:0]$10705 end - attribute \src "libresoc.v:177751.3-177783.6" - process $proc$libresoc.v:177751$10796 + attribute \src "libresoc.v:178387.3-178419.6" + process $proc$libresoc.v:178387$10711 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10797 $5\reg$next[1:0]$10802 - attribute \src "libresoc.v:177752.5-177752.29" + assign $0\reg$next[1:0]$10712 $5\reg$next[1:0]$10717 + attribute \src "libresoc.v:178388.5-178388.29" switch \initial - attribute \src "libresoc.v:177752.9-177752.17" + attribute \src "libresoc.v:178388.9-178388.17" case 1'1 case end @@ -365044,179 +331347,179 @@ module \reg_0$132 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10798 \dest10__data_i + assign $1\reg$next[1:0]$10713 \dest10__data_i case - assign $1\reg$next[1:0]$10798 \reg + assign $1\reg$next[1:0]$10713 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10799 \dest20__data_i + assign $2\reg$next[1:0]$10714 \dest20__data_i case - assign $2\reg$next[1:0]$10799 $1\reg$next[1:0]$10798 + assign $2\reg$next[1:0]$10714 $1\reg$next[1:0]$10713 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10800 \dest30__data_i + assign $3\reg$next[1:0]$10715 \dest30__data_i case - assign $3\reg$next[1:0]$10800 $2\reg$next[1:0]$10799 + assign $3\reg$next[1:0]$10715 $2\reg$next[1:0]$10714 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10801 \w0__data_i + assign $4\reg$next[1:0]$10716 \w0__data_i case - assign $4\reg$next[1:0]$10801 $3\reg$next[1:0]$10800 + assign $4\reg$next[1:0]$10716 $3\reg$next[1:0]$10715 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10802 2'00 + assign $5\reg$next[1:0]$10717 2'00 case - assign $5\reg$next[1:0]$10802 $4\reg$next[1:0]$10801 + assign $5\reg$next[1:0]$10717 $4\reg$next[1:0]$10716 end sync always - update \reg$next $0\reg$next[1:0]$10797 + update \reg$next $0\reg$next[1:0]$10712 end - connect \$9 $not$libresoc.v:177409$10729_Y - connect \$1 $not$libresoc.v:177410$10730_Y - connect \$3 $not$libresoc.v:177411$10731_Y - connect \$6 $not$libresoc.v:177412$10732_Y + connect \$9 $not$libresoc.v:178045$10644_Y + connect \$1 $not$libresoc.v:178046$10645_Y + connect \$3 $not$libresoc.v:178047$10646_Y + connect \$6 $not$libresoc.v:178048$10647_Y end -attribute \src "libresoc.v:177788.1-178137.10" +attribute \src "libresoc.v:178424.1-178773.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" attribute \generator "nMigen" module \reg_0$135 - attribute \src "libresoc.v:177858.3-177903.6" - wire width 64 $0\cia0__data_o$next[63:0]$10817 - attribute \src "libresoc.v:177856.3-177857.41" + attribute \src "libresoc.v:178494.3-178539.6" + wire width 64 $0\cia0__data_o$next[63:0]$10732 + attribute \src "libresoc.v:178492.3-178493.41" wire width 64 $0\cia0__data_o[63:0] - attribute \src "libresoc.v:177789.7-177789.20" + attribute \src "libresoc.v:178425.7-178425.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177940.3-177985.6" - wire width 64 $0\msr0__data_o$next[63:0]$10827 - attribute \src "libresoc.v:177854.3-177855.41" + attribute \src "libresoc.v:178576.3-178621.6" + wire width 64 $0\msr0__data_o$next[63:0]$10742 + attribute \src "libresoc.v:178490.3-178491.41" wire width 64 $0\msr0__data_o[63:0] - attribute \src "libresoc.v:178104.3-178136.6" - wire width 64 $0\reg$next[63:0]$10859 - attribute \src "libresoc.v:177850.3-177851.25" + attribute \src "libresoc.v:178740.3-178772.6" + wire width 64 $0\reg$next[63:0]$10774 + attribute \src "libresoc.v:178486.3-178487.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:178022.3-178067.6" - wire width 64 $0\sv0__data_o$next[63:0]$10843 - attribute \src "libresoc.v:177852.3-177853.39" + attribute \src "libresoc.v:178658.3-178703.6" + wire width 64 $0\sv0__data_o$next[63:0]$10758 + attribute \src "libresoc.v:178488.3-178489.39" wire width 64 $0\sv0__data_o[63:0] - attribute \src "libresoc.v:177986.3-178021.6" - wire $0\wr_detect$4[0:0]$10836 - attribute \src "libresoc.v:178068.3-178103.6" - wire $0\wr_detect$7[0:0]$10852 - attribute \src "libresoc.v:177904.3-177939.6" + attribute \src "libresoc.v:178622.3-178657.6" + wire $0\wr_detect$4[0:0]$10751 + attribute \src "libresoc.v:178704.3-178739.6" + wire $0\wr_detect$7[0:0]$10767 + attribute \src "libresoc.v:178540.3-178575.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:177858.3-177903.6" - wire width 64 $1\cia0__data_o$next[63:0]$10818 - attribute \src "libresoc.v:177798.14-177798.49" + attribute \src "libresoc.v:178494.3-178539.6" + wire width 64 $1\cia0__data_o$next[63:0]$10733 + attribute \src "libresoc.v:178434.14-178434.49" wire width 64 $1\cia0__data_o[63:0] - attribute \src "libresoc.v:177940.3-177985.6" - wire width 64 $1\msr0__data_o$next[63:0]$10828 - attribute \src "libresoc.v:177815.14-177815.49" + attribute \src "libresoc.v:178576.3-178621.6" + wire width 64 $1\msr0__data_o$next[63:0]$10743 + attribute \src "libresoc.v:178451.14-178451.49" wire width 64 $1\msr0__data_o[63:0] - attribute \src "libresoc.v:178104.3-178136.6" - wire width 64 $1\reg$next[63:0]$10860 - attribute \src "libresoc.v:177827.14-177827.42" + attribute \src "libresoc.v:178740.3-178772.6" + wire width 64 $1\reg$next[63:0]$10775 + attribute \src "libresoc.v:178463.14-178463.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:178022.3-178067.6" - wire width 64 $1\sv0__data_o$next[63:0]$10844 - attribute \src "libresoc.v:177834.14-177834.48" + attribute \src "libresoc.v:178658.3-178703.6" + wire width 64 $1\sv0__data_o$next[63:0]$10759 + attribute \src "libresoc.v:178470.14-178470.48" wire width 64 $1\sv0__data_o[63:0] - attribute \src "libresoc.v:177986.3-178021.6" - wire $1\wr_detect$4[0:0]$10837 - attribute \src "libresoc.v:178068.3-178103.6" - wire $1\wr_detect$7[0:0]$10853 - attribute \src "libresoc.v:177904.3-177939.6" + attribute \src "libresoc.v:178622.3-178657.6" + wire $1\wr_detect$4[0:0]$10752 + attribute \src "libresoc.v:178704.3-178739.6" + wire $1\wr_detect$7[0:0]$10768 + attribute \src "libresoc.v:178540.3-178575.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:177858.3-177903.6" - wire width 64 $2\cia0__data_o$next[63:0]$10819 - attribute \src "libresoc.v:177940.3-177985.6" - wire width 64 $2\msr0__data_o$next[63:0]$10829 - attribute \src "libresoc.v:178104.3-178136.6" - wire width 64 $2\reg$next[63:0]$10861 - attribute \src "libresoc.v:178022.3-178067.6" - wire width 64 $2\sv0__data_o$next[63:0]$10845 - attribute \src "libresoc.v:177986.3-178021.6" - wire $2\wr_detect$4[0:0]$10838 - attribute \src "libresoc.v:178068.3-178103.6" - wire $2\wr_detect$7[0:0]$10854 - attribute \src "libresoc.v:177904.3-177939.6" + attribute \src "libresoc.v:178494.3-178539.6" + wire width 64 $2\cia0__data_o$next[63:0]$10734 + attribute \src "libresoc.v:178576.3-178621.6" + wire width 64 $2\msr0__data_o$next[63:0]$10744 + attribute \src "libresoc.v:178740.3-178772.6" + wire width 64 $2\reg$next[63:0]$10776 + attribute \src "libresoc.v:178658.3-178703.6" + wire width 64 $2\sv0__data_o$next[63:0]$10760 + attribute \src "libresoc.v:178622.3-178657.6" + wire $2\wr_detect$4[0:0]$10753 + attribute \src "libresoc.v:178704.3-178739.6" + wire $2\wr_detect$7[0:0]$10769 + attribute \src "libresoc.v:178540.3-178575.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:177858.3-177903.6" - wire width 64 $3\cia0__data_o$next[63:0]$10820 - attribute \src "libresoc.v:177940.3-177985.6" - wire width 64 $3\msr0__data_o$next[63:0]$10830 - attribute \src "libresoc.v:178104.3-178136.6" - wire width 64 $3\reg$next[63:0]$10862 - attribute \src "libresoc.v:178022.3-178067.6" - wire width 64 $3\sv0__data_o$next[63:0]$10846 - attribute \src "libresoc.v:177986.3-178021.6" - wire $3\wr_detect$4[0:0]$10839 - attribute \src "libresoc.v:178068.3-178103.6" - wire $3\wr_detect$7[0:0]$10855 - attribute \src "libresoc.v:177904.3-177939.6" + attribute \src "libresoc.v:178494.3-178539.6" + wire width 64 $3\cia0__data_o$next[63:0]$10735 + attribute \src "libresoc.v:178576.3-178621.6" + wire width 64 $3\msr0__data_o$next[63:0]$10745 + attribute \src "libresoc.v:178740.3-178772.6" + wire width 64 $3\reg$next[63:0]$10777 + attribute \src "libresoc.v:178658.3-178703.6" + wire width 64 $3\sv0__data_o$next[63:0]$10761 + attribute \src "libresoc.v:178622.3-178657.6" + wire $3\wr_detect$4[0:0]$10754 + attribute \src "libresoc.v:178704.3-178739.6" + wire $3\wr_detect$7[0:0]$10770 + attribute \src "libresoc.v:178540.3-178575.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:177858.3-177903.6" - wire width 64 $4\cia0__data_o$next[63:0]$10821 - attribute \src "libresoc.v:177940.3-177985.6" - wire width 64 $4\msr0__data_o$next[63:0]$10831 - attribute \src "libresoc.v:178104.3-178136.6" - wire width 64 $4\reg$next[63:0]$10863 - attribute \src "libresoc.v:178022.3-178067.6" - wire width 64 $4\sv0__data_o$next[63:0]$10847 - attribute \src "libresoc.v:177986.3-178021.6" - wire $4\wr_detect$4[0:0]$10840 - attribute \src "libresoc.v:178068.3-178103.6" - wire $4\wr_detect$7[0:0]$10856 - attribute \src "libresoc.v:177904.3-177939.6" + attribute \src "libresoc.v:178494.3-178539.6" + wire width 64 $4\cia0__data_o$next[63:0]$10736 + attribute \src "libresoc.v:178576.3-178621.6" + wire width 64 $4\msr0__data_o$next[63:0]$10746 + attribute \src "libresoc.v:178740.3-178772.6" + wire width 64 $4\reg$next[63:0]$10778 + attribute \src "libresoc.v:178658.3-178703.6" + wire width 64 $4\sv0__data_o$next[63:0]$10762 + attribute \src "libresoc.v:178622.3-178657.6" + wire $4\wr_detect$4[0:0]$10755 + attribute \src "libresoc.v:178704.3-178739.6" + wire $4\wr_detect$7[0:0]$10771 + attribute \src "libresoc.v:178540.3-178575.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:177858.3-177903.6" - wire width 64 $5\cia0__data_o$next[63:0]$10822 - attribute \src "libresoc.v:177940.3-177985.6" - wire width 64 $5\msr0__data_o$next[63:0]$10832 - attribute \src "libresoc.v:178104.3-178136.6" - wire width 64 $5\reg$next[63:0]$10864 - attribute \src "libresoc.v:178022.3-178067.6" - wire width 64 $5\sv0__data_o$next[63:0]$10848 - attribute \src "libresoc.v:177986.3-178021.6" - wire $5\wr_detect$4[0:0]$10841 - attribute \src "libresoc.v:178068.3-178103.6" - wire $5\wr_detect$7[0:0]$10857 - attribute \src "libresoc.v:177904.3-177939.6" + attribute \src "libresoc.v:178494.3-178539.6" + wire width 64 $5\cia0__data_o$next[63:0]$10737 + attribute \src "libresoc.v:178576.3-178621.6" + wire width 64 $5\msr0__data_o$next[63:0]$10747 + attribute \src "libresoc.v:178740.3-178772.6" + wire width 64 $5\reg$next[63:0]$10779 + attribute \src "libresoc.v:178658.3-178703.6" + wire width 64 $5\sv0__data_o$next[63:0]$10763 + attribute \src "libresoc.v:178622.3-178657.6" + wire $5\wr_detect$4[0:0]$10756 + attribute \src "libresoc.v:178704.3-178739.6" + wire $5\wr_detect$7[0:0]$10772 + attribute \src "libresoc.v:178540.3-178575.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:177858.3-177903.6" - wire width 64 $6\cia0__data_o$next[63:0]$10823 - attribute \src "libresoc.v:177940.3-177985.6" - wire width 64 $6\msr0__data_o$next[63:0]$10833 - attribute \src "libresoc.v:178022.3-178067.6" - wire width 64 $6\sv0__data_o$next[63:0]$10849 - attribute \src "libresoc.v:177858.3-177903.6" - wire width 64 $7\cia0__data_o$next[63:0]$10824 - attribute \src "libresoc.v:177940.3-177985.6" - wire width 64 $7\msr0__data_o$next[63:0]$10834 - attribute \src "libresoc.v:178022.3-178067.6" - wire width 64 $7\sv0__data_o$next[63:0]$10850 - attribute \src "libresoc.v:177847.17-177847.100" - wire $not$libresoc.v:177847$10809_Y - attribute \src "libresoc.v:177848.17-177848.103" - wire $not$libresoc.v:177848$10810_Y - attribute \src "libresoc.v:177849.17-177849.103" - wire $not$libresoc.v:177849$10811_Y + attribute \src "libresoc.v:178494.3-178539.6" + wire width 64 $6\cia0__data_o$next[63:0]$10738 + attribute \src "libresoc.v:178576.3-178621.6" + wire width 64 $6\msr0__data_o$next[63:0]$10748 + attribute \src "libresoc.v:178658.3-178703.6" + wire width 64 $6\sv0__data_o$next[63:0]$10764 + attribute \src "libresoc.v:178494.3-178539.6" + wire width 64 $7\cia0__data_o$next[63:0]$10739 + attribute \src "libresoc.v:178576.3-178621.6" + wire width 64 $7\msr0__data_o$next[63:0]$10749 + attribute \src "libresoc.v:178658.3-178703.6" + wire width 64 $7\sv0__data_o$next[63:0]$10765 + attribute \src "libresoc.v:178483.17-178483.100" + wire $not$libresoc.v:178483$10724_Y + attribute \src "libresoc.v:178484.17-178484.103" + wire $not$libresoc.v:178484$10725_Y + attribute \src "libresoc.v:178485.17-178485.103" + wire $not$libresoc.v:178485$10726_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -365229,15 +331532,15 @@ module \reg_0$135 wire width 64 \cia0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia0__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr10__wen - attribute \src "libresoc.v:177789.7-177789.15" + attribute \src "libresoc.v:178425.7-178425.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr0__data_i @@ -365274,106 +331577,106 @@ module \reg_0$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177847$10809 + cell $not $not$libresoc.v:178483$10724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:177847$10809_Y + connect \Y $not$libresoc.v:178483$10724_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177848$10810 + cell $not $not$libresoc.v:178484$10725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:177848$10810_Y + connect \Y $not$libresoc.v:178484$10725_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177849$10811 + cell $not $not$libresoc.v:178485$10726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:177849$10811_Y + connect \Y $not$libresoc.v:178485$10726_Y end - attribute \src "libresoc.v:177789.7-177789.20" - process $proc$libresoc.v:177789$10865 + attribute \src "libresoc.v:178425.7-178425.20" + process $proc$libresoc.v:178425$10780 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177798.14-177798.49" - process $proc$libresoc.v:177798$10866 + attribute \src "libresoc.v:178434.14-178434.49" + process $proc$libresoc.v:178434$10781 assign { } { } assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia0__data_o $1\cia0__data_o[63:0] end - attribute \src "libresoc.v:177815.14-177815.49" - process $proc$libresoc.v:177815$10867 + attribute \src "libresoc.v:178451.14-178451.49" + process $proc$libresoc.v:178451$10782 assign { } { } assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr0__data_o $1\msr0__data_o[63:0] end - attribute \src "libresoc.v:177827.14-177827.42" - process $proc$libresoc.v:177827$10868 + attribute \src "libresoc.v:178463.14-178463.42" + process $proc$libresoc.v:178463$10783 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:177834.14-177834.48" - process $proc$libresoc.v:177834$10869 + attribute \src "libresoc.v:178470.14-178470.48" + process $proc$libresoc.v:178470$10784 assign { } { } assign $1\sv0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv0__data_o $1\sv0__data_o[63:0] end - attribute \src "libresoc.v:177850.3-177851.25" - process $proc$libresoc.v:177850$10812 + attribute \src "libresoc.v:178486.3-178487.25" + process $proc$libresoc.v:178486$10727 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:177852.3-177853.39" - process $proc$libresoc.v:177852$10813 + attribute \src "libresoc.v:178488.3-178489.39" + process $proc$libresoc.v:178488$10728 assign { } { } assign $0\sv0__data_o[63:0] \sv0__data_o$next sync posedge \coresync_clk update \sv0__data_o $0\sv0__data_o[63:0] end - attribute \src "libresoc.v:177854.3-177855.41" - process $proc$libresoc.v:177854$10814 + attribute \src "libresoc.v:178490.3-178491.41" + process $proc$libresoc.v:178490$10729 assign { } { } assign $0\msr0__data_o[63:0] \msr0__data_o$next sync posedge \coresync_clk update \msr0__data_o $0\msr0__data_o[63:0] end - attribute \src "libresoc.v:177856.3-177857.41" - process $proc$libresoc.v:177856$10815 + attribute \src "libresoc.v:178492.3-178493.41" + process $proc$libresoc.v:178492$10730 assign { } { } assign $0\cia0__data_o[63:0] \cia0__data_o$next sync posedge \coresync_clk update \cia0__data_o $0\cia0__data_o[63:0] end - attribute \src "libresoc.v:177858.3-177903.6" - process $proc$libresoc.v:177858$10816 + attribute \src "libresoc.v:178494.3-178539.6" + process $proc$libresoc.v:178494$10731 assign { } { } assign { } { } assign { } { } - assign $0\cia0__data_o$next[63:0]$10817 $7\cia0__data_o$next[63:0]$10824 - attribute \src "libresoc.v:177859.5-177859.29" + assign $0\cia0__data_o$next[63:0]$10732 $7\cia0__data_o$next[63:0]$10739 + attribute \src "libresoc.v:178495.5-178495.29" switch \initial - attribute \src "libresoc.v:177859.9-177859.17" + attribute \src "libresoc.v:178495.9-178495.17" case 1'1 case end @@ -365386,75 +331689,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\cia0__data_o$next[63:0]$10818 $6\cia0__data_o$next[63:0]$10823 + assign $1\cia0__data_o$next[63:0]$10733 $6\cia0__data_o$next[63:0]$10738 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia0__data_o$next[63:0]$10819 \nia0__data_i + assign $2\cia0__data_o$next[63:0]$10734 \nia0__data_i case - assign $2\cia0__data_o$next[63:0]$10819 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia0__data_o$next[63:0]$10734 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia0__data_o$next[63:0]$10820 \msr0__data_i + assign $3\cia0__data_o$next[63:0]$10735 \msr0__data_i case - assign $3\cia0__data_o$next[63:0]$10820 $2\cia0__data_o$next[63:0]$10819 + assign $3\cia0__data_o$next[63:0]$10735 $2\cia0__data_o$next[63:0]$10734 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia0__data_o$next[63:0]$10821 \sv0__data_i + assign $4\cia0__data_o$next[63:0]$10736 \sv0__data_i case - assign $4\cia0__data_o$next[63:0]$10821 $3\cia0__data_o$next[63:0]$10820 + assign $4\cia0__data_o$next[63:0]$10736 $3\cia0__data_o$next[63:0]$10735 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia0__data_o$next[63:0]$10822 \d_wr10__data_i + assign $5\cia0__data_o$next[63:0]$10737 \d_wr10__data_i case - assign $5\cia0__data_o$next[63:0]$10822 $4\cia0__data_o$next[63:0]$10821 + assign $5\cia0__data_o$next[63:0]$10737 $4\cia0__data_o$next[63:0]$10736 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia0__data_o$next[63:0]$10823 \reg + assign $6\cia0__data_o$next[63:0]$10738 \reg case - assign $6\cia0__data_o$next[63:0]$10823 $5\cia0__data_o$next[63:0]$10822 + assign $6\cia0__data_o$next[63:0]$10738 $5\cia0__data_o$next[63:0]$10737 end case - assign $1\cia0__data_o$next[63:0]$10818 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia0__data_o$next[63:0]$10733 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia0__data_o$next[63:0]$10824 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia0__data_o$next[63:0]$10739 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia0__data_o$next[63:0]$10824 $1\cia0__data_o$next[63:0]$10818 + assign $7\cia0__data_o$next[63:0]$10739 $1\cia0__data_o$next[63:0]$10733 end sync always - update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10817 + update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10732 end - attribute \src "libresoc.v:177904.3-177939.6" - process $proc$libresoc.v:177904$10825 + attribute \src "libresoc.v:178540.3-178575.6" + process $proc$libresoc.v:178540$10740 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177905.5-177905.29" + attribute \src "libresoc.v:178541.5-178541.29" switch \initial - attribute \src "libresoc.v:177905.9-177905.17" + attribute \src "libresoc.v:178541.9-178541.17" case 1'1 case end @@ -365510,15 +331813,15 @@ module \reg_0$135 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177940.3-177985.6" - process $proc$libresoc.v:177940$10826 + attribute \src "libresoc.v:178576.3-178621.6" + process $proc$libresoc.v:178576$10741 assign { } { } assign { } { } assign { } { } - assign $0\msr0__data_o$next[63:0]$10827 $7\msr0__data_o$next[63:0]$10834 - attribute \src "libresoc.v:177941.5-177941.29" + assign $0\msr0__data_o$next[63:0]$10742 $7\msr0__data_o$next[63:0]$10749 + attribute \src "libresoc.v:178577.5-178577.29" switch \initial - attribute \src "libresoc.v:177941.9-177941.17" + attribute \src "libresoc.v:178577.9-178577.17" case 1'1 case end @@ -365531,75 +331834,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\msr0__data_o$next[63:0]$10828 $6\msr0__data_o$next[63:0]$10833 + assign $1\msr0__data_o$next[63:0]$10743 $6\msr0__data_o$next[63:0]$10748 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr0__data_o$next[63:0]$10829 \nia0__data_i + assign $2\msr0__data_o$next[63:0]$10744 \nia0__data_i case - assign $2\msr0__data_o$next[63:0]$10829 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr0__data_o$next[63:0]$10744 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr0__data_o$next[63:0]$10830 \msr0__data_i + assign $3\msr0__data_o$next[63:0]$10745 \msr0__data_i case - assign $3\msr0__data_o$next[63:0]$10830 $2\msr0__data_o$next[63:0]$10829 + assign $3\msr0__data_o$next[63:0]$10745 $2\msr0__data_o$next[63:0]$10744 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr0__data_o$next[63:0]$10831 \sv0__data_i + assign $4\msr0__data_o$next[63:0]$10746 \sv0__data_i case - assign $4\msr0__data_o$next[63:0]$10831 $3\msr0__data_o$next[63:0]$10830 + assign $4\msr0__data_o$next[63:0]$10746 $3\msr0__data_o$next[63:0]$10745 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr0__data_o$next[63:0]$10832 \d_wr10__data_i + assign $5\msr0__data_o$next[63:0]$10747 \d_wr10__data_i case - assign $5\msr0__data_o$next[63:0]$10832 $4\msr0__data_o$next[63:0]$10831 + assign $5\msr0__data_o$next[63:0]$10747 $4\msr0__data_o$next[63:0]$10746 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr0__data_o$next[63:0]$10833 \reg + assign $6\msr0__data_o$next[63:0]$10748 \reg case - assign $6\msr0__data_o$next[63:0]$10833 $5\msr0__data_o$next[63:0]$10832 + assign $6\msr0__data_o$next[63:0]$10748 $5\msr0__data_o$next[63:0]$10747 end case - assign $1\msr0__data_o$next[63:0]$10828 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr0__data_o$next[63:0]$10743 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr0__data_o$next[63:0]$10834 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr0__data_o$next[63:0]$10749 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr0__data_o$next[63:0]$10834 $1\msr0__data_o$next[63:0]$10828 + assign $7\msr0__data_o$next[63:0]$10749 $1\msr0__data_o$next[63:0]$10743 end sync always - update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10827 + update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10742 end - attribute \src "libresoc.v:177986.3-178021.6" - process $proc$libresoc.v:177986$10835 + attribute \src "libresoc.v:178622.3-178657.6" + process $proc$libresoc.v:178622$10750 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10836 $1\wr_detect$4[0:0]$10837 - attribute \src "libresoc.v:177987.5-177987.29" + assign $0\wr_detect$4[0:0]$10751 $1\wr_detect$4[0:0]$10752 + attribute \src "libresoc.v:178623.5-178623.29" switch \initial - attribute \src "libresoc.v:177987.9-177987.17" + attribute \src "libresoc.v:178623.9-178623.17" case 1'1 case end @@ -365612,58 +331915,58 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10837 $5\wr_detect$4[0:0]$10841 + assign $1\wr_detect$4[0:0]$10752 $5\wr_detect$4[0:0]$10756 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10838 1'1 + assign $2\wr_detect$4[0:0]$10753 1'1 case - assign $2\wr_detect$4[0:0]$10838 1'0 + assign $2\wr_detect$4[0:0]$10753 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10839 1'1 + assign $3\wr_detect$4[0:0]$10754 1'1 case - assign $3\wr_detect$4[0:0]$10839 $2\wr_detect$4[0:0]$10838 + assign $3\wr_detect$4[0:0]$10754 $2\wr_detect$4[0:0]$10753 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10840 1'1 + assign $4\wr_detect$4[0:0]$10755 1'1 case - assign $4\wr_detect$4[0:0]$10840 $3\wr_detect$4[0:0]$10839 + assign $4\wr_detect$4[0:0]$10755 $3\wr_detect$4[0:0]$10754 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10841 1'1 + assign $5\wr_detect$4[0:0]$10756 1'1 case - assign $5\wr_detect$4[0:0]$10841 $4\wr_detect$4[0:0]$10840 + assign $5\wr_detect$4[0:0]$10756 $4\wr_detect$4[0:0]$10755 end case - assign $1\wr_detect$4[0:0]$10837 1'0 + assign $1\wr_detect$4[0:0]$10752 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10836 + update \wr_detect$4 $0\wr_detect$4[0:0]$10751 end - attribute \src "libresoc.v:178022.3-178067.6" - process $proc$libresoc.v:178022$10842 + attribute \src "libresoc.v:178658.3-178703.6" + process $proc$libresoc.v:178658$10757 assign { } { } assign { } { } assign { } { } - assign $0\sv0__data_o$next[63:0]$10843 $7\sv0__data_o$next[63:0]$10850 - attribute \src "libresoc.v:178023.5-178023.29" + assign $0\sv0__data_o$next[63:0]$10758 $7\sv0__data_o$next[63:0]$10765 + attribute \src "libresoc.v:178659.5-178659.29" switch \initial - attribute \src "libresoc.v:178023.9-178023.17" + attribute \src "libresoc.v:178659.9-178659.17" case 1'1 case end @@ -365676,75 +331979,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\sv0__data_o$next[63:0]$10844 $6\sv0__data_o$next[63:0]$10849 + assign $1\sv0__data_o$next[63:0]$10759 $6\sv0__data_o$next[63:0]$10764 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv0__data_o$next[63:0]$10845 \nia0__data_i + assign $2\sv0__data_o$next[63:0]$10760 \nia0__data_i case - assign $2\sv0__data_o$next[63:0]$10845 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv0__data_o$next[63:0]$10760 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv0__data_o$next[63:0]$10846 \msr0__data_i + assign $3\sv0__data_o$next[63:0]$10761 \msr0__data_i case - assign $3\sv0__data_o$next[63:0]$10846 $2\sv0__data_o$next[63:0]$10845 + assign $3\sv0__data_o$next[63:0]$10761 $2\sv0__data_o$next[63:0]$10760 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv0__data_o$next[63:0]$10847 \sv0__data_i + assign $4\sv0__data_o$next[63:0]$10762 \sv0__data_i case - assign $4\sv0__data_o$next[63:0]$10847 $3\sv0__data_o$next[63:0]$10846 + assign $4\sv0__data_o$next[63:0]$10762 $3\sv0__data_o$next[63:0]$10761 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv0__data_o$next[63:0]$10848 \d_wr10__data_i + assign $5\sv0__data_o$next[63:0]$10763 \d_wr10__data_i case - assign $5\sv0__data_o$next[63:0]$10848 $4\sv0__data_o$next[63:0]$10847 + assign $5\sv0__data_o$next[63:0]$10763 $4\sv0__data_o$next[63:0]$10762 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv0__data_o$next[63:0]$10849 \reg + assign $6\sv0__data_o$next[63:0]$10764 \reg case - assign $6\sv0__data_o$next[63:0]$10849 $5\sv0__data_o$next[63:0]$10848 + assign $6\sv0__data_o$next[63:0]$10764 $5\sv0__data_o$next[63:0]$10763 end case - assign $1\sv0__data_o$next[63:0]$10844 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv0__data_o$next[63:0]$10759 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv0__data_o$next[63:0]$10850 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv0__data_o$next[63:0]$10765 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv0__data_o$next[63:0]$10850 $1\sv0__data_o$next[63:0]$10844 + assign $7\sv0__data_o$next[63:0]$10765 $1\sv0__data_o$next[63:0]$10759 end sync always - update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10843 + update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10758 end - attribute \src "libresoc.v:178068.3-178103.6" - process $proc$libresoc.v:178068$10851 + attribute \src "libresoc.v:178704.3-178739.6" + process $proc$libresoc.v:178704$10766 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10852 $1\wr_detect$7[0:0]$10853 - attribute \src "libresoc.v:178069.5-178069.29" + assign $0\wr_detect$7[0:0]$10767 $1\wr_detect$7[0:0]$10768 + attribute \src "libresoc.v:178705.5-178705.29" switch \initial - attribute \src "libresoc.v:178069.9-178069.17" + attribute \src "libresoc.v:178705.9-178705.17" case 1'1 case end @@ -365757,61 +332060,61 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10853 $5\wr_detect$7[0:0]$10857 + assign $1\wr_detect$7[0:0]$10768 $5\wr_detect$7[0:0]$10772 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10854 1'1 + assign $2\wr_detect$7[0:0]$10769 1'1 case - assign $2\wr_detect$7[0:0]$10854 1'0 + assign $2\wr_detect$7[0:0]$10769 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10855 1'1 + assign $3\wr_detect$7[0:0]$10770 1'1 case - assign $3\wr_detect$7[0:0]$10855 $2\wr_detect$7[0:0]$10854 + assign $3\wr_detect$7[0:0]$10770 $2\wr_detect$7[0:0]$10769 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10856 1'1 + assign $4\wr_detect$7[0:0]$10771 1'1 case - assign $4\wr_detect$7[0:0]$10856 $3\wr_detect$7[0:0]$10855 + assign $4\wr_detect$7[0:0]$10771 $3\wr_detect$7[0:0]$10770 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10857 1'1 + assign $5\wr_detect$7[0:0]$10772 1'1 case - assign $5\wr_detect$7[0:0]$10857 $4\wr_detect$7[0:0]$10856 + assign $5\wr_detect$7[0:0]$10772 $4\wr_detect$7[0:0]$10771 end case - assign $1\wr_detect$7[0:0]$10853 1'0 + assign $1\wr_detect$7[0:0]$10768 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10852 + update \wr_detect$7 $0\wr_detect$7[0:0]$10767 end - attribute \src "libresoc.v:178104.3-178136.6" - process $proc$libresoc.v:178104$10858 + attribute \src "libresoc.v:178740.3-178772.6" + process $proc$libresoc.v:178740$10773 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$10859 $5\reg$next[63:0]$10864 - attribute \src "libresoc.v:178105.5-178105.29" + assign $0\reg$next[63:0]$10774 $5\reg$next[63:0]$10779 + attribute \src "libresoc.v:178741.5-178741.29" switch \initial - attribute \src "libresoc.v:178105.9-178105.17" + attribute \src "libresoc.v:178741.9-178741.17" case 1'1 case end @@ -365820,324 +332123,286 @@ module \reg_0$135 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$10860 \nia0__data_i + assign $1\reg$next[63:0]$10775 \nia0__data_i case - assign $1\reg$next[63:0]$10860 \reg + assign $1\reg$next[63:0]$10775 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$10861 \msr0__data_i + assign $2\reg$next[63:0]$10776 \msr0__data_i case - assign $2\reg$next[63:0]$10861 $1\reg$next[63:0]$10860 + assign $2\reg$next[63:0]$10776 $1\reg$next[63:0]$10775 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$10862 \sv0__data_i + assign $3\reg$next[63:0]$10777 \sv0__data_i case - assign $3\reg$next[63:0]$10862 $2\reg$next[63:0]$10861 + assign $3\reg$next[63:0]$10777 $2\reg$next[63:0]$10776 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$10863 \d_wr10__data_i + assign $4\reg$next[63:0]$10778 \d_wr10__data_i case - assign $4\reg$next[63:0]$10863 $3\reg$next[63:0]$10862 + assign $4\reg$next[63:0]$10778 $3\reg$next[63:0]$10777 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$10864 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$10779 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$10864 $4\reg$next[63:0]$10863 + assign $5\reg$next[63:0]$10779 $4\reg$next[63:0]$10778 end sync always - update \reg$next $0\reg$next[63:0]$10859 + update \reg$next $0\reg$next[63:0]$10774 end - connect \$1 $not$libresoc.v:177847$10809_Y - connect \$3 $not$libresoc.v:177848$10810_Y - connect \$6 $not$libresoc.v:177849$10811_Y + connect \$1 $not$libresoc.v:178483$10724_Y + connect \$3 $not$libresoc.v:178484$10725_Y + connect \$6 $not$libresoc.v:178485$10726_Y end -attribute \src "libresoc.v:178141.1-178696.10" +attribute \src "libresoc.v:178777.1-179248.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" attribute \generator "nMigen" module \reg_1 - attribute \src "libresoc.v:178249.3-178288.6" - wire width 4 $0\cr_pred1__data_o$next[3:0]$10884 - attribute \src "libresoc.v:178247.3-178248.49" - wire width 4 $0\cr_pred1__data_o[3:0] - attribute \src "libresoc.v:178142.7-178142.20" + attribute \src "libresoc.v:178778.7-178778.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178626.3-178665.6" - wire width 4 $0\r1__data_o$next[3:0]$10955 - attribute \src "libresoc.v:178239.3-178240.37" + attribute \src "libresoc.v:179108.3-179147.6" + wire width 4 $0\r1__data_o$next[3:0]$10840 + attribute \src "libresoc.v:178863.3-178864.37" wire width 4 $0\r1__data_o[3:0] - attribute \src "libresoc.v:178319.3-178358.6" - wire width 4 $0\r21__data_o$next[3:0]$10893 - attribute \src "libresoc.v:178237.3-178238.39" + attribute \src "libresoc.v:179178.3-179217.6" + wire width 4 $0\r21__data_o$next[3:0]$10854 + attribute \src "libresoc.v:178861.3-178862.39" wire width 4 $0\r21__data_o[3:0] - attribute \src "libresoc.v:178389.3-178415.6" - wire width 4 $0\reg$next[3:0]$10907 - attribute \src "libresoc.v:178235.3-178236.25" + attribute \src "libresoc.v:178941.3-178967.6" + wire width 4 $0\reg$next[3:0]$10806 + attribute \src "libresoc.v:178859.3-178860.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:178416.3-178455.6" - wire width 4 $0\src11__data_o$next[3:0]$10913 - attribute \src "libresoc.v:178245.3-178246.43" + attribute \src "libresoc.v:178871.3-178910.6" + wire width 4 $0\src11__data_o$next[3:0]$10797 + attribute \src "libresoc.v:178869.3-178870.43" wire width 4 $0\src11__data_o[3:0] - attribute \src "libresoc.v:178486.3-178525.6" - wire width 4 $0\src21__data_o$next[3:0]$10927 - attribute \src "libresoc.v:178243.3-178244.43" + attribute \src "libresoc.v:178968.3-179007.6" + wire width 4 $0\src21__data_o$next[3:0]$10812 + attribute \src "libresoc.v:178867.3-178868.43" wire width 4 $0\src21__data_o[3:0] - attribute \src "libresoc.v:178556.3-178595.6" - wire width 4 $0\src31__data_o$next[3:0]$10941 - attribute \src "libresoc.v:178241.3-178242.43" + attribute \src "libresoc.v:179038.3-179077.6" + wire width 4 $0\src31__data_o$next[3:0]$10826 + attribute \src "libresoc.v:178865.3-178866.43" wire width 4 $0\src31__data_o[3:0] - attribute \src "libresoc.v:178596.3-178625.6" - wire $0\wr_detect$10[0:0]$10949 - attribute \src "libresoc.v:178666.3-178695.6" - wire $0\wr_detect$13[0:0]$10963 - attribute \src "libresoc.v:178359.3-178388.6" - wire $0\wr_detect$16[0:0]$10901 - attribute \src "libresoc.v:178456.3-178485.6" - wire $0\wr_detect$4[0:0]$10921 - attribute \src "libresoc.v:178526.3-178555.6" - wire $0\wr_detect$7[0:0]$10935 - attribute \src "libresoc.v:178289.3-178318.6" + attribute \src "libresoc.v:179148.3-179177.6" + wire $0\wr_detect$10[0:0]$10848 + attribute \src "libresoc.v:179218.3-179247.6" + wire $0\wr_detect$13[0:0]$10862 + attribute \src "libresoc.v:179008.3-179037.6" + wire $0\wr_detect$4[0:0]$10820 + attribute \src "libresoc.v:179078.3-179107.6" + wire $0\wr_detect$7[0:0]$10834 + attribute \src "libresoc.v:178911.3-178940.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:178249.3-178288.6" - wire width 4 $1\cr_pred1__data_o$next[3:0]$10885 - attribute \src "libresoc.v:178161.13-178161.36" - wire width 4 $1\cr_pred1__data_o[3:0] - attribute \src "libresoc.v:178626.3-178665.6" - wire width 4 $1\r1__data_o$next[3:0]$10956 - attribute \src "libresoc.v:178176.13-178176.30" + attribute \src "libresoc.v:179108.3-179147.6" + wire width 4 $1\r1__data_o$next[3:0]$10841 + attribute \src "libresoc.v:178803.13-178803.30" wire width 4 $1\r1__data_o[3:0] - attribute \src "libresoc.v:178319.3-178358.6" - wire width 4 $1\r21__data_o$next[3:0]$10894 - attribute \src "libresoc.v:178183.13-178183.31" + attribute \src "libresoc.v:179178.3-179217.6" + wire width 4 $1\r21__data_o$next[3:0]$10855 + attribute \src "libresoc.v:178810.13-178810.31" wire width 4 $1\r21__data_o[3:0] - attribute \src "libresoc.v:178389.3-178415.6" - wire width 4 $1\reg$next[3:0]$10908 - attribute \src "libresoc.v:178189.13-178189.25" + attribute \src "libresoc.v:178941.3-178967.6" + wire width 4 $1\reg$next[3:0]$10807 + attribute \src "libresoc.v:178816.13-178816.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:178416.3-178455.6" - wire width 4 $1\src11__data_o$next[3:0]$10914 - attribute \src "libresoc.v:178194.13-178194.33" + attribute \src "libresoc.v:178871.3-178910.6" + wire width 4 $1\src11__data_o$next[3:0]$10798 + attribute \src "libresoc.v:178821.13-178821.33" wire width 4 $1\src11__data_o[3:0] - attribute \src "libresoc.v:178486.3-178525.6" - wire width 4 $1\src21__data_o$next[3:0]$10928 - attribute \src "libresoc.v:178201.13-178201.33" + attribute \src "libresoc.v:178968.3-179007.6" + wire width 4 $1\src21__data_o$next[3:0]$10813 + attribute \src "libresoc.v:178828.13-178828.33" wire width 4 $1\src21__data_o[3:0] - attribute \src "libresoc.v:178556.3-178595.6" - wire width 4 $1\src31__data_o$next[3:0]$10942 - attribute \src "libresoc.v:178208.13-178208.33" + attribute \src "libresoc.v:179038.3-179077.6" + wire width 4 $1\src31__data_o$next[3:0]$10827 + attribute \src "libresoc.v:178835.13-178835.33" wire width 4 $1\src31__data_o[3:0] - attribute \src "libresoc.v:178596.3-178625.6" - wire $1\wr_detect$10[0:0]$10950 - attribute \src "libresoc.v:178666.3-178695.6" - wire $1\wr_detect$13[0:0]$10964 - attribute \src "libresoc.v:178359.3-178388.6" - wire $1\wr_detect$16[0:0]$10902 - attribute \src "libresoc.v:178456.3-178485.6" - wire $1\wr_detect$4[0:0]$10922 - attribute \src "libresoc.v:178526.3-178555.6" - wire $1\wr_detect$7[0:0]$10936 - attribute \src "libresoc.v:178289.3-178318.6" + attribute \src "libresoc.v:179148.3-179177.6" + wire $1\wr_detect$10[0:0]$10849 + attribute \src "libresoc.v:179218.3-179247.6" + wire $1\wr_detect$13[0:0]$10863 + attribute \src "libresoc.v:179008.3-179037.6" + wire $1\wr_detect$4[0:0]$10821 + attribute \src "libresoc.v:179078.3-179107.6" + wire $1\wr_detect$7[0:0]$10835 + attribute \src "libresoc.v:178911.3-178940.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:178249.3-178288.6" - wire width 4 $2\cr_pred1__data_o$next[3:0]$10886 - attribute \src "libresoc.v:178626.3-178665.6" - wire width 4 $2\r1__data_o$next[3:0]$10957 - attribute \src "libresoc.v:178319.3-178358.6" - wire width 4 $2\r21__data_o$next[3:0]$10895 - attribute \src "libresoc.v:178389.3-178415.6" - wire width 4 $2\reg$next[3:0]$10909 - attribute \src "libresoc.v:178416.3-178455.6" - wire width 4 $2\src11__data_o$next[3:0]$10915 - attribute \src "libresoc.v:178486.3-178525.6" - wire width 4 $2\src21__data_o$next[3:0]$10929 - attribute \src "libresoc.v:178556.3-178595.6" - wire width 4 $2\src31__data_o$next[3:0]$10943 - attribute \src "libresoc.v:178596.3-178625.6" - wire $2\wr_detect$10[0:0]$10951 - attribute \src "libresoc.v:178666.3-178695.6" - wire $2\wr_detect$13[0:0]$10965 - attribute \src "libresoc.v:178359.3-178388.6" - wire $2\wr_detect$16[0:0]$10903 - attribute \src "libresoc.v:178456.3-178485.6" - wire $2\wr_detect$4[0:0]$10923 - attribute \src "libresoc.v:178526.3-178555.6" - wire $2\wr_detect$7[0:0]$10937 - attribute \src "libresoc.v:178289.3-178318.6" + attribute \src "libresoc.v:179108.3-179147.6" + wire width 4 $2\r1__data_o$next[3:0]$10842 + attribute \src "libresoc.v:179178.3-179217.6" + wire width 4 $2\r21__data_o$next[3:0]$10856 + attribute \src "libresoc.v:178941.3-178967.6" + wire width 4 $2\reg$next[3:0]$10808 + attribute \src "libresoc.v:178871.3-178910.6" + wire width 4 $2\src11__data_o$next[3:0]$10799 + attribute \src "libresoc.v:178968.3-179007.6" + wire width 4 $2\src21__data_o$next[3:0]$10814 + attribute \src "libresoc.v:179038.3-179077.6" + wire width 4 $2\src31__data_o$next[3:0]$10828 + attribute \src "libresoc.v:179148.3-179177.6" + wire $2\wr_detect$10[0:0]$10850 + attribute \src "libresoc.v:179218.3-179247.6" + wire $2\wr_detect$13[0:0]$10864 + attribute \src "libresoc.v:179008.3-179037.6" + wire $2\wr_detect$4[0:0]$10822 + attribute \src "libresoc.v:179078.3-179107.6" + wire $2\wr_detect$7[0:0]$10836 + attribute \src "libresoc.v:178911.3-178940.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:178249.3-178288.6" - wire width 4 $3\cr_pred1__data_o$next[3:0]$10887 - attribute \src "libresoc.v:178626.3-178665.6" - wire width 4 $3\r1__data_o$next[3:0]$10958 - attribute \src "libresoc.v:178319.3-178358.6" - wire width 4 $3\r21__data_o$next[3:0]$10896 - attribute \src "libresoc.v:178389.3-178415.6" - wire width 4 $3\reg$next[3:0]$10910 - attribute \src "libresoc.v:178416.3-178455.6" - wire width 4 $3\src11__data_o$next[3:0]$10916 - attribute \src "libresoc.v:178486.3-178525.6" - wire width 4 $3\src21__data_o$next[3:0]$10930 - attribute \src "libresoc.v:178556.3-178595.6" - wire width 4 $3\src31__data_o$next[3:0]$10944 - attribute \src "libresoc.v:178596.3-178625.6" - wire $3\wr_detect$10[0:0]$10952 - attribute \src "libresoc.v:178666.3-178695.6" - wire $3\wr_detect$13[0:0]$10966 - attribute \src "libresoc.v:178359.3-178388.6" - wire $3\wr_detect$16[0:0]$10904 - attribute \src "libresoc.v:178456.3-178485.6" - wire $3\wr_detect$4[0:0]$10924 - attribute \src "libresoc.v:178526.3-178555.6" - wire $3\wr_detect$7[0:0]$10938 - attribute \src "libresoc.v:178289.3-178318.6" + attribute \src "libresoc.v:179108.3-179147.6" + wire width 4 $3\r1__data_o$next[3:0]$10843 + attribute \src "libresoc.v:179178.3-179217.6" + wire width 4 $3\r21__data_o$next[3:0]$10857 + attribute \src "libresoc.v:178941.3-178967.6" + wire width 4 $3\reg$next[3:0]$10809 + attribute \src "libresoc.v:178871.3-178910.6" + wire width 4 $3\src11__data_o$next[3:0]$10800 + attribute \src "libresoc.v:178968.3-179007.6" + wire width 4 $3\src21__data_o$next[3:0]$10815 + attribute \src "libresoc.v:179038.3-179077.6" + wire width 4 $3\src31__data_o$next[3:0]$10829 + attribute \src "libresoc.v:179148.3-179177.6" + wire $3\wr_detect$10[0:0]$10851 + attribute \src "libresoc.v:179218.3-179247.6" + wire $3\wr_detect$13[0:0]$10865 + attribute \src "libresoc.v:179008.3-179037.6" + wire $3\wr_detect$4[0:0]$10823 + attribute \src "libresoc.v:179078.3-179107.6" + wire $3\wr_detect$7[0:0]$10837 + attribute \src "libresoc.v:178911.3-178940.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:178249.3-178288.6" - wire width 4 $4\cr_pred1__data_o$next[3:0]$10888 - attribute \src "libresoc.v:178626.3-178665.6" - wire width 4 $4\r1__data_o$next[3:0]$10959 - attribute \src "libresoc.v:178319.3-178358.6" - wire width 4 $4\r21__data_o$next[3:0]$10897 - attribute \src "libresoc.v:178389.3-178415.6" - wire width 4 $4\reg$next[3:0]$10911 - attribute \src "libresoc.v:178416.3-178455.6" - wire width 4 $4\src11__data_o$next[3:0]$10917 - attribute \src "libresoc.v:178486.3-178525.6" - wire width 4 $4\src21__data_o$next[3:0]$10931 - attribute \src "libresoc.v:178556.3-178595.6" - wire width 4 $4\src31__data_o$next[3:0]$10945 - attribute \src "libresoc.v:178596.3-178625.6" - wire $4\wr_detect$10[0:0]$10953 - attribute \src "libresoc.v:178666.3-178695.6" - wire $4\wr_detect$13[0:0]$10967 - attribute \src "libresoc.v:178359.3-178388.6" - wire $4\wr_detect$16[0:0]$10905 - attribute \src "libresoc.v:178456.3-178485.6" - wire $4\wr_detect$4[0:0]$10925 - attribute \src "libresoc.v:178526.3-178555.6" - wire $4\wr_detect$7[0:0]$10939 - attribute \src "libresoc.v:178289.3-178318.6" + attribute \src "libresoc.v:179108.3-179147.6" + wire width 4 $4\r1__data_o$next[3:0]$10844 + attribute \src "libresoc.v:179178.3-179217.6" + wire width 4 $4\r21__data_o$next[3:0]$10858 + attribute \src "libresoc.v:178941.3-178967.6" + wire width 4 $4\reg$next[3:0]$10810 + attribute \src "libresoc.v:178871.3-178910.6" + wire width 4 $4\src11__data_o$next[3:0]$10801 + attribute \src "libresoc.v:178968.3-179007.6" + wire width 4 $4\src21__data_o$next[3:0]$10816 + attribute \src "libresoc.v:179038.3-179077.6" + wire width 4 $4\src31__data_o$next[3:0]$10830 + attribute \src "libresoc.v:179148.3-179177.6" + wire $4\wr_detect$10[0:0]$10852 + attribute \src "libresoc.v:179218.3-179247.6" + wire $4\wr_detect$13[0:0]$10866 + attribute \src "libresoc.v:179008.3-179037.6" + wire $4\wr_detect$4[0:0]$10824 + attribute \src "libresoc.v:179078.3-179107.6" + wire $4\wr_detect$7[0:0]$10838 + attribute \src "libresoc.v:178911.3-178940.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:178249.3-178288.6" - wire width 4 $5\cr_pred1__data_o$next[3:0]$10889 - attribute \src "libresoc.v:178626.3-178665.6" - wire width 4 $5\r1__data_o$next[3:0]$10960 - attribute \src "libresoc.v:178319.3-178358.6" - wire width 4 $5\r21__data_o$next[3:0]$10898 - attribute \src "libresoc.v:178416.3-178455.6" - wire width 4 $5\src11__data_o$next[3:0]$10918 - attribute \src "libresoc.v:178486.3-178525.6" - wire width 4 $5\src21__data_o$next[3:0]$10932 - attribute \src "libresoc.v:178556.3-178595.6" - wire width 4 $5\src31__data_o$next[3:0]$10946 - attribute \src "libresoc.v:178249.3-178288.6" - wire width 4 $6\cr_pred1__data_o$next[3:0]$10890 - attribute \src "libresoc.v:178626.3-178665.6" - wire width 4 $6\r1__data_o$next[3:0]$10961 - attribute \src "libresoc.v:178319.3-178358.6" - wire width 4 $6\r21__data_o$next[3:0]$10899 - attribute \src "libresoc.v:178416.3-178455.6" - wire width 4 $6\src11__data_o$next[3:0]$10919 - attribute \src "libresoc.v:178486.3-178525.6" - wire width 4 $6\src21__data_o$next[3:0]$10933 - attribute \src "libresoc.v:178556.3-178595.6" - wire width 4 $6\src31__data_o$next[3:0]$10947 - attribute \src "libresoc.v:178229.17-178229.104" - wire $not$libresoc.v:178229$10870_Y - attribute \src "libresoc.v:178230.18-178230.105" - wire $not$libresoc.v:178230$10871_Y - attribute \src "libresoc.v:178231.18-178231.105" - wire $not$libresoc.v:178231$10872_Y - attribute \src "libresoc.v:178232.17-178232.100" - wire $not$libresoc.v:178232$10873_Y - attribute \src "libresoc.v:178233.17-178233.103" - wire $not$libresoc.v:178233$10874_Y - attribute \src "libresoc.v:178234.17-178234.103" - wire $not$libresoc.v:178234$10875_Y + attribute \src "libresoc.v:179108.3-179147.6" + wire width 4 $5\r1__data_o$next[3:0]$10845 + attribute \src "libresoc.v:179178.3-179217.6" + wire width 4 $5\r21__data_o$next[3:0]$10859 + attribute \src "libresoc.v:178871.3-178910.6" + wire width 4 $5\src11__data_o$next[3:0]$10802 + attribute \src "libresoc.v:178968.3-179007.6" + wire width 4 $5\src21__data_o$next[3:0]$10817 + attribute \src "libresoc.v:179038.3-179077.6" + wire width 4 $5\src31__data_o$next[3:0]$10831 + attribute \src "libresoc.v:179108.3-179147.6" + wire width 4 $6\r1__data_o$next[3:0]$10846 + attribute \src "libresoc.v:179178.3-179217.6" + wire width 4 $6\r21__data_o$next[3:0]$10860 + attribute \src "libresoc.v:178871.3-178910.6" + wire width 4 $6\src11__data_o$next[3:0]$10803 + attribute \src "libresoc.v:178968.3-179007.6" + wire width 4 $6\src21__data_o$next[3:0]$10818 + attribute \src "libresoc.v:179038.3-179077.6" + wire width 4 $6\src31__data_o$next[3:0]$10832 + attribute \src "libresoc.v:178854.17-178854.104" + wire $not$libresoc.v:178854$10785_Y + attribute \src "libresoc.v:178855.18-178855.105" + wire $not$libresoc.v:178855$10786_Y + attribute \src "libresoc.v:178856.17-178856.100" + wire $not$libresoc.v:178856$10787_Y + attribute \src "libresoc.v:178857.17-178857.103" + wire $not$libresoc.v:178857$10788_Y + attribute \src "libresoc.v:178858.17-178858.103" + wire $not$libresoc.v:178858$10789_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" - wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \cr_pred1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \cr_pred1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \cr_pred1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest11__data_i + wire width 4 input 9 \dest11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest11__wen + wire input 8 \dest11__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 13 \dest21__data_i + wire width 4 input 11 \dest21__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 12 \dest21__wen - attribute \src "libresoc.v:178142.7-178142.15" + wire input 10 \dest21__wen + attribute \src "libresoc.v:178778.7-178778.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r1__data_o + wire width 4 output 12 \r1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r1__ren + wire input 13 \r1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 16 \r21__data_o + wire width 4 output 14 \r21__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r21__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \r21__ren + wire input 15 \r21__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src11__data_o + wire width 4 output 3 \src11__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src11__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src11__ren + wire input 2 \src11__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src21__data_o + wire width 4 output 5 \src21__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src21__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src21__ren + wire input 4 \src21__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 9 \src31__data_o + wire width 4 output 7 \src31__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src31__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \src31__ren + wire input 6 \src31__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 18 \w1__data_i + wire width 4 input 16 \w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 19 \w1__wen + wire input 17 \w1__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -366145,433 +332410,283 @@ module \reg_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178229$10870 + cell $not $not$libresoc.v:178854$10785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:178229$10870_Y + connect \Y $not$libresoc.v:178854$10785_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178230$10871 + cell $not $not$libresoc.v:178855$10786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:178230$10871_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178231$10872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$16 - connect \Y $not$libresoc.v:178231$10872_Y + connect \Y $not$libresoc.v:178855$10786_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178232$10873 + cell $not $not$libresoc.v:178856$10787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:178232$10873_Y + connect \Y $not$libresoc.v:178856$10787_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178233$10874 + cell $not $not$libresoc.v:178857$10788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:178233$10874_Y + connect \Y $not$libresoc.v:178857$10788_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178234$10875 + cell $not $not$libresoc.v:178858$10789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:178234$10875_Y + connect \Y $not$libresoc.v:178858$10789_Y end - attribute \src "libresoc.v:178142.7-178142.20" - process $proc$libresoc.v:178142$10968 + attribute \src "libresoc.v:178778.7-178778.20" + process $proc$libresoc.v:178778$10867 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178161.13-178161.36" - process $proc$libresoc.v:178161$10969 - assign { } { } - assign $1\cr_pred1__data_o[3:0] 4'0000 - sync always - sync init - update \cr_pred1__data_o $1\cr_pred1__data_o[3:0] - end - attribute \src "libresoc.v:178176.13-178176.30" - process $proc$libresoc.v:178176$10970 + attribute \src "libresoc.v:178803.13-178803.30" + process $proc$libresoc.v:178803$10868 assign { } { } assign $1\r1__data_o[3:0] 4'0000 sync always sync init update \r1__data_o $1\r1__data_o[3:0] end - attribute \src "libresoc.v:178183.13-178183.31" - process $proc$libresoc.v:178183$10971 + attribute \src "libresoc.v:178810.13-178810.31" + process $proc$libresoc.v:178810$10869 assign { } { } assign $1\r21__data_o[3:0] 4'0000 sync always sync init update \r21__data_o $1\r21__data_o[3:0] end - attribute \src "libresoc.v:178189.13-178189.25" - process $proc$libresoc.v:178189$10972 + attribute \src "libresoc.v:178816.13-178816.25" + process $proc$libresoc.v:178816$10870 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:178194.13-178194.33" - process $proc$libresoc.v:178194$10973 + attribute \src "libresoc.v:178821.13-178821.33" + process $proc$libresoc.v:178821$10871 assign { } { } assign $1\src11__data_o[3:0] 4'0000 sync always sync init update \src11__data_o $1\src11__data_o[3:0] end - attribute \src "libresoc.v:178201.13-178201.33" - process $proc$libresoc.v:178201$10974 + attribute \src "libresoc.v:178828.13-178828.33" + process $proc$libresoc.v:178828$10872 assign { } { } assign $1\src21__data_o[3:0] 4'0000 sync always sync init update \src21__data_o $1\src21__data_o[3:0] end - attribute \src "libresoc.v:178208.13-178208.33" - process $proc$libresoc.v:178208$10975 + attribute \src "libresoc.v:178835.13-178835.33" + process $proc$libresoc.v:178835$10873 assign { } { } assign $1\src31__data_o[3:0] 4'0000 sync always sync init update \src31__data_o $1\src31__data_o[3:0] end - attribute \src "libresoc.v:178235.3-178236.25" - process $proc$libresoc.v:178235$10876 + attribute \src "libresoc.v:178859.3-178860.25" + process $proc$libresoc.v:178859$10790 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:178237.3-178238.39" - process $proc$libresoc.v:178237$10877 + attribute \src "libresoc.v:178861.3-178862.39" + process $proc$libresoc.v:178861$10791 assign { } { } assign $0\r21__data_o[3:0] \r21__data_o$next sync posedge \coresync_clk update \r21__data_o $0\r21__data_o[3:0] end - attribute \src "libresoc.v:178239.3-178240.37" - process $proc$libresoc.v:178239$10878 + attribute \src "libresoc.v:178863.3-178864.37" + process $proc$libresoc.v:178863$10792 assign { } { } assign $0\r1__data_o[3:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[3:0] end - attribute \src "libresoc.v:178241.3-178242.43" - process $proc$libresoc.v:178241$10879 + attribute \src "libresoc.v:178865.3-178866.43" + process $proc$libresoc.v:178865$10793 assign { } { } assign $0\src31__data_o[3:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[3:0] end - attribute \src "libresoc.v:178243.3-178244.43" - process $proc$libresoc.v:178243$10880 + attribute \src "libresoc.v:178867.3-178868.43" + process $proc$libresoc.v:178867$10794 assign { } { } assign $0\src21__data_o[3:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[3:0] end - attribute \src "libresoc.v:178245.3-178246.43" - process $proc$libresoc.v:178245$10881 + attribute \src "libresoc.v:178869.3-178870.43" + process $proc$libresoc.v:178869$10795 assign { } { } assign $0\src11__data_o[3:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[3:0] end - attribute \src "libresoc.v:178247.3-178248.49" - process $proc$libresoc.v:178247$10882 + attribute \src "libresoc.v:178871.3-178910.6" + process $proc$libresoc.v:178871$10796 assign { } { } - assign $0\cr_pred1__data_o[3:0] \cr_pred1__data_o$next - sync posedge \coresync_clk - update \cr_pred1__data_o $0\cr_pred1__data_o[3:0] - end - attribute \src "libresoc.v:178249.3-178288.6" - process $proc$libresoc.v:178249$10883 assign { } { } assign { } { } - assign { } { } - assign $0\cr_pred1__data_o$next[3:0]$10884 $6\cr_pred1__data_o$next[3:0]$10890 - attribute \src "libresoc.v:178250.5-178250.29" + assign $0\src11__data_o$next[3:0]$10797 $6\src11__data_o$next[3:0]$10803 + attribute \src "libresoc.v:178872.5-178872.29" switch \initial - attribute \src "libresoc.v:178250.9-178250.17" + attribute \src "libresoc.v:178872.9-178872.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred1__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\cr_pred1__data_o$next[3:0]$10885 $5\cr_pred1__data_o$next[3:0]$10889 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_pred1__data_o$next[3:0]$10886 \dest11__data_i - case - assign $2\cr_pred1__data_o$next[3:0]$10886 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_pred1__data_o$next[3:0]$10887 \dest21__data_i - case - assign $3\cr_pred1__data_o$next[3:0]$10887 $2\cr_pred1__data_o$next[3:0]$10886 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_pred1__data_o$next[3:0]$10888 \w1__data_i - case - assign $4\cr_pred1__data_o$next[3:0]$10888 $3\cr_pred1__data_o$next[3:0]$10887 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\cr_pred1__data_o$next[3:0]$10889 \reg - case - assign $5\cr_pred1__data_o$next[3:0]$10889 $4\cr_pred1__data_o$next[3:0]$10888 - end - case - assign $1\cr_pred1__data_o$next[3:0]$10885 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\cr_pred1__data_o$next[3:0]$10890 4'0000 - case - assign $6\cr_pred1__data_o$next[3:0]$10890 $1\cr_pred1__data_o$next[3:0]$10885 - end - sync always - update \cr_pred1__data_o$next $0\cr_pred1__data_o$next[3:0]$10884 - end - attribute \src "libresoc.v:178289.3-178318.6" - process $proc$libresoc.v:178289$10891 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:178290.5-178290.29" - switch \initial - attribute \src "libresoc.v:178290.9-178290.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred1__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "libresoc.v:178319.3-178358.6" - process $proc$libresoc.v:178319$10892 - assign { } { } - assign { } { } - assign { } { } - assign $0\r21__data_o$next[3:0]$10893 $6\r21__data_o$next[3:0]$10899 - attribute \src "libresoc.v:178320.5-178320.29" - switch \initial - attribute \src "libresoc.v:178320.9-178320.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r21__ren + switch \src11__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r21__data_o$next[3:0]$10894 $5\r21__data_o$next[3:0]$10898 + assign $1\src11__data_o$next[3:0]$10798 $5\src11__data_o$next[3:0]$10802 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r21__data_o$next[3:0]$10895 \dest11__data_i + assign $2\src11__data_o$next[3:0]$10799 \dest11__data_i case - assign $2\r21__data_o$next[3:0]$10895 4'0000 + assign $2\src11__data_o$next[3:0]$10799 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r21__data_o$next[3:0]$10896 \dest21__data_i + assign $3\src11__data_o$next[3:0]$10800 \dest21__data_i case - assign $3\r21__data_o$next[3:0]$10896 $2\r21__data_o$next[3:0]$10895 + assign $3\src11__data_o$next[3:0]$10800 $2\src11__data_o$next[3:0]$10799 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r21__data_o$next[3:0]$10897 \w1__data_i + assign $4\src11__data_o$next[3:0]$10801 \w1__data_i case - assign $4\r21__data_o$next[3:0]$10897 $3\r21__data_o$next[3:0]$10896 + assign $4\src11__data_o$next[3:0]$10801 $3\src11__data_o$next[3:0]$10800 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$15 + switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r21__data_o$next[3:0]$10898 \reg + assign $5\src11__data_o$next[3:0]$10802 \reg case - assign $5\r21__data_o$next[3:0]$10898 $4\r21__data_o$next[3:0]$10897 + assign $5\src11__data_o$next[3:0]$10802 $4\src11__data_o$next[3:0]$10801 end case - assign $1\r21__data_o$next[3:0]$10894 4'0000 + assign $1\src11__data_o$next[3:0]$10798 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r21__data_o$next[3:0]$10899 4'0000 + assign $6\src11__data_o$next[3:0]$10803 4'0000 case - assign $6\r21__data_o$next[3:0]$10899 $1\r21__data_o$next[3:0]$10894 + assign $6\src11__data_o$next[3:0]$10803 $1\src11__data_o$next[3:0]$10798 end sync always - update \r21__data_o$next $0\r21__data_o$next[3:0]$10893 + update \src11__data_o$next $0\src11__data_o$next[3:0]$10797 end - attribute \src "libresoc.v:178359.3-178388.6" - process $proc$libresoc.v:178359$10900 + attribute \src "libresoc.v:178911.3-178940.6" + process $proc$libresoc.v:178911$10804 assign { } { } assign { } { } - assign $0\wr_detect$16[0:0]$10901 $1\wr_detect$16[0:0]$10902 - attribute \src "libresoc.v:178360.5-178360.29" + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:178912.5-178912.29" switch \initial - attribute \src "libresoc.v:178360.9-178360.17" + attribute \src "libresoc.v:178912.9-178912.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r21__ren + switch \src11__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$16[0:0]$10902 $4\wr_detect$16[0:0]$10905 + assign $1\wr_detect[0:0] $4\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$16[0:0]$10903 1'1 + assign $2\wr_detect[0:0] 1'1 case - assign $2\wr_detect$16[0:0]$10903 1'0 + assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$16[0:0]$10904 1'1 + assign $3\wr_detect[0:0] 1'1 case - assign $3\wr_detect$16[0:0]$10904 $2\wr_detect$16[0:0]$10903 + assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$16[0:0]$10905 1'1 + assign $4\wr_detect[0:0] 1'1 case - assign $4\wr_detect$16[0:0]$10905 $3\wr_detect$16[0:0]$10904 + assign $4\wr_detect[0:0] $3\wr_detect[0:0] end case - assign $1\wr_detect$16[0:0]$10902 1'0 + assign $1\wr_detect[0:0] 1'0 end sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$10901 + update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:178389.3-178415.6" - process $proc$libresoc.v:178389$10906 + attribute \src "libresoc.v:178941.3-178967.6" + process $proc$libresoc.v:178941$10805 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10907 $4\reg$next[3:0]$10911 - attribute \src "libresoc.v:178390.5-178390.29" + assign $0\reg$next[3:0]$10806 $4\reg$next[3:0]$10810 + attribute \src "libresoc.v:178942.5-178942.29" switch \initial - attribute \src "libresoc.v:178390.9-178390.17" + attribute \src "libresoc.v:178942.9-178942.17" case 1'1 case end @@ -366580,706 +332695,705 @@ module \reg_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10908 \dest11__data_i + assign $1\reg$next[3:0]$10807 \dest11__data_i case - assign $1\reg$next[3:0]$10908 \reg + assign $1\reg$next[3:0]$10807 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10909 \dest21__data_i + assign $2\reg$next[3:0]$10808 \dest21__data_i case - assign $2\reg$next[3:0]$10909 $1\reg$next[3:0]$10908 + assign $2\reg$next[3:0]$10808 $1\reg$next[3:0]$10807 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10910 \w1__data_i + assign $3\reg$next[3:0]$10809 \w1__data_i case - assign $3\reg$next[3:0]$10910 $2\reg$next[3:0]$10909 + assign $3\reg$next[3:0]$10809 $2\reg$next[3:0]$10808 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10911 4'0000 + assign $4\reg$next[3:0]$10810 4'0000 case - assign $4\reg$next[3:0]$10911 $3\reg$next[3:0]$10910 + assign $4\reg$next[3:0]$10810 $3\reg$next[3:0]$10809 end sync always - update \reg$next $0\reg$next[3:0]$10907 + update \reg$next $0\reg$next[3:0]$10806 end - attribute \src "libresoc.v:178416.3-178455.6" - process $proc$libresoc.v:178416$10912 + attribute \src "libresoc.v:178968.3-179007.6" + process $proc$libresoc.v:178968$10811 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[3:0]$10913 $6\src11__data_o$next[3:0]$10919 - attribute \src "libresoc.v:178417.5-178417.29" + assign $0\src21__data_o$next[3:0]$10812 $6\src21__data_o$next[3:0]$10818 + attribute \src "libresoc.v:178969.5-178969.29" switch \initial - attribute \src "libresoc.v:178417.9-178417.17" + attribute \src "libresoc.v:178969.9-178969.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src11__ren + switch \src21__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[3:0]$10914 $5\src11__data_o$next[3:0]$10918 + assign $1\src21__data_o$next[3:0]$10813 $5\src21__data_o$next[3:0]$10817 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[3:0]$10915 \dest11__data_i + assign $2\src21__data_o$next[3:0]$10814 \dest11__data_i case - assign $2\src11__data_o$next[3:0]$10915 4'0000 + assign $2\src21__data_o$next[3:0]$10814 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[3:0]$10916 \dest21__data_i + assign $3\src21__data_o$next[3:0]$10815 \dest21__data_i case - assign $3\src11__data_o$next[3:0]$10916 $2\src11__data_o$next[3:0]$10915 + assign $3\src21__data_o$next[3:0]$10815 $2\src21__data_o$next[3:0]$10814 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[3:0]$10917 \w1__data_i + assign $4\src21__data_o$next[3:0]$10816 \w1__data_i case - assign $4\src11__data_o$next[3:0]$10917 $3\src11__data_o$next[3:0]$10916 + assign $4\src21__data_o$next[3:0]$10816 $3\src21__data_o$next[3:0]$10815 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[3:0]$10918 \reg + assign $5\src21__data_o$next[3:0]$10817 \reg case - assign $5\src11__data_o$next[3:0]$10918 $4\src11__data_o$next[3:0]$10917 + assign $5\src21__data_o$next[3:0]$10817 $4\src21__data_o$next[3:0]$10816 end case - assign $1\src11__data_o$next[3:0]$10914 4'0000 + assign $1\src21__data_o$next[3:0]$10813 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[3:0]$10919 4'0000 + assign $6\src21__data_o$next[3:0]$10818 4'0000 case - assign $6\src11__data_o$next[3:0]$10919 $1\src11__data_o$next[3:0]$10914 + assign $6\src21__data_o$next[3:0]$10818 $1\src21__data_o$next[3:0]$10813 end sync always - update \src11__data_o$next $0\src11__data_o$next[3:0]$10913 + update \src21__data_o$next $0\src21__data_o$next[3:0]$10812 end - attribute \src "libresoc.v:178456.3-178485.6" - process $proc$libresoc.v:178456$10920 + attribute \src "libresoc.v:179008.3-179037.6" + process $proc$libresoc.v:179008$10819 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10921 $1\wr_detect$4[0:0]$10922 - attribute \src "libresoc.v:178457.5-178457.29" + assign $0\wr_detect$4[0:0]$10820 $1\wr_detect$4[0:0]$10821 + attribute \src "libresoc.v:179009.5-179009.29" switch \initial - attribute \src "libresoc.v:178457.9-178457.17" + attribute \src "libresoc.v:179009.9-179009.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src11__ren + switch \src21__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10922 $4\wr_detect$4[0:0]$10925 + assign $1\wr_detect$4[0:0]$10821 $4\wr_detect$4[0:0]$10824 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10923 1'1 + assign $2\wr_detect$4[0:0]$10822 1'1 case - assign $2\wr_detect$4[0:0]$10923 1'0 + assign $2\wr_detect$4[0:0]$10822 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10924 1'1 + assign $3\wr_detect$4[0:0]$10823 1'1 case - assign $3\wr_detect$4[0:0]$10924 $2\wr_detect$4[0:0]$10923 + assign $3\wr_detect$4[0:0]$10823 $2\wr_detect$4[0:0]$10822 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10925 1'1 + assign $4\wr_detect$4[0:0]$10824 1'1 case - assign $4\wr_detect$4[0:0]$10925 $3\wr_detect$4[0:0]$10924 + assign $4\wr_detect$4[0:0]$10824 $3\wr_detect$4[0:0]$10823 end case - assign $1\wr_detect$4[0:0]$10922 1'0 + assign $1\wr_detect$4[0:0]$10821 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10921 + update \wr_detect$4 $0\wr_detect$4[0:0]$10820 end - attribute \src "libresoc.v:178486.3-178525.6" - process $proc$libresoc.v:178486$10926 + attribute \src "libresoc.v:179038.3-179077.6" + process $proc$libresoc.v:179038$10825 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[3:0]$10927 $6\src21__data_o$next[3:0]$10933 - attribute \src "libresoc.v:178487.5-178487.29" + assign $0\src31__data_o$next[3:0]$10826 $6\src31__data_o$next[3:0]$10832 + attribute \src "libresoc.v:179039.5-179039.29" switch \initial - attribute \src "libresoc.v:178487.9-178487.17" + attribute \src "libresoc.v:179039.9-179039.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src21__ren + switch \src31__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[3:0]$10928 $5\src21__data_o$next[3:0]$10932 + assign $1\src31__data_o$next[3:0]$10827 $5\src31__data_o$next[3:0]$10831 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[3:0]$10929 \dest11__data_i + assign $2\src31__data_o$next[3:0]$10828 \dest11__data_i case - assign $2\src21__data_o$next[3:0]$10929 4'0000 + assign $2\src31__data_o$next[3:0]$10828 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[3:0]$10930 \dest21__data_i + assign $3\src31__data_o$next[3:0]$10829 \dest21__data_i case - assign $3\src21__data_o$next[3:0]$10930 $2\src21__data_o$next[3:0]$10929 + assign $3\src31__data_o$next[3:0]$10829 $2\src31__data_o$next[3:0]$10828 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[3:0]$10931 \w1__data_i + assign $4\src31__data_o$next[3:0]$10830 \w1__data_i case - assign $4\src21__data_o$next[3:0]$10931 $3\src21__data_o$next[3:0]$10930 + assign $4\src31__data_o$next[3:0]$10830 $3\src31__data_o$next[3:0]$10829 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[3:0]$10932 \reg + assign $5\src31__data_o$next[3:0]$10831 \reg case - assign $5\src21__data_o$next[3:0]$10932 $4\src21__data_o$next[3:0]$10931 + assign $5\src31__data_o$next[3:0]$10831 $4\src31__data_o$next[3:0]$10830 end case - assign $1\src21__data_o$next[3:0]$10928 4'0000 + assign $1\src31__data_o$next[3:0]$10827 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[3:0]$10933 4'0000 + assign $6\src31__data_o$next[3:0]$10832 4'0000 case - assign $6\src21__data_o$next[3:0]$10933 $1\src21__data_o$next[3:0]$10928 + assign $6\src31__data_o$next[3:0]$10832 $1\src31__data_o$next[3:0]$10827 end sync always - update \src21__data_o$next $0\src21__data_o$next[3:0]$10927 + update \src31__data_o$next $0\src31__data_o$next[3:0]$10826 end - attribute \src "libresoc.v:178526.3-178555.6" - process $proc$libresoc.v:178526$10934 + attribute \src "libresoc.v:179078.3-179107.6" + process $proc$libresoc.v:179078$10833 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10935 $1\wr_detect$7[0:0]$10936 - attribute \src "libresoc.v:178527.5-178527.29" + assign $0\wr_detect$7[0:0]$10834 $1\wr_detect$7[0:0]$10835 + attribute \src "libresoc.v:179079.5-179079.29" switch \initial - attribute \src "libresoc.v:178527.9-178527.17" + attribute \src "libresoc.v:179079.9-179079.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src21__ren + switch \src31__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10936 $4\wr_detect$7[0:0]$10939 + assign $1\wr_detect$7[0:0]$10835 $4\wr_detect$7[0:0]$10838 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10937 1'1 + assign $2\wr_detect$7[0:0]$10836 1'1 case - assign $2\wr_detect$7[0:0]$10937 1'0 + assign $2\wr_detect$7[0:0]$10836 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10938 1'1 + assign $3\wr_detect$7[0:0]$10837 1'1 case - assign $3\wr_detect$7[0:0]$10938 $2\wr_detect$7[0:0]$10937 + assign $3\wr_detect$7[0:0]$10837 $2\wr_detect$7[0:0]$10836 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10939 1'1 + assign $4\wr_detect$7[0:0]$10838 1'1 case - assign $4\wr_detect$7[0:0]$10939 $3\wr_detect$7[0:0]$10938 + assign $4\wr_detect$7[0:0]$10838 $3\wr_detect$7[0:0]$10837 end case - assign $1\wr_detect$7[0:0]$10936 1'0 + assign $1\wr_detect$7[0:0]$10835 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10935 + update \wr_detect$7 $0\wr_detect$7[0:0]$10834 end - attribute \src "libresoc.v:178556.3-178595.6" - process $proc$libresoc.v:178556$10940 + attribute \src "libresoc.v:179108.3-179147.6" + process $proc$libresoc.v:179108$10839 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[3:0]$10941 $6\src31__data_o$next[3:0]$10947 - attribute \src "libresoc.v:178557.5-178557.29" + assign $0\r1__data_o$next[3:0]$10840 $6\r1__data_o$next[3:0]$10846 + attribute \src "libresoc.v:179109.5-179109.29" switch \initial - attribute \src "libresoc.v:178557.9-178557.17" + attribute \src "libresoc.v:179109.9-179109.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src31__ren + switch \r1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[3:0]$10942 $5\src31__data_o$next[3:0]$10946 + assign $1\r1__data_o$next[3:0]$10841 $5\r1__data_o$next[3:0]$10845 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[3:0]$10943 \dest11__data_i + assign $2\r1__data_o$next[3:0]$10842 \dest11__data_i case - assign $2\src31__data_o$next[3:0]$10943 4'0000 + assign $2\r1__data_o$next[3:0]$10842 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[3:0]$10944 \dest21__data_i + assign $3\r1__data_o$next[3:0]$10843 \dest21__data_i case - assign $3\src31__data_o$next[3:0]$10944 $2\src31__data_o$next[3:0]$10943 + assign $3\r1__data_o$next[3:0]$10843 $2\r1__data_o$next[3:0]$10842 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[3:0]$10945 \w1__data_i + assign $4\r1__data_o$next[3:0]$10844 \w1__data_i case - assign $4\src31__data_o$next[3:0]$10945 $3\src31__data_o$next[3:0]$10944 + assign $4\r1__data_o$next[3:0]$10844 $3\r1__data_o$next[3:0]$10843 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[3:0]$10946 \reg + assign $5\r1__data_o$next[3:0]$10845 \reg case - assign $5\src31__data_o$next[3:0]$10946 $4\src31__data_o$next[3:0]$10945 + assign $5\r1__data_o$next[3:0]$10845 $4\r1__data_o$next[3:0]$10844 end case - assign $1\src31__data_o$next[3:0]$10942 4'0000 + assign $1\r1__data_o$next[3:0]$10841 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[3:0]$10947 4'0000 + assign $6\r1__data_o$next[3:0]$10846 4'0000 case - assign $6\src31__data_o$next[3:0]$10947 $1\src31__data_o$next[3:0]$10942 + assign $6\r1__data_o$next[3:0]$10846 $1\r1__data_o$next[3:0]$10841 end sync always - update \src31__data_o$next $0\src31__data_o$next[3:0]$10941 + update \r1__data_o$next $0\r1__data_o$next[3:0]$10840 end - attribute \src "libresoc.v:178596.3-178625.6" - process $proc$libresoc.v:178596$10948 + attribute \src "libresoc.v:179148.3-179177.6" + process $proc$libresoc.v:179148$10847 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10949 $1\wr_detect$10[0:0]$10950 - attribute \src "libresoc.v:178597.5-178597.29" + assign $0\wr_detect$10[0:0]$10848 $1\wr_detect$10[0:0]$10849 + attribute \src "libresoc.v:179149.5-179149.29" switch \initial - attribute \src "libresoc.v:178597.9-178597.17" + attribute \src "libresoc.v:179149.9-179149.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src31__ren + switch \r1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10950 $4\wr_detect$10[0:0]$10953 + assign $1\wr_detect$10[0:0]$10849 $4\wr_detect$10[0:0]$10852 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10951 1'1 + assign $2\wr_detect$10[0:0]$10850 1'1 case - assign $2\wr_detect$10[0:0]$10951 1'0 + assign $2\wr_detect$10[0:0]$10850 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10952 1'1 + assign $3\wr_detect$10[0:0]$10851 1'1 case - assign $3\wr_detect$10[0:0]$10952 $2\wr_detect$10[0:0]$10951 + assign $3\wr_detect$10[0:0]$10851 $2\wr_detect$10[0:0]$10850 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10953 1'1 + assign $4\wr_detect$10[0:0]$10852 1'1 case - assign $4\wr_detect$10[0:0]$10953 $3\wr_detect$10[0:0]$10952 + assign $4\wr_detect$10[0:0]$10852 $3\wr_detect$10[0:0]$10851 end case - assign $1\wr_detect$10[0:0]$10950 1'0 + assign $1\wr_detect$10[0:0]$10849 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10949 + update \wr_detect$10 $0\wr_detect$10[0:0]$10848 end - attribute \src "libresoc.v:178626.3-178665.6" - process $proc$libresoc.v:178626$10954 + attribute \src "libresoc.v:179178.3-179217.6" + process $proc$libresoc.v:179178$10853 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[3:0]$10955 $6\r1__data_o$next[3:0]$10961 - attribute \src "libresoc.v:178627.5-178627.29" + assign $0\r21__data_o$next[3:0]$10854 $6\r21__data_o$next[3:0]$10860 + attribute \src "libresoc.v:179179.5-179179.29" switch \initial - attribute \src "libresoc.v:178627.9-178627.17" + attribute \src "libresoc.v:179179.9-179179.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r1__ren + switch \r21__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[3:0]$10956 $5\r1__data_o$next[3:0]$10960 + assign $1\r21__data_o$next[3:0]$10855 $5\r21__data_o$next[3:0]$10859 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[3:0]$10957 \dest11__data_i + assign $2\r21__data_o$next[3:0]$10856 \dest11__data_i case - assign $2\r1__data_o$next[3:0]$10957 4'0000 + assign $2\r21__data_o$next[3:0]$10856 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[3:0]$10958 \dest21__data_i + assign $3\r21__data_o$next[3:0]$10857 \dest21__data_i case - assign $3\r1__data_o$next[3:0]$10958 $2\r1__data_o$next[3:0]$10957 + assign $3\r21__data_o$next[3:0]$10857 $2\r21__data_o$next[3:0]$10856 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[3:0]$10959 \w1__data_i + assign $4\r21__data_o$next[3:0]$10858 \w1__data_i case - assign $4\r1__data_o$next[3:0]$10959 $3\r1__data_o$next[3:0]$10958 + assign $4\r21__data_o$next[3:0]$10858 $3\r21__data_o$next[3:0]$10857 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[3:0]$10960 \reg + assign $5\r21__data_o$next[3:0]$10859 \reg case - assign $5\r1__data_o$next[3:0]$10960 $4\r1__data_o$next[3:0]$10959 + assign $5\r21__data_o$next[3:0]$10859 $4\r21__data_o$next[3:0]$10858 end case - assign $1\r1__data_o$next[3:0]$10956 4'0000 + assign $1\r21__data_o$next[3:0]$10855 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[3:0]$10961 4'0000 + assign $6\r21__data_o$next[3:0]$10860 4'0000 case - assign $6\r1__data_o$next[3:0]$10961 $1\r1__data_o$next[3:0]$10956 + assign $6\r21__data_o$next[3:0]$10860 $1\r21__data_o$next[3:0]$10855 end sync always - update \r1__data_o$next $0\r1__data_o$next[3:0]$10955 + update \r21__data_o$next $0\r21__data_o$next[3:0]$10854 end - attribute \src "libresoc.v:178666.3-178695.6" - process $proc$libresoc.v:178666$10962 + attribute \src "libresoc.v:179218.3-179247.6" + process $proc$libresoc.v:179218$10861 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10963 $1\wr_detect$13[0:0]$10964 - attribute \src "libresoc.v:178667.5-178667.29" + assign $0\wr_detect$13[0:0]$10862 $1\wr_detect$13[0:0]$10863 + attribute \src "libresoc.v:179219.5-179219.29" switch \initial - attribute \src "libresoc.v:178667.9-178667.17" + attribute \src "libresoc.v:179219.9-179219.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r1__ren + switch \r21__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10964 $4\wr_detect$13[0:0]$10967 + assign $1\wr_detect$13[0:0]$10863 $4\wr_detect$13[0:0]$10866 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10965 1'1 + assign $2\wr_detect$13[0:0]$10864 1'1 case - assign $2\wr_detect$13[0:0]$10965 1'0 + assign $2\wr_detect$13[0:0]$10864 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10966 1'1 + assign $3\wr_detect$13[0:0]$10865 1'1 case - assign $3\wr_detect$13[0:0]$10966 $2\wr_detect$13[0:0]$10965 + assign $3\wr_detect$13[0:0]$10865 $2\wr_detect$13[0:0]$10864 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10967 1'1 + assign $4\wr_detect$13[0:0]$10866 1'1 case - assign $4\wr_detect$13[0:0]$10967 $3\wr_detect$13[0:0]$10966 + assign $4\wr_detect$13[0:0]$10866 $3\wr_detect$13[0:0]$10865 end case - assign $1\wr_detect$13[0:0]$10964 1'0 + assign $1\wr_detect$13[0:0]$10863 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10963 + update \wr_detect$13 $0\wr_detect$13[0:0]$10862 end - connect \$9 $not$libresoc.v:178229$10870_Y - connect \$12 $not$libresoc.v:178230$10871_Y - connect \$15 $not$libresoc.v:178231$10872_Y - connect \$1 $not$libresoc.v:178232$10873_Y - connect \$3 $not$libresoc.v:178233$10874_Y - connect \$6 $not$libresoc.v:178234$10875_Y + connect \$9 $not$libresoc.v:178854$10785_Y + connect \$12 $not$libresoc.v:178855$10786_Y + connect \$1 $not$libresoc.v:178856$10787_Y + connect \$3 $not$libresoc.v:178857$10788_Y + connect \$6 $not$libresoc.v:178858$10789_Y end -attribute \src "libresoc.v:178700.1-179145.10" +attribute \src "libresoc.v:179252.1-179697.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" attribute \generator "nMigen" module \reg_1$133 - attribute \src "libresoc.v:178701.7-178701.20" + attribute \src "libresoc.v:179253.7-179253.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179030.3-179075.6" - wire width 2 $0\r1__data_o$next[1:0]$11028 - attribute \src "libresoc.v:178776.3-178777.37" + attribute \src "libresoc.v:179582.3-179627.6" + wire width 2 $0\r1__data_o$next[1:0]$10926 + attribute \src "libresoc.v:179328.3-179329.37" wire width 2 $0\r1__data_o[1:0] - attribute \src "libresoc.v:179112.3-179144.6" - wire width 2 $0\reg$next[1:0]$11044 - attribute \src "libresoc.v:178774.3-178775.25" + attribute \src "libresoc.v:179664.3-179696.6" + wire width 2 $0\reg$next[1:0]$10942 + attribute \src "libresoc.v:179326.3-179327.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:178784.3-178829.6" - wire width 2 $0\src11__data_o$next[1:0]$10986 - attribute \src "libresoc.v:178782.3-178783.43" + attribute \src "libresoc.v:179336.3-179381.6" + wire width 2 $0\src11__data_o$next[1:0]$10884 + attribute \src "libresoc.v:179334.3-179335.43" wire width 2 $0\src11__data_o[1:0] - attribute \src "libresoc.v:178866.3-178911.6" - wire width 2 $0\src21__data_o$next[1:0]$10996 - attribute \src "libresoc.v:178780.3-178781.43" + attribute \src "libresoc.v:179418.3-179463.6" + wire width 2 $0\src21__data_o$next[1:0]$10894 + attribute \src "libresoc.v:179332.3-179333.43" wire width 2 $0\src21__data_o[1:0] - attribute \src "libresoc.v:178948.3-178993.6" - wire width 2 $0\src31__data_o$next[1:0]$11012 - attribute \src "libresoc.v:178778.3-178779.43" + attribute \src "libresoc.v:179500.3-179545.6" + wire width 2 $0\src31__data_o$next[1:0]$10910 + attribute \src "libresoc.v:179330.3-179331.43" wire width 2 $0\src31__data_o[1:0] - attribute \src "libresoc.v:179076.3-179111.6" - wire $0\wr_detect$10[0:0]$11037 - attribute \src "libresoc.v:178912.3-178947.6" - wire $0\wr_detect$4[0:0]$11005 - attribute \src "libresoc.v:178994.3-179029.6" - wire $0\wr_detect$7[0:0]$11021 - attribute \src "libresoc.v:178830.3-178865.6" + attribute \src "libresoc.v:179628.3-179663.6" + wire $0\wr_detect$10[0:0]$10935 + attribute \src "libresoc.v:179464.3-179499.6" + wire $0\wr_detect$4[0:0]$10903 + attribute \src "libresoc.v:179546.3-179581.6" + wire $0\wr_detect$7[0:0]$10919 + attribute \src "libresoc.v:179382.3-179417.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179030.3-179075.6" - wire width 2 $1\r1__data_o$next[1:0]$11029 - attribute \src "libresoc.v:178728.13-178728.30" + attribute \src "libresoc.v:179582.3-179627.6" + wire width 2 $1\r1__data_o$next[1:0]$10927 + attribute \src "libresoc.v:179280.13-179280.30" wire width 2 $1\r1__data_o[1:0] - attribute \src "libresoc.v:179112.3-179144.6" - wire width 2 $1\reg$next[1:0]$11045 - attribute \src "libresoc.v:178734.13-178734.25" + attribute \src "libresoc.v:179664.3-179696.6" + wire width 2 $1\reg$next[1:0]$10943 + attribute \src "libresoc.v:179286.13-179286.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:178784.3-178829.6" - wire width 2 $1\src11__data_o$next[1:0]$10987 - attribute \src "libresoc.v:178739.13-178739.33" + attribute \src "libresoc.v:179336.3-179381.6" + wire width 2 $1\src11__data_o$next[1:0]$10885 + attribute \src "libresoc.v:179291.13-179291.33" wire width 2 $1\src11__data_o[1:0] - attribute \src "libresoc.v:178866.3-178911.6" - wire width 2 $1\src21__data_o$next[1:0]$10997 - attribute \src "libresoc.v:178746.13-178746.33" + attribute \src "libresoc.v:179418.3-179463.6" + wire width 2 $1\src21__data_o$next[1:0]$10895 + attribute \src "libresoc.v:179298.13-179298.33" wire width 2 $1\src21__data_o[1:0] - attribute \src "libresoc.v:178948.3-178993.6" - wire width 2 $1\src31__data_o$next[1:0]$11013 - attribute \src "libresoc.v:178753.13-178753.33" + attribute \src "libresoc.v:179500.3-179545.6" + wire width 2 $1\src31__data_o$next[1:0]$10911 + attribute \src "libresoc.v:179305.13-179305.33" wire width 2 $1\src31__data_o[1:0] - attribute \src "libresoc.v:179076.3-179111.6" - wire $1\wr_detect$10[0:0]$11038 - attribute \src "libresoc.v:178912.3-178947.6" - wire $1\wr_detect$4[0:0]$11006 - attribute \src "libresoc.v:178994.3-179029.6" - wire $1\wr_detect$7[0:0]$11022 - attribute \src "libresoc.v:178830.3-178865.6" + attribute \src "libresoc.v:179628.3-179663.6" + wire $1\wr_detect$10[0:0]$10936 + attribute \src "libresoc.v:179464.3-179499.6" + wire $1\wr_detect$4[0:0]$10904 + attribute \src "libresoc.v:179546.3-179581.6" + wire $1\wr_detect$7[0:0]$10920 + attribute \src "libresoc.v:179382.3-179417.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179030.3-179075.6" - wire width 2 $2\r1__data_o$next[1:0]$11030 - attribute \src "libresoc.v:179112.3-179144.6" - wire width 2 $2\reg$next[1:0]$11046 - attribute \src "libresoc.v:178784.3-178829.6" - wire width 2 $2\src11__data_o$next[1:0]$10988 - attribute \src "libresoc.v:178866.3-178911.6" - wire width 2 $2\src21__data_o$next[1:0]$10998 - attribute \src "libresoc.v:178948.3-178993.6" - wire width 2 $2\src31__data_o$next[1:0]$11014 - attribute \src "libresoc.v:179076.3-179111.6" - wire $2\wr_detect$10[0:0]$11039 - attribute \src "libresoc.v:178912.3-178947.6" - wire $2\wr_detect$4[0:0]$11007 - attribute \src "libresoc.v:178994.3-179029.6" - wire $2\wr_detect$7[0:0]$11023 - attribute \src "libresoc.v:178830.3-178865.6" + attribute \src "libresoc.v:179582.3-179627.6" + wire width 2 $2\r1__data_o$next[1:0]$10928 + attribute \src "libresoc.v:179664.3-179696.6" + wire width 2 $2\reg$next[1:0]$10944 + attribute \src "libresoc.v:179336.3-179381.6" + wire width 2 $2\src11__data_o$next[1:0]$10886 + attribute \src "libresoc.v:179418.3-179463.6" + wire width 2 $2\src21__data_o$next[1:0]$10896 + attribute \src "libresoc.v:179500.3-179545.6" + wire width 2 $2\src31__data_o$next[1:0]$10912 + attribute \src "libresoc.v:179628.3-179663.6" + wire $2\wr_detect$10[0:0]$10937 + attribute \src "libresoc.v:179464.3-179499.6" + wire $2\wr_detect$4[0:0]$10905 + attribute \src "libresoc.v:179546.3-179581.6" + wire $2\wr_detect$7[0:0]$10921 + attribute \src "libresoc.v:179382.3-179417.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179030.3-179075.6" - wire width 2 $3\r1__data_o$next[1:0]$11031 - attribute \src "libresoc.v:179112.3-179144.6" - wire width 2 $3\reg$next[1:0]$11047 - attribute \src "libresoc.v:178784.3-178829.6" - wire width 2 $3\src11__data_o$next[1:0]$10989 - attribute \src "libresoc.v:178866.3-178911.6" - wire width 2 $3\src21__data_o$next[1:0]$10999 - attribute \src "libresoc.v:178948.3-178993.6" - wire width 2 $3\src31__data_o$next[1:0]$11015 - attribute \src "libresoc.v:179076.3-179111.6" - wire $3\wr_detect$10[0:0]$11040 - attribute \src "libresoc.v:178912.3-178947.6" - wire $3\wr_detect$4[0:0]$11008 - attribute \src "libresoc.v:178994.3-179029.6" - wire $3\wr_detect$7[0:0]$11024 - attribute \src "libresoc.v:178830.3-178865.6" + attribute \src "libresoc.v:179582.3-179627.6" + wire width 2 $3\r1__data_o$next[1:0]$10929 + attribute \src "libresoc.v:179664.3-179696.6" + wire width 2 $3\reg$next[1:0]$10945 + attribute \src "libresoc.v:179336.3-179381.6" + wire width 2 $3\src11__data_o$next[1:0]$10887 + attribute \src "libresoc.v:179418.3-179463.6" + wire width 2 $3\src21__data_o$next[1:0]$10897 + attribute \src "libresoc.v:179500.3-179545.6" + wire width 2 $3\src31__data_o$next[1:0]$10913 + attribute \src "libresoc.v:179628.3-179663.6" + wire $3\wr_detect$10[0:0]$10938 + attribute \src "libresoc.v:179464.3-179499.6" + wire $3\wr_detect$4[0:0]$10906 + attribute \src "libresoc.v:179546.3-179581.6" + wire $3\wr_detect$7[0:0]$10922 + attribute \src "libresoc.v:179382.3-179417.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179030.3-179075.6" - wire width 2 $4\r1__data_o$next[1:0]$11032 - attribute \src "libresoc.v:179112.3-179144.6" - wire width 2 $4\reg$next[1:0]$11048 - attribute \src "libresoc.v:178784.3-178829.6" - wire width 2 $4\src11__data_o$next[1:0]$10990 - attribute \src "libresoc.v:178866.3-178911.6" - wire width 2 $4\src21__data_o$next[1:0]$11000 - attribute \src "libresoc.v:178948.3-178993.6" - wire width 2 $4\src31__data_o$next[1:0]$11016 - attribute \src "libresoc.v:179076.3-179111.6" - wire $4\wr_detect$10[0:0]$11041 - attribute \src "libresoc.v:178912.3-178947.6" - wire $4\wr_detect$4[0:0]$11009 - attribute \src "libresoc.v:178994.3-179029.6" - wire $4\wr_detect$7[0:0]$11025 - attribute \src "libresoc.v:178830.3-178865.6" + attribute \src "libresoc.v:179582.3-179627.6" + wire width 2 $4\r1__data_o$next[1:0]$10930 + attribute \src "libresoc.v:179664.3-179696.6" + wire width 2 $4\reg$next[1:0]$10946 + attribute \src "libresoc.v:179336.3-179381.6" + wire width 2 $4\src11__data_o$next[1:0]$10888 + attribute \src "libresoc.v:179418.3-179463.6" + wire width 2 $4\src21__data_o$next[1:0]$10898 + attribute \src "libresoc.v:179500.3-179545.6" + wire width 2 $4\src31__data_o$next[1:0]$10914 + attribute \src "libresoc.v:179628.3-179663.6" + wire $4\wr_detect$10[0:0]$10939 + attribute \src "libresoc.v:179464.3-179499.6" + wire $4\wr_detect$4[0:0]$10907 + attribute \src "libresoc.v:179546.3-179581.6" + wire $4\wr_detect$7[0:0]$10923 + attribute \src "libresoc.v:179382.3-179417.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179030.3-179075.6" - wire width 2 $5\r1__data_o$next[1:0]$11033 - attribute \src "libresoc.v:179112.3-179144.6" - wire width 2 $5\reg$next[1:0]$11049 - attribute \src "libresoc.v:178784.3-178829.6" - wire width 2 $5\src11__data_o$next[1:0]$10991 - attribute \src "libresoc.v:178866.3-178911.6" - wire width 2 $5\src21__data_o$next[1:0]$11001 - attribute \src "libresoc.v:178948.3-178993.6" - wire width 2 $5\src31__data_o$next[1:0]$11017 - attribute \src "libresoc.v:179076.3-179111.6" - wire $5\wr_detect$10[0:0]$11042 - attribute \src "libresoc.v:178912.3-178947.6" - wire $5\wr_detect$4[0:0]$11010 - attribute \src "libresoc.v:178994.3-179029.6" - wire $5\wr_detect$7[0:0]$11026 - attribute \src "libresoc.v:178830.3-178865.6" + attribute \src "libresoc.v:179582.3-179627.6" + wire width 2 $5\r1__data_o$next[1:0]$10931 + attribute \src "libresoc.v:179664.3-179696.6" + wire width 2 $5\reg$next[1:0]$10947 + attribute \src "libresoc.v:179336.3-179381.6" + wire width 2 $5\src11__data_o$next[1:0]$10889 + attribute \src "libresoc.v:179418.3-179463.6" + wire width 2 $5\src21__data_o$next[1:0]$10899 + attribute \src "libresoc.v:179500.3-179545.6" + wire width 2 $5\src31__data_o$next[1:0]$10915 + attribute \src "libresoc.v:179628.3-179663.6" + wire $5\wr_detect$10[0:0]$10940 + attribute \src "libresoc.v:179464.3-179499.6" + wire $5\wr_detect$4[0:0]$10908 + attribute \src "libresoc.v:179546.3-179581.6" + wire $5\wr_detect$7[0:0]$10924 + attribute \src "libresoc.v:179382.3-179417.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:179030.3-179075.6" - wire width 2 $6\r1__data_o$next[1:0]$11034 - attribute \src "libresoc.v:178784.3-178829.6" - wire width 2 $6\src11__data_o$next[1:0]$10992 - attribute \src "libresoc.v:178866.3-178911.6" - wire width 2 $6\src21__data_o$next[1:0]$11002 - attribute \src "libresoc.v:178948.3-178993.6" - wire width 2 $6\src31__data_o$next[1:0]$11018 - attribute \src "libresoc.v:179030.3-179075.6" - wire width 2 $7\r1__data_o$next[1:0]$11035 - attribute \src "libresoc.v:178784.3-178829.6" - wire width 2 $7\src11__data_o$next[1:0]$10993 - attribute \src "libresoc.v:178866.3-178911.6" - wire width 2 $7\src21__data_o$next[1:0]$11003 - attribute \src "libresoc.v:178948.3-178993.6" - wire width 2 $7\src31__data_o$next[1:0]$11019 - attribute \src "libresoc.v:178770.17-178770.104" - wire $not$libresoc.v:178770$10976_Y - attribute \src "libresoc.v:178771.17-178771.100" - wire $not$libresoc.v:178771$10977_Y - attribute \src "libresoc.v:178772.17-178772.103" - wire $not$libresoc.v:178772$10978_Y - attribute \src "libresoc.v:178773.17-178773.103" - wire $not$libresoc.v:178773$10979_Y + attribute \src "libresoc.v:179582.3-179627.6" + wire width 2 $6\r1__data_o$next[1:0]$10932 + attribute \src "libresoc.v:179336.3-179381.6" + wire width 2 $6\src11__data_o$next[1:0]$10890 + attribute \src "libresoc.v:179418.3-179463.6" + wire width 2 $6\src21__data_o$next[1:0]$10900 + attribute \src "libresoc.v:179500.3-179545.6" + wire width 2 $6\src31__data_o$next[1:0]$10916 + attribute \src "libresoc.v:179582.3-179627.6" + wire width 2 $7\r1__data_o$next[1:0]$10933 + attribute \src "libresoc.v:179336.3-179381.6" + wire width 2 $7\src11__data_o$next[1:0]$10891 + attribute \src "libresoc.v:179418.3-179463.6" + wire width 2 $7\src21__data_o$next[1:0]$10901 + attribute \src "libresoc.v:179500.3-179545.6" + wire width 2 $7\src31__data_o$next[1:0]$10917 + attribute \src "libresoc.v:179322.17-179322.104" + wire $not$libresoc.v:179322$10874_Y + attribute \src "libresoc.v:179323.17-179323.100" + wire $not$libresoc.v:179323$10875_Y + attribute \src "libresoc.v:179324.17-179324.103" + wire $not$libresoc.v:179324$10876_Y + attribute \src "libresoc.v:179325.17-179325.103" + wire $not$libresoc.v:179325$10877_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -367288,9 +333402,9 @@ module \reg_1$133 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest11__data_i @@ -367304,7 +333418,7 @@ module \reg_1$133 wire width 2 input 13 \dest31__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest31__wen - attribute \src "libresoc.v:178701.7-178701.15" + attribute \src "libresoc.v:179253.7-179253.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r1__data_o @@ -367347,129 +333461,129 @@ module \reg_1$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178770$10976 + cell $not $not$libresoc.v:179322$10874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:178770$10976_Y + connect \Y $not$libresoc.v:179322$10874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178771$10977 + cell $not $not$libresoc.v:179323$10875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:178771$10977_Y + connect \Y $not$libresoc.v:179323$10875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178772$10978 + cell $not $not$libresoc.v:179324$10876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:178772$10978_Y + connect \Y $not$libresoc.v:179324$10876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178773$10979 + cell $not $not$libresoc.v:179325$10877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:178773$10979_Y + connect \Y $not$libresoc.v:179325$10877_Y end - attribute \src "libresoc.v:178701.7-178701.20" - process $proc$libresoc.v:178701$11050 + attribute \src "libresoc.v:179253.7-179253.20" + process $proc$libresoc.v:179253$10948 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178728.13-178728.30" - process $proc$libresoc.v:178728$11051 + attribute \src "libresoc.v:179280.13-179280.30" + process $proc$libresoc.v:179280$10949 assign { } { } assign $1\r1__data_o[1:0] 2'00 sync always sync init update \r1__data_o $1\r1__data_o[1:0] end - attribute \src "libresoc.v:178734.13-178734.25" - process $proc$libresoc.v:178734$11052 + attribute \src "libresoc.v:179286.13-179286.25" + process $proc$libresoc.v:179286$10950 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:178739.13-178739.33" - process $proc$libresoc.v:178739$11053 + attribute \src "libresoc.v:179291.13-179291.33" + process $proc$libresoc.v:179291$10951 assign { } { } assign $1\src11__data_o[1:0] 2'00 sync always sync init update \src11__data_o $1\src11__data_o[1:0] end - attribute \src "libresoc.v:178746.13-178746.33" - process $proc$libresoc.v:178746$11054 + attribute \src "libresoc.v:179298.13-179298.33" + process $proc$libresoc.v:179298$10952 assign { } { } assign $1\src21__data_o[1:0] 2'00 sync always sync init update \src21__data_o $1\src21__data_o[1:0] end - attribute \src "libresoc.v:178753.13-178753.33" - process $proc$libresoc.v:178753$11055 + attribute \src "libresoc.v:179305.13-179305.33" + process $proc$libresoc.v:179305$10953 assign { } { } assign $1\src31__data_o[1:0] 2'00 sync always sync init update \src31__data_o $1\src31__data_o[1:0] end - attribute \src "libresoc.v:178774.3-178775.25" - process $proc$libresoc.v:178774$10980 + attribute \src "libresoc.v:179326.3-179327.25" + process $proc$libresoc.v:179326$10878 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:178776.3-178777.37" - process $proc$libresoc.v:178776$10981 + attribute \src "libresoc.v:179328.3-179329.37" + process $proc$libresoc.v:179328$10879 assign { } { } assign $0\r1__data_o[1:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[1:0] end - attribute \src "libresoc.v:178778.3-178779.43" - process $proc$libresoc.v:178778$10982 + attribute \src "libresoc.v:179330.3-179331.43" + process $proc$libresoc.v:179330$10880 assign { } { } assign $0\src31__data_o[1:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[1:0] end - attribute \src "libresoc.v:178780.3-178781.43" - process $proc$libresoc.v:178780$10983 + attribute \src "libresoc.v:179332.3-179333.43" + process $proc$libresoc.v:179332$10881 assign { } { } assign $0\src21__data_o[1:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[1:0] end - attribute \src "libresoc.v:178782.3-178783.43" - process $proc$libresoc.v:178782$10984 + attribute \src "libresoc.v:179334.3-179335.43" + process $proc$libresoc.v:179334$10882 assign { } { } assign $0\src11__data_o[1:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[1:0] end - attribute \src "libresoc.v:178784.3-178829.6" - process $proc$libresoc.v:178784$10985 + attribute \src "libresoc.v:179336.3-179381.6" + process $proc$libresoc.v:179336$10883 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[1:0]$10986 $7\src11__data_o$next[1:0]$10993 - attribute \src "libresoc.v:178785.5-178785.29" + assign $0\src11__data_o$next[1:0]$10884 $7\src11__data_o$next[1:0]$10891 + attribute \src "libresoc.v:179337.5-179337.29" switch \initial - attribute \src "libresoc.v:178785.9-178785.17" + attribute \src "libresoc.v:179337.9-179337.17" case 1'1 case end @@ -367482,75 +333596,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[1:0]$10987 $6\src11__data_o$next[1:0]$10992 + assign $1\src11__data_o$next[1:0]$10885 $6\src11__data_o$next[1:0]$10890 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[1:0]$10988 \dest11__data_i + assign $2\src11__data_o$next[1:0]$10886 \dest11__data_i case - assign $2\src11__data_o$next[1:0]$10988 2'00 + assign $2\src11__data_o$next[1:0]$10886 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[1:0]$10989 \dest21__data_i + assign $3\src11__data_o$next[1:0]$10887 \dest21__data_i case - assign $3\src11__data_o$next[1:0]$10989 $2\src11__data_o$next[1:0]$10988 + assign $3\src11__data_o$next[1:0]$10887 $2\src11__data_o$next[1:0]$10886 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[1:0]$10990 \dest31__data_i + assign $4\src11__data_o$next[1:0]$10888 \dest31__data_i case - assign $4\src11__data_o$next[1:0]$10990 $3\src11__data_o$next[1:0]$10989 + assign $4\src11__data_o$next[1:0]$10888 $3\src11__data_o$next[1:0]$10887 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[1:0]$10991 \w1__data_i + assign $5\src11__data_o$next[1:0]$10889 \w1__data_i case - assign $5\src11__data_o$next[1:0]$10991 $4\src11__data_o$next[1:0]$10990 + assign $5\src11__data_o$next[1:0]$10889 $4\src11__data_o$next[1:0]$10888 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[1:0]$10992 \reg + assign $6\src11__data_o$next[1:0]$10890 \reg case - assign $6\src11__data_o$next[1:0]$10992 $5\src11__data_o$next[1:0]$10991 + assign $6\src11__data_o$next[1:0]$10890 $5\src11__data_o$next[1:0]$10889 end case - assign $1\src11__data_o$next[1:0]$10987 2'00 + assign $1\src11__data_o$next[1:0]$10885 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src11__data_o$next[1:0]$10993 2'00 + assign $7\src11__data_o$next[1:0]$10891 2'00 case - assign $7\src11__data_o$next[1:0]$10993 $1\src11__data_o$next[1:0]$10987 + assign $7\src11__data_o$next[1:0]$10891 $1\src11__data_o$next[1:0]$10885 end sync always - update \src11__data_o$next $0\src11__data_o$next[1:0]$10986 + update \src11__data_o$next $0\src11__data_o$next[1:0]$10884 end - attribute \src "libresoc.v:178830.3-178865.6" - process $proc$libresoc.v:178830$10994 + attribute \src "libresoc.v:179382.3-179417.6" + process $proc$libresoc.v:179382$10892 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:178831.5-178831.29" + attribute \src "libresoc.v:179383.5-179383.29" switch \initial - attribute \src "libresoc.v:178831.9-178831.17" + attribute \src "libresoc.v:179383.9-179383.17" case 1'1 case end @@ -367606,15 +333720,15 @@ module \reg_1$133 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:178866.3-178911.6" - process $proc$libresoc.v:178866$10995 + attribute \src "libresoc.v:179418.3-179463.6" + process $proc$libresoc.v:179418$10893 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[1:0]$10996 $7\src21__data_o$next[1:0]$11003 - attribute \src "libresoc.v:178867.5-178867.29" + assign $0\src21__data_o$next[1:0]$10894 $7\src21__data_o$next[1:0]$10901 + attribute \src "libresoc.v:179419.5-179419.29" switch \initial - attribute \src "libresoc.v:178867.9-178867.17" + attribute \src "libresoc.v:179419.9-179419.17" case 1'1 case end @@ -367627,75 +333741,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[1:0]$10997 $6\src21__data_o$next[1:0]$11002 + assign $1\src21__data_o$next[1:0]$10895 $6\src21__data_o$next[1:0]$10900 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[1:0]$10998 \dest11__data_i + assign $2\src21__data_o$next[1:0]$10896 \dest11__data_i case - assign $2\src21__data_o$next[1:0]$10998 2'00 + assign $2\src21__data_o$next[1:0]$10896 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[1:0]$10999 \dest21__data_i + assign $3\src21__data_o$next[1:0]$10897 \dest21__data_i case - assign $3\src21__data_o$next[1:0]$10999 $2\src21__data_o$next[1:0]$10998 + assign $3\src21__data_o$next[1:0]$10897 $2\src21__data_o$next[1:0]$10896 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[1:0]$11000 \dest31__data_i + assign $4\src21__data_o$next[1:0]$10898 \dest31__data_i case - assign $4\src21__data_o$next[1:0]$11000 $3\src21__data_o$next[1:0]$10999 + assign $4\src21__data_o$next[1:0]$10898 $3\src21__data_o$next[1:0]$10897 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[1:0]$11001 \w1__data_i + assign $5\src21__data_o$next[1:0]$10899 \w1__data_i case - assign $5\src21__data_o$next[1:0]$11001 $4\src21__data_o$next[1:0]$11000 + assign $5\src21__data_o$next[1:0]$10899 $4\src21__data_o$next[1:0]$10898 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[1:0]$11002 \reg + assign $6\src21__data_o$next[1:0]$10900 \reg case - assign $6\src21__data_o$next[1:0]$11002 $5\src21__data_o$next[1:0]$11001 + assign $6\src21__data_o$next[1:0]$10900 $5\src21__data_o$next[1:0]$10899 end case - assign $1\src21__data_o$next[1:0]$10997 2'00 + assign $1\src21__data_o$next[1:0]$10895 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src21__data_o$next[1:0]$11003 2'00 + assign $7\src21__data_o$next[1:0]$10901 2'00 case - assign $7\src21__data_o$next[1:0]$11003 $1\src21__data_o$next[1:0]$10997 + assign $7\src21__data_o$next[1:0]$10901 $1\src21__data_o$next[1:0]$10895 end sync always - update \src21__data_o$next $0\src21__data_o$next[1:0]$10996 + update \src21__data_o$next $0\src21__data_o$next[1:0]$10894 end - attribute \src "libresoc.v:178912.3-178947.6" - process $proc$libresoc.v:178912$11004 + attribute \src "libresoc.v:179464.3-179499.6" + process $proc$libresoc.v:179464$10902 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11005 $1\wr_detect$4[0:0]$11006 - attribute \src "libresoc.v:178913.5-178913.29" + assign $0\wr_detect$4[0:0]$10903 $1\wr_detect$4[0:0]$10904 + attribute \src "libresoc.v:179465.5-179465.29" switch \initial - attribute \src "libresoc.v:178913.9-178913.17" + attribute \src "libresoc.v:179465.9-179465.17" case 1'1 case end @@ -367708,58 +333822,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11006 $5\wr_detect$4[0:0]$11010 + assign $1\wr_detect$4[0:0]$10904 $5\wr_detect$4[0:0]$10908 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11007 1'1 + assign $2\wr_detect$4[0:0]$10905 1'1 case - assign $2\wr_detect$4[0:0]$11007 1'0 + assign $2\wr_detect$4[0:0]$10905 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11008 1'1 + assign $3\wr_detect$4[0:0]$10906 1'1 case - assign $3\wr_detect$4[0:0]$11008 $2\wr_detect$4[0:0]$11007 + assign $3\wr_detect$4[0:0]$10906 $2\wr_detect$4[0:0]$10905 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11009 1'1 + assign $4\wr_detect$4[0:0]$10907 1'1 case - assign $4\wr_detect$4[0:0]$11009 $3\wr_detect$4[0:0]$11008 + assign $4\wr_detect$4[0:0]$10907 $3\wr_detect$4[0:0]$10906 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11010 1'1 + assign $5\wr_detect$4[0:0]$10908 1'1 case - assign $5\wr_detect$4[0:0]$11010 $4\wr_detect$4[0:0]$11009 + assign $5\wr_detect$4[0:0]$10908 $4\wr_detect$4[0:0]$10907 end case - assign $1\wr_detect$4[0:0]$11006 1'0 + assign $1\wr_detect$4[0:0]$10904 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11005 + update \wr_detect$4 $0\wr_detect$4[0:0]$10903 end - attribute \src "libresoc.v:178948.3-178993.6" - process $proc$libresoc.v:178948$11011 + attribute \src "libresoc.v:179500.3-179545.6" + process $proc$libresoc.v:179500$10909 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[1:0]$11012 $7\src31__data_o$next[1:0]$11019 - attribute \src "libresoc.v:178949.5-178949.29" + assign $0\src31__data_o$next[1:0]$10910 $7\src31__data_o$next[1:0]$10917 + attribute \src "libresoc.v:179501.5-179501.29" switch \initial - attribute \src "libresoc.v:178949.9-178949.17" + attribute \src "libresoc.v:179501.9-179501.17" case 1'1 case end @@ -367772,75 +333886,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[1:0]$11013 $6\src31__data_o$next[1:0]$11018 + assign $1\src31__data_o$next[1:0]$10911 $6\src31__data_o$next[1:0]$10916 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[1:0]$11014 \dest11__data_i + assign $2\src31__data_o$next[1:0]$10912 \dest11__data_i case - assign $2\src31__data_o$next[1:0]$11014 2'00 + assign $2\src31__data_o$next[1:0]$10912 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[1:0]$11015 \dest21__data_i + assign $3\src31__data_o$next[1:0]$10913 \dest21__data_i case - assign $3\src31__data_o$next[1:0]$11015 $2\src31__data_o$next[1:0]$11014 + assign $3\src31__data_o$next[1:0]$10913 $2\src31__data_o$next[1:0]$10912 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[1:0]$11016 \dest31__data_i + assign $4\src31__data_o$next[1:0]$10914 \dest31__data_i case - assign $4\src31__data_o$next[1:0]$11016 $3\src31__data_o$next[1:0]$11015 + assign $4\src31__data_o$next[1:0]$10914 $3\src31__data_o$next[1:0]$10913 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[1:0]$11017 \w1__data_i + assign $5\src31__data_o$next[1:0]$10915 \w1__data_i case - assign $5\src31__data_o$next[1:0]$11017 $4\src31__data_o$next[1:0]$11016 + assign $5\src31__data_o$next[1:0]$10915 $4\src31__data_o$next[1:0]$10914 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[1:0]$11018 \reg + assign $6\src31__data_o$next[1:0]$10916 \reg case - assign $6\src31__data_o$next[1:0]$11018 $5\src31__data_o$next[1:0]$11017 + assign $6\src31__data_o$next[1:0]$10916 $5\src31__data_o$next[1:0]$10915 end case - assign $1\src31__data_o$next[1:0]$11013 2'00 + assign $1\src31__data_o$next[1:0]$10911 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src31__data_o$next[1:0]$11019 2'00 + assign $7\src31__data_o$next[1:0]$10917 2'00 case - assign $7\src31__data_o$next[1:0]$11019 $1\src31__data_o$next[1:0]$11013 + assign $7\src31__data_o$next[1:0]$10917 $1\src31__data_o$next[1:0]$10911 end sync always - update \src31__data_o$next $0\src31__data_o$next[1:0]$11012 + update \src31__data_o$next $0\src31__data_o$next[1:0]$10910 end - attribute \src "libresoc.v:178994.3-179029.6" - process $proc$libresoc.v:178994$11020 + attribute \src "libresoc.v:179546.3-179581.6" + process $proc$libresoc.v:179546$10918 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11021 $1\wr_detect$7[0:0]$11022 - attribute \src "libresoc.v:178995.5-178995.29" + assign $0\wr_detect$7[0:0]$10919 $1\wr_detect$7[0:0]$10920 + attribute \src "libresoc.v:179547.5-179547.29" switch \initial - attribute \src "libresoc.v:178995.9-178995.17" + attribute \src "libresoc.v:179547.9-179547.17" case 1'1 case end @@ -367853,58 +333967,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11022 $5\wr_detect$7[0:0]$11026 + assign $1\wr_detect$7[0:0]$10920 $5\wr_detect$7[0:0]$10924 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11023 1'1 + assign $2\wr_detect$7[0:0]$10921 1'1 case - assign $2\wr_detect$7[0:0]$11023 1'0 + assign $2\wr_detect$7[0:0]$10921 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11024 1'1 + assign $3\wr_detect$7[0:0]$10922 1'1 case - assign $3\wr_detect$7[0:0]$11024 $2\wr_detect$7[0:0]$11023 + assign $3\wr_detect$7[0:0]$10922 $2\wr_detect$7[0:0]$10921 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11025 1'1 + assign $4\wr_detect$7[0:0]$10923 1'1 case - assign $4\wr_detect$7[0:0]$11025 $3\wr_detect$7[0:0]$11024 + assign $4\wr_detect$7[0:0]$10923 $3\wr_detect$7[0:0]$10922 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11026 1'1 + assign $5\wr_detect$7[0:0]$10924 1'1 case - assign $5\wr_detect$7[0:0]$11026 $4\wr_detect$7[0:0]$11025 + assign $5\wr_detect$7[0:0]$10924 $4\wr_detect$7[0:0]$10923 end case - assign $1\wr_detect$7[0:0]$11022 1'0 + assign $1\wr_detect$7[0:0]$10920 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11021 + update \wr_detect$7 $0\wr_detect$7[0:0]$10919 end - attribute \src "libresoc.v:179030.3-179075.6" - process $proc$libresoc.v:179030$11027 + attribute \src "libresoc.v:179582.3-179627.6" + process $proc$libresoc.v:179582$10925 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[1:0]$11028 $7\r1__data_o$next[1:0]$11035 - attribute \src "libresoc.v:179031.5-179031.29" + assign $0\r1__data_o$next[1:0]$10926 $7\r1__data_o$next[1:0]$10933 + attribute \src "libresoc.v:179583.5-179583.29" switch \initial - attribute \src "libresoc.v:179031.9-179031.17" + attribute \src "libresoc.v:179583.9-179583.17" case 1'1 case end @@ -367917,75 +334031,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[1:0]$11029 $6\r1__data_o$next[1:0]$11034 + assign $1\r1__data_o$next[1:0]$10927 $6\r1__data_o$next[1:0]$10932 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[1:0]$11030 \dest11__data_i + assign $2\r1__data_o$next[1:0]$10928 \dest11__data_i case - assign $2\r1__data_o$next[1:0]$11030 2'00 + assign $2\r1__data_o$next[1:0]$10928 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[1:0]$11031 \dest21__data_i + assign $3\r1__data_o$next[1:0]$10929 \dest21__data_i case - assign $3\r1__data_o$next[1:0]$11031 $2\r1__data_o$next[1:0]$11030 + assign $3\r1__data_o$next[1:0]$10929 $2\r1__data_o$next[1:0]$10928 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[1:0]$11032 \dest31__data_i + assign $4\r1__data_o$next[1:0]$10930 \dest31__data_i case - assign $4\r1__data_o$next[1:0]$11032 $3\r1__data_o$next[1:0]$11031 + assign $4\r1__data_o$next[1:0]$10930 $3\r1__data_o$next[1:0]$10929 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[1:0]$11033 \w1__data_i + assign $5\r1__data_o$next[1:0]$10931 \w1__data_i case - assign $5\r1__data_o$next[1:0]$11033 $4\r1__data_o$next[1:0]$11032 + assign $5\r1__data_o$next[1:0]$10931 $4\r1__data_o$next[1:0]$10930 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[1:0]$11034 \reg + assign $6\r1__data_o$next[1:0]$10932 \reg case - assign $6\r1__data_o$next[1:0]$11034 $5\r1__data_o$next[1:0]$11033 + assign $6\r1__data_o$next[1:0]$10932 $5\r1__data_o$next[1:0]$10931 end case - assign $1\r1__data_o$next[1:0]$11029 2'00 + assign $1\r1__data_o$next[1:0]$10927 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r1__data_o$next[1:0]$11035 2'00 + assign $7\r1__data_o$next[1:0]$10933 2'00 case - assign $7\r1__data_o$next[1:0]$11035 $1\r1__data_o$next[1:0]$11029 + assign $7\r1__data_o$next[1:0]$10933 $1\r1__data_o$next[1:0]$10927 end sync always - update \r1__data_o$next $0\r1__data_o$next[1:0]$11028 + update \r1__data_o$next $0\r1__data_o$next[1:0]$10926 end - attribute \src "libresoc.v:179076.3-179111.6" - process $proc$libresoc.v:179076$11036 + attribute \src "libresoc.v:179628.3-179663.6" + process $proc$libresoc.v:179628$10934 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11037 $1\wr_detect$10[0:0]$11038 - attribute \src "libresoc.v:179077.5-179077.29" + assign $0\wr_detect$10[0:0]$10935 $1\wr_detect$10[0:0]$10936 + attribute \src "libresoc.v:179629.5-179629.29" switch \initial - attribute \src "libresoc.v:179077.9-179077.17" + attribute \src "libresoc.v:179629.9-179629.17" case 1'1 case end @@ -367998,61 +334112,61 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11038 $5\wr_detect$10[0:0]$11042 + assign $1\wr_detect$10[0:0]$10936 $5\wr_detect$10[0:0]$10940 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11039 1'1 + assign $2\wr_detect$10[0:0]$10937 1'1 case - assign $2\wr_detect$10[0:0]$11039 1'0 + assign $2\wr_detect$10[0:0]$10937 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11040 1'1 + assign $3\wr_detect$10[0:0]$10938 1'1 case - assign $3\wr_detect$10[0:0]$11040 $2\wr_detect$10[0:0]$11039 + assign $3\wr_detect$10[0:0]$10938 $2\wr_detect$10[0:0]$10937 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11041 1'1 + assign $4\wr_detect$10[0:0]$10939 1'1 case - assign $4\wr_detect$10[0:0]$11041 $3\wr_detect$10[0:0]$11040 + assign $4\wr_detect$10[0:0]$10939 $3\wr_detect$10[0:0]$10938 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$11042 1'1 + assign $5\wr_detect$10[0:0]$10940 1'1 case - assign $5\wr_detect$10[0:0]$11042 $4\wr_detect$10[0:0]$11041 + assign $5\wr_detect$10[0:0]$10940 $4\wr_detect$10[0:0]$10939 end case - assign $1\wr_detect$10[0:0]$11038 1'0 + assign $1\wr_detect$10[0:0]$10936 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11037 + update \wr_detect$10 $0\wr_detect$10[0:0]$10935 end - attribute \src "libresoc.v:179112.3-179144.6" - process $proc$libresoc.v:179112$11043 + attribute \src "libresoc.v:179664.3-179696.6" + process $proc$libresoc.v:179664$10941 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$11044 $5\reg$next[1:0]$11049 - attribute \src "libresoc.v:179113.5-179113.29" + assign $0\reg$next[1:0]$10942 $5\reg$next[1:0]$10947 + attribute \src "libresoc.v:179665.5-179665.29" switch \initial - attribute \src "libresoc.v:179113.9-179113.17" + attribute \src "libresoc.v:179665.9-179665.17" case 1'1 case end @@ -368061,179 +334175,179 @@ module \reg_1$133 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$11045 \dest11__data_i + assign $1\reg$next[1:0]$10943 \dest11__data_i case - assign $1\reg$next[1:0]$11045 \reg + assign $1\reg$next[1:0]$10943 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$11046 \dest21__data_i + assign $2\reg$next[1:0]$10944 \dest21__data_i case - assign $2\reg$next[1:0]$11046 $1\reg$next[1:0]$11045 + assign $2\reg$next[1:0]$10944 $1\reg$next[1:0]$10943 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$11047 \dest31__data_i + assign $3\reg$next[1:0]$10945 \dest31__data_i case - assign $3\reg$next[1:0]$11047 $2\reg$next[1:0]$11046 + assign $3\reg$next[1:0]$10945 $2\reg$next[1:0]$10944 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$11048 \w1__data_i + assign $4\reg$next[1:0]$10946 \w1__data_i case - assign $4\reg$next[1:0]$11048 $3\reg$next[1:0]$11047 + assign $4\reg$next[1:0]$10946 $3\reg$next[1:0]$10945 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$11049 2'00 + assign $5\reg$next[1:0]$10947 2'00 case - assign $5\reg$next[1:0]$11049 $4\reg$next[1:0]$11048 + assign $5\reg$next[1:0]$10947 $4\reg$next[1:0]$10946 end sync always - update \reg$next $0\reg$next[1:0]$11044 + update \reg$next $0\reg$next[1:0]$10942 end - connect \$9 $not$libresoc.v:178770$10976_Y - connect \$1 $not$libresoc.v:178771$10977_Y - connect \$3 $not$libresoc.v:178772$10978_Y - connect \$6 $not$libresoc.v:178773$10979_Y + connect \$9 $not$libresoc.v:179322$10874_Y + connect \$1 $not$libresoc.v:179323$10875_Y + connect \$3 $not$libresoc.v:179324$10876_Y + connect \$6 $not$libresoc.v:179325$10877_Y end -attribute \src "libresoc.v:179149.1-179498.10" +attribute \src "libresoc.v:179701.1-180050.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" attribute \generator "nMigen" module \reg_1$136 - attribute \src "libresoc.v:179219.3-179264.6" - wire width 64 $0\cia1__data_o$next[63:0]$11064 - attribute \src "libresoc.v:179217.3-179218.41" + attribute \src "libresoc.v:179771.3-179816.6" + wire width 64 $0\cia1__data_o$next[63:0]$10962 + attribute \src "libresoc.v:179769.3-179770.41" wire width 64 $0\cia1__data_o[63:0] - attribute \src "libresoc.v:179150.7-179150.20" + attribute \src "libresoc.v:179702.7-179702.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179301.3-179346.6" - wire width 64 $0\msr1__data_o$next[63:0]$11074 - attribute \src "libresoc.v:179215.3-179216.41" + attribute \src "libresoc.v:179853.3-179898.6" + wire width 64 $0\msr1__data_o$next[63:0]$10972 + attribute \src "libresoc.v:179767.3-179768.41" wire width 64 $0\msr1__data_o[63:0] - attribute \src "libresoc.v:179465.3-179497.6" - wire width 64 $0\reg$next[63:0]$11106 - attribute \src "libresoc.v:179211.3-179212.25" + attribute \src "libresoc.v:180017.3-180049.6" + wire width 64 $0\reg$next[63:0]$11004 + attribute \src "libresoc.v:179763.3-179764.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:179383.3-179428.6" - wire width 64 $0\sv1__data_o$next[63:0]$11090 - attribute \src "libresoc.v:179213.3-179214.39" + attribute \src "libresoc.v:179935.3-179980.6" + wire width 64 $0\sv1__data_o$next[63:0]$10988 + attribute \src "libresoc.v:179765.3-179766.39" wire width 64 $0\sv1__data_o[63:0] - attribute \src "libresoc.v:179347.3-179382.6" - wire $0\wr_detect$4[0:0]$11083 - attribute \src "libresoc.v:179429.3-179464.6" - wire $0\wr_detect$7[0:0]$11099 - attribute \src "libresoc.v:179265.3-179300.6" + attribute \src "libresoc.v:179899.3-179934.6" + wire $0\wr_detect$4[0:0]$10981 + attribute \src "libresoc.v:179981.3-180016.6" + wire $0\wr_detect$7[0:0]$10997 + attribute \src "libresoc.v:179817.3-179852.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179219.3-179264.6" - wire width 64 $1\cia1__data_o$next[63:0]$11065 - attribute \src "libresoc.v:179159.14-179159.49" + attribute \src "libresoc.v:179771.3-179816.6" + wire width 64 $1\cia1__data_o$next[63:0]$10963 + attribute \src "libresoc.v:179711.14-179711.49" wire width 64 $1\cia1__data_o[63:0] - attribute \src "libresoc.v:179301.3-179346.6" - wire width 64 $1\msr1__data_o$next[63:0]$11075 - attribute \src "libresoc.v:179176.14-179176.49" + attribute \src "libresoc.v:179853.3-179898.6" + wire width 64 $1\msr1__data_o$next[63:0]$10973 + attribute \src "libresoc.v:179728.14-179728.49" wire width 64 $1\msr1__data_o[63:0] - attribute \src "libresoc.v:179465.3-179497.6" - wire width 64 $1\reg$next[63:0]$11107 - attribute \src "libresoc.v:179188.14-179188.42" + attribute \src "libresoc.v:180017.3-180049.6" + wire width 64 $1\reg$next[63:0]$11005 + attribute \src "libresoc.v:179740.14-179740.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:179383.3-179428.6" - wire width 64 $1\sv1__data_o$next[63:0]$11091 - attribute \src "libresoc.v:179195.14-179195.48" + attribute \src "libresoc.v:179935.3-179980.6" + wire width 64 $1\sv1__data_o$next[63:0]$10989 + attribute \src "libresoc.v:179747.14-179747.48" wire width 64 $1\sv1__data_o[63:0] - attribute \src "libresoc.v:179347.3-179382.6" - wire $1\wr_detect$4[0:0]$11084 - attribute \src "libresoc.v:179429.3-179464.6" - wire $1\wr_detect$7[0:0]$11100 - attribute \src "libresoc.v:179265.3-179300.6" + attribute \src "libresoc.v:179899.3-179934.6" + wire $1\wr_detect$4[0:0]$10982 + attribute \src "libresoc.v:179981.3-180016.6" + wire $1\wr_detect$7[0:0]$10998 + attribute \src "libresoc.v:179817.3-179852.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179219.3-179264.6" - wire width 64 $2\cia1__data_o$next[63:0]$11066 - attribute \src "libresoc.v:179301.3-179346.6" - wire width 64 $2\msr1__data_o$next[63:0]$11076 - attribute \src "libresoc.v:179465.3-179497.6" - wire width 64 $2\reg$next[63:0]$11108 - attribute \src "libresoc.v:179383.3-179428.6" - wire width 64 $2\sv1__data_o$next[63:0]$11092 - attribute \src "libresoc.v:179347.3-179382.6" - wire $2\wr_detect$4[0:0]$11085 - attribute \src "libresoc.v:179429.3-179464.6" - wire $2\wr_detect$7[0:0]$11101 - attribute \src "libresoc.v:179265.3-179300.6" + attribute \src "libresoc.v:179771.3-179816.6" + wire width 64 $2\cia1__data_o$next[63:0]$10964 + attribute \src "libresoc.v:179853.3-179898.6" + wire width 64 $2\msr1__data_o$next[63:0]$10974 + attribute \src "libresoc.v:180017.3-180049.6" + wire width 64 $2\reg$next[63:0]$11006 + attribute \src "libresoc.v:179935.3-179980.6" + wire width 64 $2\sv1__data_o$next[63:0]$10990 + attribute \src "libresoc.v:179899.3-179934.6" + wire $2\wr_detect$4[0:0]$10983 + attribute \src "libresoc.v:179981.3-180016.6" + wire $2\wr_detect$7[0:0]$10999 + attribute \src "libresoc.v:179817.3-179852.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179219.3-179264.6" - wire width 64 $3\cia1__data_o$next[63:0]$11067 - attribute \src "libresoc.v:179301.3-179346.6" - wire width 64 $3\msr1__data_o$next[63:0]$11077 - attribute \src "libresoc.v:179465.3-179497.6" - wire width 64 $3\reg$next[63:0]$11109 - attribute \src "libresoc.v:179383.3-179428.6" - wire width 64 $3\sv1__data_o$next[63:0]$11093 - attribute \src "libresoc.v:179347.3-179382.6" - wire $3\wr_detect$4[0:0]$11086 - attribute \src "libresoc.v:179429.3-179464.6" - wire $3\wr_detect$7[0:0]$11102 - attribute \src "libresoc.v:179265.3-179300.6" + attribute \src "libresoc.v:179771.3-179816.6" + wire width 64 $3\cia1__data_o$next[63:0]$10965 + attribute \src "libresoc.v:179853.3-179898.6" + wire width 64 $3\msr1__data_o$next[63:0]$10975 + attribute \src "libresoc.v:180017.3-180049.6" + wire width 64 $3\reg$next[63:0]$11007 + attribute \src "libresoc.v:179935.3-179980.6" + wire width 64 $3\sv1__data_o$next[63:0]$10991 + attribute \src "libresoc.v:179899.3-179934.6" + wire $3\wr_detect$4[0:0]$10984 + attribute \src "libresoc.v:179981.3-180016.6" + wire $3\wr_detect$7[0:0]$11000 + attribute \src "libresoc.v:179817.3-179852.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179219.3-179264.6" - wire width 64 $4\cia1__data_o$next[63:0]$11068 - attribute \src "libresoc.v:179301.3-179346.6" - wire width 64 $4\msr1__data_o$next[63:0]$11078 - attribute \src "libresoc.v:179465.3-179497.6" - wire width 64 $4\reg$next[63:0]$11110 - attribute \src "libresoc.v:179383.3-179428.6" - wire width 64 $4\sv1__data_o$next[63:0]$11094 - attribute \src "libresoc.v:179347.3-179382.6" - wire $4\wr_detect$4[0:0]$11087 - attribute \src "libresoc.v:179429.3-179464.6" - wire $4\wr_detect$7[0:0]$11103 - attribute \src "libresoc.v:179265.3-179300.6" + attribute \src "libresoc.v:179771.3-179816.6" + wire width 64 $4\cia1__data_o$next[63:0]$10966 + attribute \src "libresoc.v:179853.3-179898.6" + wire width 64 $4\msr1__data_o$next[63:0]$10976 + attribute \src "libresoc.v:180017.3-180049.6" + wire width 64 $4\reg$next[63:0]$11008 + attribute \src "libresoc.v:179935.3-179980.6" + wire width 64 $4\sv1__data_o$next[63:0]$10992 + attribute \src "libresoc.v:179899.3-179934.6" + wire $4\wr_detect$4[0:0]$10985 + attribute \src "libresoc.v:179981.3-180016.6" + wire $4\wr_detect$7[0:0]$11001 + attribute \src "libresoc.v:179817.3-179852.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179219.3-179264.6" - wire width 64 $5\cia1__data_o$next[63:0]$11069 - attribute \src "libresoc.v:179301.3-179346.6" - wire width 64 $5\msr1__data_o$next[63:0]$11079 - attribute \src "libresoc.v:179465.3-179497.6" - wire width 64 $5\reg$next[63:0]$11111 - attribute \src "libresoc.v:179383.3-179428.6" - wire width 64 $5\sv1__data_o$next[63:0]$11095 - attribute \src "libresoc.v:179347.3-179382.6" - wire $5\wr_detect$4[0:0]$11088 - attribute \src "libresoc.v:179429.3-179464.6" - wire $5\wr_detect$7[0:0]$11104 - attribute \src "libresoc.v:179265.3-179300.6" + attribute \src "libresoc.v:179771.3-179816.6" + wire width 64 $5\cia1__data_o$next[63:0]$10967 + attribute \src "libresoc.v:179853.3-179898.6" + wire width 64 $5\msr1__data_o$next[63:0]$10977 + attribute \src "libresoc.v:180017.3-180049.6" + wire width 64 $5\reg$next[63:0]$11009 + attribute \src "libresoc.v:179935.3-179980.6" + wire width 64 $5\sv1__data_o$next[63:0]$10993 + attribute \src "libresoc.v:179899.3-179934.6" + wire $5\wr_detect$4[0:0]$10986 + attribute \src "libresoc.v:179981.3-180016.6" + wire $5\wr_detect$7[0:0]$11002 + attribute \src "libresoc.v:179817.3-179852.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:179219.3-179264.6" - wire width 64 $6\cia1__data_o$next[63:0]$11070 - attribute \src "libresoc.v:179301.3-179346.6" - wire width 64 $6\msr1__data_o$next[63:0]$11080 - attribute \src "libresoc.v:179383.3-179428.6" - wire width 64 $6\sv1__data_o$next[63:0]$11096 - attribute \src "libresoc.v:179219.3-179264.6" - wire width 64 $7\cia1__data_o$next[63:0]$11071 - attribute \src "libresoc.v:179301.3-179346.6" - wire width 64 $7\msr1__data_o$next[63:0]$11081 - attribute \src "libresoc.v:179383.3-179428.6" - wire width 64 $7\sv1__data_o$next[63:0]$11097 - attribute \src "libresoc.v:179208.17-179208.100" - wire $not$libresoc.v:179208$11056_Y - attribute \src "libresoc.v:179209.17-179209.103" - wire $not$libresoc.v:179209$11057_Y - attribute \src "libresoc.v:179210.17-179210.103" - wire $not$libresoc.v:179210$11058_Y + attribute \src "libresoc.v:179771.3-179816.6" + wire width 64 $6\cia1__data_o$next[63:0]$10968 + attribute \src "libresoc.v:179853.3-179898.6" + wire width 64 $6\msr1__data_o$next[63:0]$10978 + attribute \src "libresoc.v:179935.3-179980.6" + wire width 64 $6\sv1__data_o$next[63:0]$10994 + attribute \src "libresoc.v:179771.3-179816.6" + wire width 64 $7\cia1__data_o$next[63:0]$10969 + attribute \src "libresoc.v:179853.3-179898.6" + wire width 64 $7\msr1__data_o$next[63:0]$10979 + attribute \src "libresoc.v:179935.3-179980.6" + wire width 64 $7\sv1__data_o$next[63:0]$10995 + attribute \src "libresoc.v:179760.17-179760.100" + wire $not$libresoc.v:179760$10954_Y + attribute \src "libresoc.v:179761.17-179761.103" + wire $not$libresoc.v:179761$10955_Y + attribute \src "libresoc.v:179762.17-179762.103" + wire $not$libresoc.v:179762$10956_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -368246,15 +334360,15 @@ module \reg_1$136 wire width 64 \cia1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia1__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr11__wen - attribute \src "libresoc.v:179150.7-179150.15" + attribute \src "libresoc.v:179702.7-179702.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr1__data_i @@ -368291,106 +334405,106 @@ module \reg_1$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179208$11056 + cell $not $not$libresoc.v:179760$10954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:179208$11056_Y + connect \Y $not$libresoc.v:179760$10954_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179209$11057 + cell $not $not$libresoc.v:179761$10955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:179209$11057_Y + connect \Y $not$libresoc.v:179761$10955_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179210$11058 + cell $not $not$libresoc.v:179762$10956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:179210$11058_Y + connect \Y $not$libresoc.v:179762$10956_Y end - attribute \src "libresoc.v:179150.7-179150.20" - process $proc$libresoc.v:179150$11112 + attribute \src "libresoc.v:179702.7-179702.20" + process $proc$libresoc.v:179702$11010 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179159.14-179159.49" - process $proc$libresoc.v:179159$11113 + attribute \src "libresoc.v:179711.14-179711.49" + process $proc$libresoc.v:179711$11011 assign { } { } assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia1__data_o $1\cia1__data_o[63:0] end - attribute \src "libresoc.v:179176.14-179176.49" - process $proc$libresoc.v:179176$11114 + attribute \src "libresoc.v:179728.14-179728.49" + process $proc$libresoc.v:179728$11012 assign { } { } assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr1__data_o $1\msr1__data_o[63:0] end - attribute \src "libresoc.v:179188.14-179188.42" - process $proc$libresoc.v:179188$11115 + attribute \src "libresoc.v:179740.14-179740.42" + process $proc$libresoc.v:179740$11013 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:179195.14-179195.48" - process $proc$libresoc.v:179195$11116 + attribute \src "libresoc.v:179747.14-179747.48" + process $proc$libresoc.v:179747$11014 assign { } { } assign $1\sv1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv1__data_o $1\sv1__data_o[63:0] end - attribute \src "libresoc.v:179211.3-179212.25" - process $proc$libresoc.v:179211$11059 + attribute \src "libresoc.v:179763.3-179764.25" + process $proc$libresoc.v:179763$10957 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:179213.3-179214.39" - process $proc$libresoc.v:179213$11060 + attribute \src "libresoc.v:179765.3-179766.39" + process $proc$libresoc.v:179765$10958 assign { } { } assign $0\sv1__data_o[63:0] \sv1__data_o$next sync posedge \coresync_clk update \sv1__data_o $0\sv1__data_o[63:0] end - attribute \src "libresoc.v:179215.3-179216.41" - process $proc$libresoc.v:179215$11061 + attribute \src "libresoc.v:179767.3-179768.41" + process $proc$libresoc.v:179767$10959 assign { } { } assign $0\msr1__data_o[63:0] \msr1__data_o$next sync posedge \coresync_clk update \msr1__data_o $0\msr1__data_o[63:0] end - attribute \src "libresoc.v:179217.3-179218.41" - process $proc$libresoc.v:179217$11062 + attribute \src "libresoc.v:179769.3-179770.41" + process $proc$libresoc.v:179769$10960 assign { } { } assign $0\cia1__data_o[63:0] \cia1__data_o$next sync posedge \coresync_clk update \cia1__data_o $0\cia1__data_o[63:0] end - attribute \src "libresoc.v:179219.3-179264.6" - process $proc$libresoc.v:179219$11063 + attribute \src "libresoc.v:179771.3-179816.6" + process $proc$libresoc.v:179771$10961 assign { } { } assign { } { } assign { } { } - assign $0\cia1__data_o$next[63:0]$11064 $7\cia1__data_o$next[63:0]$11071 - attribute \src "libresoc.v:179220.5-179220.29" + assign $0\cia1__data_o$next[63:0]$10962 $7\cia1__data_o$next[63:0]$10969 + attribute \src "libresoc.v:179772.5-179772.29" switch \initial - attribute \src "libresoc.v:179220.9-179220.17" + attribute \src "libresoc.v:179772.9-179772.17" case 1'1 case end @@ -368403,75 +334517,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\cia1__data_o$next[63:0]$11065 $6\cia1__data_o$next[63:0]$11070 + assign $1\cia1__data_o$next[63:0]$10963 $6\cia1__data_o$next[63:0]$10968 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia1__data_o$next[63:0]$11066 \nia1__data_i + assign $2\cia1__data_o$next[63:0]$10964 \nia1__data_i case - assign $2\cia1__data_o$next[63:0]$11066 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia1__data_o$next[63:0]$10964 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia1__data_o$next[63:0]$11067 \msr1__data_i + assign $3\cia1__data_o$next[63:0]$10965 \msr1__data_i case - assign $3\cia1__data_o$next[63:0]$11067 $2\cia1__data_o$next[63:0]$11066 + assign $3\cia1__data_o$next[63:0]$10965 $2\cia1__data_o$next[63:0]$10964 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia1__data_o$next[63:0]$11068 \sv1__data_i + assign $4\cia1__data_o$next[63:0]$10966 \sv1__data_i case - assign $4\cia1__data_o$next[63:0]$11068 $3\cia1__data_o$next[63:0]$11067 + assign $4\cia1__data_o$next[63:0]$10966 $3\cia1__data_o$next[63:0]$10965 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia1__data_o$next[63:0]$11069 \d_wr11__data_i + assign $5\cia1__data_o$next[63:0]$10967 \d_wr11__data_i case - assign $5\cia1__data_o$next[63:0]$11069 $4\cia1__data_o$next[63:0]$11068 + assign $5\cia1__data_o$next[63:0]$10967 $4\cia1__data_o$next[63:0]$10966 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia1__data_o$next[63:0]$11070 \reg + assign $6\cia1__data_o$next[63:0]$10968 \reg case - assign $6\cia1__data_o$next[63:0]$11070 $5\cia1__data_o$next[63:0]$11069 + assign $6\cia1__data_o$next[63:0]$10968 $5\cia1__data_o$next[63:0]$10967 end case - assign $1\cia1__data_o$next[63:0]$11065 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia1__data_o$next[63:0]$10963 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia1__data_o$next[63:0]$11071 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia1__data_o$next[63:0]$10969 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia1__data_o$next[63:0]$11071 $1\cia1__data_o$next[63:0]$11065 + assign $7\cia1__data_o$next[63:0]$10969 $1\cia1__data_o$next[63:0]$10963 end sync always - update \cia1__data_o$next $0\cia1__data_o$next[63:0]$11064 + update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10962 end - attribute \src "libresoc.v:179265.3-179300.6" - process $proc$libresoc.v:179265$11072 + attribute \src "libresoc.v:179817.3-179852.6" + process $proc$libresoc.v:179817$10970 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:179266.5-179266.29" + attribute \src "libresoc.v:179818.5-179818.29" switch \initial - attribute \src "libresoc.v:179266.9-179266.17" + attribute \src "libresoc.v:179818.9-179818.17" case 1'1 case end @@ -368527,15 +334641,15 @@ module \reg_1$136 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:179301.3-179346.6" - process $proc$libresoc.v:179301$11073 + attribute \src "libresoc.v:179853.3-179898.6" + process $proc$libresoc.v:179853$10971 assign { } { } assign { } { } assign { } { } - assign $0\msr1__data_o$next[63:0]$11074 $7\msr1__data_o$next[63:0]$11081 - attribute \src "libresoc.v:179302.5-179302.29" + assign $0\msr1__data_o$next[63:0]$10972 $7\msr1__data_o$next[63:0]$10979 + attribute \src "libresoc.v:179854.5-179854.29" switch \initial - attribute \src "libresoc.v:179302.9-179302.17" + attribute \src "libresoc.v:179854.9-179854.17" case 1'1 case end @@ -368548,75 +334662,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\msr1__data_o$next[63:0]$11075 $6\msr1__data_o$next[63:0]$11080 + assign $1\msr1__data_o$next[63:0]$10973 $6\msr1__data_o$next[63:0]$10978 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr1__data_o$next[63:0]$11076 \nia1__data_i + assign $2\msr1__data_o$next[63:0]$10974 \nia1__data_i case - assign $2\msr1__data_o$next[63:0]$11076 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr1__data_o$next[63:0]$10974 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr1__data_o$next[63:0]$11077 \msr1__data_i + assign $3\msr1__data_o$next[63:0]$10975 \msr1__data_i case - assign $3\msr1__data_o$next[63:0]$11077 $2\msr1__data_o$next[63:0]$11076 + assign $3\msr1__data_o$next[63:0]$10975 $2\msr1__data_o$next[63:0]$10974 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr1__data_o$next[63:0]$11078 \sv1__data_i + assign $4\msr1__data_o$next[63:0]$10976 \sv1__data_i case - assign $4\msr1__data_o$next[63:0]$11078 $3\msr1__data_o$next[63:0]$11077 + assign $4\msr1__data_o$next[63:0]$10976 $3\msr1__data_o$next[63:0]$10975 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr1__data_o$next[63:0]$11079 \d_wr11__data_i + assign $5\msr1__data_o$next[63:0]$10977 \d_wr11__data_i case - assign $5\msr1__data_o$next[63:0]$11079 $4\msr1__data_o$next[63:0]$11078 + assign $5\msr1__data_o$next[63:0]$10977 $4\msr1__data_o$next[63:0]$10976 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr1__data_o$next[63:0]$11080 \reg + assign $6\msr1__data_o$next[63:0]$10978 \reg case - assign $6\msr1__data_o$next[63:0]$11080 $5\msr1__data_o$next[63:0]$11079 + assign $6\msr1__data_o$next[63:0]$10978 $5\msr1__data_o$next[63:0]$10977 end case - assign $1\msr1__data_o$next[63:0]$11075 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr1__data_o$next[63:0]$10973 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr1__data_o$next[63:0]$11081 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr1__data_o$next[63:0]$10979 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr1__data_o$next[63:0]$11081 $1\msr1__data_o$next[63:0]$11075 + assign $7\msr1__data_o$next[63:0]$10979 $1\msr1__data_o$next[63:0]$10973 end sync always - update \msr1__data_o$next $0\msr1__data_o$next[63:0]$11074 + update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10972 end - attribute \src "libresoc.v:179347.3-179382.6" - process $proc$libresoc.v:179347$11082 + attribute \src "libresoc.v:179899.3-179934.6" + process $proc$libresoc.v:179899$10980 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11083 $1\wr_detect$4[0:0]$11084 - attribute \src "libresoc.v:179348.5-179348.29" + assign $0\wr_detect$4[0:0]$10981 $1\wr_detect$4[0:0]$10982 + attribute \src "libresoc.v:179900.5-179900.29" switch \initial - attribute \src "libresoc.v:179348.9-179348.17" + attribute \src "libresoc.v:179900.9-179900.17" case 1'1 case end @@ -368629,58 +334743,58 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11084 $5\wr_detect$4[0:0]$11088 + assign $1\wr_detect$4[0:0]$10982 $5\wr_detect$4[0:0]$10986 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11085 1'1 + assign $2\wr_detect$4[0:0]$10983 1'1 case - assign $2\wr_detect$4[0:0]$11085 1'0 + assign $2\wr_detect$4[0:0]$10983 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11086 1'1 + assign $3\wr_detect$4[0:0]$10984 1'1 case - assign $3\wr_detect$4[0:0]$11086 $2\wr_detect$4[0:0]$11085 + assign $3\wr_detect$4[0:0]$10984 $2\wr_detect$4[0:0]$10983 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11087 1'1 + assign $4\wr_detect$4[0:0]$10985 1'1 case - assign $4\wr_detect$4[0:0]$11087 $3\wr_detect$4[0:0]$11086 + assign $4\wr_detect$4[0:0]$10985 $3\wr_detect$4[0:0]$10984 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11088 1'1 + assign $5\wr_detect$4[0:0]$10986 1'1 case - assign $5\wr_detect$4[0:0]$11088 $4\wr_detect$4[0:0]$11087 + assign $5\wr_detect$4[0:0]$10986 $4\wr_detect$4[0:0]$10985 end case - assign $1\wr_detect$4[0:0]$11084 1'0 + assign $1\wr_detect$4[0:0]$10982 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11083 + update \wr_detect$4 $0\wr_detect$4[0:0]$10981 end - attribute \src "libresoc.v:179383.3-179428.6" - process $proc$libresoc.v:179383$11089 + attribute \src "libresoc.v:179935.3-179980.6" + process $proc$libresoc.v:179935$10987 assign { } { } assign { } { } assign { } { } - assign $0\sv1__data_o$next[63:0]$11090 $7\sv1__data_o$next[63:0]$11097 - attribute \src "libresoc.v:179384.5-179384.29" + assign $0\sv1__data_o$next[63:0]$10988 $7\sv1__data_o$next[63:0]$10995 + attribute \src "libresoc.v:179936.5-179936.29" switch \initial - attribute \src "libresoc.v:179384.9-179384.17" + attribute \src "libresoc.v:179936.9-179936.17" case 1'1 case end @@ -368693,75 +334807,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\sv1__data_o$next[63:0]$11091 $6\sv1__data_o$next[63:0]$11096 + assign $1\sv1__data_o$next[63:0]$10989 $6\sv1__data_o$next[63:0]$10994 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv1__data_o$next[63:0]$11092 \nia1__data_i + assign $2\sv1__data_o$next[63:0]$10990 \nia1__data_i case - assign $2\sv1__data_o$next[63:0]$11092 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv1__data_o$next[63:0]$10990 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv1__data_o$next[63:0]$11093 \msr1__data_i + assign $3\sv1__data_o$next[63:0]$10991 \msr1__data_i case - assign $3\sv1__data_o$next[63:0]$11093 $2\sv1__data_o$next[63:0]$11092 + assign $3\sv1__data_o$next[63:0]$10991 $2\sv1__data_o$next[63:0]$10990 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv1__data_o$next[63:0]$11094 \sv1__data_i + assign $4\sv1__data_o$next[63:0]$10992 \sv1__data_i case - assign $4\sv1__data_o$next[63:0]$11094 $3\sv1__data_o$next[63:0]$11093 + assign $4\sv1__data_o$next[63:0]$10992 $3\sv1__data_o$next[63:0]$10991 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv1__data_o$next[63:0]$11095 \d_wr11__data_i + assign $5\sv1__data_o$next[63:0]$10993 \d_wr11__data_i case - assign $5\sv1__data_o$next[63:0]$11095 $4\sv1__data_o$next[63:0]$11094 + assign $5\sv1__data_o$next[63:0]$10993 $4\sv1__data_o$next[63:0]$10992 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv1__data_o$next[63:0]$11096 \reg + assign $6\sv1__data_o$next[63:0]$10994 \reg case - assign $6\sv1__data_o$next[63:0]$11096 $5\sv1__data_o$next[63:0]$11095 + assign $6\sv1__data_o$next[63:0]$10994 $5\sv1__data_o$next[63:0]$10993 end case - assign $1\sv1__data_o$next[63:0]$11091 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv1__data_o$next[63:0]$10989 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv1__data_o$next[63:0]$11097 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv1__data_o$next[63:0]$10995 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv1__data_o$next[63:0]$11097 $1\sv1__data_o$next[63:0]$11091 + assign $7\sv1__data_o$next[63:0]$10995 $1\sv1__data_o$next[63:0]$10989 end sync always - update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11090 + update \sv1__data_o$next $0\sv1__data_o$next[63:0]$10988 end - attribute \src "libresoc.v:179429.3-179464.6" - process $proc$libresoc.v:179429$11098 + attribute \src "libresoc.v:179981.3-180016.6" + process $proc$libresoc.v:179981$10996 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11099 $1\wr_detect$7[0:0]$11100 - attribute \src "libresoc.v:179430.5-179430.29" + assign $0\wr_detect$7[0:0]$10997 $1\wr_detect$7[0:0]$10998 + attribute \src "libresoc.v:179982.5-179982.29" switch \initial - attribute \src "libresoc.v:179430.9-179430.17" + attribute \src "libresoc.v:179982.9-179982.17" case 1'1 case end @@ -368774,61 +334888,61 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11100 $5\wr_detect$7[0:0]$11104 + assign $1\wr_detect$7[0:0]$10998 $5\wr_detect$7[0:0]$11002 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11101 1'1 + assign $2\wr_detect$7[0:0]$10999 1'1 case - assign $2\wr_detect$7[0:0]$11101 1'0 + assign $2\wr_detect$7[0:0]$10999 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11102 1'1 + assign $3\wr_detect$7[0:0]$11000 1'1 case - assign $3\wr_detect$7[0:0]$11102 $2\wr_detect$7[0:0]$11101 + assign $3\wr_detect$7[0:0]$11000 $2\wr_detect$7[0:0]$10999 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11103 1'1 + assign $4\wr_detect$7[0:0]$11001 1'1 case - assign $4\wr_detect$7[0:0]$11103 $3\wr_detect$7[0:0]$11102 + assign $4\wr_detect$7[0:0]$11001 $3\wr_detect$7[0:0]$11000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11104 1'1 + assign $5\wr_detect$7[0:0]$11002 1'1 case - assign $5\wr_detect$7[0:0]$11104 $4\wr_detect$7[0:0]$11103 + assign $5\wr_detect$7[0:0]$11002 $4\wr_detect$7[0:0]$11001 end case - assign $1\wr_detect$7[0:0]$11100 1'0 + assign $1\wr_detect$7[0:0]$10998 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11099 + update \wr_detect$7 $0\wr_detect$7[0:0]$10997 end - attribute \src "libresoc.v:179465.3-179497.6" - process $proc$libresoc.v:179465$11105 + attribute \src "libresoc.v:180017.3-180049.6" + process $proc$libresoc.v:180017$11003 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11106 $5\reg$next[63:0]$11111 - attribute \src "libresoc.v:179466.5-179466.29" + assign $0\reg$next[63:0]$11004 $5\reg$next[63:0]$11009 + attribute \src "libresoc.v:180018.5-180018.29" switch \initial - attribute \src "libresoc.v:179466.9-179466.17" + attribute \src "libresoc.v:180018.9-180018.17" case 1'1 case end @@ -368837,324 +334951,286 @@ module \reg_1$136 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11107 \nia1__data_i + assign $1\reg$next[63:0]$11005 \nia1__data_i case - assign $1\reg$next[63:0]$11107 \reg + assign $1\reg$next[63:0]$11005 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11108 \msr1__data_i + assign $2\reg$next[63:0]$11006 \msr1__data_i case - assign $2\reg$next[63:0]$11108 $1\reg$next[63:0]$11107 + assign $2\reg$next[63:0]$11006 $1\reg$next[63:0]$11005 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11109 \sv1__data_i + assign $3\reg$next[63:0]$11007 \sv1__data_i case - assign $3\reg$next[63:0]$11109 $2\reg$next[63:0]$11108 + assign $3\reg$next[63:0]$11007 $2\reg$next[63:0]$11006 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11110 \d_wr11__data_i + assign $4\reg$next[63:0]$11008 \d_wr11__data_i case - assign $4\reg$next[63:0]$11110 $3\reg$next[63:0]$11109 + assign $4\reg$next[63:0]$11008 $3\reg$next[63:0]$11007 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$11111 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11009 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$11111 $4\reg$next[63:0]$11110 + assign $5\reg$next[63:0]$11009 $4\reg$next[63:0]$11008 end sync always - update \reg$next $0\reg$next[63:0]$11106 + update \reg$next $0\reg$next[63:0]$11004 end - connect \$1 $not$libresoc.v:179208$11056_Y - connect \$3 $not$libresoc.v:179209$11057_Y - connect \$6 $not$libresoc.v:179210$11058_Y + connect \$1 $not$libresoc.v:179760$10954_Y + connect \$3 $not$libresoc.v:179761$10955_Y + connect \$6 $not$libresoc.v:179762$10956_Y end -attribute \src "libresoc.v:179502.1-180057.10" +attribute \src "libresoc.v:180054.1-180525.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" attribute \generator "nMigen" module \reg_2 - attribute \src "libresoc.v:179610.3-179649.6" - wire width 4 $0\cr_pred2__data_o$next[3:0]$11131 - attribute \src "libresoc.v:179608.3-179609.49" - wire width 4 $0\cr_pred2__data_o[3:0] - attribute \src "libresoc.v:179503.7-179503.20" + attribute \src "libresoc.v:180055.7-180055.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179680.3-179719.6" - wire width 4 $0\r22__data_o$next[3:0]$11140 - attribute \src "libresoc.v:179598.3-179599.39" + attribute \src "libresoc.v:180455.3-180494.6" + wire width 4 $0\r22__data_o$next[3:0]$11084 + attribute \src "libresoc.v:180138.3-180139.39" wire width 4 $0\r22__data_o[3:0] - attribute \src "libresoc.v:179987.3-180026.6" - wire width 4 $0\r2__data_o$next[3:0]$11202 - attribute \src "libresoc.v:179600.3-179601.37" + attribute \src "libresoc.v:180385.3-180424.6" + wire width 4 $0\r2__data_o$next[3:0]$11070 + attribute \src "libresoc.v:180140.3-180141.37" wire width 4 $0\r2__data_o[3:0] - attribute \src "libresoc.v:179750.3-179776.6" - wire width 4 $0\reg$next[3:0]$11154 - attribute \src "libresoc.v:179596.3-179597.25" + attribute \src "libresoc.v:180218.3-180244.6" + wire width 4 $0\reg$next[3:0]$11036 + attribute \src "libresoc.v:180136.3-180137.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:179777.3-179816.6" - wire width 4 $0\src12__data_o$next[3:0]$11160 - attribute \src "libresoc.v:179606.3-179607.43" + attribute \src "libresoc.v:180148.3-180187.6" + wire width 4 $0\src12__data_o$next[3:0]$11027 + attribute \src "libresoc.v:180146.3-180147.43" wire width 4 $0\src12__data_o[3:0] - attribute \src "libresoc.v:179847.3-179886.6" - wire width 4 $0\src22__data_o$next[3:0]$11174 - attribute \src "libresoc.v:179604.3-179605.43" + attribute \src "libresoc.v:180245.3-180284.6" + wire width 4 $0\src22__data_o$next[3:0]$11042 + attribute \src "libresoc.v:180144.3-180145.43" wire width 4 $0\src22__data_o[3:0] - attribute \src "libresoc.v:179917.3-179956.6" - wire width 4 $0\src32__data_o$next[3:0]$11188 - attribute \src "libresoc.v:179602.3-179603.43" + attribute \src "libresoc.v:180315.3-180354.6" + wire width 4 $0\src32__data_o$next[3:0]$11056 + attribute \src "libresoc.v:180142.3-180143.43" wire width 4 $0\src32__data_o[3:0] - attribute \src "libresoc.v:179957.3-179986.6" - wire $0\wr_detect$10[0:0]$11196 - attribute \src "libresoc.v:180027.3-180056.6" - wire $0\wr_detect$13[0:0]$11210 - attribute \src "libresoc.v:179720.3-179749.6" - wire $0\wr_detect$16[0:0]$11148 - attribute \src "libresoc.v:179817.3-179846.6" - wire $0\wr_detect$4[0:0]$11168 - attribute \src "libresoc.v:179887.3-179916.6" - wire $0\wr_detect$7[0:0]$11182 - attribute \src "libresoc.v:179650.3-179679.6" + attribute \src "libresoc.v:180425.3-180454.6" + wire $0\wr_detect$10[0:0]$11078 + attribute \src "libresoc.v:180495.3-180524.6" + wire $0\wr_detect$13[0:0]$11092 + attribute \src "libresoc.v:180285.3-180314.6" + wire $0\wr_detect$4[0:0]$11050 + attribute \src "libresoc.v:180355.3-180384.6" + wire $0\wr_detect$7[0:0]$11064 + attribute \src "libresoc.v:180188.3-180217.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179610.3-179649.6" - wire width 4 $1\cr_pred2__data_o$next[3:0]$11132 - attribute \src "libresoc.v:179522.13-179522.36" - wire width 4 $1\cr_pred2__data_o[3:0] - attribute \src "libresoc.v:179680.3-179719.6" - wire width 4 $1\r22__data_o$next[3:0]$11141 - attribute \src "libresoc.v:179537.13-179537.31" + attribute \src "libresoc.v:180455.3-180494.6" + wire width 4 $1\r22__data_o$next[3:0]$11085 + attribute \src "libresoc.v:180080.13-180080.31" wire width 4 $1\r22__data_o[3:0] - attribute \src "libresoc.v:179987.3-180026.6" - wire width 4 $1\r2__data_o$next[3:0]$11203 - attribute \src "libresoc.v:179544.13-179544.30" + attribute \src "libresoc.v:180385.3-180424.6" + wire width 4 $1\r2__data_o$next[3:0]$11071 + attribute \src "libresoc.v:180087.13-180087.30" wire width 4 $1\r2__data_o[3:0] - attribute \src "libresoc.v:179750.3-179776.6" - wire width 4 $1\reg$next[3:0]$11155 - attribute \src "libresoc.v:179550.13-179550.25" + attribute \src "libresoc.v:180218.3-180244.6" + wire width 4 $1\reg$next[3:0]$11037 + attribute \src "libresoc.v:180093.13-180093.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:179777.3-179816.6" - wire width 4 $1\src12__data_o$next[3:0]$11161 - attribute \src "libresoc.v:179555.13-179555.33" + attribute \src "libresoc.v:180148.3-180187.6" + wire width 4 $1\src12__data_o$next[3:0]$11028 + attribute \src "libresoc.v:180098.13-180098.33" wire width 4 $1\src12__data_o[3:0] - attribute \src "libresoc.v:179847.3-179886.6" - wire width 4 $1\src22__data_o$next[3:0]$11175 - attribute \src "libresoc.v:179562.13-179562.33" + attribute \src "libresoc.v:180245.3-180284.6" + wire width 4 $1\src22__data_o$next[3:0]$11043 + attribute \src "libresoc.v:180105.13-180105.33" wire width 4 $1\src22__data_o[3:0] - attribute \src "libresoc.v:179917.3-179956.6" - wire width 4 $1\src32__data_o$next[3:0]$11189 - attribute \src "libresoc.v:179569.13-179569.33" + attribute \src "libresoc.v:180315.3-180354.6" + wire width 4 $1\src32__data_o$next[3:0]$11057 + attribute \src "libresoc.v:180112.13-180112.33" wire width 4 $1\src32__data_o[3:0] - attribute \src "libresoc.v:179957.3-179986.6" - wire $1\wr_detect$10[0:0]$11197 - attribute \src "libresoc.v:180027.3-180056.6" - wire $1\wr_detect$13[0:0]$11211 - attribute \src "libresoc.v:179720.3-179749.6" - wire $1\wr_detect$16[0:0]$11149 - attribute \src "libresoc.v:179817.3-179846.6" - wire $1\wr_detect$4[0:0]$11169 - attribute \src "libresoc.v:179887.3-179916.6" - wire $1\wr_detect$7[0:0]$11183 - attribute \src "libresoc.v:179650.3-179679.6" + attribute \src "libresoc.v:180425.3-180454.6" + wire $1\wr_detect$10[0:0]$11079 + attribute \src "libresoc.v:180495.3-180524.6" + wire $1\wr_detect$13[0:0]$11093 + attribute \src "libresoc.v:180285.3-180314.6" + wire $1\wr_detect$4[0:0]$11051 + attribute \src "libresoc.v:180355.3-180384.6" + wire $1\wr_detect$7[0:0]$11065 + attribute \src "libresoc.v:180188.3-180217.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179610.3-179649.6" - wire width 4 $2\cr_pred2__data_o$next[3:0]$11133 - attribute \src "libresoc.v:179680.3-179719.6" - wire width 4 $2\r22__data_o$next[3:0]$11142 - attribute \src "libresoc.v:179987.3-180026.6" - wire width 4 $2\r2__data_o$next[3:0]$11204 - attribute \src "libresoc.v:179750.3-179776.6" - wire width 4 $2\reg$next[3:0]$11156 - attribute \src "libresoc.v:179777.3-179816.6" - wire width 4 $2\src12__data_o$next[3:0]$11162 - attribute \src "libresoc.v:179847.3-179886.6" - wire width 4 $2\src22__data_o$next[3:0]$11176 - attribute \src "libresoc.v:179917.3-179956.6" - wire width 4 $2\src32__data_o$next[3:0]$11190 - attribute \src "libresoc.v:179957.3-179986.6" - wire $2\wr_detect$10[0:0]$11198 - attribute \src "libresoc.v:180027.3-180056.6" - wire $2\wr_detect$13[0:0]$11212 - attribute \src "libresoc.v:179720.3-179749.6" - wire $2\wr_detect$16[0:0]$11150 - attribute \src "libresoc.v:179817.3-179846.6" - wire $2\wr_detect$4[0:0]$11170 - attribute \src "libresoc.v:179887.3-179916.6" - wire $2\wr_detect$7[0:0]$11184 - attribute \src "libresoc.v:179650.3-179679.6" + attribute \src "libresoc.v:180455.3-180494.6" + wire width 4 $2\r22__data_o$next[3:0]$11086 + attribute \src "libresoc.v:180385.3-180424.6" + wire width 4 $2\r2__data_o$next[3:0]$11072 + attribute \src "libresoc.v:180218.3-180244.6" + wire width 4 $2\reg$next[3:0]$11038 + attribute \src "libresoc.v:180148.3-180187.6" + wire width 4 $2\src12__data_o$next[3:0]$11029 + attribute \src "libresoc.v:180245.3-180284.6" + wire width 4 $2\src22__data_o$next[3:0]$11044 + attribute \src "libresoc.v:180315.3-180354.6" + wire width 4 $2\src32__data_o$next[3:0]$11058 + attribute \src "libresoc.v:180425.3-180454.6" + wire $2\wr_detect$10[0:0]$11080 + attribute \src "libresoc.v:180495.3-180524.6" + wire $2\wr_detect$13[0:0]$11094 + attribute \src "libresoc.v:180285.3-180314.6" + wire $2\wr_detect$4[0:0]$11052 + attribute \src "libresoc.v:180355.3-180384.6" + wire $2\wr_detect$7[0:0]$11066 + attribute \src "libresoc.v:180188.3-180217.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179610.3-179649.6" - wire width 4 $3\cr_pred2__data_o$next[3:0]$11134 - attribute \src "libresoc.v:179680.3-179719.6" - wire width 4 $3\r22__data_o$next[3:0]$11143 - attribute \src "libresoc.v:179987.3-180026.6" - wire width 4 $3\r2__data_o$next[3:0]$11205 - attribute \src "libresoc.v:179750.3-179776.6" - wire width 4 $3\reg$next[3:0]$11157 - attribute \src "libresoc.v:179777.3-179816.6" - wire width 4 $3\src12__data_o$next[3:0]$11163 - attribute \src "libresoc.v:179847.3-179886.6" - wire width 4 $3\src22__data_o$next[3:0]$11177 - attribute \src "libresoc.v:179917.3-179956.6" - wire width 4 $3\src32__data_o$next[3:0]$11191 - attribute \src "libresoc.v:179957.3-179986.6" - wire $3\wr_detect$10[0:0]$11199 - attribute \src "libresoc.v:180027.3-180056.6" - wire $3\wr_detect$13[0:0]$11213 - attribute \src "libresoc.v:179720.3-179749.6" - wire $3\wr_detect$16[0:0]$11151 - attribute \src "libresoc.v:179817.3-179846.6" - wire $3\wr_detect$4[0:0]$11171 - attribute \src "libresoc.v:179887.3-179916.6" - wire $3\wr_detect$7[0:0]$11185 - attribute \src "libresoc.v:179650.3-179679.6" + attribute \src "libresoc.v:180455.3-180494.6" + wire width 4 $3\r22__data_o$next[3:0]$11087 + attribute \src "libresoc.v:180385.3-180424.6" + wire width 4 $3\r2__data_o$next[3:0]$11073 + attribute \src "libresoc.v:180218.3-180244.6" + wire width 4 $3\reg$next[3:0]$11039 + attribute \src "libresoc.v:180148.3-180187.6" + wire width 4 $3\src12__data_o$next[3:0]$11030 + attribute \src "libresoc.v:180245.3-180284.6" + wire width 4 $3\src22__data_o$next[3:0]$11045 + attribute \src "libresoc.v:180315.3-180354.6" + wire width 4 $3\src32__data_o$next[3:0]$11059 + attribute \src "libresoc.v:180425.3-180454.6" + wire $3\wr_detect$10[0:0]$11081 + attribute \src "libresoc.v:180495.3-180524.6" + wire $3\wr_detect$13[0:0]$11095 + attribute \src "libresoc.v:180285.3-180314.6" + wire $3\wr_detect$4[0:0]$11053 + attribute \src "libresoc.v:180355.3-180384.6" + wire $3\wr_detect$7[0:0]$11067 + attribute \src "libresoc.v:180188.3-180217.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179610.3-179649.6" - wire width 4 $4\cr_pred2__data_o$next[3:0]$11135 - attribute \src "libresoc.v:179680.3-179719.6" - wire width 4 $4\r22__data_o$next[3:0]$11144 - attribute \src "libresoc.v:179987.3-180026.6" - wire width 4 $4\r2__data_o$next[3:0]$11206 - attribute \src "libresoc.v:179750.3-179776.6" - wire width 4 $4\reg$next[3:0]$11158 - attribute \src "libresoc.v:179777.3-179816.6" - wire width 4 $4\src12__data_o$next[3:0]$11164 - attribute \src "libresoc.v:179847.3-179886.6" - wire width 4 $4\src22__data_o$next[3:0]$11178 - attribute \src "libresoc.v:179917.3-179956.6" - wire width 4 $4\src32__data_o$next[3:0]$11192 - attribute \src "libresoc.v:179957.3-179986.6" - wire $4\wr_detect$10[0:0]$11200 - attribute \src "libresoc.v:180027.3-180056.6" - wire $4\wr_detect$13[0:0]$11214 - attribute \src "libresoc.v:179720.3-179749.6" - wire $4\wr_detect$16[0:0]$11152 - attribute \src "libresoc.v:179817.3-179846.6" - wire $4\wr_detect$4[0:0]$11172 - attribute \src "libresoc.v:179887.3-179916.6" - wire $4\wr_detect$7[0:0]$11186 - attribute \src "libresoc.v:179650.3-179679.6" + attribute \src "libresoc.v:180455.3-180494.6" + wire width 4 $4\r22__data_o$next[3:0]$11088 + attribute \src "libresoc.v:180385.3-180424.6" + wire width 4 $4\r2__data_o$next[3:0]$11074 + attribute \src "libresoc.v:180218.3-180244.6" + wire width 4 $4\reg$next[3:0]$11040 + attribute \src "libresoc.v:180148.3-180187.6" + wire width 4 $4\src12__data_o$next[3:0]$11031 + attribute \src "libresoc.v:180245.3-180284.6" + wire width 4 $4\src22__data_o$next[3:0]$11046 + attribute \src "libresoc.v:180315.3-180354.6" + wire width 4 $4\src32__data_o$next[3:0]$11060 + attribute \src "libresoc.v:180425.3-180454.6" + wire $4\wr_detect$10[0:0]$11082 + attribute \src "libresoc.v:180495.3-180524.6" + wire $4\wr_detect$13[0:0]$11096 + attribute \src "libresoc.v:180285.3-180314.6" + wire $4\wr_detect$4[0:0]$11054 + attribute \src "libresoc.v:180355.3-180384.6" + wire $4\wr_detect$7[0:0]$11068 + attribute \src "libresoc.v:180188.3-180217.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179610.3-179649.6" - wire width 4 $5\cr_pred2__data_o$next[3:0]$11136 - attribute \src "libresoc.v:179680.3-179719.6" - wire width 4 $5\r22__data_o$next[3:0]$11145 - attribute \src "libresoc.v:179987.3-180026.6" - wire width 4 $5\r2__data_o$next[3:0]$11207 - attribute \src "libresoc.v:179777.3-179816.6" - wire width 4 $5\src12__data_o$next[3:0]$11165 - attribute \src "libresoc.v:179847.3-179886.6" - wire width 4 $5\src22__data_o$next[3:0]$11179 - attribute \src "libresoc.v:179917.3-179956.6" - wire width 4 $5\src32__data_o$next[3:0]$11193 - attribute \src "libresoc.v:179610.3-179649.6" - wire width 4 $6\cr_pred2__data_o$next[3:0]$11137 - attribute \src "libresoc.v:179680.3-179719.6" - wire width 4 $6\r22__data_o$next[3:0]$11146 - attribute \src "libresoc.v:179987.3-180026.6" - wire width 4 $6\r2__data_o$next[3:0]$11208 - attribute \src "libresoc.v:179777.3-179816.6" - wire width 4 $6\src12__data_o$next[3:0]$11166 - attribute \src "libresoc.v:179847.3-179886.6" - wire width 4 $6\src22__data_o$next[3:0]$11180 - attribute \src "libresoc.v:179917.3-179956.6" - wire width 4 $6\src32__data_o$next[3:0]$11194 - attribute \src "libresoc.v:179590.17-179590.104" - wire $not$libresoc.v:179590$11117_Y - attribute \src "libresoc.v:179591.18-179591.105" - wire $not$libresoc.v:179591$11118_Y - attribute \src "libresoc.v:179592.18-179592.105" - wire $not$libresoc.v:179592$11119_Y - attribute \src "libresoc.v:179593.17-179593.100" - wire $not$libresoc.v:179593$11120_Y - attribute \src "libresoc.v:179594.17-179594.103" - wire $not$libresoc.v:179594$11121_Y - attribute \src "libresoc.v:179595.17-179595.103" - wire $not$libresoc.v:179595$11122_Y + attribute \src "libresoc.v:180455.3-180494.6" + wire width 4 $5\r22__data_o$next[3:0]$11089 + attribute \src "libresoc.v:180385.3-180424.6" + wire width 4 $5\r2__data_o$next[3:0]$11075 + attribute \src "libresoc.v:180148.3-180187.6" + wire width 4 $5\src12__data_o$next[3:0]$11032 + attribute \src "libresoc.v:180245.3-180284.6" + wire width 4 $5\src22__data_o$next[3:0]$11047 + attribute \src "libresoc.v:180315.3-180354.6" + wire width 4 $5\src32__data_o$next[3:0]$11061 + attribute \src "libresoc.v:180455.3-180494.6" + wire width 4 $6\r22__data_o$next[3:0]$11090 + attribute \src "libresoc.v:180385.3-180424.6" + wire width 4 $6\r2__data_o$next[3:0]$11076 + attribute \src "libresoc.v:180148.3-180187.6" + wire width 4 $6\src12__data_o$next[3:0]$11033 + attribute \src "libresoc.v:180245.3-180284.6" + wire width 4 $6\src22__data_o$next[3:0]$11048 + attribute \src "libresoc.v:180315.3-180354.6" + wire width 4 $6\src32__data_o$next[3:0]$11062 + attribute \src "libresoc.v:180131.17-180131.104" + wire $not$libresoc.v:180131$11015_Y + attribute \src "libresoc.v:180132.18-180132.105" + wire $not$libresoc.v:180132$11016_Y + attribute \src "libresoc.v:180133.17-180133.100" + wire $not$libresoc.v:180133$11017_Y + attribute \src "libresoc.v:180134.17-180134.103" + wire $not$libresoc.v:180134$11018_Y + attribute \src "libresoc.v:180135.17-180135.103" + wire $not$libresoc.v:180135$11019_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" - wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \cr_pred2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \cr_pred2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \cr_pred2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest12__data_i + wire width 4 input 9 \dest12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest12__wen + wire input 8 \dest12__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 13 \dest22__data_i + wire width 4 input 11 \dest22__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 12 \dest22__wen - attribute \src "libresoc.v:179503.7-179503.15" + wire input 10 \dest22__wen + attribute \src "libresoc.v:180055.7-180055.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 16 \r22__data_o + wire width 4 output 14 \r22__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r22__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \r22__ren + wire input 15 \r22__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r2__data_o + wire width 4 output 12 \r2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r2__ren + wire input 13 \r2__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src12__data_o + wire width 4 output 3 \src12__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src12__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src12__ren + wire input 2 \src12__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src22__data_o + wire width 4 output 5 \src22__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src22__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src22__ren + wire input 4 \src22__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 9 \src32__data_o + wire width 4 output 7 \src32__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src32__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \src32__ren + wire input 6 \src32__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 18 \w2__data_i + wire width 4 input 16 \w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 19 \w2__wen + wire input 17 \w2__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -369162,257 +335238,232 @@ module \reg_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179590$11117 + cell $not $not$libresoc.v:180131$11015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:179590$11117_Y + connect \Y $not$libresoc.v:180131$11015_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179591$11118 + cell $not $not$libresoc.v:180132$11016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:179591$11118_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179592$11119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$16 - connect \Y $not$libresoc.v:179592$11119_Y + connect \Y $not$libresoc.v:180132$11016_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179593$11120 + cell $not $not$libresoc.v:180133$11017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:179593$11120_Y + connect \Y $not$libresoc.v:180133$11017_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179594$11121 + cell $not $not$libresoc.v:180134$11018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:179594$11121_Y + connect \Y $not$libresoc.v:180134$11018_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179595$11122 + cell $not $not$libresoc.v:180135$11019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:179595$11122_Y + connect \Y $not$libresoc.v:180135$11019_Y end - attribute \src "libresoc.v:179503.7-179503.20" - process $proc$libresoc.v:179503$11215 + attribute \src "libresoc.v:180055.7-180055.20" + process $proc$libresoc.v:180055$11097 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179522.13-179522.36" - process $proc$libresoc.v:179522$11216 - assign { } { } - assign $1\cr_pred2__data_o[3:0] 4'0000 - sync always - sync init - update \cr_pred2__data_o $1\cr_pred2__data_o[3:0] - end - attribute \src "libresoc.v:179537.13-179537.31" - process $proc$libresoc.v:179537$11217 + attribute \src "libresoc.v:180080.13-180080.31" + process $proc$libresoc.v:180080$11098 assign { } { } assign $1\r22__data_o[3:0] 4'0000 sync always sync init update \r22__data_o $1\r22__data_o[3:0] end - attribute \src "libresoc.v:179544.13-179544.30" - process $proc$libresoc.v:179544$11218 + attribute \src "libresoc.v:180087.13-180087.30" + process $proc$libresoc.v:180087$11099 assign { } { } assign $1\r2__data_o[3:0] 4'0000 sync always sync init update \r2__data_o $1\r2__data_o[3:0] end - attribute \src "libresoc.v:179550.13-179550.25" - process $proc$libresoc.v:179550$11219 + attribute \src "libresoc.v:180093.13-180093.25" + process $proc$libresoc.v:180093$11100 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:179555.13-179555.33" - process $proc$libresoc.v:179555$11220 + attribute \src "libresoc.v:180098.13-180098.33" + process $proc$libresoc.v:180098$11101 assign { } { } assign $1\src12__data_o[3:0] 4'0000 sync always sync init update \src12__data_o $1\src12__data_o[3:0] end - attribute \src "libresoc.v:179562.13-179562.33" - process $proc$libresoc.v:179562$11221 + attribute \src "libresoc.v:180105.13-180105.33" + process $proc$libresoc.v:180105$11102 assign { } { } assign $1\src22__data_o[3:0] 4'0000 sync always sync init update \src22__data_o $1\src22__data_o[3:0] end - attribute \src "libresoc.v:179569.13-179569.33" - process $proc$libresoc.v:179569$11222 + attribute \src "libresoc.v:180112.13-180112.33" + process $proc$libresoc.v:180112$11103 assign { } { } assign $1\src32__data_o[3:0] 4'0000 sync always sync init update \src32__data_o $1\src32__data_o[3:0] end - attribute \src "libresoc.v:179596.3-179597.25" - process $proc$libresoc.v:179596$11123 + attribute \src "libresoc.v:180136.3-180137.25" + process $proc$libresoc.v:180136$11020 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:179598.3-179599.39" - process $proc$libresoc.v:179598$11124 + attribute \src "libresoc.v:180138.3-180139.39" + process $proc$libresoc.v:180138$11021 assign { } { } assign $0\r22__data_o[3:0] \r22__data_o$next sync posedge \coresync_clk update \r22__data_o $0\r22__data_o[3:0] end - attribute \src "libresoc.v:179600.3-179601.37" - process $proc$libresoc.v:179600$11125 + attribute \src "libresoc.v:180140.3-180141.37" + process $proc$libresoc.v:180140$11022 assign { } { } assign $0\r2__data_o[3:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[3:0] end - attribute \src "libresoc.v:179602.3-179603.43" - process $proc$libresoc.v:179602$11126 + attribute \src "libresoc.v:180142.3-180143.43" + process $proc$libresoc.v:180142$11023 assign { } { } assign $0\src32__data_o[3:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[3:0] end - attribute \src "libresoc.v:179604.3-179605.43" - process $proc$libresoc.v:179604$11127 + attribute \src "libresoc.v:180144.3-180145.43" + process $proc$libresoc.v:180144$11024 assign { } { } assign $0\src22__data_o[3:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[3:0] end - attribute \src "libresoc.v:179606.3-179607.43" - process $proc$libresoc.v:179606$11128 + attribute \src "libresoc.v:180146.3-180147.43" + process $proc$libresoc.v:180146$11025 assign { } { } assign $0\src12__data_o[3:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[3:0] end - attribute \src "libresoc.v:179608.3-179609.49" - process $proc$libresoc.v:179608$11129 - assign { } { } - assign $0\cr_pred2__data_o[3:0] \cr_pred2__data_o$next - sync posedge \coresync_clk - update \cr_pred2__data_o $0\cr_pred2__data_o[3:0] - end - attribute \src "libresoc.v:179610.3-179649.6" - process $proc$libresoc.v:179610$11130 + attribute \src "libresoc.v:180148.3-180187.6" + process $proc$libresoc.v:180148$11026 assign { } { } assign { } { } assign { } { } - assign $0\cr_pred2__data_o$next[3:0]$11131 $6\cr_pred2__data_o$next[3:0]$11137 - attribute \src "libresoc.v:179611.5-179611.29" + assign $0\src12__data_o$next[3:0]$11027 $6\src12__data_o$next[3:0]$11033 + attribute \src "libresoc.v:180149.5-180149.29" switch \initial - attribute \src "libresoc.v:179611.9-179611.17" + attribute \src "libresoc.v:180149.9-180149.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred2__ren + switch \src12__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\cr_pred2__data_o$next[3:0]$11132 $5\cr_pred2__data_o$next[3:0]$11136 + assign $1\src12__data_o$next[3:0]$11028 $5\src12__data_o$next[3:0]$11032 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred2__data_o$next[3:0]$11133 \dest12__data_i + assign $2\src12__data_o$next[3:0]$11029 \dest12__data_i case - assign $2\cr_pred2__data_o$next[3:0]$11133 4'0000 + assign $2\src12__data_o$next[3:0]$11029 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred2__data_o$next[3:0]$11134 \dest22__data_i + assign $3\src12__data_o$next[3:0]$11030 \dest22__data_i case - assign $3\cr_pred2__data_o$next[3:0]$11134 $2\cr_pred2__data_o$next[3:0]$11133 + assign $3\src12__data_o$next[3:0]$11030 $2\src12__data_o$next[3:0]$11029 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred2__data_o$next[3:0]$11135 \w2__data_i + assign $4\src12__data_o$next[3:0]$11031 \w2__data_i case - assign $4\cr_pred2__data_o$next[3:0]$11135 $3\cr_pred2__data_o$next[3:0]$11134 + assign $4\src12__data_o$next[3:0]$11031 $3\src12__data_o$next[3:0]$11030 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred2__data_o$next[3:0]$11136 \reg + assign $5\src12__data_o$next[3:0]$11032 \reg case - assign $5\cr_pred2__data_o$next[3:0]$11136 $4\cr_pred2__data_o$next[3:0]$11135 + assign $5\src12__data_o$next[3:0]$11032 $4\src12__data_o$next[3:0]$11031 end case - assign $1\cr_pred2__data_o$next[3:0]$11132 4'0000 + assign $1\src12__data_o$next[3:0]$11028 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred2__data_o$next[3:0]$11137 4'0000 + assign $6\src12__data_o$next[3:0]$11033 4'0000 case - assign $6\cr_pred2__data_o$next[3:0]$11137 $1\cr_pred2__data_o$next[3:0]$11132 + assign $6\src12__data_o$next[3:0]$11033 $1\src12__data_o$next[3:0]$11028 end sync always - update \cr_pred2__data_o$next $0\cr_pred2__data_o$next[3:0]$11131 + update \src12__data_o$next $0\src12__data_o$next[3:0]$11027 end - attribute \src "libresoc.v:179650.3-179679.6" - process $proc$libresoc.v:179650$11138 + attribute \src "libresoc.v:180188.3-180217.6" + process $proc$libresoc.v:180188$11034 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:179651.5-179651.29" + attribute \src "libresoc.v:180189.5-180189.29" switch \initial - attribute \src "libresoc.v:179651.9-179651.17" + attribute \src "libresoc.v:180189.9-180189.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred2__ren + switch \src12__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -369453,142 +335504,17 @@ module \reg_2 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:179680.3-179719.6" - process $proc$libresoc.v:179680$11139 - assign { } { } - assign { } { } - assign { } { } - assign $0\r22__data_o$next[3:0]$11140 $6\r22__data_o$next[3:0]$11146 - attribute \src "libresoc.v:179681.5-179681.29" - switch \initial - attribute \src "libresoc.v:179681.9-179681.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r22__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r22__data_o$next[3:0]$11141 $5\r22__data_o$next[3:0]$11145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r22__data_o$next[3:0]$11142 \dest12__data_i - case - assign $2\r22__data_o$next[3:0]$11142 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r22__data_o$next[3:0]$11143 \dest22__data_i - case - assign $3\r22__data_o$next[3:0]$11143 $2\r22__data_o$next[3:0]$11142 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r22__data_o$next[3:0]$11144 \w2__data_i - case - assign $4\r22__data_o$next[3:0]$11144 $3\r22__data_o$next[3:0]$11143 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r22__data_o$next[3:0]$11145 \reg - case - assign $5\r22__data_o$next[3:0]$11145 $4\r22__data_o$next[3:0]$11144 - end - case - assign $1\r22__data_o$next[3:0]$11141 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r22__data_o$next[3:0]$11146 4'0000 - case - assign $6\r22__data_o$next[3:0]$11146 $1\r22__data_o$next[3:0]$11141 - end - sync always - update \r22__data_o$next $0\r22__data_o$next[3:0]$11140 - end - attribute \src "libresoc.v:179720.3-179749.6" - process $proc$libresoc.v:179720$11147 - assign { } { } - assign { } { } - assign $0\wr_detect$16[0:0]$11148 $1\wr_detect$16[0:0]$11149 - attribute \src "libresoc.v:179721.5-179721.29" - switch \initial - attribute \src "libresoc.v:179721.9-179721.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r22__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$16[0:0]$11149 $4\wr_detect$16[0:0]$11152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$16[0:0]$11150 1'1 - case - assign $2\wr_detect$16[0:0]$11150 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$16[0:0]$11151 1'1 - case - assign $3\wr_detect$16[0:0]$11151 $2\wr_detect$16[0:0]$11150 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$16[0:0]$11152 1'1 - case - assign $4\wr_detect$16[0:0]$11152 $3\wr_detect$16[0:0]$11151 - end - case - assign $1\wr_detect$16[0:0]$11149 1'0 - end - sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$11148 - end - attribute \src "libresoc.v:179750.3-179776.6" - process $proc$libresoc.v:179750$11153 + attribute \src "libresoc.v:180218.3-180244.6" + process $proc$libresoc.v:180218$11035 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11154 $4\reg$next[3:0]$11158 - attribute \src "libresoc.v:179751.5-179751.29" + assign $0\reg$next[3:0]$11036 $4\reg$next[3:0]$11040 + attribute \src "libresoc.v:180219.5-180219.29" switch \initial - attribute \src "libresoc.v:179751.9-179751.17" + attribute \src "libresoc.v:180219.9-180219.17" case 1'1 case end @@ -369597,174 +335523,49 @@ module \reg_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11155 \dest12__data_i + assign $1\reg$next[3:0]$11037 \dest12__data_i case - assign $1\reg$next[3:0]$11155 \reg + assign $1\reg$next[3:0]$11037 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11156 \dest22__data_i + assign $2\reg$next[3:0]$11038 \dest22__data_i case - assign $2\reg$next[3:0]$11156 $1\reg$next[3:0]$11155 + assign $2\reg$next[3:0]$11038 $1\reg$next[3:0]$11037 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11157 \w2__data_i - case - assign $3\reg$next[3:0]$11157 $2\reg$next[3:0]$11156 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[3:0]$11158 4'0000 - case - assign $4\reg$next[3:0]$11158 $3\reg$next[3:0]$11157 - end - sync always - update \reg$next $0\reg$next[3:0]$11154 - end - attribute \src "libresoc.v:179777.3-179816.6" - process $proc$libresoc.v:179777$11159 - assign { } { } - assign { } { } - assign { } { } - assign $0\src12__data_o$next[3:0]$11160 $6\src12__data_o$next[3:0]$11166 - attribute \src "libresoc.v:179778.5-179778.29" - switch \initial - attribute \src "libresoc.v:179778.9-179778.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src12__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src12__data_o$next[3:0]$11161 $5\src12__data_o$next[3:0]$11165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src12__data_o$next[3:0]$11162 \dest12__data_i - case - assign $2\src12__data_o$next[3:0]$11162 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src12__data_o$next[3:0]$11163 \dest22__data_i - case - assign $3\src12__data_o$next[3:0]$11163 $2\src12__data_o$next[3:0]$11162 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src12__data_o$next[3:0]$11164 \w2__data_i - case - assign $4\src12__data_o$next[3:0]$11164 $3\src12__data_o$next[3:0]$11163 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src12__data_o$next[3:0]$11165 \reg - case - assign $5\src12__data_o$next[3:0]$11165 $4\src12__data_o$next[3:0]$11164 - end + assign $3\reg$next[3:0]$11039 \w2__data_i case - assign $1\src12__data_o$next[3:0]$11161 4'0000 + assign $3\reg$next[3:0]$11039 $2\reg$next[3:0]$11038 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[3:0]$11166 4'0000 - case - assign $6\src12__data_o$next[3:0]$11166 $1\src12__data_o$next[3:0]$11161 - end - sync always - update \src12__data_o$next $0\src12__data_o$next[3:0]$11160 - end - attribute \src "libresoc.v:179817.3-179846.6" - process $proc$libresoc.v:179817$11167 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$11168 $1\wr_detect$4[0:0]$11169 - attribute \src "libresoc.v:179818.5-179818.29" - switch \initial - attribute \src "libresoc.v:179818.9-179818.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src12__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$11169 $4\wr_detect$4[0:0]$11172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$11170 1'1 - case - assign $2\wr_detect$4[0:0]$11170 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$11171 1'1 - case - assign $3\wr_detect$4[0:0]$11171 $2\wr_detect$4[0:0]$11170 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$11172 1'1 - case - assign $4\wr_detect$4[0:0]$11172 $3\wr_detect$4[0:0]$11171 - end + assign $4\reg$next[3:0]$11040 4'0000 case - assign $1\wr_detect$4[0:0]$11169 1'0 + assign $4\reg$next[3:0]$11040 $3\reg$next[3:0]$11039 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11168 + update \reg$next $0\reg$next[3:0]$11036 end - attribute \src "libresoc.v:179847.3-179886.6" - process $proc$libresoc.v:179847$11173 + attribute \src "libresoc.v:180245.3-180284.6" + process $proc$libresoc.v:180245$11041 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[3:0]$11174 $6\src22__data_o$next[3:0]$11180 - attribute \src "libresoc.v:179848.5-179848.29" + assign $0\src22__data_o$next[3:0]$11042 $6\src22__data_o$next[3:0]$11048 + attribute \src "libresoc.v:180246.5-180246.29" switch \initial - attribute \src "libresoc.v:179848.9-179848.17" + attribute \src "libresoc.v:180246.9-180246.17" case 1'1 case end @@ -369776,66 +335577,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[3:0]$11175 $5\src22__data_o$next[3:0]$11179 + assign $1\src22__data_o$next[3:0]$11043 $5\src22__data_o$next[3:0]$11047 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[3:0]$11176 \dest12__data_i + assign $2\src22__data_o$next[3:0]$11044 \dest12__data_i case - assign $2\src22__data_o$next[3:0]$11176 4'0000 + assign $2\src22__data_o$next[3:0]$11044 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[3:0]$11177 \dest22__data_i + assign $3\src22__data_o$next[3:0]$11045 \dest22__data_i case - assign $3\src22__data_o$next[3:0]$11177 $2\src22__data_o$next[3:0]$11176 + assign $3\src22__data_o$next[3:0]$11045 $2\src22__data_o$next[3:0]$11044 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[3:0]$11178 \w2__data_i + assign $4\src22__data_o$next[3:0]$11046 \w2__data_i case - assign $4\src22__data_o$next[3:0]$11178 $3\src22__data_o$next[3:0]$11177 + assign $4\src22__data_o$next[3:0]$11046 $3\src22__data_o$next[3:0]$11045 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 + switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[3:0]$11179 \reg + assign $5\src22__data_o$next[3:0]$11047 \reg case - assign $5\src22__data_o$next[3:0]$11179 $4\src22__data_o$next[3:0]$11178 + assign $5\src22__data_o$next[3:0]$11047 $4\src22__data_o$next[3:0]$11046 end case - assign $1\src22__data_o$next[3:0]$11175 4'0000 + assign $1\src22__data_o$next[3:0]$11043 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[3:0]$11180 4'0000 + assign $6\src22__data_o$next[3:0]$11048 4'0000 case - assign $6\src22__data_o$next[3:0]$11180 $1\src22__data_o$next[3:0]$11175 + assign $6\src22__data_o$next[3:0]$11048 $1\src22__data_o$next[3:0]$11043 end sync always - update \src22__data_o$next $0\src22__data_o$next[3:0]$11174 + update \src22__data_o$next $0\src22__data_o$next[3:0]$11042 end - attribute \src "libresoc.v:179887.3-179916.6" - process $proc$libresoc.v:179887$11181 + attribute \src "libresoc.v:180285.3-180314.6" + process $proc$libresoc.v:180285$11049 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11182 $1\wr_detect$7[0:0]$11183 - attribute \src "libresoc.v:179888.5-179888.29" + assign $0\wr_detect$4[0:0]$11050 $1\wr_detect$4[0:0]$11051 + attribute \src "libresoc.v:180286.5-180286.29" switch \initial - attribute \src "libresoc.v:179888.9-179888.17" + attribute \src "libresoc.v:180286.9-180286.17" case 1'1 case end @@ -369847,49 +335648,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11183 $4\wr_detect$7[0:0]$11186 + assign $1\wr_detect$4[0:0]$11051 $4\wr_detect$4[0:0]$11054 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11184 1'1 + assign $2\wr_detect$4[0:0]$11052 1'1 case - assign $2\wr_detect$7[0:0]$11184 1'0 + assign $2\wr_detect$4[0:0]$11052 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11185 1'1 + assign $3\wr_detect$4[0:0]$11053 1'1 case - assign $3\wr_detect$7[0:0]$11185 $2\wr_detect$7[0:0]$11184 + assign $3\wr_detect$4[0:0]$11053 $2\wr_detect$4[0:0]$11052 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11186 1'1 + assign $4\wr_detect$4[0:0]$11054 1'1 case - assign $4\wr_detect$7[0:0]$11186 $3\wr_detect$7[0:0]$11185 + assign $4\wr_detect$4[0:0]$11054 $3\wr_detect$4[0:0]$11053 end case - assign $1\wr_detect$7[0:0]$11183 1'0 + assign $1\wr_detect$4[0:0]$11051 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11182 + update \wr_detect$4 $0\wr_detect$4[0:0]$11050 end - attribute \src "libresoc.v:179917.3-179956.6" - process $proc$libresoc.v:179917$11187 + attribute \src "libresoc.v:180315.3-180354.6" + process $proc$libresoc.v:180315$11055 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[3:0]$11188 $6\src32__data_o$next[3:0]$11194 - attribute \src "libresoc.v:179918.5-179918.29" + assign $0\src32__data_o$next[3:0]$11056 $6\src32__data_o$next[3:0]$11062 + attribute \src "libresoc.v:180316.5-180316.29" switch \initial - attribute \src "libresoc.v:179918.9-179918.17" + attribute \src "libresoc.v:180316.9-180316.17" case 1'1 case end @@ -369901,66 +335702,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[3:0]$11189 $5\src32__data_o$next[3:0]$11193 + assign $1\src32__data_o$next[3:0]$11057 $5\src32__data_o$next[3:0]$11061 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[3:0]$11190 \dest12__data_i + assign $2\src32__data_o$next[3:0]$11058 \dest12__data_i case - assign $2\src32__data_o$next[3:0]$11190 4'0000 + assign $2\src32__data_o$next[3:0]$11058 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[3:0]$11191 \dest22__data_i + assign $3\src32__data_o$next[3:0]$11059 \dest22__data_i case - assign $3\src32__data_o$next[3:0]$11191 $2\src32__data_o$next[3:0]$11190 + assign $3\src32__data_o$next[3:0]$11059 $2\src32__data_o$next[3:0]$11058 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[3:0]$11192 \w2__data_i + assign $4\src32__data_o$next[3:0]$11060 \w2__data_i case - assign $4\src32__data_o$next[3:0]$11192 $3\src32__data_o$next[3:0]$11191 + assign $4\src32__data_o$next[3:0]$11060 $3\src32__data_o$next[3:0]$11059 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 + switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[3:0]$11193 \reg + assign $5\src32__data_o$next[3:0]$11061 \reg case - assign $5\src32__data_o$next[3:0]$11193 $4\src32__data_o$next[3:0]$11192 + assign $5\src32__data_o$next[3:0]$11061 $4\src32__data_o$next[3:0]$11060 end case - assign $1\src32__data_o$next[3:0]$11189 4'0000 + assign $1\src32__data_o$next[3:0]$11057 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[3:0]$11194 4'0000 + assign $6\src32__data_o$next[3:0]$11062 4'0000 case - assign $6\src32__data_o$next[3:0]$11194 $1\src32__data_o$next[3:0]$11189 + assign $6\src32__data_o$next[3:0]$11062 $1\src32__data_o$next[3:0]$11057 end sync always - update \src32__data_o$next $0\src32__data_o$next[3:0]$11188 + update \src32__data_o$next $0\src32__data_o$next[3:0]$11056 end - attribute \src "libresoc.v:179957.3-179986.6" - process $proc$libresoc.v:179957$11195 + attribute \src "libresoc.v:180355.3-180384.6" + process $proc$libresoc.v:180355$11063 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11196 $1\wr_detect$10[0:0]$11197 - attribute \src "libresoc.v:179958.5-179958.29" + assign $0\wr_detect$7[0:0]$11064 $1\wr_detect$7[0:0]$11065 + attribute \src "libresoc.v:180356.5-180356.29" switch \initial - attribute \src "libresoc.v:179958.9-179958.17" + attribute \src "libresoc.v:180356.9-180356.17" case 1'1 case end @@ -369972,49 +335773,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11197 $4\wr_detect$10[0:0]$11200 + assign $1\wr_detect$7[0:0]$11065 $4\wr_detect$7[0:0]$11068 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11198 1'1 + assign $2\wr_detect$7[0:0]$11066 1'1 case - assign $2\wr_detect$10[0:0]$11198 1'0 + assign $2\wr_detect$7[0:0]$11066 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11199 1'1 + assign $3\wr_detect$7[0:0]$11067 1'1 case - assign $3\wr_detect$10[0:0]$11199 $2\wr_detect$10[0:0]$11198 + assign $3\wr_detect$7[0:0]$11067 $2\wr_detect$7[0:0]$11066 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11200 1'1 + assign $4\wr_detect$7[0:0]$11068 1'1 case - assign $4\wr_detect$10[0:0]$11200 $3\wr_detect$10[0:0]$11199 + assign $4\wr_detect$7[0:0]$11068 $3\wr_detect$7[0:0]$11067 end case - assign $1\wr_detect$10[0:0]$11197 1'0 + assign $1\wr_detect$7[0:0]$11065 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11196 + update \wr_detect$7 $0\wr_detect$7[0:0]$11064 end - attribute \src "libresoc.v:179987.3-180026.6" - process $proc$libresoc.v:179987$11201 + attribute \src "libresoc.v:180385.3-180424.6" + process $proc$libresoc.v:180385$11069 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[3:0]$11202 $6\r2__data_o$next[3:0]$11208 - attribute \src "libresoc.v:179988.5-179988.29" + assign $0\r2__data_o$next[3:0]$11070 $6\r2__data_o$next[3:0]$11076 + attribute \src "libresoc.v:180386.5-180386.29" switch \initial - attribute \src "libresoc.v:179988.9-179988.17" + attribute \src "libresoc.v:180386.9-180386.17" case 1'1 case end @@ -370026,66 +335827,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[3:0]$11203 $5\r2__data_o$next[3:0]$11207 + assign $1\r2__data_o$next[3:0]$11071 $5\r2__data_o$next[3:0]$11075 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[3:0]$11204 \dest12__data_i + assign $2\r2__data_o$next[3:0]$11072 \dest12__data_i case - assign $2\r2__data_o$next[3:0]$11204 4'0000 + assign $2\r2__data_o$next[3:0]$11072 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[3:0]$11205 \dest22__data_i + assign $3\r2__data_o$next[3:0]$11073 \dest22__data_i case - assign $3\r2__data_o$next[3:0]$11205 $2\r2__data_o$next[3:0]$11204 + assign $3\r2__data_o$next[3:0]$11073 $2\r2__data_o$next[3:0]$11072 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[3:0]$11206 \w2__data_i + assign $4\r2__data_o$next[3:0]$11074 \w2__data_i case - assign $4\r2__data_o$next[3:0]$11206 $3\r2__data_o$next[3:0]$11205 + assign $4\r2__data_o$next[3:0]$11074 $3\r2__data_o$next[3:0]$11073 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 + switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[3:0]$11207 \reg + assign $5\r2__data_o$next[3:0]$11075 \reg case - assign $5\r2__data_o$next[3:0]$11207 $4\r2__data_o$next[3:0]$11206 + assign $5\r2__data_o$next[3:0]$11075 $4\r2__data_o$next[3:0]$11074 end case - assign $1\r2__data_o$next[3:0]$11203 4'0000 + assign $1\r2__data_o$next[3:0]$11071 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[3:0]$11208 4'0000 + assign $6\r2__data_o$next[3:0]$11076 4'0000 case - assign $6\r2__data_o$next[3:0]$11208 $1\r2__data_o$next[3:0]$11203 + assign $6\r2__data_o$next[3:0]$11076 $1\r2__data_o$next[3:0]$11071 end sync always - update \r2__data_o$next $0\r2__data_o$next[3:0]$11202 + update \r2__data_o$next $0\r2__data_o$next[3:0]$11070 end - attribute \src "libresoc.v:180027.3-180056.6" - process $proc$libresoc.v:180027$11209 + attribute \src "libresoc.v:180425.3-180454.6" + process $proc$libresoc.v:180425$11077 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11210 $1\wr_detect$13[0:0]$11211 - attribute \src "libresoc.v:180028.5-180028.29" + assign $0\wr_detect$10[0:0]$11078 $1\wr_detect$10[0:0]$11079 + attribute \src "libresoc.v:180426.5-180426.29" switch \initial - attribute \src "libresoc.v:180028.9-180028.17" + attribute \src "libresoc.v:180426.9-180426.17" case 1'1 case end @@ -370097,206 +335898,330 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11211 $4\wr_detect$13[0:0]$11214 + assign $1\wr_detect$10[0:0]$11079 $4\wr_detect$10[0:0]$11082 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11212 1'1 + assign $2\wr_detect$10[0:0]$11080 1'1 case - assign $2\wr_detect$13[0:0]$11212 1'0 + assign $2\wr_detect$10[0:0]$11080 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11213 1'1 + assign $3\wr_detect$10[0:0]$11081 1'1 case - assign $3\wr_detect$13[0:0]$11213 $2\wr_detect$13[0:0]$11212 + assign $3\wr_detect$10[0:0]$11081 $2\wr_detect$10[0:0]$11080 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11214 1'1 + assign $4\wr_detect$10[0:0]$11082 1'1 case - assign $4\wr_detect$13[0:0]$11214 $3\wr_detect$13[0:0]$11213 + assign $4\wr_detect$10[0:0]$11082 $3\wr_detect$10[0:0]$11081 end case - assign $1\wr_detect$13[0:0]$11211 1'0 + assign $1\wr_detect$10[0:0]$11079 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11210 + update \wr_detect$10 $0\wr_detect$10[0:0]$11078 end - connect \$9 $not$libresoc.v:179590$11117_Y - connect \$12 $not$libresoc.v:179591$11118_Y - connect \$15 $not$libresoc.v:179592$11119_Y - connect \$1 $not$libresoc.v:179593$11120_Y - connect \$3 $not$libresoc.v:179594$11121_Y - connect \$6 $not$libresoc.v:179595$11122_Y + attribute \src "libresoc.v:180455.3-180494.6" + process $proc$libresoc.v:180455$11083 + assign { } { } + assign { } { } + assign { } { } + assign $0\r22__data_o$next[3:0]$11084 $6\r22__data_o$next[3:0]$11090 + attribute \src "libresoc.v:180456.5-180456.29" + switch \initial + attribute \src "libresoc.v:180456.9-180456.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r22__data_o$next[3:0]$11085 $5\r22__data_o$next[3:0]$11089 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r22__data_o$next[3:0]$11086 \dest12__data_i + case + assign $2\r22__data_o$next[3:0]$11086 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r22__data_o$next[3:0]$11087 \dest22__data_i + case + assign $3\r22__data_o$next[3:0]$11087 $2\r22__data_o$next[3:0]$11086 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r22__data_o$next[3:0]$11088 \w2__data_i + case + assign $4\r22__data_o$next[3:0]$11088 $3\r22__data_o$next[3:0]$11087 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r22__data_o$next[3:0]$11089 \reg + case + assign $5\r22__data_o$next[3:0]$11089 $4\r22__data_o$next[3:0]$11088 + end + case + assign $1\r22__data_o$next[3:0]$11085 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r22__data_o$next[3:0]$11090 4'0000 + case + assign $6\r22__data_o$next[3:0]$11090 $1\r22__data_o$next[3:0]$11085 + end + sync always + update \r22__data_o$next $0\r22__data_o$next[3:0]$11084 + end + attribute \src "libresoc.v:180495.3-180524.6" + process $proc$libresoc.v:180495$11091 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11092 $1\wr_detect$13[0:0]$11093 + attribute \src "libresoc.v:180496.5-180496.29" + switch \initial + attribute \src "libresoc.v:180496.9-180496.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11093 $4\wr_detect$13[0:0]$11096 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11094 1'1 + case + assign $2\wr_detect$13[0:0]$11094 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11095 1'1 + case + assign $3\wr_detect$13[0:0]$11095 $2\wr_detect$13[0:0]$11094 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11096 1'1 + case + assign $4\wr_detect$13[0:0]$11096 $3\wr_detect$13[0:0]$11095 + end + case + assign $1\wr_detect$13[0:0]$11093 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11092 + end + connect \$9 $not$libresoc.v:180131$11015_Y + connect \$12 $not$libresoc.v:180132$11016_Y + connect \$1 $not$libresoc.v:180133$11017_Y + connect \$3 $not$libresoc.v:180134$11018_Y + connect \$6 $not$libresoc.v:180135$11019_Y end -attribute \src "libresoc.v:180061.1-180506.10" +attribute \src "libresoc.v:180529.1-180974.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" attribute \generator "nMigen" module \reg_2$134 - attribute \src "libresoc.v:180062.7-180062.20" + attribute \src "libresoc.v:180530.7-180530.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180391.3-180436.6" - wire width 2 $0\r2__data_o$next[1:0]$11275 - attribute \src "libresoc.v:180137.3-180138.37" + attribute \src "libresoc.v:180859.3-180904.6" + wire width 2 $0\r2__data_o$next[1:0]$11156 + attribute \src "libresoc.v:180605.3-180606.37" wire width 2 $0\r2__data_o[1:0] - attribute \src "libresoc.v:180473.3-180505.6" - wire width 2 $0\reg$next[1:0]$11291 - attribute \src "libresoc.v:180135.3-180136.25" + attribute \src "libresoc.v:180941.3-180973.6" + wire width 2 $0\reg$next[1:0]$11172 + attribute \src "libresoc.v:180603.3-180604.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:180145.3-180190.6" - wire width 2 $0\src12__data_o$next[1:0]$11233 - attribute \src "libresoc.v:180143.3-180144.43" + attribute \src "libresoc.v:180613.3-180658.6" + wire width 2 $0\src12__data_o$next[1:0]$11114 + attribute \src "libresoc.v:180611.3-180612.43" wire width 2 $0\src12__data_o[1:0] - attribute \src "libresoc.v:180227.3-180272.6" - wire width 2 $0\src22__data_o$next[1:0]$11243 - attribute \src "libresoc.v:180141.3-180142.43" + attribute \src "libresoc.v:180695.3-180740.6" + wire width 2 $0\src22__data_o$next[1:0]$11124 + attribute \src "libresoc.v:180609.3-180610.43" wire width 2 $0\src22__data_o[1:0] - attribute \src "libresoc.v:180309.3-180354.6" - wire width 2 $0\src32__data_o$next[1:0]$11259 - attribute \src "libresoc.v:180139.3-180140.43" + attribute \src "libresoc.v:180777.3-180822.6" + wire width 2 $0\src32__data_o$next[1:0]$11140 + attribute \src "libresoc.v:180607.3-180608.43" wire width 2 $0\src32__data_o[1:0] - attribute \src "libresoc.v:180437.3-180472.6" - wire $0\wr_detect$10[0:0]$11284 - attribute \src "libresoc.v:180273.3-180308.6" - wire $0\wr_detect$4[0:0]$11252 - attribute \src "libresoc.v:180355.3-180390.6" - wire $0\wr_detect$7[0:0]$11268 - attribute \src "libresoc.v:180191.3-180226.6" + attribute \src "libresoc.v:180905.3-180940.6" + wire $0\wr_detect$10[0:0]$11165 + attribute \src "libresoc.v:180741.3-180776.6" + wire $0\wr_detect$4[0:0]$11133 + attribute \src "libresoc.v:180823.3-180858.6" + wire $0\wr_detect$7[0:0]$11149 + attribute \src "libresoc.v:180659.3-180694.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:180391.3-180436.6" - wire width 2 $1\r2__data_o$next[1:0]$11276 - attribute \src "libresoc.v:180089.13-180089.30" + attribute \src "libresoc.v:180859.3-180904.6" + wire width 2 $1\r2__data_o$next[1:0]$11157 + attribute \src "libresoc.v:180557.13-180557.30" wire width 2 $1\r2__data_o[1:0] - attribute \src "libresoc.v:180473.3-180505.6" - wire width 2 $1\reg$next[1:0]$11292 - attribute \src "libresoc.v:180095.13-180095.25" + attribute \src "libresoc.v:180941.3-180973.6" + wire width 2 $1\reg$next[1:0]$11173 + attribute \src "libresoc.v:180563.13-180563.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:180145.3-180190.6" - wire width 2 $1\src12__data_o$next[1:0]$11234 - attribute \src "libresoc.v:180100.13-180100.33" + attribute \src "libresoc.v:180613.3-180658.6" + wire width 2 $1\src12__data_o$next[1:0]$11115 + attribute \src "libresoc.v:180568.13-180568.33" wire width 2 $1\src12__data_o[1:0] - attribute \src "libresoc.v:180227.3-180272.6" - wire width 2 $1\src22__data_o$next[1:0]$11244 - attribute \src "libresoc.v:180107.13-180107.33" + attribute \src "libresoc.v:180695.3-180740.6" + wire width 2 $1\src22__data_o$next[1:0]$11125 + attribute \src "libresoc.v:180575.13-180575.33" wire width 2 $1\src22__data_o[1:0] - attribute \src "libresoc.v:180309.3-180354.6" - wire width 2 $1\src32__data_o$next[1:0]$11260 - attribute \src "libresoc.v:180114.13-180114.33" + attribute \src "libresoc.v:180777.3-180822.6" + wire width 2 $1\src32__data_o$next[1:0]$11141 + attribute \src "libresoc.v:180582.13-180582.33" wire width 2 $1\src32__data_o[1:0] - attribute \src "libresoc.v:180437.3-180472.6" - wire $1\wr_detect$10[0:0]$11285 - attribute \src "libresoc.v:180273.3-180308.6" - wire $1\wr_detect$4[0:0]$11253 - attribute \src "libresoc.v:180355.3-180390.6" - wire $1\wr_detect$7[0:0]$11269 - attribute \src "libresoc.v:180191.3-180226.6" + attribute \src "libresoc.v:180905.3-180940.6" + wire $1\wr_detect$10[0:0]$11166 + attribute \src "libresoc.v:180741.3-180776.6" + wire $1\wr_detect$4[0:0]$11134 + attribute \src "libresoc.v:180823.3-180858.6" + wire $1\wr_detect$7[0:0]$11150 + attribute \src "libresoc.v:180659.3-180694.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:180391.3-180436.6" - wire width 2 $2\r2__data_o$next[1:0]$11277 - attribute \src "libresoc.v:180473.3-180505.6" - wire width 2 $2\reg$next[1:0]$11293 - attribute \src "libresoc.v:180145.3-180190.6" - wire width 2 $2\src12__data_o$next[1:0]$11235 - attribute \src "libresoc.v:180227.3-180272.6" - wire width 2 $2\src22__data_o$next[1:0]$11245 - attribute \src "libresoc.v:180309.3-180354.6" - wire width 2 $2\src32__data_o$next[1:0]$11261 - attribute \src "libresoc.v:180437.3-180472.6" - wire $2\wr_detect$10[0:0]$11286 - attribute \src "libresoc.v:180273.3-180308.6" - wire $2\wr_detect$4[0:0]$11254 - attribute \src "libresoc.v:180355.3-180390.6" - wire $2\wr_detect$7[0:0]$11270 - attribute \src "libresoc.v:180191.3-180226.6" + attribute \src "libresoc.v:180859.3-180904.6" + wire width 2 $2\r2__data_o$next[1:0]$11158 + attribute \src "libresoc.v:180941.3-180973.6" + wire width 2 $2\reg$next[1:0]$11174 + attribute \src "libresoc.v:180613.3-180658.6" + wire width 2 $2\src12__data_o$next[1:0]$11116 + attribute \src "libresoc.v:180695.3-180740.6" + wire width 2 $2\src22__data_o$next[1:0]$11126 + attribute \src "libresoc.v:180777.3-180822.6" + wire width 2 $2\src32__data_o$next[1:0]$11142 + attribute \src "libresoc.v:180905.3-180940.6" + wire $2\wr_detect$10[0:0]$11167 + attribute \src "libresoc.v:180741.3-180776.6" + wire $2\wr_detect$4[0:0]$11135 + attribute \src "libresoc.v:180823.3-180858.6" + wire $2\wr_detect$7[0:0]$11151 + attribute \src "libresoc.v:180659.3-180694.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:180391.3-180436.6" - wire width 2 $3\r2__data_o$next[1:0]$11278 - attribute \src "libresoc.v:180473.3-180505.6" - wire width 2 $3\reg$next[1:0]$11294 - attribute \src "libresoc.v:180145.3-180190.6" - wire width 2 $3\src12__data_o$next[1:0]$11236 - attribute \src "libresoc.v:180227.3-180272.6" - wire width 2 $3\src22__data_o$next[1:0]$11246 - attribute \src "libresoc.v:180309.3-180354.6" - wire width 2 $3\src32__data_o$next[1:0]$11262 - attribute \src "libresoc.v:180437.3-180472.6" - wire $3\wr_detect$10[0:0]$11287 - attribute \src "libresoc.v:180273.3-180308.6" - wire $3\wr_detect$4[0:0]$11255 - attribute \src "libresoc.v:180355.3-180390.6" - wire $3\wr_detect$7[0:0]$11271 - attribute \src "libresoc.v:180191.3-180226.6" + attribute \src "libresoc.v:180859.3-180904.6" + wire width 2 $3\r2__data_o$next[1:0]$11159 + attribute \src "libresoc.v:180941.3-180973.6" + wire width 2 $3\reg$next[1:0]$11175 + attribute \src "libresoc.v:180613.3-180658.6" + wire width 2 $3\src12__data_o$next[1:0]$11117 + attribute \src "libresoc.v:180695.3-180740.6" + wire width 2 $3\src22__data_o$next[1:0]$11127 + attribute \src "libresoc.v:180777.3-180822.6" + wire width 2 $3\src32__data_o$next[1:0]$11143 + attribute \src "libresoc.v:180905.3-180940.6" + wire $3\wr_detect$10[0:0]$11168 + attribute \src "libresoc.v:180741.3-180776.6" + wire $3\wr_detect$4[0:0]$11136 + attribute \src "libresoc.v:180823.3-180858.6" + wire $3\wr_detect$7[0:0]$11152 + attribute \src "libresoc.v:180659.3-180694.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:180391.3-180436.6" - wire width 2 $4\r2__data_o$next[1:0]$11279 - attribute \src "libresoc.v:180473.3-180505.6" - wire width 2 $4\reg$next[1:0]$11295 - attribute \src "libresoc.v:180145.3-180190.6" - wire width 2 $4\src12__data_o$next[1:0]$11237 - attribute \src "libresoc.v:180227.3-180272.6" - wire width 2 $4\src22__data_o$next[1:0]$11247 - attribute \src "libresoc.v:180309.3-180354.6" - wire width 2 $4\src32__data_o$next[1:0]$11263 - attribute \src "libresoc.v:180437.3-180472.6" - wire $4\wr_detect$10[0:0]$11288 - attribute \src "libresoc.v:180273.3-180308.6" - wire $4\wr_detect$4[0:0]$11256 - attribute \src "libresoc.v:180355.3-180390.6" - wire $4\wr_detect$7[0:0]$11272 - attribute \src "libresoc.v:180191.3-180226.6" + attribute \src "libresoc.v:180859.3-180904.6" + wire width 2 $4\r2__data_o$next[1:0]$11160 + attribute \src "libresoc.v:180941.3-180973.6" + wire width 2 $4\reg$next[1:0]$11176 + attribute \src "libresoc.v:180613.3-180658.6" + wire width 2 $4\src12__data_o$next[1:0]$11118 + attribute \src "libresoc.v:180695.3-180740.6" + wire width 2 $4\src22__data_o$next[1:0]$11128 + attribute \src "libresoc.v:180777.3-180822.6" + wire width 2 $4\src32__data_o$next[1:0]$11144 + attribute \src "libresoc.v:180905.3-180940.6" + wire $4\wr_detect$10[0:0]$11169 + attribute \src "libresoc.v:180741.3-180776.6" + wire $4\wr_detect$4[0:0]$11137 + attribute \src "libresoc.v:180823.3-180858.6" + wire $4\wr_detect$7[0:0]$11153 + attribute \src "libresoc.v:180659.3-180694.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:180391.3-180436.6" - wire width 2 $5\r2__data_o$next[1:0]$11280 - attribute \src "libresoc.v:180473.3-180505.6" - wire width 2 $5\reg$next[1:0]$11296 - attribute \src "libresoc.v:180145.3-180190.6" - wire width 2 $5\src12__data_o$next[1:0]$11238 - attribute \src "libresoc.v:180227.3-180272.6" - wire width 2 $5\src22__data_o$next[1:0]$11248 - attribute \src "libresoc.v:180309.3-180354.6" - wire width 2 $5\src32__data_o$next[1:0]$11264 - attribute \src "libresoc.v:180437.3-180472.6" - wire $5\wr_detect$10[0:0]$11289 - attribute \src "libresoc.v:180273.3-180308.6" - wire $5\wr_detect$4[0:0]$11257 - attribute \src "libresoc.v:180355.3-180390.6" - wire $5\wr_detect$7[0:0]$11273 - attribute \src "libresoc.v:180191.3-180226.6" + attribute \src "libresoc.v:180859.3-180904.6" + wire width 2 $5\r2__data_o$next[1:0]$11161 + attribute \src "libresoc.v:180941.3-180973.6" + wire width 2 $5\reg$next[1:0]$11177 + attribute \src "libresoc.v:180613.3-180658.6" + wire width 2 $5\src12__data_o$next[1:0]$11119 + attribute \src "libresoc.v:180695.3-180740.6" + wire width 2 $5\src22__data_o$next[1:0]$11129 + attribute \src "libresoc.v:180777.3-180822.6" + wire width 2 $5\src32__data_o$next[1:0]$11145 + attribute \src "libresoc.v:180905.3-180940.6" + wire $5\wr_detect$10[0:0]$11170 + attribute \src "libresoc.v:180741.3-180776.6" + wire $5\wr_detect$4[0:0]$11138 + attribute \src "libresoc.v:180823.3-180858.6" + wire $5\wr_detect$7[0:0]$11154 + attribute \src "libresoc.v:180659.3-180694.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:180391.3-180436.6" - wire width 2 $6\r2__data_o$next[1:0]$11281 - attribute \src "libresoc.v:180145.3-180190.6" - wire width 2 $6\src12__data_o$next[1:0]$11239 - attribute \src "libresoc.v:180227.3-180272.6" - wire width 2 $6\src22__data_o$next[1:0]$11249 - attribute \src "libresoc.v:180309.3-180354.6" - wire width 2 $6\src32__data_o$next[1:0]$11265 - attribute \src "libresoc.v:180391.3-180436.6" - wire width 2 $7\r2__data_o$next[1:0]$11282 - attribute \src "libresoc.v:180145.3-180190.6" - wire width 2 $7\src12__data_o$next[1:0]$11240 - attribute \src "libresoc.v:180227.3-180272.6" - wire width 2 $7\src22__data_o$next[1:0]$11250 - attribute \src "libresoc.v:180309.3-180354.6" - wire width 2 $7\src32__data_o$next[1:0]$11266 - attribute \src "libresoc.v:180131.17-180131.104" - wire $not$libresoc.v:180131$11223_Y - attribute \src "libresoc.v:180132.17-180132.100" - wire $not$libresoc.v:180132$11224_Y - attribute \src "libresoc.v:180133.17-180133.103" - wire $not$libresoc.v:180133$11225_Y - attribute \src "libresoc.v:180134.17-180134.103" - wire $not$libresoc.v:180134$11226_Y + attribute \src "libresoc.v:180859.3-180904.6" + wire width 2 $6\r2__data_o$next[1:0]$11162 + attribute \src "libresoc.v:180613.3-180658.6" + wire width 2 $6\src12__data_o$next[1:0]$11120 + attribute \src "libresoc.v:180695.3-180740.6" + wire width 2 $6\src22__data_o$next[1:0]$11130 + attribute \src "libresoc.v:180777.3-180822.6" + wire width 2 $6\src32__data_o$next[1:0]$11146 + attribute \src "libresoc.v:180859.3-180904.6" + wire width 2 $7\r2__data_o$next[1:0]$11163 + attribute \src "libresoc.v:180613.3-180658.6" + wire width 2 $7\src12__data_o$next[1:0]$11121 + attribute \src "libresoc.v:180695.3-180740.6" + wire width 2 $7\src22__data_o$next[1:0]$11131 + attribute \src "libresoc.v:180777.3-180822.6" + wire width 2 $7\src32__data_o$next[1:0]$11147 + attribute \src "libresoc.v:180599.17-180599.104" + wire $not$libresoc.v:180599$11104_Y + attribute \src "libresoc.v:180600.17-180600.100" + wire $not$libresoc.v:180600$11105_Y + attribute \src "libresoc.v:180601.17-180601.103" + wire $not$libresoc.v:180601$11106_Y + attribute \src "libresoc.v:180602.17-180602.103" + wire $not$libresoc.v:180602$11107_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -370305,9 +336230,9 @@ module \reg_2$134 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest12__data_i @@ -370321,7 +336246,7 @@ module \reg_2$134 wire width 2 input 13 \dest32__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest32__wen - attribute \src "libresoc.v:180062.7-180062.15" + attribute \src "libresoc.v:180530.7-180530.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r2__data_o @@ -370364,129 +336289,129 @@ module \reg_2$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180131$11223 + cell $not $not$libresoc.v:180599$11104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:180131$11223_Y + connect \Y $not$libresoc.v:180599$11104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180132$11224 + cell $not $not$libresoc.v:180600$11105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180132$11224_Y + connect \Y $not$libresoc.v:180600$11105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180133$11225 + cell $not $not$libresoc.v:180601$11106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180133$11225_Y + connect \Y $not$libresoc.v:180601$11106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180134$11226 + cell $not $not$libresoc.v:180602$11107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180134$11226_Y + connect \Y $not$libresoc.v:180602$11107_Y end - attribute \src "libresoc.v:180062.7-180062.20" - process $proc$libresoc.v:180062$11297 + attribute \src "libresoc.v:180530.7-180530.20" + process $proc$libresoc.v:180530$11178 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180089.13-180089.30" - process $proc$libresoc.v:180089$11298 + attribute \src "libresoc.v:180557.13-180557.30" + process $proc$libresoc.v:180557$11179 assign { } { } assign $1\r2__data_o[1:0] 2'00 sync always sync init update \r2__data_o $1\r2__data_o[1:0] end - attribute \src "libresoc.v:180095.13-180095.25" - process $proc$libresoc.v:180095$11299 + attribute \src "libresoc.v:180563.13-180563.25" + process $proc$libresoc.v:180563$11180 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:180100.13-180100.33" - process $proc$libresoc.v:180100$11300 + attribute \src "libresoc.v:180568.13-180568.33" + process $proc$libresoc.v:180568$11181 assign { } { } assign $1\src12__data_o[1:0] 2'00 sync always sync init update \src12__data_o $1\src12__data_o[1:0] end - attribute \src "libresoc.v:180107.13-180107.33" - process $proc$libresoc.v:180107$11301 + attribute \src "libresoc.v:180575.13-180575.33" + process $proc$libresoc.v:180575$11182 assign { } { } assign $1\src22__data_o[1:0] 2'00 sync always sync init update \src22__data_o $1\src22__data_o[1:0] end - attribute \src "libresoc.v:180114.13-180114.33" - process $proc$libresoc.v:180114$11302 + attribute \src "libresoc.v:180582.13-180582.33" + process $proc$libresoc.v:180582$11183 assign { } { } assign $1\src32__data_o[1:0] 2'00 sync always sync init update \src32__data_o $1\src32__data_o[1:0] end - attribute \src "libresoc.v:180135.3-180136.25" - process $proc$libresoc.v:180135$11227 + attribute \src "libresoc.v:180603.3-180604.25" + process $proc$libresoc.v:180603$11108 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:180137.3-180138.37" - process $proc$libresoc.v:180137$11228 + attribute \src "libresoc.v:180605.3-180606.37" + process $proc$libresoc.v:180605$11109 assign { } { } assign $0\r2__data_o[1:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[1:0] end - attribute \src "libresoc.v:180139.3-180140.43" - process $proc$libresoc.v:180139$11229 + attribute \src "libresoc.v:180607.3-180608.43" + process $proc$libresoc.v:180607$11110 assign { } { } assign $0\src32__data_o[1:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[1:0] end - attribute \src "libresoc.v:180141.3-180142.43" - process $proc$libresoc.v:180141$11230 + attribute \src "libresoc.v:180609.3-180610.43" + process $proc$libresoc.v:180609$11111 assign { } { } assign $0\src22__data_o[1:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[1:0] end - attribute \src "libresoc.v:180143.3-180144.43" - process $proc$libresoc.v:180143$11231 + attribute \src "libresoc.v:180611.3-180612.43" + process $proc$libresoc.v:180611$11112 assign { } { } assign $0\src12__data_o[1:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[1:0] end - attribute \src "libresoc.v:180145.3-180190.6" - process $proc$libresoc.v:180145$11232 + attribute \src "libresoc.v:180613.3-180658.6" + process $proc$libresoc.v:180613$11113 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[1:0]$11233 $7\src12__data_o$next[1:0]$11240 - attribute \src "libresoc.v:180146.5-180146.29" + assign $0\src12__data_o$next[1:0]$11114 $7\src12__data_o$next[1:0]$11121 + attribute \src "libresoc.v:180614.5-180614.29" switch \initial - attribute \src "libresoc.v:180146.9-180146.17" + attribute \src "libresoc.v:180614.9-180614.17" case 1'1 case end @@ -370499,75 +336424,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[1:0]$11234 $6\src12__data_o$next[1:0]$11239 + assign $1\src12__data_o$next[1:0]$11115 $6\src12__data_o$next[1:0]$11120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[1:0]$11235 \dest12__data_i + assign $2\src12__data_o$next[1:0]$11116 \dest12__data_i case - assign $2\src12__data_o$next[1:0]$11235 2'00 + assign $2\src12__data_o$next[1:0]$11116 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[1:0]$11236 \dest22__data_i + assign $3\src12__data_o$next[1:0]$11117 \dest22__data_i case - assign $3\src12__data_o$next[1:0]$11236 $2\src12__data_o$next[1:0]$11235 + assign $3\src12__data_o$next[1:0]$11117 $2\src12__data_o$next[1:0]$11116 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[1:0]$11237 \dest32__data_i + assign $4\src12__data_o$next[1:0]$11118 \dest32__data_i case - assign $4\src12__data_o$next[1:0]$11237 $3\src12__data_o$next[1:0]$11236 + assign $4\src12__data_o$next[1:0]$11118 $3\src12__data_o$next[1:0]$11117 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[1:0]$11238 \w2__data_i + assign $5\src12__data_o$next[1:0]$11119 \w2__data_i case - assign $5\src12__data_o$next[1:0]$11238 $4\src12__data_o$next[1:0]$11237 + assign $5\src12__data_o$next[1:0]$11119 $4\src12__data_o$next[1:0]$11118 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[1:0]$11239 \reg + assign $6\src12__data_o$next[1:0]$11120 \reg case - assign $6\src12__data_o$next[1:0]$11239 $5\src12__data_o$next[1:0]$11238 + assign $6\src12__data_o$next[1:0]$11120 $5\src12__data_o$next[1:0]$11119 end case - assign $1\src12__data_o$next[1:0]$11234 2'00 + assign $1\src12__data_o$next[1:0]$11115 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src12__data_o$next[1:0]$11240 2'00 + assign $7\src12__data_o$next[1:0]$11121 2'00 case - assign $7\src12__data_o$next[1:0]$11240 $1\src12__data_o$next[1:0]$11234 + assign $7\src12__data_o$next[1:0]$11121 $1\src12__data_o$next[1:0]$11115 end sync always - update \src12__data_o$next $0\src12__data_o$next[1:0]$11233 + update \src12__data_o$next $0\src12__data_o$next[1:0]$11114 end - attribute \src "libresoc.v:180191.3-180226.6" - process $proc$libresoc.v:180191$11241 + attribute \src "libresoc.v:180659.3-180694.6" + process $proc$libresoc.v:180659$11122 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:180192.5-180192.29" + attribute \src "libresoc.v:180660.5-180660.29" switch \initial - attribute \src "libresoc.v:180192.9-180192.17" + attribute \src "libresoc.v:180660.9-180660.17" case 1'1 case end @@ -370623,15 +336548,15 @@ module \reg_2$134 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:180227.3-180272.6" - process $proc$libresoc.v:180227$11242 + attribute \src "libresoc.v:180695.3-180740.6" + process $proc$libresoc.v:180695$11123 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[1:0]$11243 $7\src22__data_o$next[1:0]$11250 - attribute \src "libresoc.v:180228.5-180228.29" + assign $0\src22__data_o$next[1:0]$11124 $7\src22__data_o$next[1:0]$11131 + attribute \src "libresoc.v:180696.5-180696.29" switch \initial - attribute \src "libresoc.v:180228.9-180228.17" + attribute \src "libresoc.v:180696.9-180696.17" case 1'1 case end @@ -370644,75 +336569,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[1:0]$11244 $6\src22__data_o$next[1:0]$11249 + assign $1\src22__data_o$next[1:0]$11125 $6\src22__data_o$next[1:0]$11130 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[1:0]$11245 \dest12__data_i + assign $2\src22__data_o$next[1:0]$11126 \dest12__data_i case - assign $2\src22__data_o$next[1:0]$11245 2'00 + assign $2\src22__data_o$next[1:0]$11126 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[1:0]$11246 \dest22__data_i + assign $3\src22__data_o$next[1:0]$11127 \dest22__data_i case - assign $3\src22__data_o$next[1:0]$11246 $2\src22__data_o$next[1:0]$11245 + assign $3\src22__data_o$next[1:0]$11127 $2\src22__data_o$next[1:0]$11126 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[1:0]$11247 \dest32__data_i + assign $4\src22__data_o$next[1:0]$11128 \dest32__data_i case - assign $4\src22__data_o$next[1:0]$11247 $3\src22__data_o$next[1:0]$11246 + assign $4\src22__data_o$next[1:0]$11128 $3\src22__data_o$next[1:0]$11127 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[1:0]$11248 \w2__data_i + assign $5\src22__data_o$next[1:0]$11129 \w2__data_i case - assign $5\src22__data_o$next[1:0]$11248 $4\src22__data_o$next[1:0]$11247 + assign $5\src22__data_o$next[1:0]$11129 $4\src22__data_o$next[1:0]$11128 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[1:0]$11249 \reg + assign $6\src22__data_o$next[1:0]$11130 \reg case - assign $6\src22__data_o$next[1:0]$11249 $5\src22__data_o$next[1:0]$11248 + assign $6\src22__data_o$next[1:0]$11130 $5\src22__data_o$next[1:0]$11129 end case - assign $1\src22__data_o$next[1:0]$11244 2'00 + assign $1\src22__data_o$next[1:0]$11125 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src22__data_o$next[1:0]$11250 2'00 + assign $7\src22__data_o$next[1:0]$11131 2'00 case - assign $7\src22__data_o$next[1:0]$11250 $1\src22__data_o$next[1:0]$11244 + assign $7\src22__data_o$next[1:0]$11131 $1\src22__data_o$next[1:0]$11125 end sync always - update \src22__data_o$next $0\src22__data_o$next[1:0]$11243 + update \src22__data_o$next $0\src22__data_o$next[1:0]$11124 end - attribute \src "libresoc.v:180273.3-180308.6" - process $proc$libresoc.v:180273$11251 + attribute \src "libresoc.v:180741.3-180776.6" + process $proc$libresoc.v:180741$11132 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11252 $1\wr_detect$4[0:0]$11253 - attribute \src "libresoc.v:180274.5-180274.29" + assign $0\wr_detect$4[0:0]$11133 $1\wr_detect$4[0:0]$11134 + attribute \src "libresoc.v:180742.5-180742.29" switch \initial - attribute \src "libresoc.v:180274.9-180274.17" + attribute \src "libresoc.v:180742.9-180742.17" case 1'1 case end @@ -370725,58 +336650,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11253 $5\wr_detect$4[0:0]$11257 + assign $1\wr_detect$4[0:0]$11134 $5\wr_detect$4[0:0]$11138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11254 1'1 + assign $2\wr_detect$4[0:0]$11135 1'1 case - assign $2\wr_detect$4[0:0]$11254 1'0 + assign $2\wr_detect$4[0:0]$11135 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11255 1'1 + assign $3\wr_detect$4[0:0]$11136 1'1 case - assign $3\wr_detect$4[0:0]$11255 $2\wr_detect$4[0:0]$11254 + assign $3\wr_detect$4[0:0]$11136 $2\wr_detect$4[0:0]$11135 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11256 1'1 + assign $4\wr_detect$4[0:0]$11137 1'1 case - assign $4\wr_detect$4[0:0]$11256 $3\wr_detect$4[0:0]$11255 + assign $4\wr_detect$4[0:0]$11137 $3\wr_detect$4[0:0]$11136 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11257 1'1 + assign $5\wr_detect$4[0:0]$11138 1'1 case - assign $5\wr_detect$4[0:0]$11257 $4\wr_detect$4[0:0]$11256 + assign $5\wr_detect$4[0:0]$11138 $4\wr_detect$4[0:0]$11137 end case - assign $1\wr_detect$4[0:0]$11253 1'0 + assign $1\wr_detect$4[0:0]$11134 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11252 + update \wr_detect$4 $0\wr_detect$4[0:0]$11133 end - attribute \src "libresoc.v:180309.3-180354.6" - process $proc$libresoc.v:180309$11258 + attribute \src "libresoc.v:180777.3-180822.6" + process $proc$libresoc.v:180777$11139 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[1:0]$11259 $7\src32__data_o$next[1:0]$11266 - attribute \src "libresoc.v:180310.5-180310.29" + assign $0\src32__data_o$next[1:0]$11140 $7\src32__data_o$next[1:0]$11147 + attribute \src "libresoc.v:180778.5-180778.29" switch \initial - attribute \src "libresoc.v:180310.9-180310.17" + attribute \src "libresoc.v:180778.9-180778.17" case 1'1 case end @@ -370789,75 +336714,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[1:0]$11260 $6\src32__data_o$next[1:0]$11265 + assign $1\src32__data_o$next[1:0]$11141 $6\src32__data_o$next[1:0]$11146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[1:0]$11261 \dest12__data_i + assign $2\src32__data_o$next[1:0]$11142 \dest12__data_i case - assign $2\src32__data_o$next[1:0]$11261 2'00 + assign $2\src32__data_o$next[1:0]$11142 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[1:0]$11262 \dest22__data_i + assign $3\src32__data_o$next[1:0]$11143 \dest22__data_i case - assign $3\src32__data_o$next[1:0]$11262 $2\src32__data_o$next[1:0]$11261 + assign $3\src32__data_o$next[1:0]$11143 $2\src32__data_o$next[1:0]$11142 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[1:0]$11263 \dest32__data_i + assign $4\src32__data_o$next[1:0]$11144 \dest32__data_i case - assign $4\src32__data_o$next[1:0]$11263 $3\src32__data_o$next[1:0]$11262 + assign $4\src32__data_o$next[1:0]$11144 $3\src32__data_o$next[1:0]$11143 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[1:0]$11264 \w2__data_i + assign $5\src32__data_o$next[1:0]$11145 \w2__data_i case - assign $5\src32__data_o$next[1:0]$11264 $4\src32__data_o$next[1:0]$11263 + assign $5\src32__data_o$next[1:0]$11145 $4\src32__data_o$next[1:0]$11144 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[1:0]$11265 \reg + assign $6\src32__data_o$next[1:0]$11146 \reg case - assign $6\src32__data_o$next[1:0]$11265 $5\src32__data_o$next[1:0]$11264 + assign $6\src32__data_o$next[1:0]$11146 $5\src32__data_o$next[1:0]$11145 end case - assign $1\src32__data_o$next[1:0]$11260 2'00 + assign $1\src32__data_o$next[1:0]$11141 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src32__data_o$next[1:0]$11266 2'00 + assign $7\src32__data_o$next[1:0]$11147 2'00 case - assign $7\src32__data_o$next[1:0]$11266 $1\src32__data_o$next[1:0]$11260 + assign $7\src32__data_o$next[1:0]$11147 $1\src32__data_o$next[1:0]$11141 end sync always - update \src32__data_o$next $0\src32__data_o$next[1:0]$11259 + update \src32__data_o$next $0\src32__data_o$next[1:0]$11140 end - attribute \src "libresoc.v:180355.3-180390.6" - process $proc$libresoc.v:180355$11267 + attribute \src "libresoc.v:180823.3-180858.6" + process $proc$libresoc.v:180823$11148 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11268 $1\wr_detect$7[0:0]$11269 - attribute \src "libresoc.v:180356.5-180356.29" + assign $0\wr_detect$7[0:0]$11149 $1\wr_detect$7[0:0]$11150 + attribute \src "libresoc.v:180824.5-180824.29" switch \initial - attribute \src "libresoc.v:180356.9-180356.17" + attribute \src "libresoc.v:180824.9-180824.17" case 1'1 case end @@ -370870,58 +336795,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11269 $5\wr_detect$7[0:0]$11273 + assign $1\wr_detect$7[0:0]$11150 $5\wr_detect$7[0:0]$11154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11270 1'1 + assign $2\wr_detect$7[0:0]$11151 1'1 case - assign $2\wr_detect$7[0:0]$11270 1'0 + assign $2\wr_detect$7[0:0]$11151 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11271 1'1 + assign $3\wr_detect$7[0:0]$11152 1'1 case - assign $3\wr_detect$7[0:0]$11271 $2\wr_detect$7[0:0]$11270 + assign $3\wr_detect$7[0:0]$11152 $2\wr_detect$7[0:0]$11151 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11272 1'1 + assign $4\wr_detect$7[0:0]$11153 1'1 case - assign $4\wr_detect$7[0:0]$11272 $3\wr_detect$7[0:0]$11271 + assign $4\wr_detect$7[0:0]$11153 $3\wr_detect$7[0:0]$11152 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11273 1'1 + assign $5\wr_detect$7[0:0]$11154 1'1 case - assign $5\wr_detect$7[0:0]$11273 $4\wr_detect$7[0:0]$11272 + assign $5\wr_detect$7[0:0]$11154 $4\wr_detect$7[0:0]$11153 end case - assign $1\wr_detect$7[0:0]$11269 1'0 + assign $1\wr_detect$7[0:0]$11150 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11268 + update \wr_detect$7 $0\wr_detect$7[0:0]$11149 end - attribute \src "libresoc.v:180391.3-180436.6" - process $proc$libresoc.v:180391$11274 + attribute \src "libresoc.v:180859.3-180904.6" + process $proc$libresoc.v:180859$11155 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[1:0]$11275 $7\r2__data_o$next[1:0]$11282 - attribute \src "libresoc.v:180392.5-180392.29" + assign $0\r2__data_o$next[1:0]$11156 $7\r2__data_o$next[1:0]$11163 + attribute \src "libresoc.v:180860.5-180860.29" switch \initial - attribute \src "libresoc.v:180392.9-180392.17" + attribute \src "libresoc.v:180860.9-180860.17" case 1'1 case end @@ -370934,75 +336859,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[1:0]$11276 $6\r2__data_o$next[1:0]$11281 + assign $1\r2__data_o$next[1:0]$11157 $6\r2__data_o$next[1:0]$11162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[1:0]$11277 \dest12__data_i + assign $2\r2__data_o$next[1:0]$11158 \dest12__data_i case - assign $2\r2__data_o$next[1:0]$11277 2'00 + assign $2\r2__data_o$next[1:0]$11158 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[1:0]$11278 \dest22__data_i + assign $3\r2__data_o$next[1:0]$11159 \dest22__data_i case - assign $3\r2__data_o$next[1:0]$11278 $2\r2__data_o$next[1:0]$11277 + assign $3\r2__data_o$next[1:0]$11159 $2\r2__data_o$next[1:0]$11158 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[1:0]$11279 \dest32__data_i + assign $4\r2__data_o$next[1:0]$11160 \dest32__data_i case - assign $4\r2__data_o$next[1:0]$11279 $3\r2__data_o$next[1:0]$11278 + assign $4\r2__data_o$next[1:0]$11160 $3\r2__data_o$next[1:0]$11159 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[1:0]$11280 \w2__data_i + assign $5\r2__data_o$next[1:0]$11161 \w2__data_i case - assign $5\r2__data_o$next[1:0]$11280 $4\r2__data_o$next[1:0]$11279 + assign $5\r2__data_o$next[1:0]$11161 $4\r2__data_o$next[1:0]$11160 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[1:0]$11281 \reg + assign $6\r2__data_o$next[1:0]$11162 \reg case - assign $6\r2__data_o$next[1:0]$11281 $5\r2__data_o$next[1:0]$11280 + assign $6\r2__data_o$next[1:0]$11162 $5\r2__data_o$next[1:0]$11161 end case - assign $1\r2__data_o$next[1:0]$11276 2'00 + assign $1\r2__data_o$next[1:0]$11157 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r2__data_o$next[1:0]$11282 2'00 + assign $7\r2__data_o$next[1:0]$11163 2'00 case - assign $7\r2__data_o$next[1:0]$11282 $1\r2__data_o$next[1:0]$11276 + assign $7\r2__data_o$next[1:0]$11163 $1\r2__data_o$next[1:0]$11157 end sync always - update \r2__data_o$next $0\r2__data_o$next[1:0]$11275 + update \r2__data_o$next $0\r2__data_o$next[1:0]$11156 end - attribute \src "libresoc.v:180437.3-180472.6" - process $proc$libresoc.v:180437$11283 + attribute \src "libresoc.v:180905.3-180940.6" + process $proc$libresoc.v:180905$11164 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11284 $1\wr_detect$10[0:0]$11285 - attribute \src "libresoc.v:180438.5-180438.29" + assign $0\wr_detect$10[0:0]$11165 $1\wr_detect$10[0:0]$11166 + attribute \src "libresoc.v:180906.5-180906.29" switch \initial - attribute \src "libresoc.v:180438.9-180438.17" + attribute \src "libresoc.v:180906.9-180906.17" case 1'1 case end @@ -371015,61 +336940,61 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11285 $5\wr_detect$10[0:0]$11289 + assign $1\wr_detect$10[0:0]$11166 $5\wr_detect$10[0:0]$11170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11286 1'1 + assign $2\wr_detect$10[0:0]$11167 1'1 case - assign $2\wr_detect$10[0:0]$11286 1'0 + assign $2\wr_detect$10[0:0]$11167 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11287 1'1 + assign $3\wr_detect$10[0:0]$11168 1'1 case - assign $3\wr_detect$10[0:0]$11287 $2\wr_detect$10[0:0]$11286 + assign $3\wr_detect$10[0:0]$11168 $2\wr_detect$10[0:0]$11167 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11288 1'1 + assign $4\wr_detect$10[0:0]$11169 1'1 case - assign $4\wr_detect$10[0:0]$11288 $3\wr_detect$10[0:0]$11287 + assign $4\wr_detect$10[0:0]$11169 $3\wr_detect$10[0:0]$11168 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$11289 1'1 + assign $5\wr_detect$10[0:0]$11170 1'1 case - assign $5\wr_detect$10[0:0]$11289 $4\wr_detect$10[0:0]$11288 + assign $5\wr_detect$10[0:0]$11170 $4\wr_detect$10[0:0]$11169 end case - assign $1\wr_detect$10[0:0]$11285 1'0 + assign $1\wr_detect$10[0:0]$11166 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11284 + update \wr_detect$10 $0\wr_detect$10[0:0]$11165 end - attribute \src "libresoc.v:180473.3-180505.6" - process $proc$libresoc.v:180473$11290 + attribute \src "libresoc.v:180941.3-180973.6" + process $proc$libresoc.v:180941$11171 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$11291 $5\reg$next[1:0]$11296 - attribute \src "libresoc.v:180474.5-180474.29" + assign $0\reg$next[1:0]$11172 $5\reg$next[1:0]$11177 + attribute \src "libresoc.v:180942.5-180942.29" switch \initial - attribute \src "libresoc.v:180474.9-180474.17" + attribute \src "libresoc.v:180942.9-180942.17" case 1'1 case end @@ -371078,179 +337003,179 @@ module \reg_2$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$11292 \dest12__data_i + assign $1\reg$next[1:0]$11173 \dest12__data_i case - assign $1\reg$next[1:0]$11292 \reg + assign $1\reg$next[1:0]$11173 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$11293 \dest22__data_i + assign $2\reg$next[1:0]$11174 \dest22__data_i case - assign $2\reg$next[1:0]$11293 $1\reg$next[1:0]$11292 + assign $2\reg$next[1:0]$11174 $1\reg$next[1:0]$11173 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$11294 \dest32__data_i + assign $3\reg$next[1:0]$11175 \dest32__data_i case - assign $3\reg$next[1:0]$11294 $2\reg$next[1:0]$11293 + assign $3\reg$next[1:0]$11175 $2\reg$next[1:0]$11174 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$11295 \w2__data_i + assign $4\reg$next[1:0]$11176 \w2__data_i case - assign $4\reg$next[1:0]$11295 $3\reg$next[1:0]$11294 + assign $4\reg$next[1:0]$11176 $3\reg$next[1:0]$11175 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$11296 2'00 + assign $5\reg$next[1:0]$11177 2'00 case - assign $5\reg$next[1:0]$11296 $4\reg$next[1:0]$11295 + assign $5\reg$next[1:0]$11177 $4\reg$next[1:0]$11176 end sync always - update \reg$next $0\reg$next[1:0]$11291 + update \reg$next $0\reg$next[1:0]$11172 end - connect \$9 $not$libresoc.v:180131$11223_Y - connect \$1 $not$libresoc.v:180132$11224_Y - connect \$3 $not$libresoc.v:180133$11225_Y - connect \$6 $not$libresoc.v:180134$11226_Y + connect \$9 $not$libresoc.v:180599$11104_Y + connect \$1 $not$libresoc.v:180600$11105_Y + connect \$3 $not$libresoc.v:180601$11106_Y + connect \$6 $not$libresoc.v:180602$11107_Y end -attribute \src "libresoc.v:180510.1-180859.10" +attribute \src "libresoc.v:180978.1-181327.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" attribute \generator "nMigen" module \reg_2$137 - attribute \src "libresoc.v:180580.3-180625.6" - wire width 64 $0\cia2__data_o$next[63:0]$11311 - attribute \src "libresoc.v:180578.3-180579.41" + attribute \src "libresoc.v:181048.3-181093.6" + wire width 64 $0\cia2__data_o$next[63:0]$11192 + attribute \src "libresoc.v:181046.3-181047.41" wire width 64 $0\cia2__data_o[63:0] - attribute \src "libresoc.v:180511.7-180511.20" + attribute \src "libresoc.v:180979.7-180979.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180662.3-180707.6" - wire width 64 $0\msr2__data_o$next[63:0]$11321 - attribute \src "libresoc.v:180576.3-180577.41" + attribute \src "libresoc.v:181130.3-181175.6" + wire width 64 $0\msr2__data_o$next[63:0]$11202 + attribute \src "libresoc.v:181044.3-181045.41" wire width 64 $0\msr2__data_o[63:0] - attribute \src "libresoc.v:180826.3-180858.6" - wire width 64 $0\reg$next[63:0]$11353 - attribute \src "libresoc.v:180572.3-180573.25" + attribute \src "libresoc.v:181294.3-181326.6" + wire width 64 $0\reg$next[63:0]$11234 + attribute \src "libresoc.v:181040.3-181041.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:180744.3-180789.6" - wire width 64 $0\sv2__data_o$next[63:0]$11337 - attribute \src "libresoc.v:180574.3-180575.39" + attribute \src "libresoc.v:181212.3-181257.6" + wire width 64 $0\sv2__data_o$next[63:0]$11218 + attribute \src "libresoc.v:181042.3-181043.39" wire width 64 $0\sv2__data_o[63:0] - attribute \src "libresoc.v:180708.3-180743.6" - wire $0\wr_detect$4[0:0]$11330 - attribute \src "libresoc.v:180790.3-180825.6" - wire $0\wr_detect$7[0:0]$11346 - attribute \src "libresoc.v:180626.3-180661.6" + attribute \src "libresoc.v:181176.3-181211.6" + wire $0\wr_detect$4[0:0]$11211 + attribute \src "libresoc.v:181258.3-181293.6" + wire $0\wr_detect$7[0:0]$11227 + attribute \src "libresoc.v:181094.3-181129.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:180580.3-180625.6" - wire width 64 $1\cia2__data_o$next[63:0]$11312 - attribute \src "libresoc.v:180520.14-180520.49" + attribute \src "libresoc.v:181048.3-181093.6" + wire width 64 $1\cia2__data_o$next[63:0]$11193 + attribute \src "libresoc.v:180988.14-180988.49" wire width 64 $1\cia2__data_o[63:0] - attribute \src "libresoc.v:180662.3-180707.6" - wire width 64 $1\msr2__data_o$next[63:0]$11322 - attribute \src "libresoc.v:180537.14-180537.49" + attribute \src "libresoc.v:181130.3-181175.6" + wire width 64 $1\msr2__data_o$next[63:0]$11203 + attribute \src "libresoc.v:181005.14-181005.49" wire width 64 $1\msr2__data_o[63:0] - attribute \src "libresoc.v:180826.3-180858.6" - wire width 64 $1\reg$next[63:0]$11354 - attribute \src "libresoc.v:180549.14-180549.42" + attribute \src "libresoc.v:181294.3-181326.6" + wire width 64 $1\reg$next[63:0]$11235 + attribute \src "libresoc.v:181017.14-181017.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:180744.3-180789.6" - wire width 64 $1\sv2__data_o$next[63:0]$11338 - attribute \src "libresoc.v:180556.14-180556.48" + attribute \src "libresoc.v:181212.3-181257.6" + wire width 64 $1\sv2__data_o$next[63:0]$11219 + attribute \src "libresoc.v:181024.14-181024.48" wire width 64 $1\sv2__data_o[63:0] - attribute \src "libresoc.v:180708.3-180743.6" - wire $1\wr_detect$4[0:0]$11331 - attribute \src "libresoc.v:180790.3-180825.6" - wire $1\wr_detect$7[0:0]$11347 - attribute \src "libresoc.v:180626.3-180661.6" + attribute \src "libresoc.v:181176.3-181211.6" + wire $1\wr_detect$4[0:0]$11212 + attribute \src "libresoc.v:181258.3-181293.6" + wire $1\wr_detect$7[0:0]$11228 + attribute \src "libresoc.v:181094.3-181129.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:180580.3-180625.6" - wire width 64 $2\cia2__data_o$next[63:0]$11313 - attribute \src "libresoc.v:180662.3-180707.6" - wire width 64 $2\msr2__data_o$next[63:0]$11323 - attribute \src "libresoc.v:180826.3-180858.6" - wire width 64 $2\reg$next[63:0]$11355 - attribute \src "libresoc.v:180744.3-180789.6" - wire width 64 $2\sv2__data_o$next[63:0]$11339 - attribute \src "libresoc.v:180708.3-180743.6" - wire $2\wr_detect$4[0:0]$11332 - attribute \src "libresoc.v:180790.3-180825.6" - wire $2\wr_detect$7[0:0]$11348 - attribute \src "libresoc.v:180626.3-180661.6" + attribute \src "libresoc.v:181048.3-181093.6" + wire width 64 $2\cia2__data_o$next[63:0]$11194 + attribute \src "libresoc.v:181130.3-181175.6" + wire width 64 $2\msr2__data_o$next[63:0]$11204 + attribute \src "libresoc.v:181294.3-181326.6" + wire width 64 $2\reg$next[63:0]$11236 + attribute \src "libresoc.v:181212.3-181257.6" + wire width 64 $2\sv2__data_o$next[63:0]$11220 + attribute \src "libresoc.v:181176.3-181211.6" + wire $2\wr_detect$4[0:0]$11213 + attribute \src "libresoc.v:181258.3-181293.6" + wire $2\wr_detect$7[0:0]$11229 + attribute \src "libresoc.v:181094.3-181129.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:180580.3-180625.6" - wire width 64 $3\cia2__data_o$next[63:0]$11314 - attribute \src "libresoc.v:180662.3-180707.6" - wire width 64 $3\msr2__data_o$next[63:0]$11324 - attribute \src "libresoc.v:180826.3-180858.6" - wire width 64 $3\reg$next[63:0]$11356 - attribute \src "libresoc.v:180744.3-180789.6" - wire width 64 $3\sv2__data_o$next[63:0]$11340 - attribute \src "libresoc.v:180708.3-180743.6" - wire $3\wr_detect$4[0:0]$11333 - attribute \src "libresoc.v:180790.3-180825.6" - wire $3\wr_detect$7[0:0]$11349 - attribute \src "libresoc.v:180626.3-180661.6" + attribute \src "libresoc.v:181048.3-181093.6" + wire width 64 $3\cia2__data_o$next[63:0]$11195 + attribute \src "libresoc.v:181130.3-181175.6" + wire width 64 $3\msr2__data_o$next[63:0]$11205 + attribute \src "libresoc.v:181294.3-181326.6" + wire width 64 $3\reg$next[63:0]$11237 + attribute \src "libresoc.v:181212.3-181257.6" + wire width 64 $3\sv2__data_o$next[63:0]$11221 + attribute \src "libresoc.v:181176.3-181211.6" + wire $3\wr_detect$4[0:0]$11214 + attribute \src "libresoc.v:181258.3-181293.6" + wire $3\wr_detect$7[0:0]$11230 + attribute \src "libresoc.v:181094.3-181129.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:180580.3-180625.6" - wire width 64 $4\cia2__data_o$next[63:0]$11315 - attribute \src "libresoc.v:180662.3-180707.6" - wire width 64 $4\msr2__data_o$next[63:0]$11325 - attribute \src "libresoc.v:180826.3-180858.6" - wire width 64 $4\reg$next[63:0]$11357 - attribute \src "libresoc.v:180744.3-180789.6" - wire width 64 $4\sv2__data_o$next[63:0]$11341 - attribute \src "libresoc.v:180708.3-180743.6" - wire $4\wr_detect$4[0:0]$11334 - attribute \src "libresoc.v:180790.3-180825.6" - wire $4\wr_detect$7[0:0]$11350 - attribute \src "libresoc.v:180626.3-180661.6" + attribute \src "libresoc.v:181048.3-181093.6" + wire width 64 $4\cia2__data_o$next[63:0]$11196 + attribute \src "libresoc.v:181130.3-181175.6" + wire width 64 $4\msr2__data_o$next[63:0]$11206 + attribute \src "libresoc.v:181294.3-181326.6" + wire width 64 $4\reg$next[63:0]$11238 + attribute \src "libresoc.v:181212.3-181257.6" + wire width 64 $4\sv2__data_o$next[63:0]$11222 + attribute \src "libresoc.v:181176.3-181211.6" + wire $4\wr_detect$4[0:0]$11215 + attribute \src "libresoc.v:181258.3-181293.6" + wire $4\wr_detect$7[0:0]$11231 + attribute \src "libresoc.v:181094.3-181129.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:180580.3-180625.6" - wire width 64 $5\cia2__data_o$next[63:0]$11316 - attribute \src "libresoc.v:180662.3-180707.6" - wire width 64 $5\msr2__data_o$next[63:0]$11326 - attribute \src "libresoc.v:180826.3-180858.6" - wire width 64 $5\reg$next[63:0]$11358 - attribute \src "libresoc.v:180744.3-180789.6" - wire width 64 $5\sv2__data_o$next[63:0]$11342 - attribute \src "libresoc.v:180708.3-180743.6" - wire $5\wr_detect$4[0:0]$11335 - attribute \src "libresoc.v:180790.3-180825.6" - wire $5\wr_detect$7[0:0]$11351 - attribute \src "libresoc.v:180626.3-180661.6" + attribute \src "libresoc.v:181048.3-181093.6" + wire width 64 $5\cia2__data_o$next[63:0]$11197 + attribute \src "libresoc.v:181130.3-181175.6" + wire width 64 $5\msr2__data_o$next[63:0]$11207 + attribute \src "libresoc.v:181294.3-181326.6" + wire width 64 $5\reg$next[63:0]$11239 + attribute \src "libresoc.v:181212.3-181257.6" + wire width 64 $5\sv2__data_o$next[63:0]$11223 + attribute \src "libresoc.v:181176.3-181211.6" + wire $5\wr_detect$4[0:0]$11216 + attribute \src "libresoc.v:181258.3-181293.6" + wire $5\wr_detect$7[0:0]$11232 + attribute \src "libresoc.v:181094.3-181129.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:180580.3-180625.6" - wire width 64 $6\cia2__data_o$next[63:0]$11317 - attribute \src "libresoc.v:180662.3-180707.6" - wire width 64 $6\msr2__data_o$next[63:0]$11327 - attribute \src "libresoc.v:180744.3-180789.6" - wire width 64 $6\sv2__data_o$next[63:0]$11343 - attribute \src "libresoc.v:180580.3-180625.6" - wire width 64 $7\cia2__data_o$next[63:0]$11318 - attribute \src "libresoc.v:180662.3-180707.6" - wire width 64 $7\msr2__data_o$next[63:0]$11328 - attribute \src "libresoc.v:180744.3-180789.6" - wire width 64 $7\sv2__data_o$next[63:0]$11344 - attribute \src "libresoc.v:180569.17-180569.100" - wire $not$libresoc.v:180569$11303_Y - attribute \src "libresoc.v:180570.17-180570.103" - wire $not$libresoc.v:180570$11304_Y - attribute \src "libresoc.v:180571.17-180571.103" - wire $not$libresoc.v:180571$11305_Y + attribute \src "libresoc.v:181048.3-181093.6" + wire width 64 $6\cia2__data_o$next[63:0]$11198 + attribute \src "libresoc.v:181130.3-181175.6" + wire width 64 $6\msr2__data_o$next[63:0]$11208 + attribute \src "libresoc.v:181212.3-181257.6" + wire width 64 $6\sv2__data_o$next[63:0]$11224 + attribute \src "libresoc.v:181048.3-181093.6" + wire width 64 $7\cia2__data_o$next[63:0]$11199 + attribute \src "libresoc.v:181130.3-181175.6" + wire width 64 $7\msr2__data_o$next[63:0]$11209 + attribute \src "libresoc.v:181212.3-181257.6" + wire width 64 $7\sv2__data_o$next[63:0]$11225 + attribute \src "libresoc.v:181037.17-181037.100" + wire $not$libresoc.v:181037$11184_Y + attribute \src "libresoc.v:181038.17-181038.103" + wire $not$libresoc.v:181038$11185_Y + attribute \src "libresoc.v:181039.17-181039.103" + wire $not$libresoc.v:181039$11186_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -371263,15 +337188,15 @@ module \reg_2$137 wire width 64 \cia2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr12__wen - attribute \src "libresoc.v:180511.7-180511.15" + attribute \src "libresoc.v:180979.7-180979.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr2__data_i @@ -371308,106 +337233,106 @@ module \reg_2$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180569$11303 + cell $not $not$libresoc.v:181037$11184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180569$11303_Y + connect \Y $not$libresoc.v:181037$11184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180570$11304 + cell $not $not$libresoc.v:181038$11185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180570$11304_Y + connect \Y $not$libresoc.v:181038$11185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180571$11305 + cell $not $not$libresoc.v:181039$11186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180571$11305_Y + connect \Y $not$libresoc.v:181039$11186_Y end - attribute \src "libresoc.v:180511.7-180511.20" - process $proc$libresoc.v:180511$11359 + attribute \src "libresoc.v:180979.7-180979.20" + process $proc$libresoc.v:180979$11240 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180520.14-180520.49" - process $proc$libresoc.v:180520$11360 + attribute \src "libresoc.v:180988.14-180988.49" + process $proc$libresoc.v:180988$11241 assign { } { } assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia2__data_o $1\cia2__data_o[63:0] end - attribute \src "libresoc.v:180537.14-180537.49" - process $proc$libresoc.v:180537$11361 + attribute \src "libresoc.v:181005.14-181005.49" + process $proc$libresoc.v:181005$11242 assign { } { } assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr2__data_o $1\msr2__data_o[63:0] end - attribute \src "libresoc.v:180549.14-180549.42" - process $proc$libresoc.v:180549$11362 + attribute \src "libresoc.v:181017.14-181017.42" + process $proc$libresoc.v:181017$11243 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:180556.14-180556.48" - process $proc$libresoc.v:180556$11363 + attribute \src "libresoc.v:181024.14-181024.48" + process $proc$libresoc.v:181024$11244 assign { } { } assign $1\sv2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv2__data_o $1\sv2__data_o[63:0] end - attribute \src "libresoc.v:180572.3-180573.25" - process $proc$libresoc.v:180572$11306 + attribute \src "libresoc.v:181040.3-181041.25" + process $proc$libresoc.v:181040$11187 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:180574.3-180575.39" - process $proc$libresoc.v:180574$11307 + attribute \src "libresoc.v:181042.3-181043.39" + process $proc$libresoc.v:181042$11188 assign { } { } assign $0\sv2__data_o[63:0] \sv2__data_o$next sync posedge \coresync_clk update \sv2__data_o $0\sv2__data_o[63:0] end - attribute \src "libresoc.v:180576.3-180577.41" - process $proc$libresoc.v:180576$11308 + attribute \src "libresoc.v:181044.3-181045.41" + process $proc$libresoc.v:181044$11189 assign { } { } assign $0\msr2__data_o[63:0] \msr2__data_o$next sync posedge \coresync_clk update \msr2__data_o $0\msr2__data_o[63:0] end - attribute \src "libresoc.v:180578.3-180579.41" - process $proc$libresoc.v:180578$11309 + attribute \src "libresoc.v:181046.3-181047.41" + process $proc$libresoc.v:181046$11190 assign { } { } assign $0\cia2__data_o[63:0] \cia2__data_o$next sync posedge \coresync_clk update \cia2__data_o $0\cia2__data_o[63:0] end - attribute \src "libresoc.v:180580.3-180625.6" - process $proc$libresoc.v:180580$11310 + attribute \src "libresoc.v:181048.3-181093.6" + process $proc$libresoc.v:181048$11191 assign { } { } assign { } { } assign { } { } - assign $0\cia2__data_o$next[63:0]$11311 $7\cia2__data_o$next[63:0]$11318 - attribute \src "libresoc.v:180581.5-180581.29" + assign $0\cia2__data_o$next[63:0]$11192 $7\cia2__data_o$next[63:0]$11199 + attribute \src "libresoc.v:181049.5-181049.29" switch \initial - attribute \src "libresoc.v:180581.9-180581.17" + attribute \src "libresoc.v:181049.9-181049.17" case 1'1 case end @@ -371420,75 +337345,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\cia2__data_o$next[63:0]$11312 $6\cia2__data_o$next[63:0]$11317 + assign $1\cia2__data_o$next[63:0]$11193 $6\cia2__data_o$next[63:0]$11198 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia2__data_o$next[63:0]$11313 \nia2__data_i + assign $2\cia2__data_o$next[63:0]$11194 \nia2__data_i case - assign $2\cia2__data_o$next[63:0]$11313 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia2__data_o$next[63:0]$11194 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia2__data_o$next[63:0]$11314 \msr2__data_i + assign $3\cia2__data_o$next[63:0]$11195 \msr2__data_i case - assign $3\cia2__data_o$next[63:0]$11314 $2\cia2__data_o$next[63:0]$11313 + assign $3\cia2__data_o$next[63:0]$11195 $2\cia2__data_o$next[63:0]$11194 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia2__data_o$next[63:0]$11315 \sv2__data_i + assign $4\cia2__data_o$next[63:0]$11196 \sv2__data_i case - assign $4\cia2__data_o$next[63:0]$11315 $3\cia2__data_o$next[63:0]$11314 + assign $4\cia2__data_o$next[63:0]$11196 $3\cia2__data_o$next[63:0]$11195 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia2__data_o$next[63:0]$11316 \d_wr12__data_i + assign $5\cia2__data_o$next[63:0]$11197 \d_wr12__data_i case - assign $5\cia2__data_o$next[63:0]$11316 $4\cia2__data_o$next[63:0]$11315 + assign $5\cia2__data_o$next[63:0]$11197 $4\cia2__data_o$next[63:0]$11196 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia2__data_o$next[63:0]$11317 \reg + assign $6\cia2__data_o$next[63:0]$11198 \reg case - assign $6\cia2__data_o$next[63:0]$11317 $5\cia2__data_o$next[63:0]$11316 + assign $6\cia2__data_o$next[63:0]$11198 $5\cia2__data_o$next[63:0]$11197 end case - assign $1\cia2__data_o$next[63:0]$11312 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia2__data_o$next[63:0]$11193 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia2__data_o$next[63:0]$11318 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia2__data_o$next[63:0]$11199 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia2__data_o$next[63:0]$11318 $1\cia2__data_o$next[63:0]$11312 + assign $7\cia2__data_o$next[63:0]$11199 $1\cia2__data_o$next[63:0]$11193 end sync always - update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11311 + update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11192 end - attribute \src "libresoc.v:180626.3-180661.6" - process $proc$libresoc.v:180626$11319 + attribute \src "libresoc.v:181094.3-181129.6" + process $proc$libresoc.v:181094$11200 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:180627.5-180627.29" + attribute \src "libresoc.v:181095.5-181095.29" switch \initial - attribute \src "libresoc.v:180627.9-180627.17" + attribute \src "libresoc.v:181095.9-181095.17" case 1'1 case end @@ -371544,15 +337469,15 @@ module \reg_2$137 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:180662.3-180707.6" - process $proc$libresoc.v:180662$11320 + attribute \src "libresoc.v:181130.3-181175.6" + process $proc$libresoc.v:181130$11201 assign { } { } assign { } { } assign { } { } - assign $0\msr2__data_o$next[63:0]$11321 $7\msr2__data_o$next[63:0]$11328 - attribute \src "libresoc.v:180663.5-180663.29" + assign $0\msr2__data_o$next[63:0]$11202 $7\msr2__data_o$next[63:0]$11209 + attribute \src "libresoc.v:181131.5-181131.29" switch \initial - attribute \src "libresoc.v:180663.9-180663.17" + attribute \src "libresoc.v:181131.9-181131.17" case 1'1 case end @@ -371565,75 +337490,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\msr2__data_o$next[63:0]$11322 $6\msr2__data_o$next[63:0]$11327 + assign $1\msr2__data_o$next[63:0]$11203 $6\msr2__data_o$next[63:0]$11208 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr2__data_o$next[63:0]$11323 \nia2__data_i + assign $2\msr2__data_o$next[63:0]$11204 \nia2__data_i case - assign $2\msr2__data_o$next[63:0]$11323 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr2__data_o$next[63:0]$11204 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr2__data_o$next[63:0]$11324 \msr2__data_i + assign $3\msr2__data_o$next[63:0]$11205 \msr2__data_i case - assign $3\msr2__data_o$next[63:0]$11324 $2\msr2__data_o$next[63:0]$11323 + assign $3\msr2__data_o$next[63:0]$11205 $2\msr2__data_o$next[63:0]$11204 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr2__data_o$next[63:0]$11325 \sv2__data_i + assign $4\msr2__data_o$next[63:0]$11206 \sv2__data_i case - assign $4\msr2__data_o$next[63:0]$11325 $3\msr2__data_o$next[63:0]$11324 + assign $4\msr2__data_o$next[63:0]$11206 $3\msr2__data_o$next[63:0]$11205 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr2__data_o$next[63:0]$11326 \d_wr12__data_i + assign $5\msr2__data_o$next[63:0]$11207 \d_wr12__data_i case - assign $5\msr2__data_o$next[63:0]$11326 $4\msr2__data_o$next[63:0]$11325 + assign $5\msr2__data_o$next[63:0]$11207 $4\msr2__data_o$next[63:0]$11206 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr2__data_o$next[63:0]$11327 \reg + assign $6\msr2__data_o$next[63:0]$11208 \reg case - assign $6\msr2__data_o$next[63:0]$11327 $5\msr2__data_o$next[63:0]$11326 + assign $6\msr2__data_o$next[63:0]$11208 $5\msr2__data_o$next[63:0]$11207 end case - assign $1\msr2__data_o$next[63:0]$11322 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr2__data_o$next[63:0]$11203 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr2__data_o$next[63:0]$11328 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr2__data_o$next[63:0]$11209 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr2__data_o$next[63:0]$11328 $1\msr2__data_o$next[63:0]$11322 + assign $7\msr2__data_o$next[63:0]$11209 $1\msr2__data_o$next[63:0]$11203 end sync always - update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11321 + update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11202 end - attribute \src "libresoc.v:180708.3-180743.6" - process $proc$libresoc.v:180708$11329 + attribute \src "libresoc.v:181176.3-181211.6" + process $proc$libresoc.v:181176$11210 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11330 $1\wr_detect$4[0:0]$11331 - attribute \src "libresoc.v:180709.5-180709.29" + assign $0\wr_detect$4[0:0]$11211 $1\wr_detect$4[0:0]$11212 + attribute \src "libresoc.v:181177.5-181177.29" switch \initial - attribute \src "libresoc.v:180709.9-180709.17" + attribute \src "libresoc.v:181177.9-181177.17" case 1'1 case end @@ -371646,58 +337571,58 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11331 $5\wr_detect$4[0:0]$11335 + assign $1\wr_detect$4[0:0]$11212 $5\wr_detect$4[0:0]$11216 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11332 1'1 + assign $2\wr_detect$4[0:0]$11213 1'1 case - assign $2\wr_detect$4[0:0]$11332 1'0 + assign $2\wr_detect$4[0:0]$11213 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11333 1'1 + assign $3\wr_detect$4[0:0]$11214 1'1 case - assign $3\wr_detect$4[0:0]$11333 $2\wr_detect$4[0:0]$11332 + assign $3\wr_detect$4[0:0]$11214 $2\wr_detect$4[0:0]$11213 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11334 1'1 + assign $4\wr_detect$4[0:0]$11215 1'1 case - assign $4\wr_detect$4[0:0]$11334 $3\wr_detect$4[0:0]$11333 + assign $4\wr_detect$4[0:0]$11215 $3\wr_detect$4[0:0]$11214 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11335 1'1 + assign $5\wr_detect$4[0:0]$11216 1'1 case - assign $5\wr_detect$4[0:0]$11335 $4\wr_detect$4[0:0]$11334 + assign $5\wr_detect$4[0:0]$11216 $4\wr_detect$4[0:0]$11215 end case - assign $1\wr_detect$4[0:0]$11331 1'0 + assign $1\wr_detect$4[0:0]$11212 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11330 + update \wr_detect$4 $0\wr_detect$4[0:0]$11211 end - attribute \src "libresoc.v:180744.3-180789.6" - process $proc$libresoc.v:180744$11336 + attribute \src "libresoc.v:181212.3-181257.6" + process $proc$libresoc.v:181212$11217 assign { } { } assign { } { } assign { } { } - assign $0\sv2__data_o$next[63:0]$11337 $7\sv2__data_o$next[63:0]$11344 - attribute \src "libresoc.v:180745.5-180745.29" + assign $0\sv2__data_o$next[63:0]$11218 $7\sv2__data_o$next[63:0]$11225 + attribute \src "libresoc.v:181213.5-181213.29" switch \initial - attribute \src "libresoc.v:180745.9-180745.17" + attribute \src "libresoc.v:181213.9-181213.17" case 1'1 case end @@ -371710,75 +337635,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\sv2__data_o$next[63:0]$11338 $6\sv2__data_o$next[63:0]$11343 + assign $1\sv2__data_o$next[63:0]$11219 $6\sv2__data_o$next[63:0]$11224 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv2__data_o$next[63:0]$11339 \nia2__data_i + assign $2\sv2__data_o$next[63:0]$11220 \nia2__data_i case - assign $2\sv2__data_o$next[63:0]$11339 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv2__data_o$next[63:0]$11220 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv2__data_o$next[63:0]$11340 \msr2__data_i + assign $3\sv2__data_o$next[63:0]$11221 \msr2__data_i case - assign $3\sv2__data_o$next[63:0]$11340 $2\sv2__data_o$next[63:0]$11339 + assign $3\sv2__data_o$next[63:0]$11221 $2\sv2__data_o$next[63:0]$11220 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv2__data_o$next[63:0]$11341 \sv2__data_i + assign $4\sv2__data_o$next[63:0]$11222 \sv2__data_i case - assign $4\sv2__data_o$next[63:0]$11341 $3\sv2__data_o$next[63:0]$11340 + assign $4\sv2__data_o$next[63:0]$11222 $3\sv2__data_o$next[63:0]$11221 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv2__data_o$next[63:0]$11342 \d_wr12__data_i + assign $5\sv2__data_o$next[63:0]$11223 \d_wr12__data_i case - assign $5\sv2__data_o$next[63:0]$11342 $4\sv2__data_o$next[63:0]$11341 + assign $5\sv2__data_o$next[63:0]$11223 $4\sv2__data_o$next[63:0]$11222 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv2__data_o$next[63:0]$11343 \reg + assign $6\sv2__data_o$next[63:0]$11224 \reg case - assign $6\sv2__data_o$next[63:0]$11343 $5\sv2__data_o$next[63:0]$11342 + assign $6\sv2__data_o$next[63:0]$11224 $5\sv2__data_o$next[63:0]$11223 end case - assign $1\sv2__data_o$next[63:0]$11338 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv2__data_o$next[63:0]$11219 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv2__data_o$next[63:0]$11344 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv2__data_o$next[63:0]$11225 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv2__data_o$next[63:0]$11344 $1\sv2__data_o$next[63:0]$11338 + assign $7\sv2__data_o$next[63:0]$11225 $1\sv2__data_o$next[63:0]$11219 end sync always - update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11337 + update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11218 end - attribute \src "libresoc.v:180790.3-180825.6" - process $proc$libresoc.v:180790$11345 + attribute \src "libresoc.v:181258.3-181293.6" + process $proc$libresoc.v:181258$11226 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11346 $1\wr_detect$7[0:0]$11347 - attribute \src "libresoc.v:180791.5-180791.29" + assign $0\wr_detect$7[0:0]$11227 $1\wr_detect$7[0:0]$11228 + attribute \src "libresoc.v:181259.5-181259.29" switch \initial - attribute \src "libresoc.v:180791.9-180791.17" + attribute \src "libresoc.v:181259.9-181259.17" case 1'1 case end @@ -371791,61 +337716,61 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11347 $5\wr_detect$7[0:0]$11351 + assign $1\wr_detect$7[0:0]$11228 $5\wr_detect$7[0:0]$11232 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11348 1'1 + assign $2\wr_detect$7[0:0]$11229 1'1 case - assign $2\wr_detect$7[0:0]$11348 1'0 + assign $2\wr_detect$7[0:0]$11229 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11349 1'1 + assign $3\wr_detect$7[0:0]$11230 1'1 case - assign $3\wr_detect$7[0:0]$11349 $2\wr_detect$7[0:0]$11348 + assign $3\wr_detect$7[0:0]$11230 $2\wr_detect$7[0:0]$11229 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11350 1'1 + assign $4\wr_detect$7[0:0]$11231 1'1 case - assign $4\wr_detect$7[0:0]$11350 $3\wr_detect$7[0:0]$11349 + assign $4\wr_detect$7[0:0]$11231 $3\wr_detect$7[0:0]$11230 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11351 1'1 + assign $5\wr_detect$7[0:0]$11232 1'1 case - assign $5\wr_detect$7[0:0]$11351 $4\wr_detect$7[0:0]$11350 + assign $5\wr_detect$7[0:0]$11232 $4\wr_detect$7[0:0]$11231 end case - assign $1\wr_detect$7[0:0]$11347 1'0 + assign $1\wr_detect$7[0:0]$11228 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11346 + update \wr_detect$7 $0\wr_detect$7[0:0]$11227 end - attribute \src "libresoc.v:180826.3-180858.6" - process $proc$libresoc.v:180826$11352 + attribute \src "libresoc.v:181294.3-181326.6" + process $proc$libresoc.v:181294$11233 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11353 $5\reg$next[63:0]$11358 - attribute \src "libresoc.v:180827.5-180827.29" + assign $0\reg$next[63:0]$11234 $5\reg$next[63:0]$11239 + attribute \src "libresoc.v:181295.5-181295.29" switch \initial - attribute \src "libresoc.v:180827.9-180827.17" + attribute \src "libresoc.v:181295.9-181295.17" case 1'1 case end @@ -371854,324 +337779,286 @@ module \reg_2$137 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11354 \nia2__data_i + assign $1\reg$next[63:0]$11235 \nia2__data_i case - assign $1\reg$next[63:0]$11354 \reg + assign $1\reg$next[63:0]$11235 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11355 \msr2__data_i + assign $2\reg$next[63:0]$11236 \msr2__data_i case - assign $2\reg$next[63:0]$11355 $1\reg$next[63:0]$11354 + assign $2\reg$next[63:0]$11236 $1\reg$next[63:0]$11235 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11356 \sv2__data_i + assign $3\reg$next[63:0]$11237 \sv2__data_i case - assign $3\reg$next[63:0]$11356 $2\reg$next[63:0]$11355 + assign $3\reg$next[63:0]$11237 $2\reg$next[63:0]$11236 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11357 \d_wr12__data_i + assign $4\reg$next[63:0]$11238 \d_wr12__data_i case - assign $4\reg$next[63:0]$11357 $3\reg$next[63:0]$11356 + assign $4\reg$next[63:0]$11238 $3\reg$next[63:0]$11237 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$11358 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11239 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$11358 $4\reg$next[63:0]$11357 + assign $5\reg$next[63:0]$11239 $4\reg$next[63:0]$11238 end sync always - update \reg$next $0\reg$next[63:0]$11353 + update \reg$next $0\reg$next[63:0]$11234 end - connect \$1 $not$libresoc.v:180569$11303_Y - connect \$3 $not$libresoc.v:180570$11304_Y - connect \$6 $not$libresoc.v:180571$11305_Y + connect \$1 $not$libresoc.v:181037$11184_Y + connect \$3 $not$libresoc.v:181038$11185_Y + connect \$6 $not$libresoc.v:181039$11186_Y end -attribute \src "libresoc.v:180863.1-181418.10" +attribute \src "libresoc.v:181331.1-181802.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" attribute \generator "nMigen" module \reg_3 - attribute \src "libresoc.v:180971.3-181010.6" - wire width 4 $0\cr_pred3__data_o$next[3:0]$11378 - attribute \src "libresoc.v:180969.3-180970.49" - wire width 4 $0\cr_pred3__data_o[3:0] - attribute \src "libresoc.v:180864.7-180864.20" + attribute \src "libresoc.v:181332.7-181332.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181041.3-181080.6" - wire width 4 $0\r23__data_o$next[3:0]$11387 - attribute \src "libresoc.v:180959.3-180960.39" + attribute \src "libresoc.v:181732.3-181771.6" + wire width 4 $0\r23__data_o$next[3:0]$11314 + attribute \src "libresoc.v:181415.3-181416.39" wire width 4 $0\r23__data_o[3:0] - attribute \src "libresoc.v:181348.3-181387.6" - wire width 4 $0\r3__data_o$next[3:0]$11449 - attribute \src "libresoc.v:180961.3-180962.37" + attribute \src "libresoc.v:181662.3-181701.6" + wire width 4 $0\r3__data_o$next[3:0]$11300 + attribute \src "libresoc.v:181417.3-181418.37" wire width 4 $0\r3__data_o[3:0] - attribute \src "libresoc.v:181111.3-181137.6" - wire width 4 $0\reg$next[3:0]$11401 - attribute \src "libresoc.v:180957.3-180958.25" + attribute \src "libresoc.v:181495.3-181521.6" + wire width 4 $0\reg$next[3:0]$11266 + attribute \src "libresoc.v:181413.3-181414.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:181138.3-181177.6" - wire width 4 $0\src13__data_o$next[3:0]$11407 - attribute \src "libresoc.v:180967.3-180968.43" + attribute \src "libresoc.v:181425.3-181464.6" + wire width 4 $0\src13__data_o$next[3:0]$11257 + attribute \src "libresoc.v:181423.3-181424.43" wire width 4 $0\src13__data_o[3:0] - attribute \src "libresoc.v:181208.3-181247.6" - wire width 4 $0\src23__data_o$next[3:0]$11421 - attribute \src "libresoc.v:180965.3-180966.43" + attribute \src "libresoc.v:181522.3-181561.6" + wire width 4 $0\src23__data_o$next[3:0]$11272 + attribute \src "libresoc.v:181421.3-181422.43" wire width 4 $0\src23__data_o[3:0] - attribute \src "libresoc.v:181278.3-181317.6" - wire width 4 $0\src33__data_o$next[3:0]$11435 - attribute \src "libresoc.v:180963.3-180964.43" + attribute \src "libresoc.v:181592.3-181631.6" + wire width 4 $0\src33__data_o$next[3:0]$11286 + attribute \src "libresoc.v:181419.3-181420.43" wire width 4 $0\src33__data_o[3:0] - attribute \src "libresoc.v:181318.3-181347.6" - wire $0\wr_detect$10[0:0]$11443 - attribute \src "libresoc.v:181388.3-181417.6" - wire $0\wr_detect$13[0:0]$11457 - attribute \src "libresoc.v:181081.3-181110.6" - wire $0\wr_detect$16[0:0]$11395 - attribute \src "libresoc.v:181178.3-181207.6" - wire $0\wr_detect$4[0:0]$11415 - attribute \src "libresoc.v:181248.3-181277.6" - wire $0\wr_detect$7[0:0]$11429 - attribute \src "libresoc.v:181011.3-181040.6" + attribute \src "libresoc.v:181702.3-181731.6" + wire $0\wr_detect$10[0:0]$11308 + attribute \src "libresoc.v:181772.3-181801.6" + wire $0\wr_detect$13[0:0]$11322 + attribute \src "libresoc.v:181562.3-181591.6" + wire $0\wr_detect$4[0:0]$11280 + attribute \src "libresoc.v:181632.3-181661.6" + wire $0\wr_detect$7[0:0]$11294 + attribute \src "libresoc.v:181465.3-181494.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:180971.3-181010.6" - wire width 4 $1\cr_pred3__data_o$next[3:0]$11379 - attribute \src "libresoc.v:180883.13-180883.36" - wire width 4 $1\cr_pred3__data_o[3:0] - attribute \src "libresoc.v:181041.3-181080.6" - wire width 4 $1\r23__data_o$next[3:0]$11388 - attribute \src "libresoc.v:180898.13-180898.31" + attribute \src "libresoc.v:181732.3-181771.6" + wire width 4 $1\r23__data_o$next[3:0]$11315 + attribute \src "libresoc.v:181357.13-181357.31" wire width 4 $1\r23__data_o[3:0] - attribute \src "libresoc.v:181348.3-181387.6" - wire width 4 $1\r3__data_o$next[3:0]$11450 - attribute \src "libresoc.v:180905.13-180905.30" + attribute \src "libresoc.v:181662.3-181701.6" + wire width 4 $1\r3__data_o$next[3:0]$11301 + attribute \src "libresoc.v:181364.13-181364.30" wire width 4 $1\r3__data_o[3:0] - attribute \src "libresoc.v:181111.3-181137.6" - wire width 4 $1\reg$next[3:0]$11402 - attribute \src "libresoc.v:180911.13-180911.25" + attribute \src "libresoc.v:181495.3-181521.6" + wire width 4 $1\reg$next[3:0]$11267 + attribute \src "libresoc.v:181370.13-181370.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:181138.3-181177.6" - wire width 4 $1\src13__data_o$next[3:0]$11408 - attribute \src "libresoc.v:180916.13-180916.33" + attribute \src "libresoc.v:181425.3-181464.6" + wire width 4 $1\src13__data_o$next[3:0]$11258 + attribute \src "libresoc.v:181375.13-181375.33" wire width 4 $1\src13__data_o[3:0] - attribute \src "libresoc.v:181208.3-181247.6" - wire width 4 $1\src23__data_o$next[3:0]$11422 - attribute \src "libresoc.v:180923.13-180923.33" + attribute \src "libresoc.v:181522.3-181561.6" + wire width 4 $1\src23__data_o$next[3:0]$11273 + attribute \src "libresoc.v:181382.13-181382.33" wire width 4 $1\src23__data_o[3:0] - attribute \src "libresoc.v:181278.3-181317.6" - wire width 4 $1\src33__data_o$next[3:0]$11436 - attribute \src "libresoc.v:180930.13-180930.33" + attribute \src "libresoc.v:181592.3-181631.6" + wire width 4 $1\src33__data_o$next[3:0]$11287 + attribute \src "libresoc.v:181389.13-181389.33" wire width 4 $1\src33__data_o[3:0] - attribute \src "libresoc.v:181318.3-181347.6" - wire $1\wr_detect$10[0:0]$11444 - attribute \src "libresoc.v:181388.3-181417.6" - wire $1\wr_detect$13[0:0]$11458 - attribute \src "libresoc.v:181081.3-181110.6" - wire $1\wr_detect$16[0:0]$11396 - attribute \src "libresoc.v:181178.3-181207.6" - wire $1\wr_detect$4[0:0]$11416 - attribute \src "libresoc.v:181248.3-181277.6" - wire $1\wr_detect$7[0:0]$11430 - attribute \src "libresoc.v:181011.3-181040.6" + attribute \src "libresoc.v:181702.3-181731.6" + wire $1\wr_detect$10[0:0]$11309 + attribute \src "libresoc.v:181772.3-181801.6" + wire $1\wr_detect$13[0:0]$11323 + attribute \src "libresoc.v:181562.3-181591.6" + wire $1\wr_detect$4[0:0]$11281 + attribute \src "libresoc.v:181632.3-181661.6" + wire $1\wr_detect$7[0:0]$11295 + attribute \src "libresoc.v:181465.3-181494.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:180971.3-181010.6" - wire width 4 $2\cr_pred3__data_o$next[3:0]$11380 - attribute \src "libresoc.v:181041.3-181080.6" - wire width 4 $2\r23__data_o$next[3:0]$11389 - attribute \src "libresoc.v:181348.3-181387.6" - wire width 4 $2\r3__data_o$next[3:0]$11451 - attribute \src "libresoc.v:181111.3-181137.6" - wire width 4 $2\reg$next[3:0]$11403 - attribute \src "libresoc.v:181138.3-181177.6" - wire width 4 $2\src13__data_o$next[3:0]$11409 - attribute \src "libresoc.v:181208.3-181247.6" - wire width 4 $2\src23__data_o$next[3:0]$11423 - attribute \src "libresoc.v:181278.3-181317.6" - wire width 4 $2\src33__data_o$next[3:0]$11437 - attribute \src "libresoc.v:181318.3-181347.6" - wire $2\wr_detect$10[0:0]$11445 - attribute \src "libresoc.v:181388.3-181417.6" - wire $2\wr_detect$13[0:0]$11459 - attribute \src "libresoc.v:181081.3-181110.6" - wire $2\wr_detect$16[0:0]$11397 - attribute \src "libresoc.v:181178.3-181207.6" - wire $2\wr_detect$4[0:0]$11417 - attribute \src "libresoc.v:181248.3-181277.6" - wire $2\wr_detect$7[0:0]$11431 - attribute \src "libresoc.v:181011.3-181040.6" + attribute \src "libresoc.v:181732.3-181771.6" + wire width 4 $2\r23__data_o$next[3:0]$11316 + attribute \src "libresoc.v:181662.3-181701.6" + wire width 4 $2\r3__data_o$next[3:0]$11302 + attribute \src "libresoc.v:181495.3-181521.6" + wire width 4 $2\reg$next[3:0]$11268 + attribute \src "libresoc.v:181425.3-181464.6" + wire width 4 $2\src13__data_o$next[3:0]$11259 + attribute \src "libresoc.v:181522.3-181561.6" + wire width 4 $2\src23__data_o$next[3:0]$11274 + attribute \src "libresoc.v:181592.3-181631.6" + wire width 4 $2\src33__data_o$next[3:0]$11288 + attribute \src "libresoc.v:181702.3-181731.6" + wire $2\wr_detect$10[0:0]$11310 + attribute \src "libresoc.v:181772.3-181801.6" + wire $2\wr_detect$13[0:0]$11324 + attribute \src "libresoc.v:181562.3-181591.6" + wire $2\wr_detect$4[0:0]$11282 + attribute \src "libresoc.v:181632.3-181661.6" + wire $2\wr_detect$7[0:0]$11296 + attribute \src "libresoc.v:181465.3-181494.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:180971.3-181010.6" - wire width 4 $3\cr_pred3__data_o$next[3:0]$11381 - attribute \src "libresoc.v:181041.3-181080.6" - wire width 4 $3\r23__data_o$next[3:0]$11390 - attribute \src "libresoc.v:181348.3-181387.6" - wire width 4 $3\r3__data_o$next[3:0]$11452 - attribute \src "libresoc.v:181111.3-181137.6" - wire width 4 $3\reg$next[3:0]$11404 - attribute \src "libresoc.v:181138.3-181177.6" - wire width 4 $3\src13__data_o$next[3:0]$11410 - attribute \src "libresoc.v:181208.3-181247.6" - wire width 4 $3\src23__data_o$next[3:0]$11424 - attribute \src "libresoc.v:181278.3-181317.6" - wire width 4 $3\src33__data_o$next[3:0]$11438 - attribute \src "libresoc.v:181318.3-181347.6" - wire $3\wr_detect$10[0:0]$11446 - attribute \src "libresoc.v:181388.3-181417.6" - wire $3\wr_detect$13[0:0]$11460 - attribute \src "libresoc.v:181081.3-181110.6" - wire $3\wr_detect$16[0:0]$11398 - attribute \src "libresoc.v:181178.3-181207.6" - wire $3\wr_detect$4[0:0]$11418 - attribute \src "libresoc.v:181248.3-181277.6" - wire $3\wr_detect$7[0:0]$11432 - attribute \src "libresoc.v:181011.3-181040.6" + attribute \src "libresoc.v:181732.3-181771.6" + wire width 4 $3\r23__data_o$next[3:0]$11317 + attribute \src "libresoc.v:181662.3-181701.6" + wire width 4 $3\r3__data_o$next[3:0]$11303 + attribute \src "libresoc.v:181495.3-181521.6" + wire width 4 $3\reg$next[3:0]$11269 + attribute \src "libresoc.v:181425.3-181464.6" + wire width 4 $3\src13__data_o$next[3:0]$11260 + attribute \src "libresoc.v:181522.3-181561.6" + wire width 4 $3\src23__data_o$next[3:0]$11275 + attribute \src "libresoc.v:181592.3-181631.6" + wire width 4 $3\src33__data_o$next[3:0]$11289 + attribute \src "libresoc.v:181702.3-181731.6" + wire $3\wr_detect$10[0:0]$11311 + attribute \src "libresoc.v:181772.3-181801.6" + wire $3\wr_detect$13[0:0]$11325 + attribute \src "libresoc.v:181562.3-181591.6" + wire $3\wr_detect$4[0:0]$11283 + attribute \src "libresoc.v:181632.3-181661.6" + wire $3\wr_detect$7[0:0]$11297 + attribute \src "libresoc.v:181465.3-181494.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:180971.3-181010.6" - wire width 4 $4\cr_pred3__data_o$next[3:0]$11382 - attribute \src "libresoc.v:181041.3-181080.6" - wire width 4 $4\r23__data_o$next[3:0]$11391 - attribute \src "libresoc.v:181348.3-181387.6" - wire width 4 $4\r3__data_o$next[3:0]$11453 - attribute \src "libresoc.v:181111.3-181137.6" - wire width 4 $4\reg$next[3:0]$11405 - attribute \src "libresoc.v:181138.3-181177.6" - wire width 4 $4\src13__data_o$next[3:0]$11411 - attribute \src "libresoc.v:181208.3-181247.6" - wire width 4 $4\src23__data_o$next[3:0]$11425 - attribute \src "libresoc.v:181278.3-181317.6" - wire width 4 $4\src33__data_o$next[3:0]$11439 - attribute \src "libresoc.v:181318.3-181347.6" - wire $4\wr_detect$10[0:0]$11447 - attribute \src "libresoc.v:181388.3-181417.6" - wire $4\wr_detect$13[0:0]$11461 - attribute \src "libresoc.v:181081.3-181110.6" - wire $4\wr_detect$16[0:0]$11399 - attribute \src "libresoc.v:181178.3-181207.6" - wire $4\wr_detect$4[0:0]$11419 - attribute \src "libresoc.v:181248.3-181277.6" - wire $4\wr_detect$7[0:0]$11433 - attribute \src "libresoc.v:181011.3-181040.6" + attribute \src "libresoc.v:181732.3-181771.6" + wire width 4 $4\r23__data_o$next[3:0]$11318 + attribute \src "libresoc.v:181662.3-181701.6" + wire width 4 $4\r3__data_o$next[3:0]$11304 + attribute \src "libresoc.v:181495.3-181521.6" + wire width 4 $4\reg$next[3:0]$11270 + attribute \src "libresoc.v:181425.3-181464.6" + wire width 4 $4\src13__data_o$next[3:0]$11261 + attribute \src "libresoc.v:181522.3-181561.6" + wire width 4 $4\src23__data_o$next[3:0]$11276 + attribute \src "libresoc.v:181592.3-181631.6" + wire width 4 $4\src33__data_o$next[3:0]$11290 + attribute \src "libresoc.v:181702.3-181731.6" + wire $4\wr_detect$10[0:0]$11312 + attribute \src "libresoc.v:181772.3-181801.6" + wire $4\wr_detect$13[0:0]$11326 + attribute \src "libresoc.v:181562.3-181591.6" + wire $4\wr_detect$4[0:0]$11284 + attribute \src "libresoc.v:181632.3-181661.6" + wire $4\wr_detect$7[0:0]$11298 + attribute \src "libresoc.v:181465.3-181494.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:180971.3-181010.6" - wire width 4 $5\cr_pred3__data_o$next[3:0]$11383 - attribute \src "libresoc.v:181041.3-181080.6" - wire width 4 $5\r23__data_o$next[3:0]$11392 - attribute \src "libresoc.v:181348.3-181387.6" - wire width 4 $5\r3__data_o$next[3:0]$11454 - attribute \src "libresoc.v:181138.3-181177.6" - wire width 4 $5\src13__data_o$next[3:0]$11412 - attribute \src "libresoc.v:181208.3-181247.6" - wire width 4 $5\src23__data_o$next[3:0]$11426 - attribute \src "libresoc.v:181278.3-181317.6" - wire width 4 $5\src33__data_o$next[3:0]$11440 - attribute \src "libresoc.v:180971.3-181010.6" - wire width 4 $6\cr_pred3__data_o$next[3:0]$11384 - attribute \src "libresoc.v:181041.3-181080.6" - wire width 4 $6\r23__data_o$next[3:0]$11393 - attribute \src "libresoc.v:181348.3-181387.6" - wire width 4 $6\r3__data_o$next[3:0]$11455 - attribute \src "libresoc.v:181138.3-181177.6" - wire width 4 $6\src13__data_o$next[3:0]$11413 - attribute \src "libresoc.v:181208.3-181247.6" - wire width 4 $6\src23__data_o$next[3:0]$11427 - attribute \src "libresoc.v:181278.3-181317.6" - wire width 4 $6\src33__data_o$next[3:0]$11441 - attribute \src "libresoc.v:180951.17-180951.104" - wire $not$libresoc.v:180951$11364_Y - attribute \src "libresoc.v:180952.18-180952.105" - wire $not$libresoc.v:180952$11365_Y - attribute \src "libresoc.v:180953.18-180953.105" - wire $not$libresoc.v:180953$11366_Y - attribute \src "libresoc.v:180954.17-180954.100" - wire $not$libresoc.v:180954$11367_Y - attribute \src "libresoc.v:180955.17-180955.103" - wire $not$libresoc.v:180955$11368_Y - attribute \src "libresoc.v:180956.17-180956.103" - wire $not$libresoc.v:180956$11369_Y + attribute \src "libresoc.v:181732.3-181771.6" + wire width 4 $5\r23__data_o$next[3:0]$11319 + attribute \src "libresoc.v:181662.3-181701.6" + wire width 4 $5\r3__data_o$next[3:0]$11305 + attribute \src "libresoc.v:181425.3-181464.6" + wire width 4 $5\src13__data_o$next[3:0]$11262 + attribute \src "libresoc.v:181522.3-181561.6" + wire width 4 $5\src23__data_o$next[3:0]$11277 + attribute \src "libresoc.v:181592.3-181631.6" + wire width 4 $5\src33__data_o$next[3:0]$11291 + attribute \src "libresoc.v:181732.3-181771.6" + wire width 4 $6\r23__data_o$next[3:0]$11320 + attribute \src "libresoc.v:181662.3-181701.6" + wire width 4 $6\r3__data_o$next[3:0]$11306 + attribute \src "libresoc.v:181425.3-181464.6" + wire width 4 $6\src13__data_o$next[3:0]$11263 + attribute \src "libresoc.v:181522.3-181561.6" + wire width 4 $6\src23__data_o$next[3:0]$11278 + attribute \src "libresoc.v:181592.3-181631.6" + wire width 4 $6\src33__data_o$next[3:0]$11292 + attribute \src "libresoc.v:181408.17-181408.104" + wire $not$libresoc.v:181408$11245_Y + attribute \src "libresoc.v:181409.18-181409.105" + wire $not$libresoc.v:181409$11246_Y + attribute \src "libresoc.v:181410.17-181410.100" + wire $not$libresoc.v:181410$11247_Y + attribute \src "libresoc.v:181411.17-181411.103" + wire $not$libresoc.v:181411$11248_Y + attribute \src "libresoc.v:181412.17-181412.103" + wire $not$libresoc.v:181412$11249_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" - wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \cr_pred3__data_o + wire width 4 input 9 \dest13__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \cr_pred3__data_o$next + wire input 8 \dest13__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \cr_pred3__ren + wire width 4 input 11 \dest23__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest13__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 13 \dest23__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 12 \dest23__wen - attribute \src "libresoc.v:180864.7-180864.15" + wire input 10 \dest23__wen + attribute \src "libresoc.v:181332.7-181332.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 16 \r23__data_o + wire width 4 output 14 \r23__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r23__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \r23__ren + wire input 15 \r23__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r3__data_o + wire width 4 output 12 \r3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r3__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r3__ren + wire input 13 \r3__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src13__data_o + wire width 4 output 3 \src13__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src13__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src13__ren + wire input 2 \src13__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src23__data_o + wire width 4 output 5 \src23__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src23__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src23__ren + wire input 4 \src23__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 9 \src33__data_o + wire width 4 output 7 \src33__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src33__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \src33__ren + wire input 6 \src33__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 18 \w3__data_i + wire width 4 input 16 \w3__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 19 \w3__wen + wire input 17 \w3__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -372179,257 +338066,232 @@ module \reg_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180951$11364 + cell $not $not$libresoc.v:181408$11245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:180951$11364_Y + connect \Y $not$libresoc.v:181408$11245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180952$11365 + cell $not $not$libresoc.v:181409$11246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:180952$11365_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180953$11366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$16 - connect \Y $not$libresoc.v:180953$11366_Y + connect \Y $not$libresoc.v:181409$11246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180954$11367 + cell $not $not$libresoc.v:181410$11247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180954$11367_Y + connect \Y $not$libresoc.v:181410$11247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180955$11368 + cell $not $not$libresoc.v:181411$11248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180955$11368_Y + connect \Y $not$libresoc.v:181411$11248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180956$11369 + cell $not $not$libresoc.v:181412$11249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180956$11369_Y + connect \Y $not$libresoc.v:181412$11249_Y end - attribute \src "libresoc.v:180864.7-180864.20" - process $proc$libresoc.v:180864$11462 + attribute \src "libresoc.v:181332.7-181332.20" + process $proc$libresoc.v:181332$11327 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180883.13-180883.36" - process $proc$libresoc.v:180883$11463 - assign { } { } - assign $1\cr_pred3__data_o[3:0] 4'0000 - sync always - sync init - update \cr_pred3__data_o $1\cr_pred3__data_o[3:0] - end - attribute \src "libresoc.v:180898.13-180898.31" - process $proc$libresoc.v:180898$11464 + attribute \src "libresoc.v:181357.13-181357.31" + process $proc$libresoc.v:181357$11328 assign { } { } assign $1\r23__data_o[3:0] 4'0000 sync always sync init update \r23__data_o $1\r23__data_o[3:0] end - attribute \src "libresoc.v:180905.13-180905.30" - process $proc$libresoc.v:180905$11465 + attribute \src "libresoc.v:181364.13-181364.30" + process $proc$libresoc.v:181364$11329 assign { } { } assign $1\r3__data_o[3:0] 4'0000 sync always sync init update \r3__data_o $1\r3__data_o[3:0] end - attribute \src "libresoc.v:180911.13-180911.25" - process $proc$libresoc.v:180911$11466 + attribute \src "libresoc.v:181370.13-181370.25" + process $proc$libresoc.v:181370$11330 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:180916.13-180916.33" - process $proc$libresoc.v:180916$11467 + attribute \src "libresoc.v:181375.13-181375.33" + process $proc$libresoc.v:181375$11331 assign { } { } assign $1\src13__data_o[3:0] 4'0000 sync always sync init update \src13__data_o $1\src13__data_o[3:0] end - attribute \src "libresoc.v:180923.13-180923.33" - process $proc$libresoc.v:180923$11468 + attribute \src "libresoc.v:181382.13-181382.33" + process $proc$libresoc.v:181382$11332 assign { } { } assign $1\src23__data_o[3:0] 4'0000 sync always sync init update \src23__data_o $1\src23__data_o[3:0] end - attribute \src "libresoc.v:180930.13-180930.33" - process $proc$libresoc.v:180930$11469 + attribute \src "libresoc.v:181389.13-181389.33" + process $proc$libresoc.v:181389$11333 assign { } { } assign $1\src33__data_o[3:0] 4'0000 sync always sync init update \src33__data_o $1\src33__data_o[3:0] end - attribute \src "libresoc.v:180957.3-180958.25" - process $proc$libresoc.v:180957$11370 + attribute \src "libresoc.v:181413.3-181414.25" + process $proc$libresoc.v:181413$11250 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:180959.3-180960.39" - process $proc$libresoc.v:180959$11371 + attribute \src "libresoc.v:181415.3-181416.39" + process $proc$libresoc.v:181415$11251 assign { } { } assign $0\r23__data_o[3:0] \r23__data_o$next sync posedge \coresync_clk update \r23__data_o $0\r23__data_o[3:0] end - attribute \src "libresoc.v:180961.3-180962.37" - process $proc$libresoc.v:180961$11372 + attribute \src "libresoc.v:181417.3-181418.37" + process $proc$libresoc.v:181417$11252 assign { } { } assign $0\r3__data_o[3:0] \r3__data_o$next sync posedge \coresync_clk update \r3__data_o $0\r3__data_o[3:0] end - attribute \src "libresoc.v:180963.3-180964.43" - process $proc$libresoc.v:180963$11373 + attribute \src "libresoc.v:181419.3-181420.43" + process $proc$libresoc.v:181419$11253 assign { } { } assign $0\src33__data_o[3:0] \src33__data_o$next sync posedge \coresync_clk update \src33__data_o $0\src33__data_o[3:0] end - attribute \src "libresoc.v:180965.3-180966.43" - process $proc$libresoc.v:180965$11374 + attribute \src "libresoc.v:181421.3-181422.43" + process $proc$libresoc.v:181421$11254 assign { } { } assign $0\src23__data_o[3:0] \src23__data_o$next sync posedge \coresync_clk update \src23__data_o $0\src23__data_o[3:0] end - attribute \src "libresoc.v:180967.3-180968.43" - process $proc$libresoc.v:180967$11375 + attribute \src "libresoc.v:181423.3-181424.43" + process $proc$libresoc.v:181423$11255 assign { } { } assign $0\src13__data_o[3:0] \src13__data_o$next sync posedge \coresync_clk update \src13__data_o $0\src13__data_o[3:0] end - attribute \src "libresoc.v:180969.3-180970.49" - process $proc$libresoc.v:180969$11376 - assign { } { } - assign $0\cr_pred3__data_o[3:0] \cr_pred3__data_o$next - sync posedge \coresync_clk - update \cr_pred3__data_o $0\cr_pred3__data_o[3:0] - end - attribute \src "libresoc.v:180971.3-181010.6" - process $proc$libresoc.v:180971$11377 + attribute \src "libresoc.v:181425.3-181464.6" + process $proc$libresoc.v:181425$11256 assign { } { } assign { } { } assign { } { } - assign $0\cr_pred3__data_o$next[3:0]$11378 $6\cr_pred3__data_o$next[3:0]$11384 - attribute \src "libresoc.v:180972.5-180972.29" + assign $0\src13__data_o$next[3:0]$11257 $6\src13__data_o$next[3:0]$11263 + attribute \src "libresoc.v:181426.5-181426.29" switch \initial - attribute \src "libresoc.v:180972.9-180972.17" + attribute \src "libresoc.v:181426.9-181426.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred3__ren + switch \src13__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\cr_pred3__data_o$next[3:0]$11379 $5\cr_pred3__data_o$next[3:0]$11383 + assign $1\src13__data_o$next[3:0]$11258 $5\src13__data_o$next[3:0]$11262 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred3__data_o$next[3:0]$11380 \dest13__data_i + assign $2\src13__data_o$next[3:0]$11259 \dest13__data_i case - assign $2\cr_pred3__data_o$next[3:0]$11380 4'0000 + assign $2\src13__data_o$next[3:0]$11259 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred3__data_o$next[3:0]$11381 \dest23__data_i + assign $3\src13__data_o$next[3:0]$11260 \dest23__data_i case - assign $3\cr_pred3__data_o$next[3:0]$11381 $2\cr_pred3__data_o$next[3:0]$11380 + assign $3\src13__data_o$next[3:0]$11260 $2\src13__data_o$next[3:0]$11259 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred3__data_o$next[3:0]$11382 \w3__data_i + assign $4\src13__data_o$next[3:0]$11261 \w3__data_i case - assign $4\cr_pred3__data_o$next[3:0]$11382 $3\cr_pred3__data_o$next[3:0]$11381 + assign $4\src13__data_o$next[3:0]$11261 $3\src13__data_o$next[3:0]$11260 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred3__data_o$next[3:0]$11383 \reg + assign $5\src13__data_o$next[3:0]$11262 \reg case - assign $5\cr_pred3__data_o$next[3:0]$11383 $4\cr_pred3__data_o$next[3:0]$11382 + assign $5\src13__data_o$next[3:0]$11262 $4\src13__data_o$next[3:0]$11261 end case - assign $1\cr_pred3__data_o$next[3:0]$11379 4'0000 + assign $1\src13__data_o$next[3:0]$11258 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred3__data_o$next[3:0]$11384 4'0000 + assign $6\src13__data_o$next[3:0]$11263 4'0000 case - assign $6\cr_pred3__data_o$next[3:0]$11384 $1\cr_pred3__data_o$next[3:0]$11379 + assign $6\src13__data_o$next[3:0]$11263 $1\src13__data_o$next[3:0]$11258 end sync always - update \cr_pred3__data_o$next $0\cr_pred3__data_o$next[3:0]$11378 + update \src13__data_o$next $0\src13__data_o$next[3:0]$11257 end - attribute \src "libresoc.v:181011.3-181040.6" - process $proc$libresoc.v:181011$11385 + attribute \src "libresoc.v:181465.3-181494.6" + process $proc$libresoc.v:181465$11264 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:181012.5-181012.29" + attribute \src "libresoc.v:181466.5-181466.29" switch \initial - attribute \src "libresoc.v:181012.9-181012.17" + attribute \src "libresoc.v:181466.9-181466.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred3__ren + switch \src13__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -372470,142 +338332,17 @@ module \reg_3 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:181041.3-181080.6" - process $proc$libresoc.v:181041$11386 - assign { } { } - assign { } { } - assign { } { } - assign $0\r23__data_o$next[3:0]$11387 $6\r23__data_o$next[3:0]$11393 - attribute \src "libresoc.v:181042.5-181042.29" - switch \initial - attribute \src "libresoc.v:181042.9-181042.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r23__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r23__data_o$next[3:0]$11388 $5\r23__data_o$next[3:0]$11392 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r23__data_o$next[3:0]$11389 \dest13__data_i - case - assign $2\r23__data_o$next[3:0]$11389 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r23__data_o$next[3:0]$11390 \dest23__data_i - case - assign $3\r23__data_o$next[3:0]$11390 $2\r23__data_o$next[3:0]$11389 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r23__data_o$next[3:0]$11391 \w3__data_i - case - assign $4\r23__data_o$next[3:0]$11391 $3\r23__data_o$next[3:0]$11390 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r23__data_o$next[3:0]$11392 \reg - case - assign $5\r23__data_o$next[3:0]$11392 $4\r23__data_o$next[3:0]$11391 - end - case - assign $1\r23__data_o$next[3:0]$11388 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r23__data_o$next[3:0]$11393 4'0000 - case - assign $6\r23__data_o$next[3:0]$11393 $1\r23__data_o$next[3:0]$11388 - end - sync always - update \r23__data_o$next $0\r23__data_o$next[3:0]$11387 - end - attribute \src "libresoc.v:181081.3-181110.6" - process $proc$libresoc.v:181081$11394 + attribute \src "libresoc.v:181495.3-181521.6" + process $proc$libresoc.v:181495$11265 assign { } { } - assign { } { } - assign $0\wr_detect$16[0:0]$11395 $1\wr_detect$16[0:0]$11396 - attribute \src "libresoc.v:181082.5-181082.29" - switch \initial - attribute \src "libresoc.v:181082.9-181082.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r23__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$16[0:0]$11396 $4\wr_detect$16[0:0]$11399 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$16[0:0]$11397 1'1 - case - assign $2\wr_detect$16[0:0]$11397 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$16[0:0]$11398 1'1 - case - assign $3\wr_detect$16[0:0]$11398 $2\wr_detect$16[0:0]$11397 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$16[0:0]$11399 1'1 - case - assign $4\wr_detect$16[0:0]$11399 $3\wr_detect$16[0:0]$11398 - end - case - assign $1\wr_detect$16[0:0]$11396 1'0 - end - sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$11395 - end - attribute \src "libresoc.v:181111.3-181137.6" - process $proc$libresoc.v:181111$11400 assign { } { } assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\reg$next[3:0]$11401 $4\reg$next[3:0]$11405 - attribute \src "libresoc.v:181112.5-181112.29" + assign $0\reg$next[3:0]$11266 $4\reg$next[3:0]$11270 + attribute \src "libresoc.v:181496.5-181496.29" switch \initial - attribute \src "libresoc.v:181112.9-181112.17" + attribute \src "libresoc.v:181496.9-181496.17" case 1'1 case end @@ -372614,818 +338351,779 @@ module \reg_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11402 \dest13__data_i + assign $1\reg$next[3:0]$11267 \dest13__data_i case - assign $1\reg$next[3:0]$11402 \reg + assign $1\reg$next[3:0]$11267 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11403 \dest23__data_i + assign $2\reg$next[3:0]$11268 \dest23__data_i case - assign $2\reg$next[3:0]$11403 $1\reg$next[3:0]$11402 + assign $2\reg$next[3:0]$11268 $1\reg$next[3:0]$11267 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11404 \w3__data_i + assign $3\reg$next[3:0]$11269 \w3__data_i case - assign $3\reg$next[3:0]$11404 $2\reg$next[3:0]$11403 + assign $3\reg$next[3:0]$11269 $2\reg$next[3:0]$11268 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11405 4'0000 + assign $4\reg$next[3:0]$11270 4'0000 case - assign $4\reg$next[3:0]$11405 $3\reg$next[3:0]$11404 + assign $4\reg$next[3:0]$11270 $3\reg$next[3:0]$11269 end sync always - update \reg$next $0\reg$next[3:0]$11401 + update \reg$next $0\reg$next[3:0]$11266 end - attribute \src "libresoc.v:181138.3-181177.6" - process $proc$libresoc.v:181138$11406 + attribute \src "libresoc.v:181522.3-181561.6" + process $proc$libresoc.v:181522$11271 assign { } { } assign { } { } assign { } { } - assign $0\src13__data_o$next[3:0]$11407 $6\src13__data_o$next[3:0]$11413 - attribute \src "libresoc.v:181139.5-181139.29" + assign $0\src23__data_o$next[3:0]$11272 $6\src23__data_o$next[3:0]$11278 + attribute \src "libresoc.v:181523.5-181523.29" switch \initial - attribute \src "libresoc.v:181139.9-181139.17" + attribute \src "libresoc.v:181523.9-181523.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src13__ren + switch \src23__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src13__data_o$next[3:0]$11408 $5\src13__data_o$next[3:0]$11412 + assign $1\src23__data_o$next[3:0]$11273 $5\src23__data_o$next[3:0]$11277 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src13__data_o$next[3:0]$11409 \dest13__data_i + assign $2\src23__data_o$next[3:0]$11274 \dest13__data_i case - assign $2\src13__data_o$next[3:0]$11409 4'0000 + assign $2\src23__data_o$next[3:0]$11274 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src13__data_o$next[3:0]$11410 \dest23__data_i + assign $3\src23__data_o$next[3:0]$11275 \dest23__data_i case - assign $3\src13__data_o$next[3:0]$11410 $2\src13__data_o$next[3:0]$11409 + assign $3\src23__data_o$next[3:0]$11275 $2\src23__data_o$next[3:0]$11274 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src13__data_o$next[3:0]$11411 \w3__data_i + assign $4\src23__data_o$next[3:0]$11276 \w3__data_i case - assign $4\src13__data_o$next[3:0]$11411 $3\src13__data_o$next[3:0]$11410 + assign $4\src23__data_o$next[3:0]$11276 $3\src23__data_o$next[3:0]$11275 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src13__data_o$next[3:0]$11412 \reg + assign $5\src23__data_o$next[3:0]$11277 \reg case - assign $5\src13__data_o$next[3:0]$11412 $4\src13__data_o$next[3:0]$11411 + assign $5\src23__data_o$next[3:0]$11277 $4\src23__data_o$next[3:0]$11276 end case - assign $1\src13__data_o$next[3:0]$11408 4'0000 + assign $1\src23__data_o$next[3:0]$11273 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src13__data_o$next[3:0]$11413 4'0000 + assign $6\src23__data_o$next[3:0]$11278 4'0000 case - assign $6\src13__data_o$next[3:0]$11413 $1\src13__data_o$next[3:0]$11408 + assign $6\src23__data_o$next[3:0]$11278 $1\src23__data_o$next[3:0]$11273 end sync always - update \src13__data_o$next $0\src13__data_o$next[3:0]$11407 + update \src23__data_o$next $0\src23__data_o$next[3:0]$11272 end - attribute \src "libresoc.v:181178.3-181207.6" - process $proc$libresoc.v:181178$11414 + attribute \src "libresoc.v:181562.3-181591.6" + process $proc$libresoc.v:181562$11279 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11415 $1\wr_detect$4[0:0]$11416 - attribute \src "libresoc.v:181179.5-181179.29" + assign $0\wr_detect$4[0:0]$11280 $1\wr_detect$4[0:0]$11281 + attribute \src "libresoc.v:181563.5-181563.29" switch \initial - attribute \src "libresoc.v:181179.9-181179.17" + attribute \src "libresoc.v:181563.9-181563.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src13__ren + switch \src23__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11416 $4\wr_detect$4[0:0]$11419 + assign $1\wr_detect$4[0:0]$11281 $4\wr_detect$4[0:0]$11284 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11417 1'1 + assign $2\wr_detect$4[0:0]$11282 1'1 case - assign $2\wr_detect$4[0:0]$11417 1'0 + assign $2\wr_detect$4[0:0]$11282 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11418 1'1 + assign $3\wr_detect$4[0:0]$11283 1'1 case - assign $3\wr_detect$4[0:0]$11418 $2\wr_detect$4[0:0]$11417 + assign $3\wr_detect$4[0:0]$11283 $2\wr_detect$4[0:0]$11282 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11419 1'1 + assign $4\wr_detect$4[0:0]$11284 1'1 case - assign $4\wr_detect$4[0:0]$11419 $3\wr_detect$4[0:0]$11418 + assign $4\wr_detect$4[0:0]$11284 $3\wr_detect$4[0:0]$11283 end case - assign $1\wr_detect$4[0:0]$11416 1'0 + assign $1\wr_detect$4[0:0]$11281 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11415 + update \wr_detect$4 $0\wr_detect$4[0:0]$11280 end - attribute \src "libresoc.v:181208.3-181247.6" - process $proc$libresoc.v:181208$11420 + attribute \src "libresoc.v:181592.3-181631.6" + process $proc$libresoc.v:181592$11285 assign { } { } assign { } { } assign { } { } - assign $0\src23__data_o$next[3:0]$11421 $6\src23__data_o$next[3:0]$11427 - attribute \src "libresoc.v:181209.5-181209.29" + assign $0\src33__data_o$next[3:0]$11286 $6\src33__data_o$next[3:0]$11292 + attribute \src "libresoc.v:181593.5-181593.29" switch \initial - attribute \src "libresoc.v:181209.9-181209.17" + attribute \src "libresoc.v:181593.9-181593.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src23__ren + switch \src33__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src23__data_o$next[3:0]$11422 $5\src23__data_o$next[3:0]$11426 + assign $1\src33__data_o$next[3:0]$11287 $5\src33__data_o$next[3:0]$11291 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src23__data_o$next[3:0]$11423 \dest13__data_i + assign $2\src33__data_o$next[3:0]$11288 \dest13__data_i case - assign $2\src23__data_o$next[3:0]$11423 4'0000 + assign $2\src33__data_o$next[3:0]$11288 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src23__data_o$next[3:0]$11424 \dest23__data_i + assign $3\src33__data_o$next[3:0]$11289 \dest23__data_i case - assign $3\src23__data_o$next[3:0]$11424 $2\src23__data_o$next[3:0]$11423 + assign $3\src33__data_o$next[3:0]$11289 $2\src33__data_o$next[3:0]$11288 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src23__data_o$next[3:0]$11425 \w3__data_i + assign $4\src33__data_o$next[3:0]$11290 \w3__data_i case - assign $4\src23__data_o$next[3:0]$11425 $3\src23__data_o$next[3:0]$11424 + assign $4\src33__data_o$next[3:0]$11290 $3\src33__data_o$next[3:0]$11289 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src23__data_o$next[3:0]$11426 \reg + assign $5\src33__data_o$next[3:0]$11291 \reg case - assign $5\src23__data_o$next[3:0]$11426 $4\src23__data_o$next[3:0]$11425 + assign $5\src33__data_o$next[3:0]$11291 $4\src33__data_o$next[3:0]$11290 end case - assign $1\src23__data_o$next[3:0]$11422 4'0000 + assign $1\src33__data_o$next[3:0]$11287 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src23__data_o$next[3:0]$11427 4'0000 + assign $6\src33__data_o$next[3:0]$11292 4'0000 case - assign $6\src23__data_o$next[3:0]$11427 $1\src23__data_o$next[3:0]$11422 + assign $6\src33__data_o$next[3:0]$11292 $1\src33__data_o$next[3:0]$11287 end sync always - update \src23__data_o$next $0\src23__data_o$next[3:0]$11421 + update \src33__data_o$next $0\src33__data_o$next[3:0]$11286 end - attribute \src "libresoc.v:181248.3-181277.6" - process $proc$libresoc.v:181248$11428 + attribute \src "libresoc.v:181632.3-181661.6" + process $proc$libresoc.v:181632$11293 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11429 $1\wr_detect$7[0:0]$11430 - attribute \src "libresoc.v:181249.5-181249.29" + assign $0\wr_detect$7[0:0]$11294 $1\wr_detect$7[0:0]$11295 + attribute \src "libresoc.v:181633.5-181633.29" switch \initial - attribute \src "libresoc.v:181249.9-181249.17" + attribute \src "libresoc.v:181633.9-181633.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src23__ren + switch \src33__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11430 $4\wr_detect$7[0:0]$11433 + assign $1\wr_detect$7[0:0]$11295 $4\wr_detect$7[0:0]$11298 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11431 1'1 + assign $2\wr_detect$7[0:0]$11296 1'1 case - assign $2\wr_detect$7[0:0]$11431 1'0 + assign $2\wr_detect$7[0:0]$11296 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11432 1'1 + assign $3\wr_detect$7[0:0]$11297 1'1 case - assign $3\wr_detect$7[0:0]$11432 $2\wr_detect$7[0:0]$11431 + assign $3\wr_detect$7[0:0]$11297 $2\wr_detect$7[0:0]$11296 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11433 1'1 + assign $4\wr_detect$7[0:0]$11298 1'1 case - assign $4\wr_detect$7[0:0]$11433 $3\wr_detect$7[0:0]$11432 + assign $4\wr_detect$7[0:0]$11298 $3\wr_detect$7[0:0]$11297 end case - assign $1\wr_detect$7[0:0]$11430 1'0 + assign $1\wr_detect$7[0:0]$11295 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11429 + update \wr_detect$7 $0\wr_detect$7[0:0]$11294 end - attribute \src "libresoc.v:181278.3-181317.6" - process $proc$libresoc.v:181278$11434 + attribute \src "libresoc.v:181662.3-181701.6" + process $proc$libresoc.v:181662$11299 assign { } { } assign { } { } assign { } { } - assign $0\src33__data_o$next[3:0]$11435 $6\src33__data_o$next[3:0]$11441 - attribute \src "libresoc.v:181279.5-181279.29" + assign $0\r3__data_o$next[3:0]$11300 $6\r3__data_o$next[3:0]$11306 + attribute \src "libresoc.v:181663.5-181663.29" switch \initial - attribute \src "libresoc.v:181279.9-181279.17" + attribute \src "libresoc.v:181663.9-181663.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src33__ren + switch \r3__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src33__data_o$next[3:0]$11436 $5\src33__data_o$next[3:0]$11440 + assign $1\r3__data_o$next[3:0]$11301 $5\r3__data_o$next[3:0]$11305 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src33__data_o$next[3:0]$11437 \dest13__data_i + assign $2\r3__data_o$next[3:0]$11302 \dest13__data_i case - assign $2\src33__data_o$next[3:0]$11437 4'0000 + assign $2\r3__data_o$next[3:0]$11302 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src33__data_o$next[3:0]$11438 \dest23__data_i + assign $3\r3__data_o$next[3:0]$11303 \dest23__data_i case - assign $3\src33__data_o$next[3:0]$11438 $2\src33__data_o$next[3:0]$11437 + assign $3\r3__data_o$next[3:0]$11303 $2\r3__data_o$next[3:0]$11302 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src33__data_o$next[3:0]$11439 \w3__data_i + assign $4\r3__data_o$next[3:0]$11304 \w3__data_i case - assign $4\src33__data_o$next[3:0]$11439 $3\src33__data_o$next[3:0]$11438 + assign $4\r3__data_o$next[3:0]$11304 $3\r3__data_o$next[3:0]$11303 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src33__data_o$next[3:0]$11440 \reg + assign $5\r3__data_o$next[3:0]$11305 \reg case - assign $5\src33__data_o$next[3:0]$11440 $4\src33__data_o$next[3:0]$11439 + assign $5\r3__data_o$next[3:0]$11305 $4\r3__data_o$next[3:0]$11304 end case - assign $1\src33__data_o$next[3:0]$11436 4'0000 + assign $1\r3__data_o$next[3:0]$11301 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src33__data_o$next[3:0]$11441 4'0000 + assign $6\r3__data_o$next[3:0]$11306 4'0000 case - assign $6\src33__data_o$next[3:0]$11441 $1\src33__data_o$next[3:0]$11436 + assign $6\r3__data_o$next[3:0]$11306 $1\r3__data_o$next[3:0]$11301 end sync always - update \src33__data_o$next $0\src33__data_o$next[3:0]$11435 + update \r3__data_o$next $0\r3__data_o$next[3:0]$11300 end - attribute \src "libresoc.v:181318.3-181347.6" - process $proc$libresoc.v:181318$11442 + attribute \src "libresoc.v:181702.3-181731.6" + process $proc$libresoc.v:181702$11307 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11443 $1\wr_detect$10[0:0]$11444 - attribute \src "libresoc.v:181319.5-181319.29" + assign $0\wr_detect$10[0:0]$11308 $1\wr_detect$10[0:0]$11309 + attribute \src "libresoc.v:181703.5-181703.29" switch \initial - attribute \src "libresoc.v:181319.9-181319.17" + attribute \src "libresoc.v:181703.9-181703.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src33__ren + switch \r3__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11444 $4\wr_detect$10[0:0]$11447 + assign $1\wr_detect$10[0:0]$11309 $4\wr_detect$10[0:0]$11312 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11445 1'1 + assign $2\wr_detect$10[0:0]$11310 1'1 case - assign $2\wr_detect$10[0:0]$11445 1'0 + assign $2\wr_detect$10[0:0]$11310 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11446 1'1 + assign $3\wr_detect$10[0:0]$11311 1'1 case - assign $3\wr_detect$10[0:0]$11446 $2\wr_detect$10[0:0]$11445 + assign $3\wr_detect$10[0:0]$11311 $2\wr_detect$10[0:0]$11310 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11447 1'1 + assign $4\wr_detect$10[0:0]$11312 1'1 case - assign $4\wr_detect$10[0:0]$11447 $3\wr_detect$10[0:0]$11446 + assign $4\wr_detect$10[0:0]$11312 $3\wr_detect$10[0:0]$11311 end case - assign $1\wr_detect$10[0:0]$11444 1'0 + assign $1\wr_detect$10[0:0]$11309 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11443 + update \wr_detect$10 $0\wr_detect$10[0:0]$11308 end - attribute \src "libresoc.v:181348.3-181387.6" - process $proc$libresoc.v:181348$11448 + attribute \src "libresoc.v:181732.3-181771.6" + process $proc$libresoc.v:181732$11313 assign { } { } assign { } { } assign { } { } - assign $0\r3__data_o$next[3:0]$11449 $6\r3__data_o$next[3:0]$11455 - attribute \src "libresoc.v:181349.5-181349.29" + assign $0\r23__data_o$next[3:0]$11314 $6\r23__data_o$next[3:0]$11320 + attribute \src "libresoc.v:181733.5-181733.29" switch \initial - attribute \src "libresoc.v:181349.9-181349.17" + attribute \src "libresoc.v:181733.9-181733.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r3__ren + switch \r23__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r3__data_o$next[3:0]$11450 $5\r3__data_o$next[3:0]$11454 + assign $1\r23__data_o$next[3:0]$11315 $5\r23__data_o$next[3:0]$11319 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r3__data_o$next[3:0]$11451 \dest13__data_i + assign $2\r23__data_o$next[3:0]$11316 \dest13__data_i case - assign $2\r3__data_o$next[3:0]$11451 4'0000 + assign $2\r23__data_o$next[3:0]$11316 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r3__data_o$next[3:0]$11452 \dest23__data_i + assign $3\r23__data_o$next[3:0]$11317 \dest23__data_i case - assign $3\r3__data_o$next[3:0]$11452 $2\r3__data_o$next[3:0]$11451 + assign $3\r23__data_o$next[3:0]$11317 $2\r23__data_o$next[3:0]$11316 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r3__data_o$next[3:0]$11453 \w3__data_i + assign $4\r23__data_o$next[3:0]$11318 \w3__data_i case - assign $4\r3__data_o$next[3:0]$11453 $3\r3__data_o$next[3:0]$11452 + assign $4\r23__data_o$next[3:0]$11318 $3\r23__data_o$next[3:0]$11317 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r3__data_o$next[3:0]$11454 \reg + assign $5\r23__data_o$next[3:0]$11319 \reg case - assign $5\r3__data_o$next[3:0]$11454 $4\r3__data_o$next[3:0]$11453 + assign $5\r23__data_o$next[3:0]$11319 $4\r23__data_o$next[3:0]$11318 end case - assign $1\r3__data_o$next[3:0]$11450 4'0000 + assign $1\r23__data_o$next[3:0]$11315 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r3__data_o$next[3:0]$11455 4'0000 + assign $6\r23__data_o$next[3:0]$11320 4'0000 case - assign $6\r3__data_o$next[3:0]$11455 $1\r3__data_o$next[3:0]$11450 + assign $6\r23__data_o$next[3:0]$11320 $1\r23__data_o$next[3:0]$11315 end sync always - update \r3__data_o$next $0\r3__data_o$next[3:0]$11449 + update \r23__data_o$next $0\r23__data_o$next[3:0]$11314 end - attribute \src "libresoc.v:181388.3-181417.6" - process $proc$libresoc.v:181388$11456 + attribute \src "libresoc.v:181772.3-181801.6" + process $proc$libresoc.v:181772$11321 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11457 $1\wr_detect$13[0:0]$11458 - attribute \src "libresoc.v:181389.5-181389.29" + assign $0\wr_detect$13[0:0]$11322 $1\wr_detect$13[0:0]$11323 + attribute \src "libresoc.v:181773.5-181773.29" switch \initial - attribute \src "libresoc.v:181389.9-181389.17" + attribute \src "libresoc.v:181773.9-181773.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r3__ren + switch \r23__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11458 $4\wr_detect$13[0:0]$11461 + assign $1\wr_detect$13[0:0]$11323 $4\wr_detect$13[0:0]$11326 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11459 1'1 + assign $2\wr_detect$13[0:0]$11324 1'1 case - assign $2\wr_detect$13[0:0]$11459 1'0 + assign $2\wr_detect$13[0:0]$11324 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11460 1'1 + assign $3\wr_detect$13[0:0]$11325 1'1 case - assign $3\wr_detect$13[0:0]$11460 $2\wr_detect$13[0:0]$11459 + assign $3\wr_detect$13[0:0]$11325 $2\wr_detect$13[0:0]$11324 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11461 1'1 + assign $4\wr_detect$13[0:0]$11326 1'1 case - assign $4\wr_detect$13[0:0]$11461 $3\wr_detect$13[0:0]$11460 + assign $4\wr_detect$13[0:0]$11326 $3\wr_detect$13[0:0]$11325 end case - assign $1\wr_detect$13[0:0]$11458 1'0 + assign $1\wr_detect$13[0:0]$11323 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11457 + update \wr_detect$13 $0\wr_detect$13[0:0]$11322 end - connect \$9 $not$libresoc.v:180951$11364_Y - connect \$12 $not$libresoc.v:180952$11365_Y - connect \$15 $not$libresoc.v:180953$11366_Y - connect \$1 $not$libresoc.v:180954$11367_Y - connect \$3 $not$libresoc.v:180955$11368_Y - connect \$6 $not$libresoc.v:180956$11369_Y + connect \$9 $not$libresoc.v:181408$11245_Y + connect \$12 $not$libresoc.v:181409$11246_Y + connect \$1 $not$libresoc.v:181410$11247_Y + connect \$3 $not$libresoc.v:181411$11248_Y + connect \$6 $not$libresoc.v:181412$11249_Y end -attribute \src "libresoc.v:181422.1-181977.10" +attribute \src "libresoc.v:181806.1-182277.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" attribute \generator "nMigen" module \reg_4 - attribute \src "libresoc.v:181530.3-181569.6" - wire width 4 $0\cr_pred4__data_o$next[3:0]$11484 - attribute \src "libresoc.v:181528.3-181529.49" - wire width 4 $0\cr_pred4__data_o[3:0] - attribute \src "libresoc.v:181423.7-181423.20" + attribute \src "libresoc.v:181807.7-181807.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181600.3-181639.6" - wire width 4 $0\r24__data_o$next[3:0]$11493 - attribute \src "libresoc.v:181518.3-181519.39" + attribute \src "libresoc.v:182207.3-182246.6" + wire width 4 $0\r24__data_o$next[3:0]$11403 + attribute \src "libresoc.v:181890.3-181891.39" wire width 4 $0\r24__data_o[3:0] - attribute \src "libresoc.v:181907.3-181946.6" - wire width 4 $0\r4__data_o$next[3:0]$11555 - attribute \src "libresoc.v:181520.3-181521.37" + attribute \src "libresoc.v:182137.3-182176.6" + wire width 4 $0\r4__data_o$next[3:0]$11389 + attribute \src "libresoc.v:181892.3-181893.37" wire width 4 $0\r4__data_o[3:0] - attribute \src "libresoc.v:181670.3-181696.6" - wire width 4 $0\reg$next[3:0]$11507 - attribute \src "libresoc.v:181516.3-181517.25" + attribute \src "libresoc.v:181970.3-181996.6" + wire width 4 $0\reg$next[3:0]$11355 + attribute \src "libresoc.v:181888.3-181889.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:181697.3-181736.6" - wire width 4 $0\src14__data_o$next[3:0]$11513 - attribute \src "libresoc.v:181526.3-181527.43" + attribute \src "libresoc.v:181900.3-181939.6" + wire width 4 $0\src14__data_o$next[3:0]$11346 + attribute \src "libresoc.v:181898.3-181899.43" wire width 4 $0\src14__data_o[3:0] - attribute \src "libresoc.v:181767.3-181806.6" - wire width 4 $0\src24__data_o$next[3:0]$11527 - attribute \src "libresoc.v:181524.3-181525.43" + attribute \src "libresoc.v:181997.3-182036.6" + wire width 4 $0\src24__data_o$next[3:0]$11361 + attribute \src "libresoc.v:181896.3-181897.43" wire width 4 $0\src24__data_o[3:0] - attribute \src "libresoc.v:181837.3-181876.6" - wire width 4 $0\src34__data_o$next[3:0]$11541 - attribute \src "libresoc.v:181522.3-181523.43" + attribute \src "libresoc.v:182067.3-182106.6" + wire width 4 $0\src34__data_o$next[3:0]$11375 + attribute \src "libresoc.v:181894.3-181895.43" wire width 4 $0\src34__data_o[3:0] - attribute \src "libresoc.v:181877.3-181906.6" - wire $0\wr_detect$10[0:0]$11549 - attribute \src "libresoc.v:181947.3-181976.6" - wire $0\wr_detect$13[0:0]$11563 - attribute \src "libresoc.v:181640.3-181669.6" - wire $0\wr_detect$16[0:0]$11501 - attribute \src "libresoc.v:181737.3-181766.6" - wire $0\wr_detect$4[0:0]$11521 - attribute \src "libresoc.v:181807.3-181836.6" - wire $0\wr_detect$7[0:0]$11535 - attribute \src "libresoc.v:181570.3-181599.6" + attribute \src "libresoc.v:182177.3-182206.6" + wire $0\wr_detect$10[0:0]$11397 + attribute \src "libresoc.v:182247.3-182276.6" + wire $0\wr_detect$13[0:0]$11411 + attribute \src "libresoc.v:182037.3-182066.6" + wire $0\wr_detect$4[0:0]$11369 + attribute \src "libresoc.v:182107.3-182136.6" + wire $0\wr_detect$7[0:0]$11383 + attribute \src "libresoc.v:181940.3-181969.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:181530.3-181569.6" - wire width 4 $1\cr_pred4__data_o$next[3:0]$11485 - attribute \src "libresoc.v:181442.13-181442.36" - wire width 4 $1\cr_pred4__data_o[3:0] - attribute \src "libresoc.v:181600.3-181639.6" - wire width 4 $1\r24__data_o$next[3:0]$11494 - attribute \src "libresoc.v:181457.13-181457.31" + attribute \src "libresoc.v:182207.3-182246.6" + wire width 4 $1\r24__data_o$next[3:0]$11404 + attribute \src "libresoc.v:181832.13-181832.31" wire width 4 $1\r24__data_o[3:0] - attribute \src "libresoc.v:181907.3-181946.6" - wire width 4 $1\r4__data_o$next[3:0]$11556 - attribute \src "libresoc.v:181464.13-181464.30" + attribute \src "libresoc.v:182137.3-182176.6" + wire width 4 $1\r4__data_o$next[3:0]$11390 + attribute \src "libresoc.v:181839.13-181839.30" wire width 4 $1\r4__data_o[3:0] - attribute \src "libresoc.v:181670.3-181696.6" - wire width 4 $1\reg$next[3:0]$11508 - attribute \src "libresoc.v:181470.13-181470.25" + attribute \src "libresoc.v:181970.3-181996.6" + wire width 4 $1\reg$next[3:0]$11356 + attribute \src "libresoc.v:181845.13-181845.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:181697.3-181736.6" - wire width 4 $1\src14__data_o$next[3:0]$11514 - attribute \src "libresoc.v:181475.13-181475.33" + attribute \src "libresoc.v:181900.3-181939.6" + wire width 4 $1\src14__data_o$next[3:0]$11347 + attribute \src "libresoc.v:181850.13-181850.33" wire width 4 $1\src14__data_o[3:0] - attribute \src "libresoc.v:181767.3-181806.6" - wire width 4 $1\src24__data_o$next[3:0]$11528 - attribute \src "libresoc.v:181482.13-181482.33" + attribute \src "libresoc.v:181997.3-182036.6" + wire width 4 $1\src24__data_o$next[3:0]$11362 + attribute \src "libresoc.v:181857.13-181857.33" wire width 4 $1\src24__data_o[3:0] - attribute \src "libresoc.v:181837.3-181876.6" - wire width 4 $1\src34__data_o$next[3:0]$11542 - attribute \src "libresoc.v:181489.13-181489.33" + attribute \src "libresoc.v:182067.3-182106.6" + wire width 4 $1\src34__data_o$next[3:0]$11376 + attribute \src "libresoc.v:181864.13-181864.33" wire width 4 $1\src34__data_o[3:0] - attribute \src "libresoc.v:181877.3-181906.6" - wire $1\wr_detect$10[0:0]$11550 - attribute \src "libresoc.v:181947.3-181976.6" - wire $1\wr_detect$13[0:0]$11564 - attribute \src "libresoc.v:181640.3-181669.6" - wire $1\wr_detect$16[0:0]$11502 - attribute \src "libresoc.v:181737.3-181766.6" - wire $1\wr_detect$4[0:0]$11522 - attribute \src "libresoc.v:181807.3-181836.6" - wire $1\wr_detect$7[0:0]$11536 - attribute \src "libresoc.v:181570.3-181599.6" + attribute \src "libresoc.v:182177.3-182206.6" + wire $1\wr_detect$10[0:0]$11398 + attribute \src "libresoc.v:182247.3-182276.6" + wire $1\wr_detect$13[0:0]$11412 + attribute \src "libresoc.v:182037.3-182066.6" + wire $1\wr_detect$4[0:0]$11370 + attribute \src "libresoc.v:182107.3-182136.6" + wire $1\wr_detect$7[0:0]$11384 + attribute \src "libresoc.v:181940.3-181969.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:181530.3-181569.6" - wire width 4 $2\cr_pred4__data_o$next[3:0]$11486 - attribute \src "libresoc.v:181600.3-181639.6" - wire width 4 $2\r24__data_o$next[3:0]$11495 - attribute \src "libresoc.v:181907.3-181946.6" - wire width 4 $2\r4__data_o$next[3:0]$11557 - attribute \src "libresoc.v:181670.3-181696.6" - wire width 4 $2\reg$next[3:0]$11509 - attribute \src "libresoc.v:181697.3-181736.6" - wire width 4 $2\src14__data_o$next[3:0]$11515 - attribute \src "libresoc.v:181767.3-181806.6" - wire width 4 $2\src24__data_o$next[3:0]$11529 - attribute \src "libresoc.v:181837.3-181876.6" - wire width 4 $2\src34__data_o$next[3:0]$11543 - attribute \src "libresoc.v:181877.3-181906.6" - wire $2\wr_detect$10[0:0]$11551 - attribute \src "libresoc.v:181947.3-181976.6" - wire $2\wr_detect$13[0:0]$11565 - attribute \src "libresoc.v:181640.3-181669.6" - wire $2\wr_detect$16[0:0]$11503 - attribute \src "libresoc.v:181737.3-181766.6" - wire $2\wr_detect$4[0:0]$11523 - attribute \src "libresoc.v:181807.3-181836.6" - wire $2\wr_detect$7[0:0]$11537 - attribute \src "libresoc.v:181570.3-181599.6" + attribute \src "libresoc.v:182207.3-182246.6" + wire width 4 $2\r24__data_o$next[3:0]$11405 + attribute \src "libresoc.v:182137.3-182176.6" + wire width 4 $2\r4__data_o$next[3:0]$11391 + attribute \src "libresoc.v:181970.3-181996.6" + wire width 4 $2\reg$next[3:0]$11357 + attribute \src "libresoc.v:181900.3-181939.6" + wire width 4 $2\src14__data_o$next[3:0]$11348 + attribute \src "libresoc.v:181997.3-182036.6" + wire width 4 $2\src24__data_o$next[3:0]$11363 + attribute \src "libresoc.v:182067.3-182106.6" + wire width 4 $2\src34__data_o$next[3:0]$11377 + attribute \src "libresoc.v:182177.3-182206.6" + wire $2\wr_detect$10[0:0]$11399 + attribute \src "libresoc.v:182247.3-182276.6" + wire $2\wr_detect$13[0:0]$11413 + attribute \src "libresoc.v:182037.3-182066.6" + wire $2\wr_detect$4[0:0]$11371 + attribute \src "libresoc.v:182107.3-182136.6" + wire $2\wr_detect$7[0:0]$11385 + attribute \src "libresoc.v:181940.3-181969.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:181530.3-181569.6" - wire width 4 $3\cr_pred4__data_o$next[3:0]$11487 - attribute \src "libresoc.v:181600.3-181639.6" - wire width 4 $3\r24__data_o$next[3:0]$11496 - attribute \src "libresoc.v:181907.3-181946.6" - wire width 4 $3\r4__data_o$next[3:0]$11558 - attribute \src "libresoc.v:181670.3-181696.6" - wire width 4 $3\reg$next[3:0]$11510 - attribute \src "libresoc.v:181697.3-181736.6" - wire width 4 $3\src14__data_o$next[3:0]$11516 - attribute \src "libresoc.v:181767.3-181806.6" - wire width 4 $3\src24__data_o$next[3:0]$11530 - attribute \src "libresoc.v:181837.3-181876.6" - wire width 4 $3\src34__data_o$next[3:0]$11544 - attribute \src "libresoc.v:181877.3-181906.6" - wire $3\wr_detect$10[0:0]$11552 - attribute \src "libresoc.v:181947.3-181976.6" - wire $3\wr_detect$13[0:0]$11566 - attribute \src "libresoc.v:181640.3-181669.6" - wire $3\wr_detect$16[0:0]$11504 - attribute \src "libresoc.v:181737.3-181766.6" - wire $3\wr_detect$4[0:0]$11524 - attribute \src "libresoc.v:181807.3-181836.6" - wire $3\wr_detect$7[0:0]$11538 - attribute \src "libresoc.v:181570.3-181599.6" + attribute \src "libresoc.v:182207.3-182246.6" + wire width 4 $3\r24__data_o$next[3:0]$11406 + attribute \src "libresoc.v:182137.3-182176.6" + wire width 4 $3\r4__data_o$next[3:0]$11392 + attribute \src "libresoc.v:181970.3-181996.6" + wire width 4 $3\reg$next[3:0]$11358 + attribute \src "libresoc.v:181900.3-181939.6" + wire width 4 $3\src14__data_o$next[3:0]$11349 + attribute \src "libresoc.v:181997.3-182036.6" + wire width 4 $3\src24__data_o$next[3:0]$11364 + attribute \src "libresoc.v:182067.3-182106.6" + wire width 4 $3\src34__data_o$next[3:0]$11378 + attribute \src "libresoc.v:182177.3-182206.6" + wire $3\wr_detect$10[0:0]$11400 + attribute \src "libresoc.v:182247.3-182276.6" + wire $3\wr_detect$13[0:0]$11414 + attribute \src "libresoc.v:182037.3-182066.6" + wire $3\wr_detect$4[0:0]$11372 + attribute \src "libresoc.v:182107.3-182136.6" + wire $3\wr_detect$7[0:0]$11386 + attribute \src "libresoc.v:181940.3-181969.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:181530.3-181569.6" - wire width 4 $4\cr_pred4__data_o$next[3:0]$11488 - attribute \src "libresoc.v:181600.3-181639.6" - wire width 4 $4\r24__data_o$next[3:0]$11497 - attribute \src "libresoc.v:181907.3-181946.6" - wire width 4 $4\r4__data_o$next[3:0]$11559 - attribute \src "libresoc.v:181670.3-181696.6" - wire width 4 $4\reg$next[3:0]$11511 - attribute \src "libresoc.v:181697.3-181736.6" - wire width 4 $4\src14__data_o$next[3:0]$11517 - attribute \src "libresoc.v:181767.3-181806.6" - wire width 4 $4\src24__data_o$next[3:0]$11531 - attribute \src "libresoc.v:181837.3-181876.6" - wire width 4 $4\src34__data_o$next[3:0]$11545 - attribute \src "libresoc.v:181877.3-181906.6" - wire $4\wr_detect$10[0:0]$11553 - attribute \src "libresoc.v:181947.3-181976.6" - wire $4\wr_detect$13[0:0]$11567 - attribute \src "libresoc.v:181640.3-181669.6" - wire $4\wr_detect$16[0:0]$11505 - attribute \src "libresoc.v:181737.3-181766.6" - wire $4\wr_detect$4[0:0]$11525 - attribute \src "libresoc.v:181807.3-181836.6" - wire $4\wr_detect$7[0:0]$11539 - attribute \src "libresoc.v:181570.3-181599.6" + attribute \src "libresoc.v:182207.3-182246.6" + wire width 4 $4\r24__data_o$next[3:0]$11407 + attribute \src "libresoc.v:182137.3-182176.6" + wire width 4 $4\r4__data_o$next[3:0]$11393 + attribute \src "libresoc.v:181970.3-181996.6" + wire width 4 $4\reg$next[3:0]$11359 + attribute \src "libresoc.v:181900.3-181939.6" + wire width 4 $4\src14__data_o$next[3:0]$11350 + attribute \src "libresoc.v:181997.3-182036.6" + wire width 4 $4\src24__data_o$next[3:0]$11365 + attribute \src "libresoc.v:182067.3-182106.6" + wire width 4 $4\src34__data_o$next[3:0]$11379 + attribute \src "libresoc.v:182177.3-182206.6" + wire $4\wr_detect$10[0:0]$11401 + attribute \src "libresoc.v:182247.3-182276.6" + wire $4\wr_detect$13[0:0]$11415 + attribute \src "libresoc.v:182037.3-182066.6" + wire $4\wr_detect$4[0:0]$11373 + attribute \src "libresoc.v:182107.3-182136.6" + wire $4\wr_detect$7[0:0]$11387 + attribute \src "libresoc.v:181940.3-181969.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:181530.3-181569.6" - wire width 4 $5\cr_pred4__data_o$next[3:0]$11489 - attribute \src "libresoc.v:181600.3-181639.6" - wire width 4 $5\r24__data_o$next[3:0]$11498 - attribute \src "libresoc.v:181907.3-181946.6" - wire width 4 $5\r4__data_o$next[3:0]$11560 - attribute \src "libresoc.v:181697.3-181736.6" - wire width 4 $5\src14__data_o$next[3:0]$11518 - attribute \src "libresoc.v:181767.3-181806.6" - wire width 4 $5\src24__data_o$next[3:0]$11532 - attribute \src "libresoc.v:181837.3-181876.6" - wire width 4 $5\src34__data_o$next[3:0]$11546 - attribute \src "libresoc.v:181530.3-181569.6" - wire width 4 $6\cr_pred4__data_o$next[3:0]$11490 - attribute \src "libresoc.v:181600.3-181639.6" - wire width 4 $6\r24__data_o$next[3:0]$11499 - attribute \src "libresoc.v:181907.3-181946.6" - wire width 4 $6\r4__data_o$next[3:0]$11561 - attribute \src "libresoc.v:181697.3-181736.6" - wire width 4 $6\src14__data_o$next[3:0]$11519 - attribute \src "libresoc.v:181767.3-181806.6" - wire width 4 $6\src24__data_o$next[3:0]$11533 - attribute \src "libresoc.v:181837.3-181876.6" - wire width 4 $6\src34__data_o$next[3:0]$11547 - attribute \src "libresoc.v:181510.17-181510.104" - wire $not$libresoc.v:181510$11470_Y - attribute \src "libresoc.v:181511.18-181511.105" - wire $not$libresoc.v:181511$11471_Y - attribute \src "libresoc.v:181512.18-181512.105" - wire $not$libresoc.v:181512$11472_Y - attribute \src "libresoc.v:181513.17-181513.100" - wire $not$libresoc.v:181513$11473_Y - attribute \src "libresoc.v:181514.17-181514.103" - wire $not$libresoc.v:181514$11474_Y - attribute \src "libresoc.v:181515.17-181515.103" - wire $not$libresoc.v:181515$11475_Y + attribute \src "libresoc.v:182207.3-182246.6" + wire width 4 $5\r24__data_o$next[3:0]$11408 + attribute \src "libresoc.v:182137.3-182176.6" + wire width 4 $5\r4__data_o$next[3:0]$11394 + attribute \src "libresoc.v:181900.3-181939.6" + wire width 4 $5\src14__data_o$next[3:0]$11351 + attribute \src "libresoc.v:181997.3-182036.6" + wire width 4 $5\src24__data_o$next[3:0]$11366 + attribute \src "libresoc.v:182067.3-182106.6" + wire width 4 $5\src34__data_o$next[3:0]$11380 + attribute \src "libresoc.v:182207.3-182246.6" + wire width 4 $6\r24__data_o$next[3:0]$11409 + attribute \src "libresoc.v:182137.3-182176.6" + wire width 4 $6\r4__data_o$next[3:0]$11395 + attribute \src "libresoc.v:181900.3-181939.6" + wire width 4 $6\src14__data_o$next[3:0]$11352 + attribute \src "libresoc.v:181997.3-182036.6" + wire width 4 $6\src24__data_o$next[3:0]$11367 + attribute \src "libresoc.v:182067.3-182106.6" + wire width 4 $6\src34__data_o$next[3:0]$11381 + attribute \src "libresoc.v:181883.17-181883.104" + wire $not$libresoc.v:181883$11334_Y + attribute \src "libresoc.v:181884.18-181884.105" + wire $not$libresoc.v:181884$11335_Y + attribute \src "libresoc.v:181885.17-181885.100" + wire $not$libresoc.v:181885$11336_Y + attribute \src "libresoc.v:181886.17-181886.103" + wire $not$libresoc.v:181886$11337_Y + attribute \src "libresoc.v:181887.17-181887.103" + wire $not$libresoc.v:181887$11338_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" - wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \cr_pred4__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \cr_pred4__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \cr_pred4__ren + wire width 4 input 9 \dest14__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest14__data_i + wire input 8 \dest14__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest14__wen + wire width 4 input 11 \dest24__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 13 \dest24__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 12 \dest24__wen - attribute \src "libresoc.v:181423.7-181423.15" + wire input 10 \dest24__wen + attribute \src "libresoc.v:181807.7-181807.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 16 \r24__data_o + wire width 4 output 14 \r24__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r24__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \r24__ren + wire input 15 \r24__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r4__data_o + wire width 4 output 12 \r4__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r4__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r4__ren + wire input 13 \r4__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src14__data_o + wire width 4 output 3 \src14__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src14__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src14__ren + wire input 2 \src14__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src24__data_o + wire width 4 output 5 \src24__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src24__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src24__ren + wire input 4 \src24__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 9 \src34__data_o + wire width 4 output 7 \src34__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src34__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \src34__ren + wire input 6 \src34__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 18 \w4__data_i + wire width 4 input 16 \w4__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 19 \w4__wen + wire input 17 \w4__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -373433,257 +339131,232 @@ module \reg_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181510$11470 + cell $not $not$libresoc.v:181883$11334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:181510$11470_Y + connect \Y $not$libresoc.v:181883$11334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181511$11471 + cell $not $not$libresoc.v:181884$11335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:181511$11471_Y + connect \Y $not$libresoc.v:181884$11335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181512$11472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$16 - connect \Y $not$libresoc.v:181512$11472_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181513$11473 + cell $not $not$libresoc.v:181885$11336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:181513$11473_Y + connect \Y $not$libresoc.v:181885$11336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181514$11474 + cell $not $not$libresoc.v:181886$11337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:181514$11474_Y + connect \Y $not$libresoc.v:181886$11337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181515$11475 + cell $not $not$libresoc.v:181887$11338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:181515$11475_Y + connect \Y $not$libresoc.v:181887$11338_Y end - attribute \src "libresoc.v:181423.7-181423.20" - process $proc$libresoc.v:181423$11568 + attribute \src "libresoc.v:181807.7-181807.20" + process $proc$libresoc.v:181807$11416 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181442.13-181442.36" - process $proc$libresoc.v:181442$11569 - assign { } { } - assign $1\cr_pred4__data_o[3:0] 4'0000 - sync always - sync init - update \cr_pred4__data_o $1\cr_pred4__data_o[3:0] - end - attribute \src "libresoc.v:181457.13-181457.31" - process $proc$libresoc.v:181457$11570 + attribute \src "libresoc.v:181832.13-181832.31" + process $proc$libresoc.v:181832$11417 assign { } { } assign $1\r24__data_o[3:0] 4'0000 sync always sync init update \r24__data_o $1\r24__data_o[3:0] end - attribute \src "libresoc.v:181464.13-181464.30" - process $proc$libresoc.v:181464$11571 + attribute \src "libresoc.v:181839.13-181839.30" + process $proc$libresoc.v:181839$11418 assign { } { } assign $1\r4__data_o[3:0] 4'0000 sync always sync init update \r4__data_o $1\r4__data_o[3:0] end - attribute \src "libresoc.v:181470.13-181470.25" - process $proc$libresoc.v:181470$11572 + attribute \src "libresoc.v:181845.13-181845.25" + process $proc$libresoc.v:181845$11419 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:181475.13-181475.33" - process $proc$libresoc.v:181475$11573 + attribute \src "libresoc.v:181850.13-181850.33" + process $proc$libresoc.v:181850$11420 assign { } { } assign $1\src14__data_o[3:0] 4'0000 sync always sync init update \src14__data_o $1\src14__data_o[3:0] end - attribute \src "libresoc.v:181482.13-181482.33" - process $proc$libresoc.v:181482$11574 + attribute \src "libresoc.v:181857.13-181857.33" + process $proc$libresoc.v:181857$11421 assign { } { } assign $1\src24__data_o[3:0] 4'0000 sync always sync init update \src24__data_o $1\src24__data_o[3:0] end - attribute \src "libresoc.v:181489.13-181489.33" - process $proc$libresoc.v:181489$11575 + attribute \src "libresoc.v:181864.13-181864.33" + process $proc$libresoc.v:181864$11422 assign { } { } assign $1\src34__data_o[3:0] 4'0000 sync always sync init update \src34__data_o $1\src34__data_o[3:0] end - attribute \src "libresoc.v:181516.3-181517.25" - process $proc$libresoc.v:181516$11476 + attribute \src "libresoc.v:181888.3-181889.25" + process $proc$libresoc.v:181888$11339 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:181518.3-181519.39" - process $proc$libresoc.v:181518$11477 + attribute \src "libresoc.v:181890.3-181891.39" + process $proc$libresoc.v:181890$11340 assign { } { } assign $0\r24__data_o[3:0] \r24__data_o$next sync posedge \coresync_clk update \r24__data_o $0\r24__data_o[3:0] end - attribute \src "libresoc.v:181520.3-181521.37" - process $proc$libresoc.v:181520$11478 + attribute \src "libresoc.v:181892.3-181893.37" + process $proc$libresoc.v:181892$11341 assign { } { } assign $0\r4__data_o[3:0] \r4__data_o$next sync posedge \coresync_clk update \r4__data_o $0\r4__data_o[3:0] end - attribute \src "libresoc.v:181522.3-181523.43" - process $proc$libresoc.v:181522$11479 + attribute \src "libresoc.v:181894.3-181895.43" + process $proc$libresoc.v:181894$11342 assign { } { } assign $0\src34__data_o[3:0] \src34__data_o$next sync posedge \coresync_clk update \src34__data_o $0\src34__data_o[3:0] end - attribute \src "libresoc.v:181524.3-181525.43" - process $proc$libresoc.v:181524$11480 + attribute \src "libresoc.v:181896.3-181897.43" + process $proc$libresoc.v:181896$11343 assign { } { } assign $0\src24__data_o[3:0] \src24__data_o$next sync posedge \coresync_clk update \src24__data_o $0\src24__data_o[3:0] end - attribute \src "libresoc.v:181526.3-181527.43" - process $proc$libresoc.v:181526$11481 + attribute \src "libresoc.v:181898.3-181899.43" + process $proc$libresoc.v:181898$11344 assign { } { } assign $0\src14__data_o[3:0] \src14__data_o$next sync posedge \coresync_clk update \src14__data_o $0\src14__data_o[3:0] end - attribute \src "libresoc.v:181528.3-181529.49" - process $proc$libresoc.v:181528$11482 - assign { } { } - assign $0\cr_pred4__data_o[3:0] \cr_pred4__data_o$next - sync posedge \coresync_clk - update \cr_pred4__data_o $0\cr_pred4__data_o[3:0] - end - attribute \src "libresoc.v:181530.3-181569.6" - process $proc$libresoc.v:181530$11483 + attribute \src "libresoc.v:181900.3-181939.6" + process $proc$libresoc.v:181900$11345 assign { } { } assign { } { } assign { } { } - assign $0\cr_pred4__data_o$next[3:0]$11484 $6\cr_pred4__data_o$next[3:0]$11490 - attribute \src "libresoc.v:181531.5-181531.29" + assign $0\src14__data_o$next[3:0]$11346 $6\src14__data_o$next[3:0]$11352 + attribute \src "libresoc.v:181901.5-181901.29" switch \initial - attribute \src "libresoc.v:181531.9-181531.17" + attribute \src "libresoc.v:181901.9-181901.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred4__ren + switch \src14__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\cr_pred4__data_o$next[3:0]$11485 $5\cr_pred4__data_o$next[3:0]$11489 + assign $1\src14__data_o$next[3:0]$11347 $5\src14__data_o$next[3:0]$11351 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred4__data_o$next[3:0]$11486 \dest14__data_i + assign $2\src14__data_o$next[3:0]$11348 \dest14__data_i case - assign $2\cr_pred4__data_o$next[3:0]$11486 4'0000 + assign $2\src14__data_o$next[3:0]$11348 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred4__data_o$next[3:0]$11487 \dest24__data_i + assign $3\src14__data_o$next[3:0]$11349 \dest24__data_i case - assign $3\cr_pred4__data_o$next[3:0]$11487 $2\cr_pred4__data_o$next[3:0]$11486 + assign $3\src14__data_o$next[3:0]$11349 $2\src14__data_o$next[3:0]$11348 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred4__data_o$next[3:0]$11488 \w4__data_i + assign $4\src14__data_o$next[3:0]$11350 \w4__data_i case - assign $4\cr_pred4__data_o$next[3:0]$11488 $3\cr_pred4__data_o$next[3:0]$11487 + assign $4\src14__data_o$next[3:0]$11350 $3\src14__data_o$next[3:0]$11349 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred4__data_o$next[3:0]$11489 \reg + assign $5\src14__data_o$next[3:0]$11351 \reg case - assign $5\cr_pred4__data_o$next[3:0]$11489 $4\cr_pred4__data_o$next[3:0]$11488 + assign $5\src14__data_o$next[3:0]$11351 $4\src14__data_o$next[3:0]$11350 end case - assign $1\cr_pred4__data_o$next[3:0]$11485 4'0000 + assign $1\src14__data_o$next[3:0]$11347 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred4__data_o$next[3:0]$11490 4'0000 + assign $6\src14__data_o$next[3:0]$11352 4'0000 case - assign $6\cr_pred4__data_o$next[3:0]$11490 $1\cr_pred4__data_o$next[3:0]$11485 + assign $6\src14__data_o$next[3:0]$11352 $1\src14__data_o$next[3:0]$11347 end sync always - update \cr_pred4__data_o$next $0\cr_pred4__data_o$next[3:0]$11484 + update \src14__data_o$next $0\src14__data_o$next[3:0]$11346 end - attribute \src "libresoc.v:181570.3-181599.6" - process $proc$libresoc.v:181570$11491 + attribute \src "libresoc.v:181940.3-181969.6" + process $proc$libresoc.v:181940$11353 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:181571.5-181571.29" + attribute \src "libresoc.v:181941.5-181941.29" switch \initial - attribute \src "libresoc.v:181571.9-181571.17" + attribute \src "libresoc.v:181941.9-181941.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred4__ren + switch \src14__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -373724,962 +339397,798 @@ module \reg_4 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:181600.3-181639.6" - process $proc$libresoc.v:181600$11492 + attribute \src "libresoc.v:181970.3-181996.6" + process $proc$libresoc.v:181970$11354 + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\r24__data_o$next[3:0]$11493 $6\r24__data_o$next[3:0]$11499 - attribute \src "libresoc.v:181601.5-181601.29" + assign { } { } + assign $0\reg$next[3:0]$11355 $4\reg$next[3:0]$11359 + attribute \src "libresoc.v:181971.5-181971.29" switch \initial - attribute \src "libresoc.v:181601.9-181601.17" + attribute \src "libresoc.v:181971.9-181971.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r24__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign $1\reg$next[3:0]$11356 \dest14__data_i + case + assign $1\reg$next[3:0]$11356 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } + assign $2\reg$next[3:0]$11357 \dest24__data_i + case + assign $2\reg$next[3:0]$11357 $1\reg$next[3:0]$11356 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign { } { } - assign $1\r24__data_o$next[3:0]$11494 $5\r24__data_o$next[3:0]$11498 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r24__data_o$next[3:0]$11495 \dest14__data_i - case - assign $2\r24__data_o$next[3:0]$11495 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r24__data_o$next[3:0]$11496 \dest24__data_i - case - assign $3\r24__data_o$next[3:0]$11496 $2\r24__data_o$next[3:0]$11495 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r24__data_o$next[3:0]$11497 \w4__data_i - case - assign $4\r24__data_o$next[3:0]$11497 $3\r24__data_o$next[3:0]$11496 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r24__data_o$next[3:0]$11498 \reg - case - assign $5\r24__data_o$next[3:0]$11498 $4\r24__data_o$next[3:0]$11497 - end + assign $3\reg$next[3:0]$11358 \w4__data_i case - assign $1\r24__data_o$next[3:0]$11494 4'0000 + assign $3\reg$next[3:0]$11358 $2\reg$next[3:0]$11357 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r24__data_o$next[3:0]$11499 4'0000 + assign $4\reg$next[3:0]$11359 4'0000 case - assign $6\r24__data_o$next[3:0]$11499 $1\r24__data_o$next[3:0]$11494 + assign $4\reg$next[3:0]$11359 $3\reg$next[3:0]$11358 end sync always - update \r24__data_o$next $0\r24__data_o$next[3:0]$11493 + update \reg$next $0\reg$next[3:0]$11355 end - attribute \src "libresoc.v:181640.3-181669.6" - process $proc$libresoc.v:181640$11500 + attribute \src "libresoc.v:181997.3-182036.6" + process $proc$libresoc.v:181997$11360 + assign { } { } assign { } { } assign { } { } - assign $0\wr_detect$16[0:0]$11501 $1\wr_detect$16[0:0]$11502 - attribute \src "libresoc.v:181641.5-181641.29" + assign $0\src24__data_o$next[3:0]$11361 $6\src24__data_o$next[3:0]$11367 + attribute \src "libresoc.v:181998.5-181998.29" switch \initial - attribute \src "libresoc.v:181641.9-181641.17" + attribute \src "libresoc.v:181998.9-181998.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r24__ren + switch \src24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$16[0:0]$11502 $4\wr_detect$16[0:0]$11505 + assign $1\src24__data_o$next[3:0]$11362 $5\src24__data_o$next[3:0]$11366 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$16[0:0]$11503 1'1 + assign $2\src24__data_o$next[3:0]$11363 \dest14__data_i case - assign $2\wr_detect$16[0:0]$11503 1'0 + assign $2\src24__data_o$next[3:0]$11363 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$16[0:0]$11504 1'1 + assign $3\src24__data_o$next[3:0]$11364 \dest24__data_i case - assign $3\wr_detect$16[0:0]$11504 $2\wr_detect$16[0:0]$11503 + assign $3\src24__data_o$next[3:0]$11364 $2\src24__data_o$next[3:0]$11363 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$16[0:0]$11505 1'1 + assign $4\src24__data_o$next[3:0]$11365 \w4__data_i case - assign $4\wr_detect$16[0:0]$11505 $3\wr_detect$16[0:0]$11504 - end - case - assign $1\wr_detect$16[0:0]$11502 1'0 - end - sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$11501 - end - attribute \src "libresoc.v:181670.3-181696.6" - process $proc$libresoc.v:181670$11506 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$11507 $4\reg$next[3:0]$11511 - attribute \src "libresoc.v:181671.5-181671.29" - switch \initial - attribute \src "libresoc.v:181671.9-181671.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest14__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[3:0]$11508 \dest14__data_i - case - assign $1\reg$next[3:0]$11508 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[3:0]$11509 \dest24__data_i - case - assign $2\reg$next[3:0]$11509 $1\reg$next[3:0]$11508 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[3:0]$11510 \w4__data_i - case - assign $3\reg$next[3:0]$11510 $2\reg$next[3:0]$11509 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[3:0]$11511 4'0000 - case - assign $4\reg$next[3:0]$11511 $3\reg$next[3:0]$11510 - end - sync always - update \reg$next $0\reg$next[3:0]$11507 - end - attribute \src "libresoc.v:181697.3-181736.6" - process $proc$libresoc.v:181697$11512 - assign { } { } - assign { } { } - assign { } { } - assign $0\src14__data_o$next[3:0]$11513 $6\src14__data_o$next[3:0]$11519 - attribute \src "libresoc.v:181698.5-181698.29" - switch \initial - attribute \src "libresoc.v:181698.9-181698.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src14__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src14__data_o$next[3:0]$11514 $5\src14__data_o$next[3:0]$11518 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src14__data_o$next[3:0]$11515 \dest14__data_i - case - assign $2\src14__data_o$next[3:0]$11515 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src14__data_o$next[3:0]$11516 \dest24__data_i - case - assign $3\src14__data_o$next[3:0]$11516 $2\src14__data_o$next[3:0]$11515 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src14__data_o$next[3:0]$11517 \w4__data_i - case - assign $4\src14__data_o$next[3:0]$11517 $3\src14__data_o$next[3:0]$11516 + assign $4\src24__data_o$next[3:0]$11365 $3\src24__data_o$next[3:0]$11364 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src14__data_o$next[3:0]$11518 \reg + assign $5\src24__data_o$next[3:0]$11366 \reg case - assign $5\src14__data_o$next[3:0]$11518 $4\src14__data_o$next[3:0]$11517 + assign $5\src24__data_o$next[3:0]$11366 $4\src24__data_o$next[3:0]$11365 end case - assign $1\src14__data_o$next[3:0]$11514 4'0000 + assign $1\src24__data_o$next[3:0]$11362 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src14__data_o$next[3:0]$11519 4'0000 + assign $6\src24__data_o$next[3:0]$11367 4'0000 case - assign $6\src14__data_o$next[3:0]$11519 $1\src14__data_o$next[3:0]$11514 + assign $6\src24__data_o$next[3:0]$11367 $1\src24__data_o$next[3:0]$11362 end sync always - update \src14__data_o$next $0\src14__data_o$next[3:0]$11513 + update \src24__data_o$next $0\src24__data_o$next[3:0]$11361 end - attribute \src "libresoc.v:181737.3-181766.6" - process $proc$libresoc.v:181737$11520 + attribute \src "libresoc.v:182037.3-182066.6" + process $proc$libresoc.v:182037$11368 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11521 $1\wr_detect$4[0:0]$11522 - attribute \src "libresoc.v:181738.5-181738.29" + assign $0\wr_detect$4[0:0]$11369 $1\wr_detect$4[0:0]$11370 + attribute \src "libresoc.v:182038.5-182038.29" switch \initial - attribute \src "libresoc.v:181738.9-181738.17" + attribute \src "libresoc.v:182038.9-182038.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src14__ren + switch \src24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11522 $4\wr_detect$4[0:0]$11525 + assign $1\wr_detect$4[0:0]$11370 $4\wr_detect$4[0:0]$11373 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11523 1'1 + assign $2\wr_detect$4[0:0]$11371 1'1 case - assign $2\wr_detect$4[0:0]$11523 1'0 + assign $2\wr_detect$4[0:0]$11371 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11524 1'1 + assign $3\wr_detect$4[0:0]$11372 1'1 case - assign $3\wr_detect$4[0:0]$11524 $2\wr_detect$4[0:0]$11523 + assign $3\wr_detect$4[0:0]$11372 $2\wr_detect$4[0:0]$11371 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11525 1'1 + assign $4\wr_detect$4[0:0]$11373 1'1 case - assign $4\wr_detect$4[0:0]$11525 $3\wr_detect$4[0:0]$11524 + assign $4\wr_detect$4[0:0]$11373 $3\wr_detect$4[0:0]$11372 end case - assign $1\wr_detect$4[0:0]$11522 1'0 + assign $1\wr_detect$4[0:0]$11370 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11521 + update \wr_detect$4 $0\wr_detect$4[0:0]$11369 end - attribute \src "libresoc.v:181767.3-181806.6" - process $proc$libresoc.v:181767$11526 + attribute \src "libresoc.v:182067.3-182106.6" + process $proc$libresoc.v:182067$11374 assign { } { } assign { } { } assign { } { } - assign $0\src24__data_o$next[3:0]$11527 $6\src24__data_o$next[3:0]$11533 - attribute \src "libresoc.v:181768.5-181768.29" + assign $0\src34__data_o$next[3:0]$11375 $6\src34__data_o$next[3:0]$11381 + attribute \src "libresoc.v:182068.5-182068.29" switch \initial - attribute \src "libresoc.v:181768.9-181768.17" + attribute \src "libresoc.v:182068.9-182068.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src24__ren + switch \src34__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src24__data_o$next[3:0]$11528 $5\src24__data_o$next[3:0]$11532 + assign $1\src34__data_o$next[3:0]$11376 $5\src34__data_o$next[3:0]$11380 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src24__data_o$next[3:0]$11529 \dest14__data_i + assign $2\src34__data_o$next[3:0]$11377 \dest14__data_i case - assign $2\src24__data_o$next[3:0]$11529 4'0000 + assign $2\src34__data_o$next[3:0]$11377 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src24__data_o$next[3:0]$11530 \dest24__data_i + assign $3\src34__data_o$next[3:0]$11378 \dest24__data_i case - assign $3\src24__data_o$next[3:0]$11530 $2\src24__data_o$next[3:0]$11529 + assign $3\src34__data_o$next[3:0]$11378 $2\src34__data_o$next[3:0]$11377 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src24__data_o$next[3:0]$11531 \w4__data_i + assign $4\src34__data_o$next[3:0]$11379 \w4__data_i case - assign $4\src24__data_o$next[3:0]$11531 $3\src24__data_o$next[3:0]$11530 + assign $4\src34__data_o$next[3:0]$11379 $3\src34__data_o$next[3:0]$11378 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src24__data_o$next[3:0]$11532 \reg + assign $5\src34__data_o$next[3:0]$11380 \reg case - assign $5\src24__data_o$next[3:0]$11532 $4\src24__data_o$next[3:0]$11531 + assign $5\src34__data_o$next[3:0]$11380 $4\src34__data_o$next[3:0]$11379 end case - assign $1\src24__data_o$next[3:0]$11528 4'0000 + assign $1\src34__data_o$next[3:0]$11376 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src24__data_o$next[3:0]$11533 4'0000 + assign $6\src34__data_o$next[3:0]$11381 4'0000 case - assign $6\src24__data_o$next[3:0]$11533 $1\src24__data_o$next[3:0]$11528 + assign $6\src34__data_o$next[3:0]$11381 $1\src34__data_o$next[3:0]$11376 end sync always - update \src24__data_o$next $0\src24__data_o$next[3:0]$11527 + update \src34__data_o$next $0\src34__data_o$next[3:0]$11375 end - attribute \src "libresoc.v:181807.3-181836.6" - process $proc$libresoc.v:181807$11534 + attribute \src "libresoc.v:182107.3-182136.6" + process $proc$libresoc.v:182107$11382 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11535 $1\wr_detect$7[0:0]$11536 - attribute \src "libresoc.v:181808.5-181808.29" + assign $0\wr_detect$7[0:0]$11383 $1\wr_detect$7[0:0]$11384 + attribute \src "libresoc.v:182108.5-182108.29" switch \initial - attribute \src "libresoc.v:181808.9-181808.17" + attribute \src "libresoc.v:182108.9-182108.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src24__ren + switch \src34__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11536 $4\wr_detect$7[0:0]$11539 + assign $1\wr_detect$7[0:0]$11384 $4\wr_detect$7[0:0]$11387 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11537 1'1 + assign $2\wr_detect$7[0:0]$11385 1'1 case - assign $2\wr_detect$7[0:0]$11537 1'0 + assign $2\wr_detect$7[0:0]$11385 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11538 1'1 + assign $3\wr_detect$7[0:0]$11386 1'1 case - assign $3\wr_detect$7[0:0]$11538 $2\wr_detect$7[0:0]$11537 + assign $3\wr_detect$7[0:0]$11386 $2\wr_detect$7[0:0]$11385 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11539 1'1 + assign $4\wr_detect$7[0:0]$11387 1'1 case - assign $4\wr_detect$7[0:0]$11539 $3\wr_detect$7[0:0]$11538 + assign $4\wr_detect$7[0:0]$11387 $3\wr_detect$7[0:0]$11386 end case - assign $1\wr_detect$7[0:0]$11536 1'0 + assign $1\wr_detect$7[0:0]$11384 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11535 + update \wr_detect$7 $0\wr_detect$7[0:0]$11383 end - attribute \src "libresoc.v:181837.3-181876.6" - process $proc$libresoc.v:181837$11540 + attribute \src "libresoc.v:182137.3-182176.6" + process $proc$libresoc.v:182137$11388 assign { } { } assign { } { } assign { } { } - assign $0\src34__data_o$next[3:0]$11541 $6\src34__data_o$next[3:0]$11547 - attribute \src "libresoc.v:181838.5-181838.29" + assign $0\r4__data_o$next[3:0]$11389 $6\r4__data_o$next[3:0]$11395 + attribute \src "libresoc.v:182138.5-182138.29" switch \initial - attribute \src "libresoc.v:181838.9-181838.17" + attribute \src "libresoc.v:182138.9-182138.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src34__ren + switch \r4__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src34__data_o$next[3:0]$11542 $5\src34__data_o$next[3:0]$11546 + assign $1\r4__data_o$next[3:0]$11390 $5\r4__data_o$next[3:0]$11394 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src34__data_o$next[3:0]$11543 \dest14__data_i + assign $2\r4__data_o$next[3:0]$11391 \dest14__data_i case - assign $2\src34__data_o$next[3:0]$11543 4'0000 + assign $2\r4__data_o$next[3:0]$11391 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src34__data_o$next[3:0]$11544 \dest24__data_i + assign $3\r4__data_o$next[3:0]$11392 \dest24__data_i case - assign $3\src34__data_o$next[3:0]$11544 $2\src34__data_o$next[3:0]$11543 + assign $3\r4__data_o$next[3:0]$11392 $2\r4__data_o$next[3:0]$11391 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src34__data_o$next[3:0]$11545 \w4__data_i + assign $4\r4__data_o$next[3:0]$11393 \w4__data_i case - assign $4\src34__data_o$next[3:0]$11545 $3\src34__data_o$next[3:0]$11544 + assign $4\r4__data_o$next[3:0]$11393 $3\r4__data_o$next[3:0]$11392 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src34__data_o$next[3:0]$11546 \reg + assign $5\r4__data_o$next[3:0]$11394 \reg case - assign $5\src34__data_o$next[3:0]$11546 $4\src34__data_o$next[3:0]$11545 + assign $5\r4__data_o$next[3:0]$11394 $4\r4__data_o$next[3:0]$11393 end case - assign $1\src34__data_o$next[3:0]$11542 4'0000 + assign $1\r4__data_o$next[3:0]$11390 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src34__data_o$next[3:0]$11547 4'0000 + assign $6\r4__data_o$next[3:0]$11395 4'0000 case - assign $6\src34__data_o$next[3:0]$11547 $1\src34__data_o$next[3:0]$11542 + assign $6\r4__data_o$next[3:0]$11395 $1\r4__data_o$next[3:0]$11390 end sync always - update \src34__data_o$next $0\src34__data_o$next[3:0]$11541 + update \r4__data_o$next $0\r4__data_o$next[3:0]$11389 end - attribute \src "libresoc.v:181877.3-181906.6" - process $proc$libresoc.v:181877$11548 + attribute \src "libresoc.v:182177.3-182206.6" + process $proc$libresoc.v:182177$11396 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11549 $1\wr_detect$10[0:0]$11550 - attribute \src "libresoc.v:181878.5-181878.29" + assign $0\wr_detect$10[0:0]$11397 $1\wr_detect$10[0:0]$11398 + attribute \src "libresoc.v:182178.5-182178.29" switch \initial - attribute \src "libresoc.v:181878.9-181878.17" + attribute \src "libresoc.v:182178.9-182178.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src34__ren + switch \r4__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11550 $4\wr_detect$10[0:0]$11553 + assign $1\wr_detect$10[0:0]$11398 $4\wr_detect$10[0:0]$11401 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11551 1'1 + assign $2\wr_detect$10[0:0]$11399 1'1 case - assign $2\wr_detect$10[0:0]$11551 1'0 + assign $2\wr_detect$10[0:0]$11399 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11552 1'1 + assign $3\wr_detect$10[0:0]$11400 1'1 case - assign $3\wr_detect$10[0:0]$11552 $2\wr_detect$10[0:0]$11551 + assign $3\wr_detect$10[0:0]$11400 $2\wr_detect$10[0:0]$11399 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11553 1'1 + assign $4\wr_detect$10[0:0]$11401 1'1 case - assign $4\wr_detect$10[0:0]$11553 $3\wr_detect$10[0:0]$11552 + assign $4\wr_detect$10[0:0]$11401 $3\wr_detect$10[0:0]$11400 end case - assign $1\wr_detect$10[0:0]$11550 1'0 + assign $1\wr_detect$10[0:0]$11398 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11549 + update \wr_detect$10 $0\wr_detect$10[0:0]$11397 end - attribute \src "libresoc.v:181907.3-181946.6" - process $proc$libresoc.v:181907$11554 + attribute \src "libresoc.v:182207.3-182246.6" + process $proc$libresoc.v:182207$11402 assign { } { } assign { } { } assign { } { } - assign $0\r4__data_o$next[3:0]$11555 $6\r4__data_o$next[3:0]$11561 - attribute \src "libresoc.v:181908.5-181908.29" + assign $0\r24__data_o$next[3:0]$11403 $6\r24__data_o$next[3:0]$11409 + attribute \src "libresoc.v:182208.5-182208.29" switch \initial - attribute \src "libresoc.v:181908.9-181908.17" + attribute \src "libresoc.v:182208.9-182208.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r4__ren + switch \r24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r4__data_o$next[3:0]$11556 $5\r4__data_o$next[3:0]$11560 + assign $1\r24__data_o$next[3:0]$11404 $5\r24__data_o$next[3:0]$11408 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r4__data_o$next[3:0]$11557 \dest14__data_i + assign $2\r24__data_o$next[3:0]$11405 \dest14__data_i case - assign $2\r4__data_o$next[3:0]$11557 4'0000 + assign $2\r24__data_o$next[3:0]$11405 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r4__data_o$next[3:0]$11558 \dest24__data_i + assign $3\r24__data_o$next[3:0]$11406 \dest24__data_i case - assign $3\r4__data_o$next[3:0]$11558 $2\r4__data_o$next[3:0]$11557 + assign $3\r24__data_o$next[3:0]$11406 $2\r24__data_o$next[3:0]$11405 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r4__data_o$next[3:0]$11559 \w4__data_i + assign $4\r24__data_o$next[3:0]$11407 \w4__data_i case - assign $4\r4__data_o$next[3:0]$11559 $3\r4__data_o$next[3:0]$11558 + assign $4\r24__data_o$next[3:0]$11407 $3\r24__data_o$next[3:0]$11406 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r4__data_o$next[3:0]$11560 \reg + assign $5\r24__data_o$next[3:0]$11408 \reg case - assign $5\r4__data_o$next[3:0]$11560 $4\r4__data_o$next[3:0]$11559 + assign $5\r24__data_o$next[3:0]$11408 $4\r24__data_o$next[3:0]$11407 end case - assign $1\r4__data_o$next[3:0]$11556 4'0000 + assign $1\r24__data_o$next[3:0]$11404 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r4__data_o$next[3:0]$11561 4'0000 + assign $6\r24__data_o$next[3:0]$11409 4'0000 case - assign $6\r4__data_o$next[3:0]$11561 $1\r4__data_o$next[3:0]$11556 + assign $6\r24__data_o$next[3:0]$11409 $1\r24__data_o$next[3:0]$11404 end sync always - update \r4__data_o$next $0\r4__data_o$next[3:0]$11555 + update \r24__data_o$next $0\r24__data_o$next[3:0]$11403 end - attribute \src "libresoc.v:181947.3-181976.6" - process $proc$libresoc.v:181947$11562 + attribute \src "libresoc.v:182247.3-182276.6" + process $proc$libresoc.v:182247$11410 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11563 $1\wr_detect$13[0:0]$11564 - attribute \src "libresoc.v:181948.5-181948.29" + assign $0\wr_detect$13[0:0]$11411 $1\wr_detect$13[0:0]$11412 + attribute \src "libresoc.v:182248.5-182248.29" switch \initial - attribute \src "libresoc.v:181948.9-181948.17" + attribute \src "libresoc.v:182248.9-182248.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r4__ren + switch \r24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11564 $4\wr_detect$13[0:0]$11567 + assign $1\wr_detect$13[0:0]$11412 $4\wr_detect$13[0:0]$11415 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11565 1'1 + assign $2\wr_detect$13[0:0]$11413 1'1 case - assign $2\wr_detect$13[0:0]$11565 1'0 + assign $2\wr_detect$13[0:0]$11413 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11566 1'1 + assign $3\wr_detect$13[0:0]$11414 1'1 case - assign $3\wr_detect$13[0:0]$11566 $2\wr_detect$13[0:0]$11565 + assign $3\wr_detect$13[0:0]$11414 $2\wr_detect$13[0:0]$11413 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11567 1'1 + assign $4\wr_detect$13[0:0]$11415 1'1 case - assign $4\wr_detect$13[0:0]$11567 $3\wr_detect$13[0:0]$11566 + assign $4\wr_detect$13[0:0]$11415 $3\wr_detect$13[0:0]$11414 end case - assign $1\wr_detect$13[0:0]$11564 1'0 + assign $1\wr_detect$13[0:0]$11412 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11563 + update \wr_detect$13 $0\wr_detect$13[0:0]$11411 end - connect \$9 $not$libresoc.v:181510$11470_Y - connect \$12 $not$libresoc.v:181511$11471_Y - connect \$15 $not$libresoc.v:181512$11472_Y - connect \$1 $not$libresoc.v:181513$11473_Y - connect \$3 $not$libresoc.v:181514$11474_Y - connect \$6 $not$libresoc.v:181515$11475_Y + connect \$9 $not$libresoc.v:181883$11334_Y + connect \$12 $not$libresoc.v:181884$11335_Y + connect \$1 $not$libresoc.v:181885$11336_Y + connect \$3 $not$libresoc.v:181886$11337_Y + connect \$6 $not$libresoc.v:181887$11338_Y end -attribute \src "libresoc.v:181981.1-182536.10" +attribute \src "libresoc.v:182281.1-182752.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" attribute \generator "nMigen" module \reg_5 - attribute \src "libresoc.v:182089.3-182128.6" - wire width 4 $0\cr_pred5__data_o$next[3:0]$11590 - attribute \src "libresoc.v:182087.3-182088.49" - wire width 4 $0\cr_pred5__data_o[3:0] - attribute \src "libresoc.v:181982.7-181982.20" + attribute \src "libresoc.v:182282.7-182282.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182159.3-182198.6" - wire width 4 $0\r25__data_o$next[3:0]$11599 - attribute \src "libresoc.v:182077.3-182078.39" + attribute \src "libresoc.v:182682.3-182721.6" + wire width 4 $0\r25__data_o$next[3:0]$11492 + attribute \src "libresoc.v:182365.3-182366.39" wire width 4 $0\r25__data_o[3:0] - attribute \src "libresoc.v:182466.3-182505.6" - wire width 4 $0\r5__data_o$next[3:0]$11661 - attribute \src "libresoc.v:182079.3-182080.37" + attribute \src "libresoc.v:182612.3-182651.6" + wire width 4 $0\r5__data_o$next[3:0]$11478 + attribute \src "libresoc.v:182367.3-182368.37" wire width 4 $0\r5__data_o[3:0] - attribute \src "libresoc.v:182229.3-182255.6" - wire width 4 $0\reg$next[3:0]$11613 - attribute \src "libresoc.v:182075.3-182076.25" + attribute \src "libresoc.v:182445.3-182471.6" + wire width 4 $0\reg$next[3:0]$11444 + attribute \src "libresoc.v:182363.3-182364.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:182256.3-182295.6" - wire width 4 $0\src15__data_o$next[3:0]$11619 - attribute \src "libresoc.v:182085.3-182086.43" + attribute \src "libresoc.v:182375.3-182414.6" + wire width 4 $0\src15__data_o$next[3:0]$11435 + attribute \src "libresoc.v:182373.3-182374.43" wire width 4 $0\src15__data_o[3:0] - attribute \src "libresoc.v:182326.3-182365.6" - wire width 4 $0\src25__data_o$next[3:0]$11633 - attribute \src "libresoc.v:182083.3-182084.43" + attribute \src "libresoc.v:182472.3-182511.6" + wire width 4 $0\src25__data_o$next[3:0]$11450 + attribute \src "libresoc.v:182371.3-182372.43" wire width 4 $0\src25__data_o[3:0] - attribute \src "libresoc.v:182396.3-182435.6" - wire width 4 $0\src35__data_o$next[3:0]$11647 - attribute \src "libresoc.v:182081.3-182082.43" + attribute \src "libresoc.v:182542.3-182581.6" + wire width 4 $0\src35__data_o$next[3:0]$11464 + attribute \src "libresoc.v:182369.3-182370.43" wire width 4 $0\src35__data_o[3:0] - attribute \src "libresoc.v:182436.3-182465.6" - wire $0\wr_detect$10[0:0]$11655 - attribute \src "libresoc.v:182506.3-182535.6" - wire $0\wr_detect$13[0:0]$11669 - attribute \src "libresoc.v:182199.3-182228.6" - wire $0\wr_detect$16[0:0]$11607 - attribute \src "libresoc.v:182296.3-182325.6" - wire $0\wr_detect$4[0:0]$11627 - attribute \src "libresoc.v:182366.3-182395.6" - wire $0\wr_detect$7[0:0]$11641 - attribute \src "libresoc.v:182129.3-182158.6" + attribute \src "libresoc.v:182652.3-182681.6" + wire $0\wr_detect$10[0:0]$11486 + attribute \src "libresoc.v:182722.3-182751.6" + wire $0\wr_detect$13[0:0]$11500 + attribute \src "libresoc.v:182512.3-182541.6" + wire $0\wr_detect$4[0:0]$11458 + attribute \src "libresoc.v:182582.3-182611.6" + wire $0\wr_detect$7[0:0]$11472 + attribute \src "libresoc.v:182415.3-182444.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:182089.3-182128.6" - wire width 4 $1\cr_pred5__data_o$next[3:0]$11591 - attribute \src "libresoc.v:182001.13-182001.36" - wire width 4 $1\cr_pred5__data_o[3:0] - attribute \src "libresoc.v:182159.3-182198.6" - wire width 4 $1\r25__data_o$next[3:0]$11600 - attribute \src "libresoc.v:182016.13-182016.31" + attribute \src "libresoc.v:182682.3-182721.6" + wire width 4 $1\r25__data_o$next[3:0]$11493 + attribute \src "libresoc.v:182307.13-182307.31" wire width 4 $1\r25__data_o[3:0] - attribute \src "libresoc.v:182466.3-182505.6" - wire width 4 $1\r5__data_o$next[3:0]$11662 - attribute \src "libresoc.v:182023.13-182023.30" + attribute \src "libresoc.v:182612.3-182651.6" + wire width 4 $1\r5__data_o$next[3:0]$11479 + attribute \src "libresoc.v:182314.13-182314.30" wire width 4 $1\r5__data_o[3:0] - attribute \src "libresoc.v:182229.3-182255.6" - wire width 4 $1\reg$next[3:0]$11614 - attribute \src "libresoc.v:182029.13-182029.25" + attribute \src "libresoc.v:182445.3-182471.6" + wire width 4 $1\reg$next[3:0]$11445 + attribute \src "libresoc.v:182320.13-182320.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:182256.3-182295.6" - wire width 4 $1\src15__data_o$next[3:0]$11620 - attribute \src "libresoc.v:182034.13-182034.33" + attribute \src "libresoc.v:182375.3-182414.6" + wire width 4 $1\src15__data_o$next[3:0]$11436 + attribute \src "libresoc.v:182325.13-182325.33" wire width 4 $1\src15__data_o[3:0] - attribute \src "libresoc.v:182326.3-182365.6" - wire width 4 $1\src25__data_o$next[3:0]$11634 - attribute \src "libresoc.v:182041.13-182041.33" + attribute \src "libresoc.v:182472.3-182511.6" + wire width 4 $1\src25__data_o$next[3:0]$11451 + attribute \src "libresoc.v:182332.13-182332.33" wire width 4 $1\src25__data_o[3:0] - attribute \src "libresoc.v:182396.3-182435.6" - wire width 4 $1\src35__data_o$next[3:0]$11648 - attribute \src "libresoc.v:182048.13-182048.33" + attribute \src "libresoc.v:182542.3-182581.6" + wire width 4 $1\src35__data_o$next[3:0]$11465 + attribute \src "libresoc.v:182339.13-182339.33" wire width 4 $1\src35__data_o[3:0] - attribute \src "libresoc.v:182436.3-182465.6" - wire $1\wr_detect$10[0:0]$11656 - attribute \src "libresoc.v:182506.3-182535.6" - wire $1\wr_detect$13[0:0]$11670 - attribute \src "libresoc.v:182199.3-182228.6" - wire $1\wr_detect$16[0:0]$11608 - attribute \src "libresoc.v:182296.3-182325.6" - wire $1\wr_detect$4[0:0]$11628 - attribute \src "libresoc.v:182366.3-182395.6" - wire $1\wr_detect$7[0:0]$11642 - attribute \src "libresoc.v:182129.3-182158.6" + attribute \src "libresoc.v:182652.3-182681.6" + wire $1\wr_detect$10[0:0]$11487 + attribute \src "libresoc.v:182722.3-182751.6" + wire $1\wr_detect$13[0:0]$11501 + attribute \src "libresoc.v:182512.3-182541.6" + wire $1\wr_detect$4[0:0]$11459 + attribute \src "libresoc.v:182582.3-182611.6" + wire $1\wr_detect$7[0:0]$11473 + attribute \src "libresoc.v:182415.3-182444.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:182089.3-182128.6" - wire width 4 $2\cr_pred5__data_o$next[3:0]$11592 - attribute \src "libresoc.v:182159.3-182198.6" - wire width 4 $2\r25__data_o$next[3:0]$11601 - attribute \src "libresoc.v:182466.3-182505.6" - wire width 4 $2\r5__data_o$next[3:0]$11663 - attribute \src "libresoc.v:182229.3-182255.6" - wire width 4 $2\reg$next[3:0]$11615 - attribute \src "libresoc.v:182256.3-182295.6" - wire width 4 $2\src15__data_o$next[3:0]$11621 - attribute \src "libresoc.v:182326.3-182365.6" - wire width 4 $2\src25__data_o$next[3:0]$11635 - attribute \src "libresoc.v:182396.3-182435.6" - wire width 4 $2\src35__data_o$next[3:0]$11649 - attribute \src "libresoc.v:182436.3-182465.6" - wire $2\wr_detect$10[0:0]$11657 - attribute \src "libresoc.v:182506.3-182535.6" - wire $2\wr_detect$13[0:0]$11671 - attribute \src "libresoc.v:182199.3-182228.6" - wire $2\wr_detect$16[0:0]$11609 - attribute \src "libresoc.v:182296.3-182325.6" - wire $2\wr_detect$4[0:0]$11629 - attribute \src "libresoc.v:182366.3-182395.6" - wire $2\wr_detect$7[0:0]$11643 - attribute \src "libresoc.v:182129.3-182158.6" + attribute \src "libresoc.v:182682.3-182721.6" + wire width 4 $2\r25__data_o$next[3:0]$11494 + attribute \src "libresoc.v:182612.3-182651.6" + wire width 4 $2\r5__data_o$next[3:0]$11480 + attribute \src "libresoc.v:182445.3-182471.6" + wire width 4 $2\reg$next[3:0]$11446 + attribute \src "libresoc.v:182375.3-182414.6" + wire width 4 $2\src15__data_o$next[3:0]$11437 + attribute \src "libresoc.v:182472.3-182511.6" + wire width 4 $2\src25__data_o$next[3:0]$11452 + attribute \src "libresoc.v:182542.3-182581.6" + wire width 4 $2\src35__data_o$next[3:0]$11466 + attribute \src "libresoc.v:182652.3-182681.6" + wire $2\wr_detect$10[0:0]$11488 + attribute \src "libresoc.v:182722.3-182751.6" + wire $2\wr_detect$13[0:0]$11502 + attribute \src "libresoc.v:182512.3-182541.6" + wire $2\wr_detect$4[0:0]$11460 + attribute \src "libresoc.v:182582.3-182611.6" + wire $2\wr_detect$7[0:0]$11474 + attribute \src "libresoc.v:182415.3-182444.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:182089.3-182128.6" - wire width 4 $3\cr_pred5__data_o$next[3:0]$11593 - attribute \src "libresoc.v:182159.3-182198.6" - wire width 4 $3\r25__data_o$next[3:0]$11602 - attribute \src "libresoc.v:182466.3-182505.6" - wire width 4 $3\r5__data_o$next[3:0]$11664 - attribute \src "libresoc.v:182229.3-182255.6" - wire width 4 $3\reg$next[3:0]$11616 - attribute \src "libresoc.v:182256.3-182295.6" - wire width 4 $3\src15__data_o$next[3:0]$11622 - attribute \src "libresoc.v:182326.3-182365.6" - wire width 4 $3\src25__data_o$next[3:0]$11636 - attribute \src "libresoc.v:182396.3-182435.6" - wire width 4 $3\src35__data_o$next[3:0]$11650 - attribute \src "libresoc.v:182436.3-182465.6" - wire $3\wr_detect$10[0:0]$11658 - attribute \src "libresoc.v:182506.3-182535.6" - wire $3\wr_detect$13[0:0]$11672 - attribute \src "libresoc.v:182199.3-182228.6" - wire $3\wr_detect$16[0:0]$11610 - attribute \src "libresoc.v:182296.3-182325.6" - wire $3\wr_detect$4[0:0]$11630 - attribute \src "libresoc.v:182366.3-182395.6" - wire $3\wr_detect$7[0:0]$11644 - attribute \src "libresoc.v:182129.3-182158.6" + attribute \src "libresoc.v:182682.3-182721.6" + wire width 4 $3\r25__data_o$next[3:0]$11495 + attribute \src "libresoc.v:182612.3-182651.6" + wire width 4 $3\r5__data_o$next[3:0]$11481 + attribute \src "libresoc.v:182445.3-182471.6" + wire width 4 $3\reg$next[3:0]$11447 + attribute \src "libresoc.v:182375.3-182414.6" + wire width 4 $3\src15__data_o$next[3:0]$11438 + attribute \src "libresoc.v:182472.3-182511.6" + wire width 4 $3\src25__data_o$next[3:0]$11453 + attribute \src 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width 4 $4\src25__data_o$next[3:0]$11637 - attribute \src "libresoc.v:182396.3-182435.6" - wire width 4 $4\src35__data_o$next[3:0]$11651 - attribute \src "libresoc.v:182436.3-182465.6" - wire $4\wr_detect$10[0:0]$11659 - attribute \src "libresoc.v:182506.3-182535.6" - wire $4\wr_detect$13[0:0]$11673 - attribute \src "libresoc.v:182199.3-182228.6" - wire $4\wr_detect$16[0:0]$11611 - attribute \src "libresoc.v:182296.3-182325.6" - wire $4\wr_detect$4[0:0]$11631 - attribute \src "libresoc.v:182366.3-182395.6" - wire $4\wr_detect$7[0:0]$11645 - attribute \src "libresoc.v:182129.3-182158.6" + attribute \src "libresoc.v:182682.3-182721.6" + wire width 4 $4\r25__data_o$next[3:0]$11496 + attribute \src "libresoc.v:182612.3-182651.6" + wire width 4 $4\r5__data_o$next[3:0]$11482 + attribute \src "libresoc.v:182445.3-182471.6" + wire width 4 $4\reg$next[3:0]$11448 + attribute \src "libresoc.v:182375.3-182414.6" + wire width 4 $4\src15__data_o$next[3:0]$11439 + attribute \src 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$not$libresoc.v:182071$11578_Y - attribute \src "libresoc.v:182072.17-182072.100" - wire $not$libresoc.v:182072$11579_Y - attribute \src "libresoc.v:182073.17-182073.103" - wire $not$libresoc.v:182073$11580_Y - attribute \src "libresoc.v:182074.17-182074.103" - wire $not$libresoc.v:182074$11581_Y + attribute \src "libresoc.v:182682.3-182721.6" + wire width 4 $5\r25__data_o$next[3:0]$11497 + attribute \src "libresoc.v:182612.3-182651.6" + wire width 4 $5\r5__data_o$next[3:0]$11483 + attribute \src "libresoc.v:182375.3-182414.6" + wire width 4 $5\src15__data_o$next[3:0]$11440 + attribute \src "libresoc.v:182472.3-182511.6" + wire width 4 $5\src25__data_o$next[3:0]$11455 + attribute \src "libresoc.v:182542.3-182581.6" + wire width 4 $5\src35__data_o$next[3:0]$11469 + attribute \src "libresoc.v:182682.3-182721.6" + wire width 4 $6\r25__data_o$next[3:0]$11498 + attribute \src "libresoc.v:182612.3-182651.6" + wire width 4 $6\r5__data_o$next[3:0]$11484 + attribute \src "libresoc.v:182375.3-182414.6" + wire width 4 $6\src15__data_o$next[3:0]$11441 + attribute \src "libresoc.v:182472.3-182511.6" + wire width 4 $6\src25__data_o$next[3:0]$11456 + attribute \src "libresoc.v:182542.3-182581.6" + wire width 4 $6\src35__data_o$next[3:0]$11470 + attribute \src "libresoc.v:182358.17-182358.104" + wire $not$libresoc.v:182358$11423_Y + attribute \src "libresoc.v:182359.18-182359.105" + wire $not$libresoc.v:182359$11424_Y + attribute \src "libresoc.v:182360.17-182360.100" + wire $not$libresoc.v:182360$11425_Y + attribute \src "libresoc.v:182361.17-182361.103" + wire $not$libresoc.v:182361$11426_Y + attribute \src "libresoc.v:182362.17-182362.103" + wire $not$libresoc.v:182362$11427_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" - wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \cr_pred5__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \cr_pred5__data_o$next + wire width 4 input 9 \dest15__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \cr_pred5__ren + wire input 8 \dest15__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest15__data_i + wire width 4 input 11 \dest25__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest15__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 13 \dest25__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 12 \dest25__wen - attribute \src "libresoc.v:181982.7-181982.15" + wire input 10 \dest25__wen + attribute \src "libresoc.v:182282.7-182282.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 16 \r25__data_o + wire width 4 output 14 \r25__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r25__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \r25__ren + wire input 15 \r25__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r5__data_o + wire width 4 output 12 \r5__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r5__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r5__ren + wire input 13 \r5__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src15__data_o + wire width 4 output 3 \src15__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src15__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src15__ren + wire input 2 \src15__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src25__data_o + wire width 4 output 5 \src25__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src25__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src25__ren + wire input 4 \src25__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 9 \src35__data_o + wire width 4 output 7 \src35__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src35__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \src35__ren + wire input 6 \src35__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 18 \w5__data_i + wire width 4 input 16 \w5__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 19 \w5__wen + wire input 17 \w5__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -374687,257 +340196,232 @@ module \reg_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182069$11576 + cell $not $not$libresoc.v:182358$11423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:182069$11576_Y + connect \Y $not$libresoc.v:182358$11423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182070$11577 + cell $not $not$libresoc.v:182359$11424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:182070$11577_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182071$11578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$16 - connect \Y $not$libresoc.v:182071$11578_Y + connect \Y $not$libresoc.v:182359$11424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182072$11579 + cell $not $not$libresoc.v:182360$11425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:182072$11579_Y + connect \Y $not$libresoc.v:182360$11425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182073$11580 + cell $not $not$libresoc.v:182361$11426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:182073$11580_Y + connect \Y $not$libresoc.v:182361$11426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182074$11581 + cell $not $not$libresoc.v:182362$11427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:182074$11581_Y + connect \Y $not$libresoc.v:182362$11427_Y end - attribute \src "libresoc.v:181982.7-181982.20" - process $proc$libresoc.v:181982$11674 + attribute \src "libresoc.v:182282.7-182282.20" + process $proc$libresoc.v:182282$11505 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182001.13-182001.36" - process $proc$libresoc.v:182001$11675 - assign { } { } - assign $1\cr_pred5__data_o[3:0] 4'0000 - sync always - sync init - update \cr_pred5__data_o $1\cr_pred5__data_o[3:0] - end - attribute \src "libresoc.v:182016.13-182016.31" - process $proc$libresoc.v:182016$11676 + attribute \src "libresoc.v:182307.13-182307.31" + process $proc$libresoc.v:182307$11506 assign { } { } assign $1\r25__data_o[3:0] 4'0000 sync always sync init update \r25__data_o $1\r25__data_o[3:0] end - attribute \src "libresoc.v:182023.13-182023.30" - process $proc$libresoc.v:182023$11677 + attribute \src "libresoc.v:182314.13-182314.30" + process $proc$libresoc.v:182314$11507 assign { } { } assign $1\r5__data_o[3:0] 4'0000 sync always sync init update \r5__data_o $1\r5__data_o[3:0] end - attribute \src "libresoc.v:182029.13-182029.25" - process $proc$libresoc.v:182029$11678 + attribute \src "libresoc.v:182320.13-182320.25" + process $proc$libresoc.v:182320$11508 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:182034.13-182034.33" - process $proc$libresoc.v:182034$11679 + attribute \src "libresoc.v:182325.13-182325.33" + process $proc$libresoc.v:182325$11509 assign { } { } assign $1\src15__data_o[3:0] 4'0000 sync always sync init update \src15__data_o $1\src15__data_o[3:0] end - attribute \src "libresoc.v:182041.13-182041.33" - process $proc$libresoc.v:182041$11680 + attribute \src "libresoc.v:182332.13-182332.33" + process $proc$libresoc.v:182332$11510 assign { } { } assign $1\src25__data_o[3:0] 4'0000 sync always sync init update \src25__data_o $1\src25__data_o[3:0] end - attribute \src "libresoc.v:182048.13-182048.33" - process $proc$libresoc.v:182048$11681 + attribute \src "libresoc.v:182339.13-182339.33" + process $proc$libresoc.v:182339$11511 assign { } { } assign $1\src35__data_o[3:0] 4'0000 sync always sync init update \src35__data_o $1\src35__data_o[3:0] end - attribute \src "libresoc.v:182075.3-182076.25" - process $proc$libresoc.v:182075$11582 + attribute \src "libresoc.v:182363.3-182364.25" + process $proc$libresoc.v:182363$11428 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:182077.3-182078.39" - process $proc$libresoc.v:182077$11583 + attribute \src "libresoc.v:182365.3-182366.39" + process $proc$libresoc.v:182365$11429 assign { } { } assign $0\r25__data_o[3:0] \r25__data_o$next sync posedge \coresync_clk update \r25__data_o $0\r25__data_o[3:0] end - attribute \src "libresoc.v:182079.3-182080.37" - process $proc$libresoc.v:182079$11584 + attribute \src "libresoc.v:182367.3-182368.37" + process $proc$libresoc.v:182367$11430 assign { } { } assign $0\r5__data_o[3:0] \r5__data_o$next sync posedge \coresync_clk update \r5__data_o $0\r5__data_o[3:0] end - attribute \src "libresoc.v:182081.3-182082.43" - process $proc$libresoc.v:182081$11585 + attribute \src "libresoc.v:182369.3-182370.43" + process $proc$libresoc.v:182369$11431 assign { } { } assign $0\src35__data_o[3:0] \src35__data_o$next sync posedge \coresync_clk update \src35__data_o $0\src35__data_o[3:0] end - attribute \src "libresoc.v:182083.3-182084.43" - process $proc$libresoc.v:182083$11586 + attribute \src "libresoc.v:182371.3-182372.43" + process $proc$libresoc.v:182371$11432 assign { } { } assign $0\src25__data_o[3:0] \src25__data_o$next sync posedge \coresync_clk update \src25__data_o $0\src25__data_o[3:0] end - attribute \src "libresoc.v:182085.3-182086.43" - process $proc$libresoc.v:182085$11587 + attribute \src "libresoc.v:182373.3-182374.43" + process $proc$libresoc.v:182373$11433 assign { } { } assign $0\src15__data_o[3:0] \src15__data_o$next sync posedge \coresync_clk update \src15__data_o $0\src15__data_o[3:0] end - attribute \src "libresoc.v:182087.3-182088.49" - process $proc$libresoc.v:182087$11588 - assign { } { } - assign $0\cr_pred5__data_o[3:0] \cr_pred5__data_o$next - sync posedge \coresync_clk - update \cr_pred5__data_o $0\cr_pred5__data_o[3:0] - end - attribute \src "libresoc.v:182089.3-182128.6" - process $proc$libresoc.v:182089$11589 + attribute \src "libresoc.v:182375.3-182414.6" + process $proc$libresoc.v:182375$11434 assign { } { } assign { } { } assign { } { } - assign $0\cr_pred5__data_o$next[3:0]$11590 $6\cr_pred5__data_o$next[3:0]$11596 - attribute \src "libresoc.v:182090.5-182090.29" + assign $0\src15__data_o$next[3:0]$11435 $6\src15__data_o$next[3:0]$11441 + attribute \src "libresoc.v:182376.5-182376.29" switch \initial - attribute \src "libresoc.v:182090.9-182090.17" + attribute \src "libresoc.v:182376.9-182376.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred5__ren + switch \src15__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\cr_pred5__data_o$next[3:0]$11591 $5\cr_pred5__data_o$next[3:0]$11595 + assign $1\src15__data_o$next[3:0]$11436 $5\src15__data_o$next[3:0]$11440 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred5__data_o$next[3:0]$11592 \dest15__data_i + assign $2\src15__data_o$next[3:0]$11437 \dest15__data_i case - assign $2\cr_pred5__data_o$next[3:0]$11592 4'0000 + assign $2\src15__data_o$next[3:0]$11437 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred5__data_o$next[3:0]$11593 \dest25__data_i + assign $3\src15__data_o$next[3:0]$11438 \dest25__data_i case - assign $3\cr_pred5__data_o$next[3:0]$11593 $2\cr_pred5__data_o$next[3:0]$11592 + assign $3\src15__data_o$next[3:0]$11438 $2\src15__data_o$next[3:0]$11437 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred5__data_o$next[3:0]$11594 \w5__data_i + assign $4\src15__data_o$next[3:0]$11439 \w5__data_i case - assign $4\cr_pred5__data_o$next[3:0]$11594 $3\cr_pred5__data_o$next[3:0]$11593 + assign $4\src15__data_o$next[3:0]$11439 $3\src15__data_o$next[3:0]$11438 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred5__data_o$next[3:0]$11595 \reg + assign $5\src15__data_o$next[3:0]$11440 \reg case - assign $5\cr_pred5__data_o$next[3:0]$11595 $4\cr_pred5__data_o$next[3:0]$11594 + assign $5\src15__data_o$next[3:0]$11440 $4\src15__data_o$next[3:0]$11439 end case - assign $1\cr_pred5__data_o$next[3:0]$11591 4'0000 + assign $1\src15__data_o$next[3:0]$11436 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred5__data_o$next[3:0]$11596 4'0000 + assign $6\src15__data_o$next[3:0]$11441 4'0000 case - assign $6\cr_pred5__data_o$next[3:0]$11596 $1\cr_pred5__data_o$next[3:0]$11591 + assign $6\src15__data_o$next[3:0]$11441 $1\src15__data_o$next[3:0]$11436 end sync always - update \cr_pred5__data_o$next $0\cr_pred5__data_o$next[3:0]$11590 + update \src15__data_o$next $0\src15__data_o$next[3:0]$11435 end - attribute \src "libresoc.v:182129.3-182158.6" - process $proc$libresoc.v:182129$11597 + attribute \src "libresoc.v:182415.3-182444.6" + process $proc$libresoc.v:182415$11442 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:182130.5-182130.29" + attribute \src "libresoc.v:182416.5-182416.29" switch \initial - attribute \src "libresoc.v:182130.9-182130.17" + attribute \src "libresoc.v:182416.9-182416.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred5__ren + switch \src15__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -374978,142 +340462,17 @@ module \reg_5 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:182159.3-182198.6" - process $proc$libresoc.v:182159$11598 - assign { } { } - assign { } { } - assign { } { } - assign $0\r25__data_o$next[3:0]$11599 $6\r25__data_o$next[3:0]$11605 - attribute \src "libresoc.v:182160.5-182160.29" - switch \initial - attribute \src "libresoc.v:182160.9-182160.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r25__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r25__data_o$next[3:0]$11600 $5\r25__data_o$next[3:0]$11604 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r25__data_o$next[3:0]$11601 \dest15__data_i - case - assign $2\r25__data_o$next[3:0]$11601 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r25__data_o$next[3:0]$11602 \dest25__data_i - case - assign $3\r25__data_o$next[3:0]$11602 $2\r25__data_o$next[3:0]$11601 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r25__data_o$next[3:0]$11603 \w5__data_i - case - assign $4\r25__data_o$next[3:0]$11603 $3\r25__data_o$next[3:0]$11602 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r25__data_o$next[3:0]$11604 \reg - case - assign $5\r25__data_o$next[3:0]$11604 $4\r25__data_o$next[3:0]$11603 - end - case - assign $1\r25__data_o$next[3:0]$11600 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r25__data_o$next[3:0]$11605 4'0000 - case - assign $6\r25__data_o$next[3:0]$11605 $1\r25__data_o$next[3:0]$11600 - end - sync always - update \r25__data_o$next $0\r25__data_o$next[3:0]$11599 - end - attribute \src "libresoc.v:182199.3-182228.6" - process $proc$libresoc.v:182199$11606 - assign { } { } - assign { } { } - assign $0\wr_detect$16[0:0]$11607 $1\wr_detect$16[0:0]$11608 - attribute \src "libresoc.v:182200.5-182200.29" - switch \initial - attribute \src "libresoc.v:182200.9-182200.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r25__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$16[0:0]$11608 $4\wr_detect$16[0:0]$11611 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$16[0:0]$11609 1'1 - case - assign $2\wr_detect$16[0:0]$11609 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$16[0:0]$11610 1'1 - case - assign $3\wr_detect$16[0:0]$11610 $2\wr_detect$16[0:0]$11609 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$16[0:0]$11611 1'1 - case - assign $4\wr_detect$16[0:0]$11611 $3\wr_detect$16[0:0]$11610 - end - case - assign $1\wr_detect$16[0:0]$11608 1'0 - end - sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$11607 - end - attribute \src "libresoc.v:182229.3-182255.6" - process $proc$libresoc.v:182229$11612 + attribute \src "libresoc.v:182445.3-182471.6" + process $proc$libresoc.v:182445$11443 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11613 $4\reg$next[3:0]$11617 - attribute \src "libresoc.v:182230.5-182230.29" + assign $0\reg$next[3:0]$11444 $4\reg$next[3:0]$11448 + attribute \src "libresoc.v:182446.5-182446.29" switch \initial - attribute \src "libresoc.v:182230.9-182230.17" + attribute \src "libresoc.v:182446.9-182446.17" case 1'1 case end @@ -375122,818 +340481,779 @@ module \reg_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11614 \dest15__data_i + assign $1\reg$next[3:0]$11445 \dest15__data_i case - assign $1\reg$next[3:0]$11614 \reg + assign $1\reg$next[3:0]$11445 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11615 \dest25__data_i + assign $2\reg$next[3:0]$11446 \dest25__data_i case - assign $2\reg$next[3:0]$11615 $1\reg$next[3:0]$11614 + assign $2\reg$next[3:0]$11446 $1\reg$next[3:0]$11445 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11616 \w5__data_i + assign $3\reg$next[3:0]$11447 \w5__data_i case - assign $3\reg$next[3:0]$11616 $2\reg$next[3:0]$11615 + assign $3\reg$next[3:0]$11447 $2\reg$next[3:0]$11446 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11617 4'0000 + assign $4\reg$next[3:0]$11448 4'0000 case - assign $4\reg$next[3:0]$11617 $3\reg$next[3:0]$11616 + assign $4\reg$next[3:0]$11448 $3\reg$next[3:0]$11447 end sync always - update \reg$next $0\reg$next[3:0]$11613 + update \reg$next $0\reg$next[3:0]$11444 end - attribute \src "libresoc.v:182256.3-182295.6" - process $proc$libresoc.v:182256$11618 + attribute \src "libresoc.v:182472.3-182511.6" + process $proc$libresoc.v:182472$11449 assign { } { } assign { } { } assign { } { } - assign $0\src15__data_o$next[3:0]$11619 $6\src15__data_o$next[3:0]$11625 - attribute \src "libresoc.v:182257.5-182257.29" + assign $0\src25__data_o$next[3:0]$11450 $6\src25__data_o$next[3:0]$11456 + attribute \src "libresoc.v:182473.5-182473.29" switch \initial - attribute \src "libresoc.v:182257.9-182257.17" + attribute \src "libresoc.v:182473.9-182473.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src15__ren + switch \src25__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src15__data_o$next[3:0]$11620 $5\src15__data_o$next[3:0]$11624 + assign $1\src25__data_o$next[3:0]$11451 $5\src25__data_o$next[3:0]$11455 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src15__data_o$next[3:0]$11621 \dest15__data_i + assign $2\src25__data_o$next[3:0]$11452 \dest15__data_i case - assign $2\src15__data_o$next[3:0]$11621 4'0000 + assign $2\src25__data_o$next[3:0]$11452 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src15__data_o$next[3:0]$11622 \dest25__data_i + assign $3\src25__data_o$next[3:0]$11453 \dest25__data_i case - assign $3\src15__data_o$next[3:0]$11622 $2\src15__data_o$next[3:0]$11621 + assign $3\src25__data_o$next[3:0]$11453 $2\src25__data_o$next[3:0]$11452 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src15__data_o$next[3:0]$11623 \w5__data_i + assign $4\src25__data_o$next[3:0]$11454 \w5__data_i case - assign $4\src15__data_o$next[3:0]$11623 $3\src15__data_o$next[3:0]$11622 + assign $4\src25__data_o$next[3:0]$11454 $3\src25__data_o$next[3:0]$11453 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src15__data_o$next[3:0]$11624 \reg + assign $5\src25__data_o$next[3:0]$11455 \reg case - assign $5\src15__data_o$next[3:0]$11624 $4\src15__data_o$next[3:0]$11623 + assign $5\src25__data_o$next[3:0]$11455 $4\src25__data_o$next[3:0]$11454 end case - assign $1\src15__data_o$next[3:0]$11620 4'0000 + assign $1\src25__data_o$next[3:0]$11451 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src15__data_o$next[3:0]$11625 4'0000 + assign $6\src25__data_o$next[3:0]$11456 4'0000 case - assign $6\src15__data_o$next[3:0]$11625 $1\src15__data_o$next[3:0]$11620 + assign $6\src25__data_o$next[3:0]$11456 $1\src25__data_o$next[3:0]$11451 end sync always - update \src15__data_o$next $0\src15__data_o$next[3:0]$11619 + update \src25__data_o$next $0\src25__data_o$next[3:0]$11450 end - attribute \src "libresoc.v:182296.3-182325.6" - process $proc$libresoc.v:182296$11626 + attribute \src "libresoc.v:182512.3-182541.6" + process $proc$libresoc.v:182512$11457 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11627 $1\wr_detect$4[0:0]$11628 - attribute \src "libresoc.v:182297.5-182297.29" + assign $0\wr_detect$4[0:0]$11458 $1\wr_detect$4[0:0]$11459 + attribute \src "libresoc.v:182513.5-182513.29" switch \initial - attribute \src "libresoc.v:182297.9-182297.17" + attribute \src "libresoc.v:182513.9-182513.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src15__ren + switch \src25__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11628 $4\wr_detect$4[0:0]$11631 + assign $1\wr_detect$4[0:0]$11459 $4\wr_detect$4[0:0]$11462 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11629 1'1 + assign $2\wr_detect$4[0:0]$11460 1'1 case - assign $2\wr_detect$4[0:0]$11629 1'0 + assign $2\wr_detect$4[0:0]$11460 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11630 1'1 + assign $3\wr_detect$4[0:0]$11461 1'1 case - assign $3\wr_detect$4[0:0]$11630 $2\wr_detect$4[0:0]$11629 + assign $3\wr_detect$4[0:0]$11461 $2\wr_detect$4[0:0]$11460 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11631 1'1 + assign $4\wr_detect$4[0:0]$11462 1'1 case - assign $4\wr_detect$4[0:0]$11631 $3\wr_detect$4[0:0]$11630 + assign $4\wr_detect$4[0:0]$11462 $3\wr_detect$4[0:0]$11461 end case - assign $1\wr_detect$4[0:0]$11628 1'0 + assign $1\wr_detect$4[0:0]$11459 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11627 + update \wr_detect$4 $0\wr_detect$4[0:0]$11458 end - attribute \src "libresoc.v:182326.3-182365.6" - process $proc$libresoc.v:182326$11632 + attribute \src "libresoc.v:182542.3-182581.6" + process $proc$libresoc.v:182542$11463 assign { } { } assign { } { } assign { } { } - assign $0\src25__data_o$next[3:0]$11633 $6\src25__data_o$next[3:0]$11639 - attribute \src "libresoc.v:182327.5-182327.29" + assign $0\src35__data_o$next[3:0]$11464 $6\src35__data_o$next[3:0]$11470 + attribute \src "libresoc.v:182543.5-182543.29" switch \initial - attribute \src "libresoc.v:182327.9-182327.17" + attribute \src "libresoc.v:182543.9-182543.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src25__ren + switch \src35__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src25__data_o$next[3:0]$11634 $5\src25__data_o$next[3:0]$11638 + assign $1\src35__data_o$next[3:0]$11465 $5\src35__data_o$next[3:0]$11469 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src25__data_o$next[3:0]$11635 \dest15__data_i + assign $2\src35__data_o$next[3:0]$11466 \dest15__data_i case - assign $2\src25__data_o$next[3:0]$11635 4'0000 + assign $2\src35__data_o$next[3:0]$11466 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src25__data_o$next[3:0]$11636 \dest25__data_i + assign $3\src35__data_o$next[3:0]$11467 \dest25__data_i case - assign $3\src25__data_o$next[3:0]$11636 $2\src25__data_o$next[3:0]$11635 + assign $3\src35__data_o$next[3:0]$11467 $2\src35__data_o$next[3:0]$11466 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src25__data_o$next[3:0]$11637 \w5__data_i + assign $4\src35__data_o$next[3:0]$11468 \w5__data_i case - assign $4\src25__data_o$next[3:0]$11637 $3\src25__data_o$next[3:0]$11636 + assign $4\src35__data_o$next[3:0]$11468 $3\src35__data_o$next[3:0]$11467 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src25__data_o$next[3:0]$11638 \reg + assign $5\src35__data_o$next[3:0]$11469 \reg case - assign $5\src25__data_o$next[3:0]$11638 $4\src25__data_o$next[3:0]$11637 + assign $5\src35__data_o$next[3:0]$11469 $4\src35__data_o$next[3:0]$11468 end case - assign $1\src25__data_o$next[3:0]$11634 4'0000 + assign $1\src35__data_o$next[3:0]$11465 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src25__data_o$next[3:0]$11639 4'0000 + assign $6\src35__data_o$next[3:0]$11470 4'0000 case - assign $6\src25__data_o$next[3:0]$11639 $1\src25__data_o$next[3:0]$11634 + assign $6\src35__data_o$next[3:0]$11470 $1\src35__data_o$next[3:0]$11465 end sync always - update \src25__data_o$next $0\src25__data_o$next[3:0]$11633 + update \src35__data_o$next $0\src35__data_o$next[3:0]$11464 end - attribute \src "libresoc.v:182366.3-182395.6" - process $proc$libresoc.v:182366$11640 + attribute \src "libresoc.v:182582.3-182611.6" + process $proc$libresoc.v:182582$11471 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11641 $1\wr_detect$7[0:0]$11642 - attribute \src "libresoc.v:182367.5-182367.29" + assign $0\wr_detect$7[0:0]$11472 $1\wr_detect$7[0:0]$11473 + attribute \src "libresoc.v:182583.5-182583.29" switch \initial - attribute \src "libresoc.v:182367.9-182367.17" + attribute \src "libresoc.v:182583.9-182583.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src25__ren + switch \src35__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11642 $4\wr_detect$7[0:0]$11645 + assign $1\wr_detect$7[0:0]$11473 $4\wr_detect$7[0:0]$11476 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11643 1'1 + assign $2\wr_detect$7[0:0]$11474 1'1 case - assign $2\wr_detect$7[0:0]$11643 1'0 + assign $2\wr_detect$7[0:0]$11474 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11644 1'1 + assign $3\wr_detect$7[0:0]$11475 1'1 case - assign $3\wr_detect$7[0:0]$11644 $2\wr_detect$7[0:0]$11643 + assign $3\wr_detect$7[0:0]$11475 $2\wr_detect$7[0:0]$11474 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11645 1'1 + assign $4\wr_detect$7[0:0]$11476 1'1 case - assign $4\wr_detect$7[0:0]$11645 $3\wr_detect$7[0:0]$11644 + assign $4\wr_detect$7[0:0]$11476 $3\wr_detect$7[0:0]$11475 end case - assign $1\wr_detect$7[0:0]$11642 1'0 + assign $1\wr_detect$7[0:0]$11473 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11641 + update \wr_detect$7 $0\wr_detect$7[0:0]$11472 end - attribute \src "libresoc.v:182396.3-182435.6" - process $proc$libresoc.v:182396$11646 + attribute \src "libresoc.v:182612.3-182651.6" + process $proc$libresoc.v:182612$11477 assign { } { } assign { } { } assign { } { } - assign $0\src35__data_o$next[3:0]$11647 $6\src35__data_o$next[3:0]$11653 - attribute \src "libresoc.v:182397.5-182397.29" + assign $0\r5__data_o$next[3:0]$11478 $6\r5__data_o$next[3:0]$11484 + attribute \src "libresoc.v:182613.5-182613.29" switch \initial - attribute \src "libresoc.v:182397.9-182397.17" + attribute \src "libresoc.v:182613.9-182613.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src35__ren + switch \r5__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src35__data_o$next[3:0]$11648 $5\src35__data_o$next[3:0]$11652 + assign $1\r5__data_o$next[3:0]$11479 $5\r5__data_o$next[3:0]$11483 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src35__data_o$next[3:0]$11649 \dest15__data_i + assign $2\r5__data_o$next[3:0]$11480 \dest15__data_i case - assign $2\src35__data_o$next[3:0]$11649 4'0000 + assign $2\r5__data_o$next[3:0]$11480 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src35__data_o$next[3:0]$11650 \dest25__data_i + assign $3\r5__data_o$next[3:0]$11481 \dest25__data_i case - assign $3\src35__data_o$next[3:0]$11650 $2\src35__data_o$next[3:0]$11649 + assign $3\r5__data_o$next[3:0]$11481 $2\r5__data_o$next[3:0]$11480 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src35__data_o$next[3:0]$11651 \w5__data_i + assign $4\r5__data_o$next[3:0]$11482 \w5__data_i case - assign $4\src35__data_o$next[3:0]$11651 $3\src35__data_o$next[3:0]$11650 + assign $4\r5__data_o$next[3:0]$11482 $3\r5__data_o$next[3:0]$11481 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src35__data_o$next[3:0]$11652 \reg + assign $5\r5__data_o$next[3:0]$11483 \reg case - assign $5\src35__data_o$next[3:0]$11652 $4\src35__data_o$next[3:0]$11651 + assign $5\r5__data_o$next[3:0]$11483 $4\r5__data_o$next[3:0]$11482 end case - assign $1\src35__data_o$next[3:0]$11648 4'0000 + assign $1\r5__data_o$next[3:0]$11479 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src35__data_o$next[3:0]$11653 4'0000 + assign $6\r5__data_o$next[3:0]$11484 4'0000 case - assign $6\src35__data_o$next[3:0]$11653 $1\src35__data_o$next[3:0]$11648 + assign $6\r5__data_o$next[3:0]$11484 $1\r5__data_o$next[3:0]$11479 end sync always - update \src35__data_o$next $0\src35__data_o$next[3:0]$11647 + update \r5__data_o$next $0\r5__data_o$next[3:0]$11478 end - attribute \src "libresoc.v:182436.3-182465.6" - process $proc$libresoc.v:182436$11654 + attribute \src "libresoc.v:182652.3-182681.6" + process $proc$libresoc.v:182652$11485 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11655 $1\wr_detect$10[0:0]$11656 - attribute \src "libresoc.v:182437.5-182437.29" + assign $0\wr_detect$10[0:0]$11486 $1\wr_detect$10[0:0]$11487 + attribute \src "libresoc.v:182653.5-182653.29" switch \initial - attribute \src "libresoc.v:182437.9-182437.17" + attribute \src "libresoc.v:182653.9-182653.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src35__ren + switch \r5__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11656 $4\wr_detect$10[0:0]$11659 + assign $1\wr_detect$10[0:0]$11487 $4\wr_detect$10[0:0]$11490 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11657 1'1 + assign $2\wr_detect$10[0:0]$11488 1'1 case - assign $2\wr_detect$10[0:0]$11657 1'0 + assign $2\wr_detect$10[0:0]$11488 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11658 1'1 + assign $3\wr_detect$10[0:0]$11489 1'1 case - assign $3\wr_detect$10[0:0]$11658 $2\wr_detect$10[0:0]$11657 + assign $3\wr_detect$10[0:0]$11489 $2\wr_detect$10[0:0]$11488 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11659 1'1 + assign $4\wr_detect$10[0:0]$11490 1'1 case - assign $4\wr_detect$10[0:0]$11659 $3\wr_detect$10[0:0]$11658 + assign $4\wr_detect$10[0:0]$11490 $3\wr_detect$10[0:0]$11489 end case - assign $1\wr_detect$10[0:0]$11656 1'0 + assign $1\wr_detect$10[0:0]$11487 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11655 + update \wr_detect$10 $0\wr_detect$10[0:0]$11486 end - attribute \src "libresoc.v:182466.3-182505.6" - process $proc$libresoc.v:182466$11660 + attribute \src "libresoc.v:182682.3-182721.6" + process $proc$libresoc.v:182682$11491 assign { } { } assign { } { } assign { } { } - assign $0\r5__data_o$next[3:0]$11661 $6\r5__data_o$next[3:0]$11667 - attribute \src "libresoc.v:182467.5-182467.29" + assign $0\r25__data_o$next[3:0]$11492 $6\r25__data_o$next[3:0]$11498 + attribute \src "libresoc.v:182683.5-182683.29" switch \initial - attribute \src "libresoc.v:182467.9-182467.17" + attribute \src "libresoc.v:182683.9-182683.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r5__ren + switch \r25__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r5__data_o$next[3:0]$11662 $5\r5__data_o$next[3:0]$11666 + assign $1\r25__data_o$next[3:0]$11493 $5\r25__data_o$next[3:0]$11497 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r5__data_o$next[3:0]$11663 \dest15__data_i + assign $2\r25__data_o$next[3:0]$11494 \dest15__data_i case - assign $2\r5__data_o$next[3:0]$11663 4'0000 + assign $2\r25__data_o$next[3:0]$11494 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r5__data_o$next[3:0]$11664 \dest25__data_i + assign $3\r25__data_o$next[3:0]$11495 \dest25__data_i case - assign $3\r5__data_o$next[3:0]$11664 $2\r5__data_o$next[3:0]$11663 + assign $3\r25__data_o$next[3:0]$11495 $2\r25__data_o$next[3:0]$11494 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r5__data_o$next[3:0]$11665 \w5__data_i + assign $4\r25__data_o$next[3:0]$11496 \w5__data_i case - assign $4\r5__data_o$next[3:0]$11665 $3\r5__data_o$next[3:0]$11664 + assign $4\r25__data_o$next[3:0]$11496 $3\r25__data_o$next[3:0]$11495 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r5__data_o$next[3:0]$11666 \reg + assign $5\r25__data_o$next[3:0]$11497 \reg case - assign $5\r5__data_o$next[3:0]$11666 $4\r5__data_o$next[3:0]$11665 + assign $5\r25__data_o$next[3:0]$11497 $4\r25__data_o$next[3:0]$11496 end case - assign $1\r5__data_o$next[3:0]$11662 4'0000 + assign $1\r25__data_o$next[3:0]$11493 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r5__data_o$next[3:0]$11667 4'0000 + assign $6\r25__data_o$next[3:0]$11498 4'0000 case - assign $6\r5__data_o$next[3:0]$11667 $1\r5__data_o$next[3:0]$11662 + assign $6\r25__data_o$next[3:0]$11498 $1\r25__data_o$next[3:0]$11493 end sync always - update \r5__data_o$next $0\r5__data_o$next[3:0]$11661 + update \r25__data_o$next $0\r25__data_o$next[3:0]$11492 end - attribute \src "libresoc.v:182506.3-182535.6" - process $proc$libresoc.v:182506$11668 + attribute \src "libresoc.v:182722.3-182751.6" + process $proc$libresoc.v:182722$11499 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11669 $1\wr_detect$13[0:0]$11670 - attribute \src "libresoc.v:182507.5-182507.29" + assign $0\wr_detect$13[0:0]$11500 $1\wr_detect$13[0:0]$11501 + attribute \src "libresoc.v:182723.5-182723.29" switch \initial - attribute \src "libresoc.v:182507.9-182507.17" + attribute \src "libresoc.v:182723.9-182723.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r5__ren + switch \r25__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11670 $4\wr_detect$13[0:0]$11673 + assign $1\wr_detect$13[0:0]$11501 $4\wr_detect$13[0:0]$11504 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11671 1'1 + assign $2\wr_detect$13[0:0]$11502 1'1 case - assign $2\wr_detect$13[0:0]$11671 1'0 + assign $2\wr_detect$13[0:0]$11502 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11672 1'1 + assign $3\wr_detect$13[0:0]$11503 1'1 case - assign $3\wr_detect$13[0:0]$11672 $2\wr_detect$13[0:0]$11671 + assign $3\wr_detect$13[0:0]$11503 $2\wr_detect$13[0:0]$11502 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11673 1'1 + assign $4\wr_detect$13[0:0]$11504 1'1 case - assign $4\wr_detect$13[0:0]$11673 $3\wr_detect$13[0:0]$11672 + assign $4\wr_detect$13[0:0]$11504 $3\wr_detect$13[0:0]$11503 end case - assign $1\wr_detect$13[0:0]$11670 1'0 + assign $1\wr_detect$13[0:0]$11501 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11669 + update \wr_detect$13 $0\wr_detect$13[0:0]$11500 end - connect \$9 $not$libresoc.v:182069$11576_Y - connect \$12 $not$libresoc.v:182070$11577_Y - connect \$15 $not$libresoc.v:182071$11578_Y - connect \$1 $not$libresoc.v:182072$11579_Y - connect \$3 $not$libresoc.v:182073$11580_Y - connect \$6 $not$libresoc.v:182074$11581_Y + connect \$9 $not$libresoc.v:182358$11423_Y + connect \$12 $not$libresoc.v:182359$11424_Y + connect \$1 $not$libresoc.v:182360$11425_Y + connect \$3 $not$libresoc.v:182361$11426_Y + connect \$6 $not$libresoc.v:182362$11427_Y end -attribute \src "libresoc.v:182540.1-183095.10" +attribute \src "libresoc.v:182756.1-183227.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" attribute \generator "nMigen" module \reg_6 - attribute \src "libresoc.v:182648.3-182687.6" - wire width 4 $0\cr_pred6__data_o$next[3:0]$11696 - attribute \src "libresoc.v:182646.3-182647.49" - wire width 4 $0\cr_pred6__data_o[3:0] - attribute \src "libresoc.v:182541.7-182541.20" + attribute \src "libresoc.v:182757.7-182757.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182718.3-182757.6" - wire width 4 $0\r26__data_o$next[3:0]$11705 - attribute \src "libresoc.v:182636.3-182637.39" + attribute \src "libresoc.v:183157.3-183196.6" + wire width 4 $0\r26__data_o$next[3:0]$11581 + attribute \src "libresoc.v:182840.3-182841.39" wire width 4 $0\r26__data_o[3:0] - attribute \src "libresoc.v:183025.3-183064.6" - wire width 4 $0\r6__data_o$next[3:0]$11767 - attribute \src "libresoc.v:182638.3-182639.37" + attribute \src "libresoc.v:183087.3-183126.6" + wire width 4 $0\r6__data_o$next[3:0]$11567 + attribute \src "libresoc.v:182842.3-182843.37" wire width 4 $0\r6__data_o[3:0] - attribute \src "libresoc.v:182788.3-182814.6" - wire width 4 $0\reg$next[3:0]$11719 - attribute \src "libresoc.v:182634.3-182635.25" + attribute \src "libresoc.v:182920.3-182946.6" + wire width 4 $0\reg$next[3:0]$11533 + attribute \src "libresoc.v:182838.3-182839.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:182815.3-182854.6" - wire width 4 $0\src16__data_o$next[3:0]$11725 - attribute \src "libresoc.v:182644.3-182645.43" + attribute \src "libresoc.v:182850.3-182889.6" + wire width 4 $0\src16__data_o$next[3:0]$11524 + attribute \src "libresoc.v:182848.3-182849.43" wire width 4 $0\src16__data_o[3:0] - attribute \src "libresoc.v:182885.3-182924.6" - wire width 4 $0\src26__data_o$next[3:0]$11739 - attribute \src "libresoc.v:182642.3-182643.43" + attribute \src "libresoc.v:182947.3-182986.6" + wire width 4 $0\src26__data_o$next[3:0]$11539 + attribute \src "libresoc.v:182846.3-182847.43" wire width 4 $0\src26__data_o[3:0] - attribute \src "libresoc.v:182955.3-182994.6" - wire width 4 $0\src36__data_o$next[3:0]$11753 - attribute \src "libresoc.v:182640.3-182641.43" + attribute \src "libresoc.v:183017.3-183056.6" + wire width 4 $0\src36__data_o$next[3:0]$11553 + attribute \src "libresoc.v:182844.3-182845.43" wire width 4 $0\src36__data_o[3:0] - attribute \src "libresoc.v:182995.3-183024.6" - wire $0\wr_detect$10[0:0]$11761 - attribute \src "libresoc.v:183065.3-183094.6" - wire $0\wr_detect$13[0:0]$11775 - attribute \src "libresoc.v:182758.3-182787.6" - wire $0\wr_detect$16[0:0]$11713 - attribute \src "libresoc.v:182855.3-182884.6" - wire $0\wr_detect$4[0:0]$11733 - attribute \src "libresoc.v:182925.3-182954.6" - wire $0\wr_detect$7[0:0]$11747 - attribute \src "libresoc.v:182688.3-182717.6" + attribute \src "libresoc.v:183127.3-183156.6" + wire $0\wr_detect$10[0:0]$11575 + attribute \src "libresoc.v:183197.3-183226.6" + wire $0\wr_detect$13[0:0]$11589 + attribute \src "libresoc.v:182987.3-183016.6" + wire $0\wr_detect$4[0:0]$11547 + attribute \src "libresoc.v:183057.3-183086.6" + wire $0\wr_detect$7[0:0]$11561 + attribute \src "libresoc.v:182890.3-182919.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:182648.3-182687.6" - wire width 4 $1\cr_pred6__data_o$next[3:0]$11697 - attribute \src "libresoc.v:182560.13-182560.36" - wire width 4 $1\cr_pred6__data_o[3:0] - attribute \src "libresoc.v:182718.3-182757.6" - wire width 4 $1\r26__data_o$next[3:0]$11706 - attribute \src "libresoc.v:182575.13-182575.31" + attribute \src "libresoc.v:183157.3-183196.6" + wire width 4 $1\r26__data_o$next[3:0]$11582 + attribute \src "libresoc.v:182782.13-182782.31" wire width 4 $1\r26__data_o[3:0] - attribute \src "libresoc.v:183025.3-183064.6" - wire width 4 $1\r6__data_o$next[3:0]$11768 - attribute \src "libresoc.v:182582.13-182582.30" + attribute \src "libresoc.v:183087.3-183126.6" + wire width 4 $1\r6__data_o$next[3:0]$11568 + attribute \src "libresoc.v:182789.13-182789.30" wire width 4 $1\r6__data_o[3:0] - attribute \src "libresoc.v:182788.3-182814.6" - wire width 4 $1\reg$next[3:0]$11720 - attribute \src "libresoc.v:182588.13-182588.25" + attribute \src "libresoc.v:182920.3-182946.6" + wire width 4 $1\reg$next[3:0]$11534 + attribute \src "libresoc.v:182795.13-182795.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:182815.3-182854.6" - wire width 4 $1\src16__data_o$next[3:0]$11726 - attribute \src "libresoc.v:182593.13-182593.33" + attribute \src "libresoc.v:182850.3-182889.6" + wire width 4 $1\src16__data_o$next[3:0]$11525 + attribute \src "libresoc.v:182800.13-182800.33" wire width 4 $1\src16__data_o[3:0] - attribute \src "libresoc.v:182885.3-182924.6" - wire width 4 $1\src26__data_o$next[3:0]$11740 - attribute \src "libresoc.v:182600.13-182600.33" + attribute \src "libresoc.v:182947.3-182986.6" + wire width 4 $1\src26__data_o$next[3:0]$11540 + attribute \src "libresoc.v:182807.13-182807.33" wire width 4 $1\src26__data_o[3:0] - attribute \src "libresoc.v:182955.3-182994.6" - wire width 4 $1\src36__data_o$next[3:0]$11754 - attribute \src "libresoc.v:182607.13-182607.33" + attribute \src "libresoc.v:183017.3-183056.6" + wire width 4 $1\src36__data_o$next[3:0]$11554 + attribute \src "libresoc.v:182814.13-182814.33" wire width 4 $1\src36__data_o[3:0] - attribute \src "libresoc.v:182995.3-183024.6" - wire $1\wr_detect$10[0:0]$11762 - attribute \src "libresoc.v:183065.3-183094.6" - wire $1\wr_detect$13[0:0]$11776 - attribute \src "libresoc.v:182758.3-182787.6" - wire $1\wr_detect$16[0:0]$11714 - attribute \src "libresoc.v:182855.3-182884.6" - wire $1\wr_detect$4[0:0]$11734 - attribute \src "libresoc.v:182925.3-182954.6" - wire $1\wr_detect$7[0:0]$11748 - attribute \src "libresoc.v:182688.3-182717.6" + attribute \src "libresoc.v:183127.3-183156.6" + wire $1\wr_detect$10[0:0]$11576 + attribute \src "libresoc.v:183197.3-183226.6" + wire $1\wr_detect$13[0:0]$11590 + attribute \src "libresoc.v:182987.3-183016.6" + wire $1\wr_detect$4[0:0]$11548 + attribute \src "libresoc.v:183057.3-183086.6" + wire $1\wr_detect$7[0:0]$11562 + attribute \src "libresoc.v:182890.3-182919.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:182648.3-182687.6" - wire width 4 $2\cr_pred6__data_o$next[3:0]$11698 - attribute \src "libresoc.v:182718.3-182757.6" - wire width 4 $2\r26__data_o$next[3:0]$11707 - attribute \src "libresoc.v:183025.3-183064.6" - wire width 4 $2\r6__data_o$next[3:0]$11769 - attribute \src "libresoc.v:182788.3-182814.6" - wire width 4 $2\reg$next[3:0]$11721 - attribute \src "libresoc.v:182815.3-182854.6" - wire width 4 $2\src16__data_o$next[3:0]$11727 - attribute \src "libresoc.v:182885.3-182924.6" - wire width 4 $2\src26__data_o$next[3:0]$11741 - attribute \src "libresoc.v:182955.3-182994.6" - wire width 4 $2\src36__data_o$next[3:0]$11755 - attribute \src "libresoc.v:182995.3-183024.6" - wire $2\wr_detect$10[0:0]$11763 - attribute \src "libresoc.v:183065.3-183094.6" - wire $2\wr_detect$13[0:0]$11777 - attribute \src "libresoc.v:182758.3-182787.6" - wire $2\wr_detect$16[0:0]$11715 - attribute \src "libresoc.v:182855.3-182884.6" - wire $2\wr_detect$4[0:0]$11735 - attribute \src "libresoc.v:182925.3-182954.6" - wire $2\wr_detect$7[0:0]$11749 - attribute \src "libresoc.v:182688.3-182717.6" + attribute \src "libresoc.v:183157.3-183196.6" + wire width 4 $2\r26__data_o$next[3:0]$11583 + attribute \src "libresoc.v:183087.3-183126.6" + wire width 4 $2\r6__data_o$next[3:0]$11569 + attribute \src "libresoc.v:182920.3-182946.6" + wire width 4 $2\reg$next[3:0]$11535 + attribute \src "libresoc.v:182850.3-182889.6" + wire width 4 $2\src16__data_o$next[3:0]$11526 + attribute \src "libresoc.v:182947.3-182986.6" + wire width 4 $2\src26__data_o$next[3:0]$11541 + attribute \src "libresoc.v:183017.3-183056.6" + wire width 4 $2\src36__data_o$next[3:0]$11555 + attribute \src "libresoc.v:183127.3-183156.6" + wire $2\wr_detect$10[0:0]$11577 + attribute \src "libresoc.v:183197.3-183226.6" + wire $2\wr_detect$13[0:0]$11591 + attribute \src "libresoc.v:182987.3-183016.6" + wire $2\wr_detect$4[0:0]$11549 + attribute \src "libresoc.v:183057.3-183086.6" + wire $2\wr_detect$7[0:0]$11563 + attribute \src "libresoc.v:182890.3-182919.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:182648.3-182687.6" - wire width 4 $3\cr_pred6__data_o$next[3:0]$11699 - attribute \src "libresoc.v:182718.3-182757.6" - wire width 4 $3\r26__data_o$next[3:0]$11708 - attribute \src "libresoc.v:183025.3-183064.6" - wire width 4 $3\r6__data_o$next[3:0]$11770 - attribute \src "libresoc.v:182788.3-182814.6" - wire width 4 $3\reg$next[3:0]$11722 - attribute \src "libresoc.v:182815.3-182854.6" - wire width 4 $3\src16__data_o$next[3:0]$11728 - attribute \src "libresoc.v:182885.3-182924.6" - wire width 4 $3\src26__data_o$next[3:0]$11742 - attribute \src "libresoc.v:182955.3-182994.6" - wire width 4 $3\src36__data_o$next[3:0]$11756 - attribute \src "libresoc.v:182995.3-183024.6" - wire $3\wr_detect$10[0:0]$11764 - attribute \src "libresoc.v:183065.3-183094.6" - wire $3\wr_detect$13[0:0]$11778 - attribute \src "libresoc.v:182758.3-182787.6" - wire $3\wr_detect$16[0:0]$11716 - attribute \src "libresoc.v:182855.3-182884.6" - wire $3\wr_detect$4[0:0]$11736 - attribute \src "libresoc.v:182925.3-182954.6" - wire $3\wr_detect$7[0:0]$11750 - attribute \src "libresoc.v:182688.3-182717.6" + attribute \src "libresoc.v:183157.3-183196.6" + wire width 4 $3\r26__data_o$next[3:0]$11584 + attribute \src "libresoc.v:183087.3-183126.6" + wire width 4 $3\r6__data_o$next[3:0]$11570 + attribute \src "libresoc.v:182920.3-182946.6" + wire width 4 $3\reg$next[3:0]$11536 + attribute \src "libresoc.v:182850.3-182889.6" + wire width 4 $3\src16__data_o$next[3:0]$11527 + attribute \src "libresoc.v:182947.3-182986.6" + wire width 4 $3\src26__data_o$next[3:0]$11542 + attribute \src "libresoc.v:183017.3-183056.6" + wire width 4 $3\src36__data_o$next[3:0]$11556 + attribute \src "libresoc.v:183127.3-183156.6" + wire $3\wr_detect$10[0:0]$11578 + attribute \src "libresoc.v:183197.3-183226.6" + wire $3\wr_detect$13[0:0]$11592 + attribute \src "libresoc.v:182987.3-183016.6" + wire $3\wr_detect$4[0:0]$11550 + attribute \src "libresoc.v:183057.3-183086.6" + wire $3\wr_detect$7[0:0]$11564 + attribute \src "libresoc.v:182890.3-182919.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:182648.3-182687.6" - wire width 4 $4\cr_pred6__data_o$next[3:0]$11700 - attribute \src "libresoc.v:182718.3-182757.6" - wire width 4 $4\r26__data_o$next[3:0]$11709 - attribute \src "libresoc.v:183025.3-183064.6" - wire width 4 $4\r6__data_o$next[3:0]$11771 - attribute \src "libresoc.v:182788.3-182814.6" - wire width 4 $4\reg$next[3:0]$11723 - attribute \src "libresoc.v:182815.3-182854.6" - wire width 4 $4\src16__data_o$next[3:0]$11729 - attribute \src "libresoc.v:182885.3-182924.6" - wire width 4 $4\src26__data_o$next[3:0]$11743 - attribute \src "libresoc.v:182955.3-182994.6" - wire width 4 $4\src36__data_o$next[3:0]$11757 - attribute \src "libresoc.v:182995.3-183024.6" - wire $4\wr_detect$10[0:0]$11765 - attribute \src "libresoc.v:183065.3-183094.6" - wire $4\wr_detect$13[0:0]$11779 - attribute \src "libresoc.v:182758.3-182787.6" - wire $4\wr_detect$16[0:0]$11717 - attribute \src "libresoc.v:182855.3-182884.6" - wire $4\wr_detect$4[0:0]$11737 - attribute \src "libresoc.v:182925.3-182954.6" - wire $4\wr_detect$7[0:0]$11751 - attribute \src "libresoc.v:182688.3-182717.6" + attribute \src "libresoc.v:183157.3-183196.6" + wire width 4 $4\r26__data_o$next[3:0]$11585 + attribute \src "libresoc.v:183087.3-183126.6" + wire width 4 $4\r6__data_o$next[3:0]$11571 + attribute \src "libresoc.v:182920.3-182946.6" + wire width 4 $4\reg$next[3:0]$11537 + attribute \src "libresoc.v:182850.3-182889.6" + wire width 4 $4\src16__data_o$next[3:0]$11528 + attribute \src "libresoc.v:182947.3-182986.6" + wire width 4 $4\src26__data_o$next[3:0]$11543 + attribute \src "libresoc.v:183017.3-183056.6" + wire width 4 $4\src36__data_o$next[3:0]$11557 + attribute \src "libresoc.v:183127.3-183156.6" + wire $4\wr_detect$10[0:0]$11579 + attribute \src "libresoc.v:183197.3-183226.6" + wire $4\wr_detect$13[0:0]$11593 + attribute \src "libresoc.v:182987.3-183016.6" + wire $4\wr_detect$4[0:0]$11551 + attribute \src "libresoc.v:183057.3-183086.6" + wire $4\wr_detect$7[0:0]$11565 + attribute \src "libresoc.v:182890.3-182919.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:182648.3-182687.6" - wire width 4 $5\cr_pred6__data_o$next[3:0]$11701 - attribute \src "libresoc.v:182718.3-182757.6" - wire width 4 $5\r26__data_o$next[3:0]$11710 - attribute \src "libresoc.v:183025.3-183064.6" - wire width 4 $5\r6__data_o$next[3:0]$11772 - attribute \src "libresoc.v:182815.3-182854.6" - wire width 4 $5\src16__data_o$next[3:0]$11730 - attribute \src "libresoc.v:182885.3-182924.6" - wire width 4 $5\src26__data_o$next[3:0]$11744 - attribute \src "libresoc.v:182955.3-182994.6" - wire width 4 $5\src36__data_o$next[3:0]$11758 - attribute \src "libresoc.v:182648.3-182687.6" - wire width 4 $6\cr_pred6__data_o$next[3:0]$11702 - attribute \src "libresoc.v:182718.3-182757.6" - wire width 4 $6\r26__data_o$next[3:0]$11711 - attribute \src "libresoc.v:183025.3-183064.6" - wire width 4 $6\r6__data_o$next[3:0]$11773 - attribute \src "libresoc.v:182815.3-182854.6" - wire width 4 $6\src16__data_o$next[3:0]$11731 - attribute \src "libresoc.v:182885.3-182924.6" - wire width 4 $6\src26__data_o$next[3:0]$11745 - attribute \src "libresoc.v:182955.3-182994.6" - wire width 4 $6\src36__data_o$next[3:0]$11759 - attribute \src "libresoc.v:182628.17-182628.104" - wire $not$libresoc.v:182628$11682_Y - attribute \src "libresoc.v:182629.18-182629.105" - wire $not$libresoc.v:182629$11683_Y - attribute \src "libresoc.v:182630.18-182630.105" - wire $not$libresoc.v:182630$11684_Y - attribute \src "libresoc.v:182631.17-182631.100" - wire $not$libresoc.v:182631$11685_Y - attribute \src "libresoc.v:182632.17-182632.103" - wire $not$libresoc.v:182632$11686_Y - attribute \src "libresoc.v:182633.17-182633.103" - wire $not$libresoc.v:182633$11687_Y + attribute \src "libresoc.v:183157.3-183196.6" + wire width 4 $5\r26__data_o$next[3:0]$11586 + attribute \src "libresoc.v:183087.3-183126.6" + wire width 4 $5\r6__data_o$next[3:0]$11572 + attribute \src "libresoc.v:182850.3-182889.6" + wire width 4 $5\src16__data_o$next[3:0]$11529 + attribute \src "libresoc.v:182947.3-182986.6" + wire width 4 $5\src26__data_o$next[3:0]$11544 + attribute \src "libresoc.v:183017.3-183056.6" + wire width 4 $5\src36__data_o$next[3:0]$11558 + attribute \src "libresoc.v:183157.3-183196.6" + wire width 4 $6\r26__data_o$next[3:0]$11587 + attribute \src "libresoc.v:183087.3-183126.6" + wire width 4 $6\r6__data_o$next[3:0]$11573 + attribute \src "libresoc.v:182850.3-182889.6" + wire width 4 $6\src16__data_o$next[3:0]$11530 + attribute \src "libresoc.v:182947.3-182986.6" + wire width 4 $6\src26__data_o$next[3:0]$11545 + attribute \src "libresoc.v:183017.3-183056.6" + wire width 4 $6\src36__data_o$next[3:0]$11559 + attribute \src "libresoc.v:182833.17-182833.104" + wire $not$libresoc.v:182833$11512_Y + attribute \src "libresoc.v:182834.18-182834.105" + wire $not$libresoc.v:182834$11513_Y + attribute \src "libresoc.v:182835.17-182835.100" + wire $not$libresoc.v:182835$11514_Y + attribute \src "libresoc.v:182836.17-182836.103" + wire $not$libresoc.v:182836$11515_Y + attribute \src "libresoc.v:182837.17-182837.103" + wire $not$libresoc.v:182837$11516_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" - wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \cr_pred6__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \cr_pred6__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \cr_pred6__ren + wire width 4 input 9 \dest16__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest16__data_i + wire input 8 \dest16__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest16__wen + wire width 4 input 11 \dest26__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 13 \dest26__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 12 \dest26__wen - attribute \src "libresoc.v:182541.7-182541.15" + wire input 10 \dest26__wen + attribute \src "libresoc.v:182757.7-182757.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 16 \r26__data_o + wire width 4 output 14 \r26__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r26__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \r26__ren + wire input 15 \r26__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r6__data_o + wire width 4 output 12 \r6__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r6__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r6__ren + wire input 13 \r6__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src16__data_o + wire width 4 output 3 \src16__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src16__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src16__ren + wire input 2 \src16__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src26__data_o + wire width 4 output 5 \src26__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src26__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src26__ren + wire input 4 \src26__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 9 \src36__data_o + wire width 4 output 7 \src36__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src36__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \src36__ren + wire input 6 \src36__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 18 \w6__data_i + wire width 4 input 16 \w6__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 19 \w6__wen + wire input 17 \w6__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -375941,257 +341261,232 @@ module \reg_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182628$11682 + cell $not $not$libresoc.v:182833$11512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:182628$11682_Y + connect \Y $not$libresoc.v:182833$11512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182629$11683 + cell $not $not$libresoc.v:182834$11513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:182629$11683_Y + connect \Y $not$libresoc.v:182834$11513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182630$11684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$16 - connect \Y $not$libresoc.v:182630$11684_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182631$11685 + cell $not $not$libresoc.v:182835$11514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:182631$11685_Y + connect \Y $not$libresoc.v:182835$11514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182632$11686 + cell $not $not$libresoc.v:182836$11515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:182632$11686_Y + connect \Y $not$libresoc.v:182836$11515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182633$11687 + cell $not $not$libresoc.v:182837$11516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:182633$11687_Y + connect \Y $not$libresoc.v:182837$11516_Y end - attribute \src "libresoc.v:182541.7-182541.20" - process $proc$libresoc.v:182541$11780 + attribute \src "libresoc.v:182757.7-182757.20" + process $proc$libresoc.v:182757$11594 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182560.13-182560.36" - process $proc$libresoc.v:182560$11781 - assign { } { } - assign $1\cr_pred6__data_o[3:0] 4'0000 - sync always - sync init - update \cr_pred6__data_o $1\cr_pred6__data_o[3:0] - end - attribute \src "libresoc.v:182575.13-182575.31" - process $proc$libresoc.v:182575$11782 + attribute \src "libresoc.v:182782.13-182782.31" + process $proc$libresoc.v:182782$11595 assign { } { } assign $1\r26__data_o[3:0] 4'0000 sync always sync init update \r26__data_o $1\r26__data_o[3:0] end - attribute \src "libresoc.v:182582.13-182582.30" - process $proc$libresoc.v:182582$11783 + attribute \src "libresoc.v:182789.13-182789.30" + process $proc$libresoc.v:182789$11596 assign { } { } assign $1\r6__data_o[3:0] 4'0000 sync always sync init update \r6__data_o $1\r6__data_o[3:0] end - attribute \src "libresoc.v:182588.13-182588.25" - process $proc$libresoc.v:182588$11784 + attribute \src "libresoc.v:182795.13-182795.25" + process $proc$libresoc.v:182795$11597 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:182593.13-182593.33" - process $proc$libresoc.v:182593$11785 + attribute \src "libresoc.v:182800.13-182800.33" + process $proc$libresoc.v:182800$11598 assign { } { } assign $1\src16__data_o[3:0] 4'0000 sync always sync init update \src16__data_o $1\src16__data_o[3:0] end - attribute \src "libresoc.v:182600.13-182600.33" - process $proc$libresoc.v:182600$11786 + attribute \src "libresoc.v:182807.13-182807.33" + process $proc$libresoc.v:182807$11599 assign { } { } assign $1\src26__data_o[3:0] 4'0000 sync always sync init update \src26__data_o $1\src26__data_o[3:0] end - attribute \src "libresoc.v:182607.13-182607.33" - process $proc$libresoc.v:182607$11787 + attribute \src "libresoc.v:182814.13-182814.33" + process $proc$libresoc.v:182814$11600 assign { } { } assign $1\src36__data_o[3:0] 4'0000 sync always sync init update \src36__data_o $1\src36__data_o[3:0] end - attribute \src "libresoc.v:182634.3-182635.25" - process $proc$libresoc.v:182634$11688 + attribute \src "libresoc.v:182838.3-182839.25" + process $proc$libresoc.v:182838$11517 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:182636.3-182637.39" - process $proc$libresoc.v:182636$11689 + attribute \src "libresoc.v:182840.3-182841.39" + process $proc$libresoc.v:182840$11518 assign { } { } assign $0\r26__data_o[3:0] \r26__data_o$next sync posedge \coresync_clk update \r26__data_o $0\r26__data_o[3:0] end - attribute \src "libresoc.v:182638.3-182639.37" - process $proc$libresoc.v:182638$11690 + attribute \src "libresoc.v:182842.3-182843.37" + process $proc$libresoc.v:182842$11519 assign { } { } assign $0\r6__data_o[3:0] \r6__data_o$next sync posedge \coresync_clk update \r6__data_o $0\r6__data_o[3:0] end - attribute \src "libresoc.v:182640.3-182641.43" - process $proc$libresoc.v:182640$11691 + attribute \src "libresoc.v:182844.3-182845.43" + process $proc$libresoc.v:182844$11520 assign { } { } assign $0\src36__data_o[3:0] \src36__data_o$next sync posedge \coresync_clk update \src36__data_o $0\src36__data_o[3:0] end - attribute \src "libresoc.v:182642.3-182643.43" - process $proc$libresoc.v:182642$11692 + attribute \src "libresoc.v:182846.3-182847.43" + process $proc$libresoc.v:182846$11521 assign { } { } assign $0\src26__data_o[3:0] \src26__data_o$next sync posedge \coresync_clk update \src26__data_o $0\src26__data_o[3:0] end - attribute \src "libresoc.v:182644.3-182645.43" - process $proc$libresoc.v:182644$11693 + attribute \src "libresoc.v:182848.3-182849.43" + process $proc$libresoc.v:182848$11522 assign { } { } assign $0\src16__data_o[3:0] \src16__data_o$next sync posedge \coresync_clk update \src16__data_o $0\src16__data_o[3:0] end - attribute \src "libresoc.v:182646.3-182647.49" - process $proc$libresoc.v:182646$11694 - assign { } { } - assign $0\cr_pred6__data_o[3:0] \cr_pred6__data_o$next - sync posedge \coresync_clk - update \cr_pred6__data_o $0\cr_pred6__data_o[3:0] - end - attribute \src "libresoc.v:182648.3-182687.6" - process $proc$libresoc.v:182648$11695 + attribute \src "libresoc.v:182850.3-182889.6" + process $proc$libresoc.v:182850$11523 assign { } { } assign { } { } assign { } { } - assign $0\cr_pred6__data_o$next[3:0]$11696 $6\cr_pred6__data_o$next[3:0]$11702 - attribute \src "libresoc.v:182649.5-182649.29" + assign $0\src16__data_o$next[3:0]$11524 $6\src16__data_o$next[3:0]$11530 + attribute \src "libresoc.v:182851.5-182851.29" switch \initial - attribute \src "libresoc.v:182649.9-182649.17" + attribute \src "libresoc.v:182851.9-182851.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred6__ren + switch \src16__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\cr_pred6__data_o$next[3:0]$11697 $5\cr_pred6__data_o$next[3:0]$11701 + assign $1\src16__data_o$next[3:0]$11525 $5\src16__data_o$next[3:0]$11529 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred6__data_o$next[3:0]$11698 \dest16__data_i + assign $2\src16__data_o$next[3:0]$11526 \dest16__data_i case - assign $2\cr_pred6__data_o$next[3:0]$11698 4'0000 + assign $2\src16__data_o$next[3:0]$11526 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred6__data_o$next[3:0]$11699 \dest26__data_i + assign $3\src16__data_o$next[3:0]$11527 \dest26__data_i case - assign $3\cr_pred6__data_o$next[3:0]$11699 $2\cr_pred6__data_o$next[3:0]$11698 + assign $3\src16__data_o$next[3:0]$11527 $2\src16__data_o$next[3:0]$11526 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred6__data_o$next[3:0]$11700 \w6__data_i + assign $4\src16__data_o$next[3:0]$11528 \w6__data_i case - assign $4\cr_pred6__data_o$next[3:0]$11700 $3\cr_pred6__data_o$next[3:0]$11699 + assign $4\src16__data_o$next[3:0]$11528 $3\src16__data_o$next[3:0]$11527 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred6__data_o$next[3:0]$11701 \reg + assign $5\src16__data_o$next[3:0]$11529 \reg case - assign $5\cr_pred6__data_o$next[3:0]$11701 $4\cr_pred6__data_o$next[3:0]$11700 + assign $5\src16__data_o$next[3:0]$11529 $4\src16__data_o$next[3:0]$11528 end case - assign $1\cr_pred6__data_o$next[3:0]$11697 4'0000 + assign $1\src16__data_o$next[3:0]$11525 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred6__data_o$next[3:0]$11702 4'0000 + assign $6\src16__data_o$next[3:0]$11530 4'0000 case - assign $6\cr_pred6__data_o$next[3:0]$11702 $1\cr_pred6__data_o$next[3:0]$11697 + assign $6\src16__data_o$next[3:0]$11530 $1\src16__data_o$next[3:0]$11525 end sync always - update \cr_pred6__data_o$next $0\cr_pred6__data_o$next[3:0]$11696 + update \src16__data_o$next $0\src16__data_o$next[3:0]$11524 end - attribute \src "libresoc.v:182688.3-182717.6" - process $proc$libresoc.v:182688$11703 + attribute \src "libresoc.v:182890.3-182919.6" + process $proc$libresoc.v:182890$11531 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:182689.5-182689.29" + attribute \src "libresoc.v:182891.5-182891.29" switch \initial - attribute \src "libresoc.v:182689.9-182689.17" + attribute \src "libresoc.v:182891.9-182891.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred6__ren + switch \src16__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -376232,962 +341527,798 @@ module \reg_6 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:182718.3-182757.6" - process $proc$libresoc.v:182718$11704 + attribute \src "libresoc.v:182920.3-182946.6" + process $proc$libresoc.v:182920$11532 assign { } { } assign { } { } assign { } { } - assign $0\r26__data_o$next[3:0]$11705 $6\r26__data_o$next[3:0]$11711 - attribute \src "libresoc.v:182719.5-182719.29" + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11533 $4\reg$next[3:0]$11537 + attribute \src "libresoc.v:182921.5-182921.29" switch \initial - attribute \src "libresoc.v:182719.9-182719.17" + attribute \src "libresoc.v:182921.9-182921.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r26__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign $1\reg$next[3:0]$11534 \dest16__data_i + case + assign $1\reg$next[3:0]$11534 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } + assign $2\reg$next[3:0]$11535 \dest26__data_i + case + assign $2\reg$next[3:0]$11535 $1\reg$next[3:0]$11534 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign { } { } - assign $1\r26__data_o$next[3:0]$11706 $5\r26__data_o$next[3:0]$11710 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r26__data_o$next[3:0]$11707 \dest16__data_i - case - assign $2\r26__data_o$next[3:0]$11707 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r26__data_o$next[3:0]$11708 \dest26__data_i - case - assign $3\r26__data_o$next[3:0]$11708 $2\r26__data_o$next[3:0]$11707 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r26__data_o$next[3:0]$11709 \w6__data_i - case - assign $4\r26__data_o$next[3:0]$11709 $3\r26__data_o$next[3:0]$11708 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r26__data_o$next[3:0]$11710 \reg - case - assign $5\r26__data_o$next[3:0]$11710 $4\r26__data_o$next[3:0]$11709 - end + assign $3\reg$next[3:0]$11536 \w6__data_i case - assign $1\r26__data_o$next[3:0]$11706 4'0000 + assign $3\reg$next[3:0]$11536 $2\reg$next[3:0]$11535 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r26__data_o$next[3:0]$11711 4'0000 + assign $4\reg$next[3:0]$11537 4'0000 case - assign $6\r26__data_o$next[3:0]$11711 $1\r26__data_o$next[3:0]$11706 + assign $4\reg$next[3:0]$11537 $3\reg$next[3:0]$11536 end sync always - update \r26__data_o$next $0\r26__data_o$next[3:0]$11705 + update \reg$next $0\reg$next[3:0]$11533 end - attribute \src "libresoc.v:182758.3-182787.6" - process $proc$libresoc.v:182758$11712 + attribute \src "libresoc.v:182947.3-182986.6" + process $proc$libresoc.v:182947$11538 + assign { } { } assign { } { } assign { } { } - assign $0\wr_detect$16[0:0]$11713 $1\wr_detect$16[0:0]$11714 - attribute \src "libresoc.v:182759.5-182759.29" + assign $0\src26__data_o$next[3:0]$11539 $6\src26__data_o$next[3:0]$11545 + attribute \src "libresoc.v:182948.5-182948.29" switch \initial - attribute \src "libresoc.v:182759.9-182759.17" + attribute \src "libresoc.v:182948.9-182948.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r26__ren + switch \src26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$16[0:0]$11714 $4\wr_detect$16[0:0]$11717 + assign $1\src26__data_o$next[3:0]$11540 $5\src26__data_o$next[3:0]$11544 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$16[0:0]$11715 1'1 + assign $2\src26__data_o$next[3:0]$11541 \dest16__data_i case - assign $2\wr_detect$16[0:0]$11715 1'0 + assign $2\src26__data_o$next[3:0]$11541 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$16[0:0]$11716 1'1 + assign $3\src26__data_o$next[3:0]$11542 \dest26__data_i case - assign $3\wr_detect$16[0:0]$11716 $2\wr_detect$16[0:0]$11715 + assign $3\src26__data_o$next[3:0]$11542 $2\src26__data_o$next[3:0]$11541 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$16[0:0]$11717 1'1 + assign $4\src26__data_o$next[3:0]$11543 \w6__data_i case - assign $4\wr_detect$16[0:0]$11717 $3\wr_detect$16[0:0]$11716 - end - case - assign $1\wr_detect$16[0:0]$11714 1'0 - end - sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$11713 - end - attribute \src "libresoc.v:182788.3-182814.6" - process $proc$libresoc.v:182788$11718 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$11719 $4\reg$next[3:0]$11723 - attribute \src "libresoc.v:182789.5-182789.29" - switch \initial - attribute \src "libresoc.v:182789.9-182789.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest16__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[3:0]$11720 \dest16__data_i - case - assign $1\reg$next[3:0]$11720 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[3:0]$11721 \dest26__data_i - case - assign $2\reg$next[3:0]$11721 $1\reg$next[3:0]$11720 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[3:0]$11722 \w6__data_i - case - assign $3\reg$next[3:0]$11722 $2\reg$next[3:0]$11721 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[3:0]$11723 4'0000 - case - assign $4\reg$next[3:0]$11723 $3\reg$next[3:0]$11722 - end - sync always - update \reg$next $0\reg$next[3:0]$11719 - end - attribute \src "libresoc.v:182815.3-182854.6" - process $proc$libresoc.v:182815$11724 - assign { } { } - assign { } { } - assign { } { } - assign $0\src16__data_o$next[3:0]$11725 $6\src16__data_o$next[3:0]$11731 - attribute \src "libresoc.v:182816.5-182816.29" - switch \initial - attribute \src "libresoc.v:182816.9-182816.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src16__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src16__data_o$next[3:0]$11726 $5\src16__data_o$next[3:0]$11730 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src16__data_o$next[3:0]$11727 \dest16__data_i - case - assign $2\src16__data_o$next[3:0]$11727 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src16__data_o$next[3:0]$11728 \dest26__data_i - case - assign $3\src16__data_o$next[3:0]$11728 $2\src16__data_o$next[3:0]$11727 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src16__data_o$next[3:0]$11729 \w6__data_i - case - assign $4\src16__data_o$next[3:0]$11729 $3\src16__data_o$next[3:0]$11728 + assign $4\src26__data_o$next[3:0]$11543 $3\src26__data_o$next[3:0]$11542 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src16__data_o$next[3:0]$11730 \reg + assign $5\src26__data_o$next[3:0]$11544 \reg case - assign $5\src16__data_o$next[3:0]$11730 $4\src16__data_o$next[3:0]$11729 + assign $5\src26__data_o$next[3:0]$11544 $4\src26__data_o$next[3:0]$11543 end case - assign $1\src16__data_o$next[3:0]$11726 4'0000 + assign $1\src26__data_o$next[3:0]$11540 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src16__data_o$next[3:0]$11731 4'0000 + assign $6\src26__data_o$next[3:0]$11545 4'0000 case - assign $6\src16__data_o$next[3:0]$11731 $1\src16__data_o$next[3:0]$11726 + assign $6\src26__data_o$next[3:0]$11545 $1\src26__data_o$next[3:0]$11540 end sync always - update \src16__data_o$next $0\src16__data_o$next[3:0]$11725 + update \src26__data_o$next $0\src26__data_o$next[3:0]$11539 end - attribute \src "libresoc.v:182855.3-182884.6" - process $proc$libresoc.v:182855$11732 + attribute \src "libresoc.v:182987.3-183016.6" + process $proc$libresoc.v:182987$11546 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11733 $1\wr_detect$4[0:0]$11734 - attribute \src "libresoc.v:182856.5-182856.29" + assign $0\wr_detect$4[0:0]$11547 $1\wr_detect$4[0:0]$11548 + attribute \src "libresoc.v:182988.5-182988.29" switch \initial - attribute \src "libresoc.v:182856.9-182856.17" + attribute \src "libresoc.v:182988.9-182988.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src16__ren + switch \src26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11734 $4\wr_detect$4[0:0]$11737 + assign $1\wr_detect$4[0:0]$11548 $4\wr_detect$4[0:0]$11551 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11735 1'1 + assign $2\wr_detect$4[0:0]$11549 1'1 case - assign $2\wr_detect$4[0:0]$11735 1'0 + assign $2\wr_detect$4[0:0]$11549 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11736 1'1 + assign $3\wr_detect$4[0:0]$11550 1'1 case - assign $3\wr_detect$4[0:0]$11736 $2\wr_detect$4[0:0]$11735 + assign $3\wr_detect$4[0:0]$11550 $2\wr_detect$4[0:0]$11549 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11737 1'1 + assign $4\wr_detect$4[0:0]$11551 1'1 case - assign $4\wr_detect$4[0:0]$11737 $3\wr_detect$4[0:0]$11736 + assign $4\wr_detect$4[0:0]$11551 $3\wr_detect$4[0:0]$11550 end case - assign $1\wr_detect$4[0:0]$11734 1'0 + assign $1\wr_detect$4[0:0]$11548 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11733 + update \wr_detect$4 $0\wr_detect$4[0:0]$11547 end - attribute \src "libresoc.v:182885.3-182924.6" - process $proc$libresoc.v:182885$11738 + attribute \src "libresoc.v:183017.3-183056.6" + process $proc$libresoc.v:183017$11552 assign { } { } assign { } { } assign { } { } - assign $0\src26__data_o$next[3:0]$11739 $6\src26__data_o$next[3:0]$11745 - attribute \src "libresoc.v:182886.5-182886.29" + assign $0\src36__data_o$next[3:0]$11553 $6\src36__data_o$next[3:0]$11559 + attribute \src "libresoc.v:183018.5-183018.29" switch \initial - attribute \src "libresoc.v:182886.9-182886.17" + attribute \src "libresoc.v:183018.9-183018.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src26__ren + switch \src36__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src26__data_o$next[3:0]$11740 $5\src26__data_o$next[3:0]$11744 + assign $1\src36__data_o$next[3:0]$11554 $5\src36__data_o$next[3:0]$11558 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src26__data_o$next[3:0]$11741 \dest16__data_i + assign $2\src36__data_o$next[3:0]$11555 \dest16__data_i case - assign $2\src26__data_o$next[3:0]$11741 4'0000 + assign $2\src36__data_o$next[3:0]$11555 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src26__data_o$next[3:0]$11742 \dest26__data_i + assign $3\src36__data_o$next[3:0]$11556 \dest26__data_i case - assign $3\src26__data_o$next[3:0]$11742 $2\src26__data_o$next[3:0]$11741 + assign $3\src36__data_o$next[3:0]$11556 $2\src36__data_o$next[3:0]$11555 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src26__data_o$next[3:0]$11743 \w6__data_i + assign $4\src36__data_o$next[3:0]$11557 \w6__data_i case - assign $4\src26__data_o$next[3:0]$11743 $3\src26__data_o$next[3:0]$11742 + assign $4\src36__data_o$next[3:0]$11557 $3\src36__data_o$next[3:0]$11556 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src26__data_o$next[3:0]$11744 \reg + assign $5\src36__data_o$next[3:0]$11558 \reg case - assign $5\src26__data_o$next[3:0]$11744 $4\src26__data_o$next[3:0]$11743 + assign $5\src36__data_o$next[3:0]$11558 $4\src36__data_o$next[3:0]$11557 end case - assign $1\src26__data_o$next[3:0]$11740 4'0000 + assign $1\src36__data_o$next[3:0]$11554 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src26__data_o$next[3:0]$11745 4'0000 + assign $6\src36__data_o$next[3:0]$11559 4'0000 case - assign $6\src26__data_o$next[3:0]$11745 $1\src26__data_o$next[3:0]$11740 + assign $6\src36__data_o$next[3:0]$11559 $1\src36__data_o$next[3:0]$11554 end sync always - update \src26__data_o$next $0\src26__data_o$next[3:0]$11739 + update \src36__data_o$next $0\src36__data_o$next[3:0]$11553 end - attribute \src "libresoc.v:182925.3-182954.6" - process $proc$libresoc.v:182925$11746 + attribute \src "libresoc.v:183057.3-183086.6" + process $proc$libresoc.v:183057$11560 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11747 $1\wr_detect$7[0:0]$11748 - attribute \src "libresoc.v:182926.5-182926.29" + assign $0\wr_detect$7[0:0]$11561 $1\wr_detect$7[0:0]$11562 + attribute \src "libresoc.v:183058.5-183058.29" switch \initial - attribute \src "libresoc.v:182926.9-182926.17" + attribute \src "libresoc.v:183058.9-183058.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src26__ren + switch \src36__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11748 $4\wr_detect$7[0:0]$11751 + assign $1\wr_detect$7[0:0]$11562 $4\wr_detect$7[0:0]$11565 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11749 1'1 + assign $2\wr_detect$7[0:0]$11563 1'1 case - assign $2\wr_detect$7[0:0]$11749 1'0 + assign $2\wr_detect$7[0:0]$11563 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11750 1'1 + assign $3\wr_detect$7[0:0]$11564 1'1 case - assign $3\wr_detect$7[0:0]$11750 $2\wr_detect$7[0:0]$11749 + assign $3\wr_detect$7[0:0]$11564 $2\wr_detect$7[0:0]$11563 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11751 1'1 + assign $4\wr_detect$7[0:0]$11565 1'1 case - assign $4\wr_detect$7[0:0]$11751 $3\wr_detect$7[0:0]$11750 + assign $4\wr_detect$7[0:0]$11565 $3\wr_detect$7[0:0]$11564 end case - assign $1\wr_detect$7[0:0]$11748 1'0 + assign $1\wr_detect$7[0:0]$11562 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11747 + update \wr_detect$7 $0\wr_detect$7[0:0]$11561 end - attribute \src "libresoc.v:182955.3-182994.6" - process $proc$libresoc.v:182955$11752 + attribute \src "libresoc.v:183087.3-183126.6" + process $proc$libresoc.v:183087$11566 assign { } { } assign { } { } assign { } { } - assign $0\src36__data_o$next[3:0]$11753 $6\src36__data_o$next[3:0]$11759 - attribute \src "libresoc.v:182956.5-182956.29" + assign $0\r6__data_o$next[3:0]$11567 $6\r6__data_o$next[3:0]$11573 + attribute \src "libresoc.v:183088.5-183088.29" switch \initial - attribute \src "libresoc.v:182956.9-182956.17" + attribute \src "libresoc.v:183088.9-183088.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src36__ren + switch \r6__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src36__data_o$next[3:0]$11754 $5\src36__data_o$next[3:0]$11758 + assign $1\r6__data_o$next[3:0]$11568 $5\r6__data_o$next[3:0]$11572 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src36__data_o$next[3:0]$11755 \dest16__data_i + assign $2\r6__data_o$next[3:0]$11569 \dest16__data_i case - assign $2\src36__data_o$next[3:0]$11755 4'0000 + assign $2\r6__data_o$next[3:0]$11569 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src36__data_o$next[3:0]$11756 \dest26__data_i + assign $3\r6__data_o$next[3:0]$11570 \dest26__data_i case - assign $3\src36__data_o$next[3:0]$11756 $2\src36__data_o$next[3:0]$11755 + assign $3\r6__data_o$next[3:0]$11570 $2\r6__data_o$next[3:0]$11569 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src36__data_o$next[3:0]$11757 \w6__data_i + assign $4\r6__data_o$next[3:0]$11571 \w6__data_i case - assign $4\src36__data_o$next[3:0]$11757 $3\src36__data_o$next[3:0]$11756 + assign $4\r6__data_o$next[3:0]$11571 $3\r6__data_o$next[3:0]$11570 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src36__data_o$next[3:0]$11758 \reg + assign $5\r6__data_o$next[3:0]$11572 \reg case - assign $5\src36__data_o$next[3:0]$11758 $4\src36__data_o$next[3:0]$11757 + assign $5\r6__data_o$next[3:0]$11572 $4\r6__data_o$next[3:0]$11571 end case - assign $1\src36__data_o$next[3:0]$11754 4'0000 + assign $1\r6__data_o$next[3:0]$11568 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src36__data_o$next[3:0]$11759 4'0000 + assign $6\r6__data_o$next[3:0]$11573 4'0000 case - assign $6\src36__data_o$next[3:0]$11759 $1\src36__data_o$next[3:0]$11754 + assign $6\r6__data_o$next[3:0]$11573 $1\r6__data_o$next[3:0]$11568 end sync always - update \src36__data_o$next $0\src36__data_o$next[3:0]$11753 + update \r6__data_o$next $0\r6__data_o$next[3:0]$11567 end - attribute \src "libresoc.v:182995.3-183024.6" - process $proc$libresoc.v:182995$11760 + attribute \src "libresoc.v:183127.3-183156.6" + process $proc$libresoc.v:183127$11574 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11761 $1\wr_detect$10[0:0]$11762 - attribute \src "libresoc.v:182996.5-182996.29" + assign $0\wr_detect$10[0:0]$11575 $1\wr_detect$10[0:0]$11576 + attribute \src "libresoc.v:183128.5-183128.29" switch \initial - attribute \src "libresoc.v:182996.9-182996.17" + attribute \src "libresoc.v:183128.9-183128.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src36__ren + switch \r6__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11762 $4\wr_detect$10[0:0]$11765 + assign $1\wr_detect$10[0:0]$11576 $4\wr_detect$10[0:0]$11579 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11763 1'1 + assign $2\wr_detect$10[0:0]$11577 1'1 case - assign $2\wr_detect$10[0:0]$11763 1'0 + assign $2\wr_detect$10[0:0]$11577 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11764 1'1 + assign $3\wr_detect$10[0:0]$11578 1'1 case - assign $3\wr_detect$10[0:0]$11764 $2\wr_detect$10[0:0]$11763 + assign $3\wr_detect$10[0:0]$11578 $2\wr_detect$10[0:0]$11577 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11765 1'1 + assign $4\wr_detect$10[0:0]$11579 1'1 case - assign $4\wr_detect$10[0:0]$11765 $3\wr_detect$10[0:0]$11764 + assign $4\wr_detect$10[0:0]$11579 $3\wr_detect$10[0:0]$11578 end case - assign $1\wr_detect$10[0:0]$11762 1'0 + assign $1\wr_detect$10[0:0]$11576 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11761 + update \wr_detect$10 $0\wr_detect$10[0:0]$11575 end - attribute \src "libresoc.v:183025.3-183064.6" - process $proc$libresoc.v:183025$11766 + attribute \src "libresoc.v:183157.3-183196.6" + process $proc$libresoc.v:183157$11580 assign { } { } assign { } { } assign { } { } - assign $0\r6__data_o$next[3:0]$11767 $6\r6__data_o$next[3:0]$11773 - attribute \src "libresoc.v:183026.5-183026.29" + assign $0\r26__data_o$next[3:0]$11581 $6\r26__data_o$next[3:0]$11587 + attribute \src "libresoc.v:183158.5-183158.29" switch \initial - attribute \src "libresoc.v:183026.9-183026.17" + attribute \src "libresoc.v:183158.9-183158.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r6__ren + switch \r26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r6__data_o$next[3:0]$11768 $5\r6__data_o$next[3:0]$11772 + assign $1\r26__data_o$next[3:0]$11582 $5\r26__data_o$next[3:0]$11586 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r6__data_o$next[3:0]$11769 \dest16__data_i + assign $2\r26__data_o$next[3:0]$11583 \dest16__data_i case - assign $2\r6__data_o$next[3:0]$11769 4'0000 + assign $2\r26__data_o$next[3:0]$11583 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r6__data_o$next[3:0]$11770 \dest26__data_i + assign $3\r26__data_o$next[3:0]$11584 \dest26__data_i case - assign $3\r6__data_o$next[3:0]$11770 $2\r6__data_o$next[3:0]$11769 + assign $3\r26__data_o$next[3:0]$11584 $2\r26__data_o$next[3:0]$11583 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r6__data_o$next[3:0]$11771 \w6__data_i + assign $4\r26__data_o$next[3:0]$11585 \w6__data_i case - assign $4\r6__data_o$next[3:0]$11771 $3\r6__data_o$next[3:0]$11770 + assign $4\r26__data_o$next[3:0]$11585 $3\r26__data_o$next[3:0]$11584 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r6__data_o$next[3:0]$11772 \reg + assign $5\r26__data_o$next[3:0]$11586 \reg case - assign $5\r6__data_o$next[3:0]$11772 $4\r6__data_o$next[3:0]$11771 + assign $5\r26__data_o$next[3:0]$11586 $4\r26__data_o$next[3:0]$11585 end case - assign $1\r6__data_o$next[3:0]$11768 4'0000 + assign $1\r26__data_o$next[3:0]$11582 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r6__data_o$next[3:0]$11773 4'0000 + assign $6\r26__data_o$next[3:0]$11587 4'0000 case - assign $6\r6__data_o$next[3:0]$11773 $1\r6__data_o$next[3:0]$11768 + assign $6\r26__data_o$next[3:0]$11587 $1\r26__data_o$next[3:0]$11582 end sync always - update \r6__data_o$next $0\r6__data_o$next[3:0]$11767 + update \r26__data_o$next $0\r26__data_o$next[3:0]$11581 end - attribute \src "libresoc.v:183065.3-183094.6" - process $proc$libresoc.v:183065$11774 + attribute \src "libresoc.v:183197.3-183226.6" + process $proc$libresoc.v:183197$11588 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11775 $1\wr_detect$13[0:0]$11776 - attribute \src "libresoc.v:183066.5-183066.29" + assign $0\wr_detect$13[0:0]$11589 $1\wr_detect$13[0:0]$11590 + attribute \src "libresoc.v:183198.5-183198.29" switch \initial - attribute \src "libresoc.v:183066.9-183066.17" + attribute \src "libresoc.v:183198.9-183198.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r6__ren + switch \r26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11776 $4\wr_detect$13[0:0]$11779 + assign $1\wr_detect$13[0:0]$11590 $4\wr_detect$13[0:0]$11593 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11777 1'1 + assign $2\wr_detect$13[0:0]$11591 1'1 case - assign $2\wr_detect$13[0:0]$11777 1'0 + assign $2\wr_detect$13[0:0]$11591 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11778 1'1 + assign $3\wr_detect$13[0:0]$11592 1'1 case - assign $3\wr_detect$13[0:0]$11778 $2\wr_detect$13[0:0]$11777 + assign $3\wr_detect$13[0:0]$11592 $2\wr_detect$13[0:0]$11591 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11779 1'1 + assign $4\wr_detect$13[0:0]$11593 1'1 case - assign $4\wr_detect$13[0:0]$11779 $3\wr_detect$13[0:0]$11778 + assign $4\wr_detect$13[0:0]$11593 $3\wr_detect$13[0:0]$11592 end case - assign $1\wr_detect$13[0:0]$11776 1'0 + assign $1\wr_detect$13[0:0]$11590 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11775 + update \wr_detect$13 $0\wr_detect$13[0:0]$11589 end - connect \$9 $not$libresoc.v:182628$11682_Y - connect \$12 $not$libresoc.v:182629$11683_Y - connect \$15 $not$libresoc.v:182630$11684_Y - connect \$1 $not$libresoc.v:182631$11685_Y - connect \$3 $not$libresoc.v:182632$11686_Y - connect \$6 $not$libresoc.v:182633$11687_Y + connect \$9 $not$libresoc.v:182833$11512_Y + connect \$12 $not$libresoc.v:182834$11513_Y + connect \$1 $not$libresoc.v:182835$11514_Y + connect \$3 $not$libresoc.v:182836$11515_Y + connect \$6 $not$libresoc.v:182837$11516_Y end -attribute \src "libresoc.v:183099.1-183654.10" +attribute \src "libresoc.v:183231.1-183702.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" attribute \generator "nMigen" module \reg_7 - attribute \src "libresoc.v:183207.3-183246.6" - wire width 4 $0\cr_pred7__data_o$next[3:0]$11802 - attribute \src "libresoc.v:183205.3-183206.49" - wire width 4 $0\cr_pred7__data_o[3:0] - attribute \src "libresoc.v:183100.7-183100.20" + attribute \src "libresoc.v:183232.7-183232.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183277.3-183316.6" - wire width 4 $0\r27__data_o$next[3:0]$11811 - attribute \src "libresoc.v:183195.3-183196.39" + attribute \src "libresoc.v:183632.3-183671.6" + wire width 4 $0\r27__data_o$next[3:0]$11670 + attribute \src "libresoc.v:183315.3-183316.39" wire width 4 $0\r27__data_o[3:0] - attribute \src "libresoc.v:183584.3-183623.6" - wire width 4 $0\r7__data_o$next[3:0]$11873 - attribute \src "libresoc.v:183197.3-183198.37" + attribute \src "libresoc.v:183562.3-183601.6" + wire width 4 $0\r7__data_o$next[3:0]$11656 + attribute \src "libresoc.v:183317.3-183318.37" wire width 4 $0\r7__data_o[3:0] - attribute \src "libresoc.v:183347.3-183373.6" - wire width 4 $0\reg$next[3:0]$11825 - attribute \src "libresoc.v:183193.3-183194.25" + attribute \src "libresoc.v:183395.3-183421.6" + wire width 4 $0\reg$next[3:0]$11622 + attribute \src "libresoc.v:183313.3-183314.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:183374.3-183413.6" - wire width 4 $0\src17__data_o$next[3:0]$11831 - attribute \src "libresoc.v:183203.3-183204.43" + attribute \src "libresoc.v:183325.3-183364.6" + wire width 4 $0\src17__data_o$next[3:0]$11613 + attribute \src "libresoc.v:183323.3-183324.43" wire width 4 $0\src17__data_o[3:0] - attribute \src "libresoc.v:183444.3-183483.6" - wire width 4 $0\src27__data_o$next[3:0]$11845 - attribute \src "libresoc.v:183201.3-183202.43" + attribute \src "libresoc.v:183422.3-183461.6" + wire width 4 $0\src27__data_o$next[3:0]$11628 + attribute \src "libresoc.v:183321.3-183322.43" wire width 4 $0\src27__data_o[3:0] - attribute \src "libresoc.v:183514.3-183553.6" - wire width 4 $0\src37__data_o$next[3:0]$11859 - attribute \src "libresoc.v:183199.3-183200.43" + attribute \src "libresoc.v:183492.3-183531.6" + wire width 4 $0\src37__data_o$next[3:0]$11642 + attribute \src "libresoc.v:183319.3-183320.43" wire width 4 $0\src37__data_o[3:0] - attribute \src "libresoc.v:183554.3-183583.6" - wire $0\wr_detect$10[0:0]$11867 - attribute \src "libresoc.v:183624.3-183653.6" - wire $0\wr_detect$13[0:0]$11881 - attribute \src "libresoc.v:183317.3-183346.6" - wire $0\wr_detect$16[0:0]$11819 - attribute \src "libresoc.v:183414.3-183443.6" - wire $0\wr_detect$4[0:0]$11839 - attribute \src "libresoc.v:183484.3-183513.6" - wire $0\wr_detect$7[0:0]$11853 - attribute \src "libresoc.v:183247.3-183276.6" + attribute \src "libresoc.v:183602.3-183631.6" + wire $0\wr_detect$10[0:0]$11664 + attribute \src "libresoc.v:183672.3-183701.6" + wire $0\wr_detect$13[0:0]$11678 + attribute \src "libresoc.v:183462.3-183491.6" + wire $0\wr_detect$4[0:0]$11636 + attribute \src "libresoc.v:183532.3-183561.6" + wire $0\wr_detect$7[0:0]$11650 + attribute \src "libresoc.v:183365.3-183394.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:183207.3-183246.6" - wire width 4 $1\cr_pred7__data_o$next[3:0]$11803 - attribute \src "libresoc.v:183119.13-183119.36" - wire width 4 $1\cr_pred7__data_o[3:0] - attribute \src "libresoc.v:183277.3-183316.6" - wire width 4 $1\r27__data_o$next[3:0]$11812 - attribute \src "libresoc.v:183134.13-183134.31" + attribute \src "libresoc.v:183632.3-183671.6" + wire width 4 $1\r27__data_o$next[3:0]$11671 + attribute \src "libresoc.v:183257.13-183257.31" wire width 4 $1\r27__data_o[3:0] - attribute \src "libresoc.v:183584.3-183623.6" - wire width 4 $1\r7__data_o$next[3:0]$11874 - attribute \src "libresoc.v:183141.13-183141.30" + attribute \src "libresoc.v:183562.3-183601.6" + wire width 4 $1\r7__data_o$next[3:0]$11657 + attribute \src "libresoc.v:183264.13-183264.30" wire width 4 $1\r7__data_o[3:0] - attribute \src "libresoc.v:183347.3-183373.6" - wire width 4 $1\reg$next[3:0]$11826 - attribute \src "libresoc.v:183147.13-183147.25" + attribute \src "libresoc.v:183395.3-183421.6" + wire width 4 $1\reg$next[3:0]$11623 + attribute \src "libresoc.v:183270.13-183270.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:183374.3-183413.6" - wire width 4 $1\src17__data_o$next[3:0]$11832 - attribute \src "libresoc.v:183152.13-183152.33" + attribute \src "libresoc.v:183325.3-183364.6" + wire width 4 $1\src17__data_o$next[3:0]$11614 + attribute \src "libresoc.v:183275.13-183275.33" wire width 4 $1\src17__data_o[3:0] - attribute \src "libresoc.v:183444.3-183483.6" - wire width 4 $1\src27__data_o$next[3:0]$11846 - attribute \src "libresoc.v:183159.13-183159.33" + attribute \src "libresoc.v:183422.3-183461.6" + wire width 4 $1\src27__data_o$next[3:0]$11629 + attribute \src "libresoc.v:183282.13-183282.33" wire width 4 $1\src27__data_o[3:0] - attribute \src "libresoc.v:183514.3-183553.6" - wire width 4 $1\src37__data_o$next[3:0]$11860 - attribute \src "libresoc.v:183166.13-183166.33" + attribute \src "libresoc.v:183492.3-183531.6" + wire width 4 $1\src37__data_o$next[3:0]$11643 + attribute \src "libresoc.v:183289.13-183289.33" wire width 4 $1\src37__data_o[3:0] - attribute \src "libresoc.v:183554.3-183583.6" - wire $1\wr_detect$10[0:0]$11868 - attribute \src "libresoc.v:183624.3-183653.6" - wire $1\wr_detect$13[0:0]$11882 - attribute \src "libresoc.v:183317.3-183346.6" - wire $1\wr_detect$16[0:0]$11820 - attribute \src "libresoc.v:183414.3-183443.6" - wire $1\wr_detect$4[0:0]$11840 - attribute \src "libresoc.v:183484.3-183513.6" - wire $1\wr_detect$7[0:0]$11854 - attribute \src "libresoc.v:183247.3-183276.6" + attribute \src "libresoc.v:183602.3-183631.6" + wire $1\wr_detect$10[0:0]$11665 + attribute \src "libresoc.v:183672.3-183701.6" + wire $1\wr_detect$13[0:0]$11679 + attribute \src "libresoc.v:183462.3-183491.6" + wire $1\wr_detect$4[0:0]$11637 + attribute \src "libresoc.v:183532.3-183561.6" + wire $1\wr_detect$7[0:0]$11651 + attribute \src "libresoc.v:183365.3-183394.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:183207.3-183246.6" - wire width 4 $2\cr_pred7__data_o$next[3:0]$11804 - attribute \src "libresoc.v:183277.3-183316.6" - wire width 4 $2\r27__data_o$next[3:0]$11813 - attribute \src "libresoc.v:183584.3-183623.6" - wire width 4 $2\r7__data_o$next[3:0]$11875 - attribute \src "libresoc.v:183347.3-183373.6" - wire width 4 $2\reg$next[3:0]$11827 - attribute \src "libresoc.v:183374.3-183413.6" - wire width 4 $2\src17__data_o$next[3:0]$11833 - attribute \src "libresoc.v:183444.3-183483.6" - wire width 4 $2\src27__data_o$next[3:0]$11847 - attribute \src "libresoc.v:183514.3-183553.6" - wire width 4 $2\src37__data_o$next[3:0]$11861 - attribute \src "libresoc.v:183554.3-183583.6" - wire $2\wr_detect$10[0:0]$11869 - attribute \src "libresoc.v:183624.3-183653.6" - wire $2\wr_detect$13[0:0]$11883 - attribute \src "libresoc.v:183317.3-183346.6" - wire $2\wr_detect$16[0:0]$11821 - attribute \src "libresoc.v:183414.3-183443.6" - wire $2\wr_detect$4[0:0]$11841 - attribute \src "libresoc.v:183484.3-183513.6" - wire $2\wr_detect$7[0:0]$11855 - attribute \src "libresoc.v:183247.3-183276.6" + attribute \src "libresoc.v:183632.3-183671.6" + wire width 4 $2\r27__data_o$next[3:0]$11672 + attribute \src "libresoc.v:183562.3-183601.6" + wire width 4 $2\r7__data_o$next[3:0]$11658 + attribute \src "libresoc.v:183395.3-183421.6" + wire width 4 $2\reg$next[3:0]$11624 + attribute \src "libresoc.v:183325.3-183364.6" + wire width 4 $2\src17__data_o$next[3:0]$11615 + attribute \src "libresoc.v:183422.3-183461.6" + wire width 4 $2\src27__data_o$next[3:0]$11630 + attribute \src "libresoc.v:183492.3-183531.6" + wire width 4 $2\src37__data_o$next[3:0]$11644 + attribute \src "libresoc.v:183602.3-183631.6" + wire $2\wr_detect$10[0:0]$11666 + attribute \src "libresoc.v:183672.3-183701.6" + wire $2\wr_detect$13[0:0]$11680 + attribute \src "libresoc.v:183462.3-183491.6" + wire $2\wr_detect$4[0:0]$11638 + attribute \src "libresoc.v:183532.3-183561.6" + wire $2\wr_detect$7[0:0]$11652 + attribute \src "libresoc.v:183365.3-183394.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:183207.3-183246.6" - wire width 4 $3\cr_pred7__data_o$next[3:0]$11805 - attribute \src "libresoc.v:183277.3-183316.6" - wire width 4 $3\r27__data_o$next[3:0]$11814 - attribute \src "libresoc.v:183584.3-183623.6" - wire width 4 $3\r7__data_o$next[3:0]$11876 - attribute \src "libresoc.v:183347.3-183373.6" - wire width 4 $3\reg$next[3:0]$11828 - attribute \src "libresoc.v:183374.3-183413.6" - wire width 4 $3\src17__data_o$next[3:0]$11834 - attribute \src "libresoc.v:183444.3-183483.6" - wire width 4 $3\src27__data_o$next[3:0]$11848 - attribute \src "libresoc.v:183514.3-183553.6" - wire width 4 $3\src37__data_o$next[3:0]$11862 - attribute \src "libresoc.v:183554.3-183583.6" - wire $3\wr_detect$10[0:0]$11870 - attribute \src "libresoc.v:183624.3-183653.6" - wire $3\wr_detect$13[0:0]$11884 - attribute \src "libresoc.v:183317.3-183346.6" - wire $3\wr_detect$16[0:0]$11822 - attribute \src "libresoc.v:183414.3-183443.6" - wire $3\wr_detect$4[0:0]$11842 - attribute \src "libresoc.v:183484.3-183513.6" - wire $3\wr_detect$7[0:0]$11856 - attribute \src "libresoc.v:183247.3-183276.6" + attribute \src "libresoc.v:183632.3-183671.6" + wire width 4 $3\r27__data_o$next[3:0]$11673 + attribute \src "libresoc.v:183562.3-183601.6" + wire width 4 $3\r7__data_o$next[3:0]$11659 + attribute \src "libresoc.v:183395.3-183421.6" + wire width 4 $3\reg$next[3:0]$11625 + attribute \src "libresoc.v:183325.3-183364.6" + wire width 4 $3\src17__data_o$next[3:0]$11616 + attribute \src "libresoc.v:183422.3-183461.6" + wire width 4 $3\src27__data_o$next[3:0]$11631 + attribute \src "libresoc.v:183492.3-183531.6" + wire width 4 $3\src37__data_o$next[3:0]$11645 + attribute \src "libresoc.v:183602.3-183631.6" + wire $3\wr_detect$10[0:0]$11667 + attribute \src "libresoc.v:183672.3-183701.6" + wire $3\wr_detect$13[0:0]$11681 + attribute \src "libresoc.v:183462.3-183491.6" + wire $3\wr_detect$4[0:0]$11639 + attribute \src "libresoc.v:183532.3-183561.6" + wire $3\wr_detect$7[0:0]$11653 + attribute \src "libresoc.v:183365.3-183394.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:183207.3-183246.6" - wire width 4 $4\cr_pred7__data_o$next[3:0]$11806 - attribute \src "libresoc.v:183277.3-183316.6" - wire width 4 $4\r27__data_o$next[3:0]$11815 - attribute \src "libresoc.v:183584.3-183623.6" - wire width 4 $4\r7__data_o$next[3:0]$11877 - attribute \src "libresoc.v:183347.3-183373.6" - wire width 4 $4\reg$next[3:0]$11829 - attribute \src "libresoc.v:183374.3-183413.6" - wire width 4 $4\src17__data_o$next[3:0]$11835 - attribute \src "libresoc.v:183444.3-183483.6" - wire width 4 $4\src27__data_o$next[3:0]$11849 - attribute \src "libresoc.v:183514.3-183553.6" - wire width 4 $4\src37__data_o$next[3:0]$11863 - attribute \src "libresoc.v:183554.3-183583.6" - wire $4\wr_detect$10[0:0]$11871 - attribute \src "libresoc.v:183624.3-183653.6" - wire $4\wr_detect$13[0:0]$11885 - attribute \src "libresoc.v:183317.3-183346.6" - wire $4\wr_detect$16[0:0]$11823 - attribute \src "libresoc.v:183414.3-183443.6" - wire $4\wr_detect$4[0:0]$11843 - attribute \src "libresoc.v:183484.3-183513.6" - wire $4\wr_detect$7[0:0]$11857 - attribute \src "libresoc.v:183247.3-183276.6" + attribute \src "libresoc.v:183632.3-183671.6" + wire width 4 $4\r27__data_o$next[3:0]$11674 + attribute \src "libresoc.v:183562.3-183601.6" + wire width 4 $4\r7__data_o$next[3:0]$11660 + attribute \src "libresoc.v:183395.3-183421.6" + wire width 4 $4\reg$next[3:0]$11626 + attribute \src "libresoc.v:183325.3-183364.6" + wire width 4 $4\src17__data_o$next[3:0]$11617 + attribute \src "libresoc.v:183422.3-183461.6" + wire width 4 $4\src27__data_o$next[3:0]$11632 + attribute \src "libresoc.v:183492.3-183531.6" + wire width 4 $4\src37__data_o$next[3:0]$11646 + attribute \src "libresoc.v:183602.3-183631.6" + wire $4\wr_detect$10[0:0]$11668 + attribute \src "libresoc.v:183672.3-183701.6" + wire $4\wr_detect$13[0:0]$11682 + attribute \src "libresoc.v:183462.3-183491.6" + wire $4\wr_detect$4[0:0]$11640 + attribute \src "libresoc.v:183532.3-183561.6" + wire $4\wr_detect$7[0:0]$11654 + attribute \src "libresoc.v:183365.3-183394.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:183207.3-183246.6" - wire width 4 $5\cr_pred7__data_o$next[3:0]$11807 - attribute \src "libresoc.v:183277.3-183316.6" - wire width 4 $5\r27__data_o$next[3:0]$11816 - attribute \src "libresoc.v:183584.3-183623.6" - wire width 4 $5\r7__data_o$next[3:0]$11878 - attribute \src "libresoc.v:183374.3-183413.6" - wire width 4 $5\src17__data_o$next[3:0]$11836 - attribute \src "libresoc.v:183444.3-183483.6" - wire width 4 $5\src27__data_o$next[3:0]$11850 - attribute \src "libresoc.v:183514.3-183553.6" - wire width 4 $5\src37__data_o$next[3:0]$11864 - attribute \src "libresoc.v:183207.3-183246.6" - wire width 4 $6\cr_pred7__data_o$next[3:0]$11808 - attribute \src "libresoc.v:183277.3-183316.6" - wire width 4 $6\r27__data_o$next[3:0]$11817 - attribute \src "libresoc.v:183584.3-183623.6" - wire width 4 $6\r7__data_o$next[3:0]$11879 - attribute \src "libresoc.v:183374.3-183413.6" - wire width 4 $6\src17__data_o$next[3:0]$11837 - attribute \src "libresoc.v:183444.3-183483.6" - wire width 4 $6\src27__data_o$next[3:0]$11851 - attribute \src "libresoc.v:183514.3-183553.6" - wire width 4 $6\src37__data_o$next[3:0]$11865 - attribute \src "libresoc.v:183187.17-183187.104" - wire $not$libresoc.v:183187$11788_Y - attribute \src "libresoc.v:183188.18-183188.105" - wire $not$libresoc.v:183188$11789_Y - attribute \src "libresoc.v:183189.18-183189.105" - wire $not$libresoc.v:183189$11790_Y - attribute \src "libresoc.v:183190.17-183190.100" - wire $not$libresoc.v:183190$11791_Y - attribute \src "libresoc.v:183191.17-183191.103" - wire $not$libresoc.v:183191$11792_Y - attribute \src "libresoc.v:183192.17-183192.103" - wire $not$libresoc.v:183192$11793_Y + attribute \src "libresoc.v:183632.3-183671.6" + wire width 4 $5\r27__data_o$next[3:0]$11675 + attribute \src "libresoc.v:183562.3-183601.6" + wire width 4 $5\r7__data_o$next[3:0]$11661 + attribute \src "libresoc.v:183325.3-183364.6" + wire width 4 $5\src17__data_o$next[3:0]$11618 + attribute \src "libresoc.v:183422.3-183461.6" + wire width 4 $5\src27__data_o$next[3:0]$11633 + attribute \src "libresoc.v:183492.3-183531.6" + wire width 4 $5\src37__data_o$next[3:0]$11647 + attribute \src "libresoc.v:183632.3-183671.6" + wire width 4 $6\r27__data_o$next[3:0]$11676 + attribute \src "libresoc.v:183562.3-183601.6" + wire width 4 $6\r7__data_o$next[3:0]$11662 + attribute \src "libresoc.v:183325.3-183364.6" + wire width 4 $6\src17__data_o$next[3:0]$11619 + attribute \src "libresoc.v:183422.3-183461.6" + wire width 4 $6\src27__data_o$next[3:0]$11634 + attribute \src "libresoc.v:183492.3-183531.6" + wire width 4 $6\src37__data_o$next[3:0]$11648 + attribute \src "libresoc.v:183308.17-183308.104" + wire $not$libresoc.v:183308$11601_Y + attribute \src "libresoc.v:183309.18-183309.105" + wire $not$libresoc.v:183309$11602_Y + attribute \src "libresoc.v:183310.17-183310.100" + wire $not$libresoc.v:183310$11603_Y + attribute \src "libresoc.v:183311.17-183311.103" + wire $not$libresoc.v:183311$11604_Y + attribute \src "libresoc.v:183312.17-183312.103" + wire $not$libresoc.v:183312$11605_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" - wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \cr_pred7__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \cr_pred7__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \cr_pred7__ren + wire width 4 input 9 \dest17__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest17__data_i + wire input 8 \dest17__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest17__wen + wire width 4 input 11 \dest27__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 13 \dest27__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 12 \dest27__wen - attribute \src "libresoc.v:183100.7-183100.15" + wire input 10 \dest27__wen + attribute \src "libresoc.v:183232.7-183232.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 16 \r27__data_o + wire width 4 output 14 \r27__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r27__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \r27__ren + wire input 15 \r27__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r7__data_o + wire width 4 output 12 \r7__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r7__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r7__ren + wire input 13 \r7__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src17__data_o + wire width 4 output 3 \src17__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src17__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src17__ren + wire input 2 \src17__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src27__data_o + wire width 4 output 5 \src27__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src27__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src27__ren + wire input 4 \src27__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 9 \src37__data_o + wire width 4 output 7 \src37__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src37__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \src37__ren + wire input 6 \src37__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 18 \w7__data_i + wire width 4 input 16 \w7__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 19 \w7__wen + wire input 17 \w7__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -377195,257 +342326,232 @@ module \reg_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183187$11788 + cell $not $not$libresoc.v:183308$11601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:183187$11788_Y + connect \Y $not$libresoc.v:183308$11601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183188$11789 + cell $not $not$libresoc.v:183309$11602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:183188$11789_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183189$11790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$16 - connect \Y $not$libresoc.v:183189$11790_Y + connect \Y $not$libresoc.v:183309$11602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183190$11791 + cell $not $not$libresoc.v:183310$11603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:183190$11791_Y + connect \Y $not$libresoc.v:183310$11603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183191$11792 + cell $not $not$libresoc.v:183311$11604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:183191$11792_Y + connect \Y $not$libresoc.v:183311$11604_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183192$11793 + cell $not $not$libresoc.v:183312$11605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:183192$11793_Y + connect \Y $not$libresoc.v:183312$11605_Y end - attribute \src "libresoc.v:183100.7-183100.20" - process $proc$libresoc.v:183100$11886 + attribute \src "libresoc.v:183232.7-183232.20" + process $proc$libresoc.v:183232$11683 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183119.13-183119.36" - process $proc$libresoc.v:183119$11887 - assign { } { } - assign $1\cr_pred7__data_o[3:0] 4'0000 - sync always - sync init - update \cr_pred7__data_o $1\cr_pred7__data_o[3:0] - end - attribute \src "libresoc.v:183134.13-183134.31" - process $proc$libresoc.v:183134$11888 + attribute \src "libresoc.v:183257.13-183257.31" + process $proc$libresoc.v:183257$11684 assign { } { } assign $1\r27__data_o[3:0] 4'0000 sync always sync init update \r27__data_o $1\r27__data_o[3:0] end - attribute \src "libresoc.v:183141.13-183141.30" - process $proc$libresoc.v:183141$11889 + attribute \src "libresoc.v:183264.13-183264.30" + process $proc$libresoc.v:183264$11685 assign { } { } assign $1\r7__data_o[3:0] 4'0000 sync always sync init update \r7__data_o $1\r7__data_o[3:0] end - attribute \src "libresoc.v:183147.13-183147.25" - process $proc$libresoc.v:183147$11890 + attribute \src "libresoc.v:183270.13-183270.25" + process $proc$libresoc.v:183270$11686 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:183152.13-183152.33" - process $proc$libresoc.v:183152$11891 + attribute \src "libresoc.v:183275.13-183275.33" + process $proc$libresoc.v:183275$11687 assign { } { } assign $1\src17__data_o[3:0] 4'0000 sync always sync init update \src17__data_o $1\src17__data_o[3:0] end - attribute \src "libresoc.v:183159.13-183159.33" - process $proc$libresoc.v:183159$11892 + attribute \src "libresoc.v:183282.13-183282.33" + process $proc$libresoc.v:183282$11688 assign { } { } assign $1\src27__data_o[3:0] 4'0000 sync always sync init update \src27__data_o $1\src27__data_o[3:0] end - attribute \src "libresoc.v:183166.13-183166.33" - process $proc$libresoc.v:183166$11893 + attribute \src "libresoc.v:183289.13-183289.33" + process $proc$libresoc.v:183289$11689 assign { } { } assign $1\src37__data_o[3:0] 4'0000 sync always sync init update \src37__data_o $1\src37__data_o[3:0] end - attribute \src "libresoc.v:183193.3-183194.25" - process $proc$libresoc.v:183193$11794 + attribute \src "libresoc.v:183313.3-183314.25" + process $proc$libresoc.v:183313$11606 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:183195.3-183196.39" - process $proc$libresoc.v:183195$11795 + attribute \src "libresoc.v:183315.3-183316.39" + process $proc$libresoc.v:183315$11607 assign { } { } assign $0\r27__data_o[3:0] \r27__data_o$next sync posedge \coresync_clk update \r27__data_o $0\r27__data_o[3:0] end - attribute \src "libresoc.v:183197.3-183198.37" - process $proc$libresoc.v:183197$11796 + attribute \src "libresoc.v:183317.3-183318.37" + process $proc$libresoc.v:183317$11608 assign { } { } assign $0\r7__data_o[3:0] \r7__data_o$next sync posedge \coresync_clk update \r7__data_o $0\r7__data_o[3:0] end - attribute \src "libresoc.v:183199.3-183200.43" - process $proc$libresoc.v:183199$11797 + attribute \src "libresoc.v:183319.3-183320.43" + process $proc$libresoc.v:183319$11609 assign { } { } assign $0\src37__data_o[3:0] \src37__data_o$next sync posedge \coresync_clk update \src37__data_o $0\src37__data_o[3:0] end - attribute \src "libresoc.v:183201.3-183202.43" - process $proc$libresoc.v:183201$11798 + attribute \src "libresoc.v:183321.3-183322.43" + process $proc$libresoc.v:183321$11610 assign { } { } assign $0\src27__data_o[3:0] \src27__data_o$next sync posedge \coresync_clk update \src27__data_o $0\src27__data_o[3:0] end - attribute \src "libresoc.v:183203.3-183204.43" - process $proc$libresoc.v:183203$11799 + attribute \src "libresoc.v:183323.3-183324.43" + process $proc$libresoc.v:183323$11611 assign { } { } assign $0\src17__data_o[3:0] \src17__data_o$next sync posedge \coresync_clk update \src17__data_o $0\src17__data_o[3:0] end - attribute \src "libresoc.v:183205.3-183206.49" - process $proc$libresoc.v:183205$11800 + attribute \src "libresoc.v:183325.3-183364.6" + process $proc$libresoc.v:183325$11612 assign { } { } - assign $0\cr_pred7__data_o[3:0] \cr_pred7__data_o$next - sync posedge \coresync_clk - update \cr_pred7__data_o $0\cr_pred7__data_o[3:0] - end - attribute \src "libresoc.v:183207.3-183246.6" - process $proc$libresoc.v:183207$11801 assign { } { } assign { } { } - assign { } { } - assign $0\cr_pred7__data_o$next[3:0]$11802 $6\cr_pred7__data_o$next[3:0]$11808 - attribute \src "libresoc.v:183208.5-183208.29" + assign $0\src17__data_o$next[3:0]$11613 $6\src17__data_o$next[3:0]$11619 + attribute \src "libresoc.v:183326.5-183326.29" switch \initial - attribute \src "libresoc.v:183208.9-183208.17" + attribute \src "libresoc.v:183326.9-183326.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred7__ren + switch \src17__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\cr_pred7__data_o$next[3:0]$11803 $5\cr_pred7__data_o$next[3:0]$11807 + assign $1\src17__data_o$next[3:0]$11614 $5\src17__data_o$next[3:0]$11618 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred7__data_o$next[3:0]$11804 \dest17__data_i + assign $2\src17__data_o$next[3:0]$11615 \dest17__data_i case - assign $2\cr_pred7__data_o$next[3:0]$11804 4'0000 + assign $2\src17__data_o$next[3:0]$11615 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred7__data_o$next[3:0]$11805 \dest27__data_i + assign $3\src17__data_o$next[3:0]$11616 \dest27__data_i case - assign $3\cr_pred7__data_o$next[3:0]$11805 $2\cr_pred7__data_o$next[3:0]$11804 + assign $3\src17__data_o$next[3:0]$11616 $2\src17__data_o$next[3:0]$11615 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred7__data_o$next[3:0]$11806 \w7__data_i + assign $4\src17__data_o$next[3:0]$11617 \w7__data_i case - assign $4\cr_pred7__data_o$next[3:0]$11806 $3\cr_pred7__data_o$next[3:0]$11805 + assign $4\src17__data_o$next[3:0]$11617 $3\src17__data_o$next[3:0]$11616 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred7__data_o$next[3:0]$11807 \reg + assign $5\src17__data_o$next[3:0]$11618 \reg case - assign $5\cr_pred7__data_o$next[3:0]$11807 $4\cr_pred7__data_o$next[3:0]$11806 + assign $5\src17__data_o$next[3:0]$11618 $4\src17__data_o$next[3:0]$11617 end case - assign $1\cr_pred7__data_o$next[3:0]$11803 4'0000 + assign $1\src17__data_o$next[3:0]$11614 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred7__data_o$next[3:0]$11808 4'0000 + assign $6\src17__data_o$next[3:0]$11619 4'0000 case - assign $6\cr_pred7__data_o$next[3:0]$11808 $1\cr_pred7__data_o$next[3:0]$11803 + assign $6\src17__data_o$next[3:0]$11619 $1\src17__data_o$next[3:0]$11614 end sync always - update \cr_pred7__data_o$next $0\cr_pred7__data_o$next[3:0]$11802 + update \src17__data_o$next $0\src17__data_o$next[3:0]$11613 end - attribute \src "libresoc.v:183247.3-183276.6" - process $proc$libresoc.v:183247$11809 + attribute \src "libresoc.v:183365.3-183394.6" + process $proc$libresoc.v:183365$11620 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:183248.5-183248.29" + attribute \src "libresoc.v:183366.5-183366.29" switch \initial - attribute \src "libresoc.v:183248.9-183248.17" + attribute \src "libresoc.v:183366.9-183366.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cr_pred7__ren + switch \src17__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -377486,142 +342592,17 @@ module \reg_7 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:183277.3-183316.6" - process $proc$libresoc.v:183277$11810 + attribute \src "libresoc.v:183395.3-183421.6" + process $proc$libresoc.v:183395$11621 assign { } { } - assign { } { } - assign { } { } - assign $0\r27__data_o$next[3:0]$11811 $6\r27__data_o$next[3:0]$11817 - attribute \src "libresoc.v:183278.5-183278.29" - switch \initial - attribute \src "libresoc.v:183278.9-183278.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r27__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r27__data_o$next[3:0]$11812 $5\r27__data_o$next[3:0]$11816 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r27__data_o$next[3:0]$11813 \dest17__data_i - case - assign $2\r27__data_o$next[3:0]$11813 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r27__data_o$next[3:0]$11814 \dest27__data_i - case - assign $3\r27__data_o$next[3:0]$11814 $2\r27__data_o$next[3:0]$11813 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r27__data_o$next[3:0]$11815 \w7__data_i - case - assign $4\r27__data_o$next[3:0]$11815 $3\r27__data_o$next[3:0]$11814 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r27__data_o$next[3:0]$11816 \reg - case - assign $5\r27__data_o$next[3:0]$11816 $4\r27__data_o$next[3:0]$11815 - end - case - assign $1\r27__data_o$next[3:0]$11812 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r27__data_o$next[3:0]$11817 4'0000 - case - assign $6\r27__data_o$next[3:0]$11817 $1\r27__data_o$next[3:0]$11812 - end - sync always - update \r27__data_o$next $0\r27__data_o$next[3:0]$11811 - end - attribute \src "libresoc.v:183317.3-183346.6" - process $proc$libresoc.v:183317$11818 - assign { } { } - assign { } { } - assign $0\wr_detect$16[0:0]$11819 $1\wr_detect$16[0:0]$11820 - attribute \src "libresoc.v:183318.5-183318.29" - switch \initial - attribute \src "libresoc.v:183318.9-183318.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r27__ren - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$16[0:0]$11820 $4\wr_detect$16[0:0]$11823 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$16[0:0]$11821 1'1 - case - assign $2\wr_detect$16[0:0]$11821 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$16[0:0]$11822 1'1 - case - assign $3\wr_detect$16[0:0]$11822 $2\wr_detect$16[0:0]$11821 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$16[0:0]$11823 1'1 - case - assign $4\wr_detect$16[0:0]$11823 $3\wr_detect$16[0:0]$11822 - end - case - assign $1\wr_detect$16[0:0]$11820 1'0 - end - sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$11819 - end - attribute \src "libresoc.v:183347.3-183373.6" - process $proc$libresoc.v:183347$11824 assign { } { } assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\reg$next[3:0]$11825 $4\reg$next[3:0]$11829 - attribute \src "libresoc.v:183348.5-183348.29" + assign $0\reg$next[3:0]$11622 $4\reg$next[3:0]$11626 + attribute \src "libresoc.v:183396.5-183396.29" switch \initial - attribute \src "libresoc.v:183348.9-183348.17" + attribute \src "libresoc.v:183396.9-183396.17" case 1'1 case end @@ -377630,578 +342611,577 @@ module \reg_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11826 \dest17__data_i + assign $1\reg$next[3:0]$11623 \dest17__data_i case - assign $1\reg$next[3:0]$11826 \reg + assign $1\reg$next[3:0]$11623 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11827 \dest27__data_i + assign $2\reg$next[3:0]$11624 \dest27__data_i case - assign $2\reg$next[3:0]$11827 $1\reg$next[3:0]$11826 + assign $2\reg$next[3:0]$11624 $1\reg$next[3:0]$11623 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11828 \w7__data_i + assign $3\reg$next[3:0]$11625 \w7__data_i case - assign $3\reg$next[3:0]$11828 $2\reg$next[3:0]$11827 + assign $3\reg$next[3:0]$11625 $2\reg$next[3:0]$11624 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11829 4'0000 + assign $4\reg$next[3:0]$11626 4'0000 case - assign $4\reg$next[3:0]$11829 $3\reg$next[3:0]$11828 + assign $4\reg$next[3:0]$11626 $3\reg$next[3:0]$11625 end sync always - update \reg$next $0\reg$next[3:0]$11825 + update \reg$next $0\reg$next[3:0]$11622 end - attribute \src "libresoc.v:183374.3-183413.6" - process $proc$libresoc.v:183374$11830 + attribute \src "libresoc.v:183422.3-183461.6" + process $proc$libresoc.v:183422$11627 assign { } { } assign { } { } assign { } { } - assign $0\src17__data_o$next[3:0]$11831 $6\src17__data_o$next[3:0]$11837 - attribute \src "libresoc.v:183375.5-183375.29" + assign $0\src27__data_o$next[3:0]$11628 $6\src27__data_o$next[3:0]$11634 + attribute \src "libresoc.v:183423.5-183423.29" switch \initial - attribute \src "libresoc.v:183375.9-183375.17" + attribute \src "libresoc.v:183423.9-183423.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src17__ren + switch \src27__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src17__data_o$next[3:0]$11832 $5\src17__data_o$next[3:0]$11836 + assign $1\src27__data_o$next[3:0]$11629 $5\src27__data_o$next[3:0]$11633 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src17__data_o$next[3:0]$11833 \dest17__data_i + assign $2\src27__data_o$next[3:0]$11630 \dest17__data_i case - assign $2\src17__data_o$next[3:0]$11833 4'0000 + assign $2\src27__data_o$next[3:0]$11630 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src17__data_o$next[3:0]$11834 \dest27__data_i + assign $3\src27__data_o$next[3:0]$11631 \dest27__data_i case - assign $3\src17__data_o$next[3:0]$11834 $2\src17__data_o$next[3:0]$11833 + assign $3\src27__data_o$next[3:0]$11631 $2\src27__data_o$next[3:0]$11630 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src17__data_o$next[3:0]$11835 \w7__data_i + assign $4\src27__data_o$next[3:0]$11632 \w7__data_i case - assign $4\src17__data_o$next[3:0]$11835 $3\src17__data_o$next[3:0]$11834 + assign $4\src27__data_o$next[3:0]$11632 $3\src27__data_o$next[3:0]$11631 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src17__data_o$next[3:0]$11836 \reg + assign $5\src27__data_o$next[3:0]$11633 \reg case - assign $5\src17__data_o$next[3:0]$11836 $4\src17__data_o$next[3:0]$11835 + assign $5\src27__data_o$next[3:0]$11633 $4\src27__data_o$next[3:0]$11632 end case - assign $1\src17__data_o$next[3:0]$11832 4'0000 + assign $1\src27__data_o$next[3:0]$11629 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src17__data_o$next[3:0]$11837 4'0000 + assign $6\src27__data_o$next[3:0]$11634 4'0000 case - assign $6\src17__data_o$next[3:0]$11837 $1\src17__data_o$next[3:0]$11832 + assign $6\src27__data_o$next[3:0]$11634 $1\src27__data_o$next[3:0]$11629 end sync always - update \src17__data_o$next $0\src17__data_o$next[3:0]$11831 + update \src27__data_o$next $0\src27__data_o$next[3:0]$11628 end - attribute \src "libresoc.v:183414.3-183443.6" - process $proc$libresoc.v:183414$11838 + attribute \src "libresoc.v:183462.3-183491.6" + process $proc$libresoc.v:183462$11635 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11839 $1\wr_detect$4[0:0]$11840 - attribute \src "libresoc.v:183415.5-183415.29" + assign $0\wr_detect$4[0:0]$11636 $1\wr_detect$4[0:0]$11637 + attribute \src "libresoc.v:183463.5-183463.29" switch \initial - attribute \src "libresoc.v:183415.9-183415.17" + attribute \src "libresoc.v:183463.9-183463.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src17__ren + switch \src27__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11840 $4\wr_detect$4[0:0]$11843 + assign $1\wr_detect$4[0:0]$11637 $4\wr_detect$4[0:0]$11640 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11841 1'1 + assign $2\wr_detect$4[0:0]$11638 1'1 case - assign $2\wr_detect$4[0:0]$11841 1'0 + assign $2\wr_detect$4[0:0]$11638 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11842 1'1 + assign $3\wr_detect$4[0:0]$11639 1'1 case - assign $3\wr_detect$4[0:0]$11842 $2\wr_detect$4[0:0]$11841 + assign $3\wr_detect$4[0:0]$11639 $2\wr_detect$4[0:0]$11638 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11843 1'1 + assign $4\wr_detect$4[0:0]$11640 1'1 case - assign $4\wr_detect$4[0:0]$11843 $3\wr_detect$4[0:0]$11842 + assign $4\wr_detect$4[0:0]$11640 $3\wr_detect$4[0:0]$11639 end case - assign $1\wr_detect$4[0:0]$11840 1'0 + assign $1\wr_detect$4[0:0]$11637 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11839 + update \wr_detect$4 $0\wr_detect$4[0:0]$11636 end - attribute \src "libresoc.v:183444.3-183483.6" - process $proc$libresoc.v:183444$11844 + attribute \src "libresoc.v:183492.3-183531.6" + process $proc$libresoc.v:183492$11641 assign { } { } assign { } { } assign { } { } - assign $0\src27__data_o$next[3:0]$11845 $6\src27__data_o$next[3:0]$11851 - attribute \src "libresoc.v:183445.5-183445.29" + assign $0\src37__data_o$next[3:0]$11642 $6\src37__data_o$next[3:0]$11648 + attribute \src "libresoc.v:183493.5-183493.29" switch \initial - attribute \src "libresoc.v:183445.9-183445.17" + attribute \src "libresoc.v:183493.9-183493.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src27__ren + switch \src37__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src27__data_o$next[3:0]$11846 $5\src27__data_o$next[3:0]$11850 + assign $1\src37__data_o$next[3:0]$11643 $5\src37__data_o$next[3:0]$11647 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src27__data_o$next[3:0]$11847 \dest17__data_i + assign $2\src37__data_o$next[3:0]$11644 \dest17__data_i case - assign $2\src27__data_o$next[3:0]$11847 4'0000 + assign $2\src37__data_o$next[3:0]$11644 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src27__data_o$next[3:0]$11848 \dest27__data_i + assign $3\src37__data_o$next[3:0]$11645 \dest27__data_i case - assign $3\src27__data_o$next[3:0]$11848 $2\src27__data_o$next[3:0]$11847 + assign $3\src37__data_o$next[3:0]$11645 $2\src37__data_o$next[3:0]$11644 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src27__data_o$next[3:0]$11849 \w7__data_i + assign $4\src37__data_o$next[3:0]$11646 \w7__data_i case - assign $4\src27__data_o$next[3:0]$11849 $3\src27__data_o$next[3:0]$11848 + assign $4\src37__data_o$next[3:0]$11646 $3\src37__data_o$next[3:0]$11645 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src27__data_o$next[3:0]$11850 \reg + assign $5\src37__data_o$next[3:0]$11647 \reg case - assign $5\src27__data_o$next[3:0]$11850 $4\src27__data_o$next[3:0]$11849 + assign $5\src37__data_o$next[3:0]$11647 $4\src37__data_o$next[3:0]$11646 end case - assign $1\src27__data_o$next[3:0]$11846 4'0000 + assign $1\src37__data_o$next[3:0]$11643 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src27__data_o$next[3:0]$11851 4'0000 + assign $6\src37__data_o$next[3:0]$11648 4'0000 case - assign $6\src27__data_o$next[3:0]$11851 $1\src27__data_o$next[3:0]$11846 + assign $6\src37__data_o$next[3:0]$11648 $1\src37__data_o$next[3:0]$11643 end sync always - update \src27__data_o$next $0\src27__data_o$next[3:0]$11845 + update \src37__data_o$next $0\src37__data_o$next[3:0]$11642 end - attribute \src "libresoc.v:183484.3-183513.6" - process $proc$libresoc.v:183484$11852 + attribute \src "libresoc.v:183532.3-183561.6" + process $proc$libresoc.v:183532$11649 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11853 $1\wr_detect$7[0:0]$11854 - attribute \src "libresoc.v:183485.5-183485.29" + assign $0\wr_detect$7[0:0]$11650 $1\wr_detect$7[0:0]$11651 + attribute \src "libresoc.v:183533.5-183533.29" switch \initial - attribute \src "libresoc.v:183485.9-183485.17" + attribute \src "libresoc.v:183533.9-183533.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src27__ren + switch \src37__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11854 $4\wr_detect$7[0:0]$11857 + assign $1\wr_detect$7[0:0]$11651 $4\wr_detect$7[0:0]$11654 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11855 1'1 + assign $2\wr_detect$7[0:0]$11652 1'1 case - assign $2\wr_detect$7[0:0]$11855 1'0 + assign $2\wr_detect$7[0:0]$11652 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11856 1'1 + assign $3\wr_detect$7[0:0]$11653 1'1 case - assign $3\wr_detect$7[0:0]$11856 $2\wr_detect$7[0:0]$11855 + assign $3\wr_detect$7[0:0]$11653 $2\wr_detect$7[0:0]$11652 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11857 1'1 + assign $4\wr_detect$7[0:0]$11654 1'1 case - assign $4\wr_detect$7[0:0]$11857 $3\wr_detect$7[0:0]$11856 + assign $4\wr_detect$7[0:0]$11654 $3\wr_detect$7[0:0]$11653 end case - assign $1\wr_detect$7[0:0]$11854 1'0 + assign $1\wr_detect$7[0:0]$11651 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11853 + update \wr_detect$7 $0\wr_detect$7[0:0]$11650 end - attribute \src "libresoc.v:183514.3-183553.6" - process $proc$libresoc.v:183514$11858 + attribute \src "libresoc.v:183562.3-183601.6" + process $proc$libresoc.v:183562$11655 assign { } { } assign { } { } assign { } { } - assign $0\src37__data_o$next[3:0]$11859 $6\src37__data_o$next[3:0]$11865 - attribute \src "libresoc.v:183515.5-183515.29" + assign $0\r7__data_o$next[3:0]$11656 $6\r7__data_o$next[3:0]$11662 + attribute \src "libresoc.v:183563.5-183563.29" switch \initial - attribute \src "libresoc.v:183515.9-183515.17" + attribute \src "libresoc.v:183563.9-183563.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src37__ren + switch \r7__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src37__data_o$next[3:0]$11860 $5\src37__data_o$next[3:0]$11864 + assign $1\r7__data_o$next[3:0]$11657 $5\r7__data_o$next[3:0]$11661 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src37__data_o$next[3:0]$11861 \dest17__data_i + assign $2\r7__data_o$next[3:0]$11658 \dest17__data_i case - assign $2\src37__data_o$next[3:0]$11861 4'0000 + assign $2\r7__data_o$next[3:0]$11658 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src37__data_o$next[3:0]$11862 \dest27__data_i + assign $3\r7__data_o$next[3:0]$11659 \dest27__data_i case - assign $3\src37__data_o$next[3:0]$11862 $2\src37__data_o$next[3:0]$11861 + assign $3\r7__data_o$next[3:0]$11659 $2\r7__data_o$next[3:0]$11658 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src37__data_o$next[3:0]$11863 \w7__data_i + assign $4\r7__data_o$next[3:0]$11660 \w7__data_i case - assign $4\src37__data_o$next[3:0]$11863 $3\src37__data_o$next[3:0]$11862 + assign $4\r7__data_o$next[3:0]$11660 $3\r7__data_o$next[3:0]$11659 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src37__data_o$next[3:0]$11864 \reg + assign $5\r7__data_o$next[3:0]$11661 \reg case - assign $5\src37__data_o$next[3:0]$11864 $4\src37__data_o$next[3:0]$11863 + assign $5\r7__data_o$next[3:0]$11661 $4\r7__data_o$next[3:0]$11660 end case - assign $1\src37__data_o$next[3:0]$11860 4'0000 + assign $1\r7__data_o$next[3:0]$11657 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src37__data_o$next[3:0]$11865 4'0000 + assign $6\r7__data_o$next[3:0]$11662 4'0000 case - assign $6\src37__data_o$next[3:0]$11865 $1\src37__data_o$next[3:0]$11860 + assign $6\r7__data_o$next[3:0]$11662 $1\r7__data_o$next[3:0]$11657 end sync always - update \src37__data_o$next $0\src37__data_o$next[3:0]$11859 + update \r7__data_o$next $0\r7__data_o$next[3:0]$11656 end - attribute \src "libresoc.v:183554.3-183583.6" - process $proc$libresoc.v:183554$11866 + attribute \src "libresoc.v:183602.3-183631.6" + process $proc$libresoc.v:183602$11663 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11867 $1\wr_detect$10[0:0]$11868 - attribute \src "libresoc.v:183555.5-183555.29" + assign $0\wr_detect$10[0:0]$11664 $1\wr_detect$10[0:0]$11665 + attribute \src "libresoc.v:183603.5-183603.29" switch \initial - attribute \src "libresoc.v:183555.9-183555.17" + attribute \src "libresoc.v:183603.9-183603.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src37__ren + switch \r7__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11868 $4\wr_detect$10[0:0]$11871 + assign $1\wr_detect$10[0:0]$11665 $4\wr_detect$10[0:0]$11668 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11869 1'1 + assign $2\wr_detect$10[0:0]$11666 1'1 case - assign $2\wr_detect$10[0:0]$11869 1'0 + assign $2\wr_detect$10[0:0]$11666 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11870 1'1 + assign $3\wr_detect$10[0:0]$11667 1'1 case - assign $3\wr_detect$10[0:0]$11870 $2\wr_detect$10[0:0]$11869 + assign $3\wr_detect$10[0:0]$11667 $2\wr_detect$10[0:0]$11666 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11871 1'1 + assign $4\wr_detect$10[0:0]$11668 1'1 case - assign $4\wr_detect$10[0:0]$11871 $3\wr_detect$10[0:0]$11870 + assign $4\wr_detect$10[0:0]$11668 $3\wr_detect$10[0:0]$11667 end case - assign $1\wr_detect$10[0:0]$11868 1'0 + assign $1\wr_detect$10[0:0]$11665 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11867 + update \wr_detect$10 $0\wr_detect$10[0:0]$11664 end - attribute \src "libresoc.v:183584.3-183623.6" - process $proc$libresoc.v:183584$11872 + attribute \src "libresoc.v:183632.3-183671.6" + process $proc$libresoc.v:183632$11669 assign { } { } assign { } { } assign { } { } - assign $0\r7__data_o$next[3:0]$11873 $6\r7__data_o$next[3:0]$11879 - attribute \src "libresoc.v:183585.5-183585.29" + assign $0\r27__data_o$next[3:0]$11670 $6\r27__data_o$next[3:0]$11676 + attribute \src "libresoc.v:183633.5-183633.29" switch \initial - attribute \src "libresoc.v:183585.9-183585.17" + attribute \src "libresoc.v:183633.9-183633.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r7__ren + switch \r27__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r7__data_o$next[3:0]$11874 $5\r7__data_o$next[3:0]$11878 + assign $1\r27__data_o$next[3:0]$11671 $5\r27__data_o$next[3:0]$11675 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r7__data_o$next[3:0]$11875 \dest17__data_i + assign $2\r27__data_o$next[3:0]$11672 \dest17__data_i case - assign $2\r7__data_o$next[3:0]$11875 4'0000 + assign $2\r27__data_o$next[3:0]$11672 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r7__data_o$next[3:0]$11876 \dest27__data_i + assign $3\r27__data_o$next[3:0]$11673 \dest27__data_i case - assign $3\r7__data_o$next[3:0]$11876 $2\r7__data_o$next[3:0]$11875 + assign $3\r27__data_o$next[3:0]$11673 $2\r27__data_o$next[3:0]$11672 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r7__data_o$next[3:0]$11877 \w7__data_i + assign $4\r27__data_o$next[3:0]$11674 \w7__data_i case - assign $4\r7__data_o$next[3:0]$11877 $3\r7__data_o$next[3:0]$11876 + assign $4\r27__data_o$next[3:0]$11674 $3\r27__data_o$next[3:0]$11673 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r7__data_o$next[3:0]$11878 \reg + assign $5\r27__data_o$next[3:0]$11675 \reg case - assign $5\r7__data_o$next[3:0]$11878 $4\r7__data_o$next[3:0]$11877 + assign $5\r27__data_o$next[3:0]$11675 $4\r27__data_o$next[3:0]$11674 end case - assign $1\r7__data_o$next[3:0]$11874 4'0000 + assign $1\r27__data_o$next[3:0]$11671 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r7__data_o$next[3:0]$11879 4'0000 + assign $6\r27__data_o$next[3:0]$11676 4'0000 case - assign $6\r7__data_o$next[3:0]$11879 $1\r7__data_o$next[3:0]$11874 + assign $6\r27__data_o$next[3:0]$11676 $1\r27__data_o$next[3:0]$11671 end sync always - update \r7__data_o$next $0\r7__data_o$next[3:0]$11873 + update \r27__data_o$next $0\r27__data_o$next[3:0]$11670 end - attribute \src "libresoc.v:183624.3-183653.6" - process $proc$libresoc.v:183624$11880 + attribute \src "libresoc.v:183672.3-183701.6" + process $proc$libresoc.v:183672$11677 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11881 $1\wr_detect$13[0:0]$11882 - attribute \src "libresoc.v:183625.5-183625.29" + assign $0\wr_detect$13[0:0]$11678 $1\wr_detect$13[0:0]$11679 + attribute \src "libresoc.v:183673.5-183673.29" switch \initial - attribute \src "libresoc.v:183625.9-183625.17" + attribute \src "libresoc.v:183673.9-183673.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r7__ren + switch \r27__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11882 $4\wr_detect$13[0:0]$11885 + assign $1\wr_detect$13[0:0]$11679 $4\wr_detect$13[0:0]$11682 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11883 1'1 + assign $2\wr_detect$13[0:0]$11680 1'1 case - assign $2\wr_detect$13[0:0]$11883 1'0 + assign $2\wr_detect$13[0:0]$11680 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11884 1'1 + assign $3\wr_detect$13[0:0]$11681 1'1 case - assign $3\wr_detect$13[0:0]$11884 $2\wr_detect$13[0:0]$11883 + assign $3\wr_detect$13[0:0]$11681 $2\wr_detect$13[0:0]$11680 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11885 1'1 + assign $4\wr_detect$13[0:0]$11682 1'1 case - assign $4\wr_detect$13[0:0]$11885 $3\wr_detect$13[0:0]$11884 + assign $4\wr_detect$13[0:0]$11682 $3\wr_detect$13[0:0]$11681 end case - assign $1\wr_detect$13[0:0]$11882 1'0 + assign $1\wr_detect$13[0:0]$11679 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11881 + update \wr_detect$13 $0\wr_detect$13[0:0]$11678 end - connect \$9 $not$libresoc.v:183187$11788_Y - connect \$12 $not$libresoc.v:183188$11789_Y - connect \$15 $not$libresoc.v:183189$11790_Y - connect \$1 $not$libresoc.v:183190$11791_Y - connect \$3 $not$libresoc.v:183191$11792_Y - connect \$6 $not$libresoc.v:183192$11793_Y + connect \$9 $not$libresoc.v:183308$11601_Y + connect \$12 $not$libresoc.v:183309$11602_Y + connect \$1 $not$libresoc.v:183310$11603_Y + connect \$3 $not$libresoc.v:183311$11604_Y + connect \$6 $not$libresoc.v:183312$11605_Y end -attribute \src "libresoc.v:183658.1-183716.10" +attribute \src "libresoc.v:183706.1-183764.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" attribute \generator "nMigen" module \req_l - attribute \src "libresoc.v:183659.7-183659.20" + attribute \src "libresoc.v:183707.7-183707.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183704.3-183712.6" - wire width 5 $0\q_int$next[4:0]$11904 - attribute \src "libresoc.v:183702.3-183703.27" + attribute \src "libresoc.v:183752.3-183760.6" + wire width 5 $0\q_int$next[4:0]$11700 + attribute \src "libresoc.v:183750.3-183751.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:183704.3-183712.6" - wire width 5 $1\q_int$next[4:0]$11905 - attribute \src "libresoc.v:183681.13-183681.26" + attribute \src "libresoc.v:183752.3-183760.6" + wire width 5 $1\q_int$next[4:0]$11701 + attribute \src "libresoc.v:183729.13-183729.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:183694.17-183694.96" - wire width 5 $and$libresoc.v:183694$11894_Y - attribute \src "libresoc.v:183699.17-183699.96" - wire width 5 $and$libresoc.v:183699$11899_Y - attribute \src "libresoc.v:183696.18-183696.93" - wire width 5 $not$libresoc.v:183696$11896_Y - attribute \src "libresoc.v:183698.17-183698.92" - wire width 5 $not$libresoc.v:183698$11898_Y - attribute \src "libresoc.v:183701.17-183701.92" - wire width 5 $not$libresoc.v:183701$11901_Y - attribute \src "libresoc.v:183695.18-183695.98" - wire width 5 $or$libresoc.v:183695$11895_Y - attribute \src "libresoc.v:183697.18-183697.99" - wire width 5 $or$libresoc.v:183697$11897_Y - attribute \src "libresoc.v:183700.17-183700.97" - wire width 5 $or$libresoc.v:183700$11900_Y + attribute \src "libresoc.v:183742.17-183742.96" + wire width 5 $and$libresoc.v:183742$11690_Y + attribute \src "libresoc.v:183747.17-183747.96" + wire width 5 $and$libresoc.v:183747$11695_Y + attribute \src "libresoc.v:183744.18-183744.93" + wire width 5 $not$libresoc.v:183744$11692_Y + attribute \src "libresoc.v:183746.17-183746.92" + wire width 5 $not$libresoc.v:183746$11694_Y + attribute \src "libresoc.v:183749.17-183749.92" + wire width 5 $not$libresoc.v:183749$11697_Y + attribute \src "libresoc.v:183743.18-183743.98" + wire width 5 $or$libresoc.v:183743$11691_Y + attribute \src "libresoc.v:183745.18-183745.99" + wire width 5 $or$libresoc.v:183745$11693_Y + attribute \src "libresoc.v:183748.17-183748.97" + wire width 5 $or$libresoc.v:183748$11696_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378218,11 +343198,11 @@ module \req_l wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:183659.7-183659.15" + attribute \src "libresoc.v:183707.7-183707.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -378239,7 +343219,7 @@ module \req_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183694$11894 + cell $and $and$libresoc.v:183742$11690 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -378247,10 +343227,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183694$11894_Y + connect \Y $and$libresoc.v:183742$11690_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183699$11899 + cell $and $and$libresoc.v:183747$11695 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -378258,34 +343238,34 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183699$11899_Y + connect \Y $and$libresoc.v:183747$11695_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183696$11896 + cell $not $not$libresoc.v:183744$11692 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:183696$11896_Y + connect \Y $not$libresoc.v:183744$11692_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183698$11898 + cell $not $not$libresoc.v:183746$11694 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:183698$11898_Y + connect \Y $not$libresoc.v:183746$11694_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183701$11901 + cell $not $not$libresoc.v:183749$11697 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:183701$11901_Y + connect \Y $not$libresoc.v:183749$11697_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183695$11895 + cell $or $or$libresoc.v:183743$11691 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -378293,10 +343273,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183695$11895_Y + connect \Y $or$libresoc.v:183743$11691_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183697$11897 + cell $or $or$libresoc.v:183745$11693 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -378304,10 +343284,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183697$11897_Y + connect \Y $or$libresoc.v:183745$11693_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183700$11900 + cell $or $or$libresoc.v:183748$11696 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -378315,39 +343295,39 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183700$11900_Y + connect \Y $or$libresoc.v:183748$11696_Y end - attribute \src "libresoc.v:183659.7-183659.20" - process $proc$libresoc.v:183659$11906 + attribute \src "libresoc.v:183707.7-183707.20" + process $proc$libresoc.v:183707$11702 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183681.13-183681.26" - process $proc$libresoc.v:183681$11907 + attribute \src "libresoc.v:183729.13-183729.26" + process $proc$libresoc.v:183729$11703 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:183702.3-183703.27" - process $proc$libresoc.v:183702$11902 + attribute \src "libresoc.v:183750.3-183751.27" + process $proc$libresoc.v:183750$11698 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:183704.3-183712.6" - process $proc$libresoc.v:183704$11903 + attribute \src "libresoc.v:183752.3-183760.6" + process $proc$libresoc.v:183752$11699 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11904 $1\q_int$next[4:0]$11905 - attribute \src "libresoc.v:183705.5-183705.29" + assign $0\q_int$next[4:0]$11700 $1\q_int$next[4:0]$11701 + attribute \src "libresoc.v:183753.5-183753.29" switch \initial - attribute \src "libresoc.v:183705.9-183705.17" + attribute \src "libresoc.v:183753.9-183753.17" case 1'1 case end @@ -378356,56 +343336,56 @@ module \req_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11905 5'00000 + assign $1\q_int$next[4:0]$11701 5'00000 case - assign $1\q_int$next[4:0]$11905 \$5 + assign $1\q_int$next[4:0]$11701 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11904 + update \q_int$next $0\q_int$next[4:0]$11700 end - connect \$9 $and$libresoc.v:183694$11894_Y - connect \$11 $or$libresoc.v:183695$11895_Y - connect \$13 $not$libresoc.v:183696$11896_Y - connect \$15 $or$libresoc.v:183697$11897_Y - connect \$1 $not$libresoc.v:183698$11898_Y - connect \$3 $and$libresoc.v:183699$11899_Y - connect \$5 $or$libresoc.v:183700$11900_Y - connect \$7 $not$libresoc.v:183701$11901_Y + connect \$9 $and$libresoc.v:183742$11690_Y + connect \$11 $or$libresoc.v:183743$11691_Y + connect \$13 $not$libresoc.v:183744$11692_Y + connect \$15 $or$libresoc.v:183745$11693_Y + connect \$1 $not$libresoc.v:183746$11694_Y + connect \$3 $and$libresoc.v:183747$11695_Y + connect \$5 $or$libresoc.v:183748$11696_Y + connect \$7 $not$libresoc.v:183749$11697_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183720.1-183778.10" +attribute \src "libresoc.v:183768.1-183826.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l" attribute \generator "nMigen" module \req_l$103 - attribute \src "libresoc.v:183721.7-183721.20" + attribute \src "libresoc.v:183769.7-183769.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183766.3-183774.6" - wire width 4 $0\q_int$next[3:0]$11918 - attribute \src "libresoc.v:183764.3-183765.27" + attribute \src "libresoc.v:183814.3-183822.6" + wire width 4 $0\q_int$next[3:0]$11714 + attribute \src "libresoc.v:183812.3-183813.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:183766.3-183774.6" - wire width 4 $1\q_int$next[3:0]$11919 - attribute \src "libresoc.v:183743.13-183743.25" + attribute \src "libresoc.v:183814.3-183822.6" + wire width 4 $1\q_int$next[3:0]$11715 + attribute \src "libresoc.v:183791.13-183791.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:183756.17-183756.96" - wire width 4 $and$libresoc.v:183756$11908_Y - attribute \src "libresoc.v:183761.17-183761.96" - wire width 4 $and$libresoc.v:183761$11913_Y - attribute \src "libresoc.v:183758.18-183758.93" - wire width 4 $not$libresoc.v:183758$11910_Y - attribute \src "libresoc.v:183760.17-183760.92" - wire width 4 $not$libresoc.v:183760$11912_Y - attribute \src "libresoc.v:183763.17-183763.92" - wire width 4 $not$libresoc.v:183763$11915_Y - attribute \src "libresoc.v:183757.18-183757.98" - wire width 4 $or$libresoc.v:183757$11909_Y - attribute \src "libresoc.v:183759.18-183759.99" - wire width 4 $or$libresoc.v:183759$11911_Y - attribute \src "libresoc.v:183762.17-183762.97" - wire width 4 $or$libresoc.v:183762$11914_Y + attribute \src "libresoc.v:183804.17-183804.96" + wire width 4 $and$libresoc.v:183804$11704_Y + attribute \src "libresoc.v:183809.17-183809.96" + wire width 4 $and$libresoc.v:183809$11709_Y + attribute \src "libresoc.v:183806.18-183806.93" + wire width 4 $not$libresoc.v:183806$11706_Y + attribute \src "libresoc.v:183808.17-183808.92" + wire width 4 $not$libresoc.v:183808$11708_Y + attribute \src "libresoc.v:183811.17-183811.92" + wire width 4 $not$libresoc.v:183811$11711_Y + attribute \src "libresoc.v:183805.18-183805.98" + wire width 4 $or$libresoc.v:183805$11705_Y + attribute \src "libresoc.v:183807.18-183807.99" + wire width 4 $or$libresoc.v:183807$11707_Y + attribute \src "libresoc.v:183810.17-183810.97" + wire width 4 $or$libresoc.v:183810$11710_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378422,11 +343402,11 @@ module \req_l$103 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:183721.7-183721.15" + attribute \src "libresoc.v:183769.7-183769.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -378443,7 +343423,7 @@ module \req_l$103 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183756$11908 + cell $and $and$libresoc.v:183804$11704 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -378451,10 +343431,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183756$11908_Y + connect \Y $and$libresoc.v:183804$11704_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183761$11913 + cell $and $and$libresoc.v:183809$11709 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -378462,34 +343442,34 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183761$11913_Y + connect \Y $and$libresoc.v:183809$11709_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183758$11910 + cell $not $not$libresoc.v:183806$11706 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:183758$11910_Y + connect \Y $not$libresoc.v:183806$11706_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183760$11912 + cell $not $not$libresoc.v:183808$11708 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:183760$11912_Y + connect \Y $not$libresoc.v:183808$11708_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183763$11915 + cell $not $not$libresoc.v:183811$11711 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:183763$11915_Y + connect \Y $not$libresoc.v:183811$11711_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183757$11909 + cell $or $or$libresoc.v:183805$11705 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -378497,10 +343477,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183757$11909_Y + connect \Y $or$libresoc.v:183805$11705_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183759$11911 + cell $or $or$libresoc.v:183807$11707 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -378508,10 +343488,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183759$11911_Y + connect \Y $or$libresoc.v:183807$11707_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183762$11914 + cell $or $or$libresoc.v:183810$11710 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -378519,39 +343499,39 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183762$11914_Y + connect \Y $or$libresoc.v:183810$11710_Y end - attribute \src "libresoc.v:183721.7-183721.20" - process $proc$libresoc.v:183721$11920 + attribute \src "libresoc.v:183769.7-183769.20" + process $proc$libresoc.v:183769$11716 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183743.13-183743.25" - process $proc$libresoc.v:183743$11921 + attribute \src "libresoc.v:183791.13-183791.25" + process $proc$libresoc.v:183791$11717 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:183764.3-183765.27" - process $proc$libresoc.v:183764$11916 + attribute \src "libresoc.v:183812.3-183813.27" + process $proc$libresoc.v:183812$11712 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:183766.3-183774.6" - process $proc$libresoc.v:183766$11917 + attribute \src "libresoc.v:183814.3-183822.6" + process $proc$libresoc.v:183814$11713 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11918 $1\q_int$next[3:0]$11919 - attribute \src "libresoc.v:183767.5-183767.29" + assign $0\q_int$next[3:0]$11714 $1\q_int$next[3:0]$11715 + attribute \src "libresoc.v:183815.5-183815.29" switch \initial - attribute \src "libresoc.v:183767.9-183767.17" + attribute \src "libresoc.v:183815.9-183815.17" case 1'1 case end @@ -378560,56 +343540,56 @@ module \req_l$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$11919 4'0000 + assign $1\q_int$next[3:0]$11715 4'0000 case - assign $1\q_int$next[3:0]$11919 \$5 + assign $1\q_int$next[3:0]$11715 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$11918 + update \q_int$next $0\q_int$next[3:0]$11714 end - connect \$9 $and$libresoc.v:183756$11908_Y - connect \$11 $or$libresoc.v:183757$11909_Y - connect \$13 $not$libresoc.v:183758$11910_Y - connect \$15 $or$libresoc.v:183759$11911_Y - connect \$1 $not$libresoc.v:183760$11912_Y - connect \$3 $and$libresoc.v:183761$11913_Y - connect \$5 $or$libresoc.v:183762$11914_Y - connect \$7 $not$libresoc.v:183763$11915_Y + connect \$9 $and$libresoc.v:183804$11704_Y + connect \$11 $or$libresoc.v:183805$11705_Y + connect \$13 $not$libresoc.v:183806$11706_Y + connect \$15 $or$libresoc.v:183807$11707_Y + connect \$1 $not$libresoc.v:183808$11708_Y + connect \$3 $and$libresoc.v:183809$11709_Y + connect \$5 $or$libresoc.v:183810$11710_Y + connect \$7 $not$libresoc.v:183811$11711_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183782.1-183840.10" +attribute \src "libresoc.v:183830.1-183888.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l" attribute \generator "nMigen" module \req_l$12 - attribute \src "libresoc.v:183783.7-183783.20" + attribute \src "libresoc.v:183831.7-183831.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183828.3-183836.6" - wire width 3 $0\q_int$next[2:0]$11932 - attribute \src "libresoc.v:183826.3-183827.27" + attribute \src "libresoc.v:183876.3-183884.6" + wire width 3 $0\q_int$next[2:0]$11728 + attribute \src "libresoc.v:183874.3-183875.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:183828.3-183836.6" - wire width 3 $1\q_int$next[2:0]$11933 - attribute \src "libresoc.v:183805.13-183805.25" + attribute \src "libresoc.v:183876.3-183884.6" + wire width 3 $1\q_int$next[2:0]$11729 + attribute \src "libresoc.v:183853.13-183853.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:183818.17-183818.96" - wire width 3 $and$libresoc.v:183818$11922_Y - attribute \src "libresoc.v:183823.17-183823.96" - wire width 3 $and$libresoc.v:183823$11927_Y - attribute \src "libresoc.v:183820.18-183820.93" - wire width 3 $not$libresoc.v:183820$11924_Y - attribute \src "libresoc.v:183822.17-183822.92" - wire width 3 $not$libresoc.v:183822$11926_Y - attribute \src "libresoc.v:183825.17-183825.92" - wire width 3 $not$libresoc.v:183825$11929_Y - attribute \src "libresoc.v:183819.18-183819.98" - wire width 3 $or$libresoc.v:183819$11923_Y - attribute \src "libresoc.v:183821.18-183821.99" - wire width 3 $or$libresoc.v:183821$11925_Y - attribute \src "libresoc.v:183824.17-183824.97" - wire width 3 $or$libresoc.v:183824$11928_Y + attribute \src "libresoc.v:183866.17-183866.96" + wire width 3 $and$libresoc.v:183866$11718_Y + attribute \src "libresoc.v:183871.17-183871.96" + wire width 3 $and$libresoc.v:183871$11723_Y + attribute \src "libresoc.v:183868.18-183868.93" + wire width 3 $not$libresoc.v:183868$11720_Y + attribute \src "libresoc.v:183870.17-183870.92" + wire width 3 $not$libresoc.v:183870$11722_Y + attribute \src "libresoc.v:183873.17-183873.92" + wire width 3 $not$libresoc.v:183873$11725_Y + attribute \src "libresoc.v:183867.18-183867.98" + wire width 3 $or$libresoc.v:183867$11719_Y + attribute \src "libresoc.v:183869.18-183869.99" + wire width 3 $or$libresoc.v:183869$11721_Y + attribute \src "libresoc.v:183872.17-183872.97" + wire width 3 $or$libresoc.v:183872$11724_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378626,11 +343606,11 @@ module \req_l$12 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:183783.7-183783.15" + attribute \src "libresoc.v:183831.7-183831.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -378647,7 +343627,7 @@ module \req_l$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183818$11922 + cell $and $and$libresoc.v:183866$11718 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378655,10 +343635,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183818$11922_Y + connect \Y $and$libresoc.v:183866$11718_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183823$11927 + cell $and $and$libresoc.v:183871$11723 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378666,34 +343646,34 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183823$11927_Y + connect \Y $and$libresoc.v:183871$11723_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183820$11924 + cell $not $not$libresoc.v:183868$11720 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:183820$11924_Y + connect \Y $not$libresoc.v:183868$11720_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183822$11926 + cell $not $not$libresoc.v:183870$11722 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183822$11926_Y + connect \Y $not$libresoc.v:183870$11722_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183825$11929 + cell $not $not$libresoc.v:183873$11725 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183825$11929_Y + connect \Y $not$libresoc.v:183873$11725_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183819$11923 + cell $or $or$libresoc.v:183867$11719 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378701,10 +343681,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183819$11923_Y + connect \Y $or$libresoc.v:183867$11719_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183821$11925 + cell $or $or$libresoc.v:183869$11721 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378712,10 +343692,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183821$11925_Y + connect \Y $or$libresoc.v:183869$11721_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183824$11928 + cell $or $or$libresoc.v:183872$11724 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378723,39 +343703,39 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183824$11928_Y + connect \Y $or$libresoc.v:183872$11724_Y end - attribute \src "libresoc.v:183783.7-183783.20" - process $proc$libresoc.v:183783$11934 + attribute \src "libresoc.v:183831.7-183831.20" + process $proc$libresoc.v:183831$11730 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183805.13-183805.25" - process $proc$libresoc.v:183805$11935 + attribute \src "libresoc.v:183853.13-183853.25" + process $proc$libresoc.v:183853$11731 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:183826.3-183827.27" - process $proc$libresoc.v:183826$11930 + attribute \src "libresoc.v:183874.3-183875.27" + process $proc$libresoc.v:183874$11726 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:183828.3-183836.6" - process $proc$libresoc.v:183828$11931 + attribute \src "libresoc.v:183876.3-183884.6" + process $proc$libresoc.v:183876$11727 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11932 $1\q_int$next[2:0]$11933 - attribute \src "libresoc.v:183829.5-183829.29" + assign $0\q_int$next[2:0]$11728 $1\q_int$next[2:0]$11729 + attribute \src "libresoc.v:183877.5-183877.29" switch \initial - attribute \src "libresoc.v:183829.9-183829.17" + attribute \src "libresoc.v:183877.9-183877.17" case 1'1 case end @@ -378764,56 +343744,56 @@ module \req_l$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11933 3'000 + assign $1\q_int$next[2:0]$11729 3'000 case - assign $1\q_int$next[2:0]$11933 \$5 + assign $1\q_int$next[2:0]$11729 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11932 + update \q_int$next $0\q_int$next[2:0]$11728 end - connect \$9 $and$libresoc.v:183818$11922_Y - connect \$11 $or$libresoc.v:183819$11923_Y - connect \$13 $not$libresoc.v:183820$11924_Y - connect \$15 $or$libresoc.v:183821$11925_Y - connect \$1 $not$libresoc.v:183822$11926_Y - connect \$3 $and$libresoc.v:183823$11927_Y - connect \$5 $or$libresoc.v:183824$11928_Y - connect \$7 $not$libresoc.v:183825$11929_Y + connect \$9 $and$libresoc.v:183866$11718_Y + connect \$11 $or$libresoc.v:183867$11719_Y + connect \$13 $not$libresoc.v:183868$11720_Y + connect \$15 $or$libresoc.v:183869$11721_Y + connect \$1 $not$libresoc.v:183870$11722_Y + connect \$3 $and$libresoc.v:183871$11723_Y + connect \$5 $or$libresoc.v:183872$11724_Y + connect \$7 $not$libresoc.v:183873$11725_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183844.1-183902.10" +attribute \src "libresoc.v:183892.1-183950.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" attribute \generator "nMigen" module \req_l$121 - attribute \src "libresoc.v:183845.7-183845.20" + attribute \src "libresoc.v:183893.7-183893.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183890.3-183898.6" - wire width 3 $0\q_int$next[2:0]$11946 - attribute \src "libresoc.v:183888.3-183889.27" + attribute \src "libresoc.v:183938.3-183946.6" + wire width 3 $0\q_int$next[2:0]$11742 + attribute \src "libresoc.v:183936.3-183937.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:183890.3-183898.6" - wire width 3 $1\q_int$next[2:0]$11947 - attribute \src "libresoc.v:183867.13-183867.25" + attribute \src "libresoc.v:183938.3-183946.6" + wire width 3 $1\q_int$next[2:0]$11743 + attribute \src "libresoc.v:183915.13-183915.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:183880.17-183880.96" - wire width 3 $and$libresoc.v:183880$11936_Y - attribute \src "libresoc.v:183885.17-183885.96" - wire width 3 $and$libresoc.v:183885$11941_Y - attribute \src "libresoc.v:183882.18-183882.93" - wire width 3 $not$libresoc.v:183882$11938_Y - attribute \src "libresoc.v:183884.17-183884.92" - wire width 3 $not$libresoc.v:183884$11940_Y - attribute \src "libresoc.v:183887.17-183887.92" - wire width 3 $not$libresoc.v:183887$11943_Y - attribute \src "libresoc.v:183881.18-183881.98" - wire width 3 $or$libresoc.v:183881$11937_Y - attribute \src "libresoc.v:183883.18-183883.99" - wire width 3 $or$libresoc.v:183883$11939_Y - attribute \src "libresoc.v:183886.17-183886.97" - wire width 3 $or$libresoc.v:183886$11942_Y + attribute \src "libresoc.v:183928.17-183928.96" + wire width 3 $and$libresoc.v:183928$11732_Y + attribute \src "libresoc.v:183933.17-183933.96" + wire width 3 $and$libresoc.v:183933$11737_Y + attribute \src "libresoc.v:183930.18-183930.93" + wire width 3 $not$libresoc.v:183930$11734_Y + attribute \src "libresoc.v:183932.17-183932.92" + wire width 3 $not$libresoc.v:183932$11736_Y + attribute \src "libresoc.v:183935.17-183935.92" + wire width 3 $not$libresoc.v:183935$11739_Y + attribute \src "libresoc.v:183929.18-183929.98" + wire width 3 $or$libresoc.v:183929$11733_Y + attribute \src "libresoc.v:183931.18-183931.99" + wire width 3 $or$libresoc.v:183931$11735_Y + attribute \src "libresoc.v:183934.17-183934.97" + wire width 3 $or$libresoc.v:183934$11738_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378830,11 +343810,11 @@ module \req_l$121 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:183845.7-183845.15" + attribute \src "libresoc.v:183893.7-183893.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -378851,7 +343831,7 @@ module \req_l$121 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183880$11936 + cell $and $and$libresoc.v:183928$11732 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378859,10 +343839,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183880$11936_Y + connect \Y $and$libresoc.v:183928$11732_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183885$11941 + cell $and $and$libresoc.v:183933$11737 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378870,34 +343850,34 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183885$11941_Y + connect \Y $and$libresoc.v:183933$11737_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183882$11938 + cell $not $not$libresoc.v:183930$11734 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:183882$11938_Y + connect \Y $not$libresoc.v:183930$11734_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183884$11940 + cell $not $not$libresoc.v:183932$11736 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183884$11940_Y + connect \Y $not$libresoc.v:183932$11736_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183887$11943 + cell $not $not$libresoc.v:183935$11739 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183887$11943_Y + connect \Y $not$libresoc.v:183935$11739_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183881$11937 + cell $or $or$libresoc.v:183929$11733 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378905,10 +343885,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183881$11937_Y + connect \Y $or$libresoc.v:183929$11733_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183883$11939 + cell $or $or$libresoc.v:183931$11735 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378916,10 +343896,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183883$11939_Y + connect \Y $or$libresoc.v:183931$11735_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183886$11942 + cell $or $or$libresoc.v:183934$11738 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378927,39 +343907,39 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183886$11942_Y + connect \Y $or$libresoc.v:183934$11738_Y end - attribute \src "libresoc.v:183845.7-183845.20" - process $proc$libresoc.v:183845$11948 + attribute \src "libresoc.v:183893.7-183893.20" + process $proc$libresoc.v:183893$11744 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183867.13-183867.25" - process $proc$libresoc.v:183867$11949 + attribute \src "libresoc.v:183915.13-183915.25" + process $proc$libresoc.v:183915$11745 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:183888.3-183889.27" - process $proc$libresoc.v:183888$11944 + attribute \src "libresoc.v:183936.3-183937.27" + process $proc$libresoc.v:183936$11740 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:183890.3-183898.6" - process $proc$libresoc.v:183890$11945 + attribute \src "libresoc.v:183938.3-183946.6" + process $proc$libresoc.v:183938$11741 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11946 $1\q_int$next[2:0]$11947 - attribute \src "libresoc.v:183891.5-183891.29" + assign $0\q_int$next[2:0]$11742 $1\q_int$next[2:0]$11743 + attribute \src "libresoc.v:183939.5-183939.29" switch \initial - attribute \src "libresoc.v:183891.9-183891.17" + attribute \src "libresoc.v:183939.9-183939.17" case 1'1 case end @@ -378968,56 +343948,56 @@ module \req_l$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11947 3'000 + assign $1\q_int$next[2:0]$11743 3'000 case - assign $1\q_int$next[2:0]$11947 \$5 + assign $1\q_int$next[2:0]$11743 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11946 + update \q_int$next $0\q_int$next[2:0]$11742 end - connect \$9 $and$libresoc.v:183880$11936_Y - connect \$11 $or$libresoc.v:183881$11937_Y - connect \$13 $not$libresoc.v:183882$11938_Y - connect \$15 $or$libresoc.v:183883$11939_Y - connect \$1 $not$libresoc.v:183884$11940_Y - connect \$3 $and$libresoc.v:183885$11941_Y - connect \$5 $or$libresoc.v:183886$11942_Y - connect \$7 $not$libresoc.v:183887$11943_Y + connect \$9 $and$libresoc.v:183928$11732_Y + connect \$11 $or$libresoc.v:183929$11733_Y + connect \$13 $not$libresoc.v:183930$11734_Y + connect \$15 $or$libresoc.v:183931$11735_Y + connect \$1 $not$libresoc.v:183932$11736_Y + connect \$3 $and$libresoc.v:183933$11737_Y + connect \$5 $or$libresoc.v:183934$11738_Y + connect \$7 $not$libresoc.v:183935$11739_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183906.1-183964.10" +attribute \src "libresoc.v:183954.1-184012.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" attribute \generator "nMigen" module \req_l$25 - attribute \src "libresoc.v:183907.7-183907.20" + attribute \src "libresoc.v:183955.7-183955.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183952.3-183960.6" - wire width 3 $0\q_int$next[2:0]$11960 - attribute \src "libresoc.v:183950.3-183951.27" + attribute \src "libresoc.v:184000.3-184008.6" + wire width 3 $0\q_int$next[2:0]$11756 + attribute \src "libresoc.v:183998.3-183999.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:183952.3-183960.6" - wire width 3 $1\q_int$next[2:0]$11961 - attribute \src "libresoc.v:183929.13-183929.25" + attribute \src "libresoc.v:184000.3-184008.6" + wire width 3 $1\q_int$next[2:0]$11757 + attribute \src "libresoc.v:183977.13-183977.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:183942.17-183942.96" - wire width 3 $and$libresoc.v:183942$11950_Y - attribute \src "libresoc.v:183947.17-183947.96" - wire width 3 $and$libresoc.v:183947$11955_Y - attribute \src "libresoc.v:183944.18-183944.93" - wire width 3 $not$libresoc.v:183944$11952_Y - attribute \src "libresoc.v:183946.17-183946.92" - wire width 3 $not$libresoc.v:183946$11954_Y - attribute \src "libresoc.v:183949.17-183949.92" - wire width 3 $not$libresoc.v:183949$11957_Y - attribute \src "libresoc.v:183943.18-183943.98" - wire width 3 $or$libresoc.v:183943$11951_Y - attribute \src "libresoc.v:183945.18-183945.99" - wire width 3 $or$libresoc.v:183945$11953_Y - attribute \src "libresoc.v:183948.17-183948.97" - wire width 3 $or$libresoc.v:183948$11956_Y + attribute \src "libresoc.v:183990.17-183990.96" + wire width 3 $and$libresoc.v:183990$11746_Y + attribute \src "libresoc.v:183995.17-183995.96" + wire width 3 $and$libresoc.v:183995$11751_Y + attribute \src "libresoc.v:183992.18-183992.93" + wire width 3 $not$libresoc.v:183992$11748_Y + attribute \src "libresoc.v:183994.17-183994.92" + wire width 3 $not$libresoc.v:183994$11750_Y + attribute \src "libresoc.v:183997.17-183997.92" + wire width 3 $not$libresoc.v:183997$11753_Y + attribute \src "libresoc.v:183991.18-183991.98" + wire width 3 $or$libresoc.v:183991$11747_Y + attribute \src "libresoc.v:183993.18-183993.99" + wire width 3 $or$libresoc.v:183993$11749_Y + attribute \src "libresoc.v:183996.17-183996.97" + wire width 3 $or$libresoc.v:183996$11752_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379034,11 +344014,11 @@ module \req_l$25 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:183907.7-183907.15" + attribute \src "libresoc.v:183955.7-183955.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -379055,7 +344035,7 @@ module \req_l$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183942$11950 + cell $and $and$libresoc.v:183990$11746 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -379063,10 +344043,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183942$11950_Y + connect \Y $and$libresoc.v:183990$11746_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183947$11955 + cell $and $and$libresoc.v:183995$11751 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -379074,34 +344054,34 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183947$11955_Y + connect \Y $and$libresoc.v:183995$11751_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183944$11952 + cell $not $not$libresoc.v:183992$11748 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:183944$11952_Y + connect \Y $not$libresoc.v:183992$11748_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183946$11954 + cell $not $not$libresoc.v:183994$11750 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183946$11954_Y + connect \Y $not$libresoc.v:183994$11750_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183949$11957 + cell $not $not$libresoc.v:183997$11753 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183949$11957_Y + connect \Y $not$libresoc.v:183997$11753_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183943$11951 + cell $or $or$libresoc.v:183991$11747 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -379109,10 +344089,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183943$11951_Y + connect \Y $or$libresoc.v:183991$11747_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183945$11953 + cell $or $or$libresoc.v:183993$11749 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -379120,10 +344100,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183945$11953_Y + connect \Y $or$libresoc.v:183993$11749_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183948$11956 + cell $or $or$libresoc.v:183996$11752 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -379131,39 +344111,39 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183948$11956_Y + connect \Y $or$libresoc.v:183996$11752_Y end - attribute \src "libresoc.v:183907.7-183907.20" - process $proc$libresoc.v:183907$11962 + attribute \src "libresoc.v:183955.7-183955.20" + process $proc$libresoc.v:183955$11758 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183929.13-183929.25" - process $proc$libresoc.v:183929$11963 + attribute \src "libresoc.v:183977.13-183977.25" + process $proc$libresoc.v:183977$11759 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:183950.3-183951.27" - process $proc$libresoc.v:183950$11958 + attribute \src "libresoc.v:183998.3-183999.27" + process $proc$libresoc.v:183998$11754 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:183952.3-183960.6" - process $proc$libresoc.v:183952$11959 + attribute \src "libresoc.v:184000.3-184008.6" + process $proc$libresoc.v:184000$11755 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11960 $1\q_int$next[2:0]$11961 - attribute \src "libresoc.v:183953.5-183953.29" + assign $0\q_int$next[2:0]$11756 $1\q_int$next[2:0]$11757 + attribute \src "libresoc.v:184001.5-184001.29" switch \initial - attribute \src "libresoc.v:183953.9-183953.17" + attribute \src "libresoc.v:184001.9-184001.17" case 1'1 case end @@ -379172,56 +344152,56 @@ module \req_l$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11961 3'000 + assign $1\q_int$next[2:0]$11757 3'000 case - assign $1\q_int$next[2:0]$11961 \$5 + assign $1\q_int$next[2:0]$11757 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11960 + update \q_int$next $0\q_int$next[2:0]$11756 end - connect \$9 $and$libresoc.v:183942$11950_Y - connect \$11 $or$libresoc.v:183943$11951_Y - connect \$13 $not$libresoc.v:183944$11952_Y - connect \$15 $or$libresoc.v:183945$11953_Y - connect \$1 $not$libresoc.v:183946$11954_Y - connect \$3 $and$libresoc.v:183947$11955_Y - connect \$5 $or$libresoc.v:183948$11956_Y - connect \$7 $not$libresoc.v:183949$11957_Y + connect \$9 $and$libresoc.v:183990$11746_Y + connect \$11 $or$libresoc.v:183991$11747_Y + connect \$13 $not$libresoc.v:183992$11748_Y + connect \$15 $or$libresoc.v:183993$11749_Y + connect \$1 $not$libresoc.v:183994$11750_Y + connect \$3 $and$libresoc.v:183995$11751_Y + connect \$5 $or$libresoc.v:183996$11752_Y + connect \$7 $not$libresoc.v:183997$11753_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183968.1-184026.10" +attribute \src "libresoc.v:184016.1-184074.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.req_l" attribute \generator "nMigen" module \req_l$41 - attribute \src "libresoc.v:183969.7-183969.20" + attribute \src "libresoc.v:184017.7-184017.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184014.3-184022.6" - wire width 5 $0\q_int$next[4:0]$11974 - attribute \src "libresoc.v:184012.3-184013.27" + attribute \src "libresoc.v:184062.3-184070.6" + wire width 5 $0\q_int$next[4:0]$11770 + attribute \src "libresoc.v:184060.3-184061.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:184014.3-184022.6" - wire width 5 $1\q_int$next[4:0]$11975 - attribute \src "libresoc.v:183991.13-183991.26" + attribute \src "libresoc.v:184062.3-184070.6" + wire width 5 $1\q_int$next[4:0]$11771 + attribute \src "libresoc.v:184039.13-184039.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:184004.17-184004.96" - wire width 5 $and$libresoc.v:184004$11964_Y - attribute \src "libresoc.v:184009.17-184009.96" - wire width 5 $and$libresoc.v:184009$11969_Y - attribute \src "libresoc.v:184006.18-184006.93" - wire width 5 $not$libresoc.v:184006$11966_Y - attribute \src "libresoc.v:184008.17-184008.92" - wire width 5 $not$libresoc.v:184008$11968_Y - attribute \src "libresoc.v:184011.17-184011.92" - wire width 5 $not$libresoc.v:184011$11971_Y - attribute \src "libresoc.v:184005.18-184005.98" - wire width 5 $or$libresoc.v:184005$11965_Y - attribute \src "libresoc.v:184007.18-184007.99" - wire width 5 $or$libresoc.v:184007$11967_Y - attribute \src "libresoc.v:184010.17-184010.97" - wire width 5 $or$libresoc.v:184010$11970_Y + attribute \src "libresoc.v:184052.17-184052.96" + wire width 5 $and$libresoc.v:184052$11760_Y + attribute \src "libresoc.v:184057.17-184057.96" + wire width 5 $and$libresoc.v:184057$11765_Y + attribute \src "libresoc.v:184054.18-184054.93" + wire width 5 $not$libresoc.v:184054$11762_Y + attribute \src "libresoc.v:184056.17-184056.92" + wire width 5 $not$libresoc.v:184056$11764_Y + attribute \src "libresoc.v:184059.17-184059.92" + wire width 5 $not$libresoc.v:184059$11767_Y + attribute \src "libresoc.v:184053.18-184053.98" + wire width 5 $or$libresoc.v:184053$11761_Y + attribute \src "libresoc.v:184055.18-184055.99" + wire width 5 $or$libresoc.v:184055$11763_Y + attribute \src "libresoc.v:184058.17-184058.97" + wire width 5 $or$libresoc.v:184058$11766_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379238,11 +344218,11 @@ module \req_l$41 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:183969.7-183969.15" + attribute \src "libresoc.v:184017.7-184017.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -379259,7 +344239,7 @@ module \req_l$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184004$11964 + cell $and $and$libresoc.v:184052$11760 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -379267,10 +344247,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184004$11964_Y + connect \Y $and$libresoc.v:184052$11760_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184009$11969 + cell $and $and$libresoc.v:184057$11765 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -379278,34 +344258,34 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184009$11969_Y + connect \Y $and$libresoc.v:184057$11765_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184006$11966 + cell $not $not$libresoc.v:184054$11762 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:184006$11966_Y + connect \Y $not$libresoc.v:184054$11762_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184008$11968 + cell $not $not$libresoc.v:184056$11764 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:184008$11968_Y + connect \Y $not$libresoc.v:184056$11764_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184011$11971 + cell $not $not$libresoc.v:184059$11767 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:184011$11971_Y + connect \Y $not$libresoc.v:184059$11767_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184005$11965 + cell $or $or$libresoc.v:184053$11761 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -379313,10 +344293,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184005$11965_Y + connect \Y $or$libresoc.v:184053$11761_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184007$11967 + cell $or $or$libresoc.v:184055$11763 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -379324,10 +344304,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184007$11967_Y + connect \Y $or$libresoc.v:184055$11763_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184010$11970 + cell $or $or$libresoc.v:184058$11766 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -379335,39 +344315,39 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184010$11970_Y + connect \Y $or$libresoc.v:184058$11766_Y end - attribute \src "libresoc.v:183969.7-183969.20" - process $proc$libresoc.v:183969$11976 + attribute \src "libresoc.v:184017.7-184017.20" + process $proc$libresoc.v:184017$11772 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183991.13-183991.26" - process $proc$libresoc.v:183991$11977 + attribute \src "libresoc.v:184039.13-184039.26" + process $proc$libresoc.v:184039$11773 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:184012.3-184013.27" - process $proc$libresoc.v:184012$11972 + attribute \src "libresoc.v:184060.3-184061.27" + process $proc$libresoc.v:184060$11768 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:184014.3-184022.6" - process $proc$libresoc.v:184014$11973 + attribute \src "libresoc.v:184062.3-184070.6" + process $proc$libresoc.v:184062$11769 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11974 $1\q_int$next[4:0]$11975 - attribute \src "libresoc.v:184015.5-184015.29" + assign $0\q_int$next[4:0]$11770 $1\q_int$next[4:0]$11771 + attribute \src "libresoc.v:184063.5-184063.29" switch \initial - attribute \src "libresoc.v:184015.9-184015.17" + attribute \src "libresoc.v:184063.9-184063.17" case 1'1 case end @@ -379376,56 +344356,56 @@ module \req_l$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11975 5'00000 + assign $1\q_int$next[4:0]$11771 5'00000 case - assign $1\q_int$next[4:0]$11975 \$5 + assign $1\q_int$next[4:0]$11771 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11974 + update \q_int$next $0\q_int$next[4:0]$11770 end - connect \$9 $and$libresoc.v:184004$11964_Y - connect \$11 $or$libresoc.v:184005$11965_Y - connect \$13 $not$libresoc.v:184006$11966_Y - connect \$15 $or$libresoc.v:184007$11967_Y - connect \$1 $not$libresoc.v:184008$11968_Y - connect \$3 $and$libresoc.v:184009$11969_Y - connect \$5 $or$libresoc.v:184010$11970_Y - connect \$7 $not$libresoc.v:184011$11971_Y + connect \$9 $and$libresoc.v:184052$11760_Y + connect \$11 $or$libresoc.v:184053$11761_Y + connect \$13 $not$libresoc.v:184054$11762_Y + connect \$15 $or$libresoc.v:184055$11763_Y + connect \$1 $not$libresoc.v:184056$11764_Y + connect \$3 $and$libresoc.v:184057$11765_Y + connect \$5 $or$libresoc.v:184058$11766_Y + connect \$7 $not$libresoc.v:184059$11767_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184030.1-184088.10" +attribute \src "libresoc.v:184078.1-184136.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l" attribute \generator "nMigen" module \req_l$57 - attribute \src "libresoc.v:184031.7-184031.20" + attribute \src "libresoc.v:184079.7-184079.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184076.3-184084.6" - wire width 2 $0\q_int$next[1:0]$11988 - attribute \src "libresoc.v:184074.3-184075.27" + attribute \src "libresoc.v:184124.3-184132.6" + wire width 2 $0\q_int$next[1:0]$11784 + attribute \src "libresoc.v:184122.3-184123.27" wire width 2 $0\q_int[1:0] - attribute \src "libresoc.v:184076.3-184084.6" - wire width 2 $1\q_int$next[1:0]$11989 - attribute \src "libresoc.v:184053.13-184053.25" + attribute \src "libresoc.v:184124.3-184132.6" + wire width 2 $1\q_int$next[1:0]$11785 + attribute \src "libresoc.v:184101.13-184101.25" wire width 2 $1\q_int[1:0] - attribute \src "libresoc.v:184066.17-184066.96" - wire width 2 $and$libresoc.v:184066$11978_Y - attribute \src "libresoc.v:184071.17-184071.96" - wire width 2 $and$libresoc.v:184071$11983_Y - attribute \src "libresoc.v:184068.18-184068.93" - wire width 2 $not$libresoc.v:184068$11980_Y - attribute \src "libresoc.v:184070.17-184070.92" - wire width 2 $not$libresoc.v:184070$11982_Y - attribute \src "libresoc.v:184073.17-184073.92" - wire width 2 $not$libresoc.v:184073$11985_Y - attribute \src "libresoc.v:184067.18-184067.98" - wire width 2 $or$libresoc.v:184067$11979_Y - attribute \src "libresoc.v:184069.18-184069.99" - wire width 2 $or$libresoc.v:184069$11981_Y - attribute \src "libresoc.v:184072.17-184072.97" - wire width 2 $or$libresoc.v:184072$11984_Y + attribute \src "libresoc.v:184114.17-184114.96" + wire width 2 $and$libresoc.v:184114$11774_Y + attribute \src "libresoc.v:184119.17-184119.96" + wire width 2 $and$libresoc.v:184119$11779_Y + attribute \src "libresoc.v:184116.18-184116.93" + wire width 2 $not$libresoc.v:184116$11776_Y + attribute \src "libresoc.v:184118.17-184118.92" + wire width 2 $not$libresoc.v:184118$11778_Y + attribute \src "libresoc.v:184121.17-184121.92" + wire width 2 $not$libresoc.v:184121$11781_Y + attribute \src "libresoc.v:184115.18-184115.98" + wire width 2 $or$libresoc.v:184115$11775_Y + attribute \src "libresoc.v:184117.18-184117.99" + wire width 2 $or$libresoc.v:184117$11777_Y + attribute \src "libresoc.v:184120.17-184120.97" + wire width 2 $or$libresoc.v:184120$11780_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379442,11 +344422,11 @@ module \req_l$57 wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:184031.7-184031.15" + attribute \src "libresoc.v:184079.7-184079.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 2 \q_int @@ -379463,7 +344443,7 @@ module \req_l$57 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 2 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184066$11978 + cell $and $and$libresoc.v:184114$11774 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -379471,10 +344451,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184066$11978_Y + connect \Y $and$libresoc.v:184114$11774_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184071$11983 + cell $and $and$libresoc.v:184119$11779 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -379482,34 +344462,34 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184071$11983_Y + connect \Y $and$libresoc.v:184119$11779_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184068$11980 + cell $not $not$libresoc.v:184116$11776 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \q_req - connect \Y $not$libresoc.v:184068$11980_Y + connect \Y $not$libresoc.v:184116$11776_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184070$11982 + cell $not $not$libresoc.v:184118$11778 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:184070$11982_Y + connect \Y $not$libresoc.v:184118$11778_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184073$11985 + cell $not $not$libresoc.v:184121$11781 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:184073$11985_Y + connect \Y $not$libresoc.v:184121$11781_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184067$11979 + cell $or $or$libresoc.v:184115$11775 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -379517,10 +344497,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184067$11979_Y + connect \Y $or$libresoc.v:184115$11775_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184069$11981 + cell $or $or$libresoc.v:184117$11777 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -379528,10 +344508,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184069$11981_Y + connect \Y $or$libresoc.v:184117$11777_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184072$11984 + cell $or $or$libresoc.v:184120$11780 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -379539,39 +344519,39 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184072$11984_Y + connect \Y $or$libresoc.v:184120$11780_Y end - attribute \src "libresoc.v:184031.7-184031.20" - process $proc$libresoc.v:184031$11990 + attribute \src "libresoc.v:184079.7-184079.20" + process $proc$libresoc.v:184079$11786 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184053.13-184053.25" - process $proc$libresoc.v:184053$11991 + attribute \src "libresoc.v:184101.13-184101.25" + process $proc$libresoc.v:184101$11787 assign { } { } assign $1\q_int[1:0] 2'00 sync always sync init update \q_int $1\q_int[1:0] end - attribute \src "libresoc.v:184074.3-184075.27" - process $proc$libresoc.v:184074$11986 + attribute \src "libresoc.v:184122.3-184123.27" + process $proc$libresoc.v:184122$11782 assign { } { } assign $0\q_int[1:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[1:0] end - attribute \src "libresoc.v:184076.3-184084.6" - process $proc$libresoc.v:184076$11987 + attribute \src "libresoc.v:184124.3-184132.6" + process $proc$libresoc.v:184124$11783 assign { } { } assign { } { } - assign $0\q_int$next[1:0]$11988 $1\q_int$next[1:0]$11989 - attribute \src "libresoc.v:184077.5-184077.29" + assign $0\q_int$next[1:0]$11784 $1\q_int$next[1:0]$11785 + attribute \src "libresoc.v:184125.5-184125.29" switch \initial - attribute \src "libresoc.v:184077.9-184077.17" + attribute \src "libresoc.v:184125.9-184125.17" case 1'1 case end @@ -379580,56 +344560,56 @@ module \req_l$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[1:0]$11989 2'00 + assign $1\q_int$next[1:0]$11785 2'00 case - assign $1\q_int$next[1:0]$11989 \$5 + assign $1\q_int$next[1:0]$11785 \$5 end sync always - update \q_int$next $0\q_int$next[1:0]$11988 + update \q_int$next $0\q_int$next[1:0]$11784 end - connect \$9 $and$libresoc.v:184066$11978_Y - connect \$11 $or$libresoc.v:184067$11979_Y - connect \$13 $not$libresoc.v:184068$11980_Y - connect \$15 $or$libresoc.v:184069$11981_Y - connect \$1 $not$libresoc.v:184070$11982_Y - connect \$3 $and$libresoc.v:184071$11983_Y - connect \$5 $or$libresoc.v:184072$11984_Y - connect \$7 $not$libresoc.v:184073$11985_Y + connect \$9 $and$libresoc.v:184114$11774_Y + connect \$11 $or$libresoc.v:184115$11775_Y + connect \$13 $not$libresoc.v:184116$11776_Y + connect \$15 $or$libresoc.v:184117$11777_Y + connect \$1 $not$libresoc.v:184118$11778_Y + connect \$3 $and$libresoc.v:184119$11779_Y + connect \$5 $or$libresoc.v:184120$11780_Y + connect \$7 $not$libresoc.v:184121$11781_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184092.1-184150.10" +attribute \src "libresoc.v:184140.1-184198.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l" attribute \generator "nMigen" module \req_l$69 - attribute \src "libresoc.v:184093.7-184093.20" + attribute \src "libresoc.v:184141.7-184141.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184138.3-184146.6" - wire width 6 $0\q_int$next[5:0]$12002 - attribute \src "libresoc.v:184136.3-184137.27" + attribute \src "libresoc.v:184186.3-184194.6" + wire width 6 $0\q_int$next[5:0]$11798 + attribute \src "libresoc.v:184184.3-184185.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:184138.3-184146.6" - wire width 6 $1\q_int$next[5:0]$12003 - attribute \src "libresoc.v:184115.13-184115.26" + attribute \src "libresoc.v:184186.3-184194.6" + wire width 6 $1\q_int$next[5:0]$11799 + attribute \src "libresoc.v:184163.13-184163.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:184128.17-184128.96" - wire width 6 $and$libresoc.v:184128$11992_Y - attribute \src "libresoc.v:184133.17-184133.96" - wire width 6 $and$libresoc.v:184133$11997_Y - attribute \src "libresoc.v:184130.18-184130.93" - wire width 6 $not$libresoc.v:184130$11994_Y - attribute \src "libresoc.v:184132.17-184132.92" - wire width 6 $not$libresoc.v:184132$11996_Y - attribute \src "libresoc.v:184135.17-184135.92" - wire width 6 $not$libresoc.v:184135$11999_Y - attribute \src "libresoc.v:184129.18-184129.98" - wire width 6 $or$libresoc.v:184129$11993_Y - attribute \src "libresoc.v:184131.18-184131.99" - wire width 6 $or$libresoc.v:184131$11995_Y - attribute \src "libresoc.v:184134.17-184134.97" - wire width 6 $or$libresoc.v:184134$11998_Y + attribute \src "libresoc.v:184176.17-184176.96" + wire width 6 $and$libresoc.v:184176$11788_Y + attribute \src "libresoc.v:184181.17-184181.96" + wire width 6 $and$libresoc.v:184181$11793_Y + attribute \src "libresoc.v:184178.18-184178.93" + wire width 6 $not$libresoc.v:184178$11790_Y + attribute \src "libresoc.v:184180.17-184180.92" + wire width 6 $not$libresoc.v:184180$11792_Y + attribute \src "libresoc.v:184183.17-184183.92" + wire width 6 $not$libresoc.v:184183$11795_Y + attribute \src "libresoc.v:184177.18-184177.98" + wire width 6 $or$libresoc.v:184177$11789_Y + attribute \src "libresoc.v:184179.18-184179.99" + wire width 6 $or$libresoc.v:184179$11791_Y + attribute \src "libresoc.v:184182.17-184182.97" + wire width 6 $or$libresoc.v:184182$11794_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379646,11 +344626,11 @@ module \req_l$69 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:184093.7-184093.15" + attribute \src "libresoc.v:184141.7-184141.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -379667,7 +344647,7 @@ module \req_l$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184128$11992 + cell $and $and$libresoc.v:184176$11788 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -379675,10 +344655,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184128$11992_Y + connect \Y $and$libresoc.v:184176$11788_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184133$11997 + cell $and $and$libresoc.v:184181$11793 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -379686,34 +344666,34 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184133$11997_Y + connect \Y $and$libresoc.v:184181$11793_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184130$11994 + cell $not $not$libresoc.v:184178$11790 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_req - connect \Y $not$libresoc.v:184130$11994_Y + connect \Y $not$libresoc.v:184178$11790_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184132$11996 + cell $not $not$libresoc.v:184180$11792 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:184132$11996_Y + connect \Y $not$libresoc.v:184180$11792_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184135$11999 + cell $not $not$libresoc.v:184183$11795 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:184135$11999_Y + connect \Y $not$libresoc.v:184183$11795_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184129$11993 + cell $or $or$libresoc.v:184177$11789 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -379721,10 +344701,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184129$11993_Y + connect \Y $or$libresoc.v:184177$11789_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184131$11995 + cell $or $or$libresoc.v:184179$11791 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -379732,10 +344712,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184131$11995_Y + connect \Y $or$libresoc.v:184179$11791_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184134$11998 + cell $or $or$libresoc.v:184182$11794 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -379743,39 +344723,39 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184134$11998_Y + connect \Y $or$libresoc.v:184182$11794_Y end - attribute \src "libresoc.v:184093.7-184093.20" - process $proc$libresoc.v:184093$12004 + attribute \src "libresoc.v:184141.7-184141.20" + process $proc$libresoc.v:184141$11800 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184115.13-184115.26" - process $proc$libresoc.v:184115$12005 + attribute \src "libresoc.v:184163.13-184163.26" + process $proc$libresoc.v:184163$11801 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:184136.3-184137.27" - process $proc$libresoc.v:184136$12000 + attribute \src "libresoc.v:184184.3-184185.27" + process $proc$libresoc.v:184184$11796 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:184138.3-184146.6" - process $proc$libresoc.v:184138$12001 + attribute \src "libresoc.v:184186.3-184194.6" + process $proc$libresoc.v:184186$11797 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$12002 $1\q_int$next[5:0]$12003 - attribute \src "libresoc.v:184139.5-184139.29" + assign $0\q_int$next[5:0]$11798 $1\q_int$next[5:0]$11799 + attribute \src "libresoc.v:184187.5-184187.29" switch \initial - attribute \src "libresoc.v:184139.9-184139.17" + attribute \src "libresoc.v:184187.9-184187.17" case 1'1 case end @@ -379784,56 +344764,56 @@ module \req_l$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$12003 6'000000 + assign $1\q_int$next[5:0]$11799 6'000000 case - assign $1\q_int$next[5:0]$12003 \$5 + assign $1\q_int$next[5:0]$11799 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$12002 + update \q_int$next $0\q_int$next[5:0]$11798 end - connect \$9 $and$libresoc.v:184128$11992_Y - connect \$11 $or$libresoc.v:184129$11993_Y - connect \$13 $not$libresoc.v:184130$11994_Y - connect \$15 $or$libresoc.v:184131$11995_Y - connect \$1 $not$libresoc.v:184132$11996_Y - connect \$3 $and$libresoc.v:184133$11997_Y - connect \$5 $or$libresoc.v:184134$11998_Y - connect \$7 $not$libresoc.v:184135$11999_Y + connect \$9 $and$libresoc.v:184176$11788_Y + connect \$11 $or$libresoc.v:184177$11789_Y + connect \$13 $not$libresoc.v:184178$11790_Y + connect \$15 $or$libresoc.v:184179$11791_Y + connect \$1 $not$libresoc.v:184180$11792_Y + connect \$3 $and$libresoc.v:184181$11793_Y + connect \$5 $or$libresoc.v:184182$11794_Y + connect \$7 $not$libresoc.v:184183$11795_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184154.1-184212.10" +attribute \src "libresoc.v:184202.1-184260.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l" attribute \generator "nMigen" module \req_l$86 - attribute \src "libresoc.v:184155.7-184155.20" + attribute \src "libresoc.v:184203.7-184203.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184200.3-184208.6" - wire width 4 $0\q_int$next[3:0]$12016 - attribute \src "libresoc.v:184198.3-184199.27" + attribute \src "libresoc.v:184248.3-184256.6" + wire width 4 $0\q_int$next[3:0]$11812 + attribute \src "libresoc.v:184246.3-184247.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:184200.3-184208.6" - wire width 4 $1\q_int$next[3:0]$12017 - attribute \src "libresoc.v:184177.13-184177.25" + attribute \src "libresoc.v:184248.3-184256.6" + wire width 4 $1\q_int$next[3:0]$11813 + attribute \src "libresoc.v:184225.13-184225.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:184190.17-184190.96" - wire width 4 $and$libresoc.v:184190$12006_Y - attribute \src "libresoc.v:184195.17-184195.96" - wire width 4 $and$libresoc.v:184195$12011_Y - attribute \src "libresoc.v:184192.18-184192.93" - wire width 4 $not$libresoc.v:184192$12008_Y - attribute \src "libresoc.v:184194.17-184194.92" - wire width 4 $not$libresoc.v:184194$12010_Y - attribute \src "libresoc.v:184197.17-184197.92" - wire width 4 $not$libresoc.v:184197$12013_Y - attribute \src "libresoc.v:184191.18-184191.98" - wire width 4 $or$libresoc.v:184191$12007_Y - attribute \src "libresoc.v:184193.18-184193.99" - wire width 4 $or$libresoc.v:184193$12009_Y - attribute \src "libresoc.v:184196.17-184196.97" - wire width 4 $or$libresoc.v:184196$12012_Y + attribute \src "libresoc.v:184238.17-184238.96" + wire width 4 $and$libresoc.v:184238$11802_Y + attribute \src "libresoc.v:184243.17-184243.96" + wire width 4 $and$libresoc.v:184243$11807_Y + attribute \src "libresoc.v:184240.18-184240.93" + wire width 4 $not$libresoc.v:184240$11804_Y + attribute \src "libresoc.v:184242.17-184242.92" + wire width 4 $not$libresoc.v:184242$11806_Y + attribute \src "libresoc.v:184245.17-184245.92" + wire width 4 $not$libresoc.v:184245$11809_Y + attribute \src "libresoc.v:184239.18-184239.98" + wire width 4 $or$libresoc.v:184239$11803_Y + attribute \src "libresoc.v:184241.18-184241.99" + wire width 4 $or$libresoc.v:184241$11805_Y + attribute \src "libresoc.v:184244.17-184244.97" + wire width 4 $or$libresoc.v:184244$11808_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379850,11 +344830,11 @@ module \req_l$86 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:184155.7-184155.15" + attribute \src "libresoc.v:184203.7-184203.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -379871,7 +344851,7 @@ module \req_l$86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184190$12006 + cell $and $and$libresoc.v:184238$11802 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -379879,10 +344859,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184190$12006_Y + connect \Y $and$libresoc.v:184238$11802_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184195$12011 + cell $and $and$libresoc.v:184243$11807 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -379890,34 +344870,34 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184195$12011_Y + connect \Y $and$libresoc.v:184243$11807_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184192$12008 + cell $not $not$libresoc.v:184240$11804 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:184192$12008_Y + connect \Y $not$libresoc.v:184240$11804_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184194$12010 + cell $not $not$libresoc.v:184242$11806 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:184194$12010_Y + connect \Y $not$libresoc.v:184242$11806_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184197$12013 + cell $not $not$libresoc.v:184245$11809 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:184197$12013_Y + connect \Y $not$libresoc.v:184245$11809_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184191$12007 + cell $or $or$libresoc.v:184239$11803 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -379925,10 +344905,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184191$12007_Y + connect \Y $or$libresoc.v:184239$11803_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184193$12009 + cell $or $or$libresoc.v:184241$11805 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -379936,10 +344916,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184193$12009_Y + connect \Y $or$libresoc.v:184241$11805_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184196$12012 + cell $or $or$libresoc.v:184244$11808 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -379947,39 +344927,39 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184196$12012_Y + connect \Y $or$libresoc.v:184244$11808_Y end - attribute \src "libresoc.v:184155.7-184155.20" - process $proc$libresoc.v:184155$12018 + attribute \src "libresoc.v:184203.7-184203.20" + process $proc$libresoc.v:184203$11814 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184177.13-184177.25" - process $proc$libresoc.v:184177$12019 + attribute \src "libresoc.v:184225.13-184225.25" + process $proc$libresoc.v:184225$11815 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:184198.3-184199.27" - process $proc$libresoc.v:184198$12014 + attribute \src "libresoc.v:184246.3-184247.27" + process $proc$libresoc.v:184246$11810 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:184200.3-184208.6" - process $proc$libresoc.v:184200$12015 + attribute \src "libresoc.v:184248.3-184256.6" + process $proc$libresoc.v:184248$11811 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$12016 $1\q_int$next[3:0]$12017 - attribute \src "libresoc.v:184201.5-184201.29" + assign $0\q_int$next[3:0]$11812 $1\q_int$next[3:0]$11813 + attribute \src "libresoc.v:184249.5-184249.29" switch \initial - attribute \src "libresoc.v:184201.9-184201.17" + attribute \src "libresoc.v:184249.9-184249.17" case 1'1 case end @@ -379988,50 +344968,50 @@ module \req_l$86 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$12017 4'0000 + assign $1\q_int$next[3:0]$11813 4'0000 case - assign $1\q_int$next[3:0]$12017 \$5 + assign $1\q_int$next[3:0]$11813 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$12016 + update \q_int$next $0\q_int$next[3:0]$11812 end - connect \$9 $and$libresoc.v:184190$12006_Y - connect \$11 $or$libresoc.v:184191$12007_Y - connect \$13 $not$libresoc.v:184192$12008_Y - connect \$15 $or$libresoc.v:184193$12009_Y - connect \$1 $not$libresoc.v:184194$12010_Y - connect \$3 $and$libresoc.v:184195$12011_Y - connect \$5 $or$libresoc.v:184196$12012_Y - connect \$7 $not$libresoc.v:184197$12013_Y + connect \$9 $and$libresoc.v:184238$11802_Y + connect \$11 $or$libresoc.v:184239$11803_Y + connect \$13 $not$libresoc.v:184240$11804_Y + connect \$15 $or$libresoc.v:184241$11805_Y + connect \$1 $not$libresoc.v:184242$11806_Y + connect \$3 $and$libresoc.v:184243$11807_Y + connect \$5 $or$libresoc.v:184244$11808_Y + connect \$7 $not$libresoc.v:184245$11809_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184216.1-184265.10" +attribute \src "libresoc.v:184264.1-184313.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" attribute \generator "nMigen" module \reset_l - attribute \src "libresoc.v:184217.7-184217.20" + attribute \src "libresoc.v:184265.7-184265.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184253.3-184261.6" - wire $0\q_int$next[0:0]$12027 - attribute \src "libresoc.v:184251.3-184252.27" + attribute \src "libresoc.v:184301.3-184309.6" + wire $0\q_int$next[0:0]$11823 + attribute \src "libresoc.v:184299.3-184300.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184253.3-184261.6" - wire $1\q_int$next[0:0]$12028 - attribute \src "libresoc.v:184233.7-184233.19" + attribute \src "libresoc.v:184301.3-184309.6" + wire $1\q_int$next[0:0]$11824 + attribute \src "libresoc.v:184281.7-184281.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184248.17-184248.96" - wire $and$libresoc.v:184248$12022_Y - attribute \src "libresoc.v:184247.17-184247.94" - wire $not$libresoc.v:184247$12021_Y - attribute \src "libresoc.v:184250.17-184250.94" - wire $not$libresoc.v:184250$12024_Y - attribute \src "libresoc.v:184246.17-184246.100" - wire $or$libresoc.v:184246$12020_Y - attribute \src "libresoc.v:184249.17-184249.99" - wire $or$libresoc.v:184249$12023_Y + attribute \src "libresoc.v:184296.17-184296.96" + wire $and$libresoc.v:184296$11818_Y + attribute \src "libresoc.v:184295.17-184295.94" + wire $not$libresoc.v:184295$11817_Y + attribute \src "libresoc.v:184298.17-184298.94" + wire $not$libresoc.v:184298$11820_Y + attribute \src "libresoc.v:184294.17-184294.100" + wire $or$libresoc.v:184294$11816_Y + attribute \src "libresoc.v:184297.17-184297.99" + wire $or$libresoc.v:184297$11819_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -380042,11 +345022,11 @@ module \reset_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:184217.7-184217.15" + attribute \src "libresoc.v:184265.7-184265.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -380063,7 +345043,7 @@ module \reset_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184248$12022 + cell $and $and$libresoc.v:184296$11818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380071,26 +345051,26 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184248$12022_Y + connect \Y $and$libresoc.v:184296$11818_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184247$12021 + cell $not $not$libresoc.v:184295$11817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:184247$12021_Y + connect \Y $not$libresoc.v:184295$11817_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184250$12024 + cell $not $not$libresoc.v:184298$11820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:184250$12024_Y + connect \Y $not$libresoc.v:184298$11820_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184246$12020 + cell $or $or$libresoc.v:184294$11816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380098,10 +345078,10 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:184246$12020_Y + connect \Y $or$libresoc.v:184294$11816_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184249$12023 + cell $or $or$libresoc.v:184297$11819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380109,39 +345089,39 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:184249$12023_Y + connect \Y $or$libresoc.v:184297$11819_Y end - attribute \src "libresoc.v:184217.7-184217.20" - process $proc$libresoc.v:184217$12029 + attribute \src "libresoc.v:184265.7-184265.20" + process $proc$libresoc.v:184265$11825 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184233.7-184233.19" - process $proc$libresoc.v:184233$12030 + attribute \src "libresoc.v:184281.7-184281.19" + process $proc$libresoc.v:184281$11826 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184251.3-184252.27" - process $proc$libresoc.v:184251$12025 + attribute \src "libresoc.v:184299.3-184300.27" + process $proc$libresoc.v:184299$11821 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184253.3-184261.6" - process $proc$libresoc.v:184253$12026 + attribute \src "libresoc.v:184301.3-184309.6" + process $proc$libresoc.v:184301$11822 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12027 $1\q_int$next[0:0]$12028 - attribute \src "libresoc.v:184254.5-184254.29" + assign $0\q_int$next[0:0]$11823 $1\q_int$next[0:0]$11824 + attribute \src "libresoc.v:184302.5-184302.29" switch \initial - attribute \src "libresoc.v:184254.9-184254.17" + attribute \src "libresoc.v:184302.9-184302.17" case 1'1 case end @@ -380150,47 +345130,47 @@ module \reset_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12028 1'0 + assign $1\q_int$next[0:0]$11824 1'0 case - assign $1\q_int$next[0:0]$12028 \$5 + assign $1\q_int$next[0:0]$11824 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12027 + update \q_int$next $0\q_int$next[0:0]$11823 end - connect \$9 $or$libresoc.v:184246$12020_Y - connect \$1 $not$libresoc.v:184247$12021_Y - connect \$3 $and$libresoc.v:184248$12022_Y - connect \$5 $or$libresoc.v:184249$12023_Y - connect \$7 $not$libresoc.v:184250$12024_Y + connect \$9 $or$libresoc.v:184294$11816_Y + connect \$1 $not$libresoc.v:184295$11817_Y + connect \$3 $and$libresoc.v:184296$11818_Y + connect \$5 $or$libresoc.v:184297$11819_Y + connect \$7 $not$libresoc.v:184298$11820_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:184269.1-184318.10" +attribute \src "libresoc.v:184317.1-184366.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" attribute \generator "nMigen" module \reset_l$131 - attribute \src "libresoc.v:184270.7-184270.20" + attribute \src "libresoc.v:184318.7-184318.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184306.3-184314.6" - wire $0\q_int$next[0:0]$12038 - attribute \src "libresoc.v:184304.3-184305.27" + attribute \src "libresoc.v:184354.3-184362.6" + wire $0\q_int$next[0:0]$11834 + attribute \src "libresoc.v:184352.3-184353.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184306.3-184314.6" - wire $1\q_int$next[0:0]$12039 - attribute \src "libresoc.v:184286.7-184286.19" + attribute \src "libresoc.v:184354.3-184362.6" + wire $1\q_int$next[0:0]$11835 + attribute \src "libresoc.v:184334.7-184334.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184301.17-184301.96" - wire $and$libresoc.v:184301$12033_Y - attribute \src "libresoc.v:184300.17-184300.94" - wire $not$libresoc.v:184300$12032_Y - attribute \src "libresoc.v:184303.17-184303.94" - wire $not$libresoc.v:184303$12035_Y - attribute \src "libresoc.v:184299.17-184299.100" - wire $or$libresoc.v:184299$12031_Y - attribute \src "libresoc.v:184302.17-184302.99" - wire $or$libresoc.v:184302$12034_Y + attribute \src "libresoc.v:184349.17-184349.96" + wire $and$libresoc.v:184349$11829_Y + attribute \src "libresoc.v:184348.17-184348.94" + wire $not$libresoc.v:184348$11828_Y + attribute \src "libresoc.v:184351.17-184351.94" + wire $not$libresoc.v:184351$11831_Y + attribute \src "libresoc.v:184347.17-184347.100" + wire $or$libresoc.v:184347$11827_Y + attribute \src "libresoc.v:184350.17-184350.99" + wire $or$libresoc.v:184350$11830_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -380201,11 +345181,11 @@ module \reset_l$131 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:184270.7-184270.15" + attribute \src "libresoc.v:184318.7-184318.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -380222,7 +345202,7 @@ module \reset_l$131 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184301$12033 + cell $and $and$libresoc.v:184349$11829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380230,26 +345210,26 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184301$12033_Y + connect \Y $and$libresoc.v:184349$11829_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184300$12032 + cell $not $not$libresoc.v:184348$11828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:184300$12032_Y + connect \Y $not$libresoc.v:184348$11828_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184303$12035 + cell $not $not$libresoc.v:184351$11831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:184303$12035_Y + connect \Y $not$libresoc.v:184351$11831_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184299$12031 + cell $or $or$libresoc.v:184347$11827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380257,10 +345237,10 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:184299$12031_Y + connect \Y $or$libresoc.v:184347$11827_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184302$12034 + cell $or $or$libresoc.v:184350$11830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380268,39 +345248,39 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:184302$12034_Y + connect \Y $or$libresoc.v:184350$11830_Y end - attribute \src "libresoc.v:184270.7-184270.20" - process $proc$libresoc.v:184270$12040 + attribute \src "libresoc.v:184318.7-184318.20" + process $proc$libresoc.v:184318$11836 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184286.7-184286.19" - process $proc$libresoc.v:184286$12041 + attribute \src "libresoc.v:184334.7-184334.19" + process $proc$libresoc.v:184334$11837 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184304.3-184305.27" - process $proc$libresoc.v:184304$12036 + attribute \src "libresoc.v:184352.3-184353.27" + process $proc$libresoc.v:184352$11832 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184306.3-184314.6" - process $proc$libresoc.v:184306$12037 + attribute \src "libresoc.v:184354.3-184362.6" + process $proc$libresoc.v:184354$11833 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12038 $1\q_int$next[0:0]$12039 - attribute \src "libresoc.v:184307.5-184307.29" + assign $0\q_int$next[0:0]$11834 $1\q_int$next[0:0]$11835 + attribute \src "libresoc.v:184355.5-184355.29" switch \initial - attribute \src "libresoc.v:184307.9-184307.17" + attribute \src "libresoc.v:184355.9-184355.17" case 1'1 case end @@ -380309,287 +345289,287 @@ module \reset_l$131 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12039 1'0 + assign $1\q_int$next[0:0]$11835 1'0 case - assign $1\q_int$next[0:0]$12039 \$5 + assign $1\q_int$next[0:0]$11835 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12038 + update \q_int$next $0\q_int$next[0:0]$11834 end - connect \$9 $or$libresoc.v:184299$12031_Y - connect \$1 $not$libresoc.v:184300$12032_Y - connect \$3 $and$libresoc.v:184301$12033_Y - connect \$5 $or$libresoc.v:184302$12034_Y - connect \$7 $not$libresoc.v:184303$12035_Y + connect \$9 $or$libresoc.v:184347$11827_Y + connect \$1 $not$libresoc.v:184348$11828_Y + connect \$3 $and$libresoc.v:184349$11829_Y + connect \$5 $or$libresoc.v:184350$11830_Y + connect \$7 $not$libresoc.v:184351$11831_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:184322.1-184909.10" +attribute \src "libresoc.v:184370.1-184957.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" attribute \generator "nMigen" module \right_mask - attribute \src "libresoc.v:184323.7-184323.20" + attribute \src "libresoc.v:184371.7-184371.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $10\mask[9:9] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $11\mask[10:10] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $12\mask[11:11] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $13\mask[12:12] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $14\mask[13:13] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $15\mask[14:14] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $16\mask[15:15] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $17\mask[16:16] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $18\mask[17:17] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $19\mask[18:18] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $1\mask[0:0] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $20\mask[19:19] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $21\mask[20:20] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $22\mask[21:21] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $23\mask[22:22] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $24\mask[23:23] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $25\mask[24:24] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $26\mask[25:25] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $27\mask[26:26] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $28\mask[27:27] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $29\mask[28:28] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $2\mask[1:1] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $30\mask[29:29] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $31\mask[30:30] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $32\mask[31:31] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $33\mask[32:32] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $34\mask[33:33] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $35\mask[34:34] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $36\mask[35:35] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $37\mask[36:36] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $38\mask[37:37] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $39\mask[38:38] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $3\mask[2:2] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $40\mask[39:39] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $41\mask[40:40] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $42\mask[41:41] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $43\mask[42:42] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $44\mask[43:43] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $45\mask[44:44] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $46\mask[45:45] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $47\mask[46:46] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $48\mask[47:47] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $49\mask[48:48] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $4\mask[3:3] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $50\mask[49:49] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $51\mask[50:50] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $52\mask[51:51] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $53\mask[52:52] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $54\mask[53:53] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $55\mask[54:54] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $56\mask[55:55] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $57\mask[56:56] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $58\mask[57:57] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $59\mask[58:58] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $5\mask[4:4] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $60\mask[59:59] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $61\mask[60:60] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $62\mask[61:61] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $63\mask[62:62] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $64\mask[63:63] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $6\mask[5:5] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $7\mask[6:6] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $8\mask[7:7] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184569.3-184956.6" wire $9\mask[8:8] - attribute \src "libresoc.v:184457.17-184457.96" - wire $gt$libresoc.v:184457$12042_Y - attribute \src "libresoc.v:184458.18-184458.98" - wire $gt$libresoc.v:184458$12043_Y - attribute \src "libresoc.v:184459.19-184459.99" - wire $gt$libresoc.v:184459$12044_Y - attribute \src "libresoc.v:184460.19-184460.99" - wire $gt$libresoc.v:184460$12045_Y - attribute \src "libresoc.v:184461.19-184461.99" - wire $gt$libresoc.v:184461$12046_Y - attribute \src "libresoc.v:184462.19-184462.99" - wire $gt$libresoc.v:184462$12047_Y - attribute \src "libresoc.v:184463.19-184463.99" - wire $gt$libresoc.v:184463$12048_Y - attribute \src "libresoc.v:184464.19-184464.99" - wire $gt$libresoc.v:184464$12049_Y - attribute \src "libresoc.v:184465.19-184465.99" - wire $gt$libresoc.v:184465$12050_Y - attribute \src "libresoc.v:184466.19-184466.99" - wire $gt$libresoc.v:184466$12051_Y - attribute \src "libresoc.v:184467.19-184467.99" - wire $gt$libresoc.v:184467$12052_Y - attribute \src "libresoc.v:184468.18-184468.97" - wire $gt$libresoc.v:184468$12053_Y - attribute \src "libresoc.v:184469.19-184469.99" - wire $gt$libresoc.v:184469$12054_Y - attribute \src "libresoc.v:184470.19-184470.99" - wire $gt$libresoc.v:184470$12055_Y - attribute \src "libresoc.v:184471.19-184471.99" - wire $gt$libresoc.v:184471$12056_Y - attribute \src "libresoc.v:184472.19-184472.99" - wire $gt$libresoc.v:184472$12057_Y - attribute \src "libresoc.v:184473.19-184473.99" - wire $gt$libresoc.v:184473$12058_Y - attribute \src "libresoc.v:184474.18-184474.97" - wire $gt$libresoc.v:184474$12059_Y - attribute \src "libresoc.v:184475.18-184475.97" - wire $gt$libresoc.v:184475$12060_Y - attribute \src "libresoc.v:184476.18-184476.97" - wire $gt$libresoc.v:184476$12061_Y - attribute \src "libresoc.v:184477.17-184477.96" - wire $gt$libresoc.v:184477$12062_Y - attribute \src "libresoc.v:184478.18-184478.97" - wire $gt$libresoc.v:184478$12063_Y - attribute \src "libresoc.v:184479.18-184479.97" - wire $gt$libresoc.v:184479$12064_Y - attribute \src "libresoc.v:184480.18-184480.97" - wire $gt$libresoc.v:184480$12065_Y - attribute \src "libresoc.v:184481.18-184481.97" - wire $gt$libresoc.v:184481$12066_Y - attribute \src "libresoc.v:184482.18-184482.97" - wire $gt$libresoc.v:184482$12067_Y - attribute \src "libresoc.v:184483.18-184483.97" - wire $gt$libresoc.v:184483$12068_Y - attribute \src "libresoc.v:184484.18-184484.97" - wire $gt$libresoc.v:184484$12069_Y - attribute \src "libresoc.v:184485.18-184485.98" - wire $gt$libresoc.v:184485$12070_Y - attribute \src "libresoc.v:184486.18-184486.98" - wire $gt$libresoc.v:184486$12071_Y - attribute \src "libresoc.v:184487.18-184487.98" - wire $gt$libresoc.v:184487$12072_Y - attribute \src "libresoc.v:184488.17-184488.96" - wire $gt$libresoc.v:184488$12073_Y - attribute \src "libresoc.v:184489.18-184489.98" - wire $gt$libresoc.v:184489$12074_Y - attribute \src "libresoc.v:184490.18-184490.98" - wire $gt$libresoc.v:184490$12075_Y - attribute \src "libresoc.v:184491.18-184491.98" - wire $gt$libresoc.v:184491$12076_Y - attribute \src "libresoc.v:184492.18-184492.98" - wire $gt$libresoc.v:184492$12077_Y - attribute \src "libresoc.v:184493.18-184493.98" - wire $gt$libresoc.v:184493$12078_Y - attribute \src "libresoc.v:184494.18-184494.98" - wire $gt$libresoc.v:184494$12079_Y - attribute \src "libresoc.v:184495.18-184495.98" - wire $gt$libresoc.v:184495$12080_Y - attribute \src "libresoc.v:184496.18-184496.98" - wire $gt$libresoc.v:184496$12081_Y - attribute \src "libresoc.v:184497.18-184497.98" - wire $gt$libresoc.v:184497$12082_Y - attribute \src "libresoc.v:184498.18-184498.98" - wire $gt$libresoc.v:184498$12083_Y - attribute \src "libresoc.v:184499.17-184499.96" - wire $gt$libresoc.v:184499$12084_Y - attribute \src "libresoc.v:184500.18-184500.98" - wire $gt$libresoc.v:184500$12085_Y - attribute \src "libresoc.v:184501.18-184501.98" - wire $gt$libresoc.v:184501$12086_Y - attribute \src "libresoc.v:184502.18-184502.98" - wire $gt$libresoc.v:184502$12087_Y - attribute \src "libresoc.v:184503.18-184503.98" - wire $gt$libresoc.v:184503$12088_Y - attribute \src "libresoc.v:184504.18-184504.98" - wire $gt$libresoc.v:184504$12089_Y - attribute \src "libresoc.v:184505.18-184505.98" - wire $gt$libresoc.v:184505$12090_Y + attribute \src "libresoc.v:184505.17-184505.96" + wire $gt$libresoc.v:184505$11838_Y attribute \src "libresoc.v:184506.18-184506.98" - wire $gt$libresoc.v:184506$12091_Y - attribute \src "libresoc.v:184507.18-184507.98" - wire $gt$libresoc.v:184507$12092_Y - attribute \src "libresoc.v:184508.18-184508.98" - wire $gt$libresoc.v:184508$12093_Y - attribute \src "libresoc.v:184509.18-184509.98" - wire $gt$libresoc.v:184509$12094_Y - attribute \src "libresoc.v:184510.17-184510.96" - wire $gt$libresoc.v:184510$12095_Y - attribute \src "libresoc.v:184511.18-184511.98" - wire $gt$libresoc.v:184511$12096_Y - attribute \src "libresoc.v:184512.18-184512.98" - wire $gt$libresoc.v:184512$12097_Y - attribute \src "libresoc.v:184513.18-184513.98" - wire $gt$libresoc.v:184513$12098_Y - attribute \src "libresoc.v:184514.18-184514.98" - wire $gt$libresoc.v:184514$12099_Y - attribute \src "libresoc.v:184515.18-184515.98" - wire $gt$libresoc.v:184515$12100_Y - attribute \src "libresoc.v:184516.18-184516.98" - wire $gt$libresoc.v:184516$12101_Y - attribute \src "libresoc.v:184517.18-184517.98" - wire $gt$libresoc.v:184517$12102_Y - attribute \src "libresoc.v:184518.18-184518.98" - wire $gt$libresoc.v:184518$12103_Y - attribute \src "libresoc.v:184519.18-184519.98" - wire $gt$libresoc.v:184519$12104_Y - attribute \src "libresoc.v:184520.18-184520.98" - wire $gt$libresoc.v:184520$12105_Y + wire $gt$libresoc.v:184506$11839_Y + attribute \src "libresoc.v:184507.19-184507.99" + wire $gt$libresoc.v:184507$11840_Y + attribute \src "libresoc.v:184508.19-184508.99" + wire $gt$libresoc.v:184508$11841_Y + attribute \src "libresoc.v:184509.19-184509.99" + wire $gt$libresoc.v:184509$11842_Y + attribute \src "libresoc.v:184510.19-184510.99" + wire $gt$libresoc.v:184510$11843_Y + attribute \src "libresoc.v:184511.19-184511.99" + wire $gt$libresoc.v:184511$11844_Y + attribute \src "libresoc.v:184512.19-184512.99" + wire $gt$libresoc.v:184512$11845_Y + attribute \src "libresoc.v:184513.19-184513.99" + wire $gt$libresoc.v:184513$11846_Y + attribute \src "libresoc.v:184514.19-184514.99" + wire $gt$libresoc.v:184514$11847_Y + attribute \src "libresoc.v:184515.19-184515.99" + wire $gt$libresoc.v:184515$11848_Y + attribute \src "libresoc.v:184516.18-184516.97" + wire $gt$libresoc.v:184516$11849_Y + attribute \src "libresoc.v:184517.19-184517.99" + wire $gt$libresoc.v:184517$11850_Y + attribute \src "libresoc.v:184518.19-184518.99" + wire $gt$libresoc.v:184518$11851_Y + attribute \src "libresoc.v:184519.19-184519.99" + wire $gt$libresoc.v:184519$11852_Y + attribute \src "libresoc.v:184520.19-184520.99" + wire $gt$libresoc.v:184520$11853_Y + attribute \src "libresoc.v:184521.19-184521.99" + wire $gt$libresoc.v:184521$11854_Y + attribute \src "libresoc.v:184522.18-184522.97" + wire $gt$libresoc.v:184522$11855_Y + attribute \src "libresoc.v:184523.18-184523.97" + wire $gt$libresoc.v:184523$11856_Y + attribute \src "libresoc.v:184524.18-184524.97" + wire $gt$libresoc.v:184524$11857_Y + attribute \src "libresoc.v:184525.17-184525.96" + wire $gt$libresoc.v:184525$11858_Y + attribute \src "libresoc.v:184526.18-184526.97" + wire $gt$libresoc.v:184526$11859_Y + attribute \src "libresoc.v:184527.18-184527.97" + wire $gt$libresoc.v:184527$11860_Y + attribute \src "libresoc.v:184528.18-184528.97" + wire $gt$libresoc.v:184528$11861_Y + attribute \src "libresoc.v:184529.18-184529.97" + wire $gt$libresoc.v:184529$11862_Y + attribute \src "libresoc.v:184530.18-184530.97" + wire $gt$libresoc.v:184530$11863_Y + attribute \src "libresoc.v:184531.18-184531.97" + wire $gt$libresoc.v:184531$11864_Y + attribute \src "libresoc.v:184532.18-184532.97" + wire $gt$libresoc.v:184532$11865_Y + attribute \src "libresoc.v:184533.18-184533.98" + wire $gt$libresoc.v:184533$11866_Y + attribute \src "libresoc.v:184534.18-184534.98" + wire $gt$libresoc.v:184534$11867_Y + attribute \src "libresoc.v:184535.18-184535.98" + wire $gt$libresoc.v:184535$11868_Y + attribute \src "libresoc.v:184536.17-184536.96" + wire $gt$libresoc.v:184536$11869_Y + attribute \src "libresoc.v:184537.18-184537.98" + wire $gt$libresoc.v:184537$11870_Y + attribute \src "libresoc.v:184538.18-184538.98" + wire $gt$libresoc.v:184538$11871_Y + attribute \src "libresoc.v:184539.18-184539.98" + wire $gt$libresoc.v:184539$11872_Y + attribute \src "libresoc.v:184540.18-184540.98" + wire $gt$libresoc.v:184540$11873_Y + attribute \src "libresoc.v:184541.18-184541.98" + wire $gt$libresoc.v:184541$11874_Y + attribute \src "libresoc.v:184542.18-184542.98" + wire $gt$libresoc.v:184542$11875_Y + attribute \src "libresoc.v:184543.18-184543.98" + wire $gt$libresoc.v:184543$11876_Y + attribute \src "libresoc.v:184544.18-184544.98" + wire $gt$libresoc.v:184544$11877_Y + attribute \src "libresoc.v:184545.18-184545.98" + wire $gt$libresoc.v:184545$11878_Y + attribute \src "libresoc.v:184546.18-184546.98" + wire $gt$libresoc.v:184546$11879_Y + attribute \src "libresoc.v:184547.17-184547.96" + wire $gt$libresoc.v:184547$11880_Y + attribute \src "libresoc.v:184548.18-184548.98" + wire $gt$libresoc.v:184548$11881_Y + attribute \src "libresoc.v:184549.18-184549.98" + wire $gt$libresoc.v:184549$11882_Y + attribute \src "libresoc.v:184550.18-184550.98" + wire $gt$libresoc.v:184550$11883_Y + attribute \src "libresoc.v:184551.18-184551.98" + wire $gt$libresoc.v:184551$11884_Y + attribute \src "libresoc.v:184552.18-184552.98" + wire $gt$libresoc.v:184552$11885_Y + attribute \src "libresoc.v:184553.18-184553.98" + wire $gt$libresoc.v:184553$11886_Y + attribute \src "libresoc.v:184554.18-184554.98" + wire $gt$libresoc.v:184554$11887_Y + attribute \src "libresoc.v:184555.18-184555.98" + wire $gt$libresoc.v:184555$11888_Y + attribute \src "libresoc.v:184556.18-184556.98" + wire $gt$libresoc.v:184556$11889_Y + attribute \src "libresoc.v:184557.18-184557.98" + wire $gt$libresoc.v:184557$11890_Y + attribute \src "libresoc.v:184558.17-184558.96" + wire $gt$libresoc.v:184558$11891_Y + attribute \src "libresoc.v:184559.18-184559.98" + wire $gt$libresoc.v:184559$11892_Y + attribute \src "libresoc.v:184560.18-184560.98" + wire $gt$libresoc.v:184560$11893_Y + attribute \src "libresoc.v:184561.18-184561.98" + wire $gt$libresoc.v:184561$11894_Y + attribute \src "libresoc.v:184562.18-184562.98" + wire $gt$libresoc.v:184562$11895_Y + attribute \src "libresoc.v:184563.18-184563.98" + wire $gt$libresoc.v:184563$11896_Y + attribute \src "libresoc.v:184564.18-184564.98" + wire $gt$libresoc.v:184564$11897_Y + attribute \src "libresoc.v:184565.18-184565.98" + wire $gt$libresoc.v:184565$11898_Y + attribute \src "libresoc.v:184566.18-184566.98" + wire $gt$libresoc.v:184566$11899_Y + attribute \src "libresoc.v:184567.18-184567.98" + wire $gt$libresoc.v:184567$11900_Y + attribute \src "libresoc.v:184568.18-184568.98" + wire $gt$libresoc.v:184568$11901_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -380718,14 +345698,14 @@ module \right_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:184323.7-184323.15" + attribute \src "libresoc.v:184371.7-184371.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184457$12042 + cell $gt $gt$libresoc.v:184505$11838 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380733,10 +345713,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:184457$12042_Y + connect \Y $gt$libresoc.v:184505$11838_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184458$12043 + cell $gt $gt$libresoc.v:184506$11839 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380744,10 +345724,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:184458$12043_Y + connect \Y $gt$libresoc.v:184506$11839_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184459$12044 + cell $gt $gt$libresoc.v:184507$11840 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380755,10 +345735,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:184459$12044_Y + connect \Y $gt$libresoc.v:184507$11840_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184460$12045 + cell $gt $gt$libresoc.v:184508$11841 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380766,10 +345746,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:184460$12045_Y + connect \Y $gt$libresoc.v:184508$11841_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184461$12046 + cell $gt $gt$libresoc.v:184509$11842 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380777,10 +345757,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:184461$12046_Y + connect \Y $gt$libresoc.v:184509$11842_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184462$12047 + cell $gt $gt$libresoc.v:184510$11843 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380788,10 +345768,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:184462$12047_Y + connect \Y $gt$libresoc.v:184510$11843_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184463$12048 + cell $gt $gt$libresoc.v:184511$11844 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380799,10 +345779,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:184463$12048_Y + connect \Y $gt$libresoc.v:184511$11844_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184464$12049 + cell $gt $gt$libresoc.v:184512$11845 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380810,10 +345790,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:184464$12049_Y + connect \Y $gt$libresoc.v:184512$11845_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184465$12050 + cell $gt $gt$libresoc.v:184513$11846 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380821,10 +345801,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:184465$12050_Y + connect \Y $gt$libresoc.v:184513$11846_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184466$12051 + cell $gt $gt$libresoc.v:184514$11847 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380832,10 +345812,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:184466$12051_Y + connect \Y $gt$libresoc.v:184514$11847_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184467$12052 + cell $gt $gt$libresoc.v:184515$11848 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380843,10 +345823,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:184467$12052_Y + connect \Y $gt$libresoc.v:184515$11848_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184468$12053 + cell $gt $gt$libresoc.v:184516$11849 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380854,10 +345834,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:184468$12053_Y + connect \Y $gt$libresoc.v:184516$11849_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184469$12054 + cell $gt $gt$libresoc.v:184517$11850 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380865,10 +345845,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:184469$12054_Y + connect \Y $gt$libresoc.v:184517$11850_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184470$12055 + cell $gt $gt$libresoc.v:184518$11851 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380876,10 +345856,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:184470$12055_Y + connect \Y $gt$libresoc.v:184518$11851_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184471$12056 + cell $gt $gt$libresoc.v:184519$11852 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380887,10 +345867,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:184471$12056_Y + connect \Y $gt$libresoc.v:184519$11852_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184472$12057 + cell $gt $gt$libresoc.v:184520$11853 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380898,10 +345878,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:184472$12057_Y + connect \Y $gt$libresoc.v:184520$11853_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184473$12058 + cell $gt $gt$libresoc.v:184521$11854 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380909,10 +345889,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:184473$12058_Y + connect \Y $gt$libresoc.v:184521$11854_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184474$12059 + cell $gt $gt$libresoc.v:184522$11855 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380920,10 +345900,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:184474$12059_Y + connect \Y $gt$libresoc.v:184522$11855_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184475$12060 + cell $gt $gt$libresoc.v:184523$11856 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380931,10 +345911,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:184475$12060_Y + connect \Y $gt$libresoc.v:184523$11856_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184476$12061 + cell $gt $gt$libresoc.v:184524$11857 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380942,10 +345922,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:184476$12061_Y + connect \Y $gt$libresoc.v:184524$11857_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184477$12062 + cell $gt $gt$libresoc.v:184525$11858 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380953,10 +345933,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:184477$12062_Y + connect \Y $gt$libresoc.v:184525$11858_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184478$12063 + cell $gt $gt$libresoc.v:184526$11859 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380964,10 +345944,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:184478$12063_Y + connect \Y $gt$libresoc.v:184526$11859_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184479$12064 + cell $gt $gt$libresoc.v:184527$11860 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380975,10 +345955,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:184479$12064_Y + connect \Y $gt$libresoc.v:184527$11860_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184480$12065 + cell $gt $gt$libresoc.v:184528$11861 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380986,10 +345966,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:184480$12065_Y + connect \Y $gt$libresoc.v:184528$11861_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184481$12066 + cell $gt $gt$libresoc.v:184529$11862 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380997,10 +345977,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:184481$12066_Y + connect \Y $gt$libresoc.v:184529$11862_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184482$12067 + cell $gt $gt$libresoc.v:184530$11863 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381008,10 +345988,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:184482$12067_Y + connect \Y $gt$libresoc.v:184530$11863_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184483$12068 + cell $gt $gt$libresoc.v:184531$11864 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381019,10 +345999,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:184483$12068_Y + connect \Y $gt$libresoc.v:184531$11864_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184484$12069 + cell $gt $gt$libresoc.v:184532$11865 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381030,10 +346010,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:184484$12069_Y + connect \Y $gt$libresoc.v:184532$11865_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184485$12070 + cell $gt $gt$libresoc.v:184533$11866 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381041,10 +346021,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:184485$12070_Y + connect \Y $gt$libresoc.v:184533$11866_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184486$12071 + cell $gt $gt$libresoc.v:184534$11867 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381052,10 +346032,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:184486$12071_Y + connect \Y $gt$libresoc.v:184534$11867_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184487$12072 + cell $gt $gt$libresoc.v:184535$11868 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381063,10 +346043,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:184487$12072_Y + connect \Y $gt$libresoc.v:184535$11868_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184488$12073 + cell $gt $gt$libresoc.v:184536$11869 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381074,10 +346054,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:184488$12073_Y + connect \Y $gt$libresoc.v:184536$11869_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184489$12074 + cell $gt $gt$libresoc.v:184537$11870 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381085,10 +346065,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:184489$12074_Y + connect \Y $gt$libresoc.v:184537$11870_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184490$12075 + cell $gt $gt$libresoc.v:184538$11871 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381096,10 +346076,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:184490$12075_Y + connect \Y $gt$libresoc.v:184538$11871_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184491$12076 + cell $gt $gt$libresoc.v:184539$11872 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381107,10 +346087,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:184491$12076_Y + connect \Y $gt$libresoc.v:184539$11872_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184492$12077 + cell $gt $gt$libresoc.v:184540$11873 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381118,10 +346098,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:184492$12077_Y + connect \Y $gt$libresoc.v:184540$11873_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184493$12078 + cell $gt $gt$libresoc.v:184541$11874 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381129,10 +346109,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:184493$12078_Y + connect \Y $gt$libresoc.v:184541$11874_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184494$12079 + cell $gt $gt$libresoc.v:184542$11875 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381140,10 +346120,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:184494$12079_Y + connect \Y $gt$libresoc.v:184542$11875_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184495$12080 + cell $gt $gt$libresoc.v:184543$11876 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381151,10 +346131,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:184495$12080_Y + connect \Y $gt$libresoc.v:184543$11876_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184496$12081 + cell $gt $gt$libresoc.v:184544$11877 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381162,10 +346142,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:184496$12081_Y + connect \Y $gt$libresoc.v:184544$11877_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184497$12082 + cell $gt $gt$libresoc.v:184545$11878 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381173,10 +346153,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:184497$12082_Y + connect \Y $gt$libresoc.v:184545$11878_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184498$12083 + cell $gt $gt$libresoc.v:184546$11879 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381184,10 +346164,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:184498$12083_Y + connect \Y $gt$libresoc.v:184546$11879_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184499$12084 + cell $gt $gt$libresoc.v:184547$11880 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381195,10 +346175,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:184499$12084_Y + connect \Y $gt$libresoc.v:184547$11880_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184500$12085 + cell $gt $gt$libresoc.v:184548$11881 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381206,10 +346186,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:184500$12085_Y + connect \Y $gt$libresoc.v:184548$11881_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184501$12086 + cell $gt $gt$libresoc.v:184549$11882 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381217,10 +346197,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:184501$12086_Y + connect \Y $gt$libresoc.v:184549$11882_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184502$12087 + cell $gt $gt$libresoc.v:184550$11883 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381228,10 +346208,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:184502$12087_Y + connect \Y $gt$libresoc.v:184550$11883_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184503$12088 + cell $gt $gt$libresoc.v:184551$11884 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381239,10 +346219,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:184503$12088_Y + connect \Y $gt$libresoc.v:184551$11884_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184504$12089 + cell $gt $gt$libresoc.v:184552$11885 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381250,10 +346230,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:184504$12089_Y + connect \Y $gt$libresoc.v:184552$11885_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184505$12090 + cell $gt $gt$libresoc.v:184553$11886 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381261,10 +346241,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:184505$12090_Y + connect \Y $gt$libresoc.v:184553$11886_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184506$12091 + cell $gt $gt$libresoc.v:184554$11887 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381272,10 +346252,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:184506$12091_Y + connect \Y $gt$libresoc.v:184554$11887_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184507$12092 + cell $gt $gt$libresoc.v:184555$11888 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381283,10 +346263,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:184507$12092_Y + connect \Y $gt$libresoc.v:184555$11888_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184508$12093 + cell $gt $gt$libresoc.v:184556$11889 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381294,10 +346274,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:184508$12093_Y + connect \Y $gt$libresoc.v:184556$11889_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184509$12094 + cell $gt $gt$libresoc.v:184557$11890 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381305,10 +346285,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:184509$12094_Y + connect \Y $gt$libresoc.v:184557$11890_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184510$12095 + cell $gt $gt$libresoc.v:184558$11891 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381316,10 +346296,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:184510$12095_Y + connect \Y $gt$libresoc.v:184558$11891_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184511$12096 + cell $gt $gt$libresoc.v:184559$11892 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381327,10 +346307,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:184511$12096_Y + connect \Y $gt$libresoc.v:184559$11892_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184512$12097 + cell $gt $gt$libresoc.v:184560$11893 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381338,10 +346318,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:184512$12097_Y + connect \Y $gt$libresoc.v:184560$11893_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184513$12098 + cell $gt $gt$libresoc.v:184561$11894 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381349,10 +346329,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:184513$12098_Y + connect \Y $gt$libresoc.v:184561$11894_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184514$12099 + cell $gt $gt$libresoc.v:184562$11895 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381360,10 +346340,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:184514$12099_Y + connect \Y $gt$libresoc.v:184562$11895_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184515$12100 + cell $gt $gt$libresoc.v:184563$11896 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381371,10 +346351,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:184515$12100_Y + connect \Y $gt$libresoc.v:184563$11896_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184516$12101 + cell $gt $gt$libresoc.v:184564$11897 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381382,10 +346362,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:184516$12101_Y + connect \Y $gt$libresoc.v:184564$11897_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184517$12102 + cell $gt $gt$libresoc.v:184565$11898 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381393,10 +346373,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:184517$12102_Y + connect \Y $gt$libresoc.v:184565$11898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184518$12103 + cell $gt $gt$libresoc.v:184566$11899 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381404,10 +346384,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:184518$12103_Y + connect \Y $gt$libresoc.v:184566$11899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184519$12104 + cell $gt $gt$libresoc.v:184567$11900 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381415,10 +346395,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:184519$12104_Y + connect \Y $gt$libresoc.v:184567$11900_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184520$12105 + cell $gt $gt$libresoc.v:184568$11901 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381426,18 +346406,18 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:184520$12105_Y + connect \Y $gt$libresoc.v:184568$11901_Y end - attribute \src "libresoc.v:184323.7-184323.20" - process $proc$libresoc.v:184323$12107 + attribute \src "libresoc.v:184371.7-184371.20" + process $proc$libresoc.v:184371$11903 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184521.3-184908.6" - process $proc$libresoc.v:184521$12106 + attribute \src "libresoc.v:184569.3-184956.6" + process $proc$libresoc.v:184569$11902 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -381504,9 +346484,9 @@ module \right_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:184522.5-184522.29" + attribute \src "libresoc.v:184570.5-184570.29" switch \initial - attribute \src "libresoc.v:184522.9-184522.17" + attribute \src "libresoc.v:184570.9-184570.17" case 1'1 case end @@ -382089,102 +347069,102 @@ module \right_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:184457$12042_Y - connect \$99 $gt$libresoc.v:184458$12043_Y - connect \$101 $gt$libresoc.v:184459$12044_Y - connect \$103 $gt$libresoc.v:184460$12045_Y - connect \$105 $gt$libresoc.v:184461$12046_Y - connect \$107 $gt$libresoc.v:184462$12047_Y - connect \$109 $gt$libresoc.v:184463$12048_Y - connect \$111 $gt$libresoc.v:184464$12049_Y - connect \$113 $gt$libresoc.v:184465$12050_Y - connect \$115 $gt$libresoc.v:184466$12051_Y - connect \$117 $gt$libresoc.v:184467$12052_Y - connect \$11 $gt$libresoc.v:184468$12053_Y - connect \$119 $gt$libresoc.v:184469$12054_Y - connect \$121 $gt$libresoc.v:184470$12055_Y - connect \$123 $gt$libresoc.v:184471$12056_Y - connect \$125 $gt$libresoc.v:184472$12057_Y - connect \$127 $gt$libresoc.v:184473$12058_Y - connect \$13 $gt$libresoc.v:184474$12059_Y - connect \$15 $gt$libresoc.v:184475$12060_Y - connect \$17 $gt$libresoc.v:184476$12061_Y - connect \$1 $gt$libresoc.v:184477$12062_Y - connect \$19 $gt$libresoc.v:184478$12063_Y - connect \$21 $gt$libresoc.v:184479$12064_Y - connect \$23 $gt$libresoc.v:184480$12065_Y - connect \$25 $gt$libresoc.v:184481$12066_Y - connect \$27 $gt$libresoc.v:184482$12067_Y - connect \$29 $gt$libresoc.v:184483$12068_Y - connect \$31 $gt$libresoc.v:184484$12069_Y - connect \$33 $gt$libresoc.v:184485$12070_Y - connect \$35 $gt$libresoc.v:184486$12071_Y - connect \$37 $gt$libresoc.v:184487$12072_Y - connect \$3 $gt$libresoc.v:184488$12073_Y - connect \$39 $gt$libresoc.v:184489$12074_Y - connect \$41 $gt$libresoc.v:184490$12075_Y - connect \$43 $gt$libresoc.v:184491$12076_Y - connect \$45 $gt$libresoc.v:184492$12077_Y - connect \$47 $gt$libresoc.v:184493$12078_Y - connect \$49 $gt$libresoc.v:184494$12079_Y - connect \$51 $gt$libresoc.v:184495$12080_Y - connect \$53 $gt$libresoc.v:184496$12081_Y - connect \$55 $gt$libresoc.v:184497$12082_Y - connect \$57 $gt$libresoc.v:184498$12083_Y - connect \$5 $gt$libresoc.v:184499$12084_Y - connect \$59 $gt$libresoc.v:184500$12085_Y - connect \$61 $gt$libresoc.v:184501$12086_Y - connect \$63 $gt$libresoc.v:184502$12087_Y - connect \$65 $gt$libresoc.v:184503$12088_Y - connect \$67 $gt$libresoc.v:184504$12089_Y - connect \$69 $gt$libresoc.v:184505$12090_Y - connect \$71 $gt$libresoc.v:184506$12091_Y - connect \$73 $gt$libresoc.v:184507$12092_Y - connect \$75 $gt$libresoc.v:184508$12093_Y - connect \$77 $gt$libresoc.v:184509$12094_Y - connect \$7 $gt$libresoc.v:184510$12095_Y - connect \$79 $gt$libresoc.v:184511$12096_Y - connect \$81 $gt$libresoc.v:184512$12097_Y - connect \$83 $gt$libresoc.v:184513$12098_Y - connect \$85 $gt$libresoc.v:184514$12099_Y - connect \$87 $gt$libresoc.v:184515$12100_Y - connect \$89 $gt$libresoc.v:184516$12101_Y - connect \$91 $gt$libresoc.v:184517$12102_Y - connect \$93 $gt$libresoc.v:184518$12103_Y - connect \$95 $gt$libresoc.v:184519$12104_Y - connect \$97 $gt$libresoc.v:184520$12105_Y + connect \$9 $gt$libresoc.v:184505$11838_Y + connect \$99 $gt$libresoc.v:184506$11839_Y + connect \$101 $gt$libresoc.v:184507$11840_Y + connect \$103 $gt$libresoc.v:184508$11841_Y + connect \$105 $gt$libresoc.v:184509$11842_Y + connect \$107 $gt$libresoc.v:184510$11843_Y + connect \$109 $gt$libresoc.v:184511$11844_Y + connect \$111 $gt$libresoc.v:184512$11845_Y + connect \$113 $gt$libresoc.v:184513$11846_Y + connect \$115 $gt$libresoc.v:184514$11847_Y + connect \$117 $gt$libresoc.v:184515$11848_Y + connect \$11 $gt$libresoc.v:184516$11849_Y + connect \$119 $gt$libresoc.v:184517$11850_Y + connect \$121 $gt$libresoc.v:184518$11851_Y + connect \$123 $gt$libresoc.v:184519$11852_Y + connect \$125 $gt$libresoc.v:184520$11853_Y + connect \$127 $gt$libresoc.v:184521$11854_Y + connect \$13 $gt$libresoc.v:184522$11855_Y + connect \$15 $gt$libresoc.v:184523$11856_Y + connect \$17 $gt$libresoc.v:184524$11857_Y + connect \$1 $gt$libresoc.v:184525$11858_Y + connect \$19 $gt$libresoc.v:184526$11859_Y + connect \$21 $gt$libresoc.v:184527$11860_Y + connect \$23 $gt$libresoc.v:184528$11861_Y + connect \$25 $gt$libresoc.v:184529$11862_Y + connect \$27 $gt$libresoc.v:184530$11863_Y + connect \$29 $gt$libresoc.v:184531$11864_Y + connect \$31 $gt$libresoc.v:184532$11865_Y + connect \$33 $gt$libresoc.v:184533$11866_Y + connect \$35 $gt$libresoc.v:184534$11867_Y + connect \$37 $gt$libresoc.v:184535$11868_Y + connect \$3 $gt$libresoc.v:184536$11869_Y + connect \$39 $gt$libresoc.v:184537$11870_Y + connect \$41 $gt$libresoc.v:184538$11871_Y + connect \$43 $gt$libresoc.v:184539$11872_Y + connect \$45 $gt$libresoc.v:184540$11873_Y + connect \$47 $gt$libresoc.v:184541$11874_Y + connect \$49 $gt$libresoc.v:184542$11875_Y + connect \$51 $gt$libresoc.v:184543$11876_Y + connect \$53 $gt$libresoc.v:184544$11877_Y + connect \$55 $gt$libresoc.v:184545$11878_Y + connect \$57 $gt$libresoc.v:184546$11879_Y + connect \$5 $gt$libresoc.v:184547$11880_Y + connect \$59 $gt$libresoc.v:184548$11881_Y + connect \$61 $gt$libresoc.v:184549$11882_Y + connect \$63 $gt$libresoc.v:184550$11883_Y + connect \$65 $gt$libresoc.v:184551$11884_Y + connect \$67 $gt$libresoc.v:184552$11885_Y + connect \$69 $gt$libresoc.v:184553$11886_Y + connect \$71 $gt$libresoc.v:184554$11887_Y + connect \$73 $gt$libresoc.v:184555$11888_Y + connect \$75 $gt$libresoc.v:184556$11889_Y + connect \$77 $gt$libresoc.v:184557$11890_Y + connect \$7 $gt$libresoc.v:184558$11891_Y + connect \$79 $gt$libresoc.v:184559$11892_Y + connect \$81 $gt$libresoc.v:184560$11893_Y + connect \$83 $gt$libresoc.v:184561$11894_Y + connect \$85 $gt$libresoc.v:184562$11895_Y + connect \$87 $gt$libresoc.v:184563$11896_Y + connect \$89 $gt$libresoc.v:184564$11897_Y + connect \$91 $gt$libresoc.v:184565$11898_Y + connect \$93 $gt$libresoc.v:184566$11899_Y + connect \$95 $gt$libresoc.v:184567$11900_Y + connect \$97 $gt$libresoc.v:184568$11901_Y end -attribute \src "libresoc.v:184913.1-184971.10" +attribute \src "libresoc.v:184961.1-185019.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l" attribute \generator "nMigen" module \rok_l - attribute \src "libresoc.v:184914.7-184914.20" + attribute \src "libresoc.v:184962.7-184962.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184959.3-184967.6" - wire $0\q_int$next[0:0]$12118 - attribute \src "libresoc.v:184957.3-184958.27" + attribute \src "libresoc.v:185007.3-185015.6" + wire $0\q_int$next[0:0]$11914 + attribute \src "libresoc.v:185005.3-185006.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184959.3-184967.6" - wire $1\q_int$next[0:0]$12119 - attribute \src "libresoc.v:184936.7-184936.19" + attribute \src "libresoc.v:185007.3-185015.6" + wire $1\q_int$next[0:0]$11915 + attribute \src "libresoc.v:184984.7-184984.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184949.17-184949.96" - wire $and$libresoc.v:184949$12108_Y - attribute \src "libresoc.v:184954.17-184954.96" - wire $and$libresoc.v:184954$12113_Y - attribute \src "libresoc.v:184951.18-184951.94" - wire $not$libresoc.v:184951$12110_Y - attribute \src "libresoc.v:184953.17-184953.93" - wire $not$libresoc.v:184953$12112_Y - attribute \src "libresoc.v:184956.17-184956.93" - wire $not$libresoc.v:184956$12115_Y - attribute \src "libresoc.v:184950.18-184950.99" - wire $or$libresoc.v:184950$12109_Y - attribute \src "libresoc.v:184952.18-184952.100" - wire $or$libresoc.v:184952$12111_Y - attribute \src "libresoc.v:184955.17-184955.98" - wire $or$libresoc.v:184955$12114_Y + attribute \src "libresoc.v:184997.17-184997.96" + wire $and$libresoc.v:184997$11904_Y + attribute \src "libresoc.v:185002.17-185002.96" + wire $and$libresoc.v:185002$11909_Y + attribute \src "libresoc.v:184999.18-184999.94" + wire $not$libresoc.v:184999$11906_Y + attribute \src "libresoc.v:185001.17-185001.93" + wire $not$libresoc.v:185001$11908_Y + attribute \src "libresoc.v:185004.17-185004.93" + wire $not$libresoc.v:185004$11911_Y + attribute \src "libresoc.v:184998.18-184998.99" + wire $or$libresoc.v:184998$11905_Y + attribute \src "libresoc.v:185000.18-185000.100" + wire $or$libresoc.v:185000$11907_Y + attribute \src "libresoc.v:185003.17-185003.98" + wire $or$libresoc.v:185003$11910_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382201,11 +347181,11 @@ module \rok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:184914.7-184914.15" + attribute \src "libresoc.v:184962.7-184962.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382222,7 +347202,7 @@ module \rok_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184949$12108 + cell $and $and$libresoc.v:184997$11904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382230,10 +347210,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184949$12108_Y + connect \Y $and$libresoc.v:184997$11904_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184954$12113 + cell $and $and$libresoc.v:185002$11909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382241,34 +347221,34 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184954$12113_Y + connect \Y $and$libresoc.v:185002$11909_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184951$12110 + cell $not $not$libresoc.v:184999$11906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:184951$12110_Y + connect \Y $not$libresoc.v:184999$11906_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184953$12112 + cell $not $not$libresoc.v:185001$11908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:184953$12112_Y + connect \Y $not$libresoc.v:185001$11908_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184956$12115 + cell $not $not$libresoc.v:185004$11911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:184956$12115_Y + connect \Y $not$libresoc.v:185004$11911_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184950$12109 + cell $or $or$libresoc.v:184998$11905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382276,10 +347256,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:184950$12109_Y + connect \Y $or$libresoc.v:184998$11905_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184952$12111 + cell $or $or$libresoc.v:185000$11907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382287,10 +347267,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:184952$12111_Y + connect \Y $or$libresoc.v:185000$11907_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184955$12114 + cell $or $or$libresoc.v:185003$11910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382298,39 +347278,39 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:184955$12114_Y + connect \Y $or$libresoc.v:185003$11910_Y end - attribute \src "libresoc.v:184914.7-184914.20" - process $proc$libresoc.v:184914$12120 + attribute \src "libresoc.v:184962.7-184962.20" + process $proc$libresoc.v:184962$11916 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184936.7-184936.19" - process $proc$libresoc.v:184936$12121 + attribute \src "libresoc.v:184984.7-184984.19" + process $proc$libresoc.v:184984$11917 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184957.3-184958.27" - process $proc$libresoc.v:184957$12116 + attribute \src "libresoc.v:185005.3-185006.27" + process $proc$libresoc.v:185005$11912 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184959.3-184967.6" - process $proc$libresoc.v:184959$12117 + attribute \src "libresoc.v:185007.3-185015.6" + process $proc$libresoc.v:185007$11913 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12118 $1\q_int$next[0:0]$12119 - attribute \src "libresoc.v:184960.5-184960.29" + assign $0\q_int$next[0:0]$11914 $1\q_int$next[0:0]$11915 + attribute \src "libresoc.v:185008.5-185008.29" switch \initial - attribute \src "libresoc.v:184960.9-184960.17" + attribute \src "libresoc.v:185008.9-185008.17" case 1'1 case end @@ -382339,56 +347319,56 @@ module \rok_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12119 1'0 + assign $1\q_int$next[0:0]$11915 1'0 case - assign $1\q_int$next[0:0]$12119 \$5 + assign $1\q_int$next[0:0]$11915 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12118 + update \q_int$next $0\q_int$next[0:0]$11914 end - connect \$9 $and$libresoc.v:184949$12108_Y - connect \$11 $or$libresoc.v:184950$12109_Y - connect \$13 $not$libresoc.v:184951$12110_Y - connect \$15 $or$libresoc.v:184952$12111_Y - connect \$1 $not$libresoc.v:184953$12112_Y - connect \$3 $and$libresoc.v:184954$12113_Y - connect \$5 $or$libresoc.v:184955$12114_Y - connect \$7 $not$libresoc.v:184956$12115_Y + connect \$9 $and$libresoc.v:184997$11904_Y + connect \$11 $or$libresoc.v:184998$11905_Y + connect \$13 $not$libresoc.v:184999$11906_Y + connect \$15 $or$libresoc.v:185000$11907_Y + connect \$1 $not$libresoc.v:185001$11908_Y + connect \$3 $and$libresoc.v:185002$11909_Y + connect \$5 $or$libresoc.v:185003$11910_Y + connect \$7 $not$libresoc.v:185004$11911_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:184975.1-185033.10" +attribute \src "libresoc.v:185023.1-185081.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l" attribute \generator "nMigen" module \rok_l$105 - attribute \src "libresoc.v:184976.7-184976.20" + attribute \src "libresoc.v:185024.7-185024.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185021.3-185029.6" - wire $0\q_int$next[0:0]$12132 - attribute \src "libresoc.v:185019.3-185020.27" + attribute \src "libresoc.v:185069.3-185077.6" + wire $0\q_int$next[0:0]$11928 + attribute \src "libresoc.v:185067.3-185068.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185021.3-185029.6" - wire $1\q_int$next[0:0]$12133 - attribute \src "libresoc.v:184998.7-184998.19" + attribute \src "libresoc.v:185069.3-185077.6" + wire $1\q_int$next[0:0]$11929 + attribute \src "libresoc.v:185046.7-185046.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185011.17-185011.96" - wire $and$libresoc.v:185011$12122_Y - attribute \src "libresoc.v:185016.17-185016.96" - wire $and$libresoc.v:185016$12127_Y - attribute \src "libresoc.v:185013.18-185013.94" - wire $not$libresoc.v:185013$12124_Y - attribute \src "libresoc.v:185015.17-185015.93" - wire $not$libresoc.v:185015$12126_Y - attribute \src "libresoc.v:185018.17-185018.93" - wire $not$libresoc.v:185018$12129_Y - attribute \src "libresoc.v:185012.18-185012.99" - wire $or$libresoc.v:185012$12123_Y - attribute \src "libresoc.v:185014.18-185014.100" - wire $or$libresoc.v:185014$12125_Y - attribute \src "libresoc.v:185017.17-185017.98" - wire $or$libresoc.v:185017$12128_Y + attribute \src "libresoc.v:185059.17-185059.96" + wire $and$libresoc.v:185059$11918_Y + attribute \src "libresoc.v:185064.17-185064.96" + wire $and$libresoc.v:185064$11923_Y + attribute \src "libresoc.v:185061.18-185061.94" + wire $not$libresoc.v:185061$11920_Y + attribute \src "libresoc.v:185063.17-185063.93" + wire $not$libresoc.v:185063$11922_Y + attribute \src "libresoc.v:185066.17-185066.93" + wire $not$libresoc.v:185066$11925_Y + attribute \src "libresoc.v:185060.18-185060.99" + wire $or$libresoc.v:185060$11919_Y + attribute \src "libresoc.v:185062.18-185062.100" + wire $or$libresoc.v:185062$11921_Y + attribute \src "libresoc.v:185065.17-185065.98" + wire $or$libresoc.v:185065$11924_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382405,11 +347385,11 @@ module \rok_l$105 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:184976.7-184976.15" + attribute \src "libresoc.v:185024.7-185024.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382426,7 +347406,7 @@ module \rok_l$105 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185011$12122 + cell $and $and$libresoc.v:185059$11918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382434,10 +347414,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185011$12122_Y + connect \Y $and$libresoc.v:185059$11918_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185016$12127 + cell $and $and$libresoc.v:185064$11923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382445,34 +347425,34 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185016$12127_Y + connect \Y $and$libresoc.v:185064$11923_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185013$12124 + cell $not $not$libresoc.v:185061$11920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185013$12124_Y + connect \Y $not$libresoc.v:185061$11920_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185015$12126 + cell $not $not$libresoc.v:185063$11922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185015$12126_Y + connect \Y $not$libresoc.v:185063$11922_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185018$12129 + cell $not $not$libresoc.v:185066$11925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185018$12129_Y + connect \Y $not$libresoc.v:185066$11925_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185012$12123 + cell $or $or$libresoc.v:185060$11919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382480,10 +347460,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185012$12123_Y + connect \Y $or$libresoc.v:185060$11919_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185014$12125 + cell $or $or$libresoc.v:185062$11921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382491,10 +347471,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185014$12125_Y + connect \Y $or$libresoc.v:185062$11921_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185017$12128 + cell $or $or$libresoc.v:185065$11924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382502,39 +347482,39 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185017$12128_Y + connect \Y $or$libresoc.v:185065$11924_Y end - attribute \src "libresoc.v:184976.7-184976.20" - process $proc$libresoc.v:184976$12134 + attribute \src "libresoc.v:185024.7-185024.20" + process $proc$libresoc.v:185024$11930 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184998.7-184998.19" - process $proc$libresoc.v:184998$12135 + attribute \src "libresoc.v:185046.7-185046.19" + process $proc$libresoc.v:185046$11931 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185019.3-185020.27" - process $proc$libresoc.v:185019$12130 + attribute \src "libresoc.v:185067.3-185068.27" + process $proc$libresoc.v:185067$11926 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185021.3-185029.6" - process $proc$libresoc.v:185021$12131 + attribute \src "libresoc.v:185069.3-185077.6" + process $proc$libresoc.v:185069$11927 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12132 $1\q_int$next[0:0]$12133 - attribute \src "libresoc.v:185022.5-185022.29" + assign $0\q_int$next[0:0]$11928 $1\q_int$next[0:0]$11929 + attribute \src "libresoc.v:185070.5-185070.29" switch \initial - attribute \src "libresoc.v:185022.9-185022.17" + attribute \src "libresoc.v:185070.9-185070.17" case 1'1 case end @@ -382543,56 +347523,56 @@ module \rok_l$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12133 1'0 + assign $1\q_int$next[0:0]$11929 1'0 case - assign $1\q_int$next[0:0]$12133 \$5 + assign $1\q_int$next[0:0]$11929 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12132 + update \q_int$next $0\q_int$next[0:0]$11928 end - connect \$9 $and$libresoc.v:185011$12122_Y - connect \$11 $or$libresoc.v:185012$12123_Y - connect \$13 $not$libresoc.v:185013$12124_Y - connect \$15 $or$libresoc.v:185014$12125_Y - connect \$1 $not$libresoc.v:185015$12126_Y - connect \$3 $and$libresoc.v:185016$12127_Y - connect \$5 $or$libresoc.v:185017$12128_Y - connect \$7 $not$libresoc.v:185018$12129_Y + connect \$9 $and$libresoc.v:185059$11918_Y + connect \$11 $or$libresoc.v:185060$11919_Y + connect \$13 $not$libresoc.v:185061$11920_Y + connect \$15 $or$libresoc.v:185062$11921_Y + connect \$1 $not$libresoc.v:185063$11922_Y + connect \$3 $and$libresoc.v:185064$11923_Y + connect \$5 $or$libresoc.v:185065$11924_Y + connect \$7 $not$libresoc.v:185066$11925_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185037.1-185095.10" +attribute \src "libresoc.v:185085.1-185143.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l" attribute \generator "nMigen" module \rok_l$123 - attribute \src "libresoc.v:185038.7-185038.20" + attribute \src "libresoc.v:185086.7-185086.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185083.3-185091.6" - wire $0\q_int$next[0:0]$12146 - attribute \src "libresoc.v:185081.3-185082.27" + attribute \src "libresoc.v:185131.3-185139.6" + wire $0\q_int$next[0:0]$11942 + attribute \src "libresoc.v:185129.3-185130.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185083.3-185091.6" - wire $1\q_int$next[0:0]$12147 - attribute \src "libresoc.v:185060.7-185060.19" + attribute \src "libresoc.v:185131.3-185139.6" + wire $1\q_int$next[0:0]$11943 + attribute \src "libresoc.v:185108.7-185108.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185073.17-185073.96" - wire $and$libresoc.v:185073$12136_Y - attribute \src "libresoc.v:185078.17-185078.96" - wire $and$libresoc.v:185078$12141_Y - attribute \src "libresoc.v:185075.18-185075.94" - wire $not$libresoc.v:185075$12138_Y - attribute \src "libresoc.v:185077.17-185077.93" - wire $not$libresoc.v:185077$12140_Y - attribute \src "libresoc.v:185080.17-185080.93" - wire $not$libresoc.v:185080$12143_Y - attribute \src "libresoc.v:185074.18-185074.99" - wire $or$libresoc.v:185074$12137_Y - attribute \src "libresoc.v:185076.18-185076.100" - wire $or$libresoc.v:185076$12139_Y - attribute \src "libresoc.v:185079.17-185079.98" - wire $or$libresoc.v:185079$12142_Y + attribute \src "libresoc.v:185121.17-185121.96" + wire $and$libresoc.v:185121$11932_Y + attribute \src "libresoc.v:185126.17-185126.96" + wire $and$libresoc.v:185126$11937_Y + attribute \src "libresoc.v:185123.18-185123.94" + wire $not$libresoc.v:185123$11934_Y + attribute \src "libresoc.v:185125.17-185125.93" + wire $not$libresoc.v:185125$11936_Y + attribute \src "libresoc.v:185128.17-185128.93" + wire $not$libresoc.v:185128$11939_Y + attribute \src "libresoc.v:185122.18-185122.99" + wire $or$libresoc.v:185122$11933_Y + attribute \src "libresoc.v:185124.18-185124.100" + wire $or$libresoc.v:185124$11935_Y + attribute \src "libresoc.v:185127.17-185127.98" + wire $or$libresoc.v:185127$11938_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382609,11 +347589,11 @@ module \rok_l$123 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:185038.7-185038.15" + attribute \src "libresoc.v:185086.7-185086.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382630,7 +347610,7 @@ module \rok_l$123 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185073$12136 + cell $and $and$libresoc.v:185121$11932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382638,10 +347618,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185073$12136_Y + connect \Y $and$libresoc.v:185121$11932_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185078$12141 + cell $and $and$libresoc.v:185126$11937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382649,34 +347629,34 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185078$12141_Y + connect \Y $and$libresoc.v:185126$11937_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185075$12138 + cell $not $not$libresoc.v:185123$11934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185075$12138_Y + connect \Y $not$libresoc.v:185123$11934_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185077$12140 + cell $not $not$libresoc.v:185125$11936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185077$12140_Y + connect \Y $not$libresoc.v:185125$11936_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185080$12143 + cell $not $not$libresoc.v:185128$11939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185080$12143_Y + connect \Y $not$libresoc.v:185128$11939_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185074$12137 + cell $or $or$libresoc.v:185122$11933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382684,10 +347664,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185074$12137_Y + connect \Y $or$libresoc.v:185122$11933_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185076$12139 + cell $or $or$libresoc.v:185124$11935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382695,10 +347675,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185076$12139_Y + connect \Y $or$libresoc.v:185124$11935_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185079$12142 + cell $or $or$libresoc.v:185127$11938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382706,39 +347686,39 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185079$12142_Y + connect \Y $or$libresoc.v:185127$11938_Y end - attribute \src "libresoc.v:185038.7-185038.20" - process $proc$libresoc.v:185038$12148 + attribute \src "libresoc.v:185086.7-185086.20" + process $proc$libresoc.v:185086$11944 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185060.7-185060.19" - process $proc$libresoc.v:185060$12149 + attribute \src "libresoc.v:185108.7-185108.19" + process $proc$libresoc.v:185108$11945 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185081.3-185082.27" - process $proc$libresoc.v:185081$12144 + attribute \src "libresoc.v:185129.3-185130.27" + process $proc$libresoc.v:185129$11940 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185083.3-185091.6" - process $proc$libresoc.v:185083$12145 + attribute \src "libresoc.v:185131.3-185139.6" + process $proc$libresoc.v:185131$11941 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12146 $1\q_int$next[0:0]$12147 - attribute \src "libresoc.v:185084.5-185084.29" + assign $0\q_int$next[0:0]$11942 $1\q_int$next[0:0]$11943 + attribute \src "libresoc.v:185132.5-185132.29" switch \initial - attribute \src "libresoc.v:185084.9-185084.17" + attribute \src "libresoc.v:185132.9-185132.17" case 1'1 case end @@ -382747,56 +347727,56 @@ module \rok_l$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12147 1'0 + assign $1\q_int$next[0:0]$11943 1'0 case - assign $1\q_int$next[0:0]$12147 \$5 + assign $1\q_int$next[0:0]$11943 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12146 + update \q_int$next $0\q_int$next[0:0]$11942 end - connect \$9 $and$libresoc.v:185073$12136_Y - connect \$11 $or$libresoc.v:185074$12137_Y - connect \$13 $not$libresoc.v:185075$12138_Y - connect \$15 $or$libresoc.v:185076$12139_Y - connect \$1 $not$libresoc.v:185077$12140_Y - connect \$3 $and$libresoc.v:185078$12141_Y - connect \$5 $or$libresoc.v:185079$12142_Y - connect \$7 $not$libresoc.v:185080$12143_Y + connect \$9 $and$libresoc.v:185121$11932_Y + connect \$11 $or$libresoc.v:185122$11933_Y + connect \$13 $not$libresoc.v:185123$11934_Y + connect \$15 $or$libresoc.v:185124$11935_Y + connect \$1 $not$libresoc.v:185125$11936_Y + connect \$3 $and$libresoc.v:185126$11937_Y + connect \$5 $or$libresoc.v:185127$11938_Y + connect \$7 $not$libresoc.v:185128$11939_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185099.1-185157.10" +attribute \src "libresoc.v:185147.1-185205.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" attribute \generator "nMigen" module \rok_l$14 - attribute \src "libresoc.v:185100.7-185100.20" + attribute \src "libresoc.v:185148.7-185148.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185145.3-185153.6" - wire $0\q_int$next[0:0]$12160 - attribute \src "libresoc.v:185143.3-185144.27" + attribute \src "libresoc.v:185193.3-185201.6" + wire $0\q_int$next[0:0]$11956 + attribute \src "libresoc.v:185191.3-185192.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185145.3-185153.6" - wire $1\q_int$next[0:0]$12161 - attribute \src "libresoc.v:185122.7-185122.19" + attribute \src "libresoc.v:185193.3-185201.6" + wire $1\q_int$next[0:0]$11957 + attribute \src "libresoc.v:185170.7-185170.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185135.17-185135.96" - wire $and$libresoc.v:185135$12150_Y - attribute \src "libresoc.v:185140.17-185140.96" - wire $and$libresoc.v:185140$12155_Y - attribute \src "libresoc.v:185137.18-185137.94" - wire $not$libresoc.v:185137$12152_Y - attribute \src "libresoc.v:185139.17-185139.93" - wire $not$libresoc.v:185139$12154_Y - attribute \src "libresoc.v:185142.17-185142.93" - wire $not$libresoc.v:185142$12157_Y - attribute \src "libresoc.v:185136.18-185136.99" - wire $or$libresoc.v:185136$12151_Y - attribute \src "libresoc.v:185138.18-185138.100" - wire $or$libresoc.v:185138$12153_Y - attribute \src "libresoc.v:185141.17-185141.98" - wire $or$libresoc.v:185141$12156_Y + attribute \src "libresoc.v:185183.17-185183.96" + wire $and$libresoc.v:185183$11946_Y + attribute \src "libresoc.v:185188.17-185188.96" + wire $and$libresoc.v:185188$11951_Y + attribute \src "libresoc.v:185185.18-185185.94" + wire $not$libresoc.v:185185$11948_Y + attribute \src "libresoc.v:185187.17-185187.93" + wire $not$libresoc.v:185187$11950_Y + attribute \src "libresoc.v:185190.17-185190.93" + wire $not$libresoc.v:185190$11953_Y + attribute \src "libresoc.v:185184.18-185184.99" + wire $or$libresoc.v:185184$11947_Y + attribute \src "libresoc.v:185186.18-185186.100" + wire $or$libresoc.v:185186$11949_Y + attribute \src "libresoc.v:185189.17-185189.98" + wire $or$libresoc.v:185189$11952_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382813,11 +347793,11 @@ module \rok_l$14 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:185100.7-185100.15" + attribute \src "libresoc.v:185148.7-185148.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382834,7 +347814,7 @@ module \rok_l$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185135$12150 + cell $and $and$libresoc.v:185183$11946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382842,10 +347822,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185135$12150_Y + connect \Y $and$libresoc.v:185183$11946_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185140$12155 + cell $and $and$libresoc.v:185188$11951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382853,34 +347833,34 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185140$12155_Y + connect \Y $and$libresoc.v:185188$11951_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185137$12152 + cell $not $not$libresoc.v:185185$11948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185137$12152_Y + connect \Y $not$libresoc.v:185185$11948_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185139$12154 + cell $not $not$libresoc.v:185187$11950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185139$12154_Y + connect \Y $not$libresoc.v:185187$11950_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185142$12157 + cell $not $not$libresoc.v:185190$11953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185142$12157_Y + connect \Y $not$libresoc.v:185190$11953_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185136$12151 + cell $or $or$libresoc.v:185184$11947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382888,10 +347868,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185136$12151_Y + connect \Y $or$libresoc.v:185184$11947_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185138$12153 + cell $or $or$libresoc.v:185186$11949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382899,10 +347879,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185138$12153_Y + connect \Y $or$libresoc.v:185186$11949_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185141$12156 + cell $or $or$libresoc.v:185189$11952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382910,39 +347890,39 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185141$12156_Y + connect \Y $or$libresoc.v:185189$11952_Y end - attribute \src "libresoc.v:185100.7-185100.20" - process $proc$libresoc.v:185100$12162 + attribute \src "libresoc.v:185148.7-185148.20" + process $proc$libresoc.v:185148$11958 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185122.7-185122.19" - process $proc$libresoc.v:185122$12163 + attribute \src "libresoc.v:185170.7-185170.19" + process $proc$libresoc.v:185170$11959 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185143.3-185144.27" - process $proc$libresoc.v:185143$12158 + attribute \src "libresoc.v:185191.3-185192.27" + process $proc$libresoc.v:185191$11954 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185145.3-185153.6" - process $proc$libresoc.v:185145$12159 + attribute \src "libresoc.v:185193.3-185201.6" + process $proc$libresoc.v:185193$11955 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12160 $1\q_int$next[0:0]$12161 - attribute \src "libresoc.v:185146.5-185146.29" + assign $0\q_int$next[0:0]$11956 $1\q_int$next[0:0]$11957 + attribute \src "libresoc.v:185194.5-185194.29" switch \initial - attribute \src "libresoc.v:185146.9-185146.17" + attribute \src "libresoc.v:185194.9-185194.17" case 1'1 case end @@ -382951,56 +347931,56 @@ module \rok_l$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12161 1'0 + assign $1\q_int$next[0:0]$11957 1'0 case - assign $1\q_int$next[0:0]$12161 \$5 + assign $1\q_int$next[0:0]$11957 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12160 + update \q_int$next $0\q_int$next[0:0]$11956 end - connect \$9 $and$libresoc.v:185135$12150_Y - connect \$11 $or$libresoc.v:185136$12151_Y - connect \$13 $not$libresoc.v:185137$12152_Y - connect \$15 $or$libresoc.v:185138$12153_Y - connect \$1 $not$libresoc.v:185139$12154_Y - connect \$3 $and$libresoc.v:185140$12155_Y - connect \$5 $or$libresoc.v:185141$12156_Y - connect \$7 $not$libresoc.v:185142$12157_Y + connect \$9 $and$libresoc.v:185183$11946_Y + connect \$11 $or$libresoc.v:185184$11947_Y + connect \$13 $not$libresoc.v:185185$11948_Y + connect \$15 $or$libresoc.v:185186$11949_Y + connect \$1 $not$libresoc.v:185187$11950_Y + connect \$3 $and$libresoc.v:185188$11951_Y + connect \$5 $or$libresoc.v:185189$11952_Y + connect \$7 $not$libresoc.v:185190$11953_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185161.1-185219.10" +attribute \src "libresoc.v:185209.1-185267.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" attribute \generator "nMigen" module \rok_l$27 - attribute \src "libresoc.v:185162.7-185162.20" + attribute \src "libresoc.v:185210.7-185210.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185207.3-185215.6" - wire $0\q_int$next[0:0]$12174 - attribute \src "libresoc.v:185205.3-185206.27" + attribute \src "libresoc.v:185255.3-185263.6" + wire $0\q_int$next[0:0]$11970 + attribute \src "libresoc.v:185253.3-185254.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185207.3-185215.6" - wire $1\q_int$next[0:0]$12175 - attribute \src "libresoc.v:185184.7-185184.19" + attribute \src "libresoc.v:185255.3-185263.6" + wire $1\q_int$next[0:0]$11971 + attribute \src "libresoc.v:185232.7-185232.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185197.17-185197.96" - wire $and$libresoc.v:185197$12164_Y - attribute \src "libresoc.v:185202.17-185202.96" - wire $and$libresoc.v:185202$12169_Y - attribute \src "libresoc.v:185199.18-185199.94" - wire $not$libresoc.v:185199$12166_Y - attribute \src "libresoc.v:185201.17-185201.93" - wire $not$libresoc.v:185201$12168_Y - attribute \src "libresoc.v:185204.17-185204.93" - wire $not$libresoc.v:185204$12171_Y - attribute \src "libresoc.v:185198.18-185198.99" - wire $or$libresoc.v:185198$12165_Y - attribute \src "libresoc.v:185200.18-185200.100" - wire $or$libresoc.v:185200$12167_Y - attribute \src "libresoc.v:185203.17-185203.98" - wire $or$libresoc.v:185203$12170_Y + attribute \src "libresoc.v:185245.17-185245.96" + wire $and$libresoc.v:185245$11960_Y + attribute \src "libresoc.v:185250.17-185250.96" + wire $and$libresoc.v:185250$11965_Y + attribute \src "libresoc.v:185247.18-185247.94" + wire $not$libresoc.v:185247$11962_Y + attribute \src "libresoc.v:185249.17-185249.93" + wire $not$libresoc.v:185249$11964_Y + attribute \src "libresoc.v:185252.17-185252.93" + wire $not$libresoc.v:185252$11967_Y + attribute \src "libresoc.v:185246.18-185246.99" + wire $or$libresoc.v:185246$11961_Y + attribute \src "libresoc.v:185248.18-185248.100" + wire $or$libresoc.v:185248$11963_Y + attribute \src "libresoc.v:185251.17-185251.98" + wire $or$libresoc.v:185251$11966_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -383017,11 +347997,11 @@ module \rok_l$27 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:185162.7-185162.15" + attribute \src "libresoc.v:185210.7-185210.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -383038,7 +348018,7 @@ module \rok_l$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185197$12164 + cell $and $and$libresoc.v:185245$11960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383046,10 +348026,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185197$12164_Y + connect \Y $and$libresoc.v:185245$11960_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185202$12169 + cell $and $and$libresoc.v:185250$11965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383057,34 +348037,34 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185202$12169_Y + connect \Y $and$libresoc.v:185250$11965_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185199$12166 + cell $not $not$libresoc.v:185247$11962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185199$12166_Y + connect \Y $not$libresoc.v:185247$11962_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185201$12168 + cell $not $not$libresoc.v:185249$11964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185201$12168_Y + connect \Y $not$libresoc.v:185249$11964_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185204$12171 + cell $not $not$libresoc.v:185252$11967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185204$12171_Y + connect \Y $not$libresoc.v:185252$11967_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185198$12165 + cell $or $or$libresoc.v:185246$11961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383092,10 +348072,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185198$12165_Y + connect \Y $or$libresoc.v:185246$11961_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185200$12167 + cell $or $or$libresoc.v:185248$11963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383103,10 +348083,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185200$12167_Y + connect \Y $or$libresoc.v:185248$11963_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185203$12170 + cell $or $or$libresoc.v:185251$11966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383114,39 +348094,39 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185203$12170_Y + connect \Y $or$libresoc.v:185251$11966_Y end - attribute \src "libresoc.v:185162.7-185162.20" - process $proc$libresoc.v:185162$12176 + attribute \src "libresoc.v:185210.7-185210.20" + process $proc$libresoc.v:185210$11972 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185184.7-185184.19" - process $proc$libresoc.v:185184$12177 + attribute \src "libresoc.v:185232.7-185232.19" + process $proc$libresoc.v:185232$11973 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185205.3-185206.27" - process $proc$libresoc.v:185205$12172 + attribute \src "libresoc.v:185253.3-185254.27" + process $proc$libresoc.v:185253$11968 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185207.3-185215.6" - process $proc$libresoc.v:185207$12173 + attribute \src "libresoc.v:185255.3-185263.6" + process $proc$libresoc.v:185255$11969 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12174 $1\q_int$next[0:0]$12175 - attribute \src "libresoc.v:185208.5-185208.29" + assign $0\q_int$next[0:0]$11970 $1\q_int$next[0:0]$11971 + attribute \src "libresoc.v:185256.5-185256.29" switch \initial - attribute \src "libresoc.v:185208.9-185208.17" + attribute \src "libresoc.v:185256.9-185256.17" case 1'1 case end @@ -383155,56 +348135,56 @@ module \rok_l$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12175 1'0 + assign $1\q_int$next[0:0]$11971 1'0 case - assign $1\q_int$next[0:0]$12175 \$5 + assign $1\q_int$next[0:0]$11971 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12174 + update \q_int$next $0\q_int$next[0:0]$11970 end - connect \$9 $and$libresoc.v:185197$12164_Y - connect \$11 $or$libresoc.v:185198$12165_Y - connect \$13 $not$libresoc.v:185199$12166_Y - connect \$15 $or$libresoc.v:185200$12167_Y - connect \$1 $not$libresoc.v:185201$12168_Y - connect \$3 $and$libresoc.v:185202$12169_Y - connect \$5 $or$libresoc.v:185203$12170_Y - connect \$7 $not$libresoc.v:185204$12171_Y + connect \$9 $and$libresoc.v:185245$11960_Y + connect \$11 $or$libresoc.v:185246$11961_Y + connect \$13 $not$libresoc.v:185247$11962_Y + connect \$15 $or$libresoc.v:185248$11963_Y + connect \$1 $not$libresoc.v:185249$11964_Y + connect \$3 $and$libresoc.v:185250$11965_Y + connect \$5 $or$libresoc.v:185251$11966_Y + connect \$7 $not$libresoc.v:185252$11967_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185223.1-185281.10" +attribute \src "libresoc.v:185271.1-185329.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" attribute \generator "nMigen" module \rok_l$43 - attribute \src "libresoc.v:185224.7-185224.20" + attribute \src "libresoc.v:185272.7-185272.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185269.3-185277.6" - wire $0\q_int$next[0:0]$12188 - attribute \src "libresoc.v:185267.3-185268.27" + attribute \src "libresoc.v:185317.3-185325.6" + wire $0\q_int$next[0:0]$11984 + attribute \src "libresoc.v:185315.3-185316.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185269.3-185277.6" - wire $1\q_int$next[0:0]$12189 - attribute \src "libresoc.v:185246.7-185246.19" + attribute \src "libresoc.v:185317.3-185325.6" + wire $1\q_int$next[0:0]$11985 + attribute \src "libresoc.v:185294.7-185294.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185259.17-185259.96" - wire $and$libresoc.v:185259$12178_Y - attribute \src "libresoc.v:185264.17-185264.96" - wire $and$libresoc.v:185264$12183_Y - attribute \src "libresoc.v:185261.18-185261.94" - wire $not$libresoc.v:185261$12180_Y - attribute \src "libresoc.v:185263.17-185263.93" - wire $not$libresoc.v:185263$12182_Y - attribute \src "libresoc.v:185266.17-185266.93" - wire $not$libresoc.v:185266$12185_Y - attribute \src "libresoc.v:185260.18-185260.99" - wire $or$libresoc.v:185260$12179_Y - attribute \src "libresoc.v:185262.18-185262.100" - wire $or$libresoc.v:185262$12181_Y - attribute \src "libresoc.v:185265.17-185265.98" - wire $or$libresoc.v:185265$12184_Y + attribute \src "libresoc.v:185307.17-185307.96" + wire $and$libresoc.v:185307$11974_Y + attribute \src "libresoc.v:185312.17-185312.96" + wire $and$libresoc.v:185312$11979_Y + attribute \src "libresoc.v:185309.18-185309.94" + wire $not$libresoc.v:185309$11976_Y + attribute \src "libresoc.v:185311.17-185311.93" + wire $not$libresoc.v:185311$11978_Y + attribute \src "libresoc.v:185314.17-185314.93" + wire $not$libresoc.v:185314$11981_Y + attribute \src "libresoc.v:185308.18-185308.99" + wire $or$libresoc.v:185308$11975_Y + attribute \src "libresoc.v:185310.18-185310.100" + wire $or$libresoc.v:185310$11977_Y + attribute \src "libresoc.v:185313.17-185313.98" + wire $or$libresoc.v:185313$11980_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -383221,11 +348201,11 @@ module \rok_l$43 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:185224.7-185224.15" + attribute \src "libresoc.v:185272.7-185272.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -383242,7 +348222,7 @@ module \rok_l$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185259$12178 + cell $and $and$libresoc.v:185307$11974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383250,10 +348230,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185259$12178_Y + connect \Y $and$libresoc.v:185307$11974_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185264$12183 + cell $and $and$libresoc.v:185312$11979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383261,34 +348241,34 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185264$12183_Y + connect \Y $and$libresoc.v:185312$11979_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185261$12180 + cell $not $not$libresoc.v:185309$11976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185261$12180_Y + connect \Y $not$libresoc.v:185309$11976_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185263$12182 + cell $not $not$libresoc.v:185311$11978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185263$12182_Y + connect \Y $not$libresoc.v:185311$11978_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185266$12185 + cell $not $not$libresoc.v:185314$11981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185266$12185_Y + connect \Y $not$libresoc.v:185314$11981_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185260$12179 + cell $or $or$libresoc.v:185308$11975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383296,10 +348276,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185260$12179_Y + connect \Y $or$libresoc.v:185308$11975_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185262$12181 + cell $or $or$libresoc.v:185310$11977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383307,10 +348287,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185262$12181_Y + connect \Y $or$libresoc.v:185310$11977_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185265$12184 + cell $or $or$libresoc.v:185313$11980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383318,39 +348298,39 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185265$12184_Y + connect \Y $or$libresoc.v:185313$11980_Y end - attribute \src "libresoc.v:185224.7-185224.20" - process $proc$libresoc.v:185224$12190 + attribute \src "libresoc.v:185272.7-185272.20" + process $proc$libresoc.v:185272$11986 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185246.7-185246.19" - process $proc$libresoc.v:185246$12191 + attribute \src "libresoc.v:185294.7-185294.19" + process $proc$libresoc.v:185294$11987 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185267.3-185268.27" - process $proc$libresoc.v:185267$12186 + attribute \src "libresoc.v:185315.3-185316.27" + process $proc$libresoc.v:185315$11982 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185269.3-185277.6" - process $proc$libresoc.v:185269$12187 + attribute \src "libresoc.v:185317.3-185325.6" + process $proc$libresoc.v:185317$11983 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12188 $1\q_int$next[0:0]$12189 - attribute \src "libresoc.v:185270.5-185270.29" + assign $0\q_int$next[0:0]$11984 $1\q_int$next[0:0]$11985 + attribute \src "libresoc.v:185318.5-185318.29" switch \initial - attribute \src "libresoc.v:185270.9-185270.17" + attribute \src "libresoc.v:185318.9-185318.17" case 1'1 case end @@ -383359,56 +348339,56 @@ module \rok_l$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12189 1'0 + assign $1\q_int$next[0:0]$11985 1'0 case - assign $1\q_int$next[0:0]$12189 \$5 + assign $1\q_int$next[0:0]$11985 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12188 + update \q_int$next $0\q_int$next[0:0]$11984 end - connect \$9 $and$libresoc.v:185259$12178_Y - connect \$11 $or$libresoc.v:185260$12179_Y - connect \$13 $not$libresoc.v:185261$12180_Y - connect \$15 $or$libresoc.v:185262$12181_Y - connect \$1 $not$libresoc.v:185263$12182_Y - connect \$3 $and$libresoc.v:185264$12183_Y - connect \$5 $or$libresoc.v:185265$12184_Y - connect \$7 $not$libresoc.v:185266$12185_Y + connect \$9 $and$libresoc.v:185307$11974_Y + connect \$11 $or$libresoc.v:185308$11975_Y + connect \$13 $not$libresoc.v:185309$11976_Y + connect \$15 $or$libresoc.v:185310$11977_Y + connect \$1 $not$libresoc.v:185311$11978_Y + connect \$3 $and$libresoc.v:185312$11979_Y + connect \$5 $or$libresoc.v:185313$11980_Y + connect \$7 $not$libresoc.v:185314$11981_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185285.1-185343.10" +attribute \src "libresoc.v:185333.1-185391.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" attribute \generator "nMigen" module \rok_l$59 - attribute \src "libresoc.v:185286.7-185286.20" + attribute \src "libresoc.v:185334.7-185334.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185331.3-185339.6" - wire $0\q_int$next[0:0]$12202 - attribute \src "libresoc.v:185329.3-185330.27" + attribute \src "libresoc.v:185379.3-185387.6" + wire $0\q_int$next[0:0]$11998 + attribute \src "libresoc.v:185377.3-185378.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185331.3-185339.6" - wire $1\q_int$next[0:0]$12203 - attribute \src "libresoc.v:185308.7-185308.19" + attribute \src "libresoc.v:185379.3-185387.6" + wire $1\q_int$next[0:0]$11999 + attribute \src "libresoc.v:185356.7-185356.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185321.17-185321.96" - wire $and$libresoc.v:185321$12192_Y - attribute \src "libresoc.v:185326.17-185326.96" - wire $and$libresoc.v:185326$12197_Y - attribute \src "libresoc.v:185323.18-185323.94" - wire $not$libresoc.v:185323$12194_Y - attribute \src "libresoc.v:185325.17-185325.93" - wire $not$libresoc.v:185325$12196_Y - attribute \src "libresoc.v:185328.17-185328.93" - wire $not$libresoc.v:185328$12199_Y - attribute \src "libresoc.v:185322.18-185322.99" - wire $or$libresoc.v:185322$12193_Y - attribute \src "libresoc.v:185324.18-185324.100" - wire $or$libresoc.v:185324$12195_Y - attribute \src "libresoc.v:185327.17-185327.98" - wire $or$libresoc.v:185327$12198_Y + attribute \src "libresoc.v:185369.17-185369.96" + wire $and$libresoc.v:185369$11988_Y + attribute \src "libresoc.v:185374.17-185374.96" + wire $and$libresoc.v:185374$11993_Y + attribute \src "libresoc.v:185371.18-185371.94" + wire $not$libresoc.v:185371$11990_Y + attribute \src "libresoc.v:185373.17-185373.93" + wire $not$libresoc.v:185373$11992_Y + attribute \src "libresoc.v:185376.17-185376.93" + wire $not$libresoc.v:185376$11995_Y + attribute \src "libresoc.v:185370.18-185370.99" + wire $or$libresoc.v:185370$11989_Y + attribute \src "libresoc.v:185372.18-185372.100" + wire $or$libresoc.v:185372$11991_Y + attribute \src "libresoc.v:185375.17-185375.98" + wire $or$libresoc.v:185375$11994_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -383425,11 +348405,11 @@ module \rok_l$59 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:185286.7-185286.15" + attribute \src "libresoc.v:185334.7-185334.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -383446,7 +348426,7 @@ module \rok_l$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185321$12192 + cell $and $and$libresoc.v:185369$11988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383454,10 +348434,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185321$12192_Y + connect \Y $and$libresoc.v:185369$11988_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185326$12197 + cell $and $and$libresoc.v:185374$11993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383465,34 +348445,34 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185326$12197_Y + connect \Y $and$libresoc.v:185374$11993_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185323$12194 + cell $not $not$libresoc.v:185371$11990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185323$12194_Y + connect \Y $not$libresoc.v:185371$11990_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185325$12196 + cell $not $not$libresoc.v:185373$11992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185325$12196_Y + connect \Y $not$libresoc.v:185373$11992_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185328$12199 + cell $not $not$libresoc.v:185376$11995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185328$12199_Y + connect \Y $not$libresoc.v:185376$11995_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185322$12193 + cell $or $or$libresoc.v:185370$11989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383500,10 +348480,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185322$12193_Y + connect \Y $or$libresoc.v:185370$11989_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185324$12195 + cell $or $or$libresoc.v:185372$11991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383511,10 +348491,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185324$12195_Y + connect \Y $or$libresoc.v:185372$11991_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185327$12198 + cell $or $or$libresoc.v:185375$11994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383522,39 +348502,39 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185327$12198_Y + connect \Y $or$libresoc.v:185375$11994_Y end - attribute \src "libresoc.v:185286.7-185286.20" - process $proc$libresoc.v:185286$12204 + attribute \src "libresoc.v:185334.7-185334.20" + process $proc$libresoc.v:185334$12000 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185308.7-185308.19" - process $proc$libresoc.v:185308$12205 + attribute \src "libresoc.v:185356.7-185356.19" + process $proc$libresoc.v:185356$12001 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185329.3-185330.27" - process $proc$libresoc.v:185329$12200 + attribute \src "libresoc.v:185377.3-185378.27" + process $proc$libresoc.v:185377$11996 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185331.3-185339.6" - process $proc$libresoc.v:185331$12201 + attribute \src "libresoc.v:185379.3-185387.6" + process $proc$libresoc.v:185379$11997 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12202 $1\q_int$next[0:0]$12203 - attribute \src "libresoc.v:185332.5-185332.29" + assign $0\q_int$next[0:0]$11998 $1\q_int$next[0:0]$11999 + attribute \src "libresoc.v:185380.5-185380.29" switch \initial - attribute \src "libresoc.v:185332.9-185332.17" + attribute \src "libresoc.v:185380.9-185380.17" case 1'1 case end @@ -383563,56 +348543,56 @@ module \rok_l$59 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12203 1'0 + assign $1\q_int$next[0:0]$11999 1'0 case - assign $1\q_int$next[0:0]$12203 \$5 + assign $1\q_int$next[0:0]$11999 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12202 + update \q_int$next $0\q_int$next[0:0]$11998 end - connect \$9 $and$libresoc.v:185321$12192_Y - connect \$11 $or$libresoc.v:185322$12193_Y - connect \$13 $not$libresoc.v:185323$12194_Y - connect \$15 $or$libresoc.v:185324$12195_Y - connect \$1 $not$libresoc.v:185325$12196_Y - connect \$3 $and$libresoc.v:185326$12197_Y - connect \$5 $or$libresoc.v:185327$12198_Y - connect \$7 $not$libresoc.v:185328$12199_Y + connect \$9 $and$libresoc.v:185369$11988_Y + connect \$11 $or$libresoc.v:185370$11989_Y + connect \$13 $not$libresoc.v:185371$11990_Y + connect \$15 $or$libresoc.v:185372$11991_Y + connect \$1 $not$libresoc.v:185373$11992_Y + connect \$3 $and$libresoc.v:185374$11993_Y + connect \$5 $or$libresoc.v:185375$11994_Y + connect \$7 $not$libresoc.v:185376$11995_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185347.1-185405.10" +attribute \src "libresoc.v:185395.1-185453.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" attribute \generator "nMigen" module \rok_l$71 - attribute \src "libresoc.v:185348.7-185348.20" + attribute \src "libresoc.v:185396.7-185396.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185393.3-185401.6" - wire $0\q_int$next[0:0]$12216 - attribute \src "libresoc.v:185391.3-185392.27" + attribute \src "libresoc.v:185441.3-185449.6" + wire $0\q_int$next[0:0]$12012 + attribute \src "libresoc.v:185439.3-185440.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185393.3-185401.6" - wire $1\q_int$next[0:0]$12217 - attribute \src "libresoc.v:185370.7-185370.19" + attribute \src "libresoc.v:185441.3-185449.6" + wire $1\q_int$next[0:0]$12013 + attribute \src "libresoc.v:185418.7-185418.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185383.17-185383.96" - wire $and$libresoc.v:185383$12206_Y - attribute \src "libresoc.v:185388.17-185388.96" - wire $and$libresoc.v:185388$12211_Y - attribute \src "libresoc.v:185385.18-185385.94" - wire $not$libresoc.v:185385$12208_Y - attribute \src "libresoc.v:185387.17-185387.93" - wire $not$libresoc.v:185387$12210_Y - attribute \src "libresoc.v:185390.17-185390.93" - wire $not$libresoc.v:185390$12213_Y - attribute \src "libresoc.v:185384.18-185384.99" - wire $or$libresoc.v:185384$12207_Y - attribute \src "libresoc.v:185386.18-185386.100" - wire $or$libresoc.v:185386$12209_Y - attribute \src "libresoc.v:185389.17-185389.98" - wire $or$libresoc.v:185389$12212_Y + attribute \src "libresoc.v:185431.17-185431.96" + wire $and$libresoc.v:185431$12002_Y + attribute \src "libresoc.v:185436.17-185436.96" + wire $and$libresoc.v:185436$12007_Y + attribute \src "libresoc.v:185433.18-185433.94" + wire $not$libresoc.v:185433$12004_Y + attribute \src "libresoc.v:185435.17-185435.93" + wire $not$libresoc.v:185435$12006_Y + attribute \src "libresoc.v:185438.17-185438.93" + wire $not$libresoc.v:185438$12009_Y + attribute \src "libresoc.v:185432.18-185432.99" + wire $or$libresoc.v:185432$12003_Y + attribute \src "libresoc.v:185434.18-185434.100" + wire $or$libresoc.v:185434$12005_Y + attribute \src "libresoc.v:185437.17-185437.98" + wire $or$libresoc.v:185437$12008_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -383629,11 +348609,11 @@ module \rok_l$71 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:185348.7-185348.15" + attribute \src "libresoc.v:185396.7-185396.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -383650,7 +348630,7 @@ module \rok_l$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185383$12206 + cell $and $and$libresoc.v:185431$12002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383658,10 +348638,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185383$12206_Y + connect \Y $and$libresoc.v:185431$12002_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185388$12211 + cell $and $and$libresoc.v:185436$12007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383669,34 +348649,34 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185388$12211_Y + connect \Y $and$libresoc.v:185436$12007_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185385$12208 + cell $not $not$libresoc.v:185433$12004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185385$12208_Y + connect \Y $not$libresoc.v:185433$12004_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185387$12210 + cell $not $not$libresoc.v:185435$12006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185387$12210_Y + connect \Y $not$libresoc.v:185435$12006_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185390$12213 + cell $not $not$libresoc.v:185438$12009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185390$12213_Y + connect \Y $not$libresoc.v:185438$12009_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185384$12207 + cell $or $or$libresoc.v:185432$12003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383704,10 +348684,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185384$12207_Y + connect \Y $or$libresoc.v:185432$12003_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185386$12209 + cell $or $or$libresoc.v:185434$12005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383715,10 +348695,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185386$12209_Y + connect \Y $or$libresoc.v:185434$12005_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185389$12212 + cell $or $or$libresoc.v:185437$12008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383726,39 +348706,39 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185389$12212_Y + connect \Y $or$libresoc.v:185437$12008_Y end - attribute \src "libresoc.v:185348.7-185348.20" - process $proc$libresoc.v:185348$12218 + attribute \src "libresoc.v:185396.7-185396.20" + process $proc$libresoc.v:185396$12014 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185370.7-185370.19" - process $proc$libresoc.v:185370$12219 + attribute \src "libresoc.v:185418.7-185418.19" + process $proc$libresoc.v:185418$12015 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185391.3-185392.27" - process $proc$libresoc.v:185391$12214 + attribute \src "libresoc.v:185439.3-185440.27" + process $proc$libresoc.v:185439$12010 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185393.3-185401.6" - process $proc$libresoc.v:185393$12215 + attribute \src "libresoc.v:185441.3-185449.6" + process $proc$libresoc.v:185441$12011 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12216 $1\q_int$next[0:0]$12217 - attribute \src "libresoc.v:185394.5-185394.29" + assign $0\q_int$next[0:0]$12012 $1\q_int$next[0:0]$12013 + attribute \src "libresoc.v:185442.5-185442.29" switch \initial - attribute \src "libresoc.v:185394.9-185394.17" + attribute \src "libresoc.v:185442.9-185442.17" case 1'1 case end @@ -383767,56 +348747,56 @@ module \rok_l$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12217 1'0 + assign $1\q_int$next[0:0]$12013 1'0 case - assign $1\q_int$next[0:0]$12217 \$5 + assign $1\q_int$next[0:0]$12013 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12216 + update \q_int$next $0\q_int$next[0:0]$12012 end - connect \$9 $and$libresoc.v:185383$12206_Y - connect \$11 $or$libresoc.v:185384$12207_Y - connect \$13 $not$libresoc.v:185385$12208_Y - connect \$15 $or$libresoc.v:185386$12209_Y - connect \$1 $not$libresoc.v:185387$12210_Y - connect \$3 $and$libresoc.v:185388$12211_Y - connect \$5 $or$libresoc.v:185389$12212_Y - connect \$7 $not$libresoc.v:185390$12213_Y + connect \$9 $and$libresoc.v:185431$12002_Y + connect \$11 $or$libresoc.v:185432$12003_Y + connect \$13 $not$libresoc.v:185433$12004_Y + connect \$15 $or$libresoc.v:185434$12005_Y + connect \$1 $not$libresoc.v:185435$12006_Y + connect \$3 $and$libresoc.v:185436$12007_Y + connect \$5 $or$libresoc.v:185437$12008_Y + connect \$7 $not$libresoc.v:185438$12009_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185409.1-185467.10" +attribute \src "libresoc.v:185457.1-185515.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l" attribute \generator "nMigen" module \rok_l$88 - attribute \src "libresoc.v:185410.7-185410.20" + attribute \src "libresoc.v:185458.7-185458.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185455.3-185463.6" - wire $0\q_int$next[0:0]$12230 - attribute \src "libresoc.v:185453.3-185454.27" + attribute \src "libresoc.v:185503.3-185511.6" + wire $0\q_int$next[0:0]$12026 + attribute \src "libresoc.v:185501.3-185502.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185455.3-185463.6" - wire $1\q_int$next[0:0]$12231 - attribute \src "libresoc.v:185432.7-185432.19" + attribute \src "libresoc.v:185503.3-185511.6" + wire $1\q_int$next[0:0]$12027 + attribute \src "libresoc.v:185480.7-185480.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185445.17-185445.96" - wire $and$libresoc.v:185445$12220_Y - attribute \src "libresoc.v:185450.17-185450.96" - wire $and$libresoc.v:185450$12225_Y - attribute \src "libresoc.v:185447.18-185447.94" - wire $not$libresoc.v:185447$12222_Y - attribute \src "libresoc.v:185449.17-185449.93" - wire $not$libresoc.v:185449$12224_Y - attribute \src "libresoc.v:185452.17-185452.93" - wire $not$libresoc.v:185452$12227_Y - attribute \src "libresoc.v:185446.18-185446.99" - wire $or$libresoc.v:185446$12221_Y - attribute \src "libresoc.v:185448.18-185448.100" - wire $or$libresoc.v:185448$12223_Y - attribute \src "libresoc.v:185451.17-185451.98" - wire $or$libresoc.v:185451$12226_Y + attribute \src "libresoc.v:185493.17-185493.96" + wire $and$libresoc.v:185493$12016_Y + attribute \src "libresoc.v:185498.17-185498.96" + wire $and$libresoc.v:185498$12021_Y + attribute \src "libresoc.v:185495.18-185495.94" + wire $not$libresoc.v:185495$12018_Y + attribute \src "libresoc.v:185497.17-185497.93" + wire $not$libresoc.v:185497$12020_Y + attribute \src "libresoc.v:185500.17-185500.93" + wire $not$libresoc.v:185500$12023_Y + attribute \src "libresoc.v:185494.18-185494.99" + wire $or$libresoc.v:185494$12017_Y + attribute \src "libresoc.v:185496.18-185496.100" + wire $or$libresoc.v:185496$12019_Y + attribute \src "libresoc.v:185499.17-185499.98" + wire $or$libresoc.v:185499$12022_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -383833,11 +348813,11 @@ module \rok_l$88 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:185410.7-185410.15" + attribute \src "libresoc.v:185458.7-185458.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -383854,7 +348834,7 @@ module \rok_l$88 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185445$12220 + cell $and $and$libresoc.v:185493$12016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383862,10 +348842,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185445$12220_Y + connect \Y $and$libresoc.v:185493$12016_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185450$12225 + cell $and $and$libresoc.v:185498$12021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383873,34 +348853,34 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185450$12225_Y + connect \Y $and$libresoc.v:185498$12021_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185447$12222 + cell $not $not$libresoc.v:185495$12018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185447$12222_Y + connect \Y $not$libresoc.v:185495$12018_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185449$12224 + cell $not $not$libresoc.v:185497$12020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185449$12224_Y + connect \Y $not$libresoc.v:185497$12020_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185452$12227 + cell $not $not$libresoc.v:185500$12023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185452$12227_Y + connect \Y $not$libresoc.v:185500$12023_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185446$12221 + cell $or $or$libresoc.v:185494$12017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383908,10 +348888,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185446$12221_Y + connect \Y $or$libresoc.v:185494$12017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185448$12223 + cell $or $or$libresoc.v:185496$12019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383919,10 +348899,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185448$12223_Y + connect \Y $or$libresoc.v:185496$12019_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185451$12226 + cell $or $or$libresoc.v:185499$12022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383930,39 +348910,39 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185451$12226_Y + connect \Y $or$libresoc.v:185499$12022_Y end - attribute \src "libresoc.v:185410.7-185410.20" - process $proc$libresoc.v:185410$12232 + attribute \src "libresoc.v:185458.7-185458.20" + process $proc$libresoc.v:185458$12028 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185432.7-185432.19" - process $proc$libresoc.v:185432$12233 + attribute \src "libresoc.v:185480.7-185480.19" + process $proc$libresoc.v:185480$12029 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185453.3-185454.27" - process $proc$libresoc.v:185453$12228 + attribute \src "libresoc.v:185501.3-185502.27" + process $proc$libresoc.v:185501$12024 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185455.3-185463.6" - process $proc$libresoc.v:185455$12229 + attribute \src "libresoc.v:185503.3-185511.6" + process $proc$libresoc.v:185503$12025 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12230 $1\q_int$next[0:0]$12231 - attribute \src "libresoc.v:185456.5-185456.29" + assign $0\q_int$next[0:0]$12026 $1\q_int$next[0:0]$12027 + attribute \src "libresoc.v:185504.5-185504.29" switch \initial - attribute \src "libresoc.v:185456.9-185456.17" + attribute \src "libresoc.v:185504.9-185504.17" case 1'1 case end @@ -383971,150 +348951,150 @@ module \rok_l$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12231 1'0 + assign $1\q_int$next[0:0]$12027 1'0 case - assign $1\q_int$next[0:0]$12231 \$5 + assign $1\q_int$next[0:0]$12027 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12230 + update \q_int$next $0\q_int$next[0:0]$12026 end - connect \$9 $and$libresoc.v:185445$12220_Y - connect \$11 $or$libresoc.v:185446$12221_Y - connect \$13 $not$libresoc.v:185447$12222_Y - connect \$15 $or$libresoc.v:185448$12223_Y - connect \$1 $not$libresoc.v:185449$12224_Y - connect \$3 $and$libresoc.v:185450$12225_Y - connect \$5 $or$libresoc.v:185451$12226_Y - connect \$7 $not$libresoc.v:185452$12227_Y + connect \$9 $and$libresoc.v:185493$12016_Y + connect \$11 $or$libresoc.v:185494$12017_Y + connect \$13 $not$libresoc.v:185495$12018_Y + connect \$15 $or$libresoc.v:185496$12019_Y + connect \$1 $not$libresoc.v:185497$12020_Y + connect \$3 $and$libresoc.v:185498$12021_Y + connect \$5 $or$libresoc.v:185499$12022_Y + connect \$7 $not$libresoc.v:185500$12023_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185471.1-185822.10" +attribute \src "libresoc.v:185519.1-185879.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" attribute \generator "nMigen" module \rotator - attribute \src "libresoc.v:185740.3-185749.6" + attribute \src "libresoc.v:185788.3-185806.6" wire $0\carry_out_o[0:0] - attribute \src "libresoc.v:185672.3-185686.6" + attribute \src "libresoc.v:185720.3-185734.6" wire width 32 $0\hi32[31:0] - attribute \src "libresoc.v:185472.7-185472.20" + attribute \src "libresoc.v:185520.7-185520.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185762.3-185795.6" - wire width 7 $0\mb$8[6:0]$12281 - attribute \src "libresoc.v:185796.3-185810.6" - wire width 7 $0\me$13[6:0]$12286 - attribute \src "libresoc.v:185697.3-185708.6" + attribute \src "libresoc.v:185819.3-185852.6" + wire width 7 $0\mb$8[6:0]$12077 + attribute \src "libresoc.v:185853.3-185867.6" + wire width 7 $0\me$13[6:0]$12082 + attribute \src "libresoc.v:185745.3-185756.6" wire width 64 $0\mr[63:0] - attribute \src "libresoc.v:185709.3-185720.6" + attribute \src "libresoc.v:185757.3-185768.6" wire width 2 $0\output_mode[1:0] - attribute \src "libresoc.v:185721.3-185739.6" + attribute \src "libresoc.v:185769.3-185787.6" wire width 64 $0\result_o[63:0] - attribute \src "libresoc.v:185687.3-185696.6" + attribute \src "libresoc.v:185735.3-185744.6" wire width 7 $0\right_mask_shift[6:0] - attribute \src "libresoc.v:185750.3-185761.6" + attribute \src "libresoc.v:185807.3-185818.6" wire width 6 $0\rot_count[5:0] - attribute \src "libresoc.v:185740.3-185749.6" + attribute \src "libresoc.v:185788.3-185806.6" wire $1\carry_out_o[0:0] - attribute \src "libresoc.v:185672.3-185686.6" + attribute \src "libresoc.v:185720.3-185734.6" wire width 32 $1\hi32[31:0] - attribute \src "libresoc.v:185762.3-185795.6" - wire width 7 $1\mb$8[6:0]$12282 - attribute \src "libresoc.v:185796.3-185810.6" - wire width 7 $1\me$13[6:0]$12287 - attribute \src "libresoc.v:185697.3-185708.6" + attribute \src "libresoc.v:185819.3-185852.6" + wire width 7 $1\mb$8[6:0]$12078 + attribute \src "libresoc.v:185853.3-185867.6" + wire width 7 $1\me$13[6:0]$12083 + attribute \src "libresoc.v:185745.3-185756.6" wire width 64 $1\mr[63:0] - attribute \src "libresoc.v:185709.3-185720.6" + attribute \src "libresoc.v:185757.3-185768.6" wire width 2 $1\output_mode[1:0] - attribute \src "libresoc.v:185721.3-185739.6" + attribute \src "libresoc.v:185769.3-185787.6" wire width 64 $1\result_o[63:0] - attribute \src "libresoc.v:185687.3-185696.6" + attribute \src "libresoc.v:185735.3-185744.6" wire width 7 $1\right_mask_shift[6:0] - attribute \src "libresoc.v:185750.3-185761.6" + attribute \src "libresoc.v:185807.3-185818.6" wire width 6 $1\rot_count[5:0] - attribute \src "libresoc.v:185762.3-185795.6" - wire width 2 $2\mb$8[6:5]$12283 - attribute \src "libresoc.v:185762.3-185795.6" - wire width 2 $3\mb$8[6:5]$12284 - attribute \src "libresoc.v:185623.18-185623.118" - wire $and$libresoc.v:185623$12237_Y - attribute \src "libresoc.v:185625.18-185625.114" - wire $and$libresoc.v:185625$12239_Y - attribute \src "libresoc.v:185634.18-185634.113" - wire $and$libresoc.v:185634$12248_Y - attribute \src "libresoc.v:185636.18-185636.114" - wire $and$libresoc.v:185636$12250_Y - attribute \src "libresoc.v:185638.18-185638.114" - wire $and$libresoc.v:185638$12252_Y - attribute \src "libresoc.v:185639.18-185639.103" - wire width 64 $and$libresoc.v:185639$12253_Y - attribute \src "libresoc.v:185640.18-185640.106" - wire width 64 $and$libresoc.v:185640$12254_Y - attribute \src "libresoc.v:185642.18-185642.103" - wire width 64 $and$libresoc.v:185642$12256_Y - attribute \src "libresoc.v:185644.18-185644.105" - wire width 64 $and$libresoc.v:185644$12258_Y - attribute \src "libresoc.v:185647.18-185647.106" - wire width 64 $and$libresoc.v:185647$12261_Y - attribute \src "libresoc.v:185650.18-185650.105" - wire width 64 $and$libresoc.v:185650$12264_Y - attribute \src "libresoc.v:185652.17-185652.109" - wire $and$libresoc.v:185652$12266_Y - attribute \src "libresoc.v:185653.18-185653.104" - wire width 64 $and$libresoc.v:185653$12267_Y - attribute \src "libresoc.v:185657.18-185657.105" - wire width 64 $and$libresoc.v:185657$12271_Y - attribute \src "libresoc.v:185621.17-185621.98" - wire width 7 $extend$libresoc.v:185621$12234_Y - attribute \src "libresoc.v:185637.18-185637.122" - wire $gt$libresoc.v:185637$12251_Y - attribute \src "libresoc.v:185627.18-185627.111" - wire $le$libresoc.v:185627$12241_Y - attribute \src "libresoc.v:185629.18-185629.111" - wire $le$libresoc.v:185629$12243_Y - attribute \src "libresoc.v:185630.17-185630.117" - wire width 7 $neg$libresoc.v:185630$12244_Y - attribute \src "libresoc.v:185622.18-185622.103" - wire $not$libresoc.v:185622$12236_Y - attribute \src "libresoc.v:185624.18-185624.108" - wire $not$libresoc.v:185624$12238_Y - attribute \src "libresoc.v:185626.18-185626.105" - wire width 6 $not$libresoc.v:185626$12240_Y - attribute \src "libresoc.v:185632.18-185632.112" - wire width 64 $not$libresoc.v:185632$12246_Y - attribute \src "libresoc.v:185633.18-185633.109" - wire $not$libresoc.v:185633$12247_Y - attribute \src "libresoc.v:185641.17-185641.105" - wire $not$libresoc.v:185641$12255_Y - attribute \src "libresoc.v:185643.18-185643.102" - wire width 64 $not$libresoc.v:185643$12257_Y - attribute \src "libresoc.v:185649.18-185649.102" - wire width 64 $not$libresoc.v:185649$12263_Y - attribute \src "libresoc.v:185654.18-185654.100" - wire width 64 $not$libresoc.v:185654$12268_Y - attribute \src "libresoc.v:185656.18-185656.100" - wire width 64 $not$libresoc.v:185656$12270_Y - attribute \src "libresoc.v:185635.18-185635.115" - wire $or$libresoc.v:185635$12249_Y - attribute \src "libresoc.v:185645.18-185645.108" - wire width 64 $or$libresoc.v:185645$12259_Y - attribute \src "libresoc.v:185646.18-185646.103" - wire width 64 $or$libresoc.v:185646$12260_Y - attribute \src "libresoc.v:185648.18-185648.103" - wire width 64 $or$libresoc.v:185648$12262_Y - attribute \src "libresoc.v:185651.18-185651.108" - wire width 64 $or$libresoc.v:185651$12265_Y - attribute \src "libresoc.v:185655.18-185655.106" - wire width 64 $or$libresoc.v:185655$12269_Y - attribute \src "libresoc.v:185621.17-185621.98" - wire width 7 $pos$libresoc.v:185621$12235_Y - attribute \src "libresoc.v:185658.18-185658.102" - wire $reduce_or$libresoc.v:185658$12272_Y - attribute \src "libresoc.v:185628.18-185628.109" - wire width 8 $sub$libresoc.v:185628$12242_Y - attribute \src "libresoc.v:185631.18-185631.110" - wire width 8 $sub$libresoc.v:185631$12245_Y + attribute \src "libresoc.v:185819.3-185852.6" + wire width 2 $2\mb$8[6:5]$12079 + attribute \src "libresoc.v:185819.3-185852.6" + wire width 2 $3\mb$8[6:5]$12080 + attribute \src "libresoc.v:185671.18-185671.118" + wire $and$libresoc.v:185671$12033_Y + attribute \src "libresoc.v:185673.18-185673.114" + wire $and$libresoc.v:185673$12035_Y + attribute \src "libresoc.v:185682.18-185682.113" + wire $and$libresoc.v:185682$12044_Y + attribute \src "libresoc.v:185684.18-185684.114" + wire $and$libresoc.v:185684$12046_Y + attribute \src "libresoc.v:185686.18-185686.114" + wire $and$libresoc.v:185686$12048_Y + attribute \src "libresoc.v:185687.18-185687.103" + wire width 64 $and$libresoc.v:185687$12049_Y + attribute \src "libresoc.v:185688.18-185688.106" + wire width 64 $and$libresoc.v:185688$12050_Y + attribute \src "libresoc.v:185690.18-185690.103" + wire width 64 $and$libresoc.v:185690$12052_Y + attribute \src "libresoc.v:185692.18-185692.105" + wire width 64 $and$libresoc.v:185692$12054_Y + attribute \src "libresoc.v:185695.18-185695.106" + wire width 64 $and$libresoc.v:185695$12057_Y + attribute \src "libresoc.v:185698.18-185698.105" + wire width 64 $and$libresoc.v:185698$12060_Y + attribute \src "libresoc.v:185700.17-185700.109" + wire $and$libresoc.v:185700$12062_Y + attribute \src "libresoc.v:185701.18-185701.104" + wire width 64 $and$libresoc.v:185701$12063_Y + attribute \src "libresoc.v:185705.18-185705.105" + wire width 64 $and$libresoc.v:185705$12067_Y + attribute \src "libresoc.v:185669.17-185669.98" + wire width 7 $extend$libresoc.v:185669$12030_Y + attribute \src "libresoc.v:185685.18-185685.122" + wire $gt$libresoc.v:185685$12047_Y + attribute \src "libresoc.v:185675.18-185675.111" + wire $le$libresoc.v:185675$12037_Y + attribute \src "libresoc.v:185677.18-185677.111" + wire $le$libresoc.v:185677$12039_Y + attribute \src "libresoc.v:185678.17-185678.117" + wire width 7 signed $neg$libresoc.v:185678$12040_Y + attribute \src "libresoc.v:185670.18-185670.103" + wire $not$libresoc.v:185670$12032_Y + attribute \src "libresoc.v:185672.18-185672.108" + wire $not$libresoc.v:185672$12034_Y + attribute \src "libresoc.v:185674.18-185674.105" + wire width 6 $not$libresoc.v:185674$12036_Y + attribute \src "libresoc.v:185680.18-185680.112" + wire width 64 $not$libresoc.v:185680$12042_Y + attribute \src "libresoc.v:185681.18-185681.109" + wire $not$libresoc.v:185681$12043_Y + attribute \src "libresoc.v:185689.17-185689.105" + wire $not$libresoc.v:185689$12051_Y + attribute \src "libresoc.v:185691.18-185691.102" + wire width 64 $not$libresoc.v:185691$12053_Y + attribute \src "libresoc.v:185697.18-185697.102" + wire width 64 $not$libresoc.v:185697$12059_Y + attribute \src "libresoc.v:185702.18-185702.100" + wire width 64 $not$libresoc.v:185702$12064_Y + attribute \src "libresoc.v:185704.18-185704.100" + wire width 64 $not$libresoc.v:185704$12066_Y + attribute \src "libresoc.v:185683.18-185683.115" + wire $or$libresoc.v:185683$12045_Y + attribute \src "libresoc.v:185693.18-185693.108" + wire width 64 $or$libresoc.v:185693$12055_Y + attribute \src "libresoc.v:185694.18-185694.103" + wire width 64 $or$libresoc.v:185694$12056_Y + attribute \src "libresoc.v:185696.18-185696.103" + wire width 64 $or$libresoc.v:185696$12058_Y + attribute \src "libresoc.v:185699.18-185699.108" + wire width 64 $or$libresoc.v:185699$12061_Y + attribute \src "libresoc.v:185703.18-185703.106" + wire width 64 $or$libresoc.v:185703$12065_Y + attribute \src "libresoc.v:185669.17-185669.98" + wire width 7 $pos$libresoc.v:185669$12031_Y + attribute \src "libresoc.v:185706.18-185706.102" + wire $reduce_or$libresoc.v:185706$12068_Y + attribute \src "libresoc.v:185676.18-185676.109" + wire width 8 $sub$libresoc.v:185676$12038_Y + attribute \src "libresoc.v:185679.18-185679.110" + wire width 8 $sub$libresoc.v:185679$12041_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" wire width 7 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" @@ -384207,7 +349187,7 @@ module \rotator wire input 10 \clear_right attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" wire width 32 \hi32 - attribute \src "libresoc.v:185472.7-185472.15" + attribute \src "libresoc.v:185520.7-185520.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" wire input 6 \is_32bit @@ -384264,7 +349244,7 @@ module \rotator attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" wire input 11 \sign_ext_rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - cell $and $and$libresoc.v:185623$12237 + cell $and $and$libresoc.v:185671$12033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384272,10 +349252,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \is_32bit - connect \Y $and$libresoc.v:185623$12237_Y + connect \Y $and$libresoc.v:185671$12033_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $and $and$libresoc.v:185625$12239 + cell $and $and$libresoc.v:185673$12035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384283,10 +349263,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$16 - connect \Y $and$libresoc.v:185625$12239_Y + connect \Y $and$libresoc.v:185673$12035_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $and $and$libresoc.v:185634$12248 + cell $and $and$libresoc.v:185682$12044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384294,10 +349274,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_left connect \B \$34 - connect \Y $and$libresoc.v:185634$12248_Y + connect \Y $and$libresoc.v:185682$12044_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - cell $and $and$libresoc.v:185636$12250 + cell $and $and$libresoc.v:185684$12046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384305,10 +349285,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \arith connect \B \repl32 [63] - connect \Y $and$libresoc.v:185636$12250_Y + connect \Y $and$libresoc.v:185684$12046_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $and $and$libresoc.v:185638$12252 + cell $and $and$libresoc.v:185686$12048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384316,10 +349296,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$42 - connect \Y $and$libresoc.v:185638$12252_Y + connect \Y $and$libresoc.v:185686$12048_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185639$12253 + cell $and $and$libresoc.v:185687$12049 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384327,10 +349307,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:185639$12253_Y + connect \Y $and$libresoc.v:185687$12049_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185640$12254 + cell $and $and$libresoc.v:185688$12050 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384338,10 +349318,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$46 - connect \Y $and$libresoc.v:185640$12254_Y + connect \Y $and$libresoc.v:185688$12050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185642$12256 + cell $and $and$libresoc.v:185690$12052 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384349,10 +349329,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:185642$12256_Y + connect \Y $and$libresoc.v:185690$12052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185644$12258 + cell $and $and$libresoc.v:185692$12054 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384360,10 +349340,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$50 - connect \Y $and$libresoc.v:185644$12258_Y + connect \Y $and$libresoc.v:185692$12054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:185647$12261 + cell $and $and$libresoc.v:185695$12057 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384371,10 +349351,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$58 - connect \Y $and$libresoc.v:185647$12261_Y + connect \Y $and$libresoc.v:185695$12057_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:185650$12264 + cell $and $and$libresoc.v:185698$12060 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384382,10 +349362,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$62 - connect \Y $and$libresoc.v:185650$12264_Y + connect \Y $and$libresoc.v:185698$12060_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $and $and$libresoc.v:185652$12266 + cell $and $and$libresoc.v:185700$12062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384393,10 +349373,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \shift [6] connect \B \$4 - connect \Y $and$libresoc.v:185652$12266_Y + connect \Y $and$libresoc.v:185700$12062_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" - cell $and $and$libresoc.v:185653$12267 + cell $and $and$libresoc.v:185701$12063 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384404,10 +349384,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \mr - connect \Y $and$libresoc.v:185653$12267_Y + connect \Y $and$libresoc.v:185701$12063_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $and $and$libresoc.v:185657$12271 + cell $and $and$libresoc.v:185705$12067 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384415,18 +349395,18 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rs connect \B \$77 - connect \Y $and$libresoc.v:185657$12271_Y + connect \Y $and$libresoc.v:185705$12067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $extend$libresoc.v:185621$12234 + cell $pos $extend$libresoc.v:185669$12030 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \mb - connect \Y $extend$libresoc.v:185621$12234_Y + connect \Y $extend$libresoc.v:185669$12030_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $gt $gt$libresoc.v:185637$12251 + cell $gt $gt$libresoc.v:185685$12047 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -384434,10 +349414,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 [5:0] connect \B \me$13 [5:0] - connect \Y $gt$libresoc.v:185637$12251_Y + connect \Y $gt$libresoc.v:185685$12047_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:185627$12241 + cell $le $le$libresoc.v:185675$12037 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -384445,10 +349425,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:185627$12241_Y + connect \Y $le$libresoc.v:185675$12037_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:185629$12243 + cell $le $le$libresoc.v:185677$12039 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -384456,98 +349436,98 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:185629$12243_Y + connect \Y $le$libresoc.v:185677$12039_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" - cell $neg $neg$libresoc.v:185630$12244 + cell $neg $neg$libresoc.v:185678$12040 parameter \A_SIGNED 1 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { \shift_signed [5] \shift_signed } - connect \Y $neg$libresoc.v:185630$12244_Y + connect \Y $neg$libresoc.v:185678$12040_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" - cell $not $not$libresoc.v:185622$12236 + cell $not $not$libresoc.v:185670$12032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sh [5] - connect \Y $not$libresoc.v:185622$12236_Y + connect \Y $not$libresoc.v:185670$12032_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $not $not$libresoc.v:185624$12238 + cell $not $not$libresoc.v:185672$12034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_left - connect \Y $not$libresoc.v:185624$12238_Y + connect \Y $not$libresoc.v:185672$12034_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" - cell $not $not$libresoc.v:185626$12240 + cell $not $not$libresoc.v:185674$12036 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \sh [5:0] - connect \Y $not$libresoc.v:185626$12240_Y + connect \Y $not$libresoc.v:185674$12036_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" - cell $not $not$libresoc.v:185632$12246 + cell $not $not$libresoc.v:185680$12042 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \left_mask_mask - connect \Y $not$libresoc.v:185632$12246_Y + connect \Y $not$libresoc.v:185680$12042_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $not $not$libresoc.v:185633$12247 + cell $not $not$libresoc.v:185681$12043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_right - connect \Y $not$libresoc.v:185633$12247_Y + connect \Y $not$libresoc.v:185681$12043_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $not $not$libresoc.v:185641$12255 + cell $not $not$libresoc.v:185689$12051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit - connect \Y $not$libresoc.v:185641$12255_Y + connect \Y $not$libresoc.v:185689$12051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $not $not$libresoc.v:185643$12257 + cell $not $not$libresoc.v:185691$12053 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$51 - connect \Y $not$libresoc.v:185643$12257_Y + connect \Y $not$libresoc.v:185691$12053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $not $not$libresoc.v:185649$12263 + cell $not $not$libresoc.v:185697$12059 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$63 - connect \Y $not$libresoc.v:185649$12263_Y + connect \Y $not$libresoc.v:185697$12059_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $not $not$libresoc.v:185654$12268 + cell $not $not$libresoc.v:185702$12064 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr - connect \Y $not$libresoc.v:185654$12268_Y + connect \Y $not$libresoc.v:185702$12064_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $not $not$libresoc.v:185656$12270 + cell $not $not$libresoc.v:185704$12066 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ml - connect \Y $not$libresoc.v:185656$12270_Y + connect \Y $not$libresoc.v:185704$12066_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $or $or$libresoc.v:185635$12249 + cell $or $or$libresoc.v:185683$12045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384555,10 +349535,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \$36 connect \B \right_shift - connect \Y $or$libresoc.v:185635$12249_Y + connect \Y $or$libresoc.v:185683$12045_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $or $or$libresoc.v:185645$12259 + cell $or $or$libresoc.v:185693$12055 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384566,10 +349546,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$48 connect \B \$54 - connect \Y $or$libresoc.v:185645$12259_Y + connect \Y $or$libresoc.v:185693$12055_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:185646$12260 + cell $or $or$libresoc.v:185694$12056 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384577,10 +349557,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:185646$12260_Y + connect \Y $or$libresoc.v:185694$12056_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:185648$12262 + cell $or $or$libresoc.v:185696$12058 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384588,10 +349568,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:185648$12262_Y + connect \Y $or$libresoc.v:185696$12058_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:185651$12265 + cell $or $or$libresoc.v:185699$12061 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384599,10 +349579,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$60 connect \B \$66 - connect \Y $or$libresoc.v:185651$12265_Y + connect \Y $or$libresoc.v:185699$12061_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $or $or$libresoc.v:185655$12269 + cell $or $or$libresoc.v:185703$12065 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384610,26 +349590,26 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$72 - connect \Y $or$libresoc.v:185655$12269_Y + connect \Y $or$libresoc.v:185703$12065_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $pos$libresoc.v:185621$12235 + cell $pos $pos$libresoc.v:185669$12031 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:185621$12234_Y - connect \Y $pos$libresoc.v:185621$12235_Y + connect \A $extend$libresoc.v:185669$12030_Y + connect \Y $pos$libresoc.v:185669$12031_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $reduce_or $reduce_or$libresoc.v:185658$12272 + cell $reduce_or $reduce_or$libresoc.v:185706$12068 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \$79 - connect \Y $reduce_or$libresoc.v:185658$12272_Y + connect \Y $reduce_or$libresoc.v:185706$12068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - cell $sub $sub$libresoc.v:185628$12242 + cell $sub $sub$libresoc.v:185676$12038 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -384637,10 +349617,10 @@ module \rotator parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \mb$8 - connect \Y $sub$libresoc.v:185628$12242_Y + connect \Y $sub$libresoc.v:185676$12038_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - cell $sub $sub$libresoc.v:185631$12245 + cell $sub $sub$libresoc.v:185679$12041 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -384648,42 +349628,42 @@ module \rotator parameter \Y_WIDTH 8 connect \A 6'111111 connect \B \me$13 - connect \Y $sub$libresoc.v:185631$12245_Y + connect \Y $sub$libresoc.v:185679$12041_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:185659.13-185662.4" + attribute \src "libresoc.v:185707.13-185710.4" cell \left_mask \left_mask connect \mask \left_mask_mask connect \shift \left_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:185663.14-185666.4" + attribute \src "libresoc.v:185711.14-185714.4" cell \right_mask \right_mask connect \mask \right_mask_mask connect \shift \right_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:185667.8-185671.4" + attribute \src "libresoc.v:185715.8-185719.4" cell \rotl \rotl connect \a \rotl_a connect \b \rotl_b connect \o \rotl_o end - attribute \src "libresoc.v:185472.7-185472.20" - process $proc$libresoc.v:185472$12288 + attribute \src "libresoc.v:185520.7-185520.20" + process $proc$libresoc.v:185520$12084 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185672.3-185686.6" - process $proc$libresoc.v:185672$12273 + attribute \src "libresoc.v:185720.3-185734.6" + process $proc$libresoc.v:185720$12069 assign { } { } assign $0\hi32[31:0] $1\hi32[31:0] - attribute \src "libresoc.v:185673.5-185673.29" + attribute \src "libresoc.v:185721.5-185721.29" switch \initial - attribute \src "libresoc.v:185673.9-185673.17" + attribute \src "libresoc.v:185721.9-185721.17" case 1'1 case end @@ -384705,14 +349685,14 @@ module \rotator sync always update \hi32 $0\hi32[31:0] end - attribute \src "libresoc.v:185687.3-185696.6" - process $proc$libresoc.v:185687$12274 + attribute \src "libresoc.v:185735.3-185744.6" + process $proc$libresoc.v:185735$12070 assign { } { } assign { } { } assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] - attribute \src "libresoc.v:185688.5-185688.29" + attribute \src "libresoc.v:185736.5-185736.29" switch \initial - attribute \src "libresoc.v:185688.9-185688.17" + attribute \src "libresoc.v:185736.9-185736.17" case 1'1 case end @@ -384728,13 +349708,13 @@ module \rotator sync always update \right_mask_shift $0\right_mask_shift[6:0] end - attribute \src "libresoc.v:185697.3-185708.6" - process $proc$libresoc.v:185697$12275 + attribute \src "libresoc.v:185745.3-185756.6" + process $proc$libresoc.v:185745$12071 assign { } { } assign $0\mr[63:0] $1\mr[63:0] - attribute \src "libresoc.v:185698.5-185698.29" + attribute \src "libresoc.v:185746.5-185746.29" switch \initial - attribute \src "libresoc.v:185698.9-185698.17" + attribute \src "libresoc.v:185746.9-185746.17" case 1'1 case end @@ -384752,13 +349732,13 @@ module \rotator sync always update \mr $0\mr[63:0] end - attribute \src "libresoc.v:185709.3-185720.6" - process $proc$libresoc.v:185709$12276 + attribute \src "libresoc.v:185757.3-185768.6" + process $proc$libresoc.v:185757$12072 assign { } { } assign $0\output_mode[1:0] $1\output_mode[1:0] - attribute \src "libresoc.v:185710.5-185710.29" + attribute \src "libresoc.v:185758.5-185758.29" switch \initial - attribute \src "libresoc.v:185710.9-185710.17" + attribute \src "libresoc.v:185758.9-185758.17" case 1'1 case end @@ -384776,14 +349756,14 @@ module \rotator sync always update \output_mode $0\output_mode[1:0] end - attribute \src "libresoc.v:185721.3-185739.6" - process $proc$libresoc.v:185721$12277 + attribute \src "libresoc.v:185769.3-185787.6" + process $proc$libresoc.v:185769$12073 assign { } { } assign { } { } assign $0\result_o[63:0] $1\result_o[63:0] - attribute \src "libresoc.v:185722.5-185722.29" + attribute \src "libresoc.v:185770.5-185770.29" switch \initial - attribute \src "libresoc.v:185722.9-185722.17" + attribute \src "libresoc.v:185770.9-185770.17" case 1'1 case end @@ -384811,20 +349791,29 @@ module \rotator sync always update \result_o $0\result_o[63:0] end - attribute \src "libresoc.v:185740.3-185749.6" - process $proc$libresoc.v:185740$12278 + attribute \src "libresoc.v:185788.3-185806.6" + process $proc$libresoc.v:185788$12074 assign { } { } assign { } { } assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] - attribute \src "libresoc.v:185741.5-185741.29" + attribute \src "libresoc.v:185789.5-185789.29" switch \initial - attribute \src "libresoc.v:185741.9-185741.17" + attribute \src "libresoc.v:185789.9-185789.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" switch \output_mode attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\carry_out_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\carry_out_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign $1\carry_out_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\carry_out_o[0:0] \$76 @@ -384834,13 +349823,13 @@ module \rotator sync always update \carry_out_o $0\carry_out_o[0:0] end - attribute \src "libresoc.v:185750.3-185761.6" - process $proc$libresoc.v:185750$12279 + attribute \src "libresoc.v:185807.3-185818.6" + process $proc$libresoc.v:185807$12075 assign { } { } assign $0\rot_count[5:0] $1\rot_count[5:0] - attribute \src "libresoc.v:185751.5-185751.29" + attribute \src "libresoc.v:185808.5-185808.29" switch \initial - attribute \src "libresoc.v:185751.9-185751.17" + attribute \src "libresoc.v:185808.9-185808.17" case 1'1 case end @@ -384858,13 +349847,13 @@ module \rotator sync always update \rot_count $0\rot_count[5:0] end - attribute \src "libresoc.v:185762.3-185795.6" - process $proc$libresoc.v:185762$12280 + attribute \src "libresoc.v:185819.3-185852.6" + process $proc$libresoc.v:185819$12076 assign { } { } - assign $0\mb$8[6:0]$12281 $1\mb$8[6:0]$12282 - attribute \src "libresoc.v:185763.5-185763.29" + assign $0\mb$8[6:0]$12077 $1\mb$8[6:0]$12078 + attribute \src "libresoc.v:185820.5-185820.29" switch \initial - attribute \src "libresoc.v:185763.9-185763.17" + attribute \src "libresoc.v:185820.9-185820.17" case 1'1 case end @@ -384873,48 +349862,48 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\mb$8[6:0]$12282 [4:0] \$9 [4:0] - assign $1\mb$8[6:0]$12282 [6:5] $2\mb$8[6:5]$12283 + assign $1\mb$8[6:0]$12078 [4:0] \$9 [4:0] + assign $1\mb$8[6:0]$12078 [6:5] $2\mb$8[6:5]$12079 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\mb$8[6:5]$12283 2'01 + assign $2\mb$8[6:5]$12079 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\mb$8[6:5]$12283 { 1'0 \mb_extra } + assign $2\mb$8[6:5]$12079 { 1'0 \mb_extra } end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\mb$8[6:0]$12282 [4:0] \sh [4:0] - assign $1\mb$8[6:0]$12282 [6:5] $3\mb$8[6:5]$12284 + assign $1\mb$8[6:0]$12078 [4:0] \sh [4:0] + assign $1\mb$8[6:0]$12078 [6:5] $3\mb$8[6:5]$12080 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\mb$8[6:5]$12284 { \sh [5] \$11 } + assign $3\mb$8[6:5]$12080 { \sh [5] \$11 } case - assign $3\mb$8[6:5]$12284 \sh [6:5] + assign $3\mb$8[6:5]$12080 \sh [6:5] end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\mb$8[6:0]$12282 { 1'0 \is_32bit 5'00000 } + assign $1\mb$8[6:0]$12078 { 1'0 \is_32bit 5'00000 } end sync always - update \mb$8 $0\mb$8[6:0]$12281 + update \mb$8 $0\mb$8[6:0]$12077 end - attribute \src "libresoc.v:185796.3-185810.6" - process $proc$libresoc.v:185796$12285 + attribute \src "libresoc.v:185853.3-185867.6" + process $proc$libresoc.v:185853$12081 assign { } { } - assign $0\me$13[6:0]$12286 $1\me$13[6:0]$12287 - attribute \src "libresoc.v:185797.5-185797.29" + assign $0\me$13[6:0]$12082 $1\me$13[6:0]$12083 + attribute \src "libresoc.v:185854.5-185854.29" switch \initial - attribute \src "libresoc.v:185797.9-185797.17" + attribute \src "libresoc.v:185854.9-185854.17" case 1'1 case end @@ -384923,57 +349912,57 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\me$13[6:0]$12287 { 2'01 \me } + assign $1\me$13[6:0]$12083 { 2'01 \me } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\me$13[6:0]$12287 { 1'0 \mb_extra \mb } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\me$13[6:0]$12287 { \sh [6] \$20 } - end - sync always - update \me$13 $0\me$13[6:0]$12286 - end - connect \$9 $pos$libresoc.v:185621$12235_Y - connect \$11 $not$libresoc.v:185622$12236_Y - connect \$14 $and$libresoc.v:185623$12237_Y - connect \$16 $not$libresoc.v:185624$12238_Y - connect \$18 $and$libresoc.v:185625$12239_Y - connect \$20 $not$libresoc.v:185626$12240_Y - connect \$22 $le$libresoc.v:185627$12241_Y - connect \$25 $sub$libresoc.v:185628$12242_Y - connect \$27 $le$libresoc.v:185629$12243_Y - connect \$2 $neg$libresoc.v:185630$12244_Y - connect \$30 $sub$libresoc.v:185631$12245_Y - connect \$32 $not$libresoc.v:185632$12246_Y - connect \$34 $not$libresoc.v:185633$12247_Y - connect \$36 $and$libresoc.v:185634$12248_Y - connect \$38 $or$libresoc.v:185635$12249_Y - connect \$40 $and$libresoc.v:185636$12250_Y - connect \$42 $gt$libresoc.v:185637$12251_Y - connect \$44 $and$libresoc.v:185638$12252_Y - connect \$46 $and$libresoc.v:185639$12253_Y - connect \$48 $and$libresoc.v:185640$12254_Y - connect \$4 $not$libresoc.v:185641$12255_Y - connect \$51 $and$libresoc.v:185642$12256_Y - connect \$50 $not$libresoc.v:185643$12257_Y - connect \$54 $and$libresoc.v:185644$12258_Y - connect \$56 $or$libresoc.v:185645$12259_Y - connect \$58 $or$libresoc.v:185646$12260_Y - connect \$60 $and$libresoc.v:185647$12261_Y - connect \$63 $or$libresoc.v:185648$12262_Y - connect \$62 $not$libresoc.v:185649$12263_Y - connect \$66 $and$libresoc.v:185650$12264_Y - connect \$68 $or$libresoc.v:185651$12265_Y - connect \$6 $and$libresoc.v:185652$12266_Y - connect \$70 $and$libresoc.v:185653$12267_Y - connect \$72 $not$libresoc.v:185654$12268_Y - connect \$74 $or$libresoc.v:185655$12269_Y - connect \$77 $not$libresoc.v:185656$12270_Y - connect \$79 $and$libresoc.v:185657$12271_Y - connect \$76 $reduce_or$libresoc.v:185658$12272_Y + assign $1\me$13[6:0]$12083 { 1'0 \mb_extra \mb } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\me$13[6:0]$12083 { \sh [6] \$20 } + end + sync always + update \me$13 $0\me$13[6:0]$12082 + end + connect \$9 $pos$libresoc.v:185669$12031_Y + connect \$11 $not$libresoc.v:185670$12032_Y + connect \$14 $and$libresoc.v:185671$12033_Y + connect \$16 $not$libresoc.v:185672$12034_Y + connect \$18 $and$libresoc.v:185673$12035_Y + connect \$20 $not$libresoc.v:185674$12036_Y + connect \$22 $le$libresoc.v:185675$12037_Y + connect \$25 $sub$libresoc.v:185676$12038_Y + connect \$27 $le$libresoc.v:185677$12039_Y + connect \$2 $neg$libresoc.v:185678$12040_Y + connect \$30 $sub$libresoc.v:185679$12041_Y + connect \$32 $not$libresoc.v:185680$12042_Y + connect \$34 $not$libresoc.v:185681$12043_Y + connect \$36 $and$libresoc.v:185682$12044_Y + connect \$38 $or$libresoc.v:185683$12045_Y + connect \$40 $and$libresoc.v:185684$12046_Y + connect \$42 $gt$libresoc.v:185685$12047_Y + connect \$44 $and$libresoc.v:185686$12048_Y + connect \$46 $and$libresoc.v:185687$12049_Y + connect \$48 $and$libresoc.v:185688$12050_Y + connect \$4 $not$libresoc.v:185689$12051_Y + connect \$51 $and$libresoc.v:185690$12052_Y + connect \$50 $not$libresoc.v:185691$12053_Y + connect \$54 $and$libresoc.v:185692$12054_Y + connect \$56 $or$libresoc.v:185693$12055_Y + connect \$58 $or$libresoc.v:185694$12056_Y + connect \$60 $and$libresoc.v:185695$12057_Y + connect \$63 $or$libresoc.v:185696$12058_Y + connect \$62 $not$libresoc.v:185697$12059_Y + connect \$66 $and$libresoc.v:185698$12060_Y + connect \$68 $or$libresoc.v:185699$12061_Y + connect \$6 $and$libresoc.v:185700$12062_Y + connect \$70 $and$libresoc.v:185701$12063_Y + connect \$72 $not$libresoc.v:185702$12064_Y + connect \$74 $or$libresoc.v:185703$12065_Y + connect \$77 $not$libresoc.v:185704$12066_Y + connect \$79 $and$libresoc.v:185705$12067_Y + connect \$76 $reduce_or$libresoc.v:185706$12068_Y connect \$1 \$2 connect \$24 \$25 connect \$29 \$30 @@ -384986,15 +349975,15 @@ module \rotator connect \shift_signed \shift [5:0] connect \repl32 { \hi32 \rs [31:0] } end -attribute \src "libresoc.v:185826.1-185840.10" +attribute \src "libresoc.v:185883.1-185897.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" attribute \generator "nMigen" module \rotl - attribute \src "libresoc.v:185838.17-185838.32" - wire width 128 $shr$libresoc.v:185838$12290_Y - attribute \src "libresoc.v:185837.17-185837.100" - wire width 8 $sub$libresoc.v:185837$12289_Y + attribute \src "libresoc.v:185895.17-185895.32" + wire width 128 $shr$libresoc.v:185895$12086_Y + attribute \src "libresoc.v:185894.17-185894.100" + wire width 8 $sub$libresoc.v:185894$12085_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" @@ -385005,8 +349994,8 @@ module \rotl wire width 6 input 1 \b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" wire width 64 output 2 \o - attribute \src "libresoc.v:185838.17-185838.32" - cell $shr $shr$libresoc.v:185838$12290 + attribute \src "libresoc.v:185895.17-185895.32" + cell $shr $shr$libresoc.v:185895$12086 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -385014,10 +350003,10 @@ module \rotl parameter \Y_WIDTH 128 connect \A { \a \a } connect \B \$2 - connect \Y $shr$libresoc.v:185838$12290_Y + connect \Y $shr$libresoc.v:185895$12086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - cell $sub $sub$libresoc.v:185837$12289 + cell $sub $sub$libresoc.v:185894$12085 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -385025,43 +350014,43 @@ module \rotl parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \b - connect \Y $sub$libresoc.v:185837$12289_Y + connect \Y $sub$libresoc.v:185894$12085_Y end - connect \$2 $sub$libresoc.v:185837$12289_Y - connect \$1 $shr$libresoc.v:185838$12290_Y [63:0] + connect \$2 $sub$libresoc.v:185894$12085_Y + connect \$1 $shr$libresoc.v:185895$12086_Y [63:0] connect \o \$1 end -attribute \src "libresoc.v:185844.1-185902.10" +attribute \src "libresoc.v:185901.1-185959.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l" attribute \generator "nMigen" module \rst_l - attribute \src "libresoc.v:185845.7-185845.20" + attribute \src "libresoc.v:185902.7-185902.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185890.3-185898.6" - wire $0\q_int$next[0:0]$12301 - attribute \src "libresoc.v:185888.3-185889.27" + attribute \src "libresoc.v:185947.3-185955.6" + wire $0\q_int$next[0:0]$12097 + attribute \src "libresoc.v:185945.3-185946.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185890.3-185898.6" - wire $1\q_int$next[0:0]$12302 - attribute \src "libresoc.v:185867.7-185867.19" + attribute \src "libresoc.v:185947.3-185955.6" + wire $1\q_int$next[0:0]$12098 + attribute \src "libresoc.v:185924.7-185924.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185880.17-185880.96" - wire $and$libresoc.v:185880$12291_Y - attribute \src "libresoc.v:185885.17-185885.96" - wire $and$libresoc.v:185885$12296_Y - attribute \src "libresoc.v:185882.18-185882.93" - wire $not$libresoc.v:185882$12293_Y - attribute \src "libresoc.v:185884.17-185884.92" - wire $not$libresoc.v:185884$12295_Y - attribute \src "libresoc.v:185887.17-185887.92" - wire $not$libresoc.v:185887$12298_Y - attribute \src "libresoc.v:185881.18-185881.98" - wire $or$libresoc.v:185881$12292_Y - attribute \src "libresoc.v:185883.18-185883.99" - wire $or$libresoc.v:185883$12294_Y - attribute \src "libresoc.v:185886.17-185886.97" - wire $or$libresoc.v:185886$12297_Y + attribute \src "libresoc.v:185937.17-185937.96" + wire $and$libresoc.v:185937$12087_Y + attribute \src "libresoc.v:185942.17-185942.96" + wire $and$libresoc.v:185942$12092_Y + attribute \src "libresoc.v:185939.18-185939.93" + wire $not$libresoc.v:185939$12089_Y + attribute \src "libresoc.v:185941.17-185941.92" + wire $not$libresoc.v:185941$12091_Y + attribute \src "libresoc.v:185944.17-185944.92" + wire $not$libresoc.v:185944$12094_Y + attribute \src "libresoc.v:185938.18-185938.98" + wire $or$libresoc.v:185938$12088_Y + attribute \src "libresoc.v:185940.18-185940.99" + wire $or$libresoc.v:185940$12090_Y + attribute \src "libresoc.v:185943.17-185943.97" + wire $or$libresoc.v:185943$12093_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385078,11 +350067,11 @@ module \rst_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:185845.7-185845.15" + attribute \src "libresoc.v:185902.7-185902.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -385099,7 +350088,7 @@ module \rst_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185880$12291 + cell $and $and$libresoc.v:185937$12087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385107,10 +350096,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185880$12291_Y + connect \Y $and$libresoc.v:185937$12087_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185885$12296 + cell $and $and$libresoc.v:185942$12092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385118,34 +350107,34 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185885$12296_Y + connect \Y $and$libresoc.v:185942$12092_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185882$12293 + cell $not $not$libresoc.v:185939$12089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:185882$12293_Y + connect \Y $not$libresoc.v:185939$12089_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185884$12295 + cell $not $not$libresoc.v:185941$12091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:185884$12295_Y + connect \Y $not$libresoc.v:185941$12091_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185887$12298 + cell $not $not$libresoc.v:185944$12094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:185887$12298_Y + connect \Y $not$libresoc.v:185944$12094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185881$12292 + cell $or $or$libresoc.v:185938$12088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385153,10 +350142,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:185881$12292_Y + connect \Y $or$libresoc.v:185938$12088_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185883$12294 + cell $or $or$libresoc.v:185940$12090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385164,10 +350153,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:185883$12294_Y + connect \Y $or$libresoc.v:185940$12090_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185886$12297 + cell $or $or$libresoc.v:185943$12093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385175,39 +350164,39 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:185886$12297_Y + connect \Y $or$libresoc.v:185943$12093_Y end - attribute \src "libresoc.v:185845.7-185845.20" - process $proc$libresoc.v:185845$12303 + attribute \src "libresoc.v:185902.7-185902.20" + process $proc$libresoc.v:185902$12099 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185867.7-185867.19" - process $proc$libresoc.v:185867$12304 + attribute \src "libresoc.v:185924.7-185924.19" + process $proc$libresoc.v:185924$12100 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185888.3-185889.27" - process $proc$libresoc.v:185888$12299 + attribute \src "libresoc.v:185945.3-185946.27" + process $proc$libresoc.v:185945$12095 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185890.3-185898.6" - process $proc$libresoc.v:185890$12300 + attribute \src "libresoc.v:185947.3-185955.6" + process $proc$libresoc.v:185947$12096 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12301 $1\q_int$next[0:0]$12302 - attribute \src "libresoc.v:185891.5-185891.29" + assign $0\q_int$next[0:0]$12097 $1\q_int$next[0:0]$12098 + attribute \src "libresoc.v:185948.5-185948.29" switch \initial - attribute \src "libresoc.v:185891.9-185891.17" + attribute \src "libresoc.v:185948.9-185948.17" case 1'1 case end @@ -385216,56 +350205,56 @@ module \rst_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12302 1'0 + assign $1\q_int$next[0:0]$12098 1'0 case - assign $1\q_int$next[0:0]$12302 \$5 + assign $1\q_int$next[0:0]$12098 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12301 + update \q_int$next $0\q_int$next[0:0]$12097 end - connect \$9 $and$libresoc.v:185880$12291_Y - connect \$11 $or$libresoc.v:185881$12292_Y - connect \$13 $not$libresoc.v:185882$12293_Y - connect \$15 $or$libresoc.v:185883$12294_Y - connect \$1 $not$libresoc.v:185884$12295_Y - connect \$3 $and$libresoc.v:185885$12296_Y - connect \$5 $or$libresoc.v:185886$12297_Y - connect \$7 $not$libresoc.v:185887$12298_Y + connect \$9 $and$libresoc.v:185937$12087_Y + connect \$11 $or$libresoc.v:185938$12088_Y + connect \$13 $not$libresoc.v:185939$12089_Y + connect \$15 $or$libresoc.v:185940$12090_Y + connect \$1 $not$libresoc.v:185941$12091_Y + connect \$3 $and$libresoc.v:185942$12092_Y + connect \$5 $or$libresoc.v:185943$12093_Y + connect \$7 $not$libresoc.v:185944$12094_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:185906.1-185964.10" +attribute \src "libresoc.v:185963.1-186021.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" attribute \generator "nMigen" module \rst_l$104 - attribute \src "libresoc.v:185907.7-185907.20" + attribute \src "libresoc.v:185964.7-185964.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185952.3-185960.6" - wire $0\q_int$next[0:0]$12315 - attribute \src "libresoc.v:185950.3-185951.27" + attribute \src "libresoc.v:186009.3-186017.6" + wire $0\q_int$next[0:0]$12111 + attribute \src "libresoc.v:186007.3-186008.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185952.3-185960.6" - wire $1\q_int$next[0:0]$12316 - attribute \src "libresoc.v:185929.7-185929.19" + attribute \src "libresoc.v:186009.3-186017.6" + wire $1\q_int$next[0:0]$12112 + attribute \src "libresoc.v:185986.7-185986.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185942.17-185942.96" - wire $and$libresoc.v:185942$12305_Y - attribute \src "libresoc.v:185947.17-185947.96" - wire $and$libresoc.v:185947$12310_Y - attribute \src "libresoc.v:185944.18-185944.93" - wire $not$libresoc.v:185944$12307_Y - attribute \src "libresoc.v:185946.17-185946.92" - wire $not$libresoc.v:185946$12309_Y - attribute \src "libresoc.v:185949.17-185949.92" - wire $not$libresoc.v:185949$12312_Y - attribute \src "libresoc.v:185943.18-185943.98" - wire $or$libresoc.v:185943$12306_Y - attribute \src "libresoc.v:185945.18-185945.99" - wire $or$libresoc.v:185945$12308_Y - attribute \src "libresoc.v:185948.17-185948.97" - wire $or$libresoc.v:185948$12311_Y + attribute \src "libresoc.v:185999.17-185999.96" + wire $and$libresoc.v:185999$12101_Y + attribute \src "libresoc.v:186004.17-186004.96" + wire $and$libresoc.v:186004$12106_Y + attribute \src "libresoc.v:186001.18-186001.93" + wire $not$libresoc.v:186001$12103_Y + attribute \src "libresoc.v:186003.17-186003.92" + wire $not$libresoc.v:186003$12105_Y + attribute \src "libresoc.v:186006.17-186006.92" + wire $not$libresoc.v:186006$12108_Y + attribute \src "libresoc.v:186000.18-186000.98" + wire $or$libresoc.v:186000$12102_Y + attribute \src "libresoc.v:186002.18-186002.99" + wire $or$libresoc.v:186002$12104_Y + attribute \src "libresoc.v:186005.17-186005.97" + wire $or$libresoc.v:186005$12107_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385282,11 +350271,11 @@ module \rst_l$104 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:185907.7-185907.15" + attribute \src "libresoc.v:185964.7-185964.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -385303,7 +350292,7 @@ module \rst_l$104 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185942$12305 + cell $and $and$libresoc.v:185999$12101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385311,10 +350300,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185942$12305_Y + connect \Y $and$libresoc.v:185999$12101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185947$12310 + cell $and $and$libresoc.v:186004$12106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385322,34 +350311,34 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185947$12310_Y + connect \Y $and$libresoc.v:186004$12106_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185944$12307 + cell $not $not$libresoc.v:186001$12103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:185944$12307_Y + connect \Y $not$libresoc.v:186001$12103_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185946$12309 + cell $not $not$libresoc.v:186003$12105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:185946$12309_Y + connect \Y $not$libresoc.v:186003$12105_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185949$12312 + cell $not $not$libresoc.v:186006$12108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:185949$12312_Y + connect \Y $not$libresoc.v:186006$12108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185943$12306 + cell $or $or$libresoc.v:186000$12102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385357,10 +350346,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:185943$12306_Y + connect \Y $or$libresoc.v:186000$12102_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185945$12308 + cell $or $or$libresoc.v:186002$12104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385368,10 +350357,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:185945$12308_Y + connect \Y $or$libresoc.v:186002$12104_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185948$12311 + cell $or $or$libresoc.v:186005$12107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385379,39 +350368,39 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:185948$12311_Y + connect \Y $or$libresoc.v:186005$12107_Y end - attribute \src "libresoc.v:185907.7-185907.20" - process $proc$libresoc.v:185907$12317 + attribute \src "libresoc.v:185964.7-185964.20" + process $proc$libresoc.v:185964$12113 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185929.7-185929.19" - process $proc$libresoc.v:185929$12318 + attribute \src "libresoc.v:185986.7-185986.19" + process $proc$libresoc.v:185986$12114 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185950.3-185951.27" - process $proc$libresoc.v:185950$12313 + attribute \src "libresoc.v:186007.3-186008.27" + process $proc$libresoc.v:186007$12109 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185952.3-185960.6" - process $proc$libresoc.v:185952$12314 + attribute \src "libresoc.v:186009.3-186017.6" + process $proc$libresoc.v:186009$12110 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12315 $1\q_int$next[0:0]$12316 - attribute \src "libresoc.v:185953.5-185953.29" + assign $0\q_int$next[0:0]$12111 $1\q_int$next[0:0]$12112 + attribute \src "libresoc.v:186010.5-186010.29" switch \initial - attribute \src "libresoc.v:185953.9-185953.17" + attribute \src "libresoc.v:186010.9-186010.17" case 1'1 case end @@ -385420,56 +350409,56 @@ module \rst_l$104 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12316 1'0 + assign $1\q_int$next[0:0]$12112 1'0 case - assign $1\q_int$next[0:0]$12316 \$5 + assign $1\q_int$next[0:0]$12112 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12315 + update \q_int$next $0\q_int$next[0:0]$12111 end - connect \$9 $and$libresoc.v:185942$12305_Y - connect \$11 $or$libresoc.v:185943$12306_Y - connect \$13 $not$libresoc.v:185944$12307_Y - connect \$15 $or$libresoc.v:185945$12308_Y - connect \$1 $not$libresoc.v:185946$12309_Y - connect \$3 $and$libresoc.v:185947$12310_Y - connect \$5 $or$libresoc.v:185948$12311_Y - connect \$7 $not$libresoc.v:185949$12312_Y + connect \$9 $and$libresoc.v:185999$12101_Y + connect \$11 $or$libresoc.v:186000$12102_Y + connect \$13 $not$libresoc.v:186001$12103_Y + connect \$15 $or$libresoc.v:186002$12104_Y + connect \$1 $not$libresoc.v:186003$12105_Y + connect \$3 $and$libresoc.v:186004$12106_Y + connect \$5 $or$libresoc.v:186005$12107_Y + connect \$7 $not$libresoc.v:186006$12108_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:185968.1-186026.10" +attribute \src "libresoc.v:186025.1-186083.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l" attribute \generator "nMigen" module \rst_l$122 - attribute \src "libresoc.v:185969.7-185969.20" + attribute \src "libresoc.v:186026.7-186026.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186014.3-186022.6" - wire $0\q_int$next[0:0]$12329 - attribute \src "libresoc.v:186012.3-186013.27" + attribute \src "libresoc.v:186071.3-186079.6" + wire $0\q_int$next[0:0]$12125 + attribute \src "libresoc.v:186069.3-186070.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186014.3-186022.6" - wire $1\q_int$next[0:0]$12330 - attribute \src "libresoc.v:185991.7-185991.19" + attribute \src "libresoc.v:186071.3-186079.6" + wire $1\q_int$next[0:0]$12126 + attribute \src "libresoc.v:186048.7-186048.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186004.17-186004.96" - wire $and$libresoc.v:186004$12319_Y - attribute \src "libresoc.v:186009.17-186009.96" - wire $and$libresoc.v:186009$12324_Y - attribute \src "libresoc.v:186006.18-186006.93" - wire $not$libresoc.v:186006$12321_Y - attribute \src "libresoc.v:186008.17-186008.92" - wire $not$libresoc.v:186008$12323_Y - attribute \src "libresoc.v:186011.17-186011.92" - wire $not$libresoc.v:186011$12326_Y - attribute \src "libresoc.v:186005.18-186005.98" - wire $or$libresoc.v:186005$12320_Y - attribute \src "libresoc.v:186007.18-186007.99" - wire $or$libresoc.v:186007$12322_Y - attribute \src "libresoc.v:186010.17-186010.97" - wire $or$libresoc.v:186010$12325_Y + attribute \src "libresoc.v:186061.17-186061.96" + wire $and$libresoc.v:186061$12115_Y + attribute \src "libresoc.v:186066.17-186066.96" + wire $and$libresoc.v:186066$12120_Y + attribute \src "libresoc.v:186063.18-186063.93" + wire $not$libresoc.v:186063$12117_Y + attribute \src "libresoc.v:186065.17-186065.92" + wire $not$libresoc.v:186065$12119_Y + attribute \src "libresoc.v:186068.17-186068.92" + wire $not$libresoc.v:186068$12122_Y + attribute \src "libresoc.v:186062.18-186062.98" + wire $or$libresoc.v:186062$12116_Y + attribute \src "libresoc.v:186064.18-186064.99" + wire $or$libresoc.v:186064$12118_Y + attribute \src "libresoc.v:186067.17-186067.97" + wire $or$libresoc.v:186067$12121_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385486,11 +350475,11 @@ module \rst_l$122 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:185969.7-185969.15" + attribute \src "libresoc.v:186026.7-186026.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -385507,7 +350496,7 @@ module \rst_l$122 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186004$12319 + cell $and $and$libresoc.v:186061$12115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385515,10 +350504,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186004$12319_Y + connect \Y $and$libresoc.v:186061$12115_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186009$12324 + cell $and $and$libresoc.v:186066$12120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385526,34 +350515,34 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186009$12324_Y + connect \Y $and$libresoc.v:186066$12120_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186006$12321 + cell $not $not$libresoc.v:186063$12117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186006$12321_Y + connect \Y $not$libresoc.v:186063$12117_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186008$12323 + cell $not $not$libresoc.v:186065$12119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186008$12323_Y + connect \Y $not$libresoc.v:186065$12119_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186011$12326 + cell $not $not$libresoc.v:186068$12122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186011$12326_Y + connect \Y $not$libresoc.v:186068$12122_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186005$12320 + cell $or $or$libresoc.v:186062$12116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385561,10 +350550,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186005$12320_Y + connect \Y $or$libresoc.v:186062$12116_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186007$12322 + cell $or $or$libresoc.v:186064$12118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385572,10 +350561,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186007$12322_Y + connect \Y $or$libresoc.v:186064$12118_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186010$12325 + cell $or $or$libresoc.v:186067$12121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385583,39 +350572,39 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186010$12325_Y + connect \Y $or$libresoc.v:186067$12121_Y end - attribute \src "libresoc.v:185969.7-185969.20" - process $proc$libresoc.v:185969$12331 + attribute \src "libresoc.v:186026.7-186026.20" + process $proc$libresoc.v:186026$12127 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185991.7-185991.19" - process $proc$libresoc.v:185991$12332 + attribute \src "libresoc.v:186048.7-186048.19" + process $proc$libresoc.v:186048$12128 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186012.3-186013.27" - process $proc$libresoc.v:186012$12327 + attribute \src "libresoc.v:186069.3-186070.27" + process $proc$libresoc.v:186069$12123 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186014.3-186022.6" - process $proc$libresoc.v:186014$12328 + attribute \src "libresoc.v:186071.3-186079.6" + process $proc$libresoc.v:186071$12124 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12329 $1\q_int$next[0:0]$12330 - attribute \src "libresoc.v:186015.5-186015.29" + assign $0\q_int$next[0:0]$12125 $1\q_int$next[0:0]$12126 + attribute \src "libresoc.v:186072.5-186072.29" switch \initial - attribute \src "libresoc.v:186015.9-186015.17" + attribute \src "libresoc.v:186072.9-186072.17" case 1'1 case end @@ -385624,56 +350613,56 @@ module \rst_l$122 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12330 1'0 + assign $1\q_int$next[0:0]$12126 1'0 case - assign $1\q_int$next[0:0]$12330 \$5 + assign $1\q_int$next[0:0]$12126 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12329 + update \q_int$next $0\q_int$next[0:0]$12125 end - connect \$9 $and$libresoc.v:186004$12319_Y - connect \$11 $or$libresoc.v:186005$12320_Y - connect \$13 $not$libresoc.v:186006$12321_Y - connect \$15 $or$libresoc.v:186007$12322_Y - connect \$1 $not$libresoc.v:186008$12323_Y - connect \$3 $and$libresoc.v:186009$12324_Y - connect \$5 $or$libresoc.v:186010$12325_Y - connect \$7 $not$libresoc.v:186011$12326_Y + connect \$9 $and$libresoc.v:186061$12115_Y + connect \$11 $or$libresoc.v:186062$12116_Y + connect \$13 $not$libresoc.v:186063$12117_Y + connect \$15 $or$libresoc.v:186064$12118_Y + connect \$1 $not$libresoc.v:186065$12119_Y + connect \$3 $and$libresoc.v:186066$12120_Y + connect \$5 $or$libresoc.v:186067$12121_Y + connect \$7 $not$libresoc.v:186068$12122_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186030.1-186088.10" +attribute \src "libresoc.v:186087.1-186145.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l" attribute \generator "nMigen" module \rst_l$129 - attribute \src "libresoc.v:186031.7-186031.20" + attribute \src "libresoc.v:186088.7-186088.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186076.3-186084.6" - wire $0\q_int$next[0:0]$12343 - attribute \src "libresoc.v:186074.3-186075.27" + attribute \src "libresoc.v:186133.3-186141.6" + wire $0\q_int$next[0:0]$12139 + attribute \src "libresoc.v:186131.3-186132.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186076.3-186084.6" - wire $1\q_int$next[0:0]$12344 - attribute \src "libresoc.v:186053.7-186053.19" + attribute \src "libresoc.v:186133.3-186141.6" + wire $1\q_int$next[0:0]$12140 + attribute \src "libresoc.v:186110.7-186110.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186066.17-186066.96" - wire $and$libresoc.v:186066$12333_Y - attribute \src "libresoc.v:186071.17-186071.96" - wire $and$libresoc.v:186071$12338_Y - attribute \src "libresoc.v:186068.18-186068.93" - wire $not$libresoc.v:186068$12335_Y - attribute \src "libresoc.v:186070.17-186070.92" - wire $not$libresoc.v:186070$12337_Y - attribute \src "libresoc.v:186073.17-186073.92" - wire $not$libresoc.v:186073$12340_Y - attribute \src "libresoc.v:186067.18-186067.98" - wire $or$libresoc.v:186067$12334_Y - attribute \src "libresoc.v:186069.18-186069.99" - wire $or$libresoc.v:186069$12336_Y - attribute \src "libresoc.v:186072.17-186072.97" - wire $or$libresoc.v:186072$12339_Y + attribute \src "libresoc.v:186123.17-186123.96" + wire $and$libresoc.v:186123$12129_Y + attribute \src "libresoc.v:186128.17-186128.96" + wire $and$libresoc.v:186128$12134_Y + attribute \src "libresoc.v:186125.18-186125.93" + wire $not$libresoc.v:186125$12131_Y + attribute \src "libresoc.v:186127.17-186127.92" + wire $not$libresoc.v:186127$12133_Y + attribute \src "libresoc.v:186130.17-186130.92" + wire $not$libresoc.v:186130$12136_Y + attribute \src "libresoc.v:186124.18-186124.98" + wire $or$libresoc.v:186124$12130_Y + attribute \src "libresoc.v:186126.18-186126.99" + wire $or$libresoc.v:186126$12132_Y + attribute \src "libresoc.v:186129.17-186129.97" + wire $or$libresoc.v:186129$12135_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385690,11 +350679,11 @@ module \rst_l$129 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:186031.7-186031.15" + attribute \src "libresoc.v:186088.7-186088.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -385711,7 +350700,7 @@ module \rst_l$129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186066$12333 + cell $and $and$libresoc.v:186123$12129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385719,10 +350708,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186066$12333_Y + connect \Y $and$libresoc.v:186123$12129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186071$12338 + cell $and $and$libresoc.v:186128$12134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385730,34 +350719,34 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186071$12338_Y + connect \Y $and$libresoc.v:186128$12134_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186068$12335 + cell $not $not$libresoc.v:186125$12131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186068$12335_Y + connect \Y $not$libresoc.v:186125$12131_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186070$12337 + cell $not $not$libresoc.v:186127$12133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186070$12337_Y + connect \Y $not$libresoc.v:186127$12133_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186073$12340 + cell $not $not$libresoc.v:186130$12136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186073$12340_Y + connect \Y $not$libresoc.v:186130$12136_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186067$12334 + cell $or $or$libresoc.v:186124$12130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385765,10 +350754,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186067$12334_Y + connect \Y $or$libresoc.v:186124$12130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186069$12336 + cell $or $or$libresoc.v:186126$12132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385776,10 +350765,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186069$12336_Y + connect \Y $or$libresoc.v:186126$12132_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186072$12339 + cell $or $or$libresoc.v:186129$12135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385787,39 +350776,39 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186072$12339_Y + connect \Y $or$libresoc.v:186129$12135_Y end - attribute \src "libresoc.v:186031.7-186031.20" - process $proc$libresoc.v:186031$12345 + attribute \src "libresoc.v:186088.7-186088.20" + process $proc$libresoc.v:186088$12141 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186053.7-186053.19" - process $proc$libresoc.v:186053$12346 + attribute \src "libresoc.v:186110.7-186110.19" + process $proc$libresoc.v:186110$12142 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186074.3-186075.27" - process $proc$libresoc.v:186074$12341 + attribute \src "libresoc.v:186131.3-186132.27" + process $proc$libresoc.v:186131$12137 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186076.3-186084.6" - process $proc$libresoc.v:186076$12342 + attribute \src "libresoc.v:186133.3-186141.6" + process $proc$libresoc.v:186133$12138 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12343 $1\q_int$next[0:0]$12344 - attribute \src "libresoc.v:186077.5-186077.29" + assign $0\q_int$next[0:0]$12139 $1\q_int$next[0:0]$12140 + attribute \src "libresoc.v:186134.5-186134.29" switch \initial - attribute \src "libresoc.v:186077.9-186077.17" + attribute \src "libresoc.v:186134.9-186134.17" case 1'1 case end @@ -385828,56 +350817,56 @@ module \rst_l$129 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12344 1'0 + assign $1\q_int$next[0:0]$12140 1'0 case - assign $1\q_int$next[0:0]$12344 \$5 + assign $1\q_int$next[0:0]$12140 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12343 + update \q_int$next $0\q_int$next[0:0]$12139 end - connect \$9 $and$libresoc.v:186066$12333_Y - connect \$11 $or$libresoc.v:186067$12334_Y - connect \$13 $not$libresoc.v:186068$12335_Y - connect \$15 $or$libresoc.v:186069$12336_Y - connect \$1 $not$libresoc.v:186070$12337_Y - connect \$3 $and$libresoc.v:186071$12338_Y - connect \$5 $or$libresoc.v:186072$12339_Y - connect \$7 $not$libresoc.v:186073$12340_Y + connect \$9 $and$libresoc.v:186123$12129_Y + connect \$11 $or$libresoc.v:186124$12130_Y + connect \$13 $not$libresoc.v:186125$12131_Y + connect \$15 $or$libresoc.v:186126$12132_Y + connect \$1 $not$libresoc.v:186127$12133_Y + connect \$3 $and$libresoc.v:186128$12134_Y + connect \$5 $or$libresoc.v:186129$12135_Y + connect \$7 $not$libresoc.v:186130$12136_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186092.1-186150.10" +attribute \src "libresoc.v:186149.1-186207.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l" attribute \generator "nMigen" module \rst_l$13 - attribute \src "libresoc.v:186093.7-186093.20" + attribute \src "libresoc.v:186150.7-186150.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186138.3-186146.6" - wire $0\q_int$next[0:0]$12357 - attribute \src "libresoc.v:186136.3-186137.27" + attribute \src "libresoc.v:186195.3-186203.6" + wire $0\q_int$next[0:0]$12153 + attribute \src "libresoc.v:186193.3-186194.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186138.3-186146.6" - wire $1\q_int$next[0:0]$12358 - attribute \src "libresoc.v:186115.7-186115.19" + attribute \src "libresoc.v:186195.3-186203.6" + wire $1\q_int$next[0:0]$12154 + attribute \src "libresoc.v:186172.7-186172.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186128.17-186128.96" - wire $and$libresoc.v:186128$12347_Y - attribute \src "libresoc.v:186133.17-186133.96" - wire $and$libresoc.v:186133$12352_Y - attribute \src "libresoc.v:186130.18-186130.93" - wire $not$libresoc.v:186130$12349_Y - attribute \src "libresoc.v:186132.17-186132.92" - wire $not$libresoc.v:186132$12351_Y - attribute \src "libresoc.v:186135.17-186135.92" - wire $not$libresoc.v:186135$12354_Y - attribute \src "libresoc.v:186129.18-186129.98" - wire $or$libresoc.v:186129$12348_Y - attribute \src "libresoc.v:186131.18-186131.99" - wire $or$libresoc.v:186131$12350_Y - attribute \src "libresoc.v:186134.17-186134.97" - wire $or$libresoc.v:186134$12353_Y + attribute \src "libresoc.v:186185.17-186185.96" + wire $and$libresoc.v:186185$12143_Y + attribute \src "libresoc.v:186190.17-186190.96" + wire $and$libresoc.v:186190$12148_Y + attribute \src "libresoc.v:186187.18-186187.93" + wire $not$libresoc.v:186187$12145_Y + attribute \src "libresoc.v:186189.17-186189.92" + wire $not$libresoc.v:186189$12147_Y + attribute \src "libresoc.v:186192.17-186192.92" + wire $not$libresoc.v:186192$12150_Y + attribute \src "libresoc.v:186186.18-186186.98" + wire $or$libresoc.v:186186$12144_Y + attribute \src "libresoc.v:186188.18-186188.99" + wire $or$libresoc.v:186188$12146_Y + attribute \src "libresoc.v:186191.17-186191.97" + wire $or$libresoc.v:186191$12149_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385894,11 +350883,11 @@ module \rst_l$13 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:186093.7-186093.15" + attribute \src "libresoc.v:186150.7-186150.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -385915,7 +350904,7 @@ module \rst_l$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186128$12347 + cell $and $and$libresoc.v:186185$12143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385923,10 +350912,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186128$12347_Y + connect \Y $and$libresoc.v:186185$12143_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186133$12352 + cell $and $and$libresoc.v:186190$12148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385934,34 +350923,34 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186133$12352_Y + connect \Y $and$libresoc.v:186190$12148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186130$12349 + cell $not $not$libresoc.v:186187$12145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186130$12349_Y + connect \Y $not$libresoc.v:186187$12145_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186132$12351 + cell $not $not$libresoc.v:186189$12147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186132$12351_Y + connect \Y $not$libresoc.v:186189$12147_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186135$12354 + cell $not $not$libresoc.v:186192$12150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186135$12354_Y + connect \Y $not$libresoc.v:186192$12150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186129$12348 + cell $or $or$libresoc.v:186186$12144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385969,10 +350958,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186129$12348_Y + connect \Y $or$libresoc.v:186186$12144_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186131$12350 + cell $or $or$libresoc.v:186188$12146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385980,10 +350969,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186131$12350_Y + connect \Y $or$libresoc.v:186188$12146_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186134$12353 + cell $or $or$libresoc.v:186191$12149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385991,39 +350980,39 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186134$12353_Y + connect \Y $or$libresoc.v:186191$12149_Y end - attribute \src "libresoc.v:186093.7-186093.20" - process $proc$libresoc.v:186093$12359 + attribute \src "libresoc.v:186150.7-186150.20" + process $proc$libresoc.v:186150$12155 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186115.7-186115.19" - process $proc$libresoc.v:186115$12360 + attribute \src "libresoc.v:186172.7-186172.19" + process $proc$libresoc.v:186172$12156 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186136.3-186137.27" - process $proc$libresoc.v:186136$12355 + attribute \src "libresoc.v:186193.3-186194.27" + process $proc$libresoc.v:186193$12151 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186138.3-186146.6" - process $proc$libresoc.v:186138$12356 + attribute \src "libresoc.v:186195.3-186203.6" + process $proc$libresoc.v:186195$12152 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12357 $1\q_int$next[0:0]$12358 - attribute \src "libresoc.v:186139.5-186139.29" + assign $0\q_int$next[0:0]$12153 $1\q_int$next[0:0]$12154 + attribute \src "libresoc.v:186196.5-186196.29" switch \initial - attribute \src "libresoc.v:186139.9-186139.17" + attribute \src "libresoc.v:186196.9-186196.17" case 1'1 case end @@ -386032,56 +351021,56 @@ module \rst_l$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12358 1'0 + assign $1\q_int$next[0:0]$12154 1'0 case - assign $1\q_int$next[0:0]$12358 \$5 + assign $1\q_int$next[0:0]$12154 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12357 + update \q_int$next $0\q_int$next[0:0]$12153 end - connect \$9 $and$libresoc.v:186128$12347_Y - connect \$11 $or$libresoc.v:186129$12348_Y - connect \$13 $not$libresoc.v:186130$12349_Y - connect \$15 $or$libresoc.v:186131$12350_Y - connect \$1 $not$libresoc.v:186132$12351_Y - connect \$3 $and$libresoc.v:186133$12352_Y - connect \$5 $or$libresoc.v:186134$12353_Y - connect \$7 $not$libresoc.v:186135$12354_Y + connect \$9 $and$libresoc.v:186185$12143_Y + connect \$11 $or$libresoc.v:186186$12144_Y + connect \$13 $not$libresoc.v:186187$12145_Y + connect \$15 $or$libresoc.v:186188$12146_Y + connect \$1 $not$libresoc.v:186189$12147_Y + connect \$3 $and$libresoc.v:186190$12148_Y + connect \$5 $or$libresoc.v:186191$12149_Y + connect \$7 $not$libresoc.v:186192$12150_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186154.1-186212.10" +attribute \src "libresoc.v:186211.1-186269.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l" attribute \generator "nMigen" module \rst_l$26 - attribute \src "libresoc.v:186155.7-186155.20" + attribute \src "libresoc.v:186212.7-186212.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186200.3-186208.6" - wire $0\q_int$next[0:0]$12371 - attribute \src "libresoc.v:186198.3-186199.27" + attribute \src "libresoc.v:186257.3-186265.6" + wire $0\q_int$next[0:0]$12167 + attribute \src "libresoc.v:186255.3-186256.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186200.3-186208.6" - wire $1\q_int$next[0:0]$12372 - attribute \src "libresoc.v:186177.7-186177.19" + attribute \src "libresoc.v:186257.3-186265.6" + wire $1\q_int$next[0:0]$12168 + attribute \src "libresoc.v:186234.7-186234.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186190.17-186190.96" - wire $and$libresoc.v:186190$12361_Y - attribute \src "libresoc.v:186195.17-186195.96" - wire $and$libresoc.v:186195$12366_Y - attribute \src "libresoc.v:186192.18-186192.93" - wire $not$libresoc.v:186192$12363_Y - attribute \src "libresoc.v:186194.17-186194.92" - wire $not$libresoc.v:186194$12365_Y - attribute \src "libresoc.v:186197.17-186197.92" - wire $not$libresoc.v:186197$12368_Y - attribute \src "libresoc.v:186191.18-186191.98" - wire $or$libresoc.v:186191$12362_Y - attribute \src "libresoc.v:186193.18-186193.99" - wire $or$libresoc.v:186193$12364_Y - attribute \src "libresoc.v:186196.17-186196.97" - wire $or$libresoc.v:186196$12367_Y + attribute \src "libresoc.v:186247.17-186247.96" + wire $and$libresoc.v:186247$12157_Y + attribute \src "libresoc.v:186252.17-186252.96" + wire $and$libresoc.v:186252$12162_Y + attribute \src "libresoc.v:186249.18-186249.93" + wire $not$libresoc.v:186249$12159_Y + attribute \src "libresoc.v:186251.17-186251.92" + wire $not$libresoc.v:186251$12161_Y + attribute \src "libresoc.v:186254.17-186254.92" + wire $not$libresoc.v:186254$12164_Y + attribute \src "libresoc.v:186248.18-186248.98" + wire $or$libresoc.v:186248$12158_Y + attribute \src "libresoc.v:186250.18-186250.99" + wire $or$libresoc.v:186250$12160_Y + attribute \src "libresoc.v:186253.17-186253.97" + wire $or$libresoc.v:186253$12163_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -386098,11 +351087,11 @@ module \rst_l$26 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:186155.7-186155.15" + attribute \src "libresoc.v:186212.7-186212.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -386119,7 +351108,7 @@ module \rst_l$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186190$12361 + cell $and $and$libresoc.v:186247$12157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386127,10 +351116,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186190$12361_Y + connect \Y $and$libresoc.v:186247$12157_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186195$12366 + cell $and $and$libresoc.v:186252$12162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386138,34 +351127,34 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186195$12366_Y + connect \Y $and$libresoc.v:186252$12162_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186192$12363 + cell $not $not$libresoc.v:186249$12159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186192$12363_Y + connect \Y $not$libresoc.v:186249$12159_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186194$12365 + cell $not $not$libresoc.v:186251$12161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186194$12365_Y + connect \Y $not$libresoc.v:186251$12161_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186197$12368 + cell $not $not$libresoc.v:186254$12164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186197$12368_Y + connect \Y $not$libresoc.v:186254$12164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186191$12362 + cell $or $or$libresoc.v:186248$12158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386173,10 +351162,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186191$12362_Y + connect \Y $or$libresoc.v:186248$12158_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186193$12364 + cell $or $or$libresoc.v:186250$12160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386184,10 +351173,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186193$12364_Y + connect \Y $or$libresoc.v:186250$12160_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186196$12367 + cell $or $or$libresoc.v:186253$12163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386195,39 +351184,39 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186196$12367_Y + connect \Y $or$libresoc.v:186253$12163_Y end - attribute \src "libresoc.v:186155.7-186155.20" - process $proc$libresoc.v:186155$12373 + attribute \src "libresoc.v:186212.7-186212.20" + process $proc$libresoc.v:186212$12169 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186177.7-186177.19" - process $proc$libresoc.v:186177$12374 + attribute \src "libresoc.v:186234.7-186234.19" + process $proc$libresoc.v:186234$12170 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186198.3-186199.27" - process $proc$libresoc.v:186198$12369 + attribute \src "libresoc.v:186255.3-186256.27" + process $proc$libresoc.v:186255$12165 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186200.3-186208.6" - process $proc$libresoc.v:186200$12370 + attribute \src "libresoc.v:186257.3-186265.6" + process $proc$libresoc.v:186257$12166 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12371 $1\q_int$next[0:0]$12372 - attribute \src "libresoc.v:186201.5-186201.29" + assign $0\q_int$next[0:0]$12167 $1\q_int$next[0:0]$12168 + attribute \src "libresoc.v:186258.5-186258.29" switch \initial - attribute \src "libresoc.v:186201.9-186201.17" + attribute \src "libresoc.v:186258.9-186258.17" case 1'1 case end @@ -386236,56 +351225,56 @@ module \rst_l$26 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12372 1'0 + assign $1\q_int$next[0:0]$12168 1'0 case - assign $1\q_int$next[0:0]$12372 \$5 + assign $1\q_int$next[0:0]$12168 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12371 + update \q_int$next $0\q_int$next[0:0]$12167 end - connect \$9 $and$libresoc.v:186190$12361_Y - connect \$11 $or$libresoc.v:186191$12362_Y - connect \$13 $not$libresoc.v:186192$12363_Y - connect \$15 $or$libresoc.v:186193$12364_Y - connect \$1 $not$libresoc.v:186194$12365_Y - connect \$3 $and$libresoc.v:186195$12366_Y - connect \$5 $or$libresoc.v:186196$12367_Y - connect \$7 $not$libresoc.v:186197$12368_Y + connect \$9 $and$libresoc.v:186247$12157_Y + connect \$11 $or$libresoc.v:186248$12158_Y + connect \$13 $not$libresoc.v:186249$12159_Y + connect \$15 $or$libresoc.v:186250$12160_Y + connect \$1 $not$libresoc.v:186251$12161_Y + connect \$3 $and$libresoc.v:186252$12162_Y + connect \$5 $or$libresoc.v:186253$12163_Y + connect \$7 $not$libresoc.v:186254$12164_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186216.1-186274.10" +attribute \src "libresoc.v:186273.1-186331.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l" attribute \generator "nMigen" module \rst_l$42 - attribute \src "libresoc.v:186217.7-186217.20" + attribute \src "libresoc.v:186274.7-186274.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186262.3-186270.6" - wire $0\q_int$next[0:0]$12385 - attribute \src "libresoc.v:186260.3-186261.27" + attribute \src "libresoc.v:186319.3-186327.6" + wire $0\q_int$next[0:0]$12181 + attribute \src "libresoc.v:186317.3-186318.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186262.3-186270.6" - wire $1\q_int$next[0:0]$12386 - attribute \src "libresoc.v:186239.7-186239.19" + attribute \src "libresoc.v:186319.3-186327.6" + wire $1\q_int$next[0:0]$12182 + attribute \src "libresoc.v:186296.7-186296.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186252.17-186252.96" - wire $and$libresoc.v:186252$12375_Y - attribute \src "libresoc.v:186257.17-186257.96" - wire $and$libresoc.v:186257$12380_Y - attribute \src "libresoc.v:186254.18-186254.93" - wire $not$libresoc.v:186254$12377_Y - attribute \src "libresoc.v:186256.17-186256.92" - wire $not$libresoc.v:186256$12379_Y - attribute \src "libresoc.v:186259.17-186259.92" - wire $not$libresoc.v:186259$12382_Y - attribute \src "libresoc.v:186253.18-186253.98" - wire $or$libresoc.v:186253$12376_Y - attribute \src "libresoc.v:186255.18-186255.99" - wire $or$libresoc.v:186255$12378_Y - attribute \src "libresoc.v:186258.17-186258.97" - wire $or$libresoc.v:186258$12381_Y + attribute \src "libresoc.v:186309.17-186309.96" + wire $and$libresoc.v:186309$12171_Y + attribute \src "libresoc.v:186314.17-186314.96" + wire $and$libresoc.v:186314$12176_Y + attribute \src "libresoc.v:186311.18-186311.93" + wire $not$libresoc.v:186311$12173_Y + attribute \src "libresoc.v:186313.17-186313.92" + wire $not$libresoc.v:186313$12175_Y + attribute \src "libresoc.v:186316.17-186316.92" + wire $not$libresoc.v:186316$12178_Y + attribute \src "libresoc.v:186310.18-186310.98" + wire $or$libresoc.v:186310$12172_Y + attribute \src "libresoc.v:186312.18-186312.99" + wire $or$libresoc.v:186312$12174_Y + attribute \src "libresoc.v:186315.17-186315.97" + wire $or$libresoc.v:186315$12177_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -386302,11 +351291,11 @@ module \rst_l$42 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:186217.7-186217.15" + attribute \src "libresoc.v:186274.7-186274.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -386323,7 +351312,7 @@ module \rst_l$42 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186252$12375 + cell $and $and$libresoc.v:186309$12171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386331,10 +351320,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186252$12375_Y + connect \Y $and$libresoc.v:186309$12171_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186257$12380 + cell $and $and$libresoc.v:186314$12176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386342,34 +351331,34 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186257$12380_Y + connect \Y $and$libresoc.v:186314$12176_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186254$12377 + cell $not $not$libresoc.v:186311$12173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186254$12377_Y + connect \Y $not$libresoc.v:186311$12173_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186256$12379 + cell $not $not$libresoc.v:186313$12175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186256$12379_Y + connect \Y $not$libresoc.v:186313$12175_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186259$12382 + cell $not $not$libresoc.v:186316$12178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186259$12382_Y + connect \Y $not$libresoc.v:186316$12178_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186253$12376 + cell $or $or$libresoc.v:186310$12172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386377,10 +351366,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186253$12376_Y + connect \Y $or$libresoc.v:186310$12172_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186255$12378 + cell $or $or$libresoc.v:186312$12174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386388,10 +351377,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186255$12378_Y + connect \Y $or$libresoc.v:186312$12174_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186258$12381 + cell $or $or$libresoc.v:186315$12177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386399,39 +351388,39 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186258$12381_Y + connect \Y $or$libresoc.v:186315$12177_Y end - attribute \src "libresoc.v:186217.7-186217.20" - process $proc$libresoc.v:186217$12387 + attribute \src "libresoc.v:186274.7-186274.20" + process $proc$libresoc.v:186274$12183 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186239.7-186239.19" - process $proc$libresoc.v:186239$12388 + attribute \src "libresoc.v:186296.7-186296.19" + process $proc$libresoc.v:186296$12184 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186260.3-186261.27" - process $proc$libresoc.v:186260$12383 + attribute \src "libresoc.v:186317.3-186318.27" + process $proc$libresoc.v:186317$12179 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186262.3-186270.6" - process $proc$libresoc.v:186262$12384 + attribute \src "libresoc.v:186319.3-186327.6" + process $proc$libresoc.v:186319$12180 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12385 $1\q_int$next[0:0]$12386 - attribute \src "libresoc.v:186263.5-186263.29" + assign $0\q_int$next[0:0]$12181 $1\q_int$next[0:0]$12182 + attribute \src "libresoc.v:186320.5-186320.29" switch \initial - attribute \src "libresoc.v:186263.9-186263.17" + attribute \src "libresoc.v:186320.9-186320.17" case 1'1 case end @@ -386440,56 +351429,56 @@ module \rst_l$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12386 1'0 + assign $1\q_int$next[0:0]$12182 1'0 case - assign $1\q_int$next[0:0]$12386 \$5 + assign $1\q_int$next[0:0]$12182 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12385 + update \q_int$next $0\q_int$next[0:0]$12181 end - connect \$9 $and$libresoc.v:186252$12375_Y - connect \$11 $or$libresoc.v:186253$12376_Y - connect \$13 $not$libresoc.v:186254$12377_Y - connect \$15 $or$libresoc.v:186255$12378_Y - connect \$1 $not$libresoc.v:186256$12379_Y - connect \$3 $and$libresoc.v:186257$12380_Y - connect \$5 $or$libresoc.v:186258$12381_Y - connect \$7 $not$libresoc.v:186259$12382_Y + connect \$9 $and$libresoc.v:186309$12171_Y + connect \$11 $or$libresoc.v:186310$12172_Y + connect \$13 $not$libresoc.v:186311$12173_Y + connect \$15 $or$libresoc.v:186312$12174_Y + connect \$1 $not$libresoc.v:186313$12175_Y + connect \$3 $and$libresoc.v:186314$12176_Y + connect \$5 $or$libresoc.v:186315$12177_Y + connect \$7 $not$libresoc.v:186316$12178_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186278.1-186336.10" +attribute \src "libresoc.v:186335.1-186393.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l" attribute \generator "nMigen" module \rst_l$58 - attribute \src "libresoc.v:186279.7-186279.20" + attribute \src "libresoc.v:186336.7-186336.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186324.3-186332.6" - wire $0\q_int$next[0:0]$12399 - attribute \src "libresoc.v:186322.3-186323.27" + attribute \src "libresoc.v:186381.3-186389.6" + wire $0\q_int$next[0:0]$12195 + attribute \src "libresoc.v:186379.3-186380.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186324.3-186332.6" - wire $1\q_int$next[0:0]$12400 - attribute \src "libresoc.v:186301.7-186301.19" + attribute \src "libresoc.v:186381.3-186389.6" + wire $1\q_int$next[0:0]$12196 + attribute \src "libresoc.v:186358.7-186358.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186314.17-186314.96" - wire $and$libresoc.v:186314$12389_Y - attribute \src "libresoc.v:186319.17-186319.96" - wire $and$libresoc.v:186319$12394_Y - attribute \src "libresoc.v:186316.18-186316.93" - wire $not$libresoc.v:186316$12391_Y - attribute \src "libresoc.v:186318.17-186318.92" - wire $not$libresoc.v:186318$12393_Y - attribute \src "libresoc.v:186321.17-186321.92" - wire $not$libresoc.v:186321$12396_Y - attribute \src "libresoc.v:186315.18-186315.98" - wire $or$libresoc.v:186315$12390_Y - attribute \src "libresoc.v:186317.18-186317.99" - wire $or$libresoc.v:186317$12392_Y - attribute \src "libresoc.v:186320.17-186320.97" - wire $or$libresoc.v:186320$12395_Y + attribute \src "libresoc.v:186371.17-186371.96" + wire $and$libresoc.v:186371$12185_Y + attribute \src "libresoc.v:186376.17-186376.96" + wire $and$libresoc.v:186376$12190_Y + attribute \src "libresoc.v:186373.18-186373.93" + wire $not$libresoc.v:186373$12187_Y + attribute \src "libresoc.v:186375.17-186375.92" + wire $not$libresoc.v:186375$12189_Y + attribute \src "libresoc.v:186378.17-186378.92" + wire $not$libresoc.v:186378$12192_Y + attribute \src "libresoc.v:186372.18-186372.98" + wire $or$libresoc.v:186372$12186_Y + attribute \src "libresoc.v:186374.18-186374.99" + wire $or$libresoc.v:186374$12188_Y + attribute \src "libresoc.v:186377.17-186377.97" + wire $or$libresoc.v:186377$12191_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -386506,11 +351495,11 @@ module \rst_l$58 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:186279.7-186279.15" + attribute \src "libresoc.v:186336.7-186336.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -386527,7 +351516,7 @@ module \rst_l$58 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186314$12389 + cell $and $and$libresoc.v:186371$12185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386535,10 +351524,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186314$12389_Y + connect \Y $and$libresoc.v:186371$12185_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186319$12394 + cell $and $and$libresoc.v:186376$12190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386546,34 +351535,34 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186319$12394_Y + connect \Y $and$libresoc.v:186376$12190_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186316$12391 + cell $not $not$libresoc.v:186373$12187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186316$12391_Y + connect \Y $not$libresoc.v:186373$12187_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186318$12393 + cell $not $not$libresoc.v:186375$12189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186318$12393_Y + connect \Y $not$libresoc.v:186375$12189_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186321$12396 + cell $not $not$libresoc.v:186378$12192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186321$12396_Y + connect \Y $not$libresoc.v:186378$12192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186315$12390 + cell $or $or$libresoc.v:186372$12186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386581,10 +351570,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186315$12390_Y + connect \Y $or$libresoc.v:186372$12186_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186317$12392 + cell $or $or$libresoc.v:186374$12188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386592,10 +351581,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186317$12392_Y + connect \Y $or$libresoc.v:186374$12188_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186320$12395 + cell $or $or$libresoc.v:186377$12191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386603,39 +351592,39 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186320$12395_Y + connect \Y $or$libresoc.v:186377$12191_Y end - attribute \src "libresoc.v:186279.7-186279.20" - process $proc$libresoc.v:186279$12401 + attribute \src "libresoc.v:186336.7-186336.20" + process $proc$libresoc.v:186336$12197 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186301.7-186301.19" - process $proc$libresoc.v:186301$12402 + attribute \src "libresoc.v:186358.7-186358.19" + process $proc$libresoc.v:186358$12198 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186322.3-186323.27" - process $proc$libresoc.v:186322$12397 + attribute \src "libresoc.v:186379.3-186380.27" + process $proc$libresoc.v:186379$12193 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186324.3-186332.6" - process $proc$libresoc.v:186324$12398 + attribute \src "libresoc.v:186381.3-186389.6" + process $proc$libresoc.v:186381$12194 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12399 $1\q_int$next[0:0]$12400 - attribute \src "libresoc.v:186325.5-186325.29" + assign $0\q_int$next[0:0]$12195 $1\q_int$next[0:0]$12196 + attribute \src "libresoc.v:186382.5-186382.29" switch \initial - attribute \src "libresoc.v:186325.9-186325.17" + attribute \src "libresoc.v:186382.9-186382.17" case 1'1 case end @@ -386644,56 +351633,56 @@ module \rst_l$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12400 1'0 + assign $1\q_int$next[0:0]$12196 1'0 case - assign $1\q_int$next[0:0]$12400 \$5 + assign $1\q_int$next[0:0]$12196 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12399 + update \q_int$next $0\q_int$next[0:0]$12195 end - connect \$9 $and$libresoc.v:186314$12389_Y - connect \$11 $or$libresoc.v:186315$12390_Y - connect \$13 $not$libresoc.v:186316$12391_Y - connect \$15 $or$libresoc.v:186317$12392_Y - connect \$1 $not$libresoc.v:186318$12393_Y - connect \$3 $and$libresoc.v:186319$12394_Y - connect \$5 $or$libresoc.v:186320$12395_Y - connect \$7 $not$libresoc.v:186321$12396_Y + connect \$9 $and$libresoc.v:186371$12185_Y + connect \$11 $or$libresoc.v:186372$12186_Y + connect \$13 $not$libresoc.v:186373$12187_Y + connect \$15 $or$libresoc.v:186374$12188_Y + connect \$1 $not$libresoc.v:186375$12189_Y + connect \$3 $and$libresoc.v:186376$12190_Y + connect \$5 $or$libresoc.v:186377$12191_Y + connect \$7 $not$libresoc.v:186378$12192_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186340.1-186398.10" +attribute \src "libresoc.v:186397.1-186455.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l" attribute \generator "nMigen" module \rst_l$70 - attribute \src "libresoc.v:186341.7-186341.20" + attribute \src "libresoc.v:186398.7-186398.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186386.3-186394.6" - wire $0\q_int$next[0:0]$12413 - attribute \src "libresoc.v:186384.3-186385.27" + attribute \src "libresoc.v:186443.3-186451.6" + wire $0\q_int$next[0:0]$12209 + attribute \src "libresoc.v:186441.3-186442.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186386.3-186394.6" - wire $1\q_int$next[0:0]$12414 - attribute \src "libresoc.v:186363.7-186363.19" + attribute \src "libresoc.v:186443.3-186451.6" + wire $1\q_int$next[0:0]$12210 + attribute \src "libresoc.v:186420.7-186420.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186376.17-186376.96" - wire $and$libresoc.v:186376$12403_Y - attribute \src "libresoc.v:186381.17-186381.96" - wire $and$libresoc.v:186381$12408_Y - attribute \src "libresoc.v:186378.18-186378.93" - wire $not$libresoc.v:186378$12405_Y - attribute \src "libresoc.v:186380.17-186380.92" - wire $not$libresoc.v:186380$12407_Y - attribute \src "libresoc.v:186383.17-186383.92" - wire $not$libresoc.v:186383$12410_Y - attribute \src "libresoc.v:186377.18-186377.98" - wire $or$libresoc.v:186377$12404_Y - attribute \src "libresoc.v:186379.18-186379.99" - wire $or$libresoc.v:186379$12406_Y - attribute \src "libresoc.v:186382.17-186382.97" - wire $or$libresoc.v:186382$12409_Y + attribute \src "libresoc.v:186433.17-186433.96" + wire $and$libresoc.v:186433$12199_Y + attribute \src "libresoc.v:186438.17-186438.96" + wire $and$libresoc.v:186438$12204_Y + attribute \src "libresoc.v:186435.18-186435.93" + wire $not$libresoc.v:186435$12201_Y + attribute \src "libresoc.v:186437.17-186437.92" + wire $not$libresoc.v:186437$12203_Y + attribute \src "libresoc.v:186440.17-186440.92" + wire $not$libresoc.v:186440$12206_Y + attribute \src "libresoc.v:186434.18-186434.98" + wire $or$libresoc.v:186434$12200_Y + attribute \src "libresoc.v:186436.18-186436.99" + wire $or$libresoc.v:186436$12202_Y + attribute \src "libresoc.v:186439.17-186439.97" + wire $or$libresoc.v:186439$12205_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -386710,11 +351699,11 @@ module \rst_l$70 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:186341.7-186341.15" + attribute \src "libresoc.v:186398.7-186398.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -386731,7 +351720,7 @@ module \rst_l$70 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186376$12403 + cell $and $and$libresoc.v:186433$12199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386739,10 +351728,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186376$12403_Y + connect \Y $and$libresoc.v:186433$12199_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186381$12408 + cell $and $and$libresoc.v:186438$12204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386750,34 +351739,34 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186381$12408_Y + connect \Y $and$libresoc.v:186438$12204_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186378$12405 + cell $not $not$libresoc.v:186435$12201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186378$12405_Y + connect \Y $not$libresoc.v:186435$12201_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186380$12407 + cell $not $not$libresoc.v:186437$12203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186380$12407_Y + connect \Y $not$libresoc.v:186437$12203_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186383$12410 + cell $not $not$libresoc.v:186440$12206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186383$12410_Y + connect \Y $not$libresoc.v:186440$12206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186377$12404 + cell $or $or$libresoc.v:186434$12200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386785,10 +351774,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186377$12404_Y + connect \Y $or$libresoc.v:186434$12200_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186379$12406 + cell $or $or$libresoc.v:186436$12202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386796,10 +351785,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186379$12406_Y + connect \Y $or$libresoc.v:186436$12202_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186382$12409 + cell $or $or$libresoc.v:186439$12205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386807,39 +351796,39 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186382$12409_Y + connect \Y $or$libresoc.v:186439$12205_Y end - attribute \src "libresoc.v:186341.7-186341.20" - process $proc$libresoc.v:186341$12415 + attribute \src "libresoc.v:186398.7-186398.20" + process $proc$libresoc.v:186398$12211 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186363.7-186363.19" - process $proc$libresoc.v:186363$12416 + attribute \src "libresoc.v:186420.7-186420.19" + process $proc$libresoc.v:186420$12212 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186384.3-186385.27" - process $proc$libresoc.v:186384$12411 + attribute \src "libresoc.v:186441.3-186442.27" + process $proc$libresoc.v:186441$12207 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186386.3-186394.6" - process $proc$libresoc.v:186386$12412 + attribute \src "libresoc.v:186443.3-186451.6" + process $proc$libresoc.v:186443$12208 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12413 $1\q_int$next[0:0]$12414 - attribute \src "libresoc.v:186387.5-186387.29" + assign $0\q_int$next[0:0]$12209 $1\q_int$next[0:0]$12210 + attribute \src "libresoc.v:186444.5-186444.29" switch \initial - attribute \src "libresoc.v:186387.9-186387.17" + attribute \src "libresoc.v:186444.9-186444.17" case 1'1 case end @@ -386848,56 +351837,56 @@ module \rst_l$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12414 1'0 + assign $1\q_int$next[0:0]$12210 1'0 case - assign $1\q_int$next[0:0]$12414 \$5 + assign $1\q_int$next[0:0]$12210 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12413 + update \q_int$next $0\q_int$next[0:0]$12209 end - connect \$9 $and$libresoc.v:186376$12403_Y - connect \$11 $or$libresoc.v:186377$12404_Y - connect \$13 $not$libresoc.v:186378$12405_Y - connect \$15 $or$libresoc.v:186379$12406_Y - connect \$1 $not$libresoc.v:186380$12407_Y - connect \$3 $and$libresoc.v:186381$12408_Y - connect \$5 $or$libresoc.v:186382$12409_Y - connect \$7 $not$libresoc.v:186383$12410_Y + connect \$9 $and$libresoc.v:186433$12199_Y + connect \$11 $or$libresoc.v:186434$12200_Y + connect \$13 $not$libresoc.v:186435$12201_Y + connect \$15 $or$libresoc.v:186436$12202_Y + connect \$1 $not$libresoc.v:186437$12203_Y + connect \$3 $and$libresoc.v:186438$12204_Y + connect \$5 $or$libresoc.v:186439$12205_Y + connect \$7 $not$libresoc.v:186440$12206_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186402.1-186460.10" +attribute \src "libresoc.v:186459.1-186517.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l" attribute \generator "nMigen" module \rst_l$87 - attribute \src "libresoc.v:186403.7-186403.20" + attribute \src "libresoc.v:186460.7-186460.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186448.3-186456.6" - wire $0\q_int$next[0:0]$12427 - attribute \src "libresoc.v:186446.3-186447.27" + attribute \src "libresoc.v:186505.3-186513.6" + wire $0\q_int$next[0:0]$12223 + attribute \src "libresoc.v:186503.3-186504.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186448.3-186456.6" - wire $1\q_int$next[0:0]$12428 - attribute \src "libresoc.v:186425.7-186425.19" + attribute \src "libresoc.v:186505.3-186513.6" + wire $1\q_int$next[0:0]$12224 + attribute \src "libresoc.v:186482.7-186482.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186438.17-186438.96" - wire $and$libresoc.v:186438$12417_Y - attribute \src "libresoc.v:186443.17-186443.96" - wire $and$libresoc.v:186443$12422_Y - attribute \src "libresoc.v:186440.18-186440.93" - wire $not$libresoc.v:186440$12419_Y - attribute \src "libresoc.v:186442.17-186442.92" - wire $not$libresoc.v:186442$12421_Y - attribute \src "libresoc.v:186445.17-186445.92" - wire $not$libresoc.v:186445$12424_Y - attribute \src "libresoc.v:186439.18-186439.98" - wire $or$libresoc.v:186439$12418_Y - attribute \src "libresoc.v:186441.18-186441.99" - wire $or$libresoc.v:186441$12420_Y - attribute \src "libresoc.v:186444.17-186444.97" - wire $or$libresoc.v:186444$12423_Y + attribute \src "libresoc.v:186495.17-186495.96" + wire $and$libresoc.v:186495$12213_Y + attribute \src "libresoc.v:186500.17-186500.96" + wire $and$libresoc.v:186500$12218_Y + attribute \src "libresoc.v:186497.18-186497.93" + wire $not$libresoc.v:186497$12215_Y + attribute \src "libresoc.v:186499.17-186499.92" + wire $not$libresoc.v:186499$12217_Y + attribute \src "libresoc.v:186502.17-186502.92" + wire $not$libresoc.v:186502$12220_Y + attribute \src "libresoc.v:186496.18-186496.98" + wire $or$libresoc.v:186496$12214_Y + attribute \src "libresoc.v:186498.18-186498.99" + wire $or$libresoc.v:186498$12216_Y + attribute \src "libresoc.v:186501.17-186501.97" + wire $or$libresoc.v:186501$12219_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -386914,11 +351903,11 @@ module \rst_l$87 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:186403.7-186403.15" + attribute \src "libresoc.v:186460.7-186460.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -386935,7 +351924,7 @@ module \rst_l$87 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186438$12417 + cell $and $and$libresoc.v:186495$12213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386943,10 +351932,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186438$12417_Y + connect \Y $and$libresoc.v:186495$12213_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186443$12422 + cell $and $and$libresoc.v:186500$12218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386954,34 +351943,34 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186443$12422_Y + connect \Y $and$libresoc.v:186500$12218_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186440$12419 + cell $not $not$libresoc.v:186497$12215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186440$12419_Y + connect \Y $not$libresoc.v:186497$12215_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186442$12421 + cell $not $not$libresoc.v:186499$12217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186442$12421_Y + connect \Y $not$libresoc.v:186499$12217_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186445$12424 + cell $not $not$libresoc.v:186502$12220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186445$12424_Y + connect \Y $not$libresoc.v:186502$12220_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186439$12418 + cell $or $or$libresoc.v:186496$12214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386989,10 +351978,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186439$12418_Y + connect \Y $or$libresoc.v:186496$12214_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186441$12420 + cell $or $or$libresoc.v:186498$12216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387000,10 +351989,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186441$12420_Y + connect \Y $or$libresoc.v:186498$12216_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186444$12423 + cell $or $or$libresoc.v:186501$12219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387011,39 +352000,39 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186444$12423_Y + connect \Y $or$libresoc.v:186501$12219_Y end - attribute \src "libresoc.v:186403.7-186403.20" - process $proc$libresoc.v:186403$12429 + attribute \src "libresoc.v:186460.7-186460.20" + process $proc$libresoc.v:186460$12225 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186425.7-186425.19" - process $proc$libresoc.v:186425$12430 + attribute \src "libresoc.v:186482.7-186482.19" + process $proc$libresoc.v:186482$12226 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186446.3-186447.27" - process $proc$libresoc.v:186446$12425 + attribute \src "libresoc.v:186503.3-186504.27" + process $proc$libresoc.v:186503$12221 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186448.3-186456.6" - process $proc$libresoc.v:186448$12426 + attribute \src "libresoc.v:186505.3-186513.6" + process $proc$libresoc.v:186505$12222 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12427 $1\q_int$next[0:0]$12428 - attribute \src "libresoc.v:186449.5-186449.29" + assign $0\q_int$next[0:0]$12223 $1\q_int$next[0:0]$12224 + attribute \src "libresoc.v:186506.5-186506.29" switch \initial - attribute \src "libresoc.v:186449.9-186449.17" + attribute \src "libresoc.v:186506.9-186506.17" case 1'1 case end @@ -387052,92 +352041,92 @@ module \rst_l$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12428 1'0 + assign $1\q_int$next[0:0]$12224 1'0 case - assign $1\q_int$next[0:0]$12428 \$5 + assign $1\q_int$next[0:0]$12224 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12427 + update \q_int$next $0\q_int$next[0:0]$12223 end - connect \$9 $and$libresoc.v:186438$12417_Y - connect \$11 $or$libresoc.v:186439$12418_Y - connect \$13 $not$libresoc.v:186440$12419_Y - connect \$15 $or$libresoc.v:186441$12420_Y - connect \$1 $not$libresoc.v:186442$12421_Y - connect \$3 $and$libresoc.v:186443$12422_Y - connect \$5 $or$libresoc.v:186444$12423_Y - connect \$7 $not$libresoc.v:186445$12424_Y + connect \$9 $and$libresoc.v:186495$12213_Y + connect \$11 $or$libresoc.v:186496$12214_Y + connect \$13 $not$libresoc.v:186497$12215_Y + connect \$15 $or$libresoc.v:186498$12216_Y + connect \$1 $not$libresoc.v:186499$12217_Y + connect \$3 $and$libresoc.v:186500$12218_Y + connect \$5 $or$libresoc.v:186501$12219_Y + connect \$7 $not$libresoc.v:186502$12220_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186464.1-186873.10" +attribute \src "libresoc.v:186521.1-186930.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" attribute \generator "nMigen" module \setup_stage - attribute \src "libresoc.v:186831.3-186856.6" + attribute \src "libresoc.v:186888.3-186913.6" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:186465.7-186465.20" + attribute \src "libresoc.v:186522.7-186522.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186831.3-186856.6" + attribute \src "libresoc.v:186888.3-186913.6" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:186831.3-186856.6" + attribute \src "libresoc.v:186888.3-186913.6" wire width 128 $2\dividend[127:0] - attribute \src "libresoc.v:186810.18-186810.122" - wire $and$libresoc.v:186810$12432_Y - attribute \src "libresoc.v:186812.18-186812.122" - wire $and$libresoc.v:186812$12434_Y - attribute \src "libresoc.v:186821.18-186821.105" - wire $and$libresoc.v:186821$12447_Y - attribute \src "libresoc.v:186824.18-186824.105" - wire $and$libresoc.v:186824$12450_Y - attribute \src "libresoc.v:186820.18-186820.123" - wire $eq$libresoc.v:186820$12446_Y - attribute \src "libresoc.v:186823.18-186823.123" - wire $eq$libresoc.v:186823$12449_Y - attribute \src "libresoc.v:186826.18-186826.117" - wire $eq$libresoc.v:186826$12452_Y - attribute \src "libresoc.v:186813.18-186813.97" - wire width 65 $extend$libresoc.v:186813$12435_Y - attribute \src "libresoc.v:186814.18-186814.91" - wire width 65 $extend$libresoc.v:186814$12437_Y - attribute \src "libresoc.v:186816.18-186816.97" - wire width 65 $extend$libresoc.v:186816$12440_Y - attribute \src "libresoc.v:186817.18-186817.91" - wire width 65 $extend$libresoc.v:186817$12442_Y - attribute \src "libresoc.v:186829.18-186829.99" - wire width 128 $extend$libresoc.v:186829$12455_Y - attribute \src "libresoc.v:186819.18-186819.112" - wire $ge$libresoc.v:186819$12445_Y - attribute \src "libresoc.v:186822.18-186822.124" - wire $ge$libresoc.v:186822$12448_Y - attribute \src "libresoc.v:186813.18-186813.97" - wire width 65 $neg$libresoc.v:186813$12436_Y - attribute \src "libresoc.v:186816.18-186816.97" - wire width 65 $neg$libresoc.v:186816$12441_Y - attribute \src "libresoc.v:186814.18-186814.91" - wire width 65 $pos$libresoc.v:186814$12438_Y - attribute \src "libresoc.v:186817.18-186817.91" - wire width 65 $pos$libresoc.v:186817$12443_Y - attribute \src "libresoc.v:186829.18-186829.99" - wire width 128 $pos$libresoc.v:186829$12456_Y - attribute \src "libresoc.v:186828.18-186828.117" - wire width 95 $sshl$libresoc.v:186828$12454_Y - attribute \src "libresoc.v:186830.18-186830.111" - wire width 191 $sshl$libresoc.v:186830$12457_Y - attribute \src "libresoc.v:186809.18-186809.131" - wire $ternary$libresoc.v:186809$12431_Y - attribute \src "libresoc.v:186811.18-186811.131" - wire $ternary$libresoc.v:186811$12433_Y - attribute \src "libresoc.v:186815.18-186815.119" - wire width 65 $ternary$libresoc.v:186815$12439_Y - attribute \src "libresoc.v:186818.18-186818.120" - wire width 65 $ternary$libresoc.v:186818$12444_Y - attribute \src "libresoc.v:186825.18-186825.130" - wire width 32 $ternary$libresoc.v:186825$12451_Y - attribute \src "libresoc.v:186827.18-186827.131" - wire width 32 $ternary$libresoc.v:186827$12453_Y + attribute \src "libresoc.v:186867.18-186867.122" + wire $and$libresoc.v:186867$12228_Y + attribute \src "libresoc.v:186869.18-186869.122" + wire $and$libresoc.v:186869$12230_Y + attribute \src "libresoc.v:186878.18-186878.105" + wire $and$libresoc.v:186878$12243_Y + attribute \src "libresoc.v:186881.18-186881.105" + wire $and$libresoc.v:186881$12246_Y + attribute \src "libresoc.v:186877.18-186877.123" + wire $eq$libresoc.v:186877$12242_Y + attribute \src "libresoc.v:186880.18-186880.123" + wire $eq$libresoc.v:186880$12245_Y + attribute \src "libresoc.v:186883.18-186883.117" + wire $eq$libresoc.v:186883$12248_Y + attribute \src "libresoc.v:186870.18-186870.97" + wire width 65 $extend$libresoc.v:186870$12231_Y + attribute \src "libresoc.v:186871.18-186871.91" + wire width 65 $extend$libresoc.v:186871$12233_Y + attribute \src "libresoc.v:186873.18-186873.97" + wire width 65 $extend$libresoc.v:186873$12236_Y + attribute \src "libresoc.v:186874.18-186874.91" + wire width 65 $extend$libresoc.v:186874$12238_Y + attribute \src "libresoc.v:186886.18-186886.99" + wire width 128 $extend$libresoc.v:186886$12251_Y + attribute \src "libresoc.v:186876.18-186876.112" + wire $ge$libresoc.v:186876$12241_Y + attribute \src "libresoc.v:186879.18-186879.124" + wire $ge$libresoc.v:186879$12244_Y + attribute \src "libresoc.v:186870.18-186870.97" + wire width 65 $neg$libresoc.v:186870$12232_Y + attribute \src "libresoc.v:186873.18-186873.97" + wire width 65 $neg$libresoc.v:186873$12237_Y + attribute \src "libresoc.v:186871.18-186871.91" + wire width 65 $pos$libresoc.v:186871$12234_Y + attribute \src "libresoc.v:186874.18-186874.91" + wire width 65 $pos$libresoc.v:186874$12239_Y + attribute \src "libresoc.v:186886.18-186886.99" + wire width 128 $pos$libresoc.v:186886$12252_Y + attribute \src "libresoc.v:186885.18-186885.117" + wire width 95 $sshl$libresoc.v:186885$12250_Y + attribute \src "libresoc.v:186887.18-186887.111" + wire width 191 $sshl$libresoc.v:186887$12253_Y + attribute \src "libresoc.v:186866.18-186866.131" + wire $ternary$libresoc.v:186866$12227_Y + attribute \src "libresoc.v:186868.18-186868.131" + wire $ternary$libresoc.v:186868$12229_Y + attribute \src "libresoc.v:186872.18-186872.119" + wire width 65 $ternary$libresoc.v:186872$12235_Y + attribute \src "libresoc.v:186875.18-186875.120" + wire width 65 $ternary$libresoc.v:186875$12240_Y + attribute \src "libresoc.v:186882.18-186882.130" + wire width 32 $ternary$libresoc.v:186882$12247_Y + attribute \src "libresoc.v:186884.18-186884.131" + wire width 32 $ternary$libresoc.v:186884$12249_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" @@ -387206,7 +352195,7 @@ module \setup_stage wire output 42 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 output 48 \divisor_radicand - attribute \src "libresoc.v:186465.7-186465.15" + attribute \src "libresoc.v:186522.7-186522.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -387483,7 +352472,7 @@ module \setup_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 41 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $and $and$libresoc.v:186810$12432 + cell $and $and$libresoc.v:186867$12228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387491,10 +352480,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$21 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:186810$12432_Y + connect \Y $and$libresoc.v:186867$12228_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $and $and$libresoc.v:186812$12434 + cell $and $and$libresoc.v:186869$12230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387502,10 +352491,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$25 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:186812$12434_Y + connect \Y $and$libresoc.v:186869$12230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $and $and$libresoc.v:186821$12447 + cell $and $and$libresoc.v:186878$12243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387513,10 +352502,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$43 connect \B \$45 - connect \Y $and$libresoc.v:186821$12447_Y + connect \Y $and$libresoc.v:186878$12243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $and $and$libresoc.v:186824$12450 + cell $and $and$libresoc.v:186881$12246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387524,10 +352513,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$49 connect \B \$51 - connect \Y $and$libresoc.v:186824$12450_Y + connect \Y $and$libresoc.v:186881$12246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $eq $eq$libresoc.v:186820$12446 + cell $eq $eq$libresoc.v:186877$12242 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387535,10 +352524,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:186820$12446_Y + connect \Y $eq$libresoc.v:186877$12242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $eq $eq$libresoc.v:186823$12449 + cell $eq $eq$libresoc.v:186880$12245 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387546,10 +352535,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:186823$12449_Y + connect \Y $eq$libresoc.v:186880$12245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - cell $eq $eq$libresoc.v:186826$12452 + cell $eq $eq$libresoc.v:186883$12248 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -387557,50 +352546,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \divisor_radicand connect \B 1'0 - connect \Y $eq$libresoc.v:186826$12452_Y + connect \Y $eq$libresoc.v:186883$12248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $pos $extend$libresoc.v:186813$12435 + cell $pos $extend$libresoc.v:186870$12231 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:186813$12435_Y + connect \Y $extend$libresoc.v:186870$12231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:186814$12437 + cell $pos $extend$libresoc.v:186871$12233 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:186814$12437_Y + connect \Y $extend$libresoc.v:186871$12233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $pos $extend$libresoc.v:186816$12440 + cell $pos $extend$libresoc.v:186873$12236 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:186816$12440_Y + connect \Y $extend$libresoc.v:186873$12236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:186817$12442 + cell $pos $extend$libresoc.v:186874$12238 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:186817$12442_Y + connect \Y $extend$libresoc.v:186874$12238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $extend$libresoc.v:186829$12455 + cell $pos $extend$libresoc.v:186886$12251 parameter \A_SIGNED 0 parameter \A_WIDTH 95 parameter \Y_WIDTH 128 connect \A \$62 - connect \Y $extend$libresoc.v:186829$12455_Y + connect \Y $extend$libresoc.v:186886$12251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - cell $ge $ge$libresoc.v:186819$12445 + cell $ge $ge$libresoc.v:186876$12241 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -387608,10 +352597,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend connect \B \abs_dor - connect \Y $ge$libresoc.v:186819$12445_Y + connect \Y $ge$libresoc.v:186876$12241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - cell $ge $ge$libresoc.v:186822$12448 + cell $ge $ge$libresoc.v:186879$12244 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -387619,50 +352608,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend [31:0] connect \B \abs_dor [31:0] - connect \Y $ge$libresoc.v:186822$12448_Y + connect \Y $ge$libresoc.v:186879$12244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $neg $neg$libresoc.v:186813$12436 + cell $neg $neg$libresoc.v:186870$12232 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:186813$12435_Y - connect \Y $neg$libresoc.v:186813$12436_Y + connect \A $extend$libresoc.v:186870$12231_Y + connect \Y $neg$libresoc.v:186870$12232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $neg $neg$libresoc.v:186816$12441 + cell $neg $neg$libresoc.v:186873$12237 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:186816$12440_Y - connect \Y $neg$libresoc.v:186816$12441_Y + connect \A $extend$libresoc.v:186873$12236_Y + connect \Y $neg$libresoc.v:186873$12237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:186814$12438 + cell $pos $pos$libresoc.v:186871$12234 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:186814$12437_Y - connect \Y $pos$libresoc.v:186814$12438_Y + connect \A $extend$libresoc.v:186871$12233_Y + connect \Y $pos$libresoc.v:186871$12234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:186817$12443 + cell $pos $pos$libresoc.v:186874$12239 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:186817$12442_Y - connect \Y $pos$libresoc.v:186817$12443_Y + connect \A $extend$libresoc.v:186874$12238_Y + connect \Y $pos$libresoc.v:186874$12239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $pos$libresoc.v:186829$12456 + cell $pos $pos$libresoc.v:186886$12252 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 128 - connect \A $extend$libresoc.v:186829$12455_Y - connect \Y $pos$libresoc.v:186829$12456_Y + connect \A $extend$libresoc.v:186886$12251_Y + connect \Y $pos$libresoc.v:186886$12252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $sshl $sshl$libresoc.v:186828$12454 + cell $sshl $sshl$libresoc.v:186885$12250 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -387670,10 +352659,10 @@ module \setup_stage parameter \Y_WIDTH 95 connect \A \abs_dend [31:0] connect \B 6'100000 - connect \Y $sshl$libresoc.v:186828$12454_Y + connect \Y $sshl$libresoc.v:186885$12250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - cell $sshl $sshl$libresoc.v:186830$12457 + cell $sshl $sshl$libresoc.v:186887$12253 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -387681,72 +352670,72 @@ module \setup_stage parameter \Y_WIDTH 191 connect \A \abs_dend connect \B 7'1000000 - connect \Y $sshl$libresoc.v:186830$12457_Y + connect \Y $sshl$libresoc.v:186887$12253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $mux $ternary$libresoc.v:186809$12431 + cell $mux $ternary$libresoc.v:186866$12227 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:186809$12431_Y + connect \Y $ternary$libresoc.v:186866$12227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $mux $ternary$libresoc.v:186811$12433 + cell $mux $ternary$libresoc.v:186868$12229 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:186811$12433_Y + connect \Y $ternary$libresoc.v:186868$12229_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $mux $ternary$libresoc.v:186815$12439 + cell $mux $ternary$libresoc.v:186872$12235 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \divisor_neg - connect \Y $ternary$libresoc.v:186815$12439_Y + connect \Y $ternary$libresoc.v:186872$12235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $mux $ternary$libresoc.v:186818$12444 + cell $mux $ternary$libresoc.v:186875$12240 parameter \WIDTH 65 connect \A \$39 connect \B \$37 connect \S \dividend_neg - connect \Y $ternary$libresoc.v:186818$12444_Y + connect \Y $ternary$libresoc.v:186875$12240_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:186825$12451 + cell $mux $ternary$libresoc.v:186882$12247 parameter \WIDTH 32 connect \A \abs_dor [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:186825$12451_Y + connect \Y $ternary$libresoc.v:186882$12247_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:186827$12453 + cell $mux $ternary$libresoc.v:186884$12249 parameter \WIDTH 32 connect \A \abs_dend [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:186827$12453_Y + connect \Y $ternary$libresoc.v:186884$12249_Y end - attribute \src "libresoc.v:186465.7-186465.20" - process $proc$libresoc.v:186465$12459 + attribute \src "libresoc.v:186522.7-186522.20" + process $proc$libresoc.v:186522$12255 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186831.3-186856.6" - process $proc$libresoc.v:186831$12458 + attribute \src "libresoc.v:186888.3-186913.6" + process $proc$libresoc.v:186888$12254 assign { } { } assign { } { } assign $0\dividend[127:0] $1\dividend[127:0] - attribute \src "libresoc.v:186832.5-186832.29" + attribute \src "libresoc.v:186889.5-186889.29" switch \initial - attribute \src "libresoc.v:186832.9-186832.17" + attribute \src "libresoc.v:186889.9-186889.17" case 1'1 case end @@ -387778,28 +352767,28 @@ module \setup_stage sync always update \dividend $0\dividend[127:0] end - connect \$21 $ternary$libresoc.v:186809$12431_Y - connect \$23 $and$libresoc.v:186810$12432_Y - connect \$25 $ternary$libresoc.v:186811$12433_Y - connect \$27 $and$libresoc.v:186812$12434_Y - connect \$30 $neg$libresoc.v:186813$12436_Y - connect \$32 $pos$libresoc.v:186814$12438_Y - connect \$34 $ternary$libresoc.v:186815$12439_Y - connect \$37 $neg$libresoc.v:186816$12441_Y - connect \$39 $pos$libresoc.v:186817$12443_Y - connect \$41 $ternary$libresoc.v:186818$12444_Y - connect \$43 $ge$libresoc.v:186819$12445_Y - connect \$45 $eq$libresoc.v:186820$12446_Y - connect \$47 $and$libresoc.v:186821$12447_Y - connect \$49 $ge$libresoc.v:186822$12448_Y - connect \$51 $eq$libresoc.v:186823$12449_Y - connect \$53 $and$libresoc.v:186824$12450_Y - connect \$55 $ternary$libresoc.v:186825$12451_Y - connect \$57 $eq$libresoc.v:186826$12452_Y - connect \$59 $ternary$libresoc.v:186827$12453_Y - connect \$62 $sshl$libresoc.v:186828$12454_Y - connect \$61 $pos$libresoc.v:186829$12456_Y - connect \$66 $sshl$libresoc.v:186830$12457_Y + connect \$21 $ternary$libresoc.v:186866$12227_Y + connect \$23 $and$libresoc.v:186867$12228_Y + connect \$25 $ternary$libresoc.v:186868$12229_Y + connect \$27 $and$libresoc.v:186869$12230_Y + connect \$30 $neg$libresoc.v:186870$12232_Y + connect \$32 $pos$libresoc.v:186871$12234_Y + connect \$34 $ternary$libresoc.v:186872$12235_Y + connect \$37 $neg$libresoc.v:186873$12237_Y + connect \$39 $pos$libresoc.v:186874$12239_Y + connect \$41 $ternary$libresoc.v:186875$12240_Y + connect \$43 $ge$libresoc.v:186876$12241_Y + connect \$45 $eq$libresoc.v:186877$12242_Y + connect \$47 $and$libresoc.v:186878$12243_Y + connect \$49 $ge$libresoc.v:186879$12244_Y + connect \$51 $eq$libresoc.v:186880$12245_Y + connect \$53 $and$libresoc.v:186881$12246_Y + connect \$55 $ternary$libresoc.v:186882$12247_Y + connect \$57 $eq$libresoc.v:186883$12248_Y + connect \$59 $ternary$libresoc.v:186884$12249_Y + connect \$62 $sshl$libresoc.v:186885$12250_Y + connect \$61 $pos$libresoc.v:186886$12252_Y + connect \$66 $sshl$libresoc.v:186887$12253_Y connect \$29 \$34 connect \$36 \$41 connect \$65 \$66 @@ -387817,513 +352806,513 @@ module \setup_stage connect \dividend_neg \$23 connect \operation 2'01 end -attribute \src "libresoc.v:186877.1-188084.10" +attribute \src "libresoc.v:186934.1-188141.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" attribute \generator "nMigen" module \shiftrot0 - attribute \src "libresoc.v:187655.3-187656.25" + attribute \src "libresoc.v:187712.3-187713.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:187653.3-187654.46" + attribute \src "libresoc.v:187710.3-187711.46" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:188004.3-188012.6" - wire $0\alu_l_r_alu$next[0:0]$12677 - attribute \src "libresoc.v:187571.3-187572.39" + attribute \src "libresoc.v:188061.3-188069.6" + wire $0\alu_l_r_alu$next[0:0]$12473 + attribute \src "libresoc.v:187628.3-187629.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 - attribute \src "libresoc.v:187599.3-187600.75" + attribute \src "libresoc.v:187898.3-187935.6" + wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12390 + attribute \src "libresoc.v:187656.3-187657.75" wire width 14 $0\alu_shift_rot0_sr_op__fn_unit[13:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 - attribute \src "libresoc.v:187601.3-187602.89" + attribute \src "libresoc.v:187898.3-187935.6" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12391 + attribute \src "libresoc.v:187658.3-187659.89" wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 - attribute \src "libresoc.v:187603.3-187604.85" + attribute \src "libresoc.v:187898.3-187935.6" + wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12392 + attribute \src "libresoc.v:187660.3-187661.85" wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 - attribute \src "libresoc.v:187617.3-187618.83" + attribute \src "libresoc.v:187898.3-187935.6" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12393 + attribute \src "libresoc.v:187674.3-187675.83" wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 - attribute \src "libresoc.v:187621.3-187622.77" + attribute \src "libresoc.v:187898.3-187935.6" + wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12394 + attribute \src "libresoc.v:187678.3-187679.77" wire $0\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 - attribute \src "libresoc.v:187629.3-187630.69" + attribute \src "libresoc.v:187898.3-187935.6" + wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12395 + attribute \src "libresoc.v:187686.3-187687.69" wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 - attribute \src "libresoc.v:187597.3-187598.79" + attribute \src "libresoc.v:187898.3-187935.6" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12396 + attribute \src "libresoc.v:187654.3-187655.79" wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 - attribute \src "libresoc.v:187615.3-187616.79" + attribute \src "libresoc.v:187898.3-187935.6" + wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12397 + attribute \src "libresoc.v:187672.3-187673.79" wire $0\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 - attribute \src "libresoc.v:187625.3-187626.77" + attribute \src "libresoc.v:187898.3-187935.6" + wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12398 + attribute \src "libresoc.v:187682.3-187683.77" wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 - attribute \src "libresoc.v:187627.3-187628.79" + attribute \src "libresoc.v:187898.3-187935.6" + wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12399 + attribute \src "libresoc.v:187684.3-187685.79" wire $0\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 - attribute \src "libresoc.v:187609.3-187610.73" + attribute \src "libresoc.v:187898.3-187935.6" + wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12400 + attribute \src "libresoc.v:187666.3-187667.73" wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 - attribute \src "libresoc.v:187611.3-187612.73" + attribute \src "libresoc.v:187898.3-187935.6" + wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12401 + attribute \src "libresoc.v:187668.3-187669.73" wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 - attribute \src "libresoc.v:187619.3-187620.85" + attribute \src "libresoc.v:187898.3-187935.6" + wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12402 + attribute \src "libresoc.v:187676.3-187677.85" wire $0\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 - attribute \src "libresoc.v:187623.3-187624.79" + attribute \src "libresoc.v:187898.3-187935.6" + wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12403 + attribute \src "libresoc.v:187680.3-187681.79" wire $0\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 - attribute \src "libresoc.v:187607.3-187608.73" + attribute \src "libresoc.v:187898.3-187935.6" + wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12404 + attribute \src "libresoc.v:187664.3-187665.73" wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 - attribute \src "libresoc.v:187605.3-187606.73" + attribute \src "libresoc.v:187898.3-187935.6" + wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12405 + attribute \src "libresoc.v:187662.3-187663.73" wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 - attribute \src "libresoc.v:187613.3-187614.79" + attribute \src "libresoc.v:187898.3-187935.6" + wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12406 + attribute \src "libresoc.v:187670.3-187671.79" wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:187995.3-188003.6" - wire $0\alui_l_r_alui$next[0:0]$12674 - attribute \src "libresoc.v:187573.3-187574.43" + attribute \src "libresoc.v:188052.3-188060.6" + wire $0\alui_l_r_alui$next[0:0]$12470 + attribute \src "libresoc.v:187630.3-187631.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:187879.3-187900.6" - wire width 64 $0\data_r0__o$next[63:0]$12635 - attribute \src "libresoc.v:187593.3-187594.37" + attribute \src "libresoc.v:187936.3-187957.6" + wire width 64 $0\data_r0__o$next[63:0]$12431 + attribute \src "libresoc.v:187650.3-187651.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:187879.3-187900.6" - wire $0\data_r0__o_ok$next[0:0]$12636 - attribute \src "libresoc.v:187595.3-187596.43" + attribute \src "libresoc.v:187936.3-187957.6" + wire $0\data_r0__o_ok$next[0:0]$12432 + attribute \src "libresoc.v:187652.3-187653.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:187901.3-187922.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$12643 - attribute \src "libresoc.v:187589.3-187590.43" + attribute \src "libresoc.v:187958.3-187979.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$12439 + attribute \src "libresoc.v:187646.3-187647.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:187901.3-187922.6" - wire $0\data_r1__cr_a_ok$next[0:0]$12644 - attribute \src "libresoc.v:187591.3-187592.49" + attribute \src "libresoc.v:187958.3-187979.6" + wire $0\data_r1__cr_a_ok$next[0:0]$12440 + attribute \src "libresoc.v:187648.3-187649.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:187923.3-187944.6" - wire width 2 $0\data_r2__xer_ca$next[1:0]$12651 - attribute \src "libresoc.v:187585.3-187586.47" + attribute \src "libresoc.v:187980.3-188001.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$12447 + attribute \src "libresoc.v:187642.3-187643.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:187923.3-187944.6" - wire $0\data_r2__xer_ca_ok$next[0:0]$12652 - attribute \src "libresoc.v:187587.3-187588.53" + attribute \src "libresoc.v:187980.3-188001.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$12448 + attribute \src "libresoc.v:187644.3-187645.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:188013.3-188022.6" + attribute \src "libresoc.v:188070.3-188079.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:188023.3-188032.6" + attribute \src "libresoc.v:188080.3-188089.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:188033.3-188042.6" + attribute \src "libresoc.v:188090.3-188099.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:186878.7-186878.20" + attribute \src "libresoc.v:186935.7-186935.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187796.3-187804.6" - wire $0\opc_l_r_opc$next[0:0]$12579 - attribute \src "libresoc.v:187639.3-187640.39" + attribute \src "libresoc.v:187853.3-187861.6" + wire $0\opc_l_r_opc$next[0:0]$12375 + attribute \src "libresoc.v:187696.3-187697.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:187787.3-187795.6" - wire $0\opc_l_s_opc$next[0:0]$12576 - attribute \src "libresoc.v:187641.3-187642.39" + attribute \src "libresoc.v:187844.3-187852.6" + wire $0\opc_l_s_opc$next[0:0]$12372 + attribute \src "libresoc.v:187698.3-187699.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:188043.3-188051.6" - wire width 3 $0\prev_wr_go$next[2:0]$12683 - attribute \src "libresoc.v:187651.3-187652.37" + attribute \src "libresoc.v:188100.3-188108.6" + wire width 3 $0\prev_wr_go$next[2:0]$12479 + attribute \src "libresoc.v:187708.3-187709.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:187741.3-187750.6" + attribute \src "libresoc.v:187798.3-187807.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:187832.3-187840.6" - wire width 3 $0\req_l_r_req$next[2:0]$12591 - attribute \src "libresoc.v:187631.3-187632.39" + attribute \src "libresoc.v:187889.3-187897.6" + wire width 3 $0\req_l_r_req$next[2:0]$12387 + attribute \src "libresoc.v:187688.3-187689.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:187823.3-187831.6" - wire width 3 $0\req_l_s_req$next[2:0]$12588 - attribute \src "libresoc.v:187633.3-187634.39" + attribute \src "libresoc.v:187880.3-187888.6" + wire width 3 $0\req_l_s_req$next[2:0]$12384 + attribute \src "libresoc.v:187690.3-187691.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:187760.3-187768.6" - wire $0\rok_l_r_rdok$next[0:0]$12567 - attribute \src "libresoc.v:187647.3-187648.41" + attribute \src "libresoc.v:187817.3-187825.6" + wire $0\rok_l_r_rdok$next[0:0]$12363 + attribute \src "libresoc.v:187704.3-187705.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:187751.3-187759.6" - wire $0\rok_l_s_rdok$next[0:0]$12564 - attribute \src "libresoc.v:187649.3-187650.41" + attribute \src "libresoc.v:187808.3-187816.6" + wire $0\rok_l_s_rdok$next[0:0]$12360 + attribute \src "libresoc.v:187706.3-187707.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:187778.3-187786.6" - wire $0\rst_l_r_rst$next[0:0]$12573 - attribute \src "libresoc.v:187643.3-187644.39" + attribute \src "libresoc.v:187835.3-187843.6" + wire $0\rst_l_r_rst$next[0:0]$12369 + attribute \src "libresoc.v:187700.3-187701.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:187769.3-187777.6" - wire $0\rst_l_s_rst$next[0:0]$12570 - attribute \src "libresoc.v:187645.3-187646.39" + attribute \src "libresoc.v:187826.3-187834.6" + wire $0\rst_l_s_rst$next[0:0]$12366 + attribute \src "libresoc.v:187702.3-187703.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:187814.3-187822.6" - wire width 5 $0\src_l_r_src$next[4:0]$12585 - attribute \src "libresoc.v:187635.3-187636.39" + attribute \src "libresoc.v:187871.3-187879.6" + wire width 5 $0\src_l_r_src$next[4:0]$12381 + attribute \src "libresoc.v:187692.3-187693.39" wire width 5 $0\src_l_r_src[4:0] - attribute \src "libresoc.v:187805.3-187813.6" - wire width 5 $0\src_l_s_src$next[4:0]$12582 - attribute \src "libresoc.v:187637.3-187638.39" + attribute \src "libresoc.v:187862.3-187870.6" + wire width 5 $0\src_l_s_src$next[4:0]$12378 + attribute \src "libresoc.v:187694.3-187695.39" wire width 5 $0\src_l_s_src[4:0] - attribute \src "libresoc.v:187945.3-187954.6" - wire width 64 $0\src_r0$next[63:0]$12659 - attribute \src "libresoc.v:187583.3-187584.29" + attribute \src "libresoc.v:188002.3-188011.6" + wire width 64 $0\src_r0$next[63:0]$12455 + attribute \src "libresoc.v:187640.3-187641.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:187955.3-187964.6" - wire width 64 $0\src_r1$next[63:0]$12662 - attribute \src "libresoc.v:187581.3-187582.29" + attribute \src "libresoc.v:188012.3-188021.6" + wire width 64 $0\src_r1$next[63:0]$12458 + attribute \src "libresoc.v:187638.3-187639.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:187965.3-187974.6" - wire width 64 $0\src_r2$next[63:0]$12665 - attribute \src "libresoc.v:187579.3-187580.29" + attribute \src "libresoc.v:188022.3-188031.6" + wire width 64 $0\src_r2$next[63:0]$12461 + attribute \src "libresoc.v:187636.3-187637.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:187975.3-187984.6" - wire $0\src_r3$next[0:0]$12668 - attribute \src "libresoc.v:187577.3-187578.29" + attribute \src "libresoc.v:188032.3-188041.6" + wire $0\src_r3$next[0:0]$12464 + attribute \src "libresoc.v:187634.3-187635.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:187985.3-187994.6" - wire width 2 $0\src_r4$next[1:0]$12671 - attribute \src "libresoc.v:187575.3-187576.29" + attribute \src "libresoc.v:188042.3-188051.6" + wire width 2 $0\src_r4$next[1:0]$12467 + attribute \src "libresoc.v:187632.3-187633.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:187000.7-187000.24" + attribute \src "libresoc.v:187057.7-187057.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:187010.7-187010.26" + attribute \src "libresoc.v:187067.7-187067.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:188004.3-188012.6" - wire $1\alu_l_r_alu$next[0:0]$12678 - attribute \src "libresoc.v:187018.7-187018.25" + attribute \src "libresoc.v:188061.3-188069.6" + wire $1\alu_l_r_alu$next[0:0]$12474 + attribute \src "libresoc.v:187075.7-187075.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 - attribute \src "libresoc.v:187061.14-187061.54" + attribute \src "libresoc.v:187898.3-187935.6" + wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12407 + attribute \src "libresoc.v:187118.14-187118.54" wire width 14 $1\alu_shift_rot0_sr_op__fn_unit[13:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 - attribute \src "libresoc.v:187065.14-187065.73" + attribute \src "libresoc.v:187898.3-187935.6" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12408 + attribute \src "libresoc.v:187122.14-187122.73" wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 - attribute \src "libresoc.v:187069.7-187069.48" + attribute \src "libresoc.v:187898.3-187935.6" + wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12409 + attribute \src "libresoc.v:187126.7-187126.48" wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 - attribute \src "libresoc.v:187077.13-187077.53" + attribute \src "libresoc.v:187898.3-187935.6" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12410 + attribute \src "libresoc.v:187134.13-187134.53" wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 - attribute \src "libresoc.v:187081.7-187081.44" + attribute \src "libresoc.v:187898.3-187935.6" + wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12411 + attribute \src "libresoc.v:187138.7-187138.44" wire $1\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 - attribute \src "libresoc.v:187085.14-187085.48" + attribute \src "libresoc.v:187898.3-187935.6" + wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12412 + attribute \src "libresoc.v:187142.14-187142.48" wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 - attribute \src "libresoc.v:187164.13-187164.52" + attribute \src "libresoc.v:187898.3-187935.6" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12413 + attribute \src "libresoc.v:187221.13-187221.52" wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 - attribute \src "libresoc.v:187168.7-187168.45" + attribute \src "libresoc.v:187898.3-187935.6" + wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12414 + attribute \src "libresoc.v:187225.7-187225.45" wire $1\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 - attribute \src "libresoc.v:187172.7-187172.44" + attribute \src "libresoc.v:187898.3-187935.6" + wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12415 + attribute \src "libresoc.v:187229.7-187229.44" wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 - attribute \src "libresoc.v:187176.7-187176.45" + attribute \src "libresoc.v:187898.3-187935.6" + wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12416 + attribute \src "libresoc.v:187233.7-187233.45" wire $1\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 - attribute \src "libresoc.v:187180.7-187180.42" + attribute \src "libresoc.v:187898.3-187935.6" + wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12417 + attribute \src "libresoc.v:187237.7-187237.42" wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 - attribute \src "libresoc.v:187184.7-187184.42" + attribute \src "libresoc.v:187898.3-187935.6" + wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12418 + attribute \src "libresoc.v:187241.7-187241.42" wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 - attribute \src "libresoc.v:187188.7-187188.48" + attribute \src "libresoc.v:187898.3-187935.6" + wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12419 + attribute \src "libresoc.v:187245.7-187245.48" wire $1\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 - attribute \src "libresoc.v:187192.7-187192.45" + attribute \src "libresoc.v:187898.3-187935.6" + wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12420 + attribute \src "libresoc.v:187249.7-187249.45" wire $1\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 - attribute \src "libresoc.v:187196.7-187196.42" + attribute \src "libresoc.v:187898.3-187935.6" + wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12421 + attribute \src "libresoc.v:187253.7-187253.42" wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 - attribute \src "libresoc.v:187200.7-187200.42" + attribute \src "libresoc.v:187898.3-187935.6" + wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12422 + attribute \src "libresoc.v:187257.7-187257.42" wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 - attribute \src "libresoc.v:187204.7-187204.45" + attribute \src "libresoc.v:187898.3-187935.6" + wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12423 + attribute \src "libresoc.v:187261.7-187261.45" wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:187995.3-188003.6" - wire $1\alui_l_r_alui$next[0:0]$12675 - attribute \src "libresoc.v:187216.7-187216.27" + attribute \src "libresoc.v:188052.3-188060.6" + wire $1\alui_l_r_alui$next[0:0]$12471 + attribute \src "libresoc.v:187273.7-187273.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:187879.3-187900.6" - wire width 64 $1\data_r0__o$next[63:0]$12637 - attribute \src "libresoc.v:187250.14-187250.47" + attribute \src "libresoc.v:187936.3-187957.6" + wire width 64 $1\data_r0__o$next[63:0]$12433 + attribute \src "libresoc.v:187307.14-187307.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:187879.3-187900.6" - wire $1\data_r0__o_ok$next[0:0]$12638 - attribute \src "libresoc.v:187254.7-187254.27" + attribute \src "libresoc.v:187936.3-187957.6" + wire $1\data_r0__o_ok$next[0:0]$12434 + attribute \src "libresoc.v:187311.7-187311.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:187901.3-187922.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$12645 - attribute \src "libresoc.v:187258.13-187258.33" + attribute \src "libresoc.v:187958.3-187979.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$12441 + attribute \src "libresoc.v:187315.13-187315.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:187901.3-187922.6" - wire $1\data_r1__cr_a_ok$next[0:0]$12646 - attribute \src "libresoc.v:187262.7-187262.30" + attribute \src "libresoc.v:187958.3-187979.6" + wire $1\data_r1__cr_a_ok$next[0:0]$12442 + attribute \src "libresoc.v:187319.7-187319.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:187923.3-187944.6" - wire width 2 $1\data_r2__xer_ca$next[1:0]$12653 - attribute \src "libresoc.v:187266.13-187266.35" + attribute \src "libresoc.v:187980.3-188001.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$12449 + attribute \src "libresoc.v:187323.13-187323.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:187923.3-187944.6" - wire $1\data_r2__xer_ca_ok$next[0:0]$12654 - attribute \src "libresoc.v:187270.7-187270.32" + attribute \src "libresoc.v:187980.3-188001.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$12450 + attribute \src "libresoc.v:187327.7-187327.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:188013.3-188022.6" + attribute \src "libresoc.v:188070.3-188079.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:188023.3-188032.6" + attribute \src "libresoc.v:188080.3-188089.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:188033.3-188042.6" + attribute \src "libresoc.v:188090.3-188099.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:187796.3-187804.6" - wire $1\opc_l_r_opc$next[0:0]$12580 - attribute \src "libresoc.v:187287.7-187287.25" + attribute \src "libresoc.v:187853.3-187861.6" + wire $1\opc_l_r_opc$next[0:0]$12376 + attribute \src "libresoc.v:187344.7-187344.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:187787.3-187795.6" - wire $1\opc_l_s_opc$next[0:0]$12577 - attribute \src "libresoc.v:187291.7-187291.25" + attribute \src "libresoc.v:187844.3-187852.6" + wire $1\opc_l_s_opc$next[0:0]$12373 + attribute \src "libresoc.v:187348.7-187348.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:188043.3-188051.6" - wire width 3 $1\prev_wr_go$next[2:0]$12684 - attribute \src "libresoc.v:187423.13-187423.30" + attribute \src "libresoc.v:188100.3-188108.6" + wire width 3 $1\prev_wr_go$next[2:0]$12480 + attribute \src "libresoc.v:187480.13-187480.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:187741.3-187750.6" + attribute \src "libresoc.v:187798.3-187807.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:187832.3-187840.6" - wire width 3 $1\req_l_r_req$next[2:0]$12592 - attribute \src "libresoc.v:187431.13-187431.31" + attribute \src "libresoc.v:187889.3-187897.6" + wire width 3 $1\req_l_r_req$next[2:0]$12388 + attribute \src "libresoc.v:187488.13-187488.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:187823.3-187831.6" - wire width 3 $1\req_l_s_req$next[2:0]$12589 - attribute \src "libresoc.v:187435.13-187435.31" + attribute \src "libresoc.v:187880.3-187888.6" + wire width 3 $1\req_l_s_req$next[2:0]$12385 + attribute \src "libresoc.v:187492.13-187492.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:187760.3-187768.6" - wire $1\rok_l_r_rdok$next[0:0]$12568 - attribute \src "libresoc.v:187447.7-187447.26" + attribute \src "libresoc.v:187817.3-187825.6" + wire $1\rok_l_r_rdok$next[0:0]$12364 + attribute \src "libresoc.v:187504.7-187504.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:187751.3-187759.6" - wire $1\rok_l_s_rdok$next[0:0]$12565 - attribute \src "libresoc.v:187451.7-187451.26" + attribute \src "libresoc.v:187808.3-187816.6" + wire $1\rok_l_s_rdok$next[0:0]$12361 + attribute \src "libresoc.v:187508.7-187508.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:187778.3-187786.6" - wire $1\rst_l_r_rst$next[0:0]$12574 - attribute \src "libresoc.v:187455.7-187455.25" + attribute \src "libresoc.v:187835.3-187843.6" + wire $1\rst_l_r_rst$next[0:0]$12370 + attribute \src "libresoc.v:187512.7-187512.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:187769.3-187777.6" - wire $1\rst_l_s_rst$next[0:0]$12571 - attribute \src "libresoc.v:187459.7-187459.25" + attribute \src "libresoc.v:187826.3-187834.6" + wire $1\rst_l_s_rst$next[0:0]$12367 + attribute \src "libresoc.v:187516.7-187516.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:187814.3-187822.6" - wire width 5 $1\src_l_r_src$next[4:0]$12586 - attribute \src "libresoc.v:187477.13-187477.32" + attribute \src "libresoc.v:187871.3-187879.6" + wire width 5 $1\src_l_r_src$next[4:0]$12382 + attribute \src "libresoc.v:187534.13-187534.32" wire width 5 $1\src_l_r_src[4:0] - attribute \src "libresoc.v:187805.3-187813.6" - wire width 5 $1\src_l_s_src$next[4:0]$12583 - attribute \src "libresoc.v:187481.13-187481.32" + attribute \src "libresoc.v:187862.3-187870.6" + wire width 5 $1\src_l_s_src$next[4:0]$12379 + attribute \src "libresoc.v:187538.13-187538.32" wire width 5 $1\src_l_s_src[4:0] - attribute \src "libresoc.v:187945.3-187954.6" - wire width 64 $1\src_r0$next[63:0]$12660 - attribute \src "libresoc.v:187487.14-187487.43" + attribute \src "libresoc.v:188002.3-188011.6" + wire width 64 $1\src_r0$next[63:0]$12456 + attribute \src "libresoc.v:187544.14-187544.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:187955.3-187964.6" - wire width 64 $1\src_r1$next[63:0]$12663 - attribute \src "libresoc.v:187491.14-187491.43" + attribute \src "libresoc.v:188012.3-188021.6" + wire width 64 $1\src_r1$next[63:0]$12459 + attribute \src "libresoc.v:187548.14-187548.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:187965.3-187974.6" - wire width 64 $1\src_r2$next[63:0]$12666 - attribute \src "libresoc.v:187495.14-187495.43" + attribute \src "libresoc.v:188022.3-188031.6" + wire width 64 $1\src_r2$next[63:0]$12462 + attribute \src "libresoc.v:187552.14-187552.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:187975.3-187984.6" - wire $1\src_r3$next[0:0]$12669 - attribute \src "libresoc.v:187499.7-187499.20" + attribute \src "libresoc.v:188032.3-188041.6" + wire $1\src_r3$next[0:0]$12465 + attribute \src "libresoc.v:187556.7-187556.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:187985.3-187994.6" - wire width 2 $1\src_r4$next[1:0]$12672 - attribute \src "libresoc.v:187503.13-187503.26" + attribute \src "libresoc.v:188042.3-188051.6" + wire width 2 $1\src_r4$next[1:0]$12468 + attribute \src "libresoc.v:187560.13-187560.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:187841.3-187878.6" - wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 - attribute \src "libresoc.v:187841.3-187878.6" - wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 - attribute \src "libresoc.v:187841.3-187878.6" - wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 - attribute \src "libresoc.v:187841.3-187878.6" - wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 - attribute \src "libresoc.v:187841.3-187878.6" - wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 - attribute \src "libresoc.v:187841.3-187878.6" - wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 - attribute \src "libresoc.v:187879.3-187900.6" - wire width 64 $2\data_r0__o$next[63:0]$12639 - attribute \src "libresoc.v:187879.3-187900.6" - wire $2\data_r0__o_ok$next[0:0]$12640 - attribute \src "libresoc.v:187901.3-187922.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$12647 - attribute \src "libresoc.v:187901.3-187922.6" - wire $2\data_r1__cr_a_ok$next[0:0]$12648 - attribute \src "libresoc.v:187923.3-187944.6" - wire width 2 $2\data_r2__xer_ca$next[1:0]$12655 - attribute \src "libresoc.v:187923.3-187944.6" - wire $2\data_r2__xer_ca_ok$next[0:0]$12656 - attribute \src "libresoc.v:187879.3-187900.6" - wire $3\data_r0__o_ok$next[0:0]$12641 - attribute \src "libresoc.v:187901.3-187922.6" - wire $3\data_r1__cr_a_ok$next[0:0]$12649 - attribute \src "libresoc.v:187923.3-187944.6" - wire $3\data_r2__xer_ca_ok$next[0:0]$12657 - attribute \src "libresoc.v:187513.19-187513.114" - wire width 5 $and$libresoc.v:187513$12461_Y - attribute \src "libresoc.v:187514.19-187514.125" - wire $and$libresoc.v:187514$12462_Y - attribute \src "libresoc.v:187515.19-187515.125" - wire $and$libresoc.v:187515$12463_Y - attribute \src "libresoc.v:187516.19-187516.125" - wire $and$libresoc.v:187516$12464_Y - attribute \src "libresoc.v:187517.18-187517.110" - wire $and$libresoc.v:187517$12465_Y - attribute \src "libresoc.v:187518.19-187518.141" - wire width 3 $and$libresoc.v:187518$12466_Y - attribute \src "libresoc.v:187519.19-187519.121" - wire width 3 $and$libresoc.v:187519$12467_Y - attribute \src "libresoc.v:187520.19-187520.127" - wire $and$libresoc.v:187520$12468_Y - attribute \src "libresoc.v:187521.19-187521.127" - wire $and$libresoc.v:187521$12469_Y - attribute \src "libresoc.v:187522.19-187522.127" - wire $and$libresoc.v:187522$12470_Y - attribute \src "libresoc.v:187524.18-187524.98" - wire $and$libresoc.v:187524$12472_Y - attribute \src "libresoc.v:187526.18-187526.100" - wire $and$libresoc.v:187526$12474_Y - attribute \src "libresoc.v:187527.18-187527.149" - wire width 3 $and$libresoc.v:187527$12475_Y - attribute \src "libresoc.v:187529.18-187529.119" - wire width 3 $and$libresoc.v:187529$12477_Y - attribute \src "libresoc.v:187532.17-187532.123" - wire $and$libresoc.v:187532$12480_Y - attribute \src "libresoc.v:187533.18-187533.116" - wire $and$libresoc.v:187533$12481_Y - attribute \src "libresoc.v:187538.18-187538.113" - wire $and$libresoc.v:187538$12486_Y - attribute \src "libresoc.v:187539.18-187539.125" - wire width 3 $and$libresoc.v:187539$12487_Y - attribute \src "libresoc.v:187541.18-187541.112" - wire $and$libresoc.v:187541$12489_Y - attribute \src "libresoc.v:187543.18-187543.132" - wire $and$libresoc.v:187543$12491_Y - attribute \src "libresoc.v:187544.18-187544.132" - wire $and$libresoc.v:187544$12492_Y - attribute \src "libresoc.v:187545.18-187545.117" - wire $and$libresoc.v:187545$12493_Y - attribute \src "libresoc.v:187551.18-187551.136" - wire $and$libresoc.v:187551$12499_Y - attribute \src "libresoc.v:187552.18-187552.124" - wire width 3 $and$libresoc.v:187552$12500_Y - attribute \src "libresoc.v:187554.18-187554.116" - wire $and$libresoc.v:187554$12502_Y - attribute \src "libresoc.v:187555.18-187555.119" - wire $and$libresoc.v:187555$12503_Y - attribute \src "libresoc.v:187556.18-187556.121" - wire $and$libresoc.v:187556$12504_Y - attribute \src "libresoc.v:187566.18-187566.140" - wire $and$libresoc.v:187566$12514_Y - attribute \src "libresoc.v:187567.18-187567.138" - wire $and$libresoc.v:187567$12515_Y - attribute \src "libresoc.v:187568.18-187568.171" - wire width 5 $and$libresoc.v:187568$12516_Y - attribute \src "libresoc.v:187570.18-187570.129" - wire width 5 $and$libresoc.v:187570$12518_Y - attribute \src "libresoc.v:187540.18-187540.113" - wire $eq$libresoc.v:187540$12488_Y - attribute \src "libresoc.v:187542.18-187542.119" - wire $eq$libresoc.v:187542$12490_Y - attribute \src "libresoc.v:187512.19-187512.115" - wire width 5 $not$libresoc.v:187512$12460_Y - attribute \src "libresoc.v:187523.18-187523.97" - wire $not$libresoc.v:187523$12471_Y - attribute \src "libresoc.v:187525.18-187525.99" - wire $not$libresoc.v:187525$12473_Y - attribute \src "libresoc.v:187528.18-187528.113" - wire width 3 $not$libresoc.v:187528$12476_Y - attribute \src "libresoc.v:187531.18-187531.106" - wire $not$libresoc.v:187531$12479_Y - attribute \src "libresoc.v:187537.18-187537.126" - wire $not$libresoc.v:187537$12485_Y - attribute \src "libresoc.v:187548.17-187548.113" - wire width 5 $not$libresoc.v:187548$12496_Y - attribute \src "libresoc.v:187569.18-187569.136" - wire $not$libresoc.v:187569$12517_Y - attribute \src "libresoc.v:187536.18-187536.112" - wire $or$libresoc.v:187536$12484_Y - attribute \src "libresoc.v:187546.18-187546.122" - wire $or$libresoc.v:187546$12494_Y - attribute \src "libresoc.v:187547.18-187547.124" - wire $or$libresoc.v:187547$12495_Y - attribute \src "libresoc.v:187549.18-187549.155" - wire width 3 $or$libresoc.v:187549$12497_Y - attribute \src "libresoc.v:187550.18-187550.181" - wire width 5 $or$libresoc.v:187550$12498_Y - attribute \src "libresoc.v:187553.18-187553.120" - wire width 3 $or$libresoc.v:187553$12501_Y - attribute \src "libresoc.v:187559.17-187559.117" - wire width 5 $or$libresoc.v:187559$12507_Y - attribute \src "libresoc.v:187565.17-187565.104" - wire $reduce_and$libresoc.v:187565$12513_Y - attribute \src "libresoc.v:187530.18-187530.106" - wire $reduce_or$libresoc.v:187530$12478_Y - attribute \src "libresoc.v:187534.18-187534.113" - wire $reduce_or$libresoc.v:187534$12482_Y - attribute \src "libresoc.v:187535.18-187535.112" - wire $reduce_or$libresoc.v:187535$12483_Y - attribute \src "libresoc.v:187557.18-187557.165" - wire $ternary$libresoc.v:187557$12505_Y - attribute \src "libresoc.v:187558.18-187558.182" - wire width 64 $ternary$libresoc.v:187558$12506_Y - attribute \src "libresoc.v:187560.18-187560.118" - wire width 64 $ternary$libresoc.v:187560$12508_Y - attribute \src "libresoc.v:187561.18-187561.115" - wire width 64 $ternary$libresoc.v:187561$12509_Y - attribute \src "libresoc.v:187562.18-187562.118" - wire width 64 $ternary$libresoc.v:187562$12510_Y - attribute \src "libresoc.v:187563.18-187563.118" - wire $ternary$libresoc.v:187563$12511_Y - attribute \src "libresoc.v:187564.18-187564.118" - wire width 2 $ternary$libresoc.v:187564$12512_Y + attribute \src "libresoc.v:187898.3-187935.6" + wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12424 + attribute \src "libresoc.v:187898.3-187935.6" + wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12425 + attribute \src "libresoc.v:187898.3-187935.6" + wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12426 + attribute \src "libresoc.v:187898.3-187935.6" + wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12427 + attribute \src "libresoc.v:187898.3-187935.6" + wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12428 + attribute \src "libresoc.v:187898.3-187935.6" + wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12429 + attribute \src "libresoc.v:187936.3-187957.6" + wire width 64 $2\data_r0__o$next[63:0]$12435 + attribute \src "libresoc.v:187936.3-187957.6" + wire $2\data_r0__o_ok$next[0:0]$12436 + attribute \src "libresoc.v:187958.3-187979.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$12443 + attribute \src "libresoc.v:187958.3-187979.6" + wire $2\data_r1__cr_a_ok$next[0:0]$12444 + attribute \src "libresoc.v:187980.3-188001.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$12451 + attribute \src "libresoc.v:187980.3-188001.6" + wire $2\data_r2__xer_ca_ok$next[0:0]$12452 + attribute \src "libresoc.v:187936.3-187957.6" + wire $3\data_r0__o_ok$next[0:0]$12437 + attribute \src "libresoc.v:187958.3-187979.6" + wire $3\data_r1__cr_a_ok$next[0:0]$12445 + attribute \src "libresoc.v:187980.3-188001.6" + wire $3\data_r2__xer_ca_ok$next[0:0]$12453 + attribute \src "libresoc.v:187570.19-187570.114" + wire width 5 $and$libresoc.v:187570$12257_Y + attribute \src "libresoc.v:187571.19-187571.125" + wire $and$libresoc.v:187571$12258_Y + attribute \src "libresoc.v:187572.19-187572.125" + wire $and$libresoc.v:187572$12259_Y + attribute \src "libresoc.v:187573.19-187573.125" + wire $and$libresoc.v:187573$12260_Y + attribute \src "libresoc.v:187574.18-187574.110" + wire $and$libresoc.v:187574$12261_Y + attribute \src "libresoc.v:187575.19-187575.141" + wire width 3 $and$libresoc.v:187575$12262_Y + attribute \src "libresoc.v:187576.19-187576.121" + wire width 3 $and$libresoc.v:187576$12263_Y + attribute \src "libresoc.v:187577.19-187577.127" + wire $and$libresoc.v:187577$12264_Y + attribute \src "libresoc.v:187578.19-187578.127" + wire $and$libresoc.v:187578$12265_Y + attribute \src "libresoc.v:187579.19-187579.127" + wire $and$libresoc.v:187579$12266_Y + attribute \src "libresoc.v:187581.18-187581.98" + wire $and$libresoc.v:187581$12268_Y + attribute \src "libresoc.v:187583.18-187583.100" + wire $and$libresoc.v:187583$12270_Y + attribute \src "libresoc.v:187584.18-187584.149" + wire width 3 $and$libresoc.v:187584$12271_Y + attribute \src "libresoc.v:187586.18-187586.119" + wire width 3 $and$libresoc.v:187586$12273_Y + attribute \src "libresoc.v:187589.17-187589.123" + wire $and$libresoc.v:187589$12276_Y + attribute \src "libresoc.v:187590.18-187590.116" + wire $and$libresoc.v:187590$12277_Y + attribute \src "libresoc.v:187595.18-187595.113" + wire $and$libresoc.v:187595$12282_Y + attribute \src "libresoc.v:187596.18-187596.125" + wire width 3 $and$libresoc.v:187596$12283_Y + attribute \src "libresoc.v:187598.18-187598.112" + wire $and$libresoc.v:187598$12285_Y + attribute \src "libresoc.v:187600.18-187600.132" + wire $and$libresoc.v:187600$12287_Y + attribute \src "libresoc.v:187601.18-187601.132" + wire $and$libresoc.v:187601$12288_Y + attribute \src "libresoc.v:187602.18-187602.117" + wire $and$libresoc.v:187602$12289_Y + attribute \src "libresoc.v:187608.18-187608.136" + wire $and$libresoc.v:187608$12295_Y + attribute \src "libresoc.v:187609.18-187609.124" + wire width 3 $and$libresoc.v:187609$12296_Y + attribute \src "libresoc.v:187611.18-187611.116" + wire $and$libresoc.v:187611$12298_Y + attribute \src "libresoc.v:187612.18-187612.119" + wire $and$libresoc.v:187612$12299_Y + attribute \src "libresoc.v:187613.18-187613.121" + wire $and$libresoc.v:187613$12300_Y + attribute \src "libresoc.v:187623.18-187623.140" + wire $and$libresoc.v:187623$12310_Y + attribute \src "libresoc.v:187624.18-187624.138" + wire $and$libresoc.v:187624$12311_Y + attribute \src "libresoc.v:187625.18-187625.171" + wire width 5 $and$libresoc.v:187625$12312_Y + attribute \src "libresoc.v:187627.18-187627.129" + wire width 5 $and$libresoc.v:187627$12314_Y + attribute \src "libresoc.v:187597.18-187597.113" + wire $eq$libresoc.v:187597$12284_Y + attribute \src "libresoc.v:187599.18-187599.119" + wire $eq$libresoc.v:187599$12286_Y + attribute \src "libresoc.v:187569.19-187569.115" + wire width 5 $not$libresoc.v:187569$12256_Y + attribute \src "libresoc.v:187580.18-187580.97" + wire $not$libresoc.v:187580$12267_Y + attribute \src "libresoc.v:187582.18-187582.99" + wire $not$libresoc.v:187582$12269_Y + attribute \src "libresoc.v:187585.18-187585.113" + wire width 3 $not$libresoc.v:187585$12272_Y + attribute \src "libresoc.v:187588.18-187588.106" + wire $not$libresoc.v:187588$12275_Y + attribute \src "libresoc.v:187594.18-187594.126" + wire $not$libresoc.v:187594$12281_Y + attribute \src "libresoc.v:187605.17-187605.113" + wire width 5 $not$libresoc.v:187605$12292_Y + attribute \src "libresoc.v:187626.18-187626.136" + wire $not$libresoc.v:187626$12313_Y + attribute \src "libresoc.v:187593.18-187593.112" + wire $or$libresoc.v:187593$12280_Y + attribute \src "libresoc.v:187603.18-187603.122" + wire $or$libresoc.v:187603$12290_Y + attribute \src "libresoc.v:187604.18-187604.124" + wire $or$libresoc.v:187604$12291_Y + attribute \src "libresoc.v:187606.18-187606.155" + wire width 3 $or$libresoc.v:187606$12293_Y + attribute \src "libresoc.v:187607.18-187607.181" + wire width 5 $or$libresoc.v:187607$12294_Y + attribute \src "libresoc.v:187610.18-187610.120" + wire width 3 $or$libresoc.v:187610$12297_Y + attribute \src "libresoc.v:187616.17-187616.117" + wire width 5 $or$libresoc.v:187616$12303_Y + attribute \src "libresoc.v:187622.17-187622.104" + wire $reduce_and$libresoc.v:187622$12309_Y + attribute \src "libresoc.v:187587.18-187587.106" + wire $reduce_or$libresoc.v:187587$12274_Y + attribute \src "libresoc.v:187591.18-187591.113" + wire $reduce_or$libresoc.v:187591$12278_Y + attribute \src "libresoc.v:187592.18-187592.112" + wire $reduce_or$libresoc.v:187592$12279_Y + attribute \src "libresoc.v:187614.18-187614.165" + wire $ternary$libresoc.v:187614$12301_Y + attribute \src "libresoc.v:187615.18-187615.182" + wire width 64 $ternary$libresoc.v:187615$12302_Y + attribute \src "libresoc.v:187617.18-187617.118" + wire width 64 $ternary$libresoc.v:187617$12304_Y + attribute \src "libresoc.v:187618.18-187618.115" + wire width 64 $ternary$libresoc.v:187618$12305_Y + attribute \src "libresoc.v:187619.18-187619.118" + wire width 64 $ternary$libresoc.v:187619$12306_Y + attribute \src "libresoc.v:187620.18-187620.118" + wire $ternary$libresoc.v:187620$12307_Y + attribute \src "libresoc.v:187621.18-187621.118" + wire width 2 $ternary$libresoc.v:187621$12308_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -388472,13 +353461,13 @@ module \shiftrot0 wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 3 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \alu_shift_rot0_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_shift_rot0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_shift_rot0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_shift_rot0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_shift_rot0_p_ready_o @@ -388652,7 +353641,7 @@ module \shiftrot0 wire \alu_shift_rot0_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \alu_shift_rot0_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \alu_shift_rot0_xer_ca$1 @@ -388666,11 +353655,11 @@ module \shiftrot0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 37 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 20 \cu_busy_o @@ -388724,9 +353713,9 @@ module \shiftrot0 wire width 4 output 34 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 36 \dest3_o - attribute \src "libresoc.v:186878.7-186878.15" + attribute \src "libresoc.v:186935.7-186935.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc @@ -388909,11 +353898,11 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 24 \src1_i + wire width 64 input 26 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 25 \src2_i + wire width 64 input 24 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 26 \src3_i + wire width 64 input 25 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 27 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" @@ -388954,10 +353943,10 @@ module \shiftrot0 wire \src_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 35 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187513$12461 + cell $and $and$libresoc.v:187570$12257 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -388965,10 +353954,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$98 connect \B \$100 - connect \Y $and$libresoc.v:187513$12461_Y + connect \Y $and$libresoc.v:187570$12257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187514$12462 + cell $and $and$libresoc.v:187571$12258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388976,10 +353965,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187514$12462_Y + connect \Y $and$libresoc.v:187571$12258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187515$12463 + cell $and $and$libresoc.v:187572$12259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388987,10 +353976,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187515$12463_Y + connect \Y $and$libresoc.v:187572$12259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187516$12464 + cell $and $and$libresoc.v:187573$12260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388998,10 +353987,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187516$12464_Y + connect \Y $and$libresoc.v:187573$12260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:187517$12465 + cell $and $and$libresoc.v:187574$12261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389009,10 +353998,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:187517$12465_Y + connect \Y $and$libresoc.v:187574$12261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:187518$12466 + cell $and $and$libresoc.v:187575$12262 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389020,10 +354009,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$104 \$106 \$108 } - connect \Y $and$libresoc.v:187518$12466_Y + connect \Y $and$libresoc.v:187575$12262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:187519$12467 + cell $and $and$libresoc.v:187576$12263 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389031,10 +354020,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187519$12467_Y + connect \Y $and$libresoc.v:187576$12263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187520$12468 + cell $and $and$libresoc.v:187577$12264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389042,10 +354031,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187520$12468_Y + connect \Y $and$libresoc.v:187577$12264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187521$12469 + cell $and $and$libresoc.v:187578$12265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389053,10 +354042,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187521$12469_Y + connect \Y $and$libresoc.v:187578$12265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187522$12470 + cell $and $and$libresoc.v:187579$12266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389064,10 +354053,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187522$12470_Y + connect \Y $and$libresoc.v:187579$12266_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:187524$12472 + cell $and $and$libresoc.v:187581$12268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389075,10 +354064,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:187524$12472_Y + connect \Y $and$libresoc.v:187581$12268_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:187526$12474 + cell $and $and$libresoc.v:187583$12270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389086,10 +354075,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:187526$12474_Y + connect \Y $and$libresoc.v:187583$12270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:187527$12475 + cell $and $and$libresoc.v:187584$12271 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389097,10 +354086,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:187527$12475_Y + connect \Y $and$libresoc.v:187584$12271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:187529$12477 + cell $and $and$libresoc.v:187586$12273 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389108,10 +354097,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:187529$12477_Y + connect \Y $and$libresoc.v:187586$12273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:187532$12480 + cell $and $and$libresoc.v:187589$12276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389119,10 +354108,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:187532$12480_Y + connect \Y $and$libresoc.v:187589$12276_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:187533$12481 + cell $and $and$libresoc.v:187590$12277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389130,10 +354119,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:187533$12481_Y + connect \Y $and$libresoc.v:187590$12277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:187538$12486 + cell $and $and$libresoc.v:187595$12282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389141,10 +354130,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:187538$12486_Y + connect \Y $and$libresoc.v:187595$12282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:187539$12487 + cell $and $and$libresoc.v:187596$12283 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389152,10 +354141,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187539$12487_Y + connect \Y $and$libresoc.v:187596$12283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:187541$12489 + cell $and $and$libresoc.v:187598$12285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389163,10 +354152,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:187541$12489_Y + connect \Y $and$libresoc.v:187598$12285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187543$12491 + cell $and $and$libresoc.v:187600$12287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389174,10 +354163,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_shift_rot0_n_ready_i - connect \Y $and$libresoc.v:187543$12491_Y + connect \Y $and$libresoc.v:187600$12287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187544$12492 + cell $and $and$libresoc.v:187601$12288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389185,10 +354174,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_shift_rot0_n_valid_o - connect \Y $and$libresoc.v:187544$12492_Y + connect \Y $and$libresoc.v:187601$12288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187545$12493 + cell $and $and$libresoc.v:187602$12289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389196,10 +354185,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:187545$12493_Y + connect \Y $and$libresoc.v:187602$12289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:187551$12499 + cell $and $and$libresoc.v:187608$12295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389207,10 +354196,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:187551$12499_Y + connect \Y $and$libresoc.v:187608$12295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:187552$12500 + cell $and $and$libresoc.v:187609$12296 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389218,10 +354207,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187552$12500_Y + connect \Y $and$libresoc.v:187609$12296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187554$12502 + cell $and $and$libresoc.v:187611$12298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389229,10 +354218,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187554$12502_Y + connect \Y $and$libresoc.v:187611$12298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187555$12503 + cell $and $and$libresoc.v:187612$12299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389240,10 +354229,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187555$12503_Y + connect \Y $and$libresoc.v:187612$12299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187556$12504 + cell $and $and$libresoc.v:187613$12300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389251,10 +354240,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187556$12504_Y + connect \Y $and$libresoc.v:187613$12300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:187566$12514 + cell $and $and$libresoc.v:187623$12310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389262,10 +354251,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:187566$12514_Y + connect \Y $and$libresoc.v:187623$12310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:187567$12515 + cell $and $and$libresoc.v:187624$12311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389273,10 +354262,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:187567$12515_Y + connect \Y $and$libresoc.v:187624$12311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187568$12516 + cell $and $and$libresoc.v:187625$12312 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -389284,10 +354273,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:187568$12516_Y + connect \Y $and$libresoc.v:187625$12312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187570$12518 + cell $and $and$libresoc.v:187627$12314 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -389295,10 +354284,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$94 connect \B { 3'111 \$96 1'1 } - connect \Y $and$libresoc.v:187570$12518_Y + connect \Y $and$libresoc.v:187627$12314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:187540$12488 + cell $eq $eq$libresoc.v:187597$12284 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389306,10 +354295,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:187540$12488_Y + connect \Y $eq$libresoc.v:187597$12284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:187542$12490 + cell $eq $eq$libresoc.v:187599$12286 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389317,74 +354306,74 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:187542$12490_Y + connect \Y $eq$libresoc.v:187599$12286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:187512$12460 + cell $not $not$libresoc.v:187569$12256 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:187512$12460_Y + connect \Y $not$libresoc.v:187569$12256_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:187523$12471 + cell $not $not$libresoc.v:187580$12267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:187523$12471_Y + connect \Y $not$libresoc.v:187580$12267_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:187525$12473 + cell $not $not$libresoc.v:187582$12269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:187525$12473_Y + connect \Y $not$libresoc.v:187582$12269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:187528$12476 + cell $not $not$libresoc.v:187585$12272 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:187528$12476_Y + connect \Y $not$libresoc.v:187585$12272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:187531$12479 + cell $not $not$libresoc.v:187588$12275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:187531$12479_Y + connect \Y $not$libresoc.v:187588$12275_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:187537$12485 + cell $not $not$libresoc.v:187594$12281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_ready_i - connect \Y $not$libresoc.v:187537$12485_Y + connect \Y $not$libresoc.v:187594$12281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:187548$12496 + cell $not $not$libresoc.v:187605$12292 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:187548$12496_Y + connect \Y $not$libresoc.v:187605$12292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:187569$12517 + cell $not $not$libresoc.v:187626$12313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $not$libresoc.v:187569$12517_Y + connect \Y $not$libresoc.v:187626$12313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:187536$12484 + cell $or $or$libresoc.v:187593$12280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389392,10 +354381,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:187536$12484_Y + connect \Y $or$libresoc.v:187593$12280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:187546$12494 + cell $or $or$libresoc.v:187603$12290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389403,10 +354392,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:187546$12494_Y + connect \Y $or$libresoc.v:187603$12290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:187547$12495 + cell $or $or$libresoc.v:187604$12291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389414,10 +354403,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:187547$12495_Y + connect \Y $or$libresoc.v:187604$12291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:187549$12497 + cell $or $or$libresoc.v:187606$12293 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389425,10 +354414,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:187549$12497_Y + connect \Y $or$libresoc.v:187606$12293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:187550$12498 + cell $or $or$libresoc.v:187607$12294 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -389436,10 +354425,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:187550$12498_Y + connect \Y $or$libresoc.v:187607$12294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:187553$12501 + cell $or $or$libresoc.v:187610$12297 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389447,10 +354436,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:187553$12501_Y + connect \Y $or$libresoc.v:187610$12297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:187559$12507 + cell $or $or$libresoc.v:187616$12303 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -389458,98 +354447,98 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:187559$12507_Y + connect \Y $or$libresoc.v:187616$12303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:187565$12513 + cell $reduce_and $reduce_and$libresoc.v:187622$12309 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:187565$12513_Y + connect \Y $reduce_and$libresoc.v:187622$12309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:187530$12478 + cell $reduce_or $reduce_or$libresoc.v:187587$12274 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:187530$12478_Y + connect \Y $reduce_or$libresoc.v:187587$12274_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:187534$12482 + cell $reduce_or $reduce_or$libresoc.v:187591$12278 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:187534$12482_Y + connect \Y $reduce_or$libresoc.v:187591$12278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:187535$12483 + cell $reduce_or $reduce_or$libresoc.v:187592$12279 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:187535$12483_Y + connect \Y $reduce_or$libresoc.v:187592$12279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:187557$12505 + cell $mux $ternary$libresoc.v:187614$12301 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:187557$12505_Y + connect \Y $ternary$libresoc.v:187614$12301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:187558$12506 + cell $mux $ternary$libresoc.v:187615$12302 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_shift_rot0_sr_op__imm_data__data connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:187558$12506_Y + connect \Y $ternary$libresoc.v:187615$12302_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187560$12508 + cell $mux $ternary$libresoc.v:187617$12304 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:187560$12508_Y + connect \Y $ternary$libresoc.v:187617$12304_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187561$12509 + cell $mux $ternary$libresoc.v:187618$12305 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:187561$12509_Y + connect \Y $ternary$libresoc.v:187618$12305_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187562$12510 + cell $mux $ternary$libresoc.v:187619$12306 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:187562$12510_Y + connect \Y $ternary$libresoc.v:187619$12306_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187563$12511 + cell $mux $ternary$libresoc.v:187620$12307 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:187563$12511_Y + connect \Y $ternary$libresoc.v:187620$12307_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187564$12512 + cell $mux $ternary$libresoc.v:187621$12308 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:187564$12512_Y + connect \Y $ternary$libresoc.v:187621$12308_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:187657.15-187663.4" + attribute \src "libresoc.v:187714.15-187720.4" cell \alu_l$125 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389558,7 +354547,7 @@ module \shiftrot0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:187664.18-187699.4" + attribute \src "libresoc.v:187721.18-187756.4" cell \alu_shift_rot0 \alu_shift_rot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389596,7 +354585,7 @@ module \shiftrot0 connect \xer_so \alu_shift_rot0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:187700.16-187706.4" + attribute \src "libresoc.v:187757.16-187763.4" cell \alui_l$124 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389605,7 +354594,7 @@ module \shiftrot0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:187707.15-187713.4" + attribute \src "libresoc.v:187764.15-187770.4" cell \opc_l$120 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389614,7 +354603,7 @@ module \shiftrot0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:187714.15-187720.4" + attribute \src "libresoc.v:187771.15-187777.4" cell \req_l$121 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389623,7 +354612,7 @@ module \shiftrot0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:187721.15-187727.4" + attribute \src "libresoc.v:187778.15-187784.4" cell \rok_l$123 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389632,7 +354621,7 @@ module \shiftrot0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:187728.15-187733.4" + attribute \src "libresoc.v:187785.15-187790.4" cell \rst_l$122 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389640,7 +354629,7 @@ module \shiftrot0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:187734.15-187740.4" + attribute \src "libresoc.v:187791.15-187797.4" cell \src_l$119 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389648,667 +354637,667 @@ module \shiftrot0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:186878.7-186878.20" - process $proc$libresoc.v:186878$12685 + attribute \src "libresoc.v:186935.7-186935.20" + process $proc$libresoc.v:186935$12481 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187000.7-187000.24" - process $proc$libresoc.v:187000$12686 + attribute \src "libresoc.v:187057.7-187057.24" + process $proc$libresoc.v:187057$12482 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:187010.7-187010.26" - process $proc$libresoc.v:187010$12687 + attribute \src "libresoc.v:187067.7-187067.26" + process $proc$libresoc.v:187067$12483 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:187018.7-187018.25" - process $proc$libresoc.v:187018$12688 + attribute \src "libresoc.v:187075.7-187075.25" + process $proc$libresoc.v:187075$12484 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:187061.14-187061.54" - process $proc$libresoc.v:187061$12689 + attribute \src "libresoc.v:187118.14-187118.54" + process $proc$libresoc.v:187118$12485 assign { } { } assign $1\alu_shift_rot0_sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:187065.14-187065.73" - process $proc$libresoc.v:187065$12690 + attribute \src "libresoc.v:187122.14-187122.73" + process $proc$libresoc.v:187122$12486 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:187069.7-187069.48" - process $proc$libresoc.v:187069$12691 + attribute \src "libresoc.v:187126.7-187126.48" + process $proc$libresoc.v:187126$12487 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:187077.13-187077.53" - process $proc$libresoc.v:187077$12692 + attribute \src "libresoc.v:187134.13-187134.53" + process $proc$libresoc.v:187134$12488 assign { } { } assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 sync always sync init update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:187081.7-187081.44" - process $proc$libresoc.v:187081$12693 + attribute \src "libresoc.v:187138.7-187138.44" + process $proc$libresoc.v:187138$12489 assign { } { } assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:187085.14-187085.48" - process $proc$libresoc.v:187085$12694 + attribute \src "libresoc.v:187142.14-187142.48" + process $proc$libresoc.v:187142$12490 assign { } { } assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 sync always sync init update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:187164.13-187164.52" - process $proc$libresoc.v:187164$12695 + attribute \src "libresoc.v:187221.13-187221.52" + process $proc$libresoc.v:187221$12491 assign { } { } assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:187168.7-187168.45" - process $proc$libresoc.v:187168$12696 + attribute \src "libresoc.v:187225.7-187225.45" + process $proc$libresoc.v:187225$12492 assign { } { } assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:187172.7-187172.44" - process $proc$libresoc.v:187172$12697 + attribute \src "libresoc.v:187229.7-187229.44" + process $proc$libresoc.v:187229$12493 assign { } { } assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:187176.7-187176.45" - process $proc$libresoc.v:187176$12698 + attribute \src "libresoc.v:187233.7-187233.45" + process $proc$libresoc.v:187233$12494 assign { } { } assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:187180.7-187180.42" - process $proc$libresoc.v:187180$12699 + attribute \src "libresoc.v:187237.7-187237.42" + process $proc$libresoc.v:187237$12495 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:187184.7-187184.42" - process $proc$libresoc.v:187184$12700 + attribute \src "libresoc.v:187241.7-187241.42" + process $proc$libresoc.v:187241$12496 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:187188.7-187188.48" - process $proc$libresoc.v:187188$12701 + attribute \src "libresoc.v:187245.7-187245.48" + process $proc$libresoc.v:187245$12497 assign { } { } assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:187192.7-187192.45" - process $proc$libresoc.v:187192$12702 + attribute \src "libresoc.v:187249.7-187249.45" + process $proc$libresoc.v:187249$12498 assign { } { } assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:187196.7-187196.42" - process $proc$libresoc.v:187196$12703 + attribute \src "libresoc.v:187253.7-187253.42" + process $proc$libresoc.v:187253$12499 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:187200.7-187200.42" - process $proc$libresoc.v:187200$12704 + attribute \src "libresoc.v:187257.7-187257.42" + process $proc$libresoc.v:187257$12500 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:187204.7-187204.45" - process $proc$libresoc.v:187204$12705 + attribute \src "libresoc.v:187261.7-187261.45" + process $proc$libresoc.v:187261$12501 assign { } { } assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:187216.7-187216.27" - process $proc$libresoc.v:187216$12706 + attribute \src "libresoc.v:187273.7-187273.27" + process $proc$libresoc.v:187273$12502 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:187250.14-187250.47" - process $proc$libresoc.v:187250$12707 + attribute \src "libresoc.v:187307.14-187307.47" + process $proc$libresoc.v:187307$12503 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:187254.7-187254.27" - process $proc$libresoc.v:187254$12708 + attribute \src "libresoc.v:187311.7-187311.27" + process $proc$libresoc.v:187311$12504 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:187258.13-187258.33" - process $proc$libresoc.v:187258$12709 + attribute \src "libresoc.v:187315.13-187315.33" + process $proc$libresoc.v:187315$12505 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:187262.7-187262.30" - process $proc$libresoc.v:187262$12710 + attribute \src "libresoc.v:187319.7-187319.30" + process $proc$libresoc.v:187319$12506 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:187266.13-187266.35" - process $proc$libresoc.v:187266$12711 + attribute \src "libresoc.v:187323.13-187323.35" + process $proc$libresoc.v:187323$12507 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:187270.7-187270.32" - process $proc$libresoc.v:187270$12712 + attribute \src "libresoc.v:187327.7-187327.32" + process $proc$libresoc.v:187327$12508 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:187287.7-187287.25" - process $proc$libresoc.v:187287$12713 + attribute \src "libresoc.v:187344.7-187344.25" + process $proc$libresoc.v:187344$12509 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:187291.7-187291.25" - process $proc$libresoc.v:187291$12714 + attribute \src "libresoc.v:187348.7-187348.25" + process $proc$libresoc.v:187348$12510 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:187423.13-187423.30" - process $proc$libresoc.v:187423$12715 + attribute \src "libresoc.v:187480.13-187480.30" + process $proc$libresoc.v:187480$12511 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:187431.13-187431.31" - process $proc$libresoc.v:187431$12716 + attribute \src "libresoc.v:187488.13-187488.31" + process $proc$libresoc.v:187488$12512 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:187435.13-187435.31" - process $proc$libresoc.v:187435$12717 + attribute \src "libresoc.v:187492.13-187492.31" + process $proc$libresoc.v:187492$12513 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:187447.7-187447.26" - process $proc$libresoc.v:187447$12718 + attribute \src "libresoc.v:187504.7-187504.26" + process $proc$libresoc.v:187504$12514 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:187451.7-187451.26" - process $proc$libresoc.v:187451$12719 + attribute \src "libresoc.v:187508.7-187508.26" + process $proc$libresoc.v:187508$12515 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:187455.7-187455.25" - process $proc$libresoc.v:187455$12720 + attribute \src "libresoc.v:187512.7-187512.25" + process $proc$libresoc.v:187512$12516 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:187459.7-187459.25" - process $proc$libresoc.v:187459$12721 + attribute \src "libresoc.v:187516.7-187516.25" + process $proc$libresoc.v:187516$12517 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:187477.13-187477.32" - process $proc$libresoc.v:187477$12722 + attribute \src "libresoc.v:187534.13-187534.32" + process $proc$libresoc.v:187534$12518 assign { } { } assign $1\src_l_r_src[4:0] 5'11111 sync always sync init update \src_l_r_src $1\src_l_r_src[4:0] end - attribute \src "libresoc.v:187481.13-187481.32" - process $proc$libresoc.v:187481$12723 + attribute \src "libresoc.v:187538.13-187538.32" + process $proc$libresoc.v:187538$12519 assign { } { } assign $1\src_l_s_src[4:0] 5'00000 sync always sync init update \src_l_s_src $1\src_l_s_src[4:0] end - attribute \src "libresoc.v:187487.14-187487.43" - process $proc$libresoc.v:187487$12724 + attribute \src "libresoc.v:187544.14-187544.43" + process $proc$libresoc.v:187544$12520 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:187491.14-187491.43" - process $proc$libresoc.v:187491$12725 + attribute \src "libresoc.v:187548.14-187548.43" + process $proc$libresoc.v:187548$12521 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:187495.14-187495.43" - process $proc$libresoc.v:187495$12726 + attribute \src "libresoc.v:187552.14-187552.43" + process $proc$libresoc.v:187552$12522 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:187499.7-187499.20" - process $proc$libresoc.v:187499$12727 + attribute \src "libresoc.v:187556.7-187556.20" + process $proc$libresoc.v:187556$12523 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:187503.13-187503.26" - process $proc$libresoc.v:187503$12728 + attribute \src "libresoc.v:187560.13-187560.26" + process $proc$libresoc.v:187560$12524 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:187571.3-187572.39" - process $proc$libresoc.v:187571$12519 + attribute \src "libresoc.v:187628.3-187629.39" + process $proc$libresoc.v:187628$12315 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:187573.3-187574.43" - process $proc$libresoc.v:187573$12520 + attribute \src "libresoc.v:187630.3-187631.43" + process $proc$libresoc.v:187630$12316 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:187575.3-187576.29" - process $proc$libresoc.v:187575$12521 + attribute \src "libresoc.v:187632.3-187633.29" + process $proc$libresoc.v:187632$12317 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:187577.3-187578.29" - process $proc$libresoc.v:187577$12522 + attribute \src "libresoc.v:187634.3-187635.29" + process $proc$libresoc.v:187634$12318 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:187579.3-187580.29" - process $proc$libresoc.v:187579$12523 + attribute \src "libresoc.v:187636.3-187637.29" + process $proc$libresoc.v:187636$12319 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:187581.3-187582.29" - process $proc$libresoc.v:187581$12524 + attribute \src "libresoc.v:187638.3-187639.29" + process $proc$libresoc.v:187638$12320 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:187583.3-187584.29" - process $proc$libresoc.v:187583$12525 + attribute \src "libresoc.v:187640.3-187641.29" + process $proc$libresoc.v:187640$12321 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:187585.3-187586.47" - process $proc$libresoc.v:187585$12526 + attribute \src "libresoc.v:187642.3-187643.47" + process $proc$libresoc.v:187642$12322 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:187587.3-187588.53" - process $proc$libresoc.v:187587$12527 + attribute \src "libresoc.v:187644.3-187645.53" + process $proc$libresoc.v:187644$12323 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:187589.3-187590.43" - process $proc$libresoc.v:187589$12528 + attribute \src "libresoc.v:187646.3-187647.43" + process $proc$libresoc.v:187646$12324 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:187591.3-187592.49" - process $proc$libresoc.v:187591$12529 + attribute \src "libresoc.v:187648.3-187649.49" + process $proc$libresoc.v:187648$12325 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:187593.3-187594.37" - process $proc$libresoc.v:187593$12530 + attribute \src "libresoc.v:187650.3-187651.37" + process $proc$libresoc.v:187650$12326 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:187595.3-187596.43" - process $proc$libresoc.v:187595$12531 + attribute \src "libresoc.v:187652.3-187653.43" + process $proc$libresoc.v:187652$12327 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:187597.3-187598.79" - process $proc$libresoc.v:187597$12532 + attribute \src "libresoc.v:187654.3-187655.79" + process $proc$libresoc.v:187654$12328 assign { } { } assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:187599.3-187600.75" - process $proc$libresoc.v:187599$12533 + attribute \src "libresoc.v:187656.3-187657.75" + process $proc$libresoc.v:187656$12329 assign { } { } assign $0\alu_shift_rot0_sr_op__fn_unit[13:0] \alu_shift_rot0_sr_op__fn_unit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:187601.3-187602.89" - process $proc$libresoc.v:187601$12534 + attribute \src "libresoc.v:187658.3-187659.89" + process $proc$libresoc.v:187658$12330 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:187603.3-187604.85" - process $proc$libresoc.v:187603$12535 + attribute \src "libresoc.v:187660.3-187661.85" + process $proc$libresoc.v:187660$12331 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:187605.3-187606.73" - process $proc$libresoc.v:187605$12536 + attribute \src "libresoc.v:187662.3-187663.73" + process $proc$libresoc.v:187662$12332 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:187607.3-187608.73" - process $proc$libresoc.v:187607$12537 + attribute \src "libresoc.v:187664.3-187665.73" + process $proc$libresoc.v:187664$12333 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:187609.3-187610.73" - process $proc$libresoc.v:187609$12538 + attribute \src "libresoc.v:187666.3-187667.73" + process $proc$libresoc.v:187666$12334 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:187611.3-187612.73" - process $proc$libresoc.v:187611$12539 + attribute \src "libresoc.v:187668.3-187669.73" + process $proc$libresoc.v:187668$12335 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:187613.3-187614.79" - process $proc$libresoc.v:187613$12540 + attribute \src "libresoc.v:187670.3-187671.79" + process $proc$libresoc.v:187670$12336 assign { } { } assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:187615.3-187616.79" - process $proc$libresoc.v:187615$12541 + attribute \src "libresoc.v:187672.3-187673.79" + process $proc$libresoc.v:187672$12337 assign { } { } assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:187617.3-187618.83" - process $proc$libresoc.v:187617$12542 + attribute \src "libresoc.v:187674.3-187675.83" + process $proc$libresoc.v:187674$12338 assign { } { } assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:187619.3-187620.85" - process $proc$libresoc.v:187619$12543 + attribute \src "libresoc.v:187676.3-187677.85" + process $proc$libresoc.v:187676$12339 assign { } { } assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:187621.3-187622.77" - process $proc$libresoc.v:187621$12544 + attribute \src "libresoc.v:187678.3-187679.77" + process $proc$libresoc.v:187678$12340 assign { } { } assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:187623.3-187624.79" - process $proc$libresoc.v:187623$12545 + attribute \src "libresoc.v:187680.3-187681.79" + process $proc$libresoc.v:187680$12341 assign { } { } assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:187625.3-187626.77" - process $proc$libresoc.v:187625$12546 + attribute \src "libresoc.v:187682.3-187683.77" + process $proc$libresoc.v:187682$12342 assign { } { } assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:187627.3-187628.79" - process $proc$libresoc.v:187627$12547 + attribute \src "libresoc.v:187684.3-187685.79" + process $proc$libresoc.v:187684$12343 assign { } { } assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:187629.3-187630.69" - process $proc$libresoc.v:187629$12548 + attribute \src "libresoc.v:187686.3-187687.69" + process $proc$libresoc.v:187686$12344 assign { } { } assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:187631.3-187632.39" - process $proc$libresoc.v:187631$12549 + attribute \src "libresoc.v:187688.3-187689.39" + process $proc$libresoc.v:187688$12345 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:187633.3-187634.39" - process $proc$libresoc.v:187633$12550 + attribute \src "libresoc.v:187690.3-187691.39" + process $proc$libresoc.v:187690$12346 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:187635.3-187636.39" - process $proc$libresoc.v:187635$12551 + attribute \src "libresoc.v:187692.3-187693.39" + process $proc$libresoc.v:187692$12347 assign { } { } assign $0\src_l_r_src[4:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[4:0] end - attribute \src "libresoc.v:187637.3-187638.39" - process $proc$libresoc.v:187637$12552 + attribute \src "libresoc.v:187694.3-187695.39" + process $proc$libresoc.v:187694$12348 assign { } { } assign $0\src_l_s_src[4:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[4:0] end - attribute \src "libresoc.v:187639.3-187640.39" - process $proc$libresoc.v:187639$12553 + attribute \src "libresoc.v:187696.3-187697.39" + process $proc$libresoc.v:187696$12349 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:187641.3-187642.39" - process $proc$libresoc.v:187641$12554 + attribute \src "libresoc.v:187698.3-187699.39" + process $proc$libresoc.v:187698$12350 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:187643.3-187644.39" - process $proc$libresoc.v:187643$12555 + attribute \src "libresoc.v:187700.3-187701.39" + process $proc$libresoc.v:187700$12351 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:187645.3-187646.39" - process $proc$libresoc.v:187645$12556 + attribute \src "libresoc.v:187702.3-187703.39" + process $proc$libresoc.v:187702$12352 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:187647.3-187648.41" - process $proc$libresoc.v:187647$12557 + attribute \src "libresoc.v:187704.3-187705.41" + process $proc$libresoc.v:187704$12353 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:187649.3-187650.41" - process $proc$libresoc.v:187649$12558 + attribute \src "libresoc.v:187706.3-187707.41" + process $proc$libresoc.v:187706$12354 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:187651.3-187652.37" - process $proc$libresoc.v:187651$12559 + attribute \src "libresoc.v:187708.3-187709.37" + process $proc$libresoc.v:187708$12355 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:187653.3-187654.46" - process $proc$libresoc.v:187653$12560 + attribute \src "libresoc.v:187710.3-187711.46" + process $proc$libresoc.v:187710$12356 assign { } { } assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:187655.3-187656.25" - process $proc$libresoc.v:187655$12561 + attribute \src "libresoc.v:187712.3-187713.25" + process $proc$libresoc.v:187712$12357 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:187741.3-187750.6" - process $proc$libresoc.v:187741$12562 + attribute \src "libresoc.v:187798.3-187807.6" + process $proc$libresoc.v:187798$12358 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:187742.5-187742.29" + attribute \src "libresoc.v:187799.5-187799.29" switch \initial - attribute \src "libresoc.v:187742.9-187742.17" + attribute \src "libresoc.v:187799.9-187799.17" case 1'1 case end @@ -390324,14 +355313,14 @@ module \shiftrot0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:187751.3-187759.6" - process $proc$libresoc.v:187751$12563 + attribute \src "libresoc.v:187808.3-187816.6" + process $proc$libresoc.v:187808$12359 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12564 $1\rok_l_s_rdok$next[0:0]$12565 - attribute \src "libresoc.v:187752.5-187752.29" + assign $0\rok_l_s_rdok$next[0:0]$12360 $1\rok_l_s_rdok$next[0:0]$12361 + attribute \src "libresoc.v:187809.5-187809.29" switch \initial - attribute \src "libresoc.v:187752.9-187752.17" + attribute \src "libresoc.v:187809.9-187809.17" case 1'1 case end @@ -390340,21 +355329,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12565 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12361 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$12565 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12361 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12564 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12360 end - attribute \src "libresoc.v:187760.3-187768.6" - process $proc$libresoc.v:187760$12566 + attribute \src "libresoc.v:187817.3-187825.6" + process $proc$libresoc.v:187817$12362 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12567 $1\rok_l_r_rdok$next[0:0]$12568 - attribute \src "libresoc.v:187761.5-187761.29" + assign $0\rok_l_r_rdok$next[0:0]$12363 $1\rok_l_r_rdok$next[0:0]$12364 + attribute \src "libresoc.v:187818.5-187818.29" switch \initial - attribute \src "libresoc.v:187761.9-187761.17" + attribute \src "libresoc.v:187818.9-187818.17" case 1'1 case end @@ -390363,21 +355352,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12568 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12364 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12568 \$64 + assign $1\rok_l_r_rdok$next[0:0]$12364 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12567 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12363 end - attribute \src "libresoc.v:187769.3-187777.6" - process $proc$libresoc.v:187769$12569 + attribute \src "libresoc.v:187826.3-187834.6" + process $proc$libresoc.v:187826$12365 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12570 $1\rst_l_s_rst$next[0:0]$12571 - attribute \src "libresoc.v:187770.5-187770.29" + assign $0\rst_l_s_rst$next[0:0]$12366 $1\rst_l_s_rst$next[0:0]$12367 + attribute \src "libresoc.v:187827.5-187827.29" switch \initial - attribute \src "libresoc.v:187770.9-187770.17" + attribute \src "libresoc.v:187827.9-187827.17" case 1'1 case end @@ -390386,21 +355375,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12571 1'0 + assign $1\rst_l_s_rst$next[0:0]$12367 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12571 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12367 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12570 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12366 end - attribute \src "libresoc.v:187778.3-187786.6" - process $proc$libresoc.v:187778$12572 + attribute \src "libresoc.v:187835.3-187843.6" + process $proc$libresoc.v:187835$12368 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12573 $1\rst_l_r_rst$next[0:0]$12574 - attribute \src "libresoc.v:187779.5-187779.29" + assign $0\rst_l_r_rst$next[0:0]$12369 $1\rst_l_r_rst$next[0:0]$12370 + attribute \src "libresoc.v:187836.5-187836.29" switch \initial - attribute \src "libresoc.v:187779.9-187779.17" + attribute \src "libresoc.v:187836.9-187836.17" case 1'1 case end @@ -390409,21 +355398,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12574 1'1 + assign $1\rst_l_r_rst$next[0:0]$12370 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12574 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12370 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12573 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12369 end - attribute \src "libresoc.v:187787.3-187795.6" - process $proc$libresoc.v:187787$12575 + attribute \src "libresoc.v:187844.3-187852.6" + process $proc$libresoc.v:187844$12371 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12576 $1\opc_l_s_opc$next[0:0]$12577 - attribute \src "libresoc.v:187788.5-187788.29" + assign $0\opc_l_s_opc$next[0:0]$12372 $1\opc_l_s_opc$next[0:0]$12373 + attribute \src "libresoc.v:187845.5-187845.29" switch \initial - attribute \src "libresoc.v:187788.9-187788.17" + attribute \src "libresoc.v:187845.9-187845.17" case 1'1 case end @@ -390432,21 +355421,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12577 1'0 + assign $1\opc_l_s_opc$next[0:0]$12373 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12577 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12373 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12576 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12372 end - attribute \src "libresoc.v:187796.3-187804.6" - process $proc$libresoc.v:187796$12578 + attribute \src "libresoc.v:187853.3-187861.6" + process $proc$libresoc.v:187853$12374 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12579 $1\opc_l_r_opc$next[0:0]$12580 - attribute \src "libresoc.v:187797.5-187797.29" + assign $0\opc_l_r_opc$next[0:0]$12375 $1\opc_l_r_opc$next[0:0]$12376 + attribute \src "libresoc.v:187854.5-187854.29" switch \initial - attribute \src "libresoc.v:187797.9-187797.17" + attribute \src "libresoc.v:187854.9-187854.17" case 1'1 case end @@ -390455,21 +355444,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12580 1'1 + assign $1\opc_l_r_opc$next[0:0]$12376 1'1 case - assign $1\opc_l_r_opc$next[0:0]$12580 \req_done + assign $1\opc_l_r_opc$next[0:0]$12376 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12579 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12375 end - attribute \src "libresoc.v:187805.3-187813.6" - process $proc$libresoc.v:187805$12581 + attribute \src "libresoc.v:187862.3-187870.6" + process $proc$libresoc.v:187862$12377 assign { } { } assign { } { } - assign $0\src_l_s_src$next[4:0]$12582 $1\src_l_s_src$next[4:0]$12583 - attribute \src "libresoc.v:187806.5-187806.29" + assign $0\src_l_s_src$next[4:0]$12378 $1\src_l_s_src$next[4:0]$12379 + attribute \src "libresoc.v:187863.5-187863.29" switch \initial - attribute \src "libresoc.v:187806.9-187806.17" + attribute \src "libresoc.v:187863.9-187863.17" case 1'1 case end @@ -390478,21 +355467,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[4:0]$12583 5'00000 + assign $1\src_l_s_src$next[4:0]$12379 5'00000 case - assign $1\src_l_s_src$next[4:0]$12583 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[4:0]$12379 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12582 + update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12378 end - attribute \src "libresoc.v:187814.3-187822.6" - process $proc$libresoc.v:187814$12584 + attribute \src "libresoc.v:187871.3-187879.6" + process $proc$libresoc.v:187871$12380 assign { } { } assign { } { } - assign $0\src_l_r_src$next[4:0]$12585 $1\src_l_r_src$next[4:0]$12586 - attribute \src "libresoc.v:187815.5-187815.29" + assign $0\src_l_r_src$next[4:0]$12381 $1\src_l_r_src$next[4:0]$12382 + attribute \src "libresoc.v:187872.5-187872.29" switch \initial - attribute \src "libresoc.v:187815.9-187815.17" + attribute \src "libresoc.v:187872.9-187872.17" case 1'1 case end @@ -390501,21 +355490,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[4:0]$12586 5'11111 + assign $1\src_l_r_src$next[4:0]$12382 5'11111 case - assign $1\src_l_r_src$next[4:0]$12586 \reset_r + assign $1\src_l_r_src$next[4:0]$12382 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12585 + update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12381 end - attribute \src "libresoc.v:187823.3-187831.6" - process $proc$libresoc.v:187823$12587 + attribute \src "libresoc.v:187880.3-187888.6" + process $proc$libresoc.v:187880$12383 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$12588 $1\req_l_s_req$next[2:0]$12589 - attribute \src "libresoc.v:187824.5-187824.29" + assign $0\req_l_s_req$next[2:0]$12384 $1\req_l_s_req$next[2:0]$12385 + attribute \src "libresoc.v:187881.5-187881.29" switch \initial - attribute \src "libresoc.v:187824.9-187824.17" + attribute \src "libresoc.v:187881.9-187881.17" case 1'1 case end @@ -390524,21 +355513,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[2:0]$12589 3'000 + assign $1\req_l_s_req$next[2:0]$12385 3'000 case - assign $1\req_l_s_req$next[2:0]$12589 \$66 + assign $1\req_l_s_req$next[2:0]$12385 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12588 + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12384 end - attribute \src "libresoc.v:187832.3-187840.6" - process $proc$libresoc.v:187832$12590 + attribute \src "libresoc.v:187889.3-187897.6" + process $proc$libresoc.v:187889$12386 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$12591 $1\req_l_r_req$next[2:0]$12592 - attribute \src "libresoc.v:187833.5-187833.29" + assign $0\req_l_r_req$next[2:0]$12387 $1\req_l_r_req$next[2:0]$12388 + attribute \src "libresoc.v:187890.5-187890.29" switch \initial - attribute \src "libresoc.v:187833.9-187833.17" + attribute \src "libresoc.v:187890.9-187890.17" case 1'1 case end @@ -390547,15 +355536,15 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[2:0]$12592 3'111 + assign $1\req_l_r_req$next[2:0]$12388 3'111 case - assign $1\req_l_r_req$next[2:0]$12592 \$68 + assign $1\req_l_r_req$next[2:0]$12388 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12591 + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12387 end - attribute \src "libresoc.v:187841.3-187878.6" - process $proc$libresoc.v:187841$12593 + attribute \src "libresoc.v:187898.3-187935.6" + process $proc$libresoc.v:187898$12389 assign { } { } assign { } { } assign { } { } @@ -390590,32 +355579,32 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 + assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12390 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12407 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 - assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 - assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 - assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 - assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 - assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 - assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 + assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12393 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12410 + assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12394 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12411 + assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12395 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12412 + assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12396 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12413 + assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12397 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12414 + assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12398 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12415 + assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12399 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12416 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 - assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 + assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12402 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12419 + assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12403 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12420 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 - assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 - assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 - assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 - assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 - assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 - assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 - attribute \src "libresoc.v:187842.5-187842.29" + assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12406 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12423 + assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12391 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12424 + assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12392 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12425 + assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12400 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12426 + assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12401 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12427 + assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12404 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12428 + assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12405 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12429 + attribute \src "libresoc.v:187899.5-187899.29" switch \initial - attribute \src "libresoc.v:187842.9-187842.17" + attribute \src "libresoc.v:187899.9-187899.17" case 1'1 case end @@ -390640,25 +355629,25 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12412 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12416 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12415 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12420 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12411 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12419 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12410 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12414 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12423 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12418 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12417 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12421 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12422 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12409 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12408 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12407 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12413 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } case - assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 \alu_shift_rot0_sr_op__fn_unit - assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 \alu_shift_rot0_sr_op__imm_data__data - assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 \alu_shift_rot0_sr_op__imm_data__ok - assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 \alu_shift_rot0_sr_op__input_carry - assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 \alu_shift_rot0_sr_op__input_cr - assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 \alu_shift_rot0_sr_op__insn - assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 \alu_shift_rot0_sr_op__insn_type - assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 \alu_shift_rot0_sr_op__invert_in - assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 \alu_shift_rot0_sr_op__is_32bit - assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 \alu_shift_rot0_sr_op__is_signed - assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 \alu_shift_rot0_sr_op__oe__oe - assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 \alu_shift_rot0_sr_op__oe__ok - assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 \alu_shift_rot0_sr_op__output_carry - assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 \alu_shift_rot0_sr_op__output_cr - assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 \alu_shift_rot0_sr_op__rc__ok - assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 \alu_shift_rot0_sr_op__rc__rc - assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 \alu_shift_rot0_sr_op__write_cr0 + assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12407 \alu_shift_rot0_sr_op__fn_unit + assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12408 \alu_shift_rot0_sr_op__imm_data__data + assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12409 \alu_shift_rot0_sr_op__imm_data__ok + assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12410 \alu_shift_rot0_sr_op__input_carry + assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12411 \alu_shift_rot0_sr_op__input_cr + assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12412 \alu_shift_rot0_sr_op__insn + assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12413 \alu_shift_rot0_sr_op__insn_type + assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12414 \alu_shift_rot0_sr_op__invert_in + assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12415 \alu_shift_rot0_sr_op__is_32bit + assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12416 \alu_shift_rot0_sr_op__is_signed + assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12417 \alu_shift_rot0_sr_op__oe__oe + assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12418 \alu_shift_rot0_sr_op__oe__ok + assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12419 \alu_shift_rot0_sr_op__output_carry + assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12420 \alu_shift_rot0_sr_op__output_cr + assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12421 \alu_shift_rot0_sr_op__rc__ok + assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12422 \alu_shift_rot0_sr_op__rc__rc + assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12423 \alu_shift_rot0_sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -390670,53 +355659,53 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 1'0 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 1'0 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 1'0 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 1'0 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 1'0 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12424 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12425 1'0 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12429 1'0 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12428 1'0 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12426 1'0 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12427 1'0 case - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12424 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12408 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12425 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12409 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12426 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12417 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12427 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12418 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12428 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12421 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12429 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12422 end sync always - update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 - update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 - update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 - update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 - update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 - update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 - update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 - update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 - update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 - update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 - update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 - update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 - update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 - update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 - update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 - update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 - update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 + update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12390 + update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12391 + update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12392 + update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12393 + update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12394 + update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12395 + update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12396 + update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12397 + update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12398 + update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12399 + update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12400 + update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12401 + update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12402 + update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12403 + update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12404 + update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12405 + update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12406 end - attribute \src "libresoc.v:187879.3-187900.6" - process $proc$libresoc.v:187879$12634 + attribute \src "libresoc.v:187936.3-187957.6" + process $proc$libresoc.v:187936$12430 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12635 $2\data_r0__o$next[63:0]$12639 + assign $0\data_r0__o$next[63:0]$12431 $2\data_r0__o$next[63:0]$12435 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12636 $3\data_r0__o_ok$next[0:0]$12641 - attribute \src "libresoc.v:187880.5-187880.29" + assign $0\data_r0__o_ok$next[0:0]$12432 $3\data_r0__o_ok$next[0:0]$12437 + attribute \src "libresoc.v:187937.5-187937.29" switch \initial - attribute \src "libresoc.v:187880.9-187880.17" + attribute \src "libresoc.v:187937.9-187937.17" case 1'1 case end @@ -390726,10 +355715,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12638 $1\data_r0__o$next[63:0]$12637 } { \o_ok \alu_shift_rot0_o } + assign { $1\data_r0__o_ok$next[0:0]$12434 $1\data_r0__o$next[63:0]$12433 } { \o_ok \alu_shift_rot0_o } case - assign $1\data_r0__o$next[63:0]$12637 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12638 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12433 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12434 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -390737,38 +355726,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12640 $2\data_r0__o$next[63:0]$12639 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12436 $2\data_r0__o$next[63:0]$12435 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12639 $1\data_r0__o$next[63:0]$12637 - assign $2\data_r0__o_ok$next[0:0]$12640 $1\data_r0__o_ok$next[0:0]$12638 + assign $2\data_r0__o$next[63:0]$12435 $1\data_r0__o$next[63:0]$12433 + assign $2\data_r0__o_ok$next[0:0]$12436 $1\data_r0__o_ok$next[0:0]$12434 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12641 1'0 + assign $3\data_r0__o_ok$next[0:0]$12437 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12641 $2\data_r0__o_ok$next[0:0]$12640 + assign $3\data_r0__o_ok$next[0:0]$12437 $2\data_r0__o_ok$next[0:0]$12436 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12635 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12636 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12431 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12432 end - attribute \src "libresoc.v:187901.3-187922.6" - process $proc$libresoc.v:187901$12642 + attribute \src "libresoc.v:187958.3-187979.6" + process $proc$libresoc.v:187958$12438 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$12643 $2\data_r1__cr_a$next[3:0]$12647 + assign $0\data_r1__cr_a$next[3:0]$12439 $2\data_r1__cr_a$next[3:0]$12443 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$12644 $3\data_r1__cr_a_ok$next[0:0]$12649 - attribute \src "libresoc.v:187902.5-187902.29" + assign $0\data_r1__cr_a_ok$next[0:0]$12440 $3\data_r1__cr_a_ok$next[0:0]$12445 + attribute \src "libresoc.v:187959.5-187959.29" switch \initial - attribute \src "libresoc.v:187902.9-187902.17" + attribute \src "libresoc.v:187959.9-187959.17" case 1'1 case end @@ -390778,10 +355767,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$12646 $1\data_r1__cr_a$next[3:0]$12645 } { \cr_a_ok \alu_shift_rot0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$12442 $1\data_r1__cr_a$next[3:0]$12441 } { \cr_a_ok \alu_shift_rot0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$12645 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$12646 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$12441 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$12442 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -390789,38 +355778,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$12648 $2\data_r1__cr_a$next[3:0]$12647 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$12444 $2\data_r1__cr_a$next[3:0]$12443 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$12647 $1\data_r1__cr_a$next[3:0]$12645 - assign $2\data_r1__cr_a_ok$next[0:0]$12648 $1\data_r1__cr_a_ok$next[0:0]$12646 + assign $2\data_r1__cr_a$next[3:0]$12443 $1\data_r1__cr_a$next[3:0]$12441 + assign $2\data_r1__cr_a_ok$next[0:0]$12444 $1\data_r1__cr_a_ok$next[0:0]$12442 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$12649 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$12445 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$12649 $2\data_r1__cr_a_ok$next[0:0]$12648 + assign $3\data_r1__cr_a_ok$next[0:0]$12445 $2\data_r1__cr_a_ok$next[0:0]$12444 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12643 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12644 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12439 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12440 end - attribute \src "libresoc.v:187923.3-187944.6" - process $proc$libresoc.v:187923$12650 + attribute \src "libresoc.v:187980.3-188001.6" + process $proc$libresoc.v:187980$12446 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ca$next[1:0]$12651 $2\data_r2__xer_ca$next[1:0]$12655 + assign $0\data_r2__xer_ca$next[1:0]$12447 $2\data_r2__xer_ca$next[1:0]$12451 assign { } { } - assign $0\data_r2__xer_ca_ok$next[0:0]$12652 $3\data_r2__xer_ca_ok$next[0:0]$12657 - attribute \src "libresoc.v:187924.5-187924.29" + assign $0\data_r2__xer_ca_ok$next[0:0]$12448 $3\data_r2__xer_ca_ok$next[0:0]$12453 + attribute \src "libresoc.v:187981.5-187981.29" switch \initial - attribute \src "libresoc.v:187924.9-187924.17" + attribute \src "libresoc.v:187981.9-187981.17" case 1'1 case end @@ -390830,10 +355819,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ca_ok$next[0:0]$12654 $1\data_r2__xer_ca$next[1:0]$12653 } { \xer_ca_ok \alu_shift_rot0_xer_ca } + assign { $1\data_r2__xer_ca_ok$next[0:0]$12450 $1\data_r2__xer_ca$next[1:0]$12449 } { \xer_ca_ok \alu_shift_rot0_xer_ca } case - assign $1\data_r2__xer_ca$next[1:0]$12653 \data_r2__xer_ca - assign $1\data_r2__xer_ca_ok$next[0:0]$12654 \data_r2__xer_ca_ok + assign $1\data_r2__xer_ca$next[1:0]$12449 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$12450 \data_r2__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -390841,32 +355830,32 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ca_ok$next[0:0]$12656 $2\data_r2__xer_ca$next[1:0]$12655 } 3'000 + assign { $2\data_r2__xer_ca_ok$next[0:0]$12452 $2\data_r2__xer_ca$next[1:0]$12451 } 3'000 case - assign $2\data_r2__xer_ca$next[1:0]$12655 $1\data_r2__xer_ca$next[1:0]$12653 - assign $2\data_r2__xer_ca_ok$next[0:0]$12656 $1\data_r2__xer_ca_ok$next[0:0]$12654 + assign $2\data_r2__xer_ca$next[1:0]$12451 $1\data_r2__xer_ca$next[1:0]$12449 + assign $2\data_r2__xer_ca_ok$next[0:0]$12452 $1\data_r2__xer_ca_ok$next[0:0]$12450 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ca_ok$next[0:0]$12657 1'0 + assign $3\data_r2__xer_ca_ok$next[0:0]$12453 1'0 case - assign $3\data_r2__xer_ca_ok$next[0:0]$12657 $2\data_r2__xer_ca_ok$next[0:0]$12656 + assign $3\data_r2__xer_ca_ok$next[0:0]$12453 $2\data_r2__xer_ca_ok$next[0:0]$12452 end sync always - update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12651 - update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12652 + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12447 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12448 end - attribute \src "libresoc.v:187945.3-187954.6" - process $proc$libresoc.v:187945$12658 + attribute \src "libresoc.v:188002.3-188011.6" + process $proc$libresoc.v:188002$12454 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12659 $1\src_r0$next[63:0]$12660 - attribute \src "libresoc.v:187946.5-187946.29" + assign $0\src_r0$next[63:0]$12455 $1\src_r0$next[63:0]$12456 + attribute \src "libresoc.v:188003.5-188003.29" switch \initial - attribute \src "libresoc.v:187946.9-187946.17" + attribute \src "libresoc.v:188003.9-188003.17" case 1'1 case end @@ -390875,21 +355864,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12660 \src1_i + assign $1\src_r0$next[63:0]$12456 \src1_i case - assign $1\src_r0$next[63:0]$12660 \src_r0 + assign $1\src_r0$next[63:0]$12456 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12659 + update \src_r0$next $0\src_r0$next[63:0]$12455 end - attribute \src "libresoc.v:187955.3-187964.6" - process $proc$libresoc.v:187955$12661 + attribute \src "libresoc.v:188012.3-188021.6" + process $proc$libresoc.v:188012$12457 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12662 $1\src_r1$next[63:0]$12663 - attribute \src "libresoc.v:187956.5-187956.29" + assign $0\src_r1$next[63:0]$12458 $1\src_r1$next[63:0]$12459 + attribute \src "libresoc.v:188013.5-188013.29" switch \initial - attribute \src "libresoc.v:187956.9-187956.17" + attribute \src "libresoc.v:188013.9-188013.17" case 1'1 case end @@ -390898,21 +355887,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12663 \src_or_imm + assign $1\src_r1$next[63:0]$12459 \src_or_imm case - assign $1\src_r1$next[63:0]$12663 \src_r1 + assign $1\src_r1$next[63:0]$12459 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12662 + update \src_r1$next $0\src_r1$next[63:0]$12458 end - attribute \src "libresoc.v:187965.3-187974.6" - process $proc$libresoc.v:187965$12664 + attribute \src "libresoc.v:188022.3-188031.6" + process $proc$libresoc.v:188022$12460 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12665 $1\src_r2$next[63:0]$12666 - attribute \src "libresoc.v:187966.5-187966.29" + assign $0\src_r2$next[63:0]$12461 $1\src_r2$next[63:0]$12462 + attribute \src "libresoc.v:188023.5-188023.29" switch \initial - attribute \src "libresoc.v:187966.9-187966.17" + attribute \src "libresoc.v:188023.9-188023.17" case 1'1 case end @@ -390921,21 +355910,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12666 \src3_i + assign $1\src_r2$next[63:0]$12462 \src3_i case - assign $1\src_r2$next[63:0]$12666 \src_r2 + assign $1\src_r2$next[63:0]$12462 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12665 + update \src_r2$next $0\src_r2$next[63:0]$12461 end - attribute \src "libresoc.v:187975.3-187984.6" - process $proc$libresoc.v:187975$12667 + attribute \src "libresoc.v:188032.3-188041.6" + process $proc$libresoc.v:188032$12463 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12668 $1\src_r3$next[0:0]$12669 - attribute \src "libresoc.v:187976.5-187976.29" + assign $0\src_r3$next[0:0]$12464 $1\src_r3$next[0:0]$12465 + attribute \src "libresoc.v:188033.5-188033.29" switch \initial - attribute \src "libresoc.v:187976.9-187976.17" + attribute \src "libresoc.v:188033.9-188033.17" case 1'1 case end @@ -390944,21 +355933,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12669 \src4_i + assign $1\src_r3$next[0:0]$12465 \src4_i case - assign $1\src_r3$next[0:0]$12669 \src_r3 + assign $1\src_r3$next[0:0]$12465 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12668 + update \src_r3$next $0\src_r3$next[0:0]$12464 end - attribute \src "libresoc.v:187985.3-187994.6" - process $proc$libresoc.v:187985$12670 + attribute \src "libresoc.v:188042.3-188051.6" + process $proc$libresoc.v:188042$12466 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12671 $1\src_r4$next[1:0]$12672 - attribute \src "libresoc.v:187986.5-187986.29" + assign $0\src_r4$next[1:0]$12467 $1\src_r4$next[1:0]$12468 + attribute \src "libresoc.v:188043.5-188043.29" switch \initial - attribute \src "libresoc.v:187986.9-187986.17" + attribute \src "libresoc.v:188043.9-188043.17" case 1'1 case end @@ -390967,21 +355956,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12672 \src5_i + assign $1\src_r4$next[1:0]$12468 \src5_i case - assign $1\src_r4$next[1:0]$12672 \src_r4 + assign $1\src_r4$next[1:0]$12468 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12671 + update \src_r4$next $0\src_r4$next[1:0]$12467 end - attribute \src "libresoc.v:187995.3-188003.6" - process $proc$libresoc.v:187995$12673 + attribute \src "libresoc.v:188052.3-188060.6" + process $proc$libresoc.v:188052$12469 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12674 $1\alui_l_r_alui$next[0:0]$12675 - attribute \src "libresoc.v:187996.5-187996.29" + assign $0\alui_l_r_alui$next[0:0]$12470 $1\alui_l_r_alui$next[0:0]$12471 + attribute \src "libresoc.v:188053.5-188053.29" switch \initial - attribute \src "libresoc.v:187996.9-187996.17" + attribute \src "libresoc.v:188053.9-188053.17" case 1'1 case end @@ -390990,21 +355979,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12675 1'1 + assign $1\alui_l_r_alui$next[0:0]$12471 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12675 \$90 + assign $1\alui_l_r_alui$next[0:0]$12471 \$90 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12674 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12470 end - attribute \src "libresoc.v:188004.3-188012.6" - process $proc$libresoc.v:188004$12676 + attribute \src "libresoc.v:188061.3-188069.6" + process $proc$libresoc.v:188061$12472 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12677 $1\alu_l_r_alu$next[0:0]$12678 - attribute \src "libresoc.v:188005.5-188005.29" + assign $0\alu_l_r_alu$next[0:0]$12473 $1\alu_l_r_alu$next[0:0]$12474 + attribute \src "libresoc.v:188062.5-188062.29" switch \initial - attribute \src "libresoc.v:188005.9-188005.17" + attribute \src "libresoc.v:188062.9-188062.17" case 1'1 case end @@ -391013,21 +356002,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12678 1'1 + assign $1\alu_l_r_alu$next[0:0]$12474 1'1 case - assign $1\alu_l_r_alu$next[0:0]$12678 \$92 + assign $1\alu_l_r_alu$next[0:0]$12474 \$92 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12677 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12473 end - attribute \src "libresoc.v:188013.3-188022.6" - process $proc$libresoc.v:188013$12679 + attribute \src "libresoc.v:188070.3-188079.6" + process $proc$libresoc.v:188070$12475 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:188014.5-188014.29" + attribute \src "libresoc.v:188071.5-188071.29" switch \initial - attribute \src "libresoc.v:188014.9-188014.17" + attribute \src "libresoc.v:188071.9-188071.17" case 1'1 case end @@ -391043,14 +356032,14 @@ module \shiftrot0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:188023.3-188032.6" - process $proc$libresoc.v:188023$12680 + attribute \src "libresoc.v:188080.3-188089.6" + process $proc$libresoc.v:188080$12476 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:188024.5-188024.29" + attribute \src "libresoc.v:188081.5-188081.29" switch \initial - attribute \src "libresoc.v:188024.9-188024.17" + attribute \src "libresoc.v:188081.9-188081.17" case 1'1 case end @@ -391066,14 +356055,14 @@ module \shiftrot0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:188033.3-188042.6" - process $proc$libresoc.v:188033$12681 + attribute \src "libresoc.v:188090.3-188099.6" + process $proc$libresoc.v:188090$12477 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:188034.5-188034.29" + attribute \src "libresoc.v:188091.5-188091.29" switch \initial - attribute \src "libresoc.v:188034.9-188034.17" + attribute \src "libresoc.v:188091.9-188091.17" case 1'1 case end @@ -391089,14 +356078,14 @@ module \shiftrot0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:188043.3-188051.6" - process $proc$libresoc.v:188043$12682 + attribute \src "libresoc.v:188100.3-188108.6" + process $proc$libresoc.v:188100$12478 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$12683 $1\prev_wr_go$next[2:0]$12684 - attribute \src "libresoc.v:188044.5-188044.29" + assign $0\prev_wr_go$next[2:0]$12479 $1\prev_wr_go$next[2:0]$12480 + attribute \src "libresoc.v:188101.5-188101.29" switch \initial - attribute \src "libresoc.v:188044.9-188044.17" + attribute \src "libresoc.v:188101.9-188101.17" case 1'1 case end @@ -391105,72 +356094,72 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[2:0]$12684 3'000 - case - assign $1\prev_wr_go$next[2:0]$12684 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12683 - end - connect \$100 $not$libresoc.v:187512$12460_Y - connect \$102 $and$libresoc.v:187513$12461_Y - connect \$104 $and$libresoc.v:187514$12462_Y - connect \$106 $and$libresoc.v:187515$12463_Y - connect \$108 $and$libresoc.v:187516$12464_Y - connect \$10 $and$libresoc.v:187517$12465_Y - connect \$110 $and$libresoc.v:187518$12466_Y - connect \$112 $and$libresoc.v:187519$12467_Y - connect \$114 $and$libresoc.v:187520$12468_Y - connect \$116 $and$libresoc.v:187521$12469_Y - connect \$118 $and$libresoc.v:187522$12470_Y - connect \$12 $not$libresoc.v:187523$12471_Y - connect \$14 $and$libresoc.v:187524$12472_Y - connect \$16 $not$libresoc.v:187525$12473_Y - connect \$18 $and$libresoc.v:187526$12474_Y - connect \$20 $and$libresoc.v:187527$12475_Y - connect \$24 $not$libresoc.v:187528$12476_Y - connect \$26 $and$libresoc.v:187529$12477_Y - connect \$23 $reduce_or$libresoc.v:187530$12478_Y - connect \$22 $not$libresoc.v:187531$12479_Y - connect \$2 $and$libresoc.v:187532$12480_Y - connect \$30 $and$libresoc.v:187533$12481_Y - connect \$32 $reduce_or$libresoc.v:187534$12482_Y - connect \$34 $reduce_or$libresoc.v:187535$12483_Y - connect \$36 $or$libresoc.v:187536$12484_Y - connect \$38 $not$libresoc.v:187537$12485_Y - connect \$40 $and$libresoc.v:187538$12486_Y - connect \$42 $and$libresoc.v:187539$12487_Y - connect \$44 $eq$libresoc.v:187540$12488_Y - connect \$46 $and$libresoc.v:187541$12489_Y - connect \$48 $eq$libresoc.v:187542$12490_Y - connect \$50 $and$libresoc.v:187543$12491_Y - connect \$52 $and$libresoc.v:187544$12492_Y - connect \$54 $and$libresoc.v:187545$12493_Y - connect \$56 $or$libresoc.v:187546$12494_Y - connect \$58 $or$libresoc.v:187547$12495_Y - connect \$5 $not$libresoc.v:187548$12496_Y - connect \$60 $or$libresoc.v:187549$12497_Y - connect \$62 $or$libresoc.v:187550$12498_Y - connect \$64 $and$libresoc.v:187551$12499_Y - connect \$66 $and$libresoc.v:187552$12500_Y - connect \$68 $or$libresoc.v:187553$12501_Y - connect \$70 $and$libresoc.v:187554$12502_Y - connect \$72 $and$libresoc.v:187555$12503_Y - connect \$74 $and$libresoc.v:187556$12504_Y - connect \$76 $ternary$libresoc.v:187557$12505_Y - connect \$78 $ternary$libresoc.v:187558$12506_Y - connect \$7 $or$libresoc.v:187559$12507_Y - connect \$80 $ternary$libresoc.v:187560$12508_Y - connect \$82 $ternary$libresoc.v:187561$12509_Y - connect \$84 $ternary$libresoc.v:187562$12510_Y - connect \$86 $ternary$libresoc.v:187563$12511_Y - connect \$88 $ternary$libresoc.v:187564$12512_Y - connect \$4 $reduce_and$libresoc.v:187565$12513_Y - connect \$90 $and$libresoc.v:187566$12514_Y - connect \$92 $and$libresoc.v:187567$12515_Y - connect \$94 $and$libresoc.v:187568$12516_Y - connect \$96 $not$libresoc.v:187569$12517_Y - connect \$98 $and$libresoc.v:187570$12518_Y + assign $1\prev_wr_go$next[2:0]$12480 3'000 + case + assign $1\prev_wr_go$next[2:0]$12480 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12479 + end + connect \$100 $not$libresoc.v:187569$12256_Y + connect \$102 $and$libresoc.v:187570$12257_Y + connect \$104 $and$libresoc.v:187571$12258_Y + connect \$106 $and$libresoc.v:187572$12259_Y + connect \$108 $and$libresoc.v:187573$12260_Y + connect \$10 $and$libresoc.v:187574$12261_Y + connect \$110 $and$libresoc.v:187575$12262_Y + connect \$112 $and$libresoc.v:187576$12263_Y + connect \$114 $and$libresoc.v:187577$12264_Y + connect \$116 $and$libresoc.v:187578$12265_Y + connect \$118 $and$libresoc.v:187579$12266_Y + connect \$12 $not$libresoc.v:187580$12267_Y + connect \$14 $and$libresoc.v:187581$12268_Y + connect \$16 $not$libresoc.v:187582$12269_Y + connect \$18 $and$libresoc.v:187583$12270_Y + connect \$20 $and$libresoc.v:187584$12271_Y + connect \$24 $not$libresoc.v:187585$12272_Y + connect \$26 $and$libresoc.v:187586$12273_Y + connect \$23 $reduce_or$libresoc.v:187587$12274_Y + connect \$22 $not$libresoc.v:187588$12275_Y + connect \$2 $and$libresoc.v:187589$12276_Y + connect \$30 $and$libresoc.v:187590$12277_Y + connect \$32 $reduce_or$libresoc.v:187591$12278_Y + connect \$34 $reduce_or$libresoc.v:187592$12279_Y + connect \$36 $or$libresoc.v:187593$12280_Y + connect \$38 $not$libresoc.v:187594$12281_Y + connect \$40 $and$libresoc.v:187595$12282_Y + connect \$42 $and$libresoc.v:187596$12283_Y + connect \$44 $eq$libresoc.v:187597$12284_Y + connect \$46 $and$libresoc.v:187598$12285_Y + connect \$48 $eq$libresoc.v:187599$12286_Y + connect \$50 $and$libresoc.v:187600$12287_Y + connect \$52 $and$libresoc.v:187601$12288_Y + connect \$54 $and$libresoc.v:187602$12289_Y + connect \$56 $or$libresoc.v:187603$12290_Y + connect \$58 $or$libresoc.v:187604$12291_Y + connect \$5 $not$libresoc.v:187605$12292_Y + connect \$60 $or$libresoc.v:187606$12293_Y + connect \$62 $or$libresoc.v:187607$12294_Y + connect \$64 $and$libresoc.v:187608$12295_Y + connect \$66 $and$libresoc.v:187609$12296_Y + connect \$68 $or$libresoc.v:187610$12297_Y + connect \$70 $and$libresoc.v:187611$12298_Y + connect \$72 $and$libresoc.v:187612$12299_Y + connect \$74 $and$libresoc.v:187613$12300_Y + connect \$76 $ternary$libresoc.v:187614$12301_Y + connect \$78 $ternary$libresoc.v:187615$12302_Y + connect \$7 $or$libresoc.v:187616$12303_Y + connect \$80 $ternary$libresoc.v:187617$12304_Y + connect \$82 $ternary$libresoc.v:187618$12305_Y + connect \$84 $ternary$libresoc.v:187619$12306_Y + connect \$86 $ternary$libresoc.v:187620$12307_Y + connect \$88 $ternary$libresoc.v:187621$12308_Y + connect \$4 $reduce_and$libresoc.v:187622$12309_Y + connect \$90 $and$libresoc.v:187623$12310_Y + connect \$92 $and$libresoc.v:187624$12311_Y + connect \$94 $and$libresoc.v:187625$12312_Y + connect \$96 $not$libresoc.v:187626$12313_Y + connect \$98 $and$libresoc.v:187627$12314_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -391204,55 +356193,61 @@ module \shiftrot0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:188088.1-188268.10" +attribute \src "libresoc.v:188145.1-188223.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.spr" attribute \generator "nMigen" module \spr - attribute \src "libresoc.v:188240.3-188243.6" - wire width 7 $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 - attribute \src "libresoc.v:188240.3-188243.6" - wire width 64 $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 - attribute \src "libresoc.v:188240.3-188243.6" - wire width 64 $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 - attribute \src "libresoc.v:188240.3-188243.6" - wire width 7 $0\_0_[6:0] - attribute \src "libresoc.v:188089.7-188089.20" + attribute \src "libresoc.v:188193.3-188196.6" + wire width 4 $0$memwr$\memory$libresoc.v:188195$12536_ADDR[3:0]$12538 + attribute \src "libresoc.v:188193.3-188196.6" + wire width 64 $0$memwr$\memory$libresoc.v:188195$12536_DATA[63:0]$12539 + attribute \src "libresoc.v:188193.3-188196.6" + wire width 64 $0$memwr$\memory$libresoc.v:188195$12536_EN[63:0]$12540 + attribute \src "libresoc.v:188193.3-188196.6" + wire width 4 $0\_0_[3:0] + attribute \src "libresoc.v:188146.7-188146.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188245.3-188253.6" - wire $0\ren_delay$next[0:0]$12850 - attribute \src "libresoc.v:188121.3-188122.35" + attribute \src "libresoc.v:188200.3-188208.6" + wire $0\ren_delay$next[0:0]$12547 + attribute \src "libresoc.v:188198.3-188199.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:188254.3-188263.6" + attribute \src "libresoc.v:188209.3-188218.6" wire width 64 $0\spr1__data_o[63:0] - attribute \src "libresoc.v:188245.3-188253.6" - wire $1\ren_delay$next[0:0]$12851 - attribute \src "libresoc.v:188105.7-188105.23" + attribute \src "libresoc.v:188193.3-188196.6" + wire width 4 $1$memwr$\memory$libresoc.v:188195$12536_ADDR[3:0]$12541 + attribute \src "libresoc.v:188193.3-188196.6" + wire width 64 $1$memwr$\memory$libresoc.v:188195$12536_DATA[63:0]$12542 + attribute \src "libresoc.v:188193.3-188196.6" + wire width 64 $1$memwr$\memory$libresoc.v:188195$12536_EN[63:0]$12543 + attribute \src "libresoc.v:188200.3-188208.6" + wire $1\ren_delay$next[0:0]$12548 + attribute \src "libresoc.v:188162.7-188162.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:188254.3-188263.6" + attribute \src "libresoc.v:188209.3-188218.6" wire width 64 $1\spr1__data_o[63:0] - attribute \src "libresoc.v:188244.26-188244.32" - wire width 64 $memrd$\memory$libresoc.v:188244$12848_DATA + attribute \src "libresoc.v:188197.26-188197.32" + wire width 64 $memrd$\memory$libresoc.v:188197$12544_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 7 $memwr$\memory$libresoc.v:188242$12842_ADDR + wire width 4 $memwr$\memory$libresoc.v:188195$12536_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:188242$12842_DATA + wire width 64 $memwr$\memory$libresoc.v:188195$12536_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:188242$12842_EN - attribute \src "libresoc.v:188239.13-188239.16" - wire width 7 \_0_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire width 64 $memwr$\memory$libresoc.v:188195$12536_EN + attribute \src "libresoc.v:188192.13-188192.16" + wire width 4 \_0_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 8 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:188089.7-188089.15" + attribute \src "libresoc.v:188146.7-188146.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 7 \memory_r_addr + wire width 4 \memory_r_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 7 \memory_w_addr + wire width 4 \memory_w_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 64 \memory_w_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" @@ -391262,9 +356257,9 @@ module \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 7 input 3 \spr1__addr + wire width 4 input 3 \spr1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 7 input 6 \spr1__addr$1 + wire width 4 input 6 \spr1__addr$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 5 \spr1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" @@ -391273,1141 +356268,121 @@ module \spr wire input 4 \spr1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 7 \spr1__wen - attribute \src "libresoc.v:188123.14-188123.20" - memory width 64 size 113 \memory - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12853 + attribute \src "libresoc.v:188178.14-188178.20" + memory width 64 size 11 \memory + attribute \src "libresoc.v:188180.5-188180.37" + cell $meminit $meminit$\memory$libresoc.v:188180$12550 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12853 + parameter \PRIORITY 12550 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12854 + attribute \src "libresoc.v:188181.5-188181.37" + cell $meminit $meminit$\memory$libresoc.v:188181$12551 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12854 + parameter \PRIORITY 12551 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12855 + attribute \src "libresoc.v:188182.5-188182.37" + cell $meminit $meminit$\memory$libresoc.v:188182$12552 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12855 + parameter \PRIORITY 12552 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12856 + attribute \src "libresoc.v:188183.5-188183.37" + cell $meminit $meminit$\memory$libresoc.v:188183$12553 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12856 + parameter \PRIORITY 12553 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12857 + attribute \src "libresoc.v:188184.5-188184.37" + cell $meminit $meminit$\memory$libresoc.v:188184$12554 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12857 + parameter \PRIORITY 12554 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12858 + attribute \src "libresoc.v:188185.5-188185.37" + cell $meminit $meminit$\memory$libresoc.v:188185$12555 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12858 + parameter \PRIORITY 12555 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12859 + attribute \src "libresoc.v:188186.5-188186.37" + cell $meminit $meminit$\memory$libresoc.v:188186$12556 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12859 + parameter \PRIORITY 12556 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12860 + attribute \src "libresoc.v:188187.5-188187.37" + cell $meminit $meminit$\memory$libresoc.v:188187$12557 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12860 + parameter \PRIORITY 12557 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12861 + attribute \src "libresoc.v:188188.5-188188.37" + cell $meminit $meminit$\memory$libresoc.v:188188$12558 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12861 + parameter \PRIORITY 12558 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12862 + attribute \src "libresoc.v:188189.5-188189.37" + cell $meminit $meminit$\memory$libresoc.v:188189$12559 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12862 + parameter \PRIORITY 12559 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12863 + attribute \src "libresoc.v:188190.5-188190.38" + cell $meminit $meminit$\memory$libresoc.v:188190$12560 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12863 + parameter \PRIORITY 12560 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12864 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12864 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 11 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12865 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12865 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 12 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12866 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12866 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 13 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12867 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12867 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 14 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12868 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12868 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 15 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12869 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12869 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 16 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12870 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12870 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 17 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12871 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12871 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 18 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12872 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12872 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 19 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12873 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12873 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 20 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12874 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12874 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 21 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12875 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12875 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 22 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12876 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12876 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 23 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12877 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12877 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 24 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12878 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12878 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 25 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12879 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12879 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 26 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12880 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12880 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 27 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12881 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12881 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 28 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12882 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12882 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 29 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12883 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12883 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 30 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12884 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12884 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 31 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12885 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12885 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 32 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12886 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12886 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 33 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12887 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12887 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 34 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12888 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12888 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 35 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12889 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12889 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 36 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12890 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12890 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 37 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12891 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12891 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 38 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12892 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12892 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 39 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12893 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12893 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 40 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12894 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12894 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 41 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12895 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12895 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 42 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12896 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12896 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 43 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12897 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12897 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 44 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12898 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12898 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 45 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12899 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12899 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 46 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12900 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12900 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 47 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12901 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12901 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 48 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12902 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12902 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 49 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12903 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12903 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 50 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12904 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12904 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 51 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12905 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12905 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 52 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12906 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12906 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 53 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12907 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12907 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 54 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12908 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12908 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 55 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12909 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12909 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 56 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12910 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12910 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 57 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12911 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12911 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 58 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12912 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12912 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 59 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12913 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12913 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 60 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12914 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12914 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 61 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12915 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12915 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 62 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12916 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12916 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 63 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12917 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12917 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 64 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12918 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12918 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 65 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12919 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12919 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 66 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12920 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12920 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 67 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12921 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12921 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 68 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12922 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12922 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 69 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12923 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12923 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 70 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12924 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12924 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 71 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12925 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12925 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 72 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12926 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12926 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 73 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12927 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12927 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 74 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12928 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12928 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 75 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12929 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12929 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 76 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12930 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12930 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 77 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12931 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12931 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 78 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12932 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12932 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 79 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12933 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12933 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 80 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12934 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12934 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 81 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12935 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12935 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 82 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12936 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12936 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 83 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12937 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12937 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 84 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12938 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12938 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 85 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12939 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12939 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 86 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12940 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12940 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 87 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12941 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12941 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 88 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12942 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12942 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 89 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12943 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12943 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 90 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12944 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12944 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 91 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12945 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12945 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 92 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12946 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12946 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 93 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12947 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12947 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 94 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12948 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12948 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 95 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12949 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12949 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 96 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12950 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12950 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 97 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12951 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12951 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 98 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12952 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12952 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 99 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12953 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12953 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 100 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12954 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12954 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 101 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12955 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12955 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 102 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12956 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12956 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 103 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12957 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12957 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 104 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12958 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12958 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 105 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12959 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12959 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 106 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12960 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12960 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 107 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12961 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12961 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 108 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12962 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12962 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 109 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12963 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12963 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 110 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12964 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12964 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 111 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12965 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12965 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 112 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:188244.26-188244.32" - cell $memrd $memrd$\memory$libresoc.v:188244$12848 - parameter \ABITS 7 + attribute \src "libresoc.v:188197.26-188197.32" + cell $memrd $memrd$\memory$libresoc.v:188197$12544 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" @@ -392415,83 +356390,81 @@ module \spr parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:188244$12848_DATA + connect \DATA $memrd$\memory$libresoc.v:188197$12544_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$12966 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 12966 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:188242$12842_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:188242$12842_DATA - connect \EN $memwr$\memory$libresoc.v:188242$12842_EN - end - attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$12969 + process $proc$libresoc.v:0$12563 sync always sync init end - attribute \src "libresoc.v:188089.7-188089.20" - process $proc$libresoc.v:188089$12967 + attribute \src "libresoc.v:188146.7-188146.20" + process $proc$libresoc.v:188146$12561 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188105.7-188105.23" - process $proc$libresoc.v:188105$12968 + attribute \src "libresoc.v:188162.7-188162.23" + process $proc$libresoc.v:188162$12562 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:188121.3-188122.35" - process $proc$libresoc.v:188121$12843 + attribute \src "libresoc.v:188193.3-188196.6" + process $proc$libresoc.v:188193$12537 + assign { } { } + assign { } { } assign { } { } - assign $0\ren_delay[0:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[0:0] - end - attribute \src "libresoc.v:188240.3-188243.6" - process $proc$libresoc.v:188240$12844 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 7'xxxxxxx - assign $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\_0_[6:0] \spr1__addr - attribute \src "libresoc.v:188242.5-188242.59" - switch \spr1__wen - attribute \src "libresoc.v:188242.9-188242.18" + assign $0\_0_[3:0] \memory_r_addr + assign $0$memwr$\memory$libresoc.v:188195$12536_ADDR[3:0]$12538 $1$memwr$\memory$libresoc.v:188195$12536_ADDR[3:0]$12541 + assign $0$memwr$\memory$libresoc.v:188195$12536_DATA[63:0]$12539 $1$memwr$\memory$libresoc.v:188195$12536_DATA[63:0]$12542 + assign $0$memwr$\memory$libresoc.v:188195$12536_EN[63:0]$12540 $1$memwr$\memory$libresoc.v:188195$12536_EN[63:0]$12543 + attribute \src "libresoc.v:188195.5-188195.61" + switch \memory_w_en + attribute \src "libresoc.v:188195.9-188195.20" case 1'1 - assign $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 \spr1__addr$1 - assign $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 \spr1__data_i - assign $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 64'1111111111111111111111111111111111111111111111111111111111111111 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\memory$libresoc.v:188195$12536_ADDR[3:0]$12541 \memory_w_addr + assign $1$memwr$\memory$libresoc.v:188195$12536_DATA[63:0]$12542 \memory_w_data + assign $1$memwr$\memory$libresoc.v:188195$12536_EN[63:0]$12543 64'1111111111111111111111111111111111111111111111111111111111111111 case + assign $1$memwr$\memory$libresoc.v:188195$12536_ADDR[3:0]$12541 4'xxxx + assign $1$memwr$\memory$libresoc.v:188195$12536_DATA[63:0]$12542 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\memory$libresoc.v:188195$12536_EN[63:0]$12543 64'0000000000000000000000000000000000000000000000000000000000000000 end sync posedge \coresync_clk - update \_0_ $0\_0_[6:0] - update $memwr$\memory$libresoc.v:188242$12842_ADDR $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 - update $memwr$\memory$libresoc.v:188242$12842_DATA $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 - update $memwr$\memory$libresoc.v:188242$12842_EN $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 + update \_0_ $0\_0_[3:0] + update $memwr$\memory$libresoc.v:188195$12536_ADDR $0$memwr$\memory$libresoc.v:188195$12536_ADDR[3:0]$12538 + update $memwr$\memory$libresoc.v:188195$12536_DATA $0$memwr$\memory$libresoc.v:188195$12536_DATA[63:0]$12539 + update $memwr$\memory$libresoc.v:188195$12536_EN $0$memwr$\memory$libresoc.v:188195$12536_EN[63:0]$12540 + attribute \src "libresoc.v:188195.22-188195.60" + memwr \memory $1$memwr$\memory$libresoc.v:188195$12536_ADDR[3:0]$12541 $1$memwr$\memory$libresoc.v:188195$12536_DATA[63:0]$12542 $1$memwr$\memory$libresoc.v:188195$12536_EN[63:0]$12543 0' end - attribute \src "libresoc.v:188245.3-188253.6" - process $proc$libresoc.v:188245$12849 + attribute \src "libresoc.v:188198.3-188199.35" + process $proc$libresoc.v:188198$12545 assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:188200.3-188208.6" + process $proc$libresoc.v:188200$12546 assign { } { } - assign $0\ren_delay$next[0:0]$12850 $1\ren_delay$next[0:0]$12851 - attribute \src "libresoc.v:188246.5-188246.29" + assign { } { } + assign $0\ren_delay$next[0:0]$12547 $1\ren_delay$next[0:0]$12548 + attribute \src "libresoc.v:188201.5-188201.29" switch \initial - attribute \src "libresoc.v:188246.9-188246.17" + attribute \src "libresoc.v:188201.9-188201.17" case 1'1 case end @@ -392500,21 +356473,21 @@ module \spr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$12851 1'0 + assign $1\ren_delay$next[0:0]$12548 1'0 case - assign $1\ren_delay$next[0:0]$12851 \spr1__ren + assign $1\ren_delay$next[0:0]$12548 \spr1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$12850 + update \ren_delay$next $0\ren_delay$next[0:0]$12547 end - attribute \src "libresoc.v:188254.3-188263.6" - process $proc$libresoc.v:188254$12852 + attribute \src "libresoc.v:188209.3-188218.6" + process $proc$libresoc.v:188209$12549 assign { } { } assign { } { } assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] - attribute \src "libresoc.v:188255.5-188255.29" + attribute \src "libresoc.v:188210.5-188210.29" switch \initial - attribute \src "libresoc.v:188255.9-188255.17" + attribute \src "libresoc.v:188210.9-188210.17" case 1'1 case end @@ -392530,503 +356503,503 @@ module \spr sync always update \spr1__data_o $0\spr1__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:188244$12848_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:188197$12544_DATA connect \memory_w_data \spr1__data_i connect \memory_w_en \spr1__wen connect \memory_w_addr \spr1__addr$1 connect \memory_r_addr \spr1__addr end -attribute \src "libresoc.v:188272.1-189525.10" +attribute \src "libresoc.v:188227.1-189480.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" attribute \generator "nMigen" module \spr0 - attribute \src "libresoc.v:189022.3-189023.25" + attribute \src "libresoc.v:188977.3-188978.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:189020.3-189021.40" + attribute \src "libresoc.v:188975.3-188976.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:189416.3-189424.6" - wire $0\alu_l_r_alu$next[0:0]$13183 - attribute \src "libresoc.v:188950.3-188951.39" + attribute \src "libresoc.v:189371.3-189379.6" + wire $0\alu_l_r_alu$next[0:0]$12777 + attribute \src "libresoc.v:188905.3-188906.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:189202.3-189214.6" - wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 - attribute \src "libresoc.v:188992.3-188993.65" + attribute \src "libresoc.v:189157.3-189169.6" + wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$12699 + attribute \src "libresoc.v:188947.3-188948.65" wire width 14 $0\alu_spr0_spr_op__fn_unit[13:0] - attribute \src "libresoc.v:189202.3-189214.6" - wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$13106 - attribute \src "libresoc.v:188994.3-188995.59" + attribute \src "libresoc.v:189157.3-189169.6" + wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12700 + attribute \src "libresoc.v:188949.3-188950.59" wire width 32 $0\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:189202.3-189214.6" - wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 - attribute \src "libresoc.v:188990.3-188991.69" + attribute \src "libresoc.v:189157.3-189169.6" + wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12701 + attribute \src "libresoc.v:188945.3-188946.69" wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:189202.3-189214.6" - wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 - attribute \src "libresoc.v:188996.3-188997.67" + attribute \src "libresoc.v:189157.3-189169.6" + wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12702 + attribute \src "libresoc.v:188951.3-188952.67" wire $0\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:189407.3-189415.6" - wire $0\alui_l_r_alui$next[0:0]$13180 - attribute \src "libresoc.v:188952.3-188953.43" + attribute \src "libresoc.v:189362.3-189370.6" + wire $0\alui_l_r_alui$next[0:0]$12774 + attribute \src "libresoc.v:188907.3-188908.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:189215.3-189236.6" - wire width 64 $0\data_r0__o$next[63:0]$13114 - attribute \src "libresoc.v:188986.3-188987.37" + attribute \src "libresoc.v:189170.3-189191.6" + wire width 64 $0\data_r0__o$next[63:0]$12708 + attribute \src "libresoc.v:188941.3-188942.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:189215.3-189236.6" - wire $0\data_r0__o_ok$next[0:0]$13115 - attribute \src "libresoc.v:188988.3-188989.43" + attribute \src "libresoc.v:189170.3-189191.6" + wire $0\data_r0__o_ok$next[0:0]$12709 + attribute \src "libresoc.v:188943.3-188944.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:189237.3-189258.6" - wire width 64 $0\data_r1__spr1$next[63:0]$13122 - attribute \src "libresoc.v:188982.3-188983.43" + attribute \src "libresoc.v:189192.3-189213.6" + wire width 64 $0\data_r1__spr1$next[63:0]$12716 + attribute \src "libresoc.v:188937.3-188938.43" wire width 64 $0\data_r1__spr1[63:0] - attribute \src "libresoc.v:189237.3-189258.6" - wire $0\data_r1__spr1_ok$next[0:0]$13123 - attribute \src "libresoc.v:188984.3-188985.49" + attribute \src "libresoc.v:189192.3-189213.6" + wire $0\data_r1__spr1_ok$next[0:0]$12717 + attribute \src "libresoc.v:188939.3-188940.49" wire $0\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:189259.3-189280.6" - wire width 64 $0\data_r2__fast1$next[63:0]$13130 - attribute \src "libresoc.v:188978.3-188979.45" + attribute \src "libresoc.v:189214.3-189235.6" + wire width 64 $0\data_r2__fast1$next[63:0]$12724 + attribute \src "libresoc.v:188933.3-188934.45" wire width 64 $0\data_r2__fast1[63:0] - attribute \src "libresoc.v:189259.3-189280.6" - wire $0\data_r2__fast1_ok$next[0:0]$13131 - attribute \src "libresoc.v:188980.3-188981.51" + attribute \src "libresoc.v:189214.3-189235.6" + wire $0\data_r2__fast1_ok$next[0:0]$12725 + attribute \src "libresoc.v:188935.3-188936.51" wire $0\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:189281.3-189302.6" - wire $0\data_r3__xer_so$next[0:0]$13138 - attribute \src "libresoc.v:188974.3-188975.47" + attribute \src "libresoc.v:189236.3-189257.6" + wire $0\data_r3__xer_so$next[0:0]$12732 + attribute \src "libresoc.v:188929.3-188930.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:189281.3-189302.6" - wire $0\data_r3__xer_so_ok$next[0:0]$13139 - attribute \src "libresoc.v:188976.3-188977.53" + attribute \src "libresoc.v:189236.3-189257.6" + wire $0\data_r3__xer_so_ok$next[0:0]$12733 + attribute \src "libresoc.v:188931.3-188932.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:189303.3-189324.6" - wire width 2 $0\data_r4__xer_ov$next[1:0]$13146 - attribute \src "libresoc.v:188970.3-188971.47" + attribute \src "libresoc.v:189258.3-189279.6" + wire width 2 $0\data_r4__xer_ov$next[1:0]$12740 + attribute \src "libresoc.v:188925.3-188926.47" wire width 2 $0\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:189303.3-189324.6" - wire $0\data_r4__xer_ov_ok$next[0:0]$13147 - attribute \src "libresoc.v:188972.3-188973.53" + attribute \src "libresoc.v:189258.3-189279.6" + wire $0\data_r4__xer_ov_ok$next[0:0]$12741 + attribute \src "libresoc.v:188927.3-188928.53" wire $0\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:189325.3-189346.6" - wire width 2 $0\data_r5__xer_ca$next[1:0]$13154 - attribute \src "libresoc.v:188966.3-188967.47" + attribute \src "libresoc.v:189280.3-189301.6" + wire width 2 $0\data_r5__xer_ca$next[1:0]$12748 + attribute \src "libresoc.v:188921.3-188922.47" wire width 2 $0\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:189325.3-189346.6" - wire $0\data_r5__xer_ca_ok$next[0:0]$13155 - attribute \src "libresoc.v:188968.3-188969.53" + attribute \src "libresoc.v:189280.3-189301.6" + wire $0\data_r5__xer_ca_ok$next[0:0]$12749 + attribute \src "libresoc.v:188923.3-188924.53" wire $0\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:189425.3-189434.6" + attribute \src "libresoc.v:189380.3-189389.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:189435.3-189444.6" + attribute \src "libresoc.v:189390.3-189399.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:189445.3-189454.6" + attribute \src "libresoc.v:189400.3-189409.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:189455.3-189464.6" + attribute \src "libresoc.v:189410.3-189419.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:189465.3-189474.6" + attribute \src "libresoc.v:189420.3-189429.6" wire width 2 $0\dest5_o[1:0] - attribute \src "libresoc.v:189475.3-189484.6" + attribute \src "libresoc.v:189430.3-189439.6" wire width 2 $0\dest6_o[1:0] - attribute \src "libresoc.v:188273.7-188273.20" + attribute \src "libresoc.v:188228.7-188228.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189157.3-189165.6" - wire $0\opc_l_r_opc$next[0:0]$13090 - attribute \src "libresoc.v:189006.3-189007.39" + attribute \src "libresoc.v:189112.3-189120.6" + wire $0\opc_l_r_opc$next[0:0]$12684 + attribute \src "libresoc.v:188961.3-188962.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:189148.3-189156.6" - wire $0\opc_l_s_opc$next[0:0]$13087 - attribute \src "libresoc.v:189008.3-189009.39" + attribute \src "libresoc.v:189103.3-189111.6" + wire $0\opc_l_s_opc$next[0:0]$12681 + attribute \src "libresoc.v:188963.3-188964.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:189485.3-189493.6" - wire width 6 $0\prev_wr_go$next[5:0]$13192 - attribute \src "libresoc.v:189018.3-189019.37" + attribute \src "libresoc.v:189440.3-189448.6" + wire width 6 $0\prev_wr_go$next[5:0]$12786 + attribute \src "libresoc.v:188973.3-188974.37" wire width 6 $0\prev_wr_go[5:0] - attribute \src "libresoc.v:189102.3-189111.6" + attribute \src "libresoc.v:189057.3-189066.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:189193.3-189201.6" - wire width 6 $0\req_l_r_req$next[5:0]$13102 - attribute \src "libresoc.v:188998.3-188999.39" + attribute \src "libresoc.v:189148.3-189156.6" + wire width 6 $0\req_l_r_req$next[5:0]$12696 + attribute \src "libresoc.v:188953.3-188954.39" wire width 6 $0\req_l_r_req[5:0] - attribute \src "libresoc.v:189184.3-189192.6" - wire width 6 $0\req_l_s_req$next[5:0]$13099 - attribute \src "libresoc.v:189000.3-189001.39" + attribute \src "libresoc.v:189139.3-189147.6" + wire width 6 $0\req_l_s_req$next[5:0]$12693 + attribute \src "libresoc.v:188955.3-188956.39" wire width 6 $0\req_l_s_req[5:0] - attribute \src "libresoc.v:189121.3-189129.6" - wire $0\rok_l_r_rdok$next[0:0]$13078 - attribute \src "libresoc.v:189014.3-189015.41" + attribute \src "libresoc.v:189076.3-189084.6" + wire $0\rok_l_r_rdok$next[0:0]$12672 + attribute \src "libresoc.v:188969.3-188970.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:189112.3-189120.6" - wire $0\rok_l_s_rdok$next[0:0]$13075 - attribute \src "libresoc.v:189016.3-189017.41" + attribute \src "libresoc.v:189067.3-189075.6" + wire $0\rok_l_s_rdok$next[0:0]$12669 + attribute \src "libresoc.v:188971.3-188972.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:189139.3-189147.6" - wire $0\rst_l_r_rst$next[0:0]$13084 - attribute \src "libresoc.v:189010.3-189011.39" + attribute \src "libresoc.v:189094.3-189102.6" + wire $0\rst_l_r_rst$next[0:0]$12678 + attribute \src "libresoc.v:188965.3-188966.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:189130.3-189138.6" - wire $0\rst_l_s_rst$next[0:0]$13081 - attribute \src "libresoc.v:189012.3-189013.39" + attribute \src "libresoc.v:189085.3-189093.6" + wire $0\rst_l_s_rst$next[0:0]$12675 + attribute \src "libresoc.v:188967.3-188968.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:189175.3-189183.6" - wire width 6 $0\src_l_r_src$next[5:0]$13096 - attribute \src "libresoc.v:189002.3-189003.39" + attribute \src "libresoc.v:189130.3-189138.6" + wire width 6 $0\src_l_r_src$next[5:0]$12690 + attribute \src "libresoc.v:188957.3-188958.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:189166.3-189174.6" - wire width 6 $0\src_l_s_src$next[5:0]$13093 - attribute \src "libresoc.v:189004.3-189005.39" + attribute \src "libresoc.v:189121.3-189129.6" + wire width 6 $0\src_l_s_src$next[5:0]$12687 + attribute \src "libresoc.v:188959.3-188960.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:189347.3-189356.6" - wire width 64 $0\src_r0$next[63:0]$13162 - attribute \src "libresoc.v:188964.3-188965.29" + attribute \src "libresoc.v:189302.3-189311.6" + wire width 64 $0\src_r0$next[63:0]$12756 + attribute \src "libresoc.v:188919.3-188920.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:189357.3-189366.6" - wire width 64 $0\src_r1$next[63:0]$13165 - attribute \src "libresoc.v:188962.3-188963.29" + attribute \src "libresoc.v:189312.3-189321.6" + wire width 64 $0\src_r1$next[63:0]$12759 + attribute \src "libresoc.v:188917.3-188918.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:189367.3-189376.6" - wire width 64 $0\src_r2$next[63:0]$13168 - attribute \src "libresoc.v:188960.3-188961.29" + attribute \src "libresoc.v:189322.3-189331.6" + wire width 64 $0\src_r2$next[63:0]$12762 + attribute \src "libresoc.v:188915.3-188916.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:189377.3-189386.6" - wire $0\src_r3$next[0:0]$13171 - attribute \src "libresoc.v:188958.3-188959.29" + attribute \src "libresoc.v:189332.3-189341.6" + wire $0\src_r3$next[0:0]$12765 + attribute \src "libresoc.v:188913.3-188914.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:189387.3-189396.6" - wire width 2 $0\src_r4$next[1:0]$13174 - attribute \src "libresoc.v:188956.3-188957.29" + attribute \src "libresoc.v:189342.3-189351.6" + wire width 2 $0\src_r4$next[1:0]$12768 + attribute \src "libresoc.v:188911.3-188912.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:189397.3-189406.6" - wire width 2 $0\src_r5$next[1:0]$13177 - attribute \src "libresoc.v:188954.3-188955.29" + attribute \src "libresoc.v:189352.3-189361.6" + wire width 2 $0\src_r5$next[1:0]$12771 + attribute \src "libresoc.v:188909.3-188910.29" wire width 2 $0\src_r5[1:0] - attribute \src "libresoc.v:188409.7-188409.24" + attribute \src "libresoc.v:188364.7-188364.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:188419.7-188419.26" + attribute \src "libresoc.v:188374.7-188374.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:189416.3-189424.6" - wire $1\alu_l_r_alu$next[0:0]$13184 - attribute \src "libresoc.v:188427.7-188427.25" + attribute \src "libresoc.v:189371.3-189379.6" + wire $1\alu_l_r_alu$next[0:0]$12778 + attribute \src "libresoc.v:188382.7-188382.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:189202.3-189214.6" - wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 - attribute \src "libresoc.v:188472.14-188472.49" + attribute \src "libresoc.v:189157.3-189169.6" + wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12703 + attribute \src "libresoc.v:188427.14-188427.49" wire width 14 $1\alu_spr0_spr_op__fn_unit[13:0] - attribute \src "libresoc.v:189202.3-189214.6" - wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$13110 - attribute \src "libresoc.v:188476.14-188476.43" + attribute \src "libresoc.v:189157.3-189169.6" + wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12704 + attribute \src "libresoc.v:188431.14-188431.43" wire width 32 $1\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:189202.3-189214.6" - wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 - attribute \src "libresoc.v:188555.13-188555.47" + attribute \src "libresoc.v:189157.3-189169.6" + wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12705 + attribute \src "libresoc.v:188510.13-188510.47" wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:189202.3-189214.6" - wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 - attribute \src "libresoc.v:188559.7-188559.39" + attribute \src "libresoc.v:189157.3-189169.6" + wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12706 + attribute \src "libresoc.v:188514.7-188514.39" wire $1\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:189407.3-189415.6" - wire $1\alui_l_r_alui$next[0:0]$13181 - attribute \src "libresoc.v:188577.7-188577.27" + attribute \src "libresoc.v:189362.3-189370.6" + wire $1\alui_l_r_alui$next[0:0]$12775 + attribute \src "libresoc.v:188532.7-188532.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:189215.3-189236.6" - wire width 64 $1\data_r0__o$next[63:0]$13116 - attribute \src "libresoc.v:188609.14-188609.47" + attribute \src "libresoc.v:189170.3-189191.6" + wire width 64 $1\data_r0__o$next[63:0]$12710 + attribute \src "libresoc.v:188564.14-188564.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:189215.3-189236.6" - wire $1\data_r0__o_ok$next[0:0]$13117 - attribute \src "libresoc.v:188613.7-188613.27" + attribute \src "libresoc.v:189170.3-189191.6" + wire $1\data_r0__o_ok$next[0:0]$12711 + attribute \src "libresoc.v:188568.7-188568.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:189237.3-189258.6" - wire width 64 $1\data_r1__spr1$next[63:0]$13124 - attribute \src "libresoc.v:188617.14-188617.50" + attribute \src "libresoc.v:189192.3-189213.6" + wire width 64 $1\data_r1__spr1$next[63:0]$12718 + attribute \src "libresoc.v:188572.14-188572.50" wire width 64 $1\data_r1__spr1[63:0] - attribute \src "libresoc.v:189237.3-189258.6" - wire $1\data_r1__spr1_ok$next[0:0]$13125 - attribute \src "libresoc.v:188621.7-188621.30" + attribute \src "libresoc.v:189192.3-189213.6" + wire $1\data_r1__spr1_ok$next[0:0]$12719 + attribute \src "libresoc.v:188576.7-188576.30" wire $1\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:189259.3-189280.6" - wire width 64 $1\data_r2__fast1$next[63:0]$13132 - attribute \src "libresoc.v:188625.14-188625.51" + attribute \src "libresoc.v:189214.3-189235.6" + wire width 64 $1\data_r2__fast1$next[63:0]$12726 + attribute \src "libresoc.v:188580.14-188580.51" wire width 64 $1\data_r2__fast1[63:0] - attribute \src "libresoc.v:189259.3-189280.6" - wire $1\data_r2__fast1_ok$next[0:0]$13133 - attribute \src "libresoc.v:188629.7-188629.31" + attribute \src "libresoc.v:189214.3-189235.6" + wire $1\data_r2__fast1_ok$next[0:0]$12727 + attribute \src "libresoc.v:188584.7-188584.31" wire $1\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:189281.3-189302.6" - wire $1\data_r3__xer_so$next[0:0]$13140 - attribute \src "libresoc.v:188633.7-188633.29" + attribute \src "libresoc.v:189236.3-189257.6" + wire $1\data_r3__xer_so$next[0:0]$12734 + attribute \src "libresoc.v:188588.7-188588.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:189281.3-189302.6" - wire $1\data_r3__xer_so_ok$next[0:0]$13141 - attribute \src "libresoc.v:188637.7-188637.32" + attribute \src "libresoc.v:189236.3-189257.6" + wire $1\data_r3__xer_so_ok$next[0:0]$12735 + attribute \src "libresoc.v:188592.7-188592.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:189303.3-189324.6" - wire width 2 $1\data_r4__xer_ov$next[1:0]$13148 - attribute \src "libresoc.v:188641.13-188641.35" + attribute \src "libresoc.v:189258.3-189279.6" + wire width 2 $1\data_r4__xer_ov$next[1:0]$12742 + attribute \src "libresoc.v:188596.13-188596.35" wire width 2 $1\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:189303.3-189324.6" - wire $1\data_r4__xer_ov_ok$next[0:0]$13149 - attribute \src "libresoc.v:188645.7-188645.32" + attribute \src "libresoc.v:189258.3-189279.6" + wire $1\data_r4__xer_ov_ok$next[0:0]$12743 + attribute \src "libresoc.v:188600.7-188600.32" wire $1\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:189325.3-189346.6" - wire width 2 $1\data_r5__xer_ca$next[1:0]$13156 - attribute \src "libresoc.v:188649.13-188649.35" + attribute \src "libresoc.v:189280.3-189301.6" + wire width 2 $1\data_r5__xer_ca$next[1:0]$12750 + attribute \src "libresoc.v:188604.13-188604.35" wire width 2 $1\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:189325.3-189346.6" - wire $1\data_r5__xer_ca_ok$next[0:0]$13157 - attribute \src "libresoc.v:188653.7-188653.32" + attribute \src "libresoc.v:189280.3-189301.6" + wire $1\data_r5__xer_ca_ok$next[0:0]$12751 + attribute \src "libresoc.v:188608.7-188608.32" wire $1\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:189425.3-189434.6" + attribute \src "libresoc.v:189380.3-189389.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:189435.3-189444.6" + attribute \src "libresoc.v:189390.3-189399.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:189445.3-189454.6" + attribute \src "libresoc.v:189400.3-189409.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:189455.3-189464.6" + attribute \src "libresoc.v:189410.3-189419.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:189465.3-189474.6" + attribute \src "libresoc.v:189420.3-189429.6" wire width 2 $1\dest5_o[1:0] - attribute \src "libresoc.v:189475.3-189484.6" + attribute \src "libresoc.v:189430.3-189439.6" wire width 2 $1\dest6_o[1:0] - attribute \src "libresoc.v:189157.3-189165.6" - wire $1\opc_l_r_opc$next[0:0]$13091 - attribute \src "libresoc.v:188681.7-188681.25" + attribute \src "libresoc.v:189112.3-189120.6" + wire $1\opc_l_r_opc$next[0:0]$12685 + attribute \src "libresoc.v:188636.7-188636.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:189148.3-189156.6" - wire $1\opc_l_s_opc$next[0:0]$13088 - attribute \src "libresoc.v:188685.7-188685.25" + attribute \src "libresoc.v:189103.3-189111.6" + wire $1\opc_l_s_opc$next[0:0]$12682 + attribute \src "libresoc.v:188640.7-188640.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:189485.3-189493.6" - wire width 6 $1\prev_wr_go$next[5:0]$13193 - attribute \src "libresoc.v:188787.13-188787.31" + attribute \src "libresoc.v:189440.3-189448.6" + wire width 6 $1\prev_wr_go$next[5:0]$12787 + attribute \src "libresoc.v:188742.13-188742.31" wire width 6 $1\prev_wr_go[5:0] - attribute \src "libresoc.v:189102.3-189111.6" + attribute \src "libresoc.v:189057.3-189066.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:189193.3-189201.6" - wire width 6 $1\req_l_r_req$next[5:0]$13103 - attribute \src "libresoc.v:188795.13-188795.32" + attribute \src "libresoc.v:189148.3-189156.6" + wire width 6 $1\req_l_r_req$next[5:0]$12697 + attribute \src "libresoc.v:188750.13-188750.32" wire width 6 $1\req_l_r_req[5:0] - attribute \src "libresoc.v:189184.3-189192.6" - wire width 6 $1\req_l_s_req$next[5:0]$13100 - attribute \src "libresoc.v:188799.13-188799.32" + attribute \src "libresoc.v:189139.3-189147.6" + wire width 6 $1\req_l_s_req$next[5:0]$12694 + attribute \src "libresoc.v:188754.13-188754.32" wire width 6 $1\req_l_s_req[5:0] - attribute \src "libresoc.v:189121.3-189129.6" - wire $1\rok_l_r_rdok$next[0:0]$13079 - attribute \src "libresoc.v:188811.7-188811.26" + attribute \src "libresoc.v:189076.3-189084.6" + wire $1\rok_l_r_rdok$next[0:0]$12673 + attribute \src "libresoc.v:188766.7-188766.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:189112.3-189120.6" - wire $1\rok_l_s_rdok$next[0:0]$13076 - attribute \src "libresoc.v:188815.7-188815.26" + attribute \src "libresoc.v:189067.3-189075.6" + wire $1\rok_l_s_rdok$next[0:0]$12670 + attribute \src "libresoc.v:188770.7-188770.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:189139.3-189147.6" - wire $1\rst_l_r_rst$next[0:0]$13085 - attribute \src "libresoc.v:188819.7-188819.25" + attribute \src "libresoc.v:189094.3-189102.6" + wire $1\rst_l_r_rst$next[0:0]$12679 + attribute \src "libresoc.v:188774.7-188774.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:189130.3-189138.6" - wire $1\rst_l_s_rst$next[0:0]$13082 - attribute \src "libresoc.v:188823.7-188823.25" + attribute \src "libresoc.v:189085.3-189093.6" + wire $1\rst_l_s_rst$next[0:0]$12676 + attribute \src "libresoc.v:188778.7-188778.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:189175.3-189183.6" - wire width 6 $1\src_l_r_src$next[5:0]$13097 - attribute \src "libresoc.v:188845.13-188845.32" + attribute \src "libresoc.v:189130.3-189138.6" + wire width 6 $1\src_l_r_src$next[5:0]$12691 + attribute \src "libresoc.v:188800.13-188800.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:189166.3-189174.6" - wire width 6 $1\src_l_s_src$next[5:0]$13094 - attribute \src "libresoc.v:188849.13-188849.32" + attribute \src "libresoc.v:189121.3-189129.6" + wire width 6 $1\src_l_s_src$next[5:0]$12688 + attribute \src "libresoc.v:188804.13-188804.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:189347.3-189356.6" - wire width 64 $1\src_r0$next[63:0]$13163 - attribute \src "libresoc.v:188853.14-188853.43" + attribute \src "libresoc.v:189302.3-189311.6" + wire width 64 $1\src_r0$next[63:0]$12757 + attribute \src "libresoc.v:188808.14-188808.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:189357.3-189366.6" - wire width 64 $1\src_r1$next[63:0]$13166 - attribute \src "libresoc.v:188857.14-188857.43" + attribute \src "libresoc.v:189312.3-189321.6" + wire width 64 $1\src_r1$next[63:0]$12760 + attribute \src "libresoc.v:188812.14-188812.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:189367.3-189376.6" - wire width 64 $1\src_r2$next[63:0]$13169 - attribute \src "libresoc.v:188861.14-188861.43" + attribute \src "libresoc.v:189322.3-189331.6" + wire width 64 $1\src_r2$next[63:0]$12763 + attribute \src "libresoc.v:188816.14-188816.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:189377.3-189386.6" - wire $1\src_r3$next[0:0]$13172 - attribute \src "libresoc.v:188865.7-188865.20" + attribute \src "libresoc.v:189332.3-189341.6" + wire $1\src_r3$next[0:0]$12766 + attribute \src "libresoc.v:188820.7-188820.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:189387.3-189396.6" - wire width 2 $1\src_r4$next[1:0]$13175 - attribute \src "libresoc.v:188869.13-188869.26" + attribute \src "libresoc.v:189342.3-189351.6" + wire width 2 $1\src_r4$next[1:0]$12769 + attribute \src "libresoc.v:188824.13-188824.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:189397.3-189406.6" - wire width 2 $1\src_r5$next[1:0]$13178 - attribute \src "libresoc.v:188873.13-188873.26" + attribute \src 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"libresoc.v:188895.18-188895.121" + wire $and$libresoc.v:188895$12620_Y + attribute \src "libresoc.v:188896.18-188896.121" + wire $and$libresoc.v:188896$12621_Y + attribute \src "libresoc.v:188897.18-188897.121" + wire $and$libresoc.v:188897$12622_Y + attribute \src "libresoc.v:188904.18-188904.134" + wire $and$libresoc.v:188904$12629_Y + attribute \src "libresoc.v:188878.18-188878.113" + wire $eq$libresoc.v:188878$12603_Y + attribute \src "libresoc.v:188880.18-188880.119" + wire $eq$libresoc.v:188880$12605_Y + attribute \src "libresoc.v:188839.17-188839.113" + wire width 6 $not$libresoc.v:188839$12564_Y + attribute \src "libresoc.v:188843.19-188843.115" + wire width 6 $not$libresoc.v:188843$12568_Y + attribute \src "libresoc.v:188862.18-188862.97" + wire $not$libresoc.v:188862$12587_Y + attribute \src "libresoc.v:188864.18-188864.99" + wire $not$libresoc.v:188864$12589_Y + attribute \src "libresoc.v:188867.18-188867.113" + wire width 6 $not$libresoc.v:188867$12592_Y + attribute \src "libresoc.v:188870.18-188870.106" + wire $not$libresoc.v:188870$12595_Y + attribute \src "libresoc.v:188875.18-188875.120" + wire $not$libresoc.v:188875$12600_Y + attribute \src "libresoc.v:188850.18-188850.118" + wire width 6 $or$libresoc.v:188850$12575_Y + attribute \src "libresoc.v:188874.18-188874.112" + wire $or$libresoc.v:188874$12599_Y + attribute \src "libresoc.v:188884.18-188884.122" + wire $or$libresoc.v:188884$12609_Y + attribute \src "libresoc.v:188885.18-188885.124" + wire $or$libresoc.v:188885$12610_Y + attribute \src "libresoc.v:188886.18-188886.194" + wire width 6 $or$libresoc.v:188886$12611_Y + attribute \src "libresoc.v:188887.18-188887.194" + wire width 6 $or$libresoc.v:188887$12612_Y + attribute \src "libresoc.v:188891.18-188891.120" + wire width 6 $or$libresoc.v:188891$12616_Y + attribute \src "libresoc.v:188856.17-188856.105" + wire $reduce_and$libresoc.v:188856$12581_Y + attribute \src "libresoc.v:188869.18-188869.106" + wire $reduce_or$libresoc.v:188869$12594_Y + attribute \src "libresoc.v:188872.18-188872.113" + wire $reduce_or$libresoc.v:188872$12597_Y + attribute \src "libresoc.v:188873.18-188873.112" + wire $reduce_or$libresoc.v:188873$12598_Y + attribute \src "libresoc.v:188898.18-188898.118" + wire width 64 $ternary$libresoc.v:188898$12623_Y + attribute \src "libresoc.v:188899.18-188899.118" + wire width 64 $ternary$libresoc.v:188899$12624_Y + attribute \src "libresoc.v:188900.18-188900.118" + wire width 64 $ternary$libresoc.v:188900$12625_Y + attribute \src "libresoc.v:188901.18-188901.118" + wire $ternary$libresoc.v:188901$12626_Y + attribute \src "libresoc.v:188902.18-188902.118" + wire width 2 $ternary$libresoc.v:188902$12627_Y + attribute \src "libresoc.v:188903.18-188903.118" + wire width 2 $ternary$libresoc.v:188903$12628_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -393189,7 +357162,7 @@ module \spr0 wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 6 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_spr0_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_spr0_fast1$2 @@ -393197,7 +357170,7 @@ module \spr0 wire \alu_spr0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_spr0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_spr0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_spr0_p_ready_o @@ -393205,7 +357178,7 @@ module \spr0 wire \alu_spr0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_spr0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_spr0_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_spr0_spr1$1 @@ -393315,15 +357288,15 @@ module \spr0 wire \alu_spr0_spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_spr0_spr_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \alu_spr0_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \alu_spr0_xer_ca$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \alu_spr0_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \alu_spr0_xer_ov$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \alu_spr0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_spr0_xer_so$3 @@ -393335,9 +357308,9 @@ module \spr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 7 \cu_busy_o @@ -393421,11 +357394,11 @@ module \spr0 wire width 2 output 24 \dest5_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 22 \dest6_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \fast1_ok - attribute \src "libresoc.v:188273.7-188273.15" + attribute \src "libresoc.v:188228.7-188228.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 17 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc @@ -393577,7 +357550,7 @@ module \spr0 wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 11 \src1_i @@ -393627,14 +357600,14 @@ module \spr0 wire width 2 \src_r5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 21 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:188885$12971 + cell $and $and$libresoc.v:188840$12565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393642,10 +357615,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:188885$12971_Y + connect \Y $and$libresoc.v:188840$12565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:188886$12972 + cell $and $and$libresoc.v:188841$12566 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393653,10 +357626,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:188886$12972_Y + connect \Y $and$libresoc.v:188841$12566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:188887$12973 + cell $and $and$libresoc.v:188842$12567 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393664,10 +357637,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$102 connect \B 6'111111 - connect \Y $and$libresoc.v:188887$12973_Y + connect \Y $and$libresoc.v:188842$12567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:188889$12975 + cell $and $and$libresoc.v:188844$12569 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393675,10 +357648,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:188889$12975_Y + connect \Y $and$libresoc.v:188844$12569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188890$12976 + cell $and $and$libresoc.v:188845$12570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393686,10 +357659,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188890$12976_Y + connect \Y $and$libresoc.v:188845$12570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188891$12977 + cell $and $and$libresoc.v:188846$12571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393697,10 +357670,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188891$12977_Y + connect \Y $and$libresoc.v:188846$12571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188892$12978 + cell $and $and$libresoc.v:188847$12572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393708,10 +357681,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188892$12978_Y + connect \Y $and$libresoc.v:188847$12572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188893$12979 + cell $and $and$libresoc.v:188848$12573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393719,10 +357692,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188893$12979_Y + connect \Y $and$libresoc.v:188848$12573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188894$12980 + cell $and $and$libresoc.v:188849$12574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393730,10 +357703,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188894$12980_Y + connect \Y $and$libresoc.v:188849$12574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188896$12982 + cell $and $and$libresoc.v:188851$12576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393741,10 +357714,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188896$12982_Y + connect \Y $and$libresoc.v:188851$12576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:188897$12983 + cell $and $and$libresoc.v:188852$12577 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393752,10 +357725,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 \$118 \$120 } - connect \Y $and$libresoc.v:188897$12983_Y + connect \Y $and$libresoc.v:188852$12577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:188898$12984 + cell $and $and$libresoc.v:188853$12578 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393763,10 +357736,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$122 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:188898$12984_Y + connect \Y $and$libresoc.v:188853$12578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188899$12985 + cell $and $and$libresoc.v:188854$12579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393774,10 +357747,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188899$12985_Y + connect \Y $and$libresoc.v:188854$12579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188900$12986 + cell $and $and$libresoc.v:188855$12580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393785,10 +357758,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188900$12986_Y + connect \Y $and$libresoc.v:188855$12580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188902$12988 + cell $and $and$libresoc.v:188857$12582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393796,10 +357769,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188902$12988_Y + connect \Y $and$libresoc.v:188857$12582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188903$12989 + cell $and $and$libresoc.v:188858$12583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393807,10 +357780,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188903$12989_Y + connect \Y $and$libresoc.v:188858$12583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188904$12990 + cell $and $and$libresoc.v:188859$12584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393818,10 +357791,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188904$12990_Y + connect \Y $and$libresoc.v:188859$12584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188905$12991 + cell $and $and$libresoc.v:188860$12585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393829,10 +357802,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [5] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188905$12991_Y + connect \Y $and$libresoc.v:188860$12585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:188906$12992 + cell $and $and$libresoc.v:188861$12586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393840,10 +357813,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$6 connect \B \$8 - connect \Y $and$libresoc.v:188906$12992_Y + connect \Y $and$libresoc.v:188861$12586_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:188908$12994 + cell $and $and$libresoc.v:188863$12588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393851,10 +357824,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$16 - connect \Y $and$libresoc.v:188908$12994_Y + connect \Y $and$libresoc.v:188863$12588_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:188910$12996 + cell $and $and$libresoc.v:188865$12590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393862,10 +357835,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$20 - connect \Y $and$libresoc.v:188910$12996_Y + connect \Y $and$libresoc.v:188865$12590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:188911$12997 + cell $and $and$libresoc.v:188866$12591 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393873,10 +357846,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:188911$12997_Y + connect \Y $and$libresoc.v:188866$12591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:188913$12999 + cell $and $and$libresoc.v:188868$12593 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393884,10 +357857,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__rel_o connect \B \$28 - connect \Y $and$libresoc.v:188913$12999_Y + connect \Y $and$libresoc.v:188868$12593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:188916$13002 + cell $and $and$libresoc.v:188871$12596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393895,10 +357868,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$26 - connect \Y $and$libresoc.v:188916$13002_Y + connect \Y $and$libresoc.v:188871$12596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:188921$13007 + cell $and $and$libresoc.v:188876$12601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393906,10 +357879,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$42 - connect \Y $and$libresoc.v:188921$13007_Y + connect \Y $and$libresoc.v:188876$12601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:188922$13008 + cell $and $and$libresoc.v:188877$12602 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393917,10 +357890,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:188922$13008_Y + connect \Y $and$libresoc.v:188877$12602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:188924$13010 + cell $and $and$libresoc.v:188879$12604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393928,10 +357901,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$48 - connect \Y $and$libresoc.v:188924$13010_Y + connect \Y $and$libresoc.v:188879$12604_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:188926$13012 + cell $and $and$libresoc.v:188881$12606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393939,10 +357912,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \alu_spr0_n_ready_i - connect \Y $and$libresoc.v:188926$13012_Y + connect \Y $and$libresoc.v:188881$12606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:188927$13013 + cell $and $and$libresoc.v:188882$12607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393950,10 +357923,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$54 connect \B \alu_spr0_n_valid_o - connect \Y $and$libresoc.v:188927$13013_Y + connect \Y $and$libresoc.v:188882$12607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:188928$13014 + cell $and $and$libresoc.v:188883$12608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393961,10 +357934,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$56 connect \B \cu_busy_o - connect \Y $and$libresoc.v:188928$13014_Y + connect \Y $and$libresoc.v:188883$12608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:188933$13019 + cell $and $and$libresoc.v:188888$12613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393972,10 +357945,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:188933$13019_Y + connect \Y $and$libresoc.v:188888$12613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:188934$13020 + cell $and $and$libresoc.v:188889$12614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393983,10 +357956,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:188934$13020_Y + connect \Y $and$libresoc.v:188889$12614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:188935$13021 + cell $and $and$libresoc.v:188890$12615 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393994,10 +357967,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:188935$13021_Y + connect \Y $and$libresoc.v:188890$12615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188937$13023 + cell $and $and$libresoc.v:188892$12617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394005,10 +357978,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188937$13023_Y + connect \Y $and$libresoc.v:188892$12617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188938$13024 + cell $and $and$libresoc.v:188893$12618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394016,10 +357989,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \spr1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188938$13024_Y + connect \Y $and$libresoc.v:188893$12618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188939$13025 + cell $and $and$libresoc.v:188894$12619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394027,10 +358000,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188939$13025_Y + connect \Y $and$libresoc.v:188894$12619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188940$13026 + cell $and $and$libresoc.v:188895$12620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394038,10 +358011,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188940$13026_Y + connect \Y $and$libresoc.v:188895$12620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188941$13027 + cell $and $and$libresoc.v:188896$12621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394049,10 +358022,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188941$13027_Y + connect \Y $and$libresoc.v:188896$12621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188942$13028 + cell $and $and$libresoc.v:188897$12622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394060,10 +358033,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188942$13028_Y + connect \Y $and$libresoc.v:188897$12622_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:188949$13035 + cell $and $and$libresoc.v:188904$12629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394071,10 +358044,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:188949$13035_Y + connect \Y $and$libresoc.v:188904$12629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:188923$13009 + cell $eq $eq$libresoc.v:188878$12603 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394082,10 +358055,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$46 connect \B 1'0 - connect \Y $eq$libresoc.v:188923$13009_Y + connect \Y $eq$libresoc.v:188878$12603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:188925$13011 + cell $eq $eq$libresoc.v:188880$12605 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394093,66 +358066,66 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:188925$13011_Y + connect \Y $eq$libresoc.v:188880$12605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:188884$12970 + cell $not $not$libresoc.v:188839$12564 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:188884$12970_Y + connect \Y $not$libresoc.v:188839$12564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:188888$12974 + cell $not $not$libresoc.v:188843$12568 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:188888$12974_Y + connect \Y $not$libresoc.v:188843$12568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:188907$12993 + cell $not $not$libresoc.v:188862$12587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:188907$12993_Y + connect \Y $not$libresoc.v:188862$12587_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:188909$12995 + cell $not $not$libresoc.v:188864$12589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:188909$12995_Y + connect \Y $not$libresoc.v:188864$12589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:188912$12998 + cell $not $not$libresoc.v:188867$12592 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:188912$12998_Y + connect \Y $not$libresoc.v:188867$12592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:188915$13001 + cell $not $not$libresoc.v:188870$12595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $not$libresoc.v:188915$13001_Y + connect \Y $not$libresoc.v:188870$12595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:188920$13006 + cell $not $not$libresoc.v:188875$12600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_ready_i - connect \Y $not$libresoc.v:188920$13006_Y + connect \Y $not$libresoc.v:188875$12600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:188895$12981 + cell $or $or$libresoc.v:188850$12575 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394160,10 +358133,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$9 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:188895$12981_Y + connect \Y $or$libresoc.v:188850$12575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:188919$13005 + cell $or $or$libresoc.v:188874$12599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394171,10 +358144,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:188919$13005_Y + connect \Y $or$libresoc.v:188874$12599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:188929$13015 + cell $or $or$libresoc.v:188884$12609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394182,10 +358155,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:188929$13015_Y + connect \Y $or$libresoc.v:188884$12609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:188930$13016 + cell $or $or$libresoc.v:188885$12610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394193,10 +358166,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:188930$13016_Y + connect \Y $or$libresoc.v:188885$12610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:188931$13017 + cell $or $or$libresoc.v:188886$12611 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394204,10 +358177,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:188931$13017_Y + connect \Y $or$libresoc.v:188886$12611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:188932$13018 + cell $or $or$libresoc.v:188887$12612 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394215,10 +358188,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:188932$13018_Y + connect \Y $or$libresoc.v:188887$12612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:188936$13022 + cell $or $or$libresoc.v:188891$12616 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394226,90 +358199,90 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:188936$13022_Y + connect \Y $or$libresoc.v:188891$12616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:188901$12987 + cell $reduce_and $reduce_and$libresoc.v:188856$12581 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$11 - connect \Y $reduce_and$libresoc.v:188901$12987_Y + connect \Y $reduce_and$libresoc.v:188856$12581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:188914$13000 + cell $reduce_or $reduce_or$libresoc.v:188869$12594 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$30 - connect \Y $reduce_or$libresoc.v:188914$13000_Y + connect \Y $reduce_or$libresoc.v:188869$12594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:188917$13003 + cell $reduce_or $reduce_or$libresoc.v:188872$12597 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:188917$13003_Y + connect \Y $reduce_or$libresoc.v:188872$12597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:188918$13004 + cell $reduce_or $reduce_or$libresoc.v:188873$12598 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:188918$13004_Y + connect \Y $reduce_or$libresoc.v:188873$12598_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188943$13029 + cell $mux $ternary$libresoc.v:188898$12623 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:188943$13029_Y + connect \Y $ternary$libresoc.v:188898$12623_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188944$13030 + cell $mux $ternary$libresoc.v:188899$12624 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:188944$13030_Y + connect \Y $ternary$libresoc.v:188899$12624_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188945$13031 + cell $mux $ternary$libresoc.v:188900$12625 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:188945$13031_Y + connect \Y $ternary$libresoc.v:188900$12625_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188946$13032 + cell $mux $ternary$libresoc.v:188901$12626 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:188946$13032_Y + connect \Y $ternary$libresoc.v:188901$12626_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188947$13033 + cell $mux $ternary$libresoc.v:188902$12627 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:188947$13033_Y + connect \Y $ternary$libresoc.v:188902$12627_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188948$13034 + cell $mux $ternary$libresoc.v:188903$12628 parameter \WIDTH 2 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:188948$13034_Y + connect \Y $ternary$libresoc.v:188903$12628_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:189024.14-189030.4" + attribute \src "libresoc.v:188979.14-188985.4" cell \alu_l$73 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394318,7 +358291,7 @@ module \spr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:189031.12-189060.4" + attribute \src "libresoc.v:188986.12-189015.4" cell \alu_spr0 \alu_spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394350,7 +358323,7 @@ module \spr0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:189061.15-189067.4" + attribute \src "libresoc.v:189016.15-189022.4" cell \alui_l$72 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394359,7 +358332,7 @@ module \spr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:189068.14-189074.4" + attribute \src "libresoc.v:189023.14-189029.4" cell \opc_l$68 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394368,7 +358341,7 @@ module \spr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:189075.14-189081.4" + attribute \src "libresoc.v:189030.14-189036.4" cell \req_l$69 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394377,7 +358350,7 @@ module \spr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:189082.14-189088.4" + attribute \src "libresoc.v:189037.14-189043.4" cell \rok_l$71 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394386,7 +358359,7 @@ module \spr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:189089.14-189094.4" + attribute \src "libresoc.v:189044.14-189049.4" cell \rst_l$70 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394394,7 +358367,7 @@ module \spr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:189095.14-189101.4" + attribute \src "libresoc.v:189050.14-189056.4" cell \src_l$67 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394402,577 +358375,577 @@ module \spr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:188273.7-188273.20" - process $proc$libresoc.v:188273$13194 + attribute \src "libresoc.v:188228.7-188228.20" + process $proc$libresoc.v:188228$12788 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188409.7-188409.24" - process $proc$libresoc.v:188409$13195 + attribute \src "libresoc.v:188364.7-188364.24" + process $proc$libresoc.v:188364$12789 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:188419.7-188419.26" - process $proc$libresoc.v:188419$13196 + attribute \src "libresoc.v:188374.7-188374.26" + process $proc$libresoc.v:188374$12790 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:188427.7-188427.25" - process $proc$libresoc.v:188427$13197 + attribute \src "libresoc.v:188382.7-188382.25" + process $proc$libresoc.v:188382$12791 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:188472.14-188472.49" - process $proc$libresoc.v:188472$13198 + attribute \src "libresoc.v:188427.14-188427.49" + process $proc$libresoc.v:188427$12792 assign { } { } assign $1\alu_spr0_spr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:188476.14-188476.43" - process $proc$libresoc.v:188476$13199 + attribute \src "libresoc.v:188431.14-188431.43" + process $proc$libresoc.v:188431$12793 assign { } { } assign $1\alu_spr0_spr_op__insn[31:0] 0 sync always sync init update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:188555.13-188555.47" - process $proc$libresoc.v:188555$13200 + attribute \src "libresoc.v:188510.13-188510.47" + process $proc$libresoc.v:188510$12794 assign { } { } assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:188559.7-188559.39" - process $proc$libresoc.v:188559$13201 + attribute \src "libresoc.v:188514.7-188514.39" + process $proc$libresoc.v:188514$12795 assign { } { } assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:188577.7-188577.27" - process $proc$libresoc.v:188577$13202 + attribute \src "libresoc.v:188532.7-188532.27" + process $proc$libresoc.v:188532$12796 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:188609.14-188609.47" - process $proc$libresoc.v:188609$13203 + attribute \src "libresoc.v:188564.14-188564.47" + process $proc$libresoc.v:188564$12797 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:188613.7-188613.27" - process $proc$libresoc.v:188613$13204 + attribute \src "libresoc.v:188568.7-188568.27" + process $proc$libresoc.v:188568$12798 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:188617.14-188617.50" - process $proc$libresoc.v:188617$13205 + attribute \src "libresoc.v:188572.14-188572.50" + process $proc$libresoc.v:188572$12799 assign { } { } assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__spr1 $1\data_r1__spr1[63:0] end - attribute \src "libresoc.v:188621.7-188621.30" - process $proc$libresoc.v:188621$13206 + attribute \src "libresoc.v:188576.7-188576.30" + process $proc$libresoc.v:188576$12800 assign { } { } assign $1\data_r1__spr1_ok[0:0] 1'0 sync always sync init update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:188625.14-188625.51" - process $proc$libresoc.v:188625$13207 + attribute \src "libresoc.v:188580.14-188580.51" + process $proc$libresoc.v:188580$12801 assign { } { } assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast1 $1\data_r2__fast1[63:0] end - attribute \src "libresoc.v:188629.7-188629.31" - process $proc$libresoc.v:188629$13208 + attribute \src "libresoc.v:188584.7-188584.31" + process $proc$libresoc.v:188584$12802 assign { } { } assign $1\data_r2__fast1_ok[0:0] 1'0 sync always sync init update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:188633.7-188633.29" - process $proc$libresoc.v:188633$13209 + attribute \src "libresoc.v:188588.7-188588.29" + process $proc$libresoc.v:188588$12803 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:188637.7-188637.32" - process $proc$libresoc.v:188637$13210 + attribute \src "libresoc.v:188592.7-188592.32" + process $proc$libresoc.v:188592$12804 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:188641.13-188641.35" - process $proc$libresoc.v:188641$13211 + attribute \src "libresoc.v:188596.13-188596.35" + process $proc$libresoc.v:188596$12805 assign { } { } assign $1\data_r4__xer_ov[1:0] 2'00 sync always sync init update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:188645.7-188645.32" - process $proc$libresoc.v:188645$13212 + attribute \src "libresoc.v:188600.7-188600.32" + process $proc$libresoc.v:188600$12806 assign { } { } assign $1\data_r4__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:188649.13-188649.35" - process $proc$libresoc.v:188649$13213 + attribute \src "libresoc.v:188604.13-188604.35" + process $proc$libresoc.v:188604$12807 assign { } { } assign $1\data_r5__xer_ca[1:0] 2'00 sync always sync init update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:188653.7-188653.32" - process $proc$libresoc.v:188653$13214 + attribute \src "libresoc.v:188608.7-188608.32" + process $proc$libresoc.v:188608$12808 assign { } { } assign $1\data_r5__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:188681.7-188681.25" - process $proc$libresoc.v:188681$13215 + attribute \src "libresoc.v:188636.7-188636.25" + process $proc$libresoc.v:188636$12809 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:188685.7-188685.25" - process $proc$libresoc.v:188685$13216 + attribute \src "libresoc.v:188640.7-188640.25" + process $proc$libresoc.v:188640$12810 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:188787.13-188787.31" - process $proc$libresoc.v:188787$13217 + attribute \src "libresoc.v:188742.13-188742.31" + process $proc$libresoc.v:188742$12811 assign { } { } assign $1\prev_wr_go[5:0] 6'000000 sync always sync init update \prev_wr_go $1\prev_wr_go[5:0] end - attribute \src "libresoc.v:188795.13-188795.32" - process $proc$libresoc.v:188795$13218 + attribute \src "libresoc.v:188750.13-188750.32" + process $proc$libresoc.v:188750$12812 assign { } { } assign $1\req_l_r_req[5:0] 6'111111 sync always sync init update \req_l_r_req $1\req_l_r_req[5:0] end - attribute \src "libresoc.v:188799.13-188799.32" - process $proc$libresoc.v:188799$13219 + attribute \src "libresoc.v:188754.13-188754.32" + process $proc$libresoc.v:188754$12813 assign { } { } assign $1\req_l_s_req[5:0] 6'000000 sync always sync init update \req_l_s_req $1\req_l_s_req[5:0] end - attribute \src "libresoc.v:188811.7-188811.26" - process $proc$libresoc.v:188811$13220 + attribute \src "libresoc.v:188766.7-188766.26" + process $proc$libresoc.v:188766$12814 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:188815.7-188815.26" - process $proc$libresoc.v:188815$13221 + attribute \src "libresoc.v:188770.7-188770.26" + process $proc$libresoc.v:188770$12815 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:188819.7-188819.25" - process $proc$libresoc.v:188819$13222 + attribute \src "libresoc.v:188774.7-188774.25" + process $proc$libresoc.v:188774$12816 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:188823.7-188823.25" - process $proc$libresoc.v:188823$13223 + attribute \src "libresoc.v:188778.7-188778.25" + process $proc$libresoc.v:188778$12817 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:188845.13-188845.32" - process $proc$libresoc.v:188845$13224 + attribute \src "libresoc.v:188800.13-188800.32" + process $proc$libresoc.v:188800$12818 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:188849.13-188849.32" - process $proc$libresoc.v:188849$13225 + attribute \src "libresoc.v:188804.13-188804.32" + process $proc$libresoc.v:188804$12819 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:188853.14-188853.43" - process $proc$libresoc.v:188853$13226 + attribute \src "libresoc.v:188808.14-188808.43" + process $proc$libresoc.v:188808$12820 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:188857.14-188857.43" - process $proc$libresoc.v:188857$13227 + attribute \src "libresoc.v:188812.14-188812.43" + process $proc$libresoc.v:188812$12821 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:188861.14-188861.43" - process $proc$libresoc.v:188861$13228 + attribute \src "libresoc.v:188816.14-188816.43" + process $proc$libresoc.v:188816$12822 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:188865.7-188865.20" - process $proc$libresoc.v:188865$13229 + attribute \src "libresoc.v:188820.7-188820.20" + process $proc$libresoc.v:188820$12823 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:188869.13-188869.26" - process $proc$libresoc.v:188869$13230 + attribute \src "libresoc.v:188824.13-188824.26" + process $proc$libresoc.v:188824$12824 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:188873.13-188873.26" - process $proc$libresoc.v:188873$13231 + attribute \src "libresoc.v:188828.13-188828.26" + process $proc$libresoc.v:188828$12825 assign { } { } assign $1\src_r5[1:0] 2'00 sync always sync init update \src_r5 $1\src_r5[1:0] end - attribute \src "libresoc.v:188950.3-188951.39" - process $proc$libresoc.v:188950$13036 + attribute \src "libresoc.v:188905.3-188906.39" + process $proc$libresoc.v:188905$12630 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:188952.3-188953.43" - process $proc$libresoc.v:188952$13037 + attribute \src "libresoc.v:188907.3-188908.43" + process $proc$libresoc.v:188907$12631 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:188954.3-188955.29" - process $proc$libresoc.v:188954$13038 + attribute \src "libresoc.v:188909.3-188910.29" + process $proc$libresoc.v:188909$12632 assign { } { } assign $0\src_r5[1:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[1:0] end - attribute \src "libresoc.v:188956.3-188957.29" - process $proc$libresoc.v:188956$13039 + attribute \src "libresoc.v:188911.3-188912.29" + process $proc$libresoc.v:188911$12633 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:188958.3-188959.29" - process $proc$libresoc.v:188958$13040 + attribute \src "libresoc.v:188913.3-188914.29" + process $proc$libresoc.v:188913$12634 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:188960.3-188961.29" - process $proc$libresoc.v:188960$13041 + attribute \src "libresoc.v:188915.3-188916.29" + process $proc$libresoc.v:188915$12635 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:188962.3-188963.29" - process $proc$libresoc.v:188962$13042 + attribute \src "libresoc.v:188917.3-188918.29" + process $proc$libresoc.v:188917$12636 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:188964.3-188965.29" - process $proc$libresoc.v:188964$13043 + attribute \src "libresoc.v:188919.3-188920.29" + process $proc$libresoc.v:188919$12637 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:188966.3-188967.47" - process $proc$libresoc.v:188966$13044 + attribute \src "libresoc.v:188921.3-188922.47" + process $proc$libresoc.v:188921$12638 assign { } { } assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next sync posedge \coresync_clk update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:188968.3-188969.53" - process $proc$libresoc.v:188968$13045 + attribute \src "libresoc.v:188923.3-188924.53" + process $proc$libresoc.v:188923$12639 assign { } { } assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next sync posedge \coresync_clk update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:188970.3-188971.47" - process $proc$libresoc.v:188970$13046 + attribute \src "libresoc.v:188925.3-188926.47" + process $proc$libresoc.v:188925$12640 assign { } { } assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next sync posedge \coresync_clk update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:188972.3-188973.53" - process $proc$libresoc.v:188972$13047 + attribute \src "libresoc.v:188927.3-188928.53" + process $proc$libresoc.v:188927$12641 assign { } { } assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next sync posedge \coresync_clk update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:188974.3-188975.47" - process $proc$libresoc.v:188974$13048 + attribute \src "libresoc.v:188929.3-188930.47" + process $proc$libresoc.v:188929$12642 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:188976.3-188977.53" - process $proc$libresoc.v:188976$13049 + attribute \src "libresoc.v:188931.3-188932.53" + process $proc$libresoc.v:188931$12643 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:188978.3-188979.45" - process $proc$libresoc.v:188978$13050 + attribute \src "libresoc.v:188933.3-188934.45" + process $proc$libresoc.v:188933$12644 assign { } { } assign $0\data_r2__fast1[63:0] \data_r2__fast1$next sync posedge \coresync_clk update \data_r2__fast1 $0\data_r2__fast1[63:0] end - attribute \src "libresoc.v:188980.3-188981.51" - process $proc$libresoc.v:188980$13051 + attribute \src "libresoc.v:188935.3-188936.51" + process $proc$libresoc.v:188935$12645 assign { } { } assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next sync posedge \coresync_clk update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:188982.3-188983.43" - process $proc$libresoc.v:188982$13052 + attribute \src "libresoc.v:188937.3-188938.43" + process $proc$libresoc.v:188937$12646 assign { } { } assign $0\data_r1__spr1[63:0] \data_r1__spr1$next sync posedge \coresync_clk update \data_r1__spr1 $0\data_r1__spr1[63:0] end - attribute \src "libresoc.v:188984.3-188985.49" - process $proc$libresoc.v:188984$13053 + attribute \src "libresoc.v:188939.3-188940.49" + process $proc$libresoc.v:188939$12647 assign { } { } assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next sync posedge \coresync_clk update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:188986.3-188987.37" - process $proc$libresoc.v:188986$13054 + attribute \src "libresoc.v:188941.3-188942.37" + process $proc$libresoc.v:188941$12648 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:188988.3-188989.43" - process $proc$libresoc.v:188988$13055 + attribute \src "libresoc.v:188943.3-188944.43" + process $proc$libresoc.v:188943$12649 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:188990.3-188991.69" - process $proc$libresoc.v:188990$13056 + attribute \src "libresoc.v:188945.3-188946.69" + process $proc$libresoc.v:188945$12650 assign { } { } assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:188992.3-188993.65" - process $proc$libresoc.v:188992$13057 + attribute \src "libresoc.v:188947.3-188948.65" + process $proc$libresoc.v:188947$12651 assign { } { } assign $0\alu_spr0_spr_op__fn_unit[13:0] \alu_spr0_spr_op__fn_unit$next sync posedge \coresync_clk update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:188994.3-188995.59" - process $proc$libresoc.v:188994$13058 + attribute \src "libresoc.v:188949.3-188950.59" + process $proc$libresoc.v:188949$12652 assign { } { } assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:188996.3-188997.67" - process $proc$libresoc.v:188996$13059 + attribute \src "libresoc.v:188951.3-188952.67" + process $proc$libresoc.v:188951$12653 assign { } { } assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next sync posedge \coresync_clk update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:188998.3-188999.39" - process $proc$libresoc.v:188998$13060 + attribute \src "libresoc.v:188953.3-188954.39" + process $proc$libresoc.v:188953$12654 assign { } { } assign $0\req_l_r_req[5:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[5:0] end - attribute \src "libresoc.v:189000.3-189001.39" - process $proc$libresoc.v:189000$13061 + attribute \src "libresoc.v:188955.3-188956.39" + process $proc$libresoc.v:188955$12655 assign { } { } assign $0\req_l_s_req[5:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[5:0] end - attribute \src "libresoc.v:189002.3-189003.39" - process $proc$libresoc.v:189002$13062 + attribute \src "libresoc.v:188957.3-188958.39" + process $proc$libresoc.v:188957$12656 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:189004.3-189005.39" - process $proc$libresoc.v:189004$13063 + attribute \src "libresoc.v:188959.3-188960.39" + process $proc$libresoc.v:188959$12657 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:189006.3-189007.39" - process $proc$libresoc.v:189006$13064 + attribute \src "libresoc.v:188961.3-188962.39" + process $proc$libresoc.v:188961$12658 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:189008.3-189009.39" - process $proc$libresoc.v:189008$13065 + attribute \src "libresoc.v:188963.3-188964.39" + process $proc$libresoc.v:188963$12659 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:189010.3-189011.39" - process $proc$libresoc.v:189010$13066 + attribute \src "libresoc.v:188965.3-188966.39" + process $proc$libresoc.v:188965$12660 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:189012.3-189013.39" - process $proc$libresoc.v:189012$13067 + attribute \src "libresoc.v:188967.3-188968.39" + process $proc$libresoc.v:188967$12661 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:189014.3-189015.41" - process $proc$libresoc.v:189014$13068 + attribute \src "libresoc.v:188969.3-188970.41" + process $proc$libresoc.v:188969$12662 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:189016.3-189017.41" - process $proc$libresoc.v:189016$13069 + attribute \src "libresoc.v:188971.3-188972.41" + process $proc$libresoc.v:188971$12663 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:189018.3-189019.37" - process $proc$libresoc.v:189018$13070 + attribute \src "libresoc.v:188973.3-188974.37" + process $proc$libresoc.v:188973$12664 assign { } { } assign $0\prev_wr_go[5:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[5:0] end - attribute \src "libresoc.v:189020.3-189021.40" - process $proc$libresoc.v:189020$13071 + attribute \src "libresoc.v:188975.3-188976.40" + process $proc$libresoc.v:188975$12665 assign { } { } assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:189022.3-189023.25" - process $proc$libresoc.v:189022$13072 + attribute \src "libresoc.v:188977.3-188978.25" + process $proc$libresoc.v:188977$12666 assign { } { } assign $0\all_rd_dly[0:0] \$14 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:189102.3-189111.6" - process $proc$libresoc.v:189102$13073 + attribute \src "libresoc.v:189057.3-189066.6" + process $proc$libresoc.v:189057$12667 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:189103.5-189103.29" + attribute \src "libresoc.v:189058.5-189058.29" switch \initial - attribute \src "libresoc.v:189103.9-189103.17" + attribute \src "libresoc.v:189058.9-189058.17" case 1'1 case end @@ -394988,14 +358961,14 @@ module \spr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:189112.3-189120.6" - process $proc$libresoc.v:189112$13074 + attribute \src "libresoc.v:189067.3-189075.6" + process $proc$libresoc.v:189067$12668 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$13075 $1\rok_l_s_rdok$next[0:0]$13076 - attribute \src "libresoc.v:189113.5-189113.29" + assign $0\rok_l_s_rdok$next[0:0]$12669 $1\rok_l_s_rdok$next[0:0]$12670 + attribute \src "libresoc.v:189068.5-189068.29" switch \initial - attribute \src "libresoc.v:189113.9-189113.17" + attribute \src "libresoc.v:189068.9-189068.17" case 1'1 case end @@ -395004,21 +358977,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$13076 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12670 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$13076 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12670 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13075 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12669 end - attribute \src "libresoc.v:189121.3-189129.6" - process $proc$libresoc.v:189121$13077 + attribute \src "libresoc.v:189076.3-189084.6" + process $proc$libresoc.v:189076$12671 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$13078 $1\rok_l_r_rdok$next[0:0]$13079 - attribute \src "libresoc.v:189122.5-189122.29" + assign $0\rok_l_r_rdok$next[0:0]$12672 $1\rok_l_r_rdok$next[0:0]$12673 + attribute \src "libresoc.v:189077.5-189077.29" switch \initial - attribute \src "libresoc.v:189122.9-189122.17" + attribute \src "libresoc.v:189077.9-189077.17" case 1'1 case end @@ -395027,21 +359000,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$13079 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12673 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$13079 \$68 + assign $1\rok_l_r_rdok$next[0:0]$12673 \$68 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13078 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12672 end - attribute \src "libresoc.v:189130.3-189138.6" - process $proc$libresoc.v:189130$13080 + attribute \src "libresoc.v:189085.3-189093.6" + process $proc$libresoc.v:189085$12674 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$13081 $1\rst_l_s_rst$next[0:0]$13082 - attribute \src "libresoc.v:189131.5-189131.29" + assign $0\rst_l_s_rst$next[0:0]$12675 $1\rst_l_s_rst$next[0:0]$12676 + attribute \src "libresoc.v:189086.5-189086.29" switch \initial - attribute \src "libresoc.v:189131.9-189131.17" + attribute \src "libresoc.v:189086.9-189086.17" case 1'1 case end @@ -395050,21 +359023,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$13082 1'0 + assign $1\rst_l_s_rst$next[0:0]$12676 1'0 case - assign $1\rst_l_s_rst$next[0:0]$13082 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12676 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13081 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12675 end - attribute \src "libresoc.v:189139.3-189147.6" - process $proc$libresoc.v:189139$13083 + attribute \src "libresoc.v:189094.3-189102.6" + process $proc$libresoc.v:189094$12677 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$13084 $1\rst_l_r_rst$next[0:0]$13085 - attribute \src "libresoc.v:189140.5-189140.29" + assign $0\rst_l_r_rst$next[0:0]$12678 $1\rst_l_r_rst$next[0:0]$12679 + attribute \src "libresoc.v:189095.5-189095.29" switch \initial - attribute \src "libresoc.v:189140.9-189140.17" + attribute \src "libresoc.v:189095.9-189095.17" case 1'1 case end @@ -395073,21 +359046,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$13085 1'1 + assign $1\rst_l_r_rst$next[0:0]$12679 1'1 case - assign $1\rst_l_r_rst$next[0:0]$13085 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12679 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13084 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12678 end - attribute \src "libresoc.v:189148.3-189156.6" - process $proc$libresoc.v:189148$13086 + attribute \src "libresoc.v:189103.3-189111.6" + process $proc$libresoc.v:189103$12680 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$13087 $1\opc_l_s_opc$next[0:0]$13088 - attribute \src "libresoc.v:189149.5-189149.29" + assign $0\opc_l_s_opc$next[0:0]$12681 $1\opc_l_s_opc$next[0:0]$12682 + attribute \src "libresoc.v:189104.5-189104.29" switch \initial - attribute \src "libresoc.v:189149.9-189149.17" + attribute \src "libresoc.v:189104.9-189104.17" case 1'1 case end @@ -395096,21 +359069,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$13088 1'0 + assign $1\opc_l_s_opc$next[0:0]$12682 1'0 case - assign $1\opc_l_s_opc$next[0:0]$13088 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12682 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13087 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12681 end - attribute \src "libresoc.v:189157.3-189165.6" - process $proc$libresoc.v:189157$13089 + attribute \src "libresoc.v:189112.3-189120.6" + process $proc$libresoc.v:189112$12683 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$13090 $1\opc_l_r_opc$next[0:0]$13091 - attribute \src "libresoc.v:189158.5-189158.29" + assign $0\opc_l_r_opc$next[0:0]$12684 $1\opc_l_r_opc$next[0:0]$12685 + attribute \src "libresoc.v:189113.5-189113.29" switch \initial - attribute \src "libresoc.v:189158.9-189158.17" + attribute \src "libresoc.v:189113.9-189113.17" case 1'1 case end @@ -395119,21 +359092,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$13091 1'1 + assign $1\opc_l_r_opc$next[0:0]$12685 1'1 case - assign $1\opc_l_r_opc$next[0:0]$13091 \req_done + assign $1\opc_l_r_opc$next[0:0]$12685 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13090 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12684 end - attribute \src "libresoc.v:189166.3-189174.6" - process $proc$libresoc.v:189166$13092 + attribute \src "libresoc.v:189121.3-189129.6" + process $proc$libresoc.v:189121$12686 assign { } { } assign { } { } - assign $0\src_l_s_src$next[5:0]$13093 $1\src_l_s_src$next[5:0]$13094 - attribute \src "libresoc.v:189167.5-189167.29" + assign $0\src_l_s_src$next[5:0]$12687 $1\src_l_s_src$next[5:0]$12688 + attribute \src "libresoc.v:189122.5-189122.29" switch \initial - attribute \src "libresoc.v:189167.9-189167.17" + attribute \src "libresoc.v:189122.9-189122.17" case 1'1 case end @@ -395142,21 +359115,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[5:0]$13094 6'000000 + assign $1\src_l_s_src$next[5:0]$12688 6'000000 case - assign $1\src_l_s_src$next[5:0]$13094 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[5:0]$12688 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$13093 + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12687 end - attribute \src "libresoc.v:189175.3-189183.6" - process $proc$libresoc.v:189175$13095 + attribute \src "libresoc.v:189130.3-189138.6" + process $proc$libresoc.v:189130$12689 assign { } { } assign { } { } - assign $0\src_l_r_src$next[5:0]$13096 $1\src_l_r_src$next[5:0]$13097 - attribute \src "libresoc.v:189176.5-189176.29" + assign $0\src_l_r_src$next[5:0]$12690 $1\src_l_r_src$next[5:0]$12691 + attribute \src "libresoc.v:189131.5-189131.29" switch \initial - attribute \src "libresoc.v:189176.9-189176.17" + attribute \src "libresoc.v:189131.9-189131.17" case 1'1 case end @@ -395165,21 +359138,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[5:0]$13097 6'111111 + assign $1\src_l_r_src$next[5:0]$12691 6'111111 case - assign $1\src_l_r_src$next[5:0]$13097 \reset_r + assign $1\src_l_r_src$next[5:0]$12691 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$13096 + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12690 end - attribute \src "libresoc.v:189184.3-189192.6" - process $proc$libresoc.v:189184$13098 + attribute \src "libresoc.v:189139.3-189147.6" + process $proc$libresoc.v:189139$12692 assign { } { } assign { } { } - assign $0\req_l_s_req$next[5:0]$13099 $1\req_l_s_req$next[5:0]$13100 - attribute \src "libresoc.v:189185.5-189185.29" + assign $0\req_l_s_req$next[5:0]$12693 $1\req_l_s_req$next[5:0]$12694 + attribute \src "libresoc.v:189140.5-189140.29" switch \initial - attribute \src "libresoc.v:189185.9-189185.17" + attribute \src "libresoc.v:189140.9-189140.17" case 1'1 case end @@ -395188,21 +359161,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[5:0]$13100 6'000000 + assign $1\req_l_s_req$next[5:0]$12694 6'000000 case - assign $1\req_l_s_req$next[5:0]$13100 \$70 + assign $1\req_l_s_req$next[5:0]$12694 \$70 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[5:0]$13099 + update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12693 end - attribute \src "libresoc.v:189193.3-189201.6" - process $proc$libresoc.v:189193$13101 + attribute \src "libresoc.v:189148.3-189156.6" + process $proc$libresoc.v:189148$12695 assign { } { } assign { } { } - assign $0\req_l_r_req$next[5:0]$13102 $1\req_l_r_req$next[5:0]$13103 - attribute \src "libresoc.v:189194.5-189194.29" + assign $0\req_l_r_req$next[5:0]$12696 $1\req_l_r_req$next[5:0]$12697 + attribute \src "libresoc.v:189149.5-189149.29" switch \initial - attribute \src "libresoc.v:189194.9-189194.17" + attribute \src "libresoc.v:189149.9-189149.17" case 1'1 case end @@ -395211,15 +359184,15 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[5:0]$13103 6'111111 + assign $1\req_l_r_req$next[5:0]$12697 6'111111 case - assign $1\req_l_r_req$next[5:0]$13103 \$72 + assign $1\req_l_r_req$next[5:0]$12697 \$72 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[5:0]$13102 + update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12696 end - attribute \src "libresoc.v:189202.3-189214.6" - process $proc$libresoc.v:189202$13104 + attribute \src "libresoc.v:189157.3-189169.6" + process $proc$libresoc.v:189157$12698 assign { } { } assign { } { } assign { } { } @@ -395228,13 +359201,13 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 - assign $0\alu_spr0_spr_op__insn$next[31:0]$13106 $1\alu_spr0_spr_op__insn$next[31:0]$13110 - assign $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 - assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 - attribute \src "libresoc.v:189203.5-189203.29" + assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$12699 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12703 + assign $0\alu_spr0_spr_op__insn$next[31:0]$12700 $1\alu_spr0_spr_op__insn$next[31:0]$12704 + assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12701 $1\alu_spr0_spr_op__insn_type$next[6:0]$12705 + assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12702 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12706 + attribute \src "libresoc.v:189158.5-189158.29" switch \initial - attribute \src "libresoc.v:189203.9-189203.17" + attribute \src "libresoc.v:189158.9-189158.17" case 1'1 case end @@ -395246,33 +359219,33 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 $1\alu_spr0_spr_op__insn$next[31:0]$13110 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12706 $1\alu_spr0_spr_op__insn$next[31:0]$12704 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12703 $1\alu_spr0_spr_op__insn_type$next[6:0]$12705 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } case - assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 \alu_spr0_spr_op__fn_unit - assign $1\alu_spr0_spr_op__insn$next[31:0]$13110 \alu_spr0_spr_op__insn - assign $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 \alu_spr0_spr_op__insn_type - assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 \alu_spr0_spr_op__is_32bit + assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$12703 \alu_spr0_spr_op__fn_unit + assign $1\alu_spr0_spr_op__insn$next[31:0]$12704 \alu_spr0_spr_op__insn + assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12705 \alu_spr0_spr_op__insn_type + assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12706 \alu_spr0_spr_op__is_32bit end sync always - update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 - update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$13106 - update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 - update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 + update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$12699 + update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12700 + update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12701 + update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12702 end - attribute \src "libresoc.v:189215.3-189236.6" - process $proc$libresoc.v:189215$13113 + attribute \src "libresoc.v:189170.3-189191.6" + process $proc$libresoc.v:189170$12707 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$13114 $2\data_r0__o$next[63:0]$13118 + assign $0\data_r0__o$next[63:0]$12708 $2\data_r0__o$next[63:0]$12712 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$13115 $3\data_r0__o_ok$next[0:0]$13120 - attribute \src "libresoc.v:189216.5-189216.29" + assign $0\data_r0__o_ok$next[0:0]$12709 $3\data_r0__o_ok$next[0:0]$12714 + attribute \src "libresoc.v:189171.5-189171.29" switch \initial - attribute \src "libresoc.v:189216.9-189216.17" + attribute \src "libresoc.v:189171.9-189171.17" case 1'1 case end @@ -395282,10 +359255,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$13117 $1\data_r0__o$next[63:0]$13116 } { \o_ok \alu_spr0_o } + assign { $1\data_r0__o_ok$next[0:0]$12711 $1\data_r0__o$next[63:0]$12710 } { \o_ok \alu_spr0_o } case - assign $1\data_r0__o$next[63:0]$13116 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$13117 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12710 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12711 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -395293,38 +359266,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$13119 $2\data_r0__o$next[63:0]$13118 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12713 $2\data_r0__o$next[63:0]$12712 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$13118 $1\data_r0__o$next[63:0]$13116 - assign $2\data_r0__o_ok$next[0:0]$13119 $1\data_r0__o_ok$next[0:0]$13117 + assign $2\data_r0__o$next[63:0]$12712 $1\data_r0__o$next[63:0]$12710 + assign $2\data_r0__o_ok$next[0:0]$12713 $1\data_r0__o_ok$next[0:0]$12711 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$13120 1'0 + assign $3\data_r0__o_ok$next[0:0]$12714 1'0 case - assign $3\data_r0__o_ok$next[0:0]$13120 $2\data_r0__o_ok$next[0:0]$13119 + assign $3\data_r0__o_ok$next[0:0]$12714 $2\data_r0__o_ok$next[0:0]$12713 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$13114 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13115 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12708 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12709 end - attribute \src "libresoc.v:189237.3-189258.6" - process $proc$libresoc.v:189237$13121 + attribute \src "libresoc.v:189192.3-189213.6" + process $proc$libresoc.v:189192$12715 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__spr1$next[63:0]$13122 $2\data_r1__spr1$next[63:0]$13126 + assign $0\data_r1__spr1$next[63:0]$12716 $2\data_r1__spr1$next[63:0]$12720 assign { } { } - assign $0\data_r1__spr1_ok$next[0:0]$13123 $3\data_r1__spr1_ok$next[0:0]$13128 - attribute \src "libresoc.v:189238.5-189238.29" + assign $0\data_r1__spr1_ok$next[0:0]$12717 $3\data_r1__spr1_ok$next[0:0]$12722 + attribute \src "libresoc.v:189193.5-189193.29" switch \initial - attribute \src "libresoc.v:189238.9-189238.17" + attribute \src "libresoc.v:189193.9-189193.17" case 1'1 case end @@ -395334,10 +359307,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__spr1_ok$next[0:0]$13125 $1\data_r1__spr1$next[63:0]$13124 } { \spr1_ok \alu_spr0_spr1 } + assign { $1\data_r1__spr1_ok$next[0:0]$12719 $1\data_r1__spr1$next[63:0]$12718 } { \spr1_ok \alu_spr0_spr1 } case - assign $1\data_r1__spr1$next[63:0]$13124 \data_r1__spr1 - assign $1\data_r1__spr1_ok$next[0:0]$13125 \data_r1__spr1_ok + assign $1\data_r1__spr1$next[63:0]$12718 \data_r1__spr1 + assign $1\data_r1__spr1_ok$next[0:0]$12719 \data_r1__spr1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -395345,38 +359318,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__spr1_ok$next[0:0]$13127 $2\data_r1__spr1$next[63:0]$13126 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__spr1_ok$next[0:0]$12721 $2\data_r1__spr1$next[63:0]$12720 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__spr1$next[63:0]$13126 $1\data_r1__spr1$next[63:0]$13124 - assign $2\data_r1__spr1_ok$next[0:0]$13127 $1\data_r1__spr1_ok$next[0:0]$13125 + assign $2\data_r1__spr1$next[63:0]$12720 $1\data_r1__spr1$next[63:0]$12718 + assign $2\data_r1__spr1_ok$next[0:0]$12721 $1\data_r1__spr1_ok$next[0:0]$12719 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__spr1_ok$next[0:0]$13128 1'0 + assign $3\data_r1__spr1_ok$next[0:0]$12722 1'0 case - assign $3\data_r1__spr1_ok$next[0:0]$13128 $2\data_r1__spr1_ok$next[0:0]$13127 + assign $3\data_r1__spr1_ok$next[0:0]$12722 $2\data_r1__spr1_ok$next[0:0]$12721 end sync always - update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$13122 - update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$13123 + update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12716 + update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12717 end - attribute \src "libresoc.v:189259.3-189280.6" - process $proc$libresoc.v:189259$13129 + attribute \src "libresoc.v:189214.3-189235.6" + process $proc$libresoc.v:189214$12723 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast1$next[63:0]$13130 $2\data_r2__fast1$next[63:0]$13134 + assign $0\data_r2__fast1$next[63:0]$12724 $2\data_r2__fast1$next[63:0]$12728 assign { } { } - assign $0\data_r2__fast1_ok$next[0:0]$13131 $3\data_r2__fast1_ok$next[0:0]$13136 - attribute \src "libresoc.v:189260.5-189260.29" + assign $0\data_r2__fast1_ok$next[0:0]$12725 $3\data_r2__fast1_ok$next[0:0]$12730 + attribute \src "libresoc.v:189215.5-189215.29" switch \initial - attribute \src "libresoc.v:189260.9-189260.17" + attribute \src "libresoc.v:189215.9-189215.17" case 1'1 case end @@ -395386,10 +359359,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast1_ok$next[0:0]$13133 $1\data_r2__fast1$next[63:0]$13132 } { \fast1_ok \alu_spr0_fast1 } + assign { $1\data_r2__fast1_ok$next[0:0]$12727 $1\data_r2__fast1$next[63:0]$12726 } { \fast1_ok \alu_spr0_fast1 } case - assign $1\data_r2__fast1$next[63:0]$13132 \data_r2__fast1 - assign $1\data_r2__fast1_ok$next[0:0]$13133 \data_r2__fast1_ok + assign $1\data_r2__fast1$next[63:0]$12726 \data_r2__fast1 + assign $1\data_r2__fast1_ok$next[0:0]$12727 \data_r2__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -395397,38 +359370,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast1_ok$next[0:0]$13135 $2\data_r2__fast1$next[63:0]$13134 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast1_ok$next[0:0]$12729 $2\data_r2__fast1$next[63:0]$12728 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast1$next[63:0]$13134 $1\data_r2__fast1$next[63:0]$13132 - assign $2\data_r2__fast1_ok$next[0:0]$13135 $1\data_r2__fast1_ok$next[0:0]$13133 + assign $2\data_r2__fast1$next[63:0]$12728 $1\data_r2__fast1$next[63:0]$12726 + assign $2\data_r2__fast1_ok$next[0:0]$12729 $1\data_r2__fast1_ok$next[0:0]$12727 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast1_ok$next[0:0]$13136 1'0 + assign $3\data_r2__fast1_ok$next[0:0]$12730 1'0 case - assign $3\data_r2__fast1_ok$next[0:0]$13136 $2\data_r2__fast1_ok$next[0:0]$13135 + assign $3\data_r2__fast1_ok$next[0:0]$12730 $2\data_r2__fast1_ok$next[0:0]$12729 end sync always - update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$13130 - update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$13131 + update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12724 + update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12725 end - attribute \src "libresoc.v:189281.3-189302.6" - process $proc$libresoc.v:189281$13137 + attribute \src "libresoc.v:189236.3-189257.6" + process $proc$libresoc.v:189236$12731 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$13138 $2\data_r3__xer_so$next[0:0]$13142 + assign $0\data_r3__xer_so$next[0:0]$12732 $2\data_r3__xer_so$next[0:0]$12736 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$13139 $3\data_r3__xer_so_ok$next[0:0]$13144 - attribute \src "libresoc.v:189282.5-189282.29" + assign $0\data_r3__xer_so_ok$next[0:0]$12733 $3\data_r3__xer_so_ok$next[0:0]$12738 + attribute \src "libresoc.v:189237.5-189237.29" switch \initial - attribute \src "libresoc.v:189282.9-189282.17" + attribute \src "libresoc.v:189237.9-189237.17" case 1'1 case end @@ -395438,10 +359411,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$13141 $1\data_r3__xer_so$next[0:0]$13140 } { \xer_so_ok \alu_spr0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$12735 $1\data_r3__xer_so$next[0:0]$12734 } { \xer_so_ok \alu_spr0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$13140 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$13141 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$12734 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$12735 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -395449,38 +359422,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$13143 $2\data_r3__xer_so$next[0:0]$13142 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$12737 $2\data_r3__xer_so$next[0:0]$12736 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$13142 $1\data_r3__xer_so$next[0:0]$13140 - assign $2\data_r3__xer_so_ok$next[0:0]$13143 $1\data_r3__xer_so_ok$next[0:0]$13141 + assign $2\data_r3__xer_so$next[0:0]$12736 $1\data_r3__xer_so$next[0:0]$12734 + assign $2\data_r3__xer_so_ok$next[0:0]$12737 $1\data_r3__xer_so_ok$next[0:0]$12735 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$13144 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$12738 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$13144 $2\data_r3__xer_so_ok$next[0:0]$13143 + assign $3\data_r3__xer_so_ok$next[0:0]$12738 $2\data_r3__xer_so_ok$next[0:0]$12737 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$13138 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$13139 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12732 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12733 end - attribute \src "libresoc.v:189303.3-189324.6" - process $proc$libresoc.v:189303$13145 + attribute \src "libresoc.v:189258.3-189279.6" + process $proc$libresoc.v:189258$12739 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__xer_ov$next[1:0]$13146 $2\data_r4__xer_ov$next[1:0]$13150 + assign $0\data_r4__xer_ov$next[1:0]$12740 $2\data_r4__xer_ov$next[1:0]$12744 assign { } { } - assign $0\data_r4__xer_ov_ok$next[0:0]$13147 $3\data_r4__xer_ov_ok$next[0:0]$13152 - attribute \src "libresoc.v:189304.5-189304.29" + assign $0\data_r4__xer_ov_ok$next[0:0]$12741 $3\data_r4__xer_ov_ok$next[0:0]$12746 + attribute \src "libresoc.v:189259.5-189259.29" switch \initial - attribute \src "libresoc.v:189304.9-189304.17" + attribute \src "libresoc.v:189259.9-189259.17" case 1'1 case end @@ -395490,10 +359463,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__xer_ov_ok$next[0:0]$13149 $1\data_r4__xer_ov$next[1:0]$13148 } { \xer_ov_ok \alu_spr0_xer_ov } + assign { $1\data_r4__xer_ov_ok$next[0:0]$12743 $1\data_r4__xer_ov$next[1:0]$12742 } { \xer_ov_ok \alu_spr0_xer_ov } case - assign $1\data_r4__xer_ov$next[1:0]$13148 \data_r4__xer_ov - assign $1\data_r4__xer_ov_ok$next[0:0]$13149 \data_r4__xer_ov_ok + assign $1\data_r4__xer_ov$next[1:0]$12742 \data_r4__xer_ov + assign $1\data_r4__xer_ov_ok$next[0:0]$12743 \data_r4__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -395501,38 +359474,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__xer_ov_ok$next[0:0]$13151 $2\data_r4__xer_ov$next[1:0]$13150 } 3'000 + assign { $2\data_r4__xer_ov_ok$next[0:0]$12745 $2\data_r4__xer_ov$next[1:0]$12744 } 3'000 case - assign $2\data_r4__xer_ov$next[1:0]$13150 $1\data_r4__xer_ov$next[1:0]$13148 - assign $2\data_r4__xer_ov_ok$next[0:0]$13151 $1\data_r4__xer_ov_ok$next[0:0]$13149 + assign $2\data_r4__xer_ov$next[1:0]$12744 $1\data_r4__xer_ov$next[1:0]$12742 + assign $2\data_r4__xer_ov_ok$next[0:0]$12745 $1\data_r4__xer_ov_ok$next[0:0]$12743 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__xer_ov_ok$next[0:0]$13152 1'0 + assign $3\data_r4__xer_ov_ok$next[0:0]$12746 1'0 case - assign $3\data_r4__xer_ov_ok$next[0:0]$13152 $2\data_r4__xer_ov_ok$next[0:0]$13151 + assign $3\data_r4__xer_ov_ok$next[0:0]$12746 $2\data_r4__xer_ov_ok$next[0:0]$12745 end sync always - update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$13146 - update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$13147 + update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12740 + update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12741 end - attribute \src "libresoc.v:189325.3-189346.6" - process $proc$libresoc.v:189325$13153 + attribute \src "libresoc.v:189280.3-189301.6" + process $proc$libresoc.v:189280$12747 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r5__xer_ca$next[1:0]$13154 $2\data_r5__xer_ca$next[1:0]$13158 + assign $0\data_r5__xer_ca$next[1:0]$12748 $2\data_r5__xer_ca$next[1:0]$12752 assign { } { } - assign $0\data_r5__xer_ca_ok$next[0:0]$13155 $3\data_r5__xer_ca_ok$next[0:0]$13160 - attribute \src "libresoc.v:189326.5-189326.29" + assign $0\data_r5__xer_ca_ok$next[0:0]$12749 $3\data_r5__xer_ca_ok$next[0:0]$12754 + attribute \src "libresoc.v:189281.5-189281.29" switch \initial - attribute \src "libresoc.v:189326.9-189326.17" + attribute \src "libresoc.v:189281.9-189281.17" case 1'1 case end @@ -395542,10 +359515,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r5__xer_ca_ok$next[0:0]$13157 $1\data_r5__xer_ca$next[1:0]$13156 } { \xer_ca_ok \alu_spr0_xer_ca } + assign { $1\data_r5__xer_ca_ok$next[0:0]$12751 $1\data_r5__xer_ca$next[1:0]$12750 } { \xer_ca_ok \alu_spr0_xer_ca } case - assign $1\data_r5__xer_ca$next[1:0]$13156 \data_r5__xer_ca - assign $1\data_r5__xer_ca_ok$next[0:0]$13157 \data_r5__xer_ca_ok + assign $1\data_r5__xer_ca$next[1:0]$12750 \data_r5__xer_ca + assign $1\data_r5__xer_ca_ok$next[0:0]$12751 \data_r5__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -395553,32 +359526,32 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r5__xer_ca_ok$next[0:0]$13159 $2\data_r5__xer_ca$next[1:0]$13158 } 3'000 + assign { $2\data_r5__xer_ca_ok$next[0:0]$12753 $2\data_r5__xer_ca$next[1:0]$12752 } 3'000 case - assign $2\data_r5__xer_ca$next[1:0]$13158 $1\data_r5__xer_ca$next[1:0]$13156 - assign $2\data_r5__xer_ca_ok$next[0:0]$13159 $1\data_r5__xer_ca_ok$next[0:0]$13157 + assign $2\data_r5__xer_ca$next[1:0]$12752 $1\data_r5__xer_ca$next[1:0]$12750 + assign $2\data_r5__xer_ca_ok$next[0:0]$12753 $1\data_r5__xer_ca_ok$next[0:0]$12751 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r5__xer_ca_ok$next[0:0]$13160 1'0 + assign $3\data_r5__xer_ca_ok$next[0:0]$12754 1'0 case - assign $3\data_r5__xer_ca_ok$next[0:0]$13160 $2\data_r5__xer_ca_ok$next[0:0]$13159 + assign $3\data_r5__xer_ca_ok$next[0:0]$12754 $2\data_r5__xer_ca_ok$next[0:0]$12753 end sync always - update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$13154 - update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$13155 + update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12748 + update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12749 end - attribute \src "libresoc.v:189347.3-189356.6" - process $proc$libresoc.v:189347$13161 + attribute \src "libresoc.v:189302.3-189311.6" + process $proc$libresoc.v:189302$12755 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$13162 $1\src_r0$next[63:0]$13163 - attribute \src "libresoc.v:189348.5-189348.29" + assign $0\src_r0$next[63:0]$12756 $1\src_r0$next[63:0]$12757 + attribute \src "libresoc.v:189303.5-189303.29" switch \initial - attribute \src "libresoc.v:189348.9-189348.17" + attribute \src "libresoc.v:189303.9-189303.17" case 1'1 case end @@ -395587,21 +359560,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$13163 \src1_i + assign $1\src_r0$next[63:0]$12757 \src1_i case - assign $1\src_r0$next[63:0]$13163 \src_r0 + assign $1\src_r0$next[63:0]$12757 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$13162 + update \src_r0$next $0\src_r0$next[63:0]$12756 end - attribute \src "libresoc.v:189357.3-189366.6" - process $proc$libresoc.v:189357$13164 + attribute \src "libresoc.v:189312.3-189321.6" + process $proc$libresoc.v:189312$12758 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$13165 $1\src_r1$next[63:0]$13166 - attribute \src "libresoc.v:189358.5-189358.29" + assign $0\src_r1$next[63:0]$12759 $1\src_r1$next[63:0]$12760 + attribute \src "libresoc.v:189313.5-189313.29" switch \initial - attribute \src "libresoc.v:189358.9-189358.17" + attribute \src "libresoc.v:189313.9-189313.17" case 1'1 case end @@ -395610,21 +359583,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$13166 \src2_i + assign $1\src_r1$next[63:0]$12760 \src2_i case - assign $1\src_r1$next[63:0]$13166 \src_r1 + assign $1\src_r1$next[63:0]$12760 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$13165 + update \src_r1$next $0\src_r1$next[63:0]$12759 end - attribute \src "libresoc.v:189367.3-189376.6" - process $proc$libresoc.v:189367$13167 + attribute \src "libresoc.v:189322.3-189331.6" + process $proc$libresoc.v:189322$12761 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$13168 $1\src_r2$next[63:0]$13169 - attribute \src "libresoc.v:189368.5-189368.29" + assign $0\src_r2$next[63:0]$12762 $1\src_r2$next[63:0]$12763 + attribute \src "libresoc.v:189323.5-189323.29" switch \initial - attribute \src "libresoc.v:189368.9-189368.17" + attribute \src "libresoc.v:189323.9-189323.17" case 1'1 case end @@ -395633,21 +359606,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$13169 \src3_i + assign $1\src_r2$next[63:0]$12763 \src3_i case - assign $1\src_r2$next[63:0]$13169 \src_r2 + assign $1\src_r2$next[63:0]$12763 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$13168 + update \src_r2$next $0\src_r2$next[63:0]$12762 end - attribute \src "libresoc.v:189377.3-189386.6" - process $proc$libresoc.v:189377$13170 + attribute \src "libresoc.v:189332.3-189341.6" + process $proc$libresoc.v:189332$12764 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$13171 $1\src_r3$next[0:0]$13172 - attribute \src "libresoc.v:189378.5-189378.29" + assign $0\src_r3$next[0:0]$12765 $1\src_r3$next[0:0]$12766 + attribute \src "libresoc.v:189333.5-189333.29" switch \initial - attribute \src "libresoc.v:189378.9-189378.17" + attribute \src "libresoc.v:189333.9-189333.17" case 1'1 case end @@ -395656,21 +359629,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$13172 \src4_i + assign $1\src_r3$next[0:0]$12766 \src4_i case - assign $1\src_r3$next[0:0]$13172 \src_r3 + assign $1\src_r3$next[0:0]$12766 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$13171 + update \src_r3$next $0\src_r3$next[0:0]$12765 end - attribute \src "libresoc.v:189387.3-189396.6" - process $proc$libresoc.v:189387$13173 + attribute \src "libresoc.v:189342.3-189351.6" + process $proc$libresoc.v:189342$12767 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$13174 $1\src_r4$next[1:0]$13175 - attribute \src "libresoc.v:189388.5-189388.29" + assign $0\src_r4$next[1:0]$12768 $1\src_r4$next[1:0]$12769 + attribute \src "libresoc.v:189343.5-189343.29" switch \initial - attribute \src "libresoc.v:189388.9-189388.17" + attribute \src "libresoc.v:189343.9-189343.17" case 1'1 case end @@ -395679,21 +359652,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$13175 \src5_i + assign $1\src_r4$next[1:0]$12769 \src5_i case - assign $1\src_r4$next[1:0]$13175 \src_r4 + assign $1\src_r4$next[1:0]$12769 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$13174 + update \src_r4$next $0\src_r4$next[1:0]$12768 end - attribute \src "libresoc.v:189397.3-189406.6" - process $proc$libresoc.v:189397$13176 + attribute \src "libresoc.v:189352.3-189361.6" + process $proc$libresoc.v:189352$12770 assign { } { } assign { } { } - assign $0\src_r5$next[1:0]$13177 $1\src_r5$next[1:0]$13178 - attribute \src "libresoc.v:189398.5-189398.29" + assign $0\src_r5$next[1:0]$12771 $1\src_r5$next[1:0]$12772 + attribute \src "libresoc.v:189353.5-189353.29" switch \initial - attribute \src "libresoc.v:189398.9-189398.17" + attribute \src "libresoc.v:189353.9-189353.17" case 1'1 case end @@ -395702,21 +359675,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r5$next[1:0]$13178 \src6_i + assign $1\src_r5$next[1:0]$12772 \src6_i case - assign $1\src_r5$next[1:0]$13178 \src_r5 + assign $1\src_r5$next[1:0]$12772 \src_r5 end sync always - update \src_r5$next $0\src_r5$next[1:0]$13177 + update \src_r5$next $0\src_r5$next[1:0]$12771 end - attribute \src "libresoc.v:189407.3-189415.6" - process $proc$libresoc.v:189407$13179 + attribute \src "libresoc.v:189362.3-189370.6" + process $proc$libresoc.v:189362$12773 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$13180 $1\alui_l_r_alui$next[0:0]$13181 - attribute \src "libresoc.v:189408.5-189408.29" + assign $0\alui_l_r_alui$next[0:0]$12774 $1\alui_l_r_alui$next[0:0]$12775 + attribute \src "libresoc.v:189363.5-189363.29" switch \initial - attribute \src "libresoc.v:189408.9-189408.17" + attribute \src "libresoc.v:189363.9-189363.17" case 1'1 case end @@ -395725,21 +359698,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$13181 1'1 + assign $1\alui_l_r_alui$next[0:0]$12775 1'1 case - assign $1\alui_l_r_alui$next[0:0]$13181 \$98 + assign $1\alui_l_r_alui$next[0:0]$12775 \$98 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13180 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12774 end - attribute \src "libresoc.v:189416.3-189424.6" - process $proc$libresoc.v:189416$13182 + attribute \src "libresoc.v:189371.3-189379.6" + process $proc$libresoc.v:189371$12776 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$13183 $1\alu_l_r_alu$next[0:0]$13184 - attribute \src "libresoc.v:189417.5-189417.29" + assign $0\alu_l_r_alu$next[0:0]$12777 $1\alu_l_r_alu$next[0:0]$12778 + attribute \src "libresoc.v:189372.5-189372.29" switch \initial - attribute \src "libresoc.v:189417.9-189417.17" + attribute \src "libresoc.v:189372.9-189372.17" case 1'1 case end @@ -395748,21 +359721,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$13184 1'1 + assign $1\alu_l_r_alu$next[0:0]$12778 1'1 case - assign $1\alu_l_r_alu$next[0:0]$13184 \$100 + assign $1\alu_l_r_alu$next[0:0]$12778 \$100 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13183 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12777 end - attribute \src "libresoc.v:189425.3-189434.6" - process $proc$libresoc.v:189425$13185 + attribute \src "libresoc.v:189380.3-189389.6" + process $proc$libresoc.v:189380$12779 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:189426.5-189426.29" + attribute \src "libresoc.v:189381.5-189381.29" switch \initial - attribute \src "libresoc.v:189426.9-189426.17" + attribute \src "libresoc.v:189381.9-189381.17" case 1'1 case end @@ -395778,14 +359751,14 @@ module \spr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:189435.3-189444.6" - process $proc$libresoc.v:189435$13186 + attribute \src "libresoc.v:189390.3-189399.6" + process $proc$libresoc.v:189390$12780 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:189436.5-189436.29" + attribute \src "libresoc.v:189391.5-189391.29" switch \initial - attribute \src "libresoc.v:189436.9-189436.17" + attribute \src "libresoc.v:189391.9-189391.17" case 1'1 case end @@ -395801,14 +359774,14 @@ module \spr0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:189445.3-189454.6" - process $proc$libresoc.v:189445$13187 + attribute \src "libresoc.v:189400.3-189409.6" + process $proc$libresoc.v:189400$12781 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:189446.5-189446.29" + attribute \src "libresoc.v:189401.5-189401.29" switch \initial - attribute \src "libresoc.v:189446.9-189446.17" + attribute \src "libresoc.v:189401.9-189401.17" case 1'1 case end @@ -395824,14 +359797,14 @@ module \spr0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:189455.3-189464.6" - process $proc$libresoc.v:189455$13188 + attribute \src "libresoc.v:189410.3-189419.6" + process $proc$libresoc.v:189410$12782 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:189456.5-189456.29" + attribute \src "libresoc.v:189411.5-189411.29" switch \initial - attribute \src "libresoc.v:189456.9-189456.17" + attribute \src "libresoc.v:189411.9-189411.17" case 1'1 case end @@ -395847,14 +359820,14 @@ module \spr0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:189465.3-189474.6" - process $proc$libresoc.v:189465$13189 + attribute \src "libresoc.v:189420.3-189429.6" + process $proc$libresoc.v:189420$12783 assign { } { } assign { } { } assign $0\dest5_o[1:0] $1\dest5_o[1:0] - attribute \src "libresoc.v:189466.5-189466.29" + attribute \src "libresoc.v:189421.5-189421.29" switch \initial - attribute \src "libresoc.v:189466.9-189466.17" + attribute \src "libresoc.v:189421.9-189421.17" case 1'1 case end @@ -395870,14 +359843,14 @@ module \spr0 sync always update \dest5_o $0\dest5_o[1:0] end - attribute \src "libresoc.v:189475.3-189484.6" - process $proc$libresoc.v:189475$13190 + attribute \src "libresoc.v:189430.3-189439.6" + process $proc$libresoc.v:189430$12784 assign { } { } assign { } { } assign $0\dest6_o[1:0] $1\dest6_o[1:0] - attribute \src "libresoc.v:189476.5-189476.29" + attribute \src "libresoc.v:189431.5-189431.29" switch \initial - attribute \src "libresoc.v:189476.9-189476.17" + attribute \src "libresoc.v:189431.9-189431.17" case 1'1 case end @@ -395893,14 +359866,14 @@ module \spr0 sync always update \dest6_o $0\dest6_o[1:0] end - attribute \src "libresoc.v:189485.3-189493.6" - process $proc$libresoc.v:189485$13191 + attribute \src "libresoc.v:189440.3-189448.6" + process $proc$libresoc.v:189440$12785 assign { } { } assign { } { } - assign $0\prev_wr_go$next[5:0]$13192 $1\prev_wr_go$next[5:0]$13193 - attribute \src "libresoc.v:189486.5-189486.29" + assign $0\prev_wr_go$next[5:0]$12786 $1\prev_wr_go$next[5:0]$12787 + attribute \src "libresoc.v:189441.5-189441.29" switch \initial - attribute \src "libresoc.v:189486.9-189486.17" + attribute \src "libresoc.v:189441.9-189441.17" case 1'1 case end @@ -395909,79 +359882,79 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[5:0]$13193 6'000000 - case - assign $1\prev_wr_go$next[5:0]$13193 \$24 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13192 - end - connect \$9 $not$libresoc.v:188884$12970_Y - connect \$100 $and$libresoc.v:188885$12971_Y - connect \$102 $and$libresoc.v:188886$12972_Y - connect \$104 $and$libresoc.v:188887$12973_Y - connect \$106 $not$libresoc.v:188888$12974_Y - connect \$108 $and$libresoc.v:188889$12975_Y - connect \$110 $and$libresoc.v:188890$12976_Y - connect \$112 $and$libresoc.v:188891$12977_Y - connect \$114 $and$libresoc.v:188892$12978_Y - connect \$116 $and$libresoc.v:188893$12979_Y - connect \$118 $and$libresoc.v:188894$12980_Y - connect \$11 $or$libresoc.v:188895$12981_Y - connect \$120 $and$libresoc.v:188896$12982_Y - connect \$122 $and$libresoc.v:188897$12983_Y - connect \$124 $and$libresoc.v:188898$12984_Y - connect \$126 $and$libresoc.v:188899$12985_Y - connect \$128 $and$libresoc.v:188900$12986_Y - connect \$8 $reduce_and$libresoc.v:188901$12987_Y - connect \$130 $and$libresoc.v:188902$12988_Y - connect \$132 $and$libresoc.v:188903$12989_Y - connect \$134 $and$libresoc.v:188904$12990_Y - connect \$136 $and$libresoc.v:188905$12991_Y - connect \$14 $and$libresoc.v:188906$12992_Y - connect \$16 $not$libresoc.v:188907$12993_Y - connect \$18 $and$libresoc.v:188908$12994_Y - connect \$20 $not$libresoc.v:188909$12995_Y - connect \$22 $and$libresoc.v:188910$12996_Y - connect \$24 $and$libresoc.v:188911$12997_Y - connect \$28 $not$libresoc.v:188912$12998_Y - connect \$30 $and$libresoc.v:188913$12999_Y - connect \$27 $reduce_or$libresoc.v:188914$13000_Y - connect \$26 $not$libresoc.v:188915$13001_Y - connect \$34 $and$libresoc.v:188916$13002_Y - connect \$36 $reduce_or$libresoc.v:188917$13003_Y - connect \$38 $reduce_or$libresoc.v:188918$13004_Y - connect \$40 $or$libresoc.v:188919$13005_Y - connect \$42 $not$libresoc.v:188920$13006_Y - connect \$44 $and$libresoc.v:188921$13007_Y - connect \$46 $and$libresoc.v:188922$13008_Y - connect \$48 $eq$libresoc.v:188923$13009_Y - connect \$50 $and$libresoc.v:188924$13010_Y - connect \$52 $eq$libresoc.v:188925$13011_Y - connect \$54 $and$libresoc.v:188926$13012_Y - connect \$56 $and$libresoc.v:188927$13013_Y - connect \$58 $and$libresoc.v:188928$13014_Y - connect \$60 $or$libresoc.v:188929$13015_Y - connect \$62 $or$libresoc.v:188930$13016_Y - connect \$64 $or$libresoc.v:188931$13017_Y - connect \$66 $or$libresoc.v:188932$13018_Y - connect \$68 $and$libresoc.v:188933$13019_Y - connect \$6 $and$libresoc.v:188934$13020_Y - connect \$70 $and$libresoc.v:188935$13021_Y - connect \$72 $or$libresoc.v:188936$13022_Y - connect \$74 $and$libresoc.v:188937$13023_Y - connect \$76 $and$libresoc.v:188938$13024_Y - connect \$78 $and$libresoc.v:188939$13025_Y - connect \$80 $and$libresoc.v:188940$13026_Y - connect \$82 $and$libresoc.v:188941$13027_Y - connect \$84 $and$libresoc.v:188942$13028_Y - connect \$86 $ternary$libresoc.v:188943$13029_Y - connect \$88 $ternary$libresoc.v:188944$13030_Y - connect \$90 $ternary$libresoc.v:188945$13031_Y - connect \$92 $ternary$libresoc.v:188946$13032_Y - connect \$94 $ternary$libresoc.v:188947$13033_Y - connect \$96 $ternary$libresoc.v:188948$13034_Y - connect \$98 $and$libresoc.v:188949$13035_Y + assign $1\prev_wr_go$next[5:0]$12787 6'000000 + case + assign $1\prev_wr_go$next[5:0]$12787 \$24 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12786 + end + connect \$9 $not$libresoc.v:188839$12564_Y + connect \$100 $and$libresoc.v:188840$12565_Y + connect \$102 $and$libresoc.v:188841$12566_Y + connect \$104 $and$libresoc.v:188842$12567_Y + connect \$106 $not$libresoc.v:188843$12568_Y + connect \$108 $and$libresoc.v:188844$12569_Y + connect \$110 $and$libresoc.v:188845$12570_Y + connect \$112 $and$libresoc.v:188846$12571_Y + connect \$114 $and$libresoc.v:188847$12572_Y + connect \$116 $and$libresoc.v:188848$12573_Y + connect \$118 $and$libresoc.v:188849$12574_Y + connect \$11 $or$libresoc.v:188850$12575_Y + connect \$120 $and$libresoc.v:188851$12576_Y + connect \$122 $and$libresoc.v:188852$12577_Y + connect \$124 $and$libresoc.v:188853$12578_Y + connect \$126 $and$libresoc.v:188854$12579_Y + connect \$128 $and$libresoc.v:188855$12580_Y + connect \$8 $reduce_and$libresoc.v:188856$12581_Y + connect \$130 $and$libresoc.v:188857$12582_Y + connect \$132 $and$libresoc.v:188858$12583_Y + connect \$134 $and$libresoc.v:188859$12584_Y + connect \$136 $and$libresoc.v:188860$12585_Y + connect \$14 $and$libresoc.v:188861$12586_Y + connect \$16 $not$libresoc.v:188862$12587_Y + connect \$18 $and$libresoc.v:188863$12588_Y + connect \$20 $not$libresoc.v:188864$12589_Y + connect \$22 $and$libresoc.v:188865$12590_Y + connect \$24 $and$libresoc.v:188866$12591_Y + connect \$28 $not$libresoc.v:188867$12592_Y + connect \$30 $and$libresoc.v:188868$12593_Y + connect \$27 $reduce_or$libresoc.v:188869$12594_Y + connect \$26 $not$libresoc.v:188870$12595_Y + connect \$34 $and$libresoc.v:188871$12596_Y + connect \$36 $reduce_or$libresoc.v:188872$12597_Y + connect \$38 $reduce_or$libresoc.v:188873$12598_Y + connect \$40 $or$libresoc.v:188874$12599_Y + connect \$42 $not$libresoc.v:188875$12600_Y + connect \$44 $and$libresoc.v:188876$12601_Y + connect \$46 $and$libresoc.v:188877$12602_Y + connect \$48 $eq$libresoc.v:188878$12603_Y + connect \$50 $and$libresoc.v:188879$12604_Y + connect \$52 $eq$libresoc.v:188880$12605_Y + connect \$54 $and$libresoc.v:188881$12606_Y + connect \$56 $and$libresoc.v:188882$12607_Y + connect \$58 $and$libresoc.v:188883$12608_Y + connect \$60 $or$libresoc.v:188884$12609_Y + connect \$62 $or$libresoc.v:188885$12610_Y + connect \$64 $or$libresoc.v:188886$12611_Y + connect \$66 $or$libresoc.v:188887$12612_Y + connect \$68 $and$libresoc.v:188888$12613_Y + connect \$6 $and$libresoc.v:188889$12614_Y + connect \$70 $and$libresoc.v:188890$12615_Y + connect \$72 $or$libresoc.v:188891$12616_Y + connect \$74 $and$libresoc.v:188892$12617_Y + connect \$76 $and$libresoc.v:188893$12618_Y + connect \$78 $and$libresoc.v:188894$12619_Y + connect \$80 $and$libresoc.v:188895$12620_Y + connect \$82 $and$libresoc.v:188896$12621_Y + connect \$84 $and$libresoc.v:188897$12622_Y + connect \$86 $ternary$libresoc.v:188898$12623_Y + connect \$88 $ternary$libresoc.v:188899$12624_Y + connect \$90 $ternary$libresoc.v:188900$12625_Y + connect \$92 $ternary$libresoc.v:188901$12626_Y + connect \$94 $ternary$libresoc.v:188902$12627_Y + connect \$96 $ternary$libresoc.v:188903$12628_Y + connect \$98 $and$libresoc.v:188904$12629_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$124 @@ -396014,150 +359987,150 @@ module \spr0 connect \all_rd_dly$next \all_rd connect \all_rd \$14 end -attribute \src "libresoc.v:189529.1-190049.10" +attribute \src "libresoc.v:189484.1-190008.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" attribute \generator "nMigen" module \spr_main - attribute \src "libresoc.v:189802.3-189817.6" - wire width 64 $0\fast1$7[63:0]$13240 - attribute \src "libresoc.v:189879.3-189894.6" + attribute \src "libresoc.v:189757.3-189772.6" + wire width 64 $0\fast1$7[63:0]$12834 + attribute \src "libresoc.v:189838.3-189853.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:189530.7-189530.20" + attribute \src "libresoc.v:189485.7-189485.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189837.3-189878.6" + attribute \src "libresoc.v:189792.3-189837.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:189837.3-189878.6" + attribute \src "libresoc.v:189792.3-189837.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:190027.3-190045.6" - wire width 64 $0\spr1$6[63:0]$13265 - attribute \src "libresoc.v:189818.3-189836.6" + attribute \src "libresoc.v:189986.3-190004.6" + wire width 64 $0\spr1$6[63:0]$12859 + attribute \src "libresoc.v:189773.3-189791.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:189982.3-190005.6" - wire width 2 $0\xer_ca$10[1:0]$13259 - attribute \src "libresoc.v:190006.3-190026.6" + attribute \src "libresoc.v:189941.3-189964.6" + wire width 2 $0\xer_ca$10[1:0]$12853 + attribute \src "libresoc.v:189965.3-189985.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:189937.3-189960.6" - wire width 2 $0\xer_ov$9[1:0]$13253 - attribute \src "libresoc.v:189961.3-189981.6" + attribute \src "libresoc.v:189896.3-189919.6" + wire width 2 $0\xer_ov$9[1:0]$12847 + attribute \src "libresoc.v:189920.3-189940.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:189895.3-189915.6" - wire $0\xer_so$8[0:0]$13247 - attribute \src "libresoc.v:189916.3-189936.6" + attribute \src "libresoc.v:189854.3-189874.6" + wire $0\xer_so$8[0:0]$12841 + attribute \src "libresoc.v:189875.3-189895.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:189802.3-189817.6" - wire width 64 $1\fast1$7[63:0]$13241 - attribute \src "libresoc.v:189879.3-189894.6" + attribute \src "libresoc.v:189757.3-189772.6" + wire width 64 $1\fast1$7[63:0]$12835 + attribute \src "libresoc.v:189838.3-189853.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:189837.3-189878.6" + attribute \src "libresoc.v:189792.3-189837.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:189837.3-189878.6" + attribute \src "libresoc.v:189792.3-189837.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:190027.3-190045.6" - wire width 64 $1\spr1$6[63:0]$13266 - attribute \src "libresoc.v:189818.3-189836.6" + attribute \src "libresoc.v:189986.3-190004.6" + wire width 64 $1\spr1$6[63:0]$12860 + attribute \src "libresoc.v:189773.3-189791.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:189982.3-190005.6" - wire width 2 $1\xer_ca$10[1:0]$13260 - attribute \src "libresoc.v:190006.3-190026.6" + attribute \src "libresoc.v:189941.3-189964.6" + wire width 2 $1\xer_ca$10[1:0]$12854 + attribute \src "libresoc.v:189965.3-189985.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:189937.3-189960.6" - wire width 2 $1\xer_ov$9[1:0]$13254 - attribute \src "libresoc.v:189961.3-189981.6" + attribute \src "libresoc.v:189896.3-189919.6" + wire width 2 $1\xer_ov$9[1:0]$12848 + attribute \src "libresoc.v:189920.3-189940.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:189895.3-189915.6" - wire $1\xer_so$8[0:0]$13248 - attribute \src "libresoc.v:189916.3-189936.6" + attribute \src "libresoc.v:189854.3-189874.6" + wire $1\xer_so$8[0:0]$12842 + attribute \src "libresoc.v:189875.3-189895.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:189802.3-189817.6" - wire width 64 $2\fast1$7[63:0]$13242 - attribute \src "libresoc.v:189879.3-189894.6" + attribute \src "libresoc.v:189757.3-189772.6" + wire width 64 $2\fast1$7[63:0]$12836 + attribute \src "libresoc.v:189838.3-189853.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:189837.3-189878.6" + attribute \src "libresoc.v:189792.3-189837.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:190027.3-190045.6" - wire width 64 $2\spr1$6[63:0]$13267 - attribute \src "libresoc.v:189818.3-189836.6" + attribute \src "libresoc.v:189986.3-190004.6" + wire width 64 $2\spr1$6[63:0]$12861 + attribute \src "libresoc.v:189773.3-189791.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:189982.3-190005.6" - wire width 2 $2\xer_ca$10[1:0]$13261 - attribute \src "libresoc.v:190006.3-190026.6" + attribute \src "libresoc.v:189941.3-189964.6" + wire width 2 $2\xer_ca$10[1:0]$12855 + attribute \src "libresoc.v:189965.3-189985.6" wire $2\xer_ca_ok[0:0] - attribute \src "libresoc.v:189937.3-189960.6" - wire width 2 $2\xer_ov$9[1:0]$13255 - attribute \src "libresoc.v:189961.3-189981.6" + attribute \src "libresoc.v:189896.3-189919.6" + wire width 2 $2\xer_ov$9[1:0]$12849 + attribute \src "libresoc.v:189920.3-189940.6" wire $2\xer_ov_ok[0:0] - attribute \src "libresoc.v:189895.3-189915.6" - wire $2\xer_so$8[0:0]$13249 - attribute \src "libresoc.v:189916.3-189936.6" + attribute \src "libresoc.v:189854.3-189874.6" + wire $2\xer_so$8[0:0]$12843 + attribute \src "libresoc.v:189875.3-189895.6" wire $2\xer_so_ok[0:0] - attribute \src "libresoc.v:189837.3-189878.6" + attribute \src "libresoc.v:189792.3-189837.6" wire width 46 $3\o[63:18] - attribute \src "libresoc.v:189982.3-190005.6" - wire width 2 $3\xer_ca$10[1:0]$13262 - attribute \src "libresoc.v:190006.3-190026.6" + attribute \src "libresoc.v:189941.3-189964.6" + wire width 2 $3\xer_ca$10[1:0]$12856 + attribute \src "libresoc.v:189965.3-189985.6" wire $3\xer_ca_ok[0:0] - attribute \src "libresoc.v:189937.3-189960.6" - wire width 2 $3\xer_ov$9[1:0]$13256 - attribute \src "libresoc.v:189961.3-189981.6" + attribute \src "libresoc.v:189896.3-189919.6" + wire width 2 $3\xer_ov$9[1:0]$12850 + attribute \src "libresoc.v:189920.3-189940.6" wire $3\xer_ov_ok[0:0] - attribute \src "libresoc.v:189895.3-189915.6" - wire $3\xer_so$8[0:0]$13250 - attribute \src "libresoc.v:189916.3-189936.6" + attribute \src "libresoc.v:189854.3-189874.6" + wire $3\xer_so$8[0:0]$12844 + attribute \src "libresoc.v:189875.3-189895.6" wire $3\xer_so_ok[0:0] - attribute \src "libresoc.v:189795.18-189795.106" - wire $eq$libresoc.v:189795$13232_Y - attribute \src "libresoc.v:189796.18-189796.106" - wire $eq$libresoc.v:189796$13233_Y - attribute \src "libresoc.v:189797.18-189797.106" - wire $eq$libresoc.v:189797$13234_Y - attribute \src "libresoc.v:189798.18-189798.106" - wire $eq$libresoc.v:189798$13235_Y - attribute \src "libresoc.v:189799.18-189799.106" - wire $eq$libresoc.v:189799$13236_Y - attribute \src "libresoc.v:189800.18-189800.106" - wire $eq$libresoc.v:189800$13237_Y - attribute \src "libresoc.v:189801.18-189801.106" - wire $eq$libresoc.v:189801$13238_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + attribute \src "libresoc.v:189750.18-189750.106" + wire $eq$libresoc.v:189750$12826_Y + attribute \src "libresoc.v:189751.18-189751.106" + wire $eq$libresoc.v:189751$12827_Y + attribute \src "libresoc.v:189752.18-189752.106" + wire $eq$libresoc.v:189752$12828_Y + attribute \src "libresoc.v:189753.18-189753.106" + wire $eq$libresoc.v:189753$12829_Y + attribute \src "libresoc.v:189754.18-189754.106" + wire $eq$libresoc.v:189754$12830_Y + attribute \src "libresoc.v:189755.18-189755.106" + wire $eq$libresoc.v:189755$12831_Y + attribute \src "libresoc.v:189756.18-189756.106" + wire $eq$libresoc.v:189756$12832_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 7 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 20 \fast1$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 21 \fast1_ok - attribute \src "libresoc.v:189530.7-189530.15" + attribute \src "libresoc.v:189485.7-189485.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 28 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 11 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 16 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 17 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 5 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:50" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 6 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 18 \spr1$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 19 \spr1_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -396357,24 +360330,24 @@ module \spr_main wire output 15 \spr_op__is_32bit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 10 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 26 \xer_ca$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 9 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 24 \xer_ov$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 8 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 22 \xer_so$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189795$13232 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" + cell $eq $eq$libresoc.v:189750$12826 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -396382,10 +360355,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189795$13232_Y + connect \Y $eq$libresoc.v:189750$12826_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189796$13233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" + cell $eq $eq$libresoc.v:189751$12827 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -396393,10 +360366,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189796$13233_Y + connect \Y $eq$libresoc.v:189751$12827_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189797$13234 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" + cell $eq $eq$libresoc.v:189752$12828 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -396404,10 +360377,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189797$13234_Y + connect \Y $eq$libresoc.v:189752$12828_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189798$13235 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" + cell $eq $eq$libresoc.v:189753$12829 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -396415,10 +360388,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189798$13235_Y + connect \Y $eq$libresoc.v:189753$12829_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189799$13236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" + cell $eq $eq$libresoc.v:189754$12830 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -396426,10 +360399,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189799$13236_Y + connect \Y $eq$libresoc.v:189754$12830_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189800$13237 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" + cell $eq $eq$libresoc.v:189755$12831 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -396437,10 +360410,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189800$13237_Y + connect \Y $eq$libresoc.v:189755$12831_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - cell $eq $eq$libresoc.v:189801$13238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" + cell $eq $eq$libresoc.v:189756$12832 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -396448,66 +360421,66 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189801$13238_Y + connect \Y $eq$libresoc.v:189756$12832_Y end - attribute \src "libresoc.v:189530.7-189530.20" - process $proc$libresoc.v:189530$13268 + attribute \src "libresoc.v:189485.7-189485.20" + process $proc$libresoc.v:189485$12862 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189802.3-189817.6" - process $proc$libresoc.v:189802$13239 + attribute \src "libresoc.v:189757.3-189772.6" + process $proc$libresoc.v:189757$12833 assign { } { } assign { } { } - assign $0\fast1$7[63:0]$13240 $1\fast1$7[63:0]$13241 - attribute \src "libresoc.v:189803.5-189803.29" + assign $0\fast1$7[63:0]$12834 $1\fast1$7[63:0]$12835 + attribute \src "libresoc.v:189758.5-189758.29" switch \initial - attribute \src "libresoc.v:189803.9-189803.17" + attribute \src "libresoc.v:189758.9-189758.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\fast1$7[63:0]$13241 $2\fast1$7[63:0]$13242 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + assign $1\fast1$7[63:0]$12835 $2\fast1$7[63:0]$12836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\fast1$7[63:0]$13242 \ra + assign $2\fast1$7[63:0]$12836 \ra case - assign $2\fast1$7[63:0]$13242 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$7[63:0]$12836 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\fast1$7[63:0]$13241 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$7[63:0]$12835 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$7 $0\fast1$7[63:0]$13240 + update \fast1$7 $0\fast1$7[63:0]$12834 end - attribute \src "libresoc.v:189818.3-189836.6" - process $proc$libresoc.v:189818$13243 + attribute \src "libresoc.v:189773.3-189791.6" + process $proc$libresoc.v:189773$12837 assign { } { } assign { } { } assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - attribute \src "libresoc.v:189819.5-189819.29" + attribute \src "libresoc.v:189774.5-189774.29" switch \initial - attribute \src "libresoc.v:189819.9-189819.17" + attribute \src "libresoc.v:189774.9-189774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 @@ -396523,36 +360496,40 @@ module \spr_main sync always update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:189837.3-189878.6" - process $proc$libresoc.v:189837$13244 + attribute \src "libresoc.v:189792.3-189837.6" + process $proc$libresoc.v:189792$12838 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:189838.5-189838.29" + attribute \src "libresoc.v:189793.5-189793.29" switch \initial - attribute \src "libresoc.v:189838.9-189838.17" + attribute \src "libresoc.v:189793.9-189793.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0101110 assign { } { } assign { } { } assign $1\o_ok[0:0] 1'1 assign $1\o[63:0] $2\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:85" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 , 10'0100001100 assign { } { } assign $2\o[63:0] [17:0] \fast1 [17:0] assign $2\o[63:0] [63:18] $3\o[63:18] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -396584,24 +360561,24 @@ module \spr_main update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:189879.3-189894.6" - process $proc$libresoc.v:189879$13245 + attribute \src "libresoc.v:189838.3-189853.6" + process $proc$libresoc.v:189838$12839 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:189880.5-189880.29" + attribute \src "libresoc.v:189839.5-189839.29" switch \initial - attribute \src "libresoc.v:189880.9-189880.17" + attribute \src "libresoc.v:189839.9-189839.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 @@ -396616,71 +360593,71 @@ module \spr_main sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:189895.3-189915.6" - process $proc$libresoc.v:189895$13246 + attribute \src "libresoc.v:189854.3-189874.6" + process $proc$libresoc.v:189854$12840 assign { } { } assign { } { } - assign $0\xer_so$8[0:0]$13247 $1\xer_so$8[0:0]$13248 - attribute \src "libresoc.v:189896.5-189896.29" + assign $0\xer_so$8[0:0]$12841 $1\xer_so$8[0:0]$12842 + attribute \src "libresoc.v:189855.5-189855.29" switch \initial - attribute \src "libresoc.v:189896.9-189896.17" + attribute \src "libresoc.v:189855.9-189855.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_so$8[0:0]$13248 $2\xer_so$8[0:0]$13249 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + assign $1\xer_so$8[0:0]$12842 $2\xer_so$8[0:0]$12843 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_so$8[0:0]$13249 $3\xer_so$8[0:0]$13250 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + assign $2\xer_so$8[0:0]$12843 $3\xer_so$8[0:0]$12844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_so$8[0:0]$13250 \ra [31] + assign $3\xer_so$8[0:0]$12844 \ra [31] case - assign $3\xer_so$8[0:0]$13250 1'0 + assign $3\xer_so$8[0:0]$12844 1'0 end case - assign $2\xer_so$8[0:0]$13249 1'0 + assign $2\xer_so$8[0:0]$12843 1'0 end case - assign $1\xer_so$8[0:0]$13248 1'0 + assign $1\xer_so$8[0:0]$12842 1'0 end sync always - update \xer_so$8 $0\xer_so$8[0:0]$13247 + update \xer_so$8 $0\xer_so$8[0:0]$12841 end - attribute \src "libresoc.v:189916.3-189936.6" - process $proc$libresoc.v:189916$13251 + attribute \src "libresoc.v:189875.3-189895.6" + process $proc$libresoc.v:189875$12845 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:189917.5-189917.29" + attribute \src "libresoc.v:189876.5-189876.29" switch \initial - attribute \src "libresoc.v:189917.9-189917.17" + attribute \src "libresoc.v:189876.9-189876.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\xer_so_ok[0:0] $2\xer_so_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } assign $2\xer_so_ok[0:0] $3\xer_so_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -396698,72 +360675,72 @@ module \spr_main sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:189937.3-189960.6" - process $proc$libresoc.v:189937$13252 + attribute \src "libresoc.v:189896.3-189919.6" + process $proc$libresoc.v:189896$12846 assign { } { } assign { } { } - assign $0\xer_ov$9[1:0]$13253 $1\xer_ov$9[1:0]$13254 - attribute \src "libresoc.v:189938.5-189938.29" + assign $0\xer_ov$9[1:0]$12847 $1\xer_ov$9[1:0]$12848 + attribute \src "libresoc.v:189897.5-189897.29" switch \initial - attribute \src "libresoc.v:189938.9-189938.17" + attribute \src "libresoc.v:189897.9-189897.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ov$9[1:0]$13254 $2\xer_ov$9[1:0]$13255 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + assign $1\xer_ov$9[1:0]$12848 $2\xer_ov$9[1:0]$12849 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ov$9[1:0]$13255 $3\xer_ov$9[1:0]$13256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + assign $2\xer_ov$9[1:0]$12849 $3\xer_ov$9[1:0]$12850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ov$9[1:0]$13256 [0] \ra [30] - assign $3\xer_ov$9[1:0]$13256 [1] \ra [19] + assign $3\xer_ov$9[1:0]$12850 [0] \ra [30] + assign $3\xer_ov$9[1:0]$12850 [1] \ra [19] case - assign $3\xer_ov$9[1:0]$13256 2'00 + assign $3\xer_ov$9[1:0]$12850 2'00 end case - assign $2\xer_ov$9[1:0]$13255 2'00 + assign $2\xer_ov$9[1:0]$12849 2'00 end case - assign $1\xer_ov$9[1:0]$13254 2'00 + assign $1\xer_ov$9[1:0]$12848 2'00 end sync always - update \xer_ov$9 $0\xer_ov$9[1:0]$13253 + update \xer_ov$9 $0\xer_ov$9[1:0]$12847 end - attribute \src "libresoc.v:189961.3-189981.6" - process $proc$libresoc.v:189961$13257 + attribute \src "libresoc.v:189920.3-189940.6" + process $proc$libresoc.v:189920$12851 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:189962.5-189962.29" + attribute \src "libresoc.v:189921.5-189921.29" switch \initial - attribute \src "libresoc.v:189962.9-189962.17" + attribute \src "libresoc.v:189921.9-189921.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\xer_ov_ok[0:0] $2\xer_ov_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } assign $2\xer_ov_ok[0:0] $3\xer_ov_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -396781,72 +360758,72 @@ module \spr_main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:189982.3-190005.6" - process $proc$libresoc.v:189982$13258 + attribute \src "libresoc.v:189941.3-189964.6" + process $proc$libresoc.v:189941$12852 assign { } { } assign { } { } - assign $0\xer_ca$10[1:0]$13259 $1\xer_ca$10[1:0]$13260 - attribute \src "libresoc.v:189983.5-189983.29" + assign $0\xer_ca$10[1:0]$12853 $1\xer_ca$10[1:0]$12854 + attribute \src "libresoc.v:189942.5-189942.29" switch \initial - attribute \src "libresoc.v:189983.9-189983.17" + attribute \src "libresoc.v:189942.9-189942.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ca$10[1:0]$13260 $2\xer_ca$10[1:0]$13261 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + assign $1\xer_ca$10[1:0]$12854 $2\xer_ca$10[1:0]$12855 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ca$10[1:0]$13261 $3\xer_ca$10[1:0]$13262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + assign $2\xer_ca$10[1:0]$12855 $3\xer_ca$10[1:0]$12856 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ca$10[1:0]$13262 [0] \ra [29] - assign $3\xer_ca$10[1:0]$13262 [1] \ra [18] + assign $3\xer_ca$10[1:0]$12856 [0] \ra [29] + assign $3\xer_ca$10[1:0]$12856 [1] \ra [18] case - assign $3\xer_ca$10[1:0]$13262 2'00 + assign $3\xer_ca$10[1:0]$12856 2'00 end case - assign $2\xer_ca$10[1:0]$13261 2'00 + assign $2\xer_ca$10[1:0]$12855 2'00 end case - assign $1\xer_ca$10[1:0]$13260 2'00 + assign $1\xer_ca$10[1:0]$12854 2'00 end sync always - update \xer_ca$10 $0\xer_ca$10[1:0]$13259 + update \xer_ca$10 $0\xer_ca$10[1:0]$12853 end - attribute \src "libresoc.v:190006.3-190026.6" - process $proc$libresoc.v:190006$13263 + attribute \src "libresoc.v:189965.3-189985.6" + process $proc$libresoc.v:189965$12857 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:190007.5-190007.29" + attribute \src "libresoc.v:189966.5-189966.29" switch \initial - attribute \src "libresoc.v:190007.9-190007.17" + attribute \src "libresoc.v:189966.9-189966.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\xer_ca_ok[0:0] $2\xer_ca_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } assign $2\xer_ca_ok[0:0] $3\xer_ca_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$21 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -396864,80 +360841,80 @@ module \spr_main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:190027.3-190045.6" - process $proc$libresoc.v:190027$13264 + attribute \src "libresoc.v:189986.3-190004.6" + process $proc$libresoc.v:189986$12858 assign { } { } assign { } { } - assign $0\spr1$6[63:0]$13265 $1\spr1$6[63:0]$13266 - attribute \src "libresoc.v:190028.5-190028.29" + assign $0\spr1$6[63:0]$12859 $1\spr1$6[63:0]$12860 + attribute \src "libresoc.v:189987.5-189987.29" switch \initial - attribute \src "libresoc.v:190028.9-190028.17" + attribute \src "libresoc.v:189987.9-189987.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\spr1$6[63:0]$13266 $2\spr1$6[63:0]$13267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + assign $1\spr1$6[63:0]$12860 $2\spr1$6[63:0]$12861 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign $2\spr1$6[63:0]$13267 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\spr1$6[63:0]$12861 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\spr1$6[63:0]$13267 \ra + assign $2\spr1$6[63:0]$12861 \ra end case - assign $1\spr1$6[63:0]$13266 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr1$6[63:0]$12860 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \spr1$6 $0\spr1$6[63:0]$13265 + update \spr1$6 $0\spr1$6[63:0]$12859 end - connect \$11 $eq$libresoc.v:189795$13232_Y - connect \$13 $eq$libresoc.v:189796$13233_Y - connect \$15 $eq$libresoc.v:189797$13234_Y - connect \$17 $eq$libresoc.v:189798$13235_Y - connect \$19 $eq$libresoc.v:189799$13236_Y - connect \$21 $eq$libresoc.v:189800$13237_Y - connect \$23 $eq$libresoc.v:189801$13238_Y + connect \$11 $eq$libresoc.v:189750$12826_Y + connect \$13 $eq$libresoc.v:189751$12827_Y + connect \$15 $eq$libresoc.v:189752$12828_Y + connect \$17 $eq$libresoc.v:189753$12829_Y + connect \$19 $eq$libresoc.v:189754$12830_Y + connect \$21 $eq$libresoc.v:189755$12831_Y + connect \$23 $eq$libresoc.v:189756$12832_Y connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \muxid$1 \muxid connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } end -attribute \src "libresoc.v:190053.1-190889.10" +attribute \src "libresoc.v:190012.1-191478.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" attribute \generator "nMigen" module \sprmap - attribute \src "libresoc.v:190183.3-190213.6" + attribute \src "libresoc.v:190142.3-190463.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:190214.3-190244.6" + attribute \src "libresoc.v:190464.3-190785.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:190054.7-190054.20" + attribute \src "libresoc.v:190013.7-190013.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190245.3-190566.6" + attribute \src "libresoc.v:190786.3-191131.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:190567.3-190888.6" + attribute \src "libresoc.v:191132.3-191477.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:190183.3-190213.6" + attribute \src "libresoc.v:190142.3-190463.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:190214.3-190244.6" + attribute \src "libresoc.v:190464.3-190785.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:190245.3-190566.6" + attribute \src "libresoc.v:190786.3-191131.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:190567.3-190888.6" + attribute \src "libresoc.v:191132.3-191477.6" wire $1\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 3 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \fast_o_ok - attribute \src "libresoc.v:190054.7-190054.15" + attribute \src "libresoc.v:190013.7-190013.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" wire width 10 input 5 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -397053,36 +361030,39 @@ module \sprmap attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 output 1 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \spr_o_ok - attribute \src "libresoc.v:190054.7-190054.20" - process $proc$libresoc.v:190054$13273 + attribute \src "libresoc.v:190013.7-190013.20" + process $proc$libresoc.v:190013$12867 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190183.3-190213.6" - process $proc$libresoc.v:190183$13269 + attribute \src "libresoc.v:190142.3-190463.6" + process $proc$libresoc.v:190142$12863 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:190184.5-190184.29" + attribute \src "libresoc.v:190143.5-190143.29" switch \initial - attribute \src "libresoc.v:190184.9-190184.17" + attribute \src "libresoc.v:190143.9-190143.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 assign { } { } assign $1\fast_o[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign { } { } assign $1\fast_o[2:0] 3'001 @@ -397091,6 +361071,18 @@ module \sprmap assign { } { } assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign { } { } assign $1\fast_o[2:0] 3'110 @@ -397103,10 +361095,286 @@ module \sprmap assign { } { } assign $1\fast_o[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign { } { } assign $1\fast_o[2:0] 3'111 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign { } { } assign $1\fast_o[2:0] 3'010 @@ -397116,24 +361384,27 @@ module \sprmap sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:190214.3-190244.6" - process $proc$libresoc.v:190214$13270 + attribute \src "libresoc.v:190464.3-190785.6" + process $proc$libresoc.v:190464$12864 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:190215.5-190215.29" + attribute \src "libresoc.v:190465.5-190465.29" switch \initial - attribute \src "libresoc.v:190215.9-190215.17" + attribute \src "libresoc.v:190465.9-190465.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign { } { } assign $1\fast_o_ok[0:0] 1'1 @@ -397142,6 +361413,18 @@ module \sprmap assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign { } { } assign $1\fast_o_ok[0:0] 1'1 @@ -397154,10 +361437,286 @@ module \sprmap assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign { } { } assign $1\fast_o_ok[0:0] 1'1 @@ -397167,24 +361726,33 @@ module \sprmap sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:190245.3-190566.6" - process $proc$libresoc.v:190245$13271 + attribute \src "libresoc.v:190786.3-191131.6" + process $proc$libresoc.v:190786$12865 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:190246.5-190246.29" + attribute \src "libresoc.v:190787.5-190787.29" switch \initial - attribute \src "libresoc.v:190246.9-190246.17" + attribute \src "libresoc.v:190787.9-190787.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign { } { } assign $1\spr_o[9:0] 10'0000000001 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign { } { } assign $1\spr_o[9:0] 10'0000000100 @@ -397201,6 +361769,15 @@ module \sprmap assign { } { } assign $1\spr_o[9:0] 10'0000000111 attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign { } { } assign $1\spr_o[9:0] 10'0000001011 @@ -397293,6 +361870,9 @@ module \sprmap assign { } { } assign $1\spr_o[9:0] 10'0000100001 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign { } { } assign $1\spr_o[9:0] 10'0000100011 @@ -397569,6 +362149,9 @@ module \sprmap assign { } { } assign $1\spr_o[9:0] 10'0001100111 attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'1100110000 assign { } { } assign $1\spr_o[9:0] 10'0001101001 @@ -397606,24 +362189,33 @@ module \sprmap sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:190567.3-190888.6" - process $proc$libresoc.v:190567$13272 + attribute \src "libresoc.v:191132.3-191477.6" + process $proc$libresoc.v:191132$12866 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:190568.5-190568.29" + attribute \src "libresoc.v:191133.5-191133.29" switch \initial - attribute \src "libresoc.v:190568.9-190568.17" + attribute \src "libresoc.v:191133.9-191133.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -397640,6 +362232,15 @@ module \sprmap assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -397732,6 +362333,9 @@ module \sprmap assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -398008,6 +362612,9 @@ module \sprmap assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'1100110000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -398046,36 +362653,36 @@ module \sprmap update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:190893.1-191729.10" +attribute \src "libresoc.v:191482.1-192948.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" attribute \generator "nMigen" module \sprmap$174 - attribute \src "libresoc.v:191023.3-191053.6" + attribute \src "libresoc.v:191612.3-191933.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:191054.3-191084.6" + attribute \src "libresoc.v:191934.3-192255.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:190894.7-190894.20" + attribute \src "libresoc.v:191483.7-191483.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191085.3-191406.6" + attribute \src "libresoc.v:192256.3-192601.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:191407.3-191728.6" + attribute \src "libresoc.v:192602.3-192947.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:191023.3-191053.6" + attribute \src "libresoc.v:191612.3-191933.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:191054.3-191084.6" + attribute \src "libresoc.v:191934.3-192255.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:191085.3-191406.6" + attribute \src "libresoc.v:192256.3-192601.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:191407.3-191728.6" + attribute \src "libresoc.v:192602.3-192947.6" wire $1\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 3 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \fast_o_ok - attribute \src "libresoc.v:190894.7-190894.15" + attribute \src "libresoc.v:191483.7-191483.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" wire width 10 input 5 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -398191,36 +362798,39 @@ module \sprmap$174 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 output 1 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \spr_o_ok - attribute \src "libresoc.v:190894.7-190894.20" - process $proc$libresoc.v:190894$13278 + attribute \src "libresoc.v:191483.7-191483.20" + process $proc$libresoc.v:191483$12872 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:191023.3-191053.6" - process $proc$libresoc.v:191023$13274 + attribute \src "libresoc.v:191612.3-191933.6" + process $proc$libresoc.v:191612$12868 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:191024.5-191024.29" + attribute \src "libresoc.v:191613.5-191613.29" switch \initial - attribute \src "libresoc.v:191024.9-191024.17" + attribute \src "libresoc.v:191613.9-191613.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 assign { } { } assign $1\fast_o[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign { } { } assign $1\fast_o[2:0] 3'001 @@ -398229,6 +362839,18 @@ module \sprmap$174 assign { } { } assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign { } { } assign $1\fast_o[2:0] 3'110 @@ -398241,10 +362863,286 @@ module \sprmap$174 assign { } { } assign $1\fast_o[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign { } { } assign $1\fast_o[2:0] 3'111 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign { } { } assign $1\fast_o[2:0] 3'010 @@ -398254,24 +363152,27 @@ module \sprmap$174 sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:191054.3-191084.6" - process $proc$libresoc.v:191054$13275 + attribute \src "libresoc.v:191934.3-192255.6" + process $proc$libresoc.v:191934$12869 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:191055.5-191055.29" + attribute \src "libresoc.v:191935.5-191935.29" switch \initial - attribute \src "libresoc.v:191055.9-191055.17" + attribute \src "libresoc.v:191935.9-191935.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign { } { } assign $1\fast_o_ok[0:0] 1'1 @@ -398280,6 +363181,18 @@ module \sprmap$174 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign { } { } assign $1\fast_o_ok[0:0] 1'1 @@ -398292,10 +363205,286 @@ module \sprmap$174 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign { } { } assign $1\fast_o_ok[0:0] 1'1 @@ -398305,24 +363494,33 @@ module \sprmap$174 sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:191085.3-191406.6" - process $proc$libresoc.v:191085$13276 + attribute \src "libresoc.v:192256.3-192601.6" + process $proc$libresoc.v:192256$12870 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:191086.5-191086.29" + attribute \src "libresoc.v:192257.5-192257.29" switch \initial - attribute \src "libresoc.v:191086.9-191086.17" + attribute \src "libresoc.v:192257.9-192257.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign { } { } assign $1\spr_o[9:0] 10'0000000001 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign { } { } assign $1\spr_o[9:0] 10'0000000100 @@ -398339,6 +363537,15 @@ module \sprmap$174 assign { } { } assign $1\spr_o[9:0] 10'0000000111 attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign { } { } assign $1\spr_o[9:0] 10'0000001011 @@ -398431,6 +363638,9 @@ module \sprmap$174 assign { } { } assign $1\spr_o[9:0] 10'0000100001 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign { } { } assign $1\spr_o[9:0] 10'0000100011 @@ -398707,6 +363917,9 @@ module \sprmap$174 assign { } { } assign $1\spr_o[9:0] 10'0001100111 attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'1100110000 assign { } { } assign $1\spr_o[9:0] 10'0001101001 @@ -398744,24 +363957,33 @@ module \sprmap$174 sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:191407.3-191728.6" - process $proc$libresoc.v:191407$13277 + attribute \src "libresoc.v:192602.3-192947.6" + process $proc$libresoc.v:192602$12871 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:191408.5-191408.29" + attribute \src "libresoc.v:192603.5-192603.29" switch \initial - attribute \src "libresoc.v:191408.9-191408.17" + attribute \src "libresoc.v:192603.9-192603.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -398778,6 +364000,15 @@ module \sprmap$174 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -398870,6 +364101,9 @@ module \sprmap$174 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -399146,6 +364380,9 @@ module \sprmap$174 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'1100110000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -399184,70 +364421,70 @@ module \sprmap$174 update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:191733.1-191873.10" +attribute \src "libresoc.v:192952.1-193092.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_0" attribute \generator "nMigen" module \sram4k_0 - attribute \src "libresoc.v:191808.3-191822.6" + attribute \src "libresoc.v:193027.3-193041.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:191838.3-191852.6" + attribute \src "libresoc.v:193057.3-193071.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:191734.7-191734.20" + attribute \src "libresoc.v:192953.7-192953.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191793.3-191807.6" - wire $0\sram4k_0_wb__ack$next[0:0]$13283 - attribute \src "libresoc.v:191774.3-191775.49" + attribute \src "libresoc.v:193012.3-193026.6" + wire $0\sram4k_0_wb__ack$next[0:0]$12877 + attribute \src "libresoc.v:192993.3-192994.49" wire $0\sram4k_0_wb__ack[0:0] - attribute \src "libresoc.v:191823.3-191837.6" + attribute \src "libresoc.v:193042.3-193056.6" wire width 64 $0\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:191783.3-191792.6" + attribute \src "libresoc.v:193002.3-193011.6" wire $0\wb_active[0:0] - attribute \src "libresoc.v:191853.3-191872.6" + attribute \src "libresoc.v:193072.3-193091.6" wire $0\we[0:0] - attribute \src "libresoc.v:191808.3-191822.6" + attribute \src "libresoc.v:193027.3-193041.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:191838.3-191852.6" + attribute \src "libresoc.v:193057.3-193071.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:191793.3-191807.6" - wire $1\sram4k_0_wb__ack$next[0:0]$13284 - attribute \src "libresoc.v:191751.7-191751.30" + attribute \src "libresoc.v:193012.3-193026.6" + wire $1\sram4k_0_wb__ack$next[0:0]$12878 + attribute \src "libresoc.v:192970.7-192970.30" wire $1\sram4k_0_wb__ack[0:0] - attribute \src "libresoc.v:191823.3-191837.6" + attribute \src "libresoc.v:193042.3-193056.6" wire width 64 $1\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:191783.3-191792.6" + attribute \src "libresoc.v:193002.3-193011.6" wire $1\wb_active[0:0] - attribute \src "libresoc.v:191853.3-191872.6" + attribute \src "libresoc.v:193072.3-193091.6" wire $1\we[0:0] - attribute \src "libresoc.v:191808.3-191822.6" + attribute \src "libresoc.v:193027.3-193041.6" wire width 9 $2\a[8:0] - attribute \src "libresoc.v:191838.3-191852.6" + attribute \src "libresoc.v:193057.3-193071.6" wire width 64 $2\d[63:0] - attribute \src "libresoc.v:191793.3-191807.6" - wire $2\sram4k_0_wb__ack$next[0:0]$13285 - attribute \src "libresoc.v:191823.3-191837.6" + attribute \src "libresoc.v:193012.3-193026.6" + wire $2\sram4k_0_wb__ack$next[0:0]$12879 + attribute \src "libresoc.v:193042.3-193056.6" wire width 64 $2\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:191853.3-191872.6" + attribute \src "libresoc.v:193072.3-193091.6" wire $2\we[0:0] - attribute \src "libresoc.v:191853.3-191872.6" + attribute \src "libresoc.v:193072.3-193091.6" wire $3\we[0:0] - attribute \src "libresoc.v:191773.17-191773.129" - wire $and$libresoc.v:191773$13279_Y + attribute \src "libresoc.v:192992.17-192992.129" + wire $and$libresoc.v:192992$12873_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 11 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire input 2 \enable - attribute \src "libresoc.v:191734.7-191734.15" + attribute \src "libresoc.v:192953.7-192953.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" wire output 5 \sram4k_0_wb__ack @@ -399272,7 +364509,7 @@ module \sram4k_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:191773$13279 + cell $and $and$libresoc.v:192992$12873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399280,10 +364517,10 @@ module \sram4k_0 parameter \Y_WIDTH 1 connect \A \sram4k_0_wb__cyc connect \B \sram4k_0_wb__stb - connect \Y $and$libresoc.v:191773$13279_Y + connect \Y $and$libresoc.v:192992$12873_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:191776.21-191782.4" + attribute \src "libresoc.v:192995.21-193001.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -399291,37 +364528,37 @@ module \sram4k_0 connect \q \q connect \we \we end - attribute \src "libresoc.v:191734.7-191734.20" - process $proc$libresoc.v:191734$13290 + attribute \src "libresoc.v:192953.7-192953.20" + process $proc$libresoc.v:192953$12884 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:191751.7-191751.30" - process $proc$libresoc.v:191751$13291 + attribute \src "libresoc.v:192970.7-192970.30" + process $proc$libresoc.v:192970$12885 assign { } { } assign $1\sram4k_0_wb__ack[0:0] 1'0 sync always sync init update \sram4k_0_wb__ack $1\sram4k_0_wb__ack[0:0] end - attribute \src "libresoc.v:191774.3-191775.49" - process $proc$libresoc.v:191774$13280 + attribute \src "libresoc.v:192993.3-192994.49" + process $proc$libresoc.v:192993$12874 assign { } { } assign $0\sram4k_0_wb__ack[0:0] \sram4k_0_wb__ack$next sync posedge \clk update \sram4k_0_wb__ack $0\sram4k_0_wb__ack[0:0] end - attribute \src "libresoc.v:191783.3-191792.6" - process $proc$libresoc.v:191783$13281 + attribute \src "libresoc.v:193002.3-193011.6" + process $proc$libresoc.v:193002$12875 assign { } { } assign { } { } assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:191784.5-191784.29" + attribute \src "libresoc.v:193003.5-193003.29" switch \initial - attribute \src "libresoc.v:191784.9-191784.17" + attribute \src "libresoc.v:193003.9-193003.17" case 1'1 case end @@ -399337,15 +364574,15 @@ module \sram4k_0 sync always update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:191793.3-191807.6" - process $proc$libresoc.v:191793$13282 + attribute \src "libresoc.v:193012.3-193026.6" + process $proc$libresoc.v:193012$12876 assign { } { } assign { } { } assign { } { } - assign $0\sram4k_0_wb__ack$next[0:0]$13283 $2\sram4k_0_wb__ack$next[0:0]$13285 - attribute \src "libresoc.v:191794.5-191794.29" + assign $0\sram4k_0_wb__ack$next[0:0]$12877 $2\sram4k_0_wb__ack$next[0:0]$12879 + attribute \src "libresoc.v:193013.5-193013.29" switch \initial - attribute \src "libresoc.v:191794.9-191794.17" + attribute \src "libresoc.v:193013.9-193013.17" case 1'1 case end @@ -399354,30 +364591,30 @@ module \sram4k_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_0_wb__ack$next[0:0]$13284 \wb_active + assign $1\sram4k_0_wb__ack$next[0:0]$12878 \wb_active case - assign $1\sram4k_0_wb__ack$next[0:0]$13284 \sram4k_0_wb__ack + assign $1\sram4k_0_wb__ack$next[0:0]$12878 \sram4k_0_wb__ack end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_0_wb__ack$next[0:0]$13285 1'0 + assign $2\sram4k_0_wb__ack$next[0:0]$12879 1'0 case - assign $2\sram4k_0_wb__ack$next[0:0]$13285 $1\sram4k_0_wb__ack$next[0:0]$13284 + assign $2\sram4k_0_wb__ack$next[0:0]$12879 $1\sram4k_0_wb__ack$next[0:0]$12878 end sync always - update \sram4k_0_wb__ack$next $0\sram4k_0_wb__ack$next[0:0]$13283 + update \sram4k_0_wb__ack$next $0\sram4k_0_wb__ack$next[0:0]$12877 end - attribute \src "libresoc.v:191808.3-191822.6" - process $proc$libresoc.v:191808$13286 + attribute \src "libresoc.v:193027.3-193041.6" + process $proc$libresoc.v:193027$12880 assign { } { } assign { } { } assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:191809.5-191809.29" + attribute \src "libresoc.v:193028.5-193028.29" switch \initial - attribute \src "libresoc.v:191809.9-191809.17" + attribute \src "libresoc.v:193028.9-193028.17" case 1'1 case end @@ -399402,14 +364639,14 @@ module \sram4k_0 sync always update \a $0\a[8:0] end - attribute \src "libresoc.v:191823.3-191837.6" - process $proc$libresoc.v:191823$13287 + attribute \src "libresoc.v:193042.3-193056.6" + process $proc$libresoc.v:193042$12881 assign { } { } assign { } { } assign $0\sram4k_0_wb__dat_r[63:0] $1\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:191824.5-191824.29" + attribute \src "libresoc.v:193043.5-193043.29" switch \initial - attribute \src "libresoc.v:191824.9-191824.17" + attribute \src "libresoc.v:193043.9-193043.17" case 1'1 case end @@ -399434,14 +364671,14 @@ module \sram4k_0 sync always update \sram4k_0_wb__dat_r $0\sram4k_0_wb__dat_r[63:0] end - attribute \src "libresoc.v:191838.3-191852.6" - process $proc$libresoc.v:191838$13288 + attribute \src "libresoc.v:193057.3-193071.6" + process $proc$libresoc.v:193057$12882 assign { } { } assign { } { } assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:191839.5-191839.29" + attribute \src "libresoc.v:193058.5-193058.29" switch \initial - attribute \src "libresoc.v:191839.9-191839.17" + attribute \src "libresoc.v:193058.9-193058.17" case 1'1 case end @@ -399466,14 +364703,14 @@ module \sram4k_0 sync always update \d $0\d[63:0] end - attribute \src "libresoc.v:191853.3-191872.6" - process $proc$libresoc.v:191853$13289 + attribute \src "libresoc.v:193072.3-193091.6" + process $proc$libresoc.v:193072$12883 assign { } { } assign { } { } assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:191854.5-191854.29" + attribute \src "libresoc.v:193073.5-193073.29" switch \initial - attribute \src "libresoc.v:191854.9-191854.17" + attribute \src "libresoc.v:193073.9-193073.17" case 1'1 case end @@ -399507,72 +364744,72 @@ module \sram4k_0 sync always update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:191773$13279_Y + connect \$1 $and$libresoc.v:192992$12873_Y end -attribute \src "libresoc.v:191877.1-192017.10" +attribute \src "libresoc.v:193096.1-193236.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_1" attribute \generator "nMigen" module \sram4k_1 - attribute \src "libresoc.v:191952.3-191966.6" + attribute \src "libresoc.v:193171.3-193185.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:191982.3-191996.6" + attribute \src "libresoc.v:193201.3-193215.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:191878.7-191878.20" + attribute \src "libresoc.v:193097.7-193097.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191937.3-191951.6" - wire $0\sram4k_1_wb__ack$next[0:0]$13296 - attribute \src "libresoc.v:191918.3-191919.49" + attribute \src "libresoc.v:193156.3-193170.6" + wire $0\sram4k_1_wb__ack$next[0:0]$12890 + attribute \src "libresoc.v:193137.3-193138.49" wire $0\sram4k_1_wb__ack[0:0] - attribute \src "libresoc.v:191967.3-191981.6" + attribute \src "libresoc.v:193186.3-193200.6" wire width 64 $0\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:191927.3-191936.6" + attribute \src "libresoc.v:193146.3-193155.6" wire $0\wb_active[0:0] - attribute \src "libresoc.v:191997.3-192016.6" + attribute \src "libresoc.v:193216.3-193235.6" wire $0\we[0:0] - attribute \src "libresoc.v:191952.3-191966.6" + attribute \src "libresoc.v:193171.3-193185.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:191982.3-191996.6" + attribute \src "libresoc.v:193201.3-193215.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:191937.3-191951.6" - wire $1\sram4k_1_wb__ack$next[0:0]$13297 - attribute \src "libresoc.v:191895.7-191895.30" + attribute \src "libresoc.v:193156.3-193170.6" + wire $1\sram4k_1_wb__ack$next[0:0]$12891 + attribute \src "libresoc.v:193114.7-193114.30" wire $1\sram4k_1_wb__ack[0:0] - attribute \src "libresoc.v:191967.3-191981.6" + attribute \src "libresoc.v:193186.3-193200.6" wire width 64 $1\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:191927.3-191936.6" + attribute \src "libresoc.v:193146.3-193155.6" wire $1\wb_active[0:0] - attribute \src "libresoc.v:191997.3-192016.6" + attribute \src "libresoc.v:193216.3-193235.6" wire $1\we[0:0] - attribute \src "libresoc.v:191952.3-191966.6" + attribute \src "libresoc.v:193171.3-193185.6" wire width 9 $2\a[8:0] - attribute \src "libresoc.v:191982.3-191996.6" + attribute \src "libresoc.v:193201.3-193215.6" wire width 64 $2\d[63:0] - attribute \src "libresoc.v:191937.3-191951.6" - wire $2\sram4k_1_wb__ack$next[0:0]$13298 - attribute \src "libresoc.v:191967.3-191981.6" + attribute \src "libresoc.v:193156.3-193170.6" + wire $2\sram4k_1_wb__ack$next[0:0]$12892 + attribute \src "libresoc.v:193186.3-193200.6" wire width 64 $2\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:191997.3-192016.6" + attribute \src "libresoc.v:193216.3-193235.6" wire $2\we[0:0] - attribute \src "libresoc.v:191997.3-192016.6" + attribute \src "libresoc.v:193216.3-193235.6" wire $3\we[0:0] - attribute \src "libresoc.v:191917.17-191917.129" - wire $and$libresoc.v:191917$13292_Y + attribute \src "libresoc.v:193136.17-193136.129" + wire $and$libresoc.v:193136$12886_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 11 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire input 2 \enable - attribute \src "libresoc.v:191878.7-191878.15" + attribute \src "libresoc.v:193097.7-193097.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" wire output 5 \sram4k_1_wb__ack @@ -399597,7 +364834,7 @@ module \sram4k_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:191917$13292 + cell $and $and$libresoc.v:193136$12886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399605,10 +364842,10 @@ module \sram4k_1 parameter \Y_WIDTH 1 connect \A \sram4k_1_wb__cyc connect \B \sram4k_1_wb__stb - connect \Y $and$libresoc.v:191917$13292_Y + connect \Y $and$libresoc.v:193136$12886_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:191920.21-191926.4" + attribute \src "libresoc.v:193139.21-193145.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -399616,37 +364853,37 @@ module \sram4k_1 connect \q \q connect \we \we end - attribute \src "libresoc.v:191878.7-191878.20" - process $proc$libresoc.v:191878$13303 + attribute \src "libresoc.v:193097.7-193097.20" + process $proc$libresoc.v:193097$12897 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:191895.7-191895.30" - process $proc$libresoc.v:191895$13304 + attribute \src "libresoc.v:193114.7-193114.30" + process $proc$libresoc.v:193114$12898 assign { } { } assign $1\sram4k_1_wb__ack[0:0] 1'0 sync always sync init update \sram4k_1_wb__ack $1\sram4k_1_wb__ack[0:0] end - attribute \src "libresoc.v:191918.3-191919.49" - process $proc$libresoc.v:191918$13293 + attribute \src "libresoc.v:193137.3-193138.49" + process $proc$libresoc.v:193137$12887 assign { } { } assign $0\sram4k_1_wb__ack[0:0] \sram4k_1_wb__ack$next sync posedge \clk update \sram4k_1_wb__ack $0\sram4k_1_wb__ack[0:0] end - attribute \src "libresoc.v:191927.3-191936.6" - process $proc$libresoc.v:191927$13294 + attribute \src "libresoc.v:193146.3-193155.6" + process $proc$libresoc.v:193146$12888 assign { } { } assign { } { } assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:191928.5-191928.29" + attribute \src "libresoc.v:193147.5-193147.29" switch \initial - attribute \src "libresoc.v:191928.9-191928.17" + attribute \src "libresoc.v:193147.9-193147.17" case 1'1 case end @@ -399662,15 +364899,15 @@ module \sram4k_1 sync always update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:191937.3-191951.6" - process $proc$libresoc.v:191937$13295 + attribute \src "libresoc.v:193156.3-193170.6" + process $proc$libresoc.v:193156$12889 assign { } { } assign { } { } assign { } { } - assign $0\sram4k_1_wb__ack$next[0:0]$13296 $2\sram4k_1_wb__ack$next[0:0]$13298 - attribute \src "libresoc.v:191938.5-191938.29" + assign $0\sram4k_1_wb__ack$next[0:0]$12890 $2\sram4k_1_wb__ack$next[0:0]$12892 + attribute \src "libresoc.v:193157.5-193157.29" switch \initial - attribute \src "libresoc.v:191938.9-191938.17" + attribute \src "libresoc.v:193157.9-193157.17" case 1'1 case end @@ -399679,30 +364916,30 @@ module \sram4k_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_1_wb__ack$next[0:0]$13297 \wb_active + assign $1\sram4k_1_wb__ack$next[0:0]$12891 \wb_active case - assign $1\sram4k_1_wb__ack$next[0:0]$13297 \sram4k_1_wb__ack + assign $1\sram4k_1_wb__ack$next[0:0]$12891 \sram4k_1_wb__ack end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_1_wb__ack$next[0:0]$13298 1'0 + assign $2\sram4k_1_wb__ack$next[0:0]$12892 1'0 case - assign $2\sram4k_1_wb__ack$next[0:0]$13298 $1\sram4k_1_wb__ack$next[0:0]$13297 + assign $2\sram4k_1_wb__ack$next[0:0]$12892 $1\sram4k_1_wb__ack$next[0:0]$12891 end sync always - update \sram4k_1_wb__ack$next $0\sram4k_1_wb__ack$next[0:0]$13296 + update \sram4k_1_wb__ack$next $0\sram4k_1_wb__ack$next[0:0]$12890 end - attribute \src "libresoc.v:191952.3-191966.6" - process $proc$libresoc.v:191952$13299 + attribute \src "libresoc.v:193171.3-193185.6" + process $proc$libresoc.v:193171$12893 assign { } { } assign { } { } assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:191953.5-191953.29" + attribute \src "libresoc.v:193172.5-193172.29" switch \initial - attribute \src "libresoc.v:191953.9-191953.17" + attribute \src "libresoc.v:193172.9-193172.17" case 1'1 case end @@ -399727,14 +364964,14 @@ module \sram4k_1 sync always update \a $0\a[8:0] end - attribute \src "libresoc.v:191967.3-191981.6" - process $proc$libresoc.v:191967$13300 + attribute \src "libresoc.v:193186.3-193200.6" + process $proc$libresoc.v:193186$12894 assign { } { } assign { } { } assign $0\sram4k_1_wb__dat_r[63:0] $1\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:191968.5-191968.29" + attribute \src "libresoc.v:193187.5-193187.29" switch \initial - attribute \src "libresoc.v:191968.9-191968.17" + attribute \src "libresoc.v:193187.9-193187.17" case 1'1 case end @@ -399759,14 +364996,14 @@ module \sram4k_1 sync always update \sram4k_1_wb__dat_r $0\sram4k_1_wb__dat_r[63:0] end - attribute \src "libresoc.v:191982.3-191996.6" - process $proc$libresoc.v:191982$13301 + attribute \src "libresoc.v:193201.3-193215.6" + process $proc$libresoc.v:193201$12895 assign { } { } assign { } { } assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:191983.5-191983.29" + attribute \src "libresoc.v:193202.5-193202.29" switch \initial - attribute \src "libresoc.v:191983.9-191983.17" + attribute \src "libresoc.v:193202.9-193202.17" case 1'1 case end @@ -399791,14 +365028,14 @@ module \sram4k_1 sync always update \d $0\d[63:0] end - attribute \src "libresoc.v:191997.3-192016.6" - process $proc$libresoc.v:191997$13302 + attribute \src "libresoc.v:193216.3-193235.6" + process $proc$libresoc.v:193216$12896 assign { } { } assign { } { } assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:191998.5-191998.29" + attribute \src "libresoc.v:193217.5-193217.29" switch \initial - attribute \src "libresoc.v:191998.9-191998.17" + attribute \src "libresoc.v:193217.9-193217.17" case 1'1 case end @@ -399832,72 +365069,72 @@ module \sram4k_1 sync always update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:191917$13292_Y + connect \$1 $and$libresoc.v:193136$12886_Y end -attribute \src "libresoc.v:192021.1-192161.10" +attribute \src "libresoc.v:193240.1-193380.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_2" attribute \generator "nMigen" module \sram4k_2 - attribute \src "libresoc.v:192096.3-192110.6" + attribute \src "libresoc.v:193315.3-193329.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:192126.3-192140.6" + attribute \src "libresoc.v:193345.3-193359.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:192022.7-192022.20" + attribute \src "libresoc.v:193241.7-193241.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192081.3-192095.6" - wire $0\sram4k_2_wb__ack$next[0:0]$13309 - attribute \src "libresoc.v:192062.3-192063.49" + attribute \src "libresoc.v:193300.3-193314.6" + wire $0\sram4k_2_wb__ack$next[0:0]$12903 + attribute \src "libresoc.v:193281.3-193282.49" wire $0\sram4k_2_wb__ack[0:0] - attribute \src "libresoc.v:192111.3-192125.6" + attribute \src "libresoc.v:193330.3-193344.6" wire width 64 $0\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:192071.3-192080.6" + attribute \src "libresoc.v:193290.3-193299.6" wire $0\wb_active[0:0] - attribute \src "libresoc.v:192141.3-192160.6" + attribute \src "libresoc.v:193360.3-193379.6" wire $0\we[0:0] - attribute \src "libresoc.v:192096.3-192110.6" + attribute \src "libresoc.v:193315.3-193329.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:192126.3-192140.6" + attribute \src "libresoc.v:193345.3-193359.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:192081.3-192095.6" - wire $1\sram4k_2_wb__ack$next[0:0]$13310 - attribute \src "libresoc.v:192039.7-192039.30" + attribute \src "libresoc.v:193300.3-193314.6" + wire $1\sram4k_2_wb__ack$next[0:0]$12904 + attribute \src "libresoc.v:193258.7-193258.30" wire $1\sram4k_2_wb__ack[0:0] - attribute \src "libresoc.v:192111.3-192125.6" + attribute \src "libresoc.v:193330.3-193344.6" wire width 64 $1\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:192071.3-192080.6" + attribute \src "libresoc.v:193290.3-193299.6" wire $1\wb_active[0:0] - attribute \src "libresoc.v:192141.3-192160.6" + attribute \src "libresoc.v:193360.3-193379.6" wire $1\we[0:0] - attribute \src "libresoc.v:192096.3-192110.6" + attribute \src "libresoc.v:193315.3-193329.6" wire width 9 $2\a[8:0] - attribute \src "libresoc.v:192126.3-192140.6" + attribute \src "libresoc.v:193345.3-193359.6" wire width 64 $2\d[63:0] - attribute \src "libresoc.v:192081.3-192095.6" - wire $2\sram4k_2_wb__ack$next[0:0]$13311 - attribute \src "libresoc.v:192111.3-192125.6" + attribute \src "libresoc.v:193300.3-193314.6" + wire $2\sram4k_2_wb__ack$next[0:0]$12905 + attribute \src "libresoc.v:193330.3-193344.6" wire width 64 $2\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:192141.3-192160.6" + attribute \src "libresoc.v:193360.3-193379.6" wire $2\we[0:0] - attribute \src "libresoc.v:192141.3-192160.6" + attribute \src "libresoc.v:193360.3-193379.6" wire $3\we[0:0] - attribute \src "libresoc.v:192061.17-192061.129" - wire $and$libresoc.v:192061$13305_Y + attribute \src "libresoc.v:193280.17-193280.129" + wire $and$libresoc.v:193280$12899_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 11 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire input 2 \enable - attribute \src "libresoc.v:192022.7-192022.15" + attribute \src "libresoc.v:193241.7-193241.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" wire output 5 \sram4k_2_wb__ack @@ -399922,7 +365159,7 @@ module \sram4k_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:192061$13305 + cell $and $and$libresoc.v:193280$12899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399930,10 +365167,10 @@ module \sram4k_2 parameter \Y_WIDTH 1 connect \A \sram4k_2_wb__cyc connect \B \sram4k_2_wb__stb - connect \Y $and$libresoc.v:192061$13305_Y + connect \Y $and$libresoc.v:193280$12899_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:192064.21-192070.4" + attribute \src "libresoc.v:193283.21-193289.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -399941,37 +365178,37 @@ module \sram4k_2 connect \q \q connect \we \we end - attribute \src "libresoc.v:192022.7-192022.20" - process $proc$libresoc.v:192022$13316 + attribute \src "libresoc.v:193241.7-193241.20" + process $proc$libresoc.v:193241$12910 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192039.7-192039.30" - process $proc$libresoc.v:192039$13317 + attribute \src "libresoc.v:193258.7-193258.30" + process $proc$libresoc.v:193258$12911 assign { } { } assign $1\sram4k_2_wb__ack[0:0] 1'0 sync always sync init update \sram4k_2_wb__ack $1\sram4k_2_wb__ack[0:0] end - attribute \src "libresoc.v:192062.3-192063.49" - process $proc$libresoc.v:192062$13306 + attribute \src "libresoc.v:193281.3-193282.49" + process $proc$libresoc.v:193281$12900 assign { } { } assign $0\sram4k_2_wb__ack[0:0] \sram4k_2_wb__ack$next sync posedge \clk update \sram4k_2_wb__ack $0\sram4k_2_wb__ack[0:0] end - attribute \src "libresoc.v:192071.3-192080.6" - process $proc$libresoc.v:192071$13307 + attribute \src "libresoc.v:193290.3-193299.6" + process $proc$libresoc.v:193290$12901 assign { } { } assign { } { } assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:192072.5-192072.29" + attribute \src "libresoc.v:193291.5-193291.29" switch \initial - attribute \src "libresoc.v:192072.9-192072.17" + attribute \src "libresoc.v:193291.9-193291.17" case 1'1 case end @@ -399987,15 +365224,15 @@ module \sram4k_2 sync always update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:192081.3-192095.6" - process $proc$libresoc.v:192081$13308 + attribute \src "libresoc.v:193300.3-193314.6" + process $proc$libresoc.v:193300$12902 assign { } { } assign { } { } assign { } { } - assign $0\sram4k_2_wb__ack$next[0:0]$13309 $2\sram4k_2_wb__ack$next[0:0]$13311 - attribute \src "libresoc.v:192082.5-192082.29" + assign $0\sram4k_2_wb__ack$next[0:0]$12903 $2\sram4k_2_wb__ack$next[0:0]$12905 + attribute \src "libresoc.v:193301.5-193301.29" switch \initial - attribute \src "libresoc.v:192082.9-192082.17" + attribute \src "libresoc.v:193301.9-193301.17" case 1'1 case end @@ -400004,30 +365241,30 @@ module \sram4k_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_2_wb__ack$next[0:0]$13310 \wb_active + assign $1\sram4k_2_wb__ack$next[0:0]$12904 \wb_active case - assign $1\sram4k_2_wb__ack$next[0:0]$13310 \sram4k_2_wb__ack + assign $1\sram4k_2_wb__ack$next[0:0]$12904 \sram4k_2_wb__ack end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_2_wb__ack$next[0:0]$13311 1'0 + assign $2\sram4k_2_wb__ack$next[0:0]$12905 1'0 case - assign $2\sram4k_2_wb__ack$next[0:0]$13311 $1\sram4k_2_wb__ack$next[0:0]$13310 + assign $2\sram4k_2_wb__ack$next[0:0]$12905 $1\sram4k_2_wb__ack$next[0:0]$12904 end sync always - update \sram4k_2_wb__ack$next $0\sram4k_2_wb__ack$next[0:0]$13309 + update \sram4k_2_wb__ack$next $0\sram4k_2_wb__ack$next[0:0]$12903 end - attribute \src "libresoc.v:192096.3-192110.6" - process $proc$libresoc.v:192096$13312 + attribute \src "libresoc.v:193315.3-193329.6" + process $proc$libresoc.v:193315$12906 assign { } { } assign { } { } assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:192097.5-192097.29" + attribute \src "libresoc.v:193316.5-193316.29" switch \initial - attribute \src "libresoc.v:192097.9-192097.17" + attribute \src "libresoc.v:193316.9-193316.17" case 1'1 case end @@ -400052,14 +365289,14 @@ module \sram4k_2 sync always update \a $0\a[8:0] end - attribute \src "libresoc.v:192111.3-192125.6" - process $proc$libresoc.v:192111$13313 + attribute \src "libresoc.v:193330.3-193344.6" + process $proc$libresoc.v:193330$12907 assign { } { } assign { } { } assign $0\sram4k_2_wb__dat_r[63:0] $1\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:192112.5-192112.29" + attribute \src "libresoc.v:193331.5-193331.29" switch \initial - attribute \src "libresoc.v:192112.9-192112.17" + attribute \src "libresoc.v:193331.9-193331.17" case 1'1 case end @@ -400084,14 +365321,14 @@ module \sram4k_2 sync always update \sram4k_2_wb__dat_r $0\sram4k_2_wb__dat_r[63:0] end - attribute \src "libresoc.v:192126.3-192140.6" - process $proc$libresoc.v:192126$13314 + attribute \src "libresoc.v:193345.3-193359.6" + process $proc$libresoc.v:193345$12908 assign { } { } assign { } { } assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:192127.5-192127.29" + attribute \src "libresoc.v:193346.5-193346.29" switch \initial - attribute \src "libresoc.v:192127.9-192127.17" + attribute \src "libresoc.v:193346.9-193346.17" case 1'1 case end @@ -400116,14 +365353,14 @@ module \sram4k_2 sync always update \d $0\d[63:0] end - attribute \src "libresoc.v:192141.3-192160.6" - process $proc$libresoc.v:192141$13315 + attribute \src "libresoc.v:193360.3-193379.6" + process $proc$libresoc.v:193360$12909 assign { } { } assign { } { } assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:192142.5-192142.29" + attribute \src "libresoc.v:193361.5-193361.29" switch \initial - attribute \src "libresoc.v:192142.9-192142.17" + attribute \src "libresoc.v:193361.9-193361.17" case 1'1 case end @@ -400157,72 +365394,72 @@ module \sram4k_2 sync always update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:192061$13305_Y + connect \$1 $and$libresoc.v:193280$12899_Y end -attribute \src "libresoc.v:192165.1-192305.10" +attribute \src "libresoc.v:193384.1-193524.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_3" attribute \generator "nMigen" module \sram4k_3 - attribute \src "libresoc.v:192240.3-192254.6" + attribute \src "libresoc.v:193459.3-193473.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:192270.3-192284.6" + attribute \src "libresoc.v:193489.3-193503.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:192166.7-192166.20" + attribute \src "libresoc.v:193385.7-193385.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192225.3-192239.6" - wire $0\sram4k_3_wb__ack$next[0:0]$13322 - attribute \src "libresoc.v:192206.3-192207.49" + attribute \src "libresoc.v:193444.3-193458.6" + wire $0\sram4k_3_wb__ack$next[0:0]$12916 + attribute \src "libresoc.v:193425.3-193426.49" wire $0\sram4k_3_wb__ack[0:0] - attribute \src "libresoc.v:192255.3-192269.6" + attribute \src "libresoc.v:193474.3-193488.6" wire width 64 $0\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:192215.3-192224.6" + attribute \src "libresoc.v:193434.3-193443.6" wire $0\wb_active[0:0] - attribute \src "libresoc.v:192285.3-192304.6" + attribute \src "libresoc.v:193504.3-193523.6" wire $0\we[0:0] - attribute \src "libresoc.v:192240.3-192254.6" + attribute \src "libresoc.v:193459.3-193473.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:192270.3-192284.6" + attribute \src "libresoc.v:193489.3-193503.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:192225.3-192239.6" - wire $1\sram4k_3_wb__ack$next[0:0]$13323 - attribute \src "libresoc.v:192183.7-192183.30" + attribute \src "libresoc.v:193444.3-193458.6" + wire $1\sram4k_3_wb__ack$next[0:0]$12917 + attribute \src "libresoc.v:193402.7-193402.30" wire $1\sram4k_3_wb__ack[0:0] - attribute \src "libresoc.v:192255.3-192269.6" + attribute \src "libresoc.v:193474.3-193488.6" wire width 64 $1\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:192215.3-192224.6" + attribute \src "libresoc.v:193434.3-193443.6" wire $1\wb_active[0:0] - attribute \src "libresoc.v:192285.3-192304.6" + attribute \src "libresoc.v:193504.3-193523.6" wire $1\we[0:0] - attribute \src "libresoc.v:192240.3-192254.6" + attribute \src "libresoc.v:193459.3-193473.6" wire width 9 $2\a[8:0] - attribute \src "libresoc.v:192270.3-192284.6" + attribute \src "libresoc.v:193489.3-193503.6" wire width 64 $2\d[63:0] - attribute \src "libresoc.v:192225.3-192239.6" - wire $2\sram4k_3_wb__ack$next[0:0]$13324 - attribute \src "libresoc.v:192255.3-192269.6" + attribute \src "libresoc.v:193444.3-193458.6" + wire $2\sram4k_3_wb__ack$next[0:0]$12918 + attribute \src "libresoc.v:193474.3-193488.6" wire width 64 $2\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:192285.3-192304.6" + attribute \src "libresoc.v:193504.3-193523.6" wire $2\we[0:0] - attribute \src "libresoc.v:192285.3-192304.6" + attribute \src "libresoc.v:193504.3-193523.6" wire $3\we[0:0] - attribute \src "libresoc.v:192205.17-192205.129" - wire $and$libresoc.v:192205$13318_Y + attribute \src "libresoc.v:193424.17-193424.129" + wire $and$libresoc.v:193424$12912_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 11 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire input 2 \enable - attribute \src "libresoc.v:192166.7-192166.15" + attribute \src "libresoc.v:193385.7-193385.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" wire output 5 \sram4k_3_wb__ack @@ -400247,7 +365484,7 @@ module \sram4k_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:192205$13318 + cell $and $and$libresoc.v:193424$12912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400255,10 +365492,10 @@ module \sram4k_3 parameter \Y_WIDTH 1 connect \A \sram4k_3_wb__cyc connect \B \sram4k_3_wb__stb - connect \Y $and$libresoc.v:192205$13318_Y + connect \Y $and$libresoc.v:193424$12912_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:192208.21-192214.4" + attribute \src "libresoc.v:193427.21-193433.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -400266,37 +365503,37 @@ module \sram4k_3 connect \q \q connect \we \we end - attribute \src "libresoc.v:192166.7-192166.20" - process $proc$libresoc.v:192166$13329 + attribute \src "libresoc.v:193385.7-193385.20" + process $proc$libresoc.v:193385$12923 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192183.7-192183.30" - process $proc$libresoc.v:192183$13330 + attribute \src "libresoc.v:193402.7-193402.30" + process $proc$libresoc.v:193402$12924 assign { } { } assign $1\sram4k_3_wb__ack[0:0] 1'0 sync always sync init update \sram4k_3_wb__ack $1\sram4k_3_wb__ack[0:0] end - attribute \src "libresoc.v:192206.3-192207.49" - process $proc$libresoc.v:192206$13319 + attribute \src "libresoc.v:193425.3-193426.49" + process $proc$libresoc.v:193425$12913 assign { } { } assign $0\sram4k_3_wb__ack[0:0] \sram4k_3_wb__ack$next sync posedge \clk update \sram4k_3_wb__ack $0\sram4k_3_wb__ack[0:0] end - attribute \src "libresoc.v:192215.3-192224.6" - process $proc$libresoc.v:192215$13320 + attribute \src "libresoc.v:193434.3-193443.6" + process $proc$libresoc.v:193434$12914 assign { } { } assign { } { } assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:192216.5-192216.29" + attribute \src "libresoc.v:193435.5-193435.29" switch \initial - attribute \src "libresoc.v:192216.9-192216.17" + attribute \src "libresoc.v:193435.9-193435.17" case 1'1 case end @@ -400312,15 +365549,15 @@ module \sram4k_3 sync always update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:192225.3-192239.6" - process $proc$libresoc.v:192225$13321 + attribute \src "libresoc.v:193444.3-193458.6" + process $proc$libresoc.v:193444$12915 assign { } { } assign { } { } assign { } { } - assign $0\sram4k_3_wb__ack$next[0:0]$13322 $2\sram4k_3_wb__ack$next[0:0]$13324 - attribute \src "libresoc.v:192226.5-192226.29" + assign $0\sram4k_3_wb__ack$next[0:0]$12916 $2\sram4k_3_wb__ack$next[0:0]$12918 + attribute \src "libresoc.v:193445.5-193445.29" switch \initial - attribute \src "libresoc.v:192226.9-192226.17" + attribute \src "libresoc.v:193445.9-193445.17" case 1'1 case end @@ -400329,30 +365566,30 @@ module \sram4k_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_3_wb__ack$next[0:0]$13323 \wb_active + assign $1\sram4k_3_wb__ack$next[0:0]$12917 \wb_active case - assign $1\sram4k_3_wb__ack$next[0:0]$13323 \sram4k_3_wb__ack + assign $1\sram4k_3_wb__ack$next[0:0]$12917 \sram4k_3_wb__ack end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_3_wb__ack$next[0:0]$13324 1'0 + assign $2\sram4k_3_wb__ack$next[0:0]$12918 1'0 case - assign $2\sram4k_3_wb__ack$next[0:0]$13324 $1\sram4k_3_wb__ack$next[0:0]$13323 + assign $2\sram4k_3_wb__ack$next[0:0]$12918 $1\sram4k_3_wb__ack$next[0:0]$12917 end sync always - update \sram4k_3_wb__ack$next $0\sram4k_3_wb__ack$next[0:0]$13322 + update \sram4k_3_wb__ack$next $0\sram4k_3_wb__ack$next[0:0]$12916 end - attribute \src "libresoc.v:192240.3-192254.6" - process $proc$libresoc.v:192240$13325 + attribute \src "libresoc.v:193459.3-193473.6" + process $proc$libresoc.v:193459$12919 assign { } { } assign { } { } assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:192241.5-192241.29" + attribute \src "libresoc.v:193460.5-193460.29" switch \initial - attribute \src "libresoc.v:192241.9-192241.17" + attribute \src "libresoc.v:193460.9-193460.17" case 1'1 case end @@ -400377,14 +365614,14 @@ module \sram4k_3 sync always update \a $0\a[8:0] end - attribute \src "libresoc.v:192255.3-192269.6" - process $proc$libresoc.v:192255$13326 + attribute \src "libresoc.v:193474.3-193488.6" + process $proc$libresoc.v:193474$12920 assign { } { } assign { } { } assign $0\sram4k_3_wb__dat_r[63:0] $1\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:192256.5-192256.29" + attribute \src "libresoc.v:193475.5-193475.29" switch \initial - attribute \src "libresoc.v:192256.9-192256.17" + attribute \src "libresoc.v:193475.9-193475.17" case 1'1 case end @@ -400409,14 +365646,14 @@ module \sram4k_3 sync always update \sram4k_3_wb__dat_r $0\sram4k_3_wb__dat_r[63:0] end - attribute \src "libresoc.v:192270.3-192284.6" - process $proc$libresoc.v:192270$13327 + attribute \src "libresoc.v:193489.3-193503.6" + process $proc$libresoc.v:193489$12921 assign { } { } assign { } { } assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:192271.5-192271.29" + attribute \src "libresoc.v:193490.5-193490.29" switch \initial - attribute \src "libresoc.v:192271.9-192271.17" + attribute \src "libresoc.v:193490.9-193490.17" case 1'1 case end @@ -400441,14 +365678,14 @@ module \sram4k_3 sync always update \d $0\d[63:0] end - attribute \src "libresoc.v:192285.3-192304.6" - process $proc$libresoc.v:192285$13328 + attribute \src "libresoc.v:193504.3-193523.6" + process $proc$libresoc.v:193504$12922 assign { } { } assign { } { } assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:192286.5-192286.29" + attribute \src "libresoc.v:193505.5-193505.29" switch \initial - attribute \src "libresoc.v:192286.9-192286.17" + attribute \src "libresoc.v:193505.9-193505.17" case 1'1 case end @@ -400482,39 +365719,39 @@ module \sram4k_3 sync always update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:192205$13318_Y + connect \$1 $and$libresoc.v:193424$12912_Y end -attribute \src "libresoc.v:192309.1-192367.10" +attribute \src "libresoc.v:193528.1-193586.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l" attribute \generator "nMigen" module \src_l - attribute \src "libresoc.v:192310.7-192310.20" + attribute \src "libresoc.v:193529.7-193529.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192355.3-192363.6" - wire width 4 $0\q_int$next[3:0]$13341 - attribute \src "libresoc.v:192353.3-192354.27" + attribute \src "libresoc.v:193574.3-193582.6" + wire width 4 $0\q_int$next[3:0]$12935 + attribute \src "libresoc.v:193572.3-193573.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:192355.3-192363.6" - wire width 4 $1\q_int$next[3:0]$13342 - attribute \src "libresoc.v:192332.13-192332.25" + attribute \src "libresoc.v:193574.3-193582.6" + wire width 4 $1\q_int$next[3:0]$12936 + attribute \src "libresoc.v:193551.13-193551.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:192345.17-192345.96" - wire width 4 $and$libresoc.v:192345$13331_Y - attribute \src "libresoc.v:192350.17-192350.96" - wire width 4 $and$libresoc.v:192350$13336_Y - attribute \src "libresoc.v:192347.18-192347.93" - wire width 4 $not$libresoc.v:192347$13333_Y - attribute \src "libresoc.v:192349.17-192349.92" - wire width 4 $not$libresoc.v:192349$13335_Y - attribute \src "libresoc.v:192352.17-192352.92" - wire width 4 $not$libresoc.v:192352$13338_Y - attribute \src "libresoc.v:192346.18-192346.98" - wire width 4 $or$libresoc.v:192346$13332_Y - attribute \src "libresoc.v:192348.18-192348.99" - wire width 4 $or$libresoc.v:192348$13334_Y - attribute \src "libresoc.v:192351.17-192351.97" - wire width 4 $or$libresoc.v:192351$13337_Y + attribute \src "libresoc.v:193564.17-193564.96" + wire width 4 $and$libresoc.v:193564$12925_Y + attribute \src "libresoc.v:193569.17-193569.96" + wire width 4 $and$libresoc.v:193569$12930_Y + attribute \src "libresoc.v:193566.18-193566.93" + wire width 4 $not$libresoc.v:193566$12927_Y + attribute \src "libresoc.v:193568.17-193568.92" + wire width 4 $not$libresoc.v:193568$12929_Y + attribute \src "libresoc.v:193571.17-193571.92" + wire width 4 $not$libresoc.v:193571$12932_Y + attribute \src "libresoc.v:193565.18-193565.98" + wire width 4 $or$libresoc.v:193565$12926_Y + attribute \src "libresoc.v:193567.18-193567.99" + wire width 4 $or$libresoc.v:193567$12928_Y + attribute \src "libresoc.v:193570.17-193570.97" + wire width 4 $or$libresoc.v:193570$12931_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -400531,11 +365768,11 @@ module \src_l wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:192310.7-192310.15" + attribute \src "libresoc.v:193529.7-193529.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -400552,7 +365789,7 @@ module \src_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192345$13331 + cell $and $and$libresoc.v:193564$12925 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -400560,10 +365797,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192345$13331_Y + connect \Y $and$libresoc.v:193564$12925_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192350$13336 + cell $and $and$libresoc.v:193569$12930 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -400571,34 +365808,34 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192350$13336_Y + connect \Y $and$libresoc.v:193569$12930_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192347$13333 + cell $not $not$libresoc.v:193566$12927 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:192347$13333_Y + connect \Y $not$libresoc.v:193566$12927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192349$13335 + cell $not $not$libresoc.v:193568$12929 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:192349$13335_Y + connect \Y $not$libresoc.v:193568$12929_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192352$13338 + cell $not $not$libresoc.v:193571$12932 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:192352$13338_Y + connect \Y $not$libresoc.v:193571$12932_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192346$13332 + cell $or $or$libresoc.v:193565$12926 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -400606,10 +365843,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192346$13332_Y + connect \Y $or$libresoc.v:193565$12926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192348$13334 + cell $or $or$libresoc.v:193567$12928 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -400617,10 +365854,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192348$13334_Y + connect \Y $or$libresoc.v:193567$12928_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192351$13337 + cell $or $or$libresoc.v:193570$12931 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -400628,39 +365865,39 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192351$13337_Y + connect \Y $or$libresoc.v:193570$12931_Y end - attribute \src "libresoc.v:192310.7-192310.20" - process $proc$libresoc.v:192310$13343 + attribute \src "libresoc.v:193529.7-193529.20" + process $proc$libresoc.v:193529$12937 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192332.13-192332.25" - process $proc$libresoc.v:192332$13344 + attribute \src "libresoc.v:193551.13-193551.25" + process $proc$libresoc.v:193551$12938 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:192353.3-192354.27" - process $proc$libresoc.v:192353$13339 + attribute \src "libresoc.v:193572.3-193573.27" + process $proc$libresoc.v:193572$12933 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:192355.3-192363.6" - process $proc$libresoc.v:192355$13340 + attribute \src "libresoc.v:193574.3-193582.6" + process $proc$libresoc.v:193574$12934 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13341 $1\q_int$next[3:0]$13342 - attribute \src "libresoc.v:192356.5-192356.29" + assign $0\q_int$next[3:0]$12935 $1\q_int$next[3:0]$12936 + attribute \src "libresoc.v:193575.5-193575.29" switch \initial - attribute \src "libresoc.v:192356.9-192356.17" + attribute \src "libresoc.v:193575.9-193575.17" case 1'1 case end @@ -400669,56 +365906,56 @@ module \src_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13342 4'0000 + assign $1\q_int$next[3:0]$12936 4'0000 case - assign $1\q_int$next[3:0]$13342 \$5 + assign $1\q_int$next[3:0]$12936 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13341 + update \q_int$next $0\q_int$next[3:0]$12935 end - connect \$9 $and$libresoc.v:192345$13331_Y - connect \$11 $or$libresoc.v:192346$13332_Y - connect \$13 $not$libresoc.v:192347$13333_Y - connect \$15 $or$libresoc.v:192348$13334_Y - connect \$1 $not$libresoc.v:192349$13335_Y - connect \$3 $and$libresoc.v:192350$13336_Y - connect \$5 $or$libresoc.v:192351$13337_Y - connect \$7 $not$libresoc.v:192352$13338_Y + connect \$9 $and$libresoc.v:193564$12925_Y + connect \$11 $or$libresoc.v:193565$12926_Y + connect \$13 $not$libresoc.v:193566$12927_Y + connect \$15 $or$libresoc.v:193567$12928_Y + connect \$1 $not$libresoc.v:193568$12929_Y + connect \$3 $and$libresoc.v:193569$12930_Y + connect \$5 $or$libresoc.v:193570$12931_Y + connect \$7 $not$libresoc.v:193571$12932_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192371.1-192429.10" +attribute \src "libresoc.v:193590.1-193648.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l" attribute \generator "nMigen" module \src_l$10 - attribute \src "libresoc.v:192372.7-192372.20" + attribute \src "libresoc.v:193591.7-193591.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192417.3-192425.6" - wire width 6 $0\q_int$next[5:0]$13355 - attribute \src "libresoc.v:192415.3-192416.27" + attribute \src "libresoc.v:193636.3-193644.6" + wire width 6 $0\q_int$next[5:0]$12949 + attribute \src "libresoc.v:193634.3-193635.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:192417.3-192425.6" - wire width 6 $1\q_int$next[5:0]$13356 - attribute \src "libresoc.v:192394.13-192394.26" + attribute \src "libresoc.v:193636.3-193644.6" + wire width 6 $1\q_int$next[5:0]$12950 + attribute \src "libresoc.v:193613.13-193613.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:192407.17-192407.96" - wire width 6 $and$libresoc.v:192407$13345_Y - attribute \src "libresoc.v:192412.17-192412.96" - wire width 6 $and$libresoc.v:192412$13350_Y - attribute \src "libresoc.v:192409.18-192409.93" - wire width 6 $not$libresoc.v:192409$13347_Y - attribute \src "libresoc.v:192411.17-192411.92" - wire width 6 $not$libresoc.v:192411$13349_Y - attribute \src "libresoc.v:192414.17-192414.92" - wire width 6 $not$libresoc.v:192414$13352_Y - attribute \src "libresoc.v:192408.18-192408.98" - wire width 6 $or$libresoc.v:192408$13346_Y - attribute \src "libresoc.v:192410.18-192410.99" - wire width 6 $or$libresoc.v:192410$13348_Y - attribute \src "libresoc.v:192413.17-192413.97" - wire width 6 $or$libresoc.v:192413$13351_Y + attribute \src "libresoc.v:193626.17-193626.96" + wire width 6 $and$libresoc.v:193626$12939_Y + attribute \src "libresoc.v:193631.17-193631.96" + wire width 6 $and$libresoc.v:193631$12944_Y + attribute \src "libresoc.v:193628.18-193628.93" + wire width 6 $not$libresoc.v:193628$12941_Y + attribute \src "libresoc.v:193630.17-193630.92" + wire width 6 $not$libresoc.v:193630$12943_Y + attribute \src "libresoc.v:193633.17-193633.92" + wire width 6 $not$libresoc.v:193633$12946_Y + attribute \src "libresoc.v:193627.18-193627.98" + wire width 6 $or$libresoc.v:193627$12940_Y + attribute \src "libresoc.v:193629.18-193629.99" + wire width 6 $or$libresoc.v:193629$12942_Y + attribute \src "libresoc.v:193632.17-193632.97" + wire width 6 $or$libresoc.v:193632$12945_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -400735,11 +365972,11 @@ module \src_l$10 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:192372.7-192372.15" + attribute \src "libresoc.v:193591.7-193591.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -400756,7 +365993,7 @@ module \src_l$10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192407$13345 + cell $and $and$libresoc.v:193626$12939 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400764,10 +366001,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192407$13345_Y + connect \Y $and$libresoc.v:193626$12939_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192412$13350 + cell $and $and$libresoc.v:193631$12944 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400775,34 +366012,34 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192412$13350_Y + connect \Y $and$libresoc.v:193631$12944_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192409$13347 + cell $not $not$libresoc.v:193628$12941 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:192409$13347_Y + connect \Y $not$libresoc.v:193628$12941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192411$13349 + cell $not $not$libresoc.v:193630$12943 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:192411$13349_Y + connect \Y $not$libresoc.v:193630$12943_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192414$13352 + cell $not $not$libresoc.v:193633$12946 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:192414$13352_Y + connect \Y $not$libresoc.v:193633$12946_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192408$13346 + cell $or $or$libresoc.v:193627$12940 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400810,10 +366047,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192408$13346_Y + connect \Y $or$libresoc.v:193627$12940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192410$13348 + cell $or $or$libresoc.v:193629$12942 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400821,10 +366058,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192410$13348_Y + connect \Y $or$libresoc.v:193629$12942_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192413$13351 + cell $or $or$libresoc.v:193632$12945 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400832,39 +366069,39 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192413$13351_Y + connect \Y $or$libresoc.v:193632$12945_Y end - attribute \src "libresoc.v:192372.7-192372.20" - process $proc$libresoc.v:192372$13357 + attribute \src "libresoc.v:193591.7-193591.20" + process $proc$libresoc.v:193591$12951 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192394.13-192394.26" - process $proc$libresoc.v:192394$13358 + attribute \src "libresoc.v:193613.13-193613.26" + process $proc$libresoc.v:193613$12952 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:192415.3-192416.27" - process $proc$libresoc.v:192415$13353 + attribute \src "libresoc.v:193634.3-193635.27" + process $proc$libresoc.v:193634$12947 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:192417.3-192425.6" - process $proc$libresoc.v:192417$13354 + attribute \src "libresoc.v:193636.3-193644.6" + process $proc$libresoc.v:193636$12948 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13355 $1\q_int$next[5:0]$13356 - attribute \src "libresoc.v:192418.5-192418.29" + assign $0\q_int$next[5:0]$12949 $1\q_int$next[5:0]$12950 + attribute \src "libresoc.v:193637.5-193637.29" switch \initial - attribute \src "libresoc.v:192418.9-192418.17" + attribute \src "libresoc.v:193637.9-193637.17" case 1'1 case end @@ -400873,56 +366110,56 @@ module \src_l$10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13356 6'000000 + assign $1\q_int$next[5:0]$12950 6'000000 case - assign $1\q_int$next[5:0]$13356 \$5 + assign $1\q_int$next[5:0]$12950 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13355 + update \q_int$next $0\q_int$next[5:0]$12949 end - connect \$9 $and$libresoc.v:192407$13345_Y - connect \$11 $or$libresoc.v:192408$13346_Y - connect \$13 $not$libresoc.v:192409$13347_Y - connect \$15 $or$libresoc.v:192410$13348_Y - connect \$1 $not$libresoc.v:192411$13349_Y - connect \$3 $and$libresoc.v:192412$13350_Y - connect \$5 $or$libresoc.v:192413$13351_Y - connect \$7 $not$libresoc.v:192414$13352_Y + connect \$9 $and$libresoc.v:193626$12939_Y + connect \$11 $or$libresoc.v:193627$12940_Y + connect \$13 $not$libresoc.v:193628$12941_Y + connect \$15 $or$libresoc.v:193629$12942_Y + connect \$1 $not$libresoc.v:193630$12943_Y + connect \$3 $and$libresoc.v:193631$12944_Y + connect \$5 $or$libresoc.v:193632$12945_Y + connect \$7 $not$libresoc.v:193633$12946_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192433.1-192491.10" +attribute \src "libresoc.v:193652.1-193710.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l" attribute \generator "nMigen" module \src_l$101 - attribute \src "libresoc.v:192434.7-192434.20" + attribute \src "libresoc.v:193653.7-193653.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192479.3-192487.6" - wire width 3 $0\q_int$next[2:0]$13369 - attribute \src "libresoc.v:192477.3-192478.27" + attribute \src "libresoc.v:193698.3-193706.6" + wire width 3 $0\q_int$next[2:0]$12963 + attribute \src "libresoc.v:193696.3-193697.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:192479.3-192487.6" - wire width 3 $1\q_int$next[2:0]$13370 - attribute \src "libresoc.v:192456.13-192456.25" + attribute \src "libresoc.v:193698.3-193706.6" + wire width 3 $1\q_int$next[2:0]$12964 + attribute \src "libresoc.v:193675.13-193675.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:192469.17-192469.96" - wire width 3 $and$libresoc.v:192469$13359_Y - attribute \src "libresoc.v:192474.17-192474.96" - wire width 3 $and$libresoc.v:192474$13364_Y - attribute \src "libresoc.v:192471.18-192471.93" - wire width 3 $not$libresoc.v:192471$13361_Y - attribute \src "libresoc.v:192473.17-192473.92" - wire width 3 $not$libresoc.v:192473$13363_Y - attribute \src "libresoc.v:192476.17-192476.92" - wire width 3 $not$libresoc.v:192476$13366_Y - attribute \src "libresoc.v:192470.18-192470.98" - wire width 3 $or$libresoc.v:192470$13360_Y - attribute \src "libresoc.v:192472.18-192472.99" - wire width 3 $or$libresoc.v:192472$13362_Y - attribute \src "libresoc.v:192475.17-192475.97" - wire width 3 $or$libresoc.v:192475$13365_Y + attribute \src "libresoc.v:193688.17-193688.96" + wire width 3 $and$libresoc.v:193688$12953_Y + attribute \src "libresoc.v:193693.17-193693.96" + wire width 3 $and$libresoc.v:193693$12958_Y + attribute \src "libresoc.v:193690.18-193690.93" + wire width 3 $not$libresoc.v:193690$12955_Y + attribute \src "libresoc.v:193692.17-193692.92" + wire width 3 $not$libresoc.v:193692$12957_Y + attribute \src "libresoc.v:193695.17-193695.92" + wire width 3 $not$libresoc.v:193695$12960_Y + attribute \src "libresoc.v:193689.18-193689.98" + wire width 3 $or$libresoc.v:193689$12954_Y + attribute \src "libresoc.v:193691.18-193691.99" + wire width 3 $or$libresoc.v:193691$12956_Y + attribute \src "libresoc.v:193694.17-193694.97" + wire width 3 $or$libresoc.v:193694$12959_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -400939,11 +366176,11 @@ module \src_l$101 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:192434.7-192434.15" + attribute \src "libresoc.v:193653.7-193653.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -400960,7 +366197,7 @@ module \src_l$101 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192469$13359 + cell $and $and$libresoc.v:193688$12953 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -400968,10 +366205,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192469$13359_Y + connect \Y $and$libresoc.v:193688$12953_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192474$13364 + cell $and $and$libresoc.v:193693$12958 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -400979,34 +366216,34 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192474$13364_Y + connect \Y $and$libresoc.v:193693$12958_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192471$13361 + cell $not $not$libresoc.v:193690$12955 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:192471$13361_Y + connect \Y $not$libresoc.v:193690$12955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192473$13363 + cell $not $not$libresoc.v:193692$12957 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192473$13363_Y + connect \Y $not$libresoc.v:193692$12957_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192476$13366 + cell $not $not$libresoc.v:193695$12960 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192476$13366_Y + connect \Y $not$libresoc.v:193695$12960_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192470$13360 + cell $or $or$libresoc.v:193689$12954 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401014,10 +366251,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192470$13360_Y + connect \Y $or$libresoc.v:193689$12954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192472$13362 + cell $or $or$libresoc.v:193691$12956 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401025,10 +366262,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192472$13362_Y + connect \Y $or$libresoc.v:193691$12956_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192475$13365 + cell $or $or$libresoc.v:193694$12959 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401036,39 +366273,39 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192475$13365_Y + connect \Y $or$libresoc.v:193694$12959_Y end - attribute \src "libresoc.v:192434.7-192434.20" - process $proc$libresoc.v:192434$13371 + attribute \src "libresoc.v:193653.7-193653.20" + process $proc$libresoc.v:193653$12965 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192456.13-192456.25" - process $proc$libresoc.v:192456$13372 + attribute \src "libresoc.v:193675.13-193675.25" + process $proc$libresoc.v:193675$12966 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:192477.3-192478.27" - process $proc$libresoc.v:192477$13367 + attribute \src "libresoc.v:193696.3-193697.27" + process $proc$libresoc.v:193696$12961 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:192479.3-192487.6" - process $proc$libresoc.v:192479$13368 + attribute \src "libresoc.v:193698.3-193706.6" + process $proc$libresoc.v:193698$12962 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13369 $1\q_int$next[2:0]$13370 - attribute \src "libresoc.v:192480.5-192480.29" + assign $0\q_int$next[2:0]$12963 $1\q_int$next[2:0]$12964 + attribute \src "libresoc.v:193699.5-193699.29" switch \initial - attribute \src "libresoc.v:192480.9-192480.17" + attribute \src "libresoc.v:193699.9-193699.17" case 1'1 case end @@ -401077,56 +366314,56 @@ module \src_l$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13370 3'000 + assign $1\q_int$next[2:0]$12964 3'000 case - assign $1\q_int$next[2:0]$13370 \$5 + assign $1\q_int$next[2:0]$12964 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13369 + update \q_int$next $0\q_int$next[2:0]$12963 end - connect \$9 $and$libresoc.v:192469$13359_Y - connect \$11 $or$libresoc.v:192470$13360_Y - connect \$13 $not$libresoc.v:192471$13361_Y - connect \$15 $or$libresoc.v:192472$13362_Y - connect \$1 $not$libresoc.v:192473$13363_Y - connect \$3 $and$libresoc.v:192474$13364_Y - connect \$5 $or$libresoc.v:192475$13365_Y - connect \$7 $not$libresoc.v:192476$13366_Y + connect \$9 $and$libresoc.v:193688$12953_Y + connect \$11 $or$libresoc.v:193689$12954_Y + connect \$13 $not$libresoc.v:193690$12955_Y + connect \$15 $or$libresoc.v:193691$12956_Y + connect \$1 $not$libresoc.v:193692$12957_Y + connect \$3 $and$libresoc.v:193693$12958_Y + connect \$5 $or$libresoc.v:193694$12959_Y + connect \$7 $not$libresoc.v:193695$12960_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192495.1-192553.10" +attribute \src "libresoc.v:193714.1-193772.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" attribute \generator "nMigen" module \src_l$119 - attribute \src "libresoc.v:192496.7-192496.20" + attribute \src "libresoc.v:193715.7-193715.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192541.3-192549.6" - wire width 5 $0\q_int$next[4:0]$13383 - attribute \src "libresoc.v:192539.3-192540.27" + attribute \src "libresoc.v:193760.3-193768.6" + wire width 5 $0\q_int$next[4:0]$12977 + attribute \src "libresoc.v:193758.3-193759.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:192541.3-192549.6" - wire width 5 $1\q_int$next[4:0]$13384 - attribute \src "libresoc.v:192518.13-192518.26" + attribute \src "libresoc.v:193760.3-193768.6" + wire width 5 $1\q_int$next[4:0]$12978 + attribute \src "libresoc.v:193737.13-193737.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:192531.17-192531.96" - wire width 5 $and$libresoc.v:192531$13373_Y - attribute \src "libresoc.v:192536.17-192536.96" - wire width 5 $and$libresoc.v:192536$13378_Y - attribute \src "libresoc.v:192533.18-192533.93" - wire width 5 $not$libresoc.v:192533$13375_Y - attribute \src "libresoc.v:192535.17-192535.92" - wire width 5 $not$libresoc.v:192535$13377_Y - attribute \src "libresoc.v:192538.17-192538.92" - wire width 5 $not$libresoc.v:192538$13380_Y - attribute \src "libresoc.v:192532.18-192532.98" - wire width 5 $or$libresoc.v:192532$13374_Y - attribute \src "libresoc.v:192534.18-192534.99" - wire width 5 $or$libresoc.v:192534$13376_Y - attribute \src "libresoc.v:192537.17-192537.97" - wire width 5 $or$libresoc.v:192537$13379_Y + attribute \src "libresoc.v:193750.17-193750.96" + wire width 5 $and$libresoc.v:193750$12967_Y + attribute \src "libresoc.v:193755.17-193755.96" + wire width 5 $and$libresoc.v:193755$12972_Y + attribute \src "libresoc.v:193752.18-193752.93" + wire width 5 $not$libresoc.v:193752$12969_Y + attribute \src "libresoc.v:193754.17-193754.92" + wire width 5 $not$libresoc.v:193754$12971_Y + attribute \src "libresoc.v:193757.17-193757.92" + wire width 5 $not$libresoc.v:193757$12974_Y + attribute \src "libresoc.v:193751.18-193751.98" + wire width 5 $or$libresoc.v:193751$12968_Y + attribute \src "libresoc.v:193753.18-193753.99" + wire width 5 $or$libresoc.v:193753$12970_Y + attribute \src "libresoc.v:193756.17-193756.97" + wire width 5 $or$libresoc.v:193756$12973_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -401143,11 +366380,11 @@ module \src_l$119 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:192496.7-192496.15" + attribute \src "libresoc.v:193715.7-193715.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -401164,7 +366401,7 @@ module \src_l$119 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192531$13373 + cell $and $and$libresoc.v:193750$12967 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -401172,10 +366409,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192531$13373_Y + connect \Y $and$libresoc.v:193750$12967_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192536$13378 + cell $and $and$libresoc.v:193755$12972 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -401183,34 +366420,34 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192536$13378_Y + connect \Y $and$libresoc.v:193755$12972_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192533$13375 + cell $not $not$libresoc.v:193752$12969 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_src - connect \Y $not$libresoc.v:192533$13375_Y + connect \Y $not$libresoc.v:193752$12969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192535$13377 + cell $not $not$libresoc.v:193754$12971 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:192535$13377_Y + connect \Y $not$libresoc.v:193754$12971_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192538$13380 + cell $not $not$libresoc.v:193757$12974 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:192538$13380_Y + connect \Y $not$libresoc.v:193757$12974_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192532$13374 + cell $or $or$libresoc.v:193751$12968 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -401218,10 +366455,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192532$13374_Y + connect \Y $or$libresoc.v:193751$12968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192534$13376 + cell $or $or$libresoc.v:193753$12970 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -401229,10 +366466,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192534$13376_Y + connect \Y $or$libresoc.v:193753$12970_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192537$13379 + cell $or $or$libresoc.v:193756$12973 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -401240,39 +366477,39 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192537$13379_Y + connect \Y $or$libresoc.v:193756$12973_Y end - attribute \src "libresoc.v:192496.7-192496.20" - process $proc$libresoc.v:192496$13385 + attribute \src "libresoc.v:193715.7-193715.20" + process $proc$libresoc.v:193715$12979 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192518.13-192518.26" - process $proc$libresoc.v:192518$13386 + attribute \src "libresoc.v:193737.13-193737.26" + process $proc$libresoc.v:193737$12980 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:192539.3-192540.27" - process $proc$libresoc.v:192539$13381 + attribute \src "libresoc.v:193758.3-193759.27" + process $proc$libresoc.v:193758$12975 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:192541.3-192549.6" - process $proc$libresoc.v:192541$13382 + attribute \src "libresoc.v:193760.3-193768.6" + process $proc$libresoc.v:193760$12976 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$13383 $1\q_int$next[4:0]$13384 - attribute \src "libresoc.v:192542.5-192542.29" + assign $0\q_int$next[4:0]$12977 $1\q_int$next[4:0]$12978 + attribute \src "libresoc.v:193761.5-193761.29" switch \initial - attribute \src "libresoc.v:192542.9-192542.17" + attribute \src "libresoc.v:193761.9-193761.17" case 1'1 case end @@ -401281,56 +366518,56 @@ module \src_l$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$13384 5'00000 + assign $1\q_int$next[4:0]$12978 5'00000 case - assign $1\q_int$next[4:0]$13384 \$5 + assign $1\q_int$next[4:0]$12978 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$13383 + update \q_int$next $0\q_int$next[4:0]$12977 end - connect \$9 $and$libresoc.v:192531$13373_Y - connect \$11 $or$libresoc.v:192532$13374_Y - connect \$13 $not$libresoc.v:192533$13375_Y - connect \$15 $or$libresoc.v:192534$13376_Y - connect \$1 $not$libresoc.v:192535$13377_Y - connect \$3 $and$libresoc.v:192536$13378_Y - connect \$5 $or$libresoc.v:192537$13379_Y - connect \$7 $not$libresoc.v:192538$13380_Y + connect \$9 $and$libresoc.v:193750$12967_Y + connect \$11 $or$libresoc.v:193751$12968_Y + connect \$13 $not$libresoc.v:193752$12969_Y + connect \$15 $or$libresoc.v:193753$12970_Y + connect \$1 $not$libresoc.v:193754$12971_Y + connect \$3 $and$libresoc.v:193755$12972_Y + connect \$5 $or$libresoc.v:193756$12973_Y + connect \$7 $not$libresoc.v:193757$12974_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192557.1-192615.10" +attribute \src "libresoc.v:193776.1-193834.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" attribute \generator "nMigen" module \src_l$127 - attribute \src "libresoc.v:192558.7-192558.20" + attribute \src "libresoc.v:193777.7-193777.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192603.3-192611.6" - wire width 3 $0\q_int$next[2:0]$13397 - attribute \src "libresoc.v:192601.3-192602.27" + attribute \src "libresoc.v:193822.3-193830.6" + wire width 3 $0\q_int$next[2:0]$12991 + attribute \src "libresoc.v:193820.3-193821.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:192603.3-192611.6" - wire width 3 $1\q_int$next[2:0]$13398 - attribute \src "libresoc.v:192580.13-192580.25" + attribute \src "libresoc.v:193822.3-193830.6" + wire width 3 $1\q_int$next[2:0]$12992 + attribute \src "libresoc.v:193799.13-193799.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:192593.17-192593.96" - wire width 3 $and$libresoc.v:192593$13387_Y - attribute \src "libresoc.v:192598.17-192598.96" - wire width 3 $and$libresoc.v:192598$13392_Y - attribute \src "libresoc.v:192595.18-192595.93" - wire width 3 $not$libresoc.v:192595$13389_Y - attribute \src "libresoc.v:192597.17-192597.92" - wire width 3 $not$libresoc.v:192597$13391_Y - attribute \src "libresoc.v:192600.17-192600.92" - wire width 3 $not$libresoc.v:192600$13394_Y - attribute \src "libresoc.v:192594.18-192594.98" - wire width 3 $or$libresoc.v:192594$13388_Y - attribute \src "libresoc.v:192596.18-192596.99" - wire width 3 $or$libresoc.v:192596$13390_Y - attribute \src "libresoc.v:192599.17-192599.97" - wire width 3 $or$libresoc.v:192599$13393_Y + attribute \src "libresoc.v:193812.17-193812.96" + wire width 3 $and$libresoc.v:193812$12981_Y + attribute \src "libresoc.v:193817.17-193817.96" + wire width 3 $and$libresoc.v:193817$12986_Y + attribute \src "libresoc.v:193814.18-193814.93" + wire width 3 $not$libresoc.v:193814$12983_Y + attribute \src "libresoc.v:193816.17-193816.92" + wire width 3 $not$libresoc.v:193816$12985_Y + attribute \src "libresoc.v:193819.17-193819.92" + wire width 3 $not$libresoc.v:193819$12988_Y + attribute \src "libresoc.v:193813.18-193813.98" + wire width 3 $or$libresoc.v:193813$12982_Y + attribute \src "libresoc.v:193815.18-193815.99" + wire width 3 $or$libresoc.v:193815$12984_Y + attribute \src "libresoc.v:193818.17-193818.97" + wire width 3 $or$libresoc.v:193818$12987_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -401347,11 +366584,11 @@ module \src_l$127 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:192558.7-192558.15" + attribute \src "libresoc.v:193777.7-193777.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -401368,7 +366605,7 @@ module \src_l$127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192593$13387 + cell $and $and$libresoc.v:193812$12981 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401376,10 +366613,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192593$13387_Y + connect \Y $and$libresoc.v:193812$12981_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192598$13392 + cell $and $and$libresoc.v:193817$12986 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401387,34 +366624,34 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192598$13392_Y + connect \Y $and$libresoc.v:193817$12986_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192595$13389 + cell $not $not$libresoc.v:193814$12983 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:192595$13389_Y + connect \Y $not$libresoc.v:193814$12983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192597$13391 + cell $not $not$libresoc.v:193816$12985 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192597$13391_Y + connect \Y $not$libresoc.v:193816$12985_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192600$13394 + cell $not $not$libresoc.v:193819$12988 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192600$13394_Y + connect \Y $not$libresoc.v:193819$12988_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192594$13388 + cell $or $or$libresoc.v:193813$12982 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401422,10 +366659,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192594$13388_Y + connect \Y $or$libresoc.v:193813$12982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192596$13390 + cell $or $or$libresoc.v:193815$12984 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401433,10 +366670,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192596$13390_Y + connect \Y $or$libresoc.v:193815$12984_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192599$13393 + cell $or $or$libresoc.v:193818$12987 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401444,39 +366681,39 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192599$13393_Y + connect \Y $or$libresoc.v:193818$12987_Y end - attribute \src "libresoc.v:192558.7-192558.20" - process $proc$libresoc.v:192558$13399 + attribute \src "libresoc.v:193777.7-193777.20" + process $proc$libresoc.v:193777$12993 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192580.13-192580.25" - process $proc$libresoc.v:192580$13400 + attribute \src "libresoc.v:193799.13-193799.25" + process $proc$libresoc.v:193799$12994 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:192601.3-192602.27" - process $proc$libresoc.v:192601$13395 + attribute \src "libresoc.v:193820.3-193821.27" + process $proc$libresoc.v:193820$12989 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:192603.3-192611.6" - process $proc$libresoc.v:192603$13396 + attribute \src "libresoc.v:193822.3-193830.6" + process $proc$libresoc.v:193822$12990 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13397 $1\q_int$next[2:0]$13398 - attribute \src "libresoc.v:192604.5-192604.29" + assign $0\q_int$next[2:0]$12991 $1\q_int$next[2:0]$12992 + attribute \src "libresoc.v:193823.5-193823.29" switch \initial - attribute \src "libresoc.v:192604.9-192604.17" + attribute \src "libresoc.v:193823.9-193823.17" case 1'1 case end @@ -401485,56 +366722,56 @@ module \src_l$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13398 3'000 + assign $1\q_int$next[2:0]$12992 3'000 case - assign $1\q_int$next[2:0]$13398 \$5 + assign $1\q_int$next[2:0]$12992 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13397 + update \q_int$next $0\q_int$next[2:0]$12991 end - connect \$9 $and$libresoc.v:192593$13387_Y - connect \$11 $or$libresoc.v:192594$13388_Y - connect \$13 $not$libresoc.v:192595$13389_Y - connect \$15 $or$libresoc.v:192596$13390_Y - connect \$1 $not$libresoc.v:192597$13391_Y - connect \$3 $and$libresoc.v:192598$13392_Y - connect \$5 $or$libresoc.v:192599$13393_Y - connect \$7 $not$libresoc.v:192600$13394_Y + connect \$9 $and$libresoc.v:193812$12981_Y + connect \$11 $or$libresoc.v:193813$12982_Y + connect \$13 $not$libresoc.v:193814$12983_Y + connect \$15 $or$libresoc.v:193815$12984_Y + connect \$1 $not$libresoc.v:193816$12985_Y + connect \$3 $and$libresoc.v:193817$12986_Y + connect \$5 $or$libresoc.v:193818$12987_Y + connect \$7 $not$libresoc.v:193819$12988_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192619.1-192677.10" +attribute \src "libresoc.v:193838.1-193896.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l" attribute \generator "nMigen" module \src_l$23 - attribute \src "libresoc.v:192620.7-192620.20" + attribute \src "libresoc.v:193839.7-193839.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192665.3-192673.6" - wire width 3 $0\q_int$next[2:0]$13411 - attribute \src "libresoc.v:192663.3-192664.27" + attribute \src "libresoc.v:193884.3-193892.6" + wire width 3 $0\q_int$next[2:0]$13005 + attribute \src "libresoc.v:193882.3-193883.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:192665.3-192673.6" - wire width 3 $1\q_int$next[2:0]$13412 - attribute \src "libresoc.v:192642.13-192642.25" + attribute \src "libresoc.v:193884.3-193892.6" + wire width 3 $1\q_int$next[2:0]$13006 + attribute \src "libresoc.v:193861.13-193861.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:192655.17-192655.96" - wire width 3 $and$libresoc.v:192655$13401_Y - attribute \src "libresoc.v:192660.17-192660.96" - wire width 3 $and$libresoc.v:192660$13406_Y - attribute \src "libresoc.v:192657.18-192657.93" - wire width 3 $not$libresoc.v:192657$13403_Y - attribute \src "libresoc.v:192659.17-192659.92" - wire width 3 $not$libresoc.v:192659$13405_Y - attribute \src "libresoc.v:192662.17-192662.92" - wire width 3 $not$libresoc.v:192662$13408_Y - attribute \src "libresoc.v:192656.18-192656.98" - wire width 3 $or$libresoc.v:192656$13402_Y - attribute \src "libresoc.v:192658.18-192658.99" - wire width 3 $or$libresoc.v:192658$13404_Y - attribute \src "libresoc.v:192661.17-192661.97" - wire width 3 $or$libresoc.v:192661$13407_Y + attribute \src "libresoc.v:193874.17-193874.96" + wire width 3 $and$libresoc.v:193874$12995_Y + attribute \src "libresoc.v:193879.17-193879.96" + wire width 3 $and$libresoc.v:193879$13000_Y + attribute \src "libresoc.v:193876.18-193876.93" + wire width 3 $not$libresoc.v:193876$12997_Y + attribute \src "libresoc.v:193878.17-193878.92" + wire width 3 $not$libresoc.v:193878$12999_Y + attribute \src "libresoc.v:193881.17-193881.92" + wire width 3 $not$libresoc.v:193881$13002_Y + attribute \src "libresoc.v:193875.18-193875.98" + wire width 3 $or$libresoc.v:193875$12996_Y + attribute \src "libresoc.v:193877.18-193877.99" + wire width 3 $or$libresoc.v:193877$12998_Y + attribute \src "libresoc.v:193880.17-193880.97" + wire width 3 $or$libresoc.v:193880$13001_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -401551,11 +366788,11 @@ module \src_l$23 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:192620.7-192620.15" + attribute \src "libresoc.v:193839.7-193839.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -401572,7 +366809,7 @@ module \src_l$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192655$13401 + cell $and $and$libresoc.v:193874$12995 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401580,10 +366817,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192655$13401_Y + connect \Y $and$libresoc.v:193874$12995_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192660$13406 + cell $and $and$libresoc.v:193879$13000 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401591,34 +366828,34 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192660$13406_Y + connect \Y $and$libresoc.v:193879$13000_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192657$13403 + cell $not $not$libresoc.v:193876$12997 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:192657$13403_Y + connect \Y $not$libresoc.v:193876$12997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192659$13405 + cell $not $not$libresoc.v:193878$12999 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192659$13405_Y + connect \Y $not$libresoc.v:193878$12999_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192662$13408 + cell $not $not$libresoc.v:193881$13002 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192662$13408_Y + connect \Y $not$libresoc.v:193881$13002_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192656$13402 + cell $or $or$libresoc.v:193875$12996 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401626,10 +366863,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192656$13402_Y + connect \Y $or$libresoc.v:193875$12996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192658$13404 + cell $or $or$libresoc.v:193877$12998 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401637,10 +366874,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192658$13404_Y + connect \Y $or$libresoc.v:193877$12998_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192661$13407 + cell $or $or$libresoc.v:193880$13001 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401648,39 +366885,39 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192661$13407_Y + connect \Y $or$libresoc.v:193880$13001_Y end - attribute \src "libresoc.v:192620.7-192620.20" - process $proc$libresoc.v:192620$13413 + attribute \src "libresoc.v:193839.7-193839.20" + process $proc$libresoc.v:193839$13007 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192642.13-192642.25" - process $proc$libresoc.v:192642$13414 + attribute \src "libresoc.v:193861.13-193861.25" + process $proc$libresoc.v:193861$13008 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:192663.3-192664.27" - process $proc$libresoc.v:192663$13409 + attribute \src "libresoc.v:193882.3-193883.27" + process $proc$libresoc.v:193882$13003 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:192665.3-192673.6" - process $proc$libresoc.v:192665$13410 + attribute \src "libresoc.v:193884.3-193892.6" + process $proc$libresoc.v:193884$13004 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13411 $1\q_int$next[2:0]$13412 - attribute \src "libresoc.v:192666.5-192666.29" + assign $0\q_int$next[2:0]$13005 $1\q_int$next[2:0]$13006 + attribute \src "libresoc.v:193885.5-193885.29" switch \initial - attribute \src "libresoc.v:192666.9-192666.17" + attribute \src "libresoc.v:193885.9-193885.17" case 1'1 case end @@ -401689,56 +366926,56 @@ module \src_l$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13412 3'000 + assign $1\q_int$next[2:0]$13006 3'000 case - assign $1\q_int$next[2:0]$13412 \$5 + assign $1\q_int$next[2:0]$13006 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13411 + update \q_int$next $0\q_int$next[2:0]$13005 end - connect \$9 $and$libresoc.v:192655$13401_Y - connect \$11 $or$libresoc.v:192656$13402_Y - connect \$13 $not$libresoc.v:192657$13403_Y - connect \$15 $or$libresoc.v:192658$13404_Y - connect \$1 $not$libresoc.v:192659$13405_Y - connect \$3 $and$libresoc.v:192660$13406_Y - connect \$5 $or$libresoc.v:192661$13407_Y - connect \$7 $not$libresoc.v:192662$13408_Y + connect \$9 $and$libresoc.v:193874$12995_Y + connect \$11 $or$libresoc.v:193875$12996_Y + connect \$13 $not$libresoc.v:193876$12997_Y + connect \$15 $or$libresoc.v:193877$12998_Y + connect \$1 $not$libresoc.v:193878$12999_Y + connect \$3 $and$libresoc.v:193879$13000_Y + connect \$5 $or$libresoc.v:193880$13001_Y + connect \$7 $not$libresoc.v:193881$13002_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192681.1-192739.10" +attribute \src "libresoc.v:193900.1-193958.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l" attribute \generator "nMigen" module \src_l$39 - attribute \src "libresoc.v:192682.7-192682.20" + attribute \src "libresoc.v:193901.7-193901.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192727.3-192735.6" - wire width 4 $0\q_int$next[3:0]$13425 - attribute \src "libresoc.v:192725.3-192726.27" + attribute \src "libresoc.v:193946.3-193954.6" + wire width 4 $0\q_int$next[3:0]$13019 + attribute \src "libresoc.v:193944.3-193945.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:192727.3-192735.6" - wire width 4 $1\q_int$next[3:0]$13426 - attribute \src "libresoc.v:192704.13-192704.25" + attribute \src "libresoc.v:193946.3-193954.6" + wire width 4 $1\q_int$next[3:0]$13020 + attribute \src "libresoc.v:193923.13-193923.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:192717.17-192717.96" - wire width 4 $and$libresoc.v:192717$13415_Y - attribute \src "libresoc.v:192722.17-192722.96" - wire width 4 $and$libresoc.v:192722$13420_Y - attribute \src "libresoc.v:192719.18-192719.93" - wire width 4 $not$libresoc.v:192719$13417_Y - attribute \src "libresoc.v:192721.17-192721.92" - wire width 4 $not$libresoc.v:192721$13419_Y - attribute \src "libresoc.v:192724.17-192724.92" - wire width 4 $not$libresoc.v:192724$13422_Y - attribute \src "libresoc.v:192718.18-192718.98" - wire width 4 $or$libresoc.v:192718$13416_Y - attribute \src "libresoc.v:192720.18-192720.99" - wire width 4 $or$libresoc.v:192720$13418_Y - attribute \src "libresoc.v:192723.17-192723.97" - wire width 4 $or$libresoc.v:192723$13421_Y + attribute \src "libresoc.v:193936.17-193936.96" + wire width 4 $and$libresoc.v:193936$13009_Y + attribute \src "libresoc.v:193941.17-193941.96" + wire width 4 $and$libresoc.v:193941$13014_Y + attribute \src "libresoc.v:193938.18-193938.93" + wire width 4 $not$libresoc.v:193938$13011_Y + attribute \src "libresoc.v:193940.17-193940.92" + wire width 4 $not$libresoc.v:193940$13013_Y + attribute \src "libresoc.v:193943.17-193943.92" + wire width 4 $not$libresoc.v:193943$13016_Y + attribute \src "libresoc.v:193937.18-193937.98" + wire width 4 $or$libresoc.v:193937$13010_Y + attribute \src "libresoc.v:193939.18-193939.99" + wire width 4 $or$libresoc.v:193939$13012_Y + attribute \src "libresoc.v:193942.17-193942.97" + wire width 4 $or$libresoc.v:193942$13015_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -401755,11 +366992,11 @@ module \src_l$39 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:192682.7-192682.15" + attribute \src "libresoc.v:193901.7-193901.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -401776,7 +367013,7 @@ module \src_l$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192717$13415 + cell $and $and$libresoc.v:193936$13009 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -401784,10 +367021,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192717$13415_Y + connect \Y $and$libresoc.v:193936$13009_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192722$13420 + cell $and $and$libresoc.v:193941$13014 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -401795,34 +367032,34 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192722$13420_Y + connect \Y $and$libresoc.v:193941$13014_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192719$13417 + cell $not $not$libresoc.v:193938$13011 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:192719$13417_Y + connect \Y $not$libresoc.v:193938$13011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192721$13419 + cell $not $not$libresoc.v:193940$13013 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:192721$13419_Y + connect \Y $not$libresoc.v:193940$13013_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192724$13422 + cell $not $not$libresoc.v:193943$13016 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:192724$13422_Y + connect \Y $not$libresoc.v:193943$13016_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192718$13416 + cell $or $or$libresoc.v:193937$13010 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -401830,10 +367067,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192718$13416_Y + connect \Y $or$libresoc.v:193937$13010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192720$13418 + cell $or $or$libresoc.v:193939$13012 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -401841,10 +367078,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192720$13418_Y + connect \Y $or$libresoc.v:193939$13012_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192723$13421 + cell $or $or$libresoc.v:193942$13015 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -401852,39 +367089,39 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192723$13421_Y + connect \Y $or$libresoc.v:193942$13015_Y end - attribute \src "libresoc.v:192682.7-192682.20" - process $proc$libresoc.v:192682$13427 + attribute \src "libresoc.v:193901.7-193901.20" + process $proc$libresoc.v:193901$13021 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192704.13-192704.25" - process $proc$libresoc.v:192704$13428 + attribute \src "libresoc.v:193923.13-193923.25" + process $proc$libresoc.v:193923$13022 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:192725.3-192726.27" - process $proc$libresoc.v:192725$13423 + attribute \src "libresoc.v:193944.3-193945.27" + process $proc$libresoc.v:193944$13017 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:192727.3-192735.6" - process $proc$libresoc.v:192727$13424 + attribute \src "libresoc.v:193946.3-193954.6" + process $proc$libresoc.v:193946$13018 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13425 $1\q_int$next[3:0]$13426 - attribute \src "libresoc.v:192728.5-192728.29" + assign $0\q_int$next[3:0]$13019 $1\q_int$next[3:0]$13020 + attribute \src "libresoc.v:193947.5-193947.29" switch \initial - attribute \src "libresoc.v:192728.9-192728.17" + attribute \src "libresoc.v:193947.9-193947.17" case 1'1 case end @@ -401893,56 +367130,56 @@ module \src_l$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13426 4'0000 + assign $1\q_int$next[3:0]$13020 4'0000 case - assign $1\q_int$next[3:0]$13426 \$5 + assign $1\q_int$next[3:0]$13020 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13425 + update \q_int$next $0\q_int$next[3:0]$13019 end - connect \$9 $and$libresoc.v:192717$13415_Y - connect \$11 $or$libresoc.v:192718$13416_Y - connect \$13 $not$libresoc.v:192719$13417_Y - connect \$15 $or$libresoc.v:192720$13418_Y - connect \$1 $not$libresoc.v:192721$13419_Y - connect \$3 $and$libresoc.v:192722$13420_Y - connect \$5 $or$libresoc.v:192723$13421_Y - connect \$7 $not$libresoc.v:192724$13422_Y + connect \$9 $and$libresoc.v:193936$13009_Y + connect \$11 $or$libresoc.v:193937$13010_Y + connect \$13 $not$libresoc.v:193938$13011_Y + connect \$15 $or$libresoc.v:193939$13012_Y + connect \$1 $not$libresoc.v:193940$13013_Y + connect \$3 $and$libresoc.v:193941$13014_Y + connect \$5 $or$libresoc.v:193942$13015_Y + connect \$7 $not$libresoc.v:193943$13016_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192743.1-192801.10" +attribute \src "libresoc.v:193962.1-194020.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l" attribute \generator "nMigen" module \src_l$55 - attribute \src "libresoc.v:192744.7-192744.20" + attribute \src "libresoc.v:193963.7-193963.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192789.3-192797.6" - wire width 3 $0\q_int$next[2:0]$13439 - attribute \src "libresoc.v:192787.3-192788.27" + attribute \src "libresoc.v:194008.3-194016.6" + wire width 3 $0\q_int$next[2:0]$13033 + attribute \src "libresoc.v:194006.3-194007.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:192789.3-192797.6" - wire width 3 $1\q_int$next[2:0]$13440 - attribute \src "libresoc.v:192766.13-192766.25" + attribute \src "libresoc.v:194008.3-194016.6" + wire width 3 $1\q_int$next[2:0]$13034 + attribute \src "libresoc.v:193985.13-193985.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:192779.17-192779.96" - wire width 3 $and$libresoc.v:192779$13429_Y - attribute \src "libresoc.v:192784.17-192784.96" - wire width 3 $and$libresoc.v:192784$13434_Y - attribute \src "libresoc.v:192781.18-192781.93" - wire width 3 $not$libresoc.v:192781$13431_Y - attribute \src "libresoc.v:192783.17-192783.92" - wire width 3 $not$libresoc.v:192783$13433_Y - attribute \src "libresoc.v:192786.17-192786.92" - wire width 3 $not$libresoc.v:192786$13436_Y - attribute \src "libresoc.v:192780.18-192780.98" - wire width 3 $or$libresoc.v:192780$13430_Y - attribute \src "libresoc.v:192782.18-192782.99" - wire width 3 $or$libresoc.v:192782$13432_Y - attribute \src "libresoc.v:192785.17-192785.97" - wire width 3 $or$libresoc.v:192785$13435_Y + attribute \src "libresoc.v:193998.17-193998.96" + wire width 3 $and$libresoc.v:193998$13023_Y + attribute \src "libresoc.v:194003.17-194003.96" + wire width 3 $and$libresoc.v:194003$13028_Y + attribute \src "libresoc.v:194000.18-194000.93" + wire width 3 $not$libresoc.v:194000$13025_Y + attribute \src "libresoc.v:194002.17-194002.92" + wire width 3 $not$libresoc.v:194002$13027_Y + attribute \src "libresoc.v:194005.17-194005.92" + wire width 3 $not$libresoc.v:194005$13030_Y + attribute \src "libresoc.v:193999.18-193999.98" + wire width 3 $or$libresoc.v:193999$13024_Y + attribute \src "libresoc.v:194001.18-194001.99" + wire width 3 $or$libresoc.v:194001$13026_Y + attribute \src "libresoc.v:194004.17-194004.97" + wire width 3 $or$libresoc.v:194004$13029_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -401959,11 +367196,11 @@ module \src_l$55 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:192744.7-192744.15" + attribute \src "libresoc.v:193963.7-193963.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -401980,7 +367217,7 @@ module \src_l$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192779$13429 + cell $and $and$libresoc.v:193998$13023 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401988,10 +367225,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192779$13429_Y + connect \Y $and$libresoc.v:193998$13023_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192784$13434 + cell $and $and$libresoc.v:194003$13028 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401999,34 +367236,34 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192784$13434_Y + connect \Y $and$libresoc.v:194003$13028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192781$13431 + cell $not $not$libresoc.v:194000$13025 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:192781$13431_Y + connect \Y $not$libresoc.v:194000$13025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192783$13433 + cell $not $not$libresoc.v:194002$13027 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192783$13433_Y + connect \Y $not$libresoc.v:194002$13027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192786$13436 + cell $not $not$libresoc.v:194005$13030 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192786$13436_Y + connect \Y $not$libresoc.v:194005$13030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192780$13430 + cell $or $or$libresoc.v:193999$13024 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402034,10 +367271,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192780$13430_Y + connect \Y $or$libresoc.v:193999$13024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192782$13432 + cell $or $or$libresoc.v:194001$13026 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402045,10 +367282,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192782$13432_Y + connect \Y $or$libresoc.v:194001$13026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192785$13435 + cell $or $or$libresoc.v:194004$13029 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402056,39 +367293,39 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192785$13435_Y + connect \Y $or$libresoc.v:194004$13029_Y end - attribute \src "libresoc.v:192744.7-192744.20" - process $proc$libresoc.v:192744$13441 + attribute \src "libresoc.v:193963.7-193963.20" + process $proc$libresoc.v:193963$13035 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192766.13-192766.25" - process $proc$libresoc.v:192766$13442 + attribute \src "libresoc.v:193985.13-193985.25" + process $proc$libresoc.v:193985$13036 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:192787.3-192788.27" - process $proc$libresoc.v:192787$13437 + attribute \src "libresoc.v:194006.3-194007.27" + process $proc$libresoc.v:194006$13031 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:192789.3-192797.6" - process $proc$libresoc.v:192789$13438 + attribute \src "libresoc.v:194008.3-194016.6" + process $proc$libresoc.v:194008$13032 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13439 $1\q_int$next[2:0]$13440 - attribute \src "libresoc.v:192790.5-192790.29" + assign $0\q_int$next[2:0]$13033 $1\q_int$next[2:0]$13034 + attribute \src "libresoc.v:194009.5-194009.29" switch \initial - attribute \src "libresoc.v:192790.9-192790.17" + attribute \src "libresoc.v:194009.9-194009.17" case 1'1 case end @@ -402097,56 +367334,56 @@ module \src_l$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13440 3'000 + assign $1\q_int$next[2:0]$13034 3'000 case - assign $1\q_int$next[2:0]$13440 \$5 + assign $1\q_int$next[2:0]$13034 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13439 + update \q_int$next $0\q_int$next[2:0]$13033 end - connect \$9 $and$libresoc.v:192779$13429_Y - connect \$11 $or$libresoc.v:192780$13430_Y - connect \$13 $not$libresoc.v:192781$13431_Y - connect \$15 $or$libresoc.v:192782$13432_Y - connect \$1 $not$libresoc.v:192783$13433_Y - connect \$3 $and$libresoc.v:192784$13434_Y - connect \$5 $or$libresoc.v:192785$13435_Y - connect \$7 $not$libresoc.v:192786$13436_Y + connect \$9 $and$libresoc.v:193998$13023_Y + connect \$11 $or$libresoc.v:193999$13024_Y + connect \$13 $not$libresoc.v:194000$13025_Y + connect \$15 $or$libresoc.v:194001$13026_Y + connect \$1 $not$libresoc.v:194002$13027_Y + connect \$3 $and$libresoc.v:194003$13028_Y + connect \$5 $or$libresoc.v:194004$13029_Y + connect \$7 $not$libresoc.v:194005$13030_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192805.1-192863.10" +attribute \src "libresoc.v:194024.1-194082.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l" attribute \generator "nMigen" module \src_l$67 - attribute \src "libresoc.v:192806.7-192806.20" + attribute \src "libresoc.v:194025.7-194025.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192851.3-192859.6" - wire width 6 $0\q_int$next[5:0]$13453 - attribute \src "libresoc.v:192849.3-192850.27" + attribute \src "libresoc.v:194070.3-194078.6" + wire width 6 $0\q_int$next[5:0]$13047 + attribute \src "libresoc.v:194068.3-194069.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:192851.3-192859.6" - wire width 6 $1\q_int$next[5:0]$13454 - attribute \src "libresoc.v:192828.13-192828.26" + attribute \src "libresoc.v:194070.3-194078.6" + wire width 6 $1\q_int$next[5:0]$13048 + attribute \src "libresoc.v:194047.13-194047.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:192841.17-192841.96" - wire width 6 $and$libresoc.v:192841$13443_Y - attribute \src "libresoc.v:192846.17-192846.96" - wire width 6 $and$libresoc.v:192846$13448_Y - attribute \src "libresoc.v:192843.18-192843.93" - wire width 6 $not$libresoc.v:192843$13445_Y - attribute \src "libresoc.v:192845.17-192845.92" - wire width 6 $not$libresoc.v:192845$13447_Y - attribute \src "libresoc.v:192848.17-192848.92" - wire width 6 $not$libresoc.v:192848$13450_Y - attribute \src "libresoc.v:192842.18-192842.98" - wire width 6 $or$libresoc.v:192842$13444_Y - attribute \src "libresoc.v:192844.18-192844.99" - wire width 6 $or$libresoc.v:192844$13446_Y - attribute \src "libresoc.v:192847.17-192847.97" - wire width 6 $or$libresoc.v:192847$13449_Y + attribute \src "libresoc.v:194060.17-194060.96" + wire width 6 $and$libresoc.v:194060$13037_Y + attribute \src "libresoc.v:194065.17-194065.96" + wire width 6 $and$libresoc.v:194065$13042_Y + attribute \src "libresoc.v:194062.18-194062.93" + wire width 6 $not$libresoc.v:194062$13039_Y + attribute \src "libresoc.v:194064.17-194064.92" + wire width 6 $not$libresoc.v:194064$13041_Y + attribute \src "libresoc.v:194067.17-194067.92" + wire width 6 $not$libresoc.v:194067$13044_Y + attribute \src "libresoc.v:194061.18-194061.98" + wire width 6 $or$libresoc.v:194061$13038_Y + attribute \src "libresoc.v:194063.18-194063.99" + wire width 6 $or$libresoc.v:194063$13040_Y + attribute \src "libresoc.v:194066.17-194066.97" + wire width 6 $or$libresoc.v:194066$13043_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -402163,11 +367400,11 @@ module \src_l$67 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:192806.7-192806.15" + attribute \src "libresoc.v:194025.7-194025.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -402184,7 +367421,7 @@ module \src_l$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192841$13443 + cell $and $and$libresoc.v:194060$13037 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -402192,10 +367429,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192841$13443_Y + connect \Y $and$libresoc.v:194060$13037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192846$13448 + cell $and $and$libresoc.v:194065$13042 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -402203,34 +367440,34 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192846$13448_Y + connect \Y $and$libresoc.v:194065$13042_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192843$13445 + cell $not $not$libresoc.v:194062$13039 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:192843$13445_Y + connect \Y $not$libresoc.v:194062$13039_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192845$13447 + cell $not $not$libresoc.v:194064$13041 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:192845$13447_Y + connect \Y $not$libresoc.v:194064$13041_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192848$13450 + cell $not $not$libresoc.v:194067$13044 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:192848$13450_Y + connect \Y $not$libresoc.v:194067$13044_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192842$13444 + cell $or $or$libresoc.v:194061$13038 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -402238,10 +367475,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192842$13444_Y + connect \Y $or$libresoc.v:194061$13038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192844$13446 + cell $or $or$libresoc.v:194063$13040 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -402249,10 +367486,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192844$13446_Y + connect \Y $or$libresoc.v:194063$13040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192847$13449 + cell $or $or$libresoc.v:194066$13043 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -402260,39 +367497,39 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192847$13449_Y + connect \Y $or$libresoc.v:194066$13043_Y end - attribute \src "libresoc.v:192806.7-192806.20" - process $proc$libresoc.v:192806$13455 + attribute \src "libresoc.v:194025.7-194025.20" + process $proc$libresoc.v:194025$13049 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192828.13-192828.26" - process $proc$libresoc.v:192828$13456 + attribute \src "libresoc.v:194047.13-194047.26" + process $proc$libresoc.v:194047$13050 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:192849.3-192850.27" - process $proc$libresoc.v:192849$13451 + attribute \src "libresoc.v:194068.3-194069.27" + process $proc$libresoc.v:194068$13045 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:192851.3-192859.6" - process $proc$libresoc.v:192851$13452 + attribute \src "libresoc.v:194070.3-194078.6" + process $proc$libresoc.v:194070$13046 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13453 $1\q_int$next[5:0]$13454 - attribute \src "libresoc.v:192852.5-192852.29" + assign $0\q_int$next[5:0]$13047 $1\q_int$next[5:0]$13048 + attribute \src "libresoc.v:194071.5-194071.29" switch \initial - attribute \src "libresoc.v:192852.9-192852.17" + attribute \src "libresoc.v:194071.9-194071.17" case 1'1 case end @@ -402301,56 +367538,56 @@ module \src_l$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13454 6'000000 + assign $1\q_int$next[5:0]$13048 6'000000 case - assign $1\q_int$next[5:0]$13454 \$5 + assign $1\q_int$next[5:0]$13048 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13453 + update \q_int$next $0\q_int$next[5:0]$13047 end - connect \$9 $and$libresoc.v:192841$13443_Y - connect \$11 $or$libresoc.v:192842$13444_Y - connect \$13 $not$libresoc.v:192843$13445_Y - connect \$15 $or$libresoc.v:192844$13446_Y - connect \$1 $not$libresoc.v:192845$13447_Y - connect \$3 $and$libresoc.v:192846$13448_Y - connect \$5 $or$libresoc.v:192847$13449_Y - connect \$7 $not$libresoc.v:192848$13450_Y + connect \$9 $and$libresoc.v:194060$13037_Y + connect \$11 $or$libresoc.v:194061$13038_Y + connect \$13 $not$libresoc.v:194062$13039_Y + connect \$15 $or$libresoc.v:194063$13040_Y + connect \$1 $not$libresoc.v:194064$13041_Y + connect \$3 $and$libresoc.v:194065$13042_Y + connect \$5 $or$libresoc.v:194066$13043_Y + connect \$7 $not$libresoc.v:194067$13044_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192867.1-192925.10" +attribute \src "libresoc.v:194086.1-194144.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" attribute \generator "nMigen" module \src_l$84 - attribute \src "libresoc.v:192868.7-192868.20" + attribute \src "libresoc.v:194087.7-194087.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192913.3-192921.6" - wire width 3 $0\q_int$next[2:0]$13467 - attribute \src "libresoc.v:192911.3-192912.27" + attribute \src "libresoc.v:194132.3-194140.6" + wire width 3 $0\q_int$next[2:0]$13061 + attribute \src "libresoc.v:194130.3-194131.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:192913.3-192921.6" - wire width 3 $1\q_int$next[2:0]$13468 - attribute \src "libresoc.v:192890.13-192890.25" + attribute \src "libresoc.v:194132.3-194140.6" + wire width 3 $1\q_int$next[2:0]$13062 + attribute \src "libresoc.v:194109.13-194109.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:192903.17-192903.96" - wire width 3 $and$libresoc.v:192903$13457_Y - attribute \src "libresoc.v:192908.17-192908.96" - wire width 3 $and$libresoc.v:192908$13462_Y - attribute \src "libresoc.v:192905.18-192905.93" - wire width 3 $not$libresoc.v:192905$13459_Y - attribute \src "libresoc.v:192907.17-192907.92" - wire width 3 $not$libresoc.v:192907$13461_Y - attribute \src "libresoc.v:192910.17-192910.92" - wire width 3 $not$libresoc.v:192910$13464_Y - attribute \src "libresoc.v:192904.18-192904.98" - wire width 3 $or$libresoc.v:192904$13458_Y - attribute \src "libresoc.v:192906.18-192906.99" - wire width 3 $or$libresoc.v:192906$13460_Y - attribute \src "libresoc.v:192909.17-192909.97" - wire width 3 $or$libresoc.v:192909$13463_Y + attribute \src "libresoc.v:194122.17-194122.96" + wire width 3 $and$libresoc.v:194122$13051_Y + attribute \src "libresoc.v:194127.17-194127.96" + wire width 3 $and$libresoc.v:194127$13056_Y + attribute \src "libresoc.v:194124.18-194124.93" + wire width 3 $not$libresoc.v:194124$13053_Y + attribute \src "libresoc.v:194126.17-194126.92" + wire width 3 $not$libresoc.v:194126$13055_Y + attribute \src "libresoc.v:194129.17-194129.92" + wire width 3 $not$libresoc.v:194129$13058_Y + attribute \src "libresoc.v:194123.18-194123.98" + wire width 3 $or$libresoc.v:194123$13052_Y + attribute \src "libresoc.v:194125.18-194125.99" + wire width 3 $or$libresoc.v:194125$13054_Y + attribute \src "libresoc.v:194128.17-194128.97" + wire width 3 $or$libresoc.v:194128$13057_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -402367,11 +367604,11 @@ module \src_l$84 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:192868.7-192868.15" + attribute \src "libresoc.v:194087.7-194087.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -402388,7 +367625,7 @@ module \src_l$84 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192903$13457 + cell $and $and$libresoc.v:194122$13051 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402396,10 +367633,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192903$13457_Y + connect \Y $and$libresoc.v:194122$13051_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192908$13462 + cell $and $and$libresoc.v:194127$13056 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402407,34 +367644,34 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192908$13462_Y + connect \Y $and$libresoc.v:194127$13056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192905$13459 + cell $not $not$libresoc.v:194124$13053 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:192905$13459_Y + connect \Y $not$libresoc.v:194124$13053_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192907$13461 + cell $not $not$libresoc.v:194126$13055 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192907$13461_Y + connect \Y $not$libresoc.v:194126$13055_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192910$13464 + cell $not $not$libresoc.v:194129$13058 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192910$13464_Y + connect \Y $not$libresoc.v:194129$13058_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192904$13458 + cell $or $or$libresoc.v:194123$13052 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402442,10 +367679,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192904$13458_Y + connect \Y $or$libresoc.v:194123$13052_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192906$13460 + cell $or $or$libresoc.v:194125$13054 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402453,10 +367690,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192906$13460_Y + connect \Y $or$libresoc.v:194125$13054_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192909$13463 + cell $or $or$libresoc.v:194128$13057 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402464,39 +367701,39 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192909$13463_Y + connect \Y $or$libresoc.v:194128$13057_Y end - attribute \src "libresoc.v:192868.7-192868.20" - process $proc$libresoc.v:192868$13469 + attribute \src "libresoc.v:194087.7-194087.20" + process $proc$libresoc.v:194087$13063 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192890.13-192890.25" - process $proc$libresoc.v:192890$13470 + attribute \src "libresoc.v:194109.13-194109.25" + process $proc$libresoc.v:194109$13064 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:192911.3-192912.27" - process $proc$libresoc.v:192911$13465 + attribute \src "libresoc.v:194130.3-194131.27" + process $proc$libresoc.v:194130$13059 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:192913.3-192921.6" - process $proc$libresoc.v:192913$13466 + attribute \src "libresoc.v:194132.3-194140.6" + process $proc$libresoc.v:194132$13060 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13467 $1\q_int$next[2:0]$13468 - attribute \src "libresoc.v:192914.5-192914.29" + assign $0\q_int$next[2:0]$13061 $1\q_int$next[2:0]$13062 + attribute \src "libresoc.v:194133.5-194133.29" switch \initial - attribute \src "libresoc.v:192914.9-192914.17" + attribute \src "libresoc.v:194133.9-194133.17" case 1'1 case end @@ -402505,56 +367742,56 @@ module \src_l$84 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13468 3'000 + assign $1\q_int$next[2:0]$13062 3'000 case - assign $1\q_int$next[2:0]$13468 \$5 + assign $1\q_int$next[2:0]$13062 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13467 + update \q_int$next $0\q_int$next[2:0]$13061 end - connect \$9 $and$libresoc.v:192903$13457_Y - connect \$11 $or$libresoc.v:192904$13458_Y - connect \$13 $not$libresoc.v:192905$13459_Y - connect \$15 $or$libresoc.v:192906$13460_Y - connect \$1 $not$libresoc.v:192907$13461_Y - connect \$3 $and$libresoc.v:192908$13462_Y - connect \$5 $or$libresoc.v:192909$13463_Y - connect \$7 $not$libresoc.v:192910$13464_Y + connect \$9 $and$libresoc.v:194122$13051_Y + connect \$11 $or$libresoc.v:194123$13052_Y + connect \$13 $not$libresoc.v:194124$13053_Y + connect \$15 $or$libresoc.v:194125$13054_Y + connect \$1 $not$libresoc.v:194126$13055_Y + connect \$3 $and$libresoc.v:194127$13056_Y + connect \$5 $or$libresoc.v:194128$13057_Y + connect \$7 $not$libresoc.v:194129$13058_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192929.1-192987.10" +attribute \src "libresoc.v:194148.1-194206.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active" attribute \generator "nMigen" module \st_active - attribute \src "libresoc.v:192930.7-192930.20" + attribute \src "libresoc.v:194149.7-194149.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192975.3-192983.6" - wire $0\q_int$next[0:0]$13481 - attribute \src "libresoc.v:192973.3-192974.27" + attribute \src "libresoc.v:194194.3-194202.6" + wire $0\q_int$next[0:0]$13075 + attribute \src "libresoc.v:194192.3-194193.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:192975.3-192983.6" - wire $1\q_int$next[0:0]$13482 - attribute \src "libresoc.v:192952.7-192952.19" + attribute \src "libresoc.v:194194.3-194202.6" + wire $1\q_int$next[0:0]$13076 + attribute \src "libresoc.v:194171.7-194171.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:192965.17-192965.96" - wire $and$libresoc.v:192965$13471_Y - attribute \src "libresoc.v:192970.17-192970.96" - wire $and$libresoc.v:192970$13476_Y - attribute \src "libresoc.v:192967.18-192967.99" - wire $not$libresoc.v:192967$13473_Y - attribute \src "libresoc.v:192969.17-192969.98" - wire $not$libresoc.v:192969$13475_Y - attribute \src "libresoc.v:192972.17-192972.98" - wire $not$libresoc.v:192972$13478_Y - attribute \src "libresoc.v:192966.18-192966.104" - wire $or$libresoc.v:192966$13472_Y - attribute \src "libresoc.v:192968.18-192968.105" - wire $or$libresoc.v:192968$13474_Y - attribute \src "libresoc.v:192971.17-192971.103" - wire $or$libresoc.v:192971$13477_Y + attribute \src "libresoc.v:194184.17-194184.96" + wire $and$libresoc.v:194184$13065_Y + attribute \src "libresoc.v:194189.17-194189.96" + wire $and$libresoc.v:194189$13070_Y + attribute \src "libresoc.v:194186.18-194186.99" + wire $not$libresoc.v:194186$13067_Y + attribute \src "libresoc.v:194188.17-194188.98" + wire $not$libresoc.v:194188$13069_Y + attribute \src "libresoc.v:194191.17-194191.98" + wire $not$libresoc.v:194191$13072_Y + attribute \src "libresoc.v:194185.18-194185.104" + wire $or$libresoc.v:194185$13066_Y + attribute \src "libresoc.v:194187.18-194187.105" + wire $or$libresoc.v:194187$13068_Y + attribute \src "libresoc.v:194190.17-194190.103" + wire $or$libresoc.v:194190$13071_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -402571,11 +367808,11 @@ module \st_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:192930.7-192930.15" + attribute \src "libresoc.v:194149.7-194149.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -402592,7 +367829,7 @@ module \st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192965$13471 + cell $and $and$libresoc.v:194184$13065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402600,10 +367837,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192965$13471_Y + connect \Y $and$libresoc.v:194184$13065_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192970$13476 + cell $and $and$libresoc.v:194189$13070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402611,34 +367848,34 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192970$13476_Y + connect \Y $and$libresoc.v:194189$13070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192967$13473 + cell $not $not$libresoc.v:194186$13067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_active - connect \Y $not$libresoc.v:192967$13473_Y + connect \Y $not$libresoc.v:194186$13067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192969$13475 + cell $not $not$libresoc.v:194188$13069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:192969$13475_Y + connect \Y $not$libresoc.v:194188$13069_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192972$13478 + cell $not $not$libresoc.v:194191$13072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:192972$13478_Y + connect \Y $not$libresoc.v:194191$13072_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192966$13472 + cell $or $or$libresoc.v:194185$13066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402646,10 +367883,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_active - connect \Y $or$libresoc.v:192966$13472_Y + connect \Y $or$libresoc.v:194185$13066_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192968$13474 + cell $or $or$libresoc.v:194187$13068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402657,10 +367894,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_st_active connect \B \q_int - connect \Y $or$libresoc.v:192968$13474_Y + connect \Y $or$libresoc.v:194187$13068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192971$13477 + cell $or $or$libresoc.v:194190$13071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402668,39 +367905,39 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_active - connect \Y $or$libresoc.v:192971$13477_Y + connect \Y $or$libresoc.v:194190$13071_Y end - attribute \src "libresoc.v:192930.7-192930.20" - process $proc$libresoc.v:192930$13483 + attribute \src "libresoc.v:194149.7-194149.20" + process $proc$libresoc.v:194149$13077 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192952.7-192952.19" - process $proc$libresoc.v:192952$13484 + attribute \src "libresoc.v:194171.7-194171.19" + process $proc$libresoc.v:194171$13078 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:192973.3-192974.27" - process $proc$libresoc.v:192973$13479 + attribute \src "libresoc.v:194192.3-194193.27" + process $proc$libresoc.v:194192$13073 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:192975.3-192983.6" - process $proc$libresoc.v:192975$13480 + attribute \src "libresoc.v:194194.3-194202.6" + process $proc$libresoc.v:194194$13074 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13481 $1\q_int$next[0:0]$13482 - attribute \src "libresoc.v:192976.5-192976.29" + assign $0\q_int$next[0:0]$13075 $1\q_int$next[0:0]$13076 + attribute \src "libresoc.v:194195.5-194195.29" switch \initial - attribute \src "libresoc.v:192976.9-192976.17" + attribute \src "libresoc.v:194195.9-194195.17" case 1'1 case end @@ -402709,56 +367946,56 @@ module \st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13482 1'0 + assign $1\q_int$next[0:0]$13076 1'0 case - assign $1\q_int$next[0:0]$13482 \$5 + assign $1\q_int$next[0:0]$13076 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13481 + update \q_int$next $0\q_int$next[0:0]$13075 end - connect \$9 $and$libresoc.v:192965$13471_Y - connect \$11 $or$libresoc.v:192966$13472_Y - connect \$13 $not$libresoc.v:192967$13473_Y - connect \$15 $or$libresoc.v:192968$13474_Y - connect \$1 $not$libresoc.v:192969$13475_Y - connect \$3 $and$libresoc.v:192970$13476_Y - connect \$5 $or$libresoc.v:192971$13477_Y - connect \$7 $not$libresoc.v:192972$13478_Y + connect \$9 $and$libresoc.v:194184$13065_Y + connect \$11 $or$libresoc.v:194185$13066_Y + connect \$13 $not$libresoc.v:194186$13067_Y + connect \$15 $or$libresoc.v:194187$13068_Y + connect \$1 $not$libresoc.v:194188$13069_Y + connect \$3 $and$libresoc.v:194189$13070_Y + connect \$5 $or$libresoc.v:194190$13071_Y + connect \$7 $not$libresoc.v:194191$13072_Y connect \qlq_st_active \$15 connect \qn_st_active \$13 connect \q_st_active \$11 end -attribute \src "libresoc.v:192991.1-193049.10" +attribute \src "libresoc.v:194210.1-194268.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done" attribute \generator "nMigen" module \st_done - attribute \src "libresoc.v:192992.7-192992.20" + attribute \src "libresoc.v:194211.7-194211.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193037.3-193045.6" - wire $0\q_int$next[0:0]$13495 - attribute \src "libresoc.v:193035.3-193036.27" + attribute \src "libresoc.v:194256.3-194264.6" + wire $0\q_int$next[0:0]$13089 + attribute \src "libresoc.v:194254.3-194255.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:193037.3-193045.6" - wire $1\q_int$next[0:0]$13496 - attribute \src "libresoc.v:193014.7-193014.19" + attribute \src "libresoc.v:194256.3-194264.6" + wire $1\q_int$next[0:0]$13090 + attribute \src "libresoc.v:194233.7-194233.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:193027.17-193027.96" - wire $and$libresoc.v:193027$13485_Y - attribute \src "libresoc.v:193032.17-193032.96" - wire $and$libresoc.v:193032$13490_Y - attribute \src "libresoc.v:193029.18-193029.97" - wire $not$libresoc.v:193029$13487_Y - attribute \src "libresoc.v:193031.17-193031.96" - wire $not$libresoc.v:193031$13489_Y - attribute \src "libresoc.v:193034.17-193034.96" - wire $not$libresoc.v:193034$13492_Y - attribute \src "libresoc.v:193028.18-193028.102" - wire $or$libresoc.v:193028$13486_Y - attribute \src "libresoc.v:193030.18-193030.103" - wire $or$libresoc.v:193030$13488_Y - attribute \src "libresoc.v:193033.17-193033.101" - wire $or$libresoc.v:193033$13491_Y + attribute \src "libresoc.v:194246.17-194246.96" + wire $and$libresoc.v:194246$13079_Y + attribute \src "libresoc.v:194251.17-194251.96" + wire $and$libresoc.v:194251$13084_Y + attribute \src "libresoc.v:194248.18-194248.97" + wire $not$libresoc.v:194248$13081_Y + attribute \src "libresoc.v:194250.17-194250.96" + wire $not$libresoc.v:194250$13083_Y + attribute \src "libresoc.v:194253.17-194253.96" + wire $not$libresoc.v:194253$13086_Y + attribute \src "libresoc.v:194247.18-194247.102" + wire $or$libresoc.v:194247$13080_Y + attribute \src "libresoc.v:194249.18-194249.103" + wire $or$libresoc.v:194249$13082_Y + attribute \src "libresoc.v:194252.17-194252.101" + wire $or$libresoc.v:194252$13085_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -402775,11 +368012,11 @@ module \st_done wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:192992.7-192992.15" + attribute \src "libresoc.v:194211.7-194211.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -402796,7 +368033,7 @@ module \st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193027$13485 + cell $and $and$libresoc.v:194246$13079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402804,10 +368041,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193027$13485_Y + connect \Y $and$libresoc.v:194246$13079_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193032$13490 + cell $and $and$libresoc.v:194251$13084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402815,34 +368052,34 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193032$13490_Y + connect \Y $and$libresoc.v:194251$13084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193029$13487 + cell $not $not$libresoc.v:194248$13081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_done - connect \Y $not$libresoc.v:193029$13487_Y + connect \Y $not$libresoc.v:194248$13081_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193031$13489 + cell $not $not$libresoc.v:194250$13083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:193031$13489_Y + connect \Y $not$libresoc.v:194250$13083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193034$13492 + cell $not $not$libresoc.v:194253$13086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:193034$13492_Y + connect \Y $not$libresoc.v:194253$13086_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193028$13486 + cell $or $or$libresoc.v:194247$13080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402850,10 +368087,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_done - connect \Y $or$libresoc.v:193028$13486_Y + connect \Y $or$libresoc.v:194247$13080_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193030$13488 + cell $or $or$libresoc.v:194249$13082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402861,10 +368098,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_st_done connect \B \q_int - connect \Y $or$libresoc.v:193030$13488_Y + connect \Y $or$libresoc.v:194249$13082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193033$13491 + cell $or $or$libresoc.v:194252$13085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402872,39 +368109,39 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_done - connect \Y $or$libresoc.v:193033$13491_Y + connect \Y $or$libresoc.v:194252$13085_Y end - attribute \src "libresoc.v:192992.7-192992.20" - process $proc$libresoc.v:192992$13497 + attribute \src "libresoc.v:194211.7-194211.20" + process $proc$libresoc.v:194211$13091 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193014.7-193014.19" - process $proc$libresoc.v:193014$13498 + attribute \src "libresoc.v:194233.7-194233.19" + process $proc$libresoc.v:194233$13092 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:193035.3-193036.27" - process $proc$libresoc.v:193035$13493 + attribute \src "libresoc.v:194254.3-194255.27" + process $proc$libresoc.v:194254$13087 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:193037.3-193045.6" - process $proc$libresoc.v:193037$13494 + attribute \src "libresoc.v:194256.3-194264.6" + process $proc$libresoc.v:194256$13088 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13495 $1\q_int$next[0:0]$13496 - attribute \src "libresoc.v:193038.5-193038.29" + assign $0\q_int$next[0:0]$13089 $1\q_int$next[0:0]$13090 + attribute \src "libresoc.v:194257.5-194257.29" switch \initial - attribute \src "libresoc.v:193038.9-193038.17" + attribute \src "libresoc.v:194257.9-194257.17" case 1'1 case end @@ -402913,86 +368150,86 @@ module \st_done attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13496 1'0 + assign $1\q_int$next[0:0]$13090 1'0 case - assign $1\q_int$next[0:0]$13496 \$5 + assign $1\q_int$next[0:0]$13090 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13495 + update \q_int$next $0\q_int$next[0:0]$13089 end - connect \$9 $and$libresoc.v:193027$13485_Y - connect \$11 $or$libresoc.v:193028$13486_Y - connect \$13 $not$libresoc.v:193029$13487_Y - connect \$15 $or$libresoc.v:193030$13488_Y - connect \$1 $not$libresoc.v:193031$13489_Y - connect \$3 $and$libresoc.v:193032$13490_Y - connect \$5 $or$libresoc.v:193033$13491_Y - connect \$7 $not$libresoc.v:193034$13492_Y + connect \$9 $and$libresoc.v:194246$13079_Y + connect \$11 $or$libresoc.v:194247$13080_Y + connect \$13 $not$libresoc.v:194248$13081_Y + connect \$15 $or$libresoc.v:194249$13082_Y + connect \$1 $not$libresoc.v:194250$13083_Y + connect \$3 $and$libresoc.v:194251$13084_Y + connect \$5 $or$libresoc.v:194252$13085_Y + connect \$7 $not$libresoc.v:194253$13086_Y connect \qlq_st_done \$15 connect \qn_st_done \$13 connect \q_st_done \$11 end -attribute \src "libresoc.v:193053.1-193349.10" +attribute \src "libresoc.v:194272.1-194568.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state" attribute \generator "nMigen" module \state - attribute \src "libresoc.v:193301.3-193310.6" + attribute \src "libresoc.v:194520.3-194529.6" wire width 64 $0\cia__data_o[63:0] - attribute \src "libresoc.v:193054.7-193054.20" + attribute \src "libresoc.v:194273.7-194273.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193320.3-193329.6" + attribute \src "libresoc.v:194539.3-194548.6" wire width 64 $0\msr__data_o[63:0] - attribute \src "libresoc.v:193311.3-193319.6" - wire width 3 $0\ren_delay$12$next[2:0]$13522 - attribute \src "libresoc.v:193215.3-193216.43" - wire width 3 $0\ren_delay$12[2:0]$13511 - attribute \src "libresoc.v:193182.13-193182.34" - wire width 3 $0\ren_delay$12[2:0]$13528 - attribute \src "libresoc.v:193273.3-193281.6" - wire width 3 $0\ren_delay$19$next[2:0]$13514 - attribute \src "libresoc.v:193213.3-193214.43" - wire width 3 $0\ren_delay$19[2:0]$13509 - attribute \src "libresoc.v:193186.13-193186.34" - wire width 3 $0\ren_delay$19[2:0]$13530 - attribute \src "libresoc.v:193292.3-193300.6" - wire width 3 $0\ren_delay$next[2:0]$13518 - attribute \src "libresoc.v:193217.3-193218.35" + attribute \src "libresoc.v:194530.3-194538.6" + wire width 3 $0\ren_delay$12$next[2:0]$13116 + attribute \src "libresoc.v:194434.3-194435.43" + wire width 3 $0\ren_delay$12[2:0]$13105 + attribute \src "libresoc.v:194401.13-194401.34" + wire width 3 $0\ren_delay$12[2:0]$13122 + attribute \src "libresoc.v:194492.3-194500.6" + wire width 3 $0\ren_delay$19$next[2:0]$13108 + attribute \src "libresoc.v:194432.3-194433.43" + wire width 3 $0\ren_delay$19[2:0]$13103 + attribute \src "libresoc.v:194405.13-194405.34" + wire width 3 $0\ren_delay$19[2:0]$13124 + attribute \src "libresoc.v:194511.3-194519.6" + wire width 3 $0\ren_delay$next[2:0]$13112 + attribute \src "libresoc.v:194436.3-194437.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:193282.3-193291.6" + attribute \src "libresoc.v:194501.3-194510.6" wire width 64 $0\sv__data_o[63:0] - attribute \src "libresoc.v:193301.3-193310.6" + attribute \src "libresoc.v:194520.3-194529.6" wire width 64 $1\cia__data_o[63:0] - attribute \src "libresoc.v:193320.3-193329.6" + attribute \src "libresoc.v:194539.3-194548.6" wire width 64 $1\msr__data_o[63:0] - attribute \src "libresoc.v:193311.3-193319.6" - wire width 3 $1\ren_delay$12$next[2:0]$13523 - attribute \src "libresoc.v:193273.3-193281.6" - wire width 3 $1\ren_delay$19$next[2:0]$13515 - attribute \src "libresoc.v:193292.3-193300.6" - wire width 3 $1\ren_delay$next[2:0]$13519 - attribute \src "libresoc.v:193180.13-193180.29" + attribute \src "libresoc.v:194530.3-194538.6" + wire width 3 $1\ren_delay$12$next[2:0]$13117 + attribute \src "libresoc.v:194492.3-194500.6" + wire width 3 $1\ren_delay$19$next[2:0]$13109 + attribute \src "libresoc.v:194511.3-194519.6" + wire width 3 $1\ren_delay$next[2:0]$13113 + attribute \src "libresoc.v:194399.13-194399.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:193282.3-193291.6" + attribute \src "libresoc.v:194501.3-194510.6" wire width 64 $1\sv__data_o[63:0] - attribute \src "libresoc.v:193204.18-193204.109" - wire width 64 $or$libresoc.v:193204$13499_Y - attribute \src "libresoc.v:193206.18-193206.124" - wire width 64 $or$libresoc.v:193206$13501_Y - attribute \src "libresoc.v:193207.18-193207.110" - wire width 64 $or$libresoc.v:193207$13502_Y - attribute \src "libresoc.v:193209.18-193209.122" - wire width 64 $or$libresoc.v:193209$13504_Y - attribute \src "libresoc.v:193210.18-193210.109" - wire width 64 $or$libresoc.v:193210$13505_Y - attribute \src "libresoc.v:193212.17-193212.123" - wire width 64 $or$libresoc.v:193212$13507_Y - attribute \src "libresoc.v:193205.18-193205.100" - wire $reduce_or$libresoc.v:193205$13500_Y - attribute \src "libresoc.v:193208.18-193208.100" - wire $reduce_or$libresoc.v:193208$13503_Y - attribute \src "libresoc.v:193211.17-193211.95" - wire $reduce_or$libresoc.v:193211$13506_Y + attribute \src "libresoc.v:194423.18-194423.109" + wire width 64 $or$libresoc.v:194423$13093_Y + attribute \src "libresoc.v:194425.18-194425.124" + wire width 64 $or$libresoc.v:194425$13095_Y + attribute \src "libresoc.v:194426.18-194426.110" + wire width 64 $or$libresoc.v:194426$13096_Y + attribute \src "libresoc.v:194428.18-194428.122" + wire width 64 $or$libresoc.v:194428$13098_Y + attribute \src "libresoc.v:194429.18-194429.109" + wire width 64 $or$libresoc.v:194429$13099_Y + attribute \src "libresoc.v:194431.17-194431.123" + wire width 64 $or$libresoc.v:194431$13101_Y + attribute \src "libresoc.v:194424.18-194424.100" + wire $reduce_or$libresoc.v:194424$13094_Y + attribute \src "libresoc.v:194427.18-194427.100" + wire $reduce_or$libresoc.v:194427$13097_Y + attribute \src "libresoc.v:194430.17-194430.95" + wire $reduce_or$libresoc.v:194430$13100_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" @@ -403015,9 +368252,9 @@ module \state wire width 64 output 3 \cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 7 \data_i @@ -403027,7 +368264,7 @@ module \state wire width 64 input 13 \data_i$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 14 \data_i$4 - attribute \src "libresoc.v:193054.7-193054.15" + attribute \src "libresoc.v:194273.7-194273.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 9 \msr__data_o @@ -403142,7 +368379,7 @@ module \state attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:193204$13499 + cell $or $or$libresoc.v:194423$13093 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -403150,10 +368387,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_cia0__data_o connect \B \$8 - connect \Y $or$libresoc.v:193204$13499_Y + connect \Y $or$libresoc.v:194423$13093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:193206$13501 + cell $or $or$libresoc.v:194425$13095 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -403161,10 +368398,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_msr1__data_o connect \B \reg_2_msr2__data_o - connect \Y $or$libresoc.v:193206$13501_Y + connect \Y $or$libresoc.v:194425$13095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:193207$13502 + cell $or $or$libresoc.v:194426$13096 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -403172,10 +368409,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_msr0__data_o connect \B \$15 - connect \Y $or$libresoc.v:193207$13502_Y + connect \Y $or$libresoc.v:194426$13096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:193209$13504 + cell $or $or$libresoc.v:194428$13098 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -403183,10 +368420,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_sv1__data_o connect \B \reg_2_sv2__data_o - connect \Y $or$libresoc.v:193209$13504_Y + connect \Y $or$libresoc.v:194428$13098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:193210$13505 + cell $or $or$libresoc.v:194429$13099 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -403194,10 +368431,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_sv0__data_o connect \B \$22 - connect \Y $or$libresoc.v:193210$13505_Y + connect \Y $or$libresoc.v:194429$13099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:193212$13507 + cell $or $or$libresoc.v:194431$13101 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -403205,34 +368442,34 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_cia1__data_o connect \B \reg_2_cia2__data_o - connect \Y $or$libresoc.v:193212$13507_Y + connect \Y $or$libresoc.v:194431$13101_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:193205$13500 + cell $reduce_or $reduce_or$libresoc.v:194424$13094 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$12 - connect \Y $reduce_or$libresoc.v:193205$13500_Y + connect \Y $reduce_or$libresoc.v:194424$13094_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:193208$13503 + cell $reduce_or $reduce_or$libresoc.v:194427$13097 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$19 - connect \Y $reduce_or$libresoc.v:193208$13503_Y + connect \Y $reduce_or$libresoc.v:194427$13097_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:193211$13506 + cell $reduce_or $reduce_or$libresoc.v:194430$13100 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:193211$13506_Y + connect \Y $reduce_or$libresoc.v:194430$13100_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:193219.15-193236.4" + attribute \src "libresoc.v:194438.15-194455.4" cell \reg_0$135 \reg_0 connect \cia0__data_o \reg_0_cia0__data_o connect \cia0__ren \reg_0_cia0__ren @@ -403252,7 +368489,7 @@ module \state connect \sv0__wen \reg_0_sv0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:193237.15-193254.4" + attribute \src "libresoc.v:194456.15-194473.4" cell \reg_1$136 \reg_1 connect \cia1__data_o \reg_1_cia1__data_o connect \cia1__ren \reg_1_cia1__ren @@ -403272,7 +368509,7 @@ module \state connect \sv1__wen \reg_1_sv1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:193255.15-193272.4" + attribute \src "libresoc.v:194474.15-194491.4" cell \reg_2$137 \reg_2 connect \cia2__data_o \reg_2_cia2__data_o connect \cia2__ren \reg_2_cia2__ren @@ -403291,67 +368528,67 @@ module \state connect \sv2__ren \reg_2_sv2__ren connect \sv2__wen \reg_2_sv2__wen end - attribute \src "libresoc.v:193054.7-193054.20" - process $proc$libresoc.v:193054$13525 + attribute \src "libresoc.v:194273.7-194273.20" + process $proc$libresoc.v:194273$13119 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193180.13-193180.29" - process $proc$libresoc.v:193180$13526 + attribute \src "libresoc.v:194399.13-194399.29" + process $proc$libresoc.v:194399$13120 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:193182.13-193182.34" - process $proc$libresoc.v:193182$13527 + attribute \src "libresoc.v:194401.13-194401.34" + process $proc$libresoc.v:194401$13121 assign { } { } - assign $0\ren_delay$12[2:0]$13528 3'000 + assign $0\ren_delay$12[2:0]$13122 3'000 sync always sync init - update \ren_delay$12 $0\ren_delay$12[2:0]$13528 + update \ren_delay$12 $0\ren_delay$12[2:0]$13122 end - attribute \src "libresoc.v:193186.13-193186.34" - process $proc$libresoc.v:193186$13529 + attribute \src "libresoc.v:194405.13-194405.34" + process $proc$libresoc.v:194405$13123 assign { } { } - assign $0\ren_delay$19[2:0]$13530 3'000 + assign $0\ren_delay$19[2:0]$13124 3'000 sync always sync init - update \ren_delay$19 $0\ren_delay$19[2:0]$13530 + update \ren_delay$19 $0\ren_delay$19[2:0]$13124 end - attribute \src "libresoc.v:193213.3-193214.43" - process $proc$libresoc.v:193213$13508 + attribute \src "libresoc.v:194432.3-194433.43" + process $proc$libresoc.v:194432$13102 assign { } { } - assign $0\ren_delay$19[2:0]$13509 \ren_delay$19$next + assign $0\ren_delay$19[2:0]$13103 \ren_delay$19$next sync posedge \coresync_clk - update \ren_delay$19 $0\ren_delay$19[2:0]$13509 + update \ren_delay$19 $0\ren_delay$19[2:0]$13103 end - attribute \src "libresoc.v:193215.3-193216.43" - process $proc$libresoc.v:193215$13510 + attribute \src "libresoc.v:194434.3-194435.43" + process $proc$libresoc.v:194434$13104 assign { } { } - assign $0\ren_delay$12[2:0]$13511 \ren_delay$12$next + assign $0\ren_delay$12[2:0]$13105 \ren_delay$12$next sync posedge \coresync_clk - update \ren_delay$12 $0\ren_delay$12[2:0]$13511 + update \ren_delay$12 $0\ren_delay$12[2:0]$13105 end - attribute \src "libresoc.v:193217.3-193218.35" - process $proc$libresoc.v:193217$13512 + attribute \src "libresoc.v:194436.3-194437.35" + process $proc$libresoc.v:194436$13106 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:193273.3-193281.6" - process $proc$libresoc.v:193273$13513 + attribute \src "libresoc.v:194492.3-194500.6" + process $proc$libresoc.v:194492$13107 assign { } { } assign { } { } - assign $0\ren_delay$19$next[2:0]$13514 $1\ren_delay$19$next[2:0]$13515 - attribute \src "libresoc.v:193274.5-193274.29" + assign $0\ren_delay$19$next[2:0]$13108 $1\ren_delay$19$next[2:0]$13109 + attribute \src "libresoc.v:194493.5-194493.29" switch \initial - attribute \src "libresoc.v:193274.9-193274.17" + attribute \src "libresoc.v:194493.9-194493.17" case 1'1 case end @@ -403360,21 +368597,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$19$next[2:0]$13515 3'000 + assign $1\ren_delay$19$next[2:0]$13109 3'000 case - assign $1\ren_delay$19$next[2:0]$13515 \sv__ren + assign $1\ren_delay$19$next[2:0]$13109 \sv__ren end sync always - update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13514 + update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13108 end - attribute \src "libresoc.v:193282.3-193291.6" - process $proc$libresoc.v:193282$13516 + attribute \src "libresoc.v:194501.3-194510.6" + process $proc$libresoc.v:194501$13110 assign { } { } assign { } { } assign $0\sv__data_o[63:0] $1\sv__data_o[63:0] - attribute \src "libresoc.v:193283.5-193283.29" + attribute \src "libresoc.v:194502.5-194502.29" switch \initial - attribute \src "libresoc.v:193283.9-193283.17" + attribute \src "libresoc.v:194502.9-194502.17" case 1'1 case end @@ -403390,14 +368627,14 @@ module \state sync always update \sv__data_o $0\sv__data_o[63:0] end - attribute \src "libresoc.v:193292.3-193300.6" - process $proc$libresoc.v:193292$13517 + attribute \src "libresoc.v:194511.3-194519.6" + process $proc$libresoc.v:194511$13111 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$13518 $1\ren_delay$next[2:0]$13519 - attribute \src "libresoc.v:193293.5-193293.29" + assign $0\ren_delay$next[2:0]$13112 $1\ren_delay$next[2:0]$13113 + attribute \src "libresoc.v:194512.5-194512.29" switch \initial - attribute \src "libresoc.v:193293.9-193293.17" + attribute \src "libresoc.v:194512.9-194512.17" case 1'1 case end @@ -403406,21 +368643,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$13519 3'000 + assign $1\ren_delay$next[2:0]$13113 3'000 case - assign $1\ren_delay$next[2:0]$13519 \cia__ren + assign $1\ren_delay$next[2:0]$13113 \cia__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$13518 + update \ren_delay$next $0\ren_delay$next[2:0]$13112 end - attribute \src "libresoc.v:193301.3-193310.6" - process $proc$libresoc.v:193301$13520 + attribute \src "libresoc.v:194520.3-194529.6" + process $proc$libresoc.v:194520$13114 assign { } { } assign { } { } assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] - attribute \src "libresoc.v:193302.5-193302.29" + attribute \src "libresoc.v:194521.5-194521.29" switch \initial - attribute \src "libresoc.v:193302.9-193302.17" + attribute \src "libresoc.v:194521.9-194521.17" case 1'1 case end @@ -403436,14 +368673,14 @@ module \state sync always update \cia__data_o $0\cia__data_o[63:0] end - attribute \src "libresoc.v:193311.3-193319.6" - process $proc$libresoc.v:193311$13521 + attribute \src "libresoc.v:194530.3-194538.6" + process $proc$libresoc.v:194530$13115 assign { } { } assign { } { } - assign $0\ren_delay$12$next[2:0]$13522 $1\ren_delay$12$next[2:0]$13523 - attribute \src "libresoc.v:193312.5-193312.29" + assign $0\ren_delay$12$next[2:0]$13116 $1\ren_delay$12$next[2:0]$13117 + attribute \src "libresoc.v:194531.5-194531.29" switch \initial - attribute \src "libresoc.v:193312.9-193312.17" + attribute \src "libresoc.v:194531.9-194531.17" case 1'1 case end @@ -403452,21 +368689,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$12$next[2:0]$13523 3'000 + assign $1\ren_delay$12$next[2:0]$13117 3'000 case - assign $1\ren_delay$12$next[2:0]$13523 \msr__ren + assign $1\ren_delay$12$next[2:0]$13117 \msr__ren end sync always - update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13522 + update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13116 end - attribute \src "libresoc.v:193320.3-193329.6" - process $proc$libresoc.v:193320$13524 + attribute \src "libresoc.v:194539.3-194548.6" + process $proc$libresoc.v:194539$13118 assign { } { } assign { } { } assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] - attribute \src "libresoc.v:193321.5-193321.29" + attribute \src "libresoc.v:194540.5-194540.29" switch \initial - attribute \src "libresoc.v:193321.9-193321.17" + attribute \src "libresoc.v:194540.9-194540.17" case 1'1 case end @@ -403482,15 +368719,15 @@ module \state sync always update \msr__data_o $0\msr__data_o[63:0] end - connect \$10 $or$libresoc.v:193204$13499_Y - connect \$13 $reduce_or$libresoc.v:193205$13500_Y - connect \$15 $or$libresoc.v:193206$13501_Y - connect \$17 $or$libresoc.v:193207$13502_Y - connect \$20 $reduce_or$libresoc.v:193208$13503_Y - connect \$22 $or$libresoc.v:193209$13504_Y - connect \$24 $or$libresoc.v:193210$13505_Y - connect \$6 $reduce_or$libresoc.v:193211$13506_Y - connect \$8 $or$libresoc.v:193212$13507_Y + connect \$10 $or$libresoc.v:194423$13093_Y + connect \$13 $reduce_or$libresoc.v:194424$13094_Y + connect \$15 $or$libresoc.v:194425$13095_Y + connect \$17 $or$libresoc.v:194426$13096_Y + connect \$20 $reduce_or$libresoc.v:194427$13097_Y + connect \$22 $or$libresoc.v:194428$13098_Y + connect \$24 $or$libresoc.v:194429$13099_Y + connect \$6 $reduce_or$libresoc.v:194430$13100_Y + connect \$8 $or$libresoc.v:194431$13101_Y connect \reg_2_d_wr12__data_i \data_i connect \reg_1_d_wr11__data_i \data_i connect \reg_0_d_wr10__data_i \data_i @@ -403511,37 +368748,37 @@ module \state connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren end -attribute \src "libresoc.v:193353.1-193411.10" +attribute \src "libresoc.v:194572.1-194630.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" attribute \generator "nMigen" module \sto_l - attribute \src "libresoc.v:193354.7-193354.20" + attribute \src "libresoc.v:194573.7-194573.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193399.3-193407.6" - wire $0\q_int$next[0:0]$13541 - attribute \src "libresoc.v:193397.3-193398.27" + attribute \src "libresoc.v:194618.3-194626.6" + wire $0\q_int$next[0:0]$13135 + attribute \src "libresoc.v:194616.3-194617.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:193399.3-193407.6" - wire $1\q_int$next[0:0]$13542 - attribute \src "libresoc.v:193376.7-193376.19" + attribute \src "libresoc.v:194618.3-194626.6" + wire $1\q_int$next[0:0]$13136 + attribute \src "libresoc.v:194595.7-194595.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:193389.17-193389.96" - wire $and$libresoc.v:193389$13531_Y - attribute \src "libresoc.v:193394.17-193394.96" - wire $and$libresoc.v:193394$13536_Y - attribute \src "libresoc.v:193391.18-193391.93" - wire $not$libresoc.v:193391$13533_Y - attribute \src "libresoc.v:193393.17-193393.92" - wire $not$libresoc.v:193393$13535_Y - attribute \src "libresoc.v:193396.17-193396.92" - wire $not$libresoc.v:193396$13538_Y - attribute \src "libresoc.v:193390.18-193390.98" - wire $or$libresoc.v:193390$13532_Y - attribute \src "libresoc.v:193392.18-193392.99" - wire $or$libresoc.v:193392$13534_Y - attribute \src "libresoc.v:193395.17-193395.97" - wire $or$libresoc.v:193395$13537_Y + attribute \src "libresoc.v:194608.17-194608.96" + wire $and$libresoc.v:194608$13125_Y + attribute \src "libresoc.v:194613.17-194613.96" + wire $and$libresoc.v:194613$13130_Y + attribute \src "libresoc.v:194610.18-194610.93" + wire $not$libresoc.v:194610$13127_Y + attribute \src "libresoc.v:194612.17-194612.92" + wire $not$libresoc.v:194612$13129_Y + attribute \src "libresoc.v:194615.17-194615.92" + wire $not$libresoc.v:194615$13132_Y + attribute \src "libresoc.v:194609.18-194609.98" + wire $or$libresoc.v:194609$13126_Y + attribute \src "libresoc.v:194611.18-194611.99" + wire $or$libresoc.v:194611$13128_Y + attribute \src "libresoc.v:194614.17-194614.97" + wire $or$libresoc.v:194614$13131_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -403558,11 +368795,11 @@ module \sto_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:193354.7-193354.15" + attribute \src "libresoc.v:194573.7-194573.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -403579,7 +368816,7 @@ module \sto_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193389$13531 + cell $and $and$libresoc.v:194608$13125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -403587,10 +368824,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193389$13531_Y + connect \Y $and$libresoc.v:194608$13125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193394$13536 + cell $and $and$libresoc.v:194613$13130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -403598,34 +368835,34 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193394$13536_Y + connect \Y $and$libresoc.v:194613$13130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193391$13533 + cell $not $not$libresoc.v:194610$13127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_sto - connect \Y $not$libresoc.v:193391$13533_Y + connect \Y $not$libresoc.v:194610$13127_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193393$13535 + cell $not $not$libresoc.v:194612$13129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:193393$13535_Y + connect \Y $not$libresoc.v:194612$13129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193396$13538 + cell $not $not$libresoc.v:194615$13132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:193396$13538_Y + connect \Y $not$libresoc.v:194615$13132_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193390$13532 + cell $or $or$libresoc.v:194609$13126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -403633,10 +368870,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_sto - connect \Y $or$libresoc.v:193390$13532_Y + connect \Y $or$libresoc.v:194609$13126_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193392$13534 + cell $or $or$libresoc.v:194611$13128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -403644,10 +368881,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_sto connect \B \q_int - connect \Y $or$libresoc.v:193392$13534_Y + connect \Y $or$libresoc.v:194611$13128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193395$13537 + cell $or $or$libresoc.v:194614$13131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -403655,39 +368892,39 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_sto - connect \Y $or$libresoc.v:193395$13537_Y + connect \Y $or$libresoc.v:194614$13131_Y end - attribute \src "libresoc.v:193354.7-193354.20" - process $proc$libresoc.v:193354$13543 + attribute \src "libresoc.v:194573.7-194573.20" + process $proc$libresoc.v:194573$13137 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193376.7-193376.19" - process $proc$libresoc.v:193376$13544 + attribute \src "libresoc.v:194595.7-194595.19" + process $proc$libresoc.v:194595$13138 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:193397.3-193398.27" - process $proc$libresoc.v:193397$13539 + attribute \src "libresoc.v:194616.3-194617.27" + process $proc$libresoc.v:194616$13133 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:193399.3-193407.6" - process $proc$libresoc.v:193399$13540 + attribute \src "libresoc.v:194618.3-194626.6" + process $proc$libresoc.v:194618$13134 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13541 $1\q_int$next[0:0]$13542 - attribute \src "libresoc.v:193400.5-193400.29" + assign $0\q_int$next[0:0]$13135 $1\q_int$next[0:0]$13136 + attribute \src "libresoc.v:194619.5-194619.29" switch \initial - attribute \src "libresoc.v:193400.9-193400.17" + attribute \src "libresoc.v:194619.9-194619.17" case 1'1 case end @@ -403696,26 +368933,26 @@ module \sto_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13542 1'0 + assign $1\q_int$next[0:0]$13136 1'0 case - assign $1\q_int$next[0:0]$13542 \$5 + assign $1\q_int$next[0:0]$13136 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13541 + update \q_int$next $0\q_int$next[0:0]$13135 end - connect \$9 $and$libresoc.v:193389$13531_Y - connect \$11 $or$libresoc.v:193390$13532_Y - connect \$13 $not$libresoc.v:193391$13533_Y - connect \$15 $or$libresoc.v:193392$13534_Y - connect \$1 $not$libresoc.v:193393$13535_Y - connect \$3 $and$libresoc.v:193394$13536_Y - connect \$5 $or$libresoc.v:193395$13537_Y - connect \$7 $not$libresoc.v:193396$13538_Y + connect \$9 $and$libresoc.v:194608$13125_Y + connect \$11 $or$libresoc.v:194609$13126_Y + connect \$13 $not$libresoc.v:194610$13127_Y + connect \$15 $or$libresoc.v:194611$13128_Y + connect \$1 $not$libresoc.v:194612$13129_Y + connect \$3 $and$libresoc.v:194613$13130_Y + connect \$5 $or$libresoc.v:194614$13131_Y + connect \$7 $not$libresoc.v:194615$13132_Y connect \qlq_sto \$15 connect \qn_sto \$13 connect \q_sto \$11 end -attribute \src "libresoc.v:193416.1-194641.10" +attribute \src "libresoc.v:194635.1-195728.10" attribute \cells_not_processed 1 attribute \top 1 attribute \nmigen.hierarchy "test_issuer" @@ -403729,36 +368966,36 @@ module \test_issuer wire output 6 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 8 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:230" wire output 5 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 400 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" + wire input 356 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" - wire width 2 input 402 \clk_sel_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:224" + wire width 2 input 358 \clk_sel_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:229" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 340 \dbus__ack + wire input 296 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 334 \dbus__adr + wire width 45 output 290 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 2 input 344 \dbus__bte + wire width 2 input 300 \dbus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 3 input 343 \dbus__cti + wire width 3 input 299 \dbus__cti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 338 \dbus__cyc + wire output 294 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 336 \dbus__dat_r + wire width 64 input 292 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 335 \dbus__dat_w + wire width 64 output 291 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 342 \dbus__err + wire input 298 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 337 \dbus__sel + wire width 8 output 293 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 339 \dbus__stb + wire output 295 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 341 \dbus__we + wire output 297 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 19 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403964,65 +369201,65 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 120 \gpio_s7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 329 \ibus__ack + wire input 285 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 323 \ibus__adr + wire width 45 output 279 \ibus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 2 input 333 \ibus__bte + wire width 2 input 289 \ibus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 3 input 332 \ibus__cti + wire width 3 input 288 \ibus__cti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 327 \ibus__cyc + wire output 283 \ibus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 325 \ibus__dat_r + wire width 64 input 281 \ibus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 324 \ibus__dat_w + wire width 64 input 280 \ibus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 331 \ibus__err + wire input 287 \ibus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 326 \ibus__sel + wire width 8 output 282 \ibus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 328 \ibus__stb + wire output 284 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 330 \ibus__we + wire input 286 \ibus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 387 \icp_wb__ack + wire output 343 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 381 \icp_wb__adr + wire width 28 input 337 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 385 \icp_wb__cyc + wire input 341 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 383 \icp_wb__dat_r + wire width 32 output 339 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 382 \icp_wb__dat_w + wire width 32 input 338 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 389 \icp_wb__err + wire input 345 \icp_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 384 \icp_wb__sel + wire width 4 input 340 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 386 \icp_wb__stb + wire input 342 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 388 \icp_wb__we + wire input 344 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 396 \ics_wb__ack + wire output 352 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 390 \ics_wb__adr + wire width 28 input 346 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 394 \ics_wb__cyc + wire input 350 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 392 \ics_wb__dat_r + wire width 32 output 348 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 391 \ics_wb__dat_w + wire width 32 input 347 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 398 \ics_wb__err + wire input 354 \ics_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 4 input 393 \ics_wb__sel + wire width 4 input 349 \ics_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 395 \ics_wb__stb + wire input 351 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 397 \ics_wb__we + wire input 353 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 399 \int_level_i + wire width 16 input 355 \int_level_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire input 17 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" @@ -404041,7 +369278,7 @@ module \test_issuer wire output 15 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 16 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:231" wire input 3 \memerr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 121 \mspi0_clk__core__o @@ -404060,491 +369297,403 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 126 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \mspi1_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 130 \mspi1_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \mspi1_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 132 \mspi1_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 135 \mspi1_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \mspi1_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \mspi1_mosi__core__o + wire input 135 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 134 \mspi1_mosi__pad__o + wire output 136 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \mtwi_scl__core__o + wire output 129 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 144 \mtwi_scl__pad__o + wire input 130 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 137 \mtwi_sda__core__i + wire input 131 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \mtwi_sda__core__o + wire input 132 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \mtwi_sda__core__oe + wire output 133 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \mtwi_sda__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 141 \mtwi_sda__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 142 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 405 \pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 134 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + wire width 64 input 361 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 1 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:226" wire width 64 output 2 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" - wire output 403 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" + wire output 359 \pll_18_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" wire \pll_clk_24_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" wire \pll_clk_pll_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" - wire output 404 \pll_lck_o + wire output 360 \pll_lck_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" wire \pll_pll_18_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1096" wire \pllclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1096" wire \pllclk_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" + wire input 357 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \pwm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 146 \pwm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \pwm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 148 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 401 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sd0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 156 \sd0_clk__pad__o + wire input 187 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 149 \sd0_cmd__core__i + wire output 188 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sd0_cmd__core__o + wire input 223 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sd0_cmd__core__oe + wire output 224 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sd0_cmd__pad__i + wire input 225 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 153 \sd0_cmd__pad__o + wire output 226 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 154 \sd0_cmd__pad__oe + wire input 227 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 157 \sd0_data0__core__i + wire output 228 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sd0_data0__core__o + wire input 189 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sd0_data0__core__oe + wire output 190 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sd0_data0__pad__i + wire input 191 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 161 \sd0_data0__pad__o + wire output 192 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 162 \sd0_data0__pad__oe + wire input 193 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 163 \sd0_data1__core__i + wire output 194 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 164 \sd0_data1__core__o + wire input 195 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 165 \sd0_data1__core__oe + wire output 196 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 166 \sd0_data1__pad__i + wire input 197 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \sd0_data1__pad__o + wire output 198 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \sd0_data1__pad__oe + wire input 199 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \sd0_data2__core__i + wire output 200 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 170 \sd0_data2__core__o + wire input 201 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 171 \sd0_data2__core__oe + wire output 202 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 172 \sd0_data2__pad__i + wire input 203 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \sd0_data2__pad__o + wire output 204 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \sd0_data2__pad__oe + wire input 205 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \sd0_data3__core__i + wire output 206 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 176 \sd0_data3__core__o + wire input 207 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 177 \sd0_data3__core__oe + wire output 208 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 178 \sd0_data3__pad__i + wire input 209 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \sd0_data3__pad__o + wire output 210 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \sd0_data3__pad__oe + wire input 217 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 231 \sdr_a_0__core__o + wire output 218 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sdr_a_0__pad__o + wire input 213 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 267 \sdr_a_10__core__o + wire output 214 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_a_10__pad__o + wire input 211 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 269 \sdr_a_11__core__o + wire output 212 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_a_11__pad__o + wire input 221 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 271 \sdr_a_12__core__o + wire output 222 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_a_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 233 \sdr_a_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sdr_a_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 235 \sdr_a_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sdr_a_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 237 \sdr_a_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sdr_a_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 239 \sdr_a_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sdr_a_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 241 \sdr_a_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sdr_a_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 243 \sdr_a_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sdr_a_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 245 \sdr_a_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sdr_a_7__pad__o + wire input 137 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 247 \sdr_a_8__core__o + wire output 138 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_a_8__pad__o + wire input 229 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 249 \sdr_a_9__core__o + wire output 230 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_a_9__pad__o + wire output 139 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 251 \sdr_ba_0__core__o + wire input 140 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_ba_0__pad__o + wire input 141 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 253 \sdr_ba_1__core__o + wire input 142 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_ba_1__pad__o + wire output 143 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 261 \sdr_cas_n__core__o + wire output 144 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_cas_n__pad__o + wire output 243 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 257 \sdr_cke__core__o + wire input 244 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_cke__pad__o + wire input 245 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 255 \sdr_clock__core__o + wire input 246 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_clock__pad__o + wire output 247 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 265 \sdr_cs_n__core__o + wire output 248 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_cs_n__pad__o + wire output 249 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 181 \sdr_dm_0__core__o + wire input 250 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \sdr_dm_0__pad__o + wire input 251 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 273 \sdr_dm_1__core__o + wire input 252 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_dm_1__pad__o + wire output 253 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \sdr_dq_0__core__i + wire output 254 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 184 \sdr_dq_0__core__o + wire output 255 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 185 \sdr_dq_0__core__oe + wire input 256 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 186 \sdr_dq_0__pad__i + wire input 257 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \sdr_dq_0__pad__o + wire input 258 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \sdr_dq_0__pad__oe + wire output 259 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_dq_10__core__i + wire output 260 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 288 \sdr_dq_10__core__o + wire output 261 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 289 \sdr_dq_10__core__oe + wire input 262 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 290 \sdr_dq_10__pad__i + wire input 263 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_dq_10__pad__o + wire input 264 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_dq_10__pad__oe + wire output 265 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_dq_11__core__i + wire output 266 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 294 \sdr_dq_11__core__o + wire output 267 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 295 \sdr_dq_11__core__oe + wire input 268 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 296 \sdr_dq_11__pad__i + wire input 269 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_11__pad__o + wire input 270 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_dq_11__pad__oe + wire output 271 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_dq_12__core__i + wire output 272 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 300 \sdr_dq_12__core__o + wire output 273 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 301 \sdr_dq_12__core__oe + wire input 274 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 302 \sdr_dq_12__pad__i + wire input 275 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_12__pad__o + wire input 276 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dq_12__pad__oe + wire output 277 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_13__core__i + wire output 278 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 306 \sdr_dq_13__core__o + wire output 145 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 307 \sdr_dq_13__core__oe + wire input 146 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 308 \sdr_dq_13__pad__i + wire input 147 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_13__pad__o + wire input 148 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_13__pad__oe + wire output 149 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_14__core__i + wire output 150 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 312 \sdr_dq_14__core__o + wire output 151 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 313 \sdr_dq_14__core__oe + wire input 152 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 314 \sdr_dq_14__pad__i + wire input 153 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_14__pad__o + wire input 154 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_14__pad__oe + wire output 155 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_15__core__i + wire output 156 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 318 \sdr_dq_15__core__o + wire output 157 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 319 \sdr_dq_15__core__oe + wire input 158 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 320 \sdr_dq_15__pad__i + wire input 159 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 321 \sdr_dq_15__pad__o + wire input 160 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 322 \sdr_dq_15__pad__oe + wire output 161 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \sdr_dq_1__core__i + wire output 162 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 190 \sdr_dq_1__core__o + wire output 163 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 191 \sdr_dq_1__core__oe + wire input 164 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 192 \sdr_dq_1__pad__i + wire input 165 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \sdr_dq_1__pad__o + wire input 166 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \sdr_dq_1__pad__oe + wire output 167 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \sdr_dq_2__core__i + wire output 168 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 196 \sdr_dq_2__core__o + wire output 169 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 197 \sdr_dq_2__core__oe + wire input 170 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 198 \sdr_dq_2__pad__i + wire input 171 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \sdr_dq_2__pad__o + wire input 172 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \sdr_dq_2__pad__oe + wire output 173 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \sdr_dq_3__core__i + wire output 174 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 202 \sdr_dq_3__core__o + wire output 175 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 203 \sdr_dq_3__core__oe + wire input 176 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 204 \sdr_dq_3__pad__i + wire input 177 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \sdr_dq_3__pad__o + wire input 178 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \sdr_dq_3__pad__oe + wire output 179 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \sdr_dq_4__core__i + wire output 180 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 208 \sdr_dq_4__core__o + wire output 181 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 209 \sdr_dq_4__core__oe + wire input 182 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 210 \sdr_dq_4__pad__i + wire input 183 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \sdr_dq_4__pad__o + wire input 184 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \sdr_dq_4__pad__oe + wire output 185 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \sdr_dq_5__core__i + wire output 186 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 214 \sdr_dq_5__core__o + wire output 231 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 215 \sdr_dq_5__core__oe + wire input 232 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 216 \sdr_dq_5__pad__i + wire input 233 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \sdr_dq_5__pad__o + wire input 234 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \sdr_dq_5__pad__oe + wire output 235 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \sdr_dq_6__core__i + wire output 236 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 220 \sdr_dq_6__core__o + wire output 237 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 221 \sdr_dq_6__core__oe + wire input 238 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 222 \sdr_dq_6__pad__i + wire input 239 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \sdr_dq_6__pad__o + wire input 240 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \sdr_dq_6__pad__oe + wire output 241 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \sdr_dq_7__core__i + wire output 242 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 226 \sdr_dq_7__core__o + wire input 215 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 227 \sdr_dq_7__core__oe + wire output 216 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 228 \sdr_dq_7__pad__i + wire input 219 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \sdr_dq_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sdr_dq_7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_dq_8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 276 \sdr_dq_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 277 \sdr_dq_8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 278 \sdr_dq_8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_dq_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_dq_8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_dq_9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 282 \sdr_dq_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 283 \sdr_dq_9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 284 \sdr_dq_9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_dq_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_dq_9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 259 \sdr_ras_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_ras_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 263 \sdr_we_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_we_n__pad__o + wire output 220 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 352 \sram4k_0_wb__ack + wire output 308 \sram4k_0_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 345 \sram4k_0_wb__adr + wire width 9 input 301 \sram4k_0_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 349 \sram4k_0_wb__cyc + wire input 305 \sram4k_0_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 347 \sram4k_0_wb__dat_r + wire width 64 output 303 \sram4k_0_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 346 \sram4k_0_wb__dat_w + wire width 64 input 302 \sram4k_0_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 353 \sram4k_0_wb__err + wire input 309 \sram4k_0_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 348 \sram4k_0_wb__sel + wire width 8 input 304 \sram4k_0_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 350 \sram4k_0_wb__stb + wire input 306 \sram4k_0_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 351 \sram4k_0_wb__we + wire input 307 \sram4k_0_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 361 \sram4k_1_wb__ack + wire output 317 \sram4k_1_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 354 \sram4k_1_wb__adr + wire width 9 input 310 \sram4k_1_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 358 \sram4k_1_wb__cyc + wire input 314 \sram4k_1_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 356 \sram4k_1_wb__dat_r + wire width 64 output 312 \sram4k_1_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 355 \sram4k_1_wb__dat_w + wire width 64 input 311 \sram4k_1_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 362 \sram4k_1_wb__err + wire input 318 \sram4k_1_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 357 \sram4k_1_wb__sel + wire width 8 input 313 \sram4k_1_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 359 \sram4k_1_wb__stb + wire input 315 \sram4k_1_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 360 \sram4k_1_wb__we + wire input 316 \sram4k_1_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 370 \sram4k_2_wb__ack + wire output 326 \sram4k_2_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 363 \sram4k_2_wb__adr + wire width 9 input 319 \sram4k_2_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 367 \sram4k_2_wb__cyc + wire input 323 \sram4k_2_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 365 \sram4k_2_wb__dat_r + wire width 64 output 321 \sram4k_2_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 364 \sram4k_2_wb__dat_w + wire width 64 input 320 \sram4k_2_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 371 \sram4k_2_wb__err + wire input 327 \sram4k_2_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 366 \sram4k_2_wb__sel + wire width 8 input 322 \sram4k_2_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 368 \sram4k_2_wb__stb + wire input 324 \sram4k_2_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 369 \sram4k_2_wb__we + wire input 325 \sram4k_2_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 379 \sram4k_3_wb__ack + wire output 335 \sram4k_3_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 372 \sram4k_3_wb__adr + wire width 9 input 328 \sram4k_3_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 376 \sram4k_3_wb__cyc + wire input 332 \sram4k_3_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 374 \sram4k_3_wb__dat_r + wire width 64 output 330 \sram4k_3_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 373 \sram4k_3_wb__dat_w + wire width 64 input 329 \sram4k_3_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 380 \sram4k_3_wb__err + wire input 336 \sram4k_3_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 375 \sram4k_3_wb__sel + wire width 8 input 331 \sram4k_3_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 377 \sram4k_3_wb__stb + wire input 333 \sram4k_3_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 378 \sram4k_3_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 334 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire \ti_coresync_clk attribute \module_not_derived 1 - attribute \src "libresoc.v:194239.7-194245.4" + attribute \src "libresoc.v:195370.7-195376.4" cell \pll \pll connect \clk_24_i \pll_clk_24_i connect \clk_pll_o \pll_clk_pll_o @@ -404553,7 +369702,7 @@ module \test_issuer connect \pll_lck_o \pll_lck_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:194246.6-194635.4" + attribute \src "libresoc.v:195377.6-195722.4" cell \ti \ti connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -404713,14 +369862,6 @@ module \test_issuer connect \mspi0_miso__pad__i \mspi0_miso__pad__i connect \mspi0_mosi__core__o \mspi0_mosi__core__o connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o - connect \mspi1_clk__core__o \mspi1_clk__core__o - connect \mspi1_clk__pad__o \mspi1_clk__pad__o - connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o - connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o - connect \mspi1_miso__core__i \mspi1_miso__core__i - connect \mspi1_miso__pad__i \mspi1_miso__pad__i - connect \mspi1_mosi__core__o \mspi1_mosi__core__o - connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o connect \mtwi_scl__core__o \mtwi_scl__core__o connect \mtwi_scl__pad__o \mtwi_scl__pad__o connect \mtwi_sda__core__i \mtwi_sda__core__i @@ -404732,43 +369873,7 @@ module \test_issuer connect \pc_i \pc_i connect \pc_i_ok \pc_i_ok connect \pc_o \pc_o - connect \pwm_0__core__o \pwm_0__core__o - connect \pwm_0__pad__o \pwm_0__pad__o - connect \pwm_1__core__o \pwm_1__core__o - connect \pwm_1__pad__o \pwm_1__pad__o connect \rst \rst - connect \sd0_clk__core__o \sd0_clk__core__o - connect \sd0_clk__pad__o \sd0_clk__pad__o - connect \sd0_cmd__core__i \sd0_cmd__core__i - connect \sd0_cmd__core__o \sd0_cmd__core__o - connect \sd0_cmd__core__oe \sd0_cmd__core__oe - connect \sd0_cmd__pad__i \sd0_cmd__pad__i - connect \sd0_cmd__pad__o \sd0_cmd__pad__o - connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe - connect \sd0_data0__core__i \sd0_data0__core__i - connect \sd0_data0__core__o \sd0_data0__core__o - connect \sd0_data0__core__oe \sd0_data0__core__oe - connect \sd0_data0__pad__i \sd0_data0__pad__i - connect \sd0_data0__pad__o \sd0_data0__pad__o - connect \sd0_data0__pad__oe \sd0_data0__pad__oe - connect \sd0_data1__core__i \sd0_data1__core__i - connect \sd0_data1__core__o \sd0_data1__core__o - connect \sd0_data1__core__oe \sd0_data1__core__oe - connect \sd0_data1__pad__i \sd0_data1__pad__i - connect \sd0_data1__pad__o \sd0_data1__pad__o - connect \sd0_data1__pad__oe \sd0_data1__pad__oe - connect \sd0_data2__core__i \sd0_data2__core__i - connect \sd0_data2__core__o \sd0_data2__core__o - connect \sd0_data2__core__oe \sd0_data2__core__oe - connect \sd0_data2__pad__i \sd0_data2__pad__i - connect \sd0_data2__pad__o \sd0_data2__pad__o - connect \sd0_data2__pad__oe \sd0_data2__pad__oe - connect \sd0_data3__core__i \sd0_data3__core__i - connect \sd0_data3__core__o \sd0_data3__core__o - connect \sd0_data3__core__oe \sd0_data3__core__oe - connect \sd0_data3__pad__i \sd0_data3__pad__i - connect \sd0_data3__pad__o \sd0_data3__pad__o - connect \sd0_data3__pad__oe \sd0_data3__pad__oe connect \sdr_a_0__core__o \sdr_a_0__core__o connect \sdr_a_0__pad__o \sdr_a_0__pad__o connect \sdr_a_10__core__o \sdr_a_10__core__o @@ -404950,1980 +370055,1836 @@ module \test_issuer connect \pll_clk_24_i \clk connect \pllclk_clk \pll_clk_pll_o end -attribute \src "libresoc.v:194645.1-199858.10" +attribute \src "libresoc.v:195732.1-200984.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti" attribute \generator "nMigen" module \ti - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $0\core_asmcode$next[7:0]$14042 - attribute \src "libresoc.v:197237.3-197238.41" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 8 $0\core_asmcode$next[7:0]$13623 + attribute \src "libresoc.v:198032.3-198033.41" wire width 8 $0\core_asmcode[7:0] - attribute \src "libresoc.v:198140.3-198164.6" - wire $0\core_bigendian_i$10$next[0:0]$13837 - attribute \src "libresoc.v:197367.3-197368.57" - wire $0\core_bigendian_i$10[0:0]$13756 - attribute \src "libresoc.v:194920.7-194920.35" - wire $0\core_bigendian_i$10[0:0]$14249 - attribute \src "libresoc.v:198723.3-198735.6" + attribute \src "libresoc.v:198909.3-198940.6" + wire $0\core_bigendian_i$10$next[0:0]$13420 + attribute \src "libresoc.v:198162.3-198163.57" + wire $0\core_bigendian_i$10[0:0]$13350 + attribute \src "libresoc.v:196007.7-196007.35" + wire $0\core_bigendian_i$10[0:0]$13771 + attribute \src "libresoc.v:199570.3-199582.6" wire width 3 $0\core_cia__ren[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 64 $0\core_core_core_cia$next[63:0]$14043 - attribute \src "libresoc.v:197311.3-197312.53" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 64 $0\core_core_core_cia$next[63:0]$13624 + attribute \src "libresoc.v:198106.3-198107.53" wire width 64 $0\core_core_core_cia[63:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $0\core_core_core_cr_rd$next[7:0]$14044 - attribute \src "libresoc.v:197355.3-197356.57" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$13625 + attribute \src "libresoc.v:198150.3-198151.57" wire width 8 $0\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_cr_rd_ok$next[0:0]$14045 - attribute \src "libresoc.v:197357.3-197358.63" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$13626 + attribute \src "libresoc.v:198152.3-198153.63" wire $0\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $0\core_core_core_cr_wr$next[7:0]$14046 - attribute \src "libresoc.v:197359.3-197360.57" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$13627 + attribute \src "libresoc.v:198154.3-198155.57" wire width 8 $0\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$3$next[0:0]$14047 - attribute \src "libresoc.v:197337.3-197338.75" - wire $0\core_core_core_exc_$signal$3[0:0]$13734 - attribute \src "libresoc.v:194946.7-194946.44" - wire $0\core_core_core_exc_$signal$3[0:0]$14257 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$4$next[0:0]$14048 - attribute \src "libresoc.v:197339.3-197340.75" - wire $0\core_core_core_exc_$signal$4[0:0]$13736 - attribute \src "libresoc.v:194950.7-194950.44" - wire $0\core_core_core_exc_$signal$4[0:0]$14259 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$5$next[0:0]$14049 - attribute \src "libresoc.v:197341.3-197342.75" - wire $0\core_core_core_exc_$signal$5[0:0]$13738 - attribute \src "libresoc.v:194954.7-194954.44" - wire $0\core_core_core_exc_$signal$5[0:0]$14261 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$6$next[0:0]$14050 - attribute \src "libresoc.v:197343.3-197344.75" - wire $0\core_core_core_exc_$signal$6[0:0]$13740 - attribute \src "libresoc.v:194958.7-194958.44" - wire $0\core_core_core_exc_$signal$6[0:0]$14263 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$7$next[0:0]$14051 - attribute \src "libresoc.v:197347.3-197348.75" - wire $0\core_core_core_exc_$signal$7[0:0]$13743 - attribute \src "libresoc.v:194962.7-194962.44" - wire $0\core_core_core_exc_$signal$7[0:0]$14265 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$8$next[0:0]$14052 - attribute \src "libresoc.v:197349.3-197350.75" - wire $0\core_core_core_exc_$signal$8[0:0]$13745 - attribute \src "libresoc.v:194966.7-194966.44" - wire $0\core_core_core_exc_$signal$8[0:0]$14267 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$9$next[0:0]$14053 - attribute \src "libresoc.v:197351.3-197352.75" - wire $0\core_core_core_exc_$signal$9[0:0]$13747 - attribute \src "libresoc.v:194970.7-194970.44" - wire $0\core_core_core_exc_$signal$9[0:0]$14269 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$next[0:0]$14054 - attribute \src "libresoc.v:197335.3-197336.71" - wire $0\core_core_core_exc_$signal[0:0]$13732 - attribute \src "libresoc.v:194944.7-194944.42" - wire $0\core_core_core_exc_$signal[0:0]$14255 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 14 $0\core_core_core_fn_unit$next[13:0]$14055 - attribute \src "libresoc.v:197317.3-197318.61" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_core_exc_$signal$3$next[0:0]$13628 + attribute \src "libresoc.v:198132.3-198133.75" + wire $0\core_core_core_exc_$signal$3[0:0]$13328 + attribute \src "libresoc.v:196033.7-196033.44" + wire $0\core_core_core_exc_$signal$3[0:0]$13779 + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_core_exc_$signal$4$next[0:0]$13629 + attribute \src "libresoc.v:198134.3-198135.75" + wire $0\core_core_core_exc_$signal$4[0:0]$13330 + attribute \src "libresoc.v:196037.7-196037.44" + wire $0\core_core_core_exc_$signal$4[0:0]$13781 + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_core_exc_$signal$5$next[0:0]$13630 + attribute \src "libresoc.v:198136.3-198137.75" + wire $0\core_core_core_exc_$signal$5[0:0]$13332 + attribute \src "libresoc.v:196041.7-196041.44" + wire $0\core_core_core_exc_$signal$5[0:0]$13783 + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_core_exc_$signal$6$next[0:0]$13631 + attribute \src "libresoc.v:198138.3-198139.75" + wire $0\core_core_core_exc_$signal$6[0:0]$13334 + attribute \src "libresoc.v:196045.7-196045.44" + wire $0\core_core_core_exc_$signal$6[0:0]$13785 + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_core_exc_$signal$7$next[0:0]$13632 + attribute \src "libresoc.v:198142.3-198143.75" + wire $0\core_core_core_exc_$signal$7[0:0]$13337 + attribute \src "libresoc.v:196049.7-196049.44" + wire $0\core_core_core_exc_$signal$7[0:0]$13787 + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_core_exc_$signal$8$next[0:0]$13633 + attribute \src "libresoc.v:198144.3-198145.75" + wire $0\core_core_core_exc_$signal$8[0:0]$13339 + attribute \src "libresoc.v:196053.7-196053.44" + wire $0\core_core_core_exc_$signal$8[0:0]$13789 + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_core_exc_$signal$9$next[0:0]$13634 + attribute \src "libresoc.v:198146.3-198147.75" + wire $0\core_core_core_exc_$signal$9[0:0]$13341 + attribute \src "libresoc.v:196057.7-196057.44" + wire $0\core_core_core_exc_$signal$9[0:0]$13791 + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_core_exc_$signal$next[0:0]$13635 + attribute \src "libresoc.v:198130.3-198131.71" + wire $0\core_core_core_exc_$signal[0:0]$13326 + attribute \src "libresoc.v:196031.7-196031.42" + wire $0\core_core_core_exc_$signal[0:0]$13777 + attribute \src "libresoc.v:200832.3-200949.6" + wire width 14 $0\core_core_core_fn_unit$next[13:0]$13636 + attribute \src "libresoc.v:198112.3-198113.61" wire width 14 $0\core_core_core_fn_unit[13:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 2 $0\core_core_core_input_carry$next[1:0]$14056 - attribute \src "libresoc.v:197331.3-197332.69" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$13637 + attribute \src "libresoc.v:198126.3-198127.69" wire width 2 $0\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 32 $0\core_core_core_insn$next[31:0]$14057 - attribute \src "libresoc.v:197313.3-197314.55" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 32 $0\core_core_core_insn$next[31:0]$13638 + attribute \src "libresoc.v:198108.3-198109.55" wire width 32 $0\core_core_core_insn[31:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_core_insn_type$next[6:0]$14058 - attribute \src "libresoc.v:197315.3-197316.65" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$13639 + attribute \src "libresoc.v:198110.3-198111.65" wire width 7 $0\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_is_32bit$next[0:0]$14059 - attribute \src "libresoc.v:197363.3-197364.63" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_core_is_32bit$next[0:0]$13640 + attribute \src "libresoc.v:198158.3-198159.63" wire $0\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 64 $0\core_core_core_msr$next[63:0]$14060 - attribute \src "libresoc.v:197309.3-197310.53" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 64 $0\core_core_core_msr$next[63:0]$13641 + attribute \src "libresoc.v:198104.3-198105.53" wire width 64 $0\core_core_core_msr[63:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_oe$next[0:0]$14061 - attribute \src "libresoc.v:197327.3-197328.51" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_core_oe$next[0:0]$13642 + attribute \src "libresoc.v:198122.3-198123.51" wire $0\core_core_core_oe[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_oe_ok$next[0:0]$14062 - attribute \src "libresoc.v:197329.3-197330.57" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_core_oe_ok$next[0:0]$13643 + attribute \src "libresoc.v:198124.3-198125.57" wire $0\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_rc$next[0:0]$14063 - attribute \src "libresoc.v:197321.3-197322.51" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_core_rc$next[0:0]$13644 + attribute \src "libresoc.v:198116.3-198117.51" wire $0\core_core_core_rc[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_rc_ok$next[0:0]$14064 - attribute \src "libresoc.v:197325.3-197326.57" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_core_rc_ok$next[0:0]$13645 + attribute \src "libresoc.v:198120.3-198121.57" wire $0\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 13 $0\core_core_core_trapaddr$next[12:0]$14065 - attribute \src "libresoc.v:197353.3-197354.63" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$13646 + attribute \src "libresoc.v:198148.3-198149.63" wire width 13 $0\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $0\core_core_core_traptype$next[7:0]$14066 - attribute \src "libresoc.v:197333.3-197334.63" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 8 $0\core_core_core_traptype$next[7:0]$13647 + attribute \src "libresoc.v:198128.3-198129.63" wire width 8 $0\core_core_core_traptype[7:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_cr_in1$next[6:0]$14067 - attribute \src "libresoc.v:197291.3-197292.49" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $0\core_core_cr_in1$next[6:0]$13648 + attribute \src "libresoc.v:198086.3-198087.49" wire width 7 $0\core_core_cr_in1[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_cr_in1_ok$next[0:0]$14068 - attribute \src "libresoc.v:197293.3-197294.55" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_cr_in1_ok$next[0:0]$13649 + attribute \src "libresoc.v:198088.3-198089.55" wire $0\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_cr_in2$1$next[6:0]$14069 - attribute \src "libresoc.v:197299.3-197300.55" - wire width 7 $0\core_core_cr_in2$1[6:0]$13712 - attribute \src "libresoc.v:195128.13-195128.41" - wire width 7 $0\core_core_cr_in2$1[6:0]$14286 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_cr_in2$next[6:0]$14070 - attribute \src "libresoc.v:197295.3-197296.49" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $0\core_core_cr_in2$1$next[6:0]$13650 + attribute \src "libresoc.v:198094.3-198095.55" + wire width 7 $0\core_core_cr_in2$1[6:0]$13306 + attribute \src "libresoc.v:196215.13-196215.41" + wire width 7 $0\core_core_cr_in2$1[6:0]$13808 + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $0\core_core_cr_in2$next[6:0]$13651 + attribute \src "libresoc.v:198090.3-198091.49" wire width 7 $0\core_core_cr_in2[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_cr_in2_ok$2$next[0:0]$14071 - attribute \src "libresoc.v:197303.3-197304.61" - wire $0\core_core_cr_in2_ok$2[0:0]$13715 - attribute \src "libresoc.v:195136.7-195136.37" - wire $0\core_core_cr_in2_ok$2[0:0]$14289 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_cr_in2_ok$next[0:0]$14072 - attribute \src "libresoc.v:197297.3-197298.55" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$13652 + attribute \src "libresoc.v:198098.3-198099.61" + wire $0\core_core_cr_in2_ok$2[0:0]$13309 + attribute \src "libresoc.v:196223.7-196223.37" + wire $0\core_core_cr_in2_ok$2[0:0]$13811 + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_cr_in2_ok$next[0:0]$13653 + attribute \src "libresoc.v:198092.3-198093.55" wire $0\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_cr_out$next[6:0]$14073 - attribute \src "libresoc.v:197305.3-197306.49" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $0\core_core_cr_out$next[6:0]$13654 + attribute \src "libresoc.v:198100.3-198101.49" wire width 7 $0\core_core_cr_out[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_cr_wr_ok$next[0:0]$14074 - attribute \src "libresoc.v:197361.3-197362.53" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_cr_wr_ok$next[0:0]$13655 + attribute \src "libresoc.v:198156.3-198157.53" wire $0\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $0\core_core_dststep$next[6:0]$13791 - attribute \src "libresoc.v:197227.3-197228.51" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 7 $0\core_core_dststep$next[6:0]$13385 + attribute \src "libresoc.v:198022.3-198023.51" wire width 7 $0\core_core_dststep[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_ea$next[6:0]$14075 - attribute \src "libresoc.v:197243.3-197244.41" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $0\core_core_ea$next[6:0]$13656 + attribute \src "libresoc.v:198038.3-198039.41" wire width 7 $0\core_core_ea[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $0\core_core_fast1$next[2:0]$14076 - attribute \src "libresoc.v:197273.3-197274.47" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 3 $0\core_core_fast1$next[2:0]$13657 + attribute \src "libresoc.v:198068.3-198069.47" wire width 3 $0\core_core_fast1[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_fast1_ok$next[0:0]$14077 - attribute \src "libresoc.v:197275.3-197276.53" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_fast1_ok$next[0:0]$13658 + attribute \src "libresoc.v:198070.3-198071.53" wire $0\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $0\core_core_fast2$next[2:0]$14078 - attribute \src "libresoc.v:197277.3-197278.47" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 3 $0\core_core_fast2$next[2:0]$13659 + attribute \src "libresoc.v:198072.3-198073.47" wire width 3 $0\core_core_fast2[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_fast2_ok$next[0:0]$14079 - attribute \src "libresoc.v:197281.3-197282.53" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_fast2_ok$next[0:0]$13660 + attribute \src "libresoc.v:198076.3-198077.53" wire $0\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $0\core_core_fasto1$next[2:0]$14080 - attribute \src "libresoc.v:197283.3-197284.49" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 3 $0\core_core_fasto1$next[2:0]$13661 + attribute \src "libresoc.v:198078.3-198079.49" wire width 3 $0\core_core_fasto1[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $0\core_core_fasto2$next[2:0]$14081 - attribute \src "libresoc.v:197287.3-197288.49" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 3 $0\core_core_fasto2$next[2:0]$13662 + attribute \src "libresoc.v:198082.3-198083.49" wire width 3 $0\core_core_fasto2[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_lk$next[0:0]$14082 - attribute \src "libresoc.v:197319.3-197320.41" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_lk$next[0:0]$13663 + attribute \src "libresoc.v:198114.3-198115.41" wire $0\core_core_lk[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $0\core_core_maxvl$next[6:0]$13792 - attribute \src "libresoc.v:197233.3-197234.47" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 7 $0\core_core_maxvl$next[6:0]$13386 + attribute \src "libresoc.v:198028.3-198029.47" wire width 7 $0\core_core_maxvl[6:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $0\core_core_pc$next[63:0]$13793 - attribute \src "libresoc.v:197205.3-197206.41" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 64 $0\core_core_pc$next[63:0]$13387 + attribute \src "libresoc.v:198000.3-198001.41" wire width 64 $0\core_core_pc[63:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_reg1$next[6:0]$14083 - attribute \src "libresoc.v:197247.3-197248.45" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $0\core_core_reg1$next[6:0]$13664 + attribute \src "libresoc.v:198042.3-198043.45" wire width 7 $0\core_core_reg1[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_reg1_ok$next[0:0]$14084 - attribute \src "libresoc.v:197249.3-197250.51" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_reg1_ok$next[0:0]$13665 + attribute \src "libresoc.v:198044.3-198045.51" wire $0\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_reg2$next[6:0]$14085 - attribute \src "libresoc.v:197251.3-197252.45" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $0\core_core_reg2$next[6:0]$13666 + attribute \src "libresoc.v:198046.3-198047.45" wire width 7 $0\core_core_reg2[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_reg2_ok$next[0:0]$14086 - attribute \src "libresoc.v:197253.3-197254.51" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_reg2_ok$next[0:0]$13667 + attribute \src "libresoc.v:198048.3-198049.51" wire $0\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_reg3$next[6:0]$14087 - attribute \src "libresoc.v:197255.3-197256.45" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $0\core_core_reg3$next[6:0]$13668 + attribute \src "libresoc.v:198050.3-198051.45" wire width 7 $0\core_core_reg3[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_reg3_ok$next[0:0]$14088 - attribute \src "libresoc.v:197259.3-197260.51" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_reg3_ok$next[0:0]$13669 + attribute \src "libresoc.v:198054.3-198055.51" wire $0\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_rego$next[6:0]$14089 - attribute \src "libresoc.v:197239.3-197240.45" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $0\core_core_rego$next[6:0]$13670 + attribute \src "libresoc.v:198034.3-198035.45" wire width 7 $0\core_core_rego[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 10 $0\core_core_spr1$next[9:0]$14090 - attribute \src "libresoc.v:197265.3-197266.45" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 10 $0\core_core_spr1$next[9:0]$13671 + attribute \src "libresoc.v:198060.3-198061.45" wire width 10 $0\core_core_spr1[9:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_spr1_ok$next[0:0]$14091 - attribute \src "libresoc.v:197267.3-197268.51" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_core_spr1_ok$next[0:0]$13672 + attribute \src "libresoc.v:198062.3-198063.51" wire $0\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 10 $0\core_core_spro$next[9:0]$14092 - attribute \src "libresoc.v:197261.3-197262.45" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 10 $0\core_core_spro$next[9:0]$13673 + attribute \src "libresoc.v:198056.3-198057.45" wire width 10 $0\core_core_spro[9:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $0\core_core_srcstep$next[6:0]$13794 - attribute \src "libresoc.v:197229.3-197230.51" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 7 $0\core_core_srcstep$next[6:0]$13388 + attribute \src "libresoc.v:198024.3-198025.51" wire width 7 $0\core_core_srcstep[6:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $0\core_core_subvl$next[1:0]$13795 - attribute \src "libresoc.v:197225.3-197226.47" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 2 $0\core_core_subvl$next[1:0]$13389 + attribute \src "libresoc.v:198020.3-198021.47" wire width 2 $0\core_core_subvl[1:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $0\core_core_svstep$next[1:0]$13796 - attribute \src "libresoc.v:197223.3-197224.49" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 2 $0\core_core_svstep$next[1:0]$13390 + attribute \src "libresoc.v:198018.3-198019.49" wire width 2 $0\core_core_svstep[1:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $0\core_core_vl$next[6:0]$13797 - attribute \src "libresoc.v:197231.3-197232.41" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 7 $0\core_core_vl$next[6:0]$13391 + attribute \src "libresoc.v:198026.3-198027.41" wire width 7 $0\core_core_vl[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $0\core_core_xer_in$next[2:0]$14093 - attribute \src "libresoc.v:197269.3-197270.49" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 3 $0\core_core_xer_in$next[2:0]$13674 + attribute \src "libresoc.v:198064.3-198065.49" wire width 3 $0\core_core_xer_in[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_cr_out_ok$next[0:0]$14094 - attribute \src "libresoc.v:197307.3-197308.45" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_cr_out_ok$next[0:0]$13675 + attribute \src "libresoc.v:198102.3-198103.45" wire $0\core_cr_out_ok[0:0] - attribute \src "libresoc.v:198308.3-198317.6" - wire width 64 $0\core_data_i$12[63:0]$13856 - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:199099.3-199108.6" + wire width 64 $0\core_data_i$12[63:0]$13434 + attribute \src "libresoc.v:199714.3-199797.6" wire width 64 $0\core_data_i[63:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $0\core_dec$next[63:0]$13798 - attribute \src "libresoc.v:197221.3-197222.33" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 64 $0\core_dec$next[63:0]$13392 + attribute \src "libresoc.v:198016.3-198017.33" wire width 64 $0\core_dec[63:0] - attribute \src "libresoc.v:198421.3-198430.6" + attribute \src "libresoc.v:199216.3-199225.6" wire width 5 $0\core_dmi__addr[4:0] - attribute \src "libresoc.v:198431.3-198440.6" + attribute \src "libresoc.v:199226.3-199235.6" wire $0\core_dmi__ren[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_ea_ok$next[0:0]$14095 - attribute \src "libresoc.v:197245.3-197246.37" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_ea_ok$next[0:0]$13676 + attribute \src "libresoc.v:198040.3-198041.37" wire $0\core_ea_ok[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire $0\core_eint$next[0:0]$13799 - attribute \src "libresoc.v:197219.3-197220.35" + attribute \src "libresoc.v:198825.3-198876.6" + wire $0\core_eint$next[0:0]$13393 + attribute \src "libresoc.v:198014.3-198015.35" wire $0\core_eint[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_fasto1_ok$next[0:0]$14096 - attribute \src "libresoc.v:197285.3-197286.45" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_fasto1_ok$next[0:0]$13677 + attribute \src "libresoc.v:198080.3-198081.45" wire $0\core_fasto1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_fasto2_ok$next[0:0]$14097 - attribute \src "libresoc.v:197289.3-197290.45" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_fasto2_ok$next[0:0]$13678 + attribute \src "libresoc.v:198084.3-198085.45" wire $0\core_fasto2_ok[0:0] - attribute \src "libresoc.v:198470.3-198479.6" + attribute \src "libresoc.v:199265.3-199274.6" wire width 8 $0\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:198509.3-198518.6" + attribute \src "libresoc.v:199304.3-199313.6" wire width 3 $0\core_full_rd__ren[2:0] - attribute \src "libresoc.v:198617.3-198631.6" - wire width 3 $0\core_issue__addr$13[2:0]$13896 - attribute \src "libresoc.v:198548.3-198562.6" + attribute \src "libresoc.v:199424.3-199446.6" + wire width 3 $0\core_issue__addr$13[2:0]$13474 + attribute \src "libresoc.v:199343.3-199361.6" wire width 3 $0\core_issue__addr[2:0] - attribute \src "libresoc.v:198647.3-198661.6" + attribute \src "libresoc.v:199470.3-199492.6" wire width 64 $0\core_issue__data_i[63:0] - attribute \src "libresoc.v:198563.3-198577.6" + attribute \src "libresoc.v:199362.3-199380.6" wire $0\core_issue__ren[0:0] - attribute \src "libresoc.v:198632.3-198646.6" + attribute \src "libresoc.v:199447.3-199469.6" wire $0\core_issue__wen[0:0] - attribute \src "libresoc.v:198354.3-198369.6" + attribute \src "libresoc.v:199145.3-199160.6" wire $0\core_issue_i[0:0] - attribute \src "libresoc.v:198329.3-198353.6" + attribute \src "libresoc.v:199120.3-199144.6" wire $0\core_ivalid_i[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $0\core_msr$next[63:0]$13800 - attribute \src "libresoc.v:197217.3-197218.33" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 64 $0\core_msr$next[63:0]$13394 + attribute \src "libresoc.v:198012.3-198013.33" wire width 64 $0\core_msr[63:0] - attribute \src "libresoc.v:198919.3-198934.6" + attribute \src "libresoc.v:199798.3-199813.6" wire width 3 $0\core_msr__ren[2:0] - attribute \src "libresoc.v:198119.3-198139.6" - wire width 32 $0\core_raw_insn_i$next[31:0]$13832 - attribute \src "libresoc.v:197389.3-197390.47" + attribute \src "libresoc.v:198877.3-198908.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$13416 + attribute \src "libresoc.v:198184.3-198185.47" wire width 32 $0\core_raw_insn_i[31:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_rego_ok$next[0:0]$14098 - attribute \src "libresoc.v:197241.3-197242.41" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_rego_ok$next[0:0]$13679 + attribute \src "libresoc.v:198036.3-198037.41" wire $0\core_rego_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_spro_ok$next[0:0]$14099 - attribute \src "libresoc.v:197263.3-197264.41" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_spro_ok$next[0:0]$13680 + attribute \src "libresoc.v:198058.3-198059.41" wire $0\core_spro_ok[0:0] - attribute \src "libresoc.v:199449.3-199479.6" + attribute \src "libresoc.v:200374.3-200424.6" wire $0\core_stopped_i[0:0] - attribute \src "libresoc.v:198761.3-198773.6" + attribute \src "libresoc.v:199608.3-199620.6" wire width 3 $0\core_sv__ren[2:0] - attribute \src "libresoc.v:198165.3-198189.6" - wire $0\core_sv_a_nz$next[0:0]$13842 - attribute \src "libresoc.v:197345.3-197346.41" + attribute \src "libresoc.v:198941.3-198972.6" + wire $0\core_sv_a_nz$next[0:0]$13424 + attribute \src "libresoc.v:198140.3-198141.41" wire $0\core_sv_a_nz[0:0] - attribute \src "libresoc.v:198298.3-198307.6" - wire width 3 $0\core_wen$11[2:0]$13853 - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:199089.3-199098.6" + wire width 3 $0\core_wen$11[2:0]$13431 + attribute \src "libresoc.v:199630.3-199713.6" wire width 3 $0\core_wen[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_xer_out$next[0:0]$14100 - attribute \src "libresoc.v:197271.3-197272.41" + attribute \src "libresoc.v:200832.3-200949.6" + wire $0\core_xer_out$next[0:0]$13681 + attribute \src "libresoc.v:198066.3-198067.41" wire $0\core_xer_out[0:0] - attribute \src "libresoc.v:197403.3-197404.43" + attribute \src "libresoc.v:198198.3-198199.43" wire $0\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $0\cur_cur_dststep$next[6:0]$13937 - attribute \src "libresoc.v:197387.3-197388.47" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $0\cur_cur_dststep$next[6:0]$13515 + attribute \src "libresoc.v:198182.3-198183.47" wire width 7 $0\cur_cur_dststep[6:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $0\cur_cur_maxvl$next[6:0]$13938 - attribute \src "libresoc.v:197395.3-197396.43" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $0\cur_cur_maxvl$next[6:0]$13516 + attribute \src "libresoc.v:198190.3-198191.43" wire width 7 $0\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $0\cur_cur_srcstep$next[6:0]$13939 - attribute \src "libresoc.v:197391.3-197392.47" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $0\cur_cur_srcstep$next[6:0]$13517 + attribute \src "libresoc.v:198186.3-198187.47" wire width 7 $0\cur_cur_srcstep[6:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $0\cur_cur_subvl$next[1:0]$13940 - attribute \src "libresoc.v:197385.3-197386.43" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 2 $0\cur_cur_subvl$next[1:0]$13518 + attribute \src "libresoc.v:198180.3-198181.43" wire width 2 $0\cur_cur_subvl[1:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $0\cur_cur_svstep$next[1:0]$13941 - attribute \src "libresoc.v:197383.3-197384.45" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 2 $0\cur_cur_svstep$next[1:0]$13519 + attribute \src "libresoc.v:198178.3-198179.45" wire width 2 $0\cur_cur_svstep[1:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $0\cur_cur_vl$next[6:0]$13942 - attribute \src "libresoc.v:197393.3-197394.37" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $0\cur_cur_vl$next[6:0]$13520 + attribute \src "libresoc.v:198188.3-198189.37" wire width 7 $0\cur_cur_vl[6:0] - attribute \src "libresoc.v:198480.3-198488.6" - wire $0\d_cr_delay$next[0:0]$13878 - attribute \src "libresoc.v:197279.3-197280.37" + attribute \src "libresoc.v:199275.3-199283.6" + wire $0\d_cr_delay$next[0:0]$13456 + attribute \src "libresoc.v:198074.3-198075.37" wire $0\d_cr_delay[0:0] - attribute \src "libresoc.v:198441.3-198449.6" - wire $0\d_reg_delay$next[0:0]$13872 - attribute \src "libresoc.v:197301.3-197302.39" + attribute \src "libresoc.v:199236.3-199244.6" + wire $0\d_reg_delay$next[0:0]$13450 + attribute \src "libresoc.v:198096.3-198097.39" wire $0\d_reg_delay[0:0] - attribute \src "libresoc.v:198519.3-198527.6" - wire $0\d_xer_delay$next[0:0]$13884 - attribute \src "libresoc.v:197257.3-197258.39" + attribute \src "libresoc.v:199314.3-199322.6" + wire $0\d_xer_delay$next[0:0]$13462 + attribute \src "libresoc.v:198052.3-198053.39" wire $0\d_xer_delay[0:0] - attribute \src "libresoc.v:199480.3-199510.6" + attribute \src "libresoc.v:200425.3-200475.6" wire $0\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:198499.3-198508.6" + attribute \src "libresoc.v:199294.3-199303.6" wire $0\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:198489.3-198498.6" + attribute \src "libresoc.v:199284.3-199293.6" wire width 64 $0\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:198460.3-198469.6" + attribute \src "libresoc.v:199255.3-199264.6" wire $0\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:198450.3-198459.6" + attribute \src "libresoc.v:199245.3-199254.6" wire width 64 $0\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:198538.3-198547.6" + attribute \src "libresoc.v:199333.3-199342.6" wire $0\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:198528.3-198537.6" + attribute \src "libresoc.v:199323.3-199332.6" wire width 64 $0\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:198037.3-198045.6" - wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13779 - attribute \src "libresoc.v:197215.3-197216.45" + attribute \src "libresoc.v:198788.3-198796.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13373 + attribute \src "libresoc.v:198010.3-198011.45" wire width 4 $0\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:198774.3-198782.6" - wire width 64 $0\dbg_dmi_din$next[63:0]$13919 - attribute \src "libresoc.v:197209.3-197210.39" + attribute \src "libresoc.v:199621.3-199629.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$13497 + attribute \src "libresoc.v:198004.3-198005.39" wire width 64 $0\dbg_dmi_din[63:0] - attribute \src "libresoc.v:198046.3-198054.6" - wire $0\dbg_dmi_req_i$next[0:0]$13782 - attribute \src "libresoc.v:197213.3-197214.43" + attribute \src "libresoc.v:198797.3-198805.6" + wire $0\dbg_dmi_req_i$next[0:0]$13376 + attribute \src "libresoc.v:198008.3-198009.43" wire $0\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:198689.3-198697.6" - wire $0\dbg_dmi_we_i$next[0:0]$13906 - attribute \src "libresoc.v:197211.3-197212.41" + attribute \src "libresoc.v:199536.3-199544.6" + wire $0\dbg_dmi_we_i$next[0:0]$13484 + attribute \src "libresoc.v:198006.3-198007.41" wire $0\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:198662.3-198677.6" - wire width 64 $0\dec2_cur_dec$next[63:0]$13901 - attribute \src "libresoc.v:197203.3-197204.41" + attribute \src "libresoc.v:199493.3-199512.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$13479 + attribute \src "libresoc.v:197998.3-197999.41" wire width 64 $0\dec2_cur_dec[63:0] - attribute \src "libresoc.v:198055.3-198063.6" - wire $0\dec2_cur_eint$next[0:0]$13785 - attribute \src "libresoc.v:197407.3-197408.43" + attribute \src "libresoc.v:198806.3-198814.6" + wire $0\dec2_cur_eint$next[0:0]$13379 + attribute \src "libresoc.v:198202.3-198203.43" wire $0\dec2_cur_eint[0:0] - attribute \src "libresoc.v:199192.3-199212.6" - wire width 64 $0\dec2_cur_msr$next[63:0]$13985 - attribute \src "libresoc.v:197377.3-197378.41" + attribute \src "libresoc.v:200071.3-200095.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$13563 + attribute \src "libresoc.v:198172.3-198173.41" wire width 64 $0\dec2_cur_msr[63:0] - attribute \src "libresoc.v:199039.3-199059.6" - wire width 64 $0\dec2_cur_pc$next[63:0]$13932 - attribute \src "libresoc.v:197397.3-197398.39" + attribute \src "libresoc.v:199918.3-199938.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$13510 + attribute \src "libresoc.v:198192.3-198193.39" wire width 64 $0\dec2_cur_pc[63:0] - attribute \src "libresoc.v:199232.3-199262.6" - wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13994 - attribute \src "libresoc.v:197373.3-197374.53" + attribute \src "libresoc.v:200119.3-200153.6" + wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13572 + attribute \src "libresoc.v:198168.3-198169.53" wire width 32 $0\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:198064.3-198073.6" - wire width 2 $0\delay$next[1:0]$13788 - attribute \src "libresoc.v:197405.3-197406.27" + attribute \src "libresoc.v:198815.3-198824.6" + wire width 2 $0\delay$next[1:0]$13382 + attribute \src "libresoc.v:198200.3-198201.27" wire width 2 $0\delay[1:0] - attribute \src "libresoc.v:198370.3-198404.6" - wire $0\exec_fsm_state$next[0:0]$13862 - attribute \src "libresoc.v:197323.3-197324.45" + attribute \src "libresoc.v:199161.3-199195.6" + wire $0\exec_fsm_state$next[0:0]$13440 + attribute \src "libresoc.v:198118.3-198119.45" wire $0\exec_fsm_state[0:0] - attribute \src "libresoc.v:198318.3-198328.6" + attribute \src "libresoc.v:199109.3-199119.6" wire $0\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:198250.3-198260.6" + attribute \src "libresoc.v:198973.3-199003.6" wire $0\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:198261.3-198276.6" + attribute \src "libresoc.v:199004.3-199043.6" wire $0\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:198405.3-198420.6" + attribute \src "libresoc.v:199196.3-199215.6" wire $0\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:199138.3-199191.6" - wire width 2 $0\fetch_fsm_state$next[1:0]$13977 - attribute \src "libresoc.v:197379.3-197380.47" + attribute \src "libresoc.v:200017.3-200070.6" + wire width 2 $0\fetch_fsm_state$next[1:0]$13555 + attribute \src "libresoc.v:198174.3-198175.47" wire width 2 $0\fetch_fsm_state[1:0] - attribute \src "libresoc.v:199702.3-199712.6" + attribute \src "libresoc.v:200729.3-200743.6" wire $0\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:199263.3-199273.6" + attribute \src "libresoc.v:200154.3-200176.6" wire $0\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:198944.3-198954.6" + attribute \src "libresoc.v:199823.3-199833.6" wire $0\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:199334.3-199349.6" + attribute \src "libresoc.v:200259.3-200274.6" wire $0\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:198578.3-198605.6" - wire width 2 $0\fsm_state$next[1:0]$13891 - attribute \src "libresoc.v:197235.3-197236.35" + attribute \src "libresoc.v:199381.3-199408.6" + wire width 2 $0\fsm_state$next[1:0]$13469 + attribute \src "libresoc.v:198030.3-198031.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:198955.3-198970.6" + attribute \src "libresoc.v:199834.3-199849.6" wire width 48 $0\imem_a_pc_i[47:0] - attribute \src "libresoc.v:198971.3-199004.6" + attribute \src "libresoc.v:199850.3-199883.6" wire $0\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199005.3-199038.6" + attribute \src "libresoc.v:199884.3-199917.6" wire $0\imem_f_valid_i[0:0] - attribute \src "libresoc.v:194646.7-194646.20" + attribute \src "libresoc.v:195733.7-195733.20" wire $0\initial[0:0] - attribute \src "libresoc.v:198190.3-198227.6" + attribute \src "libresoc.v:200744.3-200789.6" wire $0\insn_done[0:0] - attribute \src "libresoc.v:198277.3-198297.6" + attribute \src "libresoc.v:199044.3-199088.6" wire $0\is_last[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $0\issue_fsm_state$next[2:0]$14002 - attribute \src "libresoc.v:197371.3-197372.47" + attribute \src "libresoc.v:200275.3-200373.6" + wire width 3 $0\issue_fsm_state$next[2:0]$13580 + attribute \src "libresoc.v:198166.3-198167.47" wire width 3 $0\issue_fsm_state[2:0] - attribute \src "libresoc.v:198935.3-198943.6" - wire $0\jtag_dmi0__ack_o$next[0:0]$13925 - attribute \src "libresoc.v:197207.3-197208.49" + attribute \src "libresoc.v:199814.3-199822.6" + wire $0\jtag_dmi0__ack_o$next[0:0]$13503 + attribute \src "libresoc.v:198002.3-198003.49" wire $0\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:199099.3-199107.6" - wire width 64 $0\jtag_dmi0__dout$next[63:0]$13968 - attribute \src "libresoc.v:197409.3-197410.47" + attribute \src "libresoc.v:199978.3-199986.6" + wire width 64 $0\jtag_dmi0__dout$next[63:0]$13546 + attribute \src "libresoc.v:198204.3-198205.47" wire width 64 $0\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:199108.3-199137.6" - wire $0\msr_read$next[0:0]$13971 - attribute \src "libresoc.v:197381.3-197382.33" + attribute \src "libresoc.v:199987.3-200016.6" + wire $0\msr_read$next[0:0]$13549 + attribute \src "libresoc.v:198176.3-198177.33" wire $0\msr_read[0:0] - attribute \src "libresoc.v:198606.3-198616.6" + attribute \src "libresoc.v:199409.3-199423.6" wire width 64 $0\new_dec[63:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $0\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $0\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $0\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 2 $0\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 2 $0\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $0\new_svstate_vl[6:0] - attribute \src "libresoc.v:198678.3-198688.6" + attribute \src "libresoc.v:199513.3-199535.6" wire width 64 $0\new_tb[63:0] - attribute \src "libresoc.v:199213.3-199231.6" - wire width 64 $0\nia$next[63:0]$13990 - attribute \src "libresoc.v:197375.3-197376.23" + attribute \src "libresoc.v:200096.3-200118.6" + wire width 64 $0\nia$next[63:0]$13568 + attribute \src "libresoc.v:198170.3-198171.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:198707.3-198722.6" + attribute \src "libresoc.v:199554.3-199569.6" wire width 64 $0\pc[63:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $0\pc_changed$next[0:0]$14018 - attribute \src "libresoc.v:197369.3-197370.37" + attribute \src "libresoc.v:200476.3-200562.6" + wire $0\pc_changed$next[0:0]$13596 + attribute \src "libresoc.v:198164.3-198165.37" wire $0\pc_changed[0:0] - attribute \src "libresoc.v:198698.3-198706.6" - wire $0\pc_ok_delay$next[0:0]$13909 - attribute \src "libresoc.v:197401.3-197402.39" + attribute \src "libresoc.v:199545.3-199553.6" + wire $0\pc_ok_delay$next[0:0]$13487 + attribute \src "libresoc.v:198196.3-198197.39" wire $0\pc_ok_delay[0:0] - attribute \src "libresoc.v:198228.3-198238.6" + attribute \src "libresoc.v:200790.3-200808.6" wire $0\pred_insn_valid_i[0:0] - attribute \src "libresoc.v:198239.3-198249.6" + attribute \src "libresoc.v:200809.3-200831.6" wire $0\pred_mask_ready_i[0:0] - attribute \src "libresoc.v:199635.3-199701.6" - wire $0\sv_changed$next[0:0]$14030 - attribute \src "libresoc.v:197365.3-197366.37" + attribute \src "libresoc.v:200642.3-200728.6" + wire $0\sv_changed$next[0:0]$13608 + attribute \src "libresoc.v:198160.3-198161.37" wire $0\sv_changed[0:0] - attribute \src "libresoc.v:198745.3-198760.6" + attribute \src "libresoc.v:199592.3-199607.6" wire width 64 $0\svstate[63:0] - attribute \src "libresoc.v:198736.3-198744.6" - wire $0\svstate_ok_delay$next[0:0]$13914 - attribute \src "libresoc.v:197399.3-197400.49" + attribute \src "libresoc.v:199583.3-199591.6" + wire $0\svstate_ok_delay$next[0:0]$13492 + attribute \src "libresoc.v:198194.3-198195.49" wire $0\svstate_ok_delay[0:0] - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:200563.3-200641.6" wire $0\update_svstate[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $10\issue_fsm_state$next[2:0]$14012 - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $11\issue_fsm_state$next[2:0]$14013 - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $12\issue_fsm_state$next[2:0]$14014 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $1\core_asmcode$next[7:0]$14101 - attribute \src "libresoc.v:194914.13-194914.33" + attribute \src "libresoc.v:200275.3-200373.6" + wire width 3 $10\issue_fsm_state$next[2:0]$13590 + attribute \src "libresoc.v:200275.3-200373.6" + wire width 3 $11\issue_fsm_state$next[2:0]$13591 + attribute \src "libresoc.v:200275.3-200373.6" + wire width 3 $12\issue_fsm_state$next[2:0]$13592 + attribute \src "libresoc.v:200832.3-200949.6" + wire width 8 $1\core_asmcode$next[7:0]$13682 + attribute \src "libresoc.v:196001.13-196001.33" wire width 8 $1\core_asmcode[7:0] - attribute \src "libresoc.v:198140.3-198164.6" - wire $1\core_bigendian_i$10$next[0:0]$13838 - attribute \src "libresoc.v:198723.3-198735.6" + attribute \src "libresoc.v:198909.3-198940.6" + wire $1\core_bigendian_i$10$next[0:0]$13421 + attribute \src "libresoc.v:199570.3-199582.6" wire width 3 $1\core_cia__ren[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 64 $1\core_core_core_cia$next[63:0]$14102 - attribute \src "libresoc.v:194928.14-194928.55" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 64 $1\core_core_core_cia$next[63:0]$13683 + attribute \src "libresoc.v:196015.14-196015.55" wire width 64 $1\core_core_core_cia[63:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $1\core_core_core_cr_rd$next[7:0]$14103 - attribute \src "libresoc.v:194932.13-194932.41" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$13684 + attribute \src "libresoc.v:196019.13-196019.41" wire width 8 $1\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_cr_rd_ok$next[0:0]$14104 - attribute \src "libresoc.v:194936.7-194936.37" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$13685 + attribute \src "libresoc.v:196023.7-196023.37" wire $1\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $1\core_core_core_cr_wr$next[7:0]$14105 - attribute \src "libresoc.v:194940.13-194940.41" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$13686 + attribute \src "libresoc.v:196027.13-196027.41" wire width 8 $1\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$3$next[0:0]$14106 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$4$next[0:0]$14107 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$5$next[0:0]$14108 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$6$next[0:0]$14109 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$7$next[0:0]$14110 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$8$next[0:0]$14111 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$9$next[0:0]$14112 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$next[0:0]$14113 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 14 $1\core_core_core_fn_unit$next[13:0]$14114 - attribute \src "libresoc.v:194991.14-194991.47" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_core_exc_$signal$3$next[0:0]$13687 + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_core_exc_$signal$4$next[0:0]$13688 + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_core_exc_$signal$5$next[0:0]$13689 + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_core_exc_$signal$6$next[0:0]$13690 + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_core_exc_$signal$7$next[0:0]$13691 + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_core_exc_$signal$8$next[0:0]$13692 + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_core_exc_$signal$9$next[0:0]$13693 + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_core_exc_$signal$next[0:0]$13694 + attribute \src "libresoc.v:200832.3-200949.6" + wire width 14 $1\core_core_core_fn_unit$next[13:0]$13695 + attribute \src "libresoc.v:196078.14-196078.47" wire width 14 $1\core_core_core_fn_unit[13:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 2 $1\core_core_core_input_carry$next[1:0]$14115 - attribute \src "libresoc.v:194999.13-194999.46" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$13696 + attribute \src "libresoc.v:196086.13-196086.46" wire width 2 $1\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 32 $1\core_core_core_insn$next[31:0]$14116 - attribute \src "libresoc.v:195003.14-195003.41" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 32 $1\core_core_core_insn$next[31:0]$13697 + attribute \src "libresoc.v:196090.14-196090.41" wire width 32 $1\core_core_core_insn[31:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_core_insn_type$next[6:0]$14117 - attribute \src "libresoc.v:195082.13-195082.45" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$13698 + attribute \src "libresoc.v:196169.13-196169.45" wire width 7 $1\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_is_32bit$next[0:0]$14118 - attribute \src "libresoc.v:195086.7-195086.37" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_core_is_32bit$next[0:0]$13699 + attribute \src "libresoc.v:196173.7-196173.37" wire $1\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 64 $1\core_core_core_msr$next[63:0]$14119 - attribute \src "libresoc.v:195090.14-195090.55" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 64 $1\core_core_core_msr$next[63:0]$13700 + attribute \src "libresoc.v:196177.14-196177.55" wire width 64 $1\core_core_core_msr[63:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_oe$next[0:0]$14120 - attribute \src "libresoc.v:195094.7-195094.31" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_core_oe$next[0:0]$13701 + attribute \src "libresoc.v:196181.7-196181.31" wire $1\core_core_core_oe[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_oe_ok$next[0:0]$14121 - attribute \src "libresoc.v:195098.7-195098.34" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_core_oe_ok$next[0:0]$13702 + attribute \src "libresoc.v:196185.7-196185.34" wire $1\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_rc$next[0:0]$14122 - attribute \src "libresoc.v:195102.7-195102.31" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_core_rc$next[0:0]$13703 + attribute \src "libresoc.v:196189.7-196189.31" wire $1\core_core_core_rc[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_rc_ok$next[0:0]$14123 - attribute \src "libresoc.v:195106.7-195106.34" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_core_rc_ok$next[0:0]$13704 + attribute \src "libresoc.v:196193.7-196193.34" wire $1\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 13 $1\core_core_core_trapaddr$next[12:0]$14124 - attribute \src "libresoc.v:195110.14-195110.48" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$13705 + attribute \src "libresoc.v:196197.14-196197.48" wire width 13 $1\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $1\core_core_core_traptype$next[7:0]$14125 - attribute \src "libresoc.v:195114.13-195114.44" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 8 $1\core_core_core_traptype$next[7:0]$13706 + attribute \src "libresoc.v:196201.13-196201.44" wire width 8 $1\core_core_core_traptype[7:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_cr_in1$next[6:0]$14126 - attribute \src "libresoc.v:195118.13-195118.37" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $1\core_core_cr_in1$next[6:0]$13707 + attribute \src "libresoc.v:196205.13-196205.37" wire width 7 $1\core_core_cr_in1[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_cr_in1_ok$next[0:0]$14127 - attribute \src "libresoc.v:195122.7-195122.33" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_cr_in1_ok$next[0:0]$13708 + attribute \src "libresoc.v:196209.7-196209.33" wire $1\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_cr_in2$1$next[6:0]$14128 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_cr_in2$next[6:0]$14129 - attribute \src "libresoc.v:195126.13-195126.37" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $1\core_core_cr_in2$1$next[6:0]$13709 + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $1\core_core_cr_in2$next[6:0]$13710 + attribute \src "libresoc.v:196213.13-196213.37" wire width 7 $1\core_core_cr_in2[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_cr_in2_ok$2$next[0:0]$14130 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_cr_in2_ok$next[0:0]$14131 - attribute \src "libresoc.v:195134.7-195134.33" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$13711 + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_cr_in2_ok$next[0:0]$13712 + attribute \src "libresoc.v:196221.7-196221.33" wire $1\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_cr_out$next[6:0]$14132 - attribute \src "libresoc.v:195142.13-195142.37" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $1\core_core_cr_out$next[6:0]$13713 + attribute \src "libresoc.v:196229.13-196229.37" wire width 7 $1\core_core_cr_out[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_cr_wr_ok$next[0:0]$14133 - attribute \src "libresoc.v:195146.7-195146.32" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_cr_wr_ok$next[0:0]$13714 + attribute \src "libresoc.v:196233.7-196233.32" wire $1\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $1\core_core_dststep$next[6:0]$13801 - attribute \src "libresoc.v:195150.13-195150.38" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 7 $1\core_core_dststep$next[6:0]$13395 + attribute \src "libresoc.v:196237.13-196237.38" wire width 7 $1\core_core_dststep[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_ea$next[6:0]$14134 - attribute \src "libresoc.v:195154.13-195154.33" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $1\core_core_ea$next[6:0]$13715 + attribute \src "libresoc.v:196241.13-196241.33" wire width 7 $1\core_core_ea[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $1\core_core_fast1$next[2:0]$14135 - attribute \src "libresoc.v:195158.13-195158.35" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 3 $1\core_core_fast1$next[2:0]$13716 + attribute \src "libresoc.v:196245.13-196245.35" wire width 3 $1\core_core_fast1[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_fast1_ok$next[0:0]$14136 - attribute \src "libresoc.v:195162.7-195162.32" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_fast1_ok$next[0:0]$13717 + attribute \src "libresoc.v:196249.7-196249.32" wire $1\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $1\core_core_fast2$next[2:0]$14137 - attribute \src "libresoc.v:195166.13-195166.35" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 3 $1\core_core_fast2$next[2:0]$13718 + attribute \src "libresoc.v:196253.13-196253.35" wire width 3 $1\core_core_fast2[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_fast2_ok$next[0:0]$14138 - attribute \src "libresoc.v:195170.7-195170.32" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_fast2_ok$next[0:0]$13719 + attribute \src "libresoc.v:196257.7-196257.32" wire $1\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $1\core_core_fasto1$next[2:0]$14139 - attribute \src "libresoc.v:195174.13-195174.36" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 3 $1\core_core_fasto1$next[2:0]$13720 + attribute \src "libresoc.v:196261.13-196261.36" wire width 3 $1\core_core_fasto1[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $1\core_core_fasto2$next[2:0]$14140 - attribute \src "libresoc.v:195178.13-195178.36" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 3 $1\core_core_fasto2$next[2:0]$13721 + attribute \src "libresoc.v:196265.13-196265.36" wire width 3 $1\core_core_fasto2[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_lk$next[0:0]$14141 - attribute \src "libresoc.v:195182.7-195182.26" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_lk$next[0:0]$13722 + attribute \src "libresoc.v:196269.7-196269.26" wire $1\core_core_lk[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $1\core_core_maxvl$next[6:0]$13802 - attribute \src "libresoc.v:195186.13-195186.36" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 7 $1\core_core_maxvl$next[6:0]$13396 + attribute \src "libresoc.v:196273.13-196273.36" wire width 7 $1\core_core_maxvl[6:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $1\core_core_pc$next[63:0]$13803 - attribute \src "libresoc.v:195190.14-195190.49" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 64 $1\core_core_pc$next[63:0]$13397 + attribute \src "libresoc.v:196277.14-196277.49" wire width 64 $1\core_core_pc[63:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_reg1$next[6:0]$14142 - attribute \src "libresoc.v:195194.13-195194.35" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $1\core_core_reg1$next[6:0]$13723 + attribute \src "libresoc.v:196281.13-196281.35" wire width 7 $1\core_core_reg1[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_reg1_ok$next[0:0]$14143 - attribute \src "libresoc.v:195198.7-195198.31" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_reg1_ok$next[0:0]$13724 + attribute \src "libresoc.v:196285.7-196285.31" wire $1\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_reg2$next[6:0]$14144 - attribute \src "libresoc.v:195202.13-195202.35" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $1\core_core_reg2$next[6:0]$13725 + attribute \src "libresoc.v:196289.13-196289.35" wire width 7 $1\core_core_reg2[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_reg2_ok$next[0:0]$14145 - attribute \src "libresoc.v:195206.7-195206.31" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_reg2_ok$next[0:0]$13726 + attribute \src "libresoc.v:196293.7-196293.31" wire $1\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_reg3$next[6:0]$14146 - attribute \src "libresoc.v:195210.13-195210.35" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $1\core_core_reg3$next[6:0]$13727 + attribute \src "libresoc.v:196297.13-196297.35" wire width 7 $1\core_core_reg3[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_reg3_ok$next[0:0]$14147 - attribute \src "libresoc.v:195214.7-195214.31" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_reg3_ok$next[0:0]$13728 + attribute \src "libresoc.v:196301.7-196301.31" wire $1\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_rego$next[6:0]$14148 - attribute \src "libresoc.v:195218.13-195218.35" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 7 $1\core_core_rego$next[6:0]$13729 + attribute \src "libresoc.v:196305.13-196305.35" wire width 7 $1\core_core_rego[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 10 $1\core_core_spr1$next[9:0]$14149 - attribute \src "libresoc.v:195336.13-195336.37" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 10 $1\core_core_spr1$next[9:0]$13730 + attribute \src "libresoc.v:196321.13-196321.37" wire width 10 $1\core_core_spr1[9:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_spr1_ok$next[0:0]$14150 - attribute \src "libresoc.v:195340.7-195340.31" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_core_spr1_ok$next[0:0]$13731 + attribute \src "libresoc.v:196325.7-196325.31" wire $1\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 10 $1\core_core_spro$next[9:0]$14151 - attribute \src "libresoc.v:195458.13-195458.37" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 10 $1\core_core_spro$next[9:0]$13732 + attribute \src "libresoc.v:196341.13-196341.37" wire width 10 $1\core_core_spro[9:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $1\core_core_srcstep$next[6:0]$13804 - attribute \src "libresoc.v:195462.13-195462.38" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 7 $1\core_core_srcstep$next[6:0]$13398 + attribute \src "libresoc.v:196345.13-196345.38" wire width 7 $1\core_core_srcstep[6:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $1\core_core_subvl$next[1:0]$13805 - attribute \src "libresoc.v:195466.13-195466.35" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 2 $1\core_core_subvl$next[1:0]$13399 + attribute \src "libresoc.v:196349.13-196349.35" wire width 2 $1\core_core_subvl[1:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $1\core_core_svstep$next[1:0]$13806 - attribute \src "libresoc.v:195470.13-195470.36" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 2 $1\core_core_svstep$next[1:0]$13400 + attribute \src "libresoc.v:196353.13-196353.36" wire width 2 $1\core_core_svstep[1:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $1\core_core_vl$next[6:0]$13807 - attribute \src "libresoc.v:195476.13-195476.33" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 7 $1\core_core_vl$next[6:0]$13401 + attribute \src "libresoc.v:196359.13-196359.33" wire width 7 $1\core_core_vl[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $1\core_core_xer_in$next[2:0]$14152 - attribute \src "libresoc.v:195480.13-195480.36" + attribute \src "libresoc.v:200832.3-200949.6" + wire width 3 $1\core_core_xer_in$next[2:0]$13733 + attribute \src "libresoc.v:196363.13-196363.36" wire width 3 $1\core_core_xer_in[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_cr_out_ok$next[0:0]$14153 - attribute \src "libresoc.v:195488.7-195488.28" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_cr_out_ok$next[0:0]$13734 + attribute \src "libresoc.v:196371.7-196371.28" wire $1\core_cr_out_ok[0:0] - attribute \src "libresoc.v:198308.3-198317.6" - wire width 64 $1\core_data_i$12[63:0]$13857 - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:199099.3-199108.6" + wire width 64 $1\core_data_i$12[63:0]$13435 + attribute \src "libresoc.v:199714.3-199797.6" wire width 64 $1\core_data_i[63:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $1\core_dec$next[63:0]$13808 - attribute \src "libresoc.v:195504.14-195504.45" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 64 $1\core_dec$next[63:0]$13402 + attribute \src "libresoc.v:196387.14-196387.45" wire width 64 $1\core_dec[63:0] - attribute \src "libresoc.v:198421.3-198430.6" + attribute \src "libresoc.v:199216.3-199225.6" wire width 5 $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:198431.3-198440.6" + attribute \src "libresoc.v:199226.3-199235.6" wire $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_ea_ok$next[0:0]$14154 - attribute \src "libresoc.v:195514.7-195514.24" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_ea_ok$next[0:0]$13735 + attribute \src "libresoc.v:196397.7-196397.24" wire $1\core_ea_ok[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire $1\core_eint$next[0:0]$13809 - attribute \src "libresoc.v:195518.7-195518.23" + attribute \src "libresoc.v:198825.3-198876.6" + wire $1\core_eint$next[0:0]$13403 + attribute \src "libresoc.v:196401.7-196401.23" wire $1\core_eint[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_fasto1_ok$next[0:0]$14155 - attribute \src "libresoc.v:195522.7-195522.28" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_fasto1_ok$next[0:0]$13736 + attribute \src "libresoc.v:196405.7-196405.28" wire $1\core_fasto1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_fasto2_ok$next[0:0]$14156 - attribute \src "libresoc.v:195526.7-195526.28" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_fasto2_ok$next[0:0]$13737 + attribute \src "libresoc.v:196409.7-196409.28" wire $1\core_fasto2_ok[0:0] - attribute \src "libresoc.v:198470.3-198479.6" + attribute \src "libresoc.v:199265.3-199274.6" wire width 8 $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:198509.3-198518.6" + attribute \src "libresoc.v:199304.3-199313.6" wire width 3 $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:198617.3-198631.6" - wire width 3 $1\core_issue__addr$13[2:0]$13897 - attribute \src "libresoc.v:198548.3-198562.6" + attribute \src "libresoc.v:199424.3-199446.6" + wire width 3 $1\core_issue__addr$13[2:0]$13475 + attribute \src "libresoc.v:199343.3-199361.6" wire width 3 $1\core_issue__addr[2:0] - attribute \src "libresoc.v:198647.3-198661.6" + attribute \src "libresoc.v:199470.3-199492.6" wire width 64 $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:198563.3-198577.6" + attribute \src "libresoc.v:199362.3-199380.6" wire $1\core_issue__ren[0:0] - attribute \src "libresoc.v:198632.3-198646.6" + attribute \src "libresoc.v:199447.3-199469.6" wire $1\core_issue__wen[0:0] - attribute \src "libresoc.v:198354.3-198369.6" + attribute \src "libresoc.v:199145.3-199160.6" wire $1\core_issue_i[0:0] - attribute \src "libresoc.v:198329.3-198353.6" + attribute \src "libresoc.v:199120.3-199144.6" wire $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $1\core_msr$next[63:0]$13810 - attribute \src "libresoc.v:195554.14-195554.45" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 64 $1\core_msr$next[63:0]$13404 + attribute \src "libresoc.v:196437.14-196437.45" wire width 64 $1\core_msr[63:0] - attribute \src "libresoc.v:198919.3-198934.6" + attribute \src "libresoc.v:199798.3-199813.6" wire width 3 $1\core_msr__ren[2:0] - attribute \src "libresoc.v:198119.3-198139.6" - wire width 32 $1\core_raw_insn_i$next[31:0]$13833 - attribute \src "libresoc.v:195562.14-195562.37" + attribute \src "libresoc.v:198877.3-198908.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$13417 + attribute \src "libresoc.v:196445.14-196445.37" wire width 32 $1\core_raw_insn_i[31:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_rego_ok$next[0:0]$14157 - attribute \src "libresoc.v:195566.7-195566.26" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_rego_ok$next[0:0]$13738 + attribute \src "libresoc.v:196449.7-196449.26" wire $1\core_rego_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_spro_ok$next[0:0]$14158 - attribute \src "libresoc.v:195570.7-195570.26" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_spro_ok$next[0:0]$13739 + attribute \src "libresoc.v:196453.7-196453.26" wire $1\core_spro_ok[0:0] - attribute \src "libresoc.v:199449.3-199479.6" + attribute \src "libresoc.v:200374.3-200424.6" wire $1\core_stopped_i[0:0] - attribute \src "libresoc.v:198761.3-198773.6" + attribute \src "libresoc.v:199608.3-199620.6" wire width 3 $1\core_sv__ren[2:0] - attribute \src "libresoc.v:198165.3-198189.6" - wire $1\core_sv_a_nz$next[0:0]$13843 - attribute \src "libresoc.v:195582.7-195582.26" + attribute \src "libresoc.v:198941.3-198972.6" + wire $1\core_sv_a_nz$next[0:0]$13425 + attribute \src "libresoc.v:196465.7-196465.26" wire $1\core_sv_a_nz[0:0] - attribute \src "libresoc.v:198298.3-198307.6" - wire width 3 $1\core_wen$11[2:0]$13854 - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:199089.3-199098.6" + wire width 3 $1\core_wen$11[2:0]$13432 + attribute \src "libresoc.v:199630.3-199713.6" wire width 3 $1\core_wen[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_xer_out$next[0:0]$14159 - attribute \src "libresoc.v:195592.7-195592.26" + attribute \src "libresoc.v:200832.3-200949.6" + wire $1\core_xer_out$next[0:0]$13740 + attribute \src "libresoc.v:196475.7-196475.26" wire $1\core_xer_out[0:0] - attribute \src "libresoc.v:195598.7-195598.30" + attribute \src "libresoc.v:196481.7-196481.30" wire $1\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $1\cur_cur_dststep$next[6:0]$13943 - attribute \src "libresoc.v:195604.13-195604.36" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $1\cur_cur_dststep$next[6:0]$13521 + attribute \src "libresoc.v:196487.13-196487.36" wire width 7 $1\cur_cur_dststep[6:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $1\cur_cur_maxvl$next[6:0]$13944 - attribute \src "libresoc.v:195608.13-195608.34" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $1\cur_cur_maxvl$next[6:0]$13522 + attribute \src "libresoc.v:196491.13-196491.34" wire width 7 $1\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $1\cur_cur_srcstep$next[6:0]$13945 - attribute \src "libresoc.v:195612.13-195612.36" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $1\cur_cur_srcstep$next[6:0]$13523 + attribute \src "libresoc.v:196495.13-196495.36" wire width 7 $1\cur_cur_srcstep[6:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $1\cur_cur_subvl$next[1:0]$13946 - attribute \src "libresoc.v:195616.13-195616.33" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 2 $1\cur_cur_subvl$next[1:0]$13524 + attribute \src "libresoc.v:196499.13-196499.33" wire width 2 $1\cur_cur_subvl[1:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $1\cur_cur_svstep$next[1:0]$13947 - attribute \src "libresoc.v:195620.13-195620.34" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 2 $1\cur_cur_svstep$next[1:0]$13525 + attribute \src "libresoc.v:196503.13-196503.34" wire width 2 $1\cur_cur_svstep[1:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $1\cur_cur_vl$next[6:0]$13948 - attribute \src "libresoc.v:195624.13-195624.31" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $1\cur_cur_vl$next[6:0]$13526 + attribute \src "libresoc.v:196507.13-196507.31" wire width 7 $1\cur_cur_vl[6:0] - attribute \src "libresoc.v:198480.3-198488.6" - wire $1\d_cr_delay$next[0:0]$13879 - attribute \src "libresoc.v:195628.7-195628.24" + attribute \src "libresoc.v:199275.3-199283.6" + wire $1\d_cr_delay$next[0:0]$13457 + attribute \src "libresoc.v:196511.7-196511.24" wire $1\d_cr_delay[0:0] - attribute \src "libresoc.v:198441.3-198449.6" - wire $1\d_reg_delay$next[0:0]$13873 - attribute \src "libresoc.v:195632.7-195632.25" + attribute \src "libresoc.v:199236.3-199244.6" + wire $1\d_reg_delay$next[0:0]$13451 + attribute \src "libresoc.v:196515.7-196515.25" wire $1\d_reg_delay[0:0] - attribute \src "libresoc.v:198519.3-198527.6" - wire $1\d_xer_delay$next[0:0]$13885 - attribute \src "libresoc.v:195636.7-195636.25" + attribute \src "libresoc.v:199314.3-199322.6" + wire $1\d_xer_delay$next[0:0]$13463 + attribute \src "libresoc.v:196519.7-196519.25" wire $1\d_xer_delay[0:0] - attribute \src "libresoc.v:199480.3-199510.6" + attribute \src "libresoc.v:200425.3-200475.6" wire $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:198499.3-198508.6" + attribute \src "libresoc.v:199294.3-199303.6" wire $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:198489.3-198498.6" + attribute \src "libresoc.v:199284.3-199293.6" wire width 64 $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:198460.3-198469.6" + attribute \src "libresoc.v:199255.3-199264.6" wire $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:198450.3-198459.6" + attribute \src "libresoc.v:199245.3-199254.6" wire width 64 $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:198538.3-198547.6" + attribute \src "libresoc.v:199333.3-199342.6" wire $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:198528.3-198537.6" + attribute \src "libresoc.v:199323.3-199332.6" wire width 64 $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:198037.3-198045.6" - wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13780 - attribute \src "libresoc.v:195684.13-195684.34" + attribute \src "libresoc.v:198788.3-198796.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13374 + attribute \src "libresoc.v:196567.13-196567.34" wire width 4 $1\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:198774.3-198782.6" - wire width 64 $1\dbg_dmi_din$next[63:0]$13920 - attribute \src "libresoc.v:195688.14-195688.48" + attribute \src "libresoc.v:199621.3-199629.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$13498 + attribute \src "libresoc.v:196571.14-196571.48" wire width 64 $1\dbg_dmi_din[63:0] - attribute \src "libresoc.v:198046.3-198054.6" - wire $1\dbg_dmi_req_i$next[0:0]$13783 - attribute \src "libresoc.v:195694.7-195694.27" + attribute \src "libresoc.v:198797.3-198805.6" + wire $1\dbg_dmi_req_i$next[0:0]$13377 + attribute \src "libresoc.v:196577.7-196577.27" wire $1\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:198689.3-198697.6" - wire $1\dbg_dmi_we_i$next[0:0]$13907 - attribute \src "libresoc.v:195698.7-195698.26" + attribute \src "libresoc.v:199536.3-199544.6" + wire $1\dbg_dmi_we_i$next[0:0]$13485 + attribute \src "libresoc.v:196581.7-196581.26" wire $1\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:198662.3-198677.6" - wire width 64 $1\dec2_cur_dec$next[63:0]$13902 - attribute \src "libresoc.v:195752.14-195752.49" + attribute \src "libresoc.v:199493.3-199512.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$13480 + attribute \src "libresoc.v:196635.14-196635.49" wire width 64 $1\dec2_cur_dec[63:0] - attribute \src "libresoc.v:198055.3-198063.6" - wire $1\dec2_cur_eint$next[0:0]$13786 - attribute \src "libresoc.v:195756.7-195756.27" + attribute \src "libresoc.v:198806.3-198814.6" + wire $1\dec2_cur_eint$next[0:0]$13380 + attribute \src "libresoc.v:196639.7-196639.27" wire $1\dec2_cur_eint[0:0] - attribute \src "libresoc.v:199192.3-199212.6" - wire width 64 $1\dec2_cur_msr$next[63:0]$13986 - attribute \src "libresoc.v:195760.14-195760.49" + attribute \src "libresoc.v:200071.3-200095.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$13564 + attribute \src "libresoc.v:196643.14-196643.49" wire width 64 $1\dec2_cur_msr[63:0] - attribute \src "libresoc.v:199039.3-199059.6" - wire width 64 $1\dec2_cur_pc$next[63:0]$13933 - attribute \src "libresoc.v:195764.14-195764.48" + attribute \src "libresoc.v:199918.3-199938.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$13511 + attribute \src "libresoc.v:196647.14-196647.48" wire width 64 $1\dec2_cur_pc[63:0] - attribute \src "libresoc.v:199232.3-199262.6" - wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13995 - attribute \src "libresoc.v:195916.14-195916.40" + attribute \src "libresoc.v:200119.3-200153.6" + wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13573 + attribute \src "libresoc.v:196799.14-196799.40" wire width 32 $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:198064.3-198073.6" - wire width 2 $1\delay$next[1:0]$13789 - attribute \src "libresoc.v:196186.13-196186.25" + attribute \src "libresoc.v:198815.3-198824.6" + wire width 2 $1\delay$next[1:0]$13383 + attribute \src "libresoc.v:197069.13-197069.25" wire width 2 $1\delay[1:0] - attribute \src "libresoc.v:198370.3-198404.6" - wire $1\exec_fsm_state$next[0:0]$13863 - attribute \src "libresoc.v:196202.7-196202.28" + attribute \src "libresoc.v:199161.3-199195.6" + wire $1\exec_fsm_state$next[0:0]$13441 + attribute \src "libresoc.v:197085.7-197085.28" wire $1\exec_fsm_state[0:0] - attribute \src "libresoc.v:198318.3-198328.6" + attribute \src "libresoc.v:199109.3-199119.6" wire $1\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:198250.3-198260.6" + attribute \src "libresoc.v:198973.3-199003.6" wire $1\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:198261.3-198276.6" + attribute \src "libresoc.v:199004.3-199043.6" wire $1\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:198405.3-198420.6" + attribute \src "libresoc.v:199196.3-199215.6" wire $1\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:199138.3-199191.6" - wire width 2 $1\fetch_fsm_state$next[1:0]$13978 - attribute \src "libresoc.v:196214.13-196214.35" + attribute \src "libresoc.v:200017.3-200070.6" + wire width 2 $1\fetch_fsm_state$next[1:0]$13556 + attribute \src "libresoc.v:197097.13-197097.35" wire width 2 $1\fetch_fsm_state[1:0] - attribute \src "libresoc.v:199702.3-199712.6" + attribute \src "libresoc.v:200729.3-200743.6" wire $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:199263.3-199273.6" + attribute \src "libresoc.v:200154.3-200176.6" wire $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:198944.3-198954.6" + attribute \src "libresoc.v:199823.3-199833.6" wire $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:199334.3-199349.6" + attribute \src "libresoc.v:200259.3-200274.6" wire $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:198578.3-198605.6" - wire width 2 $1\fsm_state$next[1:0]$13892 - attribute \src "libresoc.v:196226.13-196226.29" + attribute \src "libresoc.v:199381.3-199408.6" + wire width 2 $1\fsm_state$next[1:0]$13470 + attribute \src "libresoc.v:197109.13-197109.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:198955.3-198970.6" + attribute \src "libresoc.v:199834.3-199849.6" wire width 48 $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:198971.3-199004.6" + attribute \src "libresoc.v:199850.3-199883.6" wire $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199005.3-199038.6" + attribute \src "libresoc.v:199884.3-199917.6" wire $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:198190.3-198227.6" + attribute \src "libresoc.v:200744.3-200789.6" wire $1\insn_done[0:0] - attribute \src "libresoc.v:198277.3-198297.6" + attribute \src "libresoc.v:199044.3-199088.6" wire $1\is_last[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $1\issue_fsm_state$next[2:0]$14003 - attribute \src "libresoc.v:196486.13-196486.35" + attribute \src "libresoc.v:200275.3-200373.6" + wire width 3 $1\issue_fsm_state$next[2:0]$13581 + attribute \src "libresoc.v:197369.13-197369.35" wire width 3 $1\issue_fsm_state[2:0] - attribute \src "libresoc.v:198935.3-198943.6" - wire $1\jtag_dmi0__ack_o$next[0:0]$13926 - attribute \src "libresoc.v:196490.7-196490.30" + attribute \src "libresoc.v:199814.3-199822.6" + wire $1\jtag_dmi0__ack_o$next[0:0]$13504 + attribute \src "libresoc.v:197373.7-197373.30" wire $1\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:199099.3-199107.6" - wire width 64 $1\jtag_dmi0__dout$next[63:0]$13969 - attribute \src "libresoc.v:196498.14-196498.52" + attribute \src "libresoc.v:199978.3-199986.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$13547 + attribute \src "libresoc.v:197381.14-197381.52" wire width 64 $1\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:199108.3-199137.6" - wire $1\msr_read$next[0:0]$13972 - attribute \src "libresoc.v:196556.7-196556.22" + attribute \src "libresoc.v:199987.3-200016.6" + wire $1\msr_read$next[0:0]$13550 + attribute \src "libresoc.v:197423.7-197423.22" wire $1\msr_read[0:0] - attribute \src "libresoc.v:198606.3-198616.6" + attribute \src "libresoc.v:199409.3-199423.6" wire width 64 $1\new_dec[63:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $1\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $1\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $1\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 2 $1\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 2 $1\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $1\new_svstate_vl[6:0] - attribute \src "libresoc.v:198678.3-198688.6" + attribute \src "libresoc.v:199513.3-199535.6" wire width 64 $1\new_tb[63:0] - attribute \src "libresoc.v:199213.3-199231.6" - wire width 64 $1\nia$next[63:0]$13991 - attribute \src "libresoc.v:196596.14-196596.40" + attribute \src "libresoc.v:200096.3-200118.6" + wire width 64 $1\nia$next[63:0]$13569 + attribute \src "libresoc.v:197463.14-197463.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:198707.3-198722.6" + attribute \src "libresoc.v:199554.3-199569.6" wire width 64 $1\pc[63:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $1\pc_changed$next[0:0]$14019 - attribute \src "libresoc.v:196602.7-196602.24" + attribute \src "libresoc.v:200476.3-200562.6" + wire $1\pc_changed$next[0:0]$13597 + attribute \src "libresoc.v:197469.7-197469.24" wire $1\pc_changed[0:0] - attribute \src "libresoc.v:198698.3-198706.6" - wire $1\pc_ok_delay$next[0:0]$13910 - attribute \src "libresoc.v:196612.7-196612.25" + attribute \src "libresoc.v:199545.3-199553.6" + wire $1\pc_ok_delay$next[0:0]$13488 + attribute \src "libresoc.v:197479.7-197479.25" wire $1\pc_ok_delay[0:0] - attribute \src "libresoc.v:198228.3-198238.6" + attribute \src "libresoc.v:200790.3-200808.6" wire $1\pred_insn_valid_i[0:0] - attribute \src "libresoc.v:198239.3-198249.6" + attribute \src "libresoc.v:200809.3-200831.6" wire $1\pred_mask_ready_i[0:0] - attribute \src "libresoc.v:199635.3-199701.6" - wire $1\sv_changed$next[0:0]$14031 - attribute \src "libresoc.v:197056.7-197056.24" + attribute \src "libresoc.v:200642.3-200728.6" + wire $1\sv_changed$next[0:0]$13609 + attribute \src "libresoc.v:197851.7-197851.24" wire $1\sv_changed[0:0] - attribute \src "libresoc.v:198745.3-198760.6" + attribute \src "libresoc.v:199592.3-199607.6" wire width 64 $1\svstate[63:0] - attribute \src "libresoc.v:198736.3-198744.6" - wire $1\svstate_ok_delay$next[0:0]$13915 - attribute \src "libresoc.v:197066.7-197066.30" + attribute \src "libresoc.v:199583.3-199591.6" + wire $1\svstate_ok_delay$next[0:0]$13493 + attribute \src "libresoc.v:197861.7-197861.30" wire $1\svstate_ok_delay[0:0] - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:200563.3-200641.6" wire $1\update_svstate[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $2\core_asmcode$next[7:0]$14160 - attribute \src "libresoc.v:198140.3-198164.6" - wire $2\core_bigendian_i$10$next[0:0]$13839 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 64 $2\core_core_core_cia$next[63:0]$14161 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $2\core_core_core_cr_rd$next[7:0]$14162 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_cr_rd_ok$next[0:0]$14163 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $2\core_core_core_cr_wr$next[7:0]$14164 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$3$next[0:0]$14165 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$4$next[0:0]$14166 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$5$next[0:0]$14167 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$6$next[0:0]$14168 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$7$next[0:0]$14169 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$8$next[0:0]$14170 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$9$next[0:0]$14171 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$next[0:0]$14172 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 14 $2\core_core_core_fn_unit$next[13:0]$14173 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 2 $2\core_core_core_input_carry$next[1:0]$14174 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 32 $2\core_core_core_insn$next[31:0]$14175 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_core_insn_type$next[6:0]$14176 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_is_32bit$next[0:0]$14177 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 64 $2\core_core_core_msr$next[63:0]$14178 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_oe$next[0:0]$14179 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_oe_ok$next[0:0]$14180 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_rc$next[0:0]$14181 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_rc_ok$next[0:0]$14182 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 13 $2\core_core_core_trapaddr$next[12:0]$14183 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $2\core_core_core_traptype$next[7:0]$14184 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_cr_in1$next[6:0]$14185 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_cr_in1_ok$next[0:0]$14186 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_cr_in2$1$next[6:0]$14187 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_cr_in2$next[6:0]$14188 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_cr_in2_ok$2$next[0:0]$14189 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_cr_in2_ok$next[0:0]$14190 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_cr_out$next[6:0]$14191 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_cr_wr_ok$next[0:0]$14192 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $2\core_core_dststep$next[6:0]$13811 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_ea$next[6:0]$14193 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $2\core_core_fast1$next[2:0]$14194 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_fast1_ok$next[0:0]$14195 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $2\core_core_fast2$next[2:0]$14196 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_fast2_ok$next[0:0]$14197 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $2\core_core_fasto1$next[2:0]$14198 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $2\core_core_fasto2$next[2:0]$14199 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_lk$next[0:0]$14200 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $2\core_core_maxvl$next[6:0]$13812 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $2\core_core_pc$next[63:0]$13813 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_reg1$next[6:0]$14201 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_reg1_ok$next[0:0]$14202 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_reg2$next[6:0]$14203 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_reg2_ok$next[0:0]$14204 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_reg3$next[6:0]$14205 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_reg3_ok$next[0:0]$14206 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_rego$next[6:0]$14207 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 10 $2\core_core_spr1$next[9:0]$14208 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_spr1_ok$next[0:0]$14209 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 10 $2\core_core_spro$next[9:0]$14210 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $2\core_core_srcstep$next[6:0]$13814 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $2\core_core_subvl$next[1:0]$13815 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $2\core_core_svstep$next[1:0]$13816 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $2\core_core_vl$next[6:0]$13817 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $2\core_core_xer_in$next[2:0]$14211 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_cr_out_ok$next[0:0]$14212 - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:198909.3-198940.6" + wire $2\core_bigendian_i$10$next[0:0]$13422 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$13741 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_core_exc_$signal$3$next[0:0]$13742 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_core_exc_$signal$4$next[0:0]$13743 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_core_exc_$signal$5$next[0:0]$13744 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_core_exc_$signal$6$next[0:0]$13745 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_core_exc_$signal$7$next[0:0]$13746 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_core_exc_$signal$8$next[0:0]$13747 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_core_exc_$signal$9$next[0:0]$13748 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_core_exc_$signal$next[0:0]$13749 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_core_oe_ok$next[0:0]$13750 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_core_rc_ok$next[0:0]$13751 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_cr_in1_ok$next[0:0]$13752 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$13753 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_cr_in2_ok$next[0:0]$13754 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_cr_wr_ok$next[0:0]$13755 + attribute \src "libresoc.v:198825.3-198876.6" + wire width 7 $2\core_core_dststep$next[6:0]$13405 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_fast1_ok$next[0:0]$13756 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_fast2_ok$next[0:0]$13757 + attribute \src "libresoc.v:198825.3-198876.6" + wire width 7 $2\core_core_maxvl$next[6:0]$13406 + attribute \src "libresoc.v:198825.3-198876.6" + wire width 64 $2\core_core_pc$next[63:0]$13407 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_reg1_ok$next[0:0]$13758 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_reg2_ok$next[0:0]$13759 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_reg3_ok$next[0:0]$13760 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_core_spr1_ok$next[0:0]$13761 + attribute \src "libresoc.v:198825.3-198876.6" + wire width 7 $2\core_core_srcstep$next[6:0]$13408 + attribute \src "libresoc.v:198825.3-198876.6" + wire width 2 $2\core_core_subvl$next[1:0]$13409 + attribute \src "libresoc.v:198825.3-198876.6" + wire width 2 $2\core_core_svstep$next[1:0]$13410 + attribute \src "libresoc.v:198825.3-198876.6" + wire width 7 $2\core_core_vl$next[6:0]$13411 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_cr_out_ok$next[0:0]$13762 + attribute \src "libresoc.v:199714.3-199797.6" wire width 64 $2\core_data_i[63:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $2\core_dec$next[63:0]$13818 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_ea_ok$next[0:0]$14213 - attribute \src "libresoc.v:198074.3-198118.6" - wire $2\core_eint$next[0:0]$13819 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_fasto1_ok$next[0:0]$14214 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_fasto2_ok$next[0:0]$14215 - attribute \src "libresoc.v:198354.3-198369.6" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 64 $2\core_dec$next[63:0]$13412 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_ea_ok$next[0:0]$13763 + attribute \src "libresoc.v:198825.3-198876.6" + wire $2\core_eint$next[0:0]$13413 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_fasto1_ok$next[0:0]$13764 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_fasto2_ok$next[0:0]$13765 + attribute \src "libresoc.v:199145.3-199160.6" wire $2\core_issue_i[0:0] - attribute \src "libresoc.v:198329.3-198353.6" + attribute \src "libresoc.v:199120.3-199144.6" wire $2\core_ivalid_i[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $2\core_msr$next[63:0]$13820 - attribute \src "libresoc.v:198919.3-198934.6" + attribute \src "libresoc.v:198825.3-198876.6" + wire width 64 $2\core_msr$next[63:0]$13414 + attribute \src "libresoc.v:199798.3-199813.6" wire width 3 $2\core_msr__ren[2:0] - attribute \src "libresoc.v:198119.3-198139.6" - wire width 32 $2\core_raw_insn_i$next[31:0]$13834 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_rego_ok$next[0:0]$14216 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_spro_ok$next[0:0]$14217 - attribute \src "libresoc.v:199449.3-199479.6" + attribute \src "libresoc.v:198877.3-198908.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$13418 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_rego_ok$next[0:0]$13766 + attribute \src "libresoc.v:200832.3-200949.6" + wire $2\core_spro_ok$next[0:0]$13767 + attribute \src "libresoc.v:200374.3-200424.6" wire $2\core_stopped_i[0:0] - attribute \src "libresoc.v:198165.3-198189.6" - wire $2\core_sv_a_nz$next[0:0]$13844 - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:198941.3-198972.6" + wire $2\core_sv_a_nz$next[0:0]$13426 + attribute \src "libresoc.v:199630.3-199713.6" wire width 3 $2\core_wen[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_xer_out$next[0:0]$14218 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $2\cur_cur_dststep$next[6:0]$13949 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $2\cur_cur_maxvl$next[6:0]$13950 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $2\cur_cur_srcstep$next[6:0]$13951 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $2\cur_cur_subvl$next[1:0]$13952 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $2\cur_cur_svstep$next[1:0]$13953 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $2\cur_cur_vl$next[6:0]$13954 - attribute \src "libresoc.v:199480.3-199510.6" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $2\cur_cur_dststep$next[6:0]$13527 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $2\cur_cur_maxvl$next[6:0]$13528 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $2\cur_cur_srcstep$next[6:0]$13529 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 2 $2\cur_cur_subvl$next[1:0]$13530 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 2 $2\cur_cur_svstep$next[1:0]$13531 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $2\cur_cur_vl$next[6:0]$13532 + attribute \src "libresoc.v:200425.3-200475.6" wire $2\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:198662.3-198677.6" - wire width 64 $2\dec2_cur_dec$next[63:0]$13903 - attribute \src "libresoc.v:199192.3-199212.6" - wire width 64 $2\dec2_cur_msr$next[63:0]$13987 - attribute \src "libresoc.v:199039.3-199059.6" - wire width 64 $2\dec2_cur_pc$next[63:0]$13934 - attribute \src "libresoc.v:199232.3-199262.6" - wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13996 - attribute \src "libresoc.v:198370.3-198404.6" - wire $2\exec_fsm_state$next[0:0]$13864 - attribute \src "libresoc.v:198261.3-198276.6" + attribute \src "libresoc.v:199493.3-199512.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$13481 + attribute \src "libresoc.v:200071.3-200095.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$13565 + attribute \src "libresoc.v:199918.3-199938.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$13512 + attribute \src "libresoc.v:200119.3-200153.6" + wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13574 + attribute \src "libresoc.v:199161.3-199195.6" + wire $2\exec_fsm_state$next[0:0]$13442 + attribute \src "libresoc.v:199004.3-199043.6" wire $2\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:198405.3-198420.6" + attribute \src "libresoc.v:199196.3-199215.6" wire $2\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:199138.3-199191.6" - wire width 2 $2\fetch_fsm_state$next[1:0]$13979 - attribute \src "libresoc.v:199334.3-199349.6" + attribute \src "libresoc.v:200017.3-200070.6" + wire width 2 $2\fetch_fsm_state$next[1:0]$13557 + attribute \src "libresoc.v:200259.3-200274.6" wire $2\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:198578.3-198605.6" - wire width 2 $2\fsm_state$next[1:0]$13893 - attribute \src "libresoc.v:198955.3-198970.6" + attribute \src "libresoc.v:199381.3-199408.6" + wire width 2 $2\fsm_state$next[1:0]$13471 + attribute \src "libresoc.v:199834.3-199849.6" wire width 48 $2\imem_a_pc_i[47:0] - attribute \src "libresoc.v:198971.3-199004.6" + attribute \src "libresoc.v:199850.3-199883.6" wire $2\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199005.3-199038.6" + attribute \src "libresoc.v:199884.3-199917.6" wire $2\imem_f_valid_i[0:0] - attribute \src "libresoc.v:198190.3-198227.6" + attribute \src "libresoc.v:200744.3-200789.6" wire $2\insn_done[0:0] - attribute \src "libresoc.v:198277.3-198297.6" + attribute \src "libresoc.v:199044.3-199088.6" wire $2\is_last[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $2\issue_fsm_state$next[2:0]$14004 - attribute \src "libresoc.v:199108.3-199137.6" - wire $2\msr_read$next[0:0]$13973 - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200275.3-200373.6" + wire width 3 $2\issue_fsm_state$next[2:0]$13582 + attribute \src "libresoc.v:199987.3-200016.6" + wire $2\msr_read$next[0:0]$13551 + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $2\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $2\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $2\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 2 $2\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 2 $2\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $2\new_svstate_vl[6:0] - attribute \src "libresoc.v:199213.3-199231.6" - wire width 64 $2\nia$next[63:0]$13992 - attribute \src "libresoc.v:198707.3-198722.6" + attribute \src "libresoc.v:200096.3-200118.6" + wire width 64 $2\nia$next[63:0]$13570 + attribute \src "libresoc.v:199554.3-199569.6" wire width 64 $2\pc[63:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $2\pc_changed$next[0:0]$14020 - attribute \src "libresoc.v:199635.3-199701.6" - wire $2\sv_changed$next[0:0]$14032 - attribute \src "libresoc.v:198745.3-198760.6" + attribute \src "libresoc.v:200476.3-200562.6" + wire $2\pc_changed$next[0:0]$13598 + attribute \src "libresoc.v:200642.3-200728.6" + wire $2\sv_changed$next[0:0]$13610 + attribute \src "libresoc.v:199592.3-199607.6" wire width 64 $2\svstate[63:0] - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:200563.3-200641.6" wire $2\update_svstate[0:0] - attribute \src "libresoc.v:198140.3-198164.6" - wire $3\core_bigendian_i$10$next[0:0]$13840 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_cr_rd_ok$next[0:0]$14219 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$3$next[0:0]$14220 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$4$next[0:0]$14221 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$5$next[0:0]$14222 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$6$next[0:0]$14223 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$7$next[0:0]$14224 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$8$next[0:0]$14225 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$9$next[0:0]$14226 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$next[0:0]$14227 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_oe_ok$next[0:0]$14228 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_rc_ok$next[0:0]$14229 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_cr_in1_ok$next[0:0]$14230 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_cr_in2_ok$2$next[0:0]$14231 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_cr_in2_ok$next[0:0]$14232 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_cr_wr_ok$next[0:0]$14233 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $3\core_core_dststep$next[6:0]$13821 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_fast1_ok$next[0:0]$14234 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_fast2_ok$next[0:0]$14235 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $3\core_core_maxvl$next[6:0]$13822 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $3\core_core_pc$next[63:0]$13823 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_reg1_ok$next[0:0]$14236 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_reg2_ok$next[0:0]$14237 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_reg3_ok$next[0:0]$14238 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_spr1_ok$next[0:0]$14239 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $3\core_core_srcstep$next[6:0]$13824 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $3\core_core_subvl$next[1:0]$13825 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $3\core_core_svstep$next[1:0]$13826 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $3\core_core_vl$next[6:0]$13827 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_cr_out_ok$next[0:0]$14240 - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:199714.3-199797.6" wire width 64 $3\core_data_i[63:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $3\core_dec$next[63:0]$13828 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_ea_ok$next[0:0]$14241 - attribute \src "libresoc.v:198074.3-198118.6" - wire $3\core_eint$next[0:0]$13829 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_fasto1_ok$next[0:0]$14242 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_fasto2_ok$next[0:0]$14243 - attribute \src "libresoc.v:198329.3-198353.6" + attribute \src "libresoc.v:199120.3-199144.6" wire $3\core_ivalid_i[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $3\core_msr$next[63:0]$13830 - attribute \src "libresoc.v:198119.3-198139.6" - wire width 32 $3\core_raw_insn_i$next[31:0]$13835 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_rego_ok$next[0:0]$14244 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_spro_ok$next[0:0]$14245 - attribute \src "libresoc.v:199449.3-199479.6" + attribute \src "libresoc.v:200374.3-200424.6" wire $3\core_stopped_i[0:0] - attribute \src "libresoc.v:198165.3-198189.6" - wire $3\core_sv_a_nz$next[0:0]$13845 - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:199630.3-199713.6" wire width 3 $3\core_wen[2:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $3\cur_cur_dststep$next[6:0]$13955 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $3\cur_cur_maxvl$next[6:0]$13956 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $3\cur_cur_srcstep$next[6:0]$13957 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $3\cur_cur_subvl$next[1:0]$13958 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $3\cur_cur_svstep$next[1:0]$13959 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $3\cur_cur_vl$next[6:0]$13960 - attribute \src "libresoc.v:199480.3-199510.6" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $3\cur_cur_dststep$next[6:0]$13533 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $3\cur_cur_maxvl$next[6:0]$13534 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $3\cur_cur_srcstep$next[6:0]$13535 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 2 $3\cur_cur_subvl$next[1:0]$13536 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 2 $3\cur_cur_svstep$next[1:0]$13537 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $3\cur_cur_vl$next[6:0]$13538 + attribute \src "libresoc.v:200425.3-200475.6" wire $3\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:199192.3-199212.6" - wire width 64 $3\dec2_cur_msr$next[63:0]$13988 - attribute \src "libresoc.v:199039.3-199059.6" - wire width 64 $3\dec2_cur_pc$next[63:0]$13935 - attribute \src "libresoc.v:199232.3-199262.6" - wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13997 - attribute \src "libresoc.v:198370.3-198404.6" - wire $3\exec_fsm_state$next[0:0]$13865 - attribute \src "libresoc.v:199138.3-199191.6" - wire width 2 $3\fetch_fsm_state$next[1:0]$13980 - attribute \src "libresoc.v:198971.3-199004.6" + attribute \src "libresoc.v:200071.3-200095.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$13566 + attribute \src "libresoc.v:199918.3-199938.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$13513 + attribute \src "libresoc.v:200119.3-200153.6" + wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13575 + attribute \src "libresoc.v:199161.3-199195.6" + wire $3\exec_fsm_state$next[0:0]$13443 + attribute \src "libresoc.v:200017.3-200070.6" + wire width 2 $3\fetch_fsm_state$next[1:0]$13558 + attribute \src "libresoc.v:199850.3-199883.6" wire $3\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199005.3-199038.6" + attribute \src "libresoc.v:199884.3-199917.6" wire $3\imem_f_valid_i[0:0] - attribute \src "libresoc.v:198190.3-198227.6" + attribute \src "libresoc.v:200744.3-200789.6" wire $3\insn_done[0:0] - attribute \src "libresoc.v:198277.3-198297.6" + attribute \src "libresoc.v:199044.3-199088.6" wire $3\is_last[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $3\issue_fsm_state$next[2:0]$14005 - attribute \src "libresoc.v:199108.3-199137.6" - wire $3\msr_read$next[0:0]$13974 - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200275.3-200373.6" + wire width 3 $3\issue_fsm_state$next[2:0]$13583 + attribute \src "libresoc.v:199987.3-200016.6" + wire $3\msr_read$next[0:0]$13552 + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $3\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $3\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $3\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 2 $3\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 2 $3\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $3\new_svstate_vl[6:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $3\pc_changed$next[0:0]$14021 - attribute \src "libresoc.v:199635.3-199701.6" - wire $3\sv_changed$next[0:0]$14033 - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:200476.3-200562.6" + wire $3\pc_changed$next[0:0]$13599 + attribute \src "libresoc.v:200642.3-200728.6" + wire $3\sv_changed$next[0:0]$13611 + attribute \src "libresoc.v:200563.3-200641.6" wire $3\update_svstate[0:0] - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:199714.3-199797.6" wire width 64 $4\core_data_i[63:0] - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:199630.3-199713.6" wire width 3 $4\core_wen[2:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $4\cur_cur_dststep$next[6:0]$13961 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $4\cur_cur_maxvl$next[6:0]$13962 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $4\cur_cur_srcstep$next[6:0]$13963 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $4\cur_cur_subvl$next[1:0]$13964 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $4\cur_cur_svstep$next[1:0]$13965 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $4\cur_cur_vl$next[6:0]$13966 - attribute \src "libresoc.v:198370.3-198404.6" - wire $4\exec_fsm_state$next[0:0]$13866 - attribute \src "libresoc.v:199138.3-199191.6" - wire width 2 $4\fetch_fsm_state$next[1:0]$13981 - attribute \src "libresoc.v:198971.3-199004.6" + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $4\cur_cur_dststep$next[6:0]$13539 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $4\cur_cur_maxvl$next[6:0]$13540 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $4\cur_cur_srcstep$next[6:0]$13541 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 2 $4\cur_cur_subvl$next[1:0]$13542 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 2 $4\cur_cur_svstep$next[1:0]$13543 + attribute \src "libresoc.v:199939.3-199977.6" + wire width 7 $4\cur_cur_vl$next[6:0]$13544 + attribute \src "libresoc.v:199161.3-199195.6" + wire $4\exec_fsm_state$next[0:0]$13444 + attribute \src "libresoc.v:200017.3-200070.6" + wire width 2 $4\fetch_fsm_state$next[1:0]$13559 + attribute \src "libresoc.v:199850.3-199883.6" wire $4\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199005.3-199038.6" + attribute \src "libresoc.v:199884.3-199917.6" wire $4\imem_f_valid_i[0:0] - attribute \src "libresoc.v:198190.3-198227.6" + attribute \src "libresoc.v:200744.3-200789.6" wire $4\insn_done[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $4\issue_fsm_state$next[2:0]$14006 - attribute \src "libresoc.v:199108.3-199137.6" - wire $4\msr_read$next[0:0]$13975 - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200275.3-200373.6" + wire width 3 $4\issue_fsm_state$next[2:0]$13584 + attribute \src "libresoc.v:199987.3-200016.6" + wire $4\msr_read$next[0:0]$13553 + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $4\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $4\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $4\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 2 $4\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 2 $4\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $4\new_svstate_vl[6:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $4\pc_changed$next[0:0]$14022 - attribute \src "libresoc.v:199635.3-199701.6" - wire $4\sv_changed$next[0:0]$14034 - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:200476.3-200562.6" + wire $4\pc_changed$next[0:0]$13600 + attribute \src "libresoc.v:200642.3-200728.6" + wire $4\sv_changed$next[0:0]$13612 + attribute \src "libresoc.v:200563.3-200641.6" wire $4\update_svstate[0:0] - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:199714.3-199797.6" wire width 64 $5\core_data_i[63:0] - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:199630.3-199713.6" wire width 3 $5\core_wen[2:0] - attribute \src "libresoc.v:198370.3-198404.6" - wire $5\exec_fsm_state$next[0:0]$13867 - attribute \src "libresoc.v:199138.3-199191.6" - wire width 2 $5\fetch_fsm_state$next[1:0]$13982 - attribute \src "libresoc.v:198190.3-198227.6" + attribute \src "libresoc.v:199161.3-199195.6" + wire $5\exec_fsm_state$next[0:0]$13445 + attribute \src "libresoc.v:200017.3-200070.6" + wire width 2 $5\fetch_fsm_state$next[1:0]$13560 + attribute \src "libresoc.v:200744.3-200789.6" wire $5\insn_done[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $5\issue_fsm_state$next[2:0]$14007 - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200275.3-200373.6" + wire width 3 $5\issue_fsm_state$next[2:0]$13585 + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $5\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $5\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $5\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 2 $5\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 2 $5\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $5\new_svstate_vl[6:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $5\pc_changed$next[0:0]$14023 - attribute \src "libresoc.v:199635.3-199701.6" - wire $5\sv_changed$next[0:0]$14035 - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:200476.3-200562.6" + wire $5\pc_changed$next[0:0]$13601 + attribute \src "libresoc.v:200642.3-200728.6" + wire $5\sv_changed$next[0:0]$13613 + attribute \src "libresoc.v:200563.3-200641.6" wire $5\update_svstate[0:0] - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:199714.3-199797.6" wire width 64 $6\core_data_i[63:0] - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:199630.3-199713.6" wire width 3 $6\core_wen[2:0] - attribute \src "libresoc.v:199138.3-199191.6" - wire width 2 $6\fetch_fsm_state$next[1:0]$13983 - attribute \src "libresoc.v:198190.3-198227.6" + attribute \src "libresoc.v:200017.3-200070.6" + wire width 2 $6\fetch_fsm_state$next[1:0]$13561 + attribute \src "libresoc.v:200744.3-200789.6" wire $6\insn_done[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $6\issue_fsm_state$next[2:0]$14008 - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200275.3-200373.6" + wire width 3 $6\issue_fsm_state$next[2:0]$13586 + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $6\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $6\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $6\pc_changed$next[0:0]$14024 - attribute \src "libresoc.v:199635.3-199701.6" - wire $6\sv_changed$next[0:0]$14036 - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:200476.3-200562.6" + wire $6\pc_changed$next[0:0]$13602 + attribute \src "libresoc.v:200642.3-200728.6" + wire $6\sv_changed$next[0:0]$13614 + attribute \src "libresoc.v:200563.3-200641.6" wire $6\update_svstate[0:0] - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:199714.3-199797.6" wire width 64 $7\core_data_i[63:0] - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:199630.3-199713.6" wire width 3 $7\core_wen[2:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $7\issue_fsm_state$next[2:0]$14009 - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200275.3-200373.6" + wire width 3 $7\issue_fsm_state$next[2:0]$13587 + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $7\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:200177.3-200258.6" wire width 7 $7\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $7\pc_changed$next[0:0]$14025 - attribute \src "libresoc.v:199635.3-199701.6" - wire $7\sv_changed$next[0:0]$14037 - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:200476.3-200562.6" + wire $7\pc_changed$next[0:0]$13603 + attribute \src "libresoc.v:200642.3-200728.6" + wire $7\sv_changed$next[0:0]$13615 + attribute \src "libresoc.v:200563.3-200641.6" wire $7\update_svstate[0:0] - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:199714.3-199797.6" wire width 64 $8\core_data_i[63:0] - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:199630.3-199713.6" wire width 3 $8\core_wen[2:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $8\issue_fsm_state$next[2:0]$14010 - attribute \src "libresoc.v:199511.3-199577.6" - wire $8\pc_changed$next[0:0]$14026 - attribute \src "libresoc.v:199635.3-199701.6" - wire $8\sv_changed$next[0:0]$14038 - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:200275.3-200373.6" + wire width 3 $8\issue_fsm_state$next[2:0]$13588 + attribute \src "libresoc.v:200476.3-200562.6" + wire $8\pc_changed$next[0:0]$13604 + attribute \src "libresoc.v:200642.3-200728.6" + wire $8\sv_changed$next[0:0]$13616 + attribute \src "libresoc.v:199714.3-199797.6" wire width 64 $9\core_data_i[63:0] - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:199630.3-199713.6" wire width 3 $9\core_wen[2:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $9\issue_fsm_state$next[2:0]$14011 - attribute \src "libresoc.v:199511.3-199577.6" - wire $9\pc_changed$next[0:0]$14027 - attribute \src "libresoc.v:199635.3-199701.6" - wire $9\sv_changed$next[0:0]$14039 - attribute \src "libresoc.v:197083.19-197083.108" - wire width 65 $add$libresoc.v:197083$13545_Y - attribute \src "libresoc.v:197095.19-197095.112" - wire width 8 $add$libresoc.v:197095$13556_Y - attribute \src "libresoc.v:197096.19-197096.112" - wire width 8 $add$libresoc.v:197096$13557_Y - attribute \src "libresoc.v:197166.19-197166.116" - wire width 65 $add$libresoc.v:197166$13627_Y - attribute \src "libresoc.v:197200.18-197200.107" - wire width 65 $add$libresoc.v:197200$13660_Y - attribute \src "libresoc.v:197088.19-197088.104" - wire $and$libresoc.v:197088$13550_Y - attribute \src "libresoc.v:197091.19-197091.104" - wire $and$libresoc.v:197091$13553_Y - attribute \src "libresoc.v:197099.19-197099.104" - wire $and$libresoc.v:197099$13560_Y - attribute \src "libresoc.v:197102.19-197102.104" - wire $and$libresoc.v:197102$13563_Y - attribute \src "libresoc.v:197104.19-197104.111" - wire $and$libresoc.v:197104$13565_Y - attribute \src "libresoc.v:197107.19-197107.104" - wire $and$libresoc.v:197107$13568_Y - attribute \src "libresoc.v:197113.19-197113.104" - wire $and$libresoc.v:197113$13573_Y - attribute \src "libresoc.v:197116.19-197116.104" - wire $and$libresoc.v:197116$13576_Y - attribute \src "libresoc.v:197119.19-197119.104" - wire $and$libresoc.v:197119$13579_Y - attribute \src "libresoc.v:197122.19-197122.104" - wire $and$libresoc.v:197122$13582_Y - attribute \src "libresoc.v:197125.19-197125.104" - wire $and$libresoc.v:197125$13585_Y - attribute \src "libresoc.v:197128.19-197128.104" - wire $and$libresoc.v:197128$13588_Y - attribute \src "libresoc.v:197129.19-197129.115" - wire width 3 $and$libresoc.v:197129$13589_Y - attribute \src "libresoc.v:197133.19-197133.104" - wire $and$libresoc.v:197133$13593_Y - attribute \src "libresoc.v:197136.19-197136.104" - wire $and$libresoc.v:197136$13596_Y - attribute \src "libresoc.v:197142.19-197142.104" - wire $and$libresoc.v:197142$13601_Y - attribute \src "libresoc.v:197145.19-197145.104" - wire $and$libresoc.v:197145$13604_Y - attribute \src "libresoc.v:197146.19-197146.115" - wire width 3 $and$libresoc.v:197146$13605_Y - attribute \src "libresoc.v:197149.19-197149.111" - wire $and$libresoc.v:197149$13608_Y - attribute \src "libresoc.v:197154.19-197154.104" - wire $and$libresoc.v:197154$13613_Y - attribute \src "libresoc.v:197157.19-197157.104" - wire $and$libresoc.v:197157$13616_Y - attribute \src "libresoc.v:197172.18-197172.109" - wire $and$libresoc.v:197172$13633_Y - attribute \src "libresoc.v:197178.18-197178.101" - wire $and$libresoc.v:197178$13640_Y - attribute \src "libresoc.v:197180.18-197180.109" - wire $and$libresoc.v:197180$13642_Y - attribute \src "libresoc.v:197183.18-197183.101" - wire $and$libresoc.v:197183$13645_Y - attribute \src "libresoc.v:197189.18-197189.101" - wire $and$libresoc.v:197189$13650_Y - attribute \src "libresoc.v:197191.18-197191.109" - wire $and$libresoc.v:197191$13652_Y - attribute \src "libresoc.v:197194.18-197194.101" - wire $and$libresoc.v:197194$13655_Y - attribute \src "libresoc.v:197103.19-197103.108" - wire $eq$libresoc.v:197103$13564_Y - attribute \src "libresoc.v:197148.19-197148.108" - wire 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$or$libresoc.v:197889$13149_Y + attribute \src "libresoc.v:197903.19-197903.113" + wire $or$libresoc.v:197903$13163_Y + attribute \src "libresoc.v:197905.19-197905.106" + wire $or$libresoc.v:197905$13164_Y + attribute \src "libresoc.v:197932.19-197932.113" + wire $or$libresoc.v:197932$13191_Y + attribute \src "libresoc.v:197934.19-197934.106" + wire $or$libresoc.v:197934$13192_Y + attribute \src "libresoc.v:197963.18-197963.110" + wire $or$libresoc.v:197963$13223_Y + attribute \src "libresoc.v:197964.18-197964.100" + wire $or$libresoc.v:197964$13224_Y + attribute \src "libresoc.v:197979.18-197979.112" + wire $or$libresoc.v:197979$13240_Y + attribute \src "libresoc.v:197981.18-197981.104" + wire $or$libresoc.v:197981$13241_Y + attribute \src "libresoc.v:197990.18-197990.112" + wire $or$libresoc.v:197990$13250_Y + attribute \src "libresoc.v:197992.18-197992.104" + wire $or$libresoc.v:197992$13251_Y + attribute \src "libresoc.v:197954.19-197954.211" + wire width 64 $pos$libresoc.v:197954$13212_Y + attribute \src "libresoc.v:197958.19-197958.114" + wire width 64 $pos$libresoc.v:197958$13217_Y + attribute \src "libresoc.v:197959.19-197959.113" + wire width 64 $pos$libresoc.v:197959$13219_Y + attribute \src "libresoc.v:197970.18-197970.109" + wire width 64 $pos$libresoc.v:197970$13231_Y + attribute \src "libresoc.v:197925.19-197925.93" + wire $reduce_or$libresoc.v:197925$13184_Y + attribute \src "libresoc.v:197942.19-197942.93" + wire $reduce_or$libresoc.v:197942$13200_Y + attribute \src "libresoc.v:197880.18-197880.41" + wire width 64 $shr$libresoc.v:197880$13141_Y + attribute \src "libresoc.v:197997.18-197997.40" + wire width 64 $shr$libresoc.v:197997$13256_Y + attribute \src "libresoc.v:197960.19-197960.116" + wire width 65 $sub$libresoc.v:197960$13220_Y + attribute \src "libresoc.v:197962.18-197962.101" + wire width 3 $sub$libresoc.v:197962$13222_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" wire width 65 \$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" wire width 65 \$101 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" wire width 7 \$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" wire \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" wire \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" wire \$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire width 8 \$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire width 8 \$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:516" wire width 8 \$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:516" wire width 8 \$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" wire \$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" wire \$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" wire \$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" wire \$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" wire \$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$192 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" wire width 3 \$195 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$200 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" wire \$210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" wire \$212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" wire \$214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$220 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$224 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$226 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$228 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" wire width 3 \$229 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" wire \$232 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" wire \$234 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" wire \$236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$238 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$240 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$242 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$244 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$246 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$248 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" wire width 3 \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:638" wire \$250 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \$252 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:725" wire \$254 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" wire \$256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" wire \$258 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" wire width 3 \$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \$260 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \$262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1003" wire width 65 \$264 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1003" wire width 65 \$265 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1019" wire width 65 \$267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1019" wire width 65 \$268 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:799" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:799" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:799" wire \$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$34 @@ -406933,59 +371894,59 @@ module \ti wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" wire \$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" wire \$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" wire \$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" wire \$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" wire \$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" wire \$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" wire \$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" wire \$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" wire \$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:338" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344" wire width 65 \$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:338" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344" wire width 65 \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:54" wire width 32 \$95 @@ -406994,46 +371955,46 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:54" wire width 32 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 338 \TAP_bus__tck + wire input 294 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 176 \TAP_bus__tdi + wire input 154 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 329 \TAP_bus__tdo + wire output 285 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 339 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + wire input 295 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:230" wire output 3 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 388 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" + wire input 344 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" wire width 8 \core_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" wire width 8 \core_asmcode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:229" wire input 4 \core_bigendian_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" wire \core_bigendian_i$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" wire \core_bigendian_i$10$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" wire width 64 \core_core_core_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" wire width 64 \core_core_core_cia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \core_core_core_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \core_core_core_cr_rd$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_cr_rd_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \core_core_core_cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \core_core_core_cr_wr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal @@ -407082,21 +372043,21 @@ module \ti attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire width 14 \core_core_core_fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire width 14 \core_core_core_fn_unit$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" wire width 2 \core_core_core_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" wire width 2 \core_core_core_input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 32 \core_core_core_insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 32 \core_core_core_insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -407173,109 +372134,109 @@ module \ti attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 7 \core_core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 7 \core_core_core_insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" wire \core_core_core_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" wire \core_core_core_is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \core_core_core_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \core_core_core_msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_oe_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_rc_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" wire width 13 \core_core_core_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" wire width 13 \core_core_core_trapaddr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" wire width 8 \core_core_core_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" wire width 8 \core_core_core_traptype$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_in1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_in1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_in2$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_in2$1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_in2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_in2_ok$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_in2_ok$2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_in2_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_wr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_wr_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \core_core_dststep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \core_core_dststep$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_ea$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fast1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fast2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_fast2_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fasto1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fasto2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" wire \core_core_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" wire \core_core_lk$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" wire width 7 \core_core_maxvl @@ -407285,273 +372246,69 @@ module \ti wire width 64 \core_core_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \core_core_pc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_reg1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_reg1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_reg2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_reg2_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_reg3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_reg3_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_rego$next attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \core_core_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \core_core_spr1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_spr1_ok$next attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \core_core_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \core_core_spro$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" wire width 7 \core_core_srcstep @@ -407565,23 +372322,23 @@ module \ti wire width 2 \core_core_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" wire width 2 \core_core_svstep$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire \core_core_terminate_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \core_core_vl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \core_core_vl$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" wire width 3 \core_core_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" wire width 3 \core_core_xer_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" wire \core_corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire \core_coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_cr_out_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire \core_cu_ad__go_i @@ -407605,21 +372362,21 @@ module \ti wire width 64 \core_dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \core_dmi__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_ea_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire \core_eint attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire \core_eint$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_fasto1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_fasto2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_fasto2_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 \core_full_rd2__data_o @@ -407641,9 +372398,9 @@ module \ti wire \core_issue__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \core_issue__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" wire \core_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105" wire \core_ivalid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \core_msr @@ -407653,29 +372410,29 @@ module \ti wire width 64 \core_msr__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_msr__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" wire width 32 \core_raw_insn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" wire width 32 \core_raw_insn_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_rego_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_rego_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_spro_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_state_nia_wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" wire \core_stopped_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_sv__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_sv__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" wire \core_sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" wire \core_sv_a_nz$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire \core_wb_dcache_en @@ -407683,11 +372440,11 @@ module \ti wire width 3 \core_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_wen$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" wire \core_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" wire \core_xer_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 2 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \cu_st__rel_o_dly @@ -407719,17 +372476,17 @@ module \ti wire width 7 \cur_cur_vl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \cur_cur_vl$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:956" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958" wire \d_cr_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:956" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958" wire \d_cr_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:946" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" wire \d_reg_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:946" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" wire \d_reg_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:966" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:968" wire \d_xer_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:966" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:968" wire \d_xer_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \dbg_core_dbg_core_dbg_dststep @@ -407813,35 +372570,35 @@ module \ti wire output 11 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 15 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" wire width 8 \dec2_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec2_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" wire width 64 \dec2_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_cr_in2$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_cr_in2_ok$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \dec2_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \dec2_cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_cr_wr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 \dec2_cur_dec @@ -407859,9 +372616,9 @@ module \ti wire width 64 \dec2_cur_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \dec2_cur_pc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal @@ -407879,21 +372636,21 @@ module \ti wire \dec2_exc_$signal$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec2_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec2_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec2_fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec2_fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_fasto2_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -407910,15 +372667,15 @@ module \ti attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire width 14 \dec2_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" wire width 2 \dec2_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 32 \dec2_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -407995,41 +372752,41 @@ module \ti attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 7 \dec2_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" wire \dec2_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" wire \dec2_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \dec2_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec2_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec2_raw_opcode_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_rego_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -408145,9 +372902,9 @@ module \ti attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \dec2_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_spr1_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -408263,66 +373020,66 @@ module \ti attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \dec2_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \dec2_sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" wire width 13 \dec2_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" wire width 8 \dec2_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" wire width 3 \dec2_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" wire \dec2_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" wire width 2 \delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" wire width 2 \delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \eint_0__core__i + wire output 155 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 24 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \eint_1__core__i + wire output 156 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 25 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \eint_2__core__i + wire output 157 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 26 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" wire \exec_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" wire \exec_fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:882" wire \exec_insn_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:879" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:881" wire \exec_insn_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:884" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:886" wire \exec_pc_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:883" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:885" wire \exec_pc_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" wire width 2 \fetch_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" wire width 2 \fetch_fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:870" wire \fetch_insn_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869" wire \fetch_insn_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:866" wire \fetch_pc_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:863" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865" wire \fetch_pc_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:991" wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:991" wire width 2 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e10__core__i + wire output 164 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 34 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408330,11 +373087,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 33 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e10__pad__o + wire output 165 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e10__pad__oe + wire output 166 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e11__core__i + wire output 167 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 37 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408342,11 +373099,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 36 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e11__pad__o + wire output 168 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_e11__pad__oe + wire output 169 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_e12__core__i + wire output 170 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 40 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408354,11 +373111,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 39 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_e12__pad__o + wire output 171 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_e12__pad__oe + wire output 172 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_e13__core__i + wire output 173 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 43 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408366,11 +373123,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 42 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_e13__pad__o + wire output 174 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_e13__pad__oe + wire output 175 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_e14__core__i + wire output 176 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 46 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408378,11 +373135,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 45 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_e14__pad__o + wire output 177 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_e14__pad__oe + wire output 178 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_e15__core__i + wire output 179 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 49 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408390,11 +373147,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 48 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_e15__pad__o + wire output 180 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_e15__pad__oe + wire output 181 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_e8__core__i + wire output 158 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 28 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408402,11 +373159,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 27 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_e8__pad__o + wire output 159 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e8__pad__oe + wire output 160 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e9__core__i + wire output 161 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 31 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408414,11 +373171,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 30 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e9__pad__o + wire output 162 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e9__pad__oe + wire output 163 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_s0__core__i + wire output 182 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 52 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408426,11 +373183,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 51 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_s0__pad__o + wire output 183 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s0__pad__oe + wire output 184 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s1__core__i + wire output 185 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 55 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408438,11 +373195,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 54 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s1__pad__o + wire output 186 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s1__pad__oe + wire output 187 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s2__core__i + wire output 188 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 58 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408450,11 +373207,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 57 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s2__pad__o + wire output 189 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s2__pad__oe + wire output 190 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s3__core__i + wire output 191 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 61 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408462,11 +373219,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 60 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s3__pad__o + wire output 192 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \gpio_s3__pad__oe + wire output 193 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \gpio_s4__core__i + wire output 194 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 64 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408474,11 +373231,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 63 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \gpio_s4__pad__o + wire output 195 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \gpio_s4__pad__oe + wire output 196 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \gpio_s5__core__i + wire output 197 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 67 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408486,11 +373243,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 66 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \gpio_s5__pad__o + wire output 198 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \gpio_s5__pad__oe + wire output 199 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \gpio_s6__core__i + wire output 200 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 70 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408498,11 +373255,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 69 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \gpio_s6__pad__o + wire output 201 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \gpio_s6__pad__oe + wire output 202 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \gpio_s7__core__i + wire output 203 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 73 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -408510,9 +373267,9 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 72 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \gpio_s7__pad__o + wire output 204 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \gpio_s7__pad__oe + wire output 205 \gpio_s7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 18 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" @@ -408528,35 +373285,35 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire output 20 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 372 \icp_wb__ack + wire output 328 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 378 \icp_wb__adr + wire width 28 input 334 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 373 \icp_wb__cyc + wire input 329 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 374 \icp_wb__dat_r + wire width 32 output 330 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 375 \icp_wb__dat_w + wire width 32 input 331 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 379 \icp_wb__sel + wire width 4 input 335 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 376 \icp_wb__stb + wire input 332 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 377 \icp_wb__we + wire input 333 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 385 \ics_wb__ack + wire output 341 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 380 \ics_wb__adr + wire width 28 input 336 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 382 \ics_wb__cyc + wire input 338 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 384 \ics_wb__dat_r + wire width 32 output 340 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 386 \ics_wb__dat_w + wire width 32 input 342 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 383 \ics_wb__stb + wire input 339 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 387 \ics_wb__we + wire input 343 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" wire width 48 \imem_a_pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" @@ -408569,19 +373326,19 @@ module \ti wire \imem_f_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire \imem_wb_icache_en - attribute \src "libresoc.v:194646.7-194646.15" + attribute \src "libresoc.v:195733.7-195733.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:259" wire \insn_done attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 381 \int_level_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" + wire width 16 input 337 \int_level_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \is_last - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" wire \is_svp64_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire width 3 \issue_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire width 3 \issue_fsm_state$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__ack_o @@ -408600,76 +373357,60 @@ module \ti attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__we_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 336 \jtag_wb__ack + wire input 292 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 330 \jtag_wb__adr + wire width 29 output 286 \jtag_wb__adr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 332 \jtag_wb__cyc + wire output 288 \jtag_wb__cyc attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 337 \jtag_wb__dat_r + wire width 64 input 293 \jtag_wb__dat_r attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 335 \jtag_wb__dat_w + wire width 64 output 291 \jtag_wb__dat_w attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 331 \jtag_wb__sel + wire output 287 \jtag_wb__sel attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 333 \jtag_wb__stb + wire output 289 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 334 \jtag_wb__we + wire output 290 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" wire \jtag_wb_sram_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 75 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \mspi0_clk__pad__o + wire output 206 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 76 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \mspi0_cs_n__pad__o + wire output 207 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \mspi0_miso__core__i + wire output 209 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 78 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 77 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \mspi0_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 79 \mspi1_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \mspi1_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \mspi1_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \mspi1_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \mspi1_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \mspi1_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \mspi1_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + wire output 208 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" wire \msr_read - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" wire \msr_read$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \mtwi_scl__core__o + wire input 82 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \mtwi_scl__pad__o + wire output 213 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \mtwi_sda__core__i + wire output 210 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 84 \mtwi_sda__core__o + wire input 80 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 85 \mtwi_sda__core__oe + wire input 81 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 83 \mtwi_sda__pad__i + wire input 79 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \mtwi_sda__pad__o + wire output 211 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:999" + wire output 212 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" wire width 64 \new_dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \new_svstate_dststep @@ -408683,489 +373424,417 @@ module \ti wire width 2 \new_svstate_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \new_svstate_vl - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" wire width 64 \new_tb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:506" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire width 7 \next_dststep - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:505" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513" wire width 7 \next_srcstep - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:846" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:848" wire width 64 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:846" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:848" wire width 64 \nia$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61" wire width 64 \pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" wire \pc_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" wire \pc_changed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 7 \pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 6 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:226" wire width 64 output 5 \pc_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" wire \pc_ok_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" wire \pc_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire \por_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:874" wire \pred_insn_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" wire \pred_insn_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" wire \pred_mask_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" wire \pred_mask_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \pwm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \pwm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \pwm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \sd0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sd0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sd0_cmd__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 90 \sd0_cmd__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 91 \sd0_cmd__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 89 \sd0_cmd__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sd0_cmd__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_cmd__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sd0_data0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \sd0_data0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 95 \sd0_data0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \sd0_data0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sd0_data0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sd0_data0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sd0_data1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 97 \sd0_data1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \sd0_data1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 96 \sd0_data1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sd0_data1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sd0_data1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sd0_data2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \sd0_data2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 101 \sd0_data2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \sd0_data2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sd0_data2__pad__o + wire input 108 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sd0_data2__pad__oe + wire output 239 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sd0_data3__core__i + wire input 126 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 103 \sd0_data3__core__o + wire output 257 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \sd0_data3__core__oe + wire input 127 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 102 \sd0_data3__pad__i + wire output 258 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sd0_data3__pad__o + wire input 128 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sd0_data3__pad__oe + wire output 259 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \sdr_a_0__core__o + wire input 109 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_a_0__pad__o + wire output 240 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_a_10__core__o + wire input 110 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_a_10__pad__o + wire output 241 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_a_11__core__o + wire input 111 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_a_11__pad__o + wire output 242 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_a_12__core__o + wire input 112 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_a_12__pad__o + wire output 243 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \sdr_a_1__core__o + wire input 113 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_a_1__pad__o + wire output 244 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \sdr_a_2__core__o + wire input 114 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_a_2__pad__o + wire output 245 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \sdr_a_3__core__o + wire input 115 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_a_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 134 \sdr_a_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_a_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \sdr_a_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_a_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \sdr_a_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_a_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_a_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_a_7__pad__o + wire output 246 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_a_8__core__o + wire input 116 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_a_8__pad__o + wire output 247 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_a_9__core__o + wire input 117 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_a_9__pad__o + wire output 248 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_ba_0__core__o + wire input 118 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_ba_0__pad__o + wire output 249 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_ba_1__core__o + wire input 119 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_ba_1__pad__o + wire output 250 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_cas_n__core__o + wire input 123 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_cas_n__pad__o + wire output 254 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_cke__core__o + wire input 121 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_cke__pad__o + wire output 252 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_clock__core__o + wire input 120 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_clock__pad__o + wire output 251 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_cs_n__core__o + wire input 125 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_cs_n__pad__o + wire output 256 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \sdr_dm_0__core__o + wire input 83 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_dm_0__pad__o + wire output 214 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dm_1__core__o + wire input 129 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dm_1__pad__o + wire output 260 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_0__core__i + wire output 215 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 107 \sdr_dq_0__core__o + wire input 85 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 108 \sdr_dq_0__core__oe + wire input 86 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \sdr_dq_0__pad__i + wire input 84 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_0__pad__o + wire output 216 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_0__pad__oe + wire output 217 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_10__core__i + wire output 267 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_10__core__o + wire input 137 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_10__core__oe + wire input 138 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_10__pad__i + wire input 136 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_10__pad__o + wire output 268 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_10__pad__oe + wire output 269 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_11__core__i + wire output 270 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_11__core__o + wire input 140 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 163 \sdr_dq_11__core__oe + wire input 141 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_11__pad__i + wire input 139 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_11__pad__o + wire output 271 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_11__pad__oe + wire output 272 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_12__core__i + wire output 273 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 165 \sdr_dq_12__core__o + wire input 143 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 166 \sdr_dq_12__core__oe + wire input 144 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 164 \sdr_dq_12__pad__i + wire input 142 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 318 \sdr_dq_12__pad__o + wire output 274 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 319 \sdr_dq_12__pad__oe + wire output 275 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 320 \sdr_dq_13__core__i + wire output 276 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 168 \sdr_dq_13__core__o + wire input 146 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 169 \sdr_dq_13__core__oe + wire input 147 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 167 \sdr_dq_13__pad__i + wire input 145 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 321 \sdr_dq_13__pad__o + wire output 277 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 322 \sdr_dq_13__pad__oe + wire output 278 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 323 \sdr_dq_14__core__i + wire output 279 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 171 \sdr_dq_14__core__o + wire input 149 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 172 \sdr_dq_14__core__oe + wire input 150 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 170 \sdr_dq_14__pad__i + wire input 148 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 324 \sdr_dq_14__pad__o + wire output 280 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 325 \sdr_dq_14__pad__oe + wire output 281 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 326 \sdr_dq_15__core__i + wire output 282 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 174 \sdr_dq_15__core__o + wire input 152 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 175 \sdr_dq_15__core__oe + wire input 153 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 173 \sdr_dq_15__pad__i + wire input 151 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 327 \sdr_dq_15__pad__o + wire output 283 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 328 \sdr_dq_15__pad__oe + wire output 284 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_1__core__i + wire output 218 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \sdr_dq_1__core__o + wire input 88 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \sdr_dq_1__core__oe + wire input 89 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 109 \sdr_dq_1__pad__i + wire input 87 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_1__pad__o + wire output 219 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_1__pad__oe + wire output 220 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_2__core__i + wire output 221 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 113 \sdr_dq_2__core__o + wire input 91 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 114 \sdr_dq_2__core__oe + wire input 92 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \sdr_dq_2__pad__i + wire input 90 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_2__pad__o + wire output 222 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_2__pad__oe + wire output 223 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_3__core__i + wire output 224 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \sdr_dq_3__core__o + wire input 94 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \sdr_dq_3__core__oe + wire input 95 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 115 \sdr_dq_3__pad__i + wire input 93 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_3__pad__o + wire output 225 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_dq_3__pad__oe + wire output 226 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_dq_4__core__i + wire output 227 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 119 \sdr_dq_4__core__o + wire input 97 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 120 \sdr_dq_4__core__oe + wire input 98 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \sdr_dq_4__pad__i + wire input 96 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_dq_4__pad__o + wire output 228 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_dq_4__pad__oe + wire output 229 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_dq_5__core__i + wire output 230 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 122 \sdr_dq_5__core__o + wire input 100 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \sdr_dq_5__core__oe + wire input 101 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \sdr_dq_5__pad__i + wire input 99 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_dq_5__pad__o + wire output 231 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_dq_5__pad__oe + wire output 232 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_dq_6__core__i + wire output 233 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \sdr_dq_6__core__o + wire input 103 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 126 \sdr_dq_6__core__oe + wire input 104 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 124 \sdr_dq_6__pad__i + wire input 102 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_dq_6__pad__o + wire output 234 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_dq_6__pad__oe + wire output 235 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_dq_7__core__i + wire output 236 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \sdr_dq_7__core__o + wire input 106 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \sdr_dq_7__core__oe + wire input 107 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 127 \sdr_dq_7__pad__i + wire input 105 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_dq_7__pad__o + wire output 237 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_dq_7__pad__oe + wire output 238 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_8__core__i + wire output 261 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_8__core__o + wire input 131 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_8__core__oe + wire input 132 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_8__pad__i + wire input 130 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dq_8__pad__o + wire output 262 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_8__pad__oe + wire output 263 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_9__core__i + wire output 264 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_9__core__o + wire input 134 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_9__core__oe + wire input 135 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_9__pad__i + wire input 133 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_9__pad__o + wire output 265 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_9__pad__oe + wire output 266 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_ras_n__core__o + wire input 122 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_ras_n__pad__o + wire output 253 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_we_n__core__o + wire input 124 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_we_n__pad__o + wire output 255 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire \sram4k_0_enable attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 342 \sram4k_0_wb__ack + wire output 298 \sram4k_0_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 343 \sram4k_0_wb__adr + wire width 9 input 299 \sram4k_0_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 340 \sram4k_0_wb__cyc + wire input 296 \sram4k_0_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 344 \sram4k_0_wb__dat_r + wire width 64 output 300 \sram4k_0_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 345 \sram4k_0_wb__dat_w + wire width 64 input 301 \sram4k_0_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 347 \sram4k_0_wb__sel + wire width 8 input 303 \sram4k_0_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 341 \sram4k_0_wb__stb + wire input 297 \sram4k_0_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 346 \sram4k_0_wb__we + wire input 302 \sram4k_0_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire \sram4k_1_enable attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 350 \sram4k_1_wb__ack + wire output 306 \sram4k_1_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 351 \sram4k_1_wb__adr + wire width 9 input 307 \sram4k_1_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 348 \sram4k_1_wb__cyc + wire input 304 \sram4k_1_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 352 \sram4k_1_wb__dat_r + wire width 64 output 308 \sram4k_1_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 353 \sram4k_1_wb__dat_w + wire width 64 input 309 \sram4k_1_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 355 \sram4k_1_wb__sel + wire width 8 input 311 \sram4k_1_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 349 \sram4k_1_wb__stb + wire input 305 \sram4k_1_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 354 \sram4k_1_wb__we + wire input 310 \sram4k_1_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire \sram4k_2_enable attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 358 \sram4k_2_wb__ack + wire output 314 \sram4k_2_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 359 \sram4k_2_wb__adr + wire width 9 input 315 \sram4k_2_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 356 \sram4k_2_wb__cyc + wire input 312 \sram4k_2_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 360 \sram4k_2_wb__dat_r + wire width 64 output 316 \sram4k_2_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 361 \sram4k_2_wb__dat_w + wire width 64 input 317 \sram4k_2_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 363 \sram4k_2_wb__sel + wire width 8 input 319 \sram4k_2_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 357 \sram4k_2_wb__stb + wire input 313 \sram4k_2_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 362 \sram4k_2_wb__we + wire input 318 \sram4k_2_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire \sram4k_3_enable attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 366 \sram4k_3_wb__ack + wire output 322 \sram4k_3_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 367 \sram4k_3_wb__adr + wire width 9 input 323 \sram4k_3_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 364 \sram4k_3_wb__cyc + wire input 320 \sram4k_3_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 368 \sram4k_3_wb__dat_r + wire width 64 output 324 \sram4k_3_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 369 \sram4k_3_wb__dat_w + wire width 64 input 325 \sram4k_3_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 371 \sram4k_3_wb__sel + wire width 8 input 327 \sram4k_3_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 365 \sram4k_3_wb__stb + wire input 321 \sram4k_3_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 370 \sram4k_3_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" + wire input 326 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:830" wire \sv_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:830" wire \sv_changed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61" wire width 64 \svstate - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 \svstate_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \svstate_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" wire \svstate_ok_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" wire \svstate_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" wire \ti_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:498" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:506" wire \update_svstate attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire \xics_icp_core_irq_o @@ -409177,8 +373846,8 @@ module \ti wire width 8 \xics_ics_icp_o_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \xics_ics_icp_o_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" - cell $add $add$libresoc.v:197083$13545 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" + cell $add $add$libresoc.v:197878$13139 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -409186,10 +373855,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:197083$13545_Y + connect \Y $add$libresoc.v:197878$13139_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507" - cell $add $add$libresoc.v:197095$13556 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + cell $add $add$libresoc.v:197890$13150 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409197,10 +373866,10 @@ module \ti parameter \Y_WIDTH 8 connect \A \cur_cur_srcstep connect \B 1'1 - connect \Y $add$libresoc.v:197095$13556_Y + connect \Y $add$libresoc.v:197890$13150_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508" - cell $add $add$libresoc.v:197096$13557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:516" + cell $add $add$libresoc.v:197891$13151 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409208,10 +373877,10 @@ module \ti parameter \Y_WIDTH 8 connect \A \cur_cur_dststep connect \B 1'1 - connect \Y $add$libresoc.v:197096$13557_Y + connect \Y $add$libresoc.v:197891$13151_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" - cell $add $add$libresoc.v:197166$13627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1019" + cell $add $add$libresoc.v:197961$13221 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -409219,10 +373888,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $add$libresoc.v:197166$13627_Y + connect \Y $add$libresoc.v:197961$13221_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:338" - cell $add $add$libresoc.v:197200$13660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344" + cell $add $add$libresoc.v:197995$13254 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -409230,10 +373899,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:197200$13660_Y + connect \Y $add$libresoc.v:197995$13254_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197088$13550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $and $and$libresoc.v:197883$13144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409241,10 +373910,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$106 connect \B \$108 - connect \Y $and$libresoc.v:197088$13550_Y + connect \Y $and$libresoc.v:197883$13144_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197091$13553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $and $and$libresoc.v:197886$13147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409252,10 +373921,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$112 connect \B \$114 - connect \Y $and$libresoc.v:197091$13553_Y + connect \Y $and$libresoc.v:197886$13147_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197099$13560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $and $and$libresoc.v:197894$13154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409263,10 +373932,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$130 connect \B \$132 - connect \Y $and$libresoc.v:197099$13560_Y + connect \Y $and$libresoc.v:197894$13154_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197102$13563 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $and $and$libresoc.v:197897$13157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409274,10 +373943,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$136 connect \B \$138 - connect \Y $and$libresoc.v:197102$13563_Y + connect \Y $and$libresoc.v:197897$13157_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $and $and$libresoc.v:197104$13565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" + cell $and $and$libresoc.v:197899$13159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409285,10 +373954,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$142 - connect \Y $and$libresoc.v:197104$13565_Y + connect \Y $and$libresoc.v:197899$13159_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197107$13568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $and $and$libresoc.v:197902$13162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409296,10 +373965,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$146 connect \B \$148 - connect \Y $and$libresoc.v:197107$13568_Y + connect \Y $and$libresoc.v:197902$13162_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197113$13573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $and $and$libresoc.v:197908$13167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409307,10 +373976,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$158 connect \B \$160 - connect \Y $and$libresoc.v:197113$13573_Y + connect \Y $and$libresoc.v:197908$13167_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197116$13576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $and $and$libresoc.v:197911$13170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409318,10 +373987,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$164 connect \B \$166 - connect \Y $and$libresoc.v:197116$13576_Y + connect \Y $and$libresoc.v:197911$13170_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197119$13579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $and $and$libresoc.v:197914$13173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409329,10 +373998,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$170 connect \B \$172 - connect \Y $and$libresoc.v:197119$13579_Y + connect \Y $and$libresoc.v:197914$13173_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197122$13582 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $and $and$libresoc.v:197917$13176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409340,10 +374009,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$176 connect \B \$178 - connect \Y $and$libresoc.v:197122$13582_Y + connect \Y $and$libresoc.v:197917$13176_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197125$13585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $and $and$libresoc.v:197920$13179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409351,10 +374020,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$182 connect \B \$184 - connect \Y $and$libresoc.v:197125$13585_Y + connect \Y $and$libresoc.v:197920$13179_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197128$13588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $and $and$libresoc.v:197923$13182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409362,10 +374031,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$188 connect \B \$190 - connect \Y $and$libresoc.v:197128$13588_Y + connect \Y $and$libresoc.v:197923$13182_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" - cell $and $and$libresoc.v:197129$13589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + cell $and $and$libresoc.v:197924$13183 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -409373,10 +374042,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 1'1 - connect \Y $and$libresoc.v:197129$13589_Y + connect \Y $and$libresoc.v:197924$13183_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197133$13593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $and $and$libresoc.v:197928$13187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409384,10 +374053,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$198 connect \B \$200 - connect \Y $and$libresoc.v:197133$13593_Y + connect \Y $and$libresoc.v:197928$13187_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197136$13596 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $and $and$libresoc.v:197931$13190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409395,10 +374064,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$204 connect \B \$206 - connect \Y $and$libresoc.v:197136$13596_Y + connect \Y $and$libresoc.v:197931$13190_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197142$13601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $and $and$libresoc.v:197937$13195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409406,10 +374075,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$216 connect \B \$218 - connect \Y $and$libresoc.v:197142$13601_Y + connect \Y $and$libresoc.v:197937$13195_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197145$13604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $and $and$libresoc.v:197940$13198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409417,10 +374086,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$222 connect \B \$224 - connect \Y $and$libresoc.v:197145$13604_Y + connect \Y $and$libresoc.v:197940$13198_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" - cell $and $and$libresoc.v:197146$13605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" + cell $and $and$libresoc.v:197941$13199 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -409428,10 +374097,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 3'100 - connect \Y $and$libresoc.v:197146$13605_Y + connect \Y $and$libresoc.v:197941$13199_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $and $and$libresoc.v:197149$13608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" + cell $and $and$libresoc.v:197944$13202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409439,10 +374108,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$232 - connect \Y $and$libresoc.v:197149$13608_Y + connect \Y $and$libresoc.v:197944$13202_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197154$13613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $and $and$libresoc.v:197949$13207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409450,10 +374119,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$238 connect \B \$240 - connect \Y $and$libresoc.v:197154$13613_Y + connect \Y $and$libresoc.v:197949$13207_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197157$13616 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $and $and$libresoc.v:197952$13210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409461,10 +374130,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$244 connect \B \$246 - connect \Y $and$libresoc.v:197157$13616_Y + connect \Y $and$libresoc.v:197952$13210_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:197172$13633 + cell $and $and$libresoc.v:197967$13227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409472,10 +374141,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_cu_st__rel_o connect \B \$34 - connect \Y $and$libresoc.v:197172$13633_Y + connect \Y $and$libresoc.v:197967$13227_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197178$13640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $and $and$libresoc.v:197973$13234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409483,10 +374152,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:197178$13640_Y + connect \Y $and$libresoc.v:197973$13234_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $and $and$libresoc.v:197180$13642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" + cell $and $and$libresoc.v:197975$13236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409494,10 +374163,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$50 - connect \Y $and$libresoc.v:197180$13642_Y + connect \Y $and$libresoc.v:197975$13236_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197183$13645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $and $and$libresoc.v:197978$13239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409505,10 +374174,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$54 connect \B \$56 - connect \Y $and$libresoc.v:197183$13645_Y + connect \Y $and$libresoc.v:197978$13239_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197189$13650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $and $and$libresoc.v:197984$13244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409516,10 +374185,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$66 connect \B \$68 - connect \Y $and$libresoc.v:197189$13650_Y + connect \Y $and$libresoc.v:197984$13244_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $and $and$libresoc.v:197191$13652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" + cell $and $and$libresoc.v:197986$13246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409527,10 +374196,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$72 - connect \Y $and$libresoc.v:197191$13652_Y + connect \Y $and$libresoc.v:197986$13246_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197194$13655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $and $and$libresoc.v:197989$13249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409538,10 +374207,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$76 connect \B \$78 - connect \Y $and$libresoc.v:197194$13655_Y + connect \Y $and$libresoc.v:197989$13249_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $eq $eq$libresoc.v:197103$13564 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" + cell $eq $eq$libresoc.v:197898$13158 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409549,10 +374218,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:197103$13564_Y + connect \Y $eq$libresoc.v:197898$13158_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $eq $eq$libresoc.v:197148$13607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" + cell $eq $eq$libresoc.v:197943$13201 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409560,10 +374229,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:197148$13607_Y + connect \Y $eq$libresoc.v:197943$13201_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" - cell $eq $eq$libresoc.v:197158$13617 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:638" + cell $eq $eq$libresoc.v:197953$13211 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409571,10 +374240,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \next_srcstep connect \B \cur_cur_vl - connect \Y $eq$libresoc.v:197158$13617_Y + connect \Y $eq$libresoc.v:197953$13211_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $eq $eq$libresoc.v:197179$13641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" + cell $eq $eq$libresoc.v:197974$13235 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409582,10 +374251,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:197179$13641_Y + connect \Y $eq$libresoc.v:197974$13235_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $eq $eq$libresoc.v:197190$13651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" + cell $eq $eq$libresoc.v:197985$13245 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409593,34 +374262,34 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:197190$13651_Y + connect \Y $eq$libresoc.v:197985$13245_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:197163$13622 + cell $pos $extend$libresoc.v:197958$13216 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \core_full_rd2__data_o - connect \Y $extend$libresoc.v:197163$13622_Y + connect \Y $extend$libresoc.v:197958$13216_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:197164$13624 + cell $pos $extend$libresoc.v:197959$13218 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \core_full_rd__data_o - connect \Y $extend$libresoc.v:197164$13624_Y + connect \Y $extend$libresoc.v:197959$13218_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:197175$13636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $extend$libresoc.v:197970$13230 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \svstate_i - connect \Y $extend$libresoc.v:197175$13636_Y + connect \Y $extend$libresoc.v:197970$13230_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:197084$13546 + cell $mul $mul$libresoc.v:197879$13140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409628,10 +374297,10 @@ module \ti parameter \Y_WIDTH 7 connect \A \$100 [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:197084$13546_Y + connect \Y $mul$libresoc.v:197879$13140_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:197201$13661 + cell $mul $mul$libresoc.v:197996$13255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409639,10 +374308,10 @@ module \ti parameter \Y_WIDTH 7 connect \A \dec2_cur_pc [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:197201$13661_Y + connect \Y $mul$libresoc.v:197996$13255_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" - cell $ne $ne$libresoc.v:197152$13611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" + cell $ne $ne$libresoc.v:197947$13205 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -409650,10 +374319,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B 1'0 - connect \Y $ne$libresoc.v:197152$13611_Y + connect \Y $ne$libresoc.v:197947$13205_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" - cell $ne $ne$libresoc.v:197160$13619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:725" + cell $ne $ne$libresoc.v:197955$13213 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409661,10 +374330,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_core_core_insn_type connect \B 7'0000001 - connect \Y $ne$libresoc.v:197160$13619_Y + connect \Y $ne$libresoc.v:197955$13213_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" - cell $ne $ne$libresoc.v:197170$13631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:799" + cell $ne $ne$libresoc.v:197965$13225 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -409672,410 +374341,410 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B \$30 - connect \Y $ne$libresoc.v:197170$13631_Y + connect \Y $ne$libresoc.v:197965$13225_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197086$13548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197881$13142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197086$13548_Y + connect \Y $not$libresoc.v:197881$13142_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197087$13549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197882$13143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197087$13549_Y + connect \Y $not$libresoc.v:197882$13143_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197089$13551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197884$13145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197089$13551_Y + connect \Y $not$libresoc.v:197884$13145_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197090$13552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197885$13146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197090$13552_Y + connect \Y $not$libresoc.v:197885$13146_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197097$13558 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197892$13152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197097$13558_Y + connect \Y $not$libresoc.v:197892$13152_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197098$13559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197893$13153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197098$13559_Y + connect \Y $not$libresoc.v:197893$13153_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197100$13561 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197895$13155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197100$13561_Y + connect \Y $not$libresoc.v:197895$13155_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197101$13562 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197896$13156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197101$13562_Y + connect \Y $not$libresoc.v:197896$13156_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197105$13566 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197900$13160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197105$13566_Y + connect \Y $not$libresoc.v:197900$13160_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197106$13567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197901$13161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197106$13567_Y + connect \Y $not$libresoc.v:197901$13161_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197111$13571 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197906$13165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197111$13571_Y + connect \Y $not$libresoc.v:197906$13165_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197112$13572 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197907$13166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197112$13572_Y + connect \Y $not$libresoc.v:197907$13166_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197114$13574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197909$13168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197114$13574_Y + connect \Y $not$libresoc.v:197909$13168_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197115$13575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197910$13169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197115$13575_Y + connect \Y $not$libresoc.v:197910$13169_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197117$13577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197912$13171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197117$13577_Y + connect \Y $not$libresoc.v:197912$13171_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197118$13578 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197913$13172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197118$13578_Y + connect \Y $not$libresoc.v:197913$13172_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197120$13580 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197915$13174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197120$13580_Y + connect \Y $not$libresoc.v:197915$13174_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197121$13581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197916$13175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197121$13581_Y + connect \Y $not$libresoc.v:197916$13175_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197123$13583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197918$13177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197123$13583_Y + connect \Y $not$libresoc.v:197918$13177_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197124$13584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197919$13178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197124$13584_Y + connect \Y $not$libresoc.v:197919$13178_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197126$13586 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197921$13180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197126$13586_Y + connect \Y $not$libresoc.v:197921$13180_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197127$13587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197922$13181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197127$13587_Y + connect \Y $not$libresoc.v:197922$13181_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197131$13591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197926$13185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197131$13591_Y + connect \Y $not$libresoc.v:197926$13185_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197132$13592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197927$13186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197132$13592_Y + connect \Y $not$libresoc.v:197927$13186_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197134$13594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197929$13188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197134$13594_Y + connect \Y $not$libresoc.v:197929$13188_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197135$13595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197930$13189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197135$13595_Y + connect \Y $not$libresoc.v:197930$13189_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197140$13599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197935$13193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197140$13599_Y + connect \Y $not$libresoc.v:197935$13193_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197141$13600 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197936$13194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197141$13600_Y + connect \Y $not$libresoc.v:197936$13194_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197143$13602 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197938$13196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197143$13602_Y + connect \Y $not$libresoc.v:197938$13196_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197144$13603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197939$13197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197144$13603_Y + connect \Y $not$libresoc.v:197939$13197_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" - cell $not $not$libresoc.v:197150$13609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" + cell $not $not$libresoc.v:197945$13203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:197150$13609_Y + connect \Y $not$libresoc.v:197945$13203_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197151$13610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197946$13204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197151$13610_Y + connect \Y $not$libresoc.v:197946$13204_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197153$13612 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197948$13206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197153$13612_Y + connect \Y $not$libresoc.v:197948$13206_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197155$13614 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197950$13208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197155$13614_Y + connect \Y $not$libresoc.v:197950$13208_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197156$13615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197951$13209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197156$13615_Y + connect \Y $not$libresoc.v:197951$13209_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" - cell $not $not$libresoc.v:197161$13620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" + cell $not $not$libresoc.v:197956$13214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:197161$13620_Y + connect \Y $not$libresoc.v:197956$13214_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" - cell $not $not$libresoc.v:197162$13621 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" + cell $not $not$libresoc.v:197957$13215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:197162$13621_Y + connect \Y $not$libresoc.v:197957$13215_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:197171$13632 + cell $not $not$libresoc.v:197966$13226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o_dly - connect \Y $not$libresoc.v:197171$13632_Y + connect \Y $not$libresoc.v:197966$13226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" - cell $not $not$libresoc.v:197173$13634 + cell $not $not$libresoc.v:197968$13228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_i_ok - connect \Y $not$libresoc.v:197173$13634_Y + connect \Y $not$libresoc.v:197968$13228_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" - cell $not $not$libresoc.v:197174$13635 + cell $not $not$libresoc.v:197969$13229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \svstate_i_ok - connect \Y $not$libresoc.v:197174$13635_Y + connect \Y $not$libresoc.v:197969$13229_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197176$13638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197971$13232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197176$13638_Y + connect \Y $not$libresoc.v:197971$13232_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197177$13639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197972$13233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197177$13639_Y + connect \Y $not$libresoc.v:197972$13233_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197181$13643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197976$13237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197181$13643_Y + connect \Y $not$libresoc.v:197976$13237_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197182$13644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197977$13238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197182$13644_Y + connect \Y $not$libresoc.v:197977$13238_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197187$13648 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197982$13242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197187$13648_Y + connect \Y $not$libresoc.v:197982$13242_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197188$13649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $not $not$libresoc.v:197983$13243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197188$13649_Y + connect \Y $not$libresoc.v:197983$13243_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197192$13653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197987$13247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197192$13653_Y + connect \Y $not$libresoc.v:197987$13247_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197193$13654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $not $not$libresoc.v:197988$13248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197193$13654_Y + connect \Y $not$libresoc.v:197988$13248_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" - cell $not $not$libresoc.v:197198$13658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" + cell $not $not$libresoc.v:197993$13252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read - connect \Y $not$libresoc.v:197198$13658_Y + connect \Y $not$libresoc.v:197993$13252_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" - cell $not $not$libresoc.v:197199$13659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" + cell $not $not$libresoc.v:197994$13253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read - connect \Y $not$libresoc.v:197199$13659_Y + connect \Y $not$libresoc.v:197994$13253_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:197092$13554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" + cell $or $or$libresoc.v:197887$13148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410083,10 +374752,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197092$13554_Y + connect \Y $or$libresoc.v:197887$13148_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:197094$13555 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" + cell $or $or$libresoc.v:197889$13149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410094,10 +374763,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$120 connect \B \is_last - connect \Y $or$libresoc.v:197094$13555_Y + connect \Y $or$libresoc.v:197889$13149_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:197108$13569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" + cell $or $or$libresoc.v:197903$13163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410105,10 +374774,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197108$13569_Y + connect \Y $or$libresoc.v:197903$13163_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:197110$13570 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" + cell $or $or$libresoc.v:197905$13164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410116,10 +374785,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$154 connect \B \is_last - connect \Y $or$libresoc.v:197110$13570_Y + connect \Y $or$libresoc.v:197905$13164_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:197137$13597 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" + cell $or $or$libresoc.v:197932$13191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410127,10 +374796,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197137$13597_Y + connect \Y $or$libresoc.v:197932$13191_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:197139$13598 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" + cell $or $or$libresoc.v:197934$13192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410138,10 +374807,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$212 connect \B \is_last - connect \Y $or$libresoc.v:197139$13598_Y + connect \Y $or$libresoc.v:197934$13192_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" - cell $or $or$libresoc.v:197168$13629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:799" + cell $or $or$libresoc.v:197963$13223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410149,10 +374818,10 @@ module \ti parameter \Y_WIDTH 1 connect \A 1'0 connect \B \dbg_core_rst_o - connect \Y $or$libresoc.v:197168$13629_Y + connect \Y $or$libresoc.v:197963$13223_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" - cell $or $or$libresoc.v:197169$13630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:799" + cell $or $or$libresoc.v:197964$13224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410160,10 +374829,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$28 connect \B \rst - connect \Y $or$libresoc.v:197169$13630_Y + connect \Y $or$libresoc.v:197964$13224_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:197184$13646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" + cell $or $or$libresoc.v:197979$13240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410171,10 +374840,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197184$13646_Y + connect \Y $or$libresoc.v:197979$13240_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:197186$13647 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" + cell $or $or$libresoc.v:197981$13241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410182,10 +374851,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$62 connect \B \is_last - connect \Y $or$libresoc.v:197186$13647_Y + connect \Y $or$libresoc.v:197981$13241_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:197195$13656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" + cell $or $or$libresoc.v:197990$13250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410193,10 +374862,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197195$13656_Y + connect \Y $or$libresoc.v:197990$13250_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:197197$13657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" + cell $or $or$libresoc.v:197992$13251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410204,58 +374873,58 @@ module \ti parameter \Y_WIDTH 1 connect \A \$84 connect \B \is_last - connect \Y $or$libresoc.v:197197$13657_Y + connect \Y $or$libresoc.v:197992$13251_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:197159$13618 + cell $pos $pos$libresoc.v:197954$13212 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } - connect \Y $pos$libresoc.v:197159$13618_Y + connect \Y $pos$libresoc.v:197954$13212_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:197163$13623 + cell $pos $pos$libresoc.v:197958$13217 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:197163$13622_Y - connect \Y $pos$libresoc.v:197163$13623_Y + connect \A $extend$libresoc.v:197958$13216_Y + connect \Y $pos$libresoc.v:197958$13217_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:197164$13625 + cell $pos $pos$libresoc.v:197959$13219 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:197164$13624_Y - connect \Y $pos$libresoc.v:197164$13625_Y + connect \A $extend$libresoc.v:197959$13218_Y + connect \Y $pos$libresoc.v:197959$13219_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:197175$13637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" + cell $pos $pos$libresoc.v:197970$13231 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:197175$13636_Y - connect \Y $pos$libresoc.v:197175$13637_Y + connect \A $extend$libresoc.v:197970$13230_Y + connect \Y $pos$libresoc.v:197970$13231_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:197130$13590 + cell $reduce_or $reduce_or$libresoc.v:197925$13184 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$195 - connect \Y $reduce_or$libresoc.v:197130$13590_Y + connect \Y $reduce_or$libresoc.v:197925$13184_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:197147$13606 + cell $reduce_or $reduce_or$libresoc.v:197942$13200 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$229 - connect \Y $reduce_or$libresoc.v:197147$13606_Y + connect \Y $reduce_or$libresoc.v:197942$13200_Y end - attribute \src "libresoc.v:197085.18-197085.41" - cell $shr $shr$libresoc.v:197085$13547 + attribute \src "libresoc.v:197880.18-197880.41" + cell $shr $shr$libresoc.v:197880$13141 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -410263,10 +374932,10 @@ module \ti parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$103 - connect \Y $shr$libresoc.v:197085$13547_Y + connect \Y $shr$libresoc.v:197880$13141_Y end - attribute \src "libresoc.v:197202.18-197202.40" - cell $shr $shr$libresoc.v:197202$13662 + attribute \src "libresoc.v:197997.18-197997.40" + cell $shr $shr$libresoc.v:197997$13256 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -410274,10 +374943,10 @@ module \ti parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$96 - connect \Y $shr$libresoc.v:197202$13662_Y + connect \Y $shr$libresoc.v:197997$13256_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" - cell $sub $sub$libresoc.v:197165$13626 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1003" + cell $sub $sub$libresoc.v:197960$13220 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -410285,10 +374954,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $sub$libresoc.v:197165$13626_Y + connect \Y $sub$libresoc.v:197960$13220_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" - cell $sub $sub$libresoc.v:197167$13628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" + cell $sub $sub$libresoc.v:197962$13222 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -410296,10 +374965,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \delay connect \B 1'1 - connect \Y $sub$libresoc.v:197167$13628_Y + connect \Y $sub$libresoc.v:197962$13222_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:197411.8-197509.4" + attribute \src "libresoc.v:198206.8-198304.4" cell \core \core connect \bigendian_i \core_bigendian_i$10 connect \cia__data_o \core_cia__data_o @@ -410400,7 +375069,7 @@ module \ti connect \wen$10 \core_wen$11 end attribute \module_not_derived 1 - attribute \src "libresoc.v:197510.7-197541.4" + attribute \src "libresoc.v:198305.7-198336.4" cell \dbg \dbg connect \clk \clk connect \core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_dststep @@ -410434,7 +375103,7 @@ module \ti connect \terminate_i \dbg_terminate_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:197542.8-197609.4" + attribute \src "libresoc.v:198337.8-198404.4" cell \dec2 \dec2 connect \asmcode \dec2_asmcode connect \bigendian \dec2_bigendian @@ -410504,7 +375173,7 @@ module \ti connect \xer_out \dec2_xer_out end attribute \module_not_derived 1 - attribute \src "libresoc.v:197610.8-197626.4" + attribute \src "libresoc.v:198405.8-198421.4" cell \imem \imem connect \a_pc_i \imem_a_pc_i connect \a_valid_i \imem_a_valid_i @@ -410523,7 +375192,7 @@ module \ti connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:197627.8-197955.4" + attribute \src "libresoc.v:198422.8-198706.4" cell \jtag \jtag connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -410654,14 +375323,6 @@ module \ti connect \mspi0_miso__pad__i \mspi0_miso__pad__i connect \mspi0_mosi__core__o \mspi0_mosi__core__o connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o - connect \mspi1_clk__core__o \mspi1_clk__core__o - connect \mspi1_clk__pad__o \mspi1_clk__pad__o - connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o - connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o - connect \mspi1_miso__core__i \mspi1_miso__core__i - connect \mspi1_miso__pad__i \mspi1_miso__pad__i - connect \mspi1_mosi__core__o \mspi1_mosi__core__o - connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o connect \mtwi_scl__core__o \mtwi_scl__core__o connect \mtwi_scl__pad__o \mtwi_scl__pad__o connect \mtwi_sda__core__i \mtwi_sda__core__i @@ -410670,43 +375331,7 @@ module \ti connect \mtwi_sda__pad__i \mtwi_sda__pad__i connect \mtwi_sda__pad__o \mtwi_sda__pad__o connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe - connect \pwm_0__core__o \pwm_0__core__o - connect \pwm_0__pad__o \pwm_0__pad__o - connect \pwm_1__core__o \pwm_1__core__o - connect \pwm_1__pad__o \pwm_1__pad__o connect \rst \rst - connect \sd0_clk__core__o \sd0_clk__core__o - connect \sd0_clk__pad__o \sd0_clk__pad__o - connect \sd0_cmd__core__i \sd0_cmd__core__i - connect \sd0_cmd__core__o \sd0_cmd__core__o - connect \sd0_cmd__core__oe \sd0_cmd__core__oe - connect \sd0_cmd__pad__i \sd0_cmd__pad__i - connect \sd0_cmd__pad__o \sd0_cmd__pad__o - connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe - connect \sd0_data0__core__i \sd0_data0__core__i - connect \sd0_data0__core__o \sd0_data0__core__o - connect \sd0_data0__core__oe \sd0_data0__core__oe - connect \sd0_data0__pad__i \sd0_data0__pad__i - connect \sd0_data0__pad__o \sd0_data0__pad__o - connect \sd0_data0__pad__oe \sd0_data0__pad__oe - connect \sd0_data1__core__i \sd0_data1__core__i - connect \sd0_data1__core__o \sd0_data1__core__o - connect \sd0_data1__core__oe \sd0_data1__core__oe - connect \sd0_data1__pad__i \sd0_data1__pad__i - connect \sd0_data1__pad__o \sd0_data1__pad__o - connect \sd0_data1__pad__oe \sd0_data1__pad__oe - connect \sd0_data2__core__i \sd0_data2__core__i - connect \sd0_data2__core__o \sd0_data2__core__o - connect \sd0_data2__core__oe \sd0_data2__core__oe - connect \sd0_data2__pad__i \sd0_data2__pad__i - connect \sd0_data2__pad__o \sd0_data2__pad__o - connect \sd0_data2__pad__oe \sd0_data2__pad__oe - connect \sd0_data3__core__i \sd0_data3__core__i - connect \sd0_data3__core__o \sd0_data3__core__o - connect \sd0_data3__core__oe \sd0_data3__core__oe - connect \sd0_data3__pad__i \sd0_data3__pad__i - connect \sd0_data3__pad__o \sd0_data3__pad__o - connect \sd0_data3__pad__oe \sd0_data3__pad__oe connect \sdr_a_0__core__o \sdr_a_0__core__o connect \sdr_a_0__pad__o \sdr_a_0__pad__o connect \sdr_a_10__core__o \sdr_a_10__core__o @@ -410854,7 +375479,7 @@ module \ti connect \wb_sram_en \jtag_wb_sram_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:197956.12-197968.4" + attribute \src "libresoc.v:198707.12-198719.4" cell \sram4k_0 \sram4k_0 connect \clk \clk connect \enable \sram4k_0_enable @@ -410869,7 +375494,7 @@ module \ti connect \sram4k_0_wb__we \sram4k_0_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:197969.12-197981.4" + attribute \src "libresoc.v:198720.12-198732.4" cell \sram4k_1 \sram4k_1 connect \clk \clk connect \enable \sram4k_1_enable @@ -410884,7 +375509,7 @@ module \ti connect \sram4k_1_wb__we \sram4k_1_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:197982.12-197994.4" + attribute \src "libresoc.v:198733.12-198745.4" cell \sram4k_2 \sram4k_2 connect \clk \clk connect \enable \sram4k_2_enable @@ -410899,7 +375524,7 @@ module \ti connect \sram4k_2_wb__we \sram4k_2_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:197995.12-198007.4" + attribute \src "libresoc.v:198746.12-198758.4" cell \sram4k_3 \sram4k_3 connect \clk \clk connect \enable \sram4k_3_enable @@ -410914,7 +375539,7 @@ module \ti connect \sram4k_3_wb__we \sram4k_3_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:198008.12-198022.4" + attribute \src "libresoc.v:198759.12-198773.4" cell \xics_icp \xics_icp connect \clk \clk connect \core_irq_o \xics_icp_core_irq_o @@ -410931,7 +375556,7 @@ module \ti connect \rst \rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:198023.12-198036.4" + attribute \src "libresoc.v:198774.12-198787.4" cell \xics_ics \xics_ics connect \clk \clk connect \icp_o_pri \xics_ics_icp_o_pri @@ -410946,1582 +375571,1582 @@ module \ti connect \int_level_i \int_level_i connect \rst \rst end - attribute \src "libresoc.v:194646.7-194646.20" - process $proc$libresoc.v:194646$14246 + attribute \src "libresoc.v:195733.7-195733.20" + process $proc$libresoc.v:195733$13768 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:194914.13-194914.33" - process $proc$libresoc.v:194914$14247 + attribute \src "libresoc.v:196001.13-196001.33" + process $proc$libresoc.v:196001$13769 assign { } { } assign $1\core_asmcode[7:0] 8'00000000 sync always sync init update \core_asmcode $1\core_asmcode[7:0] end - attribute \src "libresoc.v:194920.7-194920.35" - process $proc$libresoc.v:194920$14248 + attribute \src "libresoc.v:196007.7-196007.35" + process $proc$libresoc.v:196007$13770 assign { } { } - assign $0\core_bigendian_i$10[0:0]$14249 1'0 + assign $0\core_bigendian_i$10[0:0]$13771 1'0 sync always sync init - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14249 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13771 end - attribute \src "libresoc.v:194928.14-194928.55" - process $proc$libresoc.v:194928$14250 + attribute \src "libresoc.v:196015.14-196015.55" + process $proc$libresoc.v:196015$13772 assign { } { } assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_cia $1\core_core_core_cia[63:0] end - attribute \src "libresoc.v:194932.13-194932.41" - process $proc$libresoc.v:194932$14251 + attribute \src "libresoc.v:196019.13-196019.41" + process $proc$libresoc.v:196019$13773 assign { } { } assign $1\core_core_core_cr_rd[7:0] 8'00000000 sync always sync init update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:194936.7-194936.37" - process $proc$libresoc.v:194936$14252 + attribute \src "libresoc.v:196023.7-196023.37" + process $proc$libresoc.v:196023$13774 assign { } { } assign $1\core_core_core_cr_rd_ok[0:0] 1'0 sync always sync init update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:194940.13-194940.41" - process $proc$libresoc.v:194940$14253 + attribute \src "libresoc.v:196027.13-196027.41" + process $proc$libresoc.v:196027$13775 assign { } { } assign $1\core_core_core_cr_wr[7:0] 8'00000000 sync always sync init update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:194944.7-194944.42" - process $proc$libresoc.v:194944$14254 + attribute \src "libresoc.v:196031.7-196031.42" + process $proc$libresoc.v:196031$13776 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$14255 1'0 + assign $0\core_core_core_exc_$signal[0:0]$13777 1'0 sync always sync init - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14255 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13777 end - attribute \src "libresoc.v:194946.7-194946.44" - process $proc$libresoc.v:194946$14256 + attribute \src "libresoc.v:196033.7-196033.44" + process $proc$libresoc.v:196033$13778 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$14257 1'0 + assign $0\core_core_core_exc_$signal$3[0:0]$13779 1'0 sync always sync init - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14257 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13779 end - attribute \src "libresoc.v:194950.7-194950.44" - process $proc$libresoc.v:194950$14258 + attribute \src "libresoc.v:196037.7-196037.44" + process $proc$libresoc.v:196037$13780 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$14259 1'0 + assign $0\core_core_core_exc_$signal$4[0:0]$13781 1'0 sync always sync init - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14259 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13781 end - attribute \src "libresoc.v:194954.7-194954.44" - process $proc$libresoc.v:194954$14260 + attribute \src "libresoc.v:196041.7-196041.44" + process $proc$libresoc.v:196041$13782 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$14261 1'0 + assign $0\core_core_core_exc_$signal$5[0:0]$13783 1'0 sync always sync init - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14261 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13783 end - attribute \src "libresoc.v:194958.7-194958.44" - process $proc$libresoc.v:194958$14262 + attribute \src "libresoc.v:196045.7-196045.44" + process $proc$libresoc.v:196045$13784 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$14263 1'0 + assign $0\core_core_core_exc_$signal$6[0:0]$13785 1'0 sync always sync init - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14263 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13785 end - attribute \src "libresoc.v:194962.7-194962.44" - process $proc$libresoc.v:194962$14264 + attribute \src "libresoc.v:196049.7-196049.44" + process $proc$libresoc.v:196049$13786 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$14265 1'0 + assign $0\core_core_core_exc_$signal$7[0:0]$13787 1'0 sync always sync init - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14265 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13787 end - attribute \src "libresoc.v:194966.7-194966.44" - process $proc$libresoc.v:194966$14266 + attribute \src "libresoc.v:196053.7-196053.44" + process $proc$libresoc.v:196053$13788 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$14267 1'0 + assign $0\core_core_core_exc_$signal$8[0:0]$13789 1'0 sync always sync init - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14267 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13789 end - attribute \src "libresoc.v:194970.7-194970.44" - process $proc$libresoc.v:194970$14268 + attribute \src "libresoc.v:196057.7-196057.44" + process $proc$libresoc.v:196057$13790 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$14269 1'0 + assign $0\core_core_core_exc_$signal$9[0:0]$13791 1'0 sync always sync init - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14269 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13791 end - attribute \src "libresoc.v:194991.14-194991.47" - process $proc$libresoc.v:194991$14270 + attribute \src "libresoc.v:196078.14-196078.47" + process $proc$libresoc.v:196078$13792 assign { } { } assign $1\core_core_core_fn_unit[13:0] 14'00000000000000 sync always sync init update \core_core_core_fn_unit $1\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:194999.13-194999.46" - process $proc$libresoc.v:194999$14271 + attribute \src "libresoc.v:196086.13-196086.46" + process $proc$libresoc.v:196086$13793 assign { } { } assign $1\core_core_core_input_carry[1:0] 2'00 sync always sync init update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:195003.14-195003.41" - process $proc$libresoc.v:195003$14272 + attribute \src "libresoc.v:196090.14-196090.41" + process $proc$libresoc.v:196090$13794 assign { } { } assign $1\core_core_core_insn[31:0] 0 sync always sync init update \core_core_core_insn $1\core_core_core_insn[31:0] end - attribute \src "libresoc.v:195082.13-195082.45" - process $proc$libresoc.v:195082$14273 + attribute \src "libresoc.v:196169.13-196169.45" + process $proc$libresoc.v:196169$13795 assign { } { } assign $1\core_core_core_insn_type[6:0] 7'0000000 sync always sync init update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:195086.7-195086.37" - process $proc$libresoc.v:195086$14274 + attribute \src "libresoc.v:196173.7-196173.37" + process $proc$libresoc.v:196173$13796 assign { } { } assign $1\core_core_core_is_32bit[0:0] 1'0 sync always sync init update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:195090.14-195090.55" - process $proc$libresoc.v:195090$14275 + attribute \src "libresoc.v:196177.14-196177.55" + process $proc$libresoc.v:196177$13797 assign { } { } assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_msr $1\core_core_core_msr[63:0] end - attribute \src "libresoc.v:195094.7-195094.31" - process $proc$libresoc.v:195094$14276 + attribute \src "libresoc.v:196181.7-196181.31" + process $proc$libresoc.v:196181$13798 assign { } { } assign $1\core_core_core_oe[0:0] 1'0 sync always sync init update \core_core_core_oe $1\core_core_core_oe[0:0] end - attribute \src "libresoc.v:195098.7-195098.34" - process $proc$libresoc.v:195098$14277 + attribute \src "libresoc.v:196185.7-196185.34" + process $proc$libresoc.v:196185$13799 assign { } { } assign $1\core_core_core_oe_ok[0:0] 1'0 sync always sync init update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:195102.7-195102.31" - process $proc$libresoc.v:195102$14278 + attribute \src "libresoc.v:196189.7-196189.31" + process $proc$libresoc.v:196189$13800 assign { } { } assign $1\core_core_core_rc[0:0] 1'0 sync always sync init update \core_core_core_rc $1\core_core_core_rc[0:0] end - attribute \src "libresoc.v:195106.7-195106.34" - process $proc$libresoc.v:195106$14279 + attribute \src "libresoc.v:196193.7-196193.34" + process $proc$libresoc.v:196193$13801 assign { } { } assign $1\core_core_core_rc_ok[0:0] 1'0 sync always sync init update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:195110.14-195110.48" - process $proc$libresoc.v:195110$14280 + attribute \src "libresoc.v:196197.14-196197.48" + process $proc$libresoc.v:196197$13802 assign { } { } assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 sync always sync init update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:195114.13-195114.44" - process $proc$libresoc.v:195114$14281 + attribute \src "libresoc.v:196201.13-196201.44" + process $proc$libresoc.v:196201$13803 assign { } { } assign $1\core_core_core_traptype[7:0] 8'00000000 sync always sync init update \core_core_core_traptype $1\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:195118.13-195118.37" - process $proc$libresoc.v:195118$14282 + attribute \src "libresoc.v:196205.13-196205.37" + process $proc$libresoc.v:196205$13804 assign { } { } assign $1\core_core_cr_in1[6:0] 7'0000000 sync always sync init update \core_core_cr_in1 $1\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:195122.7-195122.33" - process $proc$libresoc.v:195122$14283 + attribute \src "libresoc.v:196209.7-196209.33" + process $proc$libresoc.v:196209$13805 assign { } { } assign $1\core_core_cr_in1_ok[0:0] 1'0 sync always sync init update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:195126.13-195126.37" - process $proc$libresoc.v:195126$14284 + attribute \src "libresoc.v:196213.13-196213.37" + process $proc$libresoc.v:196213$13806 assign { } { } assign $1\core_core_cr_in2[6:0] 7'0000000 sync always sync init update \core_core_cr_in2 $1\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:195128.13-195128.41" - process $proc$libresoc.v:195128$14285 + attribute \src "libresoc.v:196215.13-196215.41" + process $proc$libresoc.v:196215$13807 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$14286 7'0000000 + assign $0\core_core_cr_in2$1[6:0]$13808 7'0000000 sync always sync init - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14286 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13808 end - attribute \src "libresoc.v:195134.7-195134.33" - process $proc$libresoc.v:195134$14287 + attribute \src "libresoc.v:196221.7-196221.33" + process $proc$libresoc.v:196221$13809 assign { } { } assign $1\core_core_cr_in2_ok[0:0] 1'0 sync always sync init update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:195136.7-195136.37" - process $proc$libresoc.v:195136$14288 + attribute \src "libresoc.v:196223.7-196223.37" + process $proc$libresoc.v:196223$13810 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$14289 1'0 + assign $0\core_core_cr_in2_ok$2[0:0]$13811 1'0 sync always sync init - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14289 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13811 end - attribute \src "libresoc.v:195142.13-195142.37" - process $proc$libresoc.v:195142$14290 + attribute \src "libresoc.v:196229.13-196229.37" + process $proc$libresoc.v:196229$13812 assign { } { } assign $1\core_core_cr_out[6:0] 7'0000000 sync always sync init update \core_core_cr_out $1\core_core_cr_out[6:0] end - attribute \src "libresoc.v:195146.7-195146.32" - process $proc$libresoc.v:195146$14291 + attribute \src "libresoc.v:196233.7-196233.32" + process $proc$libresoc.v:196233$13813 assign { } { } assign $1\core_core_cr_wr_ok[0:0] 1'0 sync always sync init update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:195150.13-195150.38" - process $proc$libresoc.v:195150$14292 + attribute \src "libresoc.v:196237.13-196237.38" + process $proc$libresoc.v:196237$13814 assign { } { } assign $1\core_core_dststep[6:0] 7'0000000 sync always sync init update \core_core_dststep $1\core_core_dststep[6:0] end - attribute \src "libresoc.v:195154.13-195154.33" - process $proc$libresoc.v:195154$14293 + attribute \src "libresoc.v:196241.13-196241.33" + process $proc$libresoc.v:196241$13815 assign { } { } assign $1\core_core_ea[6:0] 7'0000000 sync always sync init update \core_core_ea $1\core_core_ea[6:0] end - attribute \src "libresoc.v:195158.13-195158.35" - process $proc$libresoc.v:195158$14294 + attribute \src "libresoc.v:196245.13-196245.35" + process $proc$libresoc.v:196245$13816 assign { } { } assign $1\core_core_fast1[2:0] 3'000 sync always sync init update \core_core_fast1 $1\core_core_fast1[2:0] end - attribute \src "libresoc.v:195162.7-195162.32" - process $proc$libresoc.v:195162$14295 + attribute \src "libresoc.v:196249.7-196249.32" + process $proc$libresoc.v:196249$13817 assign { } { } assign $1\core_core_fast1_ok[0:0] 1'0 sync always sync init update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:195166.13-195166.35" - process $proc$libresoc.v:195166$14296 + attribute \src "libresoc.v:196253.13-196253.35" + process $proc$libresoc.v:196253$13818 assign { } { } assign $1\core_core_fast2[2:0] 3'000 sync always sync init update \core_core_fast2 $1\core_core_fast2[2:0] end - attribute \src "libresoc.v:195170.7-195170.32" - process $proc$libresoc.v:195170$14297 + attribute \src "libresoc.v:196257.7-196257.32" + process $proc$libresoc.v:196257$13819 assign { } { } assign $1\core_core_fast2_ok[0:0] 1'0 sync always sync init update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:195174.13-195174.36" - process $proc$libresoc.v:195174$14298 + attribute \src "libresoc.v:196261.13-196261.36" + process $proc$libresoc.v:196261$13820 assign { } { } assign $1\core_core_fasto1[2:0] 3'000 sync always sync init update \core_core_fasto1 $1\core_core_fasto1[2:0] end - attribute \src "libresoc.v:195178.13-195178.36" - process $proc$libresoc.v:195178$14299 + attribute \src "libresoc.v:196265.13-196265.36" + process $proc$libresoc.v:196265$13821 assign { } { } assign $1\core_core_fasto2[2:0] 3'000 sync always sync init update \core_core_fasto2 $1\core_core_fasto2[2:0] end - attribute \src "libresoc.v:195182.7-195182.26" - process $proc$libresoc.v:195182$14300 + attribute \src "libresoc.v:196269.7-196269.26" + process $proc$libresoc.v:196269$13822 assign { } { } assign $1\core_core_lk[0:0] 1'0 sync always sync init update \core_core_lk $1\core_core_lk[0:0] end - attribute \src "libresoc.v:195186.13-195186.36" - process $proc$libresoc.v:195186$14301 + attribute \src "libresoc.v:196273.13-196273.36" + process $proc$libresoc.v:196273$13823 assign { } { } assign $1\core_core_maxvl[6:0] 7'0000000 sync always sync init update \core_core_maxvl $1\core_core_maxvl[6:0] end - attribute \src "libresoc.v:195190.14-195190.49" - process $proc$libresoc.v:195190$14302 + attribute \src "libresoc.v:196277.14-196277.49" + process $proc$libresoc.v:196277$13824 assign { } { } assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_pc $1\core_core_pc[63:0] end - attribute \src "libresoc.v:195194.13-195194.35" - process $proc$libresoc.v:195194$14303 + attribute \src "libresoc.v:196281.13-196281.35" + process $proc$libresoc.v:196281$13825 assign { } { } assign $1\core_core_reg1[6:0] 7'0000000 sync always sync init update \core_core_reg1 $1\core_core_reg1[6:0] end - attribute \src "libresoc.v:195198.7-195198.31" - process $proc$libresoc.v:195198$14304 + attribute \src "libresoc.v:196285.7-196285.31" + process $proc$libresoc.v:196285$13826 assign { } { } assign $1\core_core_reg1_ok[0:0] 1'0 sync always sync init update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:195202.13-195202.35" - process $proc$libresoc.v:195202$14305 + attribute \src "libresoc.v:196289.13-196289.35" + process $proc$libresoc.v:196289$13827 assign { } { } assign $1\core_core_reg2[6:0] 7'0000000 sync always sync init update \core_core_reg2 $1\core_core_reg2[6:0] end - attribute \src "libresoc.v:195206.7-195206.31" - process $proc$libresoc.v:195206$14306 + attribute \src "libresoc.v:196293.7-196293.31" + process $proc$libresoc.v:196293$13828 assign { } { } assign $1\core_core_reg2_ok[0:0] 1'0 sync always sync init update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:195210.13-195210.35" - process $proc$libresoc.v:195210$14307 + attribute \src "libresoc.v:196297.13-196297.35" + process $proc$libresoc.v:196297$13829 assign { } { } assign $1\core_core_reg3[6:0] 7'0000000 sync always sync init update \core_core_reg3 $1\core_core_reg3[6:0] end - attribute \src "libresoc.v:195214.7-195214.31" - process $proc$libresoc.v:195214$14308 + attribute \src "libresoc.v:196301.7-196301.31" + process $proc$libresoc.v:196301$13830 assign { } { } assign $1\core_core_reg3_ok[0:0] 1'0 sync always sync init update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:195218.13-195218.35" - process $proc$libresoc.v:195218$14309 + attribute \src "libresoc.v:196305.13-196305.35" + process $proc$libresoc.v:196305$13831 assign { } { } assign $1\core_core_rego[6:0] 7'0000000 sync always sync init update \core_core_rego $1\core_core_rego[6:0] end - attribute \src "libresoc.v:195336.13-195336.37" - process $proc$libresoc.v:195336$14310 + attribute \src "libresoc.v:196321.13-196321.37" + process $proc$libresoc.v:196321$13832 assign { } { } assign $1\core_core_spr1[9:0] 10'0000000000 sync always sync init update \core_core_spr1 $1\core_core_spr1[9:0] end - attribute \src "libresoc.v:195340.7-195340.31" - process $proc$libresoc.v:195340$14311 + attribute \src "libresoc.v:196325.7-196325.31" + process $proc$libresoc.v:196325$13833 assign { } { } assign $1\core_core_spr1_ok[0:0] 1'0 sync always sync init update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:195458.13-195458.37" - process $proc$libresoc.v:195458$14312 + attribute \src "libresoc.v:196341.13-196341.37" + process $proc$libresoc.v:196341$13834 assign { } { } assign $1\core_core_spro[9:0] 10'0000000000 sync always sync init update \core_core_spro $1\core_core_spro[9:0] end - attribute \src "libresoc.v:195462.13-195462.38" - process $proc$libresoc.v:195462$14313 + attribute \src "libresoc.v:196345.13-196345.38" + process $proc$libresoc.v:196345$13835 assign { } { } assign $1\core_core_srcstep[6:0] 7'0000000 sync always sync init update \core_core_srcstep $1\core_core_srcstep[6:0] end - attribute \src "libresoc.v:195466.13-195466.35" - process $proc$libresoc.v:195466$14314 + attribute \src "libresoc.v:196349.13-196349.35" + process $proc$libresoc.v:196349$13836 assign { } { } assign $1\core_core_subvl[1:0] 2'00 sync always sync init update \core_core_subvl $1\core_core_subvl[1:0] end - attribute \src "libresoc.v:195470.13-195470.36" - process $proc$libresoc.v:195470$14315 + attribute \src "libresoc.v:196353.13-196353.36" + process $proc$libresoc.v:196353$13837 assign { } { } assign $1\core_core_svstep[1:0] 2'00 sync always sync init update \core_core_svstep $1\core_core_svstep[1:0] end - attribute \src "libresoc.v:195476.13-195476.33" - process $proc$libresoc.v:195476$14316 + attribute \src "libresoc.v:196359.13-196359.33" + process $proc$libresoc.v:196359$13838 assign { } { } assign $1\core_core_vl[6:0] 7'0000000 sync always sync init update \core_core_vl $1\core_core_vl[6:0] end - attribute \src "libresoc.v:195480.13-195480.36" - process $proc$libresoc.v:195480$14317 + attribute \src "libresoc.v:196363.13-196363.36" + process $proc$libresoc.v:196363$13839 assign { } { } assign $1\core_core_xer_in[2:0] 3'000 sync always sync init update \core_core_xer_in $1\core_core_xer_in[2:0] end - attribute \src "libresoc.v:195488.7-195488.28" - process $proc$libresoc.v:195488$14318 + attribute \src "libresoc.v:196371.7-196371.28" + process $proc$libresoc.v:196371$13840 assign { } { } assign $1\core_cr_out_ok[0:0] 1'0 sync always sync init update \core_cr_out_ok $1\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:195504.14-195504.45" - process $proc$libresoc.v:195504$14319 + attribute \src "libresoc.v:196387.14-196387.45" + process $proc$libresoc.v:196387$13841 assign { } { } assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_dec $1\core_dec[63:0] end - attribute \src "libresoc.v:195514.7-195514.24" - process $proc$libresoc.v:195514$14320 + attribute \src "libresoc.v:196397.7-196397.24" + process $proc$libresoc.v:196397$13842 assign { } { } assign $1\core_ea_ok[0:0] 1'0 sync always sync init update \core_ea_ok $1\core_ea_ok[0:0] end - attribute \src "libresoc.v:195518.7-195518.23" - process $proc$libresoc.v:195518$14321 + attribute \src "libresoc.v:196401.7-196401.23" + process $proc$libresoc.v:196401$13843 assign { } { } assign $1\core_eint[0:0] 1'0 sync always sync init update \core_eint $1\core_eint[0:0] end - attribute \src "libresoc.v:195522.7-195522.28" - process $proc$libresoc.v:195522$14322 + attribute \src "libresoc.v:196405.7-196405.28" + process $proc$libresoc.v:196405$13844 assign { } { } assign $1\core_fasto1_ok[0:0] 1'0 sync always sync init update \core_fasto1_ok $1\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:195526.7-195526.28" - process $proc$libresoc.v:195526$14323 + attribute \src "libresoc.v:196409.7-196409.28" + process $proc$libresoc.v:196409$13845 assign { } { } assign $1\core_fasto2_ok[0:0] 1'0 sync always sync init update \core_fasto2_ok $1\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:195554.14-195554.45" - process $proc$libresoc.v:195554$14324 + attribute \src "libresoc.v:196437.14-196437.45" + process $proc$libresoc.v:196437$13846 assign { } { } assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_msr $1\core_msr[63:0] end - attribute \src "libresoc.v:195562.14-195562.37" - process $proc$libresoc.v:195562$14325 + attribute \src "libresoc.v:196445.14-196445.37" + process $proc$libresoc.v:196445$13847 assign { } { } assign $1\core_raw_insn_i[31:0] 0 sync always sync init update \core_raw_insn_i $1\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:195566.7-195566.26" - process $proc$libresoc.v:195566$14326 + attribute \src "libresoc.v:196449.7-196449.26" + process $proc$libresoc.v:196449$13848 assign { } { } assign $1\core_rego_ok[0:0] 1'0 sync always sync init update \core_rego_ok $1\core_rego_ok[0:0] end - attribute \src "libresoc.v:195570.7-195570.26" - process $proc$libresoc.v:195570$14327 + attribute \src "libresoc.v:196453.7-196453.26" + process $proc$libresoc.v:196453$13849 assign { } { } assign $1\core_spro_ok[0:0] 1'0 sync always sync init update \core_spro_ok $1\core_spro_ok[0:0] end - attribute \src "libresoc.v:195582.7-195582.26" - process $proc$libresoc.v:195582$14328 + attribute \src "libresoc.v:196465.7-196465.26" + process $proc$libresoc.v:196465$13850 assign { } { } assign $1\core_sv_a_nz[0:0] 1'0 sync always sync init update \core_sv_a_nz $1\core_sv_a_nz[0:0] end - attribute \src "libresoc.v:195592.7-195592.26" - process $proc$libresoc.v:195592$14329 + attribute \src "libresoc.v:196475.7-196475.26" + process $proc$libresoc.v:196475$13851 assign { } { } assign $1\core_xer_out[0:0] 1'0 sync always sync init update \core_xer_out $1\core_xer_out[0:0] end - attribute \src "libresoc.v:195598.7-195598.30" - process $proc$libresoc.v:195598$14330 + attribute \src "libresoc.v:196481.7-196481.30" + process $proc$libresoc.v:196481$13852 assign { } { } assign $1\cu_st__rel_o_dly[0:0] 1'0 sync always sync init update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:195604.13-195604.36" - process $proc$libresoc.v:195604$14331 + attribute \src "libresoc.v:196487.13-196487.36" + process $proc$libresoc.v:196487$13853 assign { } { } assign $1\cur_cur_dststep[6:0] 7'0000000 sync always sync init update \cur_cur_dststep $1\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:195608.13-195608.34" - process $proc$libresoc.v:195608$14332 + attribute \src "libresoc.v:196491.13-196491.34" + process $proc$libresoc.v:196491$13854 assign { } { } assign $1\cur_cur_maxvl[6:0] 7'0000000 sync always sync init update \cur_cur_maxvl $1\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:195612.13-195612.36" - process $proc$libresoc.v:195612$14333 + attribute \src "libresoc.v:196495.13-196495.36" + process $proc$libresoc.v:196495$13855 assign { } { } assign $1\cur_cur_srcstep[6:0] 7'0000000 sync always sync init update \cur_cur_srcstep $1\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:195616.13-195616.33" - process $proc$libresoc.v:195616$14334 + attribute \src "libresoc.v:196499.13-196499.33" + process $proc$libresoc.v:196499$13856 assign { } { } assign $1\cur_cur_subvl[1:0] 2'00 sync always sync init update \cur_cur_subvl $1\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:195620.13-195620.34" - process $proc$libresoc.v:195620$14335 + attribute \src "libresoc.v:196503.13-196503.34" + process $proc$libresoc.v:196503$13857 assign { } { } assign $1\cur_cur_svstep[1:0] 2'00 sync always sync init update \cur_cur_svstep $1\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:195624.13-195624.31" - process $proc$libresoc.v:195624$14336 + attribute \src "libresoc.v:196507.13-196507.31" + process $proc$libresoc.v:196507$13858 assign { } { } assign $1\cur_cur_vl[6:0] 7'0000000 sync always sync init update \cur_cur_vl $1\cur_cur_vl[6:0] end - attribute \src "libresoc.v:195628.7-195628.24" - process $proc$libresoc.v:195628$14337 + attribute \src "libresoc.v:196511.7-196511.24" + process $proc$libresoc.v:196511$13859 assign { } { } assign $1\d_cr_delay[0:0] 1'0 sync always sync init update \d_cr_delay $1\d_cr_delay[0:0] end - attribute \src "libresoc.v:195632.7-195632.25" - process $proc$libresoc.v:195632$14338 + attribute \src "libresoc.v:196515.7-196515.25" + process $proc$libresoc.v:196515$13860 assign { } { } assign $1\d_reg_delay[0:0] 1'0 sync always sync init update \d_reg_delay $1\d_reg_delay[0:0] end - attribute \src "libresoc.v:195636.7-195636.25" - process $proc$libresoc.v:195636$14339 + attribute \src "libresoc.v:196519.7-196519.25" + process $proc$libresoc.v:196519$13861 assign { } { } assign $1\d_xer_delay[0:0] 1'0 sync always sync init update \d_xer_delay $1\d_xer_delay[0:0] end - attribute \src "libresoc.v:195684.13-195684.34" - process $proc$libresoc.v:195684$14340 + attribute \src "libresoc.v:196567.13-196567.34" + process $proc$libresoc.v:196567$13862 assign { } { } assign $1\dbg_dmi_addr_i[3:0] 4'0000 sync always sync init update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:195688.14-195688.48" - process $proc$libresoc.v:195688$14341 + attribute \src "libresoc.v:196571.14-196571.48" + process $proc$libresoc.v:196571$13863 assign { } { } assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbg_dmi_din $1\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:195694.7-195694.27" - process $proc$libresoc.v:195694$14342 + attribute \src "libresoc.v:196577.7-196577.27" + process $proc$libresoc.v:196577$13864 assign { } { } assign $1\dbg_dmi_req_i[0:0] 1'0 sync always sync init update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:195698.7-195698.26" - process $proc$libresoc.v:195698$14343 + attribute \src "libresoc.v:196581.7-196581.26" + process $proc$libresoc.v:196581$13865 assign { } { } assign $1\dbg_dmi_we_i[0:0] 1'0 sync always sync init update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:195752.14-195752.49" - process $proc$libresoc.v:195752$14344 + attribute \src "libresoc.v:196635.14-196635.49" + process $proc$libresoc.v:196635$13866 assign { } { } assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_dec $1\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:195756.7-195756.27" - process $proc$libresoc.v:195756$14345 + attribute \src "libresoc.v:196639.7-196639.27" + process $proc$libresoc.v:196639$13867 assign { } { } assign $1\dec2_cur_eint[0:0] 1'0 sync always sync init update \dec2_cur_eint $1\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:195760.14-195760.49" - process $proc$libresoc.v:195760$14346 + attribute \src "libresoc.v:196643.14-196643.49" + process $proc$libresoc.v:196643$13868 assign { } { } assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_msr $1\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:195764.14-195764.48" - process $proc$libresoc.v:195764$14347 + attribute \src "libresoc.v:196647.14-196647.48" + process $proc$libresoc.v:196647$13869 assign { } { } assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_pc $1\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:195916.14-195916.40" - process $proc$libresoc.v:195916$14348 + attribute \src "libresoc.v:196799.14-196799.40" + process $proc$libresoc.v:196799$13870 assign { } { } assign $1\dec2_raw_opcode_in[31:0] 0 sync always sync init update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:196186.13-196186.25" - process $proc$libresoc.v:196186$14349 + attribute \src "libresoc.v:197069.13-197069.25" + process $proc$libresoc.v:197069$13871 assign { } { } assign $1\delay[1:0] 2'11 sync always sync init update \delay $1\delay[1:0] end - attribute \src "libresoc.v:196202.7-196202.28" - process $proc$libresoc.v:196202$14350 + attribute \src "libresoc.v:197085.7-197085.28" + process $proc$libresoc.v:197085$13872 assign { } { } assign $1\exec_fsm_state[0:0] 1'0 sync always sync init update \exec_fsm_state $1\exec_fsm_state[0:0] end - attribute \src "libresoc.v:196214.13-196214.35" - process $proc$libresoc.v:196214$14351 + attribute \src "libresoc.v:197097.13-197097.35" + process $proc$libresoc.v:197097$13873 assign { } { } assign $1\fetch_fsm_state[1:0] 2'00 sync always sync init update \fetch_fsm_state $1\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:196226.13-196226.29" - process $proc$libresoc.v:196226$14352 + attribute \src "libresoc.v:197109.13-197109.29" + process $proc$libresoc.v:197109$13874 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:196486.13-196486.35" - process $proc$libresoc.v:196486$14353 + attribute \src "libresoc.v:197369.13-197369.35" + process $proc$libresoc.v:197369$13875 assign { } { } assign $1\issue_fsm_state[2:0] 3'000 sync always sync init update \issue_fsm_state $1\issue_fsm_state[2:0] end - attribute \src "libresoc.v:196490.7-196490.30" - process $proc$libresoc.v:196490$14354 + attribute \src "libresoc.v:197373.7-197373.30" + process $proc$libresoc.v:197373$13876 assign { } { } assign $1\jtag_dmi0__ack_o[0:0] 1'0 sync always sync init update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:196498.14-196498.52" - process $proc$libresoc.v:196498$14355 + attribute \src "libresoc.v:197381.14-197381.52" + process $proc$libresoc.v:197381$13877 assign { } { } assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:196556.7-196556.22" - process $proc$libresoc.v:196556$14356 + attribute \src "libresoc.v:197423.7-197423.22" + process $proc$libresoc.v:197423$13878 assign { } { } assign $1\msr_read[0:0] 1'1 sync always sync init update \msr_read $1\msr_read[0:0] end - attribute \src "libresoc.v:196596.14-196596.40" - process $proc$libresoc.v:196596$14357 + attribute \src "libresoc.v:197463.14-197463.40" + process $proc$libresoc.v:197463$13879 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:196602.7-196602.24" - process $proc$libresoc.v:196602$14358 + attribute \src "libresoc.v:197469.7-197469.24" + process $proc$libresoc.v:197469$13880 assign { } { } assign $1\pc_changed[0:0] 1'0 sync always sync init update \pc_changed $1\pc_changed[0:0] end - attribute \src "libresoc.v:196612.7-196612.25" - process $proc$libresoc.v:196612$14359 + attribute \src "libresoc.v:197479.7-197479.25" + process $proc$libresoc.v:197479$13881 assign { } { } assign $1\pc_ok_delay[0:0] 1'0 sync always sync init update \pc_ok_delay $1\pc_ok_delay[0:0] end - attribute \src "libresoc.v:197056.7-197056.24" - process $proc$libresoc.v:197056$14360 + attribute \src "libresoc.v:197851.7-197851.24" + process $proc$libresoc.v:197851$13882 assign { } { } assign $1\sv_changed[0:0] 1'0 sync always sync init update \sv_changed $1\sv_changed[0:0] end - attribute \src "libresoc.v:197066.7-197066.30" - process $proc$libresoc.v:197066$14361 + attribute \src "libresoc.v:197861.7-197861.30" + process $proc$libresoc.v:197861$13883 assign { } { } assign $1\svstate_ok_delay[0:0] 1'0 sync always sync init update \svstate_ok_delay $1\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:197203.3-197204.41" - process $proc$libresoc.v:197203$13663 + attribute \src "libresoc.v:197998.3-197999.41" + process $proc$libresoc.v:197998$13257 assign { } { } assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next sync posedge \clk update \dec2_cur_dec $0\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:197205.3-197206.41" - process $proc$libresoc.v:197205$13664 + attribute \src "libresoc.v:198000.3-198001.41" + process $proc$libresoc.v:198000$13258 assign { } { } assign $0\core_core_pc[63:0] \core_core_pc$next sync posedge \clk update \core_core_pc $0\core_core_pc[63:0] end - attribute \src "libresoc.v:197207.3-197208.49" - process $proc$libresoc.v:197207$13665 + attribute \src "libresoc.v:198002.3-198003.49" + process $proc$libresoc.v:198002$13259 assign { } { } assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next sync posedge \clk update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:197209.3-197210.39" - process $proc$libresoc.v:197209$13666 + attribute \src "libresoc.v:198004.3-198005.39" + process $proc$libresoc.v:198004$13260 assign { } { } assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next sync posedge \clk update \dbg_dmi_din $0\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:197211.3-197212.41" - process $proc$libresoc.v:197211$13667 + attribute \src "libresoc.v:198006.3-198007.41" + process $proc$libresoc.v:198006$13261 assign { } { } assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next sync posedge \clk update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:197213.3-197214.43" - process $proc$libresoc.v:197213$13668 + attribute \src "libresoc.v:198008.3-198009.43" + process $proc$libresoc.v:198008$13262 assign { } { } assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next sync posedge \clk update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:197215.3-197216.45" - process $proc$libresoc.v:197215$13669 + attribute \src "libresoc.v:198010.3-198011.45" + process $proc$libresoc.v:198010$13263 assign { } { } assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next sync posedge \clk update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:197217.3-197218.33" - process $proc$libresoc.v:197217$13670 + attribute \src "libresoc.v:198012.3-198013.33" + process $proc$libresoc.v:198012$13264 assign { } { } assign $0\core_msr[63:0] \core_msr$next sync posedge \clk update \core_msr $0\core_msr[63:0] end - attribute \src "libresoc.v:197219.3-197220.35" - process $proc$libresoc.v:197219$13671 + attribute \src "libresoc.v:198014.3-198015.35" + process $proc$libresoc.v:198014$13265 assign { } { } assign $0\core_eint[0:0] \core_eint$next sync posedge \clk update \core_eint $0\core_eint[0:0] end - attribute \src "libresoc.v:197221.3-197222.33" - process $proc$libresoc.v:197221$13672 + attribute \src "libresoc.v:198016.3-198017.33" + process $proc$libresoc.v:198016$13266 assign { } { } assign $0\core_dec[63:0] \core_dec$next sync posedge \clk update \core_dec $0\core_dec[63:0] end - attribute \src "libresoc.v:197223.3-197224.49" - process $proc$libresoc.v:197223$13673 + attribute \src "libresoc.v:198018.3-198019.49" + process $proc$libresoc.v:198018$13267 assign { } { } assign $0\core_core_svstep[1:0] \core_core_svstep$next sync posedge \clk update \core_core_svstep $0\core_core_svstep[1:0] end - attribute \src "libresoc.v:197225.3-197226.47" - process $proc$libresoc.v:197225$13674 + attribute \src "libresoc.v:198020.3-198021.47" + process $proc$libresoc.v:198020$13268 assign { } { } assign $0\core_core_subvl[1:0] \core_core_subvl$next sync posedge \clk update \core_core_subvl $0\core_core_subvl[1:0] end - attribute \src "libresoc.v:197227.3-197228.51" - process $proc$libresoc.v:197227$13675 + attribute \src "libresoc.v:198022.3-198023.51" + process $proc$libresoc.v:198022$13269 assign { } { } assign $0\core_core_dststep[6:0] \core_core_dststep$next sync posedge \clk update \core_core_dststep $0\core_core_dststep[6:0] end - attribute \src "libresoc.v:197229.3-197230.51" - process $proc$libresoc.v:197229$13676 + attribute \src "libresoc.v:198024.3-198025.51" + process $proc$libresoc.v:198024$13270 assign { } { } assign $0\core_core_srcstep[6:0] \core_core_srcstep$next sync posedge \clk update \core_core_srcstep $0\core_core_srcstep[6:0] end - attribute \src "libresoc.v:197231.3-197232.41" - process $proc$libresoc.v:197231$13677 + attribute \src "libresoc.v:198026.3-198027.41" + process $proc$libresoc.v:198026$13271 assign { } { } assign $0\core_core_vl[6:0] \core_core_vl$next sync posedge \clk update \core_core_vl $0\core_core_vl[6:0] end - attribute \src "libresoc.v:197233.3-197234.47" - process $proc$libresoc.v:197233$13678 + attribute \src "libresoc.v:198028.3-198029.47" + process $proc$libresoc.v:198028$13272 assign { } { } assign $0\core_core_maxvl[6:0] \core_core_maxvl$next sync posedge \clk update \core_core_maxvl $0\core_core_maxvl[6:0] end - attribute \src "libresoc.v:197235.3-197236.35" - process $proc$libresoc.v:197235$13679 + attribute \src "libresoc.v:198030.3-198031.35" + process $proc$libresoc.v:198030$13273 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:197237.3-197238.41" - process $proc$libresoc.v:197237$13680 + attribute \src "libresoc.v:198032.3-198033.41" + process $proc$libresoc.v:198032$13274 assign { } { } assign $0\core_asmcode[7:0] \core_asmcode$next sync posedge \clk update \core_asmcode $0\core_asmcode[7:0] end - attribute \src "libresoc.v:197239.3-197240.45" - process $proc$libresoc.v:197239$13681 + attribute \src "libresoc.v:198034.3-198035.45" + process $proc$libresoc.v:198034$13275 assign { } { } assign $0\core_core_rego[6:0] \core_core_rego$next sync posedge \clk update \core_core_rego $0\core_core_rego[6:0] end - attribute \src "libresoc.v:197241.3-197242.41" - process $proc$libresoc.v:197241$13682 + attribute \src "libresoc.v:198036.3-198037.41" + process $proc$libresoc.v:198036$13276 assign { } { } assign $0\core_rego_ok[0:0] \core_rego_ok$next sync posedge \clk update \core_rego_ok $0\core_rego_ok[0:0] end - attribute \src "libresoc.v:197243.3-197244.41" - process $proc$libresoc.v:197243$13683 + attribute \src "libresoc.v:198038.3-198039.41" + process $proc$libresoc.v:198038$13277 assign { } { } assign $0\core_core_ea[6:0] \core_core_ea$next sync posedge \clk update \core_core_ea $0\core_core_ea[6:0] end - attribute \src "libresoc.v:197245.3-197246.37" - process $proc$libresoc.v:197245$13684 + attribute \src "libresoc.v:198040.3-198041.37" + process $proc$libresoc.v:198040$13278 assign { } { } assign $0\core_ea_ok[0:0] \core_ea_ok$next sync posedge \clk update \core_ea_ok $0\core_ea_ok[0:0] end - attribute \src "libresoc.v:197247.3-197248.45" - process $proc$libresoc.v:197247$13685 + attribute \src "libresoc.v:198042.3-198043.45" + process $proc$libresoc.v:198042$13279 assign { } { } assign $0\core_core_reg1[6:0] \core_core_reg1$next sync posedge \clk update \core_core_reg1 $0\core_core_reg1[6:0] end - attribute \src "libresoc.v:197249.3-197250.51" - process $proc$libresoc.v:197249$13686 + attribute \src "libresoc.v:198044.3-198045.51" + process $proc$libresoc.v:198044$13280 assign { } { } assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next sync posedge \clk update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:197251.3-197252.45" - process $proc$libresoc.v:197251$13687 + attribute \src "libresoc.v:198046.3-198047.45" + process $proc$libresoc.v:198046$13281 assign { } { } assign $0\core_core_reg2[6:0] \core_core_reg2$next sync posedge \clk update \core_core_reg2 $0\core_core_reg2[6:0] end - attribute \src "libresoc.v:197253.3-197254.51" - process $proc$libresoc.v:197253$13688 + attribute \src "libresoc.v:198048.3-198049.51" + process $proc$libresoc.v:198048$13282 assign { } { } assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next sync posedge \clk update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:197255.3-197256.45" - process $proc$libresoc.v:197255$13689 + attribute \src "libresoc.v:198050.3-198051.45" + process $proc$libresoc.v:198050$13283 assign { } { } assign $0\core_core_reg3[6:0] \core_core_reg3$next sync posedge \clk update \core_core_reg3 $0\core_core_reg3[6:0] end - attribute \src "libresoc.v:197257.3-197258.39" - process $proc$libresoc.v:197257$13690 + attribute \src "libresoc.v:198052.3-198053.39" + process $proc$libresoc.v:198052$13284 assign { } { } assign $0\d_xer_delay[0:0] \d_xer_delay$next sync posedge \clk update \d_xer_delay $0\d_xer_delay[0:0] end - attribute \src "libresoc.v:197259.3-197260.51" - process $proc$libresoc.v:197259$13691 + attribute \src "libresoc.v:198054.3-198055.51" + process $proc$libresoc.v:198054$13285 assign { } { } assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next sync posedge \clk update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:197261.3-197262.45" - process $proc$libresoc.v:197261$13692 + attribute \src "libresoc.v:198056.3-198057.45" + process $proc$libresoc.v:198056$13286 assign { } { } assign $0\core_core_spro[9:0] \core_core_spro$next sync posedge \clk update \core_core_spro $0\core_core_spro[9:0] end - attribute \src "libresoc.v:197263.3-197264.41" - process $proc$libresoc.v:197263$13693 + attribute \src "libresoc.v:198058.3-198059.41" + process $proc$libresoc.v:198058$13287 assign { } { } assign $0\core_spro_ok[0:0] \core_spro_ok$next sync posedge \clk update \core_spro_ok $0\core_spro_ok[0:0] end - attribute \src "libresoc.v:197265.3-197266.45" - process $proc$libresoc.v:197265$13694 + attribute \src "libresoc.v:198060.3-198061.45" + process $proc$libresoc.v:198060$13288 assign { } { } assign $0\core_core_spr1[9:0] \core_core_spr1$next sync posedge \clk update \core_core_spr1 $0\core_core_spr1[9:0] end - attribute \src "libresoc.v:197267.3-197268.51" - process $proc$libresoc.v:197267$13695 + attribute \src "libresoc.v:198062.3-198063.51" + process $proc$libresoc.v:198062$13289 assign { } { } assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next sync posedge \clk update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:197269.3-197270.49" - process $proc$libresoc.v:197269$13696 + attribute \src "libresoc.v:198064.3-198065.49" + process $proc$libresoc.v:198064$13290 assign { } { } assign $0\core_core_xer_in[2:0] \core_core_xer_in$next sync posedge \clk update \core_core_xer_in $0\core_core_xer_in[2:0] end - attribute \src "libresoc.v:197271.3-197272.41" - process $proc$libresoc.v:197271$13697 + attribute \src "libresoc.v:198066.3-198067.41" + process $proc$libresoc.v:198066$13291 assign { } { } assign $0\core_xer_out[0:0] \core_xer_out$next sync posedge \clk update \core_xer_out $0\core_xer_out[0:0] end - attribute \src "libresoc.v:197273.3-197274.47" - process $proc$libresoc.v:197273$13698 + attribute \src "libresoc.v:198068.3-198069.47" + process $proc$libresoc.v:198068$13292 assign { } { } assign $0\core_core_fast1[2:0] \core_core_fast1$next sync posedge \clk update \core_core_fast1 $0\core_core_fast1[2:0] end - attribute \src "libresoc.v:197275.3-197276.53" - process $proc$libresoc.v:197275$13699 + attribute \src "libresoc.v:198070.3-198071.53" + process $proc$libresoc.v:198070$13293 assign { } { } assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next sync posedge \clk update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:197277.3-197278.47" - process $proc$libresoc.v:197277$13700 + attribute \src "libresoc.v:198072.3-198073.47" + process $proc$libresoc.v:198072$13294 assign { } { } assign $0\core_core_fast2[2:0] \core_core_fast2$next sync posedge \clk update \core_core_fast2 $0\core_core_fast2[2:0] end - attribute \src "libresoc.v:197279.3-197280.37" - process $proc$libresoc.v:197279$13701 + attribute \src "libresoc.v:198074.3-198075.37" + process $proc$libresoc.v:198074$13295 assign { } { } assign $0\d_cr_delay[0:0] \d_cr_delay$next sync posedge \clk update \d_cr_delay $0\d_cr_delay[0:0] end - attribute \src "libresoc.v:197281.3-197282.53" - process $proc$libresoc.v:197281$13702 + attribute \src "libresoc.v:198076.3-198077.53" + process $proc$libresoc.v:198076$13296 assign { } { } assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next sync posedge \clk update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:197283.3-197284.49" - process $proc$libresoc.v:197283$13703 + attribute \src "libresoc.v:198078.3-198079.49" + process $proc$libresoc.v:198078$13297 assign { } { } assign $0\core_core_fasto1[2:0] \core_core_fasto1$next sync posedge \clk update \core_core_fasto1 $0\core_core_fasto1[2:0] end - attribute \src "libresoc.v:197285.3-197286.45" - process $proc$libresoc.v:197285$13704 + attribute \src "libresoc.v:198080.3-198081.45" + process $proc$libresoc.v:198080$13298 assign { } { } assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next sync posedge \clk update \core_fasto1_ok $0\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:197287.3-197288.49" - process $proc$libresoc.v:197287$13705 + attribute \src "libresoc.v:198082.3-198083.49" + process $proc$libresoc.v:198082$13299 assign { } { } assign $0\core_core_fasto2[2:0] \core_core_fasto2$next sync posedge \clk update \core_core_fasto2 $0\core_core_fasto2[2:0] end - attribute \src "libresoc.v:197289.3-197290.45" - process $proc$libresoc.v:197289$13706 + attribute \src "libresoc.v:198084.3-198085.45" + process $proc$libresoc.v:198084$13300 assign { } { } assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next sync posedge \clk update \core_fasto2_ok $0\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:197291.3-197292.49" - process $proc$libresoc.v:197291$13707 + attribute \src "libresoc.v:198086.3-198087.49" + process $proc$libresoc.v:198086$13301 assign { } { } assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next sync posedge \clk update \core_core_cr_in1 $0\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:197293.3-197294.55" - process $proc$libresoc.v:197293$13708 + attribute \src "libresoc.v:198088.3-198089.55" + process $proc$libresoc.v:198088$13302 assign { } { } assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next sync posedge \clk update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:197295.3-197296.49" - process $proc$libresoc.v:197295$13709 + attribute \src "libresoc.v:198090.3-198091.49" + process $proc$libresoc.v:198090$13303 assign { } { } assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next sync posedge \clk update \core_core_cr_in2 $0\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:197297.3-197298.55" - process $proc$libresoc.v:197297$13710 + attribute \src "libresoc.v:198092.3-198093.55" + process $proc$libresoc.v:198092$13304 assign { } { } assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next sync posedge \clk update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:197299.3-197300.55" - process $proc$libresoc.v:197299$13711 + attribute \src "libresoc.v:198094.3-198095.55" + process $proc$libresoc.v:198094$13305 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$13712 \core_core_cr_in2$1$next + assign $0\core_core_cr_in2$1[6:0]$13306 \core_core_cr_in2$1$next sync posedge \clk - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13712 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13306 end - attribute \src "libresoc.v:197301.3-197302.39" - process $proc$libresoc.v:197301$13713 + attribute \src "libresoc.v:198096.3-198097.39" + process $proc$libresoc.v:198096$13307 assign { } { } assign $0\d_reg_delay[0:0] \d_reg_delay$next sync posedge \clk update \d_reg_delay $0\d_reg_delay[0:0] end - attribute \src "libresoc.v:197303.3-197304.61" - process $proc$libresoc.v:197303$13714 + attribute \src "libresoc.v:198098.3-198099.61" + process $proc$libresoc.v:198098$13308 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13715 \core_core_cr_in2_ok$2$next + assign $0\core_core_cr_in2_ok$2[0:0]$13309 \core_core_cr_in2_ok$2$next sync posedge \clk - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13715 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13309 end - attribute \src "libresoc.v:197305.3-197306.49" - process $proc$libresoc.v:197305$13716 + attribute \src "libresoc.v:198100.3-198101.49" + process $proc$libresoc.v:198100$13310 assign { } { } assign $0\core_core_cr_out[6:0] \core_core_cr_out$next sync posedge \clk update \core_core_cr_out $0\core_core_cr_out[6:0] end - attribute \src "libresoc.v:197307.3-197308.45" - process $proc$libresoc.v:197307$13717 + attribute \src "libresoc.v:198102.3-198103.45" + process $proc$libresoc.v:198102$13311 assign { } { } assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next sync posedge \clk update \core_cr_out_ok $0\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:197309.3-197310.53" - process $proc$libresoc.v:197309$13718 + attribute \src "libresoc.v:198104.3-198105.53" + process $proc$libresoc.v:198104$13312 assign { } { } assign $0\core_core_core_msr[63:0] \core_core_core_msr$next sync posedge \clk update \core_core_core_msr $0\core_core_core_msr[63:0] end - attribute \src "libresoc.v:197311.3-197312.53" - process $proc$libresoc.v:197311$13719 + attribute \src "libresoc.v:198106.3-198107.53" + process $proc$libresoc.v:198106$13313 assign { } { } assign $0\core_core_core_cia[63:0] \core_core_core_cia$next sync posedge \clk update \core_core_core_cia $0\core_core_core_cia[63:0] end - attribute \src "libresoc.v:197313.3-197314.55" - process $proc$libresoc.v:197313$13720 + attribute \src "libresoc.v:198108.3-198109.55" + process $proc$libresoc.v:198108$13314 assign { } { } assign $0\core_core_core_insn[31:0] \core_core_core_insn$next sync posedge \clk update \core_core_core_insn $0\core_core_core_insn[31:0] end - attribute \src "libresoc.v:197315.3-197316.65" - process $proc$libresoc.v:197315$13721 + attribute \src "libresoc.v:198110.3-198111.65" + process $proc$libresoc.v:198110$13315 assign { } { } assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next sync posedge \clk update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:197317.3-197318.61" - process $proc$libresoc.v:197317$13722 + attribute \src "libresoc.v:198112.3-198113.61" + process $proc$libresoc.v:198112$13316 assign { } { } assign $0\core_core_core_fn_unit[13:0] \core_core_core_fn_unit$next sync posedge \clk update \core_core_core_fn_unit $0\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:197319.3-197320.41" - process $proc$libresoc.v:197319$13723 + attribute \src "libresoc.v:198114.3-198115.41" + process $proc$libresoc.v:198114$13317 assign { } { } assign $0\core_core_lk[0:0] \core_core_lk$next sync posedge \clk update \core_core_lk $0\core_core_lk[0:0] end - attribute \src "libresoc.v:197321.3-197322.51" - process $proc$libresoc.v:197321$13724 + attribute \src "libresoc.v:198116.3-198117.51" + process $proc$libresoc.v:198116$13318 assign { } { } assign $0\core_core_core_rc[0:0] \core_core_core_rc$next sync posedge \clk update \core_core_core_rc $0\core_core_core_rc[0:0] end - attribute \src "libresoc.v:197323.3-197324.45" - process $proc$libresoc.v:197323$13725 + attribute \src "libresoc.v:198118.3-198119.45" + process $proc$libresoc.v:198118$13319 assign { } { } assign $0\exec_fsm_state[0:0] \exec_fsm_state$next sync posedge \clk update \exec_fsm_state $0\exec_fsm_state[0:0] end - attribute \src "libresoc.v:197325.3-197326.57" - process $proc$libresoc.v:197325$13726 + attribute \src "libresoc.v:198120.3-198121.57" + process $proc$libresoc.v:198120$13320 assign { } { } assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next sync posedge \clk update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:197327.3-197328.51" - process $proc$libresoc.v:197327$13727 + attribute \src "libresoc.v:198122.3-198123.51" + process $proc$libresoc.v:198122$13321 assign { } { } assign $0\core_core_core_oe[0:0] \core_core_core_oe$next sync posedge \clk update \core_core_core_oe $0\core_core_core_oe[0:0] end - attribute \src "libresoc.v:197329.3-197330.57" - process $proc$libresoc.v:197329$13728 + attribute \src "libresoc.v:198124.3-198125.57" + process $proc$libresoc.v:198124$13322 assign { } { } assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next sync posedge \clk update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:197331.3-197332.69" - process $proc$libresoc.v:197331$13729 + attribute \src "libresoc.v:198126.3-198127.69" + process $proc$libresoc.v:198126$13323 assign { } { } assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next sync posedge \clk update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:197333.3-197334.63" - process $proc$libresoc.v:197333$13730 + attribute \src "libresoc.v:198128.3-198129.63" + process $proc$libresoc.v:198128$13324 assign { } { } assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next sync posedge \clk update \core_core_core_traptype $0\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:197335.3-197336.71" - process $proc$libresoc.v:197335$13731 + attribute \src "libresoc.v:198130.3-198131.71" + process $proc$libresoc.v:198130$13325 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$13732 \core_core_core_exc_$signal$next + assign $0\core_core_core_exc_$signal[0:0]$13326 \core_core_core_exc_$signal$next sync posedge \clk - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13732 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13326 end - attribute \src "libresoc.v:197337.3-197338.75" - process $proc$libresoc.v:197337$13733 + attribute \src "libresoc.v:198132.3-198133.75" + process $proc$libresoc.v:198132$13327 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$13734 \core_core_core_exc_$signal$3$next + assign $0\core_core_core_exc_$signal$3[0:0]$13328 \core_core_core_exc_$signal$3$next sync posedge \clk - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13734 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13328 end - attribute \src "libresoc.v:197339.3-197340.75" - process $proc$libresoc.v:197339$13735 + attribute \src "libresoc.v:198134.3-198135.75" + process $proc$libresoc.v:198134$13329 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$13736 \core_core_core_exc_$signal$4$next + assign $0\core_core_core_exc_$signal$4[0:0]$13330 \core_core_core_exc_$signal$4$next sync posedge \clk - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13736 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13330 end - attribute \src "libresoc.v:197341.3-197342.75" - process $proc$libresoc.v:197341$13737 + attribute \src "libresoc.v:198136.3-198137.75" + process $proc$libresoc.v:198136$13331 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$13738 \core_core_core_exc_$signal$5$next + assign $0\core_core_core_exc_$signal$5[0:0]$13332 \core_core_core_exc_$signal$5$next sync posedge \clk - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13738 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13332 end - attribute \src "libresoc.v:197343.3-197344.75" - process $proc$libresoc.v:197343$13739 + attribute \src "libresoc.v:198138.3-198139.75" + process $proc$libresoc.v:198138$13333 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$13740 \core_core_core_exc_$signal$6$next + assign $0\core_core_core_exc_$signal$6[0:0]$13334 \core_core_core_exc_$signal$6$next sync posedge \clk - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13740 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13334 end - attribute \src "libresoc.v:197345.3-197346.41" - process $proc$libresoc.v:197345$13741 + attribute \src "libresoc.v:198140.3-198141.41" + process $proc$libresoc.v:198140$13335 assign { } { } assign $0\core_sv_a_nz[0:0] \core_sv_a_nz$next sync posedge \clk update \core_sv_a_nz $0\core_sv_a_nz[0:0] end - attribute \src "libresoc.v:197347.3-197348.75" - process $proc$libresoc.v:197347$13742 + attribute \src "libresoc.v:198142.3-198143.75" + process $proc$libresoc.v:198142$13336 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$13743 \core_core_core_exc_$signal$7$next + assign $0\core_core_core_exc_$signal$7[0:0]$13337 \core_core_core_exc_$signal$7$next sync posedge \clk - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13743 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13337 end - attribute \src "libresoc.v:197349.3-197350.75" - process $proc$libresoc.v:197349$13744 + attribute \src "libresoc.v:198144.3-198145.75" + process $proc$libresoc.v:198144$13338 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$13745 \core_core_core_exc_$signal$8$next + assign $0\core_core_core_exc_$signal$8[0:0]$13339 \core_core_core_exc_$signal$8$next sync posedge \clk - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13745 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13339 end - attribute \src "libresoc.v:197351.3-197352.75" - process $proc$libresoc.v:197351$13746 + attribute \src "libresoc.v:198146.3-198147.75" + process $proc$libresoc.v:198146$13340 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$13747 \core_core_core_exc_$signal$9$next + assign $0\core_core_core_exc_$signal$9[0:0]$13341 \core_core_core_exc_$signal$9$next sync posedge \clk - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13747 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13341 end - attribute \src "libresoc.v:197353.3-197354.63" - process $proc$libresoc.v:197353$13748 + attribute \src "libresoc.v:198148.3-198149.63" + process $proc$libresoc.v:198148$13342 assign { } { } assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next sync posedge \clk update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:197355.3-197356.57" - process $proc$libresoc.v:197355$13749 + attribute \src "libresoc.v:198150.3-198151.57" + process $proc$libresoc.v:198150$13343 assign { } { } assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next sync posedge \clk update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:197357.3-197358.63" - process $proc$libresoc.v:197357$13750 + attribute \src "libresoc.v:198152.3-198153.63" + process $proc$libresoc.v:198152$13344 assign { } { } assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next sync posedge \clk update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:197359.3-197360.57" - process $proc$libresoc.v:197359$13751 + attribute \src "libresoc.v:198154.3-198155.57" + process $proc$libresoc.v:198154$13345 assign { } { } assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next sync posedge \clk update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:197361.3-197362.53" - process $proc$libresoc.v:197361$13752 + attribute \src "libresoc.v:198156.3-198157.53" + process $proc$libresoc.v:198156$13346 assign { } { } assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next sync posedge \clk update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:197363.3-197364.63" - process $proc$libresoc.v:197363$13753 + attribute \src "libresoc.v:198158.3-198159.63" + process $proc$libresoc.v:198158$13347 assign { } { } assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next sync posedge \clk update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:197365.3-197366.37" - process $proc$libresoc.v:197365$13754 + attribute \src "libresoc.v:198160.3-198161.37" + process $proc$libresoc.v:198160$13348 assign { } { } assign $0\sv_changed[0:0] \sv_changed$next sync posedge \clk update \sv_changed $0\sv_changed[0:0] end - attribute \src "libresoc.v:197367.3-197368.57" - process $proc$libresoc.v:197367$13755 + attribute \src "libresoc.v:198162.3-198163.57" + process $proc$libresoc.v:198162$13349 assign { } { } - assign $0\core_bigendian_i$10[0:0]$13756 \core_bigendian_i$10$next + assign $0\core_bigendian_i$10[0:0]$13350 \core_bigendian_i$10$next sync posedge \clk - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13756 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13350 end - attribute \src "libresoc.v:197369.3-197370.37" - process $proc$libresoc.v:197369$13757 + attribute \src "libresoc.v:198164.3-198165.37" + process $proc$libresoc.v:198164$13351 assign { } { } assign $0\pc_changed[0:0] \pc_changed$next sync posedge \clk update \pc_changed $0\pc_changed[0:0] end - attribute \src "libresoc.v:197371.3-197372.47" - process $proc$libresoc.v:197371$13758 + attribute \src "libresoc.v:198166.3-198167.47" + process $proc$libresoc.v:198166$13352 assign { } { } assign $0\issue_fsm_state[2:0] \issue_fsm_state$next sync posedge \clk update \issue_fsm_state $0\issue_fsm_state[2:0] end - attribute \src "libresoc.v:197373.3-197374.53" - process $proc$libresoc.v:197373$13759 + attribute \src "libresoc.v:198168.3-198169.53" + process $proc$libresoc.v:198168$13353 assign { } { } assign $0\dec2_raw_opcode_in[31:0] \dec2_raw_opcode_in$next sync posedge \clk update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:197375.3-197376.23" - process $proc$libresoc.v:197375$13760 + attribute \src "libresoc.v:198170.3-198171.23" + process $proc$libresoc.v:198170$13354 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:197377.3-197378.41" - process $proc$libresoc.v:197377$13761 + attribute \src "libresoc.v:198172.3-198173.41" + process $proc$libresoc.v:198172$13355 assign { } { } assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next sync posedge \clk update \dec2_cur_msr $0\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:197379.3-197380.47" - process $proc$libresoc.v:197379$13762 + attribute \src "libresoc.v:198174.3-198175.47" + process $proc$libresoc.v:198174$13356 assign { } { } assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next sync posedge \clk update \fetch_fsm_state $0\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:197381.3-197382.33" - process $proc$libresoc.v:197381$13763 + attribute \src "libresoc.v:198176.3-198177.33" + process $proc$libresoc.v:198176$13357 assign { } { } assign $0\msr_read[0:0] \msr_read$next sync posedge \clk update \msr_read $0\msr_read[0:0] end - attribute \src "libresoc.v:197383.3-197384.45" - process $proc$libresoc.v:197383$13764 + attribute \src "libresoc.v:198178.3-198179.45" + process $proc$libresoc.v:198178$13358 assign { } { } assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next sync posedge \clk update \cur_cur_svstep $0\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:197385.3-197386.43" - process $proc$libresoc.v:197385$13765 + attribute \src "libresoc.v:198180.3-198181.43" + process $proc$libresoc.v:198180$13359 assign { } { } assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next sync posedge \clk update \cur_cur_subvl $0\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:197387.3-197388.47" - process $proc$libresoc.v:197387$13766 + attribute \src "libresoc.v:198182.3-198183.47" + process $proc$libresoc.v:198182$13360 assign { } { } assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next sync posedge \clk update \cur_cur_dststep $0\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:197389.3-197390.47" - process $proc$libresoc.v:197389$13767 + attribute \src "libresoc.v:198184.3-198185.47" + process $proc$libresoc.v:198184$13361 assign { } { } assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next sync posedge \clk update \core_raw_insn_i $0\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:197391.3-197392.47" - process $proc$libresoc.v:197391$13768 + attribute \src "libresoc.v:198186.3-198187.47" + process $proc$libresoc.v:198186$13362 assign { } { } assign $0\cur_cur_srcstep[6:0] \cur_cur_srcstep$next sync posedge \clk update \cur_cur_srcstep $0\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:197393.3-197394.37" - process $proc$libresoc.v:197393$13769 + attribute \src "libresoc.v:198188.3-198189.37" + process $proc$libresoc.v:198188$13363 assign { } { } assign $0\cur_cur_vl[6:0] \cur_cur_vl$next sync posedge \clk update \cur_cur_vl $0\cur_cur_vl[6:0] end - attribute \src "libresoc.v:197395.3-197396.43" - process $proc$libresoc.v:197395$13770 + attribute \src "libresoc.v:198190.3-198191.43" + process $proc$libresoc.v:198190$13364 assign { } { } assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next sync posedge \clk update \cur_cur_maxvl $0\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:197397.3-197398.39" - process $proc$libresoc.v:197397$13771 + attribute \src "libresoc.v:198192.3-198193.39" + process $proc$libresoc.v:198192$13365 assign { } { } assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next sync posedge \clk update \dec2_cur_pc $0\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:197399.3-197400.49" - process $proc$libresoc.v:197399$13772 + attribute \src "libresoc.v:198194.3-198195.49" + process $proc$libresoc.v:198194$13366 assign { } { } assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next sync posedge \clk update \svstate_ok_delay $0\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:197401.3-197402.39" - process $proc$libresoc.v:197401$13773 + attribute \src "libresoc.v:198196.3-198197.39" + process $proc$libresoc.v:198196$13367 assign { } { } assign $0\pc_ok_delay[0:0] \pc_ok_delay$next sync posedge \clk update \pc_ok_delay $0\pc_ok_delay[0:0] end - attribute \src "libresoc.v:197403.3-197404.43" - process $proc$libresoc.v:197403$13774 + attribute \src "libresoc.v:198198.3-198199.43" + process $proc$libresoc.v:198198$13368 assign { } { } assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o sync posedge \clk update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:197405.3-197406.27" - process $proc$libresoc.v:197405$13775 + attribute \src "libresoc.v:198200.3-198201.27" + process $proc$libresoc.v:198200$13369 assign { } { } assign $0\delay[1:0] \delay$next sync posedge \por_clk update \delay $0\delay[1:0] end - attribute \src "libresoc.v:197407.3-197408.43" - process $proc$libresoc.v:197407$13776 + attribute \src "libresoc.v:198202.3-198203.43" + process $proc$libresoc.v:198202$13370 assign { } { } assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next sync posedge \clk update \dec2_cur_eint $0\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:197409.3-197410.47" - process $proc$libresoc.v:197409$13777 + attribute \src "libresoc.v:198204.3-198205.47" + process $proc$libresoc.v:198204$13371 assign { } { } assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next sync posedge \clk update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:198037.3-198045.6" - process $proc$libresoc.v:198037$13778 + attribute \src "libresoc.v:198788.3-198796.6" + process $proc$libresoc.v:198788$13372 assign { } { } assign { } { } - assign $0\dbg_dmi_addr_i$next[3:0]$13779 $1\dbg_dmi_addr_i$next[3:0]$13780 - attribute \src "libresoc.v:198038.5-198038.29" + assign $0\dbg_dmi_addr_i$next[3:0]$13373 $1\dbg_dmi_addr_i$next[3:0]$13374 + attribute \src "libresoc.v:198789.5-198789.29" switch \initial - attribute \src "libresoc.v:198038.9-198038.17" + attribute \src "libresoc.v:198789.9-198789.17" case 1'1 case end @@ -412530,21 +377155,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_addr_i$next[3:0]$13780 4'0000 + assign $1\dbg_dmi_addr_i$next[3:0]$13374 4'0000 case - assign $1\dbg_dmi_addr_i$next[3:0]$13780 \jtag_dmi0__addr_i + assign $1\dbg_dmi_addr_i$next[3:0]$13374 \jtag_dmi0__addr_i end sync always - update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13779 + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13373 end - attribute \src "libresoc.v:198046.3-198054.6" - process $proc$libresoc.v:198046$13781 + attribute \src "libresoc.v:198797.3-198805.6" + process $proc$libresoc.v:198797$13375 assign { } { } assign { } { } - assign $0\dbg_dmi_req_i$next[0:0]$13782 $1\dbg_dmi_req_i$next[0:0]$13783 - attribute \src "libresoc.v:198047.5-198047.29" + assign $0\dbg_dmi_req_i$next[0:0]$13376 $1\dbg_dmi_req_i$next[0:0]$13377 + attribute \src "libresoc.v:198798.5-198798.29" switch \initial - attribute \src "libresoc.v:198047.9-198047.17" + attribute \src "libresoc.v:198798.9-198798.17" case 1'1 case end @@ -412553,21 +377178,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_req_i$next[0:0]$13783 1'0 + assign $1\dbg_dmi_req_i$next[0:0]$13377 1'0 case - assign $1\dbg_dmi_req_i$next[0:0]$13783 \jtag_dmi0__req_i + assign $1\dbg_dmi_req_i$next[0:0]$13377 \jtag_dmi0__req_i end sync always - update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13782 + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13376 end - attribute \src "libresoc.v:198055.3-198063.6" - process $proc$libresoc.v:198055$13784 + attribute \src "libresoc.v:198806.3-198814.6" + process $proc$libresoc.v:198806$13378 assign { } { } assign { } { } - assign $0\dec2_cur_eint$next[0:0]$13785 $1\dec2_cur_eint$next[0:0]$13786 - attribute \src "libresoc.v:198056.5-198056.29" + assign $0\dec2_cur_eint$next[0:0]$13379 $1\dec2_cur_eint$next[0:0]$13380 + attribute \src "libresoc.v:198807.5-198807.29" switch \initial - attribute \src "libresoc.v:198056.9-198056.17" + attribute \src "libresoc.v:198807.9-198807.17" case 1'1 case end @@ -412576,38 +377201,38 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dec2_cur_eint$next[0:0]$13786 1'0 + assign $1\dec2_cur_eint$next[0:0]$13380 1'0 case - assign $1\dec2_cur_eint$next[0:0]$13786 \xics_icp_core_irq_o + assign $1\dec2_cur_eint$next[0:0]$13380 \xics_icp_core_irq_o end sync always - update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13785 + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13379 end - attribute \src "libresoc.v:198064.3-198073.6" - process $proc$libresoc.v:198064$13787 + attribute \src "libresoc.v:198815.3-198824.6" + process $proc$libresoc.v:198815$13381 assign { } { } assign { } { } - assign $0\delay$next[1:0]$13788 $1\delay$next[1:0]$13789 - attribute \src "libresoc.v:198065.5-198065.29" + assign $0\delay$next[1:0]$13382 $1\delay$next[1:0]$13383 + attribute \src "libresoc.v:198816.5-198816.29" switch \initial - attribute \src "libresoc.v:198065.9-198065.17" + attribute \src "libresoc.v:198816.9-198816.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\delay$next[1:0]$13789 \$25 [1:0] + assign $1\delay$next[1:0]$13383 \$25 [1:0] case - assign $1\delay$next[1:0]$13789 \delay + assign $1\delay$next[1:0]$13383 \delay end sync always - update \delay$next $0\delay$next[1:0]$13788 + update \delay$next $0\delay$next[1:0]$13382 end - attribute \src "libresoc.v:198074.3-198118.6" - process $proc$libresoc.v:198074$13790 + attribute \src "libresoc.v:198825.3-198876.6" + process $proc$libresoc.v:198825$13384 assign { } { } assign { } { } assign { } { } @@ -412638,75 +377263,74 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_dststep$next[6:0]$13791 $3\core_core_dststep$next[6:0]$13821 - assign $0\core_core_maxvl$next[6:0]$13792 $3\core_core_maxvl$next[6:0]$13822 - assign $0\core_core_pc$next[63:0]$13793 $3\core_core_pc$next[63:0]$13823 - assign $0\core_core_srcstep$next[6:0]$13794 $3\core_core_srcstep$next[6:0]$13824 - assign $0\core_core_subvl$next[1:0]$13795 $3\core_core_subvl$next[1:0]$13825 - assign $0\core_core_svstep$next[1:0]$13796 $3\core_core_svstep$next[1:0]$13826 - assign $0\core_core_vl$next[6:0]$13797 $3\core_core_vl$next[6:0]$13827 - assign $0\core_dec$next[63:0]$13798 $3\core_dec$next[63:0]$13828 - assign $0\core_eint$next[0:0]$13799 $3\core_eint$next[0:0]$13829 - assign $0\core_msr$next[63:0]$13800 $3\core_msr$next[63:0]$13830 - attribute \src "libresoc.v:198075.5-198075.29" + assign $0\core_core_dststep$next[6:0]$13385 $2\core_core_dststep$next[6:0]$13405 + assign $0\core_core_maxvl$next[6:0]$13386 $2\core_core_maxvl$next[6:0]$13406 + assign $0\core_core_pc$next[63:0]$13387 $2\core_core_pc$next[63:0]$13407 + assign $0\core_core_srcstep$next[6:0]$13388 $2\core_core_srcstep$next[6:0]$13408 + assign $0\core_core_subvl$next[1:0]$13389 $2\core_core_subvl$next[1:0]$13409 + assign $0\core_core_svstep$next[1:0]$13390 $2\core_core_svstep$next[1:0]$13410 + assign $0\core_core_vl$next[6:0]$13391 $2\core_core_vl$next[6:0]$13411 + assign $0\core_dec$next[63:0]$13392 $2\core_dec$next[63:0]$13412 + assign $0\core_eint$next[0:0]$13393 $2\core_eint$next[0:0]$13413 + assign $0\core_msr$next[63:0]$13394 $2\core_msr$next[63:0]$13414 + attribute \src "libresoc.v:198826.5-198826.29" switch \initial - attribute \src "libresoc.v:198075.9-198075.17" + attribute \src "libresoc.v:198826.9-198826.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\core_core_dststep$next[6:0]$13395 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13396 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13397 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13398 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13399 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13400 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13401 \core_core_vl + assign $1\core_dec$next[63:0]$13402 \core_dec + assign $1\core_eint$next[0:0]$13403 \core_eint + assign $1\core_msr$next[63:0]$13404 \core_msr + attribute \src "libresoc.v:0.0-0.0" case 3'001 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\core_core_dststep$next[6:0]$13801 $2\core_core_dststep$next[6:0]$13811 - assign $1\core_core_maxvl$next[6:0]$13802 $2\core_core_maxvl$next[6:0]$13812 - assign $1\core_core_pc$next[63:0]$13803 $2\core_core_pc$next[63:0]$13813 - assign $1\core_core_srcstep$next[6:0]$13804 $2\core_core_srcstep$next[6:0]$13814 - assign $1\core_core_subvl$next[1:0]$13805 $2\core_core_subvl$next[1:0]$13815 - assign $1\core_core_svstep$next[1:0]$13806 $2\core_core_svstep$next[1:0]$13816 - assign $1\core_core_vl$next[6:0]$13807 $2\core_core_vl$next[6:0]$13817 - assign $1\core_dec$next[63:0]$13808 $2\core_dec$next[63:0]$13818 - assign $1\core_eint$next[0:0]$13809 $2\core_eint$next[0:0]$13819 - assign $1\core_msr$next[63:0]$13810 $2\core_msr$next[63:0]$13820 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" - switch \fetch_insn_valid_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\core_core_maxvl$next[6:0]$13812 $2\core_core_vl$next[6:0]$13817 $2\core_core_srcstep$next[6:0]$13814 $2\core_core_dststep$next[6:0]$13811 $2\core_core_subvl$next[1:0]$13815 $2\core_core_svstep$next[1:0]$13816 $2\core_dec$next[63:0]$13818 $2\core_eint$next[0:0]$13819 $2\core_msr$next[63:0]$13820 $2\core_core_pc$next[63:0]$13813 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } - case - assign $2\core_core_dststep$next[6:0]$13811 \core_core_dststep - assign $2\core_core_maxvl$next[6:0]$13812 \core_core_maxvl - assign $2\core_core_pc$next[63:0]$13813 \core_core_pc - assign $2\core_core_srcstep$next[6:0]$13814 \core_core_srcstep - assign $2\core_core_subvl$next[1:0]$13815 \core_core_subvl - assign $2\core_core_svstep$next[1:0]$13816 \core_core_svstep - assign $2\core_core_vl$next[6:0]$13817 \core_core_vl - assign $2\core_dec$next[63:0]$13818 \core_dec - assign $2\core_eint$next[0:0]$13819 \core_eint - assign $2\core_msr$next[63:0]$13820 \core_msr - end + assign $1\core_core_dststep$next[6:0]$13395 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13396 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13397 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13398 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13399 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13400 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13401 \core_core_vl + assign $1\core_dec$next[63:0]$13402 \core_dec + assign $1\core_eint$next[0:0]$13403 \core_eint + assign $1\core_msr$next[63:0]$13404 \core_msr attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 3'011 + assign $1\core_core_dststep$next[6:0]$13395 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13396 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13397 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13398 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13399 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13400 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13401 \core_core_vl + assign $1\core_dec$next[63:0]$13402 \core_dec + assign $1\core_eint$next[0:0]$13403 \core_eint + assign $1\core_msr$next[63:0]$13404 \core_msr + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_core_dststep$next[6:0]$13395 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13396 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13397 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13398 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13399 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13400 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13401 \core_core_vl + assign $1\core_dec$next[63:0]$13402 \core_dec + assign $1\core_eint$next[0:0]$13403 \core_eint + assign $1\core_msr$next[63:0]$13404 \core_msr + attribute \src "libresoc.v:0.0-0.0" + case 3'010 assign { } { } assign { } { } assign { } { } @@ -412717,18 +377341,18 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $1\core_core_maxvl$next[6:0]$13802 $1\core_core_vl$next[6:0]$13807 $1\core_core_srcstep$next[6:0]$13804 $1\core_core_dststep$next[6:0]$13801 $1\core_core_subvl$next[1:0]$13805 $1\core_core_svstep$next[1:0]$13806 $1\core_dec$next[63:0]$13808 $1\core_eint$next[0:0]$13809 $1\core_msr$next[63:0]$13810 $1\core_core_pc$next[63:0]$13803 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + assign { $1\core_core_maxvl$next[6:0]$13396 $1\core_core_vl$next[6:0]$13401 $1\core_core_srcstep$next[6:0]$13398 $1\core_core_dststep$next[6:0]$13395 $1\core_core_subvl$next[1:0]$13399 $1\core_core_svstep$next[1:0]$13400 $1\core_dec$next[63:0]$13402 $1\core_eint$next[0:0]$13403 $1\core_msr$next[63:0]$13404 $1\core_core_pc$next[63:0]$13397 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $1\core_core_dststep$next[6:0]$13801 \core_core_dststep - assign $1\core_core_maxvl$next[6:0]$13802 \core_core_maxvl - assign $1\core_core_pc$next[63:0]$13803 \core_core_pc - assign $1\core_core_srcstep$next[6:0]$13804 \core_core_srcstep - assign $1\core_core_subvl$next[1:0]$13805 \core_core_subvl - assign $1\core_core_svstep$next[1:0]$13806 \core_core_svstep - assign $1\core_core_vl$next[6:0]$13807 \core_core_vl - assign $1\core_dec$next[63:0]$13808 \core_dec - assign $1\core_eint$next[0:0]$13809 \core_eint - assign $1\core_msr$next[63:0]$13810 \core_msr + assign $1\core_core_dststep$next[6:0]$13395 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13396 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13397 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13398 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13399 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13400 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13401 \core_core_vl + assign $1\core_dec$next[63:0]$13402 \core_dec + assign $1\core_eint$next[0:0]$13403 \core_eint + assign $1\core_msr$next[63:0]$13404 \core_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -412744,304 +377368,205 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_core_pc$next[63:0]$13823 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_msr$next[63:0]$13830 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_eint$next[0:0]$13829 1'0 - assign $3\core_dec$next[63:0]$13828 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_core_svstep$next[1:0]$13826 2'00 - assign $3\core_core_subvl$next[1:0]$13825 2'00 - assign $3\core_core_dststep$next[6:0]$13821 7'0000000 - assign $3\core_core_srcstep$next[6:0]$13824 7'0000000 - assign $3\core_core_vl$next[6:0]$13827 7'0000000 - assign $3\core_core_maxvl$next[6:0]$13822 7'0000000 + assign $2\core_core_pc$next[63:0]$13407 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\core_msr$next[63:0]$13414 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\core_eint$next[0:0]$13413 1'0 + assign $2\core_dec$next[63:0]$13412 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\core_core_svstep$next[1:0]$13410 2'00 + assign $2\core_core_subvl$next[1:0]$13409 2'00 + assign $2\core_core_dststep$next[6:0]$13405 7'0000000 + assign $2\core_core_srcstep$next[6:0]$13408 7'0000000 + assign $2\core_core_vl$next[6:0]$13411 7'0000000 + assign $2\core_core_maxvl$next[6:0]$13406 7'0000000 case - assign $3\core_core_dststep$next[6:0]$13821 $1\core_core_dststep$next[6:0]$13801 - assign $3\core_core_maxvl$next[6:0]$13822 $1\core_core_maxvl$next[6:0]$13802 - assign $3\core_core_pc$next[63:0]$13823 $1\core_core_pc$next[63:0]$13803 - assign $3\core_core_srcstep$next[6:0]$13824 $1\core_core_srcstep$next[6:0]$13804 - assign $3\core_core_subvl$next[1:0]$13825 $1\core_core_subvl$next[1:0]$13805 - assign $3\core_core_svstep$next[1:0]$13826 $1\core_core_svstep$next[1:0]$13806 - assign $3\core_core_vl$next[6:0]$13827 $1\core_core_vl$next[6:0]$13807 - assign $3\core_dec$next[63:0]$13828 $1\core_dec$next[63:0]$13808 - assign $3\core_eint$next[0:0]$13829 $1\core_eint$next[0:0]$13809 - assign $3\core_msr$next[63:0]$13830 $1\core_msr$next[63:0]$13810 + assign $2\core_core_dststep$next[6:0]$13405 $1\core_core_dststep$next[6:0]$13395 + assign $2\core_core_maxvl$next[6:0]$13406 $1\core_core_maxvl$next[6:0]$13396 + assign $2\core_core_pc$next[63:0]$13407 $1\core_core_pc$next[63:0]$13397 + assign $2\core_core_srcstep$next[6:0]$13408 $1\core_core_srcstep$next[6:0]$13398 + assign $2\core_core_subvl$next[1:0]$13409 $1\core_core_subvl$next[1:0]$13399 + assign $2\core_core_svstep$next[1:0]$13410 $1\core_core_svstep$next[1:0]$13400 + assign $2\core_core_vl$next[6:0]$13411 $1\core_core_vl$next[6:0]$13401 + assign $2\core_dec$next[63:0]$13412 $1\core_dec$next[63:0]$13402 + assign $2\core_eint$next[0:0]$13413 $1\core_eint$next[0:0]$13403 + assign $2\core_msr$next[63:0]$13414 $1\core_msr$next[63:0]$13404 end sync always - update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13791 - update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13792 - update \core_core_pc$next $0\core_core_pc$next[63:0]$13793 - update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13794 - update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13795 - update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13796 - update \core_core_vl$next $0\core_core_vl$next[6:0]$13797 - update \core_dec$next $0\core_dec$next[63:0]$13798 - update \core_eint$next $0\core_eint$next[0:0]$13799 - update \core_msr$next $0\core_msr$next[63:0]$13800 + update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13385 + update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13386 + update \core_core_pc$next $0\core_core_pc$next[63:0]$13387 + update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13388 + update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13389 + update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13390 + update \core_core_vl$next $0\core_core_vl$next[6:0]$13391 + update \core_dec$next $0\core_dec$next[63:0]$13392 + update \core_eint$next $0\core_eint$next[0:0]$13393 + update \core_msr$next $0\core_msr$next[63:0]$13394 end - attribute \src "libresoc.v:198119.3-198139.6" - process $proc$libresoc.v:198119$13831 + attribute \src "libresoc.v:198877.3-198908.6" + process $proc$libresoc.v:198877$13415 assign { } { } assign { } { } assign { } { } - assign $0\core_raw_insn_i$next[31:0]$13832 $3\core_raw_insn_i$next[31:0]$13835 - attribute \src "libresoc.v:198120.5-198120.29" + assign $0\core_raw_insn_i$next[31:0]$13416 $2\core_raw_insn_i$next[31:0]$13418 + attribute \src "libresoc.v:198878.5-198878.29" switch \initial - attribute \src "libresoc.v:198120.9-198120.17" + attribute \src "libresoc.v:198878.9-198878.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\core_raw_insn_i$next[31:0]$13417 \core_raw_insn_i + attribute \src "libresoc.v:0.0-0.0" case 3'001 + assign $1\core_raw_insn_i$next[31:0]$13417 \core_raw_insn_i + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\core_raw_insn_i$next[31:0]$13417 \core_raw_insn_i + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_raw_insn_i$next[31:0]$13417 \core_raw_insn_i + attribute \src "libresoc.v:0.0-0.0" + case 3'010 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13833 $2\core_raw_insn_i$next[31:0]$13834 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" - switch \fetch_insn_valid_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_raw_insn_i$next[31:0]$13834 \dec2_raw_opcode_in - case - assign $2\core_raw_insn_i$next[31:0]$13834 \core_raw_insn_i - end + assign $1\core_raw_insn_i$next[31:0]$13417 \dec2_raw_opcode_in case - assign $1\core_raw_insn_i$next[31:0]$13833 \core_raw_insn_i + assign $1\core_raw_insn_i$next[31:0]$13417 \core_raw_insn_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_raw_insn_i$next[31:0]$13835 0 + assign $2\core_raw_insn_i$next[31:0]$13418 0 case - assign $3\core_raw_insn_i$next[31:0]$13835 $1\core_raw_insn_i$next[31:0]$13833 + assign $2\core_raw_insn_i$next[31:0]$13418 $1\core_raw_insn_i$next[31:0]$13417 end sync always - update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13832 + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13416 end - attribute \src "libresoc.v:198140.3-198164.6" - process $proc$libresoc.v:198140$13836 + attribute \src "libresoc.v:198909.3-198940.6" + process $proc$libresoc.v:198909$13419 assign { } { } assign { } { } assign { } { } - assign $0\core_bigendian_i$10$next[0:0]$13837 $3\core_bigendian_i$10$next[0:0]$13840 - attribute \src "libresoc.v:198141.5-198141.29" + assign $0\core_bigendian_i$10$next[0:0]$13420 $2\core_bigendian_i$10$next[0:0]$13422 + attribute \src "libresoc.v:198910.5-198910.29" switch \initial - attribute \src "libresoc.v:198141.9-198141.17" + attribute \src "libresoc.v:198910.9-198910.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\core_bigendian_i$10$next[0:0]$13421 \core_bigendian_i$10 + attribute \src "libresoc.v:0.0-0.0" case 3'001 - assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13838 $2\core_bigendian_i$10$next[0:0]$13839 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" - switch \fetch_insn_valid_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_bigendian_i$10$next[0:0]$13839 \core_bigendian_i - case - assign $2\core_bigendian_i$10$next[0:0]$13839 \core_bigendian_i$10 - end + assign $1\core_bigendian_i$10$next[0:0]$13421 \core_bigendian_i$10 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 3'011 + assign $1\core_bigendian_i$10$next[0:0]$13421 \core_bigendian_i$10 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_bigendian_i$10$next[0:0]$13421 \core_bigendian_i$10 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13838 \core_bigendian_i + assign $1\core_bigendian_i$10$next[0:0]$13421 \core_bigendian_i case - assign $1\core_bigendian_i$10$next[0:0]$13838 \core_bigendian_i$10 + assign $1\core_bigendian_i$10$next[0:0]$13421 \core_bigendian_i$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_bigendian_i$10$next[0:0]$13840 1'0 + assign $2\core_bigendian_i$10$next[0:0]$13422 1'0 case - assign $3\core_bigendian_i$10$next[0:0]$13840 $1\core_bigendian_i$10$next[0:0]$13838 + assign $2\core_bigendian_i$10$next[0:0]$13422 $1\core_bigendian_i$10$next[0:0]$13421 end sync always - update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13837 + update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13420 end - attribute \src "libresoc.v:198165.3-198189.6" - process $proc$libresoc.v:198165$13841 + attribute \src "libresoc.v:198941.3-198972.6" + process $proc$libresoc.v:198941$13423 assign { } { } assign { } { } assign { } { } - assign $0\core_sv_a_nz$next[0:0]$13842 $3\core_sv_a_nz$next[0:0]$13845 - attribute \src "libresoc.v:198166.5-198166.29" + assign $0\core_sv_a_nz$next[0:0]$13424 $2\core_sv_a_nz$next[0:0]$13426 + attribute \src "libresoc.v:198942.5-198942.29" switch \initial - attribute \src "libresoc.v:198166.9-198166.17" + attribute \src "libresoc.v:198942.9-198942.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\core_sv_a_nz$next[0:0]$13425 \core_sv_a_nz + attribute \src "libresoc.v:0.0-0.0" case 3'001 - assign { } { } - assign $1\core_sv_a_nz$next[0:0]$13843 $2\core_sv_a_nz$next[0:0]$13844 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" - switch \fetch_insn_valid_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_sv_a_nz$next[0:0]$13844 \dec2_sv_a_nz - case - assign $2\core_sv_a_nz$next[0:0]$13844 \core_sv_a_nz - end + assign $1\core_sv_a_nz$next[0:0]$13425 \core_sv_a_nz attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 3'011 + assign $1\core_sv_a_nz$next[0:0]$13425 \core_sv_a_nz + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_sv_a_nz$next[0:0]$13425 \core_sv_a_nz + attribute \src "libresoc.v:0.0-0.0" + case 3'010 assign { } { } - assign $1\core_sv_a_nz$next[0:0]$13843 \dec2_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13425 \dec2_sv_a_nz case - assign $1\core_sv_a_nz$next[0:0]$13843 \core_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13425 \core_sv_a_nz end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_sv_a_nz$next[0:0]$13845 1'0 + assign $2\core_sv_a_nz$next[0:0]$13426 1'0 case - assign $3\core_sv_a_nz$next[0:0]$13845 $1\core_sv_a_nz$next[0:0]$13843 + assign $2\core_sv_a_nz$next[0:0]$13426 $1\core_sv_a_nz$next[0:0]$13425 end sync always - update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13842 + update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13424 end - attribute \src "libresoc.v:198190.3-198227.6" - process $proc$libresoc.v:198190$13846 - assign { } { } + attribute \src "libresoc.v:198973.3-199003.6" + process $proc$libresoc.v:198973$13427 assign { } { } assign { } { } - assign $0\insn_done[0:0] $4\insn_done[0:0] - attribute \src "libresoc.v:198191.5-198191.29" + assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0] + attribute \src "libresoc.v:198974.5-198974.29" switch \initial - attribute \src "libresoc.v:198191.9-198191.17" + attribute \src "libresoc.v:198974.9-198974.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\insn_done[0:0] $2\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" - switch \fetch_insn_valid_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\insn_done[0:0] $3\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - switch \$234 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\insn_done[0:0] 1'1 - case - assign $3\insn_done[0:0] 1'0 - end - case - assign $2\insn_done[0:0] 1'0 - end - case - assign $1\insn_done[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" - switch \exec_fsm_state + case 3'000 + assign $1\exec_insn_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\insn_done[0:0] $5\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" - switch \$236 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\insn_done[0:0] $6\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" - switch \exec_pc_ready_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\insn_done[0:0] 1'1 - case - assign $6\insn_done[0:0] $1\insn_done[0:0] - end - case - assign $5\insn_done[0:0] $1\insn_done[0:0] - end - case - assign $4\insn_done[0:0] $1\insn_done[0:0] - end - sync always - update \insn_done $0\insn_done[0:0] - end - attribute \src "libresoc.v:198228.3-198238.6" - process $proc$libresoc.v:198228$13847 - assign { } { } - assign { } { } - assign $0\pred_insn_valid_i[0:0] $1\pred_insn_valid_i[0:0] - attribute \src "libresoc.v:198229.5-198229.29" - switch \initial - attribute \src "libresoc.v:198229.9-198229.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" - switch \issue_fsm_state + case 3'001 + assign $1\exec_insn_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 - assign { } { } - assign $1\pred_insn_valid_i[0:0] 1'1 - case - assign $1\pred_insn_valid_i[0:0] 1'0 - end - sync always - update \pred_insn_valid_i $0\pred_insn_valid_i[0:0] - end - attribute \src "libresoc.v:198239.3-198249.6" - process $proc$libresoc.v:198239$13848 - assign { } { } - assign { } { } - assign $0\pred_mask_ready_i[0:0] $1\pred_mask_ready_i[0:0] - attribute \src "libresoc.v:198240.5-198240.29" - switch \initial - attribute \src "libresoc.v:198240.9-198240.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" - switch \issue_fsm_state + assign $1\exec_insn_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'100 - assign { } { } - assign $1\pred_mask_ready_i[0:0] 1'1 - case - assign $1\pred_mask_ready_i[0:0] 1'0 - end - sync always - update \pred_mask_ready_i $0\pred_mask_ready_i[0:0] - end - attribute \src "libresoc.v:198250.3-198260.6" - process $proc$libresoc.v:198250$13849 - assign { } { } - assign { } { } - assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:198251.5-198251.29" - switch \initial - attribute \src "libresoc.v:198251.9-198251.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" - switch \issue_fsm_state + assign $1\exec_insn_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 + assign $1\exec_insn_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 assign { } { } assign $1\exec_insn_valid_i[0:0] 1'1 case @@ -413050,24 +377575,42 @@ module \ti sync always update \exec_insn_valid_i $0\exec_insn_valid_i[0:0] end - attribute \src "libresoc.v:198261.3-198276.6" - process $proc$libresoc.v:198261$13850 + attribute \src "libresoc.v:199004.3-199043.6" + process $proc$libresoc.v:199004$13428 assign { } { } assign { } { } assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:198262.5-198262.29" + attribute \src "libresoc.v:199005.5-199005.29" switch \initial - attribute \src "libresoc.v:198262.9-198262.17" + attribute \src "libresoc.v:199005.9-199005.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\exec_pc_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\exec_pc_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\exec_pc_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\exec_pc_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\exec_pc_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'101 + assign $1\exec_pc_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'110 assign { } { } assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch \$242 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413082,30 +377625,48 @@ module \ti sync always update \exec_pc_ready_i $0\exec_pc_ready_i[0:0] end - attribute \src "libresoc.v:198277.3-198297.6" - process $proc$libresoc.v:198277$13851 + attribute \src "libresoc.v:199044.3-199088.6" + process $proc$libresoc.v:199044$13429 assign { } { } assign { } { } assign $0\is_last[0:0] $1\is_last[0:0] - attribute \src "libresoc.v:198278.5-198278.29" + attribute \src "libresoc.v:199045.5-199045.29" switch \initial - attribute \src "libresoc.v:198278.9-198278.17" + attribute \src "libresoc.v:199045.9-199045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\is_last[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\is_last[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\is_last[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\is_last[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\is_last[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'101 + assign $1\is_last[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'110 assign { } { } assign $1\is_last[0:0] $2\is_last[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch \$248 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\is_last[0:0] $3\is_last[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413123,64 +377684,64 @@ module \ti sync always update \is_last $0\is_last[0:0] end - attribute \src "libresoc.v:198298.3-198307.6" - process $proc$libresoc.v:198298$13852 + attribute \src "libresoc.v:199089.3-199098.6" + process $proc$libresoc.v:199089$13430 assign { } { } assign { } { } - assign $0\core_wen$11[2:0]$13853 $1\core_wen$11[2:0]$13854 - attribute \src "libresoc.v:198299.5-198299.29" + assign $0\core_wen$11[2:0]$13431 $1\core_wen$11[2:0]$13432 + attribute \src "libresoc.v:199090.5-199090.29" switch \initial - attribute \src "libresoc.v:198299.9-198299.17" + attribute \src "libresoc.v:199090.9-199090.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_wen$11[2:0]$13854 3'100 + assign $1\core_wen$11[2:0]$13432 3'100 case - assign $1\core_wen$11[2:0]$13854 3'000 + assign $1\core_wen$11[2:0]$13432 3'000 end sync always - update \core_wen$11 $0\core_wen$11[2:0]$13853 + update \core_wen$11 $0\core_wen$11[2:0]$13431 end - attribute \src "libresoc.v:198308.3-198317.6" - process $proc$libresoc.v:198308$13855 + attribute \src "libresoc.v:199099.3-199108.6" + process $proc$libresoc.v:199099$13433 assign { } { } assign { } { } - assign $0\core_data_i$12[63:0]$13856 $1\core_data_i$12[63:0]$13857 - attribute \src "libresoc.v:198309.5-198309.29" + assign $0\core_data_i$12[63:0]$13434 $1\core_data_i$12[63:0]$13435 + attribute \src "libresoc.v:199100.5-199100.29" switch \initial - attribute \src "libresoc.v:198309.9-198309.17" + attribute \src "libresoc.v:199100.9-199100.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_data_i$12[63:0]$13857 \$252 + assign $1\core_data_i$12[63:0]$13435 \$252 case - assign $1\core_data_i$12[63:0]$13857 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_data_i$12[63:0]$13435 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \core_data_i$12 $0\core_data_i$12[63:0]$13856 + update \core_data_i$12 $0\core_data_i$12[63:0]$13434 end - attribute \src "libresoc.v:198318.3-198328.6" - process $proc$libresoc.v:198318$13858 + attribute \src "libresoc.v:199109.3-199119.6" + process $proc$libresoc.v:199109$13436 assign { } { } assign { } { } assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:198319.5-198319.29" + attribute \src "libresoc.v:199110.5-199110.29" switch \initial - attribute \src "libresoc.v:198319.9-198319.17" + attribute \src "libresoc.v:199110.9-199110.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 @@ -413192,24 +377753,24 @@ module \ti sync always update \exec_insn_ready_o $0\exec_insn_ready_o[0:0] end - attribute \src "libresoc.v:198329.3-198353.6" - process $proc$libresoc.v:198329$13859 + attribute \src "libresoc.v:199120.3-199144.6" + process $proc$libresoc.v:199120$13437 assign { } { } assign { } { } assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:198330.5-198330.29" + attribute \src "libresoc.v:199121.5-199121.29" switch \initial - attribute \src "libresoc.v:198330.9-198330.17" + attribute \src "libresoc.v:199121.9-199121.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:716" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413222,7 +377783,7 @@ module \ti case 1'1 assign { } { } assign $1\core_ivalid_i[0:0] $3\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:725" switch \$254 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413237,24 +377798,24 @@ module \ti sync always update \core_ivalid_i $0\core_ivalid_i[0:0] end - attribute \src "libresoc.v:198354.3-198369.6" - process $proc$libresoc.v:198354$13860 + attribute \src "libresoc.v:199145.3-199160.6" + process $proc$libresoc.v:199145$13438 assign { } { } assign { } { } assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] - attribute \src "libresoc.v:198355.5-198355.29" + attribute \src "libresoc.v:199146.5-199146.29" switch \initial - attribute \src "libresoc.v:198355.9-198355.17" + attribute \src "libresoc.v:199146.9-199146.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\core_issue_i[0:0] $2\core_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:716" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413269,88 +377830,91 @@ module \ti sync always update \core_issue_i $0\core_issue_i[0:0] end - attribute \src "libresoc.v:198370.3-198404.6" - process $proc$libresoc.v:198370$13861 + attribute \src "libresoc.v:199161.3-199195.6" + process $proc$libresoc.v:199161$13439 assign { } { } assign { } { } assign { } { } - assign $0\exec_fsm_state$next[0:0]$13862 $5\exec_fsm_state$next[0:0]$13867 - attribute \src "libresoc.v:198371.5-198371.29" + assign $0\exec_fsm_state$next[0:0]$13440 $5\exec_fsm_state$next[0:0]$13445 + attribute \src "libresoc.v:199162.5-199162.29" switch \initial - attribute \src "libresoc.v:198371.9-198371.17" + attribute \src "libresoc.v:199162.9-199162.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $1\exec_fsm_state$next[0:0]$13863 $2\exec_fsm_state$next[0:0]$13864 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + assign $1\exec_fsm_state$next[0:0]$13441 $2\exec_fsm_state$next[0:0]$13442 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:716" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\exec_fsm_state$next[0:0]$13864 1'1 + assign $2\exec_fsm_state$next[0:0]$13442 1'1 case - assign $2\exec_fsm_state$next[0:0]$13864 \exec_fsm_state + assign $2\exec_fsm_state$next[0:0]$13442 \exec_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\exec_fsm_state$next[0:0]$13863 $3\exec_fsm_state$next[0:0]$13865 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + assign $1\exec_fsm_state$next[0:0]$13441 $3\exec_fsm_state$next[0:0]$13443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" switch \$256 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\exec_fsm_state$next[0:0]$13865 $4\exec_fsm_state$next[0:0]$13866 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" + assign $3\exec_fsm_state$next[0:0]$13443 $4\exec_fsm_state$next[0:0]$13444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" switch \exec_pc_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\exec_fsm_state$next[0:0]$13866 1'0 + assign $4\exec_fsm_state$next[0:0]$13444 1'0 case - assign $4\exec_fsm_state$next[0:0]$13866 \exec_fsm_state + assign $4\exec_fsm_state$next[0:0]$13444 \exec_fsm_state end case - assign $3\exec_fsm_state$next[0:0]$13865 \exec_fsm_state + assign $3\exec_fsm_state$next[0:0]$13443 \exec_fsm_state end case - assign $1\exec_fsm_state$next[0:0]$13863 \exec_fsm_state + assign $1\exec_fsm_state$next[0:0]$13441 \exec_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\exec_fsm_state$next[0:0]$13867 1'0 + assign $5\exec_fsm_state$next[0:0]$13445 1'0 case - assign $5\exec_fsm_state$next[0:0]$13867 $1\exec_fsm_state$next[0:0]$13863 + assign $5\exec_fsm_state$next[0:0]$13445 $1\exec_fsm_state$next[0:0]$13441 end sync always - update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13862 + update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13440 end - attribute \src "libresoc.v:198405.3-198420.6" - process $proc$libresoc.v:198405$13868 + attribute \src "libresoc.v:199196.3-199215.6" + process $proc$libresoc.v:199196$13446 assign { } { } assign { } { } assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:198406.5-198406.29" + attribute \src "libresoc.v:199197.5-199197.29" switch \initial - attribute \src "libresoc.v:198406.9-198406.17" + attribute \src "libresoc.v:199197.9-199197.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign $1\exec_pc_valid_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" switch \$258 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413365,18 +377929,18 @@ module \ti sync always update \exec_pc_valid_o $0\exec_pc_valid_o[0:0] end - attribute \src "libresoc.v:198421.3-198430.6" - process $proc$libresoc.v:198421$13869 + attribute \src "libresoc.v:199216.3-199225.6" + process $proc$libresoc.v:199216$13447 assign { } { } assign { } { } assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:198422.5-198422.29" + attribute \src "libresoc.v:199217.5-199217.29" switch \initial - attribute \src "libresoc.v:198422.9-198422.17" + attribute \src "libresoc.v:199217.9-199217.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:940" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413388,18 +377952,18 @@ module \ti sync always update \core_dmi__addr $0\core_dmi__addr[4:0] end - attribute \src "libresoc.v:198431.3-198440.6" - process $proc$libresoc.v:198431$13870 + attribute \src "libresoc.v:199226.3-199235.6" + process $proc$libresoc.v:199226$13448 assign { } { } assign { } { } assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:198432.5-198432.29" + attribute \src "libresoc.v:199227.5-199227.29" switch \initial - attribute \src "libresoc.v:198432.9-198432.17" + attribute \src "libresoc.v:199227.9-199227.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:940" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413411,14 +377975,14 @@ module \ti sync always update \core_dmi__ren $0\core_dmi__ren[0:0] end - attribute \src "libresoc.v:198441.3-198449.6" - process $proc$libresoc.v:198441$13871 + attribute \src "libresoc.v:199236.3-199244.6" + process $proc$libresoc.v:199236$13449 assign { } { } assign { } { } - assign $0\d_reg_delay$next[0:0]$13872 $1\d_reg_delay$next[0:0]$13873 - attribute \src "libresoc.v:198442.5-198442.29" + assign $0\d_reg_delay$next[0:0]$13450 $1\d_reg_delay$next[0:0]$13451 + attribute \src "libresoc.v:199237.5-199237.29" switch \initial - attribute \src "libresoc.v:198442.9-198442.17" + attribute \src "libresoc.v:199237.9-199237.17" case 1'1 case end @@ -413427,25 +377991,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_reg_delay$next[0:0]$13873 1'0 + assign $1\d_reg_delay$next[0:0]$13451 1'0 case - assign $1\d_reg_delay$next[0:0]$13873 \dbg_d_gpr_req + assign $1\d_reg_delay$next[0:0]$13451 \dbg_d_gpr_req end sync always - update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13872 + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13450 end - attribute \src "libresoc.v:198450.3-198459.6" - process $proc$libresoc.v:198450$13874 + attribute \src "libresoc.v:199245.3-199254.6" + process $proc$libresoc.v:199245$13452 assign { } { } assign { } { } assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:198451.5-198451.29" + attribute \src "libresoc.v:199246.5-199246.29" switch \initial - attribute \src "libresoc.v:198451.9-198451.17" + attribute \src "libresoc.v:199246.9-199246.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:950" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413457,18 +378021,18 @@ module \ti sync always update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] end - attribute \src "libresoc.v:198460.3-198469.6" - process $proc$libresoc.v:198460$13875 + attribute \src "libresoc.v:199255.3-199264.6" + process $proc$libresoc.v:199255$13453 assign { } { } assign { } { } assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:198461.5-198461.29" + attribute \src "libresoc.v:199256.5-199256.29" switch \initial - attribute \src "libresoc.v:198461.9-198461.17" + attribute \src "libresoc.v:199256.9-199256.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:950" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413480,18 +378044,18 @@ module \ti sync always update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] end - attribute \src "libresoc.v:198470.3-198479.6" - process $proc$libresoc.v:198470$13876 + attribute \src "libresoc.v:199265.3-199274.6" + process $proc$libresoc.v:199265$13454 assign { } { } assign { } { } assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:198471.5-198471.29" + attribute \src "libresoc.v:199266.5-199266.29" switch \initial - attribute \src "libresoc.v:198471.9-198471.17" + attribute \src "libresoc.v:199266.9-199266.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:954" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:956" switch \dbg_d_cr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413503,14 +378067,14 @@ module \ti sync always update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] end - attribute \src "libresoc.v:198480.3-198488.6" - process $proc$libresoc.v:198480$13877 + attribute \src "libresoc.v:199275.3-199283.6" + process $proc$libresoc.v:199275$13455 assign { } { } assign { } { } - assign $0\d_cr_delay$next[0:0]$13878 $1\d_cr_delay$next[0:0]$13879 - attribute \src "libresoc.v:198481.5-198481.29" + assign $0\d_cr_delay$next[0:0]$13456 $1\d_cr_delay$next[0:0]$13457 + attribute \src "libresoc.v:199276.5-199276.29" switch \initial - attribute \src "libresoc.v:198481.9-198481.17" + attribute \src "libresoc.v:199276.9-199276.17" case 1'1 case end @@ -413519,25 +378083,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_cr_delay$next[0:0]$13879 1'0 + assign $1\d_cr_delay$next[0:0]$13457 1'0 case - assign $1\d_cr_delay$next[0:0]$13879 \dbg_d_cr_req + assign $1\d_cr_delay$next[0:0]$13457 \dbg_d_cr_req end sync always - update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13878 + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13456 end - attribute \src "libresoc.v:198489.3-198498.6" - process $proc$libresoc.v:198489$13880 + attribute \src "libresoc.v:199284.3-199293.6" + process $proc$libresoc.v:199284$13458 assign { } { } assign { } { } assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:198490.5-198490.29" + attribute \src "libresoc.v:199285.5-199285.29" switch \initial - attribute \src "libresoc.v:198490.9-198490.17" + attribute \src "libresoc.v:199285.9-199285.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:960" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413549,18 +378113,18 @@ module \ti sync always update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] end - attribute \src "libresoc.v:198499.3-198508.6" - process $proc$libresoc.v:198499$13881 + attribute \src "libresoc.v:199294.3-199303.6" + process $proc$libresoc.v:199294$13459 assign { } { } assign { } { } assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:198500.5-198500.29" + attribute \src "libresoc.v:199295.5-199295.29" switch \initial - attribute \src "libresoc.v:198500.9-198500.17" + attribute \src "libresoc.v:199295.9-199295.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:960" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413572,18 +378136,18 @@ module \ti sync always update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] end - attribute \src "libresoc.v:198509.3-198518.6" - process $proc$libresoc.v:198509$13882 + attribute \src "libresoc.v:199304.3-199313.6" + process $proc$libresoc.v:199304$13460 assign { } { } assign { } { } assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:198510.5-198510.29" + attribute \src "libresoc.v:199305.5-199305.29" switch \initial - attribute \src "libresoc.v:198510.9-198510.17" + attribute \src "libresoc.v:199305.9-199305.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:964" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:966" switch \dbg_d_xer_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413595,14 +378159,14 @@ module \ti sync always update \core_full_rd__ren $0\core_full_rd__ren[2:0] end - attribute \src "libresoc.v:198519.3-198527.6" - process $proc$libresoc.v:198519$13883 + attribute \src "libresoc.v:199314.3-199322.6" + process $proc$libresoc.v:199314$13461 assign { } { } assign { } { } - assign $0\d_xer_delay$next[0:0]$13884 $1\d_xer_delay$next[0:0]$13885 - attribute \src "libresoc.v:198520.5-198520.29" + assign $0\d_xer_delay$next[0:0]$13462 $1\d_xer_delay$next[0:0]$13463 + attribute \src "libresoc.v:199315.5-199315.29" switch \initial - attribute \src "libresoc.v:198520.9-198520.17" + attribute \src "libresoc.v:199315.9-199315.17" case 1'1 case end @@ -413611,25 +378175,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_xer_delay$next[0:0]$13885 1'0 + assign $1\d_xer_delay$next[0:0]$13463 1'0 case - assign $1\d_xer_delay$next[0:0]$13885 \dbg_d_xer_req + assign $1\d_xer_delay$next[0:0]$13463 \dbg_d_xer_req end sync always - update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13884 + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13462 end - attribute \src "libresoc.v:198528.3-198537.6" - process $proc$libresoc.v:198528$13886 + attribute \src "libresoc.v:199323.3-199332.6" + process $proc$libresoc.v:199323$13464 assign { } { } assign { } { } assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:198529.5-198529.29" + attribute \src "libresoc.v:199324.5-199324.29" switch \initial - attribute \src "libresoc.v:198529.9-198529.17" + attribute \src "libresoc.v:199324.9-199324.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:968" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:970" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413641,18 +378205,18 @@ module \ti sync always update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] end - attribute \src "libresoc.v:198538.3-198547.6" - process $proc$libresoc.v:198538$13887 + attribute \src "libresoc.v:199333.3-199342.6" + process $proc$libresoc.v:199333$13465 assign { } { } assign { } { } assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:198539.5-198539.29" + attribute \src "libresoc.v:199334.5-199334.29" switch \initial - attribute \src "libresoc.v:198539.9-198539.17" + attribute \src "libresoc.v:199334.9-199334.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:968" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:970" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -413664,24 +378228,27 @@ module \ti sync always update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] end - attribute \src "libresoc.v:198548.3-198562.6" - process $proc$libresoc.v:198548$13888 + attribute \src "libresoc.v:199343.3-199361.6" + process $proc$libresoc.v:199343$13466 assign { } { } assign { } { } assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] - attribute \src "libresoc.v:198549.5-198549.29" + attribute \src "libresoc.v:199344.5-199344.29" switch \initial - attribute \src "libresoc.v:198549.9-198549.17" + attribute \src "libresoc.v:199344.9-199344.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:991" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_issue__addr[2:0] 3'110 attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\core_issue__addr[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\core_issue__addr[2:0] 3'111 @@ -413691,24 +378258,27 @@ module \ti sync always update \core_issue__addr $0\core_issue__addr[2:0] end - attribute \src "libresoc.v:198563.3-198577.6" - process $proc$libresoc.v:198563$13889 + attribute \src "libresoc.v:199362.3-199380.6" + process $proc$libresoc.v:199362$13467 assign { } { } assign { } { } assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] - attribute \src "libresoc.v:198564.5-198564.29" + attribute \src "libresoc.v:199363.5-199363.29" switch \initial - attribute \src "libresoc.v:198564.9-198564.17" + attribute \src "libresoc.v:199363.9-199363.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:991" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_issue__ren[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\core_issue__ren[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\core_issue__ren[0:0] 1'1 @@ -413718,65 +378288,68 @@ module \ti sync always update \core_issue__ren $0\core_issue__ren[0:0] end - attribute \src "libresoc.v:198578.3-198605.6" - process $proc$libresoc.v:198578$13890 + attribute \src "libresoc.v:199381.3-199408.6" + process $proc$libresoc.v:199381$13468 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$13891 $2\fsm_state$next[1:0]$13893 - attribute \src "libresoc.v:198579.5-198579.29" + assign $0\fsm_state$next[1:0]$13469 $2\fsm_state$next[1:0]$13471 + attribute \src "libresoc.v:199382.5-199382.29" switch \initial - attribute \src "libresoc.v:198579.9-198579.17" + attribute \src "libresoc.v:199382.9-199382.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:991" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$13892 2'01 + assign $1\fsm_state$next[1:0]$13470 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$13892 2'10 + assign $1\fsm_state$next[1:0]$13470 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$13892 2'11 + assign $1\fsm_state$next[1:0]$13470 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fsm_state$next[1:0]$13892 2'00 + assign $1\fsm_state$next[1:0]$13470 2'00 case - assign $1\fsm_state$next[1:0]$13892 \fsm_state + assign $1\fsm_state$next[1:0]$13470 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$13893 2'00 + assign $2\fsm_state$next[1:0]$13471 2'00 case - assign $2\fsm_state$next[1:0]$13893 $1\fsm_state$next[1:0]$13892 + assign $2\fsm_state$next[1:0]$13471 $1\fsm_state$next[1:0]$13470 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$13891 + update \fsm_state$next $0\fsm_state$next[1:0]$13469 end - attribute \src "libresoc.v:198606.3-198616.6" - process $proc$libresoc.v:198606$13894 + attribute \src "libresoc.v:199409.3-199423.6" + process $proc$libresoc.v:199409$13472 assign { } { } assign { } { } assign $0\new_dec[63:0] $1\new_dec[63:0] - attribute \src "libresoc.v:198607.5-198607.29" + attribute \src "libresoc.v:199410.5-199410.29" switch \initial - attribute \src "libresoc.v:198607.9-198607.17" + attribute \src "libresoc.v:199410.9-199410.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:991" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\new_dec[63:0] \$264 [63:0] @@ -413786,51 +378359,63 @@ module \ti sync always update \new_dec $0\new_dec[63:0] end - attribute \src "libresoc.v:198617.3-198631.6" - process $proc$libresoc.v:198617$13895 + attribute \src "libresoc.v:199424.3-199446.6" + process $proc$libresoc.v:199424$13473 assign { } { } assign { } { } - assign $0\core_issue__addr$13[2:0]$13896 $1\core_issue__addr$13[2:0]$13897 - attribute \src "libresoc.v:198618.5-198618.29" + assign $0\core_issue__addr$13[2:0]$13474 $1\core_issue__addr$13[2:0]$13475 + attribute \src "libresoc.v:199425.5-199425.29" switch \initial - attribute \src "libresoc.v:198618.9-198618.17" + attribute \src "libresoc.v:199425.9-199425.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:991" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\core_issue__addr$13[2:0]$13475 3'000 + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\core_issue__addr$13[2:0]$13897 3'110 + assign $1\core_issue__addr$13[2:0]$13475 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign $1\core_issue__addr$13[2:0]$13475 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\core_issue__addr$13[2:0]$13897 3'111 + assign $1\core_issue__addr$13[2:0]$13475 3'111 case - assign $1\core_issue__addr$13[2:0]$13897 3'000 + assign $1\core_issue__addr$13[2:0]$13475 3'000 end sync always - update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13896 + update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13474 end - attribute \src "libresoc.v:198632.3-198646.6" - process $proc$libresoc.v:198632$13898 + attribute \src "libresoc.v:199447.3-199469.6" + process $proc$libresoc.v:199447$13476 assign { } { } assign { } { } assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] - attribute \src "libresoc.v:198633.5-198633.29" + attribute \src "libresoc.v:199448.5-199448.29" switch \initial - attribute \src "libresoc.v:198633.9-198633.17" + attribute \src "libresoc.v:199448.9-199448.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:991" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\core_issue__wen[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\core_issue__wen[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign $1\core_issue__wen[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\core_issue__wen[0:0] 1'1 @@ -413840,24 +378425,30 @@ module \ti sync always update \core_issue__wen $0\core_issue__wen[0:0] end - attribute \src "libresoc.v:198647.3-198661.6" - process $proc$libresoc.v:198647$13899 + attribute \src "libresoc.v:199470.3-199492.6" + process $proc$libresoc.v:199470$13477 assign { } { } assign { } { } assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:198648.5-198648.29" + attribute \src "libresoc.v:199471.5-199471.29" switch \initial - attribute \src "libresoc.v:198648.9-198648.17" + attribute \src "libresoc.v:199471.9-199471.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:991" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\core_issue__data_i[63:0] \new_dec attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\core_issue__data_i[63:0] \new_tb @@ -413867,53 +378458,65 @@ module \ti sync always update \core_issue__data_i $0\core_issue__data_i[63:0] end - attribute \src "libresoc.v:198662.3-198677.6" - process $proc$libresoc.v:198662$13900 + attribute \src "libresoc.v:199493.3-199512.6" + process $proc$libresoc.v:199493$13478 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_dec$next[63:0]$13901 $2\dec2_cur_dec$next[63:0]$13903 - attribute \src "libresoc.v:198663.5-198663.29" + assign $0\dec2_cur_dec$next[63:0]$13479 $2\dec2_cur_dec$next[63:0]$13481 + attribute \src "libresoc.v:199494.5-199494.29" switch \initial - attribute \src "libresoc.v:198663.9-198663.17" + attribute \src "libresoc.v:199494.9-199494.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:991" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\dec2_cur_dec$next[63:0]$13480 \dec2_cur_dec + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_dec$next[63:0]$13902 \new_dec + assign $1\dec2_cur_dec$next[63:0]$13480 \new_dec case - assign $1\dec2_cur_dec$next[63:0]$13902 \dec2_cur_dec + assign $1\dec2_cur_dec$next[63:0]$13480 \dec2_cur_dec end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_dec$next[63:0]$13903 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dec2_cur_dec$next[63:0]$13481 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\dec2_cur_dec$next[63:0]$13903 $1\dec2_cur_dec$next[63:0]$13902 + assign $2\dec2_cur_dec$next[63:0]$13481 $1\dec2_cur_dec$next[63:0]$13480 end sync always - update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13901 + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13479 end - attribute \src "libresoc.v:198678.3-198688.6" - process $proc$libresoc.v:198678$13904 + attribute \src "libresoc.v:199513.3-199535.6" + process $proc$libresoc.v:199513$13482 assign { } { } assign { } { } assign $0\new_tb[63:0] $1\new_tb[63:0] - attribute \src "libresoc.v:198679.5-198679.29" + attribute \src "libresoc.v:199514.5-199514.29" switch \initial - attribute \src "libresoc.v:198679.9-198679.17" + attribute \src "libresoc.v:199514.9-199514.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:991" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\new_tb[63:0] \$267 [63:0] @@ -413923,14 +378526,14 @@ module \ti sync always update \new_tb $0\new_tb[63:0] end - attribute \src "libresoc.v:198689.3-198697.6" - process $proc$libresoc.v:198689$13905 + attribute \src "libresoc.v:199536.3-199544.6" + process $proc$libresoc.v:199536$13483 assign { } { } assign { } { } - assign $0\dbg_dmi_we_i$next[0:0]$13906 $1\dbg_dmi_we_i$next[0:0]$13907 - attribute \src "libresoc.v:198690.5-198690.29" + assign $0\dbg_dmi_we_i$next[0:0]$13484 $1\dbg_dmi_we_i$next[0:0]$13485 + attribute \src "libresoc.v:199537.5-199537.29" switch \initial - attribute \src "libresoc.v:198690.9-198690.17" + attribute \src "libresoc.v:199537.9-199537.17" case 1'1 case end @@ -413939,21 +378542,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_we_i$next[0:0]$13907 1'0 + assign $1\dbg_dmi_we_i$next[0:0]$13485 1'0 case - assign $1\dbg_dmi_we_i$next[0:0]$13907 \jtag_dmi0__we_i + assign $1\dbg_dmi_we_i$next[0:0]$13485 \jtag_dmi0__we_i end sync always - update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13906 + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13484 end - attribute \src "libresoc.v:198698.3-198706.6" - process $proc$libresoc.v:198698$13908 + attribute \src "libresoc.v:199545.3-199553.6" + process $proc$libresoc.v:199545$13486 assign { } { } assign { } { } - assign $0\pc_ok_delay$next[0:0]$13909 $1\pc_ok_delay$next[0:0]$13910 - attribute \src "libresoc.v:198699.5-198699.29" + assign $0\pc_ok_delay$next[0:0]$13487 $1\pc_ok_delay$next[0:0]$13488 + attribute \src "libresoc.v:199546.5-199546.29" switch \initial - attribute \src "libresoc.v:198699.9-198699.17" + attribute \src "libresoc.v:199546.9-199546.17" case 1'1 case end @@ -413962,22 +378565,22 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\pc_ok_delay$next[0:0]$13910 1'0 + assign $1\pc_ok_delay$next[0:0]$13488 1'0 case - assign $1\pc_ok_delay$next[0:0]$13910 \$38 + assign $1\pc_ok_delay$next[0:0]$13488 \$38 end sync always - update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13909 + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13487 end - attribute \src "libresoc.v:198707.3-198722.6" - process $proc$libresoc.v:198707$13911 + attribute \src "libresoc.v:199554.3-199569.6" + process $proc$libresoc.v:199554$13489 assign { } { } assign { } { } assign { } { } assign $0\pc[63:0] $2\pc[63:0] - attribute \src "libresoc.v:198708.5-198708.29" + attribute \src "libresoc.v:199555.5-199555.29" switch \initial - attribute \src "libresoc.v:198708.9-198708.17" + attribute \src "libresoc.v:199555.9-199555.17" case 1'1 case end @@ -414002,14 +378605,14 @@ module \ti sync always update \pc $0\pc[63:0] end - attribute \src "libresoc.v:198723.3-198735.6" - process $proc$libresoc.v:198723$13912 + attribute \src "libresoc.v:199570.3-199582.6" + process $proc$libresoc.v:199570$13490 assign { } { } assign { } { } assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0] - attribute \src "libresoc.v:198724.5-198724.29" + attribute \src "libresoc.v:199571.5-199571.29" switch \initial - attribute \src "libresoc.v:198724.9-198724.17" + attribute \src "libresoc.v:199571.9-199571.17" case 1'1 case end @@ -414026,14 +378629,14 @@ module \ti sync always update \core_cia__ren $0\core_cia__ren[2:0] end - attribute \src "libresoc.v:198736.3-198744.6" - process $proc$libresoc.v:198736$13913 + attribute \src "libresoc.v:199583.3-199591.6" + process $proc$libresoc.v:199583$13491 assign { } { } assign { } { } - assign $0\svstate_ok_delay$next[0:0]$13914 $1\svstate_ok_delay$next[0:0]$13915 - attribute \src "libresoc.v:198737.5-198737.29" + assign $0\svstate_ok_delay$next[0:0]$13492 $1\svstate_ok_delay$next[0:0]$13493 + attribute \src "libresoc.v:199584.5-199584.29" switch \initial - attribute \src "libresoc.v:198737.9-198737.17" + attribute \src "libresoc.v:199584.9-199584.17" case 1'1 case end @@ -414042,22 +378645,22 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\svstate_ok_delay$next[0:0]$13915 1'0 + assign $1\svstate_ok_delay$next[0:0]$13493 1'0 case - assign $1\svstate_ok_delay$next[0:0]$13915 \$40 + assign $1\svstate_ok_delay$next[0:0]$13493 \$40 end sync always - update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13914 + update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13492 end - attribute \src "libresoc.v:198745.3-198760.6" - process $proc$libresoc.v:198745$13916 + attribute \src "libresoc.v:199592.3-199607.6" + process $proc$libresoc.v:199592$13494 assign { } { } assign { } { } assign { } { } assign $0\svstate[63:0] $2\svstate[63:0] - attribute \src "libresoc.v:198746.5-198746.29" + attribute \src "libresoc.v:199593.5-199593.29" switch \initial - attribute \src "libresoc.v:198746.9-198746.17" + attribute \src "libresoc.v:199593.9-199593.17" case 1'1 case end @@ -414082,14 +378685,14 @@ module \ti sync always update \svstate $0\svstate[63:0] end - attribute \src "libresoc.v:198761.3-198773.6" - process $proc$libresoc.v:198761$13917 + attribute \src "libresoc.v:199608.3-199620.6" + process $proc$libresoc.v:199608$13495 assign { } { } assign { } { } assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0] - attribute \src "libresoc.v:198762.5-198762.29" + attribute \src "libresoc.v:199609.5-199609.29" switch \initial - attribute \src "libresoc.v:198762.9-198762.17" + attribute \src "libresoc.v:199609.9-199609.17" case 1'1 case end @@ -414106,14 +378709,14 @@ module \ti sync always update \core_sv__ren $0\core_sv__ren[2:0] end - attribute \src "libresoc.v:198774.3-198782.6" - process $proc$libresoc.v:198774$13918 + attribute \src "libresoc.v:199621.3-199629.6" + process $proc$libresoc.v:199621$13496 assign { } { } assign { } { } - assign $0\dbg_dmi_din$next[63:0]$13919 $1\dbg_dmi_din$next[63:0]$13920 - attribute \src "libresoc.v:198775.5-198775.29" + assign $0\dbg_dmi_din$next[63:0]$13497 $1\dbg_dmi_din$next[63:0]$13498 + attribute \src "libresoc.v:199622.5-199622.29" switch \initial - attribute \src "libresoc.v:198775.9-198775.17" + attribute \src "libresoc.v:199622.9-199622.17" case 1'1 case end @@ -414122,31 +378725,31 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_din$next[63:0]$13920 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dbg_dmi_din$next[63:0]$13498 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\dbg_dmi_din$next[63:0]$13920 \jtag_dmi0__din + assign $1\dbg_dmi_din$next[63:0]$13498 \jtag_dmi0__din end sync always - update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13919 + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13497 end - attribute \src "libresoc.v:198783.3-198850.6" - process $proc$libresoc.v:198783$13921 + attribute \src "libresoc.v:199630.3-199713.6" + process $proc$libresoc.v:199630$13499 assign { } { } assign { } { } assign $0\core_wen[2:0] $1\core_wen[2:0] - attribute \src "libresoc.v:198784.5-198784.29" + attribute \src "libresoc.v:199631.5-199631.29" switch \initial - attribute \src "libresoc.v:198784.9-198784.17" + attribute \src "libresoc.v:199631.9-199631.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_wen[2:0] $2\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414155,7 +378758,7 @@ module \ti case assign { } { } assign $2\core_wen[2:0] $3\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:535" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414169,13 +378772,13 @@ module \ti case 3'001 assign { } { } assign $1\core_wen[2:0] $4\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\core_wen[2:0] $5\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414188,22 +378791,34 @@ module \ti assign $4\core_wen[2:0] 3'000 end attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\core_wen[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_wen[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\core_wen[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 3'101 + assign $1\core_wen[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'110 assign { } { } assign $1\core_wen[2:0] $6\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch \$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\core_wen[2:0] $7\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\core_wen[2:0] $8\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" switch { \$64 \$60 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -414222,7 +378837,7 @@ module \ti case assign { } { } assign $6\core_wen[2:0] $9\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:675" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414238,24 +378853,24 @@ module \ti sync always update \core_wen $0\core_wen[2:0] end - attribute \src "libresoc.v:198851.3-198918.6" - process $proc$libresoc.v:198851$13922 + attribute \src "libresoc.v:199714.3-199797.6" + process $proc$libresoc.v:199714$13500 assign { } { } assign { } { } assign $0\core_data_i[63:0] $1\core_data_i[63:0] - attribute \src "libresoc.v:198852.5-198852.29" + attribute \src "libresoc.v:199715.5-199715.29" switch \initial - attribute \src "libresoc.v:198852.9-198852.17" + attribute \src "libresoc.v:199715.9-199715.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_data_i[63:0] $2\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414264,7 +378879,7 @@ module \ti case assign { } { } assign $2\core_data_i[63:0] $3\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:535" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414278,13 +378893,13 @@ module \ti case 3'001 assign { } { } assign $1\core_data_i[63:0] $4\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\core_data_i[63:0] $5\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" switch \$74 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414297,22 +378912,34 @@ module \ti assign $4\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 3'101 + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'110 assign { } { } assign $1\core_data_i[63:0] $6\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch \$80 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\core_data_i[63:0] $7\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\core_data_i[63:0] $8\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" switch { \$86 \$82 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -414331,7 +378958,7 @@ module \ti case assign { } { } assign $6\core_data_i[63:0] $9\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:675" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414347,24 +378974,24 @@ module \ti sync always update \core_data_i $0\core_data_i[63:0] end - attribute \src "libresoc.v:198919.3-198934.6" - process $proc$libresoc.v:198919$13923 + attribute \src "libresoc.v:199798.3-199813.6" + process $proc$libresoc.v:199798$13501 assign { } { } assign { } { } assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0] - attribute \src "libresoc.v:198920.5-198920.29" + attribute \src "libresoc.v:199799.5-199799.29" switch \initial - attribute \src "libresoc.v:198920.9-198920.17" + attribute \src "libresoc.v:199799.9-199799.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_msr__ren[2:0] $2\core_msr__ren[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414379,14 +379006,14 @@ module \ti sync always update \core_msr__ren $0\core_msr__ren[2:0] end - attribute \src "libresoc.v:198935.3-198943.6" - process $proc$libresoc.v:198935$13924 + attribute \src "libresoc.v:199814.3-199822.6" + process $proc$libresoc.v:199814$13502 assign { } { } assign { } { } - assign $0\jtag_dmi0__ack_o$next[0:0]$13925 $1\jtag_dmi0__ack_o$next[0:0]$13926 - attribute \src "libresoc.v:198936.5-198936.29" + assign $0\jtag_dmi0__ack_o$next[0:0]$13503 $1\jtag_dmi0__ack_o$next[0:0]$13504 + attribute \src "libresoc.v:199815.5-199815.29" switch \initial - attribute \src "libresoc.v:198936.9-198936.17" + attribute \src "libresoc.v:199815.9-199815.17" case 1'1 case end @@ -414395,25 +379022,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_dmi0__ack_o$next[0:0]$13926 1'0 + assign $1\jtag_dmi0__ack_o$next[0:0]$13504 1'0 case - assign $1\jtag_dmi0__ack_o$next[0:0]$13926 \dbg_dmi_ack_o + assign $1\jtag_dmi0__ack_o$next[0:0]$13504 \dbg_dmi_ack_o end sync always - update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13925 + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13503 end - attribute \src "libresoc.v:198944.3-198954.6" - process $proc$libresoc.v:198944$13927 + attribute \src "libresoc.v:199823.3-199833.6" + process $proc$libresoc.v:199823$13505 assign { } { } assign { } { } assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:198945.5-198945.29" + attribute \src "libresoc.v:199824.5-199824.29" switch \initial - attribute \src "libresoc.v:198945.9-198945.17" + attribute \src "libresoc.v:199824.9-199824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -414425,24 +379052,24 @@ module \ti sync always update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0] end - attribute \src "libresoc.v:198955.3-198970.6" - process $proc$libresoc.v:198955$13928 + attribute \src "libresoc.v:199834.3-199849.6" + process $proc$libresoc.v:199834$13506 assign { } { } assign { } { } assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:198956.5-198956.29" + attribute \src "libresoc.v:199835.5-199835.29" switch \initial - attribute \src "libresoc.v:198956.9-198956.17" + attribute \src "libresoc.v:199835.9-199835.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414457,24 +379084,24 @@ module \ti sync always update \imem_a_pc_i $0\imem_a_pc_i[47:0] end - attribute \src "libresoc.v:198971.3-199004.6" - process $proc$libresoc.v:198971$13929 + attribute \src "libresoc.v:199850.3-199883.6" + process $proc$libresoc.v:199850$13507 assign { } { } assign { } { } assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:198972.5-198972.29" + attribute \src "libresoc.v:199851.5-199851.29" switch \initial - attribute \src "libresoc.v:198972.9-198972.17" + attribute \src "libresoc.v:199851.9-199851.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414487,7 +379114,7 @@ module \ti case 2'01 assign { } { } assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414500,7 +379127,7 @@ module \ti case 2'11 assign { } { } assign $1\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414515,24 +379142,24 @@ module \ti sync always update \imem_a_valid_i $0\imem_a_valid_i[0:0] end - attribute \src "libresoc.v:199005.3-199038.6" - process $proc$libresoc.v:199005$13930 + attribute \src "libresoc.v:199884.3-199917.6" + process $proc$libresoc.v:199884$13508 assign { } { } assign { } { } assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:199006.5-199006.29" + attribute \src "libresoc.v:199885.5-199885.29" switch \initial - attribute \src "libresoc.v:199006.9-199006.17" + attribute \src "libresoc.v:199885.9-199885.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414545,7 +379172,7 @@ module \ti case 2'01 assign { } { } assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414558,7 +379185,7 @@ module \ti case 2'11 assign { } { } assign $1\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414573,50 +379200,50 @@ module \ti sync always update \imem_f_valid_i $0\imem_f_valid_i[0:0] end - attribute \src "libresoc.v:199039.3-199059.6" - process $proc$libresoc.v:199039$13931 + attribute \src "libresoc.v:199918.3-199938.6" + process $proc$libresoc.v:199918$13509 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_pc$next[63:0]$13932 $3\dec2_cur_pc$next[63:0]$13935 - attribute \src "libresoc.v:199040.5-199040.29" + assign $0\dec2_cur_pc$next[63:0]$13510 $3\dec2_cur_pc$next[63:0]$13513 + attribute \src "libresoc.v:199919.5-199919.29" switch \initial - attribute \src "libresoc.v:199040.9-199040.17" + attribute \src "libresoc.v:199919.9-199919.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec2_cur_pc$next[63:0]$13933 $2\dec2_cur_pc$next[63:0]$13934 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + assign $1\dec2_cur_pc$next[63:0]$13511 $2\dec2_cur_pc$next[63:0]$13512 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_pc$next[63:0]$13934 \pc + assign $2\dec2_cur_pc$next[63:0]$13512 \pc case - assign $2\dec2_cur_pc$next[63:0]$13934 \dec2_cur_pc + assign $2\dec2_cur_pc$next[63:0]$13512 \dec2_cur_pc end case - assign $1\dec2_cur_pc$next[63:0]$13933 \dec2_cur_pc + assign $1\dec2_cur_pc$next[63:0]$13511 \dec2_cur_pc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_pc$next[63:0]$13935 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_pc$next[63:0]$13513 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_pc$next[63:0]$13935 $1\dec2_cur_pc$next[63:0]$13933 + assign $3\dec2_cur_pc$next[63:0]$13513 $1\dec2_cur_pc$next[63:0]$13511 end sync always - update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13932 + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13510 end - attribute \src "libresoc.v:199060.3-199098.6" - process $proc$libresoc.v:199060$13936 + attribute \src "libresoc.v:199939.3-199977.6" + process $proc$libresoc.v:199939$13514 assign { } { } assign { } { } assign { } { } @@ -414641,19 +379268,19 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\cur_cur_dststep$next[6:0]$13937 $4\cur_cur_dststep$next[6:0]$13961 - assign $0\cur_cur_maxvl$next[6:0]$13938 $4\cur_cur_maxvl$next[6:0]$13962 - assign $0\cur_cur_srcstep$next[6:0]$13939 $4\cur_cur_srcstep$next[6:0]$13963 - assign $0\cur_cur_subvl$next[1:0]$13940 $4\cur_cur_subvl$next[1:0]$13964 - assign $0\cur_cur_svstep$next[1:0]$13941 $4\cur_cur_svstep$next[1:0]$13965 - assign $0\cur_cur_vl$next[6:0]$13942 $4\cur_cur_vl$next[6:0]$13966 - attribute \src "libresoc.v:199061.5-199061.29" + assign $0\cur_cur_dststep$next[6:0]$13515 $4\cur_cur_dststep$next[6:0]$13539 + assign $0\cur_cur_maxvl$next[6:0]$13516 $4\cur_cur_maxvl$next[6:0]$13540 + assign $0\cur_cur_srcstep$next[6:0]$13517 $4\cur_cur_srcstep$next[6:0]$13541 + assign $0\cur_cur_subvl$next[1:0]$13518 $4\cur_cur_subvl$next[1:0]$13542 + assign $0\cur_cur_svstep$next[1:0]$13519 $4\cur_cur_svstep$next[1:0]$13543 + assign $0\cur_cur_vl$next[6:0]$13520 $4\cur_cur_vl$next[6:0]$13544 + attribute \src "libresoc.v:199940.5-199940.29" switch \initial - attribute \src "libresoc.v:199061.9-199061.17" + attribute \src "libresoc.v:199940.9-199940.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -414663,13 +379290,13 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\cur_cur_dststep$next[6:0]$13943 $2\cur_cur_dststep$next[6:0]$13949 - assign $1\cur_cur_maxvl$next[6:0]$13944 $2\cur_cur_maxvl$next[6:0]$13950 - assign $1\cur_cur_srcstep$next[6:0]$13945 $2\cur_cur_srcstep$next[6:0]$13951 - assign $1\cur_cur_subvl$next[1:0]$13946 $2\cur_cur_subvl$next[1:0]$13952 - assign $1\cur_cur_svstep$next[1:0]$13947 $2\cur_cur_svstep$next[1:0]$13953 - assign $1\cur_cur_vl$next[6:0]$13948 $2\cur_cur_vl$next[6:0]$13954 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + assign $1\cur_cur_dststep$next[6:0]$13521 $2\cur_cur_dststep$next[6:0]$13527 + assign $1\cur_cur_maxvl$next[6:0]$13522 $2\cur_cur_maxvl$next[6:0]$13528 + assign $1\cur_cur_srcstep$next[6:0]$13523 $2\cur_cur_srcstep$next[6:0]$13529 + assign $1\cur_cur_subvl$next[1:0]$13524 $2\cur_cur_subvl$next[1:0]$13530 + assign $1\cur_cur_svstep$next[1:0]$13525 $2\cur_cur_svstep$next[1:0]$13531 + assign $1\cur_cur_vl$next[6:0]$13526 $2\cur_cur_vl$next[6:0]$13532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414679,24 +379306,24 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\cur_cur_maxvl$next[6:0]$13950 $2\cur_cur_vl$next[6:0]$13954 $2\cur_cur_srcstep$next[6:0]$13951 $2\cur_cur_dststep$next[6:0]$13949 $2\cur_cur_subvl$next[1:0]$13952 $2\cur_cur_svstep$next[1:0]$13953 } \svstate [31:0] + assign { $2\cur_cur_maxvl$next[6:0]$13528 $2\cur_cur_vl$next[6:0]$13532 $2\cur_cur_srcstep$next[6:0]$13529 $2\cur_cur_dststep$next[6:0]$13527 $2\cur_cur_subvl$next[1:0]$13530 $2\cur_cur_svstep$next[1:0]$13531 } \svstate [31:0] case - assign $2\cur_cur_dststep$next[6:0]$13949 \cur_cur_dststep - assign $2\cur_cur_maxvl$next[6:0]$13950 \cur_cur_maxvl - assign $2\cur_cur_srcstep$next[6:0]$13951 \cur_cur_srcstep - assign $2\cur_cur_subvl$next[1:0]$13952 \cur_cur_subvl - assign $2\cur_cur_svstep$next[1:0]$13953 \cur_cur_svstep - assign $2\cur_cur_vl$next[6:0]$13954 \cur_cur_vl + assign $2\cur_cur_dststep$next[6:0]$13527 \cur_cur_dststep + assign $2\cur_cur_maxvl$next[6:0]$13528 \cur_cur_maxvl + assign $2\cur_cur_srcstep$next[6:0]$13529 \cur_cur_srcstep + assign $2\cur_cur_subvl$next[1:0]$13530 \cur_cur_subvl + assign $2\cur_cur_svstep$next[1:0]$13531 \cur_cur_svstep + assign $2\cur_cur_vl$next[6:0]$13532 \cur_cur_vl end case - assign $1\cur_cur_dststep$next[6:0]$13943 \cur_cur_dststep - assign $1\cur_cur_maxvl$next[6:0]$13944 \cur_cur_maxvl - assign $1\cur_cur_srcstep$next[6:0]$13945 \cur_cur_srcstep - assign $1\cur_cur_subvl$next[1:0]$13946 \cur_cur_subvl - assign $1\cur_cur_svstep$next[1:0]$13947 \cur_cur_svstep - assign $1\cur_cur_vl$next[6:0]$13948 \cur_cur_vl + assign $1\cur_cur_dststep$next[6:0]$13521 \cur_cur_dststep + assign $1\cur_cur_maxvl$next[6:0]$13522 \cur_cur_maxvl + assign $1\cur_cur_srcstep$next[6:0]$13523 \cur_cur_srcstep + assign $1\cur_cur_subvl$next[1:0]$13524 \cur_cur_subvl + assign $1\cur_cur_svstep$next[1:0]$13525 \cur_cur_svstep + assign $1\cur_cur_vl$next[6:0]$13526 \cur_cur_vl end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -414706,14 +379333,14 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $3\cur_cur_maxvl$next[6:0]$13956 $3\cur_cur_vl$next[6:0]$13960 $3\cur_cur_srcstep$next[6:0]$13957 $3\cur_cur_dststep$next[6:0]$13955 $3\cur_cur_subvl$next[1:0]$13958 $3\cur_cur_svstep$next[1:0]$13959 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } + assign { $3\cur_cur_maxvl$next[6:0]$13534 $3\cur_cur_vl$next[6:0]$13538 $3\cur_cur_srcstep$next[6:0]$13535 $3\cur_cur_dststep$next[6:0]$13533 $3\cur_cur_subvl$next[1:0]$13536 $3\cur_cur_svstep$next[1:0]$13537 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } case - assign $3\cur_cur_dststep$next[6:0]$13955 $1\cur_cur_dststep$next[6:0]$13943 - assign $3\cur_cur_maxvl$next[6:0]$13956 $1\cur_cur_maxvl$next[6:0]$13944 - assign $3\cur_cur_srcstep$next[6:0]$13957 $1\cur_cur_srcstep$next[6:0]$13945 - assign $3\cur_cur_subvl$next[1:0]$13958 $1\cur_cur_subvl$next[1:0]$13946 - assign $3\cur_cur_svstep$next[1:0]$13959 $1\cur_cur_svstep$next[1:0]$13947 - assign $3\cur_cur_vl$next[6:0]$13960 $1\cur_cur_vl$next[6:0]$13948 + assign $3\cur_cur_dststep$next[6:0]$13533 $1\cur_cur_dststep$next[6:0]$13521 + assign $3\cur_cur_maxvl$next[6:0]$13534 $1\cur_cur_maxvl$next[6:0]$13522 + assign $3\cur_cur_srcstep$next[6:0]$13535 $1\cur_cur_srcstep$next[6:0]$13523 + assign $3\cur_cur_subvl$next[1:0]$13536 $1\cur_cur_subvl$next[1:0]$13524 + assign $3\cur_cur_svstep$next[1:0]$13537 $1\cur_cur_svstep$next[1:0]$13525 + assign $3\cur_cur_vl$next[6:0]$13538 $1\cur_cur_vl$next[6:0]$13526 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -414725,36 +379352,36 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $4\cur_cur_svstep$next[1:0]$13965 2'00 - assign $4\cur_cur_subvl$next[1:0]$13964 2'00 - assign $4\cur_cur_dststep$next[6:0]$13961 7'0000000 - assign $4\cur_cur_srcstep$next[6:0]$13963 7'0000000 - assign $4\cur_cur_vl$next[6:0]$13966 7'0000000 - assign $4\cur_cur_maxvl$next[6:0]$13962 7'0000000 + assign $4\cur_cur_svstep$next[1:0]$13543 2'00 + assign $4\cur_cur_subvl$next[1:0]$13542 2'00 + assign $4\cur_cur_dststep$next[6:0]$13539 7'0000000 + assign $4\cur_cur_srcstep$next[6:0]$13541 7'0000000 + assign $4\cur_cur_vl$next[6:0]$13544 7'0000000 + assign $4\cur_cur_maxvl$next[6:0]$13540 7'0000000 case - assign $4\cur_cur_dststep$next[6:0]$13961 $3\cur_cur_dststep$next[6:0]$13955 - assign $4\cur_cur_maxvl$next[6:0]$13962 $3\cur_cur_maxvl$next[6:0]$13956 - assign $4\cur_cur_srcstep$next[6:0]$13963 $3\cur_cur_srcstep$next[6:0]$13957 - assign $4\cur_cur_subvl$next[1:0]$13964 $3\cur_cur_subvl$next[1:0]$13958 - assign $4\cur_cur_svstep$next[1:0]$13965 $3\cur_cur_svstep$next[1:0]$13959 - assign $4\cur_cur_vl$next[6:0]$13966 $3\cur_cur_vl$next[6:0]$13960 + assign $4\cur_cur_dststep$next[6:0]$13539 $3\cur_cur_dststep$next[6:0]$13533 + assign $4\cur_cur_maxvl$next[6:0]$13540 $3\cur_cur_maxvl$next[6:0]$13534 + assign $4\cur_cur_srcstep$next[6:0]$13541 $3\cur_cur_srcstep$next[6:0]$13535 + assign $4\cur_cur_subvl$next[1:0]$13542 $3\cur_cur_subvl$next[1:0]$13536 + assign $4\cur_cur_svstep$next[1:0]$13543 $3\cur_cur_svstep$next[1:0]$13537 + assign $4\cur_cur_vl$next[6:0]$13544 $3\cur_cur_vl$next[6:0]$13538 end sync always - update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13937 - update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13938 - update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13939 - update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13940 - update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13941 - update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13942 + update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13515 + update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13516 + update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13517 + update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13518 + update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13519 + update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13520 end - attribute \src "libresoc.v:199099.3-199107.6" - process $proc$libresoc.v:199099$13967 + attribute \src "libresoc.v:199978.3-199986.6" + process $proc$libresoc.v:199978$13545 assign { } { } assign { } { } - assign $0\jtag_dmi0__dout$next[63:0]$13968 $1\jtag_dmi0__dout$next[63:0]$13969 - attribute \src "libresoc.v:199100.5-199100.29" + assign $0\jtag_dmi0__dout$next[63:0]$13546 $1\jtag_dmi0__dout$next[63:0]$13547 + attribute \src "libresoc.v:199979.5-199979.29" switch \initial - attribute \src "libresoc.v:199100.9-199100.17" + attribute \src "libresoc.v:199979.9-199979.17" case 1'1 case end @@ -414763,287 +379390,305 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_dmi0__dout$next[63:0]$13969 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_dmi0__dout$next[63:0]$13547 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\jtag_dmi0__dout$next[63:0]$13969 \dbg_dmi_dout + assign $1\jtag_dmi0__dout$next[63:0]$13547 \dbg_dmi_dout end sync always - update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13968 + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13546 end - attribute \src "libresoc.v:199108.3-199137.6" - process $proc$libresoc.v:199108$13970 + attribute \src "libresoc.v:199987.3-200016.6" + process $proc$libresoc.v:199987$13548 assign { } { } assign { } { } assign { } { } - assign $0\msr_read$next[0:0]$13971 $4\msr_read$next[0:0]$13975 - attribute \src "libresoc.v:199109.5-199109.29" + assign $0\msr_read$next[0:0]$13549 $4\msr_read$next[0:0]$13553 + attribute \src "libresoc.v:199988.5-199988.29" switch \initial - attribute \src "libresoc.v:199109.9-199109.17" + attribute \src "libresoc.v:199988.9-199988.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\msr_read$next[0:0]$13972 $2\msr_read$next[0:0]$13973 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + assign $1\msr_read$next[0:0]$13550 $2\msr_read$next[0:0]$13551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_read$next[0:0]$13973 1'0 + assign $2\msr_read$next[0:0]$13551 1'0 case - assign $2\msr_read$next[0:0]$13973 \msr_read + assign $2\msr_read$next[0:0]$13551 \msr_read end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\msr_read$next[0:0]$13972 $3\msr_read$next[0:0]$13974 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" + assign $1\msr_read$next[0:0]$13550 $3\msr_read$next[0:0]$13552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" switch \$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr_read$next[0:0]$13974 1'1 + assign $3\msr_read$next[0:0]$13552 1'1 case - assign $3\msr_read$next[0:0]$13974 \msr_read + assign $3\msr_read$next[0:0]$13552 \msr_read end case - assign $1\msr_read$next[0:0]$13972 \msr_read + assign $1\msr_read$next[0:0]$13550 \msr_read end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr_read$next[0:0]$13975 1'1 + assign $4\msr_read$next[0:0]$13553 1'1 case - assign $4\msr_read$next[0:0]$13975 $1\msr_read$next[0:0]$13972 + assign $4\msr_read$next[0:0]$13553 $1\msr_read$next[0:0]$13550 end sync always - update \msr_read$next $0\msr_read$next[0:0]$13971 + update \msr_read$next $0\msr_read$next[0:0]$13549 end - attribute \src "libresoc.v:199138.3-199191.6" - process $proc$libresoc.v:199138$13976 + attribute \src "libresoc.v:200017.3-200070.6" + process $proc$libresoc.v:200017$13554 assign { } { } assign { } { } assign { } { } - assign $0\fetch_fsm_state$next[1:0]$13977 $6\fetch_fsm_state$next[1:0]$13983 - attribute \src "libresoc.v:199139.5-199139.29" + assign $0\fetch_fsm_state$next[1:0]$13555 $6\fetch_fsm_state$next[1:0]$13561 + attribute \src "libresoc.v:200018.5-200018.29" switch \initial - attribute \src "libresoc.v:199139.9-199139.17" + attribute \src "libresoc.v:200018.9-200018.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13978 $2\fetch_fsm_state$next[1:0]$13979 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" + assign $1\fetch_fsm_state$next[1:0]$13556 $2\fetch_fsm_state$next[1:0]$13557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fetch_fsm_state$next[1:0]$13979 2'01 + assign $2\fetch_fsm_state$next[1:0]$13557 2'01 case - assign $2\fetch_fsm_state$next[1:0]$13979 \fetch_fsm_state + assign $2\fetch_fsm_state$next[1:0]$13557 \fetch_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13978 $3\fetch_fsm_state$next[1:0]$13980 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + assign $1\fetch_fsm_state$next[1:0]$13556 $3\fetch_fsm_state$next[1:0]$13558 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\fetch_fsm_state$next[1:0]$13980 \fetch_fsm_state + assign $3\fetch_fsm_state$next[1:0]$13558 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\fetch_fsm_state$next[1:0]$13980 2'10 + assign $3\fetch_fsm_state$next[1:0]$13558 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13978 $4\fetch_fsm_state$next[1:0]$13981 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" + assign $1\fetch_fsm_state$next[1:0]$13556 $4\fetch_fsm_state$next[1:0]$13559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\fetch_fsm_state$next[1:0]$13981 \fetch_fsm_state + assign $4\fetch_fsm_state$next[1:0]$13559 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\fetch_fsm_state$next[1:0]$13981 2'10 + assign $4\fetch_fsm_state$next[1:0]$13559 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13978 $5\fetch_fsm_state$next[1:0]$13982 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:371" + assign $1\fetch_fsm_state$next[1:0]$13556 $5\fetch_fsm_state$next[1:0]$13560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:377" switch \fetch_insn_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fetch_fsm_state$next[1:0]$13982 2'00 + assign $5\fetch_fsm_state$next[1:0]$13560 2'00 case - assign $5\fetch_fsm_state$next[1:0]$13982 \fetch_fsm_state + assign $5\fetch_fsm_state$next[1:0]$13560 \fetch_fsm_state end case - assign $1\fetch_fsm_state$next[1:0]$13978 \fetch_fsm_state + assign $1\fetch_fsm_state$next[1:0]$13556 \fetch_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fetch_fsm_state$next[1:0]$13983 2'00 + assign $6\fetch_fsm_state$next[1:0]$13561 2'00 case - assign $6\fetch_fsm_state$next[1:0]$13983 $1\fetch_fsm_state$next[1:0]$13978 + assign $6\fetch_fsm_state$next[1:0]$13561 $1\fetch_fsm_state$next[1:0]$13556 end sync always - update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13977 + update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13555 end - attribute \src "libresoc.v:199192.3-199212.6" - process $proc$libresoc.v:199192$13984 + attribute \src "libresoc.v:200071.3-200095.6" + process $proc$libresoc.v:200071$13562 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_msr$next[63:0]$13985 $3\dec2_cur_msr$next[63:0]$13988 - attribute \src "libresoc.v:199193.5-199193.29" + assign $0\dec2_cur_msr$next[63:0]$13563 $3\dec2_cur_msr$next[63:0]$13566 + attribute \src "libresoc.v:200072.5-200072.29" switch \initial - attribute \src "libresoc.v:199193.9-199193.17" + attribute \src "libresoc.v:200072.9-200072.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\dec2_cur_msr$next[63:0]$13564 \dec2_cur_msr + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_msr$next[63:0]$13986 $2\dec2_cur_msr$next[63:0]$13987 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" + assign $1\dec2_cur_msr$next[63:0]$13564 $2\dec2_cur_msr$next[63:0]$13565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" switch \$90 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_msr$next[63:0]$13987 \core_msr__data_o + assign $2\dec2_cur_msr$next[63:0]$13565 \core_msr__data_o case - assign $2\dec2_cur_msr$next[63:0]$13987 \dec2_cur_msr + assign $2\dec2_cur_msr$next[63:0]$13565 \dec2_cur_msr end case - assign $1\dec2_cur_msr$next[63:0]$13986 \dec2_cur_msr + assign $1\dec2_cur_msr$next[63:0]$13564 \dec2_cur_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_msr$next[63:0]$13988 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_msr$next[63:0]$13566 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_msr$next[63:0]$13988 $1\dec2_cur_msr$next[63:0]$13986 + assign $3\dec2_cur_msr$next[63:0]$13566 $1\dec2_cur_msr$next[63:0]$13564 end sync always - update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13985 + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13563 end - attribute \src "libresoc.v:199213.3-199231.6" - process $proc$libresoc.v:199213$13989 + attribute \src "libresoc.v:200096.3-200118.6" + process $proc$libresoc.v:200096$13567 assign { } { } assign { } { } - assign $0\nia$next[63:0]$13990 $1\nia$next[63:0]$13991 - attribute \src "libresoc.v:199214.5-199214.29" + assign $0\nia$next[63:0]$13568 $1\nia$next[63:0]$13569 + attribute \src "libresoc.v:200097.5-200097.29" switch \initial - attribute \src "libresoc.v:199214.9-199214.17" + attribute \src "libresoc.v:200097.9-200097.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\nia$next[63:0]$13569 \nia + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\nia$next[63:0]$13991 $2\nia$next[63:0]$13992 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + assign $1\nia$next[63:0]$13569 $2\nia$next[63:0]$13570 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\nia$next[63:0]$13992 \nia + assign $2\nia$next[63:0]$13570 \nia attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\nia$next[63:0]$13992 \$92 [63:0] + assign $2\nia$next[63:0]$13570 \$92 [63:0] end case - assign $1\nia$next[63:0]$13991 \nia + assign $1\nia$next[63:0]$13569 \nia end sync always - update \nia$next $0\nia$next[63:0]$13990 + update \nia$next $0\nia$next[63:0]$13568 end - attribute \src "libresoc.v:199232.3-199262.6" - process $proc$libresoc.v:199232$13993 + attribute \src "libresoc.v:200119.3-200153.6" + process $proc$libresoc.v:200119$13571 assign { } { } assign { } { } - assign $0\dec2_raw_opcode_in$next[31:0]$13994 $1\dec2_raw_opcode_in$next[31:0]$13995 - attribute \src "libresoc.v:199233.5-199233.29" + assign $0\dec2_raw_opcode_in$next[31:0]$13572 $1\dec2_raw_opcode_in$next[31:0]$13573 + attribute \src "libresoc.v:200120.5-200120.29" switch \initial - attribute \src "libresoc.v:199233.9-199233.17" + attribute \src "libresoc.v:200120.9-200120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\dec2_raw_opcode_in$next[31:0]$13573 \dec2_raw_opcode_in + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_raw_opcode_in$next[31:0]$13995 $2\dec2_raw_opcode_in$next[31:0]$13996 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + assign $1\dec2_raw_opcode_in$next[31:0]$13573 $2\dec2_raw_opcode_in$next[31:0]$13574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\dec2_raw_opcode_in$next[31:0]$13996 \dec2_raw_opcode_in + assign $2\dec2_raw_opcode_in$next[31:0]$13574 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dec2_raw_opcode_in$next[31:0]$13996 \$95 + assign $2\dec2_raw_opcode_in$next[31:0]$13574 \$95 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\dec2_raw_opcode_in$next[31:0]$13995 $3\dec2_raw_opcode_in$next[31:0]$13997 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" + assign $1\dec2_raw_opcode_in$next[31:0]$13573 $3\dec2_raw_opcode_in$next[31:0]$13575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\dec2_raw_opcode_in$next[31:0]$13997 \dec2_raw_opcode_in + assign $3\dec2_raw_opcode_in$next[31:0]$13575 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\dec2_raw_opcode_in$next[31:0]$13997 \$99 + assign $3\dec2_raw_opcode_in$next[31:0]$13575 \$99 end case - assign $1\dec2_raw_opcode_in$next[31:0]$13995 \dec2_raw_opcode_in + assign $1\dec2_raw_opcode_in$next[31:0]$13573 \dec2_raw_opcode_in end sync always - update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13994 + update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13572 end - attribute \src "libresoc.v:199263.3-199273.6" - process $proc$libresoc.v:199263$13998 + attribute \src "libresoc.v:200154.3-200176.6" + process $proc$libresoc.v:200154$13576 assign { } { } assign { } { } assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:199264.5-199264.29" + attribute \src "libresoc.v:200155.5-200155.29" switch \initial - attribute \src "libresoc.v:199264.9-199264.17" + attribute \src "libresoc.v:200155.9-200155.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\fetch_insn_valid_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\fetch_insn_valid_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign $1\fetch_insn_valid_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\fetch_insn_valid_o[0:0] 1'1 @@ -415053,8 +379698,8 @@ module \ti sync always update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0] end - attribute \src "libresoc.v:199274.3-199333.6" - process $proc$libresoc.v:199274$13999 + attribute \src "libresoc.v:200177.3-200258.6" + process $proc$libresoc.v:200177$13577 assign { } { } assign { } { } assign { } { } @@ -415068,13 +379713,13 @@ module \ti assign $0\new_svstate_subvl[1:0] $1\new_svstate_subvl[1:0] assign $0\new_svstate_svstep[1:0] $1\new_svstate_svstep[1:0] assign $0\new_svstate_vl[6:0] $1\new_svstate_vl[6:0] - attribute \src "libresoc.v:199275.5-199275.29" + attribute \src "libresoc.v:200178.5-200178.29" switch \initial - attribute \src "libresoc.v:199275.9-199275.17" + attribute \src "libresoc.v:200178.9-200178.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 @@ -415090,7 +379735,7 @@ module \ti assign $1\new_svstate_subvl[1:0] $2\new_svstate_subvl[1:0] assign $1\new_svstate_svstep[1:0] $2\new_svstate_svstep[1:0] assign $1\new_svstate_vl[6:0] $2\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \$110 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -415114,7 +379759,7 @@ module \ti assign $2\new_svstate_subvl[1:0] $3\new_svstate_subvl[1:0] assign $2\new_svstate_svstep[1:0] $3\new_svstate_svstep[1:0] assign $2\new_svstate_vl[6:0] $3\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -415135,7 +379780,47 @@ module \ti end end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\new_svstate_dststep[6:0] \cur_cur_dststep + assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $1\new_svstate_subvl[1:0] \cur_cur_subvl + assign $1\new_svstate_svstep[1:0] \cur_cur_svstep + assign $1\new_svstate_vl[6:0] \cur_cur_vl + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\new_svstate_dststep[6:0] \cur_cur_dststep + assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $1\new_svstate_subvl[1:0] \cur_cur_subvl + assign $1\new_svstate_svstep[1:0] \cur_cur_svstep + assign $1\new_svstate_vl[6:0] \cur_cur_vl + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\new_svstate_dststep[6:0] \cur_cur_dststep + assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $1\new_svstate_subvl[1:0] \cur_cur_subvl + assign $1\new_svstate_svstep[1:0] \cur_cur_svstep + assign $1\new_svstate_vl[6:0] \cur_cur_vl + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\new_svstate_dststep[6:0] \cur_cur_dststep + assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $1\new_svstate_subvl[1:0] \cur_cur_subvl + assign $1\new_svstate_svstep[1:0] \cur_cur_svstep + assign $1\new_svstate_vl[6:0] \cur_cur_vl + attribute \src "libresoc.v:0.0-0.0" case 3'101 + assign $1\new_svstate_dststep[6:0] \cur_cur_dststep + assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $1\new_svstate_subvl[1:0] \cur_cur_subvl + assign $1\new_svstate_svstep[1:0] \cur_cur_svstep + assign $1\new_svstate_vl[6:0] \cur_cur_vl + attribute \src "libresoc.v:0.0-0.0" + case 3'110 assign { } { } assign { } { } assign { } { } @@ -415148,7 +379833,7 @@ module \ti assign $1\new_svstate_subvl[1:0] $4\new_svstate_subvl[1:0] assign $1\new_svstate_svstep[1:0] $4\new_svstate_svstep[1:0] assign $1\new_svstate_vl[6:0] $4\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch \$116 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -415160,7 +379845,7 @@ module \ti assign $4\new_svstate_vl[6:0] \cur_cur_vl assign $4\new_svstate_dststep[6:0] $5\new_svstate_dststep[6:0] assign $4\new_svstate_srcstep[6:0] $5\new_svstate_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -415168,7 +379853,7 @@ module \ti assign { } { } assign $5\new_svstate_dststep[6:0] $6\new_svstate_dststep[6:0] assign $5\new_svstate_srcstep[6:0] $6\new_svstate_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" switch { \$122 \$118 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -415178,6 +379863,10 @@ module \ti case 2'1- assign $6\new_svstate_dststep[6:0] \cur_cur_dststep assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" + switch 1'0 + case + end attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -415203,7 +379892,7 @@ module \ti assign $4\new_svstate_subvl[1:0] $5\new_svstate_subvl[1:0] assign $4\new_svstate_svstep[1:0] $5\new_svstate_svstep[1:0] assign $4\new_svstate_vl[6:0] $5\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:679" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -415239,24 +379928,24 @@ module \ti update \new_svstate_svstep $0\new_svstate_svstep[1:0] update \new_svstate_vl $0\new_svstate_vl[6:0] end - attribute \src "libresoc.v:199334.3-199349.6" - process $proc$libresoc.v:199334$14000 + attribute \src "libresoc.v:200259.3-200274.6" + process $proc$libresoc.v:200259$13578 assign { } { } assign { } { } assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:199335.5-199335.29" + attribute \src "libresoc.v:200260.5-200260.29" switch \initial - attribute \src "libresoc.v:199335.9-199335.17" + attribute \src "libresoc.v:200260.9-200260.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\fetch_pc_valid_i[0:0] $2\fetch_pc_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -415271,179 +379960,179 @@ module \ti sync always update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0] end - attribute \src "libresoc.v:199350.3-199448.6" - process $proc$libresoc.v:199350$14001 + attribute \src "libresoc.v:200275.3-200373.6" + process $proc$libresoc.v:200275$13579 assign { } { } assign { } { } assign { } { } - assign $0\issue_fsm_state$next[2:0]$14002 $12\issue_fsm_state$next[2:0]$14014 - attribute \src "libresoc.v:199351.5-199351.29" + assign $0\issue_fsm_state$next[2:0]$13580 $12\issue_fsm_state$next[2:0]$13592 + attribute \src "libresoc.v:200276.5-200276.29" switch \initial - attribute \src "libresoc.v:199351.9-199351.17" + attribute \src "libresoc.v:200276.9-200276.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\issue_fsm_state$next[2:0]$14003 $2\issue_fsm_state$next[2:0]$14004 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + assign $1\issue_fsm_state$next[2:0]$13581 $2\issue_fsm_state$next[2:0]$13582 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \$140 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\issue_fsm_state$next[2:0]$14004 $3\issue_fsm_state$next[2:0]$14005 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" + assign $2\issue_fsm_state$next[2:0]$13582 $3\issue_fsm_state$next[2:0]$13583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:528" switch \fetch_pc_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\issue_fsm_state$next[2:0]$14005 3'001 + assign $3\issue_fsm_state$next[2:0]$13583 3'001 case - assign $3\issue_fsm_state$next[2:0]$14005 \issue_fsm_state + assign $3\issue_fsm_state$next[2:0]$13583 \issue_fsm_state end case - assign $2\issue_fsm_state$next[2:0]$14004 \issue_fsm_state + assign $2\issue_fsm_state$next[2:0]$13582 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\issue_fsm_state$next[2:0]$14003 $4\issue_fsm_state$next[2:0]$14006 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" + assign $1\issue_fsm_state$next[2:0]$13581 $4\issue_fsm_state$next[2:0]$13584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\issue_fsm_state$next[2:0]$14006 $5\issue_fsm_state$next[2:0]$14007 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + assign $4\issue_fsm_state$next[2:0]$13584 $5\issue_fsm_state$next[2:0]$13585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" switch \$144 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\issue_fsm_state$next[2:0]$14007 3'000 + assign $5\issue_fsm_state$next[2:0]$13585 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $5\issue_fsm_state$next[2:0]$14007 3'010 + assign $5\issue_fsm_state$next[2:0]$13585 3'010 end case - assign $4\issue_fsm_state$next[2:0]$14006 \issue_fsm_state + assign $4\issue_fsm_state$next[2:0]$13584 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\issue_fsm_state$next[2:0]$14003 $6\issue_fsm_state$next[2:0]$14008 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" + assign $1\issue_fsm_state$next[2:0]$13581 $6\issue_fsm_state$next[2:0]$13586 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" switch \pred_insn_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\issue_fsm_state$next[2:0]$14008 3'100 + assign $6\issue_fsm_state$next[2:0]$13586 3'100 case - assign $6\issue_fsm_state$next[2:0]$14008 \issue_fsm_state + assign $6\issue_fsm_state$next[2:0]$13586 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\issue_fsm_state$next[2:0]$14003 $7\issue_fsm_state$next[2:0]$14009 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" + assign $1\issue_fsm_state$next[2:0]$13581 $7\issue_fsm_state$next[2:0]$13587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" switch \pred_mask_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\issue_fsm_state$next[2:0]$14009 3'010 + assign $7\issue_fsm_state$next[2:0]$13587 3'010 case - assign $7\issue_fsm_state$next[2:0]$14009 \issue_fsm_state + assign $7\issue_fsm_state$next[2:0]$13587 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\issue_fsm_state$next[2:0]$14003 $8\issue_fsm_state$next[2:0]$14010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" + assign $1\issue_fsm_state$next[2:0]$13581 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$13581 $8\issue_fsm_state$next[2:0]$13588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" switch \exec_insn_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\issue_fsm_state$next[2:0]$14010 3'101 + assign $8\issue_fsm_state$next[2:0]$13588 3'110 case - assign $8\issue_fsm_state$next[2:0]$14010 \issue_fsm_state + assign $8\issue_fsm_state$next[2:0]$13588 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 3'110 assign { } { } - assign $1\issue_fsm_state$next[2:0]$14003 $9\issue_fsm_state$next[2:0]$14011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + assign $1\issue_fsm_state$next[2:0]$13581 $9\issue_fsm_state$next[2:0]$13589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch \$150 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\issue_fsm_state$next[2:0]$14011 $10\issue_fsm_state$next[2:0]$14012 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + assign $9\issue_fsm_state$next[2:0]$13589 $10\issue_fsm_state$next[2:0]$13590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\issue_fsm_state$next[2:0]$14012 $11\issue_fsm_state$next[2:0]$14013 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + assign $10\issue_fsm_state$next[2:0]$13590 $11\issue_fsm_state$next[2:0]$13591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" switch { \$156 \$152 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $11\issue_fsm_state$next[2:0]$14013 3'000 + assign $11\issue_fsm_state$next[2:0]$13591 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $11\issue_fsm_state$next[2:0]$14013 3'000 + assign $11\issue_fsm_state$next[2:0]$13591 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $11\issue_fsm_state$next[2:0]$14013 3'110 + assign $11\issue_fsm_state$next[2:0]$13591 3'010 end case - assign $10\issue_fsm_state$next[2:0]$14012 \issue_fsm_state + assign $10\issue_fsm_state$next[2:0]$13590 \issue_fsm_state end case - assign $9\issue_fsm_state$next[2:0]$14011 \issue_fsm_state + assign $9\issue_fsm_state$next[2:0]$13589 \issue_fsm_state end - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\issue_fsm_state$next[2:0]$14003 3'010 case - assign $1\issue_fsm_state$next[2:0]$14003 \issue_fsm_state + assign $1\issue_fsm_state$next[2:0]$13581 \issue_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $12\issue_fsm_state$next[2:0]$14014 3'000 + assign $12\issue_fsm_state$next[2:0]$13592 3'000 case - assign $12\issue_fsm_state$next[2:0]$14014 $1\issue_fsm_state$next[2:0]$14003 + assign $12\issue_fsm_state$next[2:0]$13592 $1\issue_fsm_state$next[2:0]$13581 end sync always - update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$14002 + update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13580 end - attribute \src "libresoc.v:199449.3-199479.6" - process $proc$libresoc.v:199449$14015 + attribute \src "libresoc.v:200374.3-200424.6" + process $proc$libresoc.v:200374$13593 assign { } { } assign { } { } assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] - attribute \src "libresoc.v:199450.5-199450.29" + attribute \src "libresoc.v:200375.5-200375.29" switch \initial - attribute \src "libresoc.v:199450.9-199450.17" + attribute \src "libresoc.v:200375.9-200375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \$162 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -415454,10 +380143,25 @@ module \ti assign $2\core_stopped_i[0:0] 1'1 end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'101 + assign $1\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'110 assign { } { } assign $1\core_stopped_i[0:0] $3\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch \$168 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -415473,24 +380177,24 @@ module \ti sync always update \core_stopped_i $0\core_stopped_i[0:0] end - attribute \src "libresoc.v:199480.3-199510.6" - process $proc$libresoc.v:199480$14016 + attribute \src "libresoc.v:200425.3-200475.6" + process $proc$libresoc.v:200425$13594 assign { } { } assign { } { } assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:199481.5-199481.29" + attribute \src "libresoc.v:200426.5-200426.29" switch \initial - attribute \src "libresoc.v:199481.9-199481.17" + attribute \src "libresoc.v:200426.9-200426.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \$174 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -415501,10 +380205,25 @@ module \ti assign $2\dbg_core_stopped_i[0:0] 1'1 end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'101 + assign $1\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'110 assign { } { } assign $1\dbg_core_stopped_i[0:0] $3\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch \$180 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -415520,131 +380239,146 @@ module \ti sync always update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] end - attribute \src "libresoc.v:199511.3-199577.6" - process $proc$libresoc.v:199511$14017 + attribute \src "libresoc.v:200476.3-200562.6" + process $proc$libresoc.v:200476$13595 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\pc_changed$next[0:0]$14018 $9\pc_changed$next[0:0]$14027 - attribute \src "libresoc.v:199512.5-199512.29" + assign $0\pc_changed$next[0:0]$13596 $9\pc_changed$next[0:0]$13605 + attribute \src "libresoc.v:200477.5-200477.29" switch \initial - attribute \src "libresoc.v:199512.9-199512.17" + attribute \src "libresoc.v:200477.9-200477.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\pc_changed$next[0:0]$14019 $2\pc_changed$next[0:0]$14020 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + assign $1\pc_changed$next[0:0]$13597 $2\pc_changed$next[0:0]$13598 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \$186 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\pc_changed$next[0:0]$14020 \pc_changed + assign $2\pc_changed$next[0:0]$13598 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\pc_changed$next[0:0]$14020 $3\pc_changed$next[0:0]$14021 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" + assign $2\pc_changed$next[0:0]$13598 $3\pc_changed$next[0:0]$13599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:535" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\pc_changed$next[0:0]$14021 1'1 + assign $3\pc_changed$next[0:0]$13599 1'1 case - assign $3\pc_changed$next[0:0]$14021 \pc_changed + assign $3\pc_changed$next[0:0]$13599 \pc_changed end end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\pc_changed$next[0:0]$13597 \pc_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\pc_changed$next[0:0]$13597 \pc_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\pc_changed$next[0:0]$13597 \pc_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\pc_changed$next[0:0]$13597 \pc_changed + attribute \src "libresoc.v:0.0-0.0" case 3'101 + assign $1\pc_changed$next[0:0]$13597 \pc_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'110 assign { } { } - assign $1\pc_changed$next[0:0]$14019 $4\pc_changed$next[0:0]$14022 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + assign $1\pc_changed$next[0:0]$13597 $4\pc_changed$next[0:0]$13600 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch \$192 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\pc_changed$next[0:0]$14022 \pc_changed + assign $4\pc_changed$next[0:0]$13600 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\pc_changed$next[0:0]$14022 $5\pc_changed$next[0:0]$14023 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + assign $4\pc_changed$next[0:0]$13600 $5\pc_changed$next[0:0]$13601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:675" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\pc_changed$next[0:0]$14023 1'1 + assign $5\pc_changed$next[0:0]$13601 1'1 case - assign $5\pc_changed$next[0:0]$14023 \pc_changed + assign $5\pc_changed$next[0:0]$13601 \pc_changed end end case - assign $1\pc_changed$next[0:0]$14019 \pc_changed + assign $1\pc_changed$next[0:0]$13597 \pc_changed end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $6\pc_changed$next[0:0]$14024 $7\pc_changed$next[0:0]$14025 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + assign $6\pc_changed$next[0:0]$13602 $7\pc_changed$next[0:0]$13603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:716" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\pc_changed$next[0:0]$14025 1'0 + assign $7\pc_changed$next[0:0]$13603 1'0 case - assign $7\pc_changed$next[0:0]$14025 $1\pc_changed$next[0:0]$14019 + assign $7\pc_changed$next[0:0]$13603 $1\pc_changed$next[0:0]$13597 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\pc_changed$next[0:0]$14024 $8\pc_changed$next[0:0]$14026 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" + assign $6\pc_changed$next[0:0]$13602 $8\pc_changed$next[0:0]$13604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" switch \$194 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\pc_changed$next[0:0]$14026 1'1 + assign $8\pc_changed$next[0:0]$13604 1'1 case - assign $8\pc_changed$next[0:0]$14026 $1\pc_changed$next[0:0]$14019 + assign $8\pc_changed$next[0:0]$13604 $1\pc_changed$next[0:0]$13597 end case - assign $6\pc_changed$next[0:0]$14024 $1\pc_changed$next[0:0]$14019 + assign $6\pc_changed$next[0:0]$13602 $1\pc_changed$next[0:0]$13597 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\pc_changed$next[0:0]$14027 1'0 + assign $9\pc_changed$next[0:0]$13605 1'0 case - assign $9\pc_changed$next[0:0]$14027 $6\pc_changed$next[0:0]$14024 + assign $9\pc_changed$next[0:0]$13605 $6\pc_changed$next[0:0]$13602 end sync always - update \pc_changed$next $0\pc_changed$next[0:0]$14018 + update \pc_changed$next $0\pc_changed$next[0:0]$13596 end - attribute \src "libresoc.v:199578.3-199634.6" - process $proc$libresoc.v:199578$14028 + attribute \src "libresoc.v:200563.3-200641.6" + process $proc$libresoc.v:200563$13606 assign { } { } assign { } { } assign $0\update_svstate[0:0] $1\update_svstate[0:0] - attribute \src "libresoc.v:199579.5-199579.29" + attribute \src "libresoc.v:200564.5-200564.29" switch \initial - attribute \src "libresoc.v:199579.9-199579.17" + attribute \src "libresoc.v:200564.9-200564.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\update_svstate[0:0] $2\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \$202 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -415653,7 +380387,7 @@ module \ti case assign { } { } assign $2\update_svstate[0:0] $3\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -415664,22 +380398,37 @@ module \ti end end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'101 + assign $1\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'110 assign { } { } assign $1\update_svstate[0:0] $4\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch \$208 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\update_svstate[0:0] $5\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\update_svstate[0:0] $6\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:643" switch { \$214 \$210 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -415687,6 +380436,10 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'1- assign $6\update_svstate[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" + switch 1'0 + case + end attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -415699,7 +380452,7 @@ module \ti case assign { } { } assign $4\update_svstate[0:0] $7\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:679" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -415715,127 +380468,145 @@ module \ti sync always update \update_svstate $0\update_svstate[0:0] end - attribute \src "libresoc.v:199635.3-199701.6" - process $proc$libresoc.v:199635$14029 + attribute \src "libresoc.v:200642.3-200728.6" + process $proc$libresoc.v:200642$13607 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sv_changed$next[0:0]$14030 $9\sv_changed$next[0:0]$14039 - attribute \src "libresoc.v:199636.5-199636.29" + assign $0\sv_changed$next[0:0]$13608 $9\sv_changed$next[0:0]$13617 + attribute \src "libresoc.v:200643.5-200643.29" switch \initial - attribute \src "libresoc.v:199636.9-199636.17" + attribute \src "libresoc.v:200643.9-200643.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\sv_changed$next[0:0]$14031 $2\sv_changed$next[0:0]$14032 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + assign $1\sv_changed$next[0:0]$13609 $2\sv_changed$next[0:0]$13610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \$220 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\sv_changed$next[0:0]$14032 \sv_changed + assign $2\sv_changed$next[0:0]$13610 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\sv_changed$next[0:0]$14032 $3\sv_changed$next[0:0]$14033 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" + assign $2\sv_changed$next[0:0]$13610 $3\sv_changed$next[0:0]$13611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv_changed$next[0:0]$14033 1'1 + assign $3\sv_changed$next[0:0]$13611 1'1 case - assign $3\sv_changed$next[0:0]$14033 \sv_changed + assign $3\sv_changed$next[0:0]$13611 \sv_changed end end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\sv_changed$next[0:0]$13609 \sv_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\sv_changed$next[0:0]$13609 \sv_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\sv_changed$next[0:0]$13609 \sv_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\sv_changed$next[0:0]$13609 \sv_changed + attribute \src "libresoc.v:0.0-0.0" case 3'101 + assign $1\sv_changed$next[0:0]$13609 \sv_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'110 assign { } { } - assign $1\sv_changed$next[0:0]$14031 $4\sv_changed$next[0:0]$14034 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + assign $1\sv_changed$next[0:0]$13609 $4\sv_changed$next[0:0]$13612 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch \$226 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\sv_changed$next[0:0]$14034 \sv_changed + assign $4\sv_changed$next[0:0]$13612 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\sv_changed$next[0:0]$14034 $5\sv_changed$next[0:0]$14035 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" + assign $4\sv_changed$next[0:0]$13612 $5\sv_changed$next[0:0]$13613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:679" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv_changed$next[0:0]$14035 1'1 + assign $5\sv_changed$next[0:0]$13613 1'1 case - assign $5\sv_changed$next[0:0]$14035 \sv_changed + assign $5\sv_changed$next[0:0]$13613 \sv_changed end end case - assign $1\sv_changed$next[0:0]$14031 \sv_changed + assign $1\sv_changed$next[0:0]$13609 \sv_changed end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $6\sv_changed$next[0:0]$14036 $7\sv_changed$next[0:0]$14037 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + assign $6\sv_changed$next[0:0]$13614 $7\sv_changed$next[0:0]$13615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:716" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv_changed$next[0:0]$14037 1'0 + assign $7\sv_changed$next[0:0]$13615 1'0 case - assign $7\sv_changed$next[0:0]$14037 $1\sv_changed$next[0:0]$14031 + assign $7\sv_changed$next[0:0]$13615 $1\sv_changed$next[0:0]$13609 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv_changed$next[0:0]$14036 $8\sv_changed$next[0:0]$14038 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" + assign $6\sv_changed$next[0:0]$13614 $8\sv_changed$next[0:0]$13616 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" switch \$228 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\sv_changed$next[0:0]$14038 1'1 + assign $8\sv_changed$next[0:0]$13616 1'1 case - assign $8\sv_changed$next[0:0]$14038 $1\sv_changed$next[0:0]$14031 + assign $8\sv_changed$next[0:0]$13616 $1\sv_changed$next[0:0]$13609 end case - assign $6\sv_changed$next[0:0]$14036 $1\sv_changed$next[0:0]$14031 + assign $6\sv_changed$next[0:0]$13614 $1\sv_changed$next[0:0]$13609 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\sv_changed$next[0:0]$14039 1'0 + assign $9\sv_changed$next[0:0]$13617 1'0 case - assign $9\sv_changed$next[0:0]$14039 $6\sv_changed$next[0:0]$14036 + assign $9\sv_changed$next[0:0]$13617 $6\sv_changed$next[0:0]$13614 end sync always - update \sv_changed$next $0\sv_changed$next[0:0]$14030 + update \sv_changed$next $0\sv_changed$next[0:0]$13608 end - attribute \src "libresoc.v:199702.3-199712.6" - process $proc$libresoc.v:199702$14040 + attribute \src "libresoc.v:200729.3-200743.6" + process $proc$libresoc.v:200729$13618 assign { } { } assign { } { } assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:199703.5-199703.29" + attribute \src "libresoc.v:200730.5-200730.29" switch \initial - attribute \src "libresoc.v:199703.9-199703.17" + attribute \src "libresoc.v:200730.9-200730.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\fetch_insn_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\fetch_insn_ready_i[0:0] 1'1 @@ -415845,9 +380616,144 @@ module \ti sync always update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0] end - attribute \src "libresoc.v:199713.3-199823.6" - process $proc$libresoc.v:199713$14041 + attribute \src "libresoc.v:200744.3-200789.6" + process $proc$libresoc.v:200744$13619 + assign { } { } + assign { } { } + assign { } { } + assign $0\insn_done[0:0] $4\insn_done[0:0] + attribute \src "libresoc.v:200745.5-200745.29" + switch \initial + attribute \src "libresoc.v:200745.9-200745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\insn_done[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\insn_done[0:0] $2\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\insn_done[0:0] $3\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" + switch \$234 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\insn_done[0:0] 1'1 + case + assign $3\insn_done[0:0] 1'0 + end + case + assign $2\insn_done[0:0] 1'0 + end + case + assign $1\insn_done[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign $4\insn_done[0:0] $1\insn_done[0:0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\insn_done[0:0] $5\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" + switch \$236 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\insn_done[0:0] $6\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" + switch \exec_pc_ready_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\insn_done[0:0] 1'1 + case + assign $6\insn_done[0:0] $1\insn_done[0:0] + end + case + assign $5\insn_done[0:0] $1\insn_done[0:0] + end + case + assign $4\insn_done[0:0] $1\insn_done[0:0] + end + sync always + update \insn_done $0\insn_done[0:0] + end + attribute \src "libresoc.v:200790.3-200808.6" + process $proc$libresoc.v:200790$13620 assign { } { } + assign { } { } + assign $0\pred_insn_valid_i[0:0] $1\pred_insn_valid_i[0:0] + attribute \src "libresoc.v:200791.5-200791.29" + switch \initial + attribute \src "libresoc.v:200791.9-200791.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\pred_insn_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\pred_insn_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\pred_insn_valid_i[0:0] 1'1 + case + assign $1\pred_insn_valid_i[0:0] 1'0 + end + sync always + update \pred_insn_valid_i $0\pred_insn_valid_i[0:0] + end + attribute \src "libresoc.v:200809.3-200831.6" + process $proc$libresoc.v:200809$13621 + assign { } { } + assign { } { } + assign $0\pred_mask_ready_i[0:0] $1\pred_mask_ready_i[0:0] + attribute \src "libresoc.v:200810.5-200810.29" + switch \initial + attribute \src "libresoc.v:200810.9-200810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\pred_mask_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\pred_mask_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\pred_mask_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\pred_mask_ready_i[0:0] 1'1 + case + assign $1\pred_mask_ready_i[0:0] 1'0 + end + sync always + update \pred_mask_ready_i $0\pred_mask_ready_i[0:0] + end + attribute \src "libresoc.v:200832.3-200949.6" + process $proc$libresoc.v:200832$13622 assign { } { } assign { } { } assign { } { } @@ -415965,12 +380871,12 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_asmcode$next[7:0]$14042 $1\core_asmcode$next[7:0]$14101 - assign $0\core_core_core_cia$next[63:0]$14043 $1\core_core_core_cia$next[63:0]$14102 - assign $0\core_core_core_cr_rd$next[7:0]$14044 $1\core_core_core_cr_rd$next[7:0]$14103 assign { } { } - assign $0\core_core_core_cr_wr$next[7:0]$14046 $1\core_core_core_cr_wr$next[7:0]$14105 + assign $0\core_asmcode$next[7:0]$13623 $1\core_asmcode$next[7:0]$13682 + assign $0\core_core_core_cia$next[63:0]$13624 $1\core_core_core_cia$next[63:0]$13683 + assign $0\core_core_core_cr_rd$next[7:0]$13625 $1\core_core_core_cr_rd$next[7:0]$13684 assign { } { } + assign $0\core_core_core_cr_wr$next[7:0]$13627 $1\core_core_core_cr_wr$next[7:0]$13686 assign { } { } assign { } { } assign { } { } @@ -415978,334 +380884,334 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_core_fn_unit$next[13:0]$14055 $1\core_core_core_fn_unit$next[13:0]$14114 - assign $0\core_core_core_input_carry$next[1:0]$14056 $1\core_core_core_input_carry$next[1:0]$14115 - assign $0\core_core_core_insn$next[31:0]$14057 $1\core_core_core_insn$next[31:0]$14116 - assign $0\core_core_core_insn_type$next[6:0]$14058 $1\core_core_core_insn_type$next[6:0]$14117 - assign $0\core_core_core_is_32bit$next[0:0]$14059 $1\core_core_core_is_32bit$next[0:0]$14118 - assign $0\core_core_core_msr$next[63:0]$14060 $1\core_core_core_msr$next[63:0]$14119 - assign $0\core_core_core_oe$next[0:0]$14061 $1\core_core_core_oe$next[0:0]$14120 assign { } { } - assign $0\core_core_core_rc$next[0:0]$14063 $1\core_core_core_rc$next[0:0]$14122 + assign $0\core_core_core_fn_unit$next[13:0]$13636 $1\core_core_core_fn_unit$next[13:0]$13695 + assign $0\core_core_core_input_carry$next[1:0]$13637 $1\core_core_core_input_carry$next[1:0]$13696 + assign $0\core_core_core_insn$next[31:0]$13638 $1\core_core_core_insn$next[31:0]$13697 + assign $0\core_core_core_insn_type$next[6:0]$13639 $1\core_core_core_insn_type$next[6:0]$13698 + assign $0\core_core_core_is_32bit$next[0:0]$13640 $1\core_core_core_is_32bit$next[0:0]$13699 + assign $0\core_core_core_msr$next[63:0]$13641 $1\core_core_core_msr$next[63:0]$13700 + assign $0\core_core_core_oe$next[0:0]$13642 $1\core_core_core_oe$next[0:0]$13701 assign { } { } - assign $0\core_core_core_trapaddr$next[12:0]$14065 $1\core_core_core_trapaddr$next[12:0]$14124 - assign $0\core_core_core_traptype$next[7:0]$14066 $1\core_core_core_traptype$next[7:0]$14125 - assign $0\core_core_cr_in1$next[6:0]$14067 $1\core_core_cr_in1$next[6:0]$14126 + assign $0\core_core_core_rc$next[0:0]$13644 $1\core_core_core_rc$next[0:0]$13703 assign { } { } - assign $0\core_core_cr_in2$1$next[6:0]$14069 $1\core_core_cr_in2$1$next[6:0]$14128 - assign $0\core_core_cr_in2$next[6:0]$14070 $1\core_core_cr_in2$next[6:0]$14129 + assign $0\core_core_core_trapaddr$next[12:0]$13646 $1\core_core_core_trapaddr$next[12:0]$13705 + assign $0\core_core_core_traptype$next[7:0]$13647 $1\core_core_core_traptype$next[7:0]$13706 + assign $0\core_core_cr_in1$next[6:0]$13648 $1\core_core_cr_in1$next[6:0]$13707 assign { } { } + assign $0\core_core_cr_in2$1$next[6:0]$13650 $1\core_core_cr_in2$1$next[6:0]$13709 + assign $0\core_core_cr_in2$next[6:0]$13651 $1\core_core_cr_in2$next[6:0]$13710 assign { } { } - assign $0\core_core_cr_out$next[6:0]$14073 $1\core_core_cr_out$next[6:0]$14132 assign { } { } - assign $0\core_core_ea$next[6:0]$14075 $1\core_core_ea$next[6:0]$14134 - assign $0\core_core_fast1$next[2:0]$14076 $1\core_core_fast1$next[2:0]$14135 + assign $0\core_core_cr_out$next[6:0]$13654 $1\core_core_cr_out$next[6:0]$13713 assign { } { } - assign $0\core_core_fast2$next[2:0]$14078 $1\core_core_fast2$next[2:0]$14137 + assign $0\core_core_ea$next[6:0]$13656 $1\core_core_ea$next[6:0]$13715 + assign $0\core_core_fast1$next[2:0]$13657 $1\core_core_fast1$next[2:0]$13716 assign { } { } - assign $0\core_core_fasto1$next[2:0]$14080 $1\core_core_fasto1$next[2:0]$14139 - assign $0\core_core_fasto2$next[2:0]$14081 $1\core_core_fasto2$next[2:0]$14140 - assign $0\core_core_lk$next[0:0]$14082 $1\core_core_lk$next[0:0]$14141 - assign $0\core_core_reg1$next[6:0]$14083 $1\core_core_reg1$next[6:0]$14142 + assign $0\core_core_fast2$next[2:0]$13659 $1\core_core_fast2$next[2:0]$13718 assign { } { } - assign $0\core_core_reg2$next[6:0]$14085 $1\core_core_reg2$next[6:0]$14144 + assign $0\core_core_fasto1$next[2:0]$13661 $1\core_core_fasto1$next[2:0]$13720 + assign $0\core_core_fasto2$next[2:0]$13662 $1\core_core_fasto2$next[2:0]$13721 + assign $0\core_core_lk$next[0:0]$13663 $1\core_core_lk$next[0:0]$13722 + assign $0\core_core_reg1$next[6:0]$13664 $1\core_core_reg1$next[6:0]$13723 assign { } { } - assign $0\core_core_reg3$next[6:0]$14087 $1\core_core_reg3$next[6:0]$14146 + assign $0\core_core_reg2$next[6:0]$13666 $1\core_core_reg2$next[6:0]$13725 assign { } { } - assign $0\core_core_rego$next[6:0]$14089 $1\core_core_rego$next[6:0]$14148 - assign $0\core_core_spr1$next[9:0]$14090 $1\core_core_spr1$next[9:0]$14149 + assign $0\core_core_reg3$next[6:0]$13668 $1\core_core_reg3$next[6:0]$13727 assign { } { } - assign $0\core_core_spro$next[9:0]$14092 $1\core_core_spro$next[9:0]$14151 - assign $0\core_core_xer_in$next[2:0]$14093 $1\core_core_xer_in$next[2:0]$14152 + assign $0\core_core_rego$next[6:0]$13670 $1\core_core_rego$next[6:0]$13729 + assign $0\core_core_spr1$next[9:0]$13671 $1\core_core_spr1$next[9:0]$13730 assign { } { } + assign $0\core_core_spro$next[9:0]$13673 $1\core_core_spro$next[9:0]$13732 + assign $0\core_core_xer_in$next[2:0]$13674 $1\core_core_xer_in$next[2:0]$13733 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\core_xer_out$next[0:0]$14100 $1\core_xer_out$next[0:0]$14159 - assign $0\core_core_core_cr_rd_ok$next[0:0]$14045 $3\core_core_core_cr_rd_ok$next[0:0]$14219 - assign $0\core_core_core_exc_$signal$3$next[0:0]$14047 $3\core_core_core_exc_$signal$3$next[0:0]$14220 - assign $0\core_core_core_exc_$signal$4$next[0:0]$14048 $3\core_core_core_exc_$signal$4$next[0:0]$14221 - assign $0\core_core_core_exc_$signal$5$next[0:0]$14049 $3\core_core_core_exc_$signal$5$next[0:0]$14222 - assign $0\core_core_core_exc_$signal$6$next[0:0]$14050 $3\core_core_core_exc_$signal$6$next[0:0]$14223 - assign $0\core_core_core_exc_$signal$7$next[0:0]$14051 $3\core_core_core_exc_$signal$7$next[0:0]$14224 - assign $0\core_core_core_exc_$signal$8$next[0:0]$14052 $3\core_core_core_exc_$signal$8$next[0:0]$14225 - assign $0\core_core_core_exc_$signal$9$next[0:0]$14053 $3\core_core_core_exc_$signal$9$next[0:0]$14226 - assign $0\core_core_core_exc_$signal$next[0:0]$14054 $3\core_core_core_exc_$signal$next[0:0]$14227 - assign $0\core_core_core_oe_ok$next[0:0]$14062 $3\core_core_core_oe_ok$next[0:0]$14228 - assign $0\core_core_core_rc_ok$next[0:0]$14064 $3\core_core_core_rc_ok$next[0:0]$14229 - assign $0\core_core_cr_in1_ok$next[0:0]$14068 $3\core_core_cr_in1_ok$next[0:0]$14230 - assign $0\core_core_cr_in2_ok$2$next[0:0]$14071 $3\core_core_cr_in2_ok$2$next[0:0]$14231 - assign $0\core_core_cr_in2_ok$next[0:0]$14072 $3\core_core_cr_in2_ok$next[0:0]$14232 - assign $0\core_core_cr_wr_ok$next[0:0]$14074 $3\core_core_cr_wr_ok$next[0:0]$14233 - assign $0\core_core_fast1_ok$next[0:0]$14077 $3\core_core_fast1_ok$next[0:0]$14234 - assign $0\core_core_fast2_ok$next[0:0]$14079 $3\core_core_fast2_ok$next[0:0]$14235 - assign $0\core_core_reg1_ok$next[0:0]$14084 $3\core_core_reg1_ok$next[0:0]$14236 - assign $0\core_core_reg2_ok$next[0:0]$14086 $3\core_core_reg2_ok$next[0:0]$14237 - assign $0\core_core_reg3_ok$next[0:0]$14088 $3\core_core_reg3_ok$next[0:0]$14238 - assign $0\core_core_spr1_ok$next[0:0]$14091 $3\core_core_spr1_ok$next[0:0]$14239 - assign $0\core_cr_out_ok$next[0:0]$14094 $3\core_cr_out_ok$next[0:0]$14240 - assign $0\core_ea_ok$next[0:0]$14095 $3\core_ea_ok$next[0:0]$14241 - assign $0\core_fasto1_ok$next[0:0]$14096 $3\core_fasto1_ok$next[0:0]$14242 - assign $0\core_fasto2_ok$next[0:0]$14097 $3\core_fasto2_ok$next[0:0]$14243 - assign $0\core_rego_ok$next[0:0]$14098 $3\core_rego_ok$next[0:0]$14244 - assign $0\core_spro_ok$next[0:0]$14099 $3\core_spro_ok$next[0:0]$14245 - attribute \src "libresoc.v:199714.5-199714.29" + assign { } { } + assign $0\core_xer_out$next[0:0]$13681 $1\core_xer_out$next[0:0]$13740 + assign $0\core_core_core_cr_rd_ok$next[0:0]$13626 $2\core_core_core_cr_rd_ok$next[0:0]$13741 + assign $0\core_core_core_exc_$signal$3$next[0:0]$13628 $2\core_core_core_exc_$signal$3$next[0:0]$13742 + assign $0\core_core_core_exc_$signal$4$next[0:0]$13629 $2\core_core_core_exc_$signal$4$next[0:0]$13743 + assign $0\core_core_core_exc_$signal$5$next[0:0]$13630 $2\core_core_core_exc_$signal$5$next[0:0]$13744 + assign $0\core_core_core_exc_$signal$6$next[0:0]$13631 $2\core_core_core_exc_$signal$6$next[0:0]$13745 + assign $0\core_core_core_exc_$signal$7$next[0:0]$13632 $2\core_core_core_exc_$signal$7$next[0:0]$13746 + assign $0\core_core_core_exc_$signal$8$next[0:0]$13633 $2\core_core_core_exc_$signal$8$next[0:0]$13747 + assign $0\core_core_core_exc_$signal$9$next[0:0]$13634 $2\core_core_core_exc_$signal$9$next[0:0]$13748 + assign $0\core_core_core_exc_$signal$next[0:0]$13635 $2\core_core_core_exc_$signal$next[0:0]$13749 + assign $0\core_core_core_oe_ok$next[0:0]$13643 $2\core_core_core_oe_ok$next[0:0]$13750 + assign $0\core_core_core_rc_ok$next[0:0]$13645 $2\core_core_core_rc_ok$next[0:0]$13751 + assign $0\core_core_cr_in1_ok$next[0:0]$13649 $2\core_core_cr_in1_ok$next[0:0]$13752 + assign $0\core_core_cr_in2_ok$2$next[0:0]$13652 $2\core_core_cr_in2_ok$2$next[0:0]$13753 + assign $0\core_core_cr_in2_ok$next[0:0]$13653 $2\core_core_cr_in2_ok$next[0:0]$13754 + assign $0\core_core_cr_wr_ok$next[0:0]$13655 $2\core_core_cr_wr_ok$next[0:0]$13755 + assign $0\core_core_fast1_ok$next[0:0]$13658 $2\core_core_fast1_ok$next[0:0]$13756 + assign $0\core_core_fast2_ok$next[0:0]$13660 $2\core_core_fast2_ok$next[0:0]$13757 + assign $0\core_core_reg1_ok$next[0:0]$13665 $2\core_core_reg1_ok$next[0:0]$13758 + assign $0\core_core_reg2_ok$next[0:0]$13667 $2\core_core_reg2_ok$next[0:0]$13759 + assign $0\core_core_reg3_ok$next[0:0]$13669 $2\core_core_reg3_ok$next[0:0]$13760 + assign $0\core_core_spr1_ok$next[0:0]$13672 $2\core_core_spr1_ok$next[0:0]$13761 + assign $0\core_cr_out_ok$next[0:0]$13675 $2\core_cr_out_ok$next[0:0]$13762 + assign $0\core_ea_ok$next[0:0]$13676 $2\core_ea_ok$next[0:0]$13763 + assign $0\core_fasto1_ok$next[0:0]$13677 $2\core_fasto1_ok$next[0:0]$13764 + assign $0\core_fasto2_ok$next[0:0]$13678 $2\core_fasto2_ok$next[0:0]$13765 + assign $0\core_rego_ok$next[0:0]$13679 $2\core_rego_ok$next[0:0]$13766 + assign $0\core_spro_ok$next[0:0]$13680 $2\core_spro_ok$next[0:0]$13767 + attribute \src "libresoc.v:200833.5-200833.29" switch \initial - attribute \src "libresoc.v:199714.9-199714.17" + attribute \src "libresoc.v:200833.9-200833.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\core_asmcode$next[7:0]$13682 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13683 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13684 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13685 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13686 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13687 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13688 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13689 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13690 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13691 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13692 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13693 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13694 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$13695 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13696 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13697 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13698 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13699 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13700 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13701 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13702 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13703 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13704 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13705 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13706 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$13707 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13708 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$13709 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$13710 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13711 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13712 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$13713 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13714 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$13715 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13716 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13717 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13718 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13719 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13720 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13721 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13722 \core_core_lk + assign $1\core_core_reg1$next[6:0]$13723 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13724 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$13725 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13726 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$13727 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13728 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$13729 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13730 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13731 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13732 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13733 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13734 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13735 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13736 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13737 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13738 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13739 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13740 \core_xer_out + attribute \src "libresoc.v:0.0-0.0" case 3'001 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\core_asmcode$next[7:0]$14101 $2\core_asmcode$next[7:0]$14160 - assign $1\core_core_core_cia$next[63:0]$14102 $2\core_core_core_cia$next[63:0]$14161 - assign $1\core_core_core_cr_rd$next[7:0]$14103 $2\core_core_core_cr_rd$next[7:0]$14162 - assign $1\core_core_core_cr_rd_ok$next[0:0]$14104 $2\core_core_core_cr_rd_ok$next[0:0]$14163 - assign $1\core_core_core_cr_wr$next[7:0]$14105 $2\core_core_core_cr_wr$next[7:0]$14164 - assign $1\core_core_core_exc_$signal$3$next[0:0]$14106 $2\core_core_core_exc_$signal$3$next[0:0]$14165 - assign $1\core_core_core_exc_$signal$4$next[0:0]$14107 $2\core_core_core_exc_$signal$4$next[0:0]$14166 - assign $1\core_core_core_exc_$signal$5$next[0:0]$14108 $2\core_core_core_exc_$signal$5$next[0:0]$14167 - assign $1\core_core_core_exc_$signal$6$next[0:0]$14109 $2\core_core_core_exc_$signal$6$next[0:0]$14168 - assign $1\core_core_core_exc_$signal$7$next[0:0]$14110 $2\core_core_core_exc_$signal$7$next[0:0]$14169 - assign $1\core_core_core_exc_$signal$8$next[0:0]$14111 $2\core_core_core_exc_$signal$8$next[0:0]$14170 - assign $1\core_core_core_exc_$signal$9$next[0:0]$14112 $2\core_core_core_exc_$signal$9$next[0:0]$14171 - assign $1\core_core_core_exc_$signal$next[0:0]$14113 $2\core_core_core_exc_$signal$next[0:0]$14172 - assign $1\core_core_core_fn_unit$next[13:0]$14114 $2\core_core_core_fn_unit$next[13:0]$14173 - assign $1\core_core_core_input_carry$next[1:0]$14115 $2\core_core_core_input_carry$next[1:0]$14174 - assign $1\core_core_core_insn$next[31:0]$14116 $2\core_core_core_insn$next[31:0]$14175 - assign $1\core_core_core_insn_type$next[6:0]$14117 $2\core_core_core_insn_type$next[6:0]$14176 - assign $1\core_core_core_is_32bit$next[0:0]$14118 $2\core_core_core_is_32bit$next[0:0]$14177 - assign $1\core_core_core_msr$next[63:0]$14119 $2\core_core_core_msr$next[63:0]$14178 - assign $1\core_core_core_oe$next[0:0]$14120 $2\core_core_core_oe$next[0:0]$14179 - assign $1\core_core_core_oe_ok$next[0:0]$14121 $2\core_core_core_oe_ok$next[0:0]$14180 - assign $1\core_core_core_rc$next[0:0]$14122 $2\core_core_core_rc$next[0:0]$14181 - assign $1\core_core_core_rc_ok$next[0:0]$14123 $2\core_core_core_rc_ok$next[0:0]$14182 - assign $1\core_core_core_trapaddr$next[12:0]$14124 $2\core_core_core_trapaddr$next[12:0]$14183 - assign $1\core_core_core_traptype$next[7:0]$14125 $2\core_core_core_traptype$next[7:0]$14184 - assign $1\core_core_cr_in1$next[6:0]$14126 $2\core_core_cr_in1$next[6:0]$14185 - assign $1\core_core_cr_in1_ok$next[0:0]$14127 $2\core_core_cr_in1_ok$next[0:0]$14186 - assign $1\core_core_cr_in2$1$next[6:0]$14128 $2\core_core_cr_in2$1$next[6:0]$14187 - assign $1\core_core_cr_in2$next[6:0]$14129 $2\core_core_cr_in2$next[6:0]$14188 - assign $1\core_core_cr_in2_ok$2$next[0:0]$14130 $2\core_core_cr_in2_ok$2$next[0:0]$14189 - assign $1\core_core_cr_in2_ok$next[0:0]$14131 $2\core_core_cr_in2_ok$next[0:0]$14190 - assign $1\core_core_cr_out$next[6:0]$14132 $2\core_core_cr_out$next[6:0]$14191 - assign $1\core_core_cr_wr_ok$next[0:0]$14133 $2\core_core_cr_wr_ok$next[0:0]$14192 - assign $1\core_core_ea$next[6:0]$14134 $2\core_core_ea$next[6:0]$14193 - assign $1\core_core_fast1$next[2:0]$14135 $2\core_core_fast1$next[2:0]$14194 - assign $1\core_core_fast1_ok$next[0:0]$14136 $2\core_core_fast1_ok$next[0:0]$14195 - assign $1\core_core_fast2$next[2:0]$14137 $2\core_core_fast2$next[2:0]$14196 - assign $1\core_core_fast2_ok$next[0:0]$14138 $2\core_core_fast2_ok$next[0:0]$14197 - assign $1\core_core_fasto1$next[2:0]$14139 $2\core_core_fasto1$next[2:0]$14198 - assign $1\core_core_fasto2$next[2:0]$14140 $2\core_core_fasto2$next[2:0]$14199 - assign $1\core_core_lk$next[0:0]$14141 $2\core_core_lk$next[0:0]$14200 - assign $1\core_core_reg1$next[6:0]$14142 $2\core_core_reg1$next[6:0]$14201 - assign $1\core_core_reg1_ok$next[0:0]$14143 $2\core_core_reg1_ok$next[0:0]$14202 - assign $1\core_core_reg2$next[6:0]$14144 $2\core_core_reg2$next[6:0]$14203 - assign $1\core_core_reg2_ok$next[0:0]$14145 $2\core_core_reg2_ok$next[0:0]$14204 - assign $1\core_core_reg3$next[6:0]$14146 $2\core_core_reg3$next[6:0]$14205 - assign $1\core_core_reg3_ok$next[0:0]$14147 $2\core_core_reg3_ok$next[0:0]$14206 - assign $1\core_core_rego$next[6:0]$14148 $2\core_core_rego$next[6:0]$14207 - assign $1\core_core_spr1$next[9:0]$14149 $2\core_core_spr1$next[9:0]$14208 - assign $1\core_core_spr1_ok$next[0:0]$14150 $2\core_core_spr1_ok$next[0:0]$14209 - assign $1\core_core_spro$next[9:0]$14151 $2\core_core_spro$next[9:0]$14210 - assign $1\core_core_xer_in$next[2:0]$14152 $2\core_core_xer_in$next[2:0]$14211 - assign $1\core_cr_out_ok$next[0:0]$14153 $2\core_cr_out_ok$next[0:0]$14212 - assign $1\core_ea_ok$next[0:0]$14154 $2\core_ea_ok$next[0:0]$14213 - assign $1\core_fasto1_ok$next[0:0]$14155 $2\core_fasto1_ok$next[0:0]$14214 - assign $1\core_fasto2_ok$next[0:0]$14156 $2\core_fasto2_ok$next[0:0]$14215 - assign $1\core_rego_ok$next[0:0]$14157 $2\core_rego_ok$next[0:0]$14216 - assign $1\core_spro_ok$next[0:0]$14158 $2\core_spro_ok$next[0:0]$14217 - assign $1\core_xer_out$next[0:0]$14159 $2\core_xer_out$next[0:0]$14218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" - switch \fetch_insn_valid_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\core_core_core_is_32bit$next[0:0]$14177 $2\core_core_cr_wr_ok$next[0:0]$14192 $2\core_core_core_cr_wr$next[7:0]$14164 $2\core_core_core_cr_rd_ok$next[0:0]$14163 $2\core_core_core_cr_rd$next[7:0]$14162 $2\core_core_core_trapaddr$next[12:0]$14183 $2\core_core_core_exc_$signal$9$next[0:0]$14171 $2\core_core_core_exc_$signal$8$next[0:0]$14170 $2\core_core_core_exc_$signal$7$next[0:0]$14169 $2\core_core_core_exc_$signal$6$next[0:0]$14168 $2\core_core_core_exc_$signal$5$next[0:0]$14167 $2\core_core_core_exc_$signal$4$next[0:0]$14166 $2\core_core_core_exc_$signal$3$next[0:0]$14165 $2\core_core_core_exc_$signal$next[0:0]$14172 $2\core_core_core_traptype$next[7:0]$14184 $2\core_core_core_input_carry$next[1:0]$14174 $2\core_core_core_oe_ok$next[0:0]$14180 $2\core_core_core_oe$next[0:0]$14179 $2\core_core_core_rc_ok$next[0:0]$14182 $2\core_core_core_rc$next[0:0]$14181 $2\core_core_lk$next[0:0]$14200 $2\core_core_core_fn_unit$next[13:0]$14173 $2\core_core_core_insn_type$next[6:0]$14176 $2\core_core_core_insn$next[31:0]$14175 $2\core_core_core_cia$next[63:0]$14161 $2\core_core_core_msr$next[63:0]$14178 $2\core_cr_out_ok$next[0:0]$14212 $2\core_core_cr_out$next[6:0]$14191 $2\core_core_cr_in2_ok$2$next[0:0]$14189 $2\core_core_cr_in2$1$next[6:0]$14187 $2\core_core_cr_in2_ok$next[0:0]$14190 $2\core_core_cr_in2$next[6:0]$14188 $2\core_core_cr_in1_ok$next[0:0]$14186 $2\core_core_cr_in1$next[6:0]$14185 $2\core_fasto2_ok$next[0:0]$14215 $2\core_core_fasto2$next[2:0]$14199 $2\core_fasto1_ok$next[0:0]$14214 $2\core_core_fasto1$next[2:0]$14198 $2\core_core_fast2_ok$next[0:0]$14197 $2\core_core_fast2$next[2:0]$14196 $2\core_core_fast1_ok$next[0:0]$14195 $2\core_core_fast1$next[2:0]$14194 $2\core_xer_out$next[0:0]$14218 $2\core_core_xer_in$next[2:0]$14211 $2\core_core_spr1_ok$next[0:0]$14209 $2\core_core_spr1$next[9:0]$14208 $2\core_spro_ok$next[0:0]$14217 $2\core_core_spro$next[9:0]$14210 $2\core_core_reg3_ok$next[0:0]$14206 $2\core_core_reg3$next[6:0]$14205 $2\core_core_reg2_ok$next[0:0]$14204 $2\core_core_reg2$next[6:0]$14203 $2\core_core_reg1_ok$next[0:0]$14202 $2\core_core_reg1$next[6:0]$14201 $2\core_ea_ok$next[0:0]$14213 $2\core_core_ea$next[6:0]$14193 $2\core_rego_ok$next[0:0]$14216 $2\core_core_rego$next[6:0]$14207 $2\core_asmcode$next[7:0]$14160 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } - case - assign $2\core_asmcode$next[7:0]$14160 \core_asmcode - assign $2\core_core_core_cia$next[63:0]$14161 \core_core_core_cia - assign $2\core_core_core_cr_rd$next[7:0]$14162 \core_core_core_cr_rd - assign $2\core_core_core_cr_rd_ok$next[0:0]$14163 \core_core_core_cr_rd_ok - assign $2\core_core_core_cr_wr$next[7:0]$14164 \core_core_core_cr_wr - assign $2\core_core_core_exc_$signal$3$next[0:0]$14165 \core_core_core_exc_$signal$3 - assign $2\core_core_core_exc_$signal$4$next[0:0]$14166 \core_core_core_exc_$signal$4 - assign $2\core_core_core_exc_$signal$5$next[0:0]$14167 \core_core_core_exc_$signal$5 - assign $2\core_core_core_exc_$signal$6$next[0:0]$14168 \core_core_core_exc_$signal$6 - assign $2\core_core_core_exc_$signal$7$next[0:0]$14169 \core_core_core_exc_$signal$7 - assign $2\core_core_core_exc_$signal$8$next[0:0]$14170 \core_core_core_exc_$signal$8 - assign $2\core_core_core_exc_$signal$9$next[0:0]$14171 \core_core_core_exc_$signal$9 - assign $2\core_core_core_exc_$signal$next[0:0]$14172 \core_core_core_exc_$signal - assign $2\core_core_core_fn_unit$next[13:0]$14173 \core_core_core_fn_unit - assign $2\core_core_core_input_carry$next[1:0]$14174 \core_core_core_input_carry - assign $2\core_core_core_insn$next[31:0]$14175 \core_core_core_insn - assign $2\core_core_core_insn_type$next[6:0]$14176 \core_core_core_insn_type - assign $2\core_core_core_is_32bit$next[0:0]$14177 \core_core_core_is_32bit - assign $2\core_core_core_msr$next[63:0]$14178 \core_core_core_msr - assign $2\core_core_core_oe$next[0:0]$14179 \core_core_core_oe - assign $2\core_core_core_oe_ok$next[0:0]$14180 \core_core_core_oe_ok - assign $2\core_core_core_rc$next[0:0]$14181 \core_core_core_rc - assign $2\core_core_core_rc_ok$next[0:0]$14182 \core_core_core_rc_ok - assign $2\core_core_core_trapaddr$next[12:0]$14183 \core_core_core_trapaddr - assign $2\core_core_core_traptype$next[7:0]$14184 \core_core_core_traptype - assign $2\core_core_cr_in1$next[6:0]$14185 \core_core_cr_in1 - assign $2\core_core_cr_in1_ok$next[0:0]$14186 \core_core_cr_in1_ok - assign $2\core_core_cr_in2$1$next[6:0]$14187 \core_core_cr_in2$1 - assign $2\core_core_cr_in2$next[6:0]$14188 \core_core_cr_in2 - assign $2\core_core_cr_in2_ok$2$next[0:0]$14189 \core_core_cr_in2_ok$2 - assign $2\core_core_cr_in2_ok$next[0:0]$14190 \core_core_cr_in2_ok - assign $2\core_core_cr_out$next[6:0]$14191 \core_core_cr_out - assign $2\core_core_cr_wr_ok$next[0:0]$14192 \core_core_cr_wr_ok - assign $2\core_core_ea$next[6:0]$14193 \core_core_ea - assign $2\core_core_fast1$next[2:0]$14194 \core_core_fast1 - assign $2\core_core_fast1_ok$next[0:0]$14195 \core_core_fast1_ok - assign $2\core_core_fast2$next[2:0]$14196 \core_core_fast2 - assign $2\core_core_fast2_ok$next[0:0]$14197 \core_core_fast2_ok - assign $2\core_core_fasto1$next[2:0]$14198 \core_core_fasto1 - assign $2\core_core_fasto2$next[2:0]$14199 \core_core_fasto2 - assign $2\core_core_lk$next[0:0]$14200 \core_core_lk - assign $2\core_core_reg1$next[6:0]$14201 \core_core_reg1 - assign $2\core_core_reg1_ok$next[0:0]$14202 \core_core_reg1_ok - assign $2\core_core_reg2$next[6:0]$14203 \core_core_reg2 - assign $2\core_core_reg2_ok$next[0:0]$14204 \core_core_reg2_ok - assign $2\core_core_reg3$next[6:0]$14205 \core_core_reg3 - assign $2\core_core_reg3_ok$next[0:0]$14206 \core_core_reg3_ok - assign $2\core_core_rego$next[6:0]$14207 \core_core_rego - assign $2\core_core_spr1$next[9:0]$14208 \core_core_spr1 - assign $2\core_core_spr1_ok$next[0:0]$14209 \core_core_spr1_ok - assign $2\core_core_spro$next[9:0]$14210 \core_core_spro - assign $2\core_core_xer_in$next[2:0]$14211 \core_core_xer_in - assign $2\core_cr_out_ok$next[0:0]$14212 \core_cr_out_ok - assign $2\core_ea_ok$next[0:0]$14213 \core_ea_ok - assign $2\core_fasto1_ok$next[0:0]$14214 \core_fasto1_ok - assign $2\core_fasto2_ok$next[0:0]$14215 \core_fasto2_ok - assign $2\core_rego_ok$next[0:0]$14216 \core_rego_ok - assign $2\core_spro_ok$next[0:0]$14217 \core_spro_ok - assign $2\core_xer_out$next[0:0]$14218 \core_xer_out - end + assign $1\core_asmcode$next[7:0]$13682 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13683 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13684 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13685 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13686 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13687 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13688 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13689 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13690 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13691 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13692 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13693 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13694 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$13695 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13696 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13697 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13698 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13699 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13700 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13701 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13702 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13703 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13704 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13705 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13706 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$13707 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13708 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$13709 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$13710 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13711 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13712 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$13713 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13714 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$13715 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13716 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13717 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13718 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13719 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13720 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13721 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13722 \core_core_lk + assign $1\core_core_reg1$next[6:0]$13723 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13724 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$13725 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13726 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$13727 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13728 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$13729 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13730 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13731 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13732 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13733 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13734 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13735 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13736 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13737 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13738 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13739 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13740 \core_xer_out attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 3'011 + assign $1\core_asmcode$next[7:0]$13682 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13683 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13684 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13685 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13686 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13687 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13688 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13689 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13690 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13691 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13692 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13693 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13694 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$13695 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13696 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13697 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13698 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13699 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13700 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13701 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13702 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13703 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13704 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13705 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13706 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$13707 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13708 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$13709 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$13710 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13711 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13712 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$13713 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13714 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$13715 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13716 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13717 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13718 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13719 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13720 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13721 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13722 \core_core_lk + assign $1\core_core_reg1$next[6:0]$13723 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13724 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$13725 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13726 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$13727 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13728 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$13729 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13730 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13731 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13732 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13733 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13734 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13735 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13736 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13737 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13738 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13739 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13740 \core_xer_out + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_asmcode$next[7:0]$13682 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13683 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13684 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13685 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13686 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13687 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13688 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13689 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13690 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13691 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13692 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13693 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13694 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$13695 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13696 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13697 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13698 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13699 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13700 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13701 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13702 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13703 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13704 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13705 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13706 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$13707 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13708 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$13709 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$13710 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13711 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13712 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$13713 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13714 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$13715 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13716 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13717 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13718 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13719 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13720 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13721 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13722 \core_core_lk + assign $1\core_core_reg1$next[6:0]$13723 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13724 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$13725 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13726 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$13727 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13728 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$13729 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13730 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13731 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13732 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13733 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13734 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13735 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13736 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13737 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13738 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13739 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13740 \core_xer_out + attribute \src "libresoc.v:0.0-0.0" + case 3'010 assign { } { } assign { } { } assign { } { } @@ -416365,67 +381271,67 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $1\core_core_core_is_32bit$next[0:0]$14118 $1\core_core_cr_wr_ok$next[0:0]$14133 $1\core_core_core_cr_wr$next[7:0]$14105 $1\core_core_core_cr_rd_ok$next[0:0]$14104 $1\core_core_core_cr_rd$next[7:0]$14103 $1\core_core_core_trapaddr$next[12:0]$14124 $1\core_core_core_exc_$signal$9$next[0:0]$14112 $1\core_core_core_exc_$signal$8$next[0:0]$14111 $1\core_core_core_exc_$signal$7$next[0:0]$14110 $1\core_core_core_exc_$signal$6$next[0:0]$14109 $1\core_core_core_exc_$signal$5$next[0:0]$14108 $1\core_core_core_exc_$signal$4$next[0:0]$14107 $1\core_core_core_exc_$signal$3$next[0:0]$14106 $1\core_core_core_exc_$signal$next[0:0]$14113 $1\core_core_core_traptype$next[7:0]$14125 $1\core_core_core_input_carry$next[1:0]$14115 $1\core_core_core_oe_ok$next[0:0]$14121 $1\core_core_core_oe$next[0:0]$14120 $1\core_core_core_rc_ok$next[0:0]$14123 $1\core_core_core_rc$next[0:0]$14122 $1\core_core_lk$next[0:0]$14141 $1\core_core_core_fn_unit$next[13:0]$14114 $1\core_core_core_insn_type$next[6:0]$14117 $1\core_core_core_insn$next[31:0]$14116 $1\core_core_core_cia$next[63:0]$14102 $1\core_core_core_msr$next[63:0]$14119 $1\core_cr_out_ok$next[0:0]$14153 $1\core_core_cr_out$next[6:0]$14132 $1\core_core_cr_in2_ok$2$next[0:0]$14130 $1\core_core_cr_in2$1$next[6:0]$14128 $1\core_core_cr_in2_ok$next[0:0]$14131 $1\core_core_cr_in2$next[6:0]$14129 $1\core_core_cr_in1_ok$next[0:0]$14127 $1\core_core_cr_in1$next[6:0]$14126 $1\core_fasto2_ok$next[0:0]$14156 $1\core_core_fasto2$next[2:0]$14140 $1\core_fasto1_ok$next[0:0]$14155 $1\core_core_fasto1$next[2:0]$14139 $1\core_core_fast2_ok$next[0:0]$14138 $1\core_core_fast2$next[2:0]$14137 $1\core_core_fast1_ok$next[0:0]$14136 $1\core_core_fast1$next[2:0]$14135 $1\core_xer_out$next[0:0]$14159 $1\core_core_xer_in$next[2:0]$14152 $1\core_core_spr1_ok$next[0:0]$14150 $1\core_core_spr1$next[9:0]$14149 $1\core_spro_ok$next[0:0]$14158 $1\core_core_spro$next[9:0]$14151 $1\core_core_reg3_ok$next[0:0]$14147 $1\core_core_reg3$next[6:0]$14146 $1\core_core_reg2_ok$next[0:0]$14145 $1\core_core_reg2$next[6:0]$14144 $1\core_core_reg1_ok$next[0:0]$14143 $1\core_core_reg1$next[6:0]$14142 $1\core_ea_ok$next[0:0]$14154 $1\core_core_ea$next[6:0]$14134 $1\core_rego_ok$next[0:0]$14157 $1\core_core_rego$next[6:0]$14148 $1\core_asmcode$next[7:0]$14101 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { $1\core_core_core_is_32bit$next[0:0]$13699 $1\core_core_cr_wr_ok$next[0:0]$13714 $1\core_core_core_cr_wr$next[7:0]$13686 $1\core_core_core_cr_rd_ok$next[0:0]$13685 $1\core_core_core_cr_rd$next[7:0]$13684 $1\core_core_core_trapaddr$next[12:0]$13705 $1\core_core_core_exc_$signal$9$next[0:0]$13693 $1\core_core_core_exc_$signal$8$next[0:0]$13692 $1\core_core_core_exc_$signal$7$next[0:0]$13691 $1\core_core_core_exc_$signal$6$next[0:0]$13690 $1\core_core_core_exc_$signal$5$next[0:0]$13689 $1\core_core_core_exc_$signal$4$next[0:0]$13688 $1\core_core_core_exc_$signal$3$next[0:0]$13687 $1\core_core_core_exc_$signal$next[0:0]$13694 $1\core_core_core_traptype$next[7:0]$13706 $1\core_core_core_input_carry$next[1:0]$13696 $1\core_core_core_oe_ok$next[0:0]$13702 $1\core_core_core_oe$next[0:0]$13701 $1\core_core_core_rc_ok$next[0:0]$13704 $1\core_core_core_rc$next[0:0]$13703 $1\core_core_lk$next[0:0]$13722 $1\core_core_core_fn_unit$next[13:0]$13695 $1\core_core_core_insn_type$next[6:0]$13698 $1\core_core_core_insn$next[31:0]$13697 $1\core_core_core_cia$next[63:0]$13683 $1\core_core_core_msr$next[63:0]$13700 $1\core_cr_out_ok$next[0:0]$13734 $1\core_core_cr_out$next[6:0]$13713 $1\core_core_cr_in2_ok$2$next[0:0]$13711 $1\core_core_cr_in2$1$next[6:0]$13709 $1\core_core_cr_in2_ok$next[0:0]$13712 $1\core_core_cr_in2$next[6:0]$13710 $1\core_core_cr_in1_ok$next[0:0]$13708 $1\core_core_cr_in1$next[6:0]$13707 $1\core_fasto2_ok$next[0:0]$13737 $1\core_core_fasto2$next[2:0]$13721 $1\core_fasto1_ok$next[0:0]$13736 $1\core_core_fasto1$next[2:0]$13720 $1\core_core_fast2_ok$next[0:0]$13719 $1\core_core_fast2$next[2:0]$13718 $1\core_core_fast1_ok$next[0:0]$13717 $1\core_core_fast1$next[2:0]$13716 $1\core_xer_out$next[0:0]$13740 $1\core_core_xer_in$next[2:0]$13733 $1\core_core_spr1_ok$next[0:0]$13731 $1\core_core_spr1$next[9:0]$13730 $1\core_spro_ok$next[0:0]$13739 $1\core_core_spro$next[9:0]$13732 $1\core_core_reg3_ok$next[0:0]$13728 $1\core_core_reg3$next[6:0]$13727 $1\core_core_reg2_ok$next[0:0]$13726 $1\core_core_reg2$next[6:0]$13725 $1\core_core_reg1_ok$next[0:0]$13724 $1\core_core_reg1$next[6:0]$13723 $1\core_ea_ok$next[0:0]$13735 $1\core_core_ea$next[6:0]$13715 $1\core_rego_ok$next[0:0]$13738 $1\core_core_rego$next[6:0]$13729 $1\core_asmcode$next[7:0]$13682 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case - assign $1\core_asmcode$next[7:0]$14101 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$14102 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$14103 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$14104 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$14105 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$14106 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$14107 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$14108 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$14109 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$14110 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$14111 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$14112 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$14113 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[13:0]$14114 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$14115 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$14116 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$14117 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$14118 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$14119 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$14120 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$14121 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$14122 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$14123 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$14124 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$14125 \core_core_core_traptype - assign $1\core_core_cr_in1$next[6:0]$14126 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$14127 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[6:0]$14128 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[6:0]$14129 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$14130 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$14131 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[6:0]$14132 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$14133 \core_core_cr_wr_ok - assign $1\core_core_ea$next[6:0]$14134 \core_core_ea - assign $1\core_core_fast1$next[2:0]$14135 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$14136 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$14137 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$14138 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$14139 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$14140 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$14141 \core_core_lk - assign $1\core_core_reg1$next[6:0]$14142 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$14143 \core_core_reg1_ok - assign $1\core_core_reg2$next[6:0]$14144 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$14145 \core_core_reg2_ok - assign $1\core_core_reg3$next[6:0]$14146 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$14147 \core_core_reg3_ok - assign $1\core_core_rego$next[6:0]$14148 \core_core_rego - assign $1\core_core_spr1$next[9:0]$14149 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$14150 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$14151 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$14152 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$14153 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$14154 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$14155 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$14156 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$14157 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$14158 \core_spro_ok - assign $1\core_xer_out$next[0:0]$14159 \core_xer_out + assign $1\core_asmcode$next[7:0]$13682 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13683 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13684 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13685 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13686 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13687 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13688 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13689 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13690 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13691 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13692 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13693 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13694 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$13695 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13696 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13697 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13698 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13699 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13700 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13701 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13702 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13703 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13704 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13705 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13706 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$13707 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13708 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$13709 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$13710 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13711 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13712 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$13713 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13714 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$13715 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13716 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13717 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13718 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13719 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13720 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13721 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13722 \core_core_lk + assign $1\core_core_reg1$next[6:0]$13723 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13724 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$13725 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13726 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$13727 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13728 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$13729 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13730 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13731 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13732 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13733 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13734 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13735 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13736 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13737 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13738 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13739 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13740 \core_xer_out end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -416458,243 +381364,243 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_rego_ok$next[0:0]$14244 1'0 - assign $3\core_ea_ok$next[0:0]$14241 1'0 - assign $3\core_core_reg1_ok$next[0:0]$14236 1'0 - assign $3\core_core_reg2_ok$next[0:0]$14237 1'0 - assign $3\core_core_reg3_ok$next[0:0]$14238 1'0 - assign $3\core_spro_ok$next[0:0]$14245 1'0 - assign $3\core_core_spr1_ok$next[0:0]$14239 1'0 - assign $3\core_core_fast1_ok$next[0:0]$14234 1'0 - assign $3\core_core_fast2_ok$next[0:0]$14235 1'0 - assign $3\core_fasto1_ok$next[0:0]$14242 1'0 - assign $3\core_fasto2_ok$next[0:0]$14243 1'0 - assign $3\core_core_cr_in1_ok$next[0:0]$14230 1'0 - assign $3\core_core_cr_in2_ok$next[0:0]$14232 1'0 - assign $3\core_core_cr_in2_ok$2$next[0:0]$14231 1'0 - assign $3\core_cr_out_ok$next[0:0]$14240 1'0 - assign $3\core_core_core_rc_ok$next[0:0]$14229 1'0 - assign $3\core_core_core_oe_ok$next[0:0]$14228 1'0 - assign $3\core_core_core_exc_$signal$next[0:0]$14227 1'0 - assign $3\core_core_core_exc_$signal$3$next[0:0]$14220 1'0 - assign $3\core_core_core_exc_$signal$4$next[0:0]$14221 1'0 - assign $3\core_core_core_exc_$signal$5$next[0:0]$14222 1'0 - assign $3\core_core_core_exc_$signal$6$next[0:0]$14223 1'0 - assign $3\core_core_core_exc_$signal$7$next[0:0]$14224 1'0 - assign $3\core_core_core_exc_$signal$8$next[0:0]$14225 1'0 - assign $3\core_core_core_exc_$signal$9$next[0:0]$14226 1'0 - assign $3\core_core_core_cr_rd_ok$next[0:0]$14219 1'0 - assign $3\core_core_cr_wr_ok$next[0:0]$14233 1'0 - case - assign $3\core_core_core_cr_rd_ok$next[0:0]$14219 $1\core_core_core_cr_rd_ok$next[0:0]$14104 - assign $3\core_core_core_exc_$signal$3$next[0:0]$14220 $1\core_core_core_exc_$signal$3$next[0:0]$14106 - assign $3\core_core_core_exc_$signal$4$next[0:0]$14221 $1\core_core_core_exc_$signal$4$next[0:0]$14107 - assign $3\core_core_core_exc_$signal$5$next[0:0]$14222 $1\core_core_core_exc_$signal$5$next[0:0]$14108 - assign $3\core_core_core_exc_$signal$6$next[0:0]$14223 $1\core_core_core_exc_$signal$6$next[0:0]$14109 - assign $3\core_core_core_exc_$signal$7$next[0:0]$14224 $1\core_core_core_exc_$signal$7$next[0:0]$14110 - assign $3\core_core_core_exc_$signal$8$next[0:0]$14225 $1\core_core_core_exc_$signal$8$next[0:0]$14111 - assign $3\core_core_core_exc_$signal$9$next[0:0]$14226 $1\core_core_core_exc_$signal$9$next[0:0]$14112 - assign $3\core_core_core_exc_$signal$next[0:0]$14227 $1\core_core_core_exc_$signal$next[0:0]$14113 - assign $3\core_core_core_oe_ok$next[0:0]$14228 $1\core_core_core_oe_ok$next[0:0]$14121 - assign $3\core_core_core_rc_ok$next[0:0]$14229 $1\core_core_core_rc_ok$next[0:0]$14123 - assign $3\core_core_cr_in1_ok$next[0:0]$14230 $1\core_core_cr_in1_ok$next[0:0]$14127 - assign $3\core_core_cr_in2_ok$2$next[0:0]$14231 $1\core_core_cr_in2_ok$2$next[0:0]$14130 - assign $3\core_core_cr_in2_ok$next[0:0]$14232 $1\core_core_cr_in2_ok$next[0:0]$14131 - assign $3\core_core_cr_wr_ok$next[0:0]$14233 $1\core_core_cr_wr_ok$next[0:0]$14133 - assign $3\core_core_fast1_ok$next[0:0]$14234 $1\core_core_fast1_ok$next[0:0]$14136 - assign $3\core_core_fast2_ok$next[0:0]$14235 $1\core_core_fast2_ok$next[0:0]$14138 - assign $3\core_core_reg1_ok$next[0:0]$14236 $1\core_core_reg1_ok$next[0:0]$14143 - assign $3\core_core_reg2_ok$next[0:0]$14237 $1\core_core_reg2_ok$next[0:0]$14145 - assign $3\core_core_reg3_ok$next[0:0]$14238 $1\core_core_reg3_ok$next[0:0]$14147 - assign $3\core_core_spr1_ok$next[0:0]$14239 $1\core_core_spr1_ok$next[0:0]$14150 - assign $3\core_cr_out_ok$next[0:0]$14240 $1\core_cr_out_ok$next[0:0]$14153 - assign $3\core_ea_ok$next[0:0]$14241 $1\core_ea_ok$next[0:0]$14154 - assign $3\core_fasto1_ok$next[0:0]$14242 $1\core_fasto1_ok$next[0:0]$14155 - assign $3\core_fasto2_ok$next[0:0]$14243 $1\core_fasto2_ok$next[0:0]$14156 - assign $3\core_rego_ok$next[0:0]$14244 $1\core_rego_ok$next[0:0]$14157 - assign $3\core_spro_ok$next[0:0]$14245 $1\core_spro_ok$next[0:0]$14158 - end - sync always - update \core_asmcode$next $0\core_asmcode$next[7:0]$14042 - update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$14043 - update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$14044 - update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$14045 - update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$14046 - update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$14047 - update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$14048 - update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$14049 - update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$14050 - update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$14051 - update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$14052 - update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$14053 - update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$14054 - update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$14055 - update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$14056 - update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$14057 - update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$14058 - update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$14059 - update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$14060 - update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$14061 - update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$14062 - update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$14063 - update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$14064 - update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$14065 - update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$14066 - update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$14067 - update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$14068 - update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$14069 - update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$14070 - update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$14071 - update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$14072 - update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$14073 - update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$14074 - update \core_core_ea$next $0\core_core_ea$next[6:0]$14075 - update \core_core_fast1$next $0\core_core_fast1$next[2:0]$14076 - update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$14077 - update \core_core_fast2$next $0\core_core_fast2$next[2:0]$14078 - update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$14079 - update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$14080 - update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$14081 - update \core_core_lk$next $0\core_core_lk$next[0:0]$14082 - update \core_core_reg1$next $0\core_core_reg1$next[6:0]$14083 - update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$14084 - update \core_core_reg2$next $0\core_core_reg2$next[6:0]$14085 - update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$14086 - update \core_core_reg3$next $0\core_core_reg3$next[6:0]$14087 - update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$14088 - update \core_core_rego$next $0\core_core_rego$next[6:0]$14089 - update \core_core_spr1$next $0\core_core_spr1$next[9:0]$14090 - update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$14091 - update \core_core_spro$next $0\core_core_spro$next[9:0]$14092 - update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$14093 - update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$14094 - update \core_ea_ok$next $0\core_ea_ok$next[0:0]$14095 - update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$14096 - update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$14097 - update \core_rego_ok$next $0\core_rego_ok$next[0:0]$14098 - update \core_spro_ok$next $0\core_spro_ok$next[0:0]$14099 - update \core_xer_out$next $0\core_xer_out$next[0:0]$14100 - end - connect \$101 $add$libresoc.v:197083$13545_Y - connect \$103 $mul$libresoc.v:197084$13546_Y - connect \$99 $shr$libresoc.v:197085$13547_Y [31:0] - connect \$106 $not$libresoc.v:197086$13548_Y - connect \$108 $not$libresoc.v:197087$13549_Y - connect \$110 $and$libresoc.v:197088$13550_Y - connect \$112 $not$libresoc.v:197089$13551_Y - connect \$114 $not$libresoc.v:197090$13552_Y - connect \$116 $and$libresoc.v:197091$13553_Y - connect \$118 $or$libresoc.v:197092$13554_Y + assign $2\core_rego_ok$next[0:0]$13766 1'0 + assign $2\core_ea_ok$next[0:0]$13763 1'0 + assign $2\core_core_reg1_ok$next[0:0]$13758 1'0 + assign $2\core_core_reg2_ok$next[0:0]$13759 1'0 + assign $2\core_core_reg3_ok$next[0:0]$13760 1'0 + assign $2\core_spro_ok$next[0:0]$13767 1'0 + assign $2\core_core_spr1_ok$next[0:0]$13761 1'0 + assign $2\core_core_fast1_ok$next[0:0]$13756 1'0 + assign $2\core_core_fast2_ok$next[0:0]$13757 1'0 + assign $2\core_fasto1_ok$next[0:0]$13764 1'0 + assign $2\core_fasto2_ok$next[0:0]$13765 1'0 + assign $2\core_core_cr_in1_ok$next[0:0]$13752 1'0 + assign $2\core_core_cr_in2_ok$next[0:0]$13754 1'0 + assign $2\core_core_cr_in2_ok$2$next[0:0]$13753 1'0 + assign $2\core_cr_out_ok$next[0:0]$13762 1'0 + assign $2\core_core_core_rc_ok$next[0:0]$13751 1'0 + assign $2\core_core_core_oe_ok$next[0:0]$13750 1'0 + assign $2\core_core_core_exc_$signal$next[0:0]$13749 1'0 + assign $2\core_core_core_exc_$signal$3$next[0:0]$13742 1'0 + assign $2\core_core_core_exc_$signal$4$next[0:0]$13743 1'0 + assign $2\core_core_core_exc_$signal$5$next[0:0]$13744 1'0 + assign $2\core_core_core_exc_$signal$6$next[0:0]$13745 1'0 + assign $2\core_core_core_exc_$signal$7$next[0:0]$13746 1'0 + assign $2\core_core_core_exc_$signal$8$next[0:0]$13747 1'0 + assign $2\core_core_core_exc_$signal$9$next[0:0]$13748 1'0 + assign $2\core_core_core_cr_rd_ok$next[0:0]$13741 1'0 + assign $2\core_core_cr_wr_ok$next[0:0]$13755 1'0 + case + assign $2\core_core_core_cr_rd_ok$next[0:0]$13741 $1\core_core_core_cr_rd_ok$next[0:0]$13685 + assign $2\core_core_core_exc_$signal$3$next[0:0]$13742 $1\core_core_core_exc_$signal$3$next[0:0]$13687 + assign $2\core_core_core_exc_$signal$4$next[0:0]$13743 $1\core_core_core_exc_$signal$4$next[0:0]$13688 + assign $2\core_core_core_exc_$signal$5$next[0:0]$13744 $1\core_core_core_exc_$signal$5$next[0:0]$13689 + assign $2\core_core_core_exc_$signal$6$next[0:0]$13745 $1\core_core_core_exc_$signal$6$next[0:0]$13690 + assign $2\core_core_core_exc_$signal$7$next[0:0]$13746 $1\core_core_core_exc_$signal$7$next[0:0]$13691 + assign $2\core_core_core_exc_$signal$8$next[0:0]$13747 $1\core_core_core_exc_$signal$8$next[0:0]$13692 + assign $2\core_core_core_exc_$signal$9$next[0:0]$13748 $1\core_core_core_exc_$signal$9$next[0:0]$13693 + assign $2\core_core_core_exc_$signal$next[0:0]$13749 $1\core_core_core_exc_$signal$next[0:0]$13694 + assign $2\core_core_core_oe_ok$next[0:0]$13750 $1\core_core_core_oe_ok$next[0:0]$13702 + assign $2\core_core_core_rc_ok$next[0:0]$13751 $1\core_core_core_rc_ok$next[0:0]$13704 + assign $2\core_core_cr_in1_ok$next[0:0]$13752 $1\core_core_cr_in1_ok$next[0:0]$13708 + assign $2\core_core_cr_in2_ok$2$next[0:0]$13753 $1\core_core_cr_in2_ok$2$next[0:0]$13711 + assign $2\core_core_cr_in2_ok$next[0:0]$13754 $1\core_core_cr_in2_ok$next[0:0]$13712 + assign $2\core_core_cr_wr_ok$next[0:0]$13755 $1\core_core_cr_wr_ok$next[0:0]$13714 + assign $2\core_core_fast1_ok$next[0:0]$13756 $1\core_core_fast1_ok$next[0:0]$13717 + assign $2\core_core_fast2_ok$next[0:0]$13757 $1\core_core_fast2_ok$next[0:0]$13719 + assign $2\core_core_reg1_ok$next[0:0]$13758 $1\core_core_reg1_ok$next[0:0]$13724 + assign $2\core_core_reg2_ok$next[0:0]$13759 $1\core_core_reg2_ok$next[0:0]$13726 + assign $2\core_core_reg3_ok$next[0:0]$13760 $1\core_core_reg3_ok$next[0:0]$13728 + assign $2\core_core_spr1_ok$next[0:0]$13761 $1\core_core_spr1_ok$next[0:0]$13731 + assign $2\core_cr_out_ok$next[0:0]$13762 $1\core_cr_out_ok$next[0:0]$13734 + assign $2\core_ea_ok$next[0:0]$13763 $1\core_ea_ok$next[0:0]$13735 + assign $2\core_fasto1_ok$next[0:0]$13764 $1\core_fasto1_ok$next[0:0]$13736 + assign $2\core_fasto2_ok$next[0:0]$13765 $1\core_fasto2_ok$next[0:0]$13737 + assign $2\core_rego_ok$next[0:0]$13766 $1\core_rego_ok$next[0:0]$13738 + assign $2\core_spro_ok$next[0:0]$13767 $1\core_spro_ok$next[0:0]$13739 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$13623 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13624 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13625 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13626 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13627 + update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13628 + update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13629 + update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13630 + update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13631 + update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13632 + update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13633 + update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13634 + update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13635 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13636 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13637 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13638 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13639 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13640 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13641 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13642 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13643 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13644 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13645 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13646 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13647 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13648 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13649 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13650 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13651 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13652 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13653 + update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13654 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13655 + update \core_core_ea$next $0\core_core_ea$next[6:0]$13656 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13657 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13658 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13659 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13660 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13661 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13662 + update \core_core_lk$next $0\core_core_lk$next[0:0]$13663 + update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13664 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13665 + update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13666 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13667 + update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13668 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13669 + update \core_core_rego$next $0\core_core_rego$next[6:0]$13670 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13671 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13672 + update \core_core_spro$next $0\core_core_spro$next[9:0]$13673 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13674 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13675 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13676 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13677 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13678 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13679 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13680 + update \core_xer_out$next $0\core_xer_out$next[0:0]$13681 + end + connect \$101 $add$libresoc.v:197878$13139_Y + connect \$103 $mul$libresoc.v:197879$13140_Y + connect \$99 $shr$libresoc.v:197880$13141_Y [31:0] + connect \$106 $not$libresoc.v:197881$13142_Y + connect \$108 $not$libresoc.v:197882$13143_Y + connect \$110 $and$libresoc.v:197883$13144_Y + connect \$112 $not$libresoc.v:197884$13145_Y + connect \$114 $not$libresoc.v:197885$13146_Y + connect \$116 $and$libresoc.v:197886$13147_Y + connect \$118 $or$libresoc.v:197887$13148_Y connect \$120 1'1 - connect \$122 $or$libresoc.v:197094$13555_Y - connect \$125 $add$libresoc.v:197095$13556_Y - connect \$128 $add$libresoc.v:197096$13557_Y - connect \$130 $not$libresoc.v:197097$13558_Y - connect \$132 $not$libresoc.v:197098$13559_Y - connect \$134 $and$libresoc.v:197099$13560_Y - connect \$136 $not$libresoc.v:197100$13561_Y - connect \$138 $not$libresoc.v:197101$13562_Y - connect \$140 $and$libresoc.v:197102$13563_Y - connect \$142 $eq$libresoc.v:197103$13564_Y - connect \$144 $and$libresoc.v:197104$13565_Y - connect \$146 $not$libresoc.v:197105$13566_Y - connect \$148 $not$libresoc.v:197106$13567_Y - connect \$150 $and$libresoc.v:197107$13568_Y - connect \$152 $or$libresoc.v:197108$13569_Y + connect \$122 $or$libresoc.v:197889$13149_Y + connect \$125 $add$libresoc.v:197890$13150_Y + connect \$128 $add$libresoc.v:197891$13151_Y + connect \$130 $not$libresoc.v:197892$13152_Y + connect \$132 $not$libresoc.v:197893$13153_Y + connect \$134 $and$libresoc.v:197894$13154_Y + connect \$136 $not$libresoc.v:197895$13155_Y + connect \$138 $not$libresoc.v:197896$13156_Y + connect \$140 $and$libresoc.v:197897$13157_Y + connect \$142 $eq$libresoc.v:197898$13158_Y + connect \$144 $and$libresoc.v:197899$13159_Y + connect \$146 $not$libresoc.v:197900$13160_Y + connect \$148 $not$libresoc.v:197901$13161_Y + connect \$150 $and$libresoc.v:197902$13162_Y + connect \$152 $or$libresoc.v:197903$13163_Y connect \$154 1'1 - connect \$156 $or$libresoc.v:197110$13570_Y - connect \$158 $not$libresoc.v:197111$13571_Y - connect \$160 $not$libresoc.v:197112$13572_Y - connect \$162 $and$libresoc.v:197113$13573_Y - connect \$164 $not$libresoc.v:197114$13574_Y - connect \$166 $not$libresoc.v:197115$13575_Y - connect \$168 $and$libresoc.v:197116$13576_Y - connect \$170 $not$libresoc.v:197117$13577_Y - connect \$172 $not$libresoc.v:197118$13578_Y - connect \$174 $and$libresoc.v:197119$13579_Y - connect \$176 $not$libresoc.v:197120$13580_Y - connect \$178 $not$libresoc.v:197121$13581_Y - connect \$180 $and$libresoc.v:197122$13582_Y - connect \$182 $not$libresoc.v:197123$13583_Y - connect \$184 $not$libresoc.v:197124$13584_Y - connect \$186 $and$libresoc.v:197125$13585_Y - connect \$188 $not$libresoc.v:197126$13586_Y - connect \$190 $not$libresoc.v:197127$13587_Y - connect \$192 $and$libresoc.v:197128$13588_Y - connect \$195 $and$libresoc.v:197129$13589_Y - connect \$194 $reduce_or$libresoc.v:197130$13590_Y - connect \$198 $not$libresoc.v:197131$13591_Y - connect \$200 $not$libresoc.v:197132$13592_Y - connect \$202 $and$libresoc.v:197133$13593_Y - connect \$204 $not$libresoc.v:197134$13594_Y - connect \$206 $not$libresoc.v:197135$13595_Y - connect \$208 $and$libresoc.v:197136$13596_Y - connect \$210 $or$libresoc.v:197137$13597_Y + connect \$156 $or$libresoc.v:197905$13164_Y + connect \$158 $not$libresoc.v:197906$13165_Y + connect \$160 $not$libresoc.v:197907$13166_Y + connect \$162 $and$libresoc.v:197908$13167_Y + connect \$164 $not$libresoc.v:197909$13168_Y + connect \$166 $not$libresoc.v:197910$13169_Y + connect \$168 $and$libresoc.v:197911$13170_Y + connect \$170 $not$libresoc.v:197912$13171_Y + connect \$172 $not$libresoc.v:197913$13172_Y + connect \$174 $and$libresoc.v:197914$13173_Y + connect \$176 $not$libresoc.v:197915$13174_Y + connect \$178 $not$libresoc.v:197916$13175_Y + connect \$180 $and$libresoc.v:197917$13176_Y + connect \$182 $not$libresoc.v:197918$13177_Y + connect \$184 $not$libresoc.v:197919$13178_Y + connect \$186 $and$libresoc.v:197920$13179_Y + connect \$188 $not$libresoc.v:197921$13180_Y + connect \$190 $not$libresoc.v:197922$13181_Y + connect \$192 $and$libresoc.v:197923$13182_Y + connect \$195 $and$libresoc.v:197924$13183_Y + connect \$194 $reduce_or$libresoc.v:197925$13184_Y + connect \$198 $not$libresoc.v:197926$13185_Y + connect \$200 $not$libresoc.v:197927$13186_Y + connect \$202 $and$libresoc.v:197928$13187_Y + connect \$204 $not$libresoc.v:197929$13188_Y + connect \$206 $not$libresoc.v:197930$13189_Y + connect \$208 $and$libresoc.v:197931$13190_Y + connect \$210 $or$libresoc.v:197932$13191_Y connect \$212 1'1 - connect \$214 $or$libresoc.v:197139$13598_Y - connect \$216 $not$libresoc.v:197140$13599_Y - connect \$218 $not$libresoc.v:197141$13600_Y - connect \$220 $and$libresoc.v:197142$13601_Y - connect \$222 $not$libresoc.v:197143$13602_Y - connect \$224 $not$libresoc.v:197144$13603_Y - connect \$226 $and$libresoc.v:197145$13604_Y - connect \$229 $and$libresoc.v:197146$13605_Y - connect \$228 $reduce_or$libresoc.v:197147$13606_Y - connect \$232 $eq$libresoc.v:197148$13607_Y - connect \$234 $and$libresoc.v:197149$13608_Y - connect \$236 $not$libresoc.v:197150$13609_Y - connect \$238 $not$libresoc.v:197151$13610_Y - connect \$23 $ne$libresoc.v:197152$13611_Y - connect \$240 $not$libresoc.v:197153$13612_Y - connect \$242 $and$libresoc.v:197154$13613_Y - connect \$244 $not$libresoc.v:197155$13614_Y - connect \$246 $not$libresoc.v:197156$13615_Y - connect \$248 $and$libresoc.v:197157$13616_Y - connect \$250 $eq$libresoc.v:197158$13617_Y - connect \$252 $pos$libresoc.v:197159$13618_Y - connect \$254 $ne$libresoc.v:197160$13619_Y - connect \$256 $not$libresoc.v:197161$13620_Y - connect \$258 $not$libresoc.v:197162$13621_Y - connect \$260 $pos$libresoc.v:197163$13623_Y - connect \$262 $pos$libresoc.v:197164$13625_Y - connect \$265 $sub$libresoc.v:197165$13626_Y - connect \$268 $add$libresoc.v:197166$13627_Y - connect \$26 $sub$libresoc.v:197167$13628_Y - connect \$28 $or$libresoc.v:197168$13629_Y - connect \$30 $or$libresoc.v:197169$13630_Y - connect \$32 $ne$libresoc.v:197170$13631_Y - connect \$34 $not$libresoc.v:197171$13632_Y - connect \$36 $and$libresoc.v:197172$13633_Y - connect \$38 $not$libresoc.v:197173$13634_Y - connect \$40 $not$libresoc.v:197174$13635_Y - connect \$42 $pos$libresoc.v:197175$13637_Y - connect \$44 $not$libresoc.v:197176$13638_Y - connect \$46 $not$libresoc.v:197177$13639_Y - connect \$48 $and$libresoc.v:197178$13640_Y - connect \$50 $eq$libresoc.v:197179$13641_Y - connect \$52 $and$libresoc.v:197180$13642_Y - connect \$54 $not$libresoc.v:197181$13643_Y - connect \$56 $not$libresoc.v:197182$13644_Y - connect \$58 $and$libresoc.v:197183$13645_Y - connect \$60 $or$libresoc.v:197184$13646_Y + connect \$214 $or$libresoc.v:197934$13192_Y + connect \$216 $not$libresoc.v:197935$13193_Y + connect \$218 $not$libresoc.v:197936$13194_Y + connect \$220 $and$libresoc.v:197937$13195_Y + connect \$222 $not$libresoc.v:197938$13196_Y + connect \$224 $not$libresoc.v:197939$13197_Y + connect \$226 $and$libresoc.v:197940$13198_Y + connect \$229 $and$libresoc.v:197941$13199_Y + connect \$228 $reduce_or$libresoc.v:197942$13200_Y + connect \$232 $eq$libresoc.v:197943$13201_Y + connect \$234 $and$libresoc.v:197944$13202_Y + connect \$236 $not$libresoc.v:197945$13203_Y + connect \$238 $not$libresoc.v:197946$13204_Y + connect \$23 $ne$libresoc.v:197947$13205_Y + connect \$240 $not$libresoc.v:197948$13206_Y + connect \$242 $and$libresoc.v:197949$13207_Y + connect \$244 $not$libresoc.v:197950$13208_Y + connect \$246 $not$libresoc.v:197951$13209_Y + connect \$248 $and$libresoc.v:197952$13210_Y + connect \$250 $eq$libresoc.v:197953$13211_Y + connect \$252 $pos$libresoc.v:197954$13212_Y + connect \$254 $ne$libresoc.v:197955$13213_Y + connect \$256 $not$libresoc.v:197956$13214_Y + connect \$258 $not$libresoc.v:197957$13215_Y + connect \$260 $pos$libresoc.v:197958$13217_Y + connect \$262 $pos$libresoc.v:197959$13219_Y + connect \$265 $sub$libresoc.v:197960$13220_Y + connect \$268 $add$libresoc.v:197961$13221_Y + connect \$26 $sub$libresoc.v:197962$13222_Y + connect \$28 $or$libresoc.v:197963$13223_Y + connect \$30 $or$libresoc.v:197964$13224_Y + connect \$32 $ne$libresoc.v:197965$13225_Y + connect \$34 $not$libresoc.v:197966$13226_Y + connect \$36 $and$libresoc.v:197967$13227_Y + connect \$38 $not$libresoc.v:197968$13228_Y + connect \$40 $not$libresoc.v:197969$13229_Y + connect \$42 $pos$libresoc.v:197970$13231_Y + connect \$44 $not$libresoc.v:197971$13232_Y + connect \$46 $not$libresoc.v:197972$13233_Y + connect \$48 $and$libresoc.v:197973$13234_Y + connect \$50 $eq$libresoc.v:197974$13235_Y + connect \$52 $and$libresoc.v:197975$13236_Y + connect \$54 $not$libresoc.v:197976$13237_Y + connect \$56 $not$libresoc.v:197977$13238_Y + connect \$58 $and$libresoc.v:197978$13239_Y + connect \$60 $or$libresoc.v:197979$13240_Y connect \$62 1'1 - connect \$64 $or$libresoc.v:197186$13647_Y - connect \$66 $not$libresoc.v:197187$13648_Y - connect \$68 $not$libresoc.v:197188$13649_Y - connect \$70 $and$libresoc.v:197189$13650_Y - connect \$72 $eq$libresoc.v:197190$13651_Y - connect \$74 $and$libresoc.v:197191$13652_Y - connect \$76 $not$libresoc.v:197192$13653_Y - connect \$78 $not$libresoc.v:197193$13654_Y - connect \$80 $and$libresoc.v:197194$13655_Y - connect \$82 $or$libresoc.v:197195$13656_Y + connect \$64 $or$libresoc.v:197981$13241_Y + connect \$66 $not$libresoc.v:197982$13242_Y + connect \$68 $not$libresoc.v:197983$13243_Y + connect \$70 $and$libresoc.v:197984$13244_Y + connect \$72 $eq$libresoc.v:197985$13245_Y + connect \$74 $and$libresoc.v:197986$13246_Y + connect \$76 $not$libresoc.v:197987$13247_Y + connect \$78 $not$libresoc.v:197988$13248_Y + connect \$80 $and$libresoc.v:197989$13249_Y + connect \$82 $or$libresoc.v:197990$13250_Y connect \$84 1'1 - connect \$86 $or$libresoc.v:197197$13657_Y - connect \$88 $not$libresoc.v:197198$13658_Y - connect \$90 $not$libresoc.v:197199$13659_Y - connect \$93 $add$libresoc.v:197200$13660_Y - connect \$96 $mul$libresoc.v:197201$13661_Y - connect \$95 $shr$libresoc.v:197202$13662_Y [31:0] + connect \$86 $or$libresoc.v:197992$13251_Y + connect \$88 $not$libresoc.v:197993$13252_Y + connect \$90 $not$libresoc.v:197994$13253_Y + connect \$93 $add$libresoc.v:197995$13254_Y + connect \$96 $mul$libresoc.v:197996$13255_Y + connect \$95 $shr$libresoc.v:197997$13256_Y [31:0] connect \$25 \$26 connect \$92 \$93 connect \$100 \$101 @@ -416730,485 +381636,485 @@ module \ti connect \sram4k_1_enable \jtag_wb_sram_en connect \sram4k_0_enable \jtag_wb_sram_en end -attribute \src "libresoc.v:199862.1-201053.10" +attribute \src "libresoc.v:200988.1-202179.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" attribute \generator "nMigen" module \trap0 - attribute \src "libresoc.v:200598.3-200599.25" + attribute \src "libresoc.v:201724.3-201725.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:200596.3-200597.41" + attribute \src "libresoc.v:201722.3-201723.41" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:200956.3-200964.6" - wire $0\alu_l_r_alu$next[0:0]$14567 - attribute \src "libresoc.v:200524.3-200525.39" + attribute \src "libresoc.v:202082.3-202090.6" + wire $0\alu_l_r_alu$next[0:0]$14089 + attribute \src "libresoc.v:201650.3-201651.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14493 - attribute \src "libresoc.v:200564.3-200565.61" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14015 + attribute \src "libresoc.v:201690.3-201691.61" wire width 64 $0\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 - attribute \src "libresoc.v:200558.3-200559.69" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14016 + attribute \src "libresoc.v:201684.3-201685.69" wire width 14 $0\alu_trap0_trap_op__fn_unit[13:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14495 - attribute \src "libresoc.v:200560.3-200561.63" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14017 + attribute \src "libresoc.v:201686.3-201687.63" wire width 32 $0\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 - attribute \src "libresoc.v:200556.3-200557.73" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14018 + attribute \src "libresoc.v:201682.3-201683.73" wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 - attribute \src "libresoc.v:200566.3-200567.71" + attribute \src "libresoc.v:201905.3-201922.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14019 + attribute \src "libresoc.v:201692.3-201693.71" wire $0\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 - attribute \src "libresoc.v:200572.3-200573.71" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14020 + attribute \src "libresoc.v:201698.3-201699.71" wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14499 - attribute \src "libresoc.v:200562.3-200563.61" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14021 + attribute \src "libresoc.v:201688.3-201689.61" wire width 64 $0\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 - attribute \src "libresoc.v:200570.3-200571.71" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14022 + attribute \src "libresoc.v:201696.3-201697.71" wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14501 - attribute \src "libresoc.v:200568.3-200569.71" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14023 + attribute \src "libresoc.v:201694.3-201695.71" wire width 8 $0\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:200947.3-200955.6" - wire $0\alui_l_r_alui$next[0:0]$14564 - attribute \src "libresoc.v:200526.3-200527.43" + attribute \src "libresoc.v:202073.3-202081.6" + wire $0\alui_l_r_alui$next[0:0]$14086 + attribute \src "libresoc.v:201652.3-201653.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:200797.3-200818.6" - wire width 64 $0\data_r0__o$next[63:0]$14512 - attribute \src "libresoc.v:200552.3-200553.37" + attribute \src "libresoc.v:201923.3-201944.6" + wire width 64 $0\data_r0__o$next[63:0]$14034 + attribute \src "libresoc.v:201678.3-201679.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:200797.3-200818.6" - wire $0\data_r0__o_ok$next[0:0]$14513 - attribute \src "libresoc.v:200554.3-200555.43" + attribute \src "libresoc.v:201923.3-201944.6" + wire $0\data_r0__o_ok$next[0:0]$14035 + attribute \src "libresoc.v:201680.3-201681.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:200819.3-200840.6" - wire width 64 $0\data_r1__fast1$next[63:0]$14520 - attribute \src "libresoc.v:200548.3-200549.45" + attribute \src "libresoc.v:201945.3-201966.6" + wire width 64 $0\data_r1__fast1$next[63:0]$14042 + attribute \src "libresoc.v:201674.3-201675.45" wire width 64 $0\data_r1__fast1[63:0] - attribute \src "libresoc.v:200819.3-200840.6" - wire $0\data_r1__fast1_ok$next[0:0]$14521 - attribute \src "libresoc.v:200550.3-200551.51" + attribute \src "libresoc.v:201945.3-201966.6" + wire $0\data_r1__fast1_ok$next[0:0]$14043 + attribute \src "libresoc.v:201676.3-201677.51" wire $0\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:200841.3-200862.6" - wire width 64 $0\data_r2__fast2$next[63:0]$14528 - attribute \src "libresoc.v:200544.3-200545.45" + attribute \src "libresoc.v:201967.3-201988.6" + wire width 64 $0\data_r2__fast2$next[63:0]$14050 + attribute \src "libresoc.v:201670.3-201671.45" wire width 64 $0\data_r2__fast2[63:0] - attribute \src "libresoc.v:200841.3-200862.6" - wire $0\data_r2__fast2_ok$next[0:0]$14529 - attribute \src "libresoc.v:200546.3-200547.51" + attribute \src "libresoc.v:201967.3-201988.6" + wire $0\data_r2__fast2_ok$next[0:0]$14051 + attribute \src "libresoc.v:201672.3-201673.51" wire $0\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:200863.3-200884.6" - wire width 64 $0\data_r3__nia$next[63:0]$14536 - attribute \src "libresoc.v:200540.3-200541.41" + attribute \src "libresoc.v:201989.3-202010.6" + wire width 64 $0\data_r3__nia$next[63:0]$14058 + attribute \src "libresoc.v:201666.3-201667.41" wire width 64 $0\data_r3__nia[63:0] - attribute \src "libresoc.v:200863.3-200884.6" - wire $0\data_r3__nia_ok$next[0:0]$14537 - attribute \src "libresoc.v:200542.3-200543.47" + attribute \src "libresoc.v:201989.3-202010.6" + wire $0\data_r3__nia_ok$next[0:0]$14059 + attribute \src "libresoc.v:201668.3-201669.47" wire $0\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:200885.3-200906.6" - wire width 64 $0\data_r4__msr$next[63:0]$14544 - attribute \src "libresoc.v:200536.3-200537.41" + attribute \src "libresoc.v:202011.3-202032.6" + wire width 64 $0\data_r4__msr$next[63:0]$14066 + attribute \src "libresoc.v:201662.3-201663.41" wire width 64 $0\data_r4__msr[63:0] - attribute \src "libresoc.v:200885.3-200906.6" - wire $0\data_r4__msr_ok$next[0:0]$14545 - attribute \src "libresoc.v:200538.3-200539.47" + attribute \src "libresoc.v:202011.3-202032.6" + wire $0\data_r4__msr_ok$next[0:0]$14067 + attribute \src "libresoc.v:201664.3-201665.47" wire $0\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:200965.3-200974.6" + attribute \src "libresoc.v:202091.3-202100.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:200975.3-200984.6" + attribute \src "libresoc.v:202101.3-202110.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:200985.3-200994.6" + attribute \src "libresoc.v:202111.3-202120.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:200995.3-201004.6" + attribute \src "libresoc.v:202121.3-202130.6" wire width 64 $0\dest4_o[63:0] - attribute \src "libresoc.v:201005.3-201014.6" + attribute \src "libresoc.v:202131.3-202140.6" wire width 64 $0\dest5_o[63:0] - attribute \src "libresoc.v:199863.7-199863.20" + attribute \src "libresoc.v:200989.7-200989.20" wire $0\initial[0:0] - attribute \src "libresoc.v:200734.3-200742.6" - wire $0\opc_l_r_opc$next[0:0]$14478 - attribute \src "libresoc.v:200582.3-200583.39" + attribute \src "libresoc.v:201860.3-201868.6" + wire $0\opc_l_r_opc$next[0:0]$14000 + attribute \src "libresoc.v:201708.3-201709.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:200725.3-200733.6" - wire $0\opc_l_s_opc$next[0:0]$14475 - attribute \src "libresoc.v:200584.3-200585.39" + attribute \src "libresoc.v:201851.3-201859.6" + wire $0\opc_l_s_opc$next[0:0]$13997 + attribute \src "libresoc.v:201710.3-201711.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:201015.3-201023.6" - wire width 5 $0\prev_wr_go$next[4:0]$14575 - attribute \src "libresoc.v:200594.3-200595.37" + attribute \src "libresoc.v:202141.3-202149.6" + wire width 5 $0\prev_wr_go$next[4:0]$14097 + attribute \src "libresoc.v:201720.3-201721.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:200679.3-200688.6" + attribute \src "libresoc.v:201805.3-201814.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:200770.3-200778.6" - wire width 5 $0\req_l_r_req$next[4:0]$14490 - attribute \src "libresoc.v:200574.3-200575.39" + attribute \src "libresoc.v:201896.3-201904.6" + wire width 5 $0\req_l_r_req$next[4:0]$14012 + attribute \src "libresoc.v:201700.3-201701.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:200761.3-200769.6" - wire width 5 $0\req_l_s_req$next[4:0]$14487 - attribute \src "libresoc.v:200576.3-200577.39" + attribute \src "libresoc.v:201887.3-201895.6" + wire width 5 $0\req_l_s_req$next[4:0]$14009 + attribute \src "libresoc.v:201702.3-201703.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:200698.3-200706.6" - wire $0\rok_l_r_rdok$next[0:0]$14466 - attribute \src "libresoc.v:200590.3-200591.41" + attribute \src "libresoc.v:201824.3-201832.6" + wire $0\rok_l_r_rdok$next[0:0]$13988 + attribute \src "libresoc.v:201716.3-201717.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:200689.3-200697.6" - wire $0\rok_l_s_rdok$next[0:0]$14463 - attribute \src "libresoc.v:200592.3-200593.41" + attribute \src "libresoc.v:201815.3-201823.6" + wire $0\rok_l_s_rdok$next[0:0]$13985 + attribute \src "libresoc.v:201718.3-201719.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:200716.3-200724.6" - wire $0\rst_l_r_rst$next[0:0]$14472 - attribute \src "libresoc.v:200586.3-200587.39" + attribute \src "libresoc.v:201842.3-201850.6" + wire $0\rst_l_r_rst$next[0:0]$13994 + attribute \src "libresoc.v:201712.3-201713.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:200707.3-200715.6" - wire $0\rst_l_s_rst$next[0:0]$14469 - attribute \src "libresoc.v:200588.3-200589.39" + attribute \src "libresoc.v:201833.3-201841.6" + wire $0\rst_l_s_rst$next[0:0]$13991 + attribute \src "libresoc.v:201714.3-201715.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:200752.3-200760.6" - wire width 4 $0\src_l_r_src$next[3:0]$14484 - attribute \src "libresoc.v:200578.3-200579.39" + attribute \src "libresoc.v:201878.3-201886.6" + wire width 4 $0\src_l_r_src$next[3:0]$14006 + attribute \src "libresoc.v:201704.3-201705.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:200743.3-200751.6" - wire width 4 $0\src_l_s_src$next[3:0]$14481 - attribute \src "libresoc.v:200580.3-200581.39" + attribute \src "libresoc.v:201869.3-201877.6" + wire width 4 $0\src_l_s_src$next[3:0]$14003 + attribute \src "libresoc.v:201706.3-201707.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:200907.3-200916.6" - wire width 64 $0\src_r0$next[63:0]$14552 - attribute \src "libresoc.v:200534.3-200535.29" + attribute \src "libresoc.v:202033.3-202042.6" + wire width 64 $0\src_r0$next[63:0]$14074 + attribute \src "libresoc.v:201660.3-201661.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:200917.3-200926.6" - wire width 64 $0\src_r1$next[63:0]$14555 - attribute \src "libresoc.v:200532.3-200533.29" + attribute \src "libresoc.v:202043.3-202052.6" + wire width 64 $0\src_r1$next[63:0]$14077 + attribute \src "libresoc.v:201658.3-201659.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:200927.3-200936.6" - wire width 64 $0\src_r2$next[63:0]$14558 - attribute \src "libresoc.v:200530.3-200531.29" + attribute \src "libresoc.v:202053.3-202062.6" + wire width 64 $0\src_r2$next[63:0]$14080 + attribute \src "libresoc.v:201656.3-201657.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:200937.3-200946.6" - wire width 64 $0\src_r3$next[63:0]$14561 - attribute \src "libresoc.v:200528.3-200529.29" + attribute \src "libresoc.v:202063.3-202072.6" + wire width 64 $0\src_r3$next[63:0]$14083 + attribute \src "libresoc.v:201654.3-201655.29" wire width 64 $0\src_r3[63:0] - attribute \src "libresoc.v:199989.7-199989.24" + attribute \src "libresoc.v:201115.7-201115.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:199999.7-199999.26" + attribute \src "libresoc.v:201125.7-201125.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:200956.3-200964.6" - wire $1\alu_l_r_alu$next[0:0]$14568 - attribute \src "libresoc.v:200007.7-200007.25" + attribute \src "libresoc.v:202082.3-202090.6" + wire $1\alu_l_r_alu$next[0:0]$14090 + attribute \src "libresoc.v:201133.7-201133.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14502 - attribute \src "libresoc.v:200043.14-200043.59" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14024 + attribute \src "libresoc.v:201169.14-201169.59" wire width 64 $1\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 - attribute \src "libresoc.v:200062.14-200062.51" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14025 + attribute \src "libresoc.v:201188.14-201188.51" wire width 14 $1\alu_trap0_trap_op__fn_unit[13:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14504 - attribute \src "libresoc.v:200066.14-200066.45" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14026 + attribute \src "libresoc.v:201192.14-201192.45" wire width 32 $1\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 - attribute \src "libresoc.v:200145.13-200145.49" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14027 + attribute \src "libresoc.v:201271.13-201271.49" wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 - attribute \src "libresoc.v:200149.7-200149.41" + attribute \src "libresoc.v:201905.3-201922.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14028 + attribute \src "libresoc.v:201275.7-201275.41" wire $1\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 - attribute \src "libresoc.v:200153.13-200153.48" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14029 + attribute \src "libresoc.v:201279.13-201279.48" wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14508 - attribute \src "libresoc.v:200157.14-200157.59" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14030 + attribute \src "libresoc.v:201283.14-201283.59" wire width 64 $1\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 - attribute \src "libresoc.v:200161.14-200161.52" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14031 + attribute \src "libresoc.v:201287.14-201287.52" wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14510 - attribute \src "libresoc.v:200165.13-200165.48" + attribute \src "libresoc.v:201905.3-201922.6" + wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14032 + attribute \src "libresoc.v:201291.13-201291.48" wire width 8 $1\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:200947.3-200955.6" - wire $1\alui_l_r_alui$next[0:0]$14565 - attribute \src "libresoc.v:200171.7-200171.27" + attribute \src "libresoc.v:202073.3-202081.6" + wire $1\alui_l_r_alui$next[0:0]$14087 + attribute \src "libresoc.v:201297.7-201297.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:200797.3-200818.6" - wire width 64 $1\data_r0__o$next[63:0]$14514 - attribute \src "libresoc.v:200203.14-200203.47" + attribute \src "libresoc.v:201923.3-201944.6" + wire width 64 $1\data_r0__o$next[63:0]$14036 + attribute \src "libresoc.v:201329.14-201329.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:200797.3-200818.6" - wire $1\data_r0__o_ok$next[0:0]$14515 - attribute \src "libresoc.v:200207.7-200207.27" + attribute \src "libresoc.v:201923.3-201944.6" + wire $1\data_r0__o_ok$next[0:0]$14037 + attribute \src "libresoc.v:201333.7-201333.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:200819.3-200840.6" - wire width 64 $1\data_r1__fast1$next[63:0]$14522 - attribute \src "libresoc.v:200211.14-200211.51" + attribute \src "libresoc.v:201945.3-201966.6" + wire width 64 $1\data_r1__fast1$next[63:0]$14044 + attribute \src "libresoc.v:201337.14-201337.51" wire width 64 $1\data_r1__fast1[63:0] - attribute \src "libresoc.v:200819.3-200840.6" - wire $1\data_r1__fast1_ok$next[0:0]$14523 - attribute \src "libresoc.v:200215.7-200215.31" + attribute \src "libresoc.v:201945.3-201966.6" + wire $1\data_r1__fast1_ok$next[0:0]$14045 + attribute \src "libresoc.v:201341.7-201341.31" wire $1\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:200841.3-200862.6" - wire width 64 $1\data_r2__fast2$next[63:0]$14530 - attribute \src "libresoc.v:200219.14-200219.51" + attribute \src "libresoc.v:201967.3-201988.6" + wire width 64 $1\data_r2__fast2$next[63:0]$14052 + attribute \src "libresoc.v:201345.14-201345.51" wire width 64 $1\data_r2__fast2[63:0] - attribute \src "libresoc.v:200841.3-200862.6" - wire $1\data_r2__fast2_ok$next[0:0]$14531 - attribute \src "libresoc.v:200223.7-200223.31" + attribute \src "libresoc.v:201967.3-201988.6" + wire $1\data_r2__fast2_ok$next[0:0]$14053 + attribute \src "libresoc.v:201349.7-201349.31" wire $1\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:200863.3-200884.6" - wire width 64 $1\data_r3__nia$next[63:0]$14538 - attribute \src "libresoc.v:200227.14-200227.49" + attribute \src "libresoc.v:201989.3-202010.6" + wire width 64 $1\data_r3__nia$next[63:0]$14060 + attribute \src "libresoc.v:201353.14-201353.49" wire width 64 $1\data_r3__nia[63:0] - attribute \src "libresoc.v:200863.3-200884.6" - wire $1\data_r3__nia_ok$next[0:0]$14539 - attribute \src "libresoc.v:200231.7-200231.29" + attribute \src "libresoc.v:201989.3-202010.6" + wire $1\data_r3__nia_ok$next[0:0]$14061 + attribute \src "libresoc.v:201357.7-201357.29" wire $1\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:200885.3-200906.6" - wire width 64 $1\data_r4__msr$next[63:0]$14546 - attribute \src "libresoc.v:200235.14-200235.49" + attribute \src "libresoc.v:202011.3-202032.6" + wire width 64 $1\data_r4__msr$next[63:0]$14068 + attribute \src "libresoc.v:201361.14-201361.49" wire width 64 $1\data_r4__msr[63:0] - attribute \src "libresoc.v:200885.3-200906.6" - wire $1\data_r4__msr_ok$next[0:0]$14547 - attribute \src "libresoc.v:200239.7-200239.29" + attribute \src "libresoc.v:202011.3-202032.6" + wire $1\data_r4__msr_ok$next[0:0]$14069 + attribute \src "libresoc.v:201365.7-201365.29" wire $1\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:200965.3-200974.6" + attribute \src "libresoc.v:202091.3-202100.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:200975.3-200984.6" + attribute \src "libresoc.v:202101.3-202110.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:200985.3-200994.6" + attribute \src "libresoc.v:202111.3-202120.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:200995.3-201004.6" + attribute \src "libresoc.v:202121.3-202130.6" wire width 64 $1\dest4_o[63:0] - attribute \src "libresoc.v:201005.3-201014.6" + attribute \src "libresoc.v:202131.3-202140.6" wire width 64 $1\dest5_o[63:0] - attribute \src "libresoc.v:200734.3-200742.6" - wire $1\opc_l_r_opc$next[0:0]$14479 - attribute \src "libresoc.v:200270.7-200270.25" + attribute \src "libresoc.v:201860.3-201868.6" + wire $1\opc_l_r_opc$next[0:0]$14001 + attribute \src "libresoc.v:201396.7-201396.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:200725.3-200733.6" - wire $1\opc_l_s_opc$next[0:0]$14476 - attribute \src "libresoc.v:200274.7-200274.25" + attribute \src "libresoc.v:201851.3-201859.6" + wire $1\opc_l_s_opc$next[0:0]$13998 + attribute \src "libresoc.v:201400.7-201400.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:201015.3-201023.6" - wire width 5 $1\prev_wr_go$next[4:0]$14576 - attribute \src "libresoc.v:200386.13-200386.31" + attribute \src "libresoc.v:202141.3-202149.6" + wire width 5 $1\prev_wr_go$next[4:0]$14098 + attribute \src "libresoc.v:201512.13-201512.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:200679.3-200688.6" + attribute \src "libresoc.v:201805.3-201814.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:200770.3-200778.6" - wire width 5 $1\req_l_r_req$next[4:0]$14491 - attribute \src "libresoc.v:200394.13-200394.32" + attribute \src "libresoc.v:201896.3-201904.6" + wire width 5 $1\req_l_r_req$next[4:0]$14013 + attribute \src "libresoc.v:201520.13-201520.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:200761.3-200769.6" - wire width 5 $1\req_l_s_req$next[4:0]$14488 - attribute \src "libresoc.v:200398.13-200398.32" + attribute \src "libresoc.v:201887.3-201895.6" + wire width 5 $1\req_l_s_req$next[4:0]$14010 + attribute \src "libresoc.v:201524.13-201524.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:200698.3-200706.6" - wire $1\rok_l_r_rdok$next[0:0]$14467 - attribute \src "libresoc.v:200410.7-200410.26" + attribute \src "libresoc.v:201824.3-201832.6" + wire $1\rok_l_r_rdok$next[0:0]$13989 + attribute \src "libresoc.v:201536.7-201536.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:200689.3-200697.6" - wire $1\rok_l_s_rdok$next[0:0]$14464 - attribute \src "libresoc.v:200414.7-200414.26" + attribute \src "libresoc.v:201815.3-201823.6" + wire $1\rok_l_s_rdok$next[0:0]$13986 + attribute \src "libresoc.v:201540.7-201540.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:200716.3-200724.6" - wire $1\rst_l_r_rst$next[0:0]$14473 - attribute \src "libresoc.v:200418.7-200418.25" + attribute \src "libresoc.v:201842.3-201850.6" + wire $1\rst_l_r_rst$next[0:0]$13995 + attribute \src "libresoc.v:201544.7-201544.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:200707.3-200715.6" - wire $1\rst_l_s_rst$next[0:0]$14470 - attribute \src "libresoc.v:200422.7-200422.25" + attribute \src "libresoc.v:201833.3-201841.6" + wire $1\rst_l_s_rst$next[0:0]$13992 + attribute \src "libresoc.v:201548.7-201548.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:200752.3-200760.6" - wire width 4 $1\src_l_r_src$next[3:0]$14485 - attribute \src "libresoc.v:200438.13-200438.31" + attribute \src "libresoc.v:201878.3-201886.6" + wire width 4 $1\src_l_r_src$next[3:0]$14007 + attribute \src "libresoc.v:201564.13-201564.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:200743.3-200751.6" - wire width 4 $1\src_l_s_src$next[3:0]$14482 - attribute \src "libresoc.v:200442.13-200442.31" + attribute \src "libresoc.v:201869.3-201877.6" + wire width 4 $1\src_l_s_src$next[3:0]$14004 + attribute \src "libresoc.v:201568.13-201568.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:200907.3-200916.6" - wire width 64 $1\src_r0$next[63:0]$14553 - attribute \src "libresoc.v:200446.14-200446.43" + attribute \src "libresoc.v:202033.3-202042.6" + wire width 64 $1\src_r0$next[63:0]$14075 + attribute \src "libresoc.v:201572.14-201572.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:200917.3-200926.6" - wire width 64 $1\src_r1$next[63:0]$14556 - attribute \src "libresoc.v:200450.14-200450.43" + attribute \src "libresoc.v:202043.3-202052.6" + wire width 64 $1\src_r1$next[63:0]$14078 + attribute \src "libresoc.v:201576.14-201576.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:200927.3-200936.6" - wire width 64 $1\src_r2$next[63:0]$14559 - attribute \src "libresoc.v:200454.14-200454.43" + attribute \src "libresoc.v:202053.3-202062.6" + wire width 64 $1\src_r2$next[63:0]$14081 + attribute \src "libresoc.v:201580.14-201580.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:200937.3-200946.6" - wire width 64 $1\src_r3$next[63:0]$14562 - attribute \src "libresoc.v:200458.14-200458.43" + attribute \src "libresoc.v:202063.3-202072.6" + wire width 64 $1\src_r3$next[63:0]$14084 + attribute \src "libresoc.v:201584.14-201584.43" wire width 64 $1\src_r3[63:0] - attribute \src "libresoc.v:200797.3-200818.6" - wire width 64 $2\data_r0__o$next[63:0]$14516 - attribute \src "libresoc.v:200797.3-200818.6" - wire $2\data_r0__o_ok$next[0:0]$14517 - attribute \src "libresoc.v:200819.3-200840.6" - wire width 64 $2\data_r1__fast1$next[63:0]$14524 - attribute \src "libresoc.v:200819.3-200840.6" - wire $2\data_r1__fast1_ok$next[0:0]$14525 - attribute \src "libresoc.v:200841.3-200862.6" - wire width 64 $2\data_r2__fast2$next[63:0]$14532 - attribute \src "libresoc.v:200841.3-200862.6" - wire $2\data_r2__fast2_ok$next[0:0]$14533 - attribute \src "libresoc.v:200863.3-200884.6" - wire width 64 $2\data_r3__nia$next[63:0]$14540 - attribute \src "libresoc.v:200863.3-200884.6" - wire $2\data_r3__nia_ok$next[0:0]$14541 - attribute \src "libresoc.v:200885.3-200906.6" - wire width 64 $2\data_r4__msr$next[63:0]$14548 - attribute \src "libresoc.v:200885.3-200906.6" - wire $2\data_r4__msr_ok$next[0:0]$14549 - attribute \src "libresoc.v:200797.3-200818.6" - wire $3\data_r0__o_ok$next[0:0]$14518 - attribute \src "libresoc.v:200819.3-200840.6" - wire $3\data_r1__fast1_ok$next[0:0]$14526 - attribute \src "libresoc.v:200841.3-200862.6" - wire $3\data_r2__fast2_ok$next[0:0]$14534 - attribute \src "libresoc.v:200863.3-200884.6" - wire $3\data_r3__nia_ok$next[0:0]$14542 - attribute \src "libresoc.v:200885.3-200906.6" - wire $3\data_r4__msr_ok$next[0:0]$14550 - attribute \src "libresoc.v:200464.18-200464.112" - wire width 4 $and$libresoc.v:200464$14363_Y - attribute \src "libresoc.v:200465.19-200465.125" - wire $and$libresoc.v:200465$14364_Y - attribute \src "libresoc.v:200466.19-200466.125" - wire $and$libresoc.v:200466$14365_Y - attribute \src "libresoc.v:200467.19-200467.125" - wire $and$libresoc.v:200467$14366_Y - attribute \src "libresoc.v:200468.19-200468.125" - wire $and$libresoc.v:200468$14367_Y - attribute \src "libresoc.v:200469.19-200469.125" - wire $and$libresoc.v:200469$14368_Y - attribute \src "libresoc.v:200470.19-200470.157" - wire width 5 $and$libresoc.v:200470$14369_Y - attribute \src "libresoc.v:200471.19-200471.121" - wire width 5 $and$libresoc.v:200471$14370_Y - attribute \src "libresoc.v:200472.19-200472.127" - wire $and$libresoc.v:200472$14371_Y - attribute \src "libresoc.v:200473.19-200473.127" - wire $and$libresoc.v:200473$14372_Y - attribute \src "libresoc.v:200474.18-200474.110" - wire $and$libresoc.v:200474$14373_Y - attribute \src "libresoc.v:200475.19-200475.127" - wire $and$libresoc.v:200475$14374_Y - attribute \src "libresoc.v:200476.19-200476.127" - wire $and$libresoc.v:200476$14375_Y - attribute \src "libresoc.v:200477.19-200477.127" - wire $and$libresoc.v:200477$14376_Y - attribute \src "libresoc.v:200479.18-200479.98" - wire $and$libresoc.v:200479$14378_Y - attribute \src "libresoc.v:200481.18-200481.100" - wire $and$libresoc.v:200481$14380_Y - attribute \src "libresoc.v:200482.18-200482.171" - wire width 5 $and$libresoc.v:200482$14381_Y - attribute \src "libresoc.v:200484.18-200484.119" - wire width 5 $and$libresoc.v:200484$14383_Y - attribute \src "libresoc.v:200487.18-200487.116" - wire $and$libresoc.v:200487$14386_Y - attribute \src "libresoc.v:200491.17-200491.123" - wire $and$libresoc.v:200491$14390_Y - attribute \src "libresoc.v:200493.18-200493.113" - wire $and$libresoc.v:200493$14392_Y - attribute \src "libresoc.v:200494.18-200494.125" - wire width 5 $and$libresoc.v:200494$14393_Y - attribute \src "libresoc.v:200496.18-200496.112" - wire $and$libresoc.v:200496$14395_Y - attribute \src "libresoc.v:200498.18-200498.127" - wire $and$libresoc.v:200498$14397_Y - attribute \src "libresoc.v:200499.18-200499.127" - wire $and$libresoc.v:200499$14398_Y - attribute \src "libresoc.v:200500.18-200500.117" - wire $and$libresoc.v:200500$14399_Y - attribute \src "libresoc.v:200505.18-200505.131" - wire $and$libresoc.v:200505$14404_Y - attribute \src "libresoc.v:200506.18-200506.124" - wire width 5 $and$libresoc.v:200506$14405_Y - attribute \src "libresoc.v:200509.18-200509.116" - wire $and$libresoc.v:200509$14408_Y - attribute \src "libresoc.v:200510.18-200510.120" - wire $and$libresoc.v:200510$14409_Y - attribute \src "libresoc.v:200511.18-200511.120" - wire $and$libresoc.v:200511$14410_Y - attribute \src "libresoc.v:200512.18-200512.118" - wire $and$libresoc.v:200512$14411_Y - attribute \src "libresoc.v:200513.18-200513.118" - wire $and$libresoc.v:200513$14412_Y - attribute \src "libresoc.v:200519.18-200519.135" - wire $and$libresoc.v:200519$14418_Y - attribute \src "libresoc.v:200520.18-200520.133" - wire $and$libresoc.v:200520$14419_Y - attribute \src "libresoc.v:200521.18-200521.160" - wire width 4 $and$libresoc.v:200521$14420_Y - attribute \src "libresoc.v:200522.18-200522.112" - wire width 4 $and$libresoc.v:200522$14421_Y - attribute \src "libresoc.v:200495.18-200495.113" - wire $eq$libresoc.v:200495$14394_Y - attribute \src "libresoc.v:200497.18-200497.119" - wire $eq$libresoc.v:200497$14396_Y - attribute \src "libresoc.v:200478.18-200478.97" - wire $not$libresoc.v:200478$14377_Y - attribute \src "libresoc.v:200480.18-200480.99" - wire $not$libresoc.v:200480$14379_Y - attribute \src "libresoc.v:200483.18-200483.113" - wire width 5 $not$libresoc.v:200483$14382_Y - attribute \src "libresoc.v:200486.18-200486.106" - wire $not$libresoc.v:200486$14385_Y - attribute \src "libresoc.v:200492.18-200492.121" - wire $not$libresoc.v:200492$14391_Y - attribute \src "libresoc.v:200507.17-200507.113" - wire width 4 $not$libresoc.v:200507$14406_Y - attribute \src "libresoc.v:200523.18-200523.114" - wire width 4 $not$libresoc.v:200523$14422_Y - attribute \src "libresoc.v:200490.18-200490.112" - wire $or$libresoc.v:200490$14389_Y - attribute \src "libresoc.v:200501.18-200501.122" - wire $or$libresoc.v:200501$14400_Y - attribute \src "libresoc.v:200502.18-200502.124" - wire $or$libresoc.v:200502$14401_Y - attribute \src "libresoc.v:200503.18-200503.181" - wire width 5 $or$libresoc.v:200503$14402_Y - attribute \src "libresoc.v:200504.18-200504.168" - wire width 4 $or$libresoc.v:200504$14403_Y - attribute \src "libresoc.v:200508.18-200508.120" - wire width 5 $or$libresoc.v:200508$14407_Y - attribute \src "libresoc.v:200518.17-200518.117" - wire width 4 $or$libresoc.v:200518$14417_Y - attribute \src "libresoc.v:200463.17-200463.104" - wire $reduce_and$libresoc.v:200463$14362_Y - attribute \src "libresoc.v:200485.18-200485.106" - wire $reduce_or$libresoc.v:200485$14384_Y - attribute \src "libresoc.v:200488.18-200488.113" - wire $reduce_or$libresoc.v:200488$14387_Y - attribute \src "libresoc.v:200489.18-200489.112" - wire $reduce_or$libresoc.v:200489$14388_Y - attribute \src "libresoc.v:200514.18-200514.118" - wire width 64 $ternary$libresoc.v:200514$14413_Y - attribute \src "libresoc.v:200515.18-200515.118" - wire width 64 $ternary$libresoc.v:200515$14414_Y - attribute \src "libresoc.v:200516.18-200516.118" - wire width 64 $ternary$libresoc.v:200516$14415_Y - attribute \src "libresoc.v:200517.18-200517.118" - wire width 64 $ternary$libresoc.v:200517$14416_Y + attribute \src "libresoc.v:201923.3-201944.6" + wire width 64 $2\data_r0__o$next[63:0]$14038 + attribute \src "libresoc.v:201923.3-201944.6" + wire $2\data_r0__o_ok$next[0:0]$14039 + attribute \src "libresoc.v:201945.3-201966.6" + wire width 64 $2\data_r1__fast1$next[63:0]$14046 + attribute \src "libresoc.v:201945.3-201966.6" + wire $2\data_r1__fast1_ok$next[0:0]$14047 + attribute \src "libresoc.v:201967.3-201988.6" + wire width 64 $2\data_r2__fast2$next[63:0]$14054 + attribute \src "libresoc.v:201967.3-201988.6" + wire $2\data_r2__fast2_ok$next[0:0]$14055 + attribute \src "libresoc.v:201989.3-202010.6" + wire width 64 $2\data_r3__nia$next[63:0]$14062 + attribute \src "libresoc.v:201989.3-202010.6" + wire $2\data_r3__nia_ok$next[0:0]$14063 + attribute \src "libresoc.v:202011.3-202032.6" + wire width 64 $2\data_r4__msr$next[63:0]$14070 + attribute \src "libresoc.v:202011.3-202032.6" + wire $2\data_r4__msr_ok$next[0:0]$14071 + attribute \src "libresoc.v:201923.3-201944.6" + wire $3\data_r0__o_ok$next[0:0]$14040 + attribute \src "libresoc.v:201945.3-201966.6" + wire $3\data_r1__fast1_ok$next[0:0]$14048 + attribute \src "libresoc.v:201967.3-201988.6" + wire $3\data_r2__fast2_ok$next[0:0]$14056 + attribute \src "libresoc.v:201989.3-202010.6" + wire $3\data_r3__nia_ok$next[0:0]$14064 + attribute \src "libresoc.v:202011.3-202032.6" + wire $3\data_r4__msr_ok$next[0:0]$14072 + attribute \src "libresoc.v:201590.18-201590.112" + wire width 4 $and$libresoc.v:201590$13885_Y + attribute \src "libresoc.v:201591.19-201591.125" + wire $and$libresoc.v:201591$13886_Y + attribute \src "libresoc.v:201592.19-201592.125" + wire $and$libresoc.v:201592$13887_Y + attribute \src "libresoc.v:201593.19-201593.125" + wire $and$libresoc.v:201593$13888_Y + attribute \src "libresoc.v:201594.19-201594.125" + wire $and$libresoc.v:201594$13889_Y + attribute \src "libresoc.v:201595.19-201595.125" + wire $and$libresoc.v:201595$13890_Y + attribute \src "libresoc.v:201596.19-201596.157" + wire width 5 $and$libresoc.v:201596$13891_Y + attribute \src "libresoc.v:201597.19-201597.121" + wire width 5 $and$libresoc.v:201597$13892_Y + attribute \src "libresoc.v:201598.19-201598.127" + wire $and$libresoc.v:201598$13893_Y + attribute \src "libresoc.v:201599.19-201599.127" + wire $and$libresoc.v:201599$13894_Y + attribute \src "libresoc.v:201600.18-201600.110" + wire $and$libresoc.v:201600$13895_Y + attribute \src "libresoc.v:201601.19-201601.127" + wire $and$libresoc.v:201601$13896_Y + attribute \src "libresoc.v:201602.19-201602.127" + wire $and$libresoc.v:201602$13897_Y + attribute \src "libresoc.v:201603.19-201603.127" + wire $and$libresoc.v:201603$13898_Y + attribute \src "libresoc.v:201605.18-201605.98" + wire $and$libresoc.v:201605$13900_Y + attribute \src "libresoc.v:201607.18-201607.100" + wire $and$libresoc.v:201607$13902_Y + attribute \src "libresoc.v:201608.18-201608.171" + wire width 5 $and$libresoc.v:201608$13903_Y + attribute \src "libresoc.v:201610.18-201610.119" + wire width 5 $and$libresoc.v:201610$13905_Y + attribute \src "libresoc.v:201613.18-201613.116" + wire $and$libresoc.v:201613$13908_Y + attribute \src "libresoc.v:201617.17-201617.123" + wire $and$libresoc.v:201617$13912_Y + attribute \src "libresoc.v:201619.18-201619.113" + wire $and$libresoc.v:201619$13914_Y + attribute \src "libresoc.v:201620.18-201620.125" + wire width 5 $and$libresoc.v:201620$13915_Y + attribute \src "libresoc.v:201622.18-201622.112" + wire $and$libresoc.v:201622$13917_Y + attribute \src "libresoc.v:201624.18-201624.127" + wire $and$libresoc.v:201624$13919_Y + attribute \src "libresoc.v:201625.18-201625.127" + wire $and$libresoc.v:201625$13920_Y + attribute \src "libresoc.v:201626.18-201626.117" + wire $and$libresoc.v:201626$13921_Y + attribute \src "libresoc.v:201631.18-201631.131" + wire $and$libresoc.v:201631$13926_Y + attribute \src "libresoc.v:201632.18-201632.124" + wire width 5 $and$libresoc.v:201632$13927_Y + attribute \src "libresoc.v:201635.18-201635.116" + wire $and$libresoc.v:201635$13930_Y + attribute \src "libresoc.v:201636.18-201636.120" + wire $and$libresoc.v:201636$13931_Y + attribute \src "libresoc.v:201637.18-201637.120" + wire $and$libresoc.v:201637$13932_Y + attribute \src "libresoc.v:201638.18-201638.118" + wire $and$libresoc.v:201638$13933_Y + attribute \src "libresoc.v:201639.18-201639.118" + wire $and$libresoc.v:201639$13934_Y + attribute \src "libresoc.v:201645.18-201645.135" + wire $and$libresoc.v:201645$13940_Y + attribute \src "libresoc.v:201646.18-201646.133" + wire $and$libresoc.v:201646$13941_Y + attribute \src "libresoc.v:201647.18-201647.160" + wire width 4 $and$libresoc.v:201647$13942_Y + attribute \src "libresoc.v:201648.18-201648.112" + wire width 4 $and$libresoc.v:201648$13943_Y + attribute \src "libresoc.v:201621.18-201621.113" + wire $eq$libresoc.v:201621$13916_Y + attribute \src "libresoc.v:201623.18-201623.119" + wire $eq$libresoc.v:201623$13918_Y + attribute \src "libresoc.v:201604.18-201604.97" + wire $not$libresoc.v:201604$13899_Y + attribute \src "libresoc.v:201606.18-201606.99" + wire $not$libresoc.v:201606$13901_Y + attribute \src "libresoc.v:201609.18-201609.113" + wire width 5 $not$libresoc.v:201609$13904_Y + attribute \src "libresoc.v:201612.18-201612.106" + wire $not$libresoc.v:201612$13907_Y + attribute \src "libresoc.v:201618.18-201618.121" + wire $not$libresoc.v:201618$13913_Y + attribute \src "libresoc.v:201633.17-201633.113" + wire width 4 $not$libresoc.v:201633$13928_Y + attribute \src "libresoc.v:201649.18-201649.114" + wire width 4 $not$libresoc.v:201649$13944_Y + attribute \src "libresoc.v:201616.18-201616.112" + wire $or$libresoc.v:201616$13911_Y + attribute \src "libresoc.v:201627.18-201627.122" + wire $or$libresoc.v:201627$13922_Y + attribute \src "libresoc.v:201628.18-201628.124" + wire $or$libresoc.v:201628$13923_Y + attribute \src "libresoc.v:201629.18-201629.181" + wire width 5 $or$libresoc.v:201629$13924_Y + attribute \src "libresoc.v:201630.18-201630.168" + wire width 4 $or$libresoc.v:201630$13925_Y + attribute \src "libresoc.v:201634.18-201634.120" + wire width 5 $or$libresoc.v:201634$13929_Y + attribute \src "libresoc.v:201644.17-201644.117" + wire width 4 $or$libresoc.v:201644$13939_Y + attribute \src "libresoc.v:201589.17-201589.104" + wire $reduce_and$libresoc.v:201589$13884_Y + attribute \src "libresoc.v:201611.18-201611.106" + wire $reduce_or$libresoc.v:201611$13906_Y + attribute \src "libresoc.v:201614.18-201614.113" + wire $reduce_or$libresoc.v:201614$13909_Y + attribute \src "libresoc.v:201615.18-201615.112" + wire $reduce_or$libresoc.v:201615$13910_Y + attribute \src "libresoc.v:201640.18-201640.118" + wire width 64 $ternary$libresoc.v:201640$13935_Y + attribute \src "libresoc.v:201641.18-201641.118" + wire width 64 $ternary$libresoc.v:201641$13936_Y + attribute \src "libresoc.v:201642.18-201642.118" + wire width 64 $ternary$libresoc.v:201642$13937_Y + attribute \src "libresoc.v:201643.18-201643.118" + wire width 64 $ternary$libresoc.v:201643$13938_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -417361,23 +382267,23 @@ module \trap0 wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 5 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_trap0_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_trap0_fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_trap0_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_trap0_fast2$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_trap0_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_trap0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_trap0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_trap0_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_trap0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_trap0_p_ready_o @@ -417521,9 +382427,9 @@ module \trap0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 12 \cu_busy_o @@ -417597,17 +382503,17 @@ module \trap0 wire width 64 output 29 \dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 31 \dest5_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 24 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \fast2_ok - attribute \src "libresoc.v:199863.7-199863.15" + attribute \src "libresoc.v:200989.7-200989.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 30 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 20 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc @@ -417770,9 +382676,9 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 16 \src1_i + wire width 64 input 17 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 17 \src2_i + wire width 64 input 16 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 18 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" @@ -417806,7 +382712,7 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:200464$14363 + cell $and $and$libresoc.v:201590$13885 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -417814,10 +382720,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:200464$14363_Y + connect \Y $and$libresoc.v:201590$13885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:200465$14364 + cell $and $and$libresoc.v:201591$13886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417825,10 +382731,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:200465$14364_Y + connect \Y $and$libresoc.v:201591$13886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:200466$14365 + cell $and $and$libresoc.v:201592$13887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417836,10 +382742,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:200466$14365_Y + connect \Y $and$libresoc.v:201592$13887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:200467$14366 + cell $and $and$libresoc.v:201593$13888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417847,10 +382753,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:200467$14366_Y + connect \Y $and$libresoc.v:201593$13888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:200468$14367 + cell $and $and$libresoc.v:201594$13889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417858,10 +382764,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:200468$14367_Y + connect \Y $and$libresoc.v:201594$13889_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:200469$14368 + cell $and $and$libresoc.v:201595$13890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417869,10 +382775,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:200469$14368_Y + connect \Y $and$libresoc.v:201595$13890_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:200470$14369 + cell $and $and$libresoc.v:201596$13891 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -417880,10 +382786,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 \$107 \$109 } - connect \Y $and$libresoc.v:200470$14369_Y + connect \Y $and$libresoc.v:201596$13891_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:200471$14370 + cell $and $and$libresoc.v:201597$13892 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -417891,10 +382797,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \$111 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:200471$14370_Y + connect \Y $and$libresoc.v:201597$13892_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:200472$14371 + cell $and $and$libresoc.v:201598$13893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417902,10 +382808,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:200472$14371_Y + connect \Y $and$libresoc.v:201598$13893_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:200473$14372 + cell $and $and$libresoc.v:201599$13894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417913,10 +382819,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:200473$14372_Y + connect \Y $and$libresoc.v:201599$13894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:200474$14373 + cell $and $and$libresoc.v:201600$13895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417924,10 +382830,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:200474$14373_Y + connect \Y $and$libresoc.v:201600$13895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:200475$14374 + cell $and $and$libresoc.v:201601$13896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417935,10 +382841,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:200475$14374_Y + connect \Y $and$libresoc.v:201601$13896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:200476$14375 + cell $and $and$libresoc.v:201602$13897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417946,10 +382852,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:200476$14375_Y + connect \Y $and$libresoc.v:201602$13897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:200477$14376 + cell $and $and$libresoc.v:201603$13898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417957,10 +382863,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:200477$14376_Y + connect \Y $and$libresoc.v:201603$13898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:200479$14378 + cell $and $and$libresoc.v:201605$13900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417968,10 +382874,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:200479$14378_Y + connect \Y $and$libresoc.v:201605$13900_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:200481$14380 + cell $and $and$libresoc.v:201607$13902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417979,10 +382885,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:200481$14380_Y + connect \Y $and$libresoc.v:201607$13902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:200482$14381 + cell $and $and$libresoc.v:201608$13903 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -417990,10 +382896,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:200482$14381_Y + connect \Y $and$libresoc.v:201608$13903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:200484$14383 + cell $and $and$libresoc.v:201610$13905 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -418001,10 +382907,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:200484$14383_Y + connect \Y $and$libresoc.v:201610$13905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:200487$14386 + cell $and $and$libresoc.v:201613$13908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418012,10 +382918,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:200487$14386_Y + connect \Y $and$libresoc.v:201613$13908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:200491$14390 + cell $and $and$libresoc.v:201617$13912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418023,10 +382929,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:200491$14390_Y + connect \Y $and$libresoc.v:201617$13912_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:200493$14392 + cell $and $and$libresoc.v:201619$13914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418034,10 +382940,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:200493$14392_Y + connect \Y $and$libresoc.v:201619$13914_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:200494$14393 + cell $and $and$libresoc.v:201620$13915 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -418045,10 +382951,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:200494$14393_Y + connect \Y $and$libresoc.v:201620$13915_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:200496$14395 + cell $and $and$libresoc.v:201622$13917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418056,10 +382962,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:200496$14395_Y + connect \Y $and$libresoc.v:201622$13917_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:200498$14397 + cell $and $and$libresoc.v:201624$13919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418067,10 +382973,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_trap0_n_ready_i - connect \Y $and$libresoc.v:200498$14397_Y + connect \Y $and$libresoc.v:201624$13919_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:200499$14398 + cell $and $and$libresoc.v:201625$13920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418078,10 +382984,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_trap0_n_valid_o - connect \Y $and$libresoc.v:200499$14398_Y + connect \Y $and$libresoc.v:201625$13920_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:200500$14399 + cell $and $and$libresoc.v:201626$13921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418089,10 +382995,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:200500$14399_Y + connect \Y $and$libresoc.v:201626$13921_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:200505$14404 + cell $and $and$libresoc.v:201631$13926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418100,10 +383006,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:200505$14404_Y + connect \Y $and$libresoc.v:201631$13926_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:200506$14405 + cell $and $and$libresoc.v:201632$13927 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -418111,10 +383017,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:200506$14405_Y + connect \Y $and$libresoc.v:201632$13927_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:200509$14408 + cell $and $and$libresoc.v:201635$13930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418122,10 +383028,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:200509$14408_Y + connect \Y $and$libresoc.v:201635$13930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:200510$14409 + cell $and $and$libresoc.v:201636$13931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418133,10 +383039,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:200510$14409_Y + connect \Y $and$libresoc.v:201636$13931_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:200511$14410 + cell $and $and$libresoc.v:201637$13932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418144,10 +383050,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:200511$14410_Y + connect \Y $and$libresoc.v:201637$13932_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:200512$14411 + cell $and $and$libresoc.v:201638$13933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418155,10 +383061,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:200512$14411_Y + connect \Y $and$libresoc.v:201638$13933_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:200513$14412 + cell $and $and$libresoc.v:201639$13934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418166,10 +383072,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \msr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:200513$14412_Y + connect \Y $and$libresoc.v:201639$13934_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:200519$14418 + cell $and $and$libresoc.v:201645$13940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418177,10 +383083,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:200519$14418_Y + connect \Y $and$libresoc.v:201645$13940_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:200520$14419 + cell $and $and$libresoc.v:201646$13941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418188,10 +383094,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:200520$14419_Y + connect \Y $and$libresoc.v:201646$13941_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:200521$14420 + cell $and $and$libresoc.v:201647$13942 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -418199,10 +383105,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:200521$14420_Y + connect \Y $and$libresoc.v:201647$13942_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:200522$14421 + cell $and $and$libresoc.v:201648$13943 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -418210,10 +383116,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$93 connect \B 4'1111 - connect \Y $and$libresoc.v:200522$14421_Y + connect \Y $and$libresoc.v:201648$13943_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:200495$14394 + cell $eq $eq$libresoc.v:201621$13916 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -418221,10 +383127,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:200495$14394_Y + connect \Y $eq$libresoc.v:201621$13916_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:200497$14396 + cell $eq $eq$libresoc.v:201623$13918 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -418232,66 +383138,66 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:200497$14396_Y + connect \Y $eq$libresoc.v:201623$13918_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:200478$14377 + cell $not $not$libresoc.v:201604$13899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:200478$14377_Y + connect \Y $not$libresoc.v:201604$13899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:200480$14379 + cell $not $not$libresoc.v:201606$13901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:200480$14379_Y + connect \Y $not$libresoc.v:201606$13901_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:200483$14382 + cell $not $not$libresoc.v:201609$13904 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:200483$14382_Y + connect \Y $not$libresoc.v:201609$13904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:200486$14385 + cell $not $not$libresoc.v:201612$13907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:200486$14385_Y + connect \Y $not$libresoc.v:201612$13907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:200492$14391 + cell $not $not$libresoc.v:201618$13913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_ready_i - connect \Y $not$libresoc.v:200492$14391_Y + connect \Y $not$libresoc.v:201618$13913_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:200507$14406 + cell $not $not$libresoc.v:201633$13928 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:200507$14406_Y + connect \Y $not$libresoc.v:201633$13928_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:200523$14422 + cell $not $not$libresoc.v:201649$13944 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:200523$14422_Y + connect \Y $not$libresoc.v:201649$13944_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:200490$14389 + cell $or $or$libresoc.v:201616$13911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418299,10 +383205,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:200490$14389_Y + connect \Y $or$libresoc.v:201616$13911_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:200501$14400 + cell $or $or$libresoc.v:201627$13922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418310,10 +383216,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:200501$14400_Y + connect \Y $or$libresoc.v:201627$13922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:200502$14401 + cell $or $or$libresoc.v:201628$13923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418321,10 +383227,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:200502$14401_Y + connect \Y $or$libresoc.v:201628$13923_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:200503$14402 + cell $or $or$libresoc.v:201629$13924 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -418332,10 +383238,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:200503$14402_Y + connect \Y $or$libresoc.v:201629$13924_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:200504$14403 + cell $or $or$libresoc.v:201630$13925 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -418343,10 +383249,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:200504$14403_Y + connect \Y $or$libresoc.v:201630$13925_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:200508$14407 + cell $or $or$libresoc.v:201634$13929 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -418354,10 +383260,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:200508$14407_Y + connect \Y $or$libresoc.v:201634$13929_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:200518$14417 + cell $or $or$libresoc.v:201644$13939 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -418365,74 +383271,74 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:200518$14417_Y + connect \Y $or$libresoc.v:201644$13939_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:200463$14362 + cell $reduce_and $reduce_and$libresoc.v:201589$13884 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:200463$14362_Y + connect \Y $reduce_and$libresoc.v:201589$13884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:200485$14384 + cell $reduce_or $reduce_or$libresoc.v:201611$13906 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:200485$14384_Y + connect \Y $reduce_or$libresoc.v:201611$13906_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:200488$14387 + cell $reduce_or $reduce_or$libresoc.v:201614$13909 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:200488$14387_Y + connect \Y $reduce_or$libresoc.v:201614$13909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:200489$14388 + cell $reduce_or $reduce_or$libresoc.v:201615$13910 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:200489$14388_Y + connect \Y $reduce_or$libresoc.v:201615$13910_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:200514$14413 + cell $mux $ternary$libresoc.v:201640$13935 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:200514$14413_Y + connect \Y $ternary$libresoc.v:201640$13935_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:200515$14414 + cell $mux $ternary$libresoc.v:201641$13936 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:200515$14414_Y + connect \Y $ternary$libresoc.v:201641$13936_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:200516$14415 + cell $mux $ternary$libresoc.v:201642$13937 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:200516$14415_Y + connect \Y $ternary$libresoc.v:201642$13937_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:200517$14416 + cell $mux $ternary$libresoc.v:201643$13938 parameter \WIDTH 64 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:200517$14416_Y + connect \Y $ternary$libresoc.v:201643$13938_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:200600.14-200606.4" + attribute \src "libresoc.v:201726.14-201732.4" cell \alu_l$45 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418441,7 +383347,7 @@ module \trap0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:200607.13-200637.4" + attribute \src "libresoc.v:201733.13-201763.4" cell \alu_trap0 \alu_trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418474,7 +383380,7 @@ module \trap0 connect \trap_op__traptype \alu_trap0_trap_op__traptype end attribute \module_not_derived 1 - attribute \src "libresoc.v:200638.15-200644.4" + attribute \src "libresoc.v:201764.15-201770.4" cell \alui_l$44 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418483,7 +383389,7 @@ module \trap0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:200645.14-200651.4" + attribute \src "libresoc.v:201771.14-201777.4" cell \opc_l$40 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418492,7 +383398,7 @@ module \trap0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:200652.14-200658.4" + attribute \src "libresoc.v:201778.14-201784.4" cell \req_l$41 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418501,7 +383407,7 @@ module \trap0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:200659.14-200665.4" + attribute \src "libresoc.v:201785.14-201791.4" cell \rok_l$43 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418510,7 +383416,7 @@ module \trap0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:200666.14-200671.4" + attribute \src "libresoc.v:201792.14-201797.4" cell \rst_l$42 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418518,7 +383424,7 @@ module \trap0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:200672.14-200678.4" + attribute \src "libresoc.v:201798.14-201804.4" cell \src_l$39 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418526,592 +383432,592 @@ module \trap0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:199863.7-199863.20" - process $proc$libresoc.v:199863$14577 + attribute \src "libresoc.v:200989.7-200989.20" + process $proc$libresoc.v:200989$14099 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:199989.7-199989.24" - process $proc$libresoc.v:199989$14578 + attribute \src "libresoc.v:201115.7-201115.24" + process $proc$libresoc.v:201115$14100 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:199999.7-199999.26" - process $proc$libresoc.v:199999$14579 + attribute \src "libresoc.v:201125.7-201125.26" + process $proc$libresoc.v:201125$14101 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:200007.7-200007.25" - process $proc$libresoc.v:200007$14580 + attribute \src "libresoc.v:201133.7-201133.25" + process $proc$libresoc.v:201133$14102 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:200043.14-200043.59" - process $proc$libresoc.v:200043$14581 + attribute \src "libresoc.v:201169.14-201169.59" + process $proc$libresoc.v:201169$14103 assign { } { } assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:200062.14-200062.51" - process $proc$libresoc.v:200062$14582 + attribute \src "libresoc.v:201188.14-201188.51" + process $proc$libresoc.v:201188$14104 assign { } { } assign $1\alu_trap0_trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:200066.14-200066.45" - process $proc$libresoc.v:200066$14583 + attribute \src "libresoc.v:201192.14-201192.45" + process $proc$libresoc.v:201192$14105 assign { } { } assign $1\alu_trap0_trap_op__insn[31:0] 0 sync always sync init update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:200145.13-200145.49" - process $proc$libresoc.v:200145$14584 + attribute \src "libresoc.v:201271.13-201271.49" + process $proc$libresoc.v:201271$14106 assign { } { } assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:200149.7-200149.41" - process $proc$libresoc.v:200149$14585 + attribute \src "libresoc.v:201275.7-201275.41" + process $proc$libresoc.v:201275$14107 assign { } { } assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 sync always sync init update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:200153.13-200153.48" - process $proc$libresoc.v:200153$14586 + attribute \src "libresoc.v:201279.13-201279.48" + process $proc$libresoc.v:201279$14108 assign { } { } assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:200157.14-200157.59" - process $proc$libresoc.v:200157$14587 + attribute \src "libresoc.v:201283.14-201283.59" + process $proc$libresoc.v:201283$14109 assign { } { } assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:200161.14-200161.52" - process $proc$libresoc.v:200161$14588 + attribute \src "libresoc.v:201287.14-201287.52" + process $proc$libresoc.v:201287$14110 assign { } { } assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:200165.13-200165.48" - process $proc$libresoc.v:200165$14589 + attribute \src "libresoc.v:201291.13-201291.48" + process $proc$libresoc.v:201291$14111 assign { } { } assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:200171.7-200171.27" - process $proc$libresoc.v:200171$14590 + attribute \src "libresoc.v:201297.7-201297.27" + process $proc$libresoc.v:201297$14112 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:200203.14-200203.47" - process $proc$libresoc.v:200203$14591 + attribute \src "libresoc.v:201329.14-201329.47" + process $proc$libresoc.v:201329$14113 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:200207.7-200207.27" - process $proc$libresoc.v:200207$14592 + attribute \src "libresoc.v:201333.7-201333.27" + process $proc$libresoc.v:201333$14114 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:200211.14-200211.51" - process $proc$libresoc.v:200211$14593 + attribute \src "libresoc.v:201337.14-201337.51" + process $proc$libresoc.v:201337$14115 assign { } { } assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast1 $1\data_r1__fast1[63:0] end - attribute \src "libresoc.v:200215.7-200215.31" - process $proc$libresoc.v:200215$14594 + attribute \src "libresoc.v:201341.7-201341.31" + process $proc$libresoc.v:201341$14116 assign { } { } assign $1\data_r1__fast1_ok[0:0] 1'0 sync always sync init update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:200219.14-200219.51" - process $proc$libresoc.v:200219$14595 + attribute \src "libresoc.v:201345.14-201345.51" + process $proc$libresoc.v:201345$14117 assign { } { } assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast2 $1\data_r2__fast2[63:0] end - attribute \src "libresoc.v:200223.7-200223.31" - process $proc$libresoc.v:200223$14596 + attribute \src "libresoc.v:201349.7-201349.31" + process $proc$libresoc.v:201349$14118 assign { } { } assign $1\data_r2__fast2_ok[0:0] 1'0 sync always sync init update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:200227.14-200227.49" - process $proc$libresoc.v:200227$14597 + attribute \src "libresoc.v:201353.14-201353.49" + process $proc$libresoc.v:201353$14119 assign { } { } assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r3__nia $1\data_r3__nia[63:0] end - attribute \src "libresoc.v:200231.7-200231.29" - process $proc$libresoc.v:200231$14598 + attribute \src "libresoc.v:201357.7-201357.29" + process $proc$libresoc.v:201357$14120 assign { } { } assign $1\data_r3__nia_ok[0:0] 1'0 sync always sync init update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:200235.14-200235.49" - process $proc$libresoc.v:200235$14599 + attribute \src "libresoc.v:201361.14-201361.49" + process $proc$libresoc.v:201361$14121 assign { } { } assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r4__msr $1\data_r4__msr[63:0] end - attribute \src "libresoc.v:200239.7-200239.29" - process $proc$libresoc.v:200239$14600 + attribute \src "libresoc.v:201365.7-201365.29" + process $proc$libresoc.v:201365$14122 assign { } { } assign $1\data_r4__msr_ok[0:0] 1'0 sync always sync init update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:200270.7-200270.25" - process $proc$libresoc.v:200270$14601 + attribute \src "libresoc.v:201396.7-201396.25" + process $proc$libresoc.v:201396$14123 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:200274.7-200274.25" - process $proc$libresoc.v:200274$14602 + attribute \src "libresoc.v:201400.7-201400.25" + process $proc$libresoc.v:201400$14124 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:200386.13-200386.31" - process $proc$libresoc.v:200386$14603 + attribute \src "libresoc.v:201512.13-201512.31" + process $proc$libresoc.v:201512$14125 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:200394.13-200394.32" - process $proc$libresoc.v:200394$14604 + attribute \src "libresoc.v:201520.13-201520.32" + process $proc$libresoc.v:201520$14126 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:200398.13-200398.32" - process $proc$libresoc.v:200398$14605 + attribute \src "libresoc.v:201524.13-201524.32" + process $proc$libresoc.v:201524$14127 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:200410.7-200410.26" - process $proc$libresoc.v:200410$14606 + attribute \src "libresoc.v:201536.7-201536.26" + process $proc$libresoc.v:201536$14128 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:200414.7-200414.26" - process $proc$libresoc.v:200414$14607 + attribute \src "libresoc.v:201540.7-201540.26" + process $proc$libresoc.v:201540$14129 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:200418.7-200418.25" - process $proc$libresoc.v:200418$14608 + attribute \src "libresoc.v:201544.7-201544.25" + process $proc$libresoc.v:201544$14130 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:200422.7-200422.25" - process $proc$libresoc.v:200422$14609 + attribute \src "libresoc.v:201548.7-201548.25" + process $proc$libresoc.v:201548$14131 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:200438.13-200438.31" - process $proc$libresoc.v:200438$14610 + attribute \src "libresoc.v:201564.13-201564.31" + process $proc$libresoc.v:201564$14132 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:200442.13-200442.31" - process $proc$libresoc.v:200442$14611 + attribute \src "libresoc.v:201568.13-201568.31" + process $proc$libresoc.v:201568$14133 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:200446.14-200446.43" - process $proc$libresoc.v:200446$14612 + attribute \src "libresoc.v:201572.14-201572.43" + process $proc$libresoc.v:201572$14134 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:200450.14-200450.43" - process $proc$libresoc.v:200450$14613 + attribute \src "libresoc.v:201576.14-201576.43" + process $proc$libresoc.v:201576$14135 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:200454.14-200454.43" - process $proc$libresoc.v:200454$14614 + attribute \src "libresoc.v:201580.14-201580.43" + process $proc$libresoc.v:201580$14136 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:200458.14-200458.43" - process $proc$libresoc.v:200458$14615 + attribute \src "libresoc.v:201584.14-201584.43" + process $proc$libresoc.v:201584$14137 assign { } { } assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r3 $1\src_r3[63:0] end - attribute \src "libresoc.v:200524.3-200525.39" - process $proc$libresoc.v:200524$14423 + attribute \src "libresoc.v:201650.3-201651.39" + process $proc$libresoc.v:201650$13945 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:200526.3-200527.43" - process $proc$libresoc.v:200526$14424 + attribute \src "libresoc.v:201652.3-201653.43" + process $proc$libresoc.v:201652$13946 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:200528.3-200529.29" - process $proc$libresoc.v:200528$14425 + attribute \src "libresoc.v:201654.3-201655.29" + process $proc$libresoc.v:201654$13947 assign { } { } assign $0\src_r3[63:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[63:0] end - attribute \src "libresoc.v:200530.3-200531.29" - process $proc$libresoc.v:200530$14426 + attribute \src "libresoc.v:201656.3-201657.29" + process $proc$libresoc.v:201656$13948 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:200532.3-200533.29" - process $proc$libresoc.v:200532$14427 + attribute \src "libresoc.v:201658.3-201659.29" + process $proc$libresoc.v:201658$13949 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:200534.3-200535.29" - process $proc$libresoc.v:200534$14428 + attribute \src "libresoc.v:201660.3-201661.29" + process $proc$libresoc.v:201660$13950 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:200536.3-200537.41" - process $proc$libresoc.v:200536$14429 + attribute \src "libresoc.v:201662.3-201663.41" + process $proc$libresoc.v:201662$13951 assign { } { } assign $0\data_r4__msr[63:0] \data_r4__msr$next sync posedge \coresync_clk update \data_r4__msr $0\data_r4__msr[63:0] end - attribute \src "libresoc.v:200538.3-200539.47" - process $proc$libresoc.v:200538$14430 + attribute \src "libresoc.v:201664.3-201665.47" + process $proc$libresoc.v:201664$13952 assign { } { } assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next sync posedge \coresync_clk update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:200540.3-200541.41" - process $proc$libresoc.v:200540$14431 + attribute \src "libresoc.v:201666.3-201667.41" + process $proc$libresoc.v:201666$13953 assign { } { } assign $0\data_r3__nia[63:0] \data_r3__nia$next sync posedge \coresync_clk update \data_r3__nia $0\data_r3__nia[63:0] end - attribute \src "libresoc.v:200542.3-200543.47" - process $proc$libresoc.v:200542$14432 + attribute \src "libresoc.v:201668.3-201669.47" + process $proc$libresoc.v:201668$13954 assign { } { } assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next sync posedge \coresync_clk update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:200544.3-200545.45" - process $proc$libresoc.v:200544$14433 + attribute \src "libresoc.v:201670.3-201671.45" + process $proc$libresoc.v:201670$13955 assign { } { } assign $0\data_r2__fast2[63:0] \data_r2__fast2$next sync posedge \coresync_clk update \data_r2__fast2 $0\data_r2__fast2[63:0] end - attribute \src "libresoc.v:200546.3-200547.51" - process $proc$libresoc.v:200546$14434 + attribute \src "libresoc.v:201672.3-201673.51" + process $proc$libresoc.v:201672$13956 assign { } { } assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next sync posedge \coresync_clk update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:200548.3-200549.45" - process $proc$libresoc.v:200548$14435 + attribute \src "libresoc.v:201674.3-201675.45" + process $proc$libresoc.v:201674$13957 assign { } { } assign $0\data_r1__fast1[63:0] \data_r1__fast1$next sync posedge \coresync_clk update \data_r1__fast1 $0\data_r1__fast1[63:0] end - attribute \src "libresoc.v:200550.3-200551.51" - process $proc$libresoc.v:200550$14436 + attribute \src "libresoc.v:201676.3-201677.51" + process $proc$libresoc.v:201676$13958 assign { } { } assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next sync posedge \coresync_clk update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:200552.3-200553.37" - process $proc$libresoc.v:200552$14437 + attribute \src "libresoc.v:201678.3-201679.37" + process $proc$libresoc.v:201678$13959 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:200554.3-200555.43" - process $proc$libresoc.v:200554$14438 + attribute \src "libresoc.v:201680.3-201681.43" + process $proc$libresoc.v:201680$13960 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:200556.3-200557.73" - process $proc$libresoc.v:200556$14439 + attribute \src "libresoc.v:201682.3-201683.73" + process $proc$libresoc.v:201682$13961 assign { } { } assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:200558.3-200559.69" - process $proc$libresoc.v:200558$14440 + attribute \src "libresoc.v:201684.3-201685.69" + process $proc$libresoc.v:201684$13962 assign { } { } assign $0\alu_trap0_trap_op__fn_unit[13:0] \alu_trap0_trap_op__fn_unit$next sync posedge \coresync_clk update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:200560.3-200561.63" - process $proc$libresoc.v:200560$14441 + attribute \src "libresoc.v:201686.3-201687.63" + process $proc$libresoc.v:201686$13963 assign { } { } assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:200562.3-200563.61" - process $proc$libresoc.v:200562$14442 + attribute \src "libresoc.v:201688.3-201689.61" + process $proc$libresoc.v:201688$13964 assign { } { } assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next sync posedge \coresync_clk update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:200564.3-200565.61" - process $proc$libresoc.v:200564$14443 + attribute \src "libresoc.v:201690.3-201691.61" + process $proc$libresoc.v:201690$13965 assign { } { } assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next sync posedge \coresync_clk update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:200566.3-200567.71" - process $proc$libresoc.v:200566$14444 + attribute \src "libresoc.v:201692.3-201693.71" + process $proc$libresoc.v:201692$13966 assign { } { } assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next sync posedge \coresync_clk update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:200568.3-200569.71" - process $proc$libresoc.v:200568$14445 + attribute \src "libresoc.v:201694.3-201695.71" + process $proc$libresoc.v:201694$13967 assign { } { } assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next sync posedge \coresync_clk update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:200570.3-200571.71" - process $proc$libresoc.v:200570$14446 + attribute \src "libresoc.v:201696.3-201697.71" + process $proc$libresoc.v:201696$13968 assign { } { } assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next sync posedge \coresync_clk update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:200572.3-200573.71" - process $proc$libresoc.v:200572$14447 + attribute \src "libresoc.v:201698.3-201699.71" + process $proc$libresoc.v:201698$13969 assign { } { } assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next sync posedge \coresync_clk update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:200574.3-200575.39" - process $proc$libresoc.v:200574$14448 + attribute \src "libresoc.v:201700.3-201701.39" + process $proc$libresoc.v:201700$13970 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:200576.3-200577.39" - process $proc$libresoc.v:200576$14449 + attribute \src "libresoc.v:201702.3-201703.39" + process $proc$libresoc.v:201702$13971 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:200578.3-200579.39" - process $proc$libresoc.v:200578$14450 + attribute \src "libresoc.v:201704.3-201705.39" + process $proc$libresoc.v:201704$13972 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:200580.3-200581.39" - process $proc$libresoc.v:200580$14451 + attribute \src "libresoc.v:201706.3-201707.39" + process $proc$libresoc.v:201706$13973 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:200582.3-200583.39" - process $proc$libresoc.v:200582$14452 + attribute \src "libresoc.v:201708.3-201709.39" + process $proc$libresoc.v:201708$13974 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:200584.3-200585.39" - process $proc$libresoc.v:200584$14453 + attribute \src "libresoc.v:201710.3-201711.39" + process $proc$libresoc.v:201710$13975 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:200586.3-200587.39" - process $proc$libresoc.v:200586$14454 + attribute \src "libresoc.v:201712.3-201713.39" + process $proc$libresoc.v:201712$13976 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:200588.3-200589.39" - process $proc$libresoc.v:200588$14455 + attribute \src "libresoc.v:201714.3-201715.39" + process $proc$libresoc.v:201714$13977 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:200590.3-200591.41" - process $proc$libresoc.v:200590$14456 + attribute \src "libresoc.v:201716.3-201717.41" + process $proc$libresoc.v:201716$13978 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:200592.3-200593.41" - process $proc$libresoc.v:200592$14457 + attribute \src "libresoc.v:201718.3-201719.41" + process $proc$libresoc.v:201718$13979 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:200594.3-200595.37" - process $proc$libresoc.v:200594$14458 + attribute \src "libresoc.v:201720.3-201721.37" + process $proc$libresoc.v:201720$13980 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:200596.3-200597.41" - process $proc$libresoc.v:200596$14459 + attribute \src "libresoc.v:201722.3-201723.41" + process $proc$libresoc.v:201722$13981 assign { } { } assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:200598.3-200599.25" - process $proc$libresoc.v:200598$14460 + attribute \src "libresoc.v:201724.3-201725.25" + process $proc$libresoc.v:201724$13982 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:200679.3-200688.6" - process $proc$libresoc.v:200679$14461 + attribute \src "libresoc.v:201805.3-201814.6" + process $proc$libresoc.v:201805$13983 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:200680.5-200680.29" + attribute \src "libresoc.v:201806.5-201806.29" switch \initial - attribute \src "libresoc.v:200680.9-200680.17" + attribute \src "libresoc.v:201806.9-201806.17" case 1'1 case end @@ -419127,14 +384033,14 @@ module \trap0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:200689.3-200697.6" - process $proc$libresoc.v:200689$14462 + attribute \src "libresoc.v:201815.3-201823.6" + process $proc$libresoc.v:201815$13984 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$14463 $1\rok_l_s_rdok$next[0:0]$14464 - attribute \src "libresoc.v:200690.5-200690.29" + assign $0\rok_l_s_rdok$next[0:0]$13985 $1\rok_l_s_rdok$next[0:0]$13986 + attribute \src "libresoc.v:201816.5-201816.29" switch \initial - attribute \src "libresoc.v:200690.9-200690.17" + attribute \src "libresoc.v:201816.9-201816.17" case 1'1 case end @@ -419143,21 +384049,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$14464 1'0 + assign $1\rok_l_s_rdok$next[0:0]$13986 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$14464 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$13986 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14463 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13985 end - attribute \src "libresoc.v:200698.3-200706.6" - process $proc$libresoc.v:200698$14465 + attribute \src "libresoc.v:201824.3-201832.6" + process $proc$libresoc.v:201824$13987 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$14466 $1\rok_l_r_rdok$next[0:0]$14467 - attribute \src "libresoc.v:200699.5-200699.29" + assign $0\rok_l_r_rdok$next[0:0]$13988 $1\rok_l_r_rdok$next[0:0]$13989 + attribute \src "libresoc.v:201825.5-201825.29" switch \initial - attribute \src "libresoc.v:200699.9-200699.17" + attribute \src "libresoc.v:201825.9-201825.17" case 1'1 case end @@ -419166,21 +384072,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$14467 1'1 + assign $1\rok_l_r_rdok$next[0:0]$13989 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$14467 \$65 + assign $1\rok_l_r_rdok$next[0:0]$13989 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14466 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13988 end - attribute \src "libresoc.v:200707.3-200715.6" - process $proc$libresoc.v:200707$14468 + attribute \src "libresoc.v:201833.3-201841.6" + process $proc$libresoc.v:201833$13990 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$14469 $1\rst_l_s_rst$next[0:0]$14470 - attribute \src "libresoc.v:200708.5-200708.29" + assign $0\rst_l_s_rst$next[0:0]$13991 $1\rst_l_s_rst$next[0:0]$13992 + attribute \src "libresoc.v:201834.5-201834.29" switch \initial - attribute \src "libresoc.v:200708.9-200708.17" + attribute \src "libresoc.v:201834.9-201834.17" case 1'1 case end @@ -419189,21 +384095,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$14470 1'0 + assign $1\rst_l_s_rst$next[0:0]$13992 1'0 case - assign $1\rst_l_s_rst$next[0:0]$14470 \all_rd + assign $1\rst_l_s_rst$next[0:0]$13992 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14469 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13991 end - attribute \src "libresoc.v:200716.3-200724.6" - process $proc$libresoc.v:200716$14471 + attribute \src "libresoc.v:201842.3-201850.6" + process $proc$libresoc.v:201842$13993 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$14472 $1\rst_l_r_rst$next[0:0]$14473 - attribute \src "libresoc.v:200717.5-200717.29" + assign $0\rst_l_r_rst$next[0:0]$13994 $1\rst_l_r_rst$next[0:0]$13995 + attribute \src "libresoc.v:201843.5-201843.29" switch \initial - attribute \src "libresoc.v:200717.9-200717.17" + attribute \src "libresoc.v:201843.9-201843.17" case 1'1 case end @@ -419212,21 +384118,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$14473 1'1 + assign $1\rst_l_r_rst$next[0:0]$13995 1'1 case - assign $1\rst_l_r_rst$next[0:0]$14473 \rst_r + assign $1\rst_l_r_rst$next[0:0]$13995 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14472 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13994 end - attribute \src "libresoc.v:200725.3-200733.6" - process $proc$libresoc.v:200725$14474 + attribute \src "libresoc.v:201851.3-201859.6" + process $proc$libresoc.v:201851$13996 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$14475 $1\opc_l_s_opc$next[0:0]$14476 - attribute \src "libresoc.v:200726.5-200726.29" + assign $0\opc_l_s_opc$next[0:0]$13997 $1\opc_l_s_opc$next[0:0]$13998 + attribute \src "libresoc.v:201852.5-201852.29" switch \initial - attribute \src "libresoc.v:200726.9-200726.17" + attribute \src "libresoc.v:201852.9-201852.17" case 1'1 case end @@ -419235,21 +384141,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$14476 1'0 + assign $1\opc_l_s_opc$next[0:0]$13998 1'0 case - assign $1\opc_l_s_opc$next[0:0]$14476 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$13998 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14475 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13997 end - attribute \src "libresoc.v:200734.3-200742.6" - process $proc$libresoc.v:200734$14477 + attribute \src "libresoc.v:201860.3-201868.6" + process $proc$libresoc.v:201860$13999 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$14478 $1\opc_l_r_opc$next[0:0]$14479 - attribute \src "libresoc.v:200735.5-200735.29" + assign $0\opc_l_r_opc$next[0:0]$14000 $1\opc_l_r_opc$next[0:0]$14001 + attribute \src "libresoc.v:201861.5-201861.29" switch \initial - attribute \src "libresoc.v:200735.9-200735.17" + attribute \src "libresoc.v:201861.9-201861.17" case 1'1 case end @@ -419258,21 +384164,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$14479 1'1 + assign $1\opc_l_r_opc$next[0:0]$14001 1'1 case - assign $1\opc_l_r_opc$next[0:0]$14479 \req_done + assign $1\opc_l_r_opc$next[0:0]$14001 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14478 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14000 end - attribute \src "libresoc.v:200743.3-200751.6" - process $proc$libresoc.v:200743$14480 + attribute \src "libresoc.v:201869.3-201877.6" + process $proc$libresoc.v:201869$14002 assign { } { } assign { } { } - assign $0\src_l_s_src$next[3:0]$14481 $1\src_l_s_src$next[3:0]$14482 - attribute \src "libresoc.v:200744.5-200744.29" + assign $0\src_l_s_src$next[3:0]$14003 $1\src_l_s_src$next[3:0]$14004 + attribute \src "libresoc.v:201870.5-201870.29" switch \initial - attribute \src "libresoc.v:200744.9-200744.17" + attribute \src "libresoc.v:201870.9-201870.17" case 1'1 case end @@ -419281,21 +384187,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[3:0]$14482 4'0000 + assign $1\src_l_s_src$next[3:0]$14004 4'0000 case - assign $1\src_l_s_src$next[3:0]$14482 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[3:0]$14004 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14481 + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14003 end - attribute \src "libresoc.v:200752.3-200760.6" - process $proc$libresoc.v:200752$14483 + attribute \src "libresoc.v:201878.3-201886.6" + process $proc$libresoc.v:201878$14005 assign { } { } assign { } { } - assign $0\src_l_r_src$next[3:0]$14484 $1\src_l_r_src$next[3:0]$14485 - attribute \src "libresoc.v:200753.5-200753.29" + assign $0\src_l_r_src$next[3:0]$14006 $1\src_l_r_src$next[3:0]$14007 + attribute \src "libresoc.v:201879.5-201879.29" switch \initial - attribute \src "libresoc.v:200753.9-200753.17" + attribute \src "libresoc.v:201879.9-201879.17" case 1'1 case end @@ -419304,21 +384210,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[3:0]$14485 4'1111 + assign $1\src_l_r_src$next[3:0]$14007 4'1111 case - assign $1\src_l_r_src$next[3:0]$14485 \reset_r + assign $1\src_l_r_src$next[3:0]$14007 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14484 + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14006 end - attribute \src "libresoc.v:200761.3-200769.6" - process $proc$libresoc.v:200761$14486 + attribute \src "libresoc.v:201887.3-201895.6" + process $proc$libresoc.v:201887$14008 assign { } { } assign { } { } - assign $0\req_l_s_req$next[4:0]$14487 $1\req_l_s_req$next[4:0]$14488 - attribute \src "libresoc.v:200762.5-200762.29" + assign $0\req_l_s_req$next[4:0]$14009 $1\req_l_s_req$next[4:0]$14010 + attribute \src "libresoc.v:201888.5-201888.29" switch \initial - attribute \src "libresoc.v:200762.9-200762.17" + attribute \src "libresoc.v:201888.9-201888.17" case 1'1 case end @@ -419327,21 +384233,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[4:0]$14488 5'00000 + assign $1\req_l_s_req$next[4:0]$14010 5'00000 case - assign $1\req_l_s_req$next[4:0]$14488 \$67 + assign $1\req_l_s_req$next[4:0]$14010 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14487 + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14009 end - attribute \src "libresoc.v:200770.3-200778.6" - process $proc$libresoc.v:200770$14489 + attribute \src "libresoc.v:201896.3-201904.6" + process $proc$libresoc.v:201896$14011 assign { } { } assign { } { } - assign $0\req_l_r_req$next[4:0]$14490 $1\req_l_r_req$next[4:0]$14491 - attribute \src "libresoc.v:200771.5-200771.29" + assign $0\req_l_r_req$next[4:0]$14012 $1\req_l_r_req$next[4:0]$14013 + attribute \src "libresoc.v:201897.5-201897.29" switch \initial - attribute \src "libresoc.v:200771.9-200771.17" + attribute \src "libresoc.v:201897.9-201897.17" case 1'1 case end @@ -419350,15 +384256,15 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[4:0]$14491 5'11111 + assign $1\req_l_r_req$next[4:0]$14013 5'11111 case - assign $1\req_l_r_req$next[4:0]$14491 \$69 + assign $1\req_l_r_req$next[4:0]$14013 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14490 + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14012 end - attribute \src "libresoc.v:200779.3-200796.6" - process $proc$libresoc.v:200779$14492 + attribute \src "libresoc.v:201905.3-201922.6" + process $proc$libresoc.v:201905$14014 assign { } { } assign { } { } assign { } { } @@ -419377,18 +384283,18 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign $0\alu_trap0_trap_op__cia$next[63:0]$14493 $1\alu_trap0_trap_op__cia$next[63:0]$14502 - assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 - assign $0\alu_trap0_trap_op__insn$next[31:0]$14495 $1\alu_trap0_trap_op__insn$next[31:0]$14504 - assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 - assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 - assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 - assign $0\alu_trap0_trap_op__msr$next[63:0]$14499 $1\alu_trap0_trap_op__msr$next[63:0]$14508 - assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 - assign $0\alu_trap0_trap_op__traptype$next[7:0]$14501 $1\alu_trap0_trap_op__traptype$next[7:0]$14510 - attribute \src "libresoc.v:200780.5-200780.29" + assign $0\alu_trap0_trap_op__cia$next[63:0]$14015 $1\alu_trap0_trap_op__cia$next[63:0]$14024 + assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14016 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14025 + assign $0\alu_trap0_trap_op__insn$next[31:0]$14017 $1\alu_trap0_trap_op__insn$next[31:0]$14026 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14018 $1\alu_trap0_trap_op__insn_type$next[6:0]$14027 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14019 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14028 + assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14020 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14029 + assign $0\alu_trap0_trap_op__msr$next[63:0]$14021 $1\alu_trap0_trap_op__msr$next[63:0]$14030 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14022 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14031 + assign $0\alu_trap0_trap_op__traptype$next[7:0]$14023 $1\alu_trap0_trap_op__traptype$next[7:0]$14032 + attribute \src "libresoc.v:201906.5-201906.29" switch \initial - attribute \src "libresoc.v:200780.9-200780.17" + attribute \src "libresoc.v:201906.9-201906.17" case 1'1 case end @@ -419405,43 +384311,43 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 $1\alu_trap0_trap_op__traptype$next[7:0]$14510 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 $1\alu_trap0_trap_op__cia$next[63:0]$14502 $1\alu_trap0_trap_op__msr$next[63:0]$14508 $1\alu_trap0_trap_op__insn$next[31:0]$14504 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14029 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14031 $1\alu_trap0_trap_op__traptype$next[7:0]$14032 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14028 $1\alu_trap0_trap_op__cia$next[63:0]$14024 $1\alu_trap0_trap_op__msr$next[63:0]$14030 $1\alu_trap0_trap_op__insn$next[31:0]$14026 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14025 $1\alu_trap0_trap_op__insn_type$next[6:0]$14027 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } case - assign $1\alu_trap0_trap_op__cia$next[63:0]$14502 \alu_trap0_trap_op__cia - assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 \alu_trap0_trap_op__fn_unit - assign $1\alu_trap0_trap_op__insn$next[31:0]$14504 \alu_trap0_trap_op__insn - assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 \alu_trap0_trap_op__insn_type - assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 \alu_trap0_trap_op__is_32bit - assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 \alu_trap0_trap_op__ldst_exc - assign $1\alu_trap0_trap_op__msr$next[63:0]$14508 \alu_trap0_trap_op__msr - assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 \alu_trap0_trap_op__trapaddr - assign $1\alu_trap0_trap_op__traptype$next[7:0]$14510 \alu_trap0_trap_op__traptype + assign $1\alu_trap0_trap_op__cia$next[63:0]$14024 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14025 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$14026 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14027 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14028 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14029 \alu_trap0_trap_op__ldst_exc + assign $1\alu_trap0_trap_op__msr$next[63:0]$14030 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14031 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[7:0]$14032 \alu_trap0_trap_op__traptype end sync always - update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14493 - update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 - update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14495 - update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 - update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 - update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 - update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14499 - update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 - update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14501 + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14015 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14016 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14017 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14018 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14019 + update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14020 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14021 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14022 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14023 end - attribute \src "libresoc.v:200797.3-200818.6" - process $proc$libresoc.v:200797$14511 + attribute \src "libresoc.v:201923.3-201944.6" + process $proc$libresoc.v:201923$14033 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$14512 $2\data_r0__o$next[63:0]$14516 + assign $0\data_r0__o$next[63:0]$14034 $2\data_r0__o$next[63:0]$14038 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$14513 $3\data_r0__o_ok$next[0:0]$14518 - attribute \src "libresoc.v:200798.5-200798.29" + assign $0\data_r0__o_ok$next[0:0]$14035 $3\data_r0__o_ok$next[0:0]$14040 + attribute \src "libresoc.v:201924.5-201924.29" switch \initial - attribute \src "libresoc.v:200798.9-200798.17" + attribute \src "libresoc.v:201924.9-201924.17" case 1'1 case end @@ -419451,10 +384357,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$14515 $1\data_r0__o$next[63:0]$14514 } { \o_ok \alu_trap0_o } + assign { $1\data_r0__o_ok$next[0:0]$14037 $1\data_r0__o$next[63:0]$14036 } { \o_ok \alu_trap0_o } case - assign $1\data_r0__o$next[63:0]$14514 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$14515 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$14036 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$14037 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -419462,38 +384368,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$14517 $2\data_r0__o$next[63:0]$14516 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$14039 $2\data_r0__o$next[63:0]$14038 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$14516 $1\data_r0__o$next[63:0]$14514 - assign $2\data_r0__o_ok$next[0:0]$14517 $1\data_r0__o_ok$next[0:0]$14515 + assign $2\data_r0__o$next[63:0]$14038 $1\data_r0__o$next[63:0]$14036 + assign $2\data_r0__o_ok$next[0:0]$14039 $1\data_r0__o_ok$next[0:0]$14037 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$14518 1'0 + assign $3\data_r0__o_ok$next[0:0]$14040 1'0 case - assign $3\data_r0__o_ok$next[0:0]$14518 $2\data_r0__o_ok$next[0:0]$14517 + assign $3\data_r0__o_ok$next[0:0]$14040 $2\data_r0__o_ok$next[0:0]$14039 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$14512 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14513 + update \data_r0__o$next $0\data_r0__o$next[63:0]$14034 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14035 end - attribute \src "libresoc.v:200819.3-200840.6" - process $proc$libresoc.v:200819$14519 + attribute \src "libresoc.v:201945.3-201966.6" + process $proc$libresoc.v:201945$14041 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__fast1$next[63:0]$14520 $2\data_r1__fast1$next[63:0]$14524 + assign $0\data_r1__fast1$next[63:0]$14042 $2\data_r1__fast1$next[63:0]$14046 assign { } { } - assign $0\data_r1__fast1_ok$next[0:0]$14521 $3\data_r1__fast1_ok$next[0:0]$14526 - attribute \src "libresoc.v:200820.5-200820.29" + assign $0\data_r1__fast1_ok$next[0:0]$14043 $3\data_r1__fast1_ok$next[0:0]$14048 + attribute \src "libresoc.v:201946.5-201946.29" switch \initial - attribute \src "libresoc.v:200820.9-200820.17" + attribute \src "libresoc.v:201946.9-201946.17" case 1'1 case end @@ -419503,10 +384409,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__fast1_ok$next[0:0]$14523 $1\data_r1__fast1$next[63:0]$14522 } { \fast1_ok \alu_trap0_fast1 } + assign { $1\data_r1__fast1_ok$next[0:0]$14045 $1\data_r1__fast1$next[63:0]$14044 } { \fast1_ok \alu_trap0_fast1 } case - assign $1\data_r1__fast1$next[63:0]$14522 \data_r1__fast1 - assign $1\data_r1__fast1_ok$next[0:0]$14523 \data_r1__fast1_ok + assign $1\data_r1__fast1$next[63:0]$14044 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$14045 \data_r1__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -419514,38 +384420,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__fast1_ok$next[0:0]$14525 $2\data_r1__fast1$next[63:0]$14524 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__fast1_ok$next[0:0]$14047 $2\data_r1__fast1$next[63:0]$14046 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__fast1$next[63:0]$14524 $1\data_r1__fast1$next[63:0]$14522 - assign $2\data_r1__fast1_ok$next[0:0]$14525 $1\data_r1__fast1_ok$next[0:0]$14523 + assign $2\data_r1__fast1$next[63:0]$14046 $1\data_r1__fast1$next[63:0]$14044 + assign $2\data_r1__fast1_ok$next[0:0]$14047 $1\data_r1__fast1_ok$next[0:0]$14045 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__fast1_ok$next[0:0]$14526 1'0 + assign $3\data_r1__fast1_ok$next[0:0]$14048 1'0 case - assign $3\data_r1__fast1_ok$next[0:0]$14526 $2\data_r1__fast1_ok$next[0:0]$14525 + assign $3\data_r1__fast1_ok$next[0:0]$14048 $2\data_r1__fast1_ok$next[0:0]$14047 end sync always - update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14520 - update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14521 + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14042 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14043 end - attribute \src "libresoc.v:200841.3-200862.6" - process $proc$libresoc.v:200841$14527 + attribute \src "libresoc.v:201967.3-201988.6" + process $proc$libresoc.v:201967$14049 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast2$next[63:0]$14528 $2\data_r2__fast2$next[63:0]$14532 + assign $0\data_r2__fast2$next[63:0]$14050 $2\data_r2__fast2$next[63:0]$14054 assign { } { } - assign $0\data_r2__fast2_ok$next[0:0]$14529 $3\data_r2__fast2_ok$next[0:0]$14534 - attribute \src "libresoc.v:200842.5-200842.29" + assign $0\data_r2__fast2_ok$next[0:0]$14051 $3\data_r2__fast2_ok$next[0:0]$14056 + attribute \src "libresoc.v:201968.5-201968.29" switch \initial - attribute \src "libresoc.v:200842.9-200842.17" + attribute \src "libresoc.v:201968.9-201968.17" case 1'1 case end @@ -419555,10 +384461,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast2_ok$next[0:0]$14531 $1\data_r2__fast2$next[63:0]$14530 } { \fast2_ok \alu_trap0_fast2 } + assign { $1\data_r2__fast2_ok$next[0:0]$14053 $1\data_r2__fast2$next[63:0]$14052 } { \fast2_ok \alu_trap0_fast2 } case - assign $1\data_r2__fast2$next[63:0]$14530 \data_r2__fast2 - assign $1\data_r2__fast2_ok$next[0:0]$14531 \data_r2__fast2_ok + assign $1\data_r2__fast2$next[63:0]$14052 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$14053 \data_r2__fast2_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -419566,38 +384472,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast2_ok$next[0:0]$14533 $2\data_r2__fast2$next[63:0]$14532 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast2_ok$next[0:0]$14055 $2\data_r2__fast2$next[63:0]$14054 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast2$next[63:0]$14532 $1\data_r2__fast2$next[63:0]$14530 - assign $2\data_r2__fast2_ok$next[0:0]$14533 $1\data_r2__fast2_ok$next[0:0]$14531 + assign $2\data_r2__fast2$next[63:0]$14054 $1\data_r2__fast2$next[63:0]$14052 + assign $2\data_r2__fast2_ok$next[0:0]$14055 $1\data_r2__fast2_ok$next[0:0]$14053 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast2_ok$next[0:0]$14534 1'0 + assign $3\data_r2__fast2_ok$next[0:0]$14056 1'0 case - assign $3\data_r2__fast2_ok$next[0:0]$14534 $2\data_r2__fast2_ok$next[0:0]$14533 + assign $3\data_r2__fast2_ok$next[0:0]$14056 $2\data_r2__fast2_ok$next[0:0]$14055 end sync always - update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14528 - update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14529 + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14050 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14051 end - attribute \src "libresoc.v:200863.3-200884.6" - process $proc$libresoc.v:200863$14535 + attribute \src "libresoc.v:201989.3-202010.6" + process $proc$libresoc.v:201989$14057 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__nia$next[63:0]$14536 $2\data_r3__nia$next[63:0]$14540 + assign $0\data_r3__nia$next[63:0]$14058 $2\data_r3__nia$next[63:0]$14062 assign { } { } - assign $0\data_r3__nia_ok$next[0:0]$14537 $3\data_r3__nia_ok$next[0:0]$14542 - attribute \src "libresoc.v:200864.5-200864.29" + assign $0\data_r3__nia_ok$next[0:0]$14059 $3\data_r3__nia_ok$next[0:0]$14064 + attribute \src "libresoc.v:201990.5-201990.29" switch \initial - attribute \src "libresoc.v:200864.9-200864.17" + attribute \src "libresoc.v:201990.9-201990.17" case 1'1 case end @@ -419607,10 +384513,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__nia_ok$next[0:0]$14539 $1\data_r3__nia$next[63:0]$14538 } { \nia_ok \alu_trap0_nia } + assign { $1\data_r3__nia_ok$next[0:0]$14061 $1\data_r3__nia$next[63:0]$14060 } { \nia_ok \alu_trap0_nia } case - assign $1\data_r3__nia$next[63:0]$14538 \data_r3__nia - assign $1\data_r3__nia_ok$next[0:0]$14539 \data_r3__nia_ok + assign $1\data_r3__nia$next[63:0]$14060 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$14061 \data_r3__nia_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -419618,38 +384524,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__nia_ok$next[0:0]$14541 $2\data_r3__nia$next[63:0]$14540 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r3__nia_ok$next[0:0]$14063 $2\data_r3__nia$next[63:0]$14062 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r3__nia$next[63:0]$14540 $1\data_r3__nia$next[63:0]$14538 - assign $2\data_r3__nia_ok$next[0:0]$14541 $1\data_r3__nia_ok$next[0:0]$14539 + assign $2\data_r3__nia$next[63:0]$14062 $1\data_r3__nia$next[63:0]$14060 + assign $2\data_r3__nia_ok$next[0:0]$14063 $1\data_r3__nia_ok$next[0:0]$14061 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__nia_ok$next[0:0]$14542 1'0 + assign $3\data_r3__nia_ok$next[0:0]$14064 1'0 case - assign $3\data_r3__nia_ok$next[0:0]$14542 $2\data_r3__nia_ok$next[0:0]$14541 + assign $3\data_r3__nia_ok$next[0:0]$14064 $2\data_r3__nia_ok$next[0:0]$14063 end sync always - update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14536 - update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14537 + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14058 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14059 end - attribute \src "libresoc.v:200885.3-200906.6" - process $proc$libresoc.v:200885$14543 + attribute \src "libresoc.v:202011.3-202032.6" + process $proc$libresoc.v:202011$14065 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__msr$next[63:0]$14544 $2\data_r4__msr$next[63:0]$14548 + assign $0\data_r4__msr$next[63:0]$14066 $2\data_r4__msr$next[63:0]$14070 assign { } { } - assign $0\data_r4__msr_ok$next[0:0]$14545 $3\data_r4__msr_ok$next[0:0]$14550 - attribute \src "libresoc.v:200886.5-200886.29" + assign $0\data_r4__msr_ok$next[0:0]$14067 $3\data_r4__msr_ok$next[0:0]$14072 + attribute \src "libresoc.v:202012.5-202012.29" switch \initial - attribute \src "libresoc.v:200886.9-200886.17" + attribute \src "libresoc.v:202012.9-202012.17" case 1'1 case end @@ -419659,10 +384565,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__msr_ok$next[0:0]$14547 $1\data_r4__msr$next[63:0]$14546 } { \msr_ok \alu_trap0_msr } + assign { $1\data_r4__msr_ok$next[0:0]$14069 $1\data_r4__msr$next[63:0]$14068 } { \msr_ok \alu_trap0_msr } case - assign $1\data_r4__msr$next[63:0]$14546 \data_r4__msr - assign $1\data_r4__msr_ok$next[0:0]$14547 \data_r4__msr_ok + assign $1\data_r4__msr$next[63:0]$14068 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$14069 \data_r4__msr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -419670,32 +384576,32 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__msr_ok$next[0:0]$14549 $2\data_r4__msr$next[63:0]$14548 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r4__msr_ok$next[0:0]$14071 $2\data_r4__msr$next[63:0]$14070 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r4__msr$next[63:0]$14548 $1\data_r4__msr$next[63:0]$14546 - assign $2\data_r4__msr_ok$next[0:0]$14549 $1\data_r4__msr_ok$next[0:0]$14547 + assign $2\data_r4__msr$next[63:0]$14070 $1\data_r4__msr$next[63:0]$14068 + assign $2\data_r4__msr_ok$next[0:0]$14071 $1\data_r4__msr_ok$next[0:0]$14069 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__msr_ok$next[0:0]$14550 1'0 + assign $3\data_r4__msr_ok$next[0:0]$14072 1'0 case - assign $3\data_r4__msr_ok$next[0:0]$14550 $2\data_r4__msr_ok$next[0:0]$14549 + assign $3\data_r4__msr_ok$next[0:0]$14072 $2\data_r4__msr_ok$next[0:0]$14071 end sync always - update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14544 - update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14545 + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14066 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14067 end - attribute \src "libresoc.v:200907.3-200916.6" - process $proc$libresoc.v:200907$14551 + attribute \src "libresoc.v:202033.3-202042.6" + process $proc$libresoc.v:202033$14073 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$14552 $1\src_r0$next[63:0]$14553 - attribute \src "libresoc.v:200908.5-200908.29" + assign $0\src_r0$next[63:0]$14074 $1\src_r0$next[63:0]$14075 + attribute \src "libresoc.v:202034.5-202034.29" switch \initial - attribute \src "libresoc.v:200908.9-200908.17" + attribute \src "libresoc.v:202034.9-202034.17" case 1'1 case end @@ -419704,21 +384610,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$14553 \src1_i + assign $1\src_r0$next[63:0]$14075 \src1_i case - assign $1\src_r0$next[63:0]$14553 \src_r0 + assign $1\src_r0$next[63:0]$14075 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$14552 + update \src_r0$next $0\src_r0$next[63:0]$14074 end - attribute \src "libresoc.v:200917.3-200926.6" - process $proc$libresoc.v:200917$14554 + attribute \src "libresoc.v:202043.3-202052.6" + process $proc$libresoc.v:202043$14076 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$14555 $1\src_r1$next[63:0]$14556 - attribute \src "libresoc.v:200918.5-200918.29" + assign $0\src_r1$next[63:0]$14077 $1\src_r1$next[63:0]$14078 + attribute \src "libresoc.v:202044.5-202044.29" switch \initial - attribute \src "libresoc.v:200918.9-200918.17" + attribute \src "libresoc.v:202044.9-202044.17" case 1'1 case end @@ -419727,21 +384633,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$14556 \src2_i + assign $1\src_r1$next[63:0]$14078 \src2_i case - assign $1\src_r1$next[63:0]$14556 \src_r1 + assign $1\src_r1$next[63:0]$14078 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$14555 + update \src_r1$next $0\src_r1$next[63:0]$14077 end - attribute \src "libresoc.v:200927.3-200936.6" - process $proc$libresoc.v:200927$14557 + attribute \src "libresoc.v:202053.3-202062.6" + process $proc$libresoc.v:202053$14079 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$14558 $1\src_r2$next[63:0]$14559 - attribute \src "libresoc.v:200928.5-200928.29" + assign $0\src_r2$next[63:0]$14080 $1\src_r2$next[63:0]$14081 + attribute \src "libresoc.v:202054.5-202054.29" switch \initial - attribute \src "libresoc.v:200928.9-200928.17" + attribute \src "libresoc.v:202054.9-202054.17" case 1'1 case end @@ -419750,21 +384656,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$14559 \src3_i + assign $1\src_r2$next[63:0]$14081 \src3_i case - assign $1\src_r2$next[63:0]$14559 \src_r2 + assign $1\src_r2$next[63:0]$14081 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$14558 + update \src_r2$next $0\src_r2$next[63:0]$14080 end - attribute \src "libresoc.v:200937.3-200946.6" - process $proc$libresoc.v:200937$14560 + attribute \src "libresoc.v:202063.3-202072.6" + process $proc$libresoc.v:202063$14082 assign { } { } assign { } { } - assign $0\src_r3$next[63:0]$14561 $1\src_r3$next[63:0]$14562 - attribute \src "libresoc.v:200938.5-200938.29" + assign $0\src_r3$next[63:0]$14083 $1\src_r3$next[63:0]$14084 + attribute \src "libresoc.v:202064.5-202064.29" switch \initial - attribute \src "libresoc.v:200938.9-200938.17" + attribute \src "libresoc.v:202064.9-202064.17" case 1'1 case end @@ -419773,21 +384679,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[63:0]$14562 \src4_i + assign $1\src_r3$next[63:0]$14084 \src4_i case - assign $1\src_r3$next[63:0]$14562 \src_r3 + assign $1\src_r3$next[63:0]$14084 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[63:0]$14561 + update \src_r3$next $0\src_r3$next[63:0]$14083 end - attribute \src "libresoc.v:200947.3-200955.6" - process $proc$libresoc.v:200947$14563 + attribute \src "libresoc.v:202073.3-202081.6" + process $proc$libresoc.v:202073$14085 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$14564 $1\alui_l_r_alui$next[0:0]$14565 - attribute \src "libresoc.v:200948.5-200948.29" + assign $0\alui_l_r_alui$next[0:0]$14086 $1\alui_l_r_alui$next[0:0]$14087 + attribute \src "libresoc.v:202074.5-202074.29" switch \initial - attribute \src "libresoc.v:200948.9-200948.17" + attribute \src "libresoc.v:202074.9-202074.17" case 1'1 case end @@ -419796,21 +384702,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$14565 1'1 + assign $1\alui_l_r_alui$next[0:0]$14087 1'1 case - assign $1\alui_l_r_alui$next[0:0]$14565 \$89 + assign $1\alui_l_r_alui$next[0:0]$14087 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14564 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14086 end - attribute \src "libresoc.v:200956.3-200964.6" - process $proc$libresoc.v:200956$14566 + attribute \src "libresoc.v:202082.3-202090.6" + process $proc$libresoc.v:202082$14088 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$14567 $1\alu_l_r_alu$next[0:0]$14568 - attribute \src "libresoc.v:200957.5-200957.29" + assign $0\alu_l_r_alu$next[0:0]$14089 $1\alu_l_r_alu$next[0:0]$14090 + attribute \src "libresoc.v:202083.5-202083.29" switch \initial - attribute \src "libresoc.v:200957.9-200957.17" + attribute \src "libresoc.v:202083.9-202083.17" case 1'1 case end @@ -419819,21 +384725,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$14568 1'1 + assign $1\alu_l_r_alu$next[0:0]$14090 1'1 case - assign $1\alu_l_r_alu$next[0:0]$14568 \$91 + assign $1\alu_l_r_alu$next[0:0]$14090 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14567 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14089 end - attribute \src "libresoc.v:200965.3-200974.6" - process $proc$libresoc.v:200965$14569 + attribute \src "libresoc.v:202091.3-202100.6" + process $proc$libresoc.v:202091$14091 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:200966.5-200966.29" + attribute \src "libresoc.v:202092.5-202092.29" switch \initial - attribute \src "libresoc.v:200966.9-200966.17" + attribute \src "libresoc.v:202092.9-202092.17" case 1'1 case end @@ -419849,14 +384755,14 @@ module \trap0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:200975.3-200984.6" - process $proc$libresoc.v:200975$14570 + attribute \src "libresoc.v:202101.3-202110.6" + process $proc$libresoc.v:202101$14092 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:200976.5-200976.29" + attribute \src "libresoc.v:202102.5-202102.29" switch \initial - attribute \src "libresoc.v:200976.9-200976.17" + attribute \src "libresoc.v:202102.9-202102.17" case 1'1 case end @@ -419872,14 +384778,14 @@ module \trap0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:200985.3-200994.6" - process $proc$libresoc.v:200985$14571 + attribute \src "libresoc.v:202111.3-202120.6" + process $proc$libresoc.v:202111$14093 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:200986.5-200986.29" + attribute \src "libresoc.v:202112.5-202112.29" switch \initial - attribute \src "libresoc.v:200986.9-200986.17" + attribute \src "libresoc.v:202112.9-202112.17" case 1'1 case end @@ -419895,14 +384801,14 @@ module \trap0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:200995.3-201004.6" - process $proc$libresoc.v:200995$14572 + attribute \src "libresoc.v:202121.3-202130.6" + process $proc$libresoc.v:202121$14094 assign { } { } assign { } { } assign $0\dest4_o[63:0] $1\dest4_o[63:0] - attribute \src "libresoc.v:200996.5-200996.29" + attribute \src "libresoc.v:202122.5-202122.29" switch \initial - attribute \src "libresoc.v:200996.9-200996.17" + attribute \src "libresoc.v:202122.9-202122.17" case 1'1 case end @@ -419918,14 +384824,14 @@ module \trap0 sync always update \dest4_o $0\dest4_o[63:0] end - attribute \src "libresoc.v:201005.3-201014.6" - process $proc$libresoc.v:201005$14573 + attribute \src "libresoc.v:202131.3-202140.6" + process $proc$libresoc.v:202131$14095 assign { } { } assign { } { } assign $0\dest5_o[63:0] $1\dest5_o[63:0] - attribute \src "libresoc.v:201006.5-201006.29" + attribute \src "libresoc.v:202132.5-202132.29" switch \initial - attribute \src "libresoc.v:201006.9-201006.17" + attribute \src "libresoc.v:202132.9-202132.17" case 1'1 case end @@ -419941,14 +384847,14 @@ module \trap0 sync always update \dest5_o $0\dest5_o[63:0] end - attribute \src "libresoc.v:201015.3-201023.6" - process $proc$libresoc.v:201015$14574 + attribute \src "libresoc.v:202141.3-202149.6" + process $proc$libresoc.v:202141$14096 assign { } { } assign { } { } - assign $0\prev_wr_go$next[4:0]$14575 $1\prev_wr_go$next[4:0]$14576 - attribute \src "libresoc.v:201016.5-201016.29" + assign $0\prev_wr_go$next[4:0]$14097 $1\prev_wr_go$next[4:0]$14098 + attribute \src "libresoc.v:202142.5-202142.29" switch \initial - attribute \src "libresoc.v:201016.9-201016.17" + attribute \src "libresoc.v:202142.9-202142.17" case 1'1 case end @@ -419957,74 +384863,74 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[4:0]$14576 5'00000 - case - assign $1\prev_wr_go$next[4:0]$14576 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14575 - end - connect \$5 $reduce_and$libresoc.v:200463$14362_Y - connect \$99 $and$libresoc.v:200464$14363_Y - connect \$101 $and$libresoc.v:200465$14364_Y - connect \$103 $and$libresoc.v:200466$14365_Y - connect \$105 $and$libresoc.v:200467$14366_Y - connect \$107 $and$libresoc.v:200468$14367_Y - connect \$109 $and$libresoc.v:200469$14368_Y - connect \$111 $and$libresoc.v:200470$14369_Y - connect \$113 $and$libresoc.v:200471$14370_Y - connect \$115 $and$libresoc.v:200472$14371_Y - connect \$117 $and$libresoc.v:200473$14372_Y - connect \$11 $and$libresoc.v:200474$14373_Y - connect \$119 $and$libresoc.v:200475$14374_Y - connect \$121 $and$libresoc.v:200476$14375_Y - connect \$123 $and$libresoc.v:200477$14376_Y - connect \$13 $not$libresoc.v:200478$14377_Y - connect \$15 $and$libresoc.v:200479$14378_Y - connect \$17 $not$libresoc.v:200480$14379_Y - connect \$19 $and$libresoc.v:200481$14380_Y - connect \$21 $and$libresoc.v:200482$14381_Y - connect \$25 $not$libresoc.v:200483$14382_Y - connect \$27 $and$libresoc.v:200484$14383_Y - connect \$24 $reduce_or$libresoc.v:200485$14384_Y - connect \$23 $not$libresoc.v:200486$14385_Y - connect \$31 $and$libresoc.v:200487$14386_Y - connect \$33 $reduce_or$libresoc.v:200488$14387_Y - connect \$35 $reduce_or$libresoc.v:200489$14388_Y - connect \$37 $or$libresoc.v:200490$14389_Y - connect \$3 $and$libresoc.v:200491$14390_Y - connect \$39 $not$libresoc.v:200492$14391_Y - connect \$41 $and$libresoc.v:200493$14392_Y - connect \$43 $and$libresoc.v:200494$14393_Y - connect \$45 $eq$libresoc.v:200495$14394_Y - connect \$47 $and$libresoc.v:200496$14395_Y - connect \$49 $eq$libresoc.v:200497$14396_Y - connect \$51 $and$libresoc.v:200498$14397_Y - connect \$53 $and$libresoc.v:200499$14398_Y - connect \$55 $and$libresoc.v:200500$14399_Y - connect \$57 $or$libresoc.v:200501$14400_Y - connect \$59 $or$libresoc.v:200502$14401_Y - connect \$61 $or$libresoc.v:200503$14402_Y - connect \$63 $or$libresoc.v:200504$14403_Y - connect \$65 $and$libresoc.v:200505$14404_Y - connect \$67 $and$libresoc.v:200506$14405_Y - connect \$6 $not$libresoc.v:200507$14406_Y - connect \$69 $or$libresoc.v:200508$14407_Y - connect \$71 $and$libresoc.v:200509$14408_Y - connect \$73 $and$libresoc.v:200510$14409_Y - connect \$75 $and$libresoc.v:200511$14410_Y - connect \$77 $and$libresoc.v:200512$14411_Y - connect \$79 $and$libresoc.v:200513$14412_Y - connect \$81 $ternary$libresoc.v:200514$14413_Y - connect \$83 $ternary$libresoc.v:200515$14414_Y - connect \$85 $ternary$libresoc.v:200516$14415_Y - connect \$87 $ternary$libresoc.v:200517$14416_Y - connect \$8 $or$libresoc.v:200518$14417_Y - connect \$89 $and$libresoc.v:200519$14418_Y - connect \$91 $and$libresoc.v:200520$14419_Y - connect \$93 $and$libresoc.v:200521$14420_Y - connect \$95 $and$libresoc.v:200522$14421_Y - connect \$97 $not$libresoc.v:200523$14422_Y + assign $1\prev_wr_go$next[4:0]$14098 5'00000 + case + assign $1\prev_wr_go$next[4:0]$14098 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14097 + end + connect \$5 $reduce_and$libresoc.v:201589$13884_Y + connect \$99 $and$libresoc.v:201590$13885_Y + connect \$101 $and$libresoc.v:201591$13886_Y + connect \$103 $and$libresoc.v:201592$13887_Y + connect \$105 $and$libresoc.v:201593$13888_Y + connect \$107 $and$libresoc.v:201594$13889_Y + connect \$109 $and$libresoc.v:201595$13890_Y + connect \$111 $and$libresoc.v:201596$13891_Y + connect \$113 $and$libresoc.v:201597$13892_Y + connect \$115 $and$libresoc.v:201598$13893_Y + connect \$117 $and$libresoc.v:201599$13894_Y + connect \$11 $and$libresoc.v:201600$13895_Y + connect \$119 $and$libresoc.v:201601$13896_Y + connect \$121 $and$libresoc.v:201602$13897_Y + connect \$123 $and$libresoc.v:201603$13898_Y + connect \$13 $not$libresoc.v:201604$13899_Y + connect \$15 $and$libresoc.v:201605$13900_Y + connect \$17 $not$libresoc.v:201606$13901_Y + connect \$19 $and$libresoc.v:201607$13902_Y + connect \$21 $and$libresoc.v:201608$13903_Y + connect \$25 $not$libresoc.v:201609$13904_Y + connect \$27 $and$libresoc.v:201610$13905_Y + connect \$24 $reduce_or$libresoc.v:201611$13906_Y + connect \$23 $not$libresoc.v:201612$13907_Y + connect \$31 $and$libresoc.v:201613$13908_Y + connect \$33 $reduce_or$libresoc.v:201614$13909_Y + connect \$35 $reduce_or$libresoc.v:201615$13910_Y + connect \$37 $or$libresoc.v:201616$13911_Y + connect \$3 $and$libresoc.v:201617$13912_Y + connect \$39 $not$libresoc.v:201618$13913_Y + connect \$41 $and$libresoc.v:201619$13914_Y + connect \$43 $and$libresoc.v:201620$13915_Y + connect \$45 $eq$libresoc.v:201621$13916_Y + connect \$47 $and$libresoc.v:201622$13917_Y + connect \$49 $eq$libresoc.v:201623$13918_Y + connect \$51 $and$libresoc.v:201624$13919_Y + connect \$53 $and$libresoc.v:201625$13920_Y + connect \$55 $and$libresoc.v:201626$13921_Y + connect \$57 $or$libresoc.v:201627$13922_Y + connect \$59 $or$libresoc.v:201628$13923_Y + connect \$61 $or$libresoc.v:201629$13924_Y + connect \$63 $or$libresoc.v:201630$13925_Y + connect \$65 $and$libresoc.v:201631$13926_Y + connect \$67 $and$libresoc.v:201632$13927_Y + connect \$6 $not$libresoc.v:201633$13928_Y + connect \$69 $or$libresoc.v:201634$13929_Y + connect \$71 $and$libresoc.v:201635$13930_Y + connect \$73 $and$libresoc.v:201636$13931_Y + connect \$75 $and$libresoc.v:201637$13932_Y + connect \$77 $and$libresoc.v:201638$13933_Y + connect \$79 $and$libresoc.v:201639$13934_Y + connect \$81 $ternary$libresoc.v:201640$13935_Y + connect \$83 $ternary$libresoc.v:201641$13936_Y + connect \$85 $ternary$libresoc.v:201642$13937_Y + connect \$87 $ternary$libresoc.v:201643$13938_Y + connect \$8 $or$libresoc.v:201644$13939_Y + connect \$89 $and$libresoc.v:201645$13940_Y + connect \$91 $and$libresoc.v:201646$13941_Y + connect \$93 $and$libresoc.v:201647$13942_Y + connect \$95 $and$libresoc.v:201648$13943_Y + connect \$97 $not$libresoc.v:201649$13944_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$113 @@ -420055,37 +384961,37 @@ module \trap0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:201057.1-201115.10" +attribute \src "libresoc.v:202183.1-202241.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" attribute \generator "nMigen" module \upd_l - attribute \src "libresoc.v:201058.7-201058.20" + attribute \src "libresoc.v:202184.7-202184.20" wire $0\initial[0:0] - attribute \src "libresoc.v:201103.3-201111.6" - wire $0\q_int$next[0:0]$14626 - attribute \src "libresoc.v:201101.3-201102.27" + attribute \src "libresoc.v:202229.3-202237.6" + wire $0\q_int$next[0:0]$14148 + attribute \src "libresoc.v:202227.3-202228.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:201103.3-201111.6" - wire $1\q_int$next[0:0]$14627 - attribute \src "libresoc.v:201080.7-201080.19" + attribute \src "libresoc.v:202229.3-202237.6" + wire $1\q_int$next[0:0]$14149 + attribute \src "libresoc.v:202206.7-202206.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:201093.17-201093.96" - wire $and$libresoc.v:201093$14616_Y - attribute \src "libresoc.v:201098.17-201098.96" - wire $and$libresoc.v:201098$14621_Y - attribute \src "libresoc.v:201095.18-201095.93" - wire $not$libresoc.v:201095$14618_Y - attribute \src "libresoc.v:201097.17-201097.92" - wire $not$libresoc.v:201097$14620_Y - attribute \src "libresoc.v:201100.17-201100.92" - wire $not$libresoc.v:201100$14623_Y - attribute \src "libresoc.v:201094.18-201094.98" - wire $or$libresoc.v:201094$14617_Y - attribute \src "libresoc.v:201096.18-201096.99" - wire $or$libresoc.v:201096$14619_Y - attribute \src "libresoc.v:201099.17-201099.97" - wire $or$libresoc.v:201099$14622_Y + attribute \src "libresoc.v:202219.17-202219.96" + wire $and$libresoc.v:202219$14138_Y + attribute \src "libresoc.v:202224.17-202224.96" + wire $and$libresoc.v:202224$14143_Y + attribute \src "libresoc.v:202221.18-202221.93" + wire $not$libresoc.v:202221$14140_Y + attribute \src "libresoc.v:202223.17-202223.92" + wire $not$libresoc.v:202223$14142_Y + attribute \src "libresoc.v:202226.17-202226.92" + wire $not$libresoc.v:202226$14145_Y + attribute \src "libresoc.v:202220.18-202220.98" + wire $or$libresoc.v:202220$14139_Y + attribute \src "libresoc.v:202222.18-202222.99" + wire $or$libresoc.v:202222$14141_Y + attribute \src "libresoc.v:202225.17-202225.97" + wire $or$libresoc.v:202225$14144_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -420102,11 +385008,11 @@ module \upd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:201058.7-201058.15" + attribute \src "libresoc.v:202184.7-202184.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -420123,7 +385029,7 @@ module \upd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:201093$14616 + cell $and $and$libresoc.v:202219$14138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420131,10 +385037,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:201093$14616_Y + connect \Y $and$libresoc.v:202219$14138_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:201098$14621 + cell $and $and$libresoc.v:202224$14143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420142,34 +385048,34 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:201098$14621_Y + connect \Y $and$libresoc.v:202224$14143_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:201095$14618 + cell $not $not$libresoc.v:202221$14140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_upd - connect \Y $not$libresoc.v:201095$14618_Y + connect \Y $not$libresoc.v:202221$14140_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:201097$14620 + cell $not $not$libresoc.v:202223$14142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:201097$14620_Y + connect \Y $not$libresoc.v:202223$14142_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:201100$14623 + cell $not $not$libresoc.v:202226$14145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:201100$14623_Y + connect \Y $not$libresoc.v:202226$14145_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:201094$14617 + cell $or $or$libresoc.v:202220$14139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420177,10 +385083,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_upd - connect \Y $or$libresoc.v:201094$14617_Y + connect \Y $or$libresoc.v:202220$14139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:201096$14619 + cell $or $or$libresoc.v:202222$14141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420188,10 +385094,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_upd connect \B \q_int - connect \Y $or$libresoc.v:201096$14619_Y + connect \Y $or$libresoc.v:202222$14141_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:201099$14622 + cell $or $or$libresoc.v:202225$14144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420199,39 +385105,39 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_upd - connect \Y $or$libresoc.v:201099$14622_Y + connect \Y $or$libresoc.v:202225$14144_Y end - attribute \src "libresoc.v:201058.7-201058.20" - process $proc$libresoc.v:201058$14628 + attribute \src "libresoc.v:202184.7-202184.20" + process $proc$libresoc.v:202184$14150 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:201080.7-201080.19" - process $proc$libresoc.v:201080$14629 + attribute \src "libresoc.v:202206.7-202206.19" + process $proc$libresoc.v:202206$14151 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:201101.3-201102.27" - process $proc$libresoc.v:201101$14624 + attribute \src "libresoc.v:202227.3-202228.27" + process $proc$libresoc.v:202227$14146 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:201103.3-201111.6" - process $proc$libresoc.v:201103$14625 + attribute \src "libresoc.v:202229.3-202237.6" + process $proc$libresoc.v:202229$14147 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14626 $1\q_int$next[0:0]$14627 - attribute \src "libresoc.v:201104.5-201104.29" + assign $0\q_int$next[0:0]$14148 $1\q_int$next[0:0]$14149 + attribute \src "libresoc.v:202230.5-202230.29" switch \initial - attribute \src "libresoc.v:201104.9-201104.17" + attribute \src "libresoc.v:202230.9-202230.17" case 1'1 case end @@ -420240,56 +385146,56 @@ module \upd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14627 1'0 + assign $1\q_int$next[0:0]$14149 1'0 case - assign $1\q_int$next[0:0]$14627 \$5 + assign $1\q_int$next[0:0]$14149 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14626 + update \q_int$next $0\q_int$next[0:0]$14148 end - connect \$9 $and$libresoc.v:201093$14616_Y - connect \$11 $or$libresoc.v:201094$14617_Y - connect \$13 $not$libresoc.v:201095$14618_Y - connect \$15 $or$libresoc.v:201096$14619_Y - connect \$1 $not$libresoc.v:201097$14620_Y - connect \$3 $and$libresoc.v:201098$14621_Y - connect \$5 $or$libresoc.v:201099$14622_Y - connect \$7 $not$libresoc.v:201100$14623_Y + connect \$9 $and$libresoc.v:202219$14138_Y + connect \$11 $or$libresoc.v:202220$14139_Y + connect \$13 $not$libresoc.v:202221$14140_Y + connect \$15 $or$libresoc.v:202222$14141_Y + connect \$1 $not$libresoc.v:202223$14142_Y + connect \$3 $and$libresoc.v:202224$14143_Y + connect \$5 $or$libresoc.v:202225$14144_Y + connect \$7 $not$libresoc.v:202226$14145_Y connect \qlq_upd \$15 connect \qn_upd \$13 connect \q_upd \$11 end -attribute \src "libresoc.v:201119.1-201177.10" +attribute \src "libresoc.v:202245.1-202303.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" attribute \generator "nMigen" module \valid_l - attribute \src "libresoc.v:201120.7-201120.20" + attribute \src "libresoc.v:202246.7-202246.20" wire $0\initial[0:0] - attribute \src "libresoc.v:201165.3-201173.6" - wire $0\q_int$next[0:0]$14640 - attribute \src "libresoc.v:201163.3-201164.27" + attribute \src "libresoc.v:202291.3-202299.6" + wire $0\q_int$next[0:0]$14162 + attribute \src "libresoc.v:202289.3-202290.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:201165.3-201173.6" - wire $1\q_int$next[0:0]$14641 - attribute \src "libresoc.v:201142.7-201142.19" + attribute \src "libresoc.v:202291.3-202299.6" + wire $1\q_int$next[0:0]$14163 + attribute \src "libresoc.v:202268.7-202268.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:201155.17-201155.96" - wire $and$libresoc.v:201155$14630_Y - attribute \src "libresoc.v:201160.17-201160.96" - wire $and$libresoc.v:201160$14635_Y - attribute \src "libresoc.v:201157.18-201157.95" - wire $not$libresoc.v:201157$14632_Y - attribute \src "libresoc.v:201159.17-201159.94" - wire $not$libresoc.v:201159$14634_Y - attribute \src "libresoc.v:201162.17-201162.94" - wire $not$libresoc.v:201162$14637_Y - attribute \src "libresoc.v:201156.18-201156.100" - wire $or$libresoc.v:201156$14631_Y - attribute \src "libresoc.v:201158.18-201158.101" - wire $or$libresoc.v:201158$14633_Y - attribute \src "libresoc.v:201161.17-201161.99" - wire $or$libresoc.v:201161$14636_Y + attribute \src "libresoc.v:202281.17-202281.96" + wire $and$libresoc.v:202281$14152_Y + attribute \src "libresoc.v:202286.17-202286.96" + wire $and$libresoc.v:202286$14157_Y + attribute \src "libresoc.v:202283.18-202283.95" + wire $not$libresoc.v:202283$14154_Y + attribute \src "libresoc.v:202285.17-202285.94" + wire $not$libresoc.v:202285$14156_Y + attribute \src "libresoc.v:202288.17-202288.94" + wire $not$libresoc.v:202288$14159_Y + attribute \src "libresoc.v:202282.18-202282.100" + wire $or$libresoc.v:202282$14153_Y + attribute \src "libresoc.v:202284.18-202284.101" + wire $or$libresoc.v:202284$14155_Y + attribute \src "libresoc.v:202287.17-202287.99" + wire $or$libresoc.v:202287$14158_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -420306,11 +385212,11 @@ module \valid_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:201120.7-201120.15" + attribute \src "libresoc.v:202246.7-202246.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -420327,7 +385233,7 @@ module \valid_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:201155$14630 + cell $and $and$libresoc.v:202281$14152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420335,10 +385241,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:201155$14630_Y + connect \Y $and$libresoc.v:202281$14152_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:201160$14635 + cell $and $and$libresoc.v:202286$14157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420346,34 +385252,34 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:201160$14635_Y + connect \Y $and$libresoc.v:202286$14157_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:201157$14632 + cell $not $not$libresoc.v:202283$14154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_valid - connect \Y $not$libresoc.v:201157$14632_Y + connect \Y $not$libresoc.v:202283$14154_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:201159$14634 + cell $not $not$libresoc.v:202285$14156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:201159$14634_Y + connect \Y $not$libresoc.v:202285$14156_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:201162$14637 + cell $not $not$libresoc.v:202288$14159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:201162$14637_Y + connect \Y $not$libresoc.v:202288$14159_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:201156$14631 + cell $or $or$libresoc.v:202282$14153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420381,10 +385287,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_valid - connect \Y $or$libresoc.v:201156$14631_Y + connect \Y $or$libresoc.v:202282$14153_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:201158$14633 + cell $or $or$libresoc.v:202284$14155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420392,10 +385298,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_valid connect \B \q_int - connect \Y $or$libresoc.v:201158$14633_Y + connect \Y $or$libresoc.v:202284$14155_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:201161$14636 + cell $or $or$libresoc.v:202287$14158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420403,39 +385309,39 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_valid - connect \Y $or$libresoc.v:201161$14636_Y + connect \Y $or$libresoc.v:202287$14158_Y end - attribute \src "libresoc.v:201120.7-201120.20" - process $proc$libresoc.v:201120$14642 + attribute \src "libresoc.v:202246.7-202246.20" + process $proc$libresoc.v:202246$14164 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:201142.7-201142.19" - process $proc$libresoc.v:201142$14643 + attribute \src "libresoc.v:202268.7-202268.19" + process $proc$libresoc.v:202268$14165 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:201163.3-201164.27" - process $proc$libresoc.v:201163$14638 + attribute \src "libresoc.v:202289.3-202290.27" + process $proc$libresoc.v:202289$14160 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:201165.3-201173.6" - process $proc$libresoc.v:201165$14639 + attribute \src "libresoc.v:202291.3-202299.6" + process $proc$libresoc.v:202291$14161 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14640 $1\q_int$next[0:0]$14641 - attribute \src "libresoc.v:201166.5-201166.29" + assign $0\q_int$next[0:0]$14162 $1\q_int$next[0:0]$14163 + attribute \src "libresoc.v:202292.5-202292.29" switch \initial - attribute \src "libresoc.v:201166.9-201166.17" + attribute \src "libresoc.v:202292.9-202292.17" case 1'1 case end @@ -420444,56 +385350,56 @@ module \valid_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14641 1'0 + assign $1\q_int$next[0:0]$14163 1'0 case - assign $1\q_int$next[0:0]$14641 \$5 + assign $1\q_int$next[0:0]$14163 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14640 + update \q_int$next $0\q_int$next[0:0]$14162 end - connect \$9 $and$libresoc.v:201155$14630_Y - connect \$11 $or$libresoc.v:201156$14631_Y - connect \$13 $not$libresoc.v:201157$14632_Y - connect \$15 $or$libresoc.v:201158$14633_Y - connect \$1 $not$libresoc.v:201159$14634_Y - connect \$3 $and$libresoc.v:201160$14635_Y - connect \$5 $or$libresoc.v:201161$14636_Y - connect \$7 $not$libresoc.v:201162$14637_Y + connect \$9 $and$libresoc.v:202281$14152_Y + connect \$11 $or$libresoc.v:202282$14153_Y + connect \$13 $not$libresoc.v:202283$14154_Y + connect \$15 $or$libresoc.v:202284$14155_Y + connect \$1 $not$libresoc.v:202285$14156_Y + connect \$3 $and$libresoc.v:202286$14157_Y + connect \$5 $or$libresoc.v:202287$14158_Y + connect \$7 $not$libresoc.v:202288$14159_Y connect \qlq_valid \$15 connect \qn_valid \$13 connect \q_valid \$11 end -attribute \src "libresoc.v:201181.1-201239.10" +attribute \src "libresoc.v:202307.1-202365.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" attribute \generator "nMigen" module \wri_l - attribute \src "libresoc.v:201182.7-201182.20" + attribute \src "libresoc.v:202308.7-202308.20" wire $0\initial[0:0] - attribute \src "libresoc.v:201227.3-201235.6" - wire $0\q_int$next[0:0]$14654 - attribute \src "libresoc.v:201225.3-201226.27" + attribute \src "libresoc.v:202353.3-202361.6" + wire $0\q_int$next[0:0]$14176 + attribute \src "libresoc.v:202351.3-202352.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:201227.3-201235.6" - wire $1\q_int$next[0:0]$14655 - attribute \src "libresoc.v:201204.7-201204.19" + attribute \src "libresoc.v:202353.3-202361.6" + wire $1\q_int$next[0:0]$14177 + attribute \src "libresoc.v:202330.7-202330.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:201217.17-201217.96" - wire $and$libresoc.v:201217$14644_Y - attribute \src "libresoc.v:201222.17-201222.96" - wire $and$libresoc.v:201222$14649_Y - attribute \src "libresoc.v:201219.18-201219.93" - wire $not$libresoc.v:201219$14646_Y - attribute \src "libresoc.v:201221.17-201221.92" - wire $not$libresoc.v:201221$14648_Y - attribute \src "libresoc.v:201224.17-201224.92" - wire $not$libresoc.v:201224$14651_Y - attribute \src "libresoc.v:201218.18-201218.98" - wire $or$libresoc.v:201218$14645_Y - attribute \src "libresoc.v:201220.18-201220.99" - wire $or$libresoc.v:201220$14647_Y - attribute \src "libresoc.v:201223.17-201223.97" - wire $or$libresoc.v:201223$14650_Y + attribute \src "libresoc.v:202343.17-202343.96" + wire $and$libresoc.v:202343$14166_Y + attribute \src "libresoc.v:202348.17-202348.96" + wire $and$libresoc.v:202348$14171_Y + attribute \src "libresoc.v:202345.18-202345.93" + wire $not$libresoc.v:202345$14168_Y + attribute \src "libresoc.v:202347.17-202347.92" + wire $not$libresoc.v:202347$14170_Y + attribute \src "libresoc.v:202350.17-202350.92" + wire $not$libresoc.v:202350$14173_Y + attribute \src "libresoc.v:202344.18-202344.98" + wire $or$libresoc.v:202344$14167_Y + attribute \src "libresoc.v:202346.18-202346.99" + wire $or$libresoc.v:202346$14169_Y + attribute \src "libresoc.v:202349.17-202349.97" + wire $or$libresoc.v:202349$14172_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -420510,11 +385416,11 @@ module \wri_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst - attribute \src "libresoc.v:201182.7-201182.15" + attribute \src "libresoc.v:202308.7-202308.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -420531,7 +385437,7 @@ module \wri_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:201217$14644 + cell $and $and$libresoc.v:202343$14166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420539,10 +385445,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:201217$14644_Y + connect \Y $and$libresoc.v:202343$14166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:201222$14649 + cell $and $and$libresoc.v:202348$14171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420550,34 +385456,34 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:201222$14649_Y + connect \Y $and$libresoc.v:202348$14171_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:201219$14646 + cell $not $not$libresoc.v:202345$14168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_wri - connect \Y $not$libresoc.v:201219$14646_Y + connect \Y $not$libresoc.v:202345$14168_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:201221$14648 + cell $not $not$libresoc.v:202347$14170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:201221$14648_Y + connect \Y $not$libresoc.v:202347$14170_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:201224$14651 + cell $not $not$libresoc.v:202350$14173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:201224$14651_Y + connect \Y $not$libresoc.v:202350$14173_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:201218$14645 + cell $or $or$libresoc.v:202344$14167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420585,10 +385491,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_wri - connect \Y $or$libresoc.v:201218$14645_Y + connect \Y $or$libresoc.v:202344$14167_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:201220$14647 + cell $or $or$libresoc.v:202346$14169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420596,10 +385502,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_wri connect \B \q_int - connect \Y $or$libresoc.v:201220$14647_Y + connect \Y $or$libresoc.v:202346$14169_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:201223$14650 + cell $or $or$libresoc.v:202349$14172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420607,39 +385513,39 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_wri - connect \Y $or$libresoc.v:201223$14650_Y + connect \Y $or$libresoc.v:202349$14172_Y end - attribute \src "libresoc.v:201182.7-201182.20" - process $proc$libresoc.v:201182$14656 + attribute \src "libresoc.v:202308.7-202308.20" + process $proc$libresoc.v:202308$14178 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:201204.7-201204.19" - process $proc$libresoc.v:201204$14657 + attribute \src "libresoc.v:202330.7-202330.19" + process $proc$libresoc.v:202330$14179 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:201225.3-201226.27" - process $proc$libresoc.v:201225$14652 + attribute \src "libresoc.v:202351.3-202352.27" + process $proc$libresoc.v:202351$14174 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:201227.3-201235.6" - process $proc$libresoc.v:201227$14653 + attribute \src "libresoc.v:202353.3-202361.6" + process $proc$libresoc.v:202353$14175 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14654 $1\q_int$next[0:0]$14655 - attribute \src "libresoc.v:201228.5-201228.29" + assign $0\q_int$next[0:0]$14176 $1\q_int$next[0:0]$14177 + attribute \src "libresoc.v:202354.5-202354.29" switch \initial - attribute \src "libresoc.v:201228.9-201228.17" + attribute \src "libresoc.v:202354.9-202354.17" case 1'1 case end @@ -420648,54 +385554,54 @@ module \wri_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14655 1'0 + assign $1\q_int$next[0:0]$14177 1'0 case - assign $1\q_int$next[0:0]$14655 \$5 + assign $1\q_int$next[0:0]$14177 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14654 + update \q_int$next $0\q_int$next[0:0]$14176 end - connect \$9 $and$libresoc.v:201217$14644_Y - connect \$11 $or$libresoc.v:201218$14645_Y - connect \$13 $not$libresoc.v:201219$14646_Y - connect \$15 $or$libresoc.v:201220$14647_Y - connect \$1 $not$libresoc.v:201221$14648_Y - connect \$3 $and$libresoc.v:201222$14649_Y - connect \$5 $or$libresoc.v:201223$14650_Y - connect \$7 $not$libresoc.v:201224$14651_Y + connect \$9 $and$libresoc.v:202343$14166_Y + connect \$11 $or$libresoc.v:202344$14167_Y + connect \$13 $not$libresoc.v:202345$14168_Y + connect \$15 $or$libresoc.v:202346$14169_Y + connect \$1 $not$libresoc.v:202347$14170_Y + connect \$3 $and$libresoc.v:202348$14171_Y + connect \$5 $or$libresoc.v:202349$14172_Y + connect \$7 $not$libresoc.v:202350$14173_Y connect \qlq_wri \$15 connect \qn_wri \$13 connect \q_wri \$11 end -attribute \src "libresoc.v:201243.1-201309.10" +attribute \src "libresoc.v:202369.1-202435.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" attribute \generator "nMigen" module \wrpick_CR_cr_a - attribute \src "libresoc.v:201288.17-201288.91" - wire $not$libresoc.v:201288$14658_Y - attribute \src "libresoc.v:201290.18-201290.93" - wire $not$libresoc.v:201290$14660_Y - attribute \src "libresoc.v:201292.18-201292.93" - wire $not$libresoc.v:201292$14662_Y - attribute \src "libresoc.v:201293.17-201293.89" - wire width 6 $not$libresoc.v:201293$14663_Y - attribute \src "libresoc.v:201295.18-201295.93" - wire $not$libresoc.v:201295$14665_Y - attribute \src "libresoc.v:201298.17-201298.91" - wire $not$libresoc.v:201298$14668_Y - attribute \src "libresoc.v:201289.18-201289.106" - wire $reduce_or$libresoc.v:201289$14659_Y - attribute \src "libresoc.v:201291.18-201291.106" - wire $reduce_or$libresoc.v:201291$14661_Y - attribute \src "libresoc.v:201294.18-201294.106" - wire $reduce_or$libresoc.v:201294$14664_Y - attribute \src "libresoc.v:201296.18-201296.90" - wire $reduce_or$libresoc.v:201296$14666_Y - attribute \src "libresoc.v:201297.17-201297.103" - wire $reduce_or$libresoc.v:201297$14667_Y - attribute \src "libresoc.v:201299.17-201299.105" - wire $reduce_or$libresoc.v:201299$14669_Y + attribute \src "libresoc.v:202414.17-202414.91" + wire $not$libresoc.v:202414$14180_Y + attribute \src "libresoc.v:202416.18-202416.93" + wire $not$libresoc.v:202416$14182_Y + attribute \src "libresoc.v:202418.18-202418.93" + wire $not$libresoc.v:202418$14184_Y + attribute \src "libresoc.v:202419.17-202419.89" + wire width 6 $not$libresoc.v:202419$14185_Y + attribute \src "libresoc.v:202421.18-202421.93" + wire $not$libresoc.v:202421$14187_Y + attribute \src "libresoc.v:202424.17-202424.91" + wire $not$libresoc.v:202424$14190_Y + attribute \src "libresoc.v:202415.18-202415.106" + wire $reduce_or$libresoc.v:202415$14181_Y + attribute \src "libresoc.v:202417.18-202417.106" + wire $reduce_or$libresoc.v:202417$14183_Y + attribute \src "libresoc.v:202420.18-202420.106" + wire $reduce_or$libresoc.v:202420$14186_Y + attribute \src "libresoc.v:202422.18-202422.90" + wire $reduce_or$libresoc.v:202422$14188_Y + attribute \src "libresoc.v:202423.17-202423.103" + wire $reduce_or$libresoc.v:202423$14189_Y + attribute \src "libresoc.v:202425.17-202425.105" + wire $reduce_or$libresoc.v:202425$14191_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -420741,113 +385647,113 @@ module \wrpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201288$14658 + cell $not $not$libresoc.v:202414$14180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:201288$14658_Y + connect \Y $not$libresoc.v:202414$14180_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201290$14660 + cell $not $not$libresoc.v:202416$14182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:201290$14660_Y + connect \Y $not$libresoc.v:202416$14182_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201292$14662 + cell $not $not$libresoc.v:202418$14184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:201292$14662_Y + connect \Y $not$libresoc.v:202418$14184_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201293$14663 + cell $not $not$libresoc.v:202419$14185 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:201293$14663_Y + connect \Y $not$libresoc.v:202419$14185_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201295$14665 + cell $not $not$libresoc.v:202421$14187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:201295$14665_Y + connect \Y $not$libresoc.v:202421$14187_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201298$14668 + cell $not $not$libresoc.v:202424$14190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:201298$14668_Y + connect \Y $not$libresoc.v:202424$14190_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201289$14659 + cell $reduce_or $reduce_or$libresoc.v:202415$14181 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:201289$14659_Y + connect \Y $reduce_or$libresoc.v:202415$14181_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201291$14661 + cell $reduce_or $reduce_or$libresoc.v:202417$14183 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:201291$14661_Y + connect \Y $reduce_or$libresoc.v:202417$14183_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201294$14664 + cell $reduce_or $reduce_or$libresoc.v:202420$14186 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:201294$14664_Y + connect \Y $reduce_or$libresoc.v:202420$14186_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201296$14666 + cell $reduce_or $reduce_or$libresoc.v:202422$14188 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201296$14666_Y + connect \Y $reduce_or$libresoc.v:202422$14188_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201297$14667 + cell $reduce_or $reduce_or$libresoc.v:202423$14189 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:201297$14667_Y + connect \Y $reduce_or$libresoc.v:202423$14189_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201299$14669 + cell $reduce_or $reduce_or$libresoc.v:202425$14191 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:201299$14669_Y - end - connect \$7 $not$libresoc.v:201288$14658_Y - connect \$12 $reduce_or$libresoc.v:201289$14659_Y - connect \$11 $not$libresoc.v:201290$14660_Y - connect \$16 $reduce_or$libresoc.v:201291$14661_Y - connect \$15 $not$libresoc.v:201292$14662_Y - connect \$1 $not$libresoc.v:201293$14663_Y - connect \$20 $reduce_or$libresoc.v:201294$14664_Y - connect \$19 $not$libresoc.v:201295$14665_Y - connect \$23 $reduce_or$libresoc.v:201296$14666_Y - connect \$4 $reduce_or$libresoc.v:201297$14667_Y - connect \$3 $not$libresoc.v:201298$14668_Y - connect \$8 $reduce_or$libresoc.v:201299$14669_Y + connect \Y $reduce_or$libresoc.v:202425$14191_Y + end + connect \$7 $not$libresoc.v:202414$14180_Y + connect \$12 $reduce_or$libresoc.v:202415$14181_Y + connect \$11 $not$libresoc.v:202416$14182_Y + connect \$16 $reduce_or$libresoc.v:202417$14183_Y + connect \$15 $not$libresoc.v:202418$14184_Y + connect \$1 $not$libresoc.v:202419$14185_Y + connect \$20 $reduce_or$libresoc.v:202420$14186_Y + connect \$19 $not$libresoc.v:202421$14187_Y + connect \$23 $reduce_or$libresoc.v:202422$14188_Y + connect \$4 $reduce_or$libresoc.v:202423$14189_Y + connect \$3 $not$libresoc.v:202424$14190_Y + connect \$8 $reduce_or$libresoc.v:202425$14191_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -420858,15 +385764,15 @@ module \wrpick_CR_cr_a connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:201313.1-201334.10" +attribute \src "libresoc.v:202439.1-202460.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" attribute \generator "nMigen" module \wrpick_CR_full_cr - attribute \src "libresoc.v:201328.17-201328.89" - wire $not$libresoc.v:201328$14670_Y - attribute \src "libresoc.v:201329.17-201329.89" - wire $reduce_or$libresoc.v:201329$14671_Y + attribute \src "libresoc.v:202454.17-202454.89" + wire $not$libresoc.v:202454$14192_Y + attribute \src "libresoc.v:202455.17-202455.89" + wire $reduce_or$libresoc.v:202455$14193_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -420882,53 +385788,53 @@ module \wrpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201328$14670 + cell $not $not$libresoc.v:202454$14192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:201328$14670_Y + connect \Y $not$libresoc.v:202454$14192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201329$14671 + cell $reduce_or $reduce_or$libresoc.v:202455$14193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201329$14671_Y + connect \Y $reduce_or$libresoc.v:202455$14193_Y end - connect \$1 $not$libresoc.v:201328$14670_Y - connect \$3 $reduce_or$libresoc.v:201329$14671_Y + connect \$1 $not$libresoc.v:202454$14192_Y + connect \$3 $reduce_or$libresoc.v:202455$14193_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:201338.1-201395.10" +attribute \src "libresoc.v:202464.1-202521.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" attribute \generator "nMigen" module \wrpick_FAST_fast1 - attribute \src "libresoc.v:201377.17-201377.91" - wire $not$libresoc.v:201377$14672_Y - attribute \src "libresoc.v:201379.18-201379.93" - wire $not$libresoc.v:201379$14674_Y - attribute \src "libresoc.v:201381.18-201381.93" - wire $not$libresoc.v:201381$14676_Y - attribute \src "libresoc.v:201382.17-201382.89" - wire width 5 $not$libresoc.v:201382$14677_Y - attribute \src "libresoc.v:201385.17-201385.91" - wire $not$libresoc.v:201385$14680_Y - attribute \src "libresoc.v:201378.18-201378.106" - wire $reduce_or$libresoc.v:201378$14673_Y - attribute \src "libresoc.v:201380.18-201380.106" - wire $reduce_or$libresoc.v:201380$14675_Y - attribute \src "libresoc.v:201383.18-201383.90" - wire $reduce_or$libresoc.v:201383$14678_Y - attribute \src "libresoc.v:201384.17-201384.103" - wire $reduce_or$libresoc.v:201384$14679_Y - attribute \src "libresoc.v:201386.17-201386.105" - wire $reduce_or$libresoc.v:201386$14681_Y + attribute \src "libresoc.v:202503.17-202503.91" + wire $not$libresoc.v:202503$14194_Y + attribute \src "libresoc.v:202505.18-202505.93" + wire $not$libresoc.v:202505$14196_Y + attribute \src "libresoc.v:202507.18-202507.93" + wire $not$libresoc.v:202507$14198_Y + attribute \src "libresoc.v:202508.17-202508.89" + wire width 5 $not$libresoc.v:202508$14199_Y + attribute \src "libresoc.v:202511.17-202511.91" + wire $not$libresoc.v:202511$14202_Y + attribute \src "libresoc.v:202504.18-202504.106" + wire $reduce_or$libresoc.v:202504$14195_Y + attribute \src "libresoc.v:202506.18-202506.106" + wire $reduce_or$libresoc.v:202506$14197_Y + attribute \src "libresoc.v:202509.18-202509.90" + wire $reduce_or$libresoc.v:202509$14200_Y + attribute \src "libresoc.v:202510.17-202510.103" + wire $reduce_or$libresoc.v:202510$14201_Y + attribute \src "libresoc.v:202512.17-202512.105" + wire $reduce_or$libresoc.v:202512$14203_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -420968,95 +385874,95 @@ module \wrpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201377$14672 + cell $not $not$libresoc.v:202503$14194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:201377$14672_Y + connect \Y $not$libresoc.v:202503$14194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201379$14674 + cell $not $not$libresoc.v:202505$14196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:201379$14674_Y + connect \Y $not$libresoc.v:202505$14196_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201381$14676 + cell $not $not$libresoc.v:202507$14198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:201381$14676_Y + connect \Y $not$libresoc.v:202507$14198_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201382$14677 + cell $not $not$libresoc.v:202508$14199 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \i - connect \Y $not$libresoc.v:201382$14677_Y + connect \Y $not$libresoc.v:202508$14199_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201385$14680 + cell $not $not$libresoc.v:202511$14202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:201385$14680_Y + connect \Y $not$libresoc.v:202511$14202_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201378$14673 + cell $reduce_or $reduce_or$libresoc.v:202504$14195 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:201378$14673_Y + connect \Y $reduce_or$libresoc.v:202504$14195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201380$14675 + cell $reduce_or $reduce_or$libresoc.v:202506$14197 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:201380$14675_Y + connect \Y $reduce_or$libresoc.v:202506$14197_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201383$14678 + cell $reduce_or $reduce_or$libresoc.v:202509$14200 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201383$14678_Y + connect \Y $reduce_or$libresoc.v:202509$14200_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201384$14679 + cell $reduce_or $reduce_or$libresoc.v:202510$14201 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:201384$14679_Y + connect \Y $reduce_or$libresoc.v:202510$14201_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201386$14681 + cell $reduce_or $reduce_or$libresoc.v:202512$14203 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:201386$14681_Y - end - connect \$7 $not$libresoc.v:201377$14672_Y - connect \$12 $reduce_or$libresoc.v:201378$14673_Y - connect \$11 $not$libresoc.v:201379$14674_Y - connect \$16 $reduce_or$libresoc.v:201380$14675_Y - connect \$15 $not$libresoc.v:201381$14676_Y - connect \$1 $not$libresoc.v:201382$14677_Y - connect \$19 $reduce_or$libresoc.v:201383$14678_Y - connect \$4 $reduce_or$libresoc.v:201384$14679_Y - connect \$3 $not$libresoc.v:201385$14680_Y - connect \$8 $reduce_or$libresoc.v:201386$14681_Y + connect \Y $reduce_or$libresoc.v:202512$14203_Y + end + connect \$7 $not$libresoc.v:202503$14194_Y + connect \$12 $reduce_or$libresoc.v:202504$14195_Y + connect \$11 $not$libresoc.v:202505$14196_Y + connect \$16 $reduce_or$libresoc.v:202506$14197_Y + connect \$15 $not$libresoc.v:202507$14198_Y + connect \$1 $not$libresoc.v:202508$14199_Y + connect \$19 $reduce_or$libresoc.v:202509$14200_Y + connect \$4 $reduce_or$libresoc.v:202510$14201_Y + connect \$3 $not$libresoc.v:202511$14202_Y + connect \$8 $reduce_or$libresoc.v:202512$14203_Y connect \en_o \$19 connect \o { \t4 \t3 \t2 \t1 \t0 } connect \t4 \$15 @@ -421066,51 +385972,51 @@ module \wrpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:201399.1-201501.10" +attribute \src "libresoc.v:202525.1-202627.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o" attribute \generator "nMigen" module \wrpick_INT_o - attribute \src "libresoc.v:201468.17-201468.91" - wire $not$libresoc.v:201468$14682_Y - attribute \src "libresoc.v:201470.18-201470.93" - wire $not$libresoc.v:201470$14684_Y - attribute \src "libresoc.v:201472.18-201472.93" - wire $not$libresoc.v:201472$14686_Y - attribute \src "libresoc.v:201473.17-201473.89" - wire width 10 $not$libresoc.v:201473$14687_Y - attribute \src "libresoc.v:201475.18-201475.93" - wire $not$libresoc.v:201475$14689_Y - attribute \src "libresoc.v:201477.18-201477.93" - wire $not$libresoc.v:201477$14691_Y - attribute \src "libresoc.v:201479.18-201479.93" - wire $not$libresoc.v:201479$14693_Y - attribute \src "libresoc.v:201481.18-201481.93" - wire $not$libresoc.v:201481$14695_Y - attribute \src "libresoc.v:201483.18-201483.93" - wire $not$libresoc.v:201483$14697_Y - attribute \src "libresoc.v:201486.17-201486.91" - wire $not$libresoc.v:201486$14700_Y - attribute \src "libresoc.v:201469.18-201469.106" - wire $reduce_or$libresoc.v:201469$14683_Y - attribute \src "libresoc.v:201471.18-201471.106" - wire $reduce_or$libresoc.v:201471$14685_Y - attribute \src "libresoc.v:201474.18-201474.106" - wire $reduce_or$libresoc.v:201474$14688_Y - attribute \src "libresoc.v:201476.18-201476.106" - wire $reduce_or$libresoc.v:201476$14690_Y - attribute \src "libresoc.v:201478.18-201478.106" - wire $reduce_or$libresoc.v:201478$14692_Y - attribute \src "libresoc.v:201480.18-201480.106" - wire $reduce_or$libresoc.v:201480$14694_Y - attribute \src "libresoc.v:201482.18-201482.106" - wire $reduce_or$libresoc.v:201482$14696_Y - attribute \src "libresoc.v:201484.18-201484.90" - wire $reduce_or$libresoc.v:201484$14698_Y - attribute \src "libresoc.v:201485.17-201485.103" - wire $reduce_or$libresoc.v:201485$14699_Y - attribute \src "libresoc.v:201487.17-201487.105" - wire $reduce_or$libresoc.v:201487$14701_Y + attribute \src "libresoc.v:202594.17-202594.91" + wire $not$libresoc.v:202594$14204_Y + attribute \src "libresoc.v:202596.18-202596.93" + wire $not$libresoc.v:202596$14206_Y + attribute \src "libresoc.v:202598.18-202598.93" + wire $not$libresoc.v:202598$14208_Y + attribute \src "libresoc.v:202599.17-202599.89" + wire width 10 $not$libresoc.v:202599$14209_Y + attribute \src "libresoc.v:202601.18-202601.93" + wire $not$libresoc.v:202601$14211_Y + attribute \src "libresoc.v:202603.18-202603.93" + wire $not$libresoc.v:202603$14213_Y + attribute \src "libresoc.v:202605.18-202605.93" + wire $not$libresoc.v:202605$14215_Y + attribute \src "libresoc.v:202607.18-202607.93" + wire $not$libresoc.v:202607$14217_Y + attribute \src "libresoc.v:202609.18-202609.93" + wire $not$libresoc.v:202609$14219_Y + attribute \src "libresoc.v:202612.17-202612.91" + wire $not$libresoc.v:202612$14222_Y + attribute \src "libresoc.v:202595.18-202595.106" + wire $reduce_or$libresoc.v:202595$14205_Y + attribute \src "libresoc.v:202597.18-202597.106" + wire $reduce_or$libresoc.v:202597$14207_Y + attribute \src "libresoc.v:202600.18-202600.106" + wire $reduce_or$libresoc.v:202600$14210_Y + attribute \src "libresoc.v:202602.18-202602.106" + wire $reduce_or$libresoc.v:202602$14212_Y + attribute \src "libresoc.v:202604.18-202604.106" + wire $reduce_or$libresoc.v:202604$14214_Y + attribute \src "libresoc.v:202606.18-202606.106" + wire $reduce_or$libresoc.v:202606$14216_Y + attribute \src "libresoc.v:202608.18-202608.106" + wire $reduce_or$libresoc.v:202608$14218_Y + attribute \src "libresoc.v:202610.18-202610.90" + wire $reduce_or$libresoc.v:202610$14220_Y + attribute \src "libresoc.v:202611.17-202611.103" + wire $reduce_or$libresoc.v:202611$14221_Y + attribute \src "libresoc.v:202613.17-202613.105" + wire $reduce_or$libresoc.v:202613$14223_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 10 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -421180,185 +386086,185 @@ module \wrpick_INT_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201468$14682 + cell $not $not$libresoc.v:202594$14204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:201468$14682_Y + connect \Y $not$libresoc.v:202594$14204_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201470$14684 + cell $not $not$libresoc.v:202596$14206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:201470$14684_Y + connect \Y $not$libresoc.v:202596$14206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201472$14686 + cell $not $not$libresoc.v:202598$14208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:201472$14686_Y + connect \Y $not$libresoc.v:202598$14208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201473$14687 + cell $not $not$libresoc.v:202599$14209 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 10 connect \A \i - connect \Y $not$libresoc.v:201473$14687_Y + connect \Y $not$libresoc.v:202599$14209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201475$14689 + cell $not $not$libresoc.v:202601$14211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:201475$14689_Y + connect \Y $not$libresoc.v:202601$14211_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201477$14691 + cell $not $not$libresoc.v:202603$14213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:201477$14691_Y + connect \Y $not$libresoc.v:202603$14213_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201479$14693 + cell $not $not$libresoc.v:202605$14215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:201479$14693_Y + connect \Y $not$libresoc.v:202605$14215_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201481$14695 + cell $not $not$libresoc.v:202607$14217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:201481$14695_Y + connect \Y $not$libresoc.v:202607$14217_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201483$14697 + cell $not $not$libresoc.v:202609$14219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 - connect \Y $not$libresoc.v:201483$14697_Y + connect \Y $not$libresoc.v:202609$14219_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201486$14700 + cell $not $not$libresoc.v:202612$14222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:201486$14700_Y + connect \Y $not$libresoc.v:202612$14222_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201469$14683 + cell $reduce_or $reduce_or$libresoc.v:202595$14205 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:201469$14683_Y + connect \Y $reduce_or$libresoc.v:202595$14205_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201471$14685 + cell $reduce_or $reduce_or$libresoc.v:202597$14207 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:201471$14685_Y + connect \Y $reduce_or$libresoc.v:202597$14207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201474$14688 + cell $reduce_or $reduce_or$libresoc.v:202600$14210 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:201474$14688_Y + connect \Y $reduce_or$libresoc.v:202600$14210_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201476$14690 + cell $reduce_or $reduce_or$libresoc.v:202602$14212 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:201476$14690_Y + connect \Y $reduce_or$libresoc.v:202602$14212_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201478$14692 + cell $reduce_or $reduce_or$libresoc.v:202604$14214 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:201478$14692_Y + connect \Y $reduce_or$libresoc.v:202604$14214_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201480$14694 + cell $reduce_or $reduce_or$libresoc.v:202606$14216 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:201480$14694_Y + connect \Y $reduce_or$libresoc.v:202606$14216_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201482$14696 + cell $reduce_or $reduce_or$libresoc.v:202608$14218 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A { \i [8:0] \ni [9] } - connect \Y $reduce_or$libresoc.v:201482$14696_Y + connect \Y $reduce_or$libresoc.v:202608$14218_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201484$14698 + cell $reduce_or $reduce_or$libresoc.v:202610$14220 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201484$14698_Y + connect \Y $reduce_or$libresoc.v:202610$14220_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201485$14699 + cell $reduce_or $reduce_or$libresoc.v:202611$14221 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:201485$14699_Y + connect \Y $reduce_or$libresoc.v:202611$14221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201487$14701 + cell $reduce_or $reduce_or$libresoc.v:202613$14223 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:201487$14701_Y - end - connect \$7 $not$libresoc.v:201468$14682_Y - connect \$12 $reduce_or$libresoc.v:201469$14683_Y - connect \$11 $not$libresoc.v:201470$14684_Y - connect \$16 $reduce_or$libresoc.v:201471$14685_Y - connect \$15 $not$libresoc.v:201472$14686_Y - connect \$1 $not$libresoc.v:201473$14687_Y - connect \$20 $reduce_or$libresoc.v:201474$14688_Y - connect \$19 $not$libresoc.v:201475$14689_Y - connect \$24 $reduce_or$libresoc.v:201476$14690_Y - connect \$23 $not$libresoc.v:201477$14691_Y - connect \$28 $reduce_or$libresoc.v:201478$14692_Y - connect \$27 $not$libresoc.v:201479$14693_Y - connect \$32 $reduce_or$libresoc.v:201480$14694_Y - connect \$31 $not$libresoc.v:201481$14695_Y - connect \$36 $reduce_or$libresoc.v:201482$14696_Y - connect \$35 $not$libresoc.v:201483$14697_Y - connect \$39 $reduce_or$libresoc.v:201484$14698_Y - connect \$4 $reduce_or$libresoc.v:201485$14699_Y - connect \$3 $not$libresoc.v:201486$14700_Y - connect \$8 $reduce_or$libresoc.v:201487$14701_Y + connect \Y $reduce_or$libresoc.v:202613$14223_Y + end + connect \$7 $not$libresoc.v:202594$14204_Y + connect \$12 $reduce_or$libresoc.v:202595$14205_Y + connect \$11 $not$libresoc.v:202596$14206_Y + connect \$16 $reduce_or$libresoc.v:202597$14207_Y + connect \$15 $not$libresoc.v:202598$14208_Y + connect \$1 $not$libresoc.v:202599$14209_Y + connect \$20 $reduce_or$libresoc.v:202600$14210_Y + connect \$19 $not$libresoc.v:202601$14211_Y + connect \$24 $reduce_or$libresoc.v:202602$14212_Y + connect \$23 $not$libresoc.v:202603$14213_Y + connect \$28 $reduce_or$libresoc.v:202604$14214_Y + connect \$27 $not$libresoc.v:202605$14215_Y + connect \$32 $reduce_or$libresoc.v:202606$14216_Y + connect \$31 $not$libresoc.v:202607$14217_Y + connect \$36 $reduce_or$libresoc.v:202608$14218_Y + connect \$35 $not$libresoc.v:202609$14219_Y + connect \$39 $reduce_or$libresoc.v:202610$14220_Y + connect \$4 $reduce_or$libresoc.v:202611$14221_Y + connect \$3 $not$libresoc.v:202612$14222_Y + connect \$8 $reduce_or$libresoc.v:202613$14223_Y connect \en_o \$39 connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t9 \$35 @@ -421373,15 +386279,15 @@ module \wrpick_INT_o connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:201505.1-201526.10" +attribute \src "libresoc.v:202631.1-202652.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1" attribute \generator "nMigen" module \wrpick_SPR_spr1 - attribute \src "libresoc.v:201520.17-201520.89" - wire $not$libresoc.v:201520$14702_Y - attribute \src "libresoc.v:201521.17-201521.89" - wire $reduce_or$libresoc.v:201521$14703_Y + attribute \src "libresoc.v:202646.17-202646.89" + wire $not$libresoc.v:202646$14224_Y + attribute \src "libresoc.v:202647.17-202647.89" + wire $reduce_or$libresoc.v:202647$14225_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -421397,37 +386303,37 @@ module \wrpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201520$14702 + cell $not $not$libresoc.v:202646$14224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:201520$14702_Y + connect \Y $not$libresoc.v:202646$14224_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201521$14703 + cell $reduce_or $reduce_or$libresoc.v:202647$14225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201521$14703_Y + connect \Y $reduce_or$libresoc.v:202647$14225_Y end - connect \$1 $not$libresoc.v:201520$14702_Y - connect \$3 $reduce_or$libresoc.v:201521$14703_Y + connect \$1 $not$libresoc.v:202646$14224_Y + connect \$3 $reduce_or$libresoc.v:202647$14225_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:201530.1-201551.10" +attribute \src "libresoc.v:202656.1-202677.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" attribute \generator "nMigen" module \wrpick_STATE_msr - attribute \src "libresoc.v:201545.17-201545.89" - wire $not$libresoc.v:201545$14704_Y - attribute \src "libresoc.v:201546.17-201546.89" - wire $reduce_or$libresoc.v:201546$14705_Y + attribute \src "libresoc.v:202671.17-202671.89" + wire $not$libresoc.v:202671$14226_Y + attribute \src "libresoc.v:202672.17-202672.89" + wire $reduce_or$libresoc.v:202672$14227_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -421443,41 +386349,41 @@ module \wrpick_STATE_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201545$14704 + cell $not $not$libresoc.v:202671$14226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:201545$14704_Y + connect \Y $not$libresoc.v:202671$14226_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201546$14705 + cell $reduce_or $reduce_or$libresoc.v:202672$14227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201546$14705_Y + connect \Y $reduce_or$libresoc.v:202672$14227_Y end - connect \$1 $not$libresoc.v:201545$14704_Y - connect \$3 $reduce_or$libresoc.v:201546$14705_Y + connect \$1 $not$libresoc.v:202671$14226_Y + connect \$3 $reduce_or$libresoc.v:202672$14227_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:201555.1-201585.10" +attribute \src "libresoc.v:202681.1-202711.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia" attribute \generator "nMigen" module \wrpick_STATE_nia - attribute \src "libresoc.v:201576.17-201576.89" - wire width 2 $not$libresoc.v:201576$14706_Y - attribute \src "libresoc.v:201578.17-201578.91" - wire $not$libresoc.v:201578$14708_Y - attribute \src "libresoc.v:201577.17-201577.103" - wire $reduce_or$libresoc.v:201577$14707_Y - attribute \src "libresoc.v:201579.17-201579.89" - wire $reduce_or$libresoc.v:201579$14709_Y + attribute \src "libresoc.v:202702.17-202702.89" + wire width 2 $not$libresoc.v:202702$14228_Y + attribute \src "libresoc.v:202704.17-202704.91" + wire $not$libresoc.v:202704$14230_Y + attribute \src "libresoc.v:202703.17-202703.103" + wire $reduce_or$libresoc.v:202703$14229_Y + attribute \src "libresoc.v:202705.17-202705.89" + wire $reduce_or$libresoc.v:202705$14231_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -421499,64 +386405,64 @@ module \wrpick_STATE_nia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201576$14706 + cell $not $not$libresoc.v:202702$14228 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:201576$14706_Y + connect \Y $not$libresoc.v:202702$14228_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201578$14708 + cell $not $not$libresoc.v:202704$14230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:201578$14708_Y + connect \Y $not$libresoc.v:202704$14230_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201577$14707 + cell $reduce_or $reduce_or$libresoc.v:202703$14229 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:201577$14707_Y + connect \Y $reduce_or$libresoc.v:202703$14229_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201579$14709 + cell $reduce_or $reduce_or$libresoc.v:202705$14231 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201579$14709_Y + connect \Y $reduce_or$libresoc.v:202705$14231_Y end - connect \$1 $not$libresoc.v:201576$14706_Y - connect \$4 $reduce_or$libresoc.v:201577$14707_Y - connect \$3 $not$libresoc.v:201578$14708_Y - connect \$7 $reduce_or$libresoc.v:201579$14709_Y + connect \$1 $not$libresoc.v:202702$14228_Y + connect \$4 $reduce_or$libresoc.v:202703$14229_Y + connect \$3 $not$libresoc.v:202704$14230_Y + connect \$7 $reduce_or$libresoc.v:202705$14231_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:201589.1-201628.10" +attribute \src "libresoc.v:202715.1-202754.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" attribute \generator "nMigen" module \wrpick_XER_xer_ca - attribute \src "libresoc.v:201616.17-201616.91" - wire $not$libresoc.v:201616$14710_Y - attribute \src "libresoc.v:201618.17-201618.89" - wire width 3 $not$libresoc.v:201618$14712_Y - attribute \src "libresoc.v:201620.17-201620.91" - wire $not$libresoc.v:201620$14714_Y - attribute \src "libresoc.v:201617.18-201617.90" - wire $reduce_or$libresoc.v:201617$14711_Y - attribute \src "libresoc.v:201619.17-201619.103" - wire $reduce_or$libresoc.v:201619$14713_Y - attribute \src "libresoc.v:201621.17-201621.105" - wire $reduce_or$libresoc.v:201621$14715_Y + attribute \src "libresoc.v:202742.17-202742.91" + wire $not$libresoc.v:202742$14232_Y + attribute \src "libresoc.v:202744.17-202744.89" + wire width 3 $not$libresoc.v:202744$14234_Y + attribute \src "libresoc.v:202746.17-202746.91" + wire $not$libresoc.v:202746$14236_Y + attribute \src "libresoc.v:202743.18-202743.90" + wire $reduce_or$libresoc.v:202743$14233_Y + attribute \src "libresoc.v:202745.17-202745.103" + wire $reduce_or$libresoc.v:202745$14235_Y + attribute \src "libresoc.v:202747.17-202747.105" + wire $reduce_or$libresoc.v:202747$14237_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -421584,59 +386490,59 @@ module \wrpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201616$14710 + cell $not $not$libresoc.v:202742$14232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:201616$14710_Y + connect \Y $not$libresoc.v:202742$14232_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201618$14712 + cell $not $not$libresoc.v:202744$14234 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:201618$14712_Y + connect \Y $not$libresoc.v:202744$14234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201620$14714 + cell $not $not$libresoc.v:202746$14236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:201620$14714_Y + connect \Y $not$libresoc.v:202746$14236_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201617$14711 + cell $reduce_or $reduce_or$libresoc.v:202743$14233 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201617$14711_Y + connect \Y $reduce_or$libresoc.v:202743$14233_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201619$14713 + cell $reduce_or $reduce_or$libresoc.v:202745$14235 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:201619$14713_Y + connect \Y $reduce_or$libresoc.v:202745$14235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201621$14715 + cell $reduce_or $reduce_or$libresoc.v:202747$14237 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:201621$14715_Y - end - connect \$7 $not$libresoc.v:201616$14710_Y - connect \$11 $reduce_or$libresoc.v:201617$14711_Y - connect \$1 $not$libresoc.v:201618$14712_Y - connect \$4 $reduce_or$libresoc.v:201619$14713_Y - connect \$3 $not$libresoc.v:201620$14714_Y - connect \$8 $reduce_or$libresoc.v:201621$14715_Y + connect \Y $reduce_or$libresoc.v:202747$14237_Y + end + connect \$7 $not$libresoc.v:202742$14232_Y + connect \$11 $reduce_or$libresoc.v:202743$14233_Y + connect \$1 $not$libresoc.v:202744$14234_Y + connect \$4 $reduce_or$libresoc.v:202745$14235_Y + connect \$3 $not$libresoc.v:202746$14236_Y + connect \$8 $reduce_or$libresoc.v:202747$14237_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -421644,27 +386550,27 @@ module \wrpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:201632.1-201680.10" +attribute \src "libresoc.v:202758.1-202806.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov" attribute \generator "nMigen" module \wrpick_XER_xer_ov - attribute \src "libresoc.v:201665.17-201665.91" - wire $not$libresoc.v:201665$14716_Y - attribute \src "libresoc.v:201667.18-201667.93" - wire $not$libresoc.v:201667$14718_Y - attribute \src "libresoc.v:201669.17-201669.89" - wire width 4 $not$libresoc.v:201669$14720_Y - attribute \src "libresoc.v:201671.17-201671.91" - wire $not$libresoc.v:201671$14722_Y - attribute \src "libresoc.v:201666.18-201666.106" - wire $reduce_or$libresoc.v:201666$14717_Y - attribute \src "libresoc.v:201668.18-201668.90" - wire $reduce_or$libresoc.v:201668$14719_Y - attribute \src "libresoc.v:201670.17-201670.103" - wire $reduce_or$libresoc.v:201670$14721_Y - attribute \src "libresoc.v:201672.17-201672.105" - wire $reduce_or$libresoc.v:201672$14723_Y + attribute \src "libresoc.v:202791.17-202791.91" + wire $not$libresoc.v:202791$14238_Y + attribute \src "libresoc.v:202793.18-202793.93" + wire $not$libresoc.v:202793$14240_Y + attribute \src "libresoc.v:202795.17-202795.89" + wire width 4 $not$libresoc.v:202795$14242_Y + attribute \src "libresoc.v:202797.17-202797.91" + wire $not$libresoc.v:202797$14244_Y + attribute \src "libresoc.v:202792.18-202792.106" + wire $reduce_or$libresoc.v:202792$14239_Y + attribute \src "libresoc.v:202794.18-202794.90" + wire $reduce_or$libresoc.v:202794$14241_Y + attribute \src "libresoc.v:202796.17-202796.103" + wire $reduce_or$libresoc.v:202796$14243_Y + attribute \src "libresoc.v:202798.17-202798.105" + wire $reduce_or$libresoc.v:202798$14245_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -421698,77 +386604,77 @@ module \wrpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201665$14716 + cell $not $not$libresoc.v:202791$14238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:201665$14716_Y + connect \Y $not$libresoc.v:202791$14238_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201667$14718 + cell $not $not$libresoc.v:202793$14240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:201667$14718_Y + connect \Y $not$libresoc.v:202793$14240_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201669$14720 + cell $not $not$libresoc.v:202795$14242 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:201669$14720_Y + connect \Y $not$libresoc.v:202795$14242_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201671$14722 + cell $not $not$libresoc.v:202797$14244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:201671$14722_Y + connect \Y $not$libresoc.v:202797$14244_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201666$14717 + cell $reduce_or $reduce_or$libresoc.v:202792$14239 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:201666$14717_Y + connect \Y $reduce_or$libresoc.v:202792$14239_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201668$14719 + cell $reduce_or $reduce_or$libresoc.v:202794$14241 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201668$14719_Y + connect \Y $reduce_or$libresoc.v:202794$14241_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201670$14721 + cell $reduce_or $reduce_or$libresoc.v:202796$14243 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:201670$14721_Y + connect \Y $reduce_or$libresoc.v:202796$14243_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201672$14723 + cell $reduce_or $reduce_or$libresoc.v:202798$14245 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:201672$14723_Y - end - connect \$7 $not$libresoc.v:201665$14716_Y - connect \$12 $reduce_or$libresoc.v:201666$14717_Y - connect \$11 $not$libresoc.v:201667$14718_Y - connect \$15 $reduce_or$libresoc.v:201668$14719_Y - connect \$1 $not$libresoc.v:201669$14720_Y - connect \$4 $reduce_or$libresoc.v:201670$14721_Y - connect \$3 $not$libresoc.v:201671$14722_Y - connect \$8 $reduce_or$libresoc.v:201672$14723_Y + connect \Y $reduce_or$libresoc.v:202798$14245_Y + end + connect \$7 $not$libresoc.v:202791$14238_Y + connect \$12 $reduce_or$libresoc.v:202792$14239_Y + connect \$11 $not$libresoc.v:202793$14240_Y + connect \$15 $reduce_or$libresoc.v:202794$14241_Y + connect \$1 $not$libresoc.v:202795$14242_Y + connect \$4 $reduce_or$libresoc.v:202796$14243_Y + connect \$3 $not$libresoc.v:202797$14244_Y + connect \$8 $reduce_or$libresoc.v:202798$14245_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -421777,27 +386683,27 @@ module \wrpick_XER_xer_ov connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:201684.1-201732.10" +attribute \src "libresoc.v:202810.1-202858.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so" attribute \generator "nMigen" module \wrpick_XER_xer_so - attribute \src "libresoc.v:201717.17-201717.91" - wire $not$libresoc.v:201717$14724_Y - attribute \src "libresoc.v:201719.18-201719.93" - wire $not$libresoc.v:201719$14726_Y - attribute \src "libresoc.v:201721.17-201721.89" - wire width 4 $not$libresoc.v:201721$14728_Y - attribute \src "libresoc.v:201723.17-201723.91" - wire $not$libresoc.v:201723$14730_Y - attribute \src "libresoc.v:201718.18-201718.106" - wire $reduce_or$libresoc.v:201718$14725_Y - attribute \src "libresoc.v:201720.18-201720.90" - wire $reduce_or$libresoc.v:201720$14727_Y - attribute \src "libresoc.v:201722.17-201722.103" - wire $reduce_or$libresoc.v:201722$14729_Y - attribute \src "libresoc.v:201724.17-201724.105" - wire $reduce_or$libresoc.v:201724$14731_Y + attribute \src "libresoc.v:202843.17-202843.91" + wire $not$libresoc.v:202843$14246_Y + attribute \src "libresoc.v:202845.18-202845.93" + wire $not$libresoc.v:202845$14248_Y + attribute \src "libresoc.v:202847.17-202847.89" + wire width 4 $not$libresoc.v:202847$14250_Y + attribute \src "libresoc.v:202849.17-202849.91" + wire $not$libresoc.v:202849$14252_Y + attribute \src "libresoc.v:202844.18-202844.106" + wire $reduce_or$libresoc.v:202844$14247_Y + attribute \src "libresoc.v:202846.18-202846.90" + wire $reduce_or$libresoc.v:202846$14249_Y + attribute \src "libresoc.v:202848.17-202848.103" + wire $reduce_or$libresoc.v:202848$14251_Y + attribute \src "libresoc.v:202850.17-202850.105" + wire $reduce_or$libresoc.v:202850$14253_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -421831,77 +386737,77 @@ module \wrpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201717$14724 + cell $not $not$libresoc.v:202843$14246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:201717$14724_Y + connect \Y $not$libresoc.v:202843$14246_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201719$14726 + cell $not $not$libresoc.v:202845$14248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:201719$14726_Y + connect \Y $not$libresoc.v:202845$14248_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201721$14728 + cell $not $not$libresoc.v:202847$14250 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:201721$14728_Y + connect \Y $not$libresoc.v:202847$14250_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201723$14730 + cell $not $not$libresoc.v:202849$14252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:201723$14730_Y + connect \Y $not$libresoc.v:202849$14252_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201718$14725 + cell $reduce_or $reduce_or$libresoc.v:202844$14247 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:201718$14725_Y + connect \Y $reduce_or$libresoc.v:202844$14247_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201720$14727 + cell $reduce_or $reduce_or$libresoc.v:202846$14249 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201720$14727_Y + connect \Y $reduce_or$libresoc.v:202846$14249_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201722$14729 + cell $reduce_or $reduce_or$libresoc.v:202848$14251 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:201722$14729_Y + connect \Y $reduce_or$libresoc.v:202848$14251_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201724$14731 + cell $reduce_or $reduce_or$libresoc.v:202850$14253 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:201724$14731_Y - end - connect \$7 $not$libresoc.v:201717$14724_Y - connect \$12 $reduce_or$libresoc.v:201718$14725_Y - connect \$11 $not$libresoc.v:201719$14726_Y - connect \$15 $reduce_or$libresoc.v:201720$14727_Y - connect \$1 $not$libresoc.v:201721$14728_Y - connect \$4 $reduce_or$libresoc.v:201722$14729_Y - connect \$3 $not$libresoc.v:201723$14730_Y - connect \$8 $reduce_or$libresoc.v:201724$14731_Y + connect \Y $reduce_or$libresoc.v:202850$14253_Y + end + connect \$7 $not$libresoc.v:202843$14246_Y + connect \$12 $reduce_or$libresoc.v:202844$14247_Y + connect \$11 $not$libresoc.v:202845$14248_Y + connect \$15 $reduce_or$libresoc.v:202846$14249_Y + connect \$1 $not$libresoc.v:202847$14250_Y + connect \$4 $reduce_or$libresoc.v:202848$14251_Y + connect \$3 $not$libresoc.v:202849$14252_Y + connect \$8 $reduce_or$libresoc.v:202850$14253_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -421910,67 +386816,67 @@ module \wrpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:201736.1-202056.10" +attribute \src "libresoc.v:202862.1-203182.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer" attribute \generator "nMigen" module \xer - attribute \src "libresoc.v:201737.7-201737.20" + attribute \src "libresoc.v:202863.7-202863.20" wire $0\initial[0:0] - attribute \src "libresoc.v:202016.3-202024.6" - wire width 3 $0\ren_delay$11$next[2:0]$14755 - attribute \src "libresoc.v:201914.3-201915.43" - wire width 3 $0\ren_delay$11[2:0]$14744 - attribute \src "libresoc.v:201873.13-201873.34" - wire width 3 $0\ren_delay$11[2:0]$14761 - attribute \src "libresoc.v:201978.3-201986.6" - wire width 3 $0\ren_delay$18$next[2:0]$14747 - attribute \src "libresoc.v:201912.3-201913.43" - wire width 3 $0\ren_delay$18[2:0]$14742 - attribute \src "libresoc.v:201877.13-201877.34" - wire width 3 $0\ren_delay$18[2:0]$14763 - attribute \src "libresoc.v:201997.3-202005.6" - wire width 3 $0\ren_delay$next[2:0]$14751 - attribute \src "libresoc.v:201916.3-201917.35" + attribute \src "libresoc.v:203142.3-203150.6" + wire width 3 $0\ren_delay$11$next[2:0]$14277 + attribute \src "libresoc.v:203040.3-203041.43" + wire width 3 $0\ren_delay$11[2:0]$14266 + attribute \src "libresoc.v:202999.13-202999.34" + wire width 3 $0\ren_delay$11[2:0]$14283 + attribute \src "libresoc.v:203104.3-203112.6" + wire width 3 $0\ren_delay$18$next[2:0]$14269 + attribute \src "libresoc.v:203038.3-203039.43" + wire width 3 $0\ren_delay$18[2:0]$14264 + attribute \src "libresoc.v:203003.13-203003.34" + wire width 3 $0\ren_delay$18[2:0]$14285 + attribute \src "libresoc.v:203123.3-203131.6" + wire width 3 $0\ren_delay$next[2:0]$14273 + attribute \src "libresoc.v:203042.3-203043.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:202006.3-202015.6" + attribute \src "libresoc.v:203132.3-203141.6" wire width 2 $0\src1__data_o[1:0] - attribute \src "libresoc.v:202025.3-202034.6" + attribute \src "libresoc.v:203151.3-203160.6" wire width 2 $0\src2__data_o[1:0] - attribute \src "libresoc.v:201987.3-201996.6" + attribute \src "libresoc.v:203113.3-203122.6" wire width 2 $0\src3__data_o[1:0] - attribute \src "libresoc.v:202016.3-202024.6" - wire width 3 $1\ren_delay$11$next[2:0]$14756 - attribute \src "libresoc.v:201978.3-201986.6" - wire width 3 $1\ren_delay$18$next[2:0]$14748 - attribute \src "libresoc.v:201997.3-202005.6" - wire width 3 $1\ren_delay$next[2:0]$14752 - attribute \src "libresoc.v:201871.13-201871.29" + attribute \src "libresoc.v:203142.3-203150.6" + wire width 3 $1\ren_delay$11$next[2:0]$14278 + attribute \src "libresoc.v:203104.3-203112.6" + wire width 3 $1\ren_delay$18$next[2:0]$14270 + attribute \src "libresoc.v:203123.3-203131.6" + wire width 3 $1\ren_delay$next[2:0]$14274 + attribute \src "libresoc.v:202997.13-202997.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:202006.3-202015.6" + attribute \src "libresoc.v:203132.3-203141.6" wire width 2 $1\src1__data_o[1:0] - attribute \src "libresoc.v:202025.3-202034.6" + attribute \src "libresoc.v:203151.3-203160.6" wire width 2 $1\src2__data_o[1:0] - attribute \src "libresoc.v:201987.3-201996.6" + attribute \src "libresoc.v:203113.3-203122.6" wire width 2 $1\src3__data_o[1:0] - attribute \src "libresoc.v:201903.17-201903.109" - wire width 2 $or$libresoc.v:201903$14732_Y - attribute \src "libresoc.v:201905.18-201905.126" - wire width 2 $or$libresoc.v:201905$14734_Y - attribute \src "libresoc.v:201906.18-201906.111" - wire width 2 $or$libresoc.v:201906$14735_Y - attribute \src "libresoc.v:201908.18-201908.126" - wire width 2 $or$libresoc.v:201908$14737_Y - attribute \src "libresoc.v:201909.18-201909.111" - wire width 2 $or$libresoc.v:201909$14738_Y - attribute \src "libresoc.v:201911.17-201911.125" - wire width 2 $or$libresoc.v:201911$14740_Y - attribute \src "libresoc.v:201904.18-201904.100" - wire $reduce_or$libresoc.v:201904$14733_Y - attribute \src "libresoc.v:201907.18-201907.100" - wire $reduce_or$libresoc.v:201907$14736_Y - attribute \src "libresoc.v:201910.17-201910.95" - wire $reduce_or$libresoc.v:201910$14739_Y + attribute \src "libresoc.v:203029.17-203029.109" + wire width 2 $or$libresoc.v:203029$14254_Y + attribute \src "libresoc.v:203031.18-203031.126" + wire width 2 $or$libresoc.v:203031$14256_Y + attribute \src "libresoc.v:203032.18-203032.111" + wire width 2 $or$libresoc.v:203032$14257_Y + attribute \src "libresoc.v:203034.18-203034.126" + wire width 2 $or$libresoc.v:203034$14259_Y + attribute \src "libresoc.v:203035.18-203035.111" + wire width 2 $or$libresoc.v:203035$14260_Y + attribute \src "libresoc.v:203037.17-203037.125" + wire width 2 $or$libresoc.v:203037$14262_Y + attribute \src "libresoc.v:203030.18-203030.100" + wire $reduce_or$libresoc.v:203030$14255_Y + attribute \src "libresoc.v:203033.18-203033.100" + wire $reduce_or$libresoc.v:203033$14258_Y + attribute \src "libresoc.v:203036.17-203036.95" + wire $reduce_or$libresoc.v:203036$14261_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -421989,9 +386895,9 @@ module \xer wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 10 \data_i @@ -422007,7 +386913,7 @@ module \xer wire width 6 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \full_wr__wen - attribute \src "libresoc.v:201737.7-201737.15" + attribute \src "libresoc.v:202863.7-202863.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_dest10__data_i @@ -422136,7 +387042,7 @@ module \xer attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:201903$14732 + cell $or $or$libresoc.v:203029$14254 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -422144,10 +387050,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src10__data_o connect \B \$7 - connect \Y $or$libresoc.v:201903$14732_Y + connect \Y $or$libresoc.v:203029$14254_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:201905$14734 + cell $or $or$libresoc.v:203031$14256 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -422155,10 +387061,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src21__data_o connect \B \reg_2_src22__data_o - connect \Y $or$libresoc.v:201905$14734_Y + connect \Y $or$libresoc.v:203031$14256_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:201906$14735 + cell $or $or$libresoc.v:203032$14257 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -422166,10 +387072,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src20__data_o connect \B \$14 - connect \Y $or$libresoc.v:201906$14735_Y + connect \Y $or$libresoc.v:203032$14257_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:201908$14737 + cell $or $or$libresoc.v:203034$14259 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -422177,10 +387083,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src31__data_o connect \B \reg_2_src32__data_o - connect \Y $or$libresoc.v:201908$14737_Y + connect \Y $or$libresoc.v:203034$14259_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:201909$14738 + cell $or $or$libresoc.v:203035$14260 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -422188,10 +387094,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src30__data_o connect \B \$21 - connect \Y $or$libresoc.v:201909$14738_Y + connect \Y $or$libresoc.v:203035$14260_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:201911$14740 + cell $or $or$libresoc.v:203037$14262 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -422199,34 +387105,34 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src11__data_o connect \B \reg_2_src12__data_o - connect \Y $or$libresoc.v:201911$14740_Y + connect \Y $or$libresoc.v:203037$14262_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:201904$14733 + cell $reduce_or $reduce_or$libresoc.v:203030$14255 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$11 - connect \Y $reduce_or$libresoc.v:201904$14733_Y + connect \Y $reduce_or$libresoc.v:203030$14255_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:201907$14736 + cell $reduce_or $reduce_or$libresoc.v:203033$14258 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$18 - connect \Y $reduce_or$libresoc.v:201907$14736_Y + connect \Y $reduce_or$libresoc.v:203033$14258_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:201910$14739 + cell $reduce_or $reduce_or$libresoc.v:203036$14261 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:201910$14739_Y + connect \Y $reduce_or$libresoc.v:203036$14261_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:201918.15-201937.4" + attribute \src "libresoc.v:203044.15-203063.4" cell \reg_0$132 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -422248,7 +387154,7 @@ module \xer connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:201938.15-201957.4" + attribute \src "libresoc.v:203064.15-203083.4" cell \reg_1$133 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -422270,7 +387176,7 @@ module \xer connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:201958.15-201977.4" + attribute \src "libresoc.v:203084.15-203103.4" cell \reg_2$134 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -422291,67 +387197,67 @@ module \xer connect \w2__data_i \reg_2_w2__data_i connect \w2__wen \reg_2_w2__wen end - attribute \src "libresoc.v:201737.7-201737.20" - process $proc$libresoc.v:201737$14758 + attribute \src "libresoc.v:202863.7-202863.20" + process $proc$libresoc.v:202863$14280 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:201871.13-201871.29" - process $proc$libresoc.v:201871$14759 + attribute \src "libresoc.v:202997.13-202997.29" + process $proc$libresoc.v:202997$14281 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:201873.13-201873.34" - process $proc$libresoc.v:201873$14760 + attribute \src "libresoc.v:202999.13-202999.34" + process $proc$libresoc.v:202999$14282 assign { } { } - assign $0\ren_delay$11[2:0]$14761 3'000 + assign $0\ren_delay$11[2:0]$14283 3'000 sync always sync init - update \ren_delay$11 $0\ren_delay$11[2:0]$14761 + update \ren_delay$11 $0\ren_delay$11[2:0]$14283 end - attribute \src "libresoc.v:201877.13-201877.34" - process $proc$libresoc.v:201877$14762 + attribute \src "libresoc.v:203003.13-203003.34" + process $proc$libresoc.v:203003$14284 assign { } { } - assign $0\ren_delay$18[2:0]$14763 3'000 + assign $0\ren_delay$18[2:0]$14285 3'000 sync always sync init - update \ren_delay$18 $0\ren_delay$18[2:0]$14763 + update \ren_delay$18 $0\ren_delay$18[2:0]$14285 end - attribute \src "libresoc.v:201912.3-201913.43" - process $proc$libresoc.v:201912$14741 + attribute \src "libresoc.v:203038.3-203039.43" + process $proc$libresoc.v:203038$14263 assign { } { } - assign $0\ren_delay$18[2:0]$14742 \ren_delay$18$next + assign $0\ren_delay$18[2:0]$14264 \ren_delay$18$next sync posedge \coresync_clk - update \ren_delay$18 $0\ren_delay$18[2:0]$14742 + update \ren_delay$18 $0\ren_delay$18[2:0]$14264 end - attribute \src "libresoc.v:201914.3-201915.43" - process $proc$libresoc.v:201914$14743 + attribute \src "libresoc.v:203040.3-203041.43" + process $proc$libresoc.v:203040$14265 assign { } { } - assign $0\ren_delay$11[2:0]$14744 \ren_delay$11$next + assign $0\ren_delay$11[2:0]$14266 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[2:0]$14744 + update \ren_delay$11 $0\ren_delay$11[2:0]$14266 end - attribute \src "libresoc.v:201916.3-201917.35" - process $proc$libresoc.v:201916$14745 + attribute \src "libresoc.v:203042.3-203043.35" + process $proc$libresoc.v:203042$14267 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:201978.3-201986.6" - process $proc$libresoc.v:201978$14746 + attribute \src "libresoc.v:203104.3-203112.6" + process $proc$libresoc.v:203104$14268 assign { } { } assign { } { } - assign $0\ren_delay$18$next[2:0]$14747 $1\ren_delay$18$next[2:0]$14748 - attribute \src "libresoc.v:201979.5-201979.29" + assign $0\ren_delay$18$next[2:0]$14269 $1\ren_delay$18$next[2:0]$14270 + attribute \src "libresoc.v:203105.5-203105.29" switch \initial - attribute \src "libresoc.v:201979.9-201979.17" + attribute \src "libresoc.v:203105.9-203105.17" case 1'1 case end @@ -422360,21 +387266,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$18$next[2:0]$14748 3'000 + assign $1\ren_delay$18$next[2:0]$14270 3'000 case - assign $1\ren_delay$18$next[2:0]$14748 \src3__ren + assign $1\ren_delay$18$next[2:0]$14270 \src3__ren end sync always - update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14747 + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14269 end - attribute \src "libresoc.v:201987.3-201996.6" - process $proc$libresoc.v:201987$14749 + attribute \src "libresoc.v:203113.3-203122.6" + process $proc$libresoc.v:203113$14271 assign { } { } assign { } { } assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] - attribute \src "libresoc.v:201988.5-201988.29" + attribute \src "libresoc.v:203114.5-203114.29" switch \initial - attribute \src "libresoc.v:201988.9-201988.17" + attribute \src "libresoc.v:203114.9-203114.17" case 1'1 case end @@ -422390,14 +387296,14 @@ module \xer sync always update \src3__data_o $0\src3__data_o[1:0] end - attribute \src "libresoc.v:201997.3-202005.6" - process $proc$libresoc.v:201997$14750 + attribute \src "libresoc.v:203123.3-203131.6" + process $proc$libresoc.v:203123$14272 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$14751 $1\ren_delay$next[2:0]$14752 - attribute \src "libresoc.v:201998.5-201998.29" + assign $0\ren_delay$next[2:0]$14273 $1\ren_delay$next[2:0]$14274 + attribute \src "libresoc.v:203124.5-203124.29" switch \initial - attribute \src "libresoc.v:201998.9-201998.17" + attribute \src "libresoc.v:203124.9-203124.17" case 1'1 case end @@ -422406,21 +387312,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$14752 3'000 + assign $1\ren_delay$next[2:0]$14274 3'000 case - assign $1\ren_delay$next[2:0]$14752 \src1__ren + assign $1\ren_delay$next[2:0]$14274 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$14751 + update \ren_delay$next $0\ren_delay$next[2:0]$14273 end - attribute \src "libresoc.v:202006.3-202015.6" - process $proc$libresoc.v:202006$14753 + attribute \src "libresoc.v:203132.3-203141.6" + process $proc$libresoc.v:203132$14275 assign { } { } assign { } { } assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] - attribute \src "libresoc.v:202007.5-202007.29" + attribute \src "libresoc.v:203133.5-203133.29" switch \initial - attribute \src "libresoc.v:202007.9-202007.17" + attribute \src "libresoc.v:203133.9-203133.17" case 1'1 case end @@ -422436,14 +387342,14 @@ module \xer sync always update \src1__data_o $0\src1__data_o[1:0] end - attribute \src "libresoc.v:202016.3-202024.6" - process $proc$libresoc.v:202016$14754 + attribute \src "libresoc.v:203142.3-203150.6" + process $proc$libresoc.v:203142$14276 assign { } { } assign { } { } - assign $0\ren_delay$11$next[2:0]$14755 $1\ren_delay$11$next[2:0]$14756 - attribute \src "libresoc.v:202017.5-202017.29" + assign $0\ren_delay$11$next[2:0]$14277 $1\ren_delay$11$next[2:0]$14278 + attribute \src "libresoc.v:203143.5-203143.29" switch \initial - attribute \src "libresoc.v:202017.9-202017.17" + attribute \src "libresoc.v:203143.9-203143.17" case 1'1 case end @@ -422452,21 +387358,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[2:0]$14756 3'000 + assign $1\ren_delay$11$next[2:0]$14278 3'000 case - assign $1\ren_delay$11$next[2:0]$14756 \src2__ren + assign $1\ren_delay$11$next[2:0]$14278 \src2__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14755 + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14277 end - attribute \src "libresoc.v:202025.3-202034.6" - process $proc$libresoc.v:202025$14757 + attribute \src "libresoc.v:203151.3-203160.6" + process $proc$libresoc.v:203151$14279 assign { } { } assign { } { } assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] - attribute \src "libresoc.v:202026.5-202026.29" + attribute \src "libresoc.v:203152.5-203152.29" switch \initial - attribute \src "libresoc.v:202026.9-202026.17" + attribute \src "libresoc.v:203152.9-203152.17" case 1'1 case end @@ -422482,15 +387388,15 @@ module \xer sync always update \src2__data_o $0\src2__data_o[1:0] end - connect \$9 $or$libresoc.v:201903$14732_Y - connect \$12 $reduce_or$libresoc.v:201904$14733_Y - connect \$14 $or$libresoc.v:201905$14734_Y - connect \$16 $or$libresoc.v:201906$14735_Y - connect \$19 $reduce_or$libresoc.v:201907$14736_Y - connect \$21 $or$libresoc.v:201908$14737_Y - connect \$23 $or$libresoc.v:201909$14738_Y - connect \$5 $reduce_or$libresoc.v:201910$14739_Y - connect \$7 $or$libresoc.v:201911$14740_Y + connect \$9 $or$libresoc.v:203029$14254_Y + connect \$12 $reduce_or$libresoc.v:203030$14255_Y + connect \$14 $or$libresoc.v:203031$14256_Y + connect \$16 $or$libresoc.v:203032$14257_Y + connect \$19 $reduce_or$libresoc.v:203033$14258_Y + connect \$21 $or$libresoc.v:203034$14259_Y + connect \$23 $or$libresoc.v:203035$14260_Y + connect \$5 $reduce_or$libresoc.v:203036$14261_Y + connect \$7 $or$libresoc.v:203037$14262_Y connect \full_wr__data_i 6'000000 connect \full_wr__wen 3'000 connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 @@ -422513,153 +387419,153 @@ module \xer connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:202060.1-202374.10" +attribute \src "libresoc.v:203186.1-203503.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" attribute \generator "nMigen" module \xics_icp - attribute \src "libresoc.v:202238.3-202266.6" + attribute \src "libresoc.v:203367.3-203395.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:202289.3-202297.6" - wire $0\core_irq_o$next[0:0]$14799 - attribute \src "libresoc.v:202180.3-202181.37" + attribute \src "libresoc.v:203418.3-203426.6" + wire $0\core_irq_o$next[0:0]$14321 + attribute \src "libresoc.v:203306.3-203307.37" wire $0\core_irq_o[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $0\cppr$10[7:0]$14803 - attribute \src "libresoc.v:202194.3-202209.6" - wire width 8 $0\cppr$next[7:0]$14782 - attribute \src "libresoc.v:202184.3-202185.25" + attribute \src "libresoc.v:203437.3-203499.6" + wire width 8 $0\cppr$10[7:0]$14325 + attribute \src "libresoc.v:203320.3-203335.6" + wire width 8 $0\cppr$next[7:0]$14304 + attribute \src "libresoc.v:203310.3-203311.25" wire width 8 $0\cppr[7:0] - attribute \src "libresoc.v:202298.3-202307.6" + attribute \src "libresoc.v:203427.3-203436.6" wire width 32 $0\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:202061.7-202061.20" + attribute \src "libresoc.v:203187.7-203187.20" wire $0\initial[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire $0\irq$12[0:0]$14804 - attribute \src "libresoc.v:202194.3-202209.6" - wire $0\irq$next[0:0]$14783 - attribute \src "libresoc.v:202188.3-202189.23" + attribute \src "libresoc.v:203437.3-203499.6" + wire $0\irq$12[0:0]$14326 + attribute \src "libresoc.v:203320.3-203335.6" + wire $0\irq$next[0:0]$14305 + attribute \src "libresoc.v:203314.3-203315.23" wire $0\irq[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $0\mfrr$11[7:0]$14805 - attribute \src "libresoc.v:202194.3-202209.6" - wire width 8 $0\mfrr$next[7:0]$14784 - attribute \src "libresoc.v:202186.3-202187.25" + attribute \src "libresoc.v:203437.3-203499.6" + wire width 8 $0\mfrr$11[7:0]$14327 + attribute \src "libresoc.v:203320.3-203335.6" + wire width 8 $0\mfrr$next[7:0]$14306 + attribute \src "libresoc.v:203312.3-203313.25" wire width 8 $0\mfrr[7:0] - attribute \src "libresoc.v:202277.3-202288.6" + attribute \src "libresoc.v:203406.3-203417.6" wire width 8 $0\min_pri[7:0] - attribute \src "libresoc.v:202267.3-202276.6" + attribute \src "libresoc.v:203396.3-203405.6" wire width 8 $0\pending_priority[7:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire $0\wb_ack$14[0:0]$14806 - attribute \src "libresoc.v:202194.3-202209.6" - wire $0\wb_ack$next[0:0]$14785 - attribute \src "libresoc.v:202192.3-202193.29" + attribute \src "libresoc.v:203437.3-203499.6" + wire $0\wb_ack$14[0:0]$14328 + attribute \src "libresoc.v:203320.3-203335.6" + wire $0\wb_ack$next[0:0]$14307 + attribute \src "libresoc.v:203318.3-203319.29" wire $0\wb_ack[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 32 $0\wb_rd_data$13[31:0]$14807 - attribute \src "libresoc.v:202194.3-202209.6" - wire width 32 $0\wb_rd_data$next[31:0]$14786 - attribute \src "libresoc.v:202190.3-202191.37" + attribute \src "libresoc.v:203437.3-203499.6" + wire width 32 $0\wb_rd_data$13[31:0]$14329 + attribute \src "libresoc.v:203320.3-203335.6" + wire width 32 $0\wb_rd_data$next[31:0]$14308 + attribute \src "libresoc.v:203316.3-203317.37" wire width 32 $0\wb_rd_data[31:0] - attribute \src "libresoc.v:202210.3-202237.6" + attribute \src "libresoc.v:203336.3-203366.6" wire $0\xirr_accept_rd[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 24 $0\xisr$9[23:0]$14808 - attribute \src "libresoc.v:202194.3-202209.6" - wire width 24 $0\xisr$next[23:0]$14787 - attribute \src "libresoc.v:202182.3-202183.25" + attribute \src "libresoc.v:203437.3-203499.6" + wire width 24 $0\xisr$9[23:0]$14330 + attribute \src "libresoc.v:203320.3-203335.6" + wire width 24 $0\xisr$next[23:0]$14309 + attribute \src "libresoc.v:203308.3-203309.25" wire width 24 $0\xisr[23:0] - attribute \src "libresoc.v:202238.3-202266.6" + attribute \src "libresoc.v:203367.3-203395.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:202289.3-202297.6" - wire $1\core_irq_o$next[0:0]$14800 - attribute \src "libresoc.v:202090.7-202090.24" + attribute \src "libresoc.v:203418.3-203426.6" + wire $1\core_irq_o$next[0:0]$14322 + attribute \src "libresoc.v:203216.7-203216.24" wire $1\core_irq_o[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $1\cppr$10[7:0]$14809 - attribute \src "libresoc.v:202194.3-202209.6" - wire width 8 $1\cppr$next[7:0]$14788 - attribute \src "libresoc.v:202094.13-202094.25" + attribute \src "libresoc.v:203437.3-203499.6" + wire width 8 $1\cppr$10[7:0]$14331 + attribute \src "libresoc.v:203320.3-203335.6" + wire width 8 $1\cppr$next[7:0]$14310 + attribute \src "libresoc.v:203220.13-203220.25" wire width 8 $1\cppr[7:0] - attribute \src "libresoc.v:202298.3-202307.6" + attribute \src "libresoc.v:203427.3-203436.6" wire width 32 $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire $1\irq$12[0:0]$14819 - attribute \src "libresoc.v:202194.3-202209.6" - wire $1\irq$next[0:0]$14789 - attribute \src "libresoc.v:202123.7-202123.17" + attribute \src "libresoc.v:203437.3-203499.6" + wire $1\irq$12[0:0]$14341 + attribute \src "libresoc.v:203320.3-203335.6" + wire $1\irq$next[0:0]$14311 + attribute \src "libresoc.v:203249.7-203249.17" wire $1\irq[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $1\mfrr$11[7:0]$14810 - attribute \src "libresoc.v:202194.3-202209.6" - wire width 8 $1\mfrr$next[7:0]$14790 - attribute \src "libresoc.v:202131.13-202131.25" + attribute \src "libresoc.v:203437.3-203499.6" + wire width 8 $1\mfrr$11[7:0]$14332 + attribute \src "libresoc.v:203320.3-203335.6" + wire width 8 $1\mfrr$next[7:0]$14312 + attribute \src "libresoc.v:203257.13-203257.25" wire width 8 $1\mfrr[7:0] - attribute \src "libresoc.v:202277.3-202288.6" + attribute \src "libresoc.v:203406.3-203417.6" wire width 8 $1\min_pri[7:0] - attribute \src "libresoc.v:202267.3-202276.6" + attribute \src "libresoc.v:203396.3-203405.6" wire width 8 $1\pending_priority[7:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire $1\wb_ack$14[0:0]$14811 - attribute \src "libresoc.v:202194.3-202209.6" - wire $1\wb_ack$next[0:0]$14791 - attribute \src "libresoc.v:202145.7-202145.20" + attribute \src "libresoc.v:203437.3-203499.6" + wire $1\wb_ack$14[0:0]$14333 + attribute \src "libresoc.v:203320.3-203335.6" + wire $1\wb_ack$next[0:0]$14313 + attribute \src "libresoc.v:203271.7-203271.20" wire $1\wb_ack[0:0] - attribute \src "libresoc.v:202194.3-202209.6" - wire width 32 $1\wb_rd_data$next[31:0]$14792 - attribute \src "libresoc.v:202153.14-202153.32" + attribute \src "libresoc.v:203320.3-203335.6" + wire width 32 $1\wb_rd_data$next[31:0]$14314 + attribute \src "libresoc.v:203279.14-203279.32" wire width 32 $1\wb_rd_data[31:0] - attribute \src "libresoc.v:202210.3-202237.6" + attribute \src "libresoc.v:203336.3-203366.6" wire $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 24 $1\xisr$9[23:0]$14816 - attribute \src "libresoc.v:202194.3-202209.6" - wire width 24 $1\xisr$next[23:0]$14793 - attribute \src "libresoc.v:202163.14-202163.31" + attribute \src "libresoc.v:203437.3-203499.6" + wire width 24 $1\xisr$9[23:0]$14338 + attribute \src "libresoc.v:203320.3-203335.6" + wire width 24 $1\xisr$next[23:0]$14315 + attribute \src "libresoc.v:203289.14-203289.31" wire width 24 $1\xisr[23:0] - attribute \src "libresoc.v:202238.3-202266.6" + attribute \src "libresoc.v:203367.3-203395.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $2\cppr$10[7:0]$14812 - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $2\mfrr$11[7:0]$14813 - attribute \src "libresoc.v:202210.3-202237.6" + attribute \src "libresoc.v:203437.3-203499.6" + wire width 8 $2\cppr$10[7:0]$14334 + attribute \src "libresoc.v:203437.3-203499.6" + wire width 8 $2\mfrr$11[7:0]$14335 + attribute \src "libresoc.v:203336.3-203366.6" wire $2\xirr_accept_rd[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 24 $2\xisr$9[23:0]$14817 - attribute \src "libresoc.v:202238.3-202266.6" + attribute \src "libresoc.v:203437.3-203499.6" + wire width 24 $2\xisr$9[23:0]$14339 + attribute \src "libresoc.v:203367.3-203395.6" wire width 32 $3\be_out[31:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $3\cppr$10[7:0]$14814 - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $3\mfrr$11[7:0]$14815 - attribute \src "libresoc.v:202210.3-202237.6" + attribute \src "libresoc.v:203437.3-203499.6" + wire width 8 $3\cppr$10[7:0]$14336 + attribute \src "libresoc.v:203437.3-203499.6" + wire width 8 $3\mfrr$11[7:0]$14337 + attribute \src "libresoc.v:203336.3-203366.6" wire $3\xirr_accept_rd[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $4\cppr$10[7:0]$14818 - attribute \src "libresoc.v:202210.3-202237.6" + attribute \src "libresoc.v:203437.3-203499.6" + wire width 8 $4\cppr$10[7:0]$14340 + attribute \src "libresoc.v:203336.3-203366.6" wire $4\xirr_accept_rd[0:0] - attribute \src "libresoc.v:202170.18-202170.116" - wire $and$libresoc.v:202170$14764_Y - attribute \src "libresoc.v:202174.18-202174.116" - wire $and$libresoc.v:202174$14768_Y - attribute \src "libresoc.v:202176.18-202176.116" - wire $and$libresoc.v:202176$14770_Y - attribute \src "libresoc.v:202179.17-202179.109" - wire $and$libresoc.v:202179$14773_Y - attribute \src "libresoc.v:202175.18-202175.110" - wire $eq$libresoc.v:202175$14769_Y - attribute \src "libresoc.v:202172.18-202172.114" - wire $lt$libresoc.v:202172$14766_Y - attribute \src "libresoc.v:202173.18-202173.109" - wire $lt$libresoc.v:202173$14767_Y - attribute \src "libresoc.v:202178.18-202178.114" - wire $lt$libresoc.v:202178$14772_Y - attribute \src "libresoc.v:202171.18-202171.109" - wire $ne$libresoc.v:202171$14765_Y - attribute \src "libresoc.v:202177.18-202177.109" - wire $ne$libresoc.v:202177$14771_Y + attribute \src "libresoc.v:203296.18-203296.116" + wire $and$libresoc.v:203296$14286_Y + attribute \src "libresoc.v:203300.18-203300.116" + wire $and$libresoc.v:203300$14290_Y + attribute \src "libresoc.v:203302.18-203302.116" + wire $and$libresoc.v:203302$14292_Y + attribute \src "libresoc.v:203305.17-203305.109" + wire $and$libresoc.v:203305$14295_Y + attribute \src "libresoc.v:203301.18-203301.110" + wire $eq$libresoc.v:203301$14291_Y + attribute \src "libresoc.v:203298.18-203298.114" + wire $lt$libresoc.v:203298$14288_Y + attribute \src "libresoc.v:203299.18-203299.109" + wire $lt$libresoc.v:203299$14289_Y + attribute \src "libresoc.v:203304.18-203304.114" + wire $lt$libresoc.v:203304$14294_Y + attribute \src "libresoc.v:203297.18-203297.109" + wire $ne$libresoc.v:203297$14287_Y + attribute \src "libresoc.v:203303.18-203303.109" + wire $ne$libresoc.v:203303$14293_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" @@ -422684,7 +387590,7 @@ module \xics_icp wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 13 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire output 4 \core_irq_o @@ -422718,7 +387624,7 @@ module \xics_icp wire width 8 input 3 \ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 input 2 \ics_i_src - attribute \src "libresoc.v:202061.7-202061.15" + attribute \src "libresoc.v:203187.7-203187.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq @@ -422740,7 +387646,7 @@ module \xics_icp wire width 8 \min_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" wire width 8 \pending_priority - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack @@ -422769,7 +387675,7 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:202170$14764 + cell $and $and$libresoc.v:203296$14286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -422777,10 +387683,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:202170$14764_Y + connect \Y $and$libresoc.v:203296$14286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:202174$14768 + cell $and $and$libresoc.v:203300$14290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -422788,10 +387694,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:202174$14768_Y + connect \Y $and$libresoc.v:203300$14290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:202176$14770 + cell $and $and$libresoc.v:203302$14292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -422799,10 +387705,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:202176$14770_Y + connect \Y $and$libresoc.v:203302$14292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - cell $and $and$libresoc.v:202179$14773 + cell $and $and$libresoc.v:203305$14295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -422810,10 +387716,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \wb_ack connect \B \icp_wb__cyc - connect \Y $and$libresoc.v:202179$14773_Y + connect \Y $and$libresoc.v:203305$14295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - cell $eq $eq$libresoc.v:202175$14769 + cell $eq $eq$libresoc.v:203301$14291 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -422821,10 +387727,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__sel connect \B 4'1111 - connect \Y $eq$libresoc.v:202175$14769_Y + connect \Y $eq$libresoc.v:203301$14291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:202172$14766 + cell $lt $lt$libresoc.v:203298$14288 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -422832,10 +387738,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:202172$14766_Y + connect \Y $lt$libresoc.v:203298$14288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - cell $lt $lt$libresoc.v:202173$14767 + cell $lt $lt$libresoc.v:203299$14289 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -422843,10 +387749,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \min_pri connect \B \cppr$10 - connect \Y $lt$libresoc.v:202173$14767_Y + connect \Y $lt$libresoc.v:203299$14289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:202178$14772 + cell $lt $lt$libresoc.v:203304$14294 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -422854,10 +387760,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:202178$14772_Y + connect \Y $lt$libresoc.v:203304$14294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:202171$14765 + cell $ne $ne$libresoc.v:203297$14287 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -422865,10 +387771,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:202171$14765_Y + connect \Y $ne$libresoc.v:203297$14287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:202177$14771 + cell $ne $ne$libresoc.v:203303$14293 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -422876,123 +387782,123 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:202177$14771_Y + connect \Y $ne$libresoc.v:203303$14293_Y end - attribute \src "libresoc.v:202061.7-202061.20" - process $proc$libresoc.v:202061$14820 + attribute \src "libresoc.v:203187.7-203187.20" + process $proc$libresoc.v:203187$14342 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:202090.7-202090.24" - process $proc$libresoc.v:202090$14821 + attribute \src "libresoc.v:203216.7-203216.24" + process $proc$libresoc.v:203216$14343 assign { } { } assign $1\core_irq_o[0:0] 1'0 sync always sync init update \core_irq_o $1\core_irq_o[0:0] end - attribute \src "libresoc.v:202094.13-202094.25" - process $proc$libresoc.v:202094$14822 + attribute \src "libresoc.v:203220.13-203220.25" + process $proc$libresoc.v:203220$14344 assign { } { } assign $1\cppr[7:0] 8'00000000 sync always sync init update \cppr $1\cppr[7:0] end - attribute \src "libresoc.v:202123.7-202123.17" - process $proc$libresoc.v:202123$14823 + attribute \src "libresoc.v:203249.7-203249.17" + process $proc$libresoc.v:203249$14345 assign { } { } assign $1\irq[0:0] 1'0 sync always sync init update \irq $1\irq[0:0] end - attribute \src "libresoc.v:202131.13-202131.25" - process $proc$libresoc.v:202131$14824 + attribute \src "libresoc.v:203257.13-203257.25" + process $proc$libresoc.v:203257$14346 assign { } { } assign $1\mfrr[7:0] 8'11111111 sync always sync init update \mfrr $1\mfrr[7:0] end - attribute \src "libresoc.v:202145.7-202145.20" - process $proc$libresoc.v:202145$14825 + attribute \src "libresoc.v:203271.7-203271.20" + process $proc$libresoc.v:203271$14347 assign { } { } assign $1\wb_ack[0:0] 1'0 sync always sync init update \wb_ack $1\wb_ack[0:0] end - attribute \src "libresoc.v:202153.14-202153.32" - process $proc$libresoc.v:202153$14826 + attribute \src "libresoc.v:203279.14-203279.32" + process $proc$libresoc.v:203279$14348 assign { } { } assign $1\wb_rd_data[31:0] 0 sync always sync init update \wb_rd_data $1\wb_rd_data[31:0] end - attribute \src "libresoc.v:202163.14-202163.31" - process $proc$libresoc.v:202163$14827 + attribute \src "libresoc.v:203289.14-203289.31" + process $proc$libresoc.v:203289$14349 assign { } { } assign $1\xisr[23:0] 24'000000000000000000000000 sync always sync init update \xisr $1\xisr[23:0] end - attribute \src "libresoc.v:202180.3-202181.37" - process $proc$libresoc.v:202180$14774 + attribute \src "libresoc.v:203306.3-203307.37" + process $proc$libresoc.v:203306$14296 assign { } { } assign $0\core_irq_o[0:0] \core_irq_o$next sync posedge \clk update \core_irq_o $0\core_irq_o[0:0] end - attribute \src "libresoc.v:202182.3-202183.25" - process $proc$libresoc.v:202182$14775 + attribute \src "libresoc.v:203308.3-203309.25" + process $proc$libresoc.v:203308$14297 assign { } { } assign $0\xisr[23:0] \xisr$next sync posedge \clk update \xisr $0\xisr[23:0] end - attribute \src "libresoc.v:202184.3-202185.25" - process $proc$libresoc.v:202184$14776 + attribute \src "libresoc.v:203310.3-203311.25" + process $proc$libresoc.v:203310$14298 assign { } { } assign $0\cppr[7:0] \cppr$next sync posedge \clk update \cppr $0\cppr[7:0] end - attribute \src "libresoc.v:202186.3-202187.25" - process $proc$libresoc.v:202186$14777 + attribute \src "libresoc.v:203312.3-203313.25" + process $proc$libresoc.v:203312$14299 assign { } { } assign $0\mfrr[7:0] \mfrr$next sync posedge \clk update \mfrr $0\mfrr[7:0] end - attribute \src "libresoc.v:202188.3-202189.23" - process $proc$libresoc.v:202188$14778 + attribute \src "libresoc.v:203314.3-203315.23" + process $proc$libresoc.v:203314$14300 assign { } { } assign $0\irq[0:0] \irq$next sync posedge \clk update \irq $0\irq[0:0] end - attribute \src "libresoc.v:202190.3-202191.37" - process $proc$libresoc.v:202190$14779 + attribute \src "libresoc.v:203316.3-203317.37" + process $proc$libresoc.v:203316$14301 assign { } { } assign $0\wb_rd_data[31:0] \wb_rd_data$next sync posedge \clk update \wb_rd_data $0\wb_rd_data[31:0] end - attribute \src "libresoc.v:202192.3-202193.29" - process $proc$libresoc.v:202192$14780 + attribute \src "libresoc.v:203318.3-203319.29" + process $proc$libresoc.v:203318$14302 assign { } { } assign $0\wb_ack[0:0] \wb_ack$next sync posedge \clk update \wb_ack $0\wb_ack[0:0] end - attribute \src "libresoc.v:202194.3-202209.6" - process $proc$libresoc.v:202194$14781 + attribute \src "libresoc.v:203320.3-203335.6" + process $proc$libresoc.v:203320$14303 assign { } { } assign { } { } assign { } { } @@ -423000,15 +387906,15 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\cppr$next[7:0]$14782 $1\cppr$next[7:0]$14788 - assign $0\irq$next[0:0]$14783 $1\irq$next[0:0]$14789 - assign $0\mfrr$next[7:0]$14784 $1\mfrr$next[7:0]$14790 - assign $0\wb_ack$next[0:0]$14785 $1\wb_ack$next[0:0]$14791 - assign $0\wb_rd_data$next[31:0]$14786 $1\wb_rd_data$next[31:0]$14792 - assign $0\xisr$next[23:0]$14787 $1\xisr$next[23:0]$14793 - attribute \src "libresoc.v:202195.5-202195.29" + assign $0\cppr$next[7:0]$14304 $1\cppr$next[7:0]$14310 + assign $0\irq$next[0:0]$14305 $1\irq$next[0:0]$14311 + assign $0\mfrr$next[7:0]$14306 $1\mfrr$next[7:0]$14312 + assign $0\wb_ack$next[0:0]$14307 $1\wb_ack$next[0:0]$14313 + assign $0\wb_rd_data$next[31:0]$14308 $1\wb_rd_data$next[31:0]$14314 + assign $0\xisr$next[23:0]$14309 $1\xisr$next[23:0]$14315 + attribute \src "libresoc.v:203321.5-203321.29" switch \initial - attribute \src "libresoc.v:202195.9-202195.17" + attribute \src "libresoc.v:203321.9-203321.17" case 1'1 case end @@ -423022,36 +387928,36 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\xisr$next[23:0]$14793 24'000000000000000000000000 - assign $1\cppr$next[7:0]$14788 8'00000000 - assign $1\mfrr$next[7:0]$14790 8'11111111 - assign $1\irq$next[0:0]$14789 1'0 - assign $1\wb_rd_data$next[31:0]$14792 0 - assign $1\wb_ack$next[0:0]$14791 1'0 + assign $1\xisr$next[23:0]$14315 24'000000000000000000000000 + assign $1\cppr$next[7:0]$14310 8'00000000 + assign $1\mfrr$next[7:0]$14312 8'11111111 + assign $1\irq$next[0:0]$14311 1'0 + assign $1\wb_rd_data$next[31:0]$14314 0 + assign $1\wb_ack$next[0:0]$14313 1'0 case - assign $1\cppr$next[7:0]$14788 \cppr$2 - assign $1\irq$next[0:0]$14789 \irq$4 - assign $1\mfrr$next[7:0]$14790 \mfrr$3 - assign $1\wb_ack$next[0:0]$14791 \wb_ack$6 - assign $1\wb_rd_data$next[31:0]$14792 \wb_rd_data$5 - assign $1\xisr$next[23:0]$14793 \xisr$1 + assign $1\cppr$next[7:0]$14310 \cppr$2 + assign $1\irq$next[0:0]$14311 \irq$4 + assign $1\mfrr$next[7:0]$14312 \mfrr$3 + assign $1\wb_ack$next[0:0]$14313 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$14314 \wb_rd_data$5 + assign $1\xisr$next[23:0]$14315 \xisr$1 end sync always - update \cppr$next $0\cppr$next[7:0]$14782 - update \irq$next $0\irq$next[0:0]$14783 - update \mfrr$next $0\mfrr$next[7:0]$14784 - update \wb_ack$next $0\wb_ack$next[0:0]$14785 - update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14786 - update \xisr$next $0\xisr$next[23:0]$14787 + update \cppr$next $0\cppr$next[7:0]$14304 + update \irq$next $0\irq$next[0:0]$14305 + update \mfrr$next $0\mfrr$next[7:0]$14306 + update \wb_ack$next $0\wb_ack$next[0:0]$14307 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14308 + update \xisr$next $0\xisr$next[23:0]$14309 end - attribute \src "libresoc.v:202210.3-202237.6" - process $proc$libresoc.v:202210$14794 + attribute \src "libresoc.v:203336.3-203366.6" + process $proc$libresoc.v:203336$14316 assign { } { } assign { } { } assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:202211.5-202211.29" + attribute \src "libresoc.v:203337.5-203337.29" switch \initial - attribute \src "libresoc.v:202211.9-202211.17" + attribute \src "libresoc.v:203337.9-203337.17" case 1'1 case end @@ -423073,6 +387979,9 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" + case 6'000000 + assign $3\xirr_accept_rd[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } assign $3\xirr_accept_rd[0:0] $4\xirr_accept_rd[0:0] @@ -423095,14 +388004,14 @@ module \xics_icp sync always update \xirr_accept_rd $0\xirr_accept_rd[0:0] end - attribute \src "libresoc.v:202238.3-202266.6" - process $proc$libresoc.v:202238$14795 + attribute \src "libresoc.v:203367.3-203395.6" + process $proc$libresoc.v:203367$14317 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:202239.5-202239.29" + attribute \src "libresoc.v:203368.5-203368.29" switch \initial - attribute \src "libresoc.v:202239.9-202239.17" + attribute \src "libresoc.v:203368.9-203368.17" case 1'1 case end @@ -423145,14 +388054,14 @@ module \xics_icp sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:202267.3-202276.6" - process $proc$libresoc.v:202267$14796 + attribute \src "libresoc.v:203396.3-203405.6" + process $proc$libresoc.v:203396$14318 assign { } { } assign { } { } assign $0\pending_priority[7:0] $1\pending_priority[7:0] - attribute \src "libresoc.v:202268.5-202268.29" + attribute \src "libresoc.v:203397.5-203397.29" switch \initial - attribute \src "libresoc.v:202268.9-202268.17" + attribute \src "libresoc.v:203397.9-203397.17" case 1'1 case end @@ -423168,13 +388077,13 @@ module \xics_icp sync always update \pending_priority $0\pending_priority[7:0] end - attribute \src "libresoc.v:202277.3-202288.6" - process $proc$libresoc.v:202277$14797 + attribute \src "libresoc.v:203406.3-203417.6" + process $proc$libresoc.v:203406$14319 assign { } { } assign $0\min_pri[7:0] $1\min_pri[7:0] - attribute \src "libresoc.v:202278.5-202278.29" + attribute \src "libresoc.v:203407.5-203407.29" switch \initial - attribute \src "libresoc.v:202278.9-202278.17" + attribute \src "libresoc.v:203407.9-203407.17" case 1'1 case end @@ -423192,14 +388101,14 @@ module \xics_icp sync always update \min_pri $0\min_pri[7:0] end - attribute \src "libresoc.v:202289.3-202297.6" - process $proc$libresoc.v:202289$14798 + attribute \src "libresoc.v:203418.3-203426.6" + process $proc$libresoc.v:203418$14320 assign { } { } assign { } { } - assign $0\core_irq_o$next[0:0]$14799 $1\core_irq_o$next[0:0]$14800 - attribute \src "libresoc.v:202290.5-202290.29" + assign $0\core_irq_o$next[0:0]$14321 $1\core_irq_o$next[0:0]$14322 + attribute \src "libresoc.v:203419.5-203419.29" switch \initial - attribute \src "libresoc.v:202290.9-202290.17" + attribute \src "libresoc.v:203419.9-203419.17" case 1'1 case end @@ -423208,21 +388117,21 @@ module \xics_icp attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_irq_o$next[0:0]$14800 1'0 + assign $1\core_irq_o$next[0:0]$14322 1'0 case - assign $1\core_irq_o$next[0:0]$14800 \irq + assign $1\core_irq_o$next[0:0]$14322 \irq end sync always - update \core_irq_o$next $0\core_irq_o$next[0:0]$14799 + update \core_irq_o$next $0\core_irq_o$next[0:0]$14321 end - attribute \src "libresoc.v:202298.3-202307.6" - process $proc$libresoc.v:202298$14801 + attribute \src "libresoc.v:203427.3-203436.6" + process $proc$libresoc.v:203427$14323 assign { } { } assign { } { } assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:202299.5-202299.29" + attribute \src "libresoc.v:203428.5-203428.29" switch \initial - attribute \src "libresoc.v:202299.9-202299.17" + attribute \src "libresoc.v:203428.9-203428.17" case 1'1 case end @@ -423238,8 +388147,8 @@ module \xics_icp sync always update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] end - attribute \src "libresoc.v:202308.3-202370.6" - process $proc$libresoc.v:202308$14802 + attribute \src "libresoc.v:203437.3-203499.6" + process $proc$libresoc.v:203437$14324 assign { } { } assign { } { } assign { } { } @@ -423249,18 +388158,18 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\mfrr$11[7:0]$14805 $1\mfrr$11[7:0]$14810 - assign $0\wb_ack$14[0:0]$14806 $1\wb_ack$14[0:0]$14811 + assign $0\mfrr$11[7:0]$14327 $1\mfrr$11[7:0]$14332 + assign $0\wb_ack$14[0:0]$14328 $1\wb_ack$14[0:0]$14333 assign { } { } assign { } { } assign { } { } - assign $0\xisr$9[23:0]$14808 $2\xisr$9[23:0]$14817 - assign $0\cppr$10[7:0]$14803 $4\cppr$10[7:0]$14818 - assign $0\wb_rd_data$13[31:0]$14807 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - assign $0\irq$12[0:0]$14804 $1\irq$12[0:0]$14819 - attribute \src "libresoc.v:202309.5-202309.29" + assign $0\xisr$9[23:0]$14330 $2\xisr$9[23:0]$14339 + assign $0\cppr$10[7:0]$14325 $4\cppr$10[7:0]$14340 + assign $0\wb_rd_data$13[31:0]$14329 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$14326 $1\irq$12[0:0]$14341 + attribute \src "libresoc.v:203438.5-203438.29" switch \initial - attribute \src "libresoc.v:202309.9-202309.17" + attribute \src "libresoc.v:203438.9-203438.17" case 1'1 case end @@ -423271,712 +388180,712 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\wb_ack$14[0:0]$14811 1'1 - assign $1\cppr$10[7:0]$14809 $2\cppr$10[7:0]$14812 - assign $1\mfrr$11[7:0]$14810 $2\mfrr$11[7:0]$14813 + assign $1\wb_ack$14[0:0]$14333 1'1 + assign $1\cppr$10[7:0]$14331 $2\cppr$10[7:0]$14334 + assign $1\mfrr$11[7:0]$14332 $2\mfrr$11[7:0]$14335 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $2\cppr$10[7:0]$14812 $3\cppr$10[7:0]$14814 - assign $2\mfrr$11[7:0]$14813 $3\mfrr$11[7:0]$14815 + assign $2\cppr$10[7:0]$14334 $3\cppr$10[7:0]$14336 + assign $2\mfrr$11[7:0]$14335 $3\mfrr$11[7:0]$14337 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } - assign $3\mfrr$11[7:0]$14815 \mfrr - assign $3\cppr$10[7:0]$14814 \be_in [31:24] + assign $3\mfrr$11[7:0]$14337 \mfrr + assign $3\cppr$10[7:0]$14336 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } - assign $3\mfrr$11[7:0]$14815 \mfrr - assign $3\cppr$10[7:0]$14814 \be_in [31:24] + assign $3\mfrr$11[7:0]$14337 \mfrr + assign $3\cppr$10[7:0]$14336 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000011 - assign $3\cppr$10[7:0]$14814 \cppr + assign $3\cppr$10[7:0]$14336 \cppr assign { } { } - assign $3\mfrr$11[7:0]$14815 \be_in [31:24] + assign $3\mfrr$11[7:0]$14337 \be_in [31:24] case - assign $3\cppr$10[7:0]$14814 \cppr - assign $3\mfrr$11[7:0]$14815 \mfrr + assign $3\cppr$10[7:0]$14336 \cppr + assign $3\mfrr$11[7:0]$14337 \mfrr end case - assign $2\cppr$10[7:0]$14812 \cppr - assign $2\mfrr$11[7:0]$14813 \mfrr + assign $2\cppr$10[7:0]$14334 \cppr + assign $2\mfrr$11[7:0]$14335 \mfrr end case - assign $1\cppr$10[7:0]$14809 \cppr - assign $1\mfrr$11[7:0]$14810 \mfrr - assign $1\wb_ack$14[0:0]$14811 1'0 + assign $1\cppr$10[7:0]$14331 \cppr + assign $1\mfrr$11[7:0]$14332 \mfrr + assign $1\wb_ack$14[0:0]$14333 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xisr$9[23:0]$14816 { 20'00000000000000000001 \ics_i_src } + assign $1\xisr$9[23:0]$14338 { 20'00000000000000000001 \ics_i_src } case - assign $1\xisr$9[23:0]$14816 24'000000000000000000000000 + assign $1\xisr$9[23:0]$14338 24'000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xisr$9[23:0]$14817 24'000000000000000000000010 + assign $2\xisr$9[23:0]$14339 24'000000000000000000000010 case - assign $2\xisr$9[23:0]$14817 $1\xisr$9[23:0]$14816 + assign $2\xisr$9[23:0]$14339 $1\xisr$9[23:0]$14338 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" switch \xirr_accept_rd attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cppr$10[7:0]$14818 \min_pri + assign $4\cppr$10[7:0]$14340 \min_pri case - assign $4\cppr$10[7:0]$14818 $1\cppr$10[7:0]$14809 + assign $4\cppr$10[7:0]$14340 $1\cppr$10[7:0]$14331 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" switch { \irq \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\irq$12[0:0]$14819 1'1 + assign $1\irq$12[0:0]$14341 1'1 case - assign $1\irq$12[0:0]$14819 1'0 + assign $1\irq$12[0:0]$14341 1'0 end sync always - update \cppr$10 $0\cppr$10[7:0]$14803 - update \irq$12 $0\irq$12[0:0]$14804 - update \mfrr$11 $0\mfrr$11[7:0]$14805 - update \wb_ack$14 $0\wb_ack$14[0:0]$14806 - update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14807 - update \xisr$9 $0\xisr$9[23:0]$14808 + update \cppr$10 $0\cppr$10[7:0]$14325 + update \irq$12 $0\irq$12[0:0]$14326 + update \mfrr$11 $0\mfrr$11[7:0]$14327 + update \wb_ack$14 $0\wb_ack$14[0:0]$14328 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14329 + update \xisr$9 $0\xisr$9[23:0]$14330 end - connect \$15 $and$libresoc.v:202170$14764_Y - connect \$17 $ne$libresoc.v:202171$14765_Y - connect \$19 $lt$libresoc.v:202172$14766_Y - connect \$21 $lt$libresoc.v:202173$14767_Y - connect \$23 $and$libresoc.v:202174$14768_Y - connect \$25 $eq$libresoc.v:202175$14769_Y - connect \$27 $and$libresoc.v:202176$14770_Y - connect \$29 $ne$libresoc.v:202177$14771_Y - connect \$31 $lt$libresoc.v:202178$14772_Y - connect \$7 $and$libresoc.v:202179$14773_Y + connect \$15 $and$libresoc.v:203296$14286_Y + connect \$17 $ne$libresoc.v:203297$14287_Y + connect \$19 $lt$libresoc.v:203298$14288_Y + connect \$21 $lt$libresoc.v:203299$14289_Y + connect \$23 $and$libresoc.v:203300$14290_Y + connect \$25 $eq$libresoc.v:203301$14291_Y + connect \$27 $and$libresoc.v:203302$14292_Y + connect \$29 $ne$libresoc.v:203303$14293_Y + connect \$31 $lt$libresoc.v:203304$14294_Y + connect \$7 $and$libresoc.v:203305$14295_Y connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } connect \icp_wb__ack \$7 end -attribute \src "libresoc.v:202378.1-203427.10" +attribute \src "libresoc.v:203507.1-204556.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" attribute \generator "nMigen" module \xics_ics - attribute \src "libresoc.v:203308.3-203357.6" + attribute \src "libresoc.v:204437.3-204486.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:203019.3-203028.6" + attribute \src "libresoc.v:204148.3-204157.6" wire width 4 $0\cur_idx0[3:0] - attribute \src "libresoc.v:203228.3-203237.6" + attribute \src "libresoc.v:204357.3-204366.6" wire width 4 $0\cur_idx10[3:0] - attribute \src "libresoc.v:203248.3-203257.6" + attribute \src "libresoc.v:204377.3-204386.6" wire width 4 $0\cur_idx11[3:0] - attribute \src "libresoc.v:203268.3-203277.6" + attribute \src "libresoc.v:204397.3-204406.6" wire width 4 $0\cur_idx12[3:0] - attribute \src "libresoc.v:203288.3-203297.6" + attribute \src "libresoc.v:204417.3-204426.6" wire width 4 $0\cur_idx13[3:0] - attribute \src "libresoc.v:203358.3-203367.6" + attribute \src "libresoc.v:204487.3-204496.6" wire width 4 $0\cur_idx14[3:0] - attribute \src "libresoc.v:203378.3-203387.6" + attribute \src "libresoc.v:204507.3-204516.6" wire width 4 $0\cur_idx15[3:0] - attribute \src "libresoc.v:203039.3-203048.6" + attribute \src "libresoc.v:204168.3-204177.6" wire width 4 $0\cur_idx1[3:0] - attribute \src "libresoc.v:203059.3-203068.6" + attribute \src "libresoc.v:204188.3-204197.6" wire width 4 $0\cur_idx2[3:0] - attribute \src "libresoc.v:203079.3-203088.6" + attribute \src "libresoc.v:204208.3-204217.6" wire width 4 $0\cur_idx3[3:0] - attribute \src "libresoc.v:203108.3-203117.6" + attribute \src "libresoc.v:204237.3-204246.6" wire width 4 $0\cur_idx4[3:0] - attribute \src "libresoc.v:203128.3-203137.6" + attribute \src "libresoc.v:204257.3-204266.6" wire width 4 $0\cur_idx5[3:0] - attribute \src "libresoc.v:203148.3-203157.6" + attribute \src "libresoc.v:204277.3-204286.6" wire width 4 $0\cur_idx6[3:0] - attribute \src "libresoc.v:203168.3-203177.6" + attribute \src "libresoc.v:204297.3-204306.6" wire width 4 $0\cur_idx7[3:0] - attribute \src "libresoc.v:203188.3-203197.6" + attribute \src "libresoc.v:204317.3-204326.6" wire width 4 $0\cur_idx8[3:0] - attribute \src "libresoc.v:203208.3-203217.6" + attribute \src "libresoc.v:204337.3-204346.6" wire width 4 $0\cur_idx9[3:0] - attribute \src "libresoc.v:203009.3-203018.6" + attribute \src "libresoc.v:204138.3-204147.6" wire width 8 $0\cur_pri0[7:0] - attribute \src "libresoc.v:203218.3-203227.6" + attribute \src "libresoc.v:204347.3-204356.6" wire width 8 $0\cur_pri10[7:0] - attribute \src "libresoc.v:203238.3-203247.6" + attribute \src "libresoc.v:204367.3-204376.6" wire width 8 $0\cur_pri11[7:0] - attribute \src "libresoc.v:203258.3-203267.6" + attribute \src "libresoc.v:204387.3-204396.6" wire width 8 $0\cur_pri12[7:0] - attribute \src "libresoc.v:203278.3-203287.6" + attribute \src "libresoc.v:204407.3-204416.6" wire width 8 $0\cur_pri13[7:0] - attribute \src "libresoc.v:203298.3-203307.6" + attribute \src "libresoc.v:204427.3-204436.6" wire width 8 $0\cur_pri14[7:0] - attribute \src "libresoc.v:203368.3-203377.6" + attribute \src "libresoc.v:204497.3-204506.6" wire width 8 $0\cur_pri15[7:0] - attribute \src "libresoc.v:203029.3-203038.6" + attribute \src "libresoc.v:204158.3-204167.6" wire width 8 $0\cur_pri1[7:0] - attribute \src "libresoc.v:203049.3-203058.6" + attribute \src "libresoc.v:204178.3-204187.6" wire width 8 $0\cur_pri2[7:0] - attribute \src "libresoc.v:203069.3-203078.6" + attribute \src "libresoc.v:204198.3-204207.6" wire width 8 $0\cur_pri3[7:0] - attribute \src "libresoc.v:203089.3-203098.6" + attribute \src "libresoc.v:204218.3-204227.6" wire width 8 $0\cur_pri4[7:0] - attribute \src "libresoc.v:203118.3-203127.6" + attribute \src "libresoc.v:204247.3-204256.6" wire width 8 $0\cur_pri5[7:0] - attribute \src "libresoc.v:203138.3-203147.6" + attribute \src "libresoc.v:204267.3-204276.6" wire width 8 $0\cur_pri6[7:0] - attribute \src "libresoc.v:203158.3-203167.6" + attribute \src "libresoc.v:204287.3-204296.6" wire width 8 $0\cur_pri7[7:0] - attribute \src "libresoc.v:203178.3-203187.6" + attribute \src "libresoc.v:204307.3-204316.6" wire width 8 $0\cur_pri8[7:0] - attribute \src "libresoc.v:203198.3-203207.6" + attribute \src "libresoc.v:204327.3-204336.6" wire width 8 $0\cur_pri9[7:0] - attribute \src "libresoc.v:203388.3-203397.6" + attribute \src "libresoc.v:204517.3-204526.6" wire $0\ibit[0:0] - attribute \src "libresoc.v:202883.3-202884.25" + attribute \src "libresoc.v:204012.3-204013.25" wire width 8 $0\icp_o_pri[7:0] - attribute \src "libresoc.v:202881.3-202882.28" + attribute \src "libresoc.v:204010.3-204011.28" wire width 4 $0\icp_o_src[3:0] - attribute \src "libresoc.v:203407.3-203415.6" - wire $0\ics_wb__ack$next[0:0]$15074 - attribute \src "libresoc.v:202917.3-202918.39" + attribute \src "libresoc.v:204536.3-204544.6" + wire $0\ics_wb__ack$next[0:0]$14596 + attribute \src "libresoc.v:204046.3-204047.39" wire $0\ics_wb__ack[0:0] - attribute \src "libresoc.v:203398.3-203406.6" - wire width 32 $0\ics_wb__dat_r$next[31:0]$15071 - attribute \src "libresoc.v:202919.3-202920.43" + attribute \src "libresoc.v:204527.3-204535.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$14593 + attribute \src "libresoc.v:204048.3-204049.43" wire width 32 $0\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:202379.7-202379.20" + attribute \src "libresoc.v:203508.7-203508.20" wire $0\initial[0:0] - attribute \src "libresoc.v:203099.3-203107.6" - wire width 16 $0\int_level_l$next[15:0]$15043 - attribute \src "libresoc.v:202921.3-202922.39" + attribute \src "libresoc.v:204228.3-204236.6" + wire width 16 $0\int_level_l$next[15:0]$14565 + attribute \src "libresoc.v:204050.3-204051.39" wire width 16 $0\int_level_l[15:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive0_pri$next[7:0]$14953 - attribute \src "libresoc.v:202885.3-202886.35" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive0_pri$next[7:0]$14475 + attribute \src "libresoc.v:204014.3-204015.35" wire width 8 $0\xive0_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive10_pri$next[7:0]$14954 - attribute \src "libresoc.v:202905.3-202906.37" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive10_pri$next[7:0]$14476 + attribute \src "libresoc.v:204034.3-204035.37" wire width 8 $0\xive10_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive11_pri$next[7:0]$14955 - attribute \src "libresoc.v:202907.3-202908.37" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive11_pri$next[7:0]$14477 + attribute \src "libresoc.v:204036.3-204037.37" wire width 8 $0\xive11_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive12_pri$next[7:0]$14956 - attribute \src "libresoc.v:202909.3-202910.37" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive12_pri$next[7:0]$14478 + attribute \src "libresoc.v:204038.3-204039.37" wire width 8 $0\xive12_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive13_pri$next[7:0]$14957 - attribute \src "libresoc.v:202911.3-202912.37" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive13_pri$next[7:0]$14479 + attribute \src "libresoc.v:204040.3-204041.37" wire width 8 $0\xive13_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive14_pri$next[7:0]$14958 - attribute \src "libresoc.v:202913.3-202914.37" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive14_pri$next[7:0]$14480 + attribute \src "libresoc.v:204042.3-204043.37" wire width 8 $0\xive14_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive15_pri$next[7:0]$14959 - attribute \src "libresoc.v:202915.3-202916.37" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive15_pri$next[7:0]$14481 + attribute \src "libresoc.v:204044.3-204045.37" wire width 8 $0\xive15_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive1_pri$next[7:0]$14960 - attribute \src "libresoc.v:202887.3-202888.35" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive1_pri$next[7:0]$14482 + attribute \src "libresoc.v:204016.3-204017.35" wire width 8 $0\xive1_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive2_pri$next[7:0]$14961 - attribute \src "libresoc.v:202889.3-202890.35" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive2_pri$next[7:0]$14483 + attribute \src "libresoc.v:204018.3-204019.35" wire width 8 $0\xive2_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive3_pri$next[7:0]$14962 - attribute \src "libresoc.v:202891.3-202892.35" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive3_pri$next[7:0]$14484 + attribute \src "libresoc.v:204020.3-204021.35" wire width 8 $0\xive3_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive4_pri$next[7:0]$14963 - attribute \src "libresoc.v:202893.3-202894.35" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive4_pri$next[7:0]$14485 + attribute \src "libresoc.v:204022.3-204023.35" wire width 8 $0\xive4_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive5_pri$next[7:0]$14964 - attribute \src "libresoc.v:202895.3-202896.35" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive5_pri$next[7:0]$14486 + attribute \src "libresoc.v:204024.3-204025.35" wire width 8 $0\xive5_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive6_pri$next[7:0]$14965 - attribute \src "libresoc.v:202897.3-202898.35" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive6_pri$next[7:0]$14487 + attribute \src "libresoc.v:204026.3-204027.35" wire width 8 $0\xive6_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive7_pri$next[7:0]$14966 - attribute \src "libresoc.v:202899.3-202900.35" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive7_pri$next[7:0]$14488 + attribute \src "libresoc.v:204028.3-204029.35" wire width 8 $0\xive7_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive8_pri$next[7:0]$14967 - attribute \src "libresoc.v:202901.3-202902.35" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive8_pri$next[7:0]$14489 + attribute \src "libresoc.v:204030.3-204031.35" wire width 8 $0\xive8_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive9_pri$next[7:0]$14968 - attribute \src "libresoc.v:202903.3-202904.35" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $0\xive9_pri$next[7:0]$14490 + attribute \src "libresoc.v:204032.3-204033.35" wire width 8 $0\xive9_pri[7:0] - attribute \src "libresoc.v:203308.3-203357.6" + attribute \src "libresoc.v:204437.3-204486.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:203019.3-203028.6" + attribute \src "libresoc.v:204148.3-204157.6" wire width 4 $1\cur_idx0[3:0] - attribute \src "libresoc.v:203228.3-203237.6" + attribute \src "libresoc.v:204357.3-204366.6" wire width 4 $1\cur_idx10[3:0] - attribute \src "libresoc.v:203248.3-203257.6" + attribute \src "libresoc.v:204377.3-204386.6" wire width 4 $1\cur_idx11[3:0] - attribute \src "libresoc.v:203268.3-203277.6" + attribute \src "libresoc.v:204397.3-204406.6" wire width 4 $1\cur_idx12[3:0] - attribute \src "libresoc.v:203288.3-203297.6" + attribute \src "libresoc.v:204417.3-204426.6" wire width 4 $1\cur_idx13[3:0] - attribute \src "libresoc.v:203358.3-203367.6" + attribute \src "libresoc.v:204487.3-204496.6" wire width 4 $1\cur_idx14[3:0] - attribute \src "libresoc.v:203378.3-203387.6" + attribute \src "libresoc.v:204507.3-204516.6" wire width 4 $1\cur_idx15[3:0] - attribute \src "libresoc.v:203039.3-203048.6" + attribute \src "libresoc.v:204168.3-204177.6" wire width 4 $1\cur_idx1[3:0] - attribute \src "libresoc.v:203059.3-203068.6" + attribute \src "libresoc.v:204188.3-204197.6" wire width 4 $1\cur_idx2[3:0] - attribute \src "libresoc.v:203079.3-203088.6" + attribute \src "libresoc.v:204208.3-204217.6" wire width 4 $1\cur_idx3[3:0] - attribute \src "libresoc.v:203108.3-203117.6" + attribute \src "libresoc.v:204237.3-204246.6" wire width 4 $1\cur_idx4[3:0] - attribute \src "libresoc.v:203128.3-203137.6" + attribute \src "libresoc.v:204257.3-204266.6" wire width 4 $1\cur_idx5[3:0] - attribute \src "libresoc.v:203148.3-203157.6" + attribute \src "libresoc.v:204277.3-204286.6" wire width 4 $1\cur_idx6[3:0] - attribute \src "libresoc.v:203168.3-203177.6" + attribute \src "libresoc.v:204297.3-204306.6" wire width 4 $1\cur_idx7[3:0] - attribute \src "libresoc.v:203188.3-203197.6" + attribute \src "libresoc.v:204317.3-204326.6" wire width 4 $1\cur_idx8[3:0] - attribute \src "libresoc.v:203208.3-203217.6" + attribute \src "libresoc.v:204337.3-204346.6" wire width 4 $1\cur_idx9[3:0] - attribute \src "libresoc.v:203009.3-203018.6" + attribute \src "libresoc.v:204138.3-204147.6" wire width 8 $1\cur_pri0[7:0] - attribute \src "libresoc.v:203218.3-203227.6" + attribute \src "libresoc.v:204347.3-204356.6" wire width 8 $1\cur_pri10[7:0] - attribute \src "libresoc.v:203238.3-203247.6" + attribute \src "libresoc.v:204367.3-204376.6" wire width 8 $1\cur_pri11[7:0] - attribute \src "libresoc.v:203258.3-203267.6" + attribute \src "libresoc.v:204387.3-204396.6" wire width 8 $1\cur_pri12[7:0] - attribute \src "libresoc.v:203278.3-203287.6" + attribute \src "libresoc.v:204407.3-204416.6" wire width 8 $1\cur_pri13[7:0] - attribute \src "libresoc.v:203298.3-203307.6" + attribute \src "libresoc.v:204427.3-204436.6" wire width 8 $1\cur_pri14[7:0] - attribute \src "libresoc.v:203368.3-203377.6" + attribute \src "libresoc.v:204497.3-204506.6" wire width 8 $1\cur_pri15[7:0] - attribute \src "libresoc.v:203029.3-203038.6" + attribute \src "libresoc.v:204158.3-204167.6" wire width 8 $1\cur_pri1[7:0] - attribute \src "libresoc.v:203049.3-203058.6" + attribute \src "libresoc.v:204178.3-204187.6" wire width 8 $1\cur_pri2[7:0] - attribute \src "libresoc.v:203069.3-203078.6" + attribute \src "libresoc.v:204198.3-204207.6" wire width 8 $1\cur_pri3[7:0] - attribute \src "libresoc.v:203089.3-203098.6" + attribute \src "libresoc.v:204218.3-204227.6" wire width 8 $1\cur_pri4[7:0] - attribute \src "libresoc.v:203118.3-203127.6" + attribute \src "libresoc.v:204247.3-204256.6" wire width 8 $1\cur_pri5[7:0] - attribute \src "libresoc.v:203138.3-203147.6" + attribute \src "libresoc.v:204267.3-204276.6" wire width 8 $1\cur_pri6[7:0] - attribute \src "libresoc.v:203158.3-203167.6" + attribute \src "libresoc.v:204287.3-204296.6" wire width 8 $1\cur_pri7[7:0] - attribute \src "libresoc.v:203178.3-203187.6" + attribute \src "libresoc.v:204307.3-204316.6" wire width 8 $1\cur_pri8[7:0] - attribute \src "libresoc.v:203198.3-203207.6" + attribute \src "libresoc.v:204327.3-204336.6" wire width 8 $1\cur_pri9[7:0] - attribute \src "libresoc.v:203388.3-203397.6" + attribute \src "libresoc.v:204517.3-204526.6" wire $1\ibit[0:0] - attribute \src "libresoc.v:202660.13-202660.30" + attribute \src "libresoc.v:203789.13-203789.30" wire width 8 $1\icp_o_pri[7:0] - attribute \src "libresoc.v:202665.13-202665.29" + attribute \src "libresoc.v:203794.13-203794.29" wire width 4 $1\icp_o_src[3:0] - attribute \src "libresoc.v:203407.3-203415.6" - wire $1\ics_wb__ack$next[0:0]$15075 - attribute \src "libresoc.v:202674.7-202674.25" + attribute \src "libresoc.v:204536.3-204544.6" + wire $1\ics_wb__ack$next[0:0]$14597 + attribute \src "libresoc.v:203803.7-203803.25" wire $1\ics_wb__ack[0:0] - attribute \src "libresoc.v:203398.3-203406.6" - wire width 32 $1\ics_wb__dat_r$next[31:0]$15072 - attribute \src "libresoc.v:202683.14-202683.35" + attribute \src "libresoc.v:204527.3-204535.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$14594 + attribute \src "libresoc.v:203812.14-203812.35" wire width 32 $1\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:203099.3-203107.6" - wire width 16 $1\int_level_l$next[15:0]$15044 - attribute \src "libresoc.v:202695.14-202695.36" + attribute \src "libresoc.v:204228.3-204236.6" + wire width 16 $1\int_level_l$next[15:0]$14566 + attribute \src "libresoc.v:203824.14-203824.36" wire width 16 $1\int_level_l[15:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive0_pri$next[7:0]$14969 - attribute \src "libresoc.v:202715.13-202715.30" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive0_pri$next[7:0]$14491 + attribute \src "libresoc.v:203844.13-203844.30" wire width 8 $1\xive0_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive10_pri$next[7:0]$14970 - attribute \src "libresoc.v:202719.13-202719.31" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive10_pri$next[7:0]$14492 + attribute \src "libresoc.v:203848.13-203848.31" wire width 8 $1\xive10_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive11_pri$next[7:0]$14971 - attribute \src "libresoc.v:202723.13-202723.31" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive11_pri$next[7:0]$14493 + attribute \src "libresoc.v:203852.13-203852.31" wire width 8 $1\xive11_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive12_pri$next[7:0]$14972 - attribute \src "libresoc.v:202727.13-202727.31" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive12_pri$next[7:0]$14494 + attribute \src "libresoc.v:203856.13-203856.31" wire width 8 $1\xive12_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive13_pri$next[7:0]$14973 - attribute \src "libresoc.v:202731.13-202731.31" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive13_pri$next[7:0]$14495 + attribute \src "libresoc.v:203860.13-203860.31" wire width 8 $1\xive13_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive14_pri$next[7:0]$14974 - attribute \src "libresoc.v:202735.13-202735.31" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive14_pri$next[7:0]$14496 + attribute \src "libresoc.v:203864.13-203864.31" wire width 8 $1\xive14_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive15_pri$next[7:0]$14975 - attribute \src "libresoc.v:202739.13-202739.31" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive15_pri$next[7:0]$14497 + attribute \src "libresoc.v:203868.13-203868.31" wire width 8 $1\xive15_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive1_pri$next[7:0]$14976 - attribute \src "libresoc.v:202743.13-202743.30" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive1_pri$next[7:0]$14498 + attribute \src "libresoc.v:203872.13-203872.30" wire width 8 $1\xive1_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive2_pri$next[7:0]$14977 - attribute \src "libresoc.v:202747.13-202747.30" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive2_pri$next[7:0]$14499 + attribute \src "libresoc.v:203876.13-203876.30" wire width 8 $1\xive2_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive3_pri$next[7:0]$14978 - attribute \src "libresoc.v:202751.13-202751.30" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive3_pri$next[7:0]$14500 + attribute \src "libresoc.v:203880.13-203880.30" wire width 8 $1\xive3_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive4_pri$next[7:0]$14979 - attribute \src "libresoc.v:202755.13-202755.30" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive4_pri$next[7:0]$14501 + attribute \src "libresoc.v:203884.13-203884.30" wire width 8 $1\xive4_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive5_pri$next[7:0]$14980 - attribute \src "libresoc.v:202759.13-202759.30" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive5_pri$next[7:0]$14502 + attribute \src "libresoc.v:203888.13-203888.30" wire width 8 $1\xive5_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive6_pri$next[7:0]$14981 - attribute \src "libresoc.v:202763.13-202763.30" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive6_pri$next[7:0]$14503 + attribute \src "libresoc.v:203892.13-203892.30" wire width 8 $1\xive6_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive7_pri$next[7:0]$14982 - attribute \src "libresoc.v:202767.13-202767.30" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive7_pri$next[7:0]$14504 + attribute \src "libresoc.v:203896.13-203896.30" wire width 8 $1\xive7_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive8_pri$next[7:0]$14983 - attribute \src "libresoc.v:202771.13-202771.30" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive8_pri$next[7:0]$14505 + attribute \src "libresoc.v:203900.13-203900.30" wire width 8 $1\xive8_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive9_pri$next[7:0]$14984 - attribute \src "libresoc.v:202775.13-202775.30" + attribute \src "libresoc.v:204052.3-204137.6" + wire width 8 $1\xive9_pri$next[7:0]$14506 + attribute \src "libresoc.v:203904.13-203904.30" wire width 8 $1\xive9_pri[7:0] - attribute \src "libresoc.v:203308.3-203357.6" + attribute \src "libresoc.v:204437.3-204486.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive0_pri$next[7:0]$14985 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive10_pri$next[7:0]$14986 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive11_pri$next[7:0]$14987 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive12_pri$next[7:0]$14988 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive13_pri$next[7:0]$14989 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive14_pri$next[7:0]$14990 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive15_pri$next[7:0]$14991 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive1_pri$next[7:0]$14992 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive2_pri$next[7:0]$14993 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive3_pri$next[7:0]$14994 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive4_pri$next[7:0]$14995 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive5_pri$next[7:0]$14996 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive6_pri$next[7:0]$14997 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive7_pri$next[7:0]$14998 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive8_pri$next[7:0]$14999 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive9_pri$next[7:0]$15000 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive0_pri$next[7:0]$15001 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive10_pri$next[7:0]$15002 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive11_pri$next[7:0]$15003 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive12_pri$next[7:0]$15004 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive13_pri$next[7:0]$15005 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive14_pri$next[7:0]$15006 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive15_pri$next[7:0]$15007 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive1_pri$next[7:0]$15008 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive2_pri$next[7:0]$15009 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive3_pri$next[7:0]$15010 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive4_pri$next[7:0]$15011 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive5_pri$next[7:0]$15012 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive6_pri$next[7:0]$15013 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive7_pri$next[7:0]$15014 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive8_pri$next[7:0]$15015 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $3\xive9_pri$next[7:0]$15016 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $4\xive0_pri$next[7:0]$15017 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $4\xive10_pri$next[7:0]$15018 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $4\xive11_pri$next[7:0]$15019 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $4\xive12_pri$next[7:0]$15020 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $4\xive13_pri$next[7:0]$15021 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $4\xive14_pri$next[7:0]$15022 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $4\xive15_pri$next[7:0]$15023 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $4\xive1_pri$next[7:0]$15024 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $4\xive2_pri$next[7:0]$15025 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $4\xive3_pri$next[7:0]$15026 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $4\xive4_pri$next[7:0]$15027 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $4\xive5_pri$next[7:0]$15028 - attribute \src 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"libresoc.v:204008.18-204008.111" + wire $lt$libresoc.v:204008$14451_Y + attribute \src "libresoc.v:203995.18-203995.40" + wire width 16 $shr$libresoc.v:203995$14438_Y + attribute \src "libresoc.v:203907.17-203907.114" + wire width 8 $ternary$libresoc.v:203907$14350_Y + attribute \src "libresoc.v:203929.18-203929.116" + wire width 8 $ternary$libresoc.v:203929$14372_Y + attribute \src "libresoc.v:203951.18-203951.116" + wire width 8 $ternary$libresoc.v:203951$14394_Y + attribute \src "libresoc.v:203966.19-203966.118" + wire width 8 $ternary$libresoc.v:203966$14409_Y + attribute \src "libresoc.v:203968.18-203968.116" + wire width 8 $ternary$libresoc.v:203968$14411_Y + attribute \src "libresoc.v:203970.18-203970.116" + wire width 8 $ternary$libresoc.v:203970$14413_Y + attribute \src "libresoc.v:203972.18-203972.116" + wire width 8 $ternary$libresoc.v:203972$14415_Y + attribute \src "libresoc.v:203974.18-203974.116" + wire width 8 $ternary$libresoc.v:203974$14417_Y + attribute \src "libresoc.v:203976.18-203976.116" + wire width 8 $ternary$libresoc.v:203976$14419_Y + attribute \src "libresoc.v:203979.18-203979.116" + wire width 8 $ternary$libresoc.v:203979$14422_Y + attribute \src "libresoc.v:203981.18-203981.116" + wire width 8 $ternary$libresoc.v:203981$14424_Y + attribute \src "libresoc.v:203983.18-203983.117" + wire width 8 $ternary$libresoc.v:203983$14426_Y + attribute \src "libresoc.v:203985.18-203985.117" + wire width 8 $ternary$libresoc.v:203985$14428_Y + attribute \src "libresoc.v:203987.18-203987.117" + wire width 8 $ternary$libresoc.v:203987$14430_Y + attribute \src "libresoc.v:203990.18-203990.117" + wire width 8 $ternary$libresoc.v:203990$14433_Y + attribute \src "libresoc.v:203992.18-203992.117" + wire width 8 $ternary$libresoc.v:203992$14435_Y + attribute \src "libresoc.v:203994.18-203994.117" + wire width 8 $ternary$libresoc.v:203994$14437_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" @@ -424187,7 +389096,7 @@ module \xics_ics wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 12 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx0 @@ -424285,7 +389194,7 @@ module \xics_ics wire input 7 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 11 \ics_wb__we - attribute \src "libresoc.v:202379.7-202379.15" + attribute \src "libresoc.v:203508.7-203508.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 5 \int_level_i @@ -424305,7 +389214,7 @@ module \xics_ics wire \reg_is_debug attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" wire \reg_is_xive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" wire \wb_valid @@ -424374,7 +389283,7 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202780$14830 + cell $and $and$libresoc.v:203909$14352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424382,10 +389291,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$99 - connect \Y $and$libresoc.v:202780$14830_Y + connect \Y $and$libresoc.v:203909$14352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202782$14832 + cell $and $and$libresoc.v:203911$14354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424393,10 +389302,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$103 - connect \Y $and$libresoc.v:202782$14832_Y + connect \Y $and$libresoc.v:203911$14354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202784$14834 + cell $and $and$libresoc.v:203913$14356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424404,10 +389313,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$107 - connect \Y $and$libresoc.v:202784$14834_Y + connect \Y $and$libresoc.v:203913$14356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202786$14836 + cell $and $and$libresoc.v:203915$14358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424415,10 +389324,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$111 - connect \Y $and$libresoc.v:202786$14836_Y + connect \Y $and$libresoc.v:203915$14358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202788$14838 + cell $and $and$libresoc.v:203917$14360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424426,10 +389335,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$115 - connect \Y $and$libresoc.v:202788$14838_Y + connect \Y $and$libresoc.v:203917$14360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202790$14840 + cell $and $and$libresoc.v:203919$14362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424437,10 +389346,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$119 - connect \Y $and$libresoc.v:202790$14840_Y + connect \Y $and$libresoc.v:203919$14362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202792$14842 + cell $and $and$libresoc.v:203921$14364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424448,10 +389357,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$123 - connect \Y $and$libresoc.v:202792$14842_Y + connect \Y $and$libresoc.v:203921$14364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202795$14845 + cell $and $and$libresoc.v:203924$14367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424459,10 +389368,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$127 - connect \Y $and$libresoc.v:202795$14845_Y + connect \Y $and$libresoc.v:203924$14367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202797$14847 + cell $and $and$libresoc.v:203926$14369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424470,10 +389379,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$131 - connect \Y $and$libresoc.v:202797$14847_Y + connect \Y $and$libresoc.v:203926$14369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202799$14849 + cell $and $and$libresoc.v:203928$14371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424481,10 +389390,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$135 - connect \Y $and$libresoc.v:202799$14849_Y + connect \Y $and$libresoc.v:203928$14371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202802$14852 + cell $and $and$libresoc.v:203931$14374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424492,10 +389401,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$139 - connect \Y $and$libresoc.v:202802$14852_Y + connect \Y $and$libresoc.v:203931$14374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202804$14854 + cell $and $and$libresoc.v:203933$14376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424503,10 +389412,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$143 - connect \Y $and$libresoc.v:202804$14854_Y + connect \Y $and$libresoc.v:203933$14376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202806$14856 + cell $and $and$libresoc.v:203935$14378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424514,10 +389423,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$147 - connect \Y $and$libresoc.v:202806$14856_Y + connect \Y $and$libresoc.v:203935$14378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202808$14858 + cell $and $and$libresoc.v:203937$14380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424525,10 +389434,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$151 - connect \Y $and$libresoc.v:202808$14858_Y + connect \Y $and$libresoc.v:203937$14380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202810$14860 + cell $and $and$libresoc.v:203939$14382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424536,10 +389445,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$155 - connect \Y $and$libresoc.v:202810$14860_Y + connect \Y $and$libresoc.v:203939$14382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202812$14862 + cell $and $and$libresoc.v:203941$14384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424547,10 +389456,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$159 - connect \Y $and$libresoc.v:202812$14862_Y + connect \Y $and$libresoc.v:203941$14384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202814$14864 + cell $and $and$libresoc.v:203943$14386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424558,10 +389467,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$163 - connect \Y $and$libresoc.v:202814$14864_Y + connect \Y $and$libresoc.v:203943$14386_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202817$14867 + cell $and $and$libresoc.v:203946$14389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424569,10 +389478,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$167 - connect \Y $and$libresoc.v:202817$14867_Y + connect \Y $and$libresoc.v:203946$14389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202819$14869 + cell $and $and$libresoc.v:203948$14391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424580,10 +389489,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$171 - connect \Y $and$libresoc.v:202819$14869_Y + connect \Y $and$libresoc.v:203948$14391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202821$14871 + cell $and $and$libresoc.v:203950$14393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424591,10 +389500,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$175 - connect \Y $and$libresoc.v:202821$14871_Y + connect \Y $and$libresoc.v:203950$14393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202824$14874 + cell $and $and$libresoc.v:203953$14396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424602,10 +389511,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$179 - connect \Y $and$libresoc.v:202824$14874_Y + connect \Y $and$libresoc.v:203953$14396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202826$14876 + cell $and $and$libresoc.v:203955$14398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424613,10 +389522,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$183 - connect \Y $and$libresoc.v:202826$14876_Y + connect \Y $and$libresoc.v:203955$14398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202828$14878 + cell $and $and$libresoc.v:203957$14400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424624,10 +389533,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$187 - connect \Y $and$libresoc.v:202828$14878_Y + connect \Y $and$libresoc.v:203957$14400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202830$14880 + cell $and $and$libresoc.v:203959$14402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424635,10 +389544,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$191 - connect \Y $and$libresoc.v:202830$14880_Y + connect \Y $and$libresoc.v:203959$14402_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202832$14882 + cell $and $and$libresoc.v:203961$14404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424646,10 +389555,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$195 - connect \Y $and$libresoc.v:202832$14882_Y + connect \Y $and$libresoc.v:203961$14404_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202835$14885 + cell $and $and$libresoc.v:203964$14407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424657,10 +389566,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$199 - connect \Y $and$libresoc.v:202835$14885_Y + connect \Y $and$libresoc.v:203964$14407_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - cell $and $and$libresoc.v:202859$14909 + cell $and $and$libresoc.v:203988$14431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424668,10 +389577,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__cyc connect \B \ics_wb__stb - connect \Y $and$libresoc.v:202859$14909_Y + connect \Y $and$libresoc.v:203988$14431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - cell $and $and$libresoc.v:202867$14917 + cell $and $and$libresoc.v:203996$14439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424679,10 +389588,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \wb_valid connect \B \ics_wb__we - connect \Y $and$libresoc.v:202867$14917_Y + connect \Y $and$libresoc.v:203996$14439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202869$14919 + cell $and $and$libresoc.v:203998$14441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424690,10 +389599,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$75 - connect \Y $and$libresoc.v:202869$14919_Y + connect \Y $and$libresoc.v:203998$14441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202871$14921 + cell $and $and$libresoc.v:204000$14443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424701,10 +389610,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$79 - connect \Y $and$libresoc.v:202871$14921_Y + connect \Y $and$libresoc.v:204000$14443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202873$14923 + cell $and $and$libresoc.v:204002$14445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424712,10 +389621,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$83 - connect \Y $and$libresoc.v:202873$14923_Y + connect \Y $and$libresoc.v:204002$14445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202876$14926 + cell $and $and$libresoc.v:204005$14448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424723,10 +389632,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$87 - connect \Y $and$libresoc.v:202876$14926_Y + connect \Y $and$libresoc.v:204005$14448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202878$14928 + cell $and $and$libresoc.v:204007$14450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424734,10 +389643,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$91 - connect \Y $and$libresoc.v:202878$14928_Y + connect \Y $and$libresoc.v:204007$14450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202880$14930 + cell $and $and$libresoc.v:204009$14452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424745,10 +389654,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$95 - connect \Y $and$libresoc.v:202880$14930_Y + connect \Y $and$libresoc.v:204009$14452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202794$14844 + cell $eq $eq$libresoc.v:203923$14366 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424756,10 +389665,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202794$14844_Y + connect \Y $eq$libresoc.v:203923$14366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202816$14866 + cell $eq $eq$libresoc.v:203945$14388 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424767,10 +389676,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202816$14866_Y + connect \Y $eq$libresoc.v:203945$14388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - cell $eq $eq$libresoc.v:202833$14883 + cell $eq $eq$libresoc.v:203962$14405 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -424778,10 +389687,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 1'0 - connect \Y $eq$libresoc.v:202833$14883_Y + connect \Y $eq$libresoc.v:203962$14405_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202836$14886 + cell $eq $eq$libresoc.v:203965$14408 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424789,10 +389698,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \cur_pri15 connect \B 8'11111111 - connect \Y $eq$libresoc.v:202836$14886_Y + connect \Y $eq$libresoc.v:203965$14408_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202838$14888 + cell $eq $eq$libresoc.v:203967$14410 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424800,10 +389709,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202838$14888_Y + connect \Y $eq$libresoc.v:203967$14410_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202840$14890 + cell $eq $eq$libresoc.v:203969$14412 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424811,10 +389720,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202840$14890_Y + connect \Y $eq$libresoc.v:203969$14412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202842$14892 + cell $eq $eq$libresoc.v:203971$14414 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424822,10 +389731,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202842$14892_Y + connect \Y $eq$libresoc.v:203971$14414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202844$14894 + cell $eq $eq$libresoc.v:203973$14416 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424833,10 +389742,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202844$14894_Y + connect \Y $eq$libresoc.v:203973$14416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202846$14896 + cell $eq $eq$libresoc.v:203975$14418 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424844,10 +389753,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202846$14896_Y + connect \Y $eq$libresoc.v:203975$14418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - cell $eq $eq$libresoc.v:202848$14898 + cell $eq $eq$libresoc.v:203977$14420 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -424855,10 +389764,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 3'100 - connect \Y $eq$libresoc.v:202848$14898_Y + connect \Y $eq$libresoc.v:203977$14420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202849$14899 + cell $eq $eq$libresoc.v:203978$14421 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424866,10 +389775,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202849$14899_Y + connect \Y $eq$libresoc.v:203978$14421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202851$14901 + cell $eq $eq$libresoc.v:203980$14423 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424877,10 +389786,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202851$14901_Y + connect \Y $eq$libresoc.v:203980$14423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202853$14903 + cell $eq $eq$libresoc.v:203982$14425 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424888,10 +389797,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202853$14903_Y + connect \Y $eq$libresoc.v:203982$14425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202855$14905 + cell $eq $eq$libresoc.v:203984$14427 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424899,10 +389808,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202855$14905_Y + connect \Y $eq$libresoc.v:203984$14427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202857$14907 + cell $eq $eq$libresoc.v:203986$14429 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424910,10 +389819,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202857$14907_Y + connect \Y $eq$libresoc.v:203986$14429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202860$14910 + cell $eq $eq$libresoc.v:203989$14432 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424921,10 +389830,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202860$14910_Y + connect \Y $eq$libresoc.v:203989$14432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202862$14912 + cell $eq $eq$libresoc.v:203991$14434 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424932,10 +389841,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202862$14912_Y + connect \Y $eq$libresoc.v:203991$14434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202864$14914 + cell $eq $eq$libresoc.v:203993$14436 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424943,10 +389852,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202864$14914_Y + connect \Y $eq$libresoc.v:203993$14436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202875$14925 + cell $eq $eq$libresoc.v:204004$14447 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424954,10 +389863,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202875$14925_Y + connect \Y $eq$libresoc.v:204004$14447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202779$14829 + cell $lt $lt$libresoc.v:203908$14351 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424965,10 +389874,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:202779$14829_Y + connect \Y $lt$libresoc.v:203908$14351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202781$14831 + cell $lt $lt$libresoc.v:203910$14353 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424976,10 +389885,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:202781$14831_Y + connect \Y $lt$libresoc.v:203910$14353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202783$14833 + cell $lt $lt$libresoc.v:203912$14355 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424987,10 +389896,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:202783$14833_Y + connect \Y $lt$libresoc.v:203912$14355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202785$14835 + cell $lt $lt$libresoc.v:203914$14357 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424998,10 +389907,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:202785$14835_Y + connect \Y $lt$libresoc.v:203914$14357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202787$14837 + cell $lt $lt$libresoc.v:203916$14359 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425009,10 +389918,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:202787$14837_Y + connect \Y $lt$libresoc.v:203916$14359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202789$14839 + cell $lt $lt$libresoc.v:203918$14361 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425020,10 +389929,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:202789$14839_Y + connect \Y $lt$libresoc.v:203918$14361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202791$14841 + cell $lt $lt$libresoc.v:203920$14363 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425031,10 +389940,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:202791$14841_Y + connect \Y $lt$libresoc.v:203920$14363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202793$14843 + cell $lt $lt$libresoc.v:203922$14365 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425042,10 +389951,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:202793$14843_Y + connect \Y $lt$libresoc.v:203922$14365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202796$14846 + cell $lt $lt$libresoc.v:203925$14368 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425053,10 +389962,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:202796$14846_Y + connect \Y $lt$libresoc.v:203925$14368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202798$14848 + cell $lt $lt$libresoc.v:203927$14370 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425064,10 +389973,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:202798$14848_Y + connect \Y $lt$libresoc.v:203927$14370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202801$14851 + cell $lt $lt$libresoc.v:203930$14373 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425075,10 +389984,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:202801$14851_Y + connect \Y $lt$libresoc.v:203930$14373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202803$14853 + cell $lt $lt$libresoc.v:203932$14375 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425086,10 +389995,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:202803$14853_Y + connect \Y $lt$libresoc.v:203932$14375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202805$14855 + cell $lt $lt$libresoc.v:203934$14377 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425097,10 +390006,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:202805$14855_Y + connect \Y $lt$libresoc.v:203934$14377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202807$14857 + cell $lt $lt$libresoc.v:203936$14379 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425108,10 +390017,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:202807$14857_Y + connect \Y $lt$libresoc.v:203936$14379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202809$14859 + cell $lt $lt$libresoc.v:203938$14381 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425119,10 +390028,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:202809$14859_Y + connect \Y $lt$libresoc.v:203938$14381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202811$14861 + cell $lt $lt$libresoc.v:203940$14383 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425130,10 +390039,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:202811$14861_Y + connect \Y $lt$libresoc.v:203940$14383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202813$14863 + cell $lt $lt$libresoc.v:203942$14385 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425141,10 +390050,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:202813$14863_Y + connect \Y $lt$libresoc.v:203942$14385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202815$14865 + cell $lt $lt$libresoc.v:203944$14387 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425152,10 +390061,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:202815$14865_Y + connect \Y $lt$libresoc.v:203944$14387_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202818$14868 + cell $lt $lt$libresoc.v:203947$14390 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425163,10 +390072,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:202818$14868_Y + connect \Y $lt$libresoc.v:203947$14390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202820$14870 + cell $lt $lt$libresoc.v:203949$14392 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425174,10 +390083,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:202820$14870_Y + connect \Y $lt$libresoc.v:203949$14392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202823$14873 + cell $lt $lt$libresoc.v:203952$14395 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425185,10 +390094,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:202823$14873_Y + connect \Y $lt$libresoc.v:203952$14395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202825$14875 + cell $lt $lt$libresoc.v:203954$14397 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425196,10 +390105,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:202825$14875_Y + connect \Y $lt$libresoc.v:203954$14397_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202827$14877 + cell $lt $lt$libresoc.v:203956$14399 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425207,10 +390116,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:202827$14877_Y + connect \Y $lt$libresoc.v:203956$14399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202829$14879 + cell $lt $lt$libresoc.v:203958$14401 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425218,10 +390127,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:202829$14879_Y + connect \Y $lt$libresoc.v:203958$14401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202831$14881 + cell $lt $lt$libresoc.v:203960$14403 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425229,10 +390138,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:202831$14881_Y + connect \Y $lt$libresoc.v:203960$14403_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202834$14884 + cell $lt $lt$libresoc.v:203963$14406 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425240,10 +390149,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:202834$14884_Y + connect \Y $lt$libresoc.v:203963$14406_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202868$14918 + cell $lt $lt$libresoc.v:203997$14440 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425251,10 +390160,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:202868$14918_Y + connect \Y $lt$libresoc.v:203997$14440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202870$14920 + cell $lt $lt$libresoc.v:203999$14442 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425262,10 +390171,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:202870$14920_Y + connect \Y $lt$libresoc.v:203999$14442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202872$14922 + cell $lt $lt$libresoc.v:204001$14444 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425273,10 +390182,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:202872$14922_Y + connect \Y $lt$libresoc.v:204001$14444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202874$14924 + cell $lt $lt$libresoc.v:204003$14446 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425284,10 +390193,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:202874$14924_Y + connect \Y $lt$libresoc.v:204003$14446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202877$14927 + cell $lt $lt$libresoc.v:204006$14449 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425295,10 +390204,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:202877$14927_Y + connect \Y $lt$libresoc.v:204006$14449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202879$14929 + cell $lt $lt$libresoc.v:204008$14451 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425306,10 +390215,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:202879$14929_Y + connect \Y $lt$libresoc.v:204008$14451_Y end - attribute \src "libresoc.v:202866.18-202866.40" - cell $shr $shr$libresoc.v:202866$14916 + attribute \src "libresoc.v:203995.18-203995.40" + cell $shr $shr$libresoc.v:203995$14438 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -425317,469 +390226,469 @@ module \xics_ics parameter \Y_WIDTH 16 connect \A \int_level_l connect \B \reg_idx - connect \Y $shr$libresoc.v:202866$14916_Y + connect \Y $shr$libresoc.v:203995$14438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202778$14828 + cell $mux $ternary$libresoc.v:203907$14350 parameter \WIDTH 8 connect \A \xive0_pri connect \B 8'11111111 connect \S \$8 - connect \Y $ternary$libresoc.v:202778$14828_Y + connect \Y $ternary$libresoc.v:203907$14350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202800$14850 + cell $mux $ternary$libresoc.v:203929$14372 parameter \WIDTH 8 connect \A \xive1_pri connect \B 8'11111111 connect \S \$12 - connect \Y $ternary$libresoc.v:202800$14850_Y + connect \Y $ternary$libresoc.v:203929$14372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202822$14872 + cell $mux $ternary$libresoc.v:203951$14394 parameter \WIDTH 8 connect \A \xive2_pri connect \B 8'11111111 connect \S \$16 - connect \Y $ternary$libresoc.v:202822$14872_Y + connect \Y $ternary$libresoc.v:203951$14394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202837$14887 + cell $mux $ternary$libresoc.v:203966$14409 parameter \WIDTH 8 connect \A \cur_pri15 connect \B 8'11111111 connect \S \$204 - connect \Y $ternary$libresoc.v:202837$14887_Y + connect \Y $ternary$libresoc.v:203966$14409_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202839$14889 + cell $mux $ternary$libresoc.v:203968$14411 parameter \WIDTH 8 connect \A \xive3_pri connect \B 8'11111111 connect \S \$20 - connect \Y $ternary$libresoc.v:202839$14889_Y + connect \Y $ternary$libresoc.v:203968$14411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202841$14891 + cell $mux $ternary$libresoc.v:203970$14413 parameter \WIDTH 8 connect \A \xive4_pri connect \B 8'11111111 connect \S \$24 - connect \Y $ternary$libresoc.v:202841$14891_Y + connect \Y $ternary$libresoc.v:203970$14413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202843$14893 + cell $mux $ternary$libresoc.v:203972$14415 parameter \WIDTH 8 connect \A \xive5_pri connect \B 8'11111111 connect \S \$28 - connect \Y $ternary$libresoc.v:202843$14893_Y + connect \Y $ternary$libresoc.v:203972$14415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202845$14895 + cell $mux $ternary$libresoc.v:203974$14417 parameter \WIDTH 8 connect \A \xive6_pri connect \B 8'11111111 connect \S \$32 - connect \Y $ternary$libresoc.v:202845$14895_Y + connect \Y $ternary$libresoc.v:203974$14417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202847$14897 + cell $mux $ternary$libresoc.v:203976$14419 parameter \WIDTH 8 connect \A \xive7_pri connect \B 8'11111111 connect \S \$36 - connect \Y $ternary$libresoc.v:202847$14897_Y + connect \Y $ternary$libresoc.v:203976$14419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202850$14900 + cell $mux $ternary$libresoc.v:203979$14422 parameter \WIDTH 8 connect \A \xive8_pri connect \B 8'11111111 connect \S \$40 - connect \Y $ternary$libresoc.v:202850$14900_Y + connect \Y $ternary$libresoc.v:203979$14422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202852$14902 + cell $mux $ternary$libresoc.v:203981$14424 parameter \WIDTH 8 connect \A \xive9_pri connect \B 8'11111111 connect \S \$44 - connect \Y $ternary$libresoc.v:202852$14902_Y + connect \Y $ternary$libresoc.v:203981$14424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202854$14904 + cell $mux $ternary$libresoc.v:203983$14426 parameter \WIDTH 8 connect \A \xive10_pri connect \B 8'11111111 connect \S \$48 - connect \Y $ternary$libresoc.v:202854$14904_Y + connect \Y $ternary$libresoc.v:203983$14426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202856$14906 + cell $mux $ternary$libresoc.v:203985$14428 parameter \WIDTH 8 connect \A \xive11_pri connect \B 8'11111111 connect \S \$52 - connect \Y $ternary$libresoc.v:202856$14906_Y + connect \Y $ternary$libresoc.v:203985$14428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202858$14908 + cell $mux $ternary$libresoc.v:203987$14430 parameter \WIDTH 8 connect \A \xive12_pri connect \B 8'11111111 connect \S \$56 - connect \Y $ternary$libresoc.v:202858$14908_Y + connect \Y $ternary$libresoc.v:203987$14430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202861$14911 + cell $mux $ternary$libresoc.v:203990$14433 parameter \WIDTH 8 connect \A \xive13_pri connect \B 8'11111111 connect \S \$60 - connect \Y $ternary$libresoc.v:202861$14911_Y + connect \Y $ternary$libresoc.v:203990$14433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202863$14913 + cell $mux $ternary$libresoc.v:203992$14435 parameter \WIDTH 8 connect \A \xive14_pri connect \B 8'11111111 connect \S \$64 - connect \Y $ternary$libresoc.v:202863$14913_Y + connect \Y $ternary$libresoc.v:203992$14435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202865$14915 + cell $mux $ternary$libresoc.v:203994$14437 parameter \WIDTH 8 connect \A \xive15_pri connect \B 8'11111111 connect \S \$68 - connect \Y $ternary$libresoc.v:202865$14915_Y + connect \Y $ternary$libresoc.v:203994$14437_Y end - attribute \src "libresoc.v:202379.7-202379.20" - process $proc$libresoc.v:202379$15076 + attribute \src "libresoc.v:203508.7-203508.20" + process $proc$libresoc.v:203508$14598 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:202660.13-202660.30" - process $proc$libresoc.v:202660$15077 + attribute \src "libresoc.v:203789.13-203789.30" + process $proc$libresoc.v:203789$14599 assign { } { } assign $1\icp_o_pri[7:0] 8'00000000 sync always sync init update \icp_o_pri $1\icp_o_pri[7:0] end - attribute \src "libresoc.v:202665.13-202665.29" - process $proc$libresoc.v:202665$15078 + attribute \src "libresoc.v:203794.13-203794.29" + process $proc$libresoc.v:203794$14600 assign { } { } assign $1\icp_o_src[3:0] 4'0000 sync always sync init update \icp_o_src $1\icp_o_src[3:0] end - attribute \src "libresoc.v:202674.7-202674.25" - process $proc$libresoc.v:202674$15079 + attribute \src "libresoc.v:203803.7-203803.25" + process $proc$libresoc.v:203803$14601 assign { } { } assign $1\ics_wb__ack[0:0] 1'0 sync always sync init update \ics_wb__ack $1\ics_wb__ack[0:0] end - attribute \src "libresoc.v:202683.14-202683.35" - process $proc$libresoc.v:202683$15080 + attribute \src "libresoc.v:203812.14-203812.35" + process $proc$libresoc.v:203812$14602 assign { } { } assign $1\ics_wb__dat_r[31:0] 0 sync always sync init update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:202695.14-202695.36" - process $proc$libresoc.v:202695$15081 + attribute \src "libresoc.v:203824.14-203824.36" + process $proc$libresoc.v:203824$14603 assign { } { } assign $1\int_level_l[15:0] 16'0000000000000000 sync always sync init update \int_level_l $1\int_level_l[15:0] end - attribute \src "libresoc.v:202715.13-202715.30" - process $proc$libresoc.v:202715$15082 + attribute \src "libresoc.v:203844.13-203844.30" + process $proc$libresoc.v:203844$14604 assign { } { } assign $1\xive0_pri[7:0] 8'11111111 sync always sync init update \xive0_pri $1\xive0_pri[7:0] end - attribute \src "libresoc.v:202719.13-202719.31" - process $proc$libresoc.v:202719$15083 + attribute \src "libresoc.v:203848.13-203848.31" + process $proc$libresoc.v:203848$14605 assign { } { } assign $1\xive10_pri[7:0] 8'11111111 sync always sync init update \xive10_pri $1\xive10_pri[7:0] end - attribute \src "libresoc.v:202723.13-202723.31" - process $proc$libresoc.v:202723$15084 + attribute \src "libresoc.v:203852.13-203852.31" + process $proc$libresoc.v:203852$14606 assign { } { } assign $1\xive11_pri[7:0] 8'11111111 sync always sync init update \xive11_pri $1\xive11_pri[7:0] end - attribute \src "libresoc.v:202727.13-202727.31" - process $proc$libresoc.v:202727$15085 + attribute \src "libresoc.v:203856.13-203856.31" + process $proc$libresoc.v:203856$14607 assign { } { } assign $1\xive12_pri[7:0] 8'11111111 sync always sync init update \xive12_pri $1\xive12_pri[7:0] end - attribute \src "libresoc.v:202731.13-202731.31" - process $proc$libresoc.v:202731$15086 + attribute \src "libresoc.v:203860.13-203860.31" + process $proc$libresoc.v:203860$14608 assign { } { } assign $1\xive13_pri[7:0] 8'11111111 sync always sync init update \xive13_pri $1\xive13_pri[7:0] end - attribute \src "libresoc.v:202735.13-202735.31" - process $proc$libresoc.v:202735$15087 + attribute \src "libresoc.v:203864.13-203864.31" + process $proc$libresoc.v:203864$14609 assign { } { } assign $1\xive14_pri[7:0] 8'11111111 sync always sync init update \xive14_pri $1\xive14_pri[7:0] end - attribute \src "libresoc.v:202739.13-202739.31" - process $proc$libresoc.v:202739$15088 + attribute \src "libresoc.v:203868.13-203868.31" + process $proc$libresoc.v:203868$14610 assign { } { } assign $1\xive15_pri[7:0] 8'11111111 sync always sync init update \xive15_pri $1\xive15_pri[7:0] end - attribute \src "libresoc.v:202743.13-202743.30" - process $proc$libresoc.v:202743$15089 + attribute \src "libresoc.v:203872.13-203872.30" + process $proc$libresoc.v:203872$14611 assign { } { } assign $1\xive1_pri[7:0] 8'11111111 sync always sync init update \xive1_pri $1\xive1_pri[7:0] end - attribute \src "libresoc.v:202747.13-202747.30" - process $proc$libresoc.v:202747$15090 + attribute \src "libresoc.v:203876.13-203876.30" + process $proc$libresoc.v:203876$14612 assign { } { } assign $1\xive2_pri[7:0] 8'11111111 sync always sync init update \xive2_pri $1\xive2_pri[7:0] end - attribute \src "libresoc.v:202751.13-202751.30" - process $proc$libresoc.v:202751$15091 + attribute \src "libresoc.v:203880.13-203880.30" + process $proc$libresoc.v:203880$14613 assign { } { } assign $1\xive3_pri[7:0] 8'11111111 sync always sync init update \xive3_pri $1\xive3_pri[7:0] end - attribute \src "libresoc.v:202755.13-202755.30" - process $proc$libresoc.v:202755$15092 + attribute \src "libresoc.v:203884.13-203884.30" + process $proc$libresoc.v:203884$14614 assign { } { } assign $1\xive4_pri[7:0] 8'11111111 sync always sync init update \xive4_pri $1\xive4_pri[7:0] end - attribute \src "libresoc.v:202759.13-202759.30" - process $proc$libresoc.v:202759$15093 + attribute \src "libresoc.v:203888.13-203888.30" + process $proc$libresoc.v:203888$14615 assign { } { } assign $1\xive5_pri[7:0] 8'11111111 sync always sync init update \xive5_pri $1\xive5_pri[7:0] end - attribute \src "libresoc.v:202763.13-202763.30" - process $proc$libresoc.v:202763$15094 + attribute \src "libresoc.v:203892.13-203892.30" + process $proc$libresoc.v:203892$14616 assign { } { } assign $1\xive6_pri[7:0] 8'11111111 sync always sync init update \xive6_pri $1\xive6_pri[7:0] end - attribute \src "libresoc.v:202767.13-202767.30" - process $proc$libresoc.v:202767$15095 + attribute \src "libresoc.v:203896.13-203896.30" + process $proc$libresoc.v:203896$14617 assign { } { } assign $1\xive7_pri[7:0] 8'11111111 sync always sync init update \xive7_pri $1\xive7_pri[7:0] end - attribute \src "libresoc.v:202771.13-202771.30" - process $proc$libresoc.v:202771$15096 + attribute \src "libresoc.v:203900.13-203900.30" + process $proc$libresoc.v:203900$14618 assign { } { } assign $1\xive8_pri[7:0] 8'11111111 sync always sync init update \xive8_pri $1\xive8_pri[7:0] end - attribute \src "libresoc.v:202775.13-202775.30" - process $proc$libresoc.v:202775$15097 + attribute \src "libresoc.v:203904.13-203904.30" + process $proc$libresoc.v:203904$14619 assign { } { } assign $1\xive9_pri[7:0] 8'11111111 sync always sync init update \xive9_pri $1\xive9_pri[7:0] end - attribute \src "libresoc.v:202881.3-202882.28" - process $proc$libresoc.v:202881$14931 + attribute \src "libresoc.v:204010.3-204011.28" + process $proc$libresoc.v:204010$14453 assign { } { } assign $0\icp_o_src[3:0] \cur_idx15 sync posedge \clk update \icp_o_src $0\icp_o_src[3:0] end - attribute \src "libresoc.v:202883.3-202884.25" - process $proc$libresoc.v:202883$14932 + attribute \src "libresoc.v:204012.3-204013.25" + process $proc$libresoc.v:204012$14454 assign { } { } assign $0\icp_o_pri[7:0] \$203 sync posedge \clk update \icp_o_pri $0\icp_o_pri[7:0] end - attribute \src "libresoc.v:202885.3-202886.35" - process $proc$libresoc.v:202885$14933 + attribute \src "libresoc.v:204014.3-204015.35" + process $proc$libresoc.v:204014$14455 assign { } { } assign $0\xive0_pri[7:0] \xive0_pri$next sync posedge \clk update \xive0_pri $0\xive0_pri[7:0] end - attribute \src "libresoc.v:202887.3-202888.35" - process $proc$libresoc.v:202887$14934 + attribute \src "libresoc.v:204016.3-204017.35" + process $proc$libresoc.v:204016$14456 assign { } { } assign $0\xive1_pri[7:0] \xive1_pri$next sync posedge \clk update \xive1_pri $0\xive1_pri[7:0] end - attribute \src "libresoc.v:202889.3-202890.35" - process $proc$libresoc.v:202889$14935 + attribute \src "libresoc.v:204018.3-204019.35" + process $proc$libresoc.v:204018$14457 assign { } { } assign $0\xive2_pri[7:0] \xive2_pri$next sync posedge \clk update \xive2_pri $0\xive2_pri[7:0] end - attribute \src "libresoc.v:202891.3-202892.35" - process $proc$libresoc.v:202891$14936 + attribute \src "libresoc.v:204020.3-204021.35" + process $proc$libresoc.v:204020$14458 assign { } { } assign $0\xive3_pri[7:0] \xive3_pri$next sync posedge \clk update \xive3_pri $0\xive3_pri[7:0] end - attribute \src "libresoc.v:202893.3-202894.35" - process $proc$libresoc.v:202893$14937 + attribute \src "libresoc.v:204022.3-204023.35" + process $proc$libresoc.v:204022$14459 assign { } { } assign $0\xive4_pri[7:0] \xive4_pri$next sync posedge \clk update \xive4_pri $0\xive4_pri[7:0] end - attribute \src "libresoc.v:202895.3-202896.35" - process $proc$libresoc.v:202895$14938 + attribute \src "libresoc.v:204024.3-204025.35" + process $proc$libresoc.v:204024$14460 assign { } { } assign $0\xive5_pri[7:0] \xive5_pri$next sync posedge \clk update \xive5_pri $0\xive5_pri[7:0] end - attribute \src "libresoc.v:202897.3-202898.35" - process $proc$libresoc.v:202897$14939 + attribute \src "libresoc.v:204026.3-204027.35" + process $proc$libresoc.v:204026$14461 assign { } { } assign $0\xive6_pri[7:0] \xive6_pri$next sync posedge \clk update \xive6_pri $0\xive6_pri[7:0] end - attribute \src "libresoc.v:202899.3-202900.35" - process $proc$libresoc.v:202899$14940 + attribute \src "libresoc.v:204028.3-204029.35" + process $proc$libresoc.v:204028$14462 assign { } { } assign $0\xive7_pri[7:0] \xive7_pri$next sync posedge \clk update \xive7_pri $0\xive7_pri[7:0] end - attribute \src "libresoc.v:202901.3-202902.35" - process $proc$libresoc.v:202901$14941 + attribute \src "libresoc.v:204030.3-204031.35" + process $proc$libresoc.v:204030$14463 assign { } { } assign $0\xive8_pri[7:0] \xive8_pri$next sync posedge \clk update \xive8_pri $0\xive8_pri[7:0] end - attribute \src "libresoc.v:202903.3-202904.35" - process $proc$libresoc.v:202903$14942 + attribute \src "libresoc.v:204032.3-204033.35" + process $proc$libresoc.v:204032$14464 assign { } { } assign $0\xive9_pri[7:0] \xive9_pri$next sync posedge \clk update \xive9_pri $0\xive9_pri[7:0] end - attribute \src "libresoc.v:202905.3-202906.37" - process $proc$libresoc.v:202905$14943 + attribute \src "libresoc.v:204034.3-204035.37" + process $proc$libresoc.v:204034$14465 assign { } { } assign $0\xive10_pri[7:0] \xive10_pri$next sync posedge \clk update \xive10_pri $0\xive10_pri[7:0] end - attribute \src "libresoc.v:202907.3-202908.37" - process $proc$libresoc.v:202907$14944 + attribute \src "libresoc.v:204036.3-204037.37" + process $proc$libresoc.v:204036$14466 assign { } { } assign $0\xive11_pri[7:0] \xive11_pri$next sync posedge \clk update \xive11_pri $0\xive11_pri[7:0] end - attribute \src "libresoc.v:202909.3-202910.37" - process $proc$libresoc.v:202909$14945 + attribute \src "libresoc.v:204038.3-204039.37" + process $proc$libresoc.v:204038$14467 assign { } { } assign $0\xive12_pri[7:0] \xive12_pri$next sync posedge \clk update \xive12_pri $0\xive12_pri[7:0] end - attribute \src "libresoc.v:202911.3-202912.37" - process $proc$libresoc.v:202911$14946 + attribute \src "libresoc.v:204040.3-204041.37" + process $proc$libresoc.v:204040$14468 assign { } { } assign $0\xive13_pri[7:0] \xive13_pri$next sync posedge \clk update \xive13_pri $0\xive13_pri[7:0] end - attribute \src "libresoc.v:202913.3-202914.37" - process $proc$libresoc.v:202913$14947 + attribute \src "libresoc.v:204042.3-204043.37" + process $proc$libresoc.v:204042$14469 assign { } { } assign $0\xive14_pri[7:0] \xive14_pri$next sync posedge \clk update \xive14_pri $0\xive14_pri[7:0] end - attribute \src "libresoc.v:202915.3-202916.37" - process $proc$libresoc.v:202915$14948 + attribute \src "libresoc.v:204044.3-204045.37" + process $proc$libresoc.v:204044$14470 assign { } { } assign $0\xive15_pri[7:0] \xive15_pri$next sync posedge \clk update \xive15_pri $0\xive15_pri[7:0] end - attribute \src "libresoc.v:202917.3-202918.39" - process $proc$libresoc.v:202917$14949 + attribute \src "libresoc.v:204046.3-204047.39" + process $proc$libresoc.v:204046$14471 assign { } { } assign $0\ics_wb__ack[0:0] \ics_wb__ack$next sync posedge \clk update \ics_wb__ack $0\ics_wb__ack[0:0] end - attribute \src "libresoc.v:202919.3-202920.43" - process $proc$libresoc.v:202919$14950 + attribute \src "libresoc.v:204048.3-204049.43" + process $proc$libresoc.v:204048$14472 assign { } { } assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next sync posedge \clk update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:202921.3-202922.39" - process $proc$libresoc.v:202921$14951 + attribute \src "libresoc.v:204050.3-204051.39" + process $proc$libresoc.v:204050$14473 assign { } { } assign $0\int_level_l[15:0] \int_level_l$next sync posedge \clk update \int_level_l $0\int_level_l[15:0] end - attribute \src "libresoc.v:202923.3-203008.6" - process $proc$libresoc.v:202923$14952 + attribute \src "libresoc.v:204052.3-204137.6" + process $proc$libresoc.v:204052$14474 assign { } { } assign { } { } assign { } { } @@ -425828,25 +390737,25 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $0\xive0_pri$next[7:0]$14953 $4\xive0_pri$next[7:0]$15017 - assign $0\xive10_pri$next[7:0]$14954 $4\xive10_pri$next[7:0]$15018 - assign $0\xive11_pri$next[7:0]$14955 $4\xive11_pri$next[7:0]$15019 - assign $0\xive12_pri$next[7:0]$14956 $4\xive12_pri$next[7:0]$15020 - assign $0\xive13_pri$next[7:0]$14957 $4\xive13_pri$next[7:0]$15021 - assign $0\xive14_pri$next[7:0]$14958 $4\xive14_pri$next[7:0]$15022 - assign $0\xive15_pri$next[7:0]$14959 $4\xive15_pri$next[7:0]$15023 - assign $0\xive1_pri$next[7:0]$14960 $4\xive1_pri$next[7:0]$15024 - assign $0\xive2_pri$next[7:0]$14961 $4\xive2_pri$next[7:0]$15025 - assign $0\xive3_pri$next[7:0]$14962 $4\xive3_pri$next[7:0]$15026 - assign $0\xive4_pri$next[7:0]$14963 $4\xive4_pri$next[7:0]$15027 - assign $0\xive5_pri$next[7:0]$14964 $4\xive5_pri$next[7:0]$15028 - assign $0\xive6_pri$next[7:0]$14965 $4\xive6_pri$next[7:0]$15029 - assign $0\xive7_pri$next[7:0]$14966 $4\xive7_pri$next[7:0]$15030 - assign $0\xive8_pri$next[7:0]$14967 $4\xive8_pri$next[7:0]$15031 - assign $0\xive9_pri$next[7:0]$14968 $4\xive9_pri$next[7:0]$15032 - attribute \src "libresoc.v:202924.5-202924.29" + assign $0\xive0_pri$next[7:0]$14475 $4\xive0_pri$next[7:0]$14539 + assign $0\xive10_pri$next[7:0]$14476 $4\xive10_pri$next[7:0]$14540 + assign $0\xive11_pri$next[7:0]$14477 $4\xive11_pri$next[7:0]$14541 + assign $0\xive12_pri$next[7:0]$14478 $4\xive12_pri$next[7:0]$14542 + assign $0\xive13_pri$next[7:0]$14479 $4\xive13_pri$next[7:0]$14543 + assign $0\xive14_pri$next[7:0]$14480 $4\xive14_pri$next[7:0]$14544 + assign $0\xive15_pri$next[7:0]$14481 $4\xive15_pri$next[7:0]$14545 + assign $0\xive1_pri$next[7:0]$14482 $4\xive1_pri$next[7:0]$14546 + assign $0\xive2_pri$next[7:0]$14483 $4\xive2_pri$next[7:0]$14547 + assign $0\xive3_pri$next[7:0]$14484 $4\xive3_pri$next[7:0]$14548 + assign $0\xive4_pri$next[7:0]$14485 $4\xive4_pri$next[7:0]$14549 + assign $0\xive5_pri$next[7:0]$14486 $4\xive5_pri$next[7:0]$14550 + assign $0\xive6_pri$next[7:0]$14487 $4\xive6_pri$next[7:0]$14551 + assign $0\xive7_pri$next[7:0]$14488 $4\xive7_pri$next[7:0]$14552 + assign $0\xive8_pri$next[7:0]$14489 $4\xive8_pri$next[7:0]$14553 + assign $0\xive9_pri$next[7:0]$14490 $4\xive9_pri$next[7:0]$14554 + attribute \src "libresoc.v:204053.5-204053.29" switch \initial - attribute \src "libresoc.v:202924.9-202924.17" + attribute \src "libresoc.v:204053.9-204053.17" case 1'1 case end @@ -425870,22 +390779,22 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $1\xive0_pri$next[7:0]$14969 $2\xive0_pri$next[7:0]$14985 - assign $1\xive10_pri$next[7:0]$14970 $2\xive10_pri$next[7:0]$14986 - assign $1\xive11_pri$next[7:0]$14971 $2\xive11_pri$next[7:0]$14987 - assign $1\xive12_pri$next[7:0]$14972 $2\xive12_pri$next[7:0]$14988 - assign $1\xive13_pri$next[7:0]$14973 $2\xive13_pri$next[7:0]$14989 - assign $1\xive14_pri$next[7:0]$14974 $2\xive14_pri$next[7:0]$14990 - assign $1\xive15_pri$next[7:0]$14975 $2\xive15_pri$next[7:0]$14991 - assign $1\xive1_pri$next[7:0]$14976 $2\xive1_pri$next[7:0]$14992 - assign $1\xive2_pri$next[7:0]$14977 $2\xive2_pri$next[7:0]$14993 - assign $1\xive3_pri$next[7:0]$14978 $2\xive3_pri$next[7:0]$14994 - assign $1\xive4_pri$next[7:0]$14979 $2\xive4_pri$next[7:0]$14995 - assign $1\xive5_pri$next[7:0]$14980 $2\xive5_pri$next[7:0]$14996 - assign $1\xive6_pri$next[7:0]$14981 $2\xive6_pri$next[7:0]$14997 - assign $1\xive7_pri$next[7:0]$14982 $2\xive7_pri$next[7:0]$14998 - assign $1\xive8_pri$next[7:0]$14983 $2\xive8_pri$next[7:0]$14999 - assign $1\xive9_pri$next[7:0]$14984 $2\xive9_pri$next[7:0]$15000 + assign $1\xive0_pri$next[7:0]$14491 $2\xive0_pri$next[7:0]$14507 + assign $1\xive10_pri$next[7:0]$14492 $2\xive10_pri$next[7:0]$14508 + assign $1\xive11_pri$next[7:0]$14493 $2\xive11_pri$next[7:0]$14509 + assign $1\xive12_pri$next[7:0]$14494 $2\xive12_pri$next[7:0]$14510 + assign $1\xive13_pri$next[7:0]$14495 $2\xive13_pri$next[7:0]$14511 + assign $1\xive14_pri$next[7:0]$14496 $2\xive14_pri$next[7:0]$14512 + assign $1\xive15_pri$next[7:0]$14497 $2\xive15_pri$next[7:0]$14513 + assign $1\xive1_pri$next[7:0]$14498 $2\xive1_pri$next[7:0]$14514 + assign $1\xive2_pri$next[7:0]$14499 $2\xive2_pri$next[7:0]$14515 + assign $1\xive3_pri$next[7:0]$14500 $2\xive3_pri$next[7:0]$14516 + assign $1\xive4_pri$next[7:0]$14501 $2\xive4_pri$next[7:0]$14517 + assign $1\xive5_pri$next[7:0]$14502 $2\xive5_pri$next[7:0]$14518 + assign $1\xive6_pri$next[7:0]$14503 $2\xive6_pri$next[7:0]$14519 + assign $1\xive7_pri$next[7:0]$14504 $2\xive7_pri$next[7:0]$14520 + assign $1\xive8_pri$next[7:0]$14505 $2\xive8_pri$next[7:0]$14521 + assign $1\xive9_pri$next[7:0]$14506 $2\xive9_pri$next[7:0]$14522 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" switch \reg_is_xive attribute \src "libresoc.v:0.0-0.0" @@ -425906,381 +390815,381 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $2\xive0_pri$next[7:0]$14985 $3\xive0_pri$next[7:0]$15001 - assign $2\xive10_pri$next[7:0]$14986 $3\xive10_pri$next[7:0]$15002 - assign $2\xive11_pri$next[7:0]$14987 $3\xive11_pri$next[7:0]$15003 - assign $2\xive12_pri$next[7:0]$14988 $3\xive12_pri$next[7:0]$15004 - assign $2\xive13_pri$next[7:0]$14989 $3\xive13_pri$next[7:0]$15005 - assign $2\xive14_pri$next[7:0]$14990 $3\xive14_pri$next[7:0]$15006 - assign $2\xive15_pri$next[7:0]$14991 $3\xive15_pri$next[7:0]$15007 - assign $2\xive1_pri$next[7:0]$14992 $3\xive1_pri$next[7:0]$15008 - assign $2\xive2_pri$next[7:0]$14993 $3\xive2_pri$next[7:0]$15009 - assign $2\xive3_pri$next[7:0]$14994 $3\xive3_pri$next[7:0]$15010 - assign $2\xive4_pri$next[7:0]$14995 $3\xive4_pri$next[7:0]$15011 - assign $2\xive5_pri$next[7:0]$14996 $3\xive5_pri$next[7:0]$15012 - assign $2\xive6_pri$next[7:0]$14997 $3\xive6_pri$next[7:0]$15013 - assign $2\xive7_pri$next[7:0]$14998 $3\xive7_pri$next[7:0]$15014 - assign $2\xive8_pri$next[7:0]$14999 $3\xive8_pri$next[7:0]$15015 - assign $2\xive9_pri$next[7:0]$15000 $3\xive9_pri$next[7:0]$15016 + assign $2\xive0_pri$next[7:0]$14507 $3\xive0_pri$next[7:0]$14523 + assign $2\xive10_pri$next[7:0]$14508 $3\xive10_pri$next[7:0]$14524 + assign $2\xive11_pri$next[7:0]$14509 $3\xive11_pri$next[7:0]$14525 + assign $2\xive12_pri$next[7:0]$14510 $3\xive12_pri$next[7:0]$14526 + assign $2\xive13_pri$next[7:0]$14511 $3\xive13_pri$next[7:0]$14527 + assign $2\xive14_pri$next[7:0]$14512 $3\xive14_pri$next[7:0]$14528 + assign $2\xive15_pri$next[7:0]$14513 $3\xive15_pri$next[7:0]$14529 + assign $2\xive1_pri$next[7:0]$14514 $3\xive1_pri$next[7:0]$14530 + assign $2\xive2_pri$next[7:0]$14515 $3\xive2_pri$next[7:0]$14531 + assign $2\xive3_pri$next[7:0]$14516 $3\xive3_pri$next[7:0]$14532 + assign $2\xive4_pri$next[7:0]$14517 $3\xive4_pri$next[7:0]$14533 + assign $2\xive5_pri$next[7:0]$14518 $3\xive5_pri$next[7:0]$14534 + assign $2\xive6_pri$next[7:0]$14519 $3\xive6_pri$next[7:0]$14535 + assign $2\xive7_pri$next[7:0]$14520 $3\xive7_pri$next[7:0]$14536 + assign $2\xive8_pri$next[7:0]$14521 $3\xive8_pri$next[7:0]$14537 + assign $2\xive9_pri$next[7:0]$14522 $3\xive9_pri$next[7:0]$14538 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" switch \reg_idx attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive0_pri$next[7:0]$15001 \be_in [7:0] + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive0_pri$next[7:0]$14523 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0001 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri assign { } { } - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive1_pri$next[7:0]$15008 \be_in [7:0] + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive1_pri$next[7:0]$14530 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0010 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri assign { } { } - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive2_pri$next[7:0]$15009 \be_in [7:0] + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive2_pri$next[7:0]$14531 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0011 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri assign { } { } - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive3_pri$next[7:0]$15010 \be_in [7:0] + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive3_pri$next[7:0]$14532 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0100 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri assign { } { } - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive4_pri$next[7:0]$15011 \be_in [7:0] + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive4_pri$next[7:0]$14533 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0101 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri assign { } { } - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive5_pri$next[7:0]$15012 \be_in [7:0] + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive5_pri$next[7:0]$14534 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0110 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri assign { } { } - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive6_pri$next[7:0]$15013 \be_in [7:0] + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive6_pri$next[7:0]$14535 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0111 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri assign { } { } - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive7_pri$next[7:0]$15014 \be_in [7:0] + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive7_pri$next[7:0]$14536 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1000 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri assign { } { } - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive8_pri$next[7:0]$15015 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive8_pri$next[7:0]$14537 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1001 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri assign { } { } - assign $3\xive9_pri$next[7:0]$15016 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14538 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1010 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri assign { } { } - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive10_pri$next[7:0]$15002 \be_in [7:0] + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive10_pri$next[7:0]$14524 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1011 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri assign { } { } - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive11_pri$next[7:0]$15003 \be_in [7:0] + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive11_pri$next[7:0]$14525 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1100 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri assign { } { } - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive12_pri$next[7:0]$15004 \be_in [7:0] + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive12_pri$next[7:0]$14526 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1101 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri assign { } { } - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive13_pri$next[7:0]$15005 \be_in [7:0] + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive13_pri$next[7:0]$14527 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1110 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri assign { } { } - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive14_pri$next[7:0]$15006 \be_in [7:0] + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive14_pri$next[7:0]$14528 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'---- - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri assign { } { } - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive15_pri$next[7:0]$15007 \be_in [7:0] + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri + assign $3\xive15_pri$next[7:0]$14529 \be_in [7:0] case - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive0_pri$next[7:0]$14523 \xive0_pri + assign $3\xive10_pri$next[7:0]$14524 \xive10_pri + assign $3\xive11_pri$next[7:0]$14525 \xive11_pri + assign $3\xive12_pri$next[7:0]$14526 \xive12_pri + assign $3\xive13_pri$next[7:0]$14527 \xive13_pri + assign $3\xive14_pri$next[7:0]$14528 \xive14_pri + assign $3\xive15_pri$next[7:0]$14529 \xive15_pri + assign $3\xive1_pri$next[7:0]$14530 \xive1_pri + assign $3\xive2_pri$next[7:0]$14531 \xive2_pri + assign $3\xive3_pri$next[7:0]$14532 \xive3_pri + assign $3\xive4_pri$next[7:0]$14533 \xive4_pri + assign $3\xive5_pri$next[7:0]$14534 \xive5_pri + assign $3\xive6_pri$next[7:0]$14535 \xive6_pri + assign $3\xive7_pri$next[7:0]$14536 \xive7_pri + assign $3\xive8_pri$next[7:0]$14537 \xive8_pri + assign $3\xive9_pri$next[7:0]$14538 \xive9_pri end case - assign $2\xive0_pri$next[7:0]$14985 \xive0_pri - assign $2\xive10_pri$next[7:0]$14986 \xive10_pri - assign $2\xive11_pri$next[7:0]$14987 \xive11_pri - assign $2\xive12_pri$next[7:0]$14988 \xive12_pri - assign $2\xive13_pri$next[7:0]$14989 \xive13_pri - assign $2\xive14_pri$next[7:0]$14990 \xive14_pri - assign $2\xive15_pri$next[7:0]$14991 \xive15_pri - assign $2\xive1_pri$next[7:0]$14992 \xive1_pri - assign $2\xive2_pri$next[7:0]$14993 \xive2_pri - assign $2\xive3_pri$next[7:0]$14994 \xive3_pri - assign $2\xive4_pri$next[7:0]$14995 \xive4_pri - assign $2\xive5_pri$next[7:0]$14996 \xive5_pri - assign $2\xive6_pri$next[7:0]$14997 \xive6_pri - assign $2\xive7_pri$next[7:0]$14998 \xive7_pri - assign $2\xive8_pri$next[7:0]$14999 \xive8_pri - assign $2\xive9_pri$next[7:0]$15000 \xive9_pri - end - case - assign $1\xive0_pri$next[7:0]$14969 \xive0_pri - assign $1\xive10_pri$next[7:0]$14970 \xive10_pri - assign $1\xive11_pri$next[7:0]$14971 \xive11_pri - assign $1\xive12_pri$next[7:0]$14972 \xive12_pri - assign $1\xive13_pri$next[7:0]$14973 \xive13_pri - assign $1\xive14_pri$next[7:0]$14974 \xive14_pri - assign $1\xive15_pri$next[7:0]$14975 \xive15_pri - assign $1\xive1_pri$next[7:0]$14976 \xive1_pri - assign $1\xive2_pri$next[7:0]$14977 \xive2_pri - assign $1\xive3_pri$next[7:0]$14978 \xive3_pri - assign $1\xive4_pri$next[7:0]$14979 \xive4_pri - assign $1\xive5_pri$next[7:0]$14980 \xive5_pri - assign $1\xive6_pri$next[7:0]$14981 \xive6_pri - assign $1\xive7_pri$next[7:0]$14982 \xive7_pri - assign $1\xive8_pri$next[7:0]$14983 \xive8_pri - assign $1\xive9_pri$next[7:0]$14984 \xive9_pri + assign $2\xive0_pri$next[7:0]$14507 \xive0_pri + assign $2\xive10_pri$next[7:0]$14508 \xive10_pri + assign $2\xive11_pri$next[7:0]$14509 \xive11_pri + assign $2\xive12_pri$next[7:0]$14510 \xive12_pri + assign $2\xive13_pri$next[7:0]$14511 \xive13_pri + assign $2\xive14_pri$next[7:0]$14512 \xive14_pri + assign $2\xive15_pri$next[7:0]$14513 \xive15_pri + assign $2\xive1_pri$next[7:0]$14514 \xive1_pri + assign $2\xive2_pri$next[7:0]$14515 \xive2_pri + assign $2\xive3_pri$next[7:0]$14516 \xive3_pri + assign $2\xive4_pri$next[7:0]$14517 \xive4_pri + assign $2\xive5_pri$next[7:0]$14518 \xive5_pri + assign $2\xive6_pri$next[7:0]$14519 \xive6_pri + assign $2\xive7_pri$next[7:0]$14520 \xive7_pri + assign $2\xive8_pri$next[7:0]$14521 \xive8_pri + assign $2\xive9_pri$next[7:0]$14522 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$14491 \xive0_pri + assign $1\xive10_pri$next[7:0]$14492 \xive10_pri + assign $1\xive11_pri$next[7:0]$14493 \xive11_pri + assign $1\xive12_pri$next[7:0]$14494 \xive12_pri + assign $1\xive13_pri$next[7:0]$14495 \xive13_pri + assign $1\xive14_pri$next[7:0]$14496 \xive14_pri + assign $1\xive15_pri$next[7:0]$14497 \xive15_pri + assign $1\xive1_pri$next[7:0]$14498 \xive1_pri + assign $1\xive2_pri$next[7:0]$14499 \xive2_pri + assign $1\xive3_pri$next[7:0]$14500 \xive3_pri + assign $1\xive4_pri$next[7:0]$14501 \xive4_pri + assign $1\xive5_pri$next[7:0]$14502 \xive5_pri + assign $1\xive6_pri$next[7:0]$14503 \xive6_pri + assign $1\xive7_pri$next[7:0]$14504 \xive7_pri + assign $1\xive8_pri$next[7:0]$14505 \xive8_pri + assign $1\xive9_pri$next[7:0]$14506 \xive9_pri end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -426302,66 +391211,66 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $4\xive0_pri$next[7:0]$15017 8'11111111 - assign $4\xive1_pri$next[7:0]$15024 8'11111111 - assign $4\xive2_pri$next[7:0]$15025 8'11111111 - assign $4\xive3_pri$next[7:0]$15026 8'11111111 - assign $4\xive4_pri$next[7:0]$15027 8'11111111 - assign $4\xive5_pri$next[7:0]$15028 8'11111111 - assign $4\xive6_pri$next[7:0]$15029 8'11111111 - assign $4\xive7_pri$next[7:0]$15030 8'11111111 - assign $4\xive8_pri$next[7:0]$15031 8'11111111 - assign $4\xive9_pri$next[7:0]$15032 8'11111111 - assign $4\xive10_pri$next[7:0]$15018 8'11111111 - assign $4\xive11_pri$next[7:0]$15019 8'11111111 - assign $4\xive12_pri$next[7:0]$15020 8'11111111 - assign $4\xive13_pri$next[7:0]$15021 8'11111111 - assign $4\xive14_pri$next[7:0]$15022 8'11111111 - assign $4\xive15_pri$next[7:0]$15023 8'11111111 + assign $4\xive0_pri$next[7:0]$14539 8'11111111 + assign $4\xive1_pri$next[7:0]$14546 8'11111111 + assign $4\xive2_pri$next[7:0]$14547 8'11111111 + assign $4\xive3_pri$next[7:0]$14548 8'11111111 + assign $4\xive4_pri$next[7:0]$14549 8'11111111 + assign $4\xive5_pri$next[7:0]$14550 8'11111111 + assign $4\xive6_pri$next[7:0]$14551 8'11111111 + assign $4\xive7_pri$next[7:0]$14552 8'11111111 + assign $4\xive8_pri$next[7:0]$14553 8'11111111 + assign $4\xive9_pri$next[7:0]$14554 8'11111111 + assign $4\xive10_pri$next[7:0]$14540 8'11111111 + assign $4\xive11_pri$next[7:0]$14541 8'11111111 + assign $4\xive12_pri$next[7:0]$14542 8'11111111 + assign $4\xive13_pri$next[7:0]$14543 8'11111111 + assign $4\xive14_pri$next[7:0]$14544 8'11111111 + assign $4\xive15_pri$next[7:0]$14545 8'11111111 case - assign $4\xive0_pri$next[7:0]$15017 $1\xive0_pri$next[7:0]$14969 - assign $4\xive10_pri$next[7:0]$15018 $1\xive10_pri$next[7:0]$14970 - assign $4\xive11_pri$next[7:0]$15019 $1\xive11_pri$next[7:0]$14971 - assign $4\xive12_pri$next[7:0]$15020 $1\xive12_pri$next[7:0]$14972 - assign $4\xive13_pri$next[7:0]$15021 $1\xive13_pri$next[7:0]$14973 - assign $4\xive14_pri$next[7:0]$15022 $1\xive14_pri$next[7:0]$14974 - assign $4\xive15_pri$next[7:0]$15023 $1\xive15_pri$next[7:0]$14975 - assign $4\xive1_pri$next[7:0]$15024 $1\xive1_pri$next[7:0]$14976 - assign $4\xive2_pri$next[7:0]$15025 $1\xive2_pri$next[7:0]$14977 - assign $4\xive3_pri$next[7:0]$15026 $1\xive3_pri$next[7:0]$14978 - assign $4\xive4_pri$next[7:0]$15027 $1\xive4_pri$next[7:0]$14979 - assign $4\xive5_pri$next[7:0]$15028 $1\xive5_pri$next[7:0]$14980 - assign $4\xive6_pri$next[7:0]$15029 $1\xive6_pri$next[7:0]$14981 - assign $4\xive7_pri$next[7:0]$15030 $1\xive7_pri$next[7:0]$14982 - assign $4\xive8_pri$next[7:0]$15031 $1\xive8_pri$next[7:0]$14983 - assign $4\xive9_pri$next[7:0]$15032 $1\xive9_pri$next[7:0]$14984 + assign $4\xive0_pri$next[7:0]$14539 $1\xive0_pri$next[7:0]$14491 + assign $4\xive10_pri$next[7:0]$14540 $1\xive10_pri$next[7:0]$14492 + assign $4\xive11_pri$next[7:0]$14541 $1\xive11_pri$next[7:0]$14493 + assign $4\xive12_pri$next[7:0]$14542 $1\xive12_pri$next[7:0]$14494 + assign $4\xive13_pri$next[7:0]$14543 $1\xive13_pri$next[7:0]$14495 + assign $4\xive14_pri$next[7:0]$14544 $1\xive14_pri$next[7:0]$14496 + assign $4\xive15_pri$next[7:0]$14545 $1\xive15_pri$next[7:0]$14497 + assign $4\xive1_pri$next[7:0]$14546 $1\xive1_pri$next[7:0]$14498 + assign $4\xive2_pri$next[7:0]$14547 $1\xive2_pri$next[7:0]$14499 + assign $4\xive3_pri$next[7:0]$14548 $1\xive3_pri$next[7:0]$14500 + assign $4\xive4_pri$next[7:0]$14549 $1\xive4_pri$next[7:0]$14501 + assign $4\xive5_pri$next[7:0]$14550 $1\xive5_pri$next[7:0]$14502 + assign $4\xive6_pri$next[7:0]$14551 $1\xive6_pri$next[7:0]$14503 + assign $4\xive7_pri$next[7:0]$14552 $1\xive7_pri$next[7:0]$14504 + assign $4\xive8_pri$next[7:0]$14553 $1\xive8_pri$next[7:0]$14505 + assign $4\xive9_pri$next[7:0]$14554 $1\xive9_pri$next[7:0]$14506 end sync always - update \xive0_pri$next $0\xive0_pri$next[7:0]$14953 - update \xive10_pri$next $0\xive10_pri$next[7:0]$14954 - update \xive11_pri$next $0\xive11_pri$next[7:0]$14955 - update \xive12_pri$next $0\xive12_pri$next[7:0]$14956 - update \xive13_pri$next $0\xive13_pri$next[7:0]$14957 - update \xive14_pri$next $0\xive14_pri$next[7:0]$14958 - update \xive15_pri$next $0\xive15_pri$next[7:0]$14959 - update \xive1_pri$next $0\xive1_pri$next[7:0]$14960 - update \xive2_pri$next $0\xive2_pri$next[7:0]$14961 - update \xive3_pri$next $0\xive3_pri$next[7:0]$14962 - update \xive4_pri$next $0\xive4_pri$next[7:0]$14963 - update \xive5_pri$next $0\xive5_pri$next[7:0]$14964 - update \xive6_pri$next $0\xive6_pri$next[7:0]$14965 - update \xive7_pri$next $0\xive7_pri$next[7:0]$14966 - update \xive8_pri$next $0\xive8_pri$next[7:0]$14967 - update \xive9_pri$next $0\xive9_pri$next[7:0]$14968 + update \xive0_pri$next $0\xive0_pri$next[7:0]$14475 + update \xive10_pri$next $0\xive10_pri$next[7:0]$14476 + update \xive11_pri$next $0\xive11_pri$next[7:0]$14477 + update \xive12_pri$next $0\xive12_pri$next[7:0]$14478 + update \xive13_pri$next $0\xive13_pri$next[7:0]$14479 + update \xive14_pri$next $0\xive14_pri$next[7:0]$14480 + update \xive15_pri$next $0\xive15_pri$next[7:0]$14481 + update \xive1_pri$next $0\xive1_pri$next[7:0]$14482 + update \xive2_pri$next $0\xive2_pri$next[7:0]$14483 + update \xive3_pri$next $0\xive3_pri$next[7:0]$14484 + update \xive4_pri$next $0\xive4_pri$next[7:0]$14485 + update \xive5_pri$next $0\xive5_pri$next[7:0]$14486 + update \xive6_pri$next $0\xive6_pri$next[7:0]$14487 + update \xive7_pri$next $0\xive7_pri$next[7:0]$14488 + update \xive8_pri$next $0\xive8_pri$next[7:0]$14489 + update \xive9_pri$next $0\xive9_pri$next[7:0]$14490 end - attribute \src "libresoc.v:203009.3-203018.6" - process $proc$libresoc.v:203009$15033 + attribute \src "libresoc.v:204138.3-204147.6" + process $proc$libresoc.v:204138$14555 assign { } { } assign { } { } assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] - attribute \src "libresoc.v:203010.5-203010.29" + attribute \src "libresoc.v:204139.5-204139.29" switch \initial - attribute \src "libresoc.v:203010.9-203010.17" + attribute \src "libresoc.v:204139.9-204139.17" case 1'1 case end @@ -426377,14 +391286,14 @@ module \xics_ics sync always update \cur_pri0 $0\cur_pri0[7:0] end - attribute \src "libresoc.v:203019.3-203028.6" - process $proc$libresoc.v:203019$15034 + attribute \src "libresoc.v:204148.3-204157.6" + process $proc$libresoc.v:204148$14556 assign { } { } assign { } { } assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] - attribute \src "libresoc.v:203020.5-203020.29" + attribute \src "libresoc.v:204149.5-204149.29" switch \initial - attribute \src "libresoc.v:203020.9-203020.17" + attribute \src "libresoc.v:204149.9-204149.17" case 1'1 case end @@ -426400,14 +391309,14 @@ module \xics_ics sync always update \cur_idx0 $0\cur_idx0[3:0] end - attribute \src "libresoc.v:203029.3-203038.6" - process $proc$libresoc.v:203029$15035 + attribute \src "libresoc.v:204158.3-204167.6" + process $proc$libresoc.v:204158$14557 assign { } { } assign { } { } assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] - attribute \src "libresoc.v:203030.5-203030.29" + attribute \src "libresoc.v:204159.5-204159.29" switch \initial - attribute \src "libresoc.v:203030.9-203030.17" + attribute \src "libresoc.v:204159.9-204159.17" case 1'1 case end @@ -426423,14 +391332,14 @@ module \xics_ics sync always update \cur_pri1 $0\cur_pri1[7:0] end - attribute \src "libresoc.v:203039.3-203048.6" - process $proc$libresoc.v:203039$15036 + attribute \src "libresoc.v:204168.3-204177.6" + process $proc$libresoc.v:204168$14558 assign { } { } assign { } { } assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] - attribute \src "libresoc.v:203040.5-203040.29" + attribute \src "libresoc.v:204169.5-204169.29" switch \initial - attribute \src "libresoc.v:203040.9-203040.17" + attribute \src "libresoc.v:204169.9-204169.17" case 1'1 case end @@ -426446,14 +391355,14 @@ module \xics_ics sync always update \cur_idx1 $0\cur_idx1[3:0] end - attribute \src "libresoc.v:203049.3-203058.6" - process $proc$libresoc.v:203049$15037 + attribute \src "libresoc.v:204178.3-204187.6" + process $proc$libresoc.v:204178$14559 assign { } { } assign { } { } assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] - attribute \src "libresoc.v:203050.5-203050.29" + attribute \src "libresoc.v:204179.5-204179.29" switch \initial - attribute \src "libresoc.v:203050.9-203050.17" + attribute \src "libresoc.v:204179.9-204179.17" case 1'1 case end @@ -426469,14 +391378,14 @@ module \xics_ics sync always update \cur_pri2 $0\cur_pri2[7:0] end - attribute \src "libresoc.v:203059.3-203068.6" - process $proc$libresoc.v:203059$15038 + attribute \src "libresoc.v:204188.3-204197.6" + process $proc$libresoc.v:204188$14560 assign { } { } assign { } { } assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] - attribute \src "libresoc.v:203060.5-203060.29" + attribute \src "libresoc.v:204189.5-204189.29" switch \initial - attribute \src "libresoc.v:203060.9-203060.17" + attribute \src "libresoc.v:204189.9-204189.17" case 1'1 case end @@ -426492,14 +391401,14 @@ module \xics_ics sync always update \cur_idx2 $0\cur_idx2[3:0] end - attribute \src "libresoc.v:203069.3-203078.6" - process $proc$libresoc.v:203069$15039 + attribute \src "libresoc.v:204198.3-204207.6" + process $proc$libresoc.v:204198$14561 assign { } { } assign { } { } assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] - attribute \src "libresoc.v:203070.5-203070.29" + attribute \src "libresoc.v:204199.5-204199.29" switch \initial - attribute \src "libresoc.v:203070.9-203070.17" + attribute \src "libresoc.v:204199.9-204199.17" case 1'1 case end @@ -426515,14 +391424,14 @@ module \xics_ics sync always update \cur_pri3 $0\cur_pri3[7:0] end - attribute \src "libresoc.v:203079.3-203088.6" - process $proc$libresoc.v:203079$15040 + attribute \src "libresoc.v:204208.3-204217.6" + process $proc$libresoc.v:204208$14562 assign { } { } assign { } { } assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] - attribute \src "libresoc.v:203080.5-203080.29" + attribute \src "libresoc.v:204209.5-204209.29" switch \initial - attribute \src "libresoc.v:203080.9-203080.17" + attribute \src "libresoc.v:204209.9-204209.17" case 1'1 case end @@ -426538,14 +391447,14 @@ module \xics_ics sync always update \cur_idx3 $0\cur_idx3[3:0] end - attribute \src "libresoc.v:203089.3-203098.6" - process $proc$libresoc.v:203089$15041 + attribute \src "libresoc.v:204218.3-204227.6" + process $proc$libresoc.v:204218$14563 assign { } { } assign { } { } assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] - attribute \src "libresoc.v:203090.5-203090.29" + attribute \src "libresoc.v:204219.5-204219.29" switch \initial - attribute \src "libresoc.v:203090.9-203090.17" + attribute \src "libresoc.v:204219.9-204219.17" case 1'1 case end @@ -426561,14 +391470,14 @@ module \xics_ics sync always update \cur_pri4 $0\cur_pri4[7:0] end - attribute \src "libresoc.v:203099.3-203107.6" - process $proc$libresoc.v:203099$15042 + attribute \src "libresoc.v:204228.3-204236.6" + process $proc$libresoc.v:204228$14564 assign { } { } assign { } { } - assign $0\int_level_l$next[15:0]$15043 $1\int_level_l$next[15:0]$15044 - attribute \src "libresoc.v:203100.5-203100.29" + assign $0\int_level_l$next[15:0]$14565 $1\int_level_l$next[15:0]$14566 + attribute \src "libresoc.v:204229.5-204229.29" switch \initial - attribute \src "libresoc.v:203100.9-203100.17" + attribute \src "libresoc.v:204229.9-204229.17" case 1'1 case end @@ -426577,21 +391486,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\int_level_l$next[15:0]$15044 16'0000000000000000 + assign $1\int_level_l$next[15:0]$14566 16'0000000000000000 case - assign $1\int_level_l$next[15:0]$15044 \int_level_i + assign $1\int_level_l$next[15:0]$14566 \int_level_i end sync always - update \int_level_l$next $0\int_level_l$next[15:0]$15043 + update \int_level_l$next $0\int_level_l$next[15:0]$14565 end - attribute \src "libresoc.v:203108.3-203117.6" - process $proc$libresoc.v:203108$15045 + attribute \src "libresoc.v:204237.3-204246.6" + process $proc$libresoc.v:204237$14567 assign { } { } assign { } { } assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] - attribute \src "libresoc.v:203109.5-203109.29" + attribute \src "libresoc.v:204238.5-204238.29" switch \initial - attribute \src "libresoc.v:203109.9-203109.17" + attribute \src "libresoc.v:204238.9-204238.17" case 1'1 case end @@ -426607,14 +391516,14 @@ module \xics_ics sync always update \cur_idx4 $0\cur_idx4[3:0] end - attribute \src "libresoc.v:203118.3-203127.6" - process $proc$libresoc.v:203118$15046 + attribute \src "libresoc.v:204247.3-204256.6" + process $proc$libresoc.v:204247$14568 assign { } { } assign { } { } assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] - attribute \src "libresoc.v:203119.5-203119.29" + attribute \src "libresoc.v:204248.5-204248.29" switch \initial - attribute \src "libresoc.v:203119.9-203119.17" + attribute \src "libresoc.v:204248.9-204248.17" case 1'1 case end @@ -426630,14 +391539,14 @@ module \xics_ics sync always update \cur_pri5 $0\cur_pri5[7:0] end - attribute \src "libresoc.v:203128.3-203137.6" - process $proc$libresoc.v:203128$15047 + attribute \src "libresoc.v:204257.3-204266.6" + process $proc$libresoc.v:204257$14569 assign { } { } assign { } { } assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] - attribute \src "libresoc.v:203129.5-203129.29" + attribute \src "libresoc.v:204258.5-204258.29" switch \initial - attribute \src "libresoc.v:203129.9-203129.17" + attribute \src "libresoc.v:204258.9-204258.17" case 1'1 case end @@ -426653,14 +391562,14 @@ module \xics_ics sync always update \cur_idx5 $0\cur_idx5[3:0] end - attribute \src "libresoc.v:203138.3-203147.6" - process $proc$libresoc.v:203138$15048 + attribute \src "libresoc.v:204267.3-204276.6" + process $proc$libresoc.v:204267$14570 assign { } { } assign { } { } assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] - attribute \src "libresoc.v:203139.5-203139.29" + attribute \src "libresoc.v:204268.5-204268.29" switch \initial - attribute \src "libresoc.v:203139.9-203139.17" + attribute \src "libresoc.v:204268.9-204268.17" case 1'1 case end @@ -426676,14 +391585,14 @@ module \xics_ics sync always update \cur_pri6 $0\cur_pri6[7:0] end - attribute \src "libresoc.v:203148.3-203157.6" - process $proc$libresoc.v:203148$15049 + attribute \src "libresoc.v:204277.3-204286.6" + process $proc$libresoc.v:204277$14571 assign { } { } assign { } { } assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] - attribute \src "libresoc.v:203149.5-203149.29" + attribute \src "libresoc.v:204278.5-204278.29" switch \initial - attribute \src "libresoc.v:203149.9-203149.17" + attribute \src "libresoc.v:204278.9-204278.17" case 1'1 case end @@ -426699,14 +391608,14 @@ module \xics_ics sync always update \cur_idx6 $0\cur_idx6[3:0] end - attribute \src "libresoc.v:203158.3-203167.6" - process $proc$libresoc.v:203158$15050 + attribute \src "libresoc.v:204287.3-204296.6" + process $proc$libresoc.v:204287$14572 assign { } { } assign { } { } assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] - attribute \src "libresoc.v:203159.5-203159.29" + attribute \src "libresoc.v:204288.5-204288.29" switch \initial - attribute \src "libresoc.v:203159.9-203159.17" + attribute \src "libresoc.v:204288.9-204288.17" case 1'1 case end @@ -426722,14 +391631,14 @@ module \xics_ics sync always update \cur_pri7 $0\cur_pri7[7:0] end - attribute \src "libresoc.v:203168.3-203177.6" - process $proc$libresoc.v:203168$15051 + attribute \src "libresoc.v:204297.3-204306.6" + process $proc$libresoc.v:204297$14573 assign { } { } assign { } { } assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] - attribute \src "libresoc.v:203169.5-203169.29" + attribute \src "libresoc.v:204298.5-204298.29" switch \initial - attribute \src "libresoc.v:203169.9-203169.17" + attribute \src "libresoc.v:204298.9-204298.17" case 1'1 case end @@ -426745,14 +391654,14 @@ module \xics_ics sync always update \cur_idx7 $0\cur_idx7[3:0] end - attribute \src "libresoc.v:203178.3-203187.6" - process $proc$libresoc.v:203178$15052 + attribute \src "libresoc.v:204307.3-204316.6" + process $proc$libresoc.v:204307$14574 assign { } { } assign { } { } assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] - attribute \src "libresoc.v:203179.5-203179.29" + attribute \src "libresoc.v:204308.5-204308.29" switch \initial - attribute \src "libresoc.v:203179.9-203179.17" + attribute \src "libresoc.v:204308.9-204308.17" case 1'1 case end @@ -426768,14 +391677,14 @@ module \xics_ics sync always update \cur_pri8 $0\cur_pri8[7:0] end - attribute \src "libresoc.v:203188.3-203197.6" - process $proc$libresoc.v:203188$15053 + attribute \src "libresoc.v:204317.3-204326.6" + process $proc$libresoc.v:204317$14575 assign { } { } assign { } { } assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] - attribute \src "libresoc.v:203189.5-203189.29" + attribute \src "libresoc.v:204318.5-204318.29" switch \initial - attribute \src "libresoc.v:203189.9-203189.17" + attribute \src "libresoc.v:204318.9-204318.17" case 1'1 case end @@ -426791,14 +391700,14 @@ module \xics_ics sync always update \cur_idx8 $0\cur_idx8[3:0] end - attribute \src "libresoc.v:203198.3-203207.6" - process $proc$libresoc.v:203198$15054 + attribute \src "libresoc.v:204327.3-204336.6" + process $proc$libresoc.v:204327$14576 assign { } { } assign { } { } assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] - attribute \src "libresoc.v:203199.5-203199.29" + attribute \src "libresoc.v:204328.5-204328.29" switch \initial - attribute \src "libresoc.v:203199.9-203199.17" + attribute \src "libresoc.v:204328.9-204328.17" case 1'1 case end @@ -426814,14 +391723,14 @@ module \xics_ics sync always update \cur_pri9 $0\cur_pri9[7:0] end - attribute \src "libresoc.v:203208.3-203217.6" - process $proc$libresoc.v:203208$15055 + attribute \src "libresoc.v:204337.3-204346.6" + process $proc$libresoc.v:204337$14577 assign { } { } assign { } { } assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] - attribute \src "libresoc.v:203209.5-203209.29" + attribute \src "libresoc.v:204338.5-204338.29" switch \initial - attribute \src "libresoc.v:203209.9-203209.17" + attribute \src "libresoc.v:204338.9-204338.17" case 1'1 case end @@ -426837,14 +391746,14 @@ module \xics_ics sync always update \cur_idx9 $0\cur_idx9[3:0] end - attribute \src "libresoc.v:203218.3-203227.6" - process $proc$libresoc.v:203218$15056 + attribute \src "libresoc.v:204347.3-204356.6" + process $proc$libresoc.v:204347$14578 assign { } { } assign { } { } assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] - attribute \src "libresoc.v:203219.5-203219.29" + attribute \src "libresoc.v:204348.5-204348.29" switch \initial - attribute \src "libresoc.v:203219.9-203219.17" + attribute \src "libresoc.v:204348.9-204348.17" case 1'1 case end @@ -426860,14 +391769,14 @@ module \xics_ics sync always update \cur_pri10 $0\cur_pri10[7:0] end - attribute \src "libresoc.v:203228.3-203237.6" - process $proc$libresoc.v:203228$15057 + attribute \src "libresoc.v:204357.3-204366.6" + process $proc$libresoc.v:204357$14579 assign { } { } assign { } { } assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] - attribute \src "libresoc.v:203229.5-203229.29" + attribute \src "libresoc.v:204358.5-204358.29" switch \initial - attribute \src "libresoc.v:203229.9-203229.17" + attribute \src "libresoc.v:204358.9-204358.17" case 1'1 case end @@ -426883,14 +391792,14 @@ module \xics_ics sync always update \cur_idx10 $0\cur_idx10[3:0] end - attribute \src "libresoc.v:203238.3-203247.6" - process $proc$libresoc.v:203238$15058 + attribute \src "libresoc.v:204367.3-204376.6" + process $proc$libresoc.v:204367$14580 assign { } { } assign { } { } assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] - attribute \src "libresoc.v:203239.5-203239.29" + attribute \src "libresoc.v:204368.5-204368.29" switch \initial - attribute \src "libresoc.v:203239.9-203239.17" + attribute \src "libresoc.v:204368.9-204368.17" case 1'1 case end @@ -426906,14 +391815,14 @@ module \xics_ics sync always update \cur_pri11 $0\cur_pri11[7:0] end - attribute \src "libresoc.v:203248.3-203257.6" - process $proc$libresoc.v:203248$15059 + attribute \src "libresoc.v:204377.3-204386.6" + process $proc$libresoc.v:204377$14581 assign { } { } assign { } { } assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] - attribute \src "libresoc.v:203249.5-203249.29" + attribute \src "libresoc.v:204378.5-204378.29" switch \initial - attribute \src "libresoc.v:203249.9-203249.17" + attribute \src "libresoc.v:204378.9-204378.17" case 1'1 case end @@ -426929,14 +391838,14 @@ module \xics_ics sync always update \cur_idx11 $0\cur_idx11[3:0] end - attribute \src "libresoc.v:203258.3-203267.6" - process $proc$libresoc.v:203258$15060 + attribute \src "libresoc.v:204387.3-204396.6" + process $proc$libresoc.v:204387$14582 assign { } { } assign { } { } assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] - attribute \src "libresoc.v:203259.5-203259.29" + attribute \src "libresoc.v:204388.5-204388.29" switch \initial - attribute \src "libresoc.v:203259.9-203259.17" + attribute \src "libresoc.v:204388.9-204388.17" case 1'1 case end @@ -426952,14 +391861,14 @@ module \xics_ics sync always update \cur_pri12 $0\cur_pri12[7:0] end - attribute \src "libresoc.v:203268.3-203277.6" - process $proc$libresoc.v:203268$15061 + attribute \src "libresoc.v:204397.3-204406.6" + process $proc$libresoc.v:204397$14583 assign { } { } assign { } { } assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] - attribute \src "libresoc.v:203269.5-203269.29" + attribute \src "libresoc.v:204398.5-204398.29" switch \initial - attribute \src "libresoc.v:203269.9-203269.17" + attribute \src "libresoc.v:204398.9-204398.17" case 1'1 case end @@ -426975,14 +391884,14 @@ module \xics_ics sync always update \cur_idx12 $0\cur_idx12[3:0] end - attribute \src "libresoc.v:203278.3-203287.6" - process $proc$libresoc.v:203278$15062 + attribute \src "libresoc.v:204407.3-204416.6" + process $proc$libresoc.v:204407$14584 assign { } { } assign { } { } assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] - attribute \src "libresoc.v:203279.5-203279.29" + attribute \src "libresoc.v:204408.5-204408.29" switch \initial - attribute \src "libresoc.v:203279.9-203279.17" + attribute \src "libresoc.v:204408.9-204408.17" case 1'1 case end @@ -426998,14 +391907,14 @@ module \xics_ics sync always update \cur_pri13 $0\cur_pri13[7:0] end - attribute \src "libresoc.v:203288.3-203297.6" - process $proc$libresoc.v:203288$15063 + attribute \src "libresoc.v:204417.3-204426.6" + process $proc$libresoc.v:204417$14585 assign { } { } assign { } { } assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] - attribute \src "libresoc.v:203289.5-203289.29" + attribute \src "libresoc.v:204418.5-204418.29" switch \initial - attribute \src "libresoc.v:203289.9-203289.17" + attribute \src "libresoc.v:204418.9-204418.17" case 1'1 case end @@ -427021,14 +391930,14 @@ module \xics_ics sync always update \cur_idx13 $0\cur_idx13[3:0] end - attribute \src "libresoc.v:203298.3-203307.6" - process $proc$libresoc.v:203298$15064 + attribute \src "libresoc.v:204427.3-204436.6" + process $proc$libresoc.v:204427$14586 assign { } { } assign { } { } assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] - attribute \src "libresoc.v:203299.5-203299.29" + attribute \src "libresoc.v:204428.5-204428.29" switch \initial - attribute \src "libresoc.v:203299.9-203299.17" + attribute \src "libresoc.v:204428.9-204428.17" case 1'1 case end @@ -427044,14 +391953,14 @@ module \xics_ics sync always update \cur_pri14 $0\cur_pri14[7:0] end - attribute \src "libresoc.v:203308.3-203357.6" - process $proc$libresoc.v:203308$15065 + attribute \src "libresoc.v:204437.3-204486.6" + process $proc$libresoc.v:204437$14587 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:203309.5-203309.29" + attribute \src "libresoc.v:204438.5-204438.29" switch \initial - attribute \src "libresoc.v:203309.9-203309.17" + attribute \src "libresoc.v:204438.9-204438.17" case 1'1 case end @@ -427144,14 +392053,14 @@ module \xics_ics sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:203358.3-203367.6" - process $proc$libresoc.v:203358$15066 + attribute \src "libresoc.v:204487.3-204496.6" + process $proc$libresoc.v:204487$14588 assign { } { } assign { } { } assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] - attribute \src "libresoc.v:203359.5-203359.29" + attribute \src "libresoc.v:204488.5-204488.29" switch \initial - attribute \src "libresoc.v:203359.9-203359.17" + attribute \src "libresoc.v:204488.9-204488.17" case 1'1 case end @@ -427167,14 +392076,14 @@ module \xics_ics sync always update \cur_idx14 $0\cur_idx14[3:0] end - attribute \src "libresoc.v:203368.3-203377.6" - process $proc$libresoc.v:203368$15067 + attribute \src "libresoc.v:204497.3-204506.6" + process $proc$libresoc.v:204497$14589 assign { } { } assign { } { } assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] - attribute \src "libresoc.v:203369.5-203369.29" + attribute \src "libresoc.v:204498.5-204498.29" switch \initial - attribute \src "libresoc.v:203369.9-203369.17" + attribute \src "libresoc.v:204498.9-204498.17" case 1'1 case end @@ -427190,14 +392099,14 @@ module \xics_ics sync always update \cur_pri15 $0\cur_pri15[7:0] end - attribute \src "libresoc.v:203378.3-203387.6" - process $proc$libresoc.v:203378$15068 + attribute \src "libresoc.v:204507.3-204516.6" + process $proc$libresoc.v:204507$14590 assign { } { } assign { } { } assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] - attribute \src "libresoc.v:203379.5-203379.29" + attribute \src "libresoc.v:204508.5-204508.29" switch \initial - attribute \src "libresoc.v:203379.9-203379.17" + attribute \src "libresoc.v:204508.9-204508.17" case 1'1 case end @@ -427213,14 +392122,14 @@ module \xics_ics sync always update \cur_idx15 $0\cur_idx15[3:0] end - attribute \src "libresoc.v:203388.3-203397.6" - process $proc$libresoc.v:203388$15069 + attribute \src "libresoc.v:204517.3-204526.6" + process $proc$libresoc.v:204517$14591 assign { } { } assign { } { } assign $0\ibit[0:0] $1\ibit[0:0] - attribute \src "libresoc.v:203389.5-203389.29" + attribute \src "libresoc.v:204518.5-204518.29" switch \initial - attribute \src "libresoc.v:203389.9-203389.17" + attribute \src "libresoc.v:204518.9-204518.17" case 1'1 case end @@ -427236,14 +392145,14 @@ module \xics_ics sync always update \ibit $0\ibit[0:0] end - attribute \src "libresoc.v:203398.3-203406.6" - process $proc$libresoc.v:203398$15070 + attribute \src "libresoc.v:204527.3-204535.6" + process $proc$libresoc.v:204527$14592 assign { } { } assign { } { } - assign $0\ics_wb__dat_r$next[31:0]$15071 $1\ics_wb__dat_r$next[31:0]$15072 - attribute \src "libresoc.v:203399.5-203399.29" + assign $0\ics_wb__dat_r$next[31:0]$14593 $1\ics_wb__dat_r$next[31:0]$14594 + attribute \src "libresoc.v:204528.5-204528.29" switch \initial - attribute \src "libresoc.v:203399.9-203399.17" + attribute \src "libresoc.v:204528.9-204528.17" case 1'1 case end @@ -427252,21 +392161,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__dat_r$next[31:0]$15072 0 + assign $1\ics_wb__dat_r$next[31:0]$14594 0 case - assign $1\ics_wb__dat_r$next[31:0]$15072 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $1\ics_wb__dat_r$next[31:0]$14594 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } end sync always - update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$15071 + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14593 end - attribute \src "libresoc.v:203407.3-203415.6" - process $proc$libresoc.v:203407$15073 + attribute \src "libresoc.v:204536.3-204544.6" + process $proc$libresoc.v:204536$14595 assign { } { } assign { } { } - assign $0\ics_wb__ack$next[0:0]$15074 $1\ics_wb__ack$next[0:0]$15075 - attribute \src "libresoc.v:203408.5-203408.29" + assign $0\ics_wb__ack$next[0:0]$14596 $1\ics_wb__ack$next[0:0]$14597 + attribute \src "libresoc.v:204537.5-204537.29" switch \initial - attribute \src "libresoc.v:203408.9-203408.17" + attribute \src "libresoc.v:204537.9-204537.17" case 1'1 case end @@ -427275,116 +392184,116 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__ack$next[0:0]$15075 1'0 - case - assign $1\ics_wb__ack$next[0:0]$15075 \wb_valid - end - sync always - update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$15074 - end - connect \$7 $ternary$libresoc.v:202778$14828_Y - connect \$99 $lt$libresoc.v:202779$14829_Y - connect \$101 $and$libresoc.v:202780$14830_Y - connect \$103 $lt$libresoc.v:202781$14831_Y - connect \$105 $and$libresoc.v:202782$14832_Y - connect \$107 $lt$libresoc.v:202783$14833_Y - connect \$109 $and$libresoc.v:202784$14834_Y - connect \$111 $lt$libresoc.v:202785$14835_Y - connect \$113 $and$libresoc.v:202786$14836_Y - connect \$115 $lt$libresoc.v:202787$14837_Y - connect \$117 $and$libresoc.v:202788$14838_Y - connect \$119 $lt$libresoc.v:202789$14839_Y - connect \$121 $and$libresoc.v:202790$14840_Y - connect \$123 $lt$libresoc.v:202791$14841_Y - connect \$125 $and$libresoc.v:202792$14842_Y - connect \$127 $lt$libresoc.v:202793$14843_Y - connect \$12 $eq$libresoc.v:202794$14844_Y - connect \$129 $and$libresoc.v:202795$14845_Y - connect \$131 $lt$libresoc.v:202796$14846_Y - connect \$133 $and$libresoc.v:202797$14847_Y - connect \$135 $lt$libresoc.v:202798$14848_Y - connect \$137 $and$libresoc.v:202799$14849_Y - connect \$11 $ternary$libresoc.v:202800$14850_Y - connect \$139 $lt$libresoc.v:202801$14851_Y - connect \$141 $and$libresoc.v:202802$14852_Y - connect \$143 $lt$libresoc.v:202803$14853_Y - connect \$145 $and$libresoc.v:202804$14854_Y - connect \$147 $lt$libresoc.v:202805$14855_Y - connect \$149 $and$libresoc.v:202806$14856_Y - connect \$151 $lt$libresoc.v:202807$14857_Y - connect \$153 $and$libresoc.v:202808$14858_Y - connect \$155 $lt$libresoc.v:202809$14859_Y - connect \$157 $and$libresoc.v:202810$14860_Y - connect \$159 $lt$libresoc.v:202811$14861_Y - connect \$161 $and$libresoc.v:202812$14862_Y - connect \$163 $lt$libresoc.v:202813$14863_Y - connect \$165 $and$libresoc.v:202814$14864_Y - connect \$167 $lt$libresoc.v:202815$14865_Y - connect \$16 $eq$libresoc.v:202816$14866_Y - connect \$169 $and$libresoc.v:202817$14867_Y - connect \$171 $lt$libresoc.v:202818$14868_Y - connect \$173 $and$libresoc.v:202819$14869_Y - connect \$175 $lt$libresoc.v:202820$14870_Y - connect \$177 $and$libresoc.v:202821$14871_Y - connect \$15 $ternary$libresoc.v:202822$14872_Y - connect \$179 $lt$libresoc.v:202823$14873_Y - connect \$181 $and$libresoc.v:202824$14874_Y - connect \$183 $lt$libresoc.v:202825$14875_Y - connect \$185 $and$libresoc.v:202826$14876_Y - connect \$187 $lt$libresoc.v:202827$14877_Y - connect \$189 $and$libresoc.v:202828$14878_Y - connect \$191 $lt$libresoc.v:202829$14879_Y - connect \$193 $and$libresoc.v:202830$14880_Y - connect \$195 $lt$libresoc.v:202831$14881_Y - connect \$197 $and$libresoc.v:202832$14882_Y - connect \$1 $eq$libresoc.v:202833$14883_Y - connect \$199 $lt$libresoc.v:202834$14884_Y - connect \$201 $and$libresoc.v:202835$14885_Y - connect \$204 $eq$libresoc.v:202836$14886_Y - connect \$203 $ternary$libresoc.v:202837$14887_Y - connect \$20 $eq$libresoc.v:202838$14888_Y - connect \$19 $ternary$libresoc.v:202839$14889_Y - connect \$24 $eq$libresoc.v:202840$14890_Y - connect \$23 $ternary$libresoc.v:202841$14891_Y - connect \$28 $eq$libresoc.v:202842$14892_Y - connect \$27 $ternary$libresoc.v:202843$14893_Y - connect \$32 $eq$libresoc.v:202844$14894_Y - connect \$31 $ternary$libresoc.v:202845$14895_Y - connect \$36 $eq$libresoc.v:202846$14896_Y - connect \$35 $ternary$libresoc.v:202847$14897_Y - connect \$3 $eq$libresoc.v:202848$14898_Y - connect \$40 $eq$libresoc.v:202849$14899_Y - connect \$39 $ternary$libresoc.v:202850$14900_Y - connect \$44 $eq$libresoc.v:202851$14901_Y - connect \$43 $ternary$libresoc.v:202852$14902_Y - connect \$48 $eq$libresoc.v:202853$14903_Y - connect \$47 $ternary$libresoc.v:202854$14904_Y - connect \$52 $eq$libresoc.v:202855$14905_Y - connect \$51 $ternary$libresoc.v:202856$14906_Y - connect \$56 $eq$libresoc.v:202857$14907_Y - connect \$55 $ternary$libresoc.v:202858$14908_Y - connect \$5 $and$libresoc.v:202859$14909_Y - connect \$60 $eq$libresoc.v:202860$14910_Y - connect \$59 $ternary$libresoc.v:202861$14911_Y - connect \$64 $eq$libresoc.v:202862$14912_Y - connect \$63 $ternary$libresoc.v:202863$14913_Y - connect \$68 $eq$libresoc.v:202864$14914_Y - connect \$67 $ternary$libresoc.v:202865$14915_Y - connect \$71 $shr$libresoc.v:202866$14916_Y [0] - connect \$73 $and$libresoc.v:202867$14917_Y - connect \$75 $lt$libresoc.v:202868$14918_Y - connect \$77 $and$libresoc.v:202869$14919_Y - connect \$79 $lt$libresoc.v:202870$14920_Y - connect \$81 $and$libresoc.v:202871$14921_Y - connect \$83 $lt$libresoc.v:202872$14922_Y - connect \$85 $and$libresoc.v:202873$14923_Y - connect \$87 $lt$libresoc.v:202874$14924_Y - connect \$8 $eq$libresoc.v:202875$14925_Y - connect \$89 $and$libresoc.v:202876$14926_Y - connect \$91 $lt$libresoc.v:202877$14927_Y - connect \$93 $and$libresoc.v:202878$14928_Y - connect \$95 $lt$libresoc.v:202879$14929_Y - connect \$97 $and$libresoc.v:202880$14930_Y + assign $1\ics_wb__ack$next[0:0]$14597 1'0 + case + assign $1\ics_wb__ack$next[0:0]$14597 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14596 + end + connect \$7 $ternary$libresoc.v:203907$14350_Y + connect \$99 $lt$libresoc.v:203908$14351_Y + connect \$101 $and$libresoc.v:203909$14352_Y + connect \$103 $lt$libresoc.v:203910$14353_Y + connect \$105 $and$libresoc.v:203911$14354_Y + connect \$107 $lt$libresoc.v:203912$14355_Y + connect \$109 $and$libresoc.v:203913$14356_Y + connect \$111 $lt$libresoc.v:203914$14357_Y + connect \$113 $and$libresoc.v:203915$14358_Y + connect \$115 $lt$libresoc.v:203916$14359_Y + connect \$117 $and$libresoc.v:203917$14360_Y + connect \$119 $lt$libresoc.v:203918$14361_Y + connect \$121 $and$libresoc.v:203919$14362_Y + connect \$123 $lt$libresoc.v:203920$14363_Y + connect \$125 $and$libresoc.v:203921$14364_Y + connect \$127 $lt$libresoc.v:203922$14365_Y + connect \$12 $eq$libresoc.v:203923$14366_Y + connect \$129 $and$libresoc.v:203924$14367_Y + connect \$131 $lt$libresoc.v:203925$14368_Y + connect \$133 $and$libresoc.v:203926$14369_Y + connect \$135 $lt$libresoc.v:203927$14370_Y + connect \$137 $and$libresoc.v:203928$14371_Y + connect \$11 $ternary$libresoc.v:203929$14372_Y + connect \$139 $lt$libresoc.v:203930$14373_Y + connect \$141 $and$libresoc.v:203931$14374_Y + connect \$143 $lt$libresoc.v:203932$14375_Y + connect \$145 $and$libresoc.v:203933$14376_Y + connect \$147 $lt$libresoc.v:203934$14377_Y + connect \$149 $and$libresoc.v:203935$14378_Y + connect \$151 $lt$libresoc.v:203936$14379_Y + connect \$153 $and$libresoc.v:203937$14380_Y + connect \$155 $lt$libresoc.v:203938$14381_Y + connect \$157 $and$libresoc.v:203939$14382_Y + connect \$159 $lt$libresoc.v:203940$14383_Y + connect \$161 $and$libresoc.v:203941$14384_Y + connect \$163 $lt$libresoc.v:203942$14385_Y + connect \$165 $and$libresoc.v:203943$14386_Y + connect \$167 $lt$libresoc.v:203944$14387_Y + connect \$16 $eq$libresoc.v:203945$14388_Y + connect \$169 $and$libresoc.v:203946$14389_Y + connect \$171 $lt$libresoc.v:203947$14390_Y + connect \$173 $and$libresoc.v:203948$14391_Y + connect \$175 $lt$libresoc.v:203949$14392_Y + connect \$177 $and$libresoc.v:203950$14393_Y + connect \$15 $ternary$libresoc.v:203951$14394_Y + connect \$179 $lt$libresoc.v:203952$14395_Y + connect \$181 $and$libresoc.v:203953$14396_Y + connect \$183 $lt$libresoc.v:203954$14397_Y + connect \$185 $and$libresoc.v:203955$14398_Y + connect \$187 $lt$libresoc.v:203956$14399_Y + connect \$189 $and$libresoc.v:203957$14400_Y + connect \$191 $lt$libresoc.v:203958$14401_Y + connect \$193 $and$libresoc.v:203959$14402_Y + connect \$195 $lt$libresoc.v:203960$14403_Y + connect \$197 $and$libresoc.v:203961$14404_Y + connect \$1 $eq$libresoc.v:203962$14405_Y + connect \$199 $lt$libresoc.v:203963$14406_Y + connect \$201 $and$libresoc.v:203964$14407_Y + connect \$204 $eq$libresoc.v:203965$14408_Y + connect \$203 $ternary$libresoc.v:203966$14409_Y + connect \$20 $eq$libresoc.v:203967$14410_Y + connect \$19 $ternary$libresoc.v:203968$14411_Y + connect \$24 $eq$libresoc.v:203969$14412_Y + connect \$23 $ternary$libresoc.v:203970$14413_Y + connect \$28 $eq$libresoc.v:203971$14414_Y + connect \$27 $ternary$libresoc.v:203972$14415_Y + connect \$32 $eq$libresoc.v:203973$14416_Y + connect \$31 $ternary$libresoc.v:203974$14417_Y + connect \$36 $eq$libresoc.v:203975$14418_Y + connect \$35 $ternary$libresoc.v:203976$14419_Y + connect \$3 $eq$libresoc.v:203977$14420_Y + connect \$40 $eq$libresoc.v:203978$14421_Y + connect \$39 $ternary$libresoc.v:203979$14422_Y + connect \$44 $eq$libresoc.v:203980$14423_Y + connect \$43 $ternary$libresoc.v:203981$14424_Y + connect \$48 $eq$libresoc.v:203982$14425_Y + connect \$47 $ternary$libresoc.v:203983$14426_Y + connect \$52 $eq$libresoc.v:203984$14427_Y + connect \$51 $ternary$libresoc.v:203985$14428_Y + connect \$56 $eq$libresoc.v:203986$14429_Y + connect \$55 $ternary$libresoc.v:203987$14430_Y + connect \$5 $and$libresoc.v:203988$14431_Y + connect \$60 $eq$libresoc.v:203989$14432_Y + connect \$59 $ternary$libresoc.v:203990$14433_Y + connect \$64 $eq$libresoc.v:203991$14434_Y + connect \$63 $ternary$libresoc.v:203992$14435_Y + connect \$68 $eq$libresoc.v:203993$14436_Y + connect \$67 $ternary$libresoc.v:203994$14437_Y + connect \$71 $shr$libresoc.v:203995$14438_Y [0] + connect \$73 $and$libresoc.v:203996$14439_Y + connect \$75 $lt$libresoc.v:203997$14440_Y + connect \$77 $and$libresoc.v:203998$14441_Y + connect \$79 $lt$libresoc.v:203999$14442_Y + connect \$81 $and$libresoc.v:204000$14443_Y + connect \$83 $lt$libresoc.v:204001$14444_Y + connect \$85 $and$libresoc.v:204002$14445_Y + connect \$87 $lt$libresoc.v:204003$14446_Y + connect \$8 $eq$libresoc.v:204004$14447_Y + connect \$89 $and$libresoc.v:204005$14448_Y + connect \$91 $lt$libresoc.v:204006$14449_Y + connect \$93 $and$libresoc.v:204007$14450_Y + connect \$95 $lt$libresoc.v:204008$14451_Y + connect \$97 $and$libresoc.v:204009$14452_Y connect \icp_r_pri \$203 connect \icp_r_src \cur_idx15 connect \max_idx 4'0000 -- 2.30.2